diff --git a/config/compilespecs.yml b/config/compilespecs.yml index a8a200d..02fc181 100644 --- a/config/compilespecs.yml +++ b/config/compilespecs.yml @@ -4,6 +4,13 @@ files: - src/mcu/config/compile.yml - src/riscv_core/veer_el2/config/compile.yml - src/i3c-core/config/compile.yml + - src/ast/config/compile.yml + - src/pwrmgr/config/compile.yml + - src/tlul/config/compile.yml + - src/dmi/config/compile.yml + - src/axi2tlul/config/compile.yml + - src/caliptra_ss_lc_ctrl/config/compile.yml + - src/fuse_ctrl/config/compile.yml - third_party/caliptra-rtl/src/libs/config/compile.yml - third_party/caliptra-rtl/src/ahb_lite_bus/config/compile.yml - third_party/caliptra-rtl/src/riscv_core/veer_el2/config/compile.yml diff --git a/src/ast/BUILD b/src/ast/BUILD new file mode 100644 index 0000000..fdcf974 --- /dev/null +++ b/src/ast/BUILD @@ -0,0 +1,12 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +package(default_visibility = ["//visibility:public"]) + +filegroup( + name = "all_files", + srcs = glob(["**"]) + [ + "//hw/top_earlgrey/ip/ast/data:all_files", + ], +) diff --git a/src/ast/README.md b/src/ast/README.md new file mode 100644 index 0000000..85ac710 --- /dev/null +++ b/src/ast/README.md @@ -0,0 +1,305 @@ +# Analog Sensor Top Technical Specification + +Analog Sensor Top, also known as the AST, is the OpenTitan analog and +security companion. Within the AST are various analog functions (such as +clocks, regulators, random number generators) needed to make the device +function, as well as physical security sensors necessary to protect the +device from physical attacks or manipulation. + +At a high level, AST communicates with a number of OpenTitan comportable +modules. See the diagram below for an overview. + +![Analog Sensor Top Diagram](./doc/top_diagram.png) + +In the following sections, each family of connections is briefly +described and explained. Note, the analog connections to AST are not +shown in the diagram, but will be explained as well. + +# Interface Signals Table + +See the table [here](./doc/interfaces.md). + +# Interfaces Description Note + +The information below augments the [Interface Signals Table](./doc/interfaces.md). +For further details, see the corresponding signals description in the +table. + +# Power Connectivity + +Note: Power signals may not appear in the verilog files, however, they +are described for completeness. + +## External Supplies + +AST has four external power supplies VCC, AVCC, VIOA and VIOB. VCC is +the main supply, AVCC is an analog VCC supply. VIOA and VIOB are two +additional I/O supplies. + +## Core Supplies + +The core supplies are generated from the VCC supply. There are two core +supply domains: VCMAIN and VCAON. VCAON, as its name implies, is the +always-on core supply used to power components that stay active during +device low power states. VCMAIN on the other hand, powers most chip +logic such as RISC-V processor, crypto modules and almost all memories +and peripherals. The VCMAIN supply can be turned off when requested, +VCAON on the other hand, is active whenever VCC is active. AST core +logic is powered by VCAON. + +# Power Control and Reset + +## Core Power Control and Indication + +VCMAIN is the only supply that can be directly influenced by OpenTitan. +The power manager can request VCMAIN to shutdown through main_pd_ni. The +state of VCMAIN is reflected by the vcmain_pok_o signal. + +## IO Power Indication + +IO power state is reflected to OpenTitan by vioa_pok_o and viob_pok_o +signals + +## Main (VCC) Power Detection and Flash Protection + +On VCC power-down detection, 'flash_power_ready_h_o', is +immediately negated. In addition, SYS clock, IO clock and USB clock are +stopped. This means that negation of the VCC supply always triggers the +flash brown-out (BOR) protection circuitry. + +When entering deep-sleep mode, 'flash_power_down_h_o' is +asserted before negating VCMAIN until VCMAIN is back up. + +## Resets + +The AST supports the generation of the root reset for the reset manager. +It is driven by 'vcaon_pok_o' which is generated inside AST. +The 'vcaon_pok_o' is activated when the following conditions +are met: VCC is detected, internal voltage regulator is active and +'por_ni' reset input is inactive. 'por_ni' is +driven by an external chip reset pin. The following table and diagrams +describe the AST sub-modules resets. + +| **Components** | **Reset by** | **Comments** | +|--------------------------------------------------|--------------------------|------------------------------------------------------------------------------------------------------------------------------------------| +| Regulators, 'power-OK' logic and always-on clock | self-start / vcaon_pok_o | These circuits come to life shortly after VCC crosses its detection threshold. vcaon_pok_o serves as their register configuration reset. | +| System/USB/IO clock generators | vcmain_pok_o | vcmain_pok_o is also fed by vcaon_pok_o and por_ni. | +| Interface functions | Input reset | Per the corresponding interface [clock domain reset input](#clock-and-reset-inputs). | + +# Clock Outputs + +AST generates four clocks: System clock, IO clock, USB clock and +Always-on clock. Most clocks have 'enable' inputs and a +corresponding 'valid' output. When the enable is +de-asserted, the corresponding clock stops and valid is dropped to 0. +When the enable is asserted, the clocks begin outputting in a +'glitchless' manner and the valid is raised to 1. Unless +noted otherwise, clocks duty cycle is 50% +/-5%. At boot time, clocks +start toggling at a different (typically slower) frequency than their +target. They are configured to their target frequency by the ROM code. +Once configured, their frequency is maintained within +/-3% of their +target as long as the chip remains in its intended operating conditions +until the next boot. + +The OpenTitan power and clock managers are responsible for manipulating +the enables and observing the valids to know when clocks can be safely +released to the system. + +## USB Clock Calibration + +The USB clock requires an accuracy that cannot be achieved by the AST +clocks natively. As a result, information from USB frames are used to +[calibrate the +clock](../../../ip/usbdev/README.md#clocking). + +# Clock and Reset Inputs + +The root clocks and resets are generated inside AST. However, the clocks +go through gating and optional division in the OpenTitan top level and +propagate back into AST as feedback clocks, each with associated +synchronized reset de-assertion to ensure it can synchronize with the +various comportable modules. The input resets are used for the different +AST interface functions. For further details about AST resets, see +[Resets](#resets) section. + +Note: There are several reasons for routing leaf clocks back into AST +instead of using the root clocks directly + +- The leaf clocks may be divided down from the root clock and that + frequency is used to drive the interface. For example, + clk_src_io_clk_o is 96MHz, but comportable modules use either 48MHz + or 24MHz. + +- The leaf clocks and root clocks have very different clock tree depths + and may be difficult for timing closure if they interacted directly. + +- Decouple AST internal design from OpenTitan top-level interfaces clock + and reset selection. + +# Register Access Interface + +AST registers can be accessed via TL-UL interface. These registers are +used for test and calibration purposes and are not required for runtime +operation. See the [Interface Signals +Table](#interface-signals-table) for more details. + +## AST registers initialization during boot. + +In PROD*/DEV Lifecycle states, the ROM code must copy all AST REGA +registers values from OTP to AST. During other Lifecycle states, the ROM +code may also copy all AST REGA registers. It is recommended for the +ROM code to condition the copy by a digest verification of the register +values. If such a digest is too complicated, a simple tag can be used to +condition the copy instead. The AST register copy operation must be +performed in order and must include all REGA registers (starting from +REGA0 and ending at the last REGA). AST sets the ast_init_done_o signal +after the copy completion. + +After the copy, ROM code can either poll for ast_init_done_o assertion +with 100 us timeout (in practice, it should take way less) or ignore it +and let the next SW layers handle it. It is recommended to set an OTP +field for determining the ROM code action. + +The boot code is expected to check all AST output alert signals before +handing over the control to the next code layer (ROM_EXT). The ROM code +response per alert should be defined in a dedicated OTP space. +Recommended response types (per alert): + +1. Do nothing and don't clear the event + +2. Do nothing (continue to the next SW layer) and clear the event + +3. Log the event in some NV space and halt + +4. Halt immediately + +Note that in TEST_UNLOCK*/RMA state, the booter should always act per +#1 regardless of the OTP setting. + +It is recommended to redundantly code the OTP fields that control the +ROM code branching and also to protect the branching code from fault +injection. + +# ADC + +AST contains an analog to digital converter that can be used to sample +various input signals. For OpenTitan this will primarily be used for +[debug cable detection](https://www.sparkfun.com/products/14746). +To activate the ADC, the corresponding [comportable +module](../../../ip/adc_ctrl/README.md) must first +activate the ADC through 'adc_pd_i'. Once activated, it should select +the channel to sample. Channel transition from zero to non-zero value +starts the ADC conversion. The ADC output is synchronous to the ADC +controller. + +## ADC Usage Flow + +1. Activate the ADC by negating 'adc_pd_i' + +2. Wait 30 uS for the ADC to wake up. + +3. Select an analog channel to measure by setting the corresponding bit + in 'adc_chnsel_i' bus. This triggers a measurement. + +4. Wait until 'adc_d_val' is set and read the result via + 'adc_d_o' + +5. Clear 'adc_chnsel_i' bus to 0. Note that adc_chnsel must + be cleared to 0 before a new channel is selected. + +6. Repeat steps 3-5 if more channels or more measurements are required + +7. Deactivate the ADC by setting 'adc_pd_i' to save power. + +```wavejson +{ signal: [ {node: '.a..b........', phase:0.2}, +{name: 'adc_pd_i' , wave: '10|..|.....|....|..1'}, {name: +'clk_ast_adc_i', wave: 'p.|..|.....|....|...'}, {name: +'adc_chnsel_i' , wave: '0.|.3|..04.|....|0..'}, {name: +'adc_d_val_o' , wave: '0.|..|.1.0.|.1..|.0.'}, {name: 'adc_d_o' , +wave: 'x.|..|.3.x.|.4..|.x.', data: ['ch0', 'ch1', 'ch1']}, ], +edge: [ 'a<->b wakeup time', ] } +``` + +# Random Number Generator + +AST contains a random number generator that outputs random number +bitstreams whenever it is enabled. After enabled by the [comportable +controller](../../../ip/entropy_src/README.md) +through 'rng_en_i', the AST begins generating multiple +independent four random bit streams. rng_b_o bit streams are valid and +can be sampled whenever 'rng_val_o' is asserted according to the +following diagram. + +```wavejson +{signal: [ {name: 'clk' , wave: +'p.|......|......|......'}, {name: 'rng_enable' , wave: +'01|......|......|......'}, {name: 'rng_valid' , wave: +'0.|..10..|..10..|..10..'}, {name: 'rng_b' , wave: +'x.|..3...|..4...|..5.....', data: ['es0','es1','es2']}, ]} +``` + +The expected rng_b_o valid output rate is about 50KHz. For more +information on the RNG interface, please see the [OpenTitan entropy +source module](../../../ip/entropy_src/README.md). + +# Entropy Consumption + +AST consumes entropy for defensive purposes. However, AST does not +consume its raw entropy directly. Instead, AST receives entropy from the +[Entropy Distribution Network +(EDN)](../../../ip/edn/README.md). Note +that entropy_ack and entropy_i are packed into enropy_rsp_i in the +interface. Also note that once entropy_req_o is set, it will remain set +until ack or until reset. + +```wavejson +{signal: [ + +{name: 'clk_ast_es_i' , wave: 'p.|..........'}, + +{name: 'entropy_req_o' , wave: '01|.0.1.....0'}, + +{name: 'entropy_ack_i' , wave: '0.|10.1.01..0'}, + +{name: 'entropy_i' , wave: 'xx|2x.22x222x'}, + +] } +``` + +# Countermeasures and Alerts + +## Alert Events + +AST's sensors and detectors, when triggered, output alert events +to a sensor controller. The event signals are level until acknowledged +by the controller. Further, the events are differentially encoded to +ensure they cannot be hard-wired or faulted to either '1' or +'0'. + +Inside the sensor controller, the events are then converted into alerts +as part of the wider [OpenTitan alert handling +system](../../ip_autogen/alert_handler/README.md). + +## Alert Signaling + +Outgoing alert events are level. Incoming event ack signals clear the +alert event (similar to an interrupt). Outgoing alert events should be +OR'd inside the sensor or power manager (depending on what level of deep +sleep support is needed) to generate wakeup, that way AST does not need +to do any additional handling for wakeups during low power mode. + +The AST defines each alert signal in both positive (P) and negative (N) +polarity (see ast_dif_t typedef with 'p' and 'n' +signals), however, the P and N signals are not necessarily fully +differential, for example, at times, it might occur that both P and N +are at the same value. For alert_o case, the correct way to treat it is +to propagate an alert signal if either P is high or N is low. + +## Countermeasures + +Most countermeasure enablement is controlled by Nuvoton via the +registers interface. Clock jitter is an exception because there is a +reasoning for dynamically turning it on and off (security/performance +tradeoff). Unless stated otherwise, countermeasures are active in all +modes but deep-sleep. diff --git a/src/ast/ast.core b/src/ast/ast.core new file mode 100644 index 0000000..c37f2a7 --- /dev/null +++ b/src/ast/ast.core @@ -0,0 +1,130 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:systems:ast:0.1" +description: "Analog Sensor Top generic views" +filesets: + files_rtl: + depend: + - lowrisc:ip:tlul + - lowrisc:prim:all + - lowrisc:prim:clock_buf + - lowrisc:prim:clock_div + - lowrisc:prim:clock_gating + - lowrisc:prim:clock_inv + - lowrisc:prim:lc_dec + - lowrisc:prim:lfsr + - lowrisc:ip:pinmux_reg + - lowrisc:ip:pinmux_component + - lowrisc:prim:assert + - lowrisc:prim:prim_pkg + - lowrisc:prim:mubi + - lowrisc:prim:multibit_sync + - lowrisc:ip:lc_ctrl_pkg + - lowrisc:ip:edn_pkg + - lowrisc:ip_interfaces:alert_handler_reg + - lowrisc:ip_interfaces:clkmgr_pkg + - lowrisc:ip_interfaces:rstmgr_pkg + files: + - rtl/ast_reg_pkg.sv + - rtl/ast_pkg.sv + - rtl/ast_bhv_pkg.sv + - rtl/ast.sv + - rtl/ast_reg_top.sv + - rtl/adc.sv + - rtl/adc_ana.sv + - rtl/vcc_pgd.sv + - rtl/vio_pgd.sv + - rtl/vcaon_pgd.sv + - rtl/vcmain_pgd.sv + - rtl/ast_alert.sv + - rtl/aon_clk.sv + - rtl/aon_osc.sv + - rtl/io_clk.sv + - rtl/io_osc.sv + - rtl/sys_clk.sv + - rtl/sys_osc.sv + - rtl/usb_clk.sv + - rtl/usb_osc.sv + - rtl/gfr_clk_mux2.sv + - rtl/ast_clks_byp.sv + - rtl/rglts_pdm_3p3v.sv + - rtl/ast_pulse_sync.sv + - rtl/ast_entropy.sv + - rtl/dev_entropy.sv + - rtl/rng.sv + - rtl/ast_dft.sv + file_type: systemVerilogSource + + files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common + files: + - lint/ast.vlt + file_type: vlt + + files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common + files: + - lint/ast.waiver + file_type: waiver + + files_veriblelint_waiver: + depend: + # common waivers + - lowrisc:lint:common + files: + - lint/ast.vbl + file_type: veribleLintWaiver + + +parameters: + SYNTHESIS: + datatype: bool + paramtype: vlogdefine + AST_BYPASS_CLK: + datatype: bool + paramtype: vlogdefine + ANALOGSIM: + datatype: bool + paramtype: vlogdefine + + +targets: + default: &default_target + filesets: + - tool_verilator ? (files_verilator_waiver) + - tool_ascentlint ? (files_ascentlint_waiver) + - tool_veriblelint ? (files_veriblelint_waiver) + - files_rtl + toplevel: ast + parameters: + - SYNTHESIS + - AST_BYPASS_CLK + - ANALOGSIM + + + lint: + <<: *default_target + default_tool: verilator + parameters: + - SYNTHESIS=true + tools: + verilator: + mode: lint-only + verilator_options: + - "-Wall" + + sim: + <<: *default_target + default_tool: vcs + filesets: + - files_rtl + tools: + vcs: + vcs_options: [-sverilog -ntb_opts uvm-1.2 -CFLAGS --std=c99 -CFLAGS -fno-extended-identifiers -CFLAGS --std=c++11 -timescale=1ns/1ps -l vcs.log] + toplevel: ast diff --git a/src/ast/ast_pkg.core b/src/ast/ast_pkg.core new file mode 100644 index 0000000..63703cb --- /dev/null +++ b/src/ast/ast_pkg.core @@ -0,0 +1,20 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:systems:ast_pkg" +description: "Analog sensor top (AST) wrapper package" + +filesets: + files_rtl: + depend: + - lowrisc:constants:top_pkg + - lowrisc:ip:lc_ctrl_pkg + files: + - rtl/ast_pkg.sv + file_type: systemVerilogSource + +targets: + default: + filesets: + - files_rtl diff --git a/src/ast/ast_regs.html b/src/ast/ast_regs.html new file mode 100644 index 0000000..0abde57 --- /dev/null +++ b/src/ast/ast_regs.html @@ -0,0 +1,52 @@ + + + + + +
+
ast.REVID @ 0x0
+

AST Revision Identification Register
+Reset: TLUL Reset

+
Reset default = 0x1, mask 0xff
+
+ + + +
31302928272625242322212019181716
 
1514131211109876543210
 REVID
BitsTypeResetNameDescription
7:0ro0x1REVID

Revision

+
+ + + + + +
+
ast.RWTYPE0 @ 0x4
+

RW type with one field

+
Reset default = 0xbc614e, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
RWTYPE0...
1514131211109876543210
...RWTYPE0
BitsTypeResetNameDescription
31:0rw0xbc614eRWTYPE0

field description

+
+ + + + + +
+
ast.RWTYPE1 @ 0x8
+

RW type +with long +description +and multiple fields

+
Reset default = 0x6411, mask 0xff13
+
+ + + + + + + +
31302928272625242322212019181716
 
1514131211109876543210
FIELD15_8 FIELD4 FIELD1FIELD0
BitsTypeResetNameDescription
0rw0x1FIELD0

field 0

1rw0x0FIELD1

field 1

3:2Reserved
4rw0x1FIELD4

field 4

7:5Reserved
15:8rw0x64FIELD15_8

field [15:8]

+
diff --git a/src/ast/config/compile.yml b/src/ast/config/compile.yml new file mode 100644 index 0000000..f790a23 --- /dev/null +++ b/src/ast/config/compile.yml @@ -0,0 +1,16 @@ +--- +provides: [ast_pkg] +schema_version: 2.4.0 +requires: +targets: + rtl: + directories: [$COMPILE_ROOT/rtl] + files: + - $COMPILE_ROOT/rtl/ast_pkg.sv + #- $COMPILE_ROOT/rtl/ast_bhv_pkg.sv + #- $COMPILE_ROOT/rtl/ast_reg_pkg.sv + tb: + directories: [$COMPILE_ROOT/rtl] + files: + - $COMPILE_ROOT/rtl/ast_pkg.sv + diff --git a/src/ast/data/BUILD b/src/ast/data/BUILD new file mode 100644 index 0000000..d71fefb --- /dev/null +++ b/src/ast/data/BUILD @@ -0,0 +1,30 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +package(default_visibility = ["//visibility:public"]) + +load( + "//rules:autogen.bzl", + "autogen_hjson_c_header", + "autogen_hjson_rust_header", +) + +autogen_hjson_c_header( + name = "ast_c_regs", + srcs = [ + "ast.hjson", + ], +) + +autogen_hjson_rust_header( + name = "ast_rust_regs", + srcs = [ + "ast.hjson", + ], +) + +filegroup( + name = "all_files", + srcs = glob(["**"]), +) diff --git a/src/ast/data/ast.hjson b/src/ast/data/ast.hjson new file mode 100644 index 0000000..d21b494 --- /dev/null +++ b/src/ast/data/ast.hjson @@ -0,0 +1,621 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +//############################################################################# +// *Name: ast +// *Module Description: Analog Sensors Top Registers +//############################################################################# +{ name: "ast", + // Unique comportable IP identifier defined under KNOWN_CIP_IDS in the regtool. + cip_id: "34", + design_spec: "../doc", + dv_doc: "", + hw_checklist: "", + sw_checklist: "", + version: "1.0.0", + life_stage: "L1", + design_stage: "D2", + verification_stage: "V2S", + dif_stage: "", + clocking: [ + { clock: "clk_ast_tlul_i", reset: "rst_ast_tlul_ni", primary: true }, + { clock: "clk_ast_adc_i", reset: "rst_ast_adc_ni"}, + { clock: "clk_ast_alert_i", reset: "rst_ast_alert_ni"}, + { clock: "clk_ast_es_i", reset: "rst_ast_es_ni"}, + { clock: "clk_ast_rng_i", reset: "rst_ast_rng_ni"}, + { clock: "clk_ast_usb_i", reset: "rst_ast_usb_ni"}, + ], + bus_interfaces: [ + { protocol: "tlul", + direction: "device" + } + ], + no_auto_alert_regs: "True", + param_list: [ + { name: "NumRegsB", + desc: "Number of registers in the Array-B", + type: "int", + default: "5", + local: "true", + }, + { name: "NumUsbBeaconPulses", + desc: "Number of USB valid beacon pulses for clock to re-calibrate", + type: "int", + default: "8", + local: "true" + }, + ], + regwidth: "32", + registers: [ + { name: "REGA0", + desc: "AST Register 0 for OTP/ROM Write Testing", + swaccess: "ro", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclAll" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x00", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGA1", + desc: "AST 1 Register for OTP/ROM Write Testing", + swaccess: "ro", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclAll" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x01", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGA2", + desc: "AST 2 Register for OTP/ROM Write Testing", + swaccess: "rw", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclWrite" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x02", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGA3", + desc: "AST 3 Register for OTP/ROM Write Testing", + swaccess: "rw", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclWrite" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x03", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGA4", + desc: "AST 4 Register for OTP/ROM Write Testing", + swaccess: "rw", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclWrite" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x04", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGA5", + desc: "AST 5 Register for OTP/ROM Write Testing", + swaccess: "rw", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclWrite" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x05", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGA6", + desc: "AST 6 Register for OTP/ROM Write Testing", + swaccess: "rw", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclWrite" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x06", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGA7", + desc: "AST 7 Register for OTP/ROM Write Testing", + swaccess: "rw", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclWrite" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x07", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGA8", + desc: "AST 8 Register for OTP/ROM Write Testing", + swaccess: "rw", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclWrite" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x08", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGA9", + desc: "AST 9 Register for OTP/ROM Write Testing", + swaccess: "rw", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclWrite" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x09", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGA10", + desc: "AST 10 Register for OTP/ROM Write Testing", + swaccess: "rw", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclWrite" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x0A", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGA11", + desc: "AST 11 Register for OTP/ROM Write Testing", + swaccess: "rw", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclWrite" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x0B", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGA12", + desc: "AST 13 Register for OTP/ROM Write Testing", + swaccess: "rw", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclWrite" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x0C", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGA13", + desc: "AST 13 Register for OTP/ROM Write Testing", + swaccess: "rw", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclWrite" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x0D", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGA14", + desc: "AST 14 Register for OTP/ROM Write Testing", + swaccess: "rw", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclWrite" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x0E", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGA15", + desc: "AST 15 Register for OTP/ROM Write Testing", + swaccess: "rw", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclWrite" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x0F", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGA16", + desc: "AST 16 Register for OTP/ROM Write Testing", + swaccess: "rw", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclWrite" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x10", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGA17", + desc: "AST 17 Register for OTP/ROM Write Testing", + swaccess: "rw", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclWrite" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x11", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGA18", + desc: "AST 18 Register for OTP/ROM Write Testing", + swaccess: "rw", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclWrite" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x12", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGA19", + desc: "AST 19 Register for OTP/ROM Write Testing", + swaccess: "rw", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclWrite" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x13", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGA20", + desc: "AST 20 Register for OTP/ROM Write Testing", + swaccess: "rw", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclWrite" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x14", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGA21", + desc: "AST 21 Register for OTP/ROM Write Testing", + swaccess: "rw", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclWrite" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x15", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGA22", + desc: "AST 22 Register for OTP/ROM Write Testing", + swaccess: "rw", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclWrite" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x16", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGA23", + desc: "AST 23 Register for OTP/ROM Write Testing", + swaccess: "rw", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclWrite" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x17", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGA24", + desc: "AST 24 Register for OTP/ROM Write Testing", + swaccess: "rw", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclWrite" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x18", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGA25", + desc: "AST 25 Register for OTP/ROM Write Testing", + swaccess: "rw", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclWrite" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x19", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGA26", + desc: "AST 26 Register for OTP/ROM Write Testing", + swaccess: "rw", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclWrite" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x1A", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGA27", + desc: "AST 27 Register for OTP/ROM Write Testing", + swaccess: "rw", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclWrite" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x1B", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGA28", + desc: "AST 28 Register for OTP/ROM Write Testing", + swaccess: "ro", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclWrite" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x1C", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGA29", + desc: "AST 29 Register for OTP/ROM Write Testing", + swaccess: "rw", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclWrite" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x1D", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGA30", + desc: "AST 30 Register for OTP/ROM Write Testing", + swaccess: "rw", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclWrite" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x1E", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGA31", + desc: "AST 31 Register for OTP/ROM Write Testing", + swaccess: "rw", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclWrite" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x1F", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGA32", + desc: "AST 32 Register for OTP/ROM Write Testing", + swaccess: "rw", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclWrite" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x20", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGA33", + desc: "AST 33 Register for OTP/ROM Write Testing", + swaccess: "rw", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclWrite" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x21", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGA34", + desc: "AST 34 Register for OTP/ROM Write Testing", + swaccess: "rw", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclWrite" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x22", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGA35", + desc: "AST 35 Register for OTP/ROM Write Testing", + swaccess: "rw", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclWrite" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x23", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGA36", + desc: "AST 36 Register for OTP/ROM Write Testing", + swaccess: "rw", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclWrite" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x24", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGA37", + desc: "AST 37 Register for OTP/ROM Write Testing", + swaccess: "rw", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclWrite" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x25", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGAL", + desc: "AST Last Register for OTP/ROM Write Testing", + swaccess: "wo", + hwaccess: "hrw", + hwext: "true", + hwqe: "true", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclAll" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x26", + }, + ], + }, //---------------------------------------------------------------------- + /////////////////////////////////////////////////////////////////////////// + { skipto: "0x200" } + /////////////////////////////////////////////////////////////////////////// + { multireg: + { + name: "REGB", + desc: "AST Registers Array-B to set address space size", + count: "NumRegsB", + cname: "REGB", + swaccess: "rw", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclAll" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0", + }, + ], + }, + }, //---------------------------------------------------------------------- + ], +} diff --git a/src/ast/data/ast_cdc_abstract.sgdc b/src/ast/data/ast_cdc_abstract.sgdc new file mode 100644 index 0000000..c8fe774 --- /dev/null +++ b/src/ast/data/ast_cdc_abstract.sgdc @@ -0,0 +1,631 @@ +################################################################################ +# +# This file has been generated by SpyGlass: +# File Created by: ngotliv +# File Created on: Thu May 19 11:20:01 2022 +# Working Directory: /tanap1/proj_cd14/opentitan/ngotliv/nightly_220518/nuvoton/top/spyglass +# File Location : ./ast_cdc/ast/cdc/cdc_abstract/spyglass_reports/abstract_view/ast_AdcChannels_2_AdcDataWidth_10_Ast2PadOutWidth_9_Entro_1_cdc_abstract.sgdc +# SpyGlass Version : SpyGlass_vR-2020.12-1 +# Policy Name : clock-reset +# Comment : Generated by rule Ac_abstract01 +# +################################################################################ +if { $::sg_use_cdc_abstract_view == 1 } { + abstract_file -version 5.1.0 -scope cdc + + current_design "ast" -def_param + +################################################################# +# abstract_port constraints # +################################################################# + +abstract_port -path_logic combo -ports "otp_power_seq_h_o[0]" -related_ports otp_power_seq_i[0] +abstract_port -path_logic combo -ports "otp_power_seq_h_o[1]" -related_ports otp_power_seq_i[1] +abstract_port -path_logic combo -ports "obs_ctrl_o[obmsl][0]" -related_ports padmux2ast_i[4] +abstract_port -path_logic combo -ports "obs_ctrl_o[obmsl][1]" -related_ports padmux2ast_i[5] +abstract_port -path_logic combo -ports "obs_ctrl_o[obmsl][2]" -related_ports padmux2ast_i[6] +abstract_port -path_logic combo -ports "obs_ctrl_o[obmsl][3]" -related_ports padmux2ast_i[7] +abstract_port -path_logic combo -ports "obs_ctrl_o[obgsl][0]" -related_ports padmux2ast_i[0] +abstract_port -path_logic combo -ports "obs_ctrl_o[obgsl][1]" -related_ports padmux2ast_i[1] +abstract_port -path_logic combo -ports "obs_ctrl_o[obgsl][2]" -related_ports padmux2ast_i[2] +abstract_port -path_logic combo -ports "obs_ctrl_o[obgsl][3]" -related_ports padmux2ast_i[3] + +################################################################# +# clock constraints # +################################################################# + + +# Clock constraint is not generated. + + +################################################################# +# set_case_analysis constraints # +################################################################# + +set_case_analysis -name "tl_o[d_user][rsp_intg][6]" -value 0 +set_case_analysis -name "tl_o[d_sink][0]" -value 0 +set_case_analysis -name "tl_o[d_param][0]" -value 0 +set_case_analysis -name "tl_o[d_param][1]" -value 0 +set_case_analysis -name "tl_o[d_param][2]" -value 0 +set_case_analysis -name "tl_o[d_opcode][1]" -value 0 +set_case_analysis -name "tl_o[d_opcode][2]" -value 0 + +################################################################# +# reset constraints # +################################################################# + +reset -name "tl_o[a_ready]" -value 1 +reset -name "tl_o[d_valid]" -value 0 +reset -name "ast_pwst_o[main_pok]" -value 0 +reset -name "ast_pwst_o[vcc_pok]" -value 0 +reset -name "ast_pwst_h_o[main_pok]" -value 0 +reset -name "ast_pwst_h_o[vcc_pok]" -value 0 +reset -name "flash_power_ready_h_o" -value 0 + +# Synchronous reset constraint is not generated. + + +################################################################# +# quasi_static constraints # +################################################################# + +quasi_static -name "ast2padmux_o[0]" +quasi_static -name "ast2padmux_o[1]" +quasi_static -name "ast2padmux_o[2]" +quasi_static -name "ast2padmux_o[3]" +quasi_static -name "ast2padmux_o[4]" +quasi_static -name "ast2padmux_o[5]" +quasi_static -name "ast2padmux_o[6]" +quasi_static -name "ast2padmux_o[7]" +quasi_static -name "ast2padmux_o[8]" +quasi_static -name "ast2pad_t0_ao" +quasi_static -name "ast2pad_t1_ao" +quasi_static -name "dft_scan_md_o[0]" +quasi_static -name "dft_scan_md_o[1]" +quasi_static -name "dft_scan_md_o[2]" +quasi_static -name "dft_scan_md_o[3]" + +################################################################# +# abstract_port constraints # +################################################################# + +abstract_port -ports "adc_d_o" -scope cdc -clock "clk_ast_adc_i" -related_ports "adc_pd_i" "adc_chnsel_i" +abstract_port -ports "adc_d_val_o" -scope cdc -clock "clk_ast_adc_i" -related_ports "adc_pd_i" "adc_chnsel_i" +abstract_port -ports "alert_req_o[alerts][0][n]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][0][n]" "alert_rsp_i[alerts_ack][0][n]" +abstract_port -ports "alert_req_o[alerts][0][p]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][0][p]" "alert_rsp_i[alerts_ack][0][p]" +abstract_port -ports "alert_req_o[alerts][1][n]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][1][n]" "alert_rsp_i[alerts_ack][1][n]" +abstract_port -ports "alert_req_o[alerts][1][p]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][1][p]" "alert_rsp_i[alerts_ack][1][p]" +abstract_port -ports "alert_req_o[alerts][2][n]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][2][n]" "alert_rsp_i[alerts_ack][2][n]" +abstract_port -ports "alert_req_o[alerts][2][p]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][2][p]" "alert_rsp_i[alerts_ack][2][p]" +abstract_port -ports "alert_req_o[alerts][3][n]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][3][n]" "alert_rsp_i[alerts_ack][3][n]" +abstract_port -ports "alert_req_o[alerts][3][p]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][3][p]" "alert_rsp_i[alerts_ack][3][p]" +abstract_port -ports "alert_req_o[alerts][4][n]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][4][n]" "alert_rsp_i[alerts_ack][4][n]" +abstract_port -ports "alert_req_o[alerts][4][p]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][4][p]" "alert_rsp_i[alerts_ack][4][p]" +abstract_port -ports "alert_req_o[alerts][5][n]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][5][n]" "alert_rsp_i[alerts_ack][5][n]" +abstract_port -ports "alert_req_o[alerts][5][p]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][5][p]" "alert_rsp_i[alerts_ack][5][p]" +abstract_port -ports "alert_req_o[alerts][6][n]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][6][n]" "alert_rsp_i[alerts_ack][6][n]" +abstract_port -ports "alert_req_o[alerts][6][p]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][6][p]" "alert_rsp_i[alerts_ack][6][p]" +abstract_port -ports "alert_req_o[alerts][7][n]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][7][n]" "alert_rsp_i[alerts_ack][7][n]" +abstract_port -ports "alert_req_o[alerts][7][p]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][7][p]" "alert_rsp_i[alerts_ack][7][p]" +abstract_port -ports "alert_req_o[alerts][8][n]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][8][n]" "alert_rsp_i[alerts_ack][8][n]" +abstract_port -ports "alert_req_o[alerts][8][p]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][8][p]" "alert_rsp_i[alerts_ack][8][p]" +abstract_port -ports "alert_req_o[alerts][9][n]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][9][n]" "alert_rsp_i[alerts_ack][9][n]" +abstract_port -ports "alert_req_o[alerts][9][p]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][9][p]" "alert_rsp_i[alerts_ack][9][p]" +abstract_port -ports "alert_req_o[alerts][10][n]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][10][n]" "alert_rsp_i[alerts_ack][10][n]" +abstract_port -ports "alert_req_o[alerts][10][p]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][10][p]" "alert_rsp_i[alerts_ack][10][p]" +abstract_port -ports "alert_req_o[alerts][11][n]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][11][n]" "alert_rsp_i[alerts_ack][11][n]" +abstract_port -ports "alert_req_o[alerts][11][p]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][11][p]" "alert_rsp_i[alerts_ack][11][p]" +abstract_port -ports "alert_req_o[alerts][12][n]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][12][n]" "alert_rsp_i[alerts_ack][12][n]" +abstract_port -ports "alert_req_o[alerts][12][p]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][12][p]" "alert_rsp_i[alerts_ack][12][p]" +abstract_port -ports "entropy_req_o[edn_req]" -scope cdc -clock "clk_ast_es_i" -related_ports "entropy_rsp_i[edn_ack]" +abstract_port -ports "tl_o[a_ready]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_error]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_user][rsp_intg][2]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_user][rsp_intg][3]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_size][0]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_user][rsp_intg][4]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_size][1]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_user][rsp_intg][5]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_data][0]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" "dft_strap_test_i[straps][0]" "dft_strap_test_i[straps][1]" "dft_strap_test_i[valid]" +abstract_port -ports "tl_o[d_data][1]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" "dft_strap_test_i[straps][0]" "dft_strap_test_i[straps][1]" "dft_strap_test_i[valid]" +abstract_port -ports "tl_o[d_data][2]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" "dft_strap_test_i[straps][0]" "dft_strap_test_i[straps][1]" "dft_strap_test_i[valid]" +abstract_port -ports "tl_o[d_data][3]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" "dft_strap_test_i[straps][0]" "dft_strap_test_i[straps][1]" "dft_strap_test_i[valid]" +abstract_port -ports "tl_o[d_data][4]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" "dft_strap_test_i[straps][0]" "dft_strap_test_i[straps][1]" "dft_strap_test_i[valid]" +abstract_port -ports "tl_o[d_data][5]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_data][6]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" "fla_alert_src_i[n]" "fla_alert_src_i[p]" +abstract_port -ports "tl_o[d_data][7]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" "otp_alert_src_i[n]" "otp_alert_src_i[p]" +abstract_port -ports "tl_o[d_data][8]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_data][9]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_data][10]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_data][11]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_data][12]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_data][13]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_data][14]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_data][15]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_data][16]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_data][17]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_data][18]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_data][19]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_data][20]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_data][21]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_data][22]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_data][23]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_data][24]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_data][25]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_data][26]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_data][27]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_data][28]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_data][29]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_data][30]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_data][31]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_source][0]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_source][0]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_source][1]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_source][1]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_source][2]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_source][2]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_source][3]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_source][3]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_source][4]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_source][4]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_source][5]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_source][5]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_source][6]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_source][6]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_source][7]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_source][7]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_size][0]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_size][0]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_size][1]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_size][1]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_opcode][0]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_valid]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_user][data_intg][0]" -scope cdc -clock "clk_ast_tlul_i" -combo yes -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" "dft_strap_test_i[straps][0]" "dft_strap_test_i[straps][1]" "dft_strap_test_i[valid]" +abstract_port -ports "tl_o[d_user][data_intg][1]" -scope cdc -clock "clk_ast_tlul_i" -combo yes -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" "fla_alert_src_i[n]" "fla_alert_src_i[p]" "dft_strap_test_i[straps][0]" "dft_strap_test_i[straps][1]" "dft_strap_test_i[valid]" +abstract_port -ports "tl_o[d_user][data_intg][2]" -scope cdc -clock "clk_ast_tlul_i" -combo yes -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" "otp_alert_src_i[n]" "otp_alert_src_i[p]" "dft_strap_test_i[straps][0]" "dft_strap_test_i[straps][1]" "dft_strap_test_i[valid]" +abstract_port -ports "tl_o[d_user][data_intg][3]" -scope cdc -clock "clk_ast_tlul_i" -combo yes -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" "fla_alert_src_i[n]" "fla_alert_src_i[p]" "otp_alert_src_i[n]" "otp_alert_src_i[p]" "dft_strap_test_i[straps][0]" "dft_strap_test_i[straps][1]" "dft_strap_test_i[valid]" +abstract_port -ports "tl_o[d_user][data_intg][4]" -scope cdc -clock "clk_ast_tlul_i" -combo yes -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" "dft_strap_test_i[straps][0]" "dft_strap_test_i[straps][1]" "dft_strap_test_i[valid]" +abstract_port -ports "tl_o[d_user][data_intg][5]" -scope cdc -clock "clk_ast_tlul_i" -combo yes -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" "fla_alert_src_i[n]" "fla_alert_src_i[p]" "dft_strap_test_i[straps][0]" "dft_strap_test_i[straps][1]" "dft_strap_test_i[valid]" +abstract_port -ports "tl_o[d_user][data_intg][6]" -scope cdc -clock "clk_ast_tlul_i" -combo yes -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" "otp_alert_src_i[n]" "otp_alert_src_i[p]" "dft_strap_test_i[straps][0]" "dft_strap_test_i[straps][1]" "dft_strap_test_i[valid]" +abstract_port -ports "tl_o[d_user][rsp_intg][0]" -scope cdc -clock "clk_ast_tlul_i" -combo yes -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_user][rsp_intg][1]" -scope cdc -clock "clk_ast_tlul_i" -combo yes -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "ast_init_done_o" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "usb_io_pu_cal_o" -scope cdc -clock "clk_ast_tlul_i" -combo yes -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "obs_ctrl_o[obmen][0]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "obs_ctrl_o[obmen][1]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "obs_ctrl_o[obmen][2]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "obs_ctrl_o[obmen][3]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "obs_ctrl_o[obmsl][0]" -scope cdc -clock "clk_ast_tlul_i" -combo yes -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "obs_ctrl_o[obmsl][1]" -scope cdc -clock "clk_ast_tlul_i" -combo yes -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "obs_ctrl_o[obmsl][2]" -scope cdc -clock "clk_ast_tlul_i" -combo yes -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "obs_ctrl_o[obmsl][3]" -scope cdc -clock "clk_ast_tlul_i" -combo yes -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "obs_ctrl_o[obgsl][0]" -scope cdc -clock "clk_ast_tlul_i" -combo yes -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "obs_ctrl_o[obgsl][1]" -scope cdc -clock "clk_ast_tlul_i" -combo yes -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "obs_ctrl_o[obgsl][2]" -scope cdc -clock "clk_ast_tlul_i" -combo yes -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "obs_ctrl_o[obgsl][3]" -scope cdc -clock "clk_ast_tlul_i" -combo yes -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "flash_bist_en_o" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "dpram_rmf_o[marg_b][0]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "dpram_rmf_o[marg_b][1]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "dpram_rmf_o[marg_b][2]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "dpram_rmf_o[marg_b][3]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "dpram_rmf_o[marg_en_b]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "dpram_rmf_o[marg_a][0]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "dpram_rmf_o[marg_a][1]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "dpram_rmf_o[marg_a][2]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "dpram_rmf_o[marg_a][3]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "dpram_rmf_o[marg_en_a]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "dpram_rml_o[marg_b][0]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "dpram_rml_o[marg_b][1]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "dpram_rml_o[marg_b][2]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "dpram_rml_o[marg_b][3]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "dpram_rml_o[marg_en_b]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "dpram_rml_o[marg_a][0]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "dpram_rml_o[marg_a][1]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "dpram_rml_o[marg_a][2]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "dpram_rml_o[marg_a][3]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "dpram_rml_o[marg_en_a]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "spram_rm_o[marg][0]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "spram_rm_o[marg][1]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "spram_rm_o[marg][2]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "spram_rm_o[marg][3]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "spram_rm_o[marg_en]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "sprgf_rm_o[marg][0]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "sprgf_rm_o[marg][1]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "sprgf_rm_o[marg][2]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "sprgf_rm_o[marg][3]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "sprgf_rm_o[marg_en]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "sprom_rm_o[marg][0]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "sprom_rm_o[marg][1]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "sprom_rm_o[marg][2]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "sprom_rm_o[marg][3]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "sprom_rm_o[marg_en]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "ast_pwst_o[vcc_pok]" -scope cdc -clock "clk_src_aon_o" +abstract_port -ports "ast_pwst_o[aon_pok]" -scope cdc -clock "clk_src_aon_o" -related_ports "main_pd_ni" +abstract_port -ports "ast_pwst_o[main_pok]" -scope cdc -clock "clk_src_aon_o" -combo yes -related_ports "main_pd_ni" +abstract_port -ports "ast_pwst_h_o[vcc_pok]" -scope cdc -clock "clk_src_aon_o" +abstract_port -ports "ast_pwst_h_o[aon_pok]" -scope cdc -clock "clk_src_aon_o" -related_ports "main_pd_ni" +abstract_port -ports "ast_pwst_h_o[main_pok]" -scope cdc -clock "clk_src_aon_o" -combo yes -related_ports "main_pd_ni" +abstract_port -ports "flash_power_down_h_o" -scope cdc -clock "clk_src_aon_o" +abstract_port -ports "otp_power_seq_h_o" -scope cdc -clock "clk_src_aon_o" +abstract_port -ports "clk_src_aon_val_o" -scope cdc -clock SG_VIRT_OUT_20 +abstract_port -ports "clk_src_sys_val_o" -scope cdc -clock SG_VIRT_OUT_83 +abstract_port -ports "clk_src_io_val_o" -scope cdc -clock SG_VIRT_OUT_84 +abstract_port -ports "clk_src_usb_val_o" -scope cdc -clock SG_VIRT_OUT_85 + + +################################################################# +#translating input constraints to abstract_port where it involves +#a sync crossing and apending -combo no # +################################################################# + +abstract_port -ports "clk_src_sys_en_i" -scope cdc -clock "clk_src_aon_o" -combo no -combo_ifn "clk_ast_ext_i" +abstract_port -ports "clk_src_sys_jen_i" -scope cdc -clock "clk_src_aon_o" -combo no -combo_ifn "clk_src_sys_o" +abstract_port -ports "clk_src_io_en_i" -scope cdc -clock "clk_src_aon_o" -combo no -combo_ifn "clk_ast_ext_i" +abstract_port -ports "clk_src_usb_en_i" -scope cdc -clock "clk_src_aon_o" -combo no -combo_ifn "clk_ast_ext_i" +abstract_port -ports "rng_en_i" -scope cdc -clock "clk_src_sys_o" -combo no -combo_ifn "clk_ast_tlul_i" +abstract_port -ports "rng_fips_i" -scope cdc -clock "clk_src_sys_o" -combo no -combo_ifn "clk_ast_tlul_i" +abstract_port -ports "ext_freq_is_96m_i" -scope cdc -clock "clk_ast_tlul_i" -combo no +abstract_port -ports "all_clk_byp_req_i" -scope cdc -clock "clk_ast_tlul_i" -combo no +abstract_port -ports "io_clk_byp_req_i" -scope cdc -clock "clk_ast_tlul_i" -combo no + + +################################################################# +#Adding -combo no to abstract_port defined at input port# +#If it invloves a synchronized control crossing # +################################################################# + + +################################################################# +# qualifier constraints # +################################################################# + +#Port with -ignore constraint.Reason:Path is Hanging or Blocked# +abstract_port -ports "ast_pwst_o[io_pok][0]" -scope cdc -ignore -comment "blocked or hanging path" +###################################################### +#Port with -ignore constraint.Reason:Path is Hanging or Blocked# +abstract_port -ports "ast_pwst_o[io_pok][1]" -scope cdc -ignore -comment "blocked or hanging path" +###################################################### +#Port with -ignore constraint.Reason:Path is Hanging or Blocked# +abstract_port -ports "ast_pwst_h_o[io_pok][0]" -scope cdc -ignore -comment "blocked or hanging path" +###################################################### + +#Port with -ignore constraint.Reason:Path is Hanging or Blocked# +abstract_port -ports "ast_pwst_h_o[io_pok][1]" -scope cdc -ignore -comment "blocked or hanging path" +###################################################### +################################################################# +# virtual clock constraints # +################################################################# + +clock -tag SG_VIRT_OUT_20 -domain "domain20" +## "abstraction_new_domain_83" :: bbox_merged_domain_83 +clock -tag SG_VIRT_OUT_83 -domain "abstraction_new_domain_83" +## "abstraction_new_domain_84" :: bbox_merged_domain_84 +clock -tag SG_VIRT_OUT_84 -domain "abstraction_new_domain_84" +## "abstraction_new_domain_85" :: bbox_merged_domain_85 +clock -tag SG_VIRT_OUT_85 -domain "abstraction_new_domain_85" +################################################################# +# cdc_attribute constraints # +################################################################# + + +# cdc_attribute constraint is not generated. + + +################################################################# +# reset_filter_path constraints # +################################################################# + +reset_filter_path -type rdc -from_rst "tl_o[a_ready]" -to_rst "tl_o[d_valid]" "rst_ast_tlul_ni" +reset_filter_path -type rdc -from_rst "tl_o[d_valid]" -to_rst "tl_o[a_ready]" "rst_ast_tlul_ni" +reset_filter_path -type rdc -from_rst "rst_ast_tlul_ni" -to_rst "tl_o[a_ready]" "tl_o[d_valid]" +reset_filter_path -type rdc -from_rst "ast_pwst_o[main_pok]" -to_rst "ast_pwst_h_o[main_pok]" "ast_pwst_h_o[vcc_pok]" +reset_filter_path -type rdc -from_rst "ast_pwst_h_o[main_pok]" -to_rst "ast_pwst_o[main_pok]" "ast_pwst_h_o[vcc_pok]" +reset_filter_path -type rdc -from_rst "ast_pwst_h_o[vcc_pok]" -to_rst "ast_pwst_o[main_pok]" "ast_pwst_h_o[main_pok]" +reset_filter_path -type rdc -from_rst "obs_ctrl_o[obmsl][3]" -to_rst "ast2padmux_o[0]" "ast2padmux_o[1]" "ast2padmux_o[2]" "ast2padmux_o[4]" "ast2padmux_o[5]" "ast2padmux_o[6]" "ast2padmux_o[7]" "ast2padmux_o[8]" +reset_filter_path -type rdc -from_rst "ast2padmux_o[0]" -to_rst "obs_ctrl_o[obmsl][3]" "ast2padmux_o[1]" "ast2padmux_o[2]" "ast2padmux_o[4]" "ast2padmux_o[5]" "ast2padmux_o[6]" "ast2padmux_o[7]" "ast2padmux_o[8]" +reset_filter_path -type rdc -from_rst "ast2padmux_o[1]" -to_rst "obs_ctrl_o[obmsl][3]" "ast2padmux_o[0]" "ast2padmux_o[2]" "ast2padmux_o[4]" "ast2padmux_o[5]" "ast2padmux_o[6]" "ast2padmux_o[7]" "ast2padmux_o[8]" +reset_filter_path -type rdc -from_rst "ast2padmux_o[2]" -to_rst "obs_ctrl_o[obmsl][3]" "ast2padmux_o[0]" "ast2padmux_o[1]" "ast2padmux_o[4]" "ast2padmux_o[5]" "ast2padmux_o[6]" "ast2padmux_o[7]" "ast2padmux_o[8]" +reset_filter_path -type rdc -from_rst "ast2padmux_o[4]" -to_rst "obs_ctrl_o[obmsl][3]" "ast2padmux_o[0]" "ast2padmux_o[1]" "ast2padmux_o[2]" "ast2padmux_o[5]" "ast2padmux_o[6]" "ast2padmux_o[7]" "ast2padmux_o[8]" +reset_filter_path -type rdc -from_rst "ast2padmux_o[5]" -to_rst "obs_ctrl_o[obmsl][3]" "ast2padmux_o[0]" "ast2padmux_o[1]" "ast2padmux_o[2]" "ast2padmux_o[4]" "ast2padmux_o[6]" "ast2padmux_o[7]" "ast2padmux_o[8]" +reset_filter_path -type rdc -from_rst "ast2padmux_o[6]" -to_rst "obs_ctrl_o[obmsl][3]" "ast2padmux_o[0]" "ast2padmux_o[1]" "ast2padmux_o[2]" "ast2padmux_o[4]" "ast2padmux_o[5]" "ast2padmux_o[7]" "ast2padmux_o[8]" +reset_filter_path -type rdc -from_rst "ast2padmux_o[7]" -to_rst "obs_ctrl_o[obmsl][3]" "ast2padmux_o[0]" "ast2padmux_o[1]" "ast2padmux_o[2]" "ast2padmux_o[4]" "ast2padmux_o[5]" "ast2padmux_o[6]" "ast2padmux_o[8]" +reset_filter_path -type rdc -from_rst "ast2padmux_o[8]" -to_rst "obs_ctrl_o[obmsl][3]" "ast2padmux_o[0]" "ast2padmux_o[1]" "ast2padmux_o[2]" "ast2padmux_o[4]" "ast2padmux_o[5]" "ast2padmux_o[6]" "ast2padmux_o[7]" + +################################################################# +# Inferred abstract_port constraints # +################################################################# + + +abstract_port -ports "por_ni" -clock "clk_src_aon_o" -start +abstract_port -ports "fla_alert_src_i[n]" -clock "clk_ast_tlul_i" -combo no -start +abstract_port -ports "fla_alert_src_i[p]" -clock "clk_ast_tlul_i" -combo no -start +abstract_port -ports "otp_alert_src_i[n]" -clock "clk_ast_tlul_i" -combo no -start +abstract_port -ports "otp_alert_src_i[p]" -clock "clk_ast_tlul_i" -combo no -start +abstract_port -ports "sns_clks_i[clk_io_peri]" -ignore -comment "hanging path" +abstract_port -ports "sns_clks_i[clk_usb_peri]" -ignore -comment "hanging path" +abstract_port -ports "sns_clks_i[clk_io_div2_peri]" -ignore -comment "hanging path" +abstract_port -ports "sns_clks_i[clk_io_div4_peri]" -ignore -comment "hanging path" +abstract_port -ports "sns_clks_i[clk_io_div4_timers]" -ignore -comment "hanging path" +abstract_port -ports "sns_clks_i[clk_usb_secure]" -ignore -comment "hanging path" +abstract_port -ports "sns_clks_i[clk_main_secure]" -ignore -comment "hanging path" +abstract_port -ports "sns_clks_i[clk_io_div4_secure]" -ignore -comment "hanging path" +abstract_port -ports "sns_clks_i[clk_io_div2_infra]" -ignore -comment "hanging path" +abstract_port -ports "sns_clks_i[clk_io_infra]" -ignore -comment "hanging path" +abstract_port -ports "sns_clks_i[clk_main_infra]" -ignore -comment "hanging path" +abstract_port -ports "sns_clks_i[clk_io_div4_infra]" -ignore -comment "hanging path" +abstract_port -ports "sns_clks_i[clk_main_otbn]" -ignore -comment "hanging path" +abstract_port -ports "sns_clks_i[clk_main_kmac]" -ignore -comment "hanging path" +abstract_port -ports "sns_clks_i[clk_main_hmac]" -ignore -comment "hanging path" +abstract_port -ports "sns_clks_i[clk_main_aes]" -ignore -comment "hanging path" +abstract_port -ports "sns_clks_i[clk_aon_timers]" -ignore -comment "hanging path" +abstract_port -ports "sns_clks_i[clk_aon_peri]" -ignore -comment "hanging path" +abstract_port -ports "sns_clks_i[clk_aon_secure]" -ignore -comment "hanging path" +abstract_port -ports "sns_clks_i[clk_aon_infra]" -ignore -comment "hanging path" +abstract_port -ports "sns_clks_i[clk_io_div2_powerup]" -ignore -comment "hanging path" +abstract_port -ports "sns_clks_i[clk_usb_powerup]" -ignore -comment "hanging path" +abstract_port -ports "sns_clks_i[clk_io_powerup]" -ignore -comment "hanging path" +abstract_port -ports "sns_clks_i[clk_main_powerup]" -ignore -comment "hanging path" +abstract_port -ports "sns_clks_i[clk_aon_powerup]" -ignore -comment "hanging path" +abstract_port -ports "sns_clks_i[clk_io_div4_powerup]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_i2c2_n][0]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_i2c2_n][1]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_i2c1_n][0]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_i2c1_n][1]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_i2c0_n][0]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_i2c0_n][1]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_usbif_n][0]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_usbif_n][1]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_usb_n][0]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_usb_n][1]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_spi_host1_n][0]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_spi_host1_n][1]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_spi_host0_n][0]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_spi_host0_n][1]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_spi_device_n][0]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_spi_device_n][1]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_sys_aon_n][0]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_sys_aon_n][1]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_sys_io_div4_n][0]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_sys_io_div4_n][1]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_sys_n][0]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_sys_n][1]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_sys_shadowed_n][0]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_sys_shadowed_n][1]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_lc_aon_n][0]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_lc_aon_n][1]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_lc_io_div4_n][0]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_lc_io_div4_n][1]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_lc_io_div4_shadowed_n][0]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_lc_io_div4_shadowed_n][1]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_lc_n][0]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_lc_n][1]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_lc_shadowed_n][0]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_lc_shadowed_n][1]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_por_usb_n][0]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_por_usb_n][1]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_por_io_div4_n][0]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_por_io_div4_n][1]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_por_io_div4_shadowed_n][0]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_por_io_div4_shadowed_n][1]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_por_io_div2_n][0]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_por_io_div2_n][1]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_por_io_n][0]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_por_io_n][1]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_por_n][0]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_por_n][1]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_por_aon_n][0]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_por_aon_n][1]" -ignore -comment "hanging path" +abstract_port -ports "sns_spi_ext_clk_i" -ignore -comment "hanging path" +abstract_port -ports "vcc_supp_i" -ignore -comment "hanging path" +abstract_port -ports "vcaon_supp_i" -ignore -comment "hanging path" +abstract_port -ports "vcmain_supp_i" -ignore -comment "hanging path" +abstract_port -ports "vioa_supp_i" -ignore -comment "hanging path" +abstract_port -ports "viob_supp_i" -ignore -comment "hanging path" +clock -tag SG_VCLK_1 + +################################################################# +# cdc_filter_coherency constraints # +################################################################# + + +# cdc_filter_coherency constraint is not generated. + + + +################################################################# +# clock_sense constraints # +################################################################# + + +################################################################# +# reset_sense constraints # +################################################################# + +# reset_sense constraint is not generated. Either no reset defined on input ports or no combinational path found from primary resets to output port. + +################################################################# +# block interface constraints # +################################################################# + +abstract_interface_param -name "AdcChannels" -value "2" +abstract_interface_param -name "AdcDataWidth" -value "10" +abstract_interface_param -name "EntropyStreams" -value "4" +abstract_interface_param -name "UsbCalibWidth" -value "20" +abstract_interface_param -name "Ast2PadOutWidth" -value "9" +abstract_interface_param -name "Pad2AstInWidth" -value "9" +abstract_interface_port -name "tl_i" -definition "input tlul_pkg :: tl_h2d_t tl_i;" +abstract_interface_port -name "tl_o" -definition "output tlul_pkg :: tl_d2h_t tl_o;" +abstract_interface_port -name "ast_init_done_o" -definition "output logic ast_init_done_o; " +abstract_interface_port -name "clk_ast_adc_i" -definition "input clk_ast_adc_i; " +abstract_interface_port -name "rst_ast_adc_ni" -definition "input rst_ast_adc_ni; " +abstract_interface_port -name "clk_ast_alert_i" -definition "input clk_ast_alert_i; " +abstract_interface_port -name "rst_ast_alert_ni" -definition "input rst_ast_alert_ni; " +abstract_interface_port -name "clk_ast_es_i" -definition "input clk_ast_es_i; " +abstract_interface_port -name "rst_ast_es_ni" -definition "input rst_ast_es_ni; " +abstract_interface_port -name "clk_ast_rng_i" -definition "input clk_ast_rng_i; " +abstract_interface_port -name "rst_ast_rng_ni" -definition "input rst_ast_rng_ni; " +abstract_interface_port -name "clk_ast_tlul_i" -definition "input clk_ast_tlul_i; " +abstract_interface_port -name "rst_ast_tlul_ni" -definition "input rst_ast_tlul_ni; " +abstract_interface_port -name "clk_ast_usb_i" -definition "input clk_ast_usb_i; " +abstract_interface_port -name "rst_ast_usb_ni" -definition "input rst_ast_usb_ni; " +abstract_interface_port -name "clk_ast_ext_i" -definition "input clk_ast_ext_i; " +abstract_interface_port -name "por_ni" -definition "input por_ni; " +abstract_interface_port -name "sns_clks_i" -definition "input clkmgr_pkg :: clkmgr_out_t sns_clks_i;" +abstract_interface_port -name "sns_rsts_i" -definition "input rstmgr_pkg :: rstmgr_out_t sns_rsts_i;" +abstract_interface_port -name "sns_spi_ext_clk_i" -definition "input sns_spi_ext_clk_i; " +abstract_interface_port -name "vcc_supp_i" -definition "input vcc_supp_i; " +abstract_interface_port -name "vcaon_supp_i" -definition "input vcaon_supp_i; " +abstract_interface_port -name "vcmain_supp_i" -definition "input vcmain_supp_i; " +abstract_interface_port -name "vioa_supp_i" -definition "input vioa_supp_i; " +abstract_interface_port -name "viob_supp_i" -definition "input viob_supp_i; " +abstract_interface_port -name "ast_pwst_o" -definition "output ast_pkg :: ast_pwst_t ast_pwst_o;" +abstract_interface_port -name "ast_pwst_h_o" -definition "output ast_pkg :: ast_pwst_t ast_pwst_h_o;" +abstract_interface_port -name "main_pd_ni" -definition "input main_pd_ni; " +abstract_interface_port -name "main_env_iso_en_i" -definition "input main_env_iso_en_i; " +abstract_interface_port -name "flash_power_down_h_o" -definition "output logic flash_power_down_h_o; " +abstract_interface_port -name "flash_power_ready_h_o" -definition "output logic flash_power_ready_h_o; " +abstract_interface_port -name "otp_power_seq_i" -definition "input [1:0] otp_power_seq_i; " +abstract_interface_port -name "otp_power_seq_h_o" -definition "output logic [1:0] otp_power_seq_h_o; " +abstract_interface_port -name "clk_src_sys_en_i" -definition "input clk_src_sys_en_i; " +abstract_interface_port -name "clk_src_sys_jen_i" -definition "input prim_mubi_pkg :: mubi4_t clk_src_sys_jen_i;" +abstract_interface_port -name "clk_src_sys_o" -definition "output logic clk_src_sys_o; " +abstract_interface_port -name "clk_src_sys_val_o" -definition "output logic clk_src_sys_val_o; " +abstract_interface_port -name "clk_src_aon_o" -definition "output logic clk_src_aon_o; " +abstract_interface_port -name "clk_src_aon_val_o" -definition "output logic clk_src_aon_val_o; " +abstract_interface_port -name "clk_src_io_en_i" -definition "input clk_src_io_en_i; " +abstract_interface_port -name "clk_src_io_o" -definition "output logic clk_src_io_o; " +abstract_interface_port -name "clk_src_io_val_o" -definition "output logic clk_src_io_val_o; " +abstract_interface_port -name "clk_src_io_48m_o" -definition "output prim_mubi_pkg :: mubi4_t clk_src_io_48m_o;" +abstract_interface_port -name "usb_ref_pulse_i" -definition "input usb_ref_pulse_i; " +abstract_interface_port -name "usb_ref_val_i" -definition "input usb_ref_val_i; " +abstract_interface_port -name "clk_src_usb_en_i" -definition "input clk_src_usb_en_i; " +abstract_interface_port -name "clk_src_usb_o" -definition "output logic clk_src_usb_o; " +abstract_interface_port -name "clk_src_usb_val_o" -definition "output logic clk_src_usb_val_o; " +abstract_interface_port -name "usb_io_pu_cal_o" -definition "output logic [(UsbCalibWidth - 1):0] usb_io_pu_cal_o; " +abstract_interface_port -name "adc_pd_i" -definition "input adc_pd_i; " +abstract_interface_port -name "adc_a0_ai" -definition "input ast_pkg :: awire_t adc_a0_ai;" +abstract_interface_port -name "adc_a1_ai" -definition "input ast_pkg :: awire_t adc_a1_ai;" +abstract_interface_port -name "adc_chnsel_i" -definition "input [(AdcChannels - 1):0] adc_chnsel_i; " +abstract_interface_port -name "adc_d_o" -definition "output [(AdcDataWidth - 1):0] adc_d_o; " +abstract_interface_port -name "adc_d_val_o" -definition "output adc_d_val_o; " +abstract_interface_port -name "rng_en_i" -definition "input rng_en_i; " +abstract_interface_port -name "rng_fips_i" -definition "input rng_fips_i; " +abstract_interface_port -name "rng_val_o" -definition "output logic rng_val_o; " +abstract_interface_port -name "rng_b_o" -definition "output logic [(EntropyStreams - 1):0] rng_b_o; " +abstract_interface_port -name "entropy_rsp_i" -definition "input edn_pkg :: edn_rsp_t entropy_rsp_i;" +abstract_interface_port -name "entropy_req_o" -definition "output edn_pkg :: edn_req_t entropy_req_o;" +abstract_interface_port -name "fla_alert_src_i" -definition "input ast_pkg :: ast_dif_t fla_alert_src_i;" +abstract_interface_port -name "otp_alert_src_i" -definition "input ast_pkg :: ast_dif_t otp_alert_src_i;" +abstract_interface_port -name "alert_rsp_i" -definition "input ast_pkg :: ast_alert_rsp_t alert_rsp_i;" +abstract_interface_port -name "alert_req_o" -definition "output ast_pkg :: ast_alert_req_t alert_req_o;" +abstract_interface_port -name "dft_strap_test_i" -definition "input pinmux_pkg :: dft_strap_test_req_t dft_strap_test_i;" +abstract_interface_port -name "lc_dft_en_i" -definition "input lc_ctrl_pkg :: lc_tx_t lc_dft_en_i;" +abstract_interface_port -name "fla_obs_i" -definition "input [(8 - 1):0] fla_obs_i; " +abstract_interface_port -name "otp_obs_i" -definition "input [(8 - 1):0] otp_obs_i; " +abstract_interface_port -name "otm_obs_i" -definition "input [(8 - 1):0] otm_obs_i; " +abstract_interface_port -name "usb_obs_i" -definition "input usb_obs_i; " +abstract_interface_port -name "obs_ctrl_o" -definition "output ast_pkg :: ast_obs_ctrl_t obs_ctrl_o;" +abstract_interface_port -name "padmux2ast_i" -definition "input [(Pad2AstInWidth - 1):0] padmux2ast_i; " +abstract_interface_port -name "ast2padmux_o" -definition "output logic [(Ast2PadOutWidth - 1):0] ast2padmux_o; " +abstract_interface_port -name "ast2pad_t0_ao" -definition "output ast2pad_t0_ao; " +abstract_interface_port -name "ast2pad_t1_ao" -definition "output ast2pad_t1_ao; " +abstract_interface_port -name "ext_freq_is_96m_i" -definition "input prim_mubi_pkg :: mubi4_t ext_freq_is_96m_i;" +abstract_interface_port -name "all_clk_byp_req_i" -definition "input prim_mubi_pkg :: mubi4_t all_clk_byp_req_i;" +abstract_interface_port -name "all_clk_byp_ack_o" -definition "output prim_mubi_pkg :: mubi4_t all_clk_byp_ack_o;" +abstract_interface_port -name "io_clk_byp_req_i" -definition "input prim_mubi_pkg :: mubi4_t io_clk_byp_req_i;" +abstract_interface_port -name "io_clk_byp_ack_o" -definition "output prim_mubi_pkg :: mubi4_t io_clk_byp_ack_o;" +abstract_interface_port -name "flash_bist_en_o" -definition "output prim_mubi_pkg :: mubi4_t flash_bist_en_o;" +abstract_interface_port -name "dpram_rmf_o" -definition "output ast_pkg :: dpm_rm_t dpram_rmf_o;" +abstract_interface_port -name "dpram_rml_o" -definition "output ast_pkg :: dpm_rm_t dpram_rml_o;" +abstract_interface_port -name "spram_rm_o" -definition "output ast_pkg :: spm_rm_t spram_rm_o;" +abstract_interface_port -name "sprgf_rm_o" -definition "output ast_pkg :: spm_rm_t sprgf_rm_o;" +abstract_interface_port -name "sprom_rm_o" -definition "output ast_pkg :: spm_rm_t sprom_rm_o;" +abstract_interface_port -name "dft_scan_md_o" -definition "output prim_mubi_pkg :: mubi4_t dft_scan_md_o;" +abstract_interface_port -name "scan_shift_en_o" -definition "output scan_shift_en_o; " +abstract_interface_port -name "scan_reset_no" -definition "output scan_reset_no; " +} + +if { $::sg_use_cdc_abstract_view == 1 } { + + + current_design "ast" -def_param +abstract_block_violation -name Propagate_Clocks -sev WARNING -count 1 +abstract_block_violation -name Setup_check01 -sev WARNING -count 16 +abstract_block_violation -name ErrorAnalyzeBBox -sev ERROR -count 1 -is_builtin +abstract_block_violation -name SYNTH_78 -sev WARNING -count 10 -is_builtin +abstract_block_violation -name SYNTH_89 -sev WARNING -count 4 -is_builtin +abstract_block_violation -name SYNTH_93 -sev WARNING -count 1 -is_builtin +abstract_block_violation -name SYNTH_1084 -sev ERROR -count 1 -is_builtin +abstract_block_violation -name WRN_1459 -sev WARNING -count 5 -is_builtin +abstract_block_violation -name WRN_1470 -sev WARNING -count 5 -is_builtin +abstract_block_violation -name checkCMD_dirfile03 -sev WARNING -count 29 -is_builtin +abstract_block_violation -name Propagate_Resets -sev WARNING -count 4 +abstract_block_violation -name Setup_blackbox01 -sev WARNING -count 13 +abstract_block_violation -name Clock_check07 -sev WARNING -count 27 + + +block_file_decompiled_start + + input -name "tl_i" -clock "ast.clk_ast_tlul_i" + input -name "ast.rst_ast_adc_ni" -clock "ast.clk_ast_adc_i" + input -name "ast.rst_ast_alert_ni" -clock "ast.clk_ast_alert_i" + input -name "ast.rst_ast_es_ni" -clock "ast.clk_ast_es_i" + input -name "ast.rst_ast_rng_ni" -clock "ast.clk_ast_rng_i" + input -name "ast.rst_ast_tlul_ni" -clock "ast.clk_ast_tlul_i" + input -name "ast.rst_ast_usb_ni" -clock "ast.clk_ast_usb_i" + input -name "ast.main_pd_ni" -clock "ast.clk_src_aon_o" + input -name "ast.main_env_iso_en_i" -clock "ast.clk_src_aon_o" + input -name "otp_power_seq_i" -clock "ast.clk_src_aon_o" + input -name "clk_src_sys_en_i" -clock "ast.clk_src_aon_o" + input -name "clk_src_sys_jen_i" -clock "ast.clk_src_aon_o" + input -name "clk_src_io_en_i" -clock "ast.clk_src_aon_o" + input -name "usb_ref_pulse_i" -clock "ast.clk_ast_usb_i" + input -name "usb_ref_val_i" -clock "ast.clk_ast_usb_i" + input -name "clk_src_usb_en_i" -clock "ast.clk_src_aon_o" + input -name "adc_pd_i" -clock "ast.clk_ast_adc_i" + input -name "adc_a0_ai" -clock "ast.clk_ast_adc_i" + input -name "adc_a1_ai" -clock "ast.clk_ast_adc_i" + input -name "adc_chnsel_i" -clock "ast.clk_ast_adc_i" + input -name "rng_en_i" -clock "ast.clk_src_sys_o" + input -name "rng_fips_i" -clock "ast.clk_src_sys_o" + input -name "entropy_rsp_i" -clock "ast.clk_ast_es_i" + input -name "alert_rsp_i" -clock "ast.clk_ast_alert_i" + input -name "dft_strap_test_i" -clock "ast.clk_ast_tlul_i" + input -name "lc_dft_en_i" -clock "ast.clk_ast_tlul_i" + input -name "fla_obs_i" -clock "ast.clk_ast_tlul_i" + input -name "otp_obs_i" -clock "ast.clk_ast_tlul_i" + input -name "otm_obs_i" -clock "ast.clk_ast_tlul_i" + input -name "usb_obs_i" -clock "ast.clk_ast_tlul_i" + input -name "ext_freq_is_96m_i" -clock "ast.clk_ast_tlul_i" + input -name "all_clk_byp_req_i" -clock "ast.clk_ast_tlul_i" + input -name "io_clk_byp_req_i" -clock "ast.clk_ast_tlul_i" + output -name "tl_o" -clock "ast.clk_ast_tlul_i" + output -name "ast_init_done_o" -clock "ast.clk_ast_tlul_i" + output -name "ast.flash_power_down_h_o" -clock "ast.clk_src_aon_o" + output -name "ast.flash_power_ready_h_o" -clock "ast.clk_src_aon_o" + output -name "ast.otp_power_seq_h_o" -clock "ast.clk_src_aon_o" + output -name "clk_src_sys_val_o" -clock "ast.clk_src_sys_o" + output -name "clk_src_aon_val_o" -clock "ast.clk_src_aon_o" + output -name "clk_src_io_val_o" -clock "ast.clk_src_io_o" + output -name "clk_src_io_48m_o" -clock "ast.clk_src_io_o" + output -name "clk_src_usb_val_o" -clock "ast.clk_src_usb_o" + output -name "usb_io_pu_cal_o" -clock "ast.clk_ast_tlul_i" + output -name "adc_d_o" -clock "ast.clk_ast_adc_i" + output -name "adc_d_val_o" -clock "ast.clk_ast_adc_i" + output -name "rng_val_o" -clock "ast.clk_ast_rng_i" + output -name "rng_b_o" -clock "ast.clk_ast_rng_i" + output -name "entropy_req_o" -clock "ast.clk_ast_es_i" + output -name "alert_req_o" -clock "ast.clk_ast_alert_i" + output -name "obs_ctrl_o" -clock "ast.clk_ast_tlul_i" + output -name "all_clk_byp_ack_o" -clock "ast.clk_src_io_o" + output -name "io_clk_byp_ack_o" -clock "ast.clk_src_io_o" + output -name "flash_bist_en_o" -clock "ast.clk_ast_tlul_i" + output -name "dpram_rmf_o" -clock "ast.clk_ast_tlul_i" + output -name "dpram_rml_o" -clock "ast.clk_ast_tlul_i" + output -name "spram_rm_o" -clock "ast.clk_ast_tlul_i" + output -name "sprgf_rm_o" -clock "ast.clk_ast_tlul_i" + output -name "sprom_rm_o" -clock "ast.clk_ast_tlul_i" + output -name "dft_scan_md_o" -clock "ast.clk_ast_tlul_i" + output -name "scan_shift_en_o" -clock "ast.clk_ast_tlul_i" + output -name "scan_reset_no" -clock "ast.clk_ast_tlul_i" + clock -name "clk_src_sys_o" -domain domain7 -tag SG_AUTO_TAG_7 + clock -name "clk_src_aon_o" -domain domain8 -tag SG_AUTO_TAG_8 + clock -name "clk_src_io_o" -domain domain_9 -tag SG_AUTO_TAG_9 + clock -name "clk_src_usb_o" -domain domain_10 -tag SG_AUTO_TAG_10 + reset -name "fla_alert_src_i" -value 0 + reset -name "otp_alert_src_i" -value 0 + quasi_static -name "padmux2ast_i" + quasi_static -name "ast2padmux_o" + quasi_static -name "ast2pad_t0_ao" + quasi_static -name "ast2pad_t1_ao" + +block_file_decompiled_end +} diff --git a/src/ast/doc/ast_regs.html b/src/ast/doc/ast_regs.html new file mode 100644 index 0000000..0d6a1a4 --- /dev/null +++ b/src/ast/doc/ast_regs.html @@ -0,0 +1,773 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Summary
Name Offset Length Description
ast.REGA0 0x0 4

AST Register 0 for OTP/ROM Write Testing
ast.REGA1 0x4 4

AST 1 Register for OTP/ROM Write Testing
ast.REGA2 0x8 4

AST 2 Register for OTP/ROM Write Testing
ast.REGA3 0xc 4

AST 3 Register for OTP/ROM Write Testing
ast.REGA4 0x10 4

AST 4 Register for OTP/ROM Write Testing
ast.REGA5 0x14 4

AST 5 Register for OTP/ROM Write Testing
ast.REGA6 0x18 4

AST 6 Register for OTP/ROM Write Testing
ast.REGA7 0x1c 4

AST 7 Register for OTP/ROM Write Testing
ast.REGA8 0x20 4

AST 8 Register for OTP/ROM Write Testing
ast.REGA9 0x24 4

AST 9 Register for OTP/ROM Write Testing
ast.REGA10 0x28 4

AST 10 Register for OTP/ROM Write Testing
ast.REGA11 0x2c 4

AST 11 Register for OTP/ROM Write Testing
ast.REGA12 0x30 4

AST 13 Register for OTP/ROM Write Testing
ast.REGA13 0x34 4

AST 13 Register for OTP/ROM Write Testing
ast.REGA14 0x38 4

AST 14 Register for OTP/ROM Write Testing
ast.REGA15 0x3c 4

AST 15 Register for OTP/ROM Write Testing
ast.REGA16 0x40 4

AST 16 Register for OTP/ROM Write Testing
ast.REGA17 0x44 4

AST 17 Register for OTP/ROM Write Testing
ast.REGA18 0x48 4

AST 18 Register for OTP/ROM Write Testing
ast.REGA19 0x4c 4

AST 19 Register for OTP/ROM Write Testing
ast.REGA20 0x50 4

AST 20 Register for OTP/ROM Write Testing
ast.REGA21 0x54 4

AST 21 Register for OTP/ROM Write Testing
ast.REGA22 0x58 4

AST 22 Register for OTP/ROM Write Testing
ast.REGA23 0x5c 4

AST 23 Register for OTP/ROM Write Testing
ast.REGA24 0x60 4

AST 24 Register for OTP/ROM Write Testing
ast.REGA25 0x64 4

AST 25 Register for OTP/ROM Write Testing
ast.REGA26 0x68 4

AST 26 Register for OTP/ROM Write Testing
ast.REGA27 0x6c 4

AST 27 Register for OTP/ROM Write Testing
ast.REGA28 0x70 4

AST 28 Register for OTP/ROM Write Testing
ast.REGA29 0x74 4

AST 29 Register for OTP/ROM Write Testing
ast.REGA30 0x78 4

AST 30 Register for OTP/ROM Write Testing
ast.REGA31 0x7c 4

AST 31 Register for OTP/ROM Write Testing
ast.REGA32 0x80 4

AST 32 Register for OTP/ROM Write Testing
ast.REGA33 0x84 4

AST 33 Register for OTP/ROM Write Testing
ast.REGA34 0x88 4

AST 34 Register for OTP/ROM Write Testing
ast.REGA35 0x8c 4

AST 35 Register for OTP/ROM Write Testing
ast.REGA36 0x90 4

AST 36 Register for OTP/ROM Write Testing
ast.REGA37 0x94 4

AST 37 Register for OTP/ROM Write Testing
ast.REGAL 0x98 4

AST Last Register for OTP/ROM Write Testing
ast.REGB_0 0x200 4

AST Registers Array-B to set address space size
ast.REGB_1 0x204 4

AST Registers Array-B to set address space size
ast.REGB_2 0x208 4

AST Registers Array-B to set address space size
ast.REGB_3 0x20c 4

AST Registers Array-B to set address space size
ast.REGB_4 0x210 4

AST Registers Array-B to set address space size
+ + + + +
+
ast.REGA0 @ 0x0
+

AST Register 0 for OTP/ROM Write Testing

+
Reset default = 0x0, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0ro0x0reg32

32-bit Register

+
+ + + + + +
+
ast.REGA1 @ 0x4
+

AST 1 Register for OTP/ROM Write Testing

+
Reset default = 0x1, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0ro0x1reg32

32-bit Register

+
+ + + + + +
+
ast.REGA2 @ 0x8
+

AST 2 Register for OTP/ROM Write Testing

+
Reset default = 0x2, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0x2reg32

32-bit Register

+
+ + + + + +
+
ast.REGA3 @ 0xc
+

AST 3 Register for OTP/ROM Write Testing

+
Reset default = 0x3, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0x3reg32

32-bit Register

+
+ + + + + +
+
ast.REGA4 @ 0x10
+

AST 4 Register for OTP/ROM Write Testing

+
Reset default = 0x4, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0x4reg32

32-bit Register

+
+ + + + + +
+
ast.REGA5 @ 0x14
+

AST 5 Register for OTP/ROM Write Testing

+
Reset default = 0x5, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0x5reg32

32-bit Register

+
+ + + + + +
+
ast.REGA6 @ 0x18
+

AST 6 Register for OTP/ROM Write Testing

+
Reset default = 0x6, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0x6reg32

32-bit Register

+
+ + + + + +
+
ast.REGA7 @ 0x1c
+

AST 7 Register for OTP/ROM Write Testing

+
Reset default = 0x7, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0x7reg32

32-bit Register

+
+ + + + + +
+
ast.REGA8 @ 0x20
+

AST 8 Register for OTP/ROM Write Testing

+
Reset default = 0x8, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0x8reg32

32-bit Register

+
+ + + + + +
+
ast.REGA9 @ 0x24
+

AST 9 Register for OTP/ROM Write Testing

+
Reset default = 0x9, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0x9reg32

32-bit Register

+
+ + + + + +
+
ast.REGA10 @ 0x28
+

AST 10 Register for OTP/ROM Write Testing

+
Reset default = 0xa, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0xareg32

32-bit Register

+
+ + + + + +
+
ast.REGA11 @ 0x2c
+

AST 11 Register for OTP/ROM Write Testing

+
Reset default = 0xb, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0xbreg32

32-bit Register

+
+ + + + + +
+
ast.REGA12 @ 0x30
+

AST 13 Register for OTP/ROM Write Testing

+
Reset default = 0xc, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0xcreg32

32-bit Register

+
+ + + + + +
+
ast.REGA13 @ 0x34
+

AST 13 Register for OTP/ROM Write Testing

+
Reset default = 0xd, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0xdreg32

32-bit Register

+
+ + + + + +
+
ast.REGA14 @ 0x38
+

AST 14 Register for OTP/ROM Write Testing

+
Reset default = 0xe, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0xereg32

32-bit Register

+
+ + + + + +
+
ast.REGA15 @ 0x3c
+

AST 15 Register for OTP/ROM Write Testing

+
Reset default = 0xf, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0xfreg32

32-bit Register

+
+ + + + + +
+
ast.REGA16 @ 0x40
+

AST 16 Register for OTP/ROM Write Testing

+
Reset default = 0x10, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0x10reg32

32-bit Register

+
+ + + + + +
+
ast.REGA17 @ 0x44
+

AST 17 Register for OTP/ROM Write Testing

+
Reset default = 0x11, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0x11reg32

32-bit Register

+
+ + + + + +
+
ast.REGA18 @ 0x48
+

AST 18 Register for OTP/ROM Write Testing

+
Reset default = 0x12, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0x12reg32

32-bit Register

+
+ + + + + +
+
ast.REGA19 @ 0x4c
+

AST 19 Register for OTP/ROM Write Testing

+
Reset default = 0x13, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0x13reg32

32-bit Register

+
+ + + + + +
+
ast.REGA20 @ 0x50
+

AST 20 Register for OTP/ROM Write Testing

+
Reset default = 0x14, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0x14reg32

32-bit Register

+
+ + + + + +
+
ast.REGA21 @ 0x54
+

AST 21 Register for OTP/ROM Write Testing

+
Reset default = 0x15, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0x15reg32

32-bit Register

+
+ + + + + +
+
ast.REGA22 @ 0x58
+

AST 22 Register for OTP/ROM Write Testing

+
Reset default = 0x16, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0x16reg32

32-bit Register

+
+ + + + + +
+
ast.REGA23 @ 0x5c
+

AST 23 Register for OTP/ROM Write Testing

+
Reset default = 0x17, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0x17reg32

32-bit Register

+
+ + + + + +
+
ast.REGA24 @ 0x60
+

AST 24 Register for OTP/ROM Write Testing

+
Reset default = 0x18, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0x18reg32

32-bit Register

+
+ + + + + +
+
ast.REGA25 @ 0x64
+

AST 25 Register for OTP/ROM Write Testing

+
Reset default = 0x19, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0x19reg32

32-bit Register

+
+ + + + + +
+
ast.REGA26 @ 0x68
+

AST 26 Register for OTP/ROM Write Testing

+
Reset default = 0x1a, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0x1areg32

32-bit Register

+
+ + + + + +
+
ast.REGA27 @ 0x6c
+

AST 27 Register for OTP/ROM Write Testing

+
Reset default = 0x1b, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0x1breg32

32-bit Register

+
+ + + + + +
+
ast.REGA28 @ 0x70
+

AST 28 Register for OTP/ROM Write Testing

+
Reset default = 0x1c, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0ro0x1creg32

32-bit Register

+
+ + + + + +
+
ast.REGA29 @ 0x74
+

AST 29 Register for OTP/ROM Write Testing

+
Reset default = 0x1d, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0x1dreg32

32-bit Register

+
+ + + + + +
+
ast.REGA30 @ 0x78
+

AST 30 Register for OTP/ROM Write Testing

+
Reset default = 0x1e, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0x1ereg32

32-bit Register

+
+ + + + + +
+
ast.REGA31 @ 0x7c
+

AST 31 Register for OTP/ROM Write Testing

+
Reset default = 0x1f, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0x1freg32

32-bit Register

+
+ + + + + +
+
ast.REGA32 @ 0x80
+

AST 32 Register for OTP/ROM Write Testing

+
Reset default = 0x20, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0x20reg32

32-bit Register

+
+ + + + + +
+
ast.REGA33 @ 0x84
+

AST 33 Register for OTP/ROM Write Testing

+
Reset default = 0x21, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0x21reg32

32-bit Register

+
+ + + + + +
+
ast.REGA34 @ 0x88
+

AST 34 Register for OTP/ROM Write Testing

+
Reset default = 0x22, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0x22reg32

32-bit Register

+
+ + + + + +
+
ast.REGA35 @ 0x8c
+

AST 35 Register for OTP/ROM Write Testing

+
Reset default = 0x23, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0x23reg32

32-bit Register

+
+ + + + + +
+
ast.REGA36 @ 0x90
+

AST 36 Register for OTP/ROM Write Testing

+
Reset default = 0x24, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0x24reg32

32-bit Register

+
+ + + + + +
+
ast.REGA37 @ 0x94
+

AST 37 Register for OTP/ROM Write Testing

+
Reset default = 0x25, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0x25reg32

32-bit Register

+
+ + + + + +
+
ast.REGAL @ 0x98
+

AST Last Register for OTP/ROM Write Testing

+
Reset default = 0x26, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0wo0x26reg32

32-bit Register

+
+ + + + + +
+
ast.REGB_0 @ 0x200
+

AST Registers Array-B to set address space size

+
Reset default = 0x0, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32_0...
1514131211109876543210
...reg32_0
BitsTypeResetNameDescription
31:0rw0x0reg32_0

32-bit Register

+
+ + + + + +
+
ast.REGB_1 @ 0x204
+

AST Registers Array-B to set address space size

+
Reset default = 0x0, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32_1...
1514131211109876543210
...reg32_1
BitsTypeResetNameDescription
31:0rw0x0reg32_1

For REGB1

+
+ + + + + +
+
ast.REGB_2 @ 0x208
+

AST Registers Array-B to set address space size

+
Reset default = 0x0, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32_2...
1514131211109876543210
...reg32_2
BitsTypeResetNameDescription
31:0rw0x0reg32_2

For REGB2

+
+ + + + + +
+
ast.REGB_3 @ 0x20c
+

AST Registers Array-B to set address space size

+
Reset default = 0x0, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32_3...
1514131211109876543210
...reg32_3
BitsTypeResetNameDescription
31:0rw0x0reg32_3

For REGB3

+
+ + + + + +
+
ast.REGB_4 @ 0x210
+

AST Registers Array-B to set address space size

+
Reset default = 0x0, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32_4...
1514131211109876543210
...reg32_4
BitsTypeResetNameDescription
31:0rw0x0reg32_4

For REGB4

+
diff --git a/src/ast/doc/interfaces.md b/src/ast/doc/interfaces.md new file mode 100644 index 0000000..724a06d --- /dev/null +++ b/src/ast/doc/interfaces.md @@ -0,0 +1,129 @@ +# Interface Signals + +## Table notes + +### Signal naming conventions used in this document + +Naming here is compliant with the OpenTitan [names](https://github.com/lowRISC/style-guides/blob/master/VerilogCodingStyle.md#naming) and [suffixes](https://github.com/lowRISC/style-guides/blob/master/VerilogCodingStyle.md#suffixes) specification, with the following augmentations: + +- Clock signals start with `clk_*` +- Inputs and outputs are marked with `*_i/o` +- Analog signals are marked with `*_a` +- Non-core level signals are marked with `*_h` +- Dual and negative polarity signals are marked with `*_p/n` + +### Clock domains column + +| name | freq | description | +|-------|--------------|-----------------------------------------------------------------------------------------| +| sys | Up to 100MHz | jittery system clock. Mainly used for high performance and security modules. | +| usb | 48MHz | USB module source clock. | +| aon | 200kHz | Always-on domain clock. The only active clock while chip is in deep-sleep power states. | +| async | | *It does not matter what domain drives the signal* | + +- Input clocks: Each functional interface has a dedicated clock named after the interface. + +## Table + +| Signal Name /
Affiliation | I/O | Width/
Type/
Struct | Clock Domain | Description | +|--------------------------------------------------------------------------|-----|---------------------------|--------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| +| **Power Supplies** | | | | | +| VCC | I | | | VCC is the main power supply. It is driven from an external source and is used to power the internal VCMAIN and VCAON power domains. VCC must always be present when the device is functioning; VCC is also used to power a number of pads that must be always on when the device is functioning. | +| AVCC | I | | | Analog blocks power supply. AVCC and AGND are analog supply and ground signals for the AST analog functions. They mainly serve for ADC and USB clock functionality. AVCC is expected to be driven by the same voltage regulator and have similar power availability as VCC. AVCC and AGND have dedicated package balls/pins. In the future, package pins sharing with VCC and GND may be considered based on post-silicon test results. | +| VCMAIN | O | | | Main core power, driven by internal capless voltage regulator | +| VCAON | O | | | Core voltage power for always-on domain (same voltage range as VCMAIN) | +| VIOA | I | | | IO supply, powering a set of pads. Unlike VCC, the IO supplies can be turned off by external components and the device will continue to function, the unpowered pads however, become inoperable. | +| VIOB | I | | | Same as VIOA, but for a different set of pads. | +| GND | I | | | Ground | +| AGND | I | | | Analog ground (see AVCC for further details) | +| **Power Control and Reset** | | | | | +| otp_power_seq_i | I | 2 | async | Contains the power sequencing signals coming from the OTP macro. | +| otp_power_seq_h_o | O | 2 | async | Contains the power sequencing signals going to the OTP macro (VCC domain). | +| flash_power_down_h_o | O | 1 | async | Connected to flash (VCC domain). Used for flash power management. | +| flash_power_ready_h_o | O | 1 | async | Connected to flash (VCC domain). Used for flash power management. | +| vcmain_pok (*aka* vcmain_pok_o) | O | ast_pwst | async | Main core power-exist indication. Used by the OpenTitan power manager to determine the state of the main digital supply during power up and power down sequencing. | +| vcaon_pok (*aka* vcaon_pok_o) | O | ast_pwst | async | Always-on power-exist indication. Used by the OpenTitan power manager for power-on reset root. | +| vioa_pok (*aka* vioa_pok_o) | O | ast_pwst | async | VIOA power-exist indications. Used as a power-OK status signal. | +| viob_pok (*aka* viob_pok_o) | O | ast_pwst | async | VIOB power-exist indication. Used as a power-OK status signal. | +| por_ni | I | 1 | async | Power on reset input signal to AST. See Resets section for further details | +| main_pd_ni | I | 1 | aon | Power down enable for main core power. 0: main core power is down (deep-sleep state). 1: main core power is up. It may take up to 200 uS from this signal transition to power switching completion by AST (not including boot time and so). Note that flash must be prepared for power down before this signal is asserted. | +| main_env_iso_en_i | I | 1 | aon | Preliminary indication of VCMAIN isolation signal (main_iso_en) assertion. It is used by AST logic to latch interface signals which may no longer be valid after main_iso_en is active. This signal must be set at least 30ns before main_iso_en is active and must remain active at least 30ns after main_iso_en is no longer active. Note that main_iso_en itself asserts ahead of main_pd_ni. ie, the pwrmgr will set this signal to '1' before requesting the power be turned off. Similar, on power-on, the isolation is only released after power is restored and all powered off modules have been reset. | +| ast_init_done_o | O | mubi4 | tlul | When set, it indicates that the AST initialization was performed. Note that this signal may not be set while the chip is in TEST* or RMA lifecycle states. | +| **Clock Outputs** | | | | | +| clk_src_sys_o | O | 1 | sys | 100 MHz clock with jitter (main clock domain). Used as the main system clock. | +| clk_src_sys_val_o | O | 1 | async | System clock valid. Used as "ack" signals for the power manager | +| clk_src_sys_en_i | I | 1 | aon | System clock enable. | +| clk_src_sys_jen_i | I | mubi4 | async | System clock jitter enable | +| clk_src_aon_o | O | 1 | aon | 200 KHz clock for always-on domain. | +| clk_src_aon_val_o | O | 1 | async | aon clock valid | +| clk_src_usb_o | O | 1 | usb | 48 MHz clock for USB. To comply with USB full speed clock specification, it supports frequency accuracy of +/-2500 ppm when usb_ref_pulse_i is available and +/-3% otherwise. It may take up to 50 ms for this clock to reach the accuracy target from the time 'usb_ref_pulse_i' is available. USB clock calibration interface is further detailed here. | +| clk_src_usb_val_o | O | 1 | async | USB clock valid | +| clk_src_usb_en_i | I | 1 | aon | USB clock enable | +| usb_ref_pulse_i | I | 1 | usb | USB reference pulse +/-500ppm. When valid, it is expected to pulse for one usb clock cycle every 1ms. | +| usb_ref_val_i | I | 1 | usb | USB reference valid. This bit serves as a valid signal for the usb_ref_pulse_i signal. It is set to 1 after the first valid usb_ref_pulse_i event is detected and remains high as long as usb_ref_pulse_i continues to behave as expected (per usb_ref_pulse description). Once usb_ref_pulse deviates from its expected behavior, usb_ref_val_i immediately negates to 0 and remains 0 until after the next valid usb_ref_val pulse. | +| clk_src_io_o | O | 1 | io | 96 MHz clock with +/-3% frequency accuracy. Used for peripherals that require a fixed frequency, for example SPI and UART | +| clk_src_io_val_o | O | 1 | async | I/O and timer clock valid. Used as "ack" signals for the Power manager. | +| clk_src_io_en_i | I | 1 | aon | I/O and timer clock enable | +| clk_src_io_48m_o | O | mubi4 | aon | Clock frequency indicator. When set, it indicates that the clk_src_io_o's frequency is 48 MHz; otherwise, it is 96 MHz. | +| **Clock & Reset Inputs** | | | | | +| clk_ast_adc_i | I | 1 | adc | ADC interface clock input | +| clk_ast_rng_i | I | 1 | rng | RNG interface clock input | +| clk_ast_usb_i | I | 1 | usb | USB reference interface clock input | +| clk_ast_es_i | I | 1 | es | Entropy source interface clock input | +| clk_ast_alert_i | I | 1 | alert | Alert interface clock input | +| clk_ast_tlul_i | I | 1 | tlul | TLUL bus interface clock input | +| rst_ast_adc_ni | I | 1 | adc | ADC interface reset (active low) | +| rst_ast_rng_ni | I | 1 | rng | RNG interface reset (active low) | +| rst_ast_usb_ni | I | 1 | usb | USB reference interface reset (active low) | +| rst_ast_es_ni | I | 1 | es | Entropy source interface reset (active low) | +| rst_ast_alert_ni | I | 1 | alert | Alert interface interface reset (active low) | +| rst_ast_tlul_ni | I | 1 | tlul | TLUL bus reference interface reset (active low) | +| **Register Access Interface** | | | | | +| tlul | I/O | tl_* | tlul | TLUL bus interface. Mainly used for configuration, calibration and trimming. At boot time, data is copied from non-volatile storage into AST registers by the SW boot entity. This interface has no further use beyond this point. Runtime interaction with AST is performed by other signals as described in this document. | +| **Analog modules** | | | | | +| adc_a0_ai | I | awire | async | ADC analog input channels 0 to be measured. Signal type is awire (see ana_pkg.sv) | +| adc_a1_ai | I | awire | async | ADC analog input channels 1 to be measured. Signal type is awire (see ana_pkg.sv) | +| adc_d_o | O | 10 | adc | ADC digital data | +| adc_chnsel_i | I | 2 | adc | ADC input channel select (one hot). No more than one channel should be selected at a time. Any change in 'adc_chnsel_i' value must go through all '0'. Changing 'adc_chnsel_i' from '0' value to non-'0' value starts an ADC conversion. | +| adc_d_val_o | O | 1 | adc | ADC digital data valid | +| adc_pd_i | I | 1 | adc | ADC power down - for saving power during deep-sleep state between measurements. When this signal is high, ADC module is in off state, otherwise, it is in active state. For further description about adc_pd_i usage, see ADC module description below. | +| entropy_req_o | O | edn_req | es | Request entropy from EDN | +| entropy_rsp_i | I | edn_rsp | es | EDN entropy request acknowledgement and data. | +| rng_en_i | I | 1 | rng | Input from controller to enable RNG | +| rng_fips_i | I | 1 | rng | Indicates that the AST RNG module is requested to output FIPS SP-800-90B grade RNG bits. This may, but not necessarily affect bit-rate. This bit is a placeholder. The use of this signal inside AST is TBD. | +| rng_val_o | O | 1 | rng | RNG bit valid. This is a per-transaction valid. rng_b_o can be sampled whenever this bit is high. | +| rng_b_o | O | 4 | rng | RNG digital bit streams. The downstream controller of this signal should sample the rng_b_o whenever rng_val_o is high. | +| **Countermeasures and Alerts** | | | | | +| alert_req_o | O | ast_alert_req | alert | Alert events. There are 11 such events. The alerts are associated with countermeasures like Active shield, clock glitch detector, voltage glitch detector, temperature sensor, and others. | +| alert_rsp_i | I | ast_alert_rsp | alert | This structure contains acknowledge signals and force-trigger by software signals for each alert event. The acknowledge signals are assumed to be synchronous pulses. | +| **Trimming Test and Debug** | | | | | +| dft_scan_md_o | O | mubi4 | | Scan mode indication signal. Controllable only when DFT features are enabled (Test and RMA states). Otherwise, these signals are grounded to 0. | +| scan_shift_en_o | O | 1 | | Scan shift enable | +| scan_reset_no | O | 1 | | Scan reset | +| clk_ast_ext_i | I | 1 | async | External clock. While AST generates most of its clocks on-die, it still needs an external clock for clock calibration and first flash/OTP programming. Clock calibration: AST clock sources are inaccurate by default and must be calibrated prior to use. The results of the calibration are stored in OTP and reloaded by software upon system boot. First Flash / OTP programming: AST clock sources are inaccurate by default and may be out of range for initial flash and OTP programming. In this situation, an external clock may be required for initial programming such that a software image can be loaded to calibrate clocks and advance life cycle. | +| dft_strap_test_i | I | dft_strap_test_req | async | Strap inputs for DFT selection | +| flash_bist_en_o | O | mubi4 | | Flash BIST enable | +| vcc_supp_i | I | 1 | async | VCC Supply Test. (supply indication for DV purposes). In FPGA Verilog view, the respective POK signal follows this signal. In other Verilog views this signal should be connected to constant '1' and will be disconnected inside the AST. | +| vcmain_supp_i | I | 1 | async | VCMAIN Supply Test. (supply indication for DV purposes). In FPGA Verilog view, the respective POK signal follows this signal. In other Verilog views this signal should be connected to constant '1' and will be disconnected inside the AST. | +| vcaon_supp_i | I | 1 | async | VCAON Supply Test. (supply indication for DV purposes). In FPGA Verilog view, the respective POK signal follows this signal. In other Verilog views this signal should be connected to constant '1' and will be disconnected inside the AST. | +| vioa_supp_i | I | 1 | async | VIOA Supply Test. (supply indication for DV purposes). In FPGA Verilog view, the respective POK signal follows this signal. In other Verilog views this signal should be connected to constant '1' and will be disconnected inside the AST. | +| viob_supp_i | I | 1 | async | VIOB Supply Test. (supply indication for DV purposes). In FPGA Verilog view, the respective POK signal follows this signal. In other Verilog views this signal should be connected to constant '1' and will be disconnected inside the AST. | +| ast2pad_t0_ao, ast2pad_t1_ao | I/O | async | | Analog debug signals. These signals should be connected directly to chip PADs. They can share PADs with functional signals but when they are used for their analog debug function, the functional I/O must be in tri-state. | +| dpram_rmf_o,
dpram_rml_o,
spram_rm_o,
sprgf_rm_o,
sprom_rm_o | O | dpm_rm | async | RAM/ROM Read-write Margin Trimming | +| padmux2ast_i | I | 6 | async | Digital debug input signals (routed to pin mux). These signals are controllable only when DFT features are enabled (Test and RMA states). Otherwise, these signals are grounded to 0. | +| ast2padmux_o | O | 9 | async | Digital debug output signals (routed to pin mux). These signals are only outputted when DFT features are enabled (Test and RMA states). Otherwise, these signals are grounded to 0. | +| usb_io_pu_cal_o | O | 20 | async | USB I/O calibration and trimming | +| io_clk_byp_req_i | I | mubi4 | async | External clock mux override request for OTP bootstrap purposes. AST responds to the request by setting io_clk_byp_ack_o to 'On'. When this bit is set and ack was received, clk_ast_ext_i serves as the io_clk clock root. Note: When 'On' (after ack), clk_src_io_o clock max frequency is limited to 50 MHz | +| io_clk_byp_ack_o | O | mubi4 | async | AST response to io_clk_byp_req_i. The ack is set to 'On' after clock switching function is performed. | +| all_clk_byp_req_i | I | mubi4 | async | External clock mux override request for OTP bootstrap purposes. AST responds to the request by setting io_clk_byp_ack_o to 'On'. When this bit is set and ack was received, clk_ast_ext_i serves as the io_clk clock root. Note: When 'On' (after ack), clk_src_io_o clock max frequency is limited to 50 MHz | +| all_clk_byp_ack_o | O | mubi4 | async | AST response to io_clk_byp_req_i. The ack is set to 'On' after clock switching function is performed. | +| ext_freq_is_96m_i | I | mubi4 | async | External clock frequency indication to AST. When set, it indicates that the external clock is 96MHz. | +| lc_dft_en_i | I | lc_tx | async | DFT enable | +| fla_obs_i | I | 8 | async | Flash observe bus for debug | +| otp_bos_i | I | 8 | async | OTP observe bus for debug | +| usb_obs_i | I | 1 | async | USB differential receiver output observe for debug | +| otm_obs_i | I | 8 | async | OpenTitan modules observe bus for debug (optional) | +| obs_ctrl_o | O | ast_obs_ctrl | async | Observability control structure. It contains observability module selection, signal group selection and enable logic. Open source modules may choose to use this infrastructure for selecting and gating observability signals to be driven into otm_obs_i bus. Whether to actually use this interface or not for open source modules observability is a project decision. | +| sns_clks_i | I | clkmgr_out | async | Clocks observability | +| sns_rst_i | I | rstmgr_out_t | async | Resets observability | +| sns_spi_ext_clk_i | I | 1 | async | SPI external clock observability | diff --git a/src/ast/doc/top_diagram.png b/src/ast/doc/top_diagram.png new file mode 100644 index 0000000..6fbe3c8 Binary files /dev/null and b/src/ast/doc/top_diagram.png differ diff --git a/src/ast/lib/ast.lib b/src/ast/lib/ast.lib new file mode 100644 index 0000000..b00839d --- /dev/null +++ b/src/ast/lib/ast.lib @@ -0,0 +1,98919 @@ +brary("ast") { + + technology (cmos) ; + delay_model : table_lookup ; + library_features ( report_delay_calculation ) ; + date : "Mon Oct 3 13:12:25 2022" ; + revision : "P-2019.03-SP3" ; + nom_process : 1.000 ; + nom_voltage : 0.990 ; + nom_temperature : -40.000 ; + operating_conditions( "SSG0P99VN40C" ) { + process : 1.0000 ; + voltage : 0.9900 ; + temperature : -40.0000 ; + } /* current design opcond */ + default_operating_conditions : "SSG0P99VN40C" ; + voltage_unit : "1V" ; + time_unit : "1ns" ; + capacitive_load_unit (1.000000, pf); + slew_derate_from_library : 0.5000 ; + slew_lower_threshold_pct_rise : 30.0000 ; + slew_lower_threshold_pct_fall : 30.0000 ; + slew_upper_threshold_pct_rise : 70.0000 ; + slew_upper_threshold_pct_fall : 70.0000 ; + input_threshold_pct_rise : 50.0000 ; + input_threshold_pct_fall : 50.0000 ; + output_threshold_pct_rise : 50.0000 ; + output_threshold_pct_fall : 50.0000 ; + k_process_cell_rise : 0.000000; + k_process_cell_fall : 0.000000; + k_volt_cell_rise : 0.000000; + k_volt_cell_fall : 0.000000; + k_temp_cell_rise : 0.000000; + k_temp_cell_fall : 0.000000; + k_process_rise_transition : 0.000000; + k_process_fall_transition : 0.000000; + k_volt_rise_transition : 0.000000; + k_volt_fall_transition : 0.000000; + k_temp_rise_transition : 0.000000; + k_temp_fall_transition : 0.000000; + default_fanout_load : 1.000000; + default_inout_pin_cap : 1.000000; + default_input_pin_cap : 1.000000; + default_output_pin_cap : 0.000000; + current_unit : 1mA; + pulling_resistance_unit : "1kohm"; + comment : "PrimeTime extracted Model." ; + + define(min_delay_flag, timing, boolean); + define(internal_noise_peak_time_below_high, pin, float); + define(internal_noise_width_above_low, pin, float); + define(original_pin, pin, string); + define(internal_noise_peak_time_above_low, pin, float); + define(internal_noise_width_below_high, pin, float); + define(internal_noise_height_above_low, pin, float); + define(internal_noise_height_below_high, pin, float); + + + +/* SCALAR table template is built-in */ + +/* 2-D table template f(in_trans, out_cap) */ +lu_table_template( f_itrans_ocap ) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 (" 0.0000, 1.0000 "); + index_2 (" 0.0000, 1.0000 "); +} + +/* 2-D table template f(d_trans, c_trans) */ +lu_table_template( f_dtrans_ctrans ) { + variable_1 : constrained_pin_transition; + variable_2 : related_pin_transition; + index_1 (" 0.0000, 1.0000 "); + index_2 (" 0.0000, 1.0000 "); +} + +/* 3-D table template f(i_trans, o_cap, r_cap) */ +lu_table_template( f_itrans_ocap_rcap ) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + variable_3 : related_out_total_output_net_capacitance; + index_1 (" 0.0000, 1.0000 "); + index_2 (" 0.0000, 1.0000 "); + index_3 (" 0.0000, 1.0000 "); +} + +type ( BUS109_type0 ) { + base_type : array ; + data_type : bit ; + bit_width : 109 ; + bit_from : 108 ; + bit_to : 0 ; +} /* end of type */ +type ( BUS66_type1 ) { + base_type : array ; + data_type : bit ; + bit_width : 66 ; + bit_from : 65 ; + bit_to : 0 ; +} /* end of type */ +type ( BUS27_type2 ) { + base_type : array ; + data_type : bit ; + bit_width : 27 ; + bit_from : 26 ; + bit_to : 0 ; +} /* end of type */ +type ( BUS56_type3 ) { + base_type : array ; + data_type : bit ; + bit_width : 56 ; + bit_from : 55 ; + bit_to : 0 ; +} /* end of type */ +type ( BUS5_type4 ) { + base_type : array ; + data_type : bit ; + bit_width : 5 ; + bit_from : 4 ; + bit_to : 0 ; +} /* end of type */ +type ( BUS2_type5 ) { + base_type : array ; + data_type : bit ; + bit_width : 2 ; + bit_from : 1 ; + bit_to : 0 ; +} /* end of type */ +type ( BUS4_type6 ) { + base_type : array ; + data_type : bit ; + bit_width : 4 ; + bit_from : 3 ; + bit_to : 0 ; +} /* end of type */ +type ( BUS20_type7 ) { + base_type : array ; + data_type : bit ; + bit_width : 20 ; + bit_from : 19 ; + bit_to : 0 ; +} /* end of type */ +type ( BUS10_type8 ) { + base_type : array ; + data_type : bit ; + bit_width : 10 ; + bit_from : 9 ; + bit_to : 0 ; +} /* end of type */ +type ( BUS34_type9 ) { + base_type : array ; + data_type : bit ; + bit_width : 34 ; + bit_from : 33 ; + bit_to : 0 ; +} /* end of type */ +type ( BUS1_type10 ) { + base_type : array ; + data_type : bit ; + bit_width : 1 ; + bit_from : 0 ; + bit_to : 0 ; +} /* end of type */ +type ( BUS52_type11 ) { + base_type : array ; + data_type : bit ; + bit_width : 52 ; + bit_from : 51 ; + bit_to : 0 ; +} /* end of type */ +type ( BUS26_type12 ) { + base_type : array ; + data_type : bit ; + bit_width : 26 ; + bit_from : 25 ; + bit_to : 0 ; +} /* end of type */ +type ( BUS3_type13 ) { + base_type : array ; + data_type : bit ; + bit_width : 3 ; + bit_from : 2 ; + bit_to : 0 ; +} /* end of type */ +type ( BUS8_type14 ) { + base_type : array ; + data_type : bit ; + bit_width : 8 ; + bit_from : 7 ; + bit_to : 0 ; +} /* end of type */ +type ( BUS12_type15 ) { + base_type : array ; + data_type : bit ; + bit_width : 12 ; + bit_from : 11 ; + bit_to : 0 ; +} /* end of type */ +type ( BUS9_type16 ) { + base_type : array ; + data_type : bit ; + bit_width : 9 ; + bit_from : 8 ; + bit_to : 0 ; +} /* end of type */ + +cell( ast ) { + area : 751665.937500 ; + dont_use : true ; + dont_touch : true ; + interface_timing : true; + timing_model_type : "extracted"; + is_macro_cell : true; + +short(tl_o[64], tl_o[63]); + +short(tl_o[64], tl_o[61]); + +short(tl_o[64], tl_o[60]); + +short(tl_o[64], tl_o[59]); + +short(tl_o[64], tl_o[48]); + +short(ast_pwst_o[3], ast_pwst_h_o[3]); + +short(ast_pwst_o[2], ast_pwst_h_o[2]); + +short(ast_pwst_o[1], ast_pwst_h_o[1]); + +short(ast_pwst_o[0], ast_pwst_h_o[0]); +bus ( tl_i ) { + + bus_type : BUS109_type0 ; + direction : input ; + +pin("tl_i[108]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001908 ; + + /* Other user defined attributes. */ + original_pin : tl_i[108]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "6.014905, 5.968750, 5.938533, 5.927176, 5.940784",\ + "6.095888, 6.049733, 6.019516, 6.008159, 6.021767",\ + "6.180377, 6.134222, 6.104005, 6.092648, 6.106256",\ + "6.321913, 6.275758, 6.245541, 6.234183, 6.247791",\ + "6.558708, 6.512553, 6.482336, 6.470979, 6.484587"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "4.829596, 4.783441, 4.753223, 4.741866, 4.755474",\ + "4.919121, 4.872966, 4.842749, 4.831391, 4.844999",\ + "5.021051, 4.974896, 4.944679, 4.933322, 4.946930",\ + "5.203711, 5.157556, 5.127338, 5.115981, 5.129589",\ + "5.532049, 5.485894, 5.455677, 5.444320, 5.457928"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[108]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.214260, -0.171883, -0.137304, -0.099668, 0.184188",\ + "-0.301086, -0.258709, -0.224129, -0.186494, 0.097363",\ + "-0.394315, -0.351937, -0.317358, -0.279723, 0.004134",\ + "-0.557199, -0.514821, -0.480242, -0.442607, -0.158750",\ + "-0.829713, -0.787336, -0.752757, -0.715121, -0.431265"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.264841, -0.198767, -0.140880, -0.098858, 0.121356",\ + "-0.356827, -0.290753, -0.232866, -0.190843, 0.029370",\ + "-0.463555, -0.397481, -0.339595, -0.297572, -0.077359",\ + "-0.650171, -0.584097, -0.526210, -0.484188, -0.239846",\ + "-0.884585, -0.842168, -0.807682, -0.768234, -0.461884"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[108]_hldr*/ + +} /* end of pin tl_i[108] */ + +pin("tl_i[107]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.005151 ; + + /* Other user defined attributes. */ + original_pin : tl_i[107]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.052649, 5.006495, 4.976278, 4.964921, 4.978528",\ + "5.141132, 5.094977, 5.064761, 5.053403, 5.067011",\ + "5.243252, 5.197097, 5.166880, 5.155523, 5.169130",\ + "5.444744, 5.398589, 5.368372, 5.357015, 5.370623",\ + "5.884084, 5.837929, 5.807712, 5.796355, 5.809962"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.045798, 4.999643, 4.969427, 4.958069, 4.971677",\ + "5.140346, 5.094191, 5.063974, 5.052617, 5.066224",\ + "5.268656, 5.222501, 5.192284, 5.180927, 5.194534",\ + "5.518216, 5.472061, 5.441844, 5.430487, 5.444095",\ + "5.954391, 5.908237, 5.878020, 5.866663, 5.880270"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[107]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.187805, -0.145419, -0.110860, -0.072826, 0.215981",\ + "-0.265352, -0.222966, -0.188407, -0.150372, 0.138434",\ + "-0.358696, -0.316325, -0.281731, -0.244378, 0.035979",\ + "-0.536472, -0.494140, -0.459456, -0.423841, -0.165061",\ + "-0.854036, -0.811811, -0.776879, -0.746068, -0.546918"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.171733, -0.105842, -0.048217, -0.006266, 0.214402",\ + "-0.262898, -0.197007, -0.139383, -0.097431, 0.123236",\ + "-0.377606, -0.311610, -0.253836, -0.211843, 0.008564",\ + "-0.589409, -0.523083, -0.464836, -0.422715, -0.203127",\ + "-0.959255, -0.892271, -0.833079, -0.790704, -0.572752"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[107]_hldr*/ + +} /* end of pin tl_i[107] */ + +pin("tl_i[106]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.004836 ; + + /* Other user defined attributes. */ + original_pin : tl_i[106]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.118081, 5.071926, 5.041709, 5.030352, 5.043960",\ + "5.207886, 5.161731, 5.131514, 5.120157, 5.133764",\ + "5.325253, 5.279098, 5.248881, 5.237524, 5.251131",\ + "5.541330, 5.495175, 5.464959, 5.453601, 5.467209",\ + "5.904454, 5.858299, 5.828083, 5.816725, 5.830333"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.110147, 5.063992, 5.033775, 5.022418, 5.036025",\ + "5.198250, 5.152095, 5.121878, 5.110521, 5.124128",\ + "5.332071, 5.285916, 5.255700, 5.244342, 5.257950",\ + "5.577984, 5.531829, 5.501612, 5.490255, 5.503862",\ + "5.995383, 5.949228, 5.919012, 5.907654, 5.921262"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[106]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.198447, -0.132584, -0.074998, -0.033057, 0.187678",\ + "-0.296196, -0.230332, -0.172747, -0.130806, 0.089930",\ + "-0.398836, -0.332973, -0.275387, -0.233446, -0.012711",\ + "-0.579500, -0.513636, -0.456051, -0.414110, -0.193375",\ + "-0.884380, -0.818360, -0.760550, -0.718548, -0.498201"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.292019, -0.249633, -0.215074, -0.177056, 0.111552",\ + "-0.374431, -0.332045, -0.297485, -0.259467, 0.029140",\ + "-0.488086, -0.445700, -0.411141, -0.373122, -0.084515",\ + "-0.684457, -0.642085, -0.607494, -0.570100, -0.289245",\ + "-1.001110, -0.958772, -0.924101, -0.888239, -0.626398"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[106]_hldr*/ + +} /* end of pin tl_i[106] */ + +pin("tl_i[105]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.003624 ; + + /* Other user defined attributes. */ + original_pin : tl_i[105]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "4.863893, 4.817738, 4.787521, 4.776164, 4.789771",\ + "4.956792, 4.910637, 4.880420, 4.869063, 4.882670",\ + "5.049713, 5.003558, 4.973341, 4.961984, 4.975592",\ + "5.212534, 5.166379, 5.136162, 5.124805, 5.138412",\ + "5.493520, 5.447365, 5.417148, 5.405791, 5.419398"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "4.894609, 4.848454, 4.818238, 4.806880, 4.820488",\ + "4.991653, 4.945498, 4.915282, 4.903924, 4.917532",\ + "5.091967, 5.045812, 5.015595, 5.004238, 5.017845",\ + "5.268436, 5.222281, 5.192065, 5.180707, 5.194315",\ + "5.577918, 5.531763, 5.501546, 5.490189, 5.503797"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[105]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.191328, -0.125448, -0.067841, -0.025894, 0.194803",\ + "-0.284713, -0.218834, -0.161226, -0.119279, 0.101417",\ + "-0.376971, -0.311091, -0.253484, -0.211536, 0.009160",\ + "-0.536682, -0.470803, -0.413195, -0.371248, -0.150551",\ + "-0.807364, -0.741369, -0.683595, -0.641603, -0.421195"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.219051, -0.176666, -0.142105, -0.104110, 0.184210",\ + "-0.313450, -0.271065, -0.236504, -0.198509, 0.089812",\ + "-0.408426, -0.366041, -0.331480, -0.293485, -0.005164",\ + "-0.576090, -0.533704, -0.499144, -0.461149, -0.172828",\ + "-0.853410, -0.811045, -0.776438, -0.739355, -0.462356"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[105]_hldr*/ + +} /* end of pin tl_i[105] */ + +pin("tl_i[104]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : tl_i[104]; +} /* end of pin tl_i[104] */ + +pin("tl_i[103]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : tl_i[103]; +} /* end of pin tl_i[103] */ + +pin("tl_i[102]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : tl_i[102]; +} /* end of pin tl_i[102] */ + +pin("tl_i[101]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.002631 ; + + /* Other user defined attributes. */ + original_pin : tl_i[101]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "4.040158, 3.994009, 3.963793, 3.952436, 3.966046",\ + "4.127818, 4.081669, 4.051453, 4.040096, 4.053706",\ + "4.214727, 4.168579, 4.138362, 4.127005, 4.140615",\ + "4.367462, 4.321313, 4.291097, 4.279740, 4.293350",\ + "4.608571, 4.562422, 4.532206, 4.520849, 4.534459"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "4.240349, 4.194201, 4.163985, 4.152627, 4.166238",\ + "4.323653, 4.277504, 4.247288, 4.235931, 4.249541",\ + "4.439158, 4.393010, 4.362793, 4.351436, 4.365047",\ + "4.634571, 4.588422, 4.558206, 4.546849, 4.560459",\ + "4.954862, 4.908714, 4.878498, 4.867140, 4.880751"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[101]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.134918, -0.092500, -0.058015, -0.018552, 0.287989",\ + "-0.219595, -0.177177, -0.142692, -0.103229, 0.203312",\ + "-0.310658, -0.268270, -0.233715, -0.195609, 0.094094",\ + "-0.473587, -0.431270, -0.396549, -0.361659, -0.111869",\ + "-0.749178, -0.707041, -0.671904, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.158345, -0.092411, -0.034724, 0.007245, 0.227804",\ + "-0.246288, -0.180354, -0.122667, -0.080698, 0.139861",\ + "-0.346722, -0.280644, -0.222751, -0.180726, 0.039476",\ + "-0.532525, -0.466073, -0.407644, -0.365475, -0.146201",\ + "-0.854381, -0.786954, -0.727126, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[101]_hldr*/ + +} /* end of pin tl_i[101] */ + +pin("tl_i[100]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.002123 ; + + /* Other user defined attributes. */ + original_pin : tl_i[100]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "4.031560, 3.985412, 3.955196, 3.943839, 3.957449",\ + "4.118053, 4.071905, 4.041688, 4.030331, 4.043941",\ + "4.209411, 4.163263, 4.133047, 4.121689, 4.135300",\ + "4.373650, 4.327502, 4.297286, 4.285928, 4.299539",\ + "4.639607, 4.593459, 4.563242, 4.551885, 4.565495"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "4.345016, 4.298868, 4.268651, 4.257294, 4.270905",\ + "4.436058, 4.389909, 4.359693, 4.348336, 4.361946",\ + "4.527231, 4.481082, 4.450866, 4.439509, 4.453119",\ + "4.689745, 4.643597, 4.613381, 4.602024, 4.615634",\ + "4.957426, 4.911277, 4.881061, 4.869704, 4.883314"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[100]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.134918, -0.092500, -0.058015, -0.018552, 0.287989",\ + "-0.219595, -0.177177, -0.142692, -0.103229, 0.203312",\ + "-0.310658, -0.268270, -0.233715, -0.195609, 0.094094",\ + "-0.473587, -0.431270, -0.396549, -0.361659, -0.111869",\ + "-0.749178, -0.707041, -0.671904, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.158345, -0.092411, -0.034724, 0.007245, 0.227804",\ + "-0.246288, -0.180354, -0.122667, -0.080698, 0.139861",\ + "-0.346722, -0.280644, -0.222751, -0.180726, 0.039476",\ + "-0.532525, -0.466073, -0.407644, -0.365475, -0.146201",\ + "-0.854381, -0.786954, -0.727126, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[100]_hldr*/ + +} /* end of pin tl_i[100] */ + +pin("tl_i[99]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000562 ; + + /* Other user defined attributes. */ + original_pin : tl_i[99]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.202977, 0.157053, 0.126854, 0.115510, 0.129197",\ + "0.287655, 0.241731, 0.211532, 0.200188, 0.213875",\ + "0.378849, 0.332759, 0.302547, 0.291193, 0.304823",\ + "0.542220, 0.495729, 0.465486, 0.454109, 0.467602",\ + "0.818496, 0.771022, 0.740703, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.245106, 0.169786, 0.101633, 0.078675, 0.141673",\ + "0.333057, 0.257736, 0.189583, 0.166625, 0.229623",\ + "0.433433, 0.358121, 0.290014, 0.267131, 0.330810",\ + "0.619112, 0.543823, 0.475835, 0.453147, 0.518594",\ + "0.940670, 0.865438, 0.797763, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[99]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.134918, -0.092500, -0.058015, -0.018552, 0.287989",\ + "-0.219595, -0.177177, -0.142692, -0.103229, 0.203312",\ + "-0.310658, -0.268270, -0.233715, -0.195609, 0.094094",\ + "-0.473587, -0.431270, -0.396549, -0.361659, -0.111869",\ + "-0.749178, -0.707041, -0.671904, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.158345, -0.092411, -0.034724, 0.007245, 0.227804",\ + "-0.246288, -0.180354, -0.122667, -0.080698, 0.139861",\ + "-0.346722, -0.280644, -0.222751, -0.180726, 0.039476",\ + "-0.532525, -0.466073, -0.407644, -0.365475, -0.146201",\ + "-0.854381, -0.786954, -0.727126, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[99]_hldr*/ + +} /* end of pin tl_i[99] */ + +pin("tl_i[98]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000562 ; + + /* Other user defined attributes. */ + original_pin : tl_i[98]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.202977, 0.157053, 0.126854, 0.115510, 0.129197",\ + "0.287655, 0.241731, 0.211532, 0.200188, 0.213875",\ + "0.378849, 0.332759, 0.302547, 0.291193, 0.304823",\ + "0.542220, 0.495729, 0.465486, 0.454109, 0.467602",\ + "0.818496, 0.771022, 0.740703, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.245106, 0.169786, 0.101633, 0.078675, 0.141673",\ + "0.333057, 0.257736, 0.189583, 0.166625, 0.229623",\ + "0.433433, 0.358121, 0.290014, 0.267131, 0.330810",\ + "0.619112, 0.543823, 0.475835, 0.453147, 0.518594",\ + "0.940670, 0.865438, 0.797763, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[98]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.134918, -0.092500, -0.058015, -0.018552, 0.287989",\ + "-0.219595, -0.177177, -0.142692, -0.103229, 0.203312",\ + "-0.310658, -0.268270, -0.233715, -0.195609, 0.094094",\ + "-0.473587, -0.431270, -0.396549, -0.361659, -0.111869",\ + "-0.749178, -0.707041, -0.671904, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.158345, -0.092411, -0.034724, 0.007245, 0.227804",\ + "-0.246288, -0.180354, -0.122667, -0.080698, 0.139861",\ + "-0.346722, -0.280644, -0.222751, -0.180726, 0.039476",\ + "-0.532525, -0.466073, -0.407644, -0.365475, -0.146201",\ + "-0.854381, -0.786954, -0.727126, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[98]_hldr*/ + +} /* end of pin tl_i[98] */ + +pin("tl_i[97]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000562 ; + + /* Other user defined attributes. */ + original_pin : tl_i[97]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.202977, 0.157053, 0.126854, 0.115510, 0.129197",\ + "0.287655, 0.241731, 0.211532, 0.200188, 0.213875",\ + "0.378849, 0.332759, 0.302547, 0.291193, 0.304823",\ + "0.542220, 0.495729, 0.465486, 0.454109, 0.467602",\ + "0.818496, 0.771022, 0.740703, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.245106, 0.169786, 0.101633, 0.078675, 0.141673",\ + "0.333057, 0.257736, 0.189583, 0.166625, 0.229623",\ + "0.433433, 0.358121, 0.290014, 0.267131, 0.330810",\ + "0.619112, 0.543823, 0.475835, 0.453147, 0.518594",\ + "0.940670, 0.865438, 0.797763, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[97]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.134918, -0.092500, -0.058015, -0.018552, 0.287989",\ + "-0.219595, -0.177177, -0.142692, -0.103229, 0.203312",\ + "-0.310658, -0.268270, -0.233715, -0.195609, 0.094094",\ + "-0.473587, -0.431270, -0.396549, -0.361659, -0.111869",\ + "-0.749178, -0.707041, -0.671904, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.158345, -0.092411, -0.034724, 0.007245, 0.227804",\ + "-0.246288, -0.180354, -0.122667, -0.080698, 0.139861",\ + "-0.346722, -0.280644, -0.222751, -0.180726, 0.039476",\ + "-0.532525, -0.466073, -0.407644, -0.365475, -0.146201",\ + "-0.854381, -0.786954, -0.727126, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[97]_hldr*/ + +} /* end of pin tl_i[97] */ + +pin("tl_i[96]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000562 ; + + /* Other user defined attributes. */ + original_pin : tl_i[96]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.202977, 0.157053, 0.126854, 0.115510, 0.129197",\ + "0.287655, 0.241731, 0.211532, 0.200188, 0.213875",\ + "0.378849, 0.332759, 0.302547, 0.291193, 0.304823",\ + "0.542220, 0.495729, 0.465486, 0.454109, 0.467602",\ + "0.818496, 0.771022, 0.740703, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.245106, 0.169786, 0.101633, 0.078675, 0.141673",\ + "0.333057, 0.257736, 0.189583, 0.166625, 0.229623",\ + "0.433433, 0.358121, 0.290014, 0.267131, 0.330810",\ + "0.619112, 0.543823, 0.475835, 0.453147, 0.518594",\ + "0.940670, 0.865438, 0.797763, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[96]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.134918, -0.092500, -0.058015, -0.018552, 0.287989",\ + "-0.219595, -0.177177, -0.142692, -0.103229, 0.203312",\ + "-0.310658, -0.268270, -0.233715, -0.195609, 0.094094",\ + "-0.473587, -0.431270, -0.396549, -0.361659, -0.111869",\ + "-0.749178, -0.707041, -0.671904, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.158345, -0.092411, -0.034724, 0.007245, 0.227804",\ + "-0.246288, -0.180354, -0.122667, -0.080698, 0.139861",\ + "-0.346722, -0.280644, -0.222751, -0.180726, 0.039476",\ + "-0.532525, -0.466073, -0.407644, -0.365475, -0.146201",\ + "-0.854381, -0.786954, -0.727126, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[96]_hldr*/ + +} /* end of pin tl_i[96] */ + +pin("tl_i[95]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000562 ; + + /* Other user defined attributes. */ + original_pin : tl_i[95]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.202977, 0.157053, 0.126854, 0.115510, 0.129197",\ + "0.287655, 0.241731, 0.211532, 0.200188, 0.213875",\ + "0.378849, 0.332759, 0.302547, 0.291193, 0.304823",\ + "0.542220, 0.495729, 0.465486, 0.454109, 0.467602",\ + "0.818496, 0.771022, 0.740703, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.245106, 0.169786, 0.101633, 0.078675, 0.141673",\ + "0.333057, 0.257736, 0.189583, 0.166625, 0.229623",\ + "0.433433, 0.358121, 0.290014, 0.267131, 0.330810",\ + "0.619112, 0.543823, 0.475835, 0.453147, 0.518594",\ + "0.940670, 0.865438, 0.797763, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[95]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.134918, -0.092500, -0.058015, -0.018552, 0.287989",\ + "-0.219595, -0.177177, -0.142692, -0.103229, 0.203312",\ + "-0.310658, -0.268270, -0.233715, -0.195609, 0.094094",\ + "-0.473587, -0.431270, -0.396549, -0.361659, -0.111869",\ + "-0.749178, -0.707041, -0.671904, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.158345, -0.092411, -0.034724, 0.007245, 0.227804",\ + "-0.246288, -0.180354, -0.122667, -0.080698, 0.139861",\ + "-0.346722, -0.280644, -0.222751, -0.180726, 0.039476",\ + "-0.532525, -0.466073, -0.407644, -0.365475, -0.146201",\ + "-0.854381, -0.786954, -0.727126, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[95]_hldr*/ + +} /* end of pin tl_i[95] */ + +pin("tl_i[94]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000562 ; + + /* Other user defined attributes. */ + original_pin : tl_i[94]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.202977, 0.157053, 0.126854, 0.115510, 0.129197",\ + "0.287655, 0.241731, 0.211532, 0.200188, 0.213875",\ + "0.378849, 0.332759, 0.302547, 0.291193, 0.304823",\ + "0.542220, 0.495729, 0.465486, 0.454109, 0.467602",\ + "0.818496, 0.771022, 0.740703, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.245106, 0.169786, 0.101633, 0.078675, 0.141673",\ + "0.333057, 0.257736, 0.189583, 0.166625, 0.229623",\ + "0.433433, 0.358121, 0.290014, 0.267131, 0.330810",\ + "0.619112, 0.543823, 0.475835, 0.453147, 0.518594",\ + "0.940670, 0.865438, 0.797763, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[94]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.134918, -0.092500, -0.058015, -0.018552, 0.287989",\ + "-0.219595, -0.177177, -0.142692, -0.103229, 0.203312",\ + "-0.310658, -0.268270, -0.233715, -0.195609, 0.094094",\ + "-0.473587, -0.431270, -0.396549, -0.361659, -0.111869",\ + "-0.749178, -0.707041, -0.671904, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.158345, -0.092411, -0.034724, 0.007245, 0.227804",\ + "-0.246288, -0.180354, -0.122667, -0.080698, 0.139861",\ + "-0.346722, -0.280644, -0.222751, -0.180726, 0.039476",\ + "-0.532525, -0.466073, -0.407644, -0.365475, -0.146201",\ + "-0.854381, -0.786954, -0.727126, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[94]_hldr*/ + +} /* end of pin tl_i[94] */ + +pin("tl_i[93]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000562 ; + + /* Other user defined attributes. */ + original_pin : tl_i[93]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.202977, 0.157053, 0.126854, 0.115510, 0.129197",\ + "0.287655, 0.241731, 0.211532, 0.200188, 0.213875",\ + "0.378849, 0.332759, 0.302547, 0.291193, 0.304823",\ + "0.542220, 0.495729, 0.465486, 0.454109, 0.467602",\ + "0.818496, 0.771022, 0.740703, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.245106, 0.169786, 0.101633, 0.078675, 0.141673",\ + "0.333057, 0.257736, 0.189583, 0.166625, 0.229623",\ + "0.433433, 0.358121, 0.290014, 0.267131, 0.330810",\ + "0.619112, 0.543823, 0.475835, 0.453147, 0.518594",\ + "0.940670, 0.865438, 0.797763, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[93]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.134918, -0.092500, -0.058015, -0.018552, 0.287989",\ + "-0.219595, -0.177177, -0.142692, -0.103229, 0.203312",\ + "-0.310658, -0.268270, -0.233715, -0.195609, 0.094094",\ + "-0.473587, -0.431270, -0.396549, -0.361659, -0.111869",\ + "-0.749178, -0.707041, -0.671904, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.158345, -0.092411, -0.034724, 0.007245, 0.227804",\ + "-0.246288, -0.180354, -0.122667, -0.080698, 0.139861",\ + "-0.346722, -0.280644, -0.222751, -0.180726, 0.039476",\ + "-0.532525, -0.466073, -0.407644, -0.365475, -0.146201",\ + "-0.854381, -0.786954, -0.727126, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[93]_hldr*/ + +} /* end of pin tl_i[93] */ + +pin("tl_i[92]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000562 ; + + /* Other user defined attributes. */ + original_pin : tl_i[92]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.202977, 0.157053, 0.126854, 0.115510, 0.129197",\ + "0.287655, 0.241731, 0.211532, 0.200188, 0.213875",\ + "0.378849, 0.332759, 0.302547, 0.291193, 0.304823",\ + "0.542220, 0.495729, 0.465486, 0.454109, 0.467602",\ + "0.818496, 0.771022, 0.740703, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.245106, 0.169786, 0.101633, 0.078675, 0.141673",\ + "0.333057, 0.257736, 0.189583, 0.166625, 0.229623",\ + "0.433433, 0.358121, 0.290014, 0.267131, 0.330810",\ + "0.619112, 0.543823, 0.475835, 0.453147, 0.518594",\ + "0.940670, 0.865438, 0.797763, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[92]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.134918, -0.092500, -0.058015, -0.018552, 0.287989",\ + "-0.219595, -0.177177, -0.142692, -0.103229, 0.203312",\ + "-0.310658, -0.268270, -0.233715, -0.195609, 0.094094",\ + "-0.473587, -0.431270, -0.396549, -0.361659, -0.111869",\ + "-0.749178, -0.707041, -0.671904, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.158345, -0.092411, -0.034724, 0.007245, 0.227804",\ + "-0.246288, -0.180354, -0.122667, -0.080698, 0.139861",\ + "-0.346722, -0.280644, -0.222751, -0.180726, 0.039476",\ + "-0.532525, -0.466073, -0.407644, -0.365475, -0.146201",\ + "-0.854381, -0.786954, -0.727126, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[92]_hldr*/ + +} /* end of pin tl_i[92] */ + +pin("tl_i[91]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001976 ; + + /* Other user defined attributes. */ + original_pin : tl_i[91]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "6.041809, 5.995654, 5.965437, 5.954080, 5.967688",\ + "6.129841, 6.083686, 6.053469, 6.042112, 6.055719",\ + "6.240180, 6.194025, 6.163808, 6.152451, 6.166058",\ + "6.431971, 6.385816, 6.355599, 6.344242, 6.357849",\ + "6.749926, 6.703771, 6.673554, 6.662197, 6.675805"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "6.036389, 5.990234, 5.960017, 5.948660, 5.962267",\ + "6.118236, 6.072081, 6.041864, 6.030507, 6.044114",\ + "6.243943, 6.197788, 6.167572, 6.156214, 6.169822",\ + "6.470764, 6.424609, 6.394392, 6.383035, 6.396643",\ + "6.863174, 6.817019, 6.786803, 6.775445, 6.789053"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[91]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.151672, -1.109295, -1.074716, -1.037080, -0.753224",\ + "-1.243671, -1.201294, -1.166714, -1.129079, -0.845222",\ + "-1.323829, -1.281452, -1.246872, -1.209237, -0.925380",\ + "-1.441613, -1.399235, -1.364656, -1.327021, -1.043164",\ + "-1.629556, -1.587178, -1.552599, -1.514964, -1.231107"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.146252, -1.103875, -1.069295, -1.031660, -0.747803",\ + "-1.232066, -1.189688, -1.155109, -1.117473, -0.833617",\ + "-1.316872, -1.274495, -1.239915, -1.202280, -0.918423",\ + "-1.462124, -1.419747, -1.385167, -1.347532, -1.063675",\ + "-1.705527, -1.663150, -1.628571, -1.590935, -1.307079"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[91]_hldr*/ + +} /* end of pin tl_i[91] */ + +pin("tl_i[90]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.003090 ; + + /* Other user defined attributes. */ + original_pin : tl_i[90]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.559815, 5.513660, 5.483444, 5.472086, 5.485694",\ + "5.649643, 5.603488, 5.573271, 5.561914, 5.575521",\ + "5.741996, 5.695841, 5.665624, 5.654267, 5.667874",\ + "5.908573, 5.862418, 5.832201, 5.820844, 5.834452",\ + "6.303185, 6.257030, 6.226814, 6.215456, 6.229064"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.570656, 5.524501, 5.494284, 5.482927, 5.496534",\ + "5.661279, 5.615124, 5.584907, 5.573550, 5.587157",\ + "5.780371, 5.734216, 5.703999, 5.692642, 5.706249",\ + "6.016336, 5.970181, 5.939964, 5.928607, 5.942214",\ + "6.443535, 6.397380, 6.367163, 6.355806, 6.369413"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[90]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.123815, -1.081437, -1.046858, -1.009223, -0.725366",\ + "-1.217456, -1.175079, -1.140499, -1.102864, -0.819007",\ + "-1.332136, -1.289759, -1.255179, -1.217544, -0.933687",\ + "-1.517521, -1.475144, -1.440564, -1.402929, -1.119072",\ + "-1.805479, -1.763102, -1.728523, -1.690887, -1.407031"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.159454, -1.117077, -1.082498, -1.044862, -0.761006",\ + "-1.250402, -1.208025, -1.173445, -1.135810, -0.851953",\ + "-1.352041, -1.309663, -1.275084, -1.237449, -0.953592",\ + "-1.534891, -1.492514, -1.457935, -1.420299, -1.136443",\ + "-1.849478, -1.807101, -1.772522, -1.734886, -1.451030"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[90]_hldr*/ + +} /* end of pin tl_i[90] */ + +pin("tl_i[89]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.002521 ; + + /* Other user defined attributes. */ + original_pin : tl_i[89]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.812771, 5.766616, 5.736399, 5.725042, 5.738649",\ + "5.898168, 5.852013, 5.821796, 5.810439, 5.824046",\ + "5.975654, 5.929499, 5.899282, 5.887925, 5.901533",\ + "6.119768, 6.073613, 6.043396, 6.032039, 6.045647",\ + "6.477526, 6.431371, 6.401154, 6.389797, 6.403404"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.809771, 5.763616, 5.733399, 5.722042, 5.735649",\ + "5.892390, 5.846235, 5.816019, 5.804661, 5.818269",\ + "6.004417, 5.958262, 5.928046, 5.916688, 5.930296",\ + "6.234746, 6.188591, 6.158375, 6.147017, 6.160625",\ + "6.638525, 6.592370, 6.562153, 6.550796, 6.564404"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[89]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.029578, -0.987200, -0.952621, -0.914986, -0.631129",\ + "-1.117165, -1.074787, -1.040208, -1.002573, -0.718716",\ + "-1.206337, -1.163960, -1.129380, -1.091745, -0.807888",\ + "-1.362213, -1.319836, -1.285257, -1.247621, -0.963765",\ + "-1.590532, -1.548155, -1.513575, -1.475940, -1.192083"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.059949, -1.017572, -0.982993, -0.945357, -0.661501",\ + "-1.159550, -1.117173, -1.082594, -1.044958, -0.761102",\ + "-1.261636, -1.219259, -1.184679, -1.147044, -0.863187",\ + "-1.441043, -1.398666, -1.364086, -1.326451, -1.042594",\ + "-1.748482, -1.706105, -1.671526, -1.633890, -1.350034"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[89]_hldr*/ + +} /* end of pin tl_i[89] */ + +pin("tl_i[88]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001007 ; + + /* Other user defined attributes. */ + original_pin : tl_i[88]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.471457, 5.425303, 5.395086, 5.383729, 5.397336",\ + "5.567654, 5.521499, 5.491282, 5.479925, 5.493532",\ + "5.669107, 5.622952, 5.592736, 5.581378, 5.594986",\ + "5.849272, 5.803117, 5.772900, 5.761543, 5.775150",\ + "6.163116, 6.116961, 6.086744, 6.075387, 6.088994"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.500805, 5.454650, 5.424433, 5.413076, 5.426683",\ + "5.598975, 5.552820, 5.522604, 5.511246, 5.524854",\ + "5.704100, 5.657945, 5.627728, 5.616371, 5.629978",\ + "5.884839, 5.838684, 5.808467, 5.797110, 5.810718",\ + "6.188713, 6.142558, 6.112341, 6.100984, 6.114592"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[88]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.083938, -1.041561, -1.006981, -0.969346, -0.685489",\ + "-1.181137, -1.138760, -1.104181, -1.066545, -0.782689",\ + "-1.281549, -1.239172, -1.204592, -1.166957, -0.883101",\ + "-1.453069, -1.410691, -1.376112, -1.338477, -1.054620",\ + "-1.733325, -1.690947, -1.656368, -1.618733, -1.334876"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.081498, -1.039121, -1.004542, -0.966906, -0.683050",\ + "-1.178693, -1.136315, -1.101736, -1.064101, -0.780244",\ + "-1.285877, -1.243499, -1.208920, -1.171285, -0.887428",\ + "-1.474000, -1.431623, -1.397043, -1.359408, -1.075551",\ + "-1.791995, -1.749618, -1.715039, -1.677403, -1.393547"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[88]_hldr*/ + +} /* end of pin tl_i[88] */ + +pin("tl_i[87]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001007 ; + + /* Other user defined attributes. */ + original_pin : tl_i[87]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "6.100426, 6.054271, 6.024055, 6.012697, 6.026305",\ + "6.196661, 6.150506, 6.120289, 6.108932, 6.122540",\ + "6.301589, 6.255434, 6.225217, 6.213860, 6.227468",\ + "6.487259, 6.441104, 6.410888, 6.399530, 6.413138",\ + "6.807995, 6.761840, 6.731623, 6.720266, 6.733873"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "6.124471, 6.078316, 6.048099, 6.036742, 6.050349",\ + "6.222617, 6.176462, 6.146245, 6.134888, 6.148495",\ + "6.331584, 6.285429, 6.255212, 6.243855, 6.257463",\ + "6.520377, 6.474222, 6.444005, 6.432648, 6.446256",\ + "6.841649, 6.795494, 6.765277, 6.753920, 6.767528"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[87]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.134100, -1.091722, -1.057143, -1.019508, -0.735651",\ + "-1.231353, -1.188975, -1.154396, -1.116761, -0.832904",\ + "-1.331896, -1.289519, -1.254940, -1.217304, -0.933448",\ + "-1.503641, -1.461264, -1.426684, -1.389049, -1.105192",\ + "-1.784290, -1.741913, -1.707334, -1.669698, -1.385842"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.132025, -1.089648, -1.055068, -1.017433, -0.733576",\ + "-1.229244, -1.186866, -1.152287, -1.114652, -0.830795",\ + "-1.336593, -1.294216, -1.259636, -1.222001, -0.938144",\ + "-1.525111, -1.482733, -1.448154, -1.410519, -1.126662",\ + "-1.844292, -1.801915, -1.767335, -1.729700, -1.445843"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[87]_hldr*/ + +} /* end of pin tl_i[87] */ + +pin("tl_i[86]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.002623 ; + + /* Other user defined attributes. */ + original_pin : tl_i[86]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.848853, 5.802698, 5.772481, 5.761124, 5.774731",\ + "5.936358, 5.890203, 5.859987, 5.848629, 5.862237",\ + "6.023653, 5.977498, 5.947281, 5.935924, 5.949532",\ + "6.191101, 6.144946, 6.114729, 6.103372, 6.116980",\ + "6.582396, 6.536241, 6.506024, 6.494667, 6.508274"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.843520, 5.797365, 5.767148, 5.755791, 5.769399",\ + "5.932423, 5.886268, 5.856051, 5.844694, 5.858301",\ + "6.047498, 6.001343, 5.971126, 5.959769, 5.973376",\ + "6.285758, 6.239603, 6.209386, 6.198029, 6.211636",\ + "6.722472, 6.676317, 6.646101, 6.634743, 6.648351"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[86]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.087246, -1.044869, -1.010289, -0.972654, -0.688797",\ + "-1.172364, -1.129987, -1.095407, -1.057772, -0.773916",\ + "-1.269076, -1.226699, -1.192120, -1.154484, -0.870628",\ + "-1.437615, -1.395237, -1.360658, -1.323022, -1.039166",\ + "-1.686824, -1.644446, -1.609867, -1.572232, -1.288375"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.118792, -1.076414, -1.041835, -1.004200, -0.720343",\ + "-1.209484, -1.167107, -1.132527, -1.094892, -0.811035",\ + "-1.302947, -1.260570, -1.225991, -1.188355, -0.904499",\ + "-1.465349, -1.422972, -1.388392, -1.350757, -1.066900",\ + "-1.738277, -1.695899, -1.661320, -1.623685, -1.339828"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[86]_hldr*/ + +} /* end of pin tl_i[86] */ + +pin("tl_i[85]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.003219 ; + + /* Other user defined attributes. */ + original_pin : tl_i[85]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.640028, 5.593873, 5.563656, 5.552299, 5.565907",\ + "5.724194, 5.678039, 5.647822, 5.636465, 5.650072",\ + "5.805078, 5.758923, 5.728706, 5.717349, 5.730957",\ + "5.946632, 5.900477, 5.870261, 5.858903, 5.872511",\ + "6.188352, 6.142197, 6.111980, 6.100623, 6.114231"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.625210, 5.579055, 5.548838, 5.537481, 5.551088",\ + "5.706786, 5.660631, 5.630414, 5.619057, 5.632665",\ + "5.812987, 5.766832, 5.736616, 5.725258, 5.738866",\ + "6.001375, 5.955220, 5.925003, 5.913646, 5.927253",\ + "6.317180, 6.271025, 6.240808, 6.229451, 6.243059"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[85]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.041623, -0.999245, -0.964666, -0.927031, -0.643174",\ + "-1.126700, -1.084323, -1.049744, -1.012108, -0.728252",\ + "-1.223403, -1.181025, -1.146446, -1.108811, -0.824954",\ + "-1.391917, -1.349539, -1.314960, -1.277325, -0.993468",\ + "-1.638337, -1.595960, -1.561380, -1.523745, -1.239888"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.073138, -1.030761, -0.996182, -0.958546, -0.674690",\ + "-1.161118, -1.118740, -1.084161, -1.046526, -0.762669",\ + "-1.257352, -1.214975, -1.180395, -1.142760, -0.858903",\ + "-1.419670, -1.377293, -1.342714, -1.305078, -1.021222",\ + "-1.692554, -1.650177, -1.615597, -1.577962, -1.294106"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[85]_hldr*/ + +} /* end of pin tl_i[85] */ + +pin("tl_i[84]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001002 ; + + /* Other user defined attributes. */ + original_pin : tl_i[84]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.863610, 5.817455, 5.787239, 5.775881, 5.789489",\ + "5.963272, 5.917117, 5.886900, 5.875543, 5.889151",\ + "6.072519, 6.026364, 5.996147, 5.984790, 5.998397",\ + "6.263348, 6.217193, 6.186976, 6.175619, 6.189227",\ + "6.585179, 6.539024, 6.508808, 6.497450, 6.511058"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.949015, 5.902860, 5.872643, 5.861286, 5.874893",\ + "6.048979, 6.002824, 5.972607, 5.961250, 5.974857",\ + "6.167165, 6.121010, 6.090793, 6.079436, 6.093043",\ + "6.365981, 6.319826, 6.289609, 6.278252, 6.291860",\ + "6.701097, 6.654942, 6.624725, 6.613368, 6.626975"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[84]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.056499, -1.014122, -0.979543, -0.941907, -0.658051",\ + "-1.146680, -1.104303, -1.069723, -1.032088, -0.748231",\ + "-1.259394, -1.217017, -1.182437, -1.144802, -0.860945",\ + "-1.443621, -1.401244, -1.366664, -1.329029, -1.045172",\ + "-1.712122, -1.669745, -1.635165, -1.597530, -1.313673"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.090162, -1.047785, -1.013205, -0.975570, -0.691713",\ + "-1.180082, -1.137704, -1.103125, -1.065490, -0.781633",\ + "-1.275585, -1.233208, -1.198629, -1.160993, -0.877137",\ + "-1.445900, -1.403523, -1.368944, -1.331308, -1.047452",\ + "-1.745297, -1.702920, -1.668340, -1.630705, -1.346848"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[84]_hldr*/ + +} /* end of pin tl_i[84] */ + +pin("tl_i[83]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.003541 ; + + /* Other user defined attributes. */ + original_pin : tl_i[83]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.687950, 5.641795, 5.611578, 5.600221, 5.613829",\ + "5.774795, 5.728640, 5.698423, 5.687066, 5.700673",\ + "5.876379, 5.830224, 5.800007, 5.788650, 5.802258",\ + "6.080298, 6.034143, 6.003927, 5.992569, 6.006177",\ + "6.432961, 6.386806, 6.356589, 6.345232, 6.358839"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.703408, 5.657253, 5.627037, 5.615679, 5.629287",\ + "5.789980, 5.743825, 5.713608, 5.702251, 5.715858",\ + "5.917695, 5.871540, 5.841323, 5.829966, 5.843574",\ + "6.190283, 6.144128, 6.113912, 6.102554, 6.116162",\ + "6.660905, 6.614750, 6.584533, 6.573176, 6.586783"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[83]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.867726, -0.825349, -0.790770, -0.753134, -0.469278",\ + "-0.951320, -0.908943, -0.874363, -0.836728, -0.552871",\ + "-1.016544, -0.974167, -0.939588, -0.901952, -0.618096",\ + "-1.123735, -1.081358, -1.046778, -1.009143, -0.725286",\ + "-1.291921, -1.249544, -1.214964, -1.177329, -0.893472"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.911896, -0.869519, -0.833451, -0.791428, -0.513448",\ + "-1.012793, -0.970416, -0.921834, -0.879811, -0.614345",\ + "-1.095336, -1.052959, -1.000425, -0.958402, -0.696888",\ + "-1.226252, -1.183874, -1.131083, -1.089060, -0.827803",\ + "-1.440278, -1.397901, -1.344258, -1.302235, -1.041830"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[83]_hldr*/ + +} /* end of pin tl_i[83] */ + +pin("tl_i[82]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.002444 ; + + /* Other user defined attributes. */ + original_pin : tl_i[82]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.708182, 5.662027, 5.631811, 5.620453, 5.634061",\ + "5.801434, 5.755279, 5.725062, 5.713705, 5.727312",\ + "5.894579, 5.848424, 5.818208, 5.806850, 5.820458",\ + "6.057735, 6.011580, 5.981363, 5.970006, 5.983613",\ + "6.337201, 6.291046, 6.260829, 6.249472, 6.263080"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.710078, 5.663923, 5.633707, 5.622349, 5.635957",\ + "5.807050, 5.760895, 5.730678, 5.719321, 5.732928",\ + "5.905420, 5.859265, 5.829048, 5.817691, 5.831298",\ + "6.075630, 6.029475, 5.999258, 5.987901, 6.001508",\ + "6.350610, 6.304455, 6.274238, 6.262881, 6.276488"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[82]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.931103, -0.888726, -0.854147, -0.816511, -0.532655",\ + "-1.016007, -0.973630, -0.939050, -0.901415, -0.617558",\ + "-1.106769, -1.064392, -1.029812, -0.992177, -0.708320",\ + "-1.260793, -1.218416, -1.183836, -1.146201, -0.862344",\ + "-1.523812, -1.481435, -1.446856, -1.409220, -1.125364"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.978443, -0.936065, -0.901486, -0.863851, -0.579994",\ + "-1.073078, -1.030701, -0.996121, -0.958486, -0.674629",\ + "-1.181049, -1.138672, -1.104093, -1.066457, -0.782601",\ + "-1.371690, -1.329313, -1.294734, -1.257098, -0.973242",\ + "-1.704884, -1.662507, -1.627928, -1.590292, -1.306436"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[82]_hldr*/ + +} /* end of pin tl_i[82] */ + +pin("tl_i[81]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.002980 ; + + /* Other user defined attributes. */ + original_pin : tl_i[81]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.772726, 5.726571, 5.696354, 5.684997, 5.698605",\ + "5.867767, 5.821612, 5.791396, 5.780038, 5.793646",\ + "5.991376, 5.945221, 5.915004, 5.903647, 5.917254",\ + "6.241336, 6.195181, 6.164964, 6.153607, 6.167214",\ + "6.709605, 6.663450, 6.633233, 6.621876, 6.635483"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.760269, 5.714114, 5.683897, 5.672540, 5.686147",\ + "5.853128, 5.806973, 5.776756, 5.765399, 5.779006",\ + "5.986612, 5.940457, 5.910241, 5.898883, 5.912491",\ + "6.273496, 6.227341, 6.197124, 6.185767, 6.199374",\ + "6.818243, 6.772088, 6.741871, 6.730514, 6.744122"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[81]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.928193, -0.885816, -0.851236, -0.813601, -0.529744",\ + "-1.010898, -0.968521, -0.933941, -0.896306, -0.612449",\ + "-1.110272, -1.067895, -1.033316, -0.995680, -0.711824",\ + "-1.278434, -1.236057, -1.201477, -1.163842, -0.879985",\ + "-1.568159, -1.525781, -1.491202, -1.453566, -1.169710"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.972769, -0.930391, -0.895812, -0.858176, -0.574320",\ + "-1.064861, -1.022484, -0.987905, -0.950269, -0.666413",\ + "-1.170576, -1.128199, -1.093619, -1.055984, -0.772127",\ + "-1.359091, -1.316714, -1.282135, -1.244499, -0.960643",\ + "-1.694739, -1.652362, -1.617782, -1.580147, -1.296290"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[81]_hldr*/ + +} /* end of pin tl_i[81] */ + +pin("tl_i[80]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.004096 ; + + /* Other user defined attributes. */ + original_pin : tl_i[80]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.423539, 5.377384, 5.347167, 5.335810, 5.349418",\ + "5.507660, 5.461505, 5.431288, 5.419931, 5.433538",\ + "5.588662, 5.542507, 5.512290, 5.500933, 5.514540",\ + "5.729993, 5.683838, 5.653621, 5.642264, 5.655871",\ + "5.971819, 5.925664, 5.895447, 5.884090, 5.897697"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.408631, 5.362476, 5.332260, 5.320902, 5.334510",\ + "5.490341, 5.444186, 5.413970, 5.402612, 5.416220",\ + "5.596552, 5.550397, 5.520180, 5.508823, 5.522430",\ + "5.784794, 5.738639, 5.708422, 5.697065, 5.710672",\ + "6.157783, 6.111628, 6.081411, 6.070054, 6.083661"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[80]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.991939, -0.949562, -0.914982, -0.877347, -0.593490",\ + "-1.074940, -1.032563, -0.997983, -0.960348, -0.676491",\ + "-1.172758, -1.130381, -1.095802, -1.058166, -0.774310",\ + "-1.338347, -1.295969, -1.261390, -1.223755, -0.939898",\ + "-1.624824, -1.582447, -1.547868, -1.510232, -1.226376"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.037009, -0.994632, -0.960053, -0.922417, -0.638561",\ + "-1.129460, -1.087082, -1.052503, -1.014868, -0.731011",\ + "-1.235564, -1.193187, -1.158608, -1.120972, -0.837116",\ + "-1.410576, -1.368199, -1.333619, -1.295984, -1.012127",\ + "-1.676313, -1.633936, -1.599356, -1.561721, -1.277864"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[80]_hldr*/ + +} /* end of pin tl_i[80] */ + +pin("tl_i[79]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001007 ; + + /* Other user defined attributes. */ + original_pin : tl_i[79]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.446656, 5.400501, 5.370284, 5.358927, 5.372534",\ + "5.547154, 5.500999, 5.470783, 5.459425, 5.473033",\ + "5.662600, 5.616445, 5.586228, 5.574871, 5.588478",\ + "5.873106, 5.826951, 5.796734, 5.785377, 5.798985",\ + "6.242186, 6.196031, 6.165814, 6.154457, 6.168064"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.480749, 5.434594, 5.404377, 5.393020, 5.406628",\ + "5.579840, 5.533685, 5.503468, 5.492111, 5.505718",\ + "5.703683, 5.657528, 5.627311, 5.615954, 5.629561",\ + "5.911795, 5.865640, 5.835423, 5.824066, 5.837673",\ + "6.265936, 6.219781, 6.189564, 6.178207, 6.191814"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[79]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.093242, -1.050865, -1.016285, -0.978650, -0.694793",\ + "-1.195110, -1.152733, -1.118154, -1.080518, -0.796662",\ + "-1.314294, -1.271917, -1.237338, -1.199702, -0.915846",\ + "-1.525733, -1.483356, -1.448776, -1.411141, -1.127284",\ + "-1.885126, -1.842748, -1.808169, -1.770533, -1.486677"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.071935, -1.029557, -0.994978, -0.957343, -0.673486",\ + "-1.171764, -1.129387, -1.094808, -1.057172, -0.773316",\ + "-1.298104, -1.255727, -1.221148, -1.183512, -0.899656",\ + "-1.517193, -1.474816, -1.440237, -1.402601, -1.118745",\ + "-1.889590, -1.847213, -1.812633, -1.774998, -1.491141"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[79]_hldr*/ + +} /* end of pin tl_i[79] */ + +pin("tl_i[78]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.002174 ; + + /* Other user defined attributes. */ + original_pin : tl_i[78]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.182078, 5.135923, 5.105707, 5.094349, 5.107957",\ + "5.277516, 5.231361, 5.201145, 5.189787, 5.203395",\ + "5.400351, 5.354196, 5.323979, 5.312622, 5.326229",\ + "5.638412, 5.592257, 5.562040, 5.550683, 5.564290",\ + "6.058977, 6.012822, 5.982605, 5.971248, 5.984856"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.163897, 5.117742, 5.087525, 5.076168, 5.089776",\ + "5.262290, 5.216135, 5.185918, 5.174561, 5.188169",\ + "5.405017, 5.358862, 5.328645, 5.317288, 5.330895",\ + "5.691147, 5.644992, 5.614775, 5.603418, 5.617025",\ + "6.209457, 6.163302, 6.133085, 6.121728, 6.135335"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[78]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.808182, -0.765804, -0.731225, -0.693590, -0.409733",\ + "-0.891099, -0.848721, -0.814142, -0.776506, -0.492650",\ + "-0.960506, -0.918129, -0.883550, -0.845914, -0.562058",\ + "-1.077306, -1.034929, -1.000349, -0.962714, -0.678857",\ + "-1.260451, -1.218073, -1.183494, -1.145859, -0.862002"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.822461, -0.780084, -0.745505, -0.707869, -0.424013",\ + "-0.907616, -0.865238, -0.830659, -0.793024, -0.509167",\ + "-0.995187, -0.952809, -0.918230, -0.880595, -0.596738",\ + "-1.146480, -1.104103, -1.069523, -1.031888, -0.748031",\ + "-1.401185, -1.358808, -1.324229, -1.286593, -1.002737"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[78]_hldr*/ + +} /* end of pin tl_i[78] */ + +pin("tl_i[77]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001980 ; + + /* Other user defined attributes. */ + original_pin : tl_i[77]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.530322, 5.484167, 5.453950, 5.442593, 5.456201",\ + "5.617828, 5.571673, 5.541456, 5.530099, 5.543706",\ + "5.705123, 5.658968, 5.628751, 5.617394, 5.631001",\ + "5.872606, 5.826451, 5.796235, 5.784877, 5.798485",\ + "6.261807, 6.215652, 6.185436, 6.174078, 6.187686"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.524989, 5.478834, 5.448617, 5.437260, 5.450868",\ + "5.613892, 5.567737, 5.537520, 5.526163, 5.539771",\ + "5.728968, 5.682813, 5.652596, 5.641239, 5.654846",\ + "5.967242, 5.921087, 5.890870, 5.879513, 5.893120",\ + "6.403997, 6.357842, 6.327626, 6.316268, 6.329876"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[77]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.941463, -0.899085, -0.864506, -0.826870, -0.543014",\ + "-1.026243, -0.983865, -0.949286, -0.911651, -0.627794",\ + "-1.097818, -1.055441, -1.020861, -0.983226, -0.699369",\ + "-1.219287, -1.176910, -1.142331, -1.104695, -0.820839",\ + "-1.414036, -1.371659, -1.337079, -1.299444, -1.015587"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.962457, -0.920079, -0.885500, -0.847865, -0.564008",\ + "-1.048641, -1.006264, -0.971684, -0.934049, -0.650192",\ + "-1.136345, -1.093968, -1.059388, -1.021753, -0.737896",\ + "-1.287015, -1.244637, -1.210058, -1.172423, -0.888566",\ + "-1.540997, -1.498620, -1.464041, -1.426405, -1.142549"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[77]_hldr*/ + +} /* end of pin tl_i[77] */ + +pin("tl_i[76]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.002121 ; + + /* Other user defined attributes. */ + original_pin : tl_i[76]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.188263, 5.142108, 5.111891, 5.100534, 5.114141",\ + "5.280335, 5.234180, 5.203964, 5.192606, 5.206214",\ + "5.390166, 5.344011, 5.313795, 5.302437, 5.316045",\ + "5.594857, 5.548702, 5.518486, 5.507128, 5.520736",\ + "5.971145, 5.924990, 5.894773, 5.883416, 5.897023"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.181033, 5.134878, 5.104661, 5.093304, 5.106912",\ + "5.279116, 5.232961, 5.202744, 5.191387, 5.204994",\ + "5.410749, 5.364594, 5.334378, 5.323020, 5.336628",\ + "5.655250, 5.609095, 5.578878, 5.567521, 5.581128",\ + "6.082715, 6.036560, 6.006343, 5.994986, 6.008594"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[76]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.873539, -0.831162, -0.796583, -0.758947, -0.475091",\ + "-0.958672, -0.916295, -0.881715, -0.844080, -0.560223",\ + "-1.055412, -1.013035, -0.978456, -0.940820, -0.656964",\ + "-1.223937, -1.181559, -1.146980, -1.109345, -0.825488",\ + "-1.471815, -1.429437, -1.394858, -1.357222, -1.073366"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.905092, -0.862715, -0.828135, -0.790500, -0.506643",\ + "-0.994562, -0.952185, -0.917606, -0.879970, -0.596114",\ + "-1.089293, -1.046916, -1.012336, -0.974701, -0.690844",\ + "-1.251651, -1.209274, -1.174694, -1.137059, -0.853202",\ + "-1.524578, -1.482201, -1.447622, -1.409986, -1.126130"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[76]_hldr*/ + +} /* end of pin tl_i[76] */ + +pin("tl_i[75]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.002542 ; + + /* Other user defined attributes. */ + original_pin : tl_i[75]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.559262, 5.513107, 5.482891, 5.471533, 5.485141",\ + "5.649136, 5.602981, 5.572764, 5.561407, 5.575014",\ + "5.741644, 5.695489, 5.665273, 5.653915, 5.667523",\ + "5.907515, 5.861360, 5.831143, 5.819786, 5.833393",\ + "6.276364, 6.230209, 6.199993, 6.188635, 6.202243"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.570172, 5.524017, 5.493801, 5.482443, 5.496051",\ + "5.660883, 5.614728, 5.584512, 5.573154, 5.586762",\ + "5.779753, 5.733598, 5.703381, 5.692024, 5.705631",\ + "6.011688, 5.965533, 5.935317, 5.923959, 5.937567",\ + "6.423101, 6.376946, 6.346730, 6.335372, 6.348980"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[75]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.889999, -0.847622, -0.813043, -0.775407, -0.491551",\ + "-0.980238, -0.937861, -0.903281, -0.865646, -0.581789",\ + "-1.093020, -1.050642, -1.016063, -0.978428, -0.694571",\ + "-1.275653, -1.233275, -1.198696, -1.161060, -0.877204",\ + "-1.544115, -1.501738, -1.467158, -1.429523, -1.145666"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.923539, -0.881162, -0.846582, -0.808947, -0.525090",\ + "-1.013448, -0.971071, -0.936491, -0.898856, -0.614999",\ + "-1.108924, -1.066547, -1.031967, -0.994332, -0.710475",\ + "-1.279292, -1.236915, -1.202336, -1.164700, -0.880844",\ + "-1.578850, -1.536472, -1.501893, -1.464258, -1.180401"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[75]_hldr*/ + +} /* end of pin tl_i[75] */ + +pin("tl_i[74]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.002632 ; + + /* Other user defined attributes. */ + original_pin : tl_i[74]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.253567, 5.207412, 5.177195, 5.165838, 5.179445",\ + "5.349404, 5.303249, 5.273033, 5.261675, 5.275283",\ + "5.476182, 5.430027, 5.399810, 5.388453, 5.402061",\ + "5.733068, 5.686913, 5.656696, 5.645339, 5.658946",\ + "6.219316, 6.173161, 6.142944, 6.131587, 6.145194"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.241081, 5.194926, 5.164710, 5.153352, 5.166960",\ + "5.334809, 5.288654, 5.258438, 5.247080, 5.260688",\ + "5.471406, 5.425251, 5.395034, 5.383677, 5.397285",\ + "5.764438, 5.718283, 5.688066, 5.676709, 5.690317",\ + "6.325636, 6.279481, 6.249264, 6.237907, 6.251514"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[74]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.935219, -0.892842, -0.858263, -0.820627, -0.536771",\ + "-1.028860, -0.986483, -0.951903, -0.914268, -0.630411",\ + "-1.143547, -1.101169, -1.066590, -1.028955, -0.745098",\ + "-1.326218, -1.283841, -1.249262, -1.211626, -0.927770",\ + "-1.614166, -1.571789, -1.537210, -1.499574, -1.215718"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.970892, -0.928514, -0.893935, -0.856300, -0.572443",\ + "-1.061820, -1.019442, -0.984863, -0.947227, -0.663371",\ + "-1.163435, -1.121057, -1.086478, -1.048843, -0.764986",\ + "-1.346292, -1.303915, -1.269336, -1.231700, -0.947844",\ + "-1.660875, -1.618498, -1.583918, -1.546283, -1.262426"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[74]_hldr*/ + +} /* end of pin tl_i[74] */ + +pin("tl_i[73]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.002107 ; + + /* Other user defined attributes. */ + original_pin : tl_i[73]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.554523, 5.508368, 5.478152, 5.466794, 5.480402",\ + "5.649414, 5.603259, 5.573042, 5.561685, 5.575293",\ + "5.748847, 5.702692, 5.672475, 5.661118, 5.674726",\ + "5.924383, 5.878228, 5.848011, 5.836654, 5.850262",\ + "6.224755, 6.178600, 6.148384, 6.137026, 6.150634"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.589440, 5.543285, 5.513069, 5.501711, 5.515319",\ + "5.687266, 5.641111, 5.610895, 5.599537, 5.613145",\ + "5.793367, 5.747212, 5.716996, 5.705638, 5.719246",\ + "5.973481, 5.927326, 5.897110, 5.885752, 5.899360",\ + "6.270272, 6.224117, 6.193900, 6.182543, 6.196150"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[73]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.898724, -0.856347, -0.821768, -0.784132, -0.500276",\ + "-0.983802, -0.941425, -0.906845, -0.869210, -0.585353",\ + "-1.080504, -1.038127, -1.003548, -0.965912, -0.682056",\ + "-1.249018, -1.206641, -1.172062, -1.134426, -0.850570",\ + "-1.495438, -1.453061, -1.418482, -1.380846, -1.096990"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.930240, -0.887863, -0.853283, -0.815648, -0.531791",\ + "-1.018219, -0.975842, -0.941263, -0.903627, -0.619771",\ + "-1.114454, -1.072076, -1.037497, -0.999861, -0.716005",\ + "-1.276772, -1.234395, -1.199815, -1.162180, -0.878323",\ + "-1.549656, -1.507279, -1.472699, -1.435064, -1.151207"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[73]_hldr*/ + +} /* end of pin tl_i[73] */ + +pin("tl_i[72]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001514 ; + + /* Other user defined attributes. */ + original_pin : tl_i[72]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "4.995496, 4.949341, 4.919124, 4.907767, 4.921374",\ + "5.088820, 5.042665, 5.012448, 5.001091, 5.014698",\ + "5.200553, 5.154398, 5.124181, 5.112824, 5.126431",\ + "5.410159, 5.364004, 5.333787, 5.322430, 5.336038",\ + "5.770847, 5.724692, 5.694476, 5.683118, 5.696726"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "4.983222, 4.937068, 4.906851, 4.895494, 4.909101",\ + "5.083534, 5.037379, 5.007162, 4.995805, 5.009412",\ + "5.216234, 5.170079, 5.139863, 5.128505, 5.142113",\ + "5.462753, 5.416598, 5.386382, 5.375024, 5.388632",\ + "5.894033, 5.847878, 5.817662, 5.806304, 5.819912"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[72]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.828673, -0.786296, -0.751717, -0.714081, -0.430225",\ + "-0.916407, -0.874030, -0.839450, -0.801815, -0.517958",\ + "-1.009412, -0.967034, -0.932455, -0.894819, -0.610963",\ + "-1.161535, -1.119158, -1.084578, -1.046943, -0.763086",\ + "-1.413529, -1.371152, -1.336573, -1.298937, -1.015081"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.840436, -0.798058, -0.763479, -0.725843, -0.441987",\ + "-0.930307, -0.887930, -0.853350, -0.815715, -0.531858",\ + "-1.024595, -0.982218, -0.947639, -0.910003, -0.626147",\ + "-1.178880, -1.136502, -1.101923, -1.064288, -0.780431",\ + "-1.440355, -1.397978, -1.363399, -1.325763, -1.041907"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[72]_hldr*/ + +} /* end of pin tl_i[72] */ + +pin("tl_i[71]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.002444 ; + + /* Other user defined attributes. */ + original_pin : tl_i[71]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.540210, 5.494055, 5.463838, 5.452481, 5.466088",\ + "5.637518, 5.591363, 5.561146, 5.549789, 5.563396",\ + "5.743839, 5.697684, 5.667468, 5.656110, 5.669718",\ + "5.935360, 5.889205, 5.858988, 5.847631, 5.861238",\ + "6.275519, 6.229364, 6.199148, 6.187790, 6.201398"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.544911, 5.498756, 5.468540, 5.457182, 5.470790",\ + "5.643330, 5.597175, 5.566958, 5.555601, 5.569208",\ + "5.758502, 5.712348, 5.682131, 5.670774, 5.684381",\ + "5.954805, 5.908650, 5.878434, 5.867076, 5.880684",\ + "6.290164, 6.244009, 6.213792, 6.202435, 6.216042"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[71]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.882892, -0.840514, -0.805935, -0.768299, -0.484443",\ + "-0.976532, -0.934155, -0.899575, -0.861940, -0.578083",\ + "-1.091232, -1.048855, -1.014276, -0.976640, -0.692784",\ + "-1.273476, -1.231099, -1.196519, -1.158884, -0.875027",\ + "-1.558704, -1.516327, -1.481747, -1.444112, -1.160255"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.918558, -0.876180, -0.841601, -0.803965, -0.520109",\ + "-1.009478, -0.967101, -0.932522, -0.894886, -0.611030",\ + "-1.111122, -1.068745, -1.034165, -0.996530, -0.712673",\ + "-1.293967, -1.251589, -1.217010, -1.179375, -0.895518",\ + "-1.608551, -1.566173, -1.531594, -1.493959, -1.210102"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[71]_hldr*/ + +} /* end of pin tl_i[71] */ + +pin("tl_i[70]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.002521 ; + + /* Other user defined attributes. */ + original_pin : tl_i[70]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.558736, 5.512581, 5.482364, 5.471007, 5.484614",\ + "5.646551, 5.600396, 5.570179, 5.558822, 5.572429",\ + "5.751346, 5.705191, 5.674974, 5.663617, 5.677224",\ + "5.931952, 5.885797, 5.855580, 5.844223, 5.857830",\ + "6.227381, 6.181226, 6.151009, 6.139652, 6.153259"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.559927, 5.513772, 5.483556, 5.472198, 5.485806",\ + "5.643667, 5.597512, 5.567295, 5.555938, 5.569545",\ + "5.760825, 5.714670, 5.684453, 5.673096, 5.686704",\ + "5.980465, 5.934310, 5.904093, 5.892736, 5.906343",\ + "6.363138, 6.316983, 6.286767, 6.275409, 6.289017"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[70]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.108714, -1.066337, -1.031757, -0.994122, -0.710265",\ + "-1.197711, -1.155334, -1.120755, -1.083119, -0.799263",\ + "-1.273206, -1.230828, -1.196249, -1.158614, -0.874757",\ + "-1.400542, -1.358165, -1.323586, -1.285950, -1.002094",\ + "-1.588133, -1.545756, -1.511176, -1.473541, -1.189684"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.109905, -1.067528, -1.032949, -0.995313, -0.711457",\ + "-1.194827, -1.152450, -1.117871, -1.080235, -0.796379",\ + "-1.282685, -1.240308, -1.205728, -1.168093, -0.884236",\ + "-1.434258, -1.391881, -1.357301, -1.319666, -1.035809",\ + "-1.689183, -1.646805, -1.612226, -1.574591, -1.290734"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[70]_hldr*/ + +} /* end of pin tl_i[70] */ + +pin("tl_i[69]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.003551 ; + + /* Other user defined attributes. */ + original_pin : tl_i[69]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.599169, 5.553014, 5.522797, 5.511440, 5.525047",\ + "5.692371, 5.646216, 5.615999, 5.604642, 5.618249",\ + "5.803999, 5.757844, 5.727628, 5.716270, 5.729878",\ + "6.013692, 5.967537, 5.937320, 5.925963, 5.939570",\ + "6.374660, 6.328505, 6.298288, 6.286931, 6.300539"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.586902, 5.540747, 5.510530, 5.499173, 5.512780",\ + "5.687091, 5.640936, 5.610719, 5.599362, 5.612969",\ + "5.819899, 5.773744, 5.743527, 5.732170, 5.745778",\ + "6.066907, 6.020752, 5.990536, 5.979178, 5.992786",\ + "6.499193, 6.453038, 6.422822, 6.411464, 6.425072"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[69]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.320298, -0.254656, -0.197381, -0.155524, 0.065753",\ + "-0.418767, -0.353125, -0.295851, -0.253993, -0.032716",\ + "-0.541359, -0.475718, -0.418443, -0.376585, -0.155308",\ + "-0.758841, -0.693200, -0.635925, -0.594067, -0.372790",\ + "-1.125992, -1.060351, -1.003076, -0.961219, -0.690840"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.551837, -0.504668, -0.447037, -0.405084, -0.122660",\ + "-0.642640, -0.595471, -0.537840, -0.495887, -0.213464",\ + "-0.748319, -0.701138, -0.643507, -0.601553, -0.319143",\ + "-0.935804, -0.888444, -0.830813, -0.788860, -0.506627",\ + "-1.256943, -1.209575, -1.151944, -1.109991, -0.827767"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[69]_hldr*/ + +} /* end of pin tl_i[69] */ + +pin("tl_i[68]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.003064 ; + + /* Other user defined attributes. */ + original_pin : tl_i[68]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.192542, 5.146387, 5.116170, 5.104813, 5.118420",\ + "5.290967, 5.244812, 5.214595, 5.203238, 5.216846",\ + "5.401109, 5.354954, 5.324737, 5.313380, 5.326987",\ + "5.601238, 5.555083, 5.524867, 5.513509, 5.527117",\ + "5.960707, 5.914552, 5.884336, 5.872978, 5.886586"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.225666, 5.179511, 5.149294, 5.137937, 5.151545",\ + "5.325410, 5.279255, 5.249039, 5.237681, 5.251289",\ + "5.445796, 5.399642, 5.369425, 5.358068, 5.371675",\ + "5.657081, 5.610926, 5.580709, 5.569352, 5.582960",\ + "6.029737, 5.983582, 5.953365, 5.942008, 5.955616"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[68]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.383405, -0.317283, -0.259327, -0.217286, 0.002808",\ + "-0.476585, -0.410463, -0.352507, -0.310465, -0.090372",\ + "-0.609199, -0.543558, -0.486283, -0.444425, -0.212329",\ + "-0.768597, -0.702956, -0.645681, -0.603824, -0.382547",\ + "-1.029441, -0.963800, -0.906525, -0.864667, -0.643390"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.807548, -0.765101, -0.730685, -0.689878, -0.366659",\ + "-0.886339, -0.843892, -0.809476, -0.768669, -0.445450",\ + "-0.998027, -0.955579, -0.921164, -0.880357, -0.557138",\ + "-1.202545, -1.160097, -1.125682, -1.084875, -0.761656",\ + "-1.556186, -1.513738, -1.479323, -1.438516, -1.115297"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[68]_hldr*/ + +} /* end of pin tl_i[68] */ + +pin("tl_i[67]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.004926 ; + + /* Other user defined attributes. */ + original_pin : tl_i[67]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.584554, 5.538399, 5.508182, 5.496825, 5.510432",\ + "5.677766, 5.631611, 5.601395, 5.590037, 5.603645",\ + "5.772066, 5.725911, 5.695694, 5.684337, 5.697944",\ + "5.938811, 5.892656, 5.862439, 5.851082, 5.864689",\ + "6.232008, 6.185853, 6.155637, 6.144279, 6.157887"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.609763, 5.563608, 5.533391, 5.522034, 5.535642",\ + "5.706739, 5.660584, 5.630367, 5.619010, 5.632617",\ + "5.807685, 5.761530, 5.731313, 5.719956, 5.733563",\ + "5.987043, 5.940888, 5.910672, 5.899314, 5.912922",\ + "6.348396, 6.302241, 6.272024, 6.260667, 6.274274"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[67]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.485126, -0.438062, -0.380431, -0.338477, -0.011156",\ + "-0.583825, -0.522452, -0.464496, -0.422454, -0.110899",\ + "-0.666073, -0.599951, -0.541995, -0.499953, -0.221634",\ + "-0.802234, -0.736112, -0.678156, -0.636114, -0.414195",\ + "-1.028199, -0.962077, -0.904121, -0.862080, -0.641986"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.387383, -0.321742, -0.264467, -0.222610, -0.001333",\ + "-0.478290, -0.412648, -0.355373, -0.313516, -0.092239",\ + "-0.583616, -0.517975, -0.460700, -0.418842, -0.197565",\ + "-0.772257, -0.706615, -0.649340, -0.607483, -0.386206",\ + "-1.096755, -1.031114, -0.973839, -0.931981, -0.710704"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[67]_hldr*/ + +} /* end of pin tl_i[67] */ + +pin("tl_i[66]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.005701 ; + + /* Other user defined attributes. */ + original_pin : tl_i[66]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.639438, 5.593283, 5.563066, 5.551709, 5.565317",\ + "5.733038, 5.686883, 5.656666, 5.645309, 5.658916",\ + "5.848727, 5.802572, 5.772356, 5.760998, 5.774606",\ + "6.068509, 6.022354, 5.992137, 5.980780, 5.994387",\ + "6.462988, 6.416833, 6.386617, 6.375259, 6.388867"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.621106, 5.574951, 5.544734, 5.533377, 5.546984",\ + "5.717392, 5.671237, 5.641021, 5.629663, 5.643271",\ + "5.853546, 5.807391, 5.777174, 5.765817, 5.779424",\ + "6.124442, 6.078287, 6.048070, 6.036713, 6.050320",\ + "6.621989, 6.575834, 6.545618, 6.534260, 6.547868"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[66]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.421962, -0.356320, -0.299045, -0.257188, -0.035911",\ + "-0.516417, -0.450775, -0.393500, -0.351643, -0.130366",\ + "-0.609921, -0.544280, -0.487005, -0.445147, -0.223870",\ + "-0.772065, -0.706424, -0.649149, -0.607291, -0.386014",\ + "-0.961881, -0.895759, -0.837803, -0.795761, -0.575668"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.486628, -0.441846, -0.402838, -0.353988, 0.043935",\ + "-0.578095, -0.533313, -0.494305, -0.445455, -0.047532",\ + "-0.684334, -0.639552, -0.600544, -0.551694, -0.153771",\ + "-0.874257, -0.829475, -0.790467, -0.741616, -0.343693",\ + "-1.203886, -1.159104, -1.120096, -1.071246, -0.673323"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[66]_hldr*/ + +} /* end of pin tl_i[66] */ + +pin("tl_i[65]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.005716 ; + + /* Other user defined attributes. */ + original_pin : tl_i[65]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.459126, 5.412971, 5.382754, 5.371397, 5.385004",\ + "5.554200, 5.508045, 5.477829, 5.466471, 5.480079",\ + "5.677998, 5.631843, 5.601626, 5.590269, 5.603877",\ + "5.927989, 5.881835, 5.851618, 5.840261, 5.853868",\ + "6.397048, 6.350893, 6.320677, 6.309319, 6.322927"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.446668, 5.400513, 5.370296, 5.358939, 5.372547",\ + "5.539561, 5.493406, 5.463189, 5.451832, 5.465439",\ + "5.673235, 5.627080, 5.596863, 5.585506, 5.599113",\ + "5.960149, 5.913994, 5.883777, 5.872420, 5.886027",\ + "6.505686, 6.459531, 6.429315, 6.417957, 6.431565"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[65]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.425878, -0.360237, -0.302962, -0.261104, -0.039827",\ + "-0.522669, -0.457028, -0.399753, -0.357895, -0.136618",\ + "-0.621719, -0.556077, -0.498802, -0.456945, -0.235668",\ + "-0.791700, -0.725578, -0.667622, -0.625580, -0.405487",\ + "-0.986124, -0.920002, -0.862046, -0.820004, -0.599911"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.460052, -0.415270, -0.376262, -0.327412, 0.070511",\ + "-0.556623, -0.511841, -0.472833, -0.423982, -0.026060",\ + "-0.658589, -0.613808, -0.574799, -0.525949, -0.128026",\ + "-0.841385, -0.796603, -0.757595, -0.708745, -0.310822",\ + "-1.144313, -1.099531, -1.060523, -1.011673, -0.613750"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[65]_hldr*/ + +} /* end of pin tl_i[65] */ + +pin("tl_i[64]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.004569 ; + + /* Other user defined attributes. */ + original_pin : tl_i[64]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.444655, 5.398500, 5.368283, 5.356926, 5.370533",\ + "5.543582, 5.497427, 5.467211, 5.455853, 5.469461",\ + "5.653337, 5.607182, 5.576965, 5.565608, 5.579216",\ + "5.851637, 5.805482, 5.775266, 5.763908, 5.777516",\ + "6.204331, 6.158176, 6.127959, 6.116602, 6.130209"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.478401, 5.432246, 5.402030, 5.390672, 5.404280",\ + "5.578437, 5.532282, 5.502066, 5.490708, 5.504316",\ + "5.698844, 5.652689, 5.622473, 5.611115, 5.624723",\ + "5.908003, 5.861848, 5.831632, 5.820274, 5.833882",\ + "6.273140, 6.226985, 6.196769, 6.185411, 6.199019"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[64]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.425314, -0.367605, -0.313198, -0.274713, -0.048281",\ + "-0.523194, -0.465485, -0.411079, -0.372594, -0.146162",\ + "-0.645804, -0.588095, -0.533688, -0.495204, -0.268772",\ + "-0.855838, -0.798129, -0.743723, -0.705238, -0.478806",\ + "-1.193156, -1.127033, -1.069077, -1.027036, -0.806943"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.376914, -0.311272, -0.253997, -0.212140, 0.059682",\ + "-0.475849, -0.410207, -0.352932, -0.311075, -0.039253",\ + "-0.593819, -0.528177, -0.470902, -0.429045, -0.157173",\ + "-0.797684, -0.732042, -0.674767, -0.632910, -0.360732",\ + "-1.142024, -1.076383, -1.019108, -0.977250, -0.703048"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[64]_hldr*/ + +} /* end of pin tl_i[64] */ + +pin("tl_i[63]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.005918 ; + + /* Other user defined attributes. */ + original_pin : tl_i[63]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.634018, 5.587863, 5.557646, 5.546289, 5.559896",\ + "5.727260, 5.681105, 5.650888, 5.639531, 5.653139",\ + "5.821638, 5.775483, 5.745266, 5.733909, 5.747517",\ + "5.988543, 5.942388, 5.912171, 5.900814, 5.914422",\ + "6.282049, 6.235894, 6.205677, 6.194320, 6.207927"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.659294, 5.613139, 5.582922, 5.571565, 5.585172",\ + "5.756288, 5.710133, 5.679916, 5.668559, 5.682167",\ + "5.857348, 5.811193, 5.780976, 5.769619, 5.783226",\ + "6.036880, 5.990726, 5.960509, 5.949152, 5.962759",\ + "6.341727, 6.295572, 6.265355, 6.253998, 6.267605"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[63]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.425078, -0.367369, -0.312962, -0.274477, -0.048046",\ + "-0.523533, -0.465824, -0.411418, -0.372933, -0.146501",\ + "-0.649060, -0.591351, -0.536945, -0.498460, -0.272028",\ + "-0.863705, -0.805996, -0.751590, -0.713105, -0.486673",\ + "-1.108760, -1.042638, -0.984682, -0.942640, -0.722547"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.375262, -0.309621, -0.252346, -0.210488, 0.061380",\ + "-0.475435, -0.409794, -0.352519, -0.310661, -0.038785",\ + "-0.593964, -0.528323, -0.471048, -0.429190, -0.157265",\ + "-0.799253, -0.733611, -0.676336, -0.634479, -0.362291",\ + "-1.146486, -1.080845, -1.023570, -0.981712, -0.707386"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[63]_hldr*/ + +} /* end of pin tl_i[63] */ + +pin("tl_i[62]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.005914 ; + + /* Other user defined attributes. */ + original_pin : tl_i[62]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.028421, 4.982266, 4.952050, 4.940692, 4.954300",\ + "5.115734, 5.069579, 5.039362, 5.028005, 5.041612",\ + "5.221791, 5.175636, 5.145419, 5.134062, 5.147669",\ + "5.411152, 5.364997, 5.334780, 5.323423, 5.337030",\ + "5.716925, 5.670770, 5.640553, 5.629196, 5.642803"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.030477, 4.984322, 4.954105, 4.942748, 4.956356",\ + "5.112976, 5.066821, 5.036604, 5.025247, 5.038854",\ + "5.241773, 5.195618, 5.165401, 5.154044, 5.167651",\ + "5.477729, 5.431574, 5.401357, 5.390000, 5.403607",\ + "5.884023, 5.837868, 5.807651, 5.796294, 5.809901"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[62]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.310949, -0.245308, -0.188033, -0.146175, 0.125715",\ + "-0.408722, -0.343080, -0.285805, -0.243948, 0.028056",\ + "-0.525662, -0.460020, -0.402745, -0.360888, -0.087938",\ + "-0.729867, -0.664225, -0.606950, -0.565093, -0.287448",\ + "-1.073045, -1.007404, -0.950129, -0.908272, -0.621407"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.560733, -0.518534, -0.464760, -0.422807, -0.191354",\ + "-0.659844, -0.617645, -0.563872, -0.521919, -0.290465",\ + "-0.778888, -0.736689, -0.682928, -0.640975, -0.409521",\ + "-0.986411, -0.944213, -0.890754, -0.848801, -0.617348",\ + "-1.324035, -1.281784, -1.238624, -1.196671, -0.966234"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[62]_hldr*/ + +} /* end of pin tl_i[62] */ + +pin("tl_i[61]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.004650 ; + + /* Other user defined attributes. */ + original_pin : tl_i[61]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.050911, 5.004756, 4.974539, 4.963182, 4.976789",\ + "5.138693, 5.092538, 5.062321, 5.050964, 5.064571",\ + "5.242861, 5.196706, 5.166489, 5.155132, 5.168739",\ + "5.438320, 5.392165, 5.361948, 5.350591, 5.364199",\ + "5.753279, 5.707124, 5.676907, 5.665550, 5.679157"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.054683, 5.008528, 4.978311, 4.966954, 4.980561",\ + "5.137789, 5.091634, 5.061417, 5.050060, 5.063667",\ + "5.257940, 5.211785, 5.181569, 5.170211, 5.183819",\ + "5.493972, 5.447817, 5.417600, 5.406243, 5.419850",\ + "5.883592, 5.837437, 5.807220, 5.795863, 5.809470"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[61]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.331346, -0.288929, -0.254443, -0.214995, 0.091355",\ + "-0.415000, -0.372583, -0.338097, -0.298649, 0.007701",\ + "-0.498520, -0.456102, -0.421616, -0.382169, -0.075818",\ + "-0.644671, -0.602253, -0.567767, -0.528320, -0.221969",\ + "-0.885228, -0.842810, -0.808325, -0.768877, -0.462526"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.495414, -0.429474, -0.371779, -0.329808, -0.077326",\ + "-0.577402, -0.511461, -0.453767, -0.411796, -0.165065",\ + "-0.669896, -0.603956, -0.546261, -0.504290, -0.256735",\ + "-0.831937, -0.776516, -0.718821, -0.676851, -0.409235",\ + "-1.083366, -1.040949, -1.006463, -0.967015, -0.660665"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[61]_hldr*/ + +} /* end of pin tl_i[61] */ + +pin("tl_i[60]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.004493 ; + + /* Other user defined attributes. */ + original_pin : tl_i[60]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.075901, 5.029746, 4.999529, 4.988172, 5.001780",\ + "5.162810, 5.116655, 5.086439, 5.075081, 5.088689",\ + "5.262701, 5.216546, 5.186329, 5.174972, 5.188580",\ + "5.463603, 5.417448, 5.387231, 5.375874, 5.389482",\ + "5.887491, 5.841336, 5.811120, 5.799762, 5.813370"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.069137, 5.022982, 4.992765, 4.981408, 4.995015",\ + "5.162019, 5.115864, 5.085647, 5.074290, 5.087897",\ + "5.289857, 5.243702, 5.213485, 5.202128, 5.215735",\ + "5.547719, 5.501564, 5.471347, 5.459990, 5.473598",\ + "5.999206, 5.953051, 5.922834, 5.911477, 5.925084"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[60]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.331961, -0.289544, -0.255058, -0.215610, 0.090740",\ + "-0.416689, -0.374271, -0.339785, -0.300337, 0.006013",\ + "-0.501750, -0.459332, -0.424846, -0.385399, -0.079048",\ + "-0.650840, -0.608422, -0.573936, -0.534488, -0.228138",\ + "-0.898578, -0.856161, -0.821675, -0.782227, -0.475877"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.494855, -0.428915, -0.371220, -0.329249, -0.108704",\ + "-0.577203, -0.511263, -0.453568, -0.411597, -0.191052",\ + "-0.675131, -0.609191, -0.551496, -0.509525, -0.288980",\ + "-0.848911, -0.782971, -0.725276, -0.683305, -0.462760",\ + "-1.143176, -1.077236, -1.019541, -0.977570, -0.757025"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[60]_hldr*/ + +} /* end of pin tl_i[60] */ + +pin("tl_i[59]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.004673 ; + + /* Other user defined attributes. */ + original_pin : tl_i[59]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.018675, 4.972520, 4.942304, 4.930946, 4.944554",\ + "5.111604, 5.065449, 5.035232, 5.023875, 5.037482",\ + "5.204963, 5.158808, 5.128592, 5.117234, 5.130842",\ + "5.368355, 5.322200, 5.291983, 5.280626, 5.294233",\ + "5.654718, 5.608563, 5.578346, 5.566989, 5.580596"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.048488, 5.002333, 4.972116, 4.960759, 4.974366",\ + "5.145526, 5.099371, 5.069155, 5.057797, 5.071405",\ + "5.246175, 5.200020, 5.169804, 5.158446, 5.172054",\ + "5.423032, 5.376877, 5.346661, 5.335303, 5.348911",\ + "5.720785, 5.674630, 5.644413, 5.633056, 5.646663"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[59]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.399850, -0.333910, -0.276215, -0.234244, -0.013699",\ + "-0.490388, -0.424448, -0.366753, -0.324782, -0.104237",\ + "-0.591764, -0.525824, -0.468129, -0.426158, -0.205613",\ + "-0.771660, -0.705720, -0.648025, -0.606054, -0.385509",\ + "-1.061324, -0.995383, -0.937689, -0.895718, -0.675172"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.408211, -0.365794, -0.331308, -0.291860, 0.014490",\ + "-0.495065, -0.452648, -0.418162, -0.378714, -0.072363",\ + "-0.606791, -0.564374, -0.529888, -0.490440, -0.184090",\ + "-0.793280, -0.750863, -0.716377, -0.676929, -0.370579",\ + "-1.099378, -1.056960, -1.022474, -0.983027, -0.676676"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[59]_hldr*/ + +} /* end of pin tl_i[59] */ + +pin("tl_i[58]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.005086 ; + + /* Other user defined attributes. */ + original_pin : tl_i[58]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "4.907104, 4.860949, 4.830732, 4.819375, 4.832983",\ + "4.992526, 4.946371, 4.916154, 4.904797, 4.918404",\ + "5.070096, 5.023941, 4.993724, 4.982367, 4.995975",\ + "5.244753, 5.198598, 5.168381, 5.157024, 5.170631",\ + "5.599957, 5.553802, 5.523586, 5.512228, 5.525836"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "4.904143, 4.857988, 4.827772, 4.816414, 4.830022",\ + "4.986795, 4.940640, 4.910424, 4.899066, 4.912674",\ + "5.098862, 5.052707, 5.022491, 5.011133, 5.024741",\ + "5.327568, 5.281413, 5.251196, 5.239839, 5.253446",\ + "5.728967, 5.682812, 5.652596, 5.641238, 5.654846"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[58]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.409769, -0.343829, -0.286134, -0.244163, -0.023618",\ + "-0.498234, -0.432294, -0.374599, -0.332628, -0.112083",\ + "-0.599794, -0.533854, -0.476159, -0.434188, -0.213643",\ + "-0.781831, -0.715891, -0.658196, -0.616225, -0.395680",\ + "-1.087101, -1.021161, -0.963466, -0.921496, -0.700950"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.423427, -0.381010, -0.346524, -0.307076, -0.000726",\ + "-0.507266, -0.464848, -0.430363, -0.390915, -0.084564",\ + "-0.628312, -0.585894, -0.551408, -0.511960, -0.205610",\ + "-0.825686, -0.783269, -0.748783, -0.709335, -0.402985",\ + "-1.126419, -1.084002, -1.049516, -1.010068, -0.703718"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[58]_hldr*/ + +} /* end of pin tl_i[58] */ + +pin("tl_i[57]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.004084 ; + + /* Other user defined attributes. */ + original_pin : tl_i[57]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "4.853275, 4.807120, 4.776903, 4.765546, 4.779153",\ + "4.941780, 4.895625, 4.865408, 4.854051, 4.867658",\ + "5.043512, 4.997357, 4.967141, 4.955783, 4.969391",\ + "5.245644, 5.199489, 5.169272, 5.157915, 5.171523",\ + "5.684921, 5.638766, 5.608549, 5.597192, 5.610799"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "4.846420, 4.800265, 4.770049, 4.758691, 4.772299",\ + "4.940993, 4.894838, 4.864621, 4.853264, 4.866871",\ + "5.069371, 5.023216, 4.992999, 4.981642, 4.995249",\ + "5.318837, 5.272682, 5.242465, 5.231108, 5.244716",\ + "5.754844, 5.708689, 5.678472, 5.667115, 5.680722"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[57]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.439430, -0.373490, -0.315795, -0.273825, -0.053279",\ + "-0.519622, -0.453682, -0.395987, -0.354016, -0.133471",\ + "-0.597395, -0.531455, -0.473760, -0.431789, -0.211244",\ + "-0.729801, -0.663861, -0.606166, -0.564195, -0.343650",\ + "-0.935990, -0.870050, -0.812355, -0.770384, -0.549839"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.409353, -0.366935, -0.332449, -0.293002, 0.013349",\ + "-0.497213, -0.454795, -0.420310, -0.380862, -0.074511",\ + "-0.585629, -0.543211, -0.508725, -0.469278, -0.162927",\ + "-0.741802, -0.699385, -0.664899, -0.625451, -0.319101",\ + "-0.995469, -0.953051, -0.918565, -0.879117, -0.572767"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[57]_hldr*/ + +} /* end of pin tl_i[57] */ + +pin("tl_i[56]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.005633 ; + + /* Other user defined attributes. */ + original_pin : tl_i[56]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "4.771066, 4.724911, 4.694694, 4.683337, 4.696944",\ + "4.860967, 4.814812, 4.784595, 4.773238, 4.786846",\ + "4.953480, 4.907325, 4.877108, 4.865751, 4.879358",\ + "5.122646, 5.076491, 5.046274, 5.034917, 5.048524",\ + "5.508491, 5.462336, 5.432119, 5.420762, 5.434369"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "4.784305, 4.738150, 4.707933, 4.696576, 4.710184",\ + "4.872721, 4.826566, 4.796349, 4.784992, 4.798599",\ + "4.991727, 4.945572, 4.915355, 4.903998, 4.917605",\ + "5.265233, 5.219078, 5.188861, 5.177504, 5.191111",\ + "5.790774, 5.744619, 5.714402, 5.703045, 5.716652"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[56]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.441652, -0.375711, -0.318017, -0.276046, -0.055500",\ + "-0.524614, -0.458674, -0.400979, -0.359008, -0.138463",\ + "-0.607820, -0.541879, -0.484185, -0.442214, -0.221668",\ + "-0.753165, -0.687225, -0.629530, -0.587559, -0.367014",\ + "-0.987968, -0.922028, -0.864333, -0.822362, -0.601816"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.411476, -0.369059, -0.334573, -0.295125, 0.011225",\ + "-0.499637, -0.457219, -0.422733, -0.383285, -0.076935",\ + "-0.588334, -0.545917, -0.511431, -0.471983, -0.165633",\ + "-0.746601, -0.704183, -0.669698, -0.630250, -0.323899",\ + "-1.003694, -0.961277, -0.926791, -0.887343, -0.580993"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[56]_hldr*/ + +} /* end of pin tl_i[56] */ + +pin("tl_i[55]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.023564 ; + + /* Other user defined attributes. */ + original_pin : tl_i[55]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.825782, 5.779627, 5.749410, 5.738052, 5.751660",\ + "5.912527, 5.866372, 5.836155, 5.824798, 5.838405",\ + "6.021775, 5.975620, 5.945403, 5.934046, 5.947653",\ + "6.207016, 6.160861, 6.130644, 6.119287, 6.132894",\ + "6.502526, 6.456371, 6.426154, 6.414796, 6.428404"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.826127, 5.779972, 5.749755, 5.738398, 5.752005",\ + "5.912270, 5.866115, 5.835897, 5.824540, 5.838148",\ + "6.043355, 5.997200, 5.966982, 5.955625, 5.969233",\ + "6.273898, 6.227743, 6.197526, 6.186169, 6.199776",\ + "6.665429, 6.619274, 6.589057, 6.577700, 6.591307"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[55]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.126806, -0.084700, -0.042324, -0.000326, 0.287989",\ + "-0.211450, -0.169345, -0.128664, -0.086666, 0.203312",\ + "-0.299321, -0.257215, -0.213787, -0.171789, 0.115291",\ + "-0.454534, -0.412428, -0.355362, -0.313364, -0.040427",\ + "-0.701632, -0.635483, -0.577488, -0.535436, -0.297932"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.131974, -0.065963, -0.008166, 0.033833, 0.254201",\ + "-0.225998, -0.159987, -0.102190, -0.060192, 0.160177",\ + "-0.317206, -0.251195, -0.193398, -0.151400, 0.068969",\ + "-0.474232, -0.408221, -0.350424, -0.308425, -0.088057",\ + "-0.725398, -0.659249, -0.601254, -0.559203, -0.339176"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[55]_hldr*/ + +} /* end of pin tl_i[55] */ + +pin("tl_i[54]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.024771 ; + + /* Other user defined attributes. */ + original_pin : tl_i[54]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.671892, 5.625737, 5.595520, 5.584163, 5.597770",\ + "5.766703, 5.720548, 5.690331, 5.678973, 5.692581",\ + "5.865909, 5.819754, 5.789536, 5.778179, 5.791787",\ + "6.041008, 5.994853, 5.964636, 5.953279, 5.966886",\ + "6.340645, 6.294490, 6.264273, 6.252915, 6.266523"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.706592, 5.660437, 5.630219, 5.618862, 5.632470",\ + "5.804386, 5.758231, 5.728014, 5.716657, 5.730264",\ + "5.910204, 5.864049, 5.833832, 5.822474, 5.836082",\ + "6.089930, 6.043775, 6.013557, 6.002200, 6.015808",\ + "6.385911, 6.339756, 6.309539, 6.298182, 6.311790"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[54]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.126806, -0.084700, -0.042324, -0.000326, 0.287989",\ + "-0.211450, -0.169345, -0.128664, -0.086666, 0.203312",\ + "-0.299321, -0.257215, -0.213787, -0.171789, 0.115291",\ + "-0.454534, -0.412428, -0.355362, -0.313364, -0.040427",\ + "-0.701632, -0.635483, -0.577488, -0.535436, -0.297932"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.131974, -0.065963, -0.008166, 0.033833, 0.254201",\ + "-0.225998, -0.159987, -0.102190, -0.060192, 0.160177",\ + "-0.317206, -0.251195, -0.193398, -0.151400, 0.068969",\ + "-0.474232, -0.408221, -0.350424, -0.308425, -0.088057",\ + "-0.725398, -0.659249, -0.601254, -0.559203, -0.339176"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[54]_hldr*/ + +} /* end of pin tl_i[54] */ + +pin("tl_i[53]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.025984 ; + + /* Other user defined attributes. */ + original_pin : tl_i[53]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.405560, 5.359406, 5.329188, 5.317831, 5.331439",\ + "5.489668, 5.443513, 5.413296, 5.401938, 5.415546",\ + "5.570677, 5.524522, 5.494305, 5.482947, 5.496555",\ + "5.711991, 5.665836, 5.635619, 5.624262, 5.637869",\ + "5.953867, 5.907712, 5.877495, 5.866138, 5.879745"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.390637, 5.344482, 5.314265, 5.302907, 5.316515",\ + "5.472354, 5.426199, 5.395982, 5.384624, 5.398232",\ + "5.578566, 5.532411, 5.502193, 5.490836, 5.504444",\ + "5.766796, 5.720641, 5.690423, 5.679066, 5.692674",\ + "6.084168, 6.038013, 6.007796, 5.996439, 6.010046"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[53]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.126806, -0.084700, -0.042324, -0.000326, 0.287989",\ + "-0.211450, -0.169345, -0.128664, -0.086666, 0.203312",\ + "-0.299321, -0.257215, -0.213787, -0.171789, 0.115291",\ + "-0.454534, -0.412428, -0.355362, -0.313364, -0.040427",\ + "-0.701632, -0.635483, -0.577488, -0.535436, -0.297932"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.131974, -0.065963, -0.008166, 0.033833, 0.254201",\ + "-0.225998, -0.159987, -0.102190, -0.060192, 0.160177",\ + "-0.317206, -0.251195, -0.193398, -0.151400, 0.068969",\ + "-0.474232, -0.408221, -0.350424, -0.308425, -0.088057",\ + "-0.725398, -0.659249, -0.601254, -0.559203, -0.339176"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[53]_hldr*/ + +} /* end of pin tl_i[53] */ + +pin("tl_i[52]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.023928 ; + + /* Other user defined attributes. */ + original_pin : tl_i[52]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.851366, 5.805211, 5.774994, 5.763637, 5.777244",\ + "5.940992, 5.894837, 5.864620, 5.853263, 5.866870",\ + "6.046589, 6.000434, 5.970217, 5.958859, 5.972467",\ + "6.242908, 6.196754, 6.166536, 6.155179, 6.168787",\ + "6.655770, 6.609615, 6.579398, 6.568040, 6.581648"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.844427, 5.798272, 5.768054, 5.756697, 5.770305",\ + "5.940210, 5.894055, 5.863838, 5.852481, 5.866088",\ + "6.071230, 6.025075, 5.994858, 5.983501, 5.997108",\ + "6.314948, 6.268793, 6.238575, 6.227218, 6.240826",\ + "6.731011, 6.684856, 6.654639, 6.643281, 6.656889"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[52]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.126806, -0.084700, -0.042324, -0.000326, 0.287989",\ + "-0.211450, -0.169345, -0.128664, -0.086666, 0.203312",\ + "-0.299321, -0.257215, -0.213787, -0.171789, 0.115291",\ + "-0.454534, -0.412428, -0.355362, -0.313364, -0.040427",\ + "-0.701632, -0.635483, -0.577488, -0.535436, -0.297932"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.131974, -0.065963, -0.008166, 0.033833, 0.254201",\ + "-0.225998, -0.159987, -0.102190, -0.060192, 0.160177",\ + "-0.317206, -0.251195, -0.193398, -0.151400, 0.068969",\ + "-0.474232, -0.408221, -0.350424, -0.308425, -0.088057",\ + "-0.725398, -0.659249, -0.601254, -0.559203, -0.339176"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[52]_hldr*/ + +} /* end of pin tl_i[52] */ + +pin("tl_i[51]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.024747 ; + + /* Other user defined attributes. */ + original_pin : tl_i[51]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.766789, 5.720634, 5.690417, 5.679060, 5.692667",\ + "5.856632, 5.810477, 5.780260, 5.768903, 5.782510",\ + "5.949137, 5.902982, 5.872765, 5.861408, 5.875015",\ + "6.115034, 6.068879, 6.038662, 6.027305, 6.040912",\ + "6.488516, 6.442361, 6.412144, 6.400786, 6.414394"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.777621, 5.731466, 5.701249, 5.689892, 5.703499",\ + "5.868374, 5.822219, 5.792002, 5.780644, 5.794252",\ + "5.987092, 5.940937, 5.910720, 5.899363, 5.912970",\ + "6.219129, 6.172974, 6.142756, 6.131399, 6.145007",\ + "6.630526, 6.584371, 6.554153, 6.542796, 6.556404"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[51]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.126806, -0.084700, -0.042324, -0.000326, 0.287989",\ + "-0.211450, -0.169345, -0.128664, -0.086666, 0.203312",\ + "-0.299321, -0.257215, -0.213787, -0.171789, 0.115291",\ + "-0.454534, -0.408918, -0.350984, -0.308948, -0.040427",\ + "-0.633444, -0.567337, -0.509403, -0.467367, -0.247237"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.131974, -0.065963, -0.008166, 0.033833, 0.254201",\ + "-0.225998, -0.159987, -0.102190, -0.060192, 0.160177",\ + "-0.317206, -0.251195, -0.193398, -0.151400, 0.068969",\ + "-0.474232, -0.408221, -0.350424, -0.308425, -0.088057",\ + "-0.660870, -0.594763, -0.536828, -0.494793, -0.274662"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[51]_hldr*/ + +} /* end of pin tl_i[51] */ + +pin("tl_i[50]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.024706 ; + + /* Other user defined attributes. */ + original_pin : tl_i[50]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.432938, 5.386783, 5.356565, 5.345208, 5.358816",\ + "5.522908, 5.476753, 5.446536, 5.435179, 5.448786",\ + "5.615422, 5.569267, 5.539050, 5.527693, 5.541300",\ + "5.781178, 5.735023, 5.704806, 5.693449, 5.707057",\ + "6.151173, 6.105018, 6.074801, 6.063444, 6.077051"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.443795, 5.397640, 5.367423, 5.356066, 5.369673",\ + "5.534675, 5.488520, 5.458302, 5.446945, 5.460553",\ + "5.653760, 5.607605, 5.577388, 5.566031, 5.579638",\ + "5.885449, 5.839294, 5.809077, 5.797719, 5.811327",\ + "6.297242, 6.251087, 6.220870, 6.209512, 6.223120"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[50]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.126806, -0.084700, -0.042324, -0.000326, 0.287989",\ + "-0.211450, -0.169345, -0.128664, -0.086666, 0.203312",\ + "-0.299321, -0.257215, -0.213787, -0.171789, 0.115291",\ + "-0.454534, -0.408918, -0.350984, -0.308948, -0.040427",\ + "-0.633444, -0.567337, -0.509403, -0.467367, -0.247237"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.131974, -0.065963, -0.008166, 0.033833, 0.254201",\ + "-0.225998, -0.159987, -0.102190, -0.060192, 0.160177",\ + "-0.317206, -0.251195, -0.193398, -0.151400, 0.068969",\ + "-0.474232, -0.408221, -0.350424, -0.308425, -0.088057",\ + "-0.660870, -0.594763, -0.536828, -0.494793, -0.274662"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[50]_hldr*/ + +} /* end of pin tl_i[50] */ + +pin("tl_i[49]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.014215 ; + + /* Other user defined attributes. */ + original_pin : tl_i[49]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.612003, 5.565848, 5.535631, 5.524274, 5.537881",\ + "5.697372, 5.651217, 5.621000, 5.609643, 5.623250",\ + "5.774767, 5.728612, 5.698395, 5.687037, 5.700645",\ + "5.943757, 5.897602, 5.867384, 5.856027, 5.869635",\ + "6.302785, 6.256630, 6.226413, 6.215055, 6.228663"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.608959, 5.562804, 5.532587, 5.521230, 5.534837",\ + "5.691543, 5.645388, 5.615170, 5.603813, 5.617421",\ + "5.803527, 5.757372, 5.727155, 5.715797, 5.729405",\ + "6.034389, 5.988234, 5.958016, 5.946659, 5.960267",\ + "6.439312, 6.393157, 6.362939, 6.351582, 6.365190"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[49]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.134918, -0.092500, -0.042324, -0.000326, 0.287989",\ + "-0.219595, -0.177177, -0.128664, -0.086666, 0.203312",\ + "-0.307616, -0.265198, -0.213787, -0.171789, 0.115291",\ + "-0.454448, -0.412253, -0.355362, -0.313364, -0.040427",\ + "-0.692896, -0.635483, -0.577488, -0.535436, -0.297932"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.131974, -0.065963, -0.008166, 0.033833, 0.254201",\ + "-0.225998, -0.159987, -0.102190, -0.060192, 0.160177",\ + "-0.317206, -0.251195, -0.193398, -0.151400, 0.068969",\ + "-0.474232, -0.408221, -0.350424, -0.308425, -0.088057",\ + "-0.725398, -0.659249, -0.601254, -0.559203, -0.339176"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[49]_hldr*/ + +} /* end of pin tl_i[49] */ + +pin("tl_i[48]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.015924 ; + + /* Other user defined attributes. */ + original_pin : tl_i[48]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.342521, 5.296366, 5.266149, 5.254791, 5.268399",\ + "5.430000, 5.383845, 5.353628, 5.342271, 5.355878",\ + "5.517300, 5.471145, 5.440928, 5.429570, 5.443178",\ + "5.691890, 5.645735, 5.615518, 5.604160, 5.617768",\ + "6.098689, 6.052534, 6.022317, 6.010960, 6.024567"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.337069, 5.290914, 5.260696, 5.249339, 5.262947",\ + "5.426027, 5.379872, 5.349655, 5.338298, 5.351905",\ + "5.541069, 5.494914, 5.464697, 5.453340, 5.466947",\ + "5.778956, 5.732801, 5.702584, 5.691227, 5.704834",\ + "6.214471, 6.168316, 6.138099, 6.126742, 6.140349"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[48]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.095389, -0.053327, -0.019395, 0.003631, 0.287989",\ + "-0.178535, -0.136472, -0.102541, -0.079514, 0.203312",\ + "-0.262969, -0.220876, -0.186811, -0.163726, 0.115291",\ + "-0.399970, -0.357878, -0.323812, -0.300727, -0.040427",\ + "-0.613644, -0.571552, -0.537486, -0.514401, -0.297932"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.127054, -0.062200, -0.008166, 0.033833, 0.254201",\ + "-0.207506, -0.142652, -0.088847, -0.050549, 0.160177",\ + "-0.300279, -0.235482, -0.181379, -0.142982, 0.068969",\ + "-0.445930, -0.381133, -0.327029, -0.288632, -0.088057",\ + "-0.677823, -0.613026, -0.558922, -0.520525, -0.325394"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[48]_hldr*/ + +} /* end of pin tl_i[48] */ + +pin("tl_i[47]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.015093 ; + + /* Other user defined attributes. */ + original_pin : tl_i[47]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.720613, 5.674458, 5.644240, 5.632883, 5.646491",\ + "5.808302, 5.762147, 5.731930, 5.720572, 5.734180",\ + "5.909732, 5.863577, 5.833360, 5.822003, 5.835610",\ + "6.090167, 6.044012, 6.013794, 6.002437, 6.016045",\ + "6.375024, 6.328869, 6.298652, 6.287294, 6.300902"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.723861, 5.677706, 5.647489, 5.636132, 5.649739",\ + "5.806833, 5.760678, 5.730461, 5.719103, 5.732711",\ + "5.923954, 5.877799, 5.847582, 5.836225, 5.849832",\ + "6.142916, 6.096761, 6.066544, 6.055186, 6.068794",\ + "6.505251, 6.459096, 6.428879, 6.417521, 6.431129"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[47]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.126806, -0.084700, -0.042324, -0.000326, 0.287989",\ + "-0.211450, -0.169345, -0.128664, -0.086666, 0.203312",\ + "-0.299321, -0.257215, -0.213787, -0.171789, 0.115291",\ + "-0.454448, -0.412253, -0.355362, -0.313364, -0.040427",\ + "-0.692896, -0.635483, -0.577488, -0.535436, -0.297932"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.131974, -0.065963, -0.008166, 0.033833, 0.254201",\ + "-0.225998, -0.159987, -0.102190, -0.060192, 0.160177",\ + "-0.317206, -0.251195, -0.193398, -0.151400, 0.068969",\ + "-0.474232, -0.408221, -0.350424, -0.308425, -0.088057",\ + "-0.725398, -0.659249, -0.601254, -0.559203, -0.339176"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[47]_hldr*/ + +} /* end of pin tl_i[47] */ + +pin("tl_i[46]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.015694 ; + + /* Other user defined attributes. */ + original_pin : tl_i[46]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.747210, 5.701055, 5.670837, 5.659480, 5.673088",\ + "5.834549, 5.788394, 5.758177, 5.746819, 5.760427",\ + "5.931758, 5.885603, 5.855386, 5.844028, 5.857636",\ + "6.119594, 6.073439, 6.043221, 6.031864, 6.045472",\ + "6.512118, 6.465963, 6.435746, 6.424389, 6.437996"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.740419, 5.694264, 5.664047, 5.652689, 5.666297",\ + "5.833758, 5.787603, 5.757386, 5.746029, 5.759636",\ + "5.958529, 5.912374, 5.882157, 5.870800, 5.884408",\ + "6.201867, 6.155712, 6.125495, 6.114138, 6.127745",\ + "6.619649, 6.573494, 6.543277, 6.531919, 6.545527"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[46]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.126806, -0.084700, -0.042324, -0.000326, 0.287989",\ + "-0.211450, -0.169345, -0.128664, -0.086666, 0.203312",\ + "-0.299321, -0.257215, -0.213787, -0.171789, 0.115291",\ + "-0.454448, -0.412253, -0.355362, -0.313364, -0.040427",\ + "-0.692896, -0.635483, -0.577488, -0.535436, -0.297932"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.131974, -0.065963, -0.008166, 0.033833, 0.254201",\ + "-0.225998, -0.159987, -0.102190, -0.060192, 0.160177",\ + "-0.317206, -0.251195, -0.193398, -0.151400, 0.068969",\ + "-0.474232, -0.408221, -0.350424, -0.308425, -0.088057",\ + "-0.725398, -0.659249, -0.601254, -0.559203, -0.339176"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[46]_hldr*/ + +} /* end of pin tl_i[46] */ + +pin("tl_i[45]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.017466 ; + + /* Other user defined attributes. */ + original_pin : tl_i[45]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.112432, 5.066278, 5.036060, 5.024703, 5.038311",\ + "5.197829, 5.151674, 5.121457, 5.110100, 5.123707",\ + "5.275316, 5.229161, 5.198944, 5.187587, 5.201194",\ + "5.419477, 5.373322, 5.343104, 5.331747, 5.345355",\ + "5.777201, 5.731046, 5.700829, 5.689471, 5.703079"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.109432, 5.063277, 5.033060, 5.021703, 5.035310",\ + "5.192052, 5.145897, 5.115680, 5.104322, 5.117930",\ + "5.304079, 5.257924, 5.227707, 5.216350, 5.229957",\ + "5.534409, 5.488254, 5.458036, 5.446679, 5.460287",\ + "5.938303, 5.892148, 5.861931, 5.850574, 5.864181"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[45]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.134918, -0.092500, -0.042324, -0.000326, 0.287989",\ + "-0.219595, -0.177177, -0.128664, -0.086666, 0.203312",\ + "-0.307616, -0.265198, -0.213787, -0.171789, 0.115291",\ + "-0.454448, -0.408918, -0.350984, -0.308948, -0.040427",\ + "-0.633444, -0.567337, -0.509403, -0.467367, -0.247237"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.131974, -0.065963, -0.008166, 0.033833, 0.254201",\ + "-0.225998, -0.159987, -0.102190, -0.060192, 0.160177",\ + "-0.317206, -0.251195, -0.193398, -0.151400, 0.068969",\ + "-0.474232, -0.408221, -0.350424, -0.308425, -0.088057",\ + "-0.660870, -0.594763, -0.536828, -0.494793, -0.274662"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[45]_hldr*/ + +} /* end of pin tl_i[45] */ + +pin("tl_i[44]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.016255 ; + + /* Other user defined attributes. */ + original_pin : tl_i[44]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.787257, 5.741102, 5.710885, 5.699527, 5.713135",\ + "5.887364, 5.841209, 5.810992, 5.799634, 5.813242",\ + "6.003266, 5.957111, 5.926894, 5.915536, 5.929144",\ + "6.212816, 6.166661, 6.136444, 6.125086, 6.138694",\ + "6.574124, 6.527969, 6.497752, 6.486395, 6.500002"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.833889, 5.787734, 5.757517, 5.746160, 5.759767",\ + "5.932858, 5.886703, 5.856485, 5.845128, 5.858736",\ + "6.056724, 6.010569, 5.980351, 5.968994, 5.982602",\ + "6.267234, 6.221079, 6.190862, 6.179505, 6.193112",\ + "6.625524, 6.579369, 6.549152, 6.537795, 6.551402"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[44]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.126806, -0.084700, -0.042324, -0.000326, 0.287989",\ + "-0.211450, -0.169345, -0.128664, -0.086666, 0.203312",\ + "-0.299321, -0.257215, -0.213787, -0.171789, 0.115291",\ + "-0.454448, -0.408918, -0.350984, -0.308948, -0.040427",\ + "-0.633444, -0.567337, -0.509403, -0.467367, -0.247237"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.131974, -0.065963, -0.008166, 0.033833, 0.254201",\ + "-0.225998, -0.159987, -0.102190, -0.060192, 0.160177",\ + "-0.317206, -0.251195, -0.193398, -0.151400, 0.068969",\ + "-0.474232, -0.408221, -0.350424, -0.308425, -0.088057",\ + "-0.660870, -0.594763, -0.536828, -0.494793, -0.274662"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[44]_hldr*/ + +} /* end of pin tl_i[44] */ + +pin("tl_i[43]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.018203 ; + + /* Other user defined attributes. */ + original_pin : tl_i[43]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.371556, 5.325401, 5.295184, 5.283827, 5.297434",\ + "5.461463, 5.415308, 5.385091, 5.373734, 5.387341",\ + "5.553976, 5.507821, 5.477604, 5.466247, 5.479854",\ + "5.719817, 5.673662, 5.643445, 5.632088, 5.645695",\ + "6.097318, 6.051163, 6.020946, 6.009588, 6.023196"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.382551, 5.336396, 5.306179, 5.294822, 5.308429",\ + "5.473218, 5.427063, 5.396846, 5.385489, 5.399096",\ + "5.592251, 5.546096, 5.515879, 5.504522, 5.518129",\ + "5.824078, 5.777923, 5.747705, 5.736348, 5.749956",\ + "6.235509, 6.189354, 6.159137, 6.147780, 6.161387"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[43]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.103114, -0.028963, 0.033559, 0.078022, 0.304626",\ + "-0.178370, -0.104212, -0.041630, 0.002858, 0.229475",\ + "-0.246264, -0.172106, -0.109525, -0.065037, 0.161580",\ + "-0.355098, -0.280940, -0.218359, -0.173870, 0.052747",\ + "-0.519769, -0.445611, -0.383030, -0.338542, -0.111925"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.112706, -0.065963, -0.008166, 0.033833, 0.418070",\ + "-0.200783, -0.156045, -0.102190, -0.060192, 0.330579",\ + "-0.289959, -0.245221, -0.193398, -0.151400, 0.241403",\ + "-0.449366, -0.404628, -0.350424, -0.308425, 0.081996",\ + "-0.660870, -0.594763, -0.536828, -0.494793, -0.185073"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[43]_hldr*/ + +} /* end of pin tl_i[43] */ + +pin("tl_i[42]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.019122 ; + + /* Other user defined attributes. */ + original_pin : tl_i[42]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.198272, 5.152117, 5.121900, 5.110542, 5.124150",\ + "5.294228, 5.248073, 5.217855, 5.206498, 5.220106",\ + "5.404464, 5.358309, 5.328092, 5.316734, 5.330342",\ + "5.594985, 5.548830, 5.518613, 5.507256, 5.520863",\ + "5.917032, 5.870877, 5.840660, 5.829302, 5.842910"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.190427, 5.144272, 5.114055, 5.102697, 5.116305",\ + "5.291961, 5.245806, 5.215589, 5.204232, 5.217839",\ + "5.417454, 5.371299, 5.341082, 5.329724, 5.343332",\ + "5.634560, 5.588405, 5.558187, 5.546830, 5.560438",\ + "6.000741, 5.954587, 5.924369, 5.913012, 5.926620"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[42]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.103114, -0.028963, 0.033559, 0.078022, 0.304626",\ + "-0.178370, -0.104212, -0.041630, 0.002858, 0.229475",\ + "-0.246264, -0.172106, -0.109525, -0.065037, 0.161580",\ + "-0.355098, -0.280940, -0.218359, -0.173870, 0.052747",\ + "-0.519769, -0.445611, -0.383030, -0.338542, -0.111925"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.112706, -0.065963, -0.008166, 0.033833, 0.418070",\ + "-0.200783, -0.156045, -0.102190, -0.060192, 0.330579",\ + "-0.289959, -0.245221, -0.193398, -0.151400, 0.241403",\ + "-0.449366, -0.404628, -0.350424, -0.308425, 0.081996",\ + "-0.660870, -0.594763, -0.536828, -0.494793, -0.185073"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[42]_hldr*/ + +} /* end of pin tl_i[42] */ + +pin("tl_i[41]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.022202 ; + + /* Other user defined attributes. */ + original_pin : tl_i[41]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.148859, 5.102704, 5.072487, 5.061130, 5.074737",\ + "5.233216, 5.187061, 5.156844, 5.145487, 5.159094",\ + "5.314116, 5.267961, 5.237743, 5.226386, 5.239994",\ + "5.455597, 5.409442, 5.379225, 5.367867, 5.381475",\ + "5.695938, 5.649783, 5.619565, 5.608208, 5.621816"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.134229, 5.088074, 5.057857, 5.046499, 5.060107",\ + "5.215816, 5.169661, 5.139443, 5.128086, 5.141694",\ + "5.322016, 5.275861, 5.245644, 5.234286, 5.247894",\ + "5.510269, 5.464114, 5.433897, 5.422539, 5.436147",\ + "5.825513, 5.779358, 5.749141, 5.737783, 5.751391"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[41]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.103114, -0.028963, 0.033559, 0.078022, 0.304626",\ + "-0.178370, -0.104212, -0.041630, 0.002858, 0.229475",\ + "-0.246264, -0.172106, -0.109525, -0.065037, 0.161580",\ + "-0.355098, -0.280940, -0.218359, -0.173870, 0.052747",\ + "-0.519769, -0.445611, -0.383030, -0.338542, -0.111925"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.112706, -0.065963, -0.008166, 0.033833, 0.418070",\ + "-0.200783, -0.156045, -0.102190, -0.060192, 0.330579",\ + "-0.289959, -0.245221, -0.193398, -0.151400, 0.241403",\ + "-0.449366, -0.404628, -0.350424, -0.308425, 0.081996",\ + "-0.660870, -0.594763, -0.536828, -0.494793, -0.185073"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[41]_hldr*/ + +} /* end of pin tl_i[41] */ + +pin("tl_i[40]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.021765 ; + + /* Other user defined attributes. */ + original_pin : tl_i[40]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.554589, 5.508434, 5.478217, 5.466860, 5.480467",\ + "5.642064, 5.595909, 5.565692, 5.554335, 5.567942",\ + "5.729364, 5.683209, 5.652992, 5.641635, 5.655242",\ + "5.918046, 5.871891, 5.841674, 5.830317, 5.843924",\ + "6.322921, 6.276766, 6.246549, 6.235191, 6.248799"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.549117, 5.502962, 5.472744, 5.461387, 5.474995",\ + "5.638085, 5.591930, 5.561713, 5.550356, 5.563963",\ + "5.753121, 5.706966, 5.676749, 5.665391, 5.678999",\ + "5.991310, 5.945155, 5.914938, 5.903581, 5.917188",\ + "6.427492, 6.381337, 6.351120, 6.339763, 6.353370"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[40]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.103114, -0.028963, 0.033559, 0.078022, 0.304626",\ + "-0.178370, -0.104212, -0.041630, 0.002858, 0.229475",\ + "-0.246264, -0.172106, -0.109525, -0.065037, 0.161580",\ + "-0.355098, -0.280940, -0.218359, -0.173870, 0.052747",\ + "-0.519769, -0.445611, -0.383030, -0.338542, -0.111925"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.112706, -0.065963, -0.008166, 0.033833, 0.418070",\ + "-0.200783, -0.156045, -0.102190, -0.060192, 0.330579",\ + "-0.289959, -0.245221, -0.193398, -0.151400, 0.241403",\ + "-0.449366, -0.404628, -0.350424, -0.308425, 0.081996",\ + "-0.716436, -0.659249, -0.601254, -0.559203, -0.185073"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[40]_hldr*/ + +} /* end of pin tl_i[40] */ + +pin("tl_i[39]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.017624 ; + + /* Other user defined attributes. */ + original_pin : tl_i[39]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "4.869242, 4.823087, 4.792870, 4.781513, 4.795120",\ + "4.959149, 4.912994, 4.882777, 4.871420, 4.885027",\ + "5.051662, 5.005507, 4.975290, 4.963933, 4.977540",\ + "5.217504, 5.171349, 5.141131, 5.129774, 5.143382",\ + "5.606756, 5.560601, 5.530384, 5.519027, 5.532634"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "4.880238, 4.834083, 4.803865, 4.792508, 4.806116",\ + "4.970903, 4.924748, 4.894531, 4.883174, 4.896781",\ + "5.089937, 5.043782, 5.013565, 5.002208, 5.015815",\ + "5.321764, 5.275609, 5.245392, 5.234035, 5.247642",\ + "5.733193, 5.687038, 5.656821, 5.645464, 5.659071"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[39]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.103114, -0.028963, 0.033559, 0.078022, 0.304626",\ + "-0.178370, -0.104212, -0.041630, 0.002858, 0.229475",\ + "-0.246264, -0.172106, -0.109525, -0.065037, 0.161580",\ + "-0.355098, -0.280940, -0.218359, -0.173870, 0.052747",\ + "-0.519769, -0.445611, -0.383030, -0.338542, -0.111925"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.112706, -0.065963, -0.008166, 0.033833, 0.418070",\ + "-0.200783, -0.156045, -0.102190, -0.060192, 0.330579",\ + "-0.289959, -0.245221, -0.193398, -0.151400, 0.241403",\ + "-0.449366, -0.404628, -0.350424, -0.308425, 0.081996",\ + "-0.660870, -0.594763, -0.536828, -0.494793, -0.185073"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[39]_hldr*/ + +} /* end of pin tl_i[39] */ + +pin("tl_i[38]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.020036 ; + + /* Other user defined attributes. */ + original_pin : tl_i[38]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.623479, 5.577324, 5.547107, 5.535749, 5.549357",\ + "5.708911, 5.662756, 5.632539, 5.621181, 5.634789",\ + "5.786510, 5.740355, 5.710137, 5.698780, 5.712388",\ + "5.952927, 5.906772, 5.876554, 5.865197, 5.878805",\ + "6.305354, 6.259199, 6.228982, 6.217625, 6.231232"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.620534, 5.574379, 5.544162, 5.532805, 5.546412",\ + "5.703200, 5.657045, 5.626828, 5.615471, 5.629078",\ + "5.815276, 5.769121, 5.738904, 5.727547, 5.741154",\ + "6.045676, 5.999521, 5.969304, 5.957947, 5.971554",\ + "6.448150, 6.401995, 6.371778, 6.360420, 6.374028"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[38]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.103114, -0.028963, 0.033559, 0.078022, 0.304626",\ + "-0.178370, -0.104212, -0.041630, 0.002858, 0.229475",\ + "-0.246264, -0.172106, -0.109525, -0.065037, 0.161580",\ + "-0.355098, -0.280940, -0.218359, -0.173870, 0.052747",\ + "-0.519769, -0.445611, -0.383030, -0.338542, -0.111925"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.112706, -0.065963, -0.008166, 0.033833, 0.418070",\ + "-0.200783, -0.156045, -0.102190, -0.060192, 0.330579",\ + "-0.289959, -0.245221, -0.193398, -0.151400, 0.241403",\ + "-0.449366, -0.404628, -0.350424, -0.308425, 0.081996",\ + "-0.660870, -0.594763, -0.536828, -0.494793, -0.185073"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[38]_hldr*/ + +} /* end of pin tl_i[38] */ + +pin("tl_i[37]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.020927 ; + + /* Other user defined attributes. */ + original_pin : tl_i[37]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.583619, 5.537464, 5.507247, 5.495890, 5.509497",\ + "5.673532, 5.627377, 5.597160, 5.585803, 5.599410",\ + "5.766046, 5.719891, 5.689674, 5.678317, 5.691924",\ + "5.938797, 5.892642, 5.862425, 5.851068, 5.864676",\ + "6.323754, 6.277599, 6.247382, 6.236025, 6.249632"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.594629, 5.548474, 5.518257, 5.506900, 5.520507",\ + "5.685287, 5.639132, 5.608915, 5.597558, 5.611166",\ + "5.804349, 5.758194, 5.727977, 5.716619, 5.730227",\ + "6.036157, 5.990002, 5.959785, 5.948428, 5.962035",\ + "6.447590, 6.401435, 6.371218, 6.359861, 6.373468"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[37]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.103114, -0.028963, 0.033559, 0.078022, 0.304626",\ + "-0.178370, -0.104212, -0.041630, 0.002858, 0.229475",\ + "-0.246264, -0.172106, -0.109525, -0.065037, 0.161580",\ + "-0.355098, -0.280940, -0.218359, -0.173870, 0.052747",\ + "-0.519769, -0.445611, -0.383030, -0.338542, -0.111925"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.112706, -0.065963, -0.008166, 0.033833, 0.418070",\ + "-0.200783, -0.156045, -0.102190, -0.060192, 0.330579",\ + "-0.289959, -0.245221, -0.193398, -0.151400, 0.241403",\ + "-0.449366, -0.404628, -0.350424, -0.308425, 0.081996",\ + "-0.660870, -0.594763, -0.536828, -0.494793, -0.185073"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[37]_hldr*/ + +} /* end of pin tl_i[37] */ + +pin("tl_i[36]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.022013 ; + + /* Other user defined attributes. */ + original_pin : tl_i[36]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.660564, 5.614409, 5.584192, 5.572835, 5.586442",\ + "5.744962, 5.698807, 5.668590, 5.657232, 5.670840",\ + "5.825815, 5.779660, 5.749443, 5.738086, 5.751693",\ + "5.968822, 5.922667, 5.892449, 5.881092, 5.894700",\ + "6.227637, 6.181482, 6.151265, 6.139908, 6.153515"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.645984, 5.599829, 5.569612, 5.558254, 5.571862",\ + "5.727538, 5.681383, 5.651165, 5.639808, 5.653416",\ + "5.833738, 5.787583, 5.757366, 5.746009, 5.759616",\ + "6.023547, 5.977392, 5.947175, 5.935818, 5.949425",\ + "6.386638, 6.340483, 6.310266, 6.298908, 6.312516"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[36]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.103114, -0.028963, 0.033559, 0.078022, 0.304626",\ + "-0.178370, -0.104212, -0.041630, 0.002858, 0.229475",\ + "-0.246264, -0.172106, -0.109525, -0.065037, 0.161580",\ + "-0.355098, -0.280940, -0.218359, -0.173870, 0.052747",\ + "-0.519769, -0.445611, -0.383030, -0.338542, -0.111925"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.112706, -0.065963, -0.008166, 0.033833, 0.418070",\ + "-0.200783, -0.156045, -0.102190, -0.060192, 0.330579",\ + "-0.289959, -0.245221, -0.193398, -0.151400, 0.241403",\ + "-0.449366, -0.404628, -0.350424, -0.308425, 0.081996",\ + "-0.660870, -0.594763, -0.536828, -0.494793, -0.185073"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[36]_hldr*/ + +} /* end of pin tl_i[36] */ + +pin("tl_i[35]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.023123 ; + + /* Other user defined attributes. */ + original_pin : tl_i[35]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.051503, 5.005348, 4.975131, 4.963773, 4.977381",\ + "5.138166, 5.092011, 5.061794, 5.050437, 5.064044",\ + "5.251214, 5.205059, 5.174842, 5.163485, 5.177092",\ + "5.450928, 5.404773, 5.374556, 5.363198, 5.376806",\ + "5.780051, 5.733896, 5.703679, 5.692322, 5.705929"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.051780, 5.005625, 4.975408, 4.964050, 4.977658",\ + "5.133488, 5.087333, 5.057116, 5.045758, 5.059366",\ + "5.260558, 5.214403, 5.184186, 5.172829, 5.186436",\ + "5.487176, 5.441021, 5.410804, 5.399446, 5.413054",\ + "5.889712, 5.843557, 5.813340, 5.801982, 5.815590"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[35]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.126806, -0.060002, 0.003106, 0.047821, 0.287989",\ + "-0.211450, -0.142185, -0.078960, -0.034194, 0.203312",\ + "-0.299321, -0.228917, -0.165692, -0.120927, 0.115291",\ + "-0.454448, -0.386390, -0.323164, -0.278399, -0.040427",\ + "-0.633444, -0.567337, -0.509403, -0.467367, -0.247237"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.117131, -0.065963, -0.008166, 0.033833, 0.413435",\ + "-0.206406, -0.159987, -0.102190, -0.060192, 0.324160",\ + "-0.303102, -0.251195, -0.193398, -0.151400, 0.227464",\ + "-0.474232, -0.408221, -0.350424, -0.308425, 0.053358",\ + "-0.660870, -0.594763, -0.536828, -0.494793, -0.246898"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[35]_hldr*/ + +} /* end of pin tl_i[35] */ + +pin("tl_i[34]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.023475 ; + + /* Other user defined attributes. */ + original_pin : tl_i[34]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.659205, 5.613050, 5.582833, 5.571476, 5.585083",\ + "5.746680, 5.700525, 5.670308, 5.658950, 5.672558",\ + "5.833981, 5.787826, 5.757608, 5.746251, 5.759859",\ + "6.007267, 5.961112, 5.930894, 5.919537, 5.933145",\ + "6.412266, 6.366111, 6.335894, 6.324536, 6.338144"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.653732, 5.607577, 5.577360, 5.566003, 5.579610",\ + "5.742702, 5.696547, 5.666329, 5.654972, 5.668580",\ + "5.857737, 5.811582, 5.781364, 5.770007, 5.783615",\ + "6.095998, 6.049843, 6.019626, 6.008269, 6.021876",\ + "6.532254, 6.486099, 6.455882, 6.444524, 6.458132"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[34]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.126806, -0.060002, 0.003106, 0.047821, 0.287989",\ + "-0.211450, -0.142185, -0.078960, -0.034194, 0.203312",\ + "-0.299321, -0.228917, -0.165692, -0.120927, 0.115291",\ + "-0.454448, -0.386390, -0.323164, -0.278399, -0.040427",\ + "-0.633444, -0.567337, -0.509403, -0.467367, -0.247237"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.117131, -0.065963, -0.008166, 0.033833, 0.413435",\ + "-0.206406, -0.159987, -0.102190, -0.060192, 0.324160",\ + "-0.303102, -0.251195, -0.193398, -0.151400, 0.227464",\ + "-0.474232, -0.408221, -0.350424, -0.308425, 0.053358",\ + "-0.660870, -0.594763, -0.536828, -0.494793, -0.246898"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[34]_hldr*/ + +} /* end of pin tl_i[34] */ + +pin("tl_i[33]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.026365 ; + + /* Other user defined attributes. */ + original_pin : tl_i[33]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.415846, 5.369691, 5.339474, 5.328116, 5.341724",\ + "5.492352, 5.446198, 5.415980, 5.404623, 5.418231",\ + "5.597322, 5.551167, 5.520950, 5.509593, 5.523201",\ + "5.785541, 5.739386, 5.709168, 5.697811, 5.711419",\ + "6.094803, 6.048648, 6.018431, 6.007074, 6.020681"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.396865, 5.350710, 5.320493, 5.309135, 5.322743",\ + "5.469503, 5.423348, 5.393131, 5.381774, 5.395381",\ + "5.589046, 5.542892, 5.512674, 5.501317, 5.514925",\ + "5.798637, 5.752482, 5.722265, 5.710908, 5.724515",\ + "6.156535, 6.110380, 6.080163, 6.068806, 6.082413"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[33]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.103109, -0.028958, 0.033565, 0.078027, 0.304632",\ + "-0.177282, -0.103131, -0.040609, 0.003854, 0.230458",\ + "-0.245176, -0.171025, -0.108503, -0.064040, 0.162564",\ + "-0.354010, -0.279859, -0.217337, -0.172874, 0.053730",\ + "-0.518682, -0.444530, -0.382008, -0.337546, -0.110941"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.112706, -0.065963, -0.008166, 0.033833, 0.418070",\ + "-0.200788, -0.156050, -0.102190, -0.060192, 0.330575",\ + "-0.289964, -0.245226, -0.193398, -0.151400, 0.241399",\ + "-0.449371, -0.404633, -0.350424, -0.308425, 0.081992",\ + "-0.653554, -0.594763, -0.536828, -0.494793, -0.185077"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[33]_hldr*/ + +} /* end of pin tl_i[33] */ + +pin("tl_i[32]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.025030 ; + + /* Other user defined attributes. */ + original_pin : tl_i[32]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.608686, 5.562531, 5.532314, 5.520957, 5.534564",\ + "5.696244, 5.650089, 5.619872, 5.608514, 5.622122",\ + "5.806668, 5.760513, 5.730296, 5.718939, 5.732546",\ + "5.996225, 5.950070, 5.919853, 5.908495, 5.922103",\ + "6.308736, 6.262581, 6.232364, 6.221007, 6.234614"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.604916, 5.558761, 5.528543, 5.517186, 5.530794",\ + "5.686645, 5.640490, 5.610272, 5.598915, 5.612523",\ + "5.804552, 5.758397, 5.728179, 5.716822, 5.730430",\ + "6.035892, 5.989738, 5.959520, 5.948163, 5.961771",\ + "6.435390, 6.389235, 6.359018, 6.347661, 6.361268"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[32]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.103109, -0.028958, 0.033565, 0.078027, 0.315276",\ + "-0.177282, -0.103131, -0.040609, 0.003854, 0.236790",\ + "-0.245176, -0.171025, -0.108503, -0.064040, 0.162564",\ + "-0.354010, -0.279859, -0.217337, -0.172874, 0.053730",\ + "-0.518682, -0.444530, -0.382008, -0.337546, -0.110941"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.112706, -0.048572, 0.008708, 0.050568, 0.418070",\ + "-0.200788, -0.135648, -0.078368, -0.036508, 0.330575",\ + "-0.289964, -0.226296, -0.169017, -0.127157, 0.241399",\ + "-0.449371, -0.387089, -0.329810, -0.287949, 0.081992",\ + "-0.660870, -0.594763, -0.536828, -0.494793, -0.185077"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[32]_hldr*/ + +} /* end of pin tl_i[32] */ + +pin("tl_i[31]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.025825 ; + + /* Other user defined attributes. */ + original_pin : tl_i[31]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.156651, 5.110496, 5.080278, 5.068921, 5.082529",\ + "5.240004, 5.193849, 5.163631, 5.152274, 5.165882",\ + "5.328885, 5.282730, 5.252513, 5.241156, 5.254763",\ + "5.512913, 5.466758, 5.436541, 5.425183, 5.438791",\ + "5.849318, 5.803163, 5.772945, 5.761588, 5.775196"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.160699, 5.114544, 5.084327, 5.072970, 5.086577",\ + "5.238642, 5.192487, 5.162270, 5.150913, 5.164520",\ + "5.344724, 5.298569, 5.268352, 5.256994, 5.270602",\ + "5.598361, 5.552207, 5.521989, 5.510632, 5.524240",\ + "6.070027, 6.023872, 5.993655, 5.982297, 5.995905"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[31]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.103114, -0.028963, 0.033559, 0.078022, 0.315276",\ + "-0.178370, -0.104212, -0.041630, 0.002858, 0.236790",\ + "-0.246264, -0.172106, -0.109525, -0.065037, 0.161580",\ + "-0.355098, -0.280940, -0.218359, -0.173870, 0.052747",\ + "-0.519769, -0.445611, -0.383030, -0.338542, -0.111925"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.112706, -0.048572, 0.008708, 0.050568, 0.418070",\ + "-0.200783, -0.135648, -0.078368, -0.036508, 0.330579",\ + "-0.289959, -0.226296, -0.169017, -0.127157, 0.241403",\ + "-0.449366, -0.387089, -0.329810, -0.287949, 0.081996",\ + "-0.660870, -0.594763, -0.536828, -0.494793, -0.185073"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[31]_hldr*/ + +} /* end of pin tl_i[31] */ + +pin("tl_i[30]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.025050 ; + + /* Other user defined attributes. */ + original_pin : tl_i[30]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.361538, 5.315383, 5.285166, 5.273808, 5.287416",\ + "5.445924, 5.399769, 5.369552, 5.358194, 5.371802",\ + "5.526791, 5.480636, 5.450418, 5.439061, 5.452669",\ + "5.668298, 5.622143, 5.591926, 5.580568, 5.594176",\ + "5.912872, 5.866717, 5.836500, 5.825143, 5.838750"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.346942, 5.300787, 5.270570, 5.259213, 5.272820",\ + "5.428506, 5.382351, 5.352134, 5.340776, 5.354384",\ + "5.534707, 5.488552, 5.458334, 5.446977, 5.460585",\ + "5.723008, 5.676853, 5.646636, 5.635279, 5.648886",\ + "6.057394, 6.011239, 5.981022, 5.969665, 5.983272"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[30]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.103114, -0.028963, 0.033559, 0.078022, 0.315276",\ + "-0.178370, -0.104212, -0.041630, 0.002858, 0.236790",\ + "-0.246264, -0.172106, -0.109525, -0.065037, 0.161580",\ + "-0.355098, -0.280940, -0.218359, -0.173870, 0.052747",\ + "-0.519769, -0.445611, -0.383030, -0.338542, -0.111925"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.112706, -0.048572, 0.008708, 0.050568, 0.418070",\ + "-0.200783, -0.135648, -0.078368, -0.036508, 0.330579",\ + "-0.289959, -0.226296, -0.169017, -0.127157, 0.241403",\ + "-0.449366, -0.387089, -0.329810, -0.287949, 0.081996",\ + "-0.660870, -0.594763, -0.536828, -0.494793, -0.185073"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[30]_hldr*/ + +} /* end of pin tl_i[30] */ + +pin("tl_i[29]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.026087 ; + + /* Other user defined attributes. */ + original_pin : tl_i[29]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.397203, 5.351048, 5.320831, 5.309474, 5.323081",\ + "5.485135, 5.438980, 5.408763, 5.397406, 5.411013",\ + "5.586405, 5.540250, 5.510033, 5.498675, 5.512283",\ + "5.772069, 5.725914, 5.695697, 5.684340, 5.697948",\ + "6.070103, 6.023948, 5.993731, 5.982373, 5.995981"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.401423, 5.355268, 5.325051, 5.313694, 5.327301",\ + "5.484715, 5.438560, 5.408342, 5.396985, 5.410593",\ + "5.608980, 5.562825, 5.532608, 5.521251, 5.534858",\ + "5.841204, 5.795049, 5.764832, 5.753474, 5.767082",\ + "6.247406, 6.201252, 6.171034, 6.159677, 6.173285"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[29]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.103114, -0.028963, 0.033559, 0.078022, 0.315276",\ + "-0.178370, -0.104212, -0.041630, 0.002858, 0.236790",\ + "-0.246264, -0.172106, -0.109525, -0.065037, 0.161580",\ + "-0.355098, -0.280940, -0.218359, -0.173870, 0.052747",\ + "-0.519769, -0.445611, -0.383030, -0.338542, -0.111925"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.112706, -0.048572, 0.008708, 0.050568, 0.418070",\ + "-0.200783, -0.135648, -0.078368, -0.036508, 0.330579",\ + "-0.289959, -0.226296, -0.169017, -0.127157, 0.241403",\ + "-0.449366, -0.387089, -0.329810, -0.287949, 0.081996",\ + "-0.660870, -0.594763, -0.536828, -0.494793, -0.185073"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[29]_hldr*/ + +} /* end of pin tl_i[29] */ + +pin("tl_i[28]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.025799 ; + + /* Other user defined attributes. */ + original_pin : tl_i[28]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.618461, 5.572306, 5.542089, 5.530732, 5.544339",\ + "5.717470, 5.671315, 5.641098, 5.629741, 5.643348",\ + "5.855001, 5.808846, 5.778629, 5.767272, 5.780879",\ + "6.129478, 6.083323, 6.053106, 6.041749, 6.055356",\ + "6.630586, 6.584431, 6.554214, 6.542856, 6.556464"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.605847, 5.559692, 5.529475, 5.518118, 5.531725",\ + "5.703081, 5.656926, 5.626709, 5.615352, 5.628959",\ + "5.850164, 5.804009, 5.773792, 5.762435, 5.776042",\ + "6.157188, 6.111033, 6.080816, 6.069459, 6.083066",\ + "6.726156, 6.680001, 6.649784, 6.638427, 6.652034"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[28]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.103114, -0.028963, 0.033559, 0.078022, 0.315276",\ + "-0.178370, -0.104212, -0.041630, 0.002858, 0.236790",\ + "-0.246264, -0.172106, -0.109525, -0.065037, 0.161580",\ + "-0.355098, -0.280940, -0.218359, -0.173870, 0.052747",\ + "-0.515343, -0.445611, -0.383030, -0.338542, -0.111925"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.112706, -0.048572, 0.008708, 0.050568, 0.418070",\ + "-0.200783, -0.135648, -0.078368, -0.036508, 0.330579",\ + "-0.289959, -0.226296, -0.169017, -0.127157, 0.241403",\ + "-0.449366, -0.384569, -0.318431, -0.272351, 0.081996",\ + "-0.607923, -0.533171, -0.467033, -0.420953, -0.185073"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[28]_hldr*/ + +} /* end of pin tl_i[28] */ + +pin("tl_i[27]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.025120 ; + + /* Other user defined attributes. */ + original_pin : tl_i[27]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.422370, 5.376215, 5.345998, 5.334641, 5.348248",\ + "5.509055, 5.462900, 5.432683, 5.421326, 5.434933",\ + "5.606899, 5.560744, 5.530527, 5.519170, 5.532777",\ + "5.815886, 5.769731, 5.739513, 5.728156, 5.741764",\ + "6.259951, 6.213796, 6.183579, 6.172222, 6.185829"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.415630, 5.369475, 5.339258, 5.327900, 5.341508",\ + "5.508262, 5.462107, 5.431890, 5.420532, 5.434140",\ + "5.634383, 5.588228, 5.558011, 5.546654, 5.560261",\ + "5.884534, 5.838379, 5.808162, 5.796804, 5.810412",\ + "6.321214, 6.275059, 6.244842, 6.233485, 6.247092"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[27]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.103114, -0.028963, 0.033559, 0.078022, 0.315276",\ + "-0.178370, -0.104212, -0.041630, 0.002858, 0.236790",\ + "-0.246264, -0.172106, -0.109525, -0.065037, 0.161580",\ + "-0.355098, -0.280940, -0.218359, -0.173870, 0.052747",\ + "-0.519769, -0.445611, -0.383030, -0.338542, -0.111925"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.112706, -0.048572, 0.008708, 0.050568, 0.418070",\ + "-0.200783, -0.135648, -0.078368, -0.036508, 0.330579",\ + "-0.289959, -0.226296, -0.169017, -0.127157, 0.241403",\ + "-0.449366, -0.387089, -0.329810, -0.287949, 0.081996",\ + "-0.660870, -0.594763, -0.536828, -0.494793, -0.185073"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[27]_hldr*/ + +} /* end of pin tl_i[27] */ + +pin("tl_i[26]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.025620 ; + + /* Other user defined attributes. */ + original_pin : tl_i[26]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.634807, 5.588652, 5.558434, 5.547077, 5.560685",\ + "5.726879, 5.680724, 5.650507, 5.639150, 5.652757",\ + "5.836696, 5.790541, 5.760324, 5.748966, 5.762574",\ + "6.041320, 5.995165, 5.964948, 5.953590, 5.967198",\ + "6.417303, 6.371148, 6.340931, 6.329574, 6.343181"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.627578, 5.581423, 5.551206, 5.539848, 5.553456",\ + "5.725660, 5.679505, 5.649288, 5.637930, 5.651538",\ + "5.857279, 5.811124, 5.780907, 5.769550, 5.783157",\ + "6.101712, 6.055557, 6.025340, 6.013983, 6.027590",\ + "6.528873, 6.482718, 6.452501, 6.441144, 6.454751"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[26]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.103114, -0.028963, 0.033559, 0.078022, 0.315276",\ + "-0.178370, -0.104212, -0.041630, 0.002858, 0.236790",\ + "-0.246264, -0.172106, -0.109525, -0.065037, 0.161580",\ + "-0.355098, -0.280940, -0.218359, -0.173870, 0.052747",\ + "-0.519769, -0.445611, -0.383030, -0.338542, -0.111925"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.112706, -0.048572, 0.008708, 0.050568, 0.418070",\ + "-0.200783, -0.135648, -0.078368, -0.036508, 0.330579",\ + "-0.289959, -0.226296, -0.169017, -0.127157, 0.241403",\ + "-0.449366, -0.387089, -0.329810, -0.287949, 0.081996",\ + "-0.660870, -0.594763, -0.536828, -0.494793, -0.185073"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[26]_hldr*/ + +} /* end of pin tl_i[26] */ + +pin("tl_i[25]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.027861 ; + + /* Other user defined attributes. */ + original_pin : tl_i[25]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.587914, 5.541759, 5.511542, 5.500185, 5.513792",\ + "5.685092, 5.638937, 5.608720, 5.597363, 5.610970",\ + "5.791002, 5.744847, 5.714630, 5.703273, 5.716880",\ + "5.984866, 5.938711, 5.908494, 5.897137, 5.910744",\ + "6.350015, 6.303860, 6.273643, 6.262286, 6.275893"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.597159, 5.551004, 5.520787, 5.509430, 5.523037",\ + "5.695459, 5.649304, 5.619087, 5.607729, 5.621337",\ + "5.810205, 5.764050, 5.733832, 5.722475, 5.736083",\ + "6.008989, 5.962834, 5.932617, 5.921260, 5.934867",\ + "6.374745, 6.328590, 6.298373, 6.287016, 6.300623"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[25]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.103114, -0.028963, 0.033559, 0.078022, 0.315276",\ + "-0.178370, -0.104212, -0.041630, 0.002858, 0.236790",\ + "-0.246264, -0.172106, -0.109525, -0.065037, 0.161580",\ + "-0.355098, -0.280940, -0.218359, -0.173870, 0.052747",\ + "-0.519769, -0.445611, -0.383030, -0.338542, -0.111925"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.112706, -0.048572, 0.008708, 0.050568, 0.418070",\ + "-0.200783, -0.135648, -0.078368, -0.036508, 0.330579",\ + "-0.289959, -0.226296, -0.169017, -0.127157, 0.241403",\ + "-0.449366, -0.387089, -0.329810, -0.287949, 0.081996",\ + "-0.660870, -0.594763, -0.536828, -0.494793, -0.185073"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[25]_hldr*/ + +} /* end of pin tl_i[25] */ + +pin("tl_i[24]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.026383 ; + + /* Other user defined attributes. */ + original_pin : tl_i[24]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.563736, 5.517581, 5.487364, 5.476007, 5.489614",\ + "5.661705, 5.615550, 5.585332, 5.573975, 5.587583",\ + "5.767614, 5.721459, 5.691242, 5.679884, 5.693492",\ + "5.957180, 5.911025, 5.880808, 5.869451, 5.883058",\ + "6.288558, 6.242403, 6.212186, 6.200829, 6.214436"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.590299, 5.544144, 5.513927, 5.502569, 5.516177",\ + "5.689440, 5.643285, 5.613068, 5.601710, 5.615318",\ + "5.803774, 5.757619, 5.727402, 5.716045, 5.729652",\ + "5.994250, 5.948095, 5.917878, 5.906520, 5.920128",\ + "6.312450, 6.266295, 6.236078, 6.224721, 6.238328"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[24]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.103114, -0.028963, 0.033559, 0.078022, 0.315276",\ + "-0.178370, -0.104212, -0.041630, 0.002858, 0.236790",\ + "-0.246264, -0.172106, -0.109525, -0.065037, 0.161580",\ + "-0.355098, -0.280940, -0.218359, -0.173870, 0.052747",\ + "-0.519769, -0.445611, -0.383030, -0.338542, -0.111925"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.112706, -0.048572, 0.008708, 0.050568, 0.418070",\ + "-0.200783, -0.135648, -0.078368, -0.036508, 0.330579",\ + "-0.289959, -0.226296, -0.169017, -0.127157, 0.241403",\ + "-0.449366, -0.387089, -0.329810, -0.287949, 0.081996",\ + "-0.660870, -0.594763, -0.536828, -0.494793, -0.185073"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[24]_hldr*/ + +} /* end of pin tl_i[24] */ + +pin("tl_i[23]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : tl_i[23]; +} /* end of pin tl_i[23] */ + +pin("tl_i[22]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : tl_i[22]; +} /* end of pin tl_i[22] */ + +pin("tl_i[21]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : tl_i[21]; +} /* end of pin tl_i[21] */ + +pin("tl_i[20]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : tl_i[20]; +} /* end of pin tl_i[20] */ + +pin("tl_i[19]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : tl_i[19]; +} /* end of pin tl_i[19] */ + +pin("tl_i[18]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.005233 ; + + /* Other user defined attributes. */ + original_pin : tl_i[18]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.846815, 5.800660, 5.770443, 5.759086, 5.772694",\ + "5.932193, 5.886038, 5.855821, 5.844464, 5.858071",\ + "6.009590, 5.963435, 5.933218, 5.921861, 5.935469",\ + "6.178617, 6.132463, 6.102246, 6.090889, 6.104496",\ + "6.537492, 6.491337, 6.461120, 6.449763, 6.463370"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.843783, 5.797628, 5.767412, 5.756054, 5.769662",\ + "5.926365, 5.880210, 5.849993, 5.838636, 5.852243",\ + "6.038355, 5.992200, 5.961983, 5.950626, 5.964233",\ + "6.269215, 6.223060, 6.192843, 6.181486, 6.195093",\ + "6.674184, 6.628029, 6.597812, 6.586455, 6.600062"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[18]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.329740, -0.287323, -0.252837, -0.213389, 0.092961",\ + "-0.415095, -0.372677, -0.338191, -0.298743, 0.007607",\ + "-0.499351, -0.456933, -0.422448, -0.383000, -0.076649",\ + "-0.641023, -0.598605, -0.564119, -0.524671, -0.218321",\ + "-0.860645, -0.818228, -0.783742, -0.744294, -0.437944"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.392665, -0.350247, -0.315761, -0.276314, 0.030037",\ + "-0.480853, -0.438436, -0.403950, -0.364502, -0.058152",\ + "-0.581004, -0.538587, -0.504101, -0.464653, -0.158303",\ + "-0.765285, -0.722867, -0.665898, -0.623927, -0.342583",\ + "-1.010030, -0.967612, -0.918979, -0.877008, -0.587328"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[18]_hldr*/ + +} /* end of pin tl_i[18] */ + +pin("tl_i[17]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.004306 ; + + /* Other user defined attributes. */ + original_pin : tl_i[17]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "6.132060, 6.085905, 6.055688, 6.044331, 6.057939",\ + "6.217465, 6.171310, 6.141094, 6.129736, 6.143344",\ + "6.294953, 6.248798, 6.218582, 6.207224, 6.220832",\ + "6.439157, 6.393003, 6.362786, 6.351429, 6.365036",\ + "6.796788, 6.750633, 6.720417, 6.709059, 6.722667"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "6.129071, 6.082916, 6.052700, 6.041342, 6.054950",\ + "6.211690, 6.165535, 6.135318, 6.123961, 6.137568",\ + "6.323722, 6.277567, 6.247350, 6.235993, 6.249600",\ + "6.554055, 6.507900, 6.477684, 6.466326, 6.479934",\ + "6.957980, 6.911825, 6.881608, 6.870251, 6.883859"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[17]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.329387, -0.286969, -0.252483, -0.213035, 0.093315",\ + "-0.413395, -0.370977, -0.336491, -0.297044, 0.009307",\ + "-0.496847, -0.454429, -0.419944, -0.380496, -0.074145",\ + "-0.636423, -0.594005, -0.559520, -0.520072, -0.213721",\ + "-0.849170, -0.806753, -0.772267, -0.732819, -0.426469"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.397874, -0.355456, -0.320970, -0.281523, 0.024828",\ + "-0.486065, -0.443648, -0.409162, -0.369714, -0.063364",\ + "-0.585801, -0.543384, -0.506390, -0.464420, -0.163100",\ + "-0.770163, -0.720512, -0.662817, -0.620846, -0.347461",\ + "-1.005635, -0.963218, -0.913955, -0.871984, -0.582934"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[17]_hldr*/ + +} /* end of pin tl_i[17] */ + +pin("tl_i[16]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.003506 ; + + /* Other user defined attributes. */ + original_pin : tl_i[16]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "6.061040, 6.014885, 5.984668, 5.973311, 5.986918",\ + "6.154351, 6.108196, 6.077980, 6.066622, 6.080230",\ + "6.247583, 6.201428, 6.171212, 6.159854, 6.173462",\ + "6.410316, 6.364161, 6.333944, 6.322587, 6.336194",\ + "6.686312, 6.640157, 6.609940, 6.598583, 6.612190"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "6.018520, 5.972365, 5.942149, 5.930791, 5.944399",\ + "6.115014, 6.068859, 6.038642, 6.027285, 6.040893",\ + "6.214722, 6.168567, 6.138350, 6.126993, 6.140600",\ + "6.391147, 6.344992, 6.314775, 6.303418, 6.317025",\ + "6.683747, 6.637592, 6.607376, 6.596018, 6.609626"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[16]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.394478, -0.352061, -0.317575, -0.278127, 0.028223",\ + "-0.483595, -0.441177, -0.404014, -0.362043, -0.060893",\ + "-0.569978, -0.527561, -0.480614, -0.438644, -0.147277",\ + "-0.718308, -0.666396, -0.608701, -0.566730, -0.295606",\ + "-0.932373, -0.866433, -0.808738, -0.766767, -0.544592"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.386365, -0.343947, -0.309462, -0.270014, 0.036337",\ + "-0.468621, -0.426203, -0.391718, -0.352270, -0.045919",\ + "-0.564853, -0.522435, -0.487950, -0.448502, -0.142151",\ + "-0.726358, -0.683941, -0.649455, -0.610007, -0.303657",\ + "-0.988854, -0.946436, -0.911950, -0.872503, -0.566152"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[16]_hldr*/ + +} /* end of pin tl_i[16] */ + +pin("tl_i[15]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.003647 ; + + /* Other user defined attributes. */ + original_pin : tl_i[15]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.804135, 5.757980, 5.727764, 5.716406, 5.730014",\ + "5.902175, 5.856020, 5.825803, 5.814446, 5.828053",\ + "6.008589, 5.962434, 5.932217, 5.920860, 5.934467",\ + "6.199651, 6.153496, 6.123279, 6.111922, 6.125529",\ + "6.533928, 6.487773, 6.457556, 6.446199, 6.459806"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.811823, 5.765668, 5.735451, 5.724094, 5.737701",\ + "5.911395, 5.865240, 5.835023, 5.823666, 5.837274",\ + "6.026561, 5.980406, 5.950189, 5.938832, 5.952439",\ + "6.220825, 6.174670, 6.144454, 6.133096, 6.146704",\ + "6.548571, 6.502416, 6.472199, 6.460842, 6.474449"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[15]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.333549, -0.291131, -0.256645, -0.217198, 0.089153",\ + "-0.416355, -0.373937, -0.339451, -0.300003, 0.006347",\ + "-0.498092, -0.455675, -0.421189, -0.381741, -0.075391",\ + "-0.641500, -0.599082, -0.564596, -0.525149, -0.218798",\ + "-0.881493, -0.839075, -0.804590, -0.765142, -0.458791"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.367074, -0.324657, -0.290171, -0.250723, 0.055627",\ + "-0.454947, -0.412529, -0.378044, -0.338596, -0.032245",\ + "-0.540971, -0.498554, -0.464068, -0.424620, -0.118270",\ + "-0.691009, -0.648592, -0.614106, -0.574658, -0.268308",\ + "-0.937715, -0.895297, -0.860812, -0.821364, -0.515013"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[15]_hldr*/ + +} /* end of pin tl_i[15] */ + +pin("tl_i[14]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000507 ; + + /* Other user defined attributes. */ + original_pin : tl_i[14]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.880361, 5.834206, 5.803989, 5.792632, 5.806239",\ + "5.967889, 5.921734, 5.891517, 5.880160, 5.893767",\ + "6.055178, 6.009023, 5.978806, 5.967449, 5.981056",\ + "6.230941, 6.184786, 6.154569, 6.143212, 6.156819",\ + "6.640085, 6.593930, 6.563713, 6.552356, 6.565963"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.875138, 5.828983, 5.798766, 5.787409, 5.801016",\ + "5.963992, 5.917837, 5.887620, 5.876263, 5.889871",\ + "6.079109, 6.032954, 6.002738, 5.991380, 6.004988",\ + "6.317663, 6.271508, 6.241292, 6.229934, 6.243542",\ + "6.755099, 6.708944, 6.678727, 6.667370, 6.680977"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[14]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.456322, -1.413945, -1.379366, -1.341730, -1.057874",\ + "-1.546534, -1.504156, -1.469577, -1.431942, -1.148085",\ + "-1.659324, -1.616947, -1.582367, -1.544732, -1.260875",\ + "-1.878867, -1.836490, -1.801910, -1.764275, -1.480418",\ + "-2.185190, -2.142812, -2.108233, -2.070598, -1.786741"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.489696, -1.447319, -1.412740, -1.375104, -1.091248",\ + "-1.579588, -1.537211, -1.502631, -1.464996, -1.181139",\ + "-1.675047, -1.632670, -1.598091, -1.560455, -1.276599",\ + "-1.845432, -1.803055, -1.768476, -1.730840, -1.446984",\ + "-2.145069, -2.102692, -2.068113, -2.030477, -1.746621"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[14]_hldr*/ + +} /* end of pin tl_i[14] */ + +pin("tl_i[13]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000507 ; + + /* Other user defined attributes. */ + original_pin : tl_i[13]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "6.164994, 6.118839, 6.088623, 6.077265, 6.090873",\ + "6.252498, 6.206343, 6.176126, 6.164769, 6.178376",\ + "6.339791, 6.293636, 6.263420, 6.252062, 6.265670",\ + "6.496986, 6.450831, 6.420614, 6.409257, 6.422864",\ + "6.898607, 6.852452, 6.822236, 6.810878, 6.824486"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "6.159660, 6.113505, 6.083289, 6.071931, 6.085539",\ + "6.248568, 6.202413, 6.172196, 6.160839, 6.174446",\ + "6.363653, 6.317498, 6.287282, 6.275924, 6.289532",\ + "6.601918, 6.555763, 6.525547, 6.514189, 6.527797",\ + "7.038295, 6.992140, 6.961923, 6.950566, 6.964173"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[13]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.676593, -1.628499, -1.570612, -1.528590, -1.278144",\ + "-1.766810, -1.718717, -1.660830, -1.618807, -1.368362",\ + "-1.879585, -1.831491, -1.773605, -1.731582, -1.481137",\ + "-2.098712, -2.050618, -1.992732, -1.950709, -1.700264",\ + "-2.408059, -2.359965, -2.302078, -2.260055, -2.009610"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.710053, -1.661959, -1.604072, -1.562050, -1.311604",\ + "-1.799952, -1.751858, -1.693972, -1.651949, -1.401504",\ + "-1.895418, -1.847324, -1.789437, -1.747415, -1.496969",\ + "-2.065788, -2.017694, -1.959808, -1.917785, -1.667340",\ + "-2.365375, -2.317281, -2.259394, -2.217371, -1.966926"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[13]_hldr*/ + +} /* end of pin tl_i[13] */ + +pin("tl_i[12]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001105 ; + + /* Other user defined attributes. */ + original_pin : tl_i[12]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.508289, 5.462134, 5.431918, 5.420560, 5.434168",\ + "5.592647, 5.546492, 5.516275, 5.504918, 5.518525",\ + "5.673546, 5.627391, 5.597174, 5.585817, 5.599424",\ + "5.815136, 5.768981, 5.738764, 5.727407, 5.741014",\ + "6.052000, 6.005845, 5.975628, 5.964271, 5.977879"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.430960, 5.384805, 5.354588, 5.343231, 5.356838",\ + "5.522353, 5.476198, 5.445981, 5.434624, 5.448231",\ + "5.614760, 5.568605, 5.538389, 5.527031, 5.540639",\ + "5.776403, 5.730248, 5.700032, 5.688674, 5.702282",\ + "6.049640, 6.003485, 5.973268, 5.961911, 5.975518"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[12]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.265898, -1.223521, -1.188942, -1.151306, -0.867450",\ + "-1.350510, -1.308133, -1.273553, -1.235918, -0.952061",\ + "-1.430668, -1.388291, -1.353711, -1.316076, -1.032219",\ + "-1.572586, -1.530209, -1.495630, -1.457994, -1.174138",\ + "-1.810084, -1.767707, -1.733127, -1.695492, -1.411635"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.242763, -1.200386, -1.165807, -1.128171, -0.844315",\ + "-1.334117, -1.291740, -1.257160, -1.219525, -0.935668",\ + "-1.427063, -1.384685, -1.350106, -1.312471, -1.028614",\ + "-1.589313, -1.546936, -1.512356, -1.474721, -1.190864",\ + "-1.862213, -1.819836, -1.785256, -1.747621, -1.463764"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[12]_hldr*/ + +} /* end of pin tl_i[12] */ + +pin("tl_i[11]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000507 ; + + /* Other user defined attributes. */ + original_pin : tl_i[11]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.261997, 5.215842, 5.185626, 5.174268, 5.187876",\ + "5.353421, 5.307266, 5.277050, 5.265692, 5.279300",\ + "5.463365, 5.417210, 5.386993, 5.375636, 5.389243",\ + "5.679752, 5.633597, 5.603381, 5.592023, 5.605631",\ + "6.088896, 6.042741, 6.012525, 6.001167, 6.014775"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.323949, 5.277794, 5.247577, 5.236220, 5.249827",\ + "5.412804, 5.366649, 5.336432, 5.325075, 5.338682",\ + "5.527921, 5.481766, 5.451549, 5.440192, 5.453799",\ + "5.766475, 5.720320, 5.690103, 5.678746, 5.692353",\ + "6.203910, 6.157755, 6.127538, 6.116181, 6.129788"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[11]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.231498, -1.189121, -1.154542, -1.116906, -0.833050",\ + "-1.321710, -1.279333, -1.244753, -1.207118, -0.923261",\ + "-1.434500, -1.392123, -1.357543, -1.319908, -1.036052",\ + "-1.654043, -1.611666, -1.577086, -1.539451, -1.255594",\ + "-2.055035, -2.012658, -1.978078, -1.940443, -1.656586"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.277769, -1.235391, -1.200812, -1.163177, -0.879320",\ + "-1.368203, -1.325825, -1.291246, -1.253611, -0.969754",\ + "-1.482250, -1.439872, -1.405293, -1.367658, -1.083801",\ + "-1.702415, -1.660038, -1.625458, -1.587823, -1.303966",\ + "-2.095423, -2.053046, -2.018466, -1.980831, -1.696974"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[11]_hldr*/ + +} /* end of pin tl_i[11] */ + +pin("tl_i[10]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000507 ; + + /* Other user defined attributes. */ + original_pin : tl_i[10]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.688106, 5.641951, 5.611734, 5.600377, 5.613985",\ + "5.775612, 5.729457, 5.699240, 5.687883, 5.701490",\ + "5.862906, 5.816751, 5.786535, 5.775177, 5.788785",\ + "6.017570, 5.971415, 5.941198, 5.929841, 5.943448",\ + "6.285493, 6.239338, 6.209121, 6.197764, 6.211371"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.621125, 5.574970, 5.544754, 5.533396, 5.547004",\ + "5.711027, 5.664872, 5.634655, 5.623298, 5.636906",\ + "5.806498, 5.760343, 5.730126, 5.718769, 5.732377",\ + "5.976879, 5.930724, 5.900507, 5.889150, 5.902758",\ + "6.276484, 6.230330, 6.200113, 6.188756, 6.202363"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[10]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.488494, -1.446116, -1.411537, -1.373901, -1.090045",\ + "-1.576000, -1.533622, -1.499043, -1.461408, -1.177551",\ + "-1.663294, -1.620917, -1.586338, -1.548702, -1.264846",\ + "-1.817957, -1.775580, -1.741001, -1.703365, -1.419509",\ + "-2.085881, -2.043503, -2.008924, -1.971289, -1.687432"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.387740, -1.345363, -1.310783, -1.273148, -0.989291",\ + "-1.477641, -1.435264, -1.400684, -1.363049, -1.079192",\ + "-1.573112, -1.530735, -1.496156, -1.458520, -1.174664",\ + "-1.743494, -1.701116, -1.666537, -1.628902, -1.345045",\ + "-2.043099, -2.000721, -1.966142, -1.928507, -1.644650"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[10]_hldr*/ + +} /* end of pin tl_i[10] */ + +pin("tl_i[9]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000507 ; + + /* Other user defined attributes. */ + original_pin : tl_i[9]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.299526, 5.253371, 5.223155, 5.211797, 5.225405",\ + "5.387030, 5.340875, 5.310658, 5.299301, 5.312908",\ + "5.474324, 5.428169, 5.397952, 5.386595, 5.400202",\ + "5.628947, 5.582792, 5.552575, 5.541218, 5.554825",\ + "5.896894, 5.850739, 5.820522, 5.809165, 5.822773"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.267633, 5.221478, 5.191262, 5.179904, 5.193512",\ + "5.357825, 5.311670, 5.281454, 5.270096, 5.283704",\ + "5.453746, 5.407591, 5.377375, 5.366017, 5.379625",\ + "5.626006, 5.579851, 5.549634, 5.538277, 5.551885",\ + "5.922129, 5.875974, 5.845757, 5.834400, 5.848007"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[9]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.240064, -1.197687, -1.163107, -1.125472, -0.841615",\ + "-1.327747, -1.285370, -1.250791, -1.213155, -0.929299",\ + "-1.415402, -1.373024, -1.338445, -1.300810, -1.016953",\ + "-1.572242, -1.529865, -1.495286, -1.457650, -1.173794",\ + "-1.840724, -1.798346, -1.763767, -1.726132, -1.442275"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.220831, -1.178454, -1.143874, -1.106239, -0.822382",\ + "-1.310730, -1.268353, -1.233773, -1.196138, -0.912281",\ + "-1.406196, -1.363818, -1.329239, -1.291603, -1.007747",\ + "-1.576566, -1.534189, -1.499609, -1.461974, -1.178117",\ + "-1.876152, -1.833775, -1.799196, -1.761560, -1.477704"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[9]_hldr*/ + +} /* end of pin tl_i[9] */ + +pin("tl_i[8]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000507 ; + + /* Other user defined attributes. */ + original_pin : tl_i[8]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.306569, 5.260414, 5.230197, 5.218840, 5.232448",\ + "5.394075, 5.347920, 5.317704, 5.306346, 5.319954",\ + "5.481370, 5.435215, 5.404998, 5.393641, 5.407248",\ + "5.636033, 5.589878, 5.559661, 5.548304, 5.561912",\ + "5.903956, 5.857801, 5.827585, 5.816227, 5.829835"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.239589, 5.193434, 5.163217, 5.151860, 5.165467",\ + "5.329490, 5.283335, 5.253119, 5.241761, 5.255369",\ + "5.424961, 5.378806, 5.348589, 5.337232, 5.350840",\ + "5.595343, 5.549188, 5.518971, 5.507614, 5.521221",\ + "5.894948, 5.848793, 5.818576, 5.807219, 5.820827"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[8]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.339799, -1.297422, -1.262842, -1.225207, -0.941350",\ + "-1.427305, -1.384928, -1.350348, -1.312713, -1.028856",\ + "-1.514600, -1.472222, -1.437643, -1.400007, -1.116151",\ + "-1.669263, -1.626886, -1.592306, -1.554671, -1.270814",\ + "-1.937186, -1.894809, -1.860229, -1.822594, -1.538737"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.239045, -1.196668, -1.162088, -1.124453, -0.840596",\ + "-1.328946, -1.286569, -1.251990, -1.214354, -0.930498",\ + "-1.424418, -1.382040, -1.347461, -1.309826, -1.025969",\ + "-1.594799, -1.552422, -1.517842, -1.480207, -1.196350",\ + "-1.894404, -1.852027, -1.817448, -1.779812, -1.495956"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[8]_hldr*/ + +} /* end of pin tl_i[8] */ + +pin("tl_i[7]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000507 ; + + /* Other user defined attributes. */ + original_pin : tl_i[7]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.737750, 5.691595, 5.661378, 5.650021, 5.663628",\ + "5.825280, 5.779125, 5.748908, 5.737551, 5.751158",\ + "5.912570, 5.866415, 5.836198, 5.824841, 5.838448",\ + "6.086271, 6.040116, 6.009899, 5.998541, 6.012149",\ + "6.495438, 6.449283, 6.419065, 6.407708, 6.421316"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.732527, 5.686372, 5.656155, 5.644798, 5.658405",\ + "5.821378, 5.775223, 5.745006, 5.733648, 5.747256",\ + "5.936484, 5.890329, 5.860112, 5.848755, 5.862362",\ + "6.175041, 6.128886, 6.098669, 6.087312, 6.100919",\ + "6.612741, 6.566586, 6.536369, 6.525012, 6.538620"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[7]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.210458, -1.168081, -1.133501, -1.095866, -0.812009",\ + "-1.300683, -1.258306, -1.223726, -1.186091, -0.902234",\ + "-1.413495, -1.371118, -1.336539, -1.298903, -1.015047",\ + "-1.594716, -1.552338, -1.517759, -1.480124, -1.196267",\ + "-1.863199, -1.820821, -1.786242, -1.748607, -1.464750"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.243829, -1.201452, -1.166873, -1.129237, -0.845381",\ + "-1.333722, -1.291345, -1.256766, -1.219130, -0.935274",\ + "-1.429188, -1.386811, -1.352232, -1.314596, -1.030740",\ + "-1.599584, -1.557206, -1.522627, -1.484991, -1.201135",\ + "-1.899240, -1.856863, -1.822283, -1.784648, -1.500791"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[7]_hldr*/ + +} /* end of pin tl_i[7] */ + +pin("tl_i[6]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001034 ; + + /* Other user defined attributes. */ + original_pin : tl_i[6]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.368608, 5.322453, 5.292236, 5.280879, 5.294487",\ + "5.454073, 5.407918, 5.377701, 5.366343, 5.379951",\ + "5.531495, 5.485340, 5.455123, 5.443766, 5.457373",\ + "5.675749, 5.629594, 5.599377, 5.588020, 5.601627",\ + "6.027932, 5.981777, 5.951560, 5.940202, 5.953810"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.365854, 5.319699, 5.289482, 5.278125, 5.291732",\ + "5.448556, 5.402401, 5.372184, 5.360826, 5.374434",\ + "5.560353, 5.514198, 5.483981, 5.472623, 5.486231",\ + "5.789183, 5.743028, 5.712811, 5.701454, 5.715061",\ + "6.188337, 6.142182, 6.111965, 6.100607, 6.114215"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[6]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.925690, -0.883313, -0.848733, -0.811098, -0.527241",\ + "-1.010422, -0.968045, -0.933465, -0.895830, -0.611973",\ + "-1.117256, -1.074878, -1.040299, -1.002663, -0.718807",\ + "-1.269870, -1.227492, -1.192913, -1.155277, -0.871421",\ + "-1.497461, -1.455084, -1.420505, -1.382869, -1.099013"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.942127, -0.899750, -0.865171, -0.827535, -0.543679",\ + "-1.032129, -0.989751, -0.955172, -0.917537, -0.633680",\ + "-1.120122, -1.077745, -1.043165, -1.005530, -0.721673",\ + "-1.275255, -1.232878, -1.198298, -1.160663, -0.876806",\ + "-1.540632, -1.498255, -1.463676, -1.426040, -1.142184"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[6]_hldr*/ + +} /* end of pin tl_i[6] */ + +pin("tl_i[5]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000507 ; + + /* Other user defined attributes. */ + original_pin : tl_i[5]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.646876, 5.600721, 5.570504, 5.559147, 5.572754",\ + "5.734406, 5.688251, 5.658034, 5.646677, 5.660285",\ + "5.821696, 5.775541, 5.745324, 5.733967, 5.747574",\ + "5.997414, 5.951259, 5.921041, 5.909684, 5.923292",\ + "6.406565, 6.360410, 6.330193, 6.318835, 6.332443"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.641654, 5.595499, 5.565282, 5.553925, 5.567532",\ + "5.730504, 5.684349, 5.654132, 5.642775, 5.656382",\ + "5.845611, 5.799456, 5.769239, 5.757882, 5.771489",\ + "6.084159, 6.038004, 6.007787, 5.996430, 6.010037",\ + "6.521860, 6.475705, 6.445487, 6.434130, 6.447738"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[5]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.106780, -1.064402, -1.029823, -0.992188, -0.708331",\ + "-1.197005, -1.154628, -1.120048, -1.082413, -0.798556",\ + "-1.309817, -1.267440, -1.232860, -1.195225, -0.911368",\ + "-1.491037, -1.448660, -1.414081, -1.376445, -1.092589",\ + "-1.759520, -1.717143, -1.682564, -1.644928, -1.361072"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.140151, -1.097774, -1.063194, -1.025559, -0.741702",\ + "-1.230044, -1.187667, -1.153087, -1.115452, -0.831595",\ + "-1.325510, -1.283133, -1.248553, -1.210918, -0.927061",\ + "-1.495905, -1.453528, -1.418948, -1.381313, -1.097456",\ + "-1.795562, -1.753184, -1.718605, -1.680969, -1.397113"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[5]_hldr*/ + +} /* end of pin tl_i[5] */ + +pin("tl_i[4]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001034 ; + + /* Other user defined attributes. */ + original_pin : tl_i[4]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "4.980015, 4.933860, 4.903643, 4.892286, 4.905893",\ + "5.065440, 5.019285, 4.989068, 4.977711, 4.991318",\ + "5.143021, 5.096866, 5.066648, 5.055291, 5.068899",\ + "5.322774, 5.276619, 5.246402, 5.235044, 5.248652",\ + "5.675738, 5.629583, 5.599366, 5.588009, 5.601616"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "4.977059, 4.930904, 4.900687, 4.889330, 4.902937",\ + "5.059716, 5.013561, 4.983344, 4.971986, 4.985594",\ + "5.171787, 5.125632, 5.095415, 5.084057, 5.097665",\ + "5.401430, 5.355275, 5.325058, 5.313701, 5.327308",\ + "5.800714, 5.754560, 5.724342, 5.712985, 5.726593"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[4]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.891577, -0.849200, -0.814620, -0.776985, -0.493128",\ + "-0.976303, -0.933926, -0.899346, -0.861711, -0.577854",\ + "-1.083459, -1.041082, -1.006503, -0.968867, -0.685011",\ + "-1.234205, -1.191828, -1.157249, -1.119613, -0.835757",\ + "-1.461877, -1.419500, -1.384920, -1.347285, -1.063428"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.907849, -0.865472, -0.830893, -0.793257, -0.509401",\ + "-0.997841, -0.955464, -0.920885, -0.883249, -0.599393",\ + "-1.085765, -1.043387, -1.008808, -0.971172, -0.687316",\ + "-1.240999, -1.198622, -1.164043, -1.126407, -0.842551",\ + "-1.506646, -1.464268, -1.429689, -1.392054, -1.108197"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[4]_hldr*/ + +} /* end of pin tl_i[4] */ + +pin("tl_i[3]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000507 ; + + /* Other user defined attributes. */ + original_pin : tl_i[3]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "4.861817, 4.815662, 4.785445, 4.774088, 4.787695",\ + "4.949495, 4.903340, 4.873123, 4.861766, 4.875373",\ + "5.036715, 4.990560, 4.960342, 4.948985, 4.962593",\ + "5.207161, 5.161006, 5.130789, 5.119431, 5.133039",\ + "5.608678, 5.562523, 5.532306, 5.520948, 5.534556"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "4.856341, 4.810186, 4.779969, 4.768611, 4.782219",\ + "4.945419, 4.899264, 4.869047, 4.857689, 4.871297",\ + "5.060649, 5.014494, 4.984277, 4.972920, 4.986527",\ + "5.297888, 5.251733, 5.221516, 5.210158, 5.223766",\ + "5.732176, 5.686021, 5.655804, 5.644446, 5.658054"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[3]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.940665, -0.898288, -0.863709, -0.826073, -0.542217",\ + "-1.030843, -0.988466, -0.953887, -0.916251, -0.632395",\ + "-1.143556, -1.101179, -1.066599, -1.028964, -0.745108",\ + "-1.327817, -1.285440, -1.250861, -1.213225, -0.929369",\ + "-1.596320, -1.553943, -1.519363, -1.481728, -1.197871"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.974330, -0.931952, -0.897373, -0.859738, -0.575881",\ + "-1.064250, -1.021872, -0.987293, -0.949658, -0.665801",\ + "-1.159754, -1.117377, -1.082797, -1.045162, -0.761305",\ + "-1.330068, -1.287690, -1.253111, -1.215476, -0.931619",\ + "-1.629461, -1.587083, -1.552504, -1.514869, -1.231012"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[3]_hldr*/ + +} /* end of pin tl_i[3] */ + +pin("tl_i[2]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001034 ; + + /* Other user defined attributes. */ + original_pin : tl_i[2]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "4.870526, 4.824371, 4.794154, 4.782797, 4.796404",\ + "4.955990, 4.909835, 4.879618, 4.868261, 4.881868",\ + "5.033412, 4.987257, 4.957040, 4.945683, 4.959291",\ + "5.177666, 5.131511, 5.101294, 5.089936, 5.103544",\ + "5.529849, 5.483694, 5.453477, 5.442120, 5.455727"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "4.867772, 4.821617, 4.791399, 4.780042, 4.793650",\ + "4.950474, 4.904319, 4.874102, 4.862744, 4.876352",\ + "5.062271, 5.016116, 4.985898, 4.974541, 4.988149",\ + "5.291101, 5.244946, 5.214728, 5.203371, 5.216979",\ + "5.690255, 5.644100, 5.613883, 5.602525, 5.616133"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[2]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.870275, -0.827898, -0.793318, -0.755683, -0.471826",\ + "-0.955007, -0.912630, -0.878051, -0.840415, -0.556558",\ + "-1.061841, -1.019464, -0.984884, -0.947249, -0.663392",\ + "-1.214455, -1.172078, -1.137498, -1.099863, -0.816006",\ + "-1.442046, -1.399669, -1.365090, -1.327454, -1.043598"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.886713, -0.844335, -0.809756, -0.772120, -0.488264",\ + "-0.976714, -0.934337, -0.899757, -0.862122, -0.578265",\ + "-1.064707, -1.022330, -0.987750, -0.950115, -0.666258",\ + "-1.219840, -1.177463, -1.142883, -1.105248, -0.821391",\ + "-1.485218, -1.442840, -1.408261, -1.370625, -1.086769"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[2]_hldr*/ + +} /* end of pin tl_i[2] */ + +pin("tl_i[1]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001034 ; + + /* Other user defined attributes. */ + original_pin : tl_i[1]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "4.874022, 4.827868, 4.797650, 4.786293, 4.799901",\ + "4.959486, 4.913332, 4.883114, 4.871757, 4.885365",\ + "5.036908, 4.990753, 4.960536, 4.949179, 4.962786",\ + "5.181162, 5.135007, 5.104790, 5.093432, 5.107040",\ + "5.533345, 5.487190, 5.456973, 5.445615, 5.459223"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "4.871267, 4.825112, 4.794895, 4.783538, 4.797145",\ + "4.953969, 4.907815, 4.877597, 4.866240, 4.879848",\ + "5.065766, 5.019611, 4.989394, 4.978037, 4.991644",\ + "5.294597, 5.248442, 5.218225, 5.206867, 5.220475",\ + "5.693750, 5.647595, 5.617378, 5.606021, 5.619628"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[1]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.871744, -0.829367, -0.794788, -0.757152, -0.473296",\ + "-0.956476, -0.914099, -0.879520, -0.841884, -0.558028",\ + "-1.063310, -1.020933, -0.986354, -0.948718, -0.664862",\ + "-1.215924, -1.173547, -1.138968, -1.101332, -0.817476",\ + "-1.443516, -1.401139, -1.366559, -1.328924, -1.045067"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.888182, -0.845805, -0.811225, -0.773590, -0.489733",\ + "-0.978183, -0.935806, -0.901227, -0.863591, -0.579735",\ + "-1.066176, -1.023799, -0.989220, -0.951584, -0.667728",\ + "-1.221309, -1.178932, -1.144353, -1.106717, -0.822861",\ + "-1.486687, -1.444310, -1.409730, -1.372095, -1.088238"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[1]_hldr*/ + +} /* end of pin tl_i[1] */ + +pin("tl_i[0]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000516 ; + + /* Other user defined attributes. */ + original_pin : tl_i[0]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.175613, 0.100294, 0.032151, 0.009209, 0.072356",\ + "0.264638, 0.189339, 0.121299, 0.098527, 0.163209",\ + "0.360287, 0.285032, 0.217232, 0.194849, 0.263068",\ + "0.526788, 0.451609, 0.383810, 0.361643, 0.432490",\ + "0.806358, 0.731299, 0.662593, 0.639784, 0.707364"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.201785, 0.154982, 0.124714, 0.113318, 0.126704",\ + "0.285559, 0.238387, 0.208091, 0.196673, 0.209933",\ + "0.386189, 0.338377, 0.307866, 0.296333, 0.309292",\ + "0.553781, 0.505930, 0.474764, 0.462933, 0.475551",\ + "0.832990, 0.785063, 0.752603, 0.740184, 0.752132"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[0]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.088868, -0.022902, 0.034829, 0.076810, 0.297292",\ + "-0.178002, -0.111712, -0.053514, -0.011408, 0.208267",\ + "-0.273901, -0.206863, -0.147593, -0.105196, 0.112621",\ + "-0.440525, -0.372044, -0.311267, -0.268345, -0.051699",\ + "-0.719618, -0.648392, -0.585857, -0.542000, -0.322826"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.133037, -0.090779, -0.055923, -0.023644, 0.193736",\ + "-0.216520, -0.174329, -0.139318, -0.110044, 0.070036",\ + "-0.315601, -0.273256, -0.237974, -0.213810, -0.097198",\ + "-0.479066, -0.435673, -0.400366, -0.376078, -0.258082",\ + "-0.750133, -0.704672, -0.669317, -0.644785, -0.524056"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[0]_hldr*/ + +} /* end of pin tl_i[0] */ +} /* end of bus tl_i */ +bus ( tl_o ) { + + bus_type : BUS66_type1 ; + direction : output ; + +pin("tl_o[65]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000991 ; + + /* Other user defined attributes. */ + original_pin : tl_o[65]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000991, 0.073990, 0.161246, 0.321501, 0.642011"); + values ( "0.044997, 0.199162, 0.375038, 0.698306, 1.344843",\ + "0.131049, 0.286337, 0.462145, 0.785022, 1.430777",\ + "0.213199, 0.374466, 0.550102, 0.872645, 1.517732",\ + "0.270183, 0.438865, 0.614219, 0.936559, 1.581241",\ + "0.564592, 0.788723, 0.964610, 1.285306, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000991, 0.073990, 0.161246, 0.321501, 0.642011"); + values ( "0.020343, 0.295887, 0.630096, 1.247585, 2.482563",\ + "0.025257, 0.296852, 0.632059, 1.247585, 2.482563",\ + "0.038535, 0.299143, 0.632095, 1.247585, 2.482563",\ + "0.050320, 0.302473, 0.632193, 1.247585, 2.482563",\ + "0.124837, 0.341325, 0.638465, 1.250160, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000991, 0.073990, 0.161246, 0.321501, 0.642011"); + values ( "0.064792, 0.171653, 0.283425, 0.487864, 0.896742",\ + "0.152284, 0.258972, 0.370706, 0.575169, 0.984096",\ + "0.232529, 0.339311, 0.450733, 0.655198, 1.064127",\ + "0.289052, 0.396859, 0.508277, 0.712443, 1.120775",\ + "0.581256, 0.700191, 0.811913, 1.015459, 1.422552"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000991, 0.073990, 0.161246, 0.321501, 0.642011"); + values ( "0.021933, 0.185126, 0.386052, 0.758836, 1.504404",\ + "0.021933, 0.185264, 0.386558, 0.758836, 1.504404",\ + "0.022969, 0.185264, 0.386558, 0.758836, 1.504404",\ + "0.025189, 0.185264, 0.386558, 0.758836, 1.504404",\ + "0.044032, 0.189320, 0.386558, 0.758836, 1.504684"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[65]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000991, 0.073990, 0.161246, 0.321501, 0.642011"); + values ( "0.044997, 0.199162, 0.375038, 0.698306, 1.344843",\ + "0.131049, 0.286337, 0.462145, 0.785022, 1.430777",\ + "0.213199, 0.374466, 0.550102, 0.872645, 1.517732",\ + "0.270183, 0.438865, 0.614219, 0.936559, 1.581241",\ + "0.564592, 0.788723, 0.964610, 1.285306, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000991, 0.073990, 0.161246, 0.321501, 0.642011"); + values ( "0.020343, 0.295887, 0.630096, 1.246366, 2.473547",\ + "0.025257, 0.296852, 0.632059, 1.246366, 2.473547",\ + "0.038535, 0.299143, 0.632095, 1.246442, 2.473547",\ + "0.050320, 0.302473, 0.632193, 1.247184, 2.473547",\ + "0.124837, 0.341325, 0.638465, 1.250160, 2.473547"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000991, 0.073990, 0.161246, 0.321501, 0.642011"); + values ( "0.064792, 0.171653, 0.283425, 0.487864, 0.896742",\ + "0.152284, 0.258972, 0.370706, 0.575169, 0.984096",\ + "0.232529, 0.339311, 0.450733, 0.655198, 1.064127",\ + "0.289052, 0.396859, 0.508277, 0.712443, 1.120775",\ + "0.581256, 0.700191, 0.811913, 1.015459, 1.422552"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000991, 0.073990, 0.161246, 0.321501, 0.642011"); + values ( "0.021933, 0.184336, 0.384548, 0.756608, 1.500727",\ + "0.021933, 0.184336, 0.384548, 0.756608, 1.500727",\ + "0.022969, 0.184336, 0.384548, 0.756608, 1.500727",\ + "0.025189, 0.184950, 0.385003, 0.757508, 1.502518",\ + "0.044032, 0.189320, 0.385072, 0.758276, 1.504684"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[65]_redg_min*/ + +} /* end of pin tl_o[65] */ + +pin("tl_o[64]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.153409 ; + min_capacitance : 0.000000 ; + max_fanout : 50.000000 ; + function : "0" ; + capacitance : 0.009004 ; + + /* Other user defined attributes. */ + original_pin : tl_o[64]; +} /* end of pin tl_o[64] */ + +pin("tl_o[63]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.153409 ; + min_capacitance : 0.000000 ; + max_fanout : 50.000000 ; + function : "0" ; + capacitance : 0.009004 ; + + /* Other user defined attributes. */ + original_pin : tl_o[63]; +} /* end of pin tl_o[63] */ + +pin("tl_o[62]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002088 ; + + /* Other user defined attributes. */ + original_pin : tl_o[62]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011"); + values ( "0.048389, 0.201372, 0.376697, 0.699413, 1.344843",\ + "0.134717, 0.288547, 0.463802, 0.786127, 1.430777",\ + "0.217972, 0.376674, 0.551758, 0.873749, 1.517732",\ + "0.275938, 0.441068, 0.615873, 0.937662, 1.581241",\ + "0.576253, 0.790939, 0.966256, 1.286403, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011"); + values ( "0.024378, 0.300079, 0.633266, 1.249698, 2.482563",\ + "0.028867, 0.301069, 0.635212, 1.249698, 2.482563",\ + "0.041784, 0.303321, 0.635248, 1.249698, 2.482563",\ + "0.053694, 0.306596, 0.635350, 1.249698, 2.482563",\ + "0.129380, 0.344908, 0.641605, 1.252253, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011"); + values ( "0.068004, 0.173028, 0.284443, 0.488532, 0.896711",\ + "0.155415, 0.260346, 0.371724, 0.575838, 0.984064",\ + "0.235777, 0.340680, 0.451751, 0.655866, 1.064096",\ + "0.292479, 0.398229, 0.509294, 0.713111, 1.120744",\ + "0.586381, 0.701567, 0.812926, 1.016124, 1.422520"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011"); + values ( "0.024753, 0.187586, 0.387908, 0.760055, 1.504347",\ + "0.024753, 0.187732, 0.388412, 0.760055, 1.504347",\ + "0.025828, 0.187732, 0.388412, 0.760055, 1.504347",\ + "0.027889, 0.187732, 0.388412, 0.760055, 1.504347",\ + "0.046464, 0.191695, 0.388412, 0.760055, 1.504627"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[62]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011"); + values ( "0.048389, 0.201372, 0.376697, 0.699413, 1.344843",\ + "0.134717, 0.288547, 0.463802, 0.786127, 1.430777",\ + "0.217972, 0.376674, 0.551758, 0.873749, 1.517732",\ + "0.275938, 0.441068, 0.615873, 0.937662, 1.581241",\ + "0.576253, 0.790939, 0.966256, 1.286403, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011"); + values ( "0.024378, 0.300079, 0.633266, 1.248468, 2.473548",\ + "0.028867, 0.301069, 0.635212, 1.248468, 2.473548",\ + "0.041784, 0.303321, 0.635248, 1.248544, 2.473548",\ + "0.053694, 0.306596, 0.635350, 1.249288, 2.473548",\ + "0.129380, 0.344908, 0.641605, 1.252253, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011"); + values ( "0.068004, 0.173028, 0.284443, 0.488532, 0.896711",\ + "0.155415, 0.260346, 0.371724, 0.575838, 0.984064",\ + "0.235777, 0.340680, 0.451751, 0.655866, 1.064096",\ + "0.292479, 0.398229, 0.509294, 0.713111, 1.120744",\ + "0.586381, 0.701567, 0.812926, 1.016124, 1.422520"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011"); + values ( "0.024753, 0.186786, 0.386401, 0.757824, 1.500670",\ + "0.024753, 0.186786, 0.386401, 0.757824, 1.500670",\ + "0.025828, 0.186786, 0.386401, 0.757824, 1.500670",\ + "0.027889, 0.187397, 0.386858, 0.758726, 1.502461",\ + "0.046464, 0.191695, 0.386930, 0.759496, 1.504627"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[62]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024378, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.218049, 0.171947, 0.141734, 0.130380, 0.144005",\ + "0.225343, 0.179241, 0.149028, 0.137673, 0.151299",\ + "0.298206, 0.252060, 0.221844, 0.210487, 0.224097",\ + "0.392136, 0.345682, 0.315442, 0.304067, 0.317572",\ + "0.819837, 0.772019, 0.741401, 0.729820, 0.742723"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024753, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.263674, 0.188357, 0.120223, 0.097297, 0.160585",\ + "0.270643, 0.195326, 0.127193, 0.104267, 0.167554",\ + "0.342134, 0.266818, 0.198684, 0.175758, 0.239045",\ + "0.448695, 0.373390, 0.305321, 0.282500, 0.346742",\ + "0.946962, 0.871764, 0.804107, 0.782042, 0.853404"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[62]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024378, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139030, -0.096614, -0.062124, -0.022751, 0.282672",\ + "-0.146290, -0.103874, -0.069385, -0.030012, 0.275412",\ + "-0.217578, -0.175163, -0.140673, -0.101300, 0.204124",\ + "-0.305582, -0.263210, -0.228618, -0.191228, 0.089586",\ + "-0.705049, -0.662905, -0.627627, -0.603487, -0.487141"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024753, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.129024, -0.063245, -0.005781, 0.036127, 0.257073",\ + "-0.136957, -0.071178, -0.013715, 0.028194, 0.249139",\ + "-0.213653, -0.147874, -0.090410, -0.048501, 0.172444",\ + "-0.315404, -0.249338, -0.191464, -0.149444, 0.070790",\ + "-0.774971, -0.707116, -0.646741, -0.604032, -0.387962"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[62]_hldr*/ + +} /* end of pin tl_o[62] */ + +pin("tl_o[61]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.153409 ; + min_capacitance : 0.000000 ; + max_fanout : 50.000000 ; + function : "0" ; + capacitance : 0.009004 ; + + /* Other user defined attributes. */ + original_pin : tl_o[61]; +} /* end of pin tl_o[61] */ + +pin("tl_o[60]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.153409 ; + min_capacitance : 0.000000 ; + max_fanout : 50.000000 ; + function : "0" ; + capacitance : 0.009004 ; + + /* Other user defined attributes. */ + original_pin : tl_o[60]; +} /* end of pin tl_o[60] */ + +pin("tl_o[59]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.153409 ; + min_capacitance : 0.000000 ; + max_fanout : 50.000000 ; + function : "0" ; + capacitance : 0.009004 ; + + /* Other user defined attributes. */ + original_pin : tl_o[59]; +} /* end of pin tl_o[59] */ + +pin("tl_o[58]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.003360 ; + + /* Other user defined attributes. */ + original_pin : tl_o[58]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011"); + values ( "0.051828, 0.203934, 0.378621, 0.700695, 1.344843",\ + "0.138345, 0.291109, 0.465724, 0.787408, 1.430777",\ + "0.222447, 0.379233, 0.553677, 0.875029, 1.517732",\ + "0.281266, 0.443623, 0.617791, 0.938941, 1.581241",\ + "0.586734, 0.793508, 0.968165, 1.287675, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011"); + values ( "0.028994, 0.304939, 0.636940, 1.252148, 2.482564",\ + "0.033002, 0.305957, 0.638867, 1.252148, 2.482564",\ + "0.045411, 0.308165, 0.638904, 1.252148, 2.482564",\ + "0.057383, 0.311375, 0.639010, 1.252148, 2.482564",\ + "0.134005, 0.349063, 0.645245, 1.254679, 2.482564"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011"); + values ( "0.070957, 0.174574, 0.285576, 0.489260, 0.896627",\ + "0.158358, 0.261892, 0.372857, 0.576565, 0.983980",\ + "0.238767, 0.342220, 0.452884, 0.656593, 1.064012",\ + "0.295587, 0.399770, 0.510425, 0.713837, 1.120660",\ + "0.590723, 0.703115, 0.814054, 1.016848, 1.422437"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011"); + values ( "0.027799, 0.190353, 0.389974, 0.761380, 1.504194",\ + "0.027799, 0.190507, 0.390474, 0.761380, 1.504194",\ + "0.028742, 0.190507, 0.390474, 0.761380, 1.504194",\ + "0.030673, 0.190507, 0.390474, 0.761380, 1.504194",\ + "0.048664, 0.194365, 0.390474, 0.761380, 1.504474"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[58]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011"); + values ( "0.051828, 0.203934, 0.378621, 0.700695, 1.344843",\ + "0.138345, 0.291109, 0.465724, 0.787408, 1.430777",\ + "0.222447, 0.379233, 0.553677, 0.875029, 1.517732",\ + "0.281266, 0.443623, 0.617791, 0.938941, 1.581241",\ + "0.586734, 0.793508, 0.968165, 1.287675, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011"); + values ( "0.028994, 0.304939, 0.636940, 1.250905, 2.473548",\ + "0.033002, 0.305957, 0.638867, 1.250905, 2.473548",\ + "0.045411, 0.308165, 0.638904, 1.250981, 2.473548",\ + "0.057383, 0.311375, 0.639010, 1.251728, 2.473548",\ + "0.134005, 0.349063, 0.645245, 1.254679, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011"); + values ( "0.070957, 0.174574, 0.285576, 0.489260, 0.896627",\ + "0.158358, 0.261892, 0.372857, 0.576565, 0.983980",\ + "0.238767, 0.342220, 0.452884, 0.656593, 1.064012",\ + "0.295587, 0.399770, 0.510425, 0.713837, 1.120660",\ + "0.590723, 0.703115, 0.814054, 1.016848, 1.422437"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011"); + values ( "0.027799, 0.189542, 0.388462, 0.759147, 1.500517",\ + "0.027799, 0.189542, 0.388462, 0.759147, 1.500517",\ + "0.028742, 0.189542, 0.388462, 0.759147, 1.500517",\ + "0.030673, 0.190148, 0.388922, 0.760051, 1.502309",\ + "0.048664, 0.194365, 0.388998, 0.760823, 1.504474"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[58]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.028994, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.218252, 0.172323, 0.142124, 0.130780, 0.144465",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.027799, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.252073, 0.176751, 0.108592, 0.085625, 0.148539",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[58]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.028994, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.150180, -0.107763, -0.073276, -0.033852, 0.272195",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.027799, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.165228, -0.099313, -0.041654, 0.000307, 0.220914",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[58]_hldr*/ + +} /* end of pin tl_o[58] */ + +pin("tl_o[57]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002160 ; + + /* Other user defined attributes. */ + original_pin : tl_o[57]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011"); + values ( "0.048582, 0.201516, 0.376805, 0.699484, 1.344843",\ + "0.134920, 0.288690, 0.463910, 0.786199, 1.430777",\ + "0.218223, 0.376818, 0.551865, 0.873821, 1.517732",\ + "0.276237, 0.441212, 0.615981, 0.937734, 1.581241",\ + "0.576841, 0.791083, 0.966363, 1.286475, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011"); + values ( "0.024637, 0.300352, 0.633472, 1.249836, 2.482563",\ + "0.029099, 0.301343, 0.635417, 1.249836, 2.482563",\ + "0.041988, 0.303593, 0.635453, 1.249836, 2.482563",\ + "0.053901, 0.306864, 0.635555, 1.249836, 2.482563",\ + "0.129639, 0.345141, 0.641809, 1.252389, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011"); + values ( "0.068110, 0.173083, 0.284476, 0.488542, 0.896675",\ + "0.155520, 0.260402, 0.371756, 0.575847, 0.984028",\ + "0.235884, 0.340735, 0.451783, 0.655876, 1.064060",\ + "0.292590, 0.398284, 0.509326, 0.713120, 1.120708",\ + "0.586537, 0.701623, 0.812958, 1.016134, 1.422485"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011"); + values ( "0.024862, 0.187685, 0.387967, 0.760072, 1.504282",\ + "0.024862, 0.187831, 0.388471, 0.760072, 1.504282",\ + "0.025932, 0.187831, 0.388471, 0.760072, 1.504282",\ + "0.027989, 0.187831, 0.388471, 0.760072, 1.504282",\ + "0.046543, 0.191790, 0.388471, 0.760072, 1.504562"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[57]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011"); + values ( "0.048582, 0.201516, 0.376805, 0.699484, 1.344843",\ + "0.134920, 0.288690, 0.463910, 0.786199, 1.430777",\ + "0.218223, 0.376818, 0.551865, 0.873821, 1.517732",\ + "0.276237, 0.441212, 0.615981, 0.937734, 1.581241",\ + "0.576841, 0.791083, 0.966363, 1.286475, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011"); + values ( "0.024637, 0.300352, 0.633472, 1.248605, 2.473548",\ + "0.029099, 0.301343, 0.635417, 1.248605, 2.473548",\ + "0.041988, 0.303593, 0.635453, 1.248680, 2.473548",\ + "0.053901, 0.306864, 0.635555, 1.249425, 2.473548",\ + "0.129639, 0.345141, 0.641809, 1.252389, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011"); + values ( "0.068110, 0.173083, 0.284476, 0.488542, 0.896675",\ + "0.155520, 0.260402, 0.371756, 0.575847, 0.984028",\ + "0.235884, 0.340735, 0.451783, 0.655876, 1.064060",\ + "0.292590, 0.398284, 0.509326, 0.713120, 1.120708",\ + "0.586537, 0.701623, 0.812958, 1.016134, 1.422485"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011"); + values ( "0.024862, 0.186885, 0.386460, 0.757841, 1.500604",\ + "0.024862, 0.186885, 0.386460, 0.757841, 1.500604",\ + "0.025932, 0.186885, 0.386460, 0.757841, 1.500604",\ + "0.027989, 0.187495, 0.386917, 0.758743, 1.502396",\ + "0.046543, 0.191790, 0.386989, 0.759514, 1.504562"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[57]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024637, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.216235, 0.170306, 0.140106, 0.128763, 0.142448",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024862, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.250736, 0.175414, 0.107255, 0.084288, 0.147202",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[57]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024637, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.148162, -0.105745, -0.071258, -0.031835, 0.274212",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024862, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.163891, -0.097976, -0.040317, 0.001644, 0.222251",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[57]_hldr*/ + +} /* end of pin tl_o[57] */ + +pin("tl_o[56]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000498 ; + + /* Other user defined attributes. */ + original_pin : tl_o[56]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.043170, 0.198167, 0.374291, 0.697809, 1.344843",\ + "0.129019, 0.285342, 0.461399, 0.784525, 1.430777",\ + "0.210407, 0.373473, 0.549357, 0.872149, 1.517732",\ + "0.266777, 0.437873, 0.613474, 0.936063, 1.581241",\ + "0.557497, 0.787726, 0.963869, 1.284812, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.018489, 0.294000, 0.628670, 1.246634, 2.482563",\ + "0.023601, 0.294955, 0.630640, 1.246634, 2.482563",\ + "0.036987, 0.297263, 0.630676, 1.246634, 2.482563",\ + "0.048667, 0.300618, 0.630773, 1.246634, 2.482563",\ + "0.122402, 0.339712, 0.637052, 1.249217, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.063051, 0.171050, 0.282984, 0.487580, 0.896773",\ + "0.150620, 0.258370, 0.370264, 0.574885, 0.984126",\ + "0.230770, 0.338711, 0.450291, 0.654914, 1.064158",\ + "0.287173, 0.396259, 0.507836, 0.712159, 1.120806",\ + "0.578289, 0.699588, 0.811473, 1.015176, 1.422582"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.020634, 0.184048, 0.385247, 0.758318, 1.504460",\ + "0.020634, 0.184183, 0.385754, 0.758318, 1.504460",\ + "0.021564, 0.184183, 0.385754, 0.758318, 1.504460",\ + "0.023878, 0.184183, 0.385754, 0.758318, 1.504460",\ + "0.042695, 0.188280, 0.385754, 0.758318, 1.504740"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[56]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.043170, 0.198167, 0.374291, 0.697809, 1.344843",\ + "0.129019, 0.285342, 0.461399, 0.784525, 1.430777",\ + "0.210407, 0.373473, 0.549357, 0.872149, 1.517732",\ + "0.266777, 0.437873, 0.613474, 0.936063, 1.581241",\ + "0.557497, 0.787726, 0.963869, 1.284812, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.018489, 0.294000, 0.628670, 1.245420, 2.473548",\ + "0.023601, 0.294955, 0.630640, 1.245420, 2.473548",\ + "0.036987, 0.297263, 0.630676, 1.245495, 2.473548",\ + "0.048667, 0.300618, 0.630773, 1.246236, 2.473548",\ + "0.122402, 0.339712, 0.637052, 1.249217, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.063051, 0.171050, 0.282984, 0.487580, 0.896773",\ + "0.150620, 0.258370, 0.370264, 0.574885, 0.984126",\ + "0.230770, 0.338711, 0.450291, 0.654914, 1.064158",\ + "0.287173, 0.396259, 0.507836, 0.712159, 1.120806",\ + "0.578289, 0.699588, 0.811473, 1.015176, 1.422582"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.020634, 0.183263, 0.383745, 0.756091, 1.500782",\ + "0.020634, 0.183263, 0.383745, 0.756091, 1.500782",\ + "0.021564, 0.183263, 0.383745, 0.756091, 1.500782",\ + "0.023878, 0.183878, 0.384198, 0.756990, 1.502574",\ + "0.042695, 0.188280, 0.384266, 0.757757, 1.504740"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[56]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018489, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.213388, 0.167459, 0.137260, 0.125916, 0.139601",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020634, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.248811, 0.173490, 0.105331, 0.082363, 0.145277",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[56]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018489, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.145316, -0.102899, -0.068412, -0.028988, 0.277059",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020634, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.161967, -0.096052, -0.038393, 0.003568, 0.224175",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[56]_hldr*/ + +} /* end of pin tl_o[56] */ + +pin("tl_o[55]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000498 ; + + /* Other user defined attributes. */ + original_pin : tl_o[55]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.043170, 0.198167, 0.374291, 0.697809, 1.344843",\ + "0.129019, 0.285342, 0.461399, 0.784525, 1.430777",\ + "0.210407, 0.373473, 0.549357, 0.872149, 1.517732",\ + "0.266777, 0.437873, 0.613474, 0.936063, 1.581241",\ + "0.557497, 0.787726, 0.963869, 1.284812, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.018489, 0.294000, 0.628670, 1.246634, 2.482563",\ + "0.023601, 0.294955, 0.630640, 1.246634, 2.482563",\ + "0.036987, 0.297263, 0.630676, 1.246634, 2.482563",\ + "0.048667, 0.300618, 0.630773, 1.246634, 2.482563",\ + "0.122402, 0.339712, 0.637052, 1.249217, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.063051, 0.171050, 0.282984, 0.487580, 0.896773",\ + "0.150620, 0.258370, 0.370264, 0.574885, 0.984126",\ + "0.230770, 0.338711, 0.450291, 0.654914, 1.064158",\ + "0.287173, 0.396259, 0.507836, 0.712159, 1.120806",\ + "0.578289, 0.699588, 0.811473, 1.015176, 1.422582"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.020634, 0.184048, 0.385247, 0.758318, 1.504460",\ + "0.020634, 0.184183, 0.385754, 0.758318, 1.504460",\ + "0.021564, 0.184183, 0.385754, 0.758318, 1.504460",\ + "0.023878, 0.184183, 0.385754, 0.758318, 1.504460",\ + "0.042695, 0.188280, 0.385754, 0.758318, 1.504740"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[55]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.043170, 0.198167, 0.374291, 0.697809, 1.344843",\ + "0.129019, 0.285342, 0.461399, 0.784525, 1.430777",\ + "0.210407, 0.373473, 0.549357, 0.872149, 1.517732",\ + "0.266777, 0.437873, 0.613474, 0.936063, 1.581241",\ + "0.557497, 0.787726, 0.963869, 1.284812, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.018489, 0.294000, 0.628670, 1.245420, 2.473548",\ + "0.023601, 0.294955, 0.630640, 1.245420, 2.473548",\ + "0.036987, 0.297263, 0.630676, 1.245495, 2.473548",\ + "0.048667, 0.300618, 0.630773, 1.246236, 2.473548",\ + "0.122402, 0.339712, 0.637052, 1.249217, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.063051, 0.171050, 0.282984, 0.487580, 0.896773",\ + "0.150620, 0.258370, 0.370264, 0.574885, 0.984126",\ + "0.230770, 0.338711, 0.450291, 0.654914, 1.064158",\ + "0.287173, 0.396259, 0.507836, 0.712159, 1.120806",\ + "0.578289, 0.699588, 0.811473, 1.015176, 1.422582"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.020634, 0.183263, 0.383745, 0.756091, 1.500782",\ + "0.020634, 0.183263, 0.383745, 0.756091, 1.500782",\ + "0.021564, 0.183263, 0.383745, 0.756091, 1.500782",\ + "0.023878, 0.183878, 0.384198, 0.756990, 1.502574",\ + "0.042695, 0.188280, 0.384266, 0.757757, 1.504740"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[55]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018489, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.213388, 0.167459, 0.137260, 0.125916, 0.139601",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020634, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.248811, 0.173490, 0.105331, 0.082363, 0.145277",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[55]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018489, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.145316, -0.102899, -0.068412, -0.028988, 0.277059",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020634, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.161967, -0.096052, -0.038393, 0.003568, 0.224175",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[55]_hldr*/ + +} /* end of pin tl_o[55] */ + +pin("tl_o[54]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000498 ; + + /* Other user defined attributes. */ + original_pin : tl_o[54]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.043170, 0.198167, 0.374291, 0.697809, 1.344843",\ + "0.129019, 0.285342, 0.461399, 0.784525, 1.430777",\ + "0.210407, 0.373473, 0.549357, 0.872149, 1.517732",\ + "0.266777, 0.437873, 0.613474, 0.936063, 1.581241",\ + "0.557497, 0.787726, 0.963869, 1.284812, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.018489, 0.294000, 0.628670, 1.246634, 2.482563",\ + "0.023601, 0.294955, 0.630640, 1.246634, 2.482563",\ + "0.036987, 0.297263, 0.630676, 1.246634, 2.482563",\ + "0.048667, 0.300618, 0.630773, 1.246634, 2.482563",\ + "0.122402, 0.339712, 0.637052, 1.249217, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.063051, 0.171050, 0.282984, 0.487580, 0.896773",\ + "0.150620, 0.258370, 0.370264, 0.574885, 0.984126",\ + "0.230770, 0.338711, 0.450291, 0.654914, 1.064158",\ + "0.287173, 0.396259, 0.507836, 0.712159, 1.120806",\ + "0.578289, 0.699588, 0.811473, 1.015176, 1.422582"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.020634, 0.184048, 0.385247, 0.758318, 1.504460",\ + "0.020634, 0.184183, 0.385754, 0.758318, 1.504460",\ + "0.021564, 0.184183, 0.385754, 0.758318, 1.504460",\ + "0.023878, 0.184183, 0.385754, 0.758318, 1.504460",\ + "0.042695, 0.188280, 0.385754, 0.758318, 1.504740"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[54]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.043170, 0.198167, 0.374291, 0.697809, 1.344843",\ + "0.129019, 0.285342, 0.461399, 0.784525, 1.430777",\ + "0.210407, 0.373473, 0.549357, 0.872149, 1.517732",\ + "0.266777, 0.437873, 0.613474, 0.936063, 1.581241",\ + "0.557497, 0.787726, 0.963869, 1.284812, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.018489, 0.294000, 0.628670, 1.245420, 2.473548",\ + "0.023601, 0.294955, 0.630640, 1.245420, 2.473548",\ + "0.036987, 0.297263, 0.630676, 1.245495, 2.473548",\ + "0.048667, 0.300618, 0.630773, 1.246236, 2.473548",\ + "0.122402, 0.339712, 0.637052, 1.249217, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.063051, 0.171050, 0.282984, 0.487580, 0.896773",\ + "0.150620, 0.258370, 0.370264, 0.574885, 0.984126",\ + "0.230770, 0.338711, 0.450291, 0.654914, 1.064158",\ + "0.287173, 0.396259, 0.507836, 0.712159, 1.120806",\ + "0.578289, 0.699588, 0.811473, 1.015176, 1.422582"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.020634, 0.183263, 0.383745, 0.756091, 1.500782",\ + "0.020634, 0.183263, 0.383745, 0.756091, 1.500782",\ + "0.021564, 0.183263, 0.383745, 0.756091, 1.500782",\ + "0.023878, 0.183878, 0.384198, 0.756990, 1.502574",\ + "0.042695, 0.188280, 0.384266, 0.757757, 1.504740"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[54]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018489, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.213388, 0.167459, 0.137260, 0.125916, 0.139601",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020634, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.248811, 0.173490, 0.105331, 0.082363, 0.145277",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[54]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018489, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.145316, -0.102899, -0.068412, -0.028988, 0.277059",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020634, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.161967, -0.096052, -0.038393, 0.003568, 0.224175",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[54]_hldr*/ + +} /* end of pin tl_o[54] */ + +pin("tl_o[53]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000498 ; + + /* Other user defined attributes. */ + original_pin : tl_o[53]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.043170, 0.198167, 0.374291, 0.697809, 1.344843",\ + "0.129019, 0.285342, 0.461399, 0.784525, 1.430777",\ + "0.210407, 0.373473, 0.549357, 0.872149, 1.517732",\ + "0.266777, 0.437873, 0.613474, 0.936063, 1.581241",\ + "0.557497, 0.787726, 0.963869, 1.284812, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.018489, 0.294000, 0.628670, 1.246634, 2.482563",\ + "0.023601, 0.294955, 0.630640, 1.246634, 2.482563",\ + "0.036987, 0.297263, 0.630676, 1.246634, 2.482563",\ + "0.048667, 0.300618, 0.630773, 1.246634, 2.482563",\ + "0.122402, 0.339712, 0.637052, 1.249217, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.063051, 0.171050, 0.282984, 0.487580, 0.896773",\ + "0.150620, 0.258370, 0.370264, 0.574885, 0.984126",\ + "0.230770, 0.338711, 0.450291, 0.654914, 1.064158",\ + "0.287173, 0.396259, 0.507836, 0.712159, 1.120806",\ + "0.578289, 0.699588, 0.811473, 1.015176, 1.422582"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.020634, 0.184048, 0.385247, 0.758318, 1.504460",\ + "0.020634, 0.184183, 0.385754, 0.758318, 1.504460",\ + "0.021564, 0.184183, 0.385754, 0.758318, 1.504460",\ + "0.023878, 0.184183, 0.385754, 0.758318, 1.504460",\ + "0.042695, 0.188280, 0.385754, 0.758318, 1.504740"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[53]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.043170, 0.198167, 0.374291, 0.697809, 1.344843",\ + "0.129019, 0.285342, 0.461399, 0.784525, 1.430777",\ + "0.210407, 0.373473, 0.549357, 0.872149, 1.517732",\ + "0.266777, 0.437873, 0.613474, 0.936063, 1.581241",\ + "0.557497, 0.787726, 0.963869, 1.284812, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.018489, 0.294000, 0.628670, 1.245420, 2.473548",\ + "0.023601, 0.294955, 0.630640, 1.245420, 2.473548",\ + "0.036987, 0.297263, 0.630676, 1.245495, 2.473548",\ + "0.048667, 0.300618, 0.630773, 1.246236, 2.473548",\ + "0.122402, 0.339712, 0.637052, 1.249217, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.063051, 0.171050, 0.282984, 0.487580, 0.896773",\ + "0.150620, 0.258370, 0.370264, 0.574885, 0.984126",\ + "0.230770, 0.338711, 0.450291, 0.654914, 1.064158",\ + "0.287173, 0.396259, 0.507836, 0.712159, 1.120806",\ + "0.578289, 0.699588, 0.811473, 1.015176, 1.422582"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.020634, 0.183263, 0.383745, 0.756091, 1.500782",\ + "0.020634, 0.183263, 0.383745, 0.756091, 1.500782",\ + "0.021564, 0.183263, 0.383745, 0.756091, 1.500782",\ + "0.023878, 0.183878, 0.384198, 0.756990, 1.502574",\ + "0.042695, 0.188280, 0.384266, 0.757757, 1.504740"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[53]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018489, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.213388, 0.167459, 0.137260, 0.125916, 0.139601",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020634, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.248811, 0.173490, 0.105331, 0.082363, 0.145277",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[53]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018489, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.145316, -0.102899, -0.068412, -0.028988, 0.277059",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020634, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.161967, -0.096052, -0.038393, 0.003568, 0.224175",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[53]_hldr*/ + +} /* end of pin tl_o[53] */ + +pin("tl_o[52]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000498 ; + + /* Other user defined attributes. */ + original_pin : tl_o[52]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.043170, 0.198167, 0.374291, 0.697809, 1.344843",\ + "0.129019, 0.285342, 0.461399, 0.784525, 1.430777",\ + "0.210407, 0.373473, 0.549357, 0.872149, 1.517732",\ + "0.266777, 0.437873, 0.613474, 0.936063, 1.581241",\ + "0.557497, 0.787726, 0.963869, 1.284812, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.018489, 0.294000, 0.628670, 1.246634, 2.482563",\ + "0.023601, 0.294955, 0.630640, 1.246634, 2.482563",\ + "0.036987, 0.297263, 0.630676, 1.246634, 2.482563",\ + "0.048667, 0.300618, 0.630773, 1.246634, 2.482563",\ + "0.122402, 0.339712, 0.637052, 1.249217, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.063051, 0.171050, 0.282984, 0.487580, 0.896773",\ + "0.150620, 0.258370, 0.370264, 0.574885, 0.984126",\ + "0.230770, 0.338711, 0.450291, 0.654914, 1.064158",\ + "0.287173, 0.396259, 0.507836, 0.712159, 1.120806",\ + "0.578289, 0.699588, 0.811473, 1.015176, 1.422582"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.020634, 0.184048, 0.385247, 0.758318, 1.504460",\ + "0.020634, 0.184183, 0.385754, 0.758318, 1.504460",\ + "0.021564, 0.184183, 0.385754, 0.758318, 1.504460",\ + "0.023878, 0.184183, 0.385754, 0.758318, 1.504460",\ + "0.042695, 0.188280, 0.385754, 0.758318, 1.504740"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[52]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.043170, 0.198167, 0.374291, 0.697809, 1.344843",\ + "0.129019, 0.285342, 0.461399, 0.784525, 1.430777",\ + "0.210407, 0.373473, 0.549357, 0.872149, 1.517732",\ + "0.266777, 0.437873, 0.613474, 0.936063, 1.581241",\ + "0.557497, 0.787726, 0.963869, 1.284812, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.018489, 0.294000, 0.628670, 1.245420, 2.473548",\ + "0.023601, 0.294955, 0.630640, 1.245420, 2.473548",\ + "0.036987, 0.297263, 0.630676, 1.245495, 2.473548",\ + "0.048667, 0.300618, 0.630773, 1.246236, 2.473548",\ + "0.122402, 0.339712, 0.637052, 1.249217, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.063051, 0.171050, 0.282984, 0.487580, 0.896773",\ + "0.150620, 0.258370, 0.370264, 0.574885, 0.984126",\ + "0.230770, 0.338711, 0.450291, 0.654914, 1.064158",\ + "0.287173, 0.396259, 0.507836, 0.712159, 1.120806",\ + "0.578289, 0.699588, 0.811473, 1.015176, 1.422582"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.020634, 0.183263, 0.383745, 0.756091, 1.500782",\ + "0.020634, 0.183263, 0.383745, 0.756091, 1.500782",\ + "0.021564, 0.183263, 0.383745, 0.756091, 1.500782",\ + "0.023878, 0.183878, 0.384198, 0.756990, 1.502574",\ + "0.042695, 0.188280, 0.384266, 0.757757, 1.504740"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[52]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018489, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.213388, 0.167459, 0.137260, 0.125916, 0.139601",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020634, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.248811, 0.173490, 0.105331, 0.082363, 0.145277",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[52]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018489, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.145316, -0.102899, -0.068412, -0.028988, 0.277059",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020634, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.161967, -0.096052, -0.038393, 0.003568, 0.224175",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[52]_hldr*/ + +} /* end of pin tl_o[52] */ + +pin("tl_o[51]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000498 ; + + /* Other user defined attributes. */ + original_pin : tl_o[51]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.043170, 0.198167, 0.374291, 0.697809, 1.344843",\ + "0.129019, 0.285342, 0.461399, 0.784525, 1.430777",\ + "0.210407, 0.373473, 0.549357, 0.872149, 1.517732",\ + "0.266777, 0.437873, 0.613474, 0.936063, 1.581241",\ + "0.557497, 0.787726, 0.963869, 1.284812, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.018489, 0.294000, 0.628670, 1.246634, 2.482563",\ + "0.023601, 0.294955, 0.630640, 1.246634, 2.482563",\ + "0.036987, 0.297263, 0.630676, 1.246634, 2.482563",\ + "0.048667, 0.300618, 0.630773, 1.246634, 2.482563",\ + "0.122402, 0.339712, 0.637052, 1.249217, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.063051, 0.171050, 0.282984, 0.487580, 0.896773",\ + "0.150620, 0.258370, 0.370264, 0.574885, 0.984126",\ + "0.230770, 0.338711, 0.450291, 0.654914, 1.064158",\ + "0.287173, 0.396259, 0.507836, 0.712159, 1.120806",\ + "0.578289, 0.699588, 0.811473, 1.015176, 1.422582"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.020634, 0.184048, 0.385247, 0.758318, 1.504460",\ + "0.020634, 0.184183, 0.385754, 0.758318, 1.504460",\ + "0.021564, 0.184183, 0.385754, 0.758318, 1.504460",\ + "0.023878, 0.184183, 0.385754, 0.758318, 1.504460",\ + "0.042695, 0.188280, 0.385754, 0.758318, 1.504740"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[51]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.043170, 0.198167, 0.374291, 0.697809, 1.344843",\ + "0.129019, 0.285342, 0.461399, 0.784525, 1.430777",\ + "0.210407, 0.373473, 0.549357, 0.872149, 1.517732",\ + "0.266777, 0.437873, 0.613474, 0.936063, 1.581241",\ + "0.557497, 0.787726, 0.963869, 1.284812, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.018489, 0.294000, 0.628670, 1.245420, 2.473548",\ + "0.023601, 0.294955, 0.630640, 1.245420, 2.473548",\ + "0.036987, 0.297263, 0.630676, 1.245495, 2.473548",\ + "0.048667, 0.300618, 0.630773, 1.246236, 2.473548",\ + "0.122402, 0.339712, 0.637052, 1.249217, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.063051, 0.171050, 0.282984, 0.487580, 0.896773",\ + "0.150620, 0.258370, 0.370264, 0.574885, 0.984126",\ + "0.230770, 0.338711, 0.450291, 0.654914, 1.064158",\ + "0.287173, 0.396259, 0.507836, 0.712159, 1.120806",\ + "0.578289, 0.699588, 0.811473, 1.015176, 1.422582"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.020634, 0.183263, 0.383745, 0.756091, 1.500782",\ + "0.020634, 0.183263, 0.383745, 0.756091, 1.500782",\ + "0.021564, 0.183263, 0.383745, 0.756091, 1.500782",\ + "0.023878, 0.183878, 0.384198, 0.756990, 1.502574",\ + "0.042695, 0.188280, 0.384266, 0.757757, 1.504740"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[51]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018489, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.213388, 0.167459, 0.137260, 0.125916, 0.139601",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020634, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.248811, 0.173490, 0.105331, 0.082363, 0.145277",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[51]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018489, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.145316, -0.102899, -0.068412, -0.028988, 0.277059",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020634, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.161967, -0.096052, -0.038393, 0.003568, 0.224175",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[51]_hldr*/ + +} /* end of pin tl_o[51] */ + +pin("tl_o[50]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000498 ; + + /* Other user defined attributes. */ + original_pin : tl_o[50]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.043170, 0.198167, 0.374291, 0.697809, 1.344843",\ + "0.129019, 0.285342, 0.461399, 0.784525, 1.430777",\ + "0.210407, 0.373473, 0.549357, 0.872149, 1.517732",\ + "0.266777, 0.437873, 0.613474, 0.936063, 1.581241",\ + "0.557497, 0.787726, 0.963869, 1.284812, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.018489, 0.294000, 0.628670, 1.246634, 2.482563",\ + "0.023601, 0.294955, 0.630640, 1.246634, 2.482563",\ + "0.036987, 0.297263, 0.630676, 1.246634, 2.482563",\ + "0.048667, 0.300618, 0.630773, 1.246634, 2.482563",\ + "0.122402, 0.339712, 0.637052, 1.249217, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.063051, 0.171050, 0.282984, 0.487580, 0.896773",\ + "0.150620, 0.258370, 0.370264, 0.574885, 0.984126",\ + "0.230770, 0.338711, 0.450291, 0.654914, 1.064158",\ + "0.287173, 0.396259, 0.507836, 0.712159, 1.120806",\ + "0.578289, 0.699588, 0.811473, 1.015176, 1.422582"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.020634, 0.184048, 0.385247, 0.758318, 1.504460",\ + "0.020634, 0.184183, 0.385754, 0.758318, 1.504460",\ + "0.021564, 0.184183, 0.385754, 0.758318, 1.504460",\ + "0.023878, 0.184183, 0.385754, 0.758318, 1.504460",\ + "0.042695, 0.188280, 0.385754, 0.758318, 1.504740"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[50]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.043170, 0.198167, 0.374291, 0.697809, 1.344843",\ + "0.129019, 0.285342, 0.461399, 0.784525, 1.430777",\ + "0.210407, 0.373473, 0.549357, 0.872149, 1.517732",\ + "0.266777, 0.437873, 0.613474, 0.936063, 1.581241",\ + "0.557497, 0.787726, 0.963869, 1.284812, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.018489, 0.294000, 0.628670, 1.245420, 2.473548",\ + "0.023601, 0.294955, 0.630640, 1.245420, 2.473548",\ + "0.036987, 0.297263, 0.630676, 1.245495, 2.473548",\ + "0.048667, 0.300618, 0.630773, 1.246236, 2.473548",\ + "0.122402, 0.339712, 0.637052, 1.249217, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.063051, 0.171050, 0.282984, 0.487580, 0.896773",\ + "0.150620, 0.258370, 0.370264, 0.574885, 0.984126",\ + "0.230770, 0.338711, 0.450291, 0.654914, 1.064158",\ + "0.287173, 0.396259, 0.507836, 0.712159, 1.120806",\ + "0.578289, 0.699588, 0.811473, 1.015176, 1.422582"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.020634, 0.183263, 0.383745, 0.756091, 1.500782",\ + "0.020634, 0.183263, 0.383745, 0.756091, 1.500782",\ + "0.021564, 0.183263, 0.383745, 0.756091, 1.500782",\ + "0.023878, 0.183878, 0.384198, 0.756990, 1.502574",\ + "0.042695, 0.188280, 0.384266, 0.757757, 1.504740"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[50]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018489, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.213388, 0.167459, 0.137260, 0.125916, 0.139601",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020634, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.248811, 0.173490, 0.105331, 0.082363, 0.145277",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[50]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018489, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.145316, -0.102899, -0.068412, -0.028988, 0.277059",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020634, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.161967, -0.096052, -0.038393, 0.003568, 0.224175",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[50]_hldr*/ + +} /* end of pin tl_o[50] */ + +pin("tl_o[49]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000498 ; + + /* Other user defined attributes. */ + original_pin : tl_o[49]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.043170, 0.198167, 0.374291, 0.697809, 1.344843",\ + "0.129019, 0.285342, 0.461399, 0.784525, 1.430777",\ + "0.210407, 0.373473, 0.549357, 0.872149, 1.517732",\ + "0.266777, 0.437873, 0.613474, 0.936063, 1.581241",\ + "0.557497, 0.787726, 0.963869, 1.284812, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.018489, 0.294000, 0.628670, 1.246634, 2.482563",\ + "0.023601, 0.294955, 0.630640, 1.246634, 2.482563",\ + "0.036987, 0.297263, 0.630676, 1.246634, 2.482563",\ + "0.048667, 0.300618, 0.630773, 1.246634, 2.482563",\ + "0.122402, 0.339712, 0.637052, 1.249217, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.063051, 0.171050, 0.282984, 0.487580, 0.896773",\ + "0.150620, 0.258370, 0.370264, 0.574885, 0.984126",\ + "0.230770, 0.338711, 0.450291, 0.654914, 1.064158",\ + "0.287173, 0.396259, 0.507836, 0.712159, 1.120806",\ + "0.578289, 0.699588, 0.811473, 1.015176, 1.422582"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.020634, 0.184048, 0.385247, 0.758318, 1.504460",\ + "0.020634, 0.184183, 0.385754, 0.758318, 1.504460",\ + "0.021564, 0.184183, 0.385754, 0.758318, 1.504460",\ + "0.023878, 0.184183, 0.385754, 0.758318, 1.504460",\ + "0.042695, 0.188280, 0.385754, 0.758318, 1.504740"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[49]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.043170, 0.198167, 0.374291, 0.697809, 1.344843",\ + "0.129019, 0.285342, 0.461399, 0.784525, 1.430777",\ + "0.210407, 0.373473, 0.549357, 0.872149, 1.517732",\ + "0.266777, 0.437873, 0.613474, 0.936063, 1.581241",\ + "0.557497, 0.787726, 0.963869, 1.284812, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.018489, 0.294000, 0.628670, 1.245420, 2.473548",\ + "0.023601, 0.294955, 0.630640, 1.245420, 2.473548",\ + "0.036987, 0.297263, 0.630676, 1.245495, 2.473548",\ + "0.048667, 0.300618, 0.630773, 1.246236, 2.473548",\ + "0.122402, 0.339712, 0.637052, 1.249217, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.063051, 0.171050, 0.282984, 0.487580, 0.896773",\ + "0.150620, 0.258370, 0.370264, 0.574885, 0.984126",\ + "0.230770, 0.338711, 0.450291, 0.654914, 1.064158",\ + "0.287173, 0.396259, 0.507836, 0.712159, 1.120806",\ + "0.578289, 0.699588, 0.811473, 1.015176, 1.422582"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.020634, 0.183263, 0.383745, 0.756091, 1.500782",\ + "0.020634, 0.183263, 0.383745, 0.756091, 1.500782",\ + "0.021564, 0.183263, 0.383745, 0.756091, 1.500782",\ + "0.023878, 0.183878, 0.384198, 0.756990, 1.502574",\ + "0.042695, 0.188280, 0.384266, 0.757757, 1.504740"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[49]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018489, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.213388, 0.167459, 0.137260, 0.125916, 0.139601",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020634, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.248811, 0.173490, 0.105331, 0.082363, 0.145277",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[49]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018489, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.145316, -0.102899, -0.068412, -0.028988, 0.277059",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020634, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.161967, -0.096052, -0.038393, 0.003568, 0.224175",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[49]_hldr*/ + +} /* end of pin tl_o[49] */ + +pin("tl_o[48]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.153409 ; + min_capacitance : 0.000000 ; + max_fanout : 50.000000 ; + function : "0" ; + capacitance : 0.009004 ; + + /* Other user defined attributes. */ + original_pin : tl_o[48]; +} /* end of pin tl_o[48] */ + +pin("tl_o[47]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002792 ; + + /* Other user defined attributes. */ + original_pin : tl_o[47]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011"); + values ( "0.050293, 0.202790, 0.377762, 0.700122, 1.344843",\ + "0.136725, 0.289965, 0.464866, 0.786836, 1.430777",\ + "0.220450, 0.378091, 0.552820, 0.874457, 1.517732",\ + "0.278888, 0.442483, 0.616935, 0.938370, 1.581241",\ + "0.582056, 0.792362, 0.967313, 1.287108, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011"); + values ( "0.026933, 0.302770, 0.635300, 1.251054, 2.482563",\ + "0.031156, 0.303775, 0.637236, 1.251054, 2.482563",\ + "0.043792, 0.306003, 0.637272, 1.251054, 2.482563",\ + "0.055737, 0.309242, 0.637376, 1.251054, 2.482563",\ + "0.131941, 0.347209, 0.643620, 1.253596, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011"); + values ( "0.069683, 0.173907, 0.285093, 0.488958, 0.896688",\ + "0.157089, 0.261225, 0.372374, 0.576263, 0.984041",\ + "0.237477, 0.341556, 0.452401, 0.656292, 1.064073",\ + "0.294246, 0.399105, 0.509943, 0.713536, 1.120720",\ + "0.588850, 0.702448, 0.813573, 1.016548, 1.422497"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011"); + values ( "0.026485, 0.189160, 0.389094, 0.760831, 1.504305",\ + "0.026485, 0.189310, 0.389596, 0.760831, 1.504305",\ + "0.027485, 0.189310, 0.389596, 0.760831, 1.504305",\ + "0.029472, 0.189310, 0.389596, 0.760831, 1.504305",\ + "0.047715, 0.193213, 0.389596, 0.760831, 1.504585"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[47]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011"); + values ( "0.050293, 0.202790, 0.377762, 0.700122, 1.344843",\ + "0.136725, 0.289965, 0.464866, 0.786836, 1.430777",\ + "0.220450, 0.378091, 0.552820, 0.874457, 1.517732",\ + "0.278888, 0.442483, 0.616935, 0.938370, 1.581241",\ + "0.582056, 0.792362, 0.967313, 1.287108, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011"); + values ( "0.026933, 0.302770, 0.635300, 1.249818, 2.473548",\ + "0.031156, 0.303775, 0.637236, 1.249818, 2.473548",\ + "0.043792, 0.306003, 0.637272, 1.249893, 2.473548",\ + "0.055737, 0.309242, 0.637376, 1.250639, 2.473548",\ + "0.131941, 0.347209, 0.643620, 1.253596, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011"); + values ( "0.069683, 0.173907, 0.285093, 0.488958, 0.896688",\ + "0.157089, 0.261225, 0.372374, 0.576263, 0.984041",\ + "0.237477, 0.341556, 0.452401, 0.656292, 1.064073",\ + "0.294246, 0.399105, 0.509943, 0.713536, 1.120720",\ + "0.588850, 0.702448, 0.813573, 1.016548, 1.422497"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011"); + values ( "0.026485, 0.188353, 0.387584, 0.758599, 1.500628",\ + "0.026485, 0.188353, 0.387584, 0.758599, 1.500628",\ + "0.027485, 0.188353, 0.387584, 0.758599, 1.500628",\ + "0.029472, 0.188961, 0.388043, 0.759501, 1.502419",\ + "0.047715, 0.193213, 0.388117, 0.760273, 1.504585"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[47]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026933, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\ + "0.213301, 0.167430, 0.137235, 0.125895, 0.139600",\ + "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\ + "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\ + "0.793561, 0.745754, 0.715310, 0.703809, 0.716803"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026485, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\ + "0.266577, 0.191265, 0.123161, 0.100283, 0.164008",\ + "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\ + "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\ + "0.899406, 0.824219, 0.756483, 0.734362, 0.805439"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[47]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026933, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\ + "-0.141091, -0.098663, -0.064202, -0.024280, 0.287954",\ + "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\ + "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\ + "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026485, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\ + "-0.174450, -0.108363, -0.050457, -0.008429, 0.211751",\ + "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\ + "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\ + "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[47]_hldr*/ + +} /* end of pin tl_o[47] */ + +pin("tl_o[46]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001816 ; + + /* Other user defined attributes. */ + original_pin : tl_o[46]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.047653, 0.200824, 0.376286, 0.699138, 1.344843",\ + "0.133940, 0.287998, 0.463391, 0.785853, 1.430777",\ + "0.217014, 0.376126, 0.551347, 0.873475, 1.517732",\ + "0.274798, 0.440522, 0.615463, 0.937389, 1.581241",\ + "0.574010, 0.790389, 0.965848, 1.286131, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.023390, 0.299039, 0.632479, 1.249174, 2.482563",\ + "0.027983, 0.300023, 0.634430, 1.249174, 2.482563",\ + "0.041008, 0.302285, 0.634466, 1.249174, 2.482563",\ + "0.052904, 0.305573, 0.634567, 1.249174, 2.482563",\ + "0.128390, 0.344019, 0.640826, 1.251733, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.067359, 0.172690, 0.284194, 0.488370, 0.896722",\ + "0.154772, 0.260009, 0.371475, 0.575675, 0.984076",\ + "0.235124, 0.340344, 0.451502, 0.655704, 1.064107",\ + "0.291800, 0.397892, 0.509045, 0.712948, 1.120755",\ + "0.585433, 0.701229, 0.812678, 1.015963, 1.422532"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.024087, 0.186982, 0.387454, 0.759758, 1.504368",\ + "0.024087, 0.187126, 0.387958, 0.759758, 1.504368",\ + "0.025192, 0.187126, 0.387958, 0.759758, 1.504368",\ + "0.027281, 0.187126, 0.387958, 0.759758, 1.504368",\ + "0.045983, 0.191111, 0.387958, 0.759758, 1.504648"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[46]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.047653, 0.200824, 0.376286, 0.699138, 1.344843",\ + "0.133940, 0.287998, 0.463391, 0.785853, 1.430777",\ + "0.217014, 0.376126, 0.551347, 0.873475, 1.517732",\ + "0.274798, 0.440522, 0.615463, 0.937389, 1.581241",\ + "0.574010, 0.790389, 0.965848, 1.286131, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.023390, 0.299039, 0.632479, 1.247947, 2.473548",\ + "0.027983, 0.300023, 0.634430, 1.247947, 2.473548",\ + "0.041008, 0.302285, 0.634466, 1.248022, 2.473548",\ + "0.052904, 0.305573, 0.634567, 1.248766, 2.473548",\ + "0.128390, 0.344019, 0.640826, 1.251733, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.067359, 0.172690, 0.284194, 0.488370, 0.896722",\ + "0.154772, 0.260009, 0.371475, 0.575675, 0.984076",\ + "0.235124, 0.340344, 0.451502, 0.655704, 1.064107",\ + "0.291800, 0.397892, 0.509045, 0.712948, 1.120755",\ + "0.585433, 0.701229, 0.812678, 1.015963, 1.422532"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.024087, 0.186184, 0.385947, 0.757528, 1.500690",\ + "0.024087, 0.186184, 0.385947, 0.757528, 1.500690",\ + "0.025192, 0.186184, 0.385947, 0.757528, 1.500690",\ + "0.027281, 0.186796, 0.386404, 0.758430, 1.502482",\ + "0.045983, 0.191111, 0.386476, 0.759200, 1.504648"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[46]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.023390, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\ + "0.211804, 0.165933, 0.135738, 0.124398, 0.138103",\ + "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\ + "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\ + "0.793561, 0.745754, 0.715310, 0.703809, 0.716803"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024087, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\ + "0.265681, 0.190370, 0.122265, 0.099388, 0.163112",\ + "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\ + "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\ + "0.899406, 0.824219, 0.756483, 0.734362, 0.805439"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[46]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.023390, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\ + "-0.139610, -0.097182, -0.062721, -0.022799, 0.289435",\ + "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\ + "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\ + "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024087, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\ + "-0.173560, -0.107472, -0.049566, -0.007539, 0.212641",\ + "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\ + "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\ + "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[46]_hldr*/ + +} /* end of pin tl_o[46] */ + +pin("tl_o[45]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002729 ; + + /* Other user defined attributes. */ + original_pin : tl_o[45]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011"); + values ( "0.050122, 0.202663, 0.377667, 0.700059, 1.344843",\ + "0.136545, 0.289838, 0.464771, 0.786773, 1.430777",\ + "0.220228, 0.377964, 0.552725, 0.874394, 1.517732",\ + "0.278624, 0.442356, 0.616840, 0.938307, 1.581241",\ + "0.581536, 0.792234, 0.967218, 1.287045, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011"); + values ( "0.026704, 0.302529, 0.635118, 1.250933, 2.482563",\ + "0.030951, 0.303532, 0.637054, 1.250933, 2.482563",\ + "0.043612, 0.305763, 0.637091, 1.250933, 2.482563",\ + "0.055554, 0.309005, 0.637195, 1.250933, 2.482563",\ + "0.131711, 0.347003, 0.643440, 1.253476, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011"); + values ( "0.069519, 0.173822, 0.285028, 0.488913, 0.896683",\ + "0.156925, 0.261140, 0.372309, 0.576218, 0.984036",\ + "0.237311, 0.341470, 0.452336, 0.656247, 1.064068",\ + "0.294074, 0.399020, 0.509878, 0.713491, 1.120715",\ + "0.588609, 0.702362, 0.813509, 1.016503, 1.422492"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011"); + values ( "0.026316, 0.189006, 0.388975, 0.760749, 1.504296",\ + "0.026316, 0.189156, 0.389477, 0.760749, 1.504296",\ + "0.027323, 0.189156, 0.389477, 0.760749, 1.504296",\ + "0.029318, 0.189156, 0.389477, 0.760749, 1.504296",\ + "0.047593, 0.193065, 0.389477, 0.760749, 1.504576"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[45]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011"); + values ( "0.050122, 0.202663, 0.377667, 0.700059, 1.344843",\ + "0.136545, 0.289838, 0.464771, 0.786773, 1.430777",\ + "0.220228, 0.377964, 0.552725, 0.874394, 1.517732",\ + "0.278624, 0.442356, 0.616840, 0.938307, 1.581241",\ + "0.581536, 0.792234, 0.967218, 1.287045, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011"); + values ( "0.026704, 0.302529, 0.635118, 1.249697, 2.473548",\ + "0.030951, 0.303532, 0.637054, 1.249697, 2.473548",\ + "0.043612, 0.305763, 0.637091, 1.249772, 2.473548",\ + "0.055554, 0.309005, 0.637195, 1.250518, 2.473548",\ + "0.131711, 0.347003, 0.643440, 1.253476, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011"); + values ( "0.069519, 0.173822, 0.285028, 0.488913, 0.896683",\ + "0.156925, 0.261140, 0.372309, 0.576218, 0.984036",\ + "0.237311, 0.341470, 0.452336, 0.656247, 1.064068",\ + "0.294074, 0.399020, 0.509878, 0.713491, 1.120715",\ + "0.588609, 0.702362, 0.813509, 1.016503, 1.422492"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011"); + values ( "0.026316, 0.188200, 0.387466, 0.758517, 1.500619",\ + "0.026316, 0.188200, 0.387466, 0.758517, 1.500619",\ + "0.027323, 0.188200, 0.387466, 0.758517, 1.500619",\ + "0.029318, 0.188809, 0.387924, 0.759419, 1.502410",\ + "0.047593, 0.193065, 0.387998, 0.760191, 1.504576"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[45]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026704, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\ + "0.213204, 0.167333, 0.137138, 0.125798, 0.139503",\ + "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\ + "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\ + "0.793561, 0.745754, 0.715310, 0.703809, 0.716803"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026316, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\ + "0.266513, 0.191202, 0.123098, 0.100220, 0.163945",\ + "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\ + "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\ + "0.899406, 0.824219, 0.756483, 0.734362, 0.805439"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[45]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026704, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\ + "-0.140996, -0.098567, -0.064106, -0.024184, 0.288050",\ + "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\ + "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\ + "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026316, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\ + "-0.174387, -0.108300, -0.050394, -0.008366, 0.211814",\ + "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\ + "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\ + "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[45]_hldr*/ + +} /* end of pin tl_o[45] */ + +pin("tl_o[44]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002742 ; + + /* Other user defined attributes. */ + original_pin : tl_o[44]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011"); + values ( "0.050158, 0.202690, 0.377687, 0.700072, 1.344843",\ + "0.136583, 0.289865, 0.464791, 0.786786, 1.430777",\ + "0.220274, 0.377991, 0.552745, 0.874407, 1.517732",\ + "0.278679, 0.442383, 0.616860, 0.938320, 1.581241",\ + "0.581645, 0.792261, 0.967238, 1.287058, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011"); + values ( "0.026752, 0.302579, 0.635156, 1.250959, 2.482563",\ + "0.030994, 0.303583, 0.637092, 1.250959, 2.482563",\ + "0.043650, 0.305813, 0.637129, 1.250959, 2.482563",\ + "0.055592, 0.309055, 0.637233, 1.250959, 2.482563",\ + "0.131760, 0.347046, 0.643478, 1.253501, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011"); + values ( "0.069547, 0.173836, 0.285039, 0.488919, 0.896680",\ + "0.156953, 0.261154, 0.372320, 0.576224, 0.984034",\ + "0.237340, 0.341485, 0.452347, 0.656253, 1.064065",\ + "0.294104, 0.399034, 0.509889, 0.713497, 1.120713",\ + "0.588650, 0.702376, 0.813519, 1.016509, 1.422490"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011"); + values ( "0.026345, 0.189032, 0.388994, 0.760760, 1.504292",\ + "0.026345, 0.189182, 0.389496, 0.760760, 1.504292",\ + "0.027351, 0.189182, 0.389496, 0.760760, 1.504292",\ + "0.029344, 0.189182, 0.389496, 0.760760, 1.504292",\ + "0.047614, 0.193091, 0.389496, 0.760760, 1.504572"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[44]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011"); + values ( "0.050158, 0.202690, 0.377687, 0.700072, 1.344843",\ + "0.136583, 0.289865, 0.464791, 0.786786, 1.430777",\ + "0.220274, 0.377991, 0.552745, 0.874407, 1.517732",\ + "0.278679, 0.442383, 0.616860, 0.938320, 1.581241",\ + "0.581645, 0.792261, 0.967238, 1.287058, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011"); + values ( "0.026752, 0.302579, 0.635156, 1.249722, 2.473548",\ + "0.030994, 0.303583, 0.637092, 1.249722, 2.473548",\ + "0.043650, 0.305813, 0.637129, 1.249798, 2.473548",\ + "0.055592, 0.309055, 0.637233, 1.250543, 2.473548",\ + "0.131760, 0.347046, 0.643478, 1.253501, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011"); + values ( "0.069547, 0.173836, 0.285039, 0.488919, 0.896680",\ + "0.156953, 0.261154, 0.372320, 0.576224, 0.984034",\ + "0.237340, 0.341485, 0.452347, 0.656253, 1.064065",\ + "0.294104, 0.399034, 0.509889, 0.713497, 1.120713",\ + "0.588650, 0.702376, 0.813519, 1.016509, 1.422490"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011"); + values ( "0.026345, 0.188226, 0.387484, 0.758528, 1.500614",\ + "0.026345, 0.188226, 0.387484, 0.758528, 1.500614",\ + "0.027351, 0.188226, 0.387484, 0.758528, 1.500614",\ + "0.029344, 0.188835, 0.387943, 0.759431, 1.502406",\ + "0.047614, 0.193091, 0.388017, 0.760202, 1.504572"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[44]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026752, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\ + "0.213225, 0.167354, 0.137159, 0.125818, 0.139523",\ + "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\ + "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\ + "0.793561, 0.745754, 0.715310, 0.703809, 0.716803"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026345, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\ + "0.266524, 0.191213, 0.123109, 0.100231, 0.163955",\ + "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\ + "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\ + "0.899406, 0.824219, 0.756483, 0.734362, 0.805439"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[44]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026752, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\ + "-0.141016, -0.098588, -0.064126, -0.024204, 0.288030",\ + "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\ + "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\ + "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026345, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\ + "-0.174398, -0.108311, -0.050405, -0.008377, 0.211803",\ + "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\ + "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\ + "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[44]_hldr*/ + +} /* end of pin tl_o[44] */ + +pin("tl_o[43]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002272 ; + + /* Other user defined attributes. */ + original_pin : tl_o[43]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011"); + values ( "0.048885, 0.201742, 0.376975, 0.699598, 1.344843",\ + "0.135240, 0.288916, 0.464080, 0.786312, 1.430777",\ + "0.218618, 0.377044, 0.552035, 0.873934, 1.517732",\ + "0.276707, 0.441437, 0.616150, 0.937847, 1.581241",\ + "0.577766, 0.791310, 0.966532, 1.286587, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011"); + values ( "0.025044, 0.300781, 0.633796, 1.250052, 2.482563",\ + "0.029464, 0.301774, 0.635740, 1.250052, 2.482563",\ + "0.042308, 0.304021, 0.635776, 1.250052, 2.482563",\ + "0.054226, 0.307286, 0.635878, 1.250052, 2.482563",\ + "0.130048, 0.345508, 0.642131, 1.252603, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011"); + values ( "0.068436, 0.173254, 0.284610, 0.488640, 0.896702",\ + "0.155845, 0.260572, 0.371891, 0.575945, 0.984055",\ + "0.236214, 0.340905, 0.451917, 0.655974, 1.064087",\ + "0.292933, 0.398454, 0.509460, 0.713218, 1.120734",\ + "0.587016, 0.701794, 0.813092, 1.016232, 1.422511"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011"); + values ( "0.025198, 0.187991, 0.388212, 0.760251, 1.504330",\ + "0.025198, 0.188138, 0.388715, 0.760251, 1.504330",\ + "0.026254, 0.188138, 0.388715, 0.760251, 1.504330",\ + "0.028296, 0.188138, 0.388715, 0.760251, 1.504330",\ + "0.046785, 0.192085, 0.388715, 0.760251, 1.504610"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[43]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011"); + values ( "0.048885, 0.201742, 0.376975, 0.699598, 1.344843",\ + "0.135240, 0.288916, 0.464080, 0.786312, 1.430777",\ + "0.218618, 0.377044, 0.552035, 0.873934, 1.517732",\ + "0.276707, 0.441437, 0.616150, 0.937847, 1.581241",\ + "0.577766, 0.791310, 0.966532, 1.286587, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011"); + values ( "0.025044, 0.300781, 0.633796, 1.248820, 2.473548",\ + "0.029464, 0.301774, 0.635740, 1.248820, 2.473548",\ + "0.042308, 0.304021, 0.635776, 1.248896, 2.473548",\ + "0.054226, 0.307286, 0.635878, 1.249640, 2.473548",\ + "0.130048, 0.345508, 0.642131, 1.252603, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011"); + values ( "0.068436, 0.173254, 0.284610, 0.488640, 0.896702",\ + "0.155845, 0.260572, 0.371891, 0.575945, 0.984055",\ + "0.236214, 0.340905, 0.451917, 0.655974, 1.064087",\ + "0.292933, 0.398454, 0.509460, 0.713218, 1.120734",\ + "0.587016, 0.701794, 0.813092, 1.016232, 1.422511"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011"); + values ( "0.025198, 0.187189, 0.386704, 0.758020, 1.500653",\ + "0.025198, 0.187189, 0.386704, 0.758020, 1.500653",\ + "0.026254, 0.187189, 0.386704, 0.758020, 1.500653",\ + "0.028296, 0.187799, 0.387161, 0.758922, 1.502445",\ + "0.046785, 0.192085, 0.387234, 0.759693, 1.504610"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[43]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025044, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\ + "0.212503, 0.166632, 0.136437, 0.125097, 0.138801",\ + "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\ + "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\ + "0.793561, 0.745754, 0.715310, 0.703809, 0.716803"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025198, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\ + "0.266096, 0.190785, 0.122680, 0.099803, 0.163527",\ + "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\ + "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\ + "0.899406, 0.824219, 0.756483, 0.734362, 0.805439"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[43]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025044, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\ + "-0.140302, -0.097874, -0.063412, -0.023490, 0.288744",\ + "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\ + "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\ + "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025198, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\ + "-0.173972, -0.107885, -0.049979, -0.007951, 0.212229",\ + "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\ + "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\ + "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[43]_hldr*/ + +} /* end of pin tl_o[43] */ + +pin("tl_o[42]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002445 ; + + /* Other user defined attributes. */ + original_pin : tl_o[42]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.049354, 0.202091, 0.377237, 0.699773, 1.344843",\ + "0.135735, 0.289266, 0.464342, 0.786487, 1.430777",\ + "0.219229, 0.377393, 0.552297, 0.874108, 1.517732",\ + "0.277434, 0.441786, 0.616412, 0.938021, 1.581241",\ + "0.579196, 0.791661, 0.966792, 1.286761, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.025674, 0.301444, 0.634297, 1.250386, 2.482563",\ + "0.030028, 0.302441, 0.636238, 1.250386, 2.482563",\ + "0.042803, 0.304681, 0.636274, 1.250386, 2.482563",\ + "0.054730, 0.307938, 0.636378, 1.250386, 2.482563",\ + "0.130679, 0.346075, 0.642627, 1.252934, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.068801, 0.173445, 0.284745, 0.488720, 0.896671",\ + "0.156209, 0.260764, 0.372026, 0.576025, 0.984024",\ + "0.236584, 0.341096, 0.452053, 0.656054, 1.064056",\ + "0.293318, 0.398645, 0.509595, 0.713298, 1.120704",\ + "0.587553, 0.701985, 0.813226, 1.016311, 1.422480"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.025575, 0.188333, 0.388458, 0.760397, 1.504274",\ + "0.025575, 0.188481, 0.388961, 0.760397, 1.504274",\ + "0.026615, 0.188481, 0.388961, 0.760397, 1.504274",\ + "0.028641, 0.188481, 0.388961, 0.760397, 1.504274",\ + "0.047058, 0.192416, 0.388961, 0.760397, 1.504554"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[42]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.049354, 0.202091, 0.377237, 0.699773, 1.344843",\ + "0.135735, 0.289266, 0.464342, 0.786487, 1.430777",\ + "0.219229, 0.377393, 0.552297, 0.874108, 1.517732",\ + "0.277434, 0.441786, 0.616412, 0.938021, 1.581241",\ + "0.579196, 0.791661, 0.966792, 1.286761, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.025674, 0.301444, 0.634297, 1.249153, 2.473548",\ + "0.030028, 0.302441, 0.636238, 1.249153, 2.473548",\ + "0.042803, 0.304681, 0.636274, 1.249228, 2.473548",\ + "0.054730, 0.307938, 0.636378, 1.249973, 2.473548",\ + "0.130679, 0.346075, 0.642627, 1.252934, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.068801, 0.173445, 0.284745, 0.488720, 0.896671",\ + "0.156209, 0.260764, 0.372026, 0.576025, 0.984024",\ + "0.236584, 0.341096, 0.452053, 0.656054, 1.064056",\ + "0.293318, 0.398645, 0.509595, 0.713298, 1.120704",\ + "0.587553, 0.701985, 0.813226, 1.016311, 1.422480"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.025575, 0.187530, 0.386950, 0.758165, 1.500597",\ + "0.025575, 0.187530, 0.386950, 0.758165, 1.500597",\ + "0.026615, 0.187530, 0.386950, 0.758165, 1.500597",\ + "0.028641, 0.188139, 0.387407, 0.759068, 1.502388",\ + "0.047058, 0.192416, 0.387481, 0.759838, 1.504554"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[42]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025674, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\ + "0.212769, 0.166898, 0.136703, 0.125363, 0.139067",\ + "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\ + "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\ + "0.793561, 0.745754, 0.715310, 0.703809, 0.716803"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025575, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\ + "0.266237, 0.190925, 0.122821, 0.099943, 0.163668",\ + "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\ + "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\ + "0.899406, 0.824219, 0.756483, 0.734362, 0.805439"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[42]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025674, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\ + "-0.140565, -0.098137, -0.063675, -0.023754, 0.288480",\ + "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\ + "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\ + "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025575, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\ + "-0.174112, -0.108025, -0.050119, -0.008091, 0.212089",\ + "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\ + "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\ + "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[42]_hldr*/ + +} /* end of pin tl_o[42] */ + +pin("tl_o[41]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002414 ; + + /* Other user defined attributes. */ + original_pin : tl_o[41]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.049270, 0.202028, 0.377190, 0.699741, 1.344843",\ + "0.135646, 0.289203, 0.464294, 0.786455, 1.430777",\ + "0.219118, 0.377330, 0.552249, 0.874077, 1.517732",\ + "0.277303, 0.441723, 0.616364, 0.937990, 1.581241",\ + "0.578938, 0.791597, 0.966745, 1.286729, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.025560, 0.301324, 0.634207, 1.250326, 2.482563",\ + "0.029927, 0.302321, 0.636148, 1.250326, 2.482563",\ + "0.042713, 0.304562, 0.636184, 1.250326, 2.482563",\ + "0.054639, 0.307820, 0.636287, 1.250326, 2.482563",\ + "0.130565, 0.345973, 0.642537, 1.252874, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.068784, 0.173437, 0.284746, 0.488731, 0.896702",\ + "0.156193, 0.260755, 0.372027, 0.576036, 0.984055",\ + "0.236567, 0.341087, 0.452054, 0.656065, 1.064087",\ + "0.293300, 0.398636, 0.509596, 0.713309, 1.120735",\ + "0.587529, 0.701976, 0.813228, 1.016322, 1.422511"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.025558, 0.188317, 0.388460, 0.760417, 1.504331",\ + "0.025558, 0.188465, 0.388963, 0.760417, 1.504331",\ + "0.026598, 0.188465, 0.388963, 0.760417, 1.504331",\ + "0.028625, 0.188465, 0.388963, 0.760417, 1.504331",\ + "0.047045, 0.192400, 0.388963, 0.760417, 1.504611"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[41]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.049270, 0.202028, 0.377190, 0.699741, 1.344843",\ + "0.135646, 0.289203, 0.464294, 0.786455, 1.430777",\ + "0.219118, 0.377330, 0.552249, 0.874077, 1.517732",\ + "0.277303, 0.441723, 0.616364, 0.937990, 1.581241",\ + "0.578938, 0.791597, 0.966745, 1.286729, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.025560, 0.301324, 0.634207, 1.249093, 2.473548",\ + "0.029927, 0.302321, 0.636148, 1.249093, 2.473548",\ + "0.042713, 0.304562, 0.636184, 1.249168, 2.473548",\ + "0.054639, 0.307820, 0.636287, 1.249913, 2.473548",\ + "0.130565, 0.345973, 0.642537, 1.252874, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.068784, 0.173437, 0.284746, 0.488731, 0.896702",\ + "0.156193, 0.260755, 0.372027, 0.576036, 0.984055",\ + "0.236567, 0.341087, 0.452054, 0.656065, 1.064087",\ + "0.293300, 0.398636, 0.509596, 0.713309, 1.120735",\ + "0.587529, 0.701976, 0.813228, 1.016322, 1.422511"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.025558, 0.187514, 0.386952, 0.758186, 1.500654",\ + "0.025558, 0.187514, 0.386952, 0.758186, 1.500654",\ + "0.026598, 0.187514, 0.386952, 0.758186, 1.500654",\ + "0.028625, 0.188124, 0.387410, 0.759088, 1.502445",\ + "0.047045, 0.192400, 0.387483, 0.759859, 1.504611"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[41]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025560, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\ + "0.212721, 0.166850, 0.136655, 0.125315, 0.139019",\ + "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\ + "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\ + "0.793561, 0.745754, 0.715310, 0.703809, 0.716803"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025558, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\ + "0.266230, 0.190919, 0.122815, 0.099937, 0.163661",\ + "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\ + "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\ + "0.899406, 0.824219, 0.756483, 0.734362, 0.805439"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[41]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025560, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\ + "-0.140517, -0.098089, -0.063628, -0.023706, 0.288528",\ + "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\ + "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\ + "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025558, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\ + "-0.174106, -0.108018, -0.050112, -0.008085, 0.212095",\ + "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\ + "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\ + "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[41]_hldr*/ + +} /* end of pin tl_o[41] */ + +pin("tl_o[40]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001805 ; + + /* Other user defined attributes. */ + original_pin : tl_o[40]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.047624, 0.200802, 0.376269, 0.699127, 1.344843",\ + "0.133909, 0.287977, 0.463375, 0.785842, 1.430777",\ + "0.216976, 0.376105, 0.551331, 0.873464, 1.517732",\ + "0.274753, 0.440500, 0.615446, 0.937378, 1.581241",\ + "0.573921, 0.790368, 0.965832, 1.286120, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.023351, 0.298998, 0.632448, 1.249153, 2.482563",\ + "0.027948, 0.299981, 0.634399, 1.249153, 2.482563",\ + "0.040978, 0.302244, 0.634435, 1.249153, 2.482563",\ + "0.052873, 0.305533, 0.634536, 1.249153, 2.482563",\ + "0.128351, 0.343984, 0.640795, 1.251713, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.067343, 0.172682, 0.284189, 0.488369, 0.896728",\ + "0.154756, 0.260000, 0.371470, 0.575674, 0.984081",\ + "0.235108, 0.340335, 0.451497, 0.655702, 1.064113",\ + "0.291783, 0.397884, 0.509040, 0.712947, 1.120760",\ + "0.585410, 0.701221, 0.812673, 1.015961, 1.422537"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.024071, 0.186967, 0.387445, 0.759756, 1.504378",\ + "0.024071, 0.187111, 0.387949, 0.759756, 1.504378",\ + "0.025176, 0.187111, 0.387949, 0.759756, 1.504378",\ + "0.027266, 0.187111, 0.387949, 0.759756, 1.504378",\ + "0.045971, 0.191097, 0.387949, 0.759756, 1.504658"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[40]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.047624, 0.200802, 0.376269, 0.699127, 1.344843",\ + "0.133909, 0.287977, 0.463375, 0.785842, 1.430777",\ + "0.216976, 0.376105, 0.551331, 0.873464, 1.517732",\ + "0.274753, 0.440500, 0.615446, 0.937378, 1.581241",\ + "0.573921, 0.790368, 0.965832, 1.286120, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.023351, 0.298998, 0.632448, 1.247926, 2.473548",\ + "0.027948, 0.299981, 0.634399, 1.247926, 2.473548",\ + "0.040978, 0.302244, 0.634435, 1.248002, 2.473548",\ + "0.052873, 0.305533, 0.634536, 1.248745, 2.473548",\ + "0.128351, 0.343984, 0.640795, 1.251713, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.067343, 0.172682, 0.284189, 0.488369, 0.896728",\ + "0.154756, 0.260000, 0.371470, 0.575674, 0.984081",\ + "0.235108, 0.340335, 0.451497, 0.655702, 1.064113",\ + "0.291783, 0.397884, 0.509040, 0.712947, 1.120760",\ + "0.585410, 0.701221, 0.812673, 1.015961, 1.422537"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.024071, 0.186169, 0.385939, 0.757526, 1.500700",\ + "0.024071, 0.186169, 0.385939, 0.757526, 1.500700",\ + "0.025176, 0.186169, 0.385939, 0.757526, 1.500700",\ + "0.027266, 0.186781, 0.386395, 0.758427, 1.502492",\ + "0.045971, 0.191097, 0.386467, 0.759197, 1.504658"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[40]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.023351, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\ + "0.211788, 0.165917, 0.135722, 0.124381, 0.138086",\ + "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\ + "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\ + "0.793561, 0.745754, 0.715310, 0.703809, 0.716803"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024071, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\ + "0.265675, 0.190363, 0.122259, 0.099381, 0.163106",\ + "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\ + "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\ + "0.899406, 0.824219, 0.756483, 0.734362, 0.805439"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[40]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.023351, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\ + "-0.139594, -0.097166, -0.062704, -0.022783, 0.289451",\ + "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\ + "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\ + "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024071, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\ + "-0.173554, -0.107466, -0.049560, -0.007532, 0.212647",\ + "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\ + "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\ + "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[40]_hldr*/ + +} /* end of pin tl_o[40] */ + +pin("tl_o[39]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002265 ; + + /* Other user defined attributes. */ + original_pin : tl_o[39]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011"); + values ( "0.048867, 0.201728, 0.376965, 0.699591, 1.344843",\ + "0.135221, 0.288903, 0.464069, 0.786305, 1.430777",\ + "0.218594, 0.377030, 0.552024, 0.873927, 1.517732",\ + "0.276679, 0.441423, 0.616140, 0.937840, 1.581241",\ + "0.577710, 0.791296, 0.966522, 1.286580, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011"); + values ( "0.025020, 0.300755, 0.633777, 1.250039, 2.482563",\ + "0.029442, 0.301748, 0.635720, 1.250039, 2.482563",\ + "0.042289, 0.303995, 0.635756, 1.250039, 2.482563",\ + "0.054207, 0.307260, 0.635859, 1.250039, 2.482563",\ + "0.130023, 0.345486, 0.642111, 1.252590, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011"); + values ( "0.068420, 0.173246, 0.284604, 0.488637, 0.896702",\ + "0.155830, 0.260564, 0.371885, 0.575942, 0.984056",\ + "0.236199, 0.340897, 0.451912, 0.655970, 1.064088",\ + "0.292917, 0.398446, 0.509454, 0.713215, 1.120735",\ + "0.586994, 0.701786, 0.813086, 1.016228, 1.422512"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011"); + values ( "0.025182, 0.187976, 0.388201, 0.760245, 1.504332",\ + "0.025182, 0.188123, 0.388704, 0.760245, 1.504332",\ + "0.026239, 0.188123, 0.388704, 0.760245, 1.504332",\ + "0.028282, 0.188123, 0.388704, 0.760245, 1.504332",\ + "0.046774, 0.192071, 0.388704, 0.760245, 1.504612"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[39]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011"); + values ( "0.048867, 0.201728, 0.376965, 0.699591, 1.344843",\ + "0.135221, 0.288903, 0.464069, 0.786305, 1.430777",\ + "0.218594, 0.377030, 0.552024, 0.873927, 1.517732",\ + "0.276679, 0.441423, 0.616140, 0.937840, 1.581241",\ + "0.577710, 0.791296, 0.966522, 1.286580, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011"); + values ( "0.025020, 0.300755, 0.633777, 1.248807, 2.473548",\ + "0.029442, 0.301748, 0.635720, 1.248807, 2.473548",\ + "0.042289, 0.303995, 0.635756, 1.248883, 2.473548",\ + "0.054207, 0.307260, 0.635859, 1.249627, 2.473548",\ + "0.130023, 0.345486, 0.642111, 1.252590, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011"); + values ( "0.068420, 0.173246, 0.284604, 0.488637, 0.896702",\ + "0.155830, 0.260564, 0.371885, 0.575942, 0.984056",\ + "0.236199, 0.340897, 0.451912, 0.655970, 1.064088",\ + "0.292917, 0.398446, 0.509454, 0.713215, 1.120735",\ + "0.586994, 0.701786, 0.813086, 1.016228, 1.422512"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011"); + values ( "0.025182, 0.187175, 0.386693, 0.758014, 1.500654",\ + "0.025182, 0.187175, 0.386693, 0.758014, 1.500654",\ + "0.026239, 0.187175, 0.386693, 0.758014, 1.500654",\ + "0.028282, 0.187785, 0.387151, 0.758916, 1.502446",\ + "0.046774, 0.192071, 0.387224, 0.759686, 1.504612"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[39]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025020, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\ + "0.212492, 0.166621, 0.136427, 0.125086, 0.138791",\ + "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\ + "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\ + "0.793561, 0.745754, 0.715310, 0.703809, 0.716803"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025182, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\ + "0.266090, 0.190779, 0.122675, 0.099797, 0.163521",\ + "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\ + "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\ + "0.899406, 0.824219, 0.756483, 0.734362, 0.805439"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[39]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025020, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\ + "-0.140291, -0.097863, -0.063402, -0.023480, 0.288754",\ + "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\ + "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\ + "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025182, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\ + "-0.173966, -0.107879, -0.049973, -0.007945, 0.212235",\ + "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\ + "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\ + "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[39]_hldr*/ + +} /* end of pin tl_o[39] */ + +pin("tl_o[38]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002414 ; + + /* Other user defined attributes. */ + original_pin : tl_o[38]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.049270, 0.202028, 0.377190, 0.699741, 1.344843",\ + "0.135646, 0.289203, 0.464294, 0.786455, 1.430777",\ + "0.219118, 0.377330, 0.552249, 0.874077, 1.517732",\ + "0.277303, 0.441723, 0.616364, 0.937990, 1.581241",\ + "0.578938, 0.791597, 0.966745, 1.286729, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.025560, 0.301324, 0.634207, 1.250326, 2.482563",\ + "0.029927, 0.302321, 0.636148, 1.250326, 2.482563",\ + "0.042713, 0.304562, 0.636184, 1.250326, 2.482563",\ + "0.054639, 0.307820, 0.636287, 1.250326, 2.482563",\ + "0.130565, 0.345973, 0.642537, 1.252874, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.068784, 0.173437, 0.284746, 0.488731, 0.896702",\ + "0.156193, 0.260755, 0.372027, 0.576036, 0.984055",\ + "0.236567, 0.341087, 0.452054, 0.656065, 1.064087",\ + "0.293300, 0.398636, 0.509596, 0.713309, 1.120735",\ + "0.587529, 0.701976, 0.813228, 1.016322, 1.422511"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.025558, 0.188317, 0.388460, 0.760417, 1.504331",\ + "0.025558, 0.188465, 0.388963, 0.760417, 1.504331",\ + "0.026598, 0.188465, 0.388963, 0.760417, 1.504331",\ + "0.028625, 0.188465, 0.388963, 0.760417, 1.504331",\ + "0.047045, 0.192400, 0.388963, 0.760417, 1.504611"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[38]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.049270, 0.202028, 0.377190, 0.699741, 1.344843",\ + "0.135646, 0.289203, 0.464294, 0.786455, 1.430777",\ + "0.219118, 0.377330, 0.552249, 0.874077, 1.517732",\ + "0.277303, 0.441723, 0.616364, 0.937990, 1.581241",\ + "0.578938, 0.791597, 0.966745, 1.286729, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.025560, 0.301324, 0.634207, 1.249093, 2.473548",\ + "0.029927, 0.302321, 0.636148, 1.249093, 2.473548",\ + "0.042713, 0.304562, 0.636184, 1.249168, 2.473548",\ + "0.054639, 0.307820, 0.636287, 1.249913, 2.473548",\ + "0.130565, 0.345973, 0.642537, 1.252874, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.068784, 0.173437, 0.284746, 0.488731, 0.896702",\ + "0.156193, 0.260755, 0.372027, 0.576036, 0.984055",\ + "0.236567, 0.341087, 0.452054, 0.656065, 1.064087",\ + "0.293300, 0.398636, 0.509596, 0.713309, 1.120735",\ + "0.587529, 0.701976, 0.813228, 1.016322, 1.422511"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.025558, 0.187514, 0.386952, 0.758186, 1.500654",\ + "0.025558, 0.187514, 0.386952, 0.758186, 1.500654",\ + "0.026598, 0.187514, 0.386952, 0.758186, 1.500654",\ + "0.028625, 0.188124, 0.387410, 0.759088, 1.502445",\ + "0.047045, 0.192400, 0.387483, 0.759859, 1.504611"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[38]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025560, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\ + "0.212721, 0.166850, 0.136655, 0.125315, 0.139019",\ + "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\ + "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\ + "0.793561, 0.745754, 0.715310, 0.703809, 0.716803"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025558, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\ + "0.266230, 0.190919, 0.122815, 0.099937, 0.163661",\ + "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\ + "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\ + "0.899406, 0.824219, 0.756483, 0.734362, 0.805439"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[38]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025560, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\ + "-0.140517, -0.098089, -0.063628, -0.023706, 0.288528",\ + "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\ + "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\ + "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025558, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\ + "-0.174106, -0.108018, -0.050112, -0.008085, 0.212095",\ + "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\ + "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\ + "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[38]_hldr*/ + +} /* end of pin tl_o[38] */ + +pin("tl_o[37]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002445 ; + + /* Other user defined attributes. */ + original_pin : tl_o[37]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.049354, 0.202091, 0.377237, 0.699773, 1.344843",\ + "0.135735, 0.289266, 0.464342, 0.786487, 1.430777",\ + "0.219229, 0.377393, 0.552297, 0.874108, 1.517732",\ + "0.277434, 0.441786, 0.616412, 0.938021, 1.581241",\ + "0.579196, 0.791661, 0.966792, 1.286761, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.025674, 0.301444, 0.634297, 1.250386, 2.482563",\ + "0.030028, 0.302441, 0.636238, 1.250386, 2.482563",\ + "0.042803, 0.304681, 0.636274, 1.250386, 2.482563",\ + "0.054730, 0.307938, 0.636378, 1.250386, 2.482563",\ + "0.130679, 0.346075, 0.642627, 1.252934, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.068801, 0.173445, 0.284745, 0.488720, 0.896671",\ + "0.156209, 0.260764, 0.372026, 0.576025, 0.984024",\ + "0.236584, 0.341096, 0.452053, 0.656054, 1.064056",\ + "0.293318, 0.398645, 0.509595, 0.713298, 1.120704",\ + "0.587553, 0.701985, 0.813226, 1.016311, 1.422480"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.025575, 0.188333, 0.388458, 0.760397, 1.504274",\ + "0.025575, 0.188481, 0.388961, 0.760397, 1.504274",\ + "0.026615, 0.188481, 0.388961, 0.760397, 1.504274",\ + "0.028641, 0.188481, 0.388961, 0.760397, 1.504274",\ + "0.047058, 0.192416, 0.388961, 0.760397, 1.504554"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[37]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.049354, 0.202091, 0.377237, 0.699773, 1.344843",\ + "0.135735, 0.289266, 0.464342, 0.786487, 1.430777",\ + "0.219229, 0.377393, 0.552297, 0.874108, 1.517732",\ + "0.277434, 0.441786, 0.616412, 0.938021, 1.581241",\ + "0.579196, 0.791661, 0.966792, 1.286761, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.025674, 0.301444, 0.634297, 1.249153, 2.473548",\ + "0.030028, 0.302441, 0.636238, 1.249153, 2.473548",\ + "0.042803, 0.304681, 0.636274, 1.249228, 2.473548",\ + "0.054730, 0.307938, 0.636378, 1.249973, 2.473548",\ + "0.130679, 0.346075, 0.642627, 1.252934, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.068801, 0.173445, 0.284745, 0.488720, 0.896671",\ + "0.156209, 0.260764, 0.372026, 0.576025, 0.984024",\ + "0.236584, 0.341096, 0.452053, 0.656054, 1.064056",\ + "0.293318, 0.398645, 0.509595, 0.713298, 1.120704",\ + "0.587553, 0.701985, 0.813226, 1.016311, 1.422480"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.025575, 0.187530, 0.386950, 0.758165, 1.500597",\ + "0.025575, 0.187530, 0.386950, 0.758165, 1.500597",\ + "0.026615, 0.187530, 0.386950, 0.758165, 1.500597",\ + "0.028641, 0.188139, 0.387407, 0.759068, 1.502388",\ + "0.047058, 0.192416, 0.387481, 0.759838, 1.504554"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[37]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025674, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\ + "0.212769, 0.166898, 0.136703, 0.125363, 0.139067",\ + "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\ + "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\ + "0.793561, 0.745754, 0.715310, 0.703809, 0.716803"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025575, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\ + "0.266237, 0.190925, 0.122821, 0.099943, 0.163668",\ + "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\ + "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\ + "0.899406, 0.824219, 0.756483, 0.734362, 0.805439"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[37]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025674, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\ + "-0.140565, -0.098137, -0.063675, -0.023754, 0.288480",\ + "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\ + "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\ + "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025575, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\ + "-0.174112, -0.108025, -0.050119, -0.008091, 0.212089",\ + "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\ + "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\ + "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[37]_hldr*/ + +} /* end of pin tl_o[37] */ + +pin("tl_o[36]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001816 ; + + /* Other user defined attributes. */ + original_pin : tl_o[36]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.047653, 0.200824, 0.376286, 0.699138, 1.344843",\ + "0.133940, 0.287998, 0.463391, 0.785853, 1.430777",\ + "0.217014, 0.376126, 0.551347, 0.873475, 1.517732",\ + "0.274798, 0.440522, 0.615463, 0.937389, 1.581241",\ + "0.574010, 0.790389, 0.965848, 1.286131, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.023390, 0.299039, 0.632479, 1.249174, 2.482563",\ + "0.027983, 0.300023, 0.634430, 1.249174, 2.482563",\ + "0.041008, 0.302285, 0.634466, 1.249174, 2.482563",\ + "0.052904, 0.305573, 0.634567, 1.249174, 2.482563",\ + "0.128390, 0.344019, 0.640826, 1.251733, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.067359, 0.172690, 0.284194, 0.488370, 0.896722",\ + "0.154772, 0.260009, 0.371475, 0.575675, 0.984076",\ + "0.235124, 0.340344, 0.451502, 0.655704, 1.064107",\ + "0.291800, 0.397892, 0.509045, 0.712948, 1.120755",\ + "0.585433, 0.701229, 0.812678, 1.015963, 1.422532"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.024087, 0.186982, 0.387454, 0.759758, 1.504368",\ + "0.024087, 0.187126, 0.387958, 0.759758, 1.504368",\ + "0.025192, 0.187126, 0.387958, 0.759758, 1.504368",\ + "0.027281, 0.187126, 0.387958, 0.759758, 1.504368",\ + "0.045983, 0.191111, 0.387958, 0.759758, 1.504648"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[36]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.047653, 0.200824, 0.376286, 0.699138, 1.344843",\ + "0.133940, 0.287998, 0.463391, 0.785853, 1.430777",\ + "0.217014, 0.376126, 0.551347, 0.873475, 1.517732",\ + "0.274798, 0.440522, 0.615463, 0.937389, 1.581241",\ + "0.574010, 0.790389, 0.965848, 1.286131, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.023390, 0.299039, 0.632479, 1.247947, 2.473548",\ + "0.027983, 0.300023, 0.634430, 1.247947, 2.473548",\ + "0.041008, 0.302285, 0.634466, 1.248022, 2.473548",\ + "0.052904, 0.305573, 0.634567, 1.248766, 2.473548",\ + "0.128390, 0.344019, 0.640826, 1.251733, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.067359, 0.172690, 0.284194, 0.488370, 0.896722",\ + "0.154772, 0.260009, 0.371475, 0.575675, 0.984076",\ + "0.235124, 0.340344, 0.451502, 0.655704, 1.064107",\ + "0.291800, 0.397892, 0.509045, 0.712948, 1.120755",\ + "0.585433, 0.701229, 0.812678, 1.015963, 1.422532"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.024087, 0.186184, 0.385947, 0.757528, 1.500690",\ + "0.024087, 0.186184, 0.385947, 0.757528, 1.500690",\ + "0.025192, 0.186184, 0.385947, 0.757528, 1.500690",\ + "0.027281, 0.186796, 0.386404, 0.758430, 1.502482",\ + "0.045983, 0.191111, 0.386476, 0.759200, 1.504648"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[36]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.023390, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\ + "0.211804, 0.165933, 0.135738, 0.124398, 0.138103",\ + "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\ + "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\ + "0.793561, 0.745754, 0.715310, 0.703809, 0.716803"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024087, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\ + "0.265681, 0.190370, 0.122265, 0.099388, 0.163112",\ + "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\ + "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\ + "0.899406, 0.824219, 0.756483, 0.734362, 0.805439"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[36]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.023390, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\ + "-0.139610, -0.097182, -0.062721, -0.022799, 0.289435",\ + "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\ + "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\ + "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024087, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\ + "-0.173560, -0.107472, -0.049566, -0.007539, 0.212641",\ + "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\ + "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\ + "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[36]_hldr*/ + +} /* end of pin tl_o[36] */ + +pin("tl_o[35]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002254 ; + + /* Other user defined attributes. */ + original_pin : tl_o[35]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.048838, 0.201706, 0.376948, 0.699580, 1.344843",\ + "0.135190, 0.288881, 0.464053, 0.786294, 1.430777",\ + "0.218556, 0.377008, 0.552008, 0.873916, 1.517732",\ + "0.276634, 0.441402, 0.616124, 0.937829, 1.581241",\ + "0.577621, 0.791275, 0.966506, 1.286569, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.024980, 0.300714, 0.633745, 1.250018, 2.482564",\ + "0.029407, 0.301707, 0.635689, 1.250018, 2.482564",\ + "0.042258, 0.303954, 0.635725, 1.250018, 2.482564",\ + "0.054175, 0.307220, 0.635828, 1.250018, 2.482564",\ + "0.129984, 0.345451, 0.642080, 1.252569, 2.482564"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.068404, 0.173238, 0.284599, 0.488635, 0.896708",\ + "0.155814, 0.260556, 0.371880, 0.575940, 0.984061",\ + "0.236182, 0.340889, 0.451907, 0.655969, 1.064093",\ + "0.292900, 0.398438, 0.509450, 0.713213, 1.120741",\ + "0.586970, 0.701777, 0.813081, 1.016227, 1.422517"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.025166, 0.187961, 0.388192, 0.760242, 1.504342",\ + "0.025166, 0.188108, 0.388695, 0.760242, 1.504342",\ + "0.026223, 0.188108, 0.388695, 0.760242, 1.504342",\ + "0.028267, 0.188108, 0.388695, 0.760242, 1.504342",\ + "0.046762, 0.192057, 0.388695, 0.760242, 1.504622"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[35]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.048838, 0.201706, 0.376948, 0.699580, 1.344843",\ + "0.135190, 0.288881, 0.464053, 0.786294, 1.430777",\ + "0.218556, 0.377008, 0.552008, 0.873916, 1.517732",\ + "0.276634, 0.441402, 0.616124, 0.937829, 1.581241",\ + "0.577621, 0.791275, 0.966506, 1.286569, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.024980, 0.300714, 0.633745, 1.248787, 2.473548",\ + "0.029407, 0.301707, 0.635689, 1.248787, 2.473548",\ + "0.042258, 0.303954, 0.635725, 1.248862, 2.473548",\ + "0.054175, 0.307220, 0.635828, 1.249606, 2.473548",\ + "0.129984, 0.345451, 0.642080, 1.252569, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.068404, 0.173238, 0.284599, 0.488635, 0.896708",\ + "0.155814, 0.260556, 0.371880, 0.575940, 0.984061",\ + "0.236182, 0.340889, 0.451907, 0.655969, 1.064093",\ + "0.292900, 0.398438, 0.509450, 0.713213, 1.120741",\ + "0.586970, 0.701777, 0.813081, 1.016227, 1.422517"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.025166, 0.187160, 0.386684, 0.758011, 1.500664",\ + "0.025166, 0.187160, 0.386684, 0.758011, 1.500664",\ + "0.026223, 0.187160, 0.386684, 0.758011, 1.500664",\ + "0.028267, 0.187770, 0.387142, 0.758913, 1.502456",\ + "0.046762, 0.192057, 0.387215, 0.759684, 1.504622"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[35]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024980, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\ + "0.212476, 0.166605, 0.136410, 0.125070, 0.138775",\ + "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\ + "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\ + "0.793561, 0.745754, 0.715310, 0.703809, 0.716803"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025166, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\ + "0.266084, 0.190773, 0.122668, 0.099790, 0.163515",\ + "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\ + "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\ + "0.899406, 0.824219, 0.756483, 0.734362, 0.805439"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[35]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024980, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\ + "-0.140275, -0.097847, -0.063386, -0.023464, 0.288770",\ + "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\ + "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\ + "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025166, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\ + "-0.173960, -0.107873, -0.049967, -0.007939, 0.212241",\ + "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\ + "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\ + "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[35]_hldr*/ + +} /* end of pin tl_o[35] */ + +pin("tl_o[34]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001996 ; + + /* Other user defined attributes. */ + original_pin : tl_o[34]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011"); + values ( "0.048141, 0.201187, 0.376558, 0.699320, 1.344843",\ + "0.134454, 0.288362, 0.463663, 0.786035, 1.430777",\ + "0.217649, 0.376489, 0.551619, 0.873657, 1.517732",\ + "0.275553, 0.440884, 0.615735, 0.937570, 1.581241",\ + "0.575495, 0.790754, 0.966118, 1.286311, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011"); + values ( "0.024044, 0.299728, 0.633000, 1.249521, 2.482563",\ + "0.028569, 0.300716, 0.634948, 1.249521, 2.482563",\ + "0.041522, 0.302971, 0.634984, 1.249521, 2.482563",\ + "0.053427, 0.306251, 0.635086, 1.249521, 2.482563",\ + "0.129046, 0.344608, 0.641342, 1.252077, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011"); + values ( "0.067740, 0.172889, 0.284335, 0.488454, 0.896691",\ + "0.155151, 0.260208, 0.371616, 0.575759, 0.984044",\ + "0.235509, 0.340542, 0.451643, 0.655787, 1.064076",\ + "0.292201, 0.398091, 0.509186, 0.713032, 1.120723",\ + "0.585993, 0.701429, 0.812818, 1.016046, 1.422500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011"); + values ( "0.024480, 0.187339, 0.387711, 0.759911, 1.504310",\ + "0.024480, 0.187483, 0.388215, 0.759911, 1.504310",\ + "0.025567, 0.187483, 0.388215, 0.759911, 1.504310",\ + "0.027640, 0.187483, 0.388215, 0.759911, 1.504310",\ + "0.046267, 0.191456, 0.388215, 0.759911, 1.504590"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[34]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011"); + values ( "0.048141, 0.201187, 0.376558, 0.699320, 1.344843",\ + "0.134454, 0.288362, 0.463663, 0.786035, 1.430777",\ + "0.217649, 0.376489, 0.551619, 0.873657, 1.517732",\ + "0.275553, 0.440884, 0.615735, 0.937570, 1.581241",\ + "0.575495, 0.790754, 0.966118, 1.286311, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011"); + values ( "0.024044, 0.299728, 0.633000, 1.248292, 2.473548",\ + "0.028569, 0.300716, 0.634948, 1.248292, 2.473548",\ + "0.041522, 0.302971, 0.634984, 1.248368, 2.473548",\ + "0.053427, 0.306251, 0.635086, 1.249112, 2.473548",\ + "0.129046, 0.344608, 0.641342, 1.252077, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011"); + values ( "0.067740, 0.172889, 0.284335, 0.488454, 0.896691",\ + "0.155151, 0.260208, 0.371616, 0.575759, 0.984044",\ + "0.235509, 0.340542, 0.451643, 0.655787, 1.064076",\ + "0.292201, 0.398091, 0.509186, 0.713032, 1.120723",\ + "0.585993, 0.701429, 0.812818, 1.016046, 1.422500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011"); + values ( "0.024480, 0.186540, 0.386204, 0.757680, 1.500633",\ + "0.024480, 0.186540, 0.386204, 0.757680, 1.500633",\ + "0.025567, 0.186540, 0.386204, 0.757680, 1.500633",\ + "0.027640, 0.187150, 0.386661, 0.758582, 1.502424",\ + "0.046267, 0.191456, 0.386733, 0.759352, 1.504590"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[34]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024044, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\ + "0.212080, 0.166210, 0.136015, 0.124674, 0.138379",\ + "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\ + "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\ + "0.793561, 0.745754, 0.715310, 0.703809, 0.716803"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024480, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\ + "0.265828, 0.190516, 0.122412, 0.099534, 0.163259",\ + "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\ + "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\ + "0.899406, 0.824219, 0.756483, 0.734362, 0.805439"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[34]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024044, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\ + "-0.139884, -0.097456, -0.062994, -0.023072, 0.289162",\ + "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\ + "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\ + "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024480, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\ + "-0.173706, -0.107618, -0.049712, -0.007684, 0.212495",\ + "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\ + "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\ + "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[34]_hldr*/ + +} /* end of pin tl_o[34] */ + +pin("tl_o[33]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002863 ; + + /* Other user defined attributes. */ + original_pin : tl_o[33]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.050484, 0.202933, 0.377869, 0.700194, 1.344843",\ + "0.136927, 0.290107, 0.464973, 0.786907, 1.430777",\ + "0.220698, 0.378233, 0.552927, 0.874529, 1.517732",\ + "0.279184, 0.442625, 0.617042, 0.938441, 1.581241",\ + "0.582638, 0.792504, 0.967419, 1.287178, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.027190, 0.303040, 0.635504, 1.251191, 2.482564",\ + "0.031386, 0.304046, 0.637439, 1.251191, 2.482564",\ + "0.043994, 0.306272, 0.637475, 1.251191, 2.482564",\ + "0.055941, 0.309507, 0.637579, 1.251191, 2.482564",\ + "0.132198, 0.347439, 0.643822, 1.253731, 2.482564"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.069846, 0.173993, 0.285156, 0.488998, 0.896682",\ + "0.157251, 0.261310, 0.372437, 0.576303, 0.984036",\ + "0.237642, 0.341641, 0.452464, 0.656332, 1.064067",\ + "0.294418, 0.399190, 0.510006, 0.713575, 1.120715",\ + "0.589089, 0.702533, 0.813636, 1.016588, 1.422492"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.026653, 0.189312, 0.389207, 0.760903, 1.504295",\ + "0.026653, 0.189463, 0.389709, 0.760903, 1.504295",\ + "0.027645, 0.189463, 0.389709, 0.760903, 1.504295",\ + "0.029626, 0.189463, 0.389709, 0.760903, 1.504295",\ + "0.047836, 0.193360, 0.389709, 0.760903, 1.504575"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[33]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.050484, 0.202933, 0.377869, 0.700194, 1.344843",\ + "0.136927, 0.290107, 0.464973, 0.786907, 1.430777",\ + "0.220698, 0.378233, 0.552927, 0.874529, 1.517732",\ + "0.279184, 0.442625, 0.617042, 0.938441, 1.581241",\ + "0.582638, 0.792504, 0.967419, 1.287178, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.027190, 0.303040, 0.635504, 1.249953, 2.473548",\ + "0.031386, 0.304046, 0.637439, 1.249953, 2.473548",\ + "0.043994, 0.306272, 0.637475, 1.250028, 2.473548",\ + "0.055941, 0.309507, 0.637579, 1.250774, 2.473548",\ + "0.132198, 0.347439, 0.643822, 1.253731, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.069846, 0.173993, 0.285156, 0.488998, 0.896682",\ + "0.157251, 0.261310, 0.372437, 0.576303, 0.984036",\ + "0.237642, 0.341641, 0.452464, 0.656332, 1.064067",\ + "0.294418, 0.399190, 0.510006, 0.713575, 1.120715",\ + "0.589089, 0.702533, 0.813636, 1.016588, 1.422492"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.026653, 0.188505, 0.387697, 0.758671, 1.500618",\ + "0.026653, 0.188505, 0.387697, 0.758671, 1.500618",\ + "0.027645, 0.188505, 0.387697, 0.758671, 1.500618",\ + "0.029626, 0.189113, 0.388156, 0.759574, 1.502409",\ + "0.047836, 0.193360, 0.388231, 0.760346, 1.504575"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[33]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.027190, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\ + "0.213409, 0.167538, 0.137343, 0.126003, 0.139708",\ + "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\ + "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\ + "0.793561, 0.745754, 0.715310, 0.703809, 0.716803"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026653, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\ + "0.266639, 0.191328, 0.123224, 0.100346, 0.164070",\ + "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\ + "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\ + "0.899406, 0.824219, 0.756483, 0.734362, 0.805439"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[33]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.027190, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\ + "-0.141198, -0.098770, -0.064309, -0.024387, 0.287847",\ + "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\ + "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\ + "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026653, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\ + "-0.174512, -0.108425, -0.050519, -0.008491, 0.211689",\ + "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\ + "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\ + "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[33]_hldr*/ + +} /* end of pin tl_o[33] */ + +pin("tl_o[32]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.003362 ; + + /* Other user defined attributes. */ + original_pin : tl_o[32]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.051835, 0.203939, 0.378625, 0.700698, 1.344843",\ + "0.138352, 0.291114, 0.465728, 0.787411, 1.430777",\ + "0.222457, 0.379239, 0.553681, 0.875031, 1.517732",\ + "0.281277, 0.443628, 0.617795, 0.938944, 1.581241",\ + "0.586756, 0.793514, 0.968169, 1.287678, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.029003, 0.304950, 0.636948, 1.252153, 2.482563",\ + "0.033010, 0.305967, 0.638875, 1.252153, 2.482563",\ + "0.045419, 0.308176, 0.638911, 1.252153, 2.482563",\ + "0.057391, 0.311385, 0.639017, 1.252153, 2.482563",\ + "0.134015, 0.349072, 0.645253, 1.254684, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.071047, 0.174622, 0.285622, 0.489305, 0.896671",\ + "0.158449, 0.261939, 0.372903, 0.576610, 0.984024",\ + "0.238859, 0.342267, 0.452930, 0.656639, 1.064056",\ + "0.295683, 0.399817, 0.510471, 0.713882, 1.120704",\ + "0.590856, 0.703163, 0.814100, 1.016894, 1.422481"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.027892, 0.190438, 0.390058, 0.761463, 1.504274",\ + "0.027892, 0.190592, 0.390558, 0.761463, 1.504274",\ + "0.028831, 0.190592, 0.390558, 0.761463, 1.504274",\ + "0.030758, 0.190592, 0.390558, 0.761463, 1.504274",\ + "0.048732, 0.194447, 0.390558, 0.761463, 1.504554"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[32]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.051835, 0.203939, 0.378625, 0.700698, 1.344843",\ + "0.138352, 0.291114, 0.465728, 0.787411, 1.430777",\ + "0.222457, 0.379239, 0.553681, 0.875031, 1.517732",\ + "0.281277, 0.443628, 0.617795, 0.938944, 1.581241",\ + "0.586756, 0.793514, 0.968169, 1.287678, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.029003, 0.304950, 0.636948, 1.250910, 2.473548",\ + "0.033010, 0.305967, 0.638875, 1.250910, 2.473548",\ + "0.045419, 0.308176, 0.638911, 1.250986, 2.473548",\ + "0.057391, 0.311385, 0.639017, 1.251733, 2.473548",\ + "0.134015, 0.349072, 0.645253, 1.254684, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.071047, 0.174622, 0.285622, 0.489305, 0.896671",\ + "0.158449, 0.261939, 0.372903, 0.576610, 0.984024",\ + "0.238859, 0.342267, 0.452930, 0.656639, 1.064056",\ + "0.295683, 0.399817, 0.510471, 0.713882, 1.120704",\ + "0.590856, 0.703163, 0.814100, 1.016894, 1.422481"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.027892, 0.189626, 0.388546, 0.759230, 1.500597",\ + "0.027892, 0.189626, 0.388546, 0.759230, 1.500597",\ + "0.028831, 0.189626, 0.388546, 0.759230, 1.500597",\ + "0.030758, 0.190232, 0.389006, 0.760134, 1.502388",\ + "0.048732, 0.194447, 0.389083, 0.760906, 1.504554"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[32]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.029003, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\ + "0.214175, 0.168305, 0.138110, 0.126769, 0.140474",\ + "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\ + "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\ + "0.793561, 0.745754, 0.715310, 0.703809, 0.716803"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.027892, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\ + "0.267102, 0.191791, 0.123687, 0.100809, 0.164534",\ + "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\ + "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\ + "0.899406, 0.824219, 0.756483, 0.734362, 0.805439"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[32]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.029003, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\ + "-0.141956, -0.099528, -0.065067, -0.025145, 0.287089",\ + "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\ + "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\ + "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.027892, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\ + "-0.174973, -0.108885, -0.050979, -0.008951, 0.211228",\ + "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\ + "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\ + "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[32]_hldr*/ + +} /* end of pin tl_o[32] */ + +pin("tl_o[31]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002343 ; + + /* Other user defined attributes. */ + original_pin : tl_o[31]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.049079, 0.201886, 0.377083, 0.699670, 1.344843",\ + "0.135444, 0.289061, 0.464188, 0.786384, 1.430777",\ + "0.218870, 0.377188, 0.552143, 0.874006, 1.517732",\ + "0.277007, 0.441581, 0.616258, 0.937919, 1.581241",\ + "0.578356, 0.791455, 0.966639, 1.286659, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.025304, 0.301054, 0.634003, 1.250190, 2.482563",\ + "0.029697, 0.302049, 0.635945, 1.250190, 2.482563",\ + "0.042512, 0.304293, 0.635981, 1.250190, 2.482563",\ + "0.054434, 0.307555, 0.636084, 1.250190, 2.482563",\ + "0.130308, 0.345742, 0.642335, 1.252740, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.068622, 0.173351, 0.284684, 0.488692, 0.896707",\ + "0.156030, 0.260670, 0.371965, 0.575997, 0.984061",\ + "0.236402, 0.341002, 0.451991, 0.656025, 1.064092",\ + "0.293129, 0.398551, 0.509534, 0.713269, 1.120740",\ + "0.587289, 0.701891, 0.813166, 1.016283, 1.422517"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.025390, 0.188165, 0.388347, 0.760345, 1.504341",\ + "0.025390, 0.188312, 0.388850, 0.760345, 1.504341",\ + "0.026437, 0.188312, 0.388850, 0.760345, 1.504341",\ + "0.028472, 0.188312, 0.388850, 0.760345, 1.504341",\ + "0.046924, 0.192253, 0.388850, 0.760345, 1.504621"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[31]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.049079, 0.201886, 0.377083, 0.699670, 1.344843",\ + "0.135444, 0.289061, 0.464188, 0.786384, 1.430777",\ + "0.218870, 0.377188, 0.552143, 0.874006, 1.517732",\ + "0.277007, 0.441581, 0.616258, 0.937919, 1.581241",\ + "0.578356, 0.791455, 0.966639, 1.286659, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.025304, 0.301054, 0.634003, 1.248957, 2.473548",\ + "0.029697, 0.302049, 0.635945, 1.248957, 2.473548",\ + "0.042512, 0.304293, 0.635981, 1.249033, 2.473548",\ + "0.054434, 0.307555, 0.636084, 1.249777, 2.473548",\ + "0.130308, 0.345742, 0.642335, 1.252740, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.068622, 0.173351, 0.284684, 0.488692, 0.896707",\ + "0.156030, 0.260670, 0.371965, 0.575997, 0.984061",\ + "0.236402, 0.341002, 0.451991, 0.656025, 1.064092",\ + "0.293129, 0.398551, 0.509534, 0.713269, 1.120740",\ + "0.587289, 0.701891, 0.813166, 1.016283, 1.422517"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.025390, 0.187363, 0.386838, 0.758113, 1.500664",\ + "0.025390, 0.187363, 0.386838, 0.758113, 1.500664",\ + "0.026437, 0.187363, 0.386838, 0.758113, 1.500664",\ + "0.028472, 0.187972, 0.387296, 0.759016, 1.502455",\ + "0.046924, 0.192253, 0.387369, 0.759786, 1.504621"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[31]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025304, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\ + "0.212613, 0.166742, 0.136547, 0.125206, 0.138911",\ + "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\ + "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\ + "0.793561, 0.745754, 0.715310, 0.703809, 0.716803"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025390, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\ + "0.266167, 0.190856, 0.122752, 0.099874, 0.163599",\ + "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\ + "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\ + "0.899406, 0.824219, 0.756483, 0.734362, 0.805439"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[31]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025304, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\ + "-0.140410, -0.097982, -0.063521, -0.023599, 0.288635",\ + "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\ + "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\ + "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025390, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\ + "-0.174043, -0.107956, -0.050050, -0.008022, 0.212157",\ + "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\ + "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\ + "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[31]_hldr*/ + +} /* end of pin tl_o[31] */ + +pin("tl_o[30]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.003362 ; + + /* Other user defined attributes. */ + original_pin : tl_o[30]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.051835, 0.203939, 0.378625, 0.700698, 1.344843",\ + "0.138352, 0.291114, 0.465728, 0.787411, 1.430777",\ + "0.222457, 0.379239, 0.553681, 0.875031, 1.517732",\ + "0.281277, 0.443628, 0.617795, 0.938944, 1.581241",\ + "0.586756, 0.793514, 0.968169, 1.287678, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.029003, 0.304950, 0.636948, 1.252153, 2.482563",\ + "0.033010, 0.305967, 0.638875, 1.252153, 2.482563",\ + "0.045419, 0.308176, 0.638911, 1.252153, 2.482563",\ + "0.057391, 0.311385, 0.639017, 1.252153, 2.482563",\ + "0.134015, 0.349072, 0.645253, 1.254684, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.071047, 0.174622, 0.285622, 0.489305, 0.896671",\ + "0.158449, 0.261939, 0.372903, 0.576610, 0.984024",\ + "0.238859, 0.342267, 0.452930, 0.656639, 1.064056",\ + "0.295683, 0.399817, 0.510471, 0.713882, 1.120704",\ + "0.590856, 0.703163, 0.814100, 1.016894, 1.422481"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.027892, 0.190438, 0.390058, 0.761463, 1.504274",\ + "0.027892, 0.190592, 0.390558, 0.761463, 1.504274",\ + "0.028831, 0.190592, 0.390558, 0.761463, 1.504274",\ + "0.030758, 0.190592, 0.390558, 0.761463, 1.504274",\ + "0.048732, 0.194447, 0.390558, 0.761463, 1.504554"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[30]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.051835, 0.203939, 0.378625, 0.700698, 1.344843",\ + "0.138352, 0.291114, 0.465728, 0.787411, 1.430777",\ + "0.222457, 0.379239, 0.553681, 0.875031, 1.517732",\ + "0.281277, 0.443628, 0.617795, 0.938944, 1.581241",\ + "0.586756, 0.793514, 0.968169, 1.287678, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.029003, 0.304950, 0.636948, 1.250910, 2.473548",\ + "0.033010, 0.305967, 0.638875, 1.250910, 2.473548",\ + "0.045419, 0.308176, 0.638911, 1.250986, 2.473548",\ + "0.057391, 0.311385, 0.639017, 1.251733, 2.473548",\ + "0.134015, 0.349072, 0.645253, 1.254684, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.071047, 0.174622, 0.285622, 0.489305, 0.896671",\ + "0.158449, 0.261939, 0.372903, 0.576610, 0.984024",\ + "0.238859, 0.342267, 0.452930, 0.656639, 1.064056",\ + "0.295683, 0.399817, 0.510471, 0.713882, 1.120704",\ + "0.590856, 0.703163, 0.814100, 1.016894, 1.422481"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.027892, 0.189626, 0.388546, 0.759230, 1.500597",\ + "0.027892, 0.189626, 0.388546, 0.759230, 1.500597",\ + "0.028831, 0.189626, 0.388546, 0.759230, 1.500597",\ + "0.030758, 0.190232, 0.389006, 0.760134, 1.502388",\ + "0.048732, 0.194447, 0.389083, 0.760906, 1.504554"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[30]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.029003, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\ + "0.214175, 0.168305, 0.138110, 0.126769, 0.140474",\ + "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\ + "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\ + "0.793561, 0.745754, 0.715310, 0.703809, 0.716803"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.027892, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\ + "0.267102, 0.191791, 0.123687, 0.100809, 0.164534",\ + "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\ + "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\ + "0.899406, 0.824219, 0.756483, 0.734362, 0.805439"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[30]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.029003, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\ + "-0.141956, -0.099528, -0.065067, -0.025145, 0.287089",\ + "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\ + "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\ + "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.027892, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\ + "-0.174973, -0.108885, -0.050979, -0.008951, 0.211228",\ + "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\ + "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\ + "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[30]_hldr*/ + +} /* end of pin tl_o[30] */ + +pin("tl_o[29]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002863 ; + + /* Other user defined attributes. */ + original_pin : tl_o[29]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.050484, 0.202933, 0.377869, 0.700194, 1.344843",\ + "0.136927, 0.290107, 0.464973, 0.786907, 1.430777",\ + "0.220698, 0.378233, 0.552927, 0.874529, 1.517732",\ + "0.279184, 0.442625, 0.617042, 0.938441, 1.581241",\ + "0.582638, 0.792504, 0.967419, 1.287178, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.027190, 0.303040, 0.635504, 1.251191, 2.482564",\ + "0.031386, 0.304046, 0.637439, 1.251191, 2.482564",\ + "0.043994, 0.306272, 0.637475, 1.251191, 2.482564",\ + "0.055941, 0.309507, 0.637579, 1.251191, 2.482564",\ + "0.132198, 0.347439, 0.643822, 1.253731, 2.482564"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.069846, 0.173993, 0.285156, 0.488998, 0.896682",\ + "0.157251, 0.261310, 0.372437, 0.576303, 0.984036",\ + "0.237642, 0.341641, 0.452464, 0.656332, 1.064067",\ + "0.294418, 0.399190, 0.510006, 0.713575, 1.120715",\ + "0.589089, 0.702533, 0.813636, 1.016588, 1.422492"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.026653, 0.189312, 0.389207, 0.760903, 1.504295",\ + "0.026653, 0.189463, 0.389709, 0.760903, 1.504295",\ + "0.027645, 0.189463, 0.389709, 0.760903, 1.504295",\ + "0.029626, 0.189463, 0.389709, 0.760903, 1.504295",\ + "0.047836, 0.193360, 0.389709, 0.760903, 1.504575"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[29]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.050484, 0.202933, 0.377869, 0.700194, 1.344843",\ + "0.136927, 0.290107, 0.464973, 0.786907, 1.430777",\ + "0.220698, 0.378233, 0.552927, 0.874529, 1.517732",\ + "0.279184, 0.442625, 0.617042, 0.938441, 1.581241",\ + "0.582638, 0.792504, 0.967419, 1.287178, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.027190, 0.303040, 0.635504, 1.249953, 2.473548",\ + "0.031386, 0.304046, 0.637439, 1.249953, 2.473548",\ + "0.043994, 0.306272, 0.637475, 1.250028, 2.473548",\ + "0.055941, 0.309507, 0.637579, 1.250774, 2.473548",\ + "0.132198, 0.347439, 0.643822, 1.253731, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.069846, 0.173993, 0.285156, 0.488998, 0.896682",\ + "0.157251, 0.261310, 0.372437, 0.576303, 0.984036",\ + "0.237642, 0.341641, 0.452464, 0.656332, 1.064067",\ + "0.294418, 0.399190, 0.510006, 0.713575, 1.120715",\ + "0.589089, 0.702533, 0.813636, 1.016588, 1.422492"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.026653, 0.188505, 0.387697, 0.758671, 1.500618",\ + "0.026653, 0.188505, 0.387697, 0.758671, 1.500618",\ + "0.027645, 0.188505, 0.387697, 0.758671, 1.500618",\ + "0.029626, 0.189113, 0.388156, 0.759574, 1.502409",\ + "0.047836, 0.193360, 0.388231, 0.760346, 1.504575"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[29]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.027190, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\ + "0.213409, 0.167538, 0.137343, 0.126003, 0.139708",\ + "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\ + "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\ + "0.793561, 0.745754, 0.715310, 0.703809, 0.716803"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026653, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\ + "0.266639, 0.191328, 0.123224, 0.100346, 0.164070",\ + "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\ + "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\ + "0.899406, 0.824219, 0.756483, 0.734362, 0.805439"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[29]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.027190, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\ + "-0.141198, -0.098770, -0.064309, -0.024387, 0.287847",\ + "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\ + "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\ + "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026653, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\ + "-0.174512, -0.108425, -0.050519, -0.008491, 0.211689",\ + "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\ + "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\ + "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[29]_hldr*/ + +} /* end of pin tl_o[29] */ + +pin("tl_o[28]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001816 ; + + /* Other user defined attributes. */ + original_pin : tl_o[28]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.047653, 0.200824, 0.376286, 0.699138, 1.344843",\ + "0.133940, 0.287998, 0.463391, 0.785853, 1.430777",\ + "0.217014, 0.376126, 0.551347, 0.873475, 1.517732",\ + "0.274798, 0.440522, 0.615463, 0.937389, 1.581241",\ + "0.574010, 0.790389, 0.965848, 1.286131, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.023390, 0.299039, 0.632479, 1.249174, 2.482563",\ + "0.027983, 0.300023, 0.634430, 1.249174, 2.482563",\ + "0.041008, 0.302285, 0.634466, 1.249174, 2.482563",\ + "0.052904, 0.305573, 0.634567, 1.249174, 2.482563",\ + "0.128390, 0.344019, 0.640826, 1.251733, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.067359, 0.172690, 0.284194, 0.488370, 0.896722",\ + "0.154772, 0.260009, 0.371475, 0.575675, 0.984076",\ + "0.235124, 0.340344, 0.451502, 0.655704, 1.064107",\ + "0.291800, 0.397892, 0.509045, 0.712948, 1.120755",\ + "0.585433, 0.701229, 0.812678, 1.015963, 1.422532"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.024087, 0.186982, 0.387454, 0.759758, 1.504368",\ + "0.024087, 0.187126, 0.387958, 0.759758, 1.504368",\ + "0.025192, 0.187126, 0.387958, 0.759758, 1.504368",\ + "0.027281, 0.187126, 0.387958, 0.759758, 1.504368",\ + "0.045983, 0.191111, 0.387958, 0.759758, 1.504648"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[28]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.047653, 0.200824, 0.376286, 0.699138, 1.344843",\ + "0.133940, 0.287998, 0.463391, 0.785853, 1.430777",\ + "0.217014, 0.376126, 0.551347, 0.873475, 1.517732",\ + "0.274798, 0.440522, 0.615463, 0.937389, 1.581241",\ + "0.574010, 0.790389, 0.965848, 1.286131, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.023390, 0.299039, 0.632479, 1.247947, 2.473548",\ + "0.027983, 0.300023, 0.634430, 1.247947, 2.473548",\ + "0.041008, 0.302285, 0.634466, 1.248022, 2.473548",\ + "0.052904, 0.305573, 0.634567, 1.248766, 2.473548",\ + "0.128390, 0.344019, 0.640826, 1.251733, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.067359, 0.172690, 0.284194, 0.488370, 0.896722",\ + "0.154772, 0.260009, 0.371475, 0.575675, 0.984076",\ + "0.235124, 0.340344, 0.451502, 0.655704, 1.064107",\ + "0.291800, 0.397892, 0.509045, 0.712948, 1.120755",\ + "0.585433, 0.701229, 0.812678, 1.015963, 1.422532"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.024087, 0.186184, 0.385947, 0.757528, 1.500690",\ + "0.024087, 0.186184, 0.385947, 0.757528, 1.500690",\ + "0.025192, 0.186184, 0.385947, 0.757528, 1.500690",\ + "0.027281, 0.186796, 0.386404, 0.758430, 1.502482",\ + "0.045983, 0.191111, 0.386476, 0.759200, 1.504648"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[28]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.023390, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\ + "0.211804, 0.165933, 0.135738, 0.124398, 0.138103",\ + "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\ + "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\ + "0.793561, 0.745754, 0.715310, 0.703809, 0.716803"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024087, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\ + "0.265681, 0.190370, 0.122265, 0.099388, 0.163112",\ + "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\ + "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\ + "0.899406, 0.824219, 0.756483, 0.734362, 0.805439"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[28]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.023390, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\ + "-0.139610, -0.097182, -0.062721, -0.022799, 0.289435",\ + "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\ + "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\ + "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024087, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\ + "-0.173560, -0.107472, -0.049566, -0.007539, 0.212641",\ + "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\ + "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\ + "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[28]_hldr*/ + +} /* end of pin tl_o[28] */ + +pin("tl_o[27]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.003525 ; + + /* Other user defined attributes. */ + original_pin : tl_o[27]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011"); + values ( "0.052275, 0.204267, 0.378871, 0.700862, 1.344843",\ + "0.138817, 0.291442, 0.465974, 0.787575, 1.430777",\ + "0.223030, 0.379567, 0.553927, 0.875195, 1.517732",\ + "0.281960, 0.443955, 0.618041, 0.939108, 1.581241",\ + "0.588098, 0.793843, 0.968413, 1.287841, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011"); + values ( "0.029595, 0.305572, 0.637418, 1.252467, 2.482563",\ + "0.033540, 0.306593, 0.639343, 1.252467, 2.482563",\ + "0.045883, 0.308796, 0.639379, 1.252467, 2.482563",\ + "0.057864, 0.311997, 0.639486, 1.252467, 2.482563",\ + "0.134607, 0.349604, 0.645719, 1.254995, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011"); + values ( "0.071419, 0.174817, 0.285764, 0.489395, 0.896657",\ + "0.158819, 0.262134, 0.373045, 0.576700, 0.984010",\ + "0.239235, 0.342461, 0.453072, 0.656729, 1.064042",\ + "0.296074, 0.400011, 0.510613, 0.713972, 1.120690",\ + "0.591402, 0.703358, 0.814241, 1.016983, 1.422467"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011"); + values ( "0.028276, 0.190786, 0.390316, 0.761627, 1.504248",\ + "0.028276, 0.190941, 0.390816, 0.761627, 1.504248",\ + "0.029198, 0.190941, 0.390816, 0.761627, 1.504248",\ + "0.031109, 0.190941, 0.390816, 0.761627, 1.504248",\ + "0.049009, 0.194783, 0.390816, 0.761627, 1.504528"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[27]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011"); + values ( "0.052275, 0.204267, 0.378871, 0.700862, 1.344843",\ + "0.138817, 0.291442, 0.465974, 0.787575, 1.430777",\ + "0.223030, 0.379567, 0.553927, 0.875195, 1.517732",\ + "0.281960, 0.443955, 0.618041, 0.939108, 1.581241",\ + "0.588098, 0.793843, 0.968413, 1.287841, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011"); + values ( "0.029595, 0.305572, 0.637418, 1.251222, 2.473548",\ + "0.033540, 0.306593, 0.639343, 1.251222, 2.473548",\ + "0.045883, 0.308796, 0.639379, 1.251298, 2.473548",\ + "0.057864, 0.311997, 0.639486, 1.252045, 2.473548",\ + "0.134607, 0.349604, 0.645719, 1.254995, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011"); + values ( "0.071419, 0.174817, 0.285764, 0.489395, 0.896657",\ + "0.158819, 0.262134, 0.373045, 0.576700, 0.984010",\ + "0.239235, 0.342461, 0.453072, 0.656729, 1.064042",\ + "0.296074, 0.400011, 0.510613, 0.713972, 1.120690",\ + "0.591402, 0.703358, 0.814241, 1.016983, 1.422467"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011"); + values ( "0.028276, 0.189973, 0.388804, 0.759393, 1.500571",\ + "0.028276, 0.189973, 0.388804, 0.759393, 1.500571",\ + "0.029198, 0.189973, 0.388804, 0.759393, 1.500571",\ + "0.031109, 0.190579, 0.389264, 0.760297, 1.502363",\ + "0.049009, 0.194783, 0.389341, 0.761070, 1.504528"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[27]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.029595, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\ + "0.214425, 0.168554, 0.138359, 0.127019, 0.140724",\ + "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\ + "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\ + "0.793561, 0.745754, 0.715310, 0.703809, 0.716803"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.028276, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\ + "0.267246, 0.191934, 0.123830, 0.100952, 0.164677",\ + "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\ + "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\ + "0.899406, 0.824219, 0.756483, 0.734362, 0.805439"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[27]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.029595, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\ + "-0.142204, -0.099775, -0.065314, -0.025392, 0.286842",\ + "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\ + "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\ + "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.028276, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\ + "-0.175115, -0.109028, -0.051122, -0.009094, 0.211086",\ + "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\ + "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\ + "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[27]_hldr*/ + +} /* end of pin tl_o[27] */ + +pin("tl_o[26]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002267 ; + + /* Other user defined attributes. */ + original_pin : tl_o[26]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011"); + values ( "0.048874, 0.201733, 0.376968, 0.699593, 1.344843",\ + "0.135228, 0.288908, 0.464073, 0.786308, 1.430777",\ + "0.218603, 0.377035, 0.552028, 0.873930, 1.517732",\ + "0.276689, 0.441428, 0.616144, 0.937843, 1.581241",\ + "0.577730, 0.791301, 0.966525, 1.286583, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011"); + values ( "0.025028, 0.300764, 0.633784, 1.250043, 2.482563",\ + "0.029450, 0.301758, 0.635727, 1.250043, 2.482563",\ + "0.042296, 0.304004, 0.635763, 1.250043, 2.482563",\ + "0.054214, 0.307269, 0.635866, 1.250043, 2.482563",\ + "0.130032, 0.345494, 0.642118, 1.252595, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011"); + values ( "0.068432, 0.173252, 0.284609, 0.488641, 0.896705",\ + "0.155842, 0.260570, 0.371890, 0.575946, 0.984059",\ + "0.236211, 0.340904, 0.451917, 0.655975, 1.064090",\ + "0.292930, 0.398452, 0.509460, 0.713219, 1.120738",\ + "0.587011, 0.701792, 0.813092, 1.016233, 1.422515"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011"); + values ( "0.025195, 0.187988, 0.388211, 0.760253, 1.504337",\ + "0.025195, 0.188134, 0.388714, 0.760253, 1.504337",\ + "0.026251, 0.188134, 0.388714, 0.760253, 1.504337",\ + "0.028293, 0.188134, 0.388714, 0.760253, 1.504337",\ + "0.046783, 0.192082, 0.388714, 0.760253, 1.504617"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[26]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011"); + values ( "0.048874, 0.201733, 0.376968, 0.699593, 1.344843",\ + "0.135228, 0.288908, 0.464073, 0.786308, 1.430777",\ + "0.218603, 0.377035, 0.552028, 0.873930, 1.517732",\ + "0.276689, 0.441428, 0.616144, 0.937843, 1.581241",\ + "0.577730, 0.791301, 0.966525, 1.286583, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011"); + values ( "0.025028, 0.300764, 0.633784, 1.248812, 2.473548",\ + "0.029450, 0.301758, 0.635727, 1.248812, 2.473548",\ + "0.042296, 0.304004, 0.635763, 1.248887, 2.473548",\ + "0.054214, 0.307269, 0.635866, 1.249632, 2.473548",\ + "0.130032, 0.345494, 0.642118, 1.252595, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011"); + values ( "0.068432, 0.173252, 0.284609, 0.488641, 0.896705",\ + "0.155842, 0.260570, 0.371890, 0.575946, 0.984059",\ + "0.236211, 0.340904, 0.451917, 0.655975, 1.064090",\ + "0.292930, 0.398452, 0.509460, 0.713219, 1.120738",\ + "0.587011, 0.701792, 0.813092, 1.016233, 1.422515"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011"); + values ( "0.025195, 0.187186, 0.386703, 0.758022, 1.500660",\ + "0.025195, 0.187186, 0.386703, 0.758022, 1.500660",\ + "0.026251, 0.187186, 0.386703, 0.758022, 1.500660",\ + "0.028293, 0.187796, 0.387161, 0.758924, 1.502451",\ + "0.046783, 0.192082, 0.387233, 0.759695, 1.504617"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[26]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025028, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\ + "0.212496, 0.166625, 0.136430, 0.125090, 0.138795",\ + "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\ + "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\ + "0.793561, 0.745754, 0.715310, 0.703809, 0.716803"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025195, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\ + "0.266095, 0.190783, 0.122679, 0.099801, 0.163526",\ + "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\ + "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\ + "0.899406, 0.824219, 0.756483, 0.734362, 0.805439"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[26]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025028, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\ + "-0.140295, -0.097867, -0.063406, -0.023484, 0.288750",\ + "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\ + "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\ + "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025195, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\ + "-0.173971, -0.107884, -0.049978, -0.007950, 0.212230",\ + "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\ + "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\ + "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[26]_hldr*/ + +} /* end of pin tl_o[26] */ + +pin("tl_o[25]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002846 ; + + /* Other user defined attributes. */ + original_pin : tl_o[25]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011"); + values ( "0.050438, 0.202899, 0.377843, 0.700177, 1.344843",\ + "0.136878, 0.290073, 0.464947, 0.786890, 1.430777",\ + "0.220639, 0.378199, 0.552901, 0.874512, 1.517732",\ + "0.279113, 0.442591, 0.617016, 0.938424, 1.581241",\ + "0.582498, 0.792470, 0.967394, 1.287161, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011"); + values ( "0.027128, 0.302975, 0.635455, 1.251158, 2.482563",\ + "0.031331, 0.303981, 0.637390, 1.251158, 2.482563",\ + "0.043946, 0.306208, 0.637426, 1.251158, 2.482563",\ + "0.055892, 0.309444, 0.637531, 1.251158, 2.482563",\ + "0.132136, 0.347384, 0.643774, 1.253699, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011"); + values ( "0.069801, 0.173969, 0.285138, 0.488985, 0.896680",\ + "0.157206, 0.261287, 0.372419, 0.576290, 0.984034",\ + "0.237596, 0.341617, 0.452445, 0.656319, 1.064065",\ + "0.294370, 0.399166, 0.509987, 0.713563, 1.120713",\ + "0.589023, 0.702509, 0.813617, 1.016575, 1.422490"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011"); + values ( "0.026606, 0.189270, 0.389174, 0.760880, 1.504292",\ + "0.026606, 0.189420, 0.389676, 0.760880, 1.504292",\ + "0.027601, 0.189420, 0.389676, 0.760880, 1.504292",\ + "0.029583, 0.189420, 0.389676, 0.760880, 1.504292",\ + "0.047803, 0.193320, 0.389676, 0.760880, 1.504571"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[25]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011"); + values ( "0.050438, 0.202899, 0.377843, 0.700177, 1.344843",\ + "0.136878, 0.290073, 0.464947, 0.786890, 1.430777",\ + "0.220639, 0.378199, 0.552901, 0.874512, 1.517732",\ + "0.279113, 0.442591, 0.617016, 0.938424, 1.581241",\ + "0.582498, 0.792470, 0.967394, 1.287161, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011"); + values ( "0.027128, 0.302975, 0.635455, 1.249921, 2.473548",\ + "0.031331, 0.303981, 0.637390, 1.249921, 2.473548",\ + "0.043946, 0.306208, 0.637426, 1.249996, 2.473548",\ + "0.055892, 0.309444, 0.637531, 1.250742, 2.473548",\ + "0.132136, 0.347384, 0.643774, 1.253699, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011"); + values ( "0.069801, 0.173969, 0.285138, 0.488985, 0.896680",\ + "0.157206, 0.261287, 0.372419, 0.576290, 0.984034",\ + "0.237596, 0.341617, 0.452445, 0.656319, 1.064065",\ + "0.294370, 0.399166, 0.509987, 0.713563, 1.120713",\ + "0.589023, 0.702509, 0.813617, 1.016575, 1.422490"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011"); + values ( "0.026606, 0.188463, 0.387664, 0.758648, 1.500614",\ + "0.026606, 0.188463, 0.387664, 0.758648, 1.500614",\ + "0.027601, 0.188463, 0.387664, 0.758648, 1.500614",\ + "0.029583, 0.189071, 0.388123, 0.759551, 1.502406",\ + "0.047803, 0.193320, 0.388198, 0.760322, 1.504571"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[25]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.027128, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\ + "0.213383, 0.167512, 0.137317, 0.125977, 0.139682",\ + "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\ + "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\ + "0.793561, 0.745754, 0.715310, 0.703809, 0.716803"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\ + "0.266622, 0.191311, 0.123207, 0.100329, 0.164053",\ + "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\ + "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\ + "0.899406, 0.824219, 0.756483, 0.734362, 0.805439"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[25]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.027128, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\ + "-0.141173, -0.098745, -0.064283, -0.024362, 0.287872",\ + "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\ + "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\ + "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\ + "-0.174495, -0.108408, -0.050502, -0.008474, 0.211706",\ + "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\ + "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\ + "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[25]_hldr*/ + +} /* end of pin tl_o[25] */ + +pin("tl_o[24]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.003210 ; + + /* Other user defined attributes. */ + original_pin : tl_o[24]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011"); + values ( "0.051424, 0.203633, 0.378395, 0.700544, 1.344843",\ + "0.137919, 0.290808, 0.465498, 0.787258, 1.430777",\ + "0.221922, 0.378933, 0.553452, 0.874879, 1.517732",\ + "0.280641, 0.443323, 0.617566, 0.938791, 1.581241",\ + "0.585504, 0.793207, 0.967941, 1.287526, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011"); + values ( "0.028452, 0.304369, 0.636509, 1.251860, 2.482563",\ + "0.032517, 0.305383, 0.638438, 1.251860, 2.482563",\ + "0.044986, 0.307597, 0.638475, 1.251860, 2.482563",\ + "0.056951, 0.310815, 0.638580, 1.251860, 2.482563",\ + "0.133463, 0.348576, 0.644818, 1.254395, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011"); + values ( "0.070659, 0.174419, 0.285469, 0.489200, 0.896663",\ + "0.158062, 0.261736, 0.372750, 0.576505, 0.984016",\ + "0.238466, 0.342065, 0.452777, 0.656534, 1.064048",\ + "0.295275, 0.399615, 0.510318, 0.713777, 1.120695",\ + "0.590286, 0.702959, 0.813947, 1.016789, 1.422472"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011"); + values ( "0.027492, 0.190075, 0.389778, 0.761272, 1.504259",\ + "0.027492, 0.190228, 0.390279, 0.761272, 1.504259",\ + "0.028448, 0.190228, 0.390279, 0.761272, 1.504259",\ + "0.030393, 0.190228, 0.390279, 0.761272, 1.504259",\ + "0.048443, 0.194096, 0.390279, 0.761272, 1.504539"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[24]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011"); + values ( "0.051424, 0.203633, 0.378395, 0.700544, 1.344843",\ + "0.137919, 0.290808, 0.465498, 0.787258, 1.430777",\ + "0.221922, 0.378933, 0.553452, 0.874879, 1.517732",\ + "0.280641, 0.443323, 0.617566, 0.938791, 1.581241",\ + "0.585504, 0.793207, 0.967941, 1.287526, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011"); + values ( "0.028452, 0.304369, 0.636509, 1.250620, 2.473548",\ + "0.032517, 0.305383, 0.638438, 1.250620, 2.473548",\ + "0.044986, 0.307597, 0.638475, 1.250695, 2.473548",\ + "0.056951, 0.310815, 0.638580, 1.251441, 2.473548",\ + "0.133463, 0.348576, 0.644818, 1.254395, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011"); + values ( "0.070659, 0.174419, 0.285469, 0.489200, 0.896663",\ + "0.158062, 0.261736, 0.372750, 0.576505, 0.984016",\ + "0.238466, 0.342065, 0.452777, 0.656534, 1.064048",\ + "0.295275, 0.399615, 0.510318, 0.713777, 1.120695",\ + "0.590286, 0.702959, 0.813947, 1.016789, 1.422472"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011"); + values ( "0.027492, 0.189265, 0.388267, 0.759039, 1.500582",\ + "0.027492, 0.189265, 0.388267, 0.759039, 1.500582",\ + "0.028448, 0.189265, 0.388267, 0.759039, 1.500582",\ + "0.030393, 0.189871, 0.388727, 0.759942, 1.502373",\ + "0.048443, 0.194096, 0.388802, 0.760715, 1.504539"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[24]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.028452, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\ + "0.213943, 0.168072, 0.137877, 0.126536, 0.140241",\ + "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\ + "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\ + "0.793561, 0.745754, 0.715310, 0.703809, 0.716803"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.027492, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\ + "0.266953, 0.191642, 0.123538, 0.100660, 0.164384",\ + "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\ + "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\ + "0.899406, 0.824219, 0.756483, 0.734362, 0.805439"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[24]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.028452, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\ + "-0.141726, -0.099298, -0.064837, -0.024915, 0.287319",\ + "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\ + "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\ + "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.027492, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\ + "-0.174824, -0.108737, -0.050831, -0.008803, 0.211377",\ + "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\ + "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\ + "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[24]_hldr*/ + +} /* end of pin tl_o[24] */ + +pin("tl_o[23]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002308 ; + + /* Other user defined attributes. */ + original_pin : tl_o[23]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011"); + values ( "0.048983, 0.201815, 0.377030, 0.699634, 1.344843",\ + "0.135344, 0.288990, 0.464134, 0.786349, 1.430777",\ + "0.218746, 0.377117, 0.552089, 0.873970, 1.517732",\ + "0.276859, 0.441510, 0.616205, 0.937884, 1.581241",\ + "0.578065, 0.791383, 0.966586, 1.286623, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011"); + values ( "0.025176, 0.300919, 0.633901, 1.250122, 2.482564",\ + "0.029582, 0.301914, 0.635844, 1.250122, 2.482564",\ + "0.042411, 0.304159, 0.635880, 1.250122, 2.482564",\ + "0.054332, 0.307422, 0.635983, 1.250122, 2.482564",\ + "0.130180, 0.345627, 0.642234, 1.252672, 2.482564"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011"); + values ( "0.068536, 0.173307, 0.284651, 0.488670, 0.896708",\ + "0.155945, 0.260625, 0.371931, 0.575975, 0.984061",\ + "0.236316, 0.340958, 0.451958, 0.656003, 1.064093",\ + "0.293039, 0.398507, 0.509501, 0.713248, 1.120741",\ + "0.587164, 0.701846, 0.813133, 1.016261, 1.422517"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011"); + values ( "0.025302, 0.188085, 0.388286, 0.760305, 1.504342",\ + "0.025302, 0.188232, 0.388789, 0.760305, 1.504342",\ + "0.026353, 0.188232, 0.388789, 0.760305, 1.504342",\ + "0.028391, 0.188232, 0.388789, 0.760305, 1.504342",\ + "0.046861, 0.192176, 0.388789, 0.760305, 1.504622"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[23]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011"); + values ( "0.048983, 0.201815, 0.377030, 0.699634, 1.344843",\ + "0.135344, 0.288990, 0.464134, 0.786349, 1.430777",\ + "0.218746, 0.377117, 0.552089, 0.873970, 1.517732",\ + "0.276859, 0.441510, 0.616205, 0.937884, 1.581241",\ + "0.578065, 0.791383, 0.966586, 1.286623, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011"); + values ( "0.025176, 0.300919, 0.633901, 1.248890, 2.473548",\ + "0.029582, 0.301914, 0.635844, 1.248890, 2.473548",\ + "0.042411, 0.304159, 0.635880, 1.248965, 2.473548",\ + "0.054332, 0.307422, 0.635983, 1.249710, 2.473548",\ + "0.130180, 0.345627, 0.642234, 1.252672, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011"); + values ( "0.068536, 0.173307, 0.284651, 0.488670, 0.896708",\ + "0.155945, 0.260625, 0.371931, 0.575975, 0.984061",\ + "0.236316, 0.340958, 0.451958, 0.656003, 1.064093",\ + "0.293039, 0.398507, 0.509501, 0.713248, 1.120741",\ + "0.587164, 0.701846, 0.813133, 1.016261, 1.422517"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011"); + values ( "0.025302, 0.187283, 0.386778, 0.758074, 1.500664",\ + "0.025302, 0.187283, 0.386778, 0.758074, 1.500664",\ + "0.026353, 0.187283, 0.386778, 0.758074, 1.500664",\ + "0.028391, 0.187893, 0.387236, 0.758976, 1.502456",\ + "0.046861, 0.192176, 0.387309, 0.759746, 1.504622"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[23]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025176, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\ + "0.212558, 0.166688, 0.136493, 0.125152, 0.138857",\ + "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\ + "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\ + "0.793561, 0.745754, 0.715310, 0.703809, 0.716803"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025302, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\ + "0.266135, 0.190823, 0.122719, 0.099841, 0.163566",\ + "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\ + "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\ + "0.899406, 0.824219, 0.756483, 0.734362, 0.805439"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[23]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025176, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\ + "-0.140357, -0.097929, -0.063467, -0.023545, 0.288689",\ + "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\ + "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\ + "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025302, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\ + "-0.174011, -0.107923, -0.050017, -0.007990, 0.212190",\ + "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\ + "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\ + "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[23]_hldr*/ + +} /* end of pin tl_o[23] */ + +pin("tl_o[22]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002254 ; + + /* Other user defined attributes. */ + original_pin : tl_o[22]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.048838, 0.201706, 0.376948, 0.699580, 1.344843",\ + "0.135190, 0.288881, 0.464053, 0.786294, 1.430777",\ + "0.218556, 0.377008, 0.552008, 0.873916, 1.517732",\ + "0.276634, 0.441402, 0.616124, 0.937829, 1.581241",\ + "0.577621, 0.791275, 0.966506, 1.286569, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.024980, 0.300714, 0.633745, 1.250018, 2.482564",\ + "0.029407, 0.301707, 0.635689, 1.250018, 2.482564",\ + "0.042258, 0.303954, 0.635725, 1.250018, 2.482564",\ + "0.054175, 0.307220, 0.635828, 1.250018, 2.482564",\ + "0.129984, 0.345451, 0.642080, 1.252569, 2.482564"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.068404, 0.173238, 0.284599, 0.488635, 0.896708",\ + "0.155814, 0.260556, 0.371880, 0.575940, 0.984061",\ + "0.236182, 0.340889, 0.451907, 0.655969, 1.064093",\ + "0.292900, 0.398438, 0.509450, 0.713213, 1.120741",\ + "0.586970, 0.701777, 0.813081, 1.016227, 1.422517"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.025166, 0.187961, 0.388192, 0.760242, 1.504342",\ + "0.025166, 0.188108, 0.388695, 0.760242, 1.504342",\ + "0.026223, 0.188108, 0.388695, 0.760242, 1.504342",\ + "0.028267, 0.188108, 0.388695, 0.760242, 1.504342",\ + "0.046762, 0.192057, 0.388695, 0.760242, 1.504622"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[22]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.048838, 0.201706, 0.376948, 0.699580, 1.344843",\ + "0.135190, 0.288881, 0.464053, 0.786294, 1.430777",\ + "0.218556, 0.377008, 0.552008, 0.873916, 1.517732",\ + "0.276634, 0.441402, 0.616124, 0.937829, 1.581241",\ + "0.577621, 0.791275, 0.966506, 1.286569, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.024980, 0.300714, 0.633745, 1.248787, 2.473548",\ + "0.029407, 0.301707, 0.635689, 1.248787, 2.473548",\ + "0.042258, 0.303954, 0.635725, 1.248862, 2.473548",\ + "0.054175, 0.307220, 0.635828, 1.249606, 2.473548",\ + "0.129984, 0.345451, 0.642080, 1.252569, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.068404, 0.173238, 0.284599, 0.488635, 0.896708",\ + "0.155814, 0.260556, 0.371880, 0.575940, 0.984061",\ + "0.236182, 0.340889, 0.451907, 0.655969, 1.064093",\ + "0.292900, 0.398438, 0.509450, 0.713213, 1.120741",\ + "0.586970, 0.701777, 0.813081, 1.016227, 1.422517"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.025166, 0.187160, 0.386684, 0.758011, 1.500664",\ + "0.025166, 0.187160, 0.386684, 0.758011, 1.500664",\ + "0.026223, 0.187160, 0.386684, 0.758011, 1.500664",\ + "0.028267, 0.187770, 0.387142, 0.758913, 1.502456",\ + "0.046762, 0.192057, 0.387215, 0.759684, 1.504622"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[22]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024980, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\ + "0.212476, 0.166605, 0.136410, 0.125070, 0.138775",\ + "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\ + "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\ + "0.793561, 0.745754, 0.715310, 0.703809, 0.716803"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025166, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\ + "0.266084, 0.190773, 0.122668, 0.099790, 0.163515",\ + "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\ + "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\ + "0.899406, 0.824219, 0.756483, 0.734362, 0.805439"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[22]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024980, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\ + "-0.140275, -0.097847, -0.063386, -0.023464, 0.288770",\ + "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\ + "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\ + "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025166, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\ + "-0.173960, -0.107873, -0.049967, -0.007939, 0.212241",\ + "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\ + "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\ + "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[22]_hldr*/ + +} /* end of pin tl_o[22] */ + +pin("tl_o[21]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.003224 ; + + /* Other user defined attributes. */ + original_pin : tl_o[21]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011"); + values ( "0.051460, 0.203660, 0.378415, 0.700558, 1.344843",\ + "0.137957, 0.290835, 0.465518, 0.787271, 1.430777",\ + "0.221969, 0.378960, 0.553472, 0.874892, 1.517732",\ + "0.280696, 0.443350, 0.617586, 0.938804, 1.581241",\ + "0.585613, 0.793234, 0.967961, 1.287539, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011"); + values ( "0.028500, 0.304420, 0.636547, 1.251886, 2.482563",\ + "0.032560, 0.305434, 0.638476, 1.251886, 2.482563",\ + "0.045023, 0.307647, 0.638513, 1.251886, 2.482563",\ + "0.056989, 0.310864, 0.638618, 1.251886, 2.482563",\ + "0.133511, 0.348619, 0.644856, 1.254420, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011"); + values ( "0.070687, 0.174433, 0.285479, 0.489206, 0.896660",\ + "0.158090, 0.261751, 0.372760, 0.576511, 0.984014",\ + "0.238494, 0.342080, 0.452787, 0.656540, 1.064045",\ + "0.295304, 0.399629, 0.510328, 0.713783, 1.120693",\ + "0.590327, 0.702974, 0.813957, 1.016795, 1.422470"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011"); + values ( "0.027521, 0.190101, 0.389797, 0.761283, 1.504255",\ + "0.027521, 0.190254, 0.390298, 0.761283, 1.504255",\ + "0.028476, 0.190254, 0.390298, 0.761283, 1.504255",\ + "0.030419, 0.190254, 0.390298, 0.761283, 1.504255",\ + "0.048464, 0.194122, 0.390298, 0.761283, 1.504535"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[21]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011"); + values ( "0.051460, 0.203660, 0.378415, 0.700558, 1.344843",\ + "0.137957, 0.290835, 0.465518, 0.787271, 1.430777",\ + "0.221969, 0.378960, 0.553472, 0.874892, 1.517732",\ + "0.280696, 0.443350, 0.617586, 0.938804, 1.581241",\ + "0.585613, 0.793234, 0.967961, 1.287539, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011"); + values ( "0.028500, 0.304420, 0.636547, 1.250645, 2.473547",\ + "0.032560, 0.305434, 0.638476, 1.250645, 2.473547",\ + "0.045023, 0.307647, 0.638513, 1.250720, 2.473547",\ + "0.056989, 0.310864, 0.638618, 1.251467, 2.473547",\ + "0.133511, 0.348619, 0.644856, 1.254420, 2.473547"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011"); + values ( "0.070687, 0.174433, 0.285479, 0.489206, 0.896660",\ + "0.158090, 0.261751, 0.372760, 0.576511, 0.984014",\ + "0.238494, 0.342080, 0.452787, 0.656540, 1.064045",\ + "0.295304, 0.399629, 0.510328, 0.713783, 1.120693",\ + "0.590327, 0.702974, 0.813957, 1.016795, 1.422470"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011"); + values ( "0.027521, 0.189291, 0.388286, 0.759050, 1.500578",\ + "0.027521, 0.189291, 0.388286, 0.759050, 1.500578",\ + "0.028476, 0.189291, 0.388286, 0.759050, 1.500578",\ + "0.030419, 0.189897, 0.388745, 0.759953, 1.502369",\ + "0.048464, 0.194122, 0.388821, 0.760726, 1.504535"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[21]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.028500, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\ + "0.213963, 0.168092, 0.137897, 0.126557, 0.140261",\ + "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\ + "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\ + "0.793561, 0.745754, 0.715310, 0.703809, 0.716803"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.027521, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\ + "0.266964, 0.191653, 0.123548, 0.100670, 0.164395",\ + "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\ + "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\ + "0.899406, 0.824219, 0.756483, 0.734362, 0.805439"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[21]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.028500, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\ + "-0.141746, -0.099318, -0.064857, -0.024935, 0.287299",\ + "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\ + "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\ + "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.027521, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\ + "-0.174835, -0.108748, -0.050842, -0.008814, 0.211366",\ + "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\ + "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\ + "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[21]_hldr*/ + +} /* end of pin tl_o[21] */ + +pin("tl_o[20]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001805 ; + + /* Other user defined attributes. */ + original_pin : tl_o[20]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.047624, 0.200802, 0.376269, 0.699127, 1.344843",\ + "0.133909, 0.287977, 0.463375, 0.785842, 1.430777",\ + "0.216976, 0.376105, 0.551331, 0.873464, 1.517732",\ + "0.274753, 0.440500, 0.615446, 0.937378, 1.581241",\ + "0.573921, 0.790368, 0.965832, 1.286120, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.023351, 0.298998, 0.632448, 1.249153, 2.482563",\ + "0.027948, 0.299981, 0.634399, 1.249153, 2.482563",\ + "0.040978, 0.302244, 0.634435, 1.249153, 2.482563",\ + "0.052873, 0.305533, 0.634536, 1.249153, 2.482563",\ + "0.128351, 0.343984, 0.640795, 1.251713, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.067343, 0.172682, 0.284189, 0.488369, 0.896728",\ + "0.154756, 0.260000, 0.371470, 0.575674, 0.984081",\ + "0.235108, 0.340335, 0.451497, 0.655702, 1.064113",\ + "0.291783, 0.397884, 0.509040, 0.712947, 1.120760",\ + "0.585410, 0.701221, 0.812673, 1.015961, 1.422537"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.024071, 0.186967, 0.387445, 0.759756, 1.504378",\ + "0.024071, 0.187111, 0.387949, 0.759756, 1.504378",\ + "0.025176, 0.187111, 0.387949, 0.759756, 1.504378",\ + "0.027266, 0.187111, 0.387949, 0.759756, 1.504378",\ + "0.045971, 0.191097, 0.387949, 0.759756, 1.504658"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[20]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.047624, 0.200802, 0.376269, 0.699127, 1.344843",\ + "0.133909, 0.287977, 0.463375, 0.785842, 1.430777",\ + "0.216976, 0.376105, 0.551331, 0.873464, 1.517732",\ + "0.274753, 0.440500, 0.615446, 0.937378, 1.581241",\ + "0.573921, 0.790368, 0.965832, 1.286120, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.023351, 0.298998, 0.632448, 1.247926, 2.473548",\ + "0.027948, 0.299981, 0.634399, 1.247926, 2.473548",\ + "0.040978, 0.302244, 0.634435, 1.248002, 2.473548",\ + "0.052873, 0.305533, 0.634536, 1.248745, 2.473548",\ + "0.128351, 0.343984, 0.640795, 1.251713, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.067343, 0.172682, 0.284189, 0.488369, 0.896728",\ + "0.154756, 0.260000, 0.371470, 0.575674, 0.984081",\ + "0.235108, 0.340335, 0.451497, 0.655702, 1.064113",\ + "0.291783, 0.397884, 0.509040, 0.712947, 1.120760",\ + "0.585410, 0.701221, 0.812673, 1.015961, 1.422537"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.024071, 0.186169, 0.385939, 0.757526, 1.500700",\ + "0.024071, 0.186169, 0.385939, 0.757526, 1.500700",\ + "0.025176, 0.186169, 0.385939, 0.757526, 1.500700",\ + "0.027266, 0.186781, 0.386395, 0.758427, 1.502492",\ + "0.045971, 0.191097, 0.386467, 0.759197, 1.504658"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[20]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.023351, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\ + "0.211788, 0.165917, 0.135722, 0.124381, 0.138086",\ + "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\ + "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\ + "0.793561, 0.745754, 0.715310, 0.703809, 0.716803"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024071, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\ + "0.265675, 0.190363, 0.122259, 0.099381, 0.163106",\ + "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\ + "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\ + "0.899406, 0.824219, 0.756483, 0.734362, 0.805439"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[20]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.023351, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\ + "-0.139594, -0.097166, -0.062704, -0.022783, 0.289451",\ + "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\ + "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\ + "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024071, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\ + "-0.173554, -0.107466, -0.049560, -0.007532, 0.212647",\ + "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\ + "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\ + "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[20]_hldr*/ + +} /* end of pin tl_o[20] */ + +pin("tl_o[19]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002405 ; + + /* Other user defined attributes. */ + original_pin : tl_o[19]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011"); + values ( "0.049247, 0.202011, 0.377177, 0.699733, 1.344843",\ + "0.135622, 0.289186, 0.464282, 0.786447, 1.430777",\ + "0.219089, 0.377313, 0.552236, 0.874068, 1.517732",\ + "0.277267, 0.441706, 0.616352, 0.937981, 1.581241",\ + "0.578868, 0.791580, 0.966732, 1.286721, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011"); + values ( "0.025529, 0.301292, 0.634182, 1.250309, 2.482563",\ + "0.029899, 0.302288, 0.636124, 1.250309, 2.482563",\ + "0.042689, 0.304530, 0.636160, 1.250309, 2.482563",\ + "0.054614, 0.307788, 0.636263, 1.250309, 2.482563",\ + "0.130534, 0.345945, 0.642513, 1.252858, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011"); + values ( "0.068762, 0.173425, 0.284737, 0.488725, 0.896701",\ + "0.156170, 0.260743, 0.372018, 0.576030, 0.984055",\ + "0.236545, 0.341075, 0.452045, 0.656059, 1.064086",\ + "0.293277, 0.398624, 0.509587, 0.713303, 1.120734",\ + "0.587496, 0.701965, 0.813219, 1.016316, 1.422511"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011"); + values ( "0.025535, 0.188296, 0.388444, 0.760406, 1.504329",\ + "0.025535, 0.188444, 0.388947, 0.760406, 1.504329",\ + "0.026576, 0.188444, 0.388947, 0.760406, 1.504329",\ + "0.028604, 0.188444, 0.388947, 0.760406, 1.504329",\ + "0.047029, 0.192380, 0.388947, 0.760406, 1.504609"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[19]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011"); + values ( "0.049247, 0.202011, 0.377177, 0.699733, 1.344843",\ + "0.135622, 0.289186, 0.464282, 0.786447, 1.430777",\ + "0.219089, 0.377313, 0.552236, 0.874068, 1.517732",\ + "0.277267, 0.441706, 0.616352, 0.937981, 1.581241",\ + "0.578868, 0.791580, 0.966732, 1.286721, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011"); + values ( "0.025529, 0.301292, 0.634182, 1.249076, 2.473548",\ + "0.029899, 0.302288, 0.636124, 1.249076, 2.473548",\ + "0.042689, 0.304530, 0.636160, 1.249152, 2.473548",\ + "0.054614, 0.307788, 0.636263, 1.249897, 2.473548",\ + "0.130534, 0.345945, 0.642513, 1.252858, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011"); + values ( "0.068762, 0.173425, 0.284737, 0.488725, 0.896701",\ + "0.156170, 0.260743, 0.372018, 0.576030, 0.984055",\ + "0.236545, 0.341075, 0.452045, 0.656059, 1.064086",\ + "0.293277, 0.398624, 0.509587, 0.713303, 1.120734",\ + "0.587496, 0.701965, 0.813219, 1.016316, 1.422511"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011"); + values ( "0.025535, 0.187494, 0.386936, 0.758174, 1.500652",\ + "0.025535, 0.187494, 0.386936, 0.758174, 1.500652",\ + "0.026576, 0.187494, 0.386936, 0.758174, 1.500652",\ + "0.028604, 0.188103, 0.387393, 0.759077, 1.502444",\ + "0.047029, 0.192380, 0.387467, 0.759848, 1.504609"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[19]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025529, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\ + "0.212708, 0.166837, 0.136642, 0.125302, 0.139006",\ + "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\ + "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\ + "0.793561, 0.745754, 0.715310, 0.703809, 0.716803"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025535, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\ + "0.266222, 0.190910, 0.122806, 0.099928, 0.163653",\ + "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\ + "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\ + "0.899406, 0.824219, 0.756483, 0.734362, 0.805439"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[19]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025529, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\ + "-0.140504, -0.098076, -0.063615, -0.023693, 0.288541",\ + "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\ + "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\ + "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025535, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\ + "-0.174097, -0.108010, -0.050104, -0.008076, 0.212104",\ + "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\ + "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\ + "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[19]_hldr*/ + +} /* end of pin tl_o[19] */ + +pin("tl_o[18]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002343 ; + + /* Other user defined attributes. */ + original_pin : tl_o[18]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.049079, 0.201886, 0.377083, 0.699670, 1.344843",\ + "0.135444, 0.289061, 0.464188, 0.786384, 1.430777",\ + "0.218870, 0.377188, 0.552143, 0.874006, 1.517732",\ + "0.277007, 0.441581, 0.616258, 0.937919, 1.581241",\ + "0.578356, 0.791455, 0.966639, 1.286659, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.025304, 0.301054, 0.634003, 1.250190, 2.482563",\ + "0.029697, 0.302049, 0.635945, 1.250190, 2.482563",\ + "0.042512, 0.304293, 0.635981, 1.250190, 2.482563",\ + "0.054434, 0.307555, 0.636084, 1.250190, 2.482563",\ + "0.130308, 0.345742, 0.642335, 1.252740, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.068622, 0.173351, 0.284684, 0.488692, 0.896707",\ + "0.156030, 0.260670, 0.371965, 0.575997, 0.984061",\ + "0.236402, 0.341002, 0.451991, 0.656025, 1.064092",\ + "0.293129, 0.398551, 0.509534, 0.713269, 1.120740",\ + "0.587289, 0.701891, 0.813166, 1.016283, 1.422517"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.025390, 0.188165, 0.388347, 0.760345, 1.504341",\ + "0.025390, 0.188312, 0.388850, 0.760345, 1.504341",\ + "0.026437, 0.188312, 0.388850, 0.760345, 1.504341",\ + "0.028472, 0.188312, 0.388850, 0.760345, 1.504341",\ + "0.046924, 0.192253, 0.388850, 0.760345, 1.504621"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[18]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.049079, 0.201886, 0.377083, 0.699670, 1.344843",\ + "0.135444, 0.289061, 0.464188, 0.786384, 1.430777",\ + "0.218870, 0.377188, 0.552143, 0.874006, 1.517732",\ + "0.277007, 0.441581, 0.616258, 0.937919, 1.581241",\ + "0.578356, 0.791455, 0.966639, 1.286659, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.025304, 0.301054, 0.634003, 1.248957, 2.473548",\ + "0.029697, 0.302049, 0.635945, 1.248957, 2.473548",\ + "0.042512, 0.304293, 0.635981, 1.249033, 2.473548",\ + "0.054434, 0.307555, 0.636084, 1.249777, 2.473548",\ + "0.130308, 0.345742, 0.642335, 1.252740, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.068622, 0.173351, 0.284684, 0.488692, 0.896707",\ + "0.156030, 0.260670, 0.371965, 0.575997, 0.984061",\ + "0.236402, 0.341002, 0.451991, 0.656025, 1.064092",\ + "0.293129, 0.398551, 0.509534, 0.713269, 1.120740",\ + "0.587289, 0.701891, 0.813166, 1.016283, 1.422517"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.025390, 0.187363, 0.386838, 0.758113, 1.500664",\ + "0.025390, 0.187363, 0.386838, 0.758113, 1.500664",\ + "0.026437, 0.187363, 0.386838, 0.758113, 1.500664",\ + "0.028472, 0.187972, 0.387296, 0.759016, 1.502455",\ + "0.046924, 0.192253, 0.387369, 0.759786, 1.504621"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[18]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025304, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\ + "0.212613, 0.166742, 0.136547, 0.125206, 0.138911",\ + "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\ + "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\ + "0.793561, 0.745754, 0.715310, 0.703809, 0.716803"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025390, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\ + "0.266167, 0.190856, 0.122752, 0.099874, 0.163599",\ + "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\ + "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\ + "0.899406, 0.824219, 0.756483, 0.734362, 0.805439"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[18]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025304, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\ + "-0.140410, -0.097982, -0.063521, -0.023599, 0.288635",\ + "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\ + "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\ + "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025390, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\ + "-0.174043, -0.107956, -0.050050, -0.008022, 0.212157",\ + "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\ + "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\ + "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[18]_hldr*/ + +} /* end of pin tl_o[18] */ + +pin("tl_o[17]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001292 ; + + /* Other user defined attributes. */ + original_pin : tl_o[17]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011"); + values ( "0.046108, 0.199767, 0.375492, 0.698609, 1.344843",\ + "0.132284, 0.286942, 0.462599, 0.785325, 1.430777",\ + "0.214897, 0.375071, 0.550555, 0.872948, 1.517732",\ + "0.272255, 0.439468, 0.614671, 0.936861, 1.581241",\ + "0.568906, 0.789330, 0.965061, 1.285606, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011"); + values ( "0.021470, 0.297034, 0.630964, 1.248164, 2.482563",\ + "0.026264, 0.298006, 0.632922, 1.248164, 2.482563",\ + "0.039476, 0.300287, 0.632958, 1.248164, 2.482563",\ + "0.051325, 0.303602, 0.633057, 1.248164, 2.482563",\ + "0.126317, 0.342305, 0.639325, 1.250732, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011"); + values ( "0.065928, 0.172045, 0.283720, 0.488064, 0.896750",\ + "0.153370, 0.259364, 0.371001, 0.575369, 0.984104",\ + "0.233677, 0.339702, 0.451028, 0.655397, 1.064135",\ + "0.290278, 0.397250, 0.508572, 0.712642, 1.120783",\ + "0.583192, 0.700584, 0.812206, 1.015657, 1.422559"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011"); + values ( "0.022780, 0.185829, 0.386590, 0.759200, 1.504419",\ + "0.022780, 0.185969, 0.387096, 0.759200, 1.504419",\ + "0.023886, 0.185969, 0.387096, 0.759200, 1.504419",\ + "0.026044, 0.185969, 0.387096, 0.759200, 1.504419",\ + "0.044904, 0.189998, 0.387096, 0.759200, 1.504699"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[17]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011"); + values ( "0.046108, 0.199767, 0.375492, 0.698609, 1.344843",\ + "0.132284, 0.286942, 0.462599, 0.785325, 1.430777",\ + "0.214897, 0.375071, 0.550555, 0.872948, 1.517732",\ + "0.272255, 0.439468, 0.614671, 0.936861, 1.581241",\ + "0.568906, 0.789330, 0.965061, 1.285606, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011"); + values ( "0.021470, 0.297034, 0.630964, 1.246942, 2.473548",\ + "0.026264, 0.298006, 0.632922, 1.246942, 2.473548",\ + "0.039476, 0.300287, 0.632958, 1.247017, 2.473548",\ + "0.051325, 0.303602, 0.633057, 1.247760, 2.473548",\ + "0.126317, 0.342305, 0.639325, 1.250732, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011"); + values ( "0.065928, 0.172045, 0.283720, 0.488064, 0.896750",\ + "0.153370, 0.259364, 0.371001, 0.575369, 0.984104",\ + "0.233677, 0.339702, 0.451028, 0.655397, 1.064135",\ + "0.290278, 0.397250, 0.508572, 0.712642, 1.120783",\ + "0.583192, 0.700584, 0.812206, 1.015657, 1.422559"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011"); + values ( "0.022780, 0.185036, 0.385085, 0.756971, 1.500741",\ + "0.022780, 0.185036, 0.385085, 0.756971, 1.500741",\ + "0.023886, 0.185036, 0.385085, 0.756971, 1.500741",\ + "0.026044, 0.185649, 0.385541, 0.757872, 1.502533",\ + "0.044904, 0.189998, 0.385611, 0.758640, 1.504699"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[17]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.021470, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\ + "0.210993, 0.165122, 0.134927, 0.123587, 0.137292",\ + "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\ + "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\ + "0.793561, 0.745754, 0.715310, 0.703809, 0.716803"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.022780, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\ + "0.265192, 0.189881, 0.121777, 0.098899, 0.162623",\ + "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\ + "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\ + "0.899406, 0.824219, 0.756483, 0.734362, 0.805439"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[17]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.021470, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\ + "-0.138808, -0.096380, -0.061918, -0.021997, 0.290238",\ + "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\ + "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\ + "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.022780, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\ + "-0.173074, -0.106987, -0.049081, -0.007053, 0.213127",\ + "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\ + "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\ + "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[17]_hldr*/ + +} /* end of pin tl_o[17] */ + +pin("tl_o[16]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001808 ; + + /* Other user defined attributes. */ + original_pin : tl_o[16]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011"); + values ( "0.047630, 0.200806, 0.376273, 0.699130, 1.344843",\ + "0.133916, 0.287981, 0.463378, 0.785845, 1.430777",\ + "0.216984, 0.376109, 0.551334, 0.873467, 1.517732",\ + "0.274762, 0.440505, 0.615450, 0.937380, 1.581241",\ + "0.573940, 0.790372, 0.965835, 1.286123, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011"); + values ( "0.023359, 0.299007, 0.632455, 1.249158, 2.482563",\ + "0.027955, 0.299990, 0.634405, 1.249158, 2.482563",\ + "0.040984, 0.302252, 0.634441, 1.249158, 2.482563",\ + "0.052879, 0.305541, 0.634542, 1.249158, 2.482563",\ + "0.128359, 0.343991, 0.640802, 1.251717, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011"); + values ( "0.067337, 0.172678, 0.284185, 0.488364, 0.896721",\ + "0.154749, 0.259997, 0.371466, 0.575669, 0.984075",\ + "0.235101, 0.340332, 0.451493, 0.655697, 1.064106",\ + "0.291776, 0.397881, 0.509036, 0.712942, 1.120754",\ + "0.585400, 0.701218, 0.812669, 1.015956, 1.422531"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011"); + values ( "0.024064, 0.186961, 0.387438, 0.759747, 1.504366",\ + "0.024064, 0.187105, 0.387942, 0.759747, 1.504366",\ + "0.025170, 0.187105, 0.387942, 0.759747, 1.504366",\ + "0.027260, 0.187105, 0.387942, 0.759747, 1.504366",\ + "0.045966, 0.191091, 0.387942, 0.759747, 1.504646"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[16]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011"); + values ( "0.047630, 0.200806, 0.376273, 0.699130, 1.344843",\ + "0.133916, 0.287981, 0.463378, 0.785845, 1.430777",\ + "0.216984, 0.376109, 0.551334, 0.873467, 1.517732",\ + "0.274762, 0.440505, 0.615450, 0.937380, 1.581241",\ + "0.573940, 0.790372, 0.965835, 1.286123, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011"); + values ( "0.023359, 0.299007, 0.632455, 1.247931, 2.473548",\ + "0.027955, 0.299990, 0.634405, 1.247931, 2.473548",\ + "0.040984, 0.302252, 0.634441, 1.248006, 2.473548",\ + "0.052879, 0.305541, 0.634542, 1.248749, 2.473548",\ + "0.128359, 0.343991, 0.640802, 1.251717, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011"); + values ( "0.067337, 0.172678, 0.284185, 0.488364, 0.896721",\ + "0.154749, 0.259997, 0.371466, 0.575669, 0.984075",\ + "0.235101, 0.340332, 0.451493, 0.655697, 1.064106",\ + "0.291776, 0.397881, 0.509036, 0.712942, 1.120754",\ + "0.585400, 0.701218, 0.812669, 1.015956, 1.422531"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011"); + values ( "0.024064, 0.186164, 0.385931, 0.757517, 1.500689",\ + "0.024064, 0.186164, 0.385931, 0.757517, 1.500689",\ + "0.025170, 0.186164, 0.385931, 0.757517, 1.500689",\ + "0.027260, 0.186775, 0.386388, 0.758419, 1.502481",\ + "0.045966, 0.191091, 0.386459, 0.759188, 1.504646"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[16]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.023359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\ + "0.211791, 0.165920, 0.135725, 0.124385, 0.138090",\ + "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\ + "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\ + "0.793561, 0.745754, 0.715310, 0.703809, 0.716803"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024064, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\ + "0.265672, 0.190361, 0.122257, 0.099379, 0.163103",\ + "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\ + "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\ + "0.899406, 0.824219, 0.756483, 0.734362, 0.805439"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[16]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.023359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\ + "-0.139597, -0.097169, -0.062708, -0.022786, 0.289448",\ + "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\ + "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\ + "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024064, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\ + "-0.173551, -0.107464, -0.049558, -0.007530, 0.212650",\ + "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\ + "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\ + "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[16]_hldr*/ + +} /* end of pin tl_o[16] */ + +pin("tl_o[15]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.035370 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + function : "0" ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : tl_o[15]; +} /* end of pin tl_o[15] */ + +pin("tl_o[14]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.154883 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : tl_o[14]; + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[62]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011"); + values ( "0.487261, 0.669190, 0.852549, 1.146075, 1.714279",\ + "0.520839, 0.702769, 0.886128, 1.179654, 1.747858",\ + "0.591826, 0.773756, 0.957115, 1.250640, 1.818845",\ + "0.846910, 1.028840, 1.212200, 1.505725, 2.073928",\ + "1.772164, 1.954093, 2.137452, 2.430978, 2.999182",\ + "0.574671, 0.756577, 0.940009, 1.233380, 1.801632",\ + "0.608250, 0.790156, 0.973588, 1.266959, 1.835211",\ + "0.679237, 0.861143, 1.044574, 1.337945, 1.906198",\ + "0.934321, 1.116227, 1.299660, 1.593030, 2.161281",\ + "1.859574, 2.041480, 2.224912, 2.518283, 3.086535",\ + "0.655541, 0.836911, 1.020036, 1.313408, 1.881664",\ + "0.689120, 0.870490, 1.053615, 1.346987, 1.915242",\ + "0.760107, 0.941477, 1.124601, 1.417974, 1.986230",\ + "1.015191, 1.196561, 1.379687, 1.673059, 2.241313",\ + "1.940444, 2.121814, 2.304939, 2.598311, 3.166567",\ + "0.713217, 0.894460, 1.077579, 1.370653, 1.938311",\ + "0.746796, 0.928038, 1.111158, 1.404232, 1.971890",\ + "0.817783, 0.999025, 1.182144, 1.475219, 2.042877",\ + "1.072867, 1.254110, 1.437230, 1.730303, 2.297960",\ + "1.998120, 2.179363, 2.362482, 2.655556, 3.223215",\ + "1.015892, 1.199670, 1.381211, 1.673666, 2.240149",\ + "1.049471, 1.233248, 1.414790, 1.707245, 2.273727",\ + "1.120458, 1.304235, 1.485777, 1.778232, 2.344714",\ + "1.375542, 1.559320, 1.740862, 2.033317, 2.599797",\ + "2.300795, 2.484573, 2.666114, 2.958570, 3.525052"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011"); + values ( "0.023781, 0.023781, 0.023781, 0.023781, 0.023781",\ + "0.069352, 0.069352, 0.069352, 0.069352, 0.069353",\ + "0.200458, 0.200458, 0.200458, 0.200458, 0.200458",\ + "0.686693, 0.686693, 0.686693, 0.686694, 0.686697",\ + "2.458885, 2.458885, 2.458885, 2.458885, 2.458885",\ + "0.023781, 0.023781, 0.023781, 0.023781, 0.023781",\ + "0.069352, 0.069352, 0.069352, 0.069352, 0.069353",\ + "0.200458, 0.200458, 0.200458, 0.200458, 0.200458",\ + "0.686693, 0.686693, 0.686693, 0.686694, 0.686697",\ + "2.458885, 2.458885, 2.458885, 2.458885, 2.458885",\ + "0.023781, 0.023781, 0.023781, 0.023781, 0.023781",\ + "0.069352, 0.069352, 0.069352, 0.069352, 0.069353",\ + "0.200458, 0.200458, 0.200458, 0.200458, 0.200458",\ + "0.686693, 0.686693, 0.686693, 0.686694, 0.686697",\ + "2.458885, 2.458885, 2.458885, 2.458885, 2.458885",\ + "0.023781, 0.023781, 0.023781, 0.023781, 0.023781",\ + "0.069352, 0.069352, 0.069352, 0.069352, 0.069353",\ + "0.200458, 0.200458, 0.200458, 0.200458, 0.200458",\ + "0.686693, 0.686693, 0.686693, 0.686694, 0.686697",\ + "2.458885, 2.458885, 2.458885, 2.458885, 2.458885",\ + "0.023781, 0.023781, 0.023781, 0.023781, 0.023781",\ + "0.069352, 0.069352, 0.069352, 0.069352, 0.069353",\ + "0.200458, 0.200458, 0.200458, 0.200458, 0.200458",\ + "0.686693, 0.686693, 0.686693, 0.686694, 0.686697",\ + "2.458885, 2.458885, 2.458885, 2.458885, 2.458885"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011"); + values ( "0.570397, 0.827870, 1.084327, 1.522623, 2.399216",\ + "0.611284, 0.868757, 1.125214, 1.563510, 2.440103",\ + "0.671440, 0.928913, 1.185369, 1.623666, 2.500259",\ + "0.840387, 1.097859, 1.354316, 1.792613, 2.669205",\ + "1.423797, 1.681270, 1.937729, 2.376020, 3.252604",\ + "0.658623, 0.915349, 1.171797, 1.609338, 2.485150",\ + "0.699510, 0.956236, 1.212684, 1.650225, 2.526037",\ + "0.759666, 1.016392, 1.272839, 1.710381, 2.586193",\ + "0.928613, 1.185339, 1.441786, 1.879327, 2.755138",\ + "1.512023, 1.768749, 2.025198, 2.462735, 3.338538",\ + "0.747341, 1.004170, 1.259759, 1.696960, 2.572105",\ + "0.788228, 1.045057, 1.300646, 1.737847, 2.612992",\ + "0.848383, 1.105212, 1.360802, 1.798002, 2.673148",\ + "1.017330, 1.274159, 1.529749, 1.966949, 2.842093",\ + "1.600740, 1.857569, 2.113161, 2.550357, 3.425493",\ + "0.810342, 1.069571, 1.323894, 1.760873, 2.635614",\ + "0.851229, 1.110458, 1.364781, 1.801760, 2.676501",\ + "0.911385, 1.170614, 1.424936, 1.861916, 2.736657",\ + "1.080332, 1.339561, 1.593883, 2.030862, 2.905602",\ + "1.663742, 1.922971, 2.177295, 2.614270, 3.489002",\ + "1.142661, 1.431230, 1.675450, 2.110093, 2.981070",\ + "1.183547, 1.472117, 1.716337, 2.150980, 3.021957",\ + "1.243703, 1.532272, 1.776492, 2.211136, 3.082113",\ + "1.412650, 1.701219, 1.945439, 2.380082, 3.251059",\ + "1.996059, 2.284630, 2.528851, 2.963490, 3.834458"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011"); + values ( "0.042573, 0.042574, 0.042574, 0.042574, 0.042574",\ + "0.078573, 0.078573, 0.078573, 0.078574, 0.078575",\ + "0.154782, 0.154782, 0.154782, 0.154783, 0.154784",\ + "0.431097, 0.431097, 0.431098, 0.431098, 0.431098",\ + "1.494947, 1.494947, 1.494950, 1.494958, 1.494974",\ + "0.042573, 0.042574, 0.042574, 0.042574, 0.042574",\ + "0.078573, 0.078573, 0.078573, 0.078574, 0.078575",\ + "0.154782, 0.154782, 0.154782, 0.154783, 0.154784",\ + "0.431097, 0.431097, 0.431098, 0.431098, 0.431098",\ + "1.494947, 1.494947, 1.494950, 1.494958, 1.494974",\ + "0.042573, 0.042574, 0.042574, 0.042574, 0.042574",\ + "0.078573, 0.078573, 0.078573, 0.078574, 0.078575",\ + "0.154782, 0.154782, 0.154782, 0.154783, 0.154784",\ + "0.431097, 0.431097, 0.431098, 0.431098, 0.431098",\ + "1.494947, 1.494947, 1.494950, 1.494958, 1.494974",\ + "0.042573, 0.042574, 0.042574, 0.042574, 0.042574",\ + "0.078573, 0.078573, 0.078573, 0.078574, 0.078575",\ + "0.154782, 0.154782, 0.154782, 0.154783, 0.154784",\ + "0.431097, 0.431097, 0.431098, 0.431098, 0.431098",\ + "1.494947, 1.494947, 1.494950, 1.494958, 1.494974",\ + "0.042573, 0.042574, 0.042574, 0.042574, 0.042574",\ + "0.078573, 0.078573, 0.078573, 0.078574, 0.078575",\ + "0.154782, 0.154782, 0.154782, 0.154783, 0.154784",\ + "0.431097, 0.431097, 0.431098, 0.431098, 0.431098",\ + "1.494947, 1.494947, 1.494950, 1.494958, 1.494974"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[14]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[62]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011"); + values ( "0.487261, 0.668812, 0.852015, 1.145595, 1.713488",\ + "0.520839, 0.702391, 0.885594, 1.179174, 1.747067",\ + "0.591826, 0.773378, 0.956580, 1.250161, 1.818054",\ + "0.846910, 1.028462, 1.211666, 1.505246, 2.073137",\ + "1.772164, 1.953715, 2.136918, 2.430498, 2.998391",\ + "0.574671, 0.756130, 0.939295, 1.232900, 1.800842",\ + "0.608250, 0.789709, 0.972874, 1.266479, 1.834420",\ + "0.679237, 0.860696, 1.043861, 1.337466, 1.905408",\ + "0.934321, 1.115781, 1.298946, 1.592551, 2.160491",\ + "1.859574, 2.041033, 2.224198, 2.517803, 3.085745",\ + "0.655541, 0.836464, 1.019322, 1.312929, 1.880873",\ + "0.689120, 0.870043, 1.052901, 1.346508, 1.914452",\ + "0.760107, 0.941030, 1.123888, 1.417494, 1.985439",\ + "1.015191, 1.196114, 1.378973, 1.672579, 2.240522",\ + "1.940444, 2.121367, 2.304225, 2.597832, 3.165776",\ + "0.713217, 0.894301, 1.077028, 1.370367, 1.937906",\ + "0.746796, 0.927880, 1.110607, 1.403946, 1.971485",\ + "0.817783, 0.998867, 1.181593, 1.474933, 2.042472",\ + "1.072867, 1.253952, 1.436679, 1.730018, 2.297555",\ + "1.998120, 2.179204, 2.361931, 2.655270, 3.222809",\ + "1.015892, 1.199670, 1.380685, 1.673546, 2.240149",\ + "1.049471, 1.233248, 1.414264, 1.707125, 2.273727",\ + "1.120458, 1.304235, 1.485251, 1.778112, 2.344714",\ + "1.375542, 1.559320, 1.740336, 2.033197, 2.599797",\ + "2.300795, 2.484573, 2.665588, 2.958449, 3.525052"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011"); + values ( "0.023781, 0.023781, 0.023781, 0.023781, 0.023781",\ + "0.069352, 0.069352, 0.069352, 0.069352, 0.069352",\ + "0.200457, 0.200457, 0.200457, 0.200457, 0.200457",\ + "0.686690, 0.686690, 0.686690, 0.686692, 0.686695",\ + "2.458656, 2.458656, 2.458656, 2.458656, 2.458656",\ + "0.023781, 0.023781, 0.023781, 0.023781, 0.023781",\ + "0.069352, 0.069352, 0.069352, 0.069352, 0.069352",\ + "0.200457, 0.200457, 0.200457, 0.200457, 0.200457",\ + "0.686690, 0.686690, 0.686690, 0.686692, 0.686695",\ + "2.458656, 2.458656, 2.458656, 2.458656, 2.458656",\ + "0.023781, 0.023781, 0.023781, 0.023781, 0.023781",\ + "0.069352, 0.069352, 0.069352, 0.069352, 0.069352",\ + "0.200457, 0.200457, 0.200457, 0.200457, 0.200457",\ + "0.686690, 0.686690, 0.686690, 0.686692, 0.686695",\ + "2.458656, 2.458656, 2.458656, 2.458656, 2.458656",\ + "0.023781, 0.023781, 0.023781, 0.023781, 0.023781",\ + "0.069352, 0.069352, 0.069352, 0.069352, 0.069352",\ + "0.200457, 0.200457, 0.200457, 0.200457, 0.200457",\ + "0.686690, 0.686690, 0.686690, 0.686692, 0.686695",\ + "2.458656, 2.458656, 2.458656, 2.458656, 2.458656",\ + "0.023781, 0.023781, 0.023781, 0.023781, 0.023781",\ + "0.069352, 0.069352, 0.069352, 0.069352, 0.069352",\ + "0.200457, 0.200457, 0.200457, 0.200457, 0.200457",\ + "0.686690, 0.686690, 0.686690, 0.686692, 0.686695",\ + "2.458656, 2.458656, 2.458656, 2.458656, 2.458656"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011"); + values ( "0.570397, 0.827870, 1.084327, 1.522393, 2.397526",\ + "0.611284, 0.868757, 1.125214, 1.563280, 2.438413",\ + "0.671440, 0.928913, 1.185369, 1.623435, 2.498569",\ + "0.840387, 1.097859, 1.354316, 1.792382, 2.667514",\ + "1.423797, 1.681270, 1.937729, 2.375790, 3.250914",\ + "0.658623, 0.915349, 1.171797, 1.609107, 2.483460",\ + "0.699510, 0.956236, 1.212684, 1.649994, 2.524347",\ + "0.759666, 1.016392, 1.272839, 1.710150, 2.584503",\ + "0.928613, 1.185339, 1.441786, 1.879097, 2.753448",\ + "1.512023, 1.768749, 2.025198, 2.462505, 3.336848",\ + "0.747341, 1.004170, 1.259759, 1.696743, 2.570415",\ + "0.788228, 1.045057, 1.300646, 1.737630, 2.611302",\ + "0.848383, 1.105212, 1.360802, 1.797786, 2.671458",\ + "1.017330, 1.274159, 1.529749, 1.966733, 2.840403",\ + "1.600740, 1.857569, 2.113161, 2.550140, 3.423803",\ + "0.810342, 1.069571, 1.323894, 1.760796, 2.633924",\ + "0.851229, 1.110458, 1.364781, 1.801683, 2.674811",\ + "0.911385, 1.170614, 1.424936, 1.861839, 2.734967",\ + "1.080332, 1.339561, 1.593883, 2.030786, 2.903912",\ + "1.663742, 1.922971, 2.177295, 2.614193, 3.487312",\ + "1.142661, 1.431230, 1.675450, 2.110093, 2.979380",\ + "1.183547, 1.472117, 1.716337, 2.150980, 3.020267",\ + "1.243703, 1.532272, 1.776492, 2.211136, 3.080423",\ + "1.412650, 1.701219, 1.945439, 2.380082, 3.249368",\ + "1.996059, 2.284630, 2.528851, 2.963490, 3.832768"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011"); + values ( "0.042570, 0.042570, 0.042570, 0.042570, 0.042570",\ + "0.078571, 0.078571, 0.078572, 0.078573, 0.078575",\ + "0.154780, 0.154780, 0.154781, 0.154782, 0.154784",\ + "0.431094, 0.431094, 0.431094, 0.431094, 0.431094",\ + "1.494932, 1.494932, 1.494936, 1.494948, 1.494973",\ + "0.042570, 0.042570, 0.042570, 0.042570, 0.042570",\ + "0.078571, 0.078571, 0.078572, 0.078573, 0.078575",\ + "0.154780, 0.154780, 0.154781, 0.154782, 0.154784",\ + "0.431094, 0.431094, 0.431094, 0.431094, 0.431094",\ + "1.494932, 1.494932, 1.494936, 1.494948, 1.494973",\ + "0.042570, 0.042570, 0.042570, 0.042570, 0.042570",\ + "0.078571, 0.078571, 0.078572, 0.078573, 0.078575",\ + "0.154780, 0.154780, 0.154781, 0.154782, 0.154784",\ + "0.431094, 0.431094, 0.431094, 0.431094, 0.431094",\ + "1.494932, 1.494932, 1.494936, 1.494948, 1.494973",\ + "0.042570, 0.042570, 0.042570, 0.042570, 0.042570",\ + "0.078571, 0.078571, 0.078572, 0.078573, 0.078575",\ + "0.154780, 0.154780, 0.154781, 0.154782, 0.154784",\ + "0.431094, 0.431094, 0.431094, 0.431094, 0.431094",\ + "1.494932, 1.494932, 1.494936, 1.494948, 1.494973",\ + "0.042570, 0.042570, 0.042570, 0.042570, 0.042570",\ + "0.078571, 0.078571, 0.078572, 0.078573, 0.078575",\ + "0.154780, 0.154780, 0.154781, 0.154782, 0.154784",\ + "0.431094, 0.431094, 0.431094, 0.431094, 0.431094",\ + "1.494932, 1.494932, 1.494936, 1.494948, 1.494973"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[14]_redg_min*/ + +} /* end of pin tl_o[14] */ + +pin("tl_o[13]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.035370 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : tl_o[13]; + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[58]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011"); + values ( "0.284540, 0.564046, 0.863617, 1.380944, 2.415600",\ + "0.298686, 0.578104, 0.877668, 1.395235, 2.430368",\ + "0.322356, 0.601709, 0.901313, 1.419287, 2.455237",\ + "0.588425, 0.867068, 1.165530, 1.682108, 2.715266",\ + "1.177776, 1.456090, 1.753734, 2.268545, 3.298168",\ + "0.372946, 0.651675, 0.951331, 1.467657, 2.501533",\ + "0.387092, 0.665733, 0.965383, 1.481948, 2.516302",\ + "0.410761, 0.689337, 0.989029, 1.506001, 2.541171",\ + "0.676826, 0.954691, 1.253242, 1.768821, 2.801200",\ + "1.266174, 1.543712, 1.841440, 2.355258, 3.384101",\ + "0.462897, 0.740788, 1.039296, 1.555278, 2.588488",\ + "0.477041, 0.754844, 1.053348, 1.569568, 2.603257",\ + "0.500709, 0.778447, 1.076994, 1.593621, 2.628126",\ + "0.766761, 1.043790, 1.341207, 1.856442, 2.888155",\ + "1.356101, 1.632807, 1.929405, 2.442878, 3.471056",\ + "0.527359, 0.806612, 1.103444, 1.619190, 2.651997",\ + "0.541500, 0.820667, 1.117496, 1.633481, 2.666766",\ + "0.565168, 0.844269, 1.141142, 1.657534, 2.691635",\ + "0.831207, 1.109596, 1.405354, 1.920354, 2.951664",\ + "1.420539, 1.698606, 1.993552, 2.506791, 3.534565",\ + "0.868940, 1.173349, 1.455796, 1.968728, 2.997453",\ + "0.883067, 1.187384, 1.469851, 1.983020, 3.012222",\ + "0.906732, 1.210965, 1.493501, 2.007074, 3.037091",\ + "1.172689, 1.476110, 1.757699, 2.269889, 3.297120",\ + "1.761970, 2.065045, 2.345879, 2.856318, 3.880022"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011"); + values ( "0.185739, 0.187595, 0.200176, 0.234510, 0.303179",\ + "0.203933, 0.205579, 0.217466, 0.250509, 0.316595",\ + "0.237929, 0.239084, 0.249124, 0.278309, 0.336679",\ + "0.816189, 0.816358, 0.816864, 0.818096, 0.820559",\ + "2.192673, 2.192673, 2.192836, 2.193388, 2.194490",\ + "0.185741, 0.187611, 0.200283, 0.234510, 0.303179",\ + "0.203935, 0.205594, 0.217569, 0.250509, 0.316595",\ + "0.237932, 0.239093, 0.249216, 0.278309, 0.336679",\ + "0.816190, 0.816359, 0.816868, 0.818096, 0.820559",\ + "2.192673, 2.192673, 2.192838, 2.193388, 2.194490",\ + "0.185746, 0.187647, 0.200285, 0.234510, 0.303179",\ + "0.203942, 0.205625, 0.217571, 0.250509, 0.316595",\ + "0.237941, 0.239114, 0.249217, 0.278309, 0.336679",\ + "0.816195, 0.816361, 0.816868, 0.818096, 0.820559",\ + "2.192673, 2.192673, 2.192838, 2.193388, 2.194490",\ + "0.185751, 0.187699, 0.200291, 0.234510, 0.303179",\ + "0.203948, 0.205670, 0.217577, 0.250509, 0.316595",\ + "0.237949, 0.239145, 0.249223, 0.278309, 0.336679",\ + "0.816200, 0.816364, 0.816869, 0.818096, 0.820559",\ + "2.192673, 2.192673, 2.192838, 2.193388, 2.194490",\ + "0.185783, 0.188312, 0.200639, 0.234651, 0.303179",\ + "0.203989, 0.206205, 0.217912, 0.250645, 0.316595",\ + "0.238001, 0.239502, 0.249518, 0.278429, 0.336679",\ + "0.816229, 0.816400, 0.816881, 0.818101, 0.820559",\ + "2.192673, 2.192673, 2.192844, 2.193390, 2.194490"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011"); + values ( "0.374522, 0.561124, 0.780572, 1.136359, 1.826584",\ + "0.383805, 0.570576, 0.790645, 1.147661, 1.840366",\ + "0.399074, 0.586082, 0.807015, 1.165645, 1.861569",\ + "0.557633, 0.745097, 0.967701, 1.332699, 2.042731",\ + "0.898199, 1.085553, 1.307755, 1.673592, 2.385983",\ + "0.461924, 0.648520, 0.868125, 1.223665, 1.913938",\ + "0.471207, 0.657972, 0.878200, 1.234966, 1.927719",\ + "0.486476, 0.673478, 0.894572, 1.252950, 1.948923",\ + "0.645035, 0.832494, 1.055262, 1.420004, 2.130085",\ + "0.985600, 1.172950, 1.395316, 1.760897, 2.473337",\ + "0.542814, 0.728848, 0.948152, 1.303693, 1.993969",\ + "0.552097, 0.738300, 0.958227, 1.314994, 2.007751",\ + "0.567368, 0.753806, 0.974599, 1.332979, 2.028955",\ + "0.725929, 0.912822, 1.135289, 1.500032, 2.210116",\ + "1.066495, 1.253278, 1.475343, 1.840926, 2.553368",\ + "0.600620, 0.786398, 1.005694, 1.360937, 2.050617",\ + "0.609906, 0.795850, 1.015768, 1.372238, 2.064399",\ + "0.625179, 0.811356, 1.032140, 1.390222, 2.085602",\ + "0.783746, 0.970371, 1.192830, 1.557276, 2.266764",\ + "1.124310, 1.310827, 1.532884, 1.898169, 2.610016",\ + "0.904940, 1.091713, 1.309322, 1.663948, 2.352501",\ + "0.914244, 1.101169, 1.319397, 1.675249, 2.366283",\ + "0.929544, 1.116681, 1.335769, 1.693234, 2.387488",\ + "1.088161, 1.275707, 1.496459, 1.860287, 2.568655",\ + "1.428713, 1.616160, 1.836513, 2.201180, 2.911908"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011"); + values ( "0.065408, 0.068159, 0.078360, 0.098953, 0.140695",\ + "0.068352, 0.070728, 0.079541, 0.099563, 0.141041",\ + "0.087647, 0.089359, 0.095706, 0.112588, 0.148436",\ + "0.381015, 0.381154, 0.381669, 0.388289, 0.403942",\ + "1.027611, 1.027611, 1.027611, 1.028167, 1.029517",\ + "0.065408, 0.068161, 0.078386, 0.098953, 0.140695",\ + "0.068352, 0.070731, 0.079564, 0.099563, 0.141041",\ + "0.087647, 0.089361, 0.095723, 0.112588, 0.148436",\ + "0.381015, 0.381154, 0.381670, 0.388289, 0.403942",\ + "1.027611, 1.027611, 1.027611, 1.028167, 1.029517",\ + "0.065424, 0.068161, 0.078386, 0.098953, 0.140695",\ + "0.068366, 0.070731, 0.079564, 0.099563, 0.141041",\ + "0.087657, 0.089361, 0.095723, 0.112588, 0.148436",\ + "0.381016, 0.381154, 0.381670, 0.388289, 0.403942",\ + "1.027611, 1.027611, 1.027611, 1.028167, 1.029517",\ + "0.065456, 0.068161, 0.078386, 0.098953, 0.140695",\ + "0.068394, 0.070731, 0.079564, 0.099563, 0.141041",\ + "0.087678, 0.089361, 0.095723, 0.112588, 0.148436",\ + "0.381018, 0.381154, 0.381670, 0.388289, 0.403942",\ + "1.027611, 1.027611, 1.027611, 1.028167, 1.029517",\ + "0.065761, 0.068226, 0.078386, 0.098953, 0.140710",\ + "0.068657, 0.070787, 0.079564, 0.099563, 0.141057",\ + "0.087867, 0.089401, 0.095723, 0.112588, 0.148450",\ + "0.381033, 0.381158, 0.381670, 0.388289, 0.403948",\ + "1.027611, 1.027611, 1.027611, 1.028167, 1.029517"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[13]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[58]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011"); + values ( "0.284540, 0.564046, 0.863617, 1.380550, 2.412738",\ + "0.298686, 0.578104, 0.877668, 1.394840, 2.427504",\ + "0.322356, 0.601709, 0.901313, 1.418892, 2.452366",\ + "0.588425, 0.867068, 1.165530, 1.681715, 2.712415",\ + "1.177776, 1.456090, 1.753734, 2.268156, 3.295343",\ + "0.372946, 0.651675, 0.951331, 1.467263, 2.498672",\ + "0.387092, 0.665733, 0.965383, 1.481553, 2.513437",\ + "0.410761, 0.689337, 0.989029, 1.505605, 2.538300",\ + "0.676826, 0.954691, 1.253242, 1.768429, 2.798349",\ + "1.266174, 1.543712, 1.841440, 2.354868, 3.381277",\ + "0.462897, 0.740788, 1.039296, 1.554907, 2.585627",\ + "0.477041, 0.754844, 1.053348, 1.569197, 2.600392",\ + "0.500709, 0.778447, 1.076994, 1.593250, 2.625255",\ + "0.766761, 1.043790, 1.341207, 1.856073, 2.885304",\ + "1.356101, 1.632807, 1.929405, 2.442513, 3.468232",\ + "0.527359, 0.806612, 1.103444, 1.619057, 2.649136",\ + "0.541500, 0.820667, 1.117496, 1.633347, 2.663901",\ + "0.565168, 0.844269, 1.141142, 1.657400, 2.688764",\ + "0.831207, 1.109596, 1.405354, 1.920222, 2.948813",\ + "1.420539, 1.698606, 1.993552, 2.506659, 3.531741",\ + "0.868940, 1.173349, 1.455796, 1.968728, 2.994592",\ + "0.883067, 1.187384, 1.469851, 1.983020, 3.009357",\ + "0.906732, 1.210965, 1.493501, 2.007074, 3.034220",\ + "1.172689, 1.476110, 1.757699, 2.269889, 3.294269",\ + "1.761970, 2.065045, 2.345879, 2.856318, 3.877197"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011"); + values ( "0.185739, 0.187595, 0.200176, 0.234441, 0.302676",\ + "0.203933, 0.205579, 0.217466, 0.250442, 0.316110",\ + "0.237929, 0.239084, 0.249124, 0.278250, 0.336252",\ + "0.816189, 0.816358, 0.816864, 0.818093, 0.820541",\ + "2.191667, 2.191667, 2.191920, 2.192775, 2.194479",\ + "0.185741, 0.187611, 0.200283, 0.234441, 0.302676",\ + "0.203935, 0.205594, 0.217569, 0.250442, 0.316110",\ + "0.237932, 0.239093, 0.249216, 0.278250, 0.336252",\ + "0.816190, 0.816359, 0.816868, 0.818093, 0.820541",\ + "2.191667, 2.191667, 2.191923, 2.192775, 2.194479",\ + "0.185746, 0.187647, 0.200285, 0.234445, 0.302676",\ + "0.203942, 0.205625, 0.217571, 0.250446, 0.316110",\ + "0.237941, 0.239114, 0.249217, 0.278254, 0.336252",\ + "0.816195, 0.816361, 0.816868, 0.818094, 0.820541",\ + "2.191667, 2.191667, 2.191923, 2.192775, 2.194479",\ + "0.185751, 0.187699, 0.200291, 0.234487, 0.302676",\ + "0.203948, 0.205670, 0.217577, 0.250486, 0.316110",\ + "0.237949, 0.239145, 0.249223, 0.278289, 0.336252",\ + "0.816200, 0.816364, 0.816869, 0.818095, 0.820541",\ + "2.191667, 2.191667, 2.191923, 2.192777, 2.194479",\ + "0.185783, 0.188312, 0.200639, 0.234651, 0.302676",\ + "0.203989, 0.206205, 0.217912, 0.250645, 0.316110",\ + "0.238001, 0.239502, 0.249518, 0.278429, 0.336252",\ + "0.816229, 0.816400, 0.816881, 0.818101, 0.820541",\ + "2.191667, 2.191667, 2.191932, 2.192781, 2.194479"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011"); + values ( "0.374522, 0.560710, 0.779750, 1.135509, 1.825184",\ + "0.383805, 0.570161, 0.789818, 1.146803, 1.838953",\ + "0.399074, 0.585665, 0.806181, 1.164778, 1.860141",\ + "0.557633, 0.744678, 0.966854, 1.331789, 2.041233",\ + "0.898199, 1.085135, 1.306912, 1.672675, 2.384473",\ + "0.461924, 0.648027, 0.867031, 1.222814, 1.912538",\ + "0.471207, 0.657479, 0.877099, 1.234108, 1.926307",\ + "0.486476, 0.672983, 0.893462, 1.252083, 1.947495",\ + "0.645035, 0.831996, 1.054135, 1.419094, 2.128587",\ + "0.985600, 1.172452, 1.394193, 1.759980, 2.471827",\ + "0.542814, 0.728355, 0.947058, 1.302843, 1.992569",\ + "0.552097, 0.737807, 0.957126, 1.314137, 2.006338",\ + "0.567368, 0.753311, 0.973489, 1.332111, 2.027526",\ + "0.725929, 0.912324, 1.134162, 1.499123, 2.208618",\ + "1.066495, 1.252781, 1.474220, 1.840009, 2.551858",\ + "0.600620, 0.786214, 1.004849, 1.360430, 2.049899",\ + "0.609906, 0.795666, 1.014919, 1.371727, 2.063674",\ + "0.625179, 0.811172, 1.031284, 1.389706, 2.084870",\ + "0.783746, 0.970186, 1.191961, 1.556734, 2.265996",\ + "1.124310, 1.310642, 1.532018, 1.897623, 2.609242",\ + "0.904940, 1.091713, 1.308519, 1.663736, 2.352501",\ + "0.914244, 1.101169, 1.318589, 1.675035, 2.366283",\ + "0.929544, 1.116681, 1.334955, 1.693017, 2.387488",\ + "1.088161, 1.275707, 1.495632, 1.860060, 2.568655",\ + "1.428713, 1.616160, 1.835689, 2.200952, 2.911908"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011"); + values ( "0.065408, 0.068145, 0.078282, 0.097416, 0.135633",\ + "0.068319, 0.070715, 0.079474, 0.098027, 0.135980",\ + "0.087624, 0.089350, 0.095658, 0.111069, 0.143404",\ + "0.381014, 0.381153, 0.381665, 0.388242, 0.403865",\ + "1.027072, 1.027072, 1.027072, 1.027705, 1.029249",\ + "0.065408, 0.068145, 0.078282, 0.097416, 0.135633",\ + "0.068319, 0.070715, 0.079474, 0.098027, 0.135980",\ + "0.087624, 0.089350, 0.095658, 0.111069, 0.143404",\ + "0.381014, 0.381153, 0.381665, 0.388242, 0.403865",\ + "1.027072, 1.027072, 1.027072, 1.027705, 1.029249",\ + "0.065424, 0.068145, 0.078282, 0.097416, 0.135633",\ + "0.068333, 0.070715, 0.079474, 0.098027, 0.135980",\ + "0.087634, 0.089350, 0.095658, 0.111069, 0.143404",\ + "0.381014, 0.381153, 0.381665, 0.388242, 0.403865",\ + "1.027072, 1.027072, 1.027072, 1.027705, 1.029249",\ + "0.065456, 0.068155, 0.078306, 0.097463, 0.135725",\ + "0.068362, 0.070724, 0.079494, 0.098073, 0.136072",\ + "0.087655, 0.089356, 0.095672, 0.111109, 0.143482",\ + "0.381016, 0.381154, 0.381666, 0.388261, 0.403903",\ + "1.027072, 1.027072, 1.027072, 1.027707, 1.029253",\ + "0.065761, 0.068226, 0.078310, 0.097503, 0.135836",\ + "0.068628, 0.070787, 0.079498, 0.098113, 0.136183",\ + "0.087847, 0.089401, 0.095675, 0.111142, 0.143576",\ + "0.381032, 0.381158, 0.381666, 0.388277, 0.403948",\ + "1.027072, 1.027072, 1.027072, 1.027708, 1.029258"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[13]_redg_min*/ + +} /* end of pin tl_o[13] */ + +pin("tl_o[12]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.020161 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : tl_o[12]; + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[57]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011"); + values ( "0.475879, 0.665118, 0.888399, 1.250294, 1.951686",\ + "0.526872, 0.716033, 0.939041, 1.300629, 2.001501",\ + "0.604552, 0.793643, 1.016400, 1.377502, 2.077400",\ + "0.813681, 1.002691, 1.225160, 1.585609, 2.284153",\ + "1.367036, 1.556010, 1.778356, 2.138460, 2.836268",\ + "0.563289, 0.752511, 0.975963, 1.337600, 2.039039",\ + "0.614282, 0.803427, 1.026603, 1.387934, 2.088855",\ + "0.691962, 0.881036, 1.103961, 1.464807, 2.164753",\ + "0.901091, 1.090085, 1.312721, 1.672914, 2.371507",\ + "1.454446, 1.643404, 1.865916, 2.225765, 2.923622",\ + "0.644207, 0.832845, 1.055990, 1.417628, 2.119071",\ + "0.695200, 0.883761, 1.106630, 1.467962, 2.168886",\ + "0.772879, 0.961370, 1.183988, 1.544836, 2.244785",\ + "0.982008, 1.170418, 1.392748, 1.752943, 2.451539",\ + "1.535362, 1.723738, 1.945943, 2.305794, 3.003654",\ + "0.701978, 0.890394, 1.113533, 1.474873, 2.175719",\ + "0.752969, 0.941309, 1.164173, 1.525207, 2.225534",\ + "0.830648, 1.018919, 1.241531, 1.602080, 2.301433",\ + "1.039776, 1.227967, 1.450291, 1.810187, 2.508186",\ + "1.593130, 1.781286, 2.003486, 2.363039, 3.060301",\ + "1.005526, 1.195782, 1.417165, 1.777886, 2.477606",\ + "1.056509, 1.246695, 1.467805, 1.828220, 2.527421",\ + "1.134180, 1.324303, 1.545163, 1.905094, 2.603319",\ + "1.343298, 1.533349, 1.753923, 2.113201, 2.810072",\ + "1.896648, 2.086668, 2.307118, 2.666052, 3.362187"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011"); + values ( "0.150008, 0.150413, 0.151867, 0.156224, 0.165642",\ + "0.237388, 0.237631, 0.238503, 0.240761, 0.245540",\ + "0.400537, 0.400554, 0.400616, 0.401193, 0.402548",\ + "0.873945, 0.873960, 0.874011, 0.874292, 0.874933",\ + "2.149644, 2.149644, 2.149644, 2.149724, 2.149920",\ + "0.150008, 0.150413, 0.151871, 0.156224, 0.165642",\ + "0.237388, 0.237631, 0.238506, 0.240761, 0.245540",\ + "0.400537, 0.400554, 0.400616, 0.401193, 0.402548",\ + "0.873945, 0.873960, 0.874011, 0.874292, 0.874933",\ + "2.149644, 2.149644, 2.149644, 2.149724, 2.149920",\ + "0.150011, 0.150413, 0.151871, 0.156224, 0.165642",\ + "0.237390, 0.237631, 0.238506, 0.240761, 0.245540",\ + "0.400537, 0.400554, 0.400616, 0.401193, 0.402548",\ + "0.873945, 0.873960, 0.874011, 0.874292, 0.874933",\ + "2.149644, 2.149644, 2.149644, 2.149724, 2.149920",\ + "0.150016, 0.150413, 0.151871, 0.156224, 0.165642",\ + "0.237393, 0.237631, 0.238506, 0.240761, 0.245540",\ + "0.400537, 0.400554, 0.400616, 0.401193, 0.402548",\ + "0.873946, 0.873960, 0.874011, 0.874292, 0.874933",\ + "2.149644, 2.149644, 2.149644, 2.149724, 2.149920",\ + "0.150062, 0.150423, 0.151871, 0.156224, 0.165645",\ + "0.237420, 0.237637, 0.238506, 0.240761, 0.245542",\ + "0.400539, 0.400554, 0.400616, 0.401193, 0.402548",\ + "0.873947, 0.873960, 0.874011, 0.874292, 0.874933",\ + "2.149644, 2.149644, 2.149644, 2.149724, 2.149920"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011"); + values ( "0.321064, 0.601616, 0.902007, 1.418205, 2.450602",\ + "0.356109, 0.636678, 0.937135, 1.453516, 2.486277",\ + "0.406657, 0.687216, 0.987647, 1.504000, 2.536706",\ + "0.536144, 0.816696, 1.117064, 1.633222, 2.665537",\ + "0.873984, 1.154534, 1.454850, 1.970856, 3.002866",\ + "0.409514, 0.689233, 0.989723, 1.504920, 2.536536",\ + "0.444559, 0.724295, 1.024851, 1.540230, 2.572211",\ + "0.495106, 0.774833, 1.075363, 1.590714, 2.622640",\ + "0.624593, 0.904313, 1.204779, 1.719936, 2.751471",\ + "0.962434, 1.242151, 1.542565, 2.057570, 3.088800",\ + "0.498914, 0.778364, 1.077690, 1.592542, 2.623491",\ + "0.533960, 0.813427, 1.112818, 1.627852, 2.659166",\ + "0.584508, 0.863965, 1.163329, 1.678336, 2.709595",\ + "0.713994, 0.993445, 1.292746, 1.807558, 2.838426",\ + "1.051835, 1.331282, 1.630532, 2.145192, 3.175755",\ + "0.562563, 0.844218, 1.141837, 1.656455, 2.687000",\ + "0.597610, 0.879281, 1.176965, 1.691765, 2.722675",\ + "0.648158, 0.929819, 1.227477, 1.742249, 2.773104",\ + "0.777645, 1.059298, 1.356893, 1.871471, 2.901935",\ + "1.115485, 1.397135, 1.694679, 2.209105, 3.239264",\ + "0.898997, 1.211173, 1.494183, 2.005997, 3.032455",\ + "0.934048, 1.246239, 1.529313, 2.041308, 3.068131",\ + "0.984598, 1.296772, 1.579825, 2.091792, 3.118560",\ + "1.114083, 1.426250, 1.709239, 2.221013, 3.247391",\ + "1.451924, 1.764086, 2.047024, 2.558647, 3.584720"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011"); + values ( "0.072029, 0.072117, 0.072944, 0.075686, 0.081171",\ + "0.105035, 0.105045, 0.105444, 0.106815, 0.109557",\ + "0.191067, 0.191185, 0.191447, 0.191928, 0.192889",\ + "0.434550, 0.434818, 0.434976, 0.434976, 0.434976",\ + "1.073490, 1.073490, 1.073593, 1.073946, 1.074653",\ + "0.072030, 0.072117, 0.072953, 0.075686, 0.081171",\ + "0.105035, 0.105045, 0.105449, 0.106815, 0.109557",\ + "0.191068, 0.191185, 0.191449, 0.191928, 0.192889",\ + "0.434555, 0.434819, 0.434976, 0.434976, 0.434976",\ + "1.073490, 1.073490, 1.073594, 1.073946, 1.074653",\ + "0.072035, 0.072117, 0.072953, 0.075686, 0.081171",\ + "0.105035, 0.105045, 0.105449, 0.106815, 0.109557",\ + "0.191071, 0.191187, 0.191449, 0.191928, 0.192889",\ + "0.434567, 0.434821, 0.434976, 0.434976, 0.434976",\ + "1.073490, 1.073490, 1.073594, 1.073946, 1.074653",\ + "0.072040, 0.072118, 0.072953, 0.075686, 0.081171",\ + "0.105036, 0.105045, 0.105449, 0.106815, 0.109557",\ + "0.191073, 0.191190, 0.191449, 0.191928, 0.192889",\ + "0.434578, 0.434825, 0.434976, 0.434976, 0.434976",\ + "1.073490, 1.073490, 1.073594, 1.073946, 1.074653",\ + "0.072068, 0.072127, 0.072981, 0.075698, 0.081171",\ + "0.105040, 0.105046, 0.105463, 0.106821, 0.109557",\ + "0.191088, 0.191220, 0.191454, 0.191930, 0.192889",\ + "0.434649, 0.434864, 0.434976, 0.434976, 0.434976",\ + "1.073490, 1.073490, 1.073597, 1.073947, 1.074653"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[12]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[57]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011"); + values ( "0.475879, 0.664703, 0.887555, 1.249416, 1.950237",\ + "0.526872, 0.715619, 0.938198, 1.299751, 2.000055",\ + "0.604552, 0.793229, 1.015559, 1.376628, 2.075958",\ + "0.813681, 1.002278, 1.224322, 1.584739, 2.282718",\ + "1.367036, 1.555598, 1.777518, 2.137592, 2.834837",\ + "0.563289, 0.752022, 0.974836, 1.336721, 2.037590",\ + "0.614282, 0.802938, 1.025479, 1.387056, 2.087408",\ + "0.691962, 0.880548, 1.102840, 1.463933, 2.163312",\ + "0.901091, 1.089596, 1.311603, 1.672044, 2.370072",\ + "1.454446, 1.642916, 1.864799, 2.224897, 2.922191",\ + "0.644207, 0.832355, 1.054863, 1.416749, 2.117622",\ + "0.695200, 0.883271, 1.105506, 1.467085, 2.167440",\ + "0.772879, 0.960881, 1.182867, 1.543961, 2.243343",\ + "0.982008, 1.169930, 1.391630, 1.752072, 2.450104",\ + "1.535362, 1.723250, 1.944826, 2.304926, 3.002222",\ + "0.701978, 0.890220, 1.112662, 1.474349, 2.174976",\ + "0.752969, 0.941136, 1.163305, 1.524684, 2.224792",\ + "0.830648, 1.018745, 1.240665, 1.601559, 2.300694",\ + "1.039776, 1.227793, 1.449427, 1.809669, 2.507451",\ + "1.593130, 1.781113, 2.002623, 2.362521, 3.059567",\ + "1.005526, 1.195782, 1.416335, 1.777666, 2.477606",\ + "1.056509, 1.246695, 1.466977, 1.828001, 2.527421",\ + "1.134180, 1.324303, 1.544337, 1.904875, 2.603319",\ + "1.343298, 1.533349, 1.753099, 2.112983, 2.810072",\ + "1.896648, 2.086668, 2.306295, 2.665835, 3.362187"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011"); + values ( "0.150008, 0.150411, 0.151856, 0.156196, 0.165595",\ + "0.237385, 0.237630, 0.238497, 0.240747, 0.245517",\ + "0.400536, 0.400554, 0.400616, 0.401188, 0.402541",\ + "0.873945, 0.873960, 0.874011, 0.874290, 0.874930",\ + "2.149610, 2.149610, 2.149610, 2.149694, 2.149902",\ + "0.150008, 0.150411, 0.151856, 0.156196, 0.165595",\ + "0.237385, 0.237630, 0.238497, 0.240747, 0.245517",\ + "0.400536, 0.400554, 0.400616, 0.401188, 0.402541",\ + "0.873945, 0.873960, 0.874011, 0.874290, 0.874930",\ + "2.149610, 2.149610, 2.149610, 2.149694, 2.149902",\ + "0.150011, 0.150411, 0.151856, 0.156196, 0.165595",\ + "0.237387, 0.237630, 0.238497, 0.240747, 0.245517",\ + "0.400536, 0.400554, 0.400616, 0.401188, 0.402541",\ + "0.873945, 0.873960, 0.874011, 0.874290, 0.874930",\ + "2.149610, 2.149610, 2.149610, 2.149694, 2.149902",\ + "0.150016, 0.150412, 0.151859, 0.156208, 0.165618",\ + "0.237390, 0.237631, 0.238499, 0.240753, 0.245528",\ + "0.400537, 0.400554, 0.400616, 0.401190, 0.402544",\ + "0.873945, 0.873960, 0.874011, 0.874290, 0.874931",\ + "2.149610, 2.149610, 2.149610, 2.149695, 2.149903",\ + "0.150062, 0.150423, 0.151860, 0.156217, 0.165645",\ + "0.237418, 0.237637, 0.238499, 0.240757, 0.245542",\ + "0.400539, 0.400554, 0.400616, 0.401192, 0.402548",\ + "0.873947, 0.873960, 0.874011, 0.874291, 0.874933",\ + "2.149610, 2.149610, 2.149610, 2.149695, 2.149903"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011"); + values ( "0.321064, 0.601616, 0.902007, 1.417819, 2.447771",\ + "0.356109, 0.636678, 0.937135, 1.453129, 2.483444",\ + "0.406657, 0.687216, 0.987647, 1.503613, 2.533873",\ + "0.536144, 0.816696, 1.117064, 1.632835, 2.662707",\ + "0.873984, 1.154534, 1.454850, 1.970470, 3.000039",\ + "0.409514, 0.689233, 0.989723, 1.504534, 2.533705",\ + "0.444559, 0.724295, 1.024851, 1.539844, 2.569378",\ + "0.495106, 0.774833, 1.075363, 1.590328, 2.619807",\ + "0.624593, 0.904313, 1.204779, 1.719550, 2.748641",\ + "0.962434, 1.242151, 1.542565, 2.057184, 3.085972",\ + "0.498914, 0.778364, 1.077690, 1.592179, 2.620660",\ + "0.533960, 0.813427, 1.112818, 1.627489, 2.656333",\ + "0.584508, 0.863965, 1.163329, 1.677973, 2.706762",\ + "0.713994, 0.993445, 1.292746, 1.807195, 2.835596",\ + "1.051835, 1.331282, 1.630532, 2.144830, 3.172927",\ + "0.562563, 0.844218, 1.141837, 1.656326, 2.684169",\ + "0.597610, 0.879281, 1.176965, 1.691636, 2.719842",\ + "0.648158, 0.929819, 1.227477, 1.742120, 2.770271",\ + "0.777645, 1.059298, 1.356893, 1.871342, 2.899105",\ + "1.115485, 1.397135, 1.694679, 2.208976, 3.236436",\ + "0.898997, 1.211173, 1.494183, 2.005997, 3.029625",\ + "0.934048, 1.246239, 1.529313, 2.041308, 3.065298",\ + "0.984598, 1.296772, 1.579825, 2.091792, 3.115727",\ + "1.114083, 1.426250, 1.709239, 2.221013, 3.244561",\ + "1.451924, 1.764086, 2.047024, 2.558647, 3.581892"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011"); + values ( "0.072029, 0.072117, 0.072944, 0.075681, 0.081131",\ + "0.105035, 0.105045, 0.105444, 0.106813, 0.109537",\ + "0.191067, 0.191185, 0.191447, 0.191927, 0.192882",\ + "0.434550, 0.434688, 0.434688, 0.434688, 0.434688",\ + "1.072978, 1.072978, 1.073125, 1.073633, 1.074646",\ + "0.072030, 0.072117, 0.072953, 0.075681, 0.081131",\ + "0.105035, 0.105045, 0.105449, 0.106813, 0.109537",\ + "0.191068, 0.191185, 0.191449, 0.191927, 0.192882",\ + "0.434554, 0.434688, 0.434688, 0.434688, 0.434688",\ + "1.072978, 1.072978, 1.073126, 1.073633, 1.074646",\ + "0.072035, 0.072117, 0.072953, 0.075681, 0.081131",\ + "0.105035, 0.105045, 0.105449, 0.106813, 0.109537",\ + "0.191071, 0.191187, 0.191449, 0.191927, 0.192882",\ + "0.434564, 0.434688, 0.434688, 0.434688, 0.434688",\ + "1.072978, 1.072978, 1.073126, 1.073633, 1.074646",\ + "0.072040, 0.072118, 0.072953, 0.075685, 0.081131",\ + "0.105036, 0.105045, 0.105449, 0.106814, 0.109537",\ + "0.191073, 0.191190, 0.191449, 0.191928, 0.192882",\ + "0.434574, 0.434688, 0.434688, 0.434688, 0.434688",\ + "1.072978, 1.072978, 1.073127, 1.073634, 1.074646",\ + "0.072068, 0.072127, 0.072981, 0.075698, 0.081131",\ + "0.105040, 0.105046, 0.105463, 0.106821, 0.109537",\ + "0.191088, 0.191220, 0.191454, 0.191930, 0.192882",\ + "0.434635, 0.434688, 0.434688, 0.434688, 0.434688",\ + "1.072978, 1.072978, 1.073132, 1.073636, 1.074646"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[12]_redg_min*/ + +} /* end of pin tl_o[12] */ + +pin("tl_o[11]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.154883 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : tl_o[11]; + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[1]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011"); + values ( "0.480044, 0.757907, 1.049391, 1.544816, 2.535666",\ + "0.520846, 0.798709, 1.090193, 1.585618, 2.576470",\ + "0.596179, 0.874043, 1.165526, 1.660950, 2.651799",\ + "0.851223, 1.129087, 1.420574, 1.916010, 2.906884",\ + "1.776399, 2.054266, 2.345743, 2.841143, 3.831943",\ + "0.568493, 0.845495, 1.137043, 1.631531, 2.621600",\ + "0.609294, 0.886297, 1.177845, 1.672334, 2.662404",\ + "0.684628, 0.961631, 1.253178, 1.747665, 2.737732",\ + "0.939672, 1.216675, 1.508226, 2.002726, 2.992818",\ + "1.864848, 2.141854, 2.433396, 2.927858, 3.917876",\ + "0.657525, 0.934585, 1.225009, 1.719154, 2.708555",\ + "0.698327, 0.975387, 1.265811, 1.759956, 2.749359",\ + "0.773660, 1.050721, 1.341145, 1.835288, 2.824687",\ + "1.028704, 1.305765, 1.596192, 2.090348, 3.079773",\ + "1.953881, 2.230944, 2.521362, 3.015481, 4.004831",\ + "0.720671, 1.000379, 1.289153, 1.783067, 2.772064",\ + "0.761473, 1.041181, 1.329955, 1.823870, 2.812868",\ + "0.836807, 1.116515, 1.405289, 1.899202, 2.888196",\ + "1.091850, 1.371559, 1.660336, 2.154262, 3.143282",\ + "2.017027, 2.296738, 2.585506, 3.079395, 4.068340",\ + "1.053915, 1.366570, 1.641292, 2.132528, 3.117520",\ + "1.094717, 1.407372, 1.682094, 2.173331, 3.158324",\ + "1.170050, 1.482705, 1.757427, 2.248662, 3.233653",\ + "1.425094, 1.737749, 2.012475, 2.503723, 3.488738",\ + "2.350272, 2.662929, 2.937644, 3.428855, 4.413796"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011"); + values ( "0.033097, 0.033098, 0.033098, 0.033098, 0.033098",\ + "0.082184, 0.082184, 0.082184, 0.082184, 0.082184",\ + "0.206840, 0.206841, 0.206841, 0.206841, 0.206842",\ + "0.691575, 0.691576, 0.691578, 0.691578, 0.691578",\ + "2.469653, 2.469654, 2.469654, 2.469654, 2.469654",\ + "0.033097, 0.033098, 0.033098, 0.033098, 0.033098",\ + "0.082184, 0.082184, 0.082184, 0.082184, 0.082184",\ + "0.206840, 0.206841, 0.206841, 0.206841, 0.206842",\ + "0.691575, 0.691576, 0.691578, 0.691578, 0.691578",\ + "2.469653, 2.469654, 2.469654, 2.469654, 2.469654",\ + "0.033097, 0.033098, 0.033098, 0.033098, 0.033098",\ + "0.082184, 0.082184, 0.082184, 0.082184, 0.082184",\ + "0.206840, 0.206841, 0.206841, 0.206841, 0.206842",\ + "0.691575, 0.691576, 0.691578, 0.691578, 0.691578",\ + "2.469653, 2.469654, 2.469654, 2.469654, 2.469654",\ + "0.033097, 0.033098, 0.033098, 0.033098, 0.033098",\ + "0.082184, 0.082184, 0.082184, 0.082184, 0.082184",\ + "0.206840, 0.206841, 0.206841, 0.206841, 0.206842",\ + "0.691575, 0.691576, 0.691578, 0.691578, 0.691578",\ + "2.469654, 2.469654, 2.469654, 2.469654, 2.469654",\ + "0.033097, 0.033098, 0.033098, 0.033098, 0.033098",\ + "0.082184, 0.082184, 0.082184, 0.082184, 0.082184",\ + "0.206840, 0.206841, 0.206841, 0.206841, 0.206842",\ + "0.691575, 0.691577, 0.691578, 0.691578, 0.691578",\ + "2.469654, 2.469654, 2.469654, 2.469654, 2.469654"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011"); + values ( "0.577593, 0.759063, 0.958904, 1.285183, 1.919119",\ + "0.619104, 0.800573, 1.000415, 1.326696, 1.960636",\ + "0.678962, 0.860432, 1.060273, 1.386554, 2.020497",\ + "0.847206, 1.028676, 1.228518, 1.554798, 2.188738",\ + "1.428635, 1.610105, 1.809947, 2.136236, 2.770198",\ + "0.665008, 0.846447, 1.046407, 1.372488, 2.006473",\ + "0.706519, 0.887958, 1.087918, 1.414001, 2.047990",\ + "0.766377, 0.947816, 1.147776, 1.473860, 2.107850",\ + "0.934621, 1.116060, 1.316020, 1.642103, 2.276092",\ + "1.516050, 1.697490, 1.897449, 2.223541, 2.857552",\ + "0.745878, 0.926784, 1.126434, 1.452517, 2.086504",\ + "0.787388, 0.968295, 1.167944, 1.494029, 2.128021",\ + "0.847246, 1.028153, 1.227803, 1.553888, 2.187881",\ + "1.015491, 1.196397, 1.396047, 1.722131, 2.356123",\ + "1.596920, 1.777826, 1.977476, 2.303569, 2.937583",\ + "0.803511, 0.984332, 1.183978, 1.509762, 2.143152",\ + "0.845022, 1.025843, 1.225488, 1.551274, 2.184669",\ + "0.904880, 1.085701, 1.285347, 1.611133, 2.244529",\ + "1.073124, 1.253945, 1.453591, 1.779376, 2.412771",\ + "1.654553, 1.835374, 2.035020, 2.360815, 2.994231",\ + "1.105600, 1.289533, 1.487611, 1.812776, 2.445014",\ + "1.147110, 1.331044, 1.529122, 1.854289, 2.486530",\ + "1.206968, 1.390902, 1.588980, 1.914148, 2.546391",\ + "1.375213, 1.559146, 1.757225, 2.082391, 2.714632",\ + "1.956642, 2.140575, 2.338654, 2.663829, 3.296093"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011"); + values ( "0.045173, 0.045173, 0.045173, 0.045173, 0.045173",\ + "0.078561, 0.078561, 0.078561, 0.078562, 0.078566",\ + "0.153692, 0.153692, 0.153692, 0.153692, 0.153692",\ + "0.429868, 0.429868, 0.429868, 0.429868, 0.429868",\ + "1.490308, 1.490308, 1.490308, 1.490340, 1.490420",\ + "0.045173, 0.045173, 0.045173, 0.045173, 0.045173",\ + "0.078561, 0.078561, 0.078561, 0.078562, 0.078566",\ + "0.153692, 0.153692, 0.153692, 0.153692, 0.153692",\ + "0.429868, 0.429868, 0.429868, 0.429868, 0.429868",\ + "1.490308, 1.490308, 1.490308, 1.490340, 1.490420",\ + "0.045173, 0.045173, 0.045173, 0.045173, 0.045173",\ + "0.078561, 0.078561, 0.078561, 0.078562, 0.078566",\ + "0.153692, 0.153692, 0.153692, 0.153692, 0.153692",\ + "0.429868, 0.429868, 0.429868, 0.429868, 0.429868",\ + "1.490308, 1.490308, 1.490308, 1.490340, 1.490420",\ + "0.045173, 0.045173, 0.045173, 0.045173, 0.045173",\ + "0.078561, 0.078561, 0.078561, 0.078562, 0.078566",\ + "0.153692, 0.153692, 0.153692, 0.153692, 0.153692",\ + "0.429868, 0.429868, 0.429868, 0.429868, 0.429868",\ + "1.490308, 1.490308, 1.490308, 1.490340, 1.490420",\ + "0.045173, 0.045173, 0.045173, 0.045173, 0.045173",\ + "0.078561, 0.078561, 0.078561, 0.078562, 0.078566",\ + "0.153692, 0.153692, 0.153692, 0.153692, 0.153692",\ + "0.429868, 0.429868, 0.429868, 0.429868, 0.429868",\ + "1.490308, 1.490308, 1.490308, 1.490340, 1.490420"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[11]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[1]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011"); + values ( "0.480044, 0.757907, 1.049391, 1.544474, 2.533147",\ + "0.520846, 0.798709, 1.090193, 1.585276, 2.573951",\ + "0.596179, 0.874043, 1.165526, 1.660608, 2.649279",\ + "0.851223, 1.129087, 1.420574, 1.915668, 2.904364",\ + "1.776399, 2.054266, 2.345743, 2.840801, 3.829424",\ + "0.568493, 0.845495, 1.137043, 1.631189, 2.619081",\ + "0.609294, 0.886297, 1.177845, 1.671992, 2.659884",\ + "0.684628, 0.961631, 1.253178, 1.747323, 2.735213",\ + "0.939672, 1.216675, 1.508226, 2.002384, 2.990298",\ + "1.864848, 2.141854, 2.433396, 2.927516, 3.915357",\ + "0.657525, 0.934585, 1.225009, 1.718833, 2.706036",\ + "0.698327, 0.975387, 1.265811, 1.759635, 2.746840",\ + "0.773660, 1.050721, 1.341145, 1.834967, 2.822168",\ + "1.028704, 1.305765, 1.596192, 2.090027, 3.077253",\ + "1.953881, 2.230944, 2.521362, 3.015160, 4.002313",\ + "0.720671, 1.000379, 1.289153, 1.782954, 2.769545",\ + "0.761473, 1.041181, 1.329955, 1.823757, 2.810349",\ + "0.836807, 1.116515, 1.405289, 1.899088, 2.885677",\ + "1.091850, 1.371559, 1.660336, 2.154149, 3.140762",\ + "2.017027, 2.296738, 2.585506, 3.079281, 4.065822",\ + "1.053915, 1.366570, 1.641292, 2.132528, 3.115001",\ + "1.094717, 1.407372, 1.682094, 2.173331, 3.155805",\ + "1.170050, 1.482705, 1.757427, 2.248662, 3.231133",\ + "1.425094, 1.737749, 2.012475, 2.503723, 3.486218",\ + "2.350272, 2.662929, 2.937644, 3.428855, 4.411278"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011"); + values ( "0.033097, 0.033097, 0.033097, 0.033097, 0.033097",\ + "0.082175, 0.082175, 0.082175, 0.082175, 0.082175",\ + "0.206840, 0.206841, 0.206841, 0.206841, 0.206842",\ + "0.691460, 0.691460, 0.691460, 0.691460, 0.691460",\ + "2.469630, 2.469654, 2.469654, 2.469654, 2.469654",\ + "0.033097, 0.033097, 0.033097, 0.033097, 0.033097",\ + "0.082175, 0.082175, 0.082175, 0.082175, 0.082175",\ + "0.206840, 0.206841, 0.206841, 0.206841, 0.206842",\ + "0.691460, 0.691460, 0.691460, 0.691460, 0.691460",\ + "2.469631, 2.469654, 2.469654, 2.469654, 2.469654",\ + "0.033097, 0.033097, 0.033097, 0.033097, 0.033097",\ + "0.082175, 0.082175, 0.082175, 0.082175, 0.082175",\ + "0.206840, 0.206841, 0.206841, 0.206841, 0.206842",\ + "0.691460, 0.691460, 0.691460, 0.691460, 0.691460",\ + "2.469633, 2.469654, 2.469654, 2.469654, 2.469654",\ + "0.033097, 0.033097, 0.033097, 0.033097, 0.033097",\ + "0.082175, 0.082175, 0.082175, 0.082175, 0.082175",\ + "0.206840, 0.206841, 0.206841, 0.206841, 0.206842",\ + "0.691460, 0.691460, 0.691460, 0.691460, 0.691460",\ + "2.469634, 2.469654, 2.469654, 2.469654, 2.469654",\ + "0.033097, 0.033097, 0.033097, 0.033097, 0.033097",\ + "0.082175, 0.082175, 0.082175, 0.082175, 0.082175",\ + "0.206840, 0.206841, 0.206841, 0.206841, 0.206842",\ + "0.691460, 0.691460, 0.691460, 0.691460, 0.691460",\ + "2.469645, 2.469654, 2.469654, 2.469654, 2.469654"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011"); + values ( "0.577593, 0.758693, 0.958244, 1.284509, 1.918007",\ + "0.619104, 0.800204, 0.999755, 1.326021, 1.959524",\ + "0.678962, 0.860062, 1.059613, 1.385880, 2.019384",\ + "0.847206, 1.028306, 1.227857, 1.554123, 2.187625",\ + "1.428635, 1.609735, 1.809286, 2.135561, 2.769086",\ + "0.665008, 0.846012, 1.045525, 1.371814, 2.005360",\ + "0.706519, 0.887523, 1.087036, 1.413326, 2.046877",\ + "0.766377, 0.947381, 1.146894, 1.473185, 2.106737",\ + "0.934621, 1.115625, 1.315138, 1.641428, 2.274979",\ + "1.516050, 1.697054, 1.896567, 2.222867, 2.856439",\ + "0.745878, 0.926348, 1.125552, 1.451842, 2.085392",\ + "0.787388, 0.967859, 1.167063, 1.493355, 2.126909",\ + "0.847246, 1.027717, 1.226921, 1.553214, 2.186769",\ + "1.015491, 1.195961, 1.395165, 1.721457, 2.355011",\ + "1.596920, 1.777390, 1.976594, 2.302895, 2.936471",\ + "0.803511, 0.984182, 1.183296, 1.509360, 2.142581",\ + "0.845022, 1.025692, 1.224806, 1.550872, 2.184098",\ + "0.904880, 1.085551, 1.284665, 1.610731, 2.243959",\ + "1.073124, 1.253795, 1.452909, 1.778975, 2.412200",\ + "1.654553, 1.835224, 2.034338, 2.360413, 2.993660",\ + "1.105600, 1.289533, 1.486960, 1.812607, 2.445014",\ + "1.147110, 1.331044, 1.528471, 1.854120, 2.486530",\ + "1.206968, 1.390902, 1.588329, 1.913979, 2.546391",\ + "1.375213, 1.559146, 1.756574, 2.082222, 2.714632",\ + "1.956642, 2.140575, 2.338003, 2.663660, 3.296093"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011"); + values ( "0.045164, 0.045164, 0.045164, 0.045164, 0.045164",\ + "0.078561, 0.078561, 0.078561, 0.078562, 0.078566",\ + "0.153612, 0.153612, 0.153612, 0.153612, 0.153612",\ + "0.429864, 0.429864, 0.429864, 0.429864, 0.429864",\ + "1.490306, 1.490306, 1.490306, 1.490338, 1.490419",\ + "0.045164, 0.045164, 0.045164, 0.045164, 0.045164",\ + "0.078561, 0.078561, 0.078561, 0.078562, 0.078566",\ + "0.153612, 0.153612, 0.153612, 0.153612, 0.153612",\ + "0.429864, 0.429864, 0.429864, 0.429864, 0.429864",\ + "1.490306, 1.490306, 1.490306, 1.490338, 1.490419",\ + "0.045164, 0.045164, 0.045164, 0.045164, 0.045164",\ + "0.078561, 0.078561, 0.078561, 0.078562, 0.078566",\ + "0.153612, 0.153612, 0.153612, 0.153612, 0.153612",\ + "0.429864, 0.429864, 0.429864, 0.429864, 0.429864",\ + "1.490306, 1.490306, 1.490306, 1.490338, 1.490419",\ + "0.045164, 0.045164, 0.045164, 0.045164, 0.045164",\ + "0.078561, 0.078561, 0.078561, 0.078562, 0.078566",\ + "0.153612, 0.153612, 0.153612, 0.153612, 0.153612",\ + "0.429864, 0.429864, 0.429864, 0.429864, 0.429864",\ + "1.490306, 1.490306, 1.490306, 1.490339, 1.490419",\ + "0.045164, 0.045164, 0.045164, 0.045164, 0.045164",\ + "0.078561, 0.078561, 0.078561, 0.078562, 0.078566",\ + "0.153612, 0.153612, 0.153612, 0.153612, 0.153612",\ + "0.429864, 0.429864, 0.429864, 0.429864, 0.429864",\ + "1.490306, 1.490306, 1.490306, 1.490339, 1.490420"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[11]_redg_min*/ + +} /* end of pin tl_o[11] */ + +pin("tl_o[10]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.020161 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : tl_o[10]; + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[1]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011"); + values ( "0.364012, 0.625791, 0.912362, 1.416686, 2.425334",\ + "0.413794, 0.675738, 0.964329, 1.475067, 2.496546",\ + "0.489422, 0.751529, 1.041528, 1.556366, 2.586045",\ + "0.695293, 0.957830, 1.249004, 1.765727, 2.799173",\ + "1.246075, 1.508922, 1.800327, 2.315899, 3.347043",\ + "0.451427, 0.713333, 1.000043, 1.503402, 2.511267",\ + "0.501209, 0.763281, 1.052029, 1.561783, 2.582479",\ + "0.576836, 0.839074, 1.129242, 1.643082, 2.671978",\ + "0.782708, 1.045378, 1.336724, 1.852442, 2.885106",\ + "1.333490, 1.596474, 1.888044, 2.402615, 3.432977",\ + "0.533466, 0.802315, 1.088010, 1.591024, 2.598222",\ + "0.583252, 0.852266, 1.139997, 1.649405, 2.669434",\ + "0.658880, 0.928062, 1.217209, 1.730705, 2.758933",\ + "0.864753, 1.134376, 1.424692, 1.940065, 2.972061",\ + "1.415530, 1.685480, 1.976011, 2.490237, 3.519932",\ + "0.596367, 0.867953, 1.152155, 1.654938, 2.661731",\ + "0.646156, 0.917908, 1.204143, 1.713319, 2.732943",\ + "0.721785, 0.993709, 1.281356, 1.794618, 2.822442",\ + "0.927659, 1.200036, 1.488839, 2.003978, 3.035570",\ + "1.478432, 1.751152, 2.040158, 2.554151, 3.583441",\ + "0.928059, 1.232317, 1.504384, 2.004435, 3.007188",\ + "0.977868, 1.282318, 1.556437, 2.062843, 3.078399",\ + "1.053501, 1.358177, 1.633692, 2.144160, 3.167898",\ + "1.259380, 1.564660, 1.841193, 2.353528, 3.381027",\ + "1.810129, 2.115913, 2.392501, 2.903695, 3.928897"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011"); + values ( "0.177438, 0.178519, 0.189473, 0.223901, 0.292757",\ + "0.251359, 0.253407, 0.263275, 0.290387, 0.344610",\ + "0.412697, 0.412697, 0.415313, 0.424472, 0.442790",\ + "0.885478, 0.885674, 0.886375, 0.887778, 0.890585",\ + "2.162748, 2.162748, 2.162938, 2.163605, 2.164938",\ + "0.177438, 0.178526, 0.189583, 0.223901, 0.292757",\ + "0.251359, 0.253420, 0.263361, 0.290387, 0.344610",\ + "0.412697, 0.412697, 0.415342, 0.424472, 0.442790",\ + "0.885478, 0.885676, 0.886379, 0.887778, 0.890585",\ + "2.162748, 2.162748, 2.162940, 2.163605, 2.164938",\ + "0.177475, 0.178542, 0.189585, 0.223901, 0.292757",\ + "0.251427, 0.253451, 0.263362, 0.290387, 0.344610",\ + "0.412697, 0.412697, 0.415343, 0.424472, 0.442790",\ + "0.885478, 0.885680, 0.886380, 0.887778, 0.890585",\ + "2.162748, 2.162748, 2.162940, 2.163605, 2.164938",\ + "0.177499, 0.178566, 0.189590, 0.223901, 0.292757",\ + "0.251473, 0.253495, 0.263367, 0.290387, 0.344610",\ + "0.412697, 0.412697, 0.415344, 0.424472, 0.442790",\ + "0.885478, 0.885687, 0.886380, 0.887778, 0.890585",\ + "2.162748, 2.162748, 2.162940, 2.163605, 2.164938",\ + "0.177651, 0.178840, 0.189940, 0.224044, 0.292757",\ + "0.251761, 0.254016, 0.263642, 0.290499, 0.344610",\ + "0.412697, 0.412697, 0.415437, 0.424510, 0.442790",\ + "0.885478, 0.885760, 0.886394, 0.887784, 0.890585",\ + "2.162748, 2.162748, 2.162947, 2.163608, 2.164938"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011"); + values ( "0.312852, 0.568984, 0.862555, 1.382336, 2.421899",\ + "0.348118, 0.610654, 0.902338, 1.419180, 2.452865",\ + "0.406005, 0.669261, 0.960734, 1.473580, 2.499271",\ + "0.536962, 0.800144, 1.091137, 1.602535, 2.625331",\ + "0.874185, 1.136967, 1.427801, 1.940429, 2.965686",\ + "0.400266, 0.656542, 0.950284, 1.469051, 2.507832",\ + "0.435533, 0.698205, 0.990058, 1.505895, 2.538798",\ + "0.493420, 0.756819, 1.048442, 1.560295, 2.585205",\ + "0.624377, 0.887700, 1.178840, 1.689250, 2.711264",\ + "0.961600, 1.224520, 1.515508, 2.027145, 3.051620",\ + "0.481136, 0.745561, 1.038252, 1.556674, 2.594787",\ + "0.517546, 0.787210, 1.078026, 1.593518, 2.625753",\ + "0.575445, 0.845837, 1.136409, 1.647918, 2.672160",\ + "0.706398, 0.976717, 1.266807, 1.776872, 2.798219",\ + "1.043615, 1.313530, 1.603475, 2.114767, 3.138575",\ + "0.538770, 0.811253, 1.102400, 1.620588, 2.658296",\ + "0.580430, 0.852880, 1.142173, 1.657432, 2.689262",\ + "0.638337, 0.911526, 1.200556, 1.711832, 2.735669",\ + "0.769288, 1.042406, 1.330954, 1.840786, 2.861728",\ + "1.106500, 1.379207, 1.667622, 2.178681, 3.202084",\ + "0.869562, 1.176250, 1.454786, 1.970150, 3.003752",\ + "0.912016, 1.217620, 1.494529, 2.006981, 3.034719",\ + "0.969972, 1.276495, 1.552871, 2.061365, 3.081125",\ + "1.100910, 1.407358, 1.683254, 2.190313, 3.207185",\ + "1.438092, 1.744035, 2.019935, 2.528213, 3.547540"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011"); + values ( "0.081554, 0.088992, 0.106415, 0.139136, 0.204579",\ + "0.124645, 0.129773, 0.146146, 0.179503, 0.246217",\ + "0.203924, 0.205651, 0.213739, 0.234366, 0.275621",\ + "0.443609, 0.443974, 0.447191, 0.457130, 0.477008",\ + "1.100873, 1.101320, 1.101850, 1.102085, 1.102555",\ + "0.081554, 0.089042, 0.106519, 0.139136, 0.204579",\ + "0.124645, 0.129815, 0.146252, 0.179503, 0.246217",\ + "0.203924, 0.205665, 0.213805, 0.234366, 0.275621",\ + "0.443609, 0.443976, 0.447223, 0.457130, 0.477008",\ + "1.100873, 1.101323, 1.101851, 1.102085, 1.102555",\ + "0.081568, 0.089158, 0.106521, 0.139136, 0.204579",\ + "0.124713, 0.129914, 0.146254, 0.179503, 0.246217",\ + "0.203955, 0.205697, 0.213806, 0.234366, 0.275621",\ + "0.443622, 0.443982, 0.447223, 0.457130, 0.477008",\ + "1.100888, 1.101329, 1.101851, 1.102085, 1.102555",\ + "0.081595, 0.089328, 0.106526, 0.139136, 0.204579",\ + "0.124759, 0.130058, 0.146259, 0.179503, 0.246217",\ + "0.203975, 0.205743, 0.213809, 0.234366, 0.275621",\ + "0.443630, 0.443990, 0.447225, 0.457130, 0.477008",\ + "1.100898, 1.101339, 1.101851, 1.102085, 1.102555",\ + "0.082871, 0.091307, 0.106858, 0.139272, 0.204579",\ + "0.125047, 0.131735, 0.146598, 0.179642, 0.246217",\ + "0.204103, 0.206281, 0.214019, 0.234452, 0.275621",\ + "0.443681, 0.444082, 0.447326, 0.457171, 0.477008",\ + "1.100961, 1.101453, 1.101854, 1.102086, 1.102555"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[10]_redg_2703*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[57]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011"); + values ( "0.350851, 0.591855, 0.864128, 1.320281, 2.232588",\ + "0.400592, 0.641701, 0.915140, 1.374804, 2.294134",\ + "0.476229, 0.717426, 0.992120, 1.455680, 2.382801",\ + "0.682141, 0.923562, 1.199150, 1.664642, 2.595626",\ + "1.233045, 1.474598, 1.750161, 2.214853, 3.144235",\ + "0.438261, 0.679403, 0.951654, 1.406996, 2.318522",\ + "0.488002, 0.729251, 1.002677, 1.461519, 2.380068",\ + "0.563639, 0.804976, 1.079670, 1.542395, 2.468735",\ + "0.769551, 1.011115, 1.286705, 1.751357, 2.681560",\ + "1.320455, 1.562152, 1.837715, 2.301567, 3.230169",\ + "0.519097, 0.768378, 1.039617, 1.494618, 2.405477",\ + "0.568838, 0.818228, 1.090640, 1.549141, 2.467023",\ + "0.644474, 0.893955, 1.167633, 1.630017, 2.555690",\ + "0.850399, 1.100099, 1.374669, 1.838978, 2.768515",\ + "1.401325, 1.651139, 1.925678, 2.389189, 3.317124",\ + "0.576709, 0.834005, 1.103754, 1.558531, 2.468986",\ + "0.626450, 0.883858, 1.154778, 1.613054, 2.530532",\ + "0.702087, 0.959588, 1.231772, 1.693930, 2.619199",\ + "0.908034, 1.165738, 1.438808, 1.902892, 2.832024",\ + "1.459002, 1.716783, 1.989817, 2.453102, 3.380633",\ + "0.898537, 1.198301, 1.455491, 1.907824, 2.814442",\ + "0.948280, 1.248191, 1.506551, 1.962362, 2.875988",\ + "1.023916, 1.323954, 1.583584, 2.043254, 2.964655",\ + "1.229826, 1.530187, 1.790640, 2.252224, 3.177480",\ + "1.780725, 2.081283, 2.341641, 2.802431, 3.726089"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011"); + values ( "0.177532, 0.178920, 0.189751, 0.222197, 0.287089",\ + "0.251535, 0.254167, 0.264114, 0.288993, 0.338750",\ + "0.412948, 0.412948, 0.415205, 0.423013, 0.438629",\ + "0.885646, 0.885671, 0.886007, 0.887039, 0.889103",\ + "2.163153, 2.163153, 2.163261, 2.163636, 2.164385",\ + "0.177532, 0.178929, 0.189854, 0.222197, 0.287089",\ + "0.251535, 0.254184, 0.264193, 0.288993, 0.338750",\ + "0.412948, 0.412948, 0.415229, 0.423013, 0.438629",\ + "0.885646, 0.885672, 0.886011, 0.887039, 0.889103",\ + "2.163153, 2.163153, 2.163263, 2.163636, 2.164385",\ + "0.177534, 0.178950, 0.189855, 0.222197, 0.287089",\ + "0.251540, 0.254224, 0.264194, 0.288993, 0.338750",\ + "0.412948, 0.412948, 0.415230, 0.423013, 0.438629",\ + "0.885646, 0.885672, 0.886011, 0.887039, 0.889103",\ + "2.163153, 2.163153, 2.163263, 2.163636, 2.164385",\ + "0.177539, 0.178981, 0.189861, 0.222197, 0.287089",\ + "0.251549, 0.254282, 0.264198, 0.288993, 0.338750",\ + "0.412948, 0.412948, 0.415231, 0.423013, 0.438629",\ + "0.885646, 0.885673, 0.886011, 0.887039, 0.889103",\ + "2.163153, 2.163153, 2.163263, 2.163636, 2.164385",\ + "0.177778, 0.179340, 0.190190, 0.222331, 0.287089",\ + "0.252003, 0.254964, 0.264451, 0.289096, 0.338750",\ + "0.412948, 0.412948, 0.415310, 0.423045, 0.438629",\ + "0.885646, 0.885682, 0.886021, 0.887043, 0.889103",\ + "2.163153, 2.163153, 2.163266, 2.163637, 2.164385"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011"); + values ( "0.307193, 0.533242, 0.809521, 1.279856, 2.220526",\ + "0.336644, 0.576689, 0.852349, 1.318694, 2.251385",\ + "0.393241, 0.634932, 0.911048, 1.376848, 2.308447",\ + "0.524233, 0.765871, 1.043018, 1.512641, 2.451889",\ + "0.861499, 1.102901, 1.379688, 1.849255, 2.788391",\ + "0.394603, 0.620790, 0.897092, 1.366570, 2.306459",\ + "0.424054, 0.664240, 0.939907, 1.405409, 2.337319",\ + "0.480651, 0.722487, 0.998605, 1.463562, 2.394381",\ + "0.611643, 0.853426, 1.130586, 1.599356, 2.537823",\ + "0.948909, 1.190453, 1.467256, 1.935970, 2.874325",\ + "0.475519, 0.709763, 0.985056, 1.454192, 2.393414",\ + "0.504970, 0.753222, 1.027871, 1.493031, 2.424274",\ + "0.561503, 0.811478, 1.086568, 1.551184, 2.481336",\ + "0.692478, 0.942415, 1.218550, 1.686978, 2.624778",\ + "1.029784, 1.279438, 1.555220, 2.023592, 2.961280",\ + "0.533285, 0.775388, 1.049196, 1.518106, 2.456923",\ + "0.562736, 0.818858, 1.092010, 1.556944, 2.487783",\ + "0.619148, 0.877127, 1.150707, 1.615098, 2.544845",\ + "0.750090, 1.008062, 1.282690, 1.750891, 2.688287",\ + "1.087471, 1.345078, 1.619360, 2.087505, 3.024789",\ + "0.839984, 1.139662, 1.401077, 1.867458, 2.802380",\ + "0.883084, 1.183263, 1.443850, 1.906280, 2.833239",\ + "0.940909, 1.241684, 1.502542, 1.964431, 2.890301",\ + "1.071899, 1.372601, 1.634564, 2.100240, 3.033743",\ + "1.409163, 1.709532, 1.971233, 2.436854, 3.370245"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011"); + values ( "0.079414, 0.084257, 0.099312, 0.127519, 0.183935",\ + "0.124385, 0.127318, 0.139681, 0.167608, 0.223461",\ + "0.203732, 0.204755, 0.210826, 0.226691, 0.258421",\ + "0.443641, 0.444109, 0.446299, 0.452176, 0.463930",\ + "1.100911, 1.101486, 1.102125, 1.102253, 1.102511",\ + "0.079414, 0.084301, 0.099401, 0.127519, 0.183935",\ + "0.124385, 0.127346, 0.139769, 0.167608, 0.223461",\ + "0.203732, 0.204765, 0.210876, 0.226691, 0.258421",\ + "0.443641, 0.444112, 0.446317, 0.452176, 0.463930",\ + "1.100911, 1.101489, 1.102125, 1.102253, 1.102511",\ + "0.079415, 0.084402, 0.099402, 0.127519, 0.183935",\ + "0.124385, 0.127408, 0.139771, 0.167608, 0.223461",\ + "0.203732, 0.204786, 0.210877, 0.226691, 0.258421",\ + "0.443642, 0.444120, 0.446318, 0.452176, 0.463930",\ + "1.100913, 1.101498, 1.102125, 1.102253, 1.102511",\ + "0.079417, 0.084547, 0.099407, 0.127519, 0.183935",\ + "0.124385, 0.127499, 0.139776, 0.167608, 0.223461",\ + "0.203733, 0.204818, 0.210879, 0.226691, 0.258421",\ + "0.443643, 0.444130, 0.446319, 0.452176, 0.463930",\ + "1.100914, 1.101511, 1.102125, 1.102253, 1.102511",\ + "0.079511, 0.086252, 0.099693, 0.127636, 0.183935",\ + "0.124397, 0.128559, 0.140059, 0.167723, 0.223461",\ + "0.203741, 0.205184, 0.211040, 0.226757, 0.258421",\ + "0.443724, 0.444251, 0.446378, 0.452200, 0.463930",\ + "1.101013, 1.101659, 1.102126, 1.102254, 1.102511"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[10]_redg_2585*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[58]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011"); + values ( "0.331228, 0.527324, 0.786001, 1.224167, 2.100501",\ + "0.382369, 0.578501, 0.836813, 1.274472, 2.149791",\ + "0.460186, 0.652490, 0.910342, 1.347469, 2.221725",\ + "0.669327, 0.853217, 1.110120, 1.545833, 2.417260",\ + "1.222502, 1.402990, 1.654377, 2.088484, 2.956696",\ + "0.418630, 0.614835, 0.873467, 1.310880, 2.186435",\ + "0.469770, 0.666010, 0.924278, 1.361185, 2.235725",\ + "0.547588, 0.739998, 0.997805, 1.434183, 2.307659",\ + "0.756729, 0.940720, 1.197578, 1.632546, 2.503194",\ + "1.309904, 1.490380, 1.741831, 2.175197, 3.042630",\ + "0.499484, 0.703690, 0.961427, 1.398501, 2.273390",\ + "0.550625, 0.754862, 1.012238, 1.448806, 2.322680",\ + "0.628442, 0.828845, 1.085765, 1.521803, 2.394614",\ + "0.837583, 1.029560, 1.285538, 1.720167, 2.590149",\ + "1.390758, 1.574844, 1.829791, 2.262817, 3.129585",\ + "0.557217, 0.769141, 1.025562, 1.462414, 2.336899",\ + "0.608358, 0.820308, 1.076372, 1.512718, 2.386189",\ + "0.686176, 0.894284, 1.149899, 1.585716, 2.458123",\ + "0.895316, 1.094988, 1.349672, 1.784079, 2.653658",\ + "1.448492, 1.640260, 1.893925, 2.326730, 3.193094",\ + "0.860852, 1.131485, 1.377112, 1.811626, 2.682355",\ + "0.911997, 1.182598, 1.427917, 1.861928, 2.731645",\ + "0.989815, 1.256499, 1.501439, 1.934923, 2.803579",\ + "1.198957, 1.457069, 1.701197, 2.133281, 2.999114",\ + "1.752135, 2.002200, 2.245434, 2.675925, 3.538550"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011"); + values ( "0.247574, 0.253107, 0.265836, 0.292486, 0.345785",\ + "0.313887, 0.316030, 0.323178, 0.341027, 0.376725",\ + "0.435753, 0.438083, 0.443130, 0.454659, 0.477717",\ + "0.887719, 0.887719, 0.887745, 0.887834, 0.888012",\ + "2.165595, 2.165595, 2.165595, 2.165595, 2.165595",\ + "0.247574, 0.253139, 0.265920, 0.292486, 0.345785",\ + "0.313887, 0.316042, 0.323234, 0.341027, 0.376725",\ + "0.435753, 0.438094, 0.443166, 0.454659, 0.477717",\ + "0.887719, 0.887719, 0.887746, 0.887834, 0.888012",\ + "2.165595, 2.165595, 2.165595, 2.165595, 2.165595",\ + "0.247586, 0.253211, 0.265921, 0.292486, 0.345785",\ + "0.313891, 0.316070, 0.323235, 0.341027, 0.376725",\ + "0.435759, 0.438118, 0.443167, 0.454659, 0.477717",\ + "0.887719, 0.887719, 0.887746, 0.887834, 0.888012",\ + "2.165595, 2.165595, 2.165595, 2.165595, 2.165595",\ + "0.247608, 0.253315, 0.265926, 0.292486, 0.345785",\ + "0.313900, 0.316110, 0.323238, 0.341027, 0.376725",\ + "0.435772, 0.438153, 0.443169, 0.454659, 0.477717",\ + "0.887719, 0.887719, 0.887746, 0.887834, 0.888012",\ + "2.165595, 2.165595, 2.165595, 2.165595, 2.165595",\ + "0.247822, 0.254533, 0.266196, 0.292595, 0.345785",\ + "0.313983, 0.316581, 0.323419, 0.341101, 0.376725",\ + "0.435894, 0.438565, 0.443286, 0.454706, 0.477717",\ + "0.887719, 0.887719, 0.887747, 0.887835, 0.888012",\ + "2.165595, 2.165595, 2.165595, 2.165595, 2.165595"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011"); + values ( "0.262843, 0.528242, 0.786656, 1.223429, 2.096977",\ + "0.297860, 0.563309, 0.821748, 1.258583, 2.132253",\ + "0.348398, 0.613835, 0.872220, 1.308997, 2.182551",\ + "0.477894, 0.743312, 1.001644, 1.438265, 2.311508",\ + "0.815730, 1.081145, 1.339443, 1.775996, 2.649102",\ + "0.351215, 0.615754, 0.874118, 1.310142, 2.182910",\ + "0.386233, 0.650820, 0.909210, 1.345296, 2.218187",\ + "0.436771, 0.701346, 0.959682, 1.395710, 2.268485",\ + "0.566267, 0.830823, 1.089105, 1.524978, 2.397442",\ + "0.904103, 1.168656, 1.426904, 1.862709, 2.735036",\ + "0.441060, 0.704611, 0.962078, 1.397763, 2.269865",\ + "0.476082, 0.739678, 0.997171, 1.432917, 2.305142",\ + "0.526621, 0.790203, 1.047642, 1.483330, 2.355440",\ + "0.656116, 0.919680, 1.177066, 1.612599, 2.484397",\ + "0.993953, 1.257513, 1.514864, 1.950330, 2.821991",\ + "0.505420, 0.770065, 1.026212, 1.461676, 2.333374",\ + "0.540445, 0.805132, 1.061305, 1.496829, 2.368651",\ + "0.590985, 0.855656, 1.111776, 1.547243, 2.418949",\ + "0.720478, 0.985133, 1.241200, 1.676511, 2.547906",\ + "1.058316, 1.322965, 1.578998, 2.014242, 2.885500",\ + "0.846347, 1.132446, 1.377748, 1.810882, 2.678830",\ + "0.881392, 1.167515, 1.412841, 1.846036, 2.714107",\ + "0.931940, 1.218030, 1.463312, 1.896449, 2.764405",\ + "1.061427, 1.347505, 1.592734, 2.025717, 2.893362",\ + "1.399268, 1.685334, 1.930532, 2.363448, 3.230956"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011"); + values ( "0.080673, 0.084979, 0.095299, 0.118135, 0.163806",\ + "0.121691, 0.122534, 0.126916, 0.139600, 0.164968",\ + "0.211121, 0.211686, 0.213778, 0.219384, 0.230596",\ + "0.447776, 0.448001, 0.448970, 0.451208, 0.455684",\ + "1.099948, 1.099948, 1.099948, 1.099948, 1.099948",\ + "0.080714, 0.085004, 0.095371, 0.118135, 0.163806",\ + "0.121700, 0.122539, 0.126956, 0.139600, 0.164968",\ + "0.211127, 0.211689, 0.213796, 0.219384, 0.230596",\ + "0.447776, 0.448003, 0.448977, 0.451208, 0.455684",\ + "1.099948, 1.099948, 1.099948, 1.099948, 1.099948",\ + "0.080840, 0.085056, 0.095372, 0.118135, 0.163806",\ + "0.121728, 0.122548, 0.126957, 0.139600, 0.164968",\ + "0.211145, 0.211695, 0.213796, 0.219384, 0.230596",\ + "0.447776, 0.448008, 0.448977, 0.451208, 0.455684",\ + "1.099948, 1.099948, 1.099948, 1.099948, 1.099948",\ + "0.080962, 0.085133, 0.095376, 0.118135, 0.163806",\ + "0.121755, 0.122562, 0.126959, 0.139600, 0.164968",\ + "0.211163, 0.211704, 0.213797, 0.219384, 0.230596",\ + "0.447776, 0.448014, 0.448977, 0.451208, 0.455684",\ + "1.099948, 1.099948, 1.099948, 1.099948, 1.099948",\ + "0.081743, 0.086029, 0.095607, 0.118229, 0.163806",\ + "0.121930, 0.122722, 0.127087, 0.139652, 0.164968",\ + "0.211276, 0.211814, 0.213854, 0.219407, 0.230596",\ + "0.447776, 0.448092, 0.449000, 0.451217, 0.455684",\ + "1.099948, 1.099948, 1.099948, 1.099948, 1.099948"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[10]_redg_2468*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[62]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011"); + values ( "0.515413, 0.691814, 0.891527, 1.333812, 2.218381",\ + "0.561951, 0.738352, 0.942909, 1.385434, 2.270486",\ + "0.647617, 0.824017, 1.044838, 1.487336, 2.372332",\ + "0.870983, 1.047384, 1.281978, 1.724502, 2.609548",\ + "1.434991, 1.611392, 1.857594, 2.300149, 3.185259",\ + "0.602824, 0.779196, 0.979010, 1.420527, 2.304315",\ + "0.649362, 0.825734, 1.030392, 1.472149, 2.356420",\ + "0.735027, 0.911399, 1.132321, 1.574051, 2.458265",\ + "0.958394, 1.134766, 1.369462, 1.811216, 2.695482",\ + "1.522402, 1.698774, 1.945078, 2.386864, 3.271193",\ + "0.683657, 0.859530, 1.066972, 1.508148, 2.391270",\ + "0.730195, 0.906068, 1.118354, 1.559771, 2.443375",\ + "0.815861, 0.991733, 1.220284, 1.661672, 2.545220",\ + "1.039228, 1.215100, 1.457424, 1.898838, 2.782437",\ + "1.603236, 1.779108, 2.033040, 2.474486, 3.358148",\ + "0.741263, 0.917078, 1.131107, 1.572062, 2.454779",\ + "0.787801, 0.963617, 1.182490, 1.623684, 2.506884",\ + "0.873466, 1.049282, 1.284419, 1.725586, 2.608729",\ + "1.096833, 1.272649, 1.521559, 1.962752, 2.845946",\ + "1.660841, 1.842122, 2.097176, 2.538399, 3.421657",\ + "1.043307, 1.237664, 1.482704, 1.921298, 2.800235",\ + "1.089845, 1.288972, 1.534089, 1.972921, 2.852340",\ + "1.175511, 1.390910, 1.636018, 2.074823, 2.954185",\ + "1.398878, 1.628042, 1.873158, 2.311989, 3.191402",\ + "1.962886, 2.203649, 2.448775, 2.887636, 3.767113"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011"); + values ( "0.052252, 0.052252, 0.052266, 0.052296, 0.052356",\ + "0.174387, 0.174387, 0.174377, 0.174356, 0.174314",\ + "0.378093, 0.378093, 0.378069, 0.378020, 0.377921",\ + "0.885671, 0.885671, 0.885661, 0.885629, 0.885567",\ + "2.162771, 2.162771, 2.162787, 2.162833, 2.162925",\ + "0.052252, 0.052252, 0.052266, 0.052296, 0.052356",\ + "0.174387, 0.174387, 0.174377, 0.174356, 0.174314",\ + "0.378093, 0.378093, 0.378069, 0.378020, 0.377921",\ + "0.885671, 0.885671, 0.885661, 0.885629, 0.885567",\ + "2.162771, 2.162771, 2.162787, 2.162833, 2.162925",\ + "0.052252, 0.052252, 0.052266, 0.052296, 0.052356",\ + "0.174387, 0.174387, 0.174377, 0.174356, 0.174314",\ + "0.378093, 0.378093, 0.378069, 0.378020, 0.377921",\ + "0.885671, 0.885671, 0.885661, 0.885629, 0.885567",\ + "2.162771, 2.162771, 2.162787, 2.162833, 2.162925",\ + "0.052252, 0.052252, 0.052266, 0.052296, 0.052356",\ + "0.174387, 0.174387, 0.174377, 0.174356, 0.174314",\ + "0.378093, 0.378093, 0.378069, 0.378020, 0.377921",\ + "0.885671, 0.885671, 0.885661, 0.885629, 0.885567",\ + "2.162771, 2.162772, 2.162787, 2.162833, 2.162925",\ + "0.052252, 0.052255, 0.052266, 0.052296, 0.052356",\ + "0.174387, 0.174384, 0.174376, 0.174356, 0.174314",\ + "0.378093, 0.378087, 0.378069, 0.378020, 0.377921",\ + "0.885671, 0.885670, 0.885660, 0.885629, 0.885567",\ + "2.162771, 2.162773, 2.162788, 2.162833, 2.162925"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011"); + values ( "0.453647, 0.675841, 0.933001, 1.375582, 2.260746",\ + "0.507082, 0.698390, 0.955556, 1.398159, 2.283364",\ + "0.567945, 0.744346, 0.996821, 1.439418, 2.324611",\ + "0.702647, 0.879047, 1.118872, 1.561445, 2.446589",\ + "1.049097, 1.225497, 1.451556, 1.894090, 2.779158",\ + "0.541058, 0.763317, 1.020484, 1.462297, 2.346680",\ + "0.594493, 0.785866, 1.043040, 1.484873, 2.369298",\ + "0.655356, 0.831728, 1.084305, 1.526132, 2.410545",\ + "0.790057, 0.966429, 1.206356, 1.648159, 2.532523",\ + "1.136508, 1.312880, 1.539039, 1.980805, 2.865092",\ + "0.621891, 0.852130, 1.108447, 1.549919, 2.433635",\ + "0.675327, 0.874679, 1.131002, 1.572495, 2.456253",\ + "0.736189, 0.915945, 1.172267, 1.613754, 2.497500",\ + "0.870891, 1.046763, 1.294318, 1.735781, 2.619478",\ + "1.217341, 1.393214, 1.627002, 2.068427, 2.952047",\ + "0.679497, 0.917520, 1.172582, 1.613832, 2.497144",\ + "0.732932, 0.940069, 1.195138, 1.636409, 2.519762",\ + "0.793795, 0.981336, 1.236402, 1.677668, 2.561009",\ + "0.928497, 1.104312, 1.358454, 1.799695, 2.682987",\ + "1.274947, 1.450762, 1.691137, 2.132340, 3.015556",\ + "0.991265, 1.279047, 1.524182, 1.963070, 2.842600",\ + "1.034976, 1.301596, 1.546737, 1.985646, 2.865218",\ + "1.095839, 1.342862, 1.588002, 2.026905, 2.906465",\ + "1.230541, 1.464921, 1.710053, 2.148932, 3.028443",\ + "1.576991, 1.797617, 2.042736, 2.481577, 3.361012"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011"); + values ( "0.060254, 0.060270, 0.060353, 0.060563, 0.060983",\ + "0.114289, 0.114310, 0.114425, 0.114712, 0.115288",\ + "0.199967, 0.199967, 0.200091, 0.200354, 0.200879",\ + "0.445518, 0.445518, 0.445532, 0.445561, 0.445620",\ + "1.101422, 1.101422, 1.101415, 1.101402, 1.101375",\ + "0.060254, 0.060270, 0.060354, 0.060563, 0.060983",\ + "0.114289, 0.114310, 0.114425, 0.114712, 0.115288",\ + "0.199967, 0.199967, 0.200092, 0.200354, 0.200879",\ + "0.445518, 0.445518, 0.445532, 0.445561, 0.445620",\ + "1.101422, 1.101422, 1.101415, 1.101402, 1.101375",\ + "0.060254, 0.060270, 0.060354, 0.060563, 0.060983",\ + "0.114289, 0.114311, 0.114426, 0.114712, 0.115288",\ + "0.199967, 0.199987, 0.200092, 0.200354, 0.200879",\ + "0.445518, 0.445518, 0.445532, 0.445561, 0.445620",\ + "1.101422, 1.101422, 1.101415, 1.101402, 1.101375",\ + "0.060254, 0.060271, 0.060354, 0.060563, 0.060983",\ + "0.114289, 0.114311, 0.114426, 0.114712, 0.115288",\ + "0.199967, 0.199988, 0.200092, 0.200354, 0.200879",\ + "0.445518, 0.445518, 0.445532, 0.445561, 0.445620",\ + "1.101422, 1.101422, 1.101415, 1.101402, 1.101375",\ + "0.060254, 0.060277, 0.060356, 0.060564, 0.060983",\ + "0.114289, 0.114319, 0.114428, 0.114714, 0.115288",\ + "0.199967, 0.199995, 0.200095, 0.200355, 0.200879",\ + "0.445518, 0.445521, 0.445532, 0.445561, 0.445620",\ + "1.101422, 1.101420, 1.101415, 1.101402, 1.101375"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[10]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[1]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011"); + values ( "0.248860, 0.467650, 0.646178, 0.935763, 1.497723",\ + "0.314404, 0.533194, 0.711724, 1.001313, 1.563285",\ + "0.400894, 0.619685, 0.798218, 1.087823, 1.649829",\ + "0.616887, 0.835682, 1.014242, 1.303952, 1.866190",\ + "1.171447, 1.390243, 1.568813, 1.858561, 2.420885",\ + "0.337260, 0.554969, 0.733459, 1.023068, 1.585076",\ + "0.402804, 0.620513, 0.799004, 1.088619, 1.650638",\ + "0.489294, 0.707003, 0.885499, 1.175128, 1.737183",\ + "0.705288, 0.923001, 1.101523, 1.391257, 1.953543",\ + "1.259847, 1.477562, 1.656094, 1.945866, 2.508239",\ + "0.426158, 0.635305, 0.813486, 1.103096, 1.665108",\ + "0.491702, 0.700850, 0.879031, 1.168647, 1.730670",\ + "0.578191, 0.787340, 0.965526, 1.255157, 1.817214",\ + "0.794185, 1.003338, 1.181550, 1.471285, 2.033575",\ + "1.348745, 1.557899, 1.736121, 2.025895, 2.588270",\ + "0.489181, 0.693123, 0.871180, 1.160527, 1.722125",\ + "0.554726, 0.758668, 0.936725, 1.226078, 1.787687",\ + "0.641215, 0.845158, 1.023220, 1.312588, 1.874232",\ + "0.857210, 1.061156, 1.239244, 1.528717, 2.090593",\ + "1.411770, 1.615717, 1.793815, 2.083326, 2.645288",\ + "0.817972, 0.998369, 1.174837, 1.463701, 2.024349",\ + "0.883517, 1.063914, 1.240382, 1.529251, 2.089911",\ + "0.970006, 1.150404, 1.326877, 1.615761, 2.176455",\ + "1.186001, 1.366402, 1.542901, 1.831890, 2.392817",\ + "1.740560, 1.920963, 2.097472, 2.386500, 2.947513"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011"); + values ( "0.135658, 0.135697, 0.135954, 0.136439, 0.137406",\ + "0.233360, 0.233354, 0.233337, 0.233240, 0.233017",\ + "0.397359, 0.397363, 0.397387, 0.397480, 0.397688",\ + "0.873501, 0.873500, 0.873498, 0.873489, 0.873469",\ + "2.140095, 2.140101, 2.140141, 2.140298, 2.140647",\ + "0.135659, 0.135697, 0.135954, 0.136439, 0.137406",\ + "0.233360, 0.233354, 0.233337, 0.233240, 0.233017",\ + "0.397359, 0.397363, 0.397387, 0.397480, 0.397688",\ + "0.873501, 0.873500, 0.873498, 0.873489, 0.873469",\ + "2.140095, 2.140101, 2.140141, 2.140298, 2.140647",\ + "0.135662, 0.135697, 0.135954, 0.136439, 0.137406",\ + "0.233359, 0.233354, 0.233337, 0.233240, 0.233017",\ + "0.397360, 0.397363, 0.397387, 0.397480, 0.397688",\ + "0.873500, 0.873500, 0.873498, 0.873489, 0.873469",\ + "2.140095, 2.140101, 2.140141, 2.140298, 2.140647",\ + "0.135665, 0.135698, 0.135954, 0.136441, 0.137409",\ + "0.233359, 0.233354, 0.233337, 0.233240, 0.233016",\ + "0.397360, 0.397363, 0.397387, 0.397480, 0.397689",\ + "0.873500, 0.873500, 0.873498, 0.873489, 0.873469",\ + "2.140096, 2.140101, 2.140141, 2.140298, 2.140648",\ + "0.135663, 0.135699, 0.135954, 0.136442, 0.137411",\ + "0.233359, 0.233354, 0.233337, 0.233240, 0.233016",\ + "0.397360, 0.397363, 0.397387, 0.397480, 0.397689",\ + "0.873500, 0.873500, 0.873498, 0.873489, 0.873469",\ + "2.140096, 2.140101, 2.140141, 2.140299, 2.140649"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011"); + values ( "0.265941, 0.478440, 0.661761, 0.953483, 1.516542",\ + "0.295974, 0.514750, 0.693420, 0.983435, 1.546355",\ + "0.342294, 0.561099, 0.739726, 1.029692, 1.592503",\ + "0.466491, 0.685293, 0.863899, 1.153787, 1.716424",\ + "0.798732, 1.017531, 1.196112, 1.485904, 2.048326",\ + "0.354342, 0.565759, 0.749042, 1.040788, 1.603895",\ + "0.384375, 0.602069, 0.780701, 1.070740, 1.633708",\ + "0.430695, 0.648418, 0.827006, 1.116997, 1.679856",\ + "0.554892, 0.772612, 0.951180, 1.241092, 1.803777",\ + "0.887133, 1.104849, 1.283393, 1.573209, 2.135679",\ + "0.443241, 0.646096, 0.829069, 1.120816, 1.683927",\ + "0.473273, 0.682406, 0.860728, 1.150768, 1.713740",\ + "0.519593, 0.728755, 0.907033, 1.197025, 1.759888",\ + "0.643790, 0.852948, 1.031207, 1.321121, 1.883808",\ + "0.976031, 1.185186, 1.363420, 1.653237, 2.215711",\ + "0.506266, 0.703926, 0.886774, 1.178249, 1.740947",\ + "0.536299, 0.740226, 0.918422, 1.208200, 1.770759",\ + "0.582618, 0.786573, 0.964728, 1.254457, 1.816907",\ + "0.706815, 0.910767, 1.088901, 1.378552, 1.940827",\ + "1.039055, 1.243004, 1.421114, 1.710669, 2.272729",\ + "0.825950, 1.009259, 1.190433, 1.481423, 2.043174",\ + "0.864615, 1.045486, 1.222079, 1.511375, 2.072986",\ + "0.911409, 1.091819, 1.268385, 1.557632, 2.119133",\ + "1.035605, 1.216013, 1.392558, 1.681726, 2.243053",\ + "1.367846, 1.548250, 1.724771, 2.013843, 2.574954"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011"); + values ( "0.067593, 0.067594, 0.067599, 0.067617, 0.067659",\ + "0.104760, 0.104760, 0.104762, 0.104772, 0.104794",\ + "0.190700, 0.190700, 0.190699, 0.190697, 0.190692",\ + "0.432608, 0.432613, 0.432644, 0.432766, 0.433037",\ + "1.067886, 1.067868, 1.067749, 1.067290, 1.066264",\ + "0.067593, 0.067594, 0.067599, 0.067617, 0.067659",\ + "0.104760, 0.104760, 0.104762, 0.104772, 0.104794",\ + "0.190700, 0.190700, 0.190699, 0.190697, 0.190692",\ + "0.432608, 0.432613, 0.432644, 0.432766, 0.433037",\ + "1.067886, 1.067868, 1.067749, 1.067290, 1.066264",\ + "0.067593, 0.067594, 0.067599, 0.067617, 0.067659",\ + "0.104760, 0.104760, 0.104762, 0.104772, 0.104794",\ + "0.190700, 0.190700, 0.190699, 0.190697, 0.190692",\ + "0.432609, 0.432613, 0.432644, 0.432766, 0.433037",\ + "1.067884, 1.067868, 1.067749, 1.067290, 1.066264",\ + "0.067593, 0.067594, 0.067599, 0.067617, 0.067659",\ + "0.104760, 0.104760, 0.104762, 0.104772, 0.104794",\ + "0.190700, 0.190700, 0.190699, 0.190697, 0.190692",\ + "0.432609, 0.432613, 0.432644, 0.432766, 0.433038",\ + "1.067883, 1.067868, 1.067749, 1.067289, 1.066261",\ + "0.067593, 0.067594, 0.067599, 0.067617, 0.067659",\ + "0.104760, 0.104760, 0.104762, 0.104772, 0.104794",\ + "0.190700, 0.190700, 0.190699, 0.190697, 0.190692",\ + "0.432609, 0.432613, 0.432644, 0.432766, 0.433039",\ + "1.067883, 1.067867, 1.067749, 1.067287, 1.066258"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[10]_redg_min_2547*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[57]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011"); + values ( "0.230530, 0.471836, 0.662565, 0.965687, 1.550670",\ + "0.296073, 0.537386, 0.728118, 1.031247, 1.616246",\ + "0.382561, 0.623892, 0.814634, 1.117786, 1.702834",\ + "0.598538, 0.839995, 1.030804, 1.334111, 1.919485",\ + "1.153092, 1.394595, 1.585429, 1.888794, 2.474288",\ + "0.318838, 0.559155, 0.749846, 1.052992, 1.638023",\ + "0.384382, 0.624704, 0.815398, 1.118552, 1.703600",\ + "0.470869, 0.711210, 0.901915, 1.205091, 1.790187",\ + "0.686851, 0.927314, 1.118085, 1.421416, 2.006838",\ + "1.241406, 1.481914, 1.672710, 1.976099, 2.561641",\ + "0.407830, 0.639488, 0.829873, 1.133020, 1.718055",\ + "0.473374, 0.705038, 0.895425, 1.198581, 1.783631",\ + "0.559863, 0.791544, 0.981942, 1.285120, 1.870219",\ + "0.775854, 1.007647, 1.198112, 1.501445, 2.086870",\ + "1.330413, 1.562247, 1.752737, 2.056127, 2.641673",\ + "0.471102, 0.697352, 0.887595, 1.190479, 1.775129",\ + "0.536647, 0.762902, 0.953148, 1.256040, 1.840706",\ + "0.623137, 0.849408, 1.039664, 1.342579, 1.927294",\ + "0.839138, 1.065512, 1.255835, 1.558905, 2.143945",\ + "1.393700, 1.620112, 1.810460, 2.113587, 2.698749",\ + "0.805138, 1.002911, 1.191255, 1.493676, 2.077422",\ + "0.870685, 1.068460, 1.256808, 1.559237, 2.142998",\ + "0.957184, 1.154967, 1.343324, 1.645776, 2.229586",\ + "1.173243, 1.371074, 1.559495, 1.862102, 2.446239",\ + "1.727827, 1.925676, 2.114120, 2.416785, 3.001042"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011"); + values ( "0.135507, 0.136708, 0.137351, 0.137726, 0.138133",\ + "0.232782, 0.232782, 0.232782, 0.232782, 0.232782",\ + "0.397345, 0.397457, 0.397518, 0.397656, 0.397948",\ + "0.873409, 0.873409, 0.873409, 0.873409, 0.873409",\ + "2.140071, 2.140260, 2.140361, 2.140594, 2.141085",\ + "0.135540, 0.136708, 0.137351, 0.137726, 0.138133",\ + "0.232782, 0.232782, 0.232782, 0.232782, 0.232782",\ + "0.397348, 0.397457, 0.397518, 0.397656, 0.397948",\ + "0.873409, 0.873409, 0.873409, 0.873409, 0.873409",\ + "2.140076, 2.140260, 2.140361, 2.140594, 2.141085",\ + "0.135636, 0.136708, 0.137351, 0.137726, 0.138133",\ + "0.232782, 0.232782, 0.232782, 0.232782, 0.232782",\ + "0.397357, 0.397457, 0.397518, 0.397656, 0.397948",\ + "0.873409, 0.873409, 0.873409, 0.873409, 0.873409",\ + "2.140091, 2.140260, 2.140361, 2.140594, 2.141085",\ + "0.135724, 0.136712, 0.137353, 0.137727, 0.138134",\ + "0.232782, 0.232782, 0.232782, 0.232782, 0.232782",\ + "0.397365, 0.397458, 0.397518, 0.397657, 0.397949",\ + "0.873409, 0.873409, 0.873409, 0.873409, 0.873409",\ + "2.140105, 2.140261, 2.140362, 2.140594, 2.141086",\ + "0.136284, 0.136744, 0.137353, 0.137727, 0.138135",\ + "0.232782, 0.232782, 0.232782, 0.232782, 0.232782",\ + "0.397418, 0.397461, 0.397518, 0.397657, 0.397950",\ + "0.873409, 0.873409, 0.873409, 0.873409, 0.873409",\ + "2.140193, 2.140266, 2.140362, 2.140595, 2.141087"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011"); + values ( "0.247536, 0.465909, 0.655111, 0.957872, 1.542809",\ + "0.277578, 0.504859, 0.694166, 0.997452, 1.583596",\ + "0.323906, 0.557991, 0.747485, 1.050859, 1.637228",\ + "0.448115, 0.688036, 0.877811, 1.181150, 1.767445",\ + "0.780371, 1.021927, 1.212790, 1.516219, 2.101851",\ + "0.335860, 0.553227, 0.742392, 1.045177, 1.630162",\ + "0.365901, 0.592177, 0.781447, 1.084757, 1.670949",\ + "0.412227, 0.645309, 0.834766, 1.138164, 1.724581",\ + "0.536433, 0.775355, 0.965092, 1.268455, 1.854799",\ + "0.868686, 1.109246, 1.300071, 1.603524, 2.189205",\ + "0.424900, 0.633561, 0.822419, 1.125205, 1.710194",\ + "0.454934, 0.672511, 0.861474, 1.164785, 1.750981",\ + "0.501255, 0.725643, 0.914793, 1.218192, 1.804613",\ + "0.625454, 0.855688, 1.045119, 1.348483, 1.934830",\ + "0.957698, 1.189579, 1.380097, 1.683553, 2.269236",\ + "0.488215, 0.691382, 0.880139, 1.182665, 1.767268",\ + "0.518244, 0.730333, 0.919194, 1.222246, 1.808058",\ + "0.564561, 0.783480, 0.972513, 1.275653, 1.861690",\ + "0.688753, 0.913547, 1.102839, 1.405944, 1.991908",\ + "1.020988, 1.247444, 1.437820, 1.741013, 2.326312",\ + "0.816645, 0.996641, 1.183799, 1.485862, 2.069561",\ + "0.852522, 1.035597, 1.222854, 1.525444, 2.110354",\ + "0.898812, 1.088847, 1.276173, 1.578852, 2.163987",\ + "1.022959, 1.219069, 1.406500, 1.709143, 2.294204",\ + "1.355140, 1.553009, 1.741481, 2.044211, 2.628607"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011"); + values ( "0.067590, 0.067613, 0.067625, 0.067653, 0.067711",\ + "0.104758, 0.104770, 0.104776, 0.104791, 0.104822",\ + "0.190676, 0.190676, 0.190676, 0.190676, 0.190676",\ + "0.432590, 0.432736, 0.432815, 0.432996, 0.433377",\ + "1.063080, 1.063080, 1.063080, 1.063080, 1.063080",\ + "0.067591, 0.067613, 0.067625, 0.067653, 0.067711",\ + "0.104758, 0.104770, 0.104776, 0.104791, 0.104822",\ + "0.190676, 0.190676, 0.190676, 0.190676, 0.190676",\ + "0.432594, 0.432736, 0.432815, 0.432996, 0.433377",\ + "1.063080, 1.063080, 1.063080, 1.063080, 1.063080",\ + "0.067593, 0.067613, 0.067625, 0.067653, 0.067711",\ + "0.104759, 0.104770, 0.104776, 0.104791, 0.104822",\ + "0.190676, 0.190676, 0.190676, 0.190676, 0.190676",\ + "0.432605, 0.432736, 0.432815, 0.432996, 0.433377",\ + "1.063080, 1.063080, 1.063080, 1.063080, 1.063080",\ + "0.067594, 0.067613, 0.067625, 0.067653, 0.067711",\ + "0.104760, 0.104770, 0.104776, 0.104791, 0.104822",\ + "0.190676, 0.190676, 0.190676, 0.190676, 0.190676",\ + "0.432616, 0.432737, 0.432815, 0.432996, 0.433378",\ + "1.063080, 1.063080, 1.063080, 1.063080, 1.063080",\ + "0.067593, 0.067614, 0.067625, 0.067653, 0.067711",\ + "0.104766, 0.104770, 0.104776, 0.104791, 0.104822",\ + "0.190676, 0.190676, 0.190676, 0.190676, 0.190676",\ + "0.432685, 0.432741, 0.432815, 0.432997, 0.433379",\ + "1.063080, 1.063080, 1.063080, 1.063080, 1.063080"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[10]_redg_min*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[58]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011"); + values ( "0.244473, 0.505671, 0.697935, 0.998174, 1.574785",\ + "0.300254, 0.556634, 0.748837, 1.048824, 1.624875",\ + "0.376032, 0.633972, 0.826223, 1.125987, 1.701451",\ + "0.578226, 0.841738, 1.034663, 1.334155, 1.908979",\ + "1.122810, 1.385726, 1.587938, 1.887184, 2.461388",\ + "0.332840, 0.592988, 0.785216, 1.085479, 1.662138",\ + "0.388618, 0.643952, 0.836118, 1.136129, 1.712228",\ + "0.464390, 0.721290, 0.913504, 1.213292, 1.788804",\ + "0.666574, 0.929242, 1.121944, 1.421460, 1.996333",\ + "1.211151, 1.473226, 1.675219, 1.974489, 2.548742",\ + "0.422672, 0.673316, 0.865243, 1.165508, 1.742170",\ + "0.478441, 0.724280, 0.916145, 1.216158, 1.792260",\ + "0.554191, 0.801618, 0.993531, 1.293321, 1.868836",\ + "0.756345, 1.010087, 1.201971, 1.501488, 2.076365",\ + "1.300900, 1.562060, 1.755246, 2.054518, 2.628773",\ + "0.487019, 0.731152, 0.922971, 1.222957, 1.799227",\ + "0.542778, 0.782116, 0.973873, 1.273607, 1.849315",\ + "0.618509, 0.859454, 1.051260, 1.350769, 1.925890",\ + "0.820633, 1.067923, 1.259699, 1.558936, 2.133417",\ + "1.365167, 1.621171, 1.812974, 2.111965, 2.685824",\ + "0.827863, 1.036490, 1.226631, 1.526145, 2.101498",\ + "0.883564, 1.087454, 1.277533, 1.576794, 2.151585",\ + "0.959165, 1.164792, 1.354919, 1.653956, 2.228158",\ + "1.161104, 1.373262, 1.563359, 1.862122, 2.435683",\ + "1.705499, 1.926510, 2.116634, 2.415150, 2.988089"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011"); + values ( "0.150101, 0.150101, 0.150101, 0.151542, 0.155060",\ + "0.237371, 0.237371, 0.237371, 0.238239, 0.240357",\ + "0.400588, 0.400588, 0.400588, 0.400716, 0.401031",\ + "0.873603, 0.873603, 0.873603, 0.873603, 0.873603",\ + "2.136242, 2.138523, 2.138971, 2.139329, 2.139329",\ + "0.150101, 0.150101, 0.150101, 0.151542, 0.155060",\ + "0.237371, 0.237371, 0.237371, 0.238239, 0.240357",\ + "0.400588, 0.400588, 0.400588, 0.400716, 0.401031",\ + "0.873603, 0.873603, 0.873603, 0.873603, 0.873603",\ + "2.136282, 2.138528, 2.138971, 2.139329, 2.139329",\ + "0.150101, 0.150101, 0.150101, 0.151542, 0.155060",\ + "0.237371, 0.237371, 0.237371, 0.238239, 0.240357",\ + "0.400588, 0.400588, 0.400588, 0.400716, 0.401031",\ + "0.873603, 0.873603, 0.873603, 0.873603, 0.873603",\ + "2.136409, 2.138540, 2.138971, 2.139329, 2.139329",\ + "0.150101, 0.150101, 0.150101, 0.151547, 0.155068",\ + "0.237371, 0.237371, 0.237371, 0.238242, 0.240362",\ + "0.400588, 0.400588, 0.400588, 0.400717, 0.401031",\ + "0.873603, 0.873603, 0.873603, 0.873603, 0.873603",\ + "2.136531, 2.137884, 2.138973, 2.139329, 2.139329",\ + "0.150101, 0.150101, 0.150101, 0.151550, 0.155079",\ + "0.237371, 0.237371, 0.237371, 0.238244, 0.240369",\ + "0.400588, 0.400588, 0.400588, 0.400717, 0.401032",\ + "0.873603, 0.873603, 0.873603, 0.873603, 0.873603",\ + "2.137311, 2.137926, 2.138974, 2.139329, 2.139329"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011"); + values ( "0.243871, 0.423733, 0.615818, 0.915684, 1.491530",\ + "0.279786, 0.459520, 0.651316, 0.952173, 1.530680",\ + "0.334281, 0.513862, 0.705260, 1.006477, 1.586195",\ + "0.467807, 0.647364, 0.838496, 1.139651, 1.719442",\ + "0.802494, 0.981904, 1.172736, 1.473617, 2.052986",\ + "0.331272, 0.511050, 0.703099, 1.002989, 1.578883",\ + "0.367188, 0.546838, 0.738597, 1.039478, 1.618034",\ + "0.421683, 0.601180, 0.792541, 1.093782, 1.673548",\ + "0.555208, 0.734681, 0.925777, 1.226957, 1.806796",\ + "0.889896, 1.069221, 1.260017, 1.560922, 2.140339",\ + "0.412125, 0.591378, 0.783126, 1.083017, 1.658915",\ + "0.448040, 0.627166, 0.818624, 1.119507, 1.698066",\ + "0.502534, 0.681508, 0.872568, 1.173811, 1.753580",\ + "0.636060, 0.815010, 1.005804, 1.306985, 1.886827",\ + "0.970746, 1.149549, 1.340044, 1.640951, 2.220371",\ + "0.469856, 0.649214, 0.840854, 1.140466, 1.715970",\ + "0.505769, 0.685001, 0.876351, 1.176959, 1.755127",\ + "0.560262, 0.739342, 0.930294, 1.231264, 1.810644",\ + "0.693787, 0.872844, 1.063529, 1.364439, 1.943892",\ + "1.028472, 1.207383, 1.397769, 1.698404, 2.277434",\ + "0.773472, 0.954547, 1.144514, 1.443653, 2.018239",\ + "0.809371, 0.990331, 1.180011, 1.480149, 2.057404",\ + "0.863847, 1.044668, 1.233954, 1.534456, 2.112924",\ + "0.997369, 1.178169, 1.367189, 1.667630, 2.246172",\ + "1.332038, 1.512705, 1.701428, 2.001595, 2.579713"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011"); + values ( "0.071845, 0.072069, 0.072077, 0.072933, 0.075022",\ + "0.105010, 0.105036, 0.105037, 0.105381, 0.106219",\ + "0.190967, 0.191120, 0.191139, 0.191258, 0.191538",\ + "0.431534, 0.431534, 0.431534, 0.431534, 0.431534",\ + "1.063081, 1.064842, 1.065453, 1.065643, 1.065643",\ + "0.071845, 0.072069, 0.072077, 0.072933, 0.075022",\ + "0.105010, 0.105036, 0.105037, 0.105381, 0.106219",\ + "0.190967, 0.191120, 0.191139, 0.191258, 0.191538",\ + "0.431534, 0.431534, 0.431534, 0.431534, 0.431534",\ + "1.063081, 1.064842, 1.065453, 1.065643, 1.065643",\ + "0.071847, 0.072069, 0.072077, 0.072933, 0.075022",\ + "0.105010, 0.105036, 0.105037, 0.105381, 0.106219",\ + "0.190967, 0.191120, 0.191139, 0.191258, 0.191538",\ + "0.431534, 0.431534, 0.431534, 0.431534, 0.431534",\ + "1.063091, 1.064842, 1.065453, 1.065643, 1.065643",\ + "0.071849, 0.072070, 0.072077, 0.072936, 0.075027",\ + "0.105011, 0.105036, 0.105037, 0.105382, 0.106221",\ + "0.190969, 0.191121, 0.191139, 0.191259, 0.191539",\ + "0.431534, 0.431534, 0.431534, 0.431534, 0.431534",\ + "1.063112, 1.064849, 1.065454, 1.065643, 1.065643",\ + "0.071874, 0.072076, 0.072077, 0.072938, 0.075034",\ + "0.105014, 0.105037, 0.105037, 0.105382, 0.106223",\ + "0.190986, 0.191125, 0.191139, 0.191259, 0.191540",\ + "0.431534, 0.431534, 0.431534, 0.431534, 0.431534",\ + "1.063308, 1.064895, 1.065455, 1.065643, 1.065643"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[10]_redg_min_2493*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[62]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011"); + values ( "0.377825, 0.634223, 0.868848, 1.157402, 1.717689",\ + "0.428298, 0.684702, 0.914931, 1.203491, 1.763791",\ + "0.530100, 0.786503, 1.000029, 1.288605, 1.848942",\ + "0.768016, 1.024419, 1.221793, 1.510395, 2.070789",\ + "1.340420, 1.596824, 1.783889, 2.072520, 2.632977",\ + "0.466032, 0.721699, 0.956129, 1.244707, 1.805043",\ + "0.516506, 0.772177, 1.002212, 1.290796, 1.851145",\ + "0.618307, 0.873978, 1.087310, 1.375910, 1.936295",\ + "0.856223, 1.111895, 1.309074, 1.597700, 2.158142",\ + "1.428628, 1.684300, 1.871170, 2.159825, 2.720331",\ + "0.554696, 0.810512, 1.036155, 1.324735, 1.885074",\ + "0.605170, 0.860990, 1.082239, 1.370825, 1.931176",\ + "0.706971, 0.962791, 1.167337, 1.455939, 2.016327",\ + "0.944887, 1.200708, 1.389101, 1.677728, 2.238174",\ + "1.517292, 1.773113, 1.951197, 2.239853, 2.800363",\ + "0.617648, 0.875902, 1.093848, 1.382165, 1.942089",\ + "0.668122, 0.926381, 1.139932, 1.428254, 1.988191",\ + "0.769923, 1.028182, 1.225029, 1.513368, 2.073342",\ + "1.007839, 1.266098, 1.446793, 1.735158, 2.295189",\ + "1.580244, 1.831772, 2.008889, 2.297283, 2.857378",\ + "0.949653, 1.221972, 1.397504, 1.685336, 2.244309",\ + "1.000127, 1.268054, 1.443587, 1.731425, 2.290411",\ + "1.101928, 1.353148, 1.528685, 1.816540, 2.375562",\ + "1.339844, 1.574905, 1.750449, 2.038329, 2.597409",\ + "1.912249, 2.136994, 2.312545, 2.600454, 3.159598"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011"); + values ( "0.041017, 0.041026, 0.041033, 0.041274, 0.041853",\ + "0.147926, 0.147927, 0.147928, 0.147959, 0.148033",\ + "0.374819, 0.374818, 0.374816, 0.374779, 0.374688",\ + "0.869171, 0.869170, 0.869169, 0.869164, 0.869153",\ + "2.137120, 2.137120, 2.137119, 2.137116, 2.137110",\ + "0.041017, 0.041026, 0.041033, 0.041274, 0.041853",\ + "0.147926, 0.147927, 0.147928, 0.147959, 0.148033",\ + "0.374819, 0.374818, 0.374816, 0.374779, 0.374688",\ + "0.869171, 0.869170, 0.869169, 0.869164, 0.869153",\ + "2.137120, 2.137120, 2.137119, 2.137116, 2.137110",\ + "0.041017, 0.041026, 0.041033, 0.041274, 0.041853",\ + "0.147926, 0.147927, 0.147928, 0.147959, 0.148033",\ + "0.374819, 0.374817, 0.374816, 0.374779, 0.374688",\ + "0.869171, 0.869170, 0.869169, 0.869164, 0.869153",\ + "2.137120, 2.137120, 2.137119, 2.137116, 2.137110",\ + "0.041017, 0.041026, 0.041033, 0.041275, 0.041855",\ + "0.147926, 0.147927, 0.147928, 0.147959, 0.148033",\ + "0.374819, 0.374817, 0.374816, 0.374778, 0.374688",\ + "0.869171, 0.869170, 0.869169, 0.869164, 0.869153",\ + "2.137120, 2.137120, 2.137119, 2.137116, 2.137110",\ + "0.041017, 0.041017, 0.041033, 0.041276, 0.041856",\ + "0.147926, 0.147926, 0.147928, 0.147959, 0.148034",\ + "0.374819, 0.374819, 0.374816, 0.374778, 0.374687",\ + "0.869171, 0.869171, 0.869169, 0.869164, 0.869153",\ + "2.137120, 2.137120, 2.137119, 2.137116, 2.137110"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011"); + values ( "0.419293, 0.629601, 0.807148, 1.095622, 1.655731",\ + "0.441693, 0.683002, 0.860568, 1.149118, 1.709396",\ + "0.483042, 0.739446, 0.921121, 1.209730, 1.770140",\ + "0.605027, 0.861431, 1.052488, 1.341094, 1.901499",\ + "0.936548, 1.192951, 1.389827, 1.678402, 2.238737",\ + "0.507500, 0.716919, 0.894429, 1.182927, 1.743084",\ + "0.529901, 0.770320, 0.947849, 1.236423, 1.796750",\ + "0.571249, 0.826922, 1.008402, 1.297035, 1.857493",\ + "0.693234, 0.948907, 1.139769, 1.428399, 1.988852",\ + "1.024755, 1.280427, 1.477108, 1.765707, 2.326091",\ + "0.596164, 0.797253, 0.974456, 1.262956, 1.823116",\ + "0.618565, 0.850654, 1.027876, 1.316451, 1.876781",\ + "0.659913, 0.911193, 1.088429, 1.377064, 1.937525",\ + "0.781898, 1.037719, 1.219796, 1.508428, 2.068884",\ + "1.113419, 1.369240, 1.557135, 1.845736, 2.406122",\ + "0.659116, 0.855070, 1.032148, 1.320385, 1.880130",\ + "0.681517, 0.908471, 1.085568, 1.373881, 1.933796",\ + "0.722865, 0.969009, 1.146121, 1.434493, 1.994540",\ + "0.844850, 1.100376, 1.277488, 1.565857, 2.125898",\ + "1.176371, 1.434630, 1.614827, 1.903165, 2.463137",\ + "0.981445, 1.160292, 1.335804, 1.623556, 2.182350",\ + "1.013522, 1.213693, 1.389224, 1.677052, 2.236016",\ + "1.054870, 1.274231, 1.449777, 1.737664, 2.296760",\ + "1.176855, 1.405599, 1.581144, 1.869029, 2.428119",\ + "1.508376, 1.742946, 1.918483, 2.206336, 2.765357"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011"); + values ( "0.045770, 0.045770, 0.045769, 0.045752, 0.045711",\ + "0.091340, 0.091340, 0.091340, 0.091330, 0.091307",\ + "0.185791, 0.185791, 0.185790, 0.185786, 0.185775",\ + "0.432252, 0.432252, 0.432252, 0.432251, 0.432251",\ + "1.064249, 1.064249, 1.064249, 1.064249, 1.064250",\ + "0.045770, 0.045770, 0.045769, 0.045752, 0.045711",\ + "0.091340, 0.091340, 0.091340, 0.091330, 0.091307",\ + "0.185791, 0.185791, 0.185790, 0.185786, 0.185775",\ + "0.432252, 0.432252, 0.432252, 0.432251, 0.432251",\ + "1.064249, 1.064249, 1.064249, 1.064249, 1.064250",\ + "0.045770, 0.045770, 0.045769, 0.045752, 0.045711",\ + "0.091340, 0.091340, 0.091340, 0.091330, 0.091307",\ + "0.185791, 0.185791, 0.185790, 0.185786, 0.185775",\ + "0.432252, 0.432252, 0.432252, 0.432251, 0.432251",\ + "1.064249, 1.064249, 1.064249, 1.064249, 1.064250",\ + "0.045770, 0.045770, 0.045769, 0.045752, 0.045711",\ + "0.091340, 0.091340, 0.091340, 0.091330, 0.091307",\ + "0.185791, 0.185791, 0.185790, 0.185786, 0.185775",\ + "0.432252, 0.432252, 0.432252, 0.432251, 0.432251",\ + "1.064249, 1.064249, 1.064249, 1.064249, 1.064250",\ + "0.045770, 0.045770, 0.045769, 0.045752, 0.045711",\ + "0.091340, 0.091340, 0.091340, 0.091330, 0.091307",\ + "0.185791, 0.185791, 0.185790, 0.185786, 0.185775",\ + "0.432252, 0.432252, 0.432252, 0.432251, 0.432251",\ + "1.064249, 1.064249, 1.064249, 1.064249, 1.064250"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[10]_redg_min_2445*/ + +} /* end of pin tl_o[10] */ + +pin("tl_o[9]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.020161 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : tl_o[9]; + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[1]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011"); + values ( "0.555398, 0.819461, 1.110403, 1.621818, 2.644648",\ + "0.601280, 0.865373, 1.156432, 1.668153, 2.691596",\ + "0.685796, 0.949972, 1.241371, 1.753978, 2.779193",\ + "0.906647, 1.170955, 1.462887, 1.976883, 3.004877",\ + "1.467724, 1.732179, 2.024706, 2.540253, 3.571347",\ + "0.642813, 0.907018, 1.198106, 1.708533, 2.730582",\ + "0.688695, 0.952929, 1.244136, 1.754869, 2.777529",\ + "0.773211, 1.037529, 1.329078, 1.840694, 2.865127",\ + "0.994062, 1.258512, 1.550598, 2.063599, 3.090810",\ + "1.555139, 1.819737, 2.112422, 2.626968, 3.657281",\ + "0.724929, 0.996034, 1.286073, 1.796156, 2.817537",\ + "0.770813, 1.041946, 1.332103, 1.842491, 2.864485",\ + "0.855331, 1.126547, 1.417045, 1.928316, 2.952082",\ + "1.076186, 1.347532, 1.638566, 2.151221, 3.177765",\ + "1.637269, 1.908760, 2.200390, 2.714591, 3.744236",\ + "0.787882, 1.061721, 1.350220, 1.860070, 2.881046",\ + "0.833767, 1.107633, 1.396250, 1.906405, 2.927994",\ + "0.918287, 1.192236, 1.481192, 1.992230, 3.015591",\ + "1.139145, 1.413225, 1.702713, 2.215135, 3.241274",\ + "1.700230, 1.974455, 2.264537, 2.778505, 3.807745",\ + "1.119904, 1.426659, 1.702520, 2.209597, 3.226502",\ + "1.165792, 1.472579, 1.748554, 2.255933, 3.273450",\ + "1.250324, 1.557204, 1.833505, 2.341762, 3.361047",\ + "1.471201, 1.778225, 2.055039, 2.564673, 3.586730",\ + "2.032307, 2.339493, 2.616879, 3.128049, 4.153201"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011"); + values ( "0.051283, 0.051370, 0.051891, 0.053400, 0.056417",\ + "0.173670, 0.173612, 0.173379, 0.172770, 0.171552",\ + "0.376316, 0.376196, 0.375752, 0.374635, 0.372400",\ + "0.881676, 0.881670, 0.881647, 0.881590, 0.881477",\ + "2.159552, 2.159744, 2.159980, 2.159997, 2.160033",\ + "0.051283, 0.051370, 0.051896, 0.053400, 0.056417",\ + "0.173670, 0.173612, 0.173377, 0.172770, 0.171552",\ + "0.376316, 0.376195, 0.375749, 0.374635, 0.372400",\ + "0.881676, 0.881670, 0.881647, 0.881590, 0.881477",\ + "2.159552, 2.159745, 2.159980, 2.159997, 2.160033",\ + "0.051286, 0.051372, 0.051896, 0.053400, 0.056417",\ + "0.173668, 0.173611, 0.173377, 0.172770, 0.171552",\ + "0.376312, 0.376193, 0.375749, 0.374635, 0.372400",\ + "0.881675, 0.881670, 0.881647, 0.881590, 0.881477",\ + "2.159557, 2.159749, 2.159980, 2.159997, 2.160033",\ + "0.051287, 0.051374, 0.051896, 0.053400, 0.056417",\ + "0.173667, 0.173610, 0.173377, 0.172770, 0.171552",\ + "0.376309, 0.376191, 0.375749, 0.374635, 0.372400",\ + "0.881675, 0.881670, 0.881647, 0.881590, 0.881477",\ + "2.159559, 2.159753, 2.159980, 2.159997, 2.160033",\ + "0.051300, 0.051396, 0.051912, 0.053406, 0.056417",\ + "0.173659, 0.173595, 0.173370, 0.172767, 0.171552",\ + "0.376292, 0.376160, 0.375737, 0.374630, 0.372400",\ + "0.881675, 0.881668, 0.881646, 0.881590, 0.881477",\ + "2.159577, 2.159810, 2.159980, 2.159997, 2.160033"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011"); + values ( "0.496610, 0.760268, 1.051112, 1.563657, 2.588749",\ + "0.547372, 0.811417, 1.102287, 1.613514, 2.635968",\ + "0.606137, 0.870487, 1.162590, 1.677032, 2.705914",\ + "0.741015, 1.005340, 1.297339, 1.811510, 2.839852",\ + "1.088533, 1.352702, 1.644074, 2.156609, 3.181679",\ + "0.584025, 0.847822, 1.138818, 1.650373, 2.674682",\ + "0.634786, 0.898974, 1.189989, 1.700229, 2.721902",\ + "0.693552, 0.958046, 1.250303, 1.763747, 2.791848",\ + "0.828430, 1.092898, 1.385051, 1.898225, 2.925786",\ + "1.175948, 1.440259, 1.731781, 2.243324, 3.267613",\ + "0.666128, 0.936832, 1.226786, 1.737995, 2.761637",\ + "0.716902, 0.987989, 1.277956, 1.787852, 2.808857",\ + "0.775678, 1.047066, 1.338270, 1.851369, 2.878803",\ + "0.910556, 1.181918, 1.473018, 1.985848, 3.012741",\ + "1.258068, 1.529277, 1.819748, 2.330947, 3.354568",\ + "0.729072, 1.002510, 1.290933, 1.801909, 2.825146",\ + "0.779855, 1.053676, 1.342103, 1.851766, 2.872366",\ + "0.838638, 1.112759, 1.402418, 1.915283, 2.942312",\ + "0.973515, 1.247610, 1.537165, 2.049762, 3.076250",\ + "1.321024, 1.594967, 1.883895, 2.394861, 3.418077",\ + "1.061036, 1.367345, 1.643245, 2.151441, 3.170603",\ + "1.111874, 1.418610, 1.694402, 2.201292, 3.217822",\ + "1.170700, 1.477770, 1.754749, 2.264823, 3.287768",\ + "1.305573, 1.612615, 1.889494, 2.399300, 3.421706",\ + "1.653060, 1.959932, 2.236207, 2.744392, 3.763533"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011"); + values ( "0.056276, 0.056853, 0.059193, 0.065291, 0.077487",\ + "0.108806, 0.109601, 0.112826, 0.121230, 0.138038",\ + "0.194961, 0.195687, 0.198632, 0.206304, 0.221649",\ + "0.444958, 0.445039, 0.445369, 0.446227, 0.447944",\ + "1.101681, 1.101643, 1.101491, 1.101094, 1.100299",\ + "0.056276, 0.056857, 0.059213, 0.065291, 0.077487",\ + "0.108806, 0.109606, 0.112853, 0.121230, 0.138038",\ + "0.194961, 0.195692, 0.198656, 0.206304, 0.221649",\ + "0.444958, 0.445040, 0.445371, 0.446227, 0.447944",\ + "1.101681, 1.101643, 1.101490, 1.101094, 1.100299",\ + "0.056295, 0.056865, 0.059213, 0.065291, 0.077487",\ + "0.108832, 0.109618, 0.112853, 0.121230, 0.138038",\ + "0.194985, 0.195703, 0.198657, 0.206304, 0.221649",\ + "0.444961, 0.445041, 0.445371, 0.446227, 0.447944",\ + "1.101680, 1.101642, 1.101490, 1.101094, 1.100299",\ + "0.056308, 0.056878, 0.059214, 0.065291, 0.077487",\ + "0.108850, 0.109635, 0.112855, 0.121230, 0.138038",\ + "0.195002, 0.195719, 0.198658, 0.206304, 0.221649",\ + "0.444963, 0.445043, 0.445372, 0.446227, 0.447944",\ + "1.101679, 1.101642, 1.101490, 1.101094, 1.100299",\ + "0.056389, 0.057025, 0.059276, 0.065316, 0.077487",\ + "0.108962, 0.109837, 0.112940, 0.121265, 0.138038",\ + "0.195104, 0.195903, 0.198736, 0.206336, 0.221649",\ + "0.444974, 0.445063, 0.445380, 0.446231, 0.447944",\ + "1.101673, 1.101632, 1.101485, 1.101092, 1.100299"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[9]_redg_2686*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[57]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011"); + values ( "0.541885, 0.785038, 1.063858, 1.534026, 2.474360",\ + "0.587770, 0.830960, 1.109901, 1.580353, 2.521255",\ + "0.672293, 0.915590, 1.194882, 1.666154, 2.608697",\ + "0.893156, 1.136622, 1.416462, 1.889021, 2.834138",\ + "1.454245, 1.697900, 1.978353, 2.452348, 3.400338",\ + "0.629296, 0.872602, 1.151428, 1.620740, 2.560294",\ + "0.675181, 0.918525, 1.197473, 1.667067, 2.607188",\ + "0.759703, 1.003156, 1.282456, 1.752868, 2.694631",\ + "0.980566, 1.224188, 1.504040, 1.975736, 2.920072",\ + "1.541656, 1.785468, 2.065936, 2.539063, 3.486272",\ + "0.710134, 0.961613, 1.239393, 1.708362, 2.647249",\ + "0.756019, 1.007537, 1.285437, 1.754689, 2.694144",\ + "0.840542, 1.092169, 1.370420, 1.840490, 2.781586",\ + "1.061405, 1.313204, 1.592004, 2.063357, 3.007027",\ + "1.622495, 1.874487, 2.153900, 2.626685, 3.573227",\ + "0.767752, 1.027293, 1.303532, 1.772275, 2.710758",\ + "0.813637, 1.073217, 1.349577, 1.818602, 2.757653",\ + "0.898160, 1.157852, 1.434560, 1.904403, 2.845095",\ + "1.119024, 1.378891, 1.656144, 2.127271, 3.070536",\ + "1.680114, 1.940177, 2.218040, 2.690598, 3.636736",\ + "1.089850, 1.392206, 1.655411, 2.121627, 3.056214",\ + "1.135741, 1.438139, 1.701459, 2.167955, 3.103108",\ + "1.220283, 1.522803, 1.786450, 2.253759, 3.190551",\ + "1.441176, 1.743885, 2.008048, 2.476632, 3.415992",\ + "2.002299, 2.305221, 2.569958, 3.039965, 3.982192"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011"); + values ( "0.051290, 0.051402, 0.051767, 0.052622, 0.054331",\ + "0.173665, 0.173591, 0.173350, 0.172786, 0.171658",\ + "0.376306, 0.376151, 0.375734, 0.374850, 0.373082",\ + "0.881676, 0.881673, 0.881655, 0.881609, 0.881516",\ + "2.159523, 2.159652, 2.159853, 2.159909, 2.160021",\ + "0.051290, 0.051403, 0.051770, 0.052622, 0.054331",\ + "0.173665, 0.173591, 0.173349, 0.172786, 0.171658",\ + "0.376306, 0.376150, 0.375732, 0.374850, 0.373082",\ + "0.881676, 0.881673, 0.881655, 0.881609, 0.881516",\ + "2.159523, 2.159653, 2.159854, 2.159909, 2.160021",\ + "0.051290, 0.051405, 0.051770, 0.052622, 0.054331",\ + "0.173665, 0.173589, 0.173349, 0.172786, 0.171658",\ + "0.376305, 0.376148, 0.375732, 0.374850, 0.373082",\ + "0.881676, 0.881673, 0.881655, 0.881609, 0.881516",\ + "2.159523, 2.159656, 2.159854, 2.159909, 2.160021",\ + "0.051291, 0.051407, 0.051770, 0.052622, 0.054331",\ + "0.173665, 0.173588, 0.173348, 0.172786, 0.171658",\ + "0.376305, 0.376145, 0.375731, 0.374850, 0.373082",\ + "0.881676, 0.881673, 0.881655, 0.881609, 0.881516",\ + "2.159523, 2.159659, 2.159854, 2.159909, 2.160021",\ + "0.051310, 0.051436, 0.051779, 0.052625, 0.054331",\ + "0.173652, 0.173569, 0.173343, 0.172784, 0.171658",\ + "0.376278, 0.376105, 0.375722, 0.374847, 0.373082",\ + "0.881676, 0.881672, 0.881655, 0.881609, 0.881516",\ + "2.159524, 2.159705, 2.159854, 2.159909, 2.160021"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011"); + values ( "0.483063, 0.725694, 1.002821, 1.469018, 2.401413",\ + "0.533858, 0.776987, 1.055733, 1.525727, 2.465714",\ + "0.592650, 0.836170, 1.116186, 1.589157, 2.535098",\ + "0.727526, 0.971013, 1.250922, 1.723643, 2.669083",\ + "1.075030, 1.318318, 1.597581, 2.068786, 3.011196",\ + "0.570473, 0.813255, 1.090379, 1.555733, 2.487347",\ + "0.621268, 0.864551, 1.143303, 1.612441, 2.551647",\ + "0.680060, 0.923737, 1.203766, 1.675871, 2.621032",\ + "0.814936, 1.058579, 1.338501, 1.810357, 2.755017",\ + "1.162440, 1.405883, 1.685155, 2.155501, 3.097130",\ + "0.651310, 0.902258, 1.178342, 1.643355, 2.574302",\ + "0.702106, 0.953562, 1.231267, 1.700063, 2.638602",\ + "0.760899, 1.012754, 1.291730, 1.763493, 2.707987",\ + "0.895775, 1.147596, 1.426465, 1.897979, 2.841972",\ + "1.243279, 1.494897, 1.773119, 2.243123, 3.184085",\ + "0.708926, 0.967926, 1.242482, 1.707268, 2.637811",\ + "0.759724, 1.019241, 1.295407, 1.763976, 2.702111",\ + "0.818518, 1.078441, 1.355870, 1.827407, 2.771496",\ + "0.953394, 1.213283, 1.490605, 1.961892, 2.905481",\ + "1.300897, 1.560579, 1.837259, 2.307036, 3.247594",\ + "1.030934, 1.332704, 1.594321, 2.056603, 2.983267",\ + "1.081818, 1.384149, 1.647285, 2.113327, 3.047567",\ + "1.140679, 1.443450, 1.707778, 2.176770, 3.116952",\ + "1.275549, 1.578283, 1.842510, 2.311255, 3.250937",\ + "1.623018, 1.925528, 2.189149, 2.656392, 3.593050"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011"); + values ( "0.056326, 0.057067, 0.059477, 0.065125, 0.076422",\ + "0.108874, 0.109896, 0.113217, 0.121001, 0.136571",\ + "0.195024, 0.195957, 0.198988, 0.206096, 0.220310",\ + "0.444965, 0.445069, 0.445409, 0.446204, 0.447794",\ + "1.101678, 1.101629, 1.101472, 1.101105, 1.100369",\ + "0.056326, 0.057072, 0.059494, 0.065125, 0.076422",\ + "0.108874, 0.109903, 0.113241, 0.121001, 0.136571",\ + "0.195024, 0.195963, 0.199011, 0.206096, 0.220310",\ + "0.444965, 0.445070, 0.445411, 0.446204, 0.447794",\ + "1.101678, 1.101629, 1.101471, 1.101105, 1.100369",\ + "0.056327, 0.057083, 0.059495, 0.065125, 0.076422",\ + "0.108876, 0.109918, 0.113242, 0.121001, 0.136571",\ + "0.195025, 0.195977, 0.199011, 0.206096, 0.220310",\ + "0.444965, 0.445072, 0.445411, 0.446204, 0.447794",\ + "1.101678, 1.101628, 1.101471, 1.101105, 1.100369",\ + "0.056330, 0.057100, 0.059496, 0.065125, 0.076422",\ + "0.108880, 0.109941, 0.113243, 0.121001, 0.136571",\ + "0.195029, 0.195998, 0.199012, 0.206096, 0.220310",\ + "0.444966, 0.445074, 0.445411, 0.446204, 0.447794",\ + "1.101677, 1.101627, 1.101471, 1.101105, 1.100369",\ + "0.056457, 0.057292, 0.059553, 0.065149, 0.076422",\ + "0.109056, 0.110205, 0.113322, 0.121034, 0.136571",\ + "0.195189, 0.196239, 0.199085, 0.206125, 0.220310",\ + "0.444983, 0.445101, 0.445419, 0.446207, 0.447794",\ + "1.101669, 1.101615, 1.101467, 1.101103, 1.100369"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[9]_redg_2573*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[58]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011"); + values ( "0.565069, 0.820938, 1.075987, 1.513367, 2.388129",\ + "0.610722, 0.866590, 1.121640, 1.559020, 2.433781",\ + "0.694431, 0.950300, 1.205350, 1.642730, 2.517491",\ + "0.914051, 1.169920, 1.424969, 1.862349, 2.737111",\ + "1.473307, 1.729176, 1.984225, 2.421606, 3.296367",\ + "0.653273, 0.908426, 1.163451, 1.600080, 2.474062",\ + "0.698926, 0.954078, 1.209104, 1.645733, 2.519715",\ + "0.782636, 1.037788, 1.292814, 1.729443, 2.603425",\ + "1.002255, 1.257407, 1.512433, 1.949062, 2.823044",\ + "1.561512, 1.816664, 2.071689, 2.508319, 3.382300",\ + "0.742600, 0.997231, 1.251411, 1.687701, 2.561017",\ + "0.788253, 1.042883, 1.297064, 1.733354, 2.606670",\ + "0.871963, 1.126593, 1.380774, 1.817064, 2.690380",\ + "1.091582, 1.346213, 1.600393, 2.036683, 2.909999",\ + "1.650838, 1.905469, 2.159649, 2.595939, 3.469255",\ + "0.806459, 1.062609, 1.315545, 1.751614, 2.624526",\ + "0.852112, 1.108261, 1.361198, 1.797266, 2.670179",\ + "0.935822, 1.191971, 1.444908, 1.880976, 2.753889",\ + "1.155441, 1.411591, 1.664527, 2.100595, 2.973508",\ + "1.714697, 1.970847, 2.223783, 2.659852, 3.532764",\ + "1.144184, 1.424102, 1.667087, 2.100822, 2.969982",\ + "1.189837, 1.469755, 1.712740, 2.146475, 3.015635",\ + "1.273547, 1.553465, 1.796450, 2.230185, 3.099345",\ + "1.493166, 1.773084, 2.016069, 2.449804, 3.318964",\ + "2.052423, 2.332341, 2.575326, 3.009061, 3.878221"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011"); + values ( "0.051575, 0.051575, 0.051575, 0.051575, 0.051575",\ + "0.175957, 0.175957, 0.175957, 0.175957, 0.175957",\ + "0.378358, 0.378358, 0.378358, 0.378358, 0.378358",\ + "0.881680, 0.881680, 0.881680, 0.881680, 0.881680",\ + "2.159378, 2.159378, 2.159378, 2.159378, 2.159378",\ + "0.051575, 0.051575, 0.051575, 0.051575, 0.051575",\ + "0.175957, 0.175957, 0.175957, 0.175957, 0.175957",\ + "0.378358, 0.378358, 0.378358, 0.378358, 0.378358",\ + "0.881680, 0.881680, 0.881680, 0.881680, 0.881680",\ + "2.159378, 2.159378, 2.159378, 2.159378, 2.159378",\ + "0.051575, 0.051575, 0.051575, 0.051575, 0.051575",\ + "0.175957, 0.175957, 0.175957, 0.175957, 0.175957",\ + "0.378358, 0.378358, 0.378358, 0.378358, 0.378358",\ + "0.881680, 0.881680, 0.881680, 0.881680, 0.881680",\ + "2.159378, 2.159378, 2.159378, 2.159378, 2.159378",\ + "0.051575, 0.051575, 0.051575, 0.051575, 0.051575",\ + "0.175957, 0.175957, 0.175957, 0.175957, 0.175957",\ + "0.378358, 0.378358, 0.378358, 0.378358, 0.378358",\ + "0.881680, 0.881680, 0.881680, 0.881680, 0.881680",\ + "2.159378, 2.159378, 2.159378, 2.159378, 2.159378",\ + "0.051575, 0.051575, 0.051575, 0.051575, 0.051575",\ + "0.175957, 0.175957, 0.175957, 0.175957, 0.175957",\ + "0.378358, 0.378358, 0.378358, 0.378358, 0.378358",\ + "0.881680, 0.881680, 0.881680, 0.881680, 0.881680",\ + "2.159378, 2.159378, 2.159378, 2.159378, 2.159378"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011"); + values ( "0.512229, 0.768098, 1.023147, 1.460527, 2.335289",\ + "0.557112, 0.812981, 1.068030, 1.505411, 2.380172",\ + "0.613030, 0.868899, 1.123949, 1.561329, 2.436090",\ + "0.748455, 1.004324, 1.259373, 1.696754, 2.571515",\ + "1.097588, 1.353456, 1.608506, 2.045886, 2.920648",\ + "0.600433, 0.855585, 1.110611, 1.547240, 2.421222",\ + "0.645316, 0.900469, 1.155494, 1.592124, 2.466105",\ + "0.701235, 0.956387, 1.211413, 1.648042, 2.522024",\ + "0.836659, 1.091812, 1.346837, 1.783467, 2.657449",\ + "1.185792, 1.440944, 1.695970, 2.132599, 3.006581",\ + "0.689760, 0.944391, 1.198571, 1.634861, 2.508177",\ + "0.734643, 0.989274, 1.243454, 1.679744, 2.553061",\ + "0.790562, 1.045192, 1.299373, 1.735663, 2.608979",\ + "0.925986, 1.180617, 1.434798, 1.871087, 2.744404",\ + "1.275119, 1.529750, 1.783930, 2.220220, 3.093536",\ + "0.753619, 1.009769, 1.262705, 1.698774, 2.571686",\ + "0.798502, 1.054652, 1.307589, 1.743657, 2.616570",\ + "0.854421, 1.110570, 1.363507, 1.799575, 2.672488",\ + "0.989845, 1.245995, 1.498932, 1.935000, 2.807913",\ + "1.338978, 1.595128, 1.848064, 2.284132, 3.157045",\ + "1.091344, 1.371262, 1.614247, 2.047982, 2.917142",\ + "1.136228, 1.416146, 1.659131, 2.092866, 2.962026",\ + "1.192146, 1.472064, 1.715049, 2.148784, 3.017944",\ + "1.327571, 1.607489, 1.850474, 2.284209, 3.153369",\ + "1.676703, 1.956621, 2.199606, 2.633341, 3.502501"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011"); + values ( "0.047854, 0.047854, 0.047854, 0.047854, 0.047854",\ + "0.098249, 0.098249, 0.098249, 0.098249, 0.098249",\ + "0.188801, 0.188801, 0.188801, 0.188801, 0.188801",\ + "0.444112, 0.444112, 0.444112, 0.444112, 0.444112",\ + "1.101794, 1.101794, 1.101794, 1.101794, 1.101794",\ + "0.047854, 0.047854, 0.047854, 0.047854, 0.047854",\ + "0.098249, 0.098249, 0.098249, 0.098249, 0.098249",\ + "0.188801, 0.188801, 0.188801, 0.188801, 0.188801",\ + "0.444112, 0.444112, 0.444112, 0.444112, 0.444112",\ + "1.101794, 1.101794, 1.101794, 1.101794, 1.101794",\ + "0.047854, 0.047854, 0.047854, 0.047854, 0.047854",\ + "0.098249, 0.098249, 0.098249, 0.098249, 0.098249",\ + "0.188801, 0.188801, 0.188801, 0.188801, 0.188801",\ + "0.444112, 0.444112, 0.444112, 0.444112, 0.444112",\ + "1.101794, 1.101794, 1.101794, 1.101794, 1.101794",\ + "0.047854, 0.047854, 0.047854, 0.047854, 0.047854",\ + "0.098249, 0.098249, 0.098249, 0.098249, 0.098249",\ + "0.188801, 0.188801, 0.188801, 0.188801, 0.188801",\ + "0.444112, 0.444112, 0.444112, 0.444112, 0.444112",\ + "1.101794, 1.101794, 1.101794, 1.101794, 1.101794",\ + "0.047854, 0.047854, 0.047854, 0.047854, 0.047854",\ + "0.098249, 0.098249, 0.098249, 0.098249, 0.098249",\ + "0.188801, 0.188801, 0.188801, 0.188801, 0.188801",\ + "0.444112, 0.444112, 0.444112, 0.444112, 0.444112",\ + "1.101794, 1.101794, 1.101794, 1.101794, 1.101794"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[9]_redg_2453*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[62]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011"); + values ( "0.405081, 0.661604, 0.918671, 1.360881, 2.245302",\ + "0.455961, 0.712483, 0.969534, 1.411694, 2.296014",\ + "0.533364, 0.789887, 1.046932, 1.489066, 2.373335",\ + "0.741794, 0.998316, 1.255349, 1.697444, 2.581634",\ + "1.295078, 1.551601, 1.808624, 2.250684, 3.134805",\ + "0.493291, 0.749080, 1.006153, 1.447596, 2.331236",\ + "0.544172, 0.799959, 1.057016, 1.498409, 2.381948",\ + "0.621574, 0.877363, 1.134413, 1.575781, 2.459269",\ + "0.830004, 1.085792, 1.342831, 1.784158, 2.667568",\ + "1.383288, 1.639076, 1.896105, 2.337399, 3.220738",\ + "0.581963, 0.837893, 1.094115, 1.535218, 2.418191",\ + "0.632844, 0.888772, 1.144979, 1.586031, 2.468903",\ + "0.710247, 0.966176, 1.222376, 1.663403, 2.546224",\ + "0.918676, 1.174605, 1.430793, 1.871780, 2.754523",\ + "1.471960, 1.727890, 1.984068, 2.425020, 3.307693",\ + "0.644923, 0.903284, 1.158251, 1.599131, 2.481700",\ + "0.695804, 0.954163, 1.209114, 1.649944, 2.532412",\ + "0.773206, 1.031567, 1.286511, 1.727316, 2.609733",\ + "0.981636, 1.239996, 1.494928, 1.935694, 2.818032",\ + "1.534920, 1.793280, 2.048203, 2.488934, 3.371202",\ + "0.976976, 1.264814, 1.509846, 1.948367, 2.827156",\ + "1.027857, 1.315693, 1.560709, 1.999180, 2.877868",\ + "1.105260, 1.393097, 1.638106, 2.076551, 2.955189",\ + "1.313689, 1.601526, 1.846523, 2.284929, 3.163488",\ + "1.866973, 2.154810, 2.399797, 2.838169, 3.716659"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011"); + values ( "0.235856, 0.236036, 0.236876, 0.239059, 0.243424",\ + "0.297458, 0.297578, 0.298135, 0.299584, 0.302483",\ + "0.424282, 0.424361, 0.424727, 0.425678, 0.427582",\ + "0.882507, 0.882519, 0.882580, 0.882733, 0.883038",\ + "2.159515, 2.159525, 2.159563, 2.159647, 2.159816",\ + "0.235857, 0.236037, 0.236883, 0.239059, 0.243424",\ + "0.297459, 0.297578, 0.298140, 0.299584, 0.302483",\ + "0.424283, 0.424361, 0.424730, 0.425678, 0.427582",\ + "0.882507, 0.882519, 0.882580, 0.882733, 0.883038",\ + "2.159515, 2.159525, 2.159563, 2.159647, 2.159816",\ + "0.235860, 0.236040, 0.236883, 0.239059, 0.243424",\ + "0.297461, 0.297581, 0.298140, 0.299584, 0.302483",\ + "0.424284, 0.424363, 0.424730, 0.425678, 0.427582",\ + "0.882507, 0.882519, 0.882580, 0.882733, 0.883038",\ + "2.159515, 2.159525, 2.159563, 2.159647, 2.159816",\ + "0.235863, 0.236045, 0.236883, 0.239059, 0.243424",\ + "0.297463, 0.297583, 0.298140, 0.299584, 0.302483",\ + "0.424285, 0.424365, 0.424730, 0.425678, 0.427582",\ + "0.882507, 0.882519, 0.882580, 0.882733, 0.883038",\ + "2.159515, 2.159525, 2.159563, 2.159647, 2.159816",\ + "0.235880, 0.236097, 0.236905, 0.239068, 0.243424",\ + "0.297474, 0.297618, 0.298155, 0.299590, 0.302483",\ + "0.424293, 0.424387, 0.424740, 0.425682, 0.427582",\ + "0.882507, 0.882524, 0.882582, 0.882733, 0.883038",\ + "2.159515, 2.159528, 2.159564, 2.159647, 2.159816"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011"); + values ( "0.367521, 0.579425, 0.836465, 1.278595, 2.162855",\ + "0.401633, 0.614821, 0.871879, 1.314094, 2.198523",\ + "0.451390, 0.668626, 0.925663, 1.367835, 2.252179",\ + "0.579943, 0.801765, 1.058753, 1.500789, 2.384860",\ + "0.915527, 1.146173, 1.403096, 1.844941, 2.728633",\ + "0.454931, 0.666901, 0.923947, 1.365310, 2.248789",\ + "0.489043, 0.702297, 0.959362, 1.400808, 2.284457",\ + "0.538801, 0.756101, 1.013145, 1.454550, 2.338113",\ + "0.667354, 0.889241, 1.146235, 1.587503, 2.470794",\ + "1.002937, 1.233649, 1.490577, 1.931656, 2.814567",\ + "0.535766, 0.755714, 1.011909, 1.452931, 2.335744",\ + "0.569878, 0.791110, 1.047324, 1.488430, 2.371412",\ + "0.619635, 0.844914, 1.101107, 1.542171, 2.425068",\ + "0.748188, 0.978053, 1.234197, 1.675125, 2.557749",\ + "1.083772, 1.322461, 1.578539, 2.019278, 2.901522",\ + "0.593373, 0.821105, 1.076045, 1.516845, 2.399253",\ + "0.627485, 0.856501, 1.111459, 1.552344, 2.434921",\ + "0.677243, 0.910304, 1.165242, 1.606085, 2.488577",\ + "0.805795, 1.043444, 1.298333, 1.739039, 2.621258",\ + "1.141379, 1.387851, 1.642674, 2.083191, 2.965031",\ + "0.895433, 1.182634, 1.427639, 1.866081, 2.744709",\ + "0.930201, 1.218028, 1.463055, 1.901580, 2.780377",\ + "0.984012, 1.271830, 1.516838, 1.955320, 2.834033",\ + "1.117159, 1.404967, 1.649927, 2.088274, 2.966714",\ + "1.461575, 1.749372, 1.994267, 2.432426, 3.310487"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011"); + values ( "0.080902, 0.080967, 0.081775, 0.084238, 0.089162",\ + "0.117510, 0.117523, 0.117812, 0.118746, 0.120614",\ + "0.210641, 0.210651, 0.210781, 0.211182, 0.211986",\ + "0.448308, 0.448315, 0.448372, 0.448536, 0.448865",\ + "1.101372, 1.101392, 1.101478, 1.101676, 1.102071",\ + "0.080902, 0.080968, 0.081783, 0.084238, 0.089162",\ + "0.117510, 0.117523, 0.117815, 0.118746, 0.120614",\ + "0.210641, 0.210651, 0.210782, 0.211182, 0.211986",\ + "0.448308, 0.448315, 0.448373, 0.448536, 0.448865",\ + "1.101372, 1.101392, 1.101479, 1.101676, 1.102071",\ + "0.080902, 0.080970, 0.081783, 0.084238, 0.089162",\ + "0.117510, 0.117523, 0.117815, 0.118746, 0.120614",\ + "0.210641, 0.210651, 0.210782, 0.211182, 0.211986",\ + "0.448308, 0.448315, 0.448373, 0.448536, 0.448865",\ + "1.101372, 1.101393, 1.101479, 1.101676, 1.102071",\ + "0.080902, 0.080972, 0.081783, 0.084238, 0.089162",\ + "0.117510, 0.117524, 0.117815, 0.118746, 0.120614",\ + "0.210641, 0.210651, 0.210782, 0.211182, 0.211986",\ + "0.448308, 0.448315, 0.448373, 0.448536, 0.448865",\ + "1.101372, 1.101393, 1.101479, 1.101676, 1.102071",\ + "0.080902, 0.080995, 0.081808, 0.084248, 0.089162",\ + "0.117510, 0.117529, 0.117825, 0.118750, 0.120614",\ + "0.210641, 0.210655, 0.210786, 0.211184, 0.211986",\ + "0.448308, 0.448318, 0.448374, 0.448537, 0.448865",\ + "1.101372, 1.101400, 1.101481, 1.101677, 1.102071"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[9]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[1]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011"); + values ( "0.350120, 0.565633, 0.746735, 1.037548, 1.600373",\ + "0.398981, 0.614494, 0.795596, 1.086408, 1.649232",\ + "0.501090, 0.716603, 0.897704, 1.188518, 1.751342",\ + "0.737189, 0.952702, 1.133804, 1.424618, 1.987443",\ + "1.308796, 1.524309, 1.705411, 1.996226, 2.559053",\ + "0.438515, 0.652951, 0.834015, 1.124853, 1.687726",\ + "0.487376, 0.701812, 0.882876, 1.173713, 1.736585",\ + "0.589485, 0.803921, 0.984985, 1.275823, 1.838695",\ + "0.825584, 1.040021, 1.221085, 1.511923, 2.074796",\ + "1.397191, 1.611628, 1.792692, 2.083531, 2.646406",\ + "0.527399, 0.733288, 0.914042, 1.204882, 1.767758",\ + "0.576260, 0.782149, 0.962903, 1.253742, 1.816617",\ + "0.678369, 0.884258, 1.065012, 1.355851, 1.918727",\ + "0.914468, 1.120357, 1.301112, 1.591951, 2.154828",\ + "1.486075, 1.691964, 1.872719, 2.163559, 2.726438",\ + "0.590410, 0.791118, 0.971742, 1.262314, 1.824777",\ + "0.639271, 0.839979, 1.020603, 1.311174, 1.873636",\ + "0.741380, 0.942088, 1.122712, 1.413283, 1.975746",\ + "0.977479, 1.178187, 1.358811, 1.649383, 2.211848",\ + "1.549087, 1.749794, 1.930419, 2.220991, 2.783457",\ + "0.913253, 1.096448, 1.275400, 1.565488, 2.127003",\ + "0.962113, 1.145308, 1.324261, 1.614348, 2.175863",\ + "1.064222, 1.247418, 1.426370, 1.716458, 2.277973",\ + "1.300322, 1.483517, 1.662469, 1.952558, 2.514074",\ + "1.871929, 2.055124, 2.234077, 2.524166, 3.085683"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011"); + values ( "0.032791, 0.032791, 0.032792, 0.032797, 0.032808",\ + "0.150563, 0.150563, 0.150562, 0.150560, 0.150555",\ + "0.376248, 0.376248, 0.376248, 0.376247, 0.376244",\ + "0.869894, 0.869894, 0.869894, 0.869892, 0.869888",\ + "2.137202, 2.137202, 2.137202, 2.137203, 2.137204",\ + "0.032791, 0.032791, 0.032792, 0.032797, 0.032808",\ + "0.150563, 0.150563, 0.150562, 0.150560, 0.150555",\ + "0.376248, 0.376248, 0.376248, 0.376247, 0.376244",\ + "0.869894, 0.869894, 0.869894, 0.869892, 0.869888",\ + "2.137202, 2.137202, 2.137202, 2.137203, 2.137204",\ + "0.032791, 0.032791, 0.032792, 0.032797, 0.032808",\ + "0.150563, 0.150563, 0.150562, 0.150560, 0.150555",\ + "0.376248, 0.376248, 0.376248, 0.376247, 0.376244",\ + "0.869894, 0.869894, 0.869894, 0.869892, 0.869888",\ + "2.137202, 2.137202, 2.137202, 2.137203, 2.137204",\ + "0.032791, 0.032791, 0.032792, 0.032797, 0.032808",\ + "0.150563, 0.150563, 0.150562, 0.150560, 0.150555",\ + "0.376248, 0.376248, 0.376248, 0.376247, 0.376244",\ + "0.869894, 0.869894, 0.869894, 0.869892, 0.869888",\ + "2.137202, 2.137202, 2.137202, 2.137203, 2.137204",\ + "0.032791, 0.032791, 0.032792, 0.032797, 0.032808",\ + "0.150563, 0.150563, 0.150562, 0.150560, 0.150555",\ + "0.376248, 0.376248, 0.376248, 0.376247, 0.376244",\ + "0.869894, 0.869894, 0.869894, 0.869892, 0.869888",\ + "2.137202, 2.137202, 2.137202, 2.137203, 2.137204"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011"); + values ( "0.373967, 0.592587, 0.771355, 1.061366, 1.624150",\ + "0.409637, 0.625150, 0.806253, 1.097068, 1.659896",\ + "0.450922, 0.666435, 0.847537, 1.138352, 1.701180",\ + "0.573066, 0.788579, 0.969681, 1.260496, 1.823323",\ + "0.905340, 1.120854, 1.301956, 1.592770, 2.155596",\ + "0.462362, 0.679906, 0.858636, 1.148671, 1.711503",\ + "0.498033, 0.712469, 0.893534, 1.184373, 1.747249",\ + "0.539317, 0.753753, 0.934818, 1.225657, 1.788534",\ + "0.661461, 0.875897, 1.056962, 1.347801, 1.910677",\ + "0.993736, 1.208172, 1.389236, 1.680075, 2.242949",\ + "0.551246, 0.760243, 0.938663, 1.228699, 1.791535",\ + "0.586916, 0.792806, 0.973560, 1.264401, 1.827281",\ + "0.628201, 0.834090, 1.014845, 1.305686, 1.868565",\ + "0.750345, 0.956234, 1.136989, 1.427829, 1.990708",\ + "1.082619, 1.288509, 1.469263, 1.760103, 2.322981",\ + "0.614257, 0.818060, 0.996357, 1.286131, 1.848554",\ + "0.649928, 0.850636, 1.031260, 1.321833, 1.884300",\ + "0.691212, 0.891920, 1.072545, 1.363118, 1.925585",\ + "0.813356, 1.014064, 1.194689, 1.485261, 2.047728",\ + "1.145631, 1.346339, 1.526963, 1.817535, 2.380001",\ + "0.943056, 1.123302, 1.300014, 1.589306, 2.150780",\ + "0.972770, 1.155965, 1.334918, 1.625008, 2.186526",\ + "1.014054, 1.197250, 1.376202, 1.666292, 2.227811",\ + "1.136198, 1.319394, 1.498346, 1.788436, 2.349954",\ + "1.468473, 1.651668, 1.830621, 2.120710, 2.682227"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011"); + values ( "0.047453, 0.047453, 0.047453, 0.047451, 0.047447",\ + "0.092188, 0.092188, 0.092188, 0.092188, 0.092187",\ + "0.186056, 0.186056, 0.186056, 0.186056, 0.186055",\ + "0.432423, 0.432423, 0.432423, 0.432422, 0.432422",\ + "1.065140, 1.065140, 1.065140, 1.065138, 1.065135",\ + "0.047453, 0.047453, 0.047453, 0.047451, 0.047447",\ + "0.092188, 0.092188, 0.092188, 0.092188, 0.092187",\ + "0.186056, 0.186056, 0.186056, 0.186056, 0.186055",\ + "0.432423, 0.432423, 0.432423, 0.432422, 0.432422",\ + "1.065140, 1.065140, 1.065140, 1.065138, 1.065135",\ + "0.047453, 0.047453, 0.047453, 0.047451, 0.047447",\ + "0.092188, 0.092188, 0.092188, 0.092188, 0.092187",\ + "0.186056, 0.186056, 0.186056, 0.186056, 0.186055",\ + "0.432423, 0.432423, 0.432423, 0.432422, 0.432422",\ + "1.065140, 1.065140, 1.065140, 1.065138, 1.065135",\ + "0.047453, 0.047453, 0.047453, 0.047451, 0.047447",\ + "0.092188, 0.092188, 0.092188, 0.092188, 0.092187",\ + "0.186056, 0.186056, 0.186056, 0.186056, 0.186055",\ + "0.432423, 0.432423, 0.432423, 0.432422, 0.432422",\ + "1.065140, 1.065140, 1.065140, 1.065138, 1.065135",\ + "0.047453, 0.047453, 0.047453, 0.047451, 0.047447",\ + "0.092188, 0.092188, 0.092188, 0.092188, 0.092187",\ + "0.186056, 0.186056, 0.186056, 0.186056, 0.186055",\ + "0.432423, 0.432423, 0.432423, 0.432422, 0.432422",\ + "1.065140, 1.065140, 1.065140, 1.065138, 1.065135"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[9]_redg_min_2531*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[57]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011"); + values ( "0.331760, 0.553188, 0.742512, 1.045826, 1.632024",\ + "0.380621, 0.602049, 0.791372, 1.094686, 1.680882",\ + "0.482730, 0.704158, 0.893481, 1.196795, 1.782993",\ + "0.718830, 0.940258, 1.129582, 1.432896, 2.019095",\ + "1.290437, 1.511866, 1.701190, 2.004506, 2.590707",\ + "0.420081, 0.640507, 0.829793, 1.133131, 1.719378",\ + "0.468942, 0.689367, 0.878653, 1.181991, 1.768235",\ + "0.571051, 0.791476, 0.980762, 1.284101, 1.870346",\ + "0.807150, 1.027576, 1.216862, 1.520201, 2.106449",\ + "1.378757, 1.599184, 1.788471, 2.091811, 2.678061",\ + "0.509110, 0.720840, 0.909820, 1.213160, 1.799409",\ + "0.557971, 0.769701, 0.958680, 1.262019, 1.848267",\ + "0.660080, 0.871810, 1.060789, 1.364129, 1.950378",\ + "0.896179, 1.107910, 1.296889, 1.600230, 2.186480",\ + "1.467786, 1.679518, 1.868498, 2.171839, 2.758092",\ + "0.572416, 0.778663, 0.967540, 1.270620, 1.856487",\ + "0.621277, 0.827523, 1.016400, 1.319480, 1.905344",\ + "0.723386, 0.929632, 1.118510, 1.421590, 2.007455",\ + "0.959485, 1.165732, 1.354610, 1.657691, 2.243557",\ + "1.531092, 1.737340, 1.926218, 2.229300, 2.815169",\ + "0.903758, 1.083926, 1.271200, 1.573819, 2.158782",\ + "0.952619, 1.132786, 1.320060, 1.622678, 2.207640",\ + "1.054728, 1.234896, 1.422170, 1.724788, 2.309751",\ + "1.290827, 1.470996, 1.658270, 1.960889, 2.545854",\ + "1.862434, 2.042603, 2.229878, 2.532498, 3.117465"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011"); + values ( "0.032790, 0.032796, 0.032799, 0.032806, 0.032822",\ + "0.150563, 0.150560, 0.150559, 0.150556, 0.150549",\ + "0.376248, 0.376247, 0.376246, 0.376245, 0.376241",\ + "0.869894, 0.869894, 0.869894, 0.869893, 0.869890",\ + "2.137202, 2.137202, 2.137202, 2.137202, 2.137204",\ + "0.032790, 0.032796, 0.032799, 0.032806, 0.032822",\ + "0.150563, 0.150560, 0.150559, 0.150556, 0.150549",\ + "0.376248, 0.376247, 0.376246, 0.376245, 0.376241",\ + "0.869894, 0.869894, 0.869894, 0.869893, 0.869890",\ + "2.137202, 2.137202, 2.137202, 2.137202, 2.137204",\ + "0.032791, 0.032796, 0.032799, 0.032806, 0.032822",\ + "0.150563, 0.150560, 0.150559, 0.150556, 0.150549",\ + "0.376248, 0.376247, 0.376246, 0.376245, 0.376241",\ + "0.869894, 0.869894, 0.869894, 0.869893, 0.869890",\ + "2.137202, 2.137202, 2.137202, 2.137202, 2.137204",\ + "0.032791, 0.032796, 0.032799, 0.032806, 0.032822",\ + "0.150562, 0.150560, 0.150559, 0.150556, 0.150549",\ + "0.376248, 0.376247, 0.376246, 0.376245, 0.376241",\ + "0.869894, 0.869894, 0.869894, 0.869893, 0.869890",\ + "2.137202, 2.137202, 2.137202, 2.137202, 2.137204",\ + "0.032791, 0.032796, 0.032799, 0.032807, 0.032822",\ + "0.150563, 0.150560, 0.150559, 0.150556, 0.150549",\ + "0.376248, 0.376247, 0.376246, 0.376245, 0.376241",\ + "0.869894, 0.869894, 0.869894, 0.869893, 0.869890",\ + "2.137202, 2.137202, 2.137202, 2.137202, 2.137204"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011"); + values ( "0.355611, 0.590269, 0.779821, 1.083137, 1.669339",\ + "0.391278, 0.612708, 0.802032, 1.105348, 1.691551",\ + "0.432562, 0.653992, 0.843316, 1.146633, 1.732836",\ + "0.554706, 0.776136, 0.965460, 1.268776, 1.854978",\ + "0.886981, 1.108410, 1.297734, 1.601049, 2.187249",\ + "0.443930, 0.677587, 0.867102, 1.170442, 1.756692",\ + "0.479599, 0.700026, 0.889313, 1.192653, 1.778904",\ + "0.520883, 0.741310, 0.930597, 1.233938, 1.820189",\ + "0.643027, 0.863454, 1.052741, 1.356081, 1.942332",\ + "0.975302, 1.195728, 1.385015, 1.688354, 2.274603",\ + "0.532956, 0.757921, 0.947129, 1.250471, 1.836724",\ + "0.568627, 0.780360, 0.969340, 1.272682, 1.858936",\ + "0.609912, 0.821644, 1.010624, 1.313967, 1.900221",\ + "0.732056, 0.943788, 1.132768, 1.436110, 2.022363",\ + "1.064331, 1.276062, 1.465042, 1.768383, 2.354635",\ + "0.596259, 0.815760, 1.004849, 1.307931, 1.893801",\ + "0.631934, 0.838182, 1.027060, 1.330143, 1.916013",\ + "0.673218, 0.879466, 1.068345, 1.371427, 1.957298",\ + "0.795362, 1.001610, 1.190488, 1.493571, 2.079441",\ + "1.127637, 1.333884, 1.522762, 1.825843, 2.411712",\ + "0.930491, 1.121142, 1.308509, 1.611130, 2.196097",\ + "0.963275, 1.143445, 1.330720, 1.633341, 2.218309",\ + "1.004560, 1.184730, 1.372005, 1.674626, 2.259594",\ + "1.126704, 1.306873, 1.494148, 1.796769, 2.381737",\ + "1.458978, 1.639148, 1.826422, 2.129042, 2.714008"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011"); + values ( "0.047454, 0.047451, 0.047450, 0.047447, 0.047442",\ + "0.092188, 0.092188, 0.092188, 0.092188, 0.092187",\ + "0.186056, 0.186056, 0.186056, 0.186055, 0.186055",\ + "0.432423, 0.432422, 0.432422, 0.432422, 0.432421",\ + "1.065141, 1.065139, 1.065138, 1.065135, 1.065130",\ + "0.047453, 0.047451, 0.047450, 0.047447, 0.047442",\ + "0.092188, 0.092188, 0.092188, 0.092188, 0.092187",\ + "0.186056, 0.186056, 0.186056, 0.186055, 0.186055",\ + "0.432423, 0.432422, 0.432422, 0.432422, 0.432421",\ + "1.065141, 1.065139, 1.065138, 1.065135, 1.065130",\ + "0.047453, 0.047451, 0.047450, 0.047447, 0.047442",\ + "0.092188, 0.092188, 0.092188, 0.092188, 0.092187",\ + "0.186056, 0.186056, 0.186056, 0.186055, 0.186055",\ + "0.432423, 0.432422, 0.432422, 0.432422, 0.432421",\ + "1.065140, 1.065139, 1.065138, 1.065135, 1.065130",\ + "0.047453, 0.047451, 0.047450, 0.047447, 0.047442",\ + "0.092188, 0.092188, 0.092188, 0.092188, 0.092187",\ + "0.186056, 0.186056, 0.186056, 0.186055, 0.186055",\ + "0.432423, 0.432422, 0.432422, 0.432422, 0.432421",\ + "1.065140, 1.065139, 1.065138, 1.065135, 1.065130",\ + "0.047452, 0.047451, 0.047450, 0.047447, 0.047442",\ + "0.092188, 0.092188, 0.092188, 0.092188, 0.092187",\ + "0.186056, 0.186056, 0.186056, 0.186055, 0.186055",\ + "0.432423, 0.432422, 0.432422, 0.432422, 0.432421",\ + "1.065140, 1.065139, 1.065138, 1.065135, 1.065130"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[9]_redg_min*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[58]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011"); + values ( "0.441216, 0.635561, 0.817859, 1.110553, 1.677168",\ + "0.490035, 0.684380, 0.866679, 1.159372, 1.725988",\ + "0.592166, 0.786511, 0.968809, 1.261503, 1.828118",\ + "0.828311, 1.022655, 1.204954, 1.497648, 2.064263",\ + "1.399982, 1.594326, 1.776625, 2.069319, 2.635934",\ + "0.529420, 0.722878, 0.905140, 1.197858, 1.764521",\ + "0.578240, 0.771698, 0.953960, 1.246678, 1.813341",\ + "0.680371, 0.873829, 1.056091, 1.348809, 1.915472",\ + "0.916515, 1.109973, 1.292235, 1.584953, 2.151616",\ + "1.488186, 1.681644, 1.863906, 2.156624, 2.723287",\ + "0.618747, 0.803206, 0.985167, 1.277887, 1.844553",\ + "0.667567, 0.852026, 1.033987, 1.326706, 1.893373",\ + "0.769697, 0.954157, 1.136117, 1.428837, 1.995504",\ + "1.005842, 1.190301, 1.372262, 1.664981, 2.231648",\ + "1.577513, 1.761972, 1.943933, 2.236652, 2.803319",\ + "0.681460, 0.861042, 1.042871, 1.335324, 1.901586",\ + "0.730280, 0.909862, 1.091691, 1.384144, 1.950405",\ + "0.832411, 1.011993, 1.193822, 1.486274, 2.052536",\ + "1.068555, 1.248137, 1.429966, 1.722419, 2.288681",\ + "1.640226, 1.819808, 2.001637, 2.294090, 2.860352",\ + "0.985102, 1.166382, 1.346527, 1.638502, 2.203828",\ + "1.033922, 1.215202, 1.395347, 1.687321, 2.252647",\ + "1.136052, 1.317332, 1.497478, 1.789452, 2.354778",\ + "1.372197, 1.553477, 1.733622, 2.025596, 2.590923",\ + "1.943868, 2.125148, 2.305293, 2.597268, 3.162594"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011"); + values ( "0.033216, 0.033216, 0.033216, 0.033216, 0.033216",\ + "0.150378, 0.150378, 0.150378, 0.150378, 0.150378",\ + "0.376160, 0.376160, 0.376160, 0.376160, 0.376160",\ + "0.870043, 0.870043, 0.870043, 0.870043, 0.870043",\ + "2.137131, 2.137131, 2.137131, 2.137131, 2.137131",\ + "0.033216, 0.033216, 0.033216, 0.033216, 0.033216",\ + "0.150378, 0.150378, 0.150378, 0.150378, 0.150378",\ + "0.376160, 0.376160, 0.376160, 0.376160, 0.376160",\ + "0.870043, 0.870043, 0.870043, 0.870043, 0.870043",\ + "2.137131, 2.137131, 2.137131, 2.137131, 2.137131",\ + "0.033216, 0.033216, 0.033216, 0.033216, 0.033216",\ + "0.150378, 0.150378, 0.150378, 0.150378, 0.150378",\ + "0.376160, 0.376160, 0.376160, 0.376160, 0.376160",\ + "0.870043, 0.870043, 0.870043, 0.870043, 0.870043",\ + "2.137131, 2.137131, 2.137131, 2.137131, 2.137131",\ + "0.033216, 0.033216, 0.033216, 0.033216, 0.033216",\ + "0.150378, 0.150378, 0.150378, 0.150378, 0.150378",\ + "0.376160, 0.376160, 0.376160, 0.376160, 0.376160",\ + "0.870043, 0.870043, 0.870043, 0.870043, 0.870043",\ + "2.137131, 2.137131, 2.137131, 2.137131, 2.137131",\ + "0.033216, 0.033216, 0.033216, 0.033216, 0.033216",\ + "0.150378, 0.150378, 0.150378, 0.150378, 0.150378",\ + "0.376160, 0.376160, 0.376160, 0.376160, 0.376160",\ + "0.870043, 0.870043, 0.870043, 0.870043, 0.870043",\ + "2.137131, 2.137131, 2.137131, 2.137131, 2.137131"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011"); + values ( "0.478632, 0.663448, 0.845746, 1.138440, 1.705055",\ + "0.500859, 0.695203, 0.877502, 1.170196, 1.736811",\ + "0.542150, 0.736495, 0.918793, 1.211487, 1.778102",\ + "0.664276, 0.858621, 1.040919, 1.333613, 1.900228",\ + "0.996499, 1.190843, 1.373142, 1.665835, 2.232451",\ + "0.566836, 0.750765, 0.933027, 1.225745, 1.792408",\ + "0.589063, 0.782521, 0.964783, 1.257501, 1.824164",\ + "0.630354, 0.823812, 1.006074, 1.298792, 1.865455",\ + "0.752480, 0.945938, 1.128200, 1.420918, 1.987581",\ + "1.084703, 1.278161, 1.460423, 1.753141, 2.319804",\ + "0.651614, 0.831093, 1.013054, 1.305773, 1.872440",\ + "0.678390, 0.862849, 1.044810, 1.337529, 1.904196",\ + "0.719681, 0.904140, 1.086101, 1.378820, 1.945487",\ + "0.841807, 1.026266, 1.208227, 1.500947, 2.067613",\ + "1.174030, 1.358489, 1.540450, 1.833169, 2.399836",\ + "0.709347, 0.888930, 1.070759, 1.363211, 1.929473",\ + "0.741103, 0.920685, 1.102514, 1.394967, 1.961228",\ + "0.782394, 0.961976, 1.143806, 1.436258, 2.002520",\ + "0.904520, 1.084103, 1.265932, 1.558384, 2.124646",\ + "1.236743, 1.416325, 1.598154, 1.890607, 2.456868",\ + "1.012989, 1.194269, 1.374414, 1.666389, 2.231715",\ + "1.044745, 1.226025, 1.406170, 1.698144, 2.263471",\ + "1.086036, 1.267316, 1.447461, 1.739436, 2.304762",\ + "1.208162, 1.389442, 1.569587, 1.861562, 2.426888",\ + "1.540385, 1.721665, 1.901810, 2.193784, 2.759110"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011"); + values ( "0.047293, 0.047293, 0.047293, 0.047293, 0.047293",\ + "0.092166, 0.092166, 0.092166, 0.092166, 0.092166",\ + "0.186036, 0.186036, 0.186036, 0.186036, 0.186036",\ + "0.432397, 0.432397, 0.432397, 0.432397, 0.432397",\ + "1.065004, 1.065004, 1.065004, 1.065004, 1.065004",\ + "0.047293, 0.047293, 0.047293, 0.047293, 0.047293",\ + "0.092166, 0.092166, 0.092166, 0.092166, 0.092166",\ + "0.186036, 0.186036, 0.186036, 0.186036, 0.186036",\ + "0.432397, 0.432397, 0.432397, 0.432397, 0.432397",\ + "1.065004, 1.065004, 1.065004, 1.065004, 1.065004",\ + "0.047293, 0.047293, 0.047293, 0.047293, 0.047293",\ + "0.092166, 0.092166, 0.092166, 0.092166, 0.092166",\ + "0.186036, 0.186036, 0.186036, 0.186036, 0.186036",\ + "0.432397, 0.432397, 0.432397, 0.432397, 0.432397",\ + "1.065004, 1.065004, 1.065004, 1.065004, 1.065004",\ + "0.047293, 0.047293, 0.047293, 0.047293, 0.047293",\ + "0.092166, 0.092166, 0.092166, 0.092166, 0.092166",\ + "0.186036, 0.186036, 0.186036, 0.186036, 0.186036",\ + "0.432397, 0.432397, 0.432397, 0.432397, 0.432397",\ + "1.065004, 1.065004, 1.065004, 1.065004, 1.065004",\ + "0.047293, 0.047293, 0.047293, 0.047293, 0.047293",\ + "0.092166, 0.092166, 0.092166, 0.092166, 0.092166",\ + "0.186036, 0.186036, 0.186036, 0.186036, 0.186036",\ + "0.432397, 0.432397, 0.432397, 0.432397, 0.432397",\ + "1.065004, 1.065004, 1.065004, 1.065004, 1.065004"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[9]_redg_min_2476*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[62]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011"); + values ( "0.348914, 0.525100, 0.702588, 0.991299, 1.552048",\ + "0.404496, 0.580679, 0.758142, 1.046740, 1.607235",\ + "0.479870, 0.656050, 0.833489, 1.121981, 1.682238",\ + "0.681478, 0.857653, 1.035056, 1.323386, 1.883276",\ + "1.225627, 1.401797, 1.579170, 1.867368, 2.426959",\ + "0.436324, 0.612419, 0.789869, 1.078604, 1.639402",\ + "0.491907, 0.667998, 0.845423, 1.134045, 1.694588",\ + "0.567281, 0.743368, 0.920770, 1.209286, 1.769591",\ + "0.768889, 0.944971, 1.122336, 1.410691, 1.970629",\ + "1.313037, 1.489116, 1.666451, 1.954674, 2.514312",\ + "0.517159, 0.692753, 0.869896, 1.158633, 1.719433",\ + "0.572742, 0.748332, 0.925450, 1.214074, 1.774620",\ + "0.648115, 0.823702, 1.000796, 1.289315, 1.849623",\ + "0.849723, 1.025305, 1.202363, 1.490720, 2.050661",\ + "1.393872, 1.569450, 1.746478, 2.034702, 2.594344",\ + "0.574766, 0.750569, 0.927588, 1.216063, 1.776449",\ + "0.630349, 0.806149, 0.983142, 1.271503, 1.831635",\ + "0.705722, 0.881519, 1.058488, 1.346744, 1.906637",\ + "0.907331, 1.083122, 1.260055, 1.548149, 2.107674",\ + "1.451479, 1.627266, 1.804170, 2.092131, 2.651357",\ + "0.876826, 1.055796, 1.231244, 1.519234, 2.078671",\ + "0.932408, 1.111374, 1.286798, 1.574675, 2.133856",\ + "1.007782, 1.186745, 1.362144, 1.649915, 2.208858",\ + "1.209389, 1.388348, 1.563711, 1.851319, 2.409893",\ + "1.753537, 1.932492, 2.107826, 2.395301, 2.953575"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011"); + values ( "0.151029, 0.151029, 0.151029, 0.151092, 0.151248",\ + "0.243808, 0.243808, 0.243808, 0.243837, 0.243906",\ + "0.409516, 0.409519, 0.409535, 0.409607, 0.409769",\ + "0.874760, 0.874761, 0.874769, 0.874803, 0.874880",\ + "2.138597, 2.138606, 2.138675, 2.138985, 2.139684",\ + "0.151029, 0.151029, 0.151029, 0.151092, 0.151248",\ + "0.243808, 0.243808, 0.243808, 0.243837, 0.243906",\ + "0.409516, 0.409519, 0.409535, 0.409607, 0.409769",\ + "0.874760, 0.874761, 0.874769, 0.874803, 0.874880",\ + "2.138597, 2.138606, 2.138675, 2.138985, 2.139684",\ + "0.151029, 0.151029, 0.151029, 0.151092, 0.151248",\ + "0.243808, 0.243808, 0.243808, 0.243837, 0.243906",\ + "0.409516, 0.409519, 0.409535, 0.409607, 0.409769",\ + "0.874760, 0.874761, 0.874769, 0.874803, 0.874880",\ + "2.138597, 2.138606, 2.138675, 2.138985, 2.139684",\ + "0.151029, 0.151029, 0.151029, 0.151092, 0.151248",\ + "0.243808, 0.243808, 0.243808, 0.243837, 0.243907",\ + "0.409516, 0.409519, 0.409535, 0.409607, 0.409769",\ + "0.874760, 0.874761, 0.874769, 0.874803, 0.874880",\ + "2.138597, 2.138606, 2.138675, 2.138986, 2.139686",\ + "0.151029, 0.151029, 0.151029, 0.151092, 0.151249",\ + "0.243808, 0.243808, 0.243808, 0.243837, 0.243907",\ + "0.409517, 0.409519, 0.409535, 0.409607, 0.409770",\ + "0.874760, 0.874761, 0.874769, 0.874803, 0.874881",\ + "2.138598, 2.138607, 2.138675, 2.138986, 2.139688"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011"); + values ( "0.322905, 0.543708, 0.721197, 1.009915, 1.570680",\ + "0.358307, 0.577820, 0.755311, 1.044036, 1.604817",\ + "0.412119, 0.627577, 0.805068, 1.093794, 1.654579",\ + "0.545267, 0.756130, 0.933618, 1.222334, 1.783093",\ + "0.889685, 1.091714, 1.269206, 1.557937, 2.118731",\ + "0.411116, 0.631026, 0.808478, 1.097220, 1.658034",\ + "0.446518, 0.665138, 0.842591, 1.131341, 1.692170",\ + "0.500329, 0.714895, 0.892349, 1.181100, 1.741932",\ + "0.633477, 0.843448, 1.020899, 1.309639, 1.870447",\ + "0.977895, 1.179032, 1.356487, 1.645242, 2.206084",\ + "0.499788, 0.711360, 0.888505, 1.177248, 1.738065",\ + "0.535189, 0.745472, 0.922618, 1.211369, 1.772202",\ + "0.589001, 0.795229, 0.972376, 1.261128, 1.821964",\ + "0.722149, 0.923782, 1.100926, 1.389667, 1.950478",\ + "1.066566, 1.259366, 1.436514, 1.725270, 2.286115",\ + "0.562748, 0.769177, 0.946197, 1.234678, 1.795081",\ + "0.598149, 0.803289, 0.980311, 1.268799, 1.829218",\ + "0.651961, 0.853046, 1.030068, 1.318558, 1.878979",\ + "0.785108, 0.981599, 1.158618, 1.447097, 2.007494",\ + "1.129526, 1.317183, 1.494206, 1.782700, 2.343131",\ + "0.894800, 1.074403, 1.249853, 1.537850, 2.097302",\ + "0.929545, 1.108515, 1.283966, 1.571971, 2.131439",\ + "0.979303, 1.158272, 1.333724, 1.621730, 2.181201",\ + "1.107856, 1.286825, 1.462274, 1.750269, 2.309716",\ + "1.443439, 1.622409, 1.797862, 2.085872, 2.645353"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011"); + values ( "0.073594, 0.073593, 0.073590, 0.073574, 0.073539",\ + "0.105770, 0.105770, 0.105771, 0.105778, 0.105792",\ + "0.191100, 0.191101, 0.191103, 0.191113, 0.191136",\ + "0.432555, 0.432553, 0.432541, 0.432487, 0.432365",\ + "1.065544, 1.065545, 1.065557, 1.065609, 1.065728",\ + "0.073594, 0.073593, 0.073590, 0.073574, 0.073539",\ + "0.105770, 0.105770, 0.105771, 0.105778, 0.105792",\ + "0.191100, 0.191101, 0.191103, 0.191113, 0.191136",\ + "0.432555, 0.432553, 0.432541, 0.432487, 0.432365",\ + "1.065544, 1.065545, 1.065557, 1.065609, 1.065728",\ + "0.073594, 0.073593, 0.073590, 0.073574, 0.073539",\ + "0.105770, 0.105770, 0.105771, 0.105778, 0.105792",\ + "0.191100, 0.191101, 0.191103, 0.191113, 0.191136",\ + "0.432554, 0.432553, 0.432541, 0.432487, 0.432365",\ + "1.065544, 1.065545, 1.065557, 1.065609, 1.065728",\ + "0.073594, 0.073593, 0.073590, 0.073574, 0.073539",\ + "0.105770, 0.105770, 0.105771, 0.105778, 0.105792",\ + "0.191100, 0.191101, 0.191103, 0.191113, 0.191136",\ + "0.432554, 0.432553, 0.432541, 0.432487, 0.432365",\ + "1.065544, 1.065545, 1.065557, 1.065610, 1.065728",\ + "0.073594, 0.073593, 0.073590, 0.073574, 0.073539",\ + "0.105770, 0.105770, 0.105771, 0.105778, 0.105792",\ + "0.191100, 0.191101, 0.191103, 0.191113, 0.191136",\ + "0.432554, 0.432553, 0.432541, 0.432487, 0.432365",\ + "1.065544, 1.065545, 1.065557, 1.065610, 1.065729"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[9]_redg_min_2427*/ + +} /* end of pin tl_o[9] */ + +pin("tl_o[8]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.154883 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : tl_o[8]; + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[17]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011"); + values ( "0.373916, 0.599728, 0.894574, 1.388503, 2.376363",\ + "0.415183, 0.640172, 0.934074, 1.428691, 2.417925",\ + "0.491066, 0.715879, 1.009866, 1.504530, 2.493859",\ + "0.745862, 0.970981, 1.264787, 1.759400, 2.748624",\ + "1.670986, 1.894752, 2.189083, 2.684630, 3.675724",\ + "0.461357, 0.687335, 0.982222, 1.475219, 2.462296",\ + "0.502624, 0.727773, 1.021724, 1.515406, 2.503859",\ + "0.578507, 0.803480, 1.097517, 1.591246, 2.579792",\ + "0.833304, 1.058581, 1.352438, 1.846115, 2.834558",\ + "1.758428, 1.982354, 2.276736, 2.771345, 3.761657",\ + "0.542237, 0.776480, 1.070189, 1.562842, 2.549252",\ + "0.583504, 0.816901, 1.109691, 1.603029, 2.590814",\ + "0.659387, 0.892609, 1.185483, 1.678869, 2.666748",\ + "0.914185, 1.147708, 1.440404, 1.933738, 2.921513",\ + "1.839308, 2.071485, 2.364703, 2.858968, 3.848613",\ + "0.599958, 0.842354, 1.134332, 1.626756, 2.612761",\ + "0.641225, 0.882751, 1.173835, 1.666943, 2.654323",\ + "0.717108, 0.958461, 1.249627, 1.742782, 2.730257",\ + "0.971907, 1.213556, 1.504548, 1.997652, 2.985022",\ + "1.897030, 2.137338, 2.428847, 2.922882, 3.912122",\ + "0.902648, 1.209455, 1.486456, 1.976211, 2.958217",\ + "0.943914, 1.249574, 1.525966, 2.016402, 2.999779",\ + "1.019797, 1.325301, 1.601758, 2.092241, 3.075712",\ + "1.274609, 1.580356, 1.856679, 2.347110, 3.330478",\ + "2.199727, 2.504201, 2.780987, 3.272345, 4.257577"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011"); + values ( "0.034807, 0.034870, 0.035021, 0.035342, 0.035983",\ + "0.083278, 0.083283, 0.083326, 0.083445, 0.083683",\ + "0.208556, 0.208575, 0.208609, 0.208619, 0.208640",\ + "0.692765, 0.692765, 0.692980, 0.693734, 0.695242",\ + "2.477403, 2.477403, 2.477403, 2.477403, 2.477403",\ + "0.034807, 0.034871, 0.035022, 0.035342, 0.035983",\ + "0.083278, 0.083283, 0.083327, 0.083445, 0.083683",\ + "0.208556, 0.208576, 0.208609, 0.208619, 0.208640",\ + "0.692765, 0.692765, 0.692982, 0.693734, 0.695242",\ + "2.477403, 2.477403, 2.477403, 2.477403, 2.477403",\ + "0.034807, 0.034872, 0.035022, 0.035342, 0.035983",\ + "0.083278, 0.083284, 0.083327, 0.083445, 0.083683",\ + "0.208556, 0.208576, 0.208609, 0.208619, 0.208640",\ + "0.692765, 0.692765, 0.692982, 0.693734, 0.695242",\ + "2.477403, 2.477403, 2.477403, 2.477403, 2.477403",\ + "0.034808, 0.034873, 0.035022, 0.035342, 0.035983",\ + "0.083278, 0.083284, 0.083327, 0.083445, 0.083683",\ + "0.208556, 0.208577, 0.208609, 0.208619, 0.208640",\ + "0.692765, 0.692765, 0.692982, 0.693734, 0.695242",\ + "2.477403, 2.477403, 2.477403, 2.477403, 2.477403",\ + "0.034810, 0.034887, 0.035026, 0.035343, 0.035983",\ + "0.083278, 0.083286, 0.083328, 0.083446, 0.083683",\ + "0.208556, 0.208584, 0.208609, 0.208619, 0.208640",\ + "0.692765, 0.692765, 0.692990, 0.693737, 0.695242",\ + "2.477403, 2.477403, 2.477403, 2.477403, 2.477403"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011"); + values ( "0.420490, 0.645190, 0.938944, 1.432430, 2.419402",\ + "0.461359, 0.686264, 0.979881, 1.473291, 2.460111",\ + "0.521542, 0.746363, 1.040033, 1.533430, 2.520226",\ + "0.690406, 0.915382, 1.209000, 1.702350, 2.689050",\ + "1.273072, 1.496794, 1.790318, 2.283708, 3.270487",\ + "0.507931, 0.732792, 1.026591, 1.519145, 2.505336",\ + "0.548801, 0.773865, 1.067528, 1.560006, 2.546045",\ + "0.608983, 0.833965, 1.127680, 1.620146, 2.606159",\ + "0.777848, 1.002983, 1.296647, 1.789066, 2.774984",\ + "1.360514, 1.584395, 1.877965, 2.370424, 3.356421",\ + "0.588811, 0.821923, 1.114557, 1.606768, 2.592291",\ + "0.629680, 0.862994, 1.155494, 1.647629, 2.633000",\ + "0.689863, 0.923095, 1.215646, 1.707769, 2.693114",\ + "0.858728, 1.092113, 1.384613, 1.876689, 2.861939",\ + "1.441395, 1.673523, 1.965932, 2.458046, 3.443376",\ + "0.646531, 0.887777, 1.178701, 1.670682, 2.655800",\ + "0.687400, 0.928846, 1.219638, 1.711543, 2.696509",\ + "0.747584, 0.988947, 1.279790, 1.771683, 2.756623",\ + "0.916448, 1.157964, 1.448757, 1.940602, 2.925448",\ + "1.499118, 1.739372, 2.030076, 2.521960, 3.506885",\ + "0.949211, 1.254642, 1.530820, 2.020136, 3.001256",\ + "0.990081, 1.295683, 1.571756, 2.060997, 3.041965",\ + "1.050271, 1.355798, 1.631908, 2.121136, 3.102079",\ + "1.219138, 1.524806, 1.800875, 2.290056, 3.270904",\ + "1.801826, 2.106188, 2.382194, 2.871414, 3.852341"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011"); + values ( "0.042658, 0.042646, 0.042619, 0.042581, 0.042505",\ + "0.078946, 0.078946, 0.078946, 0.078946, 0.078946",\ + "0.155293, 0.155293, 0.155279, 0.155230, 0.155132",\ + "0.431058, 0.431058, 0.431019, 0.430882, 0.430609",\ + "1.497229, 1.495745, 1.494360, 1.494360, 1.494360",\ + "0.042658, 0.042646, 0.042618, 0.042581, 0.042505",\ + "0.078946, 0.078946, 0.078946, 0.078946, 0.078946",\ + "0.155293, 0.155293, 0.155279, 0.155230, 0.155132",\ + "0.431058, 0.431058, 0.431018, 0.430882, 0.430609",\ + "1.497229, 1.495736, 1.494360, 1.494360, 1.494360",\ + "0.042658, 0.042646, 0.042618, 0.042581, 0.042505",\ + "0.078946, 0.078946, 0.078946, 0.078946, 0.078946",\ + "0.155293, 0.155293, 0.155279, 0.155230, 0.155132",\ + "0.431058, 0.431058, 0.431018, 0.430882, 0.430609",\ + "1.497225, 1.495716, 1.494360, 1.494360, 1.494360",\ + "0.042658, 0.042646, 0.042618, 0.042581, 0.042505",\ + "0.078946, 0.078946, 0.078946, 0.078946, 0.078946",\ + "0.155293, 0.155293, 0.155278, 0.155230, 0.155132",\ + "0.431058, 0.431058, 0.431018, 0.430882, 0.430609",\ + "1.497218, 1.495687, 1.494360, 1.494360, 1.494360",\ + "0.042658, 0.042642, 0.042618, 0.042580, 0.042505",\ + "0.078946, 0.078946, 0.078946, 0.078946, 0.078946",\ + "0.155293, 0.155293, 0.155278, 0.155230, 0.155132",\ + "0.431058, 0.431058, 0.431017, 0.430882, 0.430609",\ + "1.497153, 1.495349, 1.494360, 1.494360, 1.494360"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_2694*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[18]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.746021, 1.001665, 1.285647, 1.784442, 2.782033",\ + "0.780412, 1.036056, 1.320037, 1.818832, 2.816423",\ + "0.851654, 1.107299, 1.391280, 1.890076, 2.887667",\ + "1.105821, 1.361465, 1.645446, 2.144242, 3.141833",\ + "2.030393, 2.286036, 2.570016, 3.068810, 4.066399",\ + "0.833430, 1.089212, 1.373307, 1.871157, 2.867967",\ + "0.867821, 1.123603, 1.407697, 1.905547, 2.902357",\ + "0.939063, 1.194845, 1.478940, 1.976790, 2.973600",\ + "1.193229, 1.449012, 1.733106, 2.230957, 3.227767",\ + "2.117802, 2.373583, 2.657676, 3.155524, 4.152333",\ + "0.914308, 1.178178, 1.461272, 1.958778, 2.954922",\ + "0.948698, 1.212569, 1.495662, 1.993168, 2.989312",\ + "1.019941, 1.283811, 1.566905, 2.064412, 3.060555",\ + "1.274107, 1.537978, 1.821072, 2.318578, 3.314722",\ + "2.198680, 2.462549, 2.745641, 3.243146, 4.239288",\ + "0.974568, 1.243791, 1.525417, 2.022691, 3.018431",\ + "1.008959, 1.278181, 1.559807, 2.057082, 3.052821",\ + "1.080201, 1.349424, 1.631050, 2.128325, 3.124064",\ + "1.334368, 1.603591, 1.885216, 2.382491, 3.378231",\ + "2.258940, 2.528162, 2.809785, 3.307059, 4.302797",\ + "1.309682, 1.607944, 1.877586, 2.372160, 3.363887",\ + "1.344072, 1.642334, 1.911976, 2.406550, 3.398277",\ + "1.415315, 1.713577, 1.983219, 2.477793, 3.469521",\ + "1.669481, 1.967744, 2.237385, 2.731960, 3.723687",\ + "2.594053, 2.892314, 3.161954, 3.656528, 4.648253"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.034112, 0.034112, 0.034112, 0.034112, 0.034113",\ + "0.083750, 0.083750, 0.083750, 0.083750, 0.083751",\ + "0.208404, 0.208404, 0.208405, 0.208405, 0.208405",\ + "0.692758, 0.692758, 0.692759, 0.692761, 0.692766",\ + "2.464359, 2.464359, 2.464359, 2.464359, 2.464359",\ + "0.034112, 0.034112, 0.034112, 0.034112, 0.034113",\ + "0.083750, 0.083750, 0.083750, 0.083750, 0.083751",\ + "0.208404, 0.208404, 0.208405, 0.208405, 0.208405",\ + "0.692758, 0.692758, 0.692759, 0.692761, 0.692766",\ + "2.464359, 2.464359, 2.464359, 2.464359, 2.464359",\ + "0.034112, 0.034112, 0.034112, 0.034112, 0.034113",\ + "0.083750, 0.083750, 0.083750, 0.083750, 0.083751",\ + "0.208404, 0.208404, 0.208405, 0.208405, 0.208405",\ + "0.692758, 0.692758, 0.692759, 0.692761, 0.692766",\ + "2.464359, 2.464359, 2.464359, 2.464359, 2.464359",\ + "0.034112, 0.034112, 0.034112, 0.034112, 0.034113",\ + "0.083750, 0.083750, 0.083750, 0.083750, 0.083751",\ + "0.208404, 0.208404, 0.208405, 0.208405, 0.208405",\ + "0.692758, 0.692758, 0.692759, 0.692761, 0.692766",\ + "2.464359, 2.464359, 2.464359, 2.464359, 2.464359",\ + "0.034112, 0.034112, 0.034112, 0.034112, 0.034113",\ + "0.083750, 0.083750, 0.083750, 0.083750, 0.083751",\ + "0.208404, 0.208404, 0.208405, 0.208405, 0.208405",\ + "0.692758, 0.692758, 0.692759, 0.692761, 0.692766",\ + "2.464359, 2.464359, 2.464359, 2.464359, 2.464359"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.777783, 1.033425, 1.317405, 1.816199, 2.813788",\ + "0.819535, 1.075178, 1.359157, 1.857951, 2.855540",\ + "0.879465, 1.135108, 1.419087, 1.917882, 2.915471",\ + "1.047583, 1.303225, 1.587205, 2.085999, 3.083588",\ + "1.629496, 1.885133, 2.169106, 2.667897, 3.665479",\ + "0.865191, 1.120972, 1.405064, 1.902913, 2.899722",\ + "0.906944, 1.162724, 1.446817, 1.944666, 2.941474",\ + "0.966874, 1.222655, 1.506747, 2.004596, 3.001405",\ + "1.134991, 1.390772, 1.674865, 2.172714, 3.169522",\ + "1.716905, 1.972680, 2.256766, 2.754611, 3.751413",\ + "0.946069, 1.209938, 1.493030, 1.990535, 2.986677",\ + "0.987822, 1.251690, 1.534782, 2.032288, 3.028429",\ + "1.047752, 1.311621, 1.594713, 2.092218, 3.088360",\ + "1.215869, 1.479738, 1.762830, 2.260335, 3.256477",\ + "1.797783, 2.061646, 2.344732, 2.842233, 3.838368",\ + "1.006330, 1.275551, 1.557174, 2.054448, 3.050186",\ + "1.048082, 1.317303, 1.598927, 2.096201, 3.091938",\ + "1.108012, 1.377234, 1.658857, 2.156131, 3.151869",\ + "1.276130, 1.545351, 1.826975, 2.324248, 3.319986",\ + "1.858043, 2.127259, 2.408876, 2.906147, 3.901877",\ + "1.341443, 1.639703, 1.909343, 2.403917, 3.395642",\ + "1.383195, 1.681456, 1.951096, 2.445669, 3.437394",\ + "1.443126, 1.741386, 2.011026, 2.505599, 3.497324",\ + "1.611243, 1.909503, 2.179143, 2.673717, 3.665442",\ + "2.193155, 2.491410, 2.761045, 3.255615, 4.247333"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.045877, 0.045877, 0.045878, 0.045878, 0.045878",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494119, 1.494119, 1.494119, 1.494119, 1.494120",\ + "0.045877, 0.045877, 0.045878, 0.045878, 0.045878",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494119, 1.494119, 1.494119, 1.494119, 1.494120",\ + "0.045877, 0.045877, 0.045878, 0.045878, 0.045878",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494119, 1.494119, 1.494119, 1.494119, 1.494120",\ + "0.045877, 0.045877, 0.045878, 0.045878, 0.045878",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494119, 1.494119, 1.494119, 1.494119, 1.494120",\ + "0.045877, 0.045877, 0.045878, 0.045878, 0.045878",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494119, 1.494119, 1.494119, 1.494119, 1.494120"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_2719*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[23]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011"); + values ( "0.329434, 0.567970, 0.849310, 1.349062, 2.348564",\ + "0.370729, 0.609110, 0.889780, 1.387186, 2.381998",\ + "0.446657, 0.684926, 0.965184, 1.461121, 2.452996",\ + "0.702252, 0.940104, 1.219789, 1.715647, 2.707363",\ + "1.626635, 1.863892, 2.145200, 2.640602, 3.631406",\ + "0.416843, 0.655497, 0.936973, 1.435776, 2.434498",\ + "0.458138, 0.696638, 0.977436, 1.473900, 2.467931",\ + "0.534066, 0.772454, 1.052835, 1.547836, 2.538929",\ + "0.789661, 1.027628, 1.307440, 1.802361, 2.793297",\ + "1.714044, 1.951428, 2.232849, 2.727316, 3.717340",\ + "0.497703, 0.744421, 1.024939, 1.523398, 2.521453",\ + "0.538998, 0.785561, 1.065401, 1.561522, 2.554886",\ + "0.614927, 0.861378, 1.140800, 1.635457, 2.625884",\ + "0.870521, 1.116544, 1.395405, 1.889983, 2.880252",\ + "1.794904, 2.040369, 2.320814, 2.814938, 3.804295",\ + "0.555377, 0.809972, 1.089084, 1.587311, 2.584962",\ + "0.596671, 0.851113, 1.129546, 1.625435, 2.618395",\ + "0.672599, 0.926930, 1.204945, 1.699371, 2.689393",\ + "0.928193, 1.182084, 1.459549, 1.953896, 2.943761",\ + "1.852575, 2.105947, 2.384958, 2.878851, 3.867804",\ + "0.876916, 1.173402, 1.441262, 1.936784, 2.930418",\ + "0.918063, 1.214545, 1.481701, 1.974898, 2.963851",\ + "0.993829, 1.290365, 1.557085, 2.048828, 3.034849",\ + "1.249296, 1.545383, 1.811688, 2.303353, 3.289217",\ + "2.172819, 2.469679, 2.737093, 3.228306, 4.213260"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011"); + values ( "0.035016, 0.035016, 0.035955, 0.039196, 0.045676",\ + "0.083549, 0.083549, 0.083885, 0.085044, 0.087361",\ + "0.208718, 0.208718, 0.208874, 0.209415, 0.210496",\ + "0.692609, 0.692819, 0.692927, 0.693072, 0.693361",\ + "2.477031, 2.477031, 2.477148, 2.477552, 2.478359",\ + "0.035016, 0.035016, 0.035965, 0.039196, 0.045676",\ + "0.083549, 0.083549, 0.083888, 0.085044, 0.087361",\ + "0.208718, 0.208718, 0.208876, 0.209415, 0.210496",\ + "0.692609, 0.692820, 0.692927, 0.693072, 0.693361",\ + "2.477031, 2.477031, 2.477149, 2.477552, 2.478359",\ + "0.035016, 0.035016, 0.035966, 0.039196, 0.045676",\ + "0.083549, 0.083549, 0.083888, 0.085044, 0.087361",\ + "0.208718, 0.208718, 0.208876, 0.209415, 0.210496",\ + "0.692610, 0.692821, 0.692927, 0.693072, 0.693361",\ + "2.477031, 2.477031, 2.477149, 2.477552, 2.478359",\ + "0.035016, 0.035016, 0.035966, 0.039196, 0.045676",\ + "0.083549, 0.083549, 0.083889, 0.085044, 0.087361",\ + "0.208718, 0.208718, 0.208876, 0.209415, 0.210496",\ + "0.692612, 0.692822, 0.692927, 0.693072, 0.693361",\ + "2.477031, 2.477031, 2.477149, 2.477552, 2.478359",\ + "0.035016, 0.035016, 0.035999, 0.039209, 0.045676",\ + "0.083549, 0.083549, 0.083900, 0.085048, 0.087361",\ + "0.208718, 0.208718, 0.208882, 0.209417, 0.210496",\ + "0.692711, 0.692838, 0.692929, 0.693072, 0.693361",\ + "2.477031, 2.477031, 2.477154, 2.477553, 2.478359"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011"); + values ( "0.376302, 0.614890, 0.892196, 1.378119, 2.349964",\ + "0.417201, 0.655792, 0.932845, 1.417492, 2.386786",\ + "0.477347, 0.716035, 0.992408, 1.474614, 2.439025",\ + "0.646325, 0.884988, 1.160689, 1.640497, 2.600112",\ + "1.229570, 1.466407, 1.742451, 2.222424, 3.182369",\ + "0.463711, 0.702417, 0.979816, 1.464833, 2.435898",\ + "0.504610, 0.743320, 1.020461, 1.504206, 2.472719",\ + "0.564756, 0.803563, 1.080016, 1.561328, 2.524959",\ + "0.733734, 0.972517, 1.248289, 1.727211, 2.686046",\ + "1.316979, 1.553937, 1.830052, 2.309139, 3.268303",\ + "0.544574, 0.791340, 1.067780, 1.552455, 2.522853",\ + "0.585473, 0.832245, 1.108425, 1.591828, 2.559674",\ + "0.645618, 0.892489, 1.167980, 1.648950, 2.611914",\ + "0.814594, 1.061442, 1.336253, 1.814833, 2.773001",\ + "1.397827, 1.642867, 1.918017, 2.396760, 3.355258",\ + "0.602253, 0.856891, 1.131923, 1.616368, 2.586362",\ + "0.643149, 0.897798, 1.172568, 1.655741, 2.623183",\ + "0.703295, 0.958043, 1.232122, 1.712863, 2.675423",\ + "0.872267, 1.126997, 1.400395, 1.878746, 2.836510",\ + "1.455475, 1.708427, 1.982158, 2.460673, 3.418767",\ + "0.923807, 1.220314, 1.483961, 1.965784, 2.931818",\ + "0.964736, 1.261250, 1.524593, 2.005152, 2.968639",\ + "1.024895, 1.321501, 1.584123, 2.062263, 3.020879",\ + "1.193870, 1.490460, 1.752371, 2.228136, 3.181966",\ + "1.775178, 2.071965, 2.334136, 2.810064, 3.764223"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011"); + values ( "0.042685, 0.042788, 0.042938, 0.042938, 0.042938",\ + "0.078477, 0.079298, 0.079365, 0.079365, 0.079365",\ + "0.155270, 0.155314, 0.155322, 0.155322, 0.155322",\ + "0.431182, 0.431182, 0.431182, 0.431182, 0.431182",\ + "1.494069, 1.494069, 1.494069, 1.494069, 1.494069",\ + "0.042685, 0.042789, 0.042938, 0.042938, 0.042938",\ + "0.078477, 0.079299, 0.079365, 0.079365, 0.079365",\ + "0.155270, 0.155314, 0.155322, 0.155322, 0.155322",\ + "0.431182, 0.431182, 0.431182, 0.431182, 0.431182",\ + "1.494069, 1.494069, 1.494069, 1.494069, 1.494069",\ + "0.042685, 0.042791, 0.042938, 0.042938, 0.042938",\ + "0.078482, 0.079299, 0.079365, 0.079365, 0.079365",\ + "0.155270, 0.155314, 0.155322, 0.155322, 0.155322",\ + "0.431182, 0.431182, 0.431182, 0.431182, 0.431182",\ + "1.494069, 1.494069, 1.494069, 1.494069, 1.494069",\ + "0.042685, 0.042794, 0.042938, 0.042938, 0.042938",\ + "0.078491, 0.079301, 0.079365, 0.079365, 0.079365",\ + "0.155271, 0.155315, 0.155322, 0.155322, 0.155322",\ + "0.431182, 0.431182, 0.431182, 0.431182, 0.431182",\ + "1.494069, 1.494069, 1.494069, 1.494069, 1.494069",\ + "0.042685, 0.042831, 0.042938, 0.042938, 0.042938",\ + "0.078956, 0.079318, 0.079365, 0.079365, 0.079365",\ + "0.155294, 0.155316, 0.155322, 0.155322, 0.155322",\ + "0.431182, 0.431182, 0.431182, 0.431182, 0.431182",\ + "1.494069, 1.494069, 1.494069, 1.494069, 1.494069"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[8]_redg*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[24]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011"); + values ( "0.731951, 0.980905, 1.256242, 1.719746, 2.646754",\ + "0.766341, 1.015295, 1.290632, 1.754136, 2.681144",\ + "0.837584, 1.086538, 1.361876, 1.825380, 2.752387",\ + "1.091750, 1.340704, 1.616042, 2.079546, 3.006554",\ + "2.016322, 2.265275, 2.540610, 3.004114, 3.931121",\ + "0.819353, 1.068475, 1.343788, 1.806459, 2.732687",\ + "0.853744, 1.102866, 1.378179, 1.840850, 2.767077",\ + "0.924986, 1.174109, 1.449422, 1.912093, 2.838321",\ + "1.179153, 1.428275, 1.703588, 2.166259, 3.092487",\ + "2.103725, 2.352845, 2.628156, 3.090827, 4.017055",\ + "0.900166, 1.157465, 1.431751, 1.894080, 2.819643",\ + "0.934556, 1.191856, 1.466141, 1.928470, 2.854033",\ + "1.005799, 1.263098, 1.537384, 1.999714, 2.925276",\ + "1.259965, 1.517265, 1.791550, 2.253880, 3.179442",\ + "2.184537, 2.441835, 2.716118, 3.178448, 4.104010",\ + "0.957806, 1.223112, 1.495889, 1.957993, 2.883152",\ + "0.992196, 1.257502, 1.530279, 1.992383, 2.917542",\ + "1.063439, 1.328745, 1.601523, 2.063626, 2.988785",\ + "1.317605, 1.582911, 1.855689, 2.317793, 3.242951",\ + "2.242177, 2.507481, 2.780257, 3.242361, 4.167519",\ + "1.292888, 1.587742, 1.847697, 2.307310, 3.228608",\ + "1.327278, 1.622132, 1.882087, 2.341700, 3.262998",\ + "1.398521, 1.693375, 1.953330, 2.412943, 3.334241",\ + "1.652687, 1.947541, 2.207496, 2.667110, 3.588408",\ + "2.577259, 2.872111, 3.132065, 3.591678, 4.512975"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011"); + values ( "0.034112, 0.034112, 0.034112, 0.034112, 0.034112",\ + "0.083750, 0.083750, 0.083750, 0.083750, 0.083751",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692758, 0.692758, 0.692759, 0.692760, 0.692764",\ + "2.464354, 2.464354, 2.464354, 2.464354, 2.464354",\ + "0.034112, 0.034112, 0.034112, 0.034112, 0.034112",\ + "0.083750, 0.083750, 0.083750, 0.083750, 0.083751",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692758, 0.692758, 0.692759, 0.692760, 0.692764",\ + "2.464354, 2.464354, 2.464354, 2.464354, 2.464354",\ + "0.034112, 0.034112, 0.034112, 0.034112, 0.034112",\ + "0.083750, 0.083750, 0.083750, 0.083750, 0.083751",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692758, 0.692758, 0.692759, 0.692760, 0.692764",\ + "2.464354, 2.464354, 2.464354, 2.464354, 2.464354",\ + "0.034112, 0.034112, 0.034112, 0.034112, 0.034112",\ + "0.083750, 0.083750, 0.083750, 0.083750, 0.083751",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692758, 0.692758, 0.692759, 0.692760, 0.692764",\ + "2.464354, 2.464354, 2.464354, 2.464354, 2.464354",\ + "0.034112, 0.034112, 0.034112, 0.034112, 0.034112",\ + "0.083750, 0.083750, 0.083750, 0.083750, 0.083751",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692758, 0.692758, 0.692759, 0.692760, 0.692764",\ + "2.464354, 2.464354, 2.464354, 2.464354, 2.464354"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011"); + values ( "0.763712, 1.012664, 1.287999, 1.751503, 2.678509",\ + "0.805464, 1.054416, 1.329752, 1.793255, 2.720262",\ + "0.865395, 1.114347, 1.389682, 1.853185, 2.780192",\ + "1.033512, 1.282464, 1.557799, 2.021303, 2.948309",\ + "1.615425, 1.864370, 2.139697, 2.603199, 3.530203",\ + "0.851115, 1.100234, 1.375545, 1.838216, 2.764443",\ + "0.892867, 1.141987, 1.417298, 1.879968, 2.806196",\ + "0.952797, 1.201917, 1.477228, 1.939899, 2.866126",\ + "1.120914, 1.370034, 1.645345, 2.108016, 3.034243",\ + "1.702827, 1.951940, 2.227243, 2.689913, 3.616137",\ + "0.931927, 1.189224, 1.463507, 1.925837, 2.851398",\ + "0.973680, 1.230977, 1.505260, 1.967589, 2.893151",\ + "1.033610, 1.290907, 1.565190, 2.027519, 2.953081",\ + "1.201727, 1.459024, 1.733307, 2.195637, 3.121198",\ + "1.783640, 2.040930, 2.315206, 2.777534, 3.703092",\ + "0.989567, 1.254871, 1.527646, 1.989749, 2.914907",\ + "1.031319, 1.296623, 1.569398, 2.031502, 2.956660",\ + "1.091250, 1.356553, 1.629329, 2.091432, 3.016590",\ + "1.259367, 1.524671, 1.797446, 2.259549, 3.184707",\ + "1.841280, 2.106576, 2.379344, 2.841446, 3.766601",\ + "1.324649, 1.619500, 1.879453, 2.339067, 3.260363",\ + "1.366401, 1.661253, 1.921206, 2.380819, 3.302116",\ + "1.426332, 1.721183, 1.981136, 2.440749, 3.362046",\ + "1.594449, 1.889300, 2.149253, 2.608866, 3.530163",\ + "2.176360, 2.471204, 2.731152, 3.190763, 4.112057"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011"); + values ( "0.045877, 0.045877, 0.045877, 0.045877, 0.045877",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494119, 1.494119, 1.494119, 1.494119, 1.494120",\ + "0.045877, 0.045877, 0.045877, 0.045877, 0.045877",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494119, 1.494119, 1.494119, 1.494119, 1.494120",\ + "0.045877, 0.045877, 0.045877, 0.045877, 0.045877",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494119, 1.494119, 1.494119, 1.494119, 1.494120",\ + "0.045877, 0.045877, 0.045877, 0.045877, 0.045877",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494119, 1.494119, 1.494119, 1.494119, 1.494120",\ + "0.045877, 0.045877, 0.045877, 0.045877, 0.045877",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494119, 1.494119, 1.494119, 1.494119, 1.494120"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_2432*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[26]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011"); + values ( "0.602525, 0.840752, 1.118848, 1.606867, 2.582905",\ + "0.636915, 0.875142, 1.153247, 1.641296, 2.617393",\ + "0.708158, 0.946386, 1.224478, 1.712482, 2.688491",\ + "0.962324, 1.200552, 1.478688, 1.966845, 2.943158",\ + "1.886897, 2.125118, 2.403212, 2.891220, 3.867236",\ + "0.689934, 0.928280, 1.206475, 1.693581, 2.668839",\ + "0.724325, 0.962670, 1.240873, 1.728010, 2.703327",\ + "0.795567, 1.033914, 1.312104, 1.799197, 2.774425",\ + "1.049734, 1.288080, 1.566315, 2.053559, 3.029092",\ + "1.974307, 2.212646, 2.490838, 2.977934, 3.953170",\ + "0.770795, 1.017206, 1.294439, 1.781203, 2.755794",\ + "0.805185, 1.051596, 1.328838, 1.815632, 2.790282",\ + "0.876428, 1.122840, 1.400069, 1.886818, 2.861380",\ + "1.130594, 1.377006, 1.654280, 2.141181, 3.116047",\ + "2.055167, 2.301572, 2.578803, 3.065556, 4.040125",\ + "0.828465, 1.082761, 1.358582, 1.845116, 2.819303",\ + "0.862855, 1.117151, 1.392981, 1.879545, 2.853791",\ + "0.934098, 1.188395, 1.464212, 1.950732, 2.924889",\ + "1.188264, 1.442561, 1.718422, 2.205094, 3.179556",\ + "2.112837, 2.367127, 2.642946, 3.129469, 4.103634",\ + "1.149414, 1.446227, 1.710642, 2.194541, 3.164759",\ + "1.183804, 1.480617, 1.745041, 2.228970, 3.199247",\ + "1.255047, 1.551860, 1.816271, 2.300156, 3.270345",\ + "1.509214, 1.806027, 2.070484, 2.554519, 3.525012",\ + "2.433782, 2.730593, 2.995005, 3.478894, 4.449090"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011"); + values ( "0.034112, 0.034112, 0.034113, 0.034114, 0.034116",\ + "0.083749, 0.083750, 0.083752, 0.083758, 0.083770",\ + "0.208405, 0.208405, 0.208405, 0.208405, 0.208405",\ + "0.692756, 0.692757, 0.692767, 0.692798, 0.692859",\ + "2.464362, 2.464362, 2.464362, 2.464362, 2.464362",\ + "0.034112, 0.034112, 0.034113, 0.034114, 0.034116",\ + "0.083749, 0.083750, 0.083752, 0.083758, 0.083770",\ + "0.208405, 0.208405, 0.208405, 0.208405, 0.208405",\ + "0.692756, 0.692757, 0.692767, 0.692798, 0.692859",\ + "2.464362, 2.464362, 2.464362, 2.464362, 2.464362",\ + "0.034112, 0.034112, 0.034113, 0.034114, 0.034116",\ + "0.083749, 0.083750, 0.083752, 0.083758, 0.083770",\ + "0.208405, 0.208405, 0.208405, 0.208405, 0.208405",\ + "0.692756, 0.692757, 0.692767, 0.692798, 0.692859",\ + "2.464362, 2.464362, 2.464362, 2.464362, 2.464362",\ + "0.034112, 0.034112, 0.034113, 0.034114, 0.034116",\ + "0.083749, 0.083750, 0.083752, 0.083758, 0.083770",\ + "0.208405, 0.208405, 0.208405, 0.208405, 0.208405",\ + "0.692756, 0.692757, 0.692767, 0.692798, 0.692859",\ + "2.464362, 2.464362, 2.464362, 2.464362, 2.464362",\ + "0.034112, 0.034112, 0.034113, 0.034114, 0.034116",\ + "0.083749, 0.083750, 0.083752, 0.083758, 0.083770",\ + "0.208405, 0.208405, 0.208405, 0.208405, 0.208405",\ + "0.692756, 0.692757, 0.692767, 0.692798, 0.692859",\ + "2.464362, 2.464362, 2.464362, 2.464362, 2.464362"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011"); + values ( "0.634287, 0.872507, 1.150200, 1.636823, 2.610071",\ + "0.676039, 0.914259, 1.192001, 1.678792, 2.652375",\ + "0.735970, 0.974190, 1.251983, 1.738955, 2.712900",\ + "0.904087, 1.142307, 1.420172, 1.907391, 2.881829",\ + "1.486003, 1.724197, 2.002198, 2.489875, 3.465229",\ + "0.721696, 0.960035, 1.237821, 1.723538, 2.696005",\ + "0.763449, 1.001787, 1.279623, 1.765507, 2.738309",\ + "0.823379, 1.061718, 1.339606, 1.825670, 2.798834",\ + "0.991496, 1.229835, 1.507796, 1.994106, 2.967763",\ + "1.573412, 1.811725, 2.089823, 2.576589, 3.551162",\ + "0.802557, 1.048961, 1.325786, 1.811159, 2.782960",\ + "0.844309, 1.090713, 1.367588, 1.853128, 2.825264",\ + "0.904240, 1.150644, 1.427571, 1.913292, 2.885789",\ + "1.072357, 1.318761, 1.595761, 2.081728, 3.054718",\ + "1.654273, 1.900651, 2.177788, 2.664211, 3.638118",\ + "0.860227, 1.114515, 1.389929, 1.875073, 2.846469",\ + "0.901979, 1.156268, 1.431731, 1.917042, 2.888773",\ + "0.961910, 1.216198, 1.491714, 1.977205, 2.949298",\ + "1.130027, 1.384316, 1.659903, 2.145641, 3.118227",\ + "1.711942, 1.966206, 2.241930, 2.728124, 3.701627",\ + "1.181171, 1.477981, 1.741974, 2.224492, 3.191925",\ + "1.222923, 1.519734, 1.783778, 2.266461, 3.234229",\ + "1.282854, 1.579664, 1.843763, 2.326625, 3.294754",\ + "1.450971, 1.747782, 2.011955, 2.495062, 3.463683",\ + "2.032870, 2.329673, 2.593987, 3.077547, 4.047082"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011"); + values ( "0.045878, 0.045878, 0.045878, 0.045878, 0.045878",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494118, 1.494119, 1.494120, 1.494126, 1.494136",\ + "0.045878, 0.045878, 0.045878, 0.045878, 0.045878",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494118, 1.494119, 1.494120, 1.494126, 1.494136",\ + "0.045878, 0.045878, 0.045878, 0.045878, 0.045878",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494118, 1.494119, 1.494120, 1.494126, 1.494136",\ + "0.045878, 0.045878, 0.045878, 0.045878, 0.045878",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494118, 1.494119, 1.494120, 1.494126, 1.494136",\ + "0.045878, 0.045878, 0.045878, 0.045878, 0.045878",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494118, 1.494119, 1.494120, 1.494126, 1.494136"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_2526*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[28]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.555636, 0.806104, 1.084905, 1.584821, 2.584653",\ + "0.590029, 0.840498, 1.119303, 1.619235, 2.619098",\ + "0.661266, 0.911734, 1.190528, 1.690421, 2.690205",\ + "0.915433, 1.165901, 1.444770, 1.944926, 2.945236",\ + "1.840038, 2.090508, 2.369324, 2.869289, 3.869217",\ + "0.643048, 0.893609, 1.172570, 1.671536, 2.670587",\ + "0.677441, 0.928003, 1.206968, 1.705950, 2.705032",\ + "0.748679, 0.999240, 1.278193, 1.777135, 2.776139",\ + "1.002845, 1.253406, 1.532436, 2.031641, 3.031170",\ + "1.927450, 2.178014, 2.456990, 2.956004, 3.955151",\ + "0.723905, 0.982497, 1.260536, 1.759158, 2.757542",\ + "0.758298, 1.016890, 1.294935, 1.793572, 2.791987",\ + "0.829535, 1.088127, 1.366160, 1.864758, 2.863094",\ + "1.083702, 1.342294, 1.620402, 2.119263, 3.118125",\ + "2.008307, 2.266901, 2.544956, 3.043626, 4.042106",\ + "0.781799, 1.047996, 1.324681, 1.823071, 2.821051",\ + "0.816193, 1.082390, 1.359079, 1.857485, 2.855496",\ + "0.887430, 1.153626, 1.430304, 1.928671, 2.926603",\ + "1.141596, 1.407793, 1.684547, 2.183176, 3.181634",\ + "2.066201, 2.332401, 2.609101, 3.107539, 4.105615",\ + "1.114657, 1.410772, 1.676864, 2.172549, 3.166507",\ + "1.149050, 1.445166, 1.711262, 2.206963, 3.200952",\ + "1.220287, 1.516402, 1.782487, 2.278148, 3.272059",\ + "1.474454, 1.770569, 2.036732, 2.532654, 3.527090",\ + "2.399059, 2.695177, 2.961284, 3.457017, 4.451071"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.034112, 0.034113, 0.034114, 0.034119, 0.034130",\ + "0.083750, 0.083751, 0.083761, 0.083790, 0.083849",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692761, 0.692766, 0.692810, 0.692941, 0.693203",\ + "2.465173, 2.465199, 2.466091, 2.469060, 2.474999",\ + "0.034112, 0.034113, 0.034114, 0.034119, 0.034130",\ + "0.083750, 0.083751, 0.083761, 0.083790, 0.083849",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692761, 0.692766, 0.692810, 0.692941, 0.693203",\ + "2.465173, 2.465199, 2.466100, 2.469060, 2.474999",\ + "0.034112, 0.034113, 0.034114, 0.034119, 0.034130",\ + "0.083750, 0.083751, 0.083761, 0.083790, 0.083849",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692761, 0.692766, 0.692810, 0.692941, 0.693203",\ + "2.465173, 2.465199, 2.466100, 2.469060, 2.474999",\ + "0.034112, 0.034113, 0.034114, 0.034119, 0.034130",\ + "0.083750, 0.083751, 0.083761, 0.083790, 0.083849",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692761, 0.692766, 0.692810, 0.692941, 0.693203",\ + "2.465173, 2.465200, 2.466101, 2.469060, 2.474999",\ + "0.034112, 0.034113, 0.034114, 0.034119, 0.034130",\ + "0.083751, 0.083752, 0.083762, 0.083790, 0.083849",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692761, 0.692768, 0.692812, 0.692941, 0.693203",\ + "2.465173, 2.465210, 2.466131, 2.469072, 2.474999"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.587433, 0.837905, 1.116317, 1.614875, 2.611990",\ + "0.629185, 0.879656, 1.158119, 1.656853, 2.654322",\ + "0.689115, 0.939586, 1.218100, 1.717010, 2.714829",\ + "0.857231, 1.107703, 1.386286, 1.885441, 2.883749",\ + "1.439262, 1.689742, 1.968444, 2.467987, 3.467073",\ + "0.674846, 0.925410, 1.203978, 1.701590, 2.697924",\ + "0.716597, 0.967161, 1.245781, 1.743568, 2.740255",\ + "0.776528, 1.027092, 1.305762, 1.803725, 2.800763",\ + "0.944644, 1.195208, 1.473949, 1.972156, 2.969683",\ + "1.526675, 1.777247, 2.056108, 2.554702, 3.553007",\ + "0.755703, 1.014297, 1.291944, 1.789212, 2.784879",\ + "0.797454, 1.056048, 1.333747, 1.831190, 2.827210",\ + "0.857384, 1.115979, 1.393728, 1.891347, 2.887718",\ + "1.025501, 1.284095, 1.561916, 2.059778, 3.056638",\ + "1.607531, 1.866135, 2.144074, 2.642324, 3.639962",\ + "0.813597, 1.079797, 1.356089, 1.853126, 2.848388",\ + "0.855349, 1.121548, 1.397891, 1.895104, 2.890719",\ + "0.915279, 1.181478, 1.457873, 1.955260, 2.951227",\ + "1.083395, 1.349595, 1.626060, 2.123692, 3.120147",\ + "1.665427, 1.931634, 2.208219, 2.706238, 3.703471",\ + "1.146455, 1.442573, 1.708257, 2.202597, 3.193844",\ + "1.188207, 1.484324, 1.750062, 2.244576, 3.236176",\ + "1.248137, 1.544255, 1.810045, 2.304733, 3.296683",\ + "1.416253, 1.712371, 1.978235, 2.473166, 3.465603",\ + "1.998287, 2.294412, 2.560398, 3.055713, 4.048927"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.045876, 0.045875, 0.045861, 0.045821, 0.045741",\ + "0.079914, 0.079913, 0.079913, 0.079910, 0.079906",\ + "0.155804, 0.155803, 0.155792, 0.155761, 0.155698",\ + "0.431307, 0.431307, 0.431304, 0.431297, 0.431282",\ + "1.494119, 1.494120, 1.494128, 1.494150, 1.494195",\ + "0.045876, 0.045875, 0.045861, 0.045821, 0.045741",\ + "0.079914, 0.079913, 0.079913, 0.079910, 0.079906",\ + "0.155804, 0.155803, 0.155792, 0.155761, 0.155698",\ + "0.431307, 0.431307, 0.431304, 0.431297, 0.431282",\ + "1.494119, 1.494120, 1.494128, 1.494150, 1.494195",\ + "0.045876, 0.045875, 0.045861, 0.045821, 0.045741",\ + "0.079914, 0.079913, 0.079913, 0.079910, 0.079906",\ + "0.155804, 0.155803, 0.155792, 0.155761, 0.155698",\ + "0.431307, 0.431307, 0.431304, 0.431297, 0.431282",\ + "1.494119, 1.494120, 1.494128, 1.494150, 1.494195",\ + "0.045876, 0.045875, 0.045861, 0.045821, 0.045741",\ + "0.079914, 0.079913, 0.079913, 0.079910, 0.079906",\ + "0.155804, 0.155803, 0.155792, 0.155761, 0.155698",\ + "0.431307, 0.431307, 0.431304, 0.431297, 0.431282",\ + "1.494119, 1.494120, 1.494128, 1.494150, 1.494195",\ + "0.045876, 0.045874, 0.045861, 0.045821, 0.045741",\ + "0.079914, 0.079913, 0.079913, 0.079910, 0.079906",\ + "0.155804, 0.155802, 0.155792, 0.155761, 0.155698",\ + "0.431307, 0.431307, 0.431304, 0.431297, 0.431282",\ + "1.494119, 1.494120, 1.494128, 1.494150, 1.494195"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_2616*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[30]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.634427, 0.872697, 1.149292, 1.635475, 2.607842",\ + "0.668851, 0.907120, 1.183712, 1.669888, 2.642240",\ + "0.739833, 0.978100, 1.254713, 1.740957, 2.713446",\ + "0.993985, 1.232251, 1.508868, 1.995127, 2.967646",\ + "1.919059, 2.157313, 2.433878, 2.919960, 3.892124",\ + "0.721829, 0.960233, 1.236908, 1.722188, 2.693776",\ + "0.756252, 0.994656, 1.271329, 1.756601, 2.728174",\ + "0.827235, 1.065637, 1.342330, 1.827670, 2.799379",\ + "1.081387, 1.319787, 1.596485, 2.081840, 3.053579",\ + "2.006460, 2.244850, 2.521494, 3.006673, 3.978058",\ + "0.802677, 1.049143, 1.324872, 1.809809, 2.780731",\ + "0.837101, 1.083566, 1.359292, 1.844222, 2.815129",\ + "0.908083, 1.154546, 1.430293, 1.915291, 2.886334",\ + "1.162235, 1.408697, 1.684448, 2.169461, 3.140534",\ + "2.087309, 2.333760, 2.609457, 3.094293, 4.065013",\ + "0.860401, 1.114674, 1.389014, 1.873721, 2.844240",\ + "0.894825, 1.149096, 1.423434, 1.908134, 2.878638",\ + "0.965807, 1.220077, 1.494435, 1.979203, 2.949843",\ + "1.219959, 1.474228, 1.748591, 2.233373, 3.204043",\ + "2.145033, 2.399290, 2.673600, 3.158206, 4.128522",\ + "1.188527, 1.477957, 1.741051, 2.223131, 3.189696",\ + "1.222950, 1.512379, 1.775471, 2.257544, 3.224094",\ + "1.293931, 1.583360, 1.846473, 2.328613, 3.295300",\ + "1.548083, 1.837511, 2.100628, 2.582783, 3.549500",\ + "2.473149, 2.762573, 3.025636, 3.507615, 4.473978"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.034240, 0.034240, 0.034242, 0.034250, 0.034266",\ + "0.083583, 0.083583, 0.083588, 0.083605, 0.083639",\ + "0.208066, 0.208067, 0.208071, 0.208084, 0.208111",\ + "0.693291, 0.693291, 0.693291, 0.693291, 0.693291",\ + "2.470530, 2.470530, 2.470531, 2.470531, 2.470532",\ + "0.034240, 0.034240, 0.034243, 0.034250, 0.034266",\ + "0.083583, 0.083583, 0.083589, 0.083605, 0.083639",\ + "0.208066, 0.208067, 0.208071, 0.208084, 0.208111",\ + "0.693291, 0.693291, 0.693291, 0.693291, 0.693291",\ + "2.470530, 2.470530, 2.470531, 2.470531, 2.470532",\ + "0.034240, 0.034240, 0.034243, 0.034250, 0.034266",\ + "0.083583, 0.083583, 0.083589, 0.083605, 0.083639",\ + "0.208066, 0.208067, 0.208071, 0.208084, 0.208111",\ + "0.693291, 0.693291, 0.693291, 0.693291, 0.693291",\ + "2.470530, 2.470530, 2.470531, 2.470531, 2.470532",\ + "0.034240, 0.034240, 0.034243, 0.034250, 0.034266",\ + "0.083583, 0.083583, 0.083589, 0.083605, 0.083639",\ + "0.208066, 0.208067, 0.208071, 0.208084, 0.208111",\ + "0.693291, 0.693291, 0.693291, 0.693291, 0.693291",\ + "2.470530, 2.470530, 2.470531, 2.470531, 2.470532",\ + "0.034240, 0.034240, 0.034243, 0.034250, 0.034266",\ + "0.083583, 0.083583, 0.083589, 0.083605, 0.083639",\ + "0.208066, 0.208067, 0.208071, 0.208084, 0.208111",\ + "0.693291, 0.693291, 0.693291, 0.693291, 0.693291",\ + "2.470530, 2.470530, 2.470531, 2.470531, 2.470532"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.661467, 0.899737, 1.176348, 1.662586, 2.635063",\ + "0.703763, 0.942033, 1.218582, 1.704611, 2.676670",\ + "0.764325, 1.002595, 1.279082, 1.764899, 2.736534",\ + "0.933255, 1.171525, 1.447944, 1.933534, 2.904712",\ + "1.516509, 1.754779, 2.031088, 2.516304, 3.486737",\ + "0.748868, 0.987273, 1.263965, 1.749299, 2.720997",\ + "0.791164, 1.029569, 1.306198, 1.791324, 2.762603",\ + "0.851727, 1.090131, 1.366697, 1.851612, 2.822468",\ + "1.020657, 1.259062, 1.535559, 2.020247, 2.990646",\ + "1.603910, 1.842315, 2.118701, 2.603017, 3.572671",\ + "0.829717, 1.076183, 1.351928, 1.836920, 2.807952",\ + "0.872012, 1.118479, 1.394161, 1.878945, 2.849558",\ + "0.932575, 1.179041, 1.454660, 1.939233, 2.909423",\ + "1.101505, 1.347972, 1.623522, 2.107867, 3.077601",\ + "1.684759, 1.931225, 2.206665, 2.690638, 3.659626",\ + "0.887441, 1.141714, 1.416070, 1.900832, 2.871461",\ + "0.929737, 1.184009, 1.458303, 1.942857, 2.913067",\ + "0.990299, 1.244572, 1.518803, 2.003145, 2.972932",\ + "1.159229, 1.413502, 1.687665, 2.171780, 3.141110",\ + "1.742483, 1.996755, 2.270807, 2.754550, 3.723135",\ + "1.215567, 1.504997, 1.768108, 2.250242, 3.216917",\ + "1.257862, 1.547292, 1.810339, 2.292266, 3.258523",\ + "1.318425, 1.607855, 1.870836, 2.352553, 3.318388",\ + "1.487355, 1.776785, 2.039696, 2.521187, 3.486566",\ + "2.070609, 2.360038, 2.622834, 3.103956, 4.068591"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.045862, 0.045862, 0.045862, 0.045862, 0.045862",\ + "0.079960, 0.079960, 0.079960, 0.079960, 0.079960",\ + "0.155688, 0.155688, 0.155688, 0.155688, 0.155688",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498067, 1.498067, 1.498067, 1.498067, 1.498067",\ + "0.045862, 0.045862, 0.045862, 0.045862, 0.045862",\ + "0.079960, 0.079960, 0.079960, 0.079960, 0.079960",\ + "0.155688, 0.155688, 0.155688, 0.155688, 0.155688",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498067, 1.498067, 1.498067, 1.498067, 1.498067",\ + "0.045862, 0.045862, 0.045862, 0.045862, 0.045862",\ + "0.079960, 0.079960, 0.079960, 0.079960, 0.079960",\ + "0.155688, 0.155688, 0.155688, 0.155688, 0.155688",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498067, 1.498067, 1.498067, 1.498067, 1.498067",\ + "0.045862, 0.045862, 0.045862, 0.045862, 0.045862",\ + "0.079960, 0.079960, 0.079960, 0.079960, 0.079960",\ + "0.155688, 0.155688, 0.155688, 0.155688, 0.155688",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498067, 1.498067, 1.498067, 1.498067, 1.498067",\ + "0.045862, 0.045862, 0.045862, 0.045862, 0.045862",\ + "0.079960, 0.079960, 0.079960, 0.079960, 0.079960",\ + "0.155688, 0.155688, 0.155688, 0.155688, 0.155688",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498067, 1.498067, 1.498067, 1.498067, 1.498067"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_2722*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[36]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.584050, 0.834549, 1.112490, 1.609591, 2.603792",\ + "0.618482, 0.868982, 1.146923, 1.644024, 2.638226",\ + "0.689476, 0.939977, 1.217929, 1.715062, 2.709330",\ + "0.943640, 1.194143, 1.472115, 1.969317, 2.963722",\ + "1.868820, 2.119334, 2.397313, 2.894526, 3.888954",\ + "0.671463, 0.922054, 1.200147, 1.696306, 2.689726",\ + "0.705894, 0.956486, 1.234580, 1.730739, 2.724160",\ + "0.776888, 1.027482, 1.305585, 1.801777, 2.795263",\ + "1.031053, 1.281648, 1.559772, 2.056032, 3.049656",\ + "1.956232, 2.206839, 2.484970, 2.981241, 3.974888",\ + "0.752319, 1.010941, 1.288113, 1.783928, 2.776681",\ + "0.786751, 1.045373, 1.322546, 1.818361, 2.811115",\ + "0.857745, 1.116369, 1.393551, 1.889400, 2.882218",\ + "1.111909, 1.370534, 1.647738, 2.143654, 3.136611",\ + "2.037089, 2.295726, 2.572936, 3.068864, 4.061843",\ + "0.810059, 1.076439, 1.352257, 1.847842, 2.840190",\ + "0.844490, 1.110871, 1.386690, 1.882275, 2.874624",\ + "0.915485, 1.181867, 1.457695, 1.953313, 2.945727",\ + "1.169649, 1.436033, 1.711882, 2.207568, 3.200120",\ + "2.094831, 2.361224, 2.637080, 3.132777, 4.125352",\ + "1.143033, 1.439203, 1.704411, 2.197307, 3.185646",\ + "1.177464, 1.473635, 1.738844, 2.231740, 3.220080",\ + "1.248459, 1.544631, 1.809850, 2.302778, 3.291183",\ + "1.502625, 1.798797, 2.064037, 2.557034, 3.545576",\ + "2.427809, 2.723989, 2.989235, 3.482243, 4.470808"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.034240, 0.034241, 0.034251, 0.034278, 0.034331",\ + "0.083583, 0.083586, 0.083606, 0.083665, 0.083782",\ + "0.208067, 0.208069, 0.208085, 0.208132, 0.208225",\ + "0.693300, 0.693300, 0.693300, 0.693300, 0.693300",\ + "2.470758, 2.470775, 2.471205, 2.472677, 2.475621",\ + "0.034240, 0.034241, 0.034251, 0.034278, 0.034331",\ + "0.083583, 0.083586, 0.083607, 0.083665, 0.083782",\ + "0.208067, 0.208069, 0.208085, 0.208132, 0.208225",\ + "0.693300, 0.693300, 0.693300, 0.693300, 0.693300",\ + "2.470758, 2.470775, 2.471210, 2.472677, 2.475621",\ + "0.034240, 0.034241, 0.034251, 0.034278, 0.034331",\ + "0.083583, 0.083586, 0.083607, 0.083665, 0.083782",\ + "0.208067, 0.208069, 0.208085, 0.208132, 0.208225",\ + "0.693300, 0.693300, 0.693300, 0.693300, 0.693300",\ + "2.470758, 2.470775, 2.471210, 2.472677, 2.475621",\ + "0.034240, 0.034241, 0.034251, 0.034278, 0.034331",\ + "0.083583, 0.083586, 0.083607, 0.083665, 0.083782",\ + "0.208067, 0.208069, 0.208085, 0.208132, 0.208225",\ + "0.693300, 0.693300, 0.693300, 0.693300, 0.693300",\ + "2.470760, 2.470775, 2.471210, 2.472677, 2.475621",\ + "0.034240, 0.034242, 0.034251, 0.034278, 0.034331",\ + "0.083584, 0.083587, 0.083607, 0.083665, 0.083782",\ + "0.208067, 0.208070, 0.208086, 0.208132, 0.208225",\ + "0.693300, 0.693300, 0.693300, 0.693300, 0.693300",\ + "2.470765, 2.470777, 2.471225, 2.472683, 2.475621"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.611087, 0.861585, 1.139535, 1.636665, 2.630925",\ + "0.653383, 0.903882, 1.181783, 1.678745, 2.672669",\ + "0.713946, 0.964444, 1.242285, 1.739034, 2.732533",\ + "0.882876, 1.133375, 1.411144, 1.907646, 2.900649",\ + "1.466128, 1.716626, 1.994359, 2.490734, 3.483483",\ + "0.698499, 0.949090, 1.227192, 1.723380, 2.716859",\ + "0.740795, 0.991387, 1.269439, 1.765460, 2.758603",\ + "0.801358, 1.051949, 1.329940, 1.825749, 2.818467",\ + "0.970289, 1.220880, 1.498799, 1.994361, 2.986582",\ + "1.553540, 1.804131, 2.082013, 2.577449, 3.569417",\ + "0.779356, 1.037977, 1.315158, 1.811002, 2.803814",\ + "0.821652, 1.080273, 1.357405, 1.853082, 2.845558",\ + "0.882215, 1.140836, 1.417906, 1.913371, 2.905422",\ + "1.051145, 1.309767, 1.586765, 2.081983, 3.073537",\ + "1.634397, 1.893018, 2.169979, 2.665071, 3.656372",\ + "0.837095, 1.103475, 1.379302, 1.874916, 2.867323",\ + "0.879392, 1.145772, 1.421550, 1.916996, 2.909067",\ + "0.939954, 1.206334, 1.482050, 1.977285, 2.968931",\ + "1.108885, 1.375265, 1.650909, 2.145896, 3.137046",\ + "1.692136, 1.958516, 2.234123, 2.728984, 3.719881",\ + "1.170069, 1.466239, 1.731456, 2.224381, 3.212779",\ + "1.212365, 1.508535, 1.773702, 2.266461, 3.254523",\ + "1.272928, 1.569098, 1.834201, 2.326749, 3.314387",\ + "1.441859, 1.738029, 2.003057, 2.495359, 3.482502",\ + "2.025110, 2.321280, 2.586270, 3.078447, 4.065337"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.045859, 0.045858, 0.045856, 0.045847, 0.045830",\ + "0.079972, 0.079972, 0.079972, 0.079972, 0.079972",\ + "0.155685, 0.155685, 0.155683, 0.155678, 0.155666",\ + "0.431271, 0.431271, 0.431271, 0.431270, 0.431268",\ + "1.498064, 1.498063, 1.498061, 1.498051, 1.498033",\ + "0.045859, 0.045858, 0.045856, 0.045847, 0.045830",\ + "0.079972, 0.079972, 0.079972, 0.079972, 0.079972",\ + "0.155685, 0.155685, 0.155683, 0.155678, 0.155666",\ + "0.431271, 0.431271, 0.431271, 0.431270, 0.431268",\ + "1.498064, 1.498063, 1.498060, 1.498051, 1.498033",\ + "0.045859, 0.045858, 0.045856, 0.045847, 0.045830",\ + "0.079972, 0.079972, 0.079972, 0.079972, 0.079972",\ + "0.155685, 0.155685, 0.155683, 0.155678, 0.155666",\ + "0.431271, 0.431271, 0.431271, 0.431270, 0.431268",\ + "1.498064, 1.498063, 1.498060, 1.498051, 1.498033",\ + "0.045859, 0.045858, 0.045856, 0.045847, 0.045830",\ + "0.079972, 0.079972, 0.079972, 0.079972, 0.079972",\ + "0.155685, 0.155685, 0.155683, 0.155678, 0.155666",\ + "0.431271, 0.431271, 0.431271, 0.431270, 0.431268",\ + "1.498064, 1.498063, 1.498060, 1.498051, 1.498033",\ + "0.045858, 0.045858, 0.045856, 0.045847, 0.045830",\ + "0.079972, 0.079972, 0.079972, 0.079972, 0.079972",\ + "0.155685, 0.155685, 0.155683, 0.155678, 0.155666",\ + "0.431271, 0.431271, 0.431271, 0.431270, 0.431268",\ + "1.498063, 1.498063, 1.498060, 1.498051, 1.498033"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_2499*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[38]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.576605, 0.831535, 1.088524, 1.527728, 2.406135",\ + "0.611028, 0.865958, 1.122948, 1.562156, 2.440572",\ + "0.682011, 0.936939, 1.193932, 1.633147, 2.511575",\ + "0.936163, 1.191091, 1.448086, 1.887307, 2.765749",\ + "1.861240, 2.116160, 2.373173, 2.812451, 3.691008",\ + "0.664013, 0.919020, 1.175996, 1.614442, 2.492069",\ + "0.698437, 0.953443, 1.210420, 1.648871, 2.526506",\ + "0.769419, 1.024424, 1.281404, 1.719861, 2.597509",\ + "1.023571, 1.278576, 1.535558, 1.974021, 2.851683",\ + "1.948648, 2.203645, 2.460645, 2.899166, 3.776942",\ + "0.751657, 1.007845, 1.263958, 1.702063, 2.579024",\ + "0.786080, 1.042268, 1.298382, 1.736492, 2.613461",\ + "0.857063, 1.113249, 1.369366, 1.807482, 2.684464",\ + "1.111215, 1.367401, 1.623520, 2.061643, 2.938638",\ + "2.036291, 2.292470, 2.548607, 2.986787, 3.863897",\ + "0.814841, 1.073252, 1.328092, 1.765976, 2.642533",\ + "0.849265, 1.107675, 1.362517, 1.800405, 2.676970",\ + "0.920247, 1.178657, 1.433500, 1.871395, 2.747973",\ + "1.174399, 1.432808, 1.687654, 2.125556, 3.002147",\ + "2.099474, 2.357878, 2.612742, 3.050700, 3.927406",\ + "1.148308, 1.435007, 1.679656, 2.115198, 2.987988",\ + "1.182731, 1.469430, 1.714081, 2.149627, 3.022426",\ + "1.253713, 1.540412, 1.785064, 2.220617, 3.093429",\ + "1.507865, 1.794564, 2.039218, 2.474777, 3.347603",\ + "2.432936, 2.719633, 2.964306, 3.399922, 4.272861"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.034240, 0.034240, 0.034246, 0.034266, 0.034306",\ + "0.083583, 0.083583, 0.083596, 0.083639, 0.083725",\ + "0.208066, 0.208066, 0.208076, 0.208111, 0.208180",\ + "0.693294, 0.693296, 0.693300, 0.693300, 0.693300",\ + "2.470544, 2.470544, 2.470714, 2.471298, 2.472467",\ + "0.034240, 0.034240, 0.034246, 0.034266, 0.034306",\ + "0.083583, 0.083583, 0.083596, 0.083639, 0.083725",\ + "0.208066, 0.208066, 0.208077, 0.208111, 0.208180",\ + "0.693294, 0.693296, 0.693300, 0.693300, 0.693300",\ + "2.470544, 2.470544, 2.470715, 2.471298, 2.472467",\ + "0.034240, 0.034240, 0.034246, 0.034266, 0.034306",\ + "0.083583, 0.083583, 0.083596, 0.083639, 0.083725",\ + "0.208066, 0.208066, 0.208077, 0.208111, 0.208180",\ + "0.693294, 0.693296, 0.693300, 0.693300, 0.693300",\ + "2.470544, 2.470544, 2.470716, 2.471298, 2.472467",\ + "0.034240, 0.034240, 0.034246, 0.034266, 0.034306",\ + "0.083583, 0.083583, 0.083596, 0.083639, 0.083725",\ + "0.208066, 0.208066, 0.208077, 0.208111, 0.208180",\ + "0.693294, 0.693296, 0.693300, 0.693300, 0.693300",\ + "2.470544, 2.470544, 2.470716, 2.471298, 2.472467",\ + "0.034240, 0.034240, 0.034246, 0.034266, 0.034306",\ + "0.083583, 0.083583, 0.083596, 0.083639, 0.083725",\ + "0.208066, 0.208066, 0.208077, 0.208111, 0.208180",\ + "0.693294, 0.693297, 0.693300, 0.693300, 0.693300",\ + "2.470544, 2.470544, 2.470721, 2.471301, 2.472467"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.603644, 0.858574, 1.115563, 1.554765, 2.433169",\ + "0.645940, 0.900870, 1.157859, 1.597061, 2.475466",\ + "0.706502, 0.961433, 1.218421, 1.657624, 2.536028",\ + "0.875433, 1.130363, 1.387352, 1.826554, 2.704960",\ + "1.458686, 1.713616, 1.970605, 2.409806, 3.288209",\ + "0.691052, 0.946059, 1.203035, 1.641479, 2.519103",\ + "0.733348, 0.988355, 1.245331, 1.683775, 2.561400",\ + "0.793911, 1.048918, 1.305893, 1.744338, 2.621962",\ + "0.962841, 1.217848, 1.474824, 1.913269, 2.790894",\ + "1.546094, 1.801101, 2.058077, 2.496521, 3.374143",\ + "0.778696, 1.034884, 1.290997, 1.729101, 2.606058",\ + "0.820992, 1.077180, 1.333292, 1.771397, 2.648355",\ + "0.881555, 1.137743, 1.393855, 1.831960, 2.708917",\ + "1.050485, 1.306673, 1.562785, 2.000890, 2.877849",\ + "1.633738, 1.889926, 2.146038, 2.584142, 3.461098",\ + "0.841881, 1.100292, 1.355131, 1.793014, 2.669567",\ + "0.884176, 1.142587, 1.397427, 1.835310, 2.711864",\ + "0.944739, 1.203150, 1.457990, 1.895873, 2.772426",\ + "1.113669, 1.372080, 1.626920, 2.064803, 2.941358",\ + "1.696922, 1.955333, 2.210173, 2.648055, 3.524607",\ + "1.175348, 1.462047, 1.706695, 2.142236, 3.015023",\ + "1.217643, 1.504343, 1.748991, 2.184532, 3.057320",\ + "1.278206, 1.564905, 1.809554, 2.245094, 3.117882",\ + "1.447136, 1.733835, 1.978484, 2.414025, 3.286813",\ + "2.030389, 2.317089, 2.561737, 2.997277, 3.870063"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.045862, 0.045862, 0.045861, 0.045860, 0.045856",\ + "0.079962, 0.079962, 0.079962, 0.079962, 0.079962",\ + "0.155688, 0.155688, 0.155687, 0.155686, 0.155684",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498067, 1.498067, 1.498066, 1.498065, 1.498061",\ + "0.045862, 0.045862, 0.045861, 0.045860, 0.045856",\ + "0.079962, 0.079962, 0.079962, 0.079962, 0.079962",\ + "0.155688, 0.155688, 0.155687, 0.155686, 0.155684",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498067, 1.498067, 1.498066, 1.498065, 1.498061",\ + "0.045862, 0.045862, 0.045861, 0.045860, 0.045856",\ + "0.079962, 0.079962, 0.079962, 0.079962, 0.079962",\ + "0.155688, 0.155688, 0.155687, 0.155686, 0.155684",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498067, 1.498067, 1.498066, 1.498065, 1.498061",\ + "0.045862, 0.045862, 0.045861, 0.045860, 0.045856",\ + "0.079962, 0.079962, 0.079962, 0.079962, 0.079962",\ + "0.155688, 0.155688, 0.155687, 0.155686, 0.155684",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498067, 1.498067, 1.498066, 1.498065, 1.498061",\ + "0.045862, 0.045862, 0.045861, 0.045860, 0.045856",\ + "0.079962, 0.079962, 0.079962, 0.079962, 0.079962",\ + "0.155688, 0.155688, 0.155687, 0.155686, 0.155684",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498067, 1.498067, 1.498066, 1.498065, 1.498061"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_2578*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[43]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011"); + values ( "0.703817, 0.965190, 1.250386, 1.755046, 2.764366",\ + "0.738210, 0.999583, 1.284779, 1.789440, 2.798762",\ + "0.809448, 1.070821, 1.356016, 1.860676, 2.869994",\ + "1.063614, 1.324987, 1.610183, 2.114842, 3.124160",\ + "1.988218, 2.249590, 2.534788, 3.039459, 4.048801",\ + "0.791226, 1.052733, 1.338065, 1.841760, 2.850300",\ + "0.825619, 1.087126, 1.372458, 1.876155, 2.884696",\ + "0.896857, 1.158363, 1.443695, 1.947390, 2.955927",\ + "1.151023, 1.412530, 1.697862, 2.201556, 3.210094",\ + "2.075627, 2.337133, 2.622467, 3.126173, 4.134735",\ + "0.874336, 1.141692, 1.426031, 1.929382, 2.937255",\ + "0.908729, 1.176085, 1.460424, 1.963776, 2.971651",\ + "0.979967, 1.247323, 1.531661, 2.035012, 3.042882",\ + "1.234133, 1.501489, 1.785827, 2.289178, 3.297049",\ + "2.158737, 2.426092, 2.710433, 3.213795, 4.221690",\ + "0.937775, 1.207295, 1.490176, 1.993295, 3.000764",\ + "0.972168, 1.241688, 1.524569, 2.027689, 3.035160",\ + "1.043406, 1.312926, 1.595807, 2.098925, 3.106391",\ + "1.297572, 1.567092, 1.849973, 2.353091, 3.360558",\ + "2.222176, 2.491695, 2.774579, 3.277709, 4.285199",\ + "1.272869, 1.571325, 1.842405, 2.342789, 3.346220",\ + "1.307262, 1.605718, 1.876798, 2.377183, 3.380616",\ + "1.378499, 1.676956, 1.948035, 2.448418, 3.451848",\ + "1.632666, 1.931122, 2.202202, 2.702585, 3.706014",\ + "2.557269, 2.855725, 3.126807, 3.627202, 4.630655"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011"); + values ( "0.034112, 0.034112, 0.034113, 0.034115, 0.034118",\ + "0.083750, 0.083751, 0.083754, 0.083762, 0.083778",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692760, 0.692763, 0.692780, 0.692819, 0.692898",\ + "2.465101, 2.465101, 2.465179, 2.465445, 2.465979",\ + "0.034112, 0.034112, 0.034113, 0.034115, 0.034118",\ + "0.083750, 0.083751, 0.083754, 0.083762, 0.083778",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692760, 0.692763, 0.692780, 0.692819, 0.692898",\ + "2.465101, 2.465101, 2.465179, 2.465445, 2.465979",\ + "0.034112, 0.034112, 0.034113, 0.034115, 0.034118",\ + "0.083750, 0.083751, 0.083754, 0.083762, 0.083778",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692760, 0.692763, 0.692780, 0.692819, 0.692898",\ + "2.465101, 2.465101, 2.465179, 2.465445, 2.465979",\ + "0.034112, 0.034112, 0.034113, 0.034115, 0.034118",\ + "0.083750, 0.083751, 0.083754, 0.083762, 0.083778",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692760, 0.692763, 0.692780, 0.692819, 0.692898",\ + "2.465101, 2.465101, 2.465180, 2.465445, 2.465979",\ + "0.034112, 0.034112, 0.034113, 0.034115, 0.034118",\ + "0.083750, 0.083751, 0.083754, 0.083762, 0.083778",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692760, 0.692765, 0.692780, 0.692820, 0.692898",\ + "2.465101, 2.465101, 2.465182, 2.465446, 2.465979"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011"); + values ( "0.735613, 0.996985, 1.282184, 1.786857, 2.796203",\ + "0.777364, 1.038737, 1.323936, 1.828608, 2.837953",\ + "0.837295, 1.098667, 1.383866, 1.888539, 2.897883",\ + "1.005411, 1.266784, 1.551982, 2.056655, 3.065999",\ + "1.587437, 1.848807, 2.134015, 2.638729, 3.648157",\ + "0.823022, 1.084528, 1.369863, 1.873571, 2.882137",\ + "0.864774, 1.126280, 1.411614, 1.915322, 2.923887",\ + "0.924704, 1.186210, 1.471545, 1.975253, 2.983817",\ + "1.092821, 1.354327, 1.639661, 2.143369, 3.151933",\ + "1.674846, 1.936350, 2.221694, 2.725443, 3.734090",\ + "0.906132, 1.173487, 1.457829, 1.961193, 2.969092",\ + "0.947883, 1.215239, 1.499580, 2.002944, 3.010842",\ + "1.007814, 1.275169, 1.559510, 2.062875, 3.070772",\ + "1.175930, 1.443286, 1.727627, 2.230991, 3.238888",\ + "1.757956, 2.025309, 2.309659, 2.813065, 3.821045",\ + "0.969571, 1.239090, 1.521974, 2.025106, 3.032601",\ + "1.011322, 1.280842, 1.563726, 2.066857, 3.074351",\ + "1.071253, 1.340772, 1.623656, 2.126788, 3.134281",\ + "1.239369, 1.508889, 1.791773, 2.294904, 3.302397",\ + "1.821394, 2.090912, 2.373805, 2.876978, 3.884554",\ + "1.304665, 1.603120, 1.874203, 2.374600, 3.378057",\ + "1.346416, 1.644871, 1.915954, 2.416351, 3.419807",\ + "1.406347, 1.704802, 1.975885, 2.476281, 3.479737",\ + "1.574463, 1.872918, 2.144001, 2.644397, 3.647853",\ + "2.156488, 2.454941, 2.726034, 3.226472, 4.230011"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011"); + values ( "0.045877, 0.045877, 0.045877, 0.045877, 0.045877",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155804, 0.155804, 0.155804, 0.155804, 0.155804",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494119, 1.494120, 1.494123, 1.494129, 1.494143",\ + "0.045877, 0.045877, 0.045877, 0.045877, 0.045877",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155804, 0.155804, 0.155804, 0.155804, 0.155804",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494119, 1.494120, 1.494123, 1.494129, 1.494143",\ + "0.045877, 0.045877, 0.045877, 0.045877, 0.045877",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155804, 0.155804, 0.155804, 0.155804, 0.155804",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494119, 1.494120, 1.494123, 1.494129, 1.494143",\ + "0.045877, 0.045877, 0.045877, 0.045877, 0.045877",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155804, 0.155804, 0.155804, 0.155804, 0.155804",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494119, 1.494120, 1.494123, 1.494129, 1.494143",\ + "0.045877, 0.045877, 0.045877, 0.045877, 0.045877",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155804, 0.155804, 0.155804, 0.155804, 0.155804",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494119, 1.494120, 1.494123, 1.494129, 1.494143"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_2448*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[44]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011"); + values ( "0.689792, 0.930744, 1.201013, 1.654265, 2.560769",\ + "0.724185, 0.965137, 1.235406, 1.688659, 2.595164",\ + "0.795422, 1.036375, 1.306643, 1.759894, 2.666397",\ + "1.049588, 1.290541, 1.560810, 2.014061, 2.920563",\ + "1.974192, 2.215145, 2.485415, 2.938676, 3.845196",\ + "0.777198, 1.018294, 1.288529, 1.740979, 2.646702",\ + "0.811591, 1.052687, 1.322922, 1.775373, 2.681098",\ + "0.882828, 1.123924, 1.394159, 1.846608, 2.752330",\ + "1.136994, 1.378091, 1.648325, 2.100775, 3.006497",\ + "2.061598, 2.302694, 2.572931, 3.025389, 3.931130",\ + "0.858027, 1.107253, 1.376491, 1.828600, 2.733657",\ + "0.892420, 1.141646, 1.410884, 1.862994, 2.768053",\ + "0.963658, 1.212883, 1.482121, 1.934230, 2.839285",\ + "1.217824, 1.467050, 1.736287, 2.188396, 3.093452",\ + "2.142428, 2.391653, 2.660893, 3.113011, 4.018085",\ + "0.915670, 1.172855, 1.440628, 1.892513, 2.797166",\ + "0.950063, 1.207248, 1.475021, 1.926907, 2.831562",\ + "1.021300, 1.278486, 1.546258, 1.998143, 2.902794",\ + "1.275467, 1.532652, 1.800424, 2.252309, 3.156961",\ + "2.200070, 2.457256, 2.725030, 3.176924, 4.081594",\ + "1.241554, 1.536923, 1.792333, 2.241791, 3.142622",\ + "1.275947, 1.571316, 1.826726, 2.276185, 3.177018",\ + "1.347184, 1.642554, 1.897963, 2.347420, 3.248250",\ + "1.601351, 1.896721, 2.152130, 2.601587, 3.502417",\ + "2.525954, 2.821324, 3.076735, 3.526202, 4.427050"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011"); + values ( "0.034112, 0.034112, 0.034113, 0.034114, 0.034116",\ + "0.083750, 0.083751, 0.083753, 0.083759, 0.083772",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692760, 0.692762, 0.692773, 0.692804, 0.692866",\ + "2.465102, 2.465102, 2.465164, 2.465378, 2.465806",\ + "0.034112, 0.034112, 0.034113, 0.034114, 0.034116",\ + "0.083750, 0.083751, 0.083753, 0.083759, 0.083772",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692760, 0.692762, 0.692774, 0.692804, 0.692866",\ + "2.465102, 2.465102, 2.465165, 2.465378, 2.465806",\ + "0.034112, 0.034112, 0.034113, 0.034114, 0.034116",\ + "0.083750, 0.083751, 0.083753, 0.083759, 0.083772",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692760, 0.692762, 0.692774, 0.692804, 0.692866",\ + "2.465102, 2.465102, 2.465165, 2.465378, 2.465806",\ + "0.034112, 0.034112, 0.034113, 0.034114, 0.034116",\ + "0.083750, 0.083751, 0.083753, 0.083759, 0.083772",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692760, 0.692762, 0.692774, 0.692804, 0.692866",\ + "2.465102, 2.465102, 2.465165, 2.465378, 2.465806",\ + "0.034112, 0.034112, 0.034113, 0.034114, 0.034116",\ + "0.083750, 0.083751, 0.083753, 0.083759, 0.083772",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692760, 0.692762, 0.692774, 0.692805, 0.692866",\ + "2.465102, 2.465102, 2.465167, 2.465379, 2.465806"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011"); + values ( "0.721587, 0.962540, 1.232811, 1.686073, 2.592597",\ + "0.763339, 1.004291, 1.274563, 1.727824, 2.634348",\ + "0.823269, 1.064222, 1.334493, 1.787755, 2.694278",\ + "0.991386, 1.232338, 1.502609, 1.955871, 2.862394",\ + "1.573411, 1.814363, 2.084642, 2.537936, 3.444525",\ + "0.808993, 1.050089, 1.320327, 1.772787, 2.678531",\ + "0.850745, 1.091841, 1.362078, 1.814538, 2.720282",\ + "0.910675, 1.151771, 1.422008, 1.874469, 2.780212",\ + "1.078792, 1.319888, 1.590125, 2.042585, 2.948328",\ + "1.660817, 1.901912, 2.172157, 2.624650, 3.530459",\ + "0.889823, 1.139049, 1.408289, 1.860408, 2.765486",\ + "0.931575, 1.180800, 1.450040, 1.902159, 2.807237",\ + "0.991505, 1.240730, 1.509970, 1.962090, 2.867167",\ + "1.159622, 1.408847, 1.678087, 2.130206, 3.035283",\ + "1.741647, 1.990871, 2.260119, 2.712271, 3.617414",\ + "0.947466, 1.204651, 1.472426, 1.924321, 2.828995",\ + "0.989217, 1.246402, 1.514177, 1.966072, 2.870746",\ + "1.049147, 1.306333, 1.574107, 2.026003, 2.930676",\ + "1.217264, 1.474449, 1.742224, 2.194119, 3.098792",\ + "1.799289, 2.056473, 2.324256, 2.776184, 3.680923",\ + "1.273350, 1.568719, 1.824131, 2.273599, 3.174451",\ + "1.315101, 1.610470, 1.865882, 2.315350, 3.216202",\ + "1.375032, 1.670401, 1.925813, 2.375281, 3.276132",\ + "1.543148, 1.838517, 2.093929, 2.543397, 3.444248",\ + "2.125174, 2.420541, 2.675962, 3.125462, 4.026379"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011"); + values ( "0.045877, 0.045876, 0.045872, 0.045863, 0.045844",\ + "0.079914, 0.079914, 0.079913, 0.079913, 0.079912",\ + "0.155804, 0.155804, 0.155801, 0.155793, 0.155779",\ + "0.431307, 0.431307, 0.431306, 0.431304, 0.431301",\ + "1.494119, 1.494119, 1.494121, 1.494127, 1.494137",\ + "0.045877, 0.045876, 0.045872, 0.045863, 0.045844",\ + "0.079914, 0.079914, 0.079913, 0.079913, 0.079912",\ + "0.155804, 0.155804, 0.155801, 0.155793, 0.155779",\ + "0.431307, 0.431307, 0.431306, 0.431304, 0.431301",\ + "1.494119, 1.494120, 1.494121, 1.494127, 1.494137",\ + "0.045877, 0.045876, 0.045872, 0.045863, 0.045844",\ + "0.079914, 0.079914, 0.079913, 0.079913, 0.079912",\ + "0.155804, 0.155804, 0.155801, 0.155793, 0.155779",\ + "0.431307, 0.431307, 0.431306, 0.431304, 0.431301",\ + "1.494119, 1.494120, 1.494121, 1.494127, 1.494137",\ + "0.045877, 0.045876, 0.045872, 0.045863, 0.045844",\ + "0.079914, 0.079914, 0.079913, 0.079913, 0.079912",\ + "0.155804, 0.155804, 0.155801, 0.155793, 0.155779",\ + "0.431307, 0.431307, 0.431306, 0.431304, 0.431301",\ + "1.494119, 1.494120, 1.494121, 1.494127, 1.494137",\ + "0.045877, 0.045876, 0.045872, 0.045863, 0.045844",\ + "0.079914, 0.079914, 0.079913, 0.079913, 0.079912",\ + "0.155804, 0.155803, 0.155801, 0.155793, 0.155779",\ + "0.431307, 0.431307, 0.431306, 0.431304, 0.431301",\ + "1.494119, 1.494120, 1.494121, 1.494127, 1.494137"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_2742*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[47]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011"); + values ( "0.554088, 0.796303, 1.062117, 1.540354, 2.496829",\ + "0.588520, 0.830735, 1.096550, 1.574794, 2.531283",\ + "0.659515, 0.901730, 1.167548, 1.645811, 2.602338",\ + "0.913680, 1.155895, 1.421738, 1.900092, 2.856801",\ + "1.838864, 2.081077, 2.346923, 2.825343, 3.782184",\ + "0.641494, 0.883776, 1.149711, 1.627068, 2.582762",\ + "0.675925, 0.918208, 1.184143, 1.661508, 2.617217",\ + "0.746920, 0.989202, 1.255142, 1.732525, 2.688272",\ + "1.001085, 1.243367, 1.509332, 1.986806, 2.942735",\ + "1.926270, 2.168550, 2.434517, 2.912057, 3.868118",\ + "0.722307, 0.972564, 1.237674, 1.714689, 2.669717",\ + "0.756739, 1.006995, 1.272107, 1.749129, 2.704172",\ + "0.827734, 1.077990, 1.343105, 1.820146, 2.775227",\ + "1.081899, 1.332155, 1.597295, 2.074427, 3.029690",\ + "2.007083, 2.257337, 2.522481, 2.999678, 3.955073",\ + "0.781255, 1.037917, 1.301816, 1.778602, 2.733226",\ + "0.815687, 1.072348, 1.336248, 1.813042, 2.767681",\ + "0.886682, 1.143343, 1.407246, 1.884059, 2.838736",\ + "1.140847, 1.397507, 1.661436, 2.138340, 3.093199",\ + "2.066033, 2.322690, 2.586622, 3.063591, 4.018582",\ + "1.116786, 1.399065, 1.653774, 2.127983, 3.078682",\ + "1.151218, 1.433496, 1.688207, 2.162423, 3.113137",\ + "1.222213, 1.504490, 1.759205, 2.233440, 3.184192",\ + "1.476379, 1.758654, 2.013396, 2.487721, 3.438655",\ + "2.401570, 2.683832, 2.938582, 3.412973, 4.364038"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011"); + values ( "0.034240, 0.034243, 0.034261, 0.034303, 0.034388",\ + "0.083583, 0.083591, 0.083624, 0.083701, 0.083855",\ + "0.208066, 0.208072, 0.208099, 0.208159, 0.208278",\ + "0.693300, 0.693300, 0.693300, 0.693300, 0.693300",\ + "2.470761, 2.470782, 2.471502, 2.473964, 2.478889",\ + "0.034240, 0.034244, 0.034261, 0.034303, 0.034388",\ + "0.083583, 0.083591, 0.083625, 0.083701, 0.083855",\ + "0.208066, 0.208072, 0.208099, 0.208159, 0.208278",\ + "0.693300, 0.693300, 0.693300, 0.693300, 0.693300",\ + "2.470761, 2.470782, 2.471509, 2.473964, 2.478889",\ + "0.034240, 0.034244, 0.034261, 0.034303, 0.034388",\ + "0.083583, 0.083591, 0.083625, 0.083701, 0.083855",\ + "0.208066, 0.208073, 0.208099, 0.208159, 0.208278",\ + "0.693300, 0.693300, 0.693300, 0.693300, 0.693300",\ + "2.470761, 2.470782, 2.471509, 2.473964, 2.478889",\ + "0.034240, 0.034244, 0.034261, 0.034303, 0.034388",\ + "0.083583, 0.083591, 0.083625, 0.083701, 0.083855",\ + "0.208066, 0.208073, 0.208099, 0.208159, 0.208278",\ + "0.693300, 0.693300, 0.693300, 0.693300, 0.693300",\ + "2.470764, 2.470782, 2.471510, 2.473964, 2.478889",\ + "0.034240, 0.034245, 0.034262, 0.034304, 0.034388",\ + "0.083583, 0.083594, 0.083625, 0.083701, 0.083855",\ + "0.208066, 0.208075, 0.208100, 0.208159, 0.208278",\ + "0.693300, 0.693300, 0.693300, 0.693300, 0.693300",\ + "2.470774, 2.470782, 2.471535, 2.473974, 2.478889"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011"); + values ( "0.581124, 0.823340, 1.089156, 1.567400, 2.523887",\ + "0.623421, 0.865636, 1.131410, 1.609509, 2.565706",\ + "0.683983, 0.926199, 1.191909, 1.669792, 2.625559",\ + "0.852914, 1.095129, 1.360763, 1.838384, 2.793625",\ + "1.436165, 1.678380, 1.944001, 2.421576, 3.376727",\ + "0.668530, 0.910813, 1.176750, 1.654113, 2.609821",\ + "0.710826, 0.953109, 1.219003, 1.696222, 2.651640",\ + "0.771389, 1.013672, 1.279502, 1.756506, 2.711493",\ + "0.940320, 1.182602, 1.448355, 1.925098, 2.879559",\ + "1.523571, 1.765853, 2.031593, 2.508290, 3.462660",\ + "0.749343, 0.999600, 1.264713, 1.741735, 2.696776",\ + "0.791640, 1.041896, 1.306967, 1.783844, 2.738595",\ + "0.852202, 1.102459, 1.367465, 1.844127, 2.798448",\ + "1.021133, 1.271390, 1.536319, 2.012719, 2.966514",\ + "1.604384, 1.854641, 2.119556, 2.595911, 3.549615",\ + "0.808291, 1.064953, 1.328854, 1.805647, 2.760285",\ + "0.850588, 1.107249, 1.371108, 1.847756, 2.802104",\ + "0.911150, 1.167812, 1.431607, 1.908040, 2.861957",\ + "1.080081, 1.336743, 1.600460, 2.076632, 3.030023",\ + "1.663332, 1.919994, 2.183697, 2.659824, 3.613124",\ + "1.143822, 1.426101, 1.680813, 2.155028, 3.105741",\ + "1.186118, 1.468397, 1.723065, 2.197137, 3.147560",\ + "1.246681, 1.528960, 1.783561, 2.257420, 3.207412",\ + "1.415612, 1.697891, 1.952412, 2.426010, 3.375479",\ + "1.998863, 2.281142, 2.535649, 3.009202, 3.958580"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011"); + values ( "0.045859, 0.045859, 0.045870, 0.045908, 0.045983",\ + "0.079961, 0.079962, 0.079962, 0.079962, 0.079962",\ + "0.155685, 0.155686, 0.155686, 0.155686, 0.155686",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498064, 1.498064, 1.498064, 1.498064, 1.498064",\ + "0.045859, 0.045859, 0.045870, 0.045908, 0.045983",\ + "0.079961, 0.079962, 0.079962, 0.079962, 0.079962",\ + "0.155685, 0.155686, 0.155686, 0.155686, 0.155686",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498064, 1.498064, 1.498064, 1.498064, 1.498064",\ + "0.045859, 0.045859, 0.045870, 0.045908, 0.045983",\ + "0.079961, 0.079962, 0.079962, 0.079962, 0.079962",\ + "0.155685, 0.155686, 0.155686, 0.155686, 0.155686",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498064, 1.498064, 1.498064, 1.498064, 1.498064",\ + "0.045859, 0.045859, 0.045870, 0.045908, 0.045983",\ + "0.079961, 0.079962, 0.079962, 0.079962, 0.079962",\ + "0.155685, 0.155686, 0.155686, 0.155686, 0.155686",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498064, 1.498064, 1.498064, 1.498064, 1.498064",\ + "0.045859, 0.045859, 0.045871, 0.045908, 0.045983",\ + "0.079962, 0.079962, 0.079962, 0.079962, 0.079962",\ + "0.155685, 0.155686, 0.155686, 0.155686, 0.155686",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498064, 1.498064, 1.498064, 1.498064, 1.498064"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_2612*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[17]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011"); + values ( "0.306542, 0.508788, 0.717853, 1.042526, 1.663915",\ + "0.340106, 0.542413, 0.751464, 1.076125, 1.697497",\ + "0.411112, 0.613496, 0.822458, 1.147079, 1.768433",\ + "0.665955, 0.868524, 1.077364, 1.401917, 2.023216",\ + "1.591125, 1.794899, 2.003187, 2.327733, 2.949505",\ + "0.395283, 0.596107, 0.805134, 1.129831, 1.751269",\ + "0.428854, 0.629732, 0.838745, 1.163429, 1.784850",\ + "0.499862, 0.700815, 0.909738, 1.234384, 1.855787",\ + "0.754705, 0.955843, 1.164644, 1.489222, 2.110569",\ + "1.679862, 1.882218, 2.090468, 2.415038, 3.036858",\ + "0.484964, 0.676444, 0.885161, 1.209860, 1.831300",\ + "0.518558, 0.710069, 0.918772, 1.243458, 1.864882",\ + "0.589569, 0.781152, 0.989765, 1.314412, 1.935818",\ + "0.844412, 1.036181, 1.244671, 1.569251, 2.190600",\ + "1.769534, 1.962556, 2.170495, 2.495067, 3.116889",\ + "0.543833, 0.734313, 0.942926, 1.267362, 1.888460",\ + "0.577463, 0.767939, 0.976537, 1.300961, 1.922042",\ + "0.648577, 0.839021, 1.047530, 1.371915, 1.992978",\ + "0.903624, 1.094050, 1.302436, 1.626753, 2.247760",\ + "1.830206, 2.020424, 2.228258, 2.552570, 3.174051",\ + "0.846614, 1.039923, 1.246594, 1.570597, 2.190856",\ + "0.880244, 1.073548, 1.280205, 1.604196, 2.224438",\ + "0.951354, 1.144630, 1.351198, 1.675150, 2.295374",\ + "1.206399, 1.399658, 1.606104, 1.929988, 2.550156",\ + "2.132956, 2.326026, 2.531926, 2.855805, 3.476448"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011"); + values ( "0.023786, 0.023786, 0.023786, 0.023810, 0.023868",\ + "0.069294, 0.069294, 0.069294, 0.069316, 0.069369",\ + "0.199985, 0.199985, 0.199985, 0.199985, 0.199985",\ + "0.685151, 0.685311, 0.685321, 0.685321, 0.685321",\ + "2.446158, 2.446158, 2.446667, 2.447885, 2.450424",\ + "0.023786, 0.023786, 0.023786, 0.023810, 0.023868",\ + "0.069294, 0.069294, 0.069294, 0.069316, 0.069369",\ + "0.199985, 0.199985, 0.199985, 0.199985, 0.199985",\ + "0.685156, 0.685311, 0.685321, 0.685321, 0.685321",\ + "2.446158, 2.446158, 2.446667, 2.447885, 2.450424",\ + "0.023786, 0.023786, 0.023786, 0.023810, 0.023868",\ + "0.069294, 0.069294, 0.069294, 0.069316, 0.069369",\ + "0.199985, 0.199985, 0.199985, 0.199985, 0.199985",\ + "0.685169, 0.685311, 0.685321, 0.685321, 0.685321",\ + "2.446158, 2.446158, 2.446667, 2.447885, 2.450424",\ + "0.023786, 0.023786, 0.023786, 0.023810, 0.023869",\ + "0.069294, 0.069294, 0.069294, 0.069316, 0.069369",\ + "0.199985, 0.199985, 0.199985, 0.199985, 0.199985",\ + "0.685155, 0.685312, 0.685321, 0.685321, 0.685321",\ + "2.446158, 2.446158, 2.446668, 2.447888, 2.450430",\ + "0.023786, 0.023786, 0.023786, 0.023810, 0.023869",\ + "0.069294, 0.069294, 0.069294, 0.069316, 0.069370",\ + "0.199985, 0.199985, 0.199985, 0.199985, 0.199985",\ + "0.685173, 0.685316, 0.685321, 0.685321, 0.685321",\ + "2.446158, 2.446158, 2.446668, 2.447891, 2.450438"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011"); + values ( "0.300762, 0.504583, 0.713270, 1.038101, 1.660218",\ + "0.333089, 0.537036, 0.745749, 1.070675, 1.693005",\ + "0.383451, 0.587349, 0.796071, 1.121057, 1.743526",\ + "0.544532, 0.748090, 0.956809, 1.281806, 1.904306",\ + "1.125564, 1.330456, 1.540080, 1.865115, 2.486899",\ + "0.389512, 0.591901, 0.800551, 1.125406, 1.747571",\ + "0.421839, 0.624354, 0.833030, 1.157980, 1.780358",\ + "0.472201, 0.674668, 0.883352, 1.208362, 1.830879",\ + "0.633282, 0.835409, 1.044090, 1.369112, 1.991659",\ + "1.214288, 1.417775, 1.627361, 1.952420, 2.574253",\ + "0.479218, 0.672239, 0.880578, 1.205435, 1.827603",\ + "0.511548, 0.704692, 0.913057, 1.238009, 1.860390",\ + "0.561908, 0.755005, 0.963379, 1.288391, 1.910911",\ + "0.722989, 0.915746, 1.124117, 1.449140, 2.071691",\ + "1.303923, 1.498112, 1.707387, 2.032449, 2.654284",\ + "0.539760, 0.730108, 0.938342, 1.262939, 1.884765",\ + "0.572206, 0.762561, 0.970821, 1.295513, 1.917552",\ + "0.622521, 0.812874, 1.021143, 1.345895, 1.968074",\ + "0.783248, 0.973615, 1.181881, 1.506644, 2.128853",\ + "1.365347, 1.555982, 1.765154, 2.089952, 2.711445",\ + "0.842526, 1.035714, 1.242010, 1.566174, 2.187163",\ + "0.874973, 1.068167, 1.274489, 1.598749, 2.219951",\ + "0.925287, 1.118480, 1.324811, 1.649131, 2.270473",\ + "1.086016, 1.279222, 1.485549, 1.809880, 2.431253",\ + "1.668147, 1.861596, 2.068822, 2.393188, 3.013843"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011"); + values ( "0.030099, 0.030091, 0.030091, 0.030077, 0.030045",\ + "0.059380, 0.059246, 0.059238, 0.059238, 0.059238",\ + "0.131641, 0.131636, 0.131630, 0.131627, 0.131627",\ + "0.418133, 0.418133, 0.418133, 0.418133, 0.418133",\ + "1.484352, 1.482541, 1.482428, 1.482428, 1.482428",\ + "0.030099, 0.030091, 0.030091, 0.030077, 0.030045",\ + "0.059376, 0.059246, 0.059238, 0.059238, 0.059238",\ + "0.131641, 0.131636, 0.131630, 0.131627, 0.131627",\ + "0.418133, 0.418133, 0.418133, 0.418133, 0.418133",\ + "1.484298, 1.482541, 1.482428, 1.482428, 1.482428",\ + "0.030098, 0.030091, 0.030091, 0.030077, 0.030045",\ + "0.059366, 0.059246, 0.059238, 0.059238, 0.059238",\ + "0.131641, 0.131636, 0.131630, 0.131627, 0.131627",\ + "0.418133, 0.418133, 0.418133, 0.418133, 0.418133",\ + "1.484152, 1.482541, 1.482428, 1.482428, 1.482428",\ + "0.030099, 0.030091, 0.030091, 0.030077, 0.030045",\ + "0.059378, 0.059246, 0.059238, 0.059238, 0.059238",\ + "0.131641, 0.131636, 0.131630, 0.131627, 0.131627",\ + "0.418133, 0.418133, 0.418133, 0.418133, 0.418133",\ + "1.484315, 1.482534, 1.482428, 1.482428, 1.482428",\ + "0.030098, 0.030091, 0.030091, 0.030077, 0.030045",\ + "0.059362, 0.059242, 0.059238, 0.059238, 0.059238",\ + "0.131641, 0.131636, 0.131630, 0.131627, 0.131627",\ + "0.418133, 0.418133, 0.418133, 0.418133, 0.418133",\ + "1.484105, 1.482485, 1.482428, 1.482428, 1.482428"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_min_2559*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[18]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.534853, 0.754941, 0.932292, 1.220792, 1.781149",\ + "0.576549, 0.796638, 0.973989, 1.262489, 1.822845",\ + "0.652730, 0.872819, 1.050170, 1.338670, 1.899026",\ + "0.908126, 1.128215, 1.305566, 1.594066, 2.154422",\ + "1.832504, 2.052592, 2.229943, 2.518443, 3.078799",\ + "0.623250, 0.842260, 1.019573, 1.308098, 1.868502",\ + "0.664946, 0.883956, 1.061270, 1.349794, 1.910198",\ + "0.741127, 0.960137, 1.137451, 1.425975, 1.986380",\ + "0.996523, 1.215533, 1.392847, 1.681371, 2.241775",\ + "1.920900, 2.139910, 2.317224, 2.605748, 3.166152",\ + "0.712601, 0.922592, 1.099600, 1.388126, 1.948534",\ + "0.754297, 0.964289, 1.141297, 1.429822, 1.990230",\ + "0.830478, 1.040470, 1.217478, 1.506004, 2.066411",\ + "1.085874, 1.295865, 1.472873, 1.761399, 2.321807",\ + "2.010251, 2.220243, 2.397251, 2.685777, 3.246184",\ + "0.776250, 0.980408, 1.157292, 1.445555, 2.005549",\ + "0.817947, 1.022105, 1.198989, 1.487252, 2.047245",\ + "0.894128, 1.098286, 1.275170, 1.563433, 2.123426",\ + "1.149523, 1.353682, 1.530566, 1.818829, 2.378822",\ + "2.073901, 2.278059, 2.454943, 2.743206, 3.303199",\ + "1.107332, 1.285624, 1.460948, 1.748727, 2.307770",\ + "1.149029, 1.327321, 1.502644, 1.790423, 2.349466",\ + "1.225210, 1.403502, 1.578825, 1.866605, 2.425647",\ + "1.480606, 1.658898, 1.834221, 2.122000, 2.681043",\ + "2.404983, 2.583275, 2.758598, 3.046378, 3.605420"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\ + "0.199415, 0.199415, 0.199415, 0.199415, 0.199415",\ + "0.685787, 0.685787, 0.685787, 0.685787, 0.685787",\ + "2.455201, 2.455201, 2.455201, 2.455201, 2.455201",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\ + "0.199415, 0.199415, 0.199415, 0.199415, 0.199415",\ + "0.685787, 0.685787, 0.685787, 0.685787, 0.685787",\ + "2.455201, 2.455201, 2.455201, 2.455201, 2.455201",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\ + "0.199415, 0.199415, 0.199415, 0.199415, 0.199415",\ + "0.685787, 0.685787, 0.685787, 0.685787, 0.685787",\ + "2.455201, 2.455201, 2.455201, 2.455201, 2.455201",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\ + "0.199415, 0.199415, 0.199415, 0.199415, 0.199415",\ + "0.685787, 0.685787, 0.685787, 0.685787, 0.685787",\ + "2.455201, 2.455201, 2.455201, 2.455201, 2.455201",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\ + "0.199415, 0.199415, 0.199415, 0.199415, 0.199415",\ + "0.685787, 0.685787, 0.685787, 0.685787, 0.685787",\ + "2.455201, 2.455201, 2.455201, 2.455201, 2.455201"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.555098, 0.775186, 0.952537, 1.241037, 1.801394",\ + "0.587348, 0.807436, 0.984787, 1.273287, 1.833643",\ + "0.637660, 0.857748, 1.035099, 1.323599, 1.883955",\ + "0.798324, 1.018412, 1.195763, 1.484263, 2.044619",\ + "1.379457, 1.599546, 1.776897, 2.065397, 2.625753",\ + "0.643495, 0.862505, 1.039818, 1.328343, 1.888747",\ + "0.675744, 0.894754, 1.072068, 1.360592, 1.920997",\ + "0.726057, 0.945067, 1.122380, 1.410905, 1.971309",\ + "0.886720, 1.105730, 1.283044, 1.571568, 2.131973",\ + "1.467854, 1.686864, 1.864178, 2.152702, 2.713106",\ + "0.732846, 0.942837, 1.119845, 1.408371, 1.968779",\ + "0.765095, 0.975087, 1.152095, 1.440621, 2.001028",\ + "0.815408, 1.025399, 1.202407, 1.490933, 2.051341",\ + "0.976071, 1.186063, 1.363071, 1.651597, 2.212004",\ + "1.557205, 1.767197, 1.944205, 2.232730, 2.793138",\ + "0.796495, 1.000653, 1.177537, 1.465801, 2.025794",\ + "0.828745, 1.032903, 1.209787, 1.498050, 2.058043",\ + "0.879057, 1.083215, 1.260099, 1.548362, 2.108356",\ + "1.039721, 1.243879, 1.420763, 1.709026, 2.269019",\ + "1.620855, 1.825013, 2.001897, 2.290160, 2.850153",\ + "1.127577, 1.305869, 1.481193, 1.768972, 2.328015",\ + "1.159827, 1.338119, 1.513443, 1.801222, 2.360265",\ + "1.210139, 1.388431, 1.563755, 1.851534, 2.410577",\ + "1.370803, 1.549095, 1.724418, 2.012197, 2.571240",\ + "1.951937, 2.130229, 2.305552, 2.593331, 3.152374"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131486, 0.131486, 0.131486, 0.131486, 0.131486",\ + "0.419471, 0.419471, 0.419471, 0.419471, 0.419471",\ + "1.482977, 1.482977, 1.482976, 1.482976, 1.482976",\ + "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131486, 0.131486, 0.131486, 0.131486, 0.131486",\ + "0.419471, 0.419471, 0.419471, 0.419471, 0.419471",\ + "1.482977, 1.482977, 1.482976, 1.482976, 1.482976",\ + "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131486, 0.131486, 0.131486, 0.131486, 0.131486",\ + "0.419471, 0.419471, 0.419471, 0.419471, 0.419471",\ + "1.482977, 1.482977, 1.482976, 1.482976, 1.482976",\ + "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131486, 0.131486, 0.131486, 0.131486, 0.131486",\ + "0.419471, 0.419471, 0.419471, 0.419471, 0.419471",\ + "1.482977, 1.482977, 1.482976, 1.482976, 1.482976",\ + "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131486, 0.131486, 0.131486, 0.131486, 0.131486",\ + "0.419471, 0.419471, 0.419471, 0.419471, 0.419471",\ + "1.482977, 1.482977, 1.482976, 1.482976, 1.482976"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_min_2577*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[23]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011"); + values ( "0.256885, 0.492153, 0.681988, 0.987164, 1.577680",\ + "0.290472, 0.525767, 0.715632, 1.020810, 1.611303",\ + "0.361355, 0.596664, 0.786663, 1.091855, 1.682256",\ + "0.616370, 0.851426, 1.041598, 1.346846, 1.937220",\ + "1.541773, 1.775412, 1.968861, 2.274571, 2.863136",\ + "0.345363, 0.579471, 0.769269, 1.074469, 1.665033",\ + "0.378951, 0.613085, 0.802913, 1.108115, 1.698656",\ + "0.449834, 0.683983, 0.873944, 1.179160, 1.769609",\ + "0.704852, 0.938744, 1.128879, 1.434151, 2.024573",\ + "1.630270, 1.862731, 2.056142, 2.361876, 2.950490",\ + "0.434929, 0.659804, 0.849296, 1.154498, 1.745065",\ + "0.468520, 0.693418, 0.882940, 1.188143, 1.778688",\ + "0.539403, 0.764315, 0.953971, 1.259189, 1.849641",\ + "0.794431, 1.019077, 1.208906, 1.514180, 2.104605",\ + "1.719892, 1.943063, 2.136169, 2.441904, 3.030521",\ + "0.498770, 0.717639, 0.907017, 1.211964, 1.802153",\ + "0.532364, 0.751252, 0.940661, 1.245610, 1.835775",\ + "0.603247, 0.822149, 1.011693, 1.316654, 1.906729",\ + "0.858284, 1.076910, 1.266629, 1.571645, 2.161693",\ + "1.783785, 2.000890, 2.193899, 2.499368, 3.087604",\ + "0.836421, 1.022987, 1.210677, 1.515166, 2.104462",\ + "0.870034, 1.056600, 1.244321, 1.548812, 2.138084",\ + "0.940914, 1.127492, 1.315353, 1.619857, 2.209037",\ + "1.196012, 1.382245, 1.570289, 1.874848, 2.464001",\ + "2.121767, 2.306184, 2.497561, 2.802569, 3.389907"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011"); + values ( "0.023821, 0.023821, 0.023821, 0.023833, 0.023862",\ + "0.069303, 0.069303, 0.069343, 0.069357, 0.069357",\ + "0.199561, 0.199561, 0.199561, 0.199561, 0.199561",\ + "0.684891, 0.684891, 0.685012, 0.685055, 0.685055",\ + "2.453468, 2.453468, 2.454037, 2.454505, 2.455152",\ + "0.023821, 0.023821, 0.023821, 0.023833, 0.023862",\ + "0.069303, 0.069303, 0.069343, 0.069357, 0.069357",\ + "0.199561, 0.199561, 0.199561, 0.199561, 0.199561",\ + "0.684891, 0.684891, 0.685012, 0.685055, 0.685055",\ + "2.453468, 2.453468, 2.454037, 2.454505, 2.455152",\ + "0.023821, 0.023821, 0.023821, 0.023833, 0.023862",\ + "0.069303, 0.069303, 0.069343, 0.069357, 0.069357",\ + "0.199561, 0.199561, 0.199561, 0.199561, 0.199561",\ + "0.684891, 0.684891, 0.685012, 0.685055, 0.685055",\ + "2.453468, 2.453468, 2.454037, 2.454505, 2.455152",\ + "0.023821, 0.023821, 0.023821, 0.023833, 0.023862",\ + "0.069303, 0.069303, 0.069343, 0.069357, 0.069357",\ + "0.199561, 0.199561, 0.199561, 0.199561, 0.199561",\ + "0.684891, 0.684891, 0.685012, 0.685055, 0.685055",\ + "2.453468, 2.453468, 2.454039, 2.454505, 2.455154",\ + "0.023821, 0.023821, 0.023821, 0.023833, 0.023862",\ + "0.069303, 0.069303, 0.069343, 0.069357, 0.069357",\ + "0.199561, 0.199561, 0.199561, 0.199561, 0.199561",\ + "0.684891, 0.684891, 0.685012, 0.685055, 0.685055",\ + "2.453468, 2.453468, 2.454039, 2.454506, 2.455156"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011"); + values ( "0.251684, 0.487150, 0.676755, 0.981685, 1.571796",\ + "0.284092, 0.519474, 0.709133, 1.014097, 1.604246",\ + "0.334486, 0.569802, 0.759438, 1.064423, 1.654643",\ + "0.495295, 0.730692, 0.920083, 1.225063, 1.815495",\ + "1.076466, 1.311284, 1.500832, 1.805703, 2.395659",\ + "0.340147, 0.574468, 0.764036, 1.068990, 1.659150",\ + "0.372555, 0.606792, 0.796414, 1.101402, 1.691600",\ + "0.422950, 0.657120, 0.846719, 1.151728, 1.741997",\ + "0.583764, 0.818010, 1.007364, 1.312368, 1.902848",\ + "1.164940, 1.398602, 1.588113, 1.893008, 2.483012",\ + "0.429671, 0.654801, 0.844063, 1.149019, 1.739182",\ + "0.462080, 0.687125, 0.876441, 1.181431, 1.771631",\ + "0.512476, 0.737453, 0.926746, 1.231757, 1.822028",\ + "0.673307, 0.898343, 1.087391, 1.392396, 1.982880",\ + "1.254498, 1.478935, 1.668140, 1.973037, 2.563044",\ + "0.493473, 0.712635, 0.901784, 1.206484, 1.796268",\ + "0.525883, 0.744960, 0.934162, 1.238896, 1.828718",\ + "0.576281, 0.795287, 0.984467, 1.289223, 1.879116",\ + "0.737126, 0.956178, 1.145111, 1.449862, 2.039968",\ + "1.318331, 1.536764, 1.725861, 2.030502, 2.620130",\ + "0.830874, 1.017982, 1.205444, 1.509686, 2.098576",\ + "0.863289, 1.050307, 1.237822, 1.542099, 2.131026",\ + "0.913697, 1.100635, 1.288127, 1.592425, 2.181424",\ + "1.074636, 1.261533, 1.448771, 1.753065, 2.342276",\ + "1.655932, 1.842073, 2.029521, 2.333704, 2.922437"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011"); + values ( "0.030092, 0.030092, 0.030092, 0.030170, 0.030363",\ + "0.059437, 0.059437, 0.059437, 0.059474, 0.059565",\ + "0.131608, 0.131608, 0.131661, 0.131712, 0.131790",\ + "0.417862, 0.417862, 0.417862, 0.417990, 0.418302",\ + "1.478309, 1.478309, 1.478309, 1.478309, 1.478309",\ + "0.030092, 0.030092, 0.030092, 0.030170, 0.030363",\ + "0.059437, 0.059437, 0.059437, 0.059474, 0.059565",\ + "0.131608, 0.131608, 0.131661, 0.131712, 0.131790",\ + "0.417862, 0.417862, 0.417862, 0.417990, 0.418302",\ + "1.478309, 1.478309, 1.478309, 1.478309, 1.478309",\ + "0.030092, 0.030092, 0.030092, 0.030170, 0.030363",\ + "0.059437, 0.059437, 0.059437, 0.059474, 0.059565",\ + "0.131608, 0.131608, 0.131661, 0.131712, 0.131790",\ + "0.417862, 0.417862, 0.417862, 0.417990, 0.418302",\ + "1.478309, 1.478309, 1.478309, 1.478309, 1.478309",\ + "0.030092, 0.030092, 0.030092, 0.030170, 0.030363",\ + "0.059437, 0.059437, 0.059437, 0.059474, 0.059565",\ + "0.131608, 0.131608, 0.131661, 0.131712, 0.131790",\ + "0.417862, 0.417862, 0.417862, 0.417990, 0.418303",\ + "1.478309, 1.478309, 1.478309, 1.478309, 1.478309",\ + "0.030092, 0.030092, 0.030092, 0.030171, 0.030364",\ + "0.059437, 0.059437, 0.059437, 0.059474, 0.059565",\ + "0.131608, 0.131608, 0.131661, 0.131712, 0.131790",\ + "0.417862, 0.417862, 0.417862, 0.417990, 0.418303",\ + "1.478309, 1.478309, 1.478309, 1.478309, 1.478309"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_min_2320*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[24]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011"); + values ( "0.514526, 0.752428, 0.939979, 1.239804, 1.819405",\ + "0.556223, 0.794124, 0.981676, 1.281500, 1.861101",\ + "0.632404, 0.870306, 1.057857, 1.357682, 1.937282",\ + "0.887800, 1.125701, 1.313253, 1.613077, 2.192678",\ + "1.812177, 2.050079, 2.237630, 2.537455, 3.117055",\ + "0.602829, 0.839746, 1.027260, 1.327109, 1.906758",\ + "0.644526, 0.881442, 1.068957, 1.368805, 1.948454",\ + "0.720707, 0.957623, 1.145138, 1.444987, 2.024636",\ + "0.976103, 1.213019, 1.400534, 1.700382, 2.280031",\ + "1.900480, 2.137396, 2.324911, 2.624760, 3.204408",\ + "0.692380, 0.920074, 1.107287, 1.407137, 1.986790",\ + "0.734076, 0.961771, 1.148984, 1.448834, 2.028486",\ + "0.810257, 1.037952, 1.225165, 1.525015, 2.104667",\ + "1.065653, 1.293347, 1.480561, 1.780411, 2.360063",\ + "1.990030, 2.217725, 2.404938, 2.704788, 3.284440",\ + "0.756421, 0.977914, 1.165004, 1.464591, 2.043853",\ + "0.798118, 1.019611, 1.206700, 1.506287, 2.085550",\ + "0.874299, 1.095792, 1.282882, 1.582469, 2.161731",\ + "1.129694, 1.351188, 1.538277, 1.837864, 2.417127",\ + "2.054072, 2.275565, 2.462655, 2.762241, 3.341504",\ + "1.095322, 1.283284, 1.468662, 1.767782, 2.346133",\ + "1.137018, 1.324980, 1.510358, 1.809478, 2.387829",\ + "1.213199, 1.401161, 1.586540, 1.885659, 2.464011",\ + "1.468595, 1.656557, 1.841935, 2.141055, 2.719406",\ + "2.392972, 2.580935, 2.766313, 3.065432, 3.643783"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011"); + values ( "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\ + "0.199415, 0.199415, 0.199415, 0.199415, 0.199415",\ + "0.685787, 0.685787, 0.685787, 0.685787, 0.685786",\ + "2.455201, 2.455201, 2.455201, 2.455201, 2.455201",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\ + "0.199415, 0.199415, 0.199415, 0.199415, 0.199415",\ + "0.685787, 0.685787, 0.685787, 0.685787, 0.685786",\ + "2.455201, 2.455201, 2.455201, 2.455201, 2.455201",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\ + "0.199415, 0.199415, 0.199415, 0.199415, 0.199415",\ + "0.685787, 0.685787, 0.685787, 0.685787, 0.685786",\ + "2.455201, 2.455201, 2.455201, 2.455201, 2.455201",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\ + "0.199415, 0.199415, 0.199415, 0.199415, 0.199415",\ + "0.685787, 0.685787, 0.685787, 0.685787, 0.685786",\ + "2.455201, 2.455201, 2.455201, 2.455201, 2.455201",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\ + "0.199415, 0.199415, 0.199415, 0.199415, 0.199415",\ + "0.685787, 0.685787, 0.685787, 0.685787, 0.685786",\ + "2.455201, 2.455201, 2.455201, 2.455201, 2.455201"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011"); + values ( "0.534772, 0.772673, 0.960224, 1.260049, 1.839650",\ + "0.567021, 0.804923, 0.992474, 1.292299, 1.871899",\ + "0.617333, 0.855235, 1.042786, 1.342611, 1.922212",\ + "0.777997, 1.015898, 1.203450, 1.503274, 2.082875",\ + "1.359131, 1.597032, 1.784584, 2.084409, 2.664009",\ + "0.623075, 0.859991, 1.047505, 1.347354, 1.927003",\ + "0.655324, 0.892240, 1.079755, 1.379604, 1.959253",\ + "0.705636, 0.942553, 1.130067, 1.429916, 2.009565",\ + "0.866300, 1.103216, 1.290731, 1.590580, 2.170229",\ + "1.447434, 1.684350, 1.871865, 2.171714, 2.751363",\ + "0.712625, 0.940319, 1.127532, 1.427382, 2.007035",\ + "0.744874, 0.972569, 1.159782, 1.459632, 2.039284",\ + "0.795187, 1.022881, 1.210094, 1.509944, 2.089597",\ + "0.955850, 1.183545, 1.370758, 1.670608, 2.250260",\ + "1.536984, 1.764679, 1.951892, 2.251742, 2.831394",\ + "0.776666, 0.998159, 1.185249, 1.484836, 2.064098",\ + "0.808916, 1.030409, 1.217499, 1.517086, 2.096348",\ + "0.859228, 1.080721, 1.267811, 1.567398, 2.146660",\ + "1.019892, 1.241385, 1.428475, 1.728061, 2.307324",\ + "1.601026, 1.822519, 2.009609, 2.309195, 2.888458",\ + "1.115567, 1.303529, 1.488907, 1.788027, 2.366378",\ + "1.147816, 1.335778, 1.521157, 1.820276, 2.398628",\ + "1.198129, 1.386091, 1.571469, 1.870589, 2.448940",\ + "1.358792, 1.546754, 1.732133, 2.031252, 2.609604",\ + "1.939926, 2.127888, 2.313267, 2.612386, 3.190738"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011"); + values ( "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131486, 0.131486, 0.131486, 0.131486, 0.131486",\ + "0.419471, 0.419471, 0.419471, 0.419471, 0.419471",\ + "1.482977, 1.482976, 1.482976, 1.482976, 1.482976",\ + "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131486, 0.131486, 0.131486, 0.131486, 0.131486",\ + "0.419471, 0.419471, 0.419471, 0.419471, 0.419471",\ + "1.482977, 1.482976, 1.482976, 1.482976, 1.482976",\ + "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131486, 0.131486, 0.131486, 0.131486, 0.131486",\ + "0.419471, 0.419471, 0.419471, 0.419471, 0.419471",\ + "1.482977, 1.482976, 1.482976, 1.482976, 1.482976",\ + "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131486, 0.131486, 0.131486, 0.131486, 0.131486",\ + "0.419471, 0.419471, 0.419471, 0.419471, 0.419471",\ + "1.482977, 1.482976, 1.482976, 1.482976, 1.482976",\ + "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131486, 0.131486, 0.131486, 0.131486, 0.131486",\ + "0.419471, 0.419471, 0.419471, 0.419471, 0.419471",\ + "1.482976, 1.482976, 1.482976, 1.482976, 1.482976"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_min_2351*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[26]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011"); + values ( "0.430447, 0.665884, 0.855738, 1.160934, 1.751473",\ + "0.472143, 0.707581, 0.897435, 1.202631, 1.793169",\ + "0.548324, 0.783762, 0.973616, 1.278812, 1.869350",\ + "0.803720, 1.039157, 1.229011, 1.534208, 2.124746",\ + "1.728097, 1.963542, 2.153391, 2.458586, 3.049126",\ + "0.518928, 0.753203, 0.943019, 1.248240, 1.838826",\ + "0.560625, 0.794899, 0.984715, 1.289936, 1.880523",\ + "0.636806, 0.871080, 1.060897, 1.366117, 1.956704",\ + "0.892201, 1.126475, 1.316292, 1.621513, 2.212099",\ + "1.816579, 2.050861, 2.240672, 2.545891, 3.136479",\ + "0.608483, 0.833536, 1.023046, 1.328268, 1.918858",\ + "0.650179, 0.875232, 1.064742, 1.369964, 1.960554",\ + "0.726361, 0.951413, 1.140924, 1.446146, 2.036736",\ + "0.981756, 1.206808, 1.396319, 1.701541, 2.292131",\ + "1.906135, 2.131194, 2.320698, 2.625919, 3.216511",\ + "0.672303, 0.891371, 1.080767, 1.385734, 1.975946",\ + "0.713999, 0.933067, 1.122464, 1.427431, 2.017642",\ + "0.790181, 1.009248, 1.198645, 1.503612, 2.093823",\ + "1.045576, 1.264643, 1.454041, 1.759007, 2.349219",\ + "1.969955, 2.189029, 2.378420, 2.683385, 3.273599",\ + "1.009821, 1.196720, 1.384428, 1.688937, 2.278255",\ + "1.051517, 1.238416, 1.426124, 1.730633, 2.319951",\ + "1.127699, 1.314597, 1.502305, 1.806814, 2.396132",\ + "1.383094, 1.569992, 1.757701, 2.062210, 2.651528",\ + "2.307477, 2.494378, 2.682080, 2.986588, 3.575908"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011"); + values ( "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\ + "0.199414, 0.199414, 0.199414, 0.199415, 0.199419",\ + "0.685786, 0.685786, 0.685786, 0.685787, 0.685790",\ + "2.455200, 2.455200, 2.455201, 2.455201, 2.455201",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\ + "0.199414, 0.199414, 0.199414, 0.199415, 0.199419",\ + "0.685786, 0.685786, 0.685786, 0.685787, 0.685790",\ + "2.455200, 2.455200, 2.455201, 2.455201, 2.455201",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\ + "0.199414, 0.199414, 0.199414, 0.199415, 0.199419",\ + "0.685786, 0.685786, 0.685786, 0.685787, 0.685790",\ + "2.455200, 2.455200, 2.455201, 2.455201, 2.455201",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\ + "0.199414, 0.199414, 0.199414, 0.199415, 0.199419",\ + "0.685786, 0.685786, 0.685786, 0.685787, 0.685790",\ + "2.455200, 2.455200, 2.455201, 2.455201, 2.455201",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\ + "0.199414, 0.199414, 0.199414, 0.199415, 0.199419",\ + "0.685786, 0.685786, 0.685786, 0.685787, 0.685790",\ + "2.455200, 2.455200, 2.455201, 2.455201, 2.455201"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011"); + values ( "0.450692, 0.686130, 0.875983, 1.181180, 1.771718",\ + "0.482941, 0.718379, 0.908233, 1.213429, 1.803968",\ + "0.533254, 0.768692, 0.958545, 1.263741, 1.854280",\ + "0.693917, 0.929356, 1.119209, 1.424405, 2.014944",\ + "1.275051, 1.510488, 1.700342, 2.005539, 2.596077",\ + "0.539173, 0.773448, 0.963264, 1.268485, 1.859071",\ + "0.571423, 0.805697, 0.995514, 1.300734, 1.891321",\ + "0.621735, 0.856010, 1.045826, 1.351047, 1.941633",\ + "0.782399, 1.016674, 1.206490, 1.511710, 2.102297",\ + "1.363533, 1.597806, 1.787623, 2.092844, 2.683430",\ + "0.628728, 0.853781, 1.043291, 1.348513, 1.939103",\ + "0.660978, 0.886030, 1.075541, 1.380763, 1.971353",\ + "0.711290, 0.936343, 1.125853, 1.431075, 2.021665",\ + "0.871954, 1.097007, 1.286517, 1.591739, 2.182329",\ + "1.453087, 1.678139, 1.867650, 2.172873, 2.763462",\ + "0.692548, 0.911616, 1.101013, 1.405979, 1.996191",\ + "0.724798, 0.943865, 1.133262, 1.438229, 2.028440",\ + "0.775110, 0.994178, 1.183574, 1.488541, 2.078753",\ + "0.935774, 1.154842, 1.344238, 1.649205, 2.239417",\ + "1.516907, 1.735974, 1.925371, 2.230339, 2.820550",\ + "1.030066, 1.216965, 1.404673, 1.709182, 2.298500",\ + "1.062316, 1.249214, 1.436922, 1.741432, 2.330750",\ + "1.112628, 1.299527, 1.487235, 1.791744, 2.381062",\ + "1.273292, 1.460191, 1.647898, 1.952407, 2.541725",\ + "1.854424, 2.041323, 2.229032, 2.533541, 3.122859"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011"); + values ( "0.029705, 0.029705, 0.029705, 0.029705, 0.029706",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131485, 0.131485, 0.131485, 0.131486, 0.131486",\ + "0.419455, 0.419455, 0.419455, 0.419455, 0.419455",\ + "1.482976, 1.482976, 1.482976, 1.482977, 1.482979",\ + "0.029705, 0.029705, 0.029705, 0.029705, 0.029706",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131485, 0.131485, 0.131485, 0.131486, 0.131486",\ + "0.419455, 0.419455, 0.419455, 0.419455, 0.419455",\ + "1.482976, 1.482976, 1.482976, 1.482977, 1.482979",\ + "0.029705, 0.029705, 0.029705, 0.029705, 0.029706",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131485, 0.131485, 0.131485, 0.131486, 0.131486",\ + "0.419455, 0.419455, 0.419455, 0.419455, 0.419455",\ + "1.482976, 1.482976, 1.482976, 1.482977, 1.482979",\ + "0.029705, 0.029705, 0.029705, 0.029705, 0.029706",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131485, 0.131485, 0.131485, 0.131486, 0.131486",\ + "0.419455, 0.419455, 0.419455, 0.419455, 0.419455",\ + "1.482976, 1.482976, 1.482976, 1.482977, 1.482979",\ + "0.029705, 0.029705, 0.029705, 0.029705, 0.029706",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131485, 0.131485, 0.131485, 0.131486, 0.131486",\ + "0.419455, 0.419455, 0.419455, 0.419455, 0.419455",\ + "1.482976, 1.482976, 1.482976, 1.482977, 1.482979"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_min_2670*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[28]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.408175, 0.641513, 0.827140, 1.126924, 1.707803",\ + "0.449871, 0.683209, 0.868836, 1.168620, 1.749499",\ + "0.526051, 0.759389, 0.945016, 1.244800, 1.825679",\ + "0.781441, 1.014779, 1.200407, 1.500191, 2.081069",\ + "1.705890, 1.939226, 2.124851, 2.424636, 3.005520",\ + "0.496580, 0.728832, 0.914421, 1.214229, 1.795156",\ + "0.538276, 0.770527, 0.956117, 1.255925, 1.836852",\ + "0.614456, 0.846708, 1.032297, 1.332105, 1.913032",\ + "0.869846, 1.102098, 1.287688, 1.587496, 2.168422",\ + "1.794296, 2.026545, 2.212132, 2.511941, 3.092873",\ + "0.585662, 0.809167, 0.994448, 1.294258, 1.875188",\ + "0.627357, 0.850863, 1.036144, 1.335954, 1.916884",\ + "0.703538, 0.927043, 1.112324, 1.412134, 1.993064",\ + "0.958928, 1.182433, 1.367714, 1.667524, 2.248454",\ + "1.883377, 2.106880, 2.292159, 2.591970, 3.172904",\ + "0.648932, 0.866998, 1.052159, 1.351712, 1.932252",\ + "0.690627, 0.908694, 1.093855, 1.393408, 1.973947",\ + "0.766807, 0.984874, 1.170035, 1.469588, 2.050128",\ + "1.022198, 1.240264, 1.425425, 1.724978, 2.305518",\ + "1.946647, 2.164711, 2.349869, 2.649424, 3.229968",\ + "0.982958, 1.172329, 1.355818, 1.654905, 2.234531",\ + "1.024654, 1.214025, 1.397514, 1.696600, 2.276227",\ + "1.100834, 1.290205, 1.473694, 1.772781, 2.352407",\ + "1.356225, 1.545595, 1.729084, 2.028171, 2.607797",\ + "2.280672, 2.470042, 2.653529, 2.952617, 3.532248"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070075, 0.070075, 0.070075, 0.070075, 0.070076",\ + "0.199411, 0.199411, 0.199411, 0.199411, 0.199413",\ + "0.685859, 0.685859, 0.685859, 0.685862, 0.685867",\ + "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070075, 0.070075, 0.070075, 0.070075, 0.070076",\ + "0.199411, 0.199411, 0.199411, 0.199411, 0.199413",\ + "0.685859, 0.685859, 0.685859, 0.685862, 0.685867",\ + "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070075, 0.070075, 0.070075, 0.070075, 0.070076",\ + "0.199411, 0.199411, 0.199411, 0.199411, 0.199413",\ + "0.685859, 0.685859, 0.685859, 0.685862, 0.685867",\ + "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070075, 0.070075, 0.070075, 0.070075, 0.070076",\ + "0.199411, 0.199411, 0.199411, 0.199411, 0.199413",\ + "0.685859, 0.685859, 0.685859, 0.685862, 0.685867",\ + "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070075, 0.070075, 0.070075, 0.070075, 0.070076",\ + "0.199411, 0.199411, 0.199411, 0.199411, 0.199413",\ + "0.685859, 0.685859, 0.685859, 0.685862, 0.685867",\ + "2.455194, 2.455194, 2.455194, 2.455194, 2.455194"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.428422, 0.661761, 0.847388, 1.147172, 1.728051",\ + "0.460669, 0.694007, 0.879634, 1.179418, 1.760297",\ + "0.510985, 0.744323, 0.929950, 1.229734, 1.810613",\ + "0.671649, 0.904987, 1.090614, 1.390398, 1.971277",\ + "1.252766, 1.486104, 1.671732, 1.971516, 2.552394",\ + "0.516828, 0.749079, 0.934668, 1.234477, 1.815404",\ + "0.549074, 0.781326, 0.966915, 1.266723, 1.847650",\ + "0.599390, 0.831641, 1.017231, 1.317039, 1.897966",\ + "0.760054, 0.992305, 1.177894, 1.477703, 2.058630",\ + "1.341171, 1.573423, 1.759013, 2.058821, 2.639747",\ + "0.605909, 0.829414, 1.014695, 1.314505, 1.895436",\ + "0.638156, 0.861661, 1.046942, 1.346752, 1.927682",\ + "0.688472, 0.911977, 1.097257, 1.397068, 1.977998",\ + "0.849135, 1.072640, 1.257921, 1.557731, 2.138662",\ + "1.430253, 1.653758, 1.839040, 2.138849, 2.719779",\ + "0.669179, 0.887245, 1.072406, 1.371959, 1.952499",\ + "0.701426, 0.919492, 1.104653, 1.404206, 1.984746",\ + "0.751741, 0.969808, 1.154969, 1.454522, 2.035062",\ + "0.912405, 1.130471, 1.315632, 1.615185, 2.195725",\ + "1.493523, 1.711589, 1.896750, 2.196303, 2.776842",\ + "1.003206, 1.192577, 1.376065, 1.675152, 2.254779",\ + "1.035452, 1.224823, 1.408312, 1.707399, 2.287025",\ + "1.085768, 1.275139, 1.458628, 1.757715, 2.337341",\ + "1.246432, 1.435803, 1.619291, 1.918378, 2.498005",\ + "1.827550, 2.016920, 2.200410, 2.499496, 3.079122"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.029703, 0.029703, 0.029703, 0.029704, 0.029704",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\ + "0.419470, 0.419470, 0.419470, 0.419470, 0.419470",\ + "1.483040, 1.483040, 1.483040, 1.483042, 1.483046",\ + "0.029703, 0.029703, 0.029703, 0.029704, 0.029704",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\ + "0.419470, 0.419470, 0.419470, 0.419470, 0.419470",\ + "1.483040, 1.483040, 1.483040, 1.483042, 1.483046",\ + "0.029703, 0.029703, 0.029703, 0.029704, 0.029704",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\ + "0.419470, 0.419470, 0.419470, 0.419470, 0.419470",\ + "1.483040, 1.483040, 1.483040, 1.483042, 1.483046",\ + "0.029703, 0.029703, 0.029703, 0.029704, 0.029704",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\ + "0.419470, 0.419470, 0.419470, 0.419470, 0.419470",\ + "1.483040, 1.483040, 1.483040, 1.483042, 1.483046",\ + "0.029703, 0.029703, 0.029703, 0.029704, 0.029704",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\ + "0.419470, 0.419470, 0.419470, 0.419470, 0.419470",\ + "1.483040, 1.483040, 1.483040, 1.483042, 1.483047"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_min*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[30]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.454515, 0.687556, 0.876637, 1.181062, 1.770586",\ + "0.496240, 0.729281, 0.918362, 1.222787, 1.812311",\ + "0.572297, 0.805339, 0.994419, 1.298844, 1.888368",\ + "0.827855, 1.060896, 1.249979, 1.554404, 2.143927",\ + "1.752113, 1.985154, 2.174236, 2.478661, 3.068184",\ + "0.542959, 0.774874, 0.963918, 1.268367, 1.857939",\ + "0.584684, 0.816599, 1.005643, 1.310092, 1.899664",\ + "0.660741, 0.892656, 1.081700, 1.386149, 1.975721",\ + "0.916299, 1.148213, 1.337260, 1.641709, 2.231281",\ + "1.840557, 2.072472, 2.261517, 2.565966, 3.155538",\ + "0.633029, 0.855201, 1.043945, 1.348395, 1.937971",\ + "0.674754, 0.896927, 1.085670, 1.390121, 1.979696",\ + "0.750812, 0.972984, 1.161727, 1.466178, 2.055753",\ + "1.006370, 1.228541, 1.417287, 1.721738, 2.311312",\ + "1.930628, 2.152800, 2.341543, 2.645994, 3.235569",\ + "0.697606, 0.913035, 1.101665, 1.405861, 1.995059",\ + "0.739331, 0.954761, 1.143391, 1.447586, 2.036784",\ + "0.815389, 1.030818, 1.219448, 1.523643, 2.112841",\ + "1.070947, 1.286375, 1.475007, 1.779203, 2.368400",\ + "1.995205, 2.210634, 2.399264, 2.703460, 3.292657",\ + "1.037719, 1.218357, 1.405324, 1.709062, 2.297368",\ + "1.079444, 1.260083, 1.447049, 1.750787, 2.339093",\ + "1.155501, 1.336140, 1.523106, 1.826844, 2.415150",\ + "1.411059, 1.591697, 1.778666, 2.082405, 2.670709",\ + "2.335317, 2.515956, 2.702923, 3.006661, 3.594966"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.025366, 0.025366, 0.025366, 0.025366, 0.025366",\ + "0.070222, 0.070222, 0.070222, 0.070222, 0.070222",\ + "0.199531, 0.199531, 0.199531, 0.199531, 0.199531",\ + "0.686584, 0.686584, 0.686584, 0.686584, 0.686584",\ + "2.452471, 2.452462, 2.452462, 2.452446, 2.452406",\ + "0.025366, 0.025366, 0.025366, 0.025366, 0.025366",\ + "0.070222, 0.070222, 0.070222, 0.070222, 0.070222",\ + "0.199531, 0.199531, 0.199531, 0.199531, 0.199531",\ + "0.686584, 0.686584, 0.686584, 0.686584, 0.686584",\ + "2.452471, 2.452462, 2.452462, 2.452446, 2.452406",\ + "0.025366, 0.025366, 0.025366, 0.025366, 0.025366",\ + "0.070222, 0.070222, 0.070222, 0.070222, 0.070222",\ + "0.199531, 0.199531, 0.199531, 0.199531, 0.199531",\ + "0.686584, 0.686584, 0.686584, 0.686584, 0.686584",\ + "2.452471, 2.452462, 2.452462, 2.452446, 2.452406",\ + "0.025366, 0.025366, 0.025366, 0.025366, 0.025366",\ + "0.070222, 0.070222, 0.070222, 0.070222, 0.070222",\ + "0.199531, 0.199531, 0.199531, 0.199531, 0.199531",\ + "0.686584, 0.686584, 0.686584, 0.686584, 0.686584",\ + "2.452470, 2.452462, 2.452462, 2.452446, 2.452406",\ + "0.025366, 0.025366, 0.025366, 0.025366, 0.025366",\ + "0.070222, 0.070222, 0.070222, 0.070222, 0.070222",\ + "0.199531, 0.199531, 0.199531, 0.199531, 0.199531",\ + "0.686584, 0.686584, 0.686584, 0.686584, 0.686584",\ + "2.452470, 2.452462, 2.452462, 2.452446, 2.452406"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.477114, 0.710155, 0.899236, 1.203661, 1.793185",\ + "0.509144, 0.742185, 0.931266, 1.235691, 1.825215",\ + "0.559532, 0.792574, 0.981654, 1.286079, 1.875603",\ + "0.720561, 0.953603, 1.142682, 1.447107, 2.036631",\ + "1.300536, 1.533577, 1.722657, 2.027082, 2.616606",\ + "0.565558, 0.797473, 0.986517, 1.290966, 1.880538",\ + "0.597588, 0.829503, 1.018547, 1.322996, 1.912568",\ + "0.647976, 0.879891, 1.068935, 1.373384, 1.962957",\ + "0.809005, 1.040920, 1.229963, 1.534412, 2.123985",\ + "1.388980, 1.620895, 1.809938, 2.114387, 2.703959",\ + "0.655628, 0.877800, 1.066544, 1.370995, 1.960570",\ + "0.687658, 0.909830, 1.098574, 1.403025, 1.992600",\ + "0.738047, 0.960219, 1.148962, 1.453413, 2.042988",\ + "0.899075, 1.121248, 1.309990, 1.614440, 2.204016",\ + "1.479050, 1.701223, 1.889965, 2.194416, 2.783991",\ + "0.720205, 0.935634, 1.124265, 1.428460, 2.017658",\ + "0.752235, 0.967664, 1.156295, 1.460490, 2.049688",\ + "0.802624, 1.018053, 1.206683, 1.510878, 2.100076",\ + "0.963652, 1.179082, 1.367711, 1.671906, 2.261104",\ + "1.543628, 1.759057, 1.947685, 2.251881, 2.841079",\ + "1.060318, 1.240956, 1.427923, 1.731662, 2.319967",\ + "1.092348, 1.272986, 1.459953, 1.763692, 2.351997",\ + "1.142736, 1.323375, 1.510341, 1.814080, 2.402385",\ + "1.303765, 1.484404, 1.671369, 1.975107, 2.563413",\ + "1.883740, 2.064379, 2.251344, 2.555082, 3.143388"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.029863, 0.029863, 0.029863, 0.029863, 0.029863",\ + "0.059265, 0.059264, 0.059264, 0.059264, 0.059262",\ + "0.131521, 0.131521, 0.131521, 0.131521, 0.131521",\ + "0.417786, 0.417783, 0.417783, 0.417777, 0.417763",\ + "1.484506, 1.484504, 1.484504, 1.484501, 1.484494",\ + "0.029863, 0.029863, 0.029863, 0.029863, 0.029863",\ + "0.059265, 0.059264, 0.059264, 0.059264, 0.059262",\ + "0.131521, 0.131521, 0.131521, 0.131521, 0.131521",\ + "0.417786, 0.417783, 0.417783, 0.417777, 0.417763",\ + "1.484506, 1.484504, 1.484504, 1.484501, 1.484494",\ + "0.029863, 0.029863, 0.029863, 0.029863, 0.029863",\ + "0.059265, 0.059264, 0.059264, 0.059264, 0.059262",\ + "0.131521, 0.131521, 0.131521, 0.131521, 0.131521",\ + "0.417785, 0.417783, 0.417783, 0.417777, 0.417763",\ + "1.484505, 1.484504, 1.484504, 1.484501, 1.484494",\ + "0.029863, 0.029863, 0.029863, 0.029863, 0.029863",\ + "0.059265, 0.059264, 0.059264, 0.059264, 0.059262",\ + "0.131521, 0.131521, 0.131521, 0.131521, 0.131521",\ + "0.417785, 0.417783, 0.417783, 0.417777, 0.417763",\ + "1.484505, 1.484504, 1.484504, 1.484501, 1.484494",\ + "0.029863, 0.029863, 0.029863, 0.029863, 0.029863",\ + "0.059265, 0.059264, 0.059264, 0.059264, 0.059262",\ + "0.131521, 0.131521, 0.131521, 0.131521, 0.131521",\ + "0.417785, 0.417783, 0.417783, 0.417777, 0.417763",\ + "1.484505, 1.484504, 1.484504, 1.484501, 1.484493"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_min_2361*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[36]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.425794, 0.659396, 0.844981, 1.144718, 1.725521",\ + "0.467517, 0.701119, 0.886704, 1.186441, 1.767244",\ + "0.543582, 0.777185, 0.962769, 1.262506, 1.843310",\ + "0.799075, 1.032669, 1.218262, 1.518000, 2.098799",\ + "1.723381, 1.956982, 2.142568, 2.442305, 3.023108",\ + "0.514202, 0.746714, 0.932262, 1.232023, 1.812875",\ + "0.555925, 0.788437, 0.973985, 1.273746, 1.854598",\ + "0.631990, 0.864504, 1.050050, 1.349811, 1.930663",\ + "0.887482, 1.119988, 1.305543, 1.605305, 2.186153",\ + "1.811789, 2.044301, 2.229849, 2.529610, 3.110461",\ + "0.603290, 0.827050, 1.012289, 1.312051, 1.892906",\ + "0.645013, 0.868772, 1.054012, 1.353774, 1.934629",\ + "0.721078, 0.944839, 1.130077, 1.429839, 2.010695",\ + "0.976570, 1.200323, 1.385570, 1.685334, 2.266185",\ + "1.900877, 2.124636, 2.309876, 2.609639, 3.190493",\ + "0.666566, 0.884881, 1.069999, 1.369505, 1.949970",\ + "0.708289, 0.926604, 1.111723, 1.411228, 1.991693",\ + "0.784354, 1.002670, 1.187788, 1.487293, 2.067758",\ + "1.039845, 1.258154, 1.443280, 1.742788, 2.323248",\ + "1.964153, 2.182467, 2.367587, 2.667093, 3.247556",\ + "1.000632, 1.190214, 1.373659, 1.672698, 2.252249",\ + "1.042355, 1.231937, 1.415382, 1.714421, 2.293972",\ + "1.118420, 1.308003, 1.491447, 1.790486, 2.370037",\ + "1.373908, 1.563487, 1.746940, 2.045980, 2.625527",\ + "2.298218, 2.487800, 2.671246, 2.970286, 3.549836"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.025354, 0.025353, 0.025353, 0.025353, 0.025353",\ + "0.070228, 0.070228, 0.070228, 0.070228, 0.070228",\ + "0.199490, 0.199485, 0.199485, 0.199485, 0.199485",\ + "0.686682, 0.686682, 0.686679, 0.686679, 0.686679",\ + "2.452544, 2.452522, 2.452521, 2.452511, 2.452485",\ + "0.025354, 0.025353, 0.025353, 0.025353, 0.025353",\ + "0.070228, 0.070228, 0.070228, 0.070228, 0.070228",\ + "0.199490, 0.199485, 0.199485, 0.199485, 0.199485",\ + "0.686682, 0.686682, 0.686679, 0.686679, 0.686679",\ + "2.452543, 2.452522, 2.452521, 2.452511, 2.452485",\ + "0.025354, 0.025353, 0.025353, 0.025353, 0.025353",\ + "0.070228, 0.070228, 0.070228, 0.070228, 0.070228",\ + "0.199489, 0.199485, 0.199485, 0.199485, 0.199485",\ + "0.686682, 0.686682, 0.686679, 0.686679, 0.686679",\ + "2.452541, 2.452522, 2.452521, 2.452511, 2.452485",\ + "0.025354, 0.025353, 0.025353, 0.025353, 0.025353",\ + "0.070228, 0.070228, 0.070228, 0.070228, 0.070228",\ + "0.199489, 0.199485, 0.199485, 0.199485, 0.199485",\ + "0.686682, 0.686682, 0.686679, 0.686679, 0.686679",\ + "2.452540, 2.452522, 2.452521, 2.452511, 2.452485",\ + "0.025353, 0.025353, 0.025353, 0.025353, 0.025353",\ + "0.070228, 0.070228, 0.070228, 0.070228, 0.070228",\ + "0.199487, 0.199485, 0.199485, 0.199485, 0.199485",\ + "0.686682, 0.686682, 0.686679, 0.686679, 0.686679",\ + "2.452530, 2.452522, 2.452521, 2.452511, 2.452485"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.448384, 0.681985, 0.867571, 1.167308, 1.748111",\ + "0.480409, 0.714010, 0.899596, 1.199333, 1.780136",\ + "0.530816, 0.764419, 0.950003, 1.249740, 1.830544",\ + "0.691874, 0.925480, 1.111061, 1.410797, 1.991603",\ + "1.271848, 1.505453, 1.691034, 1.990770, 2.571576",\ + "0.536792, 0.769304, 0.954852, 1.254613, 1.835465",\ + "0.568817, 0.801328, 0.986877, 1.286638, 1.867489",\ + "0.619224, 0.851737, 1.037284, 1.337045, 1.917897",\ + "0.780282, 1.012799, 1.198342, 1.498102, 2.078956",\ + "1.360255, 1.592772, 1.778315, 2.078075, 2.658929",\ + "0.625880, 0.849639, 1.034879, 1.334642, 1.915496",\ + "0.657905, 0.881663, 1.066904, 1.366667, 1.947521",\ + "0.708312, 0.932072, 1.117311, 1.417073, 1.997929",\ + "0.869371, 1.093134, 1.278369, 1.578131, 2.158988",\ + "1.449344, 1.673107, 1.858342, 2.158104, 2.738961",\ + "0.689156, 0.907470, 1.092590, 1.392096, 1.972560",\ + "0.721181, 0.939495, 1.124615, 1.424121, 2.004584",\ + "0.771588, 0.989904, 1.175022, 1.474527, 2.054992",\ + "0.932647, 1.150965, 1.336080, 1.635585, 2.216051",\ + "1.512620, 1.730939, 1.916053, 2.215558, 2.796025",\ + "1.023221, 1.212804, 1.396249, 1.695289, 2.274839",\ + "1.055246, 1.244828, 1.428274, 1.727314, 2.306864",\ + "1.105654, 1.295237, 1.478681, 1.777720, 2.357271",\ + "1.266715, 1.456299, 1.639739, 1.938777, 2.518331",\ + "1.846688, 2.036272, 2.219712, 2.518751, 3.098304"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.029862, 0.029862, 0.029862, 0.029862, 0.029862",\ + "0.059267, 0.059267, 0.059267, 0.059266, 0.059265",\ + "0.131513, 0.131512, 0.131512, 0.131512, 0.131512",\ + "0.417810, 0.417803, 0.417803, 0.417799, 0.417790",\ + "1.484519, 1.484515, 1.484514, 1.484513, 1.484508",\ + "0.029862, 0.029862, 0.029862, 0.029862, 0.029862",\ + "0.059267, 0.059267, 0.059267, 0.059266, 0.059265",\ + "0.131513, 0.131512, 0.131512, 0.131512, 0.131512",\ + "0.417810, 0.417803, 0.417803, 0.417799, 0.417790",\ + "1.484518, 1.484515, 1.484514, 1.484513, 1.484508",\ + "0.029862, 0.029862, 0.029862, 0.029862, 0.029862",\ + "0.059267, 0.059267, 0.059267, 0.059266, 0.059265",\ + "0.131513, 0.131512, 0.131512, 0.131512, 0.131512",\ + "0.417810, 0.417803, 0.417803, 0.417799, 0.417790",\ + "1.484518, 1.484515, 1.484514, 1.484513, 1.484508",\ + "0.029862, 0.029862, 0.029862, 0.029862, 0.029862",\ + "0.059267, 0.059267, 0.059267, 0.059266, 0.059265",\ + "0.131513, 0.131512, 0.131512, 0.131512, 0.131512",\ + "0.417809, 0.417803, 0.417803, 0.417799, 0.417790",\ + "1.484518, 1.484515, 1.484514, 1.484513, 1.484508",\ + "0.029862, 0.029862, 0.029862, 0.029862, 0.029862",\ + "0.059267, 0.059267, 0.059267, 0.059266, 0.059265",\ + "0.131512, 0.131512, 0.131512, 0.131512, 0.131512",\ + "0.417806, 0.417803, 0.417803, 0.417799, 0.417790",\ + "1.484516, 1.484515, 1.484514, 1.484513, 1.484508"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_min_2707*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[38]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.411437, 0.641763, 0.827440, 1.121826, 1.689429",\ + "0.453163, 0.683488, 0.869165, 1.163551, 1.731154",\ + "0.529220, 0.759545, 0.945221, 1.239608, 1.807211",\ + "0.784777, 1.015107, 1.200787, 1.495173, 2.062773",\ + "1.709036, 1.939362, 2.125040, 2.419426, 2.987028",\ + "0.499750, 0.729081, 0.914721, 1.209131, 1.776782",\ + "0.541475, 0.770807, 0.956446, 1.250857, 1.818508",\ + "0.617533, 0.846863, 1.032502, 1.326913, 1.894564",\ + "0.873090, 1.102426, 1.288068, 1.582478, 2.150126",\ + "1.797349, 2.026680, 2.212321, 2.506731, 3.074381",\ + "0.588895, 0.809414, 0.994747, 1.289160, 1.856814",\ + "0.630620, 0.851139, 1.036473, 1.330885, 1.898539",\ + "0.706677, 0.927196, 1.112529, 1.406941, 1.974596",\ + "0.962234, 1.182758, 1.368095, 1.662507, 2.230158",\ + "1.886493, 2.107013, 2.292347, 2.586760, 3.154413",\ + "0.652369, 0.867238, 1.052459, 1.346598, 1.913847",\ + "0.694094, 0.908963, 1.094185, 1.388323, 1.955572",\ + "0.770151, 0.985020, 1.170241, 1.464380, 2.031629",\ + "1.025709, 1.240582, 1.425807, 1.719945, 2.287190",\ + "1.949967, 2.164837, 2.350059, 2.644198, 3.211446",\ + "0.987682, 1.172511, 1.356118, 1.649777, 2.216089",\ + "1.029408, 1.214237, 1.397843, 1.691502, 2.257815",\ + "1.105465, 1.290294, 1.473899, 1.767559, 2.333871",\ + "1.361025, 1.545856, 1.729465, 2.023124, 2.589433",\ + "2.285281, 2.470111, 2.653718, 2.947377, 3.513689"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.025366, 0.025366, 0.025366, 0.025366, 0.025366",\ + "0.070223, 0.070222, 0.070221, 0.070221, 0.070221",\ + "0.199530, 0.199530, 0.199530, 0.199530, 0.199530",\ + "0.686589, 0.686583, 0.686578, 0.686576, 0.686576",\ + "2.452462, 2.452462, 2.452462, 2.452450, 2.452423",\ + "0.025366, 0.025366, 0.025366, 0.025366, 0.025366",\ + "0.070223, 0.070222, 0.070221, 0.070221, 0.070221",\ + "0.199530, 0.199530, 0.199530, 0.199530, 0.199530",\ + "0.686589, 0.686583, 0.686578, 0.686576, 0.686576",\ + "2.452462, 2.452462, 2.452462, 2.452450, 2.452423",\ + "0.025366, 0.025366, 0.025366, 0.025366, 0.025366",\ + "0.070223, 0.070222, 0.070221, 0.070221, 0.070221",\ + "0.199530, 0.199530, 0.199530, 0.199530, 0.199530",\ + "0.686588, 0.686583, 0.686578, 0.686576, 0.686576",\ + "2.452462, 2.452462, 2.452462, 2.452450, 2.452423",\ + "0.025366, 0.025366, 0.025366, 0.025366, 0.025366",\ + "0.070223, 0.070222, 0.070221, 0.070221, 0.070221",\ + "0.199530, 0.199530, 0.199530, 0.199530, 0.199530",\ + "0.686588, 0.686583, 0.686578, 0.686576, 0.686576",\ + "2.452462, 2.452462, 2.452462, 2.452450, 2.452423",\ + "0.025366, 0.025366, 0.025366, 0.025366, 0.025366",\ + "0.070222, 0.070222, 0.070221, 0.070221, 0.070221",\ + "0.199530, 0.199530, 0.199530, 0.199530, 0.199530",\ + "0.686585, 0.686583, 0.686578, 0.686576, 0.686576",\ + "2.452462, 2.452462, 2.452462, 2.452450, 2.452422"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.434036, 0.664363, 0.850040, 1.144426, 1.712028",\ + "0.466066, 0.696393, 0.882070, 1.176457, 1.744059",\ + "0.516455, 0.746780, 0.932457, 1.226843, 1.794446",\ + "0.677484, 0.907807, 1.093482, 1.387868, 1.955473",\ + "1.257459, 1.487782, 1.673457, 1.967843, 2.535448",\ + "0.522349, 0.751681, 0.937321, 1.231731, 1.799382",\ + "0.554379, 0.783711, 0.969351, 1.263762, 1.831412",\ + "0.604768, 0.834099, 1.019738, 1.314148, 1.881800",\ + "0.765797, 0.995125, 1.180763, 1.475173, 2.042827",\ + "1.345772, 1.575100, 1.760738, 2.055148, 2.622802",\ + "0.611494, 0.832013, 1.017348, 1.311760, 1.879413",\ + "0.643524, 0.864044, 1.049378, 1.343790, 1.911444",\ + "0.693912, 0.914431, 1.099764, 1.394177, 1.961831",\ + "0.854941, 1.075458, 1.260790, 1.555202, 2.122858",\ + "1.434916, 1.655433, 1.840765, 2.135177, 2.702833",\ + "0.674968, 0.889838, 1.075059, 1.369198, 1.936446",\ + "0.706998, 0.921868, 1.107090, 1.401229, 1.968477",\ + "0.757386, 0.972255, 1.157476, 1.451615, 2.018864",\ + "0.918415, 1.133282, 1.318501, 1.612640, 2.179891",\ + "1.498390, 1.713257, 1.898476, 2.192615, 2.759866",\ + "1.010282, 1.195111, 1.378718, 1.672377, 2.238689",\ + "1.042312, 1.227141, 1.410748, 1.704407, 2.270719",\ + "1.092700, 1.277529, 1.461135, 1.754794, 2.321106",\ + "1.253727, 1.438555, 1.622160, 1.915819, 2.482133",\ + "1.833702, 2.018530, 2.202135, 2.495794, 3.062109"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.029863, 0.029863, 0.029863, 0.029863, 0.029863",\ + "0.059264, 0.059264, 0.059264, 0.059264, 0.059262",\ + "0.131521, 0.131521, 0.131521, 0.131521, 0.131521",\ + "0.417782, 0.417782, 0.417782, 0.417778, 0.417769",\ + "1.484504, 1.484504, 1.484504, 1.484501, 1.484496",\ + "0.029863, 0.029863, 0.029863, 0.029863, 0.029863",\ + "0.059264, 0.059264, 0.059264, 0.059264, 0.059262",\ + "0.131521, 0.131521, 0.131521, 0.131521, 0.131521",\ + "0.417782, 0.417782, 0.417782, 0.417778, 0.417769",\ + "1.484504, 1.484504, 1.484504, 1.484501, 1.484496",\ + "0.029863, 0.029863, 0.029863, 0.029863, 0.029863",\ + "0.059264, 0.059264, 0.059264, 0.059264, 0.059262",\ + "0.131521, 0.131521, 0.131521, 0.131521, 0.131521",\ + "0.417782, 0.417782, 0.417782, 0.417778, 0.417769",\ + "1.484504, 1.484504, 1.484504, 1.484501, 1.484496",\ + "0.029863, 0.029863, 0.029863, 0.029863, 0.029863",\ + "0.059264, 0.059264, 0.059264, 0.059264, 0.059262",\ + "0.131521, 0.131521, 0.131521, 0.131521, 0.131521",\ + "0.417782, 0.417782, 0.417782, 0.417778, 0.417769",\ + "1.484504, 1.484504, 1.484504, 1.484501, 1.484496",\ + "0.029863, 0.029863, 0.029863, 0.029863, 0.029863",\ + "0.059264, 0.059264, 0.059264, 0.059264, 0.059262",\ + "0.131521, 0.131521, 0.131521, 0.131521, 0.131521",\ + "0.417782, 0.417782, 0.417782, 0.417778, 0.417769",\ + "1.484504, 1.484504, 1.484504, 1.484501, 1.484496"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_min_2292*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[43]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011"); + values ( "0.506400, 0.723405, 0.901534, 1.190767, 1.752239",\ + "0.548095, 0.765101, 0.943229, 1.232462, 1.793935",\ + "0.624275, 0.841281, 1.019409, 1.308642, 1.870115",\ + "0.879665, 1.096670, 1.274799, 1.564032, 2.125504",\ + "1.804122, 2.021127, 2.199255, 2.488489, 3.049961",\ + "0.594776, 0.810723, 0.988814, 1.278072, 1.839592",\ + "0.636472, 0.852419, 1.030510, 1.319767, 1.881288",\ + "0.712652, 0.928599, 1.106690, 1.395947, 1.957468",\ + "0.968041, 1.183989, 1.362080, 1.651337, 2.212858",\ + "1.892498, 2.108445, 2.286536, 2.575794, 3.137315",\ + "0.684027, 0.891056, 1.068841, 1.358100, 1.919624",\ + "0.725722, 0.932752, 1.110537, 1.399796, 1.961320",\ + "0.801902, 1.008932, 1.186717, 1.475976, 2.037500",\ + "1.057292, 1.264322, 1.442107, 1.731366, 2.292889",\ + "1.981749, 2.188778, 2.366563, 2.655822, 3.217346",\ + "0.747566, 0.948873, 1.126535, 1.415531, 1.976642",\ + "0.789261, 0.990569, 1.168231, 1.457227, 2.018338",\ + "0.865441, 1.066749, 1.244411, 1.533407, 2.094518",\ + "1.120831, 1.322138, 1.499801, 1.788796, 2.349907",\ + "2.045288, 2.246595, 2.424257, 2.713253, 3.274364",\ + "1.075492, 1.254095, 1.430191, 1.718704, 2.278866",\ + "1.117188, 1.295791, 1.471887, 1.760399, 2.320562",\ + "1.193368, 1.371971, 1.548067, 1.836579, 2.396742",\ + "1.448757, 1.627361, 1.803456, 2.091969, 2.652131",\ + "2.373214, 2.551817, 2.727913, 3.016426, 3.576588"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011"); + values ( "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070076, 0.070076, 0.070076, 0.070076, 0.070076",\ + "0.199408, 0.199408, 0.199408, 0.199409, 0.199410",\ + "0.685874, 0.685874, 0.685874, 0.685874, 0.685874",\ + "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070076, 0.070076, 0.070076, 0.070076, 0.070076",\ + "0.199408, 0.199408, 0.199408, 0.199409, 0.199410",\ + "0.685874, 0.685874, 0.685874, 0.685874, 0.685874",\ + "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070076, 0.070076, 0.070076, 0.070076, 0.070076",\ + "0.199408, 0.199408, 0.199408, 0.199409, 0.199410",\ + "0.685874, 0.685874, 0.685874, 0.685874, 0.685874",\ + "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070076, 0.070076, 0.070076, 0.070076, 0.070076",\ + "0.199408, 0.199408, 0.199408, 0.199409, 0.199410",\ + "0.685874, 0.685874, 0.685874, 0.685874, 0.685874",\ + "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070076, 0.070076, 0.070076, 0.070076, 0.070076",\ + "0.199408, 0.199408, 0.199408, 0.199409, 0.199410",\ + "0.685874, 0.685874, 0.685874, 0.685874, 0.685874",\ + "2.455194, 2.455194, 2.455194, 2.455194, 2.455194"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011"); + values ( "0.526648, 0.743653, 0.921781, 1.211015, 1.772487",\ + "0.558894, 0.775899, 0.954027, 1.243261, 1.804733",\ + "0.609210, 0.826215, 1.004344, 1.293577, 1.855049",\ + "0.769874, 0.986879, 1.165008, 1.454241, 2.015713",\ + "1.350989, 1.567995, 1.746123, 2.035356, 2.596828",\ + "0.615024, 0.830971, 1.009062, 1.298320, 1.859840",\ + "0.647270, 0.863217, 1.041308, 1.330566, 1.892087",\ + "0.697586, 0.913533, 1.091625, 1.380882, 1.942403",\ + "0.858250, 1.074197, 1.252288, 1.541546, 2.103066",\ + "1.439366, 1.655313, 1.833404, 2.122661, 2.684182",\ + "0.704275, 0.911304, 1.089089, 1.378348, 1.939872",\ + "0.736521, 0.943550, 1.121335, 1.410594, 1.972118",\ + "0.786837, 0.993866, 1.171651, 1.460910, 2.022434",\ + "0.947501, 1.154530, 1.332315, 1.621574, 2.183098",\ + "1.528616, 1.735646, 1.913431, 2.202690, 2.764214",\ + "0.767814, 0.969121, 1.146783, 1.435779, 1.996890",\ + "0.800060, 1.001367, 1.179029, 1.468025, 2.029136",\ + "0.850376, 1.051683, 1.229346, 1.518341, 2.079452",\ + "1.011040, 1.212347, 1.390009, 1.679005, 2.240116",\ + "1.592155, 1.793463, 1.971125, 2.260120, 2.821231",\ + "1.095740, 1.274343, 1.450439, 1.738951, 2.299114",\ + "1.127986, 1.306589, 1.482685, 1.771198, 2.331360",\ + "1.178302, 1.356906, 1.533001, 1.821514, 2.381676",\ + "1.338966, 1.517570, 1.693665, 1.982178, 2.542340",\ + "1.920082, 2.098685, 2.274781, 2.563293, 3.123456"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011"); + values ( "0.029703, 0.029703, 0.029703, 0.029703, 0.029703",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131484, 0.131484, 0.131484, 0.131485, 0.131485",\ + "0.419485, 0.419485, 0.419484, 0.419483, 0.419481",\ + "1.483052, 1.483052, 1.483052, 1.483052, 1.483052",\ + "0.029703, 0.029703, 0.029703, 0.029703, 0.029703",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131484, 0.131484, 0.131484, 0.131485, 0.131485",\ + "0.419485, 0.419485, 0.419484, 0.419483, 0.419481",\ + "1.483052, 1.483052, 1.483052, 1.483052, 1.483052",\ + "0.029703, 0.029703, 0.029703, 0.029703, 0.029703",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131484, 0.131484, 0.131484, 0.131485, 0.131485",\ + "0.419485, 0.419485, 0.419484, 0.419483, 0.419481",\ + "1.483052, 1.483052, 1.483052, 1.483052, 1.483052",\ + "0.029703, 0.029703, 0.029703, 0.029703, 0.029703",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131484, 0.131484, 0.131484, 0.131485, 0.131485",\ + "0.419485, 0.419485, 0.419484, 0.419483, 0.419481",\ + "1.483052, 1.483052, 1.483052, 1.483052, 1.483052",\ + "0.029703, 0.029703, 0.029703, 0.029703, 0.029703",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131484, 0.131484, 0.131484, 0.131485, 0.131485",\ + "0.419485, 0.419485, 0.419484, 0.419483, 0.419481",\ + "1.483052, 1.483052, 1.483052, 1.483052, 1.483052"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_min_2480*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[44]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011"); + values ( "0.487215, 0.727664, 0.917972, 1.220770, 1.805421",\ + "0.528910, 0.769360, 0.959668, 1.262466, 1.847117",\ + "0.605090, 0.845540, 1.035848, 1.338646, 1.923296",\ + "0.860480, 1.100929, 1.291238, 1.594035, 2.178686",\ + "1.784937, 2.025386, 2.215694, 2.518492, 3.103143",\ + "0.575514, 0.814982, 1.005253, 1.308075, 1.892774",\ + "0.617210, 0.856678, 1.046949, 1.349771, 1.934470",\ + "0.693390, 0.932858, 1.123129, 1.425951, 2.010650",\ + "0.948779, 1.188247, 1.378519, 1.681340, 2.266040",\ + "1.873236, 2.112704, 2.302975, 2.605797, 3.190496",\ + "0.664798, 0.895313, 1.085280, 1.388104, 1.972806",\ + "0.706493, 0.937009, 1.126976, 1.429799, 2.014502",\ + "0.782673, 1.013189, 1.203156, 1.505979, 2.090682",\ + "1.038063, 1.268578, 1.458545, 1.761369, 2.346071",\ + "1.962520, 2.193035, 2.383002, 2.685826, 3.270528",\ + "0.728479, 0.953177, 1.143002, 1.445563, 2.029881",\ + "0.770175, 0.994873, 1.184698, 1.487259, 2.071577",\ + "0.846355, 1.071053, 1.260878, 1.563439, 2.147756",\ + "1.101744, 1.326442, 1.516268, 1.818828, 2.403146",\ + "2.026201, 2.250899, 2.440724, 2.743285, 3.327603",\ + "1.065102, 1.258723, 1.446662, 1.748759, 2.332174",\ + "1.106798, 1.300419, 1.488358, 1.790455, 2.373869",\ + "1.182978, 1.376599, 1.564538, 1.866635, 2.450049",\ + "1.438367, 1.631989, 1.819927, 2.122025, 2.705439",\ + "2.362824, 2.556445, 2.744384, 3.046481, 3.629896"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011"); + values ( "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070076, 0.070076, 0.070076, 0.070076, 0.070076",\ + "0.199408, 0.199409, 0.199409, 0.199410, 0.199412",\ + "0.685874, 0.685874, 0.685874, 0.685874, 0.685874",\ + "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070076, 0.070076, 0.070076, 0.070076, 0.070076",\ + "0.199408, 0.199409, 0.199409, 0.199410, 0.199412",\ + "0.685874, 0.685874, 0.685874, 0.685874, 0.685874",\ + "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070076, 0.070076, 0.070076, 0.070076, 0.070076",\ + "0.199408, 0.199409, 0.199409, 0.199410, 0.199412",\ + "0.685874, 0.685874, 0.685874, 0.685874, 0.685874",\ + "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070076, 0.070076, 0.070076, 0.070076, 0.070076",\ + "0.199408, 0.199409, 0.199409, 0.199410, 0.199412",\ + "0.685874, 0.685874, 0.685874, 0.685874, 0.685874",\ + "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070076, 0.070076, 0.070076, 0.070076, 0.070076",\ + "0.199409, 0.199409, 0.199409, 0.199410, 0.199412",\ + "0.685874, 0.685874, 0.685874, 0.685874, 0.685874",\ + "2.455194, 2.455194, 2.455194, 2.455194, 2.455194"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011"); + values ( "0.507462, 0.747912, 0.938220, 1.241018, 1.825669",\ + "0.539708, 0.780158, 0.970466, 1.273264, 1.857915",\ + "0.590025, 0.830474, 1.020782, 1.323580, 1.908231",\ + "0.750689, 0.991138, 1.181446, 1.484244, 2.068895",\ + "1.331804, 1.572254, 1.762562, 2.065360, 2.650010",\ + "0.595762, 0.835230, 1.025501, 1.328323, 1.913022",\ + "0.628008, 0.867476, 1.057747, 1.360569, 1.945268",\ + "0.678324, 0.917792, 1.108063, 1.410885, 1.995584",\ + "0.838988, 1.078456, 1.268727, 1.571549, 2.156248",\ + "1.420103, 1.659572, 1.849843, 2.152665, 2.737364",\ + "0.685045, 0.915561, 1.105528, 1.408352, 1.993054",\ + "0.717292, 0.947807, 1.137774, 1.440598, 2.025300",\ + "0.767608, 0.998123, 1.188090, 1.490914, 2.075616",\ + "0.928272, 1.158787, 1.348754, 1.651578, 2.236280",\ + "1.509387, 1.739902, 1.929870, 2.232693, 2.817395",\ + "0.748727, 0.973425, 1.163250, 1.465811, 2.050128",\ + "0.780973, 1.005671, 1.195496, 1.498057, 2.082375",\ + "0.831289, 1.055987, 1.245812, 1.548373, 2.132691",\ + "0.991953, 1.216651, 1.406476, 1.709037, 2.293355",\ + "1.573069, 1.797767, 1.987592, 2.290153, 2.874470",\ + "1.085350, 1.278971, 1.466910, 1.769007, 2.352422",\ + "1.117596, 1.311217, 1.499156, 1.801253, 2.384668",\ + "1.167912, 1.361534, 1.549472, 1.851569, 2.434984",\ + "1.328576, 1.522197, 1.710136, 2.012233, 2.595648",\ + "1.909692, 2.103313, 2.291251, 2.593349, 3.176763"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011"); + values ( "0.029703, 0.029703, 0.029703, 0.029703, 0.029704",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131484, 0.131485, 0.131485, 0.131485, 0.131485",\ + "0.419485, 0.419484, 0.419483, 0.419481, 0.419478",\ + "1.483052, 1.483052, 1.483052, 1.483052, 1.483052",\ + "0.029703, 0.029703, 0.029703, 0.029703, 0.029704",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131484, 0.131485, 0.131485, 0.131485, 0.131485",\ + "0.419485, 0.419484, 0.419483, 0.419481, 0.419478",\ + "1.483052, 1.483052, 1.483052, 1.483052, 1.483052",\ + "0.029703, 0.029703, 0.029703, 0.029703, 0.029704",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131484, 0.131485, 0.131485, 0.131485, 0.131485",\ + "0.419485, 0.419484, 0.419483, 0.419481, 0.419478",\ + "1.483052, 1.483052, 1.483052, 1.483052, 1.483052",\ + "0.029703, 0.029703, 0.029703, 0.029703, 0.029704",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131484, 0.131485, 0.131485, 0.131485, 0.131485",\ + "0.419485, 0.419484, 0.419483, 0.419481, 0.419478",\ + "1.483052, 1.483052, 1.483052, 1.483052, 1.483052",\ + "0.029703, 0.029703, 0.029703, 0.029703, 0.029704",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131484, 0.131485, 0.131485, 0.131485, 0.131485",\ + "0.419484, 0.419484, 0.419483, 0.419481, 0.419478",\ + "1.483052, 1.483052, 1.483052, 1.483052, 1.483052"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_min_2458*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[47]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011"); + values ( "0.401855, 0.617772, 0.797138, 1.086913, 1.648811",\ + "0.443578, 0.659495, 0.838861, 1.128636, 1.690534",\ + "0.519643, 0.735561, 0.914927, 1.204702, 1.766600",\ + "0.775133, 0.991049, 1.170417, 1.460191, 2.022084",\ + "1.699442, 1.915359, 2.094725, 2.384500, 2.946397",\ + "0.490138, 0.705090, 0.884419, 1.174218, 1.736165",\ + "0.531861, 0.746813, 0.926142, 1.215941, 1.777887",\ + "0.607927, 0.822879, 1.002208, 1.292007, 1.853954",\ + "0.863417, 1.078367, 1.257698, 1.547496, 2.109437",\ + "1.787725, 2.002677, 2.182006, 2.471805, 3.033750",\ + "0.579402, 0.785421, 0.964446, 1.254247, 1.816196",\ + "0.621125, 0.827144, 1.006169, 1.295970, 1.857919",\ + "0.697191, 0.903209, 1.082235, 1.372035, 1.933985",\ + "0.952680, 1.158697, 1.337725, 1.627524, 2.189469",\ + "1.876989, 2.083007, 2.262033, 2.551833, 3.113782",\ + "0.643076, 0.843251, 1.022143, 1.311678, 1.873216",\ + "0.684799, 0.884974, 1.063866, 1.353401, 1.914939",\ + "0.760865, 0.961040, 1.139932, 1.429467, 1.991005",\ + "1.016354, 1.216527, 1.395422, 1.684956, 2.246489",\ + "1.940663, 2.140838, 2.319730, 2.609265, 3.170802",\ + "0.967710, 1.148559, 1.325799, 1.614851, 2.175443",\ + "1.009433, 1.190282, 1.367522, 1.656574, 2.217166",\ + "1.085498, 1.266348, 1.443587, 1.732640, 2.293232",\ + "1.340988, 1.521835, 1.699077, 1.988128, 2.548716",\ + "2.265296, 2.446146, 2.623385, 2.912438, 3.473029"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011"); + values ( "0.025354, 0.025353, 0.025353, 0.025353, 0.025352",\ + "0.070228, 0.070228, 0.070228, 0.070228, 0.070228",\ + "0.199488, 0.199487, 0.199487, 0.199486, 0.199483",\ + "0.686687, 0.686687, 0.686686, 0.686686, 0.686686",\ + "2.452523, 2.452519, 2.452519, 2.452513, 2.452498",\ + "0.025354, 0.025353, 0.025353, 0.025353, 0.025352",\ + "0.070228, 0.070228, 0.070228, 0.070228, 0.070228",\ + "0.199488, 0.199487, 0.199487, 0.199486, 0.199483",\ + "0.686687, 0.686687, 0.686686, 0.686686, 0.686686",\ + "2.452523, 2.452519, 2.452519, 2.452513, 2.452498",\ + "0.025354, 0.025353, 0.025353, 0.025353, 0.025352",\ + "0.070228, 0.070228, 0.070228, 0.070228, 0.070228",\ + "0.199487, 0.199487, 0.199487, 0.199486, 0.199483",\ + "0.686687, 0.686687, 0.686686, 0.686686, 0.686686",\ + "2.452523, 2.452519, 2.452519, 2.452513, 2.452498",\ + "0.025354, 0.025353, 0.025353, 0.025353, 0.025352",\ + "0.070228, 0.070228, 0.070228, 0.070228, 0.070228",\ + "0.199487, 0.199487, 0.199487, 0.199486, 0.199483",\ + "0.686687, 0.686687, 0.686686, 0.686686, 0.686686",\ + "2.452523, 2.452519, 2.452519, 2.452513, 2.452498",\ + "0.025354, 0.025353, 0.025353, 0.025353, 0.025352",\ + "0.070228, 0.070228, 0.070228, 0.070228, 0.070228",\ + "0.199487, 0.199487, 0.199487, 0.199486, 0.199483",\ + "0.686687, 0.686687, 0.686686, 0.686686, 0.686686",\ + "2.452523, 2.452519, 2.452519, 2.452513, 2.452498"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011"); + values ( "0.424445, 0.640362, 0.819728, 1.109503, 1.671400",\ + "0.456469, 0.672387, 0.851753, 1.141528, 1.703424",\ + "0.506877, 0.722795, 0.902161, 1.191936, 1.753834",\ + "0.667936, 0.883855, 1.063220, 1.352995, 1.914896",\ + "1.247909, 1.463828, 1.643193, 1.932969, 2.494869",\ + "0.512729, 0.727680, 0.907009, 1.196808, 1.758754",\ + "0.544753, 0.759704, 0.939034, 1.228833, 1.790778",\ + "0.595161, 0.810113, 0.989442, 1.279241, 1.841187",\ + "0.756220, 0.971173, 1.150501, 1.440300, 2.002249",\ + "1.336193, 1.551146, 1.730474, 2.020274, 2.582222",\ + "0.601992, 0.808011, 0.987036, 1.276837, 1.838785",\ + "0.634017, 0.840035, 1.019061, 1.308861, 1.870810",\ + "0.684425, 0.890443, 1.069469, 1.359269, 1.921219",\ + "0.845484, 1.051504, 1.230528, 1.520329, 2.082281",\ + "1.425457, 1.631477, 1.810501, 2.100302, 2.662254",\ + "0.665666, 0.865841, 1.044734, 1.334268, 1.895805",\ + "0.697691, 0.897865, 1.076758, 1.366293, 1.927830",\ + "0.748099, 0.948274, 1.127166, 1.416701, 1.978239",\ + "0.909158, 1.109334, 1.288225, 1.577760, 2.139301",\ + "1.489131, 1.689307, 1.868198, 2.157734, 2.719274",\ + "0.990300, 1.171149, 1.348389, 1.637441, 2.198032",\ + "1.022324, 1.203173, 1.380413, 1.669466, 2.230056",\ + "1.072732, 1.253582, 1.430821, 1.719874, 2.280466",\ + "1.233791, 1.414642, 1.591880, 1.880933, 2.441528",\ + "1.813765, 1.994615, 2.171854, 2.460907, 3.021501"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011"); + values ( "0.029862, 0.029862, 0.029862, 0.029862, 0.029862",\ + "0.059267, 0.059267, 0.059267, 0.059266, 0.059266",\ + "0.131512, 0.131512, 0.131512, 0.131512, 0.131512",\ + "0.417803, 0.417802, 0.417802, 0.417800, 0.417795",\ + "1.484515, 1.484514, 1.484514, 1.484513, 1.484510",\ + "0.029862, 0.029862, 0.029862, 0.029862, 0.029862",\ + "0.059267, 0.059267, 0.059267, 0.059266, 0.059266",\ + "0.131512, 0.131512, 0.131512, 0.131512, 0.131512",\ + "0.417803, 0.417802, 0.417802, 0.417800, 0.417795",\ + "1.484515, 1.484514, 1.484514, 1.484513, 1.484510",\ + "0.029862, 0.029862, 0.029862, 0.029862, 0.029862",\ + "0.059267, 0.059267, 0.059267, 0.059266, 0.059266",\ + "0.131512, 0.131512, 0.131512, 0.131512, 0.131512",\ + "0.417803, 0.417802, 0.417802, 0.417800, 0.417795",\ + "1.484515, 1.484514, 1.484514, 1.484513, 1.484510",\ + "0.029862, 0.029862, 0.029862, 0.029862, 0.029862",\ + "0.059267, 0.059267, 0.059267, 0.059266, 0.059266",\ + "0.131512, 0.131512, 0.131512, 0.131512, 0.131512",\ + "0.417803, 0.417802, 0.417802, 0.417800, 0.417795",\ + "1.484515, 1.484514, 1.484514, 1.484513, 1.484510",\ + "0.029862, 0.029862, 0.029862, 0.029862, 0.029862",\ + "0.059267, 0.059267, 0.059267, 0.059266, 0.059266",\ + "0.131512, 0.131512, 0.131512, 0.131512, 0.131512",\ + "0.417803, 0.417802, 0.417802, 0.417800, 0.417795",\ + "1.484515, 1.484514, 1.484514, 1.484513, 1.484510"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_min_2440*/ + +} /* end of pin tl_o[8] */ + +pin("tl_o[7]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.035370 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : tl_o[7]; + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[18]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.763083, 1.005361, 1.270323, 1.744250, 2.692104",\ + "0.776922, 1.019201, 1.284163, 1.758090, 2.705944",\ + "0.800433, 1.042711, 1.307673, 1.781600, 2.729455",\ + "1.069305, 1.311583, 1.576544, 2.050472, 2.998326",\ + "1.663833, 1.906111, 2.171072, 2.644999, 3.592854",\ + "0.850491, 1.092832, 1.357904, 1.830964, 2.778038",\ + "0.864331, 1.106672, 1.371744, 1.844804, 2.791878",\ + "0.887842, 1.130182, 1.395254, 1.868315, 2.815388",\ + "1.156713, 1.399054, 1.664126, 2.137186, 3.084260",\ + "1.751242, 1.993582, 2.258653, 2.731714, 3.678787",\ + "0.931306, 1.181626, 1.445868, 1.918586, 2.864993",\ + "0.945146, 1.195466, 1.459708, 1.932426, 2.878833",\ + "0.968656, 1.218976, 1.483218, 1.955936, 2.902343",\ + "1.237528, 1.487848, 1.752090, 2.224808, 3.171215",\ + "1.832057, 2.082376, 2.346617, 2.819335, 3.765743",\ + "0.989274, 1.246989, 1.510009, 1.982499, 2.928502",\ + "1.003114, 1.260829, 1.523849, 1.996339, 2.942342",\ + "1.026624, 1.284340, 1.547359, 2.019849, 2.965852",\ + "1.295496, 1.553211, 1.816230, 2.288721, 3.234724",\ + "1.890025, 2.147739, 2.410758, 2.883248, 3.829252",\ + "1.322822, 1.608220, 1.861925, 2.331865, 3.273958",\ + "1.336662, 1.622059, 1.875765, 2.345705, 3.287798",\ + "1.360173, 1.645570, 1.899276, 2.369215, 3.311308",\ + "1.629045, 1.914441, 2.168147, 2.638086, 3.580180",\ + "2.223573, 2.508969, 2.762674, 3.232614, 4.174707"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.129963, 0.129969, 0.129995, 0.130055, 0.130175",\ + "0.157856, 0.157859, 0.157877, 0.157917, 0.157996",\ + "0.203046, 0.203047, 0.203054, 0.203070, 0.203103",\ + "0.823721, 0.823721, 0.823721, 0.823721, 0.823721",\ + "2.222145, 2.222145, 2.222145, 2.222145, 2.222145",\ + "0.129963, 0.129969, 0.129995, 0.130055, 0.130175",\ + "0.157856, 0.157859, 0.157877, 0.157917, 0.157996",\ + "0.203046, 0.203047, 0.203054, 0.203070, 0.203103",\ + "0.823721, 0.823721, 0.823721, 0.823721, 0.823721",\ + "2.222145, 2.222145, 2.222145, 2.222145, 2.222145",\ + "0.129963, 0.129969, 0.129995, 0.130055, 0.130175",\ + "0.157856, 0.157860, 0.157877, 0.157917, 0.157996",\ + "0.203046, 0.203047, 0.203054, 0.203070, 0.203103",\ + "0.823721, 0.823721, 0.823721, 0.823721, 0.823721",\ + "2.222145, 2.222145, 2.222145, 2.222145, 2.222145",\ + "0.129963, 0.129969, 0.129995, 0.130055, 0.130175",\ + "0.157856, 0.157860, 0.157877, 0.157917, 0.157996",\ + "0.203046, 0.203047, 0.203054, 0.203070, 0.203103",\ + "0.823721, 0.823721, 0.823721, 0.823721, 0.823721",\ + "2.222145, 2.222145, 2.222145, 2.222145, 2.222145",\ + "0.129963, 0.129972, 0.129996, 0.130055, 0.130175",\ + "0.157856, 0.157861, 0.157877, 0.157917, 0.157996",\ + "0.203046, 0.203048, 0.203055, 0.203071, 0.203103",\ + "0.823721, 0.823721, 0.823721, 0.823721, 0.823721",\ + "2.222145, 2.222145, 2.222145, 2.222145, 2.222145"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.698169, 0.940449, 1.205412, 1.679339, 2.627193",\ + "0.711314, 0.953594, 1.218557, 1.692484, 2.640338",\ + "0.732465, 0.974745, 1.239707, 1.713634, 2.661488",\ + "0.908675, 1.150953, 1.415913, 1.889840, 2.837695",\ + "1.242989, 1.485267, 1.750227, 2.224154, 3.172009",\ + "0.785578, 1.027920, 1.292994, 1.766054, 2.713127",\ + "0.798723, 1.041065, 1.306139, 1.779198, 2.726272",\ + "0.819874, 1.062215, 1.327289, 1.800348, 2.747422",\ + "0.996084, 1.238424, 1.503495, 1.976555, 2.923629",\ + "1.330398, 1.572737, 1.837808, 2.310869, 3.257943",\ + "0.866392, 1.116714, 1.380958, 1.853675, 2.800082",\ + "0.879538, 1.129859, 1.394103, 1.866820, 2.813227",\ + "0.900689, 1.151010, 1.415252, 1.887970, 2.834377",\ + "1.076899, 1.327218, 1.591458, 2.064176, 3.010584",\ + "1.411212, 1.661532, 1.925772, 2.398490, 3.344898",\ + "0.924360, 1.182077, 1.445098, 1.917589, 2.863591",\ + "0.937505, 1.195222, 1.458243, 1.930733, 2.876736",\ + "0.958657, 1.216373, 1.479393, 1.951883, 2.897886",\ + "1.134866, 1.392581, 1.655599, 2.128089, 3.074093",\ + "1.469180, 1.726895, 1.989913, 2.462403, 3.408407",\ + "1.257909, 1.543308, 1.797015, 2.266954, 3.209047",\ + "1.271054, 1.556453, 1.810160, 2.280099, 3.222192",\ + "1.292205, 1.577603, 1.831310, 2.301249, 3.243342",\ + "1.468415, 1.753811, 2.007515, 2.477455, 3.419549",\ + "1.802729, 2.088125, 2.341829, 2.811769, 3.753863"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.086495, 0.086495, 0.086495, 0.086495, 0.086495",\ + "0.090876, 0.090876, 0.090876, 0.090876, 0.090876",\ + "0.110244, 0.110244, 0.110244, 0.110244, 0.110244",\ + "0.380767, 0.380767, 0.380767, 0.380768, 0.380769",\ + "1.026303, 1.026303, 1.026304, 1.026307, 1.026312",\ + "0.086495, 0.086495, 0.086495, 0.086495, 0.086495",\ + "0.090876, 0.090876, 0.090876, 0.090876, 0.090876",\ + "0.110244, 0.110244, 0.110244, 0.110244, 0.110244",\ + "0.380767, 0.380767, 0.380767, 0.380768, 0.380769",\ + "1.026303, 1.026303, 1.026305, 1.026307, 1.026312",\ + "0.086495, 0.086495, 0.086495, 0.086495, 0.086495",\ + "0.090876, 0.090876, 0.090876, 0.090876, 0.090876",\ + "0.110244, 0.110244, 0.110244, 0.110244, 0.110244",\ + "0.380767, 0.380767, 0.380767, 0.380768, 0.380769",\ + "1.026303, 1.026303, 1.026305, 1.026307, 1.026312",\ + "0.086495, 0.086495, 0.086495, 0.086495, 0.086495",\ + "0.090876, 0.090876, 0.090876, 0.090876, 0.090876",\ + "0.110244, 0.110244, 0.110244, 0.110244, 0.110244",\ + "0.380767, 0.380767, 0.380767, 0.380768, 0.380769",\ + "1.026303, 1.026303, 1.026305, 1.026307, 1.026312",\ + "0.086495, 0.086495, 0.086495, 0.086495, 0.086495",\ + "0.090876, 0.090876, 0.090876, 0.090876, 0.090876",\ + "0.110244, 0.110244, 0.110244, 0.110244, 0.110244",\ + "0.380767, 0.380767, 0.380767, 0.380768, 0.380769",\ + "1.026303, 1.026303, 1.026305, 1.026307, 1.026312"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_2625*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[19]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011"); + values ( "0.787208, 1.042240, 1.299016, 1.737737, 2.615179",\ + "0.801048, 1.056080, 1.312856, 1.751576, 2.629018",\ + "0.824558, 1.079590, 1.336366, 1.775087, 2.652528",\ + "1.093430, 1.348462, 1.605238, 2.043957, 2.921395",\ + "1.687959, 1.942991, 2.199766, 2.638483, 3.515917",\ + "0.874617, 1.129725, 1.386486, 1.824451, 2.701113",\ + "0.888456, 1.143564, 1.400326, 1.838291, 2.714952",\ + "0.911967, 1.167075, 1.423836, 1.861801, 2.738462",\ + "1.180839, 1.435947, 1.692708, 2.130671, 3.007329",\ + "1.775367, 2.030476, 2.287236, 2.725197, 3.601851",\ + "0.962301, 1.218548, 1.474448, 1.912073, 2.788068",\ + "0.976141, 1.232388, 1.488288, 1.925912, 2.801907",\ + "0.999652, 1.255898, 1.511798, 1.949423, 2.825417",\ + "1.268523, 1.524770, 1.780670, 2.218293, 3.094284",\ + "1.863052, 2.119299, 2.375198, 2.812819, 3.688806",\ + "1.025488, 1.283954, 1.538583, 1.975986, 2.851577",\ + "1.039328, 1.297794, 1.552423, 1.989825, 2.865416",\ + "1.062838, 1.321304, 1.575933, 2.013336, 2.888926",\ + "1.331710, 1.590176, 1.844805, 2.282206, 3.157793",\ + "1.926239, 2.184705, 2.439332, 2.876732, 3.752315",\ + "1.358969, 1.645690, 1.890142, 2.325206, 3.197033",\ + "1.372809, 1.659530, 1.903982, 2.339045, 3.210872",\ + "1.396320, 1.683041, 1.927492, 2.362556, 3.234382",\ + "1.665192, 1.951913, 2.196364, 2.631425, 3.503249",\ + "2.259720, 2.546442, 2.790892, 3.225951, 4.097771"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011"); + values ( "0.129962, 0.129962, 0.129971, 0.130001, 0.130060",\ + "0.157855, 0.157855, 0.157861, 0.157880, 0.157920",\ + "0.203046, 0.203046, 0.203048, 0.203056, 0.203072",\ + "0.823721, 0.823721, 0.823721, 0.823721, 0.823720",\ + "2.222145, 2.222145, 2.222145, 2.222145, 2.222145",\ + "0.129962, 0.129962, 0.129971, 0.130001, 0.130060",\ + "0.157855, 0.157855, 0.157861, 0.157880, 0.157920",\ + "0.203046, 0.203046, 0.203048, 0.203056, 0.203072",\ + "0.823721, 0.823721, 0.823721, 0.823721, 0.823720",\ + "2.222145, 2.222145, 2.222145, 2.222145, 2.222145",\ + "0.129962, 0.129962, 0.129971, 0.130001, 0.130060",\ + "0.157855, 0.157855, 0.157861, 0.157880, 0.157920",\ + "0.203046, 0.203046, 0.203048, 0.203056, 0.203072",\ + "0.823721, 0.823721, 0.823721, 0.823721, 0.823720",\ + "2.222145, 2.222145, 2.222145, 2.222145, 2.222145",\ + "0.129962, 0.129962, 0.129971, 0.130001, 0.130060",\ + "0.157855, 0.157855, 0.157861, 0.157880, 0.157920",\ + "0.203046, 0.203046, 0.203048, 0.203056, 0.203072",\ + "0.823721, 0.823721, 0.823721, 0.823721, 0.823720",\ + "2.222145, 2.222145, 2.222145, 2.222145, 2.222145",\ + "0.129962, 0.129962, 0.129971, 0.130001, 0.130060",\ + "0.157855, 0.157855, 0.157861, 0.157880, 0.157920",\ + "0.203046, 0.203046, 0.203048, 0.203056, 0.203072",\ + "0.823721, 0.823721, 0.823721, 0.823721, 0.823720",\ + "2.222145, 2.222145, 2.222145, 2.222145, 2.222145"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011"); + values ( "0.722294, 0.977326, 1.234104, 1.672832, 2.550288",\ + "0.735440, 0.990472, 1.247249, 1.685975, 2.563427",\ + "0.756591, 1.011623, 1.268399, 1.707123, 2.584570",\ + "0.932801, 1.187833, 1.444607, 1.883322, 2.760752",\ + "1.267115, 1.522147, 1.778921, 2.217637, 3.095068",\ + "0.809702, 1.064811, 1.321574, 1.759546, 2.636222",\ + "0.822848, 1.077956, 1.334719, 1.772689, 2.649361",\ + "0.843999, 1.099107, 1.355870, 1.793837, 2.670504",\ + "1.020210, 1.275318, 1.532078, 1.970036, 2.846686",\ + "1.354523, 1.609631, 1.866392, 2.304351, 3.181002",\ + "0.897387, 1.153634, 1.409536, 1.847168, 2.723177",\ + "0.910533, 1.166780, 1.422681, 1.860311, 2.736316",\ + "0.931684, 1.187931, 1.443832, 1.881459, 2.757459",\ + "1.107894, 1.364141, 1.620039, 2.057658, 2.933641",\ + "1.442208, 1.698455, 1.954353, 2.391973, 3.267957",\ + "0.960574, 1.219040, 1.473671, 1.911081, 2.786686",\ + "0.973719, 1.232186, 1.486816, 1.924224, 2.799825",\ + "0.994870, 1.253337, 1.507966, 1.945372, 2.820968",\ + "1.171081, 1.429547, 1.684174, 2.121571, 2.997150",\ + "1.505394, 1.763861, 2.018488, 2.455886, 3.331466",\ + "1.294055, 1.580776, 1.825230, 2.260301, 3.132142",\ + "1.307201, 1.593922, 1.838375, 2.273444, 3.145281",\ + "1.328352, 1.615073, 1.859525, 2.294591, 3.166424",\ + "1.504562, 1.791284, 2.035733, 2.470791, 3.342606",\ + "1.838876, 2.125597, 2.370047, 2.805105, 3.676922"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011"); + values ( "0.086495, 0.086495, 0.086490, 0.086470, 0.086430",\ + "0.090877, 0.090877, 0.090872, 0.090854, 0.090818",\ + "0.110245, 0.110245, 0.110240, 0.110223, 0.110189",\ + "0.380767, 0.380767, 0.380767, 0.380767, 0.380768",\ + "1.026303, 1.026303, 1.026303, 1.026305, 1.026307",\ + "0.086495, 0.086495, 0.086490, 0.086470, 0.086430",\ + "0.090877, 0.090877, 0.090872, 0.090854, 0.090818",\ + "0.110245, 0.110245, 0.110240, 0.110223, 0.110189",\ + "0.380767, 0.380767, 0.380767, 0.380767, 0.380768",\ + "1.026303, 1.026303, 1.026303, 1.026305, 1.026307",\ + "0.086495, 0.086495, 0.086490, 0.086470, 0.086430",\ + "0.090877, 0.090877, 0.090872, 0.090854, 0.090818",\ + "0.110245, 0.110245, 0.110240, 0.110223, 0.110189",\ + "0.380767, 0.380767, 0.380767, 0.380767, 0.380768",\ + "1.026303, 1.026303, 1.026303, 1.026305, 1.026307",\ + "0.086495, 0.086495, 0.086490, 0.086470, 0.086430",\ + "0.090877, 0.090877, 0.090872, 0.090854, 0.090818",\ + "0.110245, 0.110245, 0.110240, 0.110223, 0.110189",\ + "0.380767, 0.380767, 0.380767, 0.380767, 0.380768",\ + "1.026303, 1.026303, 1.026303, 1.026305, 1.026307",\ + "0.086495, 0.086495, 0.086489, 0.086470, 0.086430",\ + "0.090877, 0.090877, 0.090872, 0.090854, 0.090818",\ + "0.110245, 0.110245, 0.110240, 0.110223, 0.110189",\ + "0.380767, 0.380767, 0.380767, 0.380767, 0.380768",\ + "1.026303, 1.026303, 1.026303, 1.026305, 1.026307"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_2692*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[22]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.841286, 1.079720, 1.357044, 1.842422, 2.813178",\ + "0.855126, 1.093560, 1.370884, 1.856262, 2.827017",\ + "0.878637, 1.117071, 1.394394, 1.879772, 2.850528",\ + "1.147509, 1.385943, 1.663266, 2.148643, 3.119398",\ + "1.742037, 1.980471, 2.257795, 2.743171, 3.713924",\ + "0.928696, 1.167248, 1.444662, 1.929136, 2.899111",\ + "0.942536, 1.181088, 1.458502, 1.942976, 2.912951",\ + "0.966046, 1.204598, 1.482012, 1.966486, 2.936461",\ + "1.234918, 1.473470, 1.750884, 2.235358, 3.205331",\ + "1.829447, 2.067999, 2.345412, 2.829885, 3.799858",\ + "1.009558, 1.256174, 1.532627, 2.016758, 2.986066",\ + "1.023398, 1.270014, 1.546467, 2.030598, 2.999906",\ + "1.046908, 1.293524, 1.569977, 2.054108, 3.023416",\ + "1.315780, 1.562396, 1.838849, 2.322979, 3.292286",\ + "1.910309, 2.156925, 2.433377, 2.917507, 3.886813",\ + "1.067230, 1.321729, 1.596769, 2.080671, 3.049575",\ + "1.081070, 1.335569, 1.610609, 2.094511, 3.063415",\ + "1.104580, 1.359079, 1.634119, 2.118021, 3.086925",\ + "1.373452, 1.627951, 1.902991, 2.386893, 3.355795",\ + "1.967981, 2.222480, 2.497520, 2.981421, 3.950322",\ + "1.388249, 1.685192, 1.948802, 2.430085, 3.395031",\ + "1.402089, 1.699032, 1.962642, 2.443925, 3.408871",\ + "1.425600, 1.722542, 1.986153, 2.467435, 3.432381",\ + "1.694472, 1.991414, 2.255024, 2.736306, 3.701252",\ + "2.289001, 2.585943, 2.849553, 3.330834, 4.295778"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.129963, 0.129963, 0.129966, 0.129976, 0.129998",\ + "0.157855, 0.157855, 0.157857, 0.157864, 0.157879",\ + "0.203046, 0.203046, 0.203046, 0.203049, 0.203055",\ + "0.823721, 0.823721, 0.823721, 0.823721, 0.823721",\ + "2.222145, 2.222145, 2.222145, 2.222145, 2.222145",\ + "0.129963, 0.129963, 0.129966, 0.129976, 0.129998",\ + "0.157855, 0.157855, 0.157857, 0.157864, 0.157879",\ + "0.203046, 0.203046, 0.203046, 0.203049, 0.203055",\ + "0.823721, 0.823721, 0.823721, 0.823721, 0.823721",\ + "2.222145, 2.222145, 2.222145, 2.222145, 2.222145",\ + "0.129963, 0.129963, 0.129966, 0.129976, 0.129998",\ + "0.157855, 0.157855, 0.157857, 0.157864, 0.157879",\ + "0.203046, 0.203046, 0.203046, 0.203049, 0.203055",\ + "0.823721, 0.823721, 0.823721, 0.823721, 0.823721",\ + "2.222145, 2.222145, 2.222145, 2.222145, 2.222145",\ + "0.129963, 0.129963, 0.129966, 0.129976, 0.129998",\ + "0.157855, 0.157855, 0.157857, 0.157864, 0.157879",\ + "0.203046, 0.203046, 0.203046, 0.203049, 0.203055",\ + "0.823721, 0.823721, 0.823721, 0.823721, 0.823721",\ + "2.222145, 2.222145, 2.222145, 2.222145, 2.222145",\ + "0.129963, 0.129963, 0.129966, 0.129977, 0.129998",\ + "0.157855, 0.157855, 0.157857, 0.157864, 0.157879",\ + "0.203046, 0.203046, 0.203047, 0.203049, 0.203055",\ + "0.823721, 0.823721, 0.823721, 0.823721, 0.823721",\ + "2.222145, 2.222145, 2.222145, 2.222145, 2.222145"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.776372, 1.014807, 1.292131, 1.777511, 2.748272",\ + "0.789518, 1.027952, 1.305276, 1.790656, 2.761415",\ + "0.810669, 1.049103, 1.326427, 1.811806, 2.782563",\ + "0.986879, 1.225313, 1.502636, 1.988012, 2.958764",\ + "1.321193, 1.559627, 1.836950, 2.322326, 3.293078",\ + "0.863782, 1.102334, 1.379749, 1.864226, 2.834206",\ + "0.876927, 1.115480, 1.392894, 1.877370, 2.847349",\ + "0.898079, 1.136631, 1.414045, 1.898520, 2.868497",\ + "1.074289, 1.312841, 1.590254, 2.074727, 3.044697",\ + "1.408602, 1.647155, 1.924568, 2.409040, 3.379012",\ + "0.944644, 1.191260, 1.467714, 1.951848, 2.921161",\ + "0.957790, 1.204406, 1.480859, 1.964992, 2.934304",\ + "0.978941, 1.225557, 1.502010, 1.986142, 2.955452",\ + "1.155151, 1.401767, 1.678219, 2.162348, 3.131652",\ + "1.489465, 1.736081, 2.012533, 2.496662, 3.465967",\ + "1.002316, 1.256815, 1.531856, 2.015761, 2.984670",\ + "1.015462, 1.269960, 1.545001, 2.028905, 2.997813",\ + "1.036613, 1.291111, 1.566152, 2.050055, 3.018961",\ + "1.212823, 1.467322, 1.742362, 2.226262, 3.195161",\ + "1.547137, 1.801636, 2.076675, 2.560575, 3.529476",\ + "1.323336, 1.620278, 1.883889, 2.365174, 3.330126",\ + "1.336481, 1.633424, 1.897034, 2.378319, 3.343269",\ + "1.357632, 1.654575, 1.918185, 2.399469, 3.364417",\ + "1.533842, 1.830785, 2.094395, 2.575675, 3.540617",\ + "1.868156, 2.165099, 2.428709, 2.909989, 3.874932"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.086495, 0.086495, 0.086493, 0.086486, 0.086471",\ + "0.090877, 0.090877, 0.090875, 0.090868, 0.090855",\ + "0.110244, 0.110244, 0.110243, 0.110237, 0.110224",\ + "0.380767, 0.380767, 0.380767, 0.380767, 0.380767",\ + "1.026303, 1.026303, 1.026303, 1.026304, 1.026305",\ + "0.086495, 0.086495, 0.086493, 0.086486, 0.086471",\ + "0.090877, 0.090877, 0.090875, 0.090868, 0.090855",\ + "0.110244, 0.110244, 0.110243, 0.110237, 0.110224",\ + "0.380767, 0.380767, 0.380767, 0.380767, 0.380767",\ + "1.026303, 1.026303, 1.026303, 1.026304, 1.026305",\ + "0.086495, 0.086495, 0.086493, 0.086486, 0.086471",\ + "0.090877, 0.090877, 0.090875, 0.090868, 0.090855",\ + "0.110244, 0.110244, 0.110243, 0.110237, 0.110224",\ + "0.380767, 0.380767, 0.380767, 0.380767, 0.380767",\ + "1.026303, 1.026303, 1.026303, 1.026304, 1.026305",\ + "0.086495, 0.086495, 0.086493, 0.086486, 0.086471",\ + "0.090877, 0.090877, 0.090875, 0.090868, 0.090855",\ + "0.110244, 0.110244, 0.110243, 0.110237, 0.110224",\ + "0.380767, 0.380767, 0.380767, 0.380767, 0.380767",\ + "1.026303, 1.026303, 1.026303, 1.026304, 1.026305",\ + "0.086495, 0.086495, 0.086493, 0.086486, 0.086471",\ + "0.090877, 0.090877, 0.090875, 0.090868, 0.090855",\ + "0.110244, 0.110244, 0.110243, 0.110237, 0.110224",\ + "0.380767, 0.380767, 0.380767, 0.380767, 0.380767",\ + "1.026303, 1.026303, 1.026303, 1.026304, 1.026305"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[7]_redg*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[25]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011"); + values ( "0.798247, 1.048384, 1.323795, 1.814843, 2.796940",\ + "0.812087, 1.062224, 1.337635, 1.828683, 2.810778",\ + "0.835598, 1.085734, 1.361145, 1.852193, 2.834289",\ + "1.104470, 1.354606, 1.630016, 2.121061, 3.103152",\ + "1.698998, 1.949135, 2.224544, 2.715585, 3.697667",\ + "0.885653, 1.135896, 1.411429, 1.901557, 2.882874",\ + "0.899493, 1.149736, 1.425268, 1.915396, 2.896712",\ + "0.923003, 1.173246, 1.448779, 1.938907, 2.920223",\ + "1.191875, 1.442118, 1.717650, 2.207775, 3.189086",\ + "1.786403, 2.036647, 2.312177, 2.802298, 3.783601",\ + "0.966497, 1.224769, 1.499393, 1.989178, 2.969829",\ + "0.980337, 1.238609, 1.513233, 2.003017, 2.983667",\ + "1.003847, 1.262119, 1.536743, 2.026528, 3.007178",\ + "1.272719, 1.530991, 1.805614, 2.295396, 3.276041",\ + "1.867248, 2.125520, 2.400141, 2.889919, 3.870556",\ + "1.026473, 1.290246, 1.563536, 2.053091, 3.033338",\ + "1.040313, 1.304086, 1.577376, 2.066930, 3.047176",\ + "1.063823, 1.327596, 1.600886, 2.090441, 3.070687",\ + "1.332695, 1.596468, 1.869757, 2.359309, 3.339550",\ + "1.927224, 2.190996, 2.464285, 2.953832, 3.934065",\ + "1.363781, 1.652852, 1.915624, 2.402524, 3.378794",\ + "1.377621, 1.666692, 1.929464, 2.416363, 3.392632",\ + "1.401132, 1.690202, 1.952974, 2.439874, 3.416142",\ + "1.670003, 1.959074, 2.221846, 2.708742, 3.685006",\ + "2.264532, 2.553603, 2.816373, 3.303265, 4.279521"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011"); + values ( "0.129964, 0.129964, 0.129977, 0.130025, 0.130119",\ + "0.157856, 0.157856, 0.157865, 0.157896, 0.157959",\ + "0.203046, 0.203046, 0.203050, 0.203062, 0.203088",\ + "0.823721, 0.823721, 0.823721, 0.823720, 0.823720",\ + "2.222145, 2.222145, 2.222145, 2.222145, 2.222145",\ + "0.129964, 0.129964, 0.129978, 0.130025, 0.130119",\ + "0.157856, 0.157856, 0.157865, 0.157896, 0.157959",\ + "0.203046, 0.203046, 0.203050, 0.203062, 0.203088",\ + "0.823721, 0.823721, 0.823721, 0.823720, 0.823720",\ + "2.222145, 2.222145, 2.222145, 2.222145, 2.222145",\ + "0.129964, 0.129964, 0.129978, 0.130025, 0.130119",\ + "0.157856, 0.157856, 0.157865, 0.157896, 0.157959",\ + "0.203046, 0.203046, 0.203050, 0.203062, 0.203088",\ + "0.823721, 0.823721, 0.823721, 0.823720, 0.823720",\ + "2.222145, 2.222145, 2.222145, 2.222145, 2.222145",\ + "0.129964, 0.129964, 0.129978, 0.130025, 0.130119",\ + "0.157856, 0.157856, 0.157865, 0.157896, 0.157959",\ + "0.203046, 0.203046, 0.203050, 0.203062, 0.203088",\ + "0.823721, 0.823721, 0.823721, 0.823720, 0.823720",\ + "2.222145, 2.222145, 2.222145, 2.222145, 2.222145",\ + "0.129964, 0.129964, 0.129978, 0.130025, 0.130119",\ + "0.157856, 0.157856, 0.157865, 0.157896, 0.157959",\ + "0.203046, 0.203046, 0.203050, 0.203062, 0.203088",\ + "0.823721, 0.823721, 0.823721, 0.823720, 0.823720",\ + "2.222145, 2.222145, 2.222145, 2.222145, 2.222145"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011"); + values ( "0.733334, 0.983470, 1.258885, 1.749946, 2.732069",\ + "0.746479, 0.996616, 1.272029, 1.763087, 2.745203",\ + "0.767630, 1.017767, 1.293179, 1.784232, 2.766337",\ + "0.943840, 1.193977, 1.469384, 1.960422, 2.942497",\ + "1.278154, 1.528290, 1.803698, 2.294737, 3.276814",\ + "0.820739, 1.070982, 1.346519, 1.836660, 2.818002",\ + "0.833884, 1.084128, 1.359663, 1.849801, 2.831136",\ + "0.855036, 1.105279, 1.380813, 1.870946, 2.852271",\ + "1.031245, 1.281489, 1.557018, 2.047136, 3.028431",\ + "1.365559, 1.615803, 1.891332, 2.381451, 3.362748",\ + "0.901583, 1.159855, 1.434483, 1.924281, 2.904958",\ + "0.914729, 1.173001, 1.447627, 1.937422, 2.918091",\ + "0.935880, 1.194152, 1.468777, 1.958567, 2.939226",\ + "1.112090, 1.370362, 1.644982, 2.134757, 3.115386",\ + "1.446404, 1.704675, 1.979296, 2.469072, 3.449703",\ + "0.961559, 1.225332, 1.498626, 1.988194, 2.968467",\ + "0.974705, 1.238478, 1.511771, 2.001335, 2.981600",\ + "0.995856, 1.259629, 1.532920, 2.022480, 3.002735",\ + "1.172065, 1.435838, 1.709126, 2.198669, 3.178895",\ + "1.506379, 1.770152, 2.043440, 2.532985, 3.513212",\ + "1.298868, 1.587939, 1.850715, 2.337627, 3.313922",\ + "1.312013, 1.601084, 1.863859, 2.350768, 3.327056",\ + "1.333164, 1.622235, 1.885009, 2.371913, 3.348191",\ + "1.509374, 1.798445, 2.061214, 2.548103, 3.524351",\ + "1.843688, 2.132759, 2.395528, 2.882418, 3.858668"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011"); + values ( "0.086494, 0.086494, 0.086484, 0.086448, 0.086375",\ + "0.090876, 0.090876, 0.090867, 0.090834, 0.090768",\ + "0.110244, 0.110244, 0.110235, 0.110204, 0.110143",\ + "0.380767, 0.380767, 0.380767, 0.380767, 0.380768",\ + "1.026303, 1.026303, 1.026304, 1.026306, 1.026310",\ + "0.086494, 0.086494, 0.086484, 0.086448, 0.086375",\ + "0.090876, 0.090876, 0.090867, 0.090834, 0.090768",\ + "0.110244, 0.110244, 0.110235, 0.110204, 0.110143",\ + "0.380767, 0.380767, 0.380767, 0.380767, 0.380768",\ + "1.026303, 1.026303, 1.026304, 1.026306, 1.026310",\ + "0.086494, 0.086494, 0.086484, 0.086448, 0.086375",\ + "0.090876, 0.090876, 0.090867, 0.090834, 0.090768",\ + "0.110244, 0.110244, 0.110235, 0.110204, 0.110143",\ + "0.380767, 0.380767, 0.380767, 0.380767, 0.380768",\ + "1.026303, 1.026303, 1.026304, 1.026306, 1.026310",\ + "0.086494, 0.086494, 0.086484, 0.086448, 0.086375",\ + "0.090876, 0.090876, 0.090867, 0.090834, 0.090768",\ + "0.110244, 0.110244, 0.110235, 0.110204, 0.110143",\ + "0.380767, 0.380767, 0.380767, 0.380767, 0.380768",\ + "1.026303, 1.026303, 1.026304, 1.026306, 1.026310",\ + "0.086494, 0.086494, 0.086483, 0.086447, 0.086375",\ + "0.090876, 0.090876, 0.090866, 0.090834, 0.090768",\ + "0.110244, 0.110244, 0.110234, 0.110204, 0.110143",\ + "0.380767, 0.380767, 0.380767, 0.380767, 0.380768",\ + "1.026303, 1.026303, 1.026304, 1.026306, 1.026310"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_2506*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[29]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.669029, 0.924047, 1.180422, 1.619320, 2.497118",\ + "0.682742, 0.937760, 1.194134, 1.633031, 2.510826",\ + "0.706267, 0.961286, 1.217660, 1.656557, 2.534352",\ + "0.974450, 1.229468, 1.485840, 1.924731, 2.802514",\ + "1.567911, 1.822930, 2.079299, 2.518181, 3.395944",\ + "0.756434, 1.011535, 1.267892, 1.706034, 2.583051",\ + "0.770147, 1.025247, 1.281604, 1.719745, 2.596760",\ + "0.793673, 1.048773, 1.305130, 1.743271, 2.620286",\ + "1.061855, 1.316955, 1.573310, 2.011445, 2.888448",\ + "1.655316, 1.910417, 2.166769, 2.604894, 3.481877",\ + "0.844902, 1.100352, 1.355853, 1.793655, 2.670006",\ + "0.858615, 1.114065, 1.369565, 1.807366, 2.683715",\ + "0.882141, 1.137591, 1.393091, 1.830892, 2.707241",\ + "1.150323, 1.405773, 1.661271, 2.099066, 2.975403",\ + "1.743784, 1.999234, 2.254730, 2.692515, 3.568832",\ + "0.908398, 1.165749, 1.419987, 1.857568, 2.733515",\ + "0.922111, 1.179461, 1.433699, 1.871279, 2.747224",\ + "0.945637, 1.202987, 1.457225, 1.894805, 2.770750",\ + "1.213819, 1.471169, 1.725405, 2.162979, 3.038912",\ + "1.807280, 2.064631, 2.318864, 2.756428, 3.632341",\ + "1.243831, 1.527415, 1.771546, 2.206786, 3.078971",\ + "1.257544, 1.541128, 1.785259, 2.220497, 3.092680",\ + "1.281070, 1.564654, 1.808785, 2.244023, 3.116206",\ + "1.549252, 1.832836, 2.076965, 2.512197, 3.384368",\ + "2.142714, 2.426297, 2.670424, 3.105646, 3.977798"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.126073, 0.126073, 0.126073, 0.126072, 0.126070",\ + "0.155270, 0.155270, 0.155270, 0.155269, 0.155268",\ + "0.202000, 0.202000, 0.202000, 0.201999, 0.201999",\ + "0.823664, 0.823664, 0.823664, 0.823664, 0.823663",\ + "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\ + "0.126073, 0.126073, 0.126073, 0.126072, 0.126070",\ + "0.155270, 0.155270, 0.155270, 0.155269, 0.155268",\ + "0.202000, 0.202000, 0.202000, 0.201999, 0.201999",\ + "0.823664, 0.823664, 0.823664, 0.823664, 0.823663",\ + "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\ + "0.126073, 0.126073, 0.126073, 0.126072, 0.126070",\ + "0.155270, 0.155270, 0.155270, 0.155269, 0.155268",\ + "0.202000, 0.202000, 0.202000, 0.201999, 0.201999",\ + "0.823664, 0.823664, 0.823664, 0.823664, 0.823663",\ + "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\ + "0.126073, 0.126073, 0.126073, 0.126072, 0.126070",\ + "0.155270, 0.155270, 0.155270, 0.155269, 0.155268",\ + "0.202000, 0.202000, 0.202000, 0.201999, 0.201999",\ + "0.823664, 0.823664, 0.823664, 0.823664, 0.823663",\ + "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\ + "0.126073, 0.126073, 0.126073, 0.126072, 0.126070",\ + "0.155270, 0.155270, 0.155270, 0.155269, 0.155268",\ + "0.202000, 0.202000, 0.202000, 0.201999, 0.201999",\ + "0.823664, 0.823664, 0.823664, 0.823664, 0.823663",\ + "2.222140, 2.222140, 2.222140, 2.222140, 2.222140"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.607434, 0.862452, 1.118835, 1.557764, 2.435622",\ + "0.619657, 0.874676, 1.131056, 1.569977, 2.447818",\ + "0.639561, 0.894580, 1.150957, 1.589866, 2.467684",\ + "0.811812, 1.066830, 1.323197, 1.762070, 2.639816",\ + "1.146382, 1.401400, 1.657768, 2.096643, 2.974393",\ + "0.694839, 0.949939, 1.206305, 1.644478, 2.521555",\ + "0.707062, 0.962163, 1.218526, 1.656691, 2.533751",\ + "0.726967, 0.982067, 1.238427, 1.676580, 2.553618",\ + "0.899217, 1.154317, 1.410667, 1.848784, 2.725749",\ + "1.233787, 1.488888, 1.745238, 2.183357, 3.060327",\ + "0.783307, 1.038757, 1.294266, 1.732099, 2.608510",\ + "0.795531, 1.050981, 1.306487, 1.744312, 2.620707",\ + "0.815435, 1.070885, 1.326388, 1.764201, 2.640573",\ + "0.987685, 1.243135, 1.498628, 1.936405, 2.812705",\ + "1.322255, 1.577705, 1.833199, 2.270978, 3.147282",\ + "0.846803, 1.104153, 1.358401, 1.796012, 2.672019",\ + "0.859026, 1.116377, 1.370622, 1.808224, 2.684216",\ + "0.878930, 1.136281, 1.390523, 1.828114, 2.704082",\ + "1.051181, 1.308532, 1.562762, 2.000318, 2.876214",\ + "1.385751, 1.643102, 1.897333, 2.334891, 3.210791",\ + "1.182236, 1.465820, 1.709960, 2.145230, 3.017476",\ + "1.194460, 1.478043, 1.722182, 2.157442, 3.029672",\ + "1.214364, 1.497947, 1.742082, 2.177332, 3.049538",\ + "1.386614, 1.670198, 1.914322, 2.349535, 3.221670",\ + "1.721184, 2.004768, 2.248892, 2.684108, 3.556247"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.077163, 0.077163, 0.077138, 0.077052, 0.076882",\ + "0.082420, 0.082420, 0.082398, 0.082320, 0.082166",\ + "0.102329, 0.102329, 0.102308, 0.102236, 0.102091",\ + "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\ + "1.026132, 1.026132, 1.026132, 1.026132, 1.026132",\ + "0.077163, 0.077163, 0.077137, 0.077052, 0.076882",\ + "0.082420, 0.082420, 0.082397, 0.082320, 0.082166",\ + "0.102329, 0.102329, 0.102308, 0.102236, 0.102091",\ + "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\ + "1.026132, 1.026132, 1.026132, 1.026132, 1.026132",\ + "0.077163, 0.077163, 0.077137, 0.077052, 0.076882",\ + "0.082420, 0.082420, 0.082397, 0.082320, 0.082166",\ + "0.102329, 0.102329, 0.102308, 0.102236, 0.102091",\ + "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\ + "1.026132, 1.026132, 1.026132, 1.026132, 1.026132",\ + "0.077163, 0.077163, 0.077137, 0.077052, 0.076882",\ + "0.082420, 0.082420, 0.082397, 0.082320, 0.082166",\ + "0.102329, 0.102329, 0.102308, 0.102236, 0.102091",\ + "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\ + "1.026132, 1.026132, 1.026132, 1.026132, 1.026132",\ + "0.077163, 0.077163, 0.077137, 0.077052, 0.076882",\ + "0.082420, 0.082420, 0.082397, 0.082320, 0.082166",\ + "0.102329, 0.102329, 0.102307, 0.102236, 0.102091",\ + "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\ + "1.026132, 1.026132, 1.026132, 1.026132, 1.026132"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_2663*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[30]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.646825, 0.888812, 1.155481, 1.637557, 2.601710",\ + "0.660538, 0.902524, 1.169192, 1.651265, 2.615411",\ + "0.684064, 0.926050, 1.192718, 1.674791, 2.638938",\ + "0.952246, 1.194231, 1.460892, 1.942948, 2.907060",\ + "1.545707, 1.787690, 2.054341, 2.536369, 3.500427",\ + "0.734227, 0.976289, 1.243085, 1.724270, 2.687644",\ + "0.747939, 0.990001, 1.256796, 1.737978, 2.701345",\ + "0.771465, 1.013527, 1.280322, 1.761504, 2.724872",\ + "1.039647, 1.281708, 1.548496, 2.029661, 2.992994",\ + "1.633109, 1.875167, 2.141944, 2.623083, 3.586361",\ + "0.815033, 1.065071, 1.331047, 1.811891, 2.774599",\ + "0.828746, 1.078784, 1.344759, 1.825599, 2.788300",\ + "0.852272, 1.102309, 1.368284, 1.849125, 2.811827",\ + "1.120454, 1.370490, 1.636458, 2.117281, 3.079949",\ + "1.713915, 1.963950, 2.229907, 2.710703, 3.673316",\ + "0.875218, 1.130416, 1.395189, 1.875803, 2.838108",\ + "0.888931, 1.144128, 1.408900, 1.889511, 2.851809",\ + "0.912457, 1.167654, 1.432426, 1.913038, 2.875336",\ + "1.180639, 1.435834, 1.700600, 2.181194, 3.143458",\ + "1.774100, 2.029294, 2.294049, 2.774616, 3.736825",\ + "1.213104, 1.491515, 1.747184, 2.225196, 3.183564",\ + "1.226817, 1.505228, 1.760895, 2.238904, 3.197265",\ + "1.250343, 1.528753, 1.784421, 2.262430, 3.220792",\ + "1.518525, 1.796934, 2.052595, 2.530586, 3.488914",\ + "2.111986, 2.390392, 2.646044, 3.124008, 4.082281"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.126070, 0.126070, 0.126065, 0.126046, 0.126010",\ + "0.155268, 0.155268, 0.155265, 0.155253, 0.155228",\ + "0.201999, 0.201999, 0.201998, 0.201993, 0.201983",\ + "0.823664, 0.823664, 0.823664, 0.823662, 0.823659",\ + "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\ + "0.126070, 0.126070, 0.126065, 0.126046, 0.126010",\ + "0.155268, 0.155268, 0.155265, 0.155253, 0.155228",\ + "0.201999, 0.201999, 0.201998, 0.201993, 0.201983",\ + "0.823664, 0.823664, 0.823664, 0.823662, 0.823659",\ + "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\ + "0.126070, 0.126070, 0.126065, 0.126046, 0.126010",\ + "0.155268, 0.155268, 0.155265, 0.155253, 0.155228",\ + "0.201999, 0.201999, 0.201998, 0.201993, 0.201983",\ + "0.823664, 0.823664, 0.823664, 0.823662, 0.823659",\ + "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\ + "0.126070, 0.126070, 0.126065, 0.126046, 0.126010",\ + "0.155268, 0.155268, 0.155265, 0.155253, 0.155228",\ + "0.201999, 0.201999, 0.201998, 0.201993, 0.201983",\ + "0.823664, 0.823664, 0.823664, 0.823662, 0.823659",\ + "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\ + "0.126070, 0.126070, 0.126065, 0.126046, 0.126010",\ + "0.155268, 0.155268, 0.155265, 0.155253, 0.155228",\ + "0.201999, 0.201999, 0.201998, 0.201993, 0.201983",\ + "0.823664, 0.823664, 0.823664, 0.823662, 0.823659",\ + "2.222140, 2.222140, 2.222140, 2.222140, 2.222140"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.585231, 0.827223, 1.093925, 1.576086, 2.540408",\ + "0.597454, 0.839445, 1.106138, 1.588275, 2.552550",\ + "0.617358, 0.859347, 1.126027, 1.608132, 2.572344",\ + "0.789607, 1.031589, 1.298230, 1.780235, 2.744245",\ + "1.124177, 1.366160, 1.632803, 2.114814, 3.078838",\ + "0.672632, 0.914701, 1.181530, 1.662799, 2.626341",\ + "0.684856, 0.926922, 1.193742, 1.674988, 2.638484",\ + "0.704759, 0.946824, 1.213631, 1.694846, 2.658278",\ + "0.877009, 1.119066, 1.385834, 1.866948, 2.830179",\ + "1.211579, 1.453637, 1.720407, 2.201528, 3.164772",\ + "0.753439, 1.003483, 1.269492, 1.750420, 2.713296",\ + "0.765663, 1.015705, 1.281705, 1.762609, 2.725439",\ + "0.785566, 1.035606, 1.301594, 1.782466, 2.745233",\ + "0.957816, 1.207848, 1.473796, 1.954568, 2.917134",\ + "1.292386, 1.542419, 1.808370, 2.289148, 3.251727",\ + "0.813624, 1.068828, 1.333634, 1.814332, 2.776805",\ + "0.825847, 1.081049, 1.345847, 1.826521, 2.788948",\ + "0.845751, 1.100950, 1.365736, 1.846379, 2.808742",\ + "1.018000, 1.273192, 1.537938, 2.018481, 2.980643",\ + "1.352571, 1.607763, 1.872511, 2.353061, 3.315236",\ + "1.151510, 1.429929, 1.685630, 2.163725, 3.122262",\ + "1.163733, 1.442150, 1.697842, 2.175914, 3.134404",\ + "1.183637, 1.462051, 1.717731, 2.195772, 3.154198",\ + "1.355886, 1.634290, 1.889933, 2.367873, 3.326099",\ + "1.690457, 1.968861, 2.224506, 2.702453, 3.660692"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.077160, 0.077143, 0.077050, 0.076813, 0.076339",\ + "0.082418, 0.082403, 0.082319, 0.082104, 0.081674",\ + "0.102327, 0.102313, 0.102234, 0.102033, 0.101631",\ + "0.380733, 0.380733, 0.380733, 0.380733, 0.380732",\ + "1.026132, 1.026132, 1.026131, 1.026130, 1.026129",\ + "0.077160, 0.077143, 0.077050, 0.076813, 0.076339",\ + "0.082418, 0.082403, 0.082318, 0.082104, 0.081674",\ + "0.102327, 0.102313, 0.102234, 0.102033, 0.101631",\ + "0.380733, 0.380733, 0.380733, 0.380733, 0.380732",\ + "1.026132, 1.026132, 1.026131, 1.026130, 1.026129",\ + "0.077160, 0.077143, 0.077050, 0.076813, 0.076339",\ + "0.082418, 0.082402, 0.082318, 0.082104, 0.081674",\ + "0.102327, 0.102313, 0.102234, 0.102033, 0.101631",\ + "0.380733, 0.380733, 0.380733, 0.380733, 0.380732",\ + "1.026132, 1.026132, 1.026131, 1.026130, 1.026129",\ + "0.077160, 0.077142, 0.077050, 0.076813, 0.076339",\ + "0.082418, 0.082402, 0.082318, 0.082104, 0.081674",\ + "0.102327, 0.102312, 0.102234, 0.102033, 0.101631",\ + "0.380733, 0.380733, 0.380733, 0.380733, 0.380732",\ + "1.026132, 1.026132, 1.026131, 1.026130, 1.026129",\ + "0.077160, 0.077137, 0.077047, 0.076812, 0.076339",\ + "0.082418, 0.082397, 0.082316, 0.082103, 0.081674",\ + "0.102327, 0.102307, 0.102232, 0.102032, 0.101631",\ + "0.380733, 0.380733, 0.380733, 0.380733, 0.380732",\ + "1.026132, 1.026132, 1.026131, 1.026130, 1.026129"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_2738*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[34]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011"); + values ( "0.837009, 1.103664, 1.394023, 1.889858, 2.881526",\ + "0.850722, 1.117377, 1.407736, 1.903570, 2.895239",\ + "0.874247, 1.140903, 1.431262, 1.927096, 2.918765",\ + "1.142429, 1.409085, 1.699444, 2.195278, 3.186947",\ + "1.735891, 2.002547, 2.292906, 2.788740, 3.780409",\ + "0.924420, 1.191252, 1.481675, 1.976572, 2.967460",\ + "0.938133, 1.204965, 1.495388, 1.990285, 2.981173",\ + "0.961659, 1.228491, 1.518914, 2.013811, 3.004699",\ + "1.229841, 1.496673, 1.787096, 2.281993, 3.272881",\ + "1.823303, 2.090135, 2.380557, 2.875455, 3.866343",\ + "1.005339, 1.280324, 1.569641, 2.064194, 3.054415",\ + "1.019052, 1.294036, 1.583354, 2.077907, 3.068128",\ + "1.042578, 1.317562, 1.606879, 2.101433, 3.091654",\ + "1.310760, 1.585744, 1.875061, 2.369615, 3.359836",\ + "1.904221, 2.179206, 2.468523, 2.963077, 3.953298",\ + "1.066406, 1.346091, 1.633785, 2.128108, 3.117924",\ + "1.080119, 1.359803, 1.647498, 2.141821, 3.131637",\ + "1.103644, 1.383329, 1.671023, 2.165346, 3.155163",\ + "1.371826, 1.651511, 1.939205, 2.433528, 3.423345",\ + "1.965288, 2.244973, 2.532667, 3.026990, 4.016807",\ + "1.402561, 1.712010, 1.985925, 2.477567, 3.463380",\ + "1.416273, 1.725723, 1.999638, 2.491279, 3.477093",\ + "1.439799, 1.749248, 2.023164, 2.514805, 3.500619",\ + "1.707981, 2.017431, 2.291346, 2.782987, 3.768801",\ + "2.301443, 2.610892, 2.884808, 3.376449, 4.362263"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011"); + values ( "0.126073, 0.126073, 0.126073, 0.126073, 0.126073",\ + "0.155270, 0.155270, 0.155270, 0.155270, 0.155270",\ + "0.202000, 0.202000, 0.202000, 0.202000, 0.202000",\ + "0.823664, 0.823664, 0.823664, 0.823664, 0.823664",\ + "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\ + "0.126073, 0.126073, 0.126073, 0.126073, 0.126073",\ + "0.155270, 0.155270, 0.155270, 0.155270, 0.155270",\ + "0.202000, 0.202000, 0.202000, 0.202000, 0.202000",\ + "0.823664, 0.823664, 0.823664, 0.823664, 0.823664",\ + "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\ + "0.126073, 0.126073, 0.126073, 0.126073, 0.126073",\ + "0.155270, 0.155270, 0.155270, 0.155270, 0.155270",\ + "0.202000, 0.202000, 0.202000, 0.202000, 0.202000",\ + "0.823664, 0.823664, 0.823664, 0.823664, 0.823664",\ + "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\ + "0.126073, 0.126073, 0.126073, 0.126073, 0.126073",\ + "0.155270, 0.155270, 0.155270, 0.155270, 0.155270",\ + "0.202000, 0.202000, 0.202000, 0.202000, 0.202000",\ + "0.823664, 0.823664, 0.823664, 0.823664, 0.823664",\ + "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\ + "0.126073, 0.126073, 0.126073, 0.126073, 0.126073",\ + "0.155270, 0.155270, 0.155270, 0.155270, 0.155270",\ + "0.202000, 0.202000, 0.202000, 0.202000, 0.202000",\ + "0.823664, 0.823664, 0.823664, 0.823664, 0.823664",\ + "2.222140, 2.222140, 2.222140, 2.222140, 2.222140"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011"); + values ( "0.775414, 1.042069, 1.332428, 1.828263, 2.819932",\ + "0.787637, 1.054293, 1.344652, 1.840486, 2.832155",\ + "0.807541, 1.074197, 1.364556, 1.860390, 2.852059",\ + "0.979792, 1.246447, 1.536806, 2.032640, 3.024309",\ + "1.314362, 1.581017, 1.871376, 2.367211, 3.358880",\ + "0.862825, 1.129657, 1.420080, 1.914977, 2.905865",\ + "0.875049, 1.141881, 1.432303, 1.927201, 2.918089",\ + "0.894953, 1.161785, 1.452208, 1.947105, 2.937993",\ + "1.067203, 1.334035, 1.624458, 2.119355, 3.110243",\ + "1.401773, 1.668605, 1.959028, 2.453925, 3.444813",\ + "0.943744, 1.218729, 1.508046, 2.002599, 2.992820",\ + "0.955968, 1.230952, 1.520269, 2.014823, 3.005044",\ + "0.975872, 1.250856, 1.540173, 2.034727, 3.024948",\ + "1.148122, 1.423107, 1.712424, 2.206977, 3.197198",\ + "1.482692, 1.757677, 2.046994, 2.541547, 3.531768",\ + "1.004811, 1.284495, 1.572190, 2.066513, 3.056329",\ + "1.017034, 1.296719, 1.584413, 2.078736, 3.068553",\ + "1.036938, 1.316623, 1.604317, 2.098640, 3.088457",\ + "1.209189, 1.488873, 1.776568, 2.270891, 3.260707",\ + "1.543759, 1.823443, 2.111138, 2.605461, 3.595277",\ + "1.340966, 1.650415, 1.924330, 2.415972, 3.401785",\ + "1.353189, 1.662638, 1.936553, 2.428195, 3.414009",\ + "1.373093, 1.682542, 1.956458, 2.448099, 3.433913",\ + "1.545344, 1.854793, 2.128708, 2.620349, 3.606163",\ + "1.879914, 2.189363, 2.463278, 2.954920, 3.940733"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011"); + values ( "0.077162, 0.077162, 0.077162, 0.077162, 0.077162",\ + "0.082420, 0.082420, 0.082420, 0.082420, 0.082420",\ + "0.102329, 0.102329, 0.102329, 0.102329, 0.102329",\ + "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\ + "1.026132, 1.026132, 1.026132, 1.026132, 1.026132",\ + "0.077162, 0.077162, 0.077162, 0.077162, 0.077162",\ + "0.082420, 0.082420, 0.082420, 0.082420, 0.082420",\ + "0.102329, 0.102329, 0.102329, 0.102329, 0.102329",\ + "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\ + "1.026132, 1.026132, 1.026132, 1.026132, 1.026132",\ + "0.077162, 0.077162, 0.077162, 0.077162, 0.077162",\ + "0.082420, 0.082420, 0.082420, 0.082420, 0.082420",\ + "0.102329, 0.102329, 0.102329, 0.102329, 0.102329",\ + "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\ + "1.026132, 1.026132, 1.026132, 1.026132, 1.026132",\ + "0.077162, 0.077162, 0.077162, 0.077162, 0.077162",\ + "0.082420, 0.082420, 0.082420, 0.082420, 0.082420",\ + "0.102329, 0.102329, 0.102329, 0.102329, 0.102329",\ + "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\ + "1.026132, 1.026132, 1.026132, 1.026132, 1.026132",\ + "0.077162, 0.077162, 0.077162, 0.077162, 0.077162",\ + "0.082420, 0.082420, 0.082420, 0.082420, 0.082420",\ + "0.102329, 0.102329, 0.102329, 0.102329, 0.102329",\ + "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\ + "1.026132, 1.026132, 1.026132, 1.026132, 1.026132"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_2382*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[35]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.820636, 1.072596, 1.352895, 1.817949, 2.748057",\ + "0.834349, 1.086309, 1.366608, 1.831662, 2.761770",\ + "0.857874, 1.109835, 1.390133, 1.855188, 2.785295",\ + "1.126056, 1.378017, 1.658316, 2.123370, 3.053478",\ + "1.719518, 1.971479, 2.251777, 2.716831, 3.646940",\ + "0.908045, 1.160181, 1.440449, 1.904663, 2.833991",\ + "0.921758, 1.173894, 1.454162, 1.918376, 2.847703",\ + "0.945284, 1.197419, 1.477687, 1.941902, 2.871229",\ + "1.213466, 1.465601, 1.745869, 2.210084, 3.139411",\ + "1.806928, 2.059063, 2.339331, 2.803546, 3.732873",\ + "0.988950, 1.249236, 1.528412, 1.992285, 2.920946",\ + "1.002662, 1.262948, 1.542125, 2.005998, 2.934659",\ + "1.026188, 1.286474, 1.565651, 2.029524, 2.958184",\ + "1.294370, 1.554656, 1.833833, 2.297706, 3.226367",\ + "1.887832, 2.148118, 2.427295, 2.891167, 3.819828",\ + "1.046704, 1.314977, 1.592551, 2.056198, 2.984455",\ + "1.060416, 1.328690, 1.606264, 2.069911, 2.998168",\ + "1.083942, 1.352216, 1.629790, 2.093437, 3.021693",\ + "1.352124, 1.620398, 1.897972, 2.361619, 3.289876",\ + "1.945586, 2.213860, 2.491434, 2.955081, 3.883337",\ + "1.375818, 1.680630, 1.944378, 2.405528, 3.329911",\ + "1.389531, 1.694343, 1.958091, 2.419240, 3.343624",\ + "1.413056, 1.717869, 1.981617, 2.442766, 3.367149",\ + "1.681239, 1.986051, 2.249799, 2.710948, 3.635332",\ + "2.274700, 2.579513, 2.843261, 3.304410, 4.228793"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.126073, 0.126073, 0.126073, 0.126073, 0.126073",\ + "0.155270, 0.155270, 0.155270, 0.155270, 0.155270",\ + "0.202000, 0.202000, 0.202000, 0.202000, 0.202000",\ + "0.823664, 0.823664, 0.823664, 0.823664, 0.823664",\ + "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\ + "0.126073, 0.126073, 0.126073, 0.126073, 0.126073",\ + "0.155270, 0.155270, 0.155270, 0.155270, 0.155270",\ + "0.202000, 0.202000, 0.202000, 0.202000, 0.202000",\ + "0.823664, 0.823664, 0.823664, 0.823664, 0.823664",\ + "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\ + "0.126073, 0.126073, 0.126073, 0.126073, 0.126073",\ + "0.155270, 0.155270, 0.155270, 0.155270, 0.155270",\ + "0.202000, 0.202000, 0.202000, 0.202000, 0.202000",\ + "0.823664, 0.823664, 0.823664, 0.823664, 0.823664",\ + "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\ + "0.126073, 0.126073, 0.126073, 0.126073, 0.126073",\ + "0.155270, 0.155270, 0.155270, 0.155270, 0.155270",\ + "0.202000, 0.202000, 0.202000, 0.202000, 0.202000",\ + "0.823664, 0.823664, 0.823664, 0.823664, 0.823664",\ + "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\ + "0.126073, 0.126073, 0.126073, 0.126073, 0.126073",\ + "0.155270, 0.155270, 0.155270, 0.155270, 0.155270",\ + "0.202000, 0.202000, 0.202000, 0.202000, 0.202000",\ + "0.823664, 0.823664, 0.823664, 0.823664, 0.823664",\ + "2.222140, 2.222140, 2.222140, 2.222140, 2.222140"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.759041, 1.011001, 1.291300, 1.756354, 2.686462",\ + "0.771264, 1.023225, 1.303523, 1.768578, 2.698686",\ + "0.791168, 1.043129, 1.323427, 1.788481, 2.718590",\ + "0.963419, 1.215379, 1.495678, 1.960732, 2.890840",\ + "1.297989, 1.549949, 1.830248, 2.295302, 3.225410",\ + "0.846450, 1.098586, 1.378854, 1.843068, 2.772396",\ + "0.858674, 1.110809, 1.391077, 1.855292, 2.784619",\ + "0.878578, 1.130713, 1.410981, 1.875196, 2.804523",\ + "1.050828, 1.302964, 1.583232, 2.047446, 2.976774",\ + "1.385398, 1.637534, 1.917802, 2.382016, 3.311344",\ + "0.927355, 1.187640, 1.466817, 1.930690, 2.859351",\ + "0.939578, 1.199864, 1.479041, 1.942914, 2.871574",\ + "0.959482, 1.219768, 1.498945, 1.962818, 2.891478",\ + "1.131733, 1.392018, 1.671195, 2.135068, 3.063729",\ + "1.466303, 1.726588, 2.005765, 2.469638, 3.398299",\ + "0.985108, 1.253382, 1.530956, 1.994603, 2.922860",\ + "0.997332, 1.265606, 1.543180, 2.006827, 2.935083",\ + "1.017236, 1.285510, 1.563084, 2.026731, 2.954987",\ + "1.189487, 1.457760, 1.735334, 2.198981, 3.127238",\ + "1.524057, 1.792330, 2.069904, 2.533551, 3.461808",\ + "1.314223, 1.619035, 1.882783, 2.343933, 3.268316",\ + "1.326446, 1.631259, 1.895007, 2.356156, 3.280540",\ + "1.346350, 1.651163, 1.914911, 2.376060, 3.300443",\ + "1.518601, 1.823413, 2.087161, 2.548311, 3.472694",\ + "1.853171, 2.157983, 2.421731, 2.882881, 3.807264"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.077162, 0.077162, 0.077162, 0.077162, 0.077162",\ + "0.082420, 0.082420, 0.082420, 0.082420, 0.082420",\ + "0.102329, 0.102329, 0.102329, 0.102329, 0.102329",\ + "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\ + "1.026132, 1.026132, 1.026132, 1.026132, 1.026132",\ + "0.077162, 0.077162, 0.077162, 0.077162, 0.077162",\ + "0.082420, 0.082420, 0.082420, 0.082420, 0.082420",\ + "0.102329, 0.102329, 0.102329, 0.102329, 0.102329",\ + "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\ + "1.026132, 1.026132, 1.026132, 1.026132, 1.026132",\ + "0.077162, 0.077162, 0.077162, 0.077162, 0.077162",\ + "0.082420, 0.082420, 0.082420, 0.082420, 0.082420",\ + "0.102329, 0.102329, 0.102329, 0.102329, 0.102329",\ + "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\ + "1.026132, 1.026132, 1.026132, 1.026132, 1.026132",\ + "0.077162, 0.077162, 0.077162, 0.077162, 0.077162",\ + "0.082420, 0.082420, 0.082420, 0.082420, 0.082420",\ + "0.102329, 0.102329, 0.102329, 0.102329, 0.102329",\ + "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\ + "1.026132, 1.026132, 1.026132, 1.026132, 1.026132",\ + "0.077162, 0.077162, 0.077162, 0.077162, 0.077162",\ + "0.082420, 0.082420, 0.082420, 0.082420, 0.082420",\ + "0.102329, 0.102329, 0.102329, 0.102329, 0.102329",\ + "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\ + "1.026132, 1.026132, 1.026132, 1.026132, 1.026132"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_2443*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[38]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.834699, 1.095622, 1.384637, 1.885838, 2.888237",\ + "0.848411, 1.109334, 1.398350, 1.899550, 2.901949",\ + "0.871937, 1.132860, 1.421876, 1.923076, 2.925475",\ + "1.140119, 1.401042, 1.690057, 2.191256, 3.193652",\ + "1.733580, 1.994503, 2.283517, 2.784714, 3.787106",\ + "0.922107, 1.183198, 1.472305, 1.972552, 2.974171",\ + "0.935819, 1.196910, 1.486017, 1.986264, 2.987883",\ + "0.959345, 1.220436, 1.509543, 2.009790, 3.011409",\ + "1.227527, 1.488618, 1.777724, 2.277970, 3.279586",\ + "1.820988, 2.082079, 2.371185, 2.871428, 3.873040",\ + "1.002997, 1.272227, 1.560270, 2.060173, 3.061126",\ + "1.016710, 1.285939, 1.573983, 2.073886, 3.074838",\ + "1.040236, 1.309465, 1.597508, 2.097411, 3.098364",\ + "1.308417, 1.577647, 1.865690, 2.365591, 3.366541",\ + "1.901878, 2.171108, 2.459150, 2.959049, 3.959995",\ + "1.063922, 1.337931, 1.624415, 2.124086, 3.124635",\ + "1.077635, 1.351643, 1.638128, 2.137799, 3.138347",\ + "1.101161, 1.375169, 1.661654, 2.161325, 3.161873",\ + "1.369342, 1.643351, 1.929835, 2.429504, 3.430050",\ + "1.962803, 2.236812, 2.523295, 3.022963, 4.023504",\ + "1.400271, 1.703161, 1.976608, 2.473565, 3.470091",\ + "1.413984, 1.716874, 1.990321, 2.487277, 3.483803",\ + "1.437509, 1.740399, 2.013846, 2.510803, 3.507329",\ + "1.705691, 2.008581, 2.282028, 2.778982, 3.775506",\ + "2.299152, 2.602042, 2.875488, 3.372441, 4.368960"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.126070, 0.126070, 0.126070, 0.126069, 0.126068",\ + "0.155268, 0.155268, 0.155268, 0.155268, 0.155267",\ + "0.201999, 0.201999, 0.201999, 0.201999, 0.201998",\ + "0.823664, 0.823664, 0.823664, 0.823664, 0.823664",\ + "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\ + "0.126070, 0.126070, 0.126070, 0.126069, 0.126068",\ + "0.155268, 0.155268, 0.155268, 0.155268, 0.155267",\ + "0.201999, 0.201999, 0.201999, 0.201999, 0.201998",\ + "0.823664, 0.823664, 0.823664, 0.823664, 0.823664",\ + "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\ + "0.126070, 0.126070, 0.126070, 0.126069, 0.126068",\ + "0.155268, 0.155268, 0.155268, 0.155268, 0.155267",\ + "0.201999, 0.201999, 0.201999, 0.201999, 0.201998",\ + "0.823664, 0.823664, 0.823664, 0.823664, 0.823664",\ + "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\ + "0.126070, 0.126070, 0.126070, 0.126069, 0.126068",\ + "0.155268, 0.155268, 0.155268, 0.155268, 0.155267",\ + "0.201999, 0.201999, 0.201999, 0.201999, 0.201998",\ + "0.823664, 0.823664, 0.823664, 0.823664, 0.823664",\ + "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\ + "0.126070, 0.126070, 0.126070, 0.126069, 0.126068",\ + "0.155268, 0.155268, 0.155268, 0.155268, 0.155267",\ + "0.201999, 0.201999, 0.201999, 0.201999, 0.201998",\ + "0.823664, 0.823664, 0.823664, 0.823664, 0.823664",\ + "2.222140, 2.222140, 2.222140, 2.222140, 2.222140"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.773106, 1.034029, 1.323047, 1.824254, 2.826667",\ + "0.785329, 1.046252, 1.335269, 1.836474, 2.838884",\ + "0.805232, 1.066155, 1.355171, 1.856374, 2.858778",\ + "0.977479, 1.238403, 1.527417, 2.028611, 3.031000",\ + "1.312050, 1.572973, 1.861987, 2.363182, 3.365571",\ + "0.860514, 1.121605, 1.410714, 1.910968, 2.912601",\ + "0.872737, 1.133828, 1.422936, 1.923188, 2.924818",\ + "0.892640, 1.153731, 1.442839, 1.943088, 2.944712",\ + "1.064888, 1.325979, 1.615084, 2.115325, 3.116933",\ + "1.399458, 1.660549, 1.949654, 2.449896, 3.451505",\ + "0.941405, 1.210634, 1.498679, 1.998589, 2.999556",\ + "0.953628, 1.222857, 1.510902, 2.010810, 3.011773",\ + "0.973531, 1.242760, 1.530804, 2.030710, 3.031667",\ + "1.145778, 1.415007, 1.703049, 2.202947, 3.203888",\ + "1.480349, 1.749578, 2.037620, 2.537518, 3.538460",\ + "1.002329, 1.276338, 1.562824, 2.062502, 3.063065",\ + "1.014552, 1.288561, 1.575047, 2.074723, 3.075282",\ + "1.034455, 1.308464, 1.594949, 2.094623, 3.095176",\ + "1.206703, 1.480712, 1.767194, 2.266860, 3.267397",\ + "1.541273, 1.815282, 2.101765, 2.601431, 3.601969",\ + "1.338678, 1.641568, 1.915017, 2.411981, 3.408521",\ + "1.350901, 1.653791, 1.927240, 2.424201, 3.420738",\ + "1.370804, 1.673694, 1.947142, 2.444101, 3.440632",\ + "1.543052, 1.845942, 2.119387, 2.616338, 3.612854",\ + "1.877622, 2.180512, 2.453958, 2.950909, 3.947425"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.077156, 0.077156, 0.077150, 0.077131, 0.077093",\ + "0.082414, 0.082414, 0.082409, 0.082392, 0.082357",\ + "0.102324, 0.102324, 0.102319, 0.102303, 0.102270",\ + "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\ + "1.026132, 1.026132, 1.026132, 1.026132, 1.026131",\ + "0.077156, 0.077156, 0.077150, 0.077131, 0.077093",\ + "0.082414, 0.082414, 0.082409, 0.082392, 0.082357",\ + "0.102324, 0.102324, 0.102319, 0.102303, 0.102270",\ + "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\ + "1.026132, 1.026132, 1.026132, 1.026132, 1.026131",\ + "0.077156, 0.077156, 0.077150, 0.077131, 0.077093",\ + "0.082414, 0.082414, 0.082409, 0.082392, 0.082357",\ + "0.102324, 0.102324, 0.102319, 0.102303, 0.102270",\ + "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\ + "1.026132, 1.026132, 1.026132, 1.026132, 1.026131",\ + "0.077156, 0.077156, 0.077150, 0.077131, 0.077093",\ + "0.082414, 0.082414, 0.082409, 0.082392, 0.082357",\ + "0.102324, 0.102324, 0.102319, 0.102303, 0.102270",\ + "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\ + "1.026132, 1.026132, 1.026132, 1.026132, 1.026131",\ + "0.077156, 0.077156, 0.077150, 0.077131, 0.077093",\ + "0.082414, 0.082414, 0.082409, 0.082392, 0.082357",\ + "0.102324, 0.102324, 0.102319, 0.102303, 0.102270",\ + "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\ + "1.026132, 1.026132, 1.026132, 1.026132, 1.026131"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_2590*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[39]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011"); + values ( "0.813664, 1.067787, 1.348972, 1.815159, 2.747532",\ + "0.827376, 1.081499, 1.362685, 1.828871, 2.761244",\ + "0.850902, 1.105025, 1.386211, 1.852397, 2.784770",\ + "1.119084, 1.373207, 1.654392, 2.120577, 3.052948",\ + "1.712545, 1.966668, 2.247853, 2.714036, 3.646404",\ + "0.901073, 1.155375, 1.436530, 1.901873, 2.833466",\ + "0.914786, 1.169088, 1.450242, 1.915586, 2.847178",\ + "0.938311, 1.192614, 1.473768, 1.939111, 2.870703",\ + "1.206493, 1.460795, 1.741949, 2.207292, 3.138882",\ + "1.799954, 2.054256, 2.335410, 2.800751, 3.732338",\ + "0.981887, 1.244438, 1.524493, 1.989495, 2.920421",\ + "0.995600, 1.258151, 1.538206, 2.003207, 2.934133",\ + "1.019126, 1.281676, 1.561732, 2.026733, 2.957659",\ + "1.287307, 1.549858, 1.829913, 2.294913, 3.225837",\ + "1.880768, 2.143319, 2.423373, 2.888372, 3.819293",\ + "1.039467, 1.310192, 1.588632, 2.053408, 2.983930",\ + "1.053180, 1.323904, 1.602345, 2.067121, 2.997642",\ + "1.076705, 1.347430, 1.625871, 2.090646, 3.021168",\ + "1.344887, 1.615612, 1.894052, 2.358827, 3.289346",\ + "1.938348, 2.209073, 2.487513, 2.952286, 3.882802",\ + "1.371275, 1.675984, 1.940471, 2.402742, 3.329386",\ + "1.384988, 1.689697, 1.954183, 2.416455, 3.343098",\ + "1.408514, 1.713222, 1.977709, 2.439981, 3.366623",\ + "1.676695, 1.981404, 2.245890, 2.708161, 3.634802",\ + "2.270156, 2.574865, 2.839351, 3.301620, 4.228258"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011"); + values ( "0.126070, 0.126070, 0.126070, 0.126069, 0.126068",\ + "0.155268, 0.155268, 0.155268, 0.155268, 0.155267",\ + "0.201999, 0.201999, 0.201999, 0.201999, 0.201999",\ + "0.823664, 0.823664, 0.823664, 0.823664, 0.823664",\ + "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\ + "0.126070, 0.126070, 0.126070, 0.126069, 0.126068",\ + "0.155268, 0.155268, 0.155268, 0.155268, 0.155267",\ + "0.201999, 0.201999, 0.201999, 0.201999, 0.201999",\ + "0.823664, 0.823664, 0.823664, 0.823664, 0.823664",\ + "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\ + "0.126070, 0.126070, 0.126070, 0.126069, 0.126068",\ + "0.155268, 0.155268, 0.155268, 0.155268, 0.155267",\ + "0.201999, 0.201999, 0.201999, 0.201999, 0.201999",\ + "0.823664, 0.823664, 0.823664, 0.823664, 0.823664",\ + "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\ + "0.126070, 0.126070, 0.126070, 0.126069, 0.126068",\ + "0.155268, 0.155268, 0.155268, 0.155268, 0.155267",\ + "0.201999, 0.201999, 0.201999, 0.201999, 0.201999",\ + "0.823664, 0.823664, 0.823664, 0.823664, 0.823664",\ + "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\ + "0.126070, 0.126070, 0.126070, 0.126069, 0.126068",\ + "0.155268, 0.155268, 0.155268, 0.155268, 0.155267",\ + "0.201999, 0.201999, 0.201999, 0.201999, 0.201999",\ + "0.823664, 0.823664, 0.823664, 0.823664, 0.823664",\ + "2.222140, 2.222140, 2.222140, 2.222140, 2.222140"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011"); + values ( "0.752071, 1.006194, 1.287381, 1.753572, 2.685955",\ + "0.764294, 1.018417, 1.299603, 1.765793, 2.698174",\ + "0.784197, 1.038320, 1.319506, 1.785694, 2.718071",\ + "0.956445, 1.210568, 1.491752, 1.957934, 2.890299",\ + "1.291015, 1.545138, 1.826322, 2.292505, 3.224871",\ + "0.839480, 1.093783, 1.374938, 1.840287, 2.771889",\ + "0.851703, 1.106005, 1.387161, 1.852508, 2.784107",\ + "0.871606, 1.125909, 1.407063, 1.872409, 2.804004",\ + "1.043854, 1.298156, 1.579309, 2.044649, 2.976233",\ + "1.378424, 1.632726, 1.913880, 2.379220, 3.310805",\ + "0.920294, 1.182845, 1.462902, 1.927908, 2.858844",\ + "0.932517, 1.195068, 1.475124, 1.940130, 2.871062",\ + "0.952420, 1.214971, 1.495027, 1.960030, 2.890960",\ + "1.124668, 1.387219, 1.667273, 2.132271, 3.063188",\ + "1.459238, 1.721789, 2.001843, 2.466841, 3.397760",\ + "0.977874, 1.248599, 1.527041, 1.991822, 2.922353",\ + "0.990097, 1.260822, 1.539264, 2.004043, 2.934571",\ + "1.010000, 1.280725, 1.559166, 2.023944, 2.954468",\ + "1.182248, 1.452972, 1.731412, 2.196184, 3.126697",\ + "1.516818, 1.787543, 2.065982, 2.530755, 3.461269",\ + "1.309683, 1.614391, 1.878880, 2.341156, 3.267809",\ + "1.321906, 1.626614, 1.891102, 2.353377, 3.280027",\ + "1.341809, 1.646517, 1.911005, 2.373278, 3.299924",\ + "1.514056, 1.818765, 2.083251, 2.545518, 3.472153",\ + "1.848626, 2.153335, 2.417821, 2.880089, 3.806725"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011"); + values ( "0.077156, 0.077156, 0.077152, 0.077138, 0.077112",\ + "0.082414, 0.082414, 0.082410, 0.082398, 0.082374",\ + "0.102323, 0.102323, 0.102320, 0.102309, 0.102286",\ + "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\ + "1.026132, 1.026132, 1.026132, 1.026132, 1.026131",\ + "0.077156, 0.077156, 0.077152, 0.077138, 0.077112",\ + "0.082414, 0.082414, 0.082410, 0.082398, 0.082374",\ + "0.102323, 0.102323, 0.102320, 0.102309, 0.102286",\ + "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\ + "1.026132, 1.026132, 1.026132, 1.026132, 1.026131",\ + "0.077156, 0.077156, 0.077152, 0.077138, 0.077112",\ + "0.082414, 0.082414, 0.082410, 0.082398, 0.082374",\ + "0.102323, 0.102323, 0.102320, 0.102309, 0.102286",\ + "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\ + "1.026132, 1.026132, 1.026132, 1.026132, 1.026131",\ + "0.077156, 0.077156, 0.077152, 0.077138, 0.077112",\ + "0.082414, 0.082414, 0.082410, 0.082398, 0.082374",\ + "0.102323, 0.102323, 0.102320, 0.102309, 0.102286",\ + "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\ + "1.026132, 1.026132, 1.026132, 1.026132, 1.026131",\ + "0.077156, 0.077156, 0.077151, 0.077138, 0.077112",\ + "0.082414, 0.082414, 0.082410, 0.082398, 0.082374",\ + "0.102323, 0.102323, 0.102320, 0.102309, 0.102286",\ + "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\ + "1.026132, 1.026132, 1.026132, 1.026132, 1.026131"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_2633*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[40]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.689280, 0.957537, 1.249948, 1.745707, 2.737226",\ + "0.703254, 0.971515, 1.263950, 1.759776, 2.751428",\ + "0.726748, 0.995009, 1.287441, 1.783259, 2.774894",\ + "0.996345, 1.264632, 1.557197, 2.053374, 3.045727",\ + "1.591995, 1.860324, 2.153094, 2.649826, 3.643289",\ + "0.776693, 1.045135, 1.337600, 1.832422, 2.823160",\ + "0.790666, 1.059113, 1.351603, 1.846491, 2.837361",\ + "0.814160, 1.082607, 1.375093, 1.869974, 2.860828",\ + "1.083757, 1.352230, 1.644851, 2.140089, 3.131661",\ + "1.679408, 1.947922, 2.240750, 2.736541, 3.729223",\ + "0.857617, 1.134236, 1.425566, 1.920044, 2.910115",\ + "0.871591, 1.148215, 1.439569, 1.934113, 2.924316",\ + "0.895085, 1.171708, 1.463060, 1.957596, 2.947783",\ + "1.164682, 1.441333, 1.732817, 2.227711, 3.218616",\ + "1.760333, 2.037025, 2.328716, 2.824163, 3.816178",\ + "0.918265, 1.200047, 1.489710, 1.983958, 2.973624",\ + "0.932239, 1.214026, 1.503713, 1.998027, 2.987825",\ + "0.955733, 1.237519, 1.527204, 2.021510, 3.011292",\ + "1.225332, 1.507144, 1.796961, 2.291625, 3.282125",\ + "1.820984, 2.102838, 2.392860, 2.888076, 3.879687",\ + "1.253788, 1.566464, 1.841850, 2.333418, 3.319080",\ + "1.267763, 1.580444, 1.855854, 2.347487, 3.333282",\ + "1.291257, 1.603937, 1.879344, 2.370970, 3.356748",\ + "1.560858, 1.873569, 2.149106, 2.641086, 3.627581",\ + "2.156515, 2.469274, 2.745010, 3.237540, 4.225142"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.130558, 0.130764, 0.132053, 0.135744, 0.143126",\ + "0.158251, 0.158388, 0.159397, 0.162380, 0.168346",\ + "0.203206, 0.203261, 0.203904, 0.205928, 0.209976",\ + "0.823780, 0.823782, 0.823793, 0.823822, 0.823881",\ + "2.222146, 2.222146, 2.222146, 2.222146, 2.222146",\ + "0.130558, 0.130766, 0.132065, 0.135744, 0.143126",\ + "0.158251, 0.158389, 0.159406, 0.162380, 0.168346",\ + "0.203206, 0.203262, 0.203910, 0.205928, 0.209976",\ + "0.823780, 0.823782, 0.823793, 0.823822, 0.823881",\ + "2.222146, 2.222146, 2.222146, 2.222146, 2.222146",\ + "0.130559, 0.130769, 0.132065, 0.135744, 0.143126",\ + "0.158251, 0.158391, 0.159406, 0.162380, 0.168346",\ + "0.203206, 0.203262, 0.203910, 0.205928, 0.209976",\ + "0.823780, 0.823782, 0.823793, 0.823822, 0.823881",\ + "2.222146, 2.222146, 2.222146, 2.222146, 2.222146",\ + "0.130568, 0.130774, 0.132066, 0.135744, 0.143126",\ + "0.158257, 0.158394, 0.159407, 0.162380, 0.168346",\ + "0.203208, 0.203264, 0.203911, 0.205928, 0.209976",\ + "0.823780, 0.823782, 0.823793, 0.823822, 0.823881",\ + "2.222146, 2.222146, 2.222146, 2.222146, 2.222146",\ + "0.130591, 0.130830, 0.132103, 0.135759, 0.143126",\ + "0.158273, 0.158432, 0.159437, 0.162392, 0.168346",\ + "0.203215, 0.203279, 0.203931, 0.205936, 0.209976",\ + "0.823780, 0.823783, 0.823793, 0.823822, 0.823881",\ + "2.222146, 2.222146, 2.222146, 2.222146, 2.222146"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.620877, 0.889007, 1.180779, 1.674812, 2.662879",\ + "0.634992, 0.903157, 1.195106, 1.689619, 2.678645",\ + "0.657454, 0.925667, 1.217856, 1.713018, 2.703341",\ + "0.837827, 1.106191, 1.399143, 1.896364, 2.890807",\ + "1.171871, 1.440226, 1.733128, 2.230216, 3.224392",\ + "0.708289, 0.976604, 1.268425, 1.761527, 2.748812",\ + "0.722404, 0.990754, 1.282755, 1.776334, 2.764579",\ + "0.744867, 1.013264, 1.305507, 1.799733, 2.789275",\ + "0.925240, 1.193790, 1.486800, 1.983079, 2.976740",\ + "1.259284, 1.527824, 1.820785, 2.316931, 3.310326",\ + "0.789214, 1.065703, 1.356391, 1.849149, 2.835768",\ + "0.803329, 1.079854, 1.370721, 1.863956, 2.851534",\ + "0.825791, 1.102365, 1.393473, 1.887355, 2.876230",\ + "1.006165, 1.282894, 1.574766, 2.070702, 3.063695",\ + "1.340209, 1.616928, 1.908751, 2.404553, 3.397281",\ + "0.849857, 1.131511, 1.420535, 1.913063, 2.899276",\ + "0.863973, 1.145663, 1.434865, 1.927870, 2.915043",\ + "0.886438, 1.168175, 1.457617, 1.951269, 2.939739",\ + "1.066817, 1.348707, 1.638911, 2.134615, 3.127204",\ + "1.400861, 1.682741, 1.972895, 2.468467, 3.460790",\ + "1.185366, 1.497892, 1.772658, 2.262515, 3.244732",\ + "1.199486, 1.512054, 1.786992, 2.277325, 3.260499",\ + "1.221956, 1.534580, 1.809751, 2.300726, 3.285195",\ + "1.402352, 1.715153, 1.991066, 2.484081, 3.472661",\ + "1.736395, 2.049184, 2.325049, 2.817932, 3.806246"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.096307, 0.096664, 0.098460, 0.103314, 0.113023",\ + "0.099768, 0.100091, 0.101719, 0.106118, 0.114915",\ + "0.118566, 0.118869, 0.120392, 0.124509, 0.132743",\ + "0.380772, 0.380786, 0.381010, 0.381719, 0.383137",\ + "1.026329, 1.026338, 1.026379, 1.026486, 1.026699",\ + "0.096307, 0.096666, 0.098476, 0.103314, 0.113023",\ + "0.099768, 0.100093, 0.101733, 0.106118, 0.114915",\ + "0.118566, 0.118871, 0.120405, 0.124509, 0.132743",\ + "0.380772, 0.380786, 0.381012, 0.381719, 0.383137",\ + "1.026329, 1.026338, 1.026379, 1.026486, 1.026699",\ + "0.096307, 0.096672, 0.098476, 0.103314, 0.113023",\ + "0.099768, 0.100099, 0.101733, 0.106118, 0.114915",\ + "0.118566, 0.118876, 0.120406, 0.124509, 0.132743",\ + "0.380772, 0.380786, 0.381012, 0.381719, 0.383137",\ + "1.026329, 1.026339, 1.026379, 1.026486, 1.026699",\ + "0.096322, 0.096680, 0.098477, 0.103314, 0.113023",\ + "0.099782, 0.100106, 0.101734, 0.106118, 0.114915",\ + "0.118579, 0.118883, 0.120406, 0.124509, 0.132743",\ + "0.380772, 0.380787, 0.381012, 0.381719, 0.383137",\ + "1.026330, 1.026339, 1.026379, 1.026486, 1.026699",\ + "0.096361, 0.096780, 0.098526, 0.103335, 0.113023",\ + "0.099817, 0.100196, 0.101779, 0.106136, 0.114915",\ + "0.118612, 0.118967, 0.120448, 0.124526, 0.132743",\ + "0.380772, 0.380792, 0.381019, 0.381722, 0.383137",\ + "1.026331, 1.026341, 1.026381, 1.026486, 1.026699"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_2683*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[42]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.195231, 0.463005, 0.734474, 1.195010, 2.116083",\ + "0.209369, 0.477311, 0.748785, 1.209873, 2.132048",\ + "0.233103, 0.501280, 0.772498, 1.233725, 2.156177",\ + "0.505445, 0.772942, 1.041862, 1.499718, 2.415430",\ + "1.101330, 1.368410, 1.636340, 2.092443, 3.004649",\ + "0.282639, 0.550544, 0.822013, 1.281725, 2.202017",\ + "0.296777, 0.564849, 0.836326, 1.296587, 2.217982",\ + "0.320749, 0.588817, 0.860040, 1.320439, 2.242111",\ + "0.593808, 0.860470, 1.129393, 1.586432, 2.501364",\ + "1.189691, 1.455935, 1.723865, 2.179157, 3.090583",\ + "0.371453, 0.639490, 0.909976, 1.369346, 2.288972",\ + "0.385884, 0.653793, 0.924289, 1.384209, 2.304937",\ + "0.410095, 0.677755, 0.948003, 1.408060, 2.329066",\ + "0.683117, 0.949390, 1.217355, 1.674054, 2.588319",\ + "1.278993, 1.544848, 1.811828, 2.266779, 3.177538",\ + "0.435127, 0.705073, 0.974115, 1.433259, 2.352481",\ + "0.449557, 0.719372, 0.988428, 1.448122, 2.368446",\ + "0.473764, 0.743329, 1.012141, 1.471974, 2.392575",\ + "0.746751, 1.014935, 1.281493, 1.737967, 2.651828",\ + "1.342621, 1.610383, 1.875965, 2.330692, 3.241047",\ + "0.771711, 1.068883, 1.325895, 1.782569, 2.697937",\ + "0.786132, 1.083144, 1.340213, 1.797434, 2.713902",\ + "0.810321, 1.107028, 1.363928, 1.821286, 2.738031",\ + "1.083085, 1.378307, 1.633246, 2.087266, 2.997284",\ + "1.678917, 1.973635, 2.227701, 2.679984, 3.586503"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.185659, 0.236480, 0.332306, 0.503768, 0.846690",\ + "0.203762, 0.251201, 0.346416, 0.519962, 0.867054",\ + "0.237818, 0.275998, 0.366817, 0.542132, 0.892761",\ + "0.823305, 0.824108, 0.854501, 0.958291, 1.165871",\ + "2.222180, 2.222247, 2.228687, 2.250859, 2.295203",\ + "0.185659, 0.236778, 0.332846, 0.503768, 0.846690",\ + "0.203762, 0.251491, 0.346963, 0.519962, 0.867054",\ + "0.238090, 0.276257, 0.367369, 0.542132, 0.892761",\ + "0.823322, 0.824110, 0.854828, 0.958291, 1.165871",\ + "2.222181, 2.222247, 2.228756, 2.250859, 2.295203",\ + "0.187582, 0.237448, 0.332856, 0.503768, 0.846690",\ + "0.205428, 0.252143, 0.346973, 0.519962, 0.867054",\ + "0.238891, 0.276838, 0.367379, 0.542132, 0.892761",\ + "0.823369, 0.824113, 0.854835, 0.958291, 1.165871",\ + "2.222186, 2.222247, 2.228758, 2.250859, 2.295203",\ + "0.188921, 0.238422, 0.332885, 0.503768, 0.846690",\ + "0.206588, 0.253091, 0.347002, 0.519962, 0.867054",\ + "0.239638, 0.277682, 0.367409, 0.542132, 0.892761",\ + "0.823414, 0.824119, 0.854852, 0.958291, 1.165871",\ + "2.222191, 2.222247, 2.228761, 2.250859, 2.295203",\ + "0.197449, 0.249827, 0.334624, 0.504477, 0.846690",\ + "0.213977, 0.264195, 0.348763, 0.520680, 0.867054",\ + "0.244398, 0.287568, 0.369187, 0.542857, 0.892761",\ + "0.823697, 0.824180, 0.855905, 0.958721, 1.165871",\ + "2.222221, 2.222247, 2.228986, 2.250950, 2.295203"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.199835, 0.394068, 0.663502, 1.119151, 2.030450",\ + "0.208748, 0.404375, 0.677456, 1.139816, 2.064535",\ + "0.223610, 0.421071, 0.699454, 1.171923, 2.116862",\ + "0.380613, 0.582386, 0.880612, 1.405667, 2.455778",\ + "0.716679, 0.922290, 1.228480, 1.784735, 2.897244",\ + "0.287243, 0.481603, 0.751025, 1.205865, 2.116384",\ + "0.296156, 0.491921, 0.765001, 1.226530, 2.150469",\ + "0.311018, 0.508632, 0.787030, 1.258637, 2.202796",\ + "0.468021, 0.669977, 0.968355, 1.492382, 2.541712",\ + "0.804087, 1.009874, 1.316321, 1.871449, 2.983178",\ + "0.368115, 0.570540, 0.838988, 1.293487, 2.203339",\ + "0.377029, 0.580882, 0.852964, 1.314152, 2.237424",\ + "0.391890, 0.597628, 0.874994, 1.346259, 2.289751",\ + "0.548893, 0.759039, 1.056321, 1.580003, 2.628667",\ + "0.884959, 1.098920, 1.404289, 1.959070, 3.070133",\ + "0.425818, 0.636109, 0.903125, 1.357400, 2.266848",\ + "0.434733, 0.646488, 0.917102, 1.378065, 2.300933",\ + "0.449593, 0.663284, 0.939134, 1.410172, 2.353260",\ + "0.606596, 0.824792, 1.120470, 1.643916, 2.692176",\ + "0.942662, 1.164649, 1.468444, 2.022984, 3.133642",\ + "0.728861, 0.999767, 1.254856, 1.706689, 2.612304",\ + "0.737784, 1.010567, 1.268901, 1.727382, 2.646389",\ + "0.752638, 1.027949, 1.291036, 1.759531, 2.698716",\ + "0.909639, 1.190589, 1.472905, 1.993493, 3.037632",\ + "1.245701, 1.530174, 1.821195, 2.372689, 3.479098"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.051713, 0.082206, 0.146667, 0.272496, 0.524154",\ + "0.059242, 0.084148, 0.146833, 0.273232, 0.526032",\ + "0.082676, 0.098099, 0.151707, 0.276480, 0.526025",\ + "0.382075, 0.382564, 0.407345, 0.490228, 0.655996",\ + "1.027888, 1.027888, 1.042321, 1.092011, 1.191392",\ + "0.051713, 0.082387, 0.147063, 0.272496, 0.524154",\ + "0.059242, 0.084316, 0.147231, 0.273232, 0.526032",\ + "0.082676, 0.098212, 0.152100, 0.276480, 0.526025",\ + "0.382075, 0.382568, 0.407606, 0.490228, 0.655996",\ + "1.027888, 1.027888, 1.042477, 1.092011, 1.191392",\ + "0.051782, 0.082793, 0.147071, 0.272496, 0.524154",\ + "0.059284, 0.084694, 0.147238, 0.273232, 0.526032",\ + "0.082697, 0.098465, 0.152108, 0.276480, 0.526025",\ + "0.382075, 0.382579, 0.407611, 0.490228, 0.655996",\ + "1.027888, 1.027888, 1.042480, 1.092011, 1.191392",\ + "0.051916, 0.083384, 0.147092, 0.272496, 0.524154",\ + "0.059368, 0.085243, 0.147259, 0.273232, 0.526032",\ + "0.082738, 0.098832, 0.152128, 0.276480, 0.526025",\ + "0.382075, 0.382594, 0.407625, 0.490228, 0.655996",\ + "1.027888, 1.027888, 1.042489, 1.092011, 1.191392",\ + "0.053133, 0.090301, 0.148368, 0.273016, 0.524154",\ + "0.060124, 0.091679, 0.148542, 0.273755, 0.526032",\ + "0.083110, 0.103136, 0.153394, 0.276996, 0.526025",\ + "0.382075, 0.382769, 0.408465, 0.490571, 0.655996",\ + "1.027888, 1.027888, 1.042993, 1.092217, 1.191392"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_2504*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[43]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011"); + values ( "0.107724, 0.368276, 0.625542, 1.061117, 1.932266",\ + "0.118290, 0.379979, 0.639987, 1.079831, 1.959519",\ + "0.141262, 0.402747, 0.664893, 1.109231, 1.997905",\ + "0.466405, 0.694370, 0.967258, 1.421195, 2.329069",\ + "1.080370, 1.299790, 1.592495, 2.085614, 3.071851",\ + "0.196001, 0.455768, 0.713003, 1.147831, 2.018200",\ + "0.206570, 0.467481, 0.727462, 1.166545, 2.045453",\ + "0.229522, 0.490254, 0.752382, 1.195945, 2.083839",\ + "0.553814, 0.781928, 1.054777, 1.507910, 2.415003",\ + "1.167779, 1.387403, 1.680137, 2.172328, 3.157785",\ + "0.284966, 0.544612, 0.800965, 1.235453, 2.105155",\ + "0.295543, 0.556347, 0.815424, 1.254167, 2.132408",\ + "0.318436, 0.579132, 0.840344, 1.283567, 2.170794",\ + "0.634637, 0.870922, 1.142740, 1.595531, 2.501958",\ + "1.248620, 1.476519, 1.768103, 2.259950, 3.244740",\ + "0.348239, 0.610047, 0.865099, 1.299366, 2.168664",\ + "0.358823, 0.621814, 0.879558, 1.318080, 2.195917",\ + "0.381662, 0.644617, 0.904480, 1.347480, 2.234303",\ + "0.692234, 0.936575, 1.206877, 1.659445, 2.565467",\ + "1.306252, 1.542352, 1.832246, 2.323863, 3.308249",\ + "0.682278, 0.972118, 1.216627, 1.648574, 2.514120",\ + "0.692910, 0.984256, 1.231130, 1.667306, 2.541373",\ + "0.715403, 1.007266, 1.256096, 1.696724, 2.579759",\ + "1.001252, 1.301193, 1.558591, 2.008728, 2.910923",\ + "1.608596, 1.909065, 2.184358, 2.673309, 3.653705"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011"); + values ( "0.074735, 0.092677, 0.146088, 0.239899, 0.427522",\ + "0.102638, 0.120071, 0.176792, 0.284601, 0.500219",\ + "0.161882, 0.174744, 0.229174, 0.352169, 0.598157",\ + "0.823637, 0.823637, 0.866367, 1.013938, 1.309078",\ + "2.221941, 2.221941, 2.244685, 2.323231, 2.480325",\ + "0.074735, 0.092846, 0.146384, 0.239899, 0.427522",\ + "0.102638, 0.120235, 0.177132, 0.284601, 0.500219",\ + "0.161882, 0.174865, 0.229562, 0.352169, 0.598157",\ + "0.823637, 0.823637, 0.866833, 1.013938, 1.309078",\ + "2.221941, 2.221941, 2.244933, 2.323231, 2.480325",\ + "0.074735, 0.093227, 0.146389, 0.239899, 0.427522",\ + "0.102638, 0.120606, 0.177138, 0.284601, 0.500219",\ + "0.161882, 0.175138, 0.229569, 0.352169, 0.598157",\ + "0.823637, 0.823637, 0.866841, 1.013938, 1.309078",\ + "2.221941, 2.221941, 2.244937, 2.323231, 2.480325",\ + "0.074735, 0.093782, 0.146405, 0.239899, 0.427522",\ + "0.102638, 0.121144, 0.177156, 0.284601, 0.500219",\ + "0.161882, 0.175536, 0.229590, 0.352169, 0.598157",\ + "0.823637, 0.823637, 0.866866, 1.013938, 1.309078",\ + "2.221941, 2.221941, 2.244950, 2.323231, 2.480325",\ + "0.074735, 0.100272, 0.147356, 0.240288, 0.427522",\ + "0.102638, 0.127451, 0.178250, 0.285047, 0.500219",\ + "0.161882, 0.180189, 0.230838, 0.352678, 0.598157",\ + "0.823637, 0.823637, 0.868363, 1.014548, 1.309078",\ + "2.221941, 2.221941, 2.245747, 2.323557, 2.480325"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011"); + values ( "0.140111, 0.321611, 0.507696, 0.851050, 1.569056",\ + "0.146136, 0.328572, 0.525511, 0.902870, 1.657587",\ + "0.156561, 0.339884, 0.570480, 0.970939, 1.771856",\ + "0.297184, 0.522021, 0.807737, 1.302651, 2.292479",\ + "0.634484, 0.861679, 1.151767, 1.684827, 2.750947",\ + "0.227520, 0.408999, 0.595163, 0.937764, 1.654990",\ + "0.233545, 0.415960, 0.612788, 0.989584, 1.743521",\ + "0.243970, 0.427273, 0.657830, 1.057653, 1.857790",\ + "0.384593, 0.609585, 0.895385, 1.389365, 2.378412",\ + "0.721893, 0.949200, 1.239535, 1.771541, 2.836881",\ + "0.308387, 0.489332, 0.675190, 1.025386, 1.741945",\ + "0.314418, 0.496293, 0.700747, 1.077206, 1.830476",\ + "0.324849, 0.509849, 0.745789, 1.145275, 1.944745",\ + "0.465472, 0.698592, 0.983351, 1.476987, 2.465368",\ + "0.802748, 1.038111, 1.327502, 1.859163, 2.923836",\ + "0.366068, 0.546880, 0.732732, 1.089299, 1.805454",\ + "0.372111, 0.553842, 0.764871, 1.141119, 1.893985",\ + "0.382553, 0.575066, 0.809918, 1.209188, 2.008254",\ + "0.523176, 0.764266, 1.047495, 1.540900, 2.528877",\ + "0.860406, 1.103644, 1.391653, 1.923076, 2.987345",\ + "0.668860, 0.879530, 1.082095, 1.438189, 2.150910",\ + "0.675009, 0.902838, 1.115808, 1.490086, 2.239441",\ + "0.685552, 0.934577, 1.161089, 1.558250, 2.353710",\ + "0.829810, 1.129123, 1.399624, 1.890354, 2.874332",\ + "1.174406, 1.466850, 1.744170, 2.272687, 3.332801"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011"); + values ( "0.063168, 0.063168, 0.086358, 0.196253, 0.354186",\ + "0.068741, 0.068741, 0.139035, 0.228534, 0.407534",\ + "0.084603, 0.084603, 0.170977, 0.272661, 0.476028",\ + "0.381099, 0.384014, 0.432690, 0.586065, 0.892815",\ + "1.028844, 1.028844, 1.069535, 1.210064, 1.491123",\ + "0.063168, 0.063168, 0.086418, 0.196253, 0.354186",\ + "0.068741, 0.068741, 0.139317, 0.228534, 0.407534",\ + "0.084603, 0.084603, 0.171298, 0.272661, 0.476028",\ + "0.381099, 0.384041, 0.433173, 0.586065, 0.892815",\ + "1.028844, 1.028844, 1.069978, 1.210064, 1.491123",\ + "0.063168, 0.063168, 0.086418, 0.196253, 0.354186",\ + "0.068741, 0.068741, 0.139322, 0.228534, 0.407534",\ + "0.084603, 0.108427, 0.171304, 0.272661, 0.476028",\ + "0.381099, 0.384103, 0.433182, 0.586065, 0.892815",\ + "1.028844, 1.028844, 1.069987, 1.210064, 1.491123",\ + "0.063168, 0.063168, 0.086418, 0.196253, 0.354186",\ + "0.068741, 0.068741, 0.139337, 0.228534, 0.407534",\ + "0.084603, 0.109141, 0.171320, 0.272661, 0.476028",\ + "0.381099, 0.384193, 0.433208, 0.586065, 0.892815",\ + "1.028844, 1.028844, 1.070010, 1.210064, 1.491123",\ + "0.063168, 0.081229, 0.118354, 0.196580, 0.354186",\ + "0.068741, 0.094387, 0.140245, 0.228905, 0.407534",\ + "0.084603, 0.117503, 0.172352, 0.273082, 0.476028",\ + "0.381099, 0.385248, 0.434764, 0.586700, 0.892815",\ + "1.028844, 1.028844, 1.071436, 1.210646, 1.491123"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_2464*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[45]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011"); + values ( "0.666340, 0.928130, 1.212847, 1.689620, 2.643166",\ + "0.680315, 0.942109, 1.226845, 1.703665, 2.657306",\ + "0.703809, 0.965603, 1.250336, 1.727151, 2.680780",\ + "0.973410, 1.235228, 1.520067, 1.997139, 2.951283",\ + "1.569066, 1.830922, 2.115924, 2.593394, 3.548335",\ + "0.753746, 1.015729, 1.300436, 1.776334, 2.729100",\ + "0.767721, 1.029708, 1.314434, 1.790379, 2.743240",\ + "0.791215, 1.053202, 1.337926, 1.813865, 2.766714",\ + "1.060816, 1.322827, 1.607657, 2.083853, 3.037217",\ + "1.656472, 1.918522, 2.203516, 2.680108, 3.634269",\ + "0.834559, 1.104799, 1.388400, 1.863955, 2.816055",\ + "0.848533, 1.118778, 1.402398, 1.878000, 2.830195",\ + "0.872027, 1.142272, 1.425889, 1.901486, 2.853669",\ + "1.141628, 1.411898, 1.695621, 2.171474, 3.124172",\ + "1.737284, 2.007593, 2.291479, 2.767729, 3.721224",\ + "0.896255, 1.170562, 1.452541, 1.927868, 2.879564",\ + "0.910230, 1.184541, 1.466539, 1.941913, 2.893704",\ + "0.933724, 1.208035, 1.490030, 1.965399, 2.917178",\ + "1.203325, 1.477661, 1.759762, 2.235387, 3.187681",\ + "1.798983, 2.073358, 2.355620, 2.831642, 3.784733",\ + "1.233218, 1.536514, 1.804484, 2.277243, 3.225020",\ + "1.247192, 1.550495, 1.818483, 2.291289, 3.239160",\ + "1.270686, 1.573988, 1.841974, 2.314774, 3.262634",\ + "1.540289, 1.843622, 2.111709, 2.584763, 3.533137",\ + "2.135948, 2.439330, 2.707571, 3.181020, 4.130188"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011"); + values ( "0.130524, 0.130598, 0.131270, 0.133249, 0.137207",\ + "0.158228, 0.158278, 0.158724, 0.160039, 0.162669",\ + "0.203197, 0.203217, 0.203397, 0.203929, 0.204993",\ + "0.823780, 0.823782, 0.823791, 0.823812, 0.823854",\ + "2.222145, 2.222146, 2.222146, 2.222149, 2.222153",\ + "0.130524, 0.130599, 0.131276, 0.133249, 0.137207",\ + "0.158228, 0.158278, 0.158728, 0.160039, 0.162669",\ + "0.203197, 0.203217, 0.203399, 0.203929, 0.204993",\ + "0.823780, 0.823782, 0.823791, 0.823812, 0.823854",\ + "2.222145, 2.222146, 2.222146, 2.222149, 2.222153",\ + "0.130525, 0.130600, 0.131276, 0.133249, 0.137207",\ + "0.158229, 0.158279, 0.158728, 0.160039, 0.162669",\ + "0.203197, 0.203217, 0.203399, 0.203929, 0.204993",\ + "0.823780, 0.823782, 0.823791, 0.823812, 0.823854",\ + "2.222145, 2.222146, 2.222146, 2.222149, 2.222153",\ + "0.130526, 0.130602, 0.131276, 0.133249, 0.137207",\ + "0.158229, 0.158280, 0.158728, 0.160039, 0.162669",\ + "0.203197, 0.203218, 0.203399, 0.203929, 0.204993",\ + "0.823780, 0.823782, 0.823791, 0.823812, 0.823854",\ + "2.222145, 2.222146, 2.222146, 2.222149, 2.222153",\ + "0.130530, 0.130626, 0.131296, 0.133257, 0.137207",\ + "0.158232, 0.158296, 0.158741, 0.160044, 0.162669",\ + "0.203198, 0.203224, 0.203404, 0.203931, 0.204993",\ + "0.823780, 0.823783, 0.823791, 0.823812, 0.823854",\ + "2.222146, 2.222146, 2.222146, 2.222149, 2.222153"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011"); + values ( "0.597919, 0.859592, 1.143801, 1.619336, 2.570405",\ + "0.612039, 0.873744, 1.158095, 1.633973, 2.585731",\ + "0.634508, 0.896258, 1.180798, 1.657142, 2.609831",\ + "0.814903, 1.076792, 1.361938, 1.839759, 2.795403",\ + "1.148946, 1.410826, 1.695932, 2.173658, 3.129110",\ + "0.685326, 0.947190, 1.231387, 1.706050, 2.656339",\ + "0.699445, 0.961343, 1.245681, 1.720687, 2.671665",\ + "0.721914, 0.983856, 1.268386, 1.743856, 2.695765",\ + "0.902309, 1.164392, 1.449531, 1.926473, 2.881336",\ + "1.236352, 1.498426, 1.783525, 2.260372, 3.215044",\ + "0.766138, 1.036258, 1.319350, 1.793671, 2.743294",\ + "0.780258, 1.050411, 1.333645, 1.808309, 2.758620",\ + "0.802727, 1.072925, 1.356350, 1.831478, 2.782720",\ + "0.983121, 1.253464, 1.537494, 2.014095, 2.968292",\ + "1.317164, 1.587497, 1.871488, 2.347994, 3.301999",\ + "0.827832, 1.102018, 1.383491, 1.857584, 2.806803",\ + "0.841953, 1.116172, 1.397786, 1.872221, 2.822129",\ + "0.864423, 1.138688, 1.420491, 1.895391, 2.846229",\ + "1.044820, 1.319229, 1.601635, 2.078008, 3.031801",\ + "1.378863, 1.653263, 1.935629, 2.411906, 3.365508",\ + "1.164787, 1.467934, 1.735422, 2.206954, 3.152259",\ + "1.178910, 1.482098, 1.749720, 2.221593, 3.167585",\ + "1.201382, 1.504627, 1.772430, 2.244764, 3.191684",\ + "1.381788, 1.685212, 1.953590, 2.427387, 3.377256",\ + "1.715830, 2.019242, 2.287583, 2.761285, 3.710964"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011"); + values ( "0.096357, 0.096687, 0.098113, 0.101595, 0.108560",\ + "0.099813, 0.100112, 0.101404, 0.104560, 0.110871",\ + "0.118608, 0.118888, 0.120098, 0.123051, 0.128958",\ + "0.380772, 0.380788, 0.380959, 0.381468, 0.382485",\ + "1.026328, 1.026331, 1.026361, 1.026448, 1.026622",\ + "0.096357, 0.096690, 0.098124, 0.101595, 0.108560",\ + "0.099813, 0.100115, 0.101414, 0.104560, 0.110871",\ + "0.118608, 0.118891, 0.120107, 0.123051, 0.128958",\ + "0.380772, 0.380788, 0.380960, 0.381468, 0.382485",\ + "1.026328, 1.026331, 1.026361, 1.026448, 1.026622",\ + "0.096357, 0.096696, 0.098124, 0.101595, 0.108560",\ + "0.099813, 0.100120, 0.101415, 0.104560, 0.110871",\ + "0.118609, 0.118896, 0.120107, 0.123051, 0.128958",\ + "0.380772, 0.380788, 0.380960, 0.381468, 0.382485",\ + "1.026328, 1.026331, 1.026361, 1.026448, 1.026622",\ + "0.096364, 0.096704, 0.098125, 0.101595, 0.108560",\ + "0.099820, 0.100128, 0.101415, 0.104560, 0.110871",\ + "0.118615, 0.118903, 0.120108, 0.123051, 0.128958",\ + "0.380772, 0.380789, 0.380961, 0.381468, 0.382485",\ + "1.026328, 1.026331, 1.026361, 1.026448, 1.026622",\ + "0.096383, 0.096806, 0.098160, 0.101610, 0.108560",\ + "0.099837, 0.100220, 0.101447, 0.104573, 0.110871",\ + "0.118631, 0.118989, 0.120138, 0.123064, 0.128958",\ + "0.380772, 0.380794, 0.380966, 0.381470, 0.382485",\ + "1.026328, 1.026332, 1.026362, 1.026448, 1.026622"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_2715*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[18]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.476785, 0.693340, 0.873015, 1.163119, 1.725535",\ + "0.496002, 0.712556, 0.892232, 1.182336, 1.744752",\ + "0.527650, 0.744204, 0.923880, 1.213984, 1.776400",\ + "0.818239, 1.034793, 1.214469, 1.504573, 2.066989",\ + "1.412242, 1.628797, 1.808472, 2.098576, 2.660992",\ + "0.565076, 0.780658, 0.960296, 1.250424, 1.812889",\ + "0.584292, 0.799874, 0.979512, 1.269641, 1.832105",\ + "0.615941, 0.831523, 1.011161, 1.301289, 1.863753",\ + "0.906530, 1.122112, 1.301750, 1.591878, 2.154342",\ + "1.500533, 1.716115, 1.895753, 2.185881, 2.748345",\ + "0.654117, 0.860991, 1.040323, 1.330453, 1.892920",\ + "0.673334, 0.880207, 1.059539, 1.349669, 1.912137",\ + "0.704982, 0.911855, 1.091188, 1.381318, 1.943785",\ + "0.995571, 1.202444, 1.381777, 1.671907, 2.234374",\ + "1.589574, 1.796447, 1.975780, 2.265910, 2.828377",\ + "0.717479, 0.918821, 1.098020, 1.387885, 1.949940",\ + "0.736695, 0.938038, 1.117237, 1.407101, 1.969157",\ + "0.768343, 0.969686, 1.148885, 1.438750, 2.000805",\ + "1.058932, 1.260275, 1.439474, 1.729339, 2.291394",\ + "1.652935, 1.854278, 2.033477, 2.323342, 2.885397",\ + "1.042371, 1.224140, 1.401676, 1.691058, 2.252168",\ + "1.061587, 1.243356, 1.420893, 1.710275, 2.271384",\ + "1.093235, 1.275004, 1.452541, 1.741923, 2.303032",\ + "1.383824, 1.565593, 1.743130, 2.032512, 2.593621",\ + "1.977827, 2.159596, 2.337133, 2.626515, 3.187624"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.115267, 0.115267, 0.115267, 0.115267, 0.115267",\ + "0.141939, 0.141939, 0.141939, 0.141939, 0.141939",\ + "0.190556, 0.190556, 0.190556, 0.190556, 0.190556",\ + "0.817533, 0.817533, 0.817533, 0.817533, 0.817533",\ + "2.193353, 2.193353, 2.193353, 2.193353, 2.193353",\ + "0.115267, 0.115267, 0.115267, 0.115267, 0.115267",\ + "0.141939, 0.141939, 0.141939, 0.141939, 0.141939",\ + "0.190556, 0.190556, 0.190556, 0.190556, 0.190556",\ + "0.817533, 0.817533, 0.817533, 0.817533, 0.817533",\ + "2.193353, 2.193353, 2.193353, 2.193353, 2.193353",\ + "0.115267, 0.115267, 0.115267, 0.115267, 0.115267",\ + "0.141939, 0.141939, 0.141939, 0.141939, 0.141939",\ + "0.190556, 0.190556, 0.190556, 0.190556, 0.190556",\ + "0.817533, 0.817533, 0.817533, 0.817533, 0.817533",\ + "2.193353, 2.193353, 2.193353, 2.193353, 2.193353",\ + "0.115267, 0.115267, 0.115267, 0.115267, 0.115267",\ + "0.141939, 0.141939, 0.141939, 0.141939, 0.141939",\ + "0.190556, 0.190556, 0.190556, 0.190556, 0.190556",\ + "0.817533, 0.817533, 0.817533, 0.817533, 0.817533",\ + "2.193353, 2.193353, 2.193353, 2.193353, 2.193353",\ + "0.115267, 0.115267, 0.115267, 0.115267, 0.115267",\ + "0.141939, 0.141939, 0.141939, 0.141939, 0.141939",\ + "0.190556, 0.190556, 0.190556, 0.190556, 0.190556",\ + "0.817533, 0.817533, 0.817533, 0.817533, 0.817533",\ + "2.193353, 2.193353, 2.193353, 2.193353, 2.193353"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.489199, 0.705753, 0.885429, 1.175533, 1.737949",\ + "0.497006, 0.713560, 0.893235, 1.183340, 1.745756",\ + "0.510387, 0.726941, 0.906617, 1.196721, 1.759137",\ + "0.662333, 0.878887, 1.058563, 1.348667, 1.911083",\ + "0.995767, 1.212322, 1.391997, 1.682102, 2.244518",\ + "0.577490, 0.793071, 0.972710, 1.262838, 1.825302",\ + "0.585296, 0.800878, 0.980516, 1.270645, 1.833109",\ + "0.598678, 0.814260, 0.993898, 1.284026, 1.846490",\ + "0.750624, 0.966205, 1.145844, 1.435972, 1.998436",\ + "1.084058, 1.299640, 1.479278, 1.769407, 2.331871",\ + "0.666531, 0.873404, 1.052737, 1.342866, 1.905334",\ + "0.674337, 0.881211, 1.060543, 1.350673, 1.913141",\ + "0.687719, 0.894592, 1.073925, 1.364055, 1.926522",\ + "0.839665, 1.046538, 1.225871, 1.516001, 2.078468",\ + "1.173099, 1.379973, 1.559305, 1.849435, 2.411902",\ + "0.729892, 0.931235, 1.110434, 1.400298, 1.962354",\ + "0.737699, 0.939041, 1.118240, 1.408105, 1.970161",\ + "0.751080, 0.952423, 1.131622, 1.421487, 1.983542",\ + "0.903026, 1.104369, 1.283568, 1.573432, 2.135488",\ + "1.236461, 1.437803, 1.617002, 1.906867, 2.468923",\ + "1.054784, 1.236553, 1.414090, 1.703472, 2.264581",\ + "1.062591, 1.244360, 1.421896, 1.711279, 2.272388",\ + "1.075972, 1.257741, 1.435278, 1.724660, 2.285769",\ + "1.227918, 1.409687, 1.587224, 1.876606, 2.437715",\ + "1.561353, 1.743122, 1.920659, 2.210041, 2.771150"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.049723, 0.049723, 0.049723, 0.049723, 0.049723",\ + "0.055443, 0.055443, 0.055443, 0.055443, 0.055443",\ + "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\ + "0.368589, 0.368589, 0.368589, 0.368589, 0.368589",\ + "1.002262, 1.002262, 1.002262, 1.002262, 1.002262",\ + "0.049723, 0.049723, 0.049723, 0.049723, 0.049723",\ + "0.055443, 0.055443, 0.055443, 0.055443, 0.055443",\ + "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\ + "0.368589, 0.368589, 0.368589, 0.368589, 0.368589",\ + "1.002262, 1.002262, 1.002262, 1.002262, 1.002262",\ + "0.049723, 0.049723, 0.049723, 0.049723, 0.049723",\ + "0.055443, 0.055443, 0.055443, 0.055443, 0.055443",\ + "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\ + "0.368589, 0.368589, 0.368589, 0.368589, 0.368589",\ + "1.002262, 1.002262, 1.002262, 1.002262, 1.002262",\ + "0.049723, 0.049723, 0.049723, 0.049723, 0.049723",\ + "0.055443, 0.055443, 0.055443, 0.055443, 0.055443",\ + "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\ + "0.368589, 0.368589, 0.368589, 0.368589, 0.368589",\ + "1.002262, 1.002262, 1.002262, 1.002262, 1.002262",\ + "0.049723, 0.049723, 0.049723, 0.049723, 0.049723",\ + "0.055443, 0.055443, 0.055443, 0.055443, 0.055443",\ + "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\ + "0.368589, 0.368589, 0.368589, 0.368589, 0.368589",\ + "1.002262, 1.002262, 1.002262, 1.002262, 1.002262"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_min_2568*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[19]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011"); + values ( "0.486016, 0.718373, 0.902601, 1.196441, 1.764052",\ + "0.505233, 0.737590, 0.921817, 1.215657, 1.783269",\ + "0.536881, 0.769238, 0.953465, 1.247305, 1.814917",\ + "0.827470, 1.059827, 1.244054, 1.537894, 2.105506",\ + "1.421473, 1.653830, 1.838057, 2.131897, 2.699509",\ + "0.574330, 0.805691, 0.989882, 1.283746, 1.851406",\ + "0.593546, 0.824908, 1.009098, 1.302962, 1.870622",\ + "0.625194, 0.856556, 1.040746, 1.334610, 1.902271",\ + "0.915783, 1.147145, 1.331335, 1.625199, 2.192860",\ + "1.509786, 1.741148, 1.925338, 2.219203, 2.786862",\ + "0.663471, 0.886024, 1.069909, 1.363774, 1.931437",\ + "0.682687, 0.905240, 1.089125, 1.382991, 1.950654",\ + "0.714335, 0.936888, 1.120773, 1.414639, 1.982302",\ + "1.004924, 1.227477, 1.411362, 1.705228, 2.272891",\ + "1.598927, 1.821480, 2.005365, 2.299231, 2.866894",\ + "0.726940, 0.943856, 1.127617, 1.421213, 1.988470",\ + "0.746156, 0.963072, 1.146833, 1.440429, 2.007687",\ + "0.777804, 0.994720, 1.178482, 1.472077, 2.039335",\ + "1.068393, 1.285309, 1.469070, 1.762666, 2.329924",\ + "1.662396, 1.879312, 2.063073, 2.356669, 2.923927",\ + "1.062221, 1.249183, 1.431275, 1.724391, 2.290713",\ + "1.081437, 1.268400, 1.450491, 1.743608, 2.309929",\ + "1.113086, 1.300048, 1.482139, 1.775256, 2.341578",\ + "1.403675, 1.590637, 1.772728, 2.065845, 2.632166",\ + "1.997678, 2.184640, 2.366731, 2.659848, 3.226169"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011"); + values ( "0.115267, 0.115267, 0.115267, 0.115267, 0.115267",\ + "0.141939, 0.141939, 0.141939, 0.141939, 0.141939",\ + "0.190556, 0.190556, 0.190556, 0.190556, 0.190556",\ + "0.817533, 0.817533, 0.817533, 0.817533, 0.817533",\ + "2.193353, 2.193353, 2.193353, 2.193353, 2.193353",\ + "0.115267, 0.115267, 0.115267, 0.115267, 0.115267",\ + "0.141939, 0.141939, 0.141939, 0.141939, 0.141939",\ + "0.190556, 0.190556, 0.190556, 0.190556, 0.190556",\ + "0.817533, 0.817533, 0.817533, 0.817533, 0.817533",\ + "2.193353, 2.193353, 2.193353, 2.193353, 2.193353",\ + "0.115267, 0.115267, 0.115267, 0.115267, 0.115267",\ + "0.141939, 0.141939, 0.141939, 0.141939, 0.141939",\ + "0.190556, 0.190556, 0.190556, 0.190556, 0.190556",\ + "0.817533, 0.817533, 0.817533, 0.817533, 0.817533",\ + "2.193353, 2.193353, 2.193353, 2.193353, 2.193353",\ + "0.115267, 0.115267, 0.115267, 0.115267, 0.115267",\ + "0.141939, 0.141939, 0.141939, 0.141939, 0.141939",\ + "0.190556, 0.190556, 0.190556, 0.190556, 0.190556",\ + "0.817533, 0.817533, 0.817533, 0.817533, 0.817533",\ + "2.193353, 2.193353, 2.193353, 2.193353, 2.193353",\ + "0.115267, 0.115267, 0.115267, 0.115267, 0.115267",\ + "0.141939, 0.141939, 0.141939, 0.141939, 0.141939",\ + "0.190556, 0.190556, 0.190556, 0.190556, 0.190556",\ + "0.817533, 0.817533, 0.817533, 0.817533, 0.817533",\ + "2.193353, 2.193353, 2.193353, 2.193353, 2.193353"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011"); + values ( "0.498430, 0.730787, 0.915014, 1.208854, 1.776466",\ + "0.506236, 0.738593, 0.922821, 1.216661, 1.784272",\ + "0.519618, 0.751975, 0.936202, 1.230042, 1.797654",\ + "0.671564, 0.903921, 1.088148, 1.381988, 1.949600",\ + "1.004998, 1.237355, 1.421583, 1.715423, 2.283034",\ + "0.586743, 0.818105, 1.002295, 1.296159, 1.863819",\ + "0.594550, 0.825911, 1.010102, 1.303966, 1.871626",\ + "0.607931, 0.839293, 1.023483, 1.317347, 1.885008",\ + "0.759877, 0.991239, 1.175429, 1.469293, 2.036953",\ + "1.093312, 1.324673, 1.508864, 1.802728, 2.370388",\ + "0.675884, 0.898437, 1.082322, 1.376188, 1.943851",\ + "0.683691, 0.906244, 1.090129, 1.383994, 1.951658",\ + "0.697072, 0.919625, 1.103510, 1.397376, 1.965039",\ + "0.849018, 1.071571, 1.255456, 1.549322, 2.116985",\ + "1.182453, 1.405006, 1.588891, 1.882756, 2.450419",\ + "0.739353, 0.956269, 1.140030, 1.433626, 2.000884",\ + "0.747160, 0.964076, 1.147837, 1.441433, 2.008690",\ + "0.760541, 0.977457, 1.161218, 1.454814, 2.022072",\ + "0.912487, 1.129403, 1.313164, 1.606760, 2.174018",\ + "1.245922, 1.462838, 1.646599, 1.940195, 2.507452",\ + "1.074634, 1.261597, 1.443688, 1.736805, 2.303126",\ + "1.082441, 1.269403, 1.451495, 1.744612, 2.310933",\ + "1.095823, 1.282785, 1.464876, 1.757993, 2.324314",\ + "1.247769, 1.434731, 1.616822, 1.909939, 2.476260",\ + "1.581203, 1.768166, 1.950257, 2.243373, 2.809695"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011"); + values ( "0.049723, 0.049723, 0.049723, 0.049723, 0.049723",\ + "0.055443, 0.055443, 0.055443, 0.055443, 0.055443",\ + "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\ + "0.368589, 0.368589, 0.368589, 0.368589, 0.368589",\ + "1.002262, 1.002262, 1.002262, 1.002262, 1.002262",\ + "0.049723, 0.049723, 0.049723, 0.049723, 0.049723",\ + "0.055443, 0.055443, 0.055443, 0.055443, 0.055443",\ + "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\ + "0.368589, 0.368589, 0.368589, 0.368589, 0.368589",\ + "1.002262, 1.002262, 1.002262, 1.002262, 1.002262",\ + "0.049723, 0.049723, 0.049723, 0.049723, 0.049723",\ + "0.055443, 0.055443, 0.055443, 0.055443, 0.055443",\ + "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\ + "0.368589, 0.368589, 0.368589, 0.368589, 0.368589",\ + "1.002262, 1.002262, 1.002262, 1.002262, 1.002262",\ + "0.049723, 0.049723, 0.049723, 0.049723, 0.049723",\ + "0.055443, 0.055443, 0.055443, 0.055443, 0.055443",\ + "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\ + "0.368589, 0.368589, 0.368589, 0.368589, 0.368589",\ + "1.002262, 1.002262, 1.002262, 1.002262, 1.002262",\ + "0.049723, 0.049723, 0.049723, 0.049723, 0.049723",\ + "0.055443, 0.055443, 0.055443, 0.055443, 0.055443",\ + "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\ + "0.368589, 0.368589, 0.368589, 0.368589, 0.368589",\ + "1.002262, 1.002262, 1.002262, 1.002262, 1.002262"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_min_2617*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[22]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.524148, 0.759556, 0.949466, 1.254683, 1.845217",\ + "0.543365, 0.778772, 0.968683, 1.273899, 1.864433",\ + "0.575013, 0.810420, 1.000331, 1.305547, 1.896082",\ + "0.865602, 1.101009, 1.290920, 1.596136, 2.186671",\ + "1.459605, 1.695012, 1.884923, 2.190139, 2.780674",\ + "0.612629, 0.846874, 1.036747, 1.341988, 1.932570",\ + "0.631845, 0.866090, 1.055964, 1.361204, 1.951787",\ + "0.663493, 0.897739, 1.087612, 1.392852, 1.983435",\ + "0.954082, 1.188328, 1.378201, 1.683442, 2.274024",\ + "1.548085, 1.782331, 1.972204, 2.277444, 2.868027",\ + "0.702172, 0.927207, 1.116774, 1.422016, 2.012602",\ + "0.721389, 0.946423, 1.135991, 1.441233, 2.031818",\ + "0.753037, 0.978072, 1.167639, 1.472881, 2.063467",\ + "1.043626, 1.268661, 1.458228, 1.763470, 2.354056",\ + "1.637629, 1.862664, 2.052231, 2.357473, 2.948059",\ + "0.765979, 0.985042, 1.174496, 1.479482, 2.069690",\ + "0.785195, 1.004258, 1.193712, 1.498699, 2.088906",\ + "0.816843, 1.035906, 1.225360, 1.530347, 2.120554",\ + "1.107432, 1.326495, 1.515949, 1.820936, 2.411143",\ + "1.701435, 1.920498, 2.109952, 2.414939, 3.005147",\ + "1.103410, 1.290390, 1.478156, 1.782685, 2.371999",\ + "1.122626, 1.309606, 1.497372, 1.801901, 2.391215",\ + "1.154274, 1.341254, 1.529020, 1.833550, 2.422863",\ + "1.444863, 1.631843, 1.819609, 2.124139, 2.713452",\ + "2.038866, 2.225846, 2.413612, 2.718142, 3.307455"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.115267, 0.115267, 0.115267, 0.115267, 0.115267",\ + "0.141939, 0.141939, 0.141939, 0.141939, 0.141939",\ + "0.190556, 0.190556, 0.190556, 0.190556, 0.190556",\ + "0.817533, 0.817533, 0.817533, 0.817533, 0.817533",\ + "2.193353, 2.193353, 2.193353, 2.193353, 2.193353",\ + "0.115267, 0.115267, 0.115267, 0.115267, 0.115267",\ + "0.141939, 0.141939, 0.141939, 0.141939, 0.141939",\ + "0.190556, 0.190556, 0.190556, 0.190556, 0.190556",\ + "0.817533, 0.817533, 0.817533, 0.817533, 0.817533",\ + "2.193353, 2.193353, 2.193353, 2.193353, 2.193353",\ + "0.115267, 0.115267, 0.115267, 0.115267, 0.115267",\ + "0.141939, 0.141939, 0.141939, 0.141939, 0.141939",\ + "0.190556, 0.190556, 0.190556, 0.190556, 0.190556",\ + "0.817533, 0.817533, 0.817533, 0.817533, 0.817533",\ + "2.193353, 2.193353, 2.193353, 2.193353, 2.193353",\ + "0.115267, 0.115267, 0.115267, 0.115267, 0.115267",\ + "0.141939, 0.141939, 0.141939, 0.141939, 0.141939",\ + "0.190556, 0.190556, 0.190556, 0.190556, 0.190556",\ + "0.817533, 0.817533, 0.817533, 0.817533, 0.817533",\ + "2.193353, 2.193353, 2.193353, 2.193353, 2.193353",\ + "0.115267, 0.115267, 0.115267, 0.115267, 0.115267",\ + "0.141939, 0.141939, 0.141939, 0.141939, 0.141939",\ + "0.190556, 0.190556, 0.190556, 0.190556, 0.190556",\ + "0.817533, 0.817533, 0.817533, 0.817533, 0.817533",\ + "2.193353, 2.193353, 2.193353, 2.193353, 2.193353"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.536562, 0.771969, 0.961880, 1.267096, 1.857630",\ + "0.544368, 0.779776, 0.969686, 1.274903, 1.865437",\ + "0.557750, 0.793157, 0.983068, 1.288284, 1.878819",\ + "0.709696, 0.945103, 1.135014, 1.440230, 2.030764",\ + "1.043130, 1.278538, 1.468448, 1.773665, 2.364199",\ + "0.625042, 0.859287, 1.049161, 1.354401, 1.944984",\ + "0.632849, 0.867094, 1.056967, 1.362208, 1.952790",\ + "0.646230, 0.880476, 1.070349, 1.375589, 1.966172",\ + "0.798176, 1.032422, 1.222295, 1.527535, 2.118118",\ + "1.131611, 1.365856, 1.555729, 1.860970, 2.451552",\ + "0.714586, 0.939620, 1.129188, 1.434430, 2.025015",\ + "0.722392, 0.947427, 1.136994, 1.442236, 2.032822",\ + "0.735774, 0.960809, 1.150376, 1.455618, 2.046204",\ + "0.887720, 1.112755, 1.302322, 1.607564, 2.198149",\ + "1.221154, 1.446189, 1.635756, 1.940998, 2.531584",\ + "0.778392, 0.997455, 1.186909, 1.491896, 2.082103",\ + "0.786199, 1.005262, 1.194716, 1.499702, 2.089910",\ + "0.799580, 1.018643, 1.208097, 1.513084, 2.103292",\ + "0.951526, 1.170589, 1.360043, 1.665030, 2.255237",\ + "1.284961, 1.504024, 1.693478, 1.998464, 2.588672",\ + "1.115823, 1.302803, 1.490569, 1.795098, 2.384412",\ + "1.123630, 1.310610, 1.498376, 1.802905, 2.392219",\ + "1.137011, 1.323991, 1.511757, 1.816287, 2.405600",\ + "1.288957, 1.475937, 1.663703, 1.968233, 2.557546",\ + "1.622392, 1.809372, 1.997138, 2.301667, 2.890981"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.049723, 0.049723, 0.049723, 0.049723, 0.049723",\ + "0.055443, 0.055443, 0.055443, 0.055443, 0.055443",\ + "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\ + "0.368589, 0.368589, 0.368589, 0.368589, 0.368589",\ + "1.002262, 1.002262, 1.002262, 1.002262, 1.002262",\ + "0.049723, 0.049723, 0.049723, 0.049723, 0.049723",\ + "0.055443, 0.055443, 0.055443, 0.055443, 0.055443",\ + "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\ + "0.368589, 0.368589, 0.368589, 0.368589, 0.368589",\ + "1.002262, 1.002262, 1.002262, 1.002262, 1.002262",\ + "0.049723, 0.049723, 0.049723, 0.049723, 0.049723",\ + "0.055443, 0.055443, 0.055443, 0.055443, 0.055443",\ + "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\ + "0.368589, 0.368589, 0.368589, 0.368589, 0.368589",\ + "1.002262, 1.002262, 1.002262, 1.002262, 1.002262",\ + "0.049723, 0.049723, 0.049723, 0.049723, 0.049723",\ + "0.055443, 0.055443, 0.055443, 0.055443, 0.055443",\ + "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\ + "0.368589, 0.368589, 0.368589, 0.368589, 0.368589",\ + "1.002262, 1.002262, 1.002262, 1.002262, 1.002262",\ + "0.049723, 0.049723, 0.049723, 0.049723, 0.049723",\ + "0.055443, 0.055443, 0.055443, 0.055443, 0.055443",\ + "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\ + "0.368589, 0.368589, 0.368589, 0.368589, 0.368589",\ + "1.002262, 1.002262, 1.002262, 1.002262, 1.002262"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_min*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[25]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011"); + values ( "0.507236, 0.738300, 0.923184, 1.222269, 1.802199",\ + "0.526452, 0.757517, 0.942400, 1.241485, 1.821415",\ + "0.558100, 0.789165, 0.974048, 1.273133, 1.853063",\ + "0.848689, 1.079754, 1.264637, 1.563722, 2.143652",\ + "1.442692, 1.673757, 1.858641, 2.157725, 2.737655",\ + "0.595614, 0.825618, 1.010465, 1.309574, 1.889552",\ + "0.614831, 0.844835, 1.029681, 1.328790, 1.908768",\ + "0.646479, 0.876483, 1.061329, 1.360438, 1.940417",\ + "0.937068, 1.167072, 1.351918, 1.651027, 2.231006",\ + "1.531071, 1.761075, 1.945922, 2.245030, 2.825009",\ + "0.685193, 0.905949, 1.090492, 1.389602, 1.969584",\ + "0.704409, 0.925165, 1.109708, 1.408819, 1.988800",\ + "0.736058, 0.956813, 1.141356, 1.440467, 2.020448",\ + "1.026647, 1.247402, 1.431945, 1.731056, 2.311038",\ + "1.620650, 1.841405, 2.025949, 2.325059, 2.905041",\ + "0.749178, 0.963779, 1.148202, 1.447056, 2.026647",\ + "0.768394, 0.982995, 1.167418, 1.466272, 2.045864",\ + "0.800042, 1.014643, 1.199067, 1.497920, 2.077512",\ + "1.090631, 1.305233, 1.489656, 1.788509, 2.368101",\ + "1.684634, 1.899235, 2.083659, 2.382513, 2.962104",\ + "1.087729, 1.269086, 1.451859, 1.750247, 2.328927",\ + "1.106946, 1.288302, 1.471076, 1.769464, 2.348143",\ + "1.138594, 1.319950, 1.502724, 1.801112, 2.379791",\ + "1.429183, 1.610539, 1.793313, 2.091701, 2.670381",\ + "2.023186, 2.204542, 2.387316, 2.685704, 3.264384"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011"); + values ( "0.115268, 0.115268, 0.115268, 0.115268, 0.115268",\ + "0.141939, 0.141939, 0.141939, 0.141939, 0.141939",\ + "0.190556, 0.190556, 0.190556, 0.190556, 0.190556",\ + "0.817533, 0.817533, 0.817533, 0.817533, 0.817533",\ + "2.193353, 2.193353, 2.193353, 2.193353, 2.193353",\ + "0.115268, 0.115268, 0.115268, 0.115268, 0.115268",\ + "0.141939, 0.141939, 0.141939, 0.141939, 0.141939",\ + "0.190556, 0.190556, 0.190556, 0.190556, 0.190556",\ + "0.817533, 0.817533, 0.817533, 0.817533, 0.817533",\ + "2.193353, 2.193353, 2.193353, 2.193353, 2.193353",\ + "0.115268, 0.115268, 0.115268, 0.115268, 0.115268",\ + "0.141939, 0.141939, 0.141939, 0.141939, 0.141939",\ + "0.190556, 0.190556, 0.190556, 0.190556, 0.190556",\ + "0.817533, 0.817533, 0.817533, 0.817533, 0.817533",\ + "2.193353, 2.193353, 2.193353, 2.193353, 2.193353",\ + "0.115268, 0.115268, 0.115268, 0.115268, 0.115268",\ + "0.141939, 0.141939, 0.141939, 0.141939, 0.141939",\ + "0.190556, 0.190556, 0.190556, 0.190556, 0.190556",\ + "0.817533, 0.817533, 0.817533, 0.817533, 0.817533",\ + "2.193353, 2.193353, 2.193353, 2.193353, 2.193353",\ + "0.115268, 0.115268, 0.115268, 0.115268, 0.115268",\ + "0.141939, 0.141939, 0.141939, 0.141939, 0.141939",\ + "0.190556, 0.190556, 0.190556, 0.190556, 0.190556",\ + "0.817533, 0.817533, 0.817533, 0.817533, 0.817533",\ + "2.193353, 2.193353, 2.193353, 2.193353, 2.193353"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011"); + values ( "0.519649, 0.750714, 0.935597, 1.234682, 1.814612",\ + "0.527456, 0.758521, 0.943404, 1.242489, 1.822419",\ + "0.540837, 0.771902, 0.956786, 1.255870, 1.835800",\ + "0.692783, 0.923848, 1.108731, 1.407816, 1.987746",\ + "1.026218, 1.257282, 1.442166, 1.741251, 2.321181",\ + "0.608028, 0.838032, 1.022878, 1.321987, 1.901966",\ + "0.615835, 0.845838, 1.030685, 1.329794, 1.909772",\ + "0.629216, 0.859220, 1.044067, 1.343176, 1.923154",\ + "0.781162, 1.011166, 1.196012, 1.495121, 2.075100",\ + "1.114597, 1.344600, 1.529447, 1.828556, 2.408534",\ + "0.697607, 0.918362, 1.102905, 1.402016, 1.981997",\ + "0.705413, 0.926169, 1.110712, 1.409823, 1.989804",\ + "0.718795, 0.939550, 1.124094, 1.423204, 2.003186",\ + "0.870741, 1.091496, 1.276039, 1.575150, 2.155131",\ + "1.204175, 1.424931, 1.609474, 1.908584, 2.488566",\ + "0.761591, 0.976192, 1.160616, 1.459469, 2.039061",\ + "0.769398, 0.983999, 1.168422, 1.467276, 2.046868",\ + "0.782779, 0.997381, 1.181804, 1.480658, 2.060249",\ + "0.934725, 1.149326, 1.333750, 1.632603, 2.212195",\ + "1.268160, 1.482761, 1.667184, 1.966038, 2.545630",\ + "1.100143, 1.281499, 1.464273, 1.762661, 2.341341",\ + "1.107950, 1.289306, 1.472080, 1.770468, 2.349147",\ + "1.121331, 1.302687, 1.485461, 1.783849, 2.362529",\ + "1.273277, 1.454633, 1.637407, 1.935795, 2.514474",\ + "1.606712, 1.788068, 1.970841, 2.269229, 2.847909"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011"); + values ( "0.049723, 0.049723, 0.049723, 0.049723, 0.049723",\ + "0.055443, 0.055443, 0.055443, 0.055443, 0.055443",\ + "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\ + "0.368589, 0.368589, 0.368589, 0.368589, 0.368589",\ + "1.002262, 1.002262, 1.002262, 1.002262, 1.002262",\ + "0.049723, 0.049723, 0.049723, 0.049723, 0.049723",\ + "0.055443, 0.055443, 0.055443, 0.055443, 0.055443",\ + "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\ + "0.368589, 0.368589, 0.368589, 0.368589, 0.368589",\ + "1.002262, 1.002262, 1.002262, 1.002262, 1.002262",\ + "0.049723, 0.049723, 0.049723, 0.049723, 0.049723",\ + "0.055443, 0.055443, 0.055443, 0.055443, 0.055443",\ + "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\ + "0.368589, 0.368589, 0.368589, 0.368589, 0.368589",\ + "1.002262, 1.002262, 1.002262, 1.002262, 1.002262",\ + "0.049723, 0.049723, 0.049723, 0.049723, 0.049723",\ + "0.055443, 0.055443, 0.055443, 0.055443, 0.055443",\ + "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\ + "0.368589, 0.368589, 0.368589, 0.368589, 0.368589",\ + "1.002262, 1.002262, 1.002262, 1.002262, 1.002262",\ + "0.049723, 0.049723, 0.049723, 0.049723, 0.049723",\ + "0.055443, 0.055443, 0.055443, 0.055443, 0.055443",\ + "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\ + "0.368589, 0.368589, 0.368589, 0.368589, 0.368589",\ + "1.002262, 1.002262, 1.002262, 1.002262, 1.002262"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_min_2419*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[29]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.424754, 0.655573, 0.839933, 1.133631, 1.700828",\ + "0.443986, 0.674805, 0.859165, 1.152863, 1.720060",\ + "0.475654, 0.706473, 0.890833, 1.184531, 1.751728",\ + "0.765910, 0.996730, 1.181089, 1.474787, 2.041985",\ + "1.359893, 1.590712, 1.775072, 2.068770, 2.635967",\ + "0.513060, 0.742891, 0.927214, 1.220936, 1.788182",\ + "0.532291, 0.762123, 0.946446, 1.240168, 1.807413",\ + "0.563959, 0.793791, 0.978114, 1.271836, 1.839081",\ + "0.854216, 1.084048, 1.268370, 1.562092, 2.129338",\ + "1.448198, 1.678030, 1.862353, 2.156075, 2.723320",\ + "0.602427, 0.823222, 1.007241, 1.300965, 1.868213",\ + "0.621658, 0.842453, 1.026473, 1.320196, 1.887445",\ + "0.653326, 0.874121, 1.058141, 1.351864, 1.919113",\ + "0.943583, 1.164378, 1.348397, 1.642121, 2.209370",\ + "1.537565, 1.758360, 1.942380, 2.236103, 2.803352",\ + "0.666215, 0.881051, 1.064950, 1.358403, 1.925246",\ + "0.685446, 0.900283, 1.084182, 1.377634, 1.944478",\ + "0.717114, 0.931951, 1.115850, 1.409302, 1.976146",\ + "1.007371, 1.222207, 1.406106, 1.699559, 2.266402",\ + "1.601353, 1.816190, 2.000089, 2.293541, 2.860385",\ + "1.003512, 1.186351, 1.368608, 1.661581, 2.227489",\ + "1.022744, 1.205583, 1.387839, 1.680812, 2.246720",\ + "1.054412, 1.237251, 1.419507, 1.712481, 2.278388",\ + "1.344668, 1.527507, 1.709764, 2.002737, 2.568645",\ + "1.938651, 2.121490, 2.303746, 2.596720, 3.162627"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.112220, 0.112220, 0.112220, 0.112220, 0.112220",\ + "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\ + "0.189997, 0.189997, 0.189997, 0.189997, 0.189997",\ + "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\ + "2.194227, 2.194227, 2.194227, 2.194227, 2.194227",\ + "0.112220, 0.112220, 0.112220, 0.112220, 0.112220",\ + "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\ + "0.189997, 0.189997, 0.189997, 0.189997, 0.189997",\ + "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\ + "2.194227, 2.194227, 2.194227, 2.194227, 2.194227",\ + "0.112220, 0.112220, 0.112220, 0.112220, 0.112220",\ + "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\ + "0.189997, 0.189997, 0.189997, 0.189997, 0.189997",\ + "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\ + "2.194227, 2.194227, 2.194227, 2.194227, 2.194227",\ + "0.112220, 0.112220, 0.112220, 0.112220, 0.112220",\ + "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\ + "0.189997, 0.189997, 0.189997, 0.189997, 0.189997",\ + "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\ + "2.194227, 2.194227, 2.194227, 2.194227, 2.194227",\ + "0.112220, 0.112220, 0.112220, 0.112220, 0.112220",\ + "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\ + "0.189997, 0.189997, 0.189997, 0.189997, 0.189997",\ + "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\ + "2.194227, 2.194227, 2.194227, 2.194227, 2.194227"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.436529, 0.667348, 0.851708, 1.145406, 1.712603",\ + "0.444331, 0.675151, 0.859510, 1.153208, 1.720405",\ + "0.457727, 0.688547, 0.872906, 1.166604, 1.733801",\ + "0.609942, 0.840761, 1.025121, 1.318819, 1.886016",\ + "0.943575, 1.174394, 1.358754, 1.652452, 2.219649",\ + "0.524834, 0.754666, 0.938989, 1.232711, 1.799956",\ + "0.532637, 0.762468, 0.946791, 1.240513, 1.807759",\ + "0.546033, 0.775864, 0.960187, 1.253909, 1.821155",\ + "0.698247, 0.928079, 1.112402, 1.406124, 1.973369",\ + "1.031881, 1.261712, 1.446035, 1.739757, 2.307003",\ + "0.614201, 0.834996, 1.019016, 1.312739, 1.879988",\ + "0.622004, 0.842799, 1.026818, 1.320542, 1.887790",\ + "0.635400, 0.856195, 1.040214, 1.333938, 1.901186",\ + "0.787614, 1.008409, 1.192429, 1.486152, 2.053401",\ + "1.121248, 1.342043, 1.526062, 1.819786, 2.387034",\ + "0.677989, 0.892826, 1.076725, 1.370177, 1.937021",\ + "0.685792, 0.900628, 1.084527, 1.377980, 1.944823",\ + "0.699188, 0.914024, 1.097923, 1.391376, 1.958219",\ + "0.851402, 1.066239, 1.250138, 1.543590, 2.110434",\ + "1.185036, 1.399872, 1.583771, 1.877224, 2.444067",\ + "1.015287, 1.198126, 1.380382, 1.673356, 2.239263",\ + "1.023089, 1.205928, 1.388185, 1.681158, 2.247066",\ + "1.036485, 1.219324, 1.401581, 1.694554, 2.260462",\ + "1.188700, 1.371539, 1.553795, 1.846768, 2.412676",\ + "1.522333, 1.705172, 1.887429, 2.180402, 2.746310"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\ + "0.055489, 0.055489, 0.055489, 0.055489, 0.055489",\ + "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\ + "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\ + "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\ + "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\ + "0.055489, 0.055489, 0.055489, 0.055489, 0.055489",\ + "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\ + "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\ + "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\ + "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\ + "0.055489, 0.055489, 0.055489, 0.055489, 0.055489",\ + "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\ + "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\ + "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\ + "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\ + "0.055489, 0.055489, 0.055489, 0.055489, 0.055489",\ + "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\ + "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\ + "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\ + "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\ + "0.055489, 0.055489, 0.055489, 0.055489, 0.055489",\ + "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\ + "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\ + "1.002321, 1.002321, 1.002321, 1.002321, 1.002321"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_min_2319*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[30]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.417176, 0.631777, 0.810666, 1.100090, 1.661570",\ + "0.436407, 0.651008, 0.829897, 1.119321, 1.680801",\ + "0.468075, 0.682676, 0.861565, 1.150989, 1.712470",\ + "0.758331, 0.972932, 1.151822, 1.441245, 2.002726",\ + "1.352314, 1.566915, 1.745804, 2.035228, 2.596708",\ + "0.505449, 0.719094, 0.897947, 1.187395, 1.748923",\ + "0.524681, 0.738326, 0.917178, 1.206626, 1.768155",\ + "0.556349, 0.769994, 0.948847, 1.238294, 1.799823",\ + "0.846605, 1.060250, 1.239103, 1.528551, 2.090079",\ + "1.440588, 1.654232, 1.833085, 2.122533, 2.684062",\ + "0.594993, 0.799422, 0.977974, 1.267423, 1.828955",\ + "0.614224, 0.818654, 0.997205, 1.286655, 1.848186",\ + "0.645892, 0.850322, 1.028873, 1.318323, 1.879855",\ + "0.936148, 1.140578, 1.319129, 1.608579, 2.170111",\ + "1.530131, 1.734560, 1.913112, 2.202561, 2.764093",\ + "0.659061, 0.857252, 1.035670, 1.324854, 1.885975",\ + "0.678293, 0.876483, 1.054902, 1.344086, 1.905207",\ + "0.709961, 0.908151, 1.086570, 1.375754, 1.936875",\ + "1.000217, 1.198407, 1.376826, 1.666010, 2.227131",\ + "1.594199, 1.792390, 1.970809, 2.259993, 2.821113",\ + "0.982918, 1.162544, 1.339325, 1.628026, 2.188202",\ + "1.002150, 1.181776, 1.358556, 1.647258, 2.207434",\ + "1.033818, 1.213444, 1.390224, 1.678926, 2.239102",\ + "1.324074, 1.503700, 1.680480, 1.969182, 2.529358",\ + "1.918056, 2.097682, 2.274463, 2.563165, 3.123341"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.112216, 0.112216, 0.112216, 0.112216, 0.112216",\ + "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\ + "0.189998, 0.189998, 0.189998, 0.189998, 0.189998",\ + "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\ + "2.194229, 2.194229, 2.194229, 2.194229, 2.194229",\ + "0.112216, 0.112216, 0.112216, 0.112216, 0.112216",\ + "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\ + "0.189998, 0.189998, 0.189998, 0.189998, 0.189998",\ + "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\ + "2.194229, 2.194229, 2.194229, 2.194229, 2.194229",\ + "0.112216, 0.112216, 0.112216, 0.112216, 0.112216",\ + "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\ + "0.189998, 0.189998, 0.189998, 0.189998, 0.189998",\ + "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\ + "2.194229, 2.194229, 2.194229, 2.194229, 2.194229",\ + "0.112216, 0.112216, 0.112216, 0.112216, 0.112216",\ + "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\ + "0.189998, 0.189998, 0.189998, 0.189998, 0.189998",\ + "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\ + "2.194229, 2.194229, 2.194229, 2.194229, 2.194229",\ + "0.112216, 0.112216, 0.112216, 0.112216, 0.112216",\ + "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\ + "0.189998, 0.189998, 0.189998, 0.189998, 0.189998",\ + "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\ + "2.194229, 2.194229, 2.194229, 2.194229, 2.194229"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.428949, 0.643550, 0.822439, 1.111863, 1.673344",\ + "0.436752, 0.651353, 0.830242, 1.119666, 1.681146",\ + "0.450148, 0.664749, 0.843638, 1.133062, 1.694542",\ + "0.602363, 0.816964, 0.995853, 1.285277, 1.846757",\ + "0.935996, 1.150597, 1.329487, 1.618910, 2.180391",\ + "0.517223, 0.730868, 0.909721, 1.199168, 1.760697",\ + "0.525026, 0.738670, 0.917523, 1.206971, 1.768500",\ + "0.538422, 0.752066, 0.930919, 1.220367, 1.781896",\ + "0.690637, 0.904281, 1.083134, 1.372582, 1.934110",\ + "1.024270, 1.237915, 1.416768, 1.706216, 2.267744",\ + "0.606766, 0.811196, 0.989747, 1.279197, 1.840729",\ + "0.614569, 0.818998, 0.997550, 1.286999, 1.848531",\ + "0.627965, 0.832394, 1.010946, 1.300395, 1.861927",\ + "0.780180, 0.984609, 1.163161, 1.452610, 2.014142",\ + "1.113814, 1.318243, 1.496794, 1.786244, 2.347776",\ + "0.670835, 0.869025, 1.047444, 1.336628, 1.897749",\ + "0.678637, 0.876828, 1.055247, 1.344431, 1.905551",\ + "0.692033, 0.890224, 1.068643, 1.357827, 1.918947",\ + "0.844248, 1.042439, 1.220857, 1.510042, 2.071162",\ + "1.177882, 1.376072, 1.554491, 1.843675, 2.404796",\ + "0.994692, 1.174318, 1.351099, 1.639800, 2.199976",\ + "1.002494, 1.182121, 1.358901, 1.647603, 2.207778",\ + "1.015890, 1.195517, 1.372297, 1.660999, 2.221174",\ + "1.168105, 1.347732, 1.524512, 1.813214, 2.373389",\ + "1.501739, 1.681365, 1.858145, 2.146847, 2.707023"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\ + "0.055490, 0.055490, 0.055490, 0.055490, 0.055490",\ + "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\ + "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\ + "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\ + "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\ + "0.055490, 0.055490, 0.055490, 0.055490, 0.055490",\ + "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\ + "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\ + "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\ + "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\ + "0.055490, 0.055490, 0.055490, 0.055490, 0.055490",\ + "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\ + "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\ + "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\ + "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\ + "0.055490, 0.055490, 0.055490, 0.055490, 0.055490",\ + "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\ + "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\ + "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\ + "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\ + "0.055490, 0.055490, 0.055490, 0.055490, 0.055490",\ + "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\ + "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\ + "1.002321, 1.002321, 1.002321, 1.002321, 1.002321"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_min_2377*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[34]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011"); + values ( "0.566889, 0.778471, 0.964383, 1.255517, 1.814850",\ + "0.586120, 0.797703, 0.983615, 1.274748, 1.834081",\ + "0.617788, 0.829371, 1.015283, 1.306417, 1.865749",\ + "0.908045, 1.119627, 1.305539, 1.596673, 2.156006",\ + "1.502027, 1.713610, 1.899522, 2.190655, 2.749988",\ + "0.655251, 0.865790, 1.051664, 1.342822, 1.902203",\ + "0.674483, 0.885021, 1.070896, 1.362054, 1.921435",\ + "0.706151, 0.916689, 1.102564, 1.393722, 1.953103",\ + "0.996407, 1.206946, 1.392820, 1.683978, 2.243359",\ + "1.590390, 1.800928, 1.986803, 2.277961, 2.837342",\ + "0.744310, 0.946124, 1.131691, 1.422850, 1.982235",\ + "0.763542, 0.965355, 1.150923, 1.442082, 2.001466",\ + "0.795210, 0.997024, 1.182591, 1.473750, 2.033134",\ + "1.085467, 1.287280, 1.472847, 1.764007, 2.323391",\ + "1.679449, 1.881263, 2.066830, 2.357989, 2.917373",\ + "0.807605, 1.003952, 1.189403, 1.480278, 2.039247",\ + "0.826837, 1.023183, 1.208634, 1.499510, 2.058478",\ + "0.858505, 1.054851, 1.240302, 1.531178, 2.090147",\ + "1.148761, 1.345108, 1.530559, 1.821435, 2.380403",\ + "1.742744, 1.939090, 2.124541, 2.415417, 2.974385",\ + "1.127529, 1.309255, 1.493062, 1.783449, 2.341464",\ + "1.146761, 1.328487, 1.512293, 1.802681, 2.360695",\ + "1.178429, 1.360155, 1.543962, 1.834349, 2.392364",\ + "1.468686, 1.650411, 1.834218, 2.124605, 2.682620",\ + "2.062668, 2.244394, 2.428200, 2.718588, 3.276602"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011"); + values ( "0.112220, 0.112220, 0.112220, 0.112220, 0.112220",\ + "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\ + "0.189997, 0.189997, 0.189997, 0.189997, 0.189997",\ + "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\ + "2.194227, 2.194227, 2.194227, 2.194227, 2.194227",\ + "0.112220, 0.112220, 0.112220, 0.112220, 0.112220",\ + "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\ + "0.189997, 0.189997, 0.189997, 0.189997, 0.189997",\ + "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\ + "2.194227, 2.194227, 2.194227, 2.194227, 2.194227",\ + "0.112220, 0.112220, 0.112220, 0.112220, 0.112220",\ + "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\ + "0.189997, 0.189997, 0.189997, 0.189997, 0.189997",\ + "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\ + "2.194227, 2.194227, 2.194227, 2.194227, 2.194227",\ + "0.112220, 0.112220, 0.112220, 0.112220, 0.112220",\ + "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\ + "0.189997, 0.189997, 0.189997, 0.189997, 0.189997",\ + "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\ + "2.194227, 2.194227, 2.194227, 2.194227, 2.194227",\ + "0.112220, 0.112220, 0.112220, 0.112220, 0.112220",\ + "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\ + "0.189997, 0.189997, 0.189997, 0.189997, 0.189997",\ + "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\ + "2.194227, 2.194227, 2.194227, 2.194227, 2.194227"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011"); + values ( "0.578663, 0.790246, 0.976158, 1.267292, 1.826624",\ + "0.586466, 0.798048, 0.983960, 1.275094, 1.834427",\ + "0.599862, 0.811444, 0.997356, 1.288490, 1.847823",\ + "0.752076, 0.963659, 1.149571, 1.440704, 2.000037",\ + "1.085710, 1.297292, 1.483204, 1.774338, 2.333671",\ + "0.667026, 0.877564, 1.063439, 1.354597, 1.913978",\ + "0.674828, 0.885367, 1.071241, 1.362399, 1.921780",\ + "0.688224, 0.898763, 1.084637, 1.375795, 1.935176",\ + "0.840439, 1.050977, 1.236852, 1.528010, 2.087391",\ + "1.174072, 1.384611, 1.570485, 1.861643, 2.421024",\ + "0.756085, 0.957898, 1.143466, 1.434625, 1.994009",\ + "0.763888, 0.965701, 1.151268, 1.442428, 2.001812",\ + "0.777284, 0.979097, 1.164664, 1.455824, 2.015208",\ + "0.929498, 1.131311, 1.316879, 1.608038, 2.167422",\ + "1.263131, 1.464945, 1.650512, 1.941671, 2.501056",\ + "0.819380, 1.015726, 1.201177, 1.492053, 2.051021",\ + "0.827182, 1.023529, 1.208980, 1.499856, 2.058824",\ + "0.840578, 1.036925, 1.222376, 1.513252, 2.072220",\ + "0.992793, 1.189139, 1.374590, 1.665466, 2.224434",\ + "1.326426, 1.522773, 1.708224, 1.999099, 2.558068",\ + "1.139304, 1.321030, 1.504837, 1.795224, 2.353239",\ + "1.147106, 1.328832, 1.512639, 1.803026, 2.361041",\ + "1.160502, 1.342228, 1.526035, 1.816422, 2.374437",\ + "1.312717, 1.494443, 1.678249, 1.968637, 2.526651",\ + "1.646350, 1.828076, 2.011883, 2.302270, 2.860285"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011"); + values ( "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\ + "0.055489, 0.055489, 0.055489, 0.055489, 0.055489",\ + "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\ + "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\ + "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\ + "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\ + "0.055489, 0.055489, 0.055489, 0.055489, 0.055489",\ + "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\ + "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\ + "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\ + "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\ + "0.055489, 0.055489, 0.055489, 0.055489, 0.055489",\ + "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\ + "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\ + "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\ + "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\ + "0.055489, 0.055489, 0.055489, 0.055489, 0.055489",\ + "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\ + "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\ + "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\ + "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\ + "0.055489, 0.055489, 0.055489, 0.055489, 0.055489",\ + "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\ + "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\ + "1.002321, 1.002321, 1.002321, 1.002321, 1.002321"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_min_2596*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[35]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.541408, 0.751703, 0.928714, 1.212888, 1.762989",\ + "0.560640, 0.770935, 0.947946, 1.232119, 1.782221",\ + "0.592308, 0.802603, 0.979614, 1.263787, 1.813889",\ + "0.882565, 1.092860, 1.269870, 1.554044, 2.104145",\ + "1.476547, 1.686842, 1.863853, 2.148026, 2.698128",\ + "0.629685, 0.839022, 1.015995, 1.300193, 1.850343",\ + "0.648917, 0.858253, 1.035227, 1.319424, 1.869574",\ + "0.680585, 0.889921, 1.066895, 1.351092, 1.901242",\ + "0.970842, 1.180178, 1.357151, 1.641349, 2.191499",\ + "1.564824, 1.774160, 1.951134, 2.235331, 2.785481",\ + "0.718639, 0.919355, 1.096022, 1.380221, 1.930374",\ + "0.737870, 0.938586, 1.115254, 1.399453, 1.949606",\ + "0.769538, 0.970254, 1.146922, 1.431121, 1.981274",\ + "1.059795, 1.260511, 1.437178, 1.721377, 2.271530",\ + "1.653777, 1.854493, 2.031161, 2.315360, 2.865513",\ + "0.781897, 0.977177, 1.153713, 1.437638, 1.987364",\ + "0.801129, 0.996408, 1.172945, 1.456870, 2.006596",\ + "0.832797, 1.028076, 1.204613, 1.488538, 2.038264",\ + "1.123053, 1.318333, 1.494869, 1.778794, 2.328521",\ + "1.717036, 1.912315, 2.088852, 2.372777, 2.922503",\ + "1.102548, 1.282436, 1.457368, 1.740799, 2.289555",\ + "1.121780, 1.301668, 1.476600, 1.760030, 2.308787",\ + "1.153448, 1.333336, 1.508268, 1.791698, 2.340455",\ + "1.443705, 1.623593, 1.798525, 2.081955, 2.630712",\ + "2.037687, 2.217575, 2.392507, 2.675937, 3.224694"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.112220, 0.112220, 0.112220, 0.112220, 0.112220",\ + "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\ + "0.189997, 0.189997, 0.189997, 0.189997, 0.189997",\ + "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\ + "2.194227, 2.194227, 2.194227, 2.194227, 2.194227",\ + "0.112220, 0.112220, 0.112220, 0.112220, 0.112220",\ + "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\ + "0.189997, 0.189997, 0.189997, 0.189997, 0.189997",\ + "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\ + "2.194227, 2.194227, 2.194227, 2.194227, 2.194227",\ + "0.112220, 0.112220, 0.112220, 0.112220, 0.112220",\ + "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\ + "0.189997, 0.189997, 0.189997, 0.189997, 0.189997",\ + "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\ + "2.194227, 2.194227, 2.194227, 2.194227, 2.194227",\ + "0.112220, 0.112220, 0.112220, 0.112220, 0.112220",\ + "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\ + "0.189997, 0.189997, 0.189997, 0.189997, 0.189997",\ + "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\ + "2.194227, 2.194227, 2.194227, 2.194227, 2.194227",\ + "0.112220, 0.112220, 0.112220, 0.112220, 0.112220",\ + "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\ + "0.189997, 0.189997, 0.189997, 0.189997, 0.189997",\ + "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\ + "2.194227, 2.194227, 2.194227, 2.194227, 2.194227"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.553183, 0.763478, 0.940489, 1.224662, 1.774764",\ + "0.560986, 0.771280, 0.948291, 1.232465, 1.782566",\ + "0.574382, 0.784676, 0.961687, 1.245861, 1.795962",\ + "0.726596, 0.936891, 1.113902, 1.398075, 1.948177",\ + "1.060230, 1.270525, 1.447535, 1.731709, 2.281810",\ + "0.641460, 0.850796, 1.027770, 1.311967, 1.862117",\ + "0.649263, 0.858599, 1.035572, 1.319770, 1.869920",\ + "0.662659, 0.871995, 1.048968, 1.333166, 1.883316",\ + "0.814873, 1.024209, 1.201183, 1.485380, 2.035530",\ + "1.148507, 1.357843, 1.534816, 1.819014, 2.369164",\ + "0.730413, 0.931129, 1.107797, 1.391996, 1.942149",\ + "0.738216, 0.938932, 1.115599, 1.399798, 1.949951",\ + "0.751612, 0.952328, 1.128995, 1.413194, 1.963347",\ + "0.903826, 1.104542, 1.281210, 1.565409, 2.115561",\ + "1.237460, 1.438176, 1.614843, 1.899042, 2.449195",\ + "0.793672, 0.988951, 1.165488, 1.449413, 1.999139",\ + "0.801474, 0.996754, 1.173290, 1.457215, 2.006941",\ + "0.814870, 1.010150, 1.186686, 1.470611, 2.020338",\ + "0.967085, 1.162364, 1.338901, 1.622826, 2.172552",\ + "1.300718, 1.495998, 1.672534, 1.956459, 2.506185",\ + "1.114323, 1.294211, 1.469143, 1.752573, 2.301330",\ + "1.122126, 1.302013, 1.476946, 1.760376, 2.309132",\ + "1.135522, 1.315410, 1.490342, 1.773772, 2.322528",\ + "1.287736, 1.467624, 1.642556, 1.925986, 2.474743",\ + "1.621369, 1.801257, 1.976189, 2.259620, 2.808376"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\ + "0.055489, 0.055489, 0.055489, 0.055489, 0.055489",\ + "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\ + "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\ + "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\ + "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\ + "0.055489, 0.055489, 0.055489, 0.055489, 0.055489",\ + "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\ + "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\ + "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\ + "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\ + "0.055489, 0.055489, 0.055489, 0.055489, 0.055489",\ + "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\ + "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\ + "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\ + "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\ + "0.055489, 0.055489, 0.055489, 0.055489, 0.055489",\ + "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\ + "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\ + "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\ + "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\ + "0.055489, 0.055489, 0.055489, 0.055489, 0.055489",\ + "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\ + "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\ + "1.002321, 1.002321, 1.002321, 1.002321, 1.002321"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_min_2653*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[38]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.563785, 0.784261, 0.961831, 1.250241, 1.810232",\ + "0.583017, 0.803492, 0.981063, 1.269472, 1.829463",\ + "0.614685, 0.835161, 1.012731, 1.301141, 1.861132",\ + "0.904941, 1.125417, 1.302987, 1.591397, 2.151388",\ + "1.498924, 1.719399, 1.896969, 2.185379, 2.745370",\ + "0.652174, 0.871579, 1.049112, 1.337546, 1.897585",\ + "0.671405, 0.890811, 1.068343, 1.356778, 1.916817",\ + "0.703073, 0.922479, 1.100012, 1.388446, 1.948485",\ + "0.993330, 1.212735, 1.390268, 1.678702, 2.238741",\ + "1.587312, 1.806717, 1.984250, 2.272684, 2.832724",\ + "0.741539, 0.951911, 1.129139, 1.417575, 1.977617",\ + "0.760771, 0.971143, 1.148370, 1.436806, 1.996849",\ + "0.792439, 1.002811, 1.180039, 1.468474, 2.028517",\ + "1.082695, 1.293067, 1.470295, 1.758730, 2.318773",\ + "1.676677, 1.887050, 2.064277, 2.352713, 2.912755",\ + "0.805219, 1.009732, 1.186831, 1.475004, 2.034631",\ + "0.824451, 1.028963, 1.206063, 1.494235, 2.053863",\ + "0.856119, 1.060631, 1.237731, 1.525903, 2.085531",\ + "1.146375, 1.350887, 1.527987, 1.816159, 2.375787",\ + "1.740357, 1.944870, 2.121970, 2.410142, 2.969770",\ + "1.135828, 1.314976, 1.490487, 1.778174, 2.336852",\ + "1.155060, 1.334207, 1.509718, 1.797406, 2.356083",\ + "1.186728, 1.365875, 1.541386, 1.829074, 2.387752",\ + "1.476984, 1.656131, 1.831642, 2.119330, 2.678008",\ + "2.070967, 2.250114, 2.425625, 2.713313, 3.271990"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.112216, 0.112216, 0.112216, 0.112216, 0.112216",\ + "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\ + "0.189998, 0.189998, 0.189998, 0.189998, 0.189998",\ + "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\ + "2.194229, 2.194229, 2.194229, 2.194229, 2.194229",\ + "0.112216, 0.112216, 0.112216, 0.112216, 0.112216",\ + "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\ + "0.189998, 0.189998, 0.189998, 0.189998, 0.189998",\ + "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\ + "2.194229, 2.194229, 2.194229, 2.194229, 2.194229",\ + "0.112216, 0.112216, 0.112216, 0.112216, 0.112216",\ + "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\ + "0.189998, 0.189998, 0.189998, 0.189998, 0.189998",\ + "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\ + "2.194229, 2.194229, 2.194229, 2.194229, 2.194229",\ + "0.112216, 0.112216, 0.112216, 0.112216, 0.112216",\ + "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\ + "0.189998, 0.189998, 0.189998, 0.189998, 0.189998",\ + "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\ + "2.194229, 2.194229, 2.194229, 2.194229, 2.194229",\ + "0.112216, 0.112216, 0.112216, 0.112216, 0.112216",\ + "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\ + "0.189998, 0.189998, 0.189998, 0.189998, 0.189998",\ + "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\ + "2.194229, 2.194229, 2.194229, 2.194229, 2.194229"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.575559, 0.796035, 0.973605, 1.262015, 1.822006",\ + "0.583362, 0.803837, 0.981407, 1.269817, 1.829808",\ + "0.596758, 0.817233, 0.994803, 1.283213, 1.843204",\ + "0.748972, 0.969448, 1.147018, 1.435428, 1.995419",\ + "1.082606, 1.303082, 1.480652, 1.769062, 2.329053",\ + "0.663947, 0.883353, 1.060886, 1.349320, 1.909359",\ + "0.671750, 0.891155, 1.068688, 1.357122, 1.917162",\ + "0.685146, 0.904551, 1.082084, 1.370518, 1.930558",\ + "0.837361, 1.056766, 1.234299, 1.522733, 2.082772",\ + "1.170995, 1.390400, 1.567933, 1.856367, 2.416406",\ + "0.753313, 0.963685, 1.140913, 1.429348, 1.989391",\ + "0.761115, 0.971488, 1.148715, 1.437151, 1.997193",\ + "0.774511, 0.984884, 1.162111, 1.450547, 2.010589",\ + "0.926726, 1.137099, 1.314326, 1.602762, 2.162804",\ + "1.260360, 1.470732, 1.647960, 1.936395, 2.496438",\ + "0.816993, 1.021505, 1.198605, 1.486777, 2.046405",\ + "0.824796, 1.029308, 1.206408, 1.494580, 2.054208",\ + "0.838192, 1.042704, 1.219804, 1.507976, 2.067604",\ + "0.990406, 1.194919, 1.372019, 1.660191, 2.219819",\ + "1.324040, 1.528552, 1.705652, 1.993824, 2.553452",\ + "1.147602, 1.326749, 1.502260, 1.789948, 2.348625",\ + "1.155405, 1.334552, 1.510063, 1.797751, 2.356428",\ + "1.168801, 1.347948, 1.523459, 1.811147, 2.369824",\ + "1.321016, 1.500163, 1.675674, 1.963362, 2.522039",\ + "1.654649, 1.833796, 2.009307, 2.296995, 2.855672"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\ + "0.055490, 0.055490, 0.055490, 0.055490, 0.055490",\ + "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\ + "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\ + "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\ + "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\ + "0.055490, 0.055490, 0.055490, 0.055490, 0.055490",\ + "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\ + "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\ + "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\ + "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\ + "0.055490, 0.055490, 0.055490, 0.055490, 0.055490",\ + "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\ + "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\ + "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\ + "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\ + "0.055490, 0.055490, 0.055490, 0.055490, 0.055490",\ + "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\ + "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\ + "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\ + "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\ + "0.055490, 0.055490, 0.055490, 0.055490, 0.055490",\ + "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\ + "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\ + "1.002321, 1.002321, 1.002321, 1.002321, 1.002321"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_min_2304*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[39]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011"); + values ( "0.537611, 0.765413, 0.949557, 1.244019, 1.813116",\ + "0.556843, 0.784645, 0.968788, 1.263250, 1.832347",\ + "0.588511, 0.816313, 1.000457, 1.294918, 1.864016",\ + "0.878767, 1.106569, 1.290713, 1.585174, 2.154272",\ + "1.472749, 1.700552, 1.884695, 2.179157, 2.748254",\ + "0.625940, 0.852732, 1.036838, 1.331324, 1.900469",\ + "0.645171, 0.871963, 1.056069, 1.350555, 1.919701",\ + "0.676839, 0.903631, 1.087738, 1.382223, 1.951369",\ + "0.967095, 1.193887, 1.377994, 1.672480, 2.241625",\ + "1.561078, 1.787870, 1.971976, 2.266462, 2.835608",\ + "0.715049, 0.933065, 1.116865, 1.411352, 1.980501",\ + "0.734280, 0.952296, 1.136096, 1.430584, 1.999732",\ + "0.765948, 0.983964, 1.167764, 1.462252, 2.031401",\ + "1.056204, 1.274220, 1.458020, 1.752508, 2.321657",\ + "1.650187, 1.868203, 2.052003, 2.346490, 2.915639",\ + "0.778454, 0.990889, 1.174573, 1.468792, 2.037537",\ + "0.797686, 1.010120, 1.193804, 1.488024, 2.056769",\ + "0.829354, 1.041789, 1.225472, 1.519692, 2.088437",\ + "1.119610, 1.332045, 1.515728, 1.809948, 2.378693",\ + "1.713592, 1.926027, 2.109711, 2.403930, 2.972675",\ + "1.113336, 1.296163, 1.478231, 1.771973, 2.339783",\ + "1.132567, 1.315395, 1.497462, 1.791204, 2.359015",\ + "1.164236, 1.347063, 1.529130, 1.822872, 2.390683",\ + "1.454492, 1.637319, 1.819386, 2.113128, 2.680939",\ + "2.048474, 2.231302, 2.413369, 2.707111, 3.274921"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011"); + values ( "0.112216, 0.112216, 0.112216, 0.112216, 0.112216",\ + "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\ + "0.189998, 0.189998, 0.189998, 0.189998, 0.189998",\ + "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\ + "2.194229, 2.194229, 2.194229, 2.194229, 2.194229",\ + "0.112216, 0.112216, 0.112216, 0.112216, 0.112216",\ + "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\ + "0.189998, 0.189998, 0.189998, 0.189998, 0.189998",\ + "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\ + "2.194229, 2.194229, 2.194229, 2.194229, 2.194229",\ + "0.112216, 0.112216, 0.112216, 0.112216, 0.112216",\ + "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\ + "0.189998, 0.189998, 0.189998, 0.189998, 0.189998",\ + "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\ + "2.194229, 2.194229, 2.194229, 2.194229, 2.194229",\ + "0.112216, 0.112216, 0.112216, 0.112216, 0.112216",\ + "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\ + "0.189998, 0.189998, 0.189998, 0.189998, 0.189998",\ + "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\ + "2.194229, 2.194229, 2.194229, 2.194229, 2.194229",\ + "0.112216, 0.112216, 0.112216, 0.112216, 0.112216",\ + "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\ + "0.189998, 0.189998, 0.189998, 0.189998, 0.189998",\ + "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\ + "2.194229, 2.194229, 2.194229, 2.194229, 2.194229"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011"); + values ( "0.549385, 0.777187, 0.961331, 1.255792, 1.824890",\ + "0.557187, 0.784990, 0.969133, 1.263595, 1.832692",\ + "0.570583, 0.798386, 0.982529, 1.276991, 1.846088",\ + "0.722798, 0.950600, 1.134744, 1.429206, 1.998303",\ + "1.056432, 1.284234, 1.468378, 1.762839, 2.331937",\ + "0.637713, 0.864505, 1.048611, 1.343097, 1.912243",\ + "0.645516, 0.872308, 1.056414, 1.350900, 1.920045",\ + "0.658912, 0.885704, 1.069810, 1.364296, 1.933442",\ + "0.811127, 1.037919, 1.222025, 1.516511, 2.085656",\ + "1.144760, 1.371552, 1.555659, 1.850145, 2.419290",\ + "0.726822, 0.944838, 1.128638, 1.423126, 1.992275",\ + "0.734625, 0.952641, 1.136441, 1.430928, 2.000077",\ + "0.748021, 0.966037, 1.149837, 1.444324, 2.013473",\ + "0.900236, 1.118252, 1.302052, 1.596539, 2.165688",\ + "1.233869, 1.451885, 1.635685, 1.930173, 2.499322",\ + "0.790228, 1.002663, 1.186347, 1.480566, 2.049311",\ + "0.798030, 1.010465, 1.194149, 1.488369, 2.057113",\ + "0.811427, 1.023861, 1.207545, 1.501765, 2.070509",\ + "0.963641, 1.176076, 1.359760, 1.653979, 2.222724",\ + "1.297275, 1.509710, 1.693393, 1.987613, 2.556358",\ + "1.125110, 1.307937, 1.490004, 1.783746, 2.351557",\ + "1.132912, 1.315740, 1.497807, 1.791549, 2.359360",\ + "1.146308, 1.329136, 1.511203, 1.804945, 2.372756",\ + "1.298523, 1.481350, 1.663418, 1.957160, 2.524971",\ + "1.632157, 1.814984, 1.997051, 2.290793, 2.858604"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011"); + values ( "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\ + "0.055490, 0.055490, 0.055490, 0.055490, 0.055490",\ + "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\ + "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\ + "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\ + "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\ + "0.055490, 0.055490, 0.055490, 0.055490, 0.055490",\ + "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\ + "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\ + "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\ + "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\ + "0.055490, 0.055490, 0.055490, 0.055490, 0.055490",\ + "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\ + "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\ + "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\ + "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\ + "0.055490, 0.055490, 0.055490, 0.055490, 0.055490",\ + "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\ + "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\ + "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\ + "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\ + "0.055490, 0.055490, 0.055490, 0.055490, 0.055490",\ + "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\ + "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\ + "1.002321, 1.002321, 1.002321, 1.002321, 1.002321"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_min_2347*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[40]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.452626, 0.644345, 0.833940, 1.131261, 1.702487",\ + "0.471843, 0.663562, 0.853157, 1.150478, 1.721704",\ + "0.503492, 0.695211, 0.884806, 1.182126, 1.753352",\ + "0.794073, 0.985792, 1.175388, 1.472708, 2.043935",\ + "1.388076, 1.579795, 1.769390, 2.066711, 2.637938",\ + "0.540843, 0.731664, 0.921221, 1.218566, 1.789840",\ + "0.560059, 0.750880, 0.940438, 1.237783, 1.809057",\ + "0.591708, 0.782529, 0.972087, 1.269431, 1.840706",\ + "0.882290, 1.073111, 1.262668, 1.560013, 2.131288",\ + "1.476292, 1.667113, 1.856671, 2.154016, 2.725291",\ + "0.629383, 0.811999, 1.001248, 1.298594, 1.869872",\ + "0.648600, 0.831216, 1.020465, 1.317811, 1.889089",\ + "0.680249, 0.862864, 1.052114, 1.349460, 1.920737",\ + "0.970830, 1.153446, 1.342695, 1.640042, 2.211320",\ + "1.564833, 1.747448, 1.936698, 2.234045, 2.805323",\ + "0.690888, 0.869827, 1.058969, 1.356037, 1.926912",\ + "0.710105, 0.889043, 1.078185, 1.375254, 1.946129",\ + "0.741754, 0.920692, 1.109834, 1.406902, 1.977778",\ + "1.032335, 1.211274, 1.400416, 1.697484, 2.268360",\ + "1.626338, 1.805276, 1.994418, 2.291487, 2.862363",\ + "0.993056, 1.175134, 1.362629, 1.659220, 2.229164",\ + "1.012272, 1.194351, 1.381846, 1.678436, 2.248380",\ + "1.043921, 1.226000, 1.413495, 1.710085, 2.280029",\ + "1.334502, 1.516581, 1.704077, 2.000667, 2.570611",\ + "1.928505, 2.110584, 2.298079, 2.594670, 3.164614"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.115198, 0.115198, 0.115199, 0.115202, 0.115208",\ + "0.141976, 0.141976, 0.141976, 0.141975, 0.141974",\ + "0.190577, 0.190577, 0.190577, 0.190577, 0.190576",\ + "0.817535, 0.817535, 0.817535, 0.817535, 0.817534",\ + "2.193373, 2.193373, 2.193373, 2.193372, 2.193370",\ + "0.115198, 0.115198, 0.115199, 0.115202, 0.115208",\ + "0.141976, 0.141976, 0.141976, 0.141975, 0.141974",\ + "0.190577, 0.190577, 0.190577, 0.190577, 0.190576",\ + "0.817535, 0.817535, 0.817535, 0.817535, 0.817534",\ + "2.193373, 2.193373, 2.193373, 2.193372, 2.193370",\ + "0.115198, 0.115198, 0.115199, 0.115202, 0.115208",\ + "0.141976, 0.141976, 0.141976, 0.141975, 0.141974",\ + "0.190577, 0.190577, 0.190577, 0.190577, 0.190576",\ + "0.817535, 0.817535, 0.817535, 0.817535, 0.817534",\ + "2.193373, 2.193373, 2.193373, 2.193372, 2.193370",\ + "0.115198, 0.115198, 0.115199, 0.115202, 0.115208",\ + "0.141976, 0.141976, 0.141976, 0.141975, 0.141974",\ + "0.190577, 0.190577, 0.190577, 0.190577, 0.190576",\ + "0.817535, 0.817535, 0.817535, 0.817535, 0.817534",\ + "2.193373, 2.193373, 2.193373, 2.193372, 2.193370",\ + "0.115198, 0.115198, 0.115199, 0.115202, 0.115208",\ + "0.141976, 0.141976, 0.141976, 0.141975, 0.141974",\ + "0.190577, 0.190577, 0.190577, 0.190577, 0.190576",\ + "0.817535, 0.817535, 0.817535, 0.817535, 0.817534",\ + "2.193373, 2.193373, 2.193373, 2.193372, 2.193370"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.465025, 0.656744, 0.846340, 1.143661, 1.714888",\ + "0.472832, 0.664551, 0.854146, 1.151467, 1.722695",\ + "0.486213, 0.677933, 0.867528, 1.164849, 1.736077",\ + "0.638165, 0.829885, 1.019480, 1.316801, 1.888028",\ + "0.971605, 1.163324, 1.352919, 1.650240, 2.221466",\ + "0.553242, 0.744063, 0.933621, 1.230966, 1.802242",\ + "0.561048, 0.751869, 0.941427, 1.238772, 1.810048",\ + "0.574430, 0.765251, 0.954809, 1.252154, 1.823430",\ + "0.726382, 0.917203, 1.106761, 1.404106, 1.975381",\ + "1.059821, 1.250642, 1.440200, 1.737545, 2.308820",\ + "0.641782, 0.824398, 1.013648, 1.310994, 1.882273",\ + "0.649589, 0.832204, 1.021454, 1.318801, 1.890080",\ + "0.662971, 0.845586, 1.034836, 1.332183, 1.903462",\ + "0.814923, 0.997538, 1.186788, 1.484134, 2.055413",\ + "1.148362, 1.330977, 1.520227, 1.817573, 2.388851",\ + "0.703287, 0.882226, 1.071368, 1.368437, 1.939313",\ + "0.711094, 0.890032, 1.079175, 1.376243, 1.947120",\ + "0.724476, 0.903414, 1.092556, 1.389625, 1.960502",\ + "0.876427, 1.055366, 1.244508, 1.541577, 2.112453",\ + "1.209867, 1.388805, 1.577947, 1.875016, 2.445891",\ + "1.005455, 1.187533, 1.375029, 1.671620, 2.241565",\ + "1.013261, 1.195340, 1.382835, 1.679426, 2.249371",\ + "1.026643, 1.208722, 1.396217, 1.692808, 2.262753",\ + "1.178595, 1.360674, 1.548169, 1.844760, 2.414704",\ + "1.512034, 1.694113, 1.881608, 2.178198, 2.748142"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.049719, 0.049719, 0.049719, 0.049719, 0.049720",\ + "0.055444, 0.055444, 0.055444, 0.055444, 0.055444",\ + "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\ + "0.368591, 0.368591, 0.368591, 0.368591, 0.368591",\ + "1.002263, 1.002263, 1.002263, 1.002263, 1.002263",\ + "0.049719, 0.049719, 0.049719, 0.049719, 0.049720",\ + "0.055444, 0.055444, 0.055444, 0.055444, 0.055444",\ + "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\ + "0.368591, 0.368591, 0.368591, 0.368591, 0.368591",\ + "1.002263, 1.002263, 1.002263, 1.002263, 1.002263",\ + "0.049719, 0.049719, 0.049719, 0.049719, 0.049720",\ + "0.055444, 0.055444, 0.055444, 0.055444, 0.055444",\ + "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\ + "0.368591, 0.368591, 0.368591, 0.368591, 0.368591",\ + "1.002263, 1.002263, 1.002263, 1.002263, 1.002263",\ + "0.049719, 0.049719, 0.049719, 0.049719, 0.049720",\ + "0.055444, 0.055444, 0.055444, 0.055444, 0.055444",\ + "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\ + "0.368591, 0.368591, 0.368591, 0.368591, 0.368591",\ + "1.002263, 1.002263, 1.002263, 1.002263, 1.002263",\ + "0.049719, 0.049719, 0.049719, 0.049719, 0.049720",\ + "0.055444, 0.055444, 0.055444, 0.055444, 0.055444",\ + "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\ + "0.368591, 0.368591, 0.368591, 0.368591, 0.368591",\ + "1.002263, 1.002263, 1.002263, 1.002263, 1.002263"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_min_2394*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[42]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.181258, 0.362750, 0.559584, 0.877059, 1.491654",\ + "0.196091, 0.377154, 0.575199, 0.895881, 1.517263",\ + "0.221299, 0.401436, 0.600771, 0.925894, 1.556997",\ + "0.494050, 0.669272, 0.865120, 1.207435, 1.883536",\ + "1.086888, 1.260498, 1.453339, 1.802428, 2.497703",\ + "0.268666, 0.450068, 0.646865, 0.964364, 1.579007",\ + "0.283499, 0.464472, 0.662480, 0.983186, 1.604617",\ + "0.308707, 0.488754, 0.688052, 1.013199, 1.644350",\ + "0.581459, 0.756590, 0.952401, 1.294740, 1.970890",\ + "1.174296, 1.347816, 1.540620, 1.889733, 2.585056",\ + "0.349534, 0.530400, 0.726892, 1.044393, 1.659039",\ + "0.364365, 0.544804, 0.742507, 1.063215, 1.684648",\ + "0.389566, 0.569086, 0.768079, 1.093227, 1.724382",\ + "0.662286, 0.836922, 1.032428, 1.374768, 2.050921",\ + "1.255114, 1.428148, 1.620646, 1.969761, 2.665088",\ + "0.407230, 0.588238, 0.784630, 1.101888, 1.716185",\ + "0.422055, 0.602641, 0.800248, 1.120718, 1.741811",\ + "0.447245, 0.626919, 0.825823, 1.150743, 1.781568",\ + "0.719903, 0.894737, 1.090165, 1.432339, 2.108216",\ + "1.312710, 1.485957, 1.678376, 2.027355, 2.722429",\ + "0.710204, 0.893608, 1.088293, 1.405116, 2.018565",\ + "0.724980, 0.907999, 1.103911, 1.423953, 2.044210",\ + "0.750065, 0.932253, 1.129487, 1.453987, 2.083996",\ + "1.022164, 1.199940, 1.393827, 1.735630, 2.410775",\ + "1.614788, 1.791118, 1.982037, 2.330666, 3.025044"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.126844, 0.127605, 0.133435, 0.151631, 0.191178",\ + "0.149772, 0.150309, 0.154650, 0.170542, 0.205735",\ + "0.195024, 0.195582, 0.198470, 0.210618, 0.237900",\ + "0.816153, 0.816255, 0.816260, 0.817805, 0.821592",\ + "2.194128, 2.194405, 2.194418, 2.195894, 2.199512",\ + "0.126844, 0.127605, 0.133435, 0.151631, 0.191178",\ + "0.149772, 0.150309, 0.154650, 0.170542, 0.205735",\ + "0.195024, 0.195582, 0.198470, 0.210618, 0.237900",\ + "0.816153, 0.816255, 0.816260, 0.817805, 0.821592",\ + "2.194128, 2.194405, 2.194418, 2.195894, 2.199512",\ + "0.126849, 0.127605, 0.133435, 0.151631, 0.191178",\ + "0.149775, 0.150309, 0.154650, 0.170542, 0.205735",\ + "0.195028, 0.195582, 0.198470, 0.210618, 0.237900",\ + "0.816153, 0.816255, 0.816260, 0.817805, 0.821592",\ + "2.194129, 2.194405, 2.194418, 2.195894, 2.199512",\ + "0.126859, 0.127607, 0.133449, 0.151680, 0.191274",\ + "0.149782, 0.150311, 0.154660, 0.170585, 0.205820",\ + "0.195035, 0.195584, 0.198477, 0.210651, 0.237965",\ + "0.816155, 0.816256, 0.816260, 0.817810, 0.821601",\ + "2.194133, 2.194406, 2.194418, 2.195898, 2.199521",\ + "0.126945, 0.127627, 0.133451, 0.151721, 0.191389",\ + "0.149843, 0.150326, 0.154662, 0.170622, 0.205922",\ + "0.195098, 0.195599, 0.198478, 0.210679, 0.238045",\ + "0.816166, 0.816259, 0.816260, 0.817813, 0.821612",\ + "2.194165, 2.194413, 2.194418, 2.195902, 2.199532"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.117102, 0.379947, 0.573156, 0.882174, 1.479232",\ + "0.126091, 0.389068, 0.582472, 0.892519, 1.491929",\ + "0.141699, 0.404157, 0.597820, 0.909153, 1.511489",\ + "0.306945, 0.562483, 0.755606, 1.068523, 1.675209",\ + "0.649757, 0.897030, 1.089718, 1.401787, 2.006775",\ + "0.205481, 0.467265, 0.660437, 0.969479, 1.566586",\ + "0.214473, 0.476386, 0.669753, 0.979824, 1.579283",\ + "0.230076, 0.491475, 0.685100, 0.996458, 1.598842",\ + "0.395245, 0.649801, 0.842887, 1.155828, 1.762562",\ + "0.738017, 0.984348, 1.176999, 1.489092, 2.094129",\ + "0.294834, 0.547598, 0.740463, 1.049507, 1.646617",\ + "0.303840, 0.556719, 0.749780, 1.059852, 1.659314",\ + "0.319425, 0.571807, 0.765127, 1.076486, 1.678874",\ + "0.484368, 0.730134, 0.922914, 1.235856, 1.842594",\ + "0.827025, 1.064680, 1.257025, 1.569121, 2.174160",\ + "0.358511, 0.605438, 0.798193, 1.106982, 1.703722",\ + "0.367529, 0.614560, 0.807510, 1.117329, 1.716424",\ + "0.383098, 0.629648, 0.822858, 1.133967, 1.735991",\ + "0.547830, 0.787974, 0.980643, 1.293342, 1.899721",\ + "0.890379, 1.122520, 1.314754, 1.626604, 2.231284",\ + "0.695115, 0.910825, 1.101854, 1.410191, 2.006050",\ + "0.704209, 0.919948, 1.111171, 1.420541, 2.018759",\ + "0.719674, 0.935035, 1.126519, 1.437182, 2.038335",\ + "0.883062, 1.093358, 1.284304, 1.596561, 2.202077",\ + "1.224926, 1.427904, 1.618415, 1.929822, 2.533635"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.044794, 0.049393, 0.054601, 0.068665, 0.098782",\ + "0.053408, 0.055750, 0.059102, 0.072238, 0.101610",\ + "0.075784, 0.075784, 0.077996, 0.088605, 0.112682",\ + "0.368045, 0.368045, 0.368833, 0.370655, 0.374434",\ + "1.001402, 1.001402, 1.001776, 1.002637, 1.004422",\ + "0.044917, 0.049393, 0.054601, 0.068665, 0.098782",\ + "0.053471, 0.055750, 0.059102, 0.072238, 0.101610",\ + "0.075784, 0.075784, 0.077996, 0.088605, 0.112682",\ + "0.368045, 0.368045, 0.368833, 0.370655, 0.374434",\ + "1.001402, 1.001402, 1.001776, 1.002637, 1.004422",\ + "0.045280, 0.049393, 0.054601, 0.068665, 0.098782",\ + "0.053656, 0.055750, 0.059102, 0.072238, 0.101610",\ + "0.075784, 0.075784, 0.077996, 0.088605, 0.112682",\ + "0.368045, 0.368045, 0.368833, 0.370655, 0.374434",\ + "1.001402, 1.001402, 1.001776, 1.002637, 1.004422",\ + "0.045619, 0.049410, 0.054613, 0.068702, 0.098855",\ + "0.053828, 0.055759, 0.059110, 0.072274, 0.101681",\ + "0.075784, 0.075784, 0.078001, 0.088634, 0.112740",\ + "0.368045, 0.368045, 0.368835, 0.370660, 0.374443",\ + "1.001402, 1.001402, 1.001777, 1.002639, 1.004426",\ + "0.047777, 0.049532, 0.054615, 0.068733, 0.098943",\ + "0.054927, 0.055821, 0.059111, 0.072304, 0.101766",\ + "0.075784, 0.075784, 0.078002, 0.088659, 0.112810",\ + "0.368045, 0.368045, 0.368835, 0.370664, 0.374454",\ + "1.001402, 1.001402, 1.001777, 1.002641, 1.004432"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_min_2316*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[43]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011"); + values ( "0.098350, 0.258117, 0.412724, 0.663632, 1.151052",\ + "0.111306, 0.279646, 0.445289, 0.710490, 1.223646",\ + "0.138089, 0.311436, 0.490658, 0.774246, 1.320793",\ + "0.424991, 0.637508, 0.825514, 1.153509, 1.801342",\ + "1.020536, 1.249709, 1.439386, 1.764952, 2.405506",\ + "0.185759, 0.345435, 0.500005, 0.750937, 1.238405",\ + "0.198715, 0.366964, 0.532570, 0.797795, 1.310999",\ + "0.225498, 0.398754, 0.577939, 0.861551, 1.408146",\ + "0.513280, 0.724826, 0.912795, 1.240814, 1.888696",\ + "1.108868, 1.337027, 1.526667, 1.852257, 2.492859",\ + "0.266486, 0.425768, 0.580032, 0.830966, 1.318437",\ + "0.279498, 0.447297, 0.612597, 0.877824, 1.391031",\ + "0.306314, 0.479087, 0.657966, 0.941579, 1.488178",\ + "0.602279, 0.805159, 0.992822, 1.320843, 1.968727",\ + "1.197992, 1.417360, 1.606694, 1.932286, 2.572891",\ + "0.323899, 0.483524, 0.637672, 0.888307, 1.375276",\ + "0.337018, 0.505085, 0.670262, 0.935196, 1.447932",\ + "0.363897, 0.536894, 0.715662, 0.998992, 1.545160",\ + "0.665584, 0.862970, 1.050539, 1.378378, 2.025954",\ + "1.261413, 1.475185, 1.664415, 1.989812, 2.630099",\ + "0.624253, 0.788317, 0.941319, 1.191402, 1.677284",\ + "0.638351, 0.810106, 0.973913, 1.238318, 1.750015",\ + "0.665802, 0.842047, 1.019319, 1.302149, 1.847340",\ + "0.990853, 1.168154, 1.354199, 1.681640, 2.328429",\ + "1.596393, 1.780461, 1.968075, 2.293067, 2.932554"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011"); + values ( "0.028418, 0.053830, 0.061535, 0.076150, 0.106328",\ + "0.053925, 0.080459, 0.084933, 0.098494, 0.128975",\ + "0.117469, 0.123739, 0.136658, 0.151484, 0.176772",\ + "0.813025, 0.813025, 0.813025, 0.814972, 0.819748",\ + "2.191689, 2.192946, 2.194005, 2.200700, 2.216248",\ + "0.028418, 0.053830, 0.061535, 0.076150, 0.106328",\ + "0.053925, 0.080459, 0.084933, 0.098494, 0.128975",\ + "0.117469, 0.123739, 0.136658, 0.151484, 0.176772",\ + "0.813025, 0.813025, 0.813025, 0.814972, 0.819748",\ + "2.191723, 2.192946, 2.194005, 2.200700, 2.216248",\ + "0.028584, 0.053830, 0.061535, 0.076150, 0.106328",\ + "0.054098, 0.080459, 0.084933, 0.098494, 0.128975",\ + "0.117510, 0.123739, 0.136658, 0.151484, 0.176772",\ + "0.813025, 0.813025, 0.813025, 0.814972, 0.819748",\ + "2.191823, 2.192946, 2.194005, 2.200700, 2.216248",\ + "0.028905, 0.053925, 0.061551, 0.076187, 0.106401",\ + "0.054433, 0.080559, 0.084941, 0.098531, 0.129049",\ + "0.117589, 0.123763, 0.136688, 0.151514, 0.176833",\ + "0.813025, 0.813025, 0.813025, 0.814978, 0.819760",\ + "2.191915, 2.192951, 2.194008, 2.200718, 2.216285",\ + "0.031805, 0.054598, 0.061553, 0.076218, 0.106489",\ + "0.057461, 0.081261, 0.084942, 0.098563, 0.129138",\ + "0.118304, 0.123929, 0.136693, 0.151541, 0.176907",\ + "0.813025, 0.813025, 0.813025, 0.814982, 0.819773",\ + "2.192503, 2.192984, 2.194008, 2.200735, 2.216331"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011"); + values ( "0.069370, 0.283193, 0.491815, 0.800919, 1.367462",\ + "0.075632, 0.304498, 0.517002, 0.813952, 1.385072",\ + "0.088234, 0.333476, 0.530104, 0.830255, 1.407585",\ + "0.254611, 0.476253, 0.671078, 0.977854, 1.568006",\ + "0.593217, 0.801399, 0.995520, 1.304053, 1.898975",\ + "0.156902, 0.370515, 0.579033, 0.888224, 1.454816",\ + "0.163435, 0.391863, 0.604283, 0.901257, 1.472425",\ + "0.176298, 0.420901, 0.617385, 0.917560, 1.494938",\ + "0.342791, 0.563572, 0.758359, 1.065159, 1.655359",\ + "0.681370, 0.888717, 1.082801, 1.391358, 1.986328",\ + "0.243698, 0.458976, 0.666990, 0.968253, 1.534847",\ + "0.251018, 0.480422, 0.684310, 0.981285, 1.552457",\ + "0.264645, 0.506852, 0.697412, 0.997588, 1.574970",\ + "0.431471, 0.643905, 0.838386, 1.145188, 1.735391",\ + "0.769972, 0.969050, 1.162828, 1.471387, 2.066360",\ + "0.304960, 0.523854, 0.731112, 1.025689, 1.591878",\ + "0.313009, 0.545444, 0.742029, 1.038728, 1.609498",\ + "0.327344, 0.564695, 0.755135, 1.055038, 1.632026",\ + "0.494481, 0.701749, 0.896119, 1.202653, 1.792478",\ + "0.832908, 1.026881, 1.220559, 1.528858, 2.123458",\ + "0.626203, 0.851949, 1.035624, 1.328867, 1.894116",\ + "0.638895, 0.858887, 1.045689, 1.341910, 1.911750",\ + "0.657734, 0.870103, 1.058796, 1.358227, 1.934296",\ + "0.821978, 1.007166, 1.199781, 1.505856, 2.094786",\ + "1.150367, 1.332198, 1.524221, 1.832065, 2.425780"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011"); + values ( "0.013843, 0.057624, 0.075770, 0.080313, 0.107471",\ + "0.025205, 0.064739, 0.067587, 0.083073, 0.115488",\ + "0.053856, 0.083413, 0.086593, 0.102413, 0.134994",\ + "0.368605, 0.368605, 0.369807, 0.373448, 0.381327",\ + "1.000406, 1.000406, 1.002130, 1.003829, 1.006481",\ + "0.014774, 0.057698, 0.075841, 0.080313, 0.107471",\ + "0.026141, 0.064772, 0.067587, 0.083073, 0.115488",\ + "0.054523, 0.083449, 0.086593, 0.102413, 0.134994",\ + "0.368605, 0.368605, 0.369807, 0.373448, 0.381327",\ + "1.000406, 1.000406, 1.002130, 1.003829, 1.006481",\ + "0.017481, 0.057867, 0.075842, 0.080313, 0.107471",\ + "0.028863, 0.064847, 0.067587, 0.083073, 0.115488",\ + "0.056460, 0.078305, 0.086593, 0.102413, 0.134994",\ + "0.368605, 0.368605, 0.369807, 0.373448, 0.381327",\ + "1.000406, 1.000406, 1.002130, 1.003829, 1.006481",\ + "0.019992, 0.058113, 0.075846, 0.080346, 0.107536",\ + "0.031388, 0.064955, 0.067602, 0.083112, 0.115566",\ + "0.058257, 0.078397, 0.086610, 0.102452, 0.135073",\ + "0.368605, 0.368605, 0.369809, 0.373458, 0.381346",\ + "1.000406, 1.000406, 1.002134, 1.003832, 1.006488",\ + "0.035969, 0.049040, 0.064123, 0.080374, 0.107616",\ + "0.047452, 0.060595, 0.067604, 0.083146, 0.115661",\ + "0.069690, 0.079044, 0.086613, 0.102486, 0.135168",\ + "0.368605, 0.368605, 0.369810, 0.373466, 0.381369",\ + "1.000406, 1.000406, 1.002134, 1.003835, 1.006495"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_min_2285*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[45]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011"); + values ( "0.431291, 0.619330, 0.796158, 1.080125, 1.629897",\ + "0.450507, 0.638547, 0.815375, 1.099342, 1.649114",\ + "0.482156, 0.670196, 0.847024, 1.130990, 1.680763",\ + "0.772737, 0.960778, 1.137606, 1.421573, 1.971346",\ + "1.366740, 1.554780, 1.731609, 2.015576, 2.565349",\ + "0.519710, 0.706648, 0.883439, 1.167430, 1.717251",\ + "0.538927, 0.725865, 0.902656, 1.186647, 1.736468",\ + "0.570576, 0.757514, 0.934305, 1.218296, 1.768116",\ + "0.861157, 1.048096, 1.224887, 1.508878, 2.058700",\ + "1.455159, 1.642098, 1.818890, 2.102881, 2.652703",\ + "0.609345, 0.786979, 0.963466, 1.247459, 1.797282",\ + "0.628561, 0.806196, 0.982683, 1.266675, 1.816499",\ + "0.660210, 0.837845, 1.014332, 1.298324, 1.848148",\ + "0.950791, 1.128427, 1.304914, 1.588907, 2.138731",\ + "1.544794, 1.722429, 1.898916, 2.182909, 2.732734",\ + "0.668670, 0.844800, 1.021158, 1.304875, 1.854273",\ + "0.687887, 0.864017, 1.040374, 1.324092, 1.873490",\ + "0.719535, 0.895665, 1.072023, 1.355741, 1.905138",\ + "1.010116, 1.186247, 1.362605, 1.646324, 2.195722",\ + "1.604119, 1.780250, 1.956608, 2.240326, 2.789725",\ + "0.971362, 1.150042, 1.324812, 1.608036, 2.156464",\ + "0.990578, 1.169258, 1.344029, 1.627252, 2.175681",\ + "1.022227, 1.200907, 1.375677, 1.658901, 2.207329",\ + "1.312808, 1.491489, 1.666260, 1.949484, 2.497913",\ + "1.906811, 2.085492, 2.260262, 2.543486, 3.091916"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011"); + values ( "0.115194, 0.115201, 0.115205, 0.115209, 0.115217",\ + "0.141976, 0.141976, 0.141976, 0.141975, 0.141974",\ + "0.190577, 0.190577, 0.190577, 0.190577, 0.190576",\ + "0.817535, 0.817535, 0.817535, 0.817534, 0.817534",\ + "2.193374, 2.193372, 2.193371, 2.193370, 2.193367",\ + "0.115194, 0.115201, 0.115205, 0.115209, 0.115217",\ + "0.141976, 0.141976, 0.141976, 0.141975, 0.141974",\ + "0.190577, 0.190577, 0.190577, 0.190577, 0.190576",\ + "0.817535, 0.817535, 0.817535, 0.817534, 0.817534",\ + "2.193374, 2.193372, 2.193371, 2.193370, 2.193367",\ + "0.115194, 0.115201, 0.115205, 0.115209, 0.115217",\ + "0.141976, 0.141976, 0.141976, 0.141975, 0.141974",\ + "0.190577, 0.190577, 0.190577, 0.190577, 0.190576",\ + "0.817535, 0.817535, 0.817535, 0.817534, 0.817534",\ + "2.193374, 2.193372, 2.193371, 2.193370, 2.193367",\ + "0.115194, 0.115201, 0.115205, 0.115209, 0.115217",\ + "0.141976, 0.141976, 0.141976, 0.141975, 0.141974",\ + "0.190577, 0.190577, 0.190577, 0.190577, 0.190576",\ + "0.817535, 0.817535, 0.817535, 0.817534, 0.817534",\ + "2.193374, 2.193372, 2.193371, 2.193370, 2.193367",\ + "0.115195, 0.115202, 0.115205, 0.115209, 0.115217",\ + "0.141976, 0.141976, 0.141976, 0.141975, 0.141974",\ + "0.190577, 0.190577, 0.190577, 0.190577, 0.190576",\ + "0.817535, 0.817535, 0.817535, 0.817534, 0.817534",\ + "2.193374, 2.193372, 2.193371, 2.193370, 2.193367"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011"); + values ( "0.443689, 0.631730, 0.808559, 1.092526, 1.642300",\ + "0.451495, 0.639537, 0.816365, 1.100333, 1.650107",\ + "0.464877, 0.652918, 0.829747, 1.113715, 1.663489",\ + "0.616830, 0.804870, 0.981699, 1.265666, 1.815439",\ + "0.950269, 1.138309, 1.315137, 1.599104, 2.148877",\ + "0.532108, 0.719048, 0.895840, 1.179832, 1.729654",\ + "0.539915, 0.726855, 0.903646, 1.187638, 1.737461",\ + "0.553297, 0.740236, 0.917028, 1.201020, 1.750842",\ + "0.705249, 0.892188, 1.068980, 1.352971, 1.902793",\ + "1.038688, 1.225627, 1.402418, 1.686409, 2.236230",\ + "0.621743, 0.799379, 0.975867, 1.259860, 1.809685",\ + "0.629550, 0.807186, 0.983673, 1.267667, 1.817492",\ + "0.642931, 0.820567, 0.997055, 1.281049, 1.830874",\ + "0.794884, 0.972519, 1.149006, 1.432999, 1.982824",\ + "1.128323, 1.305958, 1.482445, 1.766438, 2.316262",\ + "0.681068, 0.857200, 1.033558, 1.317277, 1.866676",\ + "0.688875, 0.865006, 1.041365, 1.325083, 1.874483",\ + "0.702257, 0.878388, 1.054746, 1.338465, 1.887864",\ + "0.854209, 1.030340, 1.206698, 1.490416, 2.039815",\ + "1.187648, 1.363779, 1.540136, 1.823854, 2.373252",\ + "0.983760, 1.162441, 1.337212, 1.620437, 2.168867",\ + "0.991567, 1.170248, 1.345019, 1.628244, 2.176674",\ + "1.004948, 1.183630, 1.358401, 1.641625, 2.190056",\ + "1.156901, 1.335582, 1.510352, 1.793576, 2.342006",\ + "1.490340, 1.669020, 1.843791, 2.127015, 2.675444"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011"); + values ( "0.049719, 0.049719, 0.049720, 0.049720, 0.049720",\ + "0.055444, 0.055444, 0.055444, 0.055444, 0.055444",\ + "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\ + "0.368591, 0.368591, 0.368591, 0.368591, 0.368591",\ + "1.002263, 1.002263, 1.002263, 1.002263, 1.002263",\ + "0.049719, 0.049719, 0.049720, 0.049720, 0.049720",\ + "0.055444, 0.055444, 0.055444, 0.055444, 0.055444",\ + "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\ + "0.368591, 0.368591, 0.368591, 0.368591, 0.368591",\ + "1.002263, 1.002263, 1.002263, 1.002263, 1.002263",\ + "0.049719, 0.049719, 0.049720, 0.049720, 0.049720",\ + "0.055444, 0.055444, 0.055444, 0.055444, 0.055444",\ + "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\ + "0.368591, 0.368591, 0.368591, 0.368591, 0.368591",\ + "1.002263, 1.002263, 1.002263, 1.002263, 1.002263",\ + "0.049719, 0.049719, 0.049720, 0.049720, 0.049720",\ + "0.055444, 0.055444, 0.055444, 0.055444, 0.055444",\ + "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\ + "0.368591, 0.368591, 0.368591, 0.368591, 0.368591",\ + "1.002263, 1.002263, 1.002263, 1.002263, 1.002263",\ + "0.049719, 0.049719, 0.049720, 0.049720, 0.049720",\ + "0.055444, 0.055444, 0.055444, 0.055444, 0.055444",\ + "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\ + "0.368591, 0.368591, 0.368591, 0.368591, 0.368591",\ + "1.002263, 1.002263, 1.002263, 1.002263, 1.002263"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_min_2529*/ + +} /* end of pin tl_o[7] */ + +pin("tl_o[6]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.154883 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : tl_o[6]; + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[16]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011"); + values ( "0.555603, 0.806076, 1.084885, 1.584808, 2.584653",\ + "0.589996, 0.840470, 1.119283, 1.619221, 2.619098",\ + "0.661233, 0.911707, 1.190508, 1.690407, 2.690205",\ + "0.915400, 1.165873, 1.444750, 1.944912, 2.945236",\ + "1.840005, 2.090481, 2.369305, 2.869275, 3.869217",\ + "0.643016, 0.893581, 1.172550, 1.671522, 2.670587",\ + "0.677409, 0.927975, 1.206949, 1.705936, 2.705032",\ + "0.748646, 0.999212, 1.278174, 1.777122, 2.776139",\ + "1.002812, 1.253378, 1.532416, 2.031627, 3.031170",\ + "1.927417, 2.177986, 2.456970, 2.955990, 3.955151",\ + "0.723872, 0.982469, 1.260517, 1.759145, 2.757542",\ + "0.758265, 1.016862, 1.294915, 1.793559, 2.791987",\ + "0.829503, 1.088099, 1.366140, 1.864744, 2.863094",\ + "1.083669, 1.342266, 1.620383, 2.119249, 3.118125",\ + "2.008274, 2.266873, 2.544936, 3.043612, 4.042106",\ + "0.781752, 1.047969, 1.324661, 1.823058, 2.821051",\ + "0.816145, 1.082362, 1.359060, 1.857472, 2.855496",\ + "0.887382, 1.153599, 1.430285, 1.928658, 2.926603",\ + "1.141549, 1.407765, 1.684527, 2.183163, 3.181634",\ + "2.066154, 2.332373, 2.609081, 3.107526, 4.105615",\ + "1.114573, 1.410746, 1.676844, 2.172535, 3.166507",\ + "1.148966, 1.445139, 1.711242, 2.206949, 3.200952",\ + "1.220203, 1.516376, 1.782467, 2.278135, 3.272059",\ + "1.474370, 1.770542, 2.036712, 2.532641, 3.527090",\ + "2.398975, 2.695150, 2.961264, 3.457003, 4.451071"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011"); + values ( "0.034112, 0.034113, 0.034114, 0.034119, 0.034130",\ + "0.083750, 0.083751, 0.083761, 0.083790, 0.083849",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692761, 0.692766, 0.692810, 0.692941, 0.693203",\ + "2.465173, 2.465199, 2.466091, 2.469060, 2.474999",\ + "0.034112, 0.034113, 0.034114, 0.034119, 0.034130",\ + "0.083750, 0.083751, 0.083761, 0.083790, 0.083849",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692761, 0.692766, 0.692810, 0.692941, 0.693203",\ + "2.465173, 2.465199, 2.466100, 2.469060, 2.474999",\ + "0.034112, 0.034113, 0.034114, 0.034119, 0.034130",\ + "0.083750, 0.083751, 0.083761, 0.083790, 0.083849",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692761, 0.692766, 0.692810, 0.692941, 0.693203",\ + "2.465173, 2.465199, 2.466100, 2.469060, 2.474999",\ + "0.034112, 0.034113, 0.034114, 0.034119, 0.034130",\ + "0.083750, 0.083751, 0.083761, 0.083790, 0.083849",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692761, 0.692766, 0.692810, 0.692941, 0.693203",\ + "2.465173, 2.465200, 2.466101, 2.469060, 2.474999",\ + "0.034112, 0.034113, 0.034114, 0.034119, 0.034130",\ + "0.083751, 0.083752, 0.083761, 0.083790, 0.083849",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692761, 0.692768, 0.692812, 0.692941, 0.693203",\ + "2.465173, 2.465210, 2.466131, 2.469072, 2.474999"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011"); + values ( "0.587400, 0.837877, 1.116297, 1.614862, 2.611990",\ + "0.629152, 0.879628, 1.158099, 1.656840, 2.654322",\ + "0.689082, 0.939558, 1.218080, 1.716996, 2.714829",\ + "0.857199, 1.107675, 1.386266, 1.885427, 2.883749",\ + "1.439229, 1.689714, 1.968424, 2.467974, 3.467073",\ + "0.674813, 0.925382, 1.203958, 1.701576, 2.697924",\ + "0.716564, 0.967133, 1.245761, 1.743555, 2.740255",\ + "0.776495, 1.027063, 1.305742, 1.803711, 2.800763",\ + "0.944611, 1.195180, 1.473930, 1.972142, 2.969683",\ + "1.526642, 1.777219, 2.056088, 2.554689, 3.553007",\ + "0.755670, 1.014269, 1.291924, 1.789199, 2.784879",\ + "0.797421, 1.056020, 1.333727, 1.831177, 2.827210",\ + "0.857352, 1.115951, 1.393708, 1.891333, 2.887718",\ + "1.025468, 1.284067, 1.561896, 2.059765, 3.056638",\ + "1.607499, 1.866107, 2.144055, 2.642311, 3.639962",\ + "0.813550, 1.079769, 1.356069, 1.853112, 2.848388",\ + "0.855301, 1.121520, 1.397871, 1.895091, 2.890719",\ + "0.915231, 1.181451, 1.457853, 1.955247, 2.951227",\ + "1.083348, 1.349567, 1.626040, 2.123678, 3.120147",\ + "1.665379, 1.931606, 2.208199, 2.706225, 3.703471",\ + "1.146371, 1.442547, 1.708238, 2.202584, 3.193844",\ + "1.188122, 1.484298, 1.750042, 2.244563, 3.236176",\ + "1.248053, 1.544228, 1.810025, 2.304720, 3.296683",\ + "1.416169, 1.712345, 1.978215, 2.473152, 3.465603",\ + "1.998202, 2.294386, 2.560378, 3.055700, 4.048927"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011"); + values ( "0.045876, 0.045875, 0.045861, 0.045821, 0.045741",\ + "0.079914, 0.079913, 0.079913, 0.079910, 0.079906",\ + "0.155804, 0.155803, 0.155792, 0.155761, 0.155698",\ + "0.431307, 0.431307, 0.431304, 0.431297, 0.431282",\ + "1.494119, 1.494120, 1.494128, 1.494150, 1.494195",\ + "0.045876, 0.045875, 0.045861, 0.045821, 0.045741",\ + "0.079914, 0.079913, 0.079913, 0.079910, 0.079906",\ + "0.155804, 0.155803, 0.155792, 0.155761, 0.155698",\ + "0.431307, 0.431307, 0.431304, 0.431297, 0.431282",\ + "1.494119, 1.494120, 1.494128, 1.494150, 1.494195",\ + "0.045876, 0.045875, 0.045861, 0.045821, 0.045741",\ + "0.079914, 0.079913, 0.079913, 0.079910, 0.079906",\ + "0.155804, 0.155803, 0.155792, 0.155761, 0.155698",\ + "0.431307, 0.431307, 0.431304, 0.431297, 0.431282",\ + "1.494119, 1.494120, 1.494128, 1.494150, 1.494195",\ + "0.045876, 0.045875, 0.045861, 0.045821, 0.045741",\ + "0.079914, 0.079913, 0.079913, 0.079910, 0.079906",\ + "0.155804, 0.155803, 0.155792, 0.155761, 0.155698",\ + "0.431307, 0.431307, 0.431304, 0.431297, 0.431282",\ + "1.494119, 1.494120, 1.494128, 1.494150, 1.494195",\ + "0.045876, 0.045874, 0.045861, 0.045821, 0.045741",\ + "0.079914, 0.079913, 0.079913, 0.079910, 0.079906",\ + "0.155804, 0.155802, 0.155792, 0.155761, 0.155698",\ + "0.431307, 0.431307, 0.431304, 0.431297, 0.431282",\ + "1.494119, 1.494120, 1.494128, 1.494150, 1.494195"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_2615*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[17]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011"); + values ( "0.674108, 0.912583, 1.208888, 1.707377, 2.704357",\ + "0.708540, 0.947015, 1.243320, 1.741811, 2.738792",\ + "0.779534, 1.018009, 1.314315, 1.812807, 2.809791",\ + "1.033699, 1.272174, 1.568481, 2.066974, 3.063961",\ + "1.958883, 2.197359, 2.493670, 2.992175, 3.989184",\ + "0.761549, 1.000192, 1.296551, 1.794093, 2.790291",\ + "0.795981, 1.034624, 1.330983, 1.828526, 2.824726",\ + "0.866976, 1.105618, 1.401978, 1.899523, 2.895725",\ + "1.121141, 1.359783, 1.656144, 2.153690, 3.149894",\ + "2.046324, 2.284967, 2.581333, 3.078891, 4.075118",\ + "0.842432, 1.089339, 1.384517, 1.881716, 2.877246",\ + "0.876864, 1.123771, 1.418950, 1.916149, 2.911681",\ + "0.947859, 1.194765, 1.489945, 1.987146, 2.982680",\ + "1.202024, 1.448930, 1.744111, 2.241313, 3.236850",\ + "2.127208, 2.374115, 2.669300, 3.166513, 4.162073",\ + "0.900159, 1.155216, 1.448662, 1.945630, 2.940755",\ + "0.934591, 1.189648, 1.483094, 1.980063, 2.975190",\ + "1.005585, 1.260643, 1.554090, 2.051059, 3.046189",\ + "1.259750, 1.514808, 1.808255, 2.305226, 3.300359",\ + "2.184934, 2.439992, 2.733444, 3.230427, 4.225582",\ + "1.202901, 1.522357, 1.800832, 2.295105, 3.286211",\ + "1.237333, 1.556789, 1.835264, 2.329538, 3.320646",\ + "1.308327, 1.627784, 1.906260, 2.400534, 3.391645",\ + "1.562492, 1.881949, 2.160425, 2.654701, 3.645814",\ + "2.487676, 2.807133, 3.085615, 3.579902, 4.571038"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011"); + values ( "0.034241, 0.034241, 0.034241, 0.034244, 0.034249",\ + "0.083584, 0.083584, 0.083586, 0.083591, 0.083602",\ + "0.208067, 0.208067, 0.208069, 0.208073, 0.208081",\ + "0.693279, 0.693282, 0.693285, 0.693285, 0.693285",\ + "2.470759, 2.470761, 2.470771, 2.470795, 2.470844",\ + "0.034241, 0.034241, 0.034241, 0.034244, 0.034249",\ + "0.083584, 0.083584, 0.083586, 0.083591, 0.083602",\ + "0.208067, 0.208067, 0.208069, 0.208073, 0.208081",\ + "0.693279, 0.693282, 0.693285, 0.693285, 0.693285",\ + "2.470759, 2.470761, 2.470771, 2.470795, 2.470844",\ + "0.034241, 0.034241, 0.034241, 0.034244, 0.034249",\ + "0.083584, 0.083584, 0.083586, 0.083591, 0.083602",\ + "0.208067, 0.208067, 0.208069, 0.208073, 0.208081",\ + "0.693279, 0.693282, 0.693285, 0.693285, 0.693285",\ + "2.470759, 2.470761, 2.470771, 2.470795, 2.470844",\ + "0.034241, 0.034241, 0.034241, 0.034244, 0.034249",\ + "0.083584, 0.083584, 0.083586, 0.083591, 0.083602",\ + "0.208067, 0.208067, 0.208069, 0.208073, 0.208081",\ + "0.693279, 0.693282, 0.693285, 0.693285, 0.693285",\ + "2.470759, 2.470761, 2.470771, 2.470795, 2.470844",\ + "0.034241, 0.034241, 0.034241, 0.034244, 0.034249",\ + "0.083584, 0.083584, 0.083586, 0.083591, 0.083602",\ + "0.208067, 0.208067, 0.208069, 0.208073, 0.208081",\ + "0.693279, 0.693283, 0.693285, 0.693285, 0.693285",\ + "2.470759, 2.470762, 2.470771, 2.470795, 2.470844"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011"); + values ( "0.701144, 0.939619, 1.235924, 1.734413, 2.731392",\ + "0.743441, 0.981916, 1.278220, 1.776710, 2.773689",\ + "0.804003, 1.042478, 1.338783, 1.837273, 2.834251",\ + "0.972934, 1.211409, 1.507714, 2.006203, 3.003182",\ + "1.556185, 1.794660, 2.090965, 2.589454, 3.586433",\ + "0.788586, 1.027228, 1.323587, 1.821129, 2.817326",\ + "0.830882, 1.069525, 1.365883, 1.863425, 2.859622",\ + "0.891445, 1.130087, 1.426446, 1.923988, 2.920185",\ + "1.060375, 1.299018, 1.595377, 2.092919, 3.089116",\ + "1.643626, 1.882269, 2.178628, 2.676170, 3.672367",\ + "0.869469, 1.116375, 1.411554, 1.908752, 2.904281",\ + "0.911765, 1.158672, 1.453850, 1.951048, 2.946578",\ + "0.972328, 1.219234, 1.514413, 2.011611, 3.007140",\ + "1.141259, 1.388165, 1.683344, 2.180542, 3.176071",\ + "1.724510, 1.971416, 2.266594, 2.763793, 3.759322",\ + "0.927195, 1.182252, 1.475698, 1.972666, 2.967790",\ + "0.969492, 1.224549, 1.517995, 2.014962, 3.010087",\ + "1.030054, 1.285111, 1.578557, 2.075525, 3.070649",\ + "1.198985, 1.454042, 1.747488, 2.244456, 3.239580",\ + "1.782236, 2.037293, 2.330739, 2.827706, 3.822831",\ + "1.229937, 1.549393, 1.827868, 2.322140, 3.313246",\ + "1.272233, 1.591690, 1.870165, 2.364437, 3.355543",\ + "1.332796, 1.652252, 1.930727, 2.424999, 3.416105",\ + "1.501727, 1.821183, 2.099658, 2.593930, 3.585036",\ + "2.084978, 2.404434, 2.682909, 3.177181, 4.168287"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011"); + values ( "0.045859, 0.045859, 0.045858, 0.045858, 0.045857",\ + "0.079962, 0.079962, 0.079962, 0.079962, 0.079962",\ + "0.155685, 0.155685, 0.155685, 0.155685, 0.155685",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498064, 1.498064, 1.498063, 1.498063, 1.498062",\ + "0.045859, 0.045859, 0.045858, 0.045858, 0.045857",\ + "0.079962, 0.079962, 0.079962, 0.079962, 0.079962",\ + "0.155685, 0.155685, 0.155685, 0.155685, 0.155685",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498064, 1.498064, 1.498063, 1.498063, 1.498062",\ + "0.045859, 0.045859, 0.045858, 0.045858, 0.045857",\ + "0.079962, 0.079962, 0.079962, 0.079962, 0.079962",\ + "0.155685, 0.155685, 0.155685, 0.155685, 0.155685",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498064, 1.498064, 1.498063, 1.498063, 1.498062",\ + "0.045859, 0.045859, 0.045858, 0.045858, 0.045857",\ + "0.079962, 0.079962, 0.079962, 0.079962, 0.079962",\ + "0.155685, 0.155685, 0.155685, 0.155685, 0.155685",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498064, 1.498064, 1.498063, 1.498063, 1.498062",\ + "0.045859, 0.045859, 0.045858, 0.045858, 0.045857",\ + "0.079962, 0.079962, 0.079962, 0.079962, 0.079962",\ + "0.155685, 0.155685, 0.155685, 0.155685, 0.155685",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498064, 1.498063, 1.498063, 1.498063, 1.498062"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_2662*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[19]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011"); + values ( "0.445529, 0.709512, 0.994214, 1.487610, 2.474404",\ + "0.486774, 0.750744, 1.035473, 1.529006, 2.516072",\ + "0.562671, 0.826637, 1.111362, 1.604919, 2.592032",\ + "0.817960, 1.082041, 1.366717, 1.860078, 2.846800",\ + "1.742890, 2.007130, 2.292228, 2.786041, 3.773666",\ + "0.532938, 0.797075, 1.081856, 1.574325, 2.560338",\ + "0.574183, 0.838307, 1.123116, 1.615720, 2.602005",\ + "0.650079, 0.914199, 1.199006, 1.691633, 2.677966",\ + "0.905369, 1.169603, 1.454359, 1.946792, 2.932734",\ + "1.830298, 2.094694, 2.379872, 2.872755, 3.859600",\ + "0.616182, 0.886074, 1.169821, 1.661946, 2.647293",\ + "0.657426, 0.927306, 1.211081, 1.703342, 2.688961",\ + "0.733323, 1.003198, 1.286970, 1.779255, 2.764921",\ + "0.988623, 1.258602, 1.542324, 2.034413, 3.019689",\ + "1.913549, 2.183697, 2.467836, 2.960376, 3.946555",\ + "0.679766, 0.951735, 1.233965, 1.725859, 2.710802",\ + "0.721010, 0.992966, 1.275225, 1.767255, 2.752470",\ + "0.796907, 1.068859, 1.351114, 1.843168, 2.828430",\ + "1.052215, 1.324263, 1.606468, 2.098326, 3.083198",\ + "1.977138, 2.249364, 2.531980, 3.024289, 4.010064",\ + "1.015779, 1.316457, 1.586079, 2.075305, 3.056258",\ + "1.057021, 1.357686, 1.627340, 2.116701, 3.097925",\ + "1.132920, 1.433575, 1.703230, 2.192614, 3.173886",\ + "1.388277, 1.688981, 1.958581, 2.447772, 3.428654",\ + "2.313181, 2.614154, 2.884099, 3.373737, 4.355520"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011"); + values ( "0.034901, 0.034921, 0.035051, 0.035499, 0.036393",\ + "0.083287, 0.083291, 0.083337, 0.083496, 0.083813",\ + "0.208547, 0.208578, 0.208621, 0.208624, 0.208631",\ + "0.692555, 0.692580, 0.692833, 0.693579, 0.695072",\ + "2.479533, 2.479533, 2.479533, 2.479533, 2.479533",\ + "0.034901, 0.034921, 0.035053, 0.035499, 0.036393",\ + "0.083287, 0.083291, 0.083337, 0.083496, 0.083813",\ + "0.208547, 0.208579, 0.208621, 0.208624, 0.208631",\ + "0.692555, 0.692580, 0.692835, 0.693579, 0.695072",\ + "2.479533, 2.479533, 2.479533, 2.479533, 2.479533",\ + "0.034903, 0.034921, 0.035053, 0.035499, 0.036393",\ + "0.083287, 0.083291, 0.083337, 0.083496, 0.083813",\ + "0.208547, 0.208579, 0.208621, 0.208624, 0.208631",\ + "0.692555, 0.692581, 0.692835, 0.693579, 0.695072",\ + "2.479533, 2.479533, 2.479533, 2.479533, 2.479533",\ + "0.034905, 0.034921, 0.035053, 0.035499, 0.036393",\ + "0.083287, 0.083291, 0.083337, 0.083496, 0.083813",\ + "0.208547, 0.208580, 0.208621, 0.208624, 0.208631",\ + "0.692555, 0.692581, 0.692835, 0.693579, 0.695072",\ + "2.479533, 2.479533, 2.479533, 2.479533, 2.479533",\ + "0.034914, 0.034921, 0.035057, 0.035500, 0.036393",\ + "0.083289, 0.083291, 0.083339, 0.083496, 0.083813",\ + "0.208549, 0.208590, 0.208621, 0.208624, 0.208631",\ + "0.692555, 0.692590, 0.692843, 0.693582, 0.695072",\ + "2.479533, 2.479533, 2.479533, 2.479533, 2.479533"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011"); + values ( "0.491807, 0.755750, 1.040134, 1.532324, 2.516704",\ + "0.532692, 0.796638, 1.081002, 1.573128, 2.557379",\ + "0.593088, 0.857084, 1.141423, 1.633441, 2.617476",\ + "0.762034, 1.026038, 1.310351, 1.802328, 2.786283",\ + "1.345402, 1.609523, 1.893616, 2.385030, 3.367858",\ + "0.579215, 0.843313, 1.127773, 1.619038, 2.602638",\ + "0.620100, 0.884201, 1.168641, 1.659842, 2.643312",\ + "0.680497, 0.944646, 1.229061, 1.720155, 2.703410",\ + "0.849443, 1.113601, 1.397989, 1.889042, 2.872216",\ + "1.432811, 1.697085, 1.981253, 2.471745, 3.453792",\ + "0.662453, 0.932313, 1.215738, 1.706660, 2.689593",\ + "0.703338, 0.973200, 1.256606, 1.747463, 2.730268",\ + "0.763739, 1.033646, 1.317026, 1.807776, 2.790365",\ + "0.932687, 1.202600, 1.485954, 1.976664, 2.959171",\ + "1.516071, 1.786084, 2.069218, 2.559366, 3.540747",\ + "0.726033, 0.997974, 1.279881, 1.770573, 2.753102",\ + "0.766918, 1.038862, 1.320749, 1.811376, 2.793777",\ + "0.827322, 1.099308, 1.381169, 1.871690, 2.853874",\ + "0.996272, 1.268262, 1.550097, 2.040577, 3.022680",\ + "1.579666, 1.851744, 2.133361, 2.623279, 3.604256",\ + "1.062019, 1.362705, 1.631983, 2.120014, 3.098558",\ + "1.102906, 1.403592, 1.672850, 2.160817, 3.139233",\ + "1.163330, 1.464039, 1.733269, 2.221130, 3.199330",\ + "1.332287, 1.632990, 1.902197, 2.390017, 3.368136",\ + "1.915751, 2.216458, 2.485455, 2.972717, 3.949712"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011"); + values ( "0.042675, 0.042675, 0.042652, 0.042575, 0.042419",\ + "0.078931, 0.078931, 0.078931, 0.078931, 0.078931",\ + "0.155291, 0.155291, 0.155277, 0.155229, 0.155132",\ + "0.431055, 0.431055, 0.431011, 0.430859, 0.430555",\ + "1.494840, 1.494148, 1.493909, 1.493909, 1.493909",\ + "0.042675, 0.042675, 0.042652, 0.042575, 0.042419",\ + "0.078931, 0.078931, 0.078931, 0.078931, 0.078931",\ + "0.155291, 0.155291, 0.155277, 0.155229, 0.155132",\ + "0.431055, 0.431055, 0.431011, 0.430859, 0.430555",\ + "1.494840, 1.494147, 1.493909, 1.493909, 1.493909",\ + "0.042675, 0.042675, 0.042652, 0.042575, 0.042419",\ + "0.078931, 0.078931, 0.078931, 0.078931, 0.078931",\ + "0.155291, 0.155291, 0.155277, 0.155229, 0.155132",\ + "0.431055, 0.431055, 0.431011, 0.430859, 0.430555",\ + "1.494787, 1.494143, 1.493909, 1.493909, 1.493909",\ + "0.042675, 0.042675, 0.042652, 0.042575, 0.042419",\ + "0.078931, 0.078931, 0.078931, 0.078931, 0.078931",\ + "0.155291, 0.155291, 0.155277, 0.155229, 0.155132",\ + "0.431055, 0.431055, 0.431011, 0.430859, 0.430555",\ + "1.494750, 1.494138, 1.493909, 1.493909, 1.493909",\ + "0.042675, 0.042675, 0.042651, 0.042574, 0.042419",\ + "0.078931, 0.078931, 0.078931, 0.078931, 0.078931",\ + "0.155291, 0.155291, 0.155276, 0.155229, 0.155132",\ + "0.431055, 0.431055, 0.431009, 0.430858, 0.430555",\ + "1.494514, 1.494079, 1.493909, 1.493909, 1.493909"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_2660*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[20]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.327672, 0.566275, 0.848132, 1.348276, 2.348564",\ + "0.368967, 0.607415, 0.888608, 1.386404, 2.381997",\ + "0.444897, 0.683231, 0.964015, 1.460342, 2.452995",\ + "0.700493, 0.938416, 1.218620, 1.714868, 2.707363",\ + "1.624950, 1.862182, 2.144032, 2.639823, 3.631406",\ + "0.415085, 0.653799, 0.935798, 1.434991, 2.434498",\ + "0.456380, 0.694939, 0.976266, 1.473119, 2.467931",\ + "0.532309, 0.770755, 1.051669, 1.547057, 2.538929",\ + "0.787906, 1.025936, 1.306274, 1.801582, 2.793297",\ + "1.712363, 1.949714, 2.231684, 2.726538, 3.717340",\ + "0.495952, 0.742730, 1.023765, 1.522613, 2.521453",\ + "0.537247, 0.783870, 1.064233, 1.560741, 2.554886",\ + "0.613176, 0.859686, 1.139635, 1.634679, 2.625884",\ + "0.868772, 1.114859, 1.394240, 1.889205, 2.880252",\ + "1.793228, 2.038663, 2.319650, 2.814160, 3.804295",\ + "0.553602, 0.808292, 1.087909, 1.586527, 2.584962",\ + "0.594896, 0.849433, 1.128377, 1.624655, 2.618395",\ + "0.670825, 0.925249, 1.203779, 1.698593, 2.689393",\ + "0.926420, 1.180411, 1.458384, 1.953118, 2.943761",\ + "1.850875, 2.104251, 2.383794, 2.878074, 3.867804",\ + "0.871915, 1.171803, 1.440094, 1.936005, 2.930418",\ + "0.913062, 1.212946, 1.480538, 1.974123, 2.963851",\ + "0.988827, 1.288766, 1.555925, 2.048055, 3.034849",\ + "1.244293, 1.543790, 1.810529, 2.302580, 3.289217",\ + "2.167832, 2.468068, 2.735935, 3.227534, 4.213260"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.035017, 0.035017, 0.035948, 0.039191, 0.045676",\ + "0.083549, 0.083549, 0.083882, 0.085042, 0.087361",\ + "0.208718, 0.208718, 0.208873, 0.209414, 0.210496",\ + "0.692609, 0.692819, 0.692927, 0.693071, 0.693361",\ + "2.477031, 2.477031, 2.477147, 2.477551, 2.478359",\ + "0.035017, 0.035017, 0.035958, 0.039191, 0.045676",\ + "0.083549, 0.083549, 0.083886, 0.085042, 0.087361",\ + "0.208718, 0.208718, 0.208875, 0.209414, 0.210496",\ + "0.692609, 0.692819, 0.692927, 0.693071, 0.693361",\ + "2.477031, 2.477031, 2.477149, 2.477551, 2.478359",\ + "0.035017, 0.035017, 0.035958, 0.039191, 0.045676",\ + "0.083549, 0.083549, 0.083886, 0.085042, 0.087361",\ + "0.208718, 0.208718, 0.208875, 0.209414, 0.210496",\ + "0.692610, 0.692820, 0.692927, 0.693071, 0.693361",\ + "2.477031, 2.477031, 2.477149, 2.477551, 2.478359",\ + "0.035017, 0.035017, 0.035959, 0.039191, 0.045676",\ + "0.083549, 0.083549, 0.083886, 0.085042, 0.087361",\ + "0.208718, 0.208718, 0.208875, 0.209414, 0.210496",\ + "0.692612, 0.692821, 0.692927, 0.693071, 0.693361",\ + "2.477031, 2.477031, 2.477149, 2.477551, 2.478359",\ + "0.035017, 0.035017, 0.035992, 0.039204, 0.045676",\ + "0.083549, 0.083549, 0.083898, 0.085047, 0.087361",\ + "0.208718, 0.208718, 0.208880, 0.209416, 0.210496",\ + "0.692710, 0.692838, 0.692928, 0.693072, 0.693361",\ + "2.477031, 2.477031, 2.477153, 2.477553, 2.478359"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.374541, 0.613195, 0.891051, 1.377355, 2.349964",\ + "0.415440, 0.654096, 0.931703, 1.416730, 2.386785",\ + "0.475586, 0.714339, 0.991271, 1.473856, 2.439025",\ + "0.644564, 0.883292, 1.159558, 1.639742, 2.600112",\ + "1.227810, 1.464706, 1.741320, 2.221670, 3.182369",\ + "0.461954, 0.700719, 0.978673, 1.464070, 2.435898",\ + "0.502853, 0.741620, 1.019321, 1.503445, 2.472719",\ + "0.562998, 0.801863, 1.078882, 1.560571, 2.524959",\ + "0.731977, 0.970816, 1.247161, 1.726457, 2.686046",\ + "1.315223, 1.552233, 1.828923, 2.308385, 3.268303",\ + "0.542824, 0.789649, 1.066638, 1.551692, 2.522853",\ + "0.583722, 0.830553, 1.107287, 1.591067, 2.559674",\ + "0.643867, 0.890796, 1.166847, 1.648193, 2.611914",\ + "0.812844, 1.059749, 1.335126, 1.814080, 2.773001",\ + "1.396076, 1.641170, 1.916889, 2.396007, 3.355258",\ + "0.600479, 0.855211, 1.130781, 1.615606, 2.586362",\ + "0.641375, 0.896117, 1.171429, 1.654981, 2.623183",\ + "0.701520, 0.956361, 1.230989, 1.712107, 2.675423",\ + "0.870493, 1.125315, 1.399267, 1.877993, 2.836510",\ + "1.453700, 1.706742, 1.981030, 2.459920, 3.418767",\ + "0.918806, 1.218716, 1.482825, 1.965026, 2.931818",\ + "0.959736, 1.259650, 1.523460, 2.004396, 2.968639",\ + "1.019894, 1.319901, 1.582996, 2.061512, 3.020879",\ + "1.188870, 1.488860, 1.751250, 2.227388, 3.181966",\ + "1.770179, 2.070362, 2.333014, 2.809316, 3.764223"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.042685, 0.042786, 0.042938, 0.042938, 0.042938",\ + "0.078477, 0.079297, 0.079365, 0.079365, 0.079365",\ + "0.155270, 0.155314, 0.155322, 0.155322, 0.155322",\ + "0.431181, 0.431181, 0.431181, 0.431181, 0.431181",\ + "1.494069, 1.494069, 1.494069, 1.494069, 1.494069",\ + "0.042685, 0.042787, 0.042938, 0.042938, 0.042938",\ + "0.078477, 0.079298, 0.079365, 0.079365, 0.079365",\ + "0.155270, 0.155314, 0.155322, 0.155322, 0.155322",\ + "0.431181, 0.431181, 0.431181, 0.431181, 0.431181",\ + "1.494069, 1.494069, 1.494069, 1.494069, 1.494069",\ + "0.042685, 0.042789, 0.042938, 0.042938, 0.042938",\ + "0.078482, 0.079299, 0.079365, 0.079365, 0.079365",\ + "0.155270, 0.155314, 0.155322, 0.155322, 0.155322",\ + "0.431181, 0.431181, 0.431181, 0.431181, 0.431181",\ + "1.494069, 1.494069, 1.494069, 1.494069, 1.494069",\ + "0.042685, 0.042792, 0.042938, 0.042938, 0.042938",\ + "0.078491, 0.079300, 0.079365, 0.079365, 0.079365",\ + "0.155271, 0.155314, 0.155322, 0.155322, 0.155322",\ + "0.431181, 0.431181, 0.431181, 0.431181, 0.431181",\ + "1.494069, 1.494069, 1.494069, 1.494069, 1.494069",\ + "0.042685, 0.042830, 0.042938, 0.042938, 0.042938",\ + "0.078951, 0.079317, 0.079365, 0.079365, 0.079365",\ + "0.155294, 0.155316, 0.155322, 0.155322, 0.155322",\ + "0.431181, 0.431181, 0.431181, 0.431181, 0.431181",\ + "1.494069, 1.494069, 1.494069, 1.494069, 1.494069"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_2717*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[21]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011"); + values ( "0.430110, 0.674363, 0.945987, 1.398684, 2.304079",\ + "0.471359, 0.715604, 0.987211, 1.439891, 2.345252",\ + "0.547252, 0.791500, 1.063102, 1.515754, 2.421058",\ + "0.802426, 1.046828, 1.318547, 1.770909, 2.675633",\ + "1.727400, 1.971804, 2.243712, 2.696691, 3.602648",\ + "0.517512, 0.761931, 1.033499, 1.485397, 2.390012",\ + "0.558762, 0.803171, 1.074723, 1.526605, 2.431185",\ + "0.634655, 0.879067, 1.150614, 1.602467, 2.506991",\ + "0.889829, 1.134397, 1.406058, 1.857622, 2.761567",\ + "1.814803, 2.059373, 2.331226, 2.783404, 3.688582",\ + "0.598336, 0.850913, 1.121461, 1.573018, 2.476967",\ + "0.639585, 0.892153, 1.162685, 1.614225, 2.518140",\ + "0.715478, 0.968049, 1.238575, 1.690088, 2.593946",\ + "0.970652, 1.223382, 1.494019, 1.945243, 2.848522",\ + "1.895626, 2.148358, 2.419187, 2.871025, 3.775537",\ + "0.655998, 0.916548, 1.185597, 1.636931, 2.540476",\ + "0.697247, 0.957788, 1.226822, 1.678138, 2.581649",\ + "0.773140, 1.033684, 1.302712, 1.754000, 2.657455",\ + "1.028314, 1.289021, 1.558156, 2.009156, 2.912031",\ + "1.953288, 2.213997, 2.483324, 2.934937, 3.839046",\ + "0.986976, 1.281046, 1.537295, 1.986203, 2.885932",\ + "1.028225, 1.322284, 1.578519, 2.027411, 2.927105",\ + "1.104119, 1.398180, 1.654409, 2.103273, 3.002912",\ + "1.359298, 1.653568, 1.909851, 2.358427, 3.257487",\ + "2.284269, 2.578546, 2.835025, 3.284211, 4.184502"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011"); + values ( "0.034880, 0.034905, 0.035033, 0.035354, 0.035995",\ + "0.083283, 0.083287, 0.083329, 0.083448, 0.083687",\ + "0.208545, 0.208582, 0.208618, 0.208622, 0.208628",\ + "0.692606, 0.692606, 0.692841, 0.693640, 0.695237",\ + "2.479823, 2.479823, 2.479823, 2.479823, 2.479823",\ + "0.034880, 0.034906, 0.035034, 0.035354, 0.035995",\ + "0.083283, 0.083287, 0.083329, 0.083448, 0.083687",\ + "0.208545, 0.208582, 0.208618, 0.208622, 0.208628",\ + "0.692606, 0.692606, 0.692844, 0.693640, 0.695237",\ + "2.479823, 2.479823, 2.479823, 2.479823, 2.479823",\ + "0.034880, 0.034906, 0.035034, 0.035354, 0.035995",\ + "0.083283, 0.083288, 0.083329, 0.083448, 0.083687",\ + "0.208545, 0.208582, 0.208618, 0.208622, 0.208628",\ + "0.692606, 0.692606, 0.692844, 0.693640, 0.695237",\ + "2.479823, 2.479823, 2.479823, 2.479823, 2.479823",\ + "0.034880, 0.034907, 0.035034, 0.035354, 0.035995",\ + "0.083283, 0.083288, 0.083329, 0.083448, 0.083687",\ + "0.208546, 0.208583, 0.208618, 0.208622, 0.208628",\ + "0.692606, 0.692606, 0.692844, 0.693640, 0.695237",\ + "2.479823, 2.479823, 2.479823, 2.479823, 2.479823",\ + "0.034881, 0.034915, 0.035037, 0.035355, 0.035995",\ + "0.083283, 0.083289, 0.083330, 0.083449, 0.083687",\ + "0.208552, 0.208592, 0.208618, 0.208622, 0.208628",\ + "0.692606, 0.692606, 0.692852, 0.693643, 0.695237",\ + "2.479823, 2.479823, 2.479823, 2.479823, 2.479823"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011"); + values ( "0.476452, 0.720627, 0.992222, 1.445174, 2.351079",\ + "0.517334, 0.761513, 1.033104, 1.486024, 2.391864",\ + "0.577683, 0.821926, 1.093569, 1.546380, 2.452001",\ + "0.746610, 0.990875, 1.262519, 1.715235, 2.620666",\ + "1.329814, 1.574285, 1.846012, 2.298098, 3.202269",\ + "0.563855, 0.808193, 1.079735, 1.531888, 2.437013",\ + "0.604736, 0.849079, 1.120617, 1.572738, 2.477798",\ + "0.665086, 0.909493, 1.181081, 1.633093, 2.537935",\ + "0.834013, 1.078442, 1.350031, 1.801948, 2.706600",\ + "1.417216, 1.661854, 1.933522, 2.384811, 3.288203",\ + "0.644678, 0.897174, 1.167696, 1.619509, 2.523968",\ + "0.685559, 0.938060, 1.208579, 1.660358, 2.564753",\ + "0.745909, 0.998475, 1.269043, 1.720713, 2.624890",\ + "0.914836, 1.167425, 1.437993, 1.889569, 2.793555",\ + "1.498040, 1.750840, 2.021483, 2.472431, 3.375158",\ + "0.702340, 0.962807, 1.231833, 1.683421, 2.587477",\ + "0.743221, 1.003693, 1.272716, 1.724271, 2.628262",\ + "0.803571, 1.064109, 1.333179, 1.784626, 2.688399",\ + "0.972498, 1.233060, 1.502129, 1.953481, 2.857064",\ + "1.555702, 1.816481, 2.085620, 2.536344, 3.438667",\ + "1.033316, 1.327279, 1.583534, 2.032695, 2.932933",\ + "1.074197, 1.368167, 1.624416, 2.073545, 2.973718",\ + "1.134549, 1.428604, 1.684879, 2.133899, 3.033855",\ + "1.303477, 1.597562, 1.853827, 2.302754, 3.202520",\ + "1.886688, 2.181050, 2.437312, 2.885614, 3.784123"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011"); + values ( "0.042687, 0.042687, 0.042669, 0.042608, 0.042485",\ + "0.078970, 0.078970, 0.078967, 0.078960, 0.078944",\ + "0.155296, 0.155296, 0.155281, 0.155232, 0.155132",\ + "0.431084, 0.431084, 0.431042, 0.430897, 0.430607",\ + "1.495395, 1.494888, 1.494241, 1.494241, 1.494241",\ + "0.042687, 0.042687, 0.042669, 0.042608, 0.042485",\ + "0.078970, 0.078970, 0.078967, 0.078960, 0.078944",\ + "0.155296, 0.155296, 0.155281, 0.155232, 0.155132",\ + "0.431084, 0.431084, 0.431041, 0.430897, 0.430607",\ + "1.495395, 1.494883, 1.494241, 1.494241, 1.494241",\ + "0.042687, 0.042687, 0.042669, 0.042608, 0.042485",\ + "0.078970, 0.078970, 0.078967, 0.078960, 0.078944",\ + "0.155296, 0.155296, 0.155281, 0.155232, 0.155132",\ + "0.431084, 0.431084, 0.431041, 0.430897, 0.430607",\ + "1.495394, 1.494874, 1.494241, 1.494241, 1.494241",\ + "0.042687, 0.042687, 0.042669, 0.042608, 0.042485",\ + "0.078970, 0.078970, 0.078967, 0.078960, 0.078944",\ + "0.155296, 0.155296, 0.155281, 0.155232, 0.155132",\ + "0.431084, 0.431084, 0.431041, 0.430897, 0.430607",\ + "1.495394, 1.494860, 1.494241, 1.494241, 1.494241",\ + "0.042687, 0.042687, 0.042668, 0.042607, 0.042485",\ + "0.078970, 0.078970, 0.078967, 0.078960, 0.078944",\ + "0.155296, 0.155296, 0.155280, 0.155231, 0.155132",\ + "0.431084, 0.431084, 0.431040, 0.430896, 0.430607",\ + "1.495370, 1.494698, 1.494241, 1.494241, 1.494241"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[6]_redg*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[25]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011"); + values ( "0.554256, 0.796472, 1.062238, 1.540435, 2.496829",\ + "0.588688, 0.830904, 1.096670, 1.574875, 2.531283",\ + "0.659682, 0.901899, 1.167669, 1.645892, 2.602338",\ + "0.913848, 1.156064, 1.421858, 1.900173, 2.856801",\ + "1.839032, 2.081247, 2.347044, 2.825424, 3.782184",\ + "0.641661, 0.883946, 1.149831, 1.627148, 2.582762",\ + "0.676093, 0.918377, 1.184264, 1.661588, 2.617217",\ + "0.747088, 0.989372, 1.255262, 1.732605, 2.688272",\ + "1.001253, 1.243537, 1.509452, 1.986886, 2.942735",\ + "1.926437, 2.168720, 2.434638, 2.912138, 3.868118",\ + "0.722474, 0.972733, 1.237795, 1.714769, 2.669717",\ + "0.756906, 1.007164, 1.272227, 1.749209, 2.704172",\ + "0.827901, 1.078159, 1.343225, 1.820227, 2.775227",\ + "1.082066, 1.332324, 1.597415, 2.074507, 3.029690",\ + "2.007250, 2.257506, 2.522601, 2.999759, 3.955073",\ + "0.781555, 1.038084, 1.301936, 1.778682, 2.733226",\ + "0.815987, 1.072516, 1.336368, 1.813122, 2.767681",\ + "0.886982, 1.143511, 1.407367, 1.884140, 2.838736",\ + "1.141147, 1.397675, 1.661557, 2.138420, 3.093199",\ + "2.066333, 2.322857, 2.586742, 3.063672, 4.018582",\ + "1.117315, 1.399225, 1.653894, 2.128062, 3.078682",\ + "1.151748, 1.433656, 1.688326, 2.162502, 3.113137",\ + "1.222743, 1.504651, 1.759325, 2.233520, 3.184192",\ + "1.476909, 1.758815, 2.013515, 2.487801, 3.438655",\ + "2.402100, 2.683993, 2.938702, 3.413052, 4.364038"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011"); + values ( "0.034240, 0.034243, 0.034261, 0.034303, 0.034388",\ + "0.083583, 0.083591, 0.083624, 0.083701, 0.083855",\ + "0.208066, 0.208072, 0.208099, 0.208159, 0.208278",\ + "0.693300, 0.693300, 0.693300, 0.693300, 0.693300",\ + "2.470761, 2.470782, 2.471502, 2.473964, 2.478889",\ + "0.034240, 0.034244, 0.034261, 0.034303, 0.034388",\ + "0.083583, 0.083591, 0.083625, 0.083701, 0.083855",\ + "0.208066, 0.208072, 0.208099, 0.208159, 0.208278",\ + "0.693300, 0.693300, 0.693300, 0.693300, 0.693300",\ + "2.470761, 2.470782, 2.471510, 2.473964, 2.478889",\ + "0.034240, 0.034244, 0.034261, 0.034303, 0.034388",\ + "0.083583, 0.083591, 0.083625, 0.083701, 0.083855",\ + "0.208066, 0.208073, 0.208099, 0.208159, 0.208278",\ + "0.693300, 0.693300, 0.693300, 0.693300, 0.693300",\ + "2.470761, 2.470782, 2.471510, 2.473964, 2.478889",\ + "0.034240, 0.034244, 0.034261, 0.034303, 0.034388",\ + "0.083583, 0.083591, 0.083625, 0.083701, 0.083855",\ + "0.208066, 0.208073, 0.208099, 0.208159, 0.208278",\ + "0.693300, 0.693300, 0.693300, 0.693300, 0.693300",\ + "2.470764, 2.470782, 2.471510, 2.473964, 2.478889",\ + "0.034240, 0.034245, 0.034262, 0.034304, 0.034388",\ + "0.083583, 0.083594, 0.083625, 0.083701, 0.083855",\ + "0.208066, 0.208075, 0.208100, 0.208159, 0.208278",\ + "0.693300, 0.693300, 0.693300, 0.693300, 0.693300",\ + "2.470774, 2.470782, 2.471535, 2.473975, 2.478889"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011"); + values ( "0.581292, 0.823509, 1.089276, 1.567480, 2.523887",\ + "0.623589, 0.865805, 1.131530, 1.609589, 2.565706",\ + "0.684151, 0.926368, 1.192030, 1.669873, 2.625559",\ + "0.853082, 1.095299, 1.360884, 1.838464, 2.793625",\ + "1.436333, 1.678550, 1.944122, 2.421657, 3.376727",\ + "0.668697, 0.910982, 1.176870, 1.654194, 2.609821",\ + "0.710994, 0.953278, 1.219123, 1.696303, 2.651640",\ + "0.771556, 1.013841, 1.279622, 1.756587, 2.711493",\ + "0.940487, 1.182772, 1.448475, 1.925178, 2.879559",\ + "1.523738, 1.766023, 2.031713, 2.508370, 3.462660",\ + "0.749510, 0.999769, 1.264833, 1.741815, 2.696776",\ + "0.791807, 1.042065, 1.307087, 1.783924, 2.738595",\ + "0.852369, 1.102628, 1.367586, 1.844208, 2.798448",\ + "1.021300, 1.271559, 1.536439, 2.012799, 2.966514",\ + "1.604551, 1.854810, 2.119677, 2.595992, 3.549615",\ + "0.808591, 1.065121, 1.328974, 1.805728, 2.760285",\ + "0.850888, 1.107417, 1.371228, 1.847837, 2.802104",\ + "0.911450, 1.167980, 1.431727, 1.908121, 2.861957",\ + "1.080381, 1.336911, 1.600580, 2.076712, 3.030023",\ + "1.663632, 1.920162, 2.183818, 2.659904, 3.613124",\ + "1.144351, 1.426262, 1.680932, 2.155108, 3.105741",\ + "1.186648, 1.468558, 1.723184, 2.197216, 3.147560",\ + "1.247211, 1.529121, 1.783681, 2.257499, 3.207412",\ + "1.416141, 1.698051, 1.952531, 2.426090, 3.375479",\ + "1.999392, 2.281302, 2.535769, 3.009282, 3.958580"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011"); + values ( "0.045859, 0.045859, 0.045870, 0.045908, 0.045983",\ + "0.079961, 0.079962, 0.079962, 0.079962, 0.079962",\ + "0.155685, 0.155686, 0.155686, 0.155686, 0.155686",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498064, 1.498064, 1.498064, 1.498064, 1.498064",\ + "0.045859, 0.045859, 0.045870, 0.045908, 0.045983",\ + "0.079961, 0.079962, 0.079962, 0.079962, 0.079962",\ + "0.155685, 0.155686, 0.155686, 0.155686, 0.155686",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498064, 1.498064, 1.498064, 1.498064, 1.498064",\ + "0.045859, 0.045859, 0.045870, 0.045908, 0.045983",\ + "0.079961, 0.079962, 0.079962, 0.079962, 0.079962",\ + "0.155685, 0.155686, 0.155686, 0.155686, 0.155686",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498064, 1.498064, 1.498064, 1.498064, 1.498064",\ + "0.045859, 0.045859, 0.045870, 0.045908, 0.045983",\ + "0.079961, 0.079962, 0.079962, 0.079962, 0.079962",\ + "0.155685, 0.155686, 0.155686, 0.155686, 0.155686",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498064, 1.498064, 1.498064, 1.498064, 1.498064",\ + "0.045859, 0.045859, 0.045871, 0.045908, 0.045983",\ + "0.079962, 0.079962, 0.079962, 0.079962, 0.079962",\ + "0.155685, 0.155686, 0.155686, 0.155686, 0.155686",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498064, 1.498064, 1.498064, 1.498064, 1.498064"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_2473*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[28]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.778393, 1.030571, 1.315131, 1.821345, 2.833774",\ + "0.812784, 1.064961, 1.349521, 1.855736, 2.868164",\ + "0.884026, 1.136204, 1.420765, 1.926979, 2.939408",\ + "1.138193, 1.390371, 1.674931, 2.181146, 3.193574",\ + "2.062764, 2.314940, 2.599499, 3.105713, 4.118140",\ + "0.865806, 1.118101, 1.402816, 1.908060, 2.919708",\ + "0.900196, 1.152491, 1.437207, 1.942451, 2.954098",\ + "0.971439, 1.223734, 1.508450, 2.013694, 3.025342",\ + "1.225605, 1.477901, 1.762616, 2.267860, 3.279508",\ + "2.150177, 2.402470, 2.687184, 3.192428, 4.204074",\ + "0.946677, 1.207046, 1.490783, 1.995683, 3.006663",\ + "0.981067, 1.241436, 1.525173, 2.030073, 3.041053",\ + "1.052310, 1.312679, 1.596416, 2.101316, 3.112297",\ + "1.306477, 1.566845, 1.850583, 2.355483, 3.366463",\ + "2.231048, 2.491415, 2.775151, 3.280050, 4.291029",\ + "1.005325, 1.272628, 1.554929, 2.059596, 3.070172",\ + "1.039716, 1.307018, 1.589319, 2.093987, 3.104562",\ + "1.110958, 1.378261, 1.660562, 2.165230, 3.175806",\ + "1.365125, 1.632428, 1.914729, 2.419396, 3.429972",\ + "2.289696, 2.556998, 2.839297, 3.343963, 4.354538",\ + "1.337288, 1.636376, 1.907175, 2.409100, 3.415628",\ + "1.371678, 1.670766, 1.941566, 2.443490, 3.450018",\ + "1.442921, 1.742009, 2.012809, 2.514733, 3.521262",\ + "1.697088, 1.996176, 2.266975, 2.768899, 3.775428",\ + "2.621658, 2.920745, 3.191543, 3.693467, 4.699994"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.034112, 0.034112, 0.034112, 0.034112, 0.034113",\ + "0.083750, 0.083750, 0.083750, 0.083750, 0.083752",\ + "0.208404, 0.208405, 0.208405, 0.208405, 0.208405",\ + "0.692757, 0.692757, 0.692758, 0.692761, 0.692767",\ + "2.464329, 2.464329, 2.464329, 2.464329, 2.464329",\ + "0.034112, 0.034112, 0.034112, 0.034112, 0.034113",\ + "0.083750, 0.083750, 0.083750, 0.083750, 0.083752",\ + "0.208404, 0.208405, 0.208405, 0.208405, 0.208405",\ + "0.692757, 0.692757, 0.692758, 0.692761, 0.692767",\ + "2.464329, 2.464329, 2.464329, 2.464329, 2.464329",\ + "0.034112, 0.034112, 0.034112, 0.034112, 0.034113",\ + "0.083750, 0.083750, 0.083750, 0.083750, 0.083752",\ + "0.208404, 0.208405, 0.208405, 0.208405, 0.208405",\ + "0.692757, 0.692757, 0.692758, 0.692761, 0.692767",\ + "2.464329, 2.464329, 2.464329, 2.464329, 2.464329",\ + "0.034112, 0.034112, 0.034112, 0.034112, 0.034113",\ + "0.083750, 0.083750, 0.083750, 0.083750, 0.083752",\ + "0.208404, 0.208405, 0.208405, 0.208405, 0.208405",\ + "0.692757, 0.692757, 0.692758, 0.692761, 0.692767",\ + "2.464329, 2.464329, 2.464329, 2.464329, 2.464329",\ + "0.034112, 0.034112, 0.034112, 0.034112, 0.034113",\ + "0.083750, 0.083750, 0.083750, 0.083750, 0.083752",\ + "0.208404, 0.208405, 0.208405, 0.208405, 0.208405",\ + "0.692757, 0.692757, 0.692758, 0.692761, 0.692767",\ + "2.464329, 2.464329, 2.464329, 2.464329, 2.464329"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.810153, 1.062330, 1.346888, 1.853102, 2.865529",\ + "0.851906, 1.104082, 1.388641, 1.894854, 2.907281",\ + "0.911836, 1.164013, 1.448571, 1.954785, 2.967211",\ + "1.079953, 1.332130, 1.616688, 2.122902, 3.135329",\ + "1.661862, 1.914034, 2.198587, 2.704797, 3.717218",\ + "0.897566, 1.149860, 1.434573, 1.939816, 2.951462",\ + "0.939318, 1.191612, 1.476326, 1.981569, 2.993215",\ + "0.999249, 1.251543, 1.536256, 2.041499, 3.053145",\ + "1.167366, 1.419660, 1.704374, 2.209617, 3.221262",\ + "1.749275, 2.001564, 2.286272, 2.791512, 3.803152",\ + "0.978437, 1.238804, 1.522540, 2.027439, 3.038417",\ + "1.020190, 1.280557, 1.564292, 2.069191, 3.080170",\ + "1.080120, 1.340487, 1.624223, 2.129122, 3.140100",\ + "1.248237, 1.508604, 1.792340, 2.297239, 3.308218",\ + "1.830146, 2.090508, 2.374238, 2.879134, 3.890107",\ + "1.037085, 1.304387, 1.586686, 2.091352, 3.101926",\ + "1.078838, 1.346139, 1.628438, 2.133105, 3.143679",\ + "1.138768, 1.406070, 1.688369, 2.193035, 3.203609",\ + "1.306885, 1.574187, 1.856486, 2.361152, 3.371727",\ + "1.888794, 2.156091, 2.438385, 2.943048, 3.953616",\ + "1.369048, 1.668134, 1.938932, 2.440856, 3.447382",\ + "1.410800, 1.709887, 1.980685, 2.482608, 3.489135",\ + "1.470731, 1.769817, 2.040615, 2.542538, 3.549065",\ + "1.638848, 1.937934, 2.208732, 2.710656, 3.717183",\ + "2.220756, 2.519837, 2.790631, 3.292551, 4.299072"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.045877, 0.045878, 0.045878, 0.045878, 0.045878",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494119, 1.494119, 1.494119, 1.494119, 1.494120",\ + "0.045877, 0.045878, 0.045878, 0.045878, 0.045878",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494119, 1.494119, 1.494119, 1.494119, 1.494120",\ + "0.045877, 0.045878, 0.045878, 0.045878, 0.045878",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494119, 1.494119, 1.494119, 1.494119, 1.494120",\ + "0.045877, 0.045878, 0.045878, 0.045878, 0.045878",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494119, 1.494119, 1.494119, 1.494119, 1.494120",\ + "0.045877, 0.045878, 0.045878, 0.045878, 0.045878",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494119, 1.494119, 1.494119, 1.494119, 1.494120"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_2603*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[29]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.769218, 1.013990, 1.288183, 1.753076, 2.682863",\ + "0.803608, 1.048380, 1.322573, 1.787467, 2.717253",\ + "0.874851, 1.119623, 1.393816, 1.858710, 2.788497",\ + "1.129017, 1.373789, 1.647983, 2.112876, 3.042663",\ + "2.053588, 2.298358, 2.572550, 3.037443, 3.967230",\ + "0.856623, 1.101544, 1.375734, 1.839790, 2.768797",\ + "0.891013, 1.135935, 1.410125, 1.874180, 2.803187",\ + "0.962256, 1.207178, 1.481368, 1.945424, 2.874431",\ + "1.216422, 1.461344, 1.735534, 2.199590, 3.128597",\ + "2.140993, 2.385913, 2.660101, 3.124157, 4.053164",\ + "0.937445, 1.190511, 1.463697, 1.927411, 2.855752",\ + "0.971835, 1.224902, 1.498087, 1.961801, 2.890142",\ + "1.043078, 1.296145, 1.569331, 2.033045, 2.961386",\ + "1.297244, 1.550311, 1.823497, 2.287211, 3.215552",\ + "2.221816, 2.474880, 2.748064, 3.211778, 4.140119",\ + "0.995080, 1.256125, 1.527836, 1.991324, 2.919261",\ + "1.029471, 1.290515, 1.562226, 2.025714, 2.953651",\ + "1.100714, 1.361758, 1.633469, 2.096957, 3.024895",\ + "1.354880, 1.615925, 1.887636, 2.351124, 3.279061",\ + "2.279451, 2.540493, 2.812203, 3.275691, 4.203628",\ + "1.324766, 1.620334, 1.879659, 2.340649, 3.264717",\ + "1.359156, 1.654725, 1.914049, 2.375039, 3.299107",\ + "1.430399, 1.725968, 1.985292, 2.446283, 3.370351",\ + "1.684566, 1.980134, 2.239459, 2.700449, 3.624517",\ + "2.609136, 2.904703, 3.164026, 3.625016, 4.549084"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.034112, 0.034112, 0.034112, 0.034112, 0.034113",\ + "0.083750, 0.083750, 0.083750, 0.083751, 0.083752",\ + "0.208404, 0.208405, 0.208405, 0.208405, 0.208405",\ + "0.692757, 0.692757, 0.692758, 0.692762, 0.692768",\ + "2.464326, 2.464326, 2.464326, 2.464326, 2.464326",\ + "0.034112, 0.034112, 0.034112, 0.034112, 0.034113",\ + "0.083750, 0.083750, 0.083750, 0.083751, 0.083752",\ + "0.208404, 0.208405, 0.208405, 0.208405, 0.208405",\ + "0.692757, 0.692757, 0.692758, 0.692762, 0.692768",\ + "2.464326, 2.464326, 2.464326, 2.464326, 2.464326",\ + "0.034112, 0.034112, 0.034112, 0.034112, 0.034113",\ + "0.083750, 0.083750, 0.083750, 0.083751, 0.083752",\ + "0.208404, 0.208405, 0.208405, 0.208405, 0.208405",\ + "0.692757, 0.692757, 0.692758, 0.692762, 0.692768",\ + "2.464326, 2.464326, 2.464326, 2.464326, 2.464326",\ + "0.034112, 0.034112, 0.034112, 0.034112, 0.034113",\ + "0.083750, 0.083750, 0.083750, 0.083751, 0.083752",\ + "0.208404, 0.208405, 0.208405, 0.208405, 0.208405",\ + "0.692757, 0.692757, 0.692758, 0.692762, 0.692768",\ + "2.464326, 2.464326, 2.464326, 2.464326, 2.464326",\ + "0.034112, 0.034112, 0.034112, 0.034112, 0.034113",\ + "0.083750, 0.083750, 0.083750, 0.083751, 0.083752",\ + "0.208404, 0.208405, 0.208405, 0.208405, 0.208405",\ + "0.692757, 0.692757, 0.692758, 0.692762, 0.692768",\ + "2.464326, 2.464326, 2.464326, 2.464326, 2.464326"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.800978, 1.045748, 1.319939, 1.784832, 2.714618",\ + "0.842730, 1.087500, 1.361691, 1.826584, 2.756371",\ + "0.902660, 1.147430, 1.421622, 1.886515, 2.816301",\ + "1.070778, 1.315548, 1.589739, 2.054632, 2.984419",\ + "1.652686, 1.897449, 2.171633, 2.636526, 3.566311",\ + "0.888383, 1.133302, 1.407490, 1.871546, 2.800552",\ + "0.930135, 1.175055, 1.449243, 1.913298, 2.842305",\ + "0.990066, 1.234985, 1.509173, 1.973228, 2.902235",\ + "1.158183, 1.403102, 1.677290, 2.141346, 3.070352",\ + "1.740091, 1.985004, 2.259185, 2.723239, 3.652244",\ + "0.969205, 1.222269, 1.495453, 1.959167, 2.887507",\ + "1.010957, 1.264022, 1.537205, 2.000919, 2.929260",\ + "1.070888, 1.323952, 1.597136, 2.060850, 2.989190",\ + "1.239005, 1.492069, 1.765253, 2.228967, 3.157307",\ + "1.820914, 2.073971, 2.347147, 2.810860, 3.739199",\ + "1.026840, 1.287883, 1.559592, 2.023079, 2.951016",\ + "1.068593, 1.329635, 1.601344, 2.064832, 2.992769",\ + "1.128523, 1.389565, 1.661275, 2.124762, 3.052699",\ + "1.296640, 1.557683, 1.829392, 2.292880, 3.220816",\ + "1.878549, 2.139584, 2.411286, 2.874773, 3.802708",\ + "1.356526, 1.652092, 1.911415, 2.372405, 3.296472",\ + "1.398278, 1.693844, 1.953167, 2.414157, 3.338225",\ + "1.458209, 1.753775, 2.013098, 2.474087, 3.398155",\ + "1.626326, 1.921892, 2.181215, 2.642205, 3.566272",\ + "2.208233, 2.503792, 2.763109, 3.224098, 4.148165"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.045877, 0.045878, 0.045878, 0.045878, 0.045878",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494119, 1.494119, 1.494119, 1.494119, 1.494121",\ + "0.045877, 0.045878, 0.045878, 0.045878, 0.045878",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494119, 1.494119, 1.494119, 1.494119, 1.494121",\ + "0.045877, 0.045878, 0.045878, 0.045878, 0.045878",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494119, 1.494119, 1.494119, 1.494119, 1.494121",\ + "0.045877, 0.045878, 0.045878, 0.045878, 0.045878",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494119, 1.494119, 1.494119, 1.494119, 1.494121",\ + "0.045877, 0.045878, 0.045878, 0.045878, 0.045878",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494119, 1.494119, 1.494119, 1.494119, 1.494121"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_2649*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[32]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.634427, 0.872697, 1.149292, 1.635475, 2.607842",\ + "0.668851, 0.907120, 1.183712, 1.669888, 2.642240",\ + "0.739833, 0.978100, 1.254713, 1.740957, 2.713446",\ + "0.993985, 1.232251, 1.508868, 1.995127, 2.967646",\ + "1.919059, 2.157313, 2.433878, 2.919960, 3.892124",\ + "0.721829, 0.960233, 1.236908, 1.722188, 2.693776",\ + "0.756252, 0.994656, 1.271329, 1.756601, 2.728174",\ + "0.827235, 1.065637, 1.342330, 1.827670, 2.799379",\ + "1.081387, 1.319787, 1.596485, 2.081840, 3.053579",\ + "2.006460, 2.244850, 2.521494, 3.006673, 3.978058",\ + "0.802677, 1.049143, 1.324872, 1.809809, 2.780731",\ + "0.837101, 1.083566, 1.359292, 1.844222, 2.815129",\ + "0.908083, 1.154546, 1.430293, 1.915291, 2.886334",\ + "1.162235, 1.408697, 1.684448, 2.169461, 3.140534",\ + "2.087309, 2.333760, 2.609457, 3.094293, 4.065013",\ + "0.860401, 1.114674, 1.389014, 1.873721, 2.844240",\ + "0.894825, 1.149096, 1.423434, 1.908134, 2.878638",\ + "0.965807, 1.220077, 1.494435, 1.979203, 2.949843",\ + "1.219959, 1.474228, 1.748591, 2.233373, 3.204043",\ + "2.145033, 2.399290, 2.673600, 3.158206, 4.128522",\ + "1.188527, 1.477957, 1.741051, 2.223131, 3.189696",\ + "1.222950, 1.512379, 1.775471, 2.257544, 3.224094",\ + "1.293931, 1.583360, 1.846473, 2.328613, 3.295300",\ + "1.548083, 1.837511, 2.100628, 2.582783, 3.549500",\ + "2.473149, 2.762573, 3.025636, 3.507615, 4.473978"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.034240, 0.034240, 0.034242, 0.034250, 0.034266",\ + "0.083583, 0.083583, 0.083588, 0.083605, 0.083639",\ + "0.208066, 0.208067, 0.208071, 0.208084, 0.208111",\ + "0.693291, 0.693291, 0.693291, 0.693291, 0.693291",\ + "2.470530, 2.470530, 2.470531, 2.470531, 2.470532",\ + "0.034240, 0.034240, 0.034243, 0.034250, 0.034266",\ + "0.083583, 0.083583, 0.083589, 0.083605, 0.083639",\ + "0.208066, 0.208067, 0.208071, 0.208084, 0.208111",\ + "0.693291, 0.693291, 0.693291, 0.693291, 0.693291",\ + "2.470530, 2.470530, 2.470531, 2.470531, 2.470532",\ + "0.034240, 0.034240, 0.034243, 0.034250, 0.034266",\ + "0.083583, 0.083583, 0.083589, 0.083605, 0.083639",\ + "0.208066, 0.208067, 0.208071, 0.208084, 0.208111",\ + "0.693291, 0.693291, 0.693291, 0.693291, 0.693291",\ + "2.470530, 2.470530, 2.470531, 2.470531, 2.470532",\ + "0.034240, 0.034240, 0.034243, 0.034250, 0.034266",\ + "0.083583, 0.083583, 0.083589, 0.083605, 0.083639",\ + "0.208066, 0.208067, 0.208071, 0.208084, 0.208111",\ + "0.693291, 0.693291, 0.693291, 0.693291, 0.693291",\ + "2.470530, 2.470530, 2.470531, 2.470531, 2.470532",\ + "0.034240, 0.034240, 0.034243, 0.034250, 0.034266",\ + "0.083583, 0.083583, 0.083589, 0.083605, 0.083639",\ + "0.208066, 0.208067, 0.208071, 0.208084, 0.208111",\ + "0.693291, 0.693291, 0.693291, 0.693291, 0.693291",\ + "2.470530, 2.470530, 2.470531, 2.470531, 2.470532"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.661467, 0.899737, 1.176348, 1.662586, 2.635063",\ + "0.703763, 0.942033, 1.218582, 1.704611, 2.676670",\ + "0.764325, 1.002595, 1.279082, 1.764899, 2.736534",\ + "0.933255, 1.171525, 1.447944, 1.933534, 2.904712",\ + "1.516509, 1.754779, 2.031088, 2.516304, 3.486737",\ + "0.748868, 0.987273, 1.263965, 1.749299, 2.720997",\ + "0.791164, 1.029569, 1.306198, 1.791324, 2.762603",\ + "0.851727, 1.090131, 1.366697, 1.851612, 2.822468",\ + "1.020657, 1.259062, 1.535559, 2.020247, 2.990646",\ + "1.603910, 1.842315, 2.118701, 2.603017, 3.572671",\ + "0.829717, 1.076183, 1.351928, 1.836920, 2.807952",\ + "0.872012, 1.118479, 1.394161, 1.878945, 2.849558",\ + "0.932575, 1.179041, 1.454660, 1.939233, 2.909423",\ + "1.101505, 1.347972, 1.623522, 2.107867, 3.077601",\ + "1.684759, 1.931225, 2.206665, 2.690638, 3.659626",\ + "0.887441, 1.141714, 1.416070, 1.900832, 2.871461",\ + "0.929737, 1.184009, 1.458303, 1.942857, 2.913067",\ + "0.990299, 1.244572, 1.518803, 2.003145, 2.972932",\ + "1.159229, 1.413502, 1.687665, 2.171780, 3.141110",\ + "1.742483, 1.996755, 2.270807, 2.754550, 3.723135",\ + "1.215567, 1.504997, 1.768108, 2.250242, 3.216917",\ + "1.257862, 1.547292, 1.810339, 2.292266, 3.258523",\ + "1.318425, 1.607855, 1.870836, 2.352553, 3.318388",\ + "1.487355, 1.776785, 2.039696, 2.521187, 3.486566",\ + "2.070609, 2.360038, 2.622834, 3.103956, 4.068591"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.045862, 0.045862, 0.045862, 0.045862, 0.045862",\ + "0.079960, 0.079960, 0.079960, 0.079960, 0.079960",\ + "0.155688, 0.155688, 0.155688, 0.155688, 0.155688",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498067, 1.498067, 1.498067, 1.498067, 1.498067",\ + "0.045862, 0.045862, 0.045862, 0.045862, 0.045862",\ + "0.079960, 0.079960, 0.079960, 0.079960, 0.079960",\ + "0.155688, 0.155688, 0.155688, 0.155688, 0.155688",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498067, 1.498067, 1.498067, 1.498067, 1.498067",\ + "0.045862, 0.045862, 0.045862, 0.045862, 0.045862",\ + "0.079960, 0.079960, 0.079960, 0.079960, 0.079960",\ + "0.155688, 0.155688, 0.155688, 0.155688, 0.155688",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498067, 1.498067, 1.498067, 1.498067, 1.498067",\ + "0.045862, 0.045862, 0.045862, 0.045862, 0.045862",\ + "0.079960, 0.079960, 0.079960, 0.079960, 0.079960",\ + "0.155688, 0.155688, 0.155688, 0.155688, 0.155688",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498067, 1.498067, 1.498067, 1.498067, 1.498067",\ + "0.045862, 0.045862, 0.045862, 0.045862, 0.045862",\ + "0.079960, 0.079960, 0.079960, 0.079960, 0.079960",\ + "0.155688, 0.155688, 0.155688, 0.155688, 0.155688",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498067, 1.498067, 1.498067, 1.498067, 1.498067"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_2302*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[38]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.679396, 0.938967, 1.226201, 1.725937, 2.725407",\ + "0.713789, 0.973360, 1.260594, 1.760331, 2.759802",\ + "0.785026, 1.044598, 1.331832, 1.831566, 2.831035",\ + "1.039193, 1.298764, 1.585998, 2.085732, 3.085201",\ + "1.963796, 2.223368, 2.510604, 3.010348, 4.009837",\ + "0.766804, 1.026534, 1.313864, 1.812651, 2.811341",\ + "0.801197, 1.060927, 1.348257, 1.847045, 2.845736",\ + "0.872434, 1.132165, 1.419494, 1.918280, 2.916969",\ + "1.126601, 1.386331, 1.673661, 2.172447, 3.171135",\ + "2.051204, 2.310935, 2.598267, 3.097062, 4.095771",\ + "0.847692, 1.115543, 1.401829, 1.900272, 2.898296",\ + "0.882085, 1.149936, 1.436222, 1.934666, 2.932691",\ + "0.953322, 1.221174, 1.507460, 2.005902, 3.003924",\ + "1.207489, 1.475340, 1.761626, 2.260068, 3.258090",\ + "2.132092, 2.399944, 2.686232, 3.184684, 4.182726",\ + "0.908548, 1.181219, 1.465974, 1.964185, 2.961805",\ + "0.942941, 1.215612, 1.500367, 1.998580, 2.996200",\ + "1.014178, 1.286850, 1.571604, 2.069815, 3.067433",\ + "1.268345, 1.541016, 1.825771, 2.323982, 3.321599",\ + "2.192948, 2.465620, 2.750377, 3.248597, 4.246235",\ + "1.244710, 1.546113, 1.818152, 2.313658, 3.307261",\ + "1.279103, 1.580506, 1.852545, 2.348052, 3.341656",\ + "1.350341, 1.651744, 1.923782, 2.419287, 3.412889",\ + "1.604507, 1.905910, 2.177949, 2.673453, 3.667055",\ + "2.529111, 2.830513, 3.102555, 3.598069, 4.591691"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.034112, 0.034112, 0.034113, 0.034114, 0.034117",\ + "0.083750, 0.083751, 0.083753, 0.083761, 0.083776",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692760, 0.692762, 0.692776, 0.692813, 0.692889",\ + "2.465102, 2.465102, 2.465169, 2.465398, 2.465856",\ + "0.034112, 0.034112, 0.034113, 0.034114, 0.034117",\ + "0.083750, 0.083751, 0.083753, 0.083761, 0.083776",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692760, 0.692762, 0.692776, 0.692813, 0.692889",\ + "2.465102, 2.465102, 2.465170, 2.465398, 2.465856",\ + "0.034112, 0.034112, 0.034113, 0.034114, 0.034117",\ + "0.083750, 0.083751, 0.083753, 0.083761, 0.083776",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692760, 0.692762, 0.692776, 0.692813, 0.692889",\ + "2.465102, 2.465102, 2.465170, 2.465398, 2.465856",\ + "0.034112, 0.034112, 0.034113, 0.034114, 0.034117",\ + "0.083750, 0.083751, 0.083753, 0.083761, 0.083776",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692760, 0.692762, 0.692776, 0.692813, 0.692889",\ + "2.465102, 2.465102, 2.465170, 2.465398, 2.465856",\ + "0.034112, 0.034112, 0.034113, 0.034114, 0.034117",\ + "0.083750, 0.083751, 0.083754, 0.083761, 0.083776",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692760, 0.692763, 0.692776, 0.692814, 0.692889",\ + "2.465102, 2.465102, 2.465172, 2.465399, 2.465856"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.711192, 0.970763, 1.257999, 1.757746, 2.757238",\ + "0.752943, 1.012514, 1.299751, 1.799497, 2.798988",\ + "0.812873, 1.072445, 1.359681, 1.859427, 2.858919",\ + "0.980990, 1.240561, 1.527798, 2.027544, 3.027034",\ + "1.563015, 1.822585, 2.109830, 2.609611, 3.609173",\ + "0.798600, 1.058330, 1.345662, 1.844460, 2.843172",\ + "0.840351, 1.100081, 1.387414, 1.886211, 2.884922",\ + "0.900282, 1.160012, 1.447344, 1.946141, 2.944853",\ + "1.068398, 1.328128, 1.615461, 2.114258, 3.112968",\ + "1.650424, 1.910152, 2.197493, 2.696325, 3.695107",\ + "0.879488, 1.147339, 1.433627, 1.932081, 2.930127",\ + "0.921239, 1.189090, 1.475379, 1.973832, 2.971877",\ + "0.981170, 1.249021, 1.535309, 2.033763, 3.031808",\ + "1.149286, 1.417137, 1.703426, 2.201879, 3.199923",\ + "1.731312, 1.999161, 2.285458, 2.783947, 3.782062",\ + "0.940344, 1.213015, 1.497772, 1.995995, 2.993636",\ + "0.982095, 1.254766, 1.539524, 2.037745, 3.035386",\ + "1.042026, 1.314697, 1.599454, 2.097676, 3.095317",\ + "1.210142, 1.482813, 1.767570, 2.265792, 3.263432",\ + "1.792167, 2.064837, 2.349603, 2.847860, 3.845571",\ + "1.276506, 1.577909, 1.849950, 2.345467, 3.339092",\ + "1.318258, 1.619660, 1.891702, 2.387218, 3.380842",\ + "1.378188, 1.679591, 1.951632, 2.447148, 3.440773",\ + "1.546304, 1.847707, 2.119749, 2.615264, 3.608888",\ + "2.128330, 2.429730, 2.701782, 3.197332, 4.191027"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.045877, 0.045877, 0.045877, 0.045877, 0.045877",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155804, 0.155804, 0.155804, 0.155804, 0.155804",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494119, 1.494120, 1.494122, 1.494128, 1.494141",\ + "0.045877, 0.045877, 0.045877, 0.045877, 0.045877",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155804, 0.155804, 0.155804, 0.155804, 0.155804",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494119, 1.494120, 1.494122, 1.494128, 1.494141",\ + "0.045877, 0.045877, 0.045877, 0.045877, 0.045877",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155804, 0.155804, 0.155804, 0.155804, 0.155804",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494119, 1.494120, 1.494122, 1.494128, 1.494141",\ + "0.045877, 0.045877, 0.045877, 0.045877, 0.045877",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155804, 0.155804, 0.155804, 0.155804, 0.155804",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494119, 1.494120, 1.494122, 1.494128, 1.494141",\ + "0.045877, 0.045877, 0.045877, 0.045877, 0.045877",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155804, 0.155804, 0.155804, 0.155804, 0.155804",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494119, 1.494120, 1.494122, 1.494128, 1.494141"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_2566*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[39]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011"); + values ( "0.658633, 0.912014, 1.190716, 1.652421, 2.575833",\ + "0.693026, 0.946407, 1.225109, 1.686815, 2.610227",\ + "0.764264, 1.017644, 1.296346, 1.758051, 2.681462",\ + "1.018430, 1.271811, 1.550512, 2.012218, 2.935628",\ + "1.943034, 2.196414, 2.475117, 2.936828, 3.860250",\ + "0.746043, 0.999594, 1.278259, 1.739136, 2.661767",\ + "0.780436, 1.033988, 1.312652, 1.773529, 2.696161",\ + "0.851673, 1.105225, 1.383889, 1.844766, 2.767396",\ + "1.105840, 1.359391, 1.638056, 2.098932, 3.021562",\ + "2.030443, 2.283995, 2.562661, 3.023543, 3.946184",\ + "0.826857, 1.088640, 1.366222, 1.826758, 2.748722",\ + "0.861250, 1.123033, 1.400615, 1.861151, 2.783116",\ + "0.932488, 1.194270, 1.471853, 1.932387, 2.854351",\ + "1.186654, 1.448437, 1.726019, 2.186554, 3.108517",\ + "2.111258, 2.373040, 2.650624, 3.111165, 4.033139",\ + "0.884438, 1.154368, 1.430361, 1.890671, 2.812231",\ + "0.918831, 1.188761, 1.464754, 1.925064, 2.846625",\ + "0.990068, 1.259999, 1.535991, 1.996301, 2.917860",\ + "1.244235, 1.514165, 1.790157, 2.250467, 3.172026",\ + "2.168839, 2.438769, 2.714763, 3.175078, 4.096648",\ + "1.216287, 1.519868, 1.782153, 2.239986, 3.157687",\ + "1.250680, 1.554260, 1.816547, 2.274380, 3.192081",\ + "1.321917, 1.625498, 1.887784, 2.345616, 3.263316",\ + "1.576084, 1.879665, 2.141950, 2.599783, 3.517482",\ + "2.500688, 2.804268, 3.066556, 3.524393, 4.442104"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011"); + values ( "0.034112, 0.034112, 0.034113, 0.034114, 0.034116",\ + "0.083750, 0.083750, 0.083752, 0.083758, 0.083770",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692760, 0.692760, 0.692769, 0.692798, 0.692856",\ + "2.465103, 2.465103, 2.465140, 2.465270, 2.465530",\ + "0.034112, 0.034112, 0.034113, 0.034114, 0.034116",\ + "0.083750, 0.083750, 0.083752, 0.083758, 0.083770",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692760, 0.692760, 0.692770, 0.692798, 0.692856",\ + "2.465103, 2.465103, 2.465141, 2.465270, 2.465530",\ + "0.034112, 0.034112, 0.034113, 0.034114, 0.034116",\ + "0.083750, 0.083750, 0.083752, 0.083758, 0.083770",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692760, 0.692760, 0.692770, 0.692798, 0.692856",\ + "2.465103, 2.465103, 2.465141, 2.465270, 2.465530",\ + "0.034112, 0.034112, 0.034113, 0.034114, 0.034116",\ + "0.083750, 0.083750, 0.083752, 0.083758, 0.083770",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692760, 0.692760, 0.692770, 0.692798, 0.692856",\ + "2.465103, 2.465103, 2.465141, 2.465270, 2.465530",\ + "0.034112, 0.034112, 0.034113, 0.034114, 0.034116",\ + "0.083750, 0.083750, 0.083752, 0.083758, 0.083770",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692760, 0.692761, 0.692770, 0.692799, 0.692856",\ + "2.465103, 2.465103, 2.465142, 2.465271, 2.465530"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011"); + values ( "0.690429, 0.943810, 1.222513, 1.684225, 2.607649",\ + "0.732181, 0.985561, 1.264264, 1.725976, 2.649400",\ + "0.792111, 1.045491, 1.324195, 1.785906, 2.709330",\ + "0.960228, 1.213608, 1.492311, 1.954023, 2.877446",\ + "1.542253, 1.795633, 2.074341, 2.536073, 3.459536",\ + "0.777839, 1.031390, 1.310056, 1.770939, 2.693583",\ + "0.819590, 1.073142, 1.351808, 1.812690, 2.735333",\ + "0.879520, 1.133072, 1.411738, 1.872621, 2.795264",\ + "1.047637, 1.301189, 1.579854, 2.040737, 2.963380",\ + "1.629662, 1.883214, 2.161885, 2.622787, 3.545470",\ + "0.858653, 1.120436, 1.398020, 1.858561, 2.780538",\ + "0.900405, 1.162187, 1.439771, 1.900312, 2.822289",\ + "0.960335, 1.222118, 1.499701, 1.960243, 2.882219",\ + "1.128451, 1.390234, 1.667818, 2.128359, 3.050335",\ + "1.710477, 1.972259, 2.249848, 2.710409, 3.632425",\ + "0.916234, 1.186164, 1.462158, 1.922474, 2.844047",\ + "0.957985, 1.227916, 1.503910, 1.964226, 2.885798",\ + "1.017915, 1.287846, 1.563840, 2.024156, 2.945728",\ + "1.186032, 1.455963, 1.731956, 2.192272, 3.113844",\ + "1.768058, 2.037988, 2.313987, 2.774323, 3.695934",\ + "1.248083, 1.551663, 1.813951, 2.271790, 3.189503",\ + "1.289834, 1.593415, 1.855702, 2.313541, 3.231254",\ + "1.349765, 1.653345, 1.915633, 2.373471, 3.291184",\ + "1.517881, 1.821462, 2.083749, 2.541588, 3.459300",\ + "2.099906, 2.403486, 2.665780, 3.123638, 4.041390"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011"); + values ( "0.045877, 0.045876, 0.045874, 0.045865, 0.045847",\ + "0.079914, 0.079914, 0.079913, 0.079913, 0.079912",\ + "0.155804, 0.155804, 0.155802, 0.155795, 0.155781",\ + "0.431307, 0.431307, 0.431306, 0.431305, 0.431302",\ + "1.494119, 1.494119, 1.494121, 1.494126, 1.494135",\ + "0.045877, 0.045876, 0.045874, 0.045865, 0.045847",\ + "0.079914, 0.079914, 0.079913, 0.079913, 0.079912",\ + "0.155804, 0.155804, 0.155802, 0.155795, 0.155781",\ + "0.431307, 0.431307, 0.431306, 0.431305, 0.431302",\ + "1.494119, 1.494119, 1.494121, 1.494126, 1.494135",\ + "0.045877, 0.045876, 0.045874, 0.045865, 0.045847",\ + "0.079914, 0.079914, 0.079913, 0.079913, 0.079912",\ + "0.155804, 0.155804, 0.155802, 0.155795, 0.155781",\ + "0.431307, 0.431307, 0.431306, 0.431305, 0.431302",\ + "1.494119, 1.494119, 1.494121, 1.494126, 1.494135",\ + "0.045877, 0.045876, 0.045874, 0.045865, 0.045847",\ + "0.079914, 0.079914, 0.079913, 0.079913, 0.079912",\ + "0.155804, 0.155804, 0.155802, 0.155795, 0.155781",\ + "0.431307, 0.431307, 0.431306, 0.431305, 0.431302",\ + "1.494119, 1.494119, 1.494121, 1.494126, 1.494135",\ + "0.045877, 0.045876, 0.045874, 0.045865, 0.045847",\ + "0.079914, 0.079914, 0.079913, 0.079913, 0.079912",\ + "0.155804, 0.155804, 0.155802, 0.155795, 0.155781",\ + "0.431307, 0.431307, 0.431306, 0.431305, 0.431302",\ + "1.494119, 1.494119, 1.494121, 1.494126, 1.494135"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_2608*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[41]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.576605, 0.831535, 1.088524, 1.527728, 2.406135",\ + "0.611028, 0.865958, 1.122948, 1.562156, 2.440572",\ + "0.682011, 0.936939, 1.193932, 1.633147, 2.511575",\ + "0.936163, 1.191091, 1.448086, 1.887307, 2.765749",\ + "1.861240, 2.116160, 2.373173, 2.812451, 3.691008",\ + "0.664013, 0.919020, 1.175996, 1.614442, 2.492069",\ + "0.698437, 0.953443, 1.210420, 1.648871, 2.526506",\ + "0.769419, 1.024424, 1.281404, 1.719861, 2.597509",\ + "1.023571, 1.278576, 1.535558, 1.974021, 2.851683",\ + "1.948648, 2.203645, 2.460645, 2.899166, 3.776942",\ + "0.751657, 1.007845, 1.263958, 1.702063, 2.579024",\ + "0.786080, 1.042268, 1.298382, 1.736492, 2.613461",\ + "0.857063, 1.113249, 1.369366, 1.807482, 2.684464",\ + "1.111215, 1.367401, 1.623520, 2.061643, 2.938638",\ + "2.036291, 2.292470, 2.548607, 2.986787, 3.863897",\ + "0.814841, 1.073252, 1.328092, 1.765976, 2.642533",\ + "0.849265, 1.107675, 1.362517, 1.800405, 2.676970",\ + "0.920247, 1.178657, 1.433500, 1.871395, 2.747973",\ + "1.174399, 1.432808, 1.687654, 2.125556, 3.002147",\ + "2.099474, 2.357878, 2.612742, 3.050700, 3.927406",\ + "1.148308, 1.435007, 1.679656, 2.115198, 2.987988",\ + "1.182731, 1.469430, 1.714081, 2.149627, 3.022426",\ + "1.253713, 1.540412, 1.785064, 2.220617, 3.093429",\ + "1.507865, 1.794564, 2.039218, 2.474777, 3.347603",\ + "2.432936, 2.719633, 2.964306, 3.399922, 4.272861"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.034240, 0.034240, 0.034246, 0.034266, 0.034306",\ + "0.083583, 0.083583, 0.083596, 0.083639, 0.083725",\ + "0.208066, 0.208066, 0.208076, 0.208111, 0.208180",\ + "0.693294, 0.693296, 0.693300, 0.693300, 0.693300",\ + "2.470544, 2.470544, 2.470714, 2.471298, 2.472467",\ + "0.034240, 0.034240, 0.034246, 0.034266, 0.034306",\ + "0.083583, 0.083583, 0.083596, 0.083639, 0.083725",\ + "0.208066, 0.208066, 0.208077, 0.208111, 0.208180",\ + "0.693294, 0.693296, 0.693300, 0.693300, 0.693300",\ + "2.470544, 2.470544, 2.470715, 2.471298, 2.472467",\ + "0.034240, 0.034240, 0.034246, 0.034266, 0.034306",\ + "0.083583, 0.083583, 0.083596, 0.083639, 0.083725",\ + "0.208066, 0.208066, 0.208077, 0.208111, 0.208180",\ + "0.693294, 0.693296, 0.693300, 0.693300, 0.693300",\ + "2.470544, 2.470544, 2.470716, 2.471298, 2.472467",\ + "0.034240, 0.034240, 0.034246, 0.034266, 0.034306",\ + "0.083583, 0.083583, 0.083596, 0.083639, 0.083725",\ + "0.208066, 0.208066, 0.208077, 0.208111, 0.208180",\ + "0.693294, 0.693296, 0.693300, 0.693300, 0.693300",\ + "2.470544, 2.470544, 2.470716, 2.471298, 2.472467",\ + "0.034240, 0.034240, 0.034246, 0.034266, 0.034306",\ + "0.083583, 0.083583, 0.083596, 0.083639, 0.083725",\ + "0.208066, 0.208066, 0.208077, 0.208111, 0.208180",\ + "0.693294, 0.693297, 0.693300, 0.693300, 0.693300",\ + "2.470544, 2.470544, 2.470721, 2.471301, 2.472467"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.603644, 0.858574, 1.115563, 1.554765, 2.433169",\ + "0.645940, 0.900870, 1.157859, 1.597061, 2.475466",\ + "0.706502, 0.961433, 1.218421, 1.657624, 2.536028",\ + "0.875433, 1.130363, 1.387352, 1.826554, 2.704960",\ + "1.458686, 1.713616, 1.970605, 2.409806, 3.288209",\ + "0.691052, 0.946059, 1.203035, 1.641479, 2.519103",\ + "0.733348, 0.988355, 1.245331, 1.683775, 2.561400",\ + "0.793911, 1.048918, 1.305893, 1.744338, 2.621962",\ + "0.962841, 1.217848, 1.474824, 1.913269, 2.790894",\ + "1.546094, 1.801101, 2.058077, 2.496521, 3.374143",\ + "0.778696, 1.034884, 1.290997, 1.729101, 2.606058",\ + "0.820992, 1.077180, 1.333292, 1.771397, 2.648355",\ + "0.881555, 1.137743, 1.393855, 1.831960, 2.708917",\ + "1.050485, 1.306673, 1.562785, 2.000890, 2.877849",\ + "1.633738, 1.889926, 2.146038, 2.584142, 3.461098",\ + "0.841881, 1.100292, 1.355131, 1.793014, 2.669567",\ + "0.884176, 1.142587, 1.397427, 1.835310, 2.711864",\ + "0.944739, 1.203150, 1.457990, 1.895873, 2.772426",\ + "1.113669, 1.372080, 1.626920, 2.064803, 2.941358",\ + "1.696922, 1.955333, 2.210173, 2.648055, 3.524607",\ + "1.175348, 1.462047, 1.706695, 2.142236, 3.015023",\ + "1.217643, 1.504343, 1.748991, 2.184532, 3.057320",\ + "1.278206, 1.564905, 1.809554, 2.245094, 3.117882",\ + "1.447136, 1.733835, 1.978484, 2.414025, 3.286813",\ + "2.030389, 2.317089, 2.561737, 2.997277, 3.870063"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.045862, 0.045862, 0.045861, 0.045860, 0.045856",\ + "0.079962, 0.079962, 0.079962, 0.079962, 0.079962",\ + "0.155688, 0.155688, 0.155687, 0.155686, 0.155684",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498067, 1.498067, 1.498066, 1.498065, 1.498061",\ + "0.045862, 0.045862, 0.045861, 0.045860, 0.045856",\ + "0.079962, 0.079962, 0.079962, 0.079962, 0.079962",\ + "0.155688, 0.155688, 0.155687, 0.155686, 0.155684",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498067, 1.498067, 1.498066, 1.498065, 1.498061",\ + "0.045862, 0.045862, 0.045861, 0.045860, 0.045856",\ + "0.079962, 0.079962, 0.079962, 0.079962, 0.079962",\ + "0.155688, 0.155688, 0.155687, 0.155686, 0.155684",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498067, 1.498067, 1.498066, 1.498065, 1.498061",\ + "0.045862, 0.045862, 0.045861, 0.045860, 0.045856",\ + "0.079962, 0.079962, 0.079962, 0.079962, 0.079962",\ + "0.155688, 0.155688, 0.155687, 0.155686, 0.155684",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498067, 1.498067, 1.498066, 1.498065, 1.498061",\ + "0.045862, 0.045862, 0.045861, 0.045860, 0.045856",\ + "0.079962, 0.079962, 0.079962, 0.079962, 0.079962",\ + "0.155688, 0.155688, 0.155687, 0.155686, 0.155684",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498067, 1.498067, 1.498066, 1.498065, 1.498061"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_2536*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[46]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.746778, 1.007936, 1.300121, 1.808548, 2.825403",\ + "0.781168, 1.042326, 1.334511, 1.842939, 2.859794",\ + "0.852412, 1.113570, 1.405754, 1.914182, 2.931037",\ + "1.106578, 1.367736, 1.659921, 2.168348, 3.185203",\ + "2.031144, 2.292302, 2.584487, 3.092916, 4.109773",\ + "0.834191, 1.095510, 1.387813, 1.895263, 2.911337",\ + "0.868581, 1.129900, 1.422203, 1.929654, 2.945728",\ + "0.939824, 1.201144, 1.493447, 2.000897, 3.016971",\ + "1.193991, 1.455310, 1.747613, 2.255063, 3.271137",\ + "2.118557, 2.379876, 2.672179, 3.179631, 4.195706",\ + "0.915090, 1.184556, 1.475780, 1.982886, 2.998292",\ + "0.949480, 1.218946, 1.510170, 2.017276, 3.032683",\ + "1.020724, 1.290190, 1.581414, 2.088519, 3.103926",\ + "1.274890, 1.544356, 1.835580, 2.342686, 3.358092",\ + "2.199456, 2.468922, 2.760146, 3.267253, 4.282661",\ + "0.974724, 1.250286, 1.539926, 2.046799, 3.061801",\ + "1.009114, 1.284676, 1.574316, 2.081189, 3.096192",\ + "1.080358, 1.355919, 1.645560, 2.152433, 3.167435",\ + "1.334524, 1.610085, 1.899726, 2.406599, 3.421601",\ + "2.259090, 2.534652, 2.824292, 3.331166, 4.346170",\ + "1.308449, 1.615752, 1.892195, 2.396312, 3.407257",\ + "1.342839, 1.650142, 1.926585, 2.430702, 3.441648",\ + "1.414083, 1.721386, 1.997829, 2.501945, 3.512891",\ + "1.668249, 1.975552, 2.251995, 2.756112, 3.767057",\ + "2.592815, 2.900118, 3.176561, 3.680679, 4.691627"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.034112, 0.034112, 0.034112, 0.034112, 0.034112",\ + "0.083749, 0.083749, 0.083749, 0.083750, 0.083750",\ + "0.208405, 0.208405, 0.208405, 0.208405, 0.208405",\ + "0.692756, 0.692756, 0.692756, 0.692758, 0.692761",\ + "2.464216, 2.464216, 2.464222, 2.464247, 2.464295",\ + "0.034112, 0.034112, 0.034112, 0.034112, 0.034112",\ + "0.083749, 0.083749, 0.083749, 0.083750, 0.083750",\ + "0.208405, 0.208405, 0.208405, 0.208405, 0.208405",\ + "0.692756, 0.692756, 0.692756, 0.692758, 0.692761",\ + "2.464216, 2.464216, 2.464222, 2.464247, 2.464295",\ + "0.034112, 0.034112, 0.034112, 0.034112, 0.034112",\ + "0.083749, 0.083749, 0.083749, 0.083750, 0.083750",\ + "0.208405, 0.208405, 0.208405, 0.208405, 0.208405",\ + "0.692756, 0.692756, 0.692756, 0.692758, 0.692761",\ + "2.464216, 2.464216, 2.464222, 2.464247, 2.464295",\ + "0.034112, 0.034112, 0.034112, 0.034112, 0.034112",\ + "0.083749, 0.083749, 0.083749, 0.083750, 0.083750",\ + "0.208405, 0.208405, 0.208405, 0.208405, 0.208405",\ + "0.692756, 0.692756, 0.692756, 0.692758, 0.692761",\ + "2.464216, 2.464216, 2.464222, 2.464247, 2.464295",\ + "0.034112, 0.034112, 0.034112, 0.034112, 0.034112",\ + "0.083749, 0.083749, 0.083749, 0.083750, 0.083750",\ + "0.208405, 0.208405, 0.208405, 0.208405, 0.208405",\ + "0.692756, 0.692756, 0.692756, 0.692758, 0.692761",\ + "2.464216, 2.464216, 2.464223, 2.464247, 2.464295"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.778533, 1.039691, 1.331875, 1.840304, 2.857162",\ + "0.820286, 1.081443, 1.373628, 1.882057, 2.898914",\ + "0.880216, 1.141374, 1.433558, 1.941987, 2.958845",\ + "1.048333, 1.309491, 1.601676, 2.110105, 3.126962",\ + "1.630225, 1.891381, 2.183566, 2.692000, 3.708866",\ + "0.865946, 1.127265, 1.419568, 1.927019, 2.943096",\ + "0.907698, 1.169017, 1.461320, 1.968772, 2.984848",\ + "0.967629, 1.228948, 1.521251, 2.028702, 3.044779",\ + "1.135746, 1.397065, 1.689368, 2.196820, 3.212896",\ + "1.717638, 1.978955, 2.271259, 2.778715, 3.794800",\ + "0.946845, 1.216310, 1.507534, 2.014642, 3.030051",\ + "0.988598, 1.258063, 1.549287, 2.056394, 3.071803",\ + "1.048528, 1.317993, 1.609217, 2.116324, 3.131734",\ + "1.216645, 1.486111, 1.777335, 2.284442, 3.299851",\ + "1.798537, 2.068001, 2.359225, 2.866337, 3.881755",\ + "1.006479, 1.282040, 1.571681, 2.078555, 3.093560",\ + "1.048231, 1.323793, 1.613433, 2.120307, 3.135312",\ + "1.108162, 1.383723, 1.673364, 2.180238, 3.195243",\ + "1.276279, 1.551840, 1.841481, 2.348355, 3.363360",\ + "1.858171, 2.133730, 2.423372, 2.930250, 3.945264",\ + "1.340204, 1.647506, 1.923949, 2.428067, 3.439016",\ + "1.381956, 1.689259, 1.965702, 2.469820, 3.480768",\ + "1.441887, 1.749189, 2.025632, 2.529750, 3.540699",\ + "1.610004, 1.917307, 2.193750, 2.697868, 3.708816",\ + "2.191895, 2.499197, 2.775640, 3.279763, 4.290720"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.045878, 0.045878, 0.045878, 0.045878, 0.045878",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494118, 1.494118, 1.494119, 1.494119, 1.494119",\ + "0.045878, 0.045878, 0.045878, 0.045878, 0.045878",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494118, 1.494118, 1.494119, 1.494119, 1.494119",\ + "0.045878, 0.045878, 0.045878, 0.045878, 0.045878",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494118, 1.494118, 1.494119, 1.494119, 1.494119",\ + "0.045878, 0.045878, 0.045878, 0.045878, 0.045878",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494118, 1.494118, 1.494119, 1.494119, 1.494119",\ + "0.045878, 0.045878, 0.045878, 0.045878, 0.045878",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494118, 1.494118, 1.494119, 1.494119, 1.494119"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_2630*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[47]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011"); + values ( "0.730000, 0.984087, 1.265833, 1.734427, 2.671616",\ + "0.764390, 1.018477, 1.300223, 1.768817, 2.706006",\ + "0.835634, 1.089720, 1.371467, 1.840061, 2.777249",\ + "1.089800, 1.343887, 1.625633, 2.094227, 3.031415",\ + "2.014367, 2.268453, 2.550199, 3.018794, 3.955984",\ + "0.817406, 1.071683, 1.353396, 1.821141, 2.757549",\ + "0.851796, 1.106073, 1.387787, 1.855531, 2.791939",\ + "0.923039, 1.177317, 1.459030, 1.926775, 2.863183",\ + "1.177206, 1.431483, 1.713197, 2.180941, 3.117349",\ + "2.101773, 2.356050, 2.637762, 3.105508, 4.041918",\ + "0.898242, 1.160744, 1.441359, 1.908762, 2.844504",\ + "0.932632, 1.195135, 1.475749, 1.943152, 2.878895",\ + "1.003876, 1.266378, 1.546993, 2.014396, 2.950138",\ + "1.258042, 1.520545, 1.801159, 2.268562, 3.204304",\ + "2.182609, 2.445111, 2.725725, 3.193129, 4.128873",\ + "0.955902, 1.226495, 1.505499, 1.972675, 2.908013",\ + "0.990292, 1.260885, 1.539889, 2.007065, 2.942404",\ + "1.061535, 1.332129, 1.611133, 2.078309, 3.013647",\ + "1.315702, 1.586295, 1.865299, 2.332475, 3.267813",\ + "2.240268, 2.510862, 2.789865, 3.257042, 4.192382",\ + "1.290536, 1.592309, 1.857360, 2.322016, 3.253469",\ + "1.324926, 1.626699, 1.891750, 2.356406, 3.287859",\ + "1.396169, 1.697943, 1.962993, 2.427649, 3.359103",\ + "1.650336, 1.952109, 2.217160, 2.681816, 3.613269",\ + "2.574903, 2.876675, 3.141726, 3.606383, 4.537838"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011"); + values ( "0.034112, 0.034112, 0.034112, 0.034112, 0.034112",\ + "0.083749, 0.083749, 0.083749, 0.083750, 0.083750",\ + "0.208405, 0.208405, 0.208405, 0.208405, 0.208405",\ + "0.692756, 0.692756, 0.692756, 0.692757, 0.692760",\ + "2.464221, 2.464222, 2.464226, 2.464241, 2.464270",\ + "0.034112, 0.034112, 0.034112, 0.034112, 0.034112",\ + "0.083749, 0.083749, 0.083749, 0.083750, 0.083750",\ + "0.208405, 0.208405, 0.208405, 0.208405, 0.208405",\ + "0.692756, 0.692756, 0.692756, 0.692757, 0.692760",\ + "2.464221, 2.464222, 2.464226, 2.464241, 2.464270",\ + "0.034112, 0.034112, 0.034112, 0.034112, 0.034112",\ + "0.083749, 0.083749, 0.083749, 0.083750, 0.083750",\ + "0.208405, 0.208405, 0.208405, 0.208405, 0.208405",\ + "0.692756, 0.692756, 0.692756, 0.692757, 0.692760",\ + "2.464221, 2.464222, 2.464226, 2.464241, 2.464270",\ + "0.034112, 0.034112, 0.034112, 0.034112, 0.034112",\ + "0.083749, 0.083749, 0.083749, 0.083750, 0.083750",\ + "0.208405, 0.208405, 0.208405, 0.208405, 0.208405",\ + "0.692756, 0.692756, 0.692756, 0.692757, 0.692760",\ + "2.464221, 2.464222, 2.464226, 2.464241, 2.464270",\ + "0.034112, 0.034112, 0.034112, 0.034112, 0.034112",\ + "0.083749, 0.083749, 0.083749, 0.083750, 0.083750",\ + "0.208405, 0.208405, 0.208405, 0.208405, 0.208405",\ + "0.692756, 0.692756, 0.692756, 0.692757, 0.692760",\ + "2.464221, 2.464222, 2.464226, 2.464241, 2.464270"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011"); + values ( "0.761755, 1.015841, 1.297587, 1.766182, 2.703373",\ + "0.803508, 1.057594, 1.339340, 1.807935, 2.745125",\ + "0.863438, 1.117525, 1.399270, 1.867865, 2.805056",\ + "1.031556, 1.285642, 1.567388, 2.035983, 2.973173",\ + "1.613449, 1.867533, 2.149277, 2.617876, 3.555073",\ + "0.849161, 1.103438, 1.385151, 1.852896, 2.789307",\ + "0.890914, 1.145190, 1.426903, 1.894649, 2.831059",\ + "0.950844, 1.205121, 1.486834, 1.954579, 2.890990",\ + "1.118961, 1.373238, 1.654951, 2.122696, 3.059107",\ + "1.700854, 1.955129, 2.236841, 2.704590, 3.641007",\ + "0.929998, 1.192499, 1.473114, 1.940517, 2.876262",\ + "0.971750, 1.234252, 1.514866, 1.982270, 2.918014",\ + "1.031680, 1.294182, 1.574797, 2.042201, 2.977945",\ + "1.199798, 1.462299, 1.742914, 2.210318, 3.146062",\ + "1.781691, 2.044191, 2.324804, 2.792211, 3.727962",\ + "0.987657, 1.258250, 1.537253, 2.004430, 2.939771",\ + "1.029410, 1.300003, 1.579006, 2.046183, 2.981523",\ + "1.089340, 1.359933, 1.638936, 2.106113, 3.041454",\ + "1.257457, 1.528050, 1.807054, 2.274230, 3.209571",\ + "1.839350, 2.109941, 2.388943, 2.856124, 3.791471",\ + "1.322291, 1.624063, 1.889114, 2.353771, 3.285227",\ + "1.364043, 1.665816, 1.930866, 2.395524, 3.326979",\ + "1.423974, 1.725746, 1.990797, 2.455454, 3.386910",\ + "1.592091, 1.893864, 2.158914, 2.623571, 3.555027",\ + "2.173984, 2.475754, 2.740804, 3.205465, 4.136927"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011"); + values ( "0.045878, 0.045878, 0.045878, 0.045878, 0.045878",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494118, 1.494118, 1.494119, 1.494119, 1.494119",\ + "0.045878, 0.045878, 0.045878, 0.045878, 0.045878",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494118, 1.494118, 1.494119, 1.494119, 1.494119",\ + "0.045878, 0.045878, 0.045878, 0.045878, 0.045878",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494118, 1.494118, 1.494119, 1.494119, 1.494119",\ + "0.045878, 0.045878, 0.045878, 0.045878, 0.045878",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494118, 1.494118, 1.494119, 1.494119, 1.494119",\ + "0.045878, 0.045878, 0.045878, 0.045878, 0.045878",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494118, 1.494118, 1.494119, 1.494119, 1.494119"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_2588*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[16]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011"); + values ( "0.408137, 0.641492, 0.827125, 1.126915, 1.707802",\ + "0.449833, 0.683188, 0.868821, 1.168611, 1.749498",\ + "0.526013, 0.759368, 0.945001, 1.244791, 1.825678",\ + "0.781403, 1.014758, 1.200392, 1.500182, 2.081068",\ + "1.705853, 1.939205, 2.124836, 2.424627, 3.005518",\ + "0.496543, 0.728810, 0.914406, 1.214220, 1.795155",\ + "0.538239, 0.770506, 0.956102, 1.255916, 1.836851",\ + "0.614419, 0.846686, 1.032282, 1.332096, 1.913031",\ + "0.869809, 1.102077, 1.287673, 1.587487, 2.168421",\ + "1.794258, 2.026523, 2.212117, 2.511932, 3.092872",\ + "0.585620, 0.809145, 0.994433, 1.294249, 1.875187",\ + "0.627316, 0.850841, 1.036129, 1.335945, 1.916883",\ + "0.703496, 0.927021, 1.112309, 1.412125, 1.993063",\ + "0.958887, 1.182412, 1.367700, 1.667515, 2.248453",\ + "1.883336, 2.106858, 2.292144, 2.591961, 3.172904",\ + "0.648884, 0.866977, 1.052144, 1.351703, 1.932250",\ + "0.690580, 0.908672, 1.093840, 1.393399, 1.973946",\ + "0.766760, 0.984852, 1.170020, 1.469579, 2.050126",\ + "1.022151, 1.240243, 1.425410, 1.724970, 2.305516",\ + "1.946599, 2.164690, 2.349855, 2.649415, 3.229967",\ + "0.982874, 1.172308, 1.355803, 1.654896, 2.234530",\ + "1.024570, 1.214004, 1.397499, 1.696592, 2.276226",\ + "1.100750, 1.290184, 1.473679, 1.772772, 2.352406",\ + "1.356140, 1.545574, 1.729069, 2.028162, 2.607796",\ + "2.280588, 2.470021, 2.653514, 2.952608, 3.532247"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011"); + values ( "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070075, 0.070075, 0.070075, 0.070075, 0.070076",\ + "0.199411, 0.199411, 0.199411, 0.199411, 0.199413",\ + "0.685859, 0.685859, 0.685859, 0.685862, 0.685867",\ + "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070075, 0.070075, 0.070075, 0.070075, 0.070076",\ + "0.199411, 0.199411, 0.199411, 0.199411, 0.199413",\ + "0.685859, 0.685859, 0.685859, 0.685862, 0.685867",\ + "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070075, 0.070075, 0.070075, 0.070075, 0.070076",\ + "0.199411, 0.199411, 0.199411, 0.199411, 0.199413",\ + "0.685859, 0.685859, 0.685859, 0.685862, 0.685867",\ + "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070075, 0.070075, 0.070075, 0.070075, 0.070076",\ + "0.199411, 0.199411, 0.199411, 0.199411, 0.199413",\ + "0.685859, 0.685859, 0.685859, 0.685862, 0.685867",\ + "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070075, 0.070075, 0.070075, 0.070075, 0.070076",\ + "0.199411, 0.199411, 0.199411, 0.199411, 0.199413",\ + "0.685859, 0.685859, 0.685859, 0.685862, 0.685867",\ + "2.455194, 2.455194, 2.455194, 2.455194, 2.455194"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011"); + values ( "0.428385, 0.661739, 0.847373, 1.147163, 1.728050",\ + "0.460631, 0.693986, 0.879619, 1.179409, 1.760296",\ + "0.510947, 0.744302, 0.929935, 1.229725, 1.810612",\ + "0.671611, 0.904965, 1.090599, 1.390389, 1.971276",\ + "1.252728, 1.486083, 1.671717, 1.971507, 2.552392",\ + "0.516791, 0.749058, 0.934654, 1.234468, 1.815403",\ + "0.549037, 0.781304, 0.966900, 1.266714, 1.847649",\ + "0.599353, 0.831620, 1.017216, 1.317030, 1.897965",\ + "0.760017, 0.992284, 1.177880, 1.477694, 2.058629",\ + "1.341134, 1.573402, 1.758998, 2.058812, 2.639746",\ + "0.605868, 0.829393, 1.014680, 1.314497, 1.895434",\ + "0.638114, 0.861639, 1.046927, 1.346743, 1.927681",\ + "0.688430, 0.911955, 1.097243, 1.397059, 1.977997",\ + "0.849094, 1.072619, 1.257906, 1.557723, 2.138661",\ + "1.430211, 1.653737, 1.839025, 2.138841, 2.719778",\ + "0.669132, 0.887224, 1.072391, 1.371951, 1.952498",\ + "0.701378, 0.919471, 1.104638, 1.404197, 1.984744",\ + "0.751694, 0.969786, 1.154953, 1.454513, 2.035060",\ + "0.912358, 1.130450, 1.315617, 1.615177, 2.195724",\ + "1.493475, 1.711568, 1.896736, 2.196295, 2.776841",\ + "1.003122, 1.192555, 1.376050, 1.675143, 2.254777",\ + "1.035368, 1.224802, 1.408297, 1.707390, 2.287024",\ + "1.085684, 1.275118, 1.458613, 1.757706, 2.337340",\ + "1.246348, 1.435782, 1.619277, 1.918369, 2.498003",\ + "1.827465, 2.016899, 2.200395, 2.499487, 3.079121"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011"); + values ( "0.029703, 0.029703, 0.029703, 0.029704, 0.029704",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\ + "0.419470, 0.419470, 0.419470, 0.419470, 0.419470",\ + "1.483040, 1.483040, 1.483040, 1.483042, 1.483046",\ + "0.029703, 0.029703, 0.029703, 0.029704, 0.029704",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\ + "0.419470, 0.419470, 0.419470, 0.419470, 0.419470",\ + "1.483040, 1.483040, 1.483040, 1.483042, 1.483046",\ + "0.029703, 0.029703, 0.029703, 0.029704, 0.029704",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\ + "0.419470, 0.419470, 0.419470, 0.419470, 0.419470",\ + "1.483040, 1.483040, 1.483040, 1.483042, 1.483046",\ + "0.029703, 0.029703, 0.029703, 0.029704, 0.029704",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\ + "0.419470, 0.419470, 0.419470, 0.419470, 0.419470",\ + "1.483040, 1.483040, 1.483040, 1.483042, 1.483046",\ + "0.029703, 0.029703, 0.029703, 0.029704, 0.029704",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\ + "0.419470, 0.419470, 0.419470, 0.419470, 0.419470",\ + "1.483040, 1.483040, 1.483040, 1.483042, 1.483047"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_min_2478*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[17]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011"); + values ( "0.516812, 0.720433, 0.930283, 1.259401, 1.891051",\ + "0.558535, 0.762156, 0.972006, 1.301124, 1.932775",\ + "0.634601, 0.838222, 1.048072, 1.377190, 2.008840",\ + "0.890090, 1.093710, 1.303558, 1.632676, 2.264330",\ + "1.814399, 2.018020, 2.227869, 2.556987, 3.188638",\ + "0.605540, 0.807752, 1.017564, 1.346706, 1.978405",\ + "0.647263, 0.849475, 1.059287, 1.388429, 2.020128",\ + "0.723329, 0.925541, 1.135353, 1.464495, 2.096194",\ + "0.978818, 1.181028, 1.390838, 1.719981, 2.351683",\ + "1.903127, 2.105338, 2.315150, 2.644292, 3.275992",\ + "0.695187, 0.888089, 1.097591, 1.426734, 2.058436",\ + "0.736910, 0.929812, 1.139314, 1.468457, 2.100160",\ + "0.812976, 1.005878, 1.215380, 1.544523, 2.176225",\ + "1.068465, 1.261366, 1.470865, 1.800010, 2.431715",\ + "1.992774, 2.185676, 2.395177, 2.724321, 3.356023",\ + "0.755223, 0.945959, 1.155358, 1.484250, 2.115621",\ + "0.796946, 0.987682, 1.197081, 1.525973, 2.157344",\ + "0.873011, 1.063748, 1.273147, 1.602039, 2.233410",\ + "1.128500, 1.319236, 1.528632, 1.857525, 2.488900",\ + "2.052809, 2.243546, 2.452944, 2.781836, 3.413208",\ + "1.058034, 1.251576, 1.459026, 1.787495, 2.418047",\ + "1.099757, 1.293299, 1.500749, 1.829218, 2.459770",\ + "1.175823, 1.369365, 1.576815, 1.905284, 2.535836",\ + "1.431312, 1.624853, 1.832301, 2.160770, 2.791326",\ + "2.355621, 2.549163, 2.756612, 3.085082, 3.715634"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011"); + values ( "0.025354, 0.025354, 0.025354, 0.025354, 0.025354",\ + "0.070228, 0.070228, 0.070228, 0.070228, 0.070228",\ + "0.199485, 0.199485, 0.199485, 0.199486, 0.199488",\ + "0.686680, 0.686680, 0.686680, 0.686680, 0.686680",\ + "2.452500, 2.452500, 2.452512, 2.452522, 2.452533",\ + "0.025354, 0.025354, 0.025354, 0.025354, 0.025354",\ + "0.070228, 0.070228, 0.070228, 0.070228, 0.070228",\ + "0.199485, 0.199485, 0.199485, 0.199486, 0.199488",\ + "0.686680, 0.686680, 0.686680, 0.686680, 0.686680",\ + "2.452500, 2.452500, 2.452512, 2.452522, 2.452533",\ + "0.025354, 0.025354, 0.025354, 0.025354, 0.025354",\ + "0.070228, 0.070228, 0.070228, 0.070228, 0.070228",\ + "0.199485, 0.199485, 0.199485, 0.199486, 0.199488",\ + "0.686680, 0.686680, 0.686680, 0.686680, 0.686680",\ + "2.452500, 2.452500, 2.452512, 2.452522, 2.452533",\ + "0.025354, 0.025354, 0.025354, 0.025354, 0.025354",\ + "0.070228, 0.070228, 0.070228, 0.070228, 0.070228",\ + "0.199485, 0.199485, 0.199485, 0.199486, 0.199488",\ + "0.686680, 0.686680, 0.686680, 0.686680, 0.686680",\ + "2.452500, 2.452500, 2.452512, 2.452522, 2.452533",\ + "0.025354, 0.025354, 0.025354, 0.025354, 0.025354",\ + "0.070228, 0.070228, 0.070228, 0.070228, 0.070228",\ + "0.199485, 0.199485, 0.199485, 0.199486, 0.199488",\ + "0.686680, 0.686680, 0.686680, 0.686680, 0.686680",\ + "2.452500, 2.452500, 2.452512, 2.452522, 2.452533"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011"); + values ( "0.539402, 0.743023, 0.952873, 1.281991, 1.913641",\ + "0.571427, 0.775047, 0.984897, 1.314015, 1.945666",\ + "0.621835, 0.825456, 1.035306, 1.364424, 1.996074",\ + "0.782894, 0.986516, 1.196367, 1.525485, 2.157133",\ + "1.362868, 1.566489, 1.776340, 2.105458, 2.737106",\ + "0.628130, 0.830342, 1.040154, 1.369296, 2.000995",\ + "0.660155, 0.862366, 1.072178, 1.401320, 2.033020",\ + "0.710563, 0.912774, 1.122587, 1.451729, 2.083427",\ + "0.871623, 1.073835, 1.283648, 1.612790, 2.244487",\ + "1.451596, 1.653808, 1.863621, 2.192763, 2.824460",\ + "0.717777, 0.910679, 1.120180, 1.449324, 2.081027",\ + "0.749802, 0.942704, 1.152205, 1.481349, 2.113051",\ + "0.800210, 0.993112, 1.202614, 1.531757, 2.163459",\ + "0.961270, 1.154172, 1.363675, 1.692818, 2.324518",\ + "1.541243, 1.734145, 1.943648, 2.272791, 2.904491",\ + "0.777813, 0.968549, 1.177947, 1.506840, 2.138211",\ + "0.809837, 1.000574, 1.209971, 1.538864, 2.170236",\ + "0.860245, 1.050982, 1.260381, 1.589273, 2.220644",\ + "1.021305, 1.212042, 1.421442, 1.750333, 2.381703",\ + "1.601278, 1.792015, 2.001415, 2.330307, 2.961676",\ + "1.080624, 1.274166, 1.481616, 1.810085, 2.440637",\ + "1.112649, 1.306190, 1.513640, 1.842109, 2.472662",\ + "1.163057, 1.356599, 1.564049, 1.892518, 2.523069",\ + "1.324117, 1.517659, 1.725110, 2.053579, 2.684129",\ + "1.904090, 2.097632, 2.305083, 2.633552, 3.264102"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011"); + values ( "0.029862, 0.029862, 0.029862, 0.029862, 0.029862",\ + "0.059266, 0.059266, 0.059266, 0.059267, 0.059267",\ + "0.131512, 0.131512, 0.131512, 0.131512, 0.131513",\ + "0.417796, 0.417796, 0.417800, 0.417803, 0.417807",\ + "1.484511, 1.484511, 1.484513, 1.484514, 1.484517",\ + "0.029862, 0.029862, 0.029862, 0.029862, 0.029862",\ + "0.059266, 0.059266, 0.059266, 0.059267, 0.059267",\ + "0.131512, 0.131512, 0.131512, 0.131512, 0.131513",\ + "0.417796, 0.417796, 0.417800, 0.417803, 0.417807",\ + "1.484511, 1.484511, 1.484513, 1.484514, 1.484517",\ + "0.029862, 0.029862, 0.029862, 0.029862, 0.029862",\ + "0.059266, 0.059266, 0.059266, 0.059267, 0.059267",\ + "0.131512, 0.131512, 0.131512, 0.131512, 0.131513",\ + "0.417796, 0.417796, 0.417800, 0.417803, 0.417807",\ + "1.484511, 1.484511, 1.484513, 1.484514, 1.484517",\ + "0.029862, 0.029862, 0.029862, 0.029862, 0.029862",\ + "0.059266, 0.059266, 0.059266, 0.059267, 0.059267",\ + "0.131512, 0.131512, 0.131512, 0.131512, 0.131513",\ + "0.417796, 0.417796, 0.417800, 0.417803, 0.417807",\ + "1.484511, 1.484511, 1.484513, 1.484514, 1.484517",\ + "0.029862, 0.029862, 0.029862, 0.029862, 0.029862",\ + "0.059266, 0.059266, 0.059266, 0.059267, 0.059267",\ + "0.131512, 0.131512, 0.131512, 0.131512, 0.131513",\ + "0.417796, 0.417796, 0.417800, 0.417803, 0.417807",\ + "1.484511, 1.484511, 1.484513, 1.484514, 1.484517"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_min_2528*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[19]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011"); + values ( "0.343347, 0.560733, 0.738878, 1.027873, 1.588767",\ + "0.376901, 0.594286, 0.772429, 1.061825, 1.623703",\ + "0.447931, 0.665317, 0.843465, 1.132863, 1.694739",\ + "0.702775, 0.920161, 1.098308, 1.387706, 1.949584",\ + "1.627697, 1.845075, 2.023177, 2.312590, 2.874544",\ + "0.431725, 0.648051, 0.826159, 1.115178, 1.676121",\ + "0.465279, 0.681604, 0.859710, 1.149130, 1.711057",\ + "0.536309, 0.752636, 0.930746, 1.220168, 1.782093",\ + "0.791152, 1.007479, 1.185589, 1.475011, 2.036938",\ + "1.716075, 1.932394, 2.110458, 2.399895, 2.961898",\ + "0.521054, 0.728383, 0.906186, 1.195207, 1.756152",\ + "0.554608, 0.761937, 0.939737, 1.229159, 1.791088",\ + "0.625638, 0.832968, 1.010773, 1.300196, 1.862124",\ + "0.880482, 1.087811, 1.265616, 1.555040, 2.116970",\ + "1.805404, 2.012726, 2.190485, 2.479923, 3.041929",\ + "0.584699, 0.786201, 0.963880, 1.252637, 1.813169",\ + "0.618252, 0.819754, 0.997431, 1.286590, 1.848107",\ + "0.689283, 0.890786, 1.068467, 1.357627, 1.919143",\ + "0.944126, 1.145629, 1.323310, 1.612471, 2.173989",\ + "1.869048, 2.070544, 2.248179, 2.537354, 3.098948",\ + "0.912898, 1.091426, 1.267535, 1.555809, 2.115392",\ + "0.946452, 1.124980, 1.301087, 1.589763, 2.150333",\ + "1.017482, 1.196011, 1.372123, 1.660800, 2.221369",\ + "1.272326, 1.450854, 1.626966, 1.915644, 2.476214",\ + "2.197247, 2.375769, 2.551834, 2.840528, 3.401175"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011"); + values ( "0.023744, 0.023744, 0.023744, 0.023744, 0.023744",\ + "0.069296, 0.069296, 0.069296, 0.069296, 0.069296",\ + "0.200223, 0.200225, 0.200229, 0.200251, 0.200303",\ + "0.685855, 0.685857, 0.685864, 0.685915, 0.686035",\ + "2.446888, 2.446896, 2.446897, 2.446897, 2.446897",\ + "0.023744, 0.023744, 0.023744, 0.023744, 0.023744",\ + "0.069296, 0.069296, 0.069296, 0.069296, 0.069296",\ + "0.200223, 0.200225, 0.200229, 0.200251, 0.200303",\ + "0.685855, 0.685857, 0.685864, 0.685915, 0.686035",\ + "2.446888, 2.446896, 2.446897, 2.446897, 2.446897",\ + "0.023744, 0.023744, 0.023744, 0.023744, 0.023744",\ + "0.069296, 0.069296, 0.069296, 0.069296, 0.069296",\ + "0.200223, 0.200225, 0.200229, 0.200251, 0.200303",\ + "0.685855, 0.685857, 0.685864, 0.685915, 0.686035",\ + "2.446889, 2.446896, 2.446897, 2.446897, 2.446897",\ + "0.023744, 0.023744, 0.023744, 0.023744, 0.023744",\ + "0.069296, 0.069296, 0.069296, 0.069296, 0.069296",\ + "0.200223, 0.200225, 0.200229, 0.200251, 0.200303",\ + "0.685855, 0.685857, 0.685864, 0.685915, 0.686035",\ + "2.446889, 2.446896, 2.446897, 2.446897, 2.446897",\ + "0.023744, 0.023744, 0.023744, 0.023744, 0.023744",\ + "0.069296, 0.069296, 0.069296, 0.069296, 0.069296",\ + "0.200223, 0.200225, 0.200229, 0.200251, 0.200303",\ + "0.685855, 0.685857, 0.685864, 0.685915, 0.686035",\ + "2.446889, 2.446896, 2.446897, 2.446897, 2.446897"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011"); + values ( "0.337578, 0.554964, 0.733111, 1.022508, 1.584385",\ + "0.369918, 0.587304, 0.765454, 1.054853, 1.616734",\ + "0.420270, 0.637656, 0.815804, 1.105202, 1.667081",\ + "0.581348, 0.798734, 0.976881, 1.266279, 1.828157",\ + "1.161863, 1.379232, 1.557282, 1.846629, 2.408468",\ + "0.425956, 0.642282, 0.820392, 1.109813, 1.671738",\ + "0.458296, 0.674622, 0.852735, 1.142159, 1.704088",\ + "0.508648, 0.724974, 0.903085, 1.192507, 1.754434",\ + "0.669726, 0.886052, 1.064162, 1.353584, 1.915510",\ + "1.250240, 1.466550, 1.644563, 1.933934, 2.495822",\ + "0.515285, 0.722614, 0.900419, 1.189842, 1.751770",\ + "0.547625, 0.754955, 0.932762, 1.222187, 1.784119",\ + "0.597977, 0.805307, 0.983111, 1.272535, 1.834466",\ + "0.759055, 0.966385, 1.144189, 1.433612, 1.995542",\ + "1.339568, 1.546883, 1.724590, 2.013963, 2.575853",\ + "0.578929, 0.780432, 0.958113, 1.247273, 1.808789",\ + "0.611270, 0.812772, 0.990456, 1.279618, 1.841138",\ + "0.661622, 0.863124, 1.040806, 1.329967, 1.891485",\ + "0.822700, 1.024202, 1.201883, 1.491044, 2.052561",\ + "1.403211, 1.604700, 1.782284, 2.071394, 2.632872",\ + "0.907129, 1.085657, 1.261768, 1.550446, 2.111014",\ + "0.939469, 1.117998, 1.294111, 1.582791, 2.143364",\ + "0.989821, 1.168350, 1.344461, 1.633139, 2.193710",\ + "1.150899, 1.329427, 1.505538, 1.794216, 2.354787",\ + "1.731412, 1.909925, 2.085939, 2.374567, 2.935098"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011"); + values ( "0.030095, 0.030094, 0.030093, 0.030093, 0.030093",\ + "0.059305, 0.059302, 0.059288, 0.059276, 0.059261",\ + "0.131696, 0.131694, 0.131680, 0.131669, 0.131651",\ + "0.419114, 0.419122, 0.419145, 0.419266, 0.419546",\ + "1.483332, 1.483297, 1.483098, 1.482941, 1.482729",\ + "0.030095, 0.030094, 0.030093, 0.030093, 0.030093",\ + "0.059305, 0.059302, 0.059288, 0.059276, 0.059261",\ + "0.131696, 0.131694, 0.131680, 0.131669, 0.131651",\ + "0.419115, 0.419122, 0.419145, 0.419266, 0.419546",\ + "1.483331, 1.483297, 1.483098, 1.482941, 1.482729",\ + "0.030095, 0.030094, 0.030093, 0.030093, 0.030093",\ + "0.059305, 0.059302, 0.059288, 0.059276, 0.059261",\ + "0.131696, 0.131694, 0.131680, 0.131669, 0.131651",\ + "0.419115, 0.419122, 0.419145, 0.419266, 0.419546",\ + "1.483328, 1.483297, 1.483098, 1.482941, 1.482729",\ + "0.030095, 0.030094, 0.030093, 0.030093, 0.030093",\ + "0.059304, 0.059302, 0.059288, 0.059276, 0.059261",\ + "0.131695, 0.131694, 0.131680, 0.131668, 0.131651",\ + "0.419116, 0.419122, 0.419145, 0.419267, 0.419547",\ + "1.483325, 1.483297, 1.483097, 1.482941, 1.482729",\ + "0.030095, 0.030094, 0.030093, 0.030093, 0.030093",\ + "0.059305, 0.059302, 0.059288, 0.059276, 0.059260",\ + "0.131696, 0.131694, 0.131680, 0.131668, 0.131651",\ + "0.419115, 0.419122, 0.419145, 0.419267, 0.419548",\ + "1.483327, 1.483296, 1.483097, 1.482941, 1.482728"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_min_2593*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[20]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.254656, 0.491006, 0.681199, 0.986728, 1.577708",\ + "0.288244, 0.524620, 0.714843, 1.020374, 1.611331",\ + "0.359123, 0.595519, 0.785873, 1.091419, 1.682284",\ + "0.614167, 0.850282, 1.040808, 1.346411, 1.937248",\ + "1.539512, 1.774279, 1.968056, 2.274137, 2.863164",\ + "0.343150, 0.578325, 0.768480, 1.074033, 1.665062",\ + "0.376740, 0.611939, 0.802124, 1.107679, 1.698684",\ + "0.447618, 0.682838, 0.873154, 1.178725, 1.769638",\ + "0.702665, 0.937601, 1.128089, 1.433716, 2.024602",\ + "1.628026, 1.861597, 2.055336, 2.361442, 2.950518",\ + "0.432477, 0.658660, 0.848507, 1.154062, 1.745093",\ + "0.466070, 0.692274, 0.882150, 1.187708, 1.778716",\ + "0.536949, 0.763173, 0.953181, 1.258753, 1.849669",\ + "0.792003, 1.017936, 1.208116, 1.513744, 2.104633",\ + "1.717412, 1.941932, 2.135364, 2.441470, 3.030550",\ + "0.495969, 0.716495, 0.906228, 1.211528, 1.802181",\ + "0.529564, 0.750109, 0.939872, 1.245174, 1.835804",\ + "0.600443, 0.821007, 1.010903, 1.316219, 1.906757",\ + "0.855505, 1.075769, 1.265838, 1.571210, 2.161721",\ + "1.780957, 1.999760, 2.193094, 2.498934, 3.087633",\ + "0.831401, 1.021856, 1.209889, 1.514732, 2.104490",\ + "0.865014, 1.055469, 1.243533, 1.548377, 2.138113",\ + "0.935893, 1.126362, 1.314564, 1.619422, 2.209066",\ + "1.191001, 1.381117, 1.569499, 1.874413, 2.464029",\ + "2.116730, 2.305066, 2.496756, 2.802135, 3.389936"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.023821, 0.023821, 0.023821, 0.023833, 0.023862",\ + "0.069303, 0.069303, 0.069342, 0.069357, 0.069357",\ + "0.199561, 0.199561, 0.199561, 0.199561, 0.199561",\ + "0.684891, 0.684891, 0.685011, 0.685055, 0.685055",\ + "2.453468, 2.453468, 2.454035, 2.454504, 2.455152",\ + "0.023821, 0.023821, 0.023821, 0.023833, 0.023862",\ + "0.069303, 0.069303, 0.069342, 0.069357, 0.069357",\ + "0.199561, 0.199561, 0.199561, 0.199561, 0.199561",\ + "0.684891, 0.684891, 0.685011, 0.685055, 0.685055",\ + "2.453468, 2.453468, 2.454035, 2.454504, 2.455152",\ + "0.023821, 0.023821, 0.023821, 0.023833, 0.023862",\ + "0.069303, 0.069303, 0.069342, 0.069357, 0.069357",\ + "0.199561, 0.199561, 0.199561, 0.199561, 0.199561",\ + "0.684891, 0.684891, 0.685011, 0.685055, 0.685055",\ + "2.453468, 2.453468, 2.454035, 2.454504, 2.455152",\ + "0.023821, 0.023821, 0.023821, 0.023833, 0.023862",\ + "0.069303, 0.069303, 0.069343, 0.069357, 0.069357",\ + "0.199561, 0.199561, 0.199561, 0.199561, 0.199561",\ + "0.684891, 0.684891, 0.685012, 0.685055, 0.685055",\ + "2.453468, 2.453468, 2.454036, 2.454505, 2.455154",\ + "0.023821, 0.023821, 0.023821, 0.023833, 0.023862",\ + "0.069303, 0.069303, 0.069343, 0.069357, 0.069357",\ + "0.199561, 0.199561, 0.199561, 0.199561, 0.199561",\ + "0.684891, 0.684891, 0.685012, 0.685055, 0.685055",\ + "2.453468, 2.453468, 2.454036, 2.454506, 2.455156"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.249454, 0.486004, 0.675967, 0.981250, 1.571825",\ + "0.281865, 0.518328, 0.708344, 1.013662, 1.604275",\ + "0.332260, 0.568655, 0.758650, 1.063988, 1.654672",\ + "0.493098, 0.729544, 0.919296, 1.224627, 1.815523",\ + "1.073988, 1.310152, 1.500044, 1.805268, 2.395687",\ + "0.337933, 0.573322, 0.763248, 1.068555, 1.659178",\ + "0.370344, 0.605646, 0.795625, 1.100967, 1.691628",\ + "0.420740, 0.655974, 0.845931, 1.151293, 1.742025",\ + "0.581582, 0.816862, 1.006577, 1.311932, 1.902877",\ + "1.162485, 1.397470, 1.587325, 1.892573, 2.483041",\ + "0.427218, 0.653657, 0.843275, 1.148583, 1.739210",\ + "0.459630, 0.685981, 0.875652, 1.180995, 1.771660",\ + "0.510027, 0.736309, 0.925958, 1.231322, 1.822057",\ + "0.670883, 0.897197, 1.086604, 1.391961, 1.982908",\ + "1.251823, 1.477805, 1.667352, 1.972602, 2.563072",\ + "0.490671, 0.711493, 0.900996, 1.206049, 1.796297",\ + "0.523083, 0.743816, 0.933373, 1.238461, 1.828747",\ + "0.573482, 0.794144, 0.983679, 1.288787, 1.879144",\ + "0.734351, 0.955034, 1.144324, 1.449427, 2.039996",\ + "1.315324, 1.535635, 1.725073, 2.030067, 2.620159",\ + "0.825858, 1.016851, 1.204656, 1.509252, 2.098604",\ + "0.858274, 1.049176, 1.237034, 1.541664, 2.131054",\ + "0.908682, 1.099504, 1.287340, 1.591990, 2.181452",\ + "1.069631, 1.260400, 1.447985, 1.752630, 2.342305",\ + "1.650816, 1.840953, 2.028734, 2.333270, 2.922466"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.030092, 0.030092, 0.030092, 0.030170, 0.030363",\ + "0.059437, 0.059437, 0.059437, 0.059474, 0.059565",\ + "0.131608, 0.131608, 0.131661, 0.131712, 0.131790",\ + "0.417862, 0.417862, 0.417862, 0.417989, 0.418302",\ + "1.478309, 1.478309, 1.478309, 1.478309, 1.478309",\ + "0.030092, 0.030092, 0.030092, 0.030170, 0.030363",\ + "0.059437, 0.059437, 0.059437, 0.059474, 0.059565",\ + "0.131608, 0.131608, 0.131661, 0.131712, 0.131790",\ + "0.417862, 0.417862, 0.417862, 0.417989, 0.418302",\ + "1.478309, 1.478309, 1.478309, 1.478309, 1.478309",\ + "0.030092, 0.030092, 0.030092, 0.030170, 0.030363",\ + "0.059437, 0.059437, 0.059437, 0.059474, 0.059565",\ + "0.131608, 0.131608, 0.131661, 0.131712, 0.131790",\ + "0.417862, 0.417862, 0.417862, 0.417989, 0.418302",\ + "1.478309, 1.478309, 1.478309, 1.478309, 1.478309",\ + "0.030092, 0.030092, 0.030092, 0.030170, 0.030363",\ + "0.059437, 0.059437, 0.059437, 0.059474, 0.059565",\ + "0.131608, 0.131608, 0.131661, 0.131712, 0.131790",\ + "0.417862, 0.417862, 0.417862, 0.417990, 0.418303",\ + "1.478309, 1.478309, 1.478309, 1.478309, 1.478309",\ + "0.030092, 0.030092, 0.030092, 0.030170, 0.030364",\ + "0.059437, 0.059437, 0.059437, 0.059474, 0.059565",\ + "0.131608, 0.131608, 0.131661, 0.131712, 0.131790",\ + "0.417862, 0.417862, 0.417862, 0.417990, 0.418303",\ + "1.478309, 1.478309, 1.478309, 1.478309, 1.478309"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_min_2636*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[21]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011"); + values ( "0.325472, 0.549886, 0.736679, 1.035269, 1.612348",\ + "0.359026, 0.583502, 0.770294, 1.068882, 1.645956",\ + "0.430054, 0.654527, 0.841316, 1.139890, 1.716933",\ + "0.684897, 0.909477, 1.096261, 1.394816, 1.971817",\ + "1.609849, 1.835494, 2.022258, 2.320729, 2.897541",\ + "0.413759, 0.637204, 0.823960, 1.122574, 1.699702",\ + "0.447318, 0.670820, 0.857575, 1.156187, 1.733310",\ + "0.518346, 0.741845, 0.928597, 1.227195, 1.804287",\ + "0.773189, 0.996795, 1.183542, 1.482121, 2.059171",\ + "1.698136, 1.922812, 2.109539, 2.408034, 2.984894",\ + "0.503271, 0.717533, 0.903987, 1.202602, 1.779733",\ + "0.536839, 0.751148, 0.937602, 1.236216, 1.813341",\ + "0.607869, 0.822173, 1.008624, 1.307223, 1.884319",\ + "0.862712, 1.077123, 1.263569, 1.562150, 2.139202",\ + "1.787644, 2.003140, 2.189566, 2.488062, 3.064926",\ + "0.567278, 0.775354, 0.961702, 1.260053, 1.836791",\ + "0.600857, 0.808970, 0.995318, 1.293666, 1.870399",\ + "0.671888, 0.879995, 1.066339, 1.364674, 1.941376",\ + "0.926731, 1.134945, 1.321284, 1.619600, 2.196259",\ + "1.851648, 2.060962, 2.247281, 2.545512, 3.121983",\ + "0.902611, 1.080594, 1.265360, 1.563241, 2.139063",\ + "0.936228, 1.114210, 1.298975, 1.596854, 2.172671",\ + "1.007260, 1.185235, 1.369997, 1.667862, 2.243648",\ + "1.262219, 1.440184, 1.624942, 1.922788, 2.498532",\ + "2.188276, 2.366200, 2.550939, 2.848700, 3.424254"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011"); + values ( "0.023797, 0.023797, 0.023797, 0.023789, 0.023770",\ + "0.069301, 0.069300, 0.069300, 0.069299, 0.069296",\ + "0.200200, 0.200200, 0.200200, 0.200200, 0.200200",\ + "0.685818, 0.685818, 0.685818, 0.685818, 0.685818",\ + "2.446848, 2.446711, 2.446702, 2.446700, 2.446699",\ + "0.023797, 0.023797, 0.023797, 0.023789, 0.023770",\ + "0.069301, 0.069300, 0.069300, 0.069299, 0.069296",\ + "0.200200, 0.200200, 0.200200, 0.200200, 0.200200",\ + "0.685818, 0.685818, 0.685818, 0.685818, 0.685818",\ + "2.446844, 2.446711, 2.446702, 2.446700, 2.446699",\ + "0.023797, 0.023797, 0.023797, 0.023789, 0.023770",\ + "0.069301, 0.069300, 0.069300, 0.069299, 0.069296",\ + "0.200200, 0.200200, 0.200200, 0.200200, 0.200200",\ + "0.685818, 0.685818, 0.685818, 0.685818, 0.685818",\ + "2.446834, 2.446711, 2.446702, 2.446700, 2.446699",\ + "0.023797, 0.023797, 0.023797, 0.023789, 0.023770",\ + "0.069301, 0.069300, 0.069300, 0.069299, 0.069296",\ + "0.200200, 0.200200, 0.200200, 0.200200, 0.200200",\ + "0.685818, 0.685818, 0.685818, 0.685818, 0.685818",\ + "2.446823, 2.446710, 2.446702, 2.446700, 2.446699",\ + "0.023797, 0.023797, 0.023797, 0.023789, 0.023770",\ + "0.069301, 0.069300, 0.069300, 0.069299, 0.069296",\ + "0.200200, 0.200200, 0.200200, 0.200200, 0.200200",\ + "0.685818, 0.685818, 0.685818, 0.685818, 0.685818",\ + "2.446830, 2.446707, 2.446702, 2.446700, 2.446699"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011"); + values ( "0.319701, 0.545442, 0.732220, 1.030751, 1.607697",\ + "0.352039, 0.577906, 0.764685, 1.063221, 1.640180",\ + "0.402393, 0.628225, 0.815004, 1.113542, 1.690503",\ + "0.563471, 0.788964, 0.975744, 1.274281, 1.851241",\ + "1.144048, 1.371915, 1.558729, 1.857404, 2.434677",\ + "0.407993, 0.632759, 0.819501, 1.118056, 1.695051",\ + "0.440331, 0.665224, 0.851966, 1.150527, 1.727533",\ + "0.490684, 0.715542, 0.902285, 1.200847, 1.777857",\ + "0.651763, 0.876282, 1.063025, 1.361586, 1.938595",\ + "1.232329, 1.459233, 1.646010, 1.944710, 2.522030",\ + "0.497516, 0.713088, 0.899528, 1.198085, 1.775082",\ + "0.529855, 0.745552, 0.931993, 1.230555, 1.807565",\ + "0.580208, 0.795871, 0.982312, 1.280875, 1.857888",\ + "0.741286, 0.956611, 1.143052, 1.441614, 2.018626",\ + "1.321819, 1.539562, 1.726037, 2.024738, 2.602062",\ + "0.561534, 0.770909, 0.957244, 1.255535, 1.832140",\ + "0.593874, 0.803374, 0.989709, 1.288005, 1.864622",\ + "0.644226, 0.853692, 1.040028, 1.338326, 1.914946",\ + "0.805304, 1.014432, 1.200767, 1.499064, 2.075684",\ + "1.385806, 1.597383, 1.783752, 2.082189, 2.659120",\ + "0.898194, 1.076148, 1.260901, 1.558723, 2.134412",\ + "0.930657, 1.108613, 1.293366, 1.591193, 2.166894",\ + "0.980975, 1.158931, 1.343685, 1.641514, 2.217218",\ + "1.141715, 1.319671, 1.504425, 1.802253, 2.377955",\ + "1.724358, 1.902624, 2.087410, 2.385377, 2.961392"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011"); + values ( "0.030095, 0.030095, 0.030095, 0.030095, 0.030095",\ + "0.059314, 0.059250, 0.059241, 0.059238, 0.059238",\ + "0.131704, 0.131646, 0.131637, 0.131633, 0.131629",\ + "0.418989, 0.418989, 0.418989, 0.418989, 0.418989",\ + "1.483458, 1.482592, 1.482500, 1.482470, 1.482449",\ + "0.030095, 0.030095, 0.030095, 0.030095, 0.030095",\ + "0.059313, 0.059250, 0.059241, 0.059238, 0.059238",\ + "0.131703, 0.131646, 0.131637, 0.131633, 0.131629",\ + "0.418989, 0.418989, 0.418989, 0.418989, 0.418989",\ + "1.483437, 1.482592, 1.482500, 1.482470, 1.482449",\ + "0.030095, 0.030095, 0.030095, 0.030095, 0.030095",\ + "0.059308, 0.059250, 0.059241, 0.059238, 0.059238",\ + "0.131698, 0.131646, 0.131637, 0.131633, 0.131629",\ + "0.418989, 0.418989, 0.418989, 0.418989, 0.418989",\ + "1.483369, 1.482592, 1.482500, 1.482470, 1.482449",\ + "0.030095, 0.030095, 0.030095, 0.030095, 0.030095",\ + "0.059303, 0.059250, 0.059241, 0.059238, 0.059238",\ + "0.131694, 0.131646, 0.131637, 0.131633, 0.131629",\ + "0.418989, 0.418989, 0.418989, 0.418989, 0.418989",\ + "1.483305, 1.482589, 1.482500, 1.482470, 1.482449",\ + "0.030095, 0.030095, 0.030095, 0.030095, 0.030095",\ + "0.059306, 0.059248, 0.059241, 0.059238, 0.059238",\ + "0.131697, 0.131645, 0.131637, 0.131633, 0.131629",\ + "0.418989, 0.418989, 0.418989, 0.418989, 0.418989",\ + "1.482893, 1.482566, 1.482500, 1.482470, 1.482448"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_min_2688*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[25]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011"); + values ( "0.402084, 0.617885, 0.797210, 1.086950, 1.648801",\ + "0.443807, 0.659608, 0.838933, 1.128673, 1.690524",\ + "0.519872, 0.735673, 0.914998, 1.204739, 1.766590",\ + "0.775363, 0.991161, 1.170488, 1.460228, 2.022074",\ + "1.699671, 1.915471, 2.094797, 2.384537, 2.946387",\ + "0.490367, 0.705202, 0.884491, 1.174255, 1.736155",\ + "0.532090, 0.746925, 0.926214, 1.215978, 1.777877",\ + "0.608155, 0.822991, 1.002279, 1.292044, 1.853944",\ + "0.863645, 1.078479, 1.257769, 1.547533, 2.109427",\ + "1.787954, 2.002789, 2.182077, 2.471842, 3.033741",\ + "0.579657, 0.785533, 0.964518, 1.254284, 1.816186",\ + "0.621380, 0.827256, 1.006241, 1.296007, 1.857909",\ + "0.697445, 0.903322, 1.082306, 1.372073, 1.933975",\ + "0.952935, 1.158809, 1.337796, 1.627561, 2.189459",\ + "1.877244, 2.083119, 2.262105, 2.551871, 3.113772",\ + "0.643368, 0.843363, 1.022215, 1.311715, 1.873206",\ + "0.685091, 0.885086, 1.063938, 1.353438, 1.914929",\ + "0.761157, 0.961152, 1.140003, 1.429504, 1.990995",\ + "1.016647, 1.216639, 1.395493, 1.684993, 2.246479",\ + "1.940955, 2.140950, 2.319802, 2.609302, 3.170792",\ + "0.967924, 1.148670, 1.325870, 1.614888, 2.175433",\ + "1.009647, 1.190393, 1.367593, 1.656611, 2.217156",\ + "1.085713, 1.266459, 1.443658, 1.732677, 2.293222",\ + "1.341202, 1.521946, 1.699148, 1.988165, 2.548706",\ + "2.265511, 2.446256, 2.623457, 2.912475, 3.473019"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011"); + values ( "0.025354, 0.025353, 0.025353, 0.025353, 0.025352",\ + "0.070228, 0.070228, 0.070228, 0.070228, 0.070228",\ + "0.199488, 0.199487, 0.199487, 0.199486, 0.199483",\ + "0.686687, 0.686687, 0.686686, 0.686686, 0.686686",\ + "2.452523, 2.452519, 2.452519, 2.452513, 2.452498",\ + "0.025354, 0.025353, 0.025353, 0.025353, 0.025352",\ + "0.070228, 0.070228, 0.070228, 0.070228, 0.070228",\ + "0.199488, 0.199487, 0.199487, 0.199486, 0.199483",\ + "0.686687, 0.686687, 0.686686, 0.686686, 0.686686",\ + "2.452523, 2.452519, 2.452519, 2.452513, 2.452498",\ + "0.025354, 0.025353, 0.025353, 0.025353, 0.025352",\ + "0.070228, 0.070228, 0.070228, 0.070228, 0.070228",\ + "0.199487, 0.199487, 0.199487, 0.199486, 0.199483",\ + "0.686687, 0.686687, 0.686686, 0.686686, 0.686686",\ + "2.452523, 2.452519, 2.452519, 2.452513, 2.452498",\ + "0.025354, 0.025353, 0.025353, 0.025353, 0.025352",\ + "0.070228, 0.070228, 0.070228, 0.070228, 0.070228",\ + "0.199487, 0.199487, 0.199487, 0.199486, 0.199483",\ + "0.686687, 0.686687, 0.686686, 0.686686, 0.686686",\ + "2.452523, 2.452519, 2.452519, 2.452513, 2.452498",\ + "0.025354, 0.025353, 0.025353, 0.025353, 0.025352",\ + "0.070228, 0.070228, 0.070228, 0.070228, 0.070228",\ + "0.199487, 0.199487, 0.199487, 0.199486, 0.199483",\ + "0.686687, 0.686687, 0.686686, 0.686686, 0.686686",\ + "2.452523, 2.452519, 2.452519, 2.452513, 2.452498"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011"); + values ( "0.424674, 0.640474, 0.819800, 1.109540, 1.671391",\ + "0.456699, 0.672499, 0.851824, 1.141565, 1.703415",\ + "0.507106, 0.722907, 0.902232, 1.191973, 1.753824",\ + "0.668165, 0.883968, 1.063291, 1.353033, 1.914886",\ + "1.248139, 1.463941, 1.643265, 1.933006, 2.494859",\ + "0.512957, 0.727792, 0.907081, 1.196846, 1.758744",\ + "0.544981, 0.759817, 0.939105, 1.228870, 1.790768",\ + "0.595389, 0.810225, 0.989513, 1.279278, 1.841177",\ + "0.756448, 0.971285, 1.150572, 1.440338, 2.002240",\ + "1.336421, 1.551259, 1.730546, 2.020311, 2.582213",\ + "0.602247, 0.808123, 0.987108, 1.276874, 1.838776",\ + "0.634272, 0.840147, 1.019132, 1.308898, 1.870800",\ + "0.684679, 0.890556, 1.069540, 1.359307, 1.921209",\ + "0.845739, 1.051616, 1.230599, 1.520366, 2.082271",\ + "1.425712, 1.631589, 1.810572, 2.100339, 2.662244",\ + "0.665958, 0.865953, 1.044805, 1.334306, 1.895796",\ + "0.697983, 0.897977, 1.076829, 1.366330, 1.927820",\ + "0.748391, 0.948386, 1.127237, 1.416738, 1.978229",\ + "0.909450, 1.109446, 1.288296, 1.577798, 2.139291",\ + "1.489423, 1.689419, 1.868270, 2.157771, 2.719264",\ + "0.990514, 1.171260, 1.348460, 1.637478, 2.198022",\ + "1.022539, 1.203284, 1.380485, 1.669502, 2.230046",\ + "1.072946, 1.253692, 1.430892, 1.719911, 2.280456",\ + "1.234006, 1.414753, 1.591951, 1.880970, 2.441518",\ + "1.813979, 1.994726, 2.171925, 2.460944, 3.021491"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011"); + values ( "0.029862, 0.029862, 0.029862, 0.029862, 0.029862",\ + "0.059267, 0.059267, 0.059267, 0.059266, 0.059266",\ + "0.131512, 0.131512, 0.131512, 0.131512, 0.131512",\ + "0.417803, 0.417802, 0.417802, 0.417800, 0.417795",\ + "1.484515, 1.484514, 1.484514, 1.484513, 1.484510",\ + "0.029862, 0.029862, 0.029862, 0.029862, 0.029862",\ + "0.059267, 0.059267, 0.059267, 0.059266, 0.059266",\ + "0.131512, 0.131512, 0.131512, 0.131512, 0.131512",\ + "0.417803, 0.417802, 0.417802, 0.417800, 0.417795",\ + "1.484515, 1.484514, 1.484514, 1.484513, 1.484510",\ + "0.029862, 0.029862, 0.029862, 0.029862, 0.029862",\ + "0.059267, 0.059267, 0.059267, 0.059266, 0.059266",\ + "0.131512, 0.131512, 0.131512, 0.131512, 0.131512",\ + "0.417803, 0.417802, 0.417802, 0.417800, 0.417795",\ + "1.484515, 1.484514, 1.484514, 1.484513, 1.484510",\ + "0.029862, 0.029862, 0.029862, 0.029862, 0.029862",\ + "0.059267, 0.059267, 0.059267, 0.059266, 0.059266",\ + "0.131512, 0.131512, 0.131512, 0.131512, 0.131512",\ + "0.417803, 0.417802, 0.417802, 0.417800, 0.417795",\ + "1.484515, 1.484514, 1.484514, 1.484513, 1.484510",\ + "0.029862, 0.029862, 0.029862, 0.029862, 0.029862",\ + "0.059267, 0.059267, 0.059267, 0.059266, 0.059266",\ + "0.131512, 0.131512, 0.131512, 0.131512, 0.131512",\ + "0.417803, 0.417802, 0.417802, 0.417800, 0.417795",\ + "1.484515, 1.484514, 1.484514, 1.484513, 1.484510"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_min_2386*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[28]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.556345, 0.776897, 0.954428, 1.243066, 1.803585",\ + "0.598041, 0.818593, 0.996124, 1.284762, 1.845281",\ + "0.674223, 0.894775, 1.072306, 1.360943, 1.921462",\ + "0.929618, 1.150170, 1.327701, 1.616339, 2.176858",\ + "1.853996, 2.074548, 2.252079, 2.540716, 3.101235",\ + "0.644757, 0.864215, 1.041709, 1.330371, 1.890938",\ + "0.686453, 0.905912, 1.083405, 1.372067, 1.932634",\ + "0.762635, 0.982093, 1.159587, 1.448249, 2.008816",\ + "1.018030, 1.237489, 1.414982, 1.703644, 2.264211",\ + "1.942408, 2.161866, 2.339360, 2.628021, 3.188588",\ + "0.733857, 0.944551, 1.121736, 1.410399, 1.970970",\ + "0.775553, 0.986247, 1.163432, 1.452096, 2.012666",\ + "0.851735, 1.062428, 1.239614, 1.528277, 2.088847",\ + "1.107130, 1.317824, 1.495009, 1.783673, 2.344243",\ + "2.031507, 2.242201, 2.419386, 2.708050, 3.268620",\ + "0.797144, 1.002367, 1.179428, 1.467829, 2.027984",\ + "0.838840, 1.044064, 1.221124, 1.509525, 2.069680",\ + "0.915021, 1.120245, 1.297306, 1.585706, 2.145862",\ + "1.170417, 1.375641, 1.552701, 1.841102, 2.401258",\ + "2.094794, 2.300018, 2.477078, 2.765479, 3.325634",\ + "1.128157, 1.307597, 1.483084, 1.771000, 2.330204",\ + "1.169853, 1.349293, 1.524780, 1.812697, 2.371901",\ + "1.246035, 1.425474, 1.600962, 1.888878, 2.448082",\ + "1.501431, 1.680870, 1.856357, 2.144274, 2.703477",\ + "2.425808, 2.605247, 2.780735, 3.068651, 3.627855"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\ + "0.199415, 0.199415, 0.199415, 0.199415, 0.199415",\ + "0.685787, 0.685787, 0.685787, 0.685787, 0.685786",\ + "2.455201, 2.455201, 2.455201, 2.455201, 2.455201",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\ + "0.199415, 0.199415, 0.199415, 0.199415, 0.199415",\ + "0.685787, 0.685787, 0.685787, 0.685787, 0.685786",\ + "2.455201, 2.455201, 2.455201, 2.455201, 2.455201",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\ + "0.199415, 0.199415, 0.199415, 0.199415, 0.199415",\ + "0.685787, 0.685787, 0.685787, 0.685787, 0.685786",\ + "2.455201, 2.455201, 2.455201, 2.455201, 2.455201",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\ + "0.199415, 0.199415, 0.199415, 0.199415, 0.199415",\ + "0.685787, 0.685787, 0.685787, 0.685787, 0.685786",\ + "2.455201, 2.455201, 2.455201, 2.455201, 2.455201",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\ + "0.199415, 0.199415, 0.199415, 0.199415, 0.199415",\ + "0.685787, 0.685787, 0.685787, 0.685787, 0.685786",\ + "2.455201, 2.455201, 2.455201, 2.455201, 2.455201"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.576590, 0.797142, 0.974673, 1.263311, 1.823830",\ + "0.608840, 0.829392, 1.006923, 1.295561, 1.856079",\ + "0.659152, 0.879704, 1.057235, 1.345873, 1.906392",\ + "0.819816, 1.040368, 1.217899, 1.506536, 2.067055",\ + "1.400950, 1.621502, 1.799033, 2.087670, 2.648189",\ + "0.665002, 0.884461, 1.061954, 1.350616, 1.911183",\ + "0.697252, 0.916710, 1.094204, 1.382866, 1.943433",\ + "0.747564, 0.967022, 1.144516, 1.433178, 1.993745",\ + "0.908228, 1.127686, 1.305180, 1.593842, 2.154409",\ + "1.489362, 1.708820, 1.886313, 2.174975, 2.735543",\ + "0.754102, 0.964796, 1.141981, 1.430644, 1.991215",\ + "0.786352, 0.997045, 1.174231, 1.462894, 2.023464",\ + "0.836664, 1.047358, 1.224543, 1.513206, 2.073777",\ + "0.997328, 1.208021, 1.385207, 1.673870, 2.234440",\ + "1.578462, 1.789155, 1.966340, 2.255004, 2.815574",\ + "0.817389, 1.022612, 1.199673, 1.488074, 2.048229",\ + "0.849638, 1.054862, 1.231923, 1.520324, 2.080479",\ + "0.899951, 1.105174, 1.282235, 1.570636, 2.130791",\ + "1.060614, 1.265838, 1.442899, 1.731299, 2.291455",\ + "1.641748, 1.846972, 2.024032, 2.312433, 2.872589",\ + "1.148402, 1.327842, 1.503329, 1.791245, 2.350449",\ + "1.180652, 1.360092, 1.535579, 1.823495, 2.382699",\ + "1.230964, 1.410404, 1.585891, 1.873807, 2.433011",\ + "1.391628, 1.571068, 1.746555, 2.034471, 2.593675",\ + "1.972762, 2.152201, 2.327689, 2.615605, 3.174809"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131486, 0.131486, 0.131486, 0.131486, 0.131486",\ + "0.419471, 0.419471, 0.419471, 0.419471, 0.419471",\ + "1.482976, 1.482976, 1.482976, 1.482976, 1.482976",\ + "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131486, 0.131486, 0.131486, 0.131486, 0.131486",\ + "0.419471, 0.419471, 0.419471, 0.419471, 0.419471",\ + "1.482976, 1.482976, 1.482976, 1.482976, 1.482976",\ + "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131486, 0.131486, 0.131486, 0.131486, 0.131486",\ + "0.419471, 0.419471, 0.419471, 0.419471, 0.419471",\ + "1.482976, 1.482976, 1.482976, 1.482976, 1.482976",\ + "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131486, 0.131486, 0.131486, 0.131486, 0.131486",\ + "0.419471, 0.419471, 0.419471, 0.419471, 0.419471",\ + "1.482976, 1.482976, 1.482976, 1.482976, 1.482976",\ + "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131486, 0.131486, 0.131486, 0.131486, 0.131486",\ + "0.419471, 0.419471, 0.419471, 0.419471, 0.419471",\ + "1.482976, 1.482976, 1.482976, 1.482976, 1.482976"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_min*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[29]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.538673, 0.779387, 0.972430, 1.279750, 1.873102",\ + "0.580369, 0.821084, 1.014127, 1.321447, 1.914798",\ + "0.656550, 0.897265, 1.090308, 1.397628, 1.990980",\ + "0.911946, 1.152661, 1.345703, 1.653024, 2.246375",\ + "1.836323, 2.077038, 2.270081, 2.577401, 3.170752",\ + "0.626961, 0.866705, 1.059711, 1.367055, 1.960455",\ + "0.668657, 0.908401, 1.101408, 1.408752, 2.002152",\ + "0.744839, 0.984583, 1.177589, 1.484933, 2.078333",\ + "1.000234, 1.239979, 1.432984, 1.740329, 2.333729",\ + "1.924612, 2.164356, 2.357362, 2.664706, 3.258105",\ + "0.716276, 0.947035, 1.139738, 1.447084, 2.040487",\ + "0.757973, 0.988732, 1.181434, 1.488780, 2.082183",\ + "0.834154, 1.064913, 1.257616, 1.564962, 2.158365",\ + "1.089550, 1.320309, 1.513011, 1.820357, 2.413760",\ + "2.013927, 2.244686, 2.437389, 2.744734, 3.338137",\ + "0.780015, 1.004896, 1.197467, 1.504554, 2.097583",\ + "0.821712, 1.046593, 1.239163, 1.546250, 2.139279",\ + "0.897893, 1.122774, 1.315345, 1.622432, 2.215461",\ + "1.153289, 1.378170, 1.570740, 1.877827, 2.470857",\ + "2.077666, 2.302547, 2.495118, 2.802204, 3.395233",\ + "1.117001, 1.310416, 1.501127, 1.807759, 2.399902",\ + "1.158697, 1.352113, 1.542824, 1.849456, 2.441598",\ + "1.234879, 1.428294, 1.619005, 1.925637, 2.517779",\ + "1.490274, 1.683690, 1.874401, 2.181033, 2.773175",\ + "2.414652, 2.608067, 2.798778, 3.105409, 3.697551"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\ + "0.199415, 0.199415, 0.199415, 0.199415, 0.199415",\ + "0.685787, 0.685787, 0.685787, 0.685786, 0.685786",\ + "2.455201, 2.455201, 2.455201, 2.455201, 2.455201",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\ + "0.199415, 0.199415, 0.199415, 0.199415, 0.199415",\ + "0.685787, 0.685787, 0.685787, 0.685786, 0.685786",\ + "2.455201, 2.455201, 2.455201, 2.455201, 2.455201",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\ + "0.199415, 0.199415, 0.199415, 0.199415, 0.199415",\ + "0.685787, 0.685787, 0.685787, 0.685786, 0.685786",\ + "2.455201, 2.455201, 2.455201, 2.455201, 2.455201",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\ + "0.199415, 0.199415, 0.199415, 0.199415, 0.199415",\ + "0.685787, 0.685787, 0.685787, 0.685786, 0.685786",\ + "2.455201, 2.455201, 2.455201, 2.455201, 2.455201",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\ + "0.199415, 0.199415, 0.199415, 0.199415, 0.199415",\ + "0.685787, 0.685787, 0.685787, 0.685786, 0.685786",\ + "2.455201, 2.455201, 2.455201, 2.455201, 2.455201"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.558918, 0.799632, 0.992675, 1.299995, 1.893347",\ + "0.591168, 0.831882, 1.024925, 1.332245, 1.925597",\ + "0.641480, 0.882194, 1.075237, 1.382557, 1.975909",\ + "0.802143, 1.042858, 1.235901, 1.543221, 2.136573",\ + "1.383277, 1.623992, 1.817035, 2.124355, 2.717707",\ + "0.647206, 0.886950, 1.079956, 1.387300, 1.980700",\ + "0.679456, 0.919200, 1.112206, 1.419550, 2.012950",\ + "0.729768, 0.969512, 1.162518, 1.469862, 2.063262",\ + "0.890432, 1.130176, 1.323182, 1.630526, 2.223926",\ + "1.471565, 1.711310, 1.904316, 2.211660, 2.805060",\ + "0.736521, 0.967281, 1.159983, 1.467329, 2.060732",\ + "0.768771, 0.999530, 1.192233, 1.499579, 2.092982",\ + "0.819083, 1.049842, 1.242545, 1.549891, 2.143294",\ + "0.979747, 1.210506, 1.403209, 1.710555, 2.303958",\ + "1.560881, 1.791640, 1.984343, 2.291688, 2.885092",\ + "0.800261, 1.025141, 1.217712, 1.524799, 2.117828",\ + "0.832510, 1.057391, 1.249962, 1.557049, 2.150078",\ + "0.882822, 1.107703, 1.300274, 1.607361, 2.200390",\ + "1.043486, 1.268367, 1.460938, 1.768024, 2.361054",\ + "1.624620, 1.849501, 2.042072, 2.349159, 2.942188",\ + "1.137246, 1.330662, 1.521373, 1.828004, 2.420147",\ + "1.169496, 1.362911, 1.553622, 1.860254, 2.452396",\ + "1.219808, 1.413224, 1.603935, 1.910566, 2.502709",\ + "1.380472, 1.573887, 1.764598, 2.071230, 2.663373",\ + "1.961606, 2.155021, 2.345732, 2.652364, 3.244506"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131486, 0.131486, 0.131486, 0.131486, 0.131486",\ + "0.419471, 0.419471, 0.419471, 0.419471, 0.419471",\ + "1.482976, 1.482976, 1.482976, 1.482976, 1.482976",\ + "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131486, 0.131486, 0.131486, 0.131486, 0.131486",\ + "0.419471, 0.419471, 0.419471, 0.419471, 0.419471",\ + "1.482976, 1.482976, 1.482976, 1.482976, 1.482976",\ + "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131486, 0.131486, 0.131486, 0.131486, 0.131486",\ + "0.419471, 0.419471, 0.419471, 0.419471, 0.419471",\ + "1.482976, 1.482976, 1.482976, 1.482976, 1.482976",\ + "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131486, 0.131486, 0.131486, 0.131486, 0.131486",\ + "0.419471, 0.419471, 0.419471, 0.419471, 0.419471",\ + "1.482976, 1.482976, 1.482976, 1.482976, 1.482976",\ + "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131486, 0.131486, 0.131486, 0.131486, 0.131486",\ + "0.419471, 0.419471, 0.419471, 0.419471, 0.419471",\ + "1.482976, 1.482976, 1.482976, 1.482976, 1.482976"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_min_2306*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[32]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.454515, 0.687556, 0.876637, 1.181062, 1.770586",\ + "0.496240, 0.729281, 0.918362, 1.222787, 1.812311",\ + "0.572297, 0.805339, 0.994419, 1.298844, 1.888368",\ + "0.827855, 1.060896, 1.249979, 1.554404, 2.143927",\ + "1.752113, 1.985154, 2.174236, 2.478661, 3.068184",\ + "0.542959, 0.774874, 0.963918, 1.268367, 1.857939",\ + "0.584684, 0.816599, 1.005643, 1.310092, 1.899664",\ + "0.660741, 0.892656, 1.081700, 1.386149, 1.975721",\ + "0.916299, 1.148213, 1.337260, 1.641709, 2.231281",\ + "1.840557, 2.072472, 2.261517, 2.565966, 3.155538",\ + "0.633029, 0.855201, 1.043945, 1.348395, 1.937971",\ + "0.674754, 0.896927, 1.085670, 1.390121, 1.979696",\ + "0.750812, 0.972984, 1.161727, 1.466178, 2.055753",\ + "1.006370, 1.228541, 1.417287, 1.721738, 2.311312",\ + "1.930628, 2.152800, 2.341543, 2.645994, 3.235569",\ + "0.697606, 0.913035, 1.101665, 1.405861, 1.995059",\ + "0.739331, 0.954761, 1.143391, 1.447586, 2.036784",\ + "0.815389, 1.030818, 1.219448, 1.523643, 2.112841",\ + "1.070947, 1.286375, 1.475007, 1.779203, 2.368400",\ + "1.995205, 2.210634, 2.399264, 2.703460, 3.292657",\ + "1.037719, 1.218357, 1.405324, 1.709062, 2.297368",\ + "1.079444, 1.260083, 1.447049, 1.750787, 2.339093",\ + "1.155501, 1.336140, 1.523106, 1.826844, 2.415150",\ + "1.411059, 1.591697, 1.778666, 2.082405, 2.670709",\ + "2.335317, 2.515956, 2.702923, 3.006661, 3.594966"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.025366, 0.025366, 0.025366, 0.025366, 0.025366",\ + "0.070222, 0.070222, 0.070222, 0.070222, 0.070222",\ + "0.199531, 0.199531, 0.199531, 0.199531, 0.199531",\ + "0.686584, 0.686584, 0.686584, 0.686584, 0.686584",\ + "2.452471, 2.452462, 2.452462, 2.452446, 2.452406",\ + "0.025366, 0.025366, 0.025366, 0.025366, 0.025366",\ + "0.070222, 0.070222, 0.070222, 0.070222, 0.070222",\ + "0.199531, 0.199531, 0.199531, 0.199531, 0.199531",\ + "0.686584, 0.686584, 0.686584, 0.686584, 0.686584",\ + "2.452471, 2.452462, 2.452462, 2.452446, 2.452406",\ + "0.025366, 0.025366, 0.025366, 0.025366, 0.025366",\ + "0.070222, 0.070222, 0.070222, 0.070222, 0.070222",\ + "0.199531, 0.199531, 0.199531, 0.199531, 0.199531",\ + "0.686584, 0.686584, 0.686584, 0.686584, 0.686584",\ + "2.452471, 2.452462, 2.452462, 2.452446, 2.452406",\ + "0.025366, 0.025366, 0.025366, 0.025366, 0.025366",\ + "0.070222, 0.070222, 0.070222, 0.070222, 0.070222",\ + "0.199531, 0.199531, 0.199531, 0.199531, 0.199531",\ + "0.686584, 0.686584, 0.686584, 0.686584, 0.686584",\ + "2.452470, 2.452462, 2.452462, 2.452446, 2.452406",\ + "0.025366, 0.025366, 0.025366, 0.025366, 0.025366",\ + "0.070222, 0.070222, 0.070222, 0.070222, 0.070222",\ + "0.199531, 0.199531, 0.199531, 0.199531, 0.199531",\ + "0.686584, 0.686584, 0.686584, 0.686584, 0.686584",\ + "2.452470, 2.452462, 2.452462, 2.452446, 2.452406"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.477114, 0.710155, 0.899236, 1.203661, 1.793185",\ + "0.509144, 0.742185, 0.931266, 1.235691, 1.825215",\ + "0.559532, 0.792574, 0.981654, 1.286079, 1.875603",\ + "0.720561, 0.953603, 1.142682, 1.447107, 2.036631",\ + "1.300536, 1.533577, 1.722657, 2.027082, 2.616606",\ + "0.565558, 0.797473, 0.986517, 1.290966, 1.880538",\ + "0.597588, 0.829503, 1.018547, 1.322996, 1.912568",\ + "0.647976, 0.879891, 1.068935, 1.373384, 1.962957",\ + "0.809005, 1.040920, 1.229963, 1.534412, 2.123985",\ + "1.388980, 1.620895, 1.809938, 2.114387, 2.703959",\ + "0.655628, 0.877800, 1.066544, 1.370995, 1.960570",\ + "0.687658, 0.909830, 1.098574, 1.403025, 1.992600",\ + "0.738047, 0.960219, 1.148962, 1.453413, 2.042988",\ + "0.899075, 1.121248, 1.309990, 1.614440, 2.204016",\ + "1.479050, 1.701223, 1.889965, 2.194416, 2.783991",\ + "0.720205, 0.935634, 1.124265, 1.428460, 2.017658",\ + "0.752235, 0.967664, 1.156295, 1.460490, 2.049688",\ + "0.802624, 1.018053, 1.206683, 1.510878, 2.100076",\ + "0.963652, 1.179082, 1.367711, 1.671906, 2.261104",\ + "1.543628, 1.759057, 1.947685, 2.251881, 2.841079",\ + "1.060318, 1.240956, 1.427923, 1.731662, 2.319967",\ + "1.092348, 1.272986, 1.459953, 1.763692, 2.351997",\ + "1.142736, 1.323375, 1.510341, 1.814080, 2.402385",\ + "1.303765, 1.484404, 1.671369, 1.975107, 2.563413",\ + "1.883740, 2.064379, 2.251344, 2.555082, 3.143388"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.029863, 0.029863, 0.029863, 0.029863, 0.029863",\ + "0.059265, 0.059264, 0.059264, 0.059264, 0.059262",\ + "0.131521, 0.131521, 0.131521, 0.131521, 0.131521",\ + "0.417786, 0.417783, 0.417783, 0.417777, 0.417763",\ + "1.484506, 1.484504, 1.484504, 1.484501, 1.484494",\ + "0.029863, 0.029863, 0.029863, 0.029863, 0.029863",\ + "0.059265, 0.059264, 0.059264, 0.059264, 0.059262",\ + "0.131521, 0.131521, 0.131521, 0.131521, 0.131521",\ + "0.417786, 0.417783, 0.417783, 0.417777, 0.417763",\ + "1.484506, 1.484504, 1.484504, 1.484501, 1.484494",\ + "0.029863, 0.029863, 0.029863, 0.029863, 0.029863",\ + "0.059265, 0.059264, 0.059264, 0.059264, 0.059262",\ + "0.131521, 0.131521, 0.131521, 0.131521, 0.131521",\ + "0.417785, 0.417783, 0.417783, 0.417777, 0.417763",\ + "1.484505, 1.484504, 1.484504, 1.484501, 1.484494",\ + "0.029863, 0.029863, 0.029863, 0.029863, 0.029863",\ + "0.059265, 0.059264, 0.059264, 0.059264, 0.059262",\ + "0.131521, 0.131521, 0.131521, 0.131521, 0.131521",\ + "0.417785, 0.417783, 0.417783, 0.417777, 0.417763",\ + "1.484505, 1.484504, 1.484504, 1.484501, 1.484494",\ + "0.029863, 0.029863, 0.029863, 0.029863, 0.029863",\ + "0.059265, 0.059264, 0.059264, 0.059264, 0.059262",\ + "0.131521, 0.131521, 0.131521, 0.131521, 0.131521",\ + "0.417785, 0.417783, 0.417783, 0.417777, 0.417763",\ + "1.484505, 1.484504, 1.484504, 1.484501, 1.484493"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_min_2463*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[38]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.490508, 0.711036, 0.888618, 1.176984, 1.736809",\ + "0.532203, 0.752732, 0.930314, 1.218679, 1.778504",\ + "0.608383, 0.828912, 1.006494, 1.294859, 1.854684",\ + "0.863773, 1.084302, 1.261884, 1.550249, 2.110074",\ + "1.788229, 2.008758, 2.186340, 2.474705, 3.034531",\ + "0.578896, 0.798355, 0.975899, 1.264289, 1.824162",\ + "0.620592, 0.840050, 1.017595, 1.305984, 1.865858",\ + "0.696772, 0.916230, 1.093775, 1.382164, 1.942038",\ + "0.952161, 1.171620, 1.349165, 1.637554, 2.197427",\ + "1.876618, 2.096076, 2.273621, 2.562011, 3.121884",\ + "0.668261, 0.878687, 1.055926, 1.344317, 1.904194",\ + "0.709957, 0.920382, 1.097622, 1.386013, 1.945889",\ + "0.786137, 0.996562, 1.173802, 1.462193, 2.022069",\ + "1.041527, 1.251952, 1.429191, 1.717583, 2.277459",\ + "1.965983, 2.176409, 2.353648, 2.642039, 3.201916",\ + "0.731942, 0.936503, 1.113619, 1.401746, 1.961208",\ + "0.773637, 0.978198, 1.155315, 1.443442, 2.002903",\ + "0.849817, 1.054379, 1.231495, 1.519622, 2.079083",\ + "1.105207, 1.309768, 1.486884, 1.775012, 2.334473",\ + "2.029663, 2.234225, 2.411341, 2.699468, 3.258930",\ + "1.063585, 1.241717, 1.417274, 1.704917, 2.263427",\ + "1.105281, 1.283412, 1.458970, 1.746613, 2.305123",\ + "1.181460, 1.359592, 1.535150, 1.822793, 2.381303",\ + "1.436850, 1.614982, 1.790540, 2.078182, 2.636693",\ + "2.361307, 2.539439, 2.714996, 3.002639, 3.561149"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070076, 0.070076, 0.070076, 0.070076, 0.070076",\ + "0.199409, 0.199409, 0.199409, 0.199409, 0.199410",\ + "0.685874, 0.685874, 0.685874, 0.685874, 0.685874",\ + "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070076, 0.070076, 0.070076, 0.070076, 0.070076",\ + "0.199409, 0.199409, 0.199409, 0.199409, 0.199410",\ + "0.685874, 0.685874, 0.685874, 0.685874, 0.685874",\ + "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070076, 0.070076, 0.070076, 0.070076, 0.070076",\ + "0.199409, 0.199409, 0.199409, 0.199409, 0.199410",\ + "0.685874, 0.685874, 0.685874, 0.685874, 0.685874",\ + "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070076, 0.070076, 0.070076, 0.070076, 0.070076",\ + "0.199409, 0.199409, 0.199409, 0.199409, 0.199410",\ + "0.685874, 0.685874, 0.685874, 0.685874, 0.685874",\ + "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070076, 0.070076, 0.070076, 0.070076, 0.070076",\ + "0.199409, 0.199409, 0.199409, 0.199409, 0.199410",\ + "0.685874, 0.685874, 0.685874, 0.685874, 0.685874",\ + "2.455194, 2.455194, 2.455194, 2.455194, 2.455194"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.510756, 0.731284, 0.908866, 1.197232, 1.757056",\ + "0.543002, 0.763530, 0.941112, 1.229478, 1.789302",\ + "0.593318, 0.813846, 0.991428, 1.279794, 1.839619",\ + "0.753982, 0.974510, 1.152092, 1.440458, 2.000283",\ + "1.335097, 1.555626, 1.733208, 2.021573, 2.581398",\ + "0.599144, 0.818602, 0.996147, 1.284537, 1.844410",\ + "0.631390, 0.850848, 1.028393, 1.316783, 1.876656",\ + "0.681706, 0.901165, 1.078709, 1.367099, 1.926972",\ + "0.842370, 1.061828, 1.239373, 1.527763, 2.087636",\ + "1.423486, 1.642944, 1.820489, 2.108878, 2.668751",\ + "0.688509, 0.898935, 1.076174, 1.364565, 1.924441",\ + "0.720755, 0.931181, 1.108420, 1.396811, 1.956687",\ + "0.771071, 0.981497, 1.158736, 1.447127, 2.007004",\ + "0.931735, 1.142161, 1.319400, 1.607791, 2.167668",\ + "1.512851, 1.723276, 1.900516, 2.188907, 2.748783",\ + "0.752190, 0.956751, 1.133867, 1.421994, 1.981456",\ + "0.784436, 0.988997, 1.166113, 1.454240, 2.013701",\ + "0.834752, 1.039313, 1.216429, 1.504556, 2.064018",\ + "0.995416, 1.199977, 1.377093, 1.665220, 2.224682",\ + "1.576531, 1.781092, 1.958208, 2.246336, 2.805797",\ + "1.083833, 1.261965, 1.437522, 1.725165, 2.283675",\ + "1.116079, 1.294211, 1.469768, 1.757411, 2.315921",\ + "1.166395, 1.344527, 1.520084, 1.807727, 2.366237",\ + "1.327059, 1.505191, 1.680748, 1.968391, 2.526901",\ + "1.908174, 2.086306, 2.261864, 2.549506, 3.108017"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.029703, 0.029703, 0.029703, 0.029703, 0.029703",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\ + "0.419479, 0.419479, 0.419479, 0.419479, 0.419479",\ + "1.483052, 1.483052, 1.483052, 1.483052, 1.483052",\ + "0.029703, 0.029703, 0.029703, 0.029703, 0.029703",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\ + "0.419479, 0.419479, 0.419479, 0.419479, 0.419479",\ + "1.483052, 1.483052, 1.483052, 1.483052, 1.483052",\ + "0.029703, 0.029703, 0.029703, 0.029703, 0.029703",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\ + "0.419479, 0.419479, 0.419479, 0.419479, 0.419479",\ + "1.483052, 1.483052, 1.483052, 1.483052, 1.483052",\ + "0.029703, 0.029703, 0.029703, 0.029703, 0.029703",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\ + "0.419479, 0.419479, 0.419479, 0.419479, 0.419479",\ + "1.483052, 1.483052, 1.483052, 1.483052, 1.483052",\ + "0.029703, 0.029703, 0.029703, 0.029703, 0.029703",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\ + "0.419479, 0.419479, 0.419479, 0.419479, 0.419479",\ + "1.483052, 1.483052, 1.483052, 1.483052, 1.483052"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_min_2279*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[39]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011"); + values ( "0.464141, 0.703934, 0.888128, 1.182401, 1.751067",\ + "0.505836, 0.745630, 0.929824, 1.224097, 1.792763",\ + "0.582016, 0.821810, 1.006004, 1.300277, 1.868943",\ + "0.837406, 1.077200, 1.261394, 1.555666, 2.124333",\ + "1.761863, 2.001656, 2.185850, 2.480123, 3.048789",\ + "0.552479, 0.791253, 0.975409, 1.269706, 1.838421",\ + "0.594175, 0.832948, 1.017105, 1.311402, 1.880116",\ + "0.670355, 0.909128, 1.093285, 1.387582, 1.956296",\ + "0.925745, 1.164518, 1.348675, 1.642971, 2.211686",\ + "1.850201, 2.088974, 2.273131, 2.567428, 3.136143",\ + "0.641618, 0.871586, 1.055436, 1.349735, 1.918452",\ + "0.683313, 0.913281, 1.097132, 1.391430, 1.960148",\ + "0.759493, 0.989461, 1.173312, 1.467610, 2.036328",\ + "1.014883, 1.244851, 1.428701, 1.723000, 2.291718",\ + "1.939340, 2.169307, 2.353158, 2.647456, 3.216174",\ + "0.705051, 0.929417, 1.113144, 1.407174, 1.975487",\ + "0.746746, 0.971112, 1.154840, 1.448870, 2.017183",\ + "0.822926, 1.047292, 1.231020, 1.525050, 2.093363",\ + "1.078316, 1.302682, 1.486409, 1.780439, 2.348753",\ + "2.002773, 2.227139, 2.410866, 2.704896, 3.273209",\ + "1.040106, 1.234739, 1.416802, 1.710354, 2.277733",\ + "1.081802, 1.276435, 1.458498, 1.752050, 2.319428",\ + "1.157982, 1.352615, 1.534678, 1.828230, 2.395608",\ + "1.413371, 1.608004, 1.790067, 2.083619, 2.650998",\ + "2.337828, 2.532461, 2.714524, 3.008076, 3.575455"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011"); + values ( "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070076, 0.070076, 0.070076, 0.070076, 0.070076",\ + "0.199408, 0.199408, 0.199409, 0.199409, 0.199411",\ + "0.685874, 0.685874, 0.685874, 0.685874, 0.685874",\ + "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070076, 0.070076, 0.070076, 0.070076, 0.070076",\ + "0.199408, 0.199408, 0.199409, 0.199409, 0.199411",\ + "0.685874, 0.685874, 0.685874, 0.685874, 0.685874",\ + "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070076, 0.070076, 0.070076, 0.070076, 0.070076",\ + "0.199408, 0.199408, 0.199409, 0.199409, 0.199411",\ + "0.685874, 0.685874, 0.685874, 0.685874, 0.685874",\ + "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070076, 0.070076, 0.070076, 0.070076, 0.070076",\ + "0.199408, 0.199408, 0.199409, 0.199409, 0.199411",\ + "0.685874, 0.685874, 0.685874, 0.685874, 0.685874",\ + "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070076, 0.070076, 0.070076, 0.070076, 0.070076",\ + "0.199408, 0.199408, 0.199409, 0.199409, 0.199411",\ + "0.685874, 0.685874, 0.685874, 0.685874, 0.685874",\ + "2.455194, 2.455194, 2.455194, 2.455194, 2.455194"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011"); + values ( "0.484389, 0.724182, 0.908376, 1.202649, 1.771315",\ + "0.516635, 0.756428, 0.940622, 1.234895, 1.803561",\ + "0.566951, 0.806745, 0.990938, 1.285211, 1.853878",\ + "0.727615, 0.967409, 1.151602, 1.445875, 2.014541",\ + "1.308730, 1.548524, 1.732718, 2.026990, 2.595657",\ + "0.572727, 0.811501, 0.995657, 1.289954, 1.858669",\ + "0.604973, 0.843747, 1.027903, 1.322200, 1.890915",\ + "0.655290, 0.894063, 1.078219, 1.372516, 1.941231",\ + "0.815953, 1.054727, 1.238883, 1.533180, 2.101895",\ + "1.397069, 1.635842, 1.819999, 2.114295, 2.683010",\ + "0.661866, 0.891834, 1.075684, 1.369982, 1.938700",\ + "0.694112, 0.924080, 1.107930, 1.402228, 1.970946",\ + "0.744428, 0.974396, 1.158246, 1.452545, 2.021263",\ + "0.905092, 1.135060, 1.318910, 1.613209, 2.181926",\ + "1.486207, 1.716175, 1.900026, 2.194324, 2.763042",\ + "0.725299, 0.949665, 1.133392, 1.427422, 1.995735",\ + "0.757545, 0.981911, 1.165638, 1.459668, 2.027981",\ + "0.807861, 1.032227, 1.215954, 1.509984, 2.078298",\ + "0.968525, 1.192891, 1.376618, 1.670648, 2.238961",\ + "1.549640, 1.774006, 1.957734, 2.251764, 2.820077",\ + "1.060354, 1.254987, 1.437050, 1.730602, 2.297981",\ + "1.092600, 1.287233, 1.469296, 1.762848, 2.330226",\ + "1.142916, 1.337549, 1.519612, 1.813164, 2.380543",\ + "1.303580, 1.498213, 1.680276, 1.973828, 2.541207",\ + "1.884696, 2.079328, 2.261392, 2.554944, 3.122322"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011"); + values ( "0.029703, 0.029703, 0.029703, 0.029703, 0.029704",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131484, 0.131484, 0.131484, 0.131485, 0.131485",\ + "0.419474, 0.419474, 0.419474, 0.419474, 0.419474",\ + "1.483052, 1.483052, 1.483052, 1.483052, 1.483052",\ + "0.029703, 0.029703, 0.029703, 0.029703, 0.029704",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131484, 0.131484, 0.131484, 0.131485, 0.131485",\ + "0.419474, 0.419474, 0.419474, 0.419474, 0.419474",\ + "1.483052, 1.483052, 1.483052, 1.483052, 1.483052",\ + "0.029703, 0.029703, 0.029703, 0.029703, 0.029704",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131484, 0.131484, 0.131484, 0.131485, 0.131485",\ + "0.419474, 0.419474, 0.419474, 0.419474, 0.419474",\ + "1.483052, 1.483052, 1.483052, 1.483052, 1.483052",\ + "0.029703, 0.029703, 0.029703, 0.029703, 0.029704",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131484, 0.131484, 0.131484, 0.131485, 0.131485",\ + "0.419474, 0.419474, 0.419474, 0.419474, 0.419474",\ + "1.483052, 1.483052, 1.483052, 1.483052, 1.483052",\ + "0.029703, 0.029703, 0.029703, 0.029703, 0.029704",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131484, 0.131484, 0.131484, 0.131485, 0.131485",\ + "0.419474, 0.419474, 0.419474, 0.419474, 0.419474",\ + "1.483052, 1.483052, 1.483052, 1.483052, 1.483052"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_min_2323*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[41]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.411437, 0.641763, 0.827440, 1.121826, 1.689429",\ + "0.453163, 0.683488, 0.869165, 1.163551, 1.731154",\ + "0.529220, 0.759545, 0.945221, 1.239608, 1.807211",\ + "0.784777, 1.015107, 1.200787, 1.495173, 2.062773",\ + "1.709036, 1.939362, 2.125040, 2.419426, 2.987028",\ + "0.499750, 0.729081, 0.914721, 1.209131, 1.776782",\ + "0.541475, 0.770807, 0.956446, 1.250857, 1.818508",\ + "0.617533, 0.846863, 1.032502, 1.326913, 1.894564",\ + "0.873090, 1.102426, 1.288068, 1.582478, 2.150126",\ + "1.797349, 2.026680, 2.212321, 2.506731, 3.074381",\ + "0.588895, 0.809414, 0.994747, 1.289160, 1.856814",\ + "0.630620, 0.851139, 1.036473, 1.330885, 1.898539",\ + "0.706677, 0.927196, 1.112529, 1.406941, 1.974596",\ + "0.962234, 1.182758, 1.368095, 1.662507, 2.230158",\ + "1.886493, 2.107013, 2.292347, 2.586760, 3.154413",\ + "0.652369, 0.867238, 1.052459, 1.346598, 1.913847",\ + "0.694094, 0.908963, 1.094185, 1.388323, 1.955572",\ + "0.770151, 0.985020, 1.170241, 1.464380, 2.031629",\ + "1.025709, 1.240582, 1.425807, 1.719945, 2.287190",\ + "1.949967, 2.164837, 2.350059, 2.644198, 3.211446",\ + "0.987682, 1.172511, 1.356118, 1.649777, 2.216089",\ + "1.029408, 1.214237, 1.397843, 1.691502, 2.257815",\ + "1.105465, 1.290294, 1.473899, 1.767559, 2.333871",\ + "1.361025, 1.545856, 1.729465, 2.023124, 2.589433",\ + "2.285281, 2.470111, 2.653718, 2.947377, 3.513689"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.025366, 0.025366, 0.025366, 0.025366, 0.025366",\ + "0.070223, 0.070222, 0.070221, 0.070221, 0.070221",\ + "0.199530, 0.199530, 0.199530, 0.199530, 0.199530",\ + "0.686589, 0.686583, 0.686578, 0.686576, 0.686576",\ + "2.452462, 2.452462, 2.452462, 2.452450, 2.452423",\ + "0.025366, 0.025366, 0.025366, 0.025366, 0.025366",\ + "0.070223, 0.070222, 0.070221, 0.070221, 0.070221",\ + "0.199530, 0.199530, 0.199530, 0.199530, 0.199530",\ + "0.686589, 0.686583, 0.686578, 0.686576, 0.686576",\ + "2.452462, 2.452462, 2.452462, 2.452450, 2.452423",\ + "0.025366, 0.025366, 0.025366, 0.025366, 0.025366",\ + "0.070223, 0.070222, 0.070221, 0.070221, 0.070221",\ + "0.199530, 0.199530, 0.199530, 0.199530, 0.199530",\ + "0.686588, 0.686583, 0.686578, 0.686576, 0.686576",\ + "2.452462, 2.452462, 2.452462, 2.452450, 2.452423",\ + "0.025366, 0.025366, 0.025366, 0.025366, 0.025366",\ + "0.070223, 0.070222, 0.070221, 0.070221, 0.070221",\ + "0.199530, 0.199530, 0.199530, 0.199530, 0.199530",\ + "0.686588, 0.686583, 0.686578, 0.686576, 0.686576",\ + "2.452462, 2.452462, 2.452462, 2.452450, 2.452423",\ + "0.025366, 0.025366, 0.025366, 0.025366, 0.025366",\ + "0.070222, 0.070222, 0.070221, 0.070221, 0.070221",\ + "0.199530, 0.199530, 0.199530, 0.199530, 0.199530",\ + "0.686585, 0.686583, 0.686578, 0.686576, 0.686576",\ + "2.452462, 2.452462, 2.452462, 2.452450, 2.452422"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.434036, 0.664363, 0.850040, 1.144426, 1.712028",\ + "0.466066, 0.696393, 0.882070, 1.176457, 1.744059",\ + "0.516455, 0.746780, 0.932457, 1.226843, 1.794446",\ + "0.677484, 0.907807, 1.093482, 1.387868, 1.955473",\ + "1.257459, 1.487782, 1.673457, 1.967843, 2.535448",\ + "0.522349, 0.751681, 0.937321, 1.231731, 1.799382",\ + "0.554379, 0.783711, 0.969351, 1.263762, 1.831412",\ + "0.604768, 0.834099, 1.019738, 1.314148, 1.881800",\ + "0.765797, 0.995125, 1.180763, 1.475173, 2.042827",\ + "1.345772, 1.575100, 1.760738, 2.055148, 2.622802",\ + "0.611494, 0.832013, 1.017348, 1.311760, 1.879413",\ + "0.643524, 0.864044, 1.049378, 1.343790, 1.911444",\ + "0.693912, 0.914431, 1.099764, 1.394177, 1.961831",\ + "0.854941, 1.075458, 1.260790, 1.555202, 2.122858",\ + "1.434916, 1.655433, 1.840765, 2.135177, 2.702833",\ + "0.674968, 0.889838, 1.075059, 1.369198, 1.936446",\ + "0.706998, 0.921868, 1.107090, 1.401229, 1.968477",\ + "0.757386, 0.972255, 1.157476, 1.451615, 2.018864",\ + "0.918415, 1.133282, 1.318501, 1.612640, 2.179891",\ + "1.498390, 1.713257, 1.898476, 2.192615, 2.759866",\ + "1.010282, 1.195111, 1.378718, 1.672377, 2.238689",\ + "1.042312, 1.227141, 1.410748, 1.704407, 2.270719",\ + "1.092700, 1.277529, 1.461135, 1.754794, 2.321106",\ + "1.253727, 1.438555, 1.622160, 1.915819, 2.482133",\ + "1.833702, 2.018530, 2.202135, 2.495794, 3.062109"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.029863, 0.029863, 0.029863, 0.029863, 0.029863",\ + "0.059264, 0.059264, 0.059264, 0.059264, 0.059262",\ + "0.131521, 0.131521, 0.131521, 0.131521, 0.131521",\ + "0.417782, 0.417782, 0.417782, 0.417778, 0.417769",\ + "1.484504, 1.484504, 1.484504, 1.484501, 1.484496",\ + "0.029863, 0.029863, 0.029863, 0.029863, 0.029863",\ + "0.059264, 0.059264, 0.059264, 0.059264, 0.059262",\ + "0.131521, 0.131521, 0.131521, 0.131521, 0.131521",\ + "0.417782, 0.417782, 0.417782, 0.417778, 0.417769",\ + "1.484504, 1.484504, 1.484504, 1.484501, 1.484496",\ + "0.029863, 0.029863, 0.029863, 0.029863, 0.029863",\ + "0.059264, 0.059264, 0.059264, 0.059264, 0.059262",\ + "0.131521, 0.131521, 0.131521, 0.131521, 0.131521",\ + "0.417782, 0.417782, 0.417782, 0.417778, 0.417769",\ + "1.484504, 1.484504, 1.484504, 1.484501, 1.484496",\ + "0.029863, 0.029863, 0.029863, 0.029863, 0.029863",\ + "0.059264, 0.059264, 0.059264, 0.059264, 0.059262",\ + "0.131521, 0.131521, 0.131521, 0.131521, 0.131521",\ + "0.417782, 0.417782, 0.417782, 0.417778, 0.417769",\ + "1.484504, 1.484504, 1.484504, 1.484501, 1.484496",\ + "0.029863, 0.029863, 0.029863, 0.029863, 0.029863",\ + "0.059264, 0.059264, 0.059264, 0.059264, 0.059262",\ + "0.131521, 0.131521, 0.131521, 0.131521, 0.131521",\ + "0.417782, 0.417782, 0.417782, 0.417778, 0.417769",\ + "1.484504, 1.484504, 1.484504, 1.484501, 1.484496"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_min_2346*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[46]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.554942, 0.776691, 0.954630, 1.243547, 1.804386",\ + "0.596638, 0.818387, 0.996327, 1.285244, 1.846083",\ + "0.672820, 0.894569, 1.072508, 1.361425, 1.922264",\ + "0.928215, 1.149964, 1.327903, 1.616820, 2.177659",\ + "1.852598, 2.074347, 2.252286, 2.541204, 3.102043",\ + "0.643350, 0.864010, 1.041911, 1.330852, 1.891740",\ + "0.685047, 0.905706, 1.083608, 1.372549, 1.933436",\ + "0.761228, 0.981887, 1.159789, 1.448730, 2.009617",\ + "1.016623, 1.237282, 1.415184, 1.704125, 2.265012",\ + "1.941007, 2.161666, 2.339567, 2.628509, 3.189397",\ + "0.732441, 0.944345, 1.121938, 1.410881, 1.971771",\ + "0.774137, 0.986041, 1.163634, 1.452577, 2.013468",\ + "0.850318, 1.062222, 1.239816, 1.528758, 2.089649",\ + "1.105714, 1.317617, 1.495211, 1.784153, 2.345044",\ + "2.030097, 2.242001, 2.419594, 2.708537, 3.269428",\ + "0.795719, 1.002162, 1.179631, 1.468310, 2.028787",\ + "0.837415, 1.043858, 1.221328, 1.510007, 2.070483",\ + "0.913596, 1.120039, 1.297509, 1.586188, 2.146664",\ + "1.168992, 1.375434, 1.552904, 1.841583, 2.402059",\ + "2.093375, 2.299818, 2.477287, 2.765967, 3.326444",\ + "1.127968, 1.307390, 1.483287, 1.771482, 2.331008",\ + "1.169664, 1.349087, 1.524984, 1.813179, 2.372704",\ + "1.245846, 1.425268, 1.601165, 1.889360, 2.448885",\ + "1.501241, 1.680663, 1.856560, 2.144755, 2.704280",\ + "2.425624, 2.605047, 2.780944, 3.069139, 3.628665"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070069, 0.070069",\ + "0.199414, 0.199414, 0.199414, 0.199414, 0.199414",\ + "0.685793, 0.685793, 0.685793, 0.685794, 0.685795",\ + "2.455201, 2.455201, 2.455201, 2.455201, 2.455200",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070069, 0.070069",\ + "0.199414, 0.199414, 0.199414, 0.199414, 0.199414",\ + "0.685793, 0.685793, 0.685793, 0.685794, 0.685795",\ + "2.455201, 2.455201, 2.455201, 2.455201, 2.455200",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070069, 0.070069",\ + "0.199414, 0.199414, 0.199414, 0.199414, 0.199414",\ + "0.685793, 0.685793, 0.685793, 0.685794, 0.685795",\ + "2.455201, 2.455201, 2.455201, 2.455201, 2.455200",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070069, 0.070069",\ + "0.199414, 0.199414, 0.199414, 0.199414, 0.199414",\ + "0.685793, 0.685793, 0.685793, 0.685794, 0.685795",\ + "2.455201, 2.455201, 2.455201, 2.455201, 2.455200",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070069, 0.070069",\ + "0.199414, 0.199414, 0.199414, 0.199414, 0.199414",\ + "0.685793, 0.685793, 0.685793, 0.685794, 0.685795",\ + "2.455201, 2.455201, 2.455201, 2.455201, 2.455200"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.575187, 0.796936, 0.974876, 1.263793, 1.824632",\ + "0.607437, 0.829186, 1.007125, 1.296042, 1.856881",\ + "0.657749, 0.879498, 1.057438, 1.346354, 1.907194",\ + "0.818413, 1.040162, 1.218101, 1.507018, 2.067857",\ + "1.399546, 1.621294, 1.799234, 2.088151, 2.648989",\ + "0.663596, 0.884255, 1.062156, 1.351098, 1.911985",\ + "0.695845, 0.916504, 1.094406, 1.383347, 1.944234",\ + "0.746158, 0.966817, 1.144718, 1.433660, 1.994547",\ + "0.906821, 1.127481, 1.305382, 1.594323, 2.155211",\ + "1.487954, 1.708613, 1.886515, 2.175456, 2.736343",\ + "0.752686, 0.964590, 1.142183, 1.431126, 1.992017",\ + "0.784936, 0.996840, 1.174433, 1.463375, 2.024266",\ + "0.835248, 1.047152, 1.224745, 1.513688, 2.074579",\ + "0.995912, 1.207816, 1.385409, 1.674352, 2.235242",\ + "1.577044, 1.788948, 1.966541, 2.255484, 2.816375",\ + "0.815964, 1.022407, 1.199876, 1.488556, 2.049032",\ + "0.848214, 1.054656, 1.232126, 1.520805, 2.081281",\ + "0.898526, 1.104969, 1.282438, 1.571118, 2.131594",\ + "1.059190, 1.265632, 1.443102, 1.731781, 2.292258",\ + "1.640322, 1.846765, 2.024235, 2.312914, 2.873390",\ + "1.148213, 1.327636, 1.503533, 1.791728, 2.351253",\ + "1.180463, 1.359885, 1.535782, 1.823977, 2.383502",\ + "1.230775, 1.410198, 1.586095, 1.874290, 2.433815",\ + "1.391439, 1.570861, 1.746758, 2.034954, 2.594479",\ + "1.972571, 2.151994, 2.327891, 2.616086, 3.175611"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\ + "0.419472, 0.419472, 0.419472, 0.419472, 0.419472",\ + "1.482982, 1.482982, 1.482982, 1.482983, 1.482983",\ + "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\ + "0.419472, 0.419472, 0.419472, 0.419472, 0.419472",\ + "1.482982, 1.482982, 1.482982, 1.482983, 1.482983",\ + "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\ + "0.419472, 0.419472, 0.419472, 0.419472, 0.419472",\ + "1.482982, 1.482982, 1.482982, 1.482983, 1.482983",\ + "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\ + "0.419472, 0.419472, 0.419472, 0.419472, 0.419472",\ + "1.482982, 1.482982, 1.482982, 1.482983, 1.482983",\ + "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\ + "0.419472, 0.419472, 0.419472, 0.419472, 0.419472",\ + "1.482982, 1.482982, 1.482982, 1.482983, 1.482983"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_min_2465*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[47]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011"); + values ( "0.533753, 0.762081, 0.946644, 1.241934, 1.812791",\ + "0.575449, 0.803777, 0.988340, 1.283630, 1.854487",\ + "0.651630, 0.879958, 1.064522, 1.359811, 1.930668",\ + "0.907026, 1.135353, 1.319917, 1.615206, 2.186064",\ + "1.831408, 2.059737, 2.244300, 2.539591, 3.110448",\ + "0.622078, 0.849399, 1.033925, 1.329239, 1.900144",\ + "0.663775, 0.891095, 1.075621, 1.370935, 1.941841",\ + "0.739956, 0.967276, 1.151803, 1.447117, 2.018022",\ + "0.995351, 1.222671, 1.407198, 1.702512, 2.273417",\ + "1.919734, 2.147055, 2.331581, 2.626896, 3.197802",\ + "0.711467, 0.929729, 1.113952, 1.409267, 1.980176",\ + "0.753164, 0.971426, 1.155648, 1.450964, 2.021872",\ + "0.829345, 1.047607, 1.231829, 1.527145, 2.098053",\ + "1.084740, 1.303002, 1.487225, 1.782540, 2.353448",\ + "2.009123, 2.227385, 2.411608, 2.706924, 3.277833",\ + "0.775260, 0.987553, 1.171661, 1.466710, 2.037218",\ + "0.816956, 1.029250, 1.213358, 1.508406, 2.078914",\ + "0.893137, 1.105431, 1.289539, 1.584587, 2.155095",\ + "1.148533, 1.360826, 1.544934, 1.839983, 2.410490",\ + "2.072916, 2.285210, 2.469318, 2.764367, 3.334875",\ + "1.112589, 1.292819, 1.475319, 1.769892, 2.339470",\ + "1.154285, 1.334515, 1.517015, 1.811588, 2.381167",\ + "1.230466, 1.410696, 1.593196, 1.887769, 2.457348",\ + "1.485862, 1.666091, 1.848592, 2.143165, 2.712743",\ + "2.410245, 2.590475, 2.772975, 3.067549, 3.637128"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011"); + values ( "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070069, 0.070069",\ + "0.199414, 0.199414, 0.199414, 0.199414, 0.199415",\ + "0.685793, 0.685793, 0.685794, 0.685794, 0.685795",\ + "2.455201, 2.455201, 2.455201, 2.455201, 2.455200",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070069, 0.070069",\ + "0.199414, 0.199414, 0.199414, 0.199414, 0.199415",\ + "0.685793, 0.685793, 0.685794, 0.685794, 0.685795",\ + "2.455201, 2.455201, 2.455201, 2.455201, 2.455200",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070069, 0.070069",\ + "0.199414, 0.199414, 0.199414, 0.199414, 0.199415",\ + "0.685793, 0.685793, 0.685794, 0.685794, 0.685795",\ + "2.455201, 2.455201, 2.455201, 2.455201, 2.455200",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070069, 0.070069",\ + "0.199414, 0.199414, 0.199414, 0.199414, 0.199415",\ + "0.685793, 0.685793, 0.685794, 0.685794, 0.685795",\ + "2.455201, 2.455201, 2.455201, 2.455201, 2.455200",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070069, 0.070069",\ + "0.199414, 0.199414, 0.199414, 0.199414, 0.199415",\ + "0.685793, 0.685793, 0.685794, 0.685794, 0.685795",\ + "2.455201, 2.455201, 2.455201, 2.455201, 2.455200"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011"); + values ( "0.553998, 0.782326, 0.966889, 1.262179, 1.833036",\ + "0.586248, 0.814575, 0.999139, 1.294429, 1.865286",\ + "0.636560, 0.864888, 1.049451, 1.344741, 1.915598",\ + "0.797224, 1.025552, 1.210115, 1.505405, 2.076262",\ + "1.378356, 1.606684, 1.791247, 2.086537, 2.657394",\ + "0.642324, 0.869644, 1.054170, 1.349484, 1.920390",\ + "0.674573, 0.901893, 1.086420, 1.381734, 1.952639",\ + "0.724886, 0.952206, 1.136732, 1.432046, 2.002952",\ + "0.885549, 1.112870, 1.297396, 1.592710, 2.163615",\ + "1.466682, 1.694002, 1.878528, 2.173842, 2.744748",\ + "0.731713, 0.949975, 1.134197, 1.429513, 2.000421",\ + "0.763962, 0.982224, 1.166447, 1.461762, 2.032670",\ + "0.814275, 1.032536, 1.216759, 1.512075, 2.082983",\ + "0.974938, 1.193200, 1.377423, 1.672738, 2.243647",\ + "1.556071, 1.774333, 1.958555, 2.253871, 2.824779",\ + "0.795505, 1.007799, 1.191907, 1.486955, 2.057463",\ + "0.827755, 1.040048, 1.224156, 1.519205, 2.089712",\ + "0.878067, 1.090361, 1.274469, 1.569517, 2.140025",\ + "1.038731, 1.251024, 1.435133, 1.730181, 2.300689",\ + "1.619863, 1.832157, 2.016265, 2.311313, 2.881821",\ + "1.132834, 1.313064, 1.495564, 1.790137, 2.359716",\ + "1.165084, 1.345313, 1.527814, 1.822387, 2.391965",\ + "1.215396, 1.395626, 1.578126, 1.872699, 2.442278",\ + "1.376060, 1.556290, 1.738790, 2.033363, 2.602942",\ + "1.957192, 2.137422, 2.319922, 2.614495, 3.184073"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011"); + values ( "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\ + "0.419472, 0.419472, 0.419472, 0.419472, 0.419472",\ + "1.482982, 1.482982, 1.482982, 1.482983, 1.482983",\ + "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\ + "0.419472, 0.419472, 0.419472, 0.419472, 0.419472",\ + "1.482982, 1.482982, 1.482982, 1.482983, 1.482983",\ + "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\ + "0.419472, 0.419472, 0.419472, 0.419472, 0.419472",\ + "1.482982, 1.482982, 1.482982, 1.482983, 1.482983",\ + "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\ + "0.419472, 0.419472, 0.419472, 0.419472, 0.419472",\ + "1.482982, 1.482982, 1.482982, 1.482983, 1.482983",\ + "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\ + "0.419472, 0.419472, 0.419472, 0.419472, 0.419472",\ + "1.482982, 1.482982, 1.482982, 1.482983, 1.482983"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_min_2401*/ + +} /* end of pin tl_o[6] */ + +pin("tl_o[5]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.035370 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : tl_o[5]; + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[16]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011"); + values ( "0.586415, 0.856406, 1.147453, 1.645288, 2.640958",\ + "0.600096, 0.870093, 1.161170, 1.659087, 2.654921",\ + "0.623625, 0.893621, 1.184696, 1.682603, 2.678417",\ + "0.891636, 1.161662, 1.452904, 1.951255, 2.947956",\ + "1.484832, 1.754906, 2.046407, 2.545443, 3.543516",\ + "0.673827, 0.943991, 1.235112, 1.732003, 2.726892",\ + "0.687508, 0.957678, 1.248830, 1.745802, 2.740855",\ + "0.711038, 0.981207, 1.272355, 1.769318, 2.764350",\ + "0.979048, 1.249249, 1.540565, 2.037970, 3.033889",\ + "1.572245, 1.842492, 2.134070, 2.632158, 3.629450",\ + "0.756613, 1.033065, 1.323078, 1.819625, 2.813847",\ + "0.770294, 1.046752, 1.336796, 1.833425, 2.827810",\ + "0.793824, 1.070281, 1.360321, 1.856940, 2.851305",\ + "1.061835, 1.338323, 1.628531, 2.125592, 3.120844",\ + "1.655032, 1.931567, 2.222036, 2.719780, 3.716405",\ + "0.819991, 1.098835, 1.387222, 1.883539, 2.877356",\ + "0.833672, 1.112521, 1.400940, 1.897338, 2.891319",\ + "0.857202, 1.136050, 1.424465, 1.920853, 2.914814",\ + "1.125213, 1.404093, 1.692675, 2.189505, 3.184353",\ + "1.718410, 1.997339, 2.286180, 2.783694, 3.779914",\ + "1.154701, 1.464769, 1.739384, 2.233007, 3.222812",\ + "1.168382, 1.478458, 1.753102, 2.246807, 3.236775",\ + "1.191912, 1.501987, 1.776627, 2.270322, 3.260271",\ + "1.459925, 1.770039, 2.044842, 2.538976, 3.529809",\ + "2.053125, 2.363301, 2.638354, 3.133168, 4.125370"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011"); + values ( "0.122235, 0.122284, 0.123237, 0.126336, 0.132533",\ + "0.151847, 0.152077, 0.152973, 0.155170, 0.159564",\ + "0.201011, 0.201013, 0.201253, 0.202081, 0.203737",\ + "0.823650, 0.823653, 0.823667, 0.823703, 0.823775",\ + "2.222134, 2.222134, 2.222136, 2.222140, 2.222148",\ + "0.122235, 0.122284, 0.123247, 0.126336, 0.132533",\ + "0.151847, 0.152079, 0.152980, 0.155170, 0.159564",\ + "0.201011, 0.201013, 0.201256, 0.202081, 0.203737",\ + "0.823650, 0.823653, 0.823667, 0.823703, 0.823775",\ + "2.222134, 2.222134, 2.222136, 2.222140, 2.222148",\ + "0.122236, 0.122285, 0.123247, 0.126336, 0.132533",\ + "0.151853, 0.152082, 0.152980, 0.155170, 0.159564",\ + "0.201011, 0.201013, 0.201256, 0.202081, 0.203737",\ + "0.823650, 0.823653, 0.823667, 0.823703, 0.823775",\ + "2.222134, 2.222134, 2.222136, 2.222140, 2.222148",\ + "0.122236, 0.122286, 0.123248, 0.126336, 0.132533",\ + "0.151856, 0.152088, 0.152981, 0.155170, 0.159564",\ + "0.201011, 0.201013, 0.201256, 0.202081, 0.203737",\ + "0.823650, 0.823653, 0.823667, 0.823703, 0.823775",\ + "2.222134, 2.222134, 2.222136, 2.222140, 2.222148",\ + "0.122239, 0.122302, 0.123279, 0.126348, 0.132533",\ + "0.151880, 0.152153, 0.153003, 0.155179, 0.159564",\ + "0.201011, 0.201014, 0.201264, 0.202084, 0.203737",\ + "0.823651, 0.823654, 0.823667, 0.823703, 0.823775",\ + "2.222134, 2.222135, 2.222136, 2.222140, 2.222148"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011"); + values ( "0.525645, 0.795489, 1.085730, 1.581432, 2.572836",\ + "0.537639, 0.807524, 1.097989, 1.594284, 2.586873",\ + "0.557233, 0.827173, 1.117941, 1.615037, 2.609230",\ + "0.728499, 0.998614, 1.290344, 1.789985, 2.789268",\ + "1.063132, 1.333237, 1.624904, 2.124381, 3.123334",\ + "0.613058, 0.883074, 1.173382, 1.668147, 2.658770",\ + "0.625052, 0.895109, 1.185643, 1.680999, 2.672807",\ + "0.644646, 0.914759, 1.205598, 1.701752, 2.695163",\ + "0.815911, 1.086201, 1.378008, 1.876700, 2.875202",\ + "1.150545, 1.420823, 1.712568, 2.211096, 3.209268",\ + "0.695842, 0.972144, 1.261348, 1.755769, 2.745725",\ + "0.707837, 0.984180, 1.273609, 1.768621, 2.759762",\ + "0.727431, 1.003831, 1.293564, 1.789375, 2.782119",\ + "0.898699, 1.175277, 1.465974, 1.964322, 2.962157",\ + "1.233333, 1.509899, 1.800534, 2.298718, 3.296223",\ + "0.759218, 1.037910, 1.325492, 1.819683, 2.809234",\ + "0.771213, 1.049947, 1.337753, 1.832534, 2.823271",\ + "0.790808, 1.069599, 1.357708, 1.853288, 2.845628",\ + "0.962077, 1.241050, 1.530119, 2.028236, 3.025666",\ + "1.296711, 1.575672, 1.864679, 2.362631, 3.359732",\ + "1.093920, 1.403797, 1.677632, 2.169142, 3.154690",\ + "1.105917, 1.415847, 1.689899, 2.181997, 3.168727",\ + "1.125515, 1.435517, 1.709862, 2.202754, 3.191083",\ + "1.296794, 1.607024, 1.882299, 2.377712, 3.371122",\ + "1.631427, 1.941643, 2.216857, 2.712107, 3.705188"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011"); + values ( "0.074841, 0.075254, 0.077521, 0.083520, 0.095518",\ + "0.080316, 0.080691, 0.082745, 0.088181, 0.099053",\ + "0.100360, 0.100711, 0.102633, 0.107721, 0.117897",\ + "0.380688, 0.380691, 0.380703, 0.380732, 0.380789",\ + "1.025905, 1.025920, 1.025979, 1.026125, 1.026416",\ + "0.074841, 0.075258, 0.077540, 0.083520, 0.095518",\ + "0.080316, 0.080694, 0.082762, 0.088181, 0.099053",\ + "0.100360, 0.100714, 0.102649, 0.107721, 0.117897",\ + "0.380688, 0.380691, 0.380703, 0.380732, 0.380789",\ + "1.025905, 1.025920, 1.025980, 1.026125, 1.026416",\ + "0.074846, 0.075266, 0.077540, 0.083520, 0.095518",\ + "0.080321, 0.080701, 0.082762, 0.088181, 0.099053",\ + "0.100365, 0.100721, 0.102650, 0.107721, 0.117897",\ + "0.380688, 0.380691, 0.380703, 0.380732, 0.380789",\ + "1.025905, 1.025920, 1.025980, 1.026125, 1.026416",\ + "0.074850, 0.075277, 0.077541, 0.083520, 0.095518",\ + "0.080324, 0.080712, 0.082763, 0.088181, 0.099053",\ + "0.100368, 0.100730, 0.102651, 0.107721, 0.117897",\ + "0.380688, 0.380691, 0.380703, 0.380732, 0.380789",\ + "1.025905, 1.025921, 1.025980, 1.026125, 1.026416",\ + "0.074873, 0.075411, 0.077602, 0.083545, 0.095518",\ + "0.080345, 0.080833, 0.082819, 0.088203, 0.099053",\ + "0.100387, 0.100844, 0.102702, 0.107742, 0.117897",\ + "0.380688, 0.380692, 0.380703, 0.380732, 0.380789",\ + "1.025907, 1.025925, 1.025981, 1.026126, 1.026416"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_2627*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[20]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.792764, 1.054507, 1.346593, 1.853632, 2.867709",\ + "0.806316, 1.068059, 1.360145, 1.867184, 2.881261",\ + "0.829846, 1.091589, 1.383675, 1.890714, 2.904791",\ + "1.097219, 1.358962, 1.651048, 2.158087, 3.172164",\ + "1.691027, 1.952770, 2.244857, 2.751895, 3.765972",\ + "0.880176, 1.142082, 1.434281, 1.940346, 2.953642",\ + "0.893728, 1.155634, 1.447833, 1.953899, 2.967195",\ + "0.917258, 1.179164, 1.471363, 1.977429, 2.990725",\ + "1.184632, 1.446538, 1.738737, 2.244802, 3.258098",\ + "1.778440, 2.040346, 2.332545, 2.838610, 3.851906",\ + "0.961078, 1.231132, 1.522248, 2.027969, 3.040597",\ + "0.974630, 1.244684, 1.535800, 2.041521, 3.054150",\ + "0.998160, 1.268215, 1.559330, 2.065051, 3.077680",\ + "1.265533, 1.535588, 1.826703, 2.332424, 3.345053",\ + "1.859341, 2.129396, 2.420511, 2.926232, 3.938861",\ + "1.020773, 1.296868, 1.586394, 2.091882, 3.104106",\ + "1.034325, 1.310420, 1.599946, 2.105434, 3.117659",\ + "1.057855, 1.333951, 1.623476, 2.128964, 3.141189",\ + "1.325228, 1.601324, 1.890849, 2.396338, 3.408562",\ + "1.919036, 2.195132, 2.484657, 2.990146, 4.002370",\ + "1.354614, 1.662408, 1.938648, 2.441389, 3.449563",\ + "1.368166, 1.675960, 1.952201, 2.454941, 3.463115",\ + "1.391696, 1.699491, 1.975731, 2.478471, 3.486645",\ + "1.659069, 1.966864, 2.243104, 2.745844, 3.754018",\ + "2.252877, 2.560672, 2.836912, 3.339653, 4.347826"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.121333, 0.121333, 0.121333, 0.121333, 0.121333",\ + "0.151701, 0.151701, 0.151701, 0.151701, 0.151701",\ + "0.201129, 0.201129, 0.201129, 0.201129, 0.201129",\ + "0.823409, 0.823409, 0.823409, 0.823409, 0.823409",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121333, 0.121333, 0.121333, 0.121333, 0.121333",\ + "0.151701, 0.151701, 0.151701, 0.151701, 0.151701",\ + "0.201129, 0.201129, 0.201129, 0.201129, 0.201129",\ + "0.823409, 0.823409, 0.823409, 0.823409, 0.823409",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121333, 0.121333, 0.121333, 0.121333, 0.121333",\ + "0.151701, 0.151701, 0.151701, 0.151701, 0.151701",\ + "0.201129, 0.201129, 0.201129, 0.201129, 0.201129",\ + "0.823409, 0.823409, 0.823409, 0.823409, 0.823409",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121333, 0.121333, 0.121333, 0.121333, 0.121333",\ + "0.151701, 0.151701, 0.151701, 0.151701, 0.151701",\ + "0.201129, 0.201129, 0.201129, 0.201129, 0.201129",\ + "0.823409, 0.823409, 0.823409, 0.823409, 0.823409",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121333, 0.121333, 0.121333, 0.121333, 0.121333",\ + "0.151701, 0.151701, 0.151701, 0.151701, 0.151701",\ + "0.201129, 0.201129, 0.201129, 0.201129, 0.201129",\ + "0.823409, 0.823409, 0.823409, 0.823409, 0.823409",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.760378, 1.022121, 1.314208, 1.821246, 2.835323",\ + "0.768321, 1.030064, 1.322150, 1.829189, 2.843266",\ + "0.781801, 1.043544, 1.335630, 1.842669, 2.856746",\ + "0.935753, 1.197497, 1.489583, 1.996622, 3.010698",\ + "1.275653, 1.537396, 1.829482, 2.336521, 3.350598",\ + "0.847791, 1.109697, 1.401896, 1.907961, 2.921257",\ + "0.855733, 1.117639, 1.409838, 1.915904, 2.929199",\ + "0.869213, 1.131119, 1.423318, 1.929384, 2.942679",\ + "1.023166, 1.285072, 1.577271, 2.083336, 3.096632",\ + "1.363066, 1.624972, 1.917171, 2.423236, 3.436532",\ + "0.928693, 1.198747, 1.489862, 1.995583, 3.008212",\ + "0.936635, 1.206689, 1.497805, 2.003526, 3.016155",\ + "0.950115, 1.220170, 1.511285, 2.017006, 3.029634",\ + "1.104068, 1.374122, 1.665238, 2.170959, 3.183587",\ + "1.443967, 1.714022, 2.005137, 2.510858, 3.523487",\ + "0.988388, 1.264483, 1.554008, 2.059497, 3.071721",\ + "0.996330, 1.272425, 1.561951, 2.067439, 3.079664",\ + "1.009810, 1.285905, 1.575431, 2.080919, 3.093143",\ + "1.163763, 1.439858, 1.729384, 2.234872, 3.247096",\ + "1.503662, 1.779758, 2.069283, 2.574772, 3.586996",\ + "1.322228, 1.630023, 1.906263, 2.409003, 3.417177",\ + "1.330171, 1.637965, 1.914206, 2.416946, 3.425119",\ + "1.343651, 1.651445, 1.927685, 2.430426, 3.438600",\ + "1.497604, 1.805398, 2.081638, 2.584379, 3.592552",\ + "1.837503, 2.145298, 2.421538, 2.924278, 3.932452"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.061223, 0.061223, 0.061223, 0.061223, 0.061223",\ + "0.068571, 0.068571, 0.068571, 0.068571, 0.068571",\ + "0.090396, 0.090396, 0.090396, 0.090396, 0.090396",\ + "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\ + "1.025895, 1.025895, 1.025895, 1.025895, 1.025895",\ + "0.061223, 0.061223, 0.061223, 0.061223, 0.061223",\ + "0.068571, 0.068571, 0.068571, 0.068571, 0.068571",\ + "0.090396, 0.090396, 0.090396, 0.090396, 0.090396",\ + "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\ + "1.025895, 1.025895, 1.025895, 1.025895, 1.025895",\ + "0.061223, 0.061223, 0.061223, 0.061223, 0.061223",\ + "0.068571, 0.068571, 0.068571, 0.068571, 0.068571",\ + "0.090396, 0.090396, 0.090396, 0.090396, 0.090396",\ + "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\ + "1.025895, 1.025895, 1.025895, 1.025895, 1.025895",\ + "0.061223, 0.061223, 0.061223, 0.061223, 0.061223",\ + "0.068571, 0.068571, 0.068571, 0.068571, 0.068571",\ + "0.090396, 0.090396, 0.090396, 0.090396, 0.090396",\ + "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\ + "1.025895, 1.025895, 1.025895, 1.025895, 1.025895",\ + "0.061223, 0.061223, 0.061223, 0.061223, 0.061223",\ + "0.068571, 0.068571, 0.068571, 0.068571, 0.068571",\ + "0.090396, 0.090396, 0.090396, 0.090396, 0.090396",\ + "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\ + "1.025895, 1.025895, 1.025895, 1.025895, 1.025895"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_2734*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[22]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.773575, 1.028253, 1.310824, 1.779371, 2.716465",\ + "0.787127, 1.041805, 1.324376, 1.792923, 2.730017",\ + "0.810657, 1.065335, 1.347906, 1.816453, 2.753547",\ + "1.078030, 1.332708, 1.615279, 2.083826, 3.020920",\ + "1.671839, 1.926517, 2.209088, 2.677635, 3.614729",\ + "0.860984, 1.115846, 1.398389, 1.866085, 2.802399",\ + "0.874536, 1.129398, 1.411941, 1.879637, 2.815951",\ + "0.898067, 1.152928, 1.435471, 1.903167, 2.839481",\ + "1.165440, 1.420301, 1.702844, 2.170541, 3.106854",\ + "1.759248, 2.014110, 2.296653, 2.764349, 3.700663",\ + "0.941840, 1.204919, 1.486352, 1.953707, 2.889354",\ + "0.955392, 1.218471, 1.499904, 1.967259, 2.902906",\ + "0.978923, 1.242001, 1.523435, 1.990789, 2.926436",\ + "1.246296, 1.509374, 1.790808, 2.258162, 3.193809",\ + "1.840104, 2.103183, 2.384616, 2.851971, 3.787618",\ + "0.999500, 1.270687, 1.550492, 2.017620, 2.952863",\ + "1.013052, 1.284239, 1.564044, 2.031172, 2.966415",\ + "1.036583, 1.307769, 1.587574, 2.054702, 2.989945",\ + "1.303956, 1.575142, 1.854947, 2.322075, 3.257318",\ + "1.897764, 2.168951, 2.448756, 2.915884, 3.851127",\ + "1.331207, 1.636652, 1.902354, 2.366964, 3.298319",\ + "1.344759, 1.650204, 1.915906, 2.380516, 3.311871",\ + "1.368289, 1.673734, 1.939437, 2.404047, 3.335401",\ + "1.635662, 1.941107, 2.206810, 2.671420, 3.602774",\ + "2.229471, 2.534916, 2.800618, 3.265228, 4.196583"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.121333, 0.121333, 0.121333, 0.121333, 0.121333",\ + "0.151701, 0.151701, 0.151701, 0.151701, 0.151701",\ + "0.201129, 0.201129, 0.201129, 0.201129, 0.201129",\ + "0.823409, 0.823409, 0.823409, 0.823409, 0.823409",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121333, 0.121333, 0.121333, 0.121333, 0.121333",\ + "0.151701, 0.151701, 0.151701, 0.151701, 0.151701",\ + "0.201129, 0.201129, 0.201129, 0.201129, 0.201129",\ + "0.823409, 0.823409, 0.823409, 0.823409, 0.823409",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121333, 0.121333, 0.121333, 0.121333, 0.121333",\ + "0.151701, 0.151701, 0.151701, 0.151701, 0.151701",\ + "0.201129, 0.201129, 0.201129, 0.201129, 0.201129",\ + "0.823409, 0.823409, 0.823409, 0.823409, 0.823409",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121333, 0.121333, 0.121333, 0.121333, 0.121333",\ + "0.151701, 0.151701, 0.151701, 0.151701, 0.151701",\ + "0.201129, 0.201129, 0.201129, 0.201129, 0.201129",\ + "0.823409, 0.823409, 0.823409, 0.823409, 0.823409",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121333, 0.121333, 0.121333, 0.121333, 0.121333",\ + "0.151701, 0.151701, 0.151701, 0.151701, 0.151701",\ + "0.201129, 0.201129, 0.201129, 0.201129, 0.201129",\ + "0.823409, 0.823409, 0.823409, 0.823409, 0.823409",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.741190, 0.995868, 1.278439, 1.746986, 2.684080",\ + "0.749133, 1.003811, 1.286381, 1.754929, 2.692023",\ + "0.762613, 1.017291, 1.299861, 1.768409, 2.705503",\ + "0.916565, 1.171243, 1.453814, 1.922361, 2.859455",\ + "1.256465, 1.511143, 1.793714, 2.262261, 3.199355",\ + "0.828600, 1.083461, 1.366004, 1.833700, 2.770014",\ + "0.836542, 1.091403, 1.373946, 1.841643, 2.777956",\ + "0.850022, 1.104883, 1.387426, 1.855123, 2.791436",\ + "1.003975, 1.258836, 1.541379, 2.009076, 2.945389",\ + "1.343874, 1.598736, 1.881279, 2.348975, 3.285289",\ + "0.909456, 1.172534, 1.453968, 1.921322, 2.856969",\ + "0.917398, 1.180476, 1.461910, 1.929265, 2.864911",\ + "0.930878, 1.193956, 1.475390, 1.942744, 2.878391",\ + "1.084831, 1.347909, 1.629343, 2.096697, 3.032344",\ + "1.424730, 1.687809, 1.969242, 2.436597, 3.372244",\ + "0.967116, 1.238302, 1.518107, 1.985235, 2.920478",\ + "0.975058, 1.246245, 1.526050, 1.993178, 2.928420",\ + "0.988538, 1.259725, 1.539530, 2.006658, 2.941900",\ + "1.142491, 1.413677, 1.693483, 2.160611, 3.095853",\ + "1.482390, 1.753577, 2.033382, 2.500510, 3.435753",\ + "1.298822, 1.604267, 1.869970, 2.334579, 3.265934",\ + "1.306764, 1.612210, 1.877912, 2.342522, 3.273876",\ + "1.320244, 1.625690, 1.891392, 2.356002, 3.287356",\ + "1.474197, 1.779642, 2.045345, 2.509955, 3.441309",\ + "1.814097, 2.119542, 2.385244, 2.849854, 3.781209"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.061223, 0.061223, 0.061223, 0.061223, 0.061223",\ + "0.068571, 0.068571, 0.068571, 0.068571, 0.068571",\ + "0.090396, 0.090396, 0.090396, 0.090396, 0.090396",\ + "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\ + "1.025895, 1.025895, 1.025895, 1.025895, 1.025895",\ + "0.061223, 0.061223, 0.061223, 0.061223, 0.061223",\ + "0.068571, 0.068571, 0.068571, 0.068571, 0.068571",\ + "0.090396, 0.090396, 0.090396, 0.090396, 0.090396",\ + "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\ + "1.025895, 1.025895, 1.025895, 1.025895, 1.025895",\ + "0.061223, 0.061223, 0.061223, 0.061223, 0.061223",\ + "0.068571, 0.068571, 0.068571, 0.068571, 0.068571",\ + "0.090396, 0.090396, 0.090396, 0.090396, 0.090396",\ + "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\ + "1.025895, 1.025895, 1.025895, 1.025895, 1.025895",\ + "0.061223, 0.061223, 0.061223, 0.061223, 0.061223",\ + "0.068571, 0.068571, 0.068571, 0.068571, 0.068571",\ + "0.090396, 0.090396, 0.090396, 0.090396, 0.090396",\ + "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\ + "1.025895, 1.025895, 1.025895, 1.025895, 1.025895",\ + "0.061223, 0.061223, 0.061223, 0.061223, 0.061223",\ + "0.068571, 0.068571, 0.068571, 0.068571, 0.068571",\ + "0.090396, 0.090396, 0.090396, 0.090396, 0.090396",\ + "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\ + "1.025895, 1.025895, 1.025895, 1.025895, 1.025895"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[5]_redg*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[23]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011"); + values ( "0.741012, 0.979467, 1.257014, 1.743332, 2.715968",\ + "0.754606, 0.993061, 1.270608, 1.756926, 2.729561",\ + "0.778146, 1.016601, 1.294148, 1.780466, 2.753102",\ + "1.045683, 1.284138, 1.561685, 2.048002, 3.020638",\ + "1.638147, 1.876602, 2.154149, 2.640466, 3.613101",\ + "0.828421, 1.066996, 1.344635, 1.830046, 2.801901",\ + "0.842015, 1.080589, 1.358228, 1.843640, 2.815495",\ + "0.865555, 1.104130, 1.381769, 1.867180, 2.839035",\ + "1.133092, 1.371667, 1.649306, 2.134717, 3.106571",\ + "1.725556, 1.964131, 2.241770, 2.727180, 3.699034",\ + "0.909283, 1.155921, 1.432599, 1.917668, 2.888856",\ + "0.922877, 1.169514, 1.446193, 1.931262, 2.902450",\ + "0.946417, 1.193055, 1.469733, 1.954802, 2.925990",\ + "1.213954, 1.460592, 1.737270, 2.222339, 3.193527",\ + "1.806418, 2.053056, 2.329734, 2.814802, 3.785990",\ + "0.966958, 1.221474, 1.496742, 1.981581, 2.952365",\ + "0.980552, 1.235068, 1.510336, 1.995175, 2.965959",\ + "1.004092, 1.258608, 1.533876, 2.018715, 2.989499",\ + "1.271629, 1.526145, 1.801413, 2.286252, 3.257035",\ + "1.864093, 2.118609, 2.393877, 2.878715, 3.849499",\ + "1.288363, 1.584928, 1.848784, 2.330998, 3.297822",\ + "1.301956, 1.598522, 1.862378, 2.344592, 3.311415",\ + "1.325497, 1.622062, 1.885918, 2.368132, 3.334955",\ + "1.593034, 1.889599, 2.153455, 2.635669, 3.602492",\ + "2.185498, 2.482063, 2.745919, 3.228132, 4.194955"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011"); + values ( "0.121485, 0.121485, 0.121485, 0.121485, 0.121484",\ + "0.152032, 0.152032, 0.152032, 0.152031, 0.152028",\ + "0.200984, 0.200984, 0.200984, 0.200984, 0.200984",\ + "0.823612, 0.823612, 0.823612, 0.823612, 0.823612",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121485, 0.121485, 0.121485, 0.121485, 0.121484",\ + "0.152032, 0.152032, 0.152032, 0.152031, 0.152028",\ + "0.200984, 0.200984, 0.200984, 0.200984, 0.200984",\ + "0.823612, 0.823612, 0.823612, 0.823612, 0.823612",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121485, 0.121485, 0.121485, 0.121485, 0.121484",\ + "0.152032, 0.152032, 0.152032, 0.152031, 0.152028",\ + "0.200984, 0.200984, 0.200984, 0.200984, 0.200984",\ + "0.823612, 0.823612, 0.823612, 0.823612, 0.823612",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121485, 0.121485, 0.121485, 0.121485, 0.121484",\ + "0.152032, 0.152032, 0.152032, 0.152031, 0.152028",\ + "0.200984, 0.200984, 0.200984, 0.200984, 0.200984",\ + "0.823612, 0.823612, 0.823612, 0.823612, 0.823612",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121485, 0.121485, 0.121485, 0.121485, 0.121484",\ + "0.152032, 0.152032, 0.152032, 0.152031, 0.152028",\ + "0.200984, 0.200984, 0.200984, 0.200984, 0.200984",\ + "0.823612, 0.823612, 0.823612, 0.823612, 0.823612",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011"); + values ( "0.682520, 0.920976, 1.198522, 1.684841, 2.657480",\ + "0.693882, 0.932337, 1.209884, 1.696203, 2.668840",\ + "0.712620, 0.951075, 1.228621, 1.714940, 2.687577",\ + "0.881167, 1.119623, 1.397169, 1.883486, 2.856120",\ + "1.215977, 1.454432, 1.731979, 2.218296, 3.190930",\ + "0.769929, 1.008504, 1.286143, 1.771556, 2.743413",\ + "0.781291, 1.019865, 1.297505, 1.782917, 2.754774",\ + "0.800029, 1.038603, 1.316242, 1.801654, 2.773510",\ + "0.968576, 1.207151, 1.484790, 1.970200, 2.942054",\ + "1.303386, 1.541960, 1.819599, 2.305010, 3.276864",\ + "0.850791, 1.097429, 1.374108, 1.859177, 2.830368",\ + "0.862152, 1.108790, 1.385469, 1.870539, 2.841729",\ + "0.880890, 1.127528, 1.404207, 1.889276, 2.860465",\ + "1.049438, 1.296076, 1.572754, 2.057822, 3.029009",\ + "1.384248, 1.630886, 1.907564, 2.392632, 3.363819",\ + "0.908466, 1.162982, 1.438250, 1.923091, 2.893877",\ + "0.919828, 1.174344, 1.449612, 1.934452, 2.905238",\ + "0.938565, 1.193082, 1.468349, 1.953189, 2.923974",\ + "1.107113, 1.361629, 1.636897, 2.121735, 3.092518",\ + "1.441923, 1.696439, 1.971707, 2.456545, 3.427328",\ + "1.229871, 1.526436, 1.790293, 2.272508, 3.239333",\ + "1.241232, 1.537798, 1.801654, 2.283869, 3.250694",\ + "1.259970, 1.556535, 1.820392, 2.302606, 3.269430",\ + "1.428518, 1.725083, 1.988939, 2.471152, 3.437974",\ + "1.763328, 2.059893, 2.323749, 2.805962, 3.772784"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011"); + values ( "0.068436, 0.068436, 0.068435, 0.068432, 0.068425",\ + "0.074512, 0.074512, 0.074511, 0.074509, 0.074503",\ + "0.094928, 0.094928, 0.094927, 0.094924, 0.094919",\ + "0.380690, 0.380690, 0.380690, 0.380690, 0.380690",\ + "1.025917, 1.025917, 1.025917, 1.025917, 1.025917",\ + "0.068436, 0.068436, 0.068435, 0.068432, 0.068425",\ + "0.074512, 0.074512, 0.074511, 0.074509, 0.074503",\ + "0.094928, 0.094928, 0.094927, 0.094924, 0.094919",\ + "0.380690, 0.380690, 0.380690, 0.380690, 0.380690",\ + "1.025917, 1.025917, 1.025917, 1.025917, 1.025917",\ + "0.068436, 0.068436, 0.068435, 0.068432, 0.068425",\ + "0.074512, 0.074512, 0.074511, 0.074509, 0.074503",\ + "0.094928, 0.094928, 0.094927, 0.094924, 0.094919",\ + "0.380690, 0.380690, 0.380690, 0.380690, 0.380690",\ + "1.025917, 1.025917, 1.025917, 1.025917, 1.025917",\ + "0.068436, 0.068436, 0.068435, 0.068432, 0.068425",\ + "0.074512, 0.074512, 0.074511, 0.074509, 0.074503",\ + "0.094928, 0.094928, 0.094927, 0.094924, 0.094919",\ + "0.380690, 0.380690, 0.380690, 0.380690, 0.380690",\ + "1.025917, 1.025917, 1.025917, 1.025917, 1.025917",\ + "0.068436, 0.068436, 0.068435, 0.068432, 0.068425",\ + "0.074512, 0.074512, 0.074511, 0.074509, 0.074503",\ + "0.094928, 0.094928, 0.094927, 0.094924, 0.094919",\ + "0.380690, 0.380690, 0.380690, 0.380690, 0.380690",\ + "1.025917, 1.025917, 1.025917, 1.025917, 1.025917"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_2374*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[25]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011"); + values ( "0.697898, 0.947965, 1.225734, 1.724852, 2.723087",\ + "0.711492, 0.961559, 1.239327, 1.738445, 2.736680",\ + "0.735032, 0.985099, 1.262868, 1.761985, 2.760221",\ + "1.002569, 1.252636, 1.530404, 2.029521, 3.027754",\ + "1.595033, 1.845100, 2.122868, 2.621982, 3.620212",\ + "0.785303, 1.035477, 1.313393, 1.811565, 2.809021",\ + "0.798897, 1.049071, 1.326987, 1.825159, 2.822614",\ + "0.822437, 1.072611, 1.350527, 1.848699, 2.846154",\ + "1.089974, 1.340148, 1.618063, 2.116235, 3.113688",\ + "1.682438, 1.932612, 2.210527, 2.708696, 3.706145",\ + "0.866148, 1.124350, 1.401358, 1.899186, 2.895976",\ + "0.879741, 1.137944, 1.414951, 1.912780, 2.909569",\ + "0.903282, 1.161484, 1.438491, 1.936320, 2.933109",\ + "1.170819, 1.429021, 1.706028, 2.203856, 3.200643",\ + "1.763283, 2.021485, 2.298491, 2.796317, 3.793100",\ + "0.926036, 1.189827, 1.465502, 1.963099, 2.959485",\ + "0.939630, 1.203421, 1.479096, 1.976693, 2.973078",\ + "0.963170, 1.226961, 1.502636, 2.000233, 2.996618",\ + "1.230707, 1.494498, 1.770173, 2.267768, 3.264152",\ + "1.823171, 2.086962, 2.362636, 2.860230, 3.856609",\ + "1.263356, 1.552433, 1.817672, 2.312566, 3.304941",\ + "1.276949, 1.566026, 1.831266, 2.326159, 3.318534",\ + "1.300490, 1.589567, 1.854806, 2.349699, 3.342074",\ + "1.568027, 1.857104, 2.122343, 2.617235, 3.609608",\ + "2.160491, 2.449568, 2.714806, 3.209696, 4.202065"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011"); + values ( "0.121485, 0.121485, 0.121485, 0.121483, 0.121479",\ + "0.152032, 0.152032, 0.152035, 0.152046, 0.152069",\ + "0.200984, 0.200984, 0.200984, 0.200984, 0.200984",\ + "0.823612, 0.823612, 0.823612, 0.823612, 0.823611",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121485, 0.121485, 0.121485, 0.121483, 0.121479",\ + "0.152032, 0.152032, 0.152035, 0.152046, 0.152069",\ + "0.200984, 0.200984, 0.200984, 0.200984, 0.200984",\ + "0.823612, 0.823612, 0.823612, 0.823612, 0.823611",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121485, 0.121485, 0.121485, 0.121483, 0.121479",\ + "0.152032, 0.152032, 0.152035, 0.152046, 0.152069",\ + "0.200984, 0.200984, 0.200984, 0.200984, 0.200984",\ + "0.823612, 0.823612, 0.823612, 0.823612, 0.823611",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121485, 0.121485, 0.121485, 0.121483, 0.121479",\ + "0.152032, 0.152032, 0.152035, 0.152046, 0.152069",\ + "0.200984, 0.200984, 0.200984, 0.200984, 0.200984",\ + "0.823612, 0.823612, 0.823612, 0.823612, 0.823611",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121485, 0.121485, 0.121485, 0.121483, 0.121479",\ + "0.152032, 0.152032, 0.152035, 0.152046, 0.152069",\ + "0.200984, 0.200984, 0.200984, 0.200984, 0.200984",\ + "0.823612, 0.823612, 0.823612, 0.823612, 0.823611",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011"); + values ( "0.639406, 0.889474, 1.167244, 1.666367, 2.664614",\ + "0.650768, 0.900835, 1.178605, 1.677727, 2.675971",\ + "0.669506, 0.919573, 1.197342, 1.696462, 2.694701",\ + "0.838053, 1.088120, 1.365887, 1.865001, 2.863227",\ + "1.172863, 1.422930, 1.700697, 2.199811, 3.198038",\ + "0.726812, 0.976986, 1.254903, 1.753081, 2.750548",\ + "0.738173, 0.988347, 1.266264, 1.764440, 2.761904",\ + "0.756911, 1.007085, 1.285001, 1.783175, 2.780635",\ + "0.925458, 1.175632, 1.453547, 1.951714, 2.949161",\ + "1.260268, 1.510442, 1.788356, 2.286525, 3.283972",\ + "0.807656, 1.065858, 1.342867, 1.840702, 2.837503",\ + "0.819017, 1.077220, 1.354228, 1.852061, 2.848859",\ + "0.837755, 1.095958, 1.372966, 1.870796, 2.867590",\ + "1.006303, 1.264505, 1.541511, 2.039335, 3.036116",\ + "1.341113, 1.599315, 1.876321, 2.374146, 3.370927",\ + "0.867545, 1.131335, 1.407012, 1.904615, 2.901012",\ + "0.878906, 1.142697, 1.418373, 1.915974, 2.912368",\ + "0.897644, 1.161434, 1.437110, 1.934709, 2.931099",\ + "1.066191, 1.329982, 1.605656, 2.103248, 3.099625",\ + "1.401001, 1.664792, 1.940466, 2.438058, 3.434436",\ + "1.204864, 1.493941, 1.759182, 2.254081, 3.246468",\ + "1.216225, 1.505302, 1.770543, 2.265441, 3.257824",\ + "1.234963, 1.524040, 1.789280, 2.284176, 3.276555",\ + "1.403511, 1.692588, 1.957826, 2.452714, 3.445081",\ + "1.738321, 2.027398, 2.292636, 2.787525, 3.779892"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011"); + values ( "0.068435, 0.068435, 0.068431, 0.068415, 0.068383",\ + "0.074512, 0.074512, 0.074508, 0.074493, 0.074464",\ + "0.094928, 0.094928, 0.094924, 0.094910, 0.094883",\ + "0.380690, 0.380690, 0.380690, 0.380690, 0.380691",\ + "1.025917, 1.025917, 1.025917, 1.025918, 1.025919",\ + "0.068435, 0.068435, 0.068431, 0.068415, 0.068383",\ + "0.074512, 0.074512, 0.074508, 0.074493, 0.074464",\ + "0.094928, 0.094928, 0.094924, 0.094910, 0.094883",\ + "0.380690, 0.380690, 0.380690, 0.380690, 0.380691",\ + "1.025917, 1.025917, 1.025917, 1.025918, 1.025919",\ + "0.068435, 0.068435, 0.068431, 0.068415, 0.068383",\ + "0.074512, 0.074512, 0.074508, 0.074493, 0.074464",\ + "0.094928, 0.094928, 0.094924, 0.094910, 0.094883",\ + "0.380690, 0.380690, 0.380690, 0.380690, 0.380691",\ + "1.025917, 1.025917, 1.025917, 1.025918, 1.025919",\ + "0.068435, 0.068435, 0.068431, 0.068415, 0.068383",\ + "0.074512, 0.074512, 0.074508, 0.074493, 0.074464",\ + "0.094928, 0.094928, 0.094924, 0.094910, 0.094883",\ + "0.380690, 0.380690, 0.380690, 0.380690, 0.380691",\ + "1.025917, 1.025917, 1.025917, 1.025918, 1.025919",\ + "0.068435, 0.068435, 0.068430, 0.068415, 0.068383",\ + "0.074512, 0.074512, 0.074507, 0.074493, 0.074464",\ + "0.094928, 0.094928, 0.094923, 0.094910, 0.094883",\ + "0.380690, 0.380690, 0.380690, 0.380690, 0.380691",\ + "1.025917, 1.025917, 1.025917, 1.025918, 1.025919"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_2490*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[26]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011"); + values ( "0.564894, 0.815791, 1.094396, 1.559341, 2.489231",\ + "0.578576, 0.829479, 1.108111, 1.573121, 2.503140",\ + "0.602105, 0.853007, 1.131636, 1.596638, 2.526642",\ + "0.870117, 1.121053, 1.399829, 1.865184, 2.795893",\ + "1.463316, 1.714304, 1.993307, 2.459207, 3.391007",\ + "0.652304, 0.903365, 1.181950, 1.646055, 2.575164",\ + "0.665985, 0.917053, 1.195665, 1.659835, 2.589074",\ + "0.689515, 0.940582, 1.219190, 1.683353, 2.612576",\ + "0.957527, 1.208627, 1.487384, 1.951898, 2.881827",\ + "1.550725, 1.801879, 2.080863, 2.545921, 3.476941",\ + "0.733136, 0.992396, 1.269913, 1.733677, 2.662119",\ + "0.746817, 1.006083, 1.283628, 1.747457, 2.676029",\ + "0.770346, 1.029612, 1.307153, 1.770974, 2.699531",\ + "1.038358, 1.297659, 1.575347, 2.039520, 2.968782",\ + "1.631557, 1.890911, 2.168827, 2.633543, 3.563896",\ + "0.790750, 1.058102, 1.334052, 1.797590, 2.725628",\ + "0.804431, 1.071790, 1.347767, 1.811370, 2.739538",\ + "0.827961, 1.095319, 1.371293, 1.834888, 2.763040",\ + "1.095973, 1.363366, 1.639486, 2.103433, 3.032291",\ + "1.689171, 1.956620, 2.232966, 2.697456, 3.627405",\ + "1.120458, 1.423346, 1.685878, 2.146919, 3.071084",\ + "1.134140, 1.437036, 1.699593, 2.160699, 3.084994",\ + "1.157669, 1.460564, 1.723119, 2.184217, 3.108496",\ + "1.425683, 1.728623, 1.991316, 2.452764, 3.377747",\ + "2.018884, 2.321894, 2.584802, 3.046790, 3.972861"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011"); + values ( "0.122237, 0.122291, 0.122948, 0.124971, 0.129018",\ + "0.151797, 0.151880, 0.152446, 0.154040, 0.157229",\ + "0.201011, 0.201013, 0.201172, 0.201712, 0.202792",\ + "0.823650, 0.823653, 0.823665, 0.823694, 0.823752",\ + "2.222134, 2.222134, 2.222135, 2.222138, 2.222144",\ + "0.122237, 0.122291, 0.122954, 0.124971, 0.129018",\ + "0.151797, 0.151881, 0.152451, 0.154040, 0.157229",\ + "0.201011, 0.201013, 0.201174, 0.201712, 0.202792",\ + "0.823650, 0.823653, 0.823665, 0.823694, 0.823752",\ + "2.222134, 2.222134, 2.222135, 2.222138, 2.222144",\ + "0.122237, 0.122292, 0.122954, 0.124971, 0.129018",\ + "0.151797, 0.151883, 0.152451, 0.154040, 0.157229",\ + "0.201011, 0.201013, 0.201174, 0.201712, 0.202792",\ + "0.823650, 0.823653, 0.823665, 0.823694, 0.823752",\ + "2.222134, 2.222134, 2.222135, 2.222138, 2.222144",\ + "0.122238, 0.122294, 0.122955, 0.124971, 0.129018",\ + "0.151797, 0.151885, 0.152452, 0.154040, 0.157229",\ + "0.201011, 0.201013, 0.201174, 0.201712, 0.202792",\ + "0.823650, 0.823653, 0.823665, 0.823694, 0.823752",\ + "2.222134, 2.222134, 2.222135, 2.222138, 2.222144",\ + "0.122241, 0.122311, 0.122975, 0.124980, 0.129018",\ + "0.151805, 0.151911, 0.152468, 0.154047, 0.157229",\ + "0.201012, 0.201014, 0.201180, 0.201714, 0.202792",\ + "0.823651, 0.823654, 0.823666, 0.823694, 0.823752",\ + "2.222134, 2.222134, 2.222135, 2.222138, 2.222144"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011"); + values ( "0.504118, 0.754852, 1.032751, 1.495998, 2.422494",\ + "0.516114, 0.766894, 1.044988, 1.508707, 2.436146",\ + "0.535711, 0.786551, 1.064911, 1.529268, 2.457982",\ + "0.706984, 0.958018, 1.237222, 1.703603, 2.636367",\ + "1.041617, 1.292639, 1.571788, 2.038038, 2.970540",\ + "0.591527, 0.842425, 1.120299, 1.582713, 2.508428",\ + "0.603524, 0.854467, 1.132538, 1.595422, 2.522079",\ + "0.623120, 0.874125, 1.152463, 1.615983, 2.543916",\ + "0.794393, 1.045593, 1.324780, 1.790318, 2.722301",\ + "1.129027, 1.380214, 1.659346, 2.124753, 3.056474",\ + "0.672359, 0.931452, 1.208262, 1.670335, 2.595383",\ + "0.684355, 0.943495, 1.220501, 1.683044, 2.609035",\ + "0.703952, 0.963154, 1.240426, 1.703604, 2.630871",\ + "0.875225, 1.134627, 1.412743, 1.877940, 2.809256",\ + "1.209858, 1.469247, 1.747309, 2.212375, 3.143429",\ + "0.729973, 0.997154, 1.272401, 1.734248, 2.658892",\ + "0.741969, 1.009198, 1.284640, 1.746957, 2.672544",\ + "0.761566, 1.028859, 1.304565, 1.767518, 2.694380",\ + "0.932840, 1.200337, 1.476882, 1.941853, 2.872765",\ + "1.267473, 1.534957, 1.811448, 2.276288, 3.206938",\ + "1.059672, 1.362345, 1.624210, 2.083570, 3.004348",\ + "1.071671, 1.374403, 1.636453, 2.096281, 3.018000",\ + "1.091271, 1.394084, 1.656385, 2.116844, 3.039836",\ + "1.262555, 1.565626, 1.828723, 2.291188, 3.218221",\ + "1.597188, 1.900242, 2.163287, 2.625622, 3.552394"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011"); + values ( "0.074860, 0.075317, 0.077304, 0.082076, 0.091621",\ + "0.080333, 0.080747, 0.082548, 0.086873, 0.095522",\ + "0.100376, 0.100764, 0.102449, 0.106497, 0.114592",\ + "0.380687, 0.380688, 0.380696, 0.380717, 0.380759",\ + "1.025901, 1.025907, 1.025944, 1.026050, 1.026262",\ + "0.074860, 0.075320, 0.077319, 0.082076, 0.091621",\ + "0.080333, 0.080751, 0.082562, 0.086873, 0.095522",\ + "0.100376, 0.100767, 0.102462, 0.106497, 0.114592",\ + "0.380687, 0.380688, 0.380696, 0.380717, 0.380759",\ + "1.025901, 1.025907, 1.025945, 1.026050, 1.026262",\ + "0.074860, 0.075329, 0.077319, 0.082076, 0.091621",\ + "0.080334, 0.080759, 0.082562, 0.086873, 0.095522",\ + "0.100376, 0.100774, 0.102462, 0.106497, 0.114592",\ + "0.380687, 0.380688, 0.380696, 0.380717, 0.380759",\ + "1.025901, 1.025907, 1.025945, 1.026050, 1.026262",\ + "0.074860, 0.075342, 0.077320, 0.082076, 0.091621",\ + "0.080334, 0.080770, 0.082563, 0.086873, 0.095522",\ + "0.100377, 0.100785, 0.102463, 0.106497, 0.114592",\ + "0.380687, 0.380688, 0.380696, 0.380717, 0.380759",\ + "1.025901, 1.025907, 1.025945, 1.026050, 1.026262",\ + "0.074886, 0.075492, 0.077368, 0.082096, 0.091621",\ + "0.080357, 0.080906, 0.082607, 0.086890, 0.095522",\ + "0.100399, 0.100912, 0.102504, 0.106513, 0.114592",\ + "0.380687, 0.380689, 0.380696, 0.380717, 0.380759",\ + "1.025902, 1.025909, 1.025946, 1.026050, 1.026262"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_2519*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[27]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011"); + values ( "0.601589, 0.856514, 1.112604, 1.552662, 2.432779",\ + "0.615142, 0.870066, 1.126156, 1.566215, 2.446333",\ + "0.638672, 0.893596, 1.149686, 1.589744, 2.469861",\ + "0.906045, 1.160969, 1.417061, 1.857126, 2.737255",\ + "1.499860, 1.754785, 2.010744, 2.450359, 3.329590",\ + "0.689139, 0.944005, 1.200076, 1.639375, 2.518713",\ + "0.702691, 0.957558, 1.213628, 1.652928, 2.532267",\ + "0.726222, 0.981088, 1.237158, 1.676457, 2.555795",\ + "0.993595, 1.248461, 1.504533, 1.943839, 2.823189",\ + "1.587410, 1.842276, 2.098214, 2.537072, 3.415524",\ + "0.778517, 1.032815, 1.288036, 1.726995, 2.605668",\ + "0.792069, 1.046367, 1.301588, 1.740548, 2.619222",\ + "0.815599, 1.069897, 1.325118, 1.764078, 2.642750",\ + "1.082972, 1.337270, 1.592493, 2.031459, 2.910144",\ + "1.676788, 1.931085, 2.186174, 2.624692, 3.502479",\ + "0.842460, 1.098198, 1.352170, 1.790908, 2.669177",\ + "0.856012, 1.111750, 1.365723, 1.804461, 2.682731",\ + "0.879542, 1.135280, 1.389253, 1.827990, 2.706259",\ + "1.146915, 1.402653, 1.656628, 2.095372, 2.973653",\ + "1.740730, 1.996469, 2.250309, 2.688605, 3.565988",\ + "1.180709, 1.459770, 1.703739, 2.140127, 3.014633",\ + "1.194261, 1.473322, 1.717291, 2.153680, 3.028187",\ + "1.217791, 1.496852, 1.740821, 2.177209, 3.051715",\ + "1.485164, 1.764225, 2.008196, 2.444591, 3.319109",\ + "2.078980, 2.358040, 2.601873, 3.037822, 3.911444"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011"); + values ( "0.121333, 0.121333, 0.121337, 0.121351, 0.121379",\ + "0.151701, 0.151701, 0.151700, 0.151698, 0.151693",\ + "0.201129, 0.201129, 0.201130, 0.201137, 0.201149",\ + "0.823409, 0.823409, 0.823407, 0.823401, 0.823387",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121333, 0.121333, 0.121337, 0.121351, 0.121379",\ + "0.151701, 0.151701, 0.151700, 0.151698, 0.151693",\ + "0.201129, 0.201129, 0.201130, 0.201137, 0.201149",\ + "0.823409, 0.823409, 0.823407, 0.823401, 0.823387",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121333, 0.121333, 0.121337, 0.121351, 0.121379",\ + "0.151701, 0.151701, 0.151700, 0.151698, 0.151693",\ + "0.201129, 0.201129, 0.201130, 0.201137, 0.201149",\ + "0.823409, 0.823409, 0.823407, 0.823401, 0.823387",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121333, 0.121333, 0.121337, 0.121351, 0.121379",\ + "0.151701, 0.151701, 0.151700, 0.151698, 0.151693",\ + "0.201129, 0.201129, 0.201130, 0.201137, 0.201149",\ + "0.823409, 0.823409, 0.823407, 0.823401, 0.823387",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121333, 0.121333, 0.121337, 0.121351, 0.121379",\ + "0.151701, 0.151701, 0.151700, 0.151698, 0.151693",\ + "0.201129, 0.201129, 0.201131, 0.201137, 0.201149",\ + "0.823409, 0.823409, 0.823407, 0.823401, 0.823387",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011"); + values ( "0.569211, 0.824136, 1.079695, 1.517959, 2.394488",\ + "0.577154, 0.832078, 1.087637, 1.525902, 2.402431",\ + "0.590634, 0.845558, 1.101117, 1.539382, 2.415911",\ + "0.744587, 0.999511, 1.255305, 1.694361, 2.572475",\ + "1.084486, 1.339411, 1.594970, 2.033235, 2.909765",\ + "0.656761, 0.911627, 1.167161, 1.604672, 2.480422",\ + "0.664704, 0.919570, 1.175103, 1.612615, 2.488365",\ + "0.678184, 0.933050, 1.188583, 1.626095, 2.501845",\ + "0.832137, 1.087003, 1.342773, 1.781074, 2.658409",\ + "1.172036, 1.426902, 1.682436, 2.119948, 2.995698",\ + "0.746139, 1.000437, 1.255121, 1.692293, 2.567377",\ + "0.754081, 1.008379, 1.263063, 1.700235, 2.575320",\ + "0.767561, 1.021859, 1.276543, 1.713715, 2.588800",\ + "0.921514, 1.175812, 1.430733, 1.868695, 2.745364",\ + "1.261414, 1.515711, 1.770396, 2.207568, 3.082654",\ + "0.810081, 1.065820, 1.319255, 1.756205, 2.630886",\ + "0.818024, 1.073762, 1.327198, 1.764148, 2.638829",\ + "0.831504, 1.087242, 1.340678, 1.777627, 2.652309",\ + "0.985457, 1.241195, 1.494868, 1.932607, 2.808873",\ + "1.325356, 1.581095, 1.834530, 2.271481, 3.146163",\ + "1.148331, 1.427392, 1.670806, 2.105417, 2.976342",\ + "1.156273, 1.435334, 1.678748, 2.113359, 2.984285",\ + "1.169753, 1.448814, 1.692228, 2.126839, 2.997765",\ + "1.323706, 1.602767, 1.846426, 2.281822, 3.154329",\ + "1.663605, 1.942666, 2.186081, 2.620692, 3.491619"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011"); + values ( "0.061223, 0.061223, 0.061191, 0.061085, 0.060871",\ + "0.068571, 0.068571, 0.068550, 0.068476, 0.068328",\ + "0.090396, 0.090396, 0.090388, 0.090358, 0.090299",\ + "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\ + "1.025895, 1.025895, 1.025895, 1.025895, 1.025894",\ + "0.061223, 0.061223, 0.061191, 0.061085, 0.060871",\ + "0.068571, 0.068571, 0.068549, 0.068476, 0.068328",\ + "0.090396, 0.090396, 0.090387, 0.090358, 0.090299",\ + "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\ + "1.025895, 1.025895, 1.025895, 1.025895, 1.025894",\ + "0.061223, 0.061223, 0.061191, 0.061085, 0.060871",\ + "0.068571, 0.068571, 0.068549, 0.068476, 0.068328",\ + "0.090396, 0.090396, 0.090387, 0.090358, 0.090299",\ + "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\ + "1.025895, 1.025895, 1.025895, 1.025895, 1.025894",\ + "0.061223, 0.061223, 0.061191, 0.061085, 0.060871",\ + "0.068571, 0.068571, 0.068549, 0.068476, 0.068328",\ + "0.090396, 0.090396, 0.090387, 0.090358, 0.090299",\ + "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\ + "1.025895, 1.025895, 1.025895, 1.025895, 1.025894",\ + "0.061223, 0.061223, 0.061190, 0.061084, 0.060871",\ + "0.068571, 0.068571, 0.068549, 0.068475, 0.068328",\ + "0.090396, 0.090396, 0.090387, 0.090358, 0.090299",\ + "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\ + "1.025895, 1.025895, 1.025895, 1.025895, 1.025894"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_2575*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[30]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.577162, 0.819115, 1.086143, 1.569512, 2.536249",\ + "0.590714, 0.832667, 1.099696, 1.583067, 2.549807",\ + "0.614244, 0.856197, 1.123226, 1.606594, 2.573331",\ + "0.881617, 1.123572, 1.390607, 1.873991, 2.840761",\ + "1.475569, 1.717569, 1.984519, 2.467402, 3.433167",\ + "0.664563, 0.906592, 1.173751, 1.656225, 2.622182",\ + "0.678115, 0.920144, 1.187304, 1.669780, 2.635741",\ + "0.701645, 0.943674, 1.210834, 1.693307, 2.659265",\ + "0.969019, 1.211049, 1.478215, 1.960705, 2.926694",\ + "1.562970, 1.805047, 2.072125, 2.554115, 3.519101",\ + "0.745370, 0.995374, 1.261714, 1.743845, 2.709137",\ + "0.758922, 1.008926, 1.275267, 1.757400, 2.722696",\ + "0.782452, 1.032456, 1.298797, 1.780928, 2.746220",\ + "1.049826, 1.299831, 1.566178, 2.048325, 3.013649",\ + "1.643777, 1.893830, 2.160089, 2.641735, 3.606056",\ + "0.805541, 1.060718, 1.325856, 1.807758, 2.772646",\ + "0.819093, 1.074270, 1.339409, 1.821313, 2.786205",\ + "0.842623, 1.097800, 1.362939, 1.844840, 2.809729",\ + "1.109996, 1.365175, 1.630320, 2.112238, 3.077158",\ + "1.703948, 1.959175, 2.224230, 2.705648, 3.669565",\ + "1.143425, 1.421812, 1.677865, 2.157156, 3.118103",\ + "1.156977, 1.435364, 1.691418, 2.170711, 3.131661",\ + "1.180507, 1.458894, 1.714947, 2.194238, 3.155185",\ + "1.447880, 1.726269, 1.982328, 2.461636, 3.422615",\ + "2.041832, 2.320285, 2.576234, 3.055044, 4.015021"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.121333, 0.121336, 0.121350, 0.121386, 0.121458",\ + "0.151694, 0.151694, 0.151695, 0.151695, 0.151695",\ + "0.201129, 0.201130, 0.201136, 0.201152, 0.201184",\ + "0.823409, 0.823409, 0.823409, 0.823409, 0.823409",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121333, 0.121336, 0.121350, 0.121386, 0.121458",\ + "0.151694, 0.151694, 0.151695, 0.151695, 0.151695",\ + "0.201129, 0.201130, 0.201136, 0.201152, 0.201184",\ + "0.823409, 0.823409, 0.823409, 0.823409, 0.823409",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121333, 0.121336, 0.121350, 0.121386, 0.121458",\ + "0.151694, 0.151694, 0.151695, 0.151695, 0.151695",\ + "0.201129, 0.201130, 0.201136, 0.201152, 0.201184",\ + "0.823409, 0.823409, 0.823409, 0.823409, 0.823409",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121333, 0.121336, 0.121350, 0.121386, 0.121458",\ + "0.151694, 0.151694, 0.151695, 0.151695, 0.151695",\ + "0.201129, 0.201130, 0.201136, 0.201152, 0.201184",\ + "0.823409, 0.823409, 0.823409, 0.823409, 0.823409",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121333, 0.121337, 0.121351, 0.121386, 0.121458",\ + "0.151694, 0.151694, 0.151695, 0.151695, 0.151695",\ + "0.201129, 0.201130, 0.201137, 0.201152, 0.201184",\ + "0.823409, 0.823409, 0.823409, 0.823409, 0.823409",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.544918, 0.786919, 1.051943, 1.528303, 2.481022",\ + "0.552861, 0.794861, 1.060131, 1.537319, 2.491697",\ + "0.566341, 0.808341, 1.074013, 1.552566, 2.509672",\ + "0.720294, 0.962295, 1.229085, 1.711427, 2.676111",\ + "1.060194, 1.302195, 1.568545, 2.049397, 3.011100",\ + "0.632320, 0.874396, 1.139529, 1.615016, 2.566956",\ + "0.640262, 0.882339, 1.147719, 1.624032, 2.577631",\ + "0.653742, 0.895819, 1.161606, 1.639279, 2.595606",\ + "0.807696, 1.049772, 1.316690, 1.798140, 2.762045",\ + "1.147596, 1.389672, 1.656145, 2.136110, 3.097034",\ + "0.713127, 0.963179, 1.227492, 1.702637, 2.653911",\ + "0.721069, 0.971121, 1.235682, 1.711653, 2.664586",\ + "0.734549, 0.984601, 1.249569, 1.726900, 2.682561",\ + "0.888502, 1.138555, 1.404653, 1.885761, 2.849000",\ + "1.228403, 1.478455, 1.744108, 2.223730, 3.183989",\ + "0.773297, 1.028524, 1.291633, 1.766549, 2.717420",\ + "0.781240, 1.036467, 1.299823, 1.775565, 2.728095",\ + "0.794720, 1.049947, 1.313710, 1.790812, 2.746070",\ + "0.948673, 1.203900, 1.468795, 1.949673, 2.912509",\ + "1.288574, 1.543800, 1.808250, 2.287643, 3.247498",\ + "1.111181, 1.389635, 1.643570, 2.115918, 3.062876",\ + "1.119124, 1.397577, 1.651768, 2.124938, 3.073550",\ + "1.132604, 1.411057, 1.665669, 2.140191, 3.091526",\ + "1.286557, 1.565011, 1.820792, 2.299067, 3.257965",\ + "1.626457, 1.904911, 2.160232, 2.637031, 3.592954"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.061220, 0.061199, 0.061091, 0.060821, 0.060280",\ + "0.068569, 0.068555, 0.068480, 0.068293, 0.067919",\ + "0.090395, 0.090390, 0.090360, 0.090285, 0.090136",\ + "0.380686, 0.380686, 0.380686, 0.380685, 0.380684",\ + "1.025895, 1.025895, 1.025894, 1.025891, 1.025886",\ + "0.061220, 0.061199, 0.061090, 0.060821, 0.060280",\ + "0.068569, 0.068555, 0.068480, 0.068293, 0.067919",\ + "0.090395, 0.090390, 0.090360, 0.090285, 0.090136",\ + "0.380686, 0.380686, 0.380686, 0.380685, 0.380684",\ + "1.025895, 1.025895, 1.025894, 1.025891, 1.025886",\ + "0.061220, 0.061198, 0.061090, 0.060821, 0.060280",\ + "0.068569, 0.068554, 0.068480, 0.068293, 0.067919",\ + "0.090395, 0.090390, 0.090360, 0.090285, 0.090136",\ + "0.380686, 0.380686, 0.380686, 0.380685, 0.380684",\ + "1.025895, 1.025895, 1.025894, 1.025891, 1.025886",\ + "0.061220, 0.061198, 0.061090, 0.060821, 0.060280",\ + "0.068569, 0.068554, 0.068479, 0.068293, 0.067919",\ + "0.090395, 0.090389, 0.090360, 0.090285, 0.090136",\ + "0.380686, 0.380686, 0.380686, 0.380685, 0.380684",\ + "1.025895, 1.025895, 1.025894, 1.025891, 1.025886",\ + "0.061220, 0.061191, 0.061087, 0.060819, 0.060280",\ + "0.068569, 0.068549, 0.068478, 0.068292, 0.067919",\ + "0.090395, 0.090387, 0.090359, 0.090285, 0.090136",\ + "0.380686, 0.380686, 0.380686, 0.380685, 0.380684",\ + "1.025895, 1.025895, 1.025894, 1.025891, 1.025886"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_2704*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[32]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.666137, 0.908208, 1.174611, 1.656033, 2.618876",\ + "0.679731, 0.921802, 1.188205, 1.669626, 2.632469",\ + "0.703271, 0.945343, 1.211745, 1.693166, 2.656009",\ + "0.970809, 1.212879, 1.479281, 1.960701, 2.923540",\ + "1.563272, 1.805343, 2.071744, 2.553161, 3.515995",\ + "0.753539, 0.995685, 1.262213, 1.742746, 2.704810",\ + "0.767133, 1.009279, 1.275807, 1.756339, 2.718403",\ + "0.790673, 1.032819, 1.299347, 1.779880, 2.741943",\ + "1.058210, 1.300356, 1.566883, 2.047414, 3.009474",\ + "1.650674, 1.892820, 2.159346, 2.639874, 3.601928",\ + "0.834346, 1.084466, 1.350176, 1.830367, 2.791765",\ + "0.847940, 1.098060, 1.363770, 1.843960, 2.805358",\ + "0.871480, 1.121600, 1.387310, 1.867500, 2.828898",\ + "1.139017, 1.389137, 1.654846, 2.135035, 3.096429",\ + "1.731481, 1.981601, 2.247309, 2.727494, 3.688883",\ + "0.894640, 1.149809, 1.414318, 1.894279, 2.855274",\ + "0.908234, 1.163403, 1.427911, 1.907872, 2.868867",\ + "0.931774, 1.186943, 1.451452, 1.931413, 2.892407",\ + "1.199311, 1.454480, 1.718988, 2.198947, 3.159938",\ + "1.791775, 2.046944, 2.311450, 2.791407, 3.752392",\ + "1.232542, 1.510890, 1.766306, 2.243669, 3.200730",\ + "1.246135, 1.524484, 1.779900, 2.257262, 3.214323",\ + "1.269676, 1.548024, 1.803440, 2.280803, 3.237863",\ + "1.537213, 1.815561, 2.070976, 2.548337, 3.505394",\ + "2.129677, 2.408025, 2.663439, 3.140797, 4.097848"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.121485, 0.121485, 0.121485, 0.121485, 0.121485",\ + "0.152032, 0.152032, 0.152043, 0.152082, 0.152158",\ + "0.200984, 0.200984, 0.200984, 0.200984, 0.200984",\ + "0.823612, 0.823612, 0.823612, 0.823612, 0.823612",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222135",\ + "0.121485, 0.121485, 0.121485, 0.121485, 0.121485",\ + "0.152032, 0.152032, 0.152044, 0.152082, 0.152158",\ + "0.200984, 0.200984, 0.200984, 0.200984, 0.200984",\ + "0.823612, 0.823612, 0.823612, 0.823612, 0.823612",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222135",\ + "0.121485, 0.121485, 0.121485, 0.121485, 0.121485",\ + "0.152032, 0.152032, 0.152044, 0.152082, 0.152158",\ + "0.200984, 0.200984, 0.200984, 0.200984, 0.200984",\ + "0.823612, 0.823612, 0.823612, 0.823612, 0.823612",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222135",\ + "0.121485, 0.121485, 0.121485, 0.121485, 0.121485",\ + "0.152032, 0.152032, 0.152044, 0.152082, 0.152158",\ + "0.200984, 0.200984, 0.200984, 0.200984, 0.200984",\ + "0.823612, 0.823612, 0.823612, 0.823612, 0.823612",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222135",\ + "0.121485, 0.121485, 0.121485, 0.121485, 0.121485",\ + "0.152032, 0.152032, 0.152044, 0.152082, 0.152158",\ + "0.200984, 0.200984, 0.200984, 0.200984, 0.200984",\ + "0.823612, 0.823612, 0.823612, 0.823612, 0.823612",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222135"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.607646, 0.849717, 1.116124, 1.597554, 2.560414",\ + "0.619007, 0.861079, 1.127484, 1.608912, 2.571767",\ + "0.637745, 0.879816, 1.146220, 1.627645, 2.590494",\ + "0.806293, 1.048363, 1.314763, 1.796177, 2.759006",\ + "1.141102, 1.383173, 1.649573, 2.130988, 3.093818",\ + "0.695047, 0.937194, 1.203726, 1.684267, 2.646348",\ + "0.706409, 0.948555, 1.215086, 1.695625, 2.657701",\ + "0.725146, 0.967293, 1.233822, 1.714358, 2.676428",\ + "0.893694, 1.135840, 1.402365, 1.882890, 2.844940",\ + "1.228504, 1.470650, 1.737175, 2.217701, 3.179752",\ + "0.775854, 1.025975, 1.291688, 1.771888, 2.733303",\ + "0.787216, 1.037337, 1.303049, 1.783245, 2.744656",\ + "0.805953, 1.056074, 1.321785, 1.801978, 2.763383",\ + "0.974501, 1.224621, 1.490328, 1.970511, 2.931895",\ + "1.309311, 1.559431, 1.825138, 2.305322, 3.266707",\ + "0.836149, 1.091318, 1.355830, 1.835800, 2.796812",\ + "0.847510, 1.102679, 1.367190, 1.847158, 2.808165",\ + "0.866248, 1.121417, 1.385927, 1.865891, 2.826892",\ + "1.034796, 1.289964, 1.554469, 2.034424, 2.995404",\ + "1.369605, 1.624774, 1.889280, 2.369234, 3.330216",\ + "1.174050, 1.452400, 1.707819, 2.185190, 3.142268",\ + "1.185411, 1.463761, 1.719179, 2.196548, 3.153621",\ + "1.204149, 1.482498, 1.737915, 2.215281, 3.172348",\ + "1.372697, 1.651045, 1.906458, 2.383814, 3.340860",\ + "1.707507, 1.985855, 2.241268, 2.718624, 3.675672"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.068435, 0.068435, 0.068435, 0.068435, 0.068435",\ + "0.074512, 0.074512, 0.074512, 0.074512, 0.074512",\ + "0.094928, 0.094928, 0.094928, 0.094928, 0.094928",\ + "0.380690, 0.380690, 0.380690, 0.380691, 0.380692",\ + "1.025917, 1.025917, 1.025918, 1.025920, 1.025925",\ + "0.068435, 0.068435, 0.068435, 0.068435, 0.068435",\ + "0.074512, 0.074512, 0.074512, 0.074512, 0.074512",\ + "0.094928, 0.094928, 0.094928, 0.094928, 0.094928",\ + "0.380690, 0.380690, 0.380690, 0.380691, 0.380692",\ + "1.025917, 1.025917, 1.025918, 1.025920, 1.025925",\ + "0.068435, 0.068435, 0.068435, 0.068435, 0.068435",\ + "0.074512, 0.074512, 0.074512, 0.074512, 0.074512",\ + "0.094928, 0.094928, 0.094928, 0.094928, 0.094928",\ + "0.380690, 0.380690, 0.380690, 0.380691, 0.380692",\ + "1.025917, 1.025917, 1.025918, 1.025920, 1.025925",\ + "0.068435, 0.068435, 0.068435, 0.068435, 0.068435",\ + "0.074512, 0.074512, 0.074512, 0.074512, 0.074512",\ + "0.094928, 0.094928, 0.094928, 0.094928, 0.094928",\ + "0.380690, 0.380690, 0.380690, 0.380691, 0.380692",\ + "1.025917, 1.025917, 1.025918, 1.025920, 1.025925",\ + "0.068435, 0.068435, 0.068435, 0.068435, 0.068435",\ + "0.074512, 0.074512, 0.074512, 0.074512, 0.074512",\ + "0.094928, 0.094928, 0.094928, 0.094928, 0.094928",\ + "0.380690, 0.380690, 0.380690, 0.380691, 0.380692",\ + "1.025917, 1.025917, 1.025918, 1.025920, 1.025925"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_2327*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[33]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.688394, 0.943298, 1.199532, 1.637805, 2.514353",\ + "0.701988, 0.956891, 1.213125, 1.651399, 2.527946",\ + "0.725528, 0.980432, 1.236665, 1.674939, 2.551486",\ + "0.993065, 1.247969, 1.504202, 1.942475, 2.819022",\ + "1.585529, 1.840433, 2.096666, 2.534938, 3.411482",\ + "0.775799, 1.030785, 1.286999, 1.724519, 2.600287",\ + "0.789393, 1.044379, 1.300593, 1.738113, 2.613880",\ + "0.812933, 1.067919, 1.324133, 1.761653, 2.637420",\ + "1.080470, 1.335456, 1.591670, 2.029189, 2.904955",\ + "1.672934, 1.927920, 2.184134, 2.621652, 3.497416",\ + "0.864143, 1.119604, 1.374960, 1.812140, 2.687242",\ + "0.877736, 1.133197, 1.388554, 1.825734, 2.700835",\ + "0.901277, 1.156737, 1.412094, 1.849274, 2.724375",\ + "1.168814, 1.424274, 1.679631, 2.116810, 2.991910",\ + "1.761278, 2.016739, 2.272095, 2.709273, 3.584371",\ + "0.927637, 1.185001, 1.439095, 1.876053, 2.750751",\ + "0.941231, 1.198595, 1.452689, 1.889647, 2.764344",\ + "0.964771, 1.222135, 1.476229, 1.913187, 2.787884",\ + "1.232308, 1.489672, 1.743766, 2.180723, 3.055419",\ + "1.824772, 2.082136, 2.336229, 2.773186, 3.647880",\ + "1.263060, 1.546678, 1.790648, 2.225268, 3.096207",\ + "1.276654, 1.560272, 1.804242, 2.238862, 3.109800",\ + "1.300194, 1.583812, 1.827782, 2.262402, 3.133340",\ + "1.567731, 1.851349, 2.095319, 2.529938, 3.400876",\ + "2.160195, 2.443813, 2.687783, 3.122401, 3.993336"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.121485, 0.121485, 0.121485, 0.121484, 0.121482",\ + "0.152032, 0.152032, 0.152031, 0.152028, 0.152021",\ + "0.200984, 0.200984, 0.200984, 0.200984, 0.200984",\ + "0.823612, 0.823612, 0.823612, 0.823612, 0.823612",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121485, 0.121485, 0.121485, 0.121484, 0.121482",\ + "0.152032, 0.152032, 0.152031, 0.152028, 0.152021",\ + "0.200984, 0.200984, 0.200984, 0.200984, 0.200984",\ + "0.823612, 0.823612, 0.823612, 0.823612, 0.823612",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121485, 0.121485, 0.121485, 0.121484, 0.121482",\ + "0.152032, 0.152032, 0.152031, 0.152028, 0.152021",\ + "0.200984, 0.200984, 0.200984, 0.200984, 0.200984",\ + "0.823612, 0.823612, 0.823612, 0.823612, 0.823612",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121485, 0.121485, 0.121485, 0.121484, 0.121482",\ + "0.152032, 0.152032, 0.152031, 0.152028, 0.152021",\ + "0.200984, 0.200984, 0.200984, 0.200984, 0.200984",\ + "0.823612, 0.823612, 0.823612, 0.823612, 0.823612",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121485, 0.121485, 0.121485, 0.121484, 0.121482",\ + "0.152032, 0.152032, 0.152031, 0.152028, 0.152021",\ + "0.200984, 0.200984, 0.200984, 0.200984, 0.200984",\ + "0.823612, 0.823612, 0.823612, 0.823612, 0.823612",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.629902, 0.884806, 1.141041, 1.579317, 2.455871",\ + "0.641263, 0.896167, 1.152402, 1.590678, 2.467230",\ + "0.660001, 0.914905, 1.171139, 1.609414, 2.485964",\ + "0.828549, 1.083453, 1.339686, 1.777957, 2.654500",\ + "1.163359, 1.418263, 1.674496, 2.112767, 2.989310",\ + "0.717307, 0.972293, 1.228508, 1.666031, 2.541805",\ + "0.728669, 0.983655, 1.239870, 1.677392, 2.553164",\ + "0.747406, 1.002393, 1.258607, 1.696128, 2.571898",\ + "0.915954, 1.170941, 1.427154, 1.864671, 2.740433",\ + "1.250764, 1.505750, 1.761964, 2.199481, 3.075244",\ + "0.805651, 1.061112, 1.316469, 1.753652, 2.628760",\ + "0.817012, 1.072473, 1.327831, 1.765013, 2.640119",\ + "0.835750, 1.091211, 1.346568, 1.783749, 2.658853",\ + "1.004298, 1.259759, 1.515115, 1.952292, 2.827389",\ + "1.339108, 1.594568, 1.849925, 2.287102, 3.162199",\ + "0.869145, 1.126509, 1.380604, 1.817565, 2.692269",\ + "0.880507, 1.137871, 1.391965, 1.828925, 2.703628",\ + "0.899244, 1.156608, 1.410703, 1.847662, 2.722362",\ + "1.067792, 1.325156, 1.579249, 2.016205, 2.890898",\ + "1.402602, 1.659966, 1.914059, 2.351015, 3.225708",\ + "1.204568, 1.488186, 1.732157, 2.166780, 3.037725",\ + "1.215930, 1.499547, 1.743518, 2.178141, 3.049084",\ + "1.234668, 1.518285, 1.762256, 2.196877, 3.067818",\ + "1.403215, 1.686833, 1.930802, 2.365420, 3.236354",\ + "1.738025, 2.021643, 2.265612, 2.700230, 3.571164"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.068436, 0.068436, 0.068433, 0.068425, 0.068407",\ + "0.074512, 0.074512, 0.074510, 0.074502, 0.074487",\ + "0.094928, 0.094928, 0.094926, 0.094919, 0.094904",\ + "0.380690, 0.380690, 0.380690, 0.380690, 0.380690",\ + "1.025917, 1.025917, 1.025917, 1.025917, 1.025916",\ + "0.068436, 0.068436, 0.068433, 0.068425, 0.068407",\ + "0.074512, 0.074512, 0.074510, 0.074502, 0.074487",\ + "0.094928, 0.094928, 0.094926, 0.094919, 0.094904",\ + "0.380690, 0.380690, 0.380690, 0.380690, 0.380690",\ + "1.025917, 1.025917, 1.025917, 1.025917, 1.025916",\ + "0.068436, 0.068436, 0.068433, 0.068425, 0.068407",\ + "0.074512, 0.074512, 0.074510, 0.074502, 0.074487",\ + "0.094928, 0.094928, 0.094926, 0.094919, 0.094904",\ + "0.380690, 0.380690, 0.380690, 0.380690, 0.380690",\ + "1.025917, 1.025917, 1.025917, 1.025917, 1.025916",\ + "0.068436, 0.068436, 0.068433, 0.068425, 0.068407",\ + "0.074512, 0.074512, 0.074510, 0.074502, 0.074487",\ + "0.094928, 0.094928, 0.094926, 0.094919, 0.094904",\ + "0.380690, 0.380690, 0.380690, 0.380690, 0.380690",\ + "1.025917, 1.025917, 1.025917, 1.025917, 1.025916",\ + "0.068436, 0.068436, 0.068433, 0.068425, 0.068407",\ + "0.074512, 0.074512, 0.074510, 0.074502, 0.074487",\ + "0.094928, 0.094928, 0.094926, 0.094919, 0.094904",\ + "0.380690, 0.380690, 0.380690, 0.380690, 0.380690",\ + "1.025917, 1.025917, 1.025917, 1.025917, 1.025916"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_2344*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[37]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.195231, 0.463005, 0.734474, 1.195010, 2.116083",\ + "0.209369, 0.477311, 0.748785, 1.209873, 2.132048",\ + "0.233103, 0.501280, 0.772498, 1.233725, 2.156177",\ + "0.505445, 0.772942, 1.041862, 1.499718, 2.415430",\ + "1.101330, 1.368410, 1.636340, 2.092443, 3.004649",\ + "0.282639, 0.550544, 0.822013, 1.281725, 2.202017",\ + "0.296777, 0.564849, 0.836326, 1.296587, 2.217982",\ + "0.320749, 0.588817, 0.860040, 1.320439, 2.242111",\ + "0.593808, 0.860470, 1.129393, 1.586432, 2.501364",\ + "1.189691, 1.455935, 1.723865, 2.179157, 3.090583",\ + "0.371453, 0.639490, 0.909976, 1.369346, 2.288972",\ + "0.385884, 0.653793, 0.924289, 1.384209, 2.304937",\ + "0.410095, 0.677755, 0.948003, 1.408060, 2.329066",\ + "0.683117, 0.949390, 1.217355, 1.674054, 2.588319",\ + "1.278993, 1.544848, 1.811828, 2.266779, 3.177538",\ + "0.435127, 0.705073, 0.974115, 1.433259, 2.352481",\ + "0.449557, 0.719372, 0.988428, 1.448122, 2.368446",\ + "0.473764, 0.743329, 1.012141, 1.471974, 2.392575",\ + "0.746751, 1.014935, 1.281493, 1.737967, 2.651828",\ + "1.342621, 1.610383, 1.875965, 2.330692, 3.241047",\ + "0.771711, 1.068883, 1.325895, 1.782569, 2.697937",\ + "0.786132, 1.083144, 1.340213, 1.797434, 2.713902",\ + "0.810321, 1.107028, 1.363928, 1.821286, 2.738031",\ + "1.083085, 1.378307, 1.633246, 2.087266, 2.997284",\ + "1.678917, 1.973635, 2.227701, 2.679984, 3.586503"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.185659, 0.236480, 0.332306, 0.503768, 0.846690",\ + "0.203762, 0.251201, 0.346416, 0.519962, 0.867054",\ + "0.237818, 0.275998, 0.366817, 0.542132, 0.892761",\ + "0.823305, 0.824108, 0.854501, 0.958291, 1.165871",\ + "2.222180, 2.222247, 2.228687, 2.250859, 2.295203",\ + "0.185659, 0.236778, 0.332846, 0.503768, 0.846690",\ + "0.203762, 0.251491, 0.346963, 0.519962, 0.867054",\ + "0.238090, 0.276257, 0.367369, 0.542132, 0.892761",\ + "0.823322, 0.824110, 0.854828, 0.958291, 1.165871",\ + "2.222181, 2.222247, 2.228756, 2.250859, 2.295203",\ + "0.187582, 0.237448, 0.332856, 0.503768, 0.846690",\ + "0.205428, 0.252143, 0.346973, 0.519962, 0.867054",\ + "0.238891, 0.276838, 0.367379, 0.542132, 0.892761",\ + "0.823369, 0.824113, 0.854835, 0.958291, 1.165871",\ + "2.222186, 2.222247, 2.228758, 2.250859, 2.295203",\ + "0.188921, 0.238422, 0.332885, 0.503768, 0.846690",\ + "0.206588, 0.253091, 0.347002, 0.519962, 0.867054",\ + "0.239638, 0.277682, 0.367409, 0.542132, 0.892761",\ + "0.823414, 0.824119, 0.854852, 0.958291, 1.165871",\ + "2.222191, 2.222247, 2.228761, 2.250859, 2.295203",\ + "0.197449, 0.249827, 0.334624, 0.504477, 0.846690",\ + "0.213977, 0.264195, 0.348763, 0.520680, 0.867054",\ + "0.244398, 0.287568, 0.369187, 0.542857, 0.892761",\ + "0.823697, 0.824180, 0.855905, 0.958721, 1.165871",\ + "2.222221, 2.222247, 2.228986, 2.250950, 2.295203"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.199835, 0.394068, 0.663502, 1.119151, 2.030450",\ + "0.208748, 0.404375, 0.677456, 1.139816, 2.064535",\ + "0.223610, 0.421071, 0.699454, 1.171923, 2.116862",\ + "0.380613, 0.582386, 0.880612, 1.405667, 2.455778",\ + "0.716679, 0.922290, 1.228480, 1.784735, 2.897244",\ + "0.287243, 0.481603, 0.751025, 1.205865, 2.116384",\ + "0.296156, 0.491921, 0.765001, 1.226530, 2.150469",\ + "0.311018, 0.508632, 0.787030, 1.258637, 2.202796",\ + "0.468021, 0.669977, 0.968355, 1.492382, 2.541712",\ + "0.804087, 1.009874, 1.316321, 1.871449, 2.983178",\ + "0.368115, 0.570540, 0.838988, 1.293487, 2.203339",\ + "0.377029, 0.580882, 0.852964, 1.314152, 2.237424",\ + "0.391890, 0.597628, 0.874994, 1.346259, 2.289751",\ + "0.548893, 0.759039, 1.056321, 1.580003, 2.628667",\ + "0.884959, 1.098920, 1.404289, 1.959070, 3.070133",\ + "0.425818, 0.636109, 0.903125, 1.357400, 2.266848",\ + "0.434733, 0.646488, 0.917102, 1.378065, 2.300933",\ + "0.449593, 0.663284, 0.939134, 1.410172, 2.353260",\ + "0.606596, 0.824792, 1.120470, 1.643916, 2.692176",\ + "0.942662, 1.164649, 1.468444, 2.022984, 3.133642",\ + "0.728861, 0.999767, 1.254856, 1.706689, 2.612304",\ + "0.737784, 1.010567, 1.268901, 1.727382, 2.646389",\ + "0.752638, 1.027949, 1.291036, 1.759531, 2.698716",\ + "0.909639, 1.190589, 1.472905, 1.993493, 3.037632",\ + "1.245701, 1.530174, 1.821195, 2.372689, 3.479098"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.051713, 0.082206, 0.146667, 0.272496, 0.524154",\ + "0.059242, 0.084148, 0.146833, 0.273232, 0.526032",\ + "0.082676, 0.098099, 0.151707, 0.276480, 0.526025",\ + "0.382075, 0.382564, 0.407345, 0.490228, 0.655996",\ + "1.027888, 1.027888, 1.042321, 1.092011, 1.191392",\ + "0.051713, 0.082387, 0.147063, 0.272496, 0.524154",\ + "0.059242, 0.084316, 0.147231, 0.273232, 0.526032",\ + "0.082676, 0.098212, 0.152100, 0.276480, 0.526025",\ + "0.382075, 0.382568, 0.407606, 0.490228, 0.655996",\ + "1.027888, 1.027888, 1.042477, 1.092011, 1.191392",\ + "0.051782, 0.082793, 0.147071, 0.272496, 0.524154",\ + "0.059284, 0.084694, 0.147238, 0.273232, 0.526032",\ + "0.082697, 0.098465, 0.152108, 0.276480, 0.526025",\ + "0.382075, 0.382579, 0.407611, 0.490228, 0.655996",\ + "1.027888, 1.027888, 1.042480, 1.092011, 1.191392",\ + "0.051916, 0.083384, 0.147092, 0.272496, 0.524154",\ + "0.059368, 0.085243, 0.147259, 0.273232, 0.526032",\ + "0.082738, 0.098832, 0.152128, 0.276480, 0.526025",\ + "0.382075, 0.382594, 0.407625, 0.490228, 0.655996",\ + "1.027888, 1.027888, 1.042489, 1.092011, 1.191392",\ + "0.053133, 0.090301, 0.148368, 0.273016, 0.524154",\ + "0.060124, 0.091679, 0.148542, 0.273755, 0.526032",\ + "0.083110, 0.103136, 0.153394, 0.276996, 0.526025",\ + "0.382075, 0.382769, 0.408465, 0.490571, 0.655996",\ + "1.027888, 1.027888, 1.042993, 1.092217, 1.191392"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_2530*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[40]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.737863, 1.003362, 1.291646, 1.782380, 2.763848",\ + "0.751415, 1.016914, 1.305198, 1.795933, 2.777400",\ + "0.774946, 1.040444, 1.328728, 1.819463, 2.800930",\ + "1.042319, 1.307818, 1.596103, 2.086838, 3.068308",\ + "1.636291, 1.901789, 2.190096, 2.680906, 3.662528",\ + "0.825276, 1.090943, 1.379283, 1.869095, 2.849782",\ + "0.838828, 1.104495, 1.392835, 1.882647, 2.863334",\ + "0.862358, 1.128025, 1.416365, 1.906177, 2.886864",\ + "1.129732, 1.395399, 1.683739, 2.173553, 3.154242",\ + "1.723704, 1.989370, 2.277732, 2.767621, 3.748461",\ + "0.906195, 1.180006, 1.467248, 1.956717, 2.936737",\ + "0.919747, 1.193558, 1.480801, 1.970270, 2.950289",\ + "0.943277, 1.217088, 1.504331, 1.993800, 2.973819",\ + "1.210651, 1.484462, 1.771705, 2.261175, 3.241197",\ + "1.804622, 2.078433, 2.365698, 2.855243, 3.835416",\ + "0.966681, 1.245760, 1.531392, 2.020631, 3.000246",\ + "0.980233, 1.259312, 1.544944, 2.034183, 3.013798",\ + "1.003763, 1.282842, 1.568474, 2.057713, 3.037328",\ + "1.271137, 1.550216, 1.835848, 2.325089, 3.304706",\ + "1.865109, 2.144188, 2.429842, 2.919157, 3.898925",\ + "1.301775, 1.611517, 1.883481, 2.370070, 3.345702",\ + "1.315328, 1.625069, 1.897033, 2.383622, 3.359254",\ + "1.338858, 1.648599, 1.920563, 2.407152, 3.382784",\ + "1.606231, 1.915973, 2.187937, 2.674527, 3.650162",\ + "2.200203, 2.509944, 2.781931, 3.268596, 4.244381"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.121334, 0.121334, 0.121335, 0.121338, 0.121343",\ + "0.151694, 0.151694, 0.151693, 0.151692, 0.151690",\ + "0.201129, 0.201129, 0.201129, 0.201131, 0.201133",\ + "0.823409, 0.823409, 0.823408, 0.823407, 0.823404",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121334, 0.121334, 0.121335, 0.121338, 0.121343",\ + "0.151694, 0.151694, 0.151693, 0.151692, 0.151690",\ + "0.201129, 0.201129, 0.201129, 0.201131, 0.201133",\ + "0.823409, 0.823409, 0.823408, 0.823407, 0.823404",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121334, 0.121334, 0.121335, 0.121338, 0.121343",\ + "0.151694, 0.151694, 0.151693, 0.151692, 0.151690",\ + "0.201129, 0.201129, 0.201129, 0.201131, 0.201133",\ + "0.823409, 0.823409, 0.823408, 0.823407, 0.823404",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121334, 0.121334, 0.121335, 0.121338, 0.121343",\ + "0.151694, 0.151694, 0.151693, 0.151692, 0.151690",\ + "0.201129, 0.201129, 0.201129, 0.201131, 0.201133",\ + "0.823409, 0.823409, 0.823408, 0.823407, 0.823404",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121334, 0.121334, 0.121335, 0.121338, 0.121343",\ + "0.151694, 0.151694, 0.151693, 0.151692, 0.151690",\ + "0.201129, 0.201129, 0.201129, 0.201131, 0.201133",\ + "0.823409, 0.823409, 0.823408, 0.823407, 0.823404",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.705640, 0.971139, 1.259445, 1.750256, 2.731876",\ + "0.713583, 0.979081, 1.267388, 1.758198, 2.739818",\ + "0.727063, 0.992561, 1.280868, 1.771678, 2.753298",\ + "0.881016, 1.146515, 1.434821, 1.925632, 2.907252",\ + "1.220917, 1.486415, 1.774721, 2.265532, 3.247153",\ + "0.793053, 1.058720, 1.347082, 1.836970, 2.817810",\ + "0.800995, 1.066662, 1.355024, 1.844913, 2.825752",\ + "0.814475, 1.080142, 1.368504, 1.858393, 2.839232",\ + "0.968429, 1.234096, 1.522458, 2.012346, 2.993186",\ + "1.308329, 1.573996, 1.862358, 2.352247, 3.333086",\ + "0.873972, 1.147783, 1.435048, 1.924593, 2.904765",\ + "0.881914, 1.155725, 1.442990, 1.932535, 2.912707",\ + "0.895394, 1.169205, 1.456470, 1.946015, 2.926187",\ + "1.049348, 1.323159, 1.610423, 2.099968, 3.080141",\ + "1.389248, 1.663059, 1.950324, 2.439869, 3.420042",\ + "0.934458, 1.213537, 1.499191, 1.988506, 2.968274",\ + "0.942401, 1.221480, 1.507133, 1.996449, 2.976216",\ + "0.955880, 1.234959, 1.520613, 2.009929, 2.989696",\ + "1.109834, 1.388913, 1.674567, 2.163882, 3.143650",\ + "1.449734, 1.728813, 2.014467, 2.503783, 3.483551",\ + "1.269552, 1.579294, 1.851281, 2.337945, 3.313730",\ + "1.277495, 1.587236, 1.859223, 2.345888, 3.321672",\ + "1.290975, 1.600716, 1.872703, 2.359368, 3.335152",\ + "1.444928, 1.754670, 2.026657, 2.513321, 3.489106",\ + "1.784829, 2.094570, 2.366557, 2.853222, 3.829007"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.061214, 0.061214, 0.061208, 0.061187, 0.061144",\ + "0.068565, 0.068565, 0.068561, 0.068546, 0.068517",\ + "0.090394, 0.090394, 0.090392, 0.090386, 0.090375",\ + "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\ + "1.025894, 1.025894, 1.025894, 1.025894, 1.025894",\ + "0.061214, 0.061214, 0.061207, 0.061187, 0.061144",\ + "0.068565, 0.068565, 0.068561, 0.068546, 0.068517",\ + "0.090394, 0.090394, 0.090392, 0.090386, 0.090375",\ + "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\ + "1.025894, 1.025894, 1.025894, 1.025894, 1.025894",\ + "0.061214, 0.061214, 0.061207, 0.061187, 0.061144",\ + "0.068565, 0.068565, 0.068561, 0.068546, 0.068517",\ + "0.090394, 0.090394, 0.090392, 0.090386, 0.090375",\ + "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\ + "1.025894, 1.025894, 1.025894, 1.025894, 1.025894",\ + "0.061214, 0.061214, 0.061207, 0.061187, 0.061144",\ + "0.068565, 0.068565, 0.068561, 0.068546, 0.068517",\ + "0.090394, 0.090394, 0.090392, 0.090386, 0.090375",\ + "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\ + "1.025894, 1.025894, 1.025894, 1.025894, 1.025894",\ + "0.061214, 0.061214, 0.061207, 0.061186, 0.061144",\ + "0.068565, 0.068565, 0.068561, 0.068546, 0.068517",\ + "0.090394, 0.090394, 0.090392, 0.090386, 0.090375",\ + "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\ + "1.025894, 1.025894, 1.025894, 1.025894, 1.025894"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_2668*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[44]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011"); + values ( "0.109772, 0.369798, 0.626503, 1.061758, 1.932266",\ + "0.120352, 0.381519, 0.640958, 1.080478, 1.959519",\ + "0.143356, 0.404296, 0.665874, 1.109884, 1.997905",\ + "0.467994, 0.696012, 0.968260, 1.421863, 2.329069",\ + "1.081974, 1.301531, 1.593583, 2.086339, 3.071851",\ + "0.198042, 0.457293, 0.713962, 1.148472, 2.018200",\ + "0.208624, 0.469024, 0.728430, 1.167192, 2.045453",\ + "0.231607, 0.491807, 0.753360, 1.196598, 2.083839",\ + "0.555400, 0.783574, 1.055776, 1.508577, 2.415003",\ + "1.169380, 1.389148, 1.681223, 2.173053, 3.157785",\ + "0.287235, 0.546131, 0.801923, 1.236093, 2.105155",\ + "0.297824, 0.557883, 0.816391, 1.254813, 2.132408",\ + "0.320747, 0.580678, 0.841322, 1.284219, 2.170794",\ + "0.636219, 0.872561, 1.143739, 1.596198, 2.501958",\ + "1.250216, 1.478256, 1.769187, 2.260674, 3.244740",\ + "0.350832, 0.611557, 0.866057, 1.300006, 2.168664",\ + "0.361428, 0.623341, 0.880526, 1.318726, 2.195917",\ + "0.384293, 0.646153, 0.905457, 1.348132, 2.234303",\ + "0.693839, 0.938203, 1.207876, 1.660111, 2.565467",\ + "1.307871, 1.544076, 1.833331, 2.324587, 3.308249",\ + "0.686914, 0.973559, 1.217580, 1.649209, 2.514120",\ + "0.697552, 0.985713, 1.232092, 1.667947, 2.541373",\ + "0.720052, 1.008731, 1.257069, 1.697372, 2.579759",\ + "1.005905, 1.302737, 1.559584, 2.009390, 2.910923",\ + "1.610583, 1.910693, 2.185437, 2.674028, 3.653705"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011"); + values ( "0.074635, 0.092924, 0.146295, 0.240037, 0.427522",\ + "0.102546, 0.120314, 0.177030, 0.284760, 0.500219",\ + "0.161902, 0.174975, 0.229446, 0.352350, 0.598157",\ + "0.823637, 0.823637, 0.866693, 1.014155, 1.309078",\ + "2.221941, 2.221941, 2.244858, 2.323347, 2.480325",\ + "0.074635, 0.093094, 0.146590, 0.240037, 0.427522",\ + "0.102546, 0.120480, 0.177368, 0.284760, 0.500219",\ + "0.161902, 0.175097, 0.229832, 0.352350, 0.598157",\ + "0.823637, 0.823637, 0.867157, 1.014155, 1.309078",\ + "2.221941, 2.221941, 2.245105, 2.323347, 2.480325",\ + "0.074635, 0.093474, 0.146595, 0.240037, 0.427522",\ + "0.102546, 0.120849, 0.177375, 0.284760, 0.500219",\ + "0.161902, 0.175368, 0.229839, 0.352350, 0.598157",\ + "0.823637, 0.823637, 0.867165, 1.014155, 1.309078",\ + "2.221941, 2.221941, 2.245110, 2.323347, 2.480325",\ + "0.074635, 0.094026, 0.146611, 0.240037, 0.427522",\ + "0.102546, 0.121384, 0.177393, 0.284760, 0.500219",\ + "0.161902, 0.175763, 0.229860, 0.352350, 0.598157",\ + "0.823637, 0.823637, 0.867190, 1.014155, 1.309078",\ + "2.221941, 2.221941, 2.245123, 2.323347, 2.480325",\ + "0.074635, 0.100491, 0.147562, 0.240424, 0.427522",\ + "0.102546, 0.127666, 0.178485, 0.285204, 0.500219",\ + "0.161902, 0.180384, 0.231107, 0.352857, 0.598157",\ + "0.823637, 0.823637, 0.868686, 1.014764, 1.309078",\ + "2.221941, 2.221941, 2.245919, 2.323671, 2.480325"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011"); + values ( "0.141728, 0.322683, 0.508414, 0.851578, 1.569056",\ + "0.147760, 0.329649, 0.526344, 0.903425, 1.657587",\ + "0.158195, 0.340967, 0.571363, 0.971528, 1.771856",\ + "0.298823, 0.523674, 0.808829, 1.303379, 2.292479",\ + "0.636132, 0.863255, 1.152943, 1.685611, 2.750947",\ + "0.229134, 0.410071, 0.595881, 0.938291, 1.654990",\ + "0.235166, 0.417039, 0.613620, 0.990139, 1.743521",\ + "0.245601, 0.428357, 0.658712, 1.058241, 1.857790",\ + "0.386229, 0.611242, 0.896475, 1.390093, 2.378412",\ + "0.723538, 0.950780, 1.240708, 1.772325, 2.836881",\ + "0.309995, 0.490402, 0.675907, 1.025913, 1.741945",\ + "0.316032, 0.497370, 0.701577, 1.077760, 1.830476",\ + "0.326472, 0.511248, 0.746671, 1.145863, 1.944745",\ + "0.467101, 0.700242, 0.984439, 1.477714, 2.465368",\ + "0.804387, 1.039684, 1.328675, 1.859946, 2.923836",\ + "0.367698, 0.547951, 0.733450, 1.089826, 1.805454",\ + "0.373747, 0.554919, 0.765701, 1.141673, 1.893985",\ + "0.384198, 0.576458, 0.810799, 1.209776, 2.008254",\ + "0.524826, 0.765905, 1.048583, 1.541627, 2.528877",\ + "0.862067, 1.105206, 1.392825, 1.923859, 2.987345",\ + "0.670854, 0.880709, 1.082881, 1.438713, 2.150910",\ + "0.677008, 0.904085, 1.116634, 1.490636, 2.239441",\ + "0.687558, 0.935916, 1.161966, 1.558834, 2.353710",\ + "0.834408, 1.130676, 1.400707, 1.891076, 2.874332",\ + "1.178988, 1.468337, 1.745336, 2.273465, 3.332801"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011"); + values ( "0.063168, 0.063168, 0.086452, 0.196369, 0.354186",\ + "0.068741, 0.068741, 0.139232, 0.228666, 0.407534",\ + "0.084603, 0.084603, 0.171201, 0.272810, 0.476028",\ + "0.381099, 0.384063, 0.433028, 0.586290, 0.892815",\ + "1.028844, 1.028844, 1.069845, 1.210271, 1.491123",\ + "0.063168, 0.063168, 0.086512, 0.196369, 0.354186",\ + "0.068741, 0.068741, 0.139513, 0.228666, 0.407534",\ + "0.084603, 0.084603, 0.171521, 0.272810, 0.476028",\ + "0.381099, 0.384091, 0.433510, 0.586290, 0.892815",\ + "1.028844, 1.028844, 1.070287, 1.210271, 1.491123",\ + "0.063168, 0.063168, 0.086512, 0.196369, 0.354186",\ + "0.068741, 0.068741, 0.139518, 0.228666, 0.407534",\ + "0.084603, 0.108819, 0.171527, 0.272810, 0.476028",\ + "0.381099, 0.384153, 0.433519, 0.586290, 0.892815",\ + "1.028844, 1.028844, 1.070295, 1.210271, 1.491123",\ + "0.063168, 0.063168, 0.086512, 0.196369, 0.354186",\ + "0.068741, 0.068741, 0.139534, 0.228666, 0.407534",\ + "0.084603, 0.109528, 0.171544, 0.272810, 0.476028",\ + "0.381099, 0.384242, 0.433545, 0.586290, 0.892815",\ + "1.028844, 1.028844, 1.070319, 1.210271, 1.491123",\ + "0.063168, 0.081414, 0.118527, 0.196695, 0.354186",\ + "0.068741, 0.094649, 0.140441, 0.229035, 0.407534",\ + "0.084603, 0.117839, 0.172574, 0.273230, 0.476028",\ + "0.381099, 0.385290, 0.435099, 0.586923, 0.892815",\ + "1.028844, 1.028844, 1.071743, 1.210851, 1.491123"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_2709*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[45]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011"); + values ( "0.715344, 0.975445, 1.253880, 1.716396, 2.641427",\ + "0.728896, 0.988997, 1.267432, 1.729948, 2.654979",\ + "0.752427, 1.012527, 1.290962, 1.753478, 2.678509",\ + "1.019800, 1.279901, 1.558336, 2.020853, 2.945885",\ + "1.613771, 1.873872, 2.152319, 2.614874, 3.539985",\ + "0.802750, 1.063030, 1.341425, 1.803109, 2.727360",\ + "0.816303, 1.076582, 1.354977, 1.816662, 2.740913",\ + "0.839833, 1.100112, 1.378507, 1.840192, 2.764443",\ + "1.107206, 1.367486, 1.645881, 2.107566, 3.031819",\ + "1.701178, 1.961458, 2.239864, 2.701588, 3.625918",\ + "0.883600, 1.152069, 1.429387, 1.890731, 2.814316",\ + "0.897153, 1.165621, 1.442940, 1.904283, 2.827868",\ + "0.920683, 1.189151, 1.466470, 1.927813, 2.851398",\ + "1.188056, 1.456525, 1.733844, 2.195188, 3.118774",\ + "1.782027, 2.050497, 2.327826, 2.789209, 3.712873",\ + "0.945225, 1.217787, 1.493526, 1.954644, 2.877825",\ + "0.958777, 1.231339, 1.507078, 1.968196, 2.891377",\ + "0.982307, 1.254869, 1.530608, 1.991726, 2.914907",\ + "1.249681, 1.522243, 1.797982, 2.259101, 3.182283",\ + "1.843652, 2.116215, 2.391965, 2.853122, 3.776382",\ + "1.282097, 1.583212, 1.845325, 2.303960, 3.223280",\ + "1.295649, 1.596764, 1.858877, 2.317512, 3.236833",\ + "1.319179, 1.620294, 1.882407, 2.341042, 3.260363",\ + "1.586553, 1.887668, 2.149781, 2.608417, 3.527739",\ + "2.180524, 2.481639, 2.743765, 3.202439, 4.121839"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011"); + values ( "0.121334, 0.121334, 0.121335, 0.121336, 0.121339",\ + "0.151694, 0.151694, 0.151694, 0.151693, 0.151692",\ + "0.201129, 0.201129, 0.201129, 0.201130, 0.201131",\ + "0.823409, 0.823409, 0.823409, 0.823408, 0.823406",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121334, 0.121334, 0.121335, 0.121336, 0.121339",\ + "0.151694, 0.151694, 0.151694, 0.151693, 0.151692",\ + "0.201129, 0.201129, 0.201129, 0.201130, 0.201131",\ + "0.823409, 0.823409, 0.823409, 0.823408, 0.823406",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121334, 0.121334, 0.121335, 0.121336, 0.121339",\ + "0.151694, 0.151694, 0.151694, 0.151693, 0.151692",\ + "0.201129, 0.201129, 0.201129, 0.201130, 0.201131",\ + "0.823409, 0.823409, 0.823409, 0.823408, 0.823406",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121334, 0.121334, 0.121335, 0.121336, 0.121339",\ + "0.151694, 0.151694, 0.151694, 0.151693, 0.151692",\ + "0.201129, 0.201129, 0.201129, 0.201130, 0.201131",\ + "0.823409, 0.823409, 0.823409, 0.823408, 0.823406",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121334, 0.121334, 0.121335, 0.121336, 0.121339",\ + "0.151694, 0.151694, 0.151694, 0.151693, 0.151692",\ + "0.201129, 0.201129, 0.201129, 0.201130, 0.201131",\ + "0.823409, 0.823409, 0.823409, 0.823408, 0.823406",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011"); + values ( "0.683121, 0.943222, 1.221668, 1.684223, 2.609334",\ + "0.691063, 0.951164, 1.229611, 1.692166, 2.617276",\ + "0.704543, 0.964644, 1.243091, 1.705646, 2.630756",\ + "0.858497, 1.118598, 1.397044, 1.859599, 2.784709",\ + "1.198397, 1.458498, 1.736945, 2.199500, 3.124610",\ + "0.770527, 1.030807, 1.309213, 1.770937, 2.695267",\ + "0.778469, 1.038749, 1.317156, 1.778880, 2.703210",\ + "0.791949, 1.052229, 1.330636, 1.792360, 2.716690",\ + "0.945903, 1.206183, 1.484589, 1.946313, 2.870643",\ + "1.285803, 1.546083, 1.824489, 2.286213, 3.210544",\ + "0.851377, 1.119846, 1.397176, 1.858559, 2.782223",\ + "0.859320, 1.127788, 1.405118, 1.866501, 2.790165",\ + "0.872799, 1.141268, 1.418598, 1.879981, 2.803645",\ + "1.026753, 1.295222, 1.572552, 2.033935, 2.957598",\ + "1.366653, 1.635122, 1.912452, 2.373835, 3.297499",\ + "0.913002, 1.185564, 1.461314, 1.922472, 2.845731",\ + "0.920944, 1.193506, 1.469257, 1.930414, 2.853674",\ + "0.934424, 1.206986, 1.482737, 1.943894, 2.867154",\ + "1.088378, 1.360940, 1.636690, 2.097847, 3.021107",\ + "1.428278, 1.700840, 1.976590, 2.437748, 3.361008",\ + "1.249874, 1.550989, 1.813114, 2.271788, 3.191187",\ + "1.257816, 1.558931, 1.821056, 2.279730, 3.199130",\ + "1.271296, 1.572411, 1.834536, 2.293210, 3.212610",\ + "1.425250, 1.726365, 1.988490, 2.447164, 3.366563",\ + "1.765150, 2.066265, 2.328390, 2.787064, 3.706464"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011"); + values ( "0.061213, 0.061213, 0.061210, 0.061198, 0.061174",\ + "0.068565, 0.068565, 0.068562, 0.068554, 0.068538",\ + "0.090394, 0.090394, 0.090393, 0.090389, 0.090383",\ + "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\ + "1.025894, 1.025894, 1.025894, 1.025894, 1.025894",\ + "0.061213, 0.061213, 0.061210, 0.061198, 0.061174",\ + "0.068565, 0.068565, 0.068562, 0.068554, 0.068538",\ + "0.090394, 0.090394, 0.090393, 0.090389, 0.090383",\ + "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\ + "1.025894, 1.025894, 1.025894, 1.025894, 1.025894",\ + "0.061213, 0.061213, 0.061210, 0.061198, 0.061174",\ + "0.068565, 0.068565, 0.068562, 0.068554, 0.068538",\ + "0.090394, 0.090394, 0.090393, 0.090389, 0.090383",\ + "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\ + "1.025894, 1.025894, 1.025894, 1.025894, 1.025894",\ + "0.061213, 0.061213, 0.061210, 0.061198, 0.061174",\ + "0.068565, 0.068565, 0.068562, 0.068554, 0.068538",\ + "0.090394, 0.090394, 0.090393, 0.090389, 0.090383",\ + "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\ + "1.025894, 1.025894, 1.025894, 1.025894, 1.025894",\ + "0.061213, 0.061213, 0.061210, 0.061198, 0.061174",\ + "0.068565, 0.068565, 0.068562, 0.068554, 0.068538",\ + "0.090394, 0.090394, 0.090393, 0.090389, 0.090383",\ + "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\ + "1.025894, 1.025894, 1.025894, 1.025894, 1.025894"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_2681*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[16]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011"); + values ( "0.385362, 0.574573, 0.765319, 1.061205, 1.627908",\ + "0.404628, 0.593839, 0.784585, 1.080471, 1.647174",\ + "0.436306, 0.625517, 0.816263, 1.112149, 1.678852",\ + "0.725958, 0.915169, 1.105914, 1.401800, 1.968502",\ + "1.319903, 1.509114, 1.699858, 1.995744, 2.562446",\ + "0.473615, 0.661891, 0.852600, 1.148510, 1.715261",\ + "0.492881, 0.681157, 0.871866, 1.167776, 1.734527",\ + "0.524560, 0.712836, 0.903544, 1.199454, 1.766205",\ + "0.814212, 1.002488, 1.193195, 1.489105, 2.055855",\ + "1.408156, 1.596432, 1.787139, 2.083049, 2.649799",\ + "0.562261, 0.742226, 0.932626, 1.228538, 1.795292",\ + "0.581527, 0.761492, 0.951893, 1.247805, 1.814559",\ + "0.613206, 0.793171, 0.983571, 1.279483, 1.846237",\ + "0.902858, 1.082823, 1.273222, 1.569133, 2.135887",\ + "1.496802, 1.676767, 1.867166, 2.163077, 2.729831",\ + "0.620370, 0.800057, 0.990350, 1.285975, 1.852322",\ + "0.639636, 0.819323, 1.009616, 1.305241, 1.871588",\ + "0.671315, 0.851002, 1.041294, 1.336920, 1.903266",\ + "0.960967, 1.140654, 1.330945, 1.626570, 2.192916",\ + "1.554911, 1.734598, 1.924889, 2.220514, 2.786860",\ + "0.922623, 1.105385, 1.294011, 1.589153, 2.154560",\ + "0.941889, 1.124651, 1.313277, 1.608420, 2.173826",\ + "0.973567, 1.156330, 1.344955, 1.640098, 2.205504",\ + "1.263219, 1.445982, 1.634606, 1.929748, 2.495154",\ + "1.857164, 2.039926, 2.228550, 2.523692, 3.089098"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011"); + values ( "0.107385, 0.107385, 0.107386, 0.107387, 0.107387",\ + "0.140617, 0.140617, 0.140617, 0.140618, 0.140619",\ + "0.189797, 0.189797, 0.189797, 0.189797, 0.189798",\ + "0.817737, 0.817737, 0.817737, 0.817737, 0.817737",\ + "2.195570, 2.195570, 2.195569, 2.195569, 2.195568",\ + "0.107385, 0.107385, 0.107386, 0.107387, 0.107387",\ + "0.140617, 0.140617, 0.140617, 0.140618, 0.140619",\ + "0.189797, 0.189797, 0.189797, 0.189797, 0.189798",\ + "0.817737, 0.817737, 0.817737, 0.817737, 0.817737",\ + "2.195570, 2.195570, 2.195569, 2.195569, 2.195568",\ + "0.107385, 0.107385, 0.107386, 0.107387, 0.107387",\ + "0.140617, 0.140617, 0.140617, 0.140618, 0.140619",\ + "0.189797, 0.189797, 0.189797, 0.189797, 0.189798",\ + "0.817737, 0.817737, 0.817737, 0.817737, 0.817737",\ + "2.195570, 2.195570, 2.195569, 2.195569, 2.195568",\ + "0.107385, 0.107385, 0.107386, 0.107387, 0.107387",\ + "0.140617, 0.140617, 0.140617, 0.140618, 0.140619",\ + "0.189797, 0.189797, 0.189797, 0.189797, 0.189798",\ + "0.817737, 0.817737, 0.817737, 0.817737, 0.817737",\ + "2.195570, 2.195570, 2.195569, 2.195569, 2.195568",\ + "0.107385, 0.107385, 0.107386, 0.107387, 0.107387",\ + "0.140617, 0.140617, 0.140617, 0.140618, 0.140619",\ + "0.189797, 0.189797, 0.189797, 0.189797, 0.189798",\ + "0.817737, 0.817737, 0.817737, 0.817737, 0.817737",\ + "2.195570, 2.195570, 2.195569, 2.195569, 2.195568"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011"); + values ( "0.395642, 0.585187, 0.775931, 1.071620, 1.637841",\ + "0.403773, 0.592984, 0.783728, 1.079613, 1.646315",\ + "0.417192, 0.606403, 0.797147, 1.093032, 1.659734",\ + "0.569868, 0.759079, 0.949823, 1.245708, 1.812411",\ + "0.903831, 1.093042, 1.283787, 1.579672, 2.146375",\ + "0.483904, 0.672505, 0.863212, 1.158925, 1.725194",\ + "0.492026, 0.680302, 0.871009, 1.166918, 1.733668",\ + "0.505446, 0.693722, 0.884428, 1.180337, 1.747088",\ + "0.658121, 0.846397, 1.037104, 1.333013, 1.899764",\ + "0.992085, 1.180361, 1.371068, 1.666977, 2.233728",\ + "0.572576, 0.752841, 0.943239, 1.238954, 1.805226",\ + "0.580672, 0.760637, 0.951036, 1.246946, 1.813700",\ + "0.594092, 0.774057, 0.964455, 1.260366, 1.827119",\ + "0.746767, 0.926732, 1.117131, 1.413042, 1.979796",\ + "1.080731, 1.260696, 1.451095, 1.747006, 2.313760",\ + "0.630984, 0.810671, 1.000962, 1.296390, 1.862254",\ + "0.638781, 0.818468, 1.008759, 1.304383, 1.870729",\ + "0.652200, 0.831887, 1.022178, 1.317803, 1.884149",\ + "0.804876, 0.984563, 1.174854, 1.470479, 2.036825",\ + "1.138840, 1.318527, 1.508818, 1.804443, 2.370789",\ + "0.933237, 1.115999, 1.304623, 1.599568, 2.164490",\ + "0.941034, 1.123796, 1.312420, 1.607561, 2.172967",\ + "0.954453, 1.137215, 1.325839, 1.620981, 2.186387",\ + "1.107129, 1.289891, 1.478515, 1.773657, 2.339063",\ + "1.441092, 1.623855, 1.812479, 2.107621, 2.673027"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011"); + values ( "0.049251, 0.049251, 0.049251, 0.049251, 0.049251",\ + "0.055580, 0.055580, 0.055580, 0.055580, 0.055580",\ + "0.075314, 0.075314, 0.075314, 0.075314, 0.075314",\ + "0.368762, 0.368762, 0.368762, 0.368762, 0.368762",\ + "1.002200, 1.002200, 1.002200, 1.002200, 1.002201",\ + "0.049251, 0.049251, 0.049251, 0.049251, 0.049251",\ + "0.055580, 0.055580, 0.055580, 0.055580, 0.055580",\ + "0.075314, 0.075314, 0.075314, 0.075314, 0.075314",\ + "0.368762, 0.368762, 0.368762, 0.368762, 0.368762",\ + "1.002200, 1.002200, 1.002200, 1.002200, 1.002201",\ + "0.049251, 0.049251, 0.049251, 0.049251, 0.049251",\ + "0.055580, 0.055580, 0.055580, 0.055580, 0.055580",\ + "0.075314, 0.075314, 0.075314, 0.075314, 0.075314",\ + "0.368762, 0.368762, 0.368762, 0.368762, 0.368762",\ + "1.002200, 1.002200, 1.002200, 1.002200, 1.002201",\ + "0.049251, 0.049251, 0.049251, 0.049251, 0.049251",\ + "0.055580, 0.055580, 0.055580, 0.055580, 0.055580",\ + "0.075314, 0.075314, 0.075314, 0.075314, 0.075314",\ + "0.368762, 0.368762, 0.368762, 0.368762, 0.368762",\ + "1.002200, 1.002200, 1.002200, 1.002200, 1.002201",\ + "0.049251, 0.049251, 0.049251, 0.049251, 0.049251",\ + "0.055580, 0.055580, 0.055580, 0.055580, 0.055580",\ + "0.075314, 0.075314, 0.075314, 0.075314, 0.075314",\ + "0.368762, 0.368762, 0.368762, 0.368762, 0.368762",\ + "1.002200, 1.002200, 1.002200, 1.002200, 1.002201"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_min_2495*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[20]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.535388, 0.757178, 0.935245, 1.224116, 1.784806",\ + "0.554760, 0.776550, 0.954617, 1.243488, 1.804178",\ + "0.586214, 0.808003, 0.986070, 1.274942, 1.835631",\ + "0.875148, 1.096938, 1.275005, 1.563877, 2.124566",\ + "1.469041, 1.690830, 1.868897, 2.157769, 2.718458",\ + "0.623792, 0.844496, 1.022526, 1.311421, 1.872159",\ + "0.643164, 0.863868, 1.041898, 1.330793, 1.891531",\ + "0.674618, 0.895322, 1.073351, 1.362247, 1.922985",\ + "0.963552, 1.184257, 1.362286, 1.651182, 2.211919",\ + "1.557444, 1.778149, 1.956178, 2.245074, 2.805811",\ + "0.712864, 0.924832, 1.102553, 1.391450, 1.952191",\ + "0.732236, 0.944203, 1.121924, 1.410822, 1.971563",\ + "0.763690, 0.975657, 1.153378, 1.442276, 2.003016",\ + "1.052624, 1.264592, 1.442313, 1.731210, 2.291951",\ + "1.646516, 1.858484, 2.036205, 2.325102, 2.885843",\ + "0.776122, 0.982654, 1.160246, 1.448879, 2.009206",\ + "0.795494, 1.002026, 1.179617, 1.468251, 2.028577",\ + "0.826948, 1.033479, 1.211071, 1.499705, 2.060031",\ + "1.115882, 1.322414, 1.500006, 1.788640, 2.348966",\ + "1.709774, 1.916306, 2.093898, 2.382532, 2.942858",\ + "1.107140, 1.287923, 1.463902, 1.752051, 2.311426",\ + "1.126512, 1.307295, 1.483274, 1.771423, 2.330798",\ + "1.157965, 1.338748, 1.514728, 1.802877, 2.362252",\ + "1.446900, 1.627683, 1.803662, 2.091812, 2.651186",\ + "2.040792, 2.221575, 2.397554, 2.685704, 3.245078"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.108154, 0.108154, 0.108154, 0.108154, 0.108154",\ + "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\ + "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\ + "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\ + "2.194880, 2.194880, 2.194880, 2.194880, 2.194880",\ + "0.108154, 0.108154, 0.108154, 0.108154, 0.108154",\ + "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\ + "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\ + "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\ + "2.194880, 2.194880, 2.194880, 2.194880, 2.194880",\ + "0.108154, 0.108154, 0.108154, 0.108154, 0.108154",\ + "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\ + "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\ + "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\ + "2.194880, 2.194880, 2.194880, 2.194880, 2.194880",\ + "0.108154, 0.108154, 0.108154, 0.108154, 0.108154",\ + "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\ + "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\ + "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\ + "2.194880, 2.194880, 2.194880, 2.194880, 2.194880",\ + "0.108154, 0.108154, 0.108154, 0.108154, 0.108154",\ + "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\ + "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\ + "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\ + "2.194880, 2.194880, 2.194880, 2.194880, 2.194880"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.544632, 0.766422, 0.944489, 1.233360, 1.794050",\ + "0.552443, 0.774232, 0.952299, 1.241171, 1.801860",\ + "0.565862, 0.787651, 0.965718, 1.254590, 1.815279",\ + "0.718832, 0.940622, 1.118689, 1.407560, 1.968250",\ + "1.052901, 1.274690, 1.452757, 1.741629, 2.302318",\ + "0.633036, 0.853740, 1.031770, 1.320665, 1.881403",\ + "0.640847, 0.861551, 1.039580, 1.328476, 1.889213",\ + "0.654266, 0.874970, 1.052999, 1.341895, 1.902633",\ + "0.807236, 1.027940, 1.205970, 1.494865, 2.055603",\ + "1.141305, 1.362009, 1.540038, 1.828934, 2.389672",\ + "0.722108, 0.934075, 1.111796, 1.400694, 1.961435",\ + "0.729918, 0.941886, 1.119607, 1.408504, 1.969245",\ + "0.743338, 0.955305, 1.133026, 1.421923, 1.982664",\ + "0.896308, 1.108276, 1.285997, 1.574894, 2.135635",\ + "1.230376, 1.442344, 1.620065, 1.908962, 2.469703",\ + "0.785366, 0.991898, 1.169490, 1.458123, 2.018450",\ + "0.793177, 0.999708, 1.177300, 1.465934, 2.026260",\ + "0.806596, 1.013127, 1.190719, 1.479353, 2.039679",\ + "0.959566, 1.166098, 1.343690, 1.632324, 2.192650",\ + "1.293635, 1.500166, 1.677758, 1.966392, 2.526718",\ + "1.116384, 1.297167, 1.473146, 1.761295, 2.320670",\ + "1.124194, 1.304977, 1.480956, 1.769106, 2.328480",\ + "1.137613, 1.318397, 1.494376, 1.782525, 2.341900",\ + "1.290584, 1.471367, 1.647346, 1.935495, 2.494870",\ + "1.624652, 1.805435, 1.981414, 2.269564, 2.828938"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.046250, 0.046250, 0.046250, 0.046250, 0.046250",\ + "0.051898, 0.051898, 0.051898, 0.051898, 0.051898",\ + "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\ + "0.368839, 0.368839, 0.368839, 0.368839, 0.368839",\ + "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\ + "0.046250, 0.046250, 0.046250, 0.046250, 0.046250",\ + "0.051898, 0.051898, 0.051898, 0.051898, 0.051898",\ + "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\ + "0.368839, 0.368839, 0.368839, 0.368839, 0.368839",\ + "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\ + "0.046250, 0.046250, 0.046250, 0.046250, 0.046250",\ + "0.051898, 0.051898, 0.051898, 0.051898, 0.051898",\ + "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\ + "0.368839, 0.368839, 0.368839, 0.368839, 0.368839",\ + "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\ + "0.046250, 0.046250, 0.046250, 0.046250, 0.046250",\ + "0.051898, 0.051898, 0.051898, 0.051898, 0.051898",\ + "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\ + "0.368839, 0.368839, 0.368839, 0.368839, 0.368839",\ + "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\ + "0.046250, 0.046250, 0.046250, 0.046250, 0.046250",\ + "0.051898, 0.051898, 0.051898, 0.051898, 0.051898",\ + "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\ + "0.368839, 0.368839, 0.368839, 0.368839, 0.368839",\ + "1.000959, 1.000959, 1.000959, 1.000959, 1.000959"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_min_2650*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[22]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.511815, 0.739156, 0.923211, 1.217666, 1.786831",\ + "0.531187, 0.758528, 0.942583, 1.237038, 1.806203",\ + "0.562641, 0.789981, 0.974037, 1.268491, 1.837657",\ + "0.851575, 1.078916, 1.262971, 1.557426, 2.126591",\ + "1.445467, 1.672808, 1.856863, 2.151318, 2.720483",\ + "0.600144, 0.826474, 1.010492, 1.304971, 1.874184",\ + "0.619516, 0.845846, 1.029864, 1.324343, 1.893556",\ + "0.650970, 0.877300, 1.061317, 1.355796, 1.925010",\ + "0.939904, 1.166234, 1.350252, 1.644731, 2.213945",\ + "1.533796, 1.760126, 1.944144, 2.238623, 2.807837",\ + "0.689248, 0.906807, 1.090519, 1.384999, 1.954216",\ + "0.708620, 0.926179, 1.109891, 1.404371, 1.973588",\ + "0.740074, 0.957633, 1.141344, 1.435825, 2.005042",\ + "1.029009, 1.246567, 1.430279, 1.724759, 2.293976",\ + "1.622900, 1.840459, 2.024171, 2.318651, 2.887868",\ + "0.752647, 0.964632, 1.148227, 1.442439, 2.011252",\ + "0.772019, 0.984004, 1.167598, 1.461811, 2.030624",\ + "0.803473, 1.015458, 1.199052, 1.493265, 2.062078",\ + "1.092407, 1.304392, 1.487987, 1.782200, 2.351013",\ + "1.686299, 1.898284, 2.081879, 2.376091, 2.944905",\ + "1.087484, 1.269911, 1.451885, 1.745620, 2.313499",\ + "1.106856, 1.289283, 1.471256, 1.764992, 2.332871",\ + "1.138310, 1.320737, 1.502710, 1.796445, 2.364325",\ + "1.427244, 1.609671, 1.791645, 2.085380, 2.653259",\ + "2.021136, 2.203563, 2.385537, 2.679272, 3.247151"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.108154, 0.108154, 0.108154, 0.108154, 0.108154",\ + "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\ + "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\ + "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\ + "2.194880, 2.194880, 2.194880, 2.194880, 2.194880",\ + "0.108154, 0.108154, 0.108154, 0.108154, 0.108154",\ + "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\ + "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\ + "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\ + "2.194880, 2.194880, 2.194880, 2.194880, 2.194880",\ + "0.108154, 0.108154, 0.108154, 0.108154, 0.108154",\ + "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\ + "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\ + "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\ + "2.194880, 2.194880, 2.194880, 2.194880, 2.194880",\ + "0.108154, 0.108154, 0.108154, 0.108154, 0.108154",\ + "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\ + "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\ + "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\ + "2.194880, 2.194880, 2.194880, 2.194880, 2.194880",\ + "0.108154, 0.108154, 0.108154, 0.108154, 0.108154",\ + "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\ + "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\ + "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\ + "2.194880, 2.194880, 2.194880, 2.194880, 2.194880"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.521059, 0.748400, 0.932455, 1.226910, 1.796075",\ + "0.528870, 0.756210, 0.940265, 1.234720, 1.803885",\ + "0.542289, 0.769629, 0.953685, 1.248139, 1.817305",\ + "0.695259, 0.922600, 1.106655, 1.401110, 1.970275",\ + "1.029328, 1.256668, 1.440723, 1.735178, 2.304343",\ + "0.609388, 0.835718, 1.019736, 1.314215, 1.883428",\ + "0.617199, 0.843528, 1.027546, 1.322025, 1.891239",\ + "0.630618, 0.856948, 1.040965, 1.335444, 1.904658",\ + "0.783588, 1.009918, 1.193936, 1.488415, 2.057629",\ + "1.117657, 1.343987, 1.528004, 1.822483, 2.391697",\ + "0.698492, 0.916051, 1.099763, 1.394243, 1.963460",\ + "0.706303, 0.923862, 1.107573, 1.402054, 1.971270",\ + "0.719722, 0.937281, 1.120992, 1.415473, 1.984690",\ + "0.872692, 1.090251, 1.273963, 1.568443, 2.137660",\ + "1.206761, 1.424320, 1.608031, 1.902512, 2.471728",\ + "0.761891, 0.973876, 1.157471, 1.451683, 2.020496",\ + "0.769701, 0.981686, 1.165281, 1.459494, 2.028307",\ + "0.783120, 0.995106, 1.178700, 1.472913, 2.041726",\ + "0.936091, 1.148076, 1.331671, 1.625883, 2.194696",\ + "1.270159, 1.482144, 1.665739, 1.959952, 2.528765",\ + "1.096728, 1.279155, 1.461128, 1.754864, 2.322743",\ + "1.104538, 1.286965, 1.468939, 1.762674, 2.330553",\ + "1.117958, 1.300385, 1.482358, 1.776093, 2.343972",\ + "1.270928, 1.453355, 1.635329, 1.929064, 2.496943",\ + "1.604996, 1.787423, 1.969397, 2.263132, 2.831011"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.046251, 0.046251, 0.046251, 0.046251, 0.046251",\ + "0.051898, 0.051898, 0.051898, 0.051898, 0.051898",\ + "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\ + "0.368839, 0.368839, 0.368839, 0.368839, 0.368839",\ + "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\ + "0.046251, 0.046251, 0.046251, 0.046251, 0.046251",\ + "0.051898, 0.051898, 0.051898, 0.051898, 0.051898",\ + "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\ + "0.368839, 0.368839, 0.368839, 0.368839, 0.368839",\ + "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\ + "0.046251, 0.046251, 0.046251, 0.046251, 0.046251",\ + "0.051898, 0.051898, 0.051898, 0.051898, 0.051898",\ + "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\ + "0.368839, 0.368839, 0.368839, 0.368839, 0.368839",\ + "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\ + "0.046251, 0.046251, 0.046251, 0.046251, 0.046251",\ + "0.051898, 0.051898, 0.051898, 0.051898, 0.051898",\ + "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\ + "0.368839, 0.368839, 0.368839, 0.368839, 0.368839",\ + "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\ + "0.046251, 0.046251, 0.046251, 0.046251, 0.046251",\ + "0.051898, 0.051898, 0.051898, 0.051898, 0.051898",\ + "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\ + "0.368839, 0.368839, 0.368839, 0.368839, 0.368839",\ + "1.000959, 1.000959, 1.000959, 1.000959, 1.000959"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_min_2744*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[23]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011"); + values ( "0.459602, 0.694897, 0.884768, 1.189946, 1.780432",\ + "0.478889, 0.714184, 0.904055, 1.209233, 1.799719",\ + "0.510523, 0.745818, 0.935689, 1.240867, 1.831353",\ + "0.800033, 1.035329, 1.225199, 1.530377, 2.120863",\ + "1.393967, 1.629262, 1.819133, 2.124311, 2.714797",\ + "0.548080, 0.782215, 0.972049, 1.277251, 1.867785",\ + "0.567367, 0.801502, 0.991336, 1.296538, 1.887073",\ + "0.599001, 0.833136, 1.022970, 1.328172, 1.918707",\ + "0.888512, 1.122647, 1.312480, 1.617682, 2.208217",\ + "1.482446, 1.716581, 1.906414, 2.211616, 2.802151",\ + "0.637650, 0.862548, 1.052076, 1.357279, 1.947817",\ + "0.656937, 0.881835, 1.071363, 1.376566, 1.967104",\ + "0.688571, 0.913469, 1.102997, 1.408201, 1.998738",\ + "0.978081, 1.202980, 1.392507, 1.697711, 2.288249",\ + "1.572015, 1.796914, 1.986441, 2.291645, 2.882183",\ + "0.701494, 0.920383, 1.109797, 1.414745, 2.004905",\ + "0.720781, 0.939670, 1.129084, 1.434032, 2.024192",\ + "0.752415, 0.971304, 1.160718, 1.465667, 2.055826",\ + "1.041925, 1.260814, 1.450228, 1.755177, 2.345336",\ + "1.635859, 1.854748, 2.044163, 2.349111, 2.939270",\ + "1.039162, 1.225730, 1.413457, 1.717948, 2.307214",\ + "1.058449, 1.245017, 1.432744, 1.737235, 2.326501",\ + "1.090083, 1.276651, 1.464378, 1.768869, 2.358135",\ + "1.379594, 1.566161, 1.753889, 2.058379, 2.647645",\ + "1.973528, 2.160095, 2.347823, 2.652313, 3.241579"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011"); + values ( "0.107537, 0.107537, 0.107537, 0.107537, 0.107537",\ + "0.140565, 0.140565, 0.140565, 0.140565, 0.140565",\ + "0.189766, 0.189766, 0.189766, 0.189766, 0.189766",\ + "0.817728, 0.817728, 0.817728, 0.817728, 0.817728",\ + "2.195434, 2.195434, 2.195434, 2.195434, 2.195434",\ + "0.107537, 0.107537, 0.107537, 0.107537, 0.107537",\ + "0.140565, 0.140565, 0.140565, 0.140565, 0.140565",\ + "0.189766, 0.189766, 0.189766, 0.189766, 0.189766",\ + "0.817728, 0.817728, 0.817728, 0.817728, 0.817728",\ + "2.195434, 2.195434, 2.195434, 2.195434, 2.195434",\ + "0.107537, 0.107537, 0.107537, 0.107537, 0.107537",\ + "0.140565, 0.140565, 0.140565, 0.140565, 0.140565",\ + "0.189766, 0.189766, 0.189766, 0.189766, 0.189766",\ + "0.817728, 0.817728, 0.817728, 0.817728, 0.817728",\ + "2.195434, 2.195434, 2.195434, 2.195434, 2.195434",\ + "0.107537, 0.107537, 0.107537, 0.107537, 0.107537",\ + "0.140565, 0.140565, 0.140565, 0.140565, 0.140565",\ + "0.189766, 0.189766, 0.189766, 0.189766, 0.189766",\ + "0.817728, 0.817728, 0.817728, 0.817728, 0.817728",\ + "2.195434, 2.195434, 2.195434, 2.195434, 2.195434",\ + "0.107537, 0.107537, 0.107537, 0.107537, 0.107537",\ + "0.140565, 0.140565, 0.140565, 0.140565, 0.140565",\ + "0.189766, 0.189766, 0.189766, 0.189766, 0.189766",\ + "0.817728, 0.817728, 0.817728, 0.817728, 0.817728",\ + "2.195434, 2.195434, 2.195434, 2.195434, 2.195434"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011"); + values ( "0.469945, 0.705240, 0.895111, 1.200289, 1.790776",\ + "0.477744, 0.713040, 0.902911, 1.208089, 1.798575",\ + "0.491164, 0.726459, 0.916330, 1.221508, 1.811994",\ + "0.643898, 0.879193, 1.069064, 1.374242, 1.964728",\ + "0.977882, 1.213178, 1.403048, 1.708226, 2.298713",\ + "0.558424, 0.792559, 0.982392, 1.287594, 1.878129",\ + "0.566223, 0.800358, 0.990192, 1.295394, 1.885928",\ + "0.579643, 0.813778, 1.003611, 1.308813, 1.899348",\ + "0.732376, 0.966511, 1.156345, 1.461547, 2.052081",\ + "1.066361, 1.300496, 1.490329, 1.795531, 2.386066",\ + "0.647993, 0.872891, 1.062419, 1.367623, 1.958161",\ + "0.655793, 0.880691, 1.070219, 1.375422, 1.965960",\ + "0.669212, 0.894110, 1.083638, 1.388842, 1.979379",\ + "0.821946, 1.046844, 1.236372, 1.541575, 2.132113",\ + "1.155930, 1.380829, 1.570356, 1.875560, 2.466098",\ + "0.711837, 0.930726, 1.120141, 1.425089, 2.015248",\ + "0.719636, 0.938526, 1.127940, 1.432888, 2.023048",\ + "0.733056, 0.951945, 1.141359, 1.446308, 2.036467",\ + "0.885790, 1.104679, 1.294093, 1.599041, 2.189201",\ + "1.219774, 1.438663, 1.628078, 1.933026, 2.523185",\ + "1.049506, 1.236073, 1.423800, 1.728291, 2.317557",\ + "1.057305, 1.243873, 1.431600, 1.736091, 2.325356",\ + "1.070724, 1.257292, 1.445019, 1.749510, 2.338776",\ + "1.223458, 1.410026, 1.597753, 1.902244, 2.491510",\ + "1.557443, 1.744010, 1.931738, 2.236228, 2.825494"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011"); + values ( "0.049261, 0.049261, 0.049261, 0.049261, 0.049261",\ + "0.055612, 0.055612, 0.055612, 0.055612, 0.055612",\ + "0.075309, 0.075309, 0.075309, 0.075309, 0.075309",\ + "0.368777, 0.368777, 0.368777, 0.368777, 0.368777",\ + "1.002182, 1.002182, 1.002182, 1.002182, 1.002182",\ + "0.049261, 0.049261, 0.049261, 0.049261, 0.049261",\ + "0.055612, 0.055612, 0.055612, 0.055612, 0.055612",\ + "0.075309, 0.075309, 0.075309, 0.075309, 0.075309",\ + "0.368777, 0.368777, 0.368777, 0.368777, 0.368777",\ + "1.002182, 1.002182, 1.002182, 1.002182, 1.002182",\ + "0.049261, 0.049261, 0.049261, 0.049261, 0.049261",\ + "0.055612, 0.055612, 0.055612, 0.055612, 0.055612",\ + "0.075309, 0.075309, 0.075309, 0.075309, 0.075309",\ + "0.368777, 0.368777, 0.368777, 0.368777, 0.368777",\ + "1.002182, 1.002182, 1.002182, 1.002182, 1.002182",\ + "0.049261, 0.049261, 0.049261, 0.049261, 0.049261",\ + "0.055612, 0.055612, 0.055612, 0.055612, 0.055612",\ + "0.075309, 0.075309, 0.075309, 0.075309, 0.075309",\ + "0.368777, 0.368777, 0.368777, 0.368777, 0.368777",\ + "1.002182, 1.002182, 1.002182, 1.002182, 1.002182",\ + "0.049261, 0.049261, 0.049261, 0.049261, 0.049261",\ + "0.055612, 0.055612, 0.055612, 0.055612, 0.055612",\ + "0.075309, 0.075309, 0.075309, 0.075309, 0.075309",\ + "0.368777, 0.368777, 0.368777, 0.368777, 0.368777",\ + "1.002182, 1.002182, 1.002182, 1.002182, 1.002182"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_min*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[25]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011"); + values ( "0.443166, 0.674145, 0.859025, 1.158118, 1.738072",\ + "0.462453, 0.693432, 0.878312, 1.177405, 1.757359",\ + "0.494087, 0.725066, 0.909946, 1.209039, 1.788993",\ + "0.783598, 1.014576, 1.199456, 1.498549, 2.078503",\ + "1.377531, 1.608510, 1.793390, 2.092483, 2.672437",\ + "0.531545, 0.761463, 0.946306, 1.245423, 1.825425",\ + "0.550832, 0.780750, 0.965593, 1.264710, 1.844712",\ + "0.582466, 0.812384, 0.997227, 1.296344, 1.876346",\ + "0.871976, 1.101894, 1.286737, 1.585854, 2.165856",\ + "1.465910, 1.695828, 1.880671, 2.179788, 2.759790",\ + "0.621124, 0.841793, 1.026333, 1.325452, 1.905457",\ + "0.640411, 0.861080, 1.045620, 1.344739, 1.924744",\ + "0.672045, 0.892714, 1.077254, 1.376373, 1.956378",\ + "0.961555, 1.182224, 1.366764, 1.665883, 2.245888",\ + "1.555489, 1.776158, 1.960698, 2.259817, 2.839822",\ + "0.685109, 0.899623, 1.084043, 1.382905, 1.962520",\ + "0.704396, 0.918910, 1.103330, 1.402192, 1.981807",\ + "0.736030, 0.950545, 1.134964, 1.433826, 2.013442",\ + "1.025540, 1.240054, 1.424474, 1.723336, 2.302952",\ + "1.619474, 1.833988, 2.018408, 2.317270, 2.896885",\ + "1.023662, 1.204930, 1.387700, 1.686096, 2.264800",\ + "1.042949, 1.224217, 1.406987, 1.705384, 2.284087",\ + "1.074583, 1.255852, 1.438621, 1.737018, 2.315721",\ + "1.364093, 1.545362, 1.728131, 2.026528, 2.605231",\ + "1.958027, 2.139296, 2.322065, 2.620461, 3.199165"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011"); + values ( "0.107537, 0.107537, 0.107537, 0.107537, 0.107537",\ + "0.140565, 0.140565, 0.140565, 0.140565, 0.140565",\ + "0.189766, 0.189766, 0.189766, 0.189766, 0.189766",\ + "0.817728, 0.817728, 0.817728, 0.817728, 0.817728",\ + "2.195434, 2.195434, 2.195434, 2.195434, 2.195434",\ + "0.107537, 0.107537, 0.107537, 0.107537, 0.107537",\ + "0.140565, 0.140565, 0.140565, 0.140565, 0.140565",\ + "0.189766, 0.189766, 0.189766, 0.189766, 0.189766",\ + "0.817728, 0.817728, 0.817728, 0.817728, 0.817728",\ + "2.195434, 2.195434, 2.195434, 2.195434, 2.195434",\ + "0.107537, 0.107537, 0.107537, 0.107537, 0.107537",\ + "0.140565, 0.140565, 0.140565, 0.140565, 0.140565",\ + "0.189766, 0.189766, 0.189766, 0.189766, 0.189766",\ + "0.817728, 0.817728, 0.817728, 0.817728, 0.817728",\ + "2.195434, 2.195434, 2.195434, 2.195434, 2.195434",\ + "0.107537, 0.107537, 0.107537, 0.107537, 0.107537",\ + "0.140565, 0.140565, 0.140565, 0.140565, 0.140565",\ + "0.189766, 0.189766, 0.189766, 0.189766, 0.189766",\ + "0.817728, 0.817728, 0.817728, 0.817728, 0.817728",\ + "2.195434, 2.195434, 2.195434, 2.195434, 2.195434",\ + "0.107537, 0.107537, 0.107537, 0.107537, 0.107537",\ + "0.140565, 0.140565, 0.140565, 0.140565, 0.140565",\ + "0.189766, 0.189766, 0.189766, 0.189766, 0.189766",\ + "0.817728, 0.817728, 0.817728, 0.817728, 0.817728",\ + "2.195434, 2.195434, 2.195434, 2.195434, 2.195434"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011"); + values ( "0.453509, 0.684488, 0.869368, 1.168461, 1.748415",\ + "0.461309, 0.692287, 0.877167, 1.176260, 1.756214",\ + "0.474728, 0.705707, 0.890586, 1.189680, 1.769634",\ + "0.627462, 0.858441, 1.043320, 1.342414, 1.922367",\ + "0.961447, 1.192425, 1.377305, 1.676398, 2.256352",\ + "0.541888, 0.771806, 0.956649, 1.255766, 1.835768",\ + "0.549688, 0.779605, 0.964448, 1.263565, 1.843568",\ + "0.563107, 0.793025, 0.977867, 1.276985, 1.856987",\ + "0.715841, 0.945758, 1.130601, 1.429719, 2.009721",\ + "1.049826, 1.279743, 1.464586, 1.763703, 2.343705",\ + "0.631467, 0.852136, 1.036675, 1.335794, 1.915800",\ + "0.639266, 0.859936, 1.044475, 1.343594, 1.923599",\ + "0.652686, 0.873355, 1.057894, 1.357013, 1.937019",\ + "0.805420, 1.026089, 1.210628, 1.509747, 2.089752",\ + "1.139404, 1.360074, 1.544613, 1.843732, 2.423737",\ + "0.695451, 0.909966, 1.094386, 1.393248, 1.972863",\ + "0.703251, 0.917766, 1.102185, 1.401047, 1.980663",\ + "0.716670, 0.931185, 1.115605, 1.414467, 1.994082",\ + "0.869404, 1.083919, 1.268338, 1.567201, 2.146816",\ + "1.203389, 1.417904, 1.602323, 1.901185, 2.480801",\ + "1.034004, 1.215273, 1.398043, 1.696439, 2.275143",\ + "1.041804, 1.223073, 1.405843, 1.704239, 2.282942",\ + "1.055223, 1.236492, 1.419262, 1.717658, 2.296362",\ + "1.207957, 1.389226, 1.571996, 1.870392, 2.449096",\ + "1.541942, 1.723211, 1.905981, 2.204377, 2.783080"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011"); + values ( "0.049261, 0.049261, 0.049261, 0.049261, 0.049261",\ + "0.055612, 0.055612, 0.055612, 0.055612, 0.055612",\ + "0.075309, 0.075309, 0.075309, 0.075309, 0.075309",\ + "0.368777, 0.368777, 0.368777, 0.368777, 0.368777",\ + "1.002182, 1.002182, 1.002182, 1.002182, 1.002182",\ + "0.049261, 0.049261, 0.049261, 0.049261, 0.049261",\ + "0.055612, 0.055612, 0.055612, 0.055612, 0.055612",\ + "0.075309, 0.075309, 0.075309, 0.075309, 0.075309",\ + "0.368777, 0.368777, 0.368777, 0.368777, 0.368777",\ + "1.002182, 1.002182, 1.002182, 1.002182, 1.002182",\ + "0.049261, 0.049261, 0.049261, 0.049261, 0.049261",\ + "0.055612, 0.055612, 0.055612, 0.055612, 0.055612",\ + "0.075309, 0.075309, 0.075309, 0.075309, 0.075309",\ + "0.368777, 0.368777, 0.368777, 0.368777, 0.368777",\ + "1.002182, 1.002182, 1.002182, 1.002182, 1.002182",\ + "0.049261, 0.049261, 0.049261, 0.049261, 0.049261",\ + "0.055612, 0.055612, 0.055612, 0.055612, 0.055612",\ + "0.075309, 0.075309, 0.075309, 0.075309, 0.075309",\ + "0.368777, 0.368777, 0.368777, 0.368777, 0.368777",\ + "1.002182, 1.002182, 1.002182, 1.002182, 1.002182",\ + "0.049261, 0.049261, 0.049261, 0.049261, 0.049261",\ + "0.055612, 0.055612, 0.055612, 0.055612, 0.055612",\ + "0.075309, 0.075309, 0.075309, 0.075309, 0.075309",\ + "0.368777, 0.368777, 0.368777, 0.368777, 0.368777",\ + "1.002182, 1.002182, 1.002182, 1.002182, 1.002182"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_min_2400*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[26]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011"); + values ( "0.356883, 0.553789, 0.735718, 1.027079, 1.590482",\ + "0.376149, 0.573056, 0.754984, 1.046346, 1.609749",\ + "0.407828, 0.604733, 0.786661, 1.078023, 1.641427",\ + "0.697481, 0.894382, 1.076308, 1.367671, 1.931077",\ + "1.291425, 1.488327, 1.670252, 1.961614, 2.525021",\ + "0.445232, 0.641107, 0.822999, 1.114385, 1.677836",\ + "0.464498, 0.660374, 0.842265, 1.133651, 1.697102",\ + "0.496176, 0.692052, 0.873942, 1.165328, 1.728780",\ + "0.785829, 0.981701, 1.163589, 1.454976, 2.018430",\ + "1.379774, 1.575645, 1.757533, 2.048919, 2.612374",\ + "0.534400, 0.721441, 0.903025, 1.194413, 1.757867",\ + "0.553666, 0.740707, 0.922292, 1.213680, 1.777134",\ + "0.585345, 0.772385, 0.953969, 1.245357, 1.808812",\ + "0.874998, 1.062034, 1.243616, 1.535004, 2.098462",\ + "1.468942, 1.655978, 1.837560, 2.128948, 2.692406",\ + "0.597862, 0.779261, 0.960728, 1.251846, 1.814890",\ + "0.617128, 0.798528, 0.979995, 1.271113, 1.834156",\ + "0.648807, 0.830206, 1.011672, 1.302790, 1.865834",\ + "0.938459, 1.119855, 1.301319, 1.592437, 2.155484",\ + "1.532403, 1.713799, 1.895263, 2.186381, 2.749428",\ + "0.904924, 1.084513, 1.264385, 1.555021, 2.117120",\ + "0.924190, 1.103779, 1.283652, 1.574288, 2.136386",\ + "0.955869, 1.135457, 1.315329, 1.605965, 2.168064",\ + "1.245522, 1.425106, 1.604976, 1.895612, 2.457714",\ + "1.839466, 2.019050, 2.198920, 2.489556, 3.051658"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011"); + values ( "0.107384, 0.107384, 0.107384, 0.107384, 0.107384",\ + "0.140617, 0.140617, 0.140617, 0.140617, 0.140617",\ + "0.189796, 0.189796, 0.189796, 0.189796, 0.189796",\ + "0.817737, 0.817737, 0.817737, 0.817737, 0.817737",\ + "2.195571, 2.195567, 2.195565, 2.195564, 2.195564",\ + "0.107384, 0.107384, 0.107384, 0.107384, 0.107384",\ + "0.140617, 0.140617, 0.140617, 0.140617, 0.140617",\ + "0.189796, 0.189796, 0.189796, 0.189796, 0.189796",\ + "0.817737, 0.817737, 0.817737, 0.817737, 0.817737",\ + "2.195571, 2.195567, 2.195565, 2.195564, 2.195564",\ + "0.107384, 0.107384, 0.107384, 0.107384, 0.107384",\ + "0.140617, 0.140617, 0.140617, 0.140617, 0.140617",\ + "0.189796, 0.189796, 0.189796, 0.189796, 0.189796",\ + "0.817737, 0.817737, 0.817737, 0.817737, 0.817737",\ + "2.195571, 2.195567, 2.195565, 2.195564, 2.195564",\ + "0.107384, 0.107384, 0.107384, 0.107384, 0.107384",\ + "0.140617, 0.140617, 0.140617, 0.140617, 0.140617",\ + "0.189796, 0.189796, 0.189796, 0.189796, 0.189796",\ + "0.817737, 0.817737, 0.817737, 0.817737, 0.817737",\ + "2.195570, 2.195567, 2.195565, 2.195564, 2.195564",\ + "0.107384, 0.107384, 0.107384, 0.107384, 0.107384",\ + "0.140617, 0.140617, 0.140617, 0.140617, 0.140617",\ + "0.189796, 0.189796, 0.189796, 0.189796, 0.189796",\ + "0.817737, 0.817737, 0.817737, 0.817737, 0.817737",\ + "2.195571, 2.195567, 2.195565, 2.195564, 2.195564"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011"); + values ( "0.367499, 0.564398, 0.746322, 1.037684, 1.601092",\ + "0.375296, 0.572195, 0.754119, 1.045481, 1.608889",\ + "0.388715, 0.585614, 0.767538, 1.058901, 1.622309",\ + "0.541390, 0.738291, 0.920216, 1.211578, 1.774985",\ + "0.875354, 1.072255, 1.254180, 1.545543, 2.108949",\ + "0.455848, 0.651716, 0.833603, 1.124989, 1.688446",\ + "0.463644, 0.659513, 0.841400, 1.132786, 1.696243",\ + "0.477064, 0.672932, 0.854819, 1.146206, 1.709662",\ + "0.629739, 0.825609, 1.007497, 1.298883, 1.862338",\ + "0.963703, 1.159573, 1.341461, 1.632848, 2.196303",\ + "0.545016, 0.732049, 0.913630, 1.205018, 1.768477",\ + "0.552812, 0.739846, 0.921427, 1.212815, 1.776274",\ + "0.566232, 0.753265, 0.934846, 1.226234, 1.789694",\ + "0.718907, 0.905942, 1.087524, 1.378912, 1.942370",\ + "1.052871, 1.239906, 1.421488, 1.712876, 2.276334",\ + "0.608477, 0.789870, 0.971332, 1.262451, 1.825500",\ + "0.616274, 0.797667, 0.979129, 1.270248, 1.833297",\ + "0.629693, 0.811086, 0.992549, 1.283667, 1.846716",\ + "0.782368, 0.963763, 1.145226, 1.436345, 1.999392",\ + "1.116332, 1.297727, 1.479191, 1.770309, 2.333357",\ + "0.915539, 1.095121, 1.274990, 1.565626, 2.127729",\ + "0.923336, 1.102918, 1.282787, 1.573422, 2.135526",\ + "0.936756, 1.116337, 1.296206, 1.586842, 2.148946",\ + "1.089431, 1.269014, 1.448884, 1.739519, 2.301622",\ + "1.423395, 1.602978, 1.782848, 2.073484, 2.635586"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011"); + values ( "0.049251, 0.049251, 0.049251, 0.049251, 0.049251",\ + "0.055579, 0.055579, 0.055579, 0.055579, 0.055579",\ + "0.075314, 0.075314, 0.075314, 0.075314, 0.075314",\ + "0.368762, 0.368762, 0.368762, 0.368762, 0.368762",\ + "1.002200, 1.002200, 1.002200, 1.002200, 1.002201",\ + "0.049251, 0.049251, 0.049251, 0.049251, 0.049251",\ + "0.055579, 0.055579, 0.055579, 0.055579, 0.055579",\ + "0.075314, 0.075314, 0.075314, 0.075314, 0.075314",\ + "0.368762, 0.368762, 0.368762, 0.368762, 0.368762",\ + "1.002200, 1.002200, 1.002200, 1.002200, 1.002201",\ + "0.049251, 0.049251, 0.049251, 0.049251, 0.049251",\ + "0.055579, 0.055579, 0.055579, 0.055579, 0.055579",\ + "0.075314, 0.075314, 0.075314, 0.075314, 0.075314",\ + "0.368762, 0.368762, 0.368762, 0.368762, 0.368762",\ + "1.002200, 1.002200, 1.002200, 1.002200, 1.002201",\ + "0.049251, 0.049251, 0.049251, 0.049251, 0.049251",\ + "0.055579, 0.055579, 0.055579, 0.055579, 0.055579",\ + "0.075314, 0.075314, 0.075314, 0.075314, 0.075314",\ + "0.368762, 0.368762, 0.368762, 0.368762, 0.368762",\ + "1.002200, 1.002200, 1.002200, 1.002200, 1.002201",\ + "0.049251, 0.049251, 0.049251, 0.049251, 0.049251",\ + "0.055579, 0.055579, 0.055579, 0.055579, 0.055579",\ + "0.075314, 0.075314, 0.075314, 0.075314, 0.075314",\ + "0.368762, 0.368762, 0.368762, 0.368762, 0.368762",\ + "1.002200, 1.002200, 1.002200, 1.002200, 1.002201"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_min_2447*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[27]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011"); + values ( "0.379724, 0.609078, 0.793072, 1.086354, 1.652961",\ + "0.399096, 0.628450, 0.812444, 1.105726, 1.672333",\ + "0.430550, 0.659904, 0.843898, 1.137180, 1.703787",\ + "0.719484, 0.948838, 1.132833, 1.426114, 1.992722",\ + "1.313376, 1.542730, 1.726725, 2.020006, 2.586613",\ + "0.468018, 0.696395, 0.880353, 1.173659, 1.740315",\ + "0.487390, 0.715767, 0.899725, 1.193031, 1.759686",\ + "0.518844, 0.747221, 0.931179, 1.224485, 1.791140",\ + "0.807778, 1.036156, 1.220114, 1.513419, 2.080075",\ + "1.401670, 1.630048, 1.814005, 2.107311, 2.673967",\ + "0.557713, 0.776723, 0.960380, 1.253688, 1.820346",\ + "0.577085, 0.796095, 0.979752, 1.273059, 1.839718",\ + "0.608539, 0.827548, 1.011206, 1.304513, 1.871172",\ + "0.897473, 1.116483, 1.300140, 1.593448, 2.160107",\ + "1.491365, 1.710375, 1.894032, 2.187340, 2.753998",\ + "0.621964, 0.834551, 1.018089, 1.311125, 1.877379",\ + "0.641336, 0.853923, 1.037461, 1.330497, 1.896751",\ + "0.672790, 0.885376, 1.068915, 1.361951, 1.928205",\ + "0.961724, 1.174311, 1.357849, 1.650886, 2.217139",\ + "1.555616, 1.768203, 1.951741, 2.244777, 2.811031",\ + "0.960843, 1.139831, 1.321745, 1.614302, 2.179622",\ + "0.980214, 1.159203, 1.341117, 1.633674, 2.198994",\ + "1.011668, 1.190656, 1.372571, 1.665128, 2.230447",\ + "1.300603, 1.479591, 1.661506, 1.954063, 2.519382",\ + "1.894495, 2.073483, 2.255398, 2.547955, 3.113274"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011"); + values ( "0.108154, 0.108154, 0.108154, 0.108154, 0.108154",\ + "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\ + "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\ + "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\ + "2.194880, 2.194880, 2.194880, 2.194880, 2.194880",\ + "0.108154, 0.108154, 0.108154, 0.108154, 0.108154",\ + "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\ + "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\ + "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\ + "2.194880, 2.194880, 2.194880, 2.194880, 2.194880",\ + "0.108154, 0.108154, 0.108154, 0.108154, 0.108154",\ + "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\ + "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\ + "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\ + "2.194880, 2.194880, 2.194880, 2.194880, 2.194880",\ + "0.108154, 0.108154, 0.108154, 0.108154, 0.108154",\ + "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\ + "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\ + "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\ + "2.194880, 2.194880, 2.194880, 2.194880, 2.194880",\ + "0.108154, 0.108154, 0.108154, 0.108154, 0.108154",\ + "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\ + "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\ + "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\ + "2.194880, 2.194880, 2.194880, 2.194880, 2.194880"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011"); + values ( "0.388968, 0.618322, 0.802316, 1.095598, 1.662205",\ + "0.396778, 0.626132, 0.810127, 1.103408, 1.670016",\ + "0.410197, 0.639552, 0.823546, 1.116827, 1.683435",\ + "0.563168, 0.792522, 0.976516, 1.269798, 1.836405",\ + "0.897236, 1.126590, 1.310585, 1.603866, 2.170474",\ + "0.477262, 0.705639, 0.889597, 1.182903, 1.749559",\ + "0.485072, 0.713450, 0.897408, 1.190713, 1.757369",\ + "0.498491, 0.726869, 0.910827, 1.204133, 1.770788",\ + "0.651462, 0.879839, 1.063797, 1.357103, 1.923759",\ + "0.985530, 1.213908, 1.397866, 1.691172, 2.257827",\ + "0.566957, 0.785967, 0.969624, 1.262932, 1.829590",\ + "0.574767, 0.793777, 0.977435, 1.270742, 1.837401",\ + "0.588187, 0.807196, 0.990854, 1.284161, 1.850820",\ + "0.741157, 0.960167, 1.143824, 1.437132, 2.003790",\ + "1.075225, 1.294235, 1.477893, 1.771200, 2.337859",\ + "0.631208, 0.843795, 1.027333, 1.320369, 1.886623",\ + "0.639018, 0.851605, 1.035143, 1.328180, 1.894433",\ + "0.652438, 0.865024, 1.048563, 1.341599, 1.907853",\ + "0.805408, 1.017995, 1.201533, 1.494569, 2.060823",\ + "1.139476, 1.352063, 1.535602, 1.828638, 2.394892",\ + "0.970087, 1.149075, 1.330989, 1.623546, 2.188866",\ + "0.977897, 1.156885, 1.338800, 1.631357, 2.196676",\ + "0.991316, 1.170304, 1.352219, 1.644776, 2.210095",\ + "1.144287, 1.323275, 1.505189, 1.797747, 2.363066",\ + "1.478355, 1.657343, 1.839258, 2.131815, 2.697134"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011"); + values ( "0.046251, 0.046251, 0.046251, 0.046251, 0.046251",\ + "0.051898, 0.051898, 0.051898, 0.051898, 0.051898",\ + "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\ + "0.368839, 0.368839, 0.368839, 0.368839, 0.368839",\ + "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\ + "0.046251, 0.046251, 0.046251, 0.046251, 0.046251",\ + "0.051898, 0.051898, 0.051898, 0.051898, 0.051898",\ + "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\ + "0.368839, 0.368839, 0.368839, 0.368839, 0.368839",\ + "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\ + "0.046251, 0.046251, 0.046251, 0.046251, 0.046251",\ + "0.051898, 0.051898, 0.051898, 0.051898, 0.051898",\ + "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\ + "0.368839, 0.368839, 0.368839, 0.368839, 0.368839",\ + "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\ + "0.046251, 0.046251, 0.046251, 0.046251, 0.046251",\ + "0.051898, 0.051898, 0.051898, 0.051898, 0.051898",\ + "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\ + "0.368839, 0.368839, 0.368839, 0.368839, 0.368839",\ + "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\ + "0.046251, 0.046251, 0.046251, 0.046251, 0.046251",\ + "0.051898, 0.051898, 0.051898, 0.051898, 0.051898",\ + "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\ + "0.368839, 0.368839, 0.368839, 0.368839, 0.368839",\ + "1.000959, 1.000959, 1.000959, 1.000959, 1.000959"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_min_2729*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[30]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.369185, 0.583807, 0.762700, 1.052121, 1.613591",\ + "0.388557, 0.603178, 0.782071, 1.071493, 1.632963",\ + "0.420011, 0.634632, 0.813526, 1.102947, 1.664417",\ + "0.708947, 0.923568, 1.102462, 1.391883, 1.953353",\ + "1.302839, 1.517461, 1.696354, 1.985775, 2.547245",\ + "0.457459, 0.671124, 0.849981, 1.139426, 1.700945",\ + "0.476830, 0.690496, 0.869353, 1.158798, 1.720316",\ + "0.508285, 0.721950, 0.900807, 1.190252, 1.751771",\ + "0.797221, 1.010886, 1.189743, 1.479188, 2.040707",\ + "1.391113, 1.604778, 1.783635, 2.073080, 2.634599",\ + "0.547002, 0.751452, 0.930008, 1.219455, 1.780976",\ + "0.566373, 0.770824, 0.949379, 1.238826, 1.800348",\ + "0.597828, 0.802278, 0.980834, 1.270281, 1.831802",\ + "0.886764, 1.091214, 1.269770, 1.559216, 2.120738",\ + "1.480656, 1.685106, 1.863662, 2.153109, 2.714630",\ + "0.611070, 0.809282, 0.987704, 1.276886, 1.837996",\ + "0.630442, 0.828653, 1.007076, 1.296257, 1.857368",\ + "0.661896, 0.860107, 1.038530, 1.327712, 1.888822",\ + "0.950832, 1.149043, 1.327466, 1.616648, 2.177758",\ + "1.544724, 1.742936, 1.921358, 2.210540, 2.771650",\ + "0.934949, 1.114574, 1.291359, 1.580058, 2.140224",\ + "0.954320, 1.133946, 1.310730, 1.599430, 2.159595",\ + "0.985774, 1.165400, 1.342185, 1.630884, 2.191050",\ + "1.274710, 1.454336, 1.631121, 1.919820, 2.479985",\ + "1.868603, 2.048229, 2.225013, 2.513712, 3.073878"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.108153, 0.108153, 0.108153, 0.108153, 0.108153",\ + "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\ + "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\ + "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\ + "2.194882, 2.194882, 2.194882, 2.194882, 2.194882",\ + "0.108153, 0.108153, 0.108153, 0.108153, 0.108153",\ + "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\ + "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\ + "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\ + "2.194882, 2.194882, 2.194882, 2.194882, 2.194882",\ + "0.108153, 0.108153, 0.108153, 0.108153, 0.108153",\ + "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\ + "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\ + "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\ + "2.194882, 2.194882, 2.194882, 2.194882, 2.194882",\ + "0.108153, 0.108153, 0.108153, 0.108153, 0.108153",\ + "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\ + "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\ + "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\ + "2.194882, 2.194882, 2.194882, 2.194882, 2.194882",\ + "0.108153, 0.108153, 0.108153, 0.108153, 0.108153",\ + "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\ + "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\ + "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\ + "2.194882, 2.194882, 2.194882, 2.194882, 2.194882"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.378431, 0.593053, 0.771946, 1.061368, 1.622838",\ + "0.386242, 0.600863, 0.779757, 1.069178, 1.630648",\ + "0.399661, 0.614283, 0.793176, 1.082597, 1.644067",\ + "0.552631, 0.767253, 0.946146, 1.235567, 1.797037",\ + "0.886699, 1.101321, 1.280214, 1.569635, 2.131105",\ + "0.466705, 0.680371, 0.859227, 1.148673, 1.710191",\ + "0.474516, 0.688181, 0.867038, 1.156483, 1.718002",\ + "0.487935, 0.701600, 0.880457, 1.169902, 1.731421",\ + "0.640905, 0.854570, 1.033427, 1.322872, 1.884391",\ + "0.974973, 1.188638, 1.367495, 1.656940, 2.218459",\ + "0.556248, 0.760699, 0.939254, 1.228701, 1.790223",\ + "0.564059, 0.768509, 0.947065, 1.236512, 1.798033",\ + "0.577478, 0.781928, 0.960484, 1.249931, 1.811453",\ + "0.730448, 0.934898, 1.113454, 1.402901, 1.964422",\ + "1.064516, 1.268966, 1.447522, 1.736969, 2.298491",\ + "0.620317, 0.818528, 0.996951, 1.286133, 1.847243",\ + "0.628127, 0.826339, 1.004761, 1.293943, 1.855053",\ + "0.641546, 0.839758, 1.018181, 1.307362, 1.868473",\ + "0.794516, 0.992728, 1.171150, 1.460332, 2.021443",\ + "1.128584, 1.326796, 1.505219, 1.794400, 2.355511",\ + "0.944195, 1.123821, 1.300605, 1.589304, 2.149470",\ + "0.952006, 1.131631, 1.308416, 1.597115, 2.157280",\ + "0.965425, 1.145051, 1.321835, 1.610534, 2.170700",\ + "1.118395, 1.298021, 1.474805, 1.763504, 2.323670",\ + "1.452463, 1.632089, 1.808873, 2.097572, 2.657738"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.046253, 0.046253, 0.046253, 0.046253, 0.046253",\ + "0.051900, 0.051900, 0.051900, 0.051900, 0.051900",\ + "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\ + "0.368838, 0.368838, 0.368838, 0.368838, 0.368838",\ + "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\ + "0.046253, 0.046253, 0.046253, 0.046253, 0.046253",\ + "0.051900, 0.051900, 0.051900, 0.051900, 0.051900",\ + "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\ + "0.368838, 0.368838, 0.368838, 0.368838, 0.368838",\ + "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\ + "0.046253, 0.046253, 0.046253, 0.046253, 0.046253",\ + "0.051900, 0.051900, 0.051900, 0.051900, 0.051900",\ + "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\ + "0.368838, 0.368838, 0.368838, 0.368838, 0.368838",\ + "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\ + "0.046253, 0.046253, 0.046253, 0.046253, 0.046253",\ + "0.051900, 0.051900, 0.051900, 0.051900, 0.051900",\ + "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\ + "0.368838, 0.368838, 0.368838, 0.368838, 0.368838",\ + "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\ + "0.046253, 0.046253, 0.046253, 0.046253, 0.046253",\ + "0.051900, 0.051900, 0.051900, 0.051900, 0.051900",\ + "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\ + "0.368838, 0.368838, 0.368838, 0.368838, 0.368838",\ + "1.000959, 1.000959, 1.000959, 1.000959, 1.000959"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_min_2349*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[32]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.417064, 0.631505, 0.810363, 1.099808, 1.661366",\ + "0.436351, 0.650792, 0.829650, 1.119095, 1.680653",\ + "0.467985, 0.682426, 0.861284, 1.150729, 1.712287",\ + "0.757495, 0.971936, 1.150794, 1.440239, 2.001797",\ + "1.351429, 1.565870, 1.744728, 2.034173, 2.595731",\ + "0.505338, 0.718823, 0.897644, 1.187113, 1.748719",\ + "0.524625, 0.738110, 0.916931, 1.206400, 1.768006",\ + "0.556259, 0.769744, 0.948565, 1.238034, 1.799640",\ + "0.845769, 1.059254, 1.238075, 1.527544, 2.089150",\ + "1.439703, 1.653188, 1.832009, 2.121478, 2.683084",\ + "0.594882, 0.799151, 0.977671, 1.267141, 1.828751",\ + "0.614169, 0.818438, 0.996958, 1.286428, 1.848038",\ + "0.645804, 0.850072, 1.028592, 1.318063, 1.879672",\ + "0.935313, 1.139582, 1.318102, 1.607573, 2.169182",\ + "1.529247, 1.733516, 1.912036, 2.201506, 2.763116",\ + "0.658952, 0.856980, 1.035367, 1.324573, 1.885771",\ + "0.678239, 0.876267, 1.054654, 1.343860, 1.905058",\ + "0.709873, 0.907901, 1.086289, 1.375494, 1.936692",\ + "0.999383, 1.197411, 1.375799, 1.665004, 2.226202",\ + "1.593317, 1.791345, 1.969732, 2.258938, 2.820136",\ + "0.982644, 1.162273, 1.339022, 1.627745, 2.187998",\ + "1.001931, 1.181560, 1.358309, 1.647032, 2.207285",\ + "1.033565, 1.213194, 1.389943, 1.678666, 2.238919",\ + "1.323075, 1.502704, 1.679453, 1.968176, 2.528430",\ + "1.917009, 2.096638, 2.273387, 2.562110, 3.122364"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.107537, 0.107537, 0.107537, 0.107537, 0.107537",\ + "0.140565, 0.140565, 0.140565, 0.140565, 0.140565",\ + "0.189766, 0.189766, 0.189766, 0.189766, 0.189766",\ + "0.817728, 0.817728, 0.817728, 0.817728, 0.817728",\ + "2.195434, 2.195434, 2.195434, 2.195434, 2.195434",\ + "0.107537, 0.107537, 0.107537, 0.107537, 0.107537",\ + "0.140565, 0.140565, 0.140565, 0.140565, 0.140565",\ + "0.189766, 0.189766, 0.189766, 0.189766, 0.189766",\ + "0.817728, 0.817728, 0.817728, 0.817728, 0.817728",\ + "2.195434, 2.195434, 2.195434, 2.195434, 2.195434",\ + "0.107537, 0.107537, 0.107537, 0.107537, 0.107537",\ + "0.140565, 0.140565, 0.140565, 0.140565, 0.140565",\ + "0.189766, 0.189766, 0.189766, 0.189766, 0.189766",\ + "0.817728, 0.817728, 0.817728, 0.817728, 0.817728",\ + "2.195434, 2.195434, 2.195434, 2.195434, 2.195434",\ + "0.107537, 0.107537, 0.107537, 0.107537, 0.107537",\ + "0.140565, 0.140565, 0.140565, 0.140565, 0.140565",\ + "0.189766, 0.189766, 0.189766, 0.189766, 0.189766",\ + "0.817728, 0.817728, 0.817728, 0.817728, 0.817728",\ + "2.195434, 2.195434, 2.195434, 2.195434, 2.195434",\ + "0.107537, 0.107537, 0.107537, 0.107537, 0.107537",\ + "0.140565, 0.140565, 0.140565, 0.140565, 0.140565",\ + "0.189766, 0.189766, 0.189766, 0.189766, 0.189766",\ + "0.817728, 0.817728, 0.817728, 0.817728, 0.817728",\ + "2.195434, 2.195434, 2.195434, 2.195434, 2.195434"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.427407, 0.641848, 0.820706, 1.110151, 1.671709",\ + "0.435207, 0.649648, 0.828505, 1.117950, 1.679508",\ + "0.448626, 0.663067, 0.841925, 1.131369, 1.692927",\ + "0.601360, 0.815801, 0.994659, 1.284103, 1.845661",\ + "0.935344, 1.149785, 1.328643, 1.618088, 2.179646",\ + "0.515681, 0.729166, 0.907987, 1.197456, 1.759062",\ + "0.523481, 0.736965, 0.915786, 1.205255, 1.766862",\ + "0.536900, 0.750385, 0.929206, 1.218675, 1.780281",\ + "0.689634, 0.903118, 1.081940, 1.371408, 1.933015",\ + "1.023618, 1.237103, 1.415924, 1.705393, 2.266999",\ + "0.605225, 0.809494, 0.988014, 1.277484, 1.839094",\ + "0.613025, 0.817293, 0.995813, 1.285284, 1.846893",\ + "0.626444, 0.830712, 1.009233, 1.298703, 1.860313",\ + "0.779178, 0.983446, 1.161967, 1.451437, 2.013046",\ + "1.113163, 1.317431, 1.495951, 1.785421, 2.347031",\ + "0.669295, 0.867323, 1.045710, 1.334916, 1.896114",\ + "0.677094, 0.875123, 1.053510, 1.342715, 1.903913",\ + "0.690513, 0.888542, 1.066929, 1.356135, 1.917333",\ + "0.843247, 1.041276, 1.219663, 1.508868, 2.070067",\ + "1.177232, 1.375260, 1.553648, 1.842853, 2.404051",\ + "0.992987, 1.172616, 1.349365, 1.638088, 2.198341",\ + "1.000786, 1.180416, 1.357164, 1.645887, 2.206141",\ + "1.014206, 1.193835, 1.370584, 1.659307, 2.219560",\ + "1.166939, 1.346569, 1.523317, 1.812040, 2.372294",\ + "1.500924, 1.680553, 1.857302, 2.146025, 2.706279"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.049261, 0.049261, 0.049261, 0.049261, 0.049261",\ + "0.055612, 0.055612, 0.055612, 0.055612, 0.055612",\ + "0.075309, 0.075309, 0.075309, 0.075309, 0.075309",\ + "0.368777, 0.368777, 0.368777, 0.368777, 0.368777",\ + "1.002182, 1.002182, 1.002182, 1.002182, 1.002182",\ + "0.049261, 0.049261, 0.049261, 0.049261, 0.049261",\ + "0.055612, 0.055612, 0.055612, 0.055612, 0.055612",\ + "0.075309, 0.075309, 0.075309, 0.075309, 0.075309",\ + "0.368777, 0.368777, 0.368777, 0.368777, 0.368777",\ + "1.002182, 1.002182, 1.002182, 1.002182, 1.002182",\ + "0.049261, 0.049261, 0.049261, 0.049261, 0.049261",\ + "0.055612, 0.055612, 0.055612, 0.055612, 0.055612",\ + "0.075309, 0.075309, 0.075309, 0.075309, 0.075309",\ + "0.368777, 0.368777, 0.368777, 0.368777, 0.368777",\ + "1.002182, 1.002182, 1.002182, 1.002182, 1.002182",\ + "0.049261, 0.049261, 0.049261, 0.049261, 0.049261",\ + "0.055612, 0.055612, 0.055612, 0.055612, 0.055612",\ + "0.075309, 0.075309, 0.075309, 0.075309, 0.075309",\ + "0.368777, 0.368777, 0.368777, 0.368777, 0.368777",\ + "1.002182, 1.002182, 1.002182, 1.002182, 1.002182",\ + "0.049261, 0.049261, 0.049261, 0.049261, 0.049261",\ + "0.055612, 0.055612, 0.055612, 0.055612, 0.055612",\ + "0.075309, 0.075309, 0.075309, 0.075309, 0.075309",\ + "0.368777, 0.368777, 0.368777, 0.368777, 0.368777",\ + "1.002182, 1.002182, 1.002182, 1.002182, 1.002182"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_min_2494*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[33]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.423145, 0.655225, 0.838651, 1.132010, 1.699224",\ + "0.442432, 0.674512, 0.857938, 1.151296, 1.718511",\ + "0.474066, 0.706146, 0.889572, 1.182931, 1.750145",\ + "0.763577, 0.995656, 1.179082, 1.472441, 2.039655",\ + "1.357510, 1.589590, 1.773016, 2.066375, 2.633589",\ + "0.511451, 0.742543, 0.925932, 1.219315, 1.786577",\ + "0.530738, 0.761829, 0.945219, 1.238602, 1.805864",\ + "0.562372, 0.793464, 0.976853, 1.270236, 1.837498",\ + "0.851883, 1.082974, 1.266363, 1.559746, 2.127008",\ + "1.445816, 1.676908, 1.860297, 2.153680, 2.720942",\ + "0.600820, 0.822873, 1.005959, 1.299343, 1.866609",\ + "0.620107, 0.842160, 1.025246, 1.318630, 1.885896",\ + "0.651741, 0.873794, 1.056880, 1.350264, 1.917530",\ + "0.941251, 1.163304, 1.346390, 1.639775, 2.207040",\ + "1.535185, 1.757238, 1.940324, 2.233708, 2.800974",\ + "0.664609, 0.880707, 1.063666, 1.356781, 1.923642",\ + "0.683896, 0.899994, 1.082952, 1.376068, 1.942929",\ + "0.715530, 0.931628, 1.114587, 1.407702, 1.974563",\ + "1.005041, 1.221138, 1.404097, 1.697213, 2.264073",\ + "1.598974, 1.815072, 1.998031, 2.291147, 2.858007",\ + "1.001916, 1.186040, 1.367322, 1.659959, 2.225884",\ + "1.021203, 1.205327, 1.386609, 1.679246, 2.245171",\ + "1.052837, 1.236961, 1.418243, 1.710881, 2.276805",\ + "1.342347, 1.526471, 1.707754, 2.000391, 2.566315",\ + "1.936281, 2.120405, 2.301688, 2.594325, 3.160249"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.107537, 0.107537, 0.107537, 0.107537, 0.107537",\ + "0.140565, 0.140565, 0.140565, 0.140565, 0.140565",\ + "0.189766, 0.189766, 0.189766, 0.189766, 0.189766",\ + "0.817728, 0.817728, 0.817728, 0.817728, 0.817728",\ + "2.195434, 2.195434, 2.195434, 2.195434, 2.195434",\ + "0.107537, 0.107537, 0.107537, 0.107537, 0.107537",\ + "0.140565, 0.140565, 0.140565, 0.140565, 0.140565",\ + "0.189766, 0.189766, 0.189766, 0.189766, 0.189766",\ + "0.817728, 0.817728, 0.817728, 0.817728, 0.817728",\ + "2.195434, 2.195434, 2.195434, 2.195434, 2.195434",\ + "0.107537, 0.107537, 0.107537, 0.107537, 0.107537",\ + "0.140565, 0.140565, 0.140565, 0.140565, 0.140565",\ + "0.189766, 0.189766, 0.189766, 0.189766, 0.189766",\ + "0.817728, 0.817728, 0.817728, 0.817728, 0.817728",\ + "2.195434, 2.195434, 2.195434, 2.195434, 2.195434",\ + "0.107537, 0.107537, 0.107537, 0.107537, 0.107537",\ + "0.140565, 0.140565, 0.140565, 0.140565, 0.140565",\ + "0.189766, 0.189766, 0.189766, 0.189766, 0.189766",\ + "0.817728, 0.817728, 0.817728, 0.817728, 0.817728",\ + "2.195434, 2.195434, 2.195434, 2.195434, 2.195434",\ + "0.107537, 0.107537, 0.107537, 0.107537, 0.107537",\ + "0.140565, 0.140565, 0.140565, 0.140565, 0.140565",\ + "0.189766, 0.189766, 0.189766, 0.189766, 0.189766",\ + "0.817728, 0.817728, 0.817728, 0.817728, 0.817728",\ + "2.195434, 2.195434, 2.195434, 2.195434, 2.195434"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.433489, 0.665568, 0.848994, 1.142353, 1.709567",\ + "0.441288, 0.673367, 0.856794, 1.150152, 1.717367",\ + "0.454707, 0.686787, 0.870213, 1.163572, 1.730786",\ + "0.607441, 0.839521, 1.022947, 1.316305, 1.883520",\ + "0.941426, 1.173505, 1.356931, 1.650290, 2.217504",\ + "0.521794, 0.752886, 0.936275, 1.229658, 1.796920",\ + "0.529594, 0.760685, 0.944075, 1.237458, 1.804720",\ + "0.543013, 0.774105, 0.957494, 1.250877, 1.818139",\ + "0.695747, 0.926838, 1.110228, 1.403611, 1.970873",\ + "1.029732, 1.260823, 1.444212, 1.737595, 2.304857",\ + "0.611163, 0.833216, 1.016302, 1.309687, 1.876952",\ + "0.618962, 0.841016, 1.024101, 1.317486, 1.884752",\ + "0.632382, 0.854435, 1.037521, 1.330905, 1.898171",\ + "0.785116, 1.007169, 1.190255, 1.483639, 2.050905",\ + "1.119100, 1.341153, 1.524239, 1.817624, 2.384889",\ + "0.674952, 0.891050, 1.074009, 1.367125, 1.933985",\ + "0.682752, 0.898850, 1.081808, 1.374924, 1.941785",\ + "0.696171, 0.912269, 1.095228, 1.388343, 1.955204",\ + "0.848905, 1.065003, 1.247962, 1.541077, 2.107938",\ + "1.182890, 1.398987, 1.581946, 1.875062, 2.441922",\ + "1.012259, 1.196383, 1.377666, 1.670303, 2.236228",\ + "1.020059, 1.204182, 1.385465, 1.678102, 2.244027",\ + "1.033478, 1.217602, 1.398885, 1.691522, 2.257446",\ + "1.186212, 1.370336, 1.551618, 1.844255, 2.410180",\ + "1.520197, 1.704320, 1.885603, 2.178240, 2.744164"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.049261, 0.049261, 0.049261, 0.049261, 0.049261",\ + "0.055612, 0.055612, 0.055612, 0.055612, 0.055612",\ + "0.075309, 0.075309, 0.075309, 0.075309, 0.075309",\ + "0.368777, 0.368777, 0.368777, 0.368777, 0.368777",\ + "1.002182, 1.002182, 1.002182, 1.002182, 1.002182",\ + "0.049261, 0.049261, 0.049261, 0.049261, 0.049261",\ + "0.055612, 0.055612, 0.055612, 0.055612, 0.055612",\ + "0.075309, 0.075309, 0.075309, 0.075309, 0.075309",\ + "0.368777, 0.368777, 0.368777, 0.368777, 0.368777",\ + "1.002182, 1.002182, 1.002182, 1.002182, 1.002182",\ + "0.049261, 0.049261, 0.049261, 0.049261, 0.049261",\ + "0.055612, 0.055612, 0.055612, 0.055612, 0.055612",\ + "0.075309, 0.075309, 0.075309, 0.075309, 0.075309",\ + "0.368777, 0.368777, 0.368777, 0.368777, 0.368777",\ + "1.002182, 1.002182, 1.002182, 1.002182, 1.002182",\ + "0.049261, 0.049261, 0.049261, 0.049261, 0.049261",\ + "0.055612, 0.055612, 0.055612, 0.055612, 0.055612",\ + "0.075309, 0.075309, 0.075309, 0.075309, 0.075309",\ + "0.368777, 0.368777, 0.368777, 0.368777, 0.368777",\ + "1.002182, 1.002182, 1.002182, 1.002182, 1.002182",\ + "0.049261, 0.049261, 0.049261, 0.049261, 0.049261",\ + "0.055612, 0.055612, 0.055612, 0.055612, 0.055612",\ + "0.075309, 0.075309, 0.075309, 0.075309, 0.075309",\ + "0.368777, 0.368777, 0.368777, 0.368777, 0.368777",\ + "1.002182, 1.002182, 1.002182, 1.002182, 1.002182"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_min_2512*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[37]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.181258, 0.362750, 0.559584, 0.877059, 1.491654",\ + "0.196091, 0.377154, 0.575199, 0.895881, 1.517263",\ + "0.221299, 0.401436, 0.600771, 0.925894, 1.556997",\ + "0.494050, 0.669272, 0.865120, 1.207435, 1.883536",\ + "1.086888, 1.260498, 1.453339, 1.802428, 2.497703",\ + "0.268666, 0.450068, 0.646865, 0.964364, 1.579007",\ + "0.283499, 0.464472, 0.662480, 0.983186, 1.604617",\ + "0.308707, 0.488754, 0.688052, 1.013199, 1.644350",\ + "0.581459, 0.756590, 0.952401, 1.294740, 1.970890",\ + "1.174296, 1.347816, 1.540620, 1.889733, 2.585056",\ + "0.349534, 0.530400, 0.726892, 1.044393, 1.659039",\ + "0.364365, 0.544804, 0.742507, 1.063215, 1.684648",\ + "0.389566, 0.569086, 0.768079, 1.093227, 1.724382",\ + "0.662286, 0.836922, 1.032428, 1.374768, 2.050921",\ + "1.255114, 1.428148, 1.620646, 1.969761, 2.665088",\ + "0.407230, 0.588238, 0.784630, 1.101888, 1.716185",\ + "0.422055, 0.602641, 0.800248, 1.120718, 1.741811",\ + "0.447245, 0.626919, 0.825823, 1.150743, 1.781568",\ + "0.719903, 0.894737, 1.090165, 1.432339, 2.108216",\ + "1.312710, 1.485957, 1.678376, 2.027355, 2.722429",\ + "0.710204, 0.893608, 1.088293, 1.405116, 2.018565",\ + "0.724980, 0.907999, 1.103911, 1.423953, 2.044210",\ + "0.750065, 0.932253, 1.129487, 1.453987, 2.083996",\ + "1.022164, 1.199940, 1.393827, 1.735630, 2.410775",\ + "1.614788, 1.791118, 1.982037, 2.330666, 3.025044"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.126844, 0.127605, 0.133435, 0.151631, 0.191178",\ + "0.149772, 0.150309, 0.154650, 0.170542, 0.205735",\ + "0.195024, 0.195582, 0.198470, 0.210618, 0.237900",\ + "0.816153, 0.816255, 0.816260, 0.817805, 0.821592",\ + "2.194128, 2.194405, 2.194418, 2.195894, 2.199512",\ + "0.126844, 0.127605, 0.133435, 0.151631, 0.191178",\ + "0.149772, 0.150309, 0.154650, 0.170542, 0.205735",\ + "0.195024, 0.195582, 0.198470, 0.210618, 0.237900",\ + "0.816153, 0.816255, 0.816260, 0.817805, 0.821592",\ + "2.194128, 2.194405, 2.194418, 2.195894, 2.199512",\ + "0.126849, 0.127605, 0.133435, 0.151631, 0.191178",\ + "0.149775, 0.150309, 0.154650, 0.170542, 0.205735",\ + "0.195028, 0.195582, 0.198470, 0.210618, 0.237900",\ + "0.816153, 0.816255, 0.816260, 0.817805, 0.821592",\ + "2.194129, 2.194405, 2.194418, 2.195894, 2.199512",\ + "0.126859, 0.127607, 0.133449, 0.151680, 0.191274",\ + "0.149782, 0.150311, 0.154660, 0.170585, 0.205820",\ + "0.195035, 0.195584, 0.198477, 0.210651, 0.237965",\ + "0.816155, 0.816256, 0.816260, 0.817810, 0.821601",\ + "2.194133, 2.194406, 2.194418, 2.195898, 2.199521",\ + "0.126945, 0.127627, 0.133451, 0.151721, 0.191389",\ + "0.149843, 0.150326, 0.154662, 0.170622, 0.205922",\ + "0.195098, 0.195599, 0.198478, 0.210679, 0.238045",\ + "0.816166, 0.816259, 0.816260, 0.817813, 0.821612",\ + "2.194165, 2.194413, 2.194418, 2.195902, 2.199532"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.117102, 0.379947, 0.573156, 0.882174, 1.479232",\ + "0.126091, 0.389068, 0.582472, 0.892519, 1.491929",\ + "0.141699, 0.404157, 0.597820, 0.909153, 1.511489",\ + "0.306945, 0.562483, 0.755606, 1.068523, 1.675209",\ + "0.649757, 0.897030, 1.089718, 1.401787, 2.006775",\ + "0.205481, 0.467265, 0.660437, 0.969479, 1.566586",\ + "0.214473, 0.476386, 0.669753, 0.979824, 1.579283",\ + "0.230076, 0.491475, 0.685100, 0.996458, 1.598842",\ + "0.395245, 0.649801, 0.842887, 1.155828, 1.762562",\ + "0.738017, 0.984348, 1.176999, 1.489092, 2.094129",\ + "0.294834, 0.547598, 0.740463, 1.049507, 1.646617",\ + "0.303840, 0.556719, 0.749780, 1.059852, 1.659314",\ + "0.319425, 0.571807, 0.765127, 1.076486, 1.678874",\ + "0.484368, 0.730134, 0.922914, 1.235856, 1.842594",\ + "0.827025, 1.064680, 1.257025, 1.569121, 2.174160",\ + "0.358511, 0.605438, 0.798193, 1.106982, 1.703722",\ + "0.367529, 0.614560, 0.807510, 1.117329, 1.716424",\ + "0.383098, 0.629648, 0.822858, 1.133967, 1.735991",\ + "0.547830, 0.787974, 0.980643, 1.293342, 1.899721",\ + "0.890379, 1.122520, 1.314754, 1.626604, 2.231284",\ + "0.695115, 0.910825, 1.101854, 1.410191, 2.006050",\ + "0.704209, 0.919948, 1.111171, 1.420541, 2.018759",\ + "0.719674, 0.935035, 1.126519, 1.437182, 2.038335",\ + "0.883062, 1.093358, 1.284304, 1.596561, 2.202077",\ + "1.224926, 1.427904, 1.618415, 1.929822, 2.533635"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.044794, 0.049393, 0.054601, 0.068665, 0.098782",\ + "0.053408, 0.055750, 0.059102, 0.072238, 0.101610",\ + "0.075784, 0.075784, 0.077996, 0.088605, 0.112682",\ + "0.368045, 0.368045, 0.368833, 0.370655, 0.374434",\ + "1.001402, 1.001402, 1.001776, 1.002637, 1.004422",\ + "0.044917, 0.049393, 0.054601, 0.068665, 0.098782",\ + "0.053471, 0.055750, 0.059102, 0.072238, 0.101610",\ + "0.075784, 0.075784, 0.077996, 0.088605, 0.112682",\ + "0.368045, 0.368045, 0.368833, 0.370655, 0.374434",\ + "1.001402, 1.001402, 1.001776, 1.002637, 1.004422",\ + "0.045280, 0.049393, 0.054601, 0.068665, 0.098782",\ + "0.053656, 0.055750, 0.059102, 0.072238, 0.101610",\ + "0.075784, 0.075784, 0.077996, 0.088605, 0.112682",\ + "0.368045, 0.368045, 0.368833, 0.370655, 0.374434",\ + "1.001402, 1.001402, 1.001776, 1.002637, 1.004422",\ + "0.045619, 0.049410, 0.054613, 0.068702, 0.098855",\ + "0.053828, 0.055759, 0.059110, 0.072274, 0.101681",\ + "0.075784, 0.075784, 0.078001, 0.088634, 0.112740",\ + "0.368045, 0.368045, 0.368835, 0.370660, 0.374443",\ + "1.001402, 1.001402, 1.001777, 1.002639, 1.004426",\ + "0.047777, 0.049532, 0.054615, 0.068733, 0.098943",\ + "0.054927, 0.055821, 0.059111, 0.072304, 0.101766",\ + "0.075784, 0.075784, 0.078002, 0.088659, 0.112810",\ + "0.368045, 0.368045, 0.368835, 0.370664, 0.374454",\ + "1.001402, 1.001402, 1.001777, 1.002641, 1.004432"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_min_2747*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[40]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.496413, 0.709649, 0.894786, 1.185670, 1.745053",\ + "0.515784, 0.729021, 0.914158, 1.205042, 1.764425",\ + "0.547238, 0.760475, 0.945612, 1.236496, 1.795879",\ + "0.836174, 1.049411, 1.234548, 1.525432, 2.084815",\ + "1.430066, 1.643303, 1.828440, 2.119324, 2.678707",\ + "0.584781, 0.796968, 0.982067, 1.272975, 1.832407",\ + "0.604153, 0.816339, 1.001439, 1.292347, 1.851778",\ + "0.635607, 0.847793, 1.032893, 1.323801, 1.883232",\ + "0.924543, 1.136729, 1.321829, 1.612737, 2.172168",\ + "1.518435, 1.730622, 1.915721, 2.206629, 2.766061",\ + "0.673752, 0.877303, 1.062094, 1.353004, 1.912438",\ + "0.693124, 0.896674, 1.081466, 1.372375, 1.931810",\ + "0.724578, 0.928128, 1.112920, 1.403829, 1.963264",\ + "1.013514, 1.217064, 1.401856, 1.692765, 2.252200",\ + "1.607406, 1.810957, 1.995748, 2.286657, 2.846092",\ + "0.736919, 0.935130, 1.119804, 1.410431, 1.969450",\ + "0.756291, 0.954502, 1.139176, 1.429803, 1.988822",\ + "0.787745, 0.985956, 1.170630, 1.461257, 2.020276",\ + "1.076681, 1.274892, 1.459566, 1.750193, 2.309212",\ + "1.670573, 1.868784, 2.053458, 2.344085, 2.903104",\ + "1.058360, 1.240438, 1.423463, 1.713602, 2.271667",\ + "1.077731, 1.259810, 1.442835, 1.732974, 2.291038",\ + "1.109185, 1.291264, 1.474289, 1.764428, 2.322492",\ + "1.398121, 1.580200, 1.763225, 2.053364, 2.611428",\ + "1.992013, 2.174092, 2.357117, 2.647256, 3.205320"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.108153, 0.108153, 0.108153, 0.108153, 0.108153",\ + "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\ + "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\ + "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\ + "2.194882, 2.194882, 2.194882, 2.194882, 2.194882",\ + "0.108153, 0.108153, 0.108153, 0.108153, 0.108153",\ + "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\ + "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\ + "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\ + "2.194882, 2.194882, 2.194882, 2.194882, 2.194882",\ + "0.108153, 0.108153, 0.108153, 0.108153, 0.108153",\ + "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\ + "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\ + "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\ + "2.194882, 2.194882, 2.194882, 2.194882, 2.194882",\ + "0.108153, 0.108153, 0.108153, 0.108153, 0.108153",\ + "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\ + "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\ + "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\ + "2.194882, 2.194882, 2.194882, 2.194882, 2.194882",\ + "0.108153, 0.108153, 0.108153, 0.108153, 0.108153",\ + "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\ + "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\ + "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\ + "2.194882, 2.194882, 2.194882, 2.194882, 2.194882"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.505659, 0.718896, 0.904033, 1.194916, 1.754300",\ + "0.513469, 0.726706, 0.911843, 1.202727, 1.762110",\ + "0.526889, 0.740125, 0.925263, 1.216146, 1.775529",\ + "0.679859, 0.893095, 1.078233, 1.369116, 1.928499",\ + "1.013927, 1.227163, 1.412301, 1.703184, 2.262567",\ + "0.594028, 0.806214, 0.991314, 1.282222, 1.841653",\ + "0.601838, 0.814024, 0.999124, 1.290032, 1.849463",\ + "0.615257, 0.827444, 1.012543, 1.303451, 1.862883",\ + "0.768227, 0.980414, 1.165513, 1.456421, 2.015853",\ + "1.102295, 1.314482, 1.499582, 1.790489, 2.349921",\ + "0.682999, 0.886549, 1.071341, 1.362250, 1.921685",\ + "0.690809, 0.894360, 1.079151, 1.370060, 1.929495",\ + "0.704229, 0.907779, 1.092570, 1.383480, 1.942914",\ + "0.857199, 1.060749, 1.245540, 1.536450, 2.095884",\ + "1.191267, 1.394817, 1.579608, 1.870518, 2.429952",\ + "0.746166, 0.944377, 1.129050, 1.419678, 1.978696",\ + "0.753976, 0.952187, 1.136861, 1.427488, 1.986507",\ + "0.767395, 0.965607, 1.150280, 1.440908, 1.999926",\ + "0.920365, 1.118577, 1.303250, 1.593878, 2.152896",\ + "1.254433, 1.452645, 1.637318, 1.927946, 2.486964",\ + "1.067606, 1.249685, 1.432710, 1.722849, 2.280913",\ + "1.075416, 1.257495, 1.440520, 1.730659, 2.288723",\ + "1.088836, 1.270914, 1.453939, 1.744078, 2.302143",\ + "1.241806, 1.423884, 1.606909, 1.897048, 2.455113",\ + "1.575874, 1.757952, 1.940977, 2.231116, 2.789181"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.046252, 0.046252, 0.046252, 0.046252, 0.046252",\ + "0.051899, 0.051899, 0.051899, 0.051899, 0.051899",\ + "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\ + "0.368838, 0.368838, 0.368838, 0.368838, 0.368838",\ + "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\ + "0.046252, 0.046252, 0.046252, 0.046252, 0.046252",\ + "0.051899, 0.051899, 0.051899, 0.051899, 0.051899",\ + "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\ + "0.368838, 0.368838, 0.368838, 0.368838, 0.368838",\ + "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\ + "0.046252, 0.046252, 0.046252, 0.046252, 0.046252",\ + "0.051899, 0.051899, 0.051899, 0.051899, 0.051899",\ + "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\ + "0.368838, 0.368838, 0.368838, 0.368838, 0.368838",\ + "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\ + "0.046252, 0.046252, 0.046252, 0.046252, 0.046252",\ + "0.051899, 0.051899, 0.051899, 0.051899, 0.051899",\ + "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\ + "0.368838, 0.368838, 0.368838, 0.368838, 0.368838",\ + "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\ + "0.046252, 0.046252, 0.046252, 0.046252, 0.046252",\ + "0.051899, 0.051899, 0.051899, 0.051899, 0.051899",\ + "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\ + "0.368838, 0.368838, 0.368838, 0.368838, 0.368838",\ + "1.000959, 1.000959, 1.000959, 1.000959, 1.000959"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_min_2380*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[44]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011"); + values ( "0.099932, 0.259054, 0.413318, 0.663965, 1.151026",\ + "0.112861, 0.280635, 0.445926, 0.710841, 1.223619",\ + "0.139635, 0.312455, 0.491350, 0.774619, 1.320764",\ + "0.427093, 0.638536, 0.826241, 1.153952, 1.801309",\ + "1.022612, 1.250759, 1.440120, 1.765390, 2.405472",\ + "0.187338, 0.346372, 0.500599, 0.751271, 1.238380",\ + "0.200267, 0.367953, 0.533207, 0.798146, 1.310972",\ + "0.227041, 0.399773, 0.578631, 0.861924, 1.408118",\ + "0.515372, 0.725854, 0.913522, 1.241257, 1.888662",\ + "1.110934, 1.338077, 1.527401, 1.852695, 2.492826",\ + "0.268065, 0.426703, 0.580626, 0.831299, 1.318411",\ + "0.281048, 0.448284, 0.613234, 0.878174, 1.391004",\ + "0.307853, 0.480104, 0.658657, 0.941953, 1.488149",\ + "0.604596, 0.806184, 0.993549, 1.321285, 1.968694",\ + "1.200284, 1.418408, 1.607428, 1.932723, 2.572857",\ + "0.325504, 0.484459, 0.638266, 0.888640, 1.375251",\ + "0.338594, 0.506071, 0.670899, 0.935546, 1.447905",\ + "0.365461, 0.537910, 0.716354, 0.999365, 1.545131",\ + "0.668221, 0.863995, 1.051266, 1.378821, 2.025920",\ + "1.264029, 1.476232, 1.665149, 1.990250, 2.630066",\ + "0.626239, 0.789242, 0.941912, 1.191734, 1.677259",\ + "0.640305, 0.811082, 0.974549, 1.238668, 1.749989",\ + "0.667742, 0.843054, 1.020009, 1.302522, 1.847312",\ + "0.992829, 1.169169, 1.354925, 1.682082, 2.328396",\ + "1.601053, 1.781498, 1.968808, 2.293504, 2.932521"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011"); + values ( "0.028418, 0.053985, 0.061562, 0.076171, 0.106327",\ + "0.053853, 0.080619, 0.084946, 0.098515, 0.128974",\ + "0.117398, 0.123775, 0.136709, 0.151501, 0.176771",\ + "0.813025, 0.813025, 0.813025, 0.814975, 0.819748",\ + "2.191540, 2.192948, 2.194009, 2.200710, 2.216247",\ + "0.028418, 0.053985, 0.061562, 0.076171, 0.106327",\ + "0.053853, 0.080619, 0.084946, 0.098515, 0.128974",\ + "0.117398, 0.123775, 0.136709, 0.151501, 0.176771",\ + "0.813025, 0.813025, 0.813025, 0.814975, 0.819748",\ + "2.191577, 2.192948, 2.194009, 2.200710, 2.216247",\ + "0.028577, 0.053985, 0.061562, 0.076171, 0.106327",\ + "0.054019, 0.080619, 0.084946, 0.098515, 0.128974",\ + "0.117437, 0.123775, 0.136709, 0.151501, 0.176771",\ + "0.813025, 0.813025, 0.813025, 0.814975, 0.819748",\ + "2.191688, 2.192948, 2.194009, 2.200710, 2.216247",\ + "0.028892, 0.054081, 0.061577, 0.076207, 0.106399",\ + "0.054349, 0.080719, 0.084954, 0.098552, 0.129047",\ + "0.117516, 0.123799, 0.136740, 0.151532, 0.176832",\ + "0.813025, 0.813025, 0.813025, 0.814981, 0.819759",\ + "2.191792, 2.192953, 2.194012, 2.200729, 2.216285",\ + "0.031778, 0.054753, 0.061580, 0.076239, 0.106487",\ + "0.057369, 0.081423, 0.084955, 0.098584, 0.129136",\ + "0.118236, 0.123966, 0.136744, 0.151558, 0.176905",\ + "0.813025, 0.813025, 0.813025, 0.814986, 0.819773",\ + "2.192455, 2.192990, 2.194012, 2.200745, 2.216330"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011"); + values ( "0.071387, 0.284408, 0.492606, 0.801306, 1.367433",\ + "0.077667, 0.305792, 0.517732, 0.814342, 1.385042",\ + "0.090238, 0.334877, 0.530841, 0.830649, 1.407555",\ + "0.256635, 0.477338, 0.671832, 0.978257, 1.567975",\ + "0.595228, 0.802461, 0.996271, 1.304460, 1.898944",\ + "0.158934, 0.371732, 0.579823, 0.888611, 1.454786",\ + "0.165476, 0.393159, 0.605013, 0.901647, 1.472395",\ + "0.178302, 0.422304, 0.618122, 0.917954, 1.494908",\ + "0.344810, 0.564656, 0.759113, 1.065562, 1.655329",\ + "0.683378, 0.889779, 1.083552, 1.391765, 1.986297",\ + "0.245972, 0.460189, 0.667780, 0.968640, 1.534818",\ + "0.253296, 0.481714, 0.685040, 0.981676, 1.552427",\ + "0.266884, 0.507931, 0.698149, 0.997983, 1.574940",\ + "0.433723, 0.644987, 0.839140, 1.145591, 1.735360",\ + "0.772213, 0.970110, 1.163579, 1.471793, 2.066329",\ + "0.307535, 0.525062, 0.731901, 1.026077, 1.591848",\ + "0.315597, 0.546729, 0.742759, 1.039118, 1.609468",\ + "0.329903, 0.565774, 0.755873, 1.055433, 1.631996",\ + "0.497055, 0.702831, 0.896872, 1.203056, 1.792447",\ + "0.835472, 1.027940, 1.221311, 1.529264, 2.123427",\ + "0.630646, 0.853005, 1.036340, 1.329254, 1.894087",\ + "0.643411, 0.859949, 1.046418, 1.342300, 1.911721",\ + "0.662302, 0.871170, 1.059532, 1.358621, 1.934267",\ + "0.824001, 1.008235, 1.200534, 1.506258, 2.094755",\ + "1.152404, 1.333245, 1.524972, 1.832471, 2.425749"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011"); + values ( "0.014090, 0.057759, 0.075820, 0.080331, 0.107469",\ + "0.025180, 0.064799, 0.067612, 0.083095, 0.115487",\ + "0.053782, 0.083479, 0.086622, 0.102435, 0.134993",\ + "0.368605, 0.368605, 0.369812, 0.373454, 0.381327",\ + "1.000406, 1.000406, 1.002137, 1.003830, 1.006481",\ + "0.014987, 0.057834, 0.075890, 0.080331, 0.107469",\ + "0.026088, 0.064832, 0.067612, 0.083095, 0.115487",\ + "0.054430, 0.083516, 0.086622, 0.102435, 0.134993",\ + "0.368605, 0.368605, 0.369812, 0.373454, 0.381327",\ + "1.000406, 1.000406, 1.002137, 1.003830, 1.006481",\ + "0.017662, 0.058002, 0.075892, 0.080331, 0.107469",\ + "0.028799, 0.064906, 0.067612, 0.083095, 0.115487",\ + "0.056363, 0.078451, 0.086622, 0.102435, 0.134993",\ + "0.368605, 0.368605, 0.369812, 0.373454, 0.381327",\ + "1.000406, 1.000406, 1.002137, 1.003830, 1.006481",\ + "0.020186, 0.058246, 0.075896, 0.080364, 0.107535",\ + "0.031356, 0.065014, 0.067628, 0.083134, 0.115565",\ + "0.058188, 0.078544, 0.086639, 0.102475, 0.135071",\ + "0.368605, 0.368605, 0.369814, 0.373463, 0.381346",\ + "1.000406, 1.000406, 1.002141, 1.003834, 1.006488",\ + "0.036287, 0.049252, 0.064182, 0.080393, 0.107614",\ + "0.047669, 0.060805, 0.067630, 0.083168, 0.115659",\ + "0.069823, 0.079193, 0.086642, 0.102509, 0.135166",\ + "0.368605, 0.368605, 0.369815, 0.373471, 0.381369",\ + "1.000406, 1.000406, 1.002141, 1.003836, 1.006495"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_min_2421*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[45]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011"); + values ( "0.473885, 0.684615, 0.861464, 1.145505, 1.695445",\ + "0.493257, 0.703986, 0.880836, 1.164877, 1.714816",\ + "0.524711, 0.735440, 0.912290, 1.196331, 1.746270",\ + "0.813647, 1.024377, 1.201226, 1.485267, 2.035206",\ + "1.407539, 1.618269, 1.795118, 2.079159, 2.629098",\ + "0.562155, 0.771933, 0.948745, 1.232810, 1.782798",\ + "0.581527, 0.791304, 0.968117, 1.252182, 1.802170",\ + "0.612981, 0.822758, 0.999571, 1.283636, 1.833624",\ + "0.901917, 1.111694, 1.288507, 1.572572, 2.122560",\ + "1.495809, 1.705587, 1.882399, 2.166464, 2.716452",\ + "0.651344, 0.852264, 1.028772, 1.312839, 1.862830",\ + "0.670716, 0.871635, 1.048143, 1.332211, 1.882201",\ + "0.702170, 0.903089, 1.079598, 1.363665, 1.913656",\ + "0.991106, 1.192025, 1.368534, 1.652601, 2.202591",\ + "1.584998, 1.785918, 1.962426, 2.246493, 2.796484",\ + "0.714933, 0.910084, 1.086463, 1.370256, 1.919821",\ + "0.734305, 0.929456, 1.105835, 1.389627, 1.939192",\ + "0.765759, 0.960910, 1.137289, 1.421082, 1.970646",\ + "1.054695, 1.249846, 1.426225, 1.710018, 2.259583",\ + "1.648587, 1.843739, 2.020117, 2.303910, 2.853475",\ + "1.036585, 1.215328, 1.390118, 1.673416, 2.222012",\ + "1.055957, 1.234700, 1.409489, 1.692788, 2.241384",\ + "1.087411, 1.266154, 1.440943, 1.724242, 2.272838",\ + "1.376347, 1.555090, 1.729879, 2.013178, 2.561774",\ + "1.970239, 2.148982, 2.323771, 2.607070, 3.155666"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011"); + values ( "0.108153, 0.108153, 0.108153, 0.108153, 0.108153",\ + "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\ + "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\ + "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\ + "2.194882, 2.194882, 2.194882, 2.194882, 2.194882",\ + "0.108153, 0.108153, 0.108153, 0.108153, 0.108153",\ + "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\ + "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\ + "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\ + "2.194882, 2.194882, 2.194882, 2.194882, 2.194882",\ + "0.108153, 0.108153, 0.108153, 0.108153, 0.108153",\ + "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\ + "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\ + "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\ + "2.194882, 2.194882, 2.194882, 2.194882, 2.194882",\ + "0.108153, 0.108153, 0.108153, 0.108153, 0.108153",\ + "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\ + "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\ + "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\ + "2.194882, 2.194882, 2.194882, 2.194882, 2.194882",\ + "0.108153, 0.108153, 0.108153, 0.108153, 0.108153",\ + "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\ + "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\ + "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\ + "2.194882, 2.194882, 2.194882, 2.194882, 2.194882"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011"); + values ( "0.483132, 0.693861, 0.870710, 1.154752, 1.704691",\ + "0.490942, 0.701672, 0.878521, 1.162562, 1.712502",\ + "0.504361, 0.715091, 0.891940, 1.175981, 1.725921",\ + "0.657331, 0.868061, 1.044910, 1.328951, 1.878891",\ + "0.991399, 1.202129, 1.378978, 1.663020, 2.212959",\ + "0.571402, 0.781179, 0.957991, 1.242057, 1.792045",\ + "0.579212, 0.788990, 0.965802, 1.249867, 1.799855",\ + "0.592631, 0.802409, 0.979221, 1.263286, 1.813274",\ + "0.745601, 0.955379, 1.132191, 1.416256, 1.966244",\ + "1.079669, 1.289447, 1.466259, 1.750325, 2.300312",\ + "0.660591, 0.861510, 1.038018, 1.322085, 1.872076",\ + "0.668401, 0.869320, 1.045829, 1.329896, 1.879887",\ + "0.681820, 0.882740, 1.059248, 1.343315, 1.893306",\ + "0.834790, 1.035710, 1.212218, 1.496285, 2.046276",\ + "1.168858, 1.369778, 1.546286, 1.830353, 2.380344",\ + "0.724180, 0.919331, 1.095710, 1.379503, 1.929067",\ + "0.731990, 0.927141, 1.103520, 1.387313, 1.936877",\ + "0.745409, 0.940561, 1.116939, 1.400732, 1.950297",\ + "0.898379, 1.093531, 1.269909, 1.553702, 2.103267",\ + "1.232447, 1.427599, 1.603977, 1.887770, 2.437335",\ + "1.045832, 1.224575, 1.399364, 1.682663, 2.231259",\ + "1.053642, 1.232385, 1.407174, 1.690473, 2.239069",\ + "1.067061, 1.245804, 1.420594, 1.703892, 2.252488",\ + "1.220031, 1.398774, 1.573564, 1.856862, 2.405458",\ + "1.554100, 1.732842, 1.907632, 2.190930, 2.739527"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011"); + values ( "0.046252, 0.046252, 0.046252, 0.046252, 0.046252",\ + "0.051899, 0.051899, 0.051899, 0.051899, 0.051899",\ + "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\ + "0.368838, 0.368838, 0.368838, 0.368838, 0.368838",\ + "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\ + "0.046252, 0.046252, 0.046252, 0.046252, 0.046252",\ + "0.051899, 0.051899, 0.051899, 0.051899, 0.051899",\ + "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\ + "0.368838, 0.368838, 0.368838, 0.368838, 0.368838",\ + "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\ + "0.046252, 0.046252, 0.046252, 0.046252, 0.046252",\ + "0.051899, 0.051899, 0.051899, 0.051899, 0.051899",\ + "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\ + "0.368838, 0.368838, 0.368838, 0.368838, 0.368838",\ + "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\ + "0.046252, 0.046252, 0.046252, 0.046252, 0.046252",\ + "0.051899, 0.051899, 0.051899, 0.051899, 0.051899",\ + "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\ + "0.368838, 0.368838, 0.368838, 0.368838, 0.368838",\ + "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\ + "0.046252, 0.046252, 0.046252, 0.046252, 0.046252",\ + "0.051899, 0.051899, 0.051899, 0.051899, 0.051899",\ + "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\ + "0.368838, 0.368838, 0.368838, 0.368838, 0.368838",\ + "1.000959, 1.000959, 1.000959, 1.000959, 1.000959"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_min_2516*/ + +} /* end of pin tl_o[5] */ + +pin("tl_o[4]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.020161 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : tl_o[4]; + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[17]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011"); + values ( "0.778821, 1.003429, 1.297149, 1.790603, 2.777510",\ + "0.825348, 1.049956, 1.343676, 1.837130, 2.824038",\ + "0.910982, 1.135590, 1.429310, 1.922764, 2.909672",\ + "1.134301, 1.358909, 1.652629, 2.146083, 3.132991",\ + "1.698246, 1.922854, 2.216574, 2.710028, 3.696936",\ + "0.866262, 1.091031, 1.384796, 1.877318, 2.863444",\ + "0.912789, 1.137558, 1.431323, 1.923846, 2.909971",\ + "0.998423, 1.223192, 1.516957, 2.009480, 2.995605",\ + "1.221742, 1.446511, 1.740276, 2.232799, 3.218925",\ + "1.785687, 2.010456, 2.304221, 2.796744, 3.782870",\ + "0.947141, 1.180161, 1.472762, 1.964941, 2.950399",\ + "0.993669, 1.226688, 1.519289, 2.011468, 2.996926",\ + "1.079303, 1.312322, 1.604924, 2.097103, 3.082561",\ + "1.302622, 1.535641, 1.828242, 2.320421, 3.305880",\ + "1.866567, 2.099586, 2.392188, 2.884367, 3.869825",\ + "1.004861, 1.246014, 1.536906, 2.028855, 3.013908",\ + "1.051388, 1.292541, 1.583433, 2.075382, 3.060435",\ + "1.137022, 1.378175, 1.669067, 2.161016, 3.146070",\ + "1.360341, 1.601494, 1.892386, 2.384335, 3.369389",\ + "1.924286, 2.165440, 2.456331, 2.948280, 3.933334",\ + "1.307537, 1.612873, 1.889025, 2.378309, 3.359364",\ + "1.354064, 1.659401, 1.935552, 2.424836, 3.405891",\ + "1.439698, 1.745035, 2.021186, 2.510470, 3.491526",\ + "1.663017, 1.968354, 2.244505, 2.733789, 3.714845",\ + "2.226962, 2.532299, 2.808450, 3.297734, 4.278790"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011"); + values ( "0.052220, 0.052220, 0.052220, 0.052220, 0.052220",\ + "0.174408, 0.174408, 0.174408, 0.174408, 0.174408",\ + "0.378144, 0.378144, 0.378144, 0.378144, 0.378144",\ + "0.885509, 0.885509, 0.885509, 0.885509, 0.885509",\ + "2.163010, 2.163010, 2.163010, 2.163010, 2.163010",\ + "0.052220, 0.052220, 0.052220, 0.052220, 0.052220",\ + "0.174408, 0.174408, 0.174408, 0.174408, 0.174408",\ + "0.378144, 0.378144, 0.378144, 0.378144, 0.378144",\ + "0.885509, 0.885509, 0.885509, 0.885509, 0.885509",\ + "2.163010, 2.163010, 2.163010, 2.163010, 2.163010",\ + "0.052220, 0.052220, 0.052220, 0.052220, 0.052220",\ + "0.174408, 0.174408, 0.174408, 0.174408, 0.174408",\ + "0.378144, 0.378144, 0.378144, 0.378144, 0.378144",\ + "0.885509, 0.885509, 0.885509, 0.885509, 0.885509",\ + "2.163010, 2.163010, 2.163010, 2.163010, 2.163010",\ + "0.052220, 0.052220, 0.052220, 0.052220, 0.052220",\ + "0.174408, 0.174408, 0.174408, 0.174408, 0.174408",\ + "0.378144, 0.378144, 0.378144, 0.378144, 0.378144",\ + "0.885509, 0.885509, 0.885509, 0.885509, 0.885509",\ + "2.163010, 2.163010, 2.163010, 2.163010, 2.163010",\ + "0.052220, 0.052220, 0.052220, 0.052220, 0.052220",\ + "0.174408, 0.174408, 0.174408, 0.174408, 0.174408",\ + "0.378144, 0.378144, 0.378144, 0.378144, 0.378144",\ + "0.885509, 0.885509, 0.885509, 0.885509, 0.885509",\ + "2.163010, 2.163010, 2.163010, 2.163010, 2.163010"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011"); + values ( "0.717206, 0.941815, 1.235535, 1.728989, 2.715896",\ + "0.770496, 0.995104, 1.288824, 1.782278, 2.769186",\ + "0.831244, 1.055852, 1.349573, 1.843026, 2.829934",\ + "0.965956, 1.190564, 1.484284, 1.977738, 2.964645",\ + "1.312464, 1.537072, 1.830792, 2.324246, 3.311154",\ + "0.804648, 1.029416, 1.323182, 1.815704, 2.801830",\ + "0.857937, 1.082706, 1.376471, 1.868994, 2.855119",\ + "0.918686, 1.143454, 1.437219, 1.929742, 2.915868",\ + "1.053397, 1.278166, 1.571931, 2.064453, 3.050579",\ + "1.399905, 1.624674, 1.918439, 2.410962, 3.397088",\ + "0.885527, 1.118547, 1.411148, 1.903327, 2.888785",\ + "0.938817, 1.171836, 1.464437, 1.956616, 2.942075",\ + "0.999565, 1.232585, 1.525186, 2.017365, 3.002823",\ + "1.134276, 1.367296, 1.659897, 2.152076, 3.137534",\ + "1.480785, 1.713804, 2.006406, 2.498585, 3.484043",\ + "0.943246, 1.184400, 1.475292, 1.967241, 2.952294",\ + "0.996536, 1.237689, 1.528581, 2.020530, 3.005584",\ + "1.057284, 1.298438, 1.589330, 2.081279, 3.066332",\ + "1.191995, 1.433149, 1.724041, 2.215990, 3.201043",\ + "1.538504, 1.779658, 2.070549, 2.562499, 3.547552",\ + "1.245923, 1.551259, 1.827411, 2.316695, 3.297750",\ + "1.299212, 1.604549, 1.880700, 2.369984, 3.351039",\ + "1.359961, 1.665297, 1.941449, 2.430732, 3.411788",\ + "1.494672, 1.800008, 2.076160, 2.565444, 3.546499",\ + "1.841180, 2.146517, 2.422668, 2.911952, 3.893008"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011"); + values ( "0.060037, 0.060037, 0.060037, 0.060037, 0.060037",\ + "0.113990, 0.113990, 0.113990, 0.113990, 0.113990",\ + "0.199694, 0.199694, 0.199694, 0.199694, 0.199694",\ + "0.445487, 0.445487, 0.445487, 0.445487, 0.445487",\ + "1.101436, 1.101436, 1.101436, 1.101436, 1.101436",\ + "0.060037, 0.060037, 0.060037, 0.060037, 0.060037",\ + "0.113990, 0.113990, 0.113990, 0.113990, 0.113990",\ + "0.199694, 0.199694, 0.199694, 0.199694, 0.199694",\ + "0.445487, 0.445487, 0.445487, 0.445487, 0.445487",\ + "1.101436, 1.101436, 1.101436, 1.101436, 1.101436",\ + "0.060037, 0.060037, 0.060037, 0.060037, 0.060037",\ + "0.113990, 0.113990, 0.113990, 0.113990, 0.113990",\ + "0.199694, 0.199694, 0.199694, 0.199694, 0.199694",\ + "0.445487, 0.445487, 0.445487, 0.445487, 0.445487",\ + "1.101436, 1.101436, 1.101436, 1.101436, 1.101436",\ + "0.060037, 0.060037, 0.060037, 0.060037, 0.060037",\ + "0.113990, 0.113990, 0.113990, 0.113990, 0.113990",\ + "0.199694, 0.199694, 0.199694, 0.199694, 0.199694",\ + "0.445487, 0.445487, 0.445487, 0.445487, 0.445487",\ + "1.101436, 1.101436, 1.101436, 1.101436, 1.101436",\ + "0.060037, 0.060037, 0.060037, 0.060037, 0.060037",\ + "0.113990, 0.113990, 0.113990, 0.113990, 0.113990",\ + "0.199694, 0.199694, 0.199694, 0.199694, 0.199694",\ + "0.445487, 0.445487, 0.445487, 0.445487, 0.445487",\ + "1.101436, 1.101436, 1.101436, 1.101436, 1.101436"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_2677*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[19]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011"); + values ( "0.619374, 0.887475, 1.180133, 1.686418, 2.698987",\ + "0.666474, 0.934595, 1.227354, 1.733911, 2.747024",\ + "0.753747, 1.021925, 1.314971, 1.822307, 2.836977",\ + "0.979596, 1.247862, 1.541350, 2.049887, 3.066961",\ + "1.546840, 1.815220, 2.109287, 2.619390, 3.639598",\ + "0.706782, 0.975064, 1.267816, 1.773132, 2.784921",\ + "0.753882, 1.022185, 1.315038, 1.820625, 2.832958",\ + "0.841156, 1.109515, 1.402658, 1.909021, 2.922911",\ + "1.067004, 1.335453, 1.629041, 2.136601, 3.152895",\ + "1.634248, 1.902812, 2.196982, 2.706105, 3.725532",\ + "0.790149, 1.064125, 1.355782, 1.860753, 2.871876",\ + "0.837250, 1.111246, 1.403004, 1.908246, 2.919913",\ + "0.924524, 1.198577, 1.490623, 1.996642, 3.009866",\ + "1.150375, 1.424515, 1.717007, 2.224223, 3.239850",\ + "1.717623, 1.991877, 2.284948, 2.793726, 3.812487",\ + "0.853818, 1.129875, 1.419928, 1.924667, 2.935385",\ + "0.900919, 1.176996, 1.467150, 1.972159, 2.983422",\ + "0.988195, 1.264329, 1.554770, 2.060555, 3.073375",\ + "1.214048, 1.490269, 1.781153, 2.288136, 3.303359",\ + "1.781297, 2.057633, 2.349094, 2.857639, 3.875996",\ + "1.190374, 1.495641, 1.772172, 2.274166, 3.280841",\ + "1.237478, 1.542768, 1.819397, 2.321660, 3.328878",\ + "1.324760, 1.630116, 1.907025, 2.410059, 3.418831",\ + "1.550623, 1.856080, 2.133420, 2.637645, 3.648815",\ + "2.117886, 2.423474, 2.701378, 3.207154, 4.221452"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011"); + values ( "0.053871, 0.053928, 0.055014, 0.058545, 0.065606",\ + "0.173261, 0.173221, 0.173020, 0.172475, 0.171386",\ + "0.375447, 0.375353, 0.374960, 0.373952, 0.371937",\ + "0.885472, 0.885429, 0.885258, 0.884858, 0.884057",\ + "2.163064, 2.163128, 2.163351, 2.163842, 2.164825",\ + "0.053871, 0.053928, 0.055025, 0.058545, 0.065606",\ + "0.173261, 0.173221, 0.173019, 0.172475, 0.171386",\ + "0.375447, 0.375352, 0.374957, 0.373952, 0.371937",\ + "0.885472, 0.885428, 0.885257, 0.884858, 0.884057",\ + "2.163064, 2.163129, 2.163352, 2.163842, 2.164825",\ + "0.053872, 0.053929, 0.055025, 0.058545, 0.065606",\ + "0.173260, 0.173220, 0.173019, 0.172475, 0.171386",\ + "0.375444, 0.375351, 0.374957, 0.373952, 0.371937",\ + "0.885472, 0.885428, 0.885257, 0.884858, 0.884057",\ + "2.163065, 2.163130, 2.163352, 2.163842, 2.164825",\ + "0.053873, 0.053930, 0.055026, 0.058545, 0.065606",\ + "0.173259, 0.173219, 0.173019, 0.172475, 0.171386",\ + "0.375442, 0.375349, 0.374957, 0.373952, 0.371937",\ + "0.885471, 0.885427, 0.885257, 0.884858, 0.884057",\ + "2.163066, 2.163132, 2.163352, 2.163842, 2.164825",\ + "0.053880, 0.053946, 0.055062, 0.058559, 0.065606",\ + "0.173255, 0.173209, 0.173013, 0.172473, 0.171386",\ + "0.375432, 0.375324, 0.374946, 0.373948, 0.371937",\ + "0.885469, 0.885413, 0.885253, 0.884856, 0.884057",\ + "2.163070, 2.163151, 2.163357, 2.163844, 2.164825"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011"); + values ( "0.549769, 0.817593, 1.110465, 1.618513, 2.634607",\ + "0.610729, 0.878819, 1.171421, 1.677554, 2.689819",\ + "0.677494, 0.945792, 1.239448, 1.748438, 2.766419",\ + "0.811699, 1.079980, 1.373547, 1.882297, 2.899797",\ + "1.155145, 1.423320, 1.716351, 2.223647, 3.238237",\ + "0.637177, 0.905181, 1.198154, 1.705227, 2.720541",\ + "0.698137, 0.966409, 1.259104, 1.764268, 2.775753",\ + "0.764902, 1.033383, 1.327140, 1.835153, 2.852353",\ + "0.899107, 1.167571, 1.461238, 1.969011, 2.985731",\ + "1.242554, 1.510911, 1.804038, 2.310361, 3.324171",\ + "0.720537, 0.994237, 1.286120, 1.792848, 2.807496",\ + "0.781504, 1.055469, 1.347070, 1.851890, 2.862708",\ + "0.848274, 1.122447, 1.415106, 1.922774, 2.939308",\ + "0.982479, 1.256634, 1.549204, 2.056633, 3.072686",\ + "1.325922, 1.599972, 1.892004, 2.397983, 3.411126",\ + "0.784201, 1.059981, 1.350266, 1.856762, 2.871005",\ + "0.845173, 1.121219, 1.411216, 1.915803, 2.926217",\ + "0.911947, 1.188202, 1.479252, 1.986687, 3.002817",\ + "1.046151, 1.322389, 1.613351, 2.120546, 3.136195",\ + "1.389593, 1.665724, 1.956150, 2.461896, 3.474635",\ + "1.120725, 1.425673, 1.702529, 2.206268, 3.216461",\ + "1.181728, 1.486982, 1.763459, 2.265301, 3.271673",\ + "1.248526, 1.554021, 1.831524, 2.336198, 3.348273",\ + "1.382729, 1.688203, 1.965620, 2.470056, 3.481651",\ + "1.726158, 2.031510, 2.308404, 2.811399, 3.820091"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011"); + values ( "0.071629, 0.072032, 0.074063, 0.079575, 0.090597",\ + "0.129720, 0.130266, 0.133020, 0.140492, 0.155435",\ + "0.214056, 0.214554, 0.217069, 0.223890, 0.237532",\ + "0.447094, 0.447150, 0.447431, 0.448194, 0.449721",\ + "1.100693, 1.100667, 1.100537, 1.100183, 1.099477",\ + "0.071629, 0.072034, 0.074081, 0.079575, 0.090597",\ + "0.129720, 0.130270, 0.133044, 0.140492, 0.155435",\ + "0.214056, 0.214558, 0.217090, 0.223890, 0.237532",\ + "0.447094, 0.447150, 0.447434, 0.448194, 0.449721",\ + "1.100693, 1.100667, 1.100536, 1.100183, 1.099477",\ + "0.071640, 0.072041, 0.074081, 0.079575, 0.090597",\ + "0.129735, 0.130278, 0.133044, 0.140492, 0.155435",\ + "0.214069, 0.214565, 0.217091, 0.223890, 0.237532",\ + "0.447096, 0.447151, 0.447434, 0.448194, 0.449721",\ + "1.100692, 1.100666, 1.100536, 1.100183, 1.099477",\ + "0.071647, 0.072050, 0.074082, 0.079575, 0.090597",\ + "0.129745, 0.130291, 0.133046, 0.140492, 0.155435",\ + "0.214078, 0.214577, 0.217092, 0.223890, 0.237532",\ + "0.447097, 0.447152, 0.447434, 0.448194, 0.449721",\ + "1.100691, 1.100666, 1.100535, 1.100183, 1.099477",\ + "0.071694, 0.072157, 0.074138, 0.079598, 0.090597",\ + "0.129808, 0.130436, 0.133121, 0.140523, 0.155435",\ + "0.214136, 0.214709, 0.217161, 0.223918, 0.237532",\ + "0.447103, 0.447167, 0.447442, 0.448198, 0.449721",\ + "1.100688, 1.100659, 1.100532, 1.100182, 1.099477"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_2675*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[21]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011"); + values ( "0.603037, 0.850281, 1.131477, 1.604469, 2.550452",\ + "0.650138, 0.897409, 1.178701, 1.651927, 2.598380",\ + "0.737413, 0.984763, 1.266326, 1.740225, 2.688022",\ + "0.963264, 1.210735, 1.492718, 1.967654, 2.917526",\ + "1.530512, 1.778140, 2.060669, 2.536958, 3.489536",\ + "0.690439, 0.937872, 1.219053, 1.691182, 2.636385",\ + "0.737540, 0.985001, 1.266277, 1.738640, 2.684314",\ + "0.824816, 1.072355, 1.353904, 1.826938, 2.773956",\ + "1.050667, 1.298328, 1.580299, 2.054367, 3.003459",\ + "1.617915, 1.865734, 2.148256, 2.623672, 3.575470",\ + "0.771264, 1.026907, 1.307016, 1.778803, 2.723340",\ + "0.818366, 1.074036, 1.354240, 1.826261, 2.771269",\ + "0.905641, 1.161391, 1.441867, 1.914558, 2.860911",\ + "1.131493, 1.387366, 1.668262, 2.141988, 3.090415",\ + "1.698741, 1.954774, 2.236218, 2.711293, 3.662425",\ + "0.828931, 1.092619, 1.371156, 1.842715, 2.786849",\ + "0.876032, 1.139748, 1.418380, 1.890174, 2.834778",\ + "0.963308, 1.227105, 1.506008, 1.978471, 2.924420",\ + "1.189160, 1.453082, 1.732403, 2.205900, 3.153924",\ + "1.756409, 2.020493, 2.300359, 2.775205, 3.725934",\ + "1.160146, 1.458017, 1.723059, 2.192071, 3.132305",\ + "1.207253, 1.505153, 1.770286, 2.239531, 3.180234",\ + "1.294543, 1.592528, 1.857920, 2.327831, 3.269876",\ + "1.520419, 1.818533, 2.084326, 2.555264, 3.499380",\ + "2.087698, 2.385982, 2.652296, 3.124575, 4.071390"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011"); + values ( "0.053872, 0.053951, 0.054623, 0.056651, 0.060707",\ + "0.173260, 0.173205, 0.173015, 0.172544, 0.171603",\ + "0.375444, 0.375315, 0.374890, 0.373861, 0.371802",\ + "0.885479, 0.885459, 0.885341, 0.885032, 0.884415",\ + "2.163055, 2.163084, 2.163257, 2.163712, 2.164621",\ + "0.053872, 0.053952, 0.054629, 0.056651, 0.060707",\ + "0.173260, 0.173205, 0.173013, 0.172544, 0.171603",\ + "0.375444, 0.375314, 0.374887, 0.373861, 0.371802",\ + "0.885479, 0.885459, 0.885340, 0.885032, 0.884415",\ + "2.163055, 2.163084, 2.163259, 2.163712, 2.164621",\ + "0.053873, 0.053953, 0.054629, 0.056651, 0.060707",\ + "0.173260, 0.173204, 0.173013, 0.172544, 0.171603",\ + "0.375443, 0.375312, 0.374887, 0.373861, 0.371802",\ + "0.885479, 0.885458, 0.885340, 0.885032, 0.884415",\ + "2.163055, 2.163085, 2.163259, 2.163712, 2.164621",\ + "0.053873, 0.053954, 0.054629, 0.056651, 0.060707",\ + "0.173259, 0.173203, 0.173013, 0.172544, 0.171603",\ + "0.375443, 0.375310, 0.374887, 0.373861, 0.371802",\ + "0.885479, 0.885458, 0.885340, 0.885032, 0.884415",\ + "2.163055, 2.163086, 2.163259, 2.163712, 2.164621",\ + "0.053888, 0.053973, 0.054650, 0.056659, 0.060707",\ + "0.173249, 0.173190, 0.173008, 0.172542, 0.171603",\ + "0.375418, 0.375279, 0.374876, 0.373857, 0.371802",\ + "0.885478, 0.885451, 0.885337, 0.885031, 0.884415",\ + "2.163055, 2.163095, 2.163263, 2.163714, 2.164621"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011"); + values ( "0.533423, 0.780287, 1.060158, 1.529873, 2.469302",\ + "0.594392, 0.841621, 1.122764, 1.595624, 2.541345",\ + "0.661163, 0.908679, 1.190820, 1.666147, 2.616802",\ + "0.795368, 1.042860, 1.324916, 1.800036, 2.750276",\ + "1.138811, 1.386156, 1.667706, 2.141570, 3.089298",\ + "0.620825, 0.867875, 1.147723, 1.616586, 2.555236",\ + "0.681794, 0.929212, 1.210339, 1.682338, 2.627278",\ + "0.748566, 0.996272, 1.278403, 1.752861, 2.702736",\ + "0.882770, 1.130452, 1.412499, 1.886750, 2.836210",\ + "1.226213, 1.473748, 1.755284, 2.228283, 3.175232",\ + "0.701650, 0.956905, 1.235686, 1.704207, 2.642191",\ + "0.762619, 1.018247, 1.298302, 1.769958, 2.714233",\ + "0.829392, 1.085311, 1.366366, 1.840481, 2.789691",\ + "0.963596, 1.219491, 1.500462, 1.974370, 2.923165",\ + "1.307039, 1.562785, 1.843247, 2.315904, 3.262187",\ + "0.759315, 1.022609, 1.299826, 1.768119, 2.705700",\ + "0.820286, 1.083958, 1.362442, 1.833871, 2.777742",\ + "0.887059, 1.151028, 1.430506, 1.904394, 2.853200",\ + "1.021263, 1.285207, 1.564602, 2.038283, 2.986674",\ + "1.364706, 1.628498, 1.907387, 2.379816, 3.325696",\ + "1.090457, 1.387917, 1.651696, 2.117462, 3.051156",\ + "1.151498, 1.449352, 1.714345, 2.183227, 3.123199",\ + "1.218327, 1.516490, 1.782434, 2.253760, 3.198656",\ + "1.352526, 1.650664, 1.916528, 2.387648, 3.332130",\ + "1.695940, 1.993920, 2.259300, 2.729176, 3.671152"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011"); + values ( "0.071642, 0.072195, 0.074119, 0.078878, 0.088395",\ + "0.129738, 0.130488, 0.133096, 0.139547, 0.152449",\ + "0.214072, 0.214757, 0.217138, 0.223027, 0.234806",\ + "0.447096, 0.447173, 0.447439, 0.448098, 0.449416",\ + "1.100692, 1.100656, 1.100533, 1.100228, 1.099618",\ + "0.071642, 0.072199, 0.074134, 0.078878, 0.088395",\ + "0.129738, 0.130493, 0.133116, 0.139547, 0.152449",\ + "0.214072, 0.214761, 0.217156, 0.223027, 0.234806",\ + "0.447096, 0.447173, 0.447441, 0.448098, 0.449416",\ + "1.100692, 1.100656, 1.100532, 1.100228, 1.099618",\ + "0.071643, 0.072206, 0.074135, 0.078878, 0.088395",\ + "0.129740, 0.130503, 0.133117, 0.139547, 0.152449",\ + "0.214073, 0.214770, 0.217157, 0.223027, 0.234806",\ + "0.447096, 0.447174, 0.447441, 0.448098, 0.449416",\ + "1.100692, 1.100656, 1.100532, 1.100228, 1.099618",\ + "0.071645, 0.072218, 0.074135, 0.078878, 0.088395",\ + "0.129742, 0.130518, 0.133118, 0.139547, 0.152449",\ + "0.214076, 0.214784, 0.217158, 0.223027, 0.234806",\ + "0.447096, 0.447176, 0.447441, 0.448098, 0.449416",\ + "1.100692, 1.100655, 1.100532, 1.100228, 1.099618",\ + "0.071752, 0.072348, 0.074184, 0.078897, 0.088395",\ + "0.129887, 0.130696, 0.133183, 0.139574, 0.152449",\ + "0.214208, 0.214946, 0.217217, 0.223052, 0.234806",\ + "0.447111, 0.447194, 0.447448, 0.448101, 0.449416",\ + "1.100685, 1.100646, 1.100529, 1.100227, 1.099618"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_2280*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[23]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011"); + values ( "0.240088, 0.510351, 0.797290, 1.285614, 2.262263",\ + "0.291602, 0.560872, 0.847259, 1.336249, 2.314227",\ + "0.366122, 0.638120, 0.923420, 1.410996, 2.386150",\ + "0.571697, 0.846754, 1.130217, 1.614147, 2.582006",\ + "1.124964, 1.399896, 1.682080, 2.162757, 3.124112",\ + "0.327497, 0.597936, 0.884917, 1.372329, 2.348197",\ + "0.379011, 0.648452, 0.934889, 1.422963, 2.400161",\ + "0.453531, 0.725696, 1.011044, 1.497711, 2.472083",\ + "0.660133, 0.934325, 1.217830, 1.700861, 2.667939",\ + "1.213404, 1.487464, 1.769683, 2.249471, 3.210046",\ + "0.411710, 0.686989, 0.972882, 1.459950, 2.435152",\ + "0.462735, 0.737494, 1.022853, 1.510585, 2.487116",\ + "0.540482, 0.814729, 1.099009, 1.585332, 2.559038",\ + "0.749582, 1.023346, 1.305795, 1.788483, 2.754894",\ + "1.302860, 1.576480, 1.857647, 2.337093, 3.297001",\ + "0.475438, 0.752729, 1.037025, 1.523864, 2.498661",\ + "0.526464, 0.803218, 1.086996, 1.574498, 2.550625",\ + "0.604208, 0.880438, 1.163152, 1.649246, 2.622547",\ + "0.813313, 1.089039, 1.369937, 1.852396, 2.818403",\ + "1.366598, 1.642166, 1.921789, 2.401006, 3.360510",\ + "0.812369, 1.118362, 1.389087, 1.873289, 2.844117",\ + "0.863397, 1.168668, 1.439066, 1.923926, 2.896081",\ + "0.941125, 1.245720, 1.515207, 1.998668, 2.968004",\ + "1.150264, 1.454128, 1.721955, 2.201803, 3.163859",\ + "1.703596, 2.007172, 2.273774, 2.750400, 3.705966"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011"); + values ( "0.247846, 0.302431, 0.404057, 0.594296, 0.974773",\ + "0.313758, 0.345633, 0.434590, 0.626480, 1.010259",\ + "0.435716, 0.458123, 0.529642, 0.703929, 1.052501",\ + "0.888071, 0.889365, 0.917551, 1.014829, 1.209385",\ + "2.165074, 2.165320, 2.171775, 2.192811, 2.234884",\ + "0.247846, 0.302730, 0.404657, 0.594296, 0.974773",\ + "0.313758, 0.345847, 0.435195, 0.626480, 1.010259",\ + "0.435716, 0.458259, 0.530192, 0.703929, 1.052501",\ + "0.888105, 0.889365, 0.917858, 1.014829, 1.209385",\ + "2.165074, 2.165323, 2.171841, 2.192811, 2.234884",\ + "0.250151, 0.303407, 0.404668, 0.594296, 0.974773",\ + "0.314673, 0.346332, 0.435207, 0.626480, 1.010259",\ + "0.436528, 0.458564, 0.530202, 0.703929, 1.052501",\ + "0.888203, 0.889365, 0.917863, 1.014829, 1.209385",\ + "2.165074, 2.165328, 2.171843, 2.192811, 2.234884",\ + "0.251745, 0.304389, 0.404700, 0.594296, 0.974773",\ + "0.315306, 0.347037, 0.435239, 0.626480, 1.010259",\ + "0.437090, 0.459008, 0.530231, 0.703929, 1.052501",\ + "0.888293, 0.889365, 0.917880, 1.014829, 1.209385",\ + "2.165074, 2.165335, 2.171846, 2.192811, 2.234884",\ + "0.261887, 0.315894, 0.406630, 0.595083, 0.974773",\ + "0.319332, 0.355290, 0.437185, 0.627274, 1.010259",\ + "0.440663, 0.464208, 0.531999, 0.704650, 1.052501",\ + "0.888871, 0.889365, 0.918867, 1.015232, 1.209385",\ + "2.165074, 2.165424, 2.172060, 2.192898, 2.234884"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011"); + values ( "0.240635, 0.424668, 0.712248, 1.199722, 2.174669",\ + "0.275706, 0.462604, 0.757879, 1.262184, 2.270793",\ + "0.326245, 0.516372, 0.817019, 1.338091, 2.380235",\ + "0.455748, 0.646142, 0.952035, 1.495042, 2.581054",\ + "0.793588, 0.988001, 1.296787, 1.858775, 2.982751",\ + "0.328044, 0.512258, 0.799873, 1.286436, 2.260602",\ + "0.363115, 0.550213, 0.845556, 1.348898, 2.356727",\ + "0.413654, 0.603984, 0.904750, 1.424805, 2.466169",\ + "0.543157, 0.733746, 1.039835, 1.581756, 2.666988",\ + "0.880997, 1.075589, 1.384646, 1.945489, 3.068685",\ + "0.408911, 0.601324, 0.887837, 1.374058, 2.347558",\ + "0.443982, 0.639320, 0.933522, 1.436520, 2.443682",\ + "0.494519, 0.693099, 0.992716, 1.512427, 2.553124",\ + "0.624023, 0.822845, 1.127803, 1.669378, 2.753943",\ + "0.961862, 1.164649, 1.472615, 2.033111, 3.155640",\ + "0.466595, 0.667083, 0.951980, 1.437971, 2.411067",\ + "0.501666, 0.705138, 0.997668, 1.500433, 2.507191",\ + "0.552202, 0.758927, 1.056865, 1.576340, 2.616633",\ + "0.681705, 0.888650, 1.191955, 1.733291, 2.817452",\ + "1.019543, 1.230399, 1.536770, 2.097024, 3.219149",\ + "0.769432, 1.032936, 1.304034, 1.787393, 2.756523",\ + "0.804503, 1.071688, 1.349892, 1.849925, 2.852647",\ + "0.855021, 1.125605, 1.409260, 1.925902, 2.962089",\ + "0.984519, 1.255053, 1.544572, 2.082943, 3.162908",\ + "1.322350, 1.596157, 1.889580, 2.446754, 3.564605"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011"); + values ( "0.078325, 0.113595, 0.189416, 0.342002, 0.647174",\ + "0.120997, 0.134862, 0.194741, 0.345549, 0.647167",\ + "0.210707, 0.216021, 0.258625, 0.388109, 0.647078",\ + "0.448759, 0.449630, 0.471236, 0.541414, 0.681771",\ + "1.101439, 1.102394, 1.113437, 1.151551, 1.227780",\ + "0.078325, 0.113799, 0.189898, 0.342002, 0.647174",\ + "0.120997, 0.134966, 0.195216, 0.345549, 0.647167",\ + "0.210707, 0.216054, 0.259033, 0.388109, 0.647078",\ + "0.448759, 0.449638, 0.471457, 0.541414, 0.681771",\ + "1.101439, 1.102394, 1.113557, 1.151551, 1.227780",\ + "0.078410, 0.114258, 0.189906, 0.342002, 0.647174",\ + "0.121014, 0.135201, 0.195225, 0.345549, 0.647167",\ + "0.210718, 0.216128, 0.259041, 0.388109, 0.647078",\ + "0.448759, 0.449657, 0.471461, 0.541414, 0.681771",\ + "1.101445, 1.102394, 1.113560, 1.151551, 1.227780",\ + "0.078573, 0.114926, 0.189932, 0.342002, 0.647174",\ + "0.121047, 0.135543, 0.195250, 0.345549, 0.647167",\ + "0.210740, 0.216235, 0.259062, 0.388109, 0.647078",\ + "0.448759, 0.449684, 0.471473, 0.541414, 0.681771",\ + "1.101456, 1.102394, 1.113566, 1.151551, 1.227780",\ + "0.080054, 0.122746, 0.191480, 0.342634, 0.647174",\ + "0.121349, 0.139547, 0.196780, 0.346174, 0.647167",\ + "0.210939, 0.217494, 0.260376, 0.388645, 0.647078",\ + "0.448759, 0.449998, 0.472185, 0.541705, 0.681771",\ + "1.101560, 1.102394, 1.113953, 1.151709, 1.227780"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_2359*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[24]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011"); + values ( "0.197425, 0.431841, 0.691115, 1.132558, 2.015443",\ + "0.256864, 0.482200, 0.742850, 1.186401, 2.073503",\ + "0.340685, 0.558516, 0.820189, 1.263949, 2.151470",\ + "0.552702, 0.766228, 1.030335, 1.473577, 2.360062",\ + "1.106653, 1.318570, 1.585965, 2.032625, 2.925946",\ + "0.284828, 0.519347, 0.778592, 1.219271, 2.101377",\ + "0.344267, 0.569712, 0.830334, 1.273115, 2.159437",\ + "0.428088, 0.646034, 0.907673, 1.350662, 2.237404",\ + "0.640105, 0.853764, 1.117818, 1.560291, 2.445995",\ + "1.194056, 1.406120, 1.673459, 2.119339, 3.011880",\ + "0.365631, 0.608197, 0.866553, 1.306892, 2.188332",\ + "0.425081, 0.658572, 0.918295, 1.360735, 2.246392",\ + "0.508910, 0.734909, 0.995634, 1.438283, 2.324359",\ + "0.720937, 0.942676, 1.205779, 1.647911, 2.532950",\ + "1.274892, 1.495066, 1.761420, 2.206959, 3.098835",\ + "0.423252, 0.673639, 0.930688, 1.370805, 2.251841",\ + "0.482725, 0.724031, 0.982430, 1.424648, 2.309901",\ + "0.566569, 0.800388, 1.059769, 1.502196, 2.387868",\ + "0.778616, 1.008210, 1.269914, 1.711824, 2.596459",\ + "1.332580, 1.560649, 1.825555, 2.270872, 3.162344",\ + "0.752151, 1.035876, 1.282272, 1.720031, 2.597297",\ + "0.801570, 1.086457, 1.334035, 1.773883, 2.655357",\ + "0.877150, 1.163054, 1.411376, 1.851432, 2.733324",\ + "1.083205, 1.371523, 1.621516, 2.061058, 2.941916",\ + "1.635753, 1.924533, 2.177192, 2.620120, 3.507800"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011"); + values ( "0.177313, 0.213491, 0.303378, 0.457569, 0.765950",\ + "0.250045, 0.279673, 0.356803, 0.520196, 0.846983",\ + "0.414565, 0.415724, 0.459633, 0.603345, 0.890769",\ + "0.887843, 0.887860, 0.923876, 1.046142, 1.290675",\ + "2.163223, 2.163223, 2.177277, 2.225018, 2.320500",\ + "0.177313, 0.213790, 0.303862, 0.457569, 0.765950",\ + "0.250045, 0.279868, 0.357315, 0.520196, 0.846983",\ + "0.414565, 0.415735, 0.460084, 0.603345, 0.890769",\ + "0.887843, 0.887860, 0.924259, 1.046142, 1.290675",\ + "2.163223, 2.163223, 2.177427, 2.225018, 2.320500",\ + "0.177336, 0.214442, 0.303871, 0.457569, 0.765950",\ + "0.250094, 0.280294, 0.357324, 0.520196, 0.846983",\ + "0.414565, 0.415758, 0.460092, 0.603345, 0.890769",\ + "0.887843, 0.887860, 0.924267, 1.046142, 1.290675",\ + "2.163223, 2.163223, 2.177430, 2.225018, 2.320500",\ + "0.177382, 0.215390, 0.303897, 0.457569, 0.765950",\ + "0.250194, 0.280912, 0.357352, 0.520196, 0.846983",\ + "0.414565, 0.415792, 0.460117, 0.603345, 0.890769",\ + "0.887843, 0.887860, 0.924288, 1.046142, 1.290675",\ + "2.163223, 2.163223, 2.177438, 2.225018, 2.320500",\ + "0.179822, 0.226518, 0.305460, 0.458204, 0.765950",\ + "0.255479, 0.288172, 0.359009, 0.520869, 0.846983",\ + "0.414565, 0.416193, 0.461574, 0.603937, 0.890769",\ + "0.887843, 0.887866, 0.925527, 1.046646, 1.290675",\ + "2.163223, 2.163223, 2.177922, 2.225215, 2.320500"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011"); + values ( "0.186404, 0.372214, 0.626375, 1.055893, 1.914929",\ + "0.215796, 0.420104, 0.691914, 1.154775, 2.080498",\ + "0.262340, 0.480772, 0.763179, 1.249218, 2.221297",\ + "0.391105, 0.611507, 0.905161, 1.430325, 2.480653",\ + "0.735355, 0.947201, 1.248974, 1.808736, 2.928262",\ + "0.273807, 0.459710, 0.713814, 1.142606, 2.000863",\ + "0.303199, 0.507653, 0.779458, 1.241489, 2.166432",\ + "0.349742, 0.568345, 0.850795, 1.335931, 2.307231",\ + "0.478508, 0.699079, 0.992901, 1.517038, 2.566586",\ + "0.822757, 1.034759, 1.336822, 1.895450, 3.014196",\ + "0.354668, 0.548536, 0.801774, 1.230227, 2.087818",\ + "0.384060, 0.596593, 0.867420, 1.329109, 2.253387",\ + "0.430602, 0.657342, 0.938759, 1.423552, 2.394186",\ + "0.559360, 0.788071, 1.080866, 1.604659, 2.653542",\ + "0.903600, 1.123721, 1.424789, 1.983071, 3.101151",\ + "0.412406, 0.613944, 0.865907, 1.294139, 2.151327",\ + "0.441797, 0.662169, 0.931558, 1.393022, 2.316896",\ + "0.488337, 0.722997, 1.002901, 1.487465, 2.457695",\ + "0.617079, 0.853721, 1.145016, 1.668572, 2.717051",\ + "0.961302, 1.189327, 1.488945, 2.046983, 3.164660",\ + "0.716048, 0.975780, 1.217370, 1.643317, 2.496783",\ + "0.745435, 1.025964, 1.283359, 1.742337, 2.662352",\ + "0.795621, 1.087736, 1.354937, 1.836875, 2.803151",\ + "0.926531, 1.218392, 1.497448, 2.018143, 3.062507",\ + "1.264602, 1.553481, 1.841728, 2.396697, 3.510116"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011"); + values ( "0.071183, 0.106867, 0.175274, 0.296411, 0.538686",\ + "0.120882, 0.144922, 0.213025, 0.350085, 0.624205",\ + "0.200934, 0.210784, 0.256174, 0.378831, 0.624145",\ + "0.444933, 0.444933, 0.478341, 0.591820, 0.818777",\ + "1.101084, 1.102468, 1.122484, 1.190474, 1.326455",\ + "0.071183, 0.107086, 0.175654, 0.296411, 0.538686",\ + "0.120882, 0.145109, 0.213454, 0.350085, 0.624205",\ + "0.200934, 0.210847, 0.256559, 0.378831, 0.624145",\ + "0.444933, 0.444933, 0.478697, 0.591820, 0.818777",\ + "1.101084, 1.102468, 1.122697, 1.190474, 1.326455",\ + "0.071251, 0.107567, 0.175661, 0.296411, 0.538686",\ + "0.120905, 0.145516, 0.213462, 0.350085, 0.624205",\ + "0.200952, 0.210983, 0.256566, 0.378831, 0.624145",\ + "0.444933, 0.444933, 0.478703, 0.591820, 0.818777",\ + "1.101092, 1.102468, 1.122701, 1.190474, 1.326455",\ + "0.071390, 0.108264, 0.175682, 0.296411, 0.538686",\ + "0.120951, 0.146107, 0.213486, 0.350085, 0.624205",\ + "0.200988, 0.211181, 0.256587, 0.378831, 0.624145",\ + "0.444933, 0.444933, 0.478723, 0.591820, 0.818777",\ + "1.101108, 1.102468, 1.122713, 1.190474, 1.326455",\ + "0.072681, 0.116454, 0.176910, 0.296910, 0.538686",\ + "0.121377, 0.153048, 0.214875, 0.350649, 0.624205",\ + "0.202909, 0.213502, 0.257831, 0.379336, 0.624145",\ + "0.444933, 0.444933, 0.479873, 0.592287, 0.818777",\ + "1.101257, 1.102468, 1.123402, 1.190754, 1.326455"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_2411*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[27]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011"); + values ( "0.553758, 0.808668, 1.064878, 1.505326, 2.386221",\ + "0.599911, 0.854821, 1.111032, 1.551482, 2.432382",\ + "0.684215, 0.939125, 1.195335, 1.635783, 2.516678",\ + "0.905378, 1.160288, 1.416497, 1.856937, 2.737819",\ + "1.466255, 1.721165, 1.977368, 2.417791, 3.298636",\ + "0.641291, 0.896159, 1.152351, 1.592039, 2.472155",\ + "0.687444, 0.942312, 1.198505, 1.638195, 2.518316",\ + "0.771748, 1.026616, 1.282809, 1.722496, 2.602612",\ + "0.992912, 1.247780, 1.503970, 1.943650, 2.823752",\ + "1.553789, 1.808657, 2.064841, 2.504504, 3.384570",\ + "0.730669, 0.984969, 1.240312, 1.679659, 2.559110",\ + "0.776822, 1.031122, 1.286465, 1.725815, 2.605271",\ + "0.861126, 1.115426, 1.370769, 1.810116, 2.689567",\ + "1.082289, 1.336589, 1.591930, 2.031271, 2.910707",\ + "1.643166, 1.897466, 2.152802, 2.592124, 3.471525",\ + "0.794611, 1.050352, 1.304446, 1.743572, 2.622619",\ + "0.840764, 1.096505, 1.350600, 1.789728, 2.668780",\ + "0.925068, 1.180809, 1.434903, 1.874029, 2.753076",\ + "1.146232, 1.401973, 1.656065, 2.095183, 2.974216",\ + "1.707109, 1.962849, 2.216936, 2.656037, 3.535034",\ + "1.132859, 1.411925, 1.656019, 2.092792, 2.968075",\ + "1.179013, 1.458078, 1.702173, 2.138948, 3.014236",\ + "1.263317, 1.542382, 1.786476, 2.223249, 3.098532",\ + "1.484480, 1.763546, 2.007637, 2.444404, 3.319673",\ + "2.045357, 2.324422, 2.568509, 3.005257, 3.880490"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011"); + values ( "0.051937, 0.051937, 0.051947, 0.051981, 0.052048",\ + "0.176967, 0.176967, 0.176984, 0.177041, 0.177156",\ + "0.380998, 0.380998, 0.381005, 0.381032, 0.381085",\ + "0.885970, 0.885970, 0.885970, 0.885970, 0.885971",\ + "2.162331, 2.162331, 2.162331, 2.162331, 2.162330",\ + "0.051937, 0.051937, 0.051947, 0.051981, 0.052048",\ + "0.176967, 0.176967, 0.176984, 0.177041, 0.177156",\ + "0.380998, 0.380998, 0.381006, 0.381032, 0.381085",\ + "0.885970, 0.885970, 0.885970, 0.885970, 0.885971",\ + "2.162331, 2.162331, 2.162331, 2.162331, 2.162330",\ + "0.051937, 0.051937, 0.051947, 0.051981, 0.052048",\ + "0.176967, 0.176967, 0.176984, 0.177041, 0.177156",\ + "0.380998, 0.380998, 0.381006, 0.381032, 0.381085",\ + "0.885970, 0.885970, 0.885970, 0.885970, 0.885971",\ + "2.162331, 2.162331, 2.162331, 2.162331, 2.162330",\ + "0.051937, 0.051937, 0.051947, 0.051981, 0.052048",\ + "0.176967, 0.176967, 0.176984, 0.177041, 0.177156",\ + "0.380998, 0.380998, 0.381006, 0.381032, 0.381085",\ + "0.885970, 0.885970, 0.885970, 0.885970, 0.885971",\ + "2.162331, 2.162331, 2.162331, 2.162331, 2.162330",\ + "0.051937, 0.051937, 0.051947, 0.051981, 0.052048",\ + "0.176967, 0.176967, 0.176985, 0.177042, 0.177156",\ + "0.380998, 0.380998, 0.381006, 0.381032, 0.381085",\ + "0.885970, 0.885970, 0.885970, 0.885970, 0.885971",\ + "2.162331, 2.162331, 2.162331, 2.162331, 2.162330"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011"); + values ( "0.540267, 0.795177, 1.050726, 1.488938, 2.365363",\ + "0.562618, 0.817528, 1.073077, 1.511289, 2.387713",\ + "0.603939, 0.858848, 1.114838, 1.554540, 2.433944",\ + "0.736907, 0.991817, 1.248027, 1.688475, 2.569372",\ + "1.086012, 1.340922, 1.597135, 2.037591, 2.918504",\ + "0.627801, 0.882669, 1.138192, 1.575651, 2.451297",\ + "0.650152, 0.905020, 1.160543, 1.598002, 2.473647",\ + "0.691472, 0.946340, 1.202309, 1.641253, 2.519878",\ + "0.824440, 1.079308, 1.335500, 1.775188, 2.655306",\ + "1.173546, 1.428414, 1.684608, 2.124305, 3.004438",\ + "0.717178, 0.971478, 1.226152, 1.663272, 2.538252",\ + "0.739529, 0.993829, 1.248503, 1.685622, 2.560602",\ + "0.780849, 1.035149, 1.290269, 1.728874, 2.606833",\ + "0.913818, 1.168118, 1.423461, 1.862809, 2.742261",\ + "1.262923, 1.517223, 1.772569, 2.211925, 3.091393",\ + "0.781121, 1.036862, 1.290286, 1.727184, 2.601761",\ + "0.803471, 1.059212, 1.312637, 1.749535, 2.624111",\ + "0.844792, 1.100533, 1.354404, 1.792786, 2.670342",\ + "0.977760, 1.233501, 1.487595, 1.926721, 2.805770",\ + "1.326866, 1.582607, 1.836703, 2.275837, 3.154902",\ + "1.119369, 1.398434, 1.641836, 2.076395, 2.947217",\ + "1.141720, 1.420785, 1.664187, 2.098746, 2.969567",\ + "1.183040, 1.462106, 1.705969, 2.142004, 3.015798",\ + "1.316008, 1.595074, 1.839168, 2.275942, 3.151226",\ + "1.665114, 1.944180, 2.188276, 2.625058, 3.500358"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011"); + values ( "0.048201, 0.048201, 0.048170, 0.048066, 0.047859",\ + "0.098620, 0.098620, 0.098587, 0.098478, 0.098260",\ + "0.188783, 0.188783, 0.188784, 0.188790, 0.188801",\ + "0.444126, 0.444126, 0.444125, 0.444121, 0.444113",\ + "1.101816, 1.101816, 1.101814, 1.101807, 1.101794",\ + "0.048201, 0.048201, 0.048170, 0.048066, 0.047859",\ + "0.098620, 0.098620, 0.098587, 0.098478, 0.098260",\ + "0.188783, 0.188783, 0.188784, 0.188790, 0.188801",\ + "0.444126, 0.444126, 0.444125, 0.444121, 0.444113",\ + "1.101816, 1.101816, 1.101814, 1.101807, 1.101794",\ + "0.048201, 0.048201, 0.048170, 0.048066, 0.047859",\ + "0.098620, 0.098620, 0.098587, 0.098478, 0.098260",\ + "0.188783, 0.188783, 0.188784, 0.188790, 0.188801",\ + "0.444126, 0.444126, 0.444125, 0.444121, 0.444113",\ + "1.101816, 1.101816, 1.101814, 1.101807, 1.101794",\ + "0.048201, 0.048201, 0.048170, 0.048066, 0.047859",\ + "0.098620, 0.098620, 0.098587, 0.098478, 0.098260",\ + "0.188783, 0.188783, 0.188784, 0.188790, 0.188801",\ + "0.444126, 0.444126, 0.444125, 0.444121, 0.444113",\ + "1.101816, 1.101816, 1.101814, 1.101807, 1.101794",\ + "0.048201, 0.048201, 0.048169, 0.048066, 0.047859",\ + "0.098620, 0.098620, 0.098586, 0.098478, 0.098260",\ + "0.188783, 0.188783, 0.188784, 0.188790, 0.188801",\ + "0.444126, 0.444126, 0.444125, 0.444121, 0.444113",\ + "1.101816, 1.101816, 1.101814, 1.101807, 1.101794"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_2563*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[31]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.525875, 0.768087, 1.036195, 1.520933, 2.490408",\ + "0.572028, 0.814241, 1.082351, 1.567096, 2.536584",\ + "0.656332, 0.898544, 1.166652, 1.651390, 2.620866",\ + "0.877495, 1.119706, 1.387806, 1.872524, 2.841960",\ + "1.438372, 1.680579, 1.948659, 2.433326, 3.402659",\ + "0.613284, 0.855558, 1.123811, 1.607647, 2.576342",\ + "0.659437, 0.901712, 1.169967, 1.653810, 2.622518",\ + "0.743741, 0.986015, 1.254268, 1.738104, 2.706800",\ + "0.964904, 1.207177, 1.475422, 1.959238, 2.927894",\ + "1.525780, 1.768050, 2.036275, 2.520041, 3.488593",\ + "0.694098, 0.944352, 1.211775, 1.695269, 2.663297",\ + "0.740251, 0.990506, 1.257931, 1.741431, 2.709473",\ + "0.824555, 1.074809, 1.342232, 1.825726, 2.793755",\ + "1.045718, 1.295971, 1.563386, 2.046860, 3.014849",\ + "1.606595, 1.856844, 2.124239, 2.607662, 3.575548",\ + "0.752011, 1.009716, 1.275917, 1.759182, 2.726806",\ + "0.798164, 1.055869, 1.322073, 1.805345, 2.772982",\ + "0.882468, 1.140173, 1.406374, 1.889639, 2.857264",\ + "1.103631, 1.361335, 1.627528, 2.110773, 3.078358",\ + "1.664508, 1.922208, 2.188382, 2.671575, 3.639057",\ + "1.085549, 1.370949, 1.627944, 2.108593, 3.072262",\ + "1.131702, 1.417103, 1.674100, 2.154755, 3.118438",\ + "1.216006, 1.501406, 1.758401, 2.239050, 3.202720",\ + "1.437170, 1.722567, 1.979555, 2.460184, 3.423814",\ + "1.998046, 2.283439, 2.540407, 3.020985, 3.984513"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.051938, 0.051944, 0.051982, 0.052078, 0.052272",\ + "0.176969, 0.176980, 0.177043, 0.177207, 0.177534",\ + "0.380998, 0.381003, 0.381033, 0.381108, 0.381260",\ + "0.885971, 0.885971, 0.885971, 0.885974, 0.885979",\ + "2.162331, 2.162331, 2.162331, 2.162331, 2.162331",\ + "0.051938, 0.051944, 0.051982, 0.052078, 0.052272",\ + "0.176969, 0.176980, 0.177044, 0.177207, 0.177534",\ + "0.380998, 0.381004, 0.381033, 0.381108, 0.381260",\ + "0.885971, 0.885971, 0.885971, 0.885974, 0.885979",\ + "2.162331, 2.162331, 2.162331, 2.162331, 2.162331",\ + "0.051938, 0.051945, 0.051982, 0.052078, 0.052272",\ + "0.176969, 0.176980, 0.177044, 0.177207, 0.177534",\ + "0.380998, 0.381004, 0.381033, 0.381108, 0.381260",\ + "0.885971, 0.885971, 0.885971, 0.885974, 0.885979",\ + "2.162331, 2.162331, 2.162331, 2.162331, 2.162331",\ + "0.051938, 0.051945, 0.051982, 0.052078, 0.052272",\ + "0.176969, 0.176981, 0.177044, 0.177207, 0.177534",\ + "0.380998, 0.381004, 0.381033, 0.381108, 0.381260",\ + "0.885971, 0.885971, 0.885971, 0.885974, 0.885979",\ + "2.162331, 2.162331, 2.162331, 2.162331, 2.162331",\ + "0.051938, 0.051947, 0.051983, 0.052079, 0.052272",\ + "0.176969, 0.176984, 0.177045, 0.177208, 0.177534",\ + "0.380998, 0.381006, 0.381034, 0.381109, 0.381260",\ + "0.885971, 0.885971, 0.885972, 0.885974, 0.885979",\ + "2.162331, 2.162331, 2.162331, 2.162331, 2.162331"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.512519, 0.754762, 1.019445, 1.492217, 2.437761",\ + "0.534869, 0.777112, 1.043739, 1.523217, 2.482171",\ + "0.576190, 0.818433, 1.086345, 1.570253, 2.538069",\ + "0.709024, 0.951236, 1.219345, 1.704084, 2.673563",\ + "1.058130, 1.300344, 1.568461, 2.053223, 3.022748",\ + "0.599927, 0.842233, 1.107023, 1.578931, 2.523695",\ + "0.622278, 0.864583, 1.131338, 1.609931, 2.568105",\ + "0.663599, 0.905904, 1.173958, 1.656967, 2.624003",\ + "0.796432, 1.038707, 1.306960, 1.790798, 2.759497",\ + "1.145538, 1.387814, 1.656077, 2.139938, 3.108682",\ + "0.680742, 0.931028, 1.194987, 1.666553, 2.610650",\ + "0.703093, 0.953378, 1.219303, 1.697553, 2.655060",\ + "0.744413, 0.994699, 1.261922, 1.744589, 2.710958",\ + "0.877247, 1.127501, 1.394925, 1.878420, 2.846452",\ + "1.226353, 1.476609, 1.744041, 2.227559, 3.195637",\ + "0.738655, 0.996392, 1.259127, 1.730466, 2.674159",\ + "0.761006, 1.018743, 1.283444, 1.761466, 2.718569",\ + "0.802326, 1.060063, 1.326064, 1.808502, 2.774467",\ + "0.935160, 1.192865, 1.459067, 1.942333, 2.909961",\ + "1.284266, 1.541972, 1.808183, 2.291472, 3.259146",\ + "1.072193, 1.357636, 1.611032, 2.079827, 3.019615",\ + "1.094544, 1.379987, 1.635417, 2.110855, 3.064025",\ + "1.135864, 1.421307, 1.678082, 2.157909, 3.119923",\ + "1.268698, 1.554098, 1.811093, 2.291744, 3.255417",\ + "1.617804, 1.903206, 2.160210, 2.640883, 3.604602"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.048198, 0.048178, 0.048063, 0.047766, 0.047172",\ + "0.098616, 0.098596, 0.098475, 0.098162, 0.097537",\ + "0.188783, 0.188784, 0.188790, 0.188806, 0.188837",\ + "0.444126, 0.444125, 0.444121, 0.444109, 0.444085",\ + "1.101815, 1.101814, 1.101807, 1.101788, 1.101750",\ + "0.048198, 0.048178, 0.048062, 0.047766, 0.047172",\ + "0.098616, 0.098596, 0.098474, 0.098162, 0.097537",\ + "0.188783, 0.188784, 0.188790, 0.188806, 0.188837",\ + "0.444126, 0.444125, 0.444121, 0.444109, 0.444085",\ + "1.101815, 1.101814, 1.101807, 1.101788, 1.101750",\ + "0.048198, 0.048177, 0.048062, 0.047766, 0.047172",\ + "0.098616, 0.098595, 0.098474, 0.098162, 0.097537",\ + "0.188783, 0.188784, 0.188790, 0.188806, 0.188837",\ + "0.444126, 0.444125, 0.444121, 0.444109, 0.444085",\ + "1.101815, 1.101814, 1.101807, 1.101788, 1.101750",\ + "0.048198, 0.048177, 0.048062, 0.047766, 0.047172",\ + "0.098616, 0.098594, 0.098474, 0.098162, 0.097537",\ + "0.188783, 0.188784, 0.188790, 0.188806, 0.188837",\ + "0.444126, 0.444125, 0.444121, 0.444109, 0.444085",\ + "1.101815, 1.101814, 1.101807, 1.101788, 1.101750",\ + "0.048198, 0.048170, 0.048059, 0.047765, 0.047172",\ + "0.098616, 0.098587, 0.098471, 0.098161, 0.097537",\ + "0.188783, 0.188784, 0.188790, 0.188806, 0.188837",\ + "0.444126, 0.444125, 0.444121, 0.444109, 0.444085",\ + "1.101815, 1.101814, 1.101807, 1.101788, 1.101750"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[4]_redg*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[32]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.659689, 0.901731, 1.166165, 1.640730, 2.589860",\ + "0.706217, 0.948259, 1.212695, 1.687267, 2.636411",\ + "0.791853, 1.033895, 1.298337, 1.772929, 2.722115",\ + "1.015175, 1.257217, 1.521667, 1.996292, 2.945540",\ + "1.579124, 1.821166, 2.085628, 2.560294, 3.509625",\ + "0.747090, 0.989208, 1.253745, 1.727443, 2.675794",\ + "0.793618, 1.035736, 1.300275, 1.773980, 2.722345",\ + "0.879254, 1.121372, 1.385917, 1.859643, 2.808049",\ + "1.102576, 1.344694, 1.609248, 2.083005, 3.031474",\ + "1.666525, 1.908643, 2.173209, 2.647007, 3.595559",\ + "0.827897, 1.077990, 1.341708, 1.815064, 2.762749",\ + "0.874425, 1.124518, 1.388238, 1.861601, 2.809300",\ + "0.960061, 1.210154, 1.473880, 1.947263, 2.895004",\ + "1.183383, 1.433476, 1.697210, 2.170625, 3.118429",\ + "1.747332, 1.997425, 2.261171, 2.734627, 3.682514",\ + "0.888137, 1.143334, 1.405848, 1.878976, 2.826258",\ + "0.934665, 1.189862, 1.452378, 1.925513, 2.872809",\ + "1.020301, 1.275498, 1.538020, 2.011176, 2.958513",\ + "1.243623, 1.498820, 1.761351, 2.234538, 3.181938",\ + "1.807572, 2.062769, 2.325312, 2.798540, 3.746023",\ + "1.226031, 1.504429, 1.757767, 2.228338, 3.171714",\ + "1.272558, 1.550957, 1.804297, 2.274875, 3.218265",\ + "1.358195, 1.636593, 1.889939, 2.360538, 3.303969",\ + "1.581517, 1.859915, 2.113271, 2.583900, 3.527394",\ + "2.145466, 2.423864, 2.677232, 3.147902, 4.091479"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.052222, 0.052222, 0.052228, 0.052249, 0.052290",\ + "0.174407, 0.174407, 0.174407, 0.174407, 0.174407",\ + "0.378141, 0.378141, 0.378141, 0.378141, 0.378141",\ + "0.885509, 0.885509, 0.885509, 0.885509, 0.885509",\ + "2.163010, 2.163011, 2.163015, 2.163025, 2.163045",\ + "0.052222, 0.052222, 0.052228, 0.052249, 0.052290",\ + "0.174407, 0.174407, 0.174407, 0.174407, 0.174407",\ + "0.378141, 0.378141, 0.378141, 0.378141, 0.378141",\ + "0.885509, 0.885509, 0.885509, 0.885509, 0.885509",\ + "2.163010, 2.163011, 2.163015, 2.163025, 2.163045",\ + "0.052222, 0.052222, 0.052228, 0.052249, 0.052290",\ + "0.174407, 0.174407, 0.174407, 0.174407, 0.174407",\ + "0.378141, 0.378141, 0.378141, 0.378141, 0.378141",\ + "0.885509, 0.885509, 0.885509, 0.885509, 0.885509",\ + "2.163010, 2.163011, 2.163015, 2.163025, 2.163045",\ + "0.052222, 0.052222, 0.052228, 0.052249, 0.052290",\ + "0.174407, 0.174407, 0.174407, 0.174407, 0.174407",\ + "0.378141, 0.378141, 0.378141, 0.378141, 0.378141",\ + "0.885509, 0.885509, 0.885509, 0.885509, 0.885509",\ + "2.163010, 2.163011, 2.163015, 2.163025, 2.163045",\ + "0.052222, 0.052222, 0.052229, 0.052249, 0.052290",\ + "0.174407, 0.174407, 0.174407, 0.174407, 0.174407",\ + "0.378141, 0.378141, 0.378141, 0.378141, 0.378141",\ + "0.885509, 0.885509, 0.885509, 0.885509, 0.885509",\ + "2.163010, 2.163011, 2.163015, 2.163025, 2.163045"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.598065, 0.840108, 1.104513, 1.578978, 2.527908",\ + "0.651364, 0.893406, 1.157839, 1.632400, 2.581522",\ + "0.712119, 0.954162, 1.218616, 1.693252, 2.642524",\ + "0.846830, 1.088872, 1.353324, 1.827954, 2.777214",\ + "1.193335, 1.435377, 1.699819, 2.174410, 3.123593",\ + "0.685466, 0.927585, 1.192093, 1.665691, 2.613842",\ + "0.738765, 0.980883, 1.245419, 1.719113, 2.667456",\ + "0.799521, 1.041639, 1.306196, 1.779965, 2.728458",\ + "0.934231, 1.176349, 1.440905, 1.914667, 2.863148",\ + "1.280736, 1.522854, 1.787399, 2.261123, 3.209527",\ + "0.766273, 1.016367, 1.280056, 1.753312, 2.700797",\ + "0.819572, 1.069665, 1.333382, 1.806733, 2.754411",\ + "0.880328, 1.130420, 1.394158, 1.867585, 2.815413",\ + "1.015038, 1.265131, 1.528867, 2.002288, 2.950103",\ + "1.361543, 1.611636, 1.875361, 2.348744, 3.296482",\ + "0.826513, 1.081711, 1.344196, 1.817225, 2.764306",\ + "0.879812, 1.135009, 1.397522, 1.870646, 2.817920",\ + "0.940568, 1.195765, 1.458299, 1.931498, 2.878922",\ + "1.075278, 1.330475, 1.593008, 2.066200, 3.013612",\ + "1.421783, 1.676980, 1.939502, 2.412656, 3.359991",\ + "1.164407, 1.442806, 1.696114, 2.166586, 3.109762",\ + "1.217705, 1.496104, 1.749441, 2.220008, 3.163376",\ + "1.278461, 1.556859, 1.810219, 2.280860, 3.224378",\ + "1.413172, 1.691570, 1.944927, 2.415563, 3.359068",\ + "1.759677, 2.038075, 2.291421, 2.762018, 3.705447"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.060051, 0.060051, 0.060093, 0.060235, 0.060520",\ + "0.114009, 0.114009, 0.114066, 0.114262, 0.114654",\ + "0.199711, 0.199711, 0.199764, 0.199943, 0.200301",\ + "0.445489, 0.445489, 0.445495, 0.445515, 0.445555",\ + "1.101435, 1.101435, 1.101435, 1.101435, 1.101435",\ + "0.060051, 0.060051, 0.060094, 0.060235, 0.060520",\ + "0.114009, 0.114009, 0.114067, 0.114262, 0.114654",\ + "0.199711, 0.199711, 0.199765, 0.199943, 0.200301",\ + "0.445489, 0.445489, 0.445495, 0.445515, 0.445555",\ + "1.101435, 1.101435, 1.101435, 1.101435, 1.101435",\ + "0.060051, 0.060051, 0.060094, 0.060235, 0.060520",\ + "0.114009, 0.114009, 0.114067, 0.114262, 0.114654",\ + "0.199711, 0.199711, 0.199765, 0.199943, 0.200301",\ + "0.445489, 0.445489, 0.445495, 0.445515, 0.445555",\ + "1.101435, 1.101435, 1.101435, 1.101435, 1.101435",\ + "0.060051, 0.060051, 0.060094, 0.060235, 0.060520",\ + "0.114009, 0.114009, 0.114067, 0.114262, 0.114654",\ + "0.199711, 0.199711, 0.199765, 0.199943, 0.200301",\ + "0.445489, 0.445489, 0.445495, 0.445515, 0.445555",\ + "1.101435, 1.101435, 1.101435, 1.101435, 1.101435",\ + "0.060051, 0.060051, 0.060095, 0.060236, 0.060520",\ + "0.114009, 0.114009, 0.114069, 0.114263, 0.114654",\ + "0.199711, 0.199711, 0.199767, 0.199944, 0.200301",\ + "0.445489, 0.445489, 0.445496, 0.445515, 0.445555",\ + "1.101435, 1.101435, 1.101435, 1.101435, 1.101435"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_2315*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[34]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011"); + values ( "0.689570, 0.955359, 1.243359, 1.733584, 2.714034",\ + "0.735723, 1.001512, 1.289513, 1.779738, 2.760189",\ + "0.820027, 1.085816, 1.373816, 1.864041, 2.844491",\ + "1.041190, 1.306978, 1.594979, 2.085202, 3.065649",\ + "1.602065, 1.867854, 2.155853, 2.646073, 3.626513",\ + "0.776981, 1.042942, 1.330993, 1.820299, 2.799968",\ + "0.823135, 1.089095, 1.377147, 1.866453, 2.846122",\ + "0.907439, 1.173399, 1.461450, 1.950756, 2.930425",\ + "1.128601, 1.394562, 1.682613, 2.171917, 3.151583",\ + "1.689477, 1.955437, 2.243487, 2.732788, 3.712447",\ + "0.857898, 1.132003, 1.418959, 1.907921, 2.886923",\ + "0.904051, 1.178156, 1.465112, 1.954075, 2.933077",\ + "0.988355, 1.262460, 1.549416, 2.038378, 3.017380",\ + "1.209518, 1.483622, 1.770578, 2.259539, 3.238538",\ + "1.770393, 2.044498, 2.331453, 2.820410, 3.799402",\ + "0.918904, 1.197754, 1.483102, 1.971834, 2.950432",\ + "0.965057, 1.243907, 1.529255, 2.017988, 2.996586",\ + "1.049361, 1.328211, 1.613559, 2.102291, 3.080889",\ + "1.270524, 1.549374, 1.834721, 2.323452, 3.302047",\ + "1.831399, 2.110249, 2.395596, 2.884323, 3.862911",\ + "1.254896, 1.563490, 1.835185, 2.321270, 3.295888",\ + "1.301049, 1.609643, 1.881339, 2.367424, 3.342042",\ + "1.385353, 1.693947, 1.965642, 2.451727, 3.426345",\ + "1.606516, 1.915110, 2.186805, 2.672888, 3.647503",\ + "2.167391, 2.475986, 2.747679, 3.233759, 4.208367"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011"); + values ( "0.051940, 0.051940, 0.051942, 0.051949, 0.051962",\ + "0.176972, 0.176972, 0.176976, 0.176987, 0.177010",\ + "0.381000, 0.381000, 0.381002, 0.381007, 0.381017",\ + "0.885971, 0.885971, 0.885971, 0.885971, 0.885971",\ + "2.162330, 2.162330, 2.162330, 2.162330, 2.162330",\ + "0.051940, 0.051940, 0.051942, 0.051949, 0.051962",\ + "0.176972, 0.176972, 0.176976, 0.176987, 0.177010",\ + "0.381000, 0.381000, 0.381002, 0.381007, 0.381017",\ + "0.885971, 0.885971, 0.885971, 0.885971, 0.885971",\ + "2.162330, 2.162330, 2.162330, 2.162330, 2.162330",\ + "0.051940, 0.051940, 0.051942, 0.051949, 0.051962",\ + "0.176972, 0.176972, 0.176976, 0.176987, 0.177010",\ + "0.381000, 0.381000, 0.381002, 0.381007, 0.381017",\ + "0.885971, 0.885971, 0.885971, 0.885971, 0.885971",\ + "2.162330, 2.162330, 2.162330, 2.162330, 2.162330",\ + "0.051940, 0.051940, 0.051942, 0.051949, 0.051962",\ + "0.176972, 0.176972, 0.176976, 0.176987, 0.177010",\ + "0.381000, 0.381000, 0.381002, 0.381007, 0.381017",\ + "0.885971, 0.885971, 0.885971, 0.885971, 0.885971",\ + "2.162330, 2.162330, 2.162330, 2.162330, 2.162330",\ + "0.051940, 0.051940, 0.051942, 0.051949, 0.051962",\ + "0.176972, 0.176972, 0.176976, 0.176987, 0.177010",\ + "0.381000, 0.381000, 0.381002, 0.381007, 0.381017",\ + "0.885971, 0.885971, 0.885971, 0.885971, 0.885971",\ + "2.162330, 2.162330, 2.162330, 2.162330, 2.162330"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011"); + values ( "0.676230, 0.942019, 1.230037, 1.720324, 2.700896",\ + "0.698581, 0.964369, 1.252388, 1.742674, 2.723247",\ + "0.739901, 1.005690, 1.293708, 1.783995, 2.764567",\ + "0.872719, 1.138507, 1.426508, 1.916733, 2.897183",\ + "1.221825, 1.487614, 1.775615, 2.265841, 3.246295",\ + "0.763642, 1.029602, 1.317671, 1.807038, 2.786830",\ + "0.785992, 1.051952, 1.340022, 1.829389, 2.809181",\ + "0.827313, 1.093273, 1.381342, 1.870709, 2.850501",\ + "0.960130, 1.226091, 1.514142, 2.003448, 2.983117",\ + "1.309237, 1.575197, 1.863249, 2.352556, 3.332229",\ + "0.844558, 1.118663, 1.405637, 1.894660, 2.873785",\ + "0.866909, 1.141013, 1.427987, 1.917011, 2.896136",\ + "0.908229, 1.182334, 1.469308, 1.958331, 2.937456",\ + "1.041047, 1.315151, 1.602108, 2.091070, 3.070072",\ + "1.390153, 1.664258, 1.951214, 2.440178, 3.419184",\ + "0.905564, 1.184414, 1.469780, 1.958574, 2.937294",\ + "0.927915, 1.206764, 1.492131, 1.980924, 2.959645",\ + "0.969235, 1.248085, 1.533451, 2.022245, 3.000965",\ + "1.102053, 1.380903, 1.666251, 2.154983, 3.133581",\ + "1.451159, 1.730009, 2.015357, 2.504092, 3.482693",\ + "1.241556, 1.550150, 1.821864, 2.308010, 3.282750",\ + "1.263907, 1.572501, 1.844214, 2.330360, 3.305101",\ + "1.305227, 1.613822, 1.885535, 2.371680, 3.346421",\ + "1.438045, 1.746639, 2.018334, 2.504419, 3.479037",\ + "1.787151, 2.095746, 2.367441, 2.853527, 3.828149"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011"); + values ( "0.048192, 0.048192, 0.048186, 0.048165, 0.048124",\ + "0.098610, 0.098610, 0.098604, 0.098582, 0.098538",\ + "0.188783, 0.188783, 0.188784, 0.188785, 0.188787",\ + "0.444126, 0.444126, 0.444126, 0.444125, 0.444123",\ + "1.101815, 1.101815, 1.101815, 1.101813, 1.101811",\ + "0.048192, 0.048192, 0.048186, 0.048165, 0.048124",\ + "0.098610, 0.098610, 0.098604, 0.098582, 0.098538",\ + "0.188783, 0.188783, 0.188784, 0.188785, 0.188787",\ + "0.444126, 0.444126, 0.444126, 0.444125, 0.444123",\ + "1.101815, 1.101815, 1.101815, 1.101813, 1.101811",\ + "0.048192, 0.048192, 0.048186, 0.048165, 0.048124",\ + "0.098610, 0.098610, 0.098604, 0.098582, 0.098538",\ + "0.188783, 0.188783, 0.188784, 0.188785, 0.188787",\ + "0.444126, 0.444126, 0.444126, 0.444125, 0.444123",\ + "1.101815, 1.101815, 1.101815, 1.101813, 1.101811",\ + "0.048192, 0.048192, 0.048186, 0.048165, 0.048124",\ + "0.098610, 0.098610, 0.098604, 0.098582, 0.098538",\ + "0.188783, 0.188783, 0.188784, 0.188785, 0.188787",\ + "0.444126, 0.444126, 0.444126, 0.444125, 0.444123",\ + "1.101815, 1.101815, 1.101815, 1.101813, 1.101811",\ + "0.048192, 0.048192, 0.048185, 0.048165, 0.048124",\ + "0.098610, 0.098610, 0.098604, 0.098582, 0.098538",\ + "0.188783, 0.188783, 0.188784, 0.188785, 0.188787",\ + "0.444126, 0.444126, 0.444126, 0.444125, 0.444123",\ + "1.101815, 1.101815, 1.101815, 1.101813, 1.101811"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_2360*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[35]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.664659, 0.924878, 1.203873, 1.666613, 2.592093",\ + "0.710813, 0.971031, 1.250026, 1.712767, 2.638247",\ + "0.795116, 1.055335, 1.334330, 1.797070, 2.722549",\ + "1.016279, 1.276498, 1.555493, 2.018232, 2.943710",\ + "1.577155, 1.837373, 2.116368, 2.579105, 3.504579",\ + "0.752069, 1.012459, 1.291420, 1.753327, 2.678026",\ + "0.798222, 1.058612, 1.337573, 1.799481, 2.724180",\ + "0.882526, 1.142916, 1.421877, 1.883784, 2.808483",\ + "1.103689, 1.364079, 1.643039, 2.104946, 3.029644",\ + "1.664564, 1.924954, 2.203914, 2.665819, 3.590512",\ + "0.832929, 1.101504, 1.379383, 1.840949, 2.764981",\ + "0.879082, 1.147657, 1.425536, 1.887103, 2.811135",\ + "0.963386, 1.231961, 1.509840, 1.971406, 2.895438",\ + "1.184549, 1.453124, 1.731003, 2.192568, 3.116599",\ + "1.745424, 2.013999, 2.291878, 2.753441, 3.677467",\ + "0.893718, 1.167232, 1.443522, 1.904862, 2.828490",\ + "0.939871, 1.213386, 1.489675, 1.951016, 2.874644",\ + "1.024175, 1.297689, 1.573979, 2.035319, 2.958947",\ + "1.245338, 1.518852, 1.795141, 2.256481, 3.180108",\ + "1.806213, 2.079728, 2.356016, 2.817354, 3.740976",\ + "1.228556, 1.532729, 1.795325, 2.254182, 3.173946",\ + "1.274709, 1.578882, 1.841479, 2.300336, 3.220100",\ + "1.359013, 1.663186, 1.925782, 2.384639, 3.304403",\ + "1.580175, 1.884349, 2.146945, 2.605801, 3.525564",\ + "2.141051, 2.445224, 2.707820, 3.166674, 4.086432"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.051940, 0.051940, 0.051941, 0.051945, 0.051952",\ + "0.176973, 0.176973, 0.176974, 0.176981, 0.176994",\ + "0.381000, 0.381000, 0.381001, 0.381004, 0.381010",\ + "0.885971, 0.885971, 0.885971, 0.885971, 0.885971",\ + "2.162330, 2.162330, 2.162330, 2.162330, 2.162330",\ + "0.051940, 0.051940, 0.051941, 0.051945, 0.051952",\ + "0.176973, 0.176973, 0.176974, 0.176981, 0.176994",\ + "0.381000, 0.381000, 0.381001, 0.381004, 0.381010",\ + "0.885971, 0.885971, 0.885971, 0.885971, 0.885971",\ + "2.162330, 2.162330, 2.162330, 2.162330, 2.162330",\ + "0.051940, 0.051940, 0.051941, 0.051945, 0.051952",\ + "0.176973, 0.176973, 0.176974, 0.176981, 0.176994",\ + "0.381000, 0.381000, 0.381001, 0.381004, 0.381010",\ + "0.885971, 0.885971, 0.885971, 0.885971, 0.885971",\ + "2.162330, 2.162330, 2.162330, 2.162330, 2.162330",\ + "0.051940, 0.051940, 0.051941, 0.051945, 0.051952",\ + "0.176973, 0.176973, 0.176974, 0.176981, 0.176994",\ + "0.381000, 0.381000, 0.381001, 0.381004, 0.381010",\ + "0.885971, 0.885971, 0.885971, 0.885971, 0.885971",\ + "2.162330, 2.162330, 2.162330, 2.162330, 2.162330",\ + "0.051940, 0.051940, 0.051941, 0.051945, 0.051952",\ + "0.176973, 0.176973, 0.176974, 0.176981, 0.176994",\ + "0.381000, 0.381000, 0.381001, 0.381004, 0.381010",\ + "0.885971, 0.885971, 0.885971, 0.885971, 0.885971",\ + "2.162330, 2.162330, 2.162330, 2.162330, 2.162330"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.651319, 0.911538, 1.190542, 1.653312, 2.578852",\ + "0.673670, 0.933888, 1.212892, 1.675662, 2.601202",\ + "0.714990, 0.975209, 1.254213, 1.716983, 2.642523",\ + "0.847808, 1.108027, 1.387022, 1.849762, 2.775242",\ + "1.196915, 1.457133, 1.736129, 2.198870, 3.124351",\ + "0.738728, 0.999118, 1.278088, 1.740026, 2.664785",\ + "0.761079, 1.021469, 1.300439, 1.762377, 2.687136",\ + "0.802400, 1.062789, 1.341759, 1.803697, 2.728456",\ + "0.935218, 1.195608, 1.474569, 1.936476, 2.861175",\ + "1.284324, 1.544714, 1.823675, 2.285584, 3.210285",\ + "0.819588, 1.088164, 1.366052, 1.827648, 2.751740",\ + "0.841939, 1.110514, 1.388402, 1.849998, 2.774091",\ + "0.883259, 1.151835, 1.429723, 1.891319, 2.815412",\ + "1.016078, 1.284653, 1.562532, 2.024098, 2.948130",\ + "1.365184, 1.633759, 1.911639, 2.373206, 3.297240",\ + "0.880378, 1.153892, 1.430190, 1.891561, 2.815249",\ + "0.902728, 1.176243, 1.452541, 1.913912, 2.837600",\ + "0.944049, 1.217563, 1.493861, 1.955232, 2.878921",\ + "1.076867, 1.350381, 1.626671, 2.088011, 3.011639",\ + "1.425974, 1.699488, 1.975777, 2.437119, 3.360749",\ + "1.215215, 1.519388, 1.781994, 2.240881, 3.160706",\ + "1.237566, 1.541739, 1.804345, 2.263232, 3.183056",\ + "1.278886, 1.583060, 1.845665, 2.304552, 3.224377",\ + "1.411705, 1.715878, 1.978474, 2.437331, 3.357095",\ + "1.760811, 2.064984, 2.327581, 2.786439, 3.706205"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.048191, 0.048191, 0.048188, 0.048176, 0.048153",\ + "0.098610, 0.098610, 0.098606, 0.098594, 0.098570",\ + "0.188783, 0.188783, 0.188783, 0.188784, 0.188785",\ + "0.444126, 0.444126, 0.444126, 0.444125, 0.444124",\ + "1.101815, 1.101815, 1.101815, 1.101814, 1.101813",\ + "0.048191, 0.048191, 0.048188, 0.048176, 0.048153",\ + "0.098610, 0.098610, 0.098606, 0.098594, 0.098570",\ + "0.188783, 0.188783, 0.188783, 0.188784, 0.188785",\ + "0.444126, 0.444126, 0.444126, 0.444125, 0.444124",\ + "1.101815, 1.101815, 1.101815, 1.101814, 1.101813",\ + "0.048191, 0.048191, 0.048188, 0.048176, 0.048153",\ + "0.098610, 0.098610, 0.098606, 0.098594, 0.098570",\ + "0.188783, 0.188783, 0.188783, 0.188784, 0.188785",\ + "0.444126, 0.444126, 0.444126, 0.444125, 0.444124",\ + "1.101815, 1.101815, 1.101815, 1.101814, 1.101813",\ + "0.048191, 0.048191, 0.048188, 0.048176, 0.048153",\ + "0.098610, 0.098610, 0.098606, 0.098594, 0.098570",\ + "0.188783, 0.188783, 0.188783, 0.188784, 0.188785",\ + "0.444126, 0.444126, 0.444126, 0.444125, 0.444124",\ + "1.101815, 1.101815, 1.101815, 1.101814, 1.101813",\ + "0.048191, 0.048191, 0.048188, 0.048176, 0.048153",\ + "0.098610, 0.098610, 0.098606, 0.098594, 0.098570",\ + "0.188783, 0.188783, 0.188783, 0.188784, 0.188785",\ + "0.444126, 0.444126, 0.444126, 0.444125, 0.444124",\ + "1.101815, 1.101815, 1.101815, 1.101814, 1.101813"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_2403*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[36]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.748501, 1.009671, 1.301852, 1.810246, 2.827035",\ + "0.794654, 1.055824, 1.348005, 1.856399, 2.873188",\ + "0.878958, 1.140128, 1.432309, 1.940704, 2.957492",\ + "1.100121, 1.361291, 1.653472, 2.161867, 3.178656",\ + "1.660998, 1.922168, 2.214350, 2.722744, 3.739532",\ + "0.835913, 1.097245, 1.389544, 1.896961, 2.912969",\ + "0.882066, 1.143398, 1.435697, 1.943114, 2.959122",\ + "0.966370, 1.227702, 1.520001, 2.027418, 3.043426",\ + "1.187534, 1.448865, 1.741165, 2.248582, 3.264589",\ + "1.748411, 2.009742, 2.302042, 2.809459, 3.825466",\ + "0.916813, 1.186291, 1.477511, 1.984584, 2.999924",\ + "0.962966, 1.232444, 1.523664, 2.030737, 3.046077",\ + "1.047270, 1.316748, 1.607968, 2.115041, 3.130381",\ + "1.268433, 1.537911, 1.829131, 2.336204, 3.351544",\ + "1.829310, 2.098788, 2.390008, 2.897081, 3.912421",\ + "0.976448, 1.252020, 1.541657, 2.048497, 3.063433",\ + "1.022601, 1.298173, 1.587810, 2.094650, 3.109586",\ + "1.106905, 1.382477, 1.672114, 2.178954, 3.193890",\ + "1.328068, 1.603641, 1.893278, 2.400118, 3.415053",\ + "1.888945, 2.164518, 2.454154, 2.960994, 3.975930",\ + "1.310176, 1.617488, 1.893926, 2.398009, 3.408889",\ + "1.356329, 1.663641, 1.940079, 2.444162, 3.455042",\ + "1.440634, 1.747945, 2.024383, 2.528466, 3.539346",\ + "1.661797, 1.969109, 2.245546, 2.749630, 3.760509",\ + "2.222674, 2.529986, 2.806423, 3.310507, 4.321386"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.051937, 0.051937, 0.051937, 0.051937, 0.051937",\ + "0.176967, 0.176967, 0.176967, 0.176967, 0.176967",\ + "0.380998, 0.380998, 0.380998, 0.380998, 0.380998",\ + "0.885970, 0.885970, 0.885970, 0.885970, 0.885970",\ + "2.162331, 2.162331, 2.162331, 2.162331, 2.162331",\ + "0.051937, 0.051937, 0.051937, 0.051937, 0.051937",\ + "0.176967, 0.176967, 0.176967, 0.176967, 0.176967",\ + "0.380998, 0.380998, 0.380998, 0.380998, 0.380998",\ + "0.885970, 0.885970, 0.885970, 0.885970, 0.885970",\ + "2.162331, 2.162331, 2.162331, 2.162331, 2.162331",\ + "0.051937, 0.051937, 0.051937, 0.051937, 0.051937",\ + "0.176967, 0.176967, 0.176967, 0.176967, 0.176967",\ + "0.380998, 0.380998, 0.380998, 0.380998, 0.380998",\ + "0.885970, 0.885970, 0.885970, 0.885970, 0.885970",\ + "2.162331, 2.162331, 2.162331, 2.162331, 2.162331",\ + "0.051937, 0.051937, 0.051937, 0.051937, 0.051937",\ + "0.176967, 0.176967, 0.176967, 0.176967, 0.176967",\ + "0.380998, 0.380998, 0.380998, 0.380998, 0.380998",\ + "0.885970, 0.885970, 0.885970, 0.885970, 0.885970",\ + "2.162331, 2.162331, 2.162331, 2.162331, 2.162331",\ + "0.051937, 0.051937, 0.051937, 0.051937, 0.051937",\ + "0.176967, 0.176967, 0.176967, 0.176967, 0.176967",\ + "0.380998, 0.380998, 0.380998, 0.380998, 0.380998",\ + "0.885970, 0.885970, 0.885970, 0.885970, 0.885970",\ + "2.162331, 2.162331, 2.162331, 2.162331, 2.162331"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.735004, 0.996174, 1.288355, 1.796750, 2.813539",\ + "0.757355, 1.018525, 1.310706, 1.819101, 2.835889",\ + "0.798676, 1.059846, 1.352027, 1.860421, 2.877210",\ + "0.931650, 1.192820, 1.485001, 1.993395, 3.010184",\ + "1.280755, 1.541925, 1.834106, 2.342501, 3.359290",\ + "0.822417, 1.083748, 1.376048, 1.883465, 2.899472",\ + "0.844768, 1.106099, 1.398399, 1.905816, 2.921823",\ + "0.886088, 1.147419, 1.439719, 1.947136, 2.963144",\ + "1.019062, 1.280394, 1.572693, 2.080110, 3.096118",\ + "1.368168, 1.629499, 1.921799, 2.429216, 3.445223",\ + "0.903316, 1.172794, 1.464014, 1.971087, 2.986427",\ + "0.925667, 1.195145, 1.486365, 1.993438, 3.008778",\ + "0.966988, 1.236465, 1.527686, 2.034758, 3.050099",\ + "1.099962, 1.369439, 1.660660, 2.167732, 3.183073",\ + "1.449067, 1.718545, 2.009765, 2.516838, 3.532178",\ + "0.962951, 1.238524, 1.528160, 2.035001, 3.049936",\ + "0.985302, 1.260875, 1.550511, 2.057351, 3.072287",\ + "1.026623, 1.302195, 1.591832, 2.098672, 3.113608",\ + "1.159597, 1.435169, 1.724806, 2.231646, 3.246582",\ + "1.508702, 1.784275, 2.073912, 2.580752, 3.595687",\ + "1.296680, 1.603992, 1.880429, 2.384513, 3.395392",\ + "1.319031, 1.626343, 1.902780, 2.406864, 3.417743",\ + "1.360351, 1.667663, 1.944100, 2.448184, 3.459064",\ + "1.493325, 1.800637, 2.077075, 2.581158, 3.592038",\ + "1.842431, 2.149743, 2.426180, 2.930264, 3.941144"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.048201, 0.048201, 0.048201, 0.048201, 0.048201",\ + "0.098620, 0.098620, 0.098620, 0.098620, 0.098620",\ + "0.188783, 0.188783, 0.188783, 0.188783, 0.188783",\ + "0.444126, 0.444126, 0.444126, 0.444126, 0.444126",\ + "1.101816, 1.101816, 1.101816, 1.101816, 1.101816",\ + "0.048201, 0.048201, 0.048201, 0.048201, 0.048201",\ + "0.098620, 0.098620, 0.098620, 0.098620, 0.098620",\ + "0.188783, 0.188783, 0.188783, 0.188783, 0.188783",\ + "0.444126, 0.444126, 0.444126, 0.444126, 0.444126",\ + "1.101816, 1.101816, 1.101816, 1.101816, 1.101816",\ + "0.048201, 0.048201, 0.048201, 0.048201, 0.048201",\ + "0.098620, 0.098620, 0.098620, 0.098620, 0.098620",\ + "0.188783, 0.188783, 0.188783, 0.188783, 0.188783",\ + "0.444126, 0.444126, 0.444126, 0.444126, 0.444126",\ + "1.101816, 1.101816, 1.101816, 1.101816, 1.101816",\ + "0.048201, 0.048201, 0.048201, 0.048201, 0.048201",\ + "0.098620, 0.098620, 0.098620, 0.098620, 0.098620",\ + "0.188783, 0.188783, 0.188783, 0.188783, 0.188783",\ + "0.444126, 0.444126, 0.444126, 0.444126, 0.444126",\ + "1.101816, 1.101816, 1.101816, 1.101816, 1.101816",\ + "0.048201, 0.048201, 0.048201, 0.048201, 0.048201",\ + "0.098620, 0.098620, 0.098620, 0.098620, 0.098620",\ + "0.188783, 0.188783, 0.188783, 0.188783, 0.188783",\ + "0.444126, 0.444126, 0.444126, 0.444126, 0.444126",\ + "1.101816, 1.101816, 1.101816, 1.101816, 1.101816"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_2467*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[37]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.730463, 0.984563, 1.266812, 1.735637, 2.673288",\ + "0.776616, 1.030716, 1.312965, 1.781790, 2.719441",\ + "0.860920, 1.115021, 1.397269, 1.866094, 2.803746",\ + "1.082084, 1.336184, 1.618432, 2.087258, 3.024909",\ + "1.642961, 1.897061, 2.179309, 2.648135, 3.585786",\ + "0.817871, 1.072157, 1.354377, 1.822352, 2.759222",\ + "0.864024, 1.118310, 1.400530, 1.868505, 2.805375",\ + "0.948328, 1.202614, 1.484834, 1.952809, 2.889679",\ + "1.169492, 1.423777, 1.705998, 2.173972, 3.110843",\ + "1.730369, 1.984654, 2.266875, 2.734849, 3.671720",\ + "0.898712, 1.161224, 1.442341, 1.909973, 2.846177",\ + "0.944865, 1.207377, 1.488494, 1.956126, 2.892330",\ + "1.029169, 1.291681, 1.572798, 2.040430, 2.976635",\ + "1.250332, 1.512845, 1.793961, 2.261594, 3.197798",\ + "1.811209, 2.073722, 2.354838, 2.822471, 3.758675",\ + "0.956353, 1.226984, 1.506480, 1.973886, 2.909686",\ + "1.002506, 1.273137, 1.552633, 2.020039, 2.955839",\ + "1.086810, 1.357441, 1.636937, 2.104343, 3.040143",\ + "1.307973, 1.578604, 1.858101, 2.325507, 3.261307",\ + "1.868850, 2.139482, 2.418978, 2.886384, 3.822184",\ + "1.288825, 1.592869, 1.858345, 2.323230, 3.255142",\ + "1.334978, 1.639022, 1.904498, 2.369383, 3.301295",\ + "1.419282, 1.723326, 1.988802, 2.453687, 3.385599",\ + "1.640445, 1.944490, 2.209965, 2.674851, 3.606763",\ + "2.201322, 2.505367, 2.770842, 3.235728, 4.167640"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.051937, 0.051937, 0.051937, 0.051937, 0.051937",\ + "0.176967, 0.176967, 0.176967, 0.176967, 0.176967",\ + "0.380998, 0.380998, 0.380998, 0.380998, 0.380998",\ + "0.885970, 0.885970, 0.885970, 0.885970, 0.885970",\ + "2.162331, 2.162331, 2.162331, 2.162331, 2.162331",\ + "0.051937, 0.051937, 0.051937, 0.051937, 0.051937",\ + "0.176967, 0.176967, 0.176967, 0.176967, 0.176967",\ + "0.380998, 0.380998, 0.380998, 0.380998, 0.380998",\ + "0.885970, 0.885970, 0.885970, 0.885970, 0.885970",\ + "2.162331, 2.162331, 2.162331, 2.162331, 2.162331",\ + "0.051937, 0.051937, 0.051937, 0.051937, 0.051937",\ + "0.176967, 0.176967, 0.176967, 0.176967, 0.176967",\ + "0.380998, 0.380998, 0.380998, 0.380998, 0.380998",\ + "0.885970, 0.885970, 0.885970, 0.885970, 0.885970",\ + "2.162331, 2.162331, 2.162331, 2.162331, 2.162331",\ + "0.051937, 0.051937, 0.051937, 0.051937, 0.051937",\ + "0.176967, 0.176967, 0.176967, 0.176967, 0.176967",\ + "0.380998, 0.380998, 0.380998, 0.380998, 0.380998",\ + "0.885970, 0.885970, 0.885970, 0.885970, 0.885970",\ + "2.162331, 2.162331, 2.162331, 2.162331, 2.162331",\ + "0.051937, 0.051937, 0.051937, 0.051937, 0.051937",\ + "0.176967, 0.176967, 0.176967, 0.176967, 0.176967",\ + "0.380998, 0.380998, 0.380998, 0.380998, 0.380998",\ + "0.885970, 0.885970, 0.885970, 0.885970, 0.885970",\ + "2.162331, 2.162331, 2.162331, 2.162331, 2.162331"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.716967, 0.971067, 1.253316, 1.722141, 2.659792",\ + "0.739318, 0.993418, 1.275667, 1.744492, 2.682143",\ + "0.780639, 1.034739, 1.316987, 1.785813, 2.723464",\ + "0.913612, 1.167712, 1.449961, 1.918786, 2.856437",\ + "1.262718, 1.516818, 1.799066, 2.267892, 3.205543",\ + "0.804375, 1.058661, 1.340881, 1.808856, 2.745726",\ + "0.826726, 1.081012, 1.363232, 1.831207, 2.768077",\ + "0.868047, 1.122332, 1.404552, 1.872527, 2.809398",\ + "1.001020, 1.255306, 1.537526, 2.005501, 2.942371",\ + "1.350126, 1.604411, 1.886632, 2.354606, 3.291477",\ + "0.885216, 1.147728, 1.428845, 1.896477, 2.832681",\ + "0.907567, 1.170079, 1.451195, 1.918828, 2.855032",\ + "0.948887, 1.211399, 1.492516, 1.960149, 2.896353",\ + "1.081861, 1.344373, 1.625489, 2.093122, 3.029326",\ + "1.430966, 1.693479, 1.974595, 2.442228, 3.378432",\ + "0.942857, 1.213488, 1.492984, 1.960390, 2.896190",\ + "0.965208, 1.235839, 1.515335, 1.982741, 2.918541",\ + "1.006528, 1.277159, 1.556656, 2.024062, 2.959862",\ + "1.139502, 1.410133, 1.689629, 2.157035, 3.092835",\ + "1.488607, 1.759238, 2.038735, 2.506141, 3.441941",\ + "1.275329, 1.579373, 1.844849, 2.309734, 3.241646",\ + "1.297680, 1.601724, 1.867200, 2.332085, 3.263997",\ + "1.339000, 1.643044, 1.908520, 2.373406, 3.305318",\ + "1.471974, 1.776018, 2.041493, 2.506379, 3.438291",\ + "1.821079, 2.125124, 2.390599, 2.855485, 3.787397"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.048201, 0.048201, 0.048201, 0.048201, 0.048201",\ + "0.098620, 0.098620, 0.098620, 0.098620, 0.098620",\ + "0.188783, 0.188783, 0.188783, 0.188783, 0.188783",\ + "0.444126, 0.444126, 0.444126, 0.444126, 0.444126",\ + "1.101816, 1.101816, 1.101816, 1.101816, 1.101816",\ + "0.048201, 0.048201, 0.048201, 0.048201, 0.048201",\ + "0.098620, 0.098620, 0.098620, 0.098620, 0.098620",\ + "0.188783, 0.188783, 0.188783, 0.188783, 0.188783",\ + "0.444126, 0.444126, 0.444126, 0.444126, 0.444126",\ + "1.101816, 1.101816, 1.101816, 1.101816, 1.101816",\ + "0.048201, 0.048201, 0.048201, 0.048201, 0.048201",\ + "0.098620, 0.098620, 0.098620, 0.098620, 0.098620",\ + "0.188783, 0.188783, 0.188783, 0.188783, 0.188783",\ + "0.444126, 0.444126, 0.444126, 0.444126, 0.444126",\ + "1.101816, 1.101816, 1.101816, 1.101816, 1.101816",\ + "0.048201, 0.048201, 0.048201, 0.048201, 0.048201",\ + "0.098620, 0.098620, 0.098620, 0.098620, 0.098620",\ + "0.188783, 0.188783, 0.188783, 0.188783, 0.188783",\ + "0.444126, 0.444126, 0.444126, 0.444126, 0.444126",\ + "1.101816, 1.101816, 1.101816, 1.101816, 1.101816",\ + "0.048201, 0.048201, 0.048201, 0.048201, 0.048201",\ + "0.098620, 0.098620, 0.098620, 0.098620, 0.098620",\ + "0.188783, 0.188783, 0.188783, 0.188783, 0.188783",\ + "0.444126, 0.444126, 0.444126, 0.444126, 0.444126",\ + "1.101816, 1.101816, 1.101816, 1.101816, 1.101816"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_2517*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[40]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.732857, 0.971343, 1.249163, 1.734893, 2.706354",\ + "0.779384, 1.017870, 1.295690, 1.781420, 2.752881",\ + "0.865018, 1.103504, 1.381324, 1.867054, 2.838515",\ + "1.088337, 1.326823, 1.604643, 2.090373, 3.061833",\ + "1.652282, 1.890768, 2.168588, 2.654318, 3.625778",\ + "0.820269, 1.058867, 1.336783, 1.821608, 2.792287",\ + "0.866797, 1.105394, 1.383311, 1.868135, 2.838814",\ + "0.952431, 1.191029, 1.468945, 1.953769, 2.924448",\ + "1.175750, 1.414347, 1.692263, 2.177088, 3.147767",\ + "1.739695, 1.978293, 2.256209, 2.741033, 3.711712",\ + "0.901137, 1.147799, 1.424749, 1.909230, 2.879242",\ + "0.947664, 1.194327, 1.471276, 1.955757, 2.925770",\ + "1.033299, 1.279961, 1.556910, 2.041391, 3.011404",\ + "1.256617, 1.503280, 1.780229, 2.264710, 3.234722",\ + "1.820563, 2.067225, 2.344174, 2.828655, 3.798667",\ + "0.958789, 1.213364, 1.488891, 1.973144, 2.942751",\ + "1.005316, 1.259891, 1.535418, 2.019671, 2.989279",\ + "1.090950, 1.345525, 1.621053, 2.105305, 3.074913",\ + "1.314269, 1.568844, 1.844371, 2.328624, 3.298231",\ + "1.878214, 2.132789, 2.408317, 2.892569, 3.862176",\ + "1.276921, 1.576900, 1.840930, 2.322562, 3.288208",\ + "1.323448, 1.623428, 1.887457, 2.369089, 3.334734",\ + "1.409082, 1.709062, 1.973091, 2.454723, 3.420369",\ + "1.632401, 1.932381, 2.196410, 2.678042, 3.643687",\ + "2.196346, 2.496326, 2.760355, 3.241987, 4.207632"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.052220, 0.052220, 0.052220, 0.052220, 0.052220",\ + "0.174408, 0.174408, 0.174408, 0.174408, 0.174408",\ + "0.378144, 0.378144, 0.378144, 0.378144, 0.378144",\ + "0.885509, 0.885509, 0.885509, 0.885508, 0.885506",\ + "2.163010, 2.163010, 2.163010, 2.163012, 2.163014",\ + "0.052220, 0.052220, 0.052220, 0.052220, 0.052220",\ + "0.174408, 0.174408, 0.174408, 0.174408, 0.174408",\ + "0.378144, 0.378144, 0.378144, 0.378144, 0.378144",\ + "0.885509, 0.885509, 0.885509, 0.885508, 0.885506",\ + "2.163010, 2.163010, 2.163010, 2.163012, 2.163014",\ + "0.052220, 0.052220, 0.052220, 0.052220, 0.052220",\ + "0.174408, 0.174408, 0.174408, 0.174408, 0.174408",\ + "0.378144, 0.378144, 0.378144, 0.378144, 0.378144",\ + "0.885509, 0.885509, 0.885509, 0.885508, 0.885506",\ + "2.163010, 2.163010, 2.163010, 2.163012, 2.163014",\ + "0.052220, 0.052220, 0.052220, 0.052220, 0.052220",\ + "0.174408, 0.174408, 0.174408, 0.174408, 0.174408",\ + "0.378144, 0.378144, 0.378144, 0.378144, 0.378144",\ + "0.885509, 0.885509, 0.885509, 0.885508, 0.885506",\ + "2.163010, 2.163010, 2.163010, 2.163012, 2.163014",\ + "0.052220, 0.052220, 0.052220, 0.052220, 0.052220",\ + "0.174408, 0.174408, 0.174408, 0.174408, 0.174408",\ + "0.378144, 0.378144, 0.378144, 0.378144, 0.378144",\ + "0.885509, 0.885509, 0.885509, 0.885508, 0.885506",\ + "2.163010, 2.163010, 2.163010, 2.163012, 2.163014"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.671243, 0.909729, 1.187549, 1.673279, 2.644740",\ + "0.724532, 0.963018, 1.240838, 1.726568, 2.698029",\ + "0.785280, 1.023767, 1.301586, 1.787316, 2.758777",\ + "0.919992, 1.158478, 1.436297, 1.922028, 2.893488",\ + "1.266500, 1.504986, 1.782806, 2.268536, 3.239997",\ + "0.758655, 0.997253, 1.275169, 1.759994, 2.730674",\ + "0.811945, 1.050542, 1.328459, 1.813283, 2.783962",\ + "0.872693, 1.111291, 1.389207, 1.874031, 2.844710",\ + "1.007404, 1.246002, 1.523918, 2.008743, 2.979422",\ + "1.353913, 1.592511, 1.870427, 2.355251, 3.325931",\ + "0.839523, 1.086185, 1.363135, 1.847616, 2.817629",\ + "0.892813, 1.139475, 1.416424, 1.900905, 2.870918",\ + "0.953561, 1.200223, 1.477172, 1.961653, 2.931665",\ + "1.088272, 1.334934, 1.611884, 2.096365, 3.066377",\ + "1.434781, 1.681443, 1.958392, 2.442873, 3.412886",\ + "0.897175, 1.151750, 1.427277, 1.911530, 2.881138",\ + "0.950464, 1.205039, 1.480567, 1.964819, 2.934427",\ + "1.011212, 1.265788, 1.541315, 2.025567, 2.995174",\ + "1.145923, 1.400499, 1.676026, 2.160278, 3.129886",\ + "1.492432, 1.747007, 2.022535, 2.506787, 3.476395",\ + "1.215307, 1.515286, 1.779316, 2.260948, 3.226594",\ + "1.268596, 1.568576, 1.832605, 2.314237, 3.279882",\ + "1.329345, 1.629324, 1.893353, 2.374985, 3.340631",\ + "1.464056, 1.764035, 2.028064, 2.509696, 3.475342",\ + "1.810564, 2.110544, 2.374573, 2.856205, 3.821851"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.060037, 0.060037, 0.060037, 0.060037, 0.060036",\ + "0.113989, 0.113989, 0.113989, 0.113989, 0.113988",\ + "0.199694, 0.199694, 0.199694, 0.199693, 0.199693",\ + "0.445487, 0.445487, 0.445487, 0.445487, 0.445487",\ + "1.101436, 1.101436, 1.101436, 1.101436, 1.101436",\ + "0.060037, 0.060037, 0.060037, 0.060037, 0.060036",\ + "0.113989, 0.113989, 0.113989, 0.113989, 0.113988",\ + "0.199694, 0.199694, 0.199694, 0.199693, 0.199693",\ + "0.445487, 0.445487, 0.445487, 0.445487, 0.445487",\ + "1.101436, 1.101436, 1.101436, 1.101436, 1.101436",\ + "0.060037, 0.060037, 0.060037, 0.060037, 0.060036",\ + "0.113989, 0.113989, 0.113989, 0.113989, 0.113988",\ + "0.199694, 0.199694, 0.199694, 0.199693, 0.199693",\ + "0.445487, 0.445487, 0.445487, 0.445487, 0.445487",\ + "1.101436, 1.101436, 1.101436, 1.101436, 1.101436",\ + "0.060037, 0.060037, 0.060037, 0.060037, 0.060036",\ + "0.113989, 0.113989, 0.113989, 0.113989, 0.113988",\ + "0.199694, 0.199694, 0.199694, 0.199693, 0.199693",\ + "0.445487, 0.445487, 0.445487, 0.445487, 0.445487",\ + "1.101436, 1.101436, 1.101436, 1.101436, 1.101436",\ + "0.060037, 0.060037, 0.060037, 0.060037, 0.060036",\ + "0.113989, 0.113989, 0.113989, 0.113989, 0.113988",\ + "0.199694, 0.199694, 0.199694, 0.199693, 0.199693",\ + "0.445487, 0.445487, 0.445487, 0.445487, 0.445487",\ + "1.101436, 1.101436, 1.101436, 1.101436, 1.101436"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_2654*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[46]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.687805, 0.938142, 1.214956, 1.708122, 2.694454",\ + "0.734333, 0.984670, 1.261485, 1.754655, 2.740993",\ + "0.819969, 1.070307, 1.347124, 1.840302, 2.826659",\ + "1.043291, 1.293629, 1.570450, 2.063643, 3.050026",\ + "1.607241, 1.857579, 2.134405, 2.627615, 3.614036",\ + "0.775217, 1.025647, 1.302601, 1.794837, 2.780388",\ + "0.821745, 1.072175, 1.349129, 1.841369, 2.826927",\ + "0.907382, 1.157812, 1.434768, 1.927017, 2.912592",\ + "1.130704, 1.381134, 1.658095, 2.150357, 3.135960",\ + "1.694654, 1.945083, 2.222049, 2.714330, 3.699970",\ + "0.856074, 1.114534, 1.390566, 1.882460, 2.867343",\ + "0.902602, 1.161062, 1.437095, 1.928992, 2.913882",\ + "0.988238, 1.246698, 1.522734, 2.014640, 2.999547",\ + "1.211560, 1.470021, 1.746060, 2.237980, 3.222915",\ + "1.775510, 2.033970, 2.310015, 2.801953, 3.786925",\ + "0.913872, 1.180032, 1.454710, 1.946373, 2.930852",\ + "0.960400, 1.226560, 1.501239, 1.992905, 2.977391",\ + "1.046036, 1.312197, 1.586878, 2.078553, 3.063056",\ + "1.269358, 1.535519, 1.810204, 2.301893, 3.286424",\ + "1.833308, 2.099468, 2.374159, 2.865866, 3.850434",\ + "1.246728, 1.542797, 1.806824, 2.295822, 3.276308",\ + "1.293256, 1.589325, 1.853353, 2.342354, 3.322847",\ + "1.378892, 1.674961, 1.938992, 2.428002, 3.408513",\ + "1.602214, 1.898283, 2.162318, 2.651342, 3.631880",\ + "2.166164, 2.462233, 2.726274, 3.215315, 4.195890"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.052222, 0.052222, 0.052225, 0.052234, 0.052252",\ + "0.174407, 0.174407, 0.174405, 0.174399, 0.174386",\ + "0.378140, 0.378140, 0.378136, 0.378121, 0.378092",\ + "0.885509, 0.885509, 0.885508, 0.885504, 0.885495",\ + "2.163010, 2.163010, 2.163012, 2.163018, 2.163031",\ + "0.052222, 0.052222, 0.052225, 0.052234, 0.052252",\ + "0.174407, 0.174407, 0.174405, 0.174399, 0.174386",\ + "0.378140, 0.378140, 0.378136, 0.378121, 0.378092",\ + "0.885509, 0.885509, 0.885508, 0.885504, 0.885495",\ + "2.163010, 2.163010, 2.163012, 2.163018, 2.163031",\ + "0.052222, 0.052222, 0.052225, 0.052234, 0.052252",\ + "0.174407, 0.174407, 0.174405, 0.174399, 0.174386",\ + "0.378140, 0.378140, 0.378136, 0.378121, 0.378092",\ + "0.885509, 0.885509, 0.885508, 0.885504, 0.885495",\ + "2.163010, 2.163010, 2.163012, 2.163018, 2.163031",\ + "0.052222, 0.052222, 0.052225, 0.052234, 0.052252",\ + "0.174407, 0.174407, 0.174405, 0.174399, 0.174386",\ + "0.378140, 0.378140, 0.378136, 0.378121, 0.378092",\ + "0.885509, 0.885509, 0.885508, 0.885504, 0.885495",\ + "2.163010, 2.163010, 2.163012, 2.163018, 2.163031",\ + "0.052222, 0.052222, 0.052225, 0.052234, 0.052252",\ + "0.174407, 0.174407, 0.174405, 0.174399, 0.174386",\ + "0.378140, 0.378140, 0.378136, 0.378121, 0.378092",\ + "0.885509, 0.885509, 0.885508, 0.885504, 0.885495",\ + "2.163010, 2.163010, 2.163012, 2.163018, 2.163031"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.626180, 0.876518, 1.153319, 1.646441, 2.632685",\ + "0.679480, 0.929817, 1.206631, 1.699795, 2.686123",\ + "0.740236, 0.990574, 1.267397, 1.760594, 2.746988",\ + "0.874947, 1.125284, 1.402106, 1.895301, 2.881690",\ + "1.221451, 1.471789, 1.748606, 2.241784, 3.228139",\ + "0.713593, 0.964022, 1.240963, 1.733156, 2.718619",\ + "0.766892, 1.017322, 1.294275, 1.786510, 2.772057",\ + "0.827649, 1.078079, 1.355041, 1.847309, 2.832922",\ + "0.962359, 1.212789, 1.489751, 1.982016, 2.967624",\ + "1.308864, 1.559294, 1.836250, 2.328499, 3.314073",\ + "0.794449, 1.052909, 1.328929, 1.820778, 2.805574",\ + "0.847749, 1.106209, 1.382241, 1.874132, 2.859012",\ + "0.908505, 1.166965, 1.443007, 1.934931, 2.919877",\ + "1.043216, 1.301676, 1.577716, 2.069638, 3.054579",\ + "1.389720, 1.648180, 1.924216, 2.416121, 3.401028",\ + "0.852247, 1.118408, 1.393072, 1.884692, 2.869083",\ + "0.905546, 1.171707, 1.446384, 1.938046, 2.922521",\ + "0.966303, 1.232464, 1.507150, 1.998845, 2.983386",\ + "1.101013, 1.367174, 1.641860, 2.133552, 3.118088",\ + "1.447518, 1.713679, 1.988360, 2.480035, 3.464537",\ + "1.185103, 1.481172, 1.745186, 2.234141, 3.214539",\ + "1.238403, 1.534472, 1.798498, 2.287495, 3.267977",\ + "1.299159, 1.595228, 1.859265, 2.348294, 3.328842",\ + "1.433870, 1.729939, 1.993974, 2.483001, 3.463544",\ + "1.780374, 2.076443, 2.340474, 2.829484, 3.809993"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.060053, 0.060053, 0.060071, 0.060133, 0.060259",\ + "0.114010, 0.114010, 0.114035, 0.114122, 0.114295",\ + "0.199713, 0.199713, 0.199736, 0.199815, 0.199972",\ + "0.445490, 0.445490, 0.445492, 0.445501, 0.445519",\ + "1.101435, 1.101435, 1.101434, 1.101430, 1.101422",\ + "0.060053, 0.060053, 0.060071, 0.060133, 0.060259",\ + "0.114010, 0.114010, 0.114035, 0.114122, 0.114295",\ + "0.199713, 0.199713, 0.199736, 0.199815, 0.199972",\ + "0.445490, 0.445490, 0.445492, 0.445501, 0.445519",\ + "1.101435, 1.101435, 1.101434, 1.101430, 1.101422",\ + "0.060053, 0.060053, 0.060071, 0.060133, 0.060259",\ + "0.114010, 0.114010, 0.114035, 0.114122, 0.114295",\ + "0.199713, 0.199713, 0.199736, 0.199815, 0.199972",\ + "0.445490, 0.445490, 0.445492, 0.445501, 0.445519",\ + "1.101435, 1.101435, 1.101434, 1.101430, 1.101422",\ + "0.060053, 0.060053, 0.060071, 0.060133, 0.060259",\ + "0.114010, 0.114010, 0.114036, 0.114122, 0.114295",\ + "0.199713, 0.199713, 0.199736, 0.199815, 0.199972",\ + "0.445490, 0.445490, 0.445492, 0.445501, 0.445519",\ + "1.101435, 1.101435, 1.101434, 1.101430, 1.101422",\ + "0.060053, 0.060053, 0.060071, 0.060134, 0.060259",\ + "0.114010, 0.114010, 0.114036, 0.114122, 0.114295",\ + "0.199713, 0.199713, 0.199737, 0.199815, 0.199972",\ + "0.445490, 0.445490, 0.445492, 0.445501, 0.445519",\ + "1.101435, 1.101435, 1.101434, 1.101430, 1.101422"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_2645*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[17]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011"); + values ( "0.486994, 0.689024, 0.898048, 1.222707, 1.844099",\ + "0.536854, 0.738884, 0.947908, 1.272568, 1.893960",\ + "0.638722, 0.840752, 1.049776, 1.374436, 1.995828",\ + "0.876584, 1.078614, 1.287637, 1.612297, 2.233689",\ + "1.448904, 1.650934, 1.859958, 2.184618, 2.806009",\ + "0.575735, 0.776343, 0.985328, 1.310012, 1.931453",\ + "0.625596, 0.826203, 1.035189, 1.359873, 1.981313",\ + "0.727464, 0.928071, 1.137057, 1.461741, 2.083181",\ + "0.965325, 1.165933, 1.374918, 1.699602, 2.321043",\ + "1.537645, 1.738253, 1.947239, 2.271923, 2.893363",\ + "0.665418, 0.856680, 1.065355, 1.390041, 2.011484",\ + "0.715279, 0.906541, 1.115216, 1.439901, 2.061345",\ + "0.817147, 1.008409, 1.217084, 1.541770, 2.163213",\ + "1.055008, 1.246270, 1.454945, 1.779631, 2.401074",\ + "1.627329, 1.818590, 2.027266, 2.351951, 2.973394",\ + "0.724126, 0.914549, 1.123120, 1.447544, 2.068644",\ + "0.773987, 0.964410, 1.172981, 1.497404, 2.118505",\ + "0.875855, 1.066278, 1.274849, 1.599272, 2.220373",\ + "1.113716, 1.304139, 1.512710, 1.837134, 2.458234",\ + "1.686036, 1.876459, 2.085031, 2.409454, 3.030555",\ + "1.026901, 1.220157, 1.426788, 1.750778, 2.371040",\ + "1.076761, 1.270018, 1.476649, 1.800639, 2.420901",\ + "1.178629, 1.371886, 1.578517, 1.902507, 2.522769",\ + "1.416491, 1.609747, 1.816378, 2.140368, 2.760630",\ + "1.988811, 2.182067, 2.388699, 2.712689, 3.332951"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011"); + values ( "0.039800, 0.039800, 0.039800, 0.039800, 0.039800",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375010, 0.375010, 0.375010, 0.375010, 0.375010",\ + "0.869309, 0.869309, 0.869309, 0.869309, 0.869309",\ + "2.137202, 2.137202, 2.137202, 2.137202, 2.137202",\ + "0.039800, 0.039800, 0.039800, 0.039800, 0.039800",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375010, 0.375010, 0.375010, 0.375010, 0.375010",\ + "0.869309, 0.869309, 0.869309, 0.869309, 0.869309",\ + "2.137202, 2.137202, 2.137202, 2.137202, 2.137202",\ + "0.039800, 0.039800, 0.039800, 0.039800, 0.039800",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375010, 0.375010, 0.375010, 0.375010, 0.375010",\ + "0.869309, 0.869309, 0.869309, 0.869309, 0.869309",\ + "2.137202, 2.137202, 2.137202, 2.137202, 2.137202",\ + "0.039800, 0.039800, 0.039800, 0.039800, 0.039800",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375010, 0.375010, 0.375010, 0.375010, 0.375010",\ + "0.869309, 0.869309, 0.869309, 0.869309, 0.869309",\ + "2.137202, 2.137202, 2.137202, 2.137202, 2.137202",\ + "0.039800, 0.039800, 0.039800, 0.039800, 0.039800",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375010, 0.375010, 0.375010, 0.375010, 0.375010",\ + "0.869309, 0.869309, 0.869309, 0.869309, 0.869309",\ + "2.137202, 2.137202, 2.137202, 2.137202, 2.137202"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011"); + values ( "0.527722, 0.729752, 0.938776, 1.263436, 1.884828",\ + "0.550072, 0.752102, 0.961126, 1.285786, 1.907177",\ + "0.591435, 0.793465, 1.002489, 1.327149, 1.948541",\ + "0.713471, 0.915501, 1.124525, 1.449185, 2.070576",\ + "1.045084, 1.247114, 1.456138, 1.780797, 2.402189",\ + "0.616463, 0.817071, 1.026057, 1.350741, 1.972181",\ + "0.638813, 0.839421, 1.048407, 1.373091, 1.994531",\ + "0.680177, 0.880784, 1.089770, 1.414454, 2.035894",\ + "0.802212, 1.002820, 1.211806, 1.536490, 2.157930",\ + "1.133825, 1.334433, 1.543419, 1.868103, 2.489543",\ + "0.706147, 0.897409, 1.106084, 1.430769, 2.052213",\ + "0.728497, 0.919758, 1.128434, 1.453119, 2.074563",\ + "0.769860, 0.961122, 1.169797, 1.494483, 2.115926",\ + "0.891896, 1.083158, 1.291833, 1.616518, 2.237962",\ + "1.223509, 1.414770, 1.623446, 1.948131, 2.569574",\ + "0.764855, 0.955278, 1.163849, 1.488272, 2.109373",\ + "0.787204, 0.977627, 1.186199, 1.510622, 2.131722",\ + "0.828568, 1.018991, 1.227562, 1.551985, 2.173086",\ + "0.950603, 1.141026, 1.349598, 1.674021, 2.295122",\ + "1.282216, 1.472639, 1.681211, 2.005634, 2.626734",\ + "1.067629, 1.260886, 1.467517, 1.791507, 2.411769",\ + "1.089979, 1.283235, 1.489867, 1.813857, 2.434119",\ + "1.131342, 1.324599, 1.531230, 1.855220, 2.475482",\ + "1.253378, 1.446635, 1.653266, 1.977256, 2.597517",\ + "1.584991, 1.778247, 1.984879, 2.308869, 2.929131"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011"); + values ( "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\ + "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\ + "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\ + "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\ + "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_min_2543*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[19]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011"); + values ( "0.402983, 0.589298, 0.781819, 1.078308, 1.645139",\ + "0.452846, 0.639161, 0.831682, 1.128171, 1.695002",\ + "0.554714, 0.741029, 0.933550, 1.230039, 1.796870",\ + "0.792575, 0.978890, 1.171412, 1.467901, 2.034731",\ + "1.364896, 1.551211, 1.743732, 2.040221, 2.607052",\ + "0.491182, 0.676616, 0.869099, 1.165613, 1.732492",\ + "0.541046, 0.726479, 0.918963, 1.215477, 1.782355",\ + "0.642913, 0.828347, 1.020831, 1.317344, 1.884223",\ + "0.880775, 1.066208, 1.258693, 1.555206, 2.122085",\ + "1.453095, 1.638529, 1.831013, 2.127527, 2.694405",\ + "0.578213, 0.756948, 0.949126, 1.245641, 1.812524",\ + "0.628077, 0.806812, 0.998990, 1.295505, 1.862387",\ + "0.729944, 0.908679, 1.100858, 1.397373, 1.964255",\ + "0.967806, 1.146541, 1.338719, 1.635234, 2.202116",\ + "1.540126, 1.718862, 1.911040, 2.207555, 2.774437",\ + "0.635881, 0.814778, 1.006854, 1.303079, 1.869555",\ + "0.685744, 0.864642, 1.056718, 1.352942, 1.919418",\ + "0.787612, 0.966509, 1.158586, 1.454810, 2.021286",\ + "1.025473, 1.204371, 1.396447, 1.692672, 2.259147",\ + "1.597794, 1.776692, 1.968768, 2.264992, 2.831468",\ + "0.938596, 1.120091, 1.310515, 1.606257, 2.171795",\ + "0.988459, 1.169954, 1.360379, 1.656120, 2.221658",\ + "1.090327, 1.271822, 1.462247, 1.757988, 2.323526",\ + "1.328188, 1.509683, 1.700108, 1.995849, 2.561387",\ + "1.900509, 2.082004, 2.272429, 2.568170, 3.133708"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011"); + values ( "0.039806, 0.039806, 0.039806, 0.039805, 0.039804",\ + "0.147771, 0.147771, 0.147771, 0.147771, 0.147770",\ + "0.375009, 0.375009, 0.375009, 0.375009, 0.375009",\ + "0.869292, 0.869292, 0.869292, 0.869292, 0.869292",\ + "2.137192, 2.137192, 2.137192, 2.137192, 2.137192",\ + "0.039806, 0.039806, 0.039806, 0.039805, 0.039804",\ + "0.147771, 0.147771, 0.147771, 0.147771, 0.147770",\ + "0.375009, 0.375009, 0.375009, 0.375009, 0.375009",\ + "0.869292, 0.869292, 0.869292, 0.869292, 0.869292",\ + "2.137192, 2.137192, 2.137192, 2.137192, 2.137192",\ + "0.039806, 0.039806, 0.039806, 0.039805, 0.039804",\ + "0.147771, 0.147771, 0.147771, 0.147771, 0.147770",\ + "0.375009, 0.375009, 0.375009, 0.375009, 0.375009",\ + "0.869292, 0.869292, 0.869292, 0.869292, 0.869292",\ + "2.137192, 2.137192, 2.137192, 2.137192, 2.137192",\ + "0.039806, 0.039806, 0.039806, 0.039805, 0.039804",\ + "0.147771, 0.147771, 0.147771, 0.147771, 0.147770",\ + "0.375009, 0.375009, 0.375009, 0.375009, 0.375009",\ + "0.869292, 0.869292, 0.869292, 0.869292, 0.869292",\ + "2.137192, 2.137192, 2.137192, 2.137192, 2.137192",\ + "0.039806, 0.039806, 0.039806, 0.039805, 0.039804",\ + "0.147771, 0.147771, 0.147771, 0.147771, 0.147770",\ + "0.375009, 0.375009, 0.375009, 0.375009, 0.375009",\ + "0.869292, 0.869292, 0.869292, 0.869292, 0.869292",\ + "2.137192, 2.137192, 2.137192, 2.137192, 2.137192"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011"); + values ( "0.423040, 0.630029, 0.815796, 1.107776, 1.669457",\ + "0.466065, 0.652380, 0.844901, 1.141390, 1.708220",\ + "0.507428, 0.693743, 0.886264, 1.182753, 1.749583",\ + "0.629463, 0.815778, 1.008300, 1.304789, 1.871619",\ + "0.961076, 1.147391, 1.339912, 1.636401, 2.203231",\ + "0.511411, 0.717348, 0.903077, 1.195081, 1.756810",\ + "0.554264, 0.739698, 0.932182, 1.228695, 1.795574",\ + "0.595627, 0.781061, 0.973545, 1.270058, 1.836937",\ + "0.717663, 0.903096, 1.095581, 1.392094, 1.958972",\ + "1.049275, 1.234709, 1.427193, 1.723706, 2.290585",\ + "0.600722, 0.797680, 0.983104, 1.275110, 1.836842",\ + "0.641295, 0.820030, 1.012209, 1.308724, 1.875605",\ + "0.682658, 0.861393, 1.053572, 1.350087, 1.916969",\ + "0.804694, 0.983429, 1.175608, 1.472122, 2.039004",\ + "1.136306, 1.315041, 1.507220, 1.803735, 2.370616",\ + "0.664349, 0.855510, 1.040816, 1.332541, 1.893861",\ + "0.698963, 0.877860, 1.069937, 1.366161, 1.932636",\ + "0.740326, 0.919223, 1.111300, 1.407524, 1.974000",\ + "0.862361, 1.041259, 1.233335, 1.529560, 2.096035",\ + "1.193974, 1.372871, 1.564948, 1.861172, 2.427648",\ + "0.979328, 1.160823, 1.344474, 1.635713, 2.196086",\ + "1.001678, 1.183173, 1.373598, 1.669339, 2.234876",\ + "1.043041, 1.224536, 1.414961, 1.710702, 2.276240",\ + "1.165076, 1.346571, 1.536997, 1.832738, 2.398275",\ + "1.496689, 1.678184, 1.868609, 2.164350, 2.729888"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011"); + values ( "0.045855, 0.045855, 0.045855, 0.045855, 0.045855",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\ + "0.045855, 0.045855, 0.045855, 0.045855, 0.045855",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\ + "0.045855, 0.045855, 0.045855, 0.045855, 0.045855",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\ + "0.045855, 0.045855, 0.045855, 0.045855, 0.045855",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\ + "0.045855, 0.045855, 0.045855, 0.045855, 0.045855",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_min_2604*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[21]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011"); + values ( "0.374729, 0.574327, 0.761134, 1.059803, 1.637058",\ + "0.424592, 0.624191, 0.810999, 1.109666, 1.686921",\ + "0.526460, 0.726059, 0.912867, 1.211534, 1.788789",\ + "0.764322, 0.963920, 1.150728, 1.449396, 2.026650",\ + "1.336642, 1.536241, 1.723049, 2.021717, 2.598970",\ + "0.463046, 0.661644, 0.848415, 1.147108, 1.724412",\ + "0.512909, 0.711509, 0.898280, 1.196972, 1.774274",\ + "0.614777, 0.813377, 1.000148, 1.298839, 1.876142",\ + "0.852638, 1.051238, 1.238009, 1.536701, 2.114003",\ + "1.424959, 1.623559, 1.810330, 2.109022, 2.686324",\ + "0.552645, 0.741973, 0.928442, 1.227136, 1.804443",\ + "0.602508, 0.791838, 0.978307, 1.277000, 1.854306",\ + "0.704376, 0.893705, 1.080175, 1.378868, 1.956174",\ + "0.942238, 1.131567, 1.318036, 1.616729, 2.194035",\ + "1.514558, 1.703888, 1.890357, 2.189050, 2.766356",\ + "0.616737, 0.799794, 0.986158, 1.284587, 1.861501",\ + "0.666600, 0.849659, 1.036023, 1.334451, 1.911364",\ + "0.768468, 0.951526, 1.137890, 1.436318, 2.013232",\ + "1.006329, 1.189388, 1.375752, 1.674180, 2.251093",\ + "1.578650, 1.761709, 1.948073, 2.246500, 2.823413",\ + "0.927115, 1.105032, 1.289816, 1.587775, 2.163774",\ + "0.976978, 1.154897, 1.339680, 1.637639, 2.213636",\ + "1.078846, 1.256764, 1.441548, 1.739507, 2.315504",\ + "1.316707, 1.494626, 1.679409, 1.977368, 2.553366",\ + "1.889028, 2.066947, 2.251730, 2.549689, 3.125686"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011"); + values ( "0.039798, 0.039798, 0.039798, 0.039798, 0.039798",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375008, 0.375008, 0.375009, 0.375009, 0.375009",\ + "0.869292, 0.869292, 0.869292, 0.869292, 0.869292",\ + "2.137192, 2.137192, 2.137192, 2.137192, 2.137192",\ + "0.039798, 0.039798, 0.039798, 0.039798, 0.039798",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375008, 0.375008, 0.375009, 0.375009, 0.375009",\ + "0.869292, 0.869292, 0.869292, 0.869292, 0.869292",\ + "2.137192, 2.137192, 2.137192, 2.137192, 2.137192",\ + "0.039798, 0.039798, 0.039798, 0.039798, 0.039798",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375008, 0.375008, 0.375009, 0.375009, 0.375009",\ + "0.869292, 0.869292, 0.869292, 0.869292, 0.869292",\ + "2.137192, 2.137192, 2.137192, 2.137192, 2.137192",\ + "0.039798, 0.039798, 0.039798, 0.039798, 0.039798",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375008, 0.375008, 0.375009, 0.375009, 0.375009",\ + "0.869292, 0.869292, 0.869292, 0.869292, 0.869292",\ + "2.137192, 2.137192, 2.137192, 2.137192, 2.137192",\ + "0.039798, 0.039798, 0.039798, 0.039798, 0.039798",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375008, 0.375008, 0.375009, 0.375009, 0.375009",\ + "0.869292, 0.869292, 0.869292, 0.869292, 0.869292",\ + "2.137192, 2.137192, 2.137192, 2.137192, 2.137192"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011"); + values ( "0.405230, 0.615060, 0.801868, 1.100535, 1.677789",\ + "0.437811, 0.637410, 0.824218, 1.122885, 1.700139",\ + "0.479174, 0.678774, 0.865581, 1.164248, 1.741502",\ + "0.601210, 0.800809, 0.987617, 1.286284, 1.863538",\ + "0.932822, 1.132421, 1.319229, 1.617896, 2.195150",\ + "0.493512, 0.702378, 0.889149, 1.187840, 1.765142",\ + "0.526127, 0.724728, 0.911499, 1.210190, 1.787492",\ + "0.567491, 0.766091, 0.952862, 1.251554, 1.828856",\ + "0.689526, 0.888126, 1.074898, 1.373589, 1.950891",\ + "1.021139, 1.219739, 1.406510, 1.705201, 2.282504",\ + "0.583007, 0.782706, 0.969176, 1.267869, 1.845174",\ + "0.615727, 0.805056, 0.991526, 1.290219, 1.867524",\ + "0.657090, 0.846420, 1.032889, 1.331582, 1.908887",\ + "0.779126, 0.968455, 1.154925, 1.453618, 2.030923",\ + "1.110738, 1.300067, 1.486537, 1.785230, 2.362535",\ + "0.646999, 0.840528, 1.026891, 1.325319, 1.902232",\ + "0.679819, 0.862878, 1.049241, 1.347669, 1.924582",\ + "0.721182, 0.904241, 1.090605, 1.389032, 1.965945",\ + "0.843217, 1.026276, 1.212640, 1.511068, 2.087981",\ + "1.174830, 1.357889, 1.544252, 1.842680, 2.419593",\ + "0.967847, 1.145766, 1.330549, 1.628508, 2.204504",\ + "0.990197, 1.168116, 1.352899, 1.650858, 2.226855",\ + "1.031560, 1.209479, 1.394262, 1.692221, 2.268218",\ + "1.153596, 1.331514, 1.516298, 1.814256, 2.390253",\ + "1.485208, 1.663126, 1.847910, 2.145869, 2.721866"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011"); + values ( "0.045855, 0.045855, 0.045855, 0.045855, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\ + "0.045855, 0.045855, 0.045855, 0.045855, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\ + "0.045855, 0.045855, 0.045855, 0.045855, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\ + "0.045855, 0.045855, 0.045855, 0.045855, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\ + "0.045855, 0.045855, 0.045855, 0.045855, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_min_2705*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[23]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011"); + values ( "0.222114, 0.403093, 0.604570, 0.931647, 1.565679",\ + "0.278140, 0.457431, 0.657946, 0.989844, 1.636478",\ + "0.353958, 0.531643, 0.731437, 1.068535, 1.728488",\ + "0.556156, 0.731457, 0.928039, 1.271464, 1.949653",\ + "1.100796, 1.274143, 1.466860, 1.814002, 2.504620",\ + "0.309523, 0.490411, 0.691851, 1.018952, 1.653032",\ + "0.365549, 0.544749, 0.745227, 1.077150, 1.723831",\ + "0.441367, 0.618961, 0.818717, 1.155840, 1.815842",\ + "0.643566, 0.818775, 1.015320, 1.358769, 2.037007",\ + "1.188205, 1.361462, 1.554141, 1.901307, 2.591974",\ + "0.390388, 0.570744, 0.771878, 1.098981, 1.733064",\ + "0.446403, 0.625082, 0.825254, 1.157178, 1.803863",\ + "0.522211, 0.699294, 0.898744, 1.235869, 1.895873",\ + "0.724394, 0.899108, 1.095347, 1.438797, 2.117038",\ + "1.269020, 1.441795, 1.634168, 1.981336, 2.672005",\ + "0.448070, 0.628579, 0.829627, 1.156500, 1.790257",\ + "0.504064, 0.682912, 0.883001, 1.214712, 1.861086",\ + "0.579852, 0.757117, 0.956490, 1.293419, 1.953129",\ + "0.782005, 0.956923, 1.153085, 1.496370, 2.174338",\ + "1.326607, 1.499602, 1.691897, 2.038924, 2.729335",\ + "0.750884, 0.933934, 1.133292, 1.459748, 2.092693",\ + "0.806686, 0.988222, 1.186665, 1.517973, 2.163558",\ + "0.882290, 1.062385, 1.260154, 1.596694, 2.255640",\ + "1.084171, 1.262128, 1.456748, 1.799664, 2.476902",\ + "1.628551, 1.804755, 1.995558, 2.342230, 3.031935"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011"); + values ( "0.149901, 0.149901, 0.154272, 0.175587, 0.224039",\ + "0.237266, 0.237266, 0.240202, 0.254165, 0.285843",\ + "0.399712, 0.400490, 0.400737, 0.406993, 0.422155",\ + "0.873536, 0.873536, 0.873536, 0.874623, 0.877289",\ + "2.137324, 2.139116, 2.139203, 2.139986, 2.141907",\ + "0.149901, 0.149901, 0.154272, 0.175587, 0.224039",\ + "0.237266, 0.237266, 0.240202, 0.254165, 0.285843",\ + "0.399712, 0.400490, 0.400737, 0.406993, 0.422155",\ + "0.873536, 0.873536, 0.873536, 0.874623, 0.877289",\ + "2.137324, 2.139116, 2.139203, 2.139986, 2.141907",\ + "0.149901, 0.149901, 0.154272, 0.175587, 0.224039",\ + "0.237266, 0.237266, 0.240202, 0.254165, 0.285843",\ + "0.399717, 0.400490, 0.400737, 0.406993, 0.422155",\ + "0.873536, 0.873536, 0.873536, 0.874623, 0.877289",\ + "2.137336, 2.139116, 2.139203, 2.139986, 2.141907",\ + "0.149901, 0.149901, 0.154282, 0.175646, 0.224156",\ + "0.237266, 0.237266, 0.240209, 0.254204, 0.285920",\ + "0.399727, 0.400493, 0.400738, 0.407012, 0.422192",\ + "0.873536, 0.873536, 0.873536, 0.874626, 0.877296",\ + "2.137358, 2.139123, 2.139203, 2.139988, 2.141912",\ + "0.149901, 0.149901, 0.154284, 0.175697, 0.224297",\ + "0.237266, 0.237266, 0.240210, 0.254237, 0.286012",\ + "0.399816, 0.400514, 0.400738, 0.407027, 0.422236",\ + "0.873536, 0.873536, 0.873536, 0.874629, 0.877303",\ + "2.137563, 2.139170, 2.139203, 2.139990, 2.141917"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011"); + values ( "0.146813, 0.421543, 0.619073, 0.936497, 1.550523",\ + "0.182955, 0.455962, 0.653305, 0.972716, 1.591584",\ + "0.237642, 0.505732, 0.702816, 1.023104, 1.644353",\ + "0.371091, 0.634162, 0.830900, 1.151008, 1.772115",\ + "0.705966, 0.969914, 1.166368, 1.485322, 2.103856",\ + "0.235216, 0.509090, 0.706354, 1.023802, 1.637876",\ + "0.271333, 0.543280, 0.740586, 1.060021, 1.678937",\ + "0.325990, 0.593050, 0.790097, 1.110409, 1.731706",\ + "0.459423, 0.721480, 0.918180, 1.238313, 1.859468",\ + "0.794276, 1.057232, 1.253649, 1.572627, 2.191210",\ + "0.324565, 0.589422, 0.786381, 1.103830, 1.717908",\ + "0.360611, 0.623613, 0.820613, 1.140050, 1.758969",\ + "0.415179, 0.673383, 0.870124, 1.190438, 1.811738",\ + "0.548565, 0.801813, 0.998207, 1.318341, 1.939500",\ + "0.883356, 1.137565, 1.333676, 1.652655, 2.271241",\ + "0.388205, 0.647259, 0.844120, 1.161325, 1.775052",\ + "0.424183, 0.681450, 0.878352, 1.197550, 1.816125",\ + "0.478670, 0.731220, 0.927863, 1.247941, 1.868900",\ + "0.612012, 0.859650, 1.055945, 1.375844, 1.996662",\ + "0.946745, 1.195402, 1.391413, 1.710155, 2.328397",\ + "0.724572, 0.952620, 1.147783, 1.464552, 2.077430",\ + "0.760125, 0.986813, 1.182015, 1.500782, 2.118517",\ + "0.814091, 1.036585, 1.231526, 1.551176, 2.171298",\ + "0.947154, 1.165011, 1.359608, 1.679079, 2.299060",\ + "1.281518, 1.500770, 1.695075, 2.013387, 2.630787"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011"); + values ( "0.071550, 0.074340, 0.076398, 0.092998, 0.129684",\ + "0.104996, 0.104996, 0.106760, 0.117958, 0.143880",\ + "0.191043, 0.191210, 0.191730, 0.197481, 0.211138",\ + "0.431517, 0.431517, 0.431517, 0.433284, 0.437618",\ + "1.064302, 1.065326, 1.065376, 1.065376, 1.065376",\ + "0.071556, 0.071791, 0.076398, 0.092998, 0.129684",\ + "0.104996, 0.104996, 0.106760, 0.117958, 0.143880",\ + "0.191048, 0.191210, 0.191730, 0.197481, 0.211138",\ + "0.431517, 0.431517, 0.431517, 0.433284, 0.437618",\ + "1.064330, 1.065326, 1.065376, 1.065376, 1.065376",\ + "0.071575, 0.071791, 0.076398, 0.092998, 0.129684",\ + "0.104996, 0.104996, 0.106760, 0.117958, 0.143880",\ + "0.191061, 0.191210, 0.191730, 0.197481, 0.211138",\ + "0.431517, 0.431517, 0.431517, 0.433284, 0.437618",\ + "1.064411, 1.065326, 1.065376, 1.065376, 1.065376",\ + "0.071593, 0.071792, 0.076409, 0.093042, 0.129773",\ + "0.104996, 0.104996, 0.106764, 0.117989, 0.143943",\ + "0.191073, 0.191211, 0.191731, 0.197497, 0.211171",\ + "0.431517, 0.431517, 0.431517, 0.433289, 0.437628",\ + "1.064486, 1.065330, 1.065376, 1.065376, 1.065376",\ + "0.071706, 0.071799, 0.076411, 0.093080, 0.129880",\ + "0.104996, 0.104996, 0.106764, 0.118016, 0.144018",\ + "0.191152, 0.191215, 0.191732, 0.197512, 0.211211",\ + "0.431517, 0.431517, 0.431517, 0.433294, 0.437641",\ + "1.064965, 1.065357, 1.065376, 1.065376, 1.065376"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_min*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[24]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011"); + values ( "0.170538, 0.344791, 0.534395, 0.834671, 1.413373",\ + "0.220382, 0.410357, 0.608123, 0.926913, 1.543930",\ + "0.296720, 0.496999, 0.695612, 1.028145, 1.678018",\ + "0.503635, 0.714092, 0.910615, 1.258034, 1.946089",\ + "1.056522, 1.269056, 1.463869, 1.813497, 2.508420",\ + "0.258747, 0.432108, 0.621676, 0.921976, 1.500726",\ + "0.308608, 0.497675, 0.695404, 1.014218, 1.631283",\ + "0.384956, 0.584317, 0.782893, 1.115450, 1.765372",\ + "0.591859, 0.801410, 0.997896, 1.345339, 2.033442",\ + "1.144699, 1.356374, 1.551150, 1.900803, 2.595773",\ + "0.340253, 0.512437, 0.701702, 1.002005, 1.580758",\ + "0.397921, 0.578003, 0.775430, 1.094246, 1.711315",\ + "0.474302, 0.664646, 0.862920, 1.195478, 1.845403",\ + "0.681166, 0.881738, 1.077923, 1.425368, 2.113474",\ + "1.233862, 1.436702, 1.631177, 1.980831, 2.675804",\ + "0.397891, 0.570245, 0.759425, 1.059457, 1.637819",\ + "0.461736, 0.635815, 0.833172, 1.151745, 1.768469",\ + "0.538147, 0.722460, 0.920664, 1.253017, 1.902637",\ + "0.744974, 0.939560, 1.135661, 1.482953, 2.170799",\ + "1.297532, 1.494526, 1.688912, 2.038425, 2.733147",\ + "0.700600, 0.875392, 1.063084, 1.362647, 1.940096",\ + "0.765324, 0.940987, 1.136834, 1.454975, 2.070858",\ + "0.851439, 1.027647, 1.224326, 1.556282, 2.205122",\ + "1.066882, 1.244797, 1.439323, 1.786257, 2.473396",\ + "1.621173, 1.799784, 1.992573, 2.341736, 3.035763"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011"); + values ( "0.138974, 0.138974, 0.138974, 0.148689, 0.172413",\ + "0.231167, 0.231167, 0.231167, 0.238024, 0.254767",\ + "0.397287, 0.397287, 0.397287, 0.400375, 0.407916",\ + "0.872442, 0.873368, 0.873689, 0.874395, 0.875876",\ + "2.139574, 2.140537, 2.140572, 2.140672, 2.140918",\ + "0.138974, 0.138974, 0.138974, 0.148689, 0.172413",\ + "0.231167, 0.231167, 0.231167, 0.238024, 0.254767",\ + "0.397287, 0.397287, 0.397287, 0.400375, 0.407916",\ + "0.872465, 0.873368, 0.873689, 0.874395, 0.875876",\ + "2.139599, 2.140537, 2.140572, 2.140672, 2.140918",\ + "0.138974, 0.138974, 0.138974, 0.148689, 0.172413",\ + "0.231167, 0.231167, 0.231167, 0.238024, 0.254767",\ + "0.397287, 0.397287, 0.397287, 0.400375, 0.407916",\ + "0.872537, 0.873368, 0.873689, 0.874395, 0.875876",\ + "2.139673, 2.140537, 2.140572, 2.140672, 2.140918",\ + "0.138974, 0.138974, 0.138974, 0.148718, 0.172471",\ + "0.231167, 0.231167, 0.231167, 0.238044, 0.254807",\ + "0.397287, 0.397287, 0.397287, 0.400384, 0.407935",\ + "0.872606, 0.873372, 0.873689, 0.874396, 0.875879",\ + "2.139745, 2.140541, 2.140572, 2.140673, 2.140918",\ + "0.138974, 0.138974, 0.138974, 0.148743, 0.172540",\ + "0.231167, 0.231167, 0.231167, 0.238062, 0.254856",\ + "0.397287, 0.397287, 0.397287, 0.400392, 0.407957",\ + "0.872562, 0.873396, 0.873689, 0.874398, 0.875884",\ + "2.139699, 2.140566, 2.140572, 2.140673, 2.140919"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011"); + values ( "0.114471, 0.367066, 0.558465, 0.861628, 1.446142",\ + "0.150570, 0.396419, 0.587661, 0.892759, 1.482112",\ + "0.204674, 0.442227, 0.633125, 0.939020, 1.530584",\ + "0.336064, 0.565592, 0.755956, 1.061790, 1.653617",\ + "0.673293, 0.896815, 1.086094, 1.390763, 1.980611",\ + "0.202627, 0.454384, 0.645746, 0.948933, 1.533495",\ + "0.238831, 0.483737, 0.674942, 0.980064, 1.569466",\ + "0.292913, 0.529545, 0.720406, 1.026325, 1.617937",\ + "0.424271, 0.652910, 0.843237, 1.149095, 1.740970",\ + "0.761475, 0.984133, 1.173375, 1.478068, 2.067965",\ + "0.291726, 0.534712, 0.725773, 1.028962, 1.613527",\ + "0.328254, 0.564066, 0.754969, 1.060092, 1.649498",\ + "0.382266, 0.609874, 0.800433, 1.106354, 1.697969",\ + "0.513528, 0.733239, 0.923264, 1.229123, 1.821002",\ + "0.850652, 1.064461, 1.253402, 1.558096, 2.147996",\ + "0.355336, 0.592555, 0.783499, 1.086421, 1.670602",\ + "0.392174, 0.621907, 0.812695, 1.117557, 1.706585",\ + "0.446119, 0.667711, 0.858158, 1.163821, 1.755061",\ + "0.577288, 0.791071, 0.980987, 1.286592, 1.878095",\ + "0.914335, 1.122288, 1.311124, 1.615562, 2.205085",\ + "0.691472, 0.897945, 1.087159, 1.389617, 1.972896",\ + "0.730295, 0.927282, 1.116354, 1.420759, 2.008893",\ + "0.783810, 0.973061, 1.161817, 1.467025, 2.057376",\ + "0.914389, 1.096386, 1.284647, 1.589795, 2.180410",\ + "1.248447, 1.427560, 1.614782, 1.918764, 2.507394"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011"); + values ( "0.055015, 0.067356, 0.073976, 0.088784, 0.119708",\ + "0.104870, 0.104870, 0.106669, 0.116295, 0.138275",\ + "0.190674, 0.190674, 0.191255, 0.196129, 0.207539",\ + "0.432838, 0.433934, 0.434139, 0.435063, 0.437176",\ + "1.062723, 1.062723, 1.063223, 1.064130, 1.065922",\ + "0.055327, 0.067356, 0.073976, 0.088784, 0.119708",\ + "0.104870, 0.104870, 0.106669, 0.116295, 0.138275",\ + "0.190674, 0.190674, 0.191255, 0.196129, 0.207539",\ + "0.432865, 0.433934, 0.434139, 0.435063, 0.437176",\ + "1.062723, 1.062723, 1.063223, 1.064130, 1.065922",\ + "0.056284, 0.067356, 0.073976, 0.088784, 0.119708",\ + "0.104870, 0.104870, 0.106669, 0.116295, 0.138275",\ + "0.190674, 0.190674, 0.191255, 0.196129, 0.207539",\ + "0.432950, 0.433934, 0.434139, 0.435063, 0.437176",\ + "1.062723, 1.062723, 1.063223, 1.064130, 1.065922",\ + "0.057202, 0.067402, 0.073991, 0.088822, 0.119782",\ + "0.104870, 0.104870, 0.106673, 0.116322, 0.138328",\ + "0.190674, 0.190674, 0.191256, 0.196143, 0.207567",\ + "0.433032, 0.433938, 0.434140, 0.435065, 0.437181",\ + "1.062723, 1.062723, 1.063224, 1.064132, 1.065926",\ + "0.063072, 0.067724, 0.073993, 0.088854, 0.119873",\ + "0.104870, 0.104870, 0.106674, 0.116345, 0.138392",\ + "0.190674, 0.190674, 0.191256, 0.196155, 0.207600",\ + "0.433553, 0.433966, 0.434140, 0.435067, 0.437187",\ + "1.062723, 1.062723, 1.063224, 1.064134, 1.065932"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_min_2340*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[27]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011"); + values ( "0.337877, 0.567396, 0.751267, 1.044506, 1.611115",\ + "0.385816, 0.615335, 0.799206, 1.092445, 1.659054",\ + "0.487851, 0.717370, 0.901241, 1.194480, 1.761089",\ + "0.725267, 0.954786, 1.138657, 1.431895, 1.998505",\ + "1.296926, 1.526444, 1.710315, 2.003554, 2.570163",\ + "0.426171, 0.654713, 0.838548, 1.131811, 1.698468",\ + "0.474110, 0.702653, 0.886487, 1.179750, 1.746408",\ + "0.576145, 0.804687, 0.988522, 1.281785, 1.848443",\ + "0.813561, 1.042103, 1.225938, 1.519201, 2.085858",\ + "1.385220, 1.613762, 1.797596, 2.090859, 2.657517",\ + "0.515866, 0.735041, 0.918575, 1.211839, 1.778500",\ + "0.563806, 0.782980, 0.966514, 1.259778, 1.826439",\ + "0.665841, 0.885015, 1.068549, 1.361813, 1.928474",\ + "0.903256, 1.122430, 1.305965, 1.599229, 2.165890",\ + "1.474915, 1.694089, 1.877623, 2.170888, 2.737548",\ + "0.580118, 0.792869, 0.976284, 1.269277, 1.835533",\ + "0.628057, 0.840809, 1.024223, 1.317216, 1.883472",\ + "0.730092, 0.942843, 1.126258, 1.419251, 1.985507",\ + "0.967507, 1.180259, 1.363673, 1.656667, 2.222923",\ + "1.539166, 1.751918, 1.935332, 2.228325, 2.794581",\ + "0.919018, 1.098154, 1.279940, 1.572454, 2.137775",\ + "0.966958, 1.146093, 1.327879, 1.620393, 2.185715",\ + "1.068992, 1.248128, 1.429914, 1.722428, 2.287750",\ + "1.306408, 1.485543, 1.667330, 1.959844, 2.525165",\ + "1.878067, 2.057202, 2.238988, 2.531503, 3.096824"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011"); + values ( "0.032950, 0.032950, 0.032950, 0.032950, 0.032950",\ + "0.148290, 0.148290, 0.148290, 0.148290, 0.148290",\ + "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\ + "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\ + "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\ + "0.032950, 0.032950, 0.032950, 0.032950, 0.032950",\ + "0.148290, 0.148290, 0.148290, 0.148290, 0.148290",\ + "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\ + "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\ + "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\ + "0.032950, 0.032950, 0.032950, 0.032950, 0.032950",\ + "0.148290, 0.148290, 0.148290, 0.148290, 0.148290",\ + "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\ + "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\ + "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\ + "0.032950, 0.032950, 0.032950, 0.032950, 0.032950",\ + "0.148290, 0.148290, 0.148290, 0.148290, 0.148290",\ + "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\ + "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\ + "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\ + "0.032950, 0.032950, 0.032950, 0.032950, 0.032950",\ + "0.148290, 0.148290, 0.148290, 0.148290, 0.148290",\ + "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\ + "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\ + "2.136637, 2.136637, 2.136637, 2.136637, 2.136637"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011"); + values ( "0.372253, 0.601881, 0.784032, 1.076595, 1.643049",\ + "0.397511, 0.627029, 0.810901, 1.104139, 1.670748",\ + "0.438896, 0.668415, 0.852286, 1.145524, 1.712134",\ + "0.561215, 0.790734, 0.974605, 1.267843, 1.834453",\ + "0.893448, 1.122967, 1.306838, 1.600076, 2.166686",\ + "0.460528, 0.689198, 0.871313, 1.163900, 1.730402",\ + "0.485805, 0.714347, 0.898181, 1.191444, 1.758102",\ + "0.527190, 0.755732, 0.939567, 1.232830, 1.799487",\ + "0.649509, 0.878051, 1.061886, 1.355149, 1.921806",\ + "0.981742, 1.210284, 1.394119, 1.687381, 2.254039",\ + "0.550165, 0.769525, 0.951340, 1.243928, 1.810434",\ + "0.575500, 0.794674, 0.978208, 1.271473, 1.838133",\ + "0.616885, 0.836059, 1.019594, 1.312858, 1.879519",\ + "0.739204, 0.958378, 1.141913, 1.435177, 2.001838",\ + "1.071437, 1.290611, 1.474146, 1.767410, 2.334071",\ + "0.614360, 0.827361, 1.009044, 1.301366, 1.867467",\ + "0.639751, 0.852503, 1.035917, 1.328910, 1.895166",\ + "0.681136, 0.893888, 1.077302, 1.370296, 1.936552",\ + "0.803456, 1.016207, 1.199622, 1.492615, 2.058871",\ + "1.135688, 1.348440, 1.531854, 1.824847, 2.391104",\ + "0.951814, 1.132696, 1.312700, 1.604543, 2.169709",\ + "0.978652, 1.157787, 1.339573, 1.632088, 2.197409",\ + "1.020037, 1.199172, 1.380959, 1.673473, 2.238794",\ + "1.142356, 1.321491, 1.503278, 1.795792, 2.361114",\ + "1.474589, 1.653724, 1.835510, 2.128025, 2.693346"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011"); + values ( "0.039649, 0.039649, 0.039649, 0.039649, 0.039649",\ + "0.089554, 0.089554, 0.089554, 0.089554, 0.089554",\ + "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\ + "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\ + "1.065031, 1.065031, 1.065031, 1.065031, 1.065031",\ + "0.039649, 0.039649, 0.039649, 0.039649, 0.039649",\ + "0.089554, 0.089554, 0.089554, 0.089554, 0.089554",\ + "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\ + "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\ + "1.065031, 1.065031, 1.065031, 1.065031, 1.065031",\ + "0.039649, 0.039649, 0.039649, 0.039649, 0.039649",\ + "0.089554, 0.089554, 0.089554, 0.089554, 0.089554",\ + "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\ + "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\ + "1.065031, 1.065031, 1.065031, 1.065031, 1.065031",\ + "0.039649, 0.039649, 0.039649, 0.039649, 0.039649",\ + "0.089554, 0.089554, 0.089554, 0.089554, 0.089554",\ + "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\ + "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\ + "1.065031, 1.065031, 1.065031, 1.065031, 1.065031",\ + "0.039649, 0.039649, 0.039649, 0.039649, 0.039649",\ + "0.089554, 0.089554, 0.089554, 0.089554, 0.089554",\ + "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\ + "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\ + "1.065031, 1.065031, 1.065031, 1.065031, 1.065031"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_min_2710*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[31]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.323167, 0.539803, 0.719494, 1.009588, 1.571964",\ + "0.371106, 0.587742, 0.767433, 1.057527, 1.619903",\ + "0.473141, 0.689777, 0.869468, 1.159562, 1.721938",\ + "0.710557, 0.927193, 1.106884, 1.396978, 1.959354",\ + "1.282216, 1.498852, 1.678543, 1.968637, 2.531013",\ + "0.411457, 0.627121, 0.806775, 1.096893, 1.659318",\ + "0.459396, 0.675060, 0.854714, 1.144832, 1.707257",\ + "0.561431, 0.777095, 0.956749, 1.246867, 1.809292",\ + "0.798847, 1.014511, 1.194165, 1.484283, 2.046708",\ + "1.370506, 1.586170, 1.765824, 2.055942, 2.618367",\ + "0.500498, 0.707454, 0.886802, 1.176922, 1.739349",\ + "0.548437, 0.755393, 0.934741, 1.224860, 1.787288",\ + "0.650472, 0.857428, 1.036776, 1.326895, 1.889323",\ + "0.887888, 1.094844, 1.274192, 1.564311, 2.126739",\ + "1.459547, 1.666503, 1.845851, 2.135971, 2.698398",\ + "0.563859, 0.765284, 0.944499, 1.234353, 1.796369",\ + "0.611798, 0.813223, 0.992438, 1.282292, 1.844308",\ + "0.713833, 0.915258, 1.094473, 1.384327, 1.946343",\ + "0.951249, 1.152674, 1.331889, 1.621743, 2.183759",\ + "1.522908, 1.724333, 1.903548, 2.193402, 2.755418",\ + "0.888835, 1.070603, 1.248155, 1.537527, 2.098596",\ + "0.936774, 1.118542, 1.296094, 1.585466, 2.146535",\ + "1.038809, 1.220577, 1.398129, 1.687501, 2.248570",\ + "1.276225, 1.457993, 1.635545, 1.924917, 2.485986",\ + "1.847884, 2.029652, 2.207204, 2.496576, 3.057645"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.032953, 0.032953, 0.032953, 0.032953, 0.032953",\ + "0.148289, 0.148289, 0.148289, 0.148289, 0.148289",\ + "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\ + "0.871095, 0.871095, 0.871095, 0.871095, 0.871095",\ + "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\ + "0.032953, 0.032953, 0.032953, 0.032953, 0.032953",\ + "0.148289, 0.148289, 0.148289, 0.148289, 0.148289",\ + "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\ + "0.871095, 0.871095, 0.871095, 0.871095, 0.871095",\ + "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\ + "0.032953, 0.032953, 0.032953, 0.032953, 0.032953",\ + "0.148289, 0.148289, 0.148289, 0.148289, 0.148289",\ + "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\ + "0.871095, 0.871095, 0.871095, 0.871095, 0.871095",\ + "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\ + "0.032953, 0.032953, 0.032953, 0.032953, 0.032953",\ + "0.148289, 0.148289, 0.148289, 0.148289, 0.148289",\ + "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\ + "0.871095, 0.871095, 0.871095, 0.871095, 0.871095",\ + "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\ + "0.032953, 0.032953, 0.032953, 0.032953, 0.032953",\ + "0.148289, 0.148289, 0.148289, 0.148289, 0.148289",\ + "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\ + "0.871095, 0.871095, 0.871095, 0.871095, 0.871095",\ + "2.136637, 2.136637, 2.136637, 2.136637, 2.136637"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.360736, 0.577372, 0.757063, 1.047157, 1.609533",\ + "0.382801, 0.599437, 0.779128, 1.069222, 1.631598",\ + "0.424186, 0.640822, 0.820514, 1.110608, 1.672984",\ + "0.546505, 0.763141, 0.942833, 1.232926, 1.795303",\ + "0.878738, 1.095374, 1.275065, 1.565159, 2.127535",\ + "0.449026, 0.664690, 0.844344, 1.134462, 1.696887",\ + "0.471091, 0.686755, 0.866409, 1.156527, 1.718952",\ + "0.512477, 0.728141, 0.907795, 1.197913, 1.760337",\ + "0.634796, 0.850460, 1.030114, 1.320232, 1.882656",\ + "0.967028, 1.182692, 1.362346, 1.652464, 2.214889",\ + "0.538067, 0.745023, 0.924371, 1.214491, 1.776918",\ + "0.560132, 0.767088, 0.946436, 1.236556, 1.798984",\ + "0.601517, 0.808473, 0.987821, 1.277941, 1.840369",\ + "0.723837, 0.930792, 1.110141, 1.400260, 1.962688",\ + "1.056069, 1.263025, 1.442373, 1.732492, 2.294920",\ + "0.601428, 0.802853, 0.982068, 1.271922, 1.833938",\ + "0.623493, 0.824919, 1.004133, 1.293988, 1.856004",\ + "0.664878, 0.866304, 1.045519, 1.335373, 1.897389",\ + "0.787198, 0.988623, 1.167838, 1.457692, 2.019708",\ + "1.119430, 1.320855, 1.500070, 1.789924, 2.351940",\ + "0.926404, 1.108172, 1.285724, 1.575096, 2.136165",\ + "0.948469, 1.130237, 1.307790, 1.597161, 2.158231",\ + "0.989855, 1.171622, 1.349175, 1.638546, 2.199616",\ + "1.112174, 1.293941, 1.471494, 1.760865, 2.321935",\ + "1.444406, 1.626174, 1.803726, 2.093098, 2.654167"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.039651, 0.039651, 0.039651, 0.039651, 0.039651",\ + "0.089556, 0.089556, 0.089556, 0.089556, 0.089556",\ + "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\ + "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\ + "1.065030, 1.065030, 1.065030, 1.065030, 1.065030",\ + "0.039651, 0.039651, 0.039651, 0.039651, 0.039651",\ + "0.089556, 0.089556, 0.089556, 0.089556, 0.089556",\ + "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\ + "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\ + "1.065030, 1.065030, 1.065030, 1.065030, 1.065030",\ + "0.039651, 0.039651, 0.039651, 0.039651, 0.039651",\ + "0.089556, 0.089556, 0.089556, 0.089556, 0.089556",\ + "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\ + "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\ + "1.065030, 1.065030, 1.065030, 1.065030, 1.065030",\ + "0.039651, 0.039651, 0.039651, 0.039651, 0.039651",\ + "0.089556, 0.089556, 0.089556, 0.089556, 0.089556",\ + "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\ + "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\ + "1.065030, 1.065030, 1.065030, 1.065030, 1.065030",\ + "0.039651, 0.039651, 0.039651, 0.039651, 0.039651",\ + "0.089556, 0.089556, 0.089556, 0.089556, 0.089556",\ + "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\ + "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\ + "1.065030, 1.065030, 1.065030, 1.065030, 1.065030"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_min_2399*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[32]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.393798, 0.608317, 0.787191, 1.076625, 1.638145",\ + "0.443659, 0.658178, 0.837052, 1.126486, 1.688006",\ + "0.545527, 0.760046, 0.938920, 1.228354, 1.789874",\ + "0.783388, 0.997908, 1.176781, 1.466215, 2.027735",\ + "1.355708, 1.570228, 1.749101, 2.038536, 2.600056",\ + "0.482072, 0.695635, 0.874472, 1.163930, 1.725499",\ + "0.531933, 0.745496, 0.924333, 1.213791, 1.775360",\ + "0.633801, 0.847364, 1.026201, 1.315659, 1.877228",\ + "0.871662, 1.085225, 1.264062, 1.553521, 2.115089",\ + "1.443982, 1.657546, 1.836382, 2.125841, 2.687409",\ + "0.571616, 0.775963, 0.954499, 1.243959, 1.805530",\ + "0.621477, 0.825824, 1.004360, 1.293820, 1.855391",\ + "0.723345, 0.927692, 1.106228, 1.395688, 1.957259",\ + "0.961206, 1.165553, 1.344089, 1.633549, 2.195120",\ + "1.533526, 1.737874, 1.916409, 2.205869, 2.767441",\ + "0.635684, 0.833793, 1.012195, 1.301390, 1.862550",\ + "0.685545, 0.883654, 1.062056, 1.351251, 1.912411",\ + "0.787413, 0.985522, 1.163924, 1.453119, 2.014279",\ + "1.025275, 1.223383, 1.401785, 1.690980, 2.252141",\ + "1.597595, 1.795703, 1.974106, 2.263301, 2.824461",\ + "0.959458, 1.139086, 1.315850, 1.604562, 2.164778",\ + "1.009318, 1.188946, 1.365711, 1.654423, 2.214639",\ + "1.111187, 1.290814, 1.467579, 1.756291, 2.316507",\ + "1.349048, 1.528676, 1.705440, 1.994153, 2.554368",\ + "1.921368, 2.100996, 2.277760, 2.566473, 3.126688"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.039801, 0.039801, 0.039801, 0.039801, 0.039801",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375010, 0.375010, 0.375010, 0.375010, 0.375010",\ + "0.869309, 0.869309, 0.869309, 0.869309, 0.869309",\ + "2.137202, 2.137202, 2.137202, 2.137202, 2.137202",\ + "0.039801, 0.039801, 0.039801, 0.039801, 0.039801",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375010, 0.375010, 0.375010, 0.375010, 0.375010",\ + "0.869309, 0.869309, 0.869309, 0.869309, 0.869309",\ + "2.137202, 2.137202, 2.137202, 2.137202, 2.137202",\ + "0.039801, 0.039801, 0.039801, 0.039801, 0.039801",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375010, 0.375010, 0.375010, 0.375010, 0.375010",\ + "0.869309, 0.869309, 0.869309, 0.869309, 0.869309",\ + "2.137202, 2.137202, 2.137202, 2.137202, 2.137202",\ + "0.039801, 0.039801, 0.039801, 0.039801, 0.039801",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375010, 0.375010, 0.375010, 0.375010, 0.375010",\ + "0.869309, 0.869309, 0.869309, 0.869309, 0.869309",\ + "2.137202, 2.137202, 2.137202, 2.137202, 2.137202",\ + "0.039801, 0.039801, 0.039801, 0.039801, 0.039801",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375010, 0.375010, 0.375010, 0.375010, 0.375010",\ + "0.869309, 0.869309, 0.869309, 0.869309, 0.869309",\ + "2.137202, 2.137202, 2.137202, 2.137202, 2.137202"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.434527, 0.649046, 0.827920, 1.117354, 1.678874",\ + "0.456877, 0.671396, 0.850269, 1.139704, 1.701224",\ + "0.498240, 0.712759, 0.891633, 1.181067, 1.742587",\ + "0.620276, 0.834795, 1.013668, 1.303103, 1.864623",\ + "0.951889, 1.166408, 1.345281, 1.634716, 2.196236",\ + "0.522801, 0.736364, 0.915201, 1.204659, 1.766227",\ + "0.545151, 0.758714, 0.937550, 1.227009, 1.788577",\ + "0.586514, 0.800077, 0.978914, 1.268372, 1.829941",\ + "0.708550, 0.922113, 1.100950, 1.390408, 1.951976",\ + "1.040162, 1.253726, 1.432562, 1.722021, 2.283589",\ + "0.612344, 0.816692, 0.995228, 1.284688, 1.846259",\ + "0.634694, 0.839042, 1.017577, 1.307038, 1.868609",\ + "0.676058, 0.880405, 1.058941, 1.348401, 1.909972",\ + "0.798093, 1.002441, 1.180976, 1.470437, 2.032008",\ + "1.129706, 1.334054, 1.512589, 1.802049, 2.363621",\ + "0.676413, 0.874521, 1.052924, 1.342119, 1.903279",\ + "0.698763, 0.896871, 1.075274, 1.364469, 1.925629",\ + "0.740127, 0.938235, 1.116637, 1.405832, 1.966993",\ + "0.862162, 1.060270, 1.238673, 1.527868, 2.089028",\ + "1.193775, 1.391883, 1.570286, 1.859481, 2.420641",\ + "1.000186, 1.179814, 1.356578, 1.645291, 2.205507",\ + "1.022536, 1.202164, 1.378928, 1.667641, 2.227856",\ + "1.063900, 1.243527, 1.420292, 1.709004, 2.269220",\ + "1.185935, 1.365563, 1.542327, 1.831040, 2.391255",\ + "1.517548, 1.697176, 1.873940, 2.162653, 2.722868"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\ + "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\ + "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\ + "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\ + "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_min_2477*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[34]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011"); + values ( "0.454939, 0.667221, 0.852612, 1.143493, 1.702667",\ + "0.502878, 0.715160, 0.900551, 1.191432, 1.750605",\ + "0.604913, 0.817195, 1.002586, 1.293467, 1.852640",\ + "0.842329, 1.054611, 1.240002, 1.530883, 2.090056",\ + "1.413988, 1.626270, 1.811661, 2.102542, 2.661716",\ + "0.543302, 0.754540, 0.939893, 1.230798, 1.790020",\ + "0.591241, 0.802479, 0.987832, 1.278737, 1.837959",\ + "0.693276, 0.904514, 1.089867, 1.380772, 1.939994",\ + "0.930692, 1.141930, 1.327283, 1.618188, 2.177410",\ + "1.502351, 1.713589, 1.898942, 2.189847, 2.749069",\ + "0.632361, 0.834874, 1.019920, 1.310827, 1.870051",\ + "0.680300, 0.882813, 1.067859, 1.358765, 1.917990",\ + "0.782335, 0.984848, 1.169894, 1.460800, 2.020025",\ + "1.019751, 1.222264, 1.407310, 1.698216, 2.257441",\ + "1.591410, 1.793923, 1.978969, 2.269875, 2.829100",\ + "0.695656, 0.892702, 1.077631, 1.368254, 1.927063",\ + "0.743595, 0.940641, 1.125570, 1.416193, 1.975002",\ + "0.845629, 1.042676, 1.227605, 1.518228, 2.077037",\ + "1.083045, 1.280092, 1.465021, 1.755644, 2.314453",\ + "1.654704, 1.851751, 2.036680, 2.327303, 2.886112",\ + "1.016280, 1.198005, 1.381290, 1.671425, 2.229280",\ + "1.064219, 1.245944, 1.429229, 1.719364, 2.277219",\ + "1.166254, 1.347979, 1.531264, 1.821398, 2.379254",\ + "1.403669, 1.585395, 1.768679, 2.058815, 2.616670",\ + "1.975328, 2.157054, 2.340338, 2.630474, 3.188329"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011"); + values ( "0.032953, 0.032953, 0.032953, 0.032953, 0.032953",\ + "0.148289, 0.148289, 0.148289, 0.148289, 0.148289",\ + "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\ + "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\ + "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\ + "0.032953, 0.032953, 0.032953, 0.032953, 0.032953",\ + "0.148289, 0.148289, 0.148289, 0.148289, 0.148289",\ + "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\ + "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\ + "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\ + "0.032953, 0.032953, 0.032953, 0.032953, 0.032953",\ + "0.148289, 0.148289, 0.148289, 0.148289, 0.148289",\ + "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\ + "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\ + "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\ + "0.032953, 0.032953, 0.032953, 0.032953, 0.032953",\ + "0.148289, 0.148289, 0.148289, 0.148289, 0.148289",\ + "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\ + "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\ + "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\ + "0.032953, 0.032953, 0.032953, 0.032953, 0.032953",\ + "0.148289, 0.148289, 0.148289, 0.148289, 0.148289",\ + "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\ + "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\ + "2.136637, 2.136637, 2.136637, 2.136637, 2.136637"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011"); + values ( "0.492508, 0.704790, 0.890181, 1.181062, 1.740236",\ + "0.514573, 0.726856, 0.912247, 1.203127, 1.762301",\ + "0.555959, 0.768241, 0.953632, 1.244512, 1.803686",\ + "0.678278, 0.890560, 1.075951, 1.366831, 1.926005",\ + "1.010510, 1.222792, 1.408183, 1.699064, 2.258237",\ + "0.580871, 0.792109, 0.977462, 1.268367, 1.827589",\ + "0.602936, 0.814174, 0.999527, 1.290432, 1.849654",\ + "0.644321, 0.855559, 1.040913, 1.331817, 1.891039",\ + "0.766640, 0.977878, 1.163232, 1.454136, 2.013358",\ + "1.098873, 1.310111, 1.495464, 1.786369, 2.345591",\ + "0.669930, 0.872443, 1.057489, 1.348396, 1.907620",\ + "0.691995, 0.894508, 1.079554, 1.370461, 1.929686",\ + "0.733381, 0.935894, 1.120940, 1.411846, 1.971071",\ + "0.855700, 1.058213, 1.243259, 1.534165, 2.093390",\ + "1.187932, 1.390445, 1.575491, 1.866397, 2.425622",\ + "0.733225, 0.930271, 1.115200, 1.405823, 1.964632",\ + "0.755290, 0.952336, 1.137265, 1.427888, 1.986697",\ + "0.796675, 0.993721, 1.178650, 1.469274, 2.028083",\ + "0.918994, 1.116040, 1.300969, 1.591593, 2.150402",\ + "1.251227, 1.448273, 1.633202, 1.923825, 2.482634",\ + "1.053849, 1.235574, 1.418859, 1.708994, 2.266849",\ + "1.075914, 1.257639, 1.440924, 1.731059, 2.288914",\ + "1.117299, 1.299025, 1.482309, 1.772444, 2.330299",\ + "1.239618, 1.421344, 1.604628, 1.894763, 2.452619",\ + "1.571851, 1.753576, 1.936861, 2.226995, 2.784851"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011"); + values ( "0.039651, 0.039651, 0.039651, 0.039651, 0.039651",\ + "0.089555, 0.089555, 0.089555, 0.089555, 0.089555",\ + "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\ + "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\ + "1.065030, 1.065030, 1.065030, 1.065030, 1.065030",\ + "0.039651, 0.039651, 0.039651, 0.039651, 0.039651",\ + "0.089555, 0.089555, 0.089555, 0.089555, 0.089555",\ + "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\ + "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\ + "1.065030, 1.065030, 1.065030, 1.065030, 1.065030",\ + "0.039651, 0.039651, 0.039651, 0.039651, 0.039651",\ + "0.089555, 0.089555, 0.089555, 0.089555, 0.089555",\ + "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\ + "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\ + "1.065030, 1.065030, 1.065030, 1.065030, 1.065030",\ + "0.039651, 0.039651, 0.039651, 0.039651, 0.039651",\ + "0.089555, 0.089555, 0.089555, 0.089555, 0.089555",\ + "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\ + "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\ + "1.065030, 1.065030, 1.065030, 1.065030, 1.065030",\ + "0.039651, 0.039651, 0.039651, 0.039651, 0.039651",\ + "0.089555, 0.089555, 0.089555, 0.089555, 0.089555",\ + "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\ + "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\ + "1.065030, 1.065030, 1.065030, 1.065030, 1.065030"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_min_2561*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[35]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.429494, 0.640486, 0.817408, 1.101335, 1.650898",\ + "0.477433, 0.688425, 0.865347, 1.149274, 1.698837",\ + "0.579467, 0.790460, 0.967382, 1.251309, 1.800872",\ + "0.816883, 1.027876, 1.204798, 1.488725, 2.038288",\ + "1.388543, 1.599535, 1.776457, 2.060384, 2.609947",\ + "0.517769, 0.727804, 0.904689, 1.188640, 1.738251",\ + "0.565708, 0.775743, 0.952628, 1.236579, 1.786190",\ + "0.667743, 0.877778, 1.054663, 1.338614, 1.888225",\ + "0.905159, 1.115194, 1.292079, 1.576030, 2.125641",\ + "1.476818, 1.686853, 1.863738, 2.147689, 2.697300",\ + "0.606719, 0.808137, 0.984716, 1.268669, 1.818283",\ + "0.654658, 0.856076, 1.032655, 1.316607, 1.866222",\ + "0.756693, 0.958111, 1.134690, 1.418642, 1.968257",\ + "0.994109, 1.195527, 1.372106, 1.656058, 2.205673",\ + "1.565768, 1.767186, 1.943765, 2.227717, 2.777332",\ + "0.669974, 0.865958, 1.042407, 1.326085, 1.875272",\ + "0.717913, 0.913897, 1.090346, 1.374024, 1.923211",\ + "0.819948, 1.015932, 1.192381, 1.476059, 2.025246",\ + "1.057364, 1.253348, 1.429797, 1.713475, 2.262662",\ + "1.629023, 1.825007, 2.001456, 2.285134, 2.834321",\ + "0.991556, 1.171211, 1.346062, 1.629245, 2.177461",\ + "1.039495, 1.219150, 1.394001, 1.677184, 2.225400",\ + "1.141530, 1.321185, 1.496036, 1.779219, 2.327435",\ + "1.378946, 1.558601, 1.733452, 2.016635, 2.564851",\ + "1.950605, 2.130260, 2.305111, 2.588294, 3.136510"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.032953, 0.032953, 0.032953, 0.032953, 0.032953",\ + "0.148289, 0.148289, 0.148289, 0.148289, 0.148289",\ + "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\ + "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\ + "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\ + "0.032953, 0.032953, 0.032953, 0.032953, 0.032953",\ + "0.148289, 0.148289, 0.148289, 0.148289, 0.148289",\ + "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\ + "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\ + "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\ + "0.032953, 0.032953, 0.032953, 0.032953, 0.032953",\ + "0.148289, 0.148289, 0.148289, 0.148289, 0.148289",\ + "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\ + "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\ + "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\ + "0.032953, 0.032953, 0.032953, 0.032953, 0.032953",\ + "0.148289, 0.148289, 0.148289, 0.148289, 0.148289",\ + "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\ + "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\ + "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\ + "0.032953, 0.032953, 0.032953, 0.032953, 0.032953",\ + "0.148289, 0.148289, 0.148289, 0.148289, 0.148289",\ + "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\ + "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\ + "2.136637, 2.136637, 2.136637, 2.136637, 2.136637"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.467063, 0.678055, 0.854977, 1.138904, 1.688467",\ + "0.489128, 0.700120, 0.877042, 1.160969, 1.710532",\ + "0.530513, 0.741505, 0.918428, 1.202354, 1.751917",\ + "0.652832, 0.863824, 1.040747, 1.324673, 1.874236",\ + "0.985064, 1.196057, 1.372979, 1.656906, 2.206469",\ + "0.555338, 0.765373, 0.942258, 1.226209, 1.775820",\ + "0.577403, 0.787438, 0.964323, 1.248274, 1.797885",\ + "0.618789, 0.828824, 1.005709, 1.289660, 1.839271",\ + "0.741108, 0.951143, 1.128028, 1.411978, 1.961590",\ + "1.073340, 1.283375, 1.460260, 1.744211, 2.293822",\ + "0.644288, 0.845706, 1.022285, 1.306238, 1.855852",\ + "0.666353, 0.867771, 1.044350, 1.328303, 1.877917",\ + "0.707738, 0.909157, 1.085736, 1.369688, 1.919302",\ + "0.830057, 1.031476, 1.208055, 1.492007, 2.041621",\ + "1.162290, 1.363708, 1.540287, 1.824239, 2.373854",\ + "0.707543, 0.903527, 1.079976, 1.363654, 1.912841",\ + "0.729608, 0.925592, 1.102041, 1.385719, 1.934906",\ + "0.770994, 0.966978, 1.143427, 1.427104, 1.976291",\ + "0.893313, 1.089297, 1.265746, 1.549423, 2.098610",\ + "1.225545, 1.421529, 1.597978, 1.881656, 2.430843",\ + "1.029125, 1.208780, 1.383631, 1.666814, 2.215030",\ + "1.051190, 1.230845, 1.405696, 1.688879, 2.237095",\ + "1.092575, 1.272231, 1.447082, 1.730264, 2.278481",\ + "1.214894, 1.394550, 1.569401, 1.852583, 2.400800",\ + "1.547127, 1.726782, 1.901633, 2.184816, 2.733032"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.039651, 0.039651, 0.039651, 0.039651, 0.039651",\ + "0.089556, 0.089556, 0.089556, 0.089556, 0.089556",\ + "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\ + "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\ + "1.065030, 1.065030, 1.065030, 1.065030, 1.065030",\ + "0.039651, 0.039651, 0.039651, 0.039651, 0.039651",\ + "0.089556, 0.089556, 0.089556, 0.089556, 0.089556",\ + "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\ + "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\ + "1.065030, 1.065030, 1.065030, 1.065030, 1.065030",\ + "0.039651, 0.039651, 0.039651, 0.039651, 0.039651",\ + "0.089556, 0.089556, 0.089556, 0.089556, 0.089556",\ + "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\ + "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\ + "1.065030, 1.065030, 1.065030, 1.065030, 1.065030",\ + "0.039651, 0.039651, 0.039651, 0.039651, 0.039651",\ + "0.089556, 0.089556, 0.089556, 0.089556, 0.089556",\ + "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\ + "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\ + "1.065030, 1.065030, 1.065030, 1.065030, 1.065030",\ + "0.039651, 0.039651, 0.039651, 0.039651, 0.039651",\ + "0.089556, 0.089556, 0.089556, 0.089556, 0.089556",\ + "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\ + "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\ + "1.065030, 1.065030, 1.065030, 1.065030, 1.065030"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_min_2624*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[36]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.495805, 0.717554, 0.895492, 1.184407, 1.745240",\ + "0.543744, 0.765493, 0.943432, 1.232346, 1.793180",\ + "0.645779, 0.867528, 1.045467, 1.334381, 1.895214",\ + "0.883194, 1.104943, 1.282882, 1.571797, 2.132630",\ + "1.454853, 1.676602, 1.854541, 2.143455, 2.704289",\ + "0.584213, 0.804872, 0.982773, 1.271712, 1.832594",\ + "0.632152, 0.852811, 1.030712, 1.319651, 1.880533",\ + "0.734187, 0.954846, 1.132747, 1.421686, 1.982568",\ + "0.971603, 1.192262, 1.370163, 1.659102, 2.219983",\ + "1.543261, 1.763920, 1.941822, 2.230760, 2.791642",\ + "0.673303, 0.885207, 1.062800, 1.351740, 1.912625",\ + "0.721243, 0.933146, 1.110739, 1.399680, 1.960565",\ + "0.823277, 1.035181, 1.212774, 1.501714, 2.062599",\ + "1.060693, 1.272597, 1.450190, 1.739130, 2.300015",\ + "1.632352, 1.844256, 2.021849, 2.310789, 2.871674",\ + "0.736581, 0.943024, 1.120493, 1.409170, 1.969641",\ + "0.784520, 0.990963, 1.168432, 1.457109, 2.017580",\ + "0.886555, 1.092998, 1.270467, 1.559144, 2.119615",\ + "1.123971, 1.330414, 1.507883, 1.796560, 2.357030",\ + "1.695630, 1.902072, 2.079542, 2.368218, 2.928689",\ + "1.068830, 1.248253, 1.424150, 1.712342, 2.271862",\ + "1.116770, 1.296192, 1.472089, 1.760281, 2.319801",\ + "1.218804, 1.398227, 1.574124, 1.862316, 2.421836",\ + "1.456220, 1.635643, 1.811539, 2.099732, 2.659251",\ + "2.027879, 2.207301, 2.383198, 2.671391, 3.230910"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.032950, 0.032950, 0.032950, 0.032950, 0.032950",\ + "0.148290, 0.148290, 0.148290, 0.148290, 0.148290",\ + "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\ + "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\ + "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\ + "0.032950, 0.032950, 0.032950, 0.032950, 0.032950",\ + "0.148290, 0.148290, 0.148290, 0.148290, 0.148290",\ + "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\ + "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\ + "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\ + "0.032950, 0.032950, 0.032950, 0.032950, 0.032950",\ + "0.148290, 0.148290, 0.148290, 0.148290, 0.148290",\ + "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\ + "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\ + "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\ + "0.032950, 0.032950, 0.032950, 0.032950, 0.032950",\ + "0.148290, 0.148290, 0.148290, 0.148290, 0.148290",\ + "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\ + "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\ + "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\ + "0.032950, 0.032950, 0.032950, 0.032950, 0.032950",\ + "0.148290, 0.148290, 0.148290, 0.148290, 0.148290",\ + "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\ + "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\ + "2.136637, 2.136637, 2.136637, 2.136637, 2.136637"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.529176, 0.750903, 0.928871, 1.217786, 1.778615",\ + "0.555438, 0.777187, 0.955126, 1.244040, 1.804874",\ + "0.596823, 0.818572, 0.996511, 1.285426, 1.846259",\ + "0.719142, 0.940891, 1.118830, 1.407745, 1.968578",\ + "1.051375, 1.273124, 1.451063, 1.739977, 2.300811",\ + "0.617584, 0.838221, 1.016152, 1.305091, 1.865968",\ + "0.643846, 0.864506, 1.042407, 1.331345, 1.892227",\ + "0.685232, 0.905891, 1.083792, 1.372731, 1.933612",\ + "0.807551, 1.028210, 1.206111, 1.495050, 2.055932",\ + "1.139784, 1.360443, 1.538344, 1.827282, 2.388164",\ + "0.706675, 0.918556, 1.096179, 1.385120, 1.946000",\ + "0.732937, 0.944841, 1.122434, 1.411374, 1.972259",\ + "0.774322, 0.986226, 1.163819, 1.452759, 2.013644",\ + "0.896641, 1.108545, 1.286138, 1.575078, 2.135963",\ + "1.228874, 1.440778, 1.618371, 1.907311, 2.468196",\ + "0.769953, 0.976375, 1.153872, 1.442550, 2.003015",\ + "0.796215, 1.002657, 1.180127, 1.468804, 2.029274",\ + "0.837600, 1.044043, 1.221512, 1.510189, 2.070659",\ + "0.959919, 1.166362, 1.343831, 1.632508, 2.192978",\ + "1.292152, 1.498595, 1.676064, 1.964741, 2.525211",\ + "1.101828, 1.281614, 1.457528, 1.745722, 2.305236",\ + "1.128464, 1.307886, 1.483783, 1.771976, 2.331495",\ + "1.169849, 1.349272, 1.525168, 1.813361, 2.372880",\ + "1.292168, 1.471591, 1.647487, 1.935680, 2.495200",\ + "1.624401, 1.803824, 1.979720, 2.267913, 2.827432"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.039649, 0.039649, 0.039649, 0.039649, 0.039649",\ + "0.089554, 0.089554, 0.089554, 0.089554, 0.089554",\ + "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\ + "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\ + "1.065031, 1.065031, 1.065031, 1.065031, 1.065031",\ + "0.039649, 0.039649, 0.039649, 0.039649, 0.039649",\ + "0.089554, 0.089554, 0.089554, 0.089554, 0.089554",\ + "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\ + "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\ + "1.065031, 1.065031, 1.065031, 1.065031, 1.065031",\ + "0.039649, 0.039649, 0.039649, 0.039649, 0.039649",\ + "0.089554, 0.089554, 0.089554, 0.089554, 0.089554",\ + "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\ + "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\ + "1.065031, 1.065031, 1.065031, 1.065031, 1.065031",\ + "0.039649, 0.039649, 0.039649, 0.039649, 0.039649",\ + "0.089554, 0.089554, 0.089554, 0.089554, 0.089554",\ + "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\ + "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\ + "1.065031, 1.065031, 1.065031, 1.065031, 1.065031",\ + "0.039649, 0.039649, 0.039649, 0.039649, 0.039649",\ + "0.089554, 0.089554, 0.089554, 0.089554, 0.089554",\ + "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\ + "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\ + "1.065031, 1.065031, 1.065031, 1.065031, 1.065031"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_min_2674*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[37]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.473135, 0.702103, 0.886918, 1.182452, 1.753613",\ + "0.521074, 0.750043, 0.934857, 1.230392, 1.801553",\ + "0.623109, 0.852077, 1.036892, 1.332426, 1.903588",\ + "0.860525, 1.089493, 1.274307, 1.569842, 2.141003",\ + "1.432183, 1.661152, 1.845966, 2.141501, 2.712662",\ + "0.561467, 0.789422, 0.974199, 1.269758, 1.840967",\ + "0.609406, 0.837361, 1.022138, 1.317697, 1.888906",\ + "0.711441, 0.939396, 1.124173, 1.419731, 1.990941",\ + "0.948857, 1.176811, 1.361588, 1.657147, 2.228357",\ + "1.520515, 1.748470, 1.933247, 2.228806, 2.800015",\ + "0.650685, 0.869754, 1.054226, 1.349786, 1.920998",\ + "0.698624, 0.917693, 1.102165, 1.397725, 1.968938",\ + "0.800659, 1.019728, 1.204200, 1.499760, 2.070972",\ + "1.038074, 1.257143, 1.441615, 1.737176, 2.308388",\ + "1.609733, 1.828802, 2.013274, 2.308835, 2.880047",\ + "0.714235, 0.927578, 1.111935, 1.407229, 1.978040",\ + "0.762174, 0.975517, 1.159875, 1.455168, 2.025979",\ + "0.864209, 1.077552, 1.261909, 1.557203, 2.128014",\ + "1.101624, 1.314968, 1.499325, 1.794618, 2.365430",\ + "1.673283, 1.886627, 2.070984, 2.366277, 2.937088",\ + "1.050030, 1.232851, 1.415593, 1.710411, 2.280293",\ + "1.097969, 1.280791, 1.463533, 1.758350, 2.328232",\ + "1.200004, 1.382825, 1.565567, 1.860385, 2.430267",\ + "1.437420, 1.620241, 1.802983, 2.097801, 2.667683",\ + "2.009078, 2.191900, 2.374642, 2.669460, 3.239341"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.032950, 0.032950, 0.032950, 0.032950, 0.032950",\ + "0.148290, 0.148290, 0.148290, 0.148290, 0.148290",\ + "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\ + "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\ + "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\ + "0.032950, 0.032950, 0.032950, 0.032950, 0.032950",\ + "0.148290, 0.148290, 0.148290, 0.148290, 0.148290",\ + "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\ + "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\ + "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\ + "0.032950, 0.032950, 0.032950, 0.032950, 0.032950",\ + "0.148290, 0.148290, 0.148290, 0.148290, 0.148290",\ + "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\ + "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\ + "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\ + "0.032950, 0.032950, 0.032950, 0.032950, 0.032950",\ + "0.148290, 0.148290, 0.148290, 0.148290, 0.148290",\ + "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\ + "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\ + "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\ + "0.032950, 0.032950, 0.032950, 0.032950, 0.032950",\ + "0.148290, 0.148290, 0.148290, 0.148290, 0.148290",\ + "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\ + "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\ + "2.136637, 2.136637, 2.136637, 2.136637, 2.136637"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.506490, 0.734939, 0.919745, 1.215248, 1.786338",\ + "0.532768, 0.761737, 0.946551, 1.242086, 1.813247",\ + "0.574154, 0.803122, 0.987937, 1.283471, 1.854632",\ + "0.696473, 0.925441, 1.110256, 1.405790, 1.976951",\ + "1.028706, 1.257674, 1.442488, 1.738023, 2.309184",\ + "0.594824, 0.822257, 1.007026, 1.302553, 1.873691",\ + "0.621100, 0.849055, 1.033832, 1.329391, 1.900600",\ + "0.662486, 0.890440, 1.075217, 1.370776, 1.941986",\ + "0.784805, 1.012759, 1.197537, 1.493095, 2.064305",\ + "1.117038, 1.344992, 1.529769, 1.825328, 2.396538",\ + "0.684045, 0.902590, 1.087053, 1.382582, 1.953723",\ + "0.710318, 0.929387, 1.113859, 1.409419, 1.980632",\ + "0.751704, 0.970773, 1.155244, 1.450805, 2.022017",\ + "0.874023, 1.093092, 1.277564, 1.573124, 2.144336",\ + "1.206255, 1.425324, 1.609796, 1.905357, 2.476569",\ + "0.747598, 0.960414, 1.144763, 1.440024, 2.010764",\ + "0.773868, 0.987212, 1.171569, 1.466862, 2.037673",\ + "0.815253, 1.028597, 1.212954, 1.508247, 2.079059",\ + "0.937573, 1.150916, 1.335273, 1.630566, 2.201378",\ + "1.269805, 1.483149, 1.667506, 1.962799, 2.533611",\ + "1.083412, 1.265686, 1.448421, 1.743207, 2.313017",\ + "1.109663, 1.292485, 1.475227, 1.770045, 2.339926",\ + "1.151049, 1.333870, 1.516612, 1.811430, 2.381312",\ + "1.273368, 1.456189, 1.638931, 1.933749, 2.503631",\ + "1.605601, 1.788422, 1.971164, 2.265982, 2.835864"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.039649, 0.039649, 0.039649, 0.039649, 0.039649",\ + "0.089554, 0.089554, 0.089554, 0.089554, 0.089554",\ + "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\ + "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\ + "1.065031, 1.065031, 1.065031, 1.065031, 1.065031",\ + "0.039649, 0.039649, 0.039649, 0.039649, 0.039649",\ + "0.089554, 0.089554, 0.089554, 0.089554, 0.089554",\ + "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\ + "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\ + "1.065031, 1.065031, 1.065031, 1.065031, 1.065031",\ + "0.039649, 0.039649, 0.039649, 0.039649, 0.039649",\ + "0.089554, 0.089554, 0.089554, 0.089554, 0.089554",\ + "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\ + "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\ + "1.065031, 1.065031, 1.065031, 1.065031, 1.065031",\ + "0.039649, 0.039649, 0.039649, 0.039649, 0.039649",\ + "0.089554, 0.089554, 0.089554, 0.089554, 0.089554",\ + "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\ + "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\ + "1.065031, 1.065031, 1.065031, 1.065031, 1.065031",\ + "0.039649, 0.039649, 0.039649, 0.039649, 0.039649",\ + "0.089554, 0.089554, 0.089554, 0.089554, 0.089554",\ + "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\ + "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\ + "1.065031, 1.065031, 1.065031, 1.065031, 1.065031"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_min_2733*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[40]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.434817, 0.671194, 0.861423, 1.166955, 1.757904",\ + "0.484677, 0.721055, 0.911284, 1.216816, 1.807764",\ + "0.586545, 0.822923, 1.013152, 1.318684, 1.909632",\ + "0.824407, 1.060784, 1.251013, 1.556545, 2.147494",\ + "1.396727, 1.633105, 1.823334, 2.128865, 2.719814",\ + "0.523312, 0.758513, 0.948704, 1.254260, 1.845257",\ + "0.573172, 0.808374, 0.998565, 1.304121, 1.895118",\ + "0.675041, 0.910242, 1.100433, 1.405989, 1.996986",\ + "0.912902, 1.148103, 1.338294, 1.643850, 2.234847",\ + "1.485222, 1.720423, 1.910614, 2.216170, 2.807168",\ + "0.612642, 0.838848, 1.028731, 1.334289, 1.925289",\ + "0.662503, 0.888709, 1.078592, 1.384149, 1.975149",\ + "0.764371, 0.990577, 1.180460, 1.486017, 2.077017",\ + "1.002232, 1.228438, 1.418321, 1.723879, 2.314878",\ + "1.574552, 1.800758, 1.990641, 2.296199, 2.887199",\ + "0.676136, 0.896683, 1.086453, 1.391755, 1.982376",\ + "0.725997, 0.946544, 1.136314, 1.441616, 2.032237",\ + "0.827865, 1.048412, 1.238182, 1.543484, 2.134105",\ + "1.065726, 1.286273, 1.476043, 1.781345, 2.371966",\ + "1.638046, 1.858593, 2.048363, 2.353665, 2.944287",\ + "1.011585, 1.202042, 1.390114, 1.694958, 2.284685",\ + "1.061446, 1.251903, 1.439975, 1.744819, 2.334546",\ + "1.163314, 1.353770, 1.541843, 1.846687, 2.436414",\ + "1.401175, 1.591632, 1.779704, 2.084548, 2.674275",\ + "1.973496, 2.163952, 2.352024, 2.656868, 3.246596"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.039800, 0.039800, 0.039800, 0.039800, 0.039800",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375010, 0.375010, 0.375010, 0.375010, 0.375010",\ + "0.869309, 0.869309, 0.869309, 0.869309, 0.869309",\ + "2.137202, 2.137202, 2.137202, 2.137202, 2.137202",\ + "0.039800, 0.039800, 0.039800, 0.039800, 0.039800",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375010, 0.375010, 0.375010, 0.375010, 0.375010",\ + "0.869309, 0.869309, 0.869309, 0.869309, 0.869309",\ + "2.137202, 2.137202, 2.137202, 2.137202, 2.137202",\ + "0.039800, 0.039800, 0.039800, 0.039800, 0.039800",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375010, 0.375010, 0.375010, 0.375010, 0.375010",\ + "0.869309, 0.869309, 0.869309, 0.869309, 0.869309",\ + "2.137202, 2.137202, 2.137202, 2.137202, 2.137202",\ + "0.039800, 0.039800, 0.039800, 0.039800, 0.039800",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375010, 0.375010, 0.375010, 0.375010, 0.375010",\ + "0.869309, 0.869309, 0.869309, 0.869309, 0.869309",\ + "2.137202, 2.137202, 2.137202, 2.137202, 2.137202",\ + "0.039800, 0.039800, 0.039800, 0.039800, 0.039800",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375010, 0.375010, 0.375010, 0.375010, 0.375010",\ + "0.869309, 0.869309, 0.869309, 0.869309, 0.869309",\ + "2.137202, 2.137202, 2.137202, 2.137202, 2.137202"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.475545, 0.711923, 0.902152, 1.207684, 1.798632",\ + "0.497895, 0.734273, 0.924502, 1.230033, 1.820982",\ + "0.539258, 0.775636, 0.965865, 1.271397, 1.862345",\ + "0.661294, 0.897672, 1.087901, 1.393432, 1.984381",\ + "0.992907, 1.229285, 1.419514, 1.725045, 2.315994",\ + "0.564040, 0.799242, 0.989433, 1.294989, 1.885986",\ + "0.586390, 0.821591, 1.011783, 1.317338, 1.908335",\ + "0.627753, 0.862955, 1.053146, 1.358702, 1.949699",\ + "0.749789, 0.984990, 1.175182, 1.480737, 2.071735",\ + "1.081402, 1.316603, 1.506794, 1.812350, 2.403347",\ + "0.653370, 0.879577, 1.069460, 1.375017, 1.966017",\ + "0.675720, 0.901927, 1.091810, 1.397367, 1.988367",\ + "0.717084, 0.943290, 1.133173, 1.438730, 2.029730",\ + "0.839119, 1.065326, 1.255209, 1.560766, 2.151766",\ + "1.170732, 1.396938, 1.586821, 1.892379, 2.483379",\ + "0.716865, 0.937412, 1.127182, 1.432483, 2.023105",\ + "0.739214, 0.959762, 1.149531, 1.454833, 2.045455",\ + "0.780578, 1.001125, 1.190895, 1.496197, 2.086818",\ + "0.902614, 1.123161, 1.312930, 1.618232, 2.208854",\ + "1.234226, 1.454773, 1.644543, 1.949845, 2.540467",\ + "1.052314, 1.242770, 1.430842, 1.735687, 2.325414",\ + "1.074664, 1.265120, 1.453192, 1.758036, 2.347764",\ + "1.116027, 1.306484, 1.494555, 1.799400, 2.389127",\ + "1.238063, 1.428519, 1.616591, 1.921436, 2.511163",\ + "1.569676, 1.760132, 1.948204, 2.253048, 2.842776"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\ + "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\ + "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\ + "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\ + "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_min_2365*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[46]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.415362, 0.648627, 0.834270, 1.134053, 1.714917",\ + "0.465223, 0.698488, 0.884131, 1.183914, 1.764778",\ + "0.567091, 0.800357, 0.985999, 1.285782, 1.866646",\ + "0.804953, 1.038218, 1.223860, 1.523643, 2.104508",\ + "1.377273, 1.610538, 1.796180, 2.095963, 2.676828",\ + "0.503768, 0.735946, 0.921550, 1.221358, 1.802271",\ + "0.553629, 0.785807, 0.971411, 1.271219, 1.852132",\ + "0.655497, 0.887675, 1.073280, 1.373087, 1.954000",\ + "0.893359, 1.125536, 1.311141, 1.610948, 2.191861",\ + "1.465679, 1.697857, 1.883461, 2.183269, 2.764181",\ + "0.592852, 0.816281, 1.001577, 1.301386, 1.882302",\ + "0.642713, 0.866142, 1.051438, 1.351248, 1.932163",\ + "0.744581, 0.968010, 1.153306, 1.453116, 2.034031",\ + "0.982442, 1.205871, 1.391168, 1.690977, 2.271893",\ + "1.554763, 1.778192, 1.963488, 2.263297, 2.844213",\ + "0.656124, 0.874112, 1.059288, 1.358840, 1.939366",\ + "0.705985, 0.923973, 1.109149, 1.408702, 1.989227",\ + "0.807853, 1.025841, 1.211017, 1.510570, 2.091095",\ + "1.045714, 1.263703, 1.448879, 1.748431, 2.328956",\ + "1.618035, 1.836023, 2.021199, 2.320751, 2.901277",\ + "0.990163, 1.179444, 1.362947, 1.662033, 2.241645",\ + "1.040024, 1.229305, 1.412809, 1.711895, 2.291506",\ + "1.141892, 1.331173, 1.514677, 1.813762, 2.393374",\ + "1.379753, 1.569034, 1.752538, 2.051624, 2.631236",\ + "1.952073, 2.141355, 2.324858, 2.623944, 3.203556"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.039801, 0.039801, 0.039801, 0.039801, 0.039801",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375010, 0.375010, 0.375010, 0.375010, 0.375010",\ + "0.869309, 0.869309, 0.869309, 0.869309, 0.869309",\ + "2.137202, 2.137202, 2.137202, 2.137202, 2.137202",\ + "0.039801, 0.039801, 0.039801, 0.039801, 0.039801",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375010, 0.375010, 0.375010, 0.375010, 0.375010",\ + "0.869309, 0.869309, 0.869309, 0.869309, 0.869309",\ + "2.137202, 2.137202, 2.137202, 2.137202, 2.137202",\ + "0.039801, 0.039801, 0.039801, 0.039801, 0.039801",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375010, 0.375010, 0.375010, 0.375010, 0.375010",\ + "0.869309, 0.869309, 0.869309, 0.869309, 0.869309",\ + "2.137202, 2.137202, 2.137202, 2.137202, 2.137202",\ + "0.039801, 0.039801, 0.039801, 0.039801, 0.039801",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375010, 0.375010, 0.375010, 0.375010, 0.375010",\ + "0.869309, 0.869309, 0.869309, 0.869309, 0.869309",\ + "2.137202, 2.137202, 2.137202, 2.137202, 2.137202",\ + "0.039801, 0.039801, 0.039801, 0.039801, 0.039801",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375010, 0.375010, 0.375010, 0.375010, 0.375010",\ + "0.869309, 0.869309, 0.869309, 0.869309, 0.869309",\ + "2.137202, 2.137202, 2.137202, 2.137202, 2.137202"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.456091, 0.689356, 0.874999, 1.174782, 1.755646",\ + "0.478441, 0.711706, 0.897348, 1.197132, 1.777996",\ + "0.519805, 0.753070, 0.938712, 1.238495, 1.819360",\ + "0.641840, 0.875105, 1.060748, 1.360531, 1.941395",\ + "0.973453, 1.206718, 1.392360, 1.692143, 2.273008",\ + "0.544497, 0.776675, 0.962279, 1.262087, 1.843000",\ + "0.566847, 0.799025, 0.984629, 1.284437, 1.865350",\ + "0.608211, 0.840388, 1.025993, 1.325800, 1.906713",\ + "0.730246, 0.962424, 1.148028, 1.447836, 2.028749",\ + "1.061859, 1.294037, 1.479641, 1.779449, 2.360361",\ + "0.633581, 0.857010, 1.042306, 1.342116, 1.923031",\ + "0.655931, 0.879360, 1.064656, 1.364465, 1.945381",\ + "0.697294, 0.920723, 1.106020, 1.405829, 1.986745",\ + "0.819330, 1.042759, 1.228055, 1.527864, 2.108780",\ + "1.150943, 1.374372, 1.559668, 1.859477, 2.440393",\ + "0.696853, 0.914841, 1.100017, 1.399570, 1.980095",\ + "0.719203, 0.937191, 1.122367, 1.421919, 2.002445",\ + "0.760566, 0.978555, 1.163731, 1.463283, 2.043808",\ + "0.882602, 1.100590, 1.285766, 1.585318, 2.165844",\ + "1.214215, 1.432203, 1.617379, 1.916931, 2.497457",\ + "1.030892, 1.220173, 1.403677, 1.702762, 2.282374",\ + "1.053242, 1.242523, 1.426026, 1.725112, 2.304724",\ + "1.094605, 1.283886, 1.467390, 1.766476, 2.346087",\ + "1.216641, 1.405922, 1.589425, 1.888511, 2.468123",\ + "1.548254, 1.737535, 1.921038, 2.220124, 2.799736"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\ + "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\ + "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\ + "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\ + "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_min_2479*/ + +} /* end of pin tl_o[4] */ + +pin("tl_o[3]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.034401 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : tl_o[3]; + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[20]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.510374, 0.770025, 1.057985, 1.558099, 2.558328",\ + "0.560483, 0.820133, 1.108094, 1.608212, 2.608449",\ + "0.649192, 0.908842, 1.196806, 1.696939, 2.697205",\ + "0.873358, 1.133008, 1.420973, 1.921111, 2.921387",\ + "1.425993, 1.685643, 1.973609, 2.473750, 3.474032",\ + "0.597787, 0.857587, 1.145651, 1.644814, 2.644262",\ + "0.647895, 0.907696, 1.195760, 1.694927, 2.694383",\ + "0.736605, 0.996405, 1.284473, 1.783654, 2.783139",\ + "0.960770, 1.220570, 1.508639, 2.007826, 3.007321",\ + "1.513405, 1.773205, 2.061275, 2.560465, 3.559966",\ + "0.678684, 0.946606, 1.233617, 1.732436, 2.731217",\ + "0.728793, 0.996715, 1.283726, 1.782550, 2.781338",\ + "0.817502, 1.085424, 1.372439, 1.871277, 2.870094",\ + "1.041668, 1.309589, 1.596606, 2.095448, 3.094276",\ + "1.594303, 1.862224, 2.149241, 2.648087, 3.646921",\ + "0.738268, 1.012297, 1.297762, 1.796350, 2.794726",\ + "0.788377, 1.062406, 1.347871, 1.846463, 2.844847",\ + "0.877086, 1.151115, 1.436584, 1.935190, 2.933603",\ + "1.101252, 1.375280, 1.660750, 2.159362, 3.157785",\ + "1.653887, 1.927915, 2.213386, 2.712001, 3.710430",\ + "1.071814, 1.377311, 1.649946, 2.145828, 3.140182",\ + "1.121922, 1.427420, 1.700056, 2.195941, 3.190303",\ + "1.210632, 1.516129, 1.788768, 2.284668, 3.279059",\ + "1.434798, 1.740294, 2.012935, 2.508840, 3.503241",\ + "1.987432, 2.292929, 2.565571, 3.061479, 4.055886"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.046974, 0.046974, 0.046974, 0.046974, 0.046974",\ + "0.140333, 0.140333, 0.140333, 0.140333, 0.140333",\ + "0.324731, 0.324733, 0.324746, 0.324779, 0.324846",\ + "0.855415, 0.855427, 0.855504, 0.855712, 0.856129",\ + "2.185958, 2.185963, 2.186002, 2.186108, 2.186319",\ + "0.046974, 0.046974, 0.046974, 0.046974, 0.046974",\ + "0.140333, 0.140333, 0.140333, 0.140333, 0.140333",\ + "0.324731, 0.324733, 0.324746, 0.324779, 0.324846",\ + "0.855415, 0.855427, 0.855504, 0.855712, 0.856129",\ + "2.185958, 2.185964, 2.186003, 2.186108, 2.186319",\ + "0.046974, 0.046974, 0.046974, 0.046974, 0.046974",\ + "0.140333, 0.140333, 0.140333, 0.140333, 0.140333",\ + "0.324731, 0.324733, 0.324746, 0.324779, 0.324846",\ + "0.855415, 0.855427, 0.855504, 0.855712, 0.856129",\ + "2.185958, 2.185964, 2.186003, 2.186108, 2.186319",\ + "0.046974, 0.046974, 0.046974, 0.046974, 0.046974",\ + "0.140333, 0.140333, 0.140333, 0.140333, 0.140333",\ + "0.324731, 0.324733, 0.324746, 0.324779, 0.324846",\ + "0.855415, 0.855427, 0.855504, 0.855712, 0.856129",\ + "2.185958, 2.185964, 2.186003, 2.186108, 2.186319",\ + "0.046974, 0.046974, 0.046974, 0.046974, 0.046974",\ + "0.140333, 0.140333, 0.140333, 0.140333, 0.140333",\ + "0.324731, 0.324734, 0.324746, 0.324779, 0.324846",\ + "0.855415, 0.855432, 0.855507, 0.855713, 0.856129",\ + "2.185958, 2.185966, 2.186004, 2.186108, 2.186319"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.546335, 0.805984, 1.093953, 1.594109, 2.594421",\ + "0.568030, 0.827679, 1.115650, 1.615810, 2.616129",\ + "0.609553, 0.869202, 1.157173, 1.657335, 2.657660",\ + "0.742836, 1.002485, 1.290455, 1.790615, 2.790934",\ + "1.091714, 1.351363, 1.639332, 2.139487, 3.139795",\ + "0.633748, 0.893546, 1.181620, 1.680824, 2.680355",\ + "0.655443, 0.915241, 1.203316, 1.702524, 2.702063",\ + "0.696966, 0.956764, 1.244839, 1.744050, 2.743593",\ + "0.830248, 1.090047, 1.378121, 1.877330, 2.876868",\ + "1.179126, 1.438925, 1.726998, 2.226201, 3.225729",\ + "0.714645, 0.982566, 1.269586, 1.768446, 2.767310",\ + "0.736340, 1.004261, 1.291282, 1.790147, 2.789018",\ + "0.777863, 1.045783, 1.332805, 1.831672, 2.830549",\ + "0.911146, 1.179066, 1.466088, 1.964952, 2.963823",\ + "1.260024, 1.527944, 1.814965, 2.313824, 3.312684",\ + "0.774229, 1.048256, 1.333731, 1.832360, 2.830819",\ + "0.795924, 1.069952, 1.355427, 1.854060, 2.852527",\ + "0.837447, 1.111474, 1.396950, 1.895586, 2.894058",\ + "0.970730, 1.244757, 1.530232, 2.028866, 3.027332",\ + "1.319608, 1.593635, 1.879110, 2.377737, 3.376193",\ + "1.107775, 1.413270, 1.685916, 2.181838, 3.176275",\ + "1.129470, 1.434965, 1.707612, 2.203538, 3.197983",\ + "1.170993, 1.476488, 1.749135, 2.245064, 3.239513",\ + "1.304275, 1.609771, 1.882417, 2.378344, 3.372788",\ + "1.653153, 1.958649, 2.231294, 2.727215, 3.721649"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.045624, 0.045624, 0.045626, 0.045626, 0.045626",\ + "0.082731, 0.082731, 0.082731, 0.082731, 0.082731",\ + "0.171712, 0.171713, 0.171715, 0.171723, 0.171737",\ + "0.455137, 0.455143, 0.455182, 0.455287, 0.455497",\ + "1.170722, 1.170724, 1.170739, 1.170779, 1.170860",\ + "0.045624, 0.045624, 0.045626, 0.045626, 0.045626",\ + "0.082731, 0.082731, 0.082731, 0.082731, 0.082731",\ + "0.171712, 0.171713, 0.171715, 0.171723, 0.171737",\ + "0.455137, 0.455143, 0.455182, 0.455287, 0.455497",\ + "1.170722, 1.170724, 1.170739, 1.170779, 1.170860",\ + "0.045624, 0.045624, 0.045626, 0.045626, 0.045626",\ + "0.082731, 0.082731, 0.082731, 0.082731, 0.082731",\ + "0.171712, 0.171713, 0.171715, 0.171723, 0.171737",\ + "0.455137, 0.455143, 0.455182, 0.455287, 0.455497",\ + "1.170722, 1.170724, 1.170739, 1.170779, 1.170860",\ + "0.045624, 0.045625, 0.045626, 0.045626, 0.045626",\ + "0.082731, 0.082731, 0.082731, 0.082731, 0.082731",\ + "0.171712, 0.171713, 0.171715, 0.171723, 0.171737",\ + "0.455137, 0.455143, 0.455182, 0.455287, 0.455497",\ + "1.170722, 1.170724, 1.170739, 1.170779, 1.170860",\ + "0.045624, 0.045625, 0.045626, 0.045626, 0.045626",\ + "0.082731, 0.082731, 0.082731, 0.082731, 0.082731",\ + "0.171712, 0.171713, 0.171715, 0.171723, 0.171737",\ + "0.455137, 0.455145, 0.455183, 0.455287, 0.455497",\ + "1.170722, 1.170725, 1.170740, 1.170779, 1.170860"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_2748*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[22]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.491611, 0.745113, 1.023814, 1.485459, 2.408749",\ + "0.541720, 0.795222, 1.073923, 1.535570, 2.458864",\ + "0.630429, 0.883931, 1.162634, 1.624290, 2.547600",\ + "0.854595, 1.108097, 1.386801, 1.848459, 2.771775",\ + "1.407230, 1.660732, 1.939436, 2.401096, 3.324415",\ + "0.579020, 0.832694, 1.111357, 1.572173, 2.494682",\ + "0.629129, 0.882803, 1.161466, 1.622284, 2.544798",\ + "0.717839, 0.971512, 1.250178, 1.711004, 2.633534",\ + "0.942004, 1.195678, 1.474344, 1.935173, 2.857708",\ + "1.494639, 1.748312, 2.026979, 2.487810, 3.410349",\ + "0.659835, 0.921740, 1.199320, 1.659795, 2.581637",\ + "0.709944, 0.971848, 1.249429, 1.709906, 2.631753",\ + "0.798653, 1.060558, 1.338141, 1.798626, 2.720489",\ + "1.022819, 1.284723, 1.562307, 2.022795, 2.944664",\ + "1.575454, 1.837358, 2.114943, 2.575432, 3.497304",\ + "0.717415, 0.987469, 1.263459, 1.723708, 2.645146",\ + "0.767524, 1.037577, 1.313568, 1.773819, 2.695262",\ + "0.856233, 1.126287, 1.402279, 1.862539, 2.783998",\ + "1.080399, 1.350452, 1.626446, 2.086708, 3.008173",\ + "1.633034, 1.903087, 2.179081, 2.639345, 3.560813",\ + "1.049306, 1.352971, 1.615251, 2.073024, 2.990602",\ + "1.099415, 1.403079, 1.665360, 2.123135, 3.040718",\ + "1.188124, 1.491788, 1.754072, 2.211854, 3.129454",\ + "1.412290, 1.715954, 1.978238, 2.436024, 3.353629",\ + "1.964925, 2.268589, 2.530873, 2.988661, 3.906269"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.046974, 0.046972, 0.046943, 0.046848, 0.046659",\ + "0.140333, 0.140333, 0.140330, 0.140323, 0.140308",\ + "0.324732, 0.324732, 0.324740, 0.324766, 0.324817",\ + "0.855415, 0.855418, 0.855468, 0.855628, 0.855950",\ + "2.185958, 2.185959, 2.185984, 2.186066, 2.186228",\ + "0.046974, 0.046972, 0.046943, 0.046848, 0.046659",\ + "0.140333, 0.140333, 0.140330, 0.140323, 0.140308",\ + "0.324732, 0.324732, 0.324740, 0.324766, 0.324817",\ + "0.855415, 0.855418, 0.855468, 0.855628, 0.855950",\ + "2.185958, 2.185959, 2.185985, 2.186066, 2.186228",\ + "0.046974, 0.046972, 0.046943, 0.046848, 0.046659",\ + "0.140333, 0.140333, 0.140330, 0.140323, 0.140308",\ + "0.324732, 0.324732, 0.324740, 0.324766, 0.324817",\ + "0.855415, 0.855418, 0.855468, 0.855628, 0.855950",\ + "2.185958, 2.185959, 2.185985, 2.186066, 2.186228",\ + "0.046974, 0.046972, 0.046943, 0.046848, 0.046659",\ + "0.140333, 0.140333, 0.140330, 0.140323, 0.140308",\ + "0.324732, 0.324732, 0.324740, 0.324766, 0.324817",\ + "0.855415, 0.855418, 0.855468, 0.855628, 0.855950",\ + "2.185958, 2.185959, 2.185985, 2.186066, 2.186228",\ + "0.046974, 0.046972, 0.046942, 0.046848, 0.046659",\ + "0.140333, 0.140333, 0.140330, 0.140323, 0.140308",\ + "0.324732, 0.324732, 0.324740, 0.324766, 0.324817",\ + "0.855415, 0.855419, 0.855470, 0.855629, 0.855950",\ + "2.185958, 2.185960, 2.185985, 2.186066, 2.186228"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.527572, 0.781074, 1.059780, 1.521448, 2.444784",\ + "0.549267, 0.802769, 1.081476, 1.543146, 2.466486",\ + "0.590790, 0.844292, 1.122999, 1.584671, 2.508013",\ + "0.724072, 0.977574, 1.256281, 1.717952, 2.641292",\ + "1.072951, 1.326452, 1.605159, 2.066826, 2.990160",\ + "0.614981, 0.868654, 1.147323, 1.608162, 2.530717",\ + "0.636677, 0.890350, 1.169019, 1.629860, 2.552420",\ + "0.678199, 0.931872, 1.210542, 1.671385, 2.593947",\ + "0.811482, 1.065155, 1.343825, 1.804666, 2.727225",\ + "1.160360, 1.414033, 1.692702, 2.153540, 3.076094",\ + "0.695796, 0.957700, 1.235286, 1.695784, 2.617672",\ + "0.717491, 0.979395, 1.256982, 1.717482, 2.639375",\ + "0.759014, 1.020918, 1.298506, 1.759007, 2.680902",\ + "0.892296, 1.154201, 1.431788, 1.892287, 2.814180",\ + "1.241175, 1.503079, 1.780665, 2.241162, 3.163049",\ + "0.753376, 1.023429, 1.299425, 1.759697, 2.681181",\ + "0.775071, 1.045124, 1.321121, 1.781395, 2.702884",\ + "0.816594, 1.086647, 1.362644, 1.822920, 2.744411",\ + "0.949877, 1.219929, 1.495926, 1.956201, 2.877689",\ + "1.298755, 1.568808, 1.844804, 2.305075, 3.226558",\ + "1.085267, 1.388931, 1.651218, 2.109013, 3.026638",\ + "1.106962, 1.410626, 1.672914, 2.130711, 3.048340",\ + "1.148485, 1.452149, 1.714437, 2.172235, 3.089867",\ + "1.281768, 1.585431, 1.847719, 2.305516, 3.223145",\ + "1.630646, 1.934309, 2.196596, 2.654391, 3.572014"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.045624, 0.045624, 0.045624, 0.045624, 0.045624",\ + "0.082731, 0.082731, 0.082731, 0.082731, 0.082731",\ + "0.171712, 0.171712, 0.171714, 0.171720, 0.171731",\ + "0.455137, 0.455138, 0.455163, 0.455244, 0.455407",\ + "1.170722, 1.170722, 1.170732, 1.170763, 1.170825",\ + "0.045624, 0.045624, 0.045624, 0.045624, 0.045624",\ + "0.082731, 0.082731, 0.082731, 0.082731, 0.082731",\ + "0.171712, 0.171712, 0.171714, 0.171720, 0.171731",\ + "0.455137, 0.455138, 0.455164, 0.455244, 0.455407",\ + "1.170722, 1.170722, 1.170732, 1.170763, 1.170825",\ + "0.045624, 0.045624, 0.045624, 0.045624, 0.045624",\ + "0.082731, 0.082731, 0.082731, 0.082731, 0.082731",\ + "0.171712, 0.171712, 0.171714, 0.171720, 0.171731",\ + "0.455137, 0.455138, 0.455164, 0.455244, 0.455407",\ + "1.170722, 1.170722, 1.170732, 1.170763, 1.170825",\ + "0.045624, 0.045624, 0.045624, 0.045624, 0.045624",\ + "0.082731, 0.082731, 0.082731, 0.082731, 0.082731",\ + "0.171712, 0.171712, 0.171714, 0.171720, 0.171731",\ + "0.455137, 0.455138, 0.455164, 0.455244, 0.455407",\ + "1.170722, 1.170722, 1.170732, 1.170763, 1.170825",\ + "0.045624, 0.045624, 0.045624, 0.045624, 0.045624",\ + "0.082731, 0.082731, 0.082731, 0.082731, 0.082731",\ + "0.171712, 0.171712, 0.171714, 0.171720, 0.171731",\ + "0.455137, 0.455139, 0.455164, 0.455245, 0.455407",\ + "1.170722, 1.170722, 1.170732, 1.170763, 1.170825"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_2324*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[31]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.570251, 0.828412, 1.116558, 1.622590, 2.634653",\ + "0.620360, 0.878521, 1.166668, 1.672702, 2.684771",\ + "0.709070, 0.967232, 1.255383, 1.761428, 2.773518",\ + "0.933236, 1.191399, 1.479551, 1.985599, 2.997696",\ + "1.485871, 1.744034, 2.032187, 2.538238, 3.550339",\ + "0.657660, 0.915972, 1.204241, 1.709304, 2.720587",\ + "0.707769, 0.966081, 1.254351, 1.759417, 2.770705",\ + "0.796479, 1.054792, 1.343066, 1.848142, 2.859451",\ + "1.020645, 1.278959, 1.567234, 2.072314, 3.083630",\ + "1.573280, 1.831594, 2.119870, 2.624952, 3.636273",\ + "0.738545, 1.004968, 1.292206, 1.796926, 2.807542",\ + "0.788654, 1.055077, 1.342316, 1.847038, 2.857660",\ + "0.877364, 1.143789, 1.431032, 1.935764, 2.946406",\ + "1.101530, 1.367955, 1.655199, 2.159935, 3.170585",\ + "1.654165, 1.920590, 2.207835, 2.712574, 3.723228",\ + "0.799029, 1.070625, 1.356352, 1.860839, 2.871051",\ + "0.849138, 1.120734, 1.406462, 1.910952, 2.921169",\ + "0.937848, 1.209445, 1.495178, 1.999677, 3.009915",\ + "1.162014, 1.433611, 1.719345, 2.223849, 3.234094",\ + "1.714649, 1.986246, 2.271981, 2.776487, 3.786737",\ + "1.134610, 1.435289, 1.708595, 2.210337, 3.216507",\ + "1.184719, 1.485398, 1.758705, 2.260450, 3.266625",\ + "1.273429, 1.574110, 1.847420, 2.349176, 3.355371",\ + "1.497595, 1.798276, 2.071588, 2.573347, 3.579550",\ + "2.050230, 2.350911, 2.624224, 3.125986, 4.132193"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.046967, 0.046968, 0.046968, 0.046968, 0.046968",\ + "0.140332, 0.140332, 0.140332, 0.140332, 0.140332",\ + "0.324733, 0.324734, 0.324740, 0.324758, 0.324793",\ + "0.855426, 0.855431, 0.855470, 0.855580, 0.855800",\ + "2.185963, 2.185966, 2.185986, 2.186041, 2.186152",\ + "0.046967, 0.046968, 0.046968, 0.046968, 0.046968",\ + "0.140332, 0.140332, 0.140332, 0.140332, 0.140332",\ + "0.324733, 0.324734, 0.324740, 0.324758, 0.324793",\ + "0.855426, 0.855431, 0.855470, 0.855580, 0.855800",\ + "2.185963, 2.185966, 2.185986, 2.186041, 2.186152",\ + "0.046967, 0.046968, 0.046968, 0.046968, 0.046968",\ + "0.140332, 0.140332, 0.140332, 0.140332, 0.140332",\ + "0.324733, 0.324734, 0.324740, 0.324758, 0.324793",\ + "0.855426, 0.855431, 0.855470, 0.855580, 0.855800",\ + "2.185963, 2.185966, 2.185986, 2.186041, 2.186152",\ + "0.046967, 0.046968, 0.046968, 0.046968, 0.046968",\ + "0.140332, 0.140332, 0.140332, 0.140332, 0.140332",\ + "0.324733, 0.324734, 0.324740, 0.324758, 0.324793",\ + "0.855426, 0.855431, 0.855470, 0.855580, 0.855800",\ + "2.185963, 2.185966, 2.185986, 2.186041, 2.186152",\ + "0.046967, 0.046968, 0.046968, 0.046968, 0.046968",\ + "0.140332, 0.140332, 0.140332, 0.140332, 0.140332",\ + "0.324733, 0.324734, 0.324740, 0.324758, 0.324793",\ + "0.855426, 0.855433, 0.855471, 0.855580, 0.855800",\ + "2.185963, 2.185967, 2.185986, 2.186041, 2.186152"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.606214, 0.864377, 1.152534, 1.658596, 2.670718",\ + "0.627909, 0.886073, 1.174231, 1.680295, 2.692423",\ + "0.669432, 0.927596, 1.215755, 1.721821, 2.733952",\ + "0.802715, 1.060879, 1.349037, 1.855101, 2.867229",\ + "1.151593, 1.409756, 1.697913, 2.203973, 3.216093",\ + "0.693623, 0.951938, 1.240217, 1.745310, 2.756651",\ + "0.715318, 0.973633, 1.261914, 1.767010, 2.778357",\ + "0.756841, 1.015157, 1.303438, 1.808535, 2.819886",\ + "0.890124, 1.148439, 1.436720, 1.941815, 2.953162",\ + "1.239002, 1.497316, 1.785596, 2.290687, 3.302027",\ + "0.774507, 1.040934, 1.328183, 1.832932, 2.843606",\ + "0.796203, 1.062629, 1.349880, 1.854631, 2.865312",\ + "0.837726, 1.104153, 1.391404, 1.896157, 2.906841",\ + "0.971008, 1.237435, 1.524685, 2.029437, 3.040117",\ + "1.319886, 1.586312, 1.873561, 2.378309, 3.388982",\ + "0.834992, 1.106590, 1.392329, 1.896845, 2.907115",\ + "0.856687, 1.128286, 1.414026, 1.918545, 2.928821",\ + "0.898210, 1.169809, 1.455549, 1.960070, 2.970350",\ + "1.031493, 1.303092, 1.588831, 2.093350, 3.103626",\ + "1.380370, 1.651969, 1.937707, 2.442222, 3.452491",\ + "1.170573, 1.471255, 1.744571, 2.246343, 3.252572",\ + "1.192269, 1.492951, 1.766268, 2.268043, 3.274277",\ + "1.233792, 1.534474, 1.807792, 2.309569, 3.315806",\ + "1.367074, 1.667757, 1.941074, 2.442849, 3.449082",\ + "1.715952, 2.016634, 2.289950, 2.791721, 3.797947"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.045622, 0.045622, 0.045622, 0.045622, 0.045622",\ + "0.082730, 0.082730, 0.082730, 0.082730, 0.082730",\ + "0.171713, 0.171713, 0.171714, 0.171718, 0.171726",\ + "0.455143, 0.455145, 0.455165, 0.455220, 0.455331",\ + "1.170724, 1.170725, 1.170732, 1.170754, 1.170796",\ + "0.045622, 0.045622, 0.045622, 0.045622, 0.045622",\ + "0.082730, 0.082730, 0.082730, 0.082730, 0.082730",\ + "0.171713, 0.171713, 0.171714, 0.171718, 0.171726",\ + "0.455143, 0.455145, 0.455165, 0.455220, 0.455331",\ + "1.170724, 1.170725, 1.170732, 1.170754, 1.170796",\ + "0.045622, 0.045622, 0.045622, 0.045622, 0.045622",\ + "0.082730, 0.082730, 0.082730, 0.082730, 0.082730",\ + "0.171713, 0.171713, 0.171714, 0.171718, 0.171726",\ + "0.455143, 0.455145, 0.455165, 0.455220, 0.455331",\ + "1.170724, 1.170725, 1.170732, 1.170754, 1.170796",\ + "0.045622, 0.045622, 0.045622, 0.045622, 0.045622",\ + "0.082730, 0.082730, 0.082730, 0.082730, 0.082730",\ + "0.171713, 0.171713, 0.171714, 0.171718, 0.171726",\ + "0.455143, 0.455145, 0.455165, 0.455220, 0.455331",\ + "1.170724, 1.170725, 1.170732, 1.170754, 1.170796",\ + "0.045622, 0.045622, 0.045622, 0.045622, 0.045622",\ + "0.082730, 0.082730, 0.082730, 0.082730, 0.082730",\ + "0.171713, 0.171713, 0.171714, 0.171718, 0.171726",\ + "0.455143, 0.455146, 0.455165, 0.455220, 0.455331",\ + "1.170724, 1.170725, 1.170733, 1.170754, 1.170796"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_2270*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[33]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.553742, 0.804842, 1.083529, 1.550229, 2.483630",\ + "0.603850, 0.854951, 1.133639, 1.600341, 2.533747",\ + "0.692561, 0.943663, 1.222354, 1.689065, 2.622488",\ + "0.916727, 1.167829, 1.446522, 1.913236, 2.846664",\ + "1.469362, 1.720464, 1.999158, 2.465874, 3.399306",\ + "0.641147, 0.892423, 1.171086, 1.636943, 2.569564",\ + "0.691255, 0.942532, 1.221196, 1.687055, 2.619680",\ + "0.779966, 1.031244, 1.309911, 1.775779, 2.708421",\ + "1.004132, 1.255410, 1.534079, 1.999949, 2.932598",\ + "1.556767, 1.808045, 2.086715, 2.552587, 3.485240",\ + "0.721960, 0.981448, 1.259048, 1.724564, 2.656519",\ + "0.772069, 1.031557, 1.309159, 1.774676, 2.706635",\ + "0.860779, 1.120269, 1.397874, 1.863400, 2.795376",\ + "1.084945, 1.344435, 1.622041, 2.087571, 3.019553",\ + "1.637580, 1.897070, 2.174678, 2.640208, 3.572195",\ + "0.779579, 1.047145, 1.323188, 1.788477, 2.720028",\ + "0.829687, 1.097255, 1.373298, 1.838589, 2.770144",\ + "0.918398, 1.185966, 1.462013, 1.927313, 2.858885",\ + "1.142564, 1.410133, 1.686181, 2.151483, 3.083062",\ + "1.695199, 1.962768, 2.238817, 2.704121, 3.635704",\ + "1.113274, 1.412343, 1.675029, 2.137809, 3.065484",\ + "1.163383, 1.462452, 1.725139, 2.187922, 3.115601",\ + "1.252093, 1.551164, 1.813854, 2.276645, 3.204341",\ + "1.476259, 1.775330, 2.038022, 2.500816, 3.428518",\ + "2.028894, 2.327965, 2.590658, 3.053454, 3.981160"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.046966, 0.046965, 0.046949, 0.046900, 0.046802",\ + "0.140332, 0.140332, 0.140331, 0.140327, 0.140319",\ + "0.324733, 0.324734, 0.324738, 0.324752, 0.324778",\ + "0.855428, 0.855430, 0.855457, 0.855540, 0.855707",\ + "2.185964, 2.185965, 2.185979, 2.186021, 2.186105",\ + "0.046966, 0.046965, 0.046949, 0.046900, 0.046802",\ + "0.140332, 0.140332, 0.140331, 0.140327, 0.140319",\ + "0.324733, 0.324734, 0.324738, 0.324752, 0.324778",\ + "0.855428, 0.855430, 0.855457, 0.855540, 0.855707",\ + "2.185964, 2.185965, 2.185979, 2.186021, 2.186105",\ + "0.046966, 0.046965, 0.046949, 0.046900, 0.046802",\ + "0.140332, 0.140332, 0.140331, 0.140327, 0.140319",\ + "0.324733, 0.324734, 0.324738, 0.324752, 0.324778",\ + "0.855428, 0.855430, 0.855457, 0.855540, 0.855707",\ + "2.185964, 2.185965, 2.185979, 2.186021, 2.186105",\ + "0.046966, 0.046965, 0.046949, 0.046900, 0.046802",\ + "0.140332, 0.140332, 0.140331, 0.140327, 0.140319",\ + "0.324733, 0.324734, 0.324738, 0.324752, 0.324778",\ + "0.855428, 0.855430, 0.855457, 0.855540, 0.855707",\ + "2.185964, 2.185965, 2.185979, 2.186021, 2.186105",\ + "0.046966, 0.046965, 0.046949, 0.046900, 0.046802",\ + "0.140332, 0.140332, 0.140331, 0.140327, 0.140319",\ + "0.324733, 0.324734, 0.324738, 0.324752, 0.324778",\ + "0.855428, 0.855430, 0.855458, 0.855541, 0.855707",\ + "2.185964, 2.185965, 2.185979, 2.186021, 2.186105"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.589705, 0.840809, 1.119505, 1.586230, 2.519679",\ + "0.611400, 0.862504, 1.141202, 1.607929, 2.541383",\ + "0.652923, 0.904028, 1.182726, 1.649454, 2.582911",\ + "0.786206, 1.037310, 1.316008, 1.782735, 2.716188",\ + "1.135083, 1.386187, 1.664884, 2.131607, 3.065055",\ + "0.677110, 0.928390, 1.207063, 1.672943, 2.605613",\ + "0.698805, 0.950085, 1.228760, 1.694643, 2.627316",\ + "0.740328, 0.991609, 1.270283, 1.736168, 2.668845",\ + "0.873611, 1.124891, 1.403565, 1.869448, 2.802122",\ + "1.222489, 1.473768, 1.752441, 2.218321, 3.150989",\ + "0.757923, 1.017414, 1.295025, 1.760565, 2.692568",\ + "0.779619, 1.039110, 1.316722, 1.782264, 2.714272",\ + "0.821142, 1.080633, 1.358246, 1.823789, 2.755800",\ + "0.954424, 1.213916, 1.491528, 1.957069, 2.889077",\ + "1.303302, 1.562793, 1.840404, 2.305942, 3.237944",\ + "0.815542, 1.083112, 1.359165, 1.824477, 2.756077",\ + "0.837237, 1.104808, 1.380862, 1.846177, 2.777781",\ + "0.878760, 1.146331, 1.422385, 1.887702, 2.819309",\ + "1.012043, 1.279613, 1.555667, 2.020982, 2.952586",\ + "1.360920, 1.628491, 1.904543, 2.369855, 3.301453",\ + "1.149238, 1.448310, 1.711006, 2.173810, 3.101533",\ + "1.170933, 1.470006, 1.732703, 2.195509, 3.123237",\ + "1.212456, 1.511529, 1.774227, 2.237035, 3.164765",\ + "1.345739, 1.644811, 1.907508, 2.370315, 3.298042",\ + "1.694616, 1.993689, 2.256384, 2.719187, 3.646909"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.045622, 0.045620, 0.045614, 0.045600, 0.045572",\ + "0.082730, 0.082730, 0.082728, 0.082724, 0.082717",\ + "0.171713, 0.171713, 0.171714, 0.171717, 0.171723",\ + "0.455143, 0.455144, 0.455158, 0.455200, 0.455284",\ + "1.170724, 1.170725, 1.170730, 1.170746, 1.170779",\ + "0.045622, 0.045620, 0.045614, 0.045600, 0.045572",\ + "0.082730, 0.082730, 0.082728, 0.082724, 0.082717",\ + "0.171713, 0.171713, 0.171714, 0.171717, 0.171723",\ + "0.455143, 0.455144, 0.455158, 0.455200, 0.455284",\ + "1.170724, 1.170725, 1.170730, 1.170746, 1.170779",\ + "0.045622, 0.045620, 0.045614, 0.045600, 0.045572",\ + "0.082730, 0.082730, 0.082728, 0.082724, 0.082717",\ + "0.171713, 0.171713, 0.171714, 0.171717, 0.171723",\ + "0.455143, 0.455144, 0.455158, 0.455200, 0.455284",\ + "1.170724, 1.170725, 1.170730, 1.170746, 1.170779",\ + "0.045622, 0.045620, 0.045614, 0.045600, 0.045572",\ + "0.082730, 0.082730, 0.082728, 0.082724, 0.082717",\ + "0.171713, 0.171713, 0.171714, 0.171717, 0.171723",\ + "0.455143, 0.455144, 0.455158, 0.455200, 0.455284",\ + "1.170724, 1.170725, 1.170730, 1.170746, 1.170779",\ + "0.045622, 0.045620, 0.045614, 0.045600, 0.045572",\ + "0.082730, 0.082730, 0.082728, 0.082724, 0.082717",\ + "0.171713, 0.171713, 0.171714, 0.171717, 0.171723",\ + "0.455143, 0.455145, 0.455158, 0.455200, 0.455284",\ + "1.170724, 1.170725, 1.170730, 1.170746, 1.170779"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_2356*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[35]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.451072, 0.689495, 0.967641, 1.455853, 2.432276",\ + "0.493930, 0.732354, 1.010260, 1.497643, 2.472409",\ + "0.570383, 0.808808, 1.086665, 1.573880, 2.548310",\ + "0.793657, 1.032083, 1.309620, 1.795731, 2.767951",\ + "1.356346, 1.594772, 1.872207, 2.357962, 3.329473",\ + "0.538482, 0.777023, 1.055268, 1.542567, 2.518210",\ + "0.581340, 0.819882, 1.097884, 1.584358, 2.558343",\ + "0.657793, 0.896336, 1.174289, 1.660595, 2.634244",\ + "0.881067, 1.119611, 1.397241, 1.882445, 2.853885",\ + "1.443756, 1.682300, 1.959826, 2.444677, 3.415407",\ + "0.619344, 0.865949, 1.143233, 1.630189, 2.605165",\ + "0.662202, 0.908808, 1.185849, 1.671979, 2.645298",\ + "0.738655, 0.985262, 1.262254, 1.748217, 2.721199",\ + "0.961929, 1.208537, 1.485206, 1.970067, 2.940840",\ + "1.524618, 1.771226, 2.047791, 2.532299, 3.502362",\ + "0.677016, 0.931504, 1.207376, 1.694102, 2.668674",\ + "0.719874, 0.974362, 1.249992, 1.735892, 2.708807",\ + "0.796327, 1.050816, 1.326397, 1.812130, 2.784708",\ + "1.019601, 1.274091, 1.549348, 2.033980, 3.004349",\ + "1.582290, 1.836781, 2.111933, 2.596212, 3.565871",\ + "0.998045, 1.294967, 1.559438, 2.043528, 3.014130",\ + "1.040903, 1.337826, 1.602045, 2.085314, 3.054263",\ + "1.117357, 1.414280, 1.678448, 2.161551, 3.130164",\ + "1.340631, 1.637555, 1.901389, 2.383397, 3.349805",\ + "1.903320, 2.200244, 2.463970, 2.945627, 3.911327"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.072525, 0.072525, 0.072525, 0.072525, 0.072526",\ + "0.151107, 0.151107, 0.151107, 0.151107, 0.151107",\ + "0.326363, 0.326363, 0.326363, 0.326363, 0.326363",\ + "0.855550, 0.855550, 0.855550, 0.855550, 0.855551",\ + "2.186890, 2.186890, 2.186890, 2.186890, 2.186891",\ + "0.072525, 0.072525, 0.072525, 0.072525, 0.072526",\ + "0.151107, 0.151107, 0.151107, 0.151107, 0.151107",\ + "0.326363, 0.326363, 0.326363, 0.326363, 0.326363",\ + "0.855550, 0.855550, 0.855550, 0.855550, 0.855551",\ + "2.186890, 2.186890, 2.186890, 2.186890, 2.186891",\ + "0.072525, 0.072525, 0.072525, 0.072525, 0.072526",\ + "0.151107, 0.151107, 0.151107, 0.151107, 0.151107",\ + "0.326363, 0.326363, 0.326363, 0.326363, 0.326363",\ + "0.855550, 0.855550, 0.855550, 0.855550, 0.855551",\ + "2.186890, 2.186890, 2.186890, 2.186890, 2.186891",\ + "0.072525, 0.072525, 0.072525, 0.072525, 0.072526",\ + "0.151107, 0.151107, 0.151107, 0.151107, 0.151107",\ + "0.326363, 0.326363, 0.326363, 0.326363, 0.326363",\ + "0.855550, 0.855550, 0.855550, 0.855550, 0.855551",\ + "2.186890, 2.186890, 2.186890, 2.186890, 2.186891",\ + "0.072525, 0.072525, 0.072525, 0.072525, 0.072526",\ + "0.151107, 0.151107, 0.151107, 0.151107, 0.151107",\ + "0.326363, 0.326363, 0.326363, 0.326363, 0.326363",\ + "0.855550, 0.855550, 0.855550, 0.855550, 0.855551",\ + "2.186890, 2.186890, 2.186890, 2.186890, 2.186891"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.463085, 0.701506, 0.978942, 1.464699, 2.436214",\ + "0.490745, 0.729166, 1.006601, 1.492359, 2.463874",\ + "0.539949, 0.778370, 1.055805, 1.541563, 2.513078",\ + "0.680533, 0.918956, 1.196391, 1.682148, 2.653661",\ + "1.033170, 1.271589, 1.549246, 2.035768, 3.008812",\ + "0.550495, 0.789034, 1.066561, 1.551413, 2.522148",\ + "0.578155, 0.816694, 1.094220, 1.579073, 2.549807",\ + "0.627359, 0.865897, 1.143424, 1.628277, 2.599012",\ + "0.767943, 1.006484, 1.284010, 1.768862, 2.739595",\ + "1.120580, 1.359117, 1.636868, 2.122482, 3.094745",\ + "0.631357, 0.877960, 1.154525, 1.639035, 2.609103",\ + "0.659017, 0.905619, 1.182185, 1.666695, 2.636762",\ + "0.708221, 0.954823, 1.231389, 1.715899, 2.685967",\ + "0.848805, 1.095410, 1.371975, 1.856484, 2.826550",\ + "1.201442, 1.448043, 1.724832, 2.210104, 3.181700",\ + "0.689029, 0.943515, 1.218668, 1.702948, 2.672612",\ + "0.716689, 0.971174, 1.246328, 1.730608, 2.700271",\ + "0.765893, 1.020378, 1.295531, 1.779812, 2.749476",\ + "0.906477, 1.160964, 1.436117, 1.920397, 2.890059",\ + "1.259114, 1.513598, 1.788975, 2.274017, 3.245209",\ + "1.010056, 1.306978, 1.570705, 2.052364, 3.018068",\ + "1.037716, 1.334638, 1.598365, 2.080023, 3.045727",\ + "1.086920, 1.383842, 1.647568, 2.129227, 3.094932",\ + "1.227505, 1.524428, 1.788154, 2.269813, 3.235515",\ + "1.580140, 1.877061, 2.141020, 2.623435, 3.590666"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.031044, 0.031047, 0.031141, 0.031458, 0.032092",\ + "0.078404, 0.078404, 0.078413, 0.078441, 0.078497",\ + "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\ + "0.457145, 0.457145, 0.457145, 0.457145, 0.457145",\ + "1.169261, 1.169261, 1.169280, 1.169343, 1.169468",\ + "0.031044, 0.031047, 0.031142, 0.031458, 0.032092",\ + "0.078404, 0.078404, 0.078413, 0.078441, 0.078497",\ + "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\ + "0.457145, 0.457145, 0.457145, 0.457145, 0.457145",\ + "1.169261, 1.169261, 1.169280, 1.169343, 1.169468",\ + "0.031044, 0.031047, 0.031142, 0.031458, 0.032092",\ + "0.078404, 0.078404, 0.078413, 0.078441, 0.078497",\ + "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\ + "0.457145, 0.457145, 0.457145, 0.457145, 0.457145",\ + "1.169261, 1.169261, 1.169280, 1.169343, 1.169468",\ + "0.031044, 0.031047, 0.031142, 0.031458, 0.032092",\ + "0.078404, 0.078404, 0.078413, 0.078441, 0.078497",\ + "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\ + "0.457145, 0.457145, 0.457145, 0.457145, 0.457145",\ + "1.169261, 1.169261, 1.169280, 1.169343, 1.169468",\ + "0.031045, 0.031048, 0.031146, 0.031459, 0.032092",\ + "0.078404, 0.078404, 0.078413, 0.078441, 0.078497",\ + "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\ + "0.457145, 0.457145, 0.457145, 0.457145, 0.457145",\ + "1.169261, 1.169262, 1.169281, 1.169343, 1.169468"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_2423*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[36]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.549373, 0.808602, 1.094677, 1.588458, 2.576021",\ + "0.599470, 0.858699, 1.144772, 1.638553, 2.626115",\ + "0.688134, 0.947361, 1.233431, 1.727210, 2.714768",\ + "0.912284, 1.171509, 1.457578, 1.951357, 2.938914",\ + "1.464909, 1.724133, 2.010202, 2.503980, 3.491537",\ + "0.636786, 0.896164, 1.182323, 1.675173, 2.661954",\ + "0.686883, 0.946261, 1.232418, 1.725268, 2.712049",\ + "0.775547, 1.034922, 1.321077, 1.813925, 2.800702",\ + "0.999696, 1.259071, 1.545225, 2.038072, 3.024848",\ + "1.552321, 1.811695, 2.097848, 2.590695, 3.577471",\ + "0.717681, 0.985182, 1.270288, 1.762795, 2.748909",\ + "0.767778, 1.035279, 1.320384, 1.812890, 2.799004",\ + "0.856442, 1.123940, 1.409043, 1.901547, 2.887657",\ + "1.080592, 1.348089, 1.633190, 2.125694, 3.111803",\ + "1.633216, 1.900714, 2.185814, 2.678318, 3.664426",\ + "0.777205, 1.050872, 1.334432, 1.826709, 2.812418",\ + "0.827302, 1.100968, 1.384528, 1.876804, 2.862513",\ + "0.915966, 1.189630, 1.473186, 1.965461, 2.951166",\ + "1.140115, 1.413779, 1.697334, 2.189608, 3.175312",\ + "1.692740, 1.966403, 2.249958, 2.742231, 3.727935",\ + "1.110638, 1.415870, 1.686553, 2.176160, 3.157875",\ + "1.160735, 1.465966, 1.736648, 2.226255, 3.207969",\ + "1.249399, 1.554628, 1.825307, 2.314913, 3.296622",\ + "1.473549, 1.778776, 2.049454, 2.539060, 3.520768",\ + "2.026173, 2.331400, 2.602078, 3.091683, 4.073391"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.046980, 0.046981, 0.046983, 0.046983, 0.046983",\ + "0.140333, 0.140333, 0.140334, 0.140334, 0.140334",\ + "0.324730, 0.324730, 0.324730, 0.324732, 0.324735",\ + "0.855404, 0.855405, 0.855408, 0.855419, 0.855440",\ + "2.185952, 2.185953, 2.185954, 2.185960, 2.185970",\ + "0.046980, 0.046981, 0.046983, 0.046983, 0.046983",\ + "0.140333, 0.140333, 0.140334, 0.140334, 0.140334",\ + "0.324730, 0.324730, 0.324730, 0.324732, 0.324735",\ + "0.855404, 0.855405, 0.855408, 0.855419, 0.855440",\ + "2.185952, 2.185953, 2.185954, 2.185960, 2.185970",\ + "0.046980, 0.046981, 0.046983, 0.046983, 0.046983",\ + "0.140333, 0.140333, 0.140334, 0.140334, 0.140334",\ + "0.324730, 0.324730, 0.324730, 0.324732, 0.324735",\ + "0.855404, 0.855405, 0.855408, 0.855419, 0.855440",\ + "2.185952, 2.185953, 2.185954, 2.185960, 2.185970",\ + "0.046980, 0.046981, 0.046983, 0.046983, 0.046983",\ + "0.140333, 0.140333, 0.140334, 0.140334, 0.140334",\ + "0.324730, 0.324730, 0.324730, 0.324732, 0.324735",\ + "0.855405, 0.855405, 0.855408, 0.855419, 0.855440",\ + "2.185952, 2.185953, 2.185954, 2.185960, 2.185970",\ + "0.046980, 0.046982, 0.046983, 0.046983, 0.046983",\ + "0.140333, 0.140334, 0.140334, 0.140334, 0.140334",\ + "0.324730, 0.324730, 0.324730, 0.324732, 0.324735",\ + "0.855405, 0.855405, 0.855408, 0.855419, 0.855440",\ + "2.185952, 2.185953, 2.185954, 2.185960, 2.185970"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.585206, 0.844429, 1.130494, 1.624271, 2.611824",\ + "0.606889, 0.866111, 1.152175, 1.645951, 2.633503",\ + "0.648404, 0.907626, 1.193689, 1.687465, 2.675017",\ + "0.781694, 1.040916, 1.326981, 1.820757, 2.808309",\ + "1.130589, 1.389812, 1.675878, 2.169654, 3.157208",\ + "0.672619, 0.931991, 1.218140, 1.710986, 2.697757",\ + "0.694301, 0.953673, 1.239821, 1.732666, 2.719437",\ + "0.735816, 0.995187, 1.281336, 1.774180, 2.760951",\ + "0.869107, 1.128478, 1.414627, 1.907472, 2.894243",\ + "1.218002, 1.477374, 1.763524, 2.256369, 3.243142",\ + "0.753514, 1.021009, 1.306106, 1.798608, 2.784713",\ + "0.775196, 1.042691, 1.327787, 1.820288, 2.806392",\ + "0.816712, 1.084206, 1.369301, 1.861803, 2.847906",\ + "0.950002, 1.217496, 1.502593, 1.995094, 2.981198",\ + "1.298897, 1.566392, 1.851490, 2.343992, 3.330097",\ + "0.813038, 1.086698, 1.370250, 1.862521, 2.848222",\ + "0.834720, 1.108380, 1.391931, 1.884202, 2.869901",\ + "0.876235, 1.149895, 1.433445, 1.925716, 2.911415",\ + "1.009526, 1.283186, 1.566736, 2.059008, 3.044707",\ + "1.358421, 1.632081, 1.915633, 2.407905, 3.393606",\ + "1.146470, 1.451694, 1.722370, 2.211973, 3.193677",\ + "1.168153, 1.473376, 1.744051, 2.233654, 3.215357",\ + "1.209668, 1.514891, 1.785565, 2.275168, 3.256871",\ + "1.342959, 1.648182, 1.918857, 2.408459, 3.390163",\ + "1.691854, 1.997078, 2.267754, 2.757357, 3.739062"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.045699, 0.045703, 0.045708, 0.045711, 0.045717",\ + "0.082751, 0.082753, 0.082754, 0.082755, 0.082756",\ + "0.171712, 0.171712, 0.171712, 0.171712, 0.171713",\ + "0.455132, 0.455132, 0.455133, 0.455139, 0.455149",\ + "1.170720, 1.170720, 1.170720, 1.170722, 1.170727",\ + "0.045699, 0.045703, 0.045708, 0.045711, 0.045717",\ + "0.082751, 0.082753, 0.082754, 0.082755, 0.082756",\ + "0.171712, 0.171712, 0.171712, 0.171712, 0.171713",\ + "0.455132, 0.455132, 0.455133, 0.455139, 0.455149",\ + "1.170720, 1.170720, 1.170720, 1.170722, 1.170727",\ + "0.045699, 0.045703, 0.045708, 0.045711, 0.045717",\ + "0.082751, 0.082753, 0.082754, 0.082755, 0.082756",\ + "0.171712, 0.171712, 0.171712, 0.171712, 0.171713",\ + "0.455132, 0.455132, 0.455133, 0.455139, 0.455149",\ + "1.170720, 1.170720, 1.170720, 1.170722, 1.170727",\ + "0.045699, 0.045703, 0.045708, 0.045711, 0.045717",\ + "0.082752, 0.082753, 0.082754, 0.082755, 0.082756",\ + "0.171712, 0.171712, 0.171712, 0.171712, 0.171713",\ + "0.455132, 0.455132, 0.455133, 0.455139, 0.455149",\ + "1.170720, 1.170720, 1.170720, 1.170722, 1.170727",\ + "0.045700, 0.045704, 0.045708, 0.045711, 0.045717",\ + "0.082752, 0.082753, 0.082754, 0.082755, 0.082756",\ + "0.171712, 0.171712, 0.171712, 0.171712, 0.171713",\ + "0.455132, 0.455132, 0.455133, 0.455139, 0.455149",\ + "1.170720, 1.170720, 1.170720, 1.170722, 1.170727"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_2482*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[37]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.531759, 0.784650, 1.063366, 1.526559, 2.452945",\ + "0.581856, 0.834746, 1.113461, 1.576654, 2.503039",\ + "0.670520, 0.923407, 1.202119, 1.665310, 2.591694",\ + "0.894669, 1.147555, 1.426266, 1.889457, 2.815840",\ + "1.447294, 1.700179, 1.978889, 2.442080, 3.368464",\ + "0.619167, 0.872231, 1.150913, 1.613273, 2.538878",\ + "0.669264, 0.922327, 1.201009, 1.663368, 2.588973",\ + "0.757928, 1.010988, 1.289666, 1.752025, 2.677628",\ + "0.982077, 1.235136, 1.513813, 1.976171, 2.901774",\ + "1.534702, 1.787760, 2.066437, 2.528795, 3.454397",\ + "0.699981, 0.961270, 1.238877, 1.700895, 2.625834",\ + "0.750078, 1.011366, 1.288972, 1.750990, 2.675928",\ + "0.838742, 1.100027, 1.377629, 1.839646, 2.764583",\ + "1.062892, 1.324176, 1.601776, 2.063793, 2.988729",\ + "1.615517, 1.876800, 2.154400, 2.616416, 3.541352",\ + "0.757572, 1.026990, 1.303015, 1.764808, 2.689342",\ + "0.807669, 1.077086, 1.353110, 1.814903, 2.739437",\ + "0.896333, 1.165747, 1.441768, 1.903559, 2.828092",\ + "1.120482, 1.389895, 1.665915, 2.127706, 3.052238",\ + "1.673107, 1.942519, 2.218538, 2.680329, 3.604861",\ + "1.090182, 1.392406, 1.654823, 2.114129, 3.034798",\ + "1.140279, 1.442501, 1.704918, 2.164223, 3.084893",\ + "1.228943, 1.531161, 1.793575, 2.252880, 3.173548",\ + "1.453092, 1.755309, 2.017722, 2.477027, 3.397694",\ + "2.005717, 2.307933, 2.570345, 3.029650, 3.950317"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.046980, 0.046980, 0.046980, 0.046980, 0.046980",\ + "0.140333, 0.140333, 0.140333, 0.140333, 0.140333",\ + "0.324730, 0.324730, 0.324730, 0.324731, 0.324732",\ + "0.855404, 0.855404, 0.855405, 0.855410, 0.855418",\ + "2.185952, 2.185952, 2.185953, 2.185955, 2.185959",\ + "0.046980, 0.046980, 0.046980, 0.046980, 0.046980",\ + "0.140333, 0.140333, 0.140333, 0.140333, 0.140333",\ + "0.324730, 0.324730, 0.324730, 0.324731, 0.324732",\ + "0.855404, 0.855404, 0.855405, 0.855410, 0.855418",\ + "2.185952, 2.185952, 2.185953, 2.185955, 2.185959",\ + "0.046980, 0.046980, 0.046980, 0.046980, 0.046980",\ + "0.140333, 0.140333, 0.140333, 0.140333, 0.140333",\ + "0.324730, 0.324730, 0.324730, 0.324731, 0.324732",\ + "0.855404, 0.855404, 0.855405, 0.855410, 0.855418",\ + "2.185952, 2.185952, 2.185953, 2.185955, 2.185959",\ + "0.046980, 0.046980, 0.046980, 0.046980, 0.046980",\ + "0.140333, 0.140333, 0.140333, 0.140333, 0.140333",\ + "0.324730, 0.324730, 0.324730, 0.324731, 0.324732",\ + "0.855404, 0.855404, 0.855405, 0.855410, 0.855418",\ + "2.185952, 2.185952, 2.185953, 2.185955, 2.185959",\ + "0.046980, 0.046980, 0.046980, 0.046980, 0.046980",\ + "0.140333, 0.140333, 0.140333, 0.140333, 0.140333",\ + "0.324730, 0.324730, 0.324730, 0.324731, 0.324732",\ + "0.855404, 0.855404, 0.855406, 0.855410, 0.855418",\ + "2.185952, 2.185952, 2.185953, 2.185955, 2.185959"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.567591, 0.820473, 1.099180, 1.562370, 2.488752",\ + "0.589274, 0.842155, 1.120860, 1.584051, 2.510432",\ + "0.630789, 0.883670, 1.162374, 1.625565, 2.551946",\ + "0.764080, 1.016961, 1.295666, 1.758857, 2.685237",\ + "1.112975, 1.365857, 1.644563, 2.107754, 3.034136",\ + "0.655000, 0.908054, 1.186727, 1.649085, 2.574686",\ + "0.676682, 0.929736, 1.208408, 1.670765, 2.596366",\ + "0.718198, 0.971251, 1.249922, 1.712279, 2.637879",\ + "0.851488, 1.104542, 1.383214, 1.845571, 2.771171",\ + "1.200383, 1.453438, 1.732111, 2.194468, 3.120070",\ + "0.735814, 0.997094, 1.274690, 1.736706, 2.661641",\ + "0.757496, 1.018775, 1.296371, 1.758387, 2.683321",\ + "0.799012, 1.060290, 1.337885, 1.799901, 2.724834",\ + "0.932302, 1.193581, 1.471177, 1.933192, 2.858126",\ + "1.281197, 1.542477, 1.820074, 2.282090, 3.207025",\ + "0.793404, 1.062813, 1.338829, 1.800619, 2.725150",\ + "0.815087, 1.084495, 1.360510, 1.822300, 2.746830",\ + "0.856602, 1.126010, 1.402024, 1.863814, 2.788343",\ + "0.989893, 1.259301, 1.535315, 1.997105, 2.921635",\ + "1.338787, 1.608197, 1.884213, 2.346003, 3.270534",\ + "1.126013, 1.428226, 1.690636, 2.149940, 3.070606",\ + "1.147696, 1.449908, 1.712317, 2.171620, 3.092286",\ + "1.189211, 1.491422, 1.753831, 2.213135, 3.133800",\ + "1.322502, 1.624713, 1.887123, 2.346426, 3.267091",\ + "1.671397, 1.973610, 2.236020, 2.695324, 3.615990"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.045699, 0.045705, 0.045710, 0.045712, 0.045714",\ + "0.082751, 0.082753, 0.082755, 0.082755, 0.082756",\ + "0.171712, 0.171712, 0.171712, 0.171712, 0.171712",\ + "0.455131, 0.455131, 0.455132, 0.455134, 0.455138",\ + "1.170720, 1.170720, 1.170720, 1.170721, 1.170722",\ + "0.045699, 0.045705, 0.045710, 0.045712, 0.045714",\ + "0.082751, 0.082753, 0.082755, 0.082755, 0.082756",\ + "0.171712, 0.171712, 0.171712, 0.171712, 0.171712",\ + "0.455131, 0.455131, 0.455132, 0.455134, 0.455138",\ + "1.170720, 1.170720, 1.170720, 1.170721, 1.170722",\ + "0.045699, 0.045705, 0.045710, 0.045712, 0.045714",\ + "0.082751, 0.082753, 0.082755, 0.082755, 0.082756",\ + "0.171712, 0.171712, 0.171712, 0.171712, 0.171712",\ + "0.455131, 0.455131, 0.455132, 0.455134, 0.455138",\ + "1.170720, 1.170720, 1.170720, 1.170721, 1.170722",\ + "0.045699, 0.045705, 0.045710, 0.045712, 0.045714",\ + "0.082751, 0.082753, 0.082755, 0.082755, 0.082756",\ + "0.171712, 0.171712, 0.171712, 0.171712, 0.171712",\ + "0.455131, 0.455131, 0.455132, 0.455134, 0.455138",\ + "1.170720, 1.170720, 1.170720, 1.170721, 1.170722",\ + "0.045700, 0.045706, 0.045710, 0.045712, 0.045714",\ + "0.082752, 0.082753, 0.082755, 0.082755, 0.082756",\ + "0.171712, 0.171712, 0.171712, 0.171712, 0.171712",\ + "0.455131, 0.455131, 0.455132, 0.455134, 0.455138",\ + "1.170720, 1.170720, 1.170720, 1.170721, 1.170722"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_2546*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[39]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011"); + values ( "0.406169, 0.656592, 0.934420, 1.432277, 2.427991",\ + "0.449017, 0.699439, 0.977034, 1.474087, 2.468193",\ + "0.525461, 0.775882, 1.053428, 1.550312, 2.544081",\ + "0.748731, 0.999151, 1.276378, 1.772159, 2.763722",\ + "1.311413, 1.561833, 1.838149, 2.330786, 3.316060",\ + "0.493579, 0.744100, 1.022078, 1.518992, 2.513925",\ + "0.536427, 0.786947, 1.064689, 1.560801, 2.554126",\ + "0.612871, 0.863390, 1.141083, 1.637027, 2.630014",\ + "0.836140, 1.086659, 1.364029, 1.858874, 2.849656",\ + "1.398823, 1.649341, 1.925790, 2.417500, 3.401994",\ + "0.574430, 0.832981, 1.110043, 1.606613, 2.600880",\ + "0.617278, 0.875827, 1.152654, 1.648423, 2.641081",\ + "0.693722, 0.952271, 1.229048, 1.724649, 2.716969",\ + "0.916992, 1.175540, 1.451994, 1.946496, 2.936611",\ + "1.479674, 1.738222, 2.013755, 2.505122, 3.488949",\ + "0.633136, 0.898470, 1.174188, 1.670527, 2.664389",\ + "0.675984, 0.941316, 1.216799, 1.712336, 2.704590",\ + "0.752428, 1.017760, 1.293192, 1.788562, 2.780478",\ + "0.975698, 1.241029, 1.516138, 2.010409, 3.000120",\ + "1.538380, 1.803711, 2.077899, 2.569036, 3.552458",\ + "0.968049, 1.261165, 1.526347, 2.019992, 3.009845",\ + "1.010896, 1.304012, 1.568950, 2.061798, 3.050046",\ + "1.087340, 1.380455, 1.645342, 2.138023, 3.125935",\ + "1.310609, 1.603724, 1.868277, 2.359865, 3.345576",\ + "1.873291, 2.166406, 2.430006, 2.918479, 3.897913"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011"); + values ( "0.072784, 0.072803, 0.073020, 0.073739, 0.075177",\ + "0.151157, 0.151161, 0.151203, 0.151342, 0.151621",\ + "0.326364, 0.326364, 0.326365, 0.326368, 0.326373",\ + "0.855741, 0.855755, 0.855915, 0.856445, 0.857505",\ + "2.187214, 2.187237, 2.187508, 2.188406, 2.190202",\ + "0.072784, 0.072803, 0.073022, 0.073739, 0.075177",\ + "0.151157, 0.151161, 0.151203, 0.151342, 0.151621",\ + "0.326364, 0.326364, 0.326365, 0.326368, 0.326373",\ + "0.855741, 0.855755, 0.855917, 0.856445, 0.857505",\ + "2.187214, 2.187237, 2.187511, 2.188406, 2.190202",\ + "0.072785, 0.072803, 0.073022, 0.073739, 0.075177",\ + "0.151157, 0.151161, 0.151203, 0.151342, 0.151621",\ + "0.326364, 0.326364, 0.326365, 0.326368, 0.326373",\ + "0.855742, 0.855755, 0.855917, 0.856445, 0.857505",\ + "2.187214, 2.187238, 2.187511, 2.188406, 2.190202",\ + "0.072787, 0.072803, 0.073023, 0.073739, 0.075177",\ + "0.151157, 0.151161, 0.151203, 0.151342, 0.151621",\ + "0.326364, 0.326364, 0.326365, 0.326368, 0.326373",\ + "0.855743, 0.855755, 0.855917, 0.856445, 0.857505",\ + "2.187217, 2.187238, 2.187511, 2.188406, 2.190202",\ + "0.072792, 0.072806, 0.073030, 0.073742, 0.075177",\ + "0.151158, 0.151161, 0.151205, 0.151343, 0.151621",\ + "0.326364, 0.326364, 0.326365, 0.326368, 0.326373",\ + "0.855747, 0.855757, 0.855922, 0.856447, 0.857505",\ + "2.187224, 2.187241, 2.187521, 2.188410, 2.190202"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011"); + values ( "0.418201, 0.668626, 0.943179, 1.429721, 2.402805",\ + "0.445861, 0.696286, 0.970980, 1.458010, 2.432069",\ + "0.495070, 0.745495, 1.020403, 1.508166, 2.483693",\ + "0.635634, 0.886057, 1.161631, 1.651703, 2.631847",\ + "0.988299, 1.238725, 1.516052, 2.012175, 3.004421",\ + "0.505610, 0.756134, 1.030800, 1.516435, 2.488739",\ + "0.533270, 0.783794, 1.058603, 1.544724, 2.518003",\ + "0.582480, 0.833003, 1.108028, 1.594880, 2.569627",\ + "0.723043, 0.973565, 1.249264, 1.738417, 2.717781",\ + "1.075708, 1.326233, 1.603704, 2.098890, 3.090355",\ + "0.586462, 0.845014, 1.118765, 1.604057, 2.575694",\ + "0.614122, 0.872674, 1.146568, 1.632346, 2.604958",\ + "0.663331, 0.921884, 1.195993, 1.682502, 2.656582",\ + "0.803894, 1.062445, 1.337229, 1.826039, 2.804736",\ + "1.156560, 1.415114, 1.691670, 2.186512, 3.177310",\ + "0.645168, 0.910503, 1.182908, 1.667970, 2.639203",\ + "0.672828, 0.938163, 1.210711, 1.696259, 2.668467",\ + "0.722037, 0.987373, 1.260136, 1.746415, 2.720091",\ + "0.862600, 1.127934, 1.401372, 1.889952, 2.868245",\ + "1.215266, 1.480603, 1.755814, 2.250425, 3.240819",\ + "0.980081, 1.273199, 1.534953, 2.017389, 2.984659",\ + "1.007741, 1.300859, 1.562760, 2.045680, 3.013923",\ + "1.056951, 1.350069, 1.612193, 2.095839, 3.065547",\ + "1.197513, 1.490629, 1.753453, 2.239386, 3.213701",\ + "1.550180, 1.843298, 2.107956, 2.599883, 3.586275"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011"); + values ( "0.031046, 0.031099, 0.031481, 0.032572, 0.034755",\ + "0.078404, 0.078409, 0.078443, 0.078540, 0.078733",\ + "0.173504, 0.173502, 0.173487, 0.173444, 0.173357",\ + "0.457144, 0.457135, 0.457066, 0.456868, 0.456473",\ + "1.169261, 1.169272, 1.169347, 1.169562, 1.169994",\ + "0.031046, 0.031099, 0.031484, 0.032572, 0.034755",\ + "0.078404, 0.078409, 0.078443, 0.078540, 0.078733",\ + "0.173504, 0.173502, 0.173487, 0.173444, 0.173357",\ + "0.457144, 0.457135, 0.457065, 0.456868, 0.456473",\ + "1.169261, 1.169272, 1.169348, 1.169562, 1.169994",\ + "0.031046, 0.031100, 0.031484, 0.032572, 0.034755",\ + "0.078404, 0.078409, 0.078443, 0.078540, 0.078733",\ + "0.173504, 0.173502, 0.173487, 0.173444, 0.173357",\ + "0.457144, 0.457134, 0.457065, 0.456868, 0.456473",\ + "1.169261, 1.169272, 1.169348, 1.169562, 1.169994",\ + "0.031048, 0.031101, 0.031484, 0.032572, 0.034755",\ + "0.078404, 0.078409, 0.078443, 0.078540, 0.078733",\ + "0.173504, 0.173502, 0.173487, 0.173444, 0.173357",\ + "0.457144, 0.457134, 0.457065, 0.456868, 0.456473",\ + "1.169261, 1.169272, 1.169348, 1.169562, 1.169994",\ + "0.031051, 0.031118, 0.031495, 0.032577, 0.034755",\ + "0.078405, 0.078410, 0.078444, 0.078540, 0.078733",\ + "0.173504, 0.173502, 0.173487, 0.173443, 0.173357",\ + "0.457143, 0.457131, 0.457063, 0.456867, 0.456473",\ + "1.169262, 1.169275, 1.169350, 1.169563, 1.169994"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_2619*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[41]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.553465, 0.819964, 1.109829, 1.605668, 2.597345",\ + "0.603560, 0.870058, 1.159923, 1.655763, 2.647441",\ + "0.692214, 0.958711, 1.248576, 1.744417, 2.736099",\ + "0.916360, 1.182856, 1.472721, 1.968563, 2.960246",\ + "1.468983, 1.735479, 2.025344, 2.521186, 3.512870",\ + "0.640874, 0.907555, 1.197480, 1.692382, 2.683279",\ + "0.690968, 0.957649, 1.247574, 1.742477, 2.733375",\ + "0.779622, 1.046302, 1.336226, 1.831131, 2.822032",\ + "1.003768, 1.270447, 1.560372, 2.055277, 3.046180",\ + "1.556391, 1.823070, 2.112994, 2.607900, 3.598804",\ + "0.721784, 0.996619, 1.285445, 1.780004, 2.770234",\ + "0.771879, 1.046713, 1.335539, 1.830098, 2.820330",\ + "0.860533, 1.135366, 1.424191, 1.918753, 2.908988",\ + "1.084679, 1.359511, 1.648337, 2.142899, 3.133135",\ + "1.637302, 1.912134, 2.200959, 2.695522, 3.685759",\ + "0.783629, 1.062374, 1.349589, 1.843917, 2.833743",\ + "0.833723, 1.112468, 1.399683, 1.894011, 2.883839",\ + "0.922377, 1.201121, 1.488336, 1.982666, 2.972497",\ + "1.146523, 1.425267, 1.712481, 2.206812, 3.196644",\ + "1.699146, 1.977889, 2.265103, 2.759435, 3.749268",\ + "1.121586, 1.428200, 1.701728, 2.193373, 3.179199",\ + "1.171680, 1.478294, 1.751822, 2.243467, 3.229295",\ + "1.260334, 1.566947, 1.840474, 2.332122, 3.317953",\ + "1.484480, 1.791093, 2.064620, 2.556268, 3.542100",\ + "2.037102, 2.343715, 2.617242, 3.108891, 4.094724"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.046988, 0.046989, 0.046990, 0.046990, 0.046990",\ + "0.140334, 0.140334, 0.140334, 0.140334, 0.140334",\ + "0.324728, 0.324728, 0.324728, 0.324730, 0.324733",\ + "0.855392, 0.855392, 0.855394, 0.855403, 0.855422",\ + "2.185946, 2.185946, 2.185947, 2.185952, 2.185961",\ + "0.046988, 0.046989, 0.046990, 0.046990, 0.046990",\ + "0.140334, 0.140334, 0.140334, 0.140334, 0.140334",\ + "0.324728, 0.324728, 0.324728, 0.324730, 0.324733",\ + "0.855392, 0.855392, 0.855394, 0.855403, 0.855422",\ + "2.185946, 2.185946, 2.185947, 2.185952, 2.185961",\ + "0.046988, 0.046989, 0.046990, 0.046990, 0.046990",\ + "0.140334, 0.140334, 0.140334, 0.140334, 0.140334",\ + "0.324728, 0.324728, 0.324728, 0.324730, 0.324733",\ + "0.855392, 0.855392, 0.855394, 0.855403, 0.855422",\ + "2.185946, 2.185946, 2.185947, 2.185952, 2.185961",\ + "0.046988, 0.046989, 0.046990, 0.046990, 0.046990",\ + "0.140334, 0.140334, 0.140334, 0.140334, 0.140334",\ + "0.324728, 0.324728, 0.324728, 0.324730, 0.324733",\ + "0.855392, 0.855392, 0.855394, 0.855403, 0.855422",\ + "2.185946, 2.185946, 2.185947, 2.185952, 2.185961",\ + "0.046988, 0.046989, 0.046990, 0.046990, 0.046990",\ + "0.140334, 0.140334, 0.140334, 0.140334, 0.140334",\ + "0.324728, 0.324728, 0.324728, 0.324730, 0.324733",\ + "0.855392, 0.855392, 0.855394, 0.855403, 0.855422",\ + "2.185946, 2.185946, 2.185947, 2.185952, 2.185961"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.589270, 0.855765, 1.145630, 1.641474, 2.633161",\ + "0.610950, 0.877444, 1.167309, 1.663153, 2.654842",\ + "0.652464, 0.918958, 1.208822, 1.704667, 2.696356",\ + "0.785756, 1.052250, 1.342115, 1.837959, 2.829648",\ + "1.134654, 1.401149, 1.691014, 2.186858, 3.178545",\ + "0.676679, 0.943356, 1.233280, 1.728188, 2.719095",\ + "0.698358, 0.965036, 1.254959, 1.749868, 2.740776",\ + "0.739872, 1.006549, 1.296473, 1.791381, 2.782290",\ + "0.873164, 1.139841, 1.429765, 1.924673, 2.915581",\ + "1.222063, 1.488740, 1.778664, 2.273572, 3.264479",\ + "0.757589, 1.032420, 1.321245, 1.815809, 2.806050",\ + "0.779269, 1.054100, 1.342925, 1.837489, 2.827731",\ + "0.820783, 1.095613, 1.384438, 1.879003, 2.869245",\ + "0.954075, 1.228905, 1.517730, 2.012295, 3.002537",\ + "1.302974, 1.577804, 1.866629, 2.361193, 3.351434",\ + "0.819433, 1.098175, 1.385389, 1.879722, 2.869559",\ + "0.841113, 1.119855, 1.407069, 1.901402, 2.891240",\ + "0.882627, 1.161368, 1.448582, 1.942916, 2.932754",\ + "1.015919, 1.294661, 1.581874, 2.076208, 3.066046",\ + "1.364817, 1.643559, 1.930773, 2.425107, 3.414943",\ + "1.157390, 1.464001, 1.737528, 2.229178, 3.215015",\ + "1.179069, 1.485680, 1.759207, 2.250858, 3.236696",\ + "1.220583, 1.527194, 1.800721, 2.292372, 3.278210",\ + "1.353875, 1.660486, 1.934013, 2.425664, 3.411501",\ + "1.702774, 2.009385, 2.282912, 2.774562, 3.760399"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.045715, 0.045718, 0.045719, 0.045719, 0.045719",\ + "0.082756, 0.082757, 0.082757, 0.082757, 0.082757",\ + "0.171711, 0.171711, 0.171711, 0.171712, 0.171712",\ + "0.455125, 0.455125, 0.455126, 0.455131, 0.455140",\ + "1.170717, 1.170717, 1.170718, 1.170720, 1.170723",\ + "0.045715, 0.045718, 0.045719, 0.045719, 0.045719",\ + "0.082756, 0.082757, 0.082757, 0.082757, 0.082757",\ + "0.171711, 0.171711, 0.171711, 0.171712, 0.171712",\ + "0.455125, 0.455125, 0.455126, 0.455131, 0.455140",\ + "1.170717, 1.170717, 1.170718, 1.170720, 1.170723",\ + "0.045715, 0.045718, 0.045719, 0.045719, 0.045719",\ + "0.082756, 0.082757, 0.082757, 0.082757, 0.082757",\ + "0.171711, 0.171711, 0.171711, 0.171712, 0.171712",\ + "0.455125, 0.455125, 0.455126, 0.455131, 0.455140",\ + "1.170717, 1.170717, 1.170718, 1.170720, 1.170723",\ + "0.045716, 0.045718, 0.045719, 0.045719, 0.045719",\ + "0.082756, 0.082757, 0.082757, 0.082757, 0.082757",\ + "0.171711, 0.171711, 0.171711, 0.171712, 0.171712",\ + "0.455125, 0.455125, 0.455126, 0.455131, 0.455140",\ + "1.170717, 1.170717, 1.170718, 1.170720, 1.170723",\ + "0.045716, 0.045718, 0.045719, 0.045719, 0.045719",\ + "0.082756, 0.082757, 0.082757, 0.082757, 0.082757",\ + "0.171711, 0.171711, 0.171711, 0.171712, 0.171712",\ + "0.455125, 0.455125, 0.455126, 0.455131, 0.455140",\ + "1.170717, 1.170717, 1.170718, 1.170720, 1.170723"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_2551*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[42]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.535912, 0.788172, 1.068241, 1.533239, 2.463234",\ + "0.586006, 0.838266, 1.118335, 1.583333, 2.513329",\ + "0.674661, 0.926920, 1.206988, 1.671987, 2.601985",\ + "0.898807, 1.151066, 1.431133, 1.896132, 2.826131",\ + "1.451430, 1.703688, 1.983755, 2.448755, 3.378754",\ + "0.623320, 0.875758, 1.155794, 1.619953, 2.549168",\ + "0.673414, 0.925853, 1.205888, 1.670047, 2.599263",\ + "0.762069, 1.014506, 1.294541, 1.758701, 2.687918",\ + "0.986215, 1.238652, 1.518686, 1.982847, 2.912065",\ + "1.538838, 1.791275, 2.071309, 2.535469, 3.464688",\ + "0.704222, 0.964810, 1.243757, 1.707574, 2.636123",\ + "0.754316, 1.014904, 1.293851, 1.757668, 2.686218",\ + "0.842971, 1.103558, 1.382504, 1.846323, 2.774873",\ + "1.067117, 1.327704, 1.606649, 2.070468, 2.999020",\ + "1.619740, 1.880326, 2.159272, 2.623091, 3.551643",\ + "0.761984, 1.030547, 1.307896, 1.771487, 2.699632",\ + "0.812078, 1.080642, 1.357990, 1.821582, 2.749727",\ + "0.900733, 1.169295, 1.446643, 1.910236, 2.838382",\ + "1.124879, 1.393441, 1.670788, 2.134381, 3.062529",\ + "1.677502, 1.946064, 2.223411, 2.687004, 3.615152",\ + "1.092601, 1.396168, 1.659722, 2.120816, 3.045088",\ + "1.142695, 1.446262, 1.709816, 2.170910, 3.095183",\ + "1.231350, 1.534915, 1.798469, 2.259564, 3.183838",\ + "1.455496, 1.759061, 2.022614, 2.483710, 3.407985",\ + "2.008119, 2.311684, 2.575236, 3.036332, 3.960608"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.046988, 0.046989, 0.046990, 0.046990, 0.046990",\ + "0.140334, 0.140334, 0.140334, 0.140334, 0.140334",\ + "0.324728, 0.324728, 0.324728, 0.324729, 0.324730",\ + "0.855391, 0.855391, 0.855393, 0.855398, 0.855408",\ + "2.185946, 2.185946, 2.185946, 2.185949, 2.185954",\ + "0.046988, 0.046989, 0.046990, 0.046990, 0.046990",\ + "0.140334, 0.140334, 0.140334, 0.140334, 0.140334",\ + "0.324728, 0.324728, 0.324728, 0.324729, 0.324730",\ + "0.855391, 0.855391, 0.855393, 0.855398, 0.855408",\ + "2.185946, 2.185946, 2.185946, 2.185949, 2.185954",\ + "0.046988, 0.046989, 0.046990, 0.046990, 0.046990",\ + "0.140334, 0.140334, 0.140334, 0.140334, 0.140334",\ + "0.324728, 0.324728, 0.324728, 0.324729, 0.324730",\ + "0.855391, 0.855391, 0.855393, 0.855398, 0.855408",\ + "2.185946, 2.185946, 2.185946, 2.185949, 2.185954",\ + "0.046988, 0.046989, 0.046990, 0.046990, 0.046990",\ + "0.140334, 0.140334, 0.140334, 0.140334, 0.140334",\ + "0.324728, 0.324728, 0.324728, 0.324729, 0.324730",\ + "0.855391, 0.855391, 0.855393, 0.855398, 0.855408",\ + "2.185946, 2.185946, 2.185946, 2.185949, 2.185954",\ + "0.046988, 0.046989, 0.046990, 0.046990, 0.046990",\ + "0.140334, 0.140334, 0.140334, 0.140334, 0.140334",\ + "0.324728, 0.324728, 0.324728, 0.324729, 0.324730",\ + "0.855391, 0.855391, 0.855393, 0.855398, 0.855408",\ + "2.185946, 2.185946, 2.185946, 2.185949, 2.185954"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.571718, 0.823975, 1.104042, 1.569042, 2.499043",\ + "0.593398, 0.845655, 1.125721, 1.590722, 2.520724",\ + "0.634911, 0.887169, 1.167235, 1.632236, 2.562238",\ + "0.768203, 1.020461, 1.300527, 1.765528, 2.695529",\ + "1.117102, 1.369359, 1.649426, 2.114426, 3.044427",\ + "0.659126, 0.911562, 1.191595, 1.655756, 2.584977",\ + "0.680806, 0.933241, 1.213274, 1.677436, 2.606658",\ + "0.722320, 0.974755, 1.254788, 1.718950, 2.648171",\ + "0.855612, 1.108047, 1.388080, 1.852242, 2.781463",\ + "1.204510, 1.456946, 1.736979, 2.201141, 3.130361",\ + "0.740028, 1.000613, 1.279558, 1.743378, 2.671932",\ + "0.761708, 1.022293, 1.301237, 1.765058, 2.693613",\ + "0.803222, 1.063807, 1.342751, 1.806571, 2.735126",\ + "0.936514, 1.197099, 1.476043, 1.939863, 2.868418",\ + "1.285412, 1.545998, 1.824942, 2.288762, 3.217316",\ + "0.797790, 1.066351, 1.343697, 1.807291, 2.735441",\ + "0.819470, 1.088030, 1.365376, 1.828971, 2.757122",\ + "0.860984, 1.129544, 1.406890, 1.870484, 2.798635",\ + "0.994276, 1.262836, 1.540182, 2.003777, 2.931927",\ + "1.343174, 1.611735, 1.889081, 2.352675, 3.280825",\ + "1.128407, 1.431970, 1.695523, 2.156619, 3.080897",\ + "1.150087, 1.453650, 1.717202, 2.178299, 3.102577",\ + "1.191600, 1.495163, 1.758715, 2.219813, 3.144091",\ + "1.324893, 1.628456, 1.892008, 2.353105, 3.277383",\ + "1.673791, 1.977355, 2.240907, 2.702003, 3.626281"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.045715, 0.045716, 0.045718, 0.045718, 0.045718",\ + "0.082756, 0.082756, 0.082757, 0.082757, 0.082757",\ + "0.171711, 0.171711, 0.171711, 0.171712, 0.171712",\ + "0.455125, 0.455125, 0.455126, 0.455128, 0.455133",\ + "1.170717, 1.170717, 1.170717, 1.170718, 1.170720",\ + "0.045715, 0.045716, 0.045718, 0.045718, 0.045718",\ + "0.082756, 0.082756, 0.082757, 0.082757, 0.082757",\ + "0.171711, 0.171711, 0.171711, 0.171712, 0.171712",\ + "0.455125, 0.455125, 0.455126, 0.455128, 0.455133",\ + "1.170717, 1.170717, 1.170717, 1.170718, 1.170720",\ + "0.045715, 0.045716, 0.045718, 0.045718, 0.045718",\ + "0.082756, 0.082756, 0.082757, 0.082757, 0.082757",\ + "0.171711, 0.171711, 0.171711, 0.171712, 0.171712",\ + "0.455125, 0.455125, 0.455126, 0.455128, 0.455133",\ + "1.170717, 1.170717, 1.170717, 1.170718, 1.170720",\ + "0.045715, 0.045716, 0.045718, 0.045718, 0.045718",\ + "0.082756, 0.082756, 0.082757, 0.082757, 0.082757",\ + "0.171711, 0.171711, 0.171711, 0.171712, 0.171712",\ + "0.455125, 0.455125, 0.455126, 0.455128, 0.455133",\ + "1.170717, 1.170717, 1.170717, 1.170718, 1.170720",\ + "0.045715, 0.045717, 0.045718, 0.045718, 0.045718",\ + "0.082756, 0.082756, 0.082757, 0.082757, 0.082757",\ + "0.171711, 0.171711, 0.171711, 0.171712, 0.171712",\ + "0.455125, 0.455125, 0.455126, 0.455128, 0.455133",\ + "1.170717, 1.170717, 1.170717, 1.170718, 1.170720"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_2487*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[43]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011"); + values ( "0.552964, 0.814309, 1.099442, 1.604025, 2.613190",\ + "0.595811, 0.857156, 1.142289, 1.646869, 2.656030",\ + "0.672254, 0.933599, 1.218732, 1.723310, 2.732467",\ + "0.895523, 1.156868, 1.442001, 1.946579, 2.955732",\ + "1.458204, 1.719550, 2.004683, 2.509259, 3.518410",\ + "0.640373, 0.901851, 1.187121, 1.690739, 2.699123",\ + "0.683220, 0.944698, 1.229968, 1.733584, 2.741963",\ + "0.759663, 1.021142, 1.306411, 1.810025, 2.818400",\ + "0.982932, 1.244411, 1.529680, 2.033293, 3.041666",\ + "1.545614, 1.807093, 2.092361, 2.595973, 3.604344",\ + "0.723483, 0.990810, 1.275087, 1.778361, 2.786078",\ + "0.766329, 1.033657, 1.317933, 1.821205, 2.828918",\ + "0.842772, 1.110100, 1.394377, 1.897646, 2.905355",\ + "1.066041, 1.333369, 1.617646, 2.120914, 3.128621",\ + "1.628723, 1.896051, 2.180327, 2.683595, 3.691299",\ + "0.786922, 1.056412, 1.339232, 1.842274, 2.849587",\ + "0.829768, 1.099259, 1.382079, 1.885119, 2.892427",\ + "0.906211, 1.175702, 1.458522, 1.961560, 2.968864",\ + "1.129480, 1.398971, 1.681791, 2.184828, 3.192130",\ + "1.692162, 1.961653, 2.244473, 2.747508, 3.754808",\ + "1.122015, 1.420432, 1.691460, 2.191767, 3.195044",\ + "1.164862, 1.463279, 1.734307, 2.234612, 3.237884",\ + "1.241305, 1.539723, 1.810750, 2.311053, 3.314321",\ + "1.464574, 1.762992, 2.034019, 2.534321, 3.537586",\ + "2.027255, 2.325674, 2.596701, 3.097001, 4.100264"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011"); + values ( "0.072811, 0.072811, 0.072826, 0.072880, 0.072987",\ + "0.151162, 0.151162, 0.151165, 0.151176, 0.151196",\ + "0.326364, 0.326364, 0.326364, 0.326364, 0.326365",\ + "0.855761, 0.855761, 0.855772, 0.855812, 0.855891",\ + "2.187247, 2.187247, 2.187266, 2.187333, 2.187467",\ + "0.072811, 0.072811, 0.072827, 0.072880, 0.072987",\ + "0.151162, 0.151162, 0.151165, 0.151176, 0.151196",\ + "0.326364, 0.326364, 0.326364, 0.326364, 0.326365",\ + "0.855761, 0.855761, 0.855772, 0.855812, 0.855891",\ + "2.187247, 2.187247, 2.187267, 2.187333, 2.187467",\ + "0.072811, 0.072811, 0.072827, 0.072880, 0.072987",\ + "0.151162, 0.151162, 0.151165, 0.151176, 0.151196",\ + "0.326364, 0.326364, 0.326364, 0.326364, 0.326365",\ + "0.855761, 0.855761, 0.855772, 0.855812, 0.855891",\ + "2.187247, 2.187247, 2.187267, 2.187333, 2.187467",\ + "0.072811, 0.072811, 0.072827, 0.072880, 0.072987",\ + "0.151162, 0.151162, 0.151165, 0.151176, 0.151196",\ + "0.326364, 0.326364, 0.326364, 0.326364, 0.326365",\ + "0.855761, 0.855761, 0.855772, 0.855812, 0.855891",\ + "2.187247, 2.187247, 2.187267, 2.187333, 2.187467",\ + "0.072811, 0.072811, 0.072827, 0.072880, 0.072987",\ + "0.151162, 0.151162, 0.151165, 0.151176, 0.151196",\ + "0.326364, 0.326364, 0.326364, 0.326364, 0.326365",\ + "0.855761, 0.855761, 0.855773, 0.855812, 0.855891",\ + "2.187247, 2.187247, 2.187267, 2.187334, 2.187467"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011"); + values ( "0.564998, 0.826343, 1.111477, 1.616063, 2.625237",\ + "0.592658, 0.854002, 1.139137, 1.643723, 2.652897",\ + "0.641868, 0.903212, 1.188347, 1.692935, 2.702110",\ + "0.782429, 1.043773, 1.328907, 1.833490, 2.842657",\ + "1.135098, 1.396442, 1.681576, 2.186166, 3.195345",\ + "0.652408, 0.913885, 1.199155, 1.702778, 2.711171",\ + "0.680068, 0.941545, 1.226815, 1.730438, 2.738831",\ + "0.729278, 0.990755, 1.276025, 1.779649, 2.788044",\ + "0.869838, 1.131316, 1.416586, 1.920205, 2.928591",\ + "1.222507, 1.483984, 1.769255, 2.272880, 3.281279",\ + "0.735517, 1.002843, 1.287121, 1.790400, 2.798126",\ + "0.763177, 1.030503, 1.314781, 1.818060, 2.825786",\ + "0.812387, 1.079713, 1.363991, 1.867271, 2.874999",\ + "0.952947, 1.220274, 1.504552, 2.007827, 3.015546",\ + "1.305617, 1.572943, 1.857221, 2.360502, 3.368234",\ + "0.798956, 1.068446, 1.351267, 1.854313, 2.861635",\ + "0.826616, 1.096106, 1.378927, 1.881973, 2.889295",\ + "0.875826, 1.145315, 1.428137, 1.931184, 2.938508",\ + "1.016386, 1.285877, 1.568697, 2.071740, 3.079055",\ + "1.369056, 1.638545, 1.921366, 2.424415, 3.431743",\ + "1.134049, 1.432466, 1.703495, 2.203806, 3.207091",\ + "1.161709, 1.460126, 1.731154, 2.231466, 3.234751",\ + "1.210919, 1.509335, 1.780365, 2.280677, 3.283964",\ + "1.351480, 1.649897, 1.920925, 2.421233, 3.424510",\ + "1.704149, 2.002565, 2.273594, 2.773909, 3.777199"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011"); + values ( "0.031035, 0.031069, 0.031220, 0.031570, 0.032271",\ + "0.078403, 0.078406, 0.078420, 0.078451, 0.078513",\ + "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\ + "0.457146, 0.457146, 0.457146, 0.457146, 0.457146",\ + "1.169259, 1.169266, 1.169295, 1.169365, 1.169503",\ + "0.031035, 0.031069, 0.031221, 0.031570, 0.032271",\ + "0.078403, 0.078406, 0.078420, 0.078451, 0.078513",\ + "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\ + "0.457146, 0.457146, 0.457146, 0.457146, 0.457146",\ + "1.169259, 1.169266, 1.169296, 1.169365, 1.169503",\ + "0.031035, 0.031070, 0.031221, 0.031570, 0.032271",\ + "0.078403, 0.078406, 0.078420, 0.078451, 0.078513",\ + "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\ + "0.457146, 0.457146, 0.457146, 0.457146, 0.457146",\ + "1.169259, 1.169266, 1.169296, 1.169365, 1.169503",\ + "0.031035, 0.031071, 0.031221, 0.031570, 0.032271",\ + "0.078403, 0.078406, 0.078420, 0.078451, 0.078513",\ + "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\ + "0.457146, 0.457146, 0.457146, 0.457146, 0.457146",\ + "1.169259, 1.169266, 1.169296, 1.169365, 1.169503",\ + "0.031035, 0.031083, 0.031224, 0.031571, 0.032271",\ + "0.078403, 0.078407, 0.078420, 0.078451, 0.078513",\ + "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\ + "0.457146, 0.457146, 0.457146, 0.457146, 0.457146",\ + "1.169259, 1.169268, 1.169296, 1.169365, 1.169503"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[3]_redg*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[44]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011"); + values ( "0.538940, 0.779876, 1.050099, 1.503272, 2.409617",\ + "0.581786, 0.822723, 1.092946, 1.546117, 2.452459",\ + "0.658229, 0.899166, 1.169389, 1.622558, 2.528897",\ + "0.881498, 1.122435, 1.392658, 1.845826, 2.752164",\ + "1.444180, 1.685117, 1.955339, 2.408507, 3.314842",\ + "0.626346, 0.867426, 1.137614, 1.589986, 2.495551",\ + "0.669192, 0.910272, 1.180461, 1.632831, 2.538393",\ + "0.745635, 0.986716, 1.256904, 1.709272, 2.614831",\ + "0.968904, 1.209985, 1.480173, 1.932540, 2.838098",\ + "1.531586, 1.772666, 2.042854, 2.495221, 3.400776",\ + "0.707175, 0.956384, 1.225576, 1.677607, 2.582506",\ + "0.750022, 0.999231, 1.268423, 1.720452, 2.625348",\ + "0.826465, 1.075674, 1.344866, 1.796893, 2.701786",\ + "1.049734, 1.298944, 1.568135, 2.020162, 2.925053",\ + "1.612416, 1.861625, 2.130816, 2.582842, 3.487731",\ + "0.764818, 1.021986, 1.289713, 1.741520, 2.646015",\ + "0.807664, 1.064833, 1.332560, 1.784365, 2.688857",\ + "0.884107, 1.141276, 1.409003, 1.860806, 2.765295",\ + "1.107376, 1.364545, 1.632272, 2.084074, 2.988562",\ + "1.670058, 1.927227, 2.194953, 2.646755, 3.551240",\ + "1.090702, 1.386049, 1.641418, 2.090797, 2.991471",\ + "1.133548, 1.428896, 1.684264, 2.133642, 3.034313",\ + "1.209992, 1.505339, 1.760707, 2.210084, 3.110751",\ + "1.433261, 1.728608, 1.983976, 2.433352, 3.334018",\ + "1.995942, 2.291290, 2.546658, 2.996032, 3.896696"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011"); + values ( "0.072811, 0.072811, 0.072823, 0.072863, 0.072944",\ + "0.151162, 0.151162, 0.151164, 0.151172, 0.151188",\ + "0.326364, 0.326364, 0.326364, 0.326364, 0.326365",\ + "0.855761, 0.855761, 0.855770, 0.855800, 0.855859",\ + "2.187248, 2.187248, 2.187262, 2.187313, 2.187414",\ + "0.072811, 0.072811, 0.072823, 0.072863, 0.072944",\ + "0.151162, 0.151162, 0.151165, 0.151172, 0.151188",\ + "0.326364, 0.326364, 0.326364, 0.326364, 0.326365",\ + "0.855761, 0.855761, 0.855770, 0.855800, 0.855859",\ + "2.187248, 2.187248, 2.187262, 2.187313, 2.187414",\ + "0.072811, 0.072811, 0.072823, 0.072863, 0.072944",\ + "0.151162, 0.151162, 0.151165, 0.151172, 0.151188",\ + "0.326364, 0.326364, 0.326364, 0.326364, 0.326365",\ + "0.855761, 0.855761, 0.855770, 0.855800, 0.855859",\ + "2.187248, 2.187248, 2.187262, 2.187313, 2.187414",\ + "0.072811, 0.072811, 0.072823, 0.072863, 0.072944",\ + "0.151162, 0.151162, 0.151165, 0.151172, 0.151188",\ + "0.326364, 0.326364, 0.326364, 0.326364, 0.326365",\ + "0.855761, 0.855761, 0.855770, 0.855800, 0.855859",\ + "2.187248, 2.187248, 2.187263, 2.187313, 2.187414",\ + "0.072811, 0.072811, 0.072824, 0.072864, 0.072944",\ + "0.151162, 0.151162, 0.151165, 0.151172, 0.151188",\ + "0.326364, 0.326364, 0.326364, 0.326364, 0.326365",\ + "0.855761, 0.855761, 0.855770, 0.855800, 0.855859",\ + "2.187248, 2.187248, 2.187263, 2.187313, 2.187414"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011"); + values ( "0.550974, 0.791910, 1.062134, 1.515310, 2.421661",\ + "0.578634, 0.819570, 1.089794, 1.542970, 2.449322",\ + "0.627844, 0.868780, 1.139004, 1.592180, 2.498534",\ + "0.768404, 1.009341, 1.279564, 1.732737, 2.639084",\ + "1.121073, 1.362010, 1.632233, 2.085412, 2.991768",\ + "0.638380, 0.879460, 1.149649, 1.602023, 2.507595",\ + "0.666040, 0.907120, 1.177309, 1.629683, 2.535255",\ + "0.715250, 0.956330, 1.226519, 1.678894, 2.584468",\ + "0.855810, 1.096890, 1.367079, 1.819451, 2.725018",\ + "1.208480, 1.449559, 1.719748, 2.172125, 3.077702",\ + "0.719210, 0.968418, 1.237611, 1.689645, 2.594550",\ + "0.746870, 0.996078, 1.265271, 1.717305, 2.622211",\ + "0.796080, 1.045288, 1.314481, 1.766516, 2.671423",\ + "0.936640, 1.185849, 1.455041, 1.907072, 2.811973",\ + "1.289309, 1.538518, 1.807710, 2.259747, 3.164657",\ + "0.776852, 1.034020, 1.301748, 1.753558, 2.658059",\ + "0.804512, 1.061680, 1.329408, 1.781218, 2.685719",\ + "0.853722, 1.110890, 1.378618, 1.830429, 2.734932",\ + "0.994283, 1.251451, 1.519178, 1.970985, 2.875482",\ + "1.346952, 1.604120, 1.871847, 2.323660, 3.228166",\ + "1.102736, 1.398083, 1.653452, 2.102835, 3.003515",\ + "1.130396, 1.425743, 1.681112, 2.130495, 3.031176",\ + "1.179606, 1.474952, 1.730322, 2.179706, 3.080388",\ + "1.320167, 1.615513, 1.870883, 2.320263, 3.220938",\ + "1.672836, 1.968182, 2.223552, 2.672937, 3.573622"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011"); + values ( "0.031036, 0.031054, 0.031161, 0.031438, 0.031991",\ + "0.078403, 0.078405, 0.078414, 0.078439, 0.078488",\ + "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\ + "0.457146, 0.457146, 0.457146, 0.457146, 0.457146",\ + "1.169259, 1.169263, 1.169284, 1.169338, 1.169448",\ + "0.031036, 0.031055, 0.031162, 0.031438, 0.031991",\ + "0.078403, 0.078405, 0.078414, 0.078439, 0.078488",\ + "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\ + "0.457146, 0.457146, 0.457146, 0.457146, 0.457146",\ + "1.169259, 1.169263, 1.169284, 1.169338, 1.169448",\ + "0.031036, 0.031055, 0.031162, 0.031438, 0.031991",\ + "0.078403, 0.078405, 0.078414, 0.078439, 0.078488",\ + "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\ + "0.457146, 0.457146, 0.457146, 0.457146, 0.457146",\ + "1.169259, 1.169263, 1.169284, 1.169338, 1.169448",\ + "0.031036, 0.031055, 0.031162, 0.031438, 0.031991",\ + "0.078403, 0.078405, 0.078414, 0.078439, 0.078488",\ + "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\ + "0.457146, 0.457146, 0.457146, 0.457146, 0.457146",\ + "1.169259, 1.169263, 1.169284, 1.169338, 1.169448",\ + "0.031036, 0.031062, 0.031165, 0.031439, 0.031991",\ + "0.078403, 0.078406, 0.078415, 0.078439, 0.078488",\ + "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\ + "0.457146, 0.457146, 0.457146, 0.457146, 0.457146",\ + "1.169259, 1.169264, 1.169285, 1.169339, 1.169448"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_2727*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[46]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.564410, 0.823611, 1.109689, 1.603513, 2.591161",\ + "0.607267, 0.866469, 1.152547, 1.646371, 2.634019",\ + "0.683720, 0.942922, 1.229000, 1.722825, 2.710474",\ + "0.906994, 1.166196, 1.452275, 1.946099, 2.933748",\ + "1.469683, 1.728885, 2.014963, 2.508788, 3.496438",\ + "0.651822, 0.911173, 1.197335, 1.690228, 2.677094",\ + "0.694680, 0.954031, 1.240193, 1.733086, 2.719953",\ + "0.771133, 1.030483, 1.316646, 1.809540, 2.796407",\ + "0.994407, 1.253758, 1.539921, 2.032814, 3.019682",\ + "1.557095, 1.816446, 2.102610, 2.595503, 3.582371",\ + "0.732717, 1.000191, 1.285301, 1.777850, 2.764050",\ + "0.775575, 1.043049, 1.328159, 1.820708, 2.806908",\ + "0.852028, 1.119502, 1.404612, 1.897162, 2.883362",\ + "1.075302, 1.342776, 1.627887, 2.120436, 3.106637",\ + "1.637990, 1.905464, 2.190576, 2.683125, 3.669326",\ + "0.792238, 1.065880, 1.349444, 1.841763, 2.827559",\ + "0.835095, 1.108738, 1.392303, 1.884622, 2.870417",\ + "0.911548, 1.185191, 1.468756, 1.961075, 2.946871",\ + "1.134822, 1.408465, 1.692031, 2.184350, 3.170146",\ + "1.697511, 1.971154, 2.254719, 2.747039, 3.732835",\ + "1.125661, 1.430876, 1.701565, 2.191215, 3.173015",\ + "1.168519, 1.473734, 1.744423, 2.234074, 3.215873",\ + "1.244972, 1.550187, 1.820877, 2.310527, 3.292327",\ + "1.468246, 1.773462, 2.044151, 2.533802, 3.515602",\ + "2.030934, 2.336150, 2.606840, 3.096491, 4.078291"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.072526, 0.072519, 0.072509, 0.072504, 0.072494",\ + "0.151107, 0.151106, 0.151104, 0.151103, 0.151101",\ + "0.326363, 0.326363, 0.326363, 0.326363, 0.326363",\ + "0.855551, 0.855546, 0.855538, 0.855535, 0.855527",\ + "2.186892, 2.186883, 2.186870, 2.186864, 2.186852",\ + "0.072526, 0.072519, 0.072509, 0.072504, 0.072494",\ + "0.151107, 0.151105, 0.151104, 0.151103, 0.151101",\ + "0.326363, 0.326363, 0.326363, 0.326363, 0.326363",\ + "0.855551, 0.855546, 0.855538, 0.855535, 0.855527",\ + "2.186892, 2.186883, 2.186870, 2.186864, 2.186852",\ + "0.072526, 0.072519, 0.072509, 0.072504, 0.072494",\ + "0.151107, 0.151105, 0.151104, 0.151103, 0.151101",\ + "0.326363, 0.326363, 0.326363, 0.326363, 0.326363",\ + "0.855551, 0.855546, 0.855538, 0.855535, 0.855527",\ + "2.186892, 2.186882, 2.186870, 2.186864, 2.186852",\ + "0.072526, 0.072519, 0.072509, 0.072504, 0.072494",\ + "0.151107, 0.151105, 0.151104, 0.151103, 0.151101",\ + "0.326363, 0.326363, 0.326363, 0.326363, 0.326363",\ + "0.855551, 0.855546, 0.855538, 0.855535, 0.855527",\ + "2.186892, 2.186882, 2.186870, 2.186864, 2.186852",\ + "0.072525, 0.072517, 0.072509, 0.072504, 0.072494",\ + "0.151107, 0.151105, 0.151104, 0.151103, 0.151101",\ + "0.326363, 0.326363, 0.326363, 0.326363, 0.326363",\ + "0.855551, 0.855544, 0.855538, 0.855535, 0.855527",\ + "2.186891, 2.186880, 2.186870, 2.186864, 2.186852"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.576423, 0.835624, 1.121701, 1.615525, 2.603172",\ + "0.604083, 0.863284, 1.149361, 1.643184, 2.630832",\ + "0.653288, 0.912488, 1.198565, 1.692388, 2.680036",\ + "0.793871, 1.053072, 1.339149, 1.832974, 2.820621",\ + "1.146508, 1.405709, 1.691785, 2.185609, 3.173255",\ + "0.663836, 0.923186, 1.209347, 1.702240, 2.689106",\ + "0.691496, 0.950845, 1.237007, 1.729899, 2.716765",\ + "0.740700, 1.000050, 1.286211, 1.779103, 2.765969",\ + "0.881284, 1.140634, 1.426796, 1.919688, 2.906555",\ + "1.233921, 1.493270, 1.779431, 2.272324, 3.259189",\ + "0.744731, 1.012204, 1.297313, 1.789862, 2.776061",\ + "0.772390, 1.039863, 1.324972, 1.817521, 2.803720",\ + "0.821595, 1.089068, 1.374177, 1.866726, 2.852924",\ + "0.962178, 1.229652, 1.514761, 2.007311, 2.993510",\ + "1.314816, 1.582289, 1.867397, 2.359946, 3.346144",\ + "0.804251, 1.077893, 1.361457, 1.853775, 2.839570",\ + "0.831911, 1.105553, 1.389116, 1.881435, 2.867229",\ + "0.881115, 1.154757, 1.438321, 1.930639, 2.916433",\ + "1.021699, 1.295341, 1.578905, 2.071224, 3.057019",\ + "1.374336, 1.647978, 1.931541, 2.423859, 3.409653",\ + "1.137675, 1.442889, 1.713577, 2.203227, 3.185026",\ + "1.165335, 1.470549, 1.741237, 2.230887, 3.212686",\ + "1.214539, 1.519753, 1.790441, 2.280091, 3.261889",\ + "1.355123, 1.660337, 1.931026, 2.420676, 3.402475",\ + "1.707760, 2.012974, 2.283661, 2.773311, 3.755109"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.031042, 0.031042, 0.031051, 0.031083, 0.031146",\ + "0.078404, 0.078404, 0.078405, 0.078407, 0.078413",\ + "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\ + "0.457145, 0.457145, 0.457146, 0.457146, 0.457146",\ + "1.169260, 1.169260, 1.169262, 1.169268, 1.169281",\ + "0.031042, 0.031042, 0.031051, 0.031083, 0.031146",\ + "0.078404, 0.078404, 0.078405, 0.078407, 0.078413",\ + "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\ + "0.457145, 0.457145, 0.457146, 0.457146, 0.457146",\ + "1.169260, 1.169260, 1.169262, 1.169268, 1.169281",\ + "0.031042, 0.031042, 0.031051, 0.031083, 0.031146",\ + "0.078404, 0.078404, 0.078405, 0.078407, 0.078413",\ + "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\ + "0.457145, 0.457146, 0.457146, 0.457146, 0.457146",\ + "1.169260, 1.169260, 1.169262, 1.169268, 1.169281",\ + "0.031042, 0.031042, 0.031051, 0.031083, 0.031146",\ + "0.078404, 0.078404, 0.078405, 0.078407, 0.078413",\ + "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\ + "0.457145, 0.457146, 0.457146, 0.457146, 0.457146",\ + "1.169260, 1.169260, 1.169262, 1.169268, 1.169281",\ + "0.031042, 0.031042, 0.031051, 0.031083, 0.031146",\ + "0.078404, 0.078404, 0.078405, 0.078407, 0.078413",\ + "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\ + "0.457145, 0.457146, 0.457146, 0.457146, 0.457146",\ + "1.169260, 1.169260, 1.169262, 1.169268, 1.169281"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_2658*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[47]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011"); + values ( "0.548070, 0.800917, 1.079123, 1.542119, 2.468112",\ + "0.590927, 0.843775, 1.121981, 1.584977, 2.510970",\ + "0.667380, 0.920228, 1.198434, 1.661431, 2.587423",\ + "0.890654, 1.143502, 1.421709, 1.884705, 2.810698",\ + "1.453343, 1.706191, 1.984398, 2.447394, 3.373387",\ + "0.635475, 0.888501, 1.166668, 1.628833, 2.554045",\ + "0.678333, 0.931359, 1.209527, 1.671691, 2.596904",\ + "0.754786, 1.007812, 1.285980, 1.748145, 2.673357",\ + "0.978060, 1.231086, 1.509255, 1.971419, 2.896632",\ + "1.540748, 1.793775, 2.071944, 2.534108, 3.459321",\ + "0.716287, 0.977534, 1.254631, 1.716454, 2.641000",\ + "0.759144, 1.020392, 1.297489, 1.759312, 2.683859",\ + "0.835597, 1.096845, 1.373943, 1.835766, 2.760312",\ + "1.058871, 1.320120, 1.597218, 2.059040, 2.983587",\ + "1.621560, 1.882808, 2.159906, 2.621729, 3.546276",\ + "0.773896, 1.043245, 1.318770, 1.780367, 2.704509",\ + "0.816754, 1.086103, 1.361628, 1.823225, 2.747368",\ + "0.893206, 1.162556, 1.438081, 1.899679, 2.823821",\ + "1.116481, 1.385830, 1.661356, 2.122953, 3.047096",\ + "1.679169, 1.948519, 2.224045, 2.685642, 3.609785",\ + "1.108670, 1.408584, 1.670573, 2.129684, 3.049965",\ + "1.151528, 1.451442, 1.713432, 2.172543, 3.092824",\ + "1.227981, 1.527896, 1.789885, 2.248996, 3.169277",\ + "1.451255, 1.751170, 2.013160, 2.472271, 3.392552",\ + "2.013944, 2.313859, 2.575849, 3.034960, 3.955241"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011"); + values ( "0.072526, 0.072516, 0.072505, 0.072503, 0.072500",\ + "0.151107, 0.151105, 0.151103, 0.151102, 0.151102",\ + "0.326363, 0.326363, 0.326363, 0.326363, 0.326363",\ + "0.855551, 0.855543, 0.855535, 0.855534, 0.855532",\ + "2.186892, 2.186879, 2.186865, 2.186863, 2.186859",\ + "0.072526, 0.072516, 0.072505, 0.072503, 0.072500",\ + "0.151107, 0.151105, 0.151103, 0.151102, 0.151102",\ + "0.326363, 0.326363, 0.326363, 0.326363, 0.326363",\ + "0.855551, 0.855543, 0.855535, 0.855534, 0.855532",\ + "2.186892, 2.186878, 2.186865, 2.186863, 2.186859",\ + "0.072526, 0.072515, 0.072505, 0.072503, 0.072500",\ + "0.151107, 0.151105, 0.151103, 0.151102, 0.151102",\ + "0.326363, 0.326363, 0.326363, 0.326363, 0.326363",\ + "0.855551, 0.855543, 0.855535, 0.855534, 0.855532",\ + "2.186892, 2.186878, 2.186865, 2.186863, 2.186859",\ + "0.072526, 0.072515, 0.072505, 0.072503, 0.072500",\ + "0.151107, 0.151105, 0.151103, 0.151102, 0.151102",\ + "0.326363, 0.326363, 0.326363, 0.326363, 0.326363",\ + "0.855551, 0.855543, 0.855535, 0.855534, 0.855532",\ + "2.186892, 2.186878, 2.186865, 2.186863, 2.186859",\ + "0.072524, 0.072513, 0.072505, 0.072503, 0.072500",\ + "0.151107, 0.151104, 0.151103, 0.151102, 0.151102",\ + "0.326363, 0.326363, 0.326363, 0.326363, 0.326363",\ + "0.855550, 0.855541, 0.855535, 0.855534, 0.855532",\ + "2.186889, 2.186875, 2.186865, 2.186863, 2.186859"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011"); + values ( "0.560083, 0.812930, 1.091135, 1.554131, 2.480123",\ + "0.587743, 0.840589, 1.118794, 1.581790, 2.507782",\ + "0.636947, 0.889794, 1.167998, 1.630994, 2.556986",\ + "0.777531, 1.030378, 1.308583, 1.771580, 2.697572",\ + "1.130168, 1.383014, 1.661218, 2.124214, 3.050207",\ + "0.647489, 0.900513, 1.178680, 1.640844, 2.566057",\ + "0.675148, 0.928173, 1.206340, 1.668504, 2.593716",\ + "0.724353, 0.977377, 1.255544, 1.717708, 2.642920",\ + "0.864936, 1.117962, 1.396129, 1.858294, 2.783506",\ + "1.217574, 1.470598, 1.748764, 2.210928, 3.136140",\ + "0.728300, 0.989547, 1.266643, 1.728466, 2.653012",\ + "0.755960, 1.017207, 1.294303, 1.756125, 2.680671",\ + "0.805164, 1.066411, 1.343507, 1.805329, 2.729875",\ + "0.945748, 1.206995, 1.484092, 1.945915, 2.870461",\ + "1.298385, 1.559631, 1.836727, 2.298549, 3.223095",\ + "0.785910, 1.055257, 1.330781, 1.792379, 2.716521",\ + "0.813569, 1.082917, 1.358441, 1.820038, 2.744180",\ + "0.862774, 1.132121, 1.407645, 1.869242, 2.793384",\ + "1.003357, 1.272706, 1.548230, 2.009828, 2.933970",\ + "1.355995, 1.625342, 1.900865, 2.362462, 3.286604",\ + "1.120684, 1.420597, 1.682585, 2.141696, 3.061977",\ + "1.148343, 1.448256, 1.710245, 2.169356, 3.089636",\ + "1.197548, 1.497461, 1.759449, 2.218560, 3.138840",\ + "1.338132, 1.638045, 1.900034, 2.359145, 3.279426",\ + "1.690769, 1.990681, 2.252669, 2.711780, 3.632061"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011"); + values ( "0.031042, 0.031042, 0.031047, 0.031067, 0.031107",\ + "0.078404, 0.078404, 0.078404, 0.078406, 0.078410",\ + "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\ + "0.457145, 0.457145, 0.457145, 0.457145, 0.457145",\ + "1.169260, 1.169260, 1.169261, 1.169265, 1.169273",\ + "0.031042, 0.031042, 0.031047, 0.031067, 0.031107",\ + "0.078404, 0.078404, 0.078404, 0.078406, 0.078410",\ + "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\ + "0.457145, 0.457145, 0.457145, 0.457145, 0.457145",\ + "1.169260, 1.169260, 1.169261, 1.169265, 1.169273",\ + "0.031042, 0.031042, 0.031047, 0.031067, 0.031107",\ + "0.078404, 0.078404, 0.078404, 0.078406, 0.078410",\ + "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\ + "0.457145, 0.457145, 0.457145, 0.457145, 0.457145",\ + "1.169260, 1.169260, 1.169261, 1.169265, 1.169273",\ + "0.031042, 0.031042, 0.031047, 0.031067, 0.031107",\ + "0.078404, 0.078404, 0.078404, 0.078406, 0.078410",\ + "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\ + "0.457145, 0.457145, 0.457145, 0.457145, 0.457145",\ + "1.169260, 1.169260, 1.169261, 1.169265, 1.169273",\ + "0.031042, 0.031042, 0.031048, 0.031067, 0.031107",\ + "0.078404, 0.078404, 0.078404, 0.078406, 0.078410",\ + "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\ + "0.457145, 0.457145, 0.457145, 0.457145, 0.457145",\ + "1.169260, 1.169260, 1.169261, 1.169265, 1.169273"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_2601*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[20]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.380795, 0.602668, 0.780712, 1.069465, 1.629809",\ + "0.415064, 0.636936, 0.814980, 1.103733, 1.664078",\ + "0.488546, 0.710419, 0.888463, 1.177216, 1.737561",\ + "0.709765, 0.931638, 1.109681, 1.398435, 1.958779",\ + "1.271568, 1.493441, 1.671484, 1.960238, 2.520582",\ + "0.469199, 0.689987, 0.867992, 1.156770, 1.717163",\ + "0.503468, 0.724255, 0.902261, 1.191038, 1.751431",\ + "0.576950, 0.797738, 0.975743, 1.264521, 1.824914",\ + "0.798169, 1.018957, 1.196962, 1.485740, 2.046133",\ + "1.359972, 1.580759, 1.758765, 2.047543, 2.607936",\ + "0.558271, 0.770322, 0.948019, 1.236798, 1.797194",\ + "0.592539, 0.804590, 0.982288, 1.271067, 1.831463",\ + "0.666022, 0.878073, 1.055770, 1.344549, 1.904946",\ + "0.887241, 1.099292, 1.276989, 1.565768, 2.126164",\ + "1.449044, 1.661095, 1.838792, 2.127571, 2.687967",\ + "0.621529, 0.828138, 1.005713, 1.294227, 1.854208",\ + "0.655798, 0.862407, 1.039981, 1.328496, 1.888477",\ + "0.729280, 0.935889, 1.113464, 1.401978, 1.961960",\ + "0.950499, 1.157108, 1.334682, 1.623197, 2.183178",\ + "1.512302, 1.718911, 1.896485, 2.185000, 2.744981",\ + "0.953935, 1.133367, 1.309369, 1.597399, 2.156428",\ + "0.988204, 1.167636, 1.343637, 1.631667, 2.190696",\ + "1.061687, 1.241118, 1.417120, 1.705150, 2.264179",\ + "1.282905, 1.462337, 1.638339, 1.926369, 2.485398",\ + "1.844708, 2.024140, 2.200142, 2.488172, 3.047201"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.027358, 0.027358, 0.027358, 0.027363, 0.027374",\ + "0.129497, 0.129497, 0.129497, 0.129497, 0.129497",\ + "0.314624, 0.314624, 0.314624, 0.314624, 0.314624",\ + "0.831905, 0.831905, 0.831905, 0.831905, 0.831908",\ + "2.131887, 2.131887, 2.131887, 2.131888, 2.131889",\ + "0.027358, 0.027358, 0.027358, 0.027363, 0.027374",\ + "0.129497, 0.129497, 0.129497, 0.129497, 0.129497",\ + "0.314624, 0.314624, 0.314624, 0.314624, 0.314624",\ + "0.831905, 0.831905, 0.831905, 0.831905, 0.831908",\ + "2.131887, 2.131887, 2.131887, 2.131888, 2.131889",\ + "0.027358, 0.027358, 0.027358, 0.027363, 0.027374",\ + "0.129497, 0.129497, 0.129497, 0.129497, 0.129497",\ + "0.314624, 0.314624, 0.314624, 0.314624, 0.314624",\ + "0.831905, 0.831905, 0.831905, 0.831905, 0.831908",\ + "2.131887, 2.131887, 2.131887, 2.131888, 2.131889",\ + "0.027358, 0.027358, 0.027358, 0.027363, 0.027374",\ + "0.129497, 0.129497, 0.129497, 0.129497, 0.129497",\ + "0.314624, 0.314624, 0.314624, 0.314624, 0.314624",\ + "0.831905, 0.831905, 0.831905, 0.831905, 0.831908",\ + "2.131887, 2.131887, 2.131887, 2.131888, 2.131889",\ + "0.027358, 0.027358, 0.027358, 0.027363, 0.027374",\ + "0.129497, 0.129497, 0.129497, 0.129497, 0.129497",\ + "0.314624, 0.314624, 0.314624, 0.314624, 0.314624",\ + "0.831905, 0.831905, 0.831905, 0.831905, 0.831908",\ + "2.131887, 2.131887, 2.131887, 2.131888, 2.131889"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.351941, 0.573814, 0.751857, 1.040610, 1.600955",\ + "0.377860, 0.599733, 0.777776, 1.066529, 1.626874",\ + "0.432503, 0.654375, 0.832419, 1.121172, 1.681517",\ + "0.582379, 0.804252, 0.982296, 1.271049, 1.831393",\ + "0.955531, 1.177403, 1.355447, 1.644200, 2.204545",\ + "0.440345, 0.661132, 0.839138, 1.127915, 1.688308",\ + "0.466264, 0.687051, 0.865057, 1.153834, 1.714228",\ + "0.520907, 0.741694, 0.919700, 1.208477, 1.768870",\ + "0.670783, 0.891571, 1.069576, 1.358354, 1.918747",\ + "1.043935, 1.264722, 1.442728, 1.731505, 2.291898",\ + "0.529417, 0.741468, 0.919165, 1.207944, 1.768340",\ + "0.555336, 0.767386, 0.945084, 1.233863, 1.794259",\ + "0.609978, 0.822029, 0.999727, 1.288506, 1.848902",\ + "0.759855, 0.971906, 1.149603, 1.438382, 1.998778",\ + "1.133006, 1.345057, 1.522755, 1.811534, 2.371930",\ + "0.592675, 0.799284, 0.976858, 1.265373, 1.825354",\ + "0.618594, 0.825203, 1.002777, 1.291292, 1.851273",\ + "0.673236, 0.879846, 1.057420, 1.345935, 1.905916",\ + "0.823113, 1.029722, 1.207296, 1.495811, 2.055792",\ + "1.196265, 1.402874, 1.580448, 1.868963, 2.428944",\ + "0.925081, 1.104513, 1.280515, 1.568545, 2.127573",\ + "0.951000, 1.130432, 1.306434, 1.594464, 2.153493",\ + "1.005643, 1.185075, 1.361076, 1.649106, 2.208135",\ + "1.155519, 1.334951, 1.510953, 1.798983, 2.358012",\ + "1.528671, 1.708103, 1.884104, 2.172134, 2.731164"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.015511, 0.015511, 0.015511, 0.015511, 0.015512",\ + "0.067734, 0.067734, 0.067734, 0.067734, 0.067734",\ + "0.170292, 0.170292, 0.170292, 0.170292, 0.170293",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122213, 1.122213, 1.122213, 1.122213, 1.122214",\ + "0.015511, 0.015511, 0.015511, 0.015511, 0.015512",\ + "0.067734, 0.067734, 0.067734, 0.067734, 0.067734",\ + "0.170292, 0.170292, 0.170292, 0.170292, 0.170293",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122213, 1.122213, 1.122213, 1.122213, 1.122214",\ + "0.015511, 0.015511, 0.015511, 0.015511, 0.015512",\ + "0.067734, 0.067734, 0.067734, 0.067734, 0.067734",\ + "0.170292, 0.170292, 0.170292, 0.170292, 0.170293",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122213, 1.122213, 1.122213, 1.122213, 1.122214",\ + "0.015511, 0.015511, 0.015511, 0.015511, 0.015512",\ + "0.067734, 0.067734, 0.067734, 0.067734, 0.067734",\ + "0.170292, 0.170292, 0.170292, 0.170292, 0.170293",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122213, 1.122213, 1.122213, 1.122213, 1.122214",\ + "0.015511, 0.015511, 0.015511, 0.015511, 0.015512",\ + "0.067734, 0.067734, 0.067734, 0.067734, 0.067734",\ + "0.170292, 0.170292, 0.170292, 0.170292, 0.170293",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122213, 1.122213, 1.122213, 1.122213, 1.122214"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_min_2664*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[22]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.357049, 0.595251, 0.779226, 1.073282, 1.641542",\ + "0.391318, 0.630694, 0.814727, 1.108794, 1.677077",\ + "0.464801, 0.704176, 0.888210, 1.182277, 1.750560",\ + "0.686019, 0.925396, 1.109429, 1.403496, 1.971779",\ + "1.247822, 1.487198, 1.671232, 1.965299, 2.533582",\ + "0.445388, 0.682569, 0.866506, 1.160588, 1.728896",\ + "0.479656, 0.718012, 0.902008, 1.196099, 1.764431",\ + "0.553139, 0.791495, 0.975491, 1.269582, 1.837914",\ + "0.774358, 1.012714, 1.196710, 1.490801, 2.059132",\ + "1.336161, 1.574517, 1.758512, 2.052604, 2.620935",\ + "0.534519, 0.762902, 0.946533, 1.240616, 1.808927",\ + "0.568788, 0.798345, 0.982035, 1.276128, 1.844462",\ + "0.642270, 0.871828, 1.055518, 1.349610, 1.917945",\ + "0.863489, 1.093047, 1.276737, 1.570829, 2.139164",\ + "1.425292, 1.654850, 1.838539, 2.132632, 2.700967",\ + "0.597943, 0.820727, 1.004241, 1.298055, 1.865961",\ + "0.632211, 0.856174, 1.039743, 1.333567, 1.901497",\ + "0.705694, 0.929657, 1.113225, 1.407049, 1.974979",\ + "0.926913, 1.150876, 1.334444, 1.628268, 2.196198",\ + "1.488716, 1.712679, 1.896247, 2.190071, 2.758001",\ + "0.932941, 1.126006, 1.307899, 1.601235, 2.168205",\ + "0.967209, 1.161484, 1.343401, 1.636746, 2.203741",\ + "1.040692, 1.234967, 1.416883, 1.710229, 2.277223",\ + "1.261911, 1.456186, 1.638102, 1.931448, 2.498442",\ + "1.823713, 2.017988, 2.199905, 2.493251, 3.060245"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.027366, 0.027366, 0.027366, 0.027374, 0.027393",\ + "0.129494, 0.129494, 0.129494, 0.129494, 0.129494",\ + "0.314624, 0.314624, 0.314624, 0.314624, 0.314624",\ + "0.831904, 0.831904, 0.831904, 0.831906, 0.831910",\ + "2.131887, 2.131887, 2.131887, 2.131888, 2.131891",\ + "0.027366, 0.027366, 0.027366, 0.027374, 0.027393",\ + "0.129494, 0.129494, 0.129494, 0.129494, 0.129494",\ + "0.314624, 0.314624, 0.314624, 0.314624, 0.314624",\ + "0.831904, 0.831904, 0.831904, 0.831906, 0.831910",\ + "2.131887, 2.131887, 2.131887, 2.131888, 2.131891",\ + "0.027366, 0.027366, 0.027366, 0.027374, 0.027393",\ + "0.129494, 0.129494, 0.129494, 0.129494, 0.129494",\ + "0.314624, 0.314624, 0.314624, 0.314624, 0.314624",\ + "0.831904, 0.831904, 0.831904, 0.831906, 0.831910",\ + "2.131887, 2.131887, 2.131887, 2.131888, 2.131891",\ + "0.027366, 0.027366, 0.027366, 0.027374, 0.027393",\ + "0.129494, 0.129494, 0.129494, 0.129494, 0.129494",\ + "0.314624, 0.314624, 0.314624, 0.314624, 0.314624",\ + "0.831904, 0.831904, 0.831904, 0.831906, 0.831910",\ + "2.131887, 2.131887, 2.131887, 2.131888, 2.131891",\ + "0.027366, 0.027366, 0.027366, 0.027374, 0.027393",\ + "0.129494, 0.129494, 0.129494, 0.129494, 0.129494",\ + "0.314624, 0.314624, 0.314624, 0.314624, 0.314624",\ + "0.831904, 0.831904, 0.831904, 0.831906, 0.831910",\ + "2.131887, 2.131887, 2.131887, 2.131888, 2.131891"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.328195, 0.567571, 0.751605, 1.045671, 1.613954",\ + "0.354114, 0.593490, 0.777524, 1.071590, 1.639874",\ + "0.408757, 0.648133, 0.832166, 1.126233, 1.694516",\ + "0.558634, 0.798009, 0.982043, 1.276110, 1.844393",\ + "0.931785, 1.171161, 1.355194, 1.649261, 2.217544",\ + "0.416534, 0.654889, 0.838885, 1.132977, 1.701308",\ + "0.442453, 0.680808, 0.864804, 1.158895, 1.727227",\ + "0.497095, 0.735451, 0.919447, 1.213538, 1.781870",\ + "0.646972, 0.885328, 1.069324, 1.363415, 1.931746",\ + "1.020123, 1.258479, 1.442475, 1.736566, 2.304898",\ + "0.505665, 0.735223, 0.918912, 1.213005, 1.781339",\ + "0.531584, 0.761142, 0.944831, 1.238924, 1.807259",\ + "0.586226, 0.815784, 0.999474, 1.293567, 1.861901",\ + "0.736103, 0.965661, 1.149351, 1.443443, 2.011778",\ + "1.109254, 1.338812, 1.522502, 1.816595, 2.384929",\ + "0.569089, 0.793052, 0.976620, 1.270444, 1.838374",\ + "0.595008, 0.818971, 1.002539, 1.296363, 1.864293",\ + "0.649650, 0.873613, 1.057182, 1.351006, 1.918935",\ + "0.799527, 1.023490, 1.207058, 1.500882, 2.068812",\ + "1.172678, 1.396641, 1.580210, 1.874034, 2.441963",\ + "0.904086, 1.098361, 1.280278, 1.573624, 2.140618",\ + "0.930005, 1.124280, 1.306197, 1.599543, 2.166537",\ + "0.984648, 1.178923, 1.360839, 1.654185, 2.221179",\ + "1.134525, 1.328800, 1.510716, 1.804062, 2.371056",\ + "1.507676, 1.701951, 1.883868, 2.177213, 2.744207"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.015511, 0.015511, 0.015511, 0.015511, 0.015512",\ + "0.067734, 0.067734, 0.067734, 0.067734, 0.067734",\ + "0.170292, 0.170292, 0.170292, 0.170292, 0.170293",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122212, 1.122212, 1.122212, 1.122213, 1.122215",\ + "0.015511, 0.015511, 0.015511, 0.015511, 0.015512",\ + "0.067734, 0.067734, 0.067734, 0.067734, 0.067734",\ + "0.170292, 0.170292, 0.170292, 0.170292, 0.170293",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122212, 1.122212, 1.122212, 1.122213, 1.122215",\ + "0.015511, 0.015511, 0.015511, 0.015511, 0.015512",\ + "0.067734, 0.067734, 0.067734, 0.067734, 0.067734",\ + "0.170292, 0.170292, 0.170292, 0.170292, 0.170293",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122212, 1.122212, 1.122212, 1.122213, 1.122215",\ + "0.015511, 0.015511, 0.015511, 0.015511, 0.015512",\ + "0.067734, 0.067734, 0.067734, 0.067734, 0.067734",\ + "0.170292, 0.170292, 0.170292, 0.170292, 0.170293",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122212, 1.122212, 1.122212, 1.122213, 1.122215",\ + "0.015511, 0.015511, 0.015511, 0.015511, 0.015512",\ + "0.067734, 0.067734, 0.067734, 0.067734, 0.067734",\ + "0.170292, 0.170292, 0.170292, 0.170292, 0.170293",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122212, 1.122212, 1.122212, 1.122213, 1.122215"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_min*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[31]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.439056, 0.659338, 0.836735, 1.125199, 1.685426",\ + "0.473321, 0.693604, 0.871000, 1.159464, 1.719692",\ + "0.546805, 0.767087, 0.944484, 1.232948, 1.793175",\ + "0.768026, 0.988308, 1.165705, 1.454169, 2.014396",\ + "1.329834, 1.550117, 1.727513, 2.015977, 2.576204",\ + "0.527452, 0.746657, 0.924016, 1.212504, 1.772779",\ + "0.561718, 0.780922, 0.958281, 1.246769, 1.807045",\ + "0.635202, 0.854406, 1.031765, 1.320253, 1.880529",\ + "0.856422, 1.075626, 1.252986, 1.541474, 2.101749",\ + "1.418231, 1.637435, 1.814794, 2.103282, 2.663558",\ + "0.616803, 0.826989, 1.004043, 1.292532, 1.852811",\ + "0.651068, 0.861255, 1.038308, 1.326798, 1.887077",\ + "0.724552, 0.934738, 1.111792, 1.400281, 1.960560",\ + "0.945773, 1.155959, 1.333013, 1.621502, 2.181781",\ + "1.507581, 1.717768, 1.894821, 2.183311, 2.743589",\ + "0.680452, 0.884805, 1.061735, 1.349962, 1.909826",\ + "0.714717, 0.919071, 1.096000, 1.384227, 1.944092",\ + "0.788201, 0.992554, 1.169484, 1.457711, 2.017575",\ + "1.009422, 1.213775, 1.390705, 1.678931, 2.238796",\ + "1.571230, 1.775584, 1.952513, 2.240740, 2.800604",\ + "1.011732, 1.190021, 1.365390, 1.653133, 2.212047",\ + "1.045997, 1.224287, 1.399656, 1.687398, 2.246312",\ + "1.119481, 1.297770, 1.473139, 1.760882, 2.319796",\ + "1.340702, 1.518991, 1.694360, 1.982103, 2.541017",\ + "1.902511, 2.080800, 2.256169, 2.543911, 3.102825"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.027424, 0.027424, 0.027425, 0.027426, 0.027427",\ + "0.129493, 0.129493, 0.129493, 0.129493, 0.129493",\ + "0.314624, 0.314624, 0.314624, 0.314624, 0.314623",\ + "0.831916, 0.831916, 0.831916, 0.831917, 0.831917",\ + "2.131895, 2.131895, 2.131895, 2.131895, 2.131895",\ + "0.027424, 0.027424, 0.027425, 0.027426, 0.027427",\ + "0.129493, 0.129493, 0.129493, 0.129493, 0.129493",\ + "0.314624, 0.314624, 0.314624, 0.314624, 0.314623",\ + "0.831916, 0.831916, 0.831916, 0.831917, 0.831917",\ + "2.131895, 2.131895, 2.131895, 2.131895, 2.131895",\ + "0.027424, 0.027424, 0.027425, 0.027426, 0.027427",\ + "0.129493, 0.129493, 0.129493, 0.129493, 0.129493",\ + "0.314624, 0.314624, 0.314624, 0.314624, 0.314623",\ + "0.831916, 0.831916, 0.831916, 0.831917, 0.831917",\ + "2.131895, 2.131895, 2.131895, 2.131895, 2.131895",\ + "0.027424, 0.027424, 0.027425, 0.027426, 0.027427",\ + "0.129493, 0.129493, 0.129493, 0.129493, 0.129493",\ + "0.314624, 0.314624, 0.314624, 0.314624, 0.314623",\ + "0.831916, 0.831916, 0.831916, 0.831917, 0.831917",\ + "2.131895, 2.131895, 2.131895, 2.131895, 2.131895",\ + "0.027424, 0.027424, 0.027425, 0.027426, 0.027427",\ + "0.129493, 0.129493, 0.129493, 0.129493, 0.129493",\ + "0.314624, 0.314624, 0.314624, 0.314624, 0.314623",\ + "0.831916, 0.831916, 0.831916, 0.831917, 0.831917",\ + "2.131895, 2.131895, 2.131895, 2.131895, 2.131895"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.410231, 0.630513, 0.807909, 1.096372, 1.656599",\ + "0.436125, 0.656408, 0.833804, 1.122268, 1.682495",\ + "0.490769, 0.711051, 0.888448, 1.176911, 1.737139",\ + "0.640645, 0.860927, 1.038324, 1.326787, 1.887015",\ + "1.013797, 1.234079, 1.411476, 1.699939, 2.260167",\ + "0.498627, 0.717831, 0.895190, 1.183677, 1.743952",\ + "0.524522, 0.743726, 0.921085, 1.209573, 1.769848",\ + "0.579165, 0.798369, 0.975729, 1.264216, 1.824492",\ + "0.729041, 0.948246, 1.125605, 1.414093, 1.974368",\ + "1.102193, 1.321398, 1.498757, 1.787244, 2.347520",\ + "0.587977, 0.798164, 0.975217, 1.263706, 1.823984",\ + "0.613872, 0.824059, 1.001112, 1.289602, 1.849880",\ + "0.668516, 0.878702, 1.055755, 1.344245, 1.904523",\ + "0.818392, 1.028578, 1.205631, 1.494121, 2.054400",\ + "1.191543, 1.401730, 1.578784, 1.867273, 2.427552",\ + "0.651626, 0.855980, 1.032909, 1.321135, 1.880999",\ + "0.677521, 0.881875, 1.058804, 1.347031, 1.906895",\ + "0.732164, 0.936518, 1.113448, 1.401674, 1.961538",\ + "0.882041, 1.086394, 1.263324, 1.551550, 2.111415",\ + "1.255192, 1.459546, 1.636476, 1.924702, 2.484566",\ + "0.982907, 1.161196, 1.336565, 1.624306, 2.183219",\ + "1.008801, 1.187091, 1.362460, 1.650202, 2.209116",\ + "1.063445, 1.241734, 1.417103, 1.704845, 2.263759",\ + "1.213321, 1.391610, 1.566979, 1.854722, 2.413635",\ + "1.586473, 1.764762, 1.940131, 2.227873, 2.786787"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.015464, 0.015464, 0.015465, 0.015465, 0.015467",\ + "0.067728, 0.067728, 0.067728, 0.067728, 0.067729",\ + "0.170295, 0.170295, 0.170295, 0.170295, 0.170295",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122218, 1.122218, 1.122218, 1.122218, 1.122218",\ + "0.015464, 0.015464, 0.015465, 0.015465, 0.015467",\ + "0.067728, 0.067728, 0.067728, 0.067728, 0.067729",\ + "0.170295, 0.170295, 0.170295, 0.170295, 0.170295",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122218, 1.122218, 1.122218, 1.122218, 1.122218",\ + "0.015464, 0.015464, 0.015465, 0.015465, 0.015467",\ + "0.067728, 0.067728, 0.067728, 0.067728, 0.067729",\ + "0.170295, 0.170295, 0.170295, 0.170295, 0.170295",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122218, 1.122218, 1.122218, 1.122218, 1.122218",\ + "0.015464, 0.015464, 0.015465, 0.015465, 0.015467",\ + "0.067728, 0.067728, 0.067728, 0.067728, 0.067729",\ + "0.170295, 0.170295, 0.170295, 0.170295, 0.170295",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122218, 1.122218, 1.122218, 1.122218, 1.122218",\ + "0.015464, 0.015464, 0.015465, 0.015465, 0.015467",\ + "0.067728, 0.067728, 0.067728, 0.067728, 0.067729",\ + "0.170295, 0.170295, 0.170295, 0.170295, 0.170295",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122218, 1.122218, 1.122218, 1.122218, 1.122218"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_min_2417*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[33]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.416720, 0.653678, 0.840231, 1.138631, 1.715459",\ + "0.450985, 0.687943, 0.874496, 1.172896, 1.749724",\ + "0.524469, 0.761427, 0.947980, 1.246380, 1.823208",\ + "0.745690, 0.982648, 1.169201, 1.467601, 2.044429",\ + "1.307499, 1.544456, 1.731009, 2.029409, 2.606237",\ + "0.505034, 0.740996, 0.927512, 1.225936, 1.802812",\ + "0.539300, 0.775261, 0.961777, 1.260202, 1.837078",\ + "0.612783, 0.848745, 1.035261, 1.333685, 1.910561",\ + "0.834004, 1.069966, 1.256482, 1.554906, 2.131782",\ + "1.395813, 1.631774, 1.818290, 2.116714, 2.693590",\ + "0.594427, 0.821326, 1.007539, 1.305964, 1.882844",\ + "0.628693, 0.855591, 1.041804, 1.340230, 1.917109",\ + "0.702176, 0.929075, 1.115288, 1.413714, 1.990593",\ + "0.923397, 1.150296, 1.336509, 1.634935, 2.211814",\ + "1.485206, 1.712105, 1.898317, 2.196743, 2.773622",\ + "0.658240, 0.879157, 1.065253, 1.363414, 1.939900",\ + "0.692506, 0.913422, 1.099519, 1.397680, 1.974165",\ + "0.765989, 0.986906, 1.173002, 1.471163, 2.047649",\ + "0.987210, 1.208127, 1.394223, 1.692384, 2.268870",\ + "1.549019, 1.769935, 1.956032, 2.254193, 2.830678",\ + "0.995697, 1.184467, 1.368911, 1.666602, 2.242170",\ + "1.029963, 1.218732, 1.403177, 1.700868, 2.276436",\ + "1.103446, 1.292216, 1.476660, 1.774352, 2.349919",\ + "1.324667, 1.513437, 1.697881, 1.995573, 2.571140",\ + "1.886476, 2.075245, 2.259690, 2.557381, 3.132948"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.027423, 0.027425, 0.027425, 0.027426, 0.027428",\ + "0.129493, 0.129493, 0.129493, 0.129493, 0.129493",\ + "0.314624, 0.314624, 0.314624, 0.314624, 0.314623",\ + "0.831916, 0.831916, 0.831917, 0.831917, 0.831917",\ + "2.131895, 2.131895, 2.131895, 2.131895, 2.131895",\ + "0.027423, 0.027425, 0.027425, 0.027426, 0.027428",\ + "0.129493, 0.129493, 0.129493, 0.129493, 0.129493",\ + "0.314624, 0.314624, 0.314624, 0.314624, 0.314623",\ + "0.831916, 0.831916, 0.831917, 0.831917, 0.831917",\ + "2.131895, 2.131895, 2.131895, 2.131895, 2.131895",\ + "0.027423, 0.027425, 0.027425, 0.027426, 0.027428",\ + "0.129493, 0.129493, 0.129493, 0.129493, 0.129493",\ + "0.314624, 0.314624, 0.314624, 0.314624, 0.314623",\ + "0.831916, 0.831916, 0.831917, 0.831917, 0.831917",\ + "2.131895, 2.131895, 2.131895, 2.131895, 2.131895",\ + "0.027423, 0.027425, 0.027425, 0.027426, 0.027428",\ + "0.129493, 0.129493, 0.129493, 0.129493, 0.129493",\ + "0.314624, 0.314624, 0.314624, 0.314624, 0.314623",\ + "0.831916, 0.831916, 0.831917, 0.831917, 0.831917",\ + "2.131895, 2.131895, 2.131895, 2.131895, 2.131895",\ + "0.027424, 0.027425, 0.027425, 0.027426, 0.027428",\ + "0.129493, 0.129493, 0.129493, 0.129493, 0.129493",\ + "0.314624, 0.314624, 0.314624, 0.314624, 0.314623",\ + "0.831916, 0.831916, 0.831917, 0.831917, 0.831917",\ + "2.131895, 2.131895, 2.131895, 2.131895, 2.131895"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.387894, 0.624852, 0.811405, 1.109804, 1.686631",\ + "0.413789, 0.650747, 0.837300, 1.135700, 1.712528",\ + "0.468433, 0.705391, 0.891944, 1.190343, 1.767171",\ + "0.618309, 0.855267, 1.041820, 1.340220, 1.917047",\ + "0.991461, 1.228418, 1.414971, 1.713371, 2.290199",\ + "0.476209, 0.712170, 0.898686, 1.197109, 1.773985",\ + "0.502103, 0.738065, 0.924581, 1.223005, 1.799881",\ + "0.556747, 0.792708, 0.979225, 1.277649, 1.854524",\ + "0.706623, 0.942585, 1.129101, 1.427525, 2.004401",\ + "1.079775, 1.315736, 1.502252, 1.800677, 2.377553",\ + "0.565602, 0.792500, 0.978712, 1.277138, 1.854016",\ + "0.591497, 0.818395, 1.004608, 1.303034, 1.879913",\ + "0.646140, 0.873039, 1.059251, 1.357677, 1.934556",\ + "0.796016, 1.022915, 1.209128, 1.507553, 2.084432",\ + "1.169168, 1.396067, 1.582279, 1.880705, 2.457584",\ + "0.629415, 0.850331, 1.036427, 1.334588, 1.911072",\ + "0.655310, 0.876226, 1.062322, 1.360483, 1.936969",\ + "0.709953, 0.930869, 1.116966, 1.415127, 1.991612",\ + "0.859829, 1.080746, 1.266842, 1.565003, 2.141489",\ + "1.232981, 1.453897, 1.639994, 1.938155, 2.514640",\ + "0.966871, 1.155640, 1.340085, 1.637776, 2.213343",\ + "0.992766, 1.181536, 1.365980, 1.663672, 2.239239",\ + "1.047410, 1.236179, 1.420624, 1.718315, 2.293883",\ + "1.197286, 1.386055, 1.570500, 1.868191, 2.443759",\ + "1.570438, 1.759207, 1.943652, 2.241343, 2.816911"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.015464, 0.015465, 0.015465, 0.015466, 0.015467",\ + "0.067728, 0.067728, 0.067728, 0.067728, 0.067729",\ + "0.170295, 0.170295, 0.170295, 0.170295, 0.170295",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122217, 1.122218, 1.122218, 1.122218, 1.122218",\ + "0.015464, 0.015465, 0.015465, 0.015466, 0.015467",\ + "0.067728, 0.067728, 0.067728, 0.067728, 0.067729",\ + "0.170295, 0.170295, 0.170295, 0.170295, 0.170295",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122217, 1.122218, 1.122218, 1.122218, 1.122218",\ + "0.015464, 0.015465, 0.015465, 0.015466, 0.015467",\ + "0.067728, 0.067728, 0.067728, 0.067728, 0.067729",\ + "0.170295, 0.170295, 0.170295, 0.170295, 0.170295",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122217, 1.122218, 1.122218, 1.122218, 1.122218",\ + "0.015464, 0.015465, 0.015465, 0.015466, 0.015467",\ + "0.067728, 0.067728, 0.067728, 0.067728, 0.067729",\ + "0.170295, 0.170295, 0.170295, 0.170295, 0.170295",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122217, 1.122218, 1.122218, 1.122218, 1.122218",\ + "0.015465, 0.015465, 0.015465, 0.015466, 0.015467",\ + "0.067728, 0.067728, 0.067728, 0.067728, 0.067729",\ + "0.170295, 0.170295, 0.170295, 0.170295, 0.170295",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122218, 1.122218, 1.122218, 1.122218, 1.122218"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_min_2525*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[35]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.317807, 0.553382, 0.743028, 1.048041, 1.638313",\ + "0.360716, 0.596291, 0.785937, 1.090950, 1.681222",\ + "0.437216, 0.672790, 0.862436, 1.167450, 1.757720",\ + "0.660515, 0.896090, 1.085736, 1.390749, 1.981019",\ + "1.219139, 1.454558, 1.644426, 1.949632, 2.540179",\ + "0.406273, 0.640700, 0.830308, 1.135346, 1.725666",\ + "0.449182, 0.683609, 0.873218, 1.178255, 1.768575",\ + "0.525681, 0.760108, 0.949717, 1.254755, 1.845074",\ + "0.748981, 0.983408, 1.173017, 1.478054, 2.068373",\ + "1.307619, 1.541876, 1.731707, 2.036937, 2.627532",\ + "0.495773, 0.721033, 0.910335, 1.215375, 1.805698",\ + "0.538682, 0.763942, 0.953244, 1.258284, 1.848607",\ + "0.615182, 0.840441, 1.029744, 1.334783, 1.925105",\ + "0.838481, 1.063741, 1.253043, 1.558083, 2.148405",\ + "1.397163, 1.622209, 1.811734, 2.116965, 2.707564",\ + "0.559539, 0.778868, 0.968056, 1.272841, 1.862785",\ + "0.602449, 0.821777, 1.010965, 1.315750, 1.905694",\ + "0.678948, 0.898276, 1.087465, 1.392249, 1.982193",\ + "0.902248, 1.121576, 1.310764, 1.615548, 2.205492",\ + "1.460969, 1.680044, 1.869455, 2.174432, 2.764652",\ + "0.896716, 1.084217, 1.271716, 1.576043, 2.165093",\ + "0.939625, 1.127126, 1.314625, 1.618952, 2.208002",\ + "1.016124, 1.203625, 1.391125, 1.695451, 2.284501",\ + "1.239424, 1.426925, 1.614424, 1.918751, 2.507800",\ + "1.798400, 1.985393, 2.173115, 2.477634, 3.066961"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.048588, 0.048588, 0.048588, 0.048588, 0.048588",\ + "0.136074, 0.136074, 0.136074, 0.136074, 0.136074",\ + "0.314166, 0.314166, 0.314166, 0.314166, 0.314166",\ + "0.833609, 0.833609, 0.833609, 0.833609, 0.833609",\ + "2.135110, 2.135110, 2.135110, 2.135111, 2.135114",\ + "0.048588, 0.048588, 0.048588, 0.048588, 0.048588",\ + "0.136074, 0.136074, 0.136074, 0.136074, 0.136074",\ + "0.314166, 0.314166, 0.314166, 0.314166, 0.314166",\ + "0.833609, 0.833609, 0.833609, 0.833609, 0.833609",\ + "2.135110, 2.135110, 2.135110, 2.135111, 2.135114",\ + "0.048588, 0.048588, 0.048588, 0.048588, 0.048588",\ + "0.136074, 0.136074, 0.136074, 0.136074, 0.136074",\ + "0.314166, 0.314166, 0.314166, 0.314166, 0.314166",\ + "0.833609, 0.833609, 0.833609, 0.833609, 0.833609",\ + "2.135110, 2.135110, 2.135110, 2.135111, 2.135114",\ + "0.048588, 0.048588, 0.048588, 0.048588, 0.048588",\ + "0.136074, 0.136074, 0.136074, 0.136074, 0.136074",\ + "0.314166, 0.314166, 0.314166, 0.314166, 0.314166",\ + "0.833609, 0.833609, 0.833609, 0.833609, 0.833609",\ + "2.135110, 2.135110, 2.135110, 2.135111, 2.135114",\ + "0.048588, 0.048588, 0.048588, 0.048588, 0.048588",\ + "0.136074, 0.136074, 0.136074, 0.136074, 0.136074",\ + "0.314166, 0.314166, 0.314166, 0.314166, 0.314166",\ + "0.833609, 0.833609, 0.833609, 0.833609, 0.833609",\ + "2.135110, 2.135110, 2.135110, 2.135111, 2.135114"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.305217, 0.540636, 0.730505, 1.035711, 1.626258",\ + "0.334877, 0.570296, 0.760166, 1.065372, 1.655918",\ + "0.386817, 0.622236, 0.812106, 1.117312, 1.707858",\ + "0.535277, 0.770695, 0.960565, 1.265772, 1.856318",\ + "0.899736, 1.135311, 1.324957, 1.629971, 2.220244",\ + "0.393698, 0.627954, 0.817786, 1.123016, 1.713611",\ + "0.423358, 0.657614, 0.847447, 1.152677, 1.743272",\ + "0.475298, 0.709554, 0.899387, 1.204617, 1.795212",\ + "0.623757, 0.858014, 1.047846, 1.353077, 1.943671",\ + "0.988201, 1.222629, 1.412238, 1.717276, 2.307598",\ + "0.483241, 0.708287, 0.897813, 1.203045, 1.793643",\ + "0.512901, 0.737947, 0.927473, 1.232705, 1.823303",\ + "0.564842, 0.789887, 0.979414, 1.284645, 1.875243",\ + "0.713301, 0.938347, 1.127873, 1.433105, 2.023703",\ + "1.077702, 1.302962, 1.492265, 1.797305, 2.387629",\ + "0.547048, 0.766122, 0.955534, 1.260511, 1.850731",\ + "0.576708, 0.795782, 0.985195, 1.290171, 1.880391",\ + "0.628648, 0.847722, 1.037135, 1.342111, 1.932331",\ + "0.777107, 0.996181, 1.185595, 1.490571, 2.080791",\ + "1.141469, 1.360797, 1.549985, 1.854770, 2.444716",\ + "0.884478, 1.071471, 1.259194, 1.563713, 2.153039",\ + "0.914138, 1.101131, 1.288855, 1.593374, 2.182700",\ + "0.966078, 1.153071, 1.340795, 1.645314, 2.234640",\ + "1.114538, 1.301530, 1.489255, 1.793774, 2.383100",\ + "1.478645, 1.666146, 1.853645, 2.157973, 2.747025"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.026620, 0.026620, 0.026620, 0.026620, 0.026620",\ + "0.075782, 0.075782, 0.075782, 0.075782, 0.075782",\ + "0.169298, 0.169298, 0.169298, 0.169298, 0.169298",\ + "0.439562, 0.439563, 0.439563, 0.439565, 0.439573",\ + "1.119158, 1.119160, 1.119160, 1.119170, 1.119193",\ + "0.026620, 0.026620, 0.026620, 0.026620, 0.026620",\ + "0.075782, 0.075782, 0.075782, 0.075782, 0.075782",\ + "0.169298, 0.169298, 0.169298, 0.169298, 0.169298",\ + "0.439562, 0.439563, 0.439563, 0.439565, 0.439573",\ + "1.119158, 1.119160, 1.119160, 1.119170, 1.119193",\ + "0.026620, 0.026620, 0.026620, 0.026620, 0.026620",\ + "0.075782, 0.075782, 0.075782, 0.075782, 0.075782",\ + "0.169298, 0.169298, 0.169298, 0.169298, 0.169298",\ + "0.439562, 0.439563, 0.439563, 0.439565, 0.439573",\ + "1.119158, 1.119160, 1.119160, 1.119170, 1.119193",\ + "0.026620, 0.026620, 0.026620, 0.026620, 0.026620",\ + "0.075782, 0.075782, 0.075782, 0.075782, 0.075782",\ + "0.169298, 0.169298, 0.169298, 0.169298, 0.169298",\ + "0.439562, 0.439563, 0.439563, 0.439565, 0.439573",\ + "1.119159, 1.119160, 1.119160, 1.119170, 1.119193",\ + "0.026620, 0.026620, 0.026620, 0.026620, 0.026620",\ + "0.075782, 0.075782, 0.075782, 0.075782, 0.075782",\ + "0.169298, 0.169298, 0.169298, 0.169298, 0.169298",\ + "0.439562, 0.439563, 0.439563, 0.439565, 0.439573",\ + "1.119160, 1.119160, 1.119160, 1.119170, 1.119193"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_min_2639*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[36]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.385015, 0.606699, 0.784745, 1.073680, 1.634527",\ + "0.435014, 0.656698, 0.834744, 1.123679, 1.684526",\ + "0.515571, 0.737187, 0.915297, 1.204231, 1.765078",\ + "0.736804, 0.958420, 1.136530, 1.425464, 1.986311",\ + "1.298648, 1.520264, 1.698375, 1.987309, 2.548156",\ + "0.473424, 0.694018, 0.872026, 1.160985, 1.721881",\ + "0.523423, 0.744017, 0.922025, 1.210984, 1.771880",\ + "0.603979, 0.824505, 1.002578, 1.291536, 1.852431",\ + "0.825212, 1.045738, 1.223811, 1.512769, 2.073665",\ + "1.387057, 1.607583, 1.785656, 2.074614, 2.635510",\ + "0.562514, 0.774353, 0.952053, 1.241014, 1.801912",\ + "0.612513, 0.824352, 1.002052, 1.291013, 1.851911",\ + "0.693070, 0.904840, 1.082605, 1.371564, 1.932463",\ + "0.914303, 1.126073, 1.303838, 1.592798, 2.153697",\ + "1.476147, 1.687918, 1.865683, 2.154643, 2.715541",\ + "0.625792, 0.832174, 1.009746, 1.298444, 1.858928",\ + "0.675791, 0.882173, 1.059745, 1.348443, 1.908927",\ + "0.756348, 0.962666, 1.140298, 1.428994, 1.989478",\ + "0.977581, 1.183899, 1.361531, 1.650227, 2.210711",\ + "1.539425, 1.745744, 1.923376, 2.212072, 2.772557",\ + "0.956955, 1.137434, 1.313402, 1.601616, 2.161149",\ + "1.006954, 1.187433, 1.363401, 1.651615, 2.211148",\ + "1.086373, 1.267959, 1.443954, 1.732166, 2.291699",\ + "1.307606, 1.489192, 1.665187, 1.953399, 2.512933",\ + "1.869451, 2.051037, 2.227032, 2.515244, 3.074778"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.027446, 0.027446, 0.027446, 0.027446, 0.027445",\ + "0.129491, 0.129491, 0.129491, 0.129491, 0.129491",\ + "0.314623, 0.314623, 0.314623, 0.314623, 0.314623",\ + "0.831920, 0.831920, 0.831920, 0.831920, 0.831920",\ + "2.131897, 2.131897, 2.131897, 2.131897, 2.131897",\ + "0.027446, 0.027446, 0.027446, 0.027446, 0.027445",\ + "0.129491, 0.129491, 0.129491, 0.129491, 0.129491",\ + "0.314623, 0.314623, 0.314623, 0.314623, 0.314623",\ + "0.831920, 0.831920, 0.831920, 0.831920, 0.831920",\ + "2.131897, 2.131897, 2.131897, 2.131897, 2.131897",\ + "0.027446, 0.027446, 0.027446, 0.027446, 0.027445",\ + "0.129491, 0.129491, 0.129491, 0.129491, 0.129491",\ + "0.314623, 0.314623, 0.314623, 0.314623, 0.314623",\ + "0.831920, 0.831920, 0.831920, 0.831920, 0.831920",\ + "2.131897, 2.131897, 2.131897, 2.131897, 2.131897",\ + "0.027446, 0.027446, 0.027446, 0.027446, 0.027445",\ + "0.129491, 0.129491, 0.129491, 0.129491, 0.129491",\ + "0.314623, 0.314623, 0.314623, 0.314623, 0.314623",\ + "0.831920, 0.831920, 0.831920, 0.831920, 0.831920",\ + "2.131897, 2.131897, 2.131897, 2.131897, 2.131897",\ + "0.027446, 0.027446, 0.027446, 0.027446, 0.027445",\ + "0.129491, 0.129491, 0.129491, 0.129491, 0.129491",\ + "0.314623, 0.314623, 0.314623, 0.314623, 0.314623",\ + "0.831920, 0.831920, 0.831920, 0.831920, 0.831920",\ + "2.131897, 2.131897, 2.131897, 2.131897, 2.131897"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.379185, 0.600800, 0.778912, 1.067847, 1.628695",\ + "0.404931, 0.626547, 0.804658, 1.093592, 1.654439",\ + "0.459580, 0.681196, 0.859307, 1.148241, 1.709088",\ + "0.609453, 0.831069, 1.009180, 1.298114, 1.858961",\ + "0.965195, 1.186879, 1.364924, 1.653859, 2.214706",\ + "0.467593, 0.688119, 0.866193, 1.155152, 1.716048",\ + "0.493340, 0.713866, 0.891939, 1.180897, 1.741792",\ + "0.547989, 0.768515, 0.946587, 1.235546, 1.796441",\ + "0.697862, 0.918388, 1.096461, 1.385419, 1.946315",\ + "1.053603, 1.274197, 1.452205, 1.741164, 2.302060",\ + "0.556683, 0.768454, 0.946220, 1.235180, 1.796080",\ + "0.582430, 0.794201, 0.971965, 1.260925, 1.821824",\ + "0.637079, 0.848850, 1.026614, 1.315574, 1.876473",\ + "0.786952, 0.998723, 1.176488, 1.465447, 2.026346",\ + "1.142694, 1.354532, 1.532232, 1.821193, 2.382091",\ + "0.619961, 0.826280, 1.003913, 1.292610, 1.853095",\ + "0.645708, 0.852026, 1.029659, 1.318355, 1.878839",\ + "0.700357, 0.906675, 1.084307, 1.373004, 1.933488",\ + "0.850230, 1.056549, 1.234181, 1.522877, 2.083362",\ + "1.205971, 1.412353, 1.589925, 1.878623, 2.439106",\ + "0.949987, 1.131573, 1.307569, 1.595782, 2.155316",\ + "0.975733, 1.157320, 1.333315, 1.621527, 2.181061",\ + "1.030382, 1.211969, 1.387964, 1.676176, 2.235709",\ + "1.180256, 1.361842, 1.537837, 1.826049, 2.385583",\ + "1.537134, 1.717614, 1.893581, 2.181795, 2.741328"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.015175, 0.015175, 0.015173, 0.015172, 0.015170",\ + "0.067694, 0.067694, 0.067694, 0.067694, 0.067694",\ + "0.170296, 0.170296, 0.170296, 0.170296, 0.170296",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122219, 1.122219, 1.122219, 1.122219, 1.122219",\ + "0.015175, 0.015175, 0.015173, 0.015172, 0.015170",\ + "0.067694, 0.067694, 0.067694, 0.067694, 0.067694",\ + "0.170296, 0.170296, 0.170296, 0.170296, 0.170296",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122219, 1.122219, 1.122219, 1.122219, 1.122219",\ + "0.015175, 0.015175, 0.015173, 0.015172, 0.015170",\ + "0.067694, 0.067694, 0.067694, 0.067694, 0.067694",\ + "0.170296, 0.170296, 0.170296, 0.170296, 0.170296",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122219, 1.122219, 1.122219, 1.122219, 1.122219",\ + "0.015175, 0.015175, 0.015173, 0.015172, 0.015170",\ + "0.067694, 0.067694, 0.067694, 0.067694, 0.067694",\ + "0.170296, 0.170296, 0.170296, 0.170296, 0.170296",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122219, 1.122219, 1.122219, 1.122219, 1.122219",\ + "0.015175, 0.015175, 0.015173, 0.015172, 0.015170",\ + "0.067694, 0.067694, 0.067694, 0.067694, 0.067694",\ + "0.170296, 0.170296, 0.170296, 0.170296, 0.170296",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122219, 1.122219, 1.122219, 1.122219, 1.122219"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_min_2690*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[37]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.362229, 0.589916, 0.774631, 1.069784, 1.640082",\ + "0.412228, 0.639915, 0.824630, 1.119783, 1.690081",\ + "0.492795, 0.719167, 0.903893, 1.199092, 1.769493",\ + "0.714028, 0.940400, 1.125127, 1.420325, 1.990727",\ + "1.275872, 1.502245, 1.686972, 1.982170, 2.552572",\ + "0.450567, 0.677234, 0.861912, 1.157089, 1.727435",\ + "0.500567, 0.727233, 0.911911, 1.207088, 1.777434",\ + "0.581133, 0.806485, 0.991174, 1.286397, 1.856847",\ + "0.802366, 1.027718, 1.212408, 1.507630, 2.078080",\ + "1.364210, 1.589563, 1.774253, 2.069476, 2.639925",\ + "0.539804, 0.757567, 0.941939, 1.237118, 1.807467",\ + "0.589803, 0.807566, 0.991938, 1.287117, 1.857466",\ + "0.670367, 0.886817, 1.071201, 1.366425, 1.936878",\ + "0.891600, 1.108051, 1.292434, 1.587659, 2.158112",\ + "1.453444, 1.669896, 1.854280, 2.149504, 2.719957",\ + "0.603371, 0.815390, 0.999649, 1.294559, 1.864506",\ + "0.653370, 0.865389, 1.049648, 1.344558, 1.914505",\ + "0.733934, 0.944641, 1.128911, 1.423867, 1.993918",\ + "0.955166, 1.165874, 1.350144, 1.645100, 2.215151",\ + "1.517011, 1.727719, 1.911989, 2.206946, 2.776997",\ + "0.939278, 1.120654, 1.303307, 1.597741, 2.166757",\ + "0.989277, 1.170653, 1.353306, 1.647740, 2.216756",\ + "1.069831, 1.249906, 1.432569, 1.727049, 2.296169",\ + "1.291064, 1.471139, 1.653802, 1.948282, 2.517402",\ + "1.852909, 2.032984, 2.215647, 2.510128, 3.079247"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.027448, 0.027445, 0.027445, 0.027445, 0.027445",\ + "0.129491, 0.129491, 0.129491, 0.129491, 0.129491",\ + "0.314623, 0.314623, 0.314623, 0.314623, 0.314623",\ + "0.831920, 0.831920, 0.831920, 0.831920, 0.831920",\ + "2.131897, 2.131897, 2.131897, 2.131897, 2.131897",\ + "0.027448, 0.027445, 0.027445, 0.027445, 0.027445",\ + "0.129491, 0.129491, 0.129491, 0.129491, 0.129491",\ + "0.314623, 0.314623, 0.314623, 0.314623, 0.314623",\ + "0.831920, 0.831920, 0.831920, 0.831920, 0.831920",\ + "2.131897, 2.131897, 2.131897, 2.131897, 2.131897",\ + "0.027447, 0.027445, 0.027445, 0.027445, 0.027445",\ + "0.129491, 0.129491, 0.129491, 0.129491, 0.129491",\ + "0.314623, 0.314623, 0.314623, 0.314623, 0.314623",\ + "0.831920, 0.831920, 0.831920, 0.831920, 0.831920",\ + "2.131897, 2.131897, 2.131897, 2.131897, 2.131897",\ + "0.027447, 0.027445, 0.027445, 0.027445, 0.027445",\ + "0.129491, 0.129491, 0.129491, 0.129491, 0.129491",\ + "0.314623, 0.314623, 0.314623, 0.314623, 0.314623",\ + "0.831920, 0.831920, 0.831920, 0.831920, 0.831920",\ + "2.131897, 2.131897, 2.131897, 2.131897, 2.131897",\ + "0.027446, 0.027445, 0.027445, 0.027445, 0.027445",\ + "0.129491, 0.129491, 0.129491, 0.129491, 0.129491",\ + "0.314623, 0.314623, 0.314623, 0.314623, 0.314623",\ + "0.831920, 0.831920, 0.831920, 0.831920, 0.831920",\ + "2.131897, 2.131897, 2.131897, 2.131897, 2.131897"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.356406, 0.582783, 0.767510, 1.062709, 1.633111",\ + "0.382155, 0.608528, 0.793254, 1.088453, 1.658855",\ + "0.436803, 0.663177, 0.847903, 1.143102, 1.713504",\ + "0.586677, 0.813050, 0.997777, 1.292975, 1.863377",\ + "0.942409, 1.170095, 1.354810, 1.649963, 2.220260",\ + "0.444744, 0.670102, 0.854791, 1.150014, 1.720465",\ + "0.470493, 0.695846, 0.880535, 1.175758, 1.746208",\ + "0.525141, 0.750495, 0.935184, 1.230407, 1.800857",\ + "0.675015, 0.900368, 1.085058, 1.380280, 1.950730",\ + "1.030747, 1.257413, 1.442091, 1.737268, 2.307614",\ + "0.533979, 0.750434, 0.934818, 1.230043, 1.800496",\ + "0.559727, 0.776178, 0.960562, 1.255787, 1.826240",\ + "0.614376, 0.830827, 1.015211, 1.310436, 1.880889",\ + "0.764250, 0.980701, 1.165085, 1.460309, 2.030762",\ + "1.119983, 1.337745, 1.522118, 1.817296, 2.387645",\ + "0.597545, 0.808257, 0.992528, 1.287485, 1.857536",\ + "0.623294, 0.834002, 1.018272, 1.313228, 1.883280",\ + "0.677942, 0.888651, 1.072921, 1.367877, 1.937928",\ + "0.827816, 1.038524, 1.222794, 1.517751, 2.087802",\ + "1.183551, 1.395569, 1.579828, 1.874738, 2.444685",\ + "0.933445, 1.113522, 1.296186, 1.590666, 2.159787",\ + "0.959191, 1.139267, 1.321930, 1.616410, 2.185530",\ + "1.013840, 1.193916, 1.376579, 1.671059, 2.240179",\ + "1.163714, 1.343789, 1.526452, 1.820932, 2.390052",\ + "1.519457, 1.700833, 1.883486, 2.177920, 2.746935"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.015179, 0.015170, 0.015169, 0.015169, 0.015168",\ + "0.067695, 0.067694, 0.067694, 0.067694, 0.067694",\ + "0.170296, 0.170296, 0.170296, 0.170296, 0.170296",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122219, 1.122219, 1.122219, 1.122219, 1.122219",\ + "0.015179, 0.015170, 0.015169, 0.015169, 0.015168",\ + "0.067695, 0.067694, 0.067694, 0.067694, 0.067694",\ + "0.170296, 0.170296, 0.170296, 0.170296, 0.170296",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122219, 1.122219, 1.122219, 1.122219, 1.122219",\ + "0.015178, 0.015170, 0.015169, 0.015169, 0.015168",\ + "0.067695, 0.067694, 0.067694, 0.067694, 0.067694",\ + "0.170296, 0.170296, 0.170296, 0.170296, 0.170296",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122219, 1.122219, 1.122219, 1.122219, 1.122219",\ + "0.015177, 0.015170, 0.015169, 0.015169, 0.015168",\ + "0.067695, 0.067694, 0.067694, 0.067694, 0.067694",\ + "0.170296, 0.170296, 0.170296, 0.170296, 0.170296",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122219, 1.122219, 1.122219, 1.122219, 1.122219",\ + "0.015173, 0.015170, 0.015169, 0.015169, 0.015168",\ + "0.067694, 0.067694, 0.067694, 0.067694, 0.067694",\ + "0.170296, 0.170296, 0.170296, 0.170296, 0.170296",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122219, 1.122219, 1.122219, 1.122219, 1.122219"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_min_2258*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[39]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011"); + values ( "0.309159, 0.541794, 0.727047, 1.026481, 1.606878",\ + "0.349227, 0.581863, 0.767115, 1.066549, 1.646947",\ + "0.425113, 0.657750, 0.843001, 1.142434, 1.722832",\ + "0.644749, 0.877387, 1.062637, 1.362070, 1.942469",\ + "1.197363, 1.430001, 1.615251, 1.914684, 2.495083",\ + "0.397555, 0.629112, 0.814328, 1.113786, 1.694232",\ + "0.437623, 0.669181, 0.854396, 1.153854, 1.734300",\ + "0.513508, 0.745068, 0.930282, 1.229739, 1.810186",\ + "0.733145, 0.964705, 1.149918, 1.449375, 2.029822",\ + "1.285759, 1.517319, 1.702532, 2.001989, 2.582437",\ + "0.486858, 0.709445, 0.894355, 1.193814, 1.774263",\ + "0.526927, 0.749514, 0.934423, 1.233882, 1.814332",\ + "0.602812, 0.825401, 1.010309, 1.309767, 1.890217",\ + "0.822449, 1.045038, 1.229945, 1.529404, 2.109854",\ + "1.375063, 1.597652, 1.782559, 2.082017, 2.662468",\ + "0.550445, 0.767276, 0.952066, 1.251268, 1.831326",\ + "0.590513, 0.807345, 0.992134, 1.291336, 1.871395",\ + "0.666399, 0.883232, 1.068019, 1.367221, 1.947281",\ + "0.886036, 1.102869, 1.287656, 1.586857, 2.166918",\ + "1.438650, 1.655483, 1.840269, 2.139471, 2.719532",\ + "0.886476, 1.072598, 1.255724, 1.554460, 2.133606",\ + "0.926545, 1.112668, 1.295792, 1.594528, 2.173675",\ + "1.002432, 1.188554, 1.371677, 1.670413, 2.249560",\ + "1.222068, 1.408191, 1.591314, 1.890050, 2.469197",\ + "1.774683, 1.960806, 2.143928, 2.442663, 3.021811"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011"); + values ( "0.048599, 0.048599, 0.048599, 0.048599, 0.048600",\ + "0.136046, 0.136046, 0.136046, 0.136046, 0.136046",\ + "0.314136, 0.314136, 0.314136, 0.314136, 0.314136",\ + "0.833556, 0.833556, 0.833556, 0.833556, 0.833556",\ + "2.135299, 2.135299, 2.135299, 2.135304, 2.135317",\ + "0.048599, 0.048599, 0.048599, 0.048599, 0.048600",\ + "0.136046, 0.136046, 0.136046, 0.136046, 0.136046",\ + "0.314136, 0.314136, 0.314136, 0.314136, 0.314136",\ + "0.833556, 0.833556, 0.833556, 0.833556, 0.833556",\ + "2.135299, 2.135299, 2.135299, 2.135304, 2.135317",\ + "0.048599, 0.048599, 0.048599, 0.048599, 0.048600",\ + "0.136046, 0.136046, 0.136046, 0.136046, 0.136046",\ + "0.314136, 0.314136, 0.314136, 0.314136, 0.314136",\ + "0.833556, 0.833556, 0.833556, 0.833556, 0.833556",\ + "2.135299, 2.135299, 2.135299, 2.135304, 2.135317",\ + "0.048599, 0.048599, 0.048599, 0.048599, 0.048600",\ + "0.136046, 0.136046, 0.136046, 0.136046, 0.136046",\ + "0.314136, 0.314136, 0.314136, 0.314136, 0.314136",\ + "0.833556, 0.833556, 0.833556, 0.833556, 0.833556",\ + "2.135299, 2.135299, 2.135299, 2.135304, 2.135317",\ + "0.048599, 0.048599, 0.048599, 0.048599, 0.048600",\ + "0.136046, 0.136046, 0.136046, 0.136046, 0.136046",\ + "0.314136, 0.314136, 0.314136, 0.314136, 0.314136",\ + "0.833556, 0.833556, 0.833556, 0.833556, 0.833556",\ + "2.135299, 2.135299, 2.135299, 2.135304, 2.135317"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011"); + values ( "0.283419, 0.516054, 0.701307, 1.000741, 1.581138",\ + "0.313066, 0.545699, 0.730954, 1.030388, 1.610784",\ + "0.365001, 0.597634, 0.782889, 1.082323, 1.662719",\ + "0.513456, 0.746088, 0.931344, 1.230778, 1.811174",\ + "0.885857, 1.118488, 1.303746, 1.603180, 2.183575",\ + "0.371815, 0.603373, 0.788588, 1.088046, 1.668492",\ + "0.401461, 0.633018, 0.818235, 1.117693, 1.698138",\ + "0.453396, 0.684952, 0.870170, 1.169628, 1.750072",\ + "0.601851, 0.833406, 1.018625, 1.318083, 1.898527",\ + "0.974253, 1.205806, 1.391027, 1.690485, 2.270928",\ + "0.461119, 0.683706, 0.868615, 1.168074, 1.748523",\ + "0.490765, 0.713351, 0.898262, 1.197721, 1.778169",\ + "0.542700, 0.765285, 0.950197, 1.249656, 1.830104",\ + "0.691155, 0.913739, 1.098652, 1.398111, 1.978559",\ + "1.063556, 1.286139, 1.471054, 1.770513, 2.350960",\ + "0.524705, 0.741537, 0.926326, 1.225528, 1.805587",\ + "0.554351, 0.771182, 0.955972, 1.255175, 1.835233",\ + "0.606286, 0.823116, 1.007907, 1.307110, 1.887167",\ + "0.754741, 0.971570, 1.156362, 1.455565, 2.035622",\ + "1.127142, 1.343970, 1.528764, 1.827967, 2.408023",\ + "0.860737, 1.046859, 1.229984, 1.528720, 2.107866",\ + "0.890382, 1.076504, 1.259631, 1.558367, 2.137512",\ + "0.942317, 1.128438, 1.311566, 1.610302, 2.189447",\ + "1.090771, 1.276893, 1.460021, 1.758757, 2.337902",\ + "1.463172, 1.649293, 1.832423, 2.131159, 2.710303"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011"); + values ( "0.026622, 0.026622, 0.026622, 0.026622, 0.026622",\ + "0.075784, 0.075784, 0.075784, 0.075784, 0.075784",\ + "0.169301, 0.169301, 0.169301, 0.169301, 0.169301",\ + "0.439546, 0.439546, 0.439546, 0.439549, 0.439556",\ + "1.119113, 1.119113, 1.119113, 1.119121, 1.119143",\ + "0.026622, 0.026622, 0.026622, 0.026622, 0.026622",\ + "0.075784, 0.075784, 0.075784, 0.075784, 0.075784",\ + "0.169301, 0.169301, 0.169301, 0.169301, 0.169301",\ + "0.439546, 0.439546, 0.439546, 0.439549, 0.439556",\ + "1.119113, 1.119113, 1.119113, 1.119121, 1.119143",\ + "0.026622, 0.026622, 0.026622, 0.026622, 0.026622",\ + "0.075784, 0.075784, 0.075784, 0.075784, 0.075784",\ + "0.169301, 0.169301, 0.169301, 0.169301, 0.169301",\ + "0.439546, 0.439546, 0.439546, 0.439549, 0.439556",\ + "1.119113, 1.119113, 1.119113, 1.119121, 1.119143",\ + "0.026622, 0.026622, 0.026622, 0.026622, 0.026622",\ + "0.075784, 0.075784, 0.075784, 0.075784, 0.075784",\ + "0.169301, 0.169301, 0.169301, 0.169301, 0.169301",\ + "0.439546, 0.439546, 0.439546, 0.439549, 0.439556",\ + "1.119113, 1.119113, 1.119113, 1.119121, 1.119143",\ + "0.026622, 0.026622, 0.026622, 0.026622, 0.026622",\ + "0.075784, 0.075784, 0.075784, 0.075784, 0.075784",\ + "0.169301, 0.169301, 0.169301, 0.169301, 0.169301",\ + "0.439546, 0.439546, 0.439546, 0.439549, 0.439556",\ + "1.119113, 1.119113, 1.119113, 1.119121, 1.119143"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_min_2336*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[41]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.409726, 0.620265, 0.806005, 1.096897, 1.655910",\ + "0.459725, 0.670264, 0.856003, 1.146896, 1.705909",\ + "0.539627, 0.750535, 0.935997, 1.226788, 1.785793",\ + "0.760860, 0.971768, 1.157229, 1.448020, 2.007025",\ + "1.322703, 1.533611, 1.719072, 2.009862, 2.568867",\ + "0.498079, 0.707583, 0.893286, 1.184203, 1.743264",\ + "0.548078, 0.757582, 0.943284, 1.234201, 1.793262",\ + "0.627981, 0.837853, 1.023278, 1.314093, 1.873147",\ + "0.849213, 1.059086, 1.244510, 1.535325, 2.094379",\ + "1.411056, 1.620929, 1.806353, 2.097167, 2.656221",\ + "0.587342, 0.787916, 0.973312, 1.264231, 1.823296",\ + "0.637340, 0.837914, 1.023311, 1.314230, 1.873294",\ + "0.717243, 0.918186, 1.103305, 1.394121, 1.953178",\ + "0.938476, 1.139418, 1.324537, 1.615354, 2.174411",\ + "1.500319, 1.701261, 1.886380, 2.177196, 2.736252",\ + "0.650926, 0.845743, 1.031024, 1.321659, 1.880308",\ + "0.700925, 0.895741, 1.081023, 1.371658, 1.930306",\ + "0.780828, 0.976013, 1.161016, 1.451549, 2.010190",\ + "1.002060, 1.197245, 1.382248, 1.672781, 2.231423",\ + "1.563903, 1.759089, 1.944091, 2.234624, 2.793264",\ + "0.970227, 1.151036, 1.334683, 1.624829, 2.182525",\ + "1.020226, 1.201034, 1.384681, 1.674827, 2.232523",\ + "1.100497, 1.281306, 1.464674, 1.754719, 2.312408",\ + "1.321730, 1.502538, 1.685907, 1.975951, 2.533640",\ + "1.883573, 2.064381, 2.247749, 2.537794, 3.095482"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.027428, 0.027428, 0.027429, 0.027429, 0.027431",\ + "0.129493, 0.129493, 0.129493, 0.129493, 0.129493",\ + "0.314623, 0.314623, 0.314623, 0.314623, 0.314623",\ + "0.831917, 0.831917, 0.831917, 0.831917, 0.831917",\ + "2.131895, 2.131895, 2.131895, 2.131895, 2.131896",\ + "0.027428, 0.027428, 0.027429, 0.027429, 0.027431",\ + "0.129493, 0.129493, 0.129493, 0.129493, 0.129493",\ + "0.314623, 0.314623, 0.314623, 0.314623, 0.314623",\ + "0.831917, 0.831917, 0.831917, 0.831917, 0.831917",\ + "2.131895, 2.131895, 2.131895, 2.131895, 2.131896",\ + "0.027428, 0.027428, 0.027429, 0.027429, 0.027431",\ + "0.129493, 0.129493, 0.129493, 0.129493, 0.129493",\ + "0.314623, 0.314623, 0.314623, 0.314623, 0.314623",\ + "0.831917, 0.831917, 0.831917, 0.831917, 0.831917",\ + "2.131895, 2.131895, 2.131895, 2.131895, 2.131896",\ + "0.027428, 0.027428, 0.027429, 0.027429, 0.027431",\ + "0.129493, 0.129493, 0.129493, 0.129493, 0.129493",\ + "0.314623, 0.314623, 0.314623, 0.314623, 0.314623",\ + "0.831917, 0.831917, 0.831917, 0.831917, 0.831917",\ + "2.131895, 2.131895, 2.131895, 2.131895, 2.131896",\ + "0.027428, 0.027428, 0.027429, 0.027429, 0.027431",\ + "0.129493, 0.129493, 0.129493, 0.129493, 0.129493",\ + "0.314623, 0.314623, 0.314623, 0.314623, 0.314623",\ + "0.831917, 0.831917, 0.831917, 0.831917, 0.831917",\ + "2.131895, 2.131895, 2.131895, 2.131895, 2.131896"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.403233, 0.614141, 0.799601, 1.090390, 1.649393",\ + "0.428986, 0.639894, 0.825355, 1.116146, 1.675151",\ + "0.483635, 0.694543, 0.880004, 1.170794, 1.729799",\ + "0.633508, 0.844416, 1.029877, 1.320668, 1.879673",\ + "0.989900, 1.200439, 1.386178, 1.677071, 2.236084",\ + "0.491587, 0.701459, 0.886882, 1.177695, 1.736746",\ + "0.517340, 0.727212, 0.912636, 1.203451, 1.762504",\ + "0.571988, 0.781861, 0.967285, 1.258099, 1.817153",\ + "0.721862, 0.931734, 1.117158, 1.407973, 1.967026",\ + "1.078253, 1.287757, 1.473459, 1.764376, 2.323438",\ + "0.580849, 0.781792, 0.966909, 1.257724, 1.816778",\ + "0.606602, 0.807544, 0.992663, 1.283479, 1.842536",\ + "0.661251, 0.862193, 1.047312, 1.338128, 1.897184",\ + "0.811124, 1.012067, 1.197185, 1.488001, 2.047058",\ + "1.167515, 1.368089, 1.553486, 1.844405, 2.403470",\ + "0.644433, 0.839619, 1.024620, 1.315152, 1.873790",\ + "0.670186, 0.865372, 1.050374, 1.340907, 1.899548",\ + "0.724835, 0.920020, 1.105023, 1.395556, 1.954196",\ + "0.874709, 1.069894, 1.254896, 1.545429, 2.104070",\ + "1.231100, 1.425916, 1.611198, 1.901833, 2.460482",\ + "0.964103, 1.144912, 1.328278, 1.618321, 2.176007",\ + "0.989856, 1.170664, 1.354033, 1.644077, 2.201765",\ + "1.044504, 1.225313, 1.408681, 1.698726, 2.256414",\ + "1.194378, 1.375186, 1.558555, 1.848599, 2.406287",\ + "1.550400, 1.731209, 1.914856, 2.205003, 2.762699"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.015187, 0.015187, 0.015189, 0.015192, 0.015197",\ + "0.067696, 0.067696, 0.067696, 0.067696, 0.067697",\ + "0.170295, 0.170295, 0.170295, 0.170295, 0.170295",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122218, 1.122218, 1.122218, 1.122218, 1.122218",\ + "0.015187, 0.015187, 0.015189, 0.015192, 0.015197",\ + "0.067696, 0.067696, 0.067696, 0.067696, 0.067697",\ + "0.170295, 0.170295, 0.170295, 0.170295, 0.170295",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122218, 1.122218, 1.122218, 1.122218, 1.122218",\ + "0.015187, 0.015187, 0.015189, 0.015192, 0.015197",\ + "0.067696, 0.067696, 0.067696, 0.067696, 0.067697",\ + "0.170295, 0.170295, 0.170295, 0.170295, 0.170295",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122218, 1.122218, 1.122218, 1.122218, 1.122218",\ + "0.015187, 0.015187, 0.015189, 0.015192, 0.015197",\ + "0.067696, 0.067696, 0.067696, 0.067696, 0.067697",\ + "0.170295, 0.170295, 0.170295, 0.170295, 0.170295",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122218, 1.122218, 1.122218, 1.122218, 1.122218",\ + "0.015187, 0.015187, 0.015189, 0.015192, 0.015197",\ + "0.067696, 0.067696, 0.067696, 0.067696, 0.067697",\ + "0.170295, 0.170295, 0.170295, 0.170295, 0.170295",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122218, 1.122218, 1.122218, 1.122218, 1.122218"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_min_2358*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[42]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.383225, 0.593036, 0.770038, 1.054268, 1.604513",\ + "0.433223, 0.643035, 0.820037, 1.104266, 1.654512",\ + "0.513146, 0.723307, 0.900324, 1.184595, 1.734933",\ + "0.734379, 0.944539, 1.121556, 1.405827, 1.956165",\ + "1.296223, 1.506382, 1.683399, 1.967670, 2.518007",\ + "0.471502, 0.680354, 0.857319, 1.141573, 1.691867",\ + "0.521500, 0.730353, 0.907318, 1.191571, 1.741865",\ + "0.601422, 0.810625, 0.987605, 1.271900, 1.822286",\ + "0.822655, 1.031858, 1.208837, 1.493132, 2.043518",\ + "1.384499, 1.593700, 1.770680, 2.054975, 2.605360",\ + "0.560557, 0.760687, 0.937346, 1.221601, 1.771898",\ + "0.610556, 0.810685, 0.987345, 1.271600, 1.821897",\ + "0.690474, 0.890957, 1.067632, 1.351929, 1.902318",\ + "0.911707, 1.112190, 1.288864, 1.573161, 2.123550",\ + "1.473551, 1.674033, 1.850707, 2.135003, 2.685391",\ + "0.623957, 0.818509, 0.995037, 1.279018, 1.828889",\ + "0.673955, 0.868507, 1.045036, 1.329017, 1.878888",\ + "0.753870, 0.948779, 1.125323, 1.409346, 1.959309",\ + "0.975103, 1.170012, 1.346555, 1.630578, 2.180541",\ + "1.536947, 1.731855, 1.908398, 2.192420, 2.742383",\ + "0.944232, 1.123764, 1.298692, 1.582179, 2.131082",\ + "0.994231, 1.173763, 1.348691, 1.632178, 2.181080",\ + "1.074451, 1.254037, 1.428978, 1.712507, 2.261501",\ + "1.295684, 1.475269, 1.650211, 1.933739, 2.482733",\ + "1.857528, 2.037112, 2.212053, 2.495582, 3.044575"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.027427, 0.027429, 0.027430, 0.027431, 0.027432",\ + "0.129493, 0.129493, 0.129493, 0.129493, 0.129493",\ + "0.314624, 0.314623, 0.314623, 0.314623, 0.314623",\ + "0.831917, 0.831917, 0.831917, 0.831917, 0.831918",\ + "2.131895, 2.131895, 2.131895, 2.131895, 2.131896",\ + "0.027427, 0.027429, 0.027430, 0.027431, 0.027432",\ + "0.129493, 0.129493, 0.129493, 0.129493, 0.129493",\ + "0.314624, 0.314623, 0.314623, 0.314623, 0.314623",\ + "0.831917, 0.831917, 0.831917, 0.831917, 0.831918",\ + "2.131895, 2.131895, 2.131895, 2.131895, 2.131896",\ + "0.027428, 0.027429, 0.027430, 0.027431, 0.027432",\ + "0.129493, 0.129493, 0.129493, 0.129493, 0.129493",\ + "0.314624, 0.314623, 0.314623, 0.314623, 0.314623",\ + "0.831917, 0.831917, 0.831917, 0.831917, 0.831918",\ + "2.131895, 2.131895, 2.131895, 2.131895, 2.131896",\ + "0.027428, 0.027429, 0.027430, 0.027431, 0.027432",\ + "0.129493, 0.129493, 0.129493, 0.129493, 0.129493",\ + "0.314624, 0.314623, 0.314623, 0.314623, 0.314623",\ + "0.831917, 0.831917, 0.831917, 0.831917, 0.831918",\ + "2.131895, 2.131895, 2.131895, 2.131895, 2.131896",\ + "0.027428, 0.027429, 0.027430, 0.027431, 0.027432",\ + "0.129493, 0.129493, 0.129493, 0.129493, 0.129493",\ + "0.314624, 0.314623, 0.314623, 0.314623, 0.314623",\ + "0.831917, 0.831917, 0.831917, 0.831917, 0.831918",\ + "2.131895, 2.131895, 2.131895, 2.131895, 2.131896"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.376757, 0.586911, 0.763927, 1.048197, 1.598532",\ + "0.402506, 0.612665, 0.789682, 1.073953, 1.624290",\ + "0.457155, 0.667314, 0.844331, 1.128602, 1.678938",\ + "0.607028, 0.817188, 0.994204, 1.278475, 1.828812",\ + "0.963398, 1.173210, 1.350212, 1.634442, 2.184688",\ + "0.465033, 0.674229, 0.851208, 1.135502, 1.685885",\ + "0.490782, 0.699983, 0.876963, 1.161258, 1.711643",\ + "0.545431, 0.754632, 0.931612, 1.215907, 1.766292",\ + "0.695304, 0.904506, 1.081485, 1.365780, 1.916165",\ + "1.051675, 1.260528, 1.437493, 1.721747, 2.272042",\ + "0.554085, 0.754561, 0.931235, 1.215531, 1.765917",\ + "0.579834, 0.780316, 0.956990, 1.241287, 1.791675",\ + "0.634483, 0.834964, 1.011639, 1.295935, 1.846323",\ + "0.784356, 0.984838, 1.161512, 1.445809, 1.996197",\ + "1.140731, 1.340860, 1.517520, 1.801775, 2.352073",\ + "0.617480, 0.812384, 0.988926, 1.272948, 1.822908",\ + "0.643230, 0.838138, 1.014681, 1.298704, 1.848666",\ + "0.697878, 0.892787, 1.069330, 1.353353, 1.903315",\ + "0.847752, 1.042660, 1.219203, 1.503226, 2.053188",\ + "1.204130, 1.398682, 1.575211, 1.859193, 2.409064",\ + "0.938061, 1.117640, 1.292582, 1.576109, 2.125101",\ + "0.963811, 1.143395, 1.318336, 1.601865, 2.150858",\ + "1.018459, 1.198044, 1.372985, 1.656513, 2.205507",\ + "1.168333, 1.347917, 1.522858, 1.806387, 2.355381",\ + "1.524406, 1.703938, 1.878866, 2.162354, 2.711256"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.015179, 0.015189, 0.015191, 0.015192, 0.015197",\ + "0.067695, 0.067696, 0.067696, 0.067696, 0.067697",\ + "0.170295, 0.170295, 0.170295, 0.170295, 0.170295",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122218, 1.122218, 1.122218, 1.122218, 1.122218",\ + "0.015179, 0.015189, 0.015191, 0.015192, 0.015197",\ + "0.067695, 0.067696, 0.067696, 0.067696, 0.067697",\ + "0.170295, 0.170295, 0.170295, 0.170295, 0.170295",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122218, 1.122218, 1.122218, 1.122218, 1.122218",\ + "0.015180, 0.015189, 0.015191, 0.015192, 0.015197",\ + "0.067695, 0.067696, 0.067696, 0.067696, 0.067697",\ + "0.170295, 0.170295, 0.170295, 0.170295, 0.170295",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122218, 1.122218, 1.122218, 1.122218, 1.122218",\ + "0.015181, 0.015190, 0.015191, 0.015192, 0.015197",\ + "0.067695, 0.067696, 0.067696, 0.067696, 0.067697",\ + "0.170295, 0.170295, 0.170295, 0.170295, 0.170295",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122218, 1.122218, 1.122218, 1.122218, 1.122218",\ + "0.015181, 0.015190, 0.015191, 0.015192, 0.015197",\ + "0.067695, 0.067696, 0.067696, 0.067696, 0.067697",\ + "0.170295, 0.170295, 0.170295, 0.170295, 0.170295",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122218, 1.122218, 1.122218, 1.122218, 1.122218"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_min_2303*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[43]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011"); + values ( "0.405550, 0.622555, 0.800684, 1.089918, 1.651394",\ + "0.445619, 0.662624, 0.840753, 1.129987, 1.691463",\ + "0.521505, 0.738510, 0.916639, 1.205873, 1.767349",\ + "0.741141, 0.958147, 1.136276, 1.425510, 1.986986",\ + "1.293756, 1.510761, 1.688890, 1.978124, 2.539600",\ + "0.493926, 0.709873, 0.887965, 1.177224, 1.738747",\ + "0.533995, 0.749942, 0.928034, 1.217292, 1.778816",\ + "0.609881, 0.825828, 1.003920, 1.293178, 1.854702",\ + "0.829518, 1.045465, 1.223557, 1.512815, 2.074339",\ + "1.382132, 1.598079, 1.776171, 2.065429, 2.626953",\ + "0.583177, 0.790206, 0.967992, 1.257252, 1.818779",\ + "0.623246, 0.830275, 1.008061, 1.297321, 1.858848",\ + "0.699132, 0.906161, 1.083947, 1.373207, 1.934734",\ + "0.918768, 1.125798, 1.303584, 1.592844, 2.154371",\ + "1.471382, 1.678412, 1.856198, 2.145458, 2.706985",\ + "0.646716, 0.848023, 1.025686, 1.314683, 1.875797",\ + "0.686785, 0.888092, 1.065755, 1.354752, 1.915866",\ + "0.762671, 0.963978, 1.141641, 1.430638, 1.991752",\ + "0.982307, 1.183615, 1.361278, 1.650275, 2.211389",\ + "1.534921, 1.736229, 1.913892, 2.202889, 2.764003",\ + "0.974642, 1.153245, 1.329341, 1.617855, 2.178021",\ + "1.014711, 1.193314, 1.369410, 1.657924, 2.218090",\ + "1.090597, 1.269200, 1.445296, 1.733810, 2.293976",\ + "1.310234, 1.488837, 1.664933, 1.953447, 2.513613",\ + "1.862848, 2.041451, 2.217547, 2.506061, 3.066227"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011"); + values ( "0.048600, 0.048600, 0.048600, 0.048600, 0.048600",\ + "0.136047, 0.136047, 0.136047, 0.136047, 0.136047",\ + "0.314137, 0.314137, 0.314137, 0.314137, 0.314137",\ + "0.833559, 0.833559, 0.833559, 0.833559, 0.833558",\ + "2.135322, 2.135322, 2.135323, 2.135323, 2.135323",\ + "0.048600, 0.048600, 0.048600, 0.048600, 0.048600",\ + "0.136047, 0.136047, 0.136047, 0.136047, 0.136047",\ + "0.314137, 0.314137, 0.314137, 0.314137, 0.314137",\ + "0.833559, 0.833559, 0.833559, 0.833559, 0.833558",\ + "2.135322, 2.135322, 2.135323, 2.135323, 2.135323",\ + "0.048600, 0.048600, 0.048600, 0.048600, 0.048600",\ + "0.136047, 0.136047, 0.136047, 0.136047, 0.136047",\ + "0.314137, 0.314137, 0.314137, 0.314137, 0.314137",\ + "0.833559, 0.833559, 0.833559, 0.833559, 0.833558",\ + "2.135322, 2.135322, 2.135323, 2.135323, 2.135323",\ + "0.048600, 0.048600, 0.048600, 0.048600, 0.048600",\ + "0.136047, 0.136047, 0.136047, 0.136047, 0.136047",\ + "0.314137, 0.314137, 0.314137, 0.314137, 0.314137",\ + "0.833559, 0.833559, 0.833559, 0.833559, 0.833558",\ + "2.135322, 2.135322, 2.135323, 2.135323, 2.135323",\ + "0.048600, 0.048600, 0.048600, 0.048600, 0.048600",\ + "0.136047, 0.136047, 0.136047, 0.136047, 0.136047",\ + "0.314137, 0.314137, 0.314137, 0.314137, 0.314137",\ + "0.833559, 0.833559, 0.833559, 0.833559, 0.833558",\ + "2.135322, 2.135322, 2.135323, 2.135323, 2.135323"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011"); + values ( "0.379810, 0.596815, 0.774944, 1.064179, 1.625654",\ + "0.409456, 0.626461, 0.804590, 1.093824, 1.655300",\ + "0.461390, 0.678396, 0.856524, 1.145759, 1.707235",\ + "0.609845, 0.826850, 1.004979, 1.294214, 1.855689",\ + "0.982246, 1.199251, 1.377380, 1.666614, 2.228090",\ + "0.468186, 0.684134, 0.862225, 1.151484, 1.713008",\ + "0.497832, 0.713779, 0.891871, 1.181129, 1.742653",\ + "0.549766, 0.765714, 0.943805, 1.233064, 1.794588",\ + "0.698221, 0.914169, 1.092260, 1.381519, 1.943043",\ + "1.070622, 1.286569, 1.464661, 1.753919, 2.315443",\ + "0.557437, 0.764467, 0.942252, 1.231513, 1.793039",\ + "0.587083, 0.794112, 0.971898, 1.261158, 1.822685",\ + "0.639017, 0.846047, 1.023832, 1.313093, 1.874619",\ + "0.787472, 0.994502, 1.172287, 1.461547, 2.023074",\ + "1.159873, 1.366902, 1.544688, 1.833948, 2.395475",\ + "0.620976, 0.822284, 0.999946, 1.288943, 1.850057",\ + "0.650622, 0.851929, 1.029592, 1.318589, 1.879703",\ + "0.702556, 0.903864, 1.081526, 1.370523, 1.931637",\ + "0.851011, 1.052318, 1.229981, 1.518978, 2.080092",\ + "1.223412, 1.424719, 1.602382, 1.891379, 2.452493",\ + "0.948902, 1.127506, 1.303602, 1.592116, 2.152281",\ + "0.978548, 1.157151, 1.333247, 1.621761, 2.181927",\ + "1.030483, 1.209086, 1.385182, 1.673696, 2.233861",\ + "1.178937, 1.357541, 1.533637, 1.822151, 2.382316",\ + "1.551338, 1.729941, 1.906037, 2.194551, 2.754717"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011"); + values ( "0.026625, 0.026625, 0.026625, 0.026625, 0.026625",\ + "0.075785, 0.075785, 0.075785, 0.075785, 0.075785",\ + "0.169304, 0.169304, 0.169304, 0.169304, 0.169303",\ + "0.439544, 0.439544, 0.439544, 0.439546, 0.439549",\ + "1.119108, 1.119108, 1.119109, 1.119113, 1.119123",\ + "0.026625, 0.026625, 0.026625, 0.026625, 0.026625",\ + "0.075785, 0.075785, 0.075785, 0.075785, 0.075785",\ + "0.169304, 0.169304, 0.169304, 0.169304, 0.169303",\ + "0.439544, 0.439544, 0.439544, 0.439546, 0.439549",\ + "1.119108, 1.119108, 1.119109, 1.119113, 1.119123",\ + "0.026625, 0.026625, 0.026625, 0.026625, 0.026625",\ + "0.075785, 0.075785, 0.075785, 0.075785, 0.075785",\ + "0.169304, 0.169304, 0.169304, 0.169304, 0.169303",\ + "0.439544, 0.439544, 0.439544, 0.439546, 0.439549",\ + "1.119108, 1.119108, 1.119109, 1.119113, 1.119123",\ + "0.026625, 0.026625, 0.026625, 0.026625, 0.026625",\ + "0.075785, 0.075785, 0.075785, 0.075785, 0.075785",\ + "0.169304, 0.169304, 0.169304, 0.169304, 0.169303",\ + "0.439544, 0.439544, 0.439544, 0.439546, 0.439549",\ + "1.119108, 1.119108, 1.119109, 1.119113, 1.119123",\ + "0.026625, 0.026625, 0.026625, 0.026625, 0.026625",\ + "0.075785, 0.075785, 0.075785, 0.075785, 0.075785",\ + "0.169304, 0.169304, 0.169304, 0.169304, 0.169303",\ + "0.439544, 0.439544, 0.439544, 0.439546, 0.439549",\ + "1.119108, 1.119108, 1.119109, 1.119113, 1.119123"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_min_2271*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[44]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011"); + values ( "0.386364, 0.626816, 0.817125, 1.119925, 1.704580",\ + "0.426433, 0.666885, 0.857194, 1.159994, 1.744649",\ + "0.502319, 0.742771, 0.933080, 1.235880, 1.820535",\ + "0.721956, 0.962408, 1.152717, 1.455517, 2.040172",\ + "1.274570, 1.515022, 1.705331, 2.008131, 2.592786",\ + "0.474664, 0.714134, 0.904406, 1.207230, 1.791934",\ + "0.514733, 0.754203, 0.944475, 1.247299, 1.832002",\ + "0.590619, 0.830089, 1.020361, 1.323185, 1.907888",\ + "0.810256, 1.049726, 1.239998, 1.542822, 2.127525",\ + "1.362870, 1.602340, 1.792612, 2.095436, 2.680139",\ + "0.563948, 0.794465, 0.984433, 1.287259, 1.871965",\ + "0.604017, 0.834534, 1.024502, 1.327327, 1.912034",\ + "0.679903, 0.910420, 1.100388, 1.403213, 1.987920",\ + "0.899539, 1.130056, 1.320024, 1.622850, 2.207557",\ + "1.452153, 1.682670, 1.872638, 2.175464, 2.760171",\ + "0.627629, 0.852329, 1.042155, 1.344718, 1.929040",\ + "0.667698, 0.892398, 1.082224, 1.384787, 1.969109",\ + "0.743584, 0.968284, 1.158110, 1.460673, 2.044995",\ + "0.963221, 1.187921, 1.377747, 1.680310, 2.264632",\ + "1.515835, 1.740535, 1.930361, 2.232924, 2.817246",\ + "0.964253, 1.157875, 1.345814, 1.647914, 2.231333",\ + "1.004322, 1.197944, 1.385883, 1.687983, 2.271402",\ + "1.080208, 1.273830, 1.461769, 1.763869, 2.347288",\ + "1.299845, 1.493467, 1.681406, 1.983506, 2.566925",\ + "1.852459, 2.046081, 2.234020, 2.536120, 3.119539"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011"); + values ( "0.048600, 0.048600, 0.048600, 0.048600, 0.048600",\ + "0.136047, 0.136047, 0.136047, 0.136047, 0.136047",\ + "0.314137, 0.314137, 0.314137, 0.314137, 0.314137",\ + "0.833559, 0.833559, 0.833559, 0.833558, 0.833558",\ + "2.135322, 2.135323, 2.135323, 2.135323, 2.135323",\ + "0.048600, 0.048600, 0.048600, 0.048600, 0.048600",\ + "0.136047, 0.136047, 0.136047, 0.136047, 0.136047",\ + "0.314137, 0.314137, 0.314137, 0.314137, 0.314137",\ + "0.833559, 0.833559, 0.833559, 0.833558, 0.833558",\ + "2.135322, 2.135323, 2.135323, 2.135323, 2.135323",\ + "0.048600, 0.048600, 0.048600, 0.048600, 0.048600",\ + "0.136047, 0.136047, 0.136047, 0.136047, 0.136047",\ + "0.314137, 0.314137, 0.314137, 0.314137, 0.314137",\ + "0.833559, 0.833559, 0.833559, 0.833558, 0.833558",\ + "2.135322, 2.135323, 2.135323, 2.135323, 2.135323",\ + "0.048600, 0.048600, 0.048600, 0.048600, 0.048600",\ + "0.136047, 0.136047, 0.136047, 0.136047, 0.136047",\ + "0.314137, 0.314137, 0.314137, 0.314137, 0.314137",\ + "0.833559, 0.833559, 0.833559, 0.833558, 0.833558",\ + "2.135322, 2.135323, 2.135323, 2.135323, 2.135323",\ + "0.048600, 0.048600, 0.048600, 0.048600, 0.048600",\ + "0.136047, 0.136047, 0.136047, 0.136047, 0.136047",\ + "0.314137, 0.314137, 0.314137, 0.314137, 0.314137",\ + "0.833559, 0.833559, 0.833559, 0.833558, 0.833558",\ + "2.135323, 2.135323, 2.135323, 2.135323, 2.135323"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011"); + values ( "0.360625, 0.601076, 0.791385, 1.094185, 1.678841",\ + "0.390270, 0.630722, 0.821031, 1.123831, 1.708486",\ + "0.442205, 0.682656, 0.872965, 1.175765, 1.760421",\ + "0.590660, 0.831111, 1.021420, 1.324220, 1.908875",\ + "0.963060, 1.203512, 1.393821, 1.696621, 2.281276",\ + "0.448924, 0.688394, 0.878666, 1.181490, 1.766194",\ + "0.478570, 0.718040, 0.908312, 1.211136, 1.795840",\ + "0.530504, 0.769974, 0.960246, 1.263070, 1.847774",\ + "0.678959, 0.918429, 1.108701, 1.411525, 1.996229",\ + "1.051360, 1.290830, 1.481102, 1.783926, 2.368629",\ + "0.538208, 0.768725, 0.958693, 1.261519, 1.846226",\ + "0.567854, 0.798371, 0.988339, 1.291164, 1.875871",\ + "0.619788, 0.850305, 1.040273, 1.343099, 1.927806",\ + "0.768243, 0.998760, 1.188728, 1.491554, 2.076260",\ + "1.140644, 1.371161, 1.561129, 1.863954, 2.448661",\ + "0.601890, 0.826589, 1.016415, 1.318978, 1.903300",\ + "0.631535, 0.856235, 1.046061, 1.348624, 1.932946",\ + "0.683470, 0.908169, 1.097996, 1.400558, 1.984880",\ + "0.831925, 1.056624, 1.246450, 1.549013, 2.133335",\ + "1.204325, 1.429025, 1.618851, 1.921414, 2.505736",\ + "0.938514, 1.132136, 1.320075, 1.622174, 2.205594",\ + "0.968159, 1.161781, 1.349720, 1.651820, 2.235239",\ + "1.020094, 1.213716, 1.401655, 1.703755, 2.287174",\ + "1.168548, 1.362170, 1.550110, 1.852209, 2.435628",\ + "1.540949, 1.734571, 1.922510, 2.224610, 2.808029"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011"); + values ( "0.026625, 0.026625, 0.026625, 0.026625, 0.026624",\ + "0.075785, 0.075785, 0.075785, 0.075785, 0.075785",\ + "0.169304, 0.169304, 0.169304, 0.169304, 0.169303",\ + "0.439544, 0.439546, 0.439547, 0.439548, 0.439550",\ + "1.119107, 1.119112, 1.119115, 1.119119, 1.119125",\ + "0.026625, 0.026625, 0.026625, 0.026625, 0.026624",\ + "0.075785, 0.075785, 0.075785, 0.075785, 0.075785",\ + "0.169304, 0.169304, 0.169304, 0.169304, 0.169303",\ + "0.439544, 0.439546, 0.439547, 0.439548, 0.439550",\ + "1.119107, 1.119112, 1.119115, 1.119119, 1.119125",\ + "0.026625, 0.026625, 0.026625, 0.026625, 0.026624",\ + "0.075785, 0.075785, 0.075785, 0.075785, 0.075785",\ + "0.169304, 0.169304, 0.169304, 0.169304, 0.169303",\ + "0.439544, 0.439546, 0.439547, 0.439548, 0.439550",\ + "1.119108, 1.119112, 1.119115, 1.119119, 1.119125",\ + "0.026625, 0.026625, 0.026625, 0.026625, 0.026624",\ + "0.075785, 0.075785, 0.075785, 0.075785, 0.075785",\ + "0.169304, 0.169304, 0.169304, 0.169304, 0.169303",\ + "0.439544, 0.439546, 0.439547, 0.439548, 0.439550",\ + "1.119108, 1.119112, 1.119115, 1.119119, 1.119125",\ + "0.026625, 0.026625, 0.026625, 0.026625, 0.026624",\ + "0.075785, 0.075785, 0.075785, 0.075785, 0.075785",\ + "0.169304, 0.169304, 0.169304, 0.169304, 0.169303",\ + "0.439545, 0.439546, 0.439547, 0.439548, 0.439550",\ + "1.119111, 1.119112, 1.119115, 1.119119, 1.119125"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_min_2441*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[46]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.401355, 0.623039, 0.801084, 1.090019, 1.650864",\ + "0.444265, 0.665948, 0.843993, 1.132928, 1.693773",\ + "0.520764, 0.742448, 0.920493, 1.209427, 1.770273",\ + "0.744064, 0.965747, 1.143793, 1.432727, 1.993572",\ + "1.303239, 1.524854, 1.702965, 1.991765, 2.552283",\ + "0.489764, 0.710357, 0.888365, 1.177324, 1.738218",\ + "0.532673, 0.753266, 0.931274, 1.220233, 1.781127",\ + "0.609173, 0.829766, 1.007774, 1.296732, 1.857626",\ + "0.832472, 1.053066, 1.231073, 1.520032, 2.080926",\ + "1.391647, 1.612173, 1.790246, 2.079070, 2.639636",\ + "0.578854, 0.790693, 0.968392, 1.257352, 1.818249",\ + "0.621763, 0.833602, 1.011301, 1.300261, 1.861158",\ + "0.698263, 0.910101, 1.087801, 1.376761, 1.937658",\ + "0.921562, 1.133401, 1.311100, 1.600060, 2.160957",\ + "1.480738, 1.692508, 1.870273, 2.159099, 2.719668",\ + "0.642132, 0.848514, 1.026085, 1.314782, 1.875265",\ + "0.685041, 0.891423, 1.068994, 1.357691, 1.918174",\ + "0.761541, 0.967922, 1.145494, 1.434191, 1.994673",\ + "0.984840, 1.191222, 1.368793, 1.657490, 2.217973",\ + "1.544015, 1.750334, 1.927966, 2.216528, 2.776682",\ + "0.973287, 1.153774, 1.329742, 1.617954, 2.177485",\ + "1.016196, 1.196683, 1.372651, 1.660863, 2.220395",\ + "1.092696, 1.273183, 1.449150, 1.737363, 2.296894",\ + "1.315995, 1.496482, 1.672450, 1.960662, 2.520194",\ + "1.874038, 2.055627, 2.231622, 2.519700, 3.078903"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.048588, 0.048588, 0.048588, 0.048588, 0.048588",\ + "0.136076, 0.136076, 0.136076, 0.136076, 0.136076",\ + "0.314168, 0.314168, 0.314168, 0.314168, 0.314168",\ + "0.833612, 0.833612, 0.833612, 0.833612, 0.833613",\ + "2.135107, 2.135107, 2.135107, 2.135106, 2.135106",\ + "0.048588, 0.048588, 0.048588, 0.048588, 0.048588",\ + "0.136076, 0.136076, 0.136076, 0.136076, 0.136076",\ + "0.314168, 0.314168, 0.314168, 0.314168, 0.314168",\ + "0.833612, 0.833612, 0.833612, 0.833612, 0.833613",\ + "2.135107, 2.135107, 2.135107, 2.135106, 2.135106",\ + "0.048588, 0.048588, 0.048588, 0.048588, 0.048588",\ + "0.136076, 0.136076, 0.136076, 0.136076, 0.136076",\ + "0.314168, 0.314168, 0.314168, 0.314168, 0.314168",\ + "0.833612, 0.833612, 0.833612, 0.833612, 0.833613",\ + "2.135107, 2.135107, 2.135107, 2.135106, 2.135106",\ + "0.048588, 0.048588, 0.048588, 0.048588, 0.048588",\ + "0.136076, 0.136076, 0.136076, 0.136076, 0.136076",\ + "0.314168, 0.314168, 0.314168, 0.314168, 0.314168",\ + "0.833612, 0.833612, 0.833612, 0.833612, 0.833613",\ + "2.135107, 2.135107, 2.135107, 2.135106, 2.135106",\ + "0.048588, 0.048588, 0.048588, 0.048588, 0.048588",\ + "0.136076, 0.136076, 0.136076, 0.136076, 0.136076",\ + "0.314168, 0.314168, 0.314168, 0.314168, 0.314168",\ + "0.833612, 0.833612, 0.833612, 0.833612, 0.833613",\ + "2.135107, 2.135107, 2.135107, 2.135106, 2.135106"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.389319, 0.610934, 0.789045, 1.077845, 1.638363",\ + "0.418979, 0.640595, 0.818706, 1.107506, 1.668024",\ + "0.470920, 0.692535, 0.870646, 1.159446, 1.719964",\ + "0.619380, 0.840995, 1.019106, 1.307906, 1.868424",\ + "0.983284, 1.204968, 1.383013, 1.671947, 2.232793",\ + "0.477727, 0.698253, 0.876326, 1.165150, 1.725716",\ + "0.507388, 0.727914, 0.905987, 1.194811, 1.755377",\ + "0.559328, 0.779854, 0.957927, 1.246751, 1.807317",\ + "0.707788, 0.928314, 1.106387, 1.395211, 1.955777",\ + "1.071693, 1.292286, 1.470294, 1.759253, 2.320147",\ + "0.566817, 0.778588, 0.956353, 1.245178, 1.805748",\ + "0.596478, 0.808249, 0.986014, 1.274839, 1.835409",\ + "0.648419, 0.860189, 1.037954, 1.326780, 1.887349",\ + "0.796878, 1.008649, 1.186414, 1.475240, 2.035809",\ + "1.160783, 1.372622, 1.550321, 1.839281, 2.400178",\ + "0.630095, 0.836414, 1.014046, 1.302608, 1.862762",\ + "0.659756, 0.866074, 1.043707, 1.332269, 1.892423",\ + "0.711696, 0.918015, 1.095647, 1.384209, 1.944364",\ + "0.860156, 1.066475, 1.244107, 1.532669, 2.092824",\ + "1.224061, 1.430443, 1.608014, 1.896711, 2.457193",\ + "0.960117, 1.141707, 1.317702, 1.605780, 2.164983",\ + "0.989778, 1.171368, 1.347363, 1.635441, 2.194643",\ + "1.041718, 1.223308, 1.399303, 1.687381, 2.246584",\ + "1.190178, 1.371768, 1.547763, 1.835841, 2.395044",\ + "1.555216, 1.735703, 1.911671, 2.199883, 2.759414"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.026623, 0.026623, 0.026623, 0.026623, 0.026623",\ + "0.075784, 0.075784, 0.075784, 0.075784, 0.075784",\ + "0.169301, 0.169301, 0.169301, 0.169301, 0.169301",\ + "0.439562, 0.439562, 0.439562, 0.439562, 0.439561",\ + "1.119158, 1.119158, 1.119158, 1.119158, 1.119157",\ + "0.026623, 0.026623, 0.026623, 0.026623, 0.026623",\ + "0.075784, 0.075784, 0.075784, 0.075784, 0.075784",\ + "0.169301, 0.169301, 0.169301, 0.169301, 0.169301",\ + "0.439562, 0.439562, 0.439562, 0.439562, 0.439561",\ + "1.119158, 1.119158, 1.119158, 1.119158, 1.119157",\ + "0.026623, 0.026623, 0.026623, 0.026623, 0.026623",\ + "0.075784, 0.075784, 0.075784, 0.075784, 0.075784",\ + "0.169301, 0.169301, 0.169301, 0.169301, 0.169301",\ + "0.439562, 0.439562, 0.439562, 0.439562, 0.439561",\ + "1.119158, 1.119158, 1.119158, 1.119158, 1.119157",\ + "0.026623, 0.026623, 0.026623, 0.026623, 0.026623",\ + "0.075784, 0.075784, 0.075784, 0.075784, 0.075784",\ + "0.169301, 0.169301, 0.169301, 0.169301, 0.169301",\ + "0.439562, 0.439562, 0.439562, 0.439562, 0.439561",\ + "1.119158, 1.119158, 1.119158, 1.119158, 1.119157",\ + "0.026623, 0.026623, 0.026623, 0.026623, 0.026623",\ + "0.075784, 0.075784, 0.075784, 0.075784, 0.075784",\ + "0.169301, 0.169301, 0.169301, 0.169301, 0.169301",\ + "0.439562, 0.439562, 0.439562, 0.439562, 0.439561",\ + "1.119158, 1.119158, 1.119158, 1.119158, 1.119157"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_min_2497*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[47]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011"); + values ( "0.380051, 0.607077, 0.791540, 1.086441, 1.656420",\ + "0.422960, 0.649986, 0.834449, 1.129350, 1.699329",\ + "0.499459, 0.726486, 0.910949, 1.205850, 1.775828",\ + "0.722759, 0.949785, 1.134248, 1.429149, 1.999128",\ + "1.281942, 1.507667, 1.692145, 1.987100, 2.557201",\ + "0.468382, 0.694395, 0.878821, 1.173746, 1.743773",\ + "0.511291, 0.737304, 0.921730, 1.216655, 1.786682",\ + "0.587791, 0.813804, 0.998230, 1.293155, 1.863182",\ + "0.811090, 1.037103, 1.221529, 1.516454, 2.086481",\ + "1.370273, 1.594985, 1.779426, 2.074405, 2.644555",\ + "0.557789, 0.774725, 0.958848, 1.253775, 1.823805",\ + "0.600698, 0.817634, 1.001757, 1.296684, 1.866714",\ + "0.677198, 0.894134, 1.078257, 1.373183, 1.943213",\ + "0.900497, 1.117434, 1.301556, 1.596483, 2.166513",\ + "1.459679, 1.675315, 1.859452, 2.154434, 2.724586",\ + "0.621599, 0.832548, 1.016557, 1.311216, 1.880844",\ + "0.664508, 0.875457, 1.059467, 1.354125, 1.923753",\ + "0.741007, 0.951957, 1.135966, 1.430625, 2.000253",\ + "0.964307, 1.175256, 1.359266, 1.653924, 2.223552",\ + "1.523487, 1.733139, 1.917162, 2.211875, 2.781626",\ + "0.958721, 1.137805, 1.320215, 1.614397, 2.183095",\ + "1.001630, 1.180714, 1.363124, 1.657306, 2.226004",\ + "1.078130, 1.257213, 1.439624, 1.733806, 2.302503",\ + "1.301429, 1.480513, 1.662923, 1.957105, 2.525803",\ + "1.859271, 2.038396, 2.220819, 2.515056, 3.083877"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011"); + values ( "0.048588, 0.048588, 0.048588, 0.048588, 0.048588",\ + "0.136075, 0.136076, 0.136076, 0.136076, 0.136076",\ + "0.314168, 0.314168, 0.314168, 0.314168, 0.314168",\ + "0.833612, 0.833613, 0.833613, 0.833613, 0.833613",\ + "2.135108, 2.135106, 2.135105, 2.135105, 2.135105",\ + "0.048588, 0.048588, 0.048588, 0.048588, 0.048588",\ + "0.136075, 0.136076, 0.136076, 0.136076, 0.136076",\ + "0.314168, 0.314168, 0.314168, 0.314168, 0.314168",\ + "0.833612, 0.833613, 0.833613, 0.833613, 0.833613",\ + "2.135108, 2.135106, 2.135105, 2.135105, 2.135105",\ + "0.048588, 0.048588, 0.048588, 0.048588, 0.048588",\ + "0.136076, 0.136076, 0.136076, 0.136076, 0.136076",\ + "0.314168, 0.314168, 0.314168, 0.314168, 0.314168",\ + "0.833612, 0.833613, 0.833613, 0.833613, 0.833613",\ + "2.135108, 2.135106, 2.135105, 2.135105, 2.135105",\ + "0.048588, 0.048588, 0.048588, 0.048588, 0.048588",\ + "0.136076, 0.136076, 0.136076, 0.136076, 0.136076",\ + "0.314168, 0.314168, 0.314168, 0.314168, 0.314168",\ + "0.833612, 0.833613, 0.833613, 0.833613, 0.833613",\ + "2.135108, 2.135106, 2.135105, 2.135105, 2.135105",\ + "0.048588, 0.048588, 0.048588, 0.048588, 0.048588",\ + "0.136076, 0.136076, 0.136076, 0.136076, 0.136076",\ + "0.314168, 0.314168, 0.314168, 0.314168, 0.314168",\ + "0.833612, 0.833613, 0.833613, 0.833613, 0.833613",\ + "2.135108, 2.135106, 2.135105, 2.135105, 2.135105"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011"); + values ( "0.368022, 0.593747, 0.778225, 1.073180, 1.643281",\ + "0.397682, 0.623408, 0.807886, 1.102841, 1.672942",\ + "0.449623, 0.675348, 0.859826, 1.154781, 1.724883",\ + "0.598083, 0.823808, 1.008286, 1.303241, 1.873343",\ + "0.961980, 1.189006, 1.373469, 1.668370, 2.238349",\ + "0.456353, 0.681065, 0.865506, 1.160485, 1.730635",\ + "0.486014, 0.710726, 0.895167, 1.190146, 1.760296",\ + "0.537954, 0.762666, 0.947107, 1.242086, 1.812236",\ + "0.686414, 0.911126, 1.095567, 1.390546, 1.960696",\ + "1.050311, 1.276324, 1.460750, 1.755675, 2.325702",\ + "0.545759, 0.761395, 0.945533, 1.240514, 1.810667",\ + "0.575419, 0.791056, 0.975194, 1.270175, 1.840328",\ + "0.627360, 0.842997, 1.027134, 1.322115, 1.892268",\ + "0.775819, 0.991457, 1.175594, 1.470575, 2.040728",\ + "1.139718, 1.356654, 1.540777, 1.835704, 2.405734",\ + "0.609567, 0.819218, 1.003242, 1.297955, 1.867706",\ + "0.639228, 0.848879, 1.032903, 1.327616, 1.897367",\ + "0.691168, 0.900820, 1.084843, 1.379556, 1.949308",\ + "0.839628, 1.049280, 1.233303, 1.528016, 2.097767",\ + "1.203528, 1.414477, 1.598486, 1.893145, 2.462773",\ + "0.945351, 1.124476, 1.306899, 1.601136, 2.169957",\ + "0.975012, 1.154137, 1.336560, 1.630797, 2.199618",\ + "1.026952, 1.206077, 1.388500, 1.682738, 2.251558",\ + "1.175412, 1.354537, 1.536960, 1.831198, 2.400018",\ + "1.540650, 1.719733, 1.902144, 2.196326, 2.765023"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011"); + values ( "0.026623, 0.026623, 0.026623, 0.026623, 0.026623",\ + "0.075784, 0.075784, 0.075784, 0.075784, 0.075784",\ + "0.169301, 0.169301, 0.169301, 0.169301, 0.169301",\ + "0.439562, 0.439562, 0.439561, 0.439561, 0.439561",\ + "1.119159, 1.119158, 1.119157, 1.119157, 1.119157",\ + "0.026623, 0.026623, 0.026623, 0.026623, 0.026623",\ + "0.075784, 0.075784, 0.075784, 0.075784, 0.075784",\ + "0.169301, 0.169301, 0.169301, 0.169301, 0.169301",\ + "0.439562, 0.439562, 0.439561, 0.439561, 0.439561",\ + "1.119159, 1.119158, 1.119157, 1.119157, 1.119157",\ + "0.026623, 0.026623, 0.026623, 0.026623, 0.026623",\ + "0.075784, 0.075784, 0.075784, 0.075784, 0.075784",\ + "0.169301, 0.169301, 0.169301, 0.169301, 0.169301",\ + "0.439562, 0.439562, 0.439561, 0.439561, 0.439561",\ + "1.119159, 1.119158, 1.119157, 1.119157, 1.119157",\ + "0.026623, 0.026623, 0.026623, 0.026623, 0.026623",\ + "0.075784, 0.075784, 0.075784, 0.075784, 0.075784",\ + "0.169301, 0.169301, 0.169301, 0.169301, 0.169301",\ + "0.439562, 0.439562, 0.439561, 0.439561, 0.439561",\ + "1.119159, 1.119158, 1.119157, 1.119157, 1.119157",\ + "0.026623, 0.026623, 0.026623, 0.026623, 0.026623",\ + "0.075784, 0.075784, 0.075784, 0.075784, 0.075784",\ + "0.169301, 0.169301, 0.169301, 0.169301, 0.169301",\ + "0.439562, 0.439562, 0.439561, 0.439561, 0.439561",\ + "1.119159, 1.119157, 1.119157, 1.119157, 1.119157"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_min_2420*/ + +} /* end of pin tl_o[3] */ + +pin("tl_o[2]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.020161 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : tl_o[2]; + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[16]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011"); + values ( "0.596162, 0.867359, 1.159405, 1.656731, 2.651384",\ + "0.643260, 0.914475, 1.206618, 1.704208, 2.699388",\ + "0.730525, 1.001791, 1.294214, 1.792557, 2.789245",\ + "0.956361, 1.227706, 1.520560, 2.020066, 3.019080",\ + "1.523589, 1.795036, 2.088453, 2.589476, 3.591523",\ + "0.683575, 0.954952, 1.247062, 1.743446, 2.737318",\ + "0.730672, 1.002068, 1.294276, 1.790923, 2.785322",\ + "0.817938, 1.089384, 1.381874, 1.879272, 2.875178",\ + "1.043774, 1.315300, 1.608224, 2.106781, 3.105014",\ + "1.611001, 1.882631, 2.176121, 2.676191, 3.677457",\ + "0.766406, 1.044042, 1.335028, 1.831069, 2.824273",\ + "0.813504, 1.091158, 1.382242, 1.878545, 2.872277",\ + "0.900771, 1.178475, 1.469840, 1.966895, 2.962133",\ + "1.126608, 1.404392, 1.696190, 2.194404, 3.191969",\ + "1.693838, 1.971725, 2.264088, 2.763813, 3.764412",\ + "0.829815, 1.109836, 1.399173, 1.894982, 2.887782",\ + "0.876913, 1.156952, 1.446387, 1.942459, 2.935786",\ + "0.964180, 1.244271, 1.533985, 2.030808, 3.025642",\ + "1.190018, 1.470190, 1.760335, 2.258317, 3.255478",\ + "1.757249, 2.037525, 2.328233, 2.827727, 3.827921",\ + "1.164720, 1.476052, 1.751329, 2.244448, 3.233238",\ + "1.211820, 1.523174, 1.798545, 2.291926, 3.281242",\ + "1.299091, 1.610508, 1.886151, 2.380279, 3.371099",\ + "1.524935, 1.836451, 2.112513, 2.607793, 3.600934",\ + "2.092175, 2.403818, 2.680427, 3.177208, 4.173377"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011"); + values ( "0.053862, 0.053914, 0.054909, 0.058152, 0.064638",\ + "0.173267, 0.173231, 0.173035, 0.172508, 0.171453",\ + "0.375460, 0.375376, 0.374957, 0.373858, 0.371660",\ + "0.885481, 0.885445, 0.885292, 0.884908, 0.884140",\ + "2.163051, 2.163105, 2.163316, 2.163829, 2.164857",\ + "0.053862, 0.053914, 0.054919, 0.058152, 0.064638",\ + "0.173267, 0.173231, 0.173034, 0.172508, 0.171453",\ + "0.375460, 0.375376, 0.374953, 0.373858, 0.371660",\ + "0.885481, 0.885444, 0.885291, 0.884908, 0.884140",\ + "2.163051, 2.163105, 2.163317, 2.163829, 2.164857",\ + "0.053863, 0.053915, 0.054919, 0.058152, 0.064638",\ + "0.173266, 0.173230, 0.173034, 0.172508, 0.171453",\ + "0.375459, 0.375374, 0.374953, 0.373858, 0.371660",\ + "0.885480, 0.885444, 0.885290, 0.884908, 0.884140",\ + "2.163052, 2.163106, 2.163317, 2.163829, 2.164857",\ + "0.053864, 0.053916, 0.054920, 0.058152, 0.064638",\ + "0.173266, 0.173229, 0.173034, 0.172508, 0.171453",\ + "0.375457, 0.375372, 0.374953, 0.373858, 0.371660",\ + "0.885480, 0.885443, 0.885290, 0.884908, 0.884140",\ + "2.163053, 2.163108, 2.163317, 2.163829, 2.164857",\ + "0.053868, 0.053932, 0.054952, 0.058165, 0.064638",\ + "0.173263, 0.173218, 0.173028, 0.172506, 0.171453",\ + "0.375451, 0.375346, 0.374942, 0.373853, 0.371660",\ + "0.885476, 0.885432, 0.885287, 0.884906, 0.884140",\ + "2.163059, 2.163123, 2.163322, 2.163831, 2.164857"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011"); + values ( "0.526597, 0.797546, 1.089766, 1.588771, 2.586781",\ + "0.587519, 0.858706, 1.150697, 1.647877, 2.642235",\ + "0.654254, 0.925628, 1.218645, 1.718590, 2.718481",\ + "0.788462, 1.059820, 1.352751, 1.852464, 2.851889",\ + "1.131923, 1.403187, 1.695595, 2.193900, 3.190510",\ + "0.614010, 0.885137, 1.177429, 1.675486, 2.672715",\ + "0.674932, 0.946299, 1.238354, 1.734592, 2.728169",\ + "0.741667, 1.013223, 1.306311, 1.805305, 2.804415",\ + "0.875874, 1.147414, 1.440416, 1.939178, 2.937823",\ + "1.219336, 1.490780, 1.783256, 2.280615, 3.276443",\ + "0.696837, 0.974222, 1.265395, 1.763108, 2.759670",\ + "0.757763, 1.035389, 1.326320, 1.822214, 2.815124",\ + "0.824502, 1.102316, 1.394277, 1.892928, 2.891370",\ + "0.958709, 1.236507, 1.528382, 2.026801, 3.024778",\ + "1.302169, 1.579871, 1.871222, 2.368237, 3.363399",\ + "0.760242, 1.040009, 1.329540, 1.827022, 2.823179",\ + "0.821171, 1.101182, 1.390465, 1.886127, 2.878633",\ + "0.887912, 1.168114, 1.458422, 1.956841, 2.954879",\ + "1.022119, 1.302305, 1.592527, 2.090714, 3.088287",\ + "1.365578, 1.645666, 1.935366, 2.432151, 3.426908",\ + "1.095129, 1.406150, 1.681713, 2.176495, 3.168635",\ + "1.156076, 1.467395, 1.742619, 2.235593, 3.224089",\ + "1.222832, 1.534384, 1.810604, 2.306318, 3.300335",\ + "1.357038, 1.668570, 1.944707, 2.440191, 3.433743",\ + "1.700489, 2.011903, 2.287532, 2.781621, 3.772364"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011"); + values ( "0.071571, 0.071932, 0.073911, 0.079246, 0.089916",\ + "0.129642, 0.130131, 0.132813, 0.140046, 0.154511",\ + "0.213984, 0.214431, 0.216880, 0.223483, 0.236689",\ + "0.447086, 0.447136, 0.447410, 0.448149, 0.449626",\ + "1.100696, 1.100673, 1.100546, 1.100205, 1.099521",\ + "0.071571, 0.071935, 0.073927, 0.079246, 0.089916",\ + "0.129642, 0.130135, 0.132836, 0.140046, 0.154511",\ + "0.213984, 0.214435, 0.216901, 0.223483, 0.236689",\ + "0.447086, 0.447137, 0.447412, 0.448149, 0.449626",\ + "1.100696, 1.100673, 1.100545, 1.100205, 1.099521",\ + "0.071578, 0.071942, 0.073928, 0.079246, 0.089916",\ + "0.129651, 0.130144, 0.132837, 0.140046, 0.154511",\ + "0.213993, 0.214443, 0.216901, 0.223483, 0.236689",\ + "0.447087, 0.447137, 0.447412, 0.448149, 0.449626",\ + "1.100696, 1.100673, 1.100545, 1.100205, 1.099521",\ + "0.071582, 0.071951, 0.073929, 0.079246, 0.089916",\ + "0.129657, 0.130157, 0.132838, 0.140046, 0.154511",\ + "0.213998, 0.214454, 0.216902, 0.223483, 0.236689",\ + "0.447088, 0.447139, 0.447413, 0.448149, 0.449626",\ + "1.100696, 1.100672, 1.100545, 1.100205, 1.099521",\ + "0.071611, 0.072061, 0.073983, 0.079268, 0.089916",\ + "0.129696, 0.130306, 0.132911, 0.140076, 0.154511",\ + "0.214033, 0.214590, 0.216969, 0.223510, 0.236689",\ + "0.447092, 0.447154, 0.447420, 0.448152, 0.449626",\ + "1.100694, 1.100665, 1.100542, 1.100203, 1.099521"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_2642*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[18]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.620483, 0.875327, 1.158797, 1.657448, 2.654750",\ + "0.666691, 0.921535, 1.205006, 1.703663, 2.700977",\ + "0.750941, 1.005785, 1.289255, 1.787906, 2.785209",\ + "0.971936, 1.226783, 1.510836, 2.011498, 3.012820",\ + "1.532384, 1.787236, 2.072631, 2.577909, 3.588464",\ + "0.707891, 0.962871, 1.246456, 1.744162, 2.740684",\ + "0.754100, 1.009078, 1.292665, 1.790377, 2.786911",\ + "0.838350, 1.093329, 1.376915, 1.874621, 2.871142",\ + "1.059345, 1.314327, 1.598502, 2.098212, 3.098754",\ + "1.619793, 1.874780, 2.160311, 2.664623, 3.674398",\ + "0.788766, 1.051830, 1.334422, 1.831784, 2.827639",\ + "0.834975, 1.098037, 1.380631, 1.877999, 2.873866",\ + "0.919225, 1.182288, 1.464880, 1.962242, 2.958097",\ + "1.140220, 1.403286, 1.686468, 2.185834, 3.185709",\ + "1.700668, 1.963739, 2.248277, 2.752245, 3.761353",\ + "0.848948, 1.117433, 1.398566, 1.895697, 2.891148",\ + "0.895156, 1.163640, 1.444775, 1.941912, 2.937375",\ + "0.979406, 1.247891, 1.529024, 2.026155, 3.021606",\ + "1.200402, 1.468889, 1.750613, 2.249747, 3.249218",\ + "1.760850, 2.029342, 2.312423, 2.816158, 3.824862",\ + "1.183848, 1.481469, 1.750734, 2.245165, 3.236604",\ + "1.230056, 1.527677, 1.796943, 2.291380, 3.282831",\ + "1.314306, 1.611928, 1.881192, 2.375623, 3.367063",\ + "1.535303, 1.832926, 2.102801, 2.599223, 3.594674",\ + "2.095753, 2.393380, 2.664657, 3.165653, 4.170318"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.052746, 0.052746, 0.052770, 0.052852, 0.053015",\ + "0.178338, 0.178338, 0.178378, 0.178516, 0.178792",\ + "0.381631, 0.381631, 0.381650, 0.381714, 0.381841",\ + "0.885930, 0.885935, 0.885937, 0.885937, 0.885937",\ + "2.162390, 2.162390, 2.162427, 2.162551, 2.162801",\ + "0.052746, 0.052746, 0.052770, 0.052852, 0.053015",\ + "0.178338, 0.178338, 0.178378, 0.178516, 0.178792",\ + "0.381631, 0.381631, 0.381650, 0.381714, 0.381841",\ + "0.885930, 0.885935, 0.885937, 0.885937, 0.885937",\ + "2.162390, 2.162390, 2.162427, 2.162551, 2.162801",\ + "0.052746, 0.052746, 0.052770, 0.052852, 0.053015",\ + "0.178338, 0.178338, 0.178378, 0.178516, 0.178792",\ + "0.381631, 0.381631, 0.381650, 0.381714, 0.381841",\ + "0.885930, 0.885935, 0.885937, 0.885937, 0.885937",\ + "2.162390, 2.162390, 2.162427, 2.162551, 2.162801",\ + "0.052746, 0.052746, 0.052770, 0.052852, 0.053015",\ + "0.178338, 0.178338, 0.178378, 0.178516, 0.178792",\ + "0.381631, 0.381631, 0.381650, 0.381714, 0.381841",\ + "0.885931, 0.885935, 0.885937, 0.885937, 0.885937",\ + "2.162390, 2.162390, 2.162427, 2.162551, 2.162801",\ + "0.052746, 0.052746, 0.052771, 0.052852, 0.053015",\ + "0.178338, 0.178338, 0.178380, 0.178516, 0.178792",\ + "0.381631, 0.381631, 0.381651, 0.381714, 0.381841",\ + "0.885932, 0.885936, 0.885937, 0.885937, 0.885937",\ + "2.162390, 2.162390, 2.162428, 2.162552, 2.162801"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.568910, 0.823730, 1.112547, 1.629674, 2.663928",\ + "0.612218, 0.867064, 1.154057, 1.664859, 2.686463",\ + "0.668015, 0.922863, 1.208574, 1.714952, 2.727708",\ + "0.803644, 1.058488, 1.343000, 1.845245, 2.849735",\ + "1.152943, 1.407785, 1.691260, 2.189933, 3.187279",\ + "0.656319, 0.911274, 1.200265, 1.716388, 2.749862",\ + "0.699627, 0.954607, 1.241755, 1.751573, 2.772397",\ + "0.755424, 1.010406, 1.296258, 1.801666, 2.813642",\ + "0.891053, 1.146032, 1.430671, 1.931960, 2.935669",\ + "1.240352, 1.495328, 1.778919, 2.276647, 3.273213",\ + "0.737194, 1.000233, 1.288231, 1.804010, 2.836817",\ + "0.780502, 1.043566, 1.329721, 1.839195, 2.859352",\ + "0.836299, 1.099365, 1.384223, 1.889288, 2.900597",\ + "0.971928, 1.234991, 1.518637, 2.019581, 3.022624",\ + "1.321227, 1.584288, 1.866885, 2.364269, 3.360168",\ + "0.797372, 1.065835, 1.352379, 1.867923, 2.900326",\ + "0.840683, 1.109169, 1.393867, 1.903108, 2.922861",\ + "0.896481, 1.164968, 1.448369, 1.953201, 2.964106",\ + "1.032109, 1.300594, 1.582782, 2.083494, 3.086133",\ + "1.381408, 1.649890, 1.931029, 2.428182, 3.423677",\ + "1.132264, 1.429870, 1.704734, 2.217468, 3.245782",\ + "1.175584, 1.473206, 1.746158, 2.252626, 3.268317",\ + "1.231382, 1.529005, 1.800615, 2.302701, 3.309562",\ + "1.367010, 1.664631, 1.934986, 2.432977, 3.431589",\ + "1.716307, 2.013927, 2.283197, 2.777650, 3.769133"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.046309, 0.046309, 0.046284, 0.046200, 0.046032",\ + "0.096054, 0.096054, 0.095973, 0.095695, 0.095137",\ + "0.188958, 0.188958, 0.188958, 0.188958, 0.188958",\ + "0.444028, 0.444028, 0.444025, 0.444014, 0.443993",\ + "1.101657, 1.101657, 1.101653, 1.101637, 1.101605",\ + "0.046309, 0.046309, 0.046284, 0.046200, 0.046032",\ + "0.096054, 0.096054, 0.095972, 0.095695, 0.095137",\ + "0.188958, 0.188958, 0.188958, 0.188958, 0.188958",\ + "0.444028, 0.444028, 0.444025, 0.444014, 0.443993",\ + "1.101657, 1.101657, 1.101653, 1.101637, 1.101605",\ + "0.046309, 0.046309, 0.046284, 0.046200, 0.046032",\ + "0.096054, 0.096054, 0.095972, 0.095695, 0.095137",\ + "0.188958, 0.188958, 0.188958, 0.188958, 0.188958",\ + "0.444028, 0.444028, 0.444025, 0.444014, 0.443993",\ + "1.101657, 1.101657, 1.101653, 1.101637, 1.101605",\ + "0.046309, 0.046309, 0.046284, 0.046200, 0.046032",\ + "0.096054, 0.096054, 0.095972, 0.095695, 0.095137",\ + "0.188958, 0.188958, 0.188958, 0.188958, 0.188958",\ + "0.444028, 0.444028, 0.444025, 0.444014, 0.443993",\ + "1.101657, 1.101657, 1.101653, 1.101637, 1.101605",\ + "0.046309, 0.046309, 0.046283, 0.046200, 0.046032",\ + "0.096054, 0.096054, 0.095970, 0.095693, 0.095137",\ + "0.188958, 0.188958, 0.188958, 0.188958, 0.188958",\ + "0.444028, 0.444028, 0.444025, 0.444014, 0.443993",\ + "1.101657, 1.101657, 1.101653, 1.101637, 1.101605"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_2640*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[21]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011"); + values ( "0.197465, 0.431884, 0.691143, 1.132576, 2.015443",\ + "0.256904, 0.482244, 0.742878, 1.186420, 2.073503",\ + "0.340726, 0.558560, 0.820216, 1.263968, 2.151470",\ + "0.552743, 0.766273, 1.030363, 1.473596, 2.360062",\ + "1.106694, 1.318615, 1.585993, 2.032644, 2.925946",\ + "0.284867, 0.519390, 0.778620, 1.219289, 2.101377",\ + "0.344307, 0.569755, 0.830361, 1.273133, 2.159437",\ + "0.428128, 0.646078, 0.907700, 1.350681, 2.237404",\ + "0.640145, 0.853808, 1.117845, 1.560309, 2.445995",\ + "1.194097, 1.406166, 1.673486, 2.119357, 3.011879",\ + "0.365670, 0.608240, 0.866580, 1.306910, 2.188332",\ + "0.425121, 0.658616, 0.918322, 1.360754, 2.246392",\ + "0.508950, 0.734952, 0.995661, 1.438301, 2.324359",\ + "0.720977, 0.942721, 1.205806, 1.647930, 2.532950",\ + "1.274933, 1.495112, 1.761447, 2.206978, 3.098835",\ + "0.423291, 0.673682, 0.930715, 1.370823, 2.251841",\ + "0.482765, 0.724074, 0.982457, 1.424666, 2.309901",\ + "0.566610, 0.800431, 1.059796, 1.502214, 2.387868",\ + "0.778657, 1.008255, 1.269941, 1.711842, 2.596459",\ + "1.332621, 1.560694, 1.825583, 2.270890, 3.162344",\ + "0.752280, 1.035917, 1.282299, 1.720049, 2.597297",\ + "0.801700, 1.086498, 1.334062, 1.773901, 2.655357",\ + "0.877280, 1.163095, 1.411404, 1.851450, 2.733324",\ + "1.083334, 1.371566, 1.621543, 2.061076, 2.941916",\ + "1.635803, 1.924576, 2.177220, 2.620138, 3.507800"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011"); + values ( "0.177313, 0.213506, 0.303388, 0.457575, 0.765950",\ + "0.250045, 0.279683, 0.356813, 0.520203, 0.846983",\ + "0.414563, 0.415723, 0.459642, 0.603351, 0.890769",\ + "0.887841, 0.887858, 0.923884, 1.046147, 1.290675",\ + "2.163213, 2.163213, 2.177271, 2.225014, 2.320500",\ + "0.177313, 0.213805, 0.303871, 0.457575, 0.765950",\ + "0.250045, 0.279878, 0.357325, 0.520203, 0.846983",\ + "0.414563, 0.415734, 0.460093, 0.603351, 0.890769",\ + "0.887841, 0.887859, 0.924267, 1.046147, 1.290675",\ + "2.163213, 2.163213, 2.177421, 2.225014, 2.320500",\ + "0.177336, 0.214457, 0.303880, 0.457575, 0.765950",\ + "0.250094, 0.280303, 0.357335, 0.520203, 0.846983",\ + "0.414563, 0.415757, 0.460101, 0.603351, 0.890769",\ + "0.887841, 0.887859, 0.924274, 1.046147, 1.290675",\ + "2.163213, 2.163213, 2.177424, 2.225014, 2.320500",\ + "0.177382, 0.215405, 0.303907, 0.457575, 0.765950",\ + "0.250194, 0.280922, 0.357363, 0.520203, 0.846983",\ + "0.414563, 0.415792, 0.460126, 0.603351, 0.890769",\ + "0.887841, 0.887859, 0.924295, 1.046147, 1.290675",\ + "2.163213, 2.163213, 2.177432, 2.225014, 2.320500",\ + "0.179823, 0.226531, 0.305470, 0.458210, 0.765950",\ + "0.255480, 0.288180, 0.359019, 0.520875, 0.846983",\ + "0.414563, 0.416192, 0.461583, 0.603943, 0.890769",\ + "0.887841, 0.887865, 0.925535, 1.046651, 1.290675",\ + "2.163213, 2.163213, 2.177916, 2.225211, 2.320500"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011"); + values ( "0.186444, 0.372257, 0.626401, 1.055911, 1.914929",\ + "0.215837, 0.420150, 0.691942, 1.154794, 2.080498",\ + "0.262380, 0.480818, 0.763209, 1.249238, 2.221297",\ + "0.391146, 0.611553, 0.905194, 1.430347, 2.480653",\ + "0.735395, 0.947247, 1.249008, 1.808760, 2.928262",\ + "0.273847, 0.459753, 0.713841, 1.142624, 2.000862",\ + "0.303239, 0.507698, 0.779487, 1.241508, 2.166432",\ + "0.349783, 0.568392, 0.850825, 1.335951, 2.307231",\ + "0.478548, 0.699125, 0.992933, 1.517060, 2.566586",\ + "0.822797, 1.034805, 1.336856, 1.895473, 3.014196",\ + "0.354708, 0.548579, 0.801801, 1.230244, 2.087817",\ + "0.384100, 0.596639, 0.867448, 1.329128, 2.253387",\ + "0.430643, 0.657388, 0.938789, 1.423572, 2.394186",\ + "0.559400, 0.788117, 1.080899, 1.604681, 2.653542",\ + "0.903640, 1.123767, 1.424824, 1.983094, 3.101151",\ + "0.412447, 0.613987, 0.865934, 1.294157, 2.151326",\ + "0.441838, 0.662214, 0.931587, 1.393041, 2.316896",\ + "0.488379, 0.723043, 1.002931, 1.487485, 2.457695",\ + "0.617120, 0.853767, 1.145048, 1.668593, 2.717051",\ + "0.961342, 1.189372, 1.488979, 2.047006, 3.164660",\ + "0.716098, 0.975821, 1.217396, 1.643334, 2.496783",\ + "0.745485, 1.026006, 1.283388, 1.742355, 2.662352",\ + "0.795750, 1.087780, 1.354967, 1.836895, 2.803151",\ + "0.926660, 1.218436, 1.497480, 2.018165, 3.062507",\ + "1.264652, 1.553524, 1.841762, 2.396720, 3.510116"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011"); + values ( "0.071183, 0.106877, 0.175281, 0.296416, 0.538687",\ + "0.120882, 0.144932, 0.213033, 0.350090, 0.624205",\ + "0.200934, 0.210788, 0.256182, 0.378836, 0.624145",\ + "0.444935, 0.444935, 0.478349, 0.591825, 0.818777",\ + "1.101088, 1.102468, 1.122488, 1.190477, 1.326455",\ + "0.071183, 0.107097, 0.175661, 0.296416, 0.538687",\ + "0.120882, 0.145118, 0.213463, 0.350090, 0.624205",\ + "0.200934, 0.210850, 0.256566, 0.378836, 0.624145",\ + "0.444935, 0.444935, 0.478705, 0.591825, 0.818777",\ + "1.101088, 1.102468, 1.122701, 1.190477, 1.326455",\ + "0.071251, 0.107578, 0.175668, 0.296416, 0.538687",\ + "0.120905, 0.145525, 0.213471, 0.350090, 0.624205",\ + "0.200952, 0.210986, 0.256574, 0.378836, 0.624145",\ + "0.444935, 0.444935, 0.478711, 0.591825, 0.818777",\ + "1.101096, 1.102468, 1.122705, 1.190477, 1.326455",\ + "0.071390, 0.108275, 0.175689, 0.296416, 0.538687",\ + "0.120951, 0.146116, 0.213494, 0.350090, 0.624205",\ + "0.200988, 0.211184, 0.256595, 0.378836, 0.624145",\ + "0.444935, 0.444935, 0.478731, 0.591825, 0.818777",\ + "1.101112, 1.102468, 1.122717, 1.190477, 1.326455",\ + "0.072681, 0.116463, 0.176917, 0.296915, 0.538687",\ + "0.121377, 0.153056, 0.214884, 0.350655, 0.624205",\ + "0.202910, 0.213504, 0.257838, 0.379341, 0.624145",\ + "0.444935, 0.444935, 0.479881, 0.592292, 0.818777",\ + "1.101261, 1.102468, 1.123406, 1.190757, 1.326455"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_2293*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[24]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011"); + values ( "0.606811, 0.855240, 1.131420, 1.600406, 2.538379",\ + "0.653020, 0.901448, 1.177629, 1.646621, 2.584605",\ + "0.737270, 0.985698, 1.261878, 1.730864, 2.668837",\ + "0.958264, 1.206694, 1.482871, 1.951840, 2.889778",\ + "1.518707, 1.767142, 2.043312, 2.512236, 3.450085",\ + "0.694214, 0.942805, 1.218983, 1.687119, 2.624312",\ + "0.740423, 0.989013, 1.265193, 1.733334, 2.670539",\ + "0.824672, 1.073263, 1.349441, 1.817578, 2.754771",\ + "1.045666, 1.294259, 1.570434, 2.038553, 2.975712",\ + "1.606110, 1.854707, 2.130875, 2.598950, 3.536019",\ + "0.775027, 1.031783, 1.306946, 1.774740, 2.711267",\ + "0.821236, 1.077992, 1.353155, 1.820955, 2.757494",\ + "0.905485, 1.162242, 1.437404, 1.905199, 2.841726",\ + "1.126479, 1.383237, 1.658397, 2.126174, 3.062667",\ + "1.686923, 1.943686, 2.218838, 2.686570, 3.622974",\ + "0.832667, 1.097413, 1.371085, 1.838653, 2.774776",\ + "0.878876, 1.143622, 1.417294, 1.884868, 2.821003",\ + "0.963125, 1.227872, 1.501543, 1.969111, 2.905235",\ + "1.184119, 1.448868, 1.722536, 2.190087, 3.126176",\ + "1.744563, 2.009316, 2.282977, 2.750483, 3.686483",\ + "1.167769, 1.461851, 1.722948, 2.187993, 3.120233",\ + "1.213978, 1.508059, 1.769157, 2.234208, 3.166459",\ + "1.298227, 1.592309, 1.853406, 2.318451, 3.250691",\ + "1.519221, 1.813305, 2.074399, 2.539426, 3.471632",\ + "2.079665, 2.373755, 2.634840, 3.099823, 4.031939"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011"); + values ( "0.052753, 0.052753, 0.052776, 0.052854, 0.053011",\ + "0.178350, 0.178350, 0.178389, 0.178521, 0.178785",\ + "0.381637, 0.381637, 0.381655, 0.381716, 0.381838",\ + "0.885927, 0.885931, 0.885936, 0.885936, 0.885936",\ + "2.162395, 2.162395, 2.162430, 2.162547, 2.162780",\ + "0.052753, 0.052753, 0.052777, 0.052854, 0.053011",\ + "0.178350, 0.178350, 0.178389, 0.178521, 0.178785",\ + "0.381637, 0.381637, 0.381655, 0.381716, 0.381838",\ + "0.885927, 0.885931, 0.885936, 0.885936, 0.885936",\ + "2.162395, 2.162395, 2.162430, 2.162547, 2.162780",\ + "0.052753, 0.052753, 0.052777, 0.052854, 0.053011",\ + "0.178350, 0.178350, 0.178389, 0.178521, 0.178785",\ + "0.381637, 0.381637, 0.381655, 0.381716, 0.381838",\ + "0.885927, 0.885931, 0.885936, 0.885936, 0.885936",\ + "2.162395, 2.162395, 2.162430, 2.162547, 2.162780",\ + "0.052753, 0.052753, 0.052777, 0.052854, 0.053011",\ + "0.178350, 0.178350, 0.178389, 0.178521, 0.178785",\ + "0.381637, 0.381637, 0.381655, 0.381716, 0.381838",\ + "0.885927, 0.885931, 0.885936, 0.885936, 0.885936",\ + "2.162395, 2.162395, 2.162430, 2.162547, 2.162780",\ + "0.052753, 0.052753, 0.052777, 0.052855, 0.053011",\ + "0.178350, 0.178350, 0.178390, 0.178521, 0.178785",\ + "0.381637, 0.381637, 0.381656, 0.381716, 0.381838",\ + "0.885927, 0.885932, 0.885936, 0.885936, 0.885936",\ + "2.162395, 2.162395, 2.162431, 2.162547, 2.162780"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011"); + values ( "0.555254, 0.803664, 1.079873, 1.549041, 2.487376",\ + "0.598546, 0.846975, 1.123154, 1.592132, 2.530087",\ + "0.654342, 0.902772, 1.178949, 1.647912, 2.585838",\ + "0.789973, 1.038401, 1.314582, 1.783569, 2.721544",\ + "1.139274, 1.387700, 1.663883, 2.132891, 3.070906",\ + "0.642657, 0.891229, 1.167437, 1.635754, 2.573310",\ + "0.685949, 0.934540, 1.210717, 1.678845, 2.616020",\ + "0.741745, 0.990338, 1.266512, 1.734625, 2.671772",\ + "0.877376, 1.125967, 1.402145, 1.870283, 2.807478",\ + "1.226676, 1.475265, 1.751447, 2.219604, 3.156840",\ + "0.723469, 0.980207, 1.255399, 1.723375, 2.660265",\ + "0.766762, 1.023519, 1.298680, 1.766466, 2.702976",\ + "0.822557, 1.079316, 1.354475, 1.822246, 2.758727",\ + "0.958189, 1.214945, 1.490107, 1.957903, 2.894433",\ + "1.307489, 1.564244, 1.839409, 2.307225, 3.243795",\ + "0.781109, 1.045837, 1.319539, 1.787287, 2.723774",\ + "0.824402, 1.089149, 1.362819, 1.830378, 2.766484",\ + "0.880198, 1.144946, 1.418614, 1.886158, 2.822236",\ + "1.015829, 1.280575, 1.554247, 2.021816, 2.957942",\ + "1.365129, 1.629874, 1.903549, 2.371138, 3.307304",\ + "1.116211, 1.410268, 1.671404, 2.136628, 3.069230",\ + "1.159504, 1.453587, 1.714682, 2.179718, 3.111940",\ + "1.215299, 1.509384, 1.770477, 2.235498, 3.167692",\ + "1.350931, 1.645012, 1.906110, 2.371156, 3.303398",\ + "1.700231, 1.994310, 2.255412, 2.720478, 3.652760"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011"); + values ( "0.046307, 0.046307, 0.046284, 0.046204, 0.046045",\ + "0.096045, 0.096045, 0.095965, 0.095693, 0.095150",\ + "0.188958, 0.188958, 0.188958, 0.188958, 0.188958",\ + "0.444028, 0.444028, 0.444025, 0.444014, 0.443994",\ + "1.101656, 1.101656, 1.101651, 1.101636, 1.101606",\ + "0.046307, 0.046307, 0.046284, 0.046204, 0.046045",\ + "0.096045, 0.096045, 0.095964, 0.095693, 0.095150",\ + "0.188958, 0.188958, 0.188958, 0.188958, 0.188958",\ + "0.444028, 0.444028, 0.444025, 0.444014, 0.443994",\ + "1.101656, 1.101656, 1.101651, 1.101636, 1.101606",\ + "0.046307, 0.046307, 0.046284, 0.046204, 0.046045",\ + "0.096045, 0.096045, 0.095964, 0.095693, 0.095150",\ + "0.188958, 0.188958, 0.188958, 0.188958, 0.188958",\ + "0.444028, 0.444028, 0.444025, 0.444014, 0.443994",\ + "1.101656, 1.101656, 1.101651, 1.101636, 1.101606",\ + "0.046307, 0.046307, 0.046284, 0.046204, 0.046045",\ + "0.096045, 0.096045, 0.095964, 0.095693, 0.095150",\ + "0.188958, 0.188958, 0.188958, 0.188958, 0.188958",\ + "0.444028, 0.444028, 0.444025, 0.444014, 0.443994",\ + "1.101656, 1.101656, 1.101651, 1.101636, 1.101606",\ + "0.046307, 0.046307, 0.046283, 0.046204, 0.046045",\ + "0.096045, 0.096045, 0.095961, 0.095692, 0.095150",\ + "0.188958, 0.188958, 0.188958, 0.188958, 0.188958",\ + "0.444028, 0.444028, 0.444025, 0.444014, 0.443994",\ + "1.101656, 1.101656, 1.101651, 1.101636, 1.101606"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_2451*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[26]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011"); + values ( "0.574242, 0.825673, 1.106128, 1.575345, 2.513779",\ + "0.621341, 0.872791, 1.153329, 1.622748, 2.561586",\ + "0.708610, 0.960115, 1.240890, 1.710886, 2.650879",\ + "0.934451, 1.186041, 1.467182, 1.938070, 2.879846",\ + "1.501685, 1.753387, 2.035005, 2.507055, 3.451155",\ + "0.661652, 0.913251, 1.193695, 1.662059, 2.599712",\ + "0.708750, 0.960370, 1.240897, 1.709462, 2.647520",\ + "0.796019, 1.047694, 1.328459, 1.797601, 2.736813",\ + "1.021860, 1.273621, 1.554754, 2.024784, 2.965779",\ + "1.589094, 1.840967, 2.122581, 2.593769, 3.537089",\ + "0.742484, 1.002291, 1.281659, 1.749681, 2.686667",\ + "0.789583, 1.049409, 1.328861, 1.797084, 2.734475",\ + "0.876852, 1.136734, 1.416423, 1.885223, 2.823768",\ + "1.102693, 1.362663, 1.642718, 2.112406, 3.052734",\ + "1.669927, 1.930012, 2.210544, 2.681391, 3.624044",\ + "0.800100, 1.068010, 1.345799, 1.813594, 2.750176",\ + "0.847199, 1.115129, 1.393000, 1.860997, 2.797984",\ + "0.934467, 1.202456, 1.480563, 1.949136, 2.887277",\ + "1.160309, 1.428387, 1.706858, 2.176319, 3.116243",\ + "1.727543, 1.995738, 2.274684, 2.745304, 3.687553",\ + "1.129877, 1.433405, 1.697668, 2.162941, 3.095633",\ + "1.176977, 1.480531, 1.744871, 2.210345, 3.143440",\ + "1.264251, 1.567875, 1.832440, 2.298486, 3.232733",\ + "1.490099, 1.793832, 2.058744, 2.525673, 3.461699",\ + "2.057343, 2.361218, 2.626582, 3.094663, 4.033009"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011"); + values ( "0.053866, 0.053921, 0.054375, 0.055698, 0.058344",\ + "0.173264, 0.173226, 0.173060, 0.172656, 0.171847",\ + "0.375455, 0.375364, 0.374978, 0.374041, 0.372167",\ + "0.885489, 0.885476, 0.885382, 0.885110, 0.884566",\ + "2.163040, 2.163059, 2.163198, 2.163598, 2.164399",\ + "0.053866, 0.053922, 0.054379, 0.055698, 0.058344",\ + "0.173264, 0.173226, 0.173059, 0.172656, 0.171847",\ + "0.375455, 0.375363, 0.374975, 0.374041, 0.372167",\ + "0.885489, 0.885476, 0.885381, 0.885110, 0.884566",\ + "2.163040, 2.163059, 2.163199, 2.163598, 2.164399",\ + "0.053866, 0.053923, 0.054379, 0.055698, 0.058344",\ + "0.173264, 0.173225, 0.173059, 0.172656, 0.171847",\ + "0.375455, 0.375361, 0.374975, 0.374041, 0.372167",\ + "0.885489, 0.885476, 0.885381, 0.885110, 0.884566",\ + "2.163040, 2.163059, 2.163199, 2.163598, 2.164399",\ + "0.053866, 0.053924, 0.054379, 0.055698, 0.058344",\ + "0.173264, 0.173224, 0.173059, 0.172656, 0.171847",\ + "0.375454, 0.375359, 0.374975, 0.374041, 0.372167",\ + "0.885489, 0.885476, 0.885381, 0.885110, 0.884566",\ + "2.163040, 2.163060, 2.163199, 2.163598, 2.164399",\ + "0.053870, 0.053942, 0.054392, 0.055703, 0.058344",\ + "0.173261, 0.173212, 0.173054, 0.172654, 0.171847",\ + "0.375447, 0.375331, 0.374965, 0.374037, 0.372167",\ + "0.885488, 0.885472, 0.885378, 0.885109, 0.884566",\ + "2.163042, 2.163065, 2.163203, 2.163600, 2.164399"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011"); + values ( "0.504662, 0.755823, 1.035123, 1.501524, 2.434327",\ + "0.565599, 0.817019, 1.097428, 1.566532, 2.504740",\ + "0.632345, 0.883968, 1.165247, 1.636471, 2.578919",\ + "0.766552, 1.018158, 1.299363, 1.770409, 2.712501",\ + "1.110008, 1.361510, 1.642273, 2.112240, 3.052173",\ + "0.592071, 0.843399, 1.122681, 1.588239, 2.520261",\ + "0.653008, 0.904597, 1.184994, 1.653246, 2.590674",\ + "0.719755, 0.971548, 1.252820, 1.723185, 2.664853",\ + "0.853962, 1.105738, 1.386936, 1.857124, 2.798434",\ + "1.197417, 1.449089, 1.729842, 2.198954, 3.138107",\ + "0.672903, 0.932434, 1.210645, 1.675861, 2.607216",\ + "0.733841, 0.993636, 1.272958, 1.740868, 2.677629",\ + "0.800588, 1.060591, 1.340784, 1.810807, 2.751808",\ + "0.934794, 1.194780, 1.474900, 1.944745, 2.885390",\ + "1.278250, 1.538130, 1.817806, 2.286576, 3.225062",\ + "0.730518, 0.998146, 1.274784, 1.739774, 2.670725",\ + "0.791456, 1.059355, 1.337098, 1.804781, 2.741138",\ + "0.858203, 1.126316, 1.404924, 1.874720, 2.815317",\ + "0.992410, 1.260504, 1.539040, 2.008659, 2.948899",\ + "1.335865, 1.603851, 1.881946, 2.350489, 3.288571",\ + "1.060274, 1.363457, 1.626624, 2.089109, 3.016181",\ + "1.121233, 1.424747, 1.688966, 2.154127, 3.086594",\ + "1.187996, 1.491771, 1.756814, 2.224075, 3.160773",\ + "1.322202, 1.625954, 1.890928, 2.358013, 3.294354",\ + "1.665648, 1.969269, 2.233823, 2.699839, 3.634027"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011"); + values ( "0.071595, 0.071985, 0.073663, 0.077752, 0.085929",\ + "0.129674, 0.130204, 0.132478, 0.138021, 0.149107",\ + "0.214013, 0.214497, 0.216573, 0.221634, 0.231755",\ + "0.447089, 0.447144, 0.447376, 0.447942, 0.449074",\ + "1.100695, 1.100670, 1.100562, 1.100300, 1.099777",\ + "0.071595, 0.071989, 0.073676, 0.077752, 0.085929",\ + "0.129674, 0.130208, 0.132495, 0.138021, 0.149107",\ + "0.214013, 0.214501, 0.216589, 0.221634, 0.231755",\ + "0.447089, 0.447144, 0.447378, 0.447942, 0.449074",\ + "1.100695, 1.100670, 1.100561, 1.100300, 1.099777",\ + "0.071595, 0.071996, 0.073676, 0.077752, 0.085929",\ + "0.129674, 0.130218, 0.132496, 0.138021, 0.149107",\ + "0.214014, 0.214510, 0.216590, 0.221634, 0.231755",\ + "0.447089, 0.447145, 0.447378, 0.447942, 0.449074",\ + "1.100695, 1.100669, 1.100561, 1.100300, 1.099777",\ + "0.071596, 0.072006, 0.073677, 0.077752, 0.085929",\ + "0.129675, 0.130232, 0.132497, 0.138021, 0.149107",\ + "0.214014, 0.214523, 0.216591, 0.221634, 0.231755",\ + "0.447090, 0.447146, 0.447378, 0.447942, 0.449074",\ + "1.100695, 1.100668, 1.100561, 1.100300, 1.099777",\ + "0.071627, 0.072128, 0.073719, 0.077769, 0.085929",\ + "0.129718, 0.130397, 0.132553, 0.138044, 0.149107",\ + "0.214054, 0.214674, 0.216642, 0.221655, 0.231755",\ + "0.447094, 0.447163, 0.447384, 0.447944, 0.449074",\ + "1.100693, 1.100661, 1.100559, 1.100299, 1.099777"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_2541*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[27]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011"); + values ( "0.244315, 0.514723, 0.800077, 1.287472, 2.262263",\ + "0.295834, 0.565221, 0.850051, 1.338109, 2.314226",\ + "0.370354, 0.642449, 0.926203, 1.412852, 2.386149",\ + "0.577074, 0.851060, 1.132979, 1.615988, 2.582005",\ + "1.130301, 1.404191, 1.684823, 2.164586, 3.124112",\ + "0.331716, 0.602319, 0.887697, 1.374185, 2.348197",\ + "0.383234, 0.652812, 0.937673, 1.424822, 2.400160",\ + "0.457755, 0.730036, 1.013820, 1.499564, 2.472083",\ + "0.665475, 0.938641, 1.220586, 1.702701, 2.667939",\ + "1.218705, 1.491770, 1.772419, 2.251299, 3.210045",\ + "0.417649, 0.691352, 0.975660, 1.461806, 2.435152",\ + "0.468650, 0.741835, 1.025635, 1.512442, 2.487115",\ + "0.546403, 0.819049, 1.101783, 1.587185, 2.559038",\ + "0.755504, 1.027643, 1.308548, 1.790321, 2.754894",\ + "1.308745, 1.580767, 1.860382, 2.338919, 3.297000",\ + "0.482221, 0.757061, 1.039803, 1.525718, 2.498661",\ + "0.533223, 0.807529, 1.089778, 1.576355, 2.550624",\ + "0.610973, 0.884729, 1.165926, 1.651097, 2.622547",\ + "0.820080, 1.093307, 1.372690, 1.854234, 2.818403",\ + "1.373332, 1.646424, 1.924523, 2.402832, 3.360509",\ + "0.824496, 1.122462, 1.391851, 1.875132, 2.844117",\ + "0.875514, 1.172748, 1.441833, 1.925771, 2.896080",\ + "0.953244, 1.249783, 1.517967, 2.000508, 2.968003",\ + "1.162385, 1.458171, 1.724694, 2.203629, 3.163859",\ + "1.715704, 2.011206, 2.276494, 2.752214, 3.705966"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011"); + values ( "0.247846, 0.303832, 0.405143, 0.595020, 0.974773",\ + "0.313786, 0.346638, 0.435686, 0.627210, 1.010259",\ + "0.435716, 0.458756, 0.530637, 0.704592, 1.052501",\ + "0.888071, 0.889365, 0.918106, 1.015199, 1.209385",\ + "2.165255, 2.165436, 2.171895, 2.192891, 2.234884",\ + "0.247846, 0.304139, 0.405737, 0.595020, 0.974773",\ + "0.313786, 0.346858, 0.436285, 0.627210, 1.010259",\ + "0.435716, 0.458895, 0.531182, 0.704592, 1.052501",\ + "0.888102, 0.889365, 0.918410, 1.015199, 1.209385",\ + "2.165255, 2.165437, 2.171961, 2.192891, 2.234884",\ + "0.250082, 0.304803, 0.405749, 0.595020, 0.974773",\ + "0.314671, 0.347334, 0.436296, 0.627210, 1.010259",\ + "0.436504, 0.459195, 0.531192, 0.704592, 1.052501",\ + "0.888199, 0.889365, 0.918416, 1.015199, 1.209385",\ + "2.165255, 2.165441, 2.171962, 2.192891, 2.234884",\ + "0.251727, 0.305767, 0.405781, 0.595020, 0.974773",\ + "0.315322, 0.348025, 0.436329, 0.627210, 1.010259",\ + "0.437083, 0.459631, 0.531222, 0.704592, 1.052501",\ + "0.888292, 0.889365, 0.918433, 1.015199, 1.209385",\ + "2.165255, 2.165446, 2.171966, 2.192891, 2.234884",\ + "0.262263, 0.317092, 0.407706, 0.595800, 0.974773",\ + "0.319491, 0.356149, 0.438270, 0.627998, 1.010259",\ + "0.440795, 0.464750, 0.532985, 0.705307, 1.052501",\ + "0.888892, 0.889365, 0.919417, 1.015598, 1.209385",\ + "2.165255, 2.165507, 2.172179, 2.192978, 2.234884"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011"); + values ( "0.244906, 0.429066, 0.715031, 1.201577, 2.174669",\ + "0.279961, 0.467088, 0.760757, 1.264102, 2.270793",\ + "0.330500, 0.520871, 0.819993, 1.340074, 2.380235",\ + "0.460001, 0.650607, 0.955135, 1.497108, 2.581054",\ + "0.797840, 0.992388, 1.299994, 1.860913, 2.982751",\ + "0.332306, 0.516668, 0.802648, 1.288290, 2.260602",\ + "0.367361, 0.554708, 0.848427, 1.350815, 2.356727",\ + "0.417900, 0.608494, 0.907716, 1.426787, 2.466169",\ + "0.547401, 0.738223, 1.042926, 1.583821, 2.666988",\ + "0.885240, 1.079987, 1.387844, 1.947626, 3.068685",\ + "0.413157, 0.605714, 0.890611, 1.375910, 2.347558",\ + "0.448212, 0.643794, 0.936391, 1.438436, 2.443682",\ + "0.498750, 0.697588, 0.995681, 1.514407, 2.553124",\ + "0.628251, 0.827301, 1.130892, 1.671441, 2.753943",\ + "0.966089, 1.169027, 1.475811, 2.035246, 3.155640",\ + "0.470897, 0.671442, 0.954754, 1.439822, 2.411067",\ + "0.505953, 0.709581, 1.000537, 1.502348, 2.507191",\ + "0.556489, 0.763385, 1.059829, 1.578320, 2.616633",\ + "0.685989, 0.893075, 1.195044, 1.735354, 2.817452",\ + "1.023827, 1.234747, 1.539967, 2.099159, 3.219149",\ + "0.774671, 1.037059, 1.306793, 1.789232, 2.756522",\ + "0.809728, 1.075884, 1.352747, 1.851827, 2.852647",\ + "0.860246, 1.129813, 1.412209, 1.927867, 2.962089",\ + "0.989742, 1.259233, 1.547645, 2.084991, 3.162908",\ + "1.327573, 1.600271, 1.892761, 2.448874, 3.564605"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011"); + values ( "0.078481, 0.114548, 0.190287, 0.342583, 0.647174",\ + "0.121015, 0.135349, 0.195602, 0.346123, 0.647167",\ + "0.210717, 0.216175, 0.259364, 0.388602, 0.647078",\ + "0.448759, 0.449668, 0.471637, 0.541681, 0.681771",\ + "1.102116, 1.102394, 1.113655, 1.151696, 1.227780",\ + "0.078481, 0.114757, 0.190764, 0.342583, 0.647174",\ + "0.121015, 0.135456, 0.196073, 0.346123, 0.647167",\ + "0.210717, 0.216208, 0.259768, 0.388602, 0.647078",\ + "0.448759, 0.449677, 0.471856, 0.541681, 0.681771",\ + "1.102116, 1.102394, 1.113774, 1.151696, 1.227780",\ + "0.078556, 0.115208, 0.190773, 0.342583, 0.647174",\ + "0.121030, 0.135687, 0.196082, 0.346123, 0.647167",\ + "0.210727, 0.216281, 0.259776, 0.388602, 0.647078",\ + "0.448759, 0.449695, 0.471860, 0.541681, 0.681771",\ + "1.102118, 1.102394, 1.113776, 1.151696, 1.227780",\ + "0.078710, 0.115863, 0.190799, 0.342583, 0.647174",\ + "0.121062, 0.136023, 0.196108, 0.346123, 0.647167",\ + "0.210748, 0.216386, 0.259798, 0.388602, 0.647078",\ + "0.448759, 0.449721, 0.471872, 0.541681, 0.681771",\ + "1.102121, 1.102394, 1.113783, 1.151696, 1.227780",\ + "0.080154, 0.123560, 0.192343, 0.343209, 0.647174",\ + "0.121358, 0.139963, 0.197633, 0.346742, 0.647167",\ + "0.210943, 0.217625, 0.261108, 0.389133, 0.647078",\ + "0.448759, 0.450031, 0.472582, 0.541969, 0.681771",\ + "1.102151, 1.102394, 1.114168, 1.151853, 1.227780"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_2586*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[28]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.802622, 1.056036, 1.346324, 1.867286, 2.909209",\ + "0.849165, 1.102582, 1.392879, 1.913861, 2.955825",\ + "0.934845, 1.188269, 1.478593, 1.999634, 3.041714",\ + "1.158235, 1.411669, 1.702036, 2.223166, 3.265427",\ + "1.722272, 1.975720, 2.266142, 2.787390, 3.829885",\ + "0.890034, 1.143575, 1.434056, 1.954001, 2.995142",\ + "0.936578, 1.190121, 1.480612, 2.000576, 3.041759",\ + "1.022258, 1.275808, 1.566326, 2.086349, 3.127648",\ + "1.245647, 1.499208, 1.789768, 2.309881, 3.351360",\ + "1.809685, 2.063260, 2.353875, 2.874104, 3.915819",\ + "0.970907, 1.232542, 1.522024, 2.041623, 3.082098",\ + "1.017450, 1.279087, 1.568579, 2.088199, 3.128714",\ + "1.103130, 1.364774, 1.654293, 2.173971, 3.214603",\ + "1.326520, 1.588175, 1.877736, 2.397503, 3.438315",\ + "1.890557, 2.152227, 2.441842, 2.961727, 4.002774",\ + "1.029596, 1.298156, 1.586172, 2.105536, 3.145607",\ + "1.076139, 1.344701, 1.632727, 2.152112, 3.192223",\ + "1.161819, 1.430389, 1.718441, 2.237885, 3.278112",\ + "1.385208, 1.653790, 1.941884, 2.461417, 3.501824",\ + "1.949246, 2.217842, 2.505991, 3.025640, 4.066283",\ + "1.361666, 1.662270, 1.938568, 2.455101, 3.491063",\ + "1.408209, 1.708817, 1.985123, 2.501677, 3.537679",\ + "1.493889, 1.794507, 2.070838, 2.587449, 3.623568",\ + "1.717279, 2.017912, 2.294282, 2.810982, 3.847281",\ + "2.281316, 2.581969, 2.858389, 3.375206, 4.411739"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.052266, 0.052273, 0.052301, 0.052359, 0.052477",\ + "0.174376, 0.174371, 0.174352, 0.174312, 0.174230",\ + "0.378069, 0.378057, 0.378013, 0.377917, 0.377724",\ + "0.885437, 0.885434, 0.885402, 0.885305, 0.885113",\ + "2.163117, 2.163121, 2.163168, 2.163310, 2.163594",\ + "0.052266, 0.052273, 0.052301, 0.052359, 0.052477",\ + "0.174376, 0.174371, 0.174352, 0.174312, 0.174230",\ + "0.378069, 0.378057, 0.378012, 0.377917, 0.377724",\ + "0.885437, 0.885434, 0.885401, 0.885305, 0.885113",\ + "2.163117, 2.163121, 2.163169, 2.163310, 2.163594",\ + "0.052266, 0.052274, 0.052301, 0.052359, 0.052477",\ + "0.174376, 0.174371, 0.174352, 0.174312, 0.174230",\ + "0.378069, 0.378057, 0.378012, 0.377917, 0.377724",\ + "0.885437, 0.885434, 0.885401, 0.885305, 0.885113",\ + "2.163117, 2.163121, 2.163169, 2.163310, 2.163594",\ + "0.052266, 0.052274, 0.052301, 0.052359, 0.052477",\ + "0.174376, 0.174371, 0.174352, 0.174312, 0.174230",\ + "0.378069, 0.378057, 0.378012, 0.377917, 0.377724",\ + "0.885437, 0.885434, 0.885401, 0.885305, 0.885113",\ + "2.163117, 2.163121, 2.163169, 2.163310, 2.163594",\ + "0.052266, 0.052276, 0.052301, 0.052360, 0.052477",\ + "0.174376, 0.174369, 0.174352, 0.174311, 0.174230",\ + "0.378069, 0.378052, 0.378011, 0.377916, 0.377724",\ + "0.885437, 0.885432, 0.885400, 0.885305, 0.885113",\ + "2.163117, 2.163123, 2.163170, 2.163311, 2.163594"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.740784, 0.994165, 1.284321, 1.804998, 2.846352",\ + "0.794288, 1.047701, 1.337984, 1.858934, 2.900834",\ + "0.855205, 1.108643, 1.399026, 1.920190, 2.962518",\ + "0.989902, 1.243338, 1.533712, 2.054859, 3.097151",\ + "1.336325, 1.589748, 1.880072, 2.401109, 3.443183",\ + "0.828197, 1.081704, 1.372052, 1.891713, 2.932285",\ + "0.881701, 1.135240, 1.425716, 1.945649, 2.986768",\ + "0.942617, 1.196183, 1.486758, 2.006905, 3.048452",\ + "1.077314, 1.330878, 1.621445, 2.141573, 3.183085",\ + "1.423737, 1.677287, 1.967804, 2.487824, 3.529117",\ + "0.909070, 1.170669, 1.460019, 1.979335, 3.019240",\ + "0.962574, 1.224207, 1.513683, 2.033271, 3.073723",\ + "1.023490, 1.285149, 1.574726, 2.094527, 3.135407",\ + "1.158187, 1.419844, 1.709412, 2.229196, 3.270040",\ + "1.504610, 1.766254, 2.055771, 2.575446, 3.616072",\ + "0.967758, 1.236282, 1.524167, 2.043248, 3.082749",\ + "1.021262, 1.289820, 1.577832, 2.097185, 3.137232",\ + "1.082179, 1.350764, 1.638874, 2.158441, 3.198916",\ + "1.216876, 1.485459, 1.773561, 2.293109, 3.333549",\ + "1.563299, 1.831868, 2.119919, 2.639359, 3.679581",\ + "1.299828, 1.600384, 1.876561, 2.392812, 3.428205",\ + "1.353332, 1.653935, 1.930228, 2.446749, 3.482688",\ + "1.414249, 1.714888, 1.991272, 2.508006, 3.544372",\ + "1.548946, 1.849582, 2.125958, 2.642674, 3.679005",\ + "1.895369, 2.195986, 2.472316, 2.988924, 4.025037"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.060356, 0.060405, 0.060595, 0.061007, 0.061830",\ + "0.114429, 0.114496, 0.114756, 0.115316, 0.116436",\ + "0.200095, 0.200156, 0.200394, 0.200905, 0.201928",\ + "0.445532, 0.445539, 0.445566, 0.445623, 0.445737",\ + "1.101415, 1.101412, 1.101400, 1.101373, 1.101320",\ + "0.060356, 0.060405, 0.060597, 0.061007, 0.061830",\ + "0.114429, 0.114496, 0.114758, 0.115316, 0.116436",\ + "0.200095, 0.200157, 0.200396, 0.200905, 0.201928",\ + "0.445532, 0.445539, 0.445566, 0.445623, 0.445737",\ + "1.101415, 1.101412, 1.101400, 1.101373, 1.101320",\ + "0.060356, 0.060406, 0.060597, 0.061007, 0.061830",\ + "0.114429, 0.114498, 0.114758, 0.115316, 0.116436",\ + "0.200095, 0.200158, 0.200396, 0.200905, 0.201928",\ + "0.445532, 0.445539, 0.445566, 0.445623, 0.445737",\ + "1.101415, 1.101412, 1.101400, 1.101373, 1.101320",\ + "0.060356, 0.060408, 0.060597, 0.061007, 0.061830",\ + "0.114429, 0.114500, 0.114758, 0.115316, 0.116436",\ + "0.200095, 0.200160, 0.200396, 0.200905, 0.201928",\ + "0.445532, 0.445540, 0.445566, 0.445623, 0.445737",\ + "1.101415, 1.101412, 1.101400, 1.101373, 1.101320",\ + "0.060356, 0.060425, 0.060601, 0.061009, 0.061830",\ + "0.114429, 0.114524, 0.114764, 0.115319, 0.116436",\ + "0.200095, 0.200182, 0.200401, 0.200907, 0.201928",\ + "0.445532, 0.445542, 0.445567, 0.445623, 0.445737",\ + "1.101415, 1.101411, 1.101399, 1.101373, 1.101320"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_2628*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[29]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.793277, 1.039130, 1.319023, 1.798101, 2.756257",\ + "0.839819, 1.085675, 1.365575, 1.844669, 2.802857",\ + "0.925498, 1.171358, 1.451280, 1.930420, 2.888700",\ + "1.148884, 1.394753, 1.674707, 2.153918, 3.112340",\ + "1.712918, 1.958797, 2.238793, 2.718097, 3.676705",\ + "0.880682, 1.126695, 1.406620, 1.884815, 2.842191",\ + "0.927225, 1.173240, 1.453171, 1.931383, 2.888791",\ + "1.012903, 1.258923, 1.538876, 2.017133, 2.974633",\ + "1.236289, 1.482318, 1.762303, 2.240632, 3.198274",\ + "1.800323, 2.046363, 2.326390, 2.804811, 3.762639",\ + "0.961504, 1.215685, 1.494583, 1.972436, 2.929146",\ + "1.008047, 1.262229, 1.541135, 2.019004, 2.975746",\ + "1.093725, 1.347913, 1.626839, 2.104754, 3.061589",\ + "1.317111, 1.571308, 1.850267, 2.328253, 3.285229",\ + "1.881145, 2.135353, 2.414354, 2.892432, 3.849594",\ + "1.019140, 1.281331, 1.558724, 2.036349, 2.992655",\ + "1.065682, 1.327876, 1.605276, 2.082916, 3.039255",\ + "1.151360, 1.413560, 1.690981, 2.168667, 3.125098",\ + "1.374747, 1.636955, 1.914408, 2.392166, 3.348738",\ + "1.938781, 2.201000, 2.478495, 2.956345, 3.913103",\ + "1.348815, 1.645927, 1.910691, 2.385732, 3.338111",\ + "1.395358, 1.692472, 1.957243, 2.432300, 3.384711",\ + "1.481036, 1.778158, 2.042948, 2.518051, 3.470554",\ + "1.704422, 2.001556, 2.266376, 2.741550, 3.694194",\ + "2.268456, 2.565605, 2.830464, 3.305729, 4.258559"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.052265, 0.052270, 0.052291, 0.052337, 0.052430",\ + "0.174378, 0.174374, 0.174359, 0.174327, 0.174262",\ + "0.378072, 0.378063, 0.378028, 0.377953, 0.377801",\ + "0.885436, 0.885432, 0.885397, 0.885300, 0.885105",\ + "2.163117, 2.163124, 2.163175, 2.163318, 2.163605",\ + "0.052265, 0.052270, 0.052291, 0.052337, 0.052430",\ + "0.174378, 0.174374, 0.174359, 0.174327, 0.174262",\ + "0.378072, 0.378063, 0.378028, 0.377953, 0.377801",\ + "0.885436, 0.885432, 0.885397, 0.885300, 0.885105",\ + "2.163117, 2.163124, 2.163175, 2.163318, 2.163605",\ + "0.052265, 0.052270, 0.052291, 0.052337, 0.052430",\ + "0.174378, 0.174374, 0.174359, 0.174327, 0.174262",\ + "0.378072, 0.378063, 0.378028, 0.377953, 0.377801",\ + "0.885436, 0.885432, 0.885397, 0.885300, 0.885105",\ + "2.163117, 2.163124, 2.163175, 2.163318, 2.163605",\ + "0.052265, 0.052270, 0.052291, 0.052337, 0.052430",\ + "0.174378, 0.174374, 0.174359, 0.174327, 0.174262",\ + "0.378072, 0.378062, 0.378028, 0.377953, 0.377801",\ + "0.885436, 0.885432, 0.885397, 0.885300, 0.885105",\ + "2.163117, 2.163124, 2.163175, 2.163318, 2.163605",\ + "0.052265, 0.052272, 0.052292, 0.052338, 0.052430",\ + "0.174378, 0.174372, 0.174359, 0.174327, 0.174262",\ + "0.378072, 0.378059, 0.378027, 0.377952, 0.377801",\ + "0.885436, 0.885430, 0.885396, 0.885299, 0.885105",\ + "2.163117, 2.163126, 2.163177, 2.163319, 2.163605"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.731449, 0.977276, 1.257067, 1.735920, 2.693626",\ + "0.784944, 1.030796, 1.310685, 1.789754, 2.747891",\ + "0.845853, 1.091725, 1.371691, 1.850929, 2.809405",\ + "0.980551, 1.226421, 1.506381, 1.985605, 2.944052",\ + "1.326977, 1.572838, 1.852758, 2.331896, 3.290171",\ + "0.818854, 1.064841, 1.344662, 1.822633, 2.779559",\ + "0.872349, 1.118361, 1.398281, 1.876467, 2.833825",\ + "0.933258, 1.179290, 1.459288, 1.937643, 2.895339",\ + "1.067956, 1.313987, 1.593977, 2.072318, 3.029986",\ + "1.414383, 1.660403, 1.940354, 2.418609, 3.376105",\ + "0.899676, 1.153830, 1.432626, 1.910254, 2.866514",\ + "0.953171, 1.207350, 1.486244, 1.964088, 2.920780",\ + "1.014081, 1.268280, 1.547251, 2.025264, 2.982294",\ + "1.148778, 1.402976, 1.681941, 2.159939, 3.116941",\ + "1.495205, 1.749392, 2.028318, 2.506230, 3.463060",\ + "0.957311, 1.219475, 1.496767, 1.974167, 2.930023",\ + "1.010806, 1.272997, 1.550386, 2.028001, 2.984289",\ + "1.071716, 1.333927, 1.611393, 2.089177, 3.045803",\ + "1.206414, 1.468623, 1.746082, 2.223852, 3.180450",\ + "1.552840, 1.815039, 2.092459, 2.570143, 3.526569",\ + "1.286987, 1.584062, 1.848731, 2.323550, 3.275480",\ + "1.340482, 1.637592, 1.902352, 2.377385, 3.329745",\ + "1.401392, 1.698529, 1.963361, 2.438561, 3.391259",\ + "1.536089, 1.833225, 2.098050, 2.573236, 3.525906",\ + "1.882516, 2.179637, 2.444427, 2.919527, 3.872025"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.060343, 0.060380, 0.060528, 0.060852, 0.061502",\ + "0.114411, 0.114462, 0.114664, 0.115106, 0.115991",\ + "0.200079, 0.200126, 0.200310, 0.200714, 0.201522",\ + "0.445531, 0.445536, 0.445556, 0.445602, 0.445692",\ + "1.101416, 1.101414, 1.101404, 1.101383, 1.101341",\ + "0.060343, 0.060381, 0.060529, 0.060852, 0.061502",\ + "0.114411, 0.114463, 0.114665, 0.115106, 0.115991",\ + "0.200079, 0.200126, 0.200311, 0.200714, 0.201522",\ + "0.445531, 0.445536, 0.445556, 0.445602, 0.445692",\ + "1.101416, 1.101414, 1.101404, 1.101383, 1.101341",\ + "0.060343, 0.060382, 0.060529, 0.060852, 0.061502",\ + "0.114411, 0.114464, 0.114665, 0.115106, 0.115991",\ + "0.200079, 0.200127, 0.200311, 0.200714, 0.201522",\ + "0.445531, 0.445536, 0.445556, 0.445602, 0.445692",\ + "1.101416, 1.101413, 1.101404, 1.101383, 1.101341",\ + "0.060343, 0.060383, 0.060529, 0.060852, 0.061502",\ + "0.114411, 0.114465, 0.114665, 0.115106, 0.115991",\ + "0.200079, 0.200128, 0.200311, 0.200714, 0.201522",\ + "0.445531, 0.445536, 0.445556, 0.445602, 0.445692",\ + "1.101416, 1.101413, 1.101404, 1.101383, 1.101341",\ + "0.060343, 0.060396, 0.060532, 0.060854, 0.061502",\ + "0.114411, 0.114483, 0.114670, 0.115108, 0.115991",\ + "0.200079, 0.200145, 0.200315, 0.200715, 0.201522",\ + "0.445531, 0.445538, 0.445557, 0.445602, 0.445692",\ + "1.101416, 1.101413, 1.101404, 1.101383, 1.101341"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_2679*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[31]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.704078, 0.962448, 1.254543, 1.772415, 2.808159",\ + "0.750305, 1.008676, 1.300771, 1.818645, 2.854393",\ + "0.834537, 1.092907, 1.385001, 1.902873, 2.938617",\ + "1.055475, 1.313845, 1.605937, 2.123804, 3.159536",\ + "1.615778, 1.874147, 2.166233, 2.684084, 3.719787",\ + "0.791487, 1.050012, 1.342263, 1.859129, 2.894093",\ + "0.837714, 1.096239, 1.388491, 1.905359, 2.940326",\ + "0.921945, 1.180470, 1.472721, 1.989588, 3.024551",\ + "1.142884, 1.401409, 1.693658, 2.210518, 3.245470",\ + "1.703187, 1.961710, 2.253953, 2.770799, 3.805721",\ + "0.872371, 1.139015, 1.430229, 1.946751, 2.981048",\ + "0.918598, 1.185243, 1.476457, 1.992981, 3.027281",\ + "1.002829, 1.269474, 1.560688, 2.077209, 3.111506",\ + "1.223768, 1.490412, 1.781624, 2.298140, 3.332425",\ + "1.784070, 2.050714, 2.341920, 2.858420, 3.892676",\ + "0.932831, 1.204683, 1.494377, 2.010664, 3.044557",\ + "0.979058, 1.250910, 1.540605, 2.056894, 3.090790",\ + "1.063289, 1.335141, 1.624835, 2.141123, 3.175015",\ + "1.284228, 1.556080, 1.845772, 2.362053, 3.395934",\ + "1.844531, 2.116381, 2.406067, 2.922334, 3.956185",\ + "1.268348, 1.569475, 1.846740, 2.360211, 3.390013",\ + "1.314575, 1.615702, 1.892967, 2.406441, 3.436246",\ + "1.398806, 1.699933, 1.977198, 2.490670, 3.520471",\ + "1.619745, 1.920872, 2.198134, 2.711600, 3.741390",\ + "2.180047, 2.481173, 2.758430, 3.271881, 4.301641"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.053020, 0.053022, 0.053032, 0.053060, 0.053117",\ + "0.178801, 0.178804, 0.178822, 0.178869, 0.178965",\ + "0.381845, 0.381847, 0.381855, 0.381877, 0.381921",\ + "0.885630, 0.885624, 0.885585, 0.885483, 0.885278",\ + "2.162832, 2.162841, 2.162898, 2.163049, 2.163351",\ + "0.053020, 0.053022, 0.053032, 0.053060, 0.053117",\ + "0.178801, 0.178804, 0.178822, 0.178869, 0.178965",\ + "0.381845, 0.381847, 0.381855, 0.381877, 0.381921",\ + "0.885630, 0.885624, 0.885585, 0.885483, 0.885278",\ + "2.162832, 2.162841, 2.162899, 2.163049, 2.163351",\ + "0.053020, 0.053022, 0.053032, 0.053060, 0.053117",\ + "0.178801, 0.178804, 0.178822, 0.178869, 0.178965",\ + "0.381845, 0.381847, 0.381855, 0.381877, 0.381921",\ + "0.885630, 0.885624, 0.885585, 0.885483, 0.885278",\ + "2.162832, 2.162841, 2.162899, 2.163049, 2.163351",\ + "0.053020, 0.053022, 0.053032, 0.053060, 0.053117",\ + "0.178801, 0.178804, 0.178822, 0.178869, 0.178965",\ + "0.381845, 0.381847, 0.381855, 0.381877, 0.381921",\ + "0.885630, 0.885624, 0.885585, 0.885483, 0.885278",\ + "2.162832, 2.162841, 2.162899, 2.163049, 2.163351",\ + "0.053020, 0.053022, 0.053033, 0.053061, 0.053117",\ + "0.178801, 0.178805, 0.178823, 0.178870, 0.178965",\ + "0.381845, 0.381847, 0.381855, 0.381877, 0.381921",\ + "0.885630, 0.885621, 0.885584, 0.885482, 0.885278",\ + "2.162832, 2.162845, 2.162900, 2.163050, 2.163351"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.653096, 0.911470, 1.203587, 1.721520, 2.757385",\ + "0.695785, 0.954155, 1.246248, 1.764117, 2.799856",\ + "0.751534, 1.009904, 1.301996, 1.819860, 2.855588",\ + "0.887244, 1.145615, 1.437709, 1.955581, 2.991326",\ + "1.236608, 1.494979, 1.787076, 2.304955, 3.340714",\ + "0.740505, 0.999033, 1.291307, 1.808234, 2.843319",\ + "0.783194, 1.041719, 1.333969, 1.850832, 2.885789",\ + "0.838943, 1.097468, 1.389716, 1.906574, 2.941522",\ + "0.974653, 1.233178, 1.525429, 2.042296, 3.077260",\ + "1.324017, 1.582542, 1.874796, 2.391670, 3.426647",\ + "0.821388, 1.088037, 1.379274, 1.895856, 2.930274",\ + "0.864078, 1.130722, 1.421935, 1.938454, 2.972744",\ + "0.919827, 1.186471, 1.477682, 1.994196, 3.028477",\ + "1.055537, 1.322181, 1.613395, 2.129917, 3.164215",\ + "1.404901, 1.671546, 1.962763, 2.479291, 3.513602",\ + "0.881849, 1.153705, 1.443422, 1.959769, 2.993783",\ + "0.924538, 1.196390, 1.486083, 2.002367, 3.036253",\ + "0.980287, 1.252139, 1.541830, 2.058109, 3.091986",\ + "1.115997, 1.387849, 1.677543, 2.193830, 3.227724",\ + "1.465361, 1.737213, 2.026911, 2.543204, 3.577111",\ + "1.217365, 1.518498, 1.795785, 2.309317, 3.339239",\ + "1.260055, 1.561182, 1.838445, 2.351914, 3.381710",\ + "1.315804, 1.616930, 1.894192, 2.407657, 3.437442",\ + "1.451514, 1.752641, 2.029906, 2.543378, 3.573180",\ + "1.800878, 2.102005, 2.379273, 2.892752, 3.922567"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.046012, 0.046005, 0.045968, 0.045869, 0.045670",\ + "0.095119, 0.095114, 0.095079, 0.094989, 0.094807",\ + "0.188959, 0.188960, 0.188961, 0.188966, 0.188975",\ + "0.443992, 0.443992, 0.443991, 0.443987, 0.443980",\ + "1.101604, 1.101604, 1.101601, 1.101596, 1.101585",\ + "0.046012, 0.046005, 0.045968, 0.045869, 0.045670",\ + "0.095119, 0.095114, 0.095079, 0.094989, 0.094807",\ + "0.188959, 0.188960, 0.188961, 0.188966, 0.188975",\ + "0.443992, 0.443992, 0.443991, 0.443987, 0.443980",\ + "1.101604, 1.101604, 1.101601, 1.101596, 1.101585",\ + "0.046012, 0.046005, 0.045968, 0.045869, 0.045670",\ + "0.095119, 0.095114, 0.095079, 0.094989, 0.094807",\ + "0.188959, 0.188960, 0.188961, 0.188966, 0.188975",\ + "0.443992, 0.443992, 0.443991, 0.443987, 0.443980",\ + "1.101604, 1.101604, 1.101601, 1.101596, 1.101585",\ + "0.046012, 0.046005, 0.045968, 0.045869, 0.045670",\ + "0.095119, 0.095113, 0.095079, 0.094989, 0.094807",\ + "0.188959, 0.188960, 0.188961, 0.188966, 0.188975",\ + "0.443992, 0.443992, 0.443991, 0.443987, 0.443980",\ + "1.101604, 1.101604, 1.101601, 1.101596, 1.101585",\ + "0.046012, 0.046003, 0.045967, 0.045868, 0.045670",\ + "0.095119, 0.095111, 0.095078, 0.094988, 0.094807",\ + "0.188959, 0.188960, 0.188961, 0.188966, 0.188975",\ + "0.443992, 0.443992, 0.443991, 0.443987, 0.443980",\ + "1.101604, 1.101603, 1.101601, 1.101596, 1.101585"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[2]_redg*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[33]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.687749, 0.939290, 1.220370, 1.693212, 2.638895",\ + "0.733976, 0.985517, 1.266598, 1.739441, 2.685128",\ + "0.818208, 1.069748, 1.350828, 1.823670, 2.769354",\ + "1.039147, 1.290687, 1.571764, 2.044601, 2.990274",\ + "1.599449, 1.850988, 2.132060, 2.604883, 3.550529",\ + "0.775154, 1.026875, 1.307946, 1.779925, 2.724829",\ + "0.821381, 1.073102, 1.354175, 1.826155, 2.771062",\ + "0.905613, 1.157333, 1.438405, 1.910384, 2.855288",\ + "1.126552, 1.378272, 1.659341, 2.131315, 3.076208",\ + "1.686854, 1.938572, 2.219636, 2.691597, 3.636462",\ + "0.855968, 1.115908, 1.395910, 1.867546, 2.811784",\ + "0.902195, 1.162135, 1.442138, 1.913776, 2.858017",\ + "0.986426, 1.246367, 1.526368, 1.998005, 2.942243",\ + "1.207365, 1.467305, 1.747304, 2.218936, 3.163163",\ + "1.767667, 2.027606, 2.307599, 2.779218, 3.723417",\ + "0.913586, 1.181618, 1.460050, 1.931459, 2.875293",\ + "0.959814, 1.227846, 1.506278, 1.977689, 2.921526",\ + "1.044045, 1.312077, 1.590508, 2.061918, 3.005752",\ + "1.264984, 1.533015, 1.811444, 2.282849, 3.226672",\ + "1.825286, 2.093316, 2.371740, 2.843130, 3.786926",\ + "1.247292, 1.546964, 1.811953, 2.280817, 3.220749",\ + "1.293519, 1.593192, 1.858181, 2.327047, 3.266982",\ + "1.377751, 1.677423, 1.942412, 2.411276, 3.351208",\ + "1.598690, 1.898361, 2.163348, 2.632206, 3.572128",\ + "2.158992, 2.458661, 2.723643, 3.192488, 4.132382"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.053020, 0.053023, 0.053033, 0.053059, 0.053110",\ + "0.178802, 0.178805, 0.178823, 0.178866, 0.178953",\ + "0.381846, 0.381847, 0.381856, 0.381876, 0.381916",\ + "0.885629, 0.885621, 0.885582, 0.885489, 0.885303",\ + "2.162833, 2.162845, 2.162902, 2.163039, 2.163313",\ + "0.053020, 0.053023, 0.053033, 0.053059, 0.053110",\ + "0.178802, 0.178805, 0.178823, 0.178866, 0.178953",\ + "0.381846, 0.381847, 0.381856, 0.381876, 0.381916",\ + "0.885629, 0.885621, 0.885582, 0.885489, 0.885303",\ + "2.162833, 2.162845, 2.162903, 2.163039, 2.163313",\ + "0.053020, 0.053023, 0.053033, 0.053059, 0.053110",\ + "0.178802, 0.178805, 0.178823, 0.178866, 0.178953",\ + "0.381846, 0.381847, 0.381856, 0.381876, 0.381916",\ + "0.885629, 0.885621, 0.885582, 0.885489, 0.885303",\ + "2.162833, 2.162846, 2.162903, 2.163039, 2.163313",\ + "0.053020, 0.053023, 0.053033, 0.053059, 0.053110",\ + "0.178802, 0.178805, 0.178823, 0.178866, 0.178953",\ + "0.381846, 0.381847, 0.381856, 0.381876, 0.381916",\ + "0.885629, 0.885621, 0.885582, 0.885489, 0.885303",\ + "2.162833, 2.162846, 2.162903, 2.163039, 2.163313",\ + "0.053020, 0.053023, 0.053033, 0.053059, 0.053110",\ + "0.178802, 0.178807, 0.178824, 0.178867, 0.178953",\ + "0.381846, 0.381848, 0.381856, 0.381876, 0.381916",\ + "0.885629, 0.885618, 0.885581, 0.885489, 0.885303",\ + "2.162833, 2.162850, 2.162904, 2.163039, 2.163313"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.636768, 0.888313, 1.169416, 1.642313, 2.588106",\ + "0.679456, 0.930997, 1.212076, 1.684915, 2.630593",\ + "0.735206, 0.986745, 1.267823, 1.740657, 2.686327",\ + "0.870915, 1.122456, 1.403536, 1.876378, 2.822062",\ + "1.220279, 1.471821, 1.752903, 2.225752, 3.171448",\ + "0.724173, 0.975898, 1.256993, 1.729026, 2.674040",\ + "0.766861, 1.018582, 1.299652, 1.771628, 2.716527",\ + "0.822611, 1.074330, 1.355399, 1.827371, 2.772260",\ + "0.958320, 1.210041, 1.491113, 1.963092, 2.907996",\ + "1.307685, 1.559406, 1.840480, 2.312465, 3.257382",\ + "0.804986, 1.064932, 1.344956, 1.816648, 2.760995",\ + "0.847675, 1.107615, 1.387615, 1.859249, 2.803482",\ + "0.903424, 1.163364, 1.443362, 1.914992, 2.859215",\ + "1.039134, 1.299074, 1.579076, 2.050713, 2.994951",\ + "1.388498, 1.648439, 1.928443, 2.400086, 3.344337",\ + "0.862605, 1.130642, 1.409096, 1.880560, 2.824504",\ + "0.905293, 1.173325, 1.451756, 1.923162, 2.866991",\ + "0.961043, 1.229074, 1.507503, 1.978905, 2.922724",\ + "1.096752, 1.364785, 1.643216, 2.114626, 3.058460",\ + "1.446117, 1.714149, 1.992583, 2.463999, 3.407846",\ + "1.196311, 1.495989, 1.761000, 2.229918, 3.169960",\ + "1.238999, 1.538671, 1.803659, 2.272520, 3.212447",\ + "1.294749, 1.594420, 1.859406, 2.328263, 3.268181",\ + "1.430458, 1.730130, 1.995120, 2.463984, 3.403916",\ + "1.779823, 2.079495, 2.344487, 2.813357, 3.753302"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.046010, 0.046003, 0.045965, 0.045875, 0.045695",\ + "0.095118, 0.095111, 0.095077, 0.094995, 0.094830",\ + "0.188959, 0.188960, 0.188961, 0.188966, 0.188974",\ + "0.443992, 0.443992, 0.443991, 0.443988, 0.443981",\ + "1.101604, 1.101603, 1.101601, 1.101596, 1.101586",\ + "0.046010, 0.046002, 0.045965, 0.045875, 0.045695",\ + "0.095118, 0.095111, 0.095077, 0.094995, 0.094830",\ + "0.188959, 0.188960, 0.188961, 0.188966, 0.188974",\ + "0.443992, 0.443992, 0.443991, 0.443988, 0.443981",\ + "1.101604, 1.101603, 1.101601, 1.101596, 1.101586",\ + "0.046010, 0.046002, 0.045965, 0.045875, 0.045695",\ + "0.095118, 0.095111, 0.095077, 0.094995, 0.094830",\ + "0.188959, 0.188960, 0.188961, 0.188966, 0.188974",\ + "0.443992, 0.443992, 0.443991, 0.443988, 0.443981",\ + "1.101604, 1.101603, 1.101601, 1.101596, 1.101586",\ + "0.046010, 0.046002, 0.045965, 0.045875, 0.045695",\ + "0.095118, 0.095111, 0.095077, 0.094995, 0.094830",\ + "0.188959, 0.188960, 0.188962, 0.188966, 0.188974",\ + "0.443992, 0.443992, 0.443991, 0.443988, 0.443981",\ + "1.101604, 1.101603, 1.101601, 1.101596, 1.101586",\ + "0.046010, 0.045999, 0.045964, 0.045875, 0.045695",\ + "0.095118, 0.095108, 0.095076, 0.094994, 0.094830",\ + "0.188959, 0.188960, 0.188962, 0.188966, 0.188974",\ + "0.443992, 0.443992, 0.443991, 0.443988, 0.443981",\ + "1.101604, 1.101603, 1.101601, 1.101596, 1.101586"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_2370*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[34]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011"); + values ( "0.622933, 0.904214, 1.205191, 1.719790, 2.748989",\ + "0.669468, 0.950758, 1.251803, 1.766599, 2.796192",\ + "0.755125, 1.036441, 1.337680, 1.853039, 2.883759",\ + "0.978478, 1.259834, 1.561373, 2.077602, 3.110059",\ + "1.542469, 1.823877, 2.125806, 2.643168, 3.677893",\ + "0.710344, 0.991835, 1.292902, 1.806505, 2.834923",\ + "0.756879, 1.038379, 1.339514, 1.853314, 2.882126",\ + "0.842536, 1.124062, 1.425393, 1.939754, 2.969692",\ + "1.065890, 1.347456, 1.649089, 2.164316, 3.195993",\ + "1.629880, 1.911499, 2.213525, 2.729883, 3.763827",\ + "0.799646, 1.080982, 1.380869, 1.894127, 2.921878",\ + "0.846182, 1.127527, 1.427481, 1.940936, 2.969081",\ + "0.931839, 1.213210, 1.513360, 2.027376, 3.056648",\ + "1.155193, 1.436604, 1.737056, 2.251938, 3.282948",\ + "1.719185, 2.000648, 2.301492, 2.817505, 3.850782",\ + "0.863267, 1.146859, 1.445016, 1.958041, 2.985387",\ + "0.909803, 1.193403, 1.491629, 2.004849, 3.032590",\ + "0.995460, 1.279087, 1.577507, 2.091290, 3.120157",\ + "1.218815, 1.502483, 1.801203, 2.315852, 3.346457",\ + "1.782807, 2.066528, 2.365640, 2.881418, 3.914291",\ + "1.199521, 1.514063, 1.797347, 2.307577, 3.330843",\ + "1.246057, 1.560610, 1.843961, 2.354387, 3.378046",\ + "1.331717, 1.646302, 1.929846, 2.440829, 3.465612",\ + "1.555075, 1.869709, 2.153550, 2.665395, 3.691913",\ + "2.119071, 2.433770, 2.717999, 3.230966, 4.259747"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011"); + values ( "0.052243, 0.052269, 0.054671, 0.062895, 0.079343",\ + "0.174393, 0.174375, 0.174239, 0.173844, 0.173056",\ + "0.378107, 0.378064, 0.377824, 0.377171, 0.375864",\ + "0.885321, 0.885201, 0.884881, 0.884213, 0.882876",\ + "2.163287, 2.163464, 2.163713, 2.163931, 2.164366",\ + "0.052243, 0.052269, 0.054697, 0.062895, 0.079343",\ + "0.174393, 0.174374, 0.174237, 0.173844, 0.173056",\ + "0.378107, 0.378064, 0.377822, 0.377171, 0.375864",\ + "0.885321, 0.885200, 0.884879, 0.884213, 0.882876",\ + "2.163287, 2.163465, 2.163714, 2.163931, 2.164366",\ + "0.052243, 0.052270, 0.054697, 0.062895, 0.079343",\ + "0.174392, 0.174374, 0.174237, 0.173844, 0.173056",\ + "0.378106, 0.378063, 0.377822, 0.377171, 0.375864",\ + "0.885318, 0.885198, 0.884879, 0.884213, 0.882876",\ + "2.163292, 2.163468, 2.163714, 2.163931, 2.164366",\ + "0.052244, 0.052270, 0.054698, 0.062895, 0.079343",\ + "0.174392, 0.174374, 0.174237, 0.173844, 0.173056",\ + "0.378106, 0.378062, 0.377822, 0.377171, 0.375864",\ + "0.885315, 0.885196, 0.884879, 0.884213, 0.882876",\ + "2.163296, 2.163471, 2.163714, 2.163931, 2.164366",\ + "0.052246, 0.052278, 0.054782, 0.062929, 0.079343",\ + "0.174391, 0.174368, 0.174233, 0.173843, 0.173056",\ + "0.378102, 0.378049, 0.377815, 0.377168, 0.375864",\ + "0.885300, 0.885164, 0.884872, 0.884210, 0.882876",\ + "2.163318, 2.163518, 2.163716, 2.163932, 2.164366"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011"); + values ( "0.561209, 0.842364, 1.145718, 1.669104, 2.715876",\ + "0.614604, 0.895880, 1.196912, 1.711724, 2.741347",\ + "0.675435, 0.956806, 1.258457, 1.775014, 2.808127",\ + "0.810139, 1.091502, 1.393093, 1.909477, 2.942242",\ + "1.156606, 1.437920, 1.739149, 2.254480, 3.285141",\ + "0.648620, 0.929984, 1.233457, 1.755819, 2.801810",\ + "0.702015, 0.983501, 1.284623, 1.798438, 2.827281",\ + "0.762846, 1.044428, 1.346174, 1.861729, 2.894061",\ + "0.897551, 1.179124, 1.480810, 1.996191, 3.028176",\ + "1.244017, 1.525542, 1.826863, 2.341195, 3.371075",\ + "0.737920, 1.019129, 1.321424, 1.843441, 2.888765",\ + "0.791317, 1.072648, 1.372590, 1.886060, 2.914236",\ + "0.852150, 1.133576, 1.434141, 1.949351, 2.981016",\ + "0.986854, 1.268272, 1.568777, 2.083813, 3.115131",\ + "1.333320, 1.614689, 1.914829, 2.428817, 3.458030",\ + "0.801540, 1.085002, 1.385573, 1.907354, 2.952274",\ + "0.854938, 1.138524, 1.436738, 1.949974, 2.977745",\ + "0.915772, 1.199455, 1.498289, 2.013264, 3.044525",\ + "1.050476, 1.334151, 1.632925, 2.147727, 3.178640",\ + "1.396941, 1.680567, 1.978977, 2.492730, 3.521539",\ + "1.137784, 1.452168, 1.737993, 2.256927, 3.297729",\ + "1.191192, 1.505727, 1.789070, 2.299511, 3.323201",\ + "1.252033, 1.566686, 1.850639, 2.362809, 3.389981",\ + "1.386736, 1.701380, 1.985273, 2.497271, 3.524096",\ + "1.733197, 2.047781, 2.331315, 2.842270, 3.866995"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011"); + values ( "0.060194, 0.060374, 0.061744, 0.065730, 0.073703",\ + "0.114206, 0.114454, 0.116316, 0.121721, 0.132532",\ + "0.199891, 0.200118, 0.201818, 0.206753, 0.216623",\ + "0.445510, 0.445535, 0.445725, 0.446277, 0.447381",\ + "1.101426, 1.101414, 1.101326, 1.101071, 1.100560",\ + "0.060194, 0.060375, 0.061757, 0.065730, 0.073703",\ + "0.114206, 0.114455, 0.116333, 0.121721, 0.132532",\ + "0.199891, 0.200119, 0.201834, 0.206753, 0.216623",\ + "0.445510, 0.445535, 0.445727, 0.446277, 0.447381",\ + "1.101426, 1.101414, 1.101325, 1.101071, 1.100560",\ + "0.060197, 0.060379, 0.061757, 0.065730, 0.073703",\ + "0.114210, 0.114460, 0.116333, 0.121721, 0.132532",\ + "0.199895, 0.200123, 0.201834, 0.206753, 0.216623",\ + "0.445510, 0.445535, 0.445727, 0.446277, 0.447381",\ + "1.101426, 1.101414, 1.101325, 1.101071, 1.100560",\ + "0.060200, 0.060383, 0.061757, 0.065730, 0.073703",\ + "0.114213, 0.114466, 0.116334, 0.121721, 0.132532",\ + "0.199898, 0.200129, 0.201835, 0.206753, 0.216623",\ + "0.445510, 0.445536, 0.445727, 0.446277, 0.447381",\ + "1.101425, 1.101413, 1.101325, 1.101071, 1.100560",\ + "0.060213, 0.060438, 0.061798, 0.065747, 0.073703",\ + "0.114232, 0.114541, 0.116389, 0.121744, 0.132532",\ + "0.199915, 0.200198, 0.201885, 0.206773, 0.216623",\ + "0.445512, 0.445544, 0.445733, 0.446279, 0.447381",\ + "1.101425, 1.101410, 1.101323, 1.101070, 1.100560"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_2367*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[41]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.746470, 1.014882, 1.306808, 1.802638, 2.794297",\ + "0.792702, 1.061114, 1.353041, 1.848873, 2.840536",\ + "0.876929, 1.145341, 1.437267, 1.933097, 2.924756",\ + "1.097854, 1.366266, 1.658190, 2.154013, 3.145659",\ + "1.658121, 1.926532, 2.218450, 2.714257, 3.705872",\ + "0.833878, 1.102487, 1.394459, 1.889352, 2.880230",\ + "0.880110, 1.148719, 1.440691, 1.935587, 2.926469",\ + "0.964337, 1.232946, 1.524917, 2.019811, 3.010689",\ + "1.185262, 1.453871, 1.745840, 2.240727, 3.231593",\ + "1.745530, 2.014137, 2.306100, 2.800972, 3.791806",\ + "0.914792, 1.191581, 1.482424, 1.976974, 2.967185",\ + "0.961024, 1.237813, 1.528656, 2.023208, 3.013424",\ + "1.045251, 1.322040, 1.612882, 2.107432, 3.097644",\ + "1.266176, 1.542965, 1.833805, 2.328349, 3.318548",\ + "1.826444, 2.103231, 2.394065, 2.888593, 3.878761",\ + "0.976718, 1.257380, 1.546568, 2.040887, 3.030694",\ + "1.022949, 1.303612, 1.592801, 2.087121, 3.076933",\ + "1.107176, 1.387838, 1.677027, 2.171345, 3.161153",\ + "1.328102, 1.608763, 1.897949, 2.392262, 3.382057",\ + "1.888369, 2.169030, 2.458210, 2.952506, 3.942270",\ + "1.314895, 1.623717, 1.898706, 2.390343, 3.376151",\ + "1.361127, 1.669949, 1.944939, 2.436577, 3.422390",\ + "1.445354, 1.754176, 2.029165, 2.520801, 3.506609",\ + "1.666279, 1.975101, 2.250087, 2.741717, 3.727513",\ + "2.226547, 2.535367, 2.810348, 3.301962, 4.287725"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.053085, 0.053087, 0.053099, 0.053129, 0.053189",\ + "0.178912, 0.178915, 0.178935, 0.178986, 0.179088",\ + "0.381897, 0.381898, 0.381907, 0.381931, 0.381978",\ + "0.885391, 0.885384, 0.885342, 0.885232, 0.885012",\ + "2.163183, 2.163193, 2.163255, 2.163418, 2.163742",\ + "0.053085, 0.053087, 0.053099, 0.053129, 0.053189",\ + "0.178912, 0.178915, 0.178935, 0.178986, 0.179088",\ + "0.381897, 0.381898, 0.381907, 0.381931, 0.381978",\ + "0.885391, 0.885384, 0.885342, 0.885232, 0.885012",\ + "2.163183, 2.163194, 2.163256, 2.163418, 2.163742",\ + "0.053085, 0.053087, 0.053099, 0.053129, 0.053189",\ + "0.178912, 0.178915, 0.178935, 0.178986, 0.179088",\ + "0.381897, 0.381898, 0.381907, 0.381931, 0.381978",\ + "0.885391, 0.885384, 0.885342, 0.885232, 0.885012",\ + "2.163183, 2.163194, 2.163256, 2.163418, 2.163742",\ + "0.053085, 0.053087, 0.053099, 0.053129, 0.053189",\ + "0.178912, 0.178915, 0.178935, 0.178986, 0.179088",\ + "0.381897, 0.381898, 0.381907, 0.381931, 0.381978",\ + "0.885391, 0.885384, 0.885342, 0.885232, 0.885012",\ + "2.163183, 2.163194, 2.163256, 2.163418, 2.163742",\ + "0.053085, 0.053088, 0.053099, 0.053129, 0.053189",\ + "0.178912, 0.178916, 0.178935, 0.178986, 0.179088",\ + "0.381897, 0.381899, 0.381907, 0.381931, 0.381978",\ + "0.885391, 0.885382, 0.885341, 0.885232, 0.885012",\ + "2.163183, 2.163198, 2.163258, 2.163418, 2.163742"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.695629, 0.964045, 1.256010, 1.751953, 2.743838",\ + "0.738170, 1.006582, 1.298507, 1.794334, 2.785986",\ + "0.793908, 1.062320, 1.354243, 1.850064, 2.841706",\ + "0.929637, 1.198049, 1.489976, 1.985806, 2.977466",\ + "1.279017, 1.547430, 1.839359, 2.335196, 3.326870",\ + "0.783037, 1.051650, 1.343661, 1.838667, 2.829772",\ + "0.825579, 1.094187, 1.386158, 1.881048, 2.871920",\ + "0.881317, 1.149925, 1.441893, 1.936778, 2.927640",\ + "1.017045, 1.285654, 1.577626, 2.072520, 3.063399",\ + "1.366425, 1.635035, 1.927009, 2.421910, 3.412804",\ + "0.863951, 1.140744, 1.431626, 1.926289, 2.916727",\ + "0.906492, 1.183281, 1.474123, 1.968669, 2.958875",\ + "0.962231, 1.239019, 1.529858, 2.024400, 3.014595",\ + "1.097959, 1.374748, 1.665591, 2.160141, 3.150354",\ + "1.447339, 1.724128, 2.014974, 2.509532, 3.499759",\ + "0.925877, 1.206543, 1.495770, 1.990202, 2.980236",\ + "0.968418, 1.249080, 1.538267, 2.032583, 3.022384",\ + "1.024156, 1.304818, 1.594002, 2.088313, 3.078104",\ + "1.159885, 1.440547, 1.729735, 2.224055, 3.213863",\ + "1.509265, 1.789927, 2.079118, 2.573445, 3.563268",\ + "1.264054, 1.572882, 1.847910, 2.339658, 3.325692",\ + "1.306595, 1.615417, 1.890405, 2.382038, 3.367840",\ + "1.362333, 1.671155, 1.946141, 2.437769, 3.423560",\ + "1.498062, 1.806884, 2.081874, 2.573510, 3.559319",\ + "1.847442, 2.156265, 2.431257, 2.922901, 3.908724"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.045780, 0.045773, 0.045733, 0.045626, 0.045413",\ + "0.094908, 0.094902, 0.094864, 0.094767, 0.094572",\ + "0.188970, 0.188970, 0.188972, 0.188977, 0.188987",\ + "0.443984, 0.443984, 0.443983, 0.443979, 0.443971",\ + "1.101591, 1.101591, 1.101588, 1.101583, 1.101571",\ + "0.045780, 0.045773, 0.045733, 0.045626, 0.045413",\ + "0.094908, 0.094902, 0.094864, 0.094767, 0.094572",\ + "0.188970, 0.188970, 0.188972, 0.188977, 0.188987",\ + "0.443984, 0.443984, 0.443983, 0.443979, 0.443971",\ + "1.101591, 1.101591, 1.101588, 1.101583, 1.101571",\ + "0.045780, 0.045773, 0.045733, 0.045626, 0.045413",\ + "0.094908, 0.094901, 0.094864, 0.094767, 0.094572",\ + "0.188970, 0.188970, 0.188972, 0.188977, 0.188987",\ + "0.443984, 0.443984, 0.443983, 0.443979, 0.443971",\ + "1.101591, 1.101591, 1.101588, 1.101583, 1.101571",\ + "0.045780, 0.045773, 0.045732, 0.045626, 0.045413",\ + "0.094908, 0.094901, 0.094864, 0.094767, 0.094572",\ + "0.188970, 0.188970, 0.188972, 0.188977, 0.188987",\ + "0.443984, 0.443984, 0.443983, 0.443979, 0.443971",\ + "1.101591, 1.101591, 1.101588, 1.101583, 1.101571",\ + "0.045780, 0.045771, 0.045731, 0.045626, 0.045413",\ + "0.094908, 0.094899, 0.094863, 0.094766, 0.094572",\ + "0.188970, 0.188970, 0.188972, 0.188977, 0.188987",\ + "0.443984, 0.443984, 0.443983, 0.443979, 0.443971",\ + "1.101591, 1.101591, 1.101588, 1.101583, 1.101571"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_2564*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[42]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.720239, 0.982131, 1.267428, 1.744868, 2.699749",\ + "0.766471, 1.028363, 1.313660, 1.791102, 2.745986",\ + "0.850698, 1.112590, 1.397886, 1.875327, 2.830208",\ + "1.071623, 1.333515, 1.618809, 2.096245, 3.051117",\ + "1.631890, 1.893781, 2.179071, 2.656495, 3.611344",\ + "0.807647, 1.069728, 1.355020, 1.831583, 2.785683",\ + "0.853879, 1.115960, 1.401253, 1.877816, 2.831920",\ + "0.938106, 1.200187, 1.485479, 1.962041, 2.916142",\ + "1.159031, 1.421112, 1.706402, 2.182960, 3.137051",\ + "1.719299, 1.981378, 2.266663, 2.743210, 3.697278",\ + "0.888462, 1.158804, 1.442984, 1.919204, 2.872638",\ + "0.934694, 1.205035, 1.489217, 1.965438, 2.918875",\ + "1.018921, 1.289262, 1.573443, 2.049663, 3.003097",\ + "1.239846, 1.510187, 1.794366, 2.270581, 3.224006",\ + "1.800113, 2.070453, 2.354627, 2.830831, 3.784233",\ + "0.949702, 1.224575, 1.507125, 1.983117, 2.936147",\ + "0.995934, 1.270807, 1.553358, 2.029351, 2.982384",\ + "1.080161, 1.355034, 1.637584, 2.113576, 3.066606",\ + "1.301086, 1.575958, 1.858507, 2.334494, 3.287515",\ + "1.861354, 2.136225, 2.418768, 2.894744, 3.847742",\ + "1.285416, 1.590595, 1.859077, 2.332497, 3.281603",\ + "1.331648, 1.636827, 1.905309, 2.378731, 3.327840",\ + "1.415875, 1.721054, 1.989536, 2.462955, 3.412062",\ + "1.636800, 1.941979, 2.210458, 2.683874, 3.632971",\ + "2.197067, 2.502244, 2.770720, 3.244124, 4.193198"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.053086, 0.053088, 0.053097, 0.053119, 0.053163",\ + "0.178912, 0.178915, 0.178931, 0.178968, 0.179043",\ + "0.381897, 0.381898, 0.381905, 0.381923, 0.381957",\ + "0.885390, 0.885384, 0.885350, 0.885270, 0.885109",\ + "2.163185, 2.163195, 2.163244, 2.163362, 2.163599",\ + "0.053086, 0.053088, 0.053097, 0.053119, 0.053163",\ + "0.178912, 0.178915, 0.178931, 0.178968, 0.179043",\ + "0.381897, 0.381898, 0.381905, 0.381923, 0.381957",\ + "0.885390, 0.885384, 0.885350, 0.885270, 0.885109",\ + "2.163185, 2.163195, 2.163244, 2.163362, 2.163599",\ + "0.053086, 0.053088, 0.053097, 0.053119, 0.053163",\ + "0.178912, 0.178916, 0.178931, 0.178968, 0.179043",\ + "0.381897, 0.381898, 0.381905, 0.381923, 0.381957",\ + "0.885390, 0.885383, 0.885350, 0.885270, 0.885109",\ + "2.163185, 2.163195, 2.163244, 2.163362, 2.163599",\ + "0.053086, 0.053088, 0.053097, 0.053119, 0.053163",\ + "0.178912, 0.178916, 0.178931, 0.178968, 0.179043",\ + "0.381897, 0.381898, 0.381905, 0.381923, 0.381957",\ + "0.885390, 0.885383, 0.885350, 0.885270, 0.885109",\ + "2.163185, 2.163195, 2.163244, 2.163362, 2.163599",\ + "0.053086, 0.053088, 0.053097, 0.053119, 0.053163",\ + "0.178912, 0.178917, 0.178931, 0.178968, 0.179043",\ + "0.381897, 0.381899, 0.381906, 0.381923, 0.381957",\ + "0.885390, 0.885381, 0.885349, 0.885270, 0.885109",\ + "2.163185, 2.163199, 2.163245, 2.163363, 2.163599"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.669399, 0.931295, 1.216611, 1.694099, 2.649075",\ + "0.711939, 0.973832, 1.259127, 1.736565, 2.691442",\ + "0.767677, 1.029569, 1.314863, 1.792297, 2.747166",\ + "0.903406, 1.165299, 1.450595, 1.928036, 2.882917",\ + "1.252786, 1.514679, 1.799978, 2.277424, 3.232316",\ + "0.756807, 1.018892, 1.304204, 1.780813, 2.735009",\ + "0.799348, 1.061428, 1.346719, 1.823279, 2.777375",\ + "0.855086, 1.117166, 1.402455, 1.879012, 2.833100",\ + "0.990815, 1.252895, 1.538187, 2.014750, 2.968851",\ + "1.340194, 1.602276, 1.887570, 2.364138, 3.318250",\ + "0.837622, 1.107967, 1.392168, 1.868435, 2.821964",\ + "0.880162, 1.150504, 1.434683, 1.910901, 2.864330",\ + "0.935900, 1.206241, 1.490419, 1.966633, 2.920055",\ + "1.071629, 1.341971, 1.626151, 2.102372, 3.055806",\ + "1.421009, 1.691351, 1.975534, 2.451760, 3.405205",\ + "0.898862, 1.173739, 1.456309, 1.932348, 2.885473",\ + "0.941403, 1.216275, 1.498824, 1.974814, 2.927839",\ + "0.997141, 1.272013, 1.554560, 2.030546, 2.983564",\ + "1.132869, 1.407742, 1.690292, 2.166285, 3.119315",\ + "1.482249, 1.757123, 2.039675, 2.515673, 3.468714",\ + "1.234576, 1.539761, 1.808261, 2.281728, 3.230929",\ + "1.277116, 1.582295, 1.850776, 2.324194, 3.273295",\ + "1.332854, 1.638033, 1.906512, 2.379926, 3.329020",\ + "1.468583, 1.773762, 2.042244, 2.515665, 3.464771",\ + "1.817963, 2.123143, 2.391627, 2.865052, 3.814170"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.045779, 0.045773, 0.045741, 0.045663, 0.045507",\ + "0.094907, 0.094901, 0.094871, 0.094800, 0.094658",\ + "0.188970, 0.188970, 0.188972, 0.188975, 0.188983",\ + "0.443984, 0.443984, 0.443983, 0.443980, 0.443975",\ + "1.101591, 1.101591, 1.101589, 1.101584, 1.101576",\ + "0.045779, 0.045773, 0.045740, 0.045663, 0.045507",\ + "0.094907, 0.094901, 0.094871, 0.094800, 0.094658",\ + "0.188970, 0.188970, 0.188972, 0.188975, 0.188983",\ + "0.443984, 0.443984, 0.443983, 0.443980, 0.443975",\ + "1.101591, 1.101591, 1.101589, 1.101584, 1.101576",\ + "0.045779, 0.045773, 0.045740, 0.045663, 0.045507",\ + "0.094907, 0.094901, 0.094871, 0.094800, 0.094658",\ + "0.188970, 0.188970, 0.188972, 0.188975, 0.188983",\ + "0.443984, 0.443984, 0.443983, 0.443980, 0.443975",\ + "1.101591, 1.101591, 1.101589, 1.101584, 1.101576",\ + "0.045779, 0.045772, 0.045740, 0.045663, 0.045507",\ + "0.094907, 0.094901, 0.094871, 0.094800, 0.094658",\ + "0.188970, 0.188970, 0.188972, 0.188975, 0.188983",\ + "0.443984, 0.443984, 0.443983, 0.443980, 0.443975",\ + "1.101591, 1.101591, 1.101589, 1.101584, 1.101576",\ + "0.045779, 0.045770, 0.045740, 0.045662, 0.045507",\ + "0.094907, 0.094898, 0.094871, 0.094800, 0.094658",\ + "0.188970, 0.188970, 0.188972, 0.188975, 0.188983",\ + "0.443984, 0.443984, 0.443983, 0.443980, 0.443975",\ + "1.101591, 1.101590, 1.101589, 1.101584, 1.101576"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_2515*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[45]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011"); + values ( "0.505424, 0.768046, 1.055041, 1.540850, 2.512468",\ + "0.551960, 0.814596, 1.101656, 1.587624, 2.559559",\ + "0.637620, 0.900293, 1.187543, 1.673963, 2.646803",\ + "0.860979, 1.123711, 1.411252, 1.898370, 2.872607",\ + "1.424976, 1.687784, 1.975705, 2.463734, 3.439793",\ + "0.593483, 0.855643, 1.142658, 1.627564, 2.598402",\ + "0.640020, 0.902192, 1.189274, 1.674337, 2.645493",\ + "0.725680, 0.987891, 1.275163, 1.760677, 2.732737",\ + "0.949039, 1.211309, 1.498873, 1.985084, 2.958541",\ + "1.513036, 1.775383, 2.063330, 2.550448, 3.525727",\ + "0.682045, 0.944707, 1.230622, 1.715185, 2.685357",\ + "0.728581, 0.991257, 1.277238, 1.761959, 2.732448",\ + "0.814241, 1.076956, 1.363127, 1.848298, 2.819692",\ + "1.037599, 1.300375, 1.586838, 2.072705, 3.045496",\ + "1.601596, 1.864452, 2.151294, 2.638070, 3.612682",\ + "0.745042, 1.010463, 1.294765, 1.779098, 2.748866",\ + "0.791578, 1.057013, 1.341381, 1.825872, 2.795957",\ + "0.877238, 1.142714, 1.427269, 1.912211, 2.883201",\ + "1.100596, 1.366135, 1.650980, 2.136618, 3.109005",\ + "1.664593, 1.930213, 2.215437, 2.701982, 3.676191",\ + "1.077301, 1.376325, 1.646801, 2.128510, 3.094322",\ + "1.123837, 1.422881, 1.693418, 2.175285, 3.141412",\ + "1.209496, 1.508595, 1.779311, 2.261626, 3.228657",\ + "1.432853, 1.732038, 2.003029, 2.486036, 3.454461",\ + "1.996848, 2.296144, 2.567495, 3.051404, 4.021647"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011"); + values ( "0.052246, 0.052286, 0.053457, 0.057279, 0.064922",\ + "0.174390, 0.174392, 0.174392, 0.174392, 0.174392",\ + "0.378101, 0.378105, 0.378105, 0.378105, 0.378105",\ + "0.885463, 0.885472, 0.885472, 0.885472, 0.885472",\ + "2.163077, 2.163087, 2.163255, 2.163786, 2.164848",\ + "0.052246, 0.052286, 0.053469, 0.057279, 0.064922",\ + "0.174390, 0.174392, 0.174392, 0.174392, 0.174392",\ + "0.378101, 0.378105, 0.378105, 0.378105, 0.378105",\ + "0.885464, 0.885472, 0.885472, 0.885472, 0.885472",\ + "2.163077, 2.163087, 2.163257, 2.163786, 2.164848",\ + "0.052246, 0.052287, 0.053469, 0.057279, 0.064922",\ + "0.174390, 0.174392, 0.174392, 0.174392, 0.174392",\ + "0.378102, 0.378105, 0.378105, 0.378105, 0.378105",\ + "0.885464, 0.885472, 0.885472, 0.885472, 0.885472",\ + "2.163077, 2.163087, 2.163257, 2.163786, 2.164848",\ + "0.052246, 0.052288, 0.053470, 0.057279, 0.064922",\ + "0.174390, 0.174392, 0.174392, 0.174392, 0.174392",\ + "0.378102, 0.378105, 0.378105, 0.378105, 0.378105",\ + "0.885465, 0.885472, 0.885472, 0.885472, 0.885472",\ + "2.163077, 2.163087, 2.163257, 2.163786, 2.164848",\ + "0.052246, 0.052302, 0.053509, 0.057295, 0.064922",\ + "0.174391, 0.174392, 0.174392, 0.174392, 0.174392",\ + "0.378103, 0.378105, 0.378105, 0.378105, 0.378105",\ + "0.885469, 0.885472, 0.885472, 0.885472, 0.885472",\ + "2.163077, 2.163090, 2.163262, 2.163788, 2.164848"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011"); + values ( "0.443684, 0.706121, 0.992534, 1.477296, 2.446822",\ + "0.497094, 0.759709, 1.046667, 1.532387, 2.503829",\ + "0.557938, 0.820691, 1.108342, 1.595724, 2.570488",\ + "0.692641, 0.955383, 1.242975, 1.730217, 2.704702",\ + "1.039101, 1.301772, 1.589012, 2.075409, 3.048203",\ + "0.531743, 0.793716, 1.080148, 1.564010, 2.532755",\ + "0.585154, 0.847306, 1.134284, 1.619101, 2.589763",\ + "0.645997, 0.908289, 1.195965, 1.682438, 2.656422",\ + "0.780700, 1.042981, 1.330598, 1.816931, 2.790636",\ + "1.127160, 1.389370, 1.676632, 2.162122, 3.134136",\ + "0.620305, 0.882776, 1.168112, 1.651631, 2.619710",\ + "0.673715, 0.936370, 1.222248, 1.706723, 2.676718",\ + "0.734558, 0.997357, 1.283929, 1.770059, 2.743377",\ + "0.869261, 1.132048, 1.418562, 1.904553, 2.877591",\ + "1.215722, 1.478435, 1.764596, 2.249744, 3.221091",\ + "0.683303, 0.948526, 1.232255, 1.715544, 2.683219",\ + "0.736712, 1.002125, 1.286391, 1.770636, 2.740227",\ + "0.797555, 1.063117, 1.348072, 1.833972, 2.806886",\ + "0.932258, 1.197807, 1.482705, 1.968466, 2.941100",\ + "1.278719, 1.544192, 1.828738, 2.313657, 3.284600",\ + "1.015567, 1.314320, 1.584279, 2.064952, 3.028676",\ + "1.068972, 1.367985, 1.638425, 2.120048, 3.085683",\ + "1.129811, 1.429028, 1.700123, 2.183391, 3.152342",\ + "1.264514, 1.563714, 1.834755, 2.317884, 3.286556",\ + "1.610977, 1.910073, 2.180780, 2.663072, 3.630056"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011"); + values ( "0.060218, 0.060490, 0.061813, 0.065017, 0.071424",\ + "0.114238, 0.114613, 0.116413, 0.120756, 0.129442",\ + "0.199921, 0.200263, 0.201907, 0.205872, 0.213802",\ + "0.445513, 0.445551, 0.445735, 0.446179, 0.447066",\ + "1.101424, 1.101424, 1.101424, 1.101424, 1.101424",\ + "0.060218, 0.060493, 0.061823, 0.065017, 0.071424",\ + "0.114238, 0.114616, 0.116427, 0.120756, 0.129442",\ + "0.199921, 0.200266, 0.201919, 0.205872, 0.213802",\ + "0.445513, 0.445551, 0.445736, 0.446179, 0.447066",\ + "1.101424, 1.101424, 1.101424, 1.101424, 1.101424",\ + "0.060218, 0.060498, 0.061824, 0.065017, 0.071424",\ + "0.114238, 0.114624, 0.116427, 0.120756, 0.129442",\ + "0.199921, 0.200273, 0.201920, 0.205872, 0.213802",\ + "0.445513, 0.445552, 0.445736, 0.446179, 0.447066",\ + "1.101424, 1.101424, 1.101424, 1.101424, 1.101424",\ + "0.060218, 0.060507, 0.061824, 0.065017, 0.071424",\ + "0.114238, 0.114635, 0.116428, 0.120756, 0.129442",\ + "0.199921, 0.200284, 0.201920, 0.205872, 0.213802",\ + "0.445513, 0.445553, 0.445737, 0.446179, 0.447066",\ + "1.101424, 1.101424, 1.101424, 1.101424, 1.101424",\ + "0.060218, 0.060603, 0.061857, 0.065030, 0.071424",\ + "0.114238, 0.114768, 0.116472, 0.120774, 0.129442",\ + "0.199921, 0.200405, 0.201961, 0.205888, 0.213802",\ + "0.445513, 0.445567, 0.445741, 0.446180, 0.447066",\ + "1.101424, 1.101424, 1.101424, 1.101424, 1.101424"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_2700*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[16]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011"); + values ( "0.378256, 0.565826, 0.756593, 1.054119, 1.624836",\ + "0.428118, 0.615688, 0.806455, 1.103981, 1.674699",\ + "0.529986, 0.717556, 0.908323, 1.205849, 1.776567",\ + "0.767847, 0.955417, 1.146184, 1.443710, 2.014428",\ + "1.340168, 1.527737, 1.718505, 2.016031, 2.586749",\ + "0.466466, 0.653144, 0.843873, 1.141424, 1.712190",\ + "0.516328, 0.703006, 0.893736, 1.191286, 1.762052",\ + "0.618195, 0.804874, 0.995604, 1.293154, 1.863920",\ + "0.856057, 1.042735, 1.233465, 1.531015, 2.101782",\ + "1.428377, 1.615056, 1.805786, 2.103336, 2.674102",\ + "0.553983, 0.733479, 0.923900, 1.221452, 1.792222",\ + "0.603845, 0.783341, 0.973763, 1.271315, 1.842084",\ + "0.705713, 0.885209, 1.075631, 1.373183, 1.943952",\ + "0.943574, 1.123071, 1.313492, 1.611044, 2.181813",\ + "1.515895, 1.695391, 1.885813, 2.183364, 2.754134",\ + "0.611623, 0.791310, 0.981624, 1.278894, 1.849260",\ + "0.661485, 0.841172, 1.031486, 1.328757, 1.899123",\ + "0.763353, 0.943040, 1.133354, 1.430624, 2.000991",\ + "1.001214, 1.180901, 1.371215, 1.668486, 2.238852",\ + "1.573535, 1.753222, 1.943536, 2.240806, 2.811173",\ + "0.913876, 1.096638, 1.285285, 1.582076, 2.151510",\ + "0.963738, 1.146500, 1.335147, 1.631939, 2.201373",\ + "1.065606, 1.248368, 1.437015, 1.733807, 2.303241",\ + "1.303467, 1.486229, 1.674876, 1.971668, 2.541102",\ + "1.875787, 2.058550, 2.247197, 2.543989, 3.113423"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011"); + values ( "0.039802, 0.039802, 0.039803, 0.039804, 0.039804",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375009, 0.375009, 0.375009, 0.375009, 0.375009",\ + "0.869291, 0.869291, 0.869292, 0.869292, 0.869292",\ + "2.137192, 2.137192, 2.137192, 2.137192, 2.137192",\ + "0.039802, 0.039802, 0.039803, 0.039804, 0.039804",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375009, 0.375009, 0.375009, 0.375009, 0.375009",\ + "0.869291, 0.869291, 0.869292, 0.869292, 0.869292",\ + "2.137192, 2.137192, 2.137192, 2.137192, 2.137192",\ + "0.039802, 0.039802, 0.039803, 0.039804, 0.039804",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375009, 0.375009, 0.375009, 0.375009, 0.375009",\ + "0.869291, 0.869291, 0.869292, 0.869292, 0.869292",\ + "2.137192, 2.137192, 2.137192, 2.137192, 2.137192",\ + "0.039802, 0.039802, 0.039803, 0.039804, 0.039804",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375009, 0.375009, 0.375009, 0.375009, 0.375009",\ + "0.869291, 0.869291, 0.869292, 0.869292, 0.869292",\ + "2.137192, 2.137192, 2.137192, 2.137192, 2.137192",\ + "0.039802, 0.039802, 0.039803, 0.039804, 0.039804",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375009, 0.375009, 0.375009, 0.375009, 0.375009",\ + "0.869291, 0.869291, 0.869292, 0.869292, 0.869292",\ + "2.137192, 2.137192, 2.137192, 2.137192, 2.137192"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011"); + values ( "0.406562, 0.606556, 0.797323, 1.091399, 1.653630",\ + "0.441336, 0.628906, 0.819673, 1.117199, 1.687917",\ + "0.482700, 0.670269, 0.861036, 1.158563, 1.729280",\ + "0.604735, 0.792305, 0.983072, 1.280598, 1.851316",\ + "0.936348, 1.123917, 1.314685, 1.612211, 2.182929",\ + "0.494915, 0.693874, 0.884604, 1.178704, 1.740983",\ + "0.529546, 0.716224, 0.906954, 1.204504, 1.775270",\ + "0.570909, 0.757588, 0.948317, 1.245868, 1.816634",\ + "0.692944, 0.879623, 1.070353, 1.367903, 1.938669",\ + "1.024557, 1.211236, 1.401965, 1.699516, 2.270282",\ + "0.583845, 0.774209, 0.964631, 1.258732, 1.821015",\ + "0.617063, 0.796559, 0.986981, 1.284533, 1.855302",\ + "0.658427, 0.837923, 1.028344, 1.325896, 1.896666",\ + "0.780462, 0.959958, 1.150380, 1.447932, 2.018701",\ + "1.112075, 1.291571, 1.481992, 1.779544, 2.350314",\ + "0.646974, 0.832040, 1.022354, 1.316164, 1.878034",\ + "0.674703, 0.854390, 1.044704, 1.341975, 1.912341",\ + "0.716066, 0.895753, 1.086067, 1.383338, 1.953704",\ + "0.838102, 1.017789, 1.208103, 1.505373, 2.075740",\ + "1.169714, 1.349402, 1.539716, 1.836986, 2.407352",\ + "0.954606, 1.137368, 1.326015, 1.619337, 2.180259",\ + "0.976956, 1.159718, 1.348365, 1.645157, 2.214591",\ + "1.018319, 1.201081, 1.389728, 1.686520, 2.255954",\ + "1.140355, 1.323117, 1.511764, 1.808556, 2.377990",\ + "1.471967, 1.654730, 1.843377, 2.140168, 2.709602"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011"); + values ( "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\ + "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\ + "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\ + "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\ + "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_min_2509*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[18]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.377666, 0.597755, 0.775019, 1.063430, 1.623644",\ + "0.425426, 0.645514, 0.822779, 1.111188, 1.671399",\ + "0.527520, 0.747609, 0.924873, 1.213283, 1.773495",\ + "0.765177, 0.985265, 1.162530, 1.450942, 2.011159",\ + "1.337186, 1.557274, 1.734539, 2.022954, 2.583179",\ + "0.466063, 0.685073, 0.862300, 1.150735, 1.710998",\ + "0.513823, 0.732832, 0.910060, 1.198493, 1.758752",\ + "0.615917, 0.834927, 1.012154, 1.300588, 1.860848",\ + "0.853574, 1.072584, 1.249811, 1.538247, 2.098513",\ + "1.425583, 1.644592, 1.821819, 2.110259, 2.670533",\ + "0.555414, 0.765406, 0.942327, 1.230764, 1.791029",\ + "0.603174, 0.813165, 0.990086, 1.278522, 1.838784",\ + "0.705268, 0.915260, 1.092181, 1.380617, 1.940880",\ + "0.942925, 1.152916, 1.329838, 1.618276, 2.178544",\ + "1.514933, 1.724925, 1.901846, 2.190288, 2.750564",\ + "0.619064, 0.823222, 1.000019, 1.288193, 1.848044",\ + "0.666823, 0.870981, 1.047778, 1.335951, 1.895798",\ + "0.768918, 0.973076, 1.149873, 1.438046, 1.997895",\ + "1.006574, 1.210732, 1.387530, 1.675705, 2.235559",\ + "1.578583, 1.782741, 1.959538, 2.247717, 2.807579",\ + "0.950146, 1.128438, 1.303674, 1.591364, 2.150265",\ + "0.997905, 1.176197, 1.351434, 1.639122, 2.198019",\ + "1.100000, 1.278292, 1.453528, 1.741217, 2.300115",\ + "1.337656, 1.515949, 1.691185, 1.978876, 2.537780",\ + "1.909665, 2.087957, 2.263194, 2.550888, 3.109800"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.035377, 0.035377, 0.035377, 0.035399, 0.035455",\ + "0.147294, 0.147294, 0.147294, 0.147285, 0.147262",\ + "0.375697, 0.375697, 0.375697, 0.375693, 0.375682",\ + "0.871174, 0.871174, 0.871174, 0.871174, 0.871174",\ + "2.136600, 2.136600, 2.136600, 2.136600, 2.136600",\ + "0.035377, 0.035377, 0.035377, 0.035399, 0.035455",\ + "0.147294, 0.147294, 0.147294, 0.147285, 0.147262",\ + "0.375697, 0.375697, 0.375697, 0.375693, 0.375682",\ + "0.871174, 0.871174, 0.871174, 0.871174, 0.871174",\ + "2.136600, 2.136600, 2.136600, 2.136600, 2.136600",\ + "0.035377, 0.035377, 0.035377, 0.035399, 0.035455",\ + "0.147294, 0.147294, 0.147294, 0.147285, 0.147262",\ + "0.375697, 0.375697, 0.375697, 0.375693, 0.375682",\ + "0.871174, 0.871174, 0.871174, 0.871174, 0.871174",\ + "2.136600, 2.136600, 2.136600, 2.136600, 2.136600",\ + "0.035377, 0.035377, 0.035377, 0.035399, 0.035455",\ + "0.147294, 0.147294, 0.147294, 0.147285, 0.147262",\ + "0.375697, 0.375697, 0.375697, 0.375693, 0.375681",\ + "0.871174, 0.871174, 0.871174, 0.871174, 0.871174",\ + "2.136600, 2.136600, 2.136600, 2.136600, 2.136600",\ + "0.035377, 0.035377, 0.035377, 0.035400, 0.035455",\ + "0.147294, 0.147294, 0.147294, 0.147285, 0.147262",\ + "0.375697, 0.375697, 0.375697, 0.375693, 0.375681",\ + "0.871174, 0.871174, 0.871174, 0.871174, 0.871174",\ + "2.136600, 2.136600, 2.136600, 2.136600, 2.136600"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.402575, 0.622525, 0.800017, 1.088497, 1.648804",\ + "0.437980, 0.658068, 0.835333, 1.123750, 1.683980",\ + "0.479393, 0.699481, 0.876745, 1.165163, 1.725394",\ + "0.601610, 0.821698, 0.998963, 1.287380, 1.847608",\ + "0.933557, 1.153646, 1.330910, 1.619324, 2.179546",\ + "0.490972, 0.709843, 0.887297, 1.175802, 1.736157",\ + "0.526376, 0.745386, 0.922613, 1.211055, 1.771333",\ + "0.567789, 0.786799, 0.964026, 1.252468, 1.812747",\ + "0.690007, 0.909017, 1.086244, 1.374685, 1.934961",\ + "1.021954, 1.240964, 1.418191, 1.706629, 2.266899",\ + "0.580323, 0.790176, 0.967324, 1.255831, 1.816189",\ + "0.615727, 0.825719, 1.002640, 1.291084, 1.851365",\ + "0.657140, 0.867132, 1.044053, 1.332497, 1.892779",\ + "0.779358, 0.989349, 1.166271, 1.454713, 2.014993",\ + "1.111305, 1.321296, 1.498218, 1.786658, 2.346931",\ + "0.643973, 0.848003, 1.025017, 1.313260, 1.873204",\ + "0.679377, 0.883535, 1.060332, 1.348513, 1.908380",\ + "0.720790, 0.924948, 1.101745, 1.389926, 1.949794",\ + "0.843007, 1.047165, 1.223963, 1.512143, 2.072008",\ + "1.174954, 1.379112, 1.555910, 1.844087, 2.403945",\ + "0.972398, 1.153296, 1.328672, 1.616431, 2.175425",\ + "1.010459, 1.188751, 1.363988, 1.651684, 2.210601",\ + "1.051872, 1.230164, 1.405401, 1.693097, 2.252014",\ + "1.174089, 1.352381, 1.527618, 1.815314, 2.374228",\ + "1.506037, 1.684329, 1.859565, 2.147258, 2.706166"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.039065, 0.039065, 0.039065, 0.039064, 0.039061",\ + "0.088924, 0.088924, 0.088924, 0.088923, 0.088920",\ + "0.185901, 0.185901, 0.185901, 0.185900, 0.185897",\ + "0.432264, 0.432264, 0.432264, 0.432263, 0.432260",\ + "1.064285, 1.064285, 1.064285, 1.064278, 1.064261",\ + "0.039065, 0.039065, 0.039065, 0.039064, 0.039061",\ + "0.088924, 0.088924, 0.088924, 0.088923, 0.088920",\ + "0.185901, 0.185901, 0.185901, 0.185900, 0.185897",\ + "0.432264, 0.432264, 0.432264, 0.432263, 0.432260",\ + "1.064285, 1.064285, 1.064285, 1.064278, 1.064261",\ + "0.039065, 0.039065, 0.039065, 0.039064, 0.039061",\ + "0.088924, 0.088924, 0.088924, 0.088923, 0.088920",\ + "0.185901, 0.185901, 0.185901, 0.185900, 0.185897",\ + "0.432264, 0.432264, 0.432264, 0.432263, 0.432260",\ + "1.064285, 1.064285, 1.064285, 1.064278, 1.064261",\ + "0.039065, 0.039065, 0.039065, 0.039064, 0.039061",\ + "0.088924, 0.088924, 0.088924, 0.088923, 0.088920",\ + "0.185901, 0.185901, 0.185901, 0.185900, 0.185897",\ + "0.432264, 0.432264, 0.432264, 0.432263, 0.432260",\ + "1.064285, 1.064285, 1.064285, 1.064278, 1.064261",\ + "0.039065, 0.039065, 0.039065, 0.039064, 0.039061",\ + "0.088924, 0.088924, 0.088924, 0.088923, 0.088920",\ + "0.185901, 0.185901, 0.185901, 0.185900, 0.185897",\ + "0.432264, 0.432264, 0.432264, 0.432263, 0.432260",\ + "1.064285, 1.064285, 1.064285, 1.064278, 1.064261"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_min_2574*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[21]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011"); + values ( "0.170596, 0.344816, 0.534412, 0.834679, 1.413369",\ + "0.220441, 0.410383, 0.608141, 0.926922, 1.543926",\ + "0.296778, 0.497025, 0.695631, 1.028154, 1.678015",\ + "0.503693, 0.714118, 0.910633, 1.258044, 1.946084",\ + "1.056578, 1.269082, 1.463888, 1.813508, 2.508415",\ + "0.258804, 0.432134, 0.621693, 0.921985, 1.500723",\ + "0.308666, 0.497701, 0.695422, 1.014227, 1.631279",\ + "0.385015, 0.584343, 0.782912, 1.115460, 1.765368",\ + "0.591916, 0.801436, 0.997914, 1.345350, 2.033438",\ + "1.144755, 1.356400, 1.551169, 1.900813, 2.595769",\ + "0.340291, 0.512462, 0.701720, 1.002013, 1.580754",\ + "0.397987, 0.578029, 0.775449, 1.094256, 1.711311",\ + "0.474366, 0.664671, 0.862939, 1.195488, 1.845400",\ + "0.681230, 0.881765, 1.077941, 1.425378, 2.113470",\ + "1.233925, 1.436728, 1.631195, 1.980842, 2.675800",\ + "0.397929, 0.570271, 0.759443, 1.059465, 1.637816",\ + "0.461810, 0.635841, 0.833191, 1.151754, 1.768465",\ + "0.538221, 0.722485, 0.920682, 1.253027, 1.902633",\ + "0.745047, 0.939586, 1.135680, 1.482963, 2.170795",\ + "1.297604, 1.494552, 1.688930, 2.038435, 2.733142",\ + "0.700648, 0.875417, 1.063102, 1.362655, 1.940093",\ + "0.765372, 0.941013, 1.136853, 1.454984, 2.070854",\ + "0.851488, 1.027673, 1.224345, 1.556291, 2.205118",\ + "1.066931, 1.244823, 1.439341, 1.786267, 2.473392",\ + "1.621222, 1.799810, 1.992591, 2.341746, 3.035759"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011"); + values ( "0.138974, 0.138974, 0.138974, 0.148690, 0.172413",\ + "0.231167, 0.231167, 0.231167, 0.238024, 0.254767",\ + "0.397287, 0.397287, 0.397287, 0.400375, 0.407916",\ + "0.872440, 0.873368, 0.873689, 0.874395, 0.875876",\ + "2.139579, 2.140538, 2.140572, 2.140672, 2.140918",\ + "0.138974, 0.138974, 0.138974, 0.148690, 0.172413",\ + "0.231167, 0.231167, 0.231167, 0.238024, 0.254767",\ + "0.397287, 0.397287, 0.397287, 0.400375, 0.407916",\ + "0.872464, 0.873368, 0.873689, 0.874395, 0.875876",\ + "2.139603, 2.140538, 2.140572, 2.140672, 2.140918",\ + "0.138974, 0.138974, 0.138974, 0.148690, 0.172413",\ + "0.231167, 0.231167, 0.231167, 0.238024, 0.254767",\ + "0.397287, 0.397287, 0.397287, 0.400375, 0.407916",\ + "0.872536, 0.873368, 0.873689, 0.874395, 0.875876",\ + "2.139678, 2.140538, 2.140572, 2.140672, 2.140918",\ + "0.138974, 0.138974, 0.138974, 0.148719, 0.172470",\ + "0.231167, 0.231167, 0.231167, 0.238044, 0.254807",\ + "0.397287, 0.397287, 0.397287, 0.400384, 0.407935",\ + "0.872605, 0.873372, 0.873689, 0.874397, 0.875879",\ + "2.139749, 2.140541, 2.140572, 2.140673, 2.140918",\ + "0.138974, 0.138974, 0.138974, 0.148743, 0.172540",\ + "0.231167, 0.231167, 0.231167, 0.238062, 0.254856",\ + "0.397287, 0.397287, 0.397287, 0.400392, 0.407957",\ + "0.872560, 0.873396, 0.873689, 0.874398, 0.875884",\ + "2.139703, 2.140566, 2.140572, 2.140673, 2.140919"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011"); + values ( "0.114526, 0.367093, 0.558483, 0.861637, 1.446138",\ + "0.150625, 0.396446, 0.587679, 0.892767, 1.482109",\ + "0.204730, 0.442254, 0.633143, 0.939029, 1.530580",\ + "0.336119, 0.565619, 0.755974, 1.061799, 1.653613",\ + "0.673349, 0.896842, 1.086112, 1.390772, 1.980608",\ + "0.202682, 0.454411, 0.645764, 0.948942, 1.533492",\ + "0.238886, 0.483764, 0.674960, 0.980073, 1.569463",\ + "0.292968, 0.529572, 0.720424, 1.026334, 1.617934",\ + "0.424327, 0.652937, 0.843255, 1.149104, 1.740967",\ + "0.761530, 0.984159, 1.173393, 1.478077, 2.067961",\ + "0.291788, 0.534739, 0.725791, 1.028971, 1.613523",\ + "0.328316, 0.564093, 0.754987, 1.060101, 1.649494",\ + "0.382328, 0.609901, 0.800451, 1.106363, 1.697965",\ + "0.513590, 0.733265, 0.923281, 1.229132, 1.820998",\ + "0.850714, 1.064488, 1.253420, 1.558105, 2.147993",\ + "0.355407, 0.592582, 0.783517, 1.086430, 1.670599",\ + "0.392245, 0.621934, 0.812712, 1.117566, 1.706581",\ + "0.446190, 0.667738, 0.858175, 1.163830, 1.755058",\ + "0.577359, 0.791098, 0.981005, 1.286600, 1.878091",\ + "0.914407, 1.122314, 1.311141, 1.615571, 2.205081",\ + "0.691600, 0.897972, 1.087176, 1.389626, 1.972893",\ + "0.730424, 0.927308, 1.116372, 1.420767, 2.008889",\ + "0.783940, 0.973087, 1.161835, 1.467034, 2.057372",\ + "0.914518, 1.096413, 1.284664, 1.589804, 2.180407",\ + "1.248497, 1.427586, 1.614800, 1.918772, 2.507391"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011"); + values ( "0.055015, 0.067358, 0.073977, 0.088785, 0.119708",\ + "0.104870, 0.104870, 0.106669, 0.116295, 0.138275",\ + "0.190674, 0.190674, 0.191255, 0.196129, 0.207539",\ + "0.432841, 0.433934, 0.434139, 0.435063, 0.437176",\ + "1.062723, 1.062723, 1.063223, 1.064130, 1.065922",\ + "0.055327, 0.067358, 0.073977, 0.088785, 0.119708",\ + "0.104870, 0.104870, 0.106669, 0.116295, 0.138275",\ + "0.190674, 0.190674, 0.191255, 0.196129, 0.207539",\ + "0.432868, 0.433934, 0.434139, 0.435063, 0.437176",\ + "1.062723, 1.062723, 1.063223, 1.064130, 1.065922",\ + "0.056284, 0.067358, 0.073977, 0.088785, 0.119708",\ + "0.104870, 0.104870, 0.106669, 0.116295, 0.138275",\ + "0.190674, 0.190674, 0.191255, 0.196129, 0.207539",\ + "0.432953, 0.433934, 0.434139, 0.435063, 0.437176",\ + "1.062723, 1.062723, 1.063223, 1.064130, 1.065922",\ + "0.057202, 0.067404, 0.073991, 0.088823, 0.119782",\ + "0.104870, 0.104870, 0.106673, 0.116322, 0.138328",\ + "0.190674, 0.190674, 0.191256, 0.196143, 0.207567",\ + "0.433035, 0.433938, 0.434140, 0.435065, 0.437181",\ + "1.062723, 1.062723, 1.063224, 1.064132, 1.065926",\ + "0.063074, 0.067726, 0.073994, 0.088855, 0.119873",\ + "0.104870, 0.104870, 0.106674, 0.116345, 0.138392",\ + "0.190674, 0.190674, 0.191256, 0.196155, 0.207600",\ + "0.433555, 0.433967, 0.434140, 0.435067, 0.437187",\ + "1.062723, 1.062723, 1.063224, 1.064134, 1.065932"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_min_2723*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[24]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011"); + values ( "0.357397, 0.601995, 0.794649, 1.097312, 1.679722",\ + "0.405158, 0.649756, 0.842409, 1.145087, 1.727533",\ + "0.507252, 0.751850, 0.944504, 1.247180, 1.829623",\ + "0.744907, 0.989505, 1.182159, 1.483890, 2.064025",\ + "1.316914, 1.559947, 1.747496, 2.046616, 2.624655",\ + "0.445689, 0.689313, 0.881930, 1.184617, 1.767075",\ + "0.493449, 0.737074, 0.929690, 1.232392, 1.814886",\ + "0.595543, 0.839168, 1.031785, 1.334485, 1.916976",\ + "0.833198, 1.076823, 1.269440, 1.571195, 2.151379",\ + "1.405205, 1.647264, 1.834777, 2.133921, 2.712009",\ + "0.535203, 0.769642, 0.961957, 1.264645, 1.847107",\ + "0.582964, 0.817402, 1.009717, 1.312421, 1.894918",\ + "0.685058, 0.919496, 1.111811, 1.414514, 1.997008",\ + "0.922713, 1.157152, 1.349467, 1.651224, 2.231411",\ + "1.494720, 1.727593, 1.914804, 2.213950, 2.792040",\ + "0.599211, 0.827507, 1.019685, 1.322102, 1.904177",\ + "0.646972, 0.875268, 1.067446, 1.369877, 1.951988",\ + "0.749066, 0.977362, 1.169540, 1.471970, 2.054078",\ + "0.986721, 1.215017, 1.407195, 1.708678, 2.288475",\ + "1.558728, 1.785452, 1.972520, 2.271401, 2.849100",\ + "0.937895, 1.133051, 1.323345, 1.625296, 2.206465",\ + "0.985656, 1.180812, 1.371106, 1.673071, 2.254277",\ + "1.087750, 1.282906, 1.473200, 1.775164, 2.356366",\ + "1.325405, 1.520561, 1.710855, 2.011869, 2.590756",\ + "1.897411, 2.090956, 2.276178, 2.574590, 3.151375"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011"); + values ( "0.035362, 0.035362, 0.035362, 0.035420, 0.035563",\ + "0.147300, 0.147300, 0.147300, 0.147294, 0.147280",\ + "0.375700, 0.375700, 0.375700, 0.375690, 0.375665",\ + "0.871174, 0.871174, 0.871174, 0.871174, 0.871175",\ + "2.136600, 2.136600, 2.136600, 2.136600, 2.136600",\ + "0.035362, 0.035362, 0.035362, 0.035420, 0.035563",\ + "0.147300, 0.147300, 0.147300, 0.147294, 0.147280",\ + "0.375700, 0.375700, 0.375700, 0.375690, 0.375665",\ + "0.871174, 0.871174, 0.871174, 0.871174, 0.871175",\ + "2.136600, 2.136600, 2.136600, 2.136600, 2.136600",\ + "0.035362, 0.035362, 0.035362, 0.035420, 0.035563",\ + "0.147300, 0.147300, 0.147300, 0.147294, 0.147280",\ + "0.375700, 0.375700, 0.375700, 0.375690, 0.375665",\ + "0.871174, 0.871174, 0.871174, 0.871174, 0.871175",\ + "2.136600, 2.136600, 2.136600, 2.136600, 2.136600",\ + "0.035362, 0.035362, 0.035362, 0.035421, 0.035564",\ + "0.147300, 0.147300, 0.147300, 0.147294, 0.147280",\ + "0.375700, 0.375700, 0.375700, 0.375690, 0.375665",\ + "0.871174, 0.871174, 0.871174, 0.871174, 0.871175",\ + "2.136600, 2.136600, 2.136600, 2.136600, 2.136600",\ + "0.035362, 0.035362, 0.035362, 0.035421, 0.035564",\ + "0.147300, 0.147300, 0.147300, 0.147294, 0.147280",\ + "0.375700, 0.375700, 0.375700, 0.375690, 0.375665",\ + "0.871174, 0.871174, 0.871174, 0.871174, 0.871175",\ + "2.136600, 2.136600, 2.136600, 2.136600, 2.136600"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011"); + values ( "0.382270, 0.607170, 0.794344, 1.093466, 1.671509",\ + "0.417706, 0.645645, 0.832819, 1.131939, 1.709979",\ + "0.459119, 0.700449, 0.887937, 1.187057, 1.765097",\ + "0.581337, 0.825935, 1.018589, 1.319527, 1.897724",\ + "0.913286, 1.157884, 1.350538, 1.652760, 2.234094",\ + "0.470573, 0.694488, 0.881625, 1.180771, 1.758862",\ + "0.505998, 0.732962, 0.920100, 1.219244, 1.797333",\ + "0.547411, 0.787767, 0.975218, 1.274362, 1.852450",\ + "0.669629, 0.913253, 1.105870, 1.406832, 1.985077",\ + "1.001577, 1.245202, 1.437819, 1.740065, 2.321447",\ + "0.560124, 0.774817, 0.961652, 1.260799, 1.838894",\ + "0.595513, 0.813291, 1.000127, 1.299273, 1.877364",\ + "0.636925, 0.868096, 1.055245, 1.354391, 1.932482",\ + "0.759143, 0.993582, 1.185897, 1.486860, 2.065109",\ + "1.091092, 1.325531, 1.517846, 1.820093, 2.401479",\ + "0.624166, 0.832637, 1.019369, 1.318251, 1.895954",\ + "0.659520, 0.871112, 1.057843, 1.356724, 1.934424",\ + "0.700933, 0.925949, 1.112961, 1.411842, 1.989542",\ + "0.823151, 1.051447, 1.243625, 1.544312, 2.122169",\ + "1.155100, 1.383396, 1.575574, 1.877549, 2.458546",\ + "0.960128, 1.137870, 1.323027, 1.621440, 2.198229",\ + "0.998204, 1.176344, 1.361501, 1.659913, 2.236699",\ + "1.039617, 1.231408, 1.416619, 1.715032, 2.291817",\ + "1.161835, 1.356991, 1.547285, 1.847501, 2.424445",\ + "1.493784, 1.688940, 1.879234, 2.180742, 2.760831"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011"); + values ( "0.039065, 0.039065, 0.039065, 0.039064, 0.039059",\ + "0.088925, 0.088925, 0.088925, 0.088923, 0.088919",\ + "0.185901, 0.185901, 0.185901, 0.185900, 0.185895",\ + "0.432265, 0.432265, 0.432265, 0.432264, 0.432260",\ + "1.064290, 1.064290, 1.064290, 1.064282, 1.064264",\ + "0.039065, 0.039065, 0.039065, 0.039064, 0.039059",\ + "0.088925, 0.088925, 0.088925, 0.088923, 0.088919",\ + "0.185901, 0.185901, 0.185901, 0.185900, 0.185895",\ + "0.432265, 0.432265, 0.432265, 0.432264, 0.432260",\ + "1.064290, 1.064290, 1.064290, 1.064282, 1.064264",\ + "0.039065, 0.039065, 0.039065, 0.039064, 0.039059",\ + "0.088925, 0.088925, 0.088925, 0.088923, 0.088919",\ + "0.185901, 0.185901, 0.185901, 0.185900, 0.185895",\ + "0.432265, 0.432265, 0.432265, 0.432264, 0.432260",\ + "1.064290, 1.064290, 1.064290, 1.064282, 1.064264",\ + "0.039065, 0.039065, 0.039065, 0.039064, 0.039059",\ + "0.088925, 0.088925, 0.088925, 0.088923, 0.088919",\ + "0.185901, 0.185901, 0.185901, 0.185900, 0.185895",\ + "0.432265, 0.432265, 0.432265, 0.432264, 0.432260",\ + "1.064290, 1.064290, 1.064290, 1.064282, 1.064264",\ + "0.039065, 0.039065, 0.039065, 0.039064, 0.039059",\ + "0.088925, 0.088925, 0.088925, 0.088923, 0.088919",\ + "0.185901, 0.185901, 0.185901, 0.185900, 0.185895",\ + "0.432265, 0.432265, 0.432265, 0.432264, 0.432260",\ + "1.064290, 1.064290, 1.064290, 1.064282, 1.064264"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_min_2363*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[26]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011"); + values ( "0.348095, 0.545075, 0.727042, 1.018426, 1.581852",\ + "0.397956, 0.594939, 0.776906, 1.068290, 1.631715",\ + "0.499824, 0.696806, 0.878774, 1.170157, 1.733583",\ + "0.737685, 0.934668, 1.116635, 1.408019, 1.971444",\ + "1.310006, 1.506989, 1.688956, 1.980340, 2.543765",\ + "0.436445, 0.632394, 0.814323, 1.105731, 1.669206",\ + "0.486307, 0.682257, 0.864187, 1.155595, 1.719068",\ + "0.588175, 0.784125, 0.966055, 1.257463, 1.820936",\ + "0.826036, 1.021986, 1.203916, 1.495324, 2.058797",\ + "1.398357, 1.594307, 1.776237, 2.067645, 2.631118",\ + "0.525620, 0.712727, 0.894350, 1.185759, 1.749237",\ + "0.575481, 0.762590, 0.944214, 1.235623, 1.799100",\ + "0.677349, 0.864458, 1.046082, 1.337491, 1.900968",\ + "0.915211, 1.102319, 1.283943, 1.575353, 2.138829",\ + "1.487531, 1.674640, 1.856264, 2.147673, 2.711150",\ + "0.589087, 0.770548, 0.952053, 1.243192, 1.806260",\ + "0.638949, 0.820411, 1.001917, 1.293056, 1.856122",\ + "0.740817, 0.922279, 1.103785, 1.394924, 1.957990",\ + "0.978678, 1.160140, 1.341646, 1.632786, 2.195851",\ + "1.550998, 1.732461, 1.913967, 2.205106, 2.768172",\ + "0.896146, 1.075801, 1.255710, 1.546367, 2.108490",\ + "0.946008, 1.125664, 1.305574, 1.596231, 2.158352",\ + "1.047876, 1.227532, 1.407442, 1.698099, 2.260220",\ + "1.285737, 1.465394, 1.645303, 1.935960, 2.498081",\ + "1.858057, 2.037714, 2.217624, 2.508281, 3.070402"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011"); + values ( "0.039799, 0.039799, 0.039799, 0.039799, 0.039799",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375009, 0.375009, 0.375009, 0.375009, 0.375009",\ + "0.869291, 0.869291, 0.869292, 0.869292, 0.869292",\ + "2.137191, 2.137192, 2.137192, 2.137192, 2.137192",\ + "0.039799, 0.039799, 0.039799, 0.039799, 0.039799",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375009, 0.375009, 0.375009, 0.375009, 0.375009",\ + "0.869291, 0.869291, 0.869292, 0.869292, 0.869292",\ + "2.137191, 2.137192, 2.137192, 2.137192, 2.137192",\ + "0.039799, 0.039799, 0.039799, 0.039799, 0.039799",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375009, 0.375009, 0.375009, 0.375009, 0.375009",\ + "0.869291, 0.869291, 0.869292, 0.869292, 0.869292",\ + "2.137191, 2.137192, 2.137192, 2.137192, 2.137192",\ + "0.039799, 0.039799, 0.039799, 0.039799, 0.039799",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375009, 0.375009, 0.375009, 0.375009, 0.375009",\ + "0.869291, 0.869291, 0.869292, 0.869292, 0.869292",\ + "2.137191, 2.137192, 2.137192, 2.137192, 2.137192",\ + "0.039799, 0.039799, 0.039799, 0.039799, 0.039799",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375009, 0.375009, 0.375009, 0.375009, 0.375009",\ + "0.869291, 0.869291, 0.869292, 0.869292, 0.869292",\ + "2.137191, 2.137192, 2.137192, 2.137192, 2.137192"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011"); + values ( "0.386309, 0.585807, 0.767775, 1.059158, 1.622583",\ + "0.411174, 0.608157, 0.790125, 1.081508, 1.644933",\ + "0.452537, 0.649520, 0.831488, 1.122872, 1.686296",\ + "0.574573, 0.771556, 0.953524, 1.244907, 1.808332",\ + "0.906186, 1.103168, 1.285136, 1.576519, 2.139944",\ + "0.474546, 0.673125, 0.855056, 1.146463, 1.709936",\ + "0.499525, 0.695475, 0.877406, 1.168813, 1.732286",\ + "0.540888, 0.736839, 0.918769, 1.210177, 1.773650",\ + "0.662924, 0.858874, 1.040805, 1.332212, 1.895685",\ + "0.994536, 1.190487, 1.372417, 1.663825, 2.227298",\ + "0.563389, 0.753458, 0.935083, 1.226492, 1.789968",\ + "0.588699, 0.775808, 0.957433, 1.248842, 1.812318",\ + "0.630063, 0.817172, 0.998796, 1.290205, 1.853681",\ + "0.752098, 0.939207, 1.120831, 1.412241, 1.975717",\ + "1.083711, 1.270820, 1.452444, 1.743853, 2.307329",\ + "0.626548, 0.811280, 0.992786, 1.283925, 1.846990",\ + "0.652167, 0.833630, 1.015136, 1.306275, 1.869340",\ + "0.693530, 0.874993, 1.056499, 1.347638, 1.910704",\ + "0.815566, 0.997028, 1.178535, 1.469674, 2.032739",\ + "1.147178, 1.328641, 1.510147, 1.801286, 2.364352",\ + "0.936876, 1.116533, 1.296443, 1.587100, 2.149220",\ + "0.959225, 1.138883, 1.318793, 1.609450, 2.171570",\ + "1.000589, 1.180246, 1.360156, 1.650813, 2.212934",\ + "1.122624, 1.302282, 1.482192, 1.772848, 2.334969",\ + "1.454237, 1.633894, 1.813804, 2.104461, 2.666582"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011"); + values ( "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\ + "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\ + "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\ + "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\ + "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_min_2685*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[27]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011"); + values ( "0.226427, 0.405869, 0.606598, 0.932774, 1.565599",\ + "0.282384, 0.460178, 0.659964, 0.990994, 1.636396",\ + "0.358192, 0.534364, 0.733448, 1.069708, 1.728405",\ + "0.560390, 0.734140, 0.930018, 1.272669, 1.949568",\ + "1.105015, 1.276795, 1.468799, 1.815230, 2.504534",\ + "0.313828, 0.493186, 0.693879, 1.020079, 1.652953",\ + "0.369785, 0.547496, 0.747245, 1.078299, 1.723750",\ + "0.445593, 0.621681, 0.820729, 1.157013, 1.815759",\ + "0.647791, 0.821458, 1.017299, 1.359975, 2.036922",\ + "1.192415, 1.364112, 1.556080, 1.902535, 2.591887",\ + "0.394677, 0.573514, 0.773906, 1.100108, 1.732984",\ + "0.450625, 0.627823, 0.827272, 1.158327, 1.803782",\ + "0.526423, 0.702008, 0.900756, 1.237042, 1.895791",\ + "0.728608, 0.901785, 1.097326, 1.440003, 2.116953",\ + "1.273221, 1.444439, 1.636107, 1.982563, 2.671918",\ + "0.452415, 0.631348, 0.831654, 1.157626, 1.790177",\ + "0.508343, 0.685651, 0.885018, 1.215861, 1.861005",\ + "0.584122, 0.759831, 0.958501, 1.294592, 1.953046",\ + "0.786278, 0.959598, 1.155063, 1.497575, 2.174253",\ + "1.330868, 1.502245, 1.693835, 2.040151, 2.729248",\ + "0.756161, 0.936672, 1.135317, 1.460873, 2.092613",\ + "0.811907, 0.990932, 1.188681, 1.519120, 2.163478",\ + "0.887507, 1.065070, 1.262163, 1.597865, 2.255558",\ + "1.089394, 1.264774, 1.458724, 1.800867, 2.476817",\ + "1.633766, 1.807370, 1.997495, 2.343456, 3.031849"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011"); + values ( "0.149901, 0.149901, 0.154318, 0.175674, 0.224033",\ + "0.237266, 0.237266, 0.240233, 0.254222, 0.285839",\ + "0.400134, 0.400516, 0.400740, 0.407020, 0.422153",\ + "0.873536, 0.873536, 0.873536, 0.874627, 0.877289",\ + "2.137014, 2.139136, 2.139203, 2.139990, 2.141907",\ + "0.149901, 0.149901, 0.154318, 0.175674, 0.224033",\ + "0.237266, 0.237266, 0.240233, 0.254222, 0.285839",\ + "0.400134, 0.400516, 0.400740, 0.407020, 0.422153",\ + "0.873536, 0.873536, 0.873536, 0.874627, 0.877289",\ + "2.137014, 2.139136, 2.139203, 2.139990, 2.141907",\ + "0.149901, 0.149901, 0.154318, 0.175674, 0.224033",\ + "0.237266, 0.237266, 0.240233, 0.254222, 0.285839",\ + "0.400136, 0.400516, 0.400740, 0.407020, 0.422153",\ + "0.873536, 0.873536, 0.873536, 0.874627, 0.877289",\ + "2.137026, 2.139136, 2.139203, 2.139990, 2.141907",\ + "0.149901, 0.149901, 0.154329, 0.175732, 0.224149",\ + "0.237266, 0.237266, 0.240240, 0.254260, 0.285916",\ + "0.400141, 0.400517, 0.400740, 0.407038, 0.422190",\ + "0.873536, 0.873536, 0.873536, 0.874631, 0.877295",\ + "2.137051, 2.139143, 2.139203, 2.139992, 2.141911",\ + "0.149901, 0.149901, 0.154330, 0.175783, 0.224291",\ + "0.237266, 0.237266, 0.240241, 0.254293, 0.286008",\ + "0.400183, 0.400527, 0.400740, 0.407054, 0.422234",\ + "0.873536, 0.873536, 0.873536, 0.874633, 0.877303",\ + "2.137286, 2.139199, 2.139203, 2.139994, 2.141917"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011"); + values ( "0.152176, 0.424550, 0.621056, 0.937588, 1.550446",\ + "0.188303, 0.458742, 0.655289, 0.973816, 1.591506",\ + "0.242989, 0.508512, 0.704797, 1.024208, 1.644274",\ + "0.376456, 0.636940, 0.832877, 1.152112, 1.772037",\ + "0.711310, 0.972696, 1.168342, 1.486421, 2.103779",\ + "0.240546, 0.511867, 0.708337, 1.024893, 1.637799",\ + "0.276651, 0.546059, 0.742570, 1.061121, 1.678860",\ + "0.331309, 0.595830, 0.792078, 1.111513, 1.731628",\ + "0.464761, 0.724258, 0.920158, 1.239417, 1.859390",\ + "0.799595, 1.060013, 1.255623, 1.573726, 2.191132",\ + "0.330479, 0.592194, 0.788364, 1.104922, 1.717831",\ + "0.366514, 0.626386, 0.822597, 1.141150, 1.758891",\ + "0.421085, 0.676157, 0.872105, 1.191542, 1.811660",\ + "0.554489, 0.804585, 1.000185, 1.319445, 1.939422",\ + "0.889264, 1.140340, 1.335650, 1.653755, 2.271164",\ + "0.394961, 0.650030, 0.846103, 1.162416, 1.774975",\ + "0.430928, 0.684222, 0.880335, 1.198650, 1.816048",\ + "0.485415, 0.733993, 0.929843, 1.249045, 1.868822",\ + "0.618773, 0.862421, 1.057922, 1.376948, 1.996584",\ + "0.953489, 1.198177, 1.393386, 1.711254, 2.328319",\ + "0.736666, 0.955361, 1.149764, 1.465641, 2.077353",\ + "0.772199, 0.989556, 1.183996, 1.501880, 2.118440",\ + "0.826145, 1.039328, 1.233504, 1.552278, 2.171221",\ + "0.959204, 1.167753, 1.361583, 1.680181, 2.298982",\ + "1.293546, 1.503515, 1.697047, 2.014484, 2.630710"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011"); + values ( "0.071550, 0.071795, 0.076447, 0.093063, 0.129680",\ + "0.104996, 0.104996, 0.106778, 0.118004, 0.143877",\ + "0.191021, 0.191212, 0.191736, 0.197505, 0.211137",\ + "0.431517, 0.431517, 0.431517, 0.433292, 0.437617",\ + "1.063952, 1.065332, 1.065376, 1.065376, 1.065376",\ + "0.071556, 0.071795, 0.076447, 0.093063, 0.129680",\ + "0.104996, 0.104996, 0.106778, 0.118004, 0.143877",\ + "0.191026, 0.191212, 0.191736, 0.197505, 0.211137",\ + "0.431517, 0.431517, 0.431517, 0.433292, 0.437617",\ + "1.063986, 1.065332, 1.065376, 1.065376, 1.065376",\ + "0.071574, 0.071795, 0.076447, 0.093063, 0.129680",\ + "0.104996, 0.104996, 0.106778, 0.118004, 0.143877",\ + "0.191041, 0.191212, 0.191736, 0.197505, 0.211137",\ + "0.431517, 0.431517, 0.431517, 0.433292, 0.437617",\ + "1.064092, 1.065332, 1.065376, 1.065376, 1.065376",\ + "0.071593, 0.071796, 0.076458, 0.093108, 0.129768",\ + "0.104996, 0.104996, 0.106782, 0.118035, 0.143939",\ + "0.191055, 0.191213, 0.191737, 0.197522, 0.211169",\ + "0.431517, 0.431517, 0.431517, 0.433297, 0.437628",\ + "1.064195, 1.065337, 1.065376, 1.065376, 1.065376",\ + "0.071710, 0.071803, 0.076460, 0.093146, 0.129875",\ + "0.104996, 0.104996, 0.106783, 0.118062, 0.144015",\ + "0.191146, 0.191218, 0.191737, 0.197536, 0.211209",\ + "0.431517, 0.431517, 0.431517, 0.433301, 0.437640",\ + "1.064855, 1.065373, 1.065376, 1.065376, 1.065376"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_min_2743*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[28]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.511543, 0.732095, 0.909621, 1.198355, 1.759116",\ + "0.561373, 0.781924, 0.959450, 1.248185, 1.808946",\ + "0.663244, 0.883796, 1.061322, 1.350056, 1.910817",\ + "0.901102, 1.121654, 1.299180, 1.587914, 2.148676",\ + "1.473419, 1.693970, 1.871496, 2.160231, 2.720992",\ + "0.599955, 0.819413, 0.996902, 1.285660, 1.846469",\ + "0.649784, 0.869243, 1.046731, 1.335490, 1.896299",\ + "0.751656, 0.971114, 1.148603, 1.437361, 1.998171",\ + "0.989514, 1.208973, 1.386461, 1.675220, 2.236029",\ + "1.561830, 1.781289, 1.958777, 2.247536, 2.808345",\ + "0.689055, 0.899748, 1.076928, 1.365689, 1.926501",\ + "0.738884, 0.949578, 1.126758, 1.415518, 1.976331",\ + "0.840756, 1.051450, 1.228629, 1.517390, 2.078202",\ + "1.078614, 1.289308, 1.466488, 1.755248, 2.316061",\ + "1.650930, 1.861624, 2.038804, 2.327564, 2.888377",\ + "0.752342, 0.957565, 1.134620, 1.423118, 1.983516",\ + "0.802171, 1.007395, 1.184450, 1.472948, 2.033346",\ + "0.904043, 1.109266, 1.286322, 1.574819, 2.135217",\ + "1.141901, 1.347125, 1.524180, 1.812678, 2.373076",\ + "1.714217, 1.919441, 2.096496, 2.384994, 2.945392",\ + "1.083355, 1.262794, 1.438277, 1.726290, 2.285737",\ + "1.133185, 1.312624, 1.488106, 1.776120, 2.335567",\ + "1.235056, 1.414496, 1.589978, 1.877991, 2.437438",\ + "1.472914, 1.652354, 1.827836, 2.115849, 2.675297",\ + "2.045231, 2.224670, 2.400152, 2.688166, 3.247612"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.039738, 0.039738, 0.039738, 0.039738, 0.039738",\ + "0.147762, 0.147762, 0.147762, 0.147762, 0.147762",\ + "0.375019, 0.375019, 0.375019, 0.375019, 0.375019",\ + "0.869329, 0.869329, 0.869329, 0.869329, 0.869329",\ + "2.137213, 2.137213, 2.137213, 2.137213, 2.137213",\ + "0.039738, 0.039738, 0.039738, 0.039738, 0.039738",\ + "0.147762, 0.147762, 0.147762, 0.147762, 0.147762",\ + "0.375019, 0.375019, 0.375019, 0.375019, 0.375019",\ + "0.869329, 0.869329, 0.869329, 0.869329, 0.869329",\ + "2.137213, 2.137213, 2.137213, 2.137213, 2.137213",\ + "0.039738, 0.039738, 0.039738, 0.039738, 0.039738",\ + "0.147762, 0.147762, 0.147762, 0.147762, 0.147762",\ + "0.375019, 0.375019, 0.375019, 0.375019, 0.375019",\ + "0.869329, 0.869329, 0.869329, 0.869329, 0.869329",\ + "2.137213, 2.137213, 2.137213, 2.137213, 2.137213",\ + "0.039738, 0.039738, 0.039738, 0.039738, 0.039738",\ + "0.147762, 0.147762, 0.147762, 0.147762, 0.147762",\ + "0.375019, 0.375019, 0.375019, 0.375019, 0.375019",\ + "0.869329, 0.869329, 0.869329, 0.869329, 0.869329",\ + "2.137213, 2.137213, 2.137213, 2.137213, 2.137213",\ + "0.039738, 0.039738, 0.039738, 0.039738, 0.039738",\ + "0.147762, 0.147762, 0.147762, 0.147762, 0.147762",\ + "0.375019, 0.375019, 0.375019, 0.375019, 0.375019",\ + "0.869329, 0.869329, 0.869329, 0.869329, 0.869329",\ + "2.137213, 2.137213, 2.137213, 2.137213, 2.137213"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.544225, 0.764777, 0.942302, 1.231037, 1.791798",\ + "0.574581, 0.795133, 0.972659, 1.261393, 1.822155",\ + "0.615945, 0.836497, 1.014023, 1.302758, 1.863519",\ + "0.737984, 0.958535, 1.136061, 1.424796, 1.985557",\ + "1.069601, 1.290153, 1.467679, 1.756413, 2.317174",\ + "0.632637, 0.852095, 1.029583, 1.318342, 1.879151",\ + "0.662993, 0.882452, 1.059940, 1.348698, 1.909508",\ + "0.704357, 0.923816, 1.101304, 1.390063, 1.950872",\ + "0.826395, 1.045854, 1.223342, 1.512101, 2.072910",\ + "1.158013, 1.377472, 1.554960, 1.843718, 2.404528",\ + "0.721737, 0.932430, 1.109610, 1.398370, 1.959183",\ + "0.752093, 0.962787, 1.139967, 1.428727, 1.989540",\ + "0.793457, 1.004151, 1.181331, 1.470091, 2.030904",\ + "0.915496, 1.126189, 1.303369, 1.592129, 2.152942",\ + "1.247113, 1.457807, 1.634987, 1.923747, 2.484560",\ + "0.785023, 0.990247, 1.167302, 1.455800, 2.016198",\ + "0.815380, 1.020603, 1.197659, 1.486156, 2.046555",\ + "0.856744, 1.061968, 1.239023, 1.527521, 2.087919",\ + "0.978782, 1.184006, 1.361061, 1.649559, 2.209957",\ + "1.310400, 1.515623, 1.692679, 1.981176, 2.541574",\ + "1.116037, 1.295476, 1.470958, 1.758972, 2.318419",\ + "1.146393, 1.325833, 1.501315, 1.789329, 2.348775",\ + "1.187757, 1.367197, 1.542679, 1.830693, 2.390140",\ + "1.309796, 1.489235, 1.664717, 1.952731, 2.512178",\ + "1.641413, 1.820853, 1.996335, 2.284348, 2.843795"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.045860, 0.045860, 0.045860, 0.045860, 0.045860",\ + "0.091392, 0.091392, 0.091392, 0.091392, 0.091392",\ + "0.185815, 0.185815, 0.185815, 0.185815, 0.185815",\ + "0.432253, 0.432253, 0.432253, 0.432253, 0.432253",\ + "1.064246, 1.064246, 1.064246, 1.064246, 1.064246",\ + "0.045860, 0.045860, 0.045860, 0.045860, 0.045860",\ + "0.091392, 0.091392, 0.091392, 0.091392, 0.091392",\ + "0.185815, 0.185815, 0.185815, 0.185815, 0.185815",\ + "0.432253, 0.432253, 0.432253, 0.432253, 0.432253",\ + "1.064246, 1.064246, 1.064246, 1.064246, 1.064246",\ + "0.045860, 0.045860, 0.045860, 0.045860, 0.045860",\ + "0.091392, 0.091392, 0.091392, 0.091392, 0.091392",\ + "0.185815, 0.185815, 0.185815, 0.185815, 0.185815",\ + "0.432253, 0.432253, 0.432253, 0.432253, 0.432253",\ + "1.064246, 1.064246, 1.064246, 1.064246, 1.064246",\ + "0.045860, 0.045860, 0.045860, 0.045860, 0.045860",\ + "0.091392, 0.091392, 0.091392, 0.091392, 0.091392",\ + "0.185815, 0.185815, 0.185815, 0.185815, 0.185815",\ + "0.432253, 0.432253, 0.432253, 0.432253, 0.432253",\ + "1.064246, 1.064246, 1.064246, 1.064246, 1.064246",\ + "0.045860, 0.045860, 0.045860, 0.045860, 0.045860",\ + "0.091392, 0.091392, 0.091392, 0.091392, 0.091392",\ + "0.185815, 0.185815, 0.185815, 0.185815, 0.185815",\ + "0.432253, 0.432253, 0.432253, 0.432253, 0.432253",\ + "1.064246, 1.064246, 1.064246, 1.064246, 1.064246"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_min*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[29]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.493881, 0.730366, 0.921755, 1.228337, 1.821155",\ + "0.543711, 0.780195, 0.971585, 1.278167, 1.870984",\ + "0.645582, 0.882067, 1.073456, 1.380038, 1.972856",\ + "0.883440, 1.119925, 1.311315, 1.617896, 2.210714",\ + "1.455756, 1.692241, 1.883631, 2.190213, 2.783030",\ + "0.582168, 0.817683, 1.009036, 1.315642, 1.908508",\ + "0.631998, 0.867513, 1.058866, 1.365472, 1.958338",\ + "0.733870, 0.969384, 1.160737, 1.467343, 2.060209",\ + "0.971728, 1.207243, 1.398596, 1.705202, 2.298068",\ + "1.544044, 1.779559, 1.970912, 2.277518, 2.870384",\ + "0.671482, 0.898014, 1.089063, 1.395671, 1.988540",\ + "0.721312, 0.947843, 1.138893, 1.445500, 2.038369",\ + "0.823183, 1.049715, 1.240764, 1.547372, 2.140241",\ + "1.061042, 1.287573, 1.478623, 1.785230, 2.378099",\ + "1.633358, 1.859889, 2.050939, 2.357546, 2.950415",\ + "0.735219, 0.955859, 1.146789, 1.453140, 2.045635",\ + "0.785049, 1.005688, 1.196618, 1.502970, 2.095464",\ + "0.886921, 1.107560, 1.298490, 1.604841, 2.197336",\ + "1.124779, 1.345418, 1.536348, 1.842699, 2.435194",\ + "1.697095, 1.917734, 2.108664, 2.415015, 3.007510",\ + "1.072194, 1.261268, 1.450449, 1.756345, 2.347952",\ + "1.122024, 1.311097, 1.500278, 1.806174, 2.397781",\ + "1.223895, 1.412969, 1.602150, 1.908046, 2.499653",\ + "1.461754, 1.650827, 1.840008, 2.145904, 2.737511",\ + "2.034070, 2.223143, 2.412324, 2.718220, 3.309827"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.039738, 0.039738, 0.039738, 0.039738, 0.039738",\ + "0.147762, 0.147762, 0.147762, 0.147762, 0.147762",\ + "0.375019, 0.375019, 0.375019, 0.375019, 0.375019",\ + "0.869329, 0.869329, 0.869329, 0.869329, 0.869329",\ + "2.137213, 2.137213, 2.137213, 2.137213, 2.137213",\ + "0.039738, 0.039738, 0.039738, 0.039738, 0.039738",\ + "0.147762, 0.147762, 0.147762, 0.147762, 0.147762",\ + "0.375019, 0.375019, 0.375019, 0.375019, 0.375019",\ + "0.869329, 0.869329, 0.869329, 0.869329, 0.869329",\ + "2.137213, 2.137213, 2.137213, 2.137213, 2.137213",\ + "0.039738, 0.039738, 0.039738, 0.039738, 0.039738",\ + "0.147762, 0.147762, 0.147762, 0.147762, 0.147762",\ + "0.375019, 0.375019, 0.375019, 0.375019, 0.375019",\ + "0.869329, 0.869329, 0.869329, 0.869329, 0.869329",\ + "2.137213, 2.137213, 2.137213, 2.137213, 2.137213",\ + "0.039738, 0.039738, 0.039738, 0.039738, 0.039738",\ + "0.147762, 0.147762, 0.147762, 0.147762, 0.147762",\ + "0.375019, 0.375019, 0.375019, 0.375019, 0.375019",\ + "0.869329, 0.869329, 0.869329, 0.869329, 0.869329",\ + "2.137213, 2.137213, 2.137213, 2.137213, 2.137213",\ + "0.039738, 0.039738, 0.039738, 0.039738, 0.039738",\ + "0.147762, 0.147762, 0.147762, 0.147762, 0.147762",\ + "0.375019, 0.375019, 0.375019, 0.375019, 0.375019",\ + "0.869329, 0.869329, 0.869329, 0.869329, 0.869329",\ + "2.137213, 2.137213, 2.137213, 2.137213, 2.137213"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.526563, 0.763047, 0.954437, 1.261019, 1.853837",\ + "0.556919, 0.793404, 0.984794, 1.291375, 1.884193",\ + "0.598283, 0.834768, 1.026158, 1.332739, 1.925557",\ + "0.720322, 0.956806, 1.148196, 1.454778, 2.047596",\ + "1.051939, 1.288424, 1.479813, 1.786395, 2.379213",\ + "0.614850, 0.850365, 1.041718, 1.348324, 1.941190",\ + "0.645207, 0.880722, 1.072075, 1.378680, 1.971546",\ + "0.686571, 0.922086, 1.113439, 1.420045, 2.012911",\ + "0.808609, 1.044124, 1.235477, 1.542083, 2.134949",\ + "1.140227, 1.375741, 1.567094, 1.873700, 2.466566",\ + "0.704164, 0.930695, 1.121745, 1.428352, 2.021222",\ + "0.734520, 0.961052, 1.152102, 1.458709, 2.051578",\ + "0.775885, 1.002416, 1.193466, 1.500073, 2.092942",\ + "0.897923, 1.124454, 1.315504, 1.622111, 2.214981",\ + "1.229540, 1.456072, 1.647121, 1.953729, 2.546598",\ + "0.767901, 0.988540, 1.179470, 1.485822, 2.078316",\ + "0.798258, 1.018897, 1.209827, 1.516178, 2.108673",\ + "0.839622, 1.060261, 1.251191, 1.557542, 2.150037",\ + "0.961660, 1.182299, 1.373229, 1.679581, 2.272075",\ + "1.293278, 1.513917, 1.704847, 2.011198, 2.603693",\ + "1.104876, 1.293949, 1.483130, 1.789026, 2.380633",\ + "1.135232, 1.324306, 1.513487, 1.819383, 2.410990",\ + "1.176597, 1.365670, 1.554851, 1.860747, 2.452354",\ + "1.298635, 1.487708, 1.676889, 1.982785, 2.574392",\ + "1.630252, 1.819326, 2.008507, 2.314403, 2.906010"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.045860, 0.045860, 0.045860, 0.045860, 0.045860",\ + "0.091392, 0.091392, 0.091392, 0.091392, 0.091392",\ + "0.185815, 0.185815, 0.185815, 0.185815, 0.185815",\ + "0.432253, 0.432253, 0.432253, 0.432253, 0.432253",\ + "1.064246, 1.064246, 1.064246, 1.064246, 1.064246",\ + "0.045860, 0.045860, 0.045860, 0.045860, 0.045860",\ + "0.091392, 0.091392, 0.091392, 0.091392, 0.091392",\ + "0.185815, 0.185815, 0.185815, 0.185815, 0.185815",\ + "0.432253, 0.432253, 0.432253, 0.432253, 0.432253",\ + "1.064246, 1.064246, 1.064246, 1.064246, 1.064246",\ + "0.045860, 0.045860, 0.045860, 0.045860, 0.045860",\ + "0.091392, 0.091392, 0.091392, 0.091392, 0.091392",\ + "0.185815, 0.185815, 0.185815, 0.185815, 0.185815",\ + "0.432253, 0.432253, 0.432253, 0.432253, 0.432253",\ + "1.064246, 1.064246, 1.064246, 1.064246, 1.064246",\ + "0.045860, 0.045860, 0.045860, 0.045860, 0.045860",\ + "0.091392, 0.091392, 0.091392, 0.091392, 0.091392",\ + "0.185815, 0.185815, 0.185815, 0.185815, 0.185815",\ + "0.432253, 0.432253, 0.432253, 0.432253, 0.432253",\ + "1.064246, 1.064246, 1.064246, 1.064246, 1.064246",\ + "0.045860, 0.045860, 0.045860, 0.045860, 0.045860",\ + "0.091392, 0.091392, 0.091392, 0.091392, 0.091392",\ + "0.185815, 0.185815, 0.185815, 0.185815, 0.185815",\ + "0.432253, 0.432253, 0.432253, 0.432253, 0.432253",\ + "1.064246, 1.064246, 1.064246, 1.064246, 1.064246"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_min_2333*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[31]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.470602, 0.685204, 0.866879, 1.157031, 1.717773",\ + "0.518644, 0.733246, 0.914922, 1.205074, 1.765816",\ + "0.620710, 0.835312, 1.016988, 1.307140, 1.867882",\ + "0.851211, 1.065814, 1.247489, 1.537641, 2.098383",\ + "1.409103, 1.623705, 1.805381, 2.095532, 2.656275",\ + "0.558998, 0.772522, 0.954160, 1.244336, 1.805127",\ + "0.607041, 0.820565, 1.002203, 1.292379, 1.853169",\ + "0.709107, 0.922631, 1.104269, 1.394445, 1.955235",\ + "0.939608, 1.153132, 1.334770, 1.624946, 2.185737",\ + "1.497499, 1.711023, 1.892661, 2.182837, 2.743628",\ + "0.648348, 0.852854, 1.034187, 1.324365, 1.885158",\ + "0.696391, 0.900897, 1.082230, 1.372408, 1.933201",\ + "0.798457, 1.002963, 1.184296, 1.474474, 2.035267",\ + "1.028958, 1.233464, 1.414797, 1.704975, 2.265768",\ + "1.586850, 1.791356, 1.972688, 2.262866, 2.823659",\ + "0.711997, 0.910682, 1.091889, 1.381795, 1.942174",\ + "0.760040, 0.958725, 1.139932, 1.429837, 1.990217",\ + "0.862106, 1.060791, 1.241998, 1.531904, 2.092283",\ + "1.092607, 1.291292, 1.472499, 1.762405, 2.322784",\ + "1.650499, 1.849183, 2.030391, 2.320296, 2.880676",\ + "1.035012, 1.215977, 1.395546, 1.684966, 2.244397",\ + "1.083055, 1.264019, 1.443589, 1.733009, 2.292439",\ + "1.185121, 1.366086, 1.545655, 1.835075, 2.394506",\ + "1.415622, 1.596586, 1.776156, 2.065576, 2.625007",\ + "1.973513, 2.154478, 2.334047, 2.623468, 3.182898"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.036124, 0.036124, 0.036124, 0.036124, 0.036124",\ + "0.147307, 0.147307, 0.147307, 0.147307, 0.147307",\ + "0.375576, 0.375576, 0.375576, 0.375576, 0.375576",\ + "0.871151, 0.871151, 0.871151, 0.871151, 0.871151",\ + "2.136611, 2.136611, 2.136611, 2.136611, 2.136611",\ + "0.036124, 0.036124, 0.036124, 0.036124, 0.036124",\ + "0.147307, 0.147307, 0.147307, 0.147307, 0.147307",\ + "0.375576, 0.375576, 0.375576, 0.375576, 0.375576",\ + "0.871151, 0.871151, 0.871151, 0.871151, 0.871151",\ + "2.136611, 2.136611, 2.136611, 2.136611, 2.136611",\ + "0.036124, 0.036124, 0.036124, 0.036124, 0.036124",\ + "0.147307, 0.147307, 0.147307, 0.147307, 0.147307",\ + "0.375576, 0.375576, 0.375576, 0.375576, 0.375576",\ + "0.871151, 0.871151, 0.871151, 0.871151, 0.871151",\ + "2.136611, 2.136611, 2.136611, 2.136611, 2.136611",\ + "0.036124, 0.036124, 0.036124, 0.036124, 0.036124",\ + "0.147307, 0.147307, 0.147307, 0.147307, 0.147307",\ + "0.375576, 0.375576, 0.375576, 0.375576, 0.375576",\ + "0.871151, 0.871151, 0.871151, 0.871151, 0.871151",\ + "2.136611, 2.136611, 2.136611, 2.136611, 2.136611",\ + "0.036124, 0.036124, 0.036124, 0.036124, 0.036124",\ + "0.147307, 0.147307, 0.147307, 0.147307, 0.147307",\ + "0.375576, 0.375576, 0.375576, 0.375576, 0.375576",\ + "0.871151, 0.871151, 0.871151, 0.871151, 0.871151",\ + "2.136611, 2.136611, 2.136611, 2.136611, 2.136611"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.455792, 0.670394, 0.852070, 1.142222, 1.702964",\ + "0.494395, 0.708997, 0.890673, 1.180825, 1.741567",\ + "0.549522, 0.764125, 0.945800, 1.235952, 1.796694",\ + "0.682338, 0.896940, 1.078616, 1.368768, 1.929510",\ + "1.022840, 1.237442, 1.419117, 1.709269, 2.270011",\ + "0.544189, 0.757712, 0.939351, 1.229527, 1.790317",\ + "0.582792, 0.796315, 0.977954, 1.268130, 1.828920",\ + "0.637919, 0.851443, 1.033081, 1.323257, 1.884048",\ + "0.770735, 0.984258, 1.165897, 1.456073, 2.016863",\ + "1.111236, 1.324760, 1.506398, 1.796574, 2.357365",\ + "0.633539, 0.838045, 1.019377, 1.309555, 1.870349",\ + "0.672142, 0.876648, 1.057981, 1.348158, 1.908952",\ + "0.727269, 0.931775, 1.113108, 1.403286, 1.964079",\ + "0.860085, 1.064591, 1.245924, 1.536101, 2.096895",\ + "1.200586, 1.405093, 1.586425, 1.876603, 2.437396",\ + "0.697188, 0.895872, 1.077080, 1.366985, 1.927365",\ + "0.735791, 0.934475, 1.115683, 1.405588, 1.965968",\ + "0.790918, 0.989603, 1.170810, 1.460716, 2.021095",\ + "0.923734, 1.122418, 1.303626, 1.593531, 2.153911",\ + "1.264235, 1.462920, 1.644127, 1.934033, 2.494412",\ + "1.020202, 1.201167, 1.380737, 1.670157, 2.229587",\ + "1.058805, 1.239770, 1.419340, 1.708760, 2.268190",\ + "1.113933, 1.294898, 1.474467, 1.763887, 2.323318",\ + "1.246748, 1.427713, 1.607283, 1.896703, 2.456133",\ + "1.587250, 1.768215, 1.947784, 2.237205, 2.796635"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.039238, 0.039238, 0.039238, 0.039238, 0.039238",\ + "0.089111, 0.089111, 0.089111, 0.089111, 0.089111",\ + "0.185883, 0.185883, 0.185883, 0.185883, 0.185883",\ + "0.432255, 0.432255, 0.432255, 0.432255, 0.432255",\ + "1.064240, 1.064240, 1.064240, 1.064240, 1.064240",\ + "0.039238, 0.039238, 0.039238, 0.039238, 0.039238",\ + "0.089111, 0.089111, 0.089111, 0.089111, 0.089111",\ + "0.185883, 0.185883, 0.185883, 0.185883, 0.185883",\ + "0.432255, 0.432255, 0.432255, 0.432255, 0.432255",\ + "1.064240, 1.064240, 1.064240, 1.064240, 1.064240",\ + "0.039238, 0.039238, 0.039238, 0.039238, 0.039238",\ + "0.089111, 0.089111, 0.089111, 0.089111, 0.089111",\ + "0.185883, 0.185883, 0.185883, 0.185883, 0.185883",\ + "0.432255, 0.432255, 0.432255, 0.432255, 0.432255",\ + "1.064240, 1.064240, 1.064240, 1.064240, 1.064240",\ + "0.039238, 0.039238, 0.039238, 0.039238, 0.039238",\ + "0.089111, 0.089111, 0.089111, 0.089111, 0.089111",\ + "0.185883, 0.185883, 0.185883, 0.185883, 0.185883",\ + "0.432255, 0.432255, 0.432255, 0.432255, 0.432255",\ + "1.064240, 1.064240, 1.064240, 1.064240, 1.064240",\ + "0.039238, 0.039238, 0.039238, 0.039238, 0.039238",\ + "0.089111, 0.089111, 0.089111, 0.089111, 0.089111",\ + "0.185883, 0.185883, 0.185883, 0.185883, 0.185883",\ + "0.432255, 0.432255, 0.432255, 0.432255, 0.432255",\ + "1.064240, 1.064240, 1.064240, 1.064240, 1.064240"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_min_2437*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[33]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.448199, 0.668078, 0.854477, 1.152594, 1.728783",\ + "0.496242, 0.716121, 0.902520, 1.200637, 1.776826",\ + "0.598308, 0.818187, 1.004586, 1.302703, 1.878892",\ + "0.828809, 1.048688, 1.235087, 1.533204, 2.109392",\ + "1.386700, 1.606579, 1.792978, 2.091095, 2.667284",\ + "0.536520, 0.755396, 0.941758, 1.239900, 1.816137",\ + "0.584563, 0.803439, 0.989801, 1.287942, 1.864179",\ + "0.686629, 0.905505, 1.091867, 1.390008, 1.966245",\ + "0.917129, 1.136006, 1.322368, 1.620509, 2.196746",\ + "1.475021, 1.693897, 1.880259, 2.178401, 2.754637",\ + "0.625932, 0.835726, 1.021785, 1.319928, 1.896168",\ + "0.673975, 0.883769, 1.069828, 1.367971, 1.944211",\ + "0.776041, 0.985835, 1.171894, 1.470037, 2.046277",\ + "1.006542, 1.216336, 1.402395, 1.700537, 2.276778",\ + "1.564433, 1.774227, 1.960286, 2.258429, 2.834669",\ + "0.689763, 0.893549, 1.079499, 1.377377, 1.953223",\ + "0.737806, 0.941592, 1.127542, 1.425420, 2.001266",\ + "0.839872, 1.043658, 1.229608, 1.527486, 2.103332",\ + "1.070373, 1.274158, 1.460109, 1.757986, 2.333832",\ + "1.628264, 1.832049, 2.018000, 2.315878, 2.891724",\ + "1.020000, 1.198799, 1.383157, 1.680565, 2.255491",\ + "1.068043, 1.246842, 1.431200, 1.728607, 2.303534",\ + "1.170109, 1.348908, 1.533266, 1.830673, 2.405600",\ + "1.400609, 1.579409, 1.763767, 2.061174, 2.636101",\ + "1.958501, 2.137300, 2.321658, 2.619065, 3.193992"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.036124, 0.036124, 0.036124, 0.036124, 0.036124",\ + "0.147307, 0.147307, 0.147307, 0.147307, 0.147307",\ + "0.375576, 0.375576, 0.375576, 0.375576, 0.375576",\ + "0.871151, 0.871151, 0.871151, 0.871151, 0.871151",\ + "2.136611, 2.136611, 2.136611, 2.136611, 2.136611",\ + "0.036124, 0.036124, 0.036124, 0.036124, 0.036124",\ + "0.147307, 0.147307, 0.147307, 0.147307, 0.147307",\ + "0.375576, 0.375576, 0.375576, 0.375576, 0.375576",\ + "0.871151, 0.871151, 0.871151, 0.871151, 0.871151",\ + "2.136611, 2.136611, 2.136611, 2.136611, 2.136611",\ + "0.036124, 0.036124, 0.036124, 0.036124, 0.036124",\ + "0.147307, 0.147307, 0.147307, 0.147307, 0.147307",\ + "0.375576, 0.375576, 0.375576, 0.375576, 0.375576",\ + "0.871151, 0.871151, 0.871151, 0.871151, 0.871151",\ + "2.136611, 2.136611, 2.136611, 2.136611, 2.136611",\ + "0.036124, 0.036124, 0.036124, 0.036124, 0.036124",\ + "0.147307, 0.147307, 0.147307, 0.147307, 0.147307",\ + "0.375576, 0.375576, 0.375576, 0.375576, 0.375576",\ + "0.871151, 0.871151, 0.871151, 0.871151, 0.871151",\ + "2.136611, 2.136611, 2.136611, 2.136611, 2.136611",\ + "0.036124, 0.036124, 0.036124, 0.036124, 0.036124",\ + "0.147307, 0.147307, 0.147307, 0.147307, 0.147307",\ + "0.375576, 0.375576, 0.375576, 0.375576, 0.375576",\ + "0.871151, 0.871151, 0.871151, 0.871151, 0.871151",\ + "2.136611, 2.136611, 2.136611, 2.136611, 2.136611"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.433389, 0.653268, 0.839667, 1.137784, 1.713973",\ + "0.471993, 0.691871, 0.878270, 1.176387, 1.752576",\ + "0.527120, 0.746999, 0.933398, 1.231515, 1.807704",\ + "0.659935, 0.879814, 1.066213, 1.364330, 1.940519",\ + "1.000437, 1.220316, 1.406715, 1.704832, 2.281021",\ + "0.521709, 0.740586, 0.926948, 1.225089, 1.801326",\ + "0.560313, 0.779189, 0.965551, 1.263693, 1.839930",\ + "0.615440, 0.834317, 1.020679, 1.318820, 1.895057",\ + "0.748256, 0.967132, 1.153494, 1.451635, 2.027873",\ + "1.088757, 1.307634, 1.493996, 1.792137, 2.368374",\ + "0.611122, 0.820916, 1.006975, 1.305118, 1.881358",\ + "0.649725, 0.859520, 1.045578, 1.343721, 1.919961",\ + "0.704853, 0.914647, 1.100706, 1.398849, 1.975089",\ + "0.837668, 1.047462, 1.233521, 1.531664, 2.107904",\ + "1.178170, 1.387964, 1.574023, 1.872166, 2.448406",\ + "0.674953, 0.878738, 1.064689, 1.362566, 1.938412",\ + "0.713556, 0.917342, 1.103292, 1.401170, 1.977016",\ + "0.768684, 0.972469, 1.158420, 1.456297, 2.032143",\ + "0.901499, 1.105285, 1.291235, 1.589113, 2.164959",\ + "1.242001, 1.445786, 1.631737, 1.929615, 2.505460",\ + "1.005189, 1.183989, 1.368347, 1.665754, 2.240681",\ + "1.043793, 1.222592, 1.406950, 1.704358, 2.279284",\ + "1.098920, 1.277719, 1.462078, 1.759485, 2.334412",\ + "1.231736, 1.410535, 1.594893, 1.892301, 2.467227",\ + "1.572237, 1.751037, 1.935395, 2.232802, 2.807729"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.039239, 0.039239, 0.039239, 0.039239, 0.039239",\ + "0.089112, 0.089112, 0.089112, 0.089112, 0.089112",\ + "0.185883, 0.185883, 0.185883, 0.185883, 0.185883",\ + "0.432255, 0.432255, 0.432255, 0.432255, 0.432255",\ + "1.064240, 1.064240, 1.064240, 1.064240, 1.064240",\ + "0.039239, 0.039239, 0.039239, 0.039239, 0.039239",\ + "0.089112, 0.089112, 0.089112, 0.089112, 0.089112",\ + "0.185883, 0.185883, 0.185883, 0.185883, 0.185883",\ + "0.432255, 0.432255, 0.432255, 0.432255, 0.432255",\ + "1.064240, 1.064240, 1.064240, 1.064240, 1.064240",\ + "0.039239, 0.039239, 0.039239, 0.039239, 0.039239",\ + "0.089112, 0.089112, 0.089112, 0.089112, 0.089112",\ + "0.185883, 0.185883, 0.185883, 0.185883, 0.185883",\ + "0.432255, 0.432255, 0.432255, 0.432255, 0.432255",\ + "1.064240, 1.064240, 1.064240, 1.064240, 1.064240",\ + "0.039239, 0.039239, 0.039239, 0.039239, 0.039239",\ + "0.089112, 0.089112, 0.089112, 0.089112, 0.089112",\ + "0.185883, 0.185883, 0.185883, 0.185883, 0.185883",\ + "0.432255, 0.432255, 0.432255, 0.432255, 0.432255",\ + "1.064240, 1.064240, 1.064240, 1.064240, 1.064240",\ + "0.039239, 0.039239, 0.039239, 0.039239, 0.039239",\ + "0.089112, 0.089112, 0.089112, 0.089112, 0.089112",\ + "0.185883, 0.185883, 0.185883, 0.185883, 0.185883",\ + "0.432255, 0.432255, 0.432255, 0.432255, 0.432255",\ + "1.064240, 1.064240, 1.064240, 1.064240, 1.064240"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_min_2540*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[34]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011"); + values ( "0.361629, 0.625108, 0.820219, 1.137042, 1.751491",\ + "0.411458, 0.674937, 0.870045, 1.186864, 1.801305",\ + "0.513330, 0.776809, 0.971917, 1.288736, 1.903178",\ + "0.751188, 1.014667, 1.209775, 1.526594, 2.141035",\ + "1.323504, 1.586983, 1.782091, 2.098909, 2.713349",\ + "0.450018, 0.712426, 0.907500, 1.224347, 1.838845",\ + "0.499848, 0.762256, 0.957326, 1.274169, 1.888658",\ + "0.601719, 0.864127, 1.059198, 1.376041, 1.990532",\ + "0.839577, 1.101985, 1.297056, 1.613899, 2.228389",\ + "1.411893, 1.674302, 1.869372, 2.186214, 2.800702",\ + "0.539154, 0.792761, 0.987527, 1.304375, 1.918876",\ + "0.588984, 0.842590, 1.037353, 1.354197, 1.968690",\ + "0.690855, 0.944462, 1.139225, 1.456070, 2.070563",\ + "0.928713, 1.182320, 1.377083, 1.693927, 2.308420",\ + "1.501029, 1.754636, 1.949399, 2.266243, 2.880734",\ + "0.602519, 0.850602, 1.045260, 1.361870, 1.976021",\ + "0.652348, 0.900431, 1.095087, 1.411692, 2.025835",\ + "0.754220, 1.002303, 1.196958, 1.513565, 2.127708",\ + "0.992078, 1.240161, 1.434817, 1.751422, 2.365565",\ + "1.564394, 1.812477, 2.007132, 2.323737, 2.937879",\ + "0.937147, 1.156000, 1.348922, 1.665098, 2.278399",\ + "0.986977, 1.205830, 1.398749, 1.714920, 2.328213",\ + "1.088848, 1.307701, 1.500621, 1.816792, 2.430086",\ + "1.326707, 1.545559, 1.738479, 2.054650, 2.667943",\ + "1.899023, 2.117875, 2.310795, 2.626965, 3.240257"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011"); + values ( "0.039738, 0.039738, 0.039733, 0.039724, 0.039707",\ + "0.147762, 0.147762, 0.147761, 0.147760, 0.147758",\ + "0.375020, 0.375020, 0.375020, 0.375022, 0.375024",\ + "0.869330, 0.869330, 0.869330, 0.869331, 0.869332",\ + "2.137214, 2.137214, 2.137214, 2.137214, 2.137215",\ + "0.039738, 0.039738, 0.039733, 0.039724, 0.039707",\ + "0.147762, 0.147762, 0.147761, 0.147760, 0.147758",\ + "0.375020, 0.375020, 0.375020, 0.375022, 0.375024",\ + "0.869330, 0.869330, 0.869330, 0.869331, 0.869332",\ + "2.137214, 2.137214, 2.137214, 2.137214, 2.137215",\ + "0.039738, 0.039738, 0.039733, 0.039724, 0.039707",\ + "0.147762, 0.147762, 0.147761, 0.147760, 0.147758",\ + "0.375020, 0.375020, 0.375020, 0.375022, 0.375024",\ + "0.869330, 0.869330, 0.869330, 0.869331, 0.869332",\ + "2.137214, 2.137214, 2.137214, 2.137214, 2.137215",\ + "0.039738, 0.039738, 0.039733, 0.039724, 0.039706",\ + "0.147762, 0.147762, 0.147761, 0.147760, 0.147758",\ + "0.375020, 0.375020, 0.375020, 0.375022, 0.375024",\ + "0.869330, 0.869330, 0.869330, 0.869331, 0.869332",\ + "2.137214, 2.137214, 2.137214, 2.137214, 2.137215",\ + "0.039738, 0.039738, 0.039733, 0.039724, 0.039706",\ + "0.147762, 0.147762, 0.147761, 0.147760, 0.147758",\ + "0.375020, 0.375020, 0.375020, 0.375022, 0.375024",\ + "0.869330, 0.869330, 0.869330, 0.869331, 0.869332",\ + "2.137214, 2.137214, 2.137214, 2.137215, 2.137215"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011"); + values ( "0.394276, 0.657755, 0.852725, 1.169033, 1.782342",\ + "0.424667, 0.688146, 0.883253, 1.200070, 1.814509",\ + "0.466031, 0.729510, 0.924618, 1.241435, 1.855873",\ + "0.588069, 0.851548, 1.046656, 1.363473, 1.977913",\ + "0.919687, 1.183166, 1.378274, 1.695092, 2.309533",\ + "0.482665, 0.745074, 0.940006, 1.256338, 1.869696",\ + "0.513056, 0.775464, 0.970534, 1.287375, 1.901862",\ + "0.554420, 0.816828, 1.011898, 1.328740, 1.943227",\ + "0.676459, 0.938867, 1.133937, 1.450778, 2.065267",\ + "1.008076, 1.270484, 1.465555, 1.782397, 2.396886",\ + "0.571801, 0.825408, 1.020033, 1.336366, 1.949727",\ + "0.602192, 0.855799, 1.050561, 1.367404, 1.981894",\ + "0.643556, 0.897163, 1.091925, 1.408768, 2.023258",\ + "0.765595, 1.019201, 1.213964, 1.530807, 2.145298",\ + "1.097212, 1.350819, 1.545582, 1.862426, 2.476918",\ + "0.635166, 0.883249, 1.077766, 1.393860, 2.006869",\ + "0.665557, 0.913640, 1.108294, 1.424899, 2.039039",\ + "0.706921, 0.955004, 1.149659, 1.466263, 2.080403",\ + "0.828959, 1.077042, 1.271697, 1.588302, 2.202443",\ + "1.160577, 1.408660, 1.603315, 1.919921, 2.534063",\ + "0.969795, 1.188647, 1.381428, 1.697086, 2.309244",\ + "1.000185, 1.219038, 1.411957, 1.728126, 2.341417",\ + "1.041550, 1.260402, 1.453321, 1.769491, 2.382781",\ + "1.163588, 1.382441, 1.575360, 1.891530, 2.504821",\ + "1.495205, 1.714058, 1.906978, 2.223148, 2.836441"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011"); + values ( "0.045860, 0.045860, 0.045861, 0.045861, 0.045862",\ + "0.091392, 0.091392, 0.091392, 0.091392, 0.091393",\ + "0.185815, 0.185815, 0.185815, 0.185815, 0.185816",\ + "0.432253, 0.432253, 0.432253, 0.432253, 0.432253",\ + "1.064246, 1.064246, 1.064246, 1.064246, 1.064246",\ + "0.045860, 0.045860, 0.045861, 0.045861, 0.045862",\ + "0.091392, 0.091392, 0.091392, 0.091392, 0.091393",\ + "0.185815, 0.185815, 0.185815, 0.185815, 0.185816",\ + "0.432253, 0.432253, 0.432253, 0.432253, 0.432253",\ + "1.064246, 1.064246, 1.064246, 1.064246, 1.064246",\ + "0.045860, 0.045860, 0.045861, 0.045861, 0.045862",\ + "0.091392, 0.091392, 0.091392, 0.091392, 0.091393",\ + "0.185815, 0.185815, 0.185815, 0.185815, 0.185816",\ + "0.432253, 0.432253, 0.432253, 0.432253, 0.432253",\ + "1.064246, 1.064246, 1.064246, 1.064246, 1.064246",\ + "0.045860, 0.045860, 0.045861, 0.045861, 0.045862",\ + "0.091392, 0.091392, 0.091392, 0.091392, 0.091393",\ + "0.185815, 0.185815, 0.185815, 0.185815, 0.185816",\ + "0.432253, 0.432253, 0.432253, 0.432253, 0.432253",\ + "1.064246, 1.064246, 1.064246, 1.064246, 1.064246",\ + "0.045860, 0.045860, 0.045861, 0.045861, 0.045862",\ + "0.091392, 0.091392, 0.091392, 0.091392, 0.091393",\ + "0.185815, 0.185815, 0.185815, 0.185815, 0.185816",\ + "0.432253, 0.432253, 0.432253, 0.432253, 0.432253",\ + "1.064246, 1.064246, 1.064246, 1.064246, 1.064246"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_min_2607*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[41]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.485123, 0.675497, 0.864625, 1.161795, 1.733234",\ + "0.533166, 0.723539, 0.912668, 1.209837, 1.781277",\ + "0.635232, 0.825605, 1.014734, 1.311903, 1.883343",\ + "0.865729, 1.056102, 1.245231, 1.542400, 2.113840",\ + "1.423621, 1.613994, 1.803123, 2.100292, 2.671732",\ + "0.573330, 0.762815, 0.951906, 1.249100, 1.820588",\ + "0.621373, 0.810857, 0.999949, 1.297143, 1.868630",\ + "0.723439, 0.912923, 1.102015, 1.399209, 1.970696",\ + "0.953936, 1.143420, 1.332512, 1.629706, 2.201193",\ + "1.511828, 1.701312, 1.890404, 2.187598, 2.759085",\ + "0.662165, 0.843147, 1.031933, 1.329129, 1.900620",\ + "0.710207, 0.891190, 1.079975, 1.377171, 1.948662",\ + "0.812273, 0.993256, 1.182042, 1.479237, 2.050728",\ + "1.042770, 1.223753, 1.412539, 1.709734, 2.281225",\ + "1.600662, 1.781645, 1.970431, 2.267626, 2.839117",\ + "0.722821, 0.900974, 1.089653, 1.386572, 1.957662",\ + "0.770863, 0.949017, 1.137696, 1.434614, 2.005704",\ + "0.872929, 1.051083, 1.239762, 1.536680, 2.107770",\ + "1.103426, 1.281580, 1.470258, 1.767177, 2.338267",\ + "1.661318, 1.839472, 2.028151, 2.325069, 2.896159",\ + "1.025458, 1.206267, 1.393313, 1.689754, 2.259915",\ + "1.073501, 1.254310, 1.441355, 1.737797, 2.307958",\ + "1.175567, 1.356376, 1.543421, 1.839863, 2.410024",\ + "1.406064, 1.586873, 1.773918, 2.070360, 2.640521",\ + "1.963956, 2.144765, 2.331810, 2.628252, 3.198413"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.036124, 0.036124, 0.036124, 0.036124, 0.036124",\ + "0.147307, 0.147307, 0.147307, 0.147307, 0.147307",\ + "0.375576, 0.375576, 0.375576, 0.375576, 0.375576",\ + "0.871150, 0.871150, 0.871150, 0.871150, 0.871150",\ + "2.136611, 2.136611, 2.136611, 2.136611, 2.136611",\ + "0.036124, 0.036124, 0.036124, 0.036124, 0.036124",\ + "0.147307, 0.147307, 0.147307, 0.147307, 0.147307",\ + "0.375576, 0.375576, 0.375576, 0.375576, 0.375576",\ + "0.871150, 0.871150, 0.871150, 0.871150, 0.871150",\ + "2.136611, 2.136611, 2.136611, 2.136611, 2.136611",\ + "0.036124, 0.036124, 0.036124, 0.036124, 0.036124",\ + "0.147307, 0.147307, 0.147307, 0.147307, 0.147307",\ + "0.375576, 0.375576, 0.375576, 0.375576, 0.375576",\ + "0.871150, 0.871150, 0.871150, 0.871150, 0.871150",\ + "2.136611, 2.136611, 2.136611, 2.136611, 2.136611",\ + "0.036124, 0.036124, 0.036124, 0.036124, 0.036124",\ + "0.147307, 0.147307, 0.147307, 0.147307, 0.147307",\ + "0.375576, 0.375576, 0.375576, 0.375576, 0.375576",\ + "0.871150, 0.871150, 0.871150, 0.871150, 0.871150",\ + "2.136611, 2.136611, 2.136611, 2.136611, 2.136611",\ + "0.036124, 0.036124, 0.036124, 0.036124, 0.036124",\ + "0.147307, 0.147307, 0.147307, 0.147307, 0.147307",\ + "0.375576, 0.375576, 0.375576, 0.375576, 0.375576",\ + "0.871150, 0.871150, 0.871150, 0.871150, 0.871150",\ + "2.136611, 2.136611, 2.136611, 2.136611, 2.136611"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.470306, 0.660679, 0.849808, 1.146978, 1.718417",\ + "0.508912, 0.699286, 0.888414, 1.185584, 1.757023",\ + "0.564040, 0.754413, 0.943542, 1.240712, 1.812151",\ + "0.696855, 0.887228, 1.076357, 1.373527, 1.944966",\ + "1.037356, 1.227730, 1.416858, 1.714028, 2.285468",\ + "0.558513, 0.747998, 0.937089, 1.234283, 1.805771",\ + "0.597120, 0.786604, 0.975695, 1.272889, 1.844377",\ + "0.652247, 0.841732, 1.030823, 1.328017, 1.899504",\ + "0.785062, 0.974547, 1.163638, 1.460832, 2.032320",\ + "1.125564, 1.315048, 1.504139, 1.801333, 2.372821",\ + "0.647348, 0.828330, 1.017116, 1.314311, 1.885802",\ + "0.685954, 0.866936, 1.055722, 1.352918, 1.924409",\ + "0.741081, 0.922064, 1.110850, 1.408045, 1.979536",\ + "0.873897, 1.054879, 1.243665, 1.540860, 2.112351",\ + "1.214398, 1.395380, 1.584166, 1.881362, 2.452853",\ + "0.708003, 0.886157, 1.074836, 1.371754, 1.942844",\ + "0.746610, 0.924764, 1.113442, 1.410361, 1.981451",\ + "0.801737, 0.979891, 1.168570, 1.465488, 2.036578",\ + "0.934552, 1.112706, 1.301385, 1.598303, 2.169393",\ + "1.275054, 1.453207, 1.641886, 1.938805, 2.509895",\ + "1.010641, 1.191450, 1.378495, 1.674937, 2.245098",\ + "1.049248, 1.230056, 1.417102, 1.713544, 2.283704",\ + "1.104375, 1.285184, 1.472229, 1.768671, 2.338832",\ + "1.237190, 1.417999, 1.605044, 1.901486, 2.471647",\ + "1.577692, 1.758500, 1.945546, 2.241987, 2.812148"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.039243, 0.039243, 0.039243, 0.039243, 0.039243",\ + "0.089116, 0.089116, 0.089116, 0.089116, 0.089116",\ + "0.185883, 0.185883, 0.185883, 0.185883, 0.185883",\ + "0.432255, 0.432255, 0.432255, 0.432255, 0.432255",\ + "1.064240, 1.064240, 1.064240, 1.064240, 1.064240",\ + "0.039243, 0.039243, 0.039243, 0.039243, 0.039243",\ + "0.089116, 0.089116, 0.089116, 0.089116, 0.089116",\ + "0.185883, 0.185883, 0.185883, 0.185883, 0.185883",\ + "0.432255, 0.432255, 0.432255, 0.432255, 0.432255",\ + "1.064240, 1.064240, 1.064240, 1.064240, 1.064240",\ + "0.039243, 0.039243, 0.039243, 0.039243, 0.039243",\ + "0.089116, 0.089116, 0.089116, 0.089116, 0.089116",\ + "0.185883, 0.185883, 0.185883, 0.185883, 0.185883",\ + "0.432255, 0.432255, 0.432255, 0.432255, 0.432255",\ + "1.064240, 1.064240, 1.064240, 1.064240, 1.064240",\ + "0.039243, 0.039243, 0.039243, 0.039243, 0.039243",\ + "0.089116, 0.089116, 0.089116, 0.089116, 0.089116",\ + "0.185883, 0.185883, 0.185883, 0.185883, 0.185883",\ + "0.432255, 0.432255, 0.432255, 0.432255, 0.432255",\ + "1.064240, 1.064240, 1.064240, 1.064240, 1.064240",\ + "0.039243, 0.039243, 0.039243, 0.039243, 0.039243",\ + "0.089116, 0.089116, 0.089116, 0.089116, 0.089116",\ + "0.185883, 0.185883, 0.185883, 0.185883, 0.185883",\ + "0.432255, 0.432255, 0.432255, 0.432255, 0.432255",\ + "1.064240, 1.064240, 1.064240, 1.064240, 1.064240"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_min_2372*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[42]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.459771, 0.648282, 0.825192, 1.109164, 1.658848",\ + "0.507814, 0.696324, 0.873234, 1.157206, 1.706890",\ + "0.609880, 0.798391, 0.975300, 1.259272, 1.808956",\ + "0.840377, 1.028888, 1.205797, 1.489769, 2.039453",\ + "1.398269, 1.586780, 1.763690, 2.047661, 2.597345",\ + "0.548200, 0.735600, 0.912473, 1.196469, 1.746201",\ + "0.596242, 0.783643, 0.960515, 1.244511, 1.794243",\ + "0.698308, 0.885709, 1.062581, 1.346577, 1.896309",\ + "0.928805, 1.116206, 1.293078, 1.577074, 2.126806",\ + "1.486698, 1.674098, 1.850971, 2.134966, 2.684699",\ + "0.637701, 0.815933, 0.992500, 1.276497, 1.826233",\ + "0.685743, 0.863975, 1.040542, 1.324540, 1.874275",\ + "0.787809, 0.966041, 1.142608, 1.426606, 1.976341",\ + "1.018306, 1.196538, 1.373105, 1.657103, 2.206838",\ + "1.576198, 1.754430, 1.930997, 2.214995, 2.764730",\ + "0.697261, 0.873753, 1.050191, 1.333914, 1.883222",\ + "0.745304, 0.921796, 1.098233, 1.381956, 1.931265",\ + "0.847370, 1.023862, 1.200299, 1.484022, 2.033331",\ + "1.077867, 1.254359, 1.430796, 1.714519, 2.263828",\ + "1.635759, 1.812251, 1.988688, 2.272411, 2.821720",\ + "0.999714, 1.179002, 1.353846, 1.637074, 2.185413",\ + "1.047756, 1.227044, 1.401888, 1.685117, 2.233455",\ + "1.149822, 1.329110, 1.503954, 1.787183, 2.335521",\ + "1.380320, 1.559607, 1.734451, 2.017680, 2.566018",\ + "1.938212, 2.117499, 2.292344, 2.575572, 3.123910"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.036124, 0.036124, 0.036124, 0.036124, 0.036124",\ + "0.147307, 0.147307, 0.147307, 0.147307, 0.147307",\ + "0.375576, 0.375576, 0.375576, 0.375576, 0.375576",\ + "0.871150, 0.871150, 0.871150, 0.871150, 0.871150",\ + "2.136611, 2.136611, 2.136611, 2.136611, 2.136611",\ + "0.036124, 0.036124, 0.036124, 0.036124, 0.036124",\ + "0.147307, 0.147307, 0.147307, 0.147307, 0.147307",\ + "0.375576, 0.375576, 0.375576, 0.375576, 0.375576",\ + "0.871150, 0.871150, 0.871150, 0.871150, 0.871150",\ + "2.136611, 2.136611, 2.136611, 2.136611, 2.136611",\ + "0.036124, 0.036124, 0.036124, 0.036124, 0.036124",\ + "0.147307, 0.147307, 0.147307, 0.147307, 0.147307",\ + "0.375576, 0.375576, 0.375576, 0.375576, 0.375576",\ + "0.871150, 0.871150, 0.871150, 0.871150, 0.871150",\ + "2.136611, 2.136611, 2.136611, 2.136611, 2.136611",\ + "0.036124, 0.036124, 0.036124, 0.036124, 0.036124",\ + "0.147307, 0.147307, 0.147307, 0.147307, 0.147307",\ + "0.375576, 0.375576, 0.375576, 0.375576, 0.375576",\ + "0.871150, 0.871150, 0.871150, 0.871150, 0.871150",\ + "2.136611, 2.136611, 2.136611, 2.136611, 2.136611",\ + "0.036124, 0.036124, 0.036124, 0.036124, 0.036124",\ + "0.147307, 0.147307, 0.147307, 0.147307, 0.147307",\ + "0.375576, 0.375576, 0.375576, 0.375576, 0.375576",\ + "0.871150, 0.871150, 0.871150, 0.871150, 0.871150",\ + "2.136611, 2.136611, 2.136611, 2.136611, 2.136611"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.444954, 0.633465, 0.810375, 1.094347, 1.644030",\ + "0.483561, 0.672071, 0.848981, 1.132953, 1.682637",\ + "0.538688, 0.727199, 0.904109, 1.188081, 1.737764",\ + "0.671503, 0.860014, 1.036924, 1.320896, 1.870579",\ + "1.012004, 1.200515, 1.377425, 1.661397, 2.211081",\ + "0.533383, 0.720783, 0.897656, 1.181652, 1.731384",\ + "0.571989, 0.759389, 0.936262, 1.220258, 1.769990",\ + "0.627117, 0.814517, 0.991390, 1.275386, 1.825118",\ + "0.759932, 0.947332, 1.124205, 1.408201, 1.957933",\ + "1.100433, 1.287833, 1.464706, 1.748702, 2.298434",\ + "0.622883, 0.801115, 0.977683, 1.261680, 1.811415",\ + "0.661490, 0.839722, 1.016289, 1.300287, 1.850022",\ + "0.716617, 0.894849, 1.071416, 1.355414, 1.905149",\ + "0.849432, 1.027664, 1.204232, 1.488229, 2.037964",\ + "1.189934, 1.368166, 1.544733, 1.828730, 2.378466",\ + "0.682444, 0.858936, 1.035374, 1.319097, 1.868405",\ + "0.721051, 0.897543, 1.073980, 1.357703, 1.907012",\ + "0.776178, 0.952670, 1.129108, 1.412831, 1.962139",\ + "0.908993, 1.085485, 1.261923, 1.545646, 2.094954",\ + "1.249495, 1.425987, 1.602424, 1.886147, 2.435456",\ + "0.984897, 1.164185, 1.339029, 1.622257, 2.170596",\ + "1.023503, 1.202791, 1.377635, 1.660863, 2.209202",\ + "1.078631, 1.257918, 1.432763, 1.715991, 2.264329",\ + "1.211446, 1.390733, 1.565578, 1.848806, 2.397144",\ + "1.551947, 1.731235, 1.906079, 2.189307, 2.737646"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.039243, 0.039243, 0.039243, 0.039243, 0.039243",\ + "0.089116, 0.089116, 0.089116, 0.089116, 0.089116",\ + "0.185883, 0.185883, 0.185883, 0.185883, 0.185883",\ + "0.432255, 0.432255, 0.432255, 0.432255, 0.432255",\ + "1.064240, 1.064240, 1.064240, 1.064240, 1.064240",\ + "0.039243, 0.039243, 0.039243, 0.039243, 0.039243",\ + "0.089116, 0.089116, 0.089116, 0.089116, 0.089116",\ + "0.185883, 0.185883, 0.185883, 0.185883, 0.185883",\ + "0.432255, 0.432255, 0.432255, 0.432255, 0.432255",\ + "1.064240, 1.064240, 1.064240, 1.064240, 1.064240",\ + "0.039243, 0.039243, 0.039243, 0.039243, 0.039243",\ + "0.089116, 0.089116, 0.089116, 0.089116, 0.089116",\ + "0.185883, 0.185883, 0.185883, 0.185883, 0.185883",\ + "0.432255, 0.432255, 0.432255, 0.432255, 0.432255",\ + "1.064240, 1.064240, 1.064240, 1.064240, 1.064240",\ + "0.039243, 0.039243, 0.039243, 0.039243, 0.039243",\ + "0.089116, 0.089116, 0.089116, 0.089116, 0.089116",\ + "0.185883, 0.185883, 0.185883, 0.185883, 0.185883",\ + "0.432255, 0.432255, 0.432255, 0.432255, 0.432255",\ + "1.064240, 1.064240, 1.064240, 1.064240, 1.064240",\ + "0.039243, 0.039243, 0.039243, 0.039243, 0.039243",\ + "0.089116, 0.089116, 0.089116, 0.089116, 0.089116",\ + "0.185883, 0.185883, 0.185883, 0.185883, 0.185883",\ + "0.432255, 0.432255, 0.432255, 0.432255, 0.432255",\ + "1.064240, 1.064240, 1.064240, 1.064240, 1.064240"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_min_2329*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[45]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011"); + values ( "0.301772, 0.506117, 0.689126, 0.977165, 1.531523",\ + "0.351626, 0.555943, 0.738945, 1.026979, 1.581328",\ + "0.453495, 0.657815, 0.840818, 1.128852, 1.683202",\ + "0.691355, 0.895673, 1.078675, 1.366709, 1.921058",\ + "1.263674, 1.467989, 1.650990, 1.939023, 2.493371",\ + "0.390122, 0.593435, 0.776407, 1.064470, 1.618876",\ + "0.439975, 0.643261, 0.826226, 1.114284, 1.668681",\ + "0.541844, 0.745133, 0.928099, 1.216157, 1.770555",\ + "0.779704, 0.982991, 1.165956, 1.454014, 2.008411",\ + "1.352023, 1.555307, 1.738271, 2.026328, 2.580724",\ + "0.479549, 0.673766, 0.856434, 1.144499, 1.698908",\ + "0.529399, 0.723592, 0.906253, 1.194312, 1.748713",\ + "0.631269, 0.825464, 1.008125, 1.296185, 1.850587",\ + "0.869129, 1.063322, 1.245983, 1.534042, 2.088443",\ + "1.441448, 1.635638, 1.818298, 2.106356, 2.660756",\ + "0.543362, 0.731582, 0.914140, 1.201921, 1.755909",\ + "0.593211, 0.781408, 0.963959, 1.251735, 1.805714",\ + "0.695080, 0.883280, 1.065832, 1.353608, 1.907588",\ + "0.932940, 1.121138, 1.303689, 1.591465, 2.145445",\ + "1.505259, 1.693454, 1.876004, 2.163779, 2.717757",\ + "0.859181, 1.036793, 1.217797, 1.505086, 2.058114",\ + "0.909031, 1.086618, 1.267616, 1.554900, 2.107919",\ + "1.010900, 1.188490, 1.369488, 1.656773, 2.209793",\ + "1.248760, 1.426348, 1.607346, 1.894630, 2.447649",\ + "1.821079, 1.998664, 2.179661, 2.466944, 3.019962"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011"); + values ( "0.039786, 0.039731, 0.039718, 0.039707, 0.039690",\ + "0.147768, 0.147761, 0.147759, 0.147758, 0.147756",\ + "0.375012, 0.375021, 0.375023, 0.375024, 0.375027",\ + "0.869318, 0.869319, 0.869321, 0.869323, 0.869326",\ + "2.137207, 2.137208, 2.137209, 2.137210, 2.137212",\ + "0.039784, 0.039731, 0.039718, 0.039707, 0.039690",\ + "0.147768, 0.147761, 0.147759, 0.147758, 0.147756",\ + "0.375012, 0.375021, 0.375023, 0.375024, 0.375027",\ + "0.869318, 0.869319, 0.869321, 0.869323, 0.869326",\ + "2.137207, 2.137208, 2.137209, 2.137210, 2.137212",\ + "0.039780, 0.039731, 0.039718, 0.039707, 0.039690",\ + "0.147767, 0.147761, 0.147759, 0.147758, 0.147756",\ + "0.375013, 0.375021, 0.375023, 0.375024, 0.375027",\ + "0.869318, 0.869319, 0.869321, 0.869323, 0.869326",\ + "2.137207, 2.137208, 2.137209, 2.137210, 2.137212",\ + "0.039776, 0.039731, 0.039718, 0.039707, 0.039690",\ + "0.147767, 0.147761, 0.147759, 0.147758, 0.147756",\ + "0.375014, 0.375021, 0.375023, 0.375024, 0.375027",\ + "0.869318, 0.869319, 0.869321, 0.869323, 0.869326",\ + "2.137207, 2.137208, 2.137209, 2.137210, 2.137212",\ + "0.039779, 0.039730, 0.039718, 0.039707, 0.039690",\ + "0.147767, 0.147761, 0.147759, 0.147758, 0.147756",\ + "0.375013, 0.375021, 0.375023, 0.375024, 0.375027",\ + "0.869318, 0.869319, 0.869321, 0.869323, 0.869326",\ + "2.137207, 2.137208, 2.137209, 2.137210, 2.137212"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011"); + values ( "0.335876, 0.546804, 0.729804, 1.017837, 1.572184",\ + "0.364841, 0.569151, 0.752151, 1.040183, 1.594529",\ + "0.406205, 0.610515, 0.793515, 1.081547, 1.635894",\ + "0.528241, 0.732554, 0.915554, 1.203587, 1.757934",\ + "0.859855, 1.064172, 1.247173, 1.535207, 2.089556",\ + "0.424190, 0.634122, 0.817085, 1.105142, 1.659538",\ + "0.453190, 0.656469, 0.839432, 1.127488, 1.681883",\ + "0.494554, 0.697833, 0.880796, 1.168852, 1.723248",\ + "0.616590, 0.819872, 1.002835, 1.290892, 1.845288",\ + "0.948204, 1.151490, 1.334454, 1.622512, 2.176909",\ + "0.513507, 0.714453, 0.897112, 1.185170, 1.739569",\ + "0.542614, 0.736800, 0.919459, 1.207516, 1.761914",\ + "0.583978, 0.778164, 0.960823, 1.248881, 1.803279",\ + "0.706014, 0.900203, 1.082862, 1.370920, 1.925319",\ + "1.037629, 1.231821, 1.414481, 1.702540, 2.256941",\ + "0.577218, 0.772269, 0.954818, 1.242593, 1.796571",\ + "0.606425, 0.794616, 0.977165, 1.264939, 1.818916",\ + "0.647789, 0.835980, 1.018529, 1.306303, 1.860281",\ + "0.769825, 0.958019, 1.140568, 1.428343, 1.982321",\ + "1.101440, 1.289637, 1.472187, 1.759963, 2.313942",\ + "0.899896, 1.077479, 1.258475, 1.545758, 2.098775",\ + "0.922245, 1.099826, 1.280822, 1.568104, 2.121120",\ + "0.963609, 1.141190, 1.322186, 1.609468, 2.162485",\ + "1.085645, 1.263229, 1.444225, 1.731508, 2.284525",\ + "1.417260, 1.594847, 1.775844, 2.063128, 2.616147"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011"); + values ( "0.045857, 0.045861, 0.045862, 0.045862, 0.045864",\ + "0.091390, 0.091392, 0.091392, 0.091393, 0.091393",\ + "0.185814, 0.185815, 0.185815, 0.185816, 0.185816",\ + "0.432252, 0.432253, 0.432253, 0.432253, 0.432253",\ + "1.064247, 1.064246, 1.064246, 1.064246, 1.064246",\ + "0.045857, 0.045861, 0.045862, 0.045862, 0.045864",\ + "0.091390, 0.091392, 0.091392, 0.091393, 0.091393",\ + "0.185814, 0.185815, 0.185815, 0.185816, 0.185816",\ + "0.432252, 0.432253, 0.432253, 0.432253, 0.432253",\ + "1.064247, 1.064246, 1.064246, 1.064246, 1.064246",\ + "0.045857, 0.045861, 0.045862, 0.045862, 0.045864",\ + "0.091390, 0.091392, 0.091392, 0.091393, 0.091393",\ + "0.185814, 0.185815, 0.185815, 0.185816, 0.185816",\ + "0.432252, 0.432253, 0.432253, 0.432253, 0.432253",\ + "1.064247, 1.064246, 1.064246, 1.064246, 1.064246",\ + "0.045857, 0.045861, 0.045862, 0.045862, 0.045864",\ + "0.091390, 0.091392, 0.091392, 0.091393, 0.091393",\ + "0.185814, 0.185815, 0.185815, 0.185816, 0.185816",\ + "0.432252, 0.432253, 0.432253, 0.432253, 0.432253",\ + "1.064247, 1.064246, 1.064246, 1.064246, 1.064246",\ + "0.045857, 0.045861, 0.045862, 0.045862, 0.045864",\ + "0.091390, 0.091392, 0.091392, 0.091393, 0.091393",\ + "0.185814, 0.185815, 0.185815, 0.185816, 0.185816",\ + "0.432252, 0.432253, 0.432253, 0.432253, 0.432253",\ + "1.064247, 1.064246, 1.064246, 1.064246, 1.064246"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_min_2545*/ + +} /* end of pin tl_o[2] */ + +pin("tl_o[1]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001509 ; + + /* Other user defined attributes. */ + original_pin : tl_o[1]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011"); + values ( "0.046822, 0.200204, 0.375821, 0.698828, 1.344843",\ + "0.133063, 0.287379, 0.462927, 0.785543, 1.430777",\ + "0.215932, 0.375508, 0.550883, 0.873166, 1.517732",\ + "0.273510, 0.439904, 0.614999, 0.937080, 1.581241",\ + "0.571476, 0.789768, 0.965387, 1.285824, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011"); + values ( "0.022274, 0.297864, 0.631591, 1.248582, 2.482564",\ + "0.026983, 0.298841, 0.633546, 1.248582, 2.482564",\ + "0.040131, 0.301114, 0.633582, 1.248582, 2.482564",\ + "0.052012, 0.304418, 0.633682, 1.248582, 2.482564",\ + "0.127272, 0.343015, 0.639946, 1.251147, 2.482564"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011"); + values ( "0.066617, 0.172302, 0.283906, 0.488180, 0.896728",\ + "0.154032, 0.259620, 0.371187, 0.575485, 0.984081",\ + "0.234373, 0.339957, 0.451214, 0.655513, 1.064113",\ + "0.291019, 0.397505, 0.508757, 0.712758, 1.120761",\ + "0.584343, 0.700840, 0.812391, 1.015773, 1.422537"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011"); + values ( "0.023322, 0.186287, 0.386928, 0.759411, 1.504378",\ + "0.023322, 0.186429, 0.387433, 0.759411, 1.504378",\ + "0.024460, 0.186429, 0.387433, 0.759411, 1.504378",\ + "0.026582, 0.186429, 0.387433, 0.759411, 1.504378",\ + "0.045430, 0.190441, 0.387433, 0.759411, 1.504658"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[1]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011"); + values ( "0.046822, 0.200204, 0.375821, 0.698828, 1.344843",\ + "0.133063, 0.287379, 0.462927, 0.785543, 1.430777",\ + "0.215932, 0.375508, 0.550883, 0.873166, 1.517732",\ + "0.273510, 0.439904, 0.614999, 0.937080, 1.581241",\ + "0.571476, 0.789768, 0.965387, 1.285824, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011"); + values ( "0.022274, 0.297864, 0.631591, 1.247358, 2.473548",\ + "0.026983, 0.298841, 0.633546, 1.247358, 2.473548",\ + "0.040131, 0.301114, 0.633582, 1.247433, 2.473548",\ + "0.052012, 0.304418, 0.633682, 1.248176, 2.473548",\ + "0.127272, 0.343015, 0.639946, 1.251147, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011"); + values ( "0.066617, 0.172302, 0.283906, 0.488180, 0.896728",\ + "0.154032, 0.259620, 0.371187, 0.575485, 0.984081",\ + "0.234373, 0.339957, 0.451214, 0.655513, 1.064113",\ + "0.291019, 0.397505, 0.508757, 0.712758, 1.120761",\ + "0.584343, 0.700840, 0.812391, 1.015773, 1.422537"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011"); + values ( "0.023322, 0.185492, 0.385423, 0.757182, 1.500701",\ + "0.023322, 0.185492, 0.385423, 0.757182, 1.500701",\ + "0.024460, 0.185492, 0.385423, 0.757182, 1.500701",\ + "0.026582, 0.186104, 0.385879, 0.758083, 1.502492",\ + "0.045430, 0.190441, 0.385949, 0.758852, 1.504658"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[1]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.022274, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.215141, 0.169212, 0.139013, 0.127669, 0.141354",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.023322, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.250035, 0.174713, 0.106554, 0.083587, 0.146501",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[1]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.022274, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.147068, -0.104651, -0.070164, -0.030741, 0.275306",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.023322, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.163191, -0.097276, -0.039617, 0.002344, 0.222952",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[1]_hldr*/ + +} /* end of pin tl_o[1] */ + +pin("tl_o[0]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.044859 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : tl_o[0]; + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[65]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000590, 0.001754, 0.015524, 0.044859"); + index_3 ( "0.000991, 0.073990, 0.161246, 0.321501, 0.642011"); + values ( "0.097208, 0.256769, 0.409091, 0.656426, 1.137408",\ + "0.115461, 0.284095, 0.450445, 0.715246, 1.227124",\ + "0.150308, 0.323698, 0.505958, 0.792733, 1.344666",\ + "0.555435, 0.728531, 0.927338, 1.279607, 1.977668",\ + "1.416767, 1.591727, 1.785882, 2.145544, 2.866017",\ + "0.184700, 0.344133, 0.496471, 0.743731, 1.224761",\ + "0.202953, 0.371467, 0.537861, 0.802551, 1.314477",\ + "0.237800, 0.411073, 0.593415, 0.880038, 1.432020",\ + "0.642927, 0.815906, 1.014839, 1.366912, 2.065021",\ + "1.504259, 1.679104, 1.873371, 2.232849, 2.953371",\ + "0.265280, 0.424472, 0.576498, 0.823760, 1.304793",\ + "0.283590, 0.451806, 0.617887, 0.882580, 1.394509",\ + "0.318468, 0.491412, 0.673442, 0.960067, 1.512051",\ + "0.723592, 0.896245, 1.094866, 1.446940, 2.145053",\ + "1.584936, 1.759443, 1.953398, 2.312878, 3.033402",\ + "0.322520, 0.482020, 0.634043, 0.881006, 1.361440",\ + "0.340954, 0.509354, 0.675432, 0.939825, 1.451157",\ + "0.375896, 0.548960, 0.730986, 1.017312, 1.568699",\ + "0.781016, 0.953793, 1.152410, 1.504186, 2.201700",\ + "1.642386, 1.816991, 2.010942, 2.370123, 3.090050",\ + "0.620809, 0.786662, 0.937678, 1.184021, 1.663244",\ + "0.640290, 0.814221, 0.979067, 1.242841, 1.752972",\ + "0.675782, 0.853946, 1.034621, 1.320328, 1.870529",\ + "1.080868, 1.258772, 1.456046, 1.807201, 2.503586",\ + "1.942453, 2.122015, 2.314578, 2.673139, 3.391944"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000590, 0.001754, 0.015524, 0.044859"); + index_3 ( "0.000991, 0.073990, 0.161246, 0.321501, 0.642011"); + values ( "0.031051, 0.064939, 0.106507, 0.168112, 0.284243",\ + "0.062823, 0.089481, 0.136238, 0.207829, 0.343471",\ + "0.126154, 0.132352, 0.184740, 0.267437, 0.424225",\ + "0.854886, 0.854886, 0.855036, 0.913502, 1.057002",\ + "2.399794, 2.399794, 2.399794, 2.406500, 2.422973",\ + "0.031051, 0.064968, 0.106612, 0.168112, 0.284243",\ + "0.062823, 0.089504, 0.136357, 0.207829, 0.343471",\ + "0.126154, 0.132357, 0.184878, 0.267437, 0.424225",\ + "0.854886, 0.854886, 0.855037, 0.913502, 1.057002",\ + "2.399794, 2.399794, 2.399794, 2.406500, 2.422973",\ + "0.031266, 0.064968, 0.106612, 0.168112, 0.284243",\ + "0.062992, 0.089504, 0.136357, 0.207829, 0.343471",\ + "0.126193, 0.132357, 0.184878, 0.267437, 0.424225",\ + "0.854886, 0.854886, 0.855037, 0.913502, 1.057002",\ + "2.399794, 2.399794, 2.399794, 2.406500, 2.422973",\ + "0.031727, 0.064968, 0.106612, 0.168112, 0.284243",\ + "0.063355, 0.089504, 0.136357, 0.207829, 0.343471",\ + "0.126277, 0.132357, 0.184878, 0.267437, 0.424225",\ + "0.854886, 0.854886, 0.855037, 0.913502, 1.057002",\ + "2.399794, 2.399794, 2.399794, 2.406500, 2.422973",\ + "0.035640, 0.065810, 0.106612, 0.168112, 0.284287",\ + "0.066433, 0.090167, 0.136357, 0.207829, 0.343522",\ + "0.126993, 0.132511, 0.184878, 0.267437, 0.424284",\ + "0.854886, 0.854886, 0.855037, 0.913502, 1.057056",\ + "2.399794, 2.399794, 2.399794, 2.406500, 2.422979"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000590, 0.001754, 0.015524, 0.044859"); + index_3 ( "0.000991, 0.073990, 0.161246, 0.321501, 0.642011"); + values ( "0.062809, 0.283388, 0.498683, 0.866951, 1.603486",\ + "0.068905, 0.306781, 0.537627, 0.930389, 1.715913",\ + "0.080269, 0.336426, 0.586045, 1.007586, 1.850669",\ + "0.212849, 0.497229, 0.809203, 1.343143, 2.411022",\ + "0.495174, 0.777787, 1.106916, 1.706802, 2.906575",\ + "0.150255, 0.370725, 0.585933, 0.953667, 1.689420",\ + "0.156684, 0.394170, 0.624955, 1.017105, 1.801846",\ + "0.168373, 0.423879, 0.673464, 1.094302, 1.936603",\ + "0.301203, 0.584867, 0.896980, 1.429859, 2.496955",\ + "0.583505, 0.865416, 1.194902, 1.793518, 2.992509",\ + "0.236169, 0.459238, 0.673893, 1.041290, 1.776375",\ + "0.243498, 0.482807, 0.712916, 1.104728, 1.888801",\ + "0.256066, 0.512668, 0.761427, 1.181925, 2.023558",\ + "0.389574, 0.674096, 0.984949, 1.517482, 2.583910",\ + "0.671814, 0.954623, 1.282876, 1.881141, 3.079464",\ + "0.296494, 0.524194, 0.738017, 1.105204, 1.839884",\ + "0.304623, 0.547943, 0.777044, 1.168642, 1.952310",\ + "0.317970, 0.578026, 0.825559, 1.245839, 2.087067",\ + "0.452080, 0.740091, 1.049099, 1.581396, 2.647419",\ + "0.734265, 1.020587, 1.347036, 1.945055, 3.142973",\ + "0.612030, 0.880553, 1.088866, 1.454138, 2.185340",\ + "0.625211, 0.906402, 1.128142, 1.517678, 2.297766",\ + "0.643489, 0.939075, 1.176949, 1.594995, 2.432523",\ + "0.781402, 1.108582, 1.401631, 1.931020, 2.992876",\ + "1.063240, 1.388711, 1.700238, 2.294955, 3.488429"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000590, 0.001754, 0.015524, 0.044859"); + index_3 ( "0.000991, 0.073990, 0.161246, 0.321501, 0.642011"); + values ( "0.011160, 0.064436, 0.116932, 0.202254, 0.372899",\ + "0.020800, 0.078264, 0.137685, 0.234686, 0.428687",\ + "0.041454, 0.098634, 0.166400, 0.277542, 0.499826",\ + "0.284826, 0.291930, 0.346150, 0.498019, 0.801757",\ + "0.801745, 0.802553, 0.834131, 0.941202, 1.155343",\ + "0.012155, 0.064608, 0.117203, 0.202254, 0.372899",\ + "0.021847, 0.078458, 0.137993, 0.234686, 0.428687",\ + "0.042416, 0.098854, 0.166753, 0.277542, 0.499826",\ + "0.284826, 0.291998, 0.346632, 0.498019, 0.801757",\ + "0.801745, 0.802560, 0.834471, 0.941202, 1.155343",\ + "0.014841, 0.065015, 0.117208, 0.202254, 0.372899",\ + "0.024678, 0.078917, 0.137999, 0.234686, 0.428687",\ + "0.045017, 0.099375, 0.166760, 0.277542, 0.499826",\ + "0.284826, 0.292159, 0.346641, 0.498019, 0.801757",\ + "0.801745, 0.802579, 0.834477, 0.941202, 1.155343",\ + "0.017226, 0.065607, 0.117221, 0.202254, 0.372899",\ + "0.027191, 0.079585, 0.138014, 0.234686, 0.428687",\ + "0.047325, 0.100134, 0.166777, 0.277542, 0.499826",\ + "0.284826, 0.292394, 0.346665, 0.498019, 0.801757",\ + "0.801745, 0.802605, 0.834494, 0.941202, 1.155343",\ + "0.032302, 0.072514, 0.118088, 0.202610, 0.372899",\ + "0.043078, 0.087374, 0.139000, 0.235090, 0.428687",\ + "0.061921, 0.108981, 0.167906, 0.278005, 0.499826",\ + "0.284826, 0.295133, 0.348208, 0.498652, 0.801757",\ + "0.801745, 0.802917, 0.835582, 0.941648, 1.155343"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[0]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[65]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000590, 0.001754, 0.015524, 0.044859"); + index_3 ( "0.000991, 0.073990, 0.161246, 0.321501, 0.642011"); + values ( "0.091649, 0.250131, 0.402296, 0.649078, 1.128418",\ + "0.104662, 0.273549, 0.438178, 0.701696, 1.211503",\ + "0.129595, 0.307072, 0.486657, 0.770890, 1.318582",\ + "0.419859, 0.596841, 0.797852, 1.150232, 1.846445",\ + "1.036012, 1.213814, 1.416984, 1.786820, 2.524206",\ + "0.179141, 0.337450, 0.489577, 0.736383, 1.215771",\ + "0.192154, 0.360868, 0.525459, 0.789001, 1.298857",\ + "0.217087, 0.394391, 0.573938, 0.858195, 1.405936",\ + "0.507351, 0.684160, 0.885133, 1.237537, 1.933798",\ + "1.123504, 1.301133, 1.504265, 1.874125, 2.611559",\ + "0.259715, 0.417789, 0.569604, 0.816412, 1.295803",\ + "0.272795, 0.441207, 0.605486, 0.869029, 1.378888",\ + "0.297783, 0.474730, 0.653965, 0.938223, 1.485967",\ + "0.588044, 0.764499, 0.965159, 1.317566, 2.013830",\ + "1.204202, 1.381472, 1.584292, 1.954154, 2.691591",\ + "0.316944, 0.475532, 0.627237, 0.873742, 1.352620",\ + "0.330166, 0.498989, 0.663147, 0.926397, 1.435779",\ + "0.355271, 0.532545, 0.711661, 0.995637, 1.542949",\ + "0.645525, 0.822313, 1.022907, 1.375159, 2.071169",\ + "1.261694, 1.439288, 1.642045, 2.011797, 2.749029",\ + "0.615137, 0.780253, 0.930886, 1.176831, 1.654602",\ + "0.629566, 0.803991, 0.966800, 1.229517, 1.737849",\ + "0.655668, 0.837777, 1.015319, 1.298796, 1.845130",\ + "0.945865, 1.127532, 1.326573, 1.678471, 2.373782",\ + "1.562129, 1.744529, 1.945711, 2.315152, 3.051762"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000590, 0.001754, 0.015524, 0.044859"); + index_3 ( "0.000991, 0.073990, 0.161246, 0.321501, 0.642011"); + values ( "0.022568, 0.058250, 0.097501, 0.158155, 0.273924",\ + "0.045222, 0.077904, 0.123497, 0.193808, 0.327390",\ + "0.090348, 0.107489, 0.163971, 0.245678, 0.396404",\ + "0.621445, 0.621445, 0.621445, 0.691541, 0.864683",\ + "1.751287, 1.751287, 1.752785, 1.770247, 1.811996",\ + "0.022568, 0.058250, 0.097501, 0.158155, 0.273924",\ + "0.045222, 0.077904, 0.123497, 0.193808, 0.327390",\ + "0.090348, 0.107489, 0.163971, 0.245678, 0.396404",\ + "0.621445, 0.621445, 0.621445, 0.691541, 0.864683",\ + "1.751287, 1.751287, 1.752785, 1.770247, 1.811996",\ + "0.022795, 0.058250, 0.097501, 0.158155, 0.273924",\ + "0.045430, 0.077904, 0.123497, 0.193808, 0.327390",\ + "0.090457, 0.107489, 0.163971, 0.245678, 0.396404",\ + "0.621445, 0.621445, 0.621445, 0.691541, 0.864683",\ + "1.751287, 1.751287, 1.752785, 1.770247, 1.811996",\ + "0.023283, 0.058385, 0.097589, 0.158295, 0.274203",\ + "0.045877, 0.078027, 0.123601, 0.193969, 0.327712",\ + "0.090692, 0.107553, 0.164104, 0.245861, 0.396767",\ + "0.621445, 0.621445, 0.621445, 0.691750, 0.865100",\ + "1.751287, 1.751287, 1.752788, 1.770297, 1.812096",\ + "0.027423, 0.059345, 0.097603, 0.158415, 0.274540",\ + "0.049669, 0.078907, 0.123617, 0.194107, 0.328101",\ + "0.092680, 0.108015, 0.164124, 0.246016, 0.397205",\ + "0.621445, 0.621445, 0.621445, 0.691929, 0.865604",\ + "1.751287, 1.751287, 1.752789, 1.770340, 1.812218"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000590, 0.001754, 0.015524, 0.044859"); + index_3 ( "0.000991, 0.073990, 0.161246, 0.321501, 0.642011"); + values ( "0.062799, 0.282922, 0.497986, 0.866154, 1.602100",\ + "0.068878, 0.306290, 0.537336, 0.930038, 1.714836",\ + "0.080236, 0.335964, 0.585498, 1.006969, 1.849055",\ + "0.212818, 0.496736, 0.807979, 1.341514, 2.406755",\ + "0.493894, 0.777156, 1.106499, 1.705590, 2.901373",\ + "0.150236, 0.370257, 0.585236, 0.952870, 1.688034",\ + "0.156640, 0.393680, 0.624665, 1.016754, 1.800770",\ + "0.168330, 0.423416, 0.672918, 1.093685, 1.934989",\ + "0.301173, 0.584370, 0.895755, 1.428230, 2.492689",\ + "0.582238, 0.864786, 1.194485, 1.792306, 2.987307",\ + "0.236126, 0.458767, 0.673196, 1.040499, 1.774989",\ + "0.243411, 0.482319, 0.712626, 1.104385, 1.887725",\ + "0.255996, 0.512204, 0.760881, 1.181320, 2.021944",\ + "0.389544, 0.673587, 0.983724, 1.515878, 2.579644",\ + "0.670583, 0.953997, 1.282458, 1.879963, 3.074262",\ + "0.296431, 0.523718, 0.737319, 1.104467, 1.838498",\ + "0.304497, 0.547459, 0.776753, 1.168383, 1.951234",\ + "0.317876, 0.577559, 0.825013, 1.245352, 2.085453",\ + "0.452050, 0.739568, 1.047875, 1.580045, 2.643153",\ + "0.733066, 1.019967, 1.346619, 1.944209, 3.137771",\ + "0.611833, 0.880022, 1.088168, 1.453430, 2.183954",\ + "0.624839, 0.905962, 1.127852, 1.517465, 2.296690",\ + "0.643244, 0.938579, 1.176404, 1.594573, 2.430909",\ + "0.781372, 1.107880, 1.400406, 1.929807, 2.988609",\ + "1.062240, 1.388161, 1.699817, 2.294288, 3.483227"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000590, 0.001754, 0.015524, 0.044859"); + index_3 ( "0.000991, 0.073990, 0.161246, 0.321501, 0.642011"); + values ( "0.011131, 0.063936, 0.115966, 0.201201, 0.370930",\ + "0.020777, 0.078242, 0.137616, 0.234279, 0.426765",\ + "0.041132, 0.097162, 0.164744, 0.275022, 0.494619",\ + "0.282873, 0.290343, 0.344847, 0.495374, 0.795117",\ + "0.794988, 0.797692, 0.832143, 0.938552, 1.150445",\ + "0.012121, 0.064104, 0.116237, 0.201201, 0.370930",\ + "0.021825, 0.078435, 0.137924, 0.234279, 0.426765",\ + "0.042062, 0.097382, 0.165095, 0.275022, 0.494619",\ + "0.282873, 0.290415, 0.345327, 0.495374, 0.795117",\ + "0.794988, 0.797718, 0.832482, 0.938552, 1.150445",\ + "0.014795, 0.064505, 0.116242, 0.201211, 0.370930",\ + "0.024656, 0.078894, 0.137930, 0.234291, 0.426765",\ + "0.044575, 0.097903, 0.165102, 0.275036, 0.494619",\ + "0.282873, 0.290585, 0.345336, 0.495392, 0.795117",\ + "0.794988, 0.797779, 0.832488, 0.938565, 1.150445",\ + "0.017168, 0.065086, 0.116256, 0.201314, 0.370930",\ + "0.027169, 0.079562, 0.137945, 0.234407, 0.426765",\ + "0.046806, 0.098662, 0.165119, 0.275169, 0.494619",\ + "0.282873, 0.290832, 0.345360, 0.495573, 0.795117",\ + "0.794988, 0.797869, 0.832505, 0.938693, 1.150445",\ + "0.032175, 0.071874, 0.117123, 0.201725, 0.370930",\ + "0.043057, 0.087350, 0.138929, 0.234874, 0.426765",\ + "0.060912, 0.107509, 0.166242, 0.275701, 0.494619",\ + "0.282873, 0.293712, 0.346892, 0.496300, 0.795117",\ + "0.794988, 0.798911, 0.833588, 0.939207, 1.150445"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[0]_redg_min*/ + +} /* end of pin tl_o[0] */ +} /* end of bus tl_o */ + +pin("ast_init_done_o") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000556 ; + + /* Other user defined attributes. */ + original_pin : ast_init_done_o; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000556, 0.073554, 0.160919, 0.321283, 0.642011"); + values ( "0.043384, 0.198284, 0.374379, 0.697867, 1.344843",\ + "0.129257, 0.285459, 0.461486, 0.784583, 1.430777",\ + "0.210733, 0.373589, 0.549444, 0.872207, 1.517732",\ + "0.267175, 0.437989, 0.613561, 0.936121, 1.581241",\ + "0.558327, 0.787842, 0.963956, 1.284870, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000556, 0.073554, 0.160919, 0.321283, 0.642011"); + values ( "0.018706, 0.294221, 0.628837, 1.246746, 2.482563",\ + "0.023795, 0.295177, 0.630806, 1.246746, 2.482563",\ + "0.037168, 0.297482, 0.630842, 1.246746, 2.482563",\ + "0.048861, 0.300835, 0.630939, 1.246746, 2.482563",\ + "0.122687, 0.339900, 0.637218, 1.249328, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000556, 0.073554, 0.160919, 0.321283, 0.642011"); + values ( "0.063197, 0.171101, 0.283015, 0.487593, 0.896749",\ + "0.150760, 0.258420, 0.370296, 0.574898, 0.984103",\ + "0.230918, 0.338761, 0.450323, 0.654927, 1.064134",\ + "0.287331, 0.396309, 0.507868, 0.712173, 1.120782",\ + "0.578538, 0.699638, 0.811505, 1.015189, 1.422559"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000556, 0.073554, 0.160919, 0.321283, 0.642011"); + values ( "0.020743, 0.184138, 0.385305, 0.758342, 1.504417",\ + "0.020743, 0.184274, 0.385812, 0.758342, 1.504417",\ + "0.021682, 0.184274, 0.385812, 0.758342, 1.504417",\ + "0.023987, 0.184274, 0.385812, 0.758342, 1.504417",\ + "0.042807, 0.188367, 0.385812, 0.758342, 1.504697"); + } + + } /* end of arc clk_ast_tlul_i_ast_init_done_o_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000556, 0.073554, 0.160919, 0.321283, 0.642011"); + values ( "0.043384, 0.198284, 0.374379, 0.697867, 1.344843",\ + "0.129257, 0.285459, 0.461486, 0.784583, 1.430777",\ + "0.210733, 0.373589, 0.549444, 0.872207, 1.517732",\ + "0.267175, 0.437989, 0.613561, 0.936121, 1.581241",\ + "0.558327, 0.787842, 0.963956, 1.284870, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000556, 0.073554, 0.160919, 0.321283, 0.642011"); + values ( "0.018706, 0.294221, 0.628837, 1.245531, 2.473548",\ + "0.023795, 0.295177, 0.630806, 1.245531, 2.473548",\ + "0.037168, 0.297482, 0.630842, 1.245606, 2.473548",\ + "0.048861, 0.300835, 0.630939, 1.246347, 2.473548",\ + "0.122687, 0.339900, 0.637218, 1.249328, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000556, 0.073554, 0.160919, 0.321283, 0.642011"); + values ( "0.063197, 0.171101, 0.283015, 0.487593, 0.896749",\ + "0.150760, 0.258420, 0.370296, 0.574898, 0.984103",\ + "0.230918, 0.338761, 0.450323, 0.654927, 1.064134",\ + "0.287331, 0.396309, 0.507868, 0.712173, 1.120782",\ + "0.578538, 0.699638, 0.811505, 1.015189, 1.422559"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000556, 0.073554, 0.160919, 0.321283, 0.642011"); + values ( "0.020743, 0.183352, 0.383802, 0.756115, 1.500740",\ + "0.020743, 0.183352, 0.383802, 0.756115, 1.500740",\ + "0.021682, 0.183352, 0.383802, 0.756115, 1.500740",\ + "0.023987, 0.183968, 0.384256, 0.757015, 1.502532",\ + "0.042807, 0.188367, 0.384324, 0.757782, 1.504697"); + } + + } /* end of arc clk_ast_tlul_i_ast_init_done_o_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018706, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.166278, 0.120559, 0.090376, 0.079044, 0.092801",\ + "0.171862, 0.126143, 0.095959, 0.084628, 0.098385",\ + "0.245234, 0.199449, 0.169261, 0.157926, 0.171660",\ + "0.322551, 0.276573, 0.246370, 0.235023, 0.248691",\ + "0.666536, 0.618843, 0.588507, 0.577057, 0.590140"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020743, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.195653, 0.120302, 0.052066, 0.028959, 0.090570",\ + "0.201000, 0.125650, 0.057413, 0.034307, 0.095918",\ + "0.271909, 0.196575, 0.128353, 0.105282, 0.167257",\ + "0.351861, 0.276541, 0.208391, 0.185439, 0.248491",\ + "0.700887, 0.625677, 0.558111, 0.536111, 0.607801"); + } + + } /* end of arc clk_ast_tlul_i_ast_init_done_o_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018706, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.098385, -0.055930, -0.021532, 0.019602, 0.346880",\ + "-0.103969, -0.061514, -0.027115, 0.014019, 0.341296",\ + "-0.177290, -0.134846, -0.100420, -0.059816, 0.260884",\ + "-0.254454, -0.212046, -0.177538, -0.138520, 0.162505",\ + "-0.597087, -0.554990, -0.519760, -0.494735, -0.367407"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020743, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.108800, -0.043157, 0.014117, 0.055975, 0.277251",\ + "-0.114148, -0.048505, 0.008770, 0.050627, 0.271903",\ + "-0.185082, -0.119364, -0.061987, -0.020103, 0.200995",\ + "-0.265110, -0.199164, -0.141461, -0.099488, 0.121043",\ + "-0.614747, -0.546974, -0.486651, -0.443970, -0.227977"); + } + + } /* end of arc clk_ast_tlul_i_ast_init_done_o_hldr*/ + +} /* end of pin ast_init_done_o */ + +pin("clk_ast_adc_i") { + direction : input ; + clock : true ; + max_transition : 2.480000 ; + capacitance : 0.009042 ; + + /* Other user defined attributes. */ + original_pin : clk_ast_adc_i; + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : min_pulse_width ; + fall_constraint( scalar ){ + values ( "0.151080"); + } + + } /* end of arc clk_ast_adc_i_clk_ast_adc_i_pwl*/ + + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : min_pulse_width ; + rise_constraint( scalar ){ + values ( "0.077628"); + } + + } /* end of arc clk_ast_adc_i_clk_ast_adc_i_pwh*/ + +} /* end of pin clk_ast_adc_i */ + +pin("rst_ast_adc_ni") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.009042 ; + + /* Other user defined attributes. */ + original_pin : rst_ast_adc_ni; + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : recovery_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.274432, 0.227738, 0.193623, 0.189926, 0.219386",\ + "0.355422, 0.308727, 0.274612, 0.270915, 0.300375",\ + "0.429898, 0.383203, 0.349088, 0.345391, 0.374851",\ + "0.553172, 0.506477, 0.472362, 0.468665, 0.498125",\ + "0.739732, 0.693038, 0.658922, 0.655226, 0.684685"); + } + + } /* end of arc clk_ast_adc_i_rst_ast_adc_ni_recrr*/ + + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : removal_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.027752, 0.053659, 0.141339, 0.280082, 0.570819",\ + "-0.108741, -0.027330, 0.060350, 0.199093, 0.489830",\ + "-0.183217, -0.101806, -0.014126, 0.124617, 0.415354",\ + "-0.306491, -0.225081, -0.137400, 0.001342, 0.292080",\ + "-0.493052, -0.411641, -0.323961, -0.185218, 0.105519"); + } + + } /* end of arc clk_ast_adc_i_rst_ast_adc_ni_remrr*/ + +} /* end of pin rst_ast_adc_ni */ + +pin("clk_ast_alert_i") { + direction : input ; + clock : true ; + max_transition : 2.480000 ; + capacitance : 0.111907 ; + + /* Other user defined attributes. */ + original_pin : clk_ast_alert_i; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : min_pulse_width ; + fall_constraint( scalar ){ + values ( "0.131491"); + } + + } /* end of arc clk_ast_alert_i_clk_ast_alert_i_pwl*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : min_pulse_width ; + rise_constraint( scalar ){ + values ( "0.073311"); + } + + } /* end of arc clk_ast_alert_i_clk_ast_alert_i_pwh*/ + +} /* end of pin clk_ast_alert_i */ + +pin("rst_ast_alert_ni") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.063611 ; + + /* Other user defined attributes. */ + original_pin : rst_ast_alert_ni; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : recovery_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.113563, 0.076989, 0.018933, 0.022110, 0.146261",\ + "0.193721, 0.155461, 0.100982, 0.103788, 0.220372",\ + "0.282614, 0.243810, 0.191411, 0.194005, 0.308054",\ + "0.566671, 0.464344, 0.331922, 0.334358, 0.433019",\ + "1.363218, 1.178999, 0.828491, 0.816184, 0.684690"); + } + + } /* end of arc clk_ast_alert_i_rst_ast_alert_ni_recrr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : recovery_rising ; + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.092068, 0.057718, -0.003401, -0.002983, 0.002097",\ + "0.189535, 0.154850, 0.093649, 0.094132, 0.100007",\ + "0.301664, 0.264351, 0.202415, 0.202944, 0.209366",\ + "0.503950, 0.455349, 0.390148, 0.390390, 0.393333",\ + "0.857313, 0.785929, 0.714140, 0.713804, 0.709723"); + } + + } /* end of arc clk_ast_alert_i_rst_ast_alert_ni_recfr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : removal_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.123357, 0.181341, 0.319709, 0.347503, 0.685278",\ + "0.102353, 0.159959, 0.295858, 0.323234, 0.655939",\ + "0.092806, 0.153066, 0.290747, 0.317698, 0.645224",\ + "0.064479, 0.123792, 0.266686, 0.294183, 0.628352",\ + "-0.004662, 0.048858, 0.204447, 0.233992, 0.593057"); + } + + } /* end of arc clk_ast_alert_i_rst_ast_alert_ni_remrr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : removal_rising ; + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.074257, 0.131115, 0.268439, 0.296209, 0.633696",\ + "-0.014192, 0.042690, 0.179264, 0.206921, 0.543039",\ + "-0.102387, -0.045223, 0.090380, 0.117827, 0.451393",\ + "-0.249899, -0.191425, -0.054943, -0.027706, 0.303305",\ + "-0.492713, -0.431597, -0.293340, -0.266527, 0.059328"); + } + + } /* end of arc clk_ast_alert_i_rst_ast_alert_ni_remfr*/ + +} /* end of pin rst_ast_alert_ni */ + +pin("clk_ast_es_i") { + direction : input ; + clock : true ; + max_transition : 2.480000 ; + capacitance : 0.142021 ; + + /* Other user defined attributes. */ + original_pin : clk_ast_es_i; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : min_pulse_width ; + fall_constraint( scalar ){ + values ( "0.131491"); + } + + } /* end of arc clk_ast_es_i_clk_ast_es_i_pwl*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : min_pulse_width ; + rise_constraint( scalar ){ + values ( "0.073311"); + } + + } /* end of arc clk_ast_es_i_clk_ast_es_i_pwh*/ + +} /* end of pin clk_ast_es_i */ + +pin("rst_ast_es_ni") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.184622 ; + + /* Other user defined attributes. */ + original_pin : rst_ast_es_ni; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : recovery_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.210479, 0.169372, 0.114546, 0.118621, 0.168150",\ + "0.293165, 0.250654, 0.192180, 0.195438, 0.235030",\ + "0.391384, 0.349291, 0.288209, 0.290833, 0.322724",\ + "0.566327, 0.524466, 0.460601, 0.462751, 0.488884",\ + "0.947368, 0.905673, 0.836972, 0.838520, 0.857344"); + } + + } /* end of arc clk_ast_es_i_rst_ast_es_ni_recrr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : removal_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.051490, -0.010118, 0.054432, 0.065559, 0.200781",\ + "-0.130202, -0.094826, -0.027856, -0.016996, 0.114987",\ + "-0.215839, -0.180431, -0.119977, -0.109196, 0.021823",\ + "-0.347231, -0.311623, -0.255002, -0.244742, -0.120048",\ + "-0.619519, -0.583379, -0.529999, -0.521121, -0.413232"); + } + + } /* end of arc clk_ast_es_i_rst_ast_es_ni_remrr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : recovery_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.330641, 0.279192, 0.245179, 0.243672, 0.279220",\ + "0.409639, 0.358190, 0.324177, 0.322670, 0.358218",\ + "0.487644, 0.436183, 0.402110, 0.400492, 0.435798",\ + "0.623048, 0.571541, 0.537264, 0.535269, 0.569741",\ + "0.842293, 0.790722, 0.756013, 0.753223, 0.785948"); + } + + } /* end of arc clk_ast_ext_i_rst_ast_es_ni_recrr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : removal_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.138360, -0.088735, -0.049180, 0.004893, 0.111904",\ + "-0.218903, -0.169277, -0.129723, -0.075649, 0.031362",\ + "-0.301318, -0.252007, -0.212321, -0.158231, -0.051325",\ + "-0.443423, -0.394857, -0.354861, -0.300729, -0.194073",\ + "-0.673239, -0.626523, -0.585755, -0.531523, -0.425485"); + } + + } /* end of arc clk_ast_ext_i_rst_ast_es_ni_remrr*/ + +} /* end of pin rst_ast_es_ni */ + +pin("clk_ast_rng_i") { + direction : input ; + clock : true ; + max_transition : 2.480000 ; + capacitance : 0.016298 ; + + /* Other user defined attributes. */ + original_pin : clk_ast_rng_i; + timing () { + related_pin : "clk_ast_rng_i" ; + timing_type : min_pulse_width ; + fall_constraint( scalar ){ + values ( "0.131491"); + } + + } /* end of arc clk_ast_rng_i_clk_ast_rng_i_pwl*/ + + timing () { + related_pin : "clk_ast_rng_i" ; + timing_type : min_pulse_width ; + rise_constraint( scalar ){ + values ( "0.073311"); + } + + } /* end of arc clk_ast_rng_i_clk_ast_rng_i_pwh*/ + +} /* end of pin clk_ast_rng_i */ + +pin("rst_ast_rng_ni") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.019282 ; + + /* Other user defined attributes. */ + original_pin : rst_ast_rng_ni; + timing () { + related_pin : "clk_ast_rng_i" ; + timing_type : recovery_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.397809, 0.355150, 0.299205, 0.303092, 0.350337",\ + "0.476858, 0.434199, 0.378254, 0.382142, 0.429386",\ + "0.555484, 0.512828, 0.456739, 0.460590, 0.507394",\ + "0.694132, 0.651484, 0.595040, 0.598802, 0.644521",\ + "0.924501, 0.881869, 0.824615, 0.828174, 0.871421"); + } + + } /* end of arc clk_ast_rng_i_rst_ast_rng_ni_recrr*/ + + timing () { + related_pin : "clk_ast_rng_i" ; + timing_type : removal_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.051490, -0.010118, 0.054432, 0.065559, 0.200781",\ + "-0.130202, -0.094826, -0.027856, -0.016996, 0.114987",\ + "-0.215839, -0.180431, -0.119977, -0.109196, 0.021823",\ + "-0.347231, -0.311623, -0.255002, -0.244742, -0.120048",\ + "-0.619519, -0.580113, -0.514458, -0.503429, -0.369398"); + } + + } /* end of arc clk_ast_rng_i_rst_ast_rng_ni_remrr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : recovery_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.210479, 0.160879, 0.128086, 0.118621, 0.168150",\ + "0.293165, 0.241596, 0.206622, 0.195438, 0.235030",\ + "0.391384, 0.339830, 0.303295, 0.290833, 0.322724",\ + "0.566327, 0.514573, 0.476374, 0.462751, 0.488884",\ + "0.947368, 0.895031, 0.853939, 0.838520, 0.857344"); + } + + } /* end of arc clk_ast_tlul_i_rst_ast_rng_ni_recrr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : removal_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.124168, -0.077180, -0.040446, -0.015137, 0.108101",\ + "-0.205037, -0.158304, -0.123014, -0.098281, 0.025219",\ + "-0.301967, -0.254997, -0.221149, -0.197116, -0.074898",\ + "-0.470369, -0.422280, -0.389838, -0.366778, -0.249319",\ + "-0.834370, -0.783388, -0.753247, -0.732123, -0.626660"); + } + + } /* end of arc clk_ast_tlul_i_rst_ast_rng_ni_remrr*/ + +} /* end of pin rst_ast_rng_ni */ + +pin("clk_ast_tlul_i") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.070969 ; + + /* Other user defined attributes. */ + original_pin : clk_ast_tlul_i; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : min_pulse_width ; + fall_constraint( scalar ){ + values ( "0.149001"); + } + + } /* end of arc clk_ast_tlul_i_clk_ast_tlul_i_pwl*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : min_pulse_width ; + rise_constraint( scalar ){ + values ( "0.073311"); + } + + } /* end of arc clk_ast_tlul_i_clk_ast_tlul_i_pwh*/ + +} /* end of pin clk_ast_tlul_i */ + +pin("rst_ast_tlul_ni") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 2.103311 ; + + /* Other user defined attributes. */ + original_pin : rst_ast_tlul_ni; + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : recovery_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.716936, 0.665384, 0.628579, 0.622004, 0.646451",\ + "0.794990, 0.743439, 0.706634, 0.700058, 0.724506",\ + "0.863378, 0.811826, 0.775021, 0.768446, 0.792893",\ + "0.983598, 0.932046, 0.895241, 0.888666, 0.913113",\ + "1.184568, 1.133018, 1.096165, 1.089503, 1.113762"); + } + + } /* end of arc clk_ast_ext_i_rst_ast_tlul_ni_recrr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : removal_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.208883, -0.162400, -0.121535, -0.067290, 0.038670",\ + "-0.289818, -0.243335, -0.202470, -0.148225, -0.042265",\ + "-0.371428, -0.325048, -0.284140, -0.229890, -0.123964",\ + "-0.514608, -0.468588, -0.427530, -0.373260, -0.267455",\ + "-0.754762, -0.708893, -0.668362, -0.614349, -0.508655"); + } + + } /* end of arc clk_ast_ext_i_rst_ast_tlul_ni_remrr*/ + + timing () { + related_pin : "clk_ast_rng_i" ; + timing_type : recovery_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.210479, 0.169372, 0.114546, 0.118621, 0.168150",\ + "0.293165, 0.250654, 0.192180, 0.195438, 0.235030",\ + "0.391384, 0.349291, 0.288209, 0.290833, 0.322724",\ + "0.566327, 0.524466, 0.460601, 0.462751, 0.488884",\ + "0.947368, 0.905673, 0.836972, 0.838520, 0.857344"); + } + + } /* end of arc clk_ast_rng_i_rst_ast_tlul_ni_recrr*/ + + timing () { + related_pin : "clk_ast_rng_i" ; + timing_type : removal_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.124168, -0.086693, -0.025277, -0.015137, 0.108101",\ + "-0.205037, -0.167443, -0.108443, -0.098281, 0.025219",\ + "-0.301967, -0.263763, -0.207172, -0.197116, -0.074898",\ + "-0.470369, -0.430682, -0.376443, -0.366778, -0.249319",\ + "-0.834370, -0.791194, -0.740802, -0.732123, -0.626660"); + } + + } /* end of arc clk_ast_rng_i_rst_ast_tlul_ni_remrr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : recovery_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "1.869923, 1.822277, 1.788958, 1.777550, 1.806108",\ + "1.951337, 1.903690, 1.870372, 1.858964, 1.887521",\ + "2.032032, 1.984385, 1.951067, 1.939659, 1.968216",\ + "2.170088, 2.122442, 2.089123, 2.077716, 2.106273",\ + "2.387489, 2.339843, 2.306524, 2.295116, 2.323674"); + } + + } /* end of arc clk_ast_tlul_i_rst_ast_tlul_ni_recrr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : removal_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.059314, 0.134642, 0.207217, 0.259023, 0.524416",\ + "-0.004435, 0.071727, 0.144173, 0.196109, 0.463735",\ + "-0.061661, 0.013696, 0.087717, 0.140099, 0.405234",\ + "-0.144853, -0.069971, 0.004287, 0.056772, 0.321975",\ + "-0.313738, -0.239256, -0.166173, -0.113918, 0.154394"); + } + + } /* end of arc clk_ast_tlul_i_rst_ast_tlul_ni_remrr*/ + +} /* end of pin rst_ast_tlul_ni */ + +pin("clk_ast_usb_i") { + direction : input ; + clock : true ; + max_transition : 2.480000 ; + capacitance : 0.008679 ; + + /* Other user defined attributes. */ + original_pin : clk_ast_usb_i; + timing () { + related_pin : "clk_ast_usb_i" ; + timing_type : min_pulse_width ; + fall_constraint( scalar ){ + values ( "0.131491"); + } + + } /* end of arc clk_ast_usb_i_clk_ast_usb_i_pwl*/ + + timing () { + related_pin : "clk_ast_usb_i" ; + timing_type : min_pulse_width ; + rise_constraint( scalar ){ + values ( "0.073311"); + } + + } /* end of arc clk_ast_usb_i_clk_ast_usb_i_pwh*/ + +} /* end of pin clk_ast_usb_i */ + +pin("rst_ast_usb_ni") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.013220 ; + + /* Other user defined attributes. */ + original_pin : rst_ast_usb_ni; + timing () { + related_pin : "clk_ast_usb_i" ; + timing_type : recovery_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.400327, 0.357670, 0.301625, 0.305488, 0.352426",\ + "0.476049, 0.433392, 0.377347, 0.381210, 0.428148",\ + "0.548090, 0.505436, 0.449256, 0.453084, 0.499610",\ + "0.675976, 0.633329, 0.576799, 0.580539, 0.625997",\ + "0.887381, 0.844752, 0.787402, 0.790936, 0.833890"); + } + + } /* end of arc clk_ast_usb_i_rst_ast_usb_ni_recrr*/ + + timing () { + related_pin : "clk_ast_usb_i" ; + timing_type : removal_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.128239, -0.088359, -0.022542, -0.011521, 0.122413",\ + "-0.208722, -0.168842, -0.103025, -0.092004, 0.041930",\ + "-0.287884, -0.248004, -0.182187, -0.171166, -0.037232",\ + "-0.421984, -0.382104, -0.316287, -0.305266, -0.171332",\ + "-0.631259, -0.591379, -0.525562, -0.514541, -0.380607"); + } + + } /* end of arc clk_ast_usb_i_rst_ast_usb_ni_remrr*/ + +} /* end of pin rst_ast_usb_ni */ + +pin("clk_ast_ext_i") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.005952 ; + + /* Other user defined attributes. */ + original_pin : clk_ast_ext_i; + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : min_pulse_width ; + fall_constraint( scalar ){ + values ( "0.300783"); + } + + } /* end of arc clk_ast_ext_i_clk_ast_ext_i_pwl*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : min_pulse_width ; + rise_constraint( scalar ){ + values ( "0.123380"); + } + + } /* end of arc clk_ast_ext_i_clk_ast_ext_i_pwh*/ + +} /* end of pin clk_ast_ext_i */ + +pin("por_ni") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000461 ; + + /* Other user defined attributes. */ + original_pin : por_ni; +} /* end of pin por_ni */ +bus ( sns_clks_i ) { + + bus_type : BUS27_type2 ; + direction : input ; + +pin("sns_clks_i[26]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_clks_i[26]; +} /* end of pin sns_clks_i[26] */ + +pin("sns_clks_i[25]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_clks_i[25]; +} /* end of pin sns_clks_i[25] */ + +pin("sns_clks_i[24]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_clks_i[24]; +} /* end of pin sns_clks_i[24] */ + +pin("sns_clks_i[23]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_clks_i[23]; +} /* end of pin sns_clks_i[23] */ + +pin("sns_clks_i[22]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_clks_i[22]; +} /* end of pin sns_clks_i[22] */ + +pin("sns_clks_i[21]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_clks_i[21]; +} /* end of pin sns_clks_i[21] */ + +pin("sns_clks_i[20]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_clks_i[20]; +} /* end of pin sns_clks_i[20] */ + +pin("sns_clks_i[19]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_clks_i[19]; +} /* end of pin sns_clks_i[19] */ + +pin("sns_clks_i[18]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_clks_i[18]; +} /* end of pin sns_clks_i[18] */ + +pin("sns_clks_i[17]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_clks_i[17]; +} /* end of pin sns_clks_i[17] */ + +pin("sns_clks_i[16]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_clks_i[16]; +} /* end of pin sns_clks_i[16] */ + +pin("sns_clks_i[15]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_clks_i[15]; +} /* end of pin sns_clks_i[15] */ + +pin("sns_clks_i[14]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_clks_i[14]; +} /* end of pin sns_clks_i[14] */ + +pin("sns_clks_i[13]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_clks_i[13]; +} /* end of pin sns_clks_i[13] */ + +pin("sns_clks_i[12]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_clks_i[12]; +} /* end of pin sns_clks_i[12] */ + +pin("sns_clks_i[11]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_clks_i[11]; +} /* end of pin sns_clks_i[11] */ + +pin("sns_clks_i[10]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_clks_i[10]; +} /* end of pin sns_clks_i[10] */ + +pin("sns_clks_i[9]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_clks_i[9]; +} /* end of pin sns_clks_i[9] */ + +pin("sns_clks_i[8]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_clks_i[8]; +} /* end of pin sns_clks_i[8] */ + +pin("sns_clks_i[7]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_clks_i[7]; +} /* end of pin sns_clks_i[7] */ + +pin("sns_clks_i[6]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_clks_i[6]; +} /* end of pin sns_clks_i[6] */ + +pin("sns_clks_i[5]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_clks_i[5]; +} /* end of pin sns_clks_i[5] */ + +pin("sns_clks_i[4]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_clks_i[4]; +} /* end of pin sns_clks_i[4] */ + +pin("sns_clks_i[3]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_clks_i[3]; +} /* end of pin sns_clks_i[3] */ + +pin("sns_clks_i[2]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_clks_i[2]; +} /* end of pin sns_clks_i[2] */ + +pin("sns_clks_i[1]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_clks_i[1]; +} /* end of pin sns_clks_i[1] */ + +pin("sns_clks_i[0]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_clks_i[0]; +} /* end of pin sns_clks_i[0] */ +} /* end of bus sns_clks_i */ +bus ( sns_rsts_i ) { + + bus_type : BUS56_type3 ; + direction : input ; + +pin("sns_rsts_i[55]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[55]; +} /* end of pin sns_rsts_i[55] */ + +pin("sns_rsts_i[54]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[54]; +} /* end of pin sns_rsts_i[54] */ + +pin("sns_rsts_i[53]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[53]; +} /* end of pin sns_rsts_i[53] */ + +pin("sns_rsts_i[52]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[52]; +} /* end of pin sns_rsts_i[52] */ + +pin("sns_rsts_i[51]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[51]; +} /* end of pin sns_rsts_i[51] */ + +pin("sns_rsts_i[50]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[50]; +} /* end of pin sns_rsts_i[50] */ + +pin("sns_rsts_i[49]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[49]; +} /* end of pin sns_rsts_i[49] */ + +pin("sns_rsts_i[48]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[48]; +} /* end of pin sns_rsts_i[48] */ + +pin("sns_rsts_i[47]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[47]; +} /* end of pin sns_rsts_i[47] */ + +pin("sns_rsts_i[46]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[46]; +} /* end of pin sns_rsts_i[46] */ + +pin("sns_rsts_i[45]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[45]; +} /* end of pin sns_rsts_i[45] */ + +pin("sns_rsts_i[44]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[44]; +} /* end of pin sns_rsts_i[44] */ + +pin("sns_rsts_i[43]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[43]; +} /* end of pin sns_rsts_i[43] */ + +pin("sns_rsts_i[42]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[42]; +} /* end of pin sns_rsts_i[42] */ + +pin("sns_rsts_i[41]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[41]; +} /* end of pin sns_rsts_i[41] */ + +pin("sns_rsts_i[40]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[40]; +} /* end of pin sns_rsts_i[40] */ + +pin("sns_rsts_i[39]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[39]; +} /* end of pin sns_rsts_i[39] */ + +pin("sns_rsts_i[38]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[38]; +} /* end of pin sns_rsts_i[38] */ + +pin("sns_rsts_i[37]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[37]; +} /* end of pin sns_rsts_i[37] */ + +pin("sns_rsts_i[36]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[36]; +} /* end of pin sns_rsts_i[36] */ + +pin("sns_rsts_i[35]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[35]; +} /* end of pin sns_rsts_i[35] */ + +pin("sns_rsts_i[34]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[34]; +} /* end of pin sns_rsts_i[34] */ + +pin("sns_rsts_i[33]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[33]; +} /* end of pin sns_rsts_i[33] */ + +pin("sns_rsts_i[32]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[32]; +} /* end of pin sns_rsts_i[32] */ + +pin("sns_rsts_i[31]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[31]; +} /* end of pin sns_rsts_i[31] */ + +pin("sns_rsts_i[30]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[30]; +} /* end of pin sns_rsts_i[30] */ + +pin("sns_rsts_i[29]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[29]; +} /* end of pin sns_rsts_i[29] */ + +pin("sns_rsts_i[28]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[28]; +} /* end of pin sns_rsts_i[28] */ + +pin("sns_rsts_i[27]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[27]; +} /* end of pin sns_rsts_i[27] */ + +pin("sns_rsts_i[26]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[26]; +} /* end of pin sns_rsts_i[26] */ + +pin("sns_rsts_i[25]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[25]; +} /* end of pin sns_rsts_i[25] */ + +pin("sns_rsts_i[24]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[24]; +} /* end of pin sns_rsts_i[24] */ + +pin("sns_rsts_i[23]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[23]; +} /* end of pin sns_rsts_i[23] */ + +pin("sns_rsts_i[22]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[22]; +} /* end of pin sns_rsts_i[22] */ + +pin("sns_rsts_i[21]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[21]; +} /* end of pin sns_rsts_i[21] */ + +pin("sns_rsts_i[20]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[20]; +} /* end of pin sns_rsts_i[20] */ + +pin("sns_rsts_i[19]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[19]; +} /* end of pin sns_rsts_i[19] */ + +pin("sns_rsts_i[18]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[18]; +} /* end of pin sns_rsts_i[18] */ + +pin("sns_rsts_i[17]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[17]; +} /* end of pin sns_rsts_i[17] */ + +pin("sns_rsts_i[16]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[16]; +} /* end of pin sns_rsts_i[16] */ + +pin("sns_rsts_i[15]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[15]; +} /* end of pin sns_rsts_i[15] */ + +pin("sns_rsts_i[14]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[14]; +} /* end of pin sns_rsts_i[14] */ + +pin("sns_rsts_i[13]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[13]; +} /* end of pin sns_rsts_i[13] */ + +pin("sns_rsts_i[12]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[12]; +} /* end of pin sns_rsts_i[12] */ + +pin("sns_rsts_i[11]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[11]; +} /* end of pin sns_rsts_i[11] */ + +pin("sns_rsts_i[10]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[10]; +} /* end of pin sns_rsts_i[10] */ + +pin("sns_rsts_i[9]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[9]; +} /* end of pin sns_rsts_i[9] */ + +pin("sns_rsts_i[8]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[8]; +} /* end of pin sns_rsts_i[8] */ + +pin("sns_rsts_i[7]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[7]; +} /* end of pin sns_rsts_i[7] */ + +pin("sns_rsts_i[6]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[6]; +} /* end of pin sns_rsts_i[6] */ + +pin("sns_rsts_i[5]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[5]; +} /* end of pin sns_rsts_i[5] */ + +pin("sns_rsts_i[4]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[4]; +} /* end of pin sns_rsts_i[4] */ + +pin("sns_rsts_i[3]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[3]; +} /* end of pin sns_rsts_i[3] */ + +pin("sns_rsts_i[2]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[2]; +} /* end of pin sns_rsts_i[2] */ + +pin("sns_rsts_i[1]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[1]; +} /* end of pin sns_rsts_i[1] */ + +pin("sns_rsts_i[0]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[0]; +} /* end of pin sns_rsts_i[0] */ +} /* end of bus sns_rsts_i */ + +pin("sns_spi_ext_clk_i") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_spi_ext_clk_i; +} /* end of pin sns_spi_ext_clk_i */ + +pin("vcc_supp_i") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : vcc_supp_i; +} /* end of pin vcc_supp_i */ + +pin("vcaon_supp_i") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : vcaon_supp_i; +} /* end of pin vcaon_supp_i */ + +pin("vcmain_supp_i") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : vcmain_supp_i; +} /* end of pin vcmain_supp_i */ + +pin("vioa_supp_i") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : vioa_supp_i; +} /* end of pin vioa_supp_i */ + +pin("viob_supp_i") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : viob_supp_i; +} /* end of pin viob_supp_i */ +bus ( ast_pwst_o ) { + + bus_type : BUS5_type4 ; + direction : output ; + +pin("ast_pwst_o[4]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.652273 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000495 ; + + /* Other user defined attributes. */ + original_pin : ast_pwst_o[4]; +} /* end of pin ast_pwst_o[4] */ + +pin("ast_pwst_o[3]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.634048 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.007560 ; + + /* Other user defined attributes. */ + original_pin : ast_pwst_o[3]; +} /* end of pin ast_pwst_o[3] */ + +pin("ast_pwst_o[2]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.029213 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000584 ; + + /* Other user defined attributes. */ + original_pin : ast_pwst_o[2]; + timing () { + related_pin : "ast_pwst_o[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.018088, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.120368, 0.186170, 0.300859, 0.616258, 1.455810",\ + "0.125647, 0.191441, 0.306120, 0.621529, 1.461089",\ + "0.207819, 0.273839, 0.388973, 0.704719, 1.544218",\ + "0.296772, 0.362735, 0.477872, 0.794339, 1.635091",\ + "0.704776, 0.781389, 0.901027, 1.217412, 2.063059"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.018088, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.118650, 0.232640, 0.431328, 0.981607, 2.441227",\ + "0.118668, 0.232640, 0.431330, 0.981682, 2.441227",\ + "0.118668, 0.233537, 0.432463, 0.981682, 2.441227",\ + "0.120002, 0.233537, 0.433774, 0.981682, 2.441227",\ + "0.161250, 0.255527, 0.435044, 0.981682, 2.441227"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.021349, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.061996, 0.075776, 0.099734, 0.165532, 0.340715",\ + "0.068682, 0.082462, 0.106420, 0.172219, 0.347402",\ + "0.154377, 0.169144, 0.193145, 0.258865, 0.434247",\ + "0.245754, 0.264276, 0.291081, 0.357185, 0.532518",\ + "0.645975, 0.686648, 0.737659, 0.832084, 1.014107"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.021349, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.026953, 0.051423, 0.094862, 0.215093, 0.534102",\ + "0.026955, 0.051424, 0.094862, 0.215093, 0.534102",\ + "0.033450, 0.053875, 0.094993, 0.215093, 0.534241",\ + "0.046741, 0.065795, 0.101823, 0.215093, 0.534701",\ + "0.120319, 0.148529, 0.186126, 0.267902, 0.543427"); + } + + } /* end of arc ast_pwst_o[4]_ast_pwst_o[2]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "ast_pwst_o[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.017926, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.120368, 0.186170, 0.300859, 0.616258, 1.455810",\ + "0.125568, 0.191362, 0.306040, 0.621450, 1.461010",\ + "0.207819, 0.273839, 0.388973, 0.704719, 1.544218",\ + "0.296772, 0.362735, 0.477872, 0.794339, 1.635091",\ + "0.704776, 0.781389, 0.901027, 1.217412, 2.063059"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.017926, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.118650, 0.232611, 0.431328, 0.977612, 2.431972",\ + "0.118650, 0.232611, 0.431330, 0.977612, 2.431972",\ + "0.118650, 0.233259, 0.432463, 0.977612, 2.431972",\ + "0.120002, 0.233259, 0.433774, 0.977612, 2.431972",\ + "0.161250, 0.255527, 0.435044, 0.981481, 2.431972"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.020771, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.061996, 0.075776, 0.099734, 0.165532, 0.340715",\ + "0.068410, 0.082189, 0.106148, 0.171946, 0.347129",\ + "0.154377, 0.169144, 0.193145, 0.258865, 0.434247",\ + "0.245754, 0.264276, 0.291081, 0.357185, 0.532518",\ + "0.645975, 0.686648, 0.737659, 0.832084, 1.014107"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.020771, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.026953, 0.051423, 0.094862, 0.214557, 0.534102",\ + "0.026954, 0.051424, 0.094862, 0.214557, 0.534102",\ + "0.033450, 0.053875, 0.094993, 0.214557, 0.534241",\ + "0.046741, 0.065795, 0.101823, 0.215088, 0.534701",\ + "0.120319, 0.148529, 0.186126, 0.267902, 0.543427"); + } + + } /* end of arc ast_pwst_o[4]_ast_pwst_o[2]_una_min*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : recovery_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.120145, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.404676, 0.353105, 0.318351, 0.315478, 0.348023",\ + "0.454532, 0.402961, 0.368207, 0.365334, 0.397879",\ + "0.484555, 0.432984, 0.398230, 0.395357, 0.427902",\ + "0.566329, 0.514758, 0.480004, 0.477131, 0.509676",\ + "0.956464, 0.904894, 0.869963, 0.866772, 0.898621"); + } + + } /* end of arc clk_ast_ext_i_ast_pwst_o[2]_recrr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : removal_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.118140, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.316729, -0.270030, -0.234537, -0.184982, -0.086025",\ + "-0.365783, -0.319083, -0.283591, -0.234035, -0.135079",\ + "-0.396608, -0.349909, -0.314416, -0.264861, -0.165904",\ + "-0.478382, -0.431683, -0.396190, -0.346635, -0.247678",\ + "-0.868371, -0.821645, -0.786315, -0.736867, -0.638027"); + } + + } /* end of arc clk_ast_ext_i_ast_pwst_o[2]_remrr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "380000.531250, 380000.593750, 380000.718750, 380001.031250, 380001.875000",\ + "380000.625000, 380000.687500, 380000.812500, 380001.125000, 380001.968750",\ + "380000.687500, 380000.750000, 380000.875000, 380001.187500, 380002.031250",\ + "380000.750000, 380000.812500, 380000.937500, 380001.250000, 380002.093750",\ + "380001.062500, 380001.125000, 380001.250000, 380001.562500, 380002.406250"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.120145, 0.234100, 0.432069, 0.982878, 2.445448",\ + "0.120145, 0.234100, 0.432069, 0.982878, 2.445448",\ + "0.120145, 0.234100, 0.432069, 0.982878, 2.445448",\ + "0.120145, 0.234100, 0.432069, 0.982878, 2.445448",\ + "0.120145, 0.234100, 0.432069, 0.982878, 2.445448"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "380001.875000, 380001.875000, 380001.906250, 380001.968750, 380002.156250",\ + "380001.968750, 380001.968750, 380002.000000, 380002.062500, 380002.250000",\ + "380002.062500, 380002.062500, 380002.093750, 380002.156250, 380002.343750",\ + "380002.125000, 380002.125000, 380002.156250, 380002.218750, 380002.406250",\ + "380002.468750, 380002.468750, 380002.500000, 380002.562500, 380002.750000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.031251, 0.056161, 0.101276, 0.226771, 0.561875",\ + "0.031251, 0.056161, 0.101276, 0.226771, 0.561875",\ + "0.031251, 0.056161, 0.101276, 0.226771, 0.561875",\ + "0.031251, 0.056161, 0.101276, 0.226771, 0.561875",\ + "0.031251, 0.056161, 0.101276, 0.226771, 0.561875"); + } + + } /* end of arc clk_ast_tlul_i_ast_pwst_o[2]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.396377, 0.462195, 0.577090, 0.892530, 1.731965",\ + "0.483687, 0.549505, 0.664400, 0.979841, 1.819276",\ + "0.581466, 0.647284, 0.762179, 1.077619, 1.917054",\ + "0.654025, 0.719843, 0.834738, 1.150178, 1.989613",\ + "1.042482, 1.108301, 1.223195, 1.538636, 2.378071"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.118140, 0.231881, 0.431660, 0.979741, 2.437812",\ + "0.118140, 0.231881, 0.431660, 0.979741, 2.437812",\ + "0.118140, 0.231881, 0.431660, 0.979741, 2.437812",\ + "0.118140, 0.231881, 0.431660, 0.979741, 2.437812",\ + "0.118140, 0.231881, 0.431660, 0.979741, 2.437812"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.326727, 0.341464, 0.366815, 0.435950, 0.619738",\ + "0.414576, 0.429313, 0.454664, 0.523799, 0.707587",\ + "0.495656, 0.510394, 0.535744, 0.604879, 0.788667",\ + "0.553927, 0.568665, 0.594015, 0.663150, 0.846938",\ + "0.864022, 0.878760, 0.904110, 0.973245, 1.157033"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.026020, 0.051544, 0.096671, 0.220662, 0.551206",\ + "0.026020, 0.051544, 0.096671, 0.220662, 0.551206",\ + "0.026020, 0.051544, 0.096671, 0.220662, 0.551206",\ + "0.026020, 0.051544, 0.096671, 0.220662, 0.551206",\ + "0.026020, 0.051544, 0.096671, 0.220662, 0.551206"); + } + + } /* end of arc clk_ast_tlul_i_ast_pwst_o[2]_redg_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "380000.406250, 380000.468750, 380000.593750, 380000.906250, 380001.750000",\ + "380000.500000, 380000.562500, 380000.687500, 380001.000000, 380001.843750",\ + "380000.593750, 380000.656250, 380000.781250, 380001.093750, 380001.937500",\ + "380000.750000, 380000.812500, 380000.937500, 380001.250000, 380002.093750",\ + "380001.000000, 380001.062500, 380001.187500, 380001.500000, 380002.343750"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.120145, 0.234100, 0.432069, 0.982878, 2.445448",\ + "0.120145, 0.234100, 0.432069, 0.982878, 2.445448",\ + "0.120145, 0.234100, 0.432069, 0.982878, 2.445448",\ + "0.120145, 0.234100, 0.432069, 0.982878, 2.445448",\ + "0.120145, 0.234100, 0.432069, 0.982878, 2.445448"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "380001.781250, 380001.781250, 380001.812500, 380001.875000, 380002.062500",\ + "380001.875000, 380001.875000, 380001.906250, 380001.968750, 380002.156250",\ + "380002.000000, 380002.000000, 380002.031250, 380002.093750, 380002.281250",\ + "380002.187500, 380002.187500, 380002.218750, 380002.281250, 380002.468750",\ + "380002.500000, 380002.500000, 380002.531250, 380002.593750, 380002.781250"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.031236, 0.056156, 0.101275, 0.226769, 0.561877",\ + "0.031236, 0.056156, 0.101275, 0.226769, 0.561877",\ + "0.031236, 0.056156, 0.101275, 0.226769, 0.561877",\ + "0.031236, 0.056156, 0.101275, 0.226769, 0.561877",\ + "0.031236, 0.056156, 0.101275, 0.226769, 0.561877"); + } + + } /* end of arc padmux2ast_i[4]_ast_pwst_o[2]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "379999.937500, 380000.000000, 380000.093750, 380000.406250, 380001.250000",\ + "380000.031250, 380000.093750, 380000.187500, 380000.500000, 380001.343750",\ + "380000.093750, 380000.156250, 380000.250000, 380000.562500, 380001.406250",\ + "380000.250000, 380000.312500, 380000.406250, 380000.718750, 380001.562500",\ + "380000.468750, 380000.531250, 380000.625000, 380000.937500, 380001.781250"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.118145, 0.231881, 0.431660, 0.979741, 2.437852",\ + "0.118145, 0.231881, 0.431660, 0.979741, 2.437852",\ + "0.118145, 0.231881, 0.431660, 0.979741, 2.437852",\ + "0.118145, 0.231881, 0.431660, 0.979741, 2.437852",\ + "0.118145, 0.231881, 0.431660, 0.979741, 2.437852"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "380001.375000, 380001.406250, 380001.437500, 380001.500000, 380001.687500",\ + "380001.468750, 380001.500000, 380001.531250, 380001.593750, 380001.781250",\ + "380001.562500, 380001.593750, 380001.625000, 380001.687500, 380001.875000",\ + "380001.750000, 380001.781250, 380001.812500, 380001.875000, 380002.062500",\ + "380002.000000, 380002.031250, 380002.062500, 380002.125000, 380002.312500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.026020, 0.051544, 0.096671, 0.220662, 0.551206",\ + "0.026020, 0.051544, 0.096671, 0.220662, 0.551206",\ + "0.026020, 0.051544, 0.096671, 0.220662, 0.551206",\ + "0.026020, 0.051544, 0.096671, 0.220662, 0.551206",\ + "0.026020, 0.051544, 0.096671, 0.220662, 0.551206"); + } + + } /* end of arc padmux2ast_i[4]_ast_pwst_o[2]_una_min*/ + +} /* end of pin ast_pwst_o[2] */ + +pin("ast_pwst_o[1]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.101136 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : ast_pwst_o[1]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "970008.437500, 970008.625000, 970008.750000, 970009.000000, 970009.875000",\ + "970008.562500, 970008.750000, 970008.875000, 970009.125000, 970010.000000",\ + "970008.687500, 970008.875000, 970009.000000, 970009.250000, 970010.125000",\ + "970008.687500, 970008.875000, 970009.000000, 970009.250000, 970010.125000",\ + "970009.062500, 970009.250000, 970009.375000, 970009.625000, 970010.500000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "970005.937500, 970006.062500, 970006.187500, 970006.375000, 970007.000000",\ + "970006.062500, 970006.187500, 970006.312500, 970006.500000, 970007.125000",\ + "970006.062500, 970006.187500, 970006.312500, 970006.500000, 970007.125000",\ + "970006.187500, 970006.312500, 970006.437500, 970006.625000, 970007.250000",\ + "970006.437500, 970006.562500, 970006.687500, 970006.875000, 970007.500000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101"); + } + + } /* end of arc clk_ast_tlul_i_ast_pwst_o[1]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "7.046945, 7.238483, 7.357924, 7.616586, 8.489688",\ + "7.134256, 7.325794, 7.445234, 7.703897, 8.576999",\ + "7.232034, 7.423573, 7.543013, 7.801675, 8.674777",\ + "7.304593, 7.496131, 7.615571, 7.874234, 8.747335",\ + "7.693051, 7.884589, 8.004029, 8.262691, 9.135794"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "5.236063, 5.393305, 5.518865, 5.706539, 6.296398",\ + "5.323912, 5.481154, 5.606714, 5.794387, 6.384247",\ + "5.404993, 5.562235, 5.687795, 5.875468, 6.465328",\ + "5.463264, 5.620506, 5.746066, 5.933739, 6.523599",\ + "5.773359, 5.930601, 6.056160, 6.243834, 6.833694"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.242588, 0.288084, 0.303651, 0.497673, 1.551133",\ + "0.242588, 0.288084, 0.303651, 0.497673, 1.551133",\ + "0.242588, 0.288084, 0.303651, 0.497673, 1.551133",\ + "0.242588, 0.288084, 0.303651, 0.497673, 1.551133",\ + "0.242588, 0.288084, 0.303651, 0.497673, 1.551133"); + } + + } /* end of arc clk_ast_tlul_i_ast_pwst_o[1]_redg_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "380006.593750, 380006.781250, 380006.906250, 380007.156250, 380008.031250",\ + "380006.687500, 380006.875000, 380007.000000, 380007.250000, 380008.125000",\ + "380006.781250, 380006.968750, 380007.093750, 380007.343750, 380008.218750",\ + "380006.937500, 380007.125000, 380007.250000, 380007.500000, 380008.375000",\ + "380007.187500, 380007.375000, 380007.500000, 380007.750000, 380008.625000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "380006.281250, 380006.437500, 380006.562500, 380006.750000, 380007.343750",\ + "380006.375000, 380006.531250, 380006.656250, 380006.843750, 380007.437500",\ + "380006.500000, 380006.656250, 380006.781250, 380006.968750, 380007.562500",\ + "380006.687500, 380006.843750, 380006.968750, 380007.156250, 380007.750000",\ + "380007.000000, 380007.156250, 380007.281250, 380007.468750, 380008.062500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101"); + } + + } /* end of arc padmux2ast_i[4]_ast_pwst_o[1]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "380006.593750, 380006.781250, 380006.906250, 380007.156250, 380008.031250",\ + "380006.687500, 380006.875000, 380007.000000, 380007.250000, 380008.125000",\ + "380006.750000, 380006.937500, 380007.062500, 380007.312500, 380008.187500",\ + "380006.906250, 380007.093750, 380007.218750, 380007.468750, 380008.343750",\ + "380007.125000, 380007.312500, 380007.437500, 380007.687500, 380008.562500"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "380006.281250, 380006.437500, 380006.562500, 380006.750000, 380007.343750",\ + "380006.375000, 380006.531250, 380006.656250, 380006.843750, 380007.437500",\ + "380006.468750, 380006.625000, 380006.750000, 380006.937500, 380007.531250",\ + "380006.656250, 380006.812500, 380006.937500, 380007.125000, 380007.718750",\ + "380006.906250, 380007.062500, 380007.187500, 380007.375000, 380007.968750"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\ + "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\ + "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\ + "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\ + "0.242595, 0.288092, 0.303657, 0.497674, 1.551132"); + } + + } /* end of arc padmux2ast_i[4]_ast_pwst_o[1]_una_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "970005.812500, 970005.937500, 970006.062500, 970006.250000, 970006.875000",\ + "970005.937500, 970006.062500, 970006.187500, 970006.375000, 970007.000000",\ + "970005.937500, 970006.062500, 970006.187500, 970006.375000, 970007.000000",\ + "970006.187500, 970006.312500, 970006.437500, 970006.625000, 970007.250000",\ + "970006.437500, 970006.562500, 970006.687500, 970006.875000, 970007.500000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "970008.312500, 970008.500000, 970008.625000, 970008.875000, 970009.750000",\ + "970008.437500, 970008.625000, 970008.750000, 970009.000000, 970009.875000",\ + "970008.562500, 970008.750000, 970008.875000, 970009.125000, 970010.000000",\ + "970008.812500, 970009.000000, 970009.125000, 970009.375000, 970010.250000",\ + "970009.062500, 970009.250000, 970009.375000, 970009.625000, 970010.500000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832"); + } + + } /* end of arc padmux2ast_i[4]_ast_pwst_o[1]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "970005.812500, 970005.937500, 970006.062500, 970006.250000, 970006.875000",\ + "970005.937500, 970006.062500, 970006.187500, 970006.375000, 970007.000000",\ + "970005.937500, 970006.062500, 970006.187500, 970006.375000, 970007.000000",\ + "970006.062500, 970006.187500, 970006.312500, 970006.500000, 970007.125000",\ + "970006.312500, 970006.437500, 970006.562500, 970006.750000, 970007.375000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\ + "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\ + "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\ + "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\ + "0.242595, 0.288092, 0.303657, 0.497674, 1.551132"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "970008.312500, 970008.500000, 970008.625000, 970008.875000, 970009.750000",\ + "970008.437500, 970008.625000, 970008.750000, 970009.000000, 970009.875000",\ + "970008.562500, 970008.750000, 970008.875000, 970009.125000, 970010.000000",\ + "970008.687500, 970008.875000, 970009.000000, 970009.250000, 970010.125000",\ + "970008.937500, 970009.125000, 970009.250000, 970009.500000, 970010.375000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127"); + } + + } /* end of arc padmux2ast_i[4]_ast_pwst_o[1]_inv_min*/ + + timing () { + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "590006.687500, 590006.875000, 590007.000000, 590007.250000, 590008.125000",\ + "590006.812500, 590007.000000, 590007.125000, 590007.375000, 590008.250000",\ + "590006.812500, 590007.000000, 590007.125000, 590007.375000, 590008.250000",\ + "590006.937500, 590007.125000, 590007.250000, 590007.500000, 590008.375000",\ + "590007.187500, 590007.375000, 590007.500000, 590007.750000, 590008.625000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.256090, 0.317188, 0.317188, 0.797460, 2.395127",\ + "0.256090, 0.317188, 0.317188, 0.797460, 2.395127",\ + "0.256090, 0.317188, 0.317188, 0.797460, 2.395127",\ + "0.256090, 0.317188, 0.317188, 0.797460, 2.395127",\ + "0.256090, 0.317188, 0.317188, 0.797460, 2.395127"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "590005.562500, 590005.687500, 590005.812500, 590006.000000, 590006.625000",\ + "590005.687500, 590005.812500, 590005.937500, 590006.125000, 590006.750000",\ + "590005.812500, 590005.937500, 590006.062500, 590006.250000, 590006.875000",\ + "590005.937500, 590006.062500, 590006.187500, 590006.375000, 590007.000000",\ + "590006.312500, 590006.437500, 590006.562500, 590006.750000, 590007.375000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101"); + } + + } /* end of arc padmux2ast_i[5]_ast_pwst_o[1]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "590006.687500, 590006.875000, 590007.000000, 590007.250000, 590008.125000",\ + "590006.687500, 590006.875000, 590007.000000, 590007.250000, 590008.125000",\ + "590006.812500, 590007.000000, 590007.125000, 590007.375000, 590008.250000",\ + "590006.937500, 590007.125000, 590007.250000, 590007.500000, 590008.375000",\ + "590007.187500, 590007.375000, 590007.500000, 590007.750000, 590008.625000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "590005.562500, 590005.687500, 590005.812500, 590006.000000, 590006.625000",\ + "590005.687500, 590005.812500, 590005.937500, 590006.125000, 590006.750000",\ + "590005.812500, 590005.937500, 590006.062500, 590006.250000, 590006.875000",\ + "590005.937500, 590006.062500, 590006.187500, 590006.375000, 590007.000000",\ + "590006.187500, 590006.312500, 590006.437500, 590006.625000, 590007.250000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101"); + } + + } /* end of arc padmux2ast_i[5]_ast_pwst_o[1]_una_min*/ + +} /* end of pin ast_pwst_o[1] */ + +pin("ast_pwst_o[0]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.101136 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : ast_pwst_o[0]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "970008.437500, 970008.625000, 970008.750000, 970009.000000, 970009.875000",\ + "970008.562500, 970008.750000, 970008.875000, 970009.125000, 970010.000000",\ + "970008.687500, 970008.875000, 970009.000000, 970009.250000, 970010.125000",\ + "970008.687500, 970008.875000, 970009.000000, 970009.250000, 970010.125000",\ + "970009.062500, 970009.250000, 970009.375000, 970009.625000, 970010.500000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "970005.937500, 970006.062500, 970006.187500, 970006.375000, 970007.000000",\ + "970006.062500, 970006.187500, 970006.312500, 970006.500000, 970007.125000",\ + "970006.062500, 970006.187500, 970006.312500, 970006.500000, 970007.125000",\ + "970006.187500, 970006.312500, 970006.437500, 970006.625000, 970007.250000",\ + "970006.437500, 970006.562500, 970006.687500, 970006.875000, 970007.500000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101"); + } + + } /* end of arc clk_ast_tlul_i_ast_pwst_o[0]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "7.046945, 7.238483, 7.357924, 7.616586, 8.489688",\ + "7.134256, 7.325794, 7.445234, 7.703897, 8.576999",\ + "7.232034, 7.423573, 7.543013, 7.801675, 8.674777",\ + "7.304593, 7.496131, 7.615571, 7.874234, 8.747335",\ + "7.693051, 7.884589, 8.004029, 8.262691, 9.135794"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "5.236063, 5.393305, 5.518865, 5.706539, 6.296398",\ + "5.323912, 5.481154, 5.606714, 5.794387, 6.384247",\ + "5.404993, 5.562235, 5.687795, 5.875468, 6.465328",\ + "5.463264, 5.620506, 5.746066, 5.933739, 6.523599",\ + "5.773359, 5.930601, 6.056160, 6.243834, 6.833694"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.242588, 0.288084, 0.303651, 0.497673, 1.551133",\ + "0.242588, 0.288084, 0.303651, 0.497673, 1.551133",\ + "0.242588, 0.288084, 0.303651, 0.497673, 1.551133",\ + "0.242588, 0.288084, 0.303651, 0.497673, 1.551133",\ + "0.242588, 0.288084, 0.303651, 0.497673, 1.551133"); + } + + } /* end of arc clk_ast_tlul_i_ast_pwst_o[0]_redg_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "380006.593750, 380006.781250, 380006.906250, 380007.156250, 380008.031250",\ + "380006.687500, 380006.875000, 380007.000000, 380007.250000, 380008.125000",\ + "380006.781250, 380006.968750, 380007.093750, 380007.343750, 380008.218750",\ + "380006.937500, 380007.125000, 380007.250000, 380007.500000, 380008.375000",\ + "380007.187500, 380007.375000, 380007.500000, 380007.750000, 380008.625000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "380006.281250, 380006.437500, 380006.562500, 380006.750000, 380007.343750",\ + "380006.375000, 380006.531250, 380006.656250, 380006.843750, 380007.437500",\ + "380006.500000, 380006.656250, 380006.781250, 380006.968750, 380007.562500",\ + "380006.687500, 380006.843750, 380006.968750, 380007.156250, 380007.750000",\ + "380007.000000, 380007.156250, 380007.281250, 380007.468750, 380008.062500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101"); + } + + } /* end of arc padmux2ast_i[4]_ast_pwst_o[0]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "380006.593750, 380006.781250, 380006.906250, 380007.156250, 380008.031250",\ + "380006.687500, 380006.875000, 380007.000000, 380007.250000, 380008.125000",\ + "380006.750000, 380006.937500, 380007.062500, 380007.312500, 380008.187500",\ + "380006.906250, 380007.093750, 380007.218750, 380007.468750, 380008.343750",\ + "380007.125000, 380007.312500, 380007.437500, 380007.687500, 380008.562500"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "380006.281250, 380006.437500, 380006.562500, 380006.750000, 380007.343750",\ + "380006.375000, 380006.531250, 380006.656250, 380006.843750, 380007.437500",\ + "380006.468750, 380006.625000, 380006.750000, 380006.937500, 380007.531250",\ + "380006.656250, 380006.812500, 380006.937500, 380007.125000, 380007.718750",\ + "380006.906250, 380007.062500, 380007.187500, 380007.375000, 380007.968750"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\ + "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\ + "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\ + "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\ + "0.242595, 0.288092, 0.303657, 0.497674, 1.551132"); + } + + } /* end of arc padmux2ast_i[4]_ast_pwst_o[0]_una_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "970005.812500, 970005.937500, 970006.062500, 970006.250000, 970006.875000",\ + "970005.937500, 970006.062500, 970006.187500, 970006.375000, 970007.000000",\ + "970005.937500, 970006.062500, 970006.187500, 970006.375000, 970007.000000",\ + "970006.187500, 970006.312500, 970006.437500, 970006.625000, 970007.250000",\ + "970006.437500, 970006.562500, 970006.687500, 970006.875000, 970007.500000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "970008.312500, 970008.500000, 970008.625000, 970008.875000, 970009.750000",\ + "970008.437500, 970008.625000, 970008.750000, 970009.000000, 970009.875000",\ + "970008.562500, 970008.750000, 970008.875000, 970009.125000, 970010.000000",\ + "970008.812500, 970009.000000, 970009.125000, 970009.375000, 970010.250000",\ + "970009.062500, 970009.250000, 970009.375000, 970009.625000, 970010.500000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832"); + } + + } /* end of arc padmux2ast_i[4]_ast_pwst_o[0]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "970005.812500, 970005.937500, 970006.062500, 970006.250000, 970006.875000",\ + "970005.937500, 970006.062500, 970006.187500, 970006.375000, 970007.000000",\ + "970005.937500, 970006.062500, 970006.187500, 970006.375000, 970007.000000",\ + "970006.062500, 970006.187500, 970006.312500, 970006.500000, 970007.125000",\ + "970006.312500, 970006.437500, 970006.562500, 970006.750000, 970007.375000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\ + "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\ + "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\ + "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\ + "0.242595, 0.288092, 0.303657, 0.497674, 1.551132"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "970008.312500, 970008.500000, 970008.625000, 970008.875000, 970009.750000",\ + "970008.437500, 970008.625000, 970008.750000, 970009.000000, 970009.875000",\ + "970008.562500, 970008.750000, 970008.875000, 970009.125000, 970010.000000",\ + "970008.687500, 970008.875000, 970009.000000, 970009.250000, 970010.125000",\ + "970008.937500, 970009.125000, 970009.250000, 970009.500000, 970010.375000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127"); + } + + } /* end of arc padmux2ast_i[4]_ast_pwst_o[0]_inv_min*/ + + timing () { + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "590006.687500, 590006.875000, 590007.000000, 590007.250000, 590008.125000",\ + "590006.812500, 590007.000000, 590007.125000, 590007.375000, 590008.250000",\ + "590006.812500, 590007.000000, 590007.125000, 590007.375000, 590008.250000",\ + "590006.937500, 590007.125000, 590007.250000, 590007.500000, 590008.375000",\ + "590007.187500, 590007.375000, 590007.500000, 590007.750000, 590008.625000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.256090, 0.317188, 0.317188, 0.797460, 2.395127",\ + "0.256090, 0.317188, 0.317188, 0.797460, 2.395127",\ + "0.256090, 0.317188, 0.317188, 0.797460, 2.395127",\ + "0.256090, 0.317188, 0.317188, 0.797460, 2.395127",\ + "0.256090, 0.317188, 0.317188, 0.797460, 2.395127"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "590005.562500, 590005.687500, 590005.812500, 590006.000000, 590006.625000",\ + "590005.687500, 590005.812500, 590005.937500, 590006.125000, 590006.750000",\ + "590005.812500, 590005.937500, 590006.062500, 590006.250000, 590006.875000",\ + "590005.937500, 590006.062500, 590006.187500, 590006.375000, 590007.000000",\ + "590006.312500, 590006.437500, 590006.562500, 590006.750000, 590007.375000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101"); + } + + } /* end of arc padmux2ast_i[5]_ast_pwst_o[0]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "590006.687500, 590006.875000, 590007.000000, 590007.250000, 590008.125000",\ + "590006.687500, 590006.875000, 590007.000000, 590007.250000, 590008.125000",\ + "590006.812500, 590007.000000, 590007.125000, 590007.375000, 590008.250000",\ + "590006.937500, 590007.125000, 590007.250000, 590007.500000, 590008.375000",\ + "590007.187500, 590007.375000, 590007.500000, 590007.750000, 590008.625000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "590005.562500, 590005.687500, 590005.812500, 590006.000000, 590006.625000",\ + "590005.687500, 590005.812500, 590005.937500, 590006.125000, 590006.750000",\ + "590005.812500, 590005.937500, 590006.062500, 590006.250000, 590006.875000",\ + "590005.937500, 590006.062500, 590006.187500, 590006.375000, 590007.000000",\ + "590006.187500, 590006.312500, 590006.437500, 590006.625000, 590007.250000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101"); + } + + } /* end of arc padmux2ast_i[5]_ast_pwst_o[0]_una_min*/ + +} /* end of pin ast_pwst_o[0] */ +} /* end of bus ast_pwst_o */ +bus ( ast_pwst_h_o ) { + + bus_type : BUS5_type4 ; + direction : output ; + +pin("ast_pwst_h_o[4]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.158177 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.003358 ; + + /* Other user defined attributes. */ + original_pin : ast_pwst_h_o[4]; +} /* end of pin ast_pwst_h_o[4] */ + +pin("ast_pwst_h_o[3]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.634048 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.007560 ; + + /* Other user defined attributes. */ + original_pin : ast_pwst_h_o[3]; +} /* end of pin ast_pwst_h_o[3] */ + +pin("ast_pwst_h_o[2]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.029213 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000584 ; + + /* Other user defined attributes. */ + original_pin : ast_pwst_h_o[2]; + timing () { + related_pin : "ast_pwst_o[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.018088, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.120368, 0.186170, 0.300859, 0.616258, 1.455810",\ + "0.125647, 0.191441, 0.306120, 0.621529, 1.461089",\ + "0.207819, 0.273839, 0.388973, 0.704719, 1.544218",\ + "0.296772, 0.362735, 0.477872, 0.794339, 1.635091",\ + "0.704776, 0.781389, 0.901027, 1.217412, 2.063059"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.018088, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.118650, 0.232640, 0.431328, 0.981607, 2.441227",\ + "0.118668, 0.232640, 0.431330, 0.981682, 2.441227",\ + "0.118668, 0.233537, 0.432463, 0.981682, 2.441227",\ + "0.120002, 0.233537, 0.433774, 0.981682, 2.441227",\ + "0.161250, 0.255527, 0.435044, 0.981682, 2.441227"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.021349, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.061996, 0.075776, 0.099734, 0.165532, 0.340715",\ + "0.068682, 0.082462, 0.106420, 0.172219, 0.347402",\ + "0.154377, 0.169144, 0.193145, 0.258865, 0.434247",\ + "0.245754, 0.264276, 0.291081, 0.357185, 0.532518",\ + "0.645975, 0.686648, 0.737659, 0.832084, 1.014107"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.021349, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.026953, 0.051423, 0.094862, 0.215093, 0.534102",\ + "0.026955, 0.051424, 0.094862, 0.215093, 0.534102",\ + "0.033450, 0.053875, 0.094993, 0.215093, 0.534241",\ + "0.046741, 0.065795, 0.101823, 0.215093, 0.534701",\ + "0.120319, 0.148529, 0.186126, 0.267902, 0.543427"); + } + + } /* end of arc ast_pwst_o[4]_ast_pwst_o[2]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "ast_pwst_o[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.017926, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.120368, 0.186170, 0.300859, 0.616258, 1.455810",\ + "0.125568, 0.191362, 0.306040, 0.621450, 1.461010",\ + "0.207819, 0.273839, 0.388973, 0.704719, 1.544218",\ + "0.296772, 0.362735, 0.477872, 0.794339, 1.635091",\ + "0.704776, 0.781389, 0.901027, 1.217412, 2.063059"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.017926, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.118650, 0.232611, 0.431328, 0.977612, 2.431972",\ + "0.118650, 0.232611, 0.431330, 0.977612, 2.431972",\ + "0.118650, 0.233259, 0.432463, 0.977612, 2.431972",\ + "0.120002, 0.233259, 0.433774, 0.977612, 2.431972",\ + "0.161250, 0.255527, 0.435044, 0.981481, 2.431972"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.020771, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.061996, 0.075776, 0.099734, 0.165532, 0.340715",\ + "0.068410, 0.082189, 0.106148, 0.171946, 0.347129",\ + "0.154377, 0.169144, 0.193145, 0.258865, 0.434247",\ + "0.245754, 0.264276, 0.291081, 0.357185, 0.532518",\ + "0.645975, 0.686648, 0.737659, 0.832084, 1.014107"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.020771, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.026953, 0.051423, 0.094862, 0.214557, 0.534102",\ + "0.026954, 0.051424, 0.094862, 0.214557, 0.534102",\ + "0.033450, 0.053875, 0.094993, 0.214557, 0.534241",\ + "0.046741, 0.065795, 0.101823, 0.215088, 0.534701",\ + "0.120319, 0.148529, 0.186126, 0.267902, 0.543427"); + } + + } /* end of arc ast_pwst_o[4]_ast_pwst_o[2]_una_min*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : recovery_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.120145, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.404676, 0.353105, 0.318351, 0.315478, 0.348023",\ + "0.454532, 0.402961, 0.368207, 0.365334, 0.397879",\ + "0.484555, 0.432984, 0.398230, 0.395357, 0.427902",\ + "0.566329, 0.514758, 0.480004, 0.477131, 0.509676",\ + "0.956464, 0.904894, 0.869963, 0.866772, 0.898621"); + } + + } /* end of arc clk_ast_ext_i_ast_pwst_o[2]_recrr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : removal_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.118140, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.316729, -0.270030, -0.234537, -0.184982, -0.086025",\ + "-0.365783, -0.319083, -0.283591, -0.234035, -0.135079",\ + "-0.396608, -0.349909, -0.314416, -0.264861, -0.165904",\ + "-0.478382, -0.431683, -0.396190, -0.346635, -0.247678",\ + "-0.868371, -0.821645, -0.786315, -0.736867, -0.638027"); + } + + } /* end of arc clk_ast_ext_i_ast_pwst_o[2]_remrr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "380000.531250, 380000.593750, 380000.718750, 380001.031250, 380001.875000",\ + "380000.625000, 380000.687500, 380000.812500, 380001.125000, 380001.968750",\ + "380000.687500, 380000.750000, 380000.875000, 380001.187500, 380002.031250",\ + "380000.750000, 380000.812500, 380000.937500, 380001.250000, 380002.093750",\ + "380001.062500, 380001.125000, 380001.250000, 380001.562500, 380002.406250"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.120145, 0.234100, 0.432069, 0.982878, 2.445448",\ + "0.120145, 0.234100, 0.432069, 0.982878, 2.445448",\ + "0.120145, 0.234100, 0.432069, 0.982878, 2.445448",\ + "0.120145, 0.234100, 0.432069, 0.982878, 2.445448",\ + "0.120145, 0.234100, 0.432069, 0.982878, 2.445448"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "380001.875000, 380001.875000, 380001.906250, 380001.968750, 380002.156250",\ + "380001.968750, 380001.968750, 380002.000000, 380002.062500, 380002.250000",\ + "380002.062500, 380002.062500, 380002.093750, 380002.156250, 380002.343750",\ + "380002.125000, 380002.125000, 380002.156250, 380002.218750, 380002.406250",\ + "380002.468750, 380002.468750, 380002.500000, 380002.562500, 380002.750000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.031251, 0.056161, 0.101276, 0.226771, 0.561875",\ + "0.031251, 0.056161, 0.101276, 0.226771, 0.561875",\ + "0.031251, 0.056161, 0.101276, 0.226771, 0.561875",\ + "0.031251, 0.056161, 0.101276, 0.226771, 0.561875",\ + "0.031251, 0.056161, 0.101276, 0.226771, 0.561875"); + } + + } /* end of arc clk_ast_tlul_i_ast_pwst_o[2]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.396377, 0.462195, 0.577090, 0.892530, 1.731965",\ + "0.483687, 0.549505, 0.664400, 0.979841, 1.819276",\ + "0.581466, 0.647284, 0.762179, 1.077619, 1.917054",\ + "0.654025, 0.719843, 0.834738, 1.150178, 1.989613",\ + "1.042482, 1.108301, 1.223195, 1.538636, 2.378071"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.118140, 0.231881, 0.431660, 0.979741, 2.437812",\ + "0.118140, 0.231881, 0.431660, 0.979741, 2.437812",\ + "0.118140, 0.231881, 0.431660, 0.979741, 2.437812",\ + "0.118140, 0.231881, 0.431660, 0.979741, 2.437812",\ + "0.118140, 0.231881, 0.431660, 0.979741, 2.437812"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.326727, 0.341464, 0.366815, 0.435950, 0.619738",\ + "0.414576, 0.429313, 0.454664, 0.523799, 0.707587",\ + "0.495656, 0.510394, 0.535744, 0.604879, 0.788667",\ + "0.553927, 0.568665, 0.594015, 0.663150, 0.846938",\ + "0.864022, 0.878760, 0.904110, 0.973245, 1.157033"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.026020, 0.051544, 0.096671, 0.220662, 0.551206",\ + "0.026020, 0.051544, 0.096671, 0.220662, 0.551206",\ + "0.026020, 0.051544, 0.096671, 0.220662, 0.551206",\ + "0.026020, 0.051544, 0.096671, 0.220662, 0.551206",\ + "0.026020, 0.051544, 0.096671, 0.220662, 0.551206"); + } + + } /* end of arc clk_ast_tlul_i_ast_pwst_o[2]_redg_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "380000.406250, 380000.468750, 380000.593750, 380000.906250, 380001.750000",\ + "380000.500000, 380000.562500, 380000.687500, 380001.000000, 380001.843750",\ + "380000.593750, 380000.656250, 380000.781250, 380001.093750, 380001.937500",\ + "380000.750000, 380000.812500, 380000.937500, 380001.250000, 380002.093750",\ + "380001.000000, 380001.062500, 380001.187500, 380001.500000, 380002.343750"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.120145, 0.234100, 0.432069, 0.982878, 2.445448",\ + "0.120145, 0.234100, 0.432069, 0.982878, 2.445448",\ + "0.120145, 0.234100, 0.432069, 0.982878, 2.445448",\ + "0.120145, 0.234100, 0.432069, 0.982878, 2.445448",\ + "0.120145, 0.234100, 0.432069, 0.982878, 2.445448"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "380001.781250, 380001.781250, 380001.812500, 380001.875000, 380002.062500",\ + "380001.875000, 380001.875000, 380001.906250, 380001.968750, 380002.156250",\ + "380002.000000, 380002.000000, 380002.031250, 380002.093750, 380002.281250",\ + "380002.187500, 380002.187500, 380002.218750, 380002.281250, 380002.468750",\ + "380002.500000, 380002.500000, 380002.531250, 380002.593750, 380002.781250"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.031236, 0.056156, 0.101275, 0.226769, 0.561877",\ + "0.031236, 0.056156, 0.101275, 0.226769, 0.561877",\ + "0.031236, 0.056156, 0.101275, 0.226769, 0.561877",\ + "0.031236, 0.056156, 0.101275, 0.226769, 0.561877",\ + "0.031236, 0.056156, 0.101275, 0.226769, 0.561877"); + } + + } /* end of arc padmux2ast_i[4]_ast_pwst_o[2]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "379999.937500, 380000.000000, 380000.093750, 380000.406250, 380001.250000",\ + "380000.031250, 380000.093750, 380000.187500, 380000.500000, 380001.343750",\ + "380000.093750, 380000.156250, 380000.250000, 380000.562500, 380001.406250",\ + "380000.250000, 380000.312500, 380000.406250, 380000.718750, 380001.562500",\ + "380000.468750, 380000.531250, 380000.625000, 380000.937500, 380001.781250"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.118145, 0.231881, 0.431660, 0.979741, 2.437852",\ + "0.118145, 0.231881, 0.431660, 0.979741, 2.437852",\ + "0.118145, 0.231881, 0.431660, 0.979741, 2.437852",\ + "0.118145, 0.231881, 0.431660, 0.979741, 2.437852",\ + "0.118145, 0.231881, 0.431660, 0.979741, 2.437852"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "380001.375000, 380001.406250, 380001.437500, 380001.500000, 380001.687500",\ + "380001.468750, 380001.500000, 380001.531250, 380001.593750, 380001.781250",\ + "380001.562500, 380001.593750, 380001.625000, 380001.687500, 380001.875000",\ + "380001.750000, 380001.781250, 380001.812500, 380001.875000, 380002.062500",\ + "380002.000000, 380002.031250, 380002.062500, 380002.125000, 380002.312500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.026020, 0.051544, 0.096671, 0.220662, 0.551206",\ + "0.026020, 0.051544, 0.096671, 0.220662, 0.551206",\ + "0.026020, 0.051544, 0.096671, 0.220662, 0.551206",\ + "0.026020, 0.051544, 0.096671, 0.220662, 0.551206",\ + "0.026020, 0.051544, 0.096671, 0.220662, 0.551206"); + } + + } /* end of arc padmux2ast_i[4]_ast_pwst_o[2]_una_min*/ + +} /* end of pin ast_pwst_h_o[2] */ + +pin("ast_pwst_h_o[1]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.101136 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : ast_pwst_h_o[1]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "970008.437500, 970008.625000, 970008.750000, 970009.000000, 970009.875000",\ + "970008.562500, 970008.750000, 970008.875000, 970009.125000, 970010.000000",\ + "970008.687500, 970008.875000, 970009.000000, 970009.250000, 970010.125000",\ + "970008.687500, 970008.875000, 970009.000000, 970009.250000, 970010.125000",\ + "970009.062500, 970009.250000, 970009.375000, 970009.625000, 970010.500000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "970005.937500, 970006.062500, 970006.187500, 970006.375000, 970007.000000",\ + "970006.062500, 970006.187500, 970006.312500, 970006.500000, 970007.125000",\ + "970006.062500, 970006.187500, 970006.312500, 970006.500000, 970007.125000",\ + "970006.187500, 970006.312500, 970006.437500, 970006.625000, 970007.250000",\ + "970006.437500, 970006.562500, 970006.687500, 970006.875000, 970007.500000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101"); + } + + } /* end of arc clk_ast_tlul_i_ast_pwst_o[1]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "7.046945, 7.238483, 7.357924, 7.616586, 8.489688",\ + "7.134256, 7.325794, 7.445234, 7.703897, 8.576999",\ + "7.232034, 7.423573, 7.543013, 7.801675, 8.674777",\ + "7.304593, 7.496131, 7.615571, 7.874234, 8.747335",\ + "7.693051, 7.884589, 8.004029, 8.262691, 9.135794"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "5.236063, 5.393305, 5.518865, 5.706539, 6.296398",\ + "5.323912, 5.481154, 5.606714, 5.794387, 6.384247",\ + "5.404993, 5.562235, 5.687795, 5.875468, 6.465328",\ + "5.463264, 5.620506, 5.746066, 5.933739, 6.523599",\ + "5.773359, 5.930601, 6.056160, 6.243834, 6.833694"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.242588, 0.288084, 0.303651, 0.497673, 1.551133",\ + "0.242588, 0.288084, 0.303651, 0.497673, 1.551133",\ + "0.242588, 0.288084, 0.303651, 0.497673, 1.551133",\ + "0.242588, 0.288084, 0.303651, 0.497673, 1.551133",\ + "0.242588, 0.288084, 0.303651, 0.497673, 1.551133"); + } + + } /* end of arc clk_ast_tlul_i_ast_pwst_o[1]_redg_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "380006.593750, 380006.781250, 380006.906250, 380007.156250, 380008.031250",\ + "380006.687500, 380006.875000, 380007.000000, 380007.250000, 380008.125000",\ + "380006.781250, 380006.968750, 380007.093750, 380007.343750, 380008.218750",\ + "380006.937500, 380007.125000, 380007.250000, 380007.500000, 380008.375000",\ + "380007.187500, 380007.375000, 380007.500000, 380007.750000, 380008.625000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "380006.281250, 380006.437500, 380006.562500, 380006.750000, 380007.343750",\ + "380006.375000, 380006.531250, 380006.656250, 380006.843750, 380007.437500",\ + "380006.500000, 380006.656250, 380006.781250, 380006.968750, 380007.562500",\ + "380006.687500, 380006.843750, 380006.968750, 380007.156250, 380007.750000",\ + "380007.000000, 380007.156250, 380007.281250, 380007.468750, 380008.062500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101"); + } + + } /* end of arc padmux2ast_i[4]_ast_pwst_o[1]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "380006.593750, 380006.781250, 380006.906250, 380007.156250, 380008.031250",\ + "380006.687500, 380006.875000, 380007.000000, 380007.250000, 380008.125000",\ + "380006.750000, 380006.937500, 380007.062500, 380007.312500, 380008.187500",\ + "380006.906250, 380007.093750, 380007.218750, 380007.468750, 380008.343750",\ + "380007.125000, 380007.312500, 380007.437500, 380007.687500, 380008.562500"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "380006.281250, 380006.437500, 380006.562500, 380006.750000, 380007.343750",\ + "380006.375000, 380006.531250, 380006.656250, 380006.843750, 380007.437500",\ + "380006.468750, 380006.625000, 380006.750000, 380006.937500, 380007.531250",\ + "380006.656250, 380006.812500, 380006.937500, 380007.125000, 380007.718750",\ + "380006.906250, 380007.062500, 380007.187500, 380007.375000, 380007.968750"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\ + "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\ + "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\ + "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\ + "0.242595, 0.288092, 0.303657, 0.497674, 1.551132"); + } + + } /* end of arc padmux2ast_i[4]_ast_pwst_o[1]_una_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "970005.812500, 970005.937500, 970006.062500, 970006.250000, 970006.875000",\ + "970005.937500, 970006.062500, 970006.187500, 970006.375000, 970007.000000",\ + "970005.937500, 970006.062500, 970006.187500, 970006.375000, 970007.000000",\ + "970006.187500, 970006.312500, 970006.437500, 970006.625000, 970007.250000",\ + "970006.437500, 970006.562500, 970006.687500, 970006.875000, 970007.500000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "970008.312500, 970008.500000, 970008.625000, 970008.875000, 970009.750000",\ + "970008.437500, 970008.625000, 970008.750000, 970009.000000, 970009.875000",\ + "970008.562500, 970008.750000, 970008.875000, 970009.125000, 970010.000000",\ + "970008.812500, 970009.000000, 970009.125000, 970009.375000, 970010.250000",\ + "970009.062500, 970009.250000, 970009.375000, 970009.625000, 970010.500000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832"); + } + + } /* end of arc padmux2ast_i[4]_ast_pwst_o[1]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "970005.812500, 970005.937500, 970006.062500, 970006.250000, 970006.875000",\ + "970005.937500, 970006.062500, 970006.187500, 970006.375000, 970007.000000",\ + "970005.937500, 970006.062500, 970006.187500, 970006.375000, 970007.000000",\ + "970006.062500, 970006.187500, 970006.312500, 970006.500000, 970007.125000",\ + "970006.312500, 970006.437500, 970006.562500, 970006.750000, 970007.375000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\ + "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\ + "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\ + "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\ + "0.242595, 0.288092, 0.303657, 0.497674, 1.551132"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "970008.312500, 970008.500000, 970008.625000, 970008.875000, 970009.750000",\ + "970008.437500, 970008.625000, 970008.750000, 970009.000000, 970009.875000",\ + "970008.562500, 970008.750000, 970008.875000, 970009.125000, 970010.000000",\ + "970008.687500, 970008.875000, 970009.000000, 970009.250000, 970010.125000",\ + "970008.937500, 970009.125000, 970009.250000, 970009.500000, 970010.375000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127"); + } + + } /* end of arc padmux2ast_i[4]_ast_pwst_o[1]_inv_min*/ + + timing () { + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "590006.687500, 590006.875000, 590007.000000, 590007.250000, 590008.125000",\ + "590006.812500, 590007.000000, 590007.125000, 590007.375000, 590008.250000",\ + "590006.812500, 590007.000000, 590007.125000, 590007.375000, 590008.250000",\ + "590006.937500, 590007.125000, 590007.250000, 590007.500000, 590008.375000",\ + "590007.187500, 590007.375000, 590007.500000, 590007.750000, 590008.625000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.256090, 0.317188, 0.317188, 0.797460, 2.395127",\ + "0.256090, 0.317188, 0.317188, 0.797460, 2.395127",\ + "0.256090, 0.317188, 0.317188, 0.797460, 2.395127",\ + "0.256090, 0.317188, 0.317188, 0.797460, 2.395127",\ + "0.256090, 0.317188, 0.317188, 0.797460, 2.395127"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "590005.562500, 590005.687500, 590005.812500, 590006.000000, 590006.625000",\ + "590005.687500, 590005.812500, 590005.937500, 590006.125000, 590006.750000",\ + "590005.812500, 590005.937500, 590006.062500, 590006.250000, 590006.875000",\ + "590005.937500, 590006.062500, 590006.187500, 590006.375000, 590007.000000",\ + "590006.312500, 590006.437500, 590006.562500, 590006.750000, 590007.375000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101"); + } + + } /* end of arc padmux2ast_i[5]_ast_pwst_o[1]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "590006.687500, 590006.875000, 590007.000000, 590007.250000, 590008.125000",\ + "590006.687500, 590006.875000, 590007.000000, 590007.250000, 590008.125000",\ + "590006.812500, 590007.000000, 590007.125000, 590007.375000, 590008.250000",\ + "590006.937500, 590007.125000, 590007.250000, 590007.500000, 590008.375000",\ + "590007.187500, 590007.375000, 590007.500000, 590007.750000, 590008.625000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "590005.562500, 590005.687500, 590005.812500, 590006.000000, 590006.625000",\ + "590005.687500, 590005.812500, 590005.937500, 590006.125000, 590006.750000",\ + "590005.812500, 590005.937500, 590006.062500, 590006.250000, 590006.875000",\ + "590005.937500, 590006.062500, 590006.187500, 590006.375000, 590007.000000",\ + "590006.187500, 590006.312500, 590006.437500, 590006.625000, 590007.250000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101"); + } + + } /* end of arc padmux2ast_i[5]_ast_pwst_o[1]_una_min*/ + +} /* end of pin ast_pwst_h_o[1] */ + +pin("ast_pwst_h_o[0]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.101136 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : ast_pwst_h_o[0]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "970008.437500, 970008.625000, 970008.750000, 970009.000000, 970009.875000",\ + "970008.562500, 970008.750000, 970008.875000, 970009.125000, 970010.000000",\ + "970008.687500, 970008.875000, 970009.000000, 970009.250000, 970010.125000",\ + "970008.687500, 970008.875000, 970009.000000, 970009.250000, 970010.125000",\ + "970009.062500, 970009.250000, 970009.375000, 970009.625000, 970010.500000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "970005.937500, 970006.062500, 970006.187500, 970006.375000, 970007.000000",\ + "970006.062500, 970006.187500, 970006.312500, 970006.500000, 970007.125000",\ + "970006.062500, 970006.187500, 970006.312500, 970006.500000, 970007.125000",\ + "970006.187500, 970006.312500, 970006.437500, 970006.625000, 970007.250000",\ + "970006.437500, 970006.562500, 970006.687500, 970006.875000, 970007.500000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101"); + } + + } /* end of arc clk_ast_tlul_i_ast_pwst_o[0]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "7.046945, 7.238483, 7.357924, 7.616586, 8.489688",\ + "7.134256, 7.325794, 7.445234, 7.703897, 8.576999",\ + "7.232034, 7.423573, 7.543013, 7.801675, 8.674777",\ + "7.304593, 7.496131, 7.615571, 7.874234, 8.747335",\ + "7.693051, 7.884589, 8.004029, 8.262691, 9.135794"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "5.236063, 5.393305, 5.518865, 5.706539, 6.296398",\ + "5.323912, 5.481154, 5.606714, 5.794387, 6.384247",\ + "5.404993, 5.562235, 5.687795, 5.875468, 6.465328",\ + "5.463264, 5.620506, 5.746066, 5.933739, 6.523599",\ + "5.773359, 5.930601, 6.056160, 6.243834, 6.833694"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.242588, 0.288084, 0.303651, 0.497673, 1.551133",\ + "0.242588, 0.288084, 0.303651, 0.497673, 1.551133",\ + "0.242588, 0.288084, 0.303651, 0.497673, 1.551133",\ + "0.242588, 0.288084, 0.303651, 0.497673, 1.551133",\ + "0.242588, 0.288084, 0.303651, 0.497673, 1.551133"); + } + + } /* end of arc clk_ast_tlul_i_ast_pwst_o[0]_redg_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "380006.593750, 380006.781250, 380006.906250, 380007.156250, 380008.031250",\ + "380006.687500, 380006.875000, 380007.000000, 380007.250000, 380008.125000",\ + "380006.781250, 380006.968750, 380007.093750, 380007.343750, 380008.218750",\ + "380006.937500, 380007.125000, 380007.250000, 380007.500000, 380008.375000",\ + "380007.187500, 380007.375000, 380007.500000, 380007.750000, 380008.625000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "380006.281250, 380006.437500, 380006.562500, 380006.750000, 380007.343750",\ + "380006.375000, 380006.531250, 380006.656250, 380006.843750, 380007.437500",\ + "380006.500000, 380006.656250, 380006.781250, 380006.968750, 380007.562500",\ + "380006.687500, 380006.843750, 380006.968750, 380007.156250, 380007.750000",\ + "380007.000000, 380007.156250, 380007.281250, 380007.468750, 380008.062500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101"); + } + + } /* end of arc padmux2ast_i[4]_ast_pwst_o[0]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "380006.593750, 380006.781250, 380006.906250, 380007.156250, 380008.031250",\ + "380006.687500, 380006.875000, 380007.000000, 380007.250000, 380008.125000",\ + "380006.750000, 380006.937500, 380007.062500, 380007.312500, 380008.187500",\ + "380006.906250, 380007.093750, 380007.218750, 380007.468750, 380008.343750",\ + "380007.125000, 380007.312500, 380007.437500, 380007.687500, 380008.562500"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "380006.281250, 380006.437500, 380006.562500, 380006.750000, 380007.343750",\ + "380006.375000, 380006.531250, 380006.656250, 380006.843750, 380007.437500",\ + "380006.468750, 380006.625000, 380006.750000, 380006.937500, 380007.531250",\ + "380006.656250, 380006.812500, 380006.937500, 380007.125000, 380007.718750",\ + "380006.906250, 380007.062500, 380007.187500, 380007.375000, 380007.968750"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\ + "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\ + "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\ + "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\ + "0.242595, 0.288092, 0.303657, 0.497674, 1.551132"); + } + + } /* end of arc padmux2ast_i[4]_ast_pwst_o[0]_una_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "970005.812500, 970005.937500, 970006.062500, 970006.250000, 970006.875000",\ + "970005.937500, 970006.062500, 970006.187500, 970006.375000, 970007.000000",\ + "970005.937500, 970006.062500, 970006.187500, 970006.375000, 970007.000000",\ + "970006.187500, 970006.312500, 970006.437500, 970006.625000, 970007.250000",\ + "970006.437500, 970006.562500, 970006.687500, 970006.875000, 970007.500000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "970008.312500, 970008.500000, 970008.625000, 970008.875000, 970009.750000",\ + "970008.437500, 970008.625000, 970008.750000, 970009.000000, 970009.875000",\ + "970008.562500, 970008.750000, 970008.875000, 970009.125000, 970010.000000",\ + "970008.812500, 970009.000000, 970009.125000, 970009.375000, 970010.250000",\ + "970009.062500, 970009.250000, 970009.375000, 970009.625000, 970010.500000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832"); + } + + } /* end of arc padmux2ast_i[4]_ast_pwst_o[0]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "970005.812500, 970005.937500, 970006.062500, 970006.250000, 970006.875000",\ + "970005.937500, 970006.062500, 970006.187500, 970006.375000, 970007.000000",\ + "970005.937500, 970006.062500, 970006.187500, 970006.375000, 970007.000000",\ + "970006.062500, 970006.187500, 970006.312500, 970006.500000, 970007.125000",\ + "970006.312500, 970006.437500, 970006.562500, 970006.750000, 970007.375000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\ + "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\ + "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\ + "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\ + "0.242595, 0.288092, 0.303657, 0.497674, 1.551132"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "970008.312500, 970008.500000, 970008.625000, 970008.875000, 970009.750000",\ + "970008.437500, 970008.625000, 970008.750000, 970009.000000, 970009.875000",\ + "970008.562500, 970008.750000, 970008.875000, 970009.125000, 970010.000000",\ + "970008.687500, 970008.875000, 970009.000000, 970009.250000, 970010.125000",\ + "970008.937500, 970009.125000, 970009.250000, 970009.500000, 970010.375000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127"); + } + + } /* end of arc padmux2ast_i[4]_ast_pwst_o[0]_inv_min*/ + + timing () { + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "590006.687500, 590006.875000, 590007.000000, 590007.250000, 590008.125000",\ + "590006.812500, 590007.000000, 590007.125000, 590007.375000, 590008.250000",\ + "590006.812500, 590007.000000, 590007.125000, 590007.375000, 590008.250000",\ + "590006.937500, 590007.125000, 590007.250000, 590007.500000, 590008.375000",\ + "590007.187500, 590007.375000, 590007.500000, 590007.750000, 590008.625000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.256090, 0.317188, 0.317188, 0.797460, 2.395127",\ + "0.256090, 0.317188, 0.317188, 0.797460, 2.395127",\ + "0.256090, 0.317188, 0.317188, 0.797460, 2.395127",\ + "0.256090, 0.317188, 0.317188, 0.797460, 2.395127",\ + "0.256090, 0.317188, 0.317188, 0.797460, 2.395127"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "590005.562500, 590005.687500, 590005.812500, 590006.000000, 590006.625000",\ + "590005.687500, 590005.812500, 590005.937500, 590006.125000, 590006.750000",\ + "590005.812500, 590005.937500, 590006.062500, 590006.250000, 590006.875000",\ + "590005.937500, 590006.062500, 590006.187500, 590006.375000, 590007.000000",\ + "590006.312500, 590006.437500, 590006.562500, 590006.750000, 590007.375000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101"); + } + + } /* end of arc padmux2ast_i[5]_ast_pwst_o[0]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "590006.687500, 590006.875000, 590007.000000, 590007.250000, 590008.125000",\ + "590006.687500, 590006.875000, 590007.000000, 590007.250000, 590008.125000",\ + "590006.812500, 590007.000000, 590007.125000, 590007.375000, 590008.250000",\ + "590006.937500, 590007.125000, 590007.250000, 590007.500000, 590008.375000",\ + "590007.187500, 590007.375000, 590007.500000, 590007.750000, 590008.625000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "590005.562500, 590005.687500, 590005.812500, 590006.000000, 590006.625000",\ + "590005.687500, 590005.812500, 590005.937500, 590006.125000, 590006.750000",\ + "590005.812500, 590005.937500, 590006.062500, 590006.250000, 590006.875000",\ + "590005.937500, 590006.062500, 590006.187500, 590006.375000, 590007.000000",\ + "590006.187500, 590006.312500, 590006.437500, 590006.625000, 590007.250000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101"); + } + + } /* end of arc padmux2ast_i[5]_ast_pwst_o[0]_una_min*/ + +} /* end of pin ast_pwst_h_o[0] */ +} /* end of bus ast_pwst_h_o */ + +pin("main_pd_ni") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001140 ; + + /* Other user defined attributes. */ + original_pin : main_pd_ni; +} /* end of pin main_pd_ni */ + +pin("main_env_iso_en_i") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000488 ; + + /* Other user defined attributes. */ + original_pin : main_env_iso_en_i; +} /* end of pin main_env_iso_en_i */ + +pin("flash_power_down_h_o") { + direction : output ; + max_transition : 3.720000 ; + min_transition : 0.000000 ; + max_capacitance : 0.350585 ; + min_capacitance : 0.000387 ; + max_fanout : 50.000000 ; + capacitance : 0.004062 ; + + /* Other user defined attributes. */ + original_pin : flash_power_down_h_o; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "380000.718750, 380000.781250, 380000.937500, 380001.375000, 380002.718750",\ + "380000.812500, 380000.875000, 380001.031250, 380001.468750, 380002.812500",\ + "380000.875000, 380000.937500, 380001.093750, 380001.531250, 380002.875000",\ + "380000.937500, 380001.000000, 380001.156250, 380001.593750, 380002.937500",\ + "380001.250000, 380001.312500, 380001.468750, 380001.906250, 380003.250000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.074057, 0.193193, 0.452097, 1.259663, 3.712074",\ + "0.074058, 0.193193, 0.452097, 1.259663, 3.712070",\ + "0.074060, 0.193194, 0.452097, 1.259660, 3.712049",\ + "0.074063, 0.193195, 0.452097, 1.259657, 3.712028",\ + "0.074111, 0.193204, 0.452092, 1.259600, 3.711658"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "380002.000000, 380002.031250, 380002.093750, 380002.312500, 380002.843750",\ + "380002.093750, 380002.125000, 380002.187500, 380002.406250, 380002.937500",\ + "380002.187500, 380002.218750, 380002.281250, 380002.500000, 380003.031250",\ + "380002.250000, 380002.281250, 380002.343750, 380002.562500, 380003.093750",\ + "380002.593750, 380002.625000, 380002.687500, 380002.906250, 380003.437500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.054518, 0.105901, 0.199326, 0.496289, 1.444364",\ + "0.054518, 0.105901, 0.199326, 0.496289, 1.444364",\ + "0.054518, 0.105901, 0.199326, 0.496289, 1.444364",\ + "0.054518, 0.105901, 0.199326, 0.496289, 1.444364",\ + "0.054518, 0.105901, 0.199326, 0.496289, 1.444364"); + } + + } /* end of arc clk_ast_tlul_i_flash_power_down_h_o_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.352648, 0.424230, 0.570187, 1.017271, 2.367661",\ + "0.440969, 0.512551, 0.658508, 1.105592, 2.455982",\ + "0.531538, 0.603120, 0.749077, 1.196161, 2.546552",\ + "0.596976, 0.668558, 0.814515, 1.261599, 2.611990",\ + "0.939689, 1.011271, 1.157229, 1.604312, 2.954703"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.074048, 0.193192, 0.452098, 1.259674, 3.712141",\ + "0.074048, 0.193192, 0.452098, 1.259674, 3.712141",\ + "0.074048, 0.193192, 0.452098, 1.259674, 3.712141",\ + "0.074048, 0.193192, 0.452098, 1.259674, 3.712141",\ + "0.074048, 0.193192, 0.452098, 1.259674, 3.712141"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.254546, 0.300198, 0.374019, 0.564384, 1.125543",\ + "0.341890, 0.387542, 0.461363, 0.651728, 1.212887",\ + "0.422786, 0.468439, 0.542260, 0.732625, 1.293784",\ + "0.480635, 0.526288, 0.600109, 0.790475, 1.351633",\ + "0.785321, 0.830974, 0.904795, 1.095161, 1.656318"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.054514, 0.105890, 0.199332, 0.496290, 1.444361",\ + "0.054514, 0.105890, 0.199332, 0.496290, 1.444361",\ + "0.054513, 0.105889, 0.199332, 0.496290, 1.444360",\ + "0.054513, 0.105887, 0.199332, 0.496290, 1.444359",\ + "0.054513, 0.105887, 0.199332, 0.496290, 1.444358"); + } + + } /* end of arc clk_ast_tlul_i_flash_power_down_h_o_redg_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "380000.593750, 380000.656250, 380000.812500, 380001.250000, 380002.593750",\ + "380000.687500, 380000.750000, 380000.906250, 380001.343750, 380002.687500",\ + "380000.781250, 380000.843750, 380001.000000, 380001.437500, 380002.781250",\ + "380000.937500, 380001.000000, 380001.156250, 380001.593750, 380002.937500",\ + "380001.187500, 380001.250000, 380001.406250, 380001.843750, 380003.187500"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.074048, 0.193192, 0.452098, 1.259674, 3.712141",\ + "0.074048, 0.193192, 0.452098, 1.259674, 3.712141",\ + "0.074048, 0.193192, 0.452098, 1.259674, 3.712141",\ + "0.074048, 0.193192, 0.452098, 1.259674, 3.712141",\ + "0.074048, 0.193192, 0.452098, 1.259674, 3.712141"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "380001.906250, 380001.937500, 380002.000000, 380002.218750, 380002.750000",\ + "380002.000000, 380002.031250, 380002.093750, 380002.312500, 380002.843750",\ + "380002.125000, 380002.156250, 380002.218750, 380002.437500, 380002.968750",\ + "380002.312500, 380002.343750, 380002.406250, 380002.625000, 380003.156250",\ + "380002.625000, 380002.656250, 380002.718750, 380002.937500, 380003.468750"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.054518, 0.105901, 0.199326, 0.496289, 1.444364",\ + "0.054518, 0.105901, 0.199326, 0.496289, 1.444364",\ + "0.054518, 0.105901, 0.199326, 0.496289, 1.444364",\ + "0.054518, 0.105901, 0.199326, 0.496289, 1.444364",\ + "0.054518, 0.105901, 0.199326, 0.496289, 1.444364"); + } + + } /* end of arc padmux2ast_i[4]_flash_power_down_h_o_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "380000.593750, 380000.656250, 380000.812500, 380001.250000, 380002.593750",\ + "380000.687500, 380000.750000, 380000.906250, 380001.343750, 380002.687500",\ + "380000.750000, 380000.812500, 380000.968750, 380001.406250, 380002.750000",\ + "380000.906250, 380000.968750, 380001.125000, 380001.562500, 380002.906250",\ + "380001.125000, 380001.187500, 380001.343750, 380001.781250, 380003.125000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.074048, 0.193192, 0.452098, 1.259674, 3.712141",\ + "0.074048, 0.193192, 0.452098, 1.259674, 3.712141",\ + "0.074048, 0.193192, 0.452098, 1.259674, 3.712141",\ + "0.074048, 0.193192, 0.452098, 1.259674, 3.712141",\ + "0.074048, 0.193192, 0.452098, 1.259674, 3.712141"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "380001.906250, 380001.937500, 380002.000000, 380002.218750, 380002.750000",\ + "380002.000000, 380002.031250, 380002.093750, 380002.312500, 380002.843750",\ + "380002.093750, 380002.125000, 380002.187500, 380002.406250, 380002.937500",\ + "380002.281250, 380002.312500, 380002.375000, 380002.593750, 380003.125000",\ + "380002.531250, 380002.562500, 380002.625000, 380002.843750, 380003.375000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.054518, 0.105901, 0.199326, 0.496289, 1.444364",\ + "0.054518, 0.105901, 0.199326, 0.496289, 1.444364",\ + "0.054518, 0.105901, 0.199326, 0.496289, 1.444364",\ + "0.054518, 0.105901, 0.199326, 0.496289, 1.444364",\ + "0.054518, 0.105901, 0.199326, 0.496289, 1.444364"); + } + + } /* end of arc padmux2ast_i[4]_flash_power_down_h_o_una_min*/ + +} /* end of pin flash_power_down_h_o */ + +pin("flash_power_ready_h_o") { + direction : output ; + max_transition : 3.720000 ; + min_transition : 0.000000 ; + max_capacitance : 0.350585 ; + min_capacitance : 0.000387 ; + max_fanout : 50.000000 ; + capacitance : 0.004062 ; + + /* Other user defined attributes. */ + original_pin : flash_power_ready_h_o; +} /* end of pin flash_power_ready_h_o */ +bus ( otp_power_seq_i ) { + + bus_type : BUS2_type5 ; + direction : input ; + +pin("otp_power_seq_i[1]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.002066 ; + + /* Other user defined attributes. */ + original_pin : otp_power_seq_i[1]; +} /* end of pin otp_power_seq_i[1] */ + +pin("otp_power_seq_i[0]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.002439 ; + + /* Other user defined attributes. */ + original_pin : otp_power_seq_i[0]; +} /* end of pin otp_power_seq_i[0] */ +} /* end of bus otp_power_seq_i */ +bus ( otp_power_seq_h_o ) { + + bus_type : BUS2_type5 ; + direction : output ; + +pin("otp_power_seq_h_o[1]") { + direction : output ; + max_transition : 3.720000 ; + min_transition : 0.000000 ; + max_capacitance : 0.350585 ; + min_capacitance : 0.000387 ; + max_fanout : 50.000000 ; + capacitance : 0.004062 ; + + /* Other user defined attributes. */ + original_pin : otp_power_seq_h_o[1]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "380000.812500, 380000.875000, 380001.031250, 380001.468750, 380002.812500",\ + "380000.906250, 380000.968750, 380001.125000, 380001.562500, 380002.906250",\ + "380000.968750, 380001.031250, 380001.187500, 380001.625000, 380002.968750",\ + "380001.031250, 380001.093750, 380001.250000, 380001.687500, 380003.031250",\ + "380001.343750, 380001.406250, 380001.562500, 380002.000000, 380003.343750"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.074053, 0.193192, 0.452098, 1.259669, 3.712109",\ + "0.074053, 0.193192, 0.452098, 1.259669, 3.712109",\ + "0.074053, 0.193192, 0.452098, 1.259669, 3.712109",\ + "0.074053, 0.193192, 0.452098, 1.259669, 3.712109",\ + "0.074053, 0.193192, 0.452098, 1.259669, 3.712109"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "380002.312500, 380002.343750, 380002.406250, 380002.625000, 380003.156250",\ + "380002.406250, 380002.437500, 380002.500000, 380002.718750, 380003.250000",\ + "380002.500000, 380002.531250, 380002.593750, 380002.812500, 380003.343750",\ + "380002.562500, 380002.593750, 380002.656250, 380002.875000, 380003.406250",\ + "380002.906250, 380002.937500, 380003.000000, 380003.218750, 380003.750000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.054525, 0.105893, 0.199328, 0.496289, 1.444343",\ + "0.054525, 0.105893, 0.199328, 0.496289, 1.444343",\ + "0.054525, 0.105893, 0.199328, 0.496289, 1.444343",\ + "0.054525, 0.105893, 0.199328, 0.496289, 1.444343",\ + "0.054525, 0.105893, 0.199328, 0.496289, 1.444343"); + } + + } /* end of arc clk_ast_tlul_i_otp_power_seq_h_o[1]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.448711, 0.520292, 0.666247, 1.113340, 2.463725",\ + "0.537164, 0.608745, 0.754701, 1.201793, 2.552178",\ + "0.627117, 0.698698, 0.844654, 1.291746, 2.642131",\ + "0.691522, 0.763103, 0.909059, 1.356151, 2.706536",\ + "1.028584, 1.100166, 1.246121, 1.693213, 3.043598"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.074053, 0.193192, 0.452098, 1.259669, 3.712109",\ + "0.074053, 0.193192, 0.452098, 1.259669, 3.712109",\ + "0.074053, 0.193192, 0.452098, 1.259669, 3.712109",\ + "0.074053, 0.193192, 0.452098, 1.259669, 3.712109",\ + "0.074053, 0.193192, 0.452098, 1.259669, 3.712109"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.535143, 0.580795, 0.654612, 0.844979, 1.406126",\ + "0.622520, 0.668171, 0.741989, 0.932356, 1.493503",\ + "0.703389, 0.749041, 0.822858, 1.013225, 1.574372",\ + "0.761087, 0.806739, 0.880556, 1.070923, 1.632070",\ + "1.064074, 1.109726, 1.183543, 1.373910, 1.935057"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.054525, 0.105893, 0.199328, 0.496289, 1.444343",\ + "0.054525, 0.105893, 0.199328, 0.496289, 1.444343",\ + "0.054525, 0.105893, 0.199328, 0.496289, 1.444343",\ + "0.054525, 0.105893, 0.199328, 0.496289, 1.444343",\ + "0.054525, 0.105893, 0.199328, 0.496289, 1.444343"); + } + + } /* end of arc clk_ast_tlul_i_otp_power_seq_h_o[1]_redg_min*/ + + timing () { + related_pin : "otp_power_seq_i[1]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.280735, 0.352314, 0.498262, 0.945381, 2.295748",\ + "0.365932, 0.437494, 0.583395, 1.030705, 2.380943",\ + "0.458471, 0.529972, 0.675698, 1.123714, 2.473475",\ + "0.634070, 0.705499, 0.850886, 1.299582, 2.649080",\ + "0.942777, 1.014243, 1.159029, 1.607148, 2.957408"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.074065, 0.193195, 0.452096, 1.259655, 3.712015",\ + "0.074153, 0.193212, 0.452096, 1.259655, 3.712015",\ + "0.074479, 0.193278, 0.452096, 1.259655, 3.712015",\ + "0.075512, 0.193773, 0.452096, 1.259655, 3.712015",\ + "0.077859, 0.195201, 0.452096, 1.259655, 3.712015"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.164110, 0.209762, 0.283580, 0.473944, 1.035104",\ + "0.247135, 0.292784, 0.366597, 0.556994, 1.118023",\ + "0.324377, 0.370013, 0.443807, 0.634329, 1.194869",\ + "0.452551, 0.498155, 0.571901, 0.762742, 1.322028",\ + "0.650770, 0.696491, 0.770670, 0.961172, 1.520128"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.054518, 0.105900, 0.199326, 0.496289, 1.444363",\ + "0.054583, 0.105900, 0.199350, 0.496296, 1.444363",\ + "0.054828, 0.105900, 0.199442, 0.496321, 1.444363",\ + "0.055455, 0.105900, 0.199678, 0.496387, 1.444363",\ + "0.057468, 0.107107, 0.200875, 0.496387, 1.444363"); + } + + } /* end of arc otp_power_seq_i[1]_otp_power_seq_h_o[1]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "otp_power_seq_i[1]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.280735, 0.352314, 0.498262, 0.945381, 2.295748",\ + "0.365932, 0.437494, 0.583395, 1.030705, 2.380943",\ + "0.458471, 0.529972, 0.675698, 1.123714, 2.473475",\ + "0.634070, 0.705499, 0.850886, 1.299582, 2.649080",\ + "0.942777, 1.014243, 1.159029, 1.607148, 2.957408"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.074065, 0.193195, 0.451499, 1.259037, 3.706044",\ + "0.074153, 0.193212, 0.451499, 1.259037, 3.706044",\ + "0.074479, 0.193278, 0.451499, 1.259037, 3.706044",\ + "0.075512, 0.193773, 0.451499, 1.259037, 3.706044",\ + "0.077859, 0.195201, 0.451499, 1.259378, 3.706689"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.164110, 0.209762, 0.283580, 0.473944, 1.035104",\ + "0.247135, 0.292784, 0.366597, 0.556994, 1.118023",\ + "0.324377, 0.370013, 0.443807, 0.634329, 1.194869",\ + "0.452551, 0.498155, 0.571901, 0.762742, 1.322028",\ + "0.650770, 0.696491, 0.770670, 0.961172, 1.520128"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.054518, 0.104862, 0.199326, 0.496289, 1.441414",\ + "0.054583, 0.104862, 0.199350, 0.496296, 1.441414",\ + "0.054828, 0.104862, 0.199442, 0.496321, 1.441414",\ + "0.055455, 0.104862, 0.199678, 0.496356, 1.441414",\ + "0.057468, 0.107107, 0.200875, 0.496356, 1.442153"); + } + + } /* end of arc otp_power_seq_i[1]_otp_power_seq_h_o[1]_una_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "380000.687500, 380000.750000, 380000.906250, 380001.343750, 380002.687500",\ + "380000.781250, 380000.843750, 380001.000000, 380001.437500, 380002.781250",\ + "380000.875000, 380000.937500, 380001.093750, 380001.531250, 380002.875000",\ + "380001.031250, 380001.093750, 380001.250000, 380001.687500, 380003.031250",\ + "380001.281250, 380001.343750, 380001.500000, 380001.937500, 380003.281250"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.074053, 0.193192, 0.452098, 1.259669, 3.712109",\ + "0.074053, 0.193192, 0.452098, 1.259669, 3.712109",\ + "0.074053, 0.193192, 0.452098, 1.259669, 3.712109",\ + "0.074053, 0.193192, 0.452098, 1.259669, 3.712109",\ + "0.074053, 0.193192, 0.452098, 1.259669, 3.712109"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "380002.218750, 380002.250000, 380002.312500, 380002.531250, 380003.062500",\ + "380002.312500, 380002.343750, 380002.406250, 380002.625000, 380003.156250",\ + "380002.437500, 380002.468750, 380002.531250, 380002.750000, 380003.281250",\ + "380002.625000, 380002.656250, 380002.718750, 380002.937500, 380003.468750",\ + "380002.937500, 380002.968750, 380003.031250, 380003.250000, 380003.781250"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.054525, 0.105893, 0.199328, 0.496289, 1.444343",\ + "0.054525, 0.105893, 0.199328, 0.496289, 1.444343",\ + "0.054525, 0.105893, 0.199328, 0.496289, 1.444343",\ + "0.054525, 0.105893, 0.199328, 0.496289, 1.444343",\ + "0.054525, 0.105893, 0.199328, 0.496289, 1.444343"); + } + + } /* end of arc padmux2ast_i[4]_otp_power_seq_h_o[1]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "380000.687500, 380000.750000, 380000.906250, 380001.343750, 380002.687500",\ + "380000.781250, 380000.843750, 380001.000000, 380001.437500, 380002.781250",\ + "380000.843750, 380000.906250, 380001.062500, 380001.500000, 380002.843750",\ + "380001.000000, 380001.062500, 380001.218750, 380001.656250, 380003.000000",\ + "380001.218750, 380001.281250, 380001.437500, 380001.875000, 380003.218750"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.074053, 0.193192, 0.452098, 1.259669, 3.712109",\ + "0.074053, 0.193192, 0.452098, 1.259669, 3.712109",\ + "0.074053, 0.193192, 0.452098, 1.259669, 3.712109",\ + "0.074053, 0.193192, 0.452098, 1.259669, 3.712109",\ + "0.074053, 0.193192, 0.452098, 1.259669, 3.712109"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "380002.218750, 380002.250000, 380002.312500, 380002.531250, 380003.062500",\ + "380002.312500, 380002.343750, 380002.406250, 380002.625000, 380003.156250",\ + "380002.406250, 380002.437500, 380002.500000, 380002.718750, 380003.250000",\ + "380002.593750, 380002.625000, 380002.687500, 380002.906250, 380003.437500",\ + "380002.843750, 380002.875000, 380002.937500, 380003.156250, 380003.687500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.054525, 0.105893, 0.199328, 0.496289, 1.444343",\ + "0.054525, 0.105893, 0.199328, 0.496289, 1.444343",\ + "0.054525, 0.105893, 0.199328, 0.496289, 1.444343",\ + "0.054525, 0.105893, 0.199328, 0.496289, 1.444343",\ + "0.054525, 0.105893, 0.199328, 0.496289, 1.444343"); + } + + } /* end of arc padmux2ast_i[4]_otp_power_seq_h_o[1]_una_min*/ + +} /* end of pin otp_power_seq_h_o[1] */ + +pin("otp_power_seq_h_o[0]") { + direction : output ; + max_transition : 3.720000 ; + min_transition : 0.000000 ; + max_capacitance : 0.350585 ; + min_capacitance : 0.000387 ; + max_fanout : 50.000000 ; + capacitance : 0.004062 ; + + /* Other user defined attributes. */ + original_pin : otp_power_seq_h_o[0]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "380002.312500, 380002.406250, 380002.531250, 380003.000000, 380004.343750",\ + "380002.406250, 380002.500000, 380002.625000, 380003.093750, 380004.437500",\ + "380002.500000, 380002.593750, 380002.718750, 380003.187500, 380004.531250",\ + "380002.562500, 380002.656250, 380002.781250, 380003.250000, 380004.593750",\ + "380002.906250, 380003.000000, 380003.125000, 380003.593750, 380004.937500"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.073833, 0.193149, 0.452120, 1.259926, 3.713809",\ + "0.073833, 0.193149, 0.452120, 1.259926, 3.713809",\ + "0.073833, 0.193149, 0.452120, 1.259926, 3.713809",\ + "0.073834, 0.193149, 0.452120, 1.259926, 3.713806",\ + "0.073834, 0.193149, 0.452120, 1.259926, 3.713804"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "380000.593750, 380000.656250, 380000.718750, 380000.906250, 380001.468750",\ + "380000.687500, 380000.750000, 380000.812500, 380001.000000, 380001.562500",\ + "380000.750000, 380000.812500, 380000.875000, 380001.062500, 380001.625000",\ + "380000.812500, 380000.875000, 380000.937500, 380001.125000, 380001.687500",\ + "380001.125000, 380001.187500, 380001.250000, 380001.437500, 380002.000000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.054415, 0.105307, 0.199650, 0.496371, 1.443909",\ + "0.054415, 0.105307, 0.199650, 0.496371, 1.443909",\ + "0.054415, 0.105307, 0.199650, 0.496371, 1.443909",\ + "0.054415, 0.105309, 0.199649, 0.496371, 1.443911",\ + "0.054417, 0.105319, 0.199643, 0.496370, 1.443919"); + } + + } /* end of arc clk_ast_tlul_i_otp_power_seq_h_o[0]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.573426, 0.645049, 0.791123, 1.237737, 2.588445",\ + "0.660803, 0.732425, 0.878500, 1.325114, 2.675822",\ + "0.741672, 0.813295, 0.959369, 1.405983, 2.756691",\ + "0.799370, 0.870993, 1.017067, 1.463682, 2.814389",\ + "1.102357, 1.173980, 1.320054, 1.766668, 3.117376"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.073832, 0.193148, 0.452121, 1.259928, 3.713817",\ + "0.073832, 0.193148, 0.452121, 1.259928, 3.713817",\ + "0.073832, 0.193148, 0.452121, 1.259928, 3.713817",\ + "0.073832, 0.193148, 0.452121, 1.259928, 3.713817",\ + "0.073832, 0.193148, 0.452121, 1.259928, 3.713817"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.260939, 0.306616, 0.380550, 0.571046, 1.131945",\ + "0.349392, 0.395070, 0.469004, 0.659499, 1.220399",\ + "0.439345, 0.485023, 0.558957, 0.749452, 1.310352",\ + "0.503750, 0.549428, 0.623362, 0.813857, 1.374757",\ + "0.840813, 0.886490, 0.960424, 1.150919, 1.711819"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.054414, 0.105305, 0.199651, 0.496372, 1.443908",\ + "0.054414, 0.105305, 0.199651, 0.496372, 1.443908",\ + "0.054414, 0.105305, 0.199651, 0.496372, 1.443908",\ + "0.054414, 0.105305, 0.199651, 0.496372, 1.443908",\ + "0.054414, 0.105305, 0.199651, 0.496372, 1.443908"); + } + + } /* end of arc clk_ast_tlul_i_otp_power_seq_h_o[0]_redg_min*/ + + timing () { + related_pin : "otp_power_seq_i[0]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.258742, 0.330399, 0.476573, 0.922786, 2.273765",\ + "0.342268, 0.413906, 0.560027, 1.006455, 2.357289",\ + "0.432373, 0.503959, 0.649927, 1.096969, 2.447388",\ + "0.604916, 0.676353, 0.821884, 1.270636, 2.619913",\ + "0.890695, 0.962107, 1.107175, 1.555746, 2.905733"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.073647, 0.193112, 0.452140, 1.260145, 3.715251",\ + "0.073746, 0.193131, 0.452140, 1.260145, 3.715251",\ + "0.074030, 0.193188, 0.452140, 1.260145, 3.715251",\ + "0.074867, 0.193375, 0.452140, 1.260145, 3.715251",\ + "0.076941, 0.194654, 0.452140, 1.260145, 3.715251"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.158895, 0.204571, 0.278502, 0.468994, 1.029901",\ + "0.236396, 0.282061, 0.355936, 0.546363, 1.107398",\ + "0.299798, 0.345438, 0.419238, 0.609722, 1.170409",\ + "0.399856, 0.445471, 0.519267, 0.710096, 1.269222",\ + "0.539370, 0.585337, 0.659872, 0.850367, 1.409363"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.054417, 0.105322, 0.199642, 0.496369, 1.443922",\ + "0.054466, 0.105609, 0.199642, 0.496369, 1.443922",\ + "0.054754, 0.105639, 0.199642, 0.496369, 1.443922",\ + "0.055765, 0.105639, 0.199849, 0.496390, 1.443922",\ + "0.058856, 0.108680, 0.201816, 0.496464, 1.443922"); + } + + } /* end of arc otp_power_seq_i[0]_otp_power_seq_h_o[0]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "otp_power_seq_i[0]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.258742, 0.330399, 0.476573, 0.922786, 2.273765",\ + "0.342268, 0.413906, 0.560027, 1.006455, 2.357289",\ + "0.432373, 0.503959, 0.649927, 1.096969, 2.447388",\ + "0.604916, 0.676353, 0.821884, 1.270636, 2.619913",\ + "0.890695, 0.962107, 1.107175, 1.555746, 2.905733"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.073647, 0.193112, 0.451380, 1.258785, 3.705802",\ + "0.073746, 0.193131, 0.451380, 1.258785, 3.705802",\ + "0.074030, 0.193188, 0.451380, 1.258785, 3.705802",\ + "0.074867, 0.193375, 0.451380, 1.258785, 3.705802",\ + "0.076941, 0.194654, 0.451380, 1.259595, 3.705802"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.158895, 0.204571, 0.278502, 0.468994, 1.029901",\ + "0.236396, 0.282061, 0.355936, 0.546363, 1.107398",\ + "0.299798, 0.345438, 0.419238, 0.609722, 1.170409",\ + "0.399856, 0.445471, 0.519267, 0.710096, 1.269222",\ + "0.539370, 0.585337, 0.659872, 0.850367, 1.409363"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.054417, 0.105076, 0.199414, 0.496314, 1.441319",\ + "0.054466, 0.105076, 0.199414, 0.496314, 1.441319",\ + "0.054754, 0.105076, 0.199414, 0.496314, 1.441319",\ + "0.055765, 0.105076, 0.199849, 0.496390, 1.441319",\ + "0.058856, 0.108680, 0.201816, 0.496464, 1.442721"); + } + + } /* end of arc otp_power_seq_i[0]_otp_power_seq_h_o[0]_una_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "380000.468750, 380000.531250, 380000.593750, 380000.781250, 380001.343750",\ + "380000.562500, 380000.625000, 380000.687500, 380000.875000, 380001.437500",\ + "380000.656250, 380000.718750, 380000.781250, 380000.968750, 380001.531250",\ + "380000.812500, 380000.875000, 380000.937500, 380001.125000, 380001.687500",\ + "380001.062500, 380001.125000, 380001.187500, 380001.375000, 380001.937500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.054414, 0.105305, 0.199651, 0.496372, 1.443908",\ + "0.054414, 0.105305, 0.199651, 0.496372, 1.443908",\ + "0.054414, 0.105305, 0.199651, 0.496372, 1.443908",\ + "0.054414, 0.105305, 0.199651, 0.496372, 1.443908",\ + "0.054414, 0.105305, 0.199651, 0.496372, 1.443908"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "380002.218750, 380002.312500, 380002.437500, 380002.906250, 380004.250000",\ + "380002.312500, 380002.406250, 380002.531250, 380003.000000, 380004.343750",\ + "380002.437500, 380002.531250, 380002.656250, 380003.125000, 380004.468750",\ + "380002.625000, 380002.718750, 380002.843750, 380003.312500, 380004.656250",\ + "380002.937500, 380003.031250, 380003.156250, 380003.625000, 380004.968750"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.073832, 0.193148, 0.452121, 1.259928, 3.713817",\ + "0.073832, 0.193148, 0.452121, 1.259928, 3.713817",\ + "0.073832, 0.193148, 0.452121, 1.259928, 3.713817",\ + "0.073832, 0.193148, 0.452121, 1.259928, 3.713817",\ + "0.073832, 0.193148, 0.452121, 1.259928, 3.713817"); + } + + } /* end of arc padmux2ast_i[4]_otp_power_seq_h_o[0]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "380000.468750, 380000.531250, 380000.593750, 380000.781250, 380001.343750",\ + "380000.562500, 380000.625000, 380000.687500, 380000.875000, 380001.437500",\ + "380000.625000, 380000.687500, 380000.750000, 380000.937500, 380001.500000",\ + "380000.781250, 380000.843750, 380000.906250, 380001.093750, 380001.656250",\ + "380001.000000, 380001.062500, 380001.125000, 380001.312500, 380001.875000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.054414, 0.105305, 0.199651, 0.496372, 1.443908",\ + "0.054414, 0.105305, 0.199651, 0.496372, 1.443908",\ + "0.054414, 0.105305, 0.199651, 0.496372, 1.443908",\ + "0.054414, 0.105305, 0.199651, 0.496372, 1.443908",\ + "0.054414, 0.105305, 0.199651, 0.496372, 1.443908"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "380002.218750, 380002.312500, 380002.437500, 380002.906250, 380004.250000",\ + "380002.312500, 380002.406250, 380002.531250, 380003.000000, 380004.343750",\ + "380002.406250, 380002.500000, 380002.625000, 380003.093750, 380004.437500",\ + "380002.593750, 380002.687500, 380002.812500, 380003.281250, 380004.625000",\ + "380002.843750, 380002.937500, 380003.062500, 380003.531250, 380004.875000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.073832, 0.193148, 0.452121, 1.259928, 3.713817",\ + "0.073832, 0.193148, 0.452121, 1.259928, 3.713817",\ + "0.073832, 0.193148, 0.452121, 1.259928, 3.713817",\ + "0.073832, 0.193148, 0.452121, 1.259928, 3.713817",\ + "0.073832, 0.193148, 0.452121, 1.259928, 3.713817"); + } + + } /* end of arc padmux2ast_i[4]_otp_power_seq_h_o[0]_inv_min*/ + +} /* end of pin otp_power_seq_h_o[0] */ +} /* end of bus otp_power_seq_h_o */ + +pin("clk_src_sys_en_i") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.002156 ; + + /* Other user defined attributes. */ + original_pin : clk_src_sys_en_i; + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.200076, 0.146984, 0.107694, 0.090457, 0.087585",\ + "0.271588, 0.219415, 0.179927, 0.162045, 0.157577",\ + "0.363033, 0.310027, 0.270334, 0.252385, 0.247965",\ + "0.507780, 0.454308, 0.413646, 0.395357, 0.391106",\ + "0.811131, 0.757315, 0.714144, 0.694969, 0.691143"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.249331, 0.166333, 0.091045, 0.049669, 0.020498",\ + "0.324602, 0.241857, 0.166855, 0.126539, 0.100040",\ + "0.429418, 0.345854, 0.270221, 0.227986, 0.196782",\ + "0.605833, 0.521783, 0.445878, 0.397956, 0.350944",\ + "0.983325, 0.898854, 0.822917, 0.761117, 0.674795"); + } + + } /* end of arc clk_ast_ext_i_clk_src_sys_en_i_stupr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.096530, -0.053812, -0.018112, 0.032751, 0.135173",\ + "-0.166367, -0.123600, -0.088245, -0.037477, 0.065076",\ + "-0.251291, -0.208679, -0.174484, -0.124115, -0.021332",\ + "-0.373429, -0.330963, -0.299719, -0.251733, -0.152256",\ + "-0.620310, -0.578080, -0.553843, -0.512151, -0.422314"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.130907, -0.055165, 0.010770, 0.102409, 0.285045",\ + "-0.205839, -0.131127, -0.064641, 0.027653, 0.211502",\ + "-0.308157, -0.233980, -0.166224, -0.072248, 0.114884",\ + "-0.470591, -0.397956, -0.329423, -0.234665, -0.046227",\ + "-0.811364, -0.742478, -0.673228, -0.578223, -0.389923"); + } + + } /* end of arc clk_ast_ext_i_clk_src_sys_en_i_hldr*/ + +} /* end of pin clk_src_sys_en_i */ +bus ( clk_src_sys_jen_i ) { + + bus_type : BUS4_type6 ; + direction : input ; + +pin("clk_src_sys_jen_i[3]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000648 ; + + /* Other user defined attributes. */ + original_pin : clk_src_sys_jen_i[3]; + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.116868, 0.046289, 0.009123, -0.023399, -0.072101",\ + "0.130035, 0.060315, 0.022495, -0.010308, -0.059037",\ + "0.171476, 0.101933, 0.064692, 0.030941, -0.021156",\ + "0.330098, 0.263569, 0.222296, 0.181197, 0.112987",\ + "0.772581, 0.713134, 0.646673, 0.587289, 0.496722"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.164832, 0.206226, 0.283518, 0.436969, 0.781571",\ + "0.176771, 0.218346, 0.296254, 0.450000, 0.794722",\ + "0.219963, 0.260510, 0.337961, 0.490822, 0.833567",\ + "0.396019, 0.435268, 0.507744, 0.654408, 0.985407",\ + "0.931350, 0.951153, 1.007354, 1.144760, 1.468564"); + } + + } /* end of arc clk_ast_ext_i_clk_src_sys_jen_i[3]_stupr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.015255, 0.029491, 0.060650, 0.100375, 0.176530",\ + "-0.028040, 0.015174, 0.046352, 0.086407, 0.163478",\ + "-0.067695, -0.029062, 0.006032, 0.048125, 0.126390",\ + "-0.170614, -0.143005, -0.113142, -0.070129, 0.016864",\ + "-0.388675, -0.412783, -0.403332, -0.363654, -0.262218"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.058687, -0.133819, -0.215174, -0.342668, -0.608913",\ + "-0.070579, -0.145649, -0.226804, -0.353700, -0.618487",\ + "-0.113780, -0.187774, -0.267897, -0.394083, -0.658063",\ + "-0.257059, -0.339271, -0.416614, -0.539608, -0.797794",\ + "-0.613549, -0.743897, -0.832843, -0.961101, -1.220625"); + } + + } /* end of arc clk_ast_ext_i_clk_src_sys_jen_i[3]_hldr*/ + +} /* end of pin clk_src_sys_jen_i[3] */ + +pin("clk_src_sys_jen_i[2]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001189 ; + + /* Other user defined attributes. */ + original_pin : clk_src_sys_jen_i[2]; + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.200076, 0.146984, 0.107694, 0.090457, 0.087585",\ + "0.210849, 0.158775, 0.118789, 0.100962, 0.097230",\ + "0.247906, 0.195949, 0.156513, 0.138649, 0.134169",\ + "0.400793, 0.347442, 0.307665, 0.289688, 0.285288",\ + "0.811131, 0.757315, 0.714144, 0.694969, 0.691143"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.249331, 0.166333, 0.091045, 0.049669, 0.020498",\ + "0.258619, 0.175944, 0.100656, 0.060195, 0.033618",\ + "0.297457, 0.214925, 0.140086, 0.100267, 0.074986",\ + "0.472698, 0.388796, 0.312903, 0.269875, 0.236728",\ + "0.983325, 0.898854, 0.822917, 0.761117, 0.674795"); + } + + } /* end of arc clk_ast_ext_i_clk_src_sys_jen_i[2]_stupr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.096530, -0.053812, -0.018112, 0.032751, 0.135173",\ + "-0.107327, -0.064625, -0.028931, 0.021950, 0.124428",\ + "-0.144374, -0.101567, -0.065911, -0.015040, 0.087453",\ + "-0.286358, -0.243809, -0.210094, -0.159889, -0.057011",\ + "-0.620310, -0.578080, -0.553843, -0.512151, -0.422314"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.130907, -0.055165, 0.010770, 0.102409, 0.285045",\ + "-0.140562, -0.065848, 0.000282, 0.091894, 0.274227",\ + "-0.179341, -0.104491, -0.038333, 0.053525, 0.236523",\ + "-0.350407, -0.276449, -0.208169, -0.113499, 0.074989",\ + "-0.811364, -0.742478, -0.673228, -0.578223, -0.389923"); + } + + } /* end of arc clk_ast_ext_i_clk_src_sys_jen_i[2]_hldr*/ + +} /* end of pin clk_src_sys_jen_i[2] */ + +pin("clk_src_sys_jen_i[1]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001189 ; + + /* Other user defined attributes. */ + original_pin : clk_src_sys_jen_i[1]; + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.200076, 0.146984, 0.107694, 0.090457, 0.087585",\ + "0.210849, 0.158775, 0.118789, 0.100962, 0.097230",\ + "0.247906, 0.195949, 0.156513, 0.138649, 0.134169",\ + "0.400793, 0.347442, 0.307665, 0.289688, 0.285288",\ + "0.811131, 0.757315, 0.714144, 0.694969, 0.691143"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.249331, 0.166333, 0.091045, 0.049669, 0.020498",\ + "0.258619, 0.175944, 0.100656, 0.060195, 0.033618",\ + "0.297457, 0.214925, 0.140086, 0.100267, 0.074986",\ + "0.472698, 0.388796, 0.312903, 0.269875, 0.236728",\ + "0.983325, 0.898854, 0.822917, 0.761117, 0.674795"); + } + + } /* end of arc clk_ast_ext_i_clk_src_sys_jen_i[1]_stupr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.096530, -0.053812, -0.018112, 0.032751, 0.135173",\ + "-0.107327, -0.064625, -0.028931, 0.021950, 0.124428",\ + "-0.144374, -0.101567, -0.065911, -0.015040, 0.087453",\ + "-0.286358, -0.243809, -0.210094, -0.159889, -0.057011",\ + "-0.620310, -0.578080, -0.553843, -0.512151, -0.422314"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.130907, -0.055165, 0.010770, 0.102409, 0.285045",\ + "-0.140562, -0.065848, 0.000282, 0.091894, 0.274227",\ + "-0.179341, -0.104491, -0.038333, 0.053525, 0.236523",\ + "-0.350407, -0.276449, -0.208169, -0.113499, 0.074989",\ + "-0.811364, -0.742478, -0.673228, -0.578223, -0.389923"); + } + + } /* end of arc clk_ast_ext_i_clk_src_sys_jen_i[1]_hldr*/ + +} /* end of pin clk_src_sys_jen_i[1] */ + +pin("clk_src_sys_jen_i[0]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000648 ; + + /* Other user defined attributes. */ + original_pin : clk_src_sys_jen_i[0]; + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.116868, 0.046289, 0.009123, -0.023399, -0.072101",\ + "0.130035, 0.060315, 0.022495, -0.010308, -0.059037",\ + "0.171476, 0.101933, 0.064692, 0.030941, -0.021156",\ + "0.330098, 0.263569, 0.222296, 0.181197, 0.112987",\ + "0.772581, 0.713134, 0.646673, 0.587289, 0.496722"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.164832, 0.206226, 0.283518, 0.436969, 0.781571",\ + "0.176771, 0.218346, 0.296254, 0.450000, 0.794722",\ + "0.219963, 0.260510, 0.337961, 0.490822, 0.833567",\ + "0.396019, 0.435268, 0.507744, 0.654408, 0.985407",\ + "0.931350, 0.951153, 1.007354, 1.144760, 1.468564"); + } + + } /* end of arc clk_ast_ext_i_clk_src_sys_jen_i[0]_stupr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.015255, 0.029491, 0.060650, 0.100375, 0.176530",\ + "-0.028040, 0.015174, 0.046352, 0.086407, 0.163478",\ + "-0.067695, -0.029062, 0.006032, 0.048125, 0.126390",\ + "-0.170614, -0.143005, -0.113142, -0.070129, 0.016864",\ + "-0.388675, -0.412783, -0.403332, -0.363654, -0.262218"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.058687, -0.133819, -0.215174, -0.342668, -0.608913",\ + "-0.070579, -0.145649, -0.226804, -0.353700, -0.618487",\ + "-0.113780, -0.187774, -0.267897, -0.394083, -0.658063",\ + "-0.257059, -0.339271, -0.416614, -0.539608, -0.797794",\ + "-0.613549, -0.743897, -0.832843, -0.961101, -1.220625"); + } + + } /* end of arc clk_ast_ext_i_clk_src_sys_jen_i[0]_hldr*/ + +} /* end of pin clk_src_sys_jen_i[0] */ +} /* end of bus clk_src_sys_jen_i */ + +pin("clk_src_sys_o") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.069236 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.009042 ; + + /* Other user defined attributes. */ + original_pin : clk_src_sys_o; + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : falling_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "1.261778, 1.293108, 1.361483, 1.578982, 2.139170",\ + "1.261778, 1.293108, 1.361483, 1.578982, 2.139170",\ + "1.261778, 1.293108, 1.361483, 1.578982, 2.139170",\ + "1.261778, 1.293108, 1.361483, 1.578982, 2.139170",\ + "1.261778, 1.293108, 1.361483, 1.578982, 2.139170"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "1.205621, 1.248652, 1.342563, 1.639882, 2.402873",\ + "1.205621, 1.248652, 1.342563, 1.639882, 2.402873",\ + "1.205621, 1.248652, 1.342563, 1.639882, 2.402873",\ + "1.205621, 1.248652, 1.342563, 1.639882, 2.402873",\ + "1.205621, 1.248652, 1.342563, 1.639882, 2.402873"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "0.321380, 0.396761, 0.561274, 1.083463, 2.426166",\ + "0.321380, 0.396761, 0.561274, 1.083463, 2.426166",\ + "0.321380, 0.396761, 0.561274, 1.083463, 2.426166",\ + "0.321380, 0.396761, 0.561274, 1.083463, 2.426166",\ + "0.321380, 0.396761, 0.561274, 1.083463, 2.426166"); + } + + } /* end of arc clk_ast_ext_i_clk_src_sys_o_fedg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_ext_i" ; + timing_type : falling_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "1.260982, 1.292312, 1.360687, 1.578186, 2.138375",\ + "1.260982, 1.292312, 1.360687, 1.578186, 2.138375",\ + "1.260982, 1.292312, 1.360687, 1.578186, 2.138375",\ + "1.260982, 1.292312, 1.360687, 1.578186, 2.138375",\ + "1.260982, 1.292312, 1.360687, 1.578186, 2.138375"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "1.203406, 1.246437, 1.340349, 1.637667, 2.400659",\ + "1.203406, 1.246437, 1.340349, 1.637667, 2.400659",\ + "1.203406, 1.246437, 1.340349, 1.637667, 2.400659",\ + "1.203406, 1.246437, 1.340349, 1.637667, 2.400659",\ + "1.203406, 1.246437, 1.340349, 1.637667, 2.400659"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "0.321380, 0.396761, 0.561274, 1.083463, 2.426166",\ + "0.321380, 0.396761, 0.561274, 1.083463, 2.426166",\ + "0.321380, 0.396761, 0.561274, 1.083463, 2.426166",\ + "0.321380, 0.396761, 0.561274, 1.083463, 2.426166",\ + "0.321380, 0.396761, 0.561274, 1.083463, 2.426166"); + } + + } /* end of arc clk_ast_ext_i_clk_src_sys_o_fedg_min*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "1.165332, 1.196662, 1.265037, 1.482536, 2.042725",\ + "1.244902, 1.276232, 1.344607, 1.562106, 2.122294",\ + "1.324816, 1.356146, 1.424521, 1.642020, 2.202208",\ + "1.454541, 1.485872, 1.554247, 1.771746, 2.331934",\ + "1.654547, 1.685877, 1.754252, 1.971751, 2.531940"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "1.060530, 1.103561, 1.197473, 1.494792, 2.257783",\ + "1.149702, 1.192733, 1.286645, 1.583964, 2.346955",\ + "1.240645, 1.283676, 1.377588, 1.674906, 2.437898",\ + "1.395684, 1.438715, 1.532626, 1.829945, 2.592937",\ + "1.648565, 1.691596, 1.785508, 2.082827, 2.845818"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "0.321380, 0.396761, 0.561274, 1.083463, 2.426166",\ + "0.321380, 0.396761, 0.561274, 1.083463, 2.426166",\ + "0.321380, 0.396761, 0.561274, 1.083463, 2.426166",\ + "0.321380, 0.396761, 0.561274, 1.083463, 2.426166",\ + "0.321380, 0.396761, 0.561274, 1.083463, 2.426166"); + } + + } /* end of arc clk_ast_ext_i_clk_src_sys_o_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_ext_i" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "1.149655, 1.180985, 1.249360, 1.466859, 2.027048",\ + "1.229405, 1.260735, 1.329110, 1.546609, 2.106797",\ + "1.304807, 1.336138, 1.404513, 1.622012, 2.182200",\ + "1.424932, 1.456262, 1.524637, 1.742136, 2.302324",\ + "1.608101, 1.639431, 1.707806, 1.925305, 2.485494"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "1.052743, 1.095775, 1.189686, 1.487005, 2.249996",\ + "1.140331, 1.183362, 1.277273, 1.574592, 2.337583",\ + "1.227129, 1.270160, 1.364072, 1.661390, 2.424382",\ + "1.376376, 1.419407, 1.513318, 1.810637, 2.573628",\ + "1.620792, 1.663824, 1.757735, 2.055053, 2.818045"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "0.321380, 0.396761, 0.561274, 1.083463, 2.426166",\ + "0.321380, 0.396761, 0.561274, 1.083463, 2.426166",\ + "0.321380, 0.396761, 0.561274, 1.083463, 2.426166",\ + "0.321380, 0.396761, 0.561274, 1.083463, 2.426166",\ + "0.321380, 0.396761, 0.561274, 1.083463, 2.426166"); + } + + } /* end of arc clk_ast_ext_i_clk_src_sys_o_una_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "970011.625000, 970011.687500, 970011.750000, 970011.937500, 970012.500000",\ + "970011.750000, 970011.812500, 970011.875000, 970012.062500, 970012.625000",\ + "970011.875000, 970011.937500, 970012.000000, 970012.187500, 970012.750000",\ + "970011.875000, 970011.937500, 970012.000000, 970012.187500, 970012.750000",\ + "970012.250000, 970012.312500, 970012.375000, 970012.562500, 970013.125000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "0.268551, 0.328271, 0.458604, 0.872597, 1.937878",\ + "0.268551, 0.328271, 0.458604, 0.872597, 1.937878",\ + "0.268551, 0.328271, 0.458604, 0.872597, 1.937878",\ + "0.268551, 0.328271, 0.458604, 0.872597, 1.937878",\ + "0.268551, 0.328271, 0.458604, 0.872597, 1.937878"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "970010.187500, 970010.250000, 970010.375000, 970010.625000, 970011.437500",\ + "970010.312500, 970010.375000, 970010.500000, 970010.750000, 970011.562500",\ + "970010.437500, 970010.500000, 970010.625000, 970010.875000, 970011.687500",\ + "970010.437500, 970010.500000, 970010.625000, 970010.875000, 970011.687500",\ + "970010.812500, 970010.875000, 970011.000000, 970011.250000, 970012.062500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "0.319241, 0.394420, 0.558621, 1.081391, 2.429504",\ + "0.319241, 0.394420, 0.558621, 1.081391, 2.429504",\ + "0.319241, 0.394420, 0.558621, 1.081391, 2.429504",\ + "0.319241, 0.394420, 0.558621, 1.081391, 2.429504",\ + "0.319241, 0.394420, 0.558621, 1.081391, 2.429504"); + } + + } /* end of arc clk_ast_tlul_i_clk_src_sys_o_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "0.692745, 0.724133, 0.792634, 1.010340, 1.570735",\ + "0.780545, 0.811933, 0.880435, 1.098141, 1.658535",\ + "0.861845, 0.893233, 0.961734, 1.179440, 1.739835",\ + "0.919998, 0.951386, 1.019887, 1.237593, 1.797988",\ + "1.228719, 1.260107, 1.328608, 1.546314, 2.106709"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "0.771503, 0.814271, 0.907608, 1.204488, 1.969053",\ + "0.859377, 0.902145, 0.995481, 1.292362, 2.056926",\ + "0.953713, 0.996481, 1.089818, 1.386698, 2.151263",\ + "1.021471, 1.064239, 1.157575, 1.454456, 2.219020",\ + "1.382169, 1.424937, 1.518274, 1.815154, 2.579719"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "0.317826, 0.392935, 0.556854, 1.079626, 2.426166",\ + "0.317826, 0.392935, 0.556854, 1.079626, 2.426166",\ + "0.317826, 0.392935, 0.556854, 1.079626, 2.426166",\ + "0.317826, 0.392935, 0.556854, 1.079626, 2.426166",\ + "0.317826, 0.392935, 0.556854, 1.079626, 2.426166"); + } + + } /* end of arc clk_ast_tlul_i_clk_src_sys_o_redg_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "970007.000000, 970007.000000, 970007.062500, 970007.312500, 970007.875000",\ + "970007.125000, 970007.125000, 970007.187500, 970007.437500, 970008.000000",\ + "970007.125000, 970007.125000, 970007.187500, 970007.437500, 970008.000000",\ + "970007.375000, 970007.375000, 970007.437500, 970007.687500, 970008.250000",\ + "970007.625000, 970007.625000, 970007.687500, 970007.937500, 970008.500000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "0.268551, 0.328271, 0.458604, 0.872597, 1.937878",\ + "0.268551, 0.328271, 0.458604, 0.872597, 1.937878",\ + "0.268551, 0.328271, 0.458604, 0.872597, 1.937878",\ + "0.268551, 0.328271, 0.458604, 0.872597, 1.937878",\ + "0.268551, 0.328271, 0.458604, 0.872597, 1.937878"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "970010.062500, 970010.125000, 970010.250000, 970010.500000, 970011.312500",\ + "970010.187500, 970010.250000, 970010.375000, 970010.625000, 970011.437500",\ + "970010.312500, 970010.375000, 970010.500000, 970010.750000, 970011.562500",\ + "970010.562500, 970010.625000, 970010.750000, 970011.000000, 970011.812500",\ + "970010.812500, 970010.875000, 970011.000000, 970011.250000, 970012.062500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "0.319241, 0.394420, 0.558621, 1.081391, 2.429504",\ + "0.319241, 0.394420, 0.558621, 1.081391, 2.429504",\ + "0.319241, 0.394420, 0.558621, 1.081391, 2.429504",\ + "0.319241, 0.394420, 0.558621, 1.081391, 2.429504",\ + "0.319241, 0.394420, 0.558621, 1.081391, 2.429504"); + } + + } /* end of arc padmux2ast_i[4]_clk_src_sys_o_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "380001.281250, 380001.312500, 380001.375000, 380001.593750, 380002.156250",\ + "380001.375000, 380001.406250, 380001.468750, 380001.687500, 380002.250000",\ + "380001.437500, 380001.468750, 380001.531250, 380001.750000, 380002.312500",\ + "380001.593750, 380001.625000, 380001.687500, 380001.906250, 380002.468750",\ + "380001.812500, 380001.843750, 380001.906250, 380002.125000, 380002.687500"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "380002.656250, 380002.718750, 380002.812500, 380003.093750, 380003.875000",\ + "380002.750000, 380002.812500, 380002.906250, 380003.187500, 380003.968750",\ + "380002.843750, 380002.906250, 380003.000000, 380003.281250, 380004.062500",\ + "380003.031250, 380003.093750, 380003.187500, 380003.468750, 380004.250000",\ + "380003.281250, 380003.343750, 380003.437500, 380003.718750, 380004.500000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "0.317826, 0.392935, 0.556854, 1.079626, 2.426166",\ + "0.317826, 0.392935, 0.556854, 1.079626, 2.426166",\ + "0.317826, 0.392935, 0.556854, 1.079626, 2.426166",\ + "0.317826, 0.392935, 0.556854, 1.079626, 2.426166",\ + "0.317826, 0.392935, 0.556854, 1.079626, 2.426166"); + } + + } /* end of arc padmux2ast_i[4]_clk_src_sys_o_una_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "970008.250000, 970008.250000, 970008.375000, 970008.687500, 970009.437500",\ + "970008.375000, 970008.375000, 970008.500000, 970008.812500, 970009.562500",\ + "970008.375000, 970008.375000, 970008.500000, 970008.812500, 970009.562500",\ + "970008.625000, 970008.625000, 970008.750000, 970009.062500, 970009.812500",\ + "970008.875000, 970008.875000, 970009.000000, 970009.312500, 970010.062500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "0.319241, 0.394420, 0.558621, 1.081391, 2.429504",\ + "0.319241, 0.394420, 0.558621, 1.081391, 2.429504",\ + "0.319241, 0.394420, 0.558621, 1.081391, 2.429504",\ + "0.319241, 0.394420, 0.558621, 1.081391, 2.429504",\ + "0.319241, 0.394420, 0.558621, 1.081391, 2.429504"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "970011.500000, 970011.562500, 970011.625000, 970011.812500, 970012.375000",\ + "970011.625000, 970011.687500, 970011.750000, 970011.937500, 970012.500000",\ + "970011.750000, 970011.812500, 970011.875000, 970012.062500, 970012.625000",\ + "970012.000000, 970012.062500, 970012.125000, 970012.312500, 970012.875000",\ + "970012.250000, 970012.312500, 970012.375000, 970012.562500, 970013.125000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "0.268551, 0.328271, 0.458604, 0.872597, 1.937878",\ + "0.268551, 0.328271, 0.458604, 0.872597, 1.937878",\ + "0.268551, 0.328271, 0.458604, 0.872597, 1.937878",\ + "0.268551, 0.328271, 0.458604, 0.872597, 1.937878",\ + "0.268551, 0.328271, 0.458604, 0.872597, 1.937878"); + } + + } /* end of arc padmux2ast_i[4]_clk_src_sys_o_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "380000.531250, 380000.562500, 380000.656250, 380000.937500, 380001.718750",\ + "380000.625000, 380000.656250, 380000.750000, 380001.031250, 380001.812500",\ + "380000.687500, 380000.718750, 380000.812500, 380001.093750, 380001.875000",\ + "380000.843750, 380000.875000, 380000.968750, 380001.250000, 380002.031250",\ + "380001.062500, 380001.093750, 380001.187500, 380001.468750, 380002.250000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "0.317826, 0.392935, 0.556854, 1.079626, 2.426166",\ + "0.317826, 0.392935, 0.556854, 1.079626, 2.426166",\ + "0.317826, 0.392935, 0.556854, 1.079626, 2.426166",\ + "0.317826, 0.392935, 0.556854, 1.079626, 2.426166",\ + "0.317826, 0.392935, 0.556854, 1.079626, 2.426166"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "380001.875000, 380001.906250, 380001.968750, 380002.187500, 380002.750000",\ + "380001.968750, 380002.000000, 380002.062500, 380002.281250, 380002.843750",\ + "380002.062500, 380002.093750, 380002.156250, 380002.375000, 380002.937500",\ + "380002.250000, 380002.281250, 380002.343750, 380002.562500, 380003.125000",\ + "380002.500000, 380002.531250, 380002.593750, 380002.812500, 380003.375000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571"); + } + + } /* end of arc padmux2ast_i[4]_clk_src_sys_o_inv_min*/ + + timing () { + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "590009.875000, 590009.937500, 590010.000000, 590010.187500, 590010.750000",\ + "590010.000000, 590010.062500, 590010.125000, 590010.312500, 590010.875000",\ + "590010.000000, 590010.062500, 590010.125000, 590010.312500, 590010.875000",\ + "590010.125000, 590010.187500, 590010.250000, 590010.437500, 590011.000000",\ + "590010.375000, 590010.437500, 590010.500000, 590010.687500, 590011.250000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "0.268551, 0.328271, 0.458604, 0.872597, 1.937878",\ + "0.268551, 0.328271, 0.458604, 0.872597, 1.937878",\ + "0.268551, 0.328271, 0.458604, 0.872597, 1.937878",\ + "0.268551, 0.328271, 0.458604, 0.872597, 1.937878",\ + "0.268551, 0.328271, 0.458604, 0.872597, 1.937878"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "590008.000000, 590008.000000, 590008.125000, 590008.437500, 590009.187500",\ + "590008.125000, 590008.125000, 590008.250000, 590008.562500, 590009.312500",\ + "590008.250000, 590008.250000, 590008.375000, 590008.687500, 590009.437500",\ + "590008.375000, 590008.375000, 590008.500000, 590008.812500, 590009.562500",\ + "590008.750000, 590008.750000, 590008.875000, 590009.187500, 590009.937500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "0.319235, 0.394420, 0.558621, 1.081391, 2.429503",\ + "0.319235, 0.394420, 0.558621, 1.081391, 2.429503",\ + "0.319235, 0.394420, 0.558621, 1.081391, 2.429503",\ + "0.319235, 0.394420, 0.558621, 1.081391, 2.429503",\ + "0.319235, 0.394420, 0.558621, 1.081391, 2.429503"); + } + + } /* end of arc padmux2ast_i[5]_clk_src_sys_o_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "590008.625000, 590008.625000, 590008.687500, 590008.937500, 590009.500000",\ + "590008.625000, 590008.625000, 590008.687500, 590008.937500, 590009.500000",\ + "590008.750000, 590008.750000, 590008.812500, 590009.062500, 590009.625000",\ + "590008.875000, 590008.875000, 590008.937500, 590009.187500, 590009.750000",\ + "590009.125000, 590009.125000, 590009.187500, 590009.437500, 590010.000000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "590006.875000, 590006.937500, 590007.000000, 590007.312500, 590008.062500",\ + "590007.000000, 590007.062500, 590007.125000, 590007.437500, 590008.187500",\ + "590007.125000, 590007.187500, 590007.250000, 590007.562500, 590008.312500",\ + "590007.250000, 590007.312500, 590007.375000, 590007.687500, 590008.437500",\ + "590007.500000, 590007.562500, 590007.625000, 590007.937500, 590008.687500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "0.319235, 0.394241, 0.557935, 1.080416, 2.426166",\ + "0.319235, 0.394241, 0.557935, 1.080416, 2.426166",\ + "0.319235, 0.394241, 0.557935, 1.080416, 2.426166",\ + "0.319235, 0.394241, 0.557935, 1.080416, 2.426166",\ + "0.319235, 0.394241, 0.557935, 1.080416, 2.426166"); + } + + } /* end of arc padmux2ast_i[5]_clk_src_sys_o_una_min*/ + + timing () { + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "590008.437500, 590008.500000, 590008.625000, 590008.875000, 590009.687500",\ + "590008.562500, 590008.625000, 590008.750000, 590009.000000, 590009.812500",\ + "590008.562500, 590008.625000, 590008.750000, 590009.000000, 590009.812500",\ + "590008.687500, 590008.750000, 590008.875000, 590009.125000, 590009.937500",\ + "590008.937500, 590009.000000, 590009.125000, 590009.375000, 590010.187500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "0.319235, 0.394420, 0.558621, 1.081391, 2.429503",\ + "0.319235, 0.394420, 0.558621, 1.081391, 2.429503",\ + "0.319235, 0.394420, 0.558621, 1.081391, 2.429503",\ + "0.319235, 0.394420, 0.558621, 1.081391, 2.429503",\ + "0.319235, 0.394420, 0.558621, 1.081391, 2.429503"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "590006.750000, 590006.750000, 590006.812500, 590007.062500, 590007.625000",\ + "590006.875000, 590006.875000, 590006.937500, 590007.187500, 590007.750000",\ + "590007.000000, 590007.000000, 590007.062500, 590007.312500, 590007.875000",\ + "590007.125000, 590007.125000, 590007.187500, 590007.437500, 590008.000000",\ + "590007.500000, 590007.500000, 590007.562500, 590007.812500, 590008.375000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "0.268551, 0.328271, 0.458604, 0.872597, 1.937878",\ + "0.268551, 0.328271, 0.458604, 0.872597, 1.937878",\ + "0.268551, 0.328271, 0.458604, 0.872597, 1.937878",\ + "0.268551, 0.328271, 0.458604, 0.872597, 1.937878",\ + "0.268551, 0.328271, 0.458604, 0.872597, 1.937878"); + } + + } /* end of arc padmux2ast_i[5]_clk_src_sys_o_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "590008.437500, 590008.500000, 590008.625000, 590008.875000, 590009.687500",\ + "590008.437500, 590008.500000, 590008.625000, 590008.875000, 590009.687500",\ + "590008.562500, 590008.625000, 590008.750000, 590009.000000, 590009.812500",\ + "590008.687500, 590008.750000, 590008.875000, 590009.125000, 590009.937500",\ + "590008.937500, 590009.000000, 590009.125000, 590009.375000, 590010.187500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "0.319235, 0.394241, 0.557935, 1.080416, 2.426166",\ + "0.319235, 0.394241, 0.557935, 1.080416, 2.426166",\ + "0.319235, 0.394241, 0.557935, 1.080416, 2.426166",\ + "0.319235, 0.394241, 0.557935, 1.080416, 2.426166",\ + "0.319235, 0.394241, 0.557935, 1.080416, 2.426166"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "590006.750000, 590006.750000, 590006.812500, 590007.062500, 590007.625000",\ + "590006.875000, 590006.875000, 590006.937500, 590007.187500, 590007.750000",\ + "590007.000000, 590007.000000, 590007.062500, 590007.312500, 590007.875000",\ + "590007.125000, 590007.125000, 590007.187500, 590007.437500, 590008.000000",\ + "590007.375000, 590007.375000, 590007.437500, 590007.687500, 590008.250000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571"); + } + + } /* end of arc padmux2ast_i[5]_clk_src_sys_o_inv_min*/ + +} /* end of pin clk_src_sys_o */ + +pin("clk_src_sys_val_o") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.090214 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002720 ; + + /* Other user defined attributes. */ + original_pin : clk_src_sys_val_o; + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "0.393375, 0.428628, 0.510890, 0.784879, 1.641015",\ + "0.480773, 0.516025, 0.598287, 0.872277, 1.728413",\ + "0.561620, 0.596872, 0.679134, 0.953123, 1.809259",\ + "0.699752, 0.735005, 0.817267, 1.091256, 1.947392",\ + "0.940296, 0.975559, 1.057603, 1.330256, 2.187617"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "0.090897, 0.157759, 0.313710, 0.838441, 2.477149",\ + "0.090897, 0.157759, 0.313710, 0.838441, 2.477149",\ + "0.090897, 0.157759, 0.313710, 0.838441, 2.477149",\ + "0.090897, 0.157759, 0.313710, 0.838441, 2.477149",\ + "0.090897, 0.157759, 0.313710, 0.838442, 2.477149"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "0.432455, 0.458343, 0.517176, 0.707295, 1.304954",\ + "0.519853, 0.545740, 0.604574, 0.794693, 1.392351",\ + "0.600665, 0.626553, 0.685387, 0.875506, 1.473164",\ + "0.738675, 0.764563, 0.823397, 1.013516, 1.611174",\ + "0.958865, 0.984753, 1.043586, 1.233705, 1.831364"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "0.074157, 0.115650, 0.215819, 0.564523, 1.651598",\ + "0.074157, 0.115650, 0.215819, 0.564523, 1.651598",\ + "0.074157, 0.115650, 0.215819, 0.564523, 1.651598",\ + "0.074157, 0.115650, 0.215819, 0.564523, 1.651598",\ + "0.074157, 0.115650, 0.215819, 0.564523, 1.651598"); + } + + } /* end of arc clk_ast_ext_i_clk_src_sys_val_o_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "0.266769, 0.302004, 0.384050, 0.657034, 1.516706",\ + "0.354958, 0.390193, 0.472239, 0.745222, 1.604895",\ + "0.442595, 0.477830, 0.559876, 0.832859, 1.692532",\ + "0.590863, 0.626097, 0.708144, 0.981127, 1.840799",\ + "0.826177, 0.861412, 0.943458, 1.216442, 2.076114"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "0.090757, 0.157284, 0.313129, 0.831079, 2.456895",\ + "0.090757, 0.157284, 0.313129, 0.831079, 2.456895",\ + "0.090757, 0.157284, 0.313129, 0.831079, 2.456895",\ + "0.090757, 0.157284, 0.313129, 0.831079, 2.456895",\ + "0.090757, 0.157284, 0.313129, 0.831079, 2.456895"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "0.303512, 0.329439, 0.388317, 0.578409, 1.176194",\ + "0.391701, 0.417628, 0.476506, 0.666598, 1.264383",\ + "0.479338, 0.505265, 0.564143, 0.754235, 1.352020",\ + "0.627605, 0.653533, 0.712411, 0.902503, 1.500287",\ + "0.853156, 0.879043, 0.937890, 1.128062, 1.724915"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "0.072021, 0.113734, 0.214400, 0.561002, 1.650535",\ + "0.072021, 0.113734, 0.214400, 0.561002, 1.650535",\ + "0.072021, 0.113734, 0.214400, 0.561002, 1.650535",\ + "0.072021, 0.113734, 0.214400, 0.561002, 1.650535",\ + "0.072021, 0.113734, 0.214400, 0.561002, 1.650535"); + } + + } /* end of arc clk_ast_ext_i_clk_src_sys_val_o_redg_min*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.091331, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.274613, 0.222555, 0.182645, 0.164813, 0.160978",\ + "0.311604, 0.259547, 0.219637, 0.201805, 0.197970",\ + "0.350063, 0.298005, 0.258095, 0.240263, 0.236428",\ + "0.426515, 0.374464, 0.334588, 0.316753, 0.312873",\ + "0.811131, 0.757315, 0.714144, 0.694969, 0.691143"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.074152, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.319192, 0.236521, 0.161241, 0.120791, 0.094238",\ + "0.350005, 0.267334, 0.192054, 0.151604, 0.125051",\ + "0.404336, 0.321669, 0.246404, 0.205976, 0.179465",\ + "0.493898, 0.411245, 0.336023, 0.295656, 0.269270",\ + "0.983325, 0.898854, 0.822917, 0.761117, 0.683170"); + } + + } /* end of arc clk_ast_ext_i_clk_src_sys_val_o_stupr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.090757, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.098980, -0.056266, -0.020568, 0.030300, 0.132735",\ + "-0.130504, -0.087736, -0.052066, -0.001191, 0.101296",\ + "-0.166367, -0.123600, -0.088245, -0.037477, 0.065076",\ + "-0.251291, -0.208679, -0.174484, -0.124115, -0.021332",\ + "-0.620310, -0.578080, -0.553843, -0.512151, -0.422314"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.072021, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.133098, -0.057590, 0.008390, 0.100023, 0.282590",\ + "-0.157464, -0.082691, -0.016549, 0.075171, 0.257794",\ + "-0.205839, -0.131127, -0.064641, 0.027653, 0.211502",\ + "-0.308157, -0.233980, -0.166224, -0.072248, 0.114884",\ + "-0.787774, -0.712937, -0.646782, -0.554947, -0.372013"); + } + + } /* end of arc clk_ast_ext_i_clk_src_sys_val_o_hldr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : recovery_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.091331, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.404032, 0.352558, 0.318430, 0.316711, 0.351792",\ + "0.438477, 0.387003, 0.352875, 0.351156, 0.386237",\ + "0.480582, 0.429108, 0.394981, 0.393261, 0.428342",\ + "0.577835, 0.526352, 0.492184, 0.490390, 0.525306",\ + "1.061708, 1.010135, 0.975535, 0.972941, 1.006095"); + } + + } /* end of arc clk_ast_ext_i_clk_src_sys_val_o_recrr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : removal_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.090757, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.316209, -0.269420, -0.233349, -0.183696, -0.085143",\ + "-0.350428, -0.303639, -0.267567, -0.217915, -0.119361",\ + "-0.392769, -0.345980, -0.309909, -0.260256, -0.161702",\ + "-0.490012, -0.443234, -0.407200, -0.357545, -0.258944",\ + "-0.973610, -0.926934, -0.891298, -0.841646, -0.742588"); + } + + } /* end of arc clk_ast_ext_i_clk_src_sys_val_o_remrr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "970010.375000, 970010.437500, 970010.500000, 970010.750000, 970011.625000",\ + "970010.500000, 970010.562500, 970010.625000, 970010.875000, 970011.750000",\ + "970010.625000, 970010.687500, 970010.750000, 970011.000000, 970011.875000",\ + "970010.625000, 970010.687500, 970010.750000, 970011.000000, 970011.875000",\ + "970011.000000, 970011.062500, 970011.125000, 970011.375000, 970012.250000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "0.091331, 0.157635, 0.313856, 0.840284, 2.469430",\ + "0.091331, 0.157635, 0.313856, 0.840284, 2.469430",\ + "0.091331, 0.157635, 0.313856, 0.840284, 2.469430",\ + "0.091331, 0.157635, 0.313856, 0.840284, 2.469430",\ + "0.091331, 0.157635, 0.313856, 0.840284, 2.469430"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "970010.375000, 970010.375000, 970010.437500, 970010.625000, 970011.250000",\ + "970010.500000, 970010.500000, 970010.562500, 970010.750000, 970011.375000",\ + "970010.625000, 970010.625000, 970010.687500, 970010.875000, 970011.500000",\ + "970010.625000, 970010.625000, 970010.687500, 970010.875000, 970011.500000",\ + "970011.000000, 970011.000000, 970011.062500, 970011.250000, 970011.875000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "0.074152, 0.115602, 0.215213, 0.563923, 1.651340",\ + "0.074152, 0.115602, 0.215213, 0.563923, 1.651340",\ + "0.074152, 0.115602, 0.215213, 0.563923, 1.651340",\ + "0.074152, 0.115602, 0.215213, 0.563923, 1.651340",\ + "0.074152, 0.115602, 0.215213, 0.563923, 1.651340"); + } + + } /* end of arc clk_ast_tlul_i_clk_src_sys_val_o_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "0.735494, 0.770750, 0.853002, 1.126914, 1.983374",\ + "0.823294, 0.858551, 0.940802, 1.214714, 2.071174",\ + "0.904594, 0.939850, 1.022102, 1.296013, 2.152474",\ + "0.962747, 0.998003, 1.080255, 1.354167, 2.210627",\ + "1.271467, 1.306724, 1.388975, 1.662887, 2.519347"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "0.090757, 0.157284, 0.313155, 0.830725, 2.460156",\ + "0.090757, 0.157284, 0.313155, 0.830725, 2.460156",\ + "0.090757, 0.157284, 0.313155, 0.830725, 2.460156",\ + "0.090757, 0.157284, 0.313155, 0.830725, 2.460156",\ + "0.090757, 0.157284, 0.313155, 0.830725, 2.460156"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "0.709749, 0.735637, 0.794488, 0.984673, 1.581583",\ + "0.797549, 0.823438, 0.882288, 1.072473, 1.669383",\ + "0.878849, 0.904737, 0.963588, 1.153773, 1.750682",\ + "0.937002, 0.962891, 1.021741, 1.211926, 1.808836",\ + "1.245723, 1.271611, 1.330462, 1.520647, 2.117556"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "0.072027, 0.113736, 0.214396, 0.560990, 1.651196",\ + "0.072027, 0.113736, 0.214396, 0.560990, 1.651196",\ + "0.072027, 0.113736, 0.214396, 0.560990, 1.651196",\ + "0.072027, 0.113736, 0.214396, 0.560990, 1.651196",\ + "0.072027, 0.113736, 0.214396, 0.560990, 1.651196"); + } + + } /* end of arc clk_ast_tlul_i_clk_src_sys_val_o_redg_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "970007.125000, 970007.187500, 970007.250000, 970007.562500, 970008.375000",\ + "970007.250000, 970007.312500, 970007.375000, 970007.687500, 970008.500000",\ + "970007.250000, 970007.312500, 970007.375000, 970007.687500, 970008.500000",\ + "970007.500000, 970007.562500, 970007.625000, 970007.937500, 970008.750000",\ + "970007.750000, 970007.812500, 970007.875000, 970008.187500, 970009.000000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "0.091331, 0.157635, 0.313856, 0.840284, 2.469430",\ + "0.091331, 0.157635, 0.313856, 0.840284, 2.469430",\ + "0.091331, 0.157635, 0.313856, 0.840284, 2.469430",\ + "0.091331, 0.157635, 0.313856, 0.840284, 2.469430",\ + "0.091331, 0.157635, 0.313856, 0.840284, 2.469430"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "970010.250000, 970010.250000, 970010.312500, 970010.500000, 970011.125000",\ + "970010.375000, 970010.375000, 970010.437500, 970010.625000, 970011.250000",\ + "970010.500000, 970010.500000, 970010.562500, 970010.750000, 970011.375000",\ + "970010.750000, 970010.750000, 970010.812500, 970011.000000, 970011.625000",\ + "970011.000000, 970011.000000, 970011.062500, 970011.250000, 970011.875000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "0.074152, 0.115602, 0.215213, 0.563923, 1.651340",\ + "0.074152, 0.115602, 0.215213, 0.563923, 1.651340",\ + "0.074152, 0.115602, 0.215213, 0.563923, 1.651340",\ + "0.074152, 0.115602, 0.215213, 0.563923, 1.651340",\ + "0.074152, 0.115602, 0.215213, 0.563923, 1.651340"); + } + + } /* end of arc padmux2ast_i[4]_clk_src_sys_val_o_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "380000.500000, 380000.531250, 380000.593750, 380000.875000, 380001.750000",\ + "380000.593750, 380000.625000, 380000.687500, 380000.968750, 380001.843750",\ + "380000.656250, 380000.687500, 380000.750000, 380001.031250, 380001.906250",\ + "380000.812500, 380000.843750, 380000.906250, 380001.187500, 380002.062500",\ + "380001.031250, 380001.062500, 380001.125000, 380001.406250, 380002.281250"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "0.090757, 0.157284, 0.313155, 0.830725, 2.460156",\ + "0.090757, 0.157284, 0.313155, 0.830725, 2.460156",\ + "0.090757, 0.157284, 0.313155, 0.830725, 2.460156",\ + "0.090757, 0.157284, 0.313155, 0.830725, 2.460156",\ + "0.090757, 0.157284, 0.313155, 0.830725, 2.460156"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "380001.906250, 380001.937500, 380002.000000, 380002.187500, 380002.781250",\ + "380002.000000, 380002.031250, 380002.093750, 380002.281250, 380002.875000",\ + "380002.093750, 380002.125000, 380002.187500, 380002.375000, 380002.968750",\ + "380002.281250, 380002.312500, 380002.375000, 380002.562500, 380003.156250",\ + "380002.531250, 380002.562500, 380002.625000, 380002.812500, 380003.406250"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "0.072027, 0.113736, 0.214396, 0.560990, 1.651196",\ + "0.072027, 0.113736, 0.214396, 0.560990, 1.651196",\ + "0.072027, 0.113736, 0.214396, 0.560990, 1.651196",\ + "0.072027, 0.113736, 0.214396, 0.560990, 1.651196",\ + "0.072027, 0.113736, 0.214396, 0.560990, 1.651196"); + } + + } /* end of arc padmux2ast_i[4]_clk_src_sys_val_o_una_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "970007.187500, 970007.187500, 970007.250000, 970007.437500, 970008.062500",\ + "970007.312500, 970007.312500, 970007.375000, 970007.562500, 970008.187500",\ + "970007.312500, 970007.312500, 970007.375000, 970007.562500, 970008.187500",\ + "970007.562500, 970007.562500, 970007.625000, 970007.812500, 970008.437500",\ + "970007.812500, 970007.812500, 970007.875000, 970008.062500, 970008.687500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "0.074152, 0.115602, 0.215213, 0.563923, 1.651340",\ + "0.074152, 0.115602, 0.215213, 0.563923, 1.651340",\ + "0.074152, 0.115602, 0.215213, 0.563923, 1.651340",\ + "0.074152, 0.115602, 0.215213, 0.563923, 1.651340",\ + "0.074152, 0.115602, 0.215213, 0.563923, 1.651340"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "970010.250000, 970010.312500, 970010.375000, 970010.625000, 970011.500000",\ + "970010.375000, 970010.437500, 970010.500000, 970010.750000, 970011.625000",\ + "970010.500000, 970010.562500, 970010.625000, 970010.875000, 970011.750000",\ + "970010.750000, 970010.812500, 970010.875000, 970011.125000, 970012.000000",\ + "970011.000000, 970011.062500, 970011.125000, 970011.375000, 970012.250000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "0.091331, 0.157635, 0.313856, 0.840284, 2.469430",\ + "0.091331, 0.157635, 0.313856, 0.840284, 2.469430",\ + "0.091331, 0.157635, 0.313856, 0.840284, 2.469430",\ + "0.091331, 0.157635, 0.313856, 0.840284, 2.469430",\ + "0.091331, 0.157635, 0.313856, 0.840284, 2.469430"); + } + + } /* end of arc padmux2ast_i[4]_clk_src_sys_val_o_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "380000.531250, 380000.562500, 380000.625000, 380000.812500, 380001.406250",\ + "380000.625000, 380000.656250, 380000.718750, 380000.906250, 380001.500000",\ + "380000.687500, 380000.718750, 380000.781250, 380000.968750, 380001.562500",\ + "380000.843750, 380000.875000, 380000.937500, 380001.125000, 380001.718750",\ + "380001.062500, 380001.093750, 380001.156250, 380001.343750, 380001.937500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "0.072027, 0.113736, 0.214396, 0.560990, 1.651196",\ + "0.072027, 0.113736, 0.214396, 0.560990, 1.651196",\ + "0.072027, 0.113736, 0.214396, 0.560990, 1.651196",\ + "0.072027, 0.113736, 0.214396, 0.560990, 1.651196",\ + "0.072027, 0.113736, 0.214396, 0.560990, 1.651196"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "380001.937500, 380001.968750, 380002.062500, 380002.343750, 380003.187500",\ + "380002.031250, 380002.062500, 380002.156250, 380002.437500, 380003.281250",\ + "380002.125000, 380002.156250, 380002.250000, 380002.531250, 380003.375000",\ + "380002.312500, 380002.343750, 380002.437500, 380002.718750, 380003.562500",\ + "380002.562500, 380002.593750, 380002.687500, 380002.968750, 380003.812500"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "0.090757, 0.157284, 0.313155, 0.830725, 2.460156",\ + "0.090757, 0.157284, 0.313155, 0.830725, 2.460156",\ + "0.090757, 0.157284, 0.313155, 0.830725, 2.460156",\ + "0.090757, 0.157284, 0.313155, 0.830725, 2.460156",\ + "0.090757, 0.157284, 0.313155, 0.830725, 2.460156"); + } + + } /* end of arc padmux2ast_i[4]_clk_src_sys_val_o_inv_min*/ + + timing () { + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "590008.625000, 590008.687500, 590008.750000, 590009.000000, 590009.875000",\ + "590008.750000, 590008.812500, 590008.875000, 590009.125000, 590010.000000",\ + "590008.750000, 590008.812500, 590008.875000, 590009.125000, 590010.000000",\ + "590008.875000, 590008.937500, 590009.000000, 590009.250000, 590010.125000",\ + "590009.125000, 590009.187500, 590009.250000, 590009.500000, 590010.375000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "0.091331, 0.157635, 0.313861, 0.840307, 2.469430",\ + "0.091331, 0.157635, 0.313861, 0.840307, 2.469430",\ + "0.091331, 0.157635, 0.313861, 0.840307, 2.469430",\ + "0.091331, 0.157635, 0.313861, 0.840307, 2.469430",\ + "0.091331, 0.157635, 0.313861, 0.840307, 2.469430"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "590006.937500, 590006.937500, 590007.000000, 590007.187500, 590007.812500",\ + "590007.062500, 590007.062500, 590007.125000, 590007.312500, 590007.937500",\ + "590007.187500, 590007.187500, 590007.250000, 590007.437500, 590008.062500",\ + "590007.312500, 590007.312500, 590007.375000, 590007.562500, 590008.187500",\ + "590007.687500, 590007.687500, 590007.750000, 590007.937500, 590008.562500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "0.074152, 0.115602, 0.215213, 0.563930, 1.651340",\ + "0.074152, 0.115602, 0.215213, 0.563930, 1.651340",\ + "0.074152, 0.115602, 0.215213, 0.563930, 1.651340",\ + "0.074152, 0.115602, 0.215213, 0.563930, 1.651340",\ + "0.074152, 0.115602, 0.215213, 0.563930, 1.651340"); + } + + } /* end of arc padmux2ast_i[5]_clk_src_sys_val_o_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "590008.437500, 590008.437500, 590008.562500, 590008.812500, 590009.687500",\ + "590008.437500, 590008.437500, 590008.562500, 590008.812500, 590009.687500",\ + "590008.562500, 590008.562500, 590008.687500, 590008.937500, 590009.812500",\ + "590008.687500, 590008.687500, 590008.812500, 590009.062500, 590009.937500",\ + "590008.937500, 590008.937500, 590009.062500, 590009.312500, 590010.187500"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "0.090757, 0.157286, 0.312487, 0.829843, 2.465812",\ + "0.090757, 0.157286, 0.312487, 0.829843, 2.465812",\ + "0.090757, 0.157286, 0.312487, 0.829843, 2.465812",\ + "0.090757, 0.157286, 0.312487, 0.829843, 2.465812",\ + "0.090757, 0.157286, 0.312487, 0.829843, 2.465812"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "590006.750000, 590006.812500, 590006.875000, 590007.062500, 590007.625000",\ + "590006.875000, 590006.937500, 590007.000000, 590007.187500, 590007.750000",\ + "590007.000000, 590007.062500, 590007.125000, 590007.312500, 590007.875000",\ + "590007.125000, 590007.187500, 590007.250000, 590007.437500, 590008.000000",\ + "590007.375000, 590007.437500, 590007.500000, 590007.687500, 590008.250000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "0.072111, 0.113800, 0.214396, 0.559011, 1.650020",\ + "0.072111, 0.113800, 0.214396, 0.559011, 1.650020",\ + "0.072111, 0.113800, 0.214396, 0.559011, 1.650020",\ + "0.072111, 0.113800, 0.214396, 0.559011, 1.650020",\ + "0.072111, 0.113800, 0.214396, 0.559011, 1.650020"); + } + + } /* end of arc padmux2ast_i[5]_clk_src_sys_val_o_una_min*/ + + timing () { + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "590008.625000, 590008.625000, 590008.687500, 590008.875000, 590009.500000",\ + "590008.750000, 590008.750000, 590008.812500, 590009.000000, 590009.625000",\ + "590008.750000, 590008.750000, 590008.812500, 590009.000000, 590009.625000",\ + "590008.875000, 590008.875000, 590008.937500, 590009.125000, 590009.750000",\ + "590009.125000, 590009.125000, 590009.187500, 590009.375000, 590010.000000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "0.074152, 0.115602, 0.215213, 0.563930, 1.651340",\ + "0.074152, 0.115602, 0.215213, 0.563930, 1.651340",\ + "0.074152, 0.115602, 0.215213, 0.563930, 1.651340",\ + "0.074152, 0.115602, 0.215213, 0.563930, 1.651340",\ + "0.074152, 0.115602, 0.215213, 0.563930, 1.651340"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "590006.875000, 590006.937500, 590007.000000, 590007.312500, 590008.125000",\ + "590007.000000, 590007.062500, 590007.125000, 590007.437500, 590008.250000",\ + "590007.125000, 590007.187500, 590007.250000, 590007.562500, 590008.375000",\ + "590007.250000, 590007.312500, 590007.375000, 590007.687500, 590008.500000",\ + "590007.625000, 590007.687500, 590007.750000, 590008.062500, 590008.875000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "0.091331, 0.157635, 0.313861, 0.840307, 2.469430",\ + "0.091331, 0.157635, 0.313861, 0.840307, 2.469430",\ + "0.091331, 0.157635, 0.313861, 0.840307, 2.469430",\ + "0.091331, 0.157635, 0.313861, 0.840307, 2.469430",\ + "0.091331, 0.157635, 0.313861, 0.840307, 2.469430"); + } + + } /* end of arc padmux2ast_i[5]_clk_src_sys_val_o_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "590008.625000, 590008.625000, 590008.687500, 590008.875000, 590009.500000",\ + "590008.625000, 590008.625000, 590008.687500, 590008.875000, 590009.500000",\ + "590008.750000, 590008.750000, 590008.812500, 590009.000000, 590009.625000",\ + "590008.875000, 590008.875000, 590008.937500, 590009.125000, 590009.750000",\ + "590009.125000, 590009.125000, 590009.187500, 590009.375000, 590010.000000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "0.072111, 0.113800, 0.214396, 0.559011, 1.650020",\ + "0.072111, 0.113800, 0.214396, 0.559011, 1.650020",\ + "0.072111, 0.113800, 0.214396, 0.559011, 1.650020",\ + "0.072111, 0.113800, 0.214396, 0.559011, 1.650020",\ + "0.072111, 0.113800, 0.214396, 0.559011, 1.650020"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "590006.875000, 590006.937500, 590007.000000, 590007.312500, 590008.125000",\ + "590007.000000, 590007.062500, 590007.125000, 590007.437500, 590008.250000",\ + "590007.125000, 590007.187500, 590007.250000, 590007.562500, 590008.375000",\ + "590007.250000, 590007.312500, 590007.375000, 590007.687500, 590008.500000",\ + "590007.500000, 590007.562500, 590007.625000, 590007.937500, 590008.750000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "0.090757, 0.157286, 0.312487, 0.829843, 2.465812",\ + "0.090757, 0.157286, 0.312487, 0.829843, 2.465812",\ + "0.090757, 0.157286, 0.312487, 0.829843, 2.465812",\ + "0.090757, 0.157286, 0.312487, 0.829843, 2.465812",\ + "0.090757, 0.157286, 0.312487, 0.829843, 2.465812"); + } + + } /* end of arc padmux2ast_i[5]_clk_src_sys_val_o_inv_min*/ + +} /* end of pin clk_src_sys_val_o */ + +pin("clk_src_aon_o") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 4.852190 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.018084 ; + + /* Other user defined attributes. */ + original_pin : clk_src_aon_o; + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "0.829798, 0.861406, 1.030187, 1.471304, 2.111221",\ + "0.918104, 0.949713, 1.118494, 1.559610, 2.199528",\ + "1.006314, 1.037922, 1.206704, 1.647820, 2.287737",\ + "1.155623, 1.187232, 1.356013, 1.797129, 2.437046",\ + "1.394957, 1.426565, 1.595346, 2.036462, 2.676380"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "0.018689, 0.076907, 0.397582, 1.240182, 2.462523",\ + "0.018689, 0.076907, 0.397582, 1.240182, 2.462523",\ + "0.018689, 0.076907, 0.397582, 1.240182, 2.462523",\ + "0.018689, 0.076907, 0.397582, 1.240182, 2.462523",\ + "0.018689, 0.076907, 0.397582, 1.240182, 2.462523"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "0.883488, 0.912350, 1.061245, 1.451119, 2.016701",\ + "0.970887, 0.999749, 1.148644, 1.538518, 2.104100",\ + "1.051701, 1.080563, 1.229459, 1.619333, 2.184914",\ + "1.189711, 1.218573, 1.367469, 1.757343, 2.322925",\ + "1.410200, 1.439062, 1.587957, 1.977831, 2.543413"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "0.017866, 0.065807, 0.337647, 1.043323, 2.067033",\ + "0.017866, 0.065807, 0.337647, 1.043323, 2.067033",\ + "0.017866, 0.065807, 0.337647, 1.043323, 2.067033",\ + "0.017866, 0.065807, 0.337647, 1.043323, 2.067033",\ + "0.017866, 0.065807, 0.337647, 1.043323, 2.067033"); + } + + } /* end of arc clk_ast_ext_i_clk_src_aon_o_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "0.829665, 0.861273, 1.030054, 1.471171, 2.111088",\ + "0.917971, 0.949579, 1.118361, 1.559477, 2.199394",\ + "1.006180, 1.037788, 1.206569, 1.647686, 2.287603",\ + "1.155489, 1.187097, 1.355879, 1.796995, 2.436912",\ + "1.394823, 1.426431, 1.595212, 2.036328, 2.676246"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "0.018689, 0.076907, 0.397582, 1.240182, 2.462523",\ + "0.018689, 0.076907, 0.397582, 1.240182, 2.462523",\ + "0.018689, 0.076907, 0.397582, 1.240182, 2.462523",\ + "0.018689, 0.076907, 0.397582, 1.240182, 2.462523",\ + "0.018689, 0.076907, 0.397582, 1.240182, 2.462523"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "0.882434, 0.911296, 1.060191, 1.450065, 2.015647",\ + "0.969833, 0.998695, 1.147590, 1.537464, 2.103046",\ + "1.050646, 1.079508, 1.228404, 1.618278, 2.183859",\ + "1.188651, 1.217513, 1.366409, 1.756283, 2.321865",\ + "1.409136, 1.437999, 1.586894, 1.976768, 2.542350"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "0.017866, 0.065807, 0.337647, 1.043323, 2.067033",\ + "0.017866, 0.065807, 0.337647, 1.043323, 2.067033",\ + "0.017866, 0.065807, 0.337647, 1.043323, 2.067033",\ + "0.017866, 0.065807, 0.337647, 1.043323, 2.067033",\ + "0.017866, 0.065807, 0.337647, 1.043323, 2.067033"); + } + + } /* end of arc clk_ast_ext_i_clk_src_aon_o_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "970010.562500, 970010.562500, 970010.750000, 970011.187500, 970011.812500",\ + "970010.687500, 970010.687500, 970010.875000, 970011.312500, 970011.937500",\ + "970010.812500, 970010.812500, 970011.000000, 970011.437500, 970012.062500",\ + "970010.812500, 970010.812500, 970011.000000, 970011.437500, 970012.062500",\ + "970011.187500, 970011.187500, 970011.375000, 970011.812500, 970012.437500"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "0.018690, 0.076907, 0.397572, 1.240181, 2.462535",\ + "0.018690, 0.076907, 0.397572, 1.240181, 2.462535",\ + "0.018690, 0.076907, 0.397572, 1.240181, 2.462535",\ + "0.018690, 0.076907, 0.397572, 1.240181, 2.462535",\ + "0.018690, 0.076907, 0.397572, 1.240181, 2.462535"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "970010.375000, 970010.375000, 970010.562500, 970010.937500, 970011.500000",\ + "970010.500000, 970010.500000, 970010.687500, 970011.062500, 970011.625000",\ + "970010.625000, 970010.625000, 970010.812500, 970011.187500, 970011.750000",\ + "970010.625000, 970010.625000, 970010.812500, 970011.187500, 970011.750000",\ + "970011.000000, 970011.000000, 970011.187500, 970011.562500, 970012.125000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "0.017866, 0.065807, 0.337660, 1.043334, 2.067039",\ + "0.017866, 0.065807, 0.337660, 1.043334, 2.067039",\ + "0.017866, 0.065807, 0.337660, 1.043334, 2.067039",\ + "0.017866, 0.065807, 0.337660, 1.043334, 2.067039",\ + "0.017866, 0.065807, 0.337660, 1.043334, 2.067039"); + } + + } /* end of arc clk_ast_tlul_i_clk_src_aon_o_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "0.860464, 0.892073, 1.060854, 1.501970, 2.141887",\ + "0.948265, 0.979873, 1.148654, 1.589771, 2.229688",\ + "1.029564, 1.061172, 1.229954, 1.671070, 2.310987",\ + "1.087717, 1.119326, 1.288107, 1.729223, 2.369140",\ + "1.396438, 1.428046, 1.596828, 2.037944, 2.677861"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "0.018689, 0.076907, 0.397582, 1.240182, 2.462523",\ + "0.018689, 0.076907, 0.397582, 1.240182, 2.462523",\ + "0.018689, 0.076907, 0.397582, 1.240182, 2.462523",\ + "0.018689, 0.076907, 0.397582, 1.240182, 2.462523",\ + "0.018689, 0.076907, 0.397582, 1.240182, 2.462523"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "0.970766, 0.999628, 1.148520, 1.538388, 2.103961",\ + "1.058640, 1.087502, 1.236394, 1.626262, 2.191835",\ + "1.152976, 1.181838, 1.330730, 1.720598, 2.286171",\ + "1.220734, 1.249595, 1.398488, 1.788356, 2.353929",\ + "1.581432, 1.610294, 1.759186, 2.149055, 2.714628"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "0.017866, 0.065808, 0.337669, 1.043341, 2.067043",\ + "0.017866, 0.065808, 0.337669, 1.043341, 2.067043",\ + "0.017866, 0.065808, 0.337669, 1.043341, 2.067043",\ + "0.017866, 0.065808, 0.337669, 1.043341, 2.067043",\ + "0.017866, 0.065808, 0.337669, 1.043341, 2.067043"); + } + + } /* end of arc clk_ast_tlul_i_clk_src_aon_o_redg_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "970007.187500, 970007.187500, 970007.375000, 970007.812500, 970008.437500",\ + "970007.312500, 970007.312500, 970007.500000, 970007.937500, 970008.562500",\ + "970007.312500, 970007.312500, 970007.500000, 970007.937500, 970008.562500",\ + "970007.562500, 970007.562500, 970007.750000, 970008.187500, 970008.812500",\ + "970007.812500, 970007.812500, 970008.000000, 970008.437500, 970009.062500"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "0.018690, 0.076907, 0.397572, 1.240181, 2.462535",\ + "0.018690, 0.076907, 0.397572, 1.240181, 2.462535",\ + "0.018690, 0.076907, 0.397572, 1.240181, 2.462535",\ + "0.018690, 0.076907, 0.397572, 1.240181, 2.462535",\ + "0.018690, 0.076907, 0.397572, 1.240181, 2.462535"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "970010.250000, 970010.250000, 970010.437500, 970010.812500, 970011.375000",\ + "970010.375000, 970010.375000, 970010.562500, 970010.937500, 970011.500000",\ + "970010.500000, 970010.500000, 970010.687500, 970011.062500, 970011.625000",\ + "970010.750000, 970010.750000, 970010.937500, 970011.312500, 970011.875000",\ + "970011.000000, 970011.000000, 970011.187500, 970011.562500, 970012.125000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "0.017866, 0.065807, 0.337660, 1.043334, 2.067039",\ + "0.017866, 0.065807, 0.337660, 1.043334, 2.067039",\ + "0.017866, 0.065807, 0.337660, 1.043334, 2.067039",\ + "0.017866, 0.065807, 0.337660, 1.043334, 2.067039",\ + "0.017866, 0.065807, 0.337660, 1.043334, 2.067039"); + } + + } /* end of arc padmux2ast_i[4]_clk_src_aon_o_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "380008.531250, 380008.562500, 380008.750000, 380009.187500, 380009.812500",\ + "380008.625000, 380008.656250, 380008.843750, 380009.281250, 380009.906250",\ + "380008.687500, 380008.718750, 380008.906250, 380009.343750, 380009.968750",\ + "380008.843750, 380008.875000, 380009.062500, 380009.500000, 380010.125000",\ + "380009.062500, 380009.093750, 380009.281250, 380009.718750, 380010.343750"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "0.018689, 0.076907, 0.397582, 1.240182, 2.462523",\ + "0.018689, 0.076907, 0.397582, 1.240182, 2.462523",\ + "0.018689, 0.076907, 0.397582, 1.240182, 2.462523",\ + "0.018689, 0.076907, 0.397582, 1.240182, 2.462523",\ + "0.018689, 0.076907, 0.397582, 1.240182, 2.462523"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "380007.906250, 380007.906250, 380008.062500, 380008.468750, 380009.031250",\ + "380008.000000, 380008.000000, 380008.156250, 380008.562500, 380009.125000",\ + "380008.093750, 380008.093750, 380008.250000, 380008.656250, 380009.218750",\ + "380008.281250, 380008.281250, 380008.437500, 380008.843750, 380009.406250",\ + "380008.531250, 380008.531250, 380008.687500, 380009.093750, 380009.656250"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "0.017866, 0.065808, 0.337669, 1.043341, 2.067043",\ + "0.017866, 0.065808, 0.337669, 1.043341, 2.067043",\ + "0.017866, 0.065808, 0.337669, 1.043341, 2.067043",\ + "0.017866, 0.065808, 0.337669, 1.043341, 2.067043",\ + "0.017866, 0.065808, 0.337669, 1.043341, 2.067043"); + } + + } /* end of arc padmux2ast_i[4]_clk_src_aon_o_una_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "970007.437500, 970007.437500, 970007.625000, 970008.000000, 970008.562500",\ + "970007.562500, 970007.562500, 970007.750000, 970008.125000, 970008.687500",\ + "970007.562500, 970007.562500, 970007.750000, 970008.125000, 970008.687500",\ + "970007.812500, 970007.812500, 970008.000000, 970008.375000, 970008.937500",\ + "970008.062500, 970008.062500, 970008.250000, 970008.625000, 970009.187500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "0.017866, 0.065807, 0.337660, 1.043334, 2.067039",\ + "0.017866, 0.065807, 0.337660, 1.043334, 2.067039",\ + "0.017866, 0.065807, 0.337660, 1.043334, 2.067039",\ + "0.017866, 0.065807, 0.337660, 1.043334, 2.067039",\ + "0.017866, 0.065807, 0.337660, 1.043334, 2.067039"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "970010.437500, 970010.437500, 970010.625000, 970011.062500, 970011.687500",\ + "970010.562500, 970010.562500, 970010.750000, 970011.187500, 970011.812500",\ + "970010.687500, 970010.687500, 970010.875000, 970011.312500, 970011.937500",\ + "970010.937500, 970010.937500, 970011.125000, 970011.562500, 970012.187500",\ + "970011.187500, 970011.187500, 970011.375000, 970011.812500, 970012.437500"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "0.018690, 0.076907, 0.397572, 1.240181, 2.462535",\ + "0.018690, 0.076907, 0.397572, 1.240181, 2.462535",\ + "0.018690, 0.076907, 0.397572, 1.240181, 2.462535",\ + "0.018690, 0.076907, 0.397572, 1.240181, 2.462535",\ + "0.018690, 0.076907, 0.397572, 1.240181, 2.462535"); + } + + } /* end of arc padmux2ast_i[4]_clk_src_aon_o_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "380000.750000, 380000.750000, 380000.906250, 380001.312500, 380001.875000",\ + "380000.843750, 380000.843750, 380001.000000, 380001.406250, 380001.968750",\ + "380000.906250, 380000.906250, 380001.062500, 380001.468750, 380002.031250",\ + "380001.062500, 380001.062500, 380001.218750, 380001.625000, 380002.187500",\ + "380001.281250, 380001.281250, 380001.437500, 380001.843750, 380002.406250"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "0.017866, 0.065808, 0.337669, 1.043341, 2.067043",\ + "0.017866, 0.065808, 0.337669, 1.043341, 2.067043",\ + "0.017866, 0.065808, 0.337669, 1.043341, 2.067043",\ + "0.017866, 0.065808, 0.337669, 1.043341, 2.067043",\ + "0.017866, 0.065808, 0.337669, 1.043341, 2.067043"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "380002.031250, 380002.062500, 380002.250000, 380002.687500, 380003.312500",\ + "380002.125000, 380002.156250, 380002.343750, 380002.781250, 380003.406250",\ + "380002.218750, 380002.250000, 380002.437500, 380002.875000, 380003.500000",\ + "380002.406250, 380002.437500, 380002.625000, 380003.062500, 380003.687500",\ + "380002.656250, 380002.687500, 380002.875000, 380003.312500, 380003.937500"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "0.018689, 0.076907, 0.397582, 1.240182, 2.462523",\ + "0.018689, 0.076907, 0.397582, 1.240182, 2.462523",\ + "0.018689, 0.076907, 0.397582, 1.240182, 2.462523",\ + "0.018689, 0.076907, 0.397582, 1.240182, 2.462523",\ + "0.018689, 0.076907, 0.397582, 1.240182, 2.462523"); + } + + } /* end of arc padmux2ast_i[4]_clk_src_aon_o_inv_min*/ + + timing () { + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "590008.812500, 590008.812500, 590009.000000, 590009.437500, 590010.062500",\ + "590008.937500, 590008.937500, 590009.125000, 590009.562500, 590010.187500",\ + "590008.937500, 590008.937500, 590009.125000, 590009.562500, 590010.187500",\ + "590009.062500, 590009.062500, 590009.250000, 590009.687500, 590010.312500",\ + "590009.312500, 590009.312500, 590009.500000, 590009.937500, 590010.562500"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "0.018690, 0.076907, 0.397572, 1.240181, 2.462535",\ + "0.018690, 0.076907, 0.397572, 1.240181, 2.462535",\ + "0.018690, 0.076907, 0.397572, 1.240181, 2.462535",\ + "0.018690, 0.076907, 0.397572, 1.240181, 2.462535",\ + "0.018690, 0.076907, 0.397572, 1.240181, 2.462535"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "590007.187500, 590007.187500, 590007.375000, 590007.750000, 590008.312500",\ + "590007.312500, 590007.312500, 590007.500000, 590007.875000, 590008.437500",\ + "590007.437500, 590007.437500, 590007.625000, 590008.000000, 590008.562500",\ + "590007.562500, 590007.562500, 590007.750000, 590008.125000, 590008.687500",\ + "590007.937500, 590007.937500, 590008.125000, 590008.500000, 590009.062500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "0.017866, 0.065807, 0.337660, 1.043334, 2.067039",\ + "0.017866, 0.065807, 0.337660, 1.043334, 2.067039",\ + "0.017866, 0.065807, 0.337660, 1.043334, 2.067039",\ + "0.017866, 0.065807, 0.337660, 1.043334, 2.067039",\ + "0.017866, 0.065807, 0.337660, 1.043334, 2.067039"); + } + + } /* end of arc padmux2ast_i[5]_clk_src_aon_o_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "590008.812500, 590008.812500, 590009.000000, 590009.437500, 590010.062500",\ + "590008.812500, 590008.812500, 590009.000000, 590009.437500, 590010.062500",\ + "590008.937500, 590008.937500, 590009.125000, 590009.562500, 590010.187500",\ + "590009.062500, 590009.062500, 590009.250000, 590009.687500, 590010.312500",\ + "590009.312500, 590009.312500, 590009.500000, 590009.937500, 590010.562500"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "0.018689, 0.076907, 0.397577, 1.240181, 2.462529",\ + "0.018689, 0.076907, 0.397577, 1.240181, 2.462529",\ + "0.018689, 0.076907, 0.397577, 1.240181, 2.462529",\ + "0.018689, 0.076907, 0.397577, 1.240181, 2.462529",\ + "0.018689, 0.076907, 0.397577, 1.240181, 2.462529"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "590007.187500, 590007.187500, 590007.375000, 590007.750000, 590008.312500",\ + "590007.312500, 590007.312500, 590007.500000, 590007.875000, 590008.437500",\ + "590007.437500, 590007.437500, 590007.625000, 590008.000000, 590008.562500",\ + "590007.562500, 590007.562500, 590007.750000, 590008.125000, 590008.687500",\ + "590007.812500, 590007.812500, 590008.000000, 590008.375000, 590008.937500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "0.017866, 0.065808, 0.337663, 1.043336, 2.067040",\ + "0.017866, 0.065808, 0.337663, 1.043336, 2.067040",\ + "0.017866, 0.065808, 0.337663, 1.043336, 2.067040",\ + "0.017866, 0.065808, 0.337663, 1.043336, 2.067040",\ + "0.017866, 0.065808, 0.337663, 1.043336, 2.067040"); + } + + } /* end of arc padmux2ast_i[5]_clk_src_aon_o_una_min*/ + + timing () { + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "590008.625000, 590008.625000, 590008.812500, 590009.187500, 590009.750000",\ + "590008.750000, 590008.750000, 590008.937500, 590009.312500, 590009.875000",\ + "590008.750000, 590008.750000, 590008.937500, 590009.312500, 590009.875000",\ + "590008.875000, 590008.875000, 590009.062500, 590009.437500, 590010.000000",\ + "590009.125000, 590009.125000, 590009.312500, 590009.687500, 590010.250000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "0.017866, 0.065807, 0.337660, 1.043334, 2.067039",\ + "0.017866, 0.065807, 0.337660, 1.043334, 2.067039",\ + "0.017866, 0.065807, 0.337660, 1.043334, 2.067039",\ + "0.017866, 0.065807, 0.337660, 1.043334, 2.067039",\ + "0.017866, 0.065807, 0.337660, 1.043334, 2.067039"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "590006.937500, 590006.937500, 590007.125000, 590007.562500, 590008.187500",\ + "590007.062500, 590007.062500, 590007.250000, 590007.687500, 590008.312500",\ + "590007.187500, 590007.187500, 590007.375000, 590007.812500, 590008.437500",\ + "590007.312500, 590007.312500, 590007.500000, 590007.937500, 590008.562500",\ + "590007.687500, 590007.687500, 590007.875000, 590008.312500, 590008.937500"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "0.018690, 0.076907, 0.397572, 1.240181, 2.462535",\ + "0.018690, 0.076907, 0.397572, 1.240181, 2.462535",\ + "0.018690, 0.076907, 0.397572, 1.240181, 2.462535",\ + "0.018690, 0.076907, 0.397572, 1.240181, 2.462535",\ + "0.018690, 0.076907, 0.397572, 1.240181, 2.462535"); + } + + } /* end of arc padmux2ast_i[5]_clk_src_aon_o_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "590008.625000, 590008.625000, 590008.812500, 590009.187500, 590009.750000",\ + "590008.625000, 590008.625000, 590008.812500, 590009.187500, 590009.750000",\ + "590008.750000, 590008.750000, 590008.937500, 590009.312500, 590009.875000",\ + "590008.875000, 590008.875000, 590009.062500, 590009.437500, 590010.000000",\ + "590009.125000, 590009.125000, 590009.312500, 590009.687500, 590010.250000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "0.017866, 0.065808, 0.337663, 1.043336, 2.067040",\ + "0.017866, 0.065808, 0.337663, 1.043336, 2.067040",\ + "0.017866, 0.065808, 0.337663, 1.043336, 2.067040",\ + "0.017866, 0.065808, 0.337663, 1.043336, 2.067040",\ + "0.017866, 0.065808, 0.337663, 1.043336, 2.067040"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "590006.937500, 590006.937500, 590007.125000, 590007.562500, 590008.187500",\ + "590007.062500, 590007.062500, 590007.250000, 590007.687500, 590008.312500",\ + "590007.187500, 590007.187500, 590007.375000, 590007.812500, 590008.437500",\ + "590007.312500, 590007.312500, 590007.500000, 590007.937500, 590008.562500",\ + "590007.562500, 590007.562500, 590007.750000, 590008.187500, 590008.812500"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "0.018689, 0.076907, 0.397577, 1.240181, 2.462529",\ + "0.018689, 0.076907, 0.397577, 1.240181, 2.462529",\ + "0.018689, 0.076907, 0.397577, 1.240181, 2.462529",\ + "0.018689, 0.076907, 0.397577, 1.240181, 2.462529",\ + "0.018689, 0.076907, 0.397577, 1.240181, 2.462529"); + } + + } /* end of arc padmux2ast_i[5]_clk_src_aon_o_inv_min*/ + +} /* end of pin clk_src_aon_o */ + +pin("clk_src_aon_val_o") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.090214 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001189 ; + + /* Other user defined attributes. */ + original_pin : clk_src_aon_val_o; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "970010.375000, 970010.375000, 970010.500000, 970010.750000, 970011.625000",\ + "970010.500000, 970010.500000, 970010.625000, 970010.875000, 970011.750000",\ + "970010.625000, 970010.625000, 970010.750000, 970011.000000, 970011.875000",\ + "970010.625000, 970010.625000, 970010.750000, 970011.000000, 970011.875000",\ + "970011.000000, 970011.000000, 970011.125000, 970011.375000, 970012.250000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "0.051936, 0.116244, 0.271542, 0.799035, 2.469430",\ + "0.051936, 0.116244, 0.271542, 0.799035, 2.469430",\ + "0.051936, 0.116244, 0.271542, 0.799035, 2.469430",\ + "0.051936, 0.116244, 0.271542, 0.799035, 2.469430",\ + "0.051936, 0.116244, 0.271542, 0.799035, 2.469430"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "970010.312500, 970010.375000, 970010.437500, 970010.625000, 970011.250000",\ + "970010.437500, 970010.500000, 970010.562500, 970010.750000, 970011.375000",\ + "970010.562500, 970010.625000, 970010.687500, 970010.875000, 970011.500000",\ + "970010.562500, 970010.625000, 970010.687500, 970010.875000, 970011.500000",\ + "970010.937500, 970011.000000, 970011.062500, 970011.250000, 970011.875000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "0.049199, 0.090220, 0.188113, 0.536743, 1.653005",\ + "0.049199, 0.090220, 0.188113, 0.536743, 1.653005",\ + "0.049199, 0.090220, 0.188113, 0.536743, 1.653005",\ + "0.049199, 0.090220, 0.188113, 0.536743, 1.653005",\ + "0.049199, 0.090220, 0.188113, 0.536743, 1.653005"); + } + + } /* end of arc clk_ast_tlul_i_clk_src_aon_val_o_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "0.710726, 0.747218, 0.829413, 1.103529, 1.981775",\ + "0.798527, 0.835019, 0.917213, 1.191329, 2.069575",\ + "0.879826, 0.916318, 0.998513, 1.272629, 2.150875",\ + "0.937979, 0.974471, 1.056666, 1.330782, 2.209028",\ + "1.246700, 1.283192, 1.365386, 1.639502, 2.517748"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "0.051468, 0.115906, 0.271423, 0.789292, 2.460133",\ + "0.051468, 0.115906, 0.271423, 0.789292, 2.460133",\ + "0.051468, 0.115906, 0.271423, 0.789292, 2.460133",\ + "0.051468, 0.115906, 0.271423, 0.789292, 2.460133",\ + "0.051468, 0.115906, 0.271423, 0.789292, 2.460133"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "0.688713, 0.718170, 0.777854, 0.968115, 1.580205",\ + "0.776513, 0.805970, 0.865655, 1.055915, 1.668005",\ + "0.857813, 0.887270, 0.946954, 1.137214, 1.749305",\ + "0.915966, 0.945423, 1.005107, 1.195368, 1.807458",\ + "1.224687, 1.254144, 1.313828, 1.504088, 2.116179"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "0.046907, 0.088182, 0.186999, 0.533681, 1.651611",\ + "0.046907, 0.088182, 0.186999, 0.533681, 1.651611",\ + "0.046907, 0.088182, 0.186999, 0.533681, 1.651611",\ + "0.046907, 0.088182, 0.186999, 0.533681, 1.651611",\ + "0.046907, 0.088182, 0.186999, 0.533681, 1.651611"); + } + + } /* end of arc clk_ast_tlul_i_clk_src_aon_val_o_redg_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "970007.125000, 970007.125000, 970007.250000, 970007.500000, 970008.375000",\ + "970007.250000, 970007.250000, 970007.375000, 970007.625000, 970008.500000",\ + "970007.250000, 970007.250000, 970007.375000, 970007.625000, 970008.500000",\ + "970007.500000, 970007.500000, 970007.625000, 970007.875000, 970008.750000",\ + "970007.750000, 970007.750000, 970007.875000, 970008.125000, 970009.000000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "0.051936, 0.116244, 0.271542, 0.799035, 2.469430",\ + "0.051936, 0.116244, 0.271542, 0.799035, 2.469430",\ + "0.051936, 0.116244, 0.271542, 0.799035, 2.469430",\ + "0.051936, 0.116244, 0.271542, 0.799035, 2.469430",\ + "0.051936, 0.116244, 0.271542, 0.799035, 2.469430"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "970010.187500, 970010.250000, 970010.312500, 970010.500000, 970011.125000",\ + "970010.312500, 970010.375000, 970010.437500, 970010.625000, 970011.250000",\ + "970010.437500, 970010.500000, 970010.562500, 970010.750000, 970011.375000",\ + "970010.687500, 970010.750000, 970010.812500, 970011.000000, 970011.625000",\ + "970010.937500, 970011.000000, 970011.062500, 970011.250000, 970011.875000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "0.049199, 0.090220, 0.188113, 0.536743, 1.653005",\ + "0.049199, 0.090220, 0.188113, 0.536743, 1.653005",\ + "0.049199, 0.090220, 0.188113, 0.536743, 1.653005",\ + "0.049199, 0.090220, 0.188113, 0.536743, 1.653005",\ + "0.049199, 0.090220, 0.188113, 0.536743, 1.653005"); + } + + } /* end of arc padmux2ast_i[4]_clk_src_aon_val_o_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "380000.468750, 380000.500000, 380000.593750, 380000.843750, 380001.750000",\ + "380000.562500, 380000.593750, 380000.687500, 380000.937500, 380001.843750",\ + "380000.625000, 380000.656250, 380000.750000, 380001.000000, 380001.906250",\ + "380000.781250, 380000.812500, 380000.906250, 380001.156250, 380002.062500",\ + "380001.000000, 380001.031250, 380001.125000, 380001.375000, 380002.281250"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "0.051468, 0.115906, 0.271423, 0.789292, 2.460133",\ + "0.051468, 0.115906, 0.271423, 0.789292, 2.460133",\ + "0.051468, 0.115906, 0.271423, 0.789292, 2.460133",\ + "0.051468, 0.115906, 0.271423, 0.789292, 2.460133",\ + "0.051468, 0.115906, 0.271423, 0.789292, 2.460133"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "380001.906250, 380001.937500, 380002.000000, 380002.187500, 380002.781250",\ + "380002.000000, 380002.031250, 380002.093750, 380002.281250, 380002.875000",\ + "380002.093750, 380002.125000, 380002.187500, 380002.375000, 380002.968750",\ + "380002.281250, 380002.312500, 380002.375000, 380002.562500, 380003.156250",\ + "380002.531250, 380002.562500, 380002.625000, 380002.812500, 380003.406250"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "0.046907, 0.088182, 0.186999, 0.533681, 1.651611",\ + "0.046907, 0.088182, 0.186999, 0.533681, 1.651611",\ + "0.046907, 0.088182, 0.186999, 0.533681, 1.651611",\ + "0.046907, 0.088182, 0.186999, 0.533681, 1.651611",\ + "0.046907, 0.088182, 0.186999, 0.533681, 1.651611"); + } + + } /* end of arc padmux2ast_i[4]_clk_src_aon_val_o_una_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "970007.187500, 970007.187500, 970007.250000, 970007.437500, 970008.062500",\ + "970007.312500, 970007.312500, 970007.375000, 970007.562500, 970008.187500",\ + "970007.312500, 970007.312500, 970007.375000, 970007.562500, 970008.187500",\ + "970007.562500, 970007.562500, 970007.625000, 970007.812500, 970008.437500",\ + "970007.812500, 970007.812500, 970007.875000, 970008.062500, 970008.687500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "0.049199, 0.090220, 0.188113, 0.536743, 1.653005",\ + "0.049199, 0.090220, 0.188113, 0.536743, 1.653005",\ + "0.049199, 0.090220, 0.188113, 0.536743, 1.653005",\ + "0.049199, 0.090220, 0.188113, 0.536743, 1.653005",\ + "0.049199, 0.090220, 0.188113, 0.536743, 1.653005"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "970010.250000, 970010.250000, 970010.375000, 970010.625000, 970011.500000",\ + "970010.375000, 970010.375000, 970010.500000, 970010.750000, 970011.625000",\ + "970010.500000, 970010.500000, 970010.625000, 970010.875000, 970011.750000",\ + "970010.750000, 970010.750000, 970010.875000, 970011.125000, 970012.000000",\ + "970011.000000, 970011.000000, 970011.125000, 970011.375000, 970012.250000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "0.051936, 0.116244, 0.271542, 0.799035, 2.469430",\ + "0.051936, 0.116244, 0.271542, 0.799035, 2.469430",\ + "0.051936, 0.116244, 0.271542, 0.799035, 2.469430",\ + "0.051936, 0.116244, 0.271542, 0.799035, 2.469430",\ + "0.051936, 0.116244, 0.271542, 0.799035, 2.469430"); + } + + } /* end of arc padmux2ast_i[4]_clk_src_aon_val_o_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "380000.500000, 380000.531250, 380000.593750, 380000.781250, 380001.406250",\ + "380000.593750, 380000.625000, 380000.687500, 380000.875000, 380001.500000",\ + "380000.656250, 380000.687500, 380000.750000, 380000.937500, 380001.562500",\ + "380000.812500, 380000.843750, 380000.906250, 380001.093750, 380001.718750",\ + "380001.031250, 380001.062500, 380001.125000, 380001.312500, 380001.937500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "0.046907, 0.088182, 0.186999, 0.533681, 1.651611",\ + "0.046907, 0.088182, 0.186999, 0.533681, 1.651611",\ + "0.046907, 0.088182, 0.186999, 0.533681, 1.651611",\ + "0.046907, 0.088182, 0.186999, 0.533681, 1.651611",\ + "0.046907, 0.088182, 0.186999, 0.533681, 1.651611"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "380001.906250, 380001.968750, 380002.031250, 380002.312500, 380003.187500",\ + "380002.000000, 380002.062500, 380002.125000, 380002.406250, 380003.281250",\ + "380002.093750, 380002.156250, 380002.218750, 380002.500000, 380003.375000",\ + "380002.281250, 380002.343750, 380002.406250, 380002.687500, 380003.562500",\ + "380002.531250, 380002.593750, 380002.656250, 380002.937500, 380003.812500"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "0.051468, 0.115906, 0.271423, 0.789292, 2.460133",\ + "0.051468, 0.115906, 0.271423, 0.789292, 2.460133",\ + "0.051468, 0.115906, 0.271423, 0.789292, 2.460133",\ + "0.051468, 0.115906, 0.271423, 0.789292, 2.460133",\ + "0.051468, 0.115906, 0.271423, 0.789292, 2.460133"); + } + + } /* end of arc padmux2ast_i[4]_clk_src_aon_val_o_inv_min*/ + + timing () { + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "590008.625000, 590008.625000, 590008.750000, 590009.000000, 590009.875000",\ + "590008.750000, 590008.750000, 590008.875000, 590009.125000, 590010.000000",\ + "590008.750000, 590008.750000, 590008.875000, 590009.125000, 590010.000000",\ + "590008.875000, 590008.875000, 590009.000000, 590009.250000, 590010.125000",\ + "590009.125000, 590009.125000, 590009.250000, 590009.500000, 590010.375000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "0.051936, 0.116244, 0.271542, 0.799058, 2.469430",\ + "0.051936, 0.116244, 0.271542, 0.799058, 2.469430",\ + "0.051936, 0.116244, 0.271542, 0.799058, 2.469430",\ + "0.051936, 0.116244, 0.271542, 0.799058, 2.469430",\ + "0.051936, 0.116244, 0.271542, 0.799058, 2.469430"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "590006.937500, 590006.937500, 590007.000000, 590007.187500, 590007.812500",\ + "590007.062500, 590007.062500, 590007.125000, 590007.312500, 590007.937500",\ + "590007.187500, 590007.187500, 590007.250000, 590007.437500, 590008.062500",\ + "590007.312500, 590007.312500, 590007.375000, 590007.562500, 590008.187500",\ + "590007.687500, 590007.687500, 590007.750000, 590007.937500, 590008.562500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "0.049199, 0.090220, 0.188113, 0.536750, 1.653005",\ + "0.049199, 0.090220, 0.188113, 0.536750, 1.653005",\ + "0.049199, 0.090220, 0.188113, 0.536750, 1.653005",\ + "0.049199, 0.090220, 0.188113, 0.536750, 1.653005",\ + "0.049199, 0.090220, 0.188113, 0.536750, 1.653005"); + } + + } /* end of arc padmux2ast_i[5]_clk_src_aon_val_o_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "590008.437500, 590008.437500, 590008.500000, 590008.812500, 590009.687500",\ + "590008.437500, 590008.437500, 590008.500000, 590008.812500, 590009.687500",\ + "590008.562500, 590008.562500, 590008.625000, 590008.937500, 590009.812500",\ + "590008.687500, 590008.687500, 590008.750000, 590009.062500, 590009.937500",\ + "590008.937500, 590008.937500, 590009.000000, 590009.312500, 590010.187500"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "0.051557, 0.115907, 0.271016, 0.788173, 2.465855",\ + "0.051557, 0.115907, 0.271016, 0.788173, 2.465855",\ + "0.051557, 0.115907, 0.271016, 0.788173, 2.465855",\ + "0.051557, 0.115907, 0.271016, 0.788173, 2.465855",\ + "0.051557, 0.115907, 0.271016, 0.788173, 2.465855"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "590006.750000, 590006.750000, 590006.812500, 590007.000000, 590007.625000",\ + "590006.875000, 590006.875000, 590006.937500, 590007.125000, 590007.750000",\ + "590007.000000, 590007.000000, 590007.062500, 590007.250000, 590007.875000",\ + "590007.125000, 590007.125000, 590007.187500, 590007.375000, 590008.000000",\ + "590007.375000, 590007.375000, 590007.437500, 590007.625000, 590008.250000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "0.046941, 0.088258, 0.187000, 0.531185, 1.650439",\ + "0.046941, 0.088258, 0.187000, 0.531185, 1.650439",\ + "0.046941, 0.088258, 0.187000, 0.531185, 1.650439",\ + "0.046941, 0.088258, 0.187000, 0.531185, 1.650439",\ + "0.046941, 0.088258, 0.187000, 0.531185, 1.650439"); + } + + } /* end of arc padmux2ast_i[5]_clk_src_aon_val_o_una_min*/ + + timing () { + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "590008.562500, 590008.625000, 590008.687500, 590008.875000, 590009.500000",\ + "590008.687500, 590008.750000, 590008.812500, 590009.000000, 590009.625000",\ + "590008.687500, 590008.750000, 590008.812500, 590009.000000, 590009.625000",\ + "590008.812500, 590008.875000, 590008.937500, 590009.125000, 590009.750000",\ + "590009.062500, 590009.125000, 590009.187500, 590009.375000, 590010.000000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "0.049199, 0.090220, 0.188113, 0.536750, 1.653005",\ + "0.049199, 0.090220, 0.188113, 0.536750, 1.653005",\ + "0.049199, 0.090220, 0.188113, 0.536750, 1.653005",\ + "0.049199, 0.090220, 0.188113, 0.536750, 1.653005",\ + "0.049199, 0.090220, 0.188113, 0.536750, 1.653005"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "590006.875000, 590006.875000, 590007.000000, 590007.250000, 590008.125000",\ + "590007.000000, 590007.000000, 590007.125000, 590007.375000, 590008.250000",\ + "590007.125000, 590007.125000, 590007.250000, 590007.500000, 590008.375000",\ + "590007.250000, 590007.250000, 590007.375000, 590007.625000, 590008.500000",\ + "590007.625000, 590007.625000, 590007.750000, 590008.000000, 590008.875000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "0.051936, 0.116244, 0.271542, 0.799058, 2.469430",\ + "0.051936, 0.116244, 0.271542, 0.799058, 2.469430",\ + "0.051936, 0.116244, 0.271542, 0.799058, 2.469430",\ + "0.051936, 0.116244, 0.271542, 0.799058, 2.469430",\ + "0.051936, 0.116244, 0.271542, 0.799058, 2.469430"); + } + + } /* end of arc padmux2ast_i[5]_clk_src_aon_val_o_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "590008.562500, 590008.625000, 590008.687500, 590008.875000, 590009.500000",\ + "590008.562500, 590008.625000, 590008.687500, 590008.875000, 590009.500000",\ + "590008.687500, 590008.750000, 590008.812500, 590009.000000, 590009.625000",\ + "590008.812500, 590008.875000, 590008.937500, 590009.125000, 590009.750000",\ + "590009.062500, 590009.125000, 590009.187500, 590009.375000, 590010.000000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "0.046941, 0.088258, 0.187000, 0.531185, 1.650439",\ + "0.046941, 0.088258, 0.187000, 0.531185, 1.650439",\ + "0.046941, 0.088258, 0.187000, 0.531185, 1.650439",\ + "0.046941, 0.088258, 0.187000, 0.531185, 1.650439",\ + "0.046941, 0.088258, 0.187000, 0.531185, 1.650439"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "590006.875000, 590006.875000, 590007.000000, 590007.250000, 590008.125000",\ + "590007.000000, 590007.000000, 590007.125000, 590007.375000, 590008.250000",\ + "590007.125000, 590007.125000, 590007.250000, 590007.500000, 590008.375000",\ + "590007.250000, 590007.250000, 590007.375000, 590007.625000, 590008.500000",\ + "590007.500000, 590007.500000, 590007.625000, 590007.875000, 590008.750000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "0.051557, 0.115907, 0.271016, 0.788173, 2.465855",\ + "0.051557, 0.115907, 0.271016, 0.788173, 2.465855",\ + "0.051557, 0.115907, 0.271016, 0.788173, 2.465855",\ + "0.051557, 0.115907, 0.271016, 0.788173, 2.465855",\ + "0.051557, 0.115907, 0.271016, 0.788173, 2.465855"); + } + + } /* end of arc padmux2ast_i[5]_clk_src_aon_val_o_inv_min*/ + +} /* end of pin clk_src_aon_val_o */ + +pin("clk_src_io_en_i") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.002154 ; + + /* Other user defined attributes. */ + original_pin : clk_src_io_en_i; + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.200076, 0.146984, 0.107694, 0.090457, 0.087585",\ + "0.271588, 0.219415, 0.179927, 0.162045, 0.157577",\ + "0.363033, 0.310027, 0.270334, 0.252385, 0.247965",\ + "0.507780, 0.454308, 0.413646, 0.395357, 0.391106",\ + "0.811131, 0.757315, 0.714144, 0.694969, 0.691143"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.249331, 0.166333, 0.091045, 0.049669, 0.020498",\ + "0.324602, 0.241857, 0.166855, 0.126539, 0.100040",\ + "0.429418, 0.345854, 0.270221, 0.227986, 0.196782",\ + "0.605833, 0.521783, 0.445878, 0.397956, 0.350944",\ + "0.983325, 0.898854, 0.822917, 0.761117, 0.674795"); + } + + } /* end of arc clk_ast_ext_i_clk_src_io_en_i_stupr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.096530, -0.053812, -0.018112, 0.032751, 0.135173",\ + "-0.166367, -0.123600, -0.088245, -0.037477, 0.065076",\ + "-0.251291, -0.208679, -0.174484, -0.124115, -0.021332",\ + "-0.373429, -0.330963, -0.299719, -0.251733, -0.152256",\ + "-0.620310, -0.578080, -0.553843, -0.512151, -0.422314"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.130907, -0.055165, 0.010770, 0.102409, 0.285045",\ + "-0.205839, -0.131127, -0.064641, 0.027653, 0.211502",\ + "-0.308157, -0.233980, -0.166224, -0.072248, 0.114884",\ + "-0.470591, -0.397956, -0.329423, -0.234665, -0.046227",\ + "-0.811364, -0.742478, -0.673228, -0.578223, -0.389923"); + } + + } /* end of arc clk_ast_ext_i_clk_src_io_en_i_hldr*/ + +} /* end of pin clk_src_io_en_i */ + +pin("clk_src_io_o") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.069236 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.028657 ; + + /* Other user defined attributes. */ + original_pin : clk_src_io_o; + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : falling_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "1.549102, 1.558939, 1.580409, 1.648733, 2.140488",\ + "1.549102, 1.558939, 1.580409, 1.648733, 2.140488",\ + "1.549102, 1.558939, 1.580409, 1.648733, 2.140488",\ + "1.549102, 1.558939, 1.580409, 1.648733, 2.140488",\ + "1.549102, 1.558939, 1.580409, 1.648733, 2.140488"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "1.576328, 1.589726, 1.618968, 1.712027, 2.381811",\ + "1.576328, 1.589726, 1.618968, 1.712027, 2.381811",\ + "1.576328, 1.589726, 1.618968, 1.712027, 2.381811",\ + "1.576328, 1.589726, 1.618968, 1.712027, 2.381811",\ + "1.576328, 1.589726, 1.618968, 1.712027, 2.381811"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "0.969570, 0.993149, 1.044609, 1.208373, 2.387050",\ + "0.969570, 0.993149, 1.044609, 1.208373, 2.387050",\ + "0.969570, 0.993149, 1.044609, 1.208373, 2.387050",\ + "0.969570, 0.993149, 1.044609, 1.208373, 2.387050",\ + "0.969570, 0.993149, 1.044609, 1.208373, 2.387050"); + } + + } /* end of arc clk_ast_ext_i_clk_src_io_o_fedg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_ext_i" ; + timing_type : falling_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "1.548301, 1.558138, 1.579608, 1.647932, 2.139687",\ + "1.548301, 1.558138, 1.579608, 1.647932, 2.139687",\ + "1.548301, 1.558138, 1.579608, 1.647932, 2.139687",\ + "1.548301, 1.558138, 1.579608, 1.647932, 2.139687",\ + "1.548301, 1.558138, 1.579608, 1.647932, 2.139687"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "1.574098, 1.587497, 1.616739, 1.709798, 2.379581",\ + "1.574098, 1.587497, 1.616739, 1.709798, 2.379581",\ + "1.574098, 1.587497, 1.616739, 1.709798, 2.379581",\ + "1.574098, 1.587497, 1.616739, 1.709798, 2.379581",\ + "1.574098, 1.587497, 1.616739, 1.709798, 2.379581"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "0.969570, 0.993149, 1.044608, 1.208373, 2.387050",\ + "0.969570, 0.993149, 1.044608, 1.208373, 2.387050",\ + "0.969570, 0.993149, 1.044608, 1.208373, 2.387050",\ + "0.969570, 0.993149, 1.044608, 1.208373, 2.387050",\ + "0.969570, 0.993149, 1.044608, 1.208373, 2.387050"); + } + + } /* end of arc clk_ast_ext_i_clk_src_io_o_fedg_min*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "1.452656, 1.462494, 1.483963, 1.552287, 2.044042",\ + "1.532226, 1.542063, 1.563532, 1.631856, 2.123611",\ + "1.612140, 1.621977, 1.643447, 1.711771, 2.203526",\ + "1.741866, 1.751703, 1.773172, 1.841496, 2.333251",\ + "1.941871, 1.951709, 1.973178, 2.041502, 2.533257"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "1.431237, 1.444636, 1.473878, 1.566937, 2.236720",\ + "1.520409, 1.533808, 1.563050, 1.656109, 2.325892",\ + "1.611352, 1.624751, 1.653993, 1.747052, 2.416835",\ + "1.766391, 1.779789, 1.809031, 1.902090, 2.571874",\ + "2.019272, 2.032671, 2.061913, 2.154972, 2.824755"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "0.969570, 0.993149, 1.044609, 1.208373, 2.387050",\ + "0.969570, 0.993149, 1.044609, 1.208373, 2.387050",\ + "0.969570, 0.993149, 1.044609, 1.208373, 2.387050",\ + "0.969570, 0.993149, 1.044609, 1.208373, 2.387050",\ + "0.969570, 0.993149, 1.044609, 1.208373, 2.387050"); + } + + } /* end of arc clk_ast_ext_i_clk_src_io_o_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_ext_i" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "1.436974, 1.446811, 1.468281, 1.536605, 2.028360",\ + "1.516723, 1.526561, 1.548030, 1.616354, 2.108109",\ + "1.592126, 1.601964, 1.623433, 1.691757, 2.183512",\ + "1.712250, 1.722088, 1.743557, 1.811881, 2.303636",\ + "1.895420, 1.905257, 1.926727, 1.995051, 2.486806"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "1.423435, 1.436834, 1.466076, 1.559135, 2.228919",\ + "1.511023, 1.524422, 1.553663, 1.646723, 2.316506",\ + "1.597821, 1.611220, 1.640462, 1.733521, 2.403305",\ + "1.747068, 1.760467, 1.789708, 1.882767, 2.552551",\ + "1.991484, 2.004883, 2.034125, 2.127184, 2.796968"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "0.969570, 0.993149, 1.044608, 1.208373, 2.387050",\ + "0.969570, 0.993149, 1.044608, 1.208373, 2.387050",\ + "0.969570, 0.993149, 1.044608, 1.208373, 2.387050",\ + "0.969570, 0.993149, 1.044608, 1.208373, 2.387050",\ + "0.969570, 0.993149, 1.044608, 1.208373, 2.387050"); + } + + } /* end of arc clk_ast_ext_i_clk_src_io_o_una_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "970011.937500, 970011.937500, 970011.937500, 970012.062500, 970012.500000",\ + "970012.062500, 970012.062500, 970012.062500, 970012.187500, 970012.625000",\ + "970012.187500, 970012.187500, 970012.187500, 970012.312500, 970012.750000",\ + "970012.187500, 970012.187500, 970012.187500, 970012.312500, 970012.750000",\ + "970012.562500, 970012.562500, 970012.562500, 970012.687500, 970013.125000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "0.813271, 0.831978, 0.872805, 1.002733, 1.937878",\ + "0.813271, 0.831978, 0.872805, 1.002733, 1.937878",\ + "0.813271, 0.831978, 0.872805, 1.002733, 1.937878",\ + "0.813271, 0.831978, 0.872805, 1.002733, 1.937878",\ + "0.813271, 0.831978, 0.872805, 1.002733, 1.937878"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "970010.562500, 970010.625000, 970010.625000, 970010.687500, 970011.375000",\ + "970010.687500, 970010.750000, 970010.750000, 970010.812500, 970011.500000",\ + "970010.812500, 970010.875000, 970010.875000, 970010.937500, 970011.625000",\ + "970010.812500, 970010.875000, 970010.875000, 970010.937500, 970011.625000",\ + "970011.187500, 970011.250000, 970011.250000, 970011.312500, 970012.000000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "0.967112, 0.990771, 1.042405, 1.206725, 2.390203",\ + "0.967112, 0.990771, 1.042405, 1.206725, 2.390203",\ + "0.967112, 0.990771, 1.042405, 1.206725, 2.390203",\ + "0.967112, 0.990771, 1.042405, 1.206725, 2.390203",\ + "0.967112, 0.990771, 1.042405, 1.206725, 2.390203"); + } + + } /* end of arc clk_ast_tlul_i_clk_src_io_o_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "0.979131, 0.988972, 1.010450, 1.078799, 1.570735",\ + "1.066932, 1.076773, 1.098250, 1.166599, 1.658535",\ + "1.148231, 1.158072, 1.179549, 1.247899, 1.739835",\ + "1.206384, 1.216226, 1.237703, 1.306052, 1.797988",\ + "1.515105, 1.524946, 1.546423, 1.614772, 2.106709"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "1.139635, 1.153062, 1.182364, 1.275615, 1.946779",\ + "1.227509, 1.240935, 1.270237, 1.363488, 2.034653",\ + "1.321845, 1.335272, 1.364574, 1.457825, 2.128989",\ + "1.389603, 1.403029, 1.432331, 1.525582, 2.196747",\ + "1.750301, 1.763728, 1.793030, 1.886281, 2.557446"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "0.965198, 0.988888, 1.040589, 1.205123, 2.387050",\ + "0.965198, 0.988888, 1.040589, 1.205123, 2.387050",\ + "0.965198, 0.988888, 1.040589, 1.205123, 2.387050",\ + "0.965198, 0.988888, 1.040589, 1.205123, 2.387050",\ + "0.965198, 0.988888, 1.040589, 1.205123, 2.387050"); + } + + } /* end of arc clk_ast_tlul_i_clk_src_io_o_redg_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "970007.250000, 970007.250000, 970007.312500, 970007.375000, 970007.875000",\ + "970007.375000, 970007.375000, 970007.437500, 970007.500000, 970008.000000",\ + "970007.375000, 970007.375000, 970007.437500, 970007.500000, 970008.000000",\ + "970007.625000, 970007.625000, 970007.687500, 970007.750000, 970008.250000",\ + "970007.875000, 970007.875000, 970007.937500, 970008.000000, 970008.500000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "0.813271, 0.831978, 0.872805, 1.002733, 1.937878",\ + "0.813271, 0.831978, 0.872805, 1.002733, 1.937878",\ + "0.813271, 0.831978, 0.872805, 1.002733, 1.937878",\ + "0.813271, 0.831978, 0.872805, 1.002733, 1.937878",\ + "0.813271, 0.831978, 0.872805, 1.002733, 1.937878"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "970010.437500, 970010.500000, 970010.500000, 970010.562500, 970011.250000",\ + "970010.562500, 970010.625000, 970010.625000, 970010.687500, 970011.375000",\ + "970010.687500, 970010.750000, 970010.750000, 970010.812500, 970011.500000",\ + "970010.937500, 970011.000000, 970011.000000, 970011.062500, 970011.750000",\ + "970011.187500, 970011.250000, 970011.250000, 970011.312500, 970012.000000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "0.967112, 0.990771, 1.042405, 1.206725, 2.390203",\ + "0.967112, 0.990771, 1.042405, 1.206725, 2.390203",\ + "0.967112, 0.990771, 1.042405, 1.206725, 2.390203",\ + "0.967112, 0.990771, 1.042405, 1.206725, 2.390203",\ + "0.967112, 0.990771, 1.042405, 1.206725, 2.390203"); + } + + } /* end of arc padmux2ast_i[4]_clk_src_io_o_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "380001.562500, 380001.593750, 380001.593750, 380001.687500, 380002.156250",\ + "380001.656250, 380001.687500, 380001.687500, 380001.781250, 380002.250000",\ + "380001.718750, 380001.750000, 380001.750000, 380001.843750, 380002.312500",\ + "380001.875000, 380001.906250, 380001.906250, 380002.000000, 380002.468750",\ + "380002.093750, 380002.125000, 380002.125000, 380002.218750, 380002.687500"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "380003.031250, 380003.062500, 380003.093750, 380003.187500, 380003.843750",\ + "380003.125000, 380003.156250, 380003.187500, 380003.281250, 380003.937500",\ + "380003.218750, 380003.250000, 380003.281250, 380003.375000, 380004.031250",\ + "380003.406250, 380003.437500, 380003.468750, 380003.562500, 380004.218750",\ + "380003.656250, 380003.687500, 380003.718750, 380003.812500, 380004.468750"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "0.965198, 0.988888, 1.040589, 1.205123, 2.387050",\ + "0.965198, 0.988888, 1.040589, 1.205123, 2.387050",\ + "0.965198, 0.988888, 1.040589, 1.205123, 2.387050",\ + "0.965198, 0.988888, 1.040589, 1.205123, 2.387050",\ + "0.965198, 0.988888, 1.040589, 1.205123, 2.387050"); + } + + } /* end of arc padmux2ast_i[4]_clk_src_io_o_una_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "970008.625000, 970008.625000, 970008.625000, 970008.750000, 970009.437500",\ + "970008.750000, 970008.750000, 970008.750000, 970008.875000, 970009.562500",\ + "970008.750000, 970008.750000, 970008.750000, 970008.875000, 970009.562500",\ + "970009.000000, 970009.000000, 970009.000000, 970009.125000, 970009.812500",\ + "970009.250000, 970009.250000, 970009.250000, 970009.375000, 970010.062500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "0.967112, 0.990771, 1.042405, 1.206725, 2.390203",\ + "0.967112, 0.990771, 1.042405, 1.206725, 2.390203",\ + "0.967112, 0.990771, 1.042405, 1.206725, 2.390203",\ + "0.967112, 0.990771, 1.042405, 1.206725, 2.390203",\ + "0.967112, 0.990771, 1.042405, 1.206725, 2.390203"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "970011.812500, 970011.812500, 970011.812500, 970011.937500, 970012.375000",\ + "970011.937500, 970011.937500, 970011.937500, 970012.062500, 970012.500000",\ + "970012.062500, 970012.062500, 970012.062500, 970012.187500, 970012.625000",\ + "970012.312500, 970012.312500, 970012.312500, 970012.437500, 970012.875000",\ + "970012.562500, 970012.562500, 970012.562500, 970012.687500, 970013.125000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "0.813271, 0.831978, 0.872805, 1.002733, 1.937878",\ + "0.813271, 0.831978, 0.872805, 1.002733, 1.937878",\ + "0.813271, 0.831978, 0.872805, 1.002733, 1.937878",\ + "0.813271, 0.831978, 0.872805, 1.002733, 1.937878",\ + "0.813271, 0.831978, 0.872805, 1.002733, 1.937878"); + } + + } /* end of arc padmux2ast_i[4]_clk_src_io_o_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "380000.875000, 380000.906250, 380000.937500, 380001.031250, 380001.687500",\ + "380000.968750, 380001.000000, 380001.031250, 380001.125000, 380001.781250",\ + "380001.031250, 380001.062500, 380001.093750, 380001.187500, 380001.843750",\ + "380001.187500, 380001.218750, 380001.250000, 380001.343750, 380002.000000",\ + "380001.406250, 380001.437500, 380001.468750, 380001.562500, 380002.218750"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "0.965198, 0.988888, 1.040589, 1.205123, 2.387050",\ + "0.965198, 0.988888, 1.040589, 1.205123, 2.387050",\ + "0.965198, 0.988888, 1.040589, 1.205123, 2.387050",\ + "0.965198, 0.988888, 1.040589, 1.205123, 2.387050",\ + "0.965198, 0.988888, 1.040589, 1.205123, 2.387050"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "380002.156250, 380002.187500, 380002.187500, 380002.281250, 380002.750000",\ + "380002.250000, 380002.281250, 380002.281250, 380002.375000, 380002.843750",\ + "380002.343750, 380002.375000, 380002.375000, 380002.468750, 380002.937500",\ + "380002.531250, 380002.562500, 380002.562500, 380002.656250, 380003.125000",\ + "380002.781250, 380002.812500, 380002.812500, 380002.906250, 380003.375000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571"); + } + + } /* end of arc padmux2ast_i[4]_clk_src_io_o_inv_min*/ + + timing () { + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "590010.187500, 590010.187500, 590010.187500, 590010.312500, 590010.750000",\ + "590010.312500, 590010.312500, 590010.312500, 590010.437500, 590010.875000",\ + "590010.312500, 590010.312500, 590010.312500, 590010.437500, 590010.875000",\ + "590010.437500, 590010.437500, 590010.437500, 590010.562500, 590011.000000",\ + "590010.687500, 590010.687500, 590010.687500, 590010.812500, 590011.250000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "0.813271, 0.831978, 0.872805, 1.002733, 1.937878",\ + "0.813271, 0.831978, 0.872805, 1.002733, 1.937878",\ + "0.813271, 0.831978, 0.872805, 1.002733, 1.937878",\ + "0.813271, 0.831978, 0.872805, 1.002733, 1.937878",\ + "0.813271, 0.831978, 0.872805, 1.002733, 1.937878"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "590008.375000, 590008.375000, 590008.375000, 590008.500000, 590009.187500",\ + "590008.500000, 590008.500000, 590008.500000, 590008.625000, 590009.312500",\ + "590008.625000, 590008.625000, 590008.625000, 590008.750000, 590009.437500",\ + "590008.750000, 590008.750000, 590008.750000, 590008.875000, 590009.562500",\ + "590009.125000, 590009.125000, 590009.125000, 590009.250000, 590009.937500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "0.967112, 0.990771, 1.042405, 1.206725, 2.390202",\ + "0.967112, 0.990771, 1.042405, 1.206725, 2.390202",\ + "0.967112, 0.990771, 1.042405, 1.206725, 2.390202",\ + "0.967112, 0.990771, 1.042405, 1.206725, 2.390202",\ + "0.967112, 0.990771, 1.042405, 1.206725, 2.390202"); + } + + } /* end of arc padmux2ast_i[5]_clk_src_io_o_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "590008.875000, 590008.875000, 590008.937500, 590009.000000, 590009.500000",\ + "590008.875000, 590008.875000, 590008.937500, 590009.000000, 590009.500000",\ + "590009.000000, 590009.000000, 590009.062500, 590009.125000, 590009.625000",\ + "590009.125000, 590009.125000, 590009.187500, 590009.250000, 590009.750000",\ + "590009.375000, 590009.375000, 590009.437500, 590009.500000, 590010.000000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "590007.250000, 590007.250000, 590007.312500, 590007.375000, 590008.062500",\ + "590007.375000, 590007.375000, 590007.437500, 590007.500000, 590008.187500",\ + "590007.500000, 590007.500000, 590007.562500, 590007.625000, 590008.312500",\ + "590007.625000, 590007.625000, 590007.687500, 590007.750000, 590008.437500",\ + "590007.875000, 590007.875000, 590007.937500, 590008.000000, 590008.687500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "0.965982, 0.989673, 1.041377, 1.205920, 2.387050",\ + "0.965982, 0.989673, 1.041377, 1.205920, 2.387050",\ + "0.965982, 0.989673, 1.041377, 1.205920, 2.387050",\ + "0.965982, 0.989673, 1.041377, 1.205920, 2.387050",\ + "0.965982, 0.989673, 1.041377, 1.205920, 2.387050"); + } + + } /* end of arc padmux2ast_i[5]_clk_src_io_o_una_min*/ + + timing () { + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "590008.812500, 590008.875000, 590008.875000, 590008.937500, 590009.625000",\ + "590008.937500, 590009.000000, 590009.000000, 590009.062500, 590009.750000",\ + "590008.937500, 590009.000000, 590009.000000, 590009.062500, 590009.750000",\ + "590009.062500, 590009.125000, 590009.125000, 590009.187500, 590009.875000",\ + "590009.312500, 590009.375000, 590009.375000, 590009.437500, 590010.125000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "0.967112, 0.990771, 1.042405, 1.206725, 2.390202",\ + "0.967112, 0.990771, 1.042405, 1.206725, 2.390202",\ + "0.967112, 0.990771, 1.042405, 1.206725, 2.390202",\ + "0.967112, 0.990771, 1.042405, 1.206725, 2.390202",\ + "0.967112, 0.990771, 1.042405, 1.206725, 2.390202"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "590007.000000, 590007.000000, 590007.062500, 590007.125000, 590007.625000",\ + "590007.125000, 590007.125000, 590007.187500, 590007.250000, 590007.750000",\ + "590007.250000, 590007.250000, 590007.312500, 590007.375000, 590007.875000",\ + "590007.375000, 590007.375000, 590007.437500, 590007.500000, 590008.000000",\ + "590007.750000, 590007.750000, 590007.812500, 590007.875000, 590008.375000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "0.813271, 0.831978, 0.872805, 1.002733, 1.937878",\ + "0.813271, 0.831978, 0.872805, 1.002733, 1.937878",\ + "0.813271, 0.831978, 0.872805, 1.002733, 1.937878",\ + "0.813271, 0.831978, 0.872805, 1.002733, 1.937878",\ + "0.813271, 0.831978, 0.872805, 1.002733, 1.937878"); + } + + } /* end of arc padmux2ast_i[5]_clk_src_io_o_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "590008.812500, 590008.875000, 590008.875000, 590008.937500, 590009.625000",\ + "590008.812500, 590008.875000, 590008.875000, 590008.937500, 590009.625000",\ + "590008.937500, 590009.000000, 590009.000000, 590009.062500, 590009.750000",\ + "590009.062500, 590009.125000, 590009.125000, 590009.187500, 590009.875000",\ + "590009.312500, 590009.375000, 590009.375000, 590009.437500, 590010.125000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "0.965982, 0.989673, 1.041377, 1.205920, 2.387050",\ + "0.965982, 0.989673, 1.041377, 1.205920, 2.387050",\ + "0.965982, 0.989673, 1.041377, 1.205920, 2.387050",\ + "0.965982, 0.989673, 1.041377, 1.205920, 2.387050",\ + "0.965982, 0.989673, 1.041377, 1.205920, 2.387050"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "590007.000000, 590007.000000, 590007.062500, 590007.125000, 590007.625000",\ + "590007.125000, 590007.125000, 590007.187500, 590007.250000, 590007.750000",\ + "590007.250000, 590007.250000, 590007.312500, 590007.375000, 590007.875000",\ + "590007.375000, 590007.375000, 590007.437500, 590007.500000, 590008.000000",\ + "590007.625000, 590007.625000, 590007.687500, 590007.750000, 590008.250000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571"); + } + + } /* end of arc padmux2ast_i[5]_clk_src_io_o_inv_min*/ + +} /* end of pin clk_src_io_o */ + +pin("clk_src_io_val_o") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.090214 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : clk_src_io_val_o; + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.349435, 0.390046, 0.472189, 0.746558, 1.641427",\ + "0.436833, 0.477444, 0.559587, 0.833956, 1.728824",\ + "0.517679, 0.558291, 0.640433, 0.914803, 1.809671",\ + "0.655812, 0.696423, 0.778566, 1.052935, 1.947804",\ + "0.895822, 0.936589, 1.018755, 1.291518, 2.187617"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.023045, 0.083902, 0.239677, 0.764755, 2.477069",\ + "0.023045, 0.083902, 0.239677, 0.764755, 2.477069",\ + "0.023045, 0.083902, 0.239677, 0.764755, 2.477069",\ + "0.023045, 0.083902, 0.239677, 0.764755, 2.477069",\ + "0.023045, 0.083902, 0.239677, 0.764756, 2.477069"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.392641, 0.430353, 0.490673, 0.680876, 1.305538",\ + "0.480039, 0.517751, 0.578071, 0.768273, 1.392936",\ + "0.560851, 0.598563, 0.658884, 0.849086, 1.473748",\ + "0.698861, 0.736574, 0.796894, 0.987096, 1.611758",\ + "0.919051, 0.956763, 1.017083, 1.207286, 1.831948"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.028953, 0.070788, 0.167469, 0.516472, 1.652650",\ + "0.028953, 0.070788, 0.167469, 0.516472, 1.652650",\ + "0.028953, 0.070788, 0.167469, 0.516472, 1.652650",\ + "0.028953, 0.070788, 0.167469, 0.516472, 1.652650",\ + "0.028953, 0.070788, 0.167469, 0.516472, 1.652650"); + } + + } /* end of arc clk_ast_ext_i_clk_src_io_val_o_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.222488, 0.262832, 0.344930, 0.617962, 1.516487",\ + "0.310677, 0.351020, 0.433119, 0.706150, 1.604676",\ + "0.398314, 0.438657, 0.520756, 0.793787, 1.692313",\ + "0.546582, 0.586925, 0.669023, 0.942055, 1.840581",\ + "0.781897, 0.822240, 0.904338, 1.177370, 2.075895"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.021529, 0.083764, 0.238778, 0.757629, 2.456834",\ + "0.021529, 0.083764, 0.238778, 0.757629, 2.456834",\ + "0.021529, 0.083764, 0.238778, 0.757629, 2.456834",\ + "0.021529, 0.083764, 0.238778, 0.757629, 2.456834",\ + "0.021529, 0.083764, 0.238778, 0.757629, 2.456834"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.263406, 0.301157, 0.361570, 0.551735, 1.176520",\ + "0.351595, 0.389345, 0.449758, 0.639924, 1.264709",\ + "0.439232, 0.476982, 0.537395, 0.727561, 1.352346",\ + "0.587500, 0.625250, 0.685663, 0.875828, 1.500613",\ + "0.814247, 0.851409, 0.911729, 1.102035, 1.725865"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.025912, 0.068635, 0.165828, 0.512808, 1.651582",\ + "0.025912, 0.068635, 0.165828, 0.512808, 1.651582",\ + "0.025912, 0.068635, 0.165828, 0.512808, 1.651582",\ + "0.025912, 0.068635, 0.165828, 0.512808, 1.651582",\ + "0.025912, 0.068635, 0.165828, 0.512808, 1.651582"); + } + + } /* end of arc clk_ast_ext_i_clk_src_io_val_o_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "970010.312500, 970010.375000, 970010.437500, 970010.750000, 970011.625000",\ + "970010.437500, 970010.500000, 970010.562500, 970010.875000, 970011.750000",\ + "970010.562500, 970010.625000, 970010.687500, 970011.000000, 970011.875000",\ + "970010.562500, 970010.625000, 970010.687500, 970011.000000, 970011.875000",\ + "970010.937500, 970011.000000, 970011.062500, 970011.375000, 970012.250000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.022870, 0.084359, 0.238855, 0.766786, 2.469430",\ + "0.022870, 0.084359, 0.238855, 0.766786, 2.469430",\ + "0.022870, 0.084359, 0.238855, 0.766786, 2.469430",\ + "0.022870, 0.084359, 0.238855, 0.766786, 2.469430",\ + "0.022870, 0.084359, 0.238855, 0.766786, 2.469430"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "970010.312500, 970010.375000, 970010.437500, 970010.625000, 970011.250000",\ + "970010.437500, 970010.500000, 970010.562500, 970010.750000, 970011.375000",\ + "970010.562500, 970010.625000, 970010.687500, 970010.875000, 970011.500000",\ + "970010.562500, 970010.625000, 970010.687500, 970010.875000, 970011.500000",\ + "970010.937500, 970011.000000, 970011.062500, 970011.250000, 970011.875000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.028495, 0.070786, 0.167370, 0.515896, 1.652424",\ + "0.028495, 0.070786, 0.167370, 0.515896, 1.652424",\ + "0.028495, 0.070786, 0.167370, 0.515896, 1.652424",\ + "0.028495, 0.070786, 0.167370, 0.515896, 1.652424",\ + "0.028495, 0.070786, 0.167370, 0.515896, 1.652424"); + } + + } /* end of arc clk_ast_tlul_i_clk_src_io_val_o_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.691562, 0.732168, 0.814319, 1.088582, 1.983787",\ + "0.779362, 0.819968, 0.902120, 1.176383, 2.071587",\ + "0.860662, 0.901268, 0.983419, 1.257682, 2.152886",\ + "0.918815, 0.959421, 1.041572, 1.315835, 2.211040",\ + "1.227535, 1.268142, 1.350293, 1.624556, 2.519760"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.021561, 0.083764, 0.238778, 0.757109, 2.460111",\ + "0.021561, 0.083764, 0.238778, 0.757109, 2.460111",\ + "0.021561, 0.083764, 0.238778, 0.757109, 2.460111",\ + "0.021561, 0.083764, 0.238778, 0.757109, 2.460111",\ + "0.021561, 0.083764, 0.238778, 0.757109, 2.460111"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.670852, 0.708006, 0.768329, 0.958648, 1.582536",\ + "0.758652, 0.795807, 0.856129, 1.046448, 1.670336",\ + "0.839952, 0.877106, 0.937428, 1.127748, 1.751636",\ + "0.898105, 0.935259, 0.995582, 1.185901, 1.809789",\ + "1.206825, 1.243980, 1.304302, 1.494621, 2.118509"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.025902, 0.068641, 0.165825, 0.512797, 1.652262",\ + "0.025902, 0.068641, 0.165825, 0.512797, 1.652262",\ + "0.025902, 0.068641, 0.165825, 0.512797, 1.652262",\ + "0.025902, 0.068641, 0.165825, 0.512797, 1.652262",\ + "0.025902, 0.068641, 0.165825, 0.512797, 1.652262"); + } + + } /* end of arc clk_ast_tlul_i_clk_src_io_val_o_redg_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "970007.125000, 970007.125000, 970007.250000, 970007.500000, 970008.375000",\ + "970007.250000, 970007.250000, 970007.375000, 970007.625000, 970008.500000",\ + "970007.250000, 970007.250000, 970007.375000, 970007.625000, 970008.500000",\ + "970007.500000, 970007.500000, 970007.625000, 970007.875000, 970008.750000",\ + "970007.750000, 970007.750000, 970007.875000, 970008.125000, 970009.000000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.022870, 0.084359, 0.238855, 0.766786, 2.469430",\ + "0.022870, 0.084359, 0.238855, 0.766786, 2.469430",\ + "0.022870, 0.084359, 0.238855, 0.766786, 2.469430",\ + "0.022870, 0.084359, 0.238855, 0.766786, 2.469430",\ + "0.022870, 0.084359, 0.238855, 0.766786, 2.469430"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "970010.187500, 970010.250000, 970010.312500, 970010.500000, 970011.125000",\ + "970010.312500, 970010.375000, 970010.437500, 970010.625000, 970011.250000",\ + "970010.437500, 970010.500000, 970010.562500, 970010.750000, 970011.375000",\ + "970010.687500, 970010.750000, 970010.812500, 970011.000000, 970011.625000",\ + "970010.937500, 970011.000000, 970011.062500, 970011.250000, 970011.875000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.028495, 0.070786, 0.167370, 0.515896, 1.652424",\ + "0.028495, 0.070786, 0.167370, 0.515896, 1.652424",\ + "0.028495, 0.070786, 0.167370, 0.515896, 1.652424",\ + "0.028495, 0.070786, 0.167370, 0.515896, 1.652424",\ + "0.028495, 0.070786, 0.167370, 0.515896, 1.652424"); + } + + } /* end of arc padmux2ast_i[4]_clk_src_io_val_o_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "380000.437500, 380000.500000, 380000.562500, 380000.843750, 380001.750000",\ + "380000.531250, 380000.593750, 380000.656250, 380000.937500, 380001.843750",\ + "380000.593750, 380000.656250, 380000.718750, 380001.000000, 380001.906250",\ + "380000.750000, 380000.812500, 380000.875000, 380001.156250, 380002.062500",\ + "380000.968750, 380001.031250, 380001.093750, 380001.375000, 380002.281250"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.021561, 0.083764, 0.238778, 0.757109, 2.460111",\ + "0.021561, 0.083764, 0.238778, 0.757109, 2.460111",\ + "0.021561, 0.083764, 0.238778, 0.757109, 2.460111",\ + "0.021561, 0.083764, 0.238778, 0.757109, 2.460111",\ + "0.021561, 0.083764, 0.238778, 0.757109, 2.460111"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "380001.875000, 380001.906250, 380001.968750, 380002.156250, 380002.781250",\ + "380001.968750, 380002.000000, 380002.062500, 380002.250000, 380002.875000",\ + "380002.062500, 380002.093750, 380002.156250, 380002.343750, 380002.968750",\ + "380002.250000, 380002.281250, 380002.343750, 380002.531250, 380003.156250",\ + "380002.500000, 380002.531250, 380002.593750, 380002.781250, 380003.406250"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.025902, 0.068641, 0.165825, 0.512797, 1.652262",\ + "0.025902, 0.068641, 0.165825, 0.512797, 1.652262",\ + "0.025902, 0.068641, 0.165825, 0.512797, 1.652262",\ + "0.025902, 0.068641, 0.165825, 0.512797, 1.652262",\ + "0.025902, 0.068641, 0.165825, 0.512797, 1.652262"); + } + + } /* end of arc padmux2ast_i[4]_clk_src_io_val_o_una_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "970007.125000, 970007.187500, 970007.250000, 970007.437500, 970008.062500",\ + "970007.250000, 970007.312500, 970007.375000, 970007.562500, 970008.187500",\ + "970007.250000, 970007.312500, 970007.375000, 970007.562500, 970008.187500",\ + "970007.500000, 970007.562500, 970007.625000, 970007.812500, 970008.437500",\ + "970007.750000, 970007.812500, 970007.875000, 970008.062500, 970008.687500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.028495, 0.070786, 0.167370, 0.515896, 1.652424",\ + "0.028495, 0.070786, 0.167370, 0.515896, 1.652424",\ + "0.028495, 0.070786, 0.167370, 0.515896, 1.652424",\ + "0.028495, 0.070786, 0.167370, 0.515896, 1.652424",\ + "0.028495, 0.070786, 0.167370, 0.515896, 1.652424"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "970010.187500, 970010.250000, 970010.312500, 970010.625000, 970011.500000",\ + "970010.312500, 970010.375000, 970010.437500, 970010.750000, 970011.625000",\ + "970010.437500, 970010.500000, 970010.562500, 970010.875000, 970011.750000",\ + "970010.687500, 970010.750000, 970010.812500, 970011.125000, 970012.000000",\ + "970010.937500, 970011.000000, 970011.062500, 970011.375000, 970012.250000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.022870, 0.084359, 0.238855, 0.766786, 2.469430",\ + "0.022870, 0.084359, 0.238855, 0.766786, 2.469430",\ + "0.022870, 0.084359, 0.238855, 0.766786, 2.469430",\ + "0.022870, 0.084359, 0.238855, 0.766786, 2.469430",\ + "0.022870, 0.084359, 0.238855, 0.766786, 2.469430"); + } + + } /* end of arc padmux2ast_i[4]_clk_src_io_val_o_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "380000.500000, 380000.531250, 380000.593750, 380000.781250, 380001.406250",\ + "380000.593750, 380000.625000, 380000.687500, 380000.875000, 380001.500000",\ + "380000.656250, 380000.687500, 380000.750000, 380000.937500, 380001.562500",\ + "380000.812500, 380000.843750, 380000.906250, 380001.093750, 380001.718750",\ + "380001.031250, 380001.062500, 380001.125000, 380001.312500, 380001.937500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.025902, 0.068641, 0.165825, 0.512797, 1.652262",\ + "0.025902, 0.068641, 0.165825, 0.512797, 1.652262",\ + "0.025902, 0.068641, 0.165825, 0.512797, 1.652262",\ + "0.025902, 0.068641, 0.165825, 0.512797, 1.652262",\ + "0.025902, 0.068641, 0.165825, 0.512797, 1.652262"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "380001.906250, 380001.937500, 380002.031250, 380002.281250, 380003.187500",\ + "380002.000000, 380002.031250, 380002.125000, 380002.375000, 380003.281250",\ + "380002.093750, 380002.125000, 380002.218750, 380002.468750, 380003.375000",\ + "380002.281250, 380002.312500, 380002.406250, 380002.656250, 380003.562500",\ + "380002.531250, 380002.562500, 380002.656250, 380002.906250, 380003.812500"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.021561, 0.083764, 0.238778, 0.757109, 2.460111",\ + "0.021561, 0.083764, 0.238778, 0.757109, 2.460111",\ + "0.021561, 0.083764, 0.238778, 0.757109, 2.460111",\ + "0.021561, 0.083764, 0.238778, 0.757109, 2.460111",\ + "0.021561, 0.083764, 0.238778, 0.757109, 2.460111"); + } + + } /* end of arc padmux2ast_i[4]_clk_src_io_val_o_inv_min*/ + + timing () { + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "590008.562500, 590008.625000, 590008.687500, 590009.000000, 590009.875000",\ + "590008.687500, 590008.750000, 590008.812500, 590009.125000, 590010.000000",\ + "590008.687500, 590008.750000, 590008.812500, 590009.125000, 590010.000000",\ + "590008.812500, 590008.875000, 590008.937500, 590009.250000, 590010.125000",\ + "590009.062500, 590009.125000, 590009.187500, 590009.500000, 590010.375000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.022871, 0.084359, 0.238855, 0.766810, 2.469430",\ + "0.022871, 0.084359, 0.238855, 0.766810, 2.469430",\ + "0.022871, 0.084359, 0.238855, 0.766810, 2.469430",\ + "0.022871, 0.084359, 0.238855, 0.766810, 2.469430",\ + "0.022871, 0.084359, 0.238855, 0.766810, 2.469430"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "590006.875000, 590006.937500, 590007.000000, 590007.187500, 590007.812500",\ + "590007.000000, 590007.062500, 590007.125000, 590007.312500, 590007.937500",\ + "590007.125000, 590007.187500, 590007.250000, 590007.437500, 590008.062500",\ + "590007.250000, 590007.312500, 590007.375000, 590007.562500, 590008.187500",\ + "590007.625000, 590007.687500, 590007.750000, 590007.937500, 590008.562500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.028495, 0.070786, 0.167370, 0.515903, 1.652424",\ + "0.028495, 0.070786, 0.167370, 0.515903, 1.652424",\ + "0.028495, 0.070786, 0.167370, 0.515903, 1.652424",\ + "0.028495, 0.070786, 0.167370, 0.515903, 1.652424",\ + "0.028495, 0.070786, 0.167370, 0.515903, 1.652424"); + } + + } /* end of arc padmux2ast_i[5]_clk_src_io_val_o_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "590008.375000, 590008.437500, 590008.500000, 590008.812500, 590009.687500",\ + "590008.375000, 590008.437500, 590008.500000, 590008.812500, 590009.687500",\ + "590008.500000, 590008.562500, 590008.625000, 590008.937500, 590009.812500",\ + "590008.625000, 590008.687500, 590008.750000, 590009.062500, 590009.937500",\ + "590008.875000, 590008.937500, 590009.000000, 590009.312500, 590010.187500"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.022032, 0.083764, 0.238625, 0.755849, 2.465788",\ + "0.022032, 0.083764, 0.238625, 0.755849, 2.465788",\ + "0.022032, 0.083764, 0.238625, 0.755849, 2.465788",\ + "0.022032, 0.083764, 0.238625, 0.755849, 2.465788",\ + "0.022032, 0.083764, 0.238625, 0.755849, 2.465788"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "590006.750000, 590006.750000, 590006.812500, 590007.000000, 590007.625000",\ + "590006.875000, 590006.875000, 590006.937500, 590007.125000, 590007.750000",\ + "590007.000000, 590007.000000, 590007.062500, 590007.250000, 590007.875000",\ + "590007.125000, 590007.125000, 590007.187500, 590007.375000, 590008.000000",\ + "590007.375000, 590007.375000, 590007.437500, 590007.625000, 590008.250000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.026015, 0.068726, 0.165865, 0.510718, 1.651078",\ + "0.026015, 0.068726, 0.165865, 0.510718, 1.651078",\ + "0.026015, 0.068726, 0.165865, 0.510718, 1.651078",\ + "0.026015, 0.068726, 0.165865, 0.510718, 1.651078",\ + "0.026015, 0.068726, 0.165865, 0.510718, 1.651078"); + } + + } /* end of arc padmux2ast_i[5]_clk_src_io_val_o_una_min*/ + + timing () { + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "590008.562500, 590008.625000, 590008.687500, 590008.875000, 590009.500000",\ + "590008.687500, 590008.750000, 590008.812500, 590009.000000, 590009.625000",\ + "590008.687500, 590008.750000, 590008.812500, 590009.000000, 590009.625000",\ + "590008.812500, 590008.875000, 590008.937500, 590009.125000, 590009.750000",\ + "590009.062500, 590009.125000, 590009.187500, 590009.375000, 590010.000000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.028495, 0.070786, 0.167370, 0.515903, 1.652424",\ + "0.028495, 0.070786, 0.167370, 0.515903, 1.652424",\ + "0.028495, 0.070786, 0.167370, 0.515903, 1.652424",\ + "0.028495, 0.070786, 0.167370, 0.515903, 1.652424",\ + "0.028495, 0.070786, 0.167370, 0.515903, 1.652424"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "590006.875000, 590006.875000, 590007.000000, 590007.250000, 590008.125000",\ + "590007.000000, 590007.000000, 590007.125000, 590007.375000, 590008.250000",\ + "590007.125000, 590007.125000, 590007.250000, 590007.500000, 590008.375000",\ + "590007.250000, 590007.250000, 590007.375000, 590007.625000, 590008.500000",\ + "590007.625000, 590007.625000, 590007.750000, 590008.000000, 590008.875000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.022871, 0.084359, 0.238855, 0.766810, 2.469430",\ + "0.022871, 0.084359, 0.238855, 0.766810, 2.469430",\ + "0.022871, 0.084359, 0.238855, 0.766810, 2.469430",\ + "0.022871, 0.084359, 0.238855, 0.766810, 2.469430",\ + "0.022871, 0.084359, 0.238855, 0.766810, 2.469430"); + } + + } /* end of arc padmux2ast_i[5]_clk_src_io_val_o_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "590008.562500, 590008.625000, 590008.687500, 590008.875000, 590009.500000",\ + "590008.562500, 590008.625000, 590008.687500, 590008.875000, 590009.500000",\ + "590008.687500, 590008.750000, 590008.812500, 590009.000000, 590009.625000",\ + "590008.812500, 590008.875000, 590008.937500, 590009.125000, 590009.750000",\ + "590009.062500, 590009.125000, 590009.187500, 590009.375000, 590010.000000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.026015, 0.068726, 0.165865, 0.510718, 1.651078",\ + "0.026015, 0.068726, 0.165865, 0.510718, 1.651078",\ + "0.026015, 0.068726, 0.165865, 0.510718, 1.651078",\ + "0.026015, 0.068726, 0.165865, 0.510718, 1.651078",\ + "0.026015, 0.068726, 0.165865, 0.510718, 1.651078"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "590006.875000, 590006.875000, 590007.000000, 590007.250000, 590008.125000",\ + "590007.000000, 590007.000000, 590007.125000, 590007.375000, 590008.250000",\ + "590007.125000, 590007.125000, 590007.250000, 590007.500000, 590008.375000",\ + "590007.250000, 590007.250000, 590007.375000, 590007.625000, 590008.500000",\ + "590007.500000, 590007.500000, 590007.625000, 590007.875000, 590008.750000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.022032, 0.083764, 0.238625, 0.755849, 2.465788",\ + "0.022032, 0.083764, 0.238625, 0.755849, 2.465788",\ + "0.022032, 0.083764, 0.238625, 0.755849, 2.465788",\ + "0.022032, 0.083764, 0.238625, 0.755849, 2.465788",\ + "0.022032, 0.083764, 0.238625, 0.755849, 2.465788"); + } + + } /* end of arc padmux2ast_i[5]_clk_src_io_val_o_inv_min*/ + +} /* end of pin clk_src_io_val_o */ +bus ( clk_src_io_48m_o ) { + + bus_type : BUS4_type6 ; + direction : output ; + +pin("clk_src_io_48m_o[3]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.161713 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : clk_src_io_48m_o[3]; + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.100843, 0.266735, 0.427088, 0.747616, 1.388635",\ + "0.184687, 0.350464, 0.510809, 0.831717, 1.473578",\ + "0.260267, 0.426010, 0.586434, 0.907636, 1.550114",\ + "0.386507, 0.552662, 0.713534, 1.034573, 1.676504",\ + "0.580400, 0.747044, 0.907773, 1.228098, 1.868510"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015579, 0.316961, 0.624670, 1.238691, 2.466601",\ + "0.015665, 0.316961, 0.624670, 1.238691, 2.466601",\ + "0.015665, 0.317088, 0.625771, 1.239746, 2.466601",\ + "0.015838, 0.317088, 0.625771, 1.239746, 2.466601",\ + "0.016716, 0.317340, 0.625771, 1.239746, 2.466601"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.088041, 0.202376, 0.303813, 0.506089, 0.910516",\ + "0.168483, 0.282824, 0.383745, 0.585711, 0.989669",\ + "0.247358, 0.362640, 0.463376, 0.664815, 1.067688",\ + "0.380658, 0.500049, 0.601022, 0.802517, 1.205414",\ + "0.586485, 0.719001, 0.819955, 1.021830, 1.425575"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015700, 0.193950, 0.379890, 0.747742, 1.482887",\ + "0.016044, 0.193950, 0.379890, 0.747742, 1.485202",\ + "0.017520, 0.193950, 0.379890, 0.747742, 1.485202",\ + "0.022344, 0.194037, 0.379890, 0.747742, 1.485202",\ + "0.034639, 0.196727, 0.379890, 0.748439, 1.491839"); + } + + } /* end of arc clk_ast_ext_i_clk_src_io_48m_o[3]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.100718, 0.266618, 0.426903, 0.747412, 1.388420",\ + "0.184686, 0.350463, 0.510806, 0.831715, 1.473578",\ + "0.260208, 0.425985, 0.586426, 0.907607, 1.550030",\ + "0.386259, 0.552119, 0.712336, 1.032993, 1.674352",\ + "0.580173, 0.746795, 0.907585, 1.227594, 1.867283"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015496, 0.316821, 0.622606, 1.236473, 2.462725",\ + "0.015496, 0.316821, 0.622606, 1.236473, 2.462725",\ + "0.015496, 0.316929, 0.622606, 1.236473, 2.462725",\ + "0.015814, 0.316929, 0.622606, 1.236473, 2.462725",\ + "0.016700, 0.316929, 0.623370, 1.236473, 2.462725"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.087868, 0.202376, 0.303809, 0.506029, 0.910334",\ + "0.168483, 0.282824, 0.383745, 0.585711, 0.989669",\ + "0.247358, 0.362640, 0.463376, 0.664779, 1.067573",\ + "0.380658, 0.500049, 0.601022, 0.802517, 1.205414",\ + "0.586485, 0.718955, 0.819794, 1.021516, 1.424967"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015619, 0.192979, 0.376641, 0.744531, 1.480142",\ + "0.016032, 0.192979, 0.376641, 0.744531, 1.480142",\ + "0.017339, 0.192979, 0.376641, 0.744531, 1.480142",\ + "0.022190, 0.193551, 0.376842, 0.744531, 1.480142",\ + "0.033893, 0.196557, 0.377640, 0.746288, 1.484937"); + } + + } /* end of arc clk_ast_ext_i_clk_src_io_48m_o[3]_redg_min*/ + + timing () { + related_pin : "clk_src_io_o" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.103995, 0.269872, 0.430200, 0.750758, 1.391853",\ + "0.158337, 0.324154, 0.484388, 0.804979, 1.446186",\ + "0.282603, 0.448419, 0.608923, 0.930096, 1.572477",\ + "0.334665, 0.500651, 0.661339, 0.982445, 1.624600",\ + "0.580400, 0.747044, 0.907773, 1.228098, 1.868510"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015542, 0.317035, 0.624600, 1.238588, 2.466325",\ + "0.015645, 0.317035, 0.624600, 1.238588, 2.466325",\ + "0.015645, 0.317066, 0.625211, 1.239292, 2.466325",\ + "0.015655, 0.317066, 0.625211, 1.239292, 2.466325",\ + "0.016716, 0.317340, 0.625211, 1.239292, 2.466325"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.090477, 0.204718, 0.305888, 0.507773, 0.911447",\ + "0.141442, 0.255688, 0.356617, 0.558511, 0.962305",\ + "0.270943, 0.386953, 0.487730, 0.689180, 1.092056",\ + "0.325917, 0.443620, 0.544496, 0.745968, 1.148855",\ + "0.586485, 0.719001, 0.819955, 1.021830, 1.425575"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015734, 0.193610, 0.378735, 0.747021, 1.483183",\ + "0.015916, 0.193610, 0.378735, 0.747293, 1.484513",\ + "0.018374, 0.193610, 0.378735, 0.747293, 1.484513",\ + "0.020363, 0.193614, 0.378735, 0.747293, 1.484513",\ + "0.034639, 0.196727, 0.378735, 0.748439, 1.491839"); + } + + } /* end of arc clk_src_io_o_clk_src_io_48m_o[3]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_src_io_o" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.103875, 0.269735, 0.430056, 0.750620, 1.391729",\ + "0.158336, 0.324133, 0.484382, 0.804893, 1.445917",\ + "0.282510, 0.448302, 0.608704, 0.929792, 1.572026",\ + "0.333572, 0.499397, 0.659708, 0.980584, 1.622387",\ + "0.580173, 0.746795, 0.907585, 1.227594, 1.867283"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015480, 0.316838, 0.623370, 1.236473, 2.462725",\ + "0.015480, 0.316838, 0.623370, 1.236473, 2.462725",\ + "0.015480, 0.316929, 0.623370, 1.236473, 2.462725",\ + "0.015652, 0.316929, 0.623370, 1.236473, 2.462725",\ + "0.016700, 0.316929, 0.623370, 1.236473, 2.462725"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.090378, 0.204717, 0.305882, 0.507735, 0.911343",\ + "0.141442, 0.255688, 0.356617, 0.558510, 0.962304",\ + "0.270943, 0.386953, 0.487730, 0.689150, 1.091961",\ + "0.324941, 0.442615, 0.543488, 0.744945, 1.147798",\ + "0.586485, 0.718955, 0.819794, 1.021516, 1.424967"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015687, 0.193080, 0.376676, 0.744928, 1.481536",\ + "0.015912, 0.193080, 0.376676, 0.744928, 1.481536",\ + "0.018197, 0.193080, 0.376676, 0.744928, 1.481536",\ + "0.020162, 0.193312, 0.376758, 0.744928, 1.481536",\ + "0.033893, 0.196557, 0.377640, 0.746288, 1.484937"); + } + + } /* end of arc clk_src_io_o_clk_src_io_48m_o[3]_redg_min*/ + +} /* end of pin clk_src_io_48m_o[3] */ + +pin("clk_src_io_48m_o[2]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.158177 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : clk_src_io_48m_o[2]; + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.055481, 0.185725, 0.392886, 0.714270, 1.356390",\ + "0.142013, 0.273097, 0.480288, 0.802449, 1.446276",\ + "0.227644, 0.367997, 0.574907, 0.896875, 1.540369",\ + "0.372058, 0.538899, 0.745297, 1.066605, 1.708810",\ + "0.601931, 0.834236, 1.042645, 1.363437, 2.003839"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.021797, 0.238359, 0.631876, 1.247087, 2.477274",\ + "0.025516, 0.238359, 0.631876, 1.247087, 2.477274",\ + "0.039138, 0.240277, 0.631876, 1.247087, 2.477473",\ + "0.067159, 0.248694, 0.631876, 1.247087, 2.479640",\ + "0.123088, 0.289704, 0.642858, 1.251241, 2.479640"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.082179, 0.183018, 0.316461, 0.522191, 0.932963",\ + "0.170164, 0.270956, 0.404436, 0.610175, 1.020954",\ + "0.251445, 0.351944, 0.485256, 0.690977, 1.101771",\ + "0.388999, 0.491163, 0.624361, 0.829801, 1.240010",\ + "0.607343, 0.718683, 0.852150, 1.057410, 1.467133"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.025565, 0.151628, 0.387851, 0.763293, 1.515348",\ + "0.025565, 0.151804, 0.389259, 0.763293, 1.515348",\ + "0.025976, 0.151804, 0.389479, 0.764390, 1.515348",\ + "0.029120, 0.151804, 0.389479, 0.764390, 1.515348",\ + "0.041734, 0.154598, 0.389479, 0.764390, 1.515348"); + } + + } /* end of arc clk_ast_ext_i_clk_src_io_48m_o[2]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.055478, 0.185724, 0.392885, 0.714263, 1.356368",\ + "0.141644, 0.273073, 0.480017, 0.801359, 1.443459",\ + "0.227644, 0.367995, 0.574890, 0.896861, 1.540369",\ + "0.372055, 0.538895, 0.745296, 1.066605, 1.708810",\ + "0.601899, 0.834203, 1.042596, 1.363402, 2.003839"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.021795, 0.238265, 0.630524, 1.245754, 2.477107",\ + "0.025501, 0.238265, 0.630524, 1.245754, 2.477170",\ + "0.039138, 0.240263, 0.630524, 1.245754, 2.477473",\ + "0.067158, 0.248694, 0.630752, 1.245754, 2.478674",\ + "0.122913, 0.289395, 0.639350, 1.248196, 2.478674"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.082179, 0.183018, 0.316461, 0.522190, 0.932959",\ + "0.170151, 0.270913, 0.404355, 0.610080, 1.020840",\ + "0.251186, 0.351686, 0.484981, 0.690703, 1.101507",\ + "0.388979, 0.491150, 0.624343, 0.829707, 1.239752",\ + "0.607308, 0.718634, 0.852099, 1.057372, 1.467127"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.025557, 0.151128, 0.387354, 0.761934, 1.510661",\ + "0.025557, 0.151128, 0.387354, 0.761934, 1.510661",\ + "0.025965, 0.151128, 0.387354, 0.761934, 1.511090",\ + "0.029101, 0.151585, 0.387354, 0.761934, 1.511090",\ + "0.041668, 0.154530, 0.388178, 0.761934, 1.511090"); + } + + } /* end of arc clk_ast_ext_i_clk_src_io_48m_o[2]_redg_min*/ + + timing () { + related_pin : "clk_src_io_o" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.058414, 0.188667, 0.395813, 0.717110, 1.359045",\ + "0.112550, 0.243041, 0.450135, 0.772138, 1.415649",\ + "0.253196, 0.398235, 0.605055, 0.926906, 1.570171",\ + "0.312752, 0.468715, 0.675324, 0.996903, 1.639637",\ + "0.601931, 0.834236, 1.042645, 1.363437, 2.003839"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.021790, 0.238360, 0.631894, 1.247121, 2.477336",\ + "0.023317, 0.238360, 0.631894, 1.247121, 2.477336",\ + "0.044096, 0.241766, 0.631894, 1.247121, 2.477920",\ + "0.055652, 0.245238, 0.631894, 1.247121, 2.478962",\ + "0.123088, 0.289704, 0.642858, 1.251241, 2.479640"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.085404, 0.186224, 0.319679, 0.525413, 0.936188",\ + "0.141978, 0.242754, 0.376239, 0.581985, 0.992777",\ + "0.275783, 0.376576, 0.509868, 0.715539, 1.126231",\ + "0.332511, 0.433991, 0.567236, 0.772791, 1.183241",\ + "0.607343, 0.718683, 0.852150, 1.057410, 1.467133"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.025646, 0.151693, 0.388430, 0.763132, 1.513362",\ + "0.025646, 0.151849, 0.389568, 0.763815, 1.513362",\ + "0.026529, 0.151849, 0.389568, 0.764056, 1.513362",\ + "0.027825, 0.151849, 0.389568, 0.764056, 1.513362",\ + "0.041734, 0.154598, 0.389568, 0.764056, 1.513362"); + } + + } /* end of arc clk_src_io_o_clk_src_io_48m_o[2]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_src_io_o" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.058410, 0.188665, 0.395812, 0.717100, 1.359014",\ + "0.112399, 0.243028, 0.450025, 0.771635, 1.414310",\ + "0.253195, 0.398233, 0.605040, 0.926895, 1.570171",\ + "0.311693, 0.467461, 0.674069, 0.995655, 1.638404",\ + "0.601899, 0.834203, 1.042596, 1.363402, 2.003839"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.021782, 0.238225, 0.630549, 1.245808, 2.476689",\ + "0.023311, 0.238225, 0.630549, 1.245808, 2.476689",\ + "0.044096, 0.241755, 0.630564, 1.245808, 2.477789",\ + "0.055446, 0.245170, 0.630656, 1.245808, 2.478512",\ + "0.122913, 0.289395, 0.639350, 1.248196, 2.478674"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.085404, 0.186224, 0.319679, 0.525413, 0.936188",\ + "0.141970, 0.242733, 0.376196, 0.581868, 0.992503",\ + "0.275567, 0.376362, 0.509639, 0.715298, 1.125968",\ + "0.331384, 0.432856, 0.566092, 0.771606, 1.181968",\ + "0.607308, 0.718634, 0.852099, 1.057372, 1.467127"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.025646, 0.151208, 0.387784, 0.761934, 1.511090",\ + "0.025646, 0.151208, 0.387784, 0.761934, 1.511090",\ + "0.026523, 0.151208, 0.387784, 0.761934, 1.511090",\ + "0.027795, 0.151394, 0.387784, 0.761934, 1.511090",\ + "0.041668, 0.154530, 0.388178, 0.761934, 1.511090"); + } + + } /* end of arc clk_src_io_o_clk_src_io_48m_o[2]_redg_min*/ + +} /* end of pin clk_src_io_48m_o[2] */ + +pin("clk_src_io_48m_o[1]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.158177 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : clk_src_io_48m_o[1]; + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.055481, 0.185725, 0.392886, 0.714270, 1.356390",\ + "0.142013, 0.273097, 0.480288, 0.802449, 1.446276",\ + "0.227644, 0.367997, 0.574907, 0.896875, 1.540369",\ + "0.372058, 0.538899, 0.745297, 1.066605, 1.708810",\ + "0.601931, 0.834236, 1.042645, 1.363437, 2.003839"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.021797, 0.238359, 0.631876, 1.247087, 2.477274",\ + "0.025516, 0.238359, 0.631876, 1.247087, 2.477274",\ + "0.039138, 0.240277, 0.631876, 1.247087, 2.477473",\ + "0.067159, 0.248694, 0.631876, 1.247087, 2.479640",\ + "0.123088, 0.289704, 0.642858, 1.251241, 2.479640"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.082179, 0.183018, 0.316461, 0.522191, 0.932963",\ + "0.170164, 0.270956, 0.404436, 0.610175, 1.020954",\ + "0.251445, 0.351944, 0.485256, 0.690977, 1.101771",\ + "0.388999, 0.491163, 0.624361, 0.829801, 1.240010",\ + "0.607343, 0.718683, 0.852150, 1.057410, 1.467133"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.025565, 0.151628, 0.387851, 0.763293, 1.515348",\ + "0.025565, 0.151804, 0.389259, 0.763293, 1.515348",\ + "0.025976, 0.151804, 0.389479, 0.764390, 1.515348",\ + "0.029120, 0.151804, 0.389479, 0.764390, 1.515348",\ + "0.041734, 0.154598, 0.389479, 0.764390, 1.515348"); + } + + } /* end of arc clk_ast_ext_i_clk_src_io_48m_o[1]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.055478, 0.185724, 0.392885, 0.714263, 1.356368",\ + "0.141644, 0.273073, 0.480017, 0.801359, 1.443459",\ + "0.227644, 0.367995, 0.574890, 0.896861, 1.540369",\ + "0.372055, 0.538895, 0.745296, 1.066605, 1.708810",\ + "0.601899, 0.834203, 1.042596, 1.363402, 2.003839"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.021795, 0.238265, 0.630524, 1.245754, 2.477107",\ + "0.025501, 0.238265, 0.630524, 1.245754, 2.477170",\ + "0.039138, 0.240263, 0.630524, 1.245754, 2.477473",\ + "0.067158, 0.248694, 0.630752, 1.245754, 2.478674",\ + "0.122913, 0.289395, 0.639350, 1.248196, 2.478674"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.082179, 0.183018, 0.316461, 0.522190, 0.932959",\ + "0.170151, 0.270913, 0.404355, 0.610080, 1.020840",\ + "0.251186, 0.351686, 0.484981, 0.690703, 1.101507",\ + "0.388979, 0.491150, 0.624343, 0.829707, 1.239752",\ + "0.607308, 0.718634, 0.852099, 1.057372, 1.467127"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.025557, 0.151128, 0.387354, 0.761934, 1.510661",\ + "0.025557, 0.151128, 0.387354, 0.761934, 1.510661",\ + "0.025965, 0.151128, 0.387354, 0.761934, 1.511090",\ + "0.029101, 0.151585, 0.387354, 0.761934, 1.511090",\ + "0.041668, 0.154530, 0.388178, 0.761934, 1.511090"); + } + + } /* end of arc clk_ast_ext_i_clk_src_io_48m_o[1]_redg_min*/ + + timing () { + related_pin : "clk_src_io_o" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.058414, 0.188667, 0.395813, 0.717110, 1.359045",\ + "0.112550, 0.243041, 0.450135, 0.772138, 1.415649",\ + "0.253196, 0.398235, 0.605055, 0.926906, 1.570171",\ + "0.312752, 0.468715, 0.675324, 0.996903, 1.639637",\ + "0.601931, 0.834236, 1.042645, 1.363437, 2.003839"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.021790, 0.238360, 0.631894, 1.247121, 2.477336",\ + "0.023317, 0.238360, 0.631894, 1.247121, 2.477336",\ + "0.044096, 0.241766, 0.631894, 1.247121, 2.477920",\ + "0.055652, 0.245238, 0.631894, 1.247121, 2.478962",\ + "0.123088, 0.289704, 0.642858, 1.251241, 2.479640"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.085404, 0.186224, 0.319679, 0.525413, 0.936188",\ + "0.141978, 0.242754, 0.376239, 0.581985, 0.992777",\ + "0.275783, 0.376576, 0.509868, 0.715539, 1.126231",\ + "0.332511, 0.433991, 0.567236, 0.772791, 1.183241",\ + "0.607343, 0.718683, 0.852150, 1.057410, 1.467133"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.025646, 0.151693, 0.388430, 0.763132, 1.513362",\ + "0.025646, 0.151849, 0.389568, 0.763815, 1.513362",\ + "0.026529, 0.151849, 0.389568, 0.764056, 1.513362",\ + "0.027825, 0.151849, 0.389568, 0.764056, 1.513362",\ + "0.041734, 0.154598, 0.389568, 0.764056, 1.513362"); + } + + } /* end of arc clk_src_io_o_clk_src_io_48m_o[1]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_src_io_o" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.058410, 0.188665, 0.395812, 0.717100, 1.359014",\ + "0.112399, 0.243028, 0.450025, 0.771635, 1.414310",\ + "0.253195, 0.398233, 0.605040, 0.926895, 1.570171",\ + "0.311693, 0.467461, 0.674069, 0.995655, 1.638404",\ + "0.601899, 0.834203, 1.042596, 1.363402, 2.003839"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.021782, 0.238225, 0.630549, 1.245808, 2.476689",\ + "0.023311, 0.238225, 0.630549, 1.245808, 2.476689",\ + "0.044096, 0.241755, 0.630564, 1.245808, 2.477789",\ + "0.055446, 0.245170, 0.630656, 1.245808, 2.478512",\ + "0.122913, 0.289395, 0.639350, 1.248196, 2.478674"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.085404, 0.186224, 0.319679, 0.525413, 0.936188",\ + "0.141970, 0.242733, 0.376196, 0.581868, 0.992503",\ + "0.275567, 0.376362, 0.509639, 0.715298, 1.125968",\ + "0.331384, 0.432856, 0.566092, 0.771606, 1.181968",\ + "0.607308, 0.718634, 0.852099, 1.057372, 1.467127"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.025646, 0.151208, 0.387784, 0.761934, 1.511090",\ + "0.025646, 0.151208, 0.387784, 0.761934, 1.511090",\ + "0.026523, 0.151208, 0.387784, 0.761934, 1.511090",\ + "0.027795, 0.151394, 0.387784, 0.761934, 1.511090",\ + "0.041668, 0.154530, 0.388178, 0.761934, 1.511090"); + } + + } /* end of arc clk_src_io_o_clk_src_io_48m_o[1]_redg_min*/ + +} /* end of pin clk_src_io_48m_o[1] */ + +pin("clk_src_io_48m_o[0]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.161713 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : clk_src_io_48m_o[0]; + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.100843, 0.266735, 0.427088, 0.747616, 1.388635",\ + "0.184687, 0.350464, 0.510809, 0.831717, 1.473578",\ + "0.260267, 0.426010, 0.586434, 0.907636, 1.550114",\ + "0.386507, 0.552662, 0.713534, 1.034573, 1.676504",\ + "0.580400, 0.747044, 0.907773, 1.228098, 1.868510"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015579, 0.316961, 0.624670, 1.238691, 2.466601",\ + "0.015665, 0.316961, 0.624670, 1.238691, 2.466601",\ + "0.015665, 0.317088, 0.625771, 1.239746, 2.466601",\ + "0.015838, 0.317088, 0.625771, 1.239746, 2.466601",\ + "0.016716, 0.317340, 0.625771, 1.239746, 2.466601"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.088041, 0.202376, 0.303813, 0.506089, 0.910516",\ + "0.168483, 0.282824, 0.383745, 0.585711, 0.989669",\ + "0.247358, 0.362640, 0.463376, 0.664815, 1.067688",\ + "0.380658, 0.500049, 0.601022, 0.802517, 1.205414",\ + "0.586485, 0.719001, 0.819955, 1.021830, 1.425575"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015700, 0.193950, 0.379890, 0.747742, 1.482887",\ + "0.016044, 0.193950, 0.379890, 0.747742, 1.485202",\ + "0.017520, 0.193950, 0.379890, 0.747742, 1.485202",\ + "0.022344, 0.194037, 0.379890, 0.747742, 1.485202",\ + "0.034639, 0.196727, 0.379890, 0.748439, 1.491839"); + } + + } /* end of arc clk_ast_ext_i_clk_src_io_48m_o[0]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.100718, 0.266618, 0.426903, 0.747412, 1.388420",\ + "0.184686, 0.350463, 0.510806, 0.831715, 1.473578",\ + "0.260208, 0.425985, 0.586426, 0.907607, 1.550030",\ + "0.386259, 0.552119, 0.712336, 1.032993, 1.674352",\ + "0.580173, 0.746795, 0.907585, 1.227594, 1.867283"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015496, 0.316821, 0.622606, 1.236473, 2.462725",\ + "0.015496, 0.316821, 0.622606, 1.236473, 2.462725",\ + "0.015496, 0.316929, 0.622606, 1.236473, 2.462725",\ + "0.015814, 0.316929, 0.622606, 1.236473, 2.462725",\ + "0.016700, 0.316929, 0.623370, 1.236473, 2.462725"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.087868, 0.202376, 0.303809, 0.506029, 0.910334",\ + "0.168483, 0.282824, 0.383745, 0.585711, 0.989669",\ + "0.247358, 0.362640, 0.463376, 0.664779, 1.067573",\ + "0.380658, 0.500049, 0.601022, 0.802517, 1.205414",\ + "0.586485, 0.718955, 0.819794, 1.021516, 1.424967"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015619, 0.192979, 0.376641, 0.744531, 1.480142",\ + "0.016032, 0.192979, 0.376641, 0.744531, 1.480142",\ + "0.017339, 0.192979, 0.376641, 0.744531, 1.480142",\ + "0.022190, 0.193551, 0.376842, 0.744531, 1.480142",\ + "0.033893, 0.196557, 0.377640, 0.746288, 1.484937"); + } + + } /* end of arc clk_ast_ext_i_clk_src_io_48m_o[0]_redg_min*/ + + timing () { + related_pin : "clk_src_io_o" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.103995, 0.269872, 0.430200, 0.750758, 1.391853",\ + "0.158337, 0.324154, 0.484388, 0.804979, 1.446186",\ + "0.282603, 0.448419, 0.608923, 0.930096, 1.572477",\ + "0.334665, 0.500651, 0.661339, 0.982445, 1.624600",\ + "0.580400, 0.747044, 0.907773, 1.228098, 1.868510"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015542, 0.317035, 0.624600, 1.238588, 2.466325",\ + "0.015645, 0.317035, 0.624600, 1.238588, 2.466325",\ + "0.015645, 0.317066, 0.625211, 1.239292, 2.466325",\ + "0.015655, 0.317066, 0.625211, 1.239292, 2.466325",\ + "0.016716, 0.317340, 0.625211, 1.239292, 2.466325"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.090477, 0.204718, 0.305888, 0.507773, 0.911447",\ + "0.141442, 0.255688, 0.356617, 0.558511, 0.962305",\ + "0.270943, 0.386953, 0.487730, 0.689180, 1.092056",\ + "0.325917, 0.443620, 0.544496, 0.745968, 1.148855",\ + "0.586485, 0.719001, 0.819955, 1.021830, 1.425575"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015734, 0.193610, 0.378735, 0.747021, 1.483183",\ + "0.015916, 0.193610, 0.378735, 0.747293, 1.484513",\ + "0.018374, 0.193610, 0.378735, 0.747293, 1.484513",\ + "0.020363, 0.193614, 0.378735, 0.747293, 1.484513",\ + "0.034639, 0.196727, 0.378735, 0.748439, 1.491839"); + } + + } /* end of arc clk_src_io_o_clk_src_io_48m_o[0]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_src_io_o" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.103875, 0.269735, 0.430056, 0.750620, 1.391729",\ + "0.158336, 0.324133, 0.484382, 0.804893, 1.445917",\ + "0.282510, 0.448302, 0.608704, 0.929792, 1.572026",\ + "0.333572, 0.499397, 0.659708, 0.980584, 1.622387",\ + "0.580173, 0.746795, 0.907585, 1.227594, 1.867283"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015480, 0.316838, 0.623370, 1.236473, 2.462725",\ + "0.015480, 0.316838, 0.623370, 1.236473, 2.462725",\ + "0.015480, 0.316929, 0.623370, 1.236473, 2.462725",\ + "0.015652, 0.316929, 0.623370, 1.236473, 2.462725",\ + "0.016700, 0.316929, 0.623370, 1.236473, 2.462725"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.090378, 0.204717, 0.305882, 0.507735, 0.911343",\ + "0.141442, 0.255688, 0.356617, 0.558510, 0.962304",\ + "0.270943, 0.386953, 0.487730, 0.689150, 1.091961",\ + "0.324941, 0.442615, 0.543488, 0.744945, 1.147798",\ + "0.586485, 0.718955, 0.819794, 1.021516, 1.424967"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015687, 0.193080, 0.376676, 0.744928, 1.481536",\ + "0.015912, 0.193080, 0.376676, 0.744928, 1.481536",\ + "0.018197, 0.193080, 0.376676, 0.744928, 1.481536",\ + "0.020162, 0.193312, 0.376758, 0.744928, 1.481536",\ + "0.033893, 0.196557, 0.377640, 0.746288, 1.484937"); + } + + } /* end of arc clk_src_io_o_clk_src_io_48m_o[0]_redg_min*/ + +} /* end of pin clk_src_io_48m_o[0] */ +} /* end of bus clk_src_io_48m_o */ + +pin("usb_ref_pulse_i") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000498 ; + + /* Other user defined attributes. */ + original_pin : usb_ref_pulse_i; + timing () { + related_pin : "clk_ast_usb_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.601598, 0.562432, 0.511802, 0.512897, 0.526214",\ + "0.685611, 0.646445, 0.595815, 0.596911, 0.610227",\ + "0.776643, 0.737477, 0.686847, 0.687943, 0.701259",\ + "0.941188, 0.902022, 0.851392, 0.852488, 0.865804",\ + "1.218007, 1.178841, 1.128211, 1.129307, 1.142623"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.502275, 0.444594, 0.389492, 0.390588, 0.403904",\ + "0.590200, 0.532519, 0.477417, 0.478513, 0.491829",\ + "0.690598, 0.632917, 0.577816, 0.578911, 0.592227",\ + "0.875082, 0.817401, 0.762299, 0.763395, 0.776711",\ + "1.192023, 1.134342, 1.079240, 1.080336, 1.093652"); + } + + } /* end of arc clk_ast_usb_i_usb_ref_pulse_i_stupr*/ + + timing () { + related_pin : "clk_ast_usb_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.289933, -0.256850, -0.198215, -0.184587, -0.018969",\ + "-0.373947, -0.340864, -0.282229, -0.268602, -0.102983",\ + "-0.464983, -0.431900, -0.373265, -0.359637, -0.194019",\ + "-0.629535, -0.596452, -0.537817, -0.524189, -0.358571",\ + "-0.906192, -0.873109, -0.814474, -0.800846, -0.635228"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.244346, -0.193347, -0.096886, -0.078739, 0.141805",\ + "-0.332296, -0.281297, -0.184836, -0.166688, 0.053856",\ + "-0.432681, -0.381682, -0.285221, -0.267073, -0.046529",\ + "-0.616949, -0.565951, -0.469489, -0.451342, -0.230798",\ + "-0.933995, -0.882996, -0.786535, -0.768387, -0.547843"); + } + + } /* end of arc clk_ast_usb_i_usb_ref_pulse_i_hldr*/ + +} /* end of pin usb_ref_pulse_i */ + +pin("usb_ref_val_i") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000622 ; + + /* Other user defined attributes. */ + original_pin : usb_ref_val_i; + timing () { + related_pin : "clk_ast_usb_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.572947, 0.533781, 0.483152, 0.484247, 0.497563",\ + "0.655514, 0.616348, 0.565718, 0.566814, 0.580130",\ + "0.734317, 0.695151, 0.644522, 0.645617, 0.658933",\ + "0.870061, 0.830896, 0.780266, 0.781361, 0.794677",\ + "1.084318, 1.045152, 0.994522, 0.995618, 1.008934"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.471556, 0.413875, 0.358773, 0.359869, 0.373185",\ + "0.557541, 0.499860, 0.444758, 0.445854, 0.459170",\ + "0.648123, 0.590443, 0.535341, 0.536436, 0.549753",\ + "0.811397, 0.753716, 0.698614, 0.699710, 0.713026",\ + "1.086303, 1.028622, 0.973521, 0.974616, 0.987932"); + } + + } /* end of arc clk_ast_usb_i_usb_ref_val_i_stupr*/ + + timing () { + related_pin : "clk_ast_usb_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.261299, -0.228217, -0.169581, -0.155962, 0.009554",\ + "-0.343866, -0.310783, -0.252148, -0.238528, -0.073013",\ + "-0.422669, -0.389587, -0.330951, -0.317332, -0.151816",\ + "-0.558414, -0.525331, -0.466695, -0.453076, -0.287561",\ + "-0.772670, -0.739587, -0.680952, -0.667332, -0.501817"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.213704, -0.162701, -0.066223, -0.048077, 0.172450",\ + "-0.299689, -0.248686, -0.152209, -0.134063, 0.086465",\ + "-0.390272, -0.339269, -0.242791, -0.224645, -0.004118",\ + "-0.553545, -0.502542, -0.406065, -0.387919, -0.167392",\ + "-0.828451, -0.777448, -0.680971, -0.662825, -0.442298"); + } + + } /* end of arc clk_ast_usb_i_usb_ref_val_i_hldr*/ + +} /* end of pin usb_ref_val_i */ + +pin("clk_src_usb_en_i") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001677 ; + + /* Other user defined attributes. */ + original_pin : clk_src_usb_en_i; + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.200076, 0.146984, 0.107694, 0.090457, 0.087585",\ + "0.271588, 0.219415, 0.179927, 0.162045, 0.157577",\ + "0.363033, 0.310027, 0.270334, 0.252385, 0.247965",\ + "0.507780, 0.454308, 0.413646, 0.395357, 0.391106",\ + "0.811131, 0.757315, 0.714144, 0.694969, 0.691143"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.249331, 0.166333, 0.091045, 0.049669, 0.020498",\ + "0.324602, 0.241857, 0.166855, 0.126539, 0.100040",\ + "0.429418, 0.345854, 0.270221, 0.227986, 0.196782",\ + "0.605833, 0.521783, 0.445878, 0.397956, 0.350944",\ + "0.983325, 0.898854, 0.822917, 0.761117, 0.674795"); + } + + } /* end of arc clk_ast_ext_i_clk_src_usb_en_i_stupr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.096530, -0.053812, -0.018112, 0.032751, 0.135173",\ + "-0.166367, -0.123600, -0.088245, -0.037477, 0.065076",\ + "-0.251291, -0.208679, -0.174484, -0.124115, -0.021332",\ + "-0.373429, -0.330963, -0.299719, -0.251733, -0.152256",\ + "-0.620310, -0.578080, -0.553843, -0.512151, -0.422314"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.130907, -0.055165, 0.010770, 0.102409, 0.285045",\ + "-0.205839, -0.131127, -0.064641, 0.027653, 0.211502",\ + "-0.308157, -0.233980, -0.166224, -0.072248, 0.114884",\ + "-0.470591, -0.397956, -0.329423, -0.234665, -0.046227",\ + "-0.811364, -0.742478, -0.673228, -0.578223, -0.389923"); + } + + } /* end of arc clk_ast_ext_i_clk_src_usb_en_i_hldr*/ + +} /* end of pin clk_src_usb_en_i */ + +pin("clk_src_usb_o") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.069236 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : clk_src_usb_o; + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : falling_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "1.737872, 1.770095, 1.839437, 2.057034, 2.749000",\ + "1.737872, 1.770095, 1.839437, 2.057034, 2.749000",\ + "1.737872, 1.770095, 1.839437, 2.057034, 2.749000",\ + "1.737872, 1.770095, 1.839437, 2.057034, 2.749000",\ + "1.737872, 1.770095, 1.839437, 2.057034, 2.749000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.017599, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017599, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017599, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017599, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017599, 0.075142, 0.205270, 0.618216, 1.929571"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "1.568604, 1.612346, 1.706142, 2.005007, 2.947481",\ + "1.568604, 1.612346, 1.706142, 2.005007, 2.947481",\ + "1.568604, 1.612346, 1.706142, 2.005007, 2.947481",\ + "1.568604, 1.612346, 1.706142, 2.005007, 2.947481",\ + "1.568604, 1.612346, 1.706142, 2.005007, 2.947481"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\ + "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\ + "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\ + "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\ + "0.020388, 0.096008, 0.262833, 0.786379, 2.444935"); + } + + } /* end of arc clk_ast_ext_i_clk_src_usb_o_fedg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_ext_i" ; + timing_type : falling_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "1.093582, 1.125805, 1.195148, 1.412745, 2.104710",\ + "1.093582, 1.125805, 1.195148, 1.412745, 2.104710",\ + "1.093582, 1.125805, 1.195148, 1.412745, 2.104710",\ + "1.093582, 1.125805, 1.195148, 1.412745, 2.104710",\ + "1.093582, 1.125805, 1.195148, 1.412745, 2.104710"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017600, 0.075142, 0.205270, 0.618216, 1.929571"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "1.010551, 1.054292, 1.148088, 1.446953, 2.389427",\ + "1.010551, 1.054292, 1.148088, 1.446953, 2.389427",\ + "1.010551, 1.054292, 1.148088, 1.446953, 2.389427",\ + "1.010551, 1.054292, 1.148088, 1.446953, 2.389427",\ + "1.010551, 1.054292, 1.148088, 1.446953, 2.389427"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\ + "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\ + "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\ + "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\ + "0.020388, 0.096008, 0.262833, 0.786379, 2.444935"); + } + + } /* end of arc clk_ast_ext_i_clk_src_usb_o_fedg_min*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "1.101180, 1.133403, 1.202745, 1.420342, 2.112307",\ + "1.189325, 1.221548, 1.290891, 1.508488, 2.200453",\ + "1.285347, 1.317570, 1.386912, 1.604509, 2.296474",\ + "1.453311, 1.485534, 1.554876, 1.772473, 2.464438",\ + "1.727352, 1.759575, 1.828917, 2.046515, 2.738480"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.017599, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017599, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017599, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017599, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017599, 0.075142, 0.205270, 0.618216, 1.929571"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "1.029003, 1.072744, 1.166540, 1.465405, 2.407880",\ + "1.116853, 1.160595, 1.254391, 1.553256, 2.495730",\ + "1.198296, 1.242037, 1.335833, 1.634698, 2.577173",\ + "1.337780, 1.381521, 1.475317, 1.774182, 2.716657",\ + "1.565882, 1.609623, 1.703419, 2.002285, 2.944759"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\ + "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\ + "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\ + "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\ + "0.020388, 0.096008, 0.262833, 0.786379, 2.444935"); + } + + } /* end of arc clk_ast_ext_i_clk_src_usb_o_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "1.100277, 1.132500, 1.201842, 1.419439, 2.111404",\ + "1.188403, 1.220626, 1.289968, 1.507565, 2.199530",\ + "1.284444, 1.316668, 1.386010, 1.603607, 2.295572",\ + "1.452407, 1.484630, 1.553972, 1.771569, 2.463535",\ + "1.726368, 1.758591, 1.827933, 2.045531, 2.737496"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017600, 0.075142, 0.205270, 0.618216, 1.929571"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "1.026546, 1.070287, 1.164084, 1.462948, 2.405423",\ + "1.114365, 1.158106, 1.251902, 1.550767, 2.493242",\ + "1.195575, 1.239316, 1.333112, 1.631977, 2.574452",\ + "1.335306, 1.379047, 1.472843, 1.771708, 2.714183",\ + "1.563376, 1.607117, 1.700913, 1.999778, 2.942253"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\ + "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\ + "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\ + "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\ + "0.020388, 0.096008, 0.262833, 0.786379, 2.444935"); + } + + } /* end of arc clk_ast_ext_i_clk_src_usb_o_redg_min*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "1.641426, 1.673649, 1.742991, 1.960589, 2.652554",\ + "1.720995, 1.753218, 1.822561, 2.040158, 2.732123",\ + "1.800790, 1.833013, 1.902355, 2.119953, 2.811918",\ + "1.930632, 1.962856, 2.032198, 2.249795, 2.941760",\ + "2.130731, 2.162954, 2.232296, 2.449894, 3.141859"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.017599, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017599, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017599, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017599, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017599, 0.075142, 0.205270, 0.618216, 1.929571"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "1.423514, 1.467255, 1.561051, 1.859916, 2.802391",\ + "1.512686, 1.556427, 1.650223, 1.949089, 2.891563",\ + "1.603640, 1.647381, 1.741178, 2.040043, 2.982517",\ + "1.758735, 1.802476, 1.896272, 2.195137, 3.137612",\ + "2.011581, 2.055323, 2.149119, 2.447984, 3.390458"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\ + "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\ + "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\ + "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\ + "0.020388, 0.096008, 0.262833, 0.786379, 2.444935"); + } + + } /* end of arc clk_ast_ext_i_clk_src_usb_o_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_ext_i" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "1.625646, 1.657869, 1.727212, 1.944809, 2.636774",\ + "1.705396, 1.737619, 1.806961, 2.024558, 2.716523",\ + "1.780640, 1.812864, 1.882206, 2.099803, 2.791768",\ + "1.900872, 1.933095, 2.002438, 2.220035, 2.912000",\ + "2.084163, 2.116387, 2.185729, 2.403326, 3.095291"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017600, 0.075142, 0.205270, 0.618216, 1.929571"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "1.415430, 1.459171, 1.552967, 1.851832, 2.794307",\ + "1.503017, 1.546759, 1.640555, 1.939419, 2.881894",\ + "1.589827, 1.633568, 1.727364, 2.026229, 2.968703",\ + "1.739106, 1.782847, 1.876643, 2.175508, 3.117983",\ + "1.983528, 2.027269, 2.121065, 2.419930, 3.362405"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\ + "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\ + "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\ + "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\ + "0.020388, 0.096008, 0.262833, 0.786379, 2.444935"); + } + + } /* end of arc clk_ast_ext_i_clk_src_usb_o_una_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "970012.125000, 970012.187500, 970012.250000, 970012.437500, 970013.125000",\ + "970012.250000, 970012.312500, 970012.375000, 970012.562500, 970013.250000",\ + "970012.375000, 970012.437500, 970012.500000, 970012.687500, 970013.375000",\ + "970012.375000, 970012.437500, 970012.500000, 970012.687500, 970013.375000",\ + "970012.750000, 970012.812500, 970012.875000, 970013.062500, 970013.750000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.042128, 0.086864, 0.207230, 0.622005, 1.937878",\ + "0.042128, 0.086864, 0.207230, 0.622005, 1.937878",\ + "0.042128, 0.086864, 0.207230, 0.622005, 1.937878",\ + "0.042128, 0.086864, 0.207230, 0.622005, 1.937878",\ + "0.042128, 0.086864, 0.207230, 0.622005, 1.937878"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "970010.062500, 970010.062500, 970010.187500, 970010.500000, 970011.437500",\ + "970010.187500, 970010.187500, 970010.312500, 970010.625000, 970011.562500",\ + "970010.312500, 970010.312500, 970010.437500, 970010.750000, 970011.687500",\ + "970010.312500, 970010.312500, 970010.437500, 970010.750000, 970011.687500",\ + "970010.687500, 970010.687500, 970010.812500, 970011.125000, 970012.062500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.038124, 0.100137, 0.260986, 0.783299, 2.448362",\ + "0.038124, 0.100137, 0.260986, 0.783299, 2.448362",\ + "0.038124, 0.100137, 0.260986, 0.783299, 2.448362",\ + "0.038124, 0.100137, 0.260986, 0.783299, 2.448362",\ + "0.038124, 0.100137, 0.260986, 0.783299, 2.448362"); + } + + } /* end of arc clk_ast_tlul_i_clk_src_usb_o_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.559788, 0.592011, 0.660516, 0.878515, 1.570735",\ + "0.647589, 0.679811, 0.748316, 0.966316, 1.658535",\ + "0.728888, 0.761111, 0.829615, 1.047615, 1.739835",\ + "0.787041, 0.819264, 0.887769, 1.105768, 1.797988",\ + "1.095762, 1.127984, 1.196489, 1.414489, 2.106709"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017600, 0.075142, 0.205270, 0.618216, 1.929571"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.600873, 0.644670, 0.738286, 1.035322, 1.979740",\ + "0.688747, 0.732544, 0.826160, 1.123196, 2.067614",\ + "0.783083, 0.826880, 0.920496, 1.217532, 2.161950",\ + "0.850841, 0.894638, 0.988254, 1.285290, 2.229708",\ + "1.211540, 1.255336, 1.348952, 1.645988, 2.590406"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.020039, 0.095921, 0.259491, 0.781146, 2.444935",\ + "0.020039, 0.095921, 0.259491, 0.781146, 2.444935",\ + "0.020039, 0.095921, 0.259491, 0.781146, 2.444935",\ + "0.020039, 0.095921, 0.259491, 0.781146, 2.444935",\ + "0.020039, 0.095921, 0.259491, 0.781146, 2.444935"); + } + + } /* end of arc clk_ast_tlul_i_clk_src_usb_o_redg_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "970006.875000, 970006.875000, 970006.937500, 970007.187500, 970007.875000",\ + "970007.000000, 970007.000000, 970007.062500, 970007.312500, 970008.000000",\ + "970007.000000, 970007.000000, 970007.062500, 970007.312500, 970008.000000",\ + "970007.250000, 970007.250000, 970007.312500, 970007.562500, 970008.250000",\ + "970007.500000, 970007.500000, 970007.562500, 970007.812500, 970008.500000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.042128, 0.086864, 0.207230, 0.622005, 1.937878",\ + "0.042128, 0.086864, 0.207230, 0.622005, 1.937878",\ + "0.042128, 0.086864, 0.207230, 0.622005, 1.937878",\ + "0.042128, 0.086864, 0.207230, 0.622005, 1.937878",\ + "0.042128, 0.086864, 0.207230, 0.622005, 1.937878"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "970009.937500, 970009.937500, 970010.062500, 970010.375000, 970011.312500",\ + "970010.062500, 970010.062500, 970010.187500, 970010.500000, 970011.437500",\ + "970010.187500, 970010.187500, 970010.312500, 970010.625000, 970011.562500",\ + "970010.437500, 970010.437500, 970010.562500, 970010.875000, 970011.812500",\ + "970010.687500, 970010.687500, 970010.812500, 970011.125000, 970012.062500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.038124, 0.100137, 0.260986, 0.783299, 2.448362",\ + "0.038124, 0.100137, 0.260986, 0.783299, 2.448362",\ + "0.038124, 0.100137, 0.260986, 0.783299, 2.448362",\ + "0.038124, 0.100137, 0.260986, 0.783299, 2.448362",\ + "0.038124, 0.100137, 0.260986, 0.783299, 2.448362"); + } + + } /* end of arc padmux2ast_i[4]_clk_src_usb_o_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "380001.781250, 380001.812500, 380001.875000, 380002.093750, 380002.781250",\ + "380001.875000, 380001.906250, 380001.968750, 380002.187500, 380002.875000",\ + "380001.937500, 380001.968750, 380002.031250, 380002.250000, 380002.937500",\ + "380002.093750, 380002.125000, 380002.187500, 380002.406250, 380003.093750",\ + "380002.312500, 380002.343750, 380002.406250, 380002.625000, 380003.312500"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017600, 0.075142, 0.205270, 0.618216, 1.929571"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "380003.031250, 380003.062500, 380003.156250, 380003.468750, 380004.406250",\ + "380003.125000, 380003.156250, 380003.250000, 380003.562500, 380004.500000",\ + "380003.218750, 380003.250000, 380003.343750, 380003.656250, 380004.593750",\ + "380003.406250, 380003.437500, 380003.531250, 380003.843750, 380004.781250",\ + "380003.656250, 380003.687500, 380003.781250, 380004.093750, 380005.031250"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.020039, 0.095921, 0.259491, 0.781146, 2.444935",\ + "0.020039, 0.095921, 0.259491, 0.781146, 2.444935",\ + "0.020039, 0.095921, 0.259491, 0.781146, 2.444935",\ + "0.020039, 0.095921, 0.259491, 0.781146, 2.444935",\ + "0.020039, 0.095921, 0.259491, 0.781146, 2.444935"); + } + + } /* end of arc padmux2ast_i[4]_clk_src_usb_o_una_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "970008.625000, 970008.687500, 970008.750000, 970009.062500, 970010.000000",\ + "970008.750000, 970008.812500, 970008.875000, 970009.187500, 970010.125000",\ + "970008.750000, 970008.812500, 970008.875000, 970009.187500, 970010.125000",\ + "970009.000000, 970009.062500, 970009.125000, 970009.437500, 970010.375000",\ + "970009.250000, 970009.312500, 970009.375000, 970009.687500, 970010.625000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.038124, 0.100137, 0.260986, 0.783299, 2.448362",\ + "0.038124, 0.100137, 0.260986, 0.783299, 2.448362",\ + "0.038124, 0.100137, 0.260986, 0.783299, 2.448362",\ + "0.038124, 0.100137, 0.260986, 0.783299, 2.448362",\ + "0.038124, 0.100137, 0.260986, 0.783299, 2.448362"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "970012.000000, 970012.062500, 970012.125000, 970012.312500, 970013.000000",\ + "970012.125000, 970012.187500, 970012.250000, 970012.437500, 970013.125000",\ + "970012.250000, 970012.312500, 970012.375000, 970012.562500, 970013.250000",\ + "970012.500000, 970012.562500, 970012.625000, 970012.812500, 970013.500000",\ + "970012.750000, 970012.812500, 970012.875000, 970013.062500, 970013.750000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.042128, 0.086864, 0.207230, 0.622005, 1.937878",\ + "0.042128, 0.086864, 0.207230, 0.622005, 1.937878",\ + "0.042128, 0.086864, 0.207230, 0.622005, 1.937878",\ + "0.042128, 0.086864, 0.207230, 0.622005, 1.937878",\ + "0.042128, 0.086864, 0.207230, 0.622005, 1.937878"); + } + + } /* end of arc padmux2ast_i[4]_clk_src_usb_o_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "380000.343750, 380000.375000, 380000.468750, 380000.781250, 380001.718750",\ + "380000.437500, 380000.468750, 380000.562500, 380000.875000, 380001.812500",\ + "380000.500000, 380000.531250, 380000.625000, 380000.937500, 380001.875000",\ + "380000.656250, 380000.687500, 380000.781250, 380001.093750, 380002.031250",\ + "380000.875000, 380000.906250, 380001.000000, 380001.312500, 380002.250000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.020039, 0.095921, 0.259491, 0.781146, 2.444935",\ + "0.020039, 0.095921, 0.259491, 0.781146, 2.444935",\ + "0.020039, 0.095921, 0.259491, 0.781146, 2.444935",\ + "0.020039, 0.095921, 0.259491, 0.781146, 2.444935",\ + "0.020039, 0.095921, 0.259491, 0.781146, 2.444935"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "380001.750000, 380001.781250, 380001.843750, 380002.062500, 380002.750000",\ + "380001.843750, 380001.875000, 380001.937500, 380002.156250, 380002.843750",\ + "380001.937500, 380001.968750, 380002.031250, 380002.250000, 380002.937500",\ + "380002.125000, 380002.156250, 380002.218750, 380002.437500, 380003.125000",\ + "380002.375000, 380002.406250, 380002.468750, 380002.687500, 380003.375000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017600, 0.075142, 0.205270, 0.618216, 1.929571"); + } + + } /* end of arc padmux2ast_i[4]_clk_src_usb_o_inv_min*/ + + timing () { + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "590010.375000, 590010.437500, 590010.500000, 590010.687500, 590011.375000",\ + "590010.500000, 590010.562500, 590010.625000, 590010.812500, 590011.500000",\ + "590010.500000, 590010.562500, 590010.625000, 590010.812500, 590011.500000",\ + "590010.625000, 590010.687500, 590010.750000, 590010.937500, 590011.625000",\ + "590010.875000, 590010.937500, 590011.000000, 590011.187500, 590011.875000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.042077, 0.086820, 0.207230, 0.622005, 1.937878",\ + "0.042077, 0.086820, 0.207230, 0.622005, 1.937878",\ + "0.042077, 0.086820, 0.207230, 0.622005, 1.937878",\ + "0.042077, 0.086820, 0.207230, 0.622005, 1.937878",\ + "0.042077, 0.086820, 0.207230, 0.622005, 1.937878"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "590008.375000, 590008.437500, 590008.500000, 590008.812500, 590009.750000",\ + "590008.500000, 590008.562500, 590008.625000, 590008.937500, 590009.875000",\ + "590008.625000, 590008.687500, 590008.750000, 590009.062500, 590010.000000",\ + "590008.750000, 590008.812500, 590008.875000, 590009.187500, 590010.125000",\ + "590009.125000, 590009.187500, 590009.250000, 590009.562500, 590010.500000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.038124, 0.100137, 0.260980, 0.783299, 2.448362",\ + "0.038124, 0.100137, 0.260980, 0.783299, 2.448362",\ + "0.038124, 0.100137, 0.260980, 0.783299, 2.448362",\ + "0.038124, 0.100137, 0.260980, 0.783299, 2.448362",\ + "0.038124, 0.100137, 0.260980, 0.783299, 2.448362"); + } + + } /* end of arc padmux2ast_i[5]_clk_src_usb_o_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "590008.437500, 590008.500000, 590008.562500, 590008.812500, 590009.500000",\ + "590008.437500, 590008.500000, 590008.562500, 590008.812500, 590009.500000",\ + "590008.562500, 590008.625000, 590008.687500, 590008.937500, 590009.625000",\ + "590008.687500, 590008.750000, 590008.812500, 590009.062500, 590009.750000",\ + "590008.937500, 590009.000000, 590009.062500, 590009.312500, 590010.000000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017600, 0.075142, 0.205270, 0.618216, 1.929571"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "590006.687500, 590006.750000, 590006.875000, 590007.125000, 590008.125000",\ + "590006.812500, 590006.875000, 590007.000000, 590007.250000, 590008.250000",\ + "590006.937500, 590007.000000, 590007.125000, 590007.375000, 590008.375000",\ + "590007.062500, 590007.125000, 590007.250000, 590007.500000, 590008.500000",\ + "590007.312500, 590007.375000, 590007.500000, 590007.750000, 590008.750000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.020388, 0.095624, 0.260980, 0.781920, 2.444935",\ + "0.020388, 0.095624, 0.260980, 0.781920, 2.444935",\ + "0.020388, 0.095624, 0.260980, 0.781920, 2.444935",\ + "0.020388, 0.095624, 0.260980, 0.781920, 2.444935",\ + "0.020388, 0.095624, 0.260980, 0.781920, 2.444935"); + } + + } /* end of arc padmux2ast_i[5]_clk_src_usb_o_una_min*/ + + timing () { + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "590008.312500, 590008.312500, 590008.437500, 590008.750000, 590009.687500",\ + "590008.437500, 590008.437500, 590008.562500, 590008.875000, 590009.812500",\ + "590008.437500, 590008.437500, 590008.562500, 590008.875000, 590009.812500",\ + "590008.562500, 590008.562500, 590008.687500, 590009.000000, 590009.937500",\ + "590008.812500, 590008.812500, 590008.937500, 590009.250000, 590010.187500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.038124, 0.100137, 0.260980, 0.783299, 2.448362",\ + "0.038124, 0.100137, 0.260980, 0.783299, 2.448362",\ + "0.038124, 0.100137, 0.260980, 0.783299, 2.448362",\ + "0.038124, 0.100137, 0.260980, 0.783299, 2.448362",\ + "0.038124, 0.100137, 0.260980, 0.783299, 2.448362"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "590006.625000, 590006.625000, 590006.687500, 590006.937500, 590007.625000",\ + "590006.750000, 590006.750000, 590006.812500, 590007.062500, 590007.750000",\ + "590006.875000, 590006.875000, 590006.937500, 590007.187500, 590007.875000",\ + "590007.000000, 590007.000000, 590007.062500, 590007.312500, 590008.000000",\ + "590007.375000, 590007.375000, 590007.437500, 590007.687500, 590008.375000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.042077, 0.086820, 0.207230, 0.622005, 1.937878",\ + "0.042077, 0.086820, 0.207230, 0.622005, 1.937878",\ + "0.042077, 0.086820, 0.207230, 0.622005, 1.937878",\ + "0.042077, 0.086820, 0.207230, 0.622005, 1.937878",\ + "0.042077, 0.086820, 0.207230, 0.622005, 1.937878"); + } + + } /* end of arc padmux2ast_i[5]_clk_src_usb_o_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "590008.312500, 590008.312500, 590008.437500, 590008.750000, 590009.687500",\ + "590008.312500, 590008.312500, 590008.437500, 590008.750000, 590009.687500",\ + "590008.437500, 590008.437500, 590008.562500, 590008.875000, 590009.812500",\ + "590008.562500, 590008.562500, 590008.687500, 590009.000000, 590009.937500",\ + "590008.812500, 590008.812500, 590008.937500, 590009.250000, 590010.187500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.020388, 0.095624, 0.260980, 0.781920, 2.444935",\ + "0.020388, 0.095624, 0.260980, 0.781920, 2.444935",\ + "0.020388, 0.095624, 0.260980, 0.781920, 2.444935",\ + "0.020388, 0.095624, 0.260980, 0.781920, 2.444935",\ + "0.020388, 0.095624, 0.260980, 0.781920, 2.444935"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "590006.625000, 590006.625000, 590006.687500, 590006.937500, 590007.625000",\ + "590006.750000, 590006.750000, 590006.812500, 590007.062500, 590007.750000",\ + "590006.875000, 590006.875000, 590006.937500, 590007.187500, 590007.875000",\ + "590007.000000, 590007.000000, 590007.062500, 590007.312500, 590008.000000",\ + "590007.250000, 590007.250000, 590007.312500, 590007.562500, 590008.250000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017600, 0.075142, 0.205270, 0.618216, 1.929571"); + } + + } /* end of arc padmux2ast_i[5]_clk_src_usb_o_inv_min*/ + +} /* end of pin clk_src_usb_o */ + +pin("clk_src_usb_val_o") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.090214 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : clk_src_usb_val_o; + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.349057, 0.389670, 0.471811, 0.746196, 1.641015",\ + "0.436455, 0.477067, 0.559209, 0.833594, 1.728413",\ + "0.517302, 0.557914, 0.640055, 0.914441, 1.809259",\ + "0.655434, 0.696047, 0.778188, 1.052573, 1.947392",\ + "0.895822, 0.936589, 1.018755, 1.291518, 2.187617"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.023046, 0.083902, 0.239672, 0.764755, 2.477149",\ + "0.023046, 0.083902, 0.239672, 0.764755, 2.477149",\ + "0.023046, 0.083902, 0.239672, 0.764755, 2.477149",\ + "0.023046, 0.083902, 0.239672, 0.764755, 2.477149",\ + "0.023046, 0.083902, 0.239672, 0.764756, 2.477149"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.392641, 0.430353, 0.490673, 0.680876, 1.305538",\ + "0.480039, 0.517751, 0.578071, 0.768273, 1.392936",\ + "0.560851, 0.598563, 0.658884, 0.849086, 1.473748",\ + "0.698861, 0.736574, 0.796894, 0.987096, 1.611758",\ + "0.919051, 0.956763, 1.017083, 1.207286, 1.831948"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.028951, 0.070788, 0.167468, 0.516468, 1.652661",\ + "0.028951, 0.070788, 0.167468, 0.516468, 1.652661",\ + "0.028951, 0.070788, 0.167468, 0.516468, 1.652661",\ + "0.028951, 0.070788, 0.167468, 0.516468, 1.652661",\ + "0.028951, 0.070788, 0.167468, 0.516468, 1.652661"); + } + + } /* end of arc clk_ast_ext_i_clk_src_usb_val_o_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.222724, 0.263066, 0.345165, 0.618191, 1.516706",\ + "0.310912, 0.351255, 0.433354, 0.706380, 1.604895",\ + "0.398549, 0.438892, 0.520991, 0.794016, 1.692532",\ + "0.546817, 0.587159, 0.669259, 0.942284, 1.840799",\ + "0.782132, 0.822474, 0.904573, 1.177599, 2.076114"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.021530, 0.083764, 0.238778, 0.757619, 2.456895",\ + "0.021530, 0.083764, 0.238778, 0.757619, 2.456895",\ + "0.021530, 0.083764, 0.238778, 0.757619, 2.456895",\ + "0.021530, 0.083764, 0.238778, 0.757619, 2.456895",\ + "0.021530, 0.083764, 0.238778, 0.757619, 2.456895"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.263657, 0.301407, 0.361820, 0.551984, 1.176778",\ + "0.351846, 0.389595, 0.450008, 0.640173, 1.264967",\ + "0.439483, 0.477232, 0.537645, 0.727810, 1.352604",\ + "0.587750, 0.625500, 0.685913, 0.876077, 1.500872",\ + "0.813891, 0.851054, 0.911373, 1.101677, 1.725499"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.025914, 0.068635, 0.165828, 0.512808, 1.651598",\ + "0.025914, 0.068635, 0.165828, 0.512808, 1.651598",\ + "0.025914, 0.068635, 0.165828, 0.512808, 1.651598",\ + "0.025914, 0.068635, 0.165828, 0.512808, 1.651598",\ + "0.025914, 0.068635, 0.165828, 0.512808, 1.651598"); + } + + } /* end of arc clk_ast_ext_i_clk_src_usb_val_o_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "970010.312500, 970010.375000, 970010.437500, 970010.750000, 970011.625000",\ + "970010.437500, 970010.500000, 970010.562500, 970010.875000, 970011.750000",\ + "970010.562500, 970010.625000, 970010.687500, 970011.000000, 970011.875000",\ + "970010.562500, 970010.625000, 970010.687500, 970011.000000, 970011.875000",\ + "970010.937500, 970011.000000, 970011.062500, 970011.375000, 970012.250000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.022871, 0.084362, 0.238855, 0.766838, 2.469430",\ + "0.022871, 0.084362, 0.238855, 0.766838, 2.469430",\ + "0.022871, 0.084362, 0.238855, 0.766838, 2.469430",\ + "0.022871, 0.084362, 0.238855, 0.766838, 2.469430",\ + "0.022871, 0.084362, 0.238855, 0.766838, 2.469430"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "970010.312500, 970010.375000, 970010.437500, 970010.625000, 970011.250000",\ + "970010.437500, 970010.500000, 970010.562500, 970010.750000, 970011.375000",\ + "970010.562500, 970010.625000, 970010.687500, 970010.875000, 970011.500000",\ + "970010.562500, 970010.625000, 970010.687500, 970010.875000, 970011.500000",\ + "970010.937500, 970011.000000, 970011.062500, 970011.250000, 970011.875000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.028494, 0.070786, 0.167369, 0.515912, 1.652408",\ + "0.028494, 0.070786, 0.167369, 0.515912, 1.652408",\ + "0.028494, 0.070786, 0.167369, 0.515912, 1.652408",\ + "0.028494, 0.070786, 0.167369, 0.515912, 1.652408",\ + "0.028494, 0.070786, 0.167369, 0.515912, 1.652408"); + } + + } /* end of arc clk_ast_tlul_i_clk_src_usb_val_o_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.691181, 0.731788, 0.813938, 1.088216, 1.983374",\ + "0.778982, 0.819588, 0.901739, 1.176016, 2.071174",\ + "0.860281, 0.900888, 0.983038, 1.257316, 2.152474",\ + "0.918434, 0.959041, 1.041191, 1.315469, 2.210627",\ + "1.227155, 1.267762, 1.349912, 1.624190, 2.519347"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.021562, 0.083764, 0.238778, 0.757102, 2.460156",\ + "0.021562, 0.083764, 0.238778, 0.757102, 2.460156",\ + "0.021562, 0.083764, 0.238778, 0.757102, 2.460156",\ + "0.021562, 0.083764, 0.238778, 0.757102, 2.460156",\ + "0.021562, 0.083764, 0.238778, 0.757102, 2.460156"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.670492, 0.707647, 0.767969, 0.958286, 1.582166",\ + "0.758292, 0.795447, 0.855769, 1.046087, 1.669967",\ + "0.839591, 0.876747, 0.937069, 1.127386, 1.751266",\ + "0.897745, 0.934900, 0.995222, 1.185539, 1.809419",\ + "1.206465, 1.243621, 1.303943, 1.494260, 2.118140"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.025904, 0.068640, 0.165825, 0.512797, 1.652262",\ + "0.025904, 0.068640, 0.165825, 0.512797, 1.652262",\ + "0.025904, 0.068640, 0.165825, 0.512797, 1.652262",\ + "0.025904, 0.068640, 0.165825, 0.512797, 1.652262",\ + "0.025904, 0.068640, 0.165825, 0.512797, 1.652262"); + } + + } /* end of arc clk_ast_tlul_i_clk_src_usb_val_o_redg_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "970007.125000, 970007.125000, 970007.250000, 970007.500000, 970008.375000",\ + "970007.250000, 970007.250000, 970007.375000, 970007.625000, 970008.500000",\ + "970007.250000, 970007.250000, 970007.375000, 970007.625000, 970008.500000",\ + "970007.500000, 970007.500000, 970007.625000, 970007.875000, 970008.750000",\ + "970007.750000, 970007.750000, 970007.875000, 970008.125000, 970009.000000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.022871, 0.084362, 0.238855, 0.766838, 2.469430",\ + "0.022871, 0.084362, 0.238855, 0.766838, 2.469430",\ + "0.022871, 0.084362, 0.238855, 0.766838, 2.469430",\ + "0.022871, 0.084362, 0.238855, 0.766838, 2.469430",\ + "0.022871, 0.084362, 0.238855, 0.766838, 2.469430"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "970010.187500, 970010.250000, 970010.312500, 970010.500000, 970011.125000",\ + "970010.312500, 970010.375000, 970010.437500, 970010.625000, 970011.250000",\ + "970010.437500, 970010.500000, 970010.562500, 970010.750000, 970011.375000",\ + "970010.687500, 970010.750000, 970010.812500, 970011.000000, 970011.625000",\ + "970010.937500, 970011.000000, 970011.062500, 970011.250000, 970011.875000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.028494, 0.070786, 0.167369, 0.515912, 1.652408",\ + "0.028494, 0.070786, 0.167369, 0.515912, 1.652408",\ + "0.028494, 0.070786, 0.167369, 0.515912, 1.652408",\ + "0.028494, 0.070786, 0.167369, 0.515912, 1.652408",\ + "0.028494, 0.070786, 0.167369, 0.515912, 1.652408"); + } + + } /* end of arc padmux2ast_i[4]_clk_src_usb_val_o_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "380000.437500, 380000.500000, 380000.562500, 380000.843750, 380001.750000",\ + "380000.531250, 380000.593750, 380000.656250, 380000.937500, 380001.843750",\ + "380000.593750, 380000.656250, 380000.718750, 380001.000000, 380001.906250",\ + "380000.750000, 380000.812500, 380000.875000, 380001.156250, 380002.062500",\ + "380000.968750, 380001.031250, 380001.093750, 380001.375000, 380002.281250"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.021562, 0.083764, 0.238778, 0.757102, 2.460156",\ + "0.021562, 0.083764, 0.238778, 0.757102, 2.460156",\ + "0.021562, 0.083764, 0.238778, 0.757102, 2.460156",\ + "0.021562, 0.083764, 0.238778, 0.757102, 2.460156",\ + "0.021562, 0.083764, 0.238778, 0.757102, 2.460156"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "380001.875000, 380001.906250, 380001.968750, 380002.156250, 380002.781250",\ + "380001.968750, 380002.000000, 380002.062500, 380002.250000, 380002.875000",\ + "380002.062500, 380002.093750, 380002.156250, 380002.343750, 380002.968750",\ + "380002.250000, 380002.281250, 380002.343750, 380002.531250, 380003.156250",\ + "380002.500000, 380002.531250, 380002.593750, 380002.781250, 380003.406250"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.025904, 0.068640, 0.165825, 0.512797, 1.652262",\ + "0.025904, 0.068640, 0.165825, 0.512797, 1.652262",\ + "0.025904, 0.068640, 0.165825, 0.512797, 1.652262",\ + "0.025904, 0.068640, 0.165825, 0.512797, 1.652262",\ + "0.025904, 0.068640, 0.165825, 0.512797, 1.652262"); + } + + } /* end of arc padmux2ast_i[4]_clk_src_usb_val_o_una_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "970007.125000, 970007.187500, 970007.250000, 970007.437500, 970008.062500",\ + "970007.250000, 970007.312500, 970007.375000, 970007.562500, 970008.187500",\ + "970007.250000, 970007.312500, 970007.375000, 970007.562500, 970008.187500",\ + "970007.500000, 970007.562500, 970007.625000, 970007.812500, 970008.437500",\ + "970007.750000, 970007.812500, 970007.875000, 970008.062500, 970008.687500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.028494, 0.070786, 0.167369, 0.515912, 1.652408",\ + "0.028494, 0.070786, 0.167369, 0.515912, 1.652408",\ + "0.028494, 0.070786, 0.167369, 0.515912, 1.652408",\ + "0.028494, 0.070786, 0.167369, 0.515912, 1.652408",\ + "0.028494, 0.070786, 0.167369, 0.515912, 1.652408"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "970010.187500, 970010.250000, 970010.312500, 970010.625000, 970011.500000",\ + "970010.312500, 970010.375000, 970010.437500, 970010.750000, 970011.625000",\ + "970010.437500, 970010.500000, 970010.562500, 970010.875000, 970011.750000",\ + "970010.687500, 970010.750000, 970010.812500, 970011.125000, 970012.000000",\ + "970010.937500, 970011.000000, 970011.062500, 970011.375000, 970012.250000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.022871, 0.084362, 0.238855, 0.766838, 2.469430",\ + "0.022871, 0.084362, 0.238855, 0.766838, 2.469430",\ + "0.022871, 0.084362, 0.238855, 0.766838, 2.469430",\ + "0.022871, 0.084362, 0.238855, 0.766838, 2.469430",\ + "0.022871, 0.084362, 0.238855, 0.766838, 2.469430"); + } + + } /* end of arc padmux2ast_i[4]_clk_src_usb_val_o_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "380000.500000, 380000.531250, 380000.593750, 380000.781250, 380001.406250",\ + "380000.593750, 380000.625000, 380000.687500, 380000.875000, 380001.500000",\ + "380000.656250, 380000.687500, 380000.750000, 380000.937500, 380001.562500",\ + "380000.812500, 380000.843750, 380000.906250, 380001.093750, 380001.718750",\ + "380001.031250, 380001.062500, 380001.125000, 380001.312500, 380001.937500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.025904, 0.068640, 0.165825, 0.512797, 1.652262",\ + "0.025904, 0.068640, 0.165825, 0.512797, 1.652262",\ + "0.025904, 0.068640, 0.165825, 0.512797, 1.652262",\ + "0.025904, 0.068640, 0.165825, 0.512797, 1.652262",\ + "0.025904, 0.068640, 0.165825, 0.512797, 1.652262"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "380001.906250, 380001.937500, 380002.031250, 380002.281250, 380003.187500",\ + "380002.000000, 380002.031250, 380002.125000, 380002.375000, 380003.281250",\ + "380002.093750, 380002.125000, 380002.218750, 380002.468750, 380003.375000",\ + "380002.281250, 380002.312500, 380002.406250, 380002.656250, 380003.562500",\ + "380002.531250, 380002.562500, 380002.656250, 380002.906250, 380003.812500"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.021562, 0.083764, 0.238778, 0.757102, 2.460156",\ + "0.021562, 0.083764, 0.238778, 0.757102, 2.460156",\ + "0.021562, 0.083764, 0.238778, 0.757102, 2.460156",\ + "0.021562, 0.083764, 0.238778, 0.757102, 2.460156",\ + "0.021562, 0.083764, 0.238778, 0.757102, 2.460156"); + } + + } /* end of arc padmux2ast_i[4]_clk_src_usb_val_o_inv_min*/ + + timing () { + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "590008.562500, 590008.625000, 590008.687500, 590009.000000, 590009.875000",\ + "590008.687500, 590008.750000, 590008.812500, 590009.125000, 590010.000000",\ + "590008.687500, 590008.750000, 590008.812500, 590009.125000, 590010.000000",\ + "590008.812500, 590008.875000, 590008.937500, 590009.250000, 590010.125000",\ + "590009.062500, 590009.125000, 590009.187500, 590009.500000, 590010.375000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.022871, 0.084362, 0.238855, 0.766861, 2.469430",\ + "0.022871, 0.084362, 0.238855, 0.766861, 2.469430",\ + "0.022871, 0.084362, 0.238855, 0.766861, 2.469430",\ + "0.022871, 0.084362, 0.238855, 0.766861, 2.469430",\ + "0.022871, 0.084362, 0.238855, 0.766861, 2.469430"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "590006.875000, 590006.937500, 590007.000000, 590007.187500, 590007.812500",\ + "590007.000000, 590007.062500, 590007.125000, 590007.312500, 590007.937500",\ + "590007.125000, 590007.187500, 590007.250000, 590007.437500, 590008.062500",\ + "590007.250000, 590007.312500, 590007.375000, 590007.562500, 590008.187500",\ + "590007.625000, 590007.687500, 590007.750000, 590007.937500, 590008.562500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.028494, 0.070786, 0.167369, 0.515919, 1.652408",\ + "0.028494, 0.070786, 0.167369, 0.515919, 1.652408",\ + "0.028494, 0.070786, 0.167369, 0.515919, 1.652408",\ + "0.028494, 0.070786, 0.167369, 0.515919, 1.652408",\ + "0.028494, 0.070786, 0.167369, 0.515919, 1.652408"); + } + + } /* end of arc padmux2ast_i[5]_clk_src_usb_val_o_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "590008.375000, 590008.437500, 590008.500000, 590008.812500, 590009.687500",\ + "590008.375000, 590008.437500, 590008.500000, 590008.812500, 590009.687500",\ + "590008.500000, 590008.562500, 590008.625000, 590008.937500, 590009.812500",\ + "590008.625000, 590008.687500, 590008.750000, 590009.062500, 590009.937500",\ + "590008.875000, 590008.937500, 590009.000000, 590009.312500, 590010.187500"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.022032, 0.083764, 0.238629, 0.755850, 2.465812",\ + "0.022032, 0.083764, 0.238629, 0.755850, 2.465812",\ + "0.022032, 0.083764, 0.238629, 0.755850, 2.465812",\ + "0.022032, 0.083764, 0.238629, 0.755850, 2.465812",\ + "0.022032, 0.083764, 0.238629, 0.755850, 2.465812"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "590006.750000, 590006.750000, 590006.812500, 590007.000000, 590007.625000",\ + "590006.875000, 590006.875000, 590006.937500, 590007.125000, 590007.750000",\ + "590007.000000, 590007.000000, 590007.062500, 590007.250000, 590007.875000",\ + "590007.125000, 590007.125000, 590007.187500, 590007.375000, 590008.000000",\ + "590007.375000, 590007.375000, 590007.437500, 590007.625000, 590008.250000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.026011, 0.068726, 0.165863, 0.510725, 1.651082",\ + "0.026011, 0.068726, 0.165863, 0.510725, 1.651082",\ + "0.026011, 0.068726, 0.165863, 0.510725, 1.651082",\ + "0.026011, 0.068726, 0.165863, 0.510725, 1.651082",\ + "0.026011, 0.068726, 0.165863, 0.510725, 1.651082"); + } + + } /* end of arc padmux2ast_i[5]_clk_src_usb_val_o_una_min*/ + + timing () { + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "590008.562500, 590008.625000, 590008.687500, 590008.875000, 590009.500000",\ + "590008.687500, 590008.750000, 590008.812500, 590009.000000, 590009.625000",\ + "590008.687500, 590008.750000, 590008.812500, 590009.000000, 590009.625000",\ + "590008.812500, 590008.875000, 590008.937500, 590009.125000, 590009.750000",\ + "590009.062500, 590009.125000, 590009.187500, 590009.375000, 590010.000000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.028494, 0.070786, 0.167369, 0.515919, 1.652408",\ + "0.028494, 0.070786, 0.167369, 0.515919, 1.652408",\ + "0.028494, 0.070786, 0.167369, 0.515919, 1.652408",\ + "0.028494, 0.070786, 0.167369, 0.515919, 1.652408",\ + "0.028494, 0.070786, 0.167369, 0.515919, 1.652408"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "590006.875000, 590006.875000, 590007.000000, 590007.250000, 590008.125000",\ + "590007.000000, 590007.000000, 590007.125000, 590007.375000, 590008.250000",\ + "590007.125000, 590007.125000, 590007.250000, 590007.500000, 590008.375000",\ + "590007.250000, 590007.250000, 590007.375000, 590007.625000, 590008.500000",\ + "590007.625000, 590007.625000, 590007.750000, 590008.000000, 590008.875000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.022871, 0.084362, 0.238855, 0.766861, 2.469430",\ + "0.022871, 0.084362, 0.238855, 0.766861, 2.469430",\ + "0.022871, 0.084362, 0.238855, 0.766861, 2.469430",\ + "0.022871, 0.084362, 0.238855, 0.766861, 2.469430",\ + "0.022871, 0.084362, 0.238855, 0.766861, 2.469430"); + } + + } /* end of arc padmux2ast_i[5]_clk_src_usb_val_o_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "590008.562500, 590008.625000, 590008.687500, 590008.875000, 590009.500000",\ + "590008.562500, 590008.625000, 590008.687500, 590008.875000, 590009.500000",\ + "590008.687500, 590008.750000, 590008.812500, 590009.000000, 590009.625000",\ + "590008.812500, 590008.875000, 590008.937500, 590009.125000, 590009.750000",\ + "590009.062500, 590009.125000, 590009.187500, 590009.375000, 590010.000000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.026011, 0.068726, 0.165863, 0.510725, 1.651082",\ + "0.026011, 0.068726, 0.165863, 0.510725, 1.651082",\ + "0.026011, 0.068726, 0.165863, 0.510725, 1.651082",\ + "0.026011, 0.068726, 0.165863, 0.510725, 1.651082",\ + "0.026011, 0.068726, 0.165863, 0.510725, 1.651082"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "590006.875000, 590006.875000, 590007.000000, 590007.250000, 590008.125000",\ + "590007.000000, 590007.000000, 590007.125000, 590007.375000, 590008.250000",\ + "590007.125000, 590007.125000, 590007.250000, 590007.500000, 590008.375000",\ + "590007.250000, 590007.250000, 590007.375000, 590007.625000, 590008.500000",\ + "590007.500000, 590007.500000, 590007.625000, 590007.875000, 590008.750000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.022032, 0.083764, 0.238629, 0.755850, 2.465812",\ + "0.022032, 0.083764, 0.238629, 0.755850, 2.465812",\ + "0.022032, 0.083764, 0.238629, 0.755850, 2.465812",\ + "0.022032, 0.083764, 0.238629, 0.755850, 2.465812",\ + "0.022032, 0.083764, 0.238629, 0.755850, 2.465812"); + } + + } /* end of arc padmux2ast_i[5]_clk_src_usb_val_o_inv_min*/ + +} /* end of pin clk_src_usb_val_o */ +bus ( usb_io_pu_cal_o ) { + + bus_type : BUS20_type7 ; + direction : output ; + +pin("usb_io_pu_cal_o[19]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.044612 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : usb_io_pu_cal_o[19]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.314417, 0.335777, 0.372002, 0.776684, 1.668587",\ + "0.399220, 0.420577, 0.456801, 0.861483, 1.753386",\ + "0.475457, 0.496832, 0.533065, 0.937750, 1.829653",\ + "0.530163, 0.551559, 0.587801, 0.992490, 1.884393",\ + "0.830581, 0.852045, 0.888318, 1.293020, 2.184924"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.044702, 0.070201, 0.128218, 0.852056, 2.450125",\ + "0.044702, 0.070201, 0.128218, 0.852056, 2.450125",\ + "0.044702, 0.070201, 0.128220, 0.852056, 2.450126",\ + "0.044702, 0.070225, 0.128223, 0.852056, 2.450128",\ + "0.046369, 0.071964, 0.128232, 0.852062, 2.450135"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.217558, 0.227289, 0.241063, 0.379813, 0.685715",\ + "0.306214, 0.315945, 0.329719, 0.468469, 0.774371",\ + "0.401954, 0.411685, 0.425460, 0.564210, 0.870112",\ + "0.471485, 0.481216, 0.494992, 0.633742, 0.939644",\ + "0.839028, 0.848765, 0.862546, 1.001302, 1.307204"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.025202, 0.034115, 0.048740, 0.301167, 0.860107",\ + "0.025202, 0.034115, 0.048740, 0.301167, 0.860107",\ + "0.025203, 0.034116, 0.048742, 0.301167, 0.860107",\ + "0.025205, 0.034118, 0.048744, 0.301167, 0.860107",\ + "0.025222, 0.034137, 0.048764, 0.301167, 0.860107"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[19]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.197396, 0.217798, 0.253787, 0.659515, 1.549779",\ + "0.285773, 0.306177, 0.342166, 0.747894, 1.638158",\ + "0.375534, 0.395928, 0.431912, 0.837641, 1.727905",\ + "0.439799, 0.460179, 0.496157, 0.901887, 1.792151",\ + "0.781328, 0.801955, 0.838037, 1.243750, 2.134013"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.041661, 0.069999, 0.126709, 0.849969, 2.447141",\ + "0.041661, 0.069999, 0.126709, 0.849969, 2.447141",\ + "0.041661, 0.069999, 0.126709, 0.849969, 2.447141",\ + "0.041661, 0.069999, 0.126709, 0.849969, 2.447141",\ + "0.041673, 0.070094, 0.126932, 0.849969, 2.447141"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.177011, 0.187648, 0.201756, 0.342079, 0.647165",\ + "0.264382, 0.275019, 0.289127, 0.429450, 0.734536",\ + "0.342508, 0.353145, 0.367252, 0.507575, 0.812661",\ + "0.397042, 0.407678, 0.421785, 0.562107, 0.867194",\ + "0.681430, 0.692081, 0.706196, 0.846525, 1.151605"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.024113, 0.032746, 0.047552, 0.299568, 0.856157",\ + "0.024113, 0.032746, 0.047552, 0.299568, 0.856157",\ + "0.024113, 0.032746, 0.047552, 0.299568, 0.856157",\ + "0.024113, 0.032746, 0.047552, 0.299568, 0.856157",\ + "0.024126, 0.032778, 0.047567, 0.299569, 0.856157"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[19]_redg_min*/ + +} /* end of pin usb_io_pu_cal_o[19] */ + +pin("usb_io_pu_cal_o[18]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.044612 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : usb_io_pu_cal_o[18]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.314417, 0.335777, 0.372002, 0.776684, 1.668587",\ + "0.399220, 0.420577, 0.456801, 0.861483, 1.753386",\ + "0.475457, 0.496832, 0.533065, 0.937750, 1.829653",\ + "0.530163, 0.551559, 0.587801, 0.992490, 1.884393",\ + "0.830581, 0.852045, 0.888318, 1.293020, 2.184924"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.044702, 0.070201, 0.128218, 0.852056, 2.450125",\ + "0.044702, 0.070201, 0.128218, 0.852056, 2.450125",\ + "0.044702, 0.070201, 0.128220, 0.852056, 2.450126",\ + "0.044702, 0.070225, 0.128223, 0.852056, 2.450128",\ + "0.046369, 0.071964, 0.128232, 0.852062, 2.450135"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.217558, 0.227289, 0.241063, 0.379813, 0.685715",\ + "0.306214, 0.315945, 0.329719, 0.468469, 0.774371",\ + "0.401954, 0.411685, 0.425460, 0.564210, 0.870112",\ + "0.471485, 0.481216, 0.494992, 0.633742, 0.939644",\ + "0.839028, 0.848765, 0.862546, 1.001302, 1.307204"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.025200, 0.034112, 0.048740, 0.301167, 0.860107",\ + "0.025200, 0.034112, 0.048740, 0.301167, 0.860107",\ + "0.025202, 0.034115, 0.048742, 0.301167, 0.860107",\ + "0.025205, 0.034118, 0.048744, 0.301167, 0.860107",\ + "0.025221, 0.034136, 0.048764, 0.301167, 0.860107"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[18]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.211928, 0.232331, 0.268319, 0.674047, 1.564311",\ + "0.300343, 0.320746, 0.356735, 0.762463, 1.652727",\ + "0.394726, 0.415129, 0.451117, 0.856845, 1.747110",\ + "0.462784, 0.483187, 0.519176, 0.924904, 1.815168",\ + "0.787427, 0.807827, 0.843815, 1.249543, 2.139807"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.041661, 0.070068, 0.126730, 0.849972, 2.447344",\ + "0.041661, 0.070068, 0.126730, 0.849972, 2.447344",\ + "0.041661, 0.070068, 0.126730, 0.849972, 2.447344",\ + "0.041661, 0.070068, 0.126730, 0.849972, 2.447345",\ + "0.041673, 0.070061, 0.126728, 0.849969, 2.447347"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.180996, 0.190508, 0.204096, 0.342744, 0.648655",\ + "0.266400, 0.277038, 0.291146, 0.430107, 0.736018",\ + "0.342508, 0.353145, 0.367252, 0.507575, 0.812661",\ + "0.397042, 0.407678, 0.421785, 0.562107, 0.867194",\ + "0.681430, 0.692081, 0.706196, 0.846525, 1.151605"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.024113, 0.032746, 0.047552, 0.299568, 0.856157",\ + "0.024113, 0.032746, 0.047552, 0.299568, 0.856157",\ + "0.024113, 0.032746, 0.047552, 0.299568, 0.856157",\ + "0.024113, 0.032746, 0.047552, 0.299568, 0.856157",\ + "0.024126, 0.032778, 0.047567, 0.299569, 0.856157"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[18]_redg_min*/ + +} /* end of pin usb_io_pu_cal_o[18] */ + +pin("usb_io_pu_cal_o[17]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.044612 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : usb_io_pu_cal_o[17]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.314417, 0.335777, 0.372002, 0.776684, 1.668587",\ + "0.399220, 0.420577, 0.456801, 0.861483, 1.753386",\ + "0.475457, 0.496832, 0.533065, 0.937750, 1.829653",\ + "0.530163, 0.551559, 0.587801, 0.992490, 1.884393",\ + "0.830581, 0.852045, 0.888318, 1.293020, 2.184924"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.044601, 0.070148, 0.128218, 0.852056, 2.450125",\ + "0.044663, 0.070159, 0.128218, 0.852056, 2.450125",\ + "0.044669, 0.070182, 0.128220, 0.852056, 2.450126",\ + "0.044669, 0.070225, 0.128223, 0.852056, 2.450128",\ + "0.046118, 0.071698, 0.128232, 0.852061, 2.450135"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.217558, 0.227289, 0.241063, 0.379813, 0.685715",\ + "0.306214, 0.315945, 0.329719, 0.468469, 0.774371",\ + "0.401954, 0.411685, 0.425460, 0.564210, 0.870112",\ + "0.471485, 0.481216, 0.494992, 0.633742, 0.939644",\ + "0.839028, 0.848765, 0.862546, 1.001302, 1.307204"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.025212, 0.034126, 0.048740, 0.301166, 0.860107",\ + "0.025213, 0.034127, 0.048740, 0.301166, 0.860107",\ + "0.025216, 0.034130, 0.048742, 0.301166, 0.860107",\ + "0.025218, 0.034133, 0.048744, 0.301166, 0.860107",\ + "0.025235, 0.034151, 0.048764, 0.301166, 0.860107"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[17]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.194489, 0.214889, 0.250877, 0.656605, 1.546869",\ + "0.282628, 0.303028, 0.339015, 0.744743, 1.635008",\ + "0.372036, 0.392436, 0.428424, 0.834152, 1.724416",\ + "0.436052, 0.456452, 0.492440, 0.898167, 1.788432",\ + "0.763219, 0.783617, 0.819604, 1.225332, 2.115596"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.041661, 0.070060, 0.126728, 0.849972, 2.447347",\ + "0.041661, 0.070060, 0.126728, 0.849972, 2.447347",\ + "0.041661, 0.070060, 0.126728, 0.849972, 2.447347",\ + "0.041661, 0.070060, 0.126728, 0.849972, 2.447347",\ + "0.041673, 0.070054, 0.126726, 0.849969, 2.447349"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.175899, 0.186544, 0.200656, 0.340982, 0.646065",\ + "0.263271, 0.273916, 0.288028, 0.428355, 0.733437",\ + "0.344128, 0.354771, 0.368883, 0.509209, 0.814291",\ + "0.401818, 0.412460, 0.426571, 0.566896, 0.871980",\ + "0.705550, 0.716209, 0.730328, 0.870660, 1.175736"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.024113, 0.032746, 0.047558, 0.299568, 0.856133",\ + "0.024113, 0.032746, 0.047558, 0.299568, 0.856133",\ + "0.024113, 0.032746, 0.047558, 0.299568, 0.856133",\ + "0.024113, 0.032746, 0.047558, 0.299568, 0.856133",\ + "0.024126, 0.032778, 0.047574, 0.299569, 0.856133"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[17]_redg_min*/ + +} /* end of pin usb_io_pu_cal_o[17] */ + +pin("usb_io_pu_cal_o[16]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.044612 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : usb_io_pu_cal_o[16]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.314417, 0.335777, 0.372002, 0.776684, 1.668587",\ + "0.399220, 0.420577, 0.456801, 0.861483, 1.753386",\ + "0.475457, 0.496832, 0.533065, 0.937750, 1.829653",\ + "0.530163, 0.551559, 0.587801, 0.992490, 1.884393",\ + "0.830581, 0.852045, 0.888318, 1.293020, 2.184924"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.044695, 0.070193, 0.128218, 0.852056, 2.450125",\ + "0.044695, 0.070193, 0.128218, 0.852056, 2.450125",\ + "0.044695, 0.070193, 0.128220, 0.852056, 2.450126",\ + "0.044695, 0.070225, 0.128223, 0.852056, 2.450128",\ + "0.044695, 0.070368, 0.128232, 0.852056, 2.450135"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.217558, 0.227289, 0.241063, 0.379813, 0.685715",\ + "0.306214, 0.315945, 0.329719, 0.468469, 0.774371",\ + "0.401954, 0.411685, 0.425460, 0.564210, 0.870112",\ + "0.471485, 0.481216, 0.494992, 0.633742, 0.939644",\ + "0.839028, 0.848765, 0.862546, 1.001302, 1.307204"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.025212, 0.034126, 0.048740, 0.301166, 0.860107",\ + "0.025212, 0.034126, 0.048740, 0.301166, 0.860107",\ + "0.025216, 0.034130, 0.048742, 0.301166, 0.860107",\ + "0.025218, 0.034133, 0.048744, 0.301166, 0.860107",\ + "0.025235, 0.034151, 0.048764, 0.301166, 0.860107"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[16]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.241214, 0.262542, 0.298754, 0.703431, 1.595333",\ + "0.329624, 0.350953, 0.387164, 0.791841, 1.683743",\ + "0.418828, 0.440156, 0.476368, 0.881044, 1.772947",\ + "0.478173, 0.498573, 0.534561, 0.940289, 1.830553",\ + "0.763219, 0.783617, 0.819604, 1.225332, 2.115596"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.041661, 0.070060, 0.126728, 0.849972, 2.447347",\ + "0.041661, 0.070060, 0.126728, 0.849972, 2.447347",\ + "0.041661, 0.070060, 0.126728, 0.849972, 2.447347",\ + "0.041661, 0.070060, 0.126728, 0.849972, 2.447347",\ + "0.041673, 0.070054, 0.126726, 0.849969, 2.447349"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.180996, 0.190508, 0.204096, 0.342744, 0.648655",\ + "0.268360, 0.277871, 0.291459, 0.430107, 0.736018",\ + "0.349209, 0.358716, 0.372303, 0.510951, 0.816863",\ + "0.406926, 0.416431, 0.430016, 0.568664, 0.874576",\ + "0.710950, 0.720466, 0.734056, 0.872703, 1.178614"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.024113, 0.032746, 0.047559, 0.299568, 0.856139",\ + "0.024113, 0.032746, 0.047559, 0.299568, 0.856139",\ + "0.024113, 0.032746, 0.047559, 0.299568, 0.856139",\ + "0.024113, 0.032746, 0.047559, 0.299568, 0.856139",\ + "0.024126, 0.032778, 0.047572, 0.299569, 0.856139"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[16]_redg_min*/ + +} /* end of pin usb_io_pu_cal_o[16] */ + +pin("usb_io_pu_cal_o[15]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.044612 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : usb_io_pu_cal_o[15]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.320701, 0.342069, 0.378299, 0.782982, 1.674885",\ + "0.408065, 0.429433, 0.465663, 0.870347, 1.762250",\ + "0.488969, 0.510342, 0.546573, 0.951258, 1.843161",\ + "0.546844, 0.568237, 0.604478, 1.009167, 1.901070",\ + "0.862468, 0.884064, 0.920396, 1.325122, 2.217029"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.044702, 0.070201, 0.128219, 0.852056, 2.450125",\ + "0.044702, 0.070201, 0.128219, 0.852056, 2.450125",\ + "0.044702, 0.070201, 0.128220, 0.852056, 2.450126",\ + "0.044702, 0.070220, 0.128222, 0.852056, 2.450128",\ + "0.046369, 0.071964, 0.128250, 0.852062, 2.450147"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.208477, 0.218207, 0.231981, 0.370730, 0.676633",\ + "0.296951, 0.306682, 0.320455, 0.459205, 0.765107",\ + "0.387709, 0.397440, 0.411214, 0.549964, 0.855866",\ + "0.453111, 0.462843, 0.476618, 0.615368, 0.921270",\ + "0.800244, 0.809980, 0.823761, 0.962517, 1.268419"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.025202, 0.034115, 0.048739, 0.301167, 0.860107",\ + "0.025202, 0.034115, 0.048739, 0.301167, 0.860107",\ + "0.025203, 0.034116, 0.048740, 0.301167, 0.860107",\ + "0.025205, 0.034118, 0.048742, 0.301167, 0.860107",\ + "0.025222, 0.034137, 0.048763, 0.301167, 0.860107"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[15]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.197396, 0.217798, 0.253787, 0.659515, 1.549779",\ + "0.285773, 0.306177, 0.342166, 0.747894, 1.638158",\ + "0.375534, 0.395928, 0.431912, 0.837641, 1.727905",\ + "0.439799, 0.460179, 0.496157, 0.901887, 1.792151",\ + "0.781328, 0.801955, 0.838037, 1.243750, 2.134013"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.041685, 0.069999, 0.126709, 0.849953, 2.447141",\ + "0.041695, 0.069999, 0.126709, 0.849953, 2.447141",\ + "0.041741, 0.069999, 0.126709, 0.849953, 2.447141",\ + "0.041758, 0.069999, 0.126709, 0.849953, 2.447141",\ + "0.041766, 0.070174, 0.126932, 0.849953, 2.447141"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.177011, 0.187648, 0.201756, 0.340918, 0.646830",\ + "0.264382, 0.275019, 0.289127, 0.428292, 0.734203",\ + "0.342508, 0.353145, 0.367252, 0.506601, 0.812513",\ + "0.397042, 0.407678, 0.421785, 0.561150, 0.867061",\ + "0.681430, 0.692081, 0.706196, 0.845682, 1.151594"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.024118, 0.032771, 0.047553, 0.299569, 0.856201",\ + "0.024118, 0.032771, 0.047553, 0.299569, 0.856201",\ + "0.024117, 0.032767, 0.047553, 0.299569, 0.856201",\ + "0.024117, 0.032759, 0.047552, 0.299568, 0.856201",\ + "0.024117, 0.032759, 0.047552, 0.299568, 0.856157"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[15]_redg_min*/ + +} /* end of pin usb_io_pu_cal_o[15] */ + +pin("usb_io_pu_cal_o[14]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.044612 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : usb_io_pu_cal_o[14]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.320701, 0.342069, 0.378299, 0.782982, 1.674885",\ + "0.408065, 0.429433, 0.465663, 0.870347, 1.762250",\ + "0.488969, 0.510342, 0.546573, 0.951258, 1.843161",\ + "0.546844, 0.568237, 0.604478, 1.009167, 1.901070",\ + "0.862468, 0.884064, 0.920396, 1.325122, 2.217029"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.044702, 0.070201, 0.128219, 0.852056, 2.450125",\ + "0.044702, 0.070201, 0.128219, 0.852056, 2.450125",\ + "0.044702, 0.070201, 0.128220, 0.852056, 2.450126",\ + "0.044702, 0.070220, 0.128222, 0.852056, 2.450128",\ + "0.046369, 0.071964, 0.128250, 0.852062, 2.450147"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.208477, 0.218207, 0.231981, 0.370730, 0.676633",\ + "0.296951, 0.306682, 0.320455, 0.459205, 0.765107",\ + "0.387709, 0.397440, 0.411214, 0.549964, 0.855866",\ + "0.453111, 0.462843, 0.476618, 0.615368, 0.921270",\ + "0.800244, 0.809980, 0.823761, 0.962517, 1.268419"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.025200, 0.034112, 0.048739, 0.301167, 0.860107",\ + "0.025200, 0.034112, 0.048739, 0.301167, 0.860107",\ + "0.025202, 0.034115, 0.048740, 0.301167, 0.860107",\ + "0.025205, 0.034118, 0.048742, 0.301167, 0.860107",\ + "0.025221, 0.034136, 0.048763, 0.301167, 0.860107"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[14]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.211928, 0.232331, 0.268319, 0.674047, 1.564311",\ + "0.300343, 0.320746, 0.356735, 0.762463, 1.652727",\ + "0.394726, 0.415129, 0.451117, 0.856845, 1.747110",\ + "0.462784, 0.483187, 0.519176, 0.924904, 1.815168",\ + "0.787427, 0.807827, 0.843815, 1.249543, 2.139807"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.041685, 0.070068, 0.126730, 0.849967, 2.447344",\ + "0.041695, 0.070068, 0.126730, 0.849965, 2.447344",\ + "0.041741, 0.070068, 0.126730, 0.849957, 2.447344",\ + "0.041758, 0.070068, 0.126730, 0.849954, 2.447345",\ + "0.041766, 0.070061, 0.126728, 0.849953, 2.447347"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.179169, 0.188682, 0.202271, 0.340918, 0.646830",\ + "0.266400, 0.276055, 0.289644, 0.428292, 0.734203",\ + "0.342508, 0.353145, 0.367252, 0.506601, 0.812513",\ + "0.397042, 0.407678, 0.421785, 0.561150, 0.867061",\ + "0.681430, 0.692081, 0.706196, 0.845682, 1.151594"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.024118, 0.032771, 0.047553, 0.299569, 0.856201",\ + "0.024118, 0.032771, 0.047553, 0.299569, 0.856201",\ + "0.024117, 0.032767, 0.047553, 0.299569, 0.856201",\ + "0.024117, 0.032759, 0.047552, 0.299568, 0.856201",\ + "0.024117, 0.032759, 0.047552, 0.299568, 0.856157"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[14]_redg_min*/ + +} /* end of pin usb_io_pu_cal_o[14] */ + +pin("usb_io_pu_cal_o[13]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.044612 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : usb_io_pu_cal_o[13]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.320701, 0.342069, 0.378299, 0.782982, 1.674885",\ + "0.408065, 0.429433, 0.465663, 0.870347, 1.762250",\ + "0.488969, 0.510342, 0.546573, 0.951258, 1.843161",\ + "0.546844, 0.568237, 0.604478, 1.009167, 1.901070",\ + "0.862468, 0.884064, 0.920396, 1.325122, 2.217029"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.044601, 0.070167, 0.128219, 0.852056, 2.450125",\ + "0.044663, 0.070167, 0.128219, 0.852056, 2.450125",\ + "0.044669, 0.070177, 0.128220, 0.852056, 2.450126",\ + "0.044669, 0.070220, 0.128222, 0.852056, 2.450128",\ + "0.046118, 0.071698, 0.128250, 0.852061, 2.450147"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.208477, 0.218207, 0.231981, 0.372429, 0.677586",\ + "0.296951, 0.306682, 0.320688, 0.461137, 0.766294",\ + "0.391373, 0.402162, 0.416428, 0.556878, 0.862036",\ + "0.460819, 0.471609, 0.485876, 0.626327, 0.931486",\ + "0.825748, 0.836544, 0.850818, 0.991274, 1.296437"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.025212, 0.034126, 0.048739, 0.301166, 0.860107",\ + "0.025213, 0.034127, 0.048739, 0.301166, 0.860107",\ + "0.025216, 0.034130, 0.048740, 0.301166, 0.860107",\ + "0.025218, 0.034133, 0.048742, 0.301166, 0.860107",\ + "0.025235, 0.034151, 0.048763, 0.301166, 0.860107"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[13]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.194489, 0.214889, 0.250877, 0.656605, 1.546869",\ + "0.282628, 0.303028, 0.339015, 0.744743, 1.635008",\ + "0.372036, 0.392436, 0.428424, 0.834152, 1.724416",\ + "0.436052, 0.456452, 0.492440, 0.898167, 1.788432",\ + "0.763219, 0.783617, 0.819604, 1.225332, 2.115596"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.041685, 0.070060, 0.126728, 0.849967, 2.447347",\ + "0.041695, 0.070060, 0.126728, 0.849965, 2.447347",\ + "0.041741, 0.070060, 0.126728, 0.849957, 2.447347",\ + "0.041758, 0.070060, 0.126728, 0.849954, 2.447347",\ + "0.041766, 0.070054, 0.126726, 0.849953, 2.447349"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.175899, 0.186544, 0.200656, 0.340918, 0.646065",\ + "0.263271, 0.273916, 0.288028, 0.428292, 0.733437",\ + "0.344128, 0.354365, 0.367954, 0.506601, 0.812513",\ + "0.399406, 0.408915, 0.422502, 0.561150, 0.867061",\ + "0.683934, 0.693446, 0.707035, 0.845682, 1.151594"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.024118, 0.032771, 0.047561, 0.299569, 0.856177",\ + "0.024118, 0.032771, 0.047561, 0.299569, 0.856176",\ + "0.024117, 0.032767, 0.047560, 0.299569, 0.856176",\ + "0.024117, 0.032759, 0.047558, 0.299568, 0.856176",\ + "0.024117, 0.032759, 0.047558, 0.299568, 0.856133"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[13]_redg_min*/ + +} /* end of pin usb_io_pu_cal_o[13] */ + +pin("usb_io_pu_cal_o[12]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.044612 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : usb_io_pu_cal_o[12]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.320701, 0.342069, 0.378299, 0.782982, 1.674885",\ + "0.408065, 0.429433, 0.465663, 0.870347, 1.762250",\ + "0.488969, 0.510342, 0.546573, 0.951258, 1.843161",\ + "0.546844, 0.568237, 0.604478, 1.009167, 1.901070",\ + "0.862468, 0.884064, 0.920396, 1.325122, 2.217029"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.044695, 0.070193, 0.128219, 0.852056, 2.450125",\ + "0.044695, 0.070193, 0.128219, 0.852056, 2.450125",\ + "0.044695, 0.070193, 0.128220, 0.852056, 2.450126",\ + "0.044695, 0.070220, 0.128222, 0.852056, 2.450128",\ + "0.044695, 0.070644, 0.128250, 0.852056, 2.450147"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.208477, 0.218207, 0.231981, 0.372429, 0.677586",\ + "0.296951, 0.306682, 0.320455, 0.460894, 0.766051",\ + "0.391373, 0.402162, 0.416428, 0.556878, 0.862036",\ + "0.460819, 0.471609, 0.485876, 0.626327, 0.931486",\ + "0.825748, 0.836544, 0.850818, 0.991274, 1.296437"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.025212, 0.034126, 0.048739, 0.301166, 0.860107",\ + "0.025212, 0.034126, 0.048739, 0.301166, 0.860107",\ + "0.025216, 0.034130, 0.048740, 0.301166, 0.860107",\ + "0.025218, 0.034133, 0.048742, 0.301166, 0.860107",\ + "0.025235, 0.034151, 0.048763, 0.301166, 0.860107"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[12]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.238920, 0.260258, 0.296474, 0.701152, 1.593054",\ + "0.327371, 0.348714, 0.384932, 0.789611, 1.681513",\ + "0.416587, 0.437948, 0.474174, 0.878857, 1.770759",\ + "0.478173, 0.498573, 0.534561, 0.940289, 1.830553",\ + "0.763219, 0.783617, 0.819604, 1.225332, 2.115596"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.041685, 0.070060, 0.126728, 0.849967, 2.447347",\ + "0.041695, 0.070060, 0.126728, 0.849965, 2.447347",\ + "0.041741, 0.070060, 0.126728, 0.849957, 2.447347",\ + "0.041758, 0.070060, 0.126728, 0.849954, 2.447347",\ + "0.041766, 0.070054, 0.126726, 0.849953, 2.447349"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.179169, 0.188682, 0.202271, 0.340918, 0.646830",\ + "0.266542, 0.276055, 0.289644, 0.428292, 0.734203",\ + "0.344853, 0.354365, 0.367954, 0.506601, 0.812513",\ + "0.399406, 0.408915, 0.422502, 0.561150, 0.867061",\ + "0.683934, 0.693446, 0.707035, 0.845682, 1.151594"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.024118, 0.032771, 0.047563, 0.299569, 0.856171",\ + "0.024118, 0.032771, 0.047563, 0.299569, 0.856171",\ + "0.024117, 0.032767, 0.047561, 0.299569, 0.856171",\ + "0.024117, 0.032759, 0.047559, 0.299568, 0.856171",\ + "0.024117, 0.032759, 0.047559, 0.299568, 0.856139"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[12]_redg_min*/ + +} /* end of pin usb_io_pu_cal_o[12] */ + +pin("usb_io_pu_cal_o[11]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.044612 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : usb_io_pu_cal_o[11]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.310563, 0.333600, 0.370684, 0.776237, 1.666485",\ + "0.397928, 0.420965, 0.458048, 0.863602, 1.753849",\ + "0.478891, 0.501955, 0.539050, 0.944602, 1.834849",\ + "0.536743, 0.559839, 0.596947, 1.002497, 1.892744",\ + "0.858742, 0.881931, 0.919078, 1.324622, 2.214868"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.051871, 0.077785, 0.129094, 0.852080, 2.449966",\ + "0.051871, 0.077785, 0.129094, 0.852080, 2.449966",\ + "0.051946, 0.077865, 0.129119, 0.852080, 2.449966",\ + "0.052034, 0.077959, 0.129147, 0.852081, 2.449966",\ + "0.052292, 0.078232, 0.129231, 0.852081, 2.450003"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.206143, 0.216949, 0.231236, 0.371702, 0.676873",\ + "0.294617, 0.305423, 0.319710, 0.460177, 0.765348",\ + "0.385375, 0.396181, 0.410468, 0.550935, 0.856106",\ + "0.450776, 0.461583, 0.475870, 0.616338, 0.921509",\ + "0.797902, 0.808713, 0.823006, 0.963477, 1.268652"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.025267, 0.034187, 0.048727, 0.301161, 0.860108",\ + "0.025267, 0.034187, 0.048727, 0.301161, 0.860108",\ + "0.025267, 0.034188, 0.048728, 0.301161, 0.860108",\ + "0.025268, 0.034189, 0.048730, 0.301161, 0.860108",\ + "0.025282, 0.034204, 0.048751, 0.301161, 0.860108"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[11]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.205226, 0.224853, 0.260301, 0.664656, 1.556533",\ + "0.293604, 0.313232, 0.348681, 0.753036, 1.644913",\ + "0.383357, 0.402977, 0.438423, 0.842777, 1.734654",\ + "0.447610, 0.467222, 0.502663, 0.907016, 1.798893",\ + "0.789341, 0.809115, 0.844630, 1.249013, 2.140893"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.037493, 0.066493, 0.127978, 0.850658, 2.444969",\ + "0.037493, 0.066493, 0.127978, 0.850658, 2.444969",\ + "0.037493, 0.066493, 0.127978, 0.850658, 2.444969",\ + "0.037493, 0.066493, 0.127978, 0.850658, 2.444969",\ + "0.037854, 0.066833, 0.128000, 0.850658, 2.444969"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.179497, 0.189096, 0.202727, 0.341364, 0.647272",\ + "0.266868, 0.276467, 0.290098, 0.428735, 0.734643",\ + "0.344994, 0.354592, 0.368223, 0.506860, 0.812768",\ + "0.399528, 0.409125, 0.422756, 0.561393, 0.867301",\ + "0.683921, 0.693531, 0.707168, 0.845803, 1.151711"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.024391, 0.033017, 0.047459, 0.299575, 0.856462",\ + "0.024391, 0.033017, 0.047459, 0.299575, 0.856462",\ + "0.024391, 0.033017, 0.047459, 0.299575, 0.856462",\ + "0.024391, 0.033017, 0.047459, 0.299575, 0.856462",\ + "0.024427, 0.033054, 0.047472, 0.299575, 0.856462"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[11]_redg_min*/ + +} /* end of pin usb_io_pu_cal_o[11] */ + +pin("usb_io_pu_cal_o[10]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.044612 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : usb_io_pu_cal_o[10]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.310563, 0.333600, 0.370684, 0.776237, 1.666485",\ + "0.397928, 0.420965, 0.458048, 0.863602, 1.753849",\ + "0.478891, 0.501955, 0.539050, 0.944602, 1.834849",\ + "0.536743, 0.559839, 0.596947, 1.002497, 1.892744",\ + "0.858742, 0.881931, 0.919078, 1.324622, 2.214868"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.051871, 0.077785, 0.129094, 0.852080, 2.449966",\ + "0.051871, 0.077785, 0.129094, 0.852080, 2.449966",\ + "0.051946, 0.077865, 0.129119, 0.852080, 2.449966",\ + "0.052034, 0.077959, 0.129147, 0.852081, 2.449966",\ + "0.052292, 0.078232, 0.129231, 0.852081, 2.450003"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.206143, 0.216949, 0.231236, 0.371702, 0.676873",\ + "0.294617, 0.305423, 0.319710, 0.460177, 0.765348",\ + "0.385375, 0.396181, 0.410468, 0.550935, 0.856106",\ + "0.450776, 0.461583, 0.475870, 0.616338, 0.921509",\ + "0.797902, 0.808713, 0.823006, 0.963477, 1.268652"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.025267, 0.034187, 0.048724, 0.301161, 0.860108",\ + "0.025267, 0.034187, 0.048724, 0.301161, 0.860108",\ + "0.025267, 0.034188, 0.048727, 0.301161, 0.860108",\ + "0.025268, 0.034189, 0.048730, 0.301161, 0.860108",\ + "0.025282, 0.034204, 0.048750, 0.301161, 0.860108"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[10]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.219758, 0.239385, 0.274833, 0.679189, 1.571066",\ + "0.308173, 0.327801, 0.363249, 0.767605, 1.659482",\ + "0.402556, 0.422183, 0.457632, 0.861987, 1.753864",\ + "0.470615, 0.490242, 0.525690, 0.930046, 1.821923",\ + "0.795255, 0.814880, 0.850328, 1.254683, 2.146560"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.037493, 0.066526, 0.127980, 0.850723, 2.444973",\ + "0.037493, 0.066526, 0.127980, 0.850723, 2.444973",\ + "0.037493, 0.066525, 0.127980, 0.850723, 2.444973",\ + "0.037493, 0.066525, 0.127980, 0.850723, 2.444972",\ + "0.037489, 0.066522, 0.127980, 0.850723, 2.444969"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.184074, 0.193673, 0.207304, 0.345941, 0.651849",\ + "0.268886, 0.278485, 0.292117, 0.430754, 0.736662",\ + "0.344994, 0.354592, 0.368223, 0.506860, 0.812768",\ + "0.399528, 0.409125, 0.422756, 0.561393, 0.867301",\ + "0.683921, 0.693531, 0.707168, 0.845803, 1.151711"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.024391, 0.033017, 0.047459, 0.299575, 0.856462",\ + "0.024391, 0.033017, 0.047459, 0.299575, 0.856462",\ + "0.024391, 0.033017, 0.047459, 0.299575, 0.856462",\ + "0.024391, 0.033017, 0.047459, 0.299575, 0.856462",\ + "0.024427, 0.033054, 0.047472, 0.299575, 0.856462"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[10]_redg_min*/ + +} /* end of pin usb_io_pu_cal_o[10] */ + +pin("usb_io_pu_cal_o[9]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.044612 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : usb_io_pu_cal_o[9]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.310563, 0.333600, 0.370684, 0.776237, 1.666485",\ + "0.397928, 0.420965, 0.458048, 0.863602, 1.753849",\ + "0.478891, 0.501955, 0.539050, 0.944602, 1.834849",\ + "0.536743, 0.559839, 0.596947, 1.002497, 1.892744",\ + "0.858742, 0.881931, 0.919078, 1.324622, 2.214868"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.051871, 0.077785, 0.129094, 0.852080, 2.449964",\ + "0.051871, 0.077785, 0.129094, 0.852080, 2.449965",\ + "0.051946, 0.077865, 0.129119, 0.852080, 2.449965",\ + "0.052034, 0.077959, 0.129147, 0.852081, 2.449965",\ + "0.052292, 0.078232, 0.129231, 0.852081, 2.449997"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.209465, 0.219196, 0.232970, 0.371719, 0.677621",\ + "0.298173, 0.307904, 0.321678, 0.460428, 0.766330",\ + "0.393912, 0.403643, 0.417418, 0.556169, 0.862071",\ + "0.463358, 0.473091, 0.486867, 0.625618, 0.931520",\ + "0.828290, 0.838027, 0.851809, 0.990566, 1.296468"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.025267, 0.034187, 0.048739, 0.301161, 0.860107",\ + "0.025267, 0.034187, 0.048740, 0.301161, 0.860107",\ + "0.025267, 0.034188, 0.048743, 0.301161, 0.860107",\ + "0.025268, 0.034189, 0.048747, 0.301161, 0.860107",\ + "0.025282, 0.034204, 0.048767, 0.301161, 0.860107"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[9]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.202317, 0.221942, 0.257390, 0.661745, 1.553622",\ + "0.290456, 0.310081, 0.345529, 0.749884, 1.641761",\ + "0.379864, 0.399489, 0.434937, 0.839292, 1.731169",\ + "0.443880, 0.463505, 0.498953, 0.903308, 1.795185",\ + "0.771045, 0.790669, 0.826116, 1.230471, 2.122348"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.037489, 0.066522, 0.127980, 0.850724, 2.444973",\ + "0.037489, 0.066522, 0.127980, 0.850724, 2.444973",\ + "0.037489, 0.066522, 0.127980, 0.850724, 2.444973",\ + "0.037489, 0.066522, 0.127980, 0.850724, 2.444972",\ + "0.037486, 0.066519, 0.127980, 0.850725, 2.444969"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.178388, 0.187993, 0.201627, 0.340263, 0.646171",\ + "0.265760, 0.275365, 0.289000, 0.427635, 0.733544",\ + "0.345043, 0.355588, 0.369648, 0.508490, 0.814398",\ + "0.399593, 0.410134, 0.424192, 0.564475, 0.869603",\ + "0.684147, 0.694701, 0.708766, 0.849054, 1.154177"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.024411, 0.033033, 0.047459, 0.299575, 0.856462",\ + "0.024411, 0.033033, 0.047459, 0.299575, 0.856462",\ + "0.024411, 0.033033, 0.047459, 0.299575, 0.856462",\ + "0.024411, 0.033033, 0.047459, 0.299575, 0.856462",\ + "0.024446, 0.033071, 0.047472, 0.299576, 0.856462"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[9]_redg_min*/ + +} /* end of pin usb_io_pu_cal_o[9] */ + +pin("usb_io_pu_cal_o[8]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.044612 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : usb_io_pu_cal_o[8]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.310563, 0.333600, 0.370684, 0.776237, 1.666485",\ + "0.397928, 0.420965, 0.458048, 0.863602, 1.753849",\ + "0.478891, 0.501955, 0.539050, 0.944602, 1.834849",\ + "0.536743, 0.559839, 0.596947, 1.002497, 1.892744",\ + "0.858742, 0.881931, 0.919078, 1.324622, 2.214868"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.051871, 0.077785, 0.129094, 0.852080, 2.449966",\ + "0.051871, 0.077785, 0.129094, 0.852080, 2.449966",\ + "0.051946, 0.077865, 0.129119, 0.852080, 2.449966",\ + "0.052034, 0.077959, 0.129147, 0.852081, 2.449966",\ + "0.052292, 0.078232, 0.129231, 0.852081, 2.449966"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.209465, 0.219196, 0.232970, 0.371719, 0.677621",\ + "0.297931, 0.307661, 0.321435, 0.460184, 0.766087",\ + "0.393912, 0.403643, 0.417418, 0.556169, 0.862071",\ + "0.463358, 0.473091, 0.486867, 0.625618, 0.931520",\ + "0.828290, 0.838027, 0.851809, 0.990566, 1.296468"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.025267, 0.034187, 0.048739, 0.301161, 0.860107",\ + "0.025267, 0.034187, 0.048739, 0.301161, 0.860107",\ + "0.025267, 0.034188, 0.048743, 0.301161, 0.860107",\ + "0.025268, 0.034189, 0.048747, 0.301161, 0.860107",\ + "0.025282, 0.034204, 0.048767, 0.301161, 0.860107"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[8]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.248424, 0.271436, 0.308509, 0.714064, 1.604311",\ + "0.336713, 0.359725, 0.396797, 0.802353, 1.692600",\ + "0.429673, 0.449299, 0.484746, 0.889101, 1.780978",\ + "0.486001, 0.505626, 0.541074, 0.945429, 1.837306",\ + "0.771045, 0.790669, 0.826116, 1.230471, 2.122348"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.037489, 0.066522, 0.127980, 0.850724, 2.444973",\ + "0.037489, 0.066522, 0.127980, 0.850724, 2.444973",\ + "0.037489, 0.066522, 0.127980, 0.850724, 2.444973",\ + "0.037489, 0.066522, 0.127980, 0.850724, 2.444972",\ + "0.037486, 0.066519, 0.127980, 0.850725, 2.444969"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.184129, 0.194678, 0.208740, 0.349027, 0.654152",\ + "0.268945, 0.279493, 0.293555, 0.433842, 0.738967",\ + "0.345043, 0.355588, 0.369648, 0.509933, 0.815059",\ + "0.399593, 0.410134, 0.424192, 0.564475, 0.869603",\ + "0.684147, 0.694701, 0.708766, 0.849054, 1.154177"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.024415, 0.033034, 0.047459, 0.299575, 0.856462",\ + "0.024415, 0.033034, 0.047459, 0.299575, 0.856462",\ + "0.024415, 0.033034, 0.047459, 0.299575, 0.856462",\ + "0.024415, 0.033034, 0.047459, 0.299575, 0.856462",\ + "0.024441, 0.033067, 0.047472, 0.299576, 0.856462"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[8]_redg_min*/ + +} /* end of pin usb_io_pu_cal_o[8] */ + +pin("usb_io_pu_cal_o[7]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.044612 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : usb_io_pu_cal_o[7]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.310638, 0.333683, 0.370769, 0.776322, 1.666569",\ + "0.398002, 0.421047, 0.458133, 0.863687, 1.753934",\ + "0.478900, 0.501952, 0.539042, 0.944594, 1.834842",\ + "0.536750, 0.559833, 0.596935, 1.002486, 1.892733",\ + "0.841468, 0.864657, 0.901804, 1.307347, 2.197594"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.051891, 0.077808, 0.129101, 0.852080, 2.449966",\ + "0.051892, 0.077808, 0.129101, 0.852080, 2.449966",\ + "0.051912, 0.077829, 0.129108, 0.852080, 2.449966",\ + "0.051998, 0.077921, 0.129136, 0.852080, 2.449966",\ + "0.052293, 0.078232, 0.129231, 0.852081, 2.450003"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.213971, 0.224767, 0.239042, 0.379500, 0.684663",\ + "0.302629, 0.313425, 0.327700, 0.468158, 0.773321",\ + "0.398375, 0.409171, 0.423447, 0.563905, 0.869068",\ + "0.467906, 0.478703, 0.492979, 0.633438, 0.938602",\ + "0.835457, 0.846260, 0.860543, 1.001007, 1.306175"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.025238, 0.034155, 0.048727, 0.301163, 0.860108",\ + "0.025238, 0.034155, 0.048727, 0.301163, 0.860108",\ + "0.025238, 0.034156, 0.048728, 0.301163, 0.860108",\ + "0.025240, 0.034158, 0.048730, 0.301163, 0.860108",\ + "0.025257, 0.034176, 0.048751, 0.301163, 0.860108"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[7]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.205226, 0.224853, 0.260301, 0.664656, 1.556533",\ + "0.293604, 0.313232, 0.348681, 0.753036, 1.644913",\ + "0.383357, 0.402977, 0.438423, 0.842777, 1.734654",\ + "0.447610, 0.467222, 0.502663, 0.907016, 1.798893",\ + "0.789341, 0.809115, 0.844630, 1.249013, 2.140893"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.037493, 0.066493, 0.127978, 0.850658, 2.444959",\ + "0.037493, 0.066493, 0.127978, 0.850658, 2.444959",\ + "0.037493, 0.066493, 0.127978, 0.850658, 2.444959",\ + "0.037493, 0.066493, 0.127978, 0.850658, 2.444959",\ + "0.037854, 0.066833, 0.128000, 0.850658, 2.444959"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.176807, 0.187341, 0.201395, 0.341364, 0.646807",\ + "0.264176, 0.274709, 0.288763, 0.428735, 0.734175",\ + "0.344994, 0.354592, 0.368223, 0.506860, 0.812768",\ + "0.399528, 0.409125, 0.422756, 0.561393, 0.867301",\ + "0.683921, 0.693531, 0.707168, 0.845803, 1.151711"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.024391, 0.033017, 0.047448, 0.299575, 0.856488",\ + "0.024391, 0.033017, 0.047448, 0.299575, 0.856488",\ + "0.024391, 0.033017, 0.047448, 0.299575, 0.856488",\ + "0.024391, 0.033017, 0.047450, 0.299575, 0.856488",\ + "0.024427, 0.033054, 0.047464, 0.299575, 0.856488"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[7]_redg_min*/ + +} /* end of pin usb_io_pu_cal_o[7] */ + +pin("usb_io_pu_cal_o[6]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.044612 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : usb_io_pu_cal_o[6]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.310638, 0.333683, 0.370769, 0.776322, 1.666569",\ + "0.398002, 0.421047, 0.458133, 0.863687, 1.753934",\ + "0.478900, 0.501952, 0.539042, 0.944594, 1.834842",\ + "0.536750, 0.559833, 0.596935, 1.002486, 1.892733",\ + "0.841468, 0.864657, 0.901804, 1.307347, 2.197594"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.051891, 0.077808, 0.129101, 0.852080, 2.449966",\ + "0.051892, 0.077808, 0.129101, 0.852080, 2.449966",\ + "0.051912, 0.077829, 0.129108, 0.852080, 2.449966",\ + "0.051998, 0.077921, 0.129136, 0.852080, 2.449966",\ + "0.052293, 0.078232, 0.129231, 0.852081, 2.450003"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.213971, 0.224767, 0.239042, 0.379500, 0.684663",\ + "0.302629, 0.313425, 0.327700, 0.468158, 0.773321",\ + "0.398375, 0.409171, 0.423447, 0.563905, 0.869068",\ + "0.467906, 0.478703, 0.492979, 0.633438, 0.938602",\ + "0.835457, 0.846260, 0.860543, 1.001007, 1.306175"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.025238, 0.034155, 0.048724, 0.301163, 0.860108",\ + "0.025238, 0.034155, 0.048724, 0.301163, 0.860108",\ + "0.025238, 0.034156, 0.048727, 0.301163, 0.860108",\ + "0.025240, 0.034158, 0.048730, 0.301163, 0.860108",\ + "0.025257, 0.034176, 0.048750, 0.301163, 0.860108"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[6]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.219758, 0.239385, 0.274833, 0.679189, 1.571066",\ + "0.308173, 0.327801, 0.363249, 0.767605, 1.659482",\ + "0.402556, 0.422183, 0.457632, 0.861987, 1.753864",\ + "0.469866, 0.490242, 0.525690, 0.930046, 1.821923",\ + "0.795255, 0.814880, 0.850328, 1.254683, 2.146560"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.037493, 0.066526, 0.127980, 0.850723, 2.444963",\ + "0.037493, 0.066526, 0.127980, 0.850723, 2.444963",\ + "0.037493, 0.066525, 0.127980, 0.850723, 2.444963",\ + "0.037493, 0.066525, 0.127980, 0.850723, 2.444962",\ + "0.037489, 0.066522, 0.127980, 0.850723, 2.444959"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.176807, 0.187341, 0.201395, 0.341676, 0.646807",\ + "0.264176, 0.274709, 0.288763, 0.429043, 0.734175",\ + "0.344994, 0.354592, 0.368223, 0.506860, 0.812768",\ + "0.399528, 0.409125, 0.422756, 0.561393, 0.867301",\ + "0.683921, 0.693531, 0.707168, 0.845803, 1.151711"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.024391, 0.033017, 0.047448, 0.299575, 0.856488",\ + "0.024391, 0.033017, 0.047448, 0.299575, 0.856488",\ + "0.024391, 0.033017, 0.047448, 0.299575, 0.856488",\ + "0.024391, 0.033017, 0.047450, 0.299575, 0.856488",\ + "0.024427, 0.033054, 0.047464, 0.299575, 0.856488"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[6]_redg_min*/ + +} /* end of pin usb_io_pu_cal_o[6] */ + +pin("usb_io_pu_cal_o[5]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.044612 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : usb_io_pu_cal_o[5]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.320620, 0.341983, 0.378211, 0.782894, 1.674796",\ + "0.407985, 0.429348, 0.465575, 0.870258, 1.762161",\ + "0.488889, 0.510256, 0.546486, 0.951170, 1.843073",\ + "0.546764, 0.568152, 0.604391, 1.009078, 1.900981",\ + "0.851568, 0.873026, 0.909296, 1.313997, 2.205901"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.044601, 0.070156, 0.128218, 0.852056, 2.450125",\ + "0.044663, 0.070159, 0.128218, 0.852056, 2.450125",\ + "0.044669, 0.070166, 0.128219, 0.852056, 2.450125",\ + "0.044669, 0.070209, 0.128222, 0.852056, 2.450127",\ + "0.046118, 0.071698, 0.128231, 0.852061, 2.450134"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.216513, 0.226251, 0.240034, 0.378792, 0.684694",\ + "0.305171, 0.314909, 0.328692, 0.467450, 0.773352",\ + "0.400916, 0.410655, 0.424439, 0.563197, 0.869098",\ + "0.470448, 0.480187, 0.493971, 0.632730, 0.938632",\ + "0.838001, 0.847745, 0.861536, 1.000300, 1.306202"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.025212, 0.034126, 0.048771, 0.301166, 0.860107",\ + "0.025213, 0.034127, 0.048771, 0.301166, 0.860107",\ + "0.025216, 0.034130, 0.048772, 0.301166, 0.860107",\ + "0.025218, 0.034133, 0.048774, 0.301166, 0.860107",\ + "0.025235, 0.034151, 0.048795, 0.301166, 0.860107"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[5]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.194489, 0.214889, 0.250877, 0.656605, 1.546869",\ + "0.282628, 0.303028, 0.339015, 0.744743, 1.635008",\ + "0.372036, 0.392436, 0.428424, 0.834152, 1.724416",\ + "0.436052, 0.456452, 0.492440, 0.898167, 1.788432",\ + "0.763219, 0.783617, 0.819604, 1.225332, 2.115596"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.041711, 0.070060, 0.126728, 0.849963, 2.447347",\ + "0.041711, 0.070060, 0.126728, 0.849963, 2.447347",\ + "0.041711, 0.070060, 0.126728, 0.849963, 2.447347",\ + "0.041711, 0.070060, 0.126728, 0.849963, 2.447347",\ + "0.041716, 0.070054, 0.126726, 0.849962, 2.447349"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.175899, 0.186544, 0.200656, 0.340982, 0.646065",\ + "0.263271, 0.273916, 0.288028, 0.428355, 0.733437",\ + "0.344128, 0.354771, 0.368883, 0.509209, 0.814291",\ + "0.401818, 0.412460, 0.426571, 0.566896, 0.871980",\ + "0.705550, 0.716209, 0.730328, 0.870579, 1.175736"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.024130, 0.032772, 0.047558, 0.299569, 0.856133",\ + "0.024130, 0.032772, 0.047558, 0.299569, 0.856133",\ + "0.024130, 0.032772, 0.047558, 0.299569, 0.856133",\ + "0.024130, 0.032776, 0.047558, 0.299569, 0.856133",\ + "0.024160, 0.032809, 0.047574, 0.299570, 0.856133"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[5]_redg_min*/ + +} /* end of pin usb_io_pu_cal_o[5] */ + +pin("usb_io_pu_cal_o[4]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.044612 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : usb_io_pu_cal_o[4]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.320620, 0.341983, 0.378211, 0.782894, 1.674796",\ + "0.407985, 0.429348, 0.465575, 0.870258, 1.762161",\ + "0.488889, 0.510256, 0.546486, 0.951170, 1.843073",\ + "0.546764, 0.568152, 0.604391, 1.009078, 1.900981",\ + "0.851568, 0.873026, 0.909296, 1.313997, 2.205901"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.044695, 0.070193, 0.128218, 0.852056, 2.450125",\ + "0.044695, 0.070193, 0.128218, 0.852056, 2.450125",\ + "0.044695, 0.070193, 0.128219, 0.852056, 2.450125",\ + "0.044695, 0.070209, 0.128222, 0.852056, 2.450127",\ + "0.044695, 0.070356, 0.128231, 0.852056, 2.450134"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.216513, 0.226251, 0.240034, 0.378792, 0.684694",\ + "0.305171, 0.314909, 0.328692, 0.467450, 0.773352",\ + "0.400916, 0.410655, 0.424439, 0.563197, 0.869098",\ + "0.470448, 0.480187, 0.493971, 0.632730, 0.938632",\ + "0.838001, 0.847745, 0.861536, 1.000300, 1.306202"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.025212, 0.034126, 0.048771, 0.301166, 0.860107",\ + "0.025212, 0.034126, 0.048771, 0.301166, 0.860107",\ + "0.025216, 0.034130, 0.048772, 0.301166, 0.860107",\ + "0.025218, 0.034133, 0.048774, 0.301166, 0.860107",\ + "0.025235, 0.034151, 0.048795, 0.301166, 0.860107"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[4]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.238935, 0.260283, 0.296504, 0.701185, 1.593087",\ + "0.327362, 0.348711, 0.384931, 0.789612, 1.681514",\ + "0.416458, 0.437806, 0.474027, 0.878708, 1.770610",\ + "0.478173, 0.498573, 0.534561, 0.940289, 1.830553",\ + "0.763219, 0.783617, 0.819604, 1.225332, 2.115596"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.041711, 0.070060, 0.126728, 0.849963, 2.447347",\ + "0.041711, 0.070060, 0.126728, 0.849963, 2.447347",\ + "0.041711, 0.070060, 0.126728, 0.849963, 2.447347",\ + "0.041711, 0.070060, 0.126728, 0.849963, 2.447347",\ + "0.041716, 0.070054, 0.126726, 0.849962, 2.447349"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.179257, 0.188774, 0.202365, 0.341012, 0.646923",\ + "0.266626, 0.276142, 0.289732, 0.428379, 0.734291",\ + "0.347482, 0.356996, 0.370585, 0.509232, 0.815144",\ + "0.405200, 0.414714, 0.428304, 0.566951, 0.872863",\ + "0.708812, 0.718338, 0.731933, 0.870579, 1.176490"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.024130, 0.032772, 0.047559, 0.299569, 0.856139",\ + "0.024130, 0.032772, 0.047559, 0.299569, 0.856139",\ + "0.024130, 0.032772, 0.047559, 0.299569, 0.856139",\ + "0.024130, 0.032776, 0.047559, 0.299569, 0.856139",\ + "0.024160, 0.032809, 0.047572, 0.299570, 0.856139"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[4]_redg_min*/ + +} /* end of pin usb_io_pu_cal_o[4] */ + +pin("usb_io_pu_cal_o[3]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.044612 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : usb_io_pu_cal_o[3]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.320745, 0.342120, 0.378352, 0.783037, 1.674940",\ + "0.408109, 0.429484, 0.465717, 0.870402, 1.762305",\ + "0.488983, 0.510358, 0.546591, 0.951276, 1.843179",\ + "0.546734, 0.568108, 0.604341, 1.009026, 1.900929",\ + "0.851113, 0.872490, 0.908724, 1.313410, 2.205313"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.044702, 0.070201, 0.128220, 0.852056, 2.450126",\ + "0.044702, 0.070201, 0.128220, 0.852056, 2.450126",\ + "0.044702, 0.070201, 0.128220, 0.852056, 2.450126",\ + "0.044702, 0.070201, 0.128220, 0.852056, 2.450126",\ + "0.046369, 0.071964, 0.128220, 0.852062, 2.450126"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.216415, 0.226147, 0.239922, 0.378673, 0.684575",\ + "0.304894, 0.314626, 0.328401, 0.467152, 0.773054",\ + "0.400819, 0.410552, 0.424328, 0.563079, 0.868981",\ + "0.469454, 0.479186, 0.492962, 0.631714, 0.937616",\ + "0.837901, 0.847639, 0.861421, 1.000178, 1.306080"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.025202, 0.034115, 0.048744, 0.301167, 0.860107",\ + "0.025202, 0.034115, 0.048744, 0.301167, 0.860107",\ + "0.025203, 0.034116, 0.048746, 0.301167, 0.860107",\ + "0.025205, 0.034118, 0.048746, 0.301167, 0.860107",\ + "0.025222, 0.034137, 0.048767, 0.301167, 0.860107"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[3]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.197396, 0.217798, 0.253787, 0.659515, 1.549779",\ + "0.285773, 0.306177, 0.342166, 0.747894, 1.638158",\ + "0.375534, 0.395928, 0.431912, 0.837641, 1.727905",\ + "0.439799, 0.460179, 0.496157, 0.901887, 1.792151",\ + "0.781328, 0.801955, 0.838037, 1.243750, 2.134013"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.041723, 0.069999, 0.126709, 0.849959, 2.447141",\ + "0.041723, 0.069999, 0.126709, 0.849959, 2.447141",\ + "0.041723, 0.069999, 0.126709, 0.849959, 2.447141",\ + "0.041723, 0.069999, 0.126709, 0.849959, 2.447141",\ + "0.041728, 0.070141, 0.126932, 0.849959, 2.447141"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.177011, 0.187648, 0.201756, 0.342079, 0.647165",\ + "0.264382, 0.275019, 0.289127, 0.429450, 0.734536",\ + "0.342508, 0.353145, 0.367252, 0.507575, 0.812661",\ + "0.397042, 0.407678, 0.421785, 0.562107, 0.867194",\ + "0.681430, 0.692081, 0.706196, 0.846525, 1.151605"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.024102, 0.032747, 0.047552, 0.299568, 0.856157",\ + "0.024102, 0.032747, 0.047552, 0.299568, 0.856157",\ + "0.024102, 0.032747, 0.047552, 0.299568, 0.856157",\ + "0.024102, 0.032747, 0.047552, 0.299568, 0.856157",\ + "0.024132, 0.032784, 0.047567, 0.299569, 0.856157"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[3]_redg_min*/ + +} /* end of pin usb_io_pu_cal_o[3] */ + +pin("usb_io_pu_cal_o[2]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.044612 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : usb_io_pu_cal_o[2]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.320745, 0.342120, 0.378352, 0.783037, 1.674940",\ + "0.408109, 0.429484, 0.465717, 0.870402, 1.762305",\ + "0.488983, 0.510358, 0.546591, 0.951276, 1.843179",\ + "0.546734, 0.568108, 0.604341, 1.009026, 1.900929",\ + "0.851113, 0.872490, 0.908724, 1.313410, 2.205313"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.044702, 0.070201, 0.128220, 0.852056, 2.450126",\ + "0.044702, 0.070201, 0.128220, 0.852056, 2.450126",\ + "0.044702, 0.070201, 0.128220, 0.852056, 2.450126",\ + "0.044702, 0.070201, 0.128220, 0.852056, 2.450126",\ + "0.046369, 0.071964, 0.128220, 0.852062, 2.450126"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.216415, 0.226147, 0.239922, 0.378673, 0.684575",\ + "0.304894, 0.314626, 0.328401, 0.467152, 0.773054",\ + "0.400819, 0.410552, 0.424328, 0.563079, 0.868981",\ + "0.469454, 0.479186, 0.492962, 0.631714, 0.937616",\ + "0.837901, 0.847639, 0.861421, 1.000178, 1.306080"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.025200, 0.034112, 0.048744, 0.301167, 0.860107",\ + "0.025200, 0.034112, 0.048744, 0.301167, 0.860107",\ + "0.025202, 0.034115, 0.048746, 0.301167, 0.860107",\ + "0.025205, 0.034118, 0.048746, 0.301166, 0.860107",\ + "0.025221, 0.034136, 0.048767, 0.301165, 0.860107"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[2]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.211928, 0.232331, 0.268319, 0.674047, 1.564311",\ + "0.300343, 0.320746, 0.356735, 0.762463, 1.652727",\ + "0.394726, 0.415129, 0.451117, 0.856845, 1.747110",\ + "0.462784, 0.483187, 0.519176, 0.924904, 1.815168",\ + "0.787427, 0.807827, 0.843815, 1.249543, 2.139807"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.041723, 0.070068, 0.126730, 0.849961, 2.447344",\ + "0.041723, 0.070068, 0.126730, 0.849961, 2.447344",\ + "0.041723, 0.070068, 0.126730, 0.849961, 2.447344",\ + "0.041723, 0.070068, 0.126730, 0.849961, 2.447345",\ + "0.041728, 0.070061, 0.126728, 0.849959, 2.447347"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.181588, 0.192225, 0.206333, 0.346656, 0.651742",\ + "0.266400, 0.277038, 0.291146, 0.431469, 0.736554",\ + "0.342508, 0.353145, 0.367252, 0.507575, 0.812661",\ + "0.397042, 0.407678, 0.421785, 0.562107, 0.867194",\ + "0.681430, 0.692081, 0.706196, 0.846525, 1.151605"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.024102, 0.032747, 0.047552, 0.299568, 0.856157",\ + "0.024102, 0.032747, 0.047552, 0.299568, 0.856157",\ + "0.024102, 0.032747, 0.047552, 0.299568, 0.856157",\ + "0.024102, 0.032747, 0.047552, 0.299568, 0.856157",\ + "0.024132, 0.032784, 0.047567, 0.299569, 0.856157"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[2]_redg_min*/ + +} /* end of pin usb_io_pu_cal_o[2] */ + +pin("usb_io_pu_cal_o[1]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.044612 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : usb_io_pu_cal_o[1]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.320745, 0.342120, 0.378352, 0.783037, 1.674940",\ + "0.408109, 0.429484, 0.465717, 0.870402, 1.762305",\ + "0.488983, 0.510358, 0.546591, 0.951276, 1.843179",\ + "0.546734, 0.568108, 0.604341, 1.009026, 1.900929",\ + "0.851113, 0.872490, 0.908724, 1.313410, 2.205313"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.044601, 0.070181, 0.128220, 0.852056, 2.450126",\ + "0.044663, 0.070181, 0.128220, 0.852056, 2.450126",\ + "0.044669, 0.070181, 0.128220, 0.852056, 2.450126",\ + "0.044669, 0.070181, 0.128220, 0.852056, 2.450126",\ + "0.046118, 0.071698, 0.128220, 0.852061, 2.450126"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.216415, 0.226147, 0.239922, 0.378673, 0.684575",\ + "0.304894, 0.314626, 0.328401, 0.467152, 0.773054",\ + "0.400819, 0.410552, 0.424328, 0.563079, 0.868981",\ + "0.469454, 0.479186, 0.492962, 0.631714, 0.937616",\ + "0.837901, 0.847639, 0.861421, 1.000178, 1.306080"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.025212, 0.034126, 0.048744, 0.301166, 0.860107",\ + "0.025213, 0.034127, 0.048744, 0.301166, 0.860107",\ + "0.025216, 0.034130, 0.048746, 0.301165, 0.860107",\ + "0.025218, 0.034133, 0.048746, 0.301165, 0.860107",\ + "0.025235, 0.034151, 0.048767, 0.301164, 0.860107"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[1]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.194489, 0.214889, 0.250877, 0.656605, 1.546869",\ + "0.282628, 0.303028, 0.339015, 0.744743, 1.635008",\ + "0.372036, 0.392436, 0.428424, 0.834152, 1.724416",\ + "0.436052, 0.456452, 0.492440, 0.898167, 1.788432",\ + "0.763219, 0.783617, 0.819604, 1.225332, 2.115596"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.041723, 0.070060, 0.126728, 0.849961, 2.447347",\ + "0.041723, 0.070060, 0.126728, 0.849961, 2.447347",\ + "0.041723, 0.070060, 0.126728, 0.849961, 2.447347",\ + "0.041723, 0.070060, 0.126728, 0.849961, 2.447347",\ + "0.041728, 0.070054, 0.126726, 0.849959, 2.447349"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.175899, 0.186544, 0.200656, 0.340982, 0.646065",\ + "0.263271, 0.273916, 0.288028, 0.428355, 0.733437",\ + "0.344128, 0.354771, 0.368883, 0.509209, 0.814291",\ + "0.401818, 0.412460, 0.426571, 0.566896, 0.871980",\ + "0.705550, 0.716209, 0.730328, 0.870660, 1.175736"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.024102, 0.032747, 0.047558, 0.299568, 0.856133",\ + "0.024102, 0.032747, 0.047558, 0.299568, 0.856133",\ + "0.024102, 0.032747, 0.047558, 0.299568, 0.856133",\ + "0.024102, 0.032747, 0.047558, 0.299568, 0.856133",\ + "0.024132, 0.032784, 0.047574, 0.299569, 0.856133"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[1]_redg_min*/ + +} /* end of pin usb_io_pu_cal_o[1] */ + +pin("usb_io_pu_cal_o[0]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.044612 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : usb_io_pu_cal_o[0]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.320745, 0.342120, 0.378352, 0.783037, 1.674940",\ + "0.408109, 0.429484, 0.465717, 0.870402, 1.762305",\ + "0.488983, 0.510358, 0.546591, 0.951276, 1.843179",\ + "0.546734, 0.568108, 0.604341, 1.009026, 1.900929",\ + "0.851113, 0.872490, 0.908724, 1.313410, 2.205313"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.044695, 0.070193, 0.128220, 0.852056, 2.450126",\ + "0.044695, 0.070193, 0.128220, 0.852056, 2.450126",\ + "0.044695, 0.070193, 0.128220, 0.852056, 2.450126",\ + "0.044695, 0.070193, 0.128220, 0.852056, 2.450126",\ + "0.044688, 0.070187, 0.128220, 0.852056, 2.450126"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.216415, 0.226147, 0.239922, 0.378673, 0.684575",\ + "0.304894, 0.314626, 0.328401, 0.467152, 0.773054",\ + "0.400819, 0.410552, 0.424328, 0.563079, 0.868981",\ + "0.469454, 0.479186, 0.492962, 0.631714, 0.937616",\ + "0.837901, 0.847639, 0.861421, 1.000178, 1.306080"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.025212, 0.034126, 0.048744, 0.301166, 0.860107",\ + "0.025212, 0.034126, 0.048744, 0.301166, 0.860107",\ + "0.025216, 0.034130, 0.048746, 0.301165, 0.860107",\ + "0.025218, 0.034133, 0.048746, 0.301165, 0.860107",\ + "0.025235, 0.034151, 0.048767, 0.301164, 0.860107"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[0]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.253595, 0.273995, 0.309982, 0.715710, 1.605975",\ + "0.340966, 0.361366, 0.397353, 0.803081, 1.693346",\ + "0.421845, 0.442245, 0.478233, 0.883961, 1.774225",\ + "0.478173, 0.498573, 0.534561, 0.940289, 1.830553",\ + "0.763219, 0.783617, 0.819604, 1.225332, 2.115596"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.041723, 0.070060, 0.126728, 0.849961, 2.447347",\ + "0.041723, 0.070060, 0.126728, 0.849961, 2.447347",\ + "0.041723, 0.070060, 0.126728, 0.849961, 2.447347",\ + "0.041723, 0.070060, 0.126728, 0.849961, 2.447347",\ + "0.041728, 0.070054, 0.126726, 0.849959, 2.447349"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.187072, 0.197718, 0.211831, 0.352158, 0.657240",\ + "0.275510, 0.286157, 0.300270, 0.440597, 0.745678",\ + "0.366248, 0.376893, 0.391005, 0.531331, 0.836413",\ + "0.431562, 0.442205, 0.456315, 0.596641, 0.901724",\ + "0.774613, 0.785269, 0.799387, 0.939719, 1.244796"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.024102, 0.032747, 0.047559, 0.299568, 0.856139",\ + "0.024102, 0.032747, 0.047559, 0.299568, 0.856139",\ + "0.024102, 0.032747, 0.047559, 0.299568, 0.856139",\ + "0.024102, 0.032747, 0.047559, 0.299568, 0.856139",\ + "0.024132, 0.032784, 0.047572, 0.299569, 0.856139"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[0]_redg_min*/ + +} /* end of pin usb_io_pu_cal_o[0] */ +} /* end of bus usb_io_pu_cal_o */ + +pin("adc_pd_i") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000990 ; + + /* Other user defined attributes. */ + original_pin : adc_pd_i; + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.145974, 0.070413, 0.002322, -0.008532, 0.040411",\ + "0.237817, 0.162519, 0.094482, 0.084652, 0.136438",\ + "0.327313, 0.252083, 0.184412, 0.176262, 0.232381",\ + "0.476369, 0.401228, 0.333138, 0.324719, 0.380566",\ + "0.727129, 0.652156, 0.582810, 0.572596, 0.624823"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.143537, 0.097803, 0.067619, 0.059035, 0.070038",\ + "0.237266, 0.190708, 0.160460, 0.151771, 0.162549",\ + "0.329371, 0.281569, 0.251215, 0.242361, 0.252794",\ + "0.482853, 0.435010, 0.403977, 0.394743, 0.404895",\ + "0.739407, 0.691484, 0.659103, 0.649115, 0.658707"); + } + + } /* end of arc clk_ast_adc_i_adc_pd_i_stupr*/ + + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.059104, 0.006478, 0.063764, 0.149867, 0.326932",\ + "-0.151184, -0.084885, -0.026675, 0.059343, 0.235088",\ + "-0.241063, -0.173618, -0.113766, -0.027872, 0.145596",\ + "-0.389953, -0.320592, -0.259252, -0.172562, 0.001425",\ + "-0.640054, -0.566890, -0.503114, -0.414430, -0.237640"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.075633, -0.033180, 0.001225, 0.107355, 0.367997",\ + "-0.168712, -0.126409, -0.091657, -0.008939, 0.184913",\ + "-0.259774, -0.217681, -0.182405, -0.135026, -0.041991",\ + "-0.408979, -0.365800, -0.330498, -0.282705, -0.188522",\ + "-0.657040, -0.611703, -0.576351, -0.527733, -0.431269"); + } + + } /* end of arc clk_ast_adc_i_adc_pd_i_hldr*/ + +} /* end of pin adc_pd_i */ + +pin("adc_a0_ai") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : adc_a0_ai; +} /* end of pin adc_a0_ai */ + +pin("adc_a1_ai") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : adc_a1_ai; +} /* end of pin adc_a1_ai */ +bus ( adc_chnsel_i ) { + + bus_type : BUS2_type5 ; + direction : input ; + +pin("adc_chnsel_i[1]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000460 ; + + /* Other user defined attributes. */ + original_pin : adc_chnsel_i[1]; + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.500117, 0.461902, 0.438325, 0.435047, 0.453355",\ + "0.595615, 0.557400, 0.533823, 0.530545, 0.548853",\ + "0.695525, 0.657310, 0.633733, 0.630455, 0.648763",\ + "0.875461, 0.837246, 0.813669, 0.810391, 0.828699",\ + "1.191947, 1.153731, 1.130154, 1.126876, 1.145184"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.605397, 0.537315, 0.507057, 0.526616, 0.751141",\ + "0.681420, 0.613337, 0.583080, 0.602638, 0.827164",\ + "0.783637, 0.715554, 0.685297, 0.704855, 0.929381",\ + "0.996963, 0.928735, 0.898477, 0.918181, 1.142707",\ + "1.384407, 1.315680, 1.285422, 1.305625, 1.530151"); + } + + } /* end of arc clk_ast_adc_i_adc_chnsel_i[1]_stupr*/ + + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.108536, -0.069519, -0.039211, 0.000204, 0.221057",\ + "-0.207833, -0.168834, -0.138446, -0.098987, 0.125559",\ + "-0.311546, -0.272599, -0.241997, -0.202419, 0.025649",\ + "-0.492274, -0.453433, -0.422380, -0.382553, -0.154287",\ + "-0.791907, -0.753246, -0.721402, -0.681127, -0.470772"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.305777, -0.243225, -0.192080, -0.118367, 0.030759",\ + "-0.381816, -0.319265, -0.268119, -0.194406, -0.045281",\ + "-0.483977, -0.421325, -0.370075, -0.296389, -0.147462",\ + "-0.695975, -0.632864, -0.581137, -0.507574, -0.359554",\ + "-1.082510, -1.018340, -0.965517, -0.892237, -0.746305"); + } + + } /* end of arc clk_ast_adc_i_adc_chnsel_i[1]_hldr*/ + +} /* end of pin adc_chnsel_i[1] */ + +pin("adc_chnsel_i[0]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000438 ; + + /* Other user defined attributes. */ + original_pin : adc_chnsel_i[0]; + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.501910, 0.463695, 0.440118, 0.436840, 0.455148",\ + "0.598688, 0.560473, 0.536896, 0.533618, 0.551926",\ + "0.702673, 0.664458, 0.640881, 0.637603, 0.655911",\ + "0.888472, 0.850257, 0.826680, 0.823402, 0.841710",\ + "1.218538, 1.180323, 1.156746, 1.153468, 1.171776"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.606473, 0.538391, 0.508134, 0.527691, 0.752217",\ + "0.684191, 0.616110, 0.585852, 0.605410, 0.829935",\ + "0.780333, 0.712252, 0.681994, 0.701552, 0.926077",\ + "0.980044, 0.911864, 0.881606, 0.901262, 1.125788",\ + "1.359676, 1.291175, 1.260918, 1.280894, 1.505420"); + } + + } /* end of arc clk_ast_adc_i_adc_chnsel_i[0]_stupr*/ + + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.110705, -0.071690, -0.041374, -0.001954, 0.219264",\ + "-0.211096, -0.172099, -0.141707, -0.102245, 0.122486",\ + "-0.318758, -0.279812, -0.249205, -0.209624, 0.018501",\ + "-0.505427, -0.466584, -0.435539, -0.395715, -0.167298",\ + "-0.819228, -0.780572, -0.748725, -0.708453, -0.497364"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.306862, -0.244315, -0.193173, -0.119459, 0.029674",\ + "-0.384597, -0.322050, -0.270908, -0.197194, -0.048061",\ + "-0.480694, -0.418072, -0.366852, -0.293158, -0.144173",\ + "-0.679326, -0.616367, -0.564798, -0.491194, -0.342874",\ + "-1.058081, -0.994264, -0.941806, -0.868432, -0.721804"); + } + + } /* end of arc clk_ast_adc_i_adc_chnsel_i[0]_hldr*/ + +} /* end of pin adc_chnsel_i[0] */ +} /* end of bus adc_chnsel_i */ +bus ( adc_d_o ) { + + bus_type : BUS10_type8 ; + direction : output ; + +pin("adc_d_o[9]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000474 ; + + /* Other user defined attributes. */ + original_pin : adc_d_o[9]; + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.043083, 0.198120, 0.374256, 0.697785, 1.344843",\ + "0.128923, 0.285295, 0.461364, 0.784501, 1.430777",\ + "0.210274, 0.373426, 0.549322, 0.872125, 1.517732",\ + "0.345402, 0.527885, 0.703101, 1.025419, 1.670053",\ + "0.557160, 0.787678, 0.963834, 1.284789, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.018401, 0.293911, 0.628602, 1.246589, 2.482563",\ + "0.023522, 0.294865, 0.630572, 1.246589, 2.482563",\ + "0.036913, 0.297173, 0.630608, 1.246589, 2.482563",\ + "0.064917, 0.305223, 0.630841, 1.247228, 2.482563",\ + "0.122287, 0.339635, 0.636985, 1.249173, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.062966, 0.171021, 0.282962, 0.487566, 0.896774",\ + "0.150539, 0.258340, 0.370243, 0.574871, 0.984127",\ + "0.230685, 0.338682, 0.450270, 0.654899, 1.064159",\ + "0.365948, 0.476706, 0.588287, 0.792199, 1.200024",\ + "0.578145, 0.699559, 0.811451, 1.015162, 1.422583"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.020571, 0.183996, 0.385207, 0.758292, 1.504462",\ + "0.020571, 0.184130, 0.385715, 0.758292, 1.504462",\ + "0.021496, 0.184130, 0.385715, 0.758292, 1.504462",\ + "0.027055, 0.184687, 0.385715, 0.758292, 1.504742",\ + "0.042630, 0.188229, 0.385715, 0.758292, 1.504742"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[9]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_adc_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.043083, 0.198120, 0.374256, 0.697785, 1.344843",\ + "0.128923, 0.285295, 0.461364, 0.784501, 1.430777",\ + "0.210274, 0.373426, 0.549322, 0.872125, 1.517732",\ + "0.345402, 0.527885, 0.703101, 1.025419, 1.670053",\ + "0.557160, 0.787678, 0.963834, 1.284789, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.018401, 0.293911, 0.628602, 1.245375, 2.473548",\ + "0.023522, 0.294865, 0.630572, 1.245375, 2.473548",\ + "0.036913, 0.297173, 0.630608, 1.245450, 2.473548",\ + "0.064917, 0.305223, 0.630841, 1.247228, 2.473548",\ + "0.122287, 0.339635, 0.636985, 1.249173, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.062966, 0.171021, 0.282962, 0.487566, 0.896774",\ + "0.150539, 0.258340, 0.370243, 0.574871, 0.984127",\ + "0.230685, 0.338682, 0.450270, 0.654899, 1.064159",\ + "0.365948, 0.476706, 0.588287, 0.792199, 1.200024",\ + "0.578145, 0.699559, 0.811451, 1.015162, 1.422583"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.020571, 0.183210, 0.383705, 0.756065, 1.500784",\ + "0.020571, 0.183210, 0.383705, 0.756065, 1.500784",\ + "0.021496, 0.183210, 0.383705, 0.756065, 1.500784",\ + "0.027055, 0.184687, 0.384226, 0.757731, 1.504742",\ + "0.042630, 0.188229, 0.384226, 0.757731, 1.504742"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[9]_redg_min*/ + + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018401, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.203067, 0.157249, 0.127058, 0.118464, 0.129443",\ + "0.207936, 0.162118, 0.131927, 0.123333, 0.134312",\ + "0.282684, 0.236865, 0.206674, 0.198080, 0.209060",\ + "0.376050, 0.329912, 0.299696, 0.291061, 0.301953",\ + "0.789608, 0.741801, 0.711356, 0.702451, 0.712846"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020571, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.248522, 0.173196, 0.105012, 0.094508, 0.144555",\ + "0.253666, 0.178340, 0.110157, 0.099653, 0.149700",\ + "0.325959, 0.250633, 0.182449, 0.171946, 0.221993",\ + "0.430477, 0.355166, 0.287060, 0.276913, 0.327879",\ + "0.906305, 0.831103, 0.763471, 0.755707, 0.812875"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[9]_stupr*/ + + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018401, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.129733, -0.087286, -0.052870, 0.052534, 0.311104",\ + "-0.134675, -0.092227, -0.057811, 0.047593, 0.306162",\ + "-0.208828, -0.166380, -0.131964, -0.026560, 0.232009",\ + "-0.298006, -0.255611, -0.221074, -0.123848, 0.111390",\ + "-0.695505, -0.653392, -0.618114, -0.570728, -0.477670"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020571, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.128225, -0.062545, -0.005224, 0.080862, 0.257839",\ + "-0.134070, -0.068391, -0.011070, 0.075016, 0.251993",\ + "-0.211053, -0.145374, -0.088052, -0.001967, 0.175010",\ + "-0.312522, -0.246536, -0.188774, -0.102722, 0.073645",\ + "-0.766129, -0.698256, -0.637868, -0.551957, -0.379066"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[9]_hldr*/ + +} /* end of pin adc_d_o[9] */ + +pin("adc_d_o[8]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000474 ; + + /* Other user defined attributes. */ + original_pin : adc_d_o[8]; + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.043083, 0.198120, 0.374256, 0.697785, 1.344843",\ + "0.128923, 0.285295, 0.461364, 0.784501, 1.430777",\ + "0.210274, 0.373426, 0.549322, 0.872125, 1.517732",\ + "0.345402, 0.527885, 0.703101, 1.025419, 1.670053",\ + "0.557160, 0.787678, 0.963834, 1.284789, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.018401, 0.293911, 0.628602, 1.246589, 2.482563",\ + "0.023522, 0.294865, 0.630572, 1.246589, 2.482563",\ + "0.036913, 0.297173, 0.630608, 1.246589, 2.482563",\ + "0.064917, 0.305223, 0.630841, 1.247228, 2.482563",\ + "0.122287, 0.339635, 0.636985, 1.249173, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.062966, 0.171021, 0.282962, 0.487566, 0.896774",\ + "0.150539, 0.258340, 0.370243, 0.574871, 0.984127",\ + "0.230685, 0.338682, 0.450270, 0.654899, 1.064159",\ + "0.365948, 0.476706, 0.588287, 0.792199, 1.200024",\ + "0.578145, 0.699559, 0.811451, 1.015162, 1.422583"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.020571, 0.183996, 0.385207, 0.758292, 1.504462",\ + "0.020571, 0.184130, 0.385715, 0.758292, 1.504462",\ + "0.021496, 0.184130, 0.385715, 0.758292, 1.504462",\ + "0.027055, 0.184687, 0.385715, 0.758292, 1.504742",\ + "0.042630, 0.188229, 0.385715, 0.758292, 1.504742"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[8]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_adc_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.043083, 0.198120, 0.374256, 0.697785, 1.344843",\ + "0.128923, 0.285295, 0.461364, 0.784501, 1.430777",\ + "0.210274, 0.373426, 0.549322, 0.872125, 1.517732",\ + "0.345402, 0.527885, 0.703101, 1.025419, 1.670053",\ + "0.557160, 0.787678, 0.963834, 1.284789, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.018401, 0.293911, 0.628602, 1.245375, 2.473548",\ + "0.023522, 0.294865, 0.630572, 1.245375, 2.473548",\ + "0.036913, 0.297173, 0.630608, 1.245450, 2.473548",\ + "0.064917, 0.305223, 0.630841, 1.247228, 2.473548",\ + "0.122287, 0.339635, 0.636985, 1.249173, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.062966, 0.171021, 0.282962, 0.487566, 0.896774",\ + "0.150539, 0.258340, 0.370243, 0.574871, 0.984127",\ + "0.230685, 0.338682, 0.450270, 0.654899, 1.064159",\ + "0.365948, 0.476706, 0.588287, 0.792199, 1.200024",\ + "0.578145, 0.699559, 0.811451, 1.015162, 1.422583"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.020571, 0.183210, 0.383705, 0.756065, 1.500784",\ + "0.020571, 0.183210, 0.383705, 0.756065, 1.500784",\ + "0.021496, 0.183210, 0.383705, 0.756065, 1.500784",\ + "0.027055, 0.184687, 0.384226, 0.757731, 1.504742",\ + "0.042630, 0.188229, 0.384226, 0.757731, 1.504742"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[8]_redg_min*/ + + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018401, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.203067, 0.157249, 0.127058, 0.118464, 0.129443",\ + "0.207936, 0.162118, 0.131927, 0.123333, 0.134312",\ + "0.282684, 0.236865, 0.206674, 0.198080, 0.209060",\ + "0.376050, 0.329912, 0.299696, 0.291061, 0.301953",\ + "0.789608, 0.741801, 0.711356, 0.702451, 0.712846"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020571, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.248522, 0.173196, 0.105012, 0.094508, 0.144555",\ + "0.253666, 0.178340, 0.110157, 0.099653, 0.149700",\ + "0.325959, 0.250633, 0.182449, 0.171946, 0.221993",\ + "0.430477, 0.355166, 0.287060, 0.276913, 0.327879",\ + "0.906305, 0.831103, 0.763471, 0.755707, 0.812875"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[8]_stupr*/ + + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018401, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.129733, -0.087286, -0.052870, 0.052534, 0.311104",\ + "-0.134675, -0.092227, -0.057811, 0.047593, 0.306162",\ + "-0.208828, -0.166380, -0.131964, -0.026560, 0.232009",\ + "-0.298006, -0.255611, -0.221074, -0.123848, 0.111390",\ + "-0.695505, -0.653392, -0.618114, -0.570728, -0.477670"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020571, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.128225, -0.062545, -0.005224, 0.080862, 0.257839",\ + "-0.134070, -0.068391, -0.011070, 0.075016, 0.251993",\ + "-0.211053, -0.145374, -0.088052, -0.001967, 0.175010",\ + "-0.312522, -0.246536, -0.188774, -0.102722, 0.073645",\ + "-0.766129, -0.698256, -0.637868, -0.551957, -0.379066"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[8]_hldr*/ + +} /* end of pin adc_d_o[8] */ + +pin("adc_d_o[7]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000474 ; + + /* Other user defined attributes. */ + original_pin : adc_d_o[7]; + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.043083, 0.198120, 0.374256, 0.697785, 1.344843",\ + "0.128923, 0.285295, 0.461364, 0.784501, 1.430777",\ + "0.210274, 0.373426, 0.549322, 0.872125, 1.517732",\ + "0.345402, 0.527885, 0.703101, 1.025419, 1.670053",\ + "0.557160, 0.787678, 0.963834, 1.284789, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.018401, 0.293911, 0.628602, 1.246589, 2.482563",\ + "0.023522, 0.294865, 0.630572, 1.246589, 2.482563",\ + "0.036913, 0.297173, 0.630608, 1.246589, 2.482563",\ + "0.064917, 0.305223, 0.630841, 1.247228, 2.482563",\ + "0.122287, 0.339635, 0.636985, 1.249173, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.062966, 0.171021, 0.282962, 0.487566, 0.896774",\ + "0.150539, 0.258340, 0.370243, 0.574871, 0.984127",\ + "0.230685, 0.338682, 0.450270, 0.654899, 1.064159",\ + "0.365948, 0.476706, 0.588287, 0.792199, 1.200024",\ + "0.578145, 0.699559, 0.811451, 1.015162, 1.422583"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.020571, 0.183996, 0.385207, 0.758292, 1.504462",\ + "0.020571, 0.184130, 0.385715, 0.758292, 1.504462",\ + "0.021496, 0.184130, 0.385715, 0.758292, 1.504462",\ + "0.027055, 0.184687, 0.385715, 0.758292, 1.504742",\ + "0.042630, 0.188229, 0.385715, 0.758292, 1.504742"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[7]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_adc_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.043083, 0.198120, 0.374256, 0.697785, 1.344843",\ + "0.128923, 0.285295, 0.461364, 0.784501, 1.430777",\ + "0.210274, 0.373426, 0.549322, 0.872125, 1.517732",\ + "0.345402, 0.527885, 0.703101, 1.025419, 1.670053",\ + "0.557160, 0.787678, 0.963834, 1.284789, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.018401, 0.293911, 0.628602, 1.245375, 2.473548",\ + "0.023522, 0.294865, 0.630572, 1.245375, 2.473548",\ + "0.036913, 0.297173, 0.630608, 1.245450, 2.473548",\ + "0.064917, 0.305223, 0.630841, 1.247228, 2.473548",\ + "0.122287, 0.339635, 0.636985, 1.249173, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.062966, 0.171021, 0.282962, 0.487566, 0.896774",\ + "0.150539, 0.258340, 0.370243, 0.574871, 0.984127",\ + "0.230685, 0.338682, 0.450270, 0.654899, 1.064159",\ + "0.365948, 0.476706, 0.588287, 0.792199, 1.200024",\ + "0.578145, 0.699559, 0.811451, 1.015162, 1.422583"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.020571, 0.183210, 0.383705, 0.756065, 1.500784",\ + "0.020571, 0.183210, 0.383705, 0.756065, 1.500784",\ + "0.021496, 0.183210, 0.383705, 0.756065, 1.500784",\ + "0.027055, 0.184687, 0.384226, 0.757731, 1.504742",\ + "0.042630, 0.188229, 0.384226, 0.757731, 1.504742"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[7]_redg_min*/ + + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018401, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.203067, 0.157249, 0.127058, 0.118464, 0.129443",\ + "0.207936, 0.162118, 0.131927, 0.123333, 0.134312",\ + "0.282684, 0.236865, 0.206674, 0.198080, 0.209060",\ + "0.376050, 0.329912, 0.299696, 0.291061, 0.301953",\ + "0.789608, 0.741801, 0.711356, 0.702451, 0.712846"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020571, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.248522, 0.173196, 0.105012, 0.094508, 0.144555",\ + "0.253666, 0.178340, 0.110157, 0.099653, 0.149700",\ + "0.325959, 0.250633, 0.182449, 0.171946, 0.221993",\ + "0.430477, 0.355166, 0.287060, 0.276913, 0.327879",\ + "0.906305, 0.831103, 0.763471, 0.755707, 0.812875"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[7]_stupr*/ + + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018401, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.129733, -0.087286, -0.052870, 0.052534, 0.311104",\ + "-0.134675, -0.092227, -0.057811, 0.047593, 0.306162",\ + "-0.208828, -0.166380, -0.131964, -0.026560, 0.232009",\ + "-0.298006, -0.255611, -0.221074, -0.123848, 0.111390",\ + "-0.695505, -0.653392, -0.618114, -0.570728, -0.477670"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020571, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.128225, -0.062545, -0.005224, 0.080862, 0.257839",\ + "-0.134070, -0.068391, -0.011070, 0.075016, 0.251993",\ + "-0.211053, -0.145374, -0.088052, -0.001967, 0.175010",\ + "-0.312522, -0.246536, -0.188774, -0.102722, 0.073645",\ + "-0.766129, -0.698256, -0.637868, -0.551957, -0.379066"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[7]_hldr*/ + +} /* end of pin adc_d_o[7] */ + +pin("adc_d_o[6]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000474 ; + + /* Other user defined attributes. */ + original_pin : adc_d_o[6]; + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.043083, 0.198120, 0.374256, 0.697785, 1.344843",\ + "0.128923, 0.285295, 0.461364, 0.784501, 1.430777",\ + "0.210274, 0.373426, 0.549322, 0.872125, 1.517732",\ + "0.345402, 0.527885, 0.703101, 1.025419, 1.670053",\ + "0.557160, 0.787678, 0.963834, 1.284789, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.018401, 0.293911, 0.628602, 1.246589, 2.482563",\ + "0.023522, 0.294865, 0.630572, 1.246589, 2.482563",\ + "0.036913, 0.297173, 0.630608, 1.246589, 2.482563",\ + "0.064917, 0.305223, 0.630841, 1.247228, 2.482563",\ + "0.122287, 0.339635, 0.636985, 1.249173, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.062966, 0.171021, 0.282962, 0.487566, 0.896774",\ + "0.150539, 0.258340, 0.370243, 0.574871, 0.984127",\ + "0.230685, 0.338682, 0.450270, 0.654899, 1.064159",\ + "0.365948, 0.476706, 0.588287, 0.792199, 1.200024",\ + "0.578145, 0.699559, 0.811451, 1.015162, 1.422583"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.020571, 0.183996, 0.385207, 0.758292, 1.504462",\ + "0.020571, 0.184130, 0.385715, 0.758292, 1.504462",\ + "0.021496, 0.184130, 0.385715, 0.758292, 1.504462",\ + "0.027055, 0.184687, 0.385715, 0.758292, 1.504742",\ + "0.042630, 0.188229, 0.385715, 0.758292, 1.504742"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[6]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_adc_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.043083, 0.198120, 0.374256, 0.697785, 1.344843",\ + "0.128923, 0.285295, 0.461364, 0.784501, 1.430777",\ + "0.210274, 0.373426, 0.549322, 0.872125, 1.517732",\ + "0.345402, 0.527885, 0.703101, 1.025419, 1.670053",\ + "0.557160, 0.787678, 0.963834, 1.284789, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.018401, 0.293911, 0.628602, 1.245375, 2.473548",\ + "0.023522, 0.294865, 0.630572, 1.245375, 2.473548",\ + "0.036913, 0.297173, 0.630608, 1.245450, 2.473548",\ + "0.064917, 0.305223, 0.630841, 1.247228, 2.473548",\ + "0.122287, 0.339635, 0.636985, 1.249173, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.062966, 0.171021, 0.282962, 0.487566, 0.896774",\ + "0.150539, 0.258340, 0.370243, 0.574871, 0.984127",\ + "0.230685, 0.338682, 0.450270, 0.654899, 1.064159",\ + "0.365948, 0.476706, 0.588287, 0.792199, 1.200024",\ + "0.578145, 0.699559, 0.811451, 1.015162, 1.422583"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.020571, 0.183210, 0.383705, 0.756065, 1.500784",\ + "0.020571, 0.183210, 0.383705, 0.756065, 1.500784",\ + "0.021496, 0.183210, 0.383705, 0.756065, 1.500784",\ + "0.027055, 0.184687, 0.384226, 0.757731, 1.504742",\ + "0.042630, 0.188229, 0.384226, 0.757731, 1.504742"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[6]_redg_min*/ + + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018401, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.203067, 0.157249, 0.127058, 0.118464, 0.129443",\ + "0.207936, 0.162118, 0.131927, 0.123333, 0.134312",\ + "0.282684, 0.236865, 0.206674, 0.198080, 0.209060",\ + "0.376050, 0.329912, 0.299696, 0.291061, 0.301953",\ + "0.789608, 0.741801, 0.711356, 0.702451, 0.712846"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020571, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.248522, 0.173196, 0.105012, 0.094508, 0.144555",\ + "0.253666, 0.178340, 0.110157, 0.099653, 0.149700",\ + "0.325959, 0.250633, 0.182449, 0.171946, 0.221993",\ + "0.430477, 0.355166, 0.287060, 0.276913, 0.327879",\ + "0.906305, 0.831103, 0.763471, 0.755707, 0.812875"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[6]_stupr*/ + + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018401, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.129733, -0.087286, -0.052870, 0.052534, 0.311104",\ + "-0.134675, -0.092227, -0.057811, 0.047593, 0.306162",\ + "-0.208828, -0.166380, -0.131964, -0.026560, 0.232009",\ + "-0.298006, -0.255611, -0.221074, -0.123848, 0.111390",\ + "-0.695505, -0.653392, -0.618114, -0.570728, -0.477670"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020571, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.128225, -0.062545, -0.005224, 0.080862, 0.257839",\ + "-0.134070, -0.068391, -0.011070, 0.075016, 0.251993",\ + "-0.211053, -0.145374, -0.088052, -0.001967, 0.175010",\ + "-0.312522, -0.246536, -0.188774, -0.102722, 0.073645",\ + "-0.766129, -0.698256, -0.637868, -0.551957, -0.379066"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[6]_hldr*/ + +} /* end of pin adc_d_o[6] */ + +pin("adc_d_o[5]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000474 ; + + /* Other user defined attributes. */ + original_pin : adc_d_o[5]; + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.043083, 0.198120, 0.374256, 0.697785, 1.344843",\ + "0.128923, 0.285295, 0.461364, 0.784501, 1.430777",\ + "0.210274, 0.373426, 0.549322, 0.872125, 1.517732",\ + "0.345402, 0.527885, 0.703101, 1.025419, 1.670053",\ + "0.557160, 0.787678, 0.963834, 1.284789, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.018401, 0.293911, 0.628602, 1.246589, 2.482563",\ + "0.023522, 0.294865, 0.630572, 1.246589, 2.482563",\ + "0.036913, 0.297173, 0.630608, 1.246589, 2.482563",\ + "0.064917, 0.305223, 0.630841, 1.247228, 2.482563",\ + "0.122287, 0.339635, 0.636985, 1.249173, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.062966, 0.171021, 0.282962, 0.487566, 0.896774",\ + "0.150539, 0.258340, 0.370243, 0.574871, 0.984127",\ + "0.230685, 0.338682, 0.450270, 0.654899, 1.064159",\ + "0.365948, 0.476706, 0.588287, 0.792199, 1.200024",\ + "0.578145, 0.699559, 0.811451, 1.015162, 1.422583"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.020571, 0.183996, 0.385207, 0.758292, 1.504462",\ + "0.020571, 0.184130, 0.385715, 0.758292, 1.504462",\ + "0.021496, 0.184130, 0.385715, 0.758292, 1.504462",\ + "0.027055, 0.184687, 0.385715, 0.758292, 1.504742",\ + "0.042630, 0.188229, 0.385715, 0.758292, 1.504742"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[5]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_adc_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.043083, 0.198120, 0.374256, 0.697785, 1.344843",\ + "0.128923, 0.285295, 0.461364, 0.784501, 1.430777",\ + "0.210274, 0.373426, 0.549322, 0.872125, 1.517732",\ + "0.345402, 0.527885, 0.703101, 1.025419, 1.670053",\ + "0.557160, 0.787678, 0.963834, 1.284789, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.018401, 0.293911, 0.628602, 1.245375, 2.473548",\ + "0.023522, 0.294865, 0.630572, 1.245375, 2.473548",\ + "0.036913, 0.297173, 0.630608, 1.245450, 2.473548",\ + "0.064917, 0.305223, 0.630841, 1.247228, 2.473548",\ + "0.122287, 0.339635, 0.636985, 1.249173, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.062966, 0.171021, 0.282962, 0.487566, 0.896774",\ + "0.150539, 0.258340, 0.370243, 0.574871, 0.984127",\ + "0.230685, 0.338682, 0.450270, 0.654899, 1.064159",\ + "0.365948, 0.476706, 0.588287, 0.792199, 1.200024",\ + "0.578145, 0.699559, 0.811451, 1.015162, 1.422583"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.020571, 0.183210, 0.383705, 0.756065, 1.500784",\ + "0.020571, 0.183210, 0.383705, 0.756065, 1.500784",\ + "0.021496, 0.183210, 0.383705, 0.756065, 1.500784",\ + "0.027055, 0.184687, 0.384226, 0.757731, 1.504742",\ + "0.042630, 0.188229, 0.384226, 0.757731, 1.504742"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[5]_redg_min*/ + + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018401, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.203067, 0.157249, 0.127058, 0.118464, 0.129443",\ + "0.207936, 0.162118, 0.131927, 0.123333, 0.134312",\ + "0.282684, 0.236865, 0.206674, 0.198080, 0.209060",\ + "0.376050, 0.329912, 0.299696, 0.291061, 0.301953",\ + "0.789608, 0.741801, 0.711356, 0.702451, 0.712846"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020571, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.248522, 0.173196, 0.105012, 0.094508, 0.144555",\ + "0.253666, 0.178340, 0.110157, 0.099653, 0.149700",\ + "0.325959, 0.250633, 0.182449, 0.171946, 0.221993",\ + "0.430477, 0.355166, 0.287060, 0.276913, 0.327879",\ + "0.906305, 0.831103, 0.763471, 0.755707, 0.812875"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[5]_stupr*/ + + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018401, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.129733, -0.087286, -0.052870, 0.052534, 0.311104",\ + "-0.134675, -0.092227, -0.057811, 0.047593, 0.306162",\ + "-0.208828, -0.166380, -0.131964, -0.026560, 0.232009",\ + "-0.298006, -0.255611, -0.221074, -0.123848, 0.111390",\ + "-0.695505, -0.653392, -0.618114, -0.570728, -0.477670"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020571, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.128225, -0.062545, -0.005224, 0.080862, 0.257839",\ + "-0.134070, -0.068391, -0.011070, 0.075016, 0.251993",\ + "-0.211053, -0.145374, -0.088052, -0.001967, 0.175010",\ + "-0.312522, -0.246536, -0.188774, -0.102722, 0.073645",\ + "-0.766129, -0.698256, -0.637868, -0.551957, -0.379066"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[5]_hldr*/ + +} /* end of pin adc_d_o[5] */ + +pin("adc_d_o[4]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000474 ; + + /* Other user defined attributes. */ + original_pin : adc_d_o[4]; + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.043083, 0.198120, 0.374256, 0.697785, 1.344843",\ + "0.128923, 0.285295, 0.461364, 0.784501, 1.430777",\ + "0.210274, 0.373426, 0.549322, 0.872125, 1.517732",\ + "0.345402, 0.527885, 0.703101, 1.025419, 1.670053",\ + "0.557160, 0.787678, 0.963834, 1.284789, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.018401, 0.293911, 0.628602, 1.246589, 2.482563",\ + "0.023522, 0.294865, 0.630572, 1.246589, 2.482563",\ + "0.036913, 0.297173, 0.630608, 1.246589, 2.482563",\ + "0.064917, 0.305223, 0.630841, 1.247228, 2.482563",\ + "0.122287, 0.339635, 0.636985, 1.249173, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.062966, 0.171021, 0.282962, 0.487566, 0.896774",\ + "0.150539, 0.258340, 0.370243, 0.574871, 0.984127",\ + "0.230685, 0.338682, 0.450270, 0.654899, 1.064159",\ + "0.365948, 0.476706, 0.588287, 0.792199, 1.200024",\ + "0.578145, 0.699559, 0.811451, 1.015162, 1.422583"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.020571, 0.183996, 0.385207, 0.758292, 1.504462",\ + "0.020571, 0.184130, 0.385715, 0.758292, 1.504462",\ + "0.021496, 0.184130, 0.385715, 0.758292, 1.504462",\ + "0.027055, 0.184687, 0.385715, 0.758292, 1.504742",\ + "0.042630, 0.188229, 0.385715, 0.758292, 1.504742"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[4]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_adc_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.043083, 0.198120, 0.374256, 0.697785, 1.344843",\ + "0.128923, 0.285295, 0.461364, 0.784501, 1.430777",\ + "0.210274, 0.373426, 0.549322, 0.872125, 1.517732",\ + "0.345402, 0.527885, 0.703101, 1.025419, 1.670053",\ + "0.557160, 0.787678, 0.963834, 1.284789, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.018401, 0.293911, 0.628602, 1.245375, 2.473548",\ + "0.023522, 0.294865, 0.630572, 1.245375, 2.473548",\ + "0.036913, 0.297173, 0.630608, 1.245450, 2.473548",\ + "0.064917, 0.305223, 0.630841, 1.247228, 2.473548",\ + "0.122287, 0.339635, 0.636985, 1.249173, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.062966, 0.171021, 0.282962, 0.487566, 0.896774",\ + "0.150539, 0.258340, 0.370243, 0.574871, 0.984127",\ + "0.230685, 0.338682, 0.450270, 0.654899, 1.064159",\ + "0.365948, 0.476706, 0.588287, 0.792199, 1.200024",\ + "0.578145, 0.699559, 0.811451, 1.015162, 1.422583"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.020571, 0.183210, 0.383705, 0.756065, 1.500784",\ + "0.020571, 0.183210, 0.383705, 0.756065, 1.500784",\ + "0.021496, 0.183210, 0.383705, 0.756065, 1.500784",\ + "0.027055, 0.184687, 0.384226, 0.757731, 1.504742",\ + "0.042630, 0.188229, 0.384226, 0.757731, 1.504742"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[4]_redg_min*/ + + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018401, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.203067, 0.157249, 0.127058, 0.118464, 0.129443",\ + "0.207936, 0.162118, 0.131927, 0.123333, 0.134312",\ + "0.282684, 0.236865, 0.206674, 0.198080, 0.209060",\ + "0.376050, 0.329912, 0.299696, 0.291061, 0.301953",\ + "0.789608, 0.741801, 0.711356, 0.702451, 0.712846"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020571, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.248522, 0.173196, 0.105012, 0.094508, 0.144555",\ + "0.253666, 0.178340, 0.110157, 0.099653, 0.149700",\ + "0.325959, 0.250633, 0.182449, 0.171946, 0.221993",\ + "0.430477, 0.355166, 0.287060, 0.276913, 0.327879",\ + "0.906305, 0.831103, 0.763471, 0.755707, 0.812875"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[4]_stupr*/ + + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018401, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.129733, -0.087286, -0.052870, 0.052534, 0.311104",\ + "-0.134675, -0.092227, -0.057811, 0.047593, 0.306162",\ + "-0.208828, -0.166380, -0.131964, -0.026560, 0.232009",\ + "-0.298006, -0.255611, -0.221074, -0.123848, 0.111390",\ + "-0.695505, -0.653392, -0.618114, -0.570728, -0.477670"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020571, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.128225, -0.062545, -0.005224, 0.080862, 0.257839",\ + "-0.134070, -0.068391, -0.011070, 0.075016, 0.251993",\ + "-0.211053, -0.145374, -0.088052, -0.001967, 0.175010",\ + "-0.312522, -0.246536, -0.188774, -0.102722, 0.073645",\ + "-0.766129, -0.698256, -0.637868, -0.551957, -0.379066"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[4]_hldr*/ + +} /* end of pin adc_d_o[4] */ + +pin("adc_d_o[3]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000474 ; + + /* Other user defined attributes. */ + original_pin : adc_d_o[3]; + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.043083, 0.198120, 0.374256, 0.697785, 1.344843",\ + "0.128923, 0.285295, 0.461364, 0.784501, 1.430777",\ + "0.210274, 0.373426, 0.549322, 0.872125, 1.517732",\ + "0.345402, 0.527885, 0.703101, 1.025419, 1.670053",\ + "0.557160, 0.787678, 0.963834, 1.284789, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.018401, 0.293911, 0.628602, 1.246589, 2.482563",\ + "0.023522, 0.294865, 0.630572, 1.246589, 2.482563",\ + "0.036913, 0.297173, 0.630608, 1.246589, 2.482563",\ + "0.064917, 0.305223, 0.630841, 1.247228, 2.482563",\ + "0.122287, 0.339635, 0.636985, 1.249173, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.062966, 0.171021, 0.282962, 0.487566, 0.896774",\ + "0.150539, 0.258340, 0.370243, 0.574871, 0.984127",\ + "0.230685, 0.338682, 0.450270, 0.654899, 1.064159",\ + "0.365948, 0.476706, 0.588287, 0.792199, 1.200024",\ + "0.578145, 0.699559, 0.811451, 1.015162, 1.422583"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.020571, 0.183996, 0.385207, 0.758292, 1.504462",\ + "0.020571, 0.184130, 0.385715, 0.758292, 1.504462",\ + "0.021496, 0.184130, 0.385715, 0.758292, 1.504462",\ + "0.027055, 0.184687, 0.385715, 0.758292, 1.504742",\ + "0.042630, 0.188229, 0.385715, 0.758292, 1.504742"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[3]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_adc_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.043083, 0.198120, 0.374256, 0.697785, 1.344843",\ + "0.128923, 0.285295, 0.461364, 0.784501, 1.430777",\ + "0.210274, 0.373426, 0.549322, 0.872125, 1.517732",\ + "0.345402, 0.527885, 0.703101, 1.025419, 1.670053",\ + "0.557160, 0.787678, 0.963834, 1.284789, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.018401, 0.293911, 0.628602, 1.245375, 2.473548",\ + "0.023522, 0.294865, 0.630572, 1.245375, 2.473548",\ + "0.036913, 0.297173, 0.630608, 1.245450, 2.473548",\ + "0.064917, 0.305223, 0.630841, 1.247228, 2.473548",\ + "0.122287, 0.339635, 0.636985, 1.249173, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.062966, 0.171021, 0.282962, 0.487566, 0.896774",\ + "0.150539, 0.258340, 0.370243, 0.574871, 0.984127",\ + "0.230685, 0.338682, 0.450270, 0.654899, 1.064159",\ + "0.365948, 0.476706, 0.588287, 0.792199, 1.200024",\ + "0.578145, 0.699559, 0.811451, 1.015162, 1.422583"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.020571, 0.183210, 0.383705, 0.756065, 1.500784",\ + "0.020571, 0.183210, 0.383705, 0.756065, 1.500784",\ + "0.021496, 0.183210, 0.383705, 0.756065, 1.500784",\ + "0.027055, 0.184687, 0.384226, 0.757731, 1.504742",\ + "0.042630, 0.188229, 0.384226, 0.757731, 1.504742"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[3]_redg_min*/ + + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018401, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.203067, 0.157249, 0.127058, 0.118464, 0.129443",\ + "0.207936, 0.162118, 0.131927, 0.123333, 0.134312",\ + "0.282684, 0.236865, 0.206674, 0.198080, 0.209060",\ + "0.376050, 0.329912, 0.299696, 0.291061, 0.301953",\ + "0.789608, 0.741801, 0.711356, 0.702451, 0.712846"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020571, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.248522, 0.173196, 0.105012, 0.094508, 0.144555",\ + "0.253666, 0.178340, 0.110157, 0.099653, 0.149700",\ + "0.325959, 0.250633, 0.182449, 0.171946, 0.221993",\ + "0.430477, 0.355166, 0.287060, 0.276913, 0.327879",\ + "0.906305, 0.831103, 0.763471, 0.755707, 0.812875"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[3]_stupr*/ + + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018401, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.129733, -0.087286, -0.052870, 0.052534, 0.311104",\ + "-0.134675, -0.092227, -0.057811, 0.047593, 0.306162",\ + "-0.208828, -0.166380, -0.131964, -0.026560, 0.232009",\ + "-0.298006, -0.255611, -0.221074, -0.123848, 0.111390",\ + "-0.695505, -0.653392, -0.618114, -0.570728, -0.477670"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020571, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.128225, -0.062545, -0.005224, 0.080862, 0.257839",\ + "-0.134070, -0.068391, -0.011070, 0.075016, 0.251993",\ + "-0.211053, -0.145374, -0.088052, -0.001967, 0.175010",\ + "-0.312522, -0.246536, -0.188774, -0.102722, 0.073645",\ + "-0.766129, -0.698256, -0.637868, -0.551957, -0.379066"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[3]_hldr*/ + +} /* end of pin adc_d_o[3] */ + +pin("adc_d_o[2]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000474 ; + + /* Other user defined attributes. */ + original_pin : adc_d_o[2]; + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.043083, 0.198120, 0.374256, 0.697785, 1.344843",\ + "0.128923, 0.285295, 0.461364, 0.784501, 1.430777",\ + "0.210274, 0.373426, 0.549322, 0.872125, 1.517732",\ + "0.345402, 0.527885, 0.703101, 1.025419, 1.670053",\ + "0.557160, 0.787678, 0.963834, 1.284789, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.018401, 0.293911, 0.628602, 1.246589, 2.482563",\ + "0.023522, 0.294865, 0.630572, 1.246589, 2.482563",\ + "0.036913, 0.297173, 0.630608, 1.246589, 2.482563",\ + "0.064917, 0.305223, 0.630841, 1.247228, 2.482563",\ + "0.122287, 0.339635, 0.636985, 1.249173, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.062966, 0.171021, 0.282962, 0.487566, 0.896774",\ + "0.150539, 0.258340, 0.370243, 0.574871, 0.984127",\ + "0.230685, 0.338682, 0.450270, 0.654899, 1.064159",\ + "0.365948, 0.476706, 0.588287, 0.792199, 1.200024",\ + "0.578145, 0.699559, 0.811451, 1.015162, 1.422583"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.020571, 0.183996, 0.385207, 0.758292, 1.504462",\ + "0.020571, 0.184130, 0.385715, 0.758292, 1.504462",\ + "0.021496, 0.184130, 0.385715, 0.758292, 1.504462",\ + "0.027055, 0.184687, 0.385715, 0.758292, 1.504742",\ + "0.042630, 0.188229, 0.385715, 0.758292, 1.504742"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[2]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_adc_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.043083, 0.198120, 0.374256, 0.697785, 1.344843",\ + "0.128923, 0.285295, 0.461364, 0.784501, 1.430777",\ + "0.210274, 0.373426, 0.549322, 0.872125, 1.517732",\ + "0.345402, 0.527885, 0.703101, 1.025419, 1.670053",\ + "0.557160, 0.787678, 0.963834, 1.284789, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.018401, 0.293911, 0.628602, 1.245375, 2.473548",\ + "0.023522, 0.294865, 0.630572, 1.245375, 2.473548",\ + "0.036913, 0.297173, 0.630608, 1.245450, 2.473548",\ + "0.064917, 0.305223, 0.630841, 1.247228, 2.473548",\ + "0.122287, 0.339635, 0.636985, 1.249173, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.062966, 0.171021, 0.282962, 0.487566, 0.896774",\ + "0.150539, 0.258340, 0.370243, 0.574871, 0.984127",\ + "0.230685, 0.338682, 0.450270, 0.654899, 1.064159",\ + "0.365948, 0.476706, 0.588287, 0.792199, 1.200024",\ + "0.578145, 0.699559, 0.811451, 1.015162, 1.422583"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.020571, 0.183210, 0.383705, 0.756065, 1.500784",\ + "0.020571, 0.183210, 0.383705, 0.756065, 1.500784",\ + "0.021496, 0.183210, 0.383705, 0.756065, 1.500784",\ + "0.027055, 0.184687, 0.384226, 0.757731, 1.504742",\ + "0.042630, 0.188229, 0.384226, 0.757731, 1.504742"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[2]_redg_min*/ + + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018401, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.203067, 0.157249, 0.127058, 0.118464, 0.129443",\ + "0.207936, 0.162118, 0.131927, 0.123333, 0.134312",\ + "0.282684, 0.236865, 0.206674, 0.198080, 0.209060",\ + "0.376050, 0.329912, 0.299696, 0.291061, 0.301953",\ + "0.789608, 0.741801, 0.711356, 0.702451, 0.712846"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020571, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.248522, 0.173196, 0.105012, 0.094508, 0.144555",\ + "0.253666, 0.178340, 0.110157, 0.099653, 0.149700",\ + "0.325959, 0.250633, 0.182449, 0.171946, 0.221993",\ + "0.430477, 0.355166, 0.287060, 0.276913, 0.327879",\ + "0.906305, 0.831103, 0.763471, 0.755707, 0.812875"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[2]_stupr*/ + + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018401, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.129733, -0.087286, -0.052870, 0.052534, 0.311104",\ + "-0.134675, -0.092227, -0.057811, 0.047593, 0.306162",\ + "-0.208828, -0.166380, -0.131964, -0.026560, 0.232009",\ + "-0.298006, -0.255611, -0.221074, -0.123848, 0.111390",\ + "-0.695505, -0.653392, -0.618114, -0.570728, -0.477670"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020571, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.128225, -0.062545, -0.005224, 0.080862, 0.257839",\ + "-0.134070, -0.068391, -0.011070, 0.075016, 0.251993",\ + "-0.211053, -0.145374, -0.088052, -0.001967, 0.175010",\ + "-0.312522, -0.246536, -0.188774, -0.102722, 0.073645",\ + "-0.766129, -0.698256, -0.637868, -0.551957, -0.379066"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[2]_hldr*/ + +} /* end of pin adc_d_o[2] */ + +pin("adc_d_o[1]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000474 ; + + /* Other user defined attributes. */ + original_pin : adc_d_o[1]; + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.043083, 0.198120, 0.374256, 0.697785, 1.344843",\ + "0.128923, 0.285295, 0.461364, 0.784501, 1.430777",\ + "0.210274, 0.373426, 0.549322, 0.872125, 1.517732",\ + "0.345402, 0.527885, 0.703101, 1.025419, 1.670053",\ + "0.557160, 0.787678, 0.963834, 1.284789, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.018401, 0.293911, 0.628602, 1.246589, 2.482563",\ + "0.023522, 0.294865, 0.630572, 1.246589, 2.482563",\ + "0.036913, 0.297173, 0.630608, 1.246589, 2.482563",\ + "0.064917, 0.305223, 0.630841, 1.247228, 2.482563",\ + "0.122287, 0.339635, 0.636985, 1.249173, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.062966, 0.171021, 0.282962, 0.487566, 0.896774",\ + "0.150539, 0.258340, 0.370243, 0.574871, 0.984127",\ + "0.230685, 0.338682, 0.450270, 0.654899, 1.064159",\ + "0.365948, 0.476706, 0.588287, 0.792199, 1.200024",\ + "0.578145, 0.699559, 0.811451, 1.015162, 1.422583"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.020571, 0.183996, 0.385207, 0.758292, 1.504462",\ + "0.020571, 0.184130, 0.385715, 0.758292, 1.504462",\ + "0.021496, 0.184130, 0.385715, 0.758292, 1.504462",\ + "0.027055, 0.184687, 0.385715, 0.758292, 1.504742",\ + "0.042630, 0.188229, 0.385715, 0.758292, 1.504742"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[1]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_adc_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.043083, 0.198120, 0.374256, 0.697785, 1.344843",\ + "0.128923, 0.285295, 0.461364, 0.784501, 1.430777",\ + "0.210274, 0.373426, 0.549322, 0.872125, 1.517732",\ + "0.345402, 0.527885, 0.703101, 1.025419, 1.670053",\ + "0.557160, 0.787678, 0.963834, 1.284789, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.018401, 0.293911, 0.628602, 1.245375, 2.473548",\ + "0.023522, 0.294865, 0.630572, 1.245375, 2.473548",\ + "0.036913, 0.297173, 0.630608, 1.245450, 2.473548",\ + "0.064917, 0.305223, 0.630841, 1.247228, 2.473548",\ + "0.122287, 0.339635, 0.636985, 1.249173, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.062966, 0.171021, 0.282962, 0.487566, 0.896774",\ + "0.150539, 0.258340, 0.370243, 0.574871, 0.984127",\ + "0.230685, 0.338682, 0.450270, 0.654899, 1.064159",\ + "0.365948, 0.476706, 0.588287, 0.792199, 1.200024",\ + "0.578145, 0.699559, 0.811451, 1.015162, 1.422583"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.020571, 0.183210, 0.383705, 0.756065, 1.500784",\ + "0.020571, 0.183210, 0.383705, 0.756065, 1.500784",\ + "0.021496, 0.183210, 0.383705, 0.756065, 1.500784",\ + "0.027055, 0.184687, 0.384226, 0.757731, 1.504742",\ + "0.042630, 0.188229, 0.384226, 0.757731, 1.504742"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[1]_redg_min*/ + + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018401, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.203067, 0.157249, 0.127058, 0.118464, 0.129443",\ + "0.207936, 0.162118, 0.131927, 0.123333, 0.134312",\ + "0.282684, 0.236865, 0.206674, 0.198080, 0.209060",\ + "0.376050, 0.329912, 0.299696, 0.291061, 0.301953",\ + "0.789608, 0.741801, 0.711356, 0.702451, 0.712846"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020571, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.248522, 0.173196, 0.105012, 0.094508, 0.144555",\ + "0.253666, 0.178340, 0.110157, 0.099653, 0.149700",\ + "0.325959, 0.250633, 0.182449, 0.171946, 0.221993",\ + "0.430477, 0.355166, 0.287060, 0.276913, 0.327879",\ + "0.906305, 0.831103, 0.763471, 0.755707, 0.812875"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[1]_stupr*/ + + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018401, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.129733, -0.087286, -0.052870, 0.052534, 0.311104",\ + "-0.134675, -0.092227, -0.057811, 0.047593, 0.306162",\ + "-0.208828, -0.166380, -0.131964, -0.026560, 0.232009",\ + "-0.298006, -0.255611, -0.221074, -0.123848, 0.111390",\ + "-0.695505, -0.653392, -0.618114, -0.570728, -0.477670"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020571, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.128225, -0.062545, -0.005224, 0.080862, 0.257839",\ + "-0.134070, -0.068391, -0.011070, 0.075016, 0.251993",\ + "-0.211053, -0.145374, -0.088052, -0.001967, 0.175010",\ + "-0.312522, -0.246536, -0.188774, -0.102722, 0.073645",\ + "-0.766129, -0.698256, -0.637868, -0.551957, -0.379066"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[1]_hldr*/ + +} /* end of pin adc_d_o[1] */ + +pin("adc_d_o[0]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000474 ; + + /* Other user defined attributes. */ + original_pin : adc_d_o[0]; + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.043083, 0.198120, 0.374256, 0.697785, 1.344843",\ + "0.128923, 0.285295, 0.461364, 0.784501, 1.430777",\ + "0.210274, 0.373426, 0.549322, 0.872125, 1.517732",\ + "0.345402, 0.527885, 0.703101, 1.025419, 1.670053",\ + "0.557160, 0.787678, 0.963834, 1.284789, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.018401, 0.293911, 0.628602, 1.246589, 2.482563",\ + "0.023522, 0.294865, 0.630572, 1.246589, 2.482563",\ + "0.036913, 0.297173, 0.630608, 1.246589, 2.482563",\ + "0.064917, 0.305223, 0.630841, 1.247228, 2.482563",\ + "0.122287, 0.339635, 0.636985, 1.249173, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.062966, 0.171021, 0.282962, 0.487566, 0.896774",\ + "0.150539, 0.258340, 0.370243, 0.574871, 0.984127",\ + "0.230685, 0.338682, 0.450270, 0.654899, 1.064159",\ + "0.365948, 0.476706, 0.588287, 0.792199, 1.200024",\ + "0.578145, 0.699559, 0.811451, 1.015162, 1.422583"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.020571, 0.183996, 0.385207, 0.758292, 1.504462",\ + "0.020571, 0.184130, 0.385715, 0.758292, 1.504462",\ + "0.021496, 0.184130, 0.385715, 0.758292, 1.504462",\ + "0.027055, 0.184687, 0.385715, 0.758292, 1.504742",\ + "0.042630, 0.188229, 0.385715, 0.758292, 1.504742"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[0]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_adc_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.043083, 0.198120, 0.374256, 0.697785, 1.344843",\ + "0.128923, 0.285295, 0.461364, 0.784501, 1.430777",\ + "0.210274, 0.373426, 0.549322, 0.872125, 1.517732",\ + "0.345402, 0.527885, 0.703101, 1.025419, 1.670053",\ + "0.557160, 0.787678, 0.963834, 1.284789, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.018401, 0.293911, 0.628602, 1.245375, 2.473548",\ + "0.023522, 0.294865, 0.630572, 1.245375, 2.473548",\ + "0.036913, 0.297173, 0.630608, 1.245450, 2.473548",\ + "0.064917, 0.305223, 0.630841, 1.247228, 2.473548",\ + "0.122287, 0.339635, 0.636985, 1.249173, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.062966, 0.171021, 0.282962, 0.487566, 0.896774",\ + "0.150539, 0.258340, 0.370243, 0.574871, 0.984127",\ + "0.230685, 0.338682, 0.450270, 0.654899, 1.064159",\ + "0.365948, 0.476706, 0.588287, 0.792199, 1.200024",\ + "0.578145, 0.699559, 0.811451, 1.015162, 1.422583"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.020571, 0.183210, 0.383705, 0.756065, 1.500784",\ + "0.020571, 0.183210, 0.383705, 0.756065, 1.500784",\ + "0.021496, 0.183210, 0.383705, 0.756065, 1.500784",\ + "0.027055, 0.184687, 0.384226, 0.757731, 1.504742",\ + "0.042630, 0.188229, 0.384226, 0.757731, 1.504742"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[0]_redg_min*/ + + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018401, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.203067, 0.157249, 0.127058, 0.118464, 0.129443",\ + "0.207936, 0.162118, 0.131927, 0.123333, 0.134312",\ + "0.282684, 0.236865, 0.206674, 0.198080, 0.209060",\ + "0.376050, 0.329912, 0.299696, 0.291061, 0.301953",\ + "0.789608, 0.741801, 0.711356, 0.702451, 0.712846"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020571, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.248522, 0.173196, 0.105012, 0.094508, 0.144555",\ + "0.253666, 0.178340, 0.110157, 0.099653, 0.149700",\ + "0.325959, 0.250633, 0.182449, 0.171946, 0.221993",\ + "0.430477, 0.355166, 0.287060, 0.276913, 0.327879",\ + "0.906305, 0.831103, 0.763471, 0.755707, 0.812875"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[0]_stupr*/ + + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018401, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.129733, -0.087286, -0.052870, 0.052534, 0.311104",\ + "-0.134675, -0.092227, -0.057811, 0.047593, 0.306162",\ + "-0.208828, -0.166380, -0.131964, -0.026560, 0.232009",\ + "-0.298006, -0.255611, -0.221074, -0.123848, 0.111390",\ + "-0.695505, -0.653392, -0.618114, -0.570728, -0.477670"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020571, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.128225, -0.062545, -0.005224, 0.080862, 0.257839",\ + "-0.134070, -0.068391, -0.011070, 0.075016, 0.251993",\ + "-0.211053, -0.145374, -0.088052, -0.001967, 0.175010",\ + "-0.312522, -0.246536, -0.188774, -0.102722, 0.073645",\ + "-0.766129, -0.698256, -0.637868, -0.551957, -0.379066"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[0]_hldr*/ + +} /* end of pin adc_d_o[0] */ +} /* end of bus adc_d_o */ + +pin("adc_d_val_o") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000485 ; + + /* Other user defined attributes. */ + original_pin : adc_d_val_o; + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000485, 0.073484, 0.160867, 0.321248, 0.642011"); + values ( "0.043124, 0.198142, 0.374272, 0.697796, 1.344843",\ + "0.128968, 0.285317, 0.461380, 0.784513, 1.430777",\ + "0.210336, 0.373448, 0.549338, 0.872136, 1.517732",\ + "0.345497, 0.527907, 0.703118, 1.025430, 1.670053",\ + "0.557318, 0.787701, 0.963851, 1.284800, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000485, 0.073484, 0.160867, 0.321248, 0.642011"); + values ( "0.018442, 0.293953, 0.628634, 1.246610, 2.482563",\ + "0.023559, 0.294907, 0.630604, 1.246610, 2.482563",\ + "0.036948, 0.297215, 0.630640, 1.246610, 2.482563",\ + "0.064957, 0.305264, 0.630873, 1.247249, 2.482563",\ + "0.122341, 0.339671, 0.637017, 1.249194, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000485, 0.073484, 0.160867, 0.321248, 0.642011"); + values ( "0.062980, 0.171026, 0.282963, 0.487563, 0.896764",\ + "0.150552, 0.258345, 0.370244, 0.574868, 0.984118",\ + "0.230698, 0.338686, 0.450271, 0.654897, 1.064149",\ + "0.365964, 0.476710, 0.588288, 0.792197, 1.200014",\ + "0.578168, 0.699563, 0.811453, 1.015159, 1.422574"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000485, 0.073484, 0.160867, 0.321248, 0.642011"); + values ( "0.020581, 0.184004, 0.385209, 0.758288, 1.504444",\ + "0.020581, 0.184139, 0.385717, 0.758288, 1.504444",\ + "0.021507, 0.184139, 0.385717, 0.758288, 1.504444",\ + "0.027064, 0.184695, 0.385717, 0.758288, 1.504725",\ + "0.042640, 0.188237, 0.385717, 0.758288, 1.504725"); + } + + } /* end of arc clk_ast_adc_i_adc_d_val_o_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_adc_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000485, 0.073484, 0.160867, 0.321248, 0.642011"); + values ( "0.043124, 0.198142, 0.374272, 0.697796, 1.344843",\ + "0.128968, 0.285317, 0.461380, 0.784513, 1.430777",\ + "0.210336, 0.373448, 0.549338, 0.872136, 1.517732",\ + "0.345497, 0.527907, 0.703118, 1.025430, 1.670053",\ + "0.557318, 0.787701, 0.963851, 1.284800, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000485, 0.073484, 0.160867, 0.321248, 0.642011"); + values ( "0.018442, 0.293953, 0.628634, 1.245396, 2.473548",\ + "0.023559, 0.294907, 0.630604, 1.245396, 2.473548",\ + "0.036948, 0.297215, 0.630640, 1.245471, 2.473548",\ + "0.064957, 0.305264, 0.630873, 1.247249, 2.473548",\ + "0.122341, 0.339671, 0.637017, 1.249194, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000485, 0.073484, 0.160867, 0.321248, 0.642011"); + values ( "0.062980, 0.171026, 0.282963, 0.487563, 0.896764",\ + "0.150552, 0.258345, 0.370244, 0.574868, 0.984118",\ + "0.230698, 0.338686, 0.450271, 0.654897, 1.064149",\ + "0.365964, 0.476710, 0.588288, 0.792197, 1.200014",\ + "0.578168, 0.699563, 0.811453, 1.015159, 1.422574"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000485, 0.073484, 0.160867, 0.321248, 0.642011"); + values ( "0.020581, 0.183219, 0.383707, 0.756060, 1.500767",\ + "0.020581, 0.183219, 0.383707, 0.756060, 1.500767",\ + "0.021507, 0.183219, 0.383707, 0.756060, 1.500767",\ + "0.027064, 0.184695, 0.384228, 0.757727, 1.504725",\ + "0.042640, 0.188237, 0.384228, 0.757727, 1.504725"); + } + + } /* end of arc clk_ast_adc_i_adc_d_val_o_redg_min*/ + + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018442, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.243976, 0.197294, 0.167037, 0.158332, 0.169076",\ + "0.249724, 0.203042, 0.172784, 0.164080, 0.174823",\ + "0.330128, 0.283446, 0.253188, 0.244484, 0.255227",\ + "0.421667, 0.374985, 0.344728, 0.336023, 0.346766",\ + "0.857546, 0.810300, 0.779998, 0.771221, 0.781810"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020581, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.235882, 0.160549, 0.092329, 0.081659, 0.131277",\ + "0.241065, 0.165732, 0.097513, 0.086843, 0.136460",\ + "0.320960, 0.245631, 0.177435, 0.166874, 0.216773",\ + "0.424142, 0.348830, 0.280724, 0.270576, 0.321539",\ + "0.869196, 0.793968, 0.726309, 0.718213, 0.774472"); + } + + } /* end of arc clk_ast_adc_i_adc_d_val_o_stupr*/ + + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018442, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.172771, -0.130490, -0.095686, -0.016470, 0.167392",\ + "-0.178433, -0.136153, -0.101349, -0.022133, 0.161730",\ + "-0.256684, -0.214404, -0.179600, -0.100383, 0.083479",\ + "-0.345053, -0.302773, -0.267969, -0.188752, -0.004890",\ + "-0.762797, -0.720612, -0.685586, -0.621349, -0.480218"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020581, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.121789, -0.056140, 0.001137, 0.087226, 0.264264",\ + "-0.127527, -0.061878, -0.004601, 0.081488, 0.258526",\ + "-0.211930, -0.146176, -0.088749, -0.002671, 0.174159",\ + "-0.309060, -0.243056, -0.185270, -0.099220, 0.077113",\ + "-0.732847, -0.665438, -0.605637, -0.519740, -0.346201"); + } + + } /* end of arc clk_ast_adc_i_adc_d_val_o_hldr*/ + +} /* end of pin adc_d_val_o */ + +pin("rng_en_i") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001189 ; + + /* Other user defined attributes. */ + original_pin : rng_en_i; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.200076, 0.146984, 0.107694, 0.091175, 0.087585",\ + "0.210849, 0.158775, 0.118789, 0.101895, 0.097230",\ + "0.247906, 0.195949, 0.156513, 0.139769, 0.134169",\ + "0.400793, 0.347442, 0.307665, 0.290788, 0.285288",\ + "0.811131, 0.757315, 0.714144, 0.695925, 0.691143"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.249331, 0.166333, 0.091045, 0.056957, 0.020498",\ + "0.258619, 0.175944, 0.100656, 0.066835, 0.033618",\ + "0.297457, 0.214925, 0.140086, 0.106583, 0.074986",\ + "0.472698, 0.388796, 0.312903, 0.278157, 0.236728",\ + "0.983325, 0.898854, 0.822917, 0.782684, 0.674795"); + } + + } /* end of arc clk_ast_tlul_i_rng_en_i_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.096530, -0.053812, -0.018112, 0.007162, 0.135173",\ + "-0.107327, -0.064625, -0.028931, -0.003653, 0.124428",\ + "-0.144374, -0.101567, -0.065911, -0.040647, 0.087453",\ + "-0.286358, -0.243809, -0.210094, -0.185592, -0.057011",\ + "-0.620310, -0.578080, -0.553843, -0.534595, -0.422314"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.130907, -0.055165, 0.010770, 0.056779, 0.285045",\ + "-0.140562, -0.065848, 0.000282, 0.046339, 0.274227",\ + "-0.179341, -0.104491, -0.038333, 0.007805, 0.236523",\ + "-0.350407, -0.276449, -0.208169, -0.160590, 0.074989",\ + "-0.811364, -0.742478, -0.673228, -0.625268, -0.389923"); + } + + } /* end of arc clk_ast_tlul_i_rng_en_i_hldr*/ + +} /* end of pin rng_en_i */ + +pin("rng_fips_i") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001189 ; + + /* Other user defined attributes. */ + original_pin : rng_fips_i; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.200076, 0.146984, 0.107694, 0.091175, 0.087585",\ + "0.210849, 0.158775, 0.118789, 0.101895, 0.097230",\ + "0.247906, 0.195949, 0.156513, 0.139769, 0.134169",\ + "0.400793, 0.347442, 0.307665, 0.290788, 0.285288",\ + "0.811131, 0.757315, 0.714144, 0.695925, 0.691143"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.249331, 0.166333, 0.091045, 0.056957, 0.020498",\ + "0.258619, 0.175944, 0.100656, 0.066835, 0.033618",\ + "0.297457, 0.214925, 0.140086, 0.106583, 0.074986",\ + "0.472698, 0.388796, 0.312903, 0.278157, 0.236728",\ + "0.983325, 0.898854, 0.822917, 0.782684, 0.674795"); + } + + } /* end of arc clk_ast_tlul_i_rng_fips_i_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.096530, -0.053812, -0.018112, 0.007162, 0.135173",\ + "-0.107327, -0.064625, -0.028931, -0.003653, 0.124428",\ + "-0.144374, -0.101567, -0.065911, -0.040647, 0.087453",\ + "-0.286358, -0.243809, -0.210094, -0.185592, -0.057011",\ + "-0.620310, -0.578080, -0.553843, -0.534595, -0.422314"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.130907, -0.055165, 0.010770, 0.056779, 0.285045",\ + "-0.140562, -0.065848, 0.000282, 0.046339, 0.274227",\ + "-0.179341, -0.104491, -0.038333, 0.007805, 0.236523",\ + "-0.350407, -0.276449, -0.208169, -0.160590, 0.074989",\ + "-0.811364, -0.742478, -0.673228, -0.625268, -0.389923"); + } + + } /* end of arc clk_ast_tlul_i_rng_fips_i_hldr*/ + +} /* end of pin rng_fips_i */ + +pin("rng_val_o") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000506 ; + + /* Other user defined attributes. */ + original_pin : rng_val_o; + timing () { + related_pin : "clk_ast_rng_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000506, 0.073504, 0.160882, 0.321258, 0.642011"); + values ( "0.043198, 0.198183, 0.374303, 0.697816, 1.344843",\ + "0.100770, 0.256465, 0.432811, 0.755524, 1.400950",\ + "0.234375, 0.400817, 0.576577, 0.899279, 1.544683",\ + "0.266829, 0.437889, 0.613486, 0.936071, 1.581241",\ + "0.557607, 0.787741, 0.963881, 1.284820, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000506, 0.073504, 0.160882, 0.321258, 0.642011"); + values ( "0.018518, 0.294029, 0.628692, 1.246649, 2.482563",\ + "0.020629, 0.294660, 0.630087, 1.246649, 2.482563",\ + "0.041968, 0.298715, 0.630739, 1.246649, 2.482563",\ + "0.048693, 0.300646, 0.630795, 1.246649, 2.482563",\ + "0.122440, 0.339737, 0.637074, 1.249232, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000506, 0.073504, 0.160882, 0.321258, 0.642011"); + values ( "0.063098, 0.171066, 0.282997, 0.487591, 0.896779",\ + "0.123042, 0.230894, 0.342842, 0.547360, 0.956396",\ + "0.254755, 0.363148, 0.474725, 0.679218, 1.088204",\ + "0.287224, 0.396275, 0.507850, 0.712171, 1.120812",\ + "0.578369, 0.699604, 0.811487, 1.015187, 1.422589"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000506, 0.073504, 0.160882, 0.321258, 0.642011"); + values ( "0.020669, 0.184077, 0.385272, 0.758339, 1.504472",\ + "0.020669, 0.184227, 0.385542, 0.758386, 1.504472",\ + "0.022583, 0.184227, 0.385542, 0.758386, 1.504472",\ + "0.023913, 0.184227, 0.385542, 0.758386, 1.504472",\ + "0.042731, 0.188308, 0.385542, 0.758386, 1.504752"); + } + + } /* end of arc clk_ast_rng_i_rng_val_o_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_rng_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000506, 0.073504, 0.160882, 0.321258, 0.642011"); + values ( "0.043198, 0.198183, 0.374303, 0.697816, 1.344843",\ + "0.100770, 0.256465, 0.432811, 0.755524, 1.400950",\ + "0.234375, 0.400817, 0.576577, 0.899279, 1.544683",\ + "0.266829, 0.437889, 0.613486, 0.936071, 1.581241",\ + "0.557607, 0.787741, 0.963881, 1.284820, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000506, 0.073504, 0.160882, 0.321258, 0.642011"); + values ( "0.018518, 0.294029, 0.628692, 1.245563, 2.473548",\ + "0.020629, 0.294660, 0.630087, 1.245563, 2.473548",\ + "0.041968, 0.298715, 0.630739, 1.245824, 2.473548",\ + "0.048693, 0.300646, 0.630795, 1.246251, 2.473548",\ + "0.122440, 0.339737, 0.637074, 1.249232, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000506, 0.073504, 0.160882, 0.321258, 0.642011"); + values ( "0.063098, 0.171066, 0.282997, 0.487591, 0.896779",\ + "0.123042, 0.230894, 0.342842, 0.547360, 0.956396",\ + "0.254755, 0.363148, 0.474725, 0.679218, 1.088204",\ + "0.287224, 0.396275, 0.507850, 0.712171, 1.120812",\ + "0.578369, 0.699604, 0.811487, 1.015187, 1.422589"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000506, 0.073504, 0.160882, 0.321258, 0.642011"); + values ( "0.020669, 0.183553, 0.383962, 0.756493, 1.501555",\ + "0.020669, 0.183553, 0.383962, 0.756493, 1.501555",\ + "0.022583, 0.183553, 0.383962, 0.756493, 1.501555",\ + "0.023913, 0.183907, 0.384224, 0.757011, 1.502586",\ + "0.042731, 0.188308, 0.384291, 0.757778, 1.504752"); + } + + } /* end of arc clk_ast_rng_i_rng_val_o_redg_min*/ + +} /* end of pin rng_val_o */ +bus ( rng_b_o ) { + + bus_type : BUS4_type6 ; + direction : output ; + +pin("rng_b_o[3]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001003 ; + + /* Other user defined attributes. */ + original_pin : rng_b_o[3]; + timing () { + related_pin : "clk_ast_rng_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.045041, 0.199186, 0.375056, 0.698318, 1.344843",\ + "0.102677, 0.257471, 0.433562, 0.756025, 1.400950",\ + "0.237455, 0.401819, 0.577329, 0.899780, 1.544683",\ + "0.270266, 0.438889, 0.614237, 0.936571, 1.581241",\ + "0.564763, 0.788747, 0.964628, 1.285318, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.020388, 0.295933, 0.630131, 1.247608, 2.482563",\ + "0.022435, 0.296571, 0.631520, 1.247608, 2.482563",\ + "0.043575, 0.300601, 0.632171, 1.247608, 2.482563",\ + "0.050360, 0.302518, 0.632228, 1.247608, 2.482563",\ + "0.124896, 0.341364, 0.638500, 1.250182, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.064894, 0.171688, 0.283456, 0.487892, 0.896762",\ + "0.124805, 0.231515, 0.343301, 0.547660, 0.956379",\ + "0.256621, 0.363767, 0.475184, 0.679518, 1.088186",\ + "0.289162, 0.396894, 0.508308, 0.712471, 1.120795",\ + "0.581429, 0.700226, 0.811944, 1.015486, 1.422571"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.022008, 0.185188, 0.386108, 0.758886, 1.504440",\ + "0.022008, 0.185339, 0.386379, 0.758933, 1.504440",\ + "0.023991, 0.185339, 0.386379, 0.758933, 1.504440",\ + "0.025265, 0.185339, 0.386379, 0.758933, 1.504440",\ + "0.044109, 0.189380, 0.386379, 0.758933, 1.504720"); + } + + } /* end of arc clk_ast_rng_i_rng_b_o[3]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_rng_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.045041, 0.199186, 0.375056, 0.698318, 1.344843",\ + "0.102677, 0.257471, 0.433562, 0.756025, 1.400950",\ + "0.237455, 0.401819, 0.577329, 0.899780, 1.544683",\ + "0.270266, 0.438889, 0.614237, 0.936571, 1.581241",\ + "0.564763, 0.788747, 0.964628, 1.285318, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.020388, 0.295933, 0.630131, 1.246518, 2.473548",\ + "0.022435, 0.296571, 0.631520, 1.246518, 2.473548",\ + "0.043575, 0.300601, 0.632171, 1.246779, 2.473548",\ + "0.050360, 0.302518, 0.632228, 1.247206, 2.473548",\ + "0.124896, 0.341364, 0.638500, 1.250182, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.064894, 0.171688, 0.283456, 0.487892, 0.896762",\ + "0.124805, 0.231515, 0.343301, 0.547660, 0.956379",\ + "0.256621, 0.363767, 0.475184, 0.679518, 1.088186",\ + "0.289162, 0.396894, 0.508308, 0.712471, 1.120795",\ + "0.581429, 0.700226, 0.811944, 1.015486, 1.422571"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.022008, 0.184659, 0.384798, 0.757040, 1.501523",\ + "0.022008, 0.184659, 0.384798, 0.757040, 1.501523",\ + "0.023991, 0.184659, 0.384798, 0.757040, 1.501523",\ + "0.025265, 0.185012, 0.385060, 0.757558, 1.502554",\ + "0.044109, 0.189380, 0.385129, 0.758326, 1.504720"); + } + + } /* end of arc clk_ast_rng_i_rng_b_o[3]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_falling ; + clock_gating_flag : true ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020388, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.036802, 0.036802, 0.036802, 0.036802, 0.036802",\ + "0.042346, 0.042346, 0.042346, 0.042346, 0.042346",\ + "0.109280, 0.109280, 0.109280, 0.109280, 0.109280",\ + "0.178232, 0.178232, 0.178232, 0.178232, 0.178232",\ + "0.458063, 0.458063, 0.458063, 0.458063, 0.458063"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.022008, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.053733, 0.053733, 0.053733, 0.053733, 0.053733",\ + "0.060946, 0.060946, 0.060946, 0.060946, 0.060946",\ + "0.137682, 0.137682, 0.137682, 0.137682, 0.137682",\ + "0.226588, 0.226588, 0.226588, 0.226588, 0.226588",\ + "0.644240, 0.644240, 0.644240, 0.644240, 0.644240"); + } + + } /* end of arc clk_ast_tlul_i_rng_b_o[3]_cgsf*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + clock_gating_flag : true ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020388, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.034468, -0.034468, -0.034468, -0.034468, -0.034468",\ + "-0.040015, -0.040015, -0.040015, -0.040015, -0.040015",\ + "-0.106260, -0.106260, -0.106260, -0.106260, -0.106260",\ + "-0.173208, -0.173208, -0.173208, -0.173208, -0.173208",\ + "-0.445027, -0.445027, -0.445027, -0.445027, -0.445027"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.022008, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.046633, -0.046633, -0.046633, -0.046633, -0.046633",\ + "-0.053872, -0.053872, -0.053872, -0.053872, -0.053872",\ + "-0.131912, -0.131912, -0.131912, -0.131912, -0.131912",\ + "-0.220120, -0.220120, -0.220120, -0.220120, -0.220120",\ + "-0.629632, -0.629632, -0.629632, -0.629632, -0.629632"); + } + + } /* end of arc clk_ast_tlul_i_rng_b_o[3]_cghr*/ + +} /* end of pin rng_b_o[3] */ + +pin("rng_b_o[2]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001003 ; + + /* Other user defined attributes. */ + original_pin : rng_b_o[2]; + timing () { + related_pin : "clk_ast_rng_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.045041, 0.199186, 0.375056, 0.698318, 1.344843",\ + "0.102677, 0.257471, 0.433562, 0.756025, 1.400950",\ + "0.237455, 0.401819, 0.577329, 0.899780, 1.544683",\ + "0.270266, 0.438889, 0.614237, 0.936571, 1.581241",\ + "0.564763, 0.788747, 0.964628, 1.285318, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.020388, 0.295933, 0.630131, 1.247608, 2.482563",\ + "0.022435, 0.296571, 0.631520, 1.247608, 2.482563",\ + "0.043575, 0.300601, 0.632171, 1.247608, 2.482563",\ + "0.050360, 0.302518, 0.632228, 1.247608, 2.482563",\ + "0.124896, 0.341364, 0.638500, 1.250182, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.064894, 0.171688, 0.283456, 0.487892, 0.896762",\ + "0.124805, 0.231515, 0.343301, 0.547660, 0.956379",\ + "0.256621, 0.363767, 0.475184, 0.679518, 1.088186",\ + "0.289162, 0.396894, 0.508308, 0.712471, 1.120795",\ + "0.581429, 0.700226, 0.811944, 1.015486, 1.422571"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.022008, 0.185188, 0.386108, 0.758886, 1.504440",\ + "0.022008, 0.185339, 0.386379, 0.758933, 1.504440",\ + "0.023991, 0.185339, 0.386379, 0.758933, 1.504440",\ + "0.025265, 0.185339, 0.386379, 0.758933, 1.504440",\ + "0.044109, 0.189380, 0.386379, 0.758933, 1.504720"); + } + + } /* end of arc clk_ast_rng_i_rng_b_o[2]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_rng_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.045041, 0.199186, 0.375056, 0.698318, 1.344843",\ + "0.102677, 0.257471, 0.433562, 0.756025, 1.400950",\ + "0.237455, 0.401819, 0.577329, 0.899780, 1.544683",\ + "0.270266, 0.438889, 0.614237, 0.936571, 1.581241",\ + "0.564763, 0.788747, 0.964628, 1.285318, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.020388, 0.295933, 0.630131, 1.246518, 2.473548",\ + "0.022435, 0.296571, 0.631520, 1.246518, 2.473548",\ + "0.043575, 0.300601, 0.632171, 1.246779, 2.473548",\ + "0.050360, 0.302518, 0.632228, 1.247206, 2.473548",\ + "0.124896, 0.341364, 0.638500, 1.250182, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.064894, 0.171688, 0.283456, 0.487892, 0.896762",\ + "0.124805, 0.231515, 0.343301, 0.547660, 0.956379",\ + "0.256621, 0.363767, 0.475184, 0.679518, 1.088186",\ + "0.289162, 0.396894, 0.508308, 0.712471, 1.120795",\ + "0.581429, 0.700226, 0.811944, 1.015486, 1.422571"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.022008, 0.184659, 0.384798, 0.757040, 1.501523",\ + "0.022008, 0.184659, 0.384798, 0.757040, 1.501523",\ + "0.023991, 0.184659, 0.384798, 0.757040, 1.501523",\ + "0.025265, 0.185012, 0.385060, 0.757558, 1.502554",\ + "0.044109, 0.189380, 0.385129, 0.758326, 1.504720"); + } + + } /* end of arc clk_ast_rng_i_rng_b_o[2]_redg_min*/ + +} /* end of pin rng_b_o[2] */ + +pin("rng_b_o[1]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001003 ; + + /* Other user defined attributes. */ + original_pin : rng_b_o[1]; + timing () { + related_pin : "clk_ast_rng_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.045041, 0.199186, 0.375056, 0.698318, 1.344843",\ + "0.102677, 0.257471, 0.433562, 0.756025, 1.400950",\ + "0.237455, 0.401819, 0.577329, 0.899780, 1.544683",\ + "0.270266, 0.438889, 0.614237, 0.936571, 1.581241",\ + "0.564763, 0.788747, 0.964628, 1.285318, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.020388, 0.295933, 0.630131, 1.247608, 2.482563",\ + "0.022435, 0.296571, 0.631520, 1.247608, 2.482563",\ + "0.043575, 0.300601, 0.632171, 1.247608, 2.482563",\ + "0.050360, 0.302518, 0.632228, 1.247608, 2.482563",\ + "0.124896, 0.341364, 0.638500, 1.250182, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.064894, 0.171688, 0.283456, 0.487892, 0.896762",\ + "0.124805, 0.231515, 0.343301, 0.547660, 0.956379",\ + "0.256621, 0.363767, 0.475184, 0.679518, 1.088186",\ + "0.289162, 0.396894, 0.508308, 0.712471, 1.120795",\ + "0.581429, 0.700226, 0.811944, 1.015486, 1.422571"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.022008, 0.185188, 0.386108, 0.758886, 1.504440",\ + "0.022008, 0.185339, 0.386379, 0.758933, 1.504440",\ + "0.023991, 0.185339, 0.386379, 0.758933, 1.504440",\ + "0.025265, 0.185339, 0.386379, 0.758933, 1.504440",\ + "0.044109, 0.189380, 0.386379, 0.758933, 1.504720"); + } + + } /* end of arc clk_ast_rng_i_rng_b_o[1]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_rng_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.045041, 0.199186, 0.375056, 0.698318, 1.344843",\ + "0.102677, 0.257471, 0.433562, 0.756025, 1.400950",\ + "0.237455, 0.401819, 0.577329, 0.899780, 1.544683",\ + "0.270266, 0.438889, 0.614237, 0.936571, 1.581241",\ + "0.564763, 0.788747, 0.964628, 1.285318, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.020388, 0.295933, 0.630131, 1.246518, 2.473548",\ + "0.022435, 0.296571, 0.631520, 1.246518, 2.473548",\ + "0.043575, 0.300601, 0.632171, 1.246779, 2.473548",\ + "0.050360, 0.302518, 0.632228, 1.247206, 2.473548",\ + "0.124896, 0.341364, 0.638500, 1.250182, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.064894, 0.171688, 0.283456, 0.487892, 0.896762",\ + "0.124805, 0.231515, 0.343301, 0.547660, 0.956379",\ + "0.256621, 0.363767, 0.475184, 0.679518, 1.088186",\ + "0.289162, 0.396894, 0.508308, 0.712471, 1.120795",\ + "0.581429, 0.700226, 0.811944, 1.015486, 1.422571"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.022008, 0.184659, 0.384798, 0.757040, 1.501523",\ + "0.022008, 0.184659, 0.384798, 0.757040, 1.501523",\ + "0.023991, 0.184659, 0.384798, 0.757040, 1.501523",\ + "0.025265, 0.185012, 0.385060, 0.757558, 1.502554",\ + "0.044109, 0.189380, 0.385129, 0.758326, 1.504720"); + } + + } /* end of arc clk_ast_rng_i_rng_b_o[1]_redg_min*/ + +} /* end of pin rng_b_o[1] */ + +pin("rng_b_o[0]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001003 ; + + /* Other user defined attributes. */ + original_pin : rng_b_o[0]; + timing () { + related_pin : "clk_ast_rng_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.045041, 0.199186, 0.375056, 0.698318, 1.344843",\ + "0.102677, 0.257471, 0.433562, 0.756025, 1.400950",\ + "0.237455, 0.401819, 0.577329, 0.899780, 1.544683",\ + "0.270266, 0.438889, 0.614237, 0.936571, 1.581241",\ + "0.564763, 0.788747, 0.964628, 1.285318, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.020388, 0.295933, 0.630131, 1.247608, 2.482563",\ + "0.022435, 0.296571, 0.631520, 1.247608, 2.482563",\ + "0.043575, 0.300601, 0.632171, 1.247608, 2.482563",\ + "0.050360, 0.302518, 0.632228, 1.247608, 2.482563",\ + "0.124896, 0.341364, 0.638500, 1.250182, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.064894, 0.171688, 0.283456, 0.487892, 0.896762",\ + "0.124805, 0.231515, 0.343301, 0.547660, 0.956379",\ + "0.256621, 0.363767, 0.475184, 0.679518, 1.088186",\ + "0.289162, 0.396894, 0.508308, 0.712471, 1.120795",\ + "0.581429, 0.700226, 0.811944, 1.015486, 1.422571"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.022008, 0.185188, 0.386108, 0.758886, 1.504440",\ + "0.022008, 0.185339, 0.386379, 0.758933, 1.504440",\ + "0.023991, 0.185339, 0.386379, 0.758933, 1.504440",\ + "0.025265, 0.185339, 0.386379, 0.758933, 1.504440",\ + "0.044109, 0.189380, 0.386379, 0.758933, 1.504720"); + } + + } /* end of arc clk_ast_rng_i_rng_b_o[0]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_rng_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.045041, 0.199186, 0.375056, 0.698318, 1.344843",\ + "0.102677, 0.257471, 0.433562, 0.756025, 1.400950",\ + "0.237455, 0.401819, 0.577329, 0.899780, 1.544683",\ + "0.270266, 0.438889, 0.614237, 0.936571, 1.581241",\ + "0.564763, 0.788747, 0.964628, 1.285318, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.020388, 0.295933, 0.630131, 1.246518, 2.473548",\ + "0.022435, 0.296571, 0.631520, 1.246518, 2.473548",\ + "0.043575, 0.300601, 0.632171, 1.246779, 2.473548",\ + "0.050360, 0.302518, 0.632228, 1.247206, 2.473548",\ + "0.124896, 0.341364, 0.638500, 1.250182, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.064894, 0.171688, 0.283456, 0.487892, 0.896762",\ + "0.124805, 0.231515, 0.343301, 0.547660, 0.956379",\ + "0.256621, 0.363767, 0.475184, 0.679518, 1.088186",\ + "0.289162, 0.396894, 0.508308, 0.712471, 1.120795",\ + "0.581429, 0.700226, 0.811944, 1.015486, 1.422571"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.022008, 0.184659, 0.384798, 0.757040, 1.501523",\ + "0.022008, 0.184659, 0.384798, 0.757040, 1.501523",\ + "0.023991, 0.184659, 0.384798, 0.757040, 1.501523",\ + "0.025265, 0.185012, 0.385060, 0.757558, 1.502554",\ + "0.044109, 0.189380, 0.385129, 0.758326, 1.504720"); + } + + } /* end of arc clk_ast_rng_i_rng_b_o[0]_redg_min*/ + +} /* end of pin rng_b_o[0] */ +} /* end of bus rng_b_o */ +bus ( entropy_rsp_i ) { + + bus_type : BUS34_type9 ; + direction : input ; + +pin("entropy_rsp_i[33]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001563 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[33]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "1.119801, 1.062115, 1.000165, 1.001253, 1.020223",\ + "1.200891, 1.143205, 1.081255, 1.082343, 1.101313",\ + "1.316914, 1.259228, 1.197278, 1.198366, 1.217336",\ + "1.518457, 1.460771, 1.398821, 1.399909, 1.418879",\ + "1.859802, 1.802116, 1.740050, 1.741138, 1.760224"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.903123, 0.863686, 0.813020, 0.814108, 0.827330",\ + "1.003527, 0.964090, 0.913424, 0.914512, 0.927734",\ + "1.127836, 1.088399, 1.037733, 1.038821, 1.052043",\ + "1.347378, 1.307941, 1.257275, 1.258363, 1.271584",\ + "1.738717, 1.699280, 1.648614, 1.649702, 1.662924"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[33]_stupr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.168954, -0.118035, -0.021877, -0.003703, 0.217154",\ + "-0.249369, -0.198449, -0.102291, -0.084118, 0.136740",\ + "-0.329424, -0.278473, -0.182197, -0.164034, 0.056702",\ + "-0.457832, -0.406830, -0.310356, -0.292210, -0.071679",\ + "-0.639075, -0.587937, -0.490944, -0.472842, -0.252849"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.139897, -0.089049, 0.006833, 0.025029, 0.246173",\ + "-0.240100, -0.189184, -0.093041, -0.074866, 0.146007",\ + "-0.358064, -0.306668, -0.208689, -0.190671, 0.057939",\ + "-0.516949, -0.483468, -0.393287, -0.375391, -0.096605",\ + "-0.756377, -0.722936, -0.665170, -0.641259, -0.350671"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[33]_hldr*/ + +} /* end of pin entropy_rsp_i[33] */ + +pin("entropy_rsp_i[32]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[32]; +} /* end of pin entropy_rsp_i[32] */ + +pin("entropy_rsp_i[31]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001123 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[31]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\ + "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\ + "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\ + "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\ + "0.818496, 0.778874, 0.728184, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\ + "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\ + "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\ + "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\ + "0.940670, 0.882965, 0.769819, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[31]_stupr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\ + "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\ + "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\ + "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\ + "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\ + "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\ + "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\ + "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\ + "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[31]_hldr*/ + +} /* end of pin entropy_rsp_i[31] */ + +pin("entropy_rsp_i[30]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001123 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[30]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\ + "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\ + "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\ + "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\ + "0.818496, 0.778874, 0.728184, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\ + "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\ + "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\ + "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\ + "0.940670, 0.882965, 0.769819, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[30]_stupr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\ + "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\ + "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\ + "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\ + "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\ + "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\ + "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\ + "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\ + "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[30]_hldr*/ + +} /* end of pin entropy_rsp_i[30] */ + +pin("entropy_rsp_i[29]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001123 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[29]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\ + "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\ + "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\ + "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\ + "0.818496, 0.778874, 0.728184, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\ + "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\ + "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\ + "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\ + "0.940670, 0.882965, 0.769819, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[29]_stupr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\ + "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\ + "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\ + "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\ + "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\ + "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\ + "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\ + "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\ + "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[29]_hldr*/ + +} /* end of pin entropy_rsp_i[29] */ + +pin("entropy_rsp_i[28]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001123 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[28]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\ + "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\ + "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\ + "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\ + "0.818496, 0.778874, 0.728184, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\ + "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\ + "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\ + "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\ + "0.940670, 0.882965, 0.769819, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[28]_stupr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\ + "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\ + "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\ + "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\ + "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\ + "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\ + "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\ + "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\ + "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[28]_hldr*/ + +} /* end of pin entropy_rsp_i[28] */ + +pin("entropy_rsp_i[27]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001123 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[27]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\ + "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\ + "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\ + "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\ + "0.818496, 0.778874, 0.728184, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\ + "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\ + "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\ + "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\ + "0.940670, 0.882965, 0.769819, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[27]_stupr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\ + "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\ + "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\ + "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\ + "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\ + "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\ + "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\ + "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\ + "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[27]_hldr*/ + +} /* end of pin entropy_rsp_i[27] */ + +pin("entropy_rsp_i[26]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001123 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[26]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\ + "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\ + "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\ + "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\ + "0.818496, 0.778874, 0.728184, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\ + "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\ + "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\ + "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\ + "0.940670, 0.882965, 0.769819, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[26]_stupr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\ + "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\ + "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\ + "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\ + "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\ + "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\ + "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\ + "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\ + "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[26]_hldr*/ + +} /* end of pin entropy_rsp_i[26] */ + +pin("entropy_rsp_i[25]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001123 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[25]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\ + "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\ + "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\ + "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\ + "0.818496, 0.778874, 0.728184, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\ + "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\ + "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\ + "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\ + "0.940670, 0.882965, 0.769819, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[25]_stupr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\ + "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\ + "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\ + "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\ + "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\ + "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\ + "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\ + "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\ + "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[25]_hldr*/ + +} /* end of pin entropy_rsp_i[25] */ + +pin("entropy_rsp_i[24]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001123 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[24]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\ + "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\ + "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\ + "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\ + "0.818496, 0.778874, 0.728184, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\ + "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\ + "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\ + "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\ + "0.940670, 0.882965, 0.769819, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[24]_stupr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\ + "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\ + "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\ + "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\ + "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\ + "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\ + "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\ + "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\ + "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[24]_hldr*/ + +} /* end of pin entropy_rsp_i[24] */ + +pin("entropy_rsp_i[23]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001123 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[23]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\ + "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\ + "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\ + "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\ + "0.818496, 0.778874, 0.728184, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\ + "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\ + "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\ + "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\ + "0.940670, 0.882965, 0.769819, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[23]_stupr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\ + "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\ + "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\ + "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\ + "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\ + "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\ + "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\ + "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\ + "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[23]_hldr*/ + +} /* end of pin entropy_rsp_i[23] */ + +pin("entropy_rsp_i[22]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001123 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[22]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\ + "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\ + "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\ + "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\ + "0.818496, 0.778874, 0.728184, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\ + "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\ + "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\ + "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\ + "0.940670, 0.882965, 0.769819, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[22]_stupr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\ + "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\ + "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\ + "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\ + "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\ + "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\ + "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\ + "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\ + "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[22]_hldr*/ + +} /* end of pin entropy_rsp_i[22] */ + +pin("entropy_rsp_i[21]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001123 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[21]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\ + "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\ + "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\ + "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\ + "0.818496, 0.778874, 0.728184, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\ + "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\ + "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\ + "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\ + "0.940670, 0.882965, 0.769819, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[21]_stupr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\ + "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\ + "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\ + "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\ + "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\ + "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\ + "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\ + "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\ + "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[21]_hldr*/ + +} /* end of pin entropy_rsp_i[21] */ + +pin("entropy_rsp_i[20]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001123 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[20]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\ + "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\ + "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\ + "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\ + "0.818496, 0.778874, 0.728184, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\ + "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\ + "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\ + "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\ + "0.940670, 0.882965, 0.769819, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[20]_stupr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\ + "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\ + "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\ + "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\ + "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\ + "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\ + "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\ + "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\ + "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[20]_hldr*/ + +} /* end of pin entropy_rsp_i[20] */ + +pin("entropy_rsp_i[19]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001123 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[19]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\ + "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\ + "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\ + "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\ + "0.818496, 0.778874, 0.728184, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\ + "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\ + "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\ + "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\ + "0.940670, 0.882965, 0.769819, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[19]_stupr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\ + "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\ + "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\ + "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\ + "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\ + "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\ + "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\ + "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\ + "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[19]_hldr*/ + +} /* end of pin entropy_rsp_i[19] */ + +pin("entropy_rsp_i[18]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001123 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[18]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\ + "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\ + "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\ + "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\ + "0.818496, 0.778874, 0.728184, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\ + "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\ + "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\ + "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\ + "0.940670, 0.882965, 0.769819, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[18]_stupr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\ + "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\ + "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\ + "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\ + "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\ + "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\ + "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\ + "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\ + "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[18]_hldr*/ + +} /* end of pin entropy_rsp_i[18] */ + +pin("entropy_rsp_i[17]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001123 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[17]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\ + "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\ + "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\ + "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\ + "0.818496, 0.778874, 0.728184, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\ + "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\ + "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\ + "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\ + "0.940670, 0.882965, 0.769819, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[17]_stupr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\ + "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\ + "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\ + "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\ + "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\ + "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\ + "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\ + "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\ + "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[17]_hldr*/ + +} /* end of pin entropy_rsp_i[17] */ + +pin("entropy_rsp_i[16]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001123 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[16]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\ + "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\ + "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\ + "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\ + "0.818496, 0.778874, 0.728184, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\ + "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\ + "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\ + "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\ + "0.940670, 0.882965, 0.769819, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[16]_stupr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\ + "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\ + "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\ + "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\ + "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\ + "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\ + "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\ + "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\ + "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[16]_hldr*/ + +} /* end of pin entropy_rsp_i[16] */ + +pin("entropy_rsp_i[15]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001123 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[15]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\ + "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\ + "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\ + "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\ + "0.818496, 0.778874, 0.728184, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\ + "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\ + "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\ + "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\ + "0.940670, 0.882965, 0.769819, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[15]_stupr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\ + "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\ + "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\ + "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\ + "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\ + "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\ + "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\ + "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\ + "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[15]_hldr*/ + +} /* end of pin entropy_rsp_i[15] */ + +pin("entropy_rsp_i[14]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001123 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[14]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\ + "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\ + "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\ + "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\ + "0.818496, 0.778874, 0.728184, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\ + "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\ + "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\ + "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\ + "0.940670, 0.882965, 0.769819, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[14]_stupr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\ + "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\ + "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\ + "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\ + "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\ + "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\ + "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\ + "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\ + "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[14]_hldr*/ + +} /* end of pin entropy_rsp_i[14] */ + +pin("entropy_rsp_i[13]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001123 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[13]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\ + "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\ + "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\ + "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\ + "0.818496, 0.778874, 0.728184, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\ + "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\ + "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\ + "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\ + "0.940670, 0.882965, 0.769819, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[13]_stupr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\ + "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\ + "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\ + "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\ + "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\ + "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\ + "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\ + "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\ + "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[13]_hldr*/ + +} /* end of pin entropy_rsp_i[13] */ + +pin("entropy_rsp_i[12]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001123 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[12]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\ + "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\ + "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\ + "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\ + "0.818496, 0.778874, 0.728184, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\ + "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\ + "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\ + "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\ + "0.940670, 0.882965, 0.769819, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[12]_stupr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\ + "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\ + "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\ + "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\ + "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\ + "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\ + "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\ + "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\ + "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[12]_hldr*/ + +} /* end of pin entropy_rsp_i[12] */ + +pin("entropy_rsp_i[11]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001123 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[11]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\ + "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\ + "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\ + "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\ + "0.818496, 0.778874, 0.728184, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\ + "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\ + "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\ + "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\ + "0.940670, 0.882965, 0.769819, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[11]_stupr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\ + "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\ + "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\ + "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\ + "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\ + "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\ + "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\ + "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\ + "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[11]_hldr*/ + +} /* end of pin entropy_rsp_i[11] */ + +pin("entropy_rsp_i[10]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001123 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[10]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\ + "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\ + "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\ + "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\ + "0.818496, 0.778874, 0.728184, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\ + "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\ + "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\ + "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\ + "0.940670, 0.882965, 0.769819, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[10]_stupr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\ + "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\ + "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\ + "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\ + "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\ + "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\ + "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\ + "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\ + "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[10]_hldr*/ + +} /* end of pin entropy_rsp_i[10] */ + +pin("entropy_rsp_i[9]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001123 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[9]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\ + "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\ + "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\ + "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\ + "0.818496, 0.778874, 0.728184, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\ + "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\ + "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\ + "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\ + "0.940670, 0.882965, 0.769819, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[9]_stupr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\ + "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\ + "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\ + "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\ + "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\ + "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\ + "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\ + "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\ + "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[9]_hldr*/ + +} /* end of pin entropy_rsp_i[9] */ + +pin("entropy_rsp_i[8]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001123 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[8]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\ + "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\ + "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\ + "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\ + "0.818496, 0.778874, 0.728184, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\ + "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\ + "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\ + "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\ + "0.940670, 0.882965, 0.769819, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[8]_stupr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\ + "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\ + "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\ + "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\ + "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\ + "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\ + "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\ + "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\ + "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[8]_hldr*/ + +} /* end of pin entropy_rsp_i[8] */ + +pin("entropy_rsp_i[7]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001123 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[7]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\ + "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\ + "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\ + "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\ + "0.818496, 0.778874, 0.728184, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\ + "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\ + "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\ + "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\ + "0.940670, 0.882965, 0.769819, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[7]_stupr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\ + "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\ + "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\ + "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\ + "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\ + "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\ + "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\ + "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\ + "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[7]_hldr*/ + +} /* end of pin entropy_rsp_i[7] */ + +pin("entropy_rsp_i[6]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001123 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[6]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\ + "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\ + "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\ + "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\ + "0.818496, 0.778874, 0.728184, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\ + "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\ + "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\ + "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\ + "0.940670, 0.882965, 0.769819, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[6]_stupr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\ + "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\ + "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\ + "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\ + "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\ + "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\ + "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\ + "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\ + "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[6]_hldr*/ + +} /* end of pin entropy_rsp_i[6] */ + +pin("entropy_rsp_i[5]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001123 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[5]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\ + "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\ + "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\ + "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\ + "0.818496, 0.778874, 0.728184, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\ + "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\ + "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\ + "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\ + "0.940670, 0.882965, 0.769819, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[5]_stupr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\ + "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\ + "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\ + "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\ + "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\ + "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\ + "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\ + "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\ + "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[5]_hldr*/ + +} /* end of pin entropy_rsp_i[5] */ + +pin("entropy_rsp_i[4]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001123 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[4]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\ + "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\ + "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\ + "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\ + "0.818496, 0.778874, 0.728184, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\ + "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\ + "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\ + "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\ + "0.940670, 0.882965, 0.769819, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[4]_stupr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\ + "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\ + "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\ + "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\ + "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\ + "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\ + "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\ + "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\ + "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[4]_hldr*/ + +} /* end of pin entropy_rsp_i[4] */ + +pin("entropy_rsp_i[3]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001123 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[3]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\ + "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\ + "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\ + "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\ + "0.818496, 0.778874, 0.728184, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\ + "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\ + "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\ + "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\ + "0.940670, 0.882965, 0.769819, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[3]_stupr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\ + "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\ + "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\ + "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\ + "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\ + "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\ + "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\ + "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\ + "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[3]_hldr*/ + +} /* end of pin entropy_rsp_i[3] */ + +pin("entropy_rsp_i[2]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001123 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[2]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\ + "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\ + "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\ + "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\ + "0.818496, 0.778874, 0.728184, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\ + "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\ + "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\ + "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\ + "0.940670, 0.882965, 0.769819, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[2]_stupr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\ + "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\ + "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\ + "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\ + "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\ + "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\ + "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\ + "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\ + "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[2]_hldr*/ + +} /* end of pin entropy_rsp_i[2] */ + +pin("entropy_rsp_i[1]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001123 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[1]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\ + "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\ + "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\ + "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\ + "0.818496, 0.778874, 0.728184, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\ + "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\ + "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\ + "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\ + "0.940670, 0.882965, 0.769819, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[1]_stupr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\ + "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\ + "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\ + "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\ + "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\ + "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\ + "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\ + "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\ + "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[1]_hldr*/ + +} /* end of pin entropy_rsp_i[1] */ + +pin("entropy_rsp_i[0]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001123 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[0]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\ + "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\ + "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\ + "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\ + "0.818496, 0.778874, 0.728184, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\ + "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\ + "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\ + "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\ + "0.940670, 0.882965, 0.769819, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[0]_stupr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\ + "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\ + "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\ + "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\ + "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\ + "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\ + "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\ + "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\ + "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[0]_hldr*/ + +} /* end of pin entropy_rsp_i[0] */ +} /* end of bus entropy_rsp_i */ +bus ( entropy_req_o ) { + + bus_type : BUS1_type10 ; + direction : output ; + +pin("entropy_req_o[0]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : entropy_req_o[0]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.072998, 0.160503, 0.321005, 0.642011"); + values ( "0.041147, 0.197164, 0.373538, 0.697306, 1.344843",\ + "0.098611, 0.255444, 0.432048, 0.755015, 1.400950",\ + "0.230794, 0.399801, 0.575814, 0.898771, 1.544683",\ + "0.262809, 0.436873, 0.612723, 0.935562, 1.581241",\ + "0.549011, 0.786720, 0.963122, 1.284314, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.072998, 0.160503, 0.321005, 0.642011"); + values ( "0.016407, 0.292097, 0.627231, 1.245675, 2.482563",\ + "0.018818, 0.292719, 0.628632, 1.245675, 2.482563",\ + "0.040240, 0.296800, 0.629285, 1.245675, 2.482563",\ + "0.046879, 0.298746, 0.629340, 1.245675, 2.482563",\ + "0.119467, 0.338085, 0.635627, 1.248267, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.072998, 0.160503, 0.321005, 0.642011"); + values ( "0.061012, 0.170429, 0.282525, 0.487280, 0.896790",\ + "0.121003, 0.230257, 0.342370, 0.547049, 0.956407",\ + "0.252523, 0.362513, 0.474253, 0.678907, 1.088215",\ + "0.284909, 0.395640, 0.507378, 0.711860, 1.120823",\ + "0.574684, 0.698966, 0.811016, 1.014877, 1.422600"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.072998, 0.160503, 0.321005, 0.642011"); + values ( "0.018854, 0.182937, 0.384410, 0.757771, 1.504492",\ + "0.018854, 0.183085, 0.384681, 0.757818, 1.504492",\ + "0.021110, 0.183085, 0.384681, 0.757818, 1.504492",\ + "0.022486, 0.183085, 0.384681, 0.757818, 1.504492",\ + "0.041128, 0.187207, 0.384681, 0.757818, 1.504772"); + } + + } /* end of arc clk_ast_es_i_entropy_req_o[0]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_es_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.072998, 0.160503, 0.321005, 0.642011"); + values ( "0.041147, 0.197164, 0.373538, 0.697306, 1.344843",\ + "0.098611, 0.255444, 0.432048, 0.755015, 1.400950",\ + "0.230794, 0.399801, 0.575814, 0.898771, 1.544683",\ + "0.262809, 0.436873, 0.612723, 0.935562, 1.581241",\ + "0.549011, 0.786720, 0.963122, 1.284314, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.072998, 0.160503, 0.321005, 0.642011"); + values ( "0.016407, 0.292097, 0.627231, 1.244593, 2.473548",\ + "0.018818, 0.292719, 0.628632, 1.244593, 2.473548",\ + "0.040240, 0.296800, 0.629285, 1.244855, 2.473548",\ + "0.046879, 0.298746, 0.629340, 1.245281, 2.473548",\ + "0.119467, 0.338085, 0.635627, 1.248267, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.072998, 0.160503, 0.321005, 0.642011"); + values ( "0.061012, 0.170429, 0.282525, 0.487280, 0.896790",\ + "0.121003, 0.230257, 0.342370, 0.547049, 0.956407",\ + "0.252523, 0.362513, 0.474253, 0.678907, 1.088215",\ + "0.284909, 0.395640, 0.507378, 0.711860, 1.120823",\ + "0.574684, 0.698966, 0.811016, 1.014877, 1.422600"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.072998, 0.160503, 0.321005, 0.642011"); + values ( "0.018854, 0.182418, 0.383102, 0.755926, 1.501575",\ + "0.018854, 0.182418, 0.383102, 0.755926, 1.501575",\ + "0.021110, 0.182418, 0.383102, 0.755926, 1.501575",\ + "0.022486, 0.182773, 0.383362, 0.756444, 1.502606",\ + "0.041128, 0.187207, 0.383428, 0.757210, 1.504772"); + } + + } /* end of arc clk_ast_es_i_entropy_req_o[0]_redg_min*/ + +} /* end of pin entropy_req_o[0] */ +} /* end of bus entropy_req_o */ +bus ( fla_alert_src_i ) { + + bus_type : BUS2_type5 ; + direction : input ; + +pin("fla_alert_src_i[1]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000977 ; + + /* Other user defined attributes. */ + original_pin : fla_alert_src_i[1]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.160061, 0.122171, 0.071764, 0.072890, 0.086576",\ + "0.244155, 0.206260, 0.155798, 0.156930, 0.170689",\ + "0.325133, 0.287001, 0.236508, 0.237633, 0.251310",\ + "0.464429, 0.425692, 0.375119, 0.376227, 0.389693",\ + "0.687556, 0.647617, 0.596849, 0.597922, 0.610956"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.188609, 0.130944, 0.016876, 0.021970, 0.083878",\ + "0.276270, 0.218603, 0.104578, 0.109703, 0.171989",\ + "0.365048, 0.307375, 0.193490, 0.198718, 0.262247",\ + "0.519717, 0.462029, 0.348488, 0.353966, 0.420536",\ + "0.771986, 0.714301, 0.601221, 0.607099, 0.678536"); + } + + } /* end of arc clk_ast_alert_i_fla_alert_src_i[1]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.092219, -0.058653, -0.001237, 0.026220, 0.359896",\ + "-0.176268, -0.142720, -0.085214, -0.058223, 0.269794",\ + "-0.257056, -0.223577, -0.165901, -0.140924, 0.162616",\ + "-0.395865, -0.362566, -0.304455, -0.284621, -0.043580",\ + "-0.617889, -0.584914, -0.525934, -0.516364, -0.400062"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.101777, -0.050927, 0.044966, 0.063162, 0.284294",\ + "-0.189465, -0.138565, -0.042479, -0.024300, 0.196634",\ + "-0.278331, -0.227265, -0.130550, -0.112424, 0.107856",\ + "-0.433215, -0.381745, -0.283488, -0.265494, -0.046811",\ + "-0.685809, -0.633481, -0.532401, -0.514612, -0.298423"); + } + + } /* end of arc clk_ast_alert_i_fla_alert_src_i[1]_hldr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : recovery_rising ; + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.346181, 0.303572, 0.245705, 0.249110, 0.290489",\ + "0.442377, 0.399789, 0.341790, 0.345163, 0.386153",\ + "0.570076, 0.527583, 0.468994, 0.472224, 0.511474",\ + "0.816390, 0.774143, 0.714024, 0.716882, 0.751614",\ + "1.243561, 1.201654, 1.139151, 1.141470, 1.169661"); + } + + } /* end of arc clk_ast_alert_i_fla_alert_src_i[1]_recfr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : removal_rising ; + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.258352, -0.220900, -0.161340, -0.151153, -0.027357",\ + "-0.354483, -0.317000, -0.257562, -0.247380, -0.123649",\ + "-0.481891, -0.444270, -0.385376, -0.375219, -0.251777",\ + "-0.727449, -0.689470, -0.631990, -0.621894, -0.499204",\ + "-1.152401, -1.113697, -1.058374, -1.048432, -0.927596"); + } + + } /* end of arc clk_ast_alert_i_fla_alert_src_i[1]_remfr*/ + +} /* end of pin fla_alert_src_i[1] */ + +pin("fla_alert_src_i[0]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001210 ; + + /* Other user defined attributes. */ + original_pin : fla_alert_src_i[0]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.153898, 0.096234, -0.017862, -0.012789, 0.048865",\ + "0.234547, 0.176873, 0.063006, 0.068247, 0.131938",\ + "0.312922, 0.255231, 0.141780, 0.147323, 0.214693",\ + "0.443628, 0.385987, 0.272716, 0.278561, 0.349586",\ + "0.643976, 0.586670, 0.471971, 0.477562, 0.545510"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.135497, 0.097521, 0.047194, 0.048307, 0.061839",\ + "0.227162, 0.188584, 0.138031, 0.139144, 0.152665",\ + "0.314547, 0.274830, 0.224128, 0.225207, 0.238331",\ + "0.459106, 0.419271, 0.367632, 0.368682, 0.381446",\ + "0.699539, 0.659946, 0.606277, 0.607276, 0.619410"); + } + + } /* end of arc clk_ast_alert_i_fla_alert_src_i[0]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.067048, -0.016232, 0.079533, 0.097739, 0.319005",\ + "-0.147841, -0.096754, 0.000043, 0.018162, 0.238358",\ + "-0.226477, -0.174901, -0.076238, -0.058278, 0.159985",\ + "-0.357390, -0.304774, -0.203323, -0.185507, 0.031000",\ + "-0.557290, -0.502515, -0.398294, -0.380283, -0.161393"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.067653, -0.034085, 0.023249, 0.050680, 0.384046",\ + "-0.158725, -0.125379, -0.067382, -0.046199, 0.211248",\ + "-0.245194, -0.212186, -0.153370, -0.141879, -0.002219",\ + "-0.386154, -0.352349, -0.293338, -0.283677, -0.166272",\ + "-0.618941, -0.583206, -0.524120, -0.514248, -0.394277"); + } + + } /* end of arc clk_ast_alert_i_fla_alert_src_i[0]_hldr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : recovery_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.348301, 0.305676, 0.248104, 0.251583, 0.293858",\ + "0.429286, 0.386661, 0.329089, 0.332567, 0.374842",\ + "0.504635, 0.462011, 0.404396, 0.407864, 0.450008",\ + "0.638699, 0.596084, 0.538251, 0.541665, 0.583146",\ + "0.863013, 0.820471, 0.762185, 0.765489, 0.805634"); + } + + } /* end of arc clk_ast_alert_i_fla_alert_src_i[0]_recrr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : removal_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.260501, -0.223062, -0.163229, -0.153056, -0.029425",\ + "-0.341485, -0.304046, -0.244213, -0.234040, -0.110409",\ + "-0.416836, -0.379397, -0.319604, -0.309428, -0.185759",\ + "-0.550887, -0.513443, -0.453851, -0.443663, -0.319850",\ + "-0.774977, -0.737427, -0.678253, -0.668084, -0.544492"); + } + + } /* end of arc clk_ast_alert_i_fla_alert_src_i[0]_remrr*/ + +} /* end of pin fla_alert_src_i[0] */ +} /* end of bus fla_alert_src_i */ +bus ( otp_alert_src_i ) { + + bus_type : BUS2_type5 ; + direction : input ; + +pin("otp_alert_src_i[1]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000977 ; + + /* Other user defined attributes. */ + original_pin : otp_alert_src_i[1]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.160061, 0.122171, 0.071764, 0.072890, 0.086576",\ + "0.244155, 0.206260, 0.155798, 0.156930, 0.170689",\ + "0.325133, 0.287001, 0.236508, 0.237633, 0.251310",\ + "0.464429, 0.425692, 0.375119, 0.376227, 0.389693",\ + "0.687556, 0.647617, 0.596849, 0.597922, 0.610956"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.188609, 0.130944, 0.016876, 0.021970, 0.083878",\ + "0.276270, 0.218603, 0.104578, 0.109703, 0.171989",\ + "0.365048, 0.307375, 0.193490, 0.198718, 0.262247",\ + "0.519717, 0.462029, 0.348488, 0.353966, 0.420536",\ + "0.771986, 0.714301, 0.601221, 0.607099, 0.678536"); + } + + } /* end of arc clk_ast_alert_i_otp_alert_src_i[1]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.092219, -0.058653, -0.001237, 0.026220, 0.359896",\ + "-0.176268, -0.142720, -0.085214, -0.058223, 0.269794",\ + "-0.257056, -0.223577, -0.165901, -0.140924, 0.162616",\ + "-0.395865, -0.362566, -0.304455, -0.284621, -0.043580",\ + "-0.617889, -0.584914, -0.525934, -0.516364, -0.400062"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.101777, -0.050927, 0.044966, 0.063162, 0.284294",\ + "-0.189465, -0.138565, -0.042479, -0.024300, 0.196634",\ + "-0.278331, -0.227265, -0.130550, -0.112424, 0.107856",\ + "-0.433215, -0.381745, -0.283488, -0.265494, -0.046811",\ + "-0.685809, -0.633481, -0.532401, -0.514612, -0.298423"); + } + + } /* end of arc clk_ast_alert_i_otp_alert_src_i[1]_hldr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : recovery_rising ; + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.346181, 0.303572, 0.245705, 0.249110, 0.290489",\ + "0.442377, 0.399789, 0.341790, 0.345163, 0.386153",\ + "0.570076, 0.527583, 0.468994, 0.472224, 0.511474",\ + "0.816390, 0.774143, 0.714024, 0.716882, 0.751614",\ + "1.243561, 1.201654, 1.139151, 1.141470, 1.169661"); + } + + } /* end of arc clk_ast_alert_i_otp_alert_src_i[1]_recfr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : removal_rising ; + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.258352, -0.220900, -0.161340, -0.151153, -0.027357",\ + "-0.354483, -0.317000, -0.257562, -0.247380, -0.123649",\ + "-0.481891, -0.444270, -0.385376, -0.375219, -0.251777",\ + "-0.727449, -0.689470, -0.631990, -0.621894, -0.499204",\ + "-1.152401, -1.113697, -1.058374, -1.048432, -0.927596"); + } + + } /* end of arc clk_ast_alert_i_otp_alert_src_i[1]_remfr*/ + +} /* end of pin otp_alert_src_i[1] */ + +pin("otp_alert_src_i[0]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001210 ; + + /* Other user defined attributes. */ + original_pin : otp_alert_src_i[0]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.153898, 0.096234, -0.017862, -0.012789, 0.048865",\ + "0.234547, 0.176873, 0.063006, 0.068247, 0.131938",\ + "0.312922, 0.255231, 0.141780, 0.147323, 0.214693",\ + "0.443628, 0.385987, 0.272716, 0.278561, 0.349586",\ + "0.643976, 0.586670, 0.471971, 0.477562, 0.545510"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.135497, 0.097521, 0.047194, 0.048307, 0.061839",\ + "0.227162, 0.188584, 0.138031, 0.139144, 0.152665",\ + "0.314547, 0.274830, 0.224128, 0.225207, 0.238331",\ + "0.459106, 0.419271, 0.367632, 0.368682, 0.381446",\ + "0.699539, 0.659946, 0.606277, 0.607276, 0.619410"); + } + + } /* end of arc clk_ast_alert_i_otp_alert_src_i[0]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.067048, -0.016232, 0.079533, 0.097739, 0.319005",\ + "-0.147841, -0.096754, 0.000043, 0.018162, 0.238358",\ + "-0.226477, -0.174901, -0.076238, -0.058278, 0.159985",\ + "-0.357390, -0.304774, -0.203323, -0.185507, 0.031000",\ + "-0.557290, -0.502515, -0.398294, -0.380283, -0.161393"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.067653, -0.034085, 0.023249, 0.050680, 0.384046",\ + "-0.158725, -0.125379, -0.067382, -0.046199, 0.211248",\ + "-0.245194, -0.212186, -0.153370, -0.141879, -0.002219",\ + "-0.386154, -0.352349, -0.293338, -0.283677, -0.166272",\ + "-0.618941, -0.583206, -0.524120, -0.514248, -0.394277"); + } + + } /* end of arc clk_ast_alert_i_otp_alert_src_i[0]_hldr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : recovery_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.348301, 0.305676, 0.248104, 0.251583, 0.293858",\ + "0.429286, 0.386661, 0.329089, 0.332567, 0.374842",\ + "0.504635, 0.462011, 0.404396, 0.407864, 0.450008",\ + "0.638699, 0.596084, 0.538251, 0.541665, 0.583146",\ + "0.863013, 0.820471, 0.762185, 0.765489, 0.805634"); + } + + } /* end of arc clk_ast_alert_i_otp_alert_src_i[0]_recrr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : removal_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.260501, -0.223062, -0.163229, -0.153056, -0.029425",\ + "-0.341485, -0.304046, -0.244213, -0.234040, -0.110409",\ + "-0.416836, -0.379397, -0.319604, -0.309428, -0.185759",\ + "-0.550887, -0.513443, -0.453851, -0.443663, -0.319850",\ + "-0.774977, -0.737427, -0.678253, -0.668084, -0.544492"); + } + + } /* end of arc clk_ast_alert_i_otp_alert_src_i[0]_remrr*/ + +} /* end of pin otp_alert_src_i[0] */ +} /* end of bus otp_alert_src_i */ +bus ( alert_rsp_i ) { + + bus_type : BUS52_type11 ; + direction : input ; + +pin("alert_rsp_i[51]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000591 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[51]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.199726, 0.138633, 0.033463, 0.054461, 0.309637",\ + "0.287373, 0.226285, 0.121029, 0.142110, 0.398309",\ + "0.384684, 0.323610, 0.218105, 0.239430, 0.498591",\ + "0.560847, 0.499591, 0.393454, 0.414928, 0.675905",\ + "0.860633, 0.798634, 0.691077, 0.712170, 0.968509"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.214871, 0.178837, 0.123974, 0.124132, 0.126049",\ + "0.298634, 0.262602, 0.208037, 0.208173, 0.209823",\ + "0.403277, 0.367383, 0.313251, 0.313345, 0.314481",\ + "0.578488, 0.543087, 0.488416, 0.488511, 0.489666",\ + "0.868870, 0.834430, 0.778706, 0.778804, 0.779997"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[51]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.112157, -0.054218, 0.050557, 0.069205, 0.295841",\ + "-0.199804, -0.141906, -0.036659, -0.018006, 0.208689",\ + "-0.297115, -0.239335, -0.132721, -0.114053, 0.112815",\ + "-0.473050, -0.415309, -0.306338, -0.287512, -0.058720",\ + "-0.771971, -0.713924, -0.601352, -0.581984, -0.346599"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.126284, -0.091801, -0.026053, 0.006825, 0.406380",\ + "-0.209910, -0.175609, -0.109372, -0.076372, 0.324685",\ + "-0.312970, -0.278942, -0.212075, -0.178671, 0.227297",\ + "-0.483276, -0.448963, -0.383263, -0.349244, 0.064176",\ + "-0.764074, -0.729205, -0.665784, -0.630568, -0.202592"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[51]_hldr*/ + +} /* end of pin alert_rsp_i[51] */ + +pin("alert_rsp_i[50]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000589 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[50]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.192162, 0.131067, 0.025934, 0.046895, 0.301630",\ + "0.279200, 0.218116, 0.112785, 0.133940, 0.391038",\ + "0.372216, 0.311153, 0.205428, 0.226969, 0.488754",\ + "0.526955, 0.465449, 0.358834, 0.380180, 0.639596",\ + "0.781727, 0.719289, 0.610887, 0.631753, 0.885337"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.203639, 0.167601, 0.112469, 0.112646, 0.114806",\ + "0.292883, 0.256848, 0.201897, 0.202061, 0.204057",\ + "0.398578, 0.362549, 0.308291, 0.308405, 0.309779",\ + "0.587975, 0.552224, 0.497936, 0.498030, 0.499172",\ + "0.915076, 0.879998, 0.824973, 0.825069, 0.826237"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[50]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.104592, -0.046636, 0.057935, 0.076581, 0.303191",\ + "-0.191631, -0.133768, -0.028107, -0.009449, 0.217299",\ + "-0.284646, -0.226970, -0.119146, -0.100465, 0.126557",\ + "-0.438866, -0.381023, -0.270840, -0.251831, -0.020821",\ + "-0.692552, -0.634323, -0.519612, -0.499921, -0.260619"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.115174, -0.080527, -0.015220, 0.017546, 0.415745",\ + "-0.204335, -0.169799, -0.104194, -0.071353, 0.327762",\ + "-0.309715, -0.275599, -0.208862, -0.175734, 0.226866",\ + "-0.496251, -0.462141, -0.395611, -0.362029, 0.046093",\ + "-0.816650, -0.782151, -0.717215, -0.682795, -0.264493"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[50]_hldr*/ + +} /* end of pin alert_rsp_i[50] */ + +pin("alert_rsp_i[49]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000591 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[49]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.199726, 0.138633, 0.033463, 0.054461, 0.309637",\ + "0.287373, 0.226285, 0.121029, 0.142110, 0.398309",\ + "0.384684, 0.323610, 0.218105, 0.239430, 0.498591",\ + "0.560847, 0.499591, 0.393454, 0.414928, 0.675905",\ + "0.860633, 0.798634, 0.691077, 0.712170, 0.968509"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.214871, 0.178837, 0.123974, 0.124132, 0.126049",\ + "0.298634, 0.262602, 0.208037, 0.208173, 0.209823",\ + "0.403277, 0.367383, 0.313251, 0.313345, 0.314481",\ + "0.578488, 0.543087, 0.488416, 0.488511, 0.489666",\ + "0.868870, 0.834430, 0.778706, 0.778804, 0.779997"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[49]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.112157, -0.054218, 0.050557, 0.069205, 0.295841",\ + "-0.199804, -0.141906, -0.036659, -0.018006, 0.208689",\ + "-0.297115, -0.239335, -0.132721, -0.114053, 0.112815",\ + "-0.473050, -0.415309, -0.306338, -0.287512, -0.058720",\ + "-0.771971, -0.713924, -0.601352, -0.581984, -0.346599"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.126284, -0.091801, -0.026053, 0.006825, 0.406380",\ + "-0.209910, -0.175609, -0.109372, -0.076372, 0.324685",\ + "-0.312970, -0.278942, -0.212075, -0.178671, 0.227297",\ + "-0.483276, -0.448963, -0.383263, -0.349244, 0.064176",\ + "-0.764074, -0.729205, -0.665784, -0.630568, -0.202592"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[49]_hldr*/ + +} /* end of pin alert_rsp_i[49] */ + +pin("alert_rsp_i[48]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000589 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[48]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.192162, 0.131067, 0.025934, 0.046895, 0.301630",\ + "0.279200, 0.218116, 0.112785, 0.133940, 0.391038",\ + "0.372216, 0.311153, 0.205428, 0.226969, 0.488754",\ + "0.526955, 0.465449, 0.358834, 0.380180, 0.639596",\ + "0.781727, 0.719289, 0.610887, 0.631753, 0.885337"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.203639, 0.167601, 0.112469, 0.112646, 0.114806",\ + "0.292883, 0.256848, 0.201897, 0.202061, 0.204057",\ + "0.398578, 0.362549, 0.308291, 0.308405, 0.309779",\ + "0.587975, 0.552224, 0.497936, 0.498030, 0.499172",\ + "0.915076, 0.879998, 0.824973, 0.825069, 0.826237"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[48]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.104592, -0.046636, 0.057935, 0.076581, 0.303191",\ + "-0.191631, -0.133768, -0.028107, -0.009449, 0.217299",\ + "-0.284646, -0.226970, -0.119146, -0.100465, 0.126557",\ + "-0.438866, -0.381023, -0.270840, -0.251831, -0.020821",\ + "-0.692552, -0.634323, -0.519612, -0.499921, -0.260619"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.115174, -0.080527, -0.015220, 0.017546, 0.415745",\ + "-0.204335, -0.169799, -0.104194, -0.071353, 0.327762",\ + "-0.309715, -0.275599, -0.208862, -0.175734, 0.226866",\ + "-0.496251, -0.462141, -0.395611, -0.362029, 0.046093",\ + "-0.816650, -0.782151, -0.717215, -0.682795, -0.264493"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[48]_hldr*/ + +} /* end of pin alert_rsp_i[48] */ + +pin("alert_rsp_i[47]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000591 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[47]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.199726, 0.138633, 0.033463, 0.054461, 0.309637",\ + "0.287373, 0.226285, 0.121029, 0.142110, 0.398309",\ + "0.384684, 0.323610, 0.218105, 0.239430, 0.498591",\ + "0.560847, 0.499591, 0.393454, 0.414928, 0.675905",\ + "0.860633, 0.798634, 0.691077, 0.712170, 0.968509"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.214871, 0.178837, 0.123974, 0.124132, 0.126049",\ + "0.298634, 0.262602, 0.208037, 0.208173, 0.209823",\ + "0.403277, 0.367383, 0.313251, 0.313345, 0.314481",\ + "0.578488, 0.543087, 0.488416, 0.488511, 0.489666",\ + "0.868870, 0.834430, 0.778706, 0.778804, 0.779997"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[47]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.112157, -0.054218, 0.050557, 0.069205, 0.295841",\ + "-0.199804, -0.141906, -0.036659, -0.018006, 0.208689",\ + "-0.297115, -0.239335, -0.132721, -0.114053, 0.112815",\ + "-0.473050, -0.415309, -0.306338, -0.287512, -0.058720",\ + "-0.771971, -0.713924, -0.601352, -0.581984, -0.346599"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.126284, -0.091801, -0.026053, 0.006825, 0.406380",\ + "-0.209910, -0.175609, -0.109372, -0.076372, 0.324685",\ + "-0.312970, -0.278942, -0.212075, -0.178671, 0.227297",\ + "-0.483276, -0.448963, -0.383263, -0.349244, 0.064176",\ + "-0.764074, -0.729205, -0.665784, -0.630568, -0.202592"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[47]_hldr*/ + +} /* end of pin alert_rsp_i[47] */ + +pin("alert_rsp_i[46]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000589 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[46]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.192162, 0.131067, 0.025934, 0.046895, 0.301630",\ + "0.279200, 0.218116, 0.112785, 0.133940, 0.391038",\ + "0.372216, 0.311153, 0.205428, 0.226969, 0.488754",\ + "0.526955, 0.465449, 0.358834, 0.380180, 0.639596",\ + "0.781727, 0.719289, 0.610887, 0.631753, 0.885337"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.203639, 0.167601, 0.112469, 0.112646, 0.114806",\ + "0.292883, 0.256848, 0.201897, 0.202061, 0.204057",\ + "0.398578, 0.362549, 0.308291, 0.308405, 0.309779",\ + "0.587975, 0.552224, 0.497936, 0.498030, 0.499172",\ + "0.915076, 0.879998, 0.824973, 0.825069, 0.826237"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[46]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.104592, -0.046636, 0.057935, 0.076581, 0.303191",\ + "-0.191631, -0.133768, -0.028107, -0.009449, 0.217299",\ + "-0.284646, -0.226970, -0.119146, -0.100465, 0.126557",\ + "-0.438866, -0.381023, -0.270840, -0.251831, -0.020821",\ + "-0.692552, -0.634323, -0.519612, -0.499921, -0.260619"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.115174, -0.080527, -0.015220, 0.017546, 0.415745",\ + "-0.204335, -0.169799, -0.104194, -0.071353, 0.327762",\ + "-0.309715, -0.275599, -0.208862, -0.175734, 0.226866",\ + "-0.496251, -0.462141, -0.395611, -0.362029, 0.046093",\ + "-0.816650, -0.782151, -0.717215, -0.682795, -0.264493"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[46]_hldr*/ + +} /* end of pin alert_rsp_i[46] */ + +pin("alert_rsp_i[45]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000591 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[45]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.199726, 0.138633, 0.033463, 0.054461, 0.309637",\ + "0.287373, 0.226285, 0.121029, 0.142110, 0.398309",\ + "0.384684, 0.323610, 0.218105, 0.239430, 0.498591",\ + "0.560847, 0.499591, 0.393454, 0.414928, 0.675905",\ + "0.860633, 0.798634, 0.691077, 0.712170, 0.968509"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.214871, 0.178837, 0.123974, 0.124132, 0.126049",\ + "0.298634, 0.262602, 0.208037, 0.208173, 0.209823",\ + "0.403277, 0.367383, 0.313251, 0.313345, 0.314481",\ + "0.578488, 0.543087, 0.488416, 0.488511, 0.489666",\ + "0.868870, 0.834430, 0.778706, 0.778804, 0.779997"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[45]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.112157, -0.054218, 0.050557, 0.069205, 0.295841",\ + "-0.199804, -0.141906, -0.036659, -0.018006, 0.208689",\ + "-0.297115, -0.239335, -0.132721, -0.114053, 0.112815",\ + "-0.473050, -0.415309, -0.306338, -0.287512, -0.058720",\ + "-0.771971, -0.713924, -0.601352, -0.581984, -0.346599"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.126284, -0.091801, -0.026053, 0.006825, 0.406380",\ + "-0.209910, -0.175609, -0.109372, -0.076372, 0.324685",\ + "-0.312970, -0.278942, -0.212075, -0.178671, 0.227297",\ + "-0.483276, -0.448963, -0.383263, -0.349244, 0.064176",\ + "-0.764074, -0.729205, -0.665784, -0.630568, -0.202592"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[45]_hldr*/ + +} /* end of pin alert_rsp_i[45] */ + +pin("alert_rsp_i[44]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000589 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[44]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.192162, 0.131067, 0.025934, 0.046895, 0.301630",\ + "0.279200, 0.218116, 0.112785, 0.133940, 0.391038",\ + "0.372216, 0.311153, 0.205428, 0.226969, 0.488754",\ + "0.526955, 0.465449, 0.358834, 0.380180, 0.639596",\ + "0.781727, 0.719289, 0.610887, 0.631753, 0.885337"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.203639, 0.167601, 0.112469, 0.112646, 0.114806",\ + "0.292883, 0.256848, 0.201897, 0.202061, 0.204057",\ + "0.398578, 0.362549, 0.308291, 0.308405, 0.309779",\ + "0.587975, 0.552224, 0.497936, 0.498030, 0.499172",\ + "0.915076, 0.879998, 0.824973, 0.825069, 0.826237"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[44]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.104592, -0.046636, 0.057935, 0.076581, 0.303191",\ + "-0.191631, -0.133768, -0.028107, -0.009449, 0.217299",\ + "-0.284646, -0.226970, -0.119146, -0.100465, 0.126557",\ + "-0.438866, -0.381023, -0.270840, -0.251831, -0.020821",\ + "-0.692552, -0.634323, -0.519612, -0.499921, -0.260619"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.115174, -0.080527, -0.015220, 0.017546, 0.415745",\ + "-0.204335, -0.169799, -0.104194, -0.071353, 0.327762",\ + "-0.309715, -0.275599, -0.208862, -0.175734, 0.226866",\ + "-0.496251, -0.462141, -0.395611, -0.362029, 0.046093",\ + "-0.816650, -0.782151, -0.717215, -0.682795, -0.264493"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[44]_hldr*/ + +} /* end of pin alert_rsp_i[44] */ + +pin("alert_rsp_i[43]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000591 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[43]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.199726, 0.138633, 0.033463, 0.054461, 0.309637",\ + "0.287373, 0.226285, 0.121029, 0.142110, 0.398309",\ + "0.384684, 0.323610, 0.218105, 0.239430, 0.498591",\ + "0.560847, 0.499591, 0.393454, 0.414928, 0.675905",\ + "0.860633, 0.798634, 0.691077, 0.712170, 0.968509"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.214871, 0.178837, 0.123974, 0.124132, 0.126049",\ + "0.298634, 0.262602, 0.208037, 0.208173, 0.209823",\ + "0.403277, 0.367383, 0.313251, 0.313345, 0.314481",\ + "0.578488, 0.543087, 0.488416, 0.488511, 0.489666",\ + "0.868870, 0.834430, 0.778706, 0.778804, 0.779997"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[43]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.112157, -0.054218, 0.050557, 0.069205, 0.295841",\ + "-0.199804, -0.141906, -0.036659, -0.018006, 0.208689",\ + "-0.297115, -0.239335, -0.132721, -0.114053, 0.112815",\ + "-0.473050, -0.415309, -0.306338, -0.287512, -0.058720",\ + "-0.771971, -0.713924, -0.601352, -0.581984, -0.346599"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.126284, -0.091801, -0.026053, 0.006825, 0.406380",\ + "-0.209910, -0.175609, -0.109372, -0.076372, 0.324685",\ + "-0.312970, -0.278942, -0.212075, -0.178671, 0.227297",\ + "-0.483276, -0.448963, -0.383263, -0.349244, 0.064176",\ + "-0.764074, -0.729205, -0.665784, -0.630568, -0.202592"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[43]_hldr*/ + +} /* end of pin alert_rsp_i[43] */ + +pin("alert_rsp_i[42]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000589 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[42]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.192162, 0.131067, 0.025934, 0.046895, 0.301630",\ + "0.279200, 0.218116, 0.112785, 0.133940, 0.391038",\ + "0.372216, 0.311153, 0.205428, 0.226969, 0.488754",\ + "0.526955, 0.465449, 0.358834, 0.380180, 0.639596",\ + "0.781727, 0.719289, 0.610887, 0.631753, 0.885337"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.203639, 0.167601, 0.112469, 0.112646, 0.114806",\ + "0.292883, 0.256848, 0.201897, 0.202061, 0.204057",\ + "0.398578, 0.362549, 0.308291, 0.308405, 0.309779",\ + "0.587975, 0.552224, 0.497936, 0.498030, 0.499172",\ + "0.915076, 0.879998, 0.824973, 0.825069, 0.826237"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[42]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.104592, -0.046636, 0.057935, 0.076581, 0.303191",\ + "-0.191631, -0.133768, -0.028107, -0.009449, 0.217299",\ + "-0.284646, -0.226970, -0.119146, -0.100465, 0.126557",\ + "-0.438866, -0.381023, -0.270840, -0.251831, -0.020821",\ + "-0.692552, -0.634323, -0.519612, -0.499921, -0.260619"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.115174, -0.080527, -0.015220, 0.017546, 0.415745",\ + "-0.204335, -0.169799, -0.104194, -0.071353, 0.327762",\ + "-0.309715, -0.275599, -0.208862, -0.175734, 0.226866",\ + "-0.496251, -0.462141, -0.395611, -0.362029, 0.046093",\ + "-0.816650, -0.782151, -0.717215, -0.682795, -0.264493"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[42]_hldr*/ + +} /* end of pin alert_rsp_i[42] */ + +pin("alert_rsp_i[41]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000591 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[41]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.199726, 0.138633, 0.033463, 0.054461, 0.309637",\ + "0.287373, 0.226285, 0.121029, 0.142110, 0.398309",\ + "0.384684, 0.323610, 0.218105, 0.239430, 0.498591",\ + "0.560847, 0.499591, 0.393454, 0.414928, 0.675905",\ + "0.860633, 0.798634, 0.691077, 0.712170, 0.968509"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.214871, 0.178837, 0.123974, 0.124132, 0.126049",\ + "0.298634, 0.262602, 0.208037, 0.208173, 0.209823",\ + "0.403277, 0.367383, 0.313251, 0.313345, 0.314481",\ + "0.578488, 0.543087, 0.488416, 0.488511, 0.489666",\ + "0.868870, 0.834430, 0.778706, 0.778804, 0.779997"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[41]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.112157, -0.054218, 0.050557, 0.069205, 0.295841",\ + "-0.199804, -0.141906, -0.036659, -0.018006, 0.208689",\ + "-0.297115, -0.239335, -0.132721, -0.114053, 0.112815",\ + "-0.473050, -0.415309, -0.306338, -0.287512, -0.058720",\ + "-0.771971, -0.713924, -0.601352, -0.581984, -0.346599"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.126284, -0.091801, -0.026053, 0.006825, 0.406380",\ + "-0.209910, -0.175609, -0.109372, -0.076372, 0.324685",\ + "-0.312970, -0.278942, -0.212075, -0.178671, 0.227297",\ + "-0.483276, -0.448963, -0.383263, -0.349244, 0.064176",\ + "-0.764074, -0.729205, -0.665784, -0.630568, -0.202592"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[41]_hldr*/ + +} /* end of pin alert_rsp_i[41] */ + +pin("alert_rsp_i[40]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000589 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[40]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.192162, 0.131067, 0.025934, 0.046895, 0.301630",\ + "0.279200, 0.218116, 0.112785, 0.133940, 0.391038",\ + "0.372216, 0.311153, 0.205428, 0.226969, 0.488754",\ + "0.526955, 0.465449, 0.358834, 0.380180, 0.639596",\ + "0.781727, 0.719289, 0.610887, 0.631753, 0.885337"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.203639, 0.167601, 0.112469, 0.112646, 0.114806",\ + "0.292883, 0.256848, 0.201897, 0.202061, 0.204057",\ + "0.398578, 0.362549, 0.308291, 0.308405, 0.309779",\ + "0.587975, 0.552224, 0.497936, 0.498030, 0.499172",\ + "0.915076, 0.879998, 0.824973, 0.825069, 0.826237"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[40]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.104592, -0.046636, 0.057935, 0.076581, 0.303191",\ + "-0.191631, -0.133768, -0.028107, -0.009449, 0.217299",\ + "-0.284646, -0.226970, -0.119146, -0.100465, 0.126557",\ + "-0.438866, -0.381023, -0.270840, -0.251831, -0.020821",\ + "-0.692552, -0.634323, -0.519612, -0.499921, -0.260619"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.115174, -0.080527, -0.015220, 0.017546, 0.415745",\ + "-0.204335, -0.169799, -0.104194, -0.071353, 0.327762",\ + "-0.309715, -0.275599, -0.208862, -0.175734, 0.226866",\ + "-0.496251, -0.462141, -0.395611, -0.362029, 0.046093",\ + "-0.816650, -0.782151, -0.717215, -0.682795, -0.264493"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[40]_hldr*/ + +} /* end of pin alert_rsp_i[40] */ + +pin("alert_rsp_i[39]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000591 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[39]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.199726, 0.138633, 0.033463, 0.054461, 0.309637",\ + "0.287373, 0.226285, 0.121029, 0.142110, 0.398309",\ + "0.384684, 0.323610, 0.218105, 0.239430, 0.498591",\ + "0.560847, 0.499591, 0.393454, 0.414928, 0.675905",\ + "0.860633, 0.798634, 0.691077, 0.712170, 0.968509"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.214871, 0.178837, 0.123974, 0.124132, 0.126049",\ + "0.298634, 0.262602, 0.208037, 0.208173, 0.209823",\ + "0.403277, 0.367383, 0.313251, 0.313345, 0.314481",\ + "0.578488, 0.543087, 0.488416, 0.488511, 0.489666",\ + "0.868870, 0.834430, 0.778706, 0.778804, 0.779997"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[39]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.112157, -0.054218, 0.050557, 0.069205, 0.295841",\ + "-0.199804, -0.141906, -0.036659, -0.018006, 0.208689",\ + "-0.297115, -0.239335, -0.132721, -0.114053, 0.112815",\ + "-0.473050, -0.415309, -0.306338, -0.287512, -0.058720",\ + "-0.771971, -0.713924, -0.601352, -0.581984, -0.346599"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.126284, -0.091801, -0.026053, 0.006825, 0.406380",\ + "-0.209910, -0.175609, -0.109372, -0.076372, 0.324685",\ + "-0.312970, -0.278942, -0.212075, -0.178671, 0.227297",\ + "-0.483276, -0.448963, -0.383263, -0.349244, 0.064176",\ + "-0.764074, -0.729205, -0.665784, -0.630568, -0.202592"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[39]_hldr*/ + +} /* end of pin alert_rsp_i[39] */ + +pin("alert_rsp_i[38]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000589 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[38]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.192162, 0.131067, 0.025934, 0.046895, 0.301630",\ + "0.279200, 0.218116, 0.112785, 0.133940, 0.391038",\ + "0.372216, 0.311153, 0.205428, 0.226969, 0.488754",\ + "0.526955, 0.465449, 0.358834, 0.380180, 0.639596",\ + "0.781727, 0.719289, 0.610887, 0.631753, 0.885337"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.203639, 0.167601, 0.112469, 0.112646, 0.114806",\ + "0.292883, 0.256848, 0.201897, 0.202061, 0.204057",\ + "0.398578, 0.362549, 0.308291, 0.308405, 0.309779",\ + "0.587975, 0.552224, 0.497936, 0.498030, 0.499172",\ + "0.915076, 0.879998, 0.824973, 0.825069, 0.826237"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[38]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.104592, -0.046636, 0.057935, 0.076581, 0.303191",\ + "-0.191631, -0.133768, -0.028107, -0.009449, 0.217299",\ + "-0.284646, -0.226970, -0.119146, -0.100465, 0.126557",\ + "-0.438866, -0.381023, -0.270840, -0.251831, -0.020821",\ + "-0.692552, -0.634323, -0.519612, -0.499921, -0.260619"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.115174, -0.080527, -0.015220, 0.017546, 0.415745",\ + "-0.204335, -0.169799, -0.104194, -0.071353, 0.327762",\ + "-0.309715, -0.275599, -0.208862, -0.175734, 0.226866",\ + "-0.496251, -0.462141, -0.395611, -0.362029, 0.046093",\ + "-0.816650, -0.782151, -0.717215, -0.682795, -0.264493"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[38]_hldr*/ + +} /* end of pin alert_rsp_i[38] */ + +pin("alert_rsp_i[37]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000591 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[37]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.199726, 0.138633, 0.033463, 0.054461, 0.309637",\ + "0.287373, 0.226285, 0.121029, 0.142110, 0.398309",\ + "0.384684, 0.323610, 0.218105, 0.239430, 0.498591",\ + "0.560847, 0.499591, 0.393454, 0.414928, 0.675905",\ + "0.860633, 0.798634, 0.691077, 0.712170, 0.968509"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.214871, 0.178837, 0.123974, 0.124132, 0.126049",\ + "0.298634, 0.262602, 0.208037, 0.208173, 0.209823",\ + "0.403277, 0.367383, 0.313251, 0.313345, 0.314481",\ + "0.578488, 0.543087, 0.488416, 0.488511, 0.489666",\ + "0.868870, 0.834430, 0.778706, 0.778804, 0.779997"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[37]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.112157, -0.054218, 0.050557, 0.069205, 0.295841",\ + "-0.199804, -0.141906, -0.036659, -0.018006, 0.208689",\ + "-0.297115, -0.239335, -0.132721, -0.114053, 0.112815",\ + "-0.473050, -0.415309, -0.306338, -0.287512, -0.058720",\ + "-0.771971, -0.713924, -0.601352, -0.581984, -0.346599"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.126284, -0.091801, -0.026053, 0.006825, 0.406380",\ + "-0.209910, -0.175609, -0.109372, -0.076372, 0.324685",\ + "-0.312970, -0.278942, -0.212075, -0.178671, 0.227297",\ + "-0.483276, -0.448963, -0.383263, -0.349244, 0.064176",\ + "-0.764074, -0.729205, -0.665784, -0.630568, -0.202592"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[37]_hldr*/ + +} /* end of pin alert_rsp_i[37] */ + +pin("alert_rsp_i[36]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000589 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[36]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.192162, 0.131067, 0.025934, 0.046895, 0.301630",\ + "0.279200, 0.218116, 0.112785, 0.133940, 0.391038",\ + "0.372216, 0.311153, 0.205428, 0.226969, 0.488754",\ + "0.526955, 0.465449, 0.358834, 0.380180, 0.639596",\ + "0.781727, 0.719289, 0.610887, 0.631753, 0.885337"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.203639, 0.167601, 0.112469, 0.112646, 0.114806",\ + "0.292883, 0.256848, 0.201897, 0.202061, 0.204057",\ + "0.398578, 0.362549, 0.308291, 0.308405, 0.309779",\ + "0.587975, 0.552224, 0.497936, 0.498030, 0.499172",\ + "0.915076, 0.879998, 0.824973, 0.825069, 0.826237"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[36]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.104592, -0.046636, 0.057935, 0.076581, 0.303191",\ + "-0.191631, -0.133768, -0.028107, -0.009449, 0.217299",\ + "-0.284646, -0.226970, -0.119146, -0.100465, 0.126557",\ + "-0.438866, -0.381023, -0.270840, -0.251831, -0.020821",\ + "-0.692552, -0.634323, -0.519612, -0.499921, -0.260619"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.115174, -0.080527, -0.015220, 0.017546, 0.415745",\ + "-0.204335, -0.169799, -0.104194, -0.071353, 0.327762",\ + "-0.309715, -0.275599, -0.208862, -0.175734, 0.226866",\ + "-0.496251, -0.462141, -0.395611, -0.362029, 0.046093",\ + "-0.816650, -0.782151, -0.717215, -0.682795, -0.264493"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[36]_hldr*/ + +} /* end of pin alert_rsp_i[36] */ + +pin("alert_rsp_i[35]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000591 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[35]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.199726, 0.138633, 0.033463, 0.054461, 0.309637",\ + "0.287373, 0.226285, 0.121029, 0.142110, 0.398309",\ + "0.384684, 0.323610, 0.218105, 0.239430, 0.498591",\ + "0.560847, 0.499591, 0.393454, 0.414928, 0.675905",\ + "0.860633, 0.798634, 0.691077, 0.712170, 0.968509"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.214871, 0.178837, 0.123974, 0.124132, 0.126049",\ + "0.298634, 0.262602, 0.208037, 0.208173, 0.209823",\ + "0.403277, 0.367383, 0.313251, 0.313345, 0.314481",\ + "0.578488, 0.543087, 0.488416, 0.488511, 0.489666",\ + "0.868870, 0.834430, 0.778706, 0.778804, 0.779997"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[35]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.112157, -0.054218, 0.050557, 0.069205, 0.295841",\ + "-0.199804, -0.141906, -0.036659, -0.018006, 0.208689",\ + "-0.297115, -0.239335, -0.132721, -0.114053, 0.112815",\ + "-0.473050, -0.415309, -0.306338, -0.287512, -0.058720",\ + "-0.771971, -0.713924, -0.601352, -0.581984, -0.346599"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.126284, -0.091801, -0.026053, 0.006825, 0.406380",\ + "-0.209910, -0.175609, -0.109372, -0.076372, 0.324685",\ + "-0.312970, -0.278942, -0.212075, -0.178671, 0.227297",\ + "-0.483276, -0.448963, -0.383263, -0.349244, 0.064176",\ + "-0.764074, -0.729205, -0.665784, -0.630568, -0.202592"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[35]_hldr*/ + +} /* end of pin alert_rsp_i[35] */ + +pin("alert_rsp_i[34]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000589 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[34]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.192162, 0.131067, 0.025934, 0.046895, 0.301630",\ + "0.279200, 0.218116, 0.112785, 0.133940, 0.391038",\ + "0.372216, 0.311153, 0.205428, 0.226969, 0.488754",\ + "0.526955, 0.465449, 0.358834, 0.380180, 0.639596",\ + "0.781727, 0.719289, 0.610887, 0.631753, 0.885337"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.203639, 0.167601, 0.112469, 0.112646, 0.114806",\ + "0.292883, 0.256848, 0.201897, 0.202061, 0.204057",\ + "0.398578, 0.362549, 0.308291, 0.308405, 0.309779",\ + "0.587975, 0.552224, 0.497936, 0.498030, 0.499172",\ + "0.915076, 0.879998, 0.824973, 0.825069, 0.826237"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[34]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.104592, -0.046636, 0.057935, 0.076581, 0.303191",\ + "-0.191631, -0.133768, -0.028107, -0.009449, 0.217299",\ + "-0.284646, -0.226970, -0.119146, -0.100465, 0.126557",\ + "-0.438866, -0.381023, -0.270840, -0.251831, -0.020821",\ + "-0.692552, -0.634323, -0.519612, -0.499921, -0.260619"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.115174, -0.080527, -0.015220, 0.017546, 0.415745",\ + "-0.204335, -0.169799, -0.104194, -0.071353, 0.327762",\ + "-0.309715, -0.275599, -0.208862, -0.175734, 0.226866",\ + "-0.496251, -0.462141, -0.395611, -0.362029, 0.046093",\ + "-0.816650, -0.782151, -0.717215, -0.682795, -0.264493"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[34]_hldr*/ + +} /* end of pin alert_rsp_i[34] */ + +pin("alert_rsp_i[33]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000591 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[33]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.199726, 0.138633, 0.033463, 0.054461, 0.309637",\ + "0.287373, 0.226285, 0.121029, 0.142110, 0.398309",\ + "0.384684, 0.323610, 0.218105, 0.239430, 0.498591",\ + "0.560847, 0.499591, 0.393454, 0.414928, 0.675905",\ + "0.860633, 0.798634, 0.691077, 0.712170, 0.968509"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.214871, 0.178837, 0.123974, 0.124132, 0.126049",\ + "0.298634, 0.262602, 0.208037, 0.208173, 0.209823",\ + "0.403277, 0.367383, 0.313251, 0.313345, 0.314481",\ + "0.578488, 0.543087, 0.488416, 0.488511, 0.489666",\ + "0.868870, 0.834430, 0.778706, 0.778804, 0.779997"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[33]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.112157, -0.054218, 0.050557, 0.069205, 0.295841",\ + "-0.199804, -0.141906, -0.036659, -0.018006, 0.208689",\ + "-0.297115, -0.239335, -0.132721, -0.114053, 0.112815",\ + "-0.473050, -0.415309, -0.306338, -0.287512, -0.058720",\ + "-0.771971, -0.713924, -0.601352, -0.581984, -0.346599"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.126284, -0.091801, -0.026053, 0.006825, 0.406380",\ + "-0.209910, -0.175609, -0.109372, -0.076372, 0.324685",\ + "-0.312970, -0.278942, -0.212075, -0.178671, 0.227297",\ + "-0.483276, -0.448963, -0.383263, -0.349244, 0.064176",\ + "-0.764074, -0.729205, -0.665784, -0.630568, -0.202592"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[33]_hldr*/ + +} /* end of pin alert_rsp_i[33] */ + +pin("alert_rsp_i[32]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000589 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[32]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.192162, 0.131067, 0.025934, 0.046895, 0.301630",\ + "0.279200, 0.218116, 0.112785, 0.133940, 0.391038",\ + "0.372216, 0.311153, 0.205428, 0.226969, 0.488754",\ + "0.526955, 0.465449, 0.358834, 0.380180, 0.639596",\ + "0.781727, 0.719289, 0.610887, 0.631753, 0.885337"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.203639, 0.167601, 0.112469, 0.112646, 0.114806",\ + "0.292883, 0.256848, 0.201897, 0.202061, 0.204057",\ + "0.398578, 0.362549, 0.308291, 0.308405, 0.309779",\ + "0.587975, 0.552224, 0.497936, 0.498030, 0.499172",\ + "0.915076, 0.879998, 0.824973, 0.825069, 0.826237"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[32]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.104592, -0.046636, 0.057935, 0.076581, 0.303191",\ + "-0.191631, -0.133768, -0.028107, -0.009449, 0.217299",\ + "-0.284646, -0.226970, -0.119146, -0.100465, 0.126557",\ + "-0.438866, -0.381023, -0.270840, -0.251831, -0.020821",\ + "-0.692552, -0.634323, -0.519612, -0.499921, -0.260619"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.115174, -0.080527, -0.015220, 0.017546, 0.415745",\ + "-0.204335, -0.169799, -0.104194, -0.071353, 0.327762",\ + "-0.309715, -0.275599, -0.208862, -0.175734, 0.226866",\ + "-0.496251, -0.462141, -0.395611, -0.362029, 0.046093",\ + "-0.816650, -0.782151, -0.717215, -0.682795, -0.264493"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[32]_hldr*/ + +} /* end of pin alert_rsp_i[32] */ + +pin("alert_rsp_i[31]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000591 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[31]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.199726, 0.138633, 0.033463, 0.054461, 0.309637",\ + "0.287373, 0.226285, 0.121029, 0.142110, 0.398309",\ + "0.384684, 0.323610, 0.218105, 0.239430, 0.498591",\ + "0.560847, 0.499591, 0.393454, 0.414928, 0.675905",\ + "0.860633, 0.798634, 0.691077, 0.712170, 0.968509"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.214871, 0.178837, 0.123974, 0.124132, 0.126049",\ + "0.298634, 0.262602, 0.208037, 0.208173, 0.209823",\ + "0.403277, 0.367383, 0.313251, 0.313345, 0.314481",\ + "0.578488, 0.543087, 0.488416, 0.488511, 0.489666",\ + "0.868870, 0.834430, 0.778706, 0.778804, 0.779997"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[31]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.112157, -0.054218, 0.050557, 0.069205, 0.295841",\ + "-0.199804, -0.141906, -0.036659, -0.018006, 0.208689",\ + "-0.297115, -0.239335, -0.132721, -0.114053, 0.112815",\ + "-0.473050, -0.415309, -0.306338, -0.287512, -0.058720",\ + "-0.771971, -0.713924, -0.601352, -0.581984, -0.346599"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.126284, -0.091801, -0.026053, 0.006825, 0.406380",\ + "-0.209910, -0.175609, -0.109372, -0.076372, 0.324685",\ + "-0.312970, -0.278942, -0.212075, -0.178671, 0.227297",\ + "-0.483276, -0.448963, -0.383263, -0.349244, 0.064176",\ + "-0.764074, -0.729205, -0.665784, -0.630568, -0.202592"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[31]_hldr*/ + +} /* end of pin alert_rsp_i[31] */ + +pin("alert_rsp_i[30]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000589 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[30]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.192162, 0.131067, 0.025934, 0.046895, 0.301630",\ + "0.279200, 0.218116, 0.112785, 0.133940, 0.391038",\ + "0.372216, 0.311153, 0.205428, 0.226969, 0.488754",\ + "0.526955, 0.465449, 0.358834, 0.380180, 0.639596",\ + "0.781727, 0.719289, 0.610887, 0.631753, 0.885337"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.203639, 0.167601, 0.112469, 0.112646, 0.114806",\ + "0.292883, 0.256848, 0.201897, 0.202061, 0.204057",\ + "0.398578, 0.362549, 0.308291, 0.308405, 0.309779",\ + "0.587975, 0.552224, 0.497936, 0.498030, 0.499172",\ + "0.915076, 0.879998, 0.824973, 0.825069, 0.826237"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[30]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.104592, -0.046636, 0.057935, 0.076581, 0.303191",\ + "-0.191631, -0.133768, -0.028107, -0.009449, 0.217299",\ + "-0.284646, -0.226970, -0.119146, -0.100465, 0.126557",\ + "-0.438866, -0.381023, -0.270840, -0.251831, -0.020821",\ + "-0.692552, -0.634323, -0.519612, -0.499921, -0.260619"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.115174, -0.080527, -0.015220, 0.017546, 0.415745",\ + "-0.204335, -0.169799, -0.104194, -0.071353, 0.327762",\ + "-0.309715, -0.275599, -0.208862, -0.175734, 0.226866",\ + "-0.496251, -0.462141, -0.395611, -0.362029, 0.046093",\ + "-0.816650, -0.782151, -0.717215, -0.682795, -0.264493"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[30]_hldr*/ + +} /* end of pin alert_rsp_i[30] */ + +pin("alert_rsp_i[29]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000591 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[29]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.199726, 0.138633, 0.033463, 0.054461, 0.309637",\ + "0.287373, 0.226285, 0.121029, 0.142110, 0.398309",\ + "0.384684, 0.323610, 0.218105, 0.239430, 0.498591",\ + "0.560847, 0.499591, 0.393454, 0.414928, 0.675905",\ + "0.860633, 0.798634, 0.691077, 0.712170, 0.968509"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.214871, 0.178837, 0.123974, 0.124132, 0.126049",\ + "0.298634, 0.262602, 0.208037, 0.208173, 0.209823",\ + "0.403277, 0.367383, 0.313251, 0.313345, 0.314481",\ + "0.578488, 0.543087, 0.488416, 0.488511, 0.489666",\ + "0.868870, 0.834430, 0.778706, 0.778804, 0.779997"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[29]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.112157, -0.054218, 0.050557, 0.069205, 0.295841",\ + "-0.199804, -0.141906, -0.036659, -0.018006, 0.208689",\ + "-0.297115, -0.239335, -0.132721, -0.114053, 0.112815",\ + "-0.473050, -0.415309, -0.306338, -0.287512, -0.058720",\ + "-0.771971, -0.713924, -0.601352, -0.581984, -0.346599"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.126284, -0.091801, -0.026053, 0.006825, 0.406380",\ + "-0.209910, -0.175609, -0.109372, -0.076372, 0.324685",\ + "-0.312970, -0.278942, -0.212075, -0.178671, 0.227297",\ + "-0.483276, -0.448963, -0.383263, -0.349244, 0.064176",\ + "-0.764074, -0.729205, -0.665784, -0.630568, -0.202592"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[29]_hldr*/ + +} /* end of pin alert_rsp_i[29] */ + +pin("alert_rsp_i[28]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000589 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[28]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.192162, 0.131067, 0.025934, 0.046895, 0.301630",\ + "0.279200, 0.218116, 0.112785, 0.133940, 0.391038",\ + "0.372216, 0.311153, 0.205428, 0.226969, 0.488754",\ + "0.526955, 0.465449, 0.358834, 0.380180, 0.639596",\ + "0.781727, 0.719289, 0.610887, 0.631753, 0.885337"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.203639, 0.167601, 0.112469, 0.112646, 0.114806",\ + "0.292883, 0.256848, 0.201897, 0.202061, 0.204057",\ + "0.398578, 0.362549, 0.308291, 0.308405, 0.309779",\ + "0.587975, 0.552224, 0.497936, 0.498030, 0.499172",\ + "0.915076, 0.879998, 0.824973, 0.825069, 0.826237"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[28]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.104592, -0.046636, 0.057935, 0.076581, 0.303191",\ + "-0.191631, -0.133768, -0.028107, -0.009449, 0.217299",\ + "-0.284646, -0.226970, -0.119146, -0.100465, 0.126557",\ + "-0.438866, -0.381023, -0.270840, -0.251831, -0.020821",\ + "-0.692552, -0.634323, -0.519612, -0.499921, -0.260619"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.115174, -0.080527, -0.015220, 0.017546, 0.415745",\ + "-0.204335, -0.169799, -0.104194, -0.071353, 0.327762",\ + "-0.309715, -0.275599, -0.208862, -0.175734, 0.226866",\ + "-0.496251, -0.462141, -0.395611, -0.362029, 0.046093",\ + "-0.816650, -0.782151, -0.717215, -0.682795, -0.264493"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[28]_hldr*/ + +} /* end of pin alert_rsp_i[28] */ + +pin("alert_rsp_i[27]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000591 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[27]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.199726, 0.138633, 0.033463, 0.054461, 0.309637",\ + "0.287373, 0.226285, 0.121029, 0.142110, 0.398309",\ + "0.384684, 0.323610, 0.218105, 0.239430, 0.498591",\ + "0.560847, 0.499591, 0.393454, 0.414928, 0.675905",\ + "0.860633, 0.798634, 0.691077, 0.712170, 0.968509"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.214871, 0.178837, 0.123974, 0.124132, 0.126049",\ + "0.298634, 0.262602, 0.208037, 0.208173, 0.209823",\ + "0.403277, 0.367383, 0.313251, 0.313345, 0.314481",\ + "0.578488, 0.543087, 0.488416, 0.488511, 0.489666",\ + "0.868870, 0.834430, 0.778706, 0.778804, 0.779997"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[27]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.112157, -0.054218, 0.050557, 0.069205, 0.295841",\ + "-0.199804, -0.141906, -0.036659, -0.018006, 0.208689",\ + "-0.297115, -0.239335, -0.132721, -0.114053, 0.112815",\ + "-0.473050, -0.415309, -0.306338, -0.287512, -0.058720",\ + "-0.771971, -0.713924, -0.601352, -0.581984, -0.346599"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.126284, -0.091801, -0.026053, 0.006825, 0.406380",\ + "-0.209910, -0.175609, -0.109372, -0.076372, 0.324685",\ + "-0.312970, -0.278942, -0.212075, -0.178671, 0.227297",\ + "-0.483276, -0.448963, -0.383263, -0.349244, 0.064176",\ + "-0.764074, -0.729205, -0.665784, -0.630568, -0.202592"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[27]_hldr*/ + +} /* end of pin alert_rsp_i[27] */ + +pin("alert_rsp_i[26]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000589 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[26]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.192162, 0.131067, 0.025934, 0.046895, 0.301630",\ + "0.279200, 0.218116, 0.112785, 0.133940, 0.391038",\ + "0.372216, 0.311153, 0.205428, 0.226969, 0.488754",\ + "0.526955, 0.465449, 0.358834, 0.380180, 0.639596",\ + "0.781727, 0.719289, 0.610887, 0.631753, 0.885337"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.203639, 0.167601, 0.112469, 0.112646, 0.114806",\ + "0.292883, 0.256848, 0.201897, 0.202061, 0.204057",\ + "0.398578, 0.362549, 0.308291, 0.308405, 0.309779",\ + "0.587975, 0.552224, 0.497936, 0.498030, 0.499172",\ + "0.915076, 0.879998, 0.824973, 0.825069, 0.826237"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[26]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.104592, -0.046636, 0.057935, 0.076581, 0.303191",\ + "-0.191631, -0.133768, -0.028107, -0.009449, 0.217299",\ + "-0.284646, -0.226970, -0.119146, -0.100465, 0.126557",\ + "-0.438866, -0.381023, -0.270840, -0.251831, -0.020821",\ + "-0.692552, -0.634323, -0.519612, -0.499921, -0.260619"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.115174, -0.080527, -0.015220, 0.017546, 0.415745",\ + "-0.204335, -0.169799, -0.104194, -0.071353, 0.327762",\ + "-0.309715, -0.275599, -0.208862, -0.175734, 0.226866",\ + "-0.496251, -0.462141, -0.395611, -0.362029, 0.046093",\ + "-0.816650, -0.782151, -0.717215, -0.682795, -0.264493"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[26]_hldr*/ + +} /* end of pin alert_rsp_i[26] */ + +pin("alert_rsp_i[25]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000448 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[25]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.185938, 0.149895, 0.094200, 0.094419, 0.097084",\ + "0.272325, 0.236283, 0.180640, 0.180856, 0.183473",\ + "0.358907, 0.322867, 0.267423, 0.267624, 0.270063",\ + "0.517339, 0.481305, 0.426450, 0.426607, 0.428517",\ + "0.782742, 0.746824, 0.692719, 0.692812, 0.693947"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.247782, 0.186691, 0.081487, 0.102517, 0.358097",\ + "0.337069, 0.275978, 0.170775, 0.191805, 0.447385",\ + "0.437523, 0.376437, 0.271157, 0.292262, 0.548747",\ + "0.618326, 0.557252, 0.451732, 0.473072, 0.732422",\ + "0.922412, 0.861156, 0.755022, 0.776496, 1.037479"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[25]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.097073, -0.062070, 0.002277, 0.034799, 0.430045",\ + "-0.183156, -0.148183, -0.083758, -0.051216, 0.344267",\ + "-0.269694, -0.234839, -0.170093, -0.137470, 0.259003",\ + "-0.427321, -0.392813, -0.327135, -0.294275, 0.105065",\ + "-0.690363, -0.656367, -0.589370, -0.556034, -0.150898"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.143047, -0.085078, 0.019349, 0.037994, 0.264586",\ + "-0.232868, -0.174900, -0.070472, -0.051827, 0.174765",\ + "-0.335734, -0.277819, -0.172775, -0.154124, 0.072546",\ + "-0.517254, -0.459461, -0.352995, -0.334328, -0.107479",\ + "-0.818219, -0.760494, -0.651701, -0.632901, -0.404435"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[25]_hldr*/ + +} /* end of pin alert_rsp_i[25] */ + +pin("alert_rsp_i[24]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000500 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[24]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.220674, 0.184637, 0.129589, 0.129760, 0.131844",\ + "0.297060, 0.261023, 0.205975, 0.206146, 0.208230",\ + "0.368632, 0.332596, 0.277611, 0.277778, 0.279805",\ + "0.497931, 0.461898, 0.407219, 0.407363, 0.409115",\ + "0.712779, 0.676837, 0.622759, 0.622852, 0.623986"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.209550, 0.148448, 0.043450, 0.064279, 0.317417",\ + "0.301584, 0.240483, 0.135457, 0.156314, 0.409784",\ + "0.402135, 0.341040, 0.235908, 0.256868, 0.511598",\ + "0.580476, 0.519395, 0.414005, 0.435218, 0.693015",\ + "0.877762, 0.816594, 0.710628, 0.732149, 0.993683"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[24]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.105222, -0.070365, -0.005626, 0.026996, 0.423447",\ + "-0.183185, -0.148328, -0.083588, -0.050966, 0.345485",\ + "-0.257972, -0.223201, -0.158231, -0.125551, 0.271609",\ + "-0.390468, -0.355966, -0.290271, -0.257407, 0.141987",\ + "-0.603765, -0.569785, -0.502723, -0.469420, -0.064694"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.121294, -0.063271, 0.040519, 0.059158, 0.285669",\ + "-0.213390, -0.155380, -0.051441, -0.032801, 0.193729",\ + "-0.313842, -0.255881, -0.151371, -0.132725, 0.093876",\ + "-0.490960, -0.433113, -0.327285, -0.308625, -0.081856",\ + "-0.786249, -0.728564, -0.620239, -0.601510, -0.373902"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[24]_hldr*/ + +} /* end of pin alert_rsp_i[24] */ + +pin("alert_rsp_i[23]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000448 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[23]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.185938, 0.149895, 0.094200, 0.094419, 0.097084",\ + "0.272325, 0.236283, 0.180640, 0.180856, 0.183473",\ + "0.358907, 0.322867, 0.267423, 0.267624, 0.270063",\ + "0.517339, 0.481305, 0.426450, 0.426607, 0.428517",\ + "0.782742, 0.746824, 0.692719, 0.692812, 0.693947"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.247782, 0.186691, 0.081487, 0.102517, 0.358097",\ + "0.337069, 0.275978, 0.170775, 0.191805, 0.447385",\ + "0.437523, 0.376437, 0.271157, 0.292262, 0.548747",\ + "0.618326, 0.557252, 0.451732, 0.473072, 0.732422",\ + "0.922412, 0.861156, 0.755022, 0.776496, 1.037479"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[23]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.097073, -0.062070, 0.002277, 0.034799, 0.430045",\ + "-0.183156, -0.148183, -0.083758, -0.051216, 0.344267",\ + "-0.269694, -0.234839, -0.170093, -0.137470, 0.259003",\ + "-0.427321, -0.392813, -0.327135, -0.294275, 0.105065",\ + "-0.690363, -0.656367, -0.589370, -0.556034, -0.150898"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.143047, -0.085078, 0.019349, 0.037994, 0.264586",\ + "-0.232868, -0.174900, -0.070472, -0.051827, 0.174765",\ + "-0.335734, -0.277819, -0.172775, -0.154124, 0.072546",\ + "-0.517254, -0.459461, -0.352995, -0.334328, -0.107479",\ + "-0.818219, -0.760494, -0.651701, -0.632901, -0.404435"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[23]_hldr*/ + +} /* end of pin alert_rsp_i[23] */ + +pin("alert_rsp_i[22]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000500 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[22]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.220674, 0.184637, 0.129589, 0.129760, 0.131844",\ + "0.297060, 0.261023, 0.205975, 0.206146, 0.208230",\ + "0.368632, 0.332596, 0.277611, 0.277778, 0.279805",\ + "0.497931, 0.461898, 0.407219, 0.407363, 0.409115",\ + "0.712779, 0.676837, 0.622759, 0.622852, 0.623986"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.209550, 0.148448, 0.043450, 0.064279, 0.317417",\ + "0.301584, 0.240483, 0.135457, 0.156314, 0.409784",\ + "0.402135, 0.341040, 0.235908, 0.256868, 0.511598",\ + "0.580476, 0.519395, 0.414005, 0.435218, 0.693015",\ + "0.877762, 0.816594, 0.710628, 0.732149, 0.993683"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[22]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.105222, -0.070365, -0.005626, 0.026996, 0.423447",\ + "-0.183185, -0.148328, -0.083588, -0.050966, 0.345485",\ + "-0.257972, -0.223201, -0.158231, -0.125551, 0.271609",\ + "-0.390468, -0.355966, -0.290271, -0.257407, 0.141987",\ + "-0.603765, -0.569785, -0.502723, -0.469420, -0.064694"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.121294, -0.063271, 0.040519, 0.059158, 0.285669",\ + "-0.213390, -0.155380, -0.051441, -0.032801, 0.193729",\ + "-0.313842, -0.255881, -0.151371, -0.132725, 0.093876",\ + "-0.490960, -0.433113, -0.327285, -0.308625, -0.081856",\ + "-0.786249, -0.728564, -0.620239, -0.601510, -0.373902"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[22]_hldr*/ + +} /* end of pin alert_rsp_i[22] */ + +pin("alert_rsp_i[21]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000448 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[21]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.185938, 0.149895, 0.094200, 0.094419, 0.097084",\ + "0.272325, 0.236283, 0.180640, 0.180856, 0.183473",\ + "0.358907, 0.322867, 0.267423, 0.267624, 0.270063",\ + "0.517339, 0.481305, 0.426450, 0.426607, 0.428517",\ + "0.782742, 0.746824, 0.692719, 0.692812, 0.693947"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.247782, 0.186691, 0.081487, 0.102517, 0.358097",\ + "0.337069, 0.275978, 0.170775, 0.191805, 0.447385",\ + "0.437523, 0.376437, 0.271157, 0.292262, 0.548747",\ + "0.618326, 0.557252, 0.451732, 0.473072, 0.732422",\ + "0.922412, 0.861156, 0.755022, 0.776496, 1.037479"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[21]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.097073, -0.062070, 0.002277, 0.034799, 0.430045",\ + "-0.183156, -0.148183, -0.083758, -0.051216, 0.344267",\ + "-0.269694, -0.234839, -0.170093, -0.137470, 0.259003",\ + "-0.427321, -0.392813, -0.327135, -0.294275, 0.105065",\ + "-0.690363, -0.656367, -0.589370, -0.556034, -0.150898"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.143047, -0.085078, 0.019349, 0.037994, 0.264586",\ + "-0.232868, -0.174900, -0.070472, -0.051827, 0.174765",\ + "-0.335734, -0.277819, -0.172775, -0.154124, 0.072546",\ + "-0.517254, -0.459461, -0.352995, -0.334328, -0.107479",\ + "-0.818219, -0.760494, -0.651701, -0.632901, -0.404435"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[21]_hldr*/ + +} /* end of pin alert_rsp_i[21] */ + +pin("alert_rsp_i[20]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000500 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[20]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.220674, 0.184637, 0.129589, 0.129760, 0.131844",\ + "0.297060, 0.261023, 0.205975, 0.206146, 0.208230",\ + "0.368632, 0.332596, 0.277611, 0.277778, 0.279805",\ + "0.497931, 0.461898, 0.407219, 0.407363, 0.409115",\ + "0.712779, 0.676837, 0.622759, 0.622852, 0.623986"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.209550, 0.148448, 0.043450, 0.064279, 0.317417",\ + "0.301584, 0.240483, 0.135457, 0.156314, 0.409784",\ + "0.402135, 0.341040, 0.235908, 0.256868, 0.511598",\ + "0.580476, 0.519395, 0.414005, 0.435218, 0.693015",\ + "0.877762, 0.816594, 0.710628, 0.732149, 0.993683"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[20]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.105222, -0.070365, -0.005626, 0.026996, 0.423447",\ + "-0.183185, -0.148328, -0.083588, -0.050966, 0.345485",\ + "-0.257972, -0.223201, -0.158231, -0.125551, 0.271609",\ + "-0.390468, -0.355966, -0.290271, -0.257407, 0.141987",\ + "-0.603765, -0.569785, -0.502723, -0.469420, -0.064694"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.121294, -0.063271, 0.040519, 0.059158, 0.285669",\ + "-0.213390, -0.155380, -0.051441, -0.032801, 0.193729",\ + "-0.313842, -0.255881, -0.151371, -0.132725, 0.093876",\ + "-0.490960, -0.433113, -0.327285, -0.308625, -0.081856",\ + "-0.786249, -0.728564, -0.620239, -0.601510, -0.373902"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[20]_hldr*/ + +} /* end of pin alert_rsp_i[20] */ + +pin("alert_rsp_i[19]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000448 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[19]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.185938, 0.149895, 0.094200, 0.094419, 0.097084",\ + "0.272325, 0.236283, 0.180640, 0.180856, 0.183473",\ + "0.358907, 0.322867, 0.267423, 0.267624, 0.270063",\ + "0.517339, 0.481305, 0.426450, 0.426607, 0.428517",\ + "0.782742, 0.746824, 0.692719, 0.692812, 0.693947"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.247782, 0.186691, 0.081487, 0.102517, 0.358097",\ + "0.337069, 0.275978, 0.170775, 0.191805, 0.447385",\ + "0.437523, 0.376437, 0.271157, 0.292262, 0.548747",\ + "0.618326, 0.557252, 0.451732, 0.473072, 0.732422",\ + "0.922412, 0.861156, 0.755022, 0.776496, 1.037479"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[19]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.097073, -0.062070, 0.002277, 0.034799, 0.430045",\ + "-0.183156, -0.148183, -0.083758, -0.051216, 0.344267",\ + "-0.269694, -0.234839, -0.170093, -0.137470, 0.259003",\ + "-0.427321, -0.392813, -0.327135, -0.294275, 0.105065",\ + "-0.690363, -0.656367, -0.589370, -0.556034, -0.150898"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.143047, -0.085078, 0.019349, 0.037994, 0.264586",\ + "-0.232868, -0.174900, -0.070472, -0.051827, 0.174765",\ + "-0.335734, -0.277819, -0.172775, -0.154124, 0.072546",\ + "-0.517254, -0.459461, -0.352995, -0.334328, -0.107479",\ + "-0.818219, -0.760494, -0.651701, -0.632901, -0.404435"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[19]_hldr*/ + +} /* end of pin alert_rsp_i[19] */ + +pin("alert_rsp_i[18]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000500 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[18]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.220674, 0.184637, 0.129589, 0.129760, 0.131844",\ + "0.297060, 0.261023, 0.205975, 0.206146, 0.208230",\ + "0.368632, 0.332596, 0.277611, 0.277778, 0.279805",\ + "0.497931, 0.461898, 0.407219, 0.407363, 0.409115",\ + "0.712779, 0.676837, 0.622759, 0.622852, 0.623986"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.209550, 0.148448, 0.043450, 0.064279, 0.317417",\ + "0.301584, 0.240483, 0.135457, 0.156314, 0.409784",\ + "0.402135, 0.341040, 0.235908, 0.256868, 0.511598",\ + "0.580476, 0.519395, 0.414005, 0.435218, 0.693015",\ + "0.877762, 0.816594, 0.710628, 0.732149, 0.993683"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[18]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.105222, -0.070365, -0.005626, 0.026996, 0.423447",\ + "-0.183185, -0.148328, -0.083588, -0.050966, 0.345485",\ + "-0.257972, -0.223201, -0.158231, -0.125551, 0.271609",\ + "-0.390468, -0.355966, -0.290271, -0.257407, 0.141987",\ + "-0.603765, -0.569785, -0.502723, -0.469420, -0.064694"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.121294, -0.063271, 0.040519, 0.059158, 0.285669",\ + "-0.213390, -0.155380, -0.051441, -0.032801, 0.193729",\ + "-0.313842, -0.255881, -0.151371, -0.132725, 0.093876",\ + "-0.490960, -0.433113, -0.327285, -0.308625, -0.081856",\ + "-0.786249, -0.728564, -0.620239, -0.601510, -0.373902"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[18]_hldr*/ + +} /* end of pin alert_rsp_i[18] */ + +pin("alert_rsp_i[17]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000448 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[17]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.185938, 0.149895, 0.094200, 0.094419, 0.097084",\ + "0.272325, 0.236283, 0.180640, 0.180856, 0.183473",\ + "0.358907, 0.322867, 0.267423, 0.267624, 0.270063",\ + "0.517339, 0.481305, 0.426450, 0.426607, 0.428517",\ + "0.782742, 0.746824, 0.692719, 0.692812, 0.693947"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.247782, 0.186691, 0.081487, 0.102517, 0.358097",\ + "0.337069, 0.275978, 0.170775, 0.191805, 0.447385",\ + "0.437523, 0.376437, 0.271157, 0.292262, 0.548747",\ + "0.618326, 0.557252, 0.451732, 0.473072, 0.732422",\ + "0.922412, 0.861156, 0.755022, 0.776496, 1.037479"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[17]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.097073, -0.062070, 0.002277, 0.034799, 0.430045",\ + "-0.183156, -0.148183, -0.083758, -0.051216, 0.344267",\ + "-0.269694, -0.234839, -0.170093, -0.137470, 0.259003",\ + "-0.427321, -0.392813, -0.327135, -0.294275, 0.105065",\ + "-0.690363, -0.656367, -0.589370, -0.556034, -0.150898"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.143047, -0.085078, 0.019349, 0.037994, 0.264586",\ + "-0.232868, -0.174900, -0.070472, -0.051827, 0.174765",\ + "-0.335734, -0.277819, -0.172775, -0.154124, 0.072546",\ + "-0.517254, -0.459461, -0.352995, -0.334328, -0.107479",\ + "-0.818219, -0.760494, -0.651701, -0.632901, -0.404435"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[17]_hldr*/ + +} /* end of pin alert_rsp_i[17] */ + +pin("alert_rsp_i[16]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000500 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[16]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.220674, 0.184637, 0.129589, 0.129760, 0.131844",\ + "0.297060, 0.261023, 0.205975, 0.206146, 0.208230",\ + "0.368632, 0.332596, 0.277611, 0.277778, 0.279805",\ + "0.497931, 0.461898, 0.407219, 0.407363, 0.409115",\ + "0.712779, 0.676837, 0.622759, 0.622852, 0.623986"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.209550, 0.148448, 0.043450, 0.064279, 0.317417",\ + "0.301584, 0.240483, 0.135457, 0.156314, 0.409784",\ + "0.402135, 0.341040, 0.235908, 0.256868, 0.511598",\ + "0.580476, 0.519395, 0.414005, 0.435218, 0.693015",\ + "0.877762, 0.816594, 0.710628, 0.732149, 0.993683"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[16]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.105222, -0.070365, -0.005626, 0.026996, 0.423447",\ + "-0.183185, -0.148328, -0.083588, -0.050966, 0.345485",\ + "-0.257972, -0.223201, -0.158231, -0.125551, 0.271609",\ + "-0.390468, -0.355966, -0.290271, -0.257407, 0.141987",\ + "-0.603765, -0.569785, -0.502723, -0.469420, -0.064694"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.121294, -0.063271, 0.040519, 0.059158, 0.285669",\ + "-0.213390, -0.155380, -0.051441, -0.032801, 0.193729",\ + "-0.313842, -0.255881, -0.151371, -0.132725, 0.093876",\ + "-0.490960, -0.433113, -0.327285, -0.308625, -0.081856",\ + "-0.786249, -0.728564, -0.620239, -0.601510, -0.373902"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[16]_hldr*/ + +} /* end of pin alert_rsp_i[16] */ + +pin("alert_rsp_i[15]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000448 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[15]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.185938, 0.149895, 0.094200, 0.094419, 0.097084",\ + "0.272325, 0.236283, 0.180640, 0.180856, 0.183473",\ + "0.358907, 0.322867, 0.267423, 0.267624, 0.270063",\ + "0.517339, 0.481305, 0.426450, 0.426607, 0.428517",\ + "0.782742, 0.746824, 0.692719, 0.692812, 0.693947"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.247782, 0.186691, 0.081487, 0.102517, 0.358097",\ + "0.337069, 0.275978, 0.170775, 0.191805, 0.447385",\ + "0.437523, 0.376437, 0.271157, 0.292262, 0.548747",\ + "0.618326, 0.557252, 0.451732, 0.473072, 0.732422",\ + "0.922412, 0.861156, 0.755022, 0.776496, 1.037479"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[15]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.097073, -0.062070, 0.002277, 0.034799, 0.430045",\ + "-0.183156, -0.148183, -0.083758, -0.051216, 0.344267",\ + "-0.269694, -0.234839, -0.170093, -0.137470, 0.259003",\ + "-0.427321, -0.392813, -0.327135, -0.294275, 0.105065",\ + "-0.690363, -0.656367, -0.589370, -0.556034, -0.150898"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.143047, -0.085078, 0.019349, 0.037994, 0.264586",\ + "-0.232868, -0.174900, -0.070472, -0.051827, 0.174765",\ + "-0.335734, -0.277819, -0.172775, -0.154124, 0.072546",\ + "-0.517254, -0.459461, -0.352995, -0.334328, -0.107479",\ + "-0.818219, -0.760494, -0.651701, -0.632901, -0.404435"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[15]_hldr*/ + +} /* end of pin alert_rsp_i[15] */ + +pin("alert_rsp_i[14]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000500 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[14]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.220674, 0.184637, 0.129589, 0.129760, 0.131844",\ + "0.297060, 0.261023, 0.205975, 0.206146, 0.208230",\ + "0.368632, 0.332596, 0.277611, 0.277778, 0.279805",\ + "0.497931, 0.461898, 0.407219, 0.407363, 0.409115",\ + "0.712779, 0.676837, 0.622759, 0.622852, 0.623986"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.209550, 0.148448, 0.043450, 0.064279, 0.317417",\ + "0.301584, 0.240483, 0.135457, 0.156314, 0.409784",\ + "0.402135, 0.341040, 0.235908, 0.256868, 0.511598",\ + "0.580476, 0.519395, 0.414005, 0.435218, 0.693015",\ + "0.877762, 0.816594, 0.710628, 0.732149, 0.993683"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[14]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.105222, -0.070365, -0.005626, 0.026996, 0.423447",\ + "-0.183185, -0.148328, -0.083588, -0.050966, 0.345485",\ + "-0.257972, -0.223201, -0.158231, -0.125551, 0.271609",\ + "-0.390468, -0.355966, -0.290271, -0.257407, 0.141987",\ + "-0.603765, -0.569785, -0.502723, -0.469420, -0.064694"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.121294, -0.063271, 0.040519, 0.059158, 0.285669",\ + "-0.213390, -0.155380, -0.051441, -0.032801, 0.193729",\ + "-0.313842, -0.255881, -0.151371, -0.132725, 0.093876",\ + "-0.490960, -0.433113, -0.327285, -0.308625, -0.081856",\ + "-0.786249, -0.728564, -0.620239, -0.601510, -0.373902"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[14]_hldr*/ + +} /* end of pin alert_rsp_i[14] */ + +pin("alert_rsp_i[13]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000448 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[13]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.185938, 0.149895, 0.094200, 0.094419, 0.097084",\ + "0.272325, 0.236283, 0.180640, 0.180856, 0.183473",\ + "0.358907, 0.322867, 0.267423, 0.267624, 0.270063",\ + "0.517339, 0.481305, 0.426450, 0.426607, 0.428517",\ + "0.782742, 0.746824, 0.692719, 0.692812, 0.693947"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.247782, 0.186691, 0.081487, 0.102517, 0.358097",\ + "0.337069, 0.275978, 0.170775, 0.191805, 0.447385",\ + "0.437523, 0.376437, 0.271157, 0.292262, 0.548747",\ + "0.618326, 0.557252, 0.451732, 0.473072, 0.732422",\ + "0.922412, 0.861156, 0.755022, 0.776496, 1.037479"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[13]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.097073, -0.062070, 0.002277, 0.034799, 0.430045",\ + "-0.183156, -0.148183, -0.083758, -0.051216, 0.344267",\ + "-0.269694, -0.234839, -0.170093, -0.137470, 0.259003",\ + "-0.427321, -0.392813, -0.327135, -0.294275, 0.105065",\ + "-0.690363, -0.656367, -0.589370, -0.556034, -0.150898"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.143047, -0.085078, 0.019349, 0.037994, 0.264586",\ + "-0.232868, -0.174900, -0.070472, -0.051827, 0.174765",\ + "-0.335734, -0.277819, -0.172775, -0.154124, 0.072546",\ + "-0.517254, -0.459461, -0.352995, -0.334328, -0.107479",\ + "-0.818219, -0.760494, -0.651701, -0.632901, -0.404435"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[13]_hldr*/ + +} /* end of pin alert_rsp_i[13] */ + +pin("alert_rsp_i[12]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000500 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[12]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.220674, 0.184637, 0.129589, 0.129760, 0.131844",\ + "0.297060, 0.261023, 0.205975, 0.206146, 0.208230",\ + "0.368632, 0.332596, 0.277611, 0.277778, 0.279805",\ + "0.497931, 0.461898, 0.407219, 0.407363, 0.409115",\ + "0.712779, 0.676837, 0.622759, 0.622852, 0.623986"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.209550, 0.148448, 0.043450, 0.064279, 0.317417",\ + "0.301584, 0.240483, 0.135457, 0.156314, 0.409784",\ + "0.402135, 0.341040, 0.235908, 0.256868, 0.511598",\ + "0.580476, 0.519395, 0.414005, 0.435218, 0.693015",\ + "0.877762, 0.816594, 0.710628, 0.732149, 0.993683"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[12]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.105222, -0.070365, -0.005626, 0.026996, 0.423447",\ + "-0.183185, -0.148328, -0.083588, -0.050966, 0.345485",\ + "-0.257972, -0.223201, -0.158231, -0.125551, 0.271609",\ + "-0.390468, -0.355966, -0.290271, -0.257407, 0.141987",\ + "-0.603765, -0.569785, -0.502723, -0.469420, -0.064694"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.121294, -0.063271, 0.040519, 0.059158, 0.285669",\ + "-0.213390, -0.155380, -0.051441, -0.032801, 0.193729",\ + "-0.313842, -0.255881, -0.151371, -0.132725, 0.093876",\ + "-0.490960, -0.433113, -0.327285, -0.308625, -0.081856",\ + "-0.786249, -0.728564, -0.620239, -0.601510, -0.373902"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[12]_hldr*/ + +} /* end of pin alert_rsp_i[12] */ + +pin("alert_rsp_i[11]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000448 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[11]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.185938, 0.149895, 0.094200, 0.094419, 0.097084",\ + "0.272325, 0.236283, 0.180640, 0.180856, 0.183473",\ + "0.358907, 0.322867, 0.267423, 0.267624, 0.270063",\ + "0.517339, 0.481305, 0.426450, 0.426607, 0.428517",\ + "0.782742, 0.746824, 0.692719, 0.692812, 0.693947"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.247782, 0.186691, 0.081487, 0.102517, 0.358097",\ + "0.337069, 0.275978, 0.170775, 0.191805, 0.447385",\ + "0.437523, 0.376437, 0.271157, 0.292262, 0.548747",\ + "0.618326, 0.557252, 0.451732, 0.473072, 0.732422",\ + "0.922412, 0.861156, 0.755022, 0.776496, 1.037479"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[11]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.097073, -0.062070, 0.002277, 0.034799, 0.430045",\ + "-0.183156, -0.148183, -0.083758, -0.051216, 0.344267",\ + "-0.269694, -0.234839, -0.170093, -0.137470, 0.259003",\ + "-0.427321, -0.392813, -0.327135, -0.294275, 0.105065",\ + "-0.690363, -0.656367, -0.589370, -0.556034, -0.150898"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.143047, -0.085078, 0.019349, 0.037994, 0.264586",\ + "-0.232868, -0.174900, -0.070472, -0.051827, 0.174765",\ + "-0.335734, -0.277819, -0.172775, -0.154124, 0.072546",\ + "-0.517254, -0.459461, -0.352995, -0.334328, -0.107479",\ + "-0.818219, -0.760494, -0.651701, -0.632901, -0.404435"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[11]_hldr*/ + +} /* end of pin alert_rsp_i[11] */ + +pin("alert_rsp_i[10]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000500 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[10]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.220674, 0.184637, 0.129589, 0.129760, 0.131844",\ + "0.297060, 0.261023, 0.205975, 0.206146, 0.208230",\ + "0.368632, 0.332596, 0.277611, 0.277778, 0.279805",\ + "0.497931, 0.461898, 0.407219, 0.407363, 0.409115",\ + "0.712779, 0.676837, 0.622759, 0.622852, 0.623986"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.209550, 0.148448, 0.043450, 0.064279, 0.317417",\ + "0.301584, 0.240483, 0.135457, 0.156314, 0.409784",\ + "0.402135, 0.341040, 0.235908, 0.256868, 0.511598",\ + "0.580476, 0.519395, 0.414005, 0.435218, 0.693015",\ + "0.877762, 0.816594, 0.710628, 0.732149, 0.993683"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[10]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.105222, -0.070365, -0.005626, 0.026996, 0.423447",\ + "-0.183185, -0.148328, -0.083588, -0.050966, 0.345485",\ + "-0.257972, -0.223201, -0.158231, -0.125551, 0.271609",\ + "-0.390468, -0.355966, -0.290271, -0.257407, 0.141987",\ + "-0.603765, -0.569785, -0.502723, -0.469420, -0.064694"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.121294, -0.063271, 0.040519, 0.059158, 0.285669",\ + "-0.213390, -0.155380, -0.051441, -0.032801, 0.193729",\ + "-0.313842, -0.255881, -0.151371, -0.132725, 0.093876",\ + "-0.490960, -0.433113, -0.327285, -0.308625, -0.081856",\ + "-0.786249, -0.728564, -0.620239, -0.601510, -0.373902"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[10]_hldr*/ + +} /* end of pin alert_rsp_i[10] */ + +pin("alert_rsp_i[9]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000448 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[9]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.185938, 0.149895, 0.094200, 0.094419, 0.097084",\ + "0.272325, 0.236283, 0.180640, 0.180856, 0.183473",\ + "0.358907, 0.322867, 0.267423, 0.267624, 0.270063",\ + "0.517339, 0.481305, 0.426450, 0.426607, 0.428517",\ + "0.782742, 0.746824, 0.692719, 0.692812, 0.693947"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.247782, 0.186691, 0.081487, 0.102517, 0.358097",\ + "0.337069, 0.275978, 0.170775, 0.191805, 0.447385",\ + "0.437523, 0.376437, 0.271157, 0.292262, 0.548747",\ + "0.618326, 0.557252, 0.451732, 0.473072, 0.732422",\ + "0.922412, 0.861156, 0.755022, 0.776496, 1.037479"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[9]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.097073, -0.062070, 0.002277, 0.034799, 0.430045",\ + "-0.183156, -0.148183, -0.083758, -0.051216, 0.344267",\ + "-0.269694, -0.234839, -0.170093, -0.137470, 0.259003",\ + "-0.427321, -0.392813, -0.327135, -0.294275, 0.105065",\ + "-0.690363, -0.656367, -0.589370, -0.556034, -0.150898"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.143047, -0.085078, 0.019349, 0.037994, 0.264586",\ + "-0.232868, -0.174900, -0.070472, -0.051827, 0.174765",\ + "-0.335734, -0.277819, -0.172775, -0.154124, 0.072546",\ + "-0.517254, -0.459461, -0.352995, -0.334328, -0.107479",\ + "-0.818219, -0.760494, -0.651701, -0.632901, -0.404435"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[9]_hldr*/ + +} /* end of pin alert_rsp_i[9] */ + +pin("alert_rsp_i[8]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000500 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[8]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.220674, 0.184637, 0.129589, 0.129760, 0.131844",\ + "0.297060, 0.261023, 0.205975, 0.206146, 0.208230",\ + "0.368632, 0.332596, 0.277611, 0.277778, 0.279805",\ + "0.497931, 0.461898, 0.407219, 0.407363, 0.409115",\ + "0.712779, 0.676837, 0.622759, 0.622852, 0.623986"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.209550, 0.148448, 0.043450, 0.064279, 0.317417",\ + "0.301584, 0.240483, 0.135457, 0.156314, 0.409784",\ + "0.402135, 0.341040, 0.235908, 0.256868, 0.511598",\ + "0.580476, 0.519395, 0.414005, 0.435218, 0.693015",\ + "0.877762, 0.816594, 0.710628, 0.732149, 0.993683"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[8]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.105222, -0.070365, -0.005626, 0.026996, 0.423447",\ + "-0.183185, -0.148328, -0.083588, -0.050966, 0.345485",\ + "-0.257972, -0.223201, -0.158231, -0.125551, 0.271609",\ + "-0.390468, -0.355966, -0.290271, -0.257407, 0.141987",\ + "-0.603765, -0.569785, -0.502723, -0.469420, -0.064694"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.121294, -0.063271, 0.040519, 0.059158, 0.285669",\ + "-0.213390, -0.155380, -0.051441, -0.032801, 0.193729",\ + "-0.313842, -0.255881, -0.151371, -0.132725, 0.093876",\ + "-0.490960, -0.433113, -0.327285, -0.308625, -0.081856",\ + "-0.786249, -0.728564, -0.620239, -0.601510, -0.373902"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[8]_hldr*/ + +} /* end of pin alert_rsp_i[8] */ + +pin("alert_rsp_i[7]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000448 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[7]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.185938, 0.149895, 0.094200, 0.094419, 0.097084",\ + "0.272325, 0.236283, 0.180640, 0.180856, 0.183473",\ + "0.358907, 0.322867, 0.267423, 0.267624, 0.270063",\ + "0.517339, 0.481305, 0.426450, 0.426607, 0.428517",\ + "0.782742, 0.746824, 0.692719, 0.692812, 0.693947"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.247782, 0.186691, 0.081487, 0.102517, 0.358097",\ + "0.337069, 0.275978, 0.170775, 0.191805, 0.447385",\ + "0.437523, 0.376437, 0.271157, 0.292262, 0.548747",\ + "0.618326, 0.557252, 0.451732, 0.473072, 0.732422",\ + "0.922412, 0.861156, 0.755022, 0.776496, 1.037479"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[7]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.097073, -0.062070, 0.002277, 0.034799, 0.430045",\ + "-0.183156, -0.148183, -0.083758, -0.051216, 0.344267",\ + "-0.269694, -0.234839, -0.170093, -0.137470, 0.259003",\ + "-0.427321, -0.392813, -0.327135, -0.294275, 0.105065",\ + "-0.690363, -0.656367, -0.589370, -0.556034, -0.150898"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.143047, -0.085078, 0.019349, 0.037994, 0.264586",\ + "-0.232868, -0.174900, -0.070472, -0.051827, 0.174765",\ + "-0.335734, -0.277819, -0.172775, -0.154124, 0.072546",\ + "-0.517254, -0.459461, -0.352995, -0.334328, -0.107479",\ + "-0.818219, -0.760494, -0.651701, -0.632901, -0.404435"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[7]_hldr*/ + +} /* end of pin alert_rsp_i[7] */ + +pin("alert_rsp_i[6]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000500 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[6]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.220674, 0.184637, 0.129589, 0.129760, 0.131844",\ + "0.297060, 0.261023, 0.205975, 0.206146, 0.208230",\ + "0.368632, 0.332596, 0.277611, 0.277778, 0.279805",\ + "0.497931, 0.461898, 0.407219, 0.407363, 0.409115",\ + "0.712779, 0.676837, 0.622759, 0.622852, 0.623986"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.209550, 0.148448, 0.043450, 0.064279, 0.317417",\ + "0.301584, 0.240483, 0.135457, 0.156314, 0.409784",\ + "0.402135, 0.341040, 0.235908, 0.256868, 0.511598",\ + "0.580476, 0.519395, 0.414005, 0.435218, 0.693015",\ + "0.877762, 0.816594, 0.710628, 0.732149, 0.993683"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[6]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.105222, -0.070365, -0.005626, 0.026996, 0.423447",\ + "-0.183185, -0.148328, -0.083588, -0.050966, 0.345485",\ + "-0.257972, -0.223201, -0.158231, -0.125551, 0.271609",\ + "-0.390468, -0.355966, -0.290271, -0.257407, 0.141987",\ + "-0.603765, -0.569785, -0.502723, -0.469420, -0.064694"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.121294, -0.063271, 0.040519, 0.059158, 0.285669",\ + "-0.213390, -0.155380, -0.051441, -0.032801, 0.193729",\ + "-0.313842, -0.255881, -0.151371, -0.132725, 0.093876",\ + "-0.490960, -0.433113, -0.327285, -0.308625, -0.081856",\ + "-0.786249, -0.728564, -0.620239, -0.601510, -0.373902"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[6]_hldr*/ + +} /* end of pin alert_rsp_i[6] */ + +pin("alert_rsp_i[5]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000448 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[5]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.185938, 0.149895, 0.094200, 0.094419, 0.097084",\ + "0.272325, 0.236283, 0.180640, 0.180856, 0.183473",\ + "0.358907, 0.322867, 0.267423, 0.267624, 0.270063",\ + "0.517339, 0.481305, 0.426450, 0.426607, 0.428517",\ + "0.782742, 0.746824, 0.692719, 0.692812, 0.693947"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.247782, 0.186691, 0.081487, 0.102517, 0.358097",\ + "0.337069, 0.275978, 0.170775, 0.191805, 0.447385",\ + "0.437523, 0.376437, 0.271157, 0.292262, 0.548747",\ + "0.618326, 0.557252, 0.451732, 0.473072, 0.732422",\ + "0.922412, 0.861156, 0.755022, 0.776496, 1.037479"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[5]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.097073, -0.062070, 0.002277, 0.034799, 0.430045",\ + "-0.183156, -0.148183, -0.083758, -0.051216, 0.344267",\ + "-0.269694, -0.234839, -0.170093, -0.137470, 0.259003",\ + "-0.427321, -0.392813, -0.327135, -0.294275, 0.105065",\ + "-0.690363, -0.656367, -0.589370, -0.556034, -0.150898"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.143047, -0.085078, 0.019349, 0.037994, 0.264586",\ + "-0.232868, -0.174900, -0.070472, -0.051827, 0.174765",\ + "-0.335734, -0.277819, -0.172775, -0.154124, 0.072546",\ + "-0.517254, -0.459461, -0.352995, -0.334328, -0.107479",\ + "-0.818219, -0.760494, -0.651701, -0.632901, -0.404435"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[5]_hldr*/ + +} /* end of pin alert_rsp_i[5] */ + +pin("alert_rsp_i[4]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000500 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[4]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.220674, 0.184637, 0.129589, 0.129760, 0.131844",\ + "0.297060, 0.261023, 0.205975, 0.206146, 0.208230",\ + "0.368632, 0.332596, 0.277611, 0.277778, 0.279805",\ + "0.497931, 0.461898, 0.407219, 0.407363, 0.409115",\ + "0.712779, 0.676837, 0.622759, 0.622852, 0.623986"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.209550, 0.148448, 0.043450, 0.064279, 0.317417",\ + "0.301584, 0.240483, 0.135457, 0.156314, 0.409784",\ + "0.402135, 0.341040, 0.235908, 0.256868, 0.511598",\ + "0.580476, 0.519395, 0.414005, 0.435218, 0.693015",\ + "0.877762, 0.816594, 0.710628, 0.732149, 0.993683"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[4]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.105222, -0.070365, -0.005626, 0.026996, 0.423447",\ + "-0.183185, -0.148328, -0.083588, -0.050966, 0.345485",\ + "-0.257972, -0.223201, -0.158231, -0.125551, 0.271609",\ + "-0.390468, -0.355966, -0.290271, -0.257407, 0.141987",\ + "-0.603765, -0.569785, -0.502723, -0.469420, -0.064694"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.121294, -0.063271, 0.040519, 0.059158, 0.285669",\ + "-0.213390, -0.155380, -0.051441, -0.032801, 0.193729",\ + "-0.313842, -0.255881, -0.151371, -0.132725, 0.093876",\ + "-0.490960, -0.433113, -0.327285, -0.308625, -0.081856",\ + "-0.786249, -0.728564, -0.620239, -0.601510, -0.373902"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[4]_hldr*/ + +} /* end of pin alert_rsp_i[4] */ + +pin("alert_rsp_i[3]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000448 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[3]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.185938, 0.149895, 0.094200, 0.094419, 0.097084",\ + "0.272325, 0.236283, 0.180640, 0.180856, 0.183473",\ + "0.358907, 0.322867, 0.267423, 0.267624, 0.270063",\ + "0.517339, 0.481305, 0.426450, 0.426607, 0.428517",\ + "0.782742, 0.746824, 0.692719, 0.692812, 0.693947"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.247782, 0.186691, 0.081487, 0.102517, 0.358097",\ + "0.337069, 0.275978, 0.170775, 0.191805, 0.447385",\ + "0.437523, 0.376437, 0.271157, 0.292262, 0.548747",\ + "0.618326, 0.557252, 0.451732, 0.473072, 0.732422",\ + "0.922412, 0.861156, 0.755022, 0.776496, 1.037479"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[3]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.097073, -0.062070, 0.002277, 0.034799, 0.430045",\ + "-0.183156, -0.148183, -0.083758, -0.051216, 0.344267",\ + "-0.269694, -0.234839, -0.170093, -0.137470, 0.259003",\ + "-0.427321, -0.392813, -0.327135, -0.294275, 0.105065",\ + "-0.690363, -0.656367, -0.589370, -0.556034, -0.150898"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.143047, -0.085078, 0.019349, 0.037994, 0.264586",\ + "-0.232868, -0.174900, -0.070472, -0.051827, 0.174765",\ + "-0.335734, -0.277819, -0.172775, -0.154124, 0.072546",\ + "-0.517254, -0.459461, -0.352995, -0.334328, -0.107479",\ + "-0.818219, -0.760494, -0.651701, -0.632901, -0.404435"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[3]_hldr*/ + +} /* end of pin alert_rsp_i[3] */ + +pin("alert_rsp_i[2]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000500 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[2]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.220674, 0.184637, 0.129589, 0.129760, 0.131844",\ + "0.297060, 0.261023, 0.205975, 0.206146, 0.208230",\ + "0.368632, 0.332596, 0.277611, 0.277778, 0.279805",\ + "0.497931, 0.461898, 0.407219, 0.407363, 0.409115",\ + "0.712779, 0.676837, 0.622759, 0.622852, 0.623986"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.209550, 0.148448, 0.043450, 0.064279, 0.317417",\ + "0.301584, 0.240483, 0.135457, 0.156314, 0.409784",\ + "0.402135, 0.341040, 0.235908, 0.256868, 0.511598",\ + "0.580476, 0.519395, 0.414005, 0.435218, 0.693015",\ + "0.877762, 0.816594, 0.710628, 0.732149, 0.993683"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[2]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.105222, -0.070365, -0.005626, 0.026996, 0.423447",\ + "-0.183185, -0.148328, -0.083588, -0.050966, 0.345485",\ + "-0.257972, -0.223201, -0.158231, -0.125551, 0.271609",\ + "-0.390468, -0.355966, -0.290271, -0.257407, 0.141987",\ + "-0.603765, -0.569785, -0.502723, -0.469420, -0.064694"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.121294, -0.063271, 0.040519, 0.059158, 0.285669",\ + "-0.213390, -0.155380, -0.051441, -0.032801, 0.193729",\ + "-0.313842, -0.255881, -0.151371, -0.132725, 0.093876",\ + "-0.490960, -0.433113, -0.327285, -0.308625, -0.081856",\ + "-0.786249, -0.728564, -0.620239, -0.601510, -0.373902"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[2]_hldr*/ + +} /* end of pin alert_rsp_i[2] */ + +pin("alert_rsp_i[1]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000448 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[1]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.185938, 0.149895, 0.094200, 0.094419, 0.097084",\ + "0.272325, 0.236283, 0.180640, 0.180856, 0.183473",\ + "0.358907, 0.322867, 0.267423, 0.267624, 0.270063",\ + "0.517339, 0.481305, 0.426450, 0.426607, 0.428517",\ + "0.782742, 0.746824, 0.692719, 0.692812, 0.693947"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.247782, 0.186691, 0.081487, 0.102517, 0.358097",\ + "0.337069, 0.275978, 0.170775, 0.191805, 0.447385",\ + "0.437523, 0.376437, 0.271157, 0.292262, 0.548747",\ + "0.618326, 0.557252, 0.451732, 0.473072, 0.732422",\ + "0.922412, 0.861156, 0.755022, 0.776496, 1.037479"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[1]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.097073, -0.062070, 0.002277, 0.034799, 0.430045",\ + "-0.183156, -0.148183, -0.083758, -0.051216, 0.344267",\ + "-0.269694, -0.234839, -0.170093, -0.137470, 0.259003",\ + "-0.427321, -0.392813, -0.327135, -0.294275, 0.105065",\ + "-0.690363, -0.656367, -0.589370, -0.556034, -0.150898"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.143047, -0.085078, 0.019349, 0.037994, 0.264586",\ + "-0.232868, -0.174900, -0.070472, -0.051827, 0.174765",\ + "-0.335734, -0.277819, -0.172775, -0.154124, 0.072546",\ + "-0.517254, -0.459461, -0.352995, -0.334328, -0.107479",\ + "-0.818219, -0.760494, -0.651701, -0.632901, -0.404435"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[1]_hldr*/ + +} /* end of pin alert_rsp_i[1] */ + +pin("alert_rsp_i[0]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000500 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[0]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.220674, 0.184637, 0.129589, 0.129760, 0.131844",\ + "0.297060, 0.261023, 0.205975, 0.206146, 0.208230",\ + "0.368632, 0.332596, 0.277611, 0.277778, 0.279805",\ + "0.497931, 0.461898, 0.407219, 0.407363, 0.409115",\ + "0.712779, 0.676837, 0.622759, 0.622852, 0.623986"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.209550, 0.148448, 0.043450, 0.064279, 0.317417",\ + "0.301584, 0.240483, 0.135457, 0.156314, 0.409784",\ + "0.402135, 0.341040, 0.235908, 0.256868, 0.511598",\ + "0.580476, 0.519395, 0.414005, 0.435218, 0.693015",\ + "0.877762, 0.816594, 0.710628, 0.732149, 0.993683"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[0]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.105222, -0.070365, -0.005626, 0.026996, 0.423447",\ + "-0.183185, -0.148328, -0.083588, -0.050966, 0.345485",\ + "-0.257972, -0.223201, -0.158231, -0.125551, 0.271609",\ + "-0.390468, -0.355966, -0.290271, -0.257407, 0.141987",\ + "-0.603765, -0.569785, -0.502723, -0.469420, -0.064694"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.121294, -0.063271, 0.040519, 0.059158, 0.285669",\ + "-0.213390, -0.155380, -0.051441, -0.032801, 0.193729",\ + "-0.313842, -0.255881, -0.151371, -0.132725, 0.093876",\ + "-0.490960, -0.433113, -0.327285, -0.308625, -0.081856",\ + "-0.786249, -0.728564, -0.620239, -0.601510, -0.373902"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[0]_hldr*/ + +} /* end of pin alert_rsp_i[0] */ +} /* end of bus alert_rsp_i */ +bus ( alert_req_o ) { + + bus_type : BUS26_type12 ; + direction : output ; + +pin("alert_req_o[25]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.634048 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000982 ; + + /* Other user defined attributes. */ + original_pin : alert_req_o[25]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\ + "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\ + "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\ + "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\ + "0.584903, 0.727700, 0.813314, 0.950396, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.026420, 0.137079, 0.296659, 0.552264, 2.441059",\ + "0.027606, 0.137424, 0.296659, 0.552264, 2.442441",\ + "0.048973, 0.143889, 0.302016, 0.555346, 2.445574",\ + "0.056124, 0.147298, 0.303942, 0.555346, 2.445574",\ + "0.135119, 0.207795, 0.342920, 0.559922, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\ + "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\ + "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\ + "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\ + "0.637044, 0.700813, 0.755435, 0.842904, 1.478811"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.022299, 0.090049, 0.186120, 0.340034, 1.494292",\ + "0.022299, 0.090163, 0.186120, 0.340034, 1.494292",\ + "0.024376, 0.090410, 0.186120, 0.340034, 1.494292",\ + "0.025559, 0.090772, 0.186120, 0.340034, 1.494292",\ + "0.043338, 0.097514, 0.190357, 0.340034, 1.494292"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[25]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\ + "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\ + "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\ + "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\ + "0.584903, 0.727700, 0.813314, 0.950396, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.026420, 0.137079, 0.296653, 0.551706, 2.441059",\ + "0.027606, 0.137424, 0.296653, 0.551706, 2.442441",\ + "0.048973, 0.143889, 0.302016, 0.554928, 2.445574",\ + "0.056124, 0.147298, 0.303942, 0.554928, 2.445574",\ + "0.135119, 0.207795, 0.342920, 0.559922, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\ + "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\ + "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\ + "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\ + "0.637044, 0.700813, 0.755435, 0.842904, 1.478811"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.022299, 0.090049, 0.185649, 0.338251, 1.490219",\ + "0.022299, 0.090163, 0.185649, 0.338251, 1.490219",\ + "0.024376, 0.090410, 0.185649, 0.338251, 1.490219",\ + "0.025559, 0.090772, 0.185933, 0.338414, 1.490219",\ + "0.043338, 0.097514, 0.190357, 0.339166, 1.490219"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[25]_redg_min*/ + +} /* end of pin alert_req_o[25] */ + +pin("alert_req_o[24]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.634048 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001149 ; + + /* Other user defined attributes. */ + original_pin : alert_req_o[24]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\ + "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\ + "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\ + "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\ + "0.587490, 0.728041, 0.813655, 0.950730, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.027116, 0.137715, 0.297295, 0.552903, 2.441059",\ + "0.028270, 0.138058, 0.297295, 0.552903, 2.442441",\ + "0.049599, 0.144519, 0.302646, 0.555988, 2.445574",\ + "0.056771, 0.147922, 0.304566, 0.555988, 2.445574",\ + "0.136105, 0.208333, 0.343458, 0.560560, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\ + "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\ + "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\ + "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\ + "0.638051, 0.701022, 0.755644, 0.843111, 1.478802"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.022737, 0.090417, 0.186489, 0.340409, 1.494277",\ + "0.022756, 0.090531, 0.186489, 0.340409, 1.494277",\ + "0.024833, 0.090775, 0.186489, 0.340409, 1.494277",\ + "0.025999, 0.091137, 0.186489, 0.340409, 1.494277",\ + "0.043741, 0.097870, 0.190712, 0.340409, 1.494277"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[24]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\ + "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\ + "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\ + "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\ + "0.587490, 0.728041, 0.813655, 0.950730, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.027116, 0.137715, 0.297287, 0.552346, 2.441059",\ + "0.028270, 0.138058, 0.297287, 0.552346, 2.442441",\ + "0.049599, 0.144519, 0.302646, 0.555570, 2.445574",\ + "0.056771, 0.147922, 0.304566, 0.555570, 2.445574",\ + "0.136105, 0.208333, 0.343458, 0.560560, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\ + "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\ + "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\ + "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\ + "0.638051, 0.701022, 0.755644, 0.843111, 1.478802"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.022737, 0.090417, 0.186014, 0.338627, 1.490204",\ + "0.022756, 0.090531, 0.186014, 0.338627, 1.490204",\ + "0.024833, 0.090775, 0.186014, 0.338627, 1.490204",\ + "0.025999, 0.091137, 0.186298, 0.338790, 1.490204",\ + "0.043741, 0.097870, 0.190712, 0.339540, 1.490204"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[24]_redg_min*/ + +} /* end of pin alert_req_o[24] */ + +pin("alert_req_o[23]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.634048 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000982 ; + + /* Other user defined attributes. */ + original_pin : alert_req_o[23]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\ + "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\ + "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\ + "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\ + "0.584903, 0.727700, 0.813314, 0.950396, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.026420, 0.137079, 0.296659, 0.552264, 2.441059",\ + "0.027606, 0.137424, 0.296659, 0.552264, 2.442441",\ + "0.048973, 0.143889, 0.302016, 0.555346, 2.445574",\ + "0.056124, 0.147298, 0.303942, 0.555346, 2.445574",\ + "0.135119, 0.207795, 0.342920, 0.559922, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\ + "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\ + "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\ + "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\ + "0.637044, 0.700813, 0.755435, 0.842904, 1.478811"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.022299, 0.090049, 0.186120, 0.340034, 1.494292",\ + "0.022299, 0.090163, 0.186120, 0.340034, 1.494292",\ + "0.024376, 0.090410, 0.186120, 0.340034, 1.494292",\ + "0.025559, 0.090772, 0.186120, 0.340034, 1.494292",\ + "0.043338, 0.097514, 0.190357, 0.340034, 1.494292"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[23]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\ + "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\ + "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\ + "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\ + "0.584903, 0.727700, 0.813314, 0.950396, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.026420, 0.137079, 0.296653, 0.551706, 2.441059",\ + "0.027606, 0.137424, 0.296653, 0.551706, 2.442441",\ + "0.048973, 0.143889, 0.302016, 0.554928, 2.445574",\ + "0.056124, 0.147298, 0.303942, 0.554928, 2.445574",\ + "0.135119, 0.207795, 0.342920, 0.559922, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\ + "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\ + "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\ + "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\ + "0.637044, 0.700813, 0.755435, 0.842904, 1.478811"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.022299, 0.090049, 0.185649, 0.338251, 1.490219",\ + "0.022299, 0.090163, 0.185649, 0.338251, 1.490219",\ + "0.024376, 0.090410, 0.185649, 0.338251, 1.490219",\ + "0.025559, 0.090772, 0.185933, 0.338414, 1.490219",\ + "0.043338, 0.097514, 0.190357, 0.339166, 1.490219"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[23]_redg_min*/ + +} /* end of pin alert_req_o[23] */ + +pin("alert_req_o[22]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.634048 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001149 ; + + /* Other user defined attributes. */ + original_pin : alert_req_o[22]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\ + "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\ + "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\ + "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\ + "0.587490, 0.728041, 0.813655, 0.950730, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.027116, 0.137715, 0.297295, 0.552903, 2.441059",\ + "0.028270, 0.138058, 0.297295, 0.552903, 2.442441",\ + "0.049599, 0.144519, 0.302646, 0.555988, 2.445574",\ + "0.056771, 0.147922, 0.304566, 0.555988, 2.445574",\ + "0.136105, 0.208333, 0.343458, 0.560560, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\ + "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\ + "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\ + "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\ + "0.638051, 0.701022, 0.755644, 0.843111, 1.478802"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.022737, 0.090417, 0.186489, 0.340409, 1.494277",\ + "0.022756, 0.090531, 0.186489, 0.340409, 1.494277",\ + "0.024833, 0.090775, 0.186489, 0.340409, 1.494277",\ + "0.025999, 0.091137, 0.186489, 0.340409, 1.494277",\ + "0.043741, 0.097870, 0.190712, 0.340409, 1.494277"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[22]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\ + "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\ + "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\ + "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\ + "0.587490, 0.728041, 0.813655, 0.950730, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.027116, 0.137715, 0.297287, 0.552346, 2.441059",\ + "0.028270, 0.138058, 0.297287, 0.552346, 2.442441",\ + "0.049599, 0.144519, 0.302646, 0.555570, 2.445574",\ + "0.056771, 0.147922, 0.304566, 0.555570, 2.445574",\ + "0.136105, 0.208333, 0.343458, 0.560560, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\ + "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\ + "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\ + "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\ + "0.638051, 0.701022, 0.755644, 0.843111, 1.478802"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.022737, 0.090417, 0.186014, 0.338627, 1.490204",\ + "0.022756, 0.090531, 0.186014, 0.338627, 1.490204",\ + "0.024833, 0.090775, 0.186014, 0.338627, 1.490204",\ + "0.025999, 0.091137, 0.186298, 0.338790, 1.490204",\ + "0.043741, 0.097870, 0.190712, 0.339540, 1.490204"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[22]_redg_min*/ + +} /* end of pin alert_req_o[22] */ + +pin("alert_req_o[21]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.634048 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000982 ; + + /* Other user defined attributes. */ + original_pin : alert_req_o[21]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\ + "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\ + "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\ + "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\ + "0.584903, 0.727700, 0.813314, 0.950396, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.026420, 0.137079, 0.296659, 0.552264, 2.441059",\ + "0.027606, 0.137424, 0.296659, 0.552264, 2.442441",\ + "0.048973, 0.143889, 0.302016, 0.555346, 2.445574",\ + "0.056124, 0.147298, 0.303942, 0.555346, 2.445574",\ + "0.135119, 0.207795, 0.342920, 0.559922, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\ + "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\ + "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\ + "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\ + "0.637044, 0.700813, 0.755435, 0.842904, 1.478811"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.022299, 0.090049, 0.186120, 0.340034, 1.494292",\ + "0.022299, 0.090163, 0.186120, 0.340034, 1.494292",\ + "0.024376, 0.090410, 0.186120, 0.340034, 1.494292",\ + "0.025559, 0.090772, 0.186120, 0.340034, 1.494292",\ + "0.043338, 0.097514, 0.190357, 0.340034, 1.494292"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[21]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\ + "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\ + "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\ + "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\ + "0.584903, 0.727700, 0.813314, 0.950396, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.026420, 0.137079, 0.296653, 0.551706, 2.441059",\ + "0.027606, 0.137424, 0.296653, 0.551706, 2.442441",\ + "0.048973, 0.143889, 0.302016, 0.554928, 2.445574",\ + "0.056124, 0.147298, 0.303942, 0.554928, 2.445574",\ + "0.135119, 0.207795, 0.342920, 0.559922, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\ + "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\ + "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\ + "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\ + "0.637044, 0.700813, 0.755435, 0.842904, 1.478811"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.022299, 0.090049, 0.185649, 0.338251, 1.490219",\ + "0.022299, 0.090163, 0.185649, 0.338251, 1.490219",\ + "0.024376, 0.090410, 0.185649, 0.338251, 1.490219",\ + "0.025559, 0.090772, 0.185933, 0.338414, 1.490219",\ + "0.043338, 0.097514, 0.190357, 0.339166, 1.490219"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[21]_redg_min*/ + +} /* end of pin alert_req_o[21] */ + +pin("alert_req_o[20]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.634048 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001149 ; + + /* Other user defined attributes. */ + original_pin : alert_req_o[20]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\ + "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\ + "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\ + "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\ + "0.587490, 0.728041, 0.813655, 0.950730, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.027116, 0.137715, 0.297295, 0.552903, 2.441059",\ + "0.028270, 0.138058, 0.297295, 0.552903, 2.442441",\ + "0.049599, 0.144519, 0.302646, 0.555988, 2.445574",\ + "0.056771, 0.147922, 0.304566, 0.555988, 2.445574",\ + "0.136105, 0.208333, 0.343458, 0.560560, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\ + "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\ + "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\ + "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\ + "0.638051, 0.701022, 0.755644, 0.843111, 1.478802"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.022737, 0.090417, 0.186489, 0.340409, 1.494277",\ + "0.022756, 0.090531, 0.186489, 0.340409, 1.494277",\ + "0.024833, 0.090775, 0.186489, 0.340409, 1.494277",\ + "0.025999, 0.091137, 0.186489, 0.340409, 1.494277",\ + "0.043741, 0.097870, 0.190712, 0.340409, 1.494277"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[20]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\ + "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\ + "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\ + "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\ + "0.587490, 0.728041, 0.813655, 0.950730, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.027116, 0.137715, 0.297287, 0.552346, 2.441059",\ + "0.028270, 0.138058, 0.297287, 0.552346, 2.442441",\ + "0.049599, 0.144519, 0.302646, 0.555570, 2.445574",\ + "0.056771, 0.147922, 0.304566, 0.555570, 2.445574",\ + "0.136105, 0.208333, 0.343458, 0.560560, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\ + "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\ + "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\ + "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\ + "0.638051, 0.701022, 0.755644, 0.843111, 1.478802"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.022737, 0.090417, 0.186014, 0.338627, 1.490204",\ + "0.022756, 0.090531, 0.186014, 0.338627, 1.490204",\ + "0.024833, 0.090775, 0.186014, 0.338627, 1.490204",\ + "0.025999, 0.091137, 0.186298, 0.338790, 1.490204",\ + "0.043741, 0.097870, 0.190712, 0.339540, 1.490204"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[20]_redg_min*/ + +} /* end of pin alert_req_o[20] */ + +pin("alert_req_o[19]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.634048 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000982 ; + + /* Other user defined attributes. */ + original_pin : alert_req_o[19]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\ + "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\ + "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\ + "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\ + "0.584903, 0.727700, 0.813314, 0.950396, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.026420, 0.137079, 0.296659, 0.552264, 2.441059",\ + "0.027606, 0.137424, 0.296659, 0.552264, 2.442441",\ + "0.048973, 0.143889, 0.302016, 0.555346, 2.445574",\ + "0.056124, 0.147298, 0.303942, 0.555346, 2.445574",\ + "0.135119, 0.207795, 0.342920, 0.559922, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\ + "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\ + "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\ + "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\ + "0.637044, 0.700813, 0.755435, 0.842904, 1.478811"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.022299, 0.090049, 0.186120, 0.340034, 1.494292",\ + "0.022299, 0.090163, 0.186120, 0.340034, 1.494292",\ + "0.024376, 0.090410, 0.186120, 0.340034, 1.494292",\ + "0.025559, 0.090772, 0.186120, 0.340034, 1.494292",\ + "0.043338, 0.097514, 0.190357, 0.340034, 1.494292"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[19]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\ + "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\ + "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\ + "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\ + "0.584903, 0.727700, 0.813314, 0.950396, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.026420, 0.137079, 0.296653, 0.551706, 2.441059",\ + "0.027606, 0.137424, 0.296653, 0.551706, 2.442441",\ + "0.048973, 0.143889, 0.302016, 0.554928, 2.445574",\ + "0.056124, 0.147298, 0.303942, 0.554928, 2.445574",\ + "0.135119, 0.207795, 0.342920, 0.559922, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\ + "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\ + "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\ + "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\ + "0.637044, 0.700813, 0.755435, 0.842904, 1.478811"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.022299, 0.090049, 0.185649, 0.338251, 1.490219",\ + "0.022299, 0.090163, 0.185649, 0.338251, 1.490219",\ + "0.024376, 0.090410, 0.185649, 0.338251, 1.490219",\ + "0.025559, 0.090772, 0.185933, 0.338414, 1.490219",\ + "0.043338, 0.097514, 0.190357, 0.339166, 1.490219"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[19]_redg_min*/ + +} /* end of pin alert_req_o[19] */ + +pin("alert_req_o[18]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.634048 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001149 ; + + /* Other user defined attributes. */ + original_pin : alert_req_o[18]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\ + "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\ + "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\ + "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\ + "0.587490, 0.728041, 0.813655, 0.950730, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.027116, 0.137715, 0.297295, 0.552903, 2.441059",\ + "0.028270, 0.138058, 0.297295, 0.552903, 2.442441",\ + "0.049599, 0.144519, 0.302646, 0.555988, 2.445574",\ + "0.056771, 0.147922, 0.304566, 0.555988, 2.445574",\ + "0.136105, 0.208333, 0.343458, 0.560560, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\ + "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\ + "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\ + "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\ + "0.638051, 0.701022, 0.755644, 0.843111, 1.478802"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.022737, 0.090417, 0.186489, 0.340409, 1.494277",\ + "0.022756, 0.090531, 0.186489, 0.340409, 1.494277",\ + "0.024833, 0.090775, 0.186489, 0.340409, 1.494277",\ + "0.025999, 0.091137, 0.186489, 0.340409, 1.494277",\ + "0.043741, 0.097870, 0.190712, 0.340409, 1.494277"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[18]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\ + "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\ + "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\ + "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\ + "0.587490, 0.728041, 0.813655, 0.950730, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.027116, 0.137715, 0.297287, 0.552346, 2.441059",\ + "0.028270, 0.138058, 0.297287, 0.552346, 2.442441",\ + "0.049599, 0.144519, 0.302646, 0.555570, 2.445574",\ + "0.056771, 0.147922, 0.304566, 0.555570, 2.445574",\ + "0.136105, 0.208333, 0.343458, 0.560560, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\ + "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\ + "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\ + "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\ + "0.638051, 0.701022, 0.755644, 0.843111, 1.478802"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.022737, 0.090417, 0.186014, 0.338627, 1.490204",\ + "0.022756, 0.090531, 0.186014, 0.338627, 1.490204",\ + "0.024833, 0.090775, 0.186014, 0.338627, 1.490204",\ + "0.025999, 0.091137, 0.186298, 0.338790, 1.490204",\ + "0.043741, 0.097870, 0.190712, 0.339540, 1.490204"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[18]_redg_min*/ + +} /* end of pin alert_req_o[18] */ + +pin("alert_req_o[17]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.634048 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000982 ; + + /* Other user defined attributes. */ + original_pin : alert_req_o[17]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\ + "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\ + "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\ + "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\ + "0.584903, 0.727700, 0.813314, 0.950396, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.026420, 0.137079, 0.296659, 0.552264, 2.441059",\ + "0.027606, 0.137424, 0.296659, 0.552264, 2.442441",\ + "0.048973, 0.143889, 0.302016, 0.555346, 2.445574",\ + "0.056124, 0.147298, 0.303942, 0.555346, 2.445574",\ + "0.135119, 0.207795, 0.342920, 0.559922, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\ + "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\ + "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\ + "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\ + "0.637044, 0.700813, 0.755435, 0.842904, 1.478811"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.022299, 0.090049, 0.186120, 0.340034, 1.494292",\ + "0.022299, 0.090163, 0.186120, 0.340034, 1.494292",\ + "0.024376, 0.090410, 0.186120, 0.340034, 1.494292",\ + "0.025559, 0.090772, 0.186120, 0.340034, 1.494292",\ + "0.043338, 0.097514, 0.190357, 0.340034, 1.494292"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[17]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\ + "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\ + "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\ + "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\ + "0.584903, 0.727700, 0.813314, 0.950396, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.026420, 0.137079, 0.296653, 0.551706, 2.441059",\ + "0.027606, 0.137424, 0.296653, 0.551706, 2.442441",\ + "0.048973, 0.143889, 0.302016, 0.554928, 2.445574",\ + "0.056124, 0.147298, 0.303942, 0.554928, 2.445574",\ + "0.135119, 0.207795, 0.342920, 0.559922, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\ + "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\ + "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\ + "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\ + "0.637044, 0.700813, 0.755435, 0.842904, 1.478811"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.022299, 0.090049, 0.185649, 0.338251, 1.490219",\ + "0.022299, 0.090163, 0.185649, 0.338251, 1.490219",\ + "0.024376, 0.090410, 0.185649, 0.338251, 1.490219",\ + "0.025559, 0.090772, 0.185933, 0.338414, 1.490219",\ + "0.043338, 0.097514, 0.190357, 0.339166, 1.490219"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[17]_redg_min*/ + +} /* end of pin alert_req_o[17] */ + +pin("alert_req_o[16]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.634048 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001149 ; + + /* Other user defined attributes. */ + original_pin : alert_req_o[16]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\ + "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\ + "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\ + "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\ + "0.587490, 0.728041, 0.813655, 0.950730, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.027116, 0.137715, 0.297295, 0.552903, 2.441059",\ + "0.028270, 0.138058, 0.297295, 0.552903, 2.442441",\ + "0.049599, 0.144519, 0.302646, 0.555988, 2.445574",\ + "0.056771, 0.147922, 0.304566, 0.555988, 2.445574",\ + "0.136105, 0.208333, 0.343458, 0.560560, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\ + "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\ + "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\ + "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\ + "0.638051, 0.701022, 0.755644, 0.843111, 1.478802"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.022737, 0.090417, 0.186489, 0.340409, 1.494277",\ + "0.022756, 0.090531, 0.186489, 0.340409, 1.494277",\ + "0.024833, 0.090775, 0.186489, 0.340409, 1.494277",\ + "0.025999, 0.091137, 0.186489, 0.340409, 1.494277",\ + "0.043741, 0.097870, 0.190712, 0.340409, 1.494277"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[16]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\ + "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\ + "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\ + "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\ + "0.587490, 0.728041, 0.813655, 0.950730, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.027116, 0.137715, 0.297287, 0.552346, 2.441059",\ + "0.028270, 0.138058, 0.297287, 0.552346, 2.442441",\ + "0.049599, 0.144519, 0.302646, 0.555570, 2.445574",\ + "0.056771, 0.147922, 0.304566, 0.555570, 2.445574",\ + "0.136105, 0.208333, 0.343458, 0.560560, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\ + "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\ + "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\ + "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\ + "0.638051, 0.701022, 0.755644, 0.843111, 1.478802"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.022737, 0.090417, 0.186014, 0.338627, 1.490204",\ + "0.022756, 0.090531, 0.186014, 0.338627, 1.490204",\ + "0.024833, 0.090775, 0.186014, 0.338627, 1.490204",\ + "0.025999, 0.091137, 0.186298, 0.338790, 1.490204",\ + "0.043741, 0.097870, 0.190712, 0.339540, 1.490204"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[16]_redg_min*/ + +} /* end of pin alert_req_o[16] */ + +pin("alert_req_o[15]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.634048 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000982 ; + + /* Other user defined attributes. */ + original_pin : alert_req_o[15]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\ + "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\ + "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\ + "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\ + "0.584903, 0.727700, 0.813314, 0.950396, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.026420, 0.137079, 0.296659, 0.552264, 2.441059",\ + "0.027606, 0.137424, 0.296659, 0.552264, 2.442441",\ + "0.048973, 0.143889, 0.302016, 0.555346, 2.445574",\ + "0.056124, 0.147298, 0.303942, 0.555346, 2.445574",\ + "0.135119, 0.207795, 0.342920, 0.559922, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\ + "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\ + "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\ + "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\ + "0.637044, 0.700813, 0.755435, 0.842904, 1.478811"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.022299, 0.090049, 0.186120, 0.340034, 1.494292",\ + "0.022299, 0.090163, 0.186120, 0.340034, 1.494292",\ + "0.024376, 0.090410, 0.186120, 0.340034, 1.494292",\ + "0.025559, 0.090772, 0.186120, 0.340034, 1.494292",\ + "0.043338, 0.097514, 0.190357, 0.340034, 1.494292"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[15]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\ + "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\ + "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\ + "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\ + "0.584903, 0.727700, 0.813314, 0.950396, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.026420, 0.137079, 0.296653, 0.551706, 2.441059",\ + "0.027606, 0.137424, 0.296653, 0.551706, 2.442441",\ + "0.048973, 0.143889, 0.302016, 0.554928, 2.445574",\ + "0.056124, 0.147298, 0.303942, 0.554928, 2.445574",\ + "0.135119, 0.207795, 0.342920, 0.559922, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\ + "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\ + "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\ + "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\ + "0.637044, 0.700813, 0.755435, 0.842904, 1.478811"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.022299, 0.090049, 0.185649, 0.338251, 1.490219",\ + "0.022299, 0.090163, 0.185649, 0.338251, 1.490219",\ + "0.024376, 0.090410, 0.185649, 0.338251, 1.490219",\ + "0.025559, 0.090772, 0.185933, 0.338414, 1.490219",\ + "0.043338, 0.097514, 0.190357, 0.339166, 1.490219"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[15]_redg_min*/ + +} /* end of pin alert_req_o[15] */ + +pin("alert_req_o[14]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.634048 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001149 ; + + /* Other user defined attributes. */ + original_pin : alert_req_o[14]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\ + "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\ + "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\ + "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\ + "0.587490, 0.728041, 0.813655, 0.950730, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.027116, 0.137715, 0.297295, 0.552903, 2.441059",\ + "0.028270, 0.138058, 0.297295, 0.552903, 2.442441",\ + "0.049599, 0.144519, 0.302646, 0.555988, 2.445574",\ + "0.056771, 0.147922, 0.304566, 0.555988, 2.445574",\ + "0.136105, 0.208333, 0.343458, 0.560560, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\ + "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\ + "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\ + "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\ + "0.638051, 0.701022, 0.755644, 0.843111, 1.478802"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.022737, 0.090417, 0.186489, 0.340409, 1.494277",\ + "0.022756, 0.090531, 0.186489, 0.340409, 1.494277",\ + "0.024833, 0.090775, 0.186489, 0.340409, 1.494277",\ + "0.025999, 0.091137, 0.186489, 0.340409, 1.494277",\ + "0.043741, 0.097870, 0.190712, 0.340409, 1.494277"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[14]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\ + "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\ + "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\ + "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\ + "0.587490, 0.728041, 0.813655, 0.950730, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.027116, 0.137715, 0.297287, 0.552346, 2.441059",\ + "0.028270, 0.138058, 0.297287, 0.552346, 2.442441",\ + "0.049599, 0.144519, 0.302646, 0.555570, 2.445574",\ + "0.056771, 0.147922, 0.304566, 0.555570, 2.445574",\ + "0.136105, 0.208333, 0.343458, 0.560560, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\ + "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\ + "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\ + "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\ + "0.638051, 0.701022, 0.755644, 0.843111, 1.478802"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.022737, 0.090417, 0.186014, 0.338627, 1.490204",\ + "0.022756, 0.090531, 0.186014, 0.338627, 1.490204",\ + "0.024833, 0.090775, 0.186014, 0.338627, 1.490204",\ + "0.025999, 0.091137, 0.186298, 0.338790, 1.490204",\ + "0.043741, 0.097870, 0.190712, 0.339540, 1.490204"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[14]_redg_min*/ + +} /* end of pin alert_req_o[14] */ + +pin("alert_req_o[13]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.634048 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000982 ; + + /* Other user defined attributes. */ + original_pin : alert_req_o[13]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\ + "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\ + "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\ + "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\ + "0.584903, 0.727700, 0.813314, 0.950396, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.026420, 0.137079, 0.296659, 0.552264, 2.441059",\ + "0.027606, 0.137424, 0.296659, 0.552264, 2.442441",\ + "0.048973, 0.143889, 0.302016, 0.555346, 2.445574",\ + "0.056124, 0.147298, 0.303942, 0.555346, 2.445574",\ + "0.135119, 0.207795, 0.342920, 0.559922, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\ + "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\ + "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\ + "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\ + "0.637044, 0.700813, 0.755435, 0.842904, 1.478811"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.022299, 0.090049, 0.186120, 0.340034, 1.494292",\ + "0.022299, 0.090163, 0.186120, 0.340034, 1.494292",\ + "0.024376, 0.090410, 0.186120, 0.340034, 1.494292",\ + "0.025559, 0.090772, 0.186120, 0.340034, 1.494292",\ + "0.043338, 0.097514, 0.190357, 0.340034, 1.494292"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[13]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\ + "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\ + "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\ + "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\ + "0.584903, 0.727700, 0.813314, 0.950396, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.026420, 0.137079, 0.296653, 0.551706, 2.441059",\ + "0.027606, 0.137424, 0.296653, 0.551706, 2.442441",\ + "0.048973, 0.143889, 0.302016, 0.554928, 2.445574",\ + "0.056124, 0.147298, 0.303942, 0.554928, 2.445574",\ + "0.135119, 0.207795, 0.342920, 0.559922, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\ + "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\ + "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\ + "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\ + "0.637044, 0.700813, 0.755435, 0.842904, 1.478811"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.022299, 0.090049, 0.185649, 0.338251, 1.490219",\ + "0.022299, 0.090163, 0.185649, 0.338251, 1.490219",\ + "0.024376, 0.090410, 0.185649, 0.338251, 1.490219",\ + "0.025559, 0.090772, 0.185933, 0.338414, 1.490219",\ + "0.043338, 0.097514, 0.190357, 0.339166, 1.490219"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[13]_redg_min*/ + +} /* end of pin alert_req_o[13] */ + +pin("alert_req_o[12]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.634048 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001149 ; + + /* Other user defined attributes. */ + original_pin : alert_req_o[12]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\ + "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\ + "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\ + "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\ + "0.587490, 0.728041, 0.813655, 0.950730, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.027116, 0.137715, 0.297295, 0.552903, 2.441059",\ + "0.028270, 0.138058, 0.297295, 0.552903, 2.442441",\ + "0.049599, 0.144519, 0.302646, 0.555988, 2.445574",\ + "0.056771, 0.147922, 0.304566, 0.555988, 2.445574",\ + "0.136105, 0.208333, 0.343458, 0.560560, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\ + "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\ + "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\ + "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\ + "0.638051, 0.701022, 0.755644, 0.843111, 1.478802"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.022737, 0.090417, 0.186489, 0.340409, 1.494277",\ + "0.022756, 0.090531, 0.186489, 0.340409, 1.494277",\ + "0.024833, 0.090775, 0.186489, 0.340409, 1.494277",\ + "0.025999, 0.091137, 0.186489, 0.340409, 1.494277",\ + "0.043741, 0.097870, 0.190712, 0.340409, 1.494277"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[12]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\ + "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\ + "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\ + "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\ + "0.587490, 0.728041, 0.813655, 0.950730, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.027116, 0.137715, 0.297287, 0.552346, 2.441059",\ + "0.028270, 0.138058, 0.297287, 0.552346, 2.442441",\ + "0.049599, 0.144519, 0.302646, 0.555570, 2.445574",\ + "0.056771, 0.147922, 0.304566, 0.555570, 2.445574",\ + "0.136105, 0.208333, 0.343458, 0.560560, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\ + "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\ + "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\ + "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\ + "0.638051, 0.701022, 0.755644, 0.843111, 1.478802"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.022737, 0.090417, 0.186014, 0.338627, 1.490204",\ + "0.022756, 0.090531, 0.186014, 0.338627, 1.490204",\ + "0.024833, 0.090775, 0.186014, 0.338627, 1.490204",\ + "0.025999, 0.091137, 0.186298, 0.338790, 1.490204",\ + "0.043741, 0.097870, 0.190712, 0.339540, 1.490204"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[12]_redg_min*/ + +} /* end of pin alert_req_o[12] */ + +pin("alert_req_o[11]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.634048 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000982 ; + + /* Other user defined attributes. */ + original_pin : alert_req_o[11]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\ + "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\ + "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\ + "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\ + "0.584903, 0.727700, 0.813314, 0.950396, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.026420, 0.137079, 0.296659, 0.552264, 2.441059",\ + "0.027606, 0.137424, 0.296659, 0.552264, 2.442441",\ + "0.048973, 0.143889, 0.302016, 0.555346, 2.445574",\ + "0.056124, 0.147298, 0.303942, 0.555346, 2.445574",\ + "0.135119, 0.207795, 0.342920, 0.559922, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\ + "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\ + "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\ + "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\ + "0.637044, 0.700813, 0.755435, 0.842904, 1.478811"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.022299, 0.090049, 0.186120, 0.340034, 1.494292",\ + "0.022299, 0.090163, 0.186120, 0.340034, 1.494292",\ + "0.024376, 0.090410, 0.186120, 0.340034, 1.494292",\ + "0.025559, 0.090772, 0.186120, 0.340034, 1.494292",\ + "0.043338, 0.097514, 0.190357, 0.340034, 1.494292"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[11]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\ + "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\ + "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\ + "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\ + "0.584903, 0.727700, 0.813314, 0.950396, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.026420, 0.137079, 0.296653, 0.551706, 2.441059",\ + "0.027606, 0.137424, 0.296653, 0.551706, 2.442441",\ + "0.048973, 0.143889, 0.302016, 0.554928, 2.445574",\ + "0.056124, 0.147298, 0.303942, 0.554928, 2.445574",\ + "0.135119, 0.207795, 0.342920, 0.559922, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\ + "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\ + "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\ + "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\ + "0.637044, 0.700813, 0.755435, 0.842904, 1.478811"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.022299, 0.090049, 0.185649, 0.338251, 1.490219",\ + "0.022299, 0.090163, 0.185649, 0.338251, 1.490219",\ + "0.024376, 0.090410, 0.185649, 0.338251, 1.490219",\ + "0.025559, 0.090772, 0.185933, 0.338414, 1.490219",\ + "0.043338, 0.097514, 0.190357, 0.339166, 1.490219"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[11]_redg_min*/ + +} /* end of pin alert_req_o[11] */ + +pin("alert_req_o[10]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.634048 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001149 ; + + /* Other user defined attributes. */ + original_pin : alert_req_o[10]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\ + "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\ + "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\ + "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\ + "0.587490, 0.728041, 0.813655, 0.950730, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.027116, 0.137715, 0.297295, 0.552903, 2.441059",\ + "0.028270, 0.138058, 0.297295, 0.552903, 2.442441",\ + "0.049599, 0.144519, 0.302646, 0.555988, 2.445574",\ + "0.056771, 0.147922, 0.304566, 0.555988, 2.445574",\ + "0.136105, 0.208333, 0.343458, 0.560560, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\ + "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\ + "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\ + "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\ + "0.638051, 0.701022, 0.755644, 0.843111, 1.478802"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.022737, 0.090417, 0.186489, 0.340409, 1.494277",\ + "0.022756, 0.090531, 0.186489, 0.340409, 1.494277",\ + "0.024833, 0.090775, 0.186489, 0.340409, 1.494277",\ + "0.025999, 0.091137, 0.186489, 0.340409, 1.494277",\ + "0.043741, 0.097870, 0.190712, 0.340409, 1.494277"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[10]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\ + "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\ + "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\ + "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\ + "0.587490, 0.728041, 0.813655, 0.950730, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.027116, 0.137715, 0.297287, 0.552346, 2.441059",\ + "0.028270, 0.138058, 0.297287, 0.552346, 2.442441",\ + "0.049599, 0.144519, 0.302646, 0.555570, 2.445574",\ + "0.056771, 0.147922, 0.304566, 0.555570, 2.445574",\ + "0.136105, 0.208333, 0.343458, 0.560560, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\ + "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\ + "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\ + "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\ + "0.638051, 0.701022, 0.755644, 0.843111, 1.478802"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.022737, 0.090417, 0.186014, 0.338627, 1.490204",\ + "0.022756, 0.090531, 0.186014, 0.338627, 1.490204",\ + "0.024833, 0.090775, 0.186014, 0.338627, 1.490204",\ + "0.025999, 0.091137, 0.186298, 0.338790, 1.490204",\ + "0.043741, 0.097870, 0.190712, 0.339540, 1.490204"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[10]_redg_min*/ + +} /* end of pin alert_req_o[10] */ + +pin("alert_req_o[9]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.634048 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000982 ; + + /* Other user defined attributes. */ + original_pin : alert_req_o[9]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\ + "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\ + "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\ + "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\ + "0.584903, 0.727700, 0.813314, 0.950396, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.026420, 0.137079, 0.296659, 0.552264, 2.441059",\ + "0.027606, 0.137424, 0.296659, 0.552264, 2.442441",\ + "0.048973, 0.143889, 0.302016, 0.555346, 2.445574",\ + "0.056124, 0.147298, 0.303942, 0.555346, 2.445574",\ + "0.135119, 0.207795, 0.342920, 0.559922, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\ + "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\ + "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\ + "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\ + "0.637044, 0.700813, 0.755435, 0.842904, 1.478811"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.022299, 0.090049, 0.186120, 0.340034, 1.494292",\ + "0.022299, 0.090163, 0.186120, 0.340034, 1.494292",\ + "0.024376, 0.090410, 0.186120, 0.340034, 1.494292",\ + "0.025559, 0.090772, 0.186120, 0.340034, 1.494292",\ + "0.043338, 0.097514, 0.190357, 0.340034, 1.494292"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[9]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\ + "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\ + "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\ + "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\ + "0.584903, 0.727700, 0.813314, 0.950396, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.026420, 0.137079, 0.296653, 0.551706, 2.441059",\ + "0.027606, 0.137424, 0.296653, 0.551706, 2.442441",\ + "0.048973, 0.143889, 0.302016, 0.554928, 2.445574",\ + "0.056124, 0.147298, 0.303942, 0.554928, 2.445574",\ + "0.135119, 0.207795, 0.342920, 0.559922, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\ + "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\ + "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\ + "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\ + "0.637044, 0.700813, 0.755435, 0.842904, 1.478811"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.022299, 0.090049, 0.185649, 0.338251, 1.490219",\ + "0.022299, 0.090163, 0.185649, 0.338251, 1.490219",\ + "0.024376, 0.090410, 0.185649, 0.338251, 1.490219",\ + "0.025559, 0.090772, 0.185933, 0.338414, 1.490219",\ + "0.043338, 0.097514, 0.190357, 0.339166, 1.490219"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[9]_redg_min*/ + +} /* end of pin alert_req_o[9] */ + +pin("alert_req_o[8]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.634048 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001149 ; + + /* Other user defined attributes. */ + original_pin : alert_req_o[8]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\ + "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\ + "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\ + "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\ + "0.587490, 0.728041, 0.813655, 0.950730, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.027116, 0.137715, 0.297295, 0.552903, 2.441059",\ + "0.028270, 0.138058, 0.297295, 0.552903, 2.442441",\ + "0.049599, 0.144519, 0.302646, 0.555988, 2.445574",\ + "0.056771, 0.147922, 0.304566, 0.555988, 2.445574",\ + "0.136105, 0.208333, 0.343458, 0.560560, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\ + "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\ + "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\ + "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\ + "0.638051, 0.701022, 0.755644, 0.843111, 1.478802"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.022737, 0.090417, 0.186489, 0.340409, 1.494277",\ + "0.022756, 0.090531, 0.186489, 0.340409, 1.494277",\ + "0.024833, 0.090775, 0.186489, 0.340409, 1.494277",\ + "0.025999, 0.091137, 0.186489, 0.340409, 1.494277",\ + "0.043741, 0.097870, 0.190712, 0.340409, 1.494277"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[8]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\ + "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\ + "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\ + "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\ + "0.587490, 0.728041, 0.813655, 0.950730, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.027116, 0.137715, 0.297287, 0.552346, 2.441059",\ + "0.028270, 0.138058, 0.297287, 0.552346, 2.442441",\ + "0.049599, 0.144519, 0.302646, 0.555570, 2.445574",\ + "0.056771, 0.147922, 0.304566, 0.555570, 2.445574",\ + "0.136105, 0.208333, 0.343458, 0.560560, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\ + "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\ + "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\ + "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\ + "0.638051, 0.701022, 0.755644, 0.843111, 1.478802"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.022737, 0.090417, 0.186014, 0.338627, 1.490204",\ + "0.022756, 0.090531, 0.186014, 0.338627, 1.490204",\ + "0.024833, 0.090775, 0.186014, 0.338627, 1.490204",\ + "0.025999, 0.091137, 0.186298, 0.338790, 1.490204",\ + "0.043741, 0.097870, 0.190712, 0.339540, 1.490204"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[8]_redg_min*/ + +} /* end of pin alert_req_o[8] */ + +pin("alert_req_o[7]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.634048 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000982 ; + + /* Other user defined attributes. */ + original_pin : alert_req_o[7]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\ + "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\ + "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\ + "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\ + "0.584903, 0.727700, 0.813314, 0.950396, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.026420, 0.137079, 0.296659, 0.552264, 2.441059",\ + "0.027606, 0.137424, 0.296659, 0.552264, 2.442441",\ + "0.048973, 0.143889, 0.302016, 0.555346, 2.445574",\ + "0.056124, 0.147298, 0.303942, 0.555346, 2.445574",\ + "0.135119, 0.207795, 0.342920, 0.559922, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\ + "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\ + "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\ + "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\ + "0.637044, 0.700813, 0.755435, 0.842904, 1.478811"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.022299, 0.090049, 0.186120, 0.340034, 1.494292",\ + "0.022299, 0.090163, 0.186120, 0.340034, 1.494292",\ + "0.024376, 0.090410, 0.186120, 0.340034, 1.494292",\ + "0.025559, 0.090772, 0.186120, 0.340034, 1.494292",\ + "0.043338, 0.097514, 0.190357, 0.340034, 1.494292"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[7]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\ + "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\ + "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\ + "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\ + "0.584903, 0.727700, 0.813314, 0.950396, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.026420, 0.137079, 0.296653, 0.551706, 2.441059",\ + "0.027606, 0.137424, 0.296653, 0.551706, 2.442441",\ + "0.048973, 0.143889, 0.302016, 0.554928, 2.445574",\ + "0.056124, 0.147298, 0.303942, 0.554928, 2.445574",\ + "0.135119, 0.207795, 0.342920, 0.559922, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\ + "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\ + "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\ + "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\ + "0.637044, 0.700813, 0.755435, 0.842904, 1.478811"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.022299, 0.090049, 0.185649, 0.338251, 1.490219",\ + "0.022299, 0.090163, 0.185649, 0.338251, 1.490219",\ + "0.024376, 0.090410, 0.185649, 0.338251, 1.490219",\ + "0.025559, 0.090772, 0.185933, 0.338414, 1.490219",\ + "0.043338, 0.097514, 0.190357, 0.339166, 1.490219"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[7]_redg_min*/ + +} /* end of pin alert_req_o[7] */ + +pin("alert_req_o[6]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.634048 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001149 ; + + /* Other user defined attributes. */ + original_pin : alert_req_o[6]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\ + "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\ + "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\ + "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\ + "0.587490, 0.728041, 0.813655, 0.950730, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.027116, 0.137715, 0.297295, 0.552903, 2.441059",\ + "0.028270, 0.138058, 0.297295, 0.552903, 2.442441",\ + "0.049599, 0.144519, 0.302646, 0.555988, 2.445574",\ + "0.056771, 0.147922, 0.304566, 0.555988, 2.445574",\ + "0.136105, 0.208333, 0.343458, 0.560560, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\ + "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\ + "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\ + "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\ + "0.638051, 0.701022, 0.755644, 0.843111, 1.478802"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.022737, 0.090417, 0.186489, 0.340409, 1.494277",\ + "0.022756, 0.090531, 0.186489, 0.340409, 1.494277",\ + "0.024833, 0.090775, 0.186489, 0.340409, 1.494277",\ + "0.025999, 0.091137, 0.186489, 0.340409, 1.494277",\ + "0.043741, 0.097870, 0.190712, 0.340409, 1.494277"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[6]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\ + "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\ + "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\ + "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\ + "0.587490, 0.728041, 0.813655, 0.950730, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.027116, 0.137715, 0.297287, 0.552346, 2.441059",\ + "0.028270, 0.138058, 0.297287, 0.552346, 2.442441",\ + "0.049599, 0.144519, 0.302646, 0.555570, 2.445574",\ + "0.056771, 0.147922, 0.304566, 0.555570, 2.445574",\ + "0.136105, 0.208333, 0.343458, 0.560560, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\ + "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\ + "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\ + "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\ + "0.638051, 0.701022, 0.755644, 0.843111, 1.478802"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.022737, 0.090417, 0.186014, 0.338627, 1.490204",\ + "0.022756, 0.090531, 0.186014, 0.338627, 1.490204",\ + "0.024833, 0.090775, 0.186014, 0.338627, 1.490204",\ + "0.025999, 0.091137, 0.186298, 0.338790, 1.490204",\ + "0.043741, 0.097870, 0.190712, 0.339540, 1.490204"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[6]_redg_min*/ + +} /* end of pin alert_req_o[6] */ + +pin("alert_req_o[5]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.634048 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000982 ; + + /* Other user defined attributes. */ + original_pin : alert_req_o[5]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\ + "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\ + "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\ + "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\ + "0.584903, 0.727700, 0.813314, 0.950396, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.026420, 0.137079, 0.296659, 0.552264, 2.441059",\ + "0.027606, 0.137424, 0.296659, 0.552264, 2.442441",\ + "0.048973, 0.143889, 0.302016, 0.555346, 2.445574",\ + "0.056124, 0.147298, 0.303942, 0.555346, 2.445574",\ + "0.135119, 0.207795, 0.342920, 0.559922, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\ + "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\ + "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\ + "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\ + "0.637044, 0.700813, 0.755435, 0.842904, 1.478811"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.022299, 0.090049, 0.186120, 0.340034, 1.494292",\ + "0.022299, 0.090163, 0.186120, 0.340034, 1.494292",\ + "0.024376, 0.090410, 0.186120, 0.340034, 1.494292",\ + "0.025559, 0.090772, 0.186120, 0.340034, 1.494292",\ + "0.043338, 0.097514, 0.190357, 0.340034, 1.494292"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[5]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\ + "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\ + "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\ + "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\ + "0.584903, 0.727700, 0.813314, 0.950396, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.026420, 0.137079, 0.296653, 0.551706, 2.441059",\ + "0.027606, 0.137424, 0.296653, 0.551706, 2.442441",\ + "0.048973, 0.143889, 0.302016, 0.554928, 2.445574",\ + "0.056124, 0.147298, 0.303942, 0.554928, 2.445574",\ + "0.135119, 0.207795, 0.342920, 0.559922, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\ + "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\ + "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\ + "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\ + "0.637044, 0.700813, 0.755435, 0.842904, 1.478811"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.022299, 0.090049, 0.185649, 0.338251, 1.490219",\ + "0.022299, 0.090163, 0.185649, 0.338251, 1.490219",\ + "0.024376, 0.090410, 0.185649, 0.338251, 1.490219",\ + "0.025559, 0.090772, 0.185933, 0.338414, 1.490219",\ + "0.043338, 0.097514, 0.190357, 0.339166, 1.490219"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[5]_redg_min*/ + +} /* end of pin alert_req_o[5] */ + +pin("alert_req_o[4]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.634048 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001149 ; + + /* Other user defined attributes. */ + original_pin : alert_req_o[4]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\ + "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\ + "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\ + "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\ + "0.587490, 0.728041, 0.813655, 0.950730, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.027116, 0.137715, 0.297295, 0.552903, 2.441059",\ + "0.028270, 0.138058, 0.297295, 0.552903, 2.442441",\ + "0.049599, 0.144519, 0.302646, 0.555988, 2.445574",\ + "0.056771, 0.147922, 0.304566, 0.555988, 2.445574",\ + "0.136105, 0.208333, 0.343458, 0.560560, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\ + "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\ + "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\ + "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\ + "0.638051, 0.701022, 0.755644, 0.843111, 1.478802"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.022737, 0.090417, 0.186489, 0.340409, 1.494277",\ + "0.022756, 0.090531, 0.186489, 0.340409, 1.494277",\ + "0.024833, 0.090775, 0.186489, 0.340409, 1.494277",\ + "0.025999, 0.091137, 0.186489, 0.340409, 1.494277",\ + "0.043741, 0.097870, 0.190712, 0.340409, 1.494277"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[4]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\ + "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\ + "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\ + "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\ + "0.587490, 0.728041, 0.813655, 0.950730, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.027116, 0.137715, 0.297287, 0.552346, 2.441059",\ + "0.028270, 0.138058, 0.297287, 0.552346, 2.442441",\ + "0.049599, 0.144519, 0.302646, 0.555570, 2.445574",\ + "0.056771, 0.147922, 0.304566, 0.555570, 2.445574",\ + "0.136105, 0.208333, 0.343458, 0.560560, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\ + "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\ + "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\ + "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\ + "0.638051, 0.701022, 0.755644, 0.843111, 1.478802"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.022737, 0.090417, 0.186014, 0.338627, 1.490204",\ + "0.022756, 0.090531, 0.186014, 0.338627, 1.490204",\ + "0.024833, 0.090775, 0.186014, 0.338627, 1.490204",\ + "0.025999, 0.091137, 0.186298, 0.338790, 1.490204",\ + "0.043741, 0.097870, 0.190712, 0.339540, 1.490204"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[4]_redg_min*/ + +} /* end of pin alert_req_o[4] */ + +pin("alert_req_o[3]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.634048 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000982 ; + + /* Other user defined attributes. */ + original_pin : alert_req_o[3]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\ + "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\ + "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\ + "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\ + "0.584903, 0.727700, 0.813314, 0.950396, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.026420, 0.137079, 0.296659, 0.552264, 2.441059",\ + "0.027606, 0.137424, 0.296659, 0.552264, 2.442441",\ + "0.048973, 0.143889, 0.302016, 0.555346, 2.445574",\ + "0.056124, 0.147298, 0.303942, 0.555346, 2.445574",\ + "0.135119, 0.207795, 0.342920, 0.559922, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\ + "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\ + "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\ + "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\ + "0.637044, 0.700813, 0.755435, 0.842904, 1.478811"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.022299, 0.090049, 0.186120, 0.340034, 1.494292",\ + "0.022299, 0.090163, 0.186120, 0.340034, 1.494292",\ + "0.024376, 0.090410, 0.186120, 0.340034, 1.494292",\ + "0.025559, 0.090772, 0.186120, 0.340034, 1.494292",\ + "0.043338, 0.097514, 0.190357, 0.340034, 1.494292"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[3]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\ + "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\ + "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\ + "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\ + "0.584903, 0.727700, 0.813314, 0.950396, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.026420, 0.137079, 0.296653, 0.551706, 2.441059",\ + "0.027606, 0.137424, 0.296653, 0.551706, 2.442441",\ + "0.048973, 0.143889, 0.302016, 0.554928, 2.445574",\ + "0.056124, 0.147298, 0.303942, 0.554928, 2.445574",\ + "0.135119, 0.207795, 0.342920, 0.559922, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\ + "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\ + "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\ + "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\ + "0.637044, 0.700813, 0.755435, 0.842904, 1.478811"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.022299, 0.090049, 0.185649, 0.338251, 1.490219",\ + "0.022299, 0.090163, 0.185649, 0.338251, 1.490219",\ + "0.024376, 0.090410, 0.185649, 0.338251, 1.490219",\ + "0.025559, 0.090772, 0.185933, 0.338414, 1.490219",\ + "0.043338, 0.097514, 0.190357, 0.339166, 1.490219"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[3]_redg_min*/ + +} /* end of pin alert_req_o[3] */ + +pin("alert_req_o[2]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.634048 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001149 ; + + /* Other user defined attributes. */ + original_pin : alert_req_o[2]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\ + "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\ + "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\ + "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\ + "0.587490, 0.728041, 0.813655, 0.950730, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.027116, 0.137715, 0.297295, 0.552903, 2.441059",\ + "0.028270, 0.138058, 0.297295, 0.552903, 2.442441",\ + "0.049599, 0.144519, 0.302646, 0.555988, 2.445574",\ + "0.056771, 0.147922, 0.304566, 0.555988, 2.445574",\ + "0.136105, 0.208333, 0.343458, 0.560560, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\ + "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\ + "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\ + "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\ + "0.638051, 0.701022, 0.755644, 0.843111, 1.478802"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.022737, 0.090417, 0.186489, 0.340409, 1.494277",\ + "0.022756, 0.090531, 0.186489, 0.340409, 1.494277",\ + "0.024833, 0.090775, 0.186489, 0.340409, 1.494277",\ + "0.025999, 0.091137, 0.186489, 0.340409, 1.494277",\ + "0.043741, 0.097870, 0.190712, 0.340409, 1.494277"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[2]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\ + "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\ + "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\ + "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\ + "0.587490, 0.728041, 0.813655, 0.950730, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.027116, 0.137715, 0.297287, 0.552346, 2.441059",\ + "0.028270, 0.138058, 0.297287, 0.552346, 2.442441",\ + "0.049599, 0.144519, 0.302646, 0.555570, 2.445574",\ + "0.056771, 0.147922, 0.304566, 0.555570, 2.445574",\ + "0.136105, 0.208333, 0.343458, 0.560560, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\ + "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\ + "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\ + "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\ + "0.638051, 0.701022, 0.755644, 0.843111, 1.478802"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.022737, 0.090417, 0.186014, 0.338627, 1.490204",\ + "0.022756, 0.090531, 0.186014, 0.338627, 1.490204",\ + "0.024833, 0.090775, 0.186014, 0.338627, 1.490204",\ + "0.025999, 0.091137, 0.186298, 0.338790, 1.490204",\ + "0.043741, 0.097870, 0.190712, 0.339540, 1.490204"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[2]_redg_min*/ + +} /* end of pin alert_req_o[2] */ + +pin("alert_req_o[1]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.634048 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001011 ; + + /* Other user defined attributes. */ + original_pin : alert_req_o[1]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001011, 0.031191, 0.073104, 0.140232, 0.634048"); + values ( "0.054759, 0.128313, 0.213323, 0.349457, 1.341047",\ + "0.111579, 0.185344, 0.270112, 0.405873, 1.402083",\ + "0.250250, 0.333539, 0.418248, 0.553913, 1.548154",\ + "0.283987, 0.371683, 0.456312, 0.591852, 1.586834",\ + "0.585354, 0.727759, 0.813374, 0.950454, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001011, 0.031191, 0.073104, 0.140232, 0.634048"); + values ( "0.026541, 0.137190, 0.296770, 0.552376, 2.441059",\ + "0.027722, 0.137535, 0.296770, 0.552376, 2.442441",\ + "0.049082, 0.143999, 0.302126, 0.555458, 2.445574",\ + "0.056237, 0.147407, 0.304051, 0.555458, 2.445574",\ + "0.135291, 0.207889, 0.343014, 0.560034, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001011, 0.031191, 0.073104, 0.140232, 0.634048"); + values ( "0.074438, 0.127065, 0.181703, 0.269191, 0.901573",\ + "0.135357, 0.187983, 0.242503, 0.329807, 0.964298",\ + "0.278376, 0.331673, 0.386077, 0.473193, 1.104686",\ + "0.313854, 0.367693, 0.422104, 0.509231, 1.140694",\ + "0.637244, 0.700854, 0.755477, 0.842945, 1.478814"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001011, 0.031191, 0.073104, 0.140232, 0.634048"); + values ( "0.022386, 0.090122, 0.186194, 0.340109, 1.494298",\ + "0.022386, 0.090236, 0.186194, 0.340109, 1.494298",\ + "0.024466, 0.090482, 0.186194, 0.340109, 1.494298",\ + "0.025646, 0.090844, 0.186194, 0.340109, 1.494298",\ + "0.043418, 0.097585, 0.190427, 0.340109, 1.494298"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[1]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001011, 0.031191, 0.073104, 0.140232, 0.634048"); + values ( "0.054759, 0.128313, 0.213323, 0.349457, 1.341047",\ + "0.111579, 0.185344, 0.270112, 0.405873, 1.402083",\ + "0.250250, 0.333539, 0.418248, 0.553913, 1.548154",\ + "0.283987, 0.371683, 0.456312, 0.591852, 1.586834",\ + "0.585354, 0.727759, 0.813374, 0.950454, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001011, 0.031191, 0.073104, 0.140232, 0.634048"); + values ( "0.026541, 0.137190, 0.296764, 0.551818, 2.441059",\ + "0.027722, 0.137535, 0.296764, 0.551818, 2.442441",\ + "0.049082, 0.143999, 0.302126, 0.555040, 2.445574",\ + "0.056237, 0.147407, 0.304051, 0.555040, 2.445574",\ + "0.135291, 0.207889, 0.343014, 0.560034, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001011, 0.031191, 0.073104, 0.140232, 0.634048"); + values ( "0.074438, 0.127065, 0.181703, 0.269191, 0.901573",\ + "0.135357, 0.187983, 0.242503, 0.329807, 0.964298",\ + "0.278376, 0.331673, 0.386077, 0.473193, 1.104686",\ + "0.313854, 0.367693, 0.422104, 0.509231, 1.140694",\ + "0.637244, 0.700854, 0.755477, 0.842945, 1.478814"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001011, 0.031191, 0.073104, 0.140232, 0.634048"); + values ( "0.022386, 0.090122, 0.185722, 0.338326, 1.490226",\ + "0.022386, 0.090236, 0.185722, 0.338326, 1.490226",\ + "0.024466, 0.090482, 0.185722, 0.338326, 1.490226",\ + "0.025646, 0.090844, 0.186005, 0.338489, 1.490226",\ + "0.043418, 0.097585, 0.190427, 0.339240, 1.490226"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[1]_redg_min*/ + +} /* end of pin alert_req_o[1] */ + +pin("alert_req_o[0]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.634048 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000990 ; + + /* Other user defined attributes. */ + original_pin : alert_req_o[0]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000990, 0.031170, 0.073083, 0.140211, 0.634048"); + values ( "0.054663, 0.128270, 0.213280, 0.349414, 1.341047",\ + "0.111482, 0.185301, 0.270069, 0.405830, 1.402083",\ + "0.250105, 0.333496, 0.418205, 0.553870, 1.548154",\ + "0.283826, 0.371640, 0.456269, 0.591809, 1.586834",\ + "0.585026, 0.727716, 0.813330, 0.950411, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000990, 0.031170, 0.073083, 0.140211, 0.634048"); + values ( "0.026453, 0.137109, 0.296689, 0.552294, 2.441059",\ + "0.027638, 0.137454, 0.296689, 0.552294, 2.442441",\ + "0.049002, 0.143919, 0.302046, 0.555377, 2.445574",\ + "0.056155, 0.147327, 0.303971, 0.555377, 2.445574",\ + "0.135166, 0.207821, 0.342945, 0.559953, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000990, 0.031170, 0.073083, 0.140211, 0.634048"); + values ( "0.074369, 0.127040, 0.181679, 0.269167, 0.901576",\ + "0.135288, 0.187959, 0.242479, 0.329784, 0.964302",\ + "0.278302, 0.331649, 0.386053, 0.473170, 1.104690",\ + "0.313777, 0.367669, 0.422080, 0.509207, 1.140697",\ + "0.637128, 0.700830, 0.755452, 0.842922, 1.478818"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000990, 0.031170, 0.073083, 0.140211, 0.634048"); + values ( "0.022335, 0.090079, 0.186151, 0.340065, 1.494304",\ + "0.022335, 0.090194, 0.186151, 0.340065, 1.494304",\ + "0.024413, 0.090440, 0.186151, 0.340065, 1.494304",\ + "0.025595, 0.090802, 0.186151, 0.340065, 1.494304",\ + "0.043371, 0.097543, 0.190386, 0.340065, 1.494304"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[0]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000990, 0.031170, 0.073083, 0.140211, 0.634048"); + values ( "0.054663, 0.128270, 0.213280, 0.349414, 1.341047",\ + "0.111482, 0.185301, 0.270069, 0.405830, 1.402083",\ + "0.250105, 0.333496, 0.418205, 0.553870, 1.548154",\ + "0.283826, 0.371640, 0.456269, 0.591809, 1.586834",\ + "0.585026, 0.727716, 0.813330, 0.950411, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000990, 0.031170, 0.073083, 0.140211, 0.634048"); + values ( "0.026453, 0.137109, 0.296683, 0.551737, 2.441059",\ + "0.027638, 0.137454, 0.296683, 0.551737, 2.442441",\ + "0.049002, 0.143919, 0.302046, 0.554959, 2.445574",\ + "0.056155, 0.147327, 0.303971, 0.554959, 2.445574",\ + "0.135166, 0.207821, 0.342945, 0.559953, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000990, 0.031170, 0.073083, 0.140211, 0.634048"); + values ( "0.074369, 0.127040, 0.181679, 0.269167, 0.901576",\ + "0.135288, 0.187959, 0.242479, 0.329784, 0.964302",\ + "0.278302, 0.331649, 0.386053, 0.473170, 1.104690",\ + "0.313777, 0.367669, 0.422080, 0.509207, 1.140697",\ + "0.637128, 0.700830, 0.755452, 0.842922, 1.478818"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000990, 0.031170, 0.073083, 0.140211, 0.634048"); + values ( "0.022335, 0.090079, 0.185679, 0.338282, 1.490232",\ + "0.022335, 0.090194, 0.185679, 0.338282, 1.490232",\ + "0.024413, 0.090440, 0.185679, 0.338282, 1.490232",\ + "0.025595, 0.090802, 0.185963, 0.338445, 1.490232",\ + "0.043371, 0.097543, 0.190386, 0.339197, 1.490232"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[0]_redg_min*/ + +} /* end of pin alert_req_o[0] */ +} /* end of bus alert_req_o */ +bus ( dft_strap_test_i ) { + + bus_type : BUS3_type13 ; + direction : input ; + +pin("dft_strap_test_i[2]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001120 ; + + /* Other user defined attributes. */ + original_pin : dft_strap_test_i[2]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.478706, 0.503228, 0.581052, 0.648637, 1.079464",\ + "0.567148, 0.591670, 0.669494, 0.737079, 1.167906",\ + "0.650074, 0.674596, 0.752419, 0.820004, 1.250831",\ + "0.793078, 0.817600, 0.895423, 0.963008, 1.393835",\ + "1.032445, 1.056946, 1.134770, 1.202355, 1.633182"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.463301, 0.380673, 0.305530, 0.271812, 0.239120",\ + "0.556491, 0.473863, 0.398720, 0.365002, 0.332310",\ + "0.646873, 0.564245, 0.489102, 0.455384, 0.422692",\ + "0.811633, 0.729010, 0.653883, 0.620177, 0.587543",\ + "1.181053, 1.098457, 1.023414, 0.989768, 0.957438"); + } + + } /* end of arc clk_ast_tlul_i_dft_strap_test_i[2]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.265123, -0.222342, -0.186677, -0.161410, -0.033314",\ + "-0.347654, -0.304874, -0.269208, -0.243941, -0.115845",\ + "-0.437836, -0.395055, -0.359390, -0.334122, -0.206027",\ + "-0.606076, -0.563289, -0.527626, -0.502359, -0.374263",\ + "-0.890704, -0.847899, -0.812254, -0.786994, -0.658891"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.255864, -0.182785, -0.116647, -0.070567, 0.157553",\ + "-0.349537, -0.279942, -0.213805, -0.167724, 0.060396",\ + "-0.440910, -0.389678, -0.323541, -0.277461, -0.049341",\ + "-0.599026, -0.557614, -0.524142, -0.478056, -0.249871",\ + "-0.851183, -0.809770, -0.777053, -0.739869, -0.511712"); + } + + } /* end of arc clk_ast_tlul_i_dft_strap_test_i[2]_hldr*/ + +} /* end of pin dft_strap_test_i[2] */ + +pin("dft_strap_test_i[1]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001321 ; + + /* Other user defined attributes. */ + original_pin : dft_strap_test_i[1]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.428035, 0.345406, 0.276171, 0.259388, 0.254027",\ + "0.519710, 0.437082, 0.361939, 0.340063, 0.334702",\ + "0.618532, 0.535904, 0.460761, 0.427043, 0.420880",\ + "0.797361, 0.714733, 0.639590, 0.605872, 0.573180",\ + "1.098214, 1.015590, 0.940461, 0.906752, 0.874108"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.453520, 0.478042, 0.555866, 0.623451, 1.054278",\ + "0.538258, 0.562780, 0.640604, 0.708189, 1.139016",\ + "0.651889, 0.676378, 0.754202, 0.821787, 1.252614",\ + "0.864482, 0.889878, 0.967702, 1.035287, 1.466114",\ + "1.235476, 1.260812, 1.338683, 1.406288, 1.837127"); + } + + } /* end of arc clk_ast_tlul_i_dft_strap_test_i[1]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.221451, -0.180039, -0.147321, -0.110125, 0.118032",\ + "-0.314428, -0.273016, -0.240298, -0.203102, 0.025055",\ + "-0.409753, -0.368340, -0.335623, -0.298439, -0.070282",\ + "-0.551259, -0.508465, -0.472804, -0.447539, -0.236382",\ + "-0.757339, -0.714548, -0.679008, -0.653790, -0.510956"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.247877, -0.173125, -0.106987, -0.060907, 0.167213",\ + "-0.342789, -0.268037, -0.201899, -0.155819, 0.072301",\ + "-0.443799, -0.369047, -0.302909, -0.256829, -0.028709",\ + "-0.627085, -0.552322, -0.486182, -0.440095, -0.211908",\ + "-0.932472, -0.857684, -0.791539, -0.745437, -0.517093"); + } + + } /* end of arc clk_ast_tlul_i_dft_strap_test_i[1]_hldr*/ + +} /* end of pin dft_strap_test_i[1] */ + +pin("dft_strap_test_i[0]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000495 ; + + /* Other user defined attributes. */ + original_pin : dft_strap_test_i[0]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.476989, 0.501509, 0.579333, 0.646918, 1.077745",\ + "0.568510, 0.593031, 0.670855, 0.738440, 1.169267",\ + "0.663180, 0.687701, 0.765525, 0.833110, 1.263937",\ + "0.832054, 0.856556, 0.934380, 1.001965, 1.432792",\ + "1.118659, 1.143116, 1.220940, 1.288525, 1.719352"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.474663, 0.392034, 0.328853, 0.312070, 0.306709",\ + "0.571978, 0.489349, 0.424889, 0.408106, 0.402744",\ + "0.676749, 0.594121, 0.529069, 0.512287, 0.506925",\ + "0.856563, 0.773935, 0.708488, 0.691705, 0.686343",\ + "1.151508, 1.068880, 1.004139, 0.987361, 0.981971"); + } + + } /* end of arc clk_ast_tlul_i_dft_strap_test_i[0]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.289829, -0.215077, -0.148940, -0.102859, 0.125261",\ + "-0.385674, -0.310922, -0.244784, -0.198704, 0.029416",\ + "-0.484928, -0.410176, -0.344038, -0.297958, -0.069838",\ + "-0.657145, -0.582393, -0.516256, -0.470176, -0.242056",\ + "-0.943033, -0.868281, -0.802144, -0.756064, -0.527944"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.269424, -0.228012, -0.195294, -0.158099, 0.070058",\ + "-0.366945, -0.325532, -0.292815, -0.255619, -0.027462",\ + "-0.471935, -0.430523, -0.397805, -0.360610, -0.132453",\ + "-0.650169, -0.608757, -0.576039, -0.538849, -0.310692",\ + "-0.940386, -0.898973, -0.866256, -0.829075, -0.600918"); + } + + } /* end of arc clk_ast_tlul_i_dft_strap_test_i[0]_hldr*/ + +} /* end of pin dft_strap_test_i[0] */ +} /* end of bus dft_strap_test_i */ +bus ( lc_dft_en_i ) { + + bus_type : BUS4_type6 ; + direction : input ; + +pin("lc_dft_en_i[3]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000648 ; + + /* Other user defined attributes. */ + original_pin : lc_dft_en_i[3]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.116868, 0.046289, 0.009123, -0.011232, -0.072101",\ + "0.130035, 0.060315, 0.022495, 0.001866, -0.059037",\ + "0.171476, 0.101933, 0.064692, 0.043957, -0.021156",\ + "0.330098, 0.263569, 0.222296, 0.198239, 0.112987",\ + "0.772581, 0.713134, 0.646673, 0.609916, 0.496722"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.164832, 0.206226, 0.283518, 0.350873, 0.781571",\ + "0.176771, 0.218346, 0.296254, 0.363875, 0.794722",\ + "0.219963, 0.260510, 0.337961, 0.405191, 0.833567",\ + "0.396019, 0.435268, 0.507744, 0.571712, 0.985407",\ + "0.931350, 0.951153, 1.007354, 1.063861, 1.468564"); + } + + } /* end of arc clk_ast_tlul_i_lc_dft_en_i[3]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.015255, 0.029491, 0.060650, 0.081348, 0.176530",\ + "-0.028040, 0.015174, 0.046352, 0.067152, 0.163478",\ + "-0.067695, -0.029062, 0.006032, 0.028571, 0.126390",\ + "-0.170614, -0.143005, -0.113142, -0.091864, 0.016864",\ + "-0.388675, -0.412783, -0.403332, -0.388997, -0.262218"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.058687, -0.133819, -0.215174, -0.276149, -0.608913",\ + "-0.070579, -0.145649, -0.226804, -0.287545, -0.618487",\ + "-0.113780, -0.187774, -0.267897, -0.328130, -0.658063",\ + "-0.257059, -0.339271, -0.416614, -0.475103, -0.797794",\ + "-0.613549, -0.743897, -0.832843, -0.896262, -1.220625"); + } + + } /* end of arc clk_ast_tlul_i_lc_dft_en_i[3]_hldr*/ + +} /* end of pin lc_dft_en_i[3] */ + +pin("lc_dft_en_i[2]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001189 ; + + /* Other user defined attributes. */ + original_pin : lc_dft_en_i[2]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.200076, 0.146984, 0.107694, 0.091175, 0.087585",\ + "0.210849, 0.158775, 0.118789, 0.101895, 0.097230",\ + "0.247906, 0.195949, 0.156513, 0.139769, 0.134169",\ + "0.400793, 0.347442, 0.307665, 0.290788, 0.285288",\ + "0.811131, 0.757315, 0.714144, 0.695925, 0.691143"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.249331, 0.166333, 0.091045, 0.056957, 0.020498",\ + "0.258619, 0.175944, 0.100656, 0.066835, 0.033618",\ + "0.297457, 0.214925, 0.140086, 0.106583, 0.074986",\ + "0.472698, 0.388796, 0.312903, 0.278157, 0.236728",\ + "0.983325, 0.898854, 0.822917, 0.782684, 0.674795"); + } + + } /* end of arc clk_ast_tlul_i_lc_dft_en_i[2]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.096530, -0.053812, -0.018112, 0.007162, 0.135173",\ + "-0.107327, -0.064625, -0.028931, -0.003653, 0.124428",\ + "-0.144374, -0.101567, -0.065911, -0.040647, 0.087453",\ + "-0.286358, -0.243809, -0.210094, -0.185592, -0.057011",\ + "-0.620310, -0.578080, -0.553843, -0.534595, -0.422314"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.130907, -0.055165, 0.010770, 0.056779, 0.285045",\ + "-0.140562, -0.065848, 0.000282, 0.046339, 0.274227",\ + "-0.179341, -0.104491, -0.038333, 0.007805, 0.236523",\ + "-0.350407, -0.276449, -0.208169, -0.160590, 0.074989",\ + "-0.811364, -0.742478, -0.673228, -0.625268, -0.389923"); + } + + } /* end of arc clk_ast_tlul_i_lc_dft_en_i[2]_hldr*/ + +} /* end of pin lc_dft_en_i[2] */ + +pin("lc_dft_en_i[1]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000648 ; + + /* Other user defined attributes. */ + original_pin : lc_dft_en_i[1]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.116868, 0.046289, 0.009123, -0.011232, -0.072101",\ + "0.130035, 0.060315, 0.022495, 0.001866, -0.059037",\ + "0.171476, 0.101933, 0.064692, 0.043957, -0.021156",\ + "0.330098, 0.263569, 0.222296, 0.198239, 0.112987",\ + "0.772581, 0.713134, 0.646673, 0.609916, 0.496722"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.164832, 0.206226, 0.283518, 0.350873, 0.781571",\ + "0.176771, 0.218346, 0.296254, 0.363875, 0.794722",\ + "0.219963, 0.260510, 0.337961, 0.405191, 0.833567",\ + "0.396019, 0.435268, 0.507744, 0.571712, 0.985407",\ + "0.931350, 0.951153, 1.007354, 1.063861, 1.468564"); + } + + } /* end of arc clk_ast_tlul_i_lc_dft_en_i[1]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.015255, 0.029491, 0.060650, 0.081348, 0.176530",\ + "-0.028040, 0.015174, 0.046352, 0.067152, 0.163478",\ + "-0.067695, -0.029062, 0.006032, 0.028571, 0.126390",\ + "-0.170614, -0.143005, -0.113142, -0.091864, 0.016864",\ + "-0.388675, -0.412783, -0.403332, -0.388997, -0.262218"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.058687, -0.133819, -0.215174, -0.276149, -0.608913",\ + "-0.070579, -0.145649, -0.226804, -0.287545, -0.618487",\ + "-0.113780, -0.187774, -0.267897, -0.328130, -0.658063",\ + "-0.257059, -0.339271, -0.416614, -0.475103, -0.797794",\ + "-0.613549, -0.743897, -0.832843, -0.896262, -1.220625"); + } + + } /* end of arc clk_ast_tlul_i_lc_dft_en_i[1]_hldr*/ + +} /* end of pin lc_dft_en_i[1] */ + +pin("lc_dft_en_i[0]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001189 ; + + /* Other user defined attributes. */ + original_pin : lc_dft_en_i[0]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.200076, 0.146984, 0.107694, 0.091175, 0.087585",\ + "0.210849, 0.158775, 0.118789, 0.101895, 0.097230",\ + "0.247906, 0.195949, 0.156513, 0.139769, 0.134169",\ + "0.400793, 0.347442, 0.307665, 0.290788, 0.285288",\ + "0.811131, 0.757315, 0.714144, 0.695925, 0.691143"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.249331, 0.166333, 0.091045, 0.056957, 0.020498",\ + "0.258619, 0.175944, 0.100656, 0.066835, 0.033618",\ + "0.297457, 0.214925, 0.140086, 0.106583, 0.074986",\ + "0.472698, 0.388796, 0.312903, 0.278157, 0.236728",\ + "0.983325, 0.898854, 0.822917, 0.782684, 0.674795"); + } + + } /* end of arc clk_ast_tlul_i_lc_dft_en_i[0]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.096530, -0.053812, -0.018112, 0.007162, 0.135173",\ + "-0.107327, -0.064625, -0.028931, -0.003653, 0.124428",\ + "-0.144374, -0.101567, -0.065911, -0.040647, 0.087453",\ + "-0.286358, -0.243809, -0.210094, -0.185592, -0.057011",\ + "-0.620310, -0.578080, -0.553843, -0.534595, -0.422314"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.130907, -0.055165, 0.010770, 0.056779, 0.285045",\ + "-0.140562, -0.065848, 0.000282, 0.046339, 0.274227",\ + "-0.179341, -0.104491, -0.038333, 0.007805, 0.236523",\ + "-0.350407, -0.276449, -0.208169, -0.160590, 0.074989",\ + "-0.811364, -0.742478, -0.673228, -0.625268, -0.389923"); + } + + } /* end of arc clk_ast_tlul_i_lc_dft_en_i[0]_hldr*/ + +} /* end of pin lc_dft_en_i[0] */ +} /* end of bus lc_dft_en_i */ +bus ( fla_obs_i ) { + + bus_type : BUS8_type14 ; + direction : input ; + +pin("fla_obs_i[7]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000492 ; + + /* Other user defined attributes. */ + original_pin : fla_obs_i[7]; +} /* end of pin fla_obs_i[7] */ + +pin("fla_obs_i[6]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000492 ; + + /* Other user defined attributes. */ + original_pin : fla_obs_i[6]; +} /* end of pin fla_obs_i[6] */ + +pin("fla_obs_i[5]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000492 ; + + /* Other user defined attributes. */ + original_pin : fla_obs_i[5]; +} /* end of pin fla_obs_i[5] */ + +pin("fla_obs_i[4]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000492 ; + + /* Other user defined attributes. */ + original_pin : fla_obs_i[4]; +} /* end of pin fla_obs_i[4] */ + +pin("fla_obs_i[3]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000492 ; + + /* Other user defined attributes. */ + original_pin : fla_obs_i[3]; +} /* end of pin fla_obs_i[3] */ + +pin("fla_obs_i[2]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000492 ; + + /* Other user defined attributes. */ + original_pin : fla_obs_i[2]; +} /* end of pin fla_obs_i[2] */ + +pin("fla_obs_i[1]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000492 ; + + /* Other user defined attributes. */ + original_pin : fla_obs_i[1]; +} /* end of pin fla_obs_i[1] */ + +pin("fla_obs_i[0]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000492 ; + + /* Other user defined attributes. */ + original_pin : fla_obs_i[0]; +} /* end of pin fla_obs_i[0] */ +} /* end of bus fla_obs_i */ +bus ( otp_obs_i ) { + + bus_type : BUS8_type14 ; + direction : input ; + +pin("otp_obs_i[7]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000506 ; + + /* Other user defined attributes. */ + original_pin : otp_obs_i[7]; +} /* end of pin otp_obs_i[7] */ + +pin("otp_obs_i[6]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000506 ; + + /* Other user defined attributes. */ + original_pin : otp_obs_i[6]; +} /* end of pin otp_obs_i[6] */ + +pin("otp_obs_i[5]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000506 ; + + /* Other user defined attributes. */ + original_pin : otp_obs_i[5]; +} /* end of pin otp_obs_i[5] */ + +pin("otp_obs_i[4]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000506 ; + + /* Other user defined attributes. */ + original_pin : otp_obs_i[4]; +} /* end of pin otp_obs_i[4] */ + +pin("otp_obs_i[3]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000506 ; + + /* Other user defined attributes. */ + original_pin : otp_obs_i[3]; +} /* end of pin otp_obs_i[3] */ + +pin("otp_obs_i[2]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000506 ; + + /* Other user defined attributes. */ + original_pin : otp_obs_i[2]; +} /* end of pin otp_obs_i[2] */ + +pin("otp_obs_i[1]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000506 ; + + /* Other user defined attributes. */ + original_pin : otp_obs_i[1]; +} /* end of pin otp_obs_i[1] */ + +pin("otp_obs_i[0]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000506 ; + + /* Other user defined attributes. */ + original_pin : otp_obs_i[0]; +} /* end of pin otp_obs_i[0] */ +} /* end of bus otp_obs_i */ +bus ( otm_obs_i ) { + + bus_type : BUS8_type14 ; + direction : input ; + +pin("otm_obs_i[7]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000506 ; + + /* Other user defined attributes. */ + original_pin : otm_obs_i[7]; +} /* end of pin otm_obs_i[7] */ + +pin("otm_obs_i[6]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000506 ; + + /* Other user defined attributes. */ + original_pin : otm_obs_i[6]; +} /* end of pin otm_obs_i[6] */ + +pin("otm_obs_i[5]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000506 ; + + /* Other user defined attributes. */ + original_pin : otm_obs_i[5]; +} /* end of pin otm_obs_i[5] */ + +pin("otm_obs_i[4]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000506 ; + + /* Other user defined attributes. */ + original_pin : otm_obs_i[4]; +} /* end of pin otm_obs_i[4] */ + +pin("otm_obs_i[3]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000506 ; + + /* Other user defined attributes. */ + original_pin : otm_obs_i[3]; +} /* end of pin otm_obs_i[3] */ + +pin("otm_obs_i[2]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000506 ; + + /* Other user defined attributes. */ + original_pin : otm_obs_i[2]; +} /* end of pin otm_obs_i[2] */ + +pin("otm_obs_i[1]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000506 ; + + /* Other user defined attributes. */ + original_pin : otm_obs_i[1]; +} /* end of pin otm_obs_i[1] */ + +pin("otm_obs_i[0]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000492 ; + + /* Other user defined attributes. */ + original_pin : otm_obs_i[0]; +} /* end of pin otm_obs_i[0] */ +} /* end of bus otm_obs_i */ + +pin("usb_obs_i") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : usb_obs_i; +} /* end of pin usb_obs_i */ +bus ( obs_ctrl_o ) { + + bus_type : BUS12_type15 ; + direction : output ; + +pin("obs_ctrl_o[11]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.156168 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000605 ; + + /* Other user defined attributes. */ + original_pin : obs_ctrl_o[11]; + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[0]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.551399, 0.731602, 0.919092, 1.221084, 1.804596",\ + "0.583544, 0.763747, 0.951237, 1.253229, 1.836741",\ + "0.655451, 0.835654, 1.023144, 1.325136, 1.908648",\ + "0.911916, 1.092119, 1.279609, 1.581602, 2.165114",\ + "1.830892, 2.011095, 2.198585, 2.500578, 3.084090",\ + "0.636337, 0.816885, 1.005100, 1.307096, 1.890974",\ + "0.668482, 0.849030, 1.037246, 1.339242, 1.923120",\ + "0.740389, 0.920937, 1.109152, 1.411149, 1.995026",\ + "0.996855, 1.177402, 1.365618, 1.667614, 2.251492",\ + "1.915831, 2.096378, 2.284594, 2.586590, 3.170468",\ + "0.712249, 0.892328, 1.079909, 1.381693, 1.965147",\ + "0.744394, 0.924473, 1.112054, 1.413838, 1.997292",\ + "0.816301, 0.996380, 1.183961, 1.485745, 2.069199",\ + "1.072767, 1.252846, 1.440427, 1.742211, 2.325664",\ + "1.991743, 2.171822, 2.359403, 2.661187, 3.244640",\ + "0.766618, 0.946840, 1.134560, 1.436233, 2.019464",\ + "0.798764, 0.978985, 1.166705, 1.468378, 2.051609",\ + "0.870670, 1.050892, 1.238612, 1.540285, 2.123516",\ + "1.127136, 1.307358, 1.495078, 1.796751, 2.379982",\ + "2.046112, 2.226333, 2.414054, 2.715726, 3.298958",\ + "1.048213, 1.232108, 1.418511, 1.719959, 2.302742",\ + "1.080358, 1.264253, 1.450656, 1.752105, 2.334887",\ + "1.152265, 1.336160, 1.522563, 1.824011, 2.406794",\ + "1.408731, 1.592625, 1.779028, 2.080477, 2.663259",\ + "2.327707, 2.511601, 2.698004, 2.999453, 3.582235"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.034926, 0.034926, 0.034926, 0.034926, 0.034926",\ + "0.080177, 0.080177, 0.080177, 0.080177, 0.080177",\ + "0.211196, 0.211196, 0.211196, 0.211196, 0.211196",\ + "0.703322, 0.703322, 0.703322, 0.703322, 0.703322",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\ + "0.034926, 0.034926, 0.034926, 0.034926, 0.034926",\ + "0.080177, 0.080177, 0.080177, 0.080177, 0.080177",\ + "0.211196, 0.211196, 0.211196, 0.211196, 0.211196",\ + "0.703322, 0.703322, 0.703322, 0.703322, 0.703322",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\ + "0.034926, 0.034926, 0.034926, 0.034926, 0.034926",\ + "0.080177, 0.080177, 0.080177, 0.080177, 0.080177",\ + "0.211196, 0.211196, 0.211196, 0.211196, 0.211196",\ + "0.703322, 0.703322, 0.703322, 0.703322, 0.703322",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\ + "0.034926, 0.034926, 0.034926, 0.034926, 0.034926",\ + "0.080177, 0.080177, 0.080177, 0.080177, 0.080177",\ + "0.211196, 0.211196, 0.211196, 0.211196, 0.211196",\ + "0.703322, 0.703322, 0.703322, 0.703322, 0.703322",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\ + "0.034926, 0.034926, 0.034926, 0.034926, 0.034926",\ + "0.080177, 0.080177, 0.080177, 0.080177, 0.080177",\ + "0.211196, 0.211196, 0.211196, 0.211196, 0.211196",\ + "0.703322, 0.703322, 0.703322, 0.703322, 0.703322",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.410192, 0.677978, 0.939558, 1.379255, 2.258650",\ + "0.437946, 0.705732, 0.967312, 1.407009, 2.286404",\ + "0.489378, 0.757164, 1.018744, 1.458441, 2.337836",\ + "0.655862, 0.923647, 1.185227, 1.624924, 2.504319",\ + "1.246932, 1.514718, 1.776298, 2.215995, 3.095390",\ + "0.498896, 0.766053, 1.028199, 1.467484, 2.346055",\ + "0.526650, 0.793807, 1.055953, 1.495238, 2.373809",\ + "0.578082, 0.845239, 1.107385, 1.546670, 2.425241",\ + "0.744566, 1.011722, 1.273868, 1.713154, 2.591724",\ + "1.335636, 1.602793, 1.864939, 2.304224, 3.182795",\ + "0.591838, 0.859198, 1.119924, 1.559648, 2.439097",\ + "0.619592, 0.886952, 1.147678, 1.587402, 2.466851",\ + "0.671024, 0.938384, 1.199110, 1.638834, 2.518283",\ + "0.837508, 1.104867, 1.365594, 1.805318, 2.684766",\ + "1.428578, 1.695938, 1.956664, 2.396388, 3.275837",\ + "0.657682, 0.927762, 1.186944, 1.626498, 2.505608",\ + "0.685436, 0.955516, 1.214698, 1.654252, 2.533362",\ + "0.736868, 1.006948, 1.266130, 1.705685, 2.584794",\ + "0.903352, 1.173432, 1.432614, 1.872168, 2.751277",\ + "1.494422, 1.764502, 2.023684, 2.463239, 3.342348",\ + "1.004203, 1.308598, 1.557607, 1.995652, 2.871743",\ + "1.031957, 1.336352, 1.585361, 2.023406, 2.899497",\ + "1.083390, 1.387784, 1.636793, 2.074838, 2.950930",\ + "1.249873, 1.554267, 1.803276, 2.241322, 3.117413",\ + "1.840944, 2.145338, 2.394347, 2.832392, 3.708484"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.036752, 0.036752, 0.036752, 0.036752, 0.036752",\ + "0.066655, 0.066655, 0.066655, 0.066655, 0.066655",\ + "0.142207, 0.142207, 0.142207, 0.142207, 0.142207",\ + "0.440316, 0.440316, 0.440316, 0.440316, 0.440316",\ + "1.523676, 1.523676, 1.523676, 1.523676, 1.523677",\ + "0.036752, 0.036752, 0.036752, 0.036752, 0.036752",\ + "0.066655, 0.066655, 0.066655, 0.066655, 0.066655",\ + "0.142207, 0.142207, 0.142207, 0.142207, 0.142207",\ + "0.440316, 0.440316, 0.440316, 0.440316, 0.440316",\ + "1.523676, 1.523676, 1.523676, 1.523676, 1.523677",\ + "0.036752, 0.036752, 0.036752, 0.036752, 0.036752",\ + "0.066655, 0.066655, 0.066655, 0.066655, 0.066655",\ + "0.142207, 0.142207, 0.142207, 0.142207, 0.142207",\ + "0.440316, 0.440316, 0.440316, 0.440316, 0.440316",\ + "1.523676, 1.523676, 1.523676, 1.523676, 1.523677",\ + "0.036752, 0.036752, 0.036752, 0.036752, 0.036752",\ + "0.066655, 0.066655, 0.066655, 0.066655, 0.066655",\ + "0.142207, 0.142207, 0.142207, 0.142207, 0.142207",\ + "0.440316, 0.440316, 0.440316, 0.440316, 0.440316",\ + "1.523676, 1.523676, 1.523676, 1.523676, 1.523677",\ + "0.036752, 0.036752, 0.036752, 0.036752, 0.036752",\ + "0.066655, 0.066655, 0.066655, 0.066655, 0.066655",\ + "0.142207, 0.142207, 0.142207, 0.142207, 0.142207",\ + "0.440316, 0.440316, 0.440316, 0.440316, 0.440316",\ + "1.523676, 1.523676, 1.523676, 1.523676, 1.523677"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[11]_redg_2706*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[1]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.459504, 0.723077, 0.999350, 1.468080, 2.405539",\ + "0.491649, 0.755223, 1.031495, 1.500225, 2.437684",\ + "0.563556, 0.827130, 1.103402, 1.572132, 2.509591",\ + "0.820022, 1.083595, 1.359868, 1.828597, 2.766056",\ + "1.738997, 2.002571, 2.278844, 2.747575, 3.685036",\ + "0.547698, 0.810618, 1.086918, 1.554795, 2.491473",\ + "0.579843, 0.842764, 1.119063, 1.586940, 2.523618",\ + "0.651750, 0.914670, 1.190970, 1.658847, 2.595525",\ + "0.908216, 1.171136, 1.447435, 1.915312, 2.851990",\ + "1.827192, 2.090112, 2.366412, 2.834290, 3.770969",\ + "0.636014, 0.899599, 1.174883, 1.642418, 2.578428",\ + "0.668159, 0.931744, 1.207028, 1.674563, 2.610573",\ + "0.740066, 1.003651, 1.278935, 1.746470, 2.682480",\ + "0.996532, 1.260116, 1.535400, 2.002935, 2.938945",\ + "1.915508, 2.179092, 2.454377, 2.921913, 3.857924",\ + "0.698510, 0.965234, 1.239022, 1.706331, 2.641937",\ + "0.730655, 0.997379, 1.271168, 1.738477, 2.674082",\ + "0.802562, 1.069286, 1.343075, 1.810383, 2.745989",\ + "1.059028, 1.325751, 1.599540, 2.066849, 3.002454",\ + "1.978004, 2.244727, 2.518517, 2.985826, 3.921433",\ + "1.027636, 1.329564, 1.590890, 2.055681, 2.987393",\ + "1.059781, 1.361710, 1.623035, 2.087826, 3.019538",\ + "1.131688, 1.433616, 1.694942, 2.159733, 3.091445",\ + "1.388154, 1.690082, 1.951407, 2.416198, 3.347910",\ + "2.307129, 2.609058, 2.870384, 3.335176, 4.266890"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.034926, 0.034926, 0.034926, 0.034926, 0.034925",\ + "0.080177, 0.080177, 0.080177, 0.080177, 0.080177",\ + "0.211196, 0.211196, 0.211196, 0.211195, 0.211195",\ + "0.703322, 0.703322, 0.703321, 0.703320, 0.703316",\ + "2.463890, 2.463890, 2.463889, 2.463887, 2.463883",\ + "0.034926, 0.034926, 0.034926, 0.034926, 0.034925",\ + "0.080177, 0.080177, 0.080177, 0.080177, 0.080177",\ + "0.211196, 0.211196, 0.211196, 0.211195, 0.211195",\ + "0.703322, 0.703322, 0.703321, 0.703320, 0.703316",\ + "2.463890, 2.463890, 2.463889, 2.463887, 2.463883",\ + "0.034926, 0.034926, 0.034926, 0.034926, 0.034925",\ + "0.080177, 0.080177, 0.080177, 0.080177, 0.080177",\ + "0.211196, 0.211196, 0.211196, 0.211195, 0.211195",\ + "0.703322, 0.703322, 0.703321, 0.703320, 0.703316",\ + "2.463890, 2.463890, 2.463889, 2.463887, 2.463883",\ + "0.034926, 0.034926, 0.034926, 0.034926, 0.034925",\ + "0.080177, 0.080177, 0.080177, 0.080177, 0.080177",\ + "0.211196, 0.211196, 0.211196, 0.211195, 0.211195",\ + "0.703322, 0.703322, 0.703321, 0.703320, 0.703316",\ + "2.463890, 2.463890, 2.463889, 2.463887, 2.463883",\ + "0.034926, 0.034926, 0.034926, 0.034926, 0.034925",\ + "0.080177, 0.080177, 0.080177, 0.080177, 0.080177",\ + "0.211196, 0.211196, 0.211196, 0.211195, 0.211195",\ + "0.703322, 0.703322, 0.703321, 0.703320, 0.703316",\ + "2.463890, 2.463890, 2.463889, 2.463887, 2.463883"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.393145, 0.575577, 0.771969, 1.081022, 1.675830",\ + "0.420899, 0.603331, 0.799723, 1.108776, 1.703585",\ + "0.472331, 0.654763, 0.851155, 1.160208, 1.755017",\ + "0.638815, 0.821247, 1.017638, 1.326692, 1.921499",\ + "1.229885, 1.412317, 1.608709, 1.917762, 2.512568",\ + "0.480560, 0.662962, 0.859462, 1.168327, 1.763184",\ + "0.508314, 0.690716, 0.887216, 1.196081, 1.790938",\ + "0.559746, 0.742149, 0.938648, 1.247514, 1.842370",\ + "0.726229, 0.908632, 1.105132, 1.413997, 2.008852",\ + "1.317300, 1.499703, 1.696202, 2.005067, 2.599921",\ + "0.561436, 0.743299, 0.939489, 1.248356, 1.843215",\ + "0.589190, 0.771053, 0.967243, 1.276110, 1.870970",\ + "0.640622, 0.822485, 1.018675, 1.327542, 1.922402",\ + "0.807106, 0.988969, 1.185158, 1.494025, 2.088884",\ + "1.398176, 1.580039, 1.776229, 2.085095, 2.679953",\ + "0.619083, 0.800848, 0.997033, 1.305601, 1.899863",\ + "0.646837, 0.828601, 1.024787, 1.333355, 1.927617",\ + "0.698269, 0.880034, 1.076219, 1.384787, 1.979049",\ + "0.864752, 1.046517, 1.242702, 1.551270, 2.145531",\ + "1.455823, 1.637588, 1.833773, 2.142340, 2.736601",\ + "0.921290, 1.106072, 1.300666, 1.608616, 2.201710",\ + "0.949044, 1.133826, 1.328420, 1.636370, 2.229464",\ + "1.000476, 1.185258, 1.379853, 1.687802, 2.280896",\ + "1.166960, 1.351742, 1.546336, 1.854285, 2.447378",\ + "1.758030, 1.942812, 2.137407, 2.445355, 3.038447"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.036752, 0.036752, 0.036752, 0.036752, 0.036751",\ + "0.066655, 0.066655, 0.066655, 0.066654, 0.066652",\ + "0.142207, 0.142207, 0.142207, 0.142207, 0.142207",\ + "0.440316, 0.440316, 0.440316, 0.440316, 0.440315",\ + "1.523676, 1.523676, 1.523676, 1.523676, 1.523674",\ + "0.036752, 0.036752, 0.036752, 0.036752, 0.036751",\ + "0.066655, 0.066655, 0.066655, 0.066654, 0.066652",\ + "0.142207, 0.142207, 0.142207, 0.142207, 0.142207",\ + "0.440316, 0.440316, 0.440316, 0.440316, 0.440315",\ + "1.523676, 1.523676, 1.523676, 1.523676, 1.523674",\ + "0.036752, 0.036752, 0.036752, 0.036752, 0.036751",\ + "0.066655, 0.066655, 0.066655, 0.066654, 0.066652",\ + "0.142207, 0.142207, 0.142207, 0.142207, 0.142207",\ + "0.440316, 0.440316, 0.440316, 0.440316, 0.440315",\ + "1.523676, 1.523676, 1.523676, 1.523676, 1.523674",\ + "0.036752, 0.036752, 0.036752, 0.036752, 0.036751",\ + "0.066655, 0.066655, 0.066655, 0.066654, 0.066652",\ + "0.142207, 0.142207, 0.142207, 0.142207, 0.142207",\ + "0.440316, 0.440316, 0.440316, 0.440316, 0.440315",\ + "1.523676, 1.523676, 1.523676, 1.523676, 1.523674",\ + "0.036752, 0.036752, 0.036752, 0.036752, 0.036751",\ + "0.066655, 0.066655, 0.066655, 0.066654, 0.066652",\ + "0.142207, 0.142207, 0.142207, 0.142207, 0.142207",\ + "0.440316, 0.440316, 0.440316, 0.440316, 0.440315",\ + "1.523676, 1.523676, 1.523676, 1.523676, 1.523674"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[11]_redg_2637*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[2]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.455529, 0.715158, 0.987030, 1.443910, 2.357670",\ + "0.487674, 0.747303, 1.019175, 1.476055, 2.389815",\ + "0.559581, 0.819210, 1.091082, 1.547962, 2.461721",\ + "0.816046, 1.075675, 1.347547, 1.804427, 2.718186",\ + "1.735022, 1.994652, 2.266525, 2.723405, 3.637166",\ + "0.543634, 0.802691, 1.074561, 1.530625, 2.443603",\ + "0.575779, 0.834837, 1.106706, 1.562770, 2.475748",\ + "0.647686, 0.906743, 1.178613, 1.634677, 2.547655",\ + "0.904151, 1.163209, 1.435078, 1.891142, 2.804120",\ + "1.823127, 2.082185, 2.354055, 2.810120, 3.723099",\ + "0.631664, 0.891657, 1.162525, 1.618248, 2.530558",\ + "0.663809, 0.923802, 1.194670, 1.650393, 2.562703",\ + "0.735716, 0.995709, 1.266577, 1.722300, 2.634610",\ + "0.992181, 1.252175, 1.523042, 1.978765, 2.891075",\ + "1.911157, 2.171151, 2.442019, 2.897743, 3.810054",\ + "0.693885, 0.957271, 1.226663, 1.682162, 2.594067",\ + "0.726030, 0.989416, 1.258808, 1.714307, 2.626212",\ + "0.797937, 1.061323, 1.330715, 1.786214, 2.698119",\ + "1.054402, 1.317788, 1.587180, 2.042679, 2.954584",\ + "1.973378, 2.236765, 2.506157, 2.961657, 3.873563",\ + "1.021272, 1.321346, 1.578410, 2.031462, 2.939523",\ + "1.053417, 1.353491, 1.610555, 2.063607, 2.971668",\ + "1.125324, 1.425398, 1.682462, 2.135514, 3.043575",\ + "1.381790, 1.681863, 1.938927, 2.391979, 3.300040",\ + "2.300766, 2.600840, 2.857904, 3.310957, 4.219019"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.034926, 0.034926, 0.034926, 0.034926, 0.034925",\ + "0.080177, 0.080177, 0.080177, 0.080177, 0.080177",\ + "0.211196, 0.211196, 0.211196, 0.211195, 0.211195",\ + "0.703322, 0.703322, 0.703321, 0.703318, 0.703312",\ + "2.463890, 2.463890, 2.463888, 2.463885, 2.463879",\ + "0.034926, 0.034926, 0.034926, 0.034926, 0.034925",\ + "0.080177, 0.080177, 0.080177, 0.080177, 0.080177",\ + "0.211196, 0.211196, 0.211196, 0.211195, 0.211195",\ + "0.703322, 0.703322, 0.703321, 0.703318, 0.703312",\ + "2.463890, 2.463890, 2.463888, 2.463885, 2.463879",\ + "0.034926, 0.034926, 0.034926, 0.034926, 0.034925",\ + "0.080177, 0.080177, 0.080177, 0.080177, 0.080177",\ + "0.211196, 0.211196, 0.211196, 0.211195, 0.211195",\ + "0.703322, 0.703322, 0.703321, 0.703318, 0.703312",\ + "2.463890, 2.463890, 2.463888, 2.463885, 2.463879",\ + "0.034926, 0.034926, 0.034926, 0.034926, 0.034925",\ + "0.080177, 0.080177, 0.080177, 0.080177, 0.080177",\ + "0.211196, 0.211196, 0.211196, 0.211195, 0.211195",\ + "0.703322, 0.703322, 0.703321, 0.703318, 0.703312",\ + "2.463890, 2.463890, 2.463888, 2.463885, 2.463879",\ + "0.034926, 0.034926, 0.034926, 0.034926, 0.034925",\ + "0.080177, 0.080177, 0.080177, 0.080177, 0.080177",\ + "0.211196, 0.211196, 0.211196, 0.211195, 0.211195",\ + "0.703322, 0.703322, 0.703321, 0.703318, 0.703312",\ + "2.463890, 2.463889, 2.463888, 2.463885, 2.463879"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.391484, 0.574025, 0.770279, 1.079497, 1.674793",\ + "0.419237, 0.601779, 0.798033, 1.107251, 1.702548",\ + "0.470670, 0.653211, 0.849465, 1.158683, 1.753979",\ + "0.637153, 0.819694, 1.015949, 1.325166, 1.920461",\ + "1.228224, 1.410765, 1.607020, 1.916236, 2.511531",\ + "0.478904, 0.661410, 0.857772, 1.166802, 1.762147",\ + "0.506657, 0.689164, 0.885526, 1.194556, 1.789901",\ + "0.558090, 0.740596, 0.936958, 1.245988, 1.841333",\ + "0.724573, 0.907080, 1.103442, 1.412471, 2.007815",\ + "1.315644, 1.498150, 1.694512, 2.003541, 2.598884",\ + "0.559771, 0.741747, 0.937799, 1.246830, 1.842178",\ + "0.587525, 0.769501, 0.965553, 1.274584, 1.869933",\ + "0.638957, 0.820933, 1.016985, 1.326016, 1.921365",\ + "0.805441, 0.987416, 1.183469, 1.492499, 2.087847",\ + "1.396511, 1.578487, 1.774539, 2.083570, 2.678916",\ + "0.617410, 0.799295, 0.995343, 1.304075, 1.898826",\ + "0.645164, 0.827049, 1.023097, 1.331829, 1.926580",\ + "0.696596, 0.878481, 1.074529, 1.383261, 1.978012",\ + "0.863080, 1.044965, 1.241013, 1.549745, 2.144494",\ + "1.454150, 1.636036, 1.832083, 2.140815, 2.735564",\ + "0.919505, 1.104522, 1.298977, 1.607090, 2.200673",\ + "0.947259, 1.132276, 1.326731, 1.634844, 2.228427",\ + "0.998691, 1.183708, 1.378163, 1.686276, 2.279859",\ + "1.165175, 1.350191, 1.544647, 1.852759, 2.446341",\ + "1.756245, 1.941262, 2.135717, 2.443830, 3.037410"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.036752, 0.036752, 0.036752, 0.036752, 0.036751",\ + "0.066655, 0.066655, 0.066655, 0.066654, 0.066651",\ + "0.142207, 0.142207, 0.142207, 0.142207, 0.142207",\ + "0.440316, 0.440316, 0.440316, 0.440316, 0.440315",\ + "1.523676, 1.523676, 1.523676, 1.523676, 1.523674",\ + "0.036752, 0.036752, 0.036752, 0.036752, 0.036751",\ + "0.066655, 0.066655, 0.066655, 0.066654, 0.066651",\ + "0.142207, 0.142207, 0.142207, 0.142207, 0.142207",\ + "0.440316, 0.440316, 0.440316, 0.440316, 0.440315",\ + "1.523676, 1.523676, 1.523676, 1.523676, 1.523674",\ + "0.036752, 0.036752, 0.036752, 0.036752, 0.036751",\ + "0.066655, 0.066655, 0.066655, 0.066654, 0.066651",\ + "0.142207, 0.142207, 0.142207, 0.142207, 0.142207",\ + "0.440316, 0.440316, 0.440316, 0.440316, 0.440315",\ + "1.523676, 1.523676, 1.523676, 1.523676, 1.523674",\ + "0.036752, 0.036752, 0.036752, 0.036752, 0.036751",\ + "0.066655, 0.066655, 0.066655, 0.066654, 0.066651",\ + "0.142207, 0.142207, 0.142207, 0.142207, 0.142207",\ + "0.440316, 0.440316, 0.440316, 0.440316, 0.440315",\ + "1.523676, 1.523676, 1.523676, 1.523676, 1.523674",\ + "0.036752, 0.036752, 0.036752, 0.036752, 0.036751",\ + "0.066655, 0.066655, 0.066655, 0.066654, 0.066651",\ + "0.142207, 0.142207, 0.142207, 0.142207, 0.142207",\ + "0.440316, 0.440316, 0.440316, 0.440316, 0.440315",\ + "1.523676, 1.523676, 1.523676, 1.523676, 1.523674"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[11]_redg_2582*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[3]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.547812, 0.726239, 0.906500, 1.192706, 1.743823",\ + "0.579958, 0.758384, 0.938645, 1.224851, 1.775968",\ + "0.651865, 0.830291, 1.010552, 1.296758, 1.847875",\ + "0.908330, 1.086757, 1.267017, 1.553223, 2.104340",\ + "1.827306, 2.005733, 2.185993, 2.472199, 3.023317",\ + "0.632751, 0.811512, 0.992415, 1.278626, 1.830201",\ + "0.664896, 0.843657, 1.024560, 1.310771, 1.862346",\ + "0.736803, 0.915564, 1.096467, 1.382678, 1.934253",\ + "0.993268, 1.172029, 1.352932, 1.639144, 2.190719",\ + "1.912244, 2.091005, 2.271908, 2.558120, 3.109695",\ + "0.708657, 0.886955, 1.067224, 1.353223, 1.904374",\ + "0.740802, 0.919100, 1.099369, 1.385368, 1.936519",\ + "0.812709, 0.991007, 1.171276, 1.457275, 2.008426",\ + "1.069174, 1.247472, 1.427741, 1.713740, 2.264891",\ + "1.988150, 2.166448, 2.346717, 2.632716, 3.183867",\ + "0.763009, 0.941467, 1.121875, 1.407763, 1.958691",\ + "0.795154, 0.973612, 1.154020, 1.439908, 1.990836",\ + "0.867061, 1.045519, 1.225927, 1.511815, 2.062743",\ + "1.123527, 1.301984, 1.482392, 1.768280, 2.319208",\ + "2.042502, 2.220960, 2.401368, 2.687256, 3.238184",\ + "1.044431, 1.226694, 1.405825, 1.691489, 2.241968",\ + "1.076576, 1.258839, 1.437970, 1.723634, 2.274114",\ + "1.148483, 1.330746, 1.509877, 1.795541, 2.346020",\ + "1.404948, 1.587211, 1.766343, 2.052006, 2.602486",\ + "2.323924, 2.506187, 2.685318, 2.970983, 3.521462"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.034926, 0.034926, 0.034926, 0.034926, 0.034926",\ + "0.080177, 0.080177, 0.080177, 0.080177, 0.080177",\ + "0.211196, 0.211196, 0.211196, 0.211196, 0.211196",\ + "0.703322, 0.703322, 0.703322, 0.703322, 0.703322",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\ + "0.034926, 0.034926, 0.034926, 0.034926, 0.034926",\ + "0.080177, 0.080177, 0.080177, 0.080177, 0.080177",\ + "0.211196, 0.211196, 0.211196, 0.211196, 0.211196",\ + "0.703322, 0.703322, 0.703322, 0.703322, 0.703322",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\ + "0.034926, 0.034926, 0.034926, 0.034926, 0.034926",\ + "0.080177, 0.080177, 0.080177, 0.080177, 0.080177",\ + "0.211196, 0.211196, 0.211196, 0.211196, 0.211196",\ + "0.703322, 0.703322, 0.703322, 0.703322, 0.703322",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\ + "0.034926, 0.034926, 0.034926, 0.034926, 0.034926",\ + "0.080177, 0.080177, 0.080177, 0.080177, 0.080177",\ + "0.211196, 0.211196, 0.211196, 0.211196, 0.211196",\ + "0.703322, 0.703322, 0.703322, 0.703322, 0.703322",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\ + "0.034926, 0.034926, 0.034926, 0.034926, 0.034926",\ + "0.080177, 0.080177, 0.080177, 0.080177, 0.080177",\ + "0.211196, 0.211196, 0.211196, 0.211196, 0.211196",\ + "0.703322, 0.703322, 0.703322, 0.703322, 0.703322",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.408756, 0.673926, 0.933128, 1.369310, 2.241675",\ + "0.436510, 0.701680, 0.960881, 1.397064, 2.269429",\ + "0.487942, 0.753112, 1.012314, 1.448496, 2.320861",\ + "0.654426, 0.919595, 1.178797, 1.614980, 2.487345",\ + "1.245496, 1.510666, 1.769868, 2.206050, 3.078415",\ + "0.497422, 0.762001, 1.021768, 1.457539, 2.329080",\ + "0.525175, 0.789755, 1.049522, 1.485293, 2.356834",\ + "0.576608, 0.841187, 1.100955, 1.536725, 2.408266",\ + "0.743091, 1.007670, 1.267438, 1.703208, 2.574750",\ + "1.334162, 1.598741, 1.858509, 2.294279, 3.165820",\ + "0.590228, 0.855124, 1.113494, 1.549703, 2.422122",\ + "0.617982, 0.882878, 1.141248, 1.577457, 2.449876",\ + "0.669414, 0.934310, 1.192680, 1.628889, 2.501308",\ + "0.835898, 1.100793, 1.359163, 1.795373, 2.667792",\ + "1.426969, 1.691864, 1.950234, 2.386443, 3.258862",\ + "0.655951, 0.923658, 1.180514, 1.616553, 2.488633",\ + "0.683705, 0.951412, 1.208267, 1.644307, 2.516387",\ + "0.735137, 1.002844, 1.259700, 1.695739, 2.567819",\ + "0.901620, 1.169327, 1.426183, 1.862223, 2.734303",\ + "1.492691, 1.760398, 2.017254, 2.453294, 3.325373",\ + "1.001740, 1.304156, 1.551144, 1.985685, 2.854766",\ + "1.029494, 1.331910, 1.578898, 2.013438, 2.882520",\ + "1.080926, 1.383342, 1.630330, 2.064871, 2.933952",\ + "1.247410, 1.549826, 1.796813, 2.231354, 3.100436",\ + "1.838480, 2.140896, 2.387884, 2.822425, 3.691506"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.036752, 0.036752, 0.036752, 0.036752, 0.036752",\ + "0.066655, 0.066655, 0.066655, 0.066655, 0.066655",\ + "0.142207, 0.142207, 0.142207, 0.142207, 0.142207",\ + "0.440316, 0.440316, 0.440316, 0.440316, 0.440316",\ + "1.523676, 1.523676, 1.523676, 1.523676, 1.523677",\ + "0.036752, 0.036752, 0.036752, 0.036752, 0.036752",\ + "0.066655, 0.066655, 0.066655, 0.066655, 0.066655",\ + "0.142207, 0.142207, 0.142207, 0.142207, 0.142207",\ + "0.440316, 0.440316, 0.440316, 0.440316, 0.440316",\ + "1.523676, 1.523676, 1.523676, 1.523676, 1.523677",\ + "0.036752, 0.036752, 0.036752, 0.036752, 0.036752",\ + "0.066655, 0.066655, 0.066655, 0.066655, 0.066655",\ + "0.142207, 0.142207, 0.142207, 0.142207, 0.142207",\ + "0.440316, 0.440316, 0.440316, 0.440316, 0.440316",\ + "1.523676, 1.523676, 1.523676, 1.523676, 1.523677",\ + "0.036752, 0.036752, 0.036752, 0.036752, 0.036752",\ + "0.066655, 0.066655, 0.066655, 0.066655, 0.066655",\ + "0.142207, 0.142207, 0.142207, 0.142207, 0.142207",\ + "0.440316, 0.440316, 0.440316, 0.440316, 0.440316",\ + "1.523676, 1.523676, 1.523676, 1.523676, 1.523677",\ + "0.036752, 0.036752, 0.036752, 0.036752, 0.036752",\ + "0.066655, 0.066655, 0.066655, 0.066655, 0.066655",\ + "0.142207, 0.142207, 0.142207, 0.142207, 0.142207",\ + "0.440316, 0.440316, 0.440316, 0.440316, 0.440316",\ + "1.523676, 1.523676, 1.523676, 1.523676, 1.523677"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[11]_redg_2520*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + values ( "0.315086, 0.347231, 0.419138, 0.675604, 1.594576",\ + "0.402477, 0.434622, 0.506529, 0.762995, 1.681967",\ + "0.483396, 0.515541, 0.587448, 0.843914, 1.762885",\ + "0.541136, 0.573281, 0.645189, 0.901655, 1.820624",\ + "0.843842, 0.875987, 0.947895, 1.204361, 2.123326"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + values ( "0.034927, 0.080178, 0.211197, 0.703303, 2.463871",\ + "0.034927, 0.080178, 0.211262, 0.703303, 2.463871",\ + "0.034927, 0.080178, 0.211506, 0.703303, 2.463871",\ + "0.034928, 0.080178, 0.211506, 0.703303, 2.463871",\ + "0.035124, 0.080207, 0.211847, 0.703316, 2.463884"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + values ( "0.288640, 0.316394, 0.367826, 0.534309, 1.125380",\ + "0.376032, 0.403786, 0.455218, 0.621702, 1.212772",\ + "0.456902, 0.484656, 0.536088, 0.702571, 1.293642",\ + "0.514551, 0.542304, 0.593737, 0.760220, 1.351291",\ + "0.817630, 0.845638, 0.897452, 1.064344, 1.655102"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + values ( "0.036752, 0.066655, 0.142211, 0.440316, 1.524426",\ + "0.036752, 0.066655, 0.142211, 0.440316, 1.524426",\ + "0.036752, 0.066655, 0.142211, 0.440316, 1.524300",\ + "0.036752, 0.066655, 0.142211, 0.440316, 1.524064",\ + "0.036746, 0.066581, 0.142211, 0.440310, 1.523676"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[11]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[0]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.499182, 0.679295, 0.866874, 1.168853, 1.751950",\ + "0.529816, 0.709930, 0.897508, 1.199488, 1.782584",\ + "0.601083, 0.781197, 0.968775, 1.270755, 1.853851",\ + "0.856808, 1.036922, 1.224500, 1.526480, 2.109576",\ + "1.774034, 1.954148, 2.141726, 2.443706, 3.026802",\ + "0.584120, 0.764131, 0.951944, 1.254360, 1.838328",\ + "0.614754, 0.794765, 0.982578, 1.284994, 1.868962",\ + "0.686022, 0.866033, 1.053846, 1.356261, 1.940230",\ + "0.941746, 1.121757, 1.309570, 1.611986, 2.195954",\ + "1.858973, 2.038984, 2.226796, 2.529212, 3.113181",\ + "0.660032, 0.839574, 1.026753, 1.328956, 1.912500",\ + "0.690666, 0.870209, 1.057387, 1.359591, 1.943135",\ + "0.761934, 0.941476, 1.128654, 1.430858, 2.014402",\ + "1.017658, 1.197201, 1.384379, 1.686583, 2.270127",\ + "1.934885, 2.114427, 2.301605, 2.603809, 3.187353",\ + "0.714401, 0.894326, 1.081641, 1.383562, 1.966818",\ + "0.745036, 0.924960, 1.112276, 1.414196, 1.997452",\ + "0.816303, 0.996228, 1.183543, 1.485464, 2.068719",\ + "1.072027, 1.251952, 1.439268, 1.741188, 2.324444",\ + "1.989254, 2.169178, 2.356494, 2.658415, 3.241670",\ + "0.995996, 1.179891, 1.365817, 1.667288, 2.250095",\ + "1.026630, 1.210525, 1.396451, 1.697923, 2.280730",\ + "1.097898, 1.281793, 1.467719, 1.769190, 2.351997",\ + "1.353622, 1.537517, 1.723443, 2.024915, 2.607721",\ + "2.270849, 2.454743, 2.640669, 2.942141, 3.524948"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.031515, 0.031515, 0.031515, 0.031515, 0.031515",\ + "0.077660, 0.077660, 0.077660, 0.077660, 0.077660",\ + "0.209649, 0.209649, 0.209649, 0.209649, 0.209649",\ + "0.699350, 0.699350, 0.699350, 0.699350, 0.699350",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\ + "0.031515, 0.031515, 0.031515, 0.031515, 0.031515",\ + "0.077660, 0.077660, 0.077660, 0.077660, 0.077660",\ + "0.209649, 0.209649, 0.209649, 0.209649, 0.209649",\ + "0.699350, 0.699350, 0.699350, 0.699350, 0.699350",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\ + "0.031515, 0.031515, 0.031515, 0.031515, 0.031515",\ + "0.077660, 0.077660, 0.077660, 0.077660, 0.077660",\ + "0.209649, 0.209649, 0.209649, 0.209649, 0.209649",\ + "0.699350, 0.699350, 0.699350, 0.699350, 0.699350",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\ + "0.031515, 0.031515, 0.031515, 0.031515, 0.031515",\ + "0.077660, 0.077660, 0.077660, 0.077660, 0.077660",\ + "0.209649, 0.209649, 0.209649, 0.209649, 0.209649",\ + "0.699350, 0.699350, 0.699350, 0.699350, 0.699350",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\ + "0.031515, 0.031515, 0.031515, 0.031515, 0.031515",\ + "0.077660, 0.077660, 0.077660, 0.077660, 0.077660",\ + "0.209649, 0.209649, 0.209649, 0.209649, 0.209649",\ + "0.699350, 0.699350, 0.699350, 0.699350, 0.699350",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.382273, 0.649883, 0.911284, 1.351061, 2.230222",\ + "0.407140, 0.674750, 0.936142, 1.375888, 2.254987",\ + "0.455457, 0.723068, 0.984460, 1.424205, 2.303304",\ + "0.620747, 0.888357, 1.149749, 1.589495, 2.468594",\ + "1.214576, 1.482187, 1.743588, 2.183365, 3.062526",\ + "0.470977, 0.737958, 0.999925, 1.439290, 2.317627",\ + "0.495844, 0.762825, 1.024783, 1.464117, 2.342392",\ + "0.544161, 0.811142, 1.073101, 1.512434, 2.390709",\ + "0.709451, 0.976432, 1.238390, 1.677724, 2.555999",\ + "1.303280, 1.570262, 1.832229, 2.271594, 3.149931",\ + "0.563919, 0.831278, 1.091970, 1.531536, 2.410669",\ + "0.588786, 0.856145, 1.116828, 1.556363, 2.435434",\ + "0.637103, 0.904463, 1.165145, 1.604680, 2.483751",\ + "0.802393, 1.069752, 1.330435, 1.769970, 2.649041",\ + "1.396222, 1.663582, 1.924273, 2.363840, 3.242973",\ + "0.629763, 0.899843, 1.159026, 1.598547, 2.477591",\ + "0.654629, 0.924710, 1.183884, 1.623374, 2.502355",\ + "0.702947, 0.973027, 1.232201, 1.671691, 2.550673",\ + "0.868237, 1.138317, 1.397491, 1.836981, 2.715962",\ + "1.462066, 1.732146, 1.991329, 2.430851, 3.309894",\ + "0.976284, 1.280678, 1.529696, 1.967773, 2.843926",\ + "1.001151, 1.305545, 1.554554, 1.992599, 2.868690",\ + "1.049468, 1.353863, 1.602872, 2.040917, 2.917008",\ + "1.214758, 1.519152, 1.768161, 2.206207, 3.082298",\ + "1.808588, 2.112982, 2.362000, 2.800076, 3.676230"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.028581, 0.028581, 0.028581, 0.028581, 0.028581",\ + "0.057562, 0.057562, 0.057562, 0.057562, 0.057562",\ + "0.134857, 0.134857, 0.134857, 0.134857, 0.134857",\ + "0.435749, 0.435749, 0.435749, 0.435749, 0.435750",\ + "1.519015, 1.519015, 1.519015, 1.519015, 1.519015",\ + "0.028581, 0.028581, 0.028581, 0.028581, 0.028581",\ + "0.057562, 0.057562, 0.057562, 0.057562, 0.057562",\ + "0.134857, 0.134857, 0.134857, 0.134857, 0.134857",\ + "0.435749, 0.435749, 0.435749, 0.435749, 0.435750",\ + "1.519015, 1.519015, 1.519015, 1.519015, 1.519015",\ + "0.028581, 0.028581, 0.028581, 0.028581, 0.028581",\ + "0.057562, 0.057562, 0.057562, 0.057562, 0.057562",\ + "0.134857, 0.134857, 0.134857, 0.134857, 0.134857",\ + "0.435749, 0.435749, 0.435749, 0.435749, 0.435750",\ + "1.519015, 1.519015, 1.519015, 1.519015, 1.519015",\ + "0.028581, 0.028581, 0.028581, 0.028581, 0.028581",\ + "0.057562, 0.057562, 0.057562, 0.057562, 0.057562",\ + "0.134857, 0.134857, 0.134857, 0.134857, 0.134857",\ + "0.435749, 0.435749, 0.435749, 0.435749, 0.435750",\ + "1.519015, 1.519015, 1.519015, 1.519015, 1.519015",\ + "0.028581, 0.028581, 0.028581, 0.028581, 0.028581",\ + "0.057562, 0.057562, 0.057562, 0.057562, 0.057562",\ + "0.134857, 0.134857, 0.134857, 0.134857, 0.134857",\ + "0.435749, 0.435749, 0.435749, 0.435749, 0.435750",\ + "1.519015, 1.519015, 1.519015, 1.519015, 1.519015"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[11]_redg_min_2461*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[1]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.407290, 0.670821, 0.946941, 1.415072, 2.350076",\ + "0.437925, 0.701456, 0.977575, 1.445707, 2.380711",\ + "0.509192, 0.772723, 1.048843, 1.516974, 2.451978",\ + "0.764916, 1.028448, 1.304567, 1.772699, 2.707703",\ + "1.682143, 1.945674, 2.221793, 2.689925, 3.624929",\ + "0.495484, 0.758362, 1.034508, 1.501788, 2.436010",\ + "0.526119, 0.788996, 1.065142, 1.532422, 2.466645",\ + "0.597386, 0.860264, 1.136409, 1.603690, 2.537912",\ + "0.853111, 1.115988, 1.392134, 1.859414, 2.793636",\ + "1.770337, 2.033214, 2.309360, 2.776640, 3.710862",\ + "0.583800, 0.847341, 1.122472, 1.589428, 2.522965",\ + "0.614435, 0.877976, 1.153107, 1.620063, 2.553600",\ + "0.685702, 0.949243, 1.224374, 1.691330, 2.624867",\ + "0.941427, 1.204967, 1.480099, 1.947054, 2.880591",\ + "1.858653, 2.122194, 2.397325, 2.864281, 3.797817",\ + "0.646296, 0.912975, 1.186612, 1.653517, 2.586474",\ + "0.676931, 0.943609, 1.217247, 1.684151, 2.617109",\ + "0.748198, 1.014877, 1.288514, 1.755419, 2.688376",\ + "1.003923, 1.270601, 1.544238, 2.011143, 2.944100",\ + "1.921149, 2.187827, 2.461465, 2.928370, 3.861326",\ + "0.975422, 1.277290, 1.538476, 2.002961, 2.931930",\ + "1.006057, 1.307924, 1.569111, 2.033595, 2.962565",\ + "1.077324, 1.379191, 1.640378, 2.104863, 3.033832",\ + "1.333048, 1.634916, 1.896102, 2.360587, 3.289557",\ + "2.250275, 2.552142, 2.813329, 3.277813, 4.206782"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.031515, 0.031515, 0.031516, 0.031516, 0.031517",\ + "0.077660, 0.077660, 0.077660, 0.077660, 0.077660",\ + "0.209649, 0.209649, 0.209649, 0.209649, 0.209649",\ + "0.699350, 0.699350, 0.699350, 0.699349, 0.699348",\ + "2.448223, 2.448223, 2.448224, 2.448226, 2.448230",\ + "0.031515, 0.031515, 0.031516, 0.031516, 0.031517",\ + "0.077660, 0.077660, 0.077660, 0.077660, 0.077660",\ + "0.209649, 0.209649, 0.209649, 0.209649, 0.209649",\ + "0.699350, 0.699350, 0.699350, 0.699349, 0.699348",\ + "2.448223, 2.448223, 2.448224, 2.448226, 2.448230",\ + "0.031515, 0.031515, 0.031516, 0.031516, 0.031517",\ + "0.077660, 0.077660, 0.077660, 0.077660, 0.077660",\ + "0.209649, 0.209649, 0.209649, 0.209649, 0.209649",\ + "0.699350, 0.699350, 0.699350, 0.699349, 0.699348",\ + "2.448223, 2.448223, 2.448224, 2.448226, 2.448230",\ + "0.031515, 0.031515, 0.031516, 0.031516, 0.031517",\ + "0.077660, 0.077660, 0.077660, 0.077660, 0.077660",\ + "0.209649, 0.209649, 0.209649, 0.209649, 0.209649",\ + "0.699350, 0.699350, 0.699350, 0.699349, 0.699348",\ + "2.448223, 2.448223, 2.448224, 2.448226, 2.448230",\ + "0.031515, 0.031515, 0.031516, 0.031516, 0.031517",\ + "0.077660, 0.077660, 0.077660, 0.077660, 0.077660",\ + "0.209649, 0.209649, 0.209649, 0.209649, 0.209649",\ + "0.699350, 0.699350, 0.699350, 0.699349, 0.699348",\ + "2.448223, 2.448223, 2.448224, 2.448226, 2.448230"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.365228, 0.547285, 0.743519, 1.052700, 1.647184",\ + "0.390093, 0.572150, 0.768283, 1.077415, 1.671868",\ + "0.438410, 0.620468, 0.816601, 1.125732, 1.720186",\ + "0.603700, 0.785757, 0.981890, 1.291023, 1.885478",\ + "1.197531, 1.379589, 1.575822, 1.885003, 2.479486",\ + "0.452642, 0.634604, 0.830800, 1.140005, 1.734538",\ + "0.477507, 0.659469, 0.855564, 1.164720, 1.759222",\ + "0.525825, 0.707786, 0.903881, 1.213037, 1.807539",\ + "0.691115, 0.873076, 1.069171, 1.378328, 1.972831",\ + "1.284946, 1.466908, 1.663103, 1.972308, 2.566839",\ + "0.533519, 0.714940, 0.910827, 1.220034, 1.814569",\ + "0.558384, 0.739805, 0.935591, 1.244748, 1.839253",\ + "0.606701, 0.788123, 0.983908, 1.293066, 1.887571",\ + "0.771991, 0.953413, 1.149198, 1.458356, 2.052863",\ + "1.365822, 1.547244, 1.743130, 2.052336, 2.646871",\ + "0.591165, 0.772777, 0.968562, 1.277504, 1.871665",\ + "0.616030, 0.797642, 0.993326, 1.302219, 1.896349",\ + "0.664348, 0.845960, 1.041644, 1.350536, 1.944667",\ + "0.829637, 1.011249, 1.206933, 1.515826, 2.109958",\ + "1.423469, 1.605081, 1.800866, 2.109807, 2.703966",\ + "0.893373, 1.078154, 1.272226, 1.580711, 2.173983",\ + "0.918238, 1.103019, 1.296990, 1.605426, 2.198667",\ + "0.966555, 1.151337, 1.345307, 1.653743, 2.246984",\ + "1.131845, 1.316627, 1.510597, 1.819033, 2.412276",\ + "1.725676, 1.910458, 2.104529, 2.413014, 3.006285"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.028581, 0.028581, 0.028581, 0.028582, 0.028582",\ + "0.057562, 0.057562, 0.057562, 0.057563, 0.057564",\ + "0.134857, 0.134857, 0.134857, 0.134858, 0.134859",\ + "0.435749, 0.435749, 0.435750, 0.435755, 0.435768",\ + "1.519015, 1.519015, 1.519015, 1.519016, 1.519017",\ + "0.028581, 0.028581, 0.028581, 0.028582, 0.028582",\ + "0.057562, 0.057562, 0.057562, 0.057563, 0.057564",\ + "0.134857, 0.134857, 0.134857, 0.134858, 0.134859",\ + "0.435749, 0.435749, 0.435750, 0.435755, 0.435768",\ + "1.519015, 1.519015, 1.519015, 1.519016, 1.519017",\ + "0.028581, 0.028581, 0.028581, 0.028582, 0.028582",\ + "0.057562, 0.057562, 0.057562, 0.057563, 0.057564",\ + "0.134857, 0.134857, 0.134857, 0.134858, 0.134859",\ + "0.435749, 0.435749, 0.435750, 0.435755, 0.435768",\ + "1.519015, 1.519015, 1.519015, 1.519016, 1.519017",\ + "0.028581, 0.028581, 0.028581, 0.028582, 0.028582",\ + "0.057562, 0.057562, 0.057562, 0.057563, 0.057564",\ + "0.134857, 0.134857, 0.134857, 0.134858, 0.134859",\ + "0.435749, 0.435749, 0.435750, 0.435755, 0.435768",\ + "1.519015, 1.519015, 1.519015, 1.519016, 1.519017",\ + "0.028581, 0.028581, 0.028581, 0.028582, 0.028582",\ + "0.057562, 0.057562, 0.057562, 0.057563, 0.057564",\ + "0.134857, 0.134857, 0.134857, 0.134858, 0.134859",\ + "0.435749, 0.435749, 0.435750, 0.435755, 0.435768",\ + "1.519015, 1.519015, 1.519015, 1.519016, 1.519017"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[11]_redg_min_2383*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[2]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.403312, 0.662871, 0.934506, 1.390667, 2.301835",\ + "0.433946, 0.693506, 0.965141, 1.421302, 2.332470",\ + "0.505214, 0.764773, 1.036408, 1.492569, 2.403737",\ + "0.760938, 1.020497, 1.292132, 1.748294, 2.659461",\ + "1.678164, 1.937724, 2.209359, 2.665520, 3.576688",\ + "0.491417, 0.750404, 1.022035, 1.477383, 2.387769",\ + "0.522051, 0.781039, 1.052670, 1.508018, 2.418404",\ + "0.593319, 0.852306, 1.123937, 1.579285, 2.489671",\ + "0.849043, 1.108030, 1.379661, 1.835009, 2.745395",\ + "1.766269, 2.025257, 2.296888, 2.752235, 3.662621",\ + "0.579447, 0.839368, 1.109999, 1.565022, 2.474724",\ + "0.610081, 0.870003, 1.140634, 1.595656, 2.505359",\ + "0.681349, 0.941270, 1.211901, 1.666924, 2.576626",\ + "0.937073, 1.196995, 1.467626, 1.922648, 2.832350",\ + "1.854300, 2.114221, 2.384852, 2.839874, 3.749576",\ + "0.641668, 0.904980, 1.174137, 1.629096, 2.538233",\ + "0.672303, 0.935614, 1.204772, 1.659731, 2.568868",\ + "0.743570, 1.006881, 1.276039, 1.730998, 2.640135",\ + "0.999294, 1.262606, 1.531763, 1.986722, 2.895859",\ + "1.916521, 2.179832, 2.448990, 2.903949, 3.813085",\ + "0.969056, 1.269028, 1.525880, 1.978482, 2.883689",\ + "0.999690, 1.299663, 1.556514, 2.009117, 2.914324",\ + "1.070957, 1.370930, 1.627782, 2.080384, 2.985591",\ + "1.326682, 1.626654, 1.883506, 2.336109, 3.241315",\ + "2.243908, 2.543881, 2.800732, 3.253335, 4.158542"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.031515, 0.031515, 0.031516, 0.031517, 0.031519",\ + "0.077660, 0.077660, 0.077660, 0.077660, 0.077661",\ + "0.209649, 0.209649, 0.209649, 0.209649, 0.209649",\ + "0.699350, 0.699350, 0.699350, 0.699349, 0.699347",\ + "2.448223, 2.448223, 2.448225, 2.448228, 2.448234",\ + "0.031515, 0.031515, 0.031516, 0.031517, 0.031519",\ + "0.077660, 0.077660, 0.077660, 0.077660, 0.077661",\ + "0.209649, 0.209649, 0.209649, 0.209649, 0.209649",\ + "0.699350, 0.699350, 0.699350, 0.699349, 0.699347",\ + "2.448223, 2.448223, 2.448225, 2.448228, 2.448234",\ + "0.031515, 0.031515, 0.031516, 0.031517, 0.031519",\ + "0.077660, 0.077660, 0.077660, 0.077660, 0.077661",\ + "0.209649, 0.209649, 0.209649, 0.209649, 0.209649",\ + "0.699350, 0.699350, 0.699350, 0.699349, 0.699347",\ + "2.448223, 2.448223, 2.448225, 2.448228, 2.448234",\ + "0.031515, 0.031515, 0.031516, 0.031517, 0.031519",\ + "0.077660, 0.077660, 0.077660, 0.077660, 0.077661",\ + "0.209649, 0.209649, 0.209649, 0.209649, 0.209649",\ + "0.699350, 0.699350, 0.699350, 0.699349, 0.699347",\ + "2.448223, 2.448223, 2.448225, 2.448228, 2.448234",\ + "0.031515, 0.031515, 0.031516, 0.031517, 0.031519",\ + "0.077660, 0.077660, 0.077660, 0.077660, 0.077661",\ + "0.209649, 0.209649, 0.209649, 0.209649, 0.209649",\ + "0.699350, 0.699350, 0.699350, 0.699349, 0.699347",\ + "2.448223, 2.448223, 2.448225, 2.448228, 2.448234"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.363564, 0.545731, 0.741830, 1.051168, 1.646128",\ + "0.388431, 0.570598, 0.766595, 1.075888, 1.670830",\ + "0.436748, 0.618916, 0.814913, 1.124206, 1.719148",\ + "0.602038, 0.784206, 0.980202, 1.289496, 1.884440",\ + "1.195867, 1.378035, 1.574133, 1.883471, 2.478430",\ + "0.450984, 0.633050, 0.829111, 1.138473, 1.733482",\ + "0.475851, 0.657917, 0.853876, 1.163193, 1.758184",\ + "0.524168, 0.706235, 0.902193, 1.211511, 1.806502",\ + "0.689458, 0.871524, 1.067483, 1.376801, 1.971793",\ + "1.283288, 1.465354, 1.661414, 1.970776, 2.565784",\ + "0.531851, 0.713387, 0.909137, 1.218501, 1.813514",\ + "0.556719, 0.738254, 0.933903, 1.243222, 1.838215",\ + "0.605036, 0.786572, 0.982220, 1.291539, 1.886533",\ + "0.770326, 0.951861, 1.147510, 1.456830, 2.051825",\ + "1.364155, 1.545691, 1.741441, 2.050804, 2.645815",\ + "0.589490, 0.771224, 0.966873, 1.275972, 1.870610",\ + "0.614358, 0.796091, 0.991638, 1.300693, 1.895312",\ + "0.662675, 0.844408, 1.039955, 1.349010, 1.943630",\ + "0.827965, 1.009698, 1.205245, 1.514301, 2.108922",\ + "1.421794, 1.603527, 1.799176, 2.108275, 2.702911",\ + "0.891585, 1.076602, 1.270536, 1.579180, 2.172930",\ + "0.916453, 1.101469, 1.295302, 1.603900, 2.197631",\ + "0.964770, 1.149787, 1.343619, 1.652218, 2.245949",\ + "1.130060, 1.315076, 1.508909, 1.817508, 2.411241",\ + "1.723889, 1.908906, 2.102840, 2.411483, 3.005231"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.028581, 0.028581, 0.028581, 0.028582, 0.028582",\ + "0.057562, 0.057562, 0.057562, 0.057563, 0.057564",\ + "0.134857, 0.134857, 0.134857, 0.134858, 0.134859",\ + "0.435749, 0.435749, 0.435750, 0.435756, 0.435770",\ + "1.519015, 1.519015, 1.519015, 1.519016, 1.519017",\ + "0.028581, 0.028581, 0.028581, 0.028582, 0.028582",\ + "0.057562, 0.057562, 0.057562, 0.057563, 0.057564",\ + "0.134857, 0.134857, 0.134857, 0.134858, 0.134859",\ + "0.435749, 0.435749, 0.435750, 0.435756, 0.435770",\ + "1.519015, 1.519015, 1.519015, 1.519016, 1.519017",\ + "0.028581, 0.028581, 0.028581, 0.028582, 0.028582",\ + "0.057562, 0.057562, 0.057562, 0.057563, 0.057564",\ + "0.134857, 0.134857, 0.134857, 0.134858, 0.134859",\ + "0.435749, 0.435749, 0.435750, 0.435756, 0.435770",\ + "1.519015, 1.519015, 1.519015, 1.519016, 1.519017",\ + "0.028581, 0.028581, 0.028581, 0.028582, 0.028582",\ + "0.057562, 0.057562, 0.057562, 0.057563, 0.057564",\ + "0.134857, 0.134857, 0.134857, 0.134858, 0.134859",\ + "0.435749, 0.435749, 0.435750, 0.435756, 0.435770",\ + "1.519015, 1.519015, 1.519015, 1.519016, 1.519017",\ + "0.028581, 0.028581, 0.028581, 0.028582, 0.028582",\ + "0.057562, 0.057562, 0.057562, 0.057563, 0.057564",\ + "0.134857, 0.134857, 0.134857, 0.134858, 0.134859",\ + "0.435749, 0.435749, 0.435750, 0.435756, 0.435770",\ + "1.519015, 1.519015, 1.519015, 1.519016, 1.519017"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[11]_redg_min_2325*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[3]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.495595, 0.673935, 0.854281, 1.140468, 1.691221",\ + "0.526230, 0.704569, 0.884916, 1.171102, 1.721856",\ + "0.597497, 0.775836, 0.956183, 1.242370, 1.793123",\ + "0.853221, 1.031561, 1.211908, 1.498094, 2.048847",\ + "1.770448, 1.948787, 2.129134, 2.415321, 2.966074",\ + "0.580534, 0.758770, 0.939351, 1.225974, 1.777599",\ + "0.611168, 0.789405, 0.969986, 1.256609, 1.808234",\ + "0.682435, 0.860672, 1.041253, 1.327876, 1.879501",\ + "0.938160, 1.116397, 1.296978, 1.583601, 2.135226",\ + "1.855386, 2.033623, 2.214204, 2.500827, 3.052452",\ + "0.656440, 0.834214, 1.014160, 1.300571, 1.851772",\ + "0.687074, 0.864848, 1.044795, 1.331205, 1.882406",\ + "0.758341, 0.936116, 1.116062, 1.402473, 1.953674",\ + "1.014066, 1.191840, 1.371787, 1.658197, 2.209398",\ + "1.931292, 2.109066, 2.289013, 2.575424, 3.126625",\ + "0.710792, 0.888959, 1.069026, 1.355165, 1.906089",\ + "0.741426, 0.919594, 1.099660, 1.385799, 1.936724",\ + "0.812694, 0.990861, 1.170928, 1.457067, 2.007991",\ + "1.068418, 1.246586, 1.426652, 1.712791, 2.263715",\ + "1.985644, 2.163812, 2.343878, 2.630017, 3.180942",\ + "0.992214, 1.174477, 1.353179, 1.638891, 2.189367",\ + "1.022848, 1.205111, 1.383813, 1.669525, 2.220001",\ + "1.094115, 1.276379, 1.455081, 1.740793, 2.291269",\ + "1.349840, 1.532103, 1.710805, 1.996517, 2.546993",\ + "2.267066, 2.449329, 2.628031, 2.913743, 3.464219"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.031515, 0.031515, 0.031515, 0.031515, 0.031515",\ + "0.077660, 0.077660, 0.077660, 0.077660, 0.077660",\ + "0.209649, 0.209649, 0.209649, 0.209649, 0.209649",\ + "0.699350, 0.699350, 0.699350, 0.699350, 0.699350",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\ + "0.031515, 0.031515, 0.031515, 0.031515, 0.031515",\ + "0.077660, 0.077660, 0.077660, 0.077660, 0.077660",\ + "0.209649, 0.209649, 0.209649, 0.209649, 0.209649",\ + "0.699350, 0.699350, 0.699350, 0.699350, 0.699350",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\ + "0.031515, 0.031515, 0.031515, 0.031515, 0.031515",\ + "0.077660, 0.077660, 0.077660, 0.077660, 0.077660",\ + "0.209649, 0.209649, 0.209649, 0.209649, 0.209649",\ + "0.699350, 0.699350, 0.699350, 0.699350, 0.699350",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\ + "0.031515, 0.031515, 0.031515, 0.031515, 0.031515",\ + "0.077660, 0.077660, 0.077660, 0.077660, 0.077660",\ + "0.209649, 0.209649, 0.209649, 0.209649, 0.209649",\ + "0.699350, 0.699350, 0.699350, 0.699350, 0.699350",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\ + "0.031515, 0.031515, 0.031515, 0.031515, 0.031515",\ + "0.077660, 0.077660, 0.077660, 0.077660, 0.077660",\ + "0.209649, 0.209649, 0.209649, 0.209649, 0.209649",\ + "0.699350, 0.699350, 0.699350, 0.699350, 0.699350",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.380837, 0.645836, 0.904865, 1.341130, 2.213276",\ + "0.405704, 0.670703, 0.929723, 1.365952, 2.238030",\ + "0.454021, 0.719020, 0.978040, 1.414270, 2.286347",\ + "0.619311, 0.884310, 1.143330, 1.579559, 2.451637",\ + "1.213140, 1.478139, 1.737169, 2.173433, 3.045579",\ + "0.469502, 0.733911, 0.993506, 1.429358, 2.300681",\ + "0.494369, 0.758778, 1.018363, 1.454181, 2.325435",\ + "0.542686, 0.807095, 1.066681, 1.502498, 2.373752",\ + "0.707976, 0.972385, 1.231971, 1.667788, 2.539042",\ + "1.301806, 1.566214, 1.825810, 2.261662, 3.132985",\ + "0.562309, 0.827204, 1.085541, 1.521602, 2.393723",\ + "0.587176, 0.852071, 1.110399, 1.546425, 2.418477",\ + "0.635493, 0.900389, 1.158716, 1.594742, 2.466794",\ + "0.800783, 1.065678, 1.324006, 1.760032, 2.632084",\ + "1.394613, 1.659508, 1.917845, 2.353905, 3.226027",\ + "0.628031, 0.895738, 1.152596, 1.588608, 2.460633",\ + "0.652898, 0.920605, 1.177454, 1.613431, 2.485386",\ + "0.701216, 0.968923, 1.225771, 1.661748, 2.533704",\ + "0.866506, 1.134212, 1.391061, 1.827038, 2.698993",\ + "1.460335, 1.728042, 1.984900, 2.420912, 3.292936",\ + "0.973821, 1.276237, 1.523234, 1.957809, 2.826960",\ + "0.998688, 1.301104, 1.548091, 1.982632, 2.851713",\ + "1.047005, 1.349421, 1.596409, 2.030949, 2.900031",\ + "1.212295, 1.514711, 1.761698, 2.196239, 3.065320",\ + "1.806124, 2.108541, 2.355538, 2.790113, 3.659263"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.028581, 0.028581, 0.028581, 0.028581, 0.028581",\ + "0.057562, 0.057562, 0.057562, 0.057562, 0.057562",\ + "0.134857, 0.134857, 0.134857, 0.134857, 0.134857",\ + "0.435749, 0.435749, 0.435749, 0.435749, 0.435750",\ + "1.519015, 1.519015, 1.519015, 1.519015, 1.519015",\ + "0.028581, 0.028581, 0.028581, 0.028581, 0.028581",\ + "0.057562, 0.057562, 0.057562, 0.057562, 0.057562",\ + "0.134857, 0.134857, 0.134857, 0.134857, 0.134857",\ + "0.435749, 0.435749, 0.435749, 0.435749, 0.435750",\ + "1.519015, 1.519015, 1.519015, 1.519015, 1.519015",\ + "0.028581, 0.028581, 0.028581, 0.028581, 0.028581",\ + "0.057562, 0.057562, 0.057562, 0.057562, 0.057562",\ + "0.134857, 0.134857, 0.134857, 0.134857, 0.134857",\ + "0.435749, 0.435749, 0.435749, 0.435749, 0.435750",\ + "1.519015, 1.519015, 1.519015, 1.519015, 1.519015",\ + "0.028581, 0.028581, 0.028581, 0.028581, 0.028581",\ + "0.057562, 0.057562, 0.057562, 0.057562, 0.057562",\ + "0.134857, 0.134857, 0.134857, 0.134857, 0.134857",\ + "0.435749, 0.435749, 0.435749, 0.435749, 0.435750",\ + "1.519015, 1.519015, 1.519015, 1.519015, 1.519015",\ + "0.028581, 0.028581, 0.028581, 0.028581, 0.028581",\ + "0.057562, 0.057562, 0.057562, 0.057562, 0.057562",\ + "0.134857, 0.134857, 0.134857, 0.134857, 0.134857",\ + "0.435749, 0.435749, 0.435749, 0.435749, 0.435750",\ + "1.519015, 1.519015, 1.519015, 1.519015, 1.519015"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[11]_redg_min_2267*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + values ( "0.132999, 0.164048, 0.235821, 0.492102, 1.411098",\ + "0.221194, 0.252231, 0.324016, 0.580346, 1.499024",\ + "0.309537, 0.340556, 0.412339, 0.668869, 1.587106",\ + "0.372125, 0.403153, 0.474871, 0.731698, 1.650402",\ + "0.701985, 0.733051, 0.804557, 1.061823, 1.982165"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + values ( "0.031515, 0.077660, 0.209649, 0.699350, 2.448223",\ + "0.031515, 0.077660, 0.209649, 0.699350, 2.448223",\ + "0.031515, 0.077660, 0.209649, 0.699350, 2.448223",\ + "0.031515, 0.077660, 0.209649, 0.699350, 2.448223",\ + "0.031515, 0.077660, 0.209649, 0.699350, 2.448223"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + values ( "0.172647, 0.198025, 0.247447, 0.413179, 1.004020",\ + "0.260051, 0.285429, 0.334851, 0.500582, 1.091424",\ + "0.340949, 0.366324, 0.415751, 0.581486, 1.172337",\ + "0.398613, 0.423981, 0.473417, 0.639160, 1.230028",\ + "0.700957, 0.726326, 0.775791, 0.941604, 1.532645"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + values ( "0.028580, 0.057560, 0.134856, 0.434927, 1.516730",\ + "0.028580, 0.057560, 0.134856, 0.434927, 1.516730",\ + "0.028580, 0.057560, 0.134856, 0.434975, 1.516730",\ + "0.028580, 0.057560, 0.134856, 0.435062, 1.516730",\ + "0.028580, 0.057561, 0.134856, 0.435749, 1.516730"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[11]_redg_min*/ + + timing () { + related_pin : "padmux2ast_i[3]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + values ( "0.079929, 0.111758, 0.183223, 0.439138, 1.359203",\ + "0.167497, 0.199454, 0.270769, 0.526908, 1.444562",\ + "0.264286, 0.298668, 0.370756, 0.626584, 1.547694",\ + "0.439501, 0.480020, 0.554277, 0.809849, 1.732299",\ + "0.736451, 0.793429, 0.877676, 1.133252, 2.048527"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + values ( "0.033688, 0.079103, 0.210853, 0.705450, 2.481454",\ + "0.034938, 0.079398, 0.210853, 0.707160, 2.481454",\ + "0.042553, 0.084403, 0.210853, 0.707160, 2.481454",\ + "0.062025, 0.097740, 0.214926, 0.707160, 2.481454",\ + "0.107816, 0.136398, 0.233803, 0.707160, 2.481454"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + values ( "0.118927, 0.147104, 0.198913, 0.365810, 0.957538",\ + "0.198088, 0.226133, 0.277877, 0.444754, 1.035269",\ + "0.300437, 0.331131, 0.384010, 0.550764, 1.143163",\ + "0.474766, 0.514213, 0.573035, 0.741315, 1.332791",\ + "0.755439, 0.816369, 0.892028, 1.065959, 1.655414"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + values ( "0.037147, 0.066922, 0.142202, 0.440625, 1.525476",\ + "0.037147, 0.066922, 0.142202, 0.440625, 1.525476",\ + "0.046795, 0.072955, 0.144989, 0.440625, 1.525476",\ + "0.074873, 0.097054, 0.159133, 0.443319, 1.525476",\ + "0.131163, 0.155817, 0.206305, 0.453921, 1.527125"); + } + + } /* end of arc padmux2ast_i[3]_obs_ctrl_o[11]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[3]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + values ( "0.076002, 0.106508, 0.177677, 0.433841, 1.352120",\ + "0.163173, 0.193992, 0.265018, 0.521506, 1.439207",\ + "0.258934, 0.291253, 0.363111, 0.618813, 1.536303",\ + "0.430665, 0.469075, 0.541536, 0.798208, 1.718362",\ + "0.721771, 0.774421, 0.855976, 1.109381, 2.025527"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + values ( "0.030664, 0.077525, 0.209536, 0.696987, 2.440521",\ + "0.032038, 0.077878, 0.209536, 0.696987, 2.440521",\ + "0.038668, 0.082173, 0.210178, 0.699757, 2.449750",\ + "0.056119, 0.094147, 0.214335, 0.699757, 2.460771",\ + "0.095850, 0.132052, 0.230566, 0.703608, 2.462313"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + values ( "0.085902, 0.110542, 0.159236, 0.324759, 0.917124",\ + "0.171172, 0.195634, 0.244356, 0.409704, 1.001295",\ + "0.269100, 0.297524, 0.347992, 0.513168, 1.105193",\ + "0.434670, 0.473174, 0.529868, 0.695133, 1.285706",\ + "0.702119, 0.762927, 0.838318, 1.010679, 1.597765"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + values ( "0.029180, 0.058574, 0.135500, 0.435380, 1.519944",\ + "0.030330, 0.058789, 0.135664, 0.436655, 1.520555",\ + "0.042270, 0.067457, 0.139493, 0.437267, 1.520555",\ + "0.069987, 0.091747, 0.153270, 0.440379, 1.520568",\ + "0.124960, 0.149736, 0.200354, 0.450127, 1.523278"); + } + + } /* end of arc padmux2ast_i[3]_obs_ctrl_o[11]_una_min*/ + +} /* end of pin obs_ctrl_o[11] */ + +pin("obs_ctrl_o[10]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.156168 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002440 ; + + /* Other user defined attributes. */ + original_pin : obs_ctrl_o[10]; + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[0]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.570547, 0.750750, 0.938240, 1.240232, 1.823744",\ + "0.598946, 0.779149, 0.966639, 1.268632, 1.852144",\ + "0.670479, 0.850682, 1.038172, 1.340165, 1.923677",\ + "0.926915, 1.107118, 1.294608, 1.596601, 2.180113",\ + "1.830892, 2.011095, 2.198585, 2.500578, 3.084090",\ + "0.655485, 0.836033, 1.024249, 1.326245, 1.910123",\ + "0.683885, 0.864432, 1.052648, 1.354644, 1.938522",\ + "0.755418, 0.935965, 1.124181, 1.426177, 2.010055",\ + "1.011854, 1.192401, 1.380617, 1.682613, 2.266491",\ + "1.915831, 2.096378, 2.284594, 2.586590, 3.170468",\ + "0.731397, 0.911476, 1.099057, 1.400841, 1.984295",\ + "0.759797, 0.939876, 1.127457, 1.429241, 2.012694",\ + "0.831330, 1.011409, 1.198990, 1.500774, 2.084227",\ + "1.087766, 1.267845, 1.455426, 1.757210, 2.340663",\ + "1.991743, 2.171822, 2.359403, 2.661187, 3.244640",\ + "0.785767, 0.965988, 1.153708, 1.455381, 2.038612",\ + "0.814166, 0.994387, 1.182108, 1.483781, 2.067012",\ + "0.885699, 1.065920, 1.253641, 1.555314, 2.138545",\ + "1.142135, 1.322356, 1.510077, 1.811749, 2.394980",\ + "2.046112, 2.226333, 2.414054, 2.715726, 3.298958",\ + "1.067361, 1.251256, 1.437659, 1.739108, 2.321890",\ + "1.095761, 1.279655, 1.466058, 1.767507, 2.350289",\ + "1.167294, 1.351188, 1.537591, 1.839040, 2.421822",\ + "1.423730, 1.607624, 1.794027, 2.095476, 2.678258",\ + "2.327707, 2.511601, 2.698004, 2.999453, 3.582235"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.059998, 0.059998, 0.059998, 0.059998, 0.059998",\ + "0.108036, 0.108036, 0.108036, 0.108036, 0.108036",\ + "0.239906, 0.239906, 0.239906, 0.239906, 0.239906",\ + "0.732057, 0.732057, 0.732057, 0.732057, 0.732057",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\ + "0.059998, 0.059998, 0.059998, 0.059998, 0.059998",\ + "0.108036, 0.108036, 0.108036, 0.108036, 0.108036",\ + "0.239906, 0.239906, 0.239906, 0.239906, 0.239906",\ + "0.732057, 0.732057, 0.732057, 0.732057, 0.732057",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\ + "0.059998, 0.059998, 0.059998, 0.059998, 0.059998",\ + "0.108036, 0.108036, 0.108036, 0.108036, 0.108036",\ + "0.239906, 0.239906, 0.239906, 0.239906, 0.239906",\ + "0.732057, 0.732057, 0.732057, 0.732057, 0.732057",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\ + "0.059998, 0.059998, 0.059998, 0.059998, 0.059998",\ + "0.108036, 0.108036, 0.108036, 0.108036, 0.108036",\ + "0.239906, 0.239906, 0.239906, 0.239906, 0.239906",\ + "0.732057, 0.732057, 0.732057, 0.732057, 0.732057",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\ + "0.059998, 0.059998, 0.059998, 0.059998, 0.059998",\ + "0.108036, 0.108036, 0.108036, 0.108036, 0.108036",\ + "0.239906, 0.239906, 0.239906, 0.239906, 0.239906",\ + "0.732057, 0.732057, 0.732057, 0.732057, 0.732057",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.426873, 0.694659, 0.956239, 1.395936, 2.275331",\ + "0.448702, 0.716487, 0.978067, 1.417764, 2.297159",\ + "0.498842, 0.766628, 1.028208, 1.467905, 2.347300",\ + "0.665219, 0.933004, 1.194584, 1.634281, 2.513676",\ + "1.246642, 1.514428, 1.776008, 2.215705, 3.095100",\ + "0.515577, 0.782734, 1.044880, 1.484165, 2.362736",\ + "0.537406, 0.804562, 1.066708, 1.505994, 2.384564",\ + "0.587546, 0.854703, 1.116849, 1.556134, 2.434705",\ + "0.753923, 1.021079, 1.283225, 1.722511, 2.601081",\ + "1.335346, 1.602503, 1.864649, 2.303934, 3.182505",\ + "0.608520, 0.875879, 1.136606, 1.576329, 2.455778",\ + "0.630348, 0.897707, 1.158434, 1.598158, 2.477606",\ + "0.680488, 0.947848, 1.208574, 1.648298, 2.527747",\ + "0.846865, 1.114224, 1.374951, 1.814675, 2.694123",\ + "1.428288, 1.695648, 1.956374, 2.396098, 3.275547",\ + "0.674363, 0.944443, 1.203625, 1.643180, 2.522289",\ + "0.696192, 0.966272, 1.225454, 1.665008, 2.544117",\ + "0.746332, 1.016412, 1.275594, 1.715149, 2.594258",\ + "0.912709, 1.182789, 1.441971, 1.881525, 2.760634",\ + "1.494132, 1.764212, 2.023394, 2.462949, 3.342058",\ + "1.020885, 1.325279, 1.574288, 2.012334, 2.888425",\ + "1.042713, 1.347107, 1.596116, 2.034162, 2.910253",\ + "1.092854, 1.397248, 1.646257, 2.084302, 2.960393",\ + "1.259230, 1.563624, 1.812633, 2.250679, 3.126770",\ + "1.840654, 2.145048, 2.394057, 2.832103, 3.708194"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.053502, 0.053502, 0.053502, 0.053502, 0.053502",\ + "0.082236, 0.082236, 0.082236, 0.082236, 0.082235",\ + "0.159094, 0.159094, 0.159094, 0.159094, 0.159094",\ + "0.457392, 0.457392, 0.457392, 0.457392, 0.457392",\ + "1.523144, 1.523144, 1.523144, 1.523144, 1.523144",\ + "0.053502, 0.053502, 0.053502, 0.053502, 0.053502",\ + "0.082236, 0.082236, 0.082236, 0.082236, 0.082235",\ + "0.159094, 0.159094, 0.159094, 0.159094, 0.159094",\ + "0.457392, 0.457392, 0.457392, 0.457392, 0.457392",\ + "1.523144, 1.523144, 1.523144, 1.523144, 1.523144",\ + "0.053502, 0.053502, 0.053502, 0.053502, 0.053502",\ + "0.082236, 0.082236, 0.082236, 0.082236, 0.082235",\ + "0.159094, 0.159094, 0.159094, 0.159094, 0.159094",\ + "0.457392, 0.457392, 0.457392, 0.457392, 0.457392",\ + "1.523144, 1.523144, 1.523144, 1.523144, 1.523144",\ + "0.053502, 0.053502, 0.053502, 0.053502, 0.053502",\ + "0.082236, 0.082236, 0.082236, 0.082236, 0.082235",\ + "0.159094, 0.159094, 0.159094, 0.159094, 0.159094",\ + "0.457392, 0.457392, 0.457392, 0.457392, 0.457392",\ + "1.523144, 1.523144, 1.523144, 1.523144, 1.523144",\ + "0.053502, 0.053502, 0.053502, 0.053502, 0.053502",\ + "0.082236, 0.082236, 0.082236, 0.082236, 0.082235",\ + "0.159094, 0.159094, 0.159094, 0.159094, 0.159094",\ + "0.457392, 0.457392, 0.457392, 0.457392, 0.457392",\ + "1.523144, 1.523144, 1.523144, 1.523144, 1.523144"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[10]_redg_2689*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[1]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.478652, 0.742226, 1.018498, 1.487228, 2.424687",\ + "0.507052, 0.770625, 1.046898, 1.515627, 2.453087",\ + "0.578584, 0.842158, 1.118431, 1.587160, 2.524619",\ + "0.835020, 1.098594, 1.374866, 1.843596, 2.781055",\ + "1.738997, 2.002571, 2.278844, 2.747575, 3.685036",\ + "0.566846, 0.829767, 1.106066, 1.573943, 2.510621",\ + "0.595246, 0.858166, 1.134465, 1.602343, 2.539020",\ + "0.666779, 0.929699, 1.205998, 1.673875, 2.610553",\ + "0.923215, 1.186135, 1.462434, 1.930311, 2.866989",\ + "1.827192, 2.090112, 2.366412, 2.834290, 3.770969",\ + "0.655163, 0.918747, 1.194031, 1.661566, 2.597576",\ + "0.683562, 0.947146, 1.222430, 1.689965, 2.625975",\ + "0.755095, 1.018679, 1.293963, 1.761498, 2.697508",\ + "1.011531, 1.275115, 1.550399, 2.017934, 2.953944",\ + "1.915508, 2.179092, 2.454377, 2.921913, 3.857924",\ + "0.717659, 0.984382, 1.258171, 1.725480, 2.661085",\ + "0.746058, 1.012781, 1.286570, 1.753879, 2.689484",\ + "0.817591, 1.084314, 1.358103, 1.825412, 2.761017",\ + "1.074027, 1.340750, 1.614539, 2.081847, 3.017453",\ + "1.978004, 2.244727, 2.518517, 2.985826, 3.921433",\ + "1.046784, 1.348713, 1.610038, 2.074829, 3.006541",\ + "1.075184, 1.377112, 1.638437, 2.103229, 3.034940",\ + "1.146717, 1.448645, 1.709970, 2.174761, 3.106473",\ + "1.403152, 1.705081, 1.966406, 2.431197, 3.362909",\ + "2.307129, 2.609058, 2.870384, 3.335176, 4.266890"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.059998, 0.059998, 0.059998, 0.059998, 0.059998",\ + "0.108036, 0.108036, 0.108036, 0.108036, 0.108035",\ + "0.239906, 0.239906, 0.239905, 0.239905, 0.239905",\ + "0.732057, 0.732057, 0.732056, 0.732054, 0.732051",\ + "2.463890, 2.463890, 2.463889, 2.463887, 2.463883",\ + "0.059998, 0.059998, 0.059998, 0.059998, 0.059998",\ + "0.108036, 0.108036, 0.108036, 0.108036, 0.108035",\ + "0.239906, 0.239906, 0.239905, 0.239905, 0.239905",\ + "0.732057, 0.732057, 0.732056, 0.732054, 0.732051",\ + "2.463890, 2.463890, 2.463889, 2.463887, 2.463883",\ + "0.059998, 0.059998, 0.059998, 0.059998, 0.059998",\ + "0.108036, 0.108036, 0.108036, 0.108036, 0.108035",\ + "0.239906, 0.239906, 0.239905, 0.239905, 0.239905",\ + "0.732057, 0.732057, 0.732056, 0.732054, 0.732051",\ + "2.463890, 2.463890, 2.463889, 2.463887, 2.463883",\ + "0.059998, 0.059998, 0.059998, 0.059998, 0.059998",\ + "0.108036, 0.108036, 0.108036, 0.108036, 0.108035",\ + "0.239906, 0.239906, 0.239905, 0.239905, 0.239905",\ + "0.732057, 0.732057, 0.732056, 0.732054, 0.732051",\ + "2.463890, 2.463890, 2.463889, 2.463887, 2.463883",\ + "0.059998, 0.059998, 0.059998, 0.059998, 0.059998",\ + "0.108036, 0.108036, 0.108036, 0.108036, 0.108035",\ + "0.239906, 0.239906, 0.239905, 0.239905, 0.239905",\ + "0.732057, 0.732057, 0.732056, 0.732054, 0.732051",\ + "2.463890, 2.463890, 2.463889, 2.463887, 2.463883"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.409826, 0.592258, 0.788650, 1.097704, 1.692512",\ + "0.431655, 0.614087, 0.810479, 1.119532, 1.714340",\ + "0.481795, 0.664227, 0.860619, 1.169672, 1.764480",\ + "0.648172, 0.830604, 1.026996, 1.336049, 1.930856",\ + "1.229595, 1.412027, 1.608419, 1.917472, 2.512278",\ + "0.497241, 0.679644, 0.876143, 1.185009, 1.779865",\ + "0.519070, 0.701472, 0.897972, 1.206837, 1.801694",\ + "0.569210, 0.751613, 0.948112, 1.256977, 1.851834",\ + "0.735586, 0.917989, 1.114489, 1.423354, 2.018209",\ + "1.317010, 1.499413, 1.695912, 2.004777, 2.599632",\ + "0.578118, 0.759980, 0.956170, 1.265037, 1.859897",\ + "0.599946, 0.781809, 0.977999, 1.286866, 1.881726",\ + "0.650086, 0.831949, 1.028139, 1.337006, 1.931865",\ + "0.816463, 0.998326, 1.194516, 1.503382, 2.098241",\ + "1.397886, 1.579749, 1.775939, 2.084805, 2.679663",\ + "0.635764, 0.817529, 1.013714, 1.322282, 1.916544",\ + "0.657592, 0.839357, 1.035542, 1.344111, 1.938373",\ + "0.707733, 0.889498, 1.085683, 1.394251, 1.988513",\ + "0.874109, 1.055874, 1.252059, 1.560627, 2.154888",\ + "1.455533, 1.637298, 1.833483, 2.142051, 2.736311",\ + "0.937972, 1.122753, 1.317348, 1.625297, 2.218391",\ + "0.959800, 1.144582, 1.339176, 1.647125, 2.240220",\ + "1.009940, 1.194722, 1.389317, 1.697266, 2.290360",\ + "1.176317, 1.361099, 1.555693, 1.863642, 2.456735",\ + "1.757740, 1.942522, 2.137117, 2.445065, 3.038157"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.053502, 0.053502, 0.053502, 0.053501, 0.053499",\ + "0.082236, 0.082236, 0.082235, 0.082235, 0.082233",\ + "0.159095, 0.159095, 0.159095, 0.159095, 0.159095",\ + "0.457392, 0.457392, 0.457392, 0.457392, 0.457392",\ + "1.523144, 1.523144, 1.523144, 1.523144, 1.523142",\ + "0.053502, 0.053502, 0.053502, 0.053501, 0.053499",\ + "0.082236, 0.082236, 0.082235, 0.082235, 0.082233",\ + "0.159095, 0.159095, 0.159095, 0.159095, 0.159095",\ + "0.457392, 0.457392, 0.457392, 0.457392, 0.457392",\ + "1.523144, 1.523144, 1.523144, 1.523144, 1.523142",\ + "0.053502, 0.053502, 0.053502, 0.053501, 0.053499",\ + "0.082236, 0.082236, 0.082235, 0.082235, 0.082233",\ + "0.159095, 0.159095, 0.159095, 0.159095, 0.159095",\ + "0.457392, 0.457392, 0.457392, 0.457392, 0.457392",\ + "1.523144, 1.523144, 1.523144, 1.523144, 1.523142",\ + "0.053502, 0.053502, 0.053502, 0.053501, 0.053499",\ + "0.082236, 0.082236, 0.082235, 0.082235, 0.082233",\ + "0.159095, 0.159095, 0.159095, 0.159095, 0.159095",\ + "0.457392, 0.457392, 0.457392, 0.457392, 0.457392",\ + "1.523144, 1.523144, 1.523144, 1.523144, 1.523142",\ + "0.053502, 0.053502, 0.053502, 0.053501, 0.053499",\ + "0.082236, 0.082236, 0.082235, 0.082235, 0.082233",\ + "0.159095, 0.159095, 0.159095, 0.159095, 0.159095",\ + "0.457392, 0.457392, 0.457392, 0.457392, 0.457392",\ + "1.523144, 1.523144, 1.523144, 1.523144, 1.523142"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[10]_redg_2623*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[2]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.474677, 0.734306, 1.006178, 1.463058, 2.376818",\ + "0.503076, 0.762705, 1.034578, 1.491457, 2.405217",\ + "0.574609, 0.834238, 1.106111, 1.562990, 2.476750",\ + "0.831045, 1.090674, 1.362546, 1.819426, 2.733185",\ + "1.735022, 1.994652, 2.266525, 2.723405, 3.637166",\ + "0.562782, 0.821840, 1.093709, 1.549773, 2.462751",\ + "0.591181, 0.850239, 1.122108, 1.578173, 2.491151",\ + "0.662714, 0.921772, 1.193641, 1.649706, 2.562684",\ + "0.919150, 1.178208, 1.450077, 1.906141, 2.819119",\ + "1.823127, 2.082185, 2.354055, 2.810120, 3.723099",\ + "0.650812, 0.910805, 1.181673, 1.637396, 2.549706",\ + "0.679211, 0.939205, 1.210072, 1.665795, 2.578106",\ + "0.750744, 1.010738, 1.281605, 1.737328, 2.649639",\ + "1.007180, 1.267174, 1.538041, 1.993764, 2.906074",\ + "1.911157, 2.171151, 2.442019, 2.897743, 3.810054",\ + "0.713033, 0.976419, 1.245811, 1.701310, 2.613215",\ + "0.741432, 1.004818, 1.274210, 1.729709, 2.641615",\ + "0.812965, 1.076351, 1.345743, 1.801242, 2.713148",\ + "1.069401, 1.332787, 1.602179, 2.057678, 2.969583",\ + "1.973378, 2.236765, 2.506157, 2.961657, 3.873563",\ + "1.040421, 1.340494, 1.597558, 2.050611, 2.958672",\ + "1.068820, 1.368893, 1.625957, 2.079010, 2.987071",\ + "1.140353, 1.440426, 1.697490, 2.150543, 3.058604",\ + "1.396789, 1.696862, 1.953926, 2.406978, 3.315039",\ + "2.300766, 2.600840, 2.857904, 3.310957, 4.219019"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.059998, 0.059998, 0.059998, 0.059998, 0.059998",\ + "0.108036, 0.108036, 0.108036, 0.108036, 0.108035",\ + "0.239906, 0.239906, 0.239905, 0.239905, 0.239905",\ + "0.732057, 0.732057, 0.732056, 0.732053, 0.732046",\ + "2.463890, 2.463890, 2.463888, 2.463885, 2.463879",\ + "0.059998, 0.059998, 0.059998, 0.059998, 0.059998",\ + "0.108036, 0.108036, 0.108036, 0.108036, 0.108035",\ + "0.239906, 0.239906, 0.239905, 0.239905, 0.239905",\ + "0.732057, 0.732057, 0.732056, 0.732053, 0.732046",\ + "2.463890, 2.463890, 2.463888, 2.463885, 2.463879",\ + "0.059998, 0.059998, 0.059998, 0.059998, 0.059998",\ + "0.108036, 0.108036, 0.108036, 0.108036, 0.108035",\ + "0.239906, 0.239906, 0.239905, 0.239905, 0.239905",\ + "0.732057, 0.732057, 0.732056, 0.732053, 0.732046",\ + "2.463890, 2.463890, 2.463888, 2.463885, 2.463879",\ + "0.059998, 0.059998, 0.059998, 0.059998, 0.059998",\ + "0.108036, 0.108036, 0.108036, 0.108036, 0.108035",\ + "0.239906, 0.239906, 0.239905, 0.239905, 0.239905",\ + "0.732057, 0.732057, 0.732056, 0.732053, 0.732046",\ + "2.463890, 2.463890, 2.463888, 2.463885, 2.463879",\ + "0.059998, 0.059998, 0.059998, 0.059998, 0.059998",\ + "0.108036, 0.108036, 0.108036, 0.108036, 0.108035",\ + "0.239906, 0.239905, 0.239905, 0.239905, 0.239905",\ + "0.732057, 0.732057, 0.732056, 0.732053, 0.732046",\ + "2.463890, 2.463889, 2.463888, 2.463885, 2.463879"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.408165, 0.590706, 0.786961, 1.096178, 1.691475",\ + "0.429993, 0.612534, 0.808789, 1.118006, 1.713303",\ + "0.480134, 0.662675, 0.858930, 1.168147, 1.763443",\ + "0.646510, 0.829051, 1.025306, 1.334523, 1.929818",\ + "1.227934, 1.410475, 1.606730, 1.915946, 2.511241",\ + "0.495585, 0.678091, 0.874454, 1.183483, 1.778828",\ + "0.517413, 0.699920, 0.896282, 1.205312, 1.800657",\ + "0.567554, 0.750060, 0.946422, 1.255452, 1.850797",\ + "0.733930, 0.916437, 1.112799, 1.421828, 2.017172",\ + "1.315354, 1.497860, 1.694222, 2.003251, 2.598594",\ + "0.576453, 0.758428, 0.954480, 1.263512, 1.858860",\ + "0.598281, 0.780257, 0.976309, 1.285340, 1.880688",\ + "0.648421, 0.830397, 1.026449, 1.335480, 1.930828",\ + "0.814798, 0.996773, 1.192826, 1.501856, 2.097203",\ + "1.396221, 1.578197, 1.774249, 2.083280, 2.678626",\ + "0.634091, 0.815977, 1.012024, 1.320757, 1.915507",\ + "0.655920, 0.837805, 1.033853, 1.342585, 1.937336",\ + "0.706060, 0.887945, 1.083993, 1.392725, 1.987476",\ + "0.872437, 1.054322, 1.250370, 1.559102, 2.153851",\ + "1.453860, 1.635746, 1.831793, 2.140525, 2.735273",\ + "0.936187, 1.121203, 1.315658, 1.623772, 2.217354",\ + "0.958015, 1.143031, 1.337487, 1.645600, 2.239183",\ + "1.008155, 1.193172, 1.387627, 1.695740, 2.289323",\ + "1.174532, 1.359548, 1.554004, 1.862116, 2.455698",\ + "1.755955, 1.940972, 2.135427, 2.443540, 3.037120"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.053502, 0.053502, 0.053502, 0.053501, 0.053499",\ + "0.082236, 0.082236, 0.082235, 0.082234, 0.082232",\ + "0.159095, 0.159095, 0.159095, 0.159095, 0.159095",\ + "0.457392, 0.457392, 0.457392, 0.457392, 0.457392",\ + "1.523144, 1.523144, 1.523144, 1.523144, 1.523142",\ + "0.053502, 0.053502, 0.053502, 0.053501, 0.053499",\ + "0.082236, 0.082236, 0.082235, 0.082234, 0.082232",\ + "0.159095, 0.159095, 0.159095, 0.159095, 0.159095",\ + "0.457392, 0.457392, 0.457392, 0.457392, 0.457392",\ + "1.523144, 1.523144, 1.523144, 1.523144, 1.523142",\ + "0.053502, 0.053502, 0.053502, 0.053501, 0.053499",\ + "0.082236, 0.082236, 0.082235, 0.082234, 0.082232",\ + "0.159095, 0.159095, 0.159095, 0.159095, 0.159095",\ + "0.457392, 0.457392, 0.457392, 0.457392, 0.457392",\ + "1.523144, 1.523144, 1.523144, 1.523144, 1.523142",\ + "0.053502, 0.053502, 0.053502, 0.053501, 0.053499",\ + "0.082236, 0.082236, 0.082235, 0.082234, 0.082232",\ + "0.159095, 0.159095, 0.159095, 0.159095, 0.159095",\ + "0.457392, 0.457392, 0.457392, 0.457392, 0.457392",\ + "1.523144, 1.523144, 1.523144, 1.523144, 1.523142",\ + "0.053502, 0.053502, 0.053502, 0.053501, 0.053499",\ + "0.082236, 0.082236, 0.082235, 0.082234, 0.082232",\ + "0.159095, 0.159095, 0.159095, 0.159095, 0.159095",\ + "0.457392, 0.457392, 0.457392, 0.457392, 0.457392",\ + "1.523144, 1.523144, 1.523144, 1.523144, 1.523142"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[10]_redg_2570*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[3]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.566961, 0.745387, 0.925648, 1.211854, 1.762971",\ + "0.595360, 0.773787, 0.954047, 1.240253, 1.791370",\ + "0.666893, 0.845320, 1.025580, 1.311786, 1.862903",\ + "0.923329, 1.101756, 1.282016, 1.568222, 2.119339",\ + "1.827306, 2.005733, 2.185993, 2.472199, 3.023317",\ + "0.651899, 0.830660, 1.011563, 1.297774, 1.849349",\ + "0.680298, 0.859059, 1.039962, 1.326174, 1.877749",\ + "0.751831, 0.930592, 1.111495, 1.397707, 1.949282",\ + "1.008267, 1.187028, 1.367931, 1.654143, 2.205718",\ + "1.912244, 2.091005, 2.271908, 2.558120, 3.109695",\ + "0.727805, 0.906103, 1.086372, 1.372371, 1.923522",\ + "0.756204, 0.934502, 1.114771, 1.400770, 1.951921",\ + "0.827737, 1.006035, 1.186304, 1.472303, 2.023454",\ + "1.084173, 1.262471, 1.442740, 1.728739, 2.279890",\ + "1.988150, 2.166448, 2.346717, 2.632716, 3.183867",\ + "0.782157, 0.960615, 1.141023, 1.426911, 1.977839",\ + "0.810557, 0.989014, 1.169422, 1.455310, 2.006238",\ + "0.882089, 1.060547, 1.240955, 1.526843, 2.077771",\ + "1.138525, 1.316983, 1.497391, 1.783279, 2.334207",\ + "2.042502, 2.220960, 2.401368, 2.687256, 3.238184",\ + "1.063579, 1.245842, 1.424973, 1.710637, 2.261117",\ + "1.091979, 1.274241, 1.453373, 1.739037, 2.289516",\ + "1.163512, 1.345774, 1.524906, 1.810570, 2.361049",\ + "1.419947, 1.602210, 1.781342, 2.067005, 2.617485",\ + "2.323924, 2.506187, 2.685318, 2.970983, 3.521462"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.059998, 0.059998, 0.059998, 0.059998, 0.059998",\ + "0.108036, 0.108036, 0.108036, 0.108036, 0.108036",\ + "0.239906, 0.239906, 0.239906, 0.239906, 0.239906",\ + "0.732057, 0.732057, 0.732057, 0.732057, 0.732057",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\ + "0.059998, 0.059998, 0.059998, 0.059998, 0.059998",\ + "0.108036, 0.108036, 0.108036, 0.108036, 0.108036",\ + "0.239906, 0.239906, 0.239906, 0.239906, 0.239906",\ + "0.732057, 0.732057, 0.732057, 0.732057, 0.732057",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\ + "0.059998, 0.059998, 0.059998, 0.059998, 0.059998",\ + "0.108036, 0.108036, 0.108036, 0.108036, 0.108036",\ + "0.239906, 0.239906, 0.239906, 0.239906, 0.239906",\ + "0.732057, 0.732057, 0.732057, 0.732057, 0.732057",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\ + "0.059998, 0.059998, 0.059998, 0.059998, 0.059998",\ + "0.108036, 0.108036, 0.108036, 0.108036, 0.108036",\ + "0.239906, 0.239906, 0.239906, 0.239906, 0.239906",\ + "0.732057, 0.732057, 0.732057, 0.732057, 0.732057",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\ + "0.059998, 0.059998, 0.059998, 0.059998, 0.059998",\ + "0.108036, 0.108036, 0.108036, 0.108036, 0.108036",\ + "0.239906, 0.239906, 0.239906, 0.239906, 0.239906",\ + "0.732057, 0.732057, 0.732057, 0.732057, 0.732057",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.425437, 0.690607, 0.949809, 1.385991, 2.258357",\ + "0.447266, 0.712435, 0.971637, 1.407820, 2.280185",\ + "0.497406, 0.762576, 1.021778, 1.457960, 2.330325",\ + "0.663783, 0.928952, 1.188154, 1.624336, 2.496702",\ + "1.245206, 1.510376, 1.769578, 2.205760, 3.078125",\ + "0.514103, 0.778682, 1.038450, 1.474220, 2.345762",\ + "0.535931, 0.800510, 1.060278, 1.496048, 2.367590",\ + "0.586072, 0.850651, 1.110419, 1.546189, 2.417730",\ + "0.752448, 1.017027, 1.276795, 1.712565, 2.584107",\ + "1.333872, 1.598451, 1.858219, 2.293989, 3.165530",\ + "0.606910, 0.871805, 1.130175, 1.566384, 2.438803",\ + "0.628738, 0.893633, 1.152003, 1.588213, 2.460632",\ + "0.678878, 0.943774, 1.202144, 1.638353, 2.510772",\ + "0.845255, 1.110150, 1.368520, 1.804730, 2.677149",\ + "1.426679, 1.691574, 1.949944, 2.386153, 3.258572",\ + "0.672632, 0.940339, 1.197195, 1.633235, 2.505315",\ + "0.694461, 0.962168, 1.219023, 1.655063, 2.527143",\ + "0.744601, 1.012308, 1.269164, 1.705203, 2.577283",\ + "0.910977, 1.178684, 1.435540, 1.871580, 2.743660",\ + "1.492401, 1.760108, 2.016964, 2.453003, 3.325083",\ + "1.018422, 1.320838, 1.567825, 2.002366, 2.871448",\ + "1.040250, 1.342666, 1.589653, 2.024194, 2.893276",\ + "1.090390, 1.392806, 1.639794, 2.074335, 2.943416",\ + "1.256767, 1.559183, 1.806170, 2.240711, 3.109793",\ + "1.838190, 2.140606, 2.387594, 2.822135, 3.691216"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.053502, 0.053502, 0.053502, 0.053502, 0.053502",\ + "0.082236, 0.082236, 0.082236, 0.082236, 0.082235",\ + "0.159094, 0.159094, 0.159094, 0.159094, 0.159094",\ + "0.457392, 0.457392, 0.457392, 0.457392, 0.457392",\ + "1.523144, 1.523144, 1.523144, 1.523144, 1.523144",\ + "0.053502, 0.053502, 0.053502, 0.053502, 0.053502",\ + "0.082236, 0.082236, 0.082236, 0.082236, 0.082235",\ + "0.159094, 0.159094, 0.159094, 0.159094, 0.159094",\ + "0.457392, 0.457392, 0.457392, 0.457392, 0.457392",\ + "1.523144, 1.523144, 1.523144, 1.523144, 1.523144",\ + "0.053502, 0.053502, 0.053502, 0.053502, 0.053502",\ + "0.082236, 0.082236, 0.082236, 0.082236, 0.082235",\ + "0.159094, 0.159094, 0.159094, 0.159094, 0.159094",\ + "0.457392, 0.457392, 0.457392, 0.457392, 0.457392",\ + "1.523144, 1.523144, 1.523144, 1.523144, 1.523144",\ + "0.053502, 0.053502, 0.053502, 0.053502, 0.053502",\ + "0.082236, 0.082236, 0.082236, 0.082236, 0.082235",\ + "0.159094, 0.159094, 0.159094, 0.159094, 0.159094",\ + "0.457392, 0.457392, 0.457392, 0.457392, 0.457392",\ + "1.523144, 1.523144, 1.523144, 1.523144, 1.523144",\ + "0.053502, 0.053502, 0.053502, 0.053502, 0.053502",\ + "0.082236, 0.082236, 0.082236, 0.082236, 0.082235",\ + "0.159094, 0.159094, 0.159094, 0.159094, 0.159094",\ + "0.457392, 0.457392, 0.457392, 0.457392, 0.457392",\ + "1.523144, 1.523144, 1.523144, 1.523144, 1.523144"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[10]_redg_2508*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + values ( "0.334234, 0.362633, 0.434167, 0.690603, 1.594576",\ + "0.421625, 0.450024, 0.521558, 0.777994, 1.681967",\ + "0.502544, 0.530943, 0.602477, 0.858913, 1.762885",\ + "0.560284, 0.588684, 0.660217, 0.916654, 1.820624",\ + "0.862990, 0.891389, 0.962923, 1.219360, 2.123326"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + values ( "0.059999, 0.108036, 0.239907, 0.732038, 2.463871",\ + "0.059999, 0.108053, 0.240000, 0.732038, 2.463871",\ + "0.059999, 0.108094, 0.240218, 0.732038, 2.463871",\ + "0.059999, 0.108094, 0.240218, 0.732038, 2.463871",\ + "0.060087, 0.108094, 0.240545, 0.732051, 2.463884"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + values ( "0.305321, 0.327149, 0.377290, 0.543666, 1.125090",\ + "0.392714, 0.414542, 0.464682, 0.631059, 1.212482",\ + "0.473583, 0.495412, 0.545552, 0.711928, 1.293352",\ + "0.531232, 0.553060, 0.603201, 0.769577, 1.351001",\ + "0.834460, 0.856477, 0.906940, 1.073696, 1.654812"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + values ( "0.053502, 0.082236, 0.159102, 0.457392, 1.523894",\ + "0.053502, 0.082236, 0.159102, 0.457392, 1.523894",\ + "0.053502, 0.082236, 0.159102, 0.457392, 1.523767",\ + "0.053502, 0.082236, 0.159102, 0.457392, 1.523532",\ + "0.053458, 0.082179, 0.159102, 0.457388, 1.523144"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[10]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[0]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.517252, 0.697365, 0.884944, 1.186924, 1.770020",\ + "0.545074, 0.725188, 0.912766, 1.214746, 1.797842",\ + "0.616076, 0.796190, 0.983769, 1.285748, 1.868845",\ + "0.871803, 1.051917, 1.239495, 1.541475, 2.124571",\ + "1.774034, 1.954148, 2.141726, 2.443706, 3.026802",\ + "0.602190, 0.782201, 0.970014, 1.272430, 1.856398",\ + "0.630012, 0.810023, 0.997836, 1.300252, 1.884220",\ + "0.701015, 0.881026, 1.068839, 1.371255, 1.955223",\ + "0.956741, 1.136753, 1.324565, 1.626981, 2.210949",\ + "1.858973, 2.038984, 2.226796, 2.529212, 3.113181",\ + "0.678102, 0.857644, 1.044823, 1.347027, 1.930570",\ + "0.705924, 0.885467, 1.072645, 1.374849, 1.958393",\ + "0.776927, 0.956469, 1.143648, 1.445851, 2.029395",\ + "1.032653, 1.212196, 1.399374, 1.701578, 2.285122",\ + "1.934885, 2.114427, 2.301605, 2.603809, 3.187353",\ + "0.732471, 0.912396, 1.099712, 1.401632, 1.984888",\ + "0.760294, 0.940218, 1.127534, 1.429455, 2.012710",\ + "0.831296, 1.011221, 1.198536, 1.500457, 2.083713",\ + "1.087023, 1.266947, 1.454263, 1.756184, 2.339439",\ + "1.989254, 2.169178, 2.356494, 2.658415, 3.241670",\ + "1.014066, 1.197961, 1.383887, 1.685358, 2.268165",\ + "1.041888, 1.225783, 1.411709, 1.713181, 2.295988",\ + "1.112891, 1.296786, 1.482712, 1.784183, 2.366990",\ + "1.368618, 1.552512, 1.738438, 2.039910, 2.622717",\ + "2.270849, 2.454743, 2.640669, 2.942141, 3.524948"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.057228, 0.057228, 0.057228, 0.057228, 0.057228",\ + "0.105834, 0.105834, 0.105834, 0.105834, 0.105834",\ + "0.238478, 0.238478, 0.238478, 0.238478, 0.238478",\ + "0.727955, 0.727955, 0.727955, 0.727955, 0.727955",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\ + "0.057228, 0.057228, 0.057228, 0.057228, 0.057228",\ + "0.105834, 0.105834, 0.105834, 0.105834, 0.105834",\ + "0.238478, 0.238478, 0.238478, 0.238478, 0.238478",\ + "0.727955, 0.727955, 0.727955, 0.727955, 0.727955",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\ + "0.057228, 0.057228, 0.057228, 0.057228, 0.057228",\ + "0.105834, 0.105834, 0.105834, 0.105834, 0.105834",\ + "0.238478, 0.238478, 0.238478, 0.238478, 0.238478",\ + "0.727955, 0.727955, 0.727955, 0.727955, 0.727955",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\ + "0.057228, 0.057228, 0.057228, 0.057228, 0.057228",\ + "0.105834, 0.105834, 0.105834, 0.105834, 0.105834",\ + "0.238478, 0.238478, 0.238478, 0.238478, 0.238478",\ + "0.727955, 0.727955, 0.727955, 0.727955, 0.727955",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\ + "0.057228, 0.057228, 0.057228, 0.057228, 0.057228",\ + "0.105834, 0.105834, 0.105834, 0.105834, 0.105834",\ + "0.238478, 0.238478, 0.238478, 0.238478, 0.238478",\ + "0.727955, 0.727955, 0.727955, 0.727955, 0.727955",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.397272, 0.664882, 0.926275, 1.366020, 2.245119",\ + "0.417207, 0.684818, 0.946210, 1.385955, 2.265054",\ + "0.464850, 0.732461, 0.993853, 1.433599, 2.312697",\ + "0.630183, 0.897793, 1.159185, 1.598931, 2.478030",\ + "1.214286, 1.481897, 1.743298, 2.183075, 3.062236",\ + "0.485976, 0.752957, 1.014915, 1.454249, 2.332524",\ + "0.505911, 0.772893, 1.034851, 1.474185, 2.352459",\ + "0.553554, 0.820536, 1.082494, 1.521828, 2.400102",\ + "0.718887, 0.985868, 1.247826, 1.687160, 2.565435",\ + "1.302990, 1.569972, 1.831939, 2.271304, 3.149641",\ + "0.578918, 0.846278, 1.106960, 1.546495, 2.425566",\ + "0.598853, 0.866213, 1.126895, 1.566430, 2.445501",\ + "0.646497, 0.913856, 1.174538, 1.614074, 2.493144",\ + "0.811829, 1.079188, 1.339871, 1.779406, 2.658477",\ + "1.395933, 1.663292, 1.923983, 2.363550, 3.242683",\ + "0.644762, 0.914842, 1.174016, 1.613506, 2.492487",\ + "0.664697, 0.934777, 1.193951, 1.633442, 2.512423",\ + "0.712340, 0.982420, 1.241595, 1.681085, 2.560066",\ + "0.877673, 1.147753, 1.406927, 1.846417, 2.725398",\ + "1.461776, 1.731856, 1.991039, 2.430561, 3.309604",\ + "0.991283, 1.295677, 1.544687, 1.982732, 2.858823",\ + "1.011218, 1.315613, 1.564622, 2.002667, 2.878758",\ + "1.058862, 1.363256, 1.612265, 2.050310, 2.926401",\ + "1.224194, 1.528588, 1.777597, 2.215642, 3.091733",\ + "1.808298, 2.112692, 2.361710, 2.799787, 3.675940"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.044581, 0.044581, 0.044581, 0.044581, 0.044581",\ + "0.073511, 0.073511, 0.073511, 0.073511, 0.073511",\ + "0.152010, 0.152010, 0.152010, 0.152010, 0.152010",\ + "0.452924, 0.452924, 0.452924, 0.452925, 0.452925",\ + "1.518485, 1.518485, 1.518485, 1.518485, 1.518485",\ + "0.044581, 0.044581, 0.044581, 0.044581, 0.044581",\ + "0.073511, 0.073511, 0.073511, 0.073511, 0.073511",\ + "0.152010, 0.152010, 0.152010, 0.152010, 0.152010",\ + "0.452924, 0.452924, 0.452924, 0.452925, 0.452925",\ + "1.518485, 1.518485, 1.518485, 1.518485, 1.518485",\ + "0.044581, 0.044581, 0.044581, 0.044581, 0.044581",\ + "0.073511, 0.073511, 0.073511, 0.073511, 0.073511",\ + "0.152010, 0.152010, 0.152010, 0.152010, 0.152010",\ + "0.452924, 0.452924, 0.452924, 0.452925, 0.452925",\ + "1.518485, 1.518485, 1.518485, 1.518485, 1.518485",\ + "0.044581, 0.044581, 0.044581, 0.044581, 0.044581",\ + "0.073511, 0.073511, 0.073511, 0.073511, 0.073511",\ + "0.152010, 0.152010, 0.152010, 0.152010, 0.152010",\ + "0.452924, 0.452924, 0.452924, 0.452925, 0.452925",\ + "1.518485, 1.518485, 1.518485, 1.518485, 1.518485",\ + "0.044581, 0.044581, 0.044581, 0.044581, 0.044581",\ + "0.073511, 0.073511, 0.073511, 0.073511, 0.073511",\ + "0.152010, 0.152010, 0.152010, 0.152010, 0.152010",\ + "0.452924, 0.452924, 0.452924, 0.452925, 0.452925",\ + "1.518485, 1.518485, 1.518485, 1.518485, 1.518485"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[10]_redg_min_2444*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[1]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.425360, 0.688891, 0.965011, 1.433143, 2.368146",\ + "0.453182, 0.716714, 0.992833, 1.460965, 2.395969",\ + "0.524185, 0.787716, 1.063836, 1.531968, 2.466971",\ + "0.779912, 1.043443, 1.319562, 1.787694, 2.722698",\ + "1.682143, 1.945674, 2.221793, 2.689925, 3.624929",\ + "0.513554, 0.776432, 1.052578, 1.519858, 2.454080",\ + "0.541377, 0.804254, 1.080400, 1.547680, 2.481903",\ + "0.612379, 0.875257, 1.151402, 1.618683, 2.552905",\ + "0.868106, 1.130983, 1.407129, 1.874409, 2.808632",\ + "1.770337, 2.033214, 2.309360, 2.776640, 3.710862",\ + "0.601870, 0.865411, 1.140543, 1.607498, 2.541035",\ + "0.629693, 0.893234, 1.168365, 1.635320, 2.568858",\ + "0.700695, 0.964236, 1.239367, 1.706323, 2.639860",\ + "0.956422, 1.219963, 1.495094, 1.962050, 2.895587",\ + "1.858653, 2.122194, 2.397325, 2.864281, 3.797817",\ + "0.664366, 0.931045, 1.204682, 1.671587, 2.604544",\ + "0.692189, 0.958867, 1.232504, 1.699409, 2.632367",\ + "0.763191, 1.029870, 1.303507, 1.770412, 2.703369",\ + "1.018918, 1.285596, 1.559234, 2.026138, 2.959096",\ + "1.921149, 2.187827, 2.461465, 2.928370, 3.861326",\ + "0.993492, 1.295360, 1.556546, 2.021031, 2.950000",\ + "1.021315, 1.323182, 1.584368, 2.048853, 2.977823",\ + "1.092317, 1.394185, 1.655371, 2.119856, 3.048825",\ + "1.348044, 1.649911, 1.911098, 2.375582, 3.304552",\ + "2.250275, 2.552142, 2.813329, 3.277813, 4.206782"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.057228, 0.057228, 0.057228, 0.057228, 0.057229",\ + "0.105834, 0.105834, 0.105834, 0.105834, 0.105835",\ + "0.238478, 0.238478, 0.238478, 0.238478, 0.238479",\ + "0.727955, 0.727955, 0.727955, 0.727955, 0.727954",\ + "2.448223, 2.448223, 2.448224, 2.448226, 2.448230",\ + "0.057228, 0.057228, 0.057228, 0.057228, 0.057229",\ + "0.105834, 0.105834, 0.105834, 0.105834, 0.105835",\ + "0.238478, 0.238478, 0.238478, 0.238478, 0.238479",\ + "0.727955, 0.727955, 0.727955, 0.727955, 0.727954",\ + "2.448223, 2.448223, 2.448224, 2.448226, 2.448230",\ + "0.057228, 0.057228, 0.057228, 0.057228, 0.057229",\ + "0.105834, 0.105834, 0.105834, 0.105834, 0.105835",\ + "0.238478, 0.238478, 0.238478, 0.238478, 0.238479",\ + "0.727955, 0.727955, 0.727955, 0.727955, 0.727954",\ + "2.448223, 2.448223, 2.448224, 2.448226, 2.448230",\ + "0.057228, 0.057228, 0.057228, 0.057228, 0.057229",\ + "0.105834, 0.105834, 0.105834, 0.105834, 0.105835",\ + "0.238478, 0.238478, 0.238478, 0.238478, 0.238479",\ + "0.727955, 0.727955, 0.727955, 0.727955, 0.727954",\ + "2.448223, 2.448223, 2.448224, 2.448226, 2.448230",\ + "0.057228, 0.057228, 0.057228, 0.057228, 0.057229",\ + "0.105834, 0.105834, 0.105834, 0.105834, 0.105835",\ + "0.238478, 0.238478, 0.238478, 0.238478, 0.238479",\ + "0.727955, 0.727955, 0.727955, 0.727955, 0.727954",\ + "2.448223, 2.448223, 2.448224, 2.448226, 2.448230"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.380225, 0.562282, 0.758415, 1.067547, 1.662000",\ + "0.400160, 0.582218, 0.778351, 1.087482, 1.681936",\ + "0.447803, 0.629861, 0.825994, 1.135126, 1.729579",\ + "0.613136, 0.795193, 0.991326, 1.300459, 1.894914",\ + "1.197241, 1.379299, 1.575532, 1.884713, 2.479196",\ + "0.467640, 0.649601, 0.845696, 1.154852, 1.749354",\ + "0.487575, 0.669536, 0.865631, 1.174787, 1.769289",\ + "0.535218, 0.717180, 0.913275, 1.222431, 1.816933",\ + "0.700550, 0.882512, 1.078607, 1.387764, 1.982267",\ + "1.284656, 1.466618, 1.662813, 1.972018, 2.566549",\ + "0.548516, 0.729938, 0.925723, 1.234881, 1.829386",\ + "0.568451, 0.749873, 0.945658, 1.254816, 1.849321",\ + "0.616094, 0.797516, 0.993302, 1.302459, 1.896965",\ + "0.781427, 0.962848, 1.158634, 1.467792, 2.062299",\ + "1.365532, 1.546954, 1.742840, 2.052047, 2.646581",\ + "0.606162, 0.787775, 0.983459, 1.292351, 1.886481",\ + "0.626098, 0.807710, 1.003394, 1.312286, 1.906416",\ + "0.673741, 0.855353, 1.051037, 1.359930, 1.954060",\ + "0.839073, 1.020685, 1.216369, 1.525263, 2.119395",\ + "1.423179, 1.604791, 1.800576, 2.109517, 2.703676",\ + "0.908370, 1.093152, 1.287122, 1.595558, 2.188799",\ + "0.928305, 1.113087, 1.307057, 1.615493, 2.208735",\ + "0.975949, 1.160730, 1.354700, 1.663137, 2.256378",\ + "1.141281, 1.326062, 1.520033, 1.828470, 2.421713",\ + "1.725386, 1.910168, 2.104239, 2.412724, 3.005995"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.044581, 0.044581, 0.044581, 0.044581, 0.044582",\ + "0.073511, 0.073511, 0.073511, 0.073511, 0.073513",\ + "0.152010, 0.152010, 0.152010, 0.152011, 0.152012",\ + "0.452924, 0.452924, 0.452925, 0.452931, 0.452943",\ + "1.518485, 1.518485, 1.518485, 1.518486, 1.518488",\ + "0.044581, 0.044581, 0.044581, 0.044581, 0.044582",\ + "0.073511, 0.073511, 0.073511, 0.073511, 0.073513",\ + "0.152010, 0.152010, 0.152010, 0.152011, 0.152012",\ + "0.452924, 0.452924, 0.452925, 0.452931, 0.452943",\ + "1.518485, 1.518485, 1.518485, 1.518486, 1.518488",\ + "0.044581, 0.044581, 0.044581, 0.044581, 0.044582",\ + "0.073511, 0.073511, 0.073511, 0.073511, 0.073513",\ + "0.152010, 0.152010, 0.152010, 0.152011, 0.152012",\ + "0.452924, 0.452924, 0.452925, 0.452931, 0.452943",\ + "1.518485, 1.518485, 1.518485, 1.518486, 1.518488",\ + "0.044581, 0.044581, 0.044581, 0.044581, 0.044582",\ + "0.073511, 0.073511, 0.073511, 0.073511, 0.073513",\ + "0.152010, 0.152010, 0.152010, 0.152011, 0.152012",\ + "0.452924, 0.452924, 0.452925, 0.452931, 0.452943",\ + "1.518485, 1.518485, 1.518485, 1.518486, 1.518488",\ + "0.044581, 0.044581, 0.044581, 0.044581, 0.044582",\ + "0.073511, 0.073511, 0.073511, 0.073511, 0.073513",\ + "0.152010, 0.152010, 0.152010, 0.152011, 0.152012",\ + "0.452924, 0.452924, 0.452925, 0.452931, 0.452943",\ + "1.518485, 1.518485, 1.518485, 1.518486, 1.518488"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[10]_redg_min_2368*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[2]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.421382, 0.680941, 0.952576, 1.408738, 2.319905",\ + "0.449204, 0.708764, 0.980399, 1.436560, 2.347728",\ + "0.520207, 0.779766, 1.051401, 1.507563, 2.418730",\ + "0.775933, 1.035493, 1.307128, 1.763289, 2.674457",\ + "1.678164, 1.937724, 2.209359, 2.665520, 3.576688",\ + "0.509487, 0.768474, 1.040105, 1.495453, 2.405839",\ + "0.537309, 0.796296, 1.067928, 1.523275, 2.433661",\ + "0.608312, 0.867299, 1.138930, 1.594278, 2.504664",\ + "0.864038, 1.123026, 1.394657, 1.850005, 2.760391",\ + "1.766269, 2.025257, 2.296888, 2.752235, 3.662621",\ + "0.597517, 0.857438, 1.128069, 1.583092, 2.492794",\ + "0.625339, 0.885261, 1.155892, 1.610914, 2.520617",\ + "0.696342, 0.956263, 1.226894, 1.681917, 2.591619",\ + "0.952068, 1.211990, 1.482621, 1.937644, 2.847346",\ + "1.854300, 2.114221, 2.384852, 2.839874, 3.749576",\ + "0.659738, 0.923050, 1.192207, 1.647166, 2.556303",\ + "0.687560, 0.950872, 1.220030, 1.674989, 2.584126",\ + "0.758563, 1.021875, 1.291032, 1.745991, 2.655128",\ + "1.014290, 1.277601, 1.546759, 2.001718, 2.910855",\ + "1.916521, 2.179832, 2.448990, 2.903949, 3.813085",\ + "0.987126, 1.287098, 1.543950, 1.996553, 2.901759",\ + "1.014948, 1.314920, 1.571772, 2.024375, 2.929582",\ + "1.085950, 1.385923, 1.642775, 2.095378, 3.000584",\ + "1.341677, 1.641650, 1.898501, 2.351104, 3.256311",\ + "2.243908, 2.543881, 2.800732, 3.253335, 4.158542"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.057228, 0.057228, 0.057228, 0.057229, 0.057230",\ + "0.105834, 0.105834, 0.105834, 0.105835, 0.105835",\ + "0.238478, 0.238478, 0.238478, 0.238479, 0.238479",\ + "0.727955, 0.727955, 0.727955, 0.727954, 0.727953",\ + "2.448223, 2.448223, 2.448225, 2.448228, 2.448234",\ + "0.057228, 0.057228, 0.057228, 0.057229, 0.057230",\ + "0.105834, 0.105834, 0.105834, 0.105835, 0.105835",\ + "0.238478, 0.238478, 0.238478, 0.238479, 0.238479",\ + "0.727955, 0.727955, 0.727955, 0.727954, 0.727953",\ + "2.448223, 2.448223, 2.448225, 2.448228, 2.448234",\ + "0.057228, 0.057228, 0.057228, 0.057229, 0.057230",\ + "0.105834, 0.105834, 0.105834, 0.105835, 0.105835",\ + "0.238478, 0.238478, 0.238478, 0.238479, 0.238479",\ + "0.727955, 0.727955, 0.727955, 0.727954, 0.727953",\ + "2.448223, 2.448223, 2.448225, 2.448228, 2.448234",\ + "0.057228, 0.057228, 0.057228, 0.057229, 0.057230",\ + "0.105834, 0.105834, 0.105834, 0.105835, 0.105835",\ + "0.238478, 0.238478, 0.238478, 0.238479, 0.238479",\ + "0.727955, 0.727955, 0.727955, 0.727954, 0.727953",\ + "2.448223, 2.448223, 2.448225, 2.448228, 2.448234",\ + "0.057228, 0.057228, 0.057228, 0.057229, 0.057230",\ + "0.105834, 0.105834, 0.105834, 0.105835, 0.105835",\ + "0.238478, 0.238478, 0.238478, 0.238479, 0.238479",\ + "0.727955, 0.727955, 0.727955, 0.727954, 0.727953",\ + "2.448223, 2.448223, 2.448225, 2.448228, 2.448234"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.378563, 0.560731, 0.756728, 1.066021, 1.660963",\ + "0.398499, 0.580666, 0.776663, 1.085956, 1.680898",\ + "0.446142, 0.628309, 0.824306, 1.133599, 1.728542",\ + "0.611474, 0.793641, 0.989638, 1.298932, 1.893877",\ + "1.195578, 1.377745, 1.573843, 1.883181, 2.478140",\ + "0.465983, 0.648049, 0.844008, 1.153326, 1.748316",\ + "0.485919, 0.667985, 0.863944, 1.173261, 1.768251",\ + "0.533562, 0.715628, 0.911587, 1.220904, 1.815895",\ + "0.698894, 0.880960, 1.076919, 1.386237, 1.981230",\ + "1.282998, 1.465064, 1.661124, 1.970486, 2.565494",\ + "0.546851, 0.728386, 0.924035, 1.233354, 1.828348",\ + "0.566786, 0.748322, 0.943970, 1.253289, 1.848283",\ + "0.614429, 0.795965, 0.991614, 1.300933, 1.895927",\ + "0.779762, 0.961297, 1.156946, 1.466266, 2.061262",\ + "1.363865, 1.545401, 1.741151, 2.050514, 2.645525",\ + "0.604490, 0.786223, 0.981770, 1.290825, 1.885444",\ + "0.624425, 0.806158, 1.001706, 1.310760, 1.905379",\ + "0.672068, 0.853802, 1.049349, 1.358404, 1.953023",\ + "0.837401, 1.019134, 1.214681, 1.523737, 2.118358",\ + "1.421504, 1.603237, 1.798886, 2.107985, 2.702621",\ + "0.906585, 1.091602, 1.285434, 1.594033, 2.187764",\ + "0.926520, 1.111537, 1.305369, 1.613968, 2.207699",\ + "0.974163, 1.159180, 1.353012, 1.661611, 2.255342",\ + "1.139496, 1.324512, 1.518345, 1.826944, 2.420678",\ + "1.723599, 1.908616, 2.102550, 2.411193, 3.004941"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.044581, 0.044581, 0.044581, 0.044581, 0.044582",\ + "0.073511, 0.073511, 0.073511, 0.073512, 0.073513",\ + "0.152010, 0.152010, 0.152010, 0.152011, 0.152012",\ + "0.452924, 0.452924, 0.452925, 0.452931, 0.452944",\ + "1.518485, 1.518485, 1.518485, 1.518486, 1.518488",\ + "0.044581, 0.044581, 0.044581, 0.044581, 0.044582",\ + "0.073511, 0.073511, 0.073511, 0.073512, 0.073513",\ + "0.152010, 0.152010, 0.152010, 0.152011, 0.152012",\ + "0.452924, 0.452924, 0.452925, 0.452931, 0.452944",\ + "1.518485, 1.518485, 1.518485, 1.518486, 1.518488",\ + "0.044581, 0.044581, 0.044581, 0.044581, 0.044582",\ + "0.073511, 0.073511, 0.073511, 0.073512, 0.073513",\ + "0.152010, 0.152010, 0.152010, 0.152011, 0.152012",\ + "0.452924, 0.452924, 0.452925, 0.452931, 0.452944",\ + "1.518485, 1.518485, 1.518485, 1.518486, 1.518488",\ + "0.044581, 0.044581, 0.044581, 0.044581, 0.044582",\ + "0.073511, 0.073511, 0.073511, 0.073512, 0.073513",\ + "0.152010, 0.152010, 0.152010, 0.152011, 0.152012",\ + "0.452924, 0.452924, 0.452925, 0.452931, 0.452944",\ + "1.518485, 1.518485, 1.518485, 1.518486, 1.518488",\ + "0.044581, 0.044581, 0.044581, 0.044581, 0.044582",\ + "0.073511, 0.073511, 0.073511, 0.073512, 0.073513",\ + "0.152010, 0.152010, 0.152010, 0.152011, 0.152012",\ + "0.452924, 0.452924, 0.452925, 0.452931, 0.452944",\ + "1.518485, 1.518485, 1.518485, 1.518486, 1.518488"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[10]_redg_min_2312*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[3]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.513665, 0.692005, 0.872351, 1.158538, 1.709291",\ + "0.541488, 0.719827, 0.900174, 1.186360, 1.737113",\ + "0.612490, 0.790830, 0.971176, 1.257363, 1.808116",\ + "0.868217, 1.046556, 1.226903, 1.513090, 2.063843",\ + "1.770448, 1.948787, 2.129134, 2.415321, 2.966074",\ + "0.598604, 0.776840, 0.957422, 1.244044, 1.795670",\ + "0.626426, 0.804663, 0.985244, 1.271867, 1.823492",\ + "0.697429, 0.875665, 1.056247, 1.342869, 1.894494",\ + "0.953155, 1.131392, 1.311973, 1.598596, 2.150221",\ + "1.855386, 2.033623, 2.214204, 2.500827, 3.052452",\ + "0.674510, 0.852284, 1.032230, 1.318641, 1.869842",\ + "0.702332, 0.880106, 1.060053, 1.346463, 1.897664",\ + "0.773335, 0.951109, 1.131055, 1.417466, 1.968667",\ + "1.029061, 1.206835, 1.386782, 1.673193, 2.224393",\ + "1.931292, 2.109066, 2.289013, 2.575424, 3.126625",\ + "0.728862, 0.907029, 1.087096, 1.373235, 1.924159",\ + "0.756684, 0.934852, 1.114918, 1.401057, 1.951982",\ + "0.827687, 1.005854, 1.185921, 1.472059, 2.022984",\ + "1.083413, 1.261581, 1.441647, 1.727786, 2.278711",\ + "1.985644, 2.163812, 2.343878, 2.630017, 3.180942",\ + "1.010284, 1.192547, 1.371249, 1.656961, 2.207437",\ + "1.038106, 1.220369, 1.399071, 1.684783, 2.235259",\ + "1.109109, 1.291372, 1.470074, 1.755786, 2.306262",\ + "1.364835, 1.547098, 1.725800, 2.011513, 2.561988",\ + "2.267066, 2.449329, 2.628031, 2.913743, 3.464219"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.057228, 0.057228, 0.057228, 0.057228, 0.057228",\ + "0.105834, 0.105834, 0.105834, 0.105834, 0.105834",\ + "0.238478, 0.238478, 0.238478, 0.238478, 0.238478",\ + "0.727955, 0.727955, 0.727955, 0.727955, 0.727955",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\ + "0.057228, 0.057228, 0.057228, 0.057228, 0.057228",\ + "0.105834, 0.105834, 0.105834, 0.105834, 0.105834",\ + "0.238478, 0.238478, 0.238478, 0.238478, 0.238478",\ + "0.727955, 0.727955, 0.727955, 0.727955, 0.727955",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\ + "0.057228, 0.057228, 0.057228, 0.057228, 0.057228",\ + "0.105834, 0.105834, 0.105834, 0.105834, 0.105834",\ + "0.238478, 0.238478, 0.238478, 0.238478, 0.238478",\ + "0.727955, 0.727955, 0.727955, 0.727955, 0.727955",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\ + "0.057228, 0.057228, 0.057228, 0.057228, 0.057228",\ + "0.105834, 0.105834, 0.105834, 0.105834, 0.105834",\ + "0.238478, 0.238478, 0.238478, 0.238478, 0.238478",\ + "0.727955, 0.727955, 0.727955, 0.727955, 0.727955",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\ + "0.057228, 0.057228, 0.057228, 0.057228, 0.057228",\ + "0.105834, 0.105834, 0.105834, 0.105834, 0.105834",\ + "0.238478, 0.238478, 0.238478, 0.238478, 0.238478",\ + "0.727955, 0.727955, 0.727955, 0.727955, 0.727955",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.395836, 0.660835, 0.919855, 1.356084, 2.228162",\ + "0.415771, 0.680770, 0.939790, 1.376020, 2.248097",\ + "0.463414, 0.728413, 0.987433, 1.423663, 2.295740",\ + "0.628747, 0.893746, 1.152766, 1.588995, 2.461072",\ + "1.212850, 1.477849, 1.736879, 2.173143, 3.045290",\ + "0.484501, 0.748910, 1.008496, 1.444313, 2.315567",\ + "0.504437, 0.768845, 1.028431, 1.464249, 2.335502",\ + "0.552080, 0.816488, 1.076074, 1.511892, 2.383145",\ + "0.717412, 0.981821, 1.241406, 1.677224, 2.548478",\ + "1.301516, 1.565924, 1.825520, 2.261372, 3.132695",\ + "0.577308, 0.842203, 1.100531, 1.536557, 2.408609",\ + "0.597243, 0.862139, 1.120466, 1.556492, 2.428544",\ + "0.644887, 0.909782, 1.168109, 1.604135, 2.476187",\ + "0.810219, 1.075114, 1.333442, 1.769467, 2.641520",\ + "1.394323, 1.659218, 1.917555, 2.353615, 3.225737",\ + "0.643031, 0.910738, 1.167586, 1.603563, 2.475518",\ + "0.662966, 0.930673, 1.187521, 1.623498, 2.495454",\ + "0.710609, 0.978316, 1.235164, 1.671142, 2.543097",\ + "0.875941, 1.143648, 1.400497, 1.836474, 2.708429",\ + "1.460045, 1.727752, 1.984610, 2.420622, 3.292646",\ + "0.988820, 1.291236, 1.538224, 1.972764, 2.841846",\ + "1.008755, 1.311171, 1.558159, 1.992699, 2.861781",\ + "1.056399, 1.358814, 1.605802, 2.040343, 2.909424",\ + "1.221731, 1.524147, 1.771134, 2.205675, 3.074756",\ + "1.805834, 2.108251, 2.355248, 2.789823, 3.658973"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.044581, 0.044581, 0.044581, 0.044581, 0.044581",\ + "0.073511, 0.073511, 0.073511, 0.073511, 0.073511",\ + "0.152010, 0.152010, 0.152010, 0.152010, 0.152010",\ + "0.452924, 0.452924, 0.452924, 0.452925, 0.452925",\ + "1.518485, 1.518485, 1.518485, 1.518485, 1.518485",\ + "0.044581, 0.044581, 0.044581, 0.044581, 0.044581",\ + "0.073511, 0.073511, 0.073511, 0.073511, 0.073511",\ + "0.152010, 0.152010, 0.152010, 0.152010, 0.152010",\ + "0.452924, 0.452924, 0.452924, 0.452925, 0.452925",\ + "1.518485, 1.518485, 1.518485, 1.518485, 1.518485",\ + "0.044581, 0.044581, 0.044581, 0.044581, 0.044581",\ + "0.073511, 0.073511, 0.073511, 0.073511, 0.073511",\ + "0.152010, 0.152010, 0.152010, 0.152010, 0.152010",\ + "0.452924, 0.452924, 0.452924, 0.452925, 0.452925",\ + "1.518485, 1.518485, 1.518485, 1.518485, 1.518485",\ + "0.044581, 0.044581, 0.044581, 0.044581, 0.044581",\ + "0.073511, 0.073511, 0.073511, 0.073511, 0.073511",\ + "0.152010, 0.152010, 0.152010, 0.152010, 0.152010",\ + "0.452924, 0.452924, 0.452924, 0.452925, 0.452925",\ + "1.518485, 1.518485, 1.518485, 1.518485, 1.518485",\ + "0.044581, 0.044581, 0.044581, 0.044581, 0.044581",\ + "0.073511, 0.073511, 0.073511, 0.073511, 0.073511",\ + "0.152010, 0.152010, 0.152010, 0.152010, 0.152010",\ + "0.452924, 0.452924, 0.452924, 0.452925, 0.452925",\ + "1.518485, 1.518485, 1.518485, 1.518485, 1.518485"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[10]_redg_min_2754*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + values ( "0.151345, 0.179420, 0.250838, 0.507101, 1.411098",\ + "0.239529, 0.267606, 0.339037, 0.595340, 1.499024",\ + "0.327854, 0.355929, 0.427371, 0.683856, 1.587106",\ + "0.390452, 0.418510, 0.489921, 0.746692, 1.650402",\ + "0.720352, 0.748358, 0.819633, 1.076844, 1.982165"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + values ( "0.057228, 0.105834, 0.238478, 0.727955, 2.448223",\ + "0.057228, 0.105834, 0.238478, 0.727955, 2.448223",\ + "0.057228, 0.105834, 0.238478, 0.727955, 2.448223",\ + "0.057228, 0.105834, 0.238478, 0.727955, 2.448223",\ + "0.057228, 0.105834, 0.238478, 0.727955, 2.448223"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + values ( "0.187745, 0.208337, 0.256868, 0.422532, 1.003731",\ + "0.275148, 0.295740, 0.344271, 0.509935, 1.091134",\ + "0.356045, 0.376636, 0.425171, 0.590840, 1.172047",\ + "0.413704, 0.434296, 0.482838, 0.648514, 1.229738",\ + "0.716053, 0.736646, 0.785216, 0.950960, 1.532355"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + values ( "0.044579, 0.073509, 0.152008, 0.452080, 1.516200",\ + "0.044579, 0.073509, 0.152008, 0.452080, 1.516200",\ + "0.044579, 0.073509, 0.152008, 0.452124, 1.516200",\ + "0.044579, 0.073509, 0.152008, 0.452204, 1.516200",\ + "0.044579, 0.073509, 0.152008, 0.452924, 1.516200"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[10]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_falling ; + clock_gating_flag : true ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.146298, 0.146298, 0.146298, 0.146298, 0.146298",\ + "0.171440, 0.171440, 0.171440, 0.171440, 0.171440",\ + "0.241225, 0.241225, 0.241225, 0.241225, 0.241225",\ + "0.364369, 0.364369, 0.364369, 0.364369, 0.364369",\ + "0.930611, 0.930611, 0.930611, 0.930611, 0.930611"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.419370, 0.419370, 0.419370, 0.419370, 0.419370",\ + "0.439927, 0.439927, 0.439927, 0.439927, 0.439927",\ + "0.498432, 0.498432, 0.498432, 0.498432, 0.498432",\ + "0.607706, 0.607706, 0.607706, 0.607706, 0.607706",\ + "1.345296, 1.345296, 1.345296, 1.345296, 1.345296"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[10]_cgsf*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + clock_gating_flag : true ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.138551, -0.138551, -0.138551, -0.138551, -0.138551",\ + "-0.162150, -0.162150, -0.162150, -0.162150, -0.162150",\ + "-0.233628, -0.233628, -0.233628, -0.233628, -0.233628",\ + "-0.357370, -0.357370, -0.357370, -0.357370, -0.357370",\ + "-0.923132, -0.923132, -0.923132, -0.923132, -0.923132"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.415516, -0.415516, -0.415516, -0.415516, -0.415516",\ + "-0.432323, -0.432323, -0.432323, -0.432323, -0.432323",\ + "-0.494548, -0.494548, -0.494548, -0.494548, -0.494548",\ + "-0.603812, -0.603812, -0.603812, -0.603812, -0.603812",\ + "-1.339799, -1.339799, -1.339799, -1.339799, -1.339799"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[10]_cghr*/ + + timing () { + related_pin : "padmux2ast_i[2]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + values ( "0.098861, 0.127061, 0.198218, 0.454154, 1.359203",\ + "0.186535, 0.214722, 0.285779, 0.541885, 1.444562",\ + "0.285062, 0.314115, 0.385746, 0.641617, 1.547694",\ + "0.464742, 0.495967, 0.569252, 0.824864, 1.732299",\ + "0.773180, 0.811674, 0.892653, 1.148190, 2.048527"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + values ( "0.058877, 0.106972, 0.239632, 0.734291, 2.481454",\ + "0.059452, 0.107162, 0.239653, 0.735798, 2.481454",\ + "0.065492, 0.111214, 0.239653, 0.735798, 2.481454",\ + "0.080964, 0.122543, 0.243345, 0.735798, 2.481454",\ + "0.122739, 0.156713, 0.261409, 0.735798, 2.481454"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + values ( "0.135906, 0.157942, 0.208401, 0.375177, 0.957248",\ + "0.214952, 0.236957, 0.287364, 0.454102, 1.034980",\ + "0.319131, 0.342208, 0.393489, 0.560142, 1.142872",\ + "0.499405, 0.526607, 0.582603, 0.750679, 1.332501",\ + "0.794222, 0.832488, 0.901924, 1.075291, 1.655125"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + values ( "0.053775, 0.082436, 0.159158, 0.457799, 1.524944",\ + "0.053775, 0.082436, 0.159158, 0.457799, 1.524944",\ + "0.061142, 0.087763, 0.161724, 0.457799, 1.524944",\ + "0.087222, 0.109690, 0.175261, 0.460373, 1.524944",\ + "0.145864, 0.166027, 0.220323, 0.470910, 1.526598"); + } + + } /* end of arc padmux2ast_i[2]_obs_ctrl_o[10]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[2]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + values ( "0.094010, 0.121742, 0.192687, 0.448829, 1.352120",\ + "0.181367, 0.209191, 0.280055, 0.536519, 1.439207",\ + "0.278263, 0.306648, 0.378094, 0.633788, 1.536303",\ + "0.454444, 0.484657, 0.556595, 0.813226, 1.718362",\ + "0.755309, 0.792056, 0.870822, 1.124333, 2.025527"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + values ( "0.056753, 0.105860, 0.238203, 0.725444, 2.440521",\ + "0.057457, 0.106111, 0.238203, 0.725444, 2.440521",\ + "0.062809, 0.109450, 0.238891, 0.728499, 2.449750",\ + "0.076809, 0.119663, 0.242773, 0.728499, 2.460771",\ + "0.116537, 0.152614, 0.258265, 0.732313, 2.462313"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + values ( "0.100529, 0.120692, 0.168644, 0.334136, 0.916833",\ + "0.185614, 0.205791, 0.253754, 0.419069, 1.001005",\ + "0.286304, 0.308070, 0.357380, 0.522540, 1.104903",\ + "0.458699, 0.485107, 0.539262, 0.704482, 1.285416",\ + "0.740887, 0.778992, 0.848123, 1.019973, 1.597477"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + values ( "0.045486, 0.074449, 0.152541, 0.452549, 1.519412",\ + "0.046012, 0.074648, 0.152769, 0.453825, 1.520024",\ + "0.056013, 0.082252, 0.156413, 0.454416, 1.520024",\ + "0.082035, 0.104246, 0.169572, 0.457496, 1.520040",\ + "0.139812, 0.159966, 0.214496, 0.467116, 1.522752"); + } + + } /* end of arc padmux2ast_i[2]_obs_ctrl_o[10]_una_min*/ + +} /* end of pin obs_ctrl_o[10] */ + +pin("obs_ctrl_o[9]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.156168 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001432 ; + + /* Other user defined attributes. */ + original_pin : obs_ctrl_o[9]; + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[0]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.560564, 0.740767, 0.928257, 1.230250, 1.813761",\ + "0.590490, 0.770693, 0.958183, 1.260175, 1.843687",\ + "0.662228, 0.842431, 1.029921, 1.331913, 1.915425",\ + "0.918680, 1.098883, 1.286373, 1.588366, 2.171877",\ + "1.830892, 2.011095, 2.198585, 2.500578, 3.084090",\ + "0.645502, 0.826050, 1.014266, 1.316262, 1.900140",\ + "0.675428, 0.855976, 1.044191, 1.346187, 1.930065",\ + "0.747166, 0.927714, 1.115929, 1.417926, 2.001803",\ + "1.003618, 1.184166, 1.372382, 1.674378, 2.258256",\ + "1.915831, 2.096378, 2.284594, 2.586590, 3.170468",\ + "0.721415, 0.901494, 1.089075, 1.390859, 1.974312",\ + "0.751340, 0.931419, 1.119000, 1.420784, 2.004238",\ + "0.823078, 1.003157, 1.190738, 1.492522, 2.075976",\ + "1.079530, 1.259610, 1.447191, 1.748975, 2.332428",\ + "1.991743, 2.171822, 2.359403, 2.661187, 3.244640",\ + "0.775784, 0.956005, 1.143726, 1.445398, 2.028629",\ + "0.805709, 0.985931, 1.173651, 1.475324, 2.058555",\ + "0.877448, 1.057669, 1.245389, 1.547062, 2.130293",\ + "1.133900, 1.314121, 1.501842, 1.803514, 2.386745",\ + "2.046112, 2.226333, 2.414054, 2.715726, 3.298958",\ + "1.057379, 1.241273, 1.427676, 1.729125, 2.311907",\ + "1.087304, 1.271199, 1.457602, 1.759050, 2.341833",\ + "1.159042, 1.342937, 1.529340, 1.830788, 2.413571",\ + "1.415495, 1.599389, 1.785792, 2.087241, 2.670023",\ + "2.327707, 2.511601, 2.698004, 2.999453, 3.582235"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.046137, 0.046137, 0.046137, 0.046137, 0.046137",\ + "0.092740, 0.092740, 0.092740, 0.092740, 0.092740",\ + "0.224143, 0.224143, 0.224143, 0.224143, 0.224143",\ + "0.716280, 0.716280, 0.716280, 0.716280, 0.716280",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\ + "0.046137, 0.046137, 0.046137, 0.046137, 0.046137",\ + "0.092740, 0.092740, 0.092740, 0.092740, 0.092740",\ + "0.224143, 0.224143, 0.224143, 0.224143, 0.224143",\ + "0.716280, 0.716280, 0.716280, 0.716280, 0.716280",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\ + "0.046137, 0.046137, 0.046137, 0.046137, 0.046137",\ + "0.092740, 0.092740, 0.092740, 0.092740, 0.092740",\ + "0.224143, 0.224143, 0.224143, 0.224143, 0.224143",\ + "0.716280, 0.716280, 0.716280, 0.716280, 0.716280",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\ + "0.046137, 0.046137, 0.046137, 0.046137, 0.046137",\ + "0.092740, 0.092740, 0.092740, 0.092740, 0.092740",\ + "0.224143, 0.224143, 0.224143, 0.224143, 0.224143",\ + "0.716280, 0.716280, 0.716280, 0.716280, 0.716280",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\ + "0.046137, 0.046137, 0.046137, 0.046137, 0.046137",\ + "0.092740, 0.092740, 0.092740, 0.092740, 0.092740",\ + "0.224143, 0.224143, 0.224143, 0.224143, 0.224143",\ + "0.716280, 0.716280, 0.716280, 0.716280, 0.716280",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.418380, 0.686166, 0.947746, 1.387443, 2.266838",\ + "0.442754, 0.710540, 0.972120, 1.411817, 2.291212",\ + "0.493609, 0.761395, 1.022975, 1.462672, 2.342067",\ + "0.660045, 0.927830, 1.189410, 1.629108, 2.508502",\ + "1.246765, 1.514551, 1.776131, 2.215828, 3.095223",\ + "0.507084, 0.774241, 1.036387, 1.475672, 2.354243",\ + "0.531458, 0.798615, 1.060761, 1.500046, 2.378617",\ + "0.582313, 0.849470, 1.111616, 1.550901, 2.429472",\ + "0.748749, 1.015905, 1.278051, 1.717337, 2.595908",\ + "1.335469, 1.602626, 1.864772, 2.304057, 3.182628",\ + "0.600027, 0.867386, 1.128112, 1.567836, 2.447285",\ + "0.624401, 0.891760, 1.152486, 1.592211, 2.471659",\ + "0.675255, 0.942615, 1.203341, 1.643065, 2.522514",\ + "0.841691, 1.109051, 1.369777, 1.809501, 2.688950",\ + "1.428411, 1.695771, 1.956497, 2.396221, 3.275670",\ + "0.665870, 0.935950, 1.195132, 1.634687, 2.513796",\ + "0.690244, 0.960324, 1.219506, 1.659061, 2.538170",\ + "0.741099, 1.011179, 1.270361, 1.709916, 2.589025",\ + "0.907535, 1.177615, 1.436797, 1.876351, 2.755461",\ + "1.494255, 1.764335, 2.023517, 2.463071, 3.342181",\ + "1.012392, 1.316786, 1.565795, 2.003840, 2.879932",\ + "1.036766, 1.341160, 1.590169, 2.028214, 2.904306",\ + "1.087620, 1.392015, 1.641024, 2.079069, 2.955161",\ + "1.254056, 1.558450, 1.807460, 2.245505, 3.121596",\ + "1.840776, 2.145171, 2.394180, 2.832225, 3.708317"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.044458, 0.044458, 0.044458, 0.044458, 0.044458",\ + "0.073621, 0.073621, 0.073621, 0.073621, 0.073620",\ + "0.149757, 0.149757, 0.149757, 0.149757, 0.149757",\ + "0.447950, 0.447950, 0.447950, 0.447950, 0.447950",\ + "1.523369, 1.523369, 1.523369, 1.523369, 1.523370",\ + "0.044458, 0.044458, 0.044458, 0.044458, 0.044458",\ + "0.073621, 0.073621, 0.073621, 0.073621, 0.073620",\ + "0.149757, 0.149757, 0.149757, 0.149757, 0.149757",\ + "0.447950, 0.447950, 0.447950, 0.447950, 0.447950",\ + "1.523369, 1.523369, 1.523369, 1.523369, 1.523370",\ + "0.044458, 0.044458, 0.044458, 0.044458, 0.044458",\ + "0.073621, 0.073621, 0.073621, 0.073621, 0.073620",\ + "0.149757, 0.149757, 0.149757, 0.149757, 0.149757",\ + "0.447950, 0.447950, 0.447950, 0.447950, 0.447950",\ + "1.523369, 1.523369, 1.523369, 1.523369, 1.523370",\ + "0.044458, 0.044458, 0.044458, 0.044458, 0.044458",\ + "0.073621, 0.073621, 0.073621, 0.073621, 0.073620",\ + "0.149757, 0.149757, 0.149757, 0.149757, 0.149757",\ + "0.447950, 0.447950, 0.447950, 0.447950, 0.447950",\ + "1.523369, 1.523369, 1.523369, 1.523369, 1.523370",\ + "0.044458, 0.044458, 0.044458, 0.044458, 0.044458",\ + "0.073621, 0.073621, 0.073621, 0.073621, 0.073620",\ + "0.149757, 0.149757, 0.149757, 0.149757, 0.149757",\ + "0.447950, 0.447950, 0.447950, 0.447950, 0.447950",\ + "1.523369, 1.523369, 1.523369, 1.523369, 1.523370"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[9]_redg_2714*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[1]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.468669, 0.732243, 1.008515, 1.477245, 2.414704",\ + "0.498595, 0.762168, 1.038441, 1.507171, 2.444630",\ + "0.570333, 0.833907, 1.110179, 1.578909, 2.516368",\ + "0.826785, 1.090359, 1.366631, 1.835361, 2.772820",\ + "1.738997, 2.002571, 2.278844, 2.747575, 3.685036",\ + "0.556864, 0.819784, 1.096083, 1.563960, 2.500638",\ + "0.586789, 0.849709, 1.126009, 1.593886, 2.530564",\ + "0.658527, 0.921448, 1.197747, 1.665624, 2.602302",\ + "0.914980, 1.177900, 1.454199, 1.922076, 2.858753",\ + "1.827192, 2.090112, 2.366412, 2.834290, 3.770969",\ + "0.645180, 0.908764, 1.184048, 1.651583, 2.587593",\ + "0.675105, 0.938690, 1.213974, 1.681509, 2.617519",\ + "0.746844, 1.010428, 1.285712, 1.753247, 2.689257",\ + "1.003296, 1.266880, 1.542164, 2.009699, 2.945708",\ + "1.915508, 2.179092, 2.454377, 2.921913, 3.857924",\ + "0.707676, 0.974399, 1.248188, 1.715497, 2.651102",\ + "0.737601, 1.004325, 1.278113, 1.745422, 2.681028",\ + "0.809340, 1.076063, 1.349852, 1.817160, 2.752766",\ + "1.065792, 1.332515, 1.606304, 2.073612, 3.009217",\ + "1.978004, 2.244727, 2.518517, 2.985826, 3.921433",\ + "1.036801, 1.338730, 1.600055, 2.064846, 2.996558",\ + "1.066727, 1.368655, 1.629981, 2.094772, 3.026484",\ + "1.138465, 1.440394, 1.701719, 2.166510, 3.098222",\ + "1.394917, 1.696846, 1.958171, 2.422962, 3.354673",\ + "2.307129, 2.609058, 2.870384, 3.335176, 4.266890"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.046137, 0.046137, 0.046137, 0.046137, 0.046136",\ + "0.092740, 0.092740, 0.092740, 0.092740, 0.092740",\ + "0.224143, 0.224143, 0.224142, 0.224142, 0.224142",\ + "0.716281, 0.716280, 0.716280, 0.716278, 0.716274",\ + "2.463890, 2.463890, 2.463889, 2.463887, 2.463883",\ + "0.046137, 0.046137, 0.046137, 0.046137, 0.046136",\ + "0.092740, 0.092740, 0.092740, 0.092740, 0.092740",\ + "0.224143, 0.224143, 0.224142, 0.224142, 0.224142",\ + "0.716281, 0.716280, 0.716280, 0.716278, 0.716274",\ + "2.463890, 2.463890, 2.463889, 2.463887, 2.463883",\ + "0.046137, 0.046137, 0.046137, 0.046137, 0.046136",\ + "0.092740, 0.092740, 0.092740, 0.092740, 0.092740",\ + "0.224143, 0.224143, 0.224142, 0.224142, 0.224142",\ + "0.716281, 0.716280, 0.716280, 0.716278, 0.716274",\ + "2.463890, 2.463890, 2.463889, 2.463887, 2.463883",\ + "0.046137, 0.046137, 0.046137, 0.046137, 0.046136",\ + "0.092740, 0.092740, 0.092740, 0.092740, 0.092740",\ + "0.224143, 0.224143, 0.224142, 0.224142, 0.224142",\ + "0.716281, 0.716280, 0.716280, 0.716278, 0.716274",\ + "2.463890, 2.463890, 2.463889, 2.463887, 2.463883",\ + "0.046137, 0.046137, 0.046137, 0.046137, 0.046136",\ + "0.092740, 0.092740, 0.092740, 0.092740, 0.092740",\ + "0.224143, 0.224143, 0.224142, 0.224142, 0.224142",\ + "0.716281, 0.716280, 0.716280, 0.716278, 0.716274",\ + "2.463890, 2.463890, 2.463889, 2.463887, 2.463883"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.401333, 0.583765, 0.780157, 1.089211, 1.684018",\ + "0.425707, 0.608139, 0.804531, 1.113585, 1.708393",\ + "0.476562, 0.658994, 0.855386, 1.164439, 1.759248",\ + "0.642998, 0.825430, 1.021822, 1.330875, 1.925682",\ + "1.229718, 1.412150, 1.608542, 1.917595, 2.512401",\ + "0.488748, 0.671151, 0.867650, 1.176516, 1.771372",\ + "0.513122, 0.695525, 0.892024, 1.200890, 1.795747",\ + "0.563977, 0.746379, 0.942879, 1.251745, 1.846601",\ + "0.730413, 0.912815, 1.109315, 1.418180, 2.013035",\ + "1.317133, 1.499535, 1.696035, 2.004900, 2.599754",\ + "0.569624, 0.751487, 0.947677, 1.256544, 1.851403",\ + "0.593999, 0.775861, 0.972051, 1.280918, 1.875778",\ + "0.644853, 0.826716, 1.022906, 1.331773, 1.926633",\ + "0.811289, 0.993152, 1.189342, 1.498208, 2.093067",\ + "1.398009, 1.579872, 1.776062, 2.084928, 2.679786",\ + "0.627271, 0.809036, 1.005221, 1.313789, 1.908051",\ + "0.651645, 0.833410, 1.029595, 1.338163, 1.932426",\ + "0.702500, 0.884265, 1.080450, 1.389018, 1.983280",\ + "0.868935, 1.050700, 1.246886, 1.555453, 2.149714",\ + "1.455656, 1.637420, 1.833606, 2.142173, 2.736434",\ + "0.929479, 1.114260, 1.308855, 1.616804, 2.209898",\ + "0.953853, 1.138634, 1.333229, 1.641178, 2.234272",\ + "1.004707, 1.189489, 1.384084, 1.692033, 2.285127",\ + "1.171143, 1.355925, 1.550519, 1.858468, 2.451561",\ + "1.757863, 1.942645, 2.137239, 2.445188, 3.038280"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.044458, 0.044458, 0.044458, 0.044458, 0.044458",\ + "0.073621, 0.073621, 0.073620, 0.073619, 0.073617",\ + "0.149757, 0.149757, 0.149757, 0.149757, 0.149757",\ + "0.447950, 0.447950, 0.447950, 0.447950, 0.447950",\ + "1.523369, 1.523369, 1.523369, 1.523369, 1.523368",\ + "0.044458, 0.044458, 0.044458, 0.044458, 0.044458",\ + "0.073621, 0.073621, 0.073620, 0.073619, 0.073617",\ + "0.149757, 0.149757, 0.149757, 0.149757, 0.149757",\ + "0.447950, 0.447950, 0.447950, 0.447950, 0.447950",\ + "1.523369, 1.523369, 1.523369, 1.523369, 1.523368",\ + "0.044458, 0.044458, 0.044458, 0.044458, 0.044458",\ + "0.073621, 0.073621, 0.073620, 0.073619, 0.073617",\ + "0.149757, 0.149757, 0.149757, 0.149757, 0.149757",\ + "0.447950, 0.447950, 0.447950, 0.447950, 0.447950",\ + "1.523369, 1.523369, 1.523369, 1.523369, 1.523368",\ + "0.044458, 0.044458, 0.044458, 0.044458, 0.044458",\ + "0.073621, 0.073621, 0.073620, 0.073619, 0.073617",\ + "0.149757, 0.149757, 0.149757, 0.149757, 0.149757",\ + "0.447950, 0.447950, 0.447950, 0.447950, 0.447950",\ + "1.523369, 1.523369, 1.523369, 1.523369, 1.523368",\ + "0.044458, 0.044458, 0.044458, 0.044458, 0.044458",\ + "0.073621, 0.073621, 0.073620, 0.073619, 0.073617",\ + "0.149757, 0.149757, 0.149757, 0.149757, 0.149757",\ + "0.447950, 0.447950, 0.447950, 0.447950, 0.447950",\ + "1.523369, 1.523369, 1.523369, 1.523369, 1.523368"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[9]_redg_2644*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[2]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.464694, 0.724323, 0.996195, 1.453075, 2.366835",\ + "0.494620, 0.754249, 1.026121, 1.483001, 2.396760",\ + "0.566358, 0.825987, 1.097859, 1.554739, 2.468498",\ + "0.822810, 1.082439, 1.354311, 1.811191, 2.724950",\ + "1.735022, 1.994652, 2.266525, 2.723405, 3.637166",\ + "0.552799, 0.811857, 1.083726, 1.539791, 2.452769",\ + "0.582724, 0.841782, 1.113652, 1.569716, 2.482694",\ + "0.654463, 0.913521, 1.185390, 1.641454, 2.554432",\ + "0.910915, 1.169973, 1.441842, 1.897906, 2.810884",\ + "1.823127, 2.082185, 2.354055, 2.810120, 3.723099",\ + "0.640829, 0.900823, 1.171690, 1.627413, 2.539724",\ + "0.670754, 0.930748, 1.201616, 1.657339, 2.569649",\ + "0.742493, 1.002486, 1.273354, 1.729077, 2.641387",\ + "0.998945, 1.258938, 1.529806, 1.985529, 2.897839",\ + "1.911157, 2.171151, 2.442019, 2.897743, 3.810054",\ + "0.703050, 0.966436, 1.235828, 1.691327, 2.603233",\ + "0.732976, 0.996362, 1.265754, 1.721252, 2.633158",\ + "0.804714, 1.068100, 1.337492, 1.792991, 2.704896",\ + "1.061166, 1.324552, 1.593944, 2.049443, 2.961348",\ + "1.973378, 2.236765, 2.506157, 2.961657, 3.873563",\ + "1.030438, 1.330511, 1.587575, 2.040628, 2.948689",\ + "1.060363, 1.360437, 1.617501, 2.070553, 2.978614",\ + "1.132102, 1.432175, 1.689239, 2.142292, 3.050352",\ + "1.388554, 1.688627, 1.945691, 2.398743, 3.306804",\ + "2.300766, 2.600840, 2.857904, 3.310957, 4.219019"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.046137, 0.046137, 0.046137, 0.046137, 0.046136",\ + "0.092740, 0.092740, 0.092740, 0.092740, 0.092740",\ + "0.224143, 0.224143, 0.224142, 0.224142, 0.224142",\ + "0.716281, 0.716280, 0.716279, 0.716276, 0.716270",\ + "2.463890, 2.463890, 2.463888, 2.463885, 2.463879",\ + "0.046137, 0.046137, 0.046137, 0.046137, 0.046136",\ + "0.092740, 0.092740, 0.092740, 0.092740, 0.092740",\ + "0.224143, 0.224143, 0.224142, 0.224142, 0.224142",\ + "0.716281, 0.716280, 0.716279, 0.716276, 0.716270",\ + "2.463890, 2.463890, 2.463888, 2.463885, 2.463879",\ + "0.046137, 0.046137, 0.046137, 0.046137, 0.046136",\ + "0.092740, 0.092740, 0.092740, 0.092740, 0.092740",\ + "0.224143, 0.224143, 0.224142, 0.224142, 0.224142",\ + "0.716281, 0.716280, 0.716279, 0.716276, 0.716270",\ + "2.463890, 2.463890, 2.463888, 2.463885, 2.463879",\ + "0.046137, 0.046137, 0.046137, 0.046137, 0.046136",\ + "0.092740, 0.092740, 0.092740, 0.092740, 0.092740",\ + "0.224143, 0.224143, 0.224142, 0.224142, 0.224142",\ + "0.716281, 0.716280, 0.716279, 0.716276, 0.716270",\ + "2.463890, 2.463890, 2.463888, 2.463885, 2.463879",\ + "0.046137, 0.046137, 0.046137, 0.046137, 0.046136",\ + "0.092740, 0.092740, 0.092740, 0.092740, 0.092740",\ + "0.224143, 0.224142, 0.224142, 0.224142, 0.224142",\ + "0.716281, 0.716280, 0.716279, 0.716276, 0.716270",\ + "2.463890, 2.463889, 2.463888, 2.463885, 2.463879"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.399672, 0.582213, 0.778468, 1.087685, 1.682981",\ + "0.424046, 0.606587, 0.802842, 1.112059, 1.707356",\ + "0.474901, 0.657442, 0.853696, 1.162914, 1.758210",\ + "0.641336, 0.823877, 1.020132, 1.329349, 1.924644",\ + "1.228057, 1.410598, 1.606853, 1.916069, 2.511364",\ + "0.487092, 0.669598, 0.865960, 1.174990, 1.770335",\ + "0.511466, 0.693972, 0.890334, 1.199364, 1.794710",\ + "0.562321, 0.744827, 0.941189, 1.250219, 1.845564",\ + "0.728756, 0.911263, 1.107625, 1.416654, 2.011998",\ + "1.315477, 1.497983, 1.694345, 2.003374, 2.598717",\ + "0.567959, 0.749935, 0.945987, 1.255018, 1.850366",\ + "0.592334, 0.774309, 0.970361, 1.279393, 1.874741",\ + "0.643188, 0.825164, 1.021216, 1.330247, 1.925596",\ + "0.809624, 0.991600, 1.187652, 1.496683, 2.092030",\ + "1.396344, 1.578320, 1.774372, 2.083403, 2.678749",\ + "0.625598, 0.807484, 1.003531, 1.312263, 1.907014",\ + "0.649972, 0.831858, 1.027905, 1.336638, 1.931389",\ + "0.700827, 0.882712, 1.078760, 1.387492, 1.982243",\ + "0.867263, 1.049148, 1.245196, 1.553928, 2.148677",\ + "1.453983, 1.635868, 1.831916, 2.140648, 2.735396",\ + "0.927693, 1.112710, 1.307165, 1.615278, 2.208861",\ + "0.952068, 1.137084, 1.331539, 1.639653, 2.233236",\ + "1.002922, 1.187939, 1.382394, 1.690507, 2.284090",\ + "1.169358, 1.354374, 1.548830, 1.856943, 2.450524",\ + "1.756078, 1.941095, 2.135550, 2.443663, 3.037243"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.044458, 0.044458, 0.044458, 0.044458, 0.044458",\ + "0.073621, 0.073621, 0.073620, 0.073619, 0.073617",\ + "0.149757, 0.149757, 0.149757, 0.149757, 0.149757",\ + "0.447950, 0.447950, 0.447950, 0.447950, 0.447950",\ + "1.523369, 1.523369, 1.523369, 1.523369, 1.523367",\ + "0.044458, 0.044458, 0.044458, 0.044458, 0.044458",\ + "0.073621, 0.073621, 0.073620, 0.073619, 0.073617",\ + "0.149757, 0.149757, 0.149757, 0.149757, 0.149757",\ + "0.447950, 0.447950, 0.447950, 0.447950, 0.447950",\ + "1.523369, 1.523369, 1.523369, 1.523369, 1.523367",\ + "0.044458, 0.044458, 0.044458, 0.044458, 0.044458",\ + "0.073621, 0.073621, 0.073620, 0.073619, 0.073617",\ + "0.149757, 0.149757, 0.149757, 0.149757, 0.149757",\ + "0.447950, 0.447950, 0.447950, 0.447950, 0.447950",\ + "1.523369, 1.523369, 1.523369, 1.523369, 1.523367",\ + "0.044458, 0.044458, 0.044458, 0.044458, 0.044458",\ + "0.073621, 0.073621, 0.073620, 0.073619, 0.073617",\ + "0.149757, 0.149757, 0.149757, 0.149757, 0.149757",\ + "0.447950, 0.447950, 0.447950, 0.447950, 0.447950",\ + "1.523369, 1.523369, 1.523369, 1.523369, 1.523367",\ + "0.044458, 0.044458, 0.044458, 0.044458, 0.044458",\ + "0.073621, 0.073621, 0.073620, 0.073619, 0.073617",\ + "0.149757, 0.149757, 0.149757, 0.149757, 0.149757",\ + "0.447950, 0.447950, 0.447950, 0.447950, 0.447950",\ + "1.523369, 1.523369, 1.523369, 1.523369, 1.523367"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[9]_redg_2587*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[3]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.556978, 0.735404, 0.915665, 1.201871, 1.752988",\ + "0.586903, 0.765330, 0.945590, 1.231797, 1.782914",\ + "0.658642, 0.837068, 1.017329, 1.303535, 1.854652",\ + "0.915094, 1.093521, 1.273781, 1.559987, 2.111104",\ + "1.827306, 2.005733, 2.185993, 2.472199, 3.023317",\ + "0.641916, 0.820677, 1.001580, 1.287791, 1.839366",\ + "0.671842, 0.850602, 1.031505, 1.317717, 1.869292",\ + "0.743580, 0.922341, 1.103244, 1.389455, 1.941030",\ + "1.000032, 1.178793, 1.359696, 1.645907, 2.197482",\ + "1.912244, 2.091005, 2.271908, 2.558120, 3.109695",\ + "0.717822, 0.896120, 1.076389, 1.362388, 1.913539",\ + "0.747748, 0.926046, 1.106314, 1.392314, 1.943465",\ + "0.819486, 0.997784, 1.178053, 1.464052, 2.015203",\ + "1.075938, 1.254236, 1.434505, 1.720504, 2.271655",\ + "1.988150, 2.166448, 2.346717, 2.632716, 3.183867",\ + "0.772174, 0.950632, 1.131040, 1.416928, 1.967856",\ + "0.802100, 0.980558, 1.160965, 1.446854, 1.997782",\ + "0.873838, 1.052296, 1.232704, 1.518592, 2.069520",\ + "1.130290, 1.308748, 1.489156, 1.775044, 2.325972",\ + "2.042502, 2.220960, 2.401368, 2.687256, 3.238184",\ + "1.053596, 1.235859, 1.414990, 1.700654, 2.251134",\ + "1.083522, 1.265785, 1.444916, 1.730580, 2.281059",\ + "1.155260, 1.337523, 1.516654, 1.802318, 2.352798",\ + "1.411712, 1.593975, 1.773107, 2.058770, 2.609250",\ + "2.323924, 2.506187, 2.685318, 2.970983, 3.521462"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.046137, 0.046137, 0.046137, 0.046137, 0.046137",\ + "0.092740, 0.092740, 0.092740, 0.092740, 0.092740",\ + "0.224143, 0.224143, 0.224143, 0.224143, 0.224143",\ + "0.716280, 0.716280, 0.716280, 0.716280, 0.716280",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\ + "0.046137, 0.046137, 0.046137, 0.046137, 0.046137",\ + "0.092740, 0.092740, 0.092740, 0.092740, 0.092740",\ + "0.224143, 0.224143, 0.224143, 0.224143, 0.224143",\ + "0.716280, 0.716280, 0.716280, 0.716280, 0.716280",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\ + "0.046137, 0.046137, 0.046137, 0.046137, 0.046137",\ + "0.092740, 0.092740, 0.092740, 0.092740, 0.092740",\ + "0.224143, 0.224143, 0.224143, 0.224143, 0.224143",\ + "0.716280, 0.716280, 0.716280, 0.716280, 0.716280",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\ + "0.046137, 0.046137, 0.046137, 0.046137, 0.046137",\ + "0.092740, 0.092740, 0.092740, 0.092740, 0.092740",\ + "0.224143, 0.224143, 0.224143, 0.224143, 0.224143",\ + "0.716280, 0.716280, 0.716280, 0.716280, 0.716280",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\ + "0.046137, 0.046137, 0.046137, 0.046137, 0.046137",\ + "0.092740, 0.092740, 0.092740, 0.092740, 0.092740",\ + "0.224143, 0.224143, 0.224143, 0.224143, 0.224143",\ + "0.716280, 0.716280, 0.716280, 0.716280, 0.716280",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.416944, 0.682114, 0.941316, 1.377498, 2.249863",\ + "0.441318, 0.706488, 0.965690, 1.401872, 2.274237",\ + "0.492173, 0.757343, 1.016545, 1.452727, 2.325092",\ + "0.658609, 0.923779, 1.182980, 1.619163, 2.491528",\ + "1.245329, 1.510499, 1.769700, 2.205883, 3.078248",\ + "0.505610, 0.770189, 1.029957, 1.465727, 2.337268",\ + "0.529984, 0.794563, 1.054331, 1.490101, 2.361642",\ + "0.580839, 0.845418, 1.105186, 1.540956, 2.412497",\ + "0.747274, 1.011853, 1.271621, 1.707392, 2.578933",\ + "1.333995, 1.598574, 1.858341, 2.294112, 3.165653",\ + "0.598417, 0.863312, 1.121682, 1.557891, 2.430310",\ + "0.622791, 0.887686, 1.146056, 1.582265, 2.454684",\ + "0.673645, 0.938541, 1.196911, 1.633120, 2.505539",\ + "0.840081, 1.104976, 1.363346, 1.799556, 2.671975",\ + "1.426801, 1.691697, 1.950067, 2.386276, 3.258695",\ + "0.664139, 0.931846, 1.188702, 1.624742, 2.496821",\ + "0.688513, 0.956220, 1.213076, 1.649116, 2.521195",\ + "0.739368, 1.007075, 1.263931, 1.699970, 2.572050",\ + "0.905804, 1.173511, 1.430366, 1.866406, 2.738486",\ + "1.492524, 1.760231, 2.017087, 2.453126, 3.325206",\ + "1.009929, 1.312345, 1.559332, 1.993873, 2.862955",\ + "1.034303, 1.336719, 1.583706, 2.018247, 2.887329",\ + "1.085157, 1.387573, 1.634561, 2.069102, 2.938183",\ + "1.251593, 1.554009, 1.800997, 2.235537, 3.104619",\ + "1.838313, 2.140729, 2.387717, 2.822258, 3.691339"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.044458, 0.044458, 0.044458, 0.044458, 0.044458",\ + "0.073621, 0.073621, 0.073621, 0.073621, 0.073620",\ + "0.149757, 0.149757, 0.149757, 0.149757, 0.149757",\ + "0.447950, 0.447950, 0.447950, 0.447950, 0.447950",\ + "1.523369, 1.523369, 1.523369, 1.523369, 1.523370",\ + "0.044458, 0.044458, 0.044458, 0.044458, 0.044458",\ + "0.073621, 0.073621, 0.073621, 0.073621, 0.073620",\ + "0.149757, 0.149757, 0.149757, 0.149757, 0.149757",\ + "0.447950, 0.447950, 0.447950, 0.447950, 0.447950",\ + "1.523369, 1.523369, 1.523369, 1.523369, 1.523370",\ + "0.044458, 0.044458, 0.044458, 0.044458, 0.044458",\ + "0.073621, 0.073621, 0.073621, 0.073621, 0.073620",\ + "0.149757, 0.149757, 0.149757, 0.149757, 0.149757",\ + "0.447950, 0.447950, 0.447950, 0.447950, 0.447950",\ + "1.523369, 1.523369, 1.523369, 1.523369, 1.523370",\ + "0.044458, 0.044458, 0.044458, 0.044458, 0.044458",\ + "0.073621, 0.073621, 0.073621, 0.073621, 0.073620",\ + "0.149757, 0.149757, 0.149757, 0.149757, 0.149757",\ + "0.447950, 0.447950, 0.447950, 0.447950, 0.447950",\ + "1.523369, 1.523369, 1.523369, 1.523369, 1.523370",\ + "0.044458, 0.044458, 0.044458, 0.044458, 0.044458",\ + "0.073621, 0.073621, 0.073621, 0.073621, 0.073620",\ + "0.149757, 0.149757, 0.149757, 0.149757, 0.149757",\ + "0.447950, 0.447950, 0.447950, 0.447950, 0.447950",\ + "1.523369, 1.523369, 1.523369, 1.523369, 1.523370"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[9]_redg_2527*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + values ( "0.324251, 0.354177, 0.425915, 0.682368, 1.594576",\ + "0.411642, 0.441568, 0.513306, 0.769759, 1.681967",\ + "0.492561, 0.522487, 0.594225, 0.850678, 1.762885",\ + "0.550301, 0.580227, 0.651966, 0.908419, 1.820624",\ + "0.853007, 0.882932, 0.954672, 1.211125, 2.123326"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + values ( "0.046138, 0.092741, 0.224144, 0.716261, 2.463871",\ + "0.046138, 0.092741, 0.224221, 0.716261, 2.463871",\ + "0.046138, 0.092741, 0.224454, 0.716261, 2.463871",\ + "0.046138, 0.092741, 0.224454, 0.716261, 2.463871",\ + "0.046298, 0.092766, 0.224788, 0.716274, 2.463884"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + values ( "0.296828, 0.321202, 0.372057, 0.538492, 1.125213",\ + "0.384221, 0.408595, 0.459449, 0.625885, 1.212605",\ + "0.465090, 0.489464, 0.540319, 0.706755, 1.293475",\ + "0.522739, 0.547113, 0.597968, 0.764403, 1.351124",\ + "0.825878, 0.850484, 0.901694, 1.068525, 1.654935"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + values ( "0.044458, 0.073621, 0.149762, 0.447950, 1.524119",\ + "0.044458, 0.073621, 0.149762, 0.447950, 1.524119",\ + "0.044458, 0.073621, 0.149762, 0.447950, 1.523993",\ + "0.044458, 0.073621, 0.149762, 0.447950, 1.523757",\ + "0.044456, 0.073554, 0.149762, 0.447945, 1.523369"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[9]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[0]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.507754, 0.687868, 0.875446, 1.177426, 1.760522",\ + "0.536697, 0.716810, 0.904389, 1.206369, 1.789465",\ + "0.607845, 0.787958, 0.975537, 1.277516, 1.860613",\ + "0.863570, 1.043684, 1.231262, 1.533242, 2.116338",\ + "1.774034, 1.954148, 2.141726, 2.443706, 3.026802",\ + "0.592692, 0.772703, 0.960516, 1.262932, 1.846900",\ + "0.621635, 0.801646, 0.989459, 1.291875, 1.875843",\ + "0.692783, 0.872794, 1.060607, 1.363023, 1.946991",\ + "0.948508, 1.128520, 1.316332, 1.618748, 2.202716",\ + "1.858973, 2.038984, 2.226796, 2.529212, 3.113181",\ + "0.668604, 0.848147, 1.035325, 1.337529, 1.921072",\ + "0.697547, 0.877090, 1.064268, 1.366472, 1.950015",\ + "0.768695, 0.948237, 1.135416, 1.437619, 2.021163",\ + "1.024420, 1.203963, 1.391141, 1.693345, 2.276889",\ + "1.934885, 2.114427, 2.301605, 2.603809, 3.187353",\ + "0.722973, 0.902898, 1.090214, 1.392134, 1.975390",\ + "0.751916, 0.931841, 1.119157, 1.421077, 2.004333",\ + "0.823064, 1.002989, 1.190305, 1.492225, 2.075481",\ + "1.078790, 1.258714, 1.446030, 1.747951, 2.331206",\ + "1.989254, 2.169178, 2.356494, 2.658415, 3.241670",\ + "1.004568, 1.188463, 1.374389, 1.675861, 2.258667",\ + "1.033511, 1.217406, 1.403332, 1.704803, 2.287610",\ + "1.104659, 1.288554, 1.474480, 1.775951, 2.358758",\ + "1.360384, 1.544279, 1.730205, 2.031677, 2.614483",\ + "2.270849, 2.454743, 2.640669, 2.942141, 3.524948"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.043180, 0.043180, 0.043180, 0.043180, 0.043180",\ + "0.090365, 0.090365, 0.090365, 0.090365, 0.090365",\ + "0.222668, 0.222668, 0.222668, 0.222668, 0.222668",\ + "0.712250, 0.712250, 0.712250, 0.712250, 0.712250",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\ + "0.043180, 0.043180, 0.043180, 0.043180, 0.043180",\ + "0.090365, 0.090365, 0.090365, 0.090365, 0.090365",\ + "0.222668, 0.222668, 0.222668, 0.222668, 0.222668",\ + "0.712250, 0.712250, 0.712250, 0.712250, 0.712250",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\ + "0.043180, 0.043180, 0.043180, 0.043180, 0.043180",\ + "0.090365, 0.090365, 0.090365, 0.090365, 0.090365",\ + "0.222668, 0.222668, 0.222668, 0.222668, 0.222668",\ + "0.712250, 0.712250, 0.712250, 0.712250, 0.712250",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\ + "0.043180, 0.043180, 0.043180, 0.043180, 0.043180",\ + "0.090365, 0.090365, 0.090365, 0.090365, 0.090365",\ + "0.222668, 0.222668, 0.222668, 0.222668, 0.222668",\ + "0.712250, 0.712250, 0.712250, 0.712250, 0.712250",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\ + "0.043180, 0.043180, 0.043180, 0.043180, 0.043180",\ + "0.090365, 0.090365, 0.090365, 0.090365, 0.090365",\ + "0.222668, 0.222668, 0.222668, 0.222668, 0.222668",\ + "0.712250, 0.712250, 0.712250, 0.712250, 0.712250",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.389691, 0.657302, 0.918703, 1.358480, 2.237641",\ + "0.411640, 0.679251, 0.940643, 1.380389, 2.259487",\ + "0.459656, 0.727267, 0.988659, 1.428405, 2.307503",\ + "0.624965, 0.892576, 1.153968, 1.593714, 2.472812",\ + "1.214409, 1.482020, 1.743420, 2.183197, 3.062358",\ + "0.478395, 0.745377, 1.007344, 1.446709, 2.325046",\ + "0.500344, 0.767326, 1.029284, 1.468618, 2.346892",\ + "0.548360, 0.815342, 1.077300, 1.516634, 2.394908",\ + "0.713669, 0.980651, 1.242609, 1.681943, 2.560217",\ + "1.303113, 1.570095, 1.832061, 2.271426, 3.149764",\ + "0.571337, 0.838697, 1.099388, 1.538955, 2.418088",\ + "0.593287, 0.860646, 1.121328, 1.560864, 2.439934",\ + "0.641303, 0.908662, 1.169344, 1.608880, 2.487950",\ + "0.806611, 1.073971, 1.334653, 1.774188, 2.653259",\ + "1.396055, 1.663415, 1.924106, 2.363672, 3.242805",\ + "0.637181, 0.907261, 1.166444, 1.605966, 2.485009",\ + "0.659130, 0.929210, 1.188385, 1.627875, 2.506856",\ + "0.707146, 0.977226, 1.236400, 1.675891, 2.554872",\ + "0.872455, 1.142535, 1.401709, 1.841200, 2.720181",\ + "1.461899, 1.731979, 1.991162, 2.430684, 3.309727",\ + "0.983703, 1.288097, 1.537115, 1.975192, 2.851345",\ + "1.005652, 1.310046, 1.559055, 1.997100, 2.873191",\ + "1.053668, 1.358062, 1.607071, 2.045116, 2.921207",\ + "1.218976, 1.523371, 1.772380, 2.210425, 3.086516",\ + "1.808420, 2.112815, 2.361833, 2.799909, 3.676063"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.035869, 0.035869, 0.035869, 0.035869, 0.035869",\ + "0.064692, 0.064692, 0.064692, 0.064692, 0.064692",\ + "0.142526, 0.142526, 0.142526, 0.142526, 0.142526",\ + "0.443427, 0.443427, 0.443427, 0.443428, 0.443428",\ + "1.518709, 1.518709, 1.518709, 1.518709, 1.518710",\ + "0.035869, 0.035869, 0.035869, 0.035869, 0.035869",\ + "0.064692, 0.064692, 0.064692, 0.064692, 0.064692",\ + "0.142526, 0.142526, 0.142526, 0.142526, 0.142526",\ + "0.443427, 0.443427, 0.443427, 0.443428, 0.443428",\ + "1.518709, 1.518709, 1.518709, 1.518709, 1.518710",\ + "0.035869, 0.035869, 0.035869, 0.035869, 0.035869",\ + "0.064692, 0.064692, 0.064692, 0.064692, 0.064692",\ + "0.142526, 0.142526, 0.142526, 0.142526, 0.142526",\ + "0.443427, 0.443427, 0.443427, 0.443428, 0.443428",\ + "1.518709, 1.518709, 1.518709, 1.518709, 1.518710",\ + "0.035869, 0.035869, 0.035869, 0.035869, 0.035869",\ + "0.064692, 0.064692, 0.064692, 0.064692, 0.064692",\ + "0.142526, 0.142526, 0.142526, 0.142526, 0.142526",\ + "0.443427, 0.443427, 0.443427, 0.443428, 0.443428",\ + "1.518709, 1.518709, 1.518709, 1.518709, 1.518710",\ + "0.035869, 0.035869, 0.035869, 0.035869, 0.035869",\ + "0.064692, 0.064692, 0.064692, 0.064692, 0.064692",\ + "0.142526, 0.142526, 0.142526, 0.142526, 0.142526",\ + "0.443427, 0.443427, 0.443427, 0.443428, 0.443428",\ + "1.518709, 1.518709, 1.518709, 1.518709, 1.518710"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[9]_redg_min_2469*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[1]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.415862, 0.679394, 0.955513, 1.423645, 2.358649",\ + "0.444805, 0.708336, 0.984456, 1.452588, 2.387592",\ + "0.515953, 0.779484, 1.055604, 1.523736, 2.458740",\ + "0.771678, 1.035210, 1.311329, 1.779461, 2.714465",\ + "1.682143, 1.945674, 2.221793, 2.689925, 3.624929",\ + "0.504057, 0.766934, 1.043080, 1.510360, 2.444582",\ + "0.532999, 0.795877, 1.072023, 1.539303, 2.473526",\ + "0.604147, 0.867025, 1.143171, 1.610451, 2.544673",\ + "0.859873, 1.122750, 1.398896, 1.866176, 2.800399",\ + "1.770337, 2.033214, 2.309360, 2.776640, 3.710862",\ + "0.592373, 0.855914, 1.131045, 1.598000, 2.531538",\ + "0.621315, 0.884856, 1.159988, 1.626943, 2.560481",\ + "0.692463, 0.956004, 1.231135, 1.698091, 2.631628",\ + "0.948189, 1.211730, 1.486861, 1.953817, 2.887354",\ + "1.858653, 2.122194, 2.397325, 2.864281, 3.797817",\ + "0.654869, 0.921547, 1.195184, 1.662089, 2.595047",\ + "0.683811, 0.950490, 1.224127, 1.691032, 2.623990",\ + "0.754959, 1.021638, 1.295275, 1.762180, 2.695137",\ + "1.010685, 1.277363, 1.551000, 2.017905, 2.950863",\ + "1.921149, 2.187827, 2.461465, 2.928370, 3.861326",\ + "0.983994, 1.285862, 1.547048, 2.011533, 2.940503",\ + "1.012937, 1.314805, 1.575991, 2.040476, 2.969446",\ + "1.084085, 1.385953, 1.647139, 2.111624, 3.040593",\ + "1.339811, 1.641678, 1.902864, 2.367349, 3.296319",\ + "2.250275, 2.552142, 2.813329, 3.277813, 4.206782"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.043180, 0.043180, 0.043181, 0.043181, 0.043182",\ + "0.090365, 0.090365, 0.090365, 0.090365, 0.090366",\ + "0.222668, 0.222668, 0.222668, 0.222668, 0.222668",\ + "0.712250, 0.712250, 0.712249, 0.712249, 0.712248",\ + "2.448223, 2.448223, 2.448224, 2.448226, 2.448230",\ + "0.043180, 0.043180, 0.043181, 0.043181, 0.043182",\ + "0.090365, 0.090365, 0.090365, 0.090365, 0.090366",\ + "0.222668, 0.222668, 0.222668, 0.222668, 0.222668",\ + "0.712250, 0.712250, 0.712249, 0.712249, 0.712248",\ + "2.448223, 2.448223, 2.448224, 2.448226, 2.448230",\ + "0.043180, 0.043180, 0.043181, 0.043181, 0.043182",\ + "0.090365, 0.090365, 0.090365, 0.090365, 0.090366",\ + "0.222668, 0.222668, 0.222668, 0.222668, 0.222668",\ + "0.712250, 0.712250, 0.712249, 0.712249, 0.712248",\ + "2.448223, 2.448223, 2.448224, 2.448226, 2.448230",\ + "0.043180, 0.043180, 0.043181, 0.043181, 0.043182",\ + "0.090365, 0.090365, 0.090365, 0.090365, 0.090366",\ + "0.222668, 0.222668, 0.222668, 0.222668, 0.222668",\ + "0.712250, 0.712250, 0.712249, 0.712249, 0.712248",\ + "2.448223, 2.448223, 2.448224, 2.448226, 2.448230",\ + "0.043180, 0.043181, 0.043181, 0.043181, 0.043182",\ + "0.090365, 0.090365, 0.090365, 0.090365, 0.090366",\ + "0.222668, 0.222668, 0.222668, 0.222668, 0.222668",\ + "0.712250, 0.712250, 0.712249, 0.712249, 0.712248",\ + "2.448223, 2.448223, 2.448224, 2.448226, 2.448230"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.372646, 0.554704, 0.750937, 1.060114, 1.654586",\ + "0.394593, 0.576651, 0.772784, 1.081916, 1.676369",\ + "0.442609, 0.624667, 0.820800, 1.129932, 1.724385",\ + "0.607918, 0.789976, 0.986109, 1.295241, 1.889696",\ + "1.197364, 1.379422, 1.575655, 1.884836, 2.479319",\ + "0.460061, 0.642022, 0.838218, 1.147419, 1.741940",\ + "0.482008, 0.663970, 0.860065, 1.169221, 1.763722",\ + "0.530024, 0.711986, 0.908081, 1.217237, 1.811739",\ + "0.695333, 0.877294, 1.073389, 1.382546, 1.977050",\ + "1.284779, 1.466740, 1.662936, 1.972141, 2.566672",\ + "0.540937, 0.722359, 0.918245, 1.227448, 1.821971",\ + "0.562884, 0.744306, 0.940092, 1.249249, 1.843754",\ + "0.610900, 0.792322, 0.988108, 1.297265, 1.891770",\ + "0.776209, 0.957631, 1.153416, 1.462574, 2.057081",\ + "1.365655, 1.547077, 1.742963, 2.052169, 2.646704",\ + "0.598584, 0.780196, 0.975981, 1.284918, 1.879067",\ + "0.620531, 0.802143, 0.997827, 1.306720, 1.900850",\ + "0.668547, 0.850159, 1.045843, 1.354736, 1.948866",\ + "0.833856, 1.015468, 1.211152, 1.520045, 2.114177",\ + "1.423301, 1.604914, 1.800699, 2.109640, 2.703799",\ + "0.900791, 1.085573, 1.279644, 1.588125, 2.181385",\ + "0.922739, 1.107520, 1.301491, 1.609926, 2.203168",\ + "0.970755, 1.155536, 1.349506, 1.657943, 2.251184",\ + "1.136063, 1.320845, 1.514815, 1.823252, 2.416495",\ + "1.725509, 1.910291, 2.104362, 2.412847, 3.006117"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.035869, 0.035869, 0.035869, 0.035869, 0.035870",\ + "0.064692, 0.064692, 0.064692, 0.064693, 0.064694",\ + "0.142526, 0.142526, 0.142526, 0.142526, 0.142527",\ + "0.443427, 0.443427, 0.443428, 0.443434, 0.443446",\ + "1.518709, 1.518709, 1.518710, 1.518710, 1.518712",\ + "0.035869, 0.035869, 0.035869, 0.035869, 0.035870",\ + "0.064692, 0.064692, 0.064692, 0.064693, 0.064694",\ + "0.142526, 0.142526, 0.142526, 0.142526, 0.142527",\ + "0.443427, 0.443427, 0.443428, 0.443434, 0.443446",\ + "1.518709, 1.518709, 1.518710, 1.518710, 1.518712",\ + "0.035869, 0.035869, 0.035869, 0.035869, 0.035870",\ + "0.064692, 0.064692, 0.064692, 0.064693, 0.064694",\ + "0.142526, 0.142526, 0.142526, 0.142526, 0.142527",\ + "0.443427, 0.443427, 0.443428, 0.443434, 0.443446",\ + "1.518709, 1.518709, 1.518710, 1.518710, 1.518712",\ + "0.035869, 0.035869, 0.035869, 0.035870, 0.035870",\ + "0.064692, 0.064692, 0.064692, 0.064693, 0.064694",\ + "0.142526, 0.142526, 0.142526, 0.142526, 0.142527",\ + "0.443427, 0.443427, 0.443428, 0.443434, 0.443446",\ + "1.518709, 1.518709, 1.518710, 1.518710, 1.518712",\ + "0.035869, 0.035869, 0.035869, 0.035870, 0.035870",\ + "0.064692, 0.064692, 0.064692, 0.064693, 0.064694",\ + "0.142526, 0.142526, 0.142526, 0.142526, 0.142527",\ + "0.443427, 0.443427, 0.443428, 0.443434, 0.443446",\ + "1.518709, 1.518709, 1.518710, 1.518710, 1.518712"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[9]_redg_min_2391*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[2]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.411884, 0.671443, 0.943078, 1.399240, 2.310408",\ + "0.440827, 0.700386, 0.972021, 1.428183, 2.339350",\ + "0.511975, 0.771534, 1.043169, 1.499331, 2.410498",\ + "0.767700, 1.027260, 1.298895, 1.755056, 2.666224",\ + "1.678164, 1.937724, 2.209359, 2.665520, 3.576688",\ + "0.499989, 0.758976, 1.030607, 1.485955, 2.396341",\ + "0.528932, 0.787919, 1.059550, 1.514898, 2.425284",\ + "0.600080, 0.859067, 1.130698, 1.586046, 2.496432",\ + "0.855805, 1.114792, 1.386424, 1.841771, 2.752157",\ + "1.766269, 2.025257, 2.296888, 2.752235, 3.662621",\ + "0.588019, 0.847941, 1.118572, 1.573594, 2.483296",\ + "0.616962, 0.876883, 1.147514, 1.602537, 2.512239",\ + "0.688110, 0.948031, 1.218662, 1.673685, 2.583387",\ + "0.943835, 1.203757, 1.474388, 1.929410, 2.839113",\ + "1.854300, 2.114221, 2.384852, 2.839874, 3.749576",\ + "0.650240, 0.913552, 1.182709, 1.637669, 2.546805",\ + "0.679183, 0.942495, 1.211652, 1.666611, 2.575748",\ + "0.750331, 1.013643, 1.282800, 1.737759, 2.646896",\ + "1.006057, 1.269368, 1.538526, 1.993485, 2.902622",\ + "1.916521, 2.179832, 2.448990, 2.903949, 3.813085",\ + "0.977628, 1.277600, 1.534452, 1.987055, 2.892262",\ + "1.006571, 1.306543, 1.563395, 2.015998, 2.921204",\ + "1.077719, 1.377691, 1.634543, 2.087146, 2.992352",\ + "1.333444, 1.633417, 1.890268, 2.342871, 3.248078",\ + "2.243908, 2.543881, 2.800732, 3.253335, 4.158542"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.043180, 0.043181, 0.043181, 0.043181, 0.043183",\ + "0.090365, 0.090365, 0.090365, 0.090365, 0.090366",\ + "0.222668, 0.222668, 0.222668, 0.222668, 0.222668",\ + "0.712250, 0.712250, 0.712249, 0.712249, 0.712247",\ + "2.448223, 2.448223, 2.448225, 2.448228, 2.448234",\ + "0.043180, 0.043181, 0.043181, 0.043181, 0.043183",\ + "0.090365, 0.090365, 0.090365, 0.090365, 0.090366",\ + "0.222668, 0.222668, 0.222668, 0.222668, 0.222668",\ + "0.712250, 0.712250, 0.712249, 0.712249, 0.712247",\ + "2.448223, 2.448223, 2.448225, 2.448228, 2.448234",\ + "0.043180, 0.043181, 0.043181, 0.043181, 0.043183",\ + "0.090365, 0.090365, 0.090365, 0.090365, 0.090366",\ + "0.222668, 0.222668, 0.222668, 0.222668, 0.222668",\ + "0.712250, 0.712250, 0.712249, 0.712249, 0.712247",\ + "2.448223, 2.448223, 2.448225, 2.448228, 2.448234",\ + "0.043180, 0.043181, 0.043181, 0.043181, 0.043183",\ + "0.090365, 0.090365, 0.090365, 0.090365, 0.090366",\ + "0.222668, 0.222668, 0.222668, 0.222668, 0.222668",\ + "0.712250, 0.712250, 0.712249, 0.712249, 0.712247",\ + "2.448223, 2.448223, 2.448225, 2.448228, 2.448234",\ + "0.043180, 0.043181, 0.043181, 0.043181, 0.043183",\ + "0.090365, 0.090365, 0.090365, 0.090365, 0.090366",\ + "0.222668, 0.222668, 0.222668, 0.222668, 0.222668",\ + "0.712250, 0.712250, 0.712249, 0.712249, 0.712247",\ + "2.448223, 2.448223, 2.448225, 2.448228, 2.448234"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.370982, 0.553150, 0.749248, 1.058587, 1.653547",\ + "0.392932, 0.575099, 0.771096, 1.080389, 1.675331",\ + "0.440948, 0.623115, 0.819112, 1.128405, 1.723348",\ + "0.606257, 0.788424, 0.984421, 1.293715, 1.888659",\ + "1.195700, 1.377868, 1.573966, 1.883303, 2.478263",\ + "0.458403, 0.640469, 0.836529, 1.145892, 1.740901",\ + "0.480352, 0.662418, 0.858377, 1.167694, 1.762685",\ + "0.528368, 0.710434, 0.906393, 1.215710, 1.810701",\ + "0.693677, 0.875743, 1.071702, 1.381020, 1.976012",\ + "1.283120, 1.465186, 1.661247, 1.970608, 2.565616",\ + "0.539270, 0.720805, 0.916556, 1.225920, 1.820932",\ + "0.561219, 0.742755, 0.938404, 1.247723, 1.842716",\ + "0.609235, 0.790771, 0.986420, 1.295739, 1.890733",\ + "0.774544, 0.956080, 1.151728, 1.461048, 2.056044",\ + "1.363988, 1.545523, 1.741274, 2.050637, 2.645648",\ + "0.596909, 0.778642, 0.974291, 1.283391, 1.878029",\ + "0.618858, 0.800592, 0.996139, 1.305194, 1.899813",\ + "0.666874, 0.848608, 1.044155, 1.353210, 1.947829",\ + "0.832183, 1.013916, 1.209464, 1.518519, 2.113140",\ + "1.421627, 1.603360, 1.799009, 2.108108, 2.702744",\ + "0.899004, 1.084021, 1.277955, 1.586599, 2.180348",\ + "0.920954, 1.105970, 1.299802, 1.608401, 2.202132",\ + "0.968969, 1.153986, 1.347818, 1.656417, 2.250149",\ + "1.134278, 1.319295, 1.513127, 1.821727, 2.415460",\ + "1.723722, 1.908738, 2.102673, 2.411315, 3.005064"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.035869, 0.035869, 0.035869, 0.035870, 0.035870",\ + "0.064692, 0.064692, 0.064692, 0.064693, 0.064694",\ + "0.142526, 0.142526, 0.142526, 0.142526, 0.142527",\ + "0.443427, 0.443427, 0.443428, 0.443434, 0.443448",\ + "1.518709, 1.518709, 1.518710, 1.518710, 1.518712",\ + "0.035869, 0.035869, 0.035869, 0.035870, 0.035870",\ + "0.064692, 0.064692, 0.064692, 0.064693, 0.064694",\ + "0.142526, 0.142526, 0.142526, 0.142526, 0.142527",\ + "0.443427, 0.443427, 0.443428, 0.443434, 0.443448",\ + "1.518709, 1.518709, 1.518710, 1.518710, 1.518712",\ + "0.035869, 0.035869, 0.035869, 0.035870, 0.035870",\ + "0.064692, 0.064692, 0.064692, 0.064693, 0.064694",\ + "0.142526, 0.142526, 0.142526, 0.142526, 0.142527",\ + "0.443427, 0.443427, 0.443428, 0.443434, 0.443448",\ + "1.518709, 1.518709, 1.518710, 1.518710, 1.518712",\ + "0.035869, 0.035869, 0.035869, 0.035870, 0.035870",\ + "0.064692, 0.064692, 0.064692, 0.064693, 0.064694",\ + "0.142526, 0.142526, 0.142526, 0.142526, 0.142527",\ + "0.443427, 0.443427, 0.443428, 0.443434, 0.443448",\ + "1.518709, 1.518709, 1.518710, 1.518710, 1.518712",\ + "0.035869, 0.035869, 0.035869, 0.035870, 0.035870",\ + "0.064692, 0.064692, 0.064692, 0.064693, 0.064694",\ + "0.142526, 0.142526, 0.142526, 0.142526, 0.142527",\ + "0.443427, 0.443427, 0.443428, 0.443434, 0.443448",\ + "1.518709, 1.518709, 1.518710, 1.518710, 1.518712"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[9]_redg_min_2332*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[3]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.504167, 0.682507, 0.862854, 1.149040, 1.699793",\ + "0.533110, 0.711450, 0.891797, 1.177983, 1.728736",\ + "0.604258, 0.782598, 0.962945, 1.249131, 1.799884",\ + "0.859984, 1.038323, 1.218670, 1.504856, 2.055609",\ + "1.770448, 1.948787, 2.129134, 2.415321, 2.966074",\ + "0.589106, 0.767343, 0.947924, 1.234547, 1.786172",\ + "0.618049, 0.796286, 0.976867, 1.263489, 1.815114",\ + "0.689197, 0.867433, 1.048015, 1.334637, 1.886262",\ + "0.944922, 1.123159, 1.303740, 1.590363, 2.141988",\ + "1.855386, 2.033623, 2.214204, 2.500827, 3.052452",\ + "0.665012, 0.842786, 1.022733, 1.309143, 1.860344",\ + "0.693955, 0.871729, 1.051676, 1.338086, 1.889287",\ + "0.765103, 0.942877, 1.122823, 1.409234, 1.960435",\ + "1.020828, 1.198602, 1.378549, 1.664959, 2.216160",\ + "1.931292, 2.109066, 2.289013, 2.575424, 3.126625",\ + "0.719364, 0.897532, 1.077598, 1.363737, 1.914661",\ + "0.748307, 0.926474, 1.106541, 1.392680, 1.943604",\ + "0.819455, 0.997622, 1.177689, 1.463828, 2.014752",\ + "1.075180, 1.253348, 1.433414, 1.719553, 2.270478",\ + "1.985644, 2.163812, 2.343878, 2.630017, 3.180942",\ + "1.000786, 1.183049, 1.361751, 1.647463, 2.197939",\ + "1.029729, 1.211992, 1.390694, 1.676406, 2.226882",\ + "1.100877, 1.283140, 1.461842, 1.747554, 2.298030",\ + "1.356602, 1.538865, 1.717567, 2.003279, 2.553755",\ + "2.267066, 2.449329, 2.628031, 2.913743, 3.464219"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.043180, 0.043180, 0.043180, 0.043180, 0.043181",\ + "0.090365, 0.090365, 0.090365, 0.090365, 0.090365",\ + "0.222668, 0.222668, 0.222668, 0.222668, 0.222668",\ + "0.712250, 0.712250, 0.712250, 0.712250, 0.712250",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\ + "0.043180, 0.043180, 0.043180, 0.043180, 0.043181",\ + "0.090365, 0.090365, 0.090365, 0.090365, 0.090365",\ + "0.222668, 0.222668, 0.222668, 0.222668, 0.222668",\ + "0.712250, 0.712250, 0.712250, 0.712250, 0.712250",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\ + "0.043180, 0.043180, 0.043180, 0.043180, 0.043181",\ + "0.090365, 0.090365, 0.090365, 0.090365, 0.090365",\ + "0.222668, 0.222668, 0.222668, 0.222668, 0.222668",\ + "0.712250, 0.712250, 0.712250, 0.712250, 0.712250",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\ + "0.043180, 0.043180, 0.043180, 0.043180, 0.043181",\ + "0.090365, 0.090365, 0.090365, 0.090365, 0.090365",\ + "0.222668, 0.222668, 0.222668, 0.222668, 0.222668",\ + "0.712250, 0.712250, 0.712250, 0.712250, 0.712250",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\ + "0.043180, 0.043180, 0.043180, 0.043180, 0.043181",\ + "0.090365, 0.090365, 0.090365, 0.090365, 0.090365",\ + "0.222668, 0.222668, 0.222668, 0.222668, 0.222668",\ + "0.712250, 0.712250, 0.712250, 0.712250, 0.712250",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.388255, 0.653254, 0.912284, 1.348548, 2.220695",\ + "0.410204, 0.675204, 0.934223, 1.370453, 2.242530",\ + "0.458220, 0.723220, 0.982239, 1.418469, 2.290546",\ + "0.623529, 0.888528, 1.147548, 1.583778, 2.455855",\ + "1.212973, 1.477972, 1.737002, 2.173266, 3.045412",\ + "0.476921, 0.741329, 1.000925, 1.436777, 2.308100",\ + "0.498870, 0.763278, 1.022864, 1.458682, 2.329936",\ + "0.546886, 0.811294, 1.070880, 1.506698, 2.377952",\ + "0.712195, 0.976603, 1.236189, 1.672007, 2.543260",\ + "1.301638, 1.566047, 1.825642, 2.261495, 3.132817",\ + "0.569727, 0.834623, 1.092960, 1.529020, 2.401142",\ + "0.591677, 0.856572, 1.114899, 1.550925, 2.422977",\ + "0.639693, 0.904588, 1.162915, 1.598941, 2.470994",\ + "0.805001, 1.069897, 1.328224, 1.764250, 2.636302",\ + "1.394445, 1.659341, 1.917678, 2.353738, 3.225859",\ + "0.635450, 0.903157, 1.160015, 1.596027, 2.468051",\ + "0.657399, 0.925106, 1.181954, 1.617932, 2.489887",\ + "0.705415, 0.973122, 1.229970, 1.665948, 2.537903",\ + "0.870724, 1.138431, 1.395279, 1.831257, 2.703212",\ + "1.460168, 1.727875, 1.984733, 2.420745, 3.292769",\ + "0.981239, 1.283655, 1.530653, 1.965228, 2.834378",\ + "1.003189, 1.305605, 1.552592, 1.987133, 2.856214",\ + "1.051205, 1.353621, 1.600608, 2.035149, 2.904230",\ + "1.216513, 1.518929, 1.765917, 2.200458, 3.069539",\ + "1.805957, 2.108373, 2.355371, 2.789946, 3.659096"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.035869, 0.035869, 0.035869, 0.035869, 0.035869",\ + "0.064692, 0.064692, 0.064692, 0.064692, 0.064692",\ + "0.142526, 0.142526, 0.142526, 0.142526, 0.142526",\ + "0.443427, 0.443427, 0.443427, 0.443428, 0.443428",\ + "1.518709, 1.518709, 1.518709, 1.518709, 1.518710",\ + "0.035869, 0.035869, 0.035869, 0.035869, 0.035869",\ + "0.064692, 0.064692, 0.064692, 0.064692, 0.064692",\ + "0.142526, 0.142526, 0.142526, 0.142526, 0.142526",\ + "0.443427, 0.443427, 0.443427, 0.443428, 0.443428",\ + "1.518709, 1.518709, 1.518709, 1.518709, 1.518710",\ + "0.035869, 0.035869, 0.035869, 0.035869, 0.035869",\ + "0.064692, 0.064692, 0.064692, 0.064692, 0.064692",\ + "0.142526, 0.142526, 0.142526, 0.142526, 0.142526",\ + "0.443427, 0.443427, 0.443427, 0.443428, 0.443428",\ + "1.518709, 1.518709, 1.518709, 1.518709, 1.518710",\ + "0.035869, 0.035869, 0.035869, 0.035869, 0.035869",\ + "0.064692, 0.064692, 0.064692, 0.064692, 0.064692",\ + "0.142526, 0.142526, 0.142526, 0.142526, 0.142526",\ + "0.443427, 0.443427, 0.443427, 0.443428, 0.443429",\ + "1.518709, 1.518709, 1.518709, 1.518709, 1.518710",\ + "0.035869, 0.035869, 0.035869, 0.035869, 0.035869",\ + "0.064692, 0.064692, 0.064692, 0.064692, 0.064692",\ + "0.142526, 0.142526, 0.142526, 0.142526, 0.142526",\ + "0.443427, 0.443427, 0.443427, 0.443428, 0.443429",\ + "1.518709, 1.518709, 1.518709, 1.518709, 1.518710"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[9]_redg_min_2273*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + values ( "0.141721, 0.170980, 0.242593, 0.498866, 1.411098",\ + "0.229906, 0.259165, 0.330790, 0.587108, 1.499024",\ + "0.318231, 0.347489, 0.419118, 0.675627, 1.587106",\ + "0.380823, 0.410078, 0.481658, 0.738460, 1.650402",\ + "0.710704, 0.739954, 0.811356, 1.068597, 1.982165"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + values ( "0.043180, 0.090365, 0.222668, 0.712250, 2.448223",\ + "0.043180, 0.090365, 0.222668, 0.712250, 2.448223",\ + "0.043180, 0.090365, 0.222668, 0.712250, 2.448223",\ + "0.043180, 0.090365, 0.222668, 0.712250, 2.448223",\ + "0.043180, 0.090365, 0.222668, 0.712250, 2.448223"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + values ( "0.179981, 0.202635, 0.251659, 0.417360, 1.003853",\ + "0.267384, 0.290039, 0.339062, 0.504764, 1.091257",\ + "0.348282, 0.370934, 0.419962, 0.585668, 1.172170",\ + "0.405945, 0.428592, 0.477629, 0.643342, 1.229861",\ + "0.708302, 0.730939, 0.780004, 0.945787, 1.532477"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + values ( "0.035869, 0.064690, 0.142524, 0.442595, 1.516425",\ + "0.035869, 0.064690, 0.142524, 0.442595, 1.516425",\ + "0.035869, 0.064690, 0.142524, 0.442641, 1.516425",\ + "0.035869, 0.064690, 0.142524, 0.442726, 1.516425",\ + "0.035869, 0.064691, 0.142524, 0.443427, 1.516425"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[9]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_falling ; + clock_gating_flag : true ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.146678, 0.146678, 0.146678, 0.146678, 0.146678",\ + "0.165298, 0.165298, 0.165298, 0.165298, 0.165298",\ + "0.241802, 0.241802, 0.241802, 0.241802, 0.241802",\ + "0.367706, 0.367706, 0.367706, 0.367706, 0.367706",\ + "0.946794, 0.946794, 0.946794, 0.946794, 0.946794"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.412191, 0.412191, 0.412191, 0.412191, 0.412191",\ + "0.424880, 0.424880, 0.424880, 0.424880, 0.424880",\ + "0.479563, 0.479563, 0.479563, 0.479563, 0.479563",\ + "0.581996, 0.581996, 0.581996, 0.581996, 0.581996",\ + "1.256928, 1.256928, 1.256928, 1.256928, 1.256928"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[9]_cgsf*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + clock_gating_flag : true ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.138937, -0.138937, -0.138937, -0.138937, -0.138937",\ + "-0.155751, -0.155751, -0.155751, -0.155751, -0.155751",\ + "-0.234216, -0.234216, -0.234216, -0.234216, -0.234216",\ + "-0.360721, -0.360721, -0.360721, -0.360721, -0.360721",\ + "-0.939265, -0.939265, -0.939265, -0.939265, -0.939265"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.408326, -0.408326, -0.408326, -0.408326, -0.408326",\ + "-0.417967, -0.417967, -0.417967, -0.417967, -0.417967",\ + "-0.475689, -0.475689, -0.475689, -0.475689, -0.475689",\ + "-0.578062, -0.578062, -0.578062, -0.578062, -0.578062",\ + "-1.250684, -1.250684, -1.250684, -1.250684, -1.250684"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[9]_cghr*/ + + timing () { + related_pin : "padmux2ast_i[1]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + values ( "0.088963, 0.118659, 0.189985, 0.445909, 1.359203",\ + "0.176595, 0.206339, 0.277538, 0.533662, 1.444562",\ + "0.274330, 0.305634, 0.377516, 0.633363, 1.547694",\ + "0.452110, 0.487212, 0.561030, 0.816620, 1.732299",\ + "0.755237, 0.801656, 0.884430, 1.139988, 2.048527"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + values ( "0.044962, 0.091670, 0.223831, 0.718456, 2.481454",\ + "0.045846, 0.091918, 0.223831, 0.720074, 2.481454",\ + "0.052795, 0.096494, 0.223831, 0.720074, 2.481454",\ + "0.070125, 0.108925, 0.227741, 0.720074, 2.481454",\ + "0.113963, 0.145559, 0.246252, 0.720074, 2.481454"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + values ( "0.127301, 0.151950, 0.203155, 0.369998, 0.957371",\ + "0.206362, 0.230972, 0.282119, 0.448933, 1.035102",\ + "0.309711, 0.336083, 0.388248, 0.554957, 1.142995",\ + "0.487304, 0.519754, 0.577312, 0.745501, 1.332624",\ + "0.775221, 0.823575, 0.896452, 1.070131, 1.655247"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + values ( "0.044715, 0.073858, 0.149782, 0.448303, 1.525169",\ + "0.044715, 0.073858, 0.149782, 0.448303, 1.525169",\ + "0.053324, 0.079575, 0.152471, 0.448303, 1.525169",\ + "0.080832, 0.102703, 0.166343, 0.450943, 1.525169",\ + "0.138432, 0.160382, 0.212572, 0.461516, 1.526821"); + } + + } /* end of arc padmux2ast_i[1]_obs_ctrl_o[9]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[1]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + values ( "0.084586, 0.113378, 0.184446, 0.440600, 1.352120",\ + "0.171768, 0.200846, 0.271799, 0.528276, 1.439207",\ + "0.268285, 0.298195, 0.369868, 0.625566, 1.536303",\ + "0.442396, 0.476138, 0.548327, 0.804981, 1.718362",\ + "0.738546, 0.782374, 0.862671, 1.116124, 2.025527"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + values ( "0.042344, 0.090303, 0.222464, 0.709820, 2.440521",\ + "0.043472, 0.090646, 0.222464, 0.709820, 2.440521",\ + "0.049500, 0.094474, 0.223126, 0.712718, 2.449750",\ + "0.065555, 0.105654, 0.227159, 0.712718, 2.460771",\ + "0.105524, 0.141324, 0.243057, 0.716552, 2.462313"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + values ( "0.093008, 0.115079, 0.163442, 0.328951, 0.916956",\ + "0.178087, 0.200175, 0.248558, 0.413891, 1.001128",\ + "0.277566, 0.302239, 0.352189, 0.517358, 1.105026",\ + "0.446802, 0.478509, 0.534068, 0.699312, 1.285539",\ + "0.721986, 0.770109, 0.842702, 1.014834, 1.597599"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + values ( "0.036627, 0.065671, 0.143118, 0.443055, 1.519637",\ + "0.037498, 0.065879, 0.143311, 0.444331, 1.520249",\ + "0.048608, 0.074072, 0.147057, 0.444933, 1.520249",\ + "0.075730, 0.097335, 0.160558, 0.448031, 1.520263",\ + "0.132420, 0.154310, 0.206677, 0.457722, 1.522974"); + } + + } /* end of arc padmux2ast_i[1]_obs_ctrl_o[9]_una_min*/ + +} /* end of pin obs_ctrl_o[9] */ + +pin("obs_ctrl_o[8]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.156168 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001401 ; + + /* Other user defined attributes. */ + original_pin : obs_ctrl_o[8]; + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[0]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.560256, 0.740460, 0.927949, 1.229942, 1.813454",\ + "0.590229, 0.770432, 0.957922, 1.259915, 1.843426",\ + "0.661974, 0.842177, 1.029667, 1.331659, 1.915171",\ + "0.918426, 1.098629, 1.286119, 1.588112, 2.171624",\ + "1.830892, 2.011095, 2.198585, 2.500578, 3.084090",\ + "0.645195, 0.825743, 1.013958, 1.315954, 1.899832",\ + "0.675168, 0.855715, 1.043931, 1.345927, 1.929805",\ + "0.746912, 0.927460, 1.115675, 1.417671, 2.001549",\ + "1.003365, 1.183912, 1.372128, 1.674124, 2.258002",\ + "1.915831, 2.096378, 2.284594, 2.586590, 3.170468",\ + "0.721107, 0.901186, 1.088767, 1.390551, 1.974005",\ + "0.751079, 0.931159, 1.118740, 1.420524, 2.003977",\ + "0.822824, 1.002903, 1.190484, 1.492268, 2.075722",\ + "1.079277, 1.259356, 1.446937, 1.748721, 2.332174",\ + "1.991743, 2.171822, 2.359403, 2.661187, 3.244640",\ + "0.775476, 0.955698, 1.143418, 1.445091, 2.028322",\ + "0.805449, 0.985670, 1.173391, 1.475063, 2.058295",\ + "0.877193, 1.057415, 1.245135, 1.546808, 2.130039",\ + "1.133646, 1.313868, 1.501588, 1.803261, 2.386492",\ + "2.046112, 2.226333, 2.414054, 2.715726, 3.298958",\ + "1.057071, 1.240966, 1.427369, 1.728817, 2.311599",\ + "1.087044, 1.270938, 1.457341, 1.758790, 2.341572",\ + "1.158788, 1.342683, 1.529086, 1.830534, 2.413317",\ + "1.415241, 1.599136, 1.785538, 2.086987, 2.669769",\ + "2.327707, 2.511601, 2.698004, 2.999453, 3.582235"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.045710, 0.045710, 0.045710, 0.045710, 0.045710",\ + "0.092269, 0.092269, 0.092269, 0.092269, 0.092269",\ + "0.223657, 0.223657, 0.223657, 0.223657, 0.223657",\ + "0.715794, 0.715794, 0.715794, 0.715794, 0.715794",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\ + "0.045710, 0.045710, 0.045710, 0.045710, 0.045710",\ + "0.092269, 0.092269, 0.092269, 0.092269, 0.092269",\ + "0.223657, 0.223657, 0.223657, 0.223657, 0.223657",\ + "0.715794, 0.715794, 0.715794, 0.715794, 0.715794",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\ + "0.045710, 0.045710, 0.045710, 0.045710, 0.045710",\ + "0.092269, 0.092269, 0.092269, 0.092269, 0.092269",\ + "0.223657, 0.223657, 0.223657, 0.223657, 0.223657",\ + "0.715794, 0.715794, 0.715794, 0.715794, 0.715794",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\ + "0.045710, 0.045710, 0.045710, 0.045710, 0.045710",\ + "0.092269, 0.092269, 0.092269, 0.092269, 0.092269",\ + "0.223657, 0.223657, 0.223657, 0.223657, 0.223657",\ + "0.715794, 0.715794, 0.715794, 0.715794, 0.715794",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\ + "0.045710, 0.045710, 0.045710, 0.045710, 0.045710",\ + "0.092269, 0.092269, 0.092269, 0.092269, 0.092269",\ + "0.223657, 0.223657, 0.223657, 0.223657, 0.223657",\ + "0.715794, 0.715794, 0.715794, 0.715794, 0.715794",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.418156, 0.685942, 0.947522, 1.387219, 2.266614",\ + "0.442597, 0.710383, 0.971963, 1.411660, 2.291055",\ + "0.493471, 0.761257, 1.022837, 1.462534, 2.341929",\ + "0.659908, 0.927694, 1.189274, 1.628971, 2.508366",\ + "1.246791, 1.514577, 1.776157, 2.215854, 3.095249",\ + "0.506860, 0.774017, 1.036163, 1.475448, 2.354019",\ + "0.531302, 0.798458, 1.060604, 1.499889, 2.378460",\ + "0.582175, 0.849332, 1.111478, 1.550763, 2.429334",\ + "0.748612, 1.015769, 1.277915, 1.717200, 2.595771",\ + "1.335496, 1.602652, 1.864798, 2.304084, 3.182654",\ + "0.599803, 0.867162, 1.127888, 1.567612, 2.447061",\ + "0.624244, 0.891603, 1.152330, 1.592054, 2.471502",\ + "0.675117, 0.942477, 1.203203, 1.642927, 2.522376",\ + "0.841555, 1.108914, 1.369640, 1.809364, 2.688813",\ + "1.428438, 1.695797, 1.956524, 2.396248, 3.275696",\ + "0.665646, 0.935726, 1.194908, 1.634463, 2.513572",\ + "0.690087, 0.960168, 1.219349, 1.658904, 2.538013",\ + "0.740961, 1.011041, 1.270223, 1.709777, 2.588887",\ + "0.907398, 1.177478, 1.436660, 1.876215, 2.755324",\ + "1.494281, 1.764362, 2.023544, 2.463098, 3.342207",\ + "1.012168, 1.316562, 1.565571, 2.003616, 2.879708",\ + "1.036609, 1.341003, 1.590012, 2.028058, 2.904149",\ + "1.087482, 1.391877, 1.640886, 2.078931, 2.955022",\ + "1.253920, 1.558314, 1.807323, 2.245368, 3.121460",\ + "1.840803, 2.145197, 2.394207, 2.832252, 3.708343"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.044220, 0.044220, 0.044220, 0.044220, 0.044220",\ + "0.073393, 0.073393, 0.073393, 0.073393, 0.073393",\ + "0.149510, 0.149510, 0.149510, 0.149510, 0.149510",\ + "0.447701, 0.447701, 0.447701, 0.447701, 0.447701",\ + "1.523418, 1.523418, 1.523418, 1.523418, 1.523419",\ + "0.044220, 0.044220, 0.044220, 0.044220, 0.044220",\ + "0.073393, 0.073393, 0.073393, 0.073393, 0.073393",\ + "0.149510, 0.149510, 0.149510, 0.149510, 0.149510",\ + "0.447701, 0.447701, 0.447701, 0.447701, 0.447701",\ + "1.523418, 1.523418, 1.523418, 1.523418, 1.523419",\ + "0.044220, 0.044220, 0.044220, 0.044220, 0.044220",\ + "0.073393, 0.073393, 0.073393, 0.073393, 0.073393",\ + "0.149510, 0.149510, 0.149510, 0.149510, 0.149510",\ + "0.447701, 0.447701, 0.447701, 0.447701, 0.447701",\ + "1.523418, 1.523418, 1.523418, 1.523418, 1.523419",\ + "0.044220, 0.044220, 0.044220, 0.044220, 0.044220",\ + "0.073393, 0.073393, 0.073393, 0.073393, 0.073393",\ + "0.149510, 0.149510, 0.149510, 0.149510, 0.149510",\ + "0.447701, 0.447701, 0.447701, 0.447701, 0.447701",\ + "1.523418, 1.523418, 1.523418, 1.523418, 1.523419",\ + "0.044220, 0.044220, 0.044220, 0.044220, 0.044220",\ + "0.073393, 0.073393, 0.073393, 0.073393, 0.073393",\ + "0.149510, 0.149510, 0.149510, 0.149510, 0.149510",\ + "0.447701, 0.447701, 0.447701, 0.447701, 0.447701",\ + "1.523418, 1.523418, 1.523418, 1.523418, 1.523419"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[8]_redg_2698*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[1]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.468362, 0.731935, 1.008208, 1.476938, 2.414397",\ + "0.498334, 0.761908, 1.038180, 1.506910, 2.444369",\ + "0.570079, 0.833652, 1.109925, 1.578655, 2.516114",\ + "0.826532, 1.090105, 1.366378, 1.835107, 2.772566",\ + "1.738997, 2.002571, 2.278844, 2.747575, 3.685036",\ + "0.556556, 0.819476, 1.095776, 1.563653, 2.500330",\ + "0.586529, 0.849449, 1.125748, 1.593625, 2.530303",\ + "0.658273, 0.921193, 1.197493, 1.665370, 2.602047",\ + "0.914726, 1.177646, 1.453945, 1.921822, 2.858500",\ + "1.827192, 2.090112, 2.366412, 2.834290, 3.770969",\ + "0.644872, 0.908457, 1.183741, 1.651275, 2.587286",\ + "0.674845, 0.938429, 1.213713, 1.681248, 2.617258",\ + "0.746589, 1.010174, 1.285458, 1.752992, 2.689003",\ + "1.003042, 1.266626, 1.541910, 2.009445, 2.945455",\ + "1.915508, 2.179092, 2.454377, 2.921913, 3.857924",\ + "0.707368, 0.974091, 1.247880, 1.715189, 2.650795",\ + "0.737341, 1.004064, 1.277853, 1.745162, 2.680767",\ + "0.809085, 1.075809, 1.349597, 1.816906, 2.752512",\ + "1.065538, 1.332261, 1.606050, 2.073359, 3.008964",\ + "1.978004, 2.244727, 2.518517, 2.985826, 3.921433",\ + "1.036494, 1.338422, 1.599747, 2.064539, 2.996251",\ + "1.066466, 1.368395, 1.629720, 2.094511, 3.026223",\ + "1.138211, 1.440139, 1.701465, 2.166256, 3.097968",\ + "1.394664, 1.696592, 1.957917, 2.422708, 3.354420",\ + "2.307129, 2.609058, 2.870384, 3.335176, 4.266890"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.045710, 0.045710, 0.045710, 0.045710, 0.045709",\ + "0.092269, 0.092269, 0.092269, 0.092269, 0.092269",\ + "0.223657, 0.223657, 0.223657, 0.223656, 0.223656",\ + "0.715794, 0.715794, 0.715793, 0.715792, 0.715788",\ + "2.463890, 2.463890, 2.463889, 2.463887, 2.463883",\ + "0.045710, 0.045710, 0.045710, 0.045710, 0.045709",\ + "0.092269, 0.092269, 0.092269, 0.092269, 0.092269",\ + "0.223657, 0.223657, 0.223657, 0.223656, 0.223656",\ + "0.715794, 0.715794, 0.715793, 0.715792, 0.715788",\ + "2.463890, 2.463890, 2.463889, 2.463887, 2.463883",\ + "0.045710, 0.045710, 0.045710, 0.045710, 0.045709",\ + "0.092269, 0.092269, 0.092269, 0.092269, 0.092269",\ + "0.223657, 0.223657, 0.223657, 0.223656, 0.223656",\ + "0.715794, 0.715794, 0.715793, 0.715792, 0.715788",\ + "2.463890, 2.463890, 2.463889, 2.463887, 2.463883",\ + "0.045710, 0.045710, 0.045710, 0.045710, 0.045709",\ + "0.092269, 0.092269, 0.092269, 0.092269, 0.092269",\ + "0.223657, 0.223657, 0.223657, 0.223656, 0.223656",\ + "0.715794, 0.715794, 0.715793, 0.715792, 0.715788",\ + "2.463890, 2.463890, 2.463889, 2.463887, 2.463883",\ + "0.045710, 0.045710, 0.045710, 0.045710, 0.045709",\ + "0.092269, 0.092269, 0.092269, 0.092269, 0.092269",\ + "0.223657, 0.223657, 0.223657, 0.223656, 0.223656",\ + "0.715794, 0.715794, 0.715793, 0.715792, 0.715788",\ + "2.463890, 2.463890, 2.463889, 2.463887, 2.463883"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.401109, 0.583541, 0.779933, 1.088987, 1.683794",\ + "0.425551, 0.607982, 0.804374, 1.113428, 1.708236",\ + "0.476424, 0.658856, 0.855248, 1.164301, 1.759109",\ + "0.642861, 0.825293, 1.021685, 1.330738, 1.925545",\ + "1.229745, 1.412177, 1.608569, 1.917621, 2.512428",\ + "0.488524, 0.670927, 0.867426, 1.176292, 1.771148",\ + "0.512965, 0.695368, 0.891868, 1.200733, 1.795590",\ + "0.563839, 0.746242, 0.942741, 1.251606, 1.846463",\ + "0.730276, 0.912679, 1.109178, 1.418043, 2.012899",\ + "1.317160, 1.499562, 1.696062, 2.004926, 2.599781",\ + "0.569400, 0.751263, 0.947453, 1.256320, 1.851179",\ + "0.593842, 0.775705, 0.971894, 1.280761, 1.875621",\ + "0.644715, 0.826578, 1.022768, 1.331635, 1.926494",\ + "0.811152, 0.993015, 1.189205, 1.498072, 2.092930",\ + "1.398036, 1.579899, 1.776089, 2.084955, 2.679813",\ + "0.627047, 0.808812, 1.004997, 1.313565, 1.907827",\ + "0.651488, 0.833253, 1.029438, 1.338006, 1.932269",\ + "0.702362, 0.884127, 1.080312, 1.388880, 1.983142",\ + "0.868799, 1.050564, 1.246749, 1.555317, 2.149578",\ + "1.455682, 1.637447, 1.833632, 2.142200, 2.736460",\ + "0.929255, 1.114036, 1.308631, 1.616580, 2.209674",\ + "0.953696, 1.138477, 1.333072, 1.641021, 2.234116",\ + "1.004569, 1.189351, 1.383945, 1.691895, 2.284989",\ + "1.171007, 1.355788, 1.550383, 1.858332, 2.451425",\ + "1.757890, 1.942672, 2.137266, 2.445215, 3.038307"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.044220, 0.044220, 0.044220, 0.044220, 0.044220",\ + "0.073393, 0.073393, 0.073393, 0.073392, 0.073390",\ + "0.149511, 0.149511, 0.149511, 0.149511, 0.149511",\ + "0.447701, 0.447701, 0.447701, 0.447701, 0.447701",\ + "1.523418, 1.523418, 1.523418, 1.523418, 1.523417",\ + "0.044220, 0.044220, 0.044220, 0.044220, 0.044220",\ + "0.073393, 0.073393, 0.073393, 0.073392, 0.073390",\ + "0.149511, 0.149511, 0.149511, 0.149511, 0.149511",\ + "0.447701, 0.447701, 0.447701, 0.447701, 0.447701",\ + "1.523418, 1.523418, 1.523418, 1.523418, 1.523417",\ + "0.044220, 0.044220, 0.044220, 0.044220, 0.044220",\ + "0.073393, 0.073393, 0.073393, 0.073392, 0.073390",\ + "0.149511, 0.149511, 0.149511, 0.149511, 0.149511",\ + "0.447701, 0.447701, 0.447701, 0.447701, 0.447701",\ + "1.523418, 1.523418, 1.523418, 1.523418, 1.523417",\ + "0.044220, 0.044220, 0.044220, 0.044220, 0.044220",\ + "0.073393, 0.073393, 0.073393, 0.073392, 0.073390",\ + "0.149511, 0.149511, 0.149511, 0.149511, 0.149511",\ + "0.447701, 0.447701, 0.447701, 0.447701, 0.447701",\ + "1.523418, 1.523418, 1.523418, 1.523418, 1.523417",\ + "0.044220, 0.044220, 0.044220, 0.044220, 0.044220",\ + "0.073393, 0.073393, 0.073393, 0.073392, 0.073390",\ + "0.149511, 0.149511, 0.149511, 0.149511, 0.149511",\ + "0.447701, 0.447701, 0.447701, 0.447701, 0.447701",\ + "1.523418, 1.523418, 1.523418, 1.523418, 1.523417"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[8]_redg_2629*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[2]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.464386, 0.724016, 0.995888, 1.452767, 2.366527",\ + "0.494359, 0.753988, 1.025861, 1.482740, 2.396500",\ + "0.566104, 0.825733, 1.097605, 1.554485, 2.468244",\ + "0.822556, 1.082185, 1.354057, 1.810937, 2.724696",\ + "1.735022, 1.994652, 2.266525, 2.723405, 3.637166",\ + "0.552491, 0.811549, 1.083418, 1.539483, 2.452461",\ + "0.582464, 0.841522, 1.113391, 1.569456, 2.482434",\ + "0.654208, 0.913266, 1.185135, 1.641200, 2.554178",\ + "0.910661, 1.169719, 1.441588, 1.897652, 2.810630",\ + "1.823127, 2.082185, 2.354055, 2.810120, 3.723099",\ + "0.640521, 0.900515, 1.171383, 1.627106, 2.539416",\ + "0.670494, 0.930488, 1.201355, 1.657078, 2.569389",\ + "0.742239, 1.002232, 1.273100, 1.728823, 2.641133",\ + "0.998691, 1.258685, 1.529552, 1.985275, 2.897585",\ + "1.911157, 2.171151, 2.442019, 2.897743, 3.810054",\ + "0.702743, 0.966129, 1.235520, 1.691019, 2.602925",\ + "0.732715, 0.996101, 1.265493, 1.720992, 2.632898",\ + "0.804460, 1.067846, 1.337237, 1.792736, 2.704642",\ + "1.060912, 1.324298, 1.593690, 2.049189, 2.961094",\ + "1.973378, 2.236765, 2.506157, 2.961657, 3.873563",\ + "1.030130, 1.330203, 1.587268, 2.040320, 2.948381",\ + "1.060103, 1.360176, 1.617240, 2.070293, 2.978354",\ + "1.131847, 1.431921, 1.688985, 2.142037, 3.050098",\ + "1.388300, 1.688373, 1.945437, 2.398489, 3.306550",\ + "2.300766, 2.600840, 2.857904, 3.310957, 4.219019"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.045710, 0.045710, 0.045710, 0.045710, 0.045709",\ + "0.092269, 0.092269, 0.092269, 0.092269, 0.092269",\ + "0.223657, 0.223657, 0.223657, 0.223656, 0.223656",\ + "0.715794, 0.715794, 0.715793, 0.715790, 0.715784",\ + "2.463890, 2.463890, 2.463888, 2.463885, 2.463879",\ + "0.045710, 0.045710, 0.045710, 0.045710, 0.045709",\ + "0.092269, 0.092269, 0.092269, 0.092269, 0.092269",\ + "0.223657, 0.223657, 0.223657, 0.223656, 0.223656",\ + "0.715794, 0.715794, 0.715793, 0.715790, 0.715784",\ + "2.463890, 2.463890, 2.463888, 2.463885, 2.463879",\ + "0.045710, 0.045710, 0.045710, 0.045710, 0.045709",\ + "0.092269, 0.092269, 0.092269, 0.092269, 0.092269",\ + "0.223657, 0.223657, 0.223657, 0.223656, 0.223656",\ + "0.715794, 0.715794, 0.715793, 0.715790, 0.715784",\ + "2.463890, 2.463890, 2.463888, 2.463885, 2.463879",\ + "0.045710, 0.045710, 0.045710, 0.045710, 0.045709",\ + "0.092269, 0.092269, 0.092269, 0.092269, 0.092269",\ + "0.223657, 0.223657, 0.223657, 0.223656, 0.223656",\ + "0.715794, 0.715794, 0.715793, 0.715790, 0.715784",\ + "2.463890, 2.463890, 2.463888, 2.463885, 2.463879",\ + "0.045710, 0.045710, 0.045710, 0.045710, 0.045709",\ + "0.092269, 0.092269, 0.092269, 0.092269, 0.092269",\ + "0.223657, 0.223657, 0.223657, 0.223656, 0.223656",\ + "0.715794, 0.715794, 0.715793, 0.715790, 0.715784",\ + "2.463890, 2.463889, 2.463888, 2.463885, 2.463879"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.399448, 0.581989, 0.778244, 1.087461, 1.682757",\ + "0.423889, 0.606430, 0.802685, 1.111902, 1.707199",\ + "0.474763, 0.657304, 0.853558, 1.162776, 1.758072",\ + "0.641200, 0.823741, 1.019996, 1.329213, 1.924508",\ + "1.228083, 1.410624, 1.606879, 1.916096, 2.511390",\ + "0.486868, 0.669374, 0.865736, 1.174766, 1.770111",\ + "0.511309, 0.693815, 0.890178, 1.199207, 1.794553",\ + "0.562183, 0.744689, 0.941051, 1.250081, 1.845426",\ + "0.728620, 0.911126, 1.107488, 1.416518, 2.011862",\ + "1.315503, 1.498010, 1.694372, 2.003401, 2.598744",\ + "0.567735, 0.749711, 0.945763, 1.254794, 1.850142",\ + "0.592177, 0.774152, 0.970205, 1.279236, 1.874584",\ + "0.643050, 0.825026, 1.021078, 1.330109, 1.925457",\ + "0.809487, 0.991463, 1.187515, 1.496546, 2.091893",\ + "1.396371, 1.578347, 1.774399, 2.083429, 2.678775",\ + "0.625374, 0.807260, 1.003307, 1.312040, 1.906790",\ + "0.649816, 0.831701, 1.027748, 1.336481, 1.931232",\ + "0.700689, 0.882574, 1.078622, 1.387354, 1.982105",\ + "0.867126, 1.049011, 1.245059, 1.553791, 2.148541",\ + "1.454010, 1.635895, 1.831943, 2.140674, 2.735423",\ + "0.927469, 1.112486, 1.306941, 1.615054, 2.208637",\ + "0.951911, 1.136927, 1.331383, 1.639496, 2.233079",\ + "1.002784, 1.187801, 1.382256, 1.690369, 2.283952",\ + "1.169221, 1.354238, 1.548693, 1.856806, 2.450387",\ + "1.756105, 1.941121, 2.135577, 2.443689, 3.037270"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.044220, 0.044220, 0.044220, 0.044220, 0.044220",\ + "0.073393, 0.073393, 0.073393, 0.073392, 0.073390",\ + "0.149511, 0.149511, 0.149511, 0.149511, 0.149511",\ + "0.447701, 0.447701, 0.447701, 0.447701, 0.447701",\ + "1.523418, 1.523418, 1.523418, 1.523418, 1.523416",\ + "0.044220, 0.044220, 0.044220, 0.044220, 0.044220",\ + "0.073393, 0.073393, 0.073393, 0.073392, 0.073390",\ + "0.149511, 0.149511, 0.149511, 0.149511, 0.149511",\ + "0.447701, 0.447701, 0.447701, 0.447701, 0.447701",\ + "1.523418, 1.523418, 1.523418, 1.523418, 1.523416",\ + "0.044220, 0.044220, 0.044220, 0.044220, 0.044220",\ + "0.073393, 0.073393, 0.073393, 0.073392, 0.073390",\ + "0.149511, 0.149511, 0.149511, 0.149511, 0.149511",\ + "0.447701, 0.447701, 0.447701, 0.447701, 0.447701",\ + "1.523418, 1.523418, 1.523418, 1.523418, 1.523416",\ + "0.044220, 0.044220, 0.044220, 0.044220, 0.044220",\ + "0.073393, 0.073393, 0.073393, 0.073392, 0.073390",\ + "0.149511, 0.149511, 0.149511, 0.149511, 0.149511",\ + "0.447701, 0.447701, 0.447701, 0.447701, 0.447701",\ + "1.523418, 1.523418, 1.523418, 1.523418, 1.523416",\ + "0.044220, 0.044220, 0.044220, 0.044220, 0.044220",\ + "0.073393, 0.073393, 0.073393, 0.073392, 0.073390",\ + "0.149511, 0.149511, 0.149511, 0.149511, 0.149511",\ + "0.447701, 0.447701, 0.447701, 0.447701, 0.447701",\ + "1.523418, 1.523418, 1.523418, 1.523418, 1.523416"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[8]_redg_2576*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[3]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.556670, 0.735097, 0.915357, 1.201564, 1.752681",\ + "0.586643, 0.765069, 0.945330, 1.231536, 1.782653",\ + "0.658387, 0.836814, 1.017074, 1.303281, 1.854398",\ + "0.914840, 1.093267, 1.273527, 1.559734, 2.110850",\ + "1.827306, 2.005733, 2.185993, 2.472199, 3.023317",\ + "0.641609, 0.820369, 1.001272, 1.287484, 1.839059",\ + "0.671581, 0.850342, 1.031245, 1.317456, 1.869031",\ + "0.743326, 0.922086, 1.102990, 1.389201, 1.940776",\ + "0.999778, 1.178539, 1.359442, 1.645654, 2.197229",\ + "1.912244, 2.091005, 2.271908, 2.558120, 3.109695",\ + "0.717515, 0.895813, 1.076081, 1.362081, 1.913231",\ + "0.747487, 0.925785, 1.106054, 1.392053, 1.943204",\ + "0.819232, 0.997530, 1.177799, 1.463798, 2.014948",\ + "1.075685, 1.253982, 1.434251, 1.720250, 2.271401",\ + "1.988150, 2.166448, 2.346717, 2.632716, 3.183867",\ + "0.771867, 0.950324, 1.130732, 1.416620, 1.967548",\ + "0.801839, 0.980297, 1.160705, 1.446593, 1.997521",\ + "0.873584, 1.052042, 1.232450, 1.518338, 2.069266",\ + "1.130037, 1.308494, 1.488902, 1.774790, 2.325718",\ + "2.042502, 2.220960, 2.401368, 2.687256, 3.238184",\ + "1.053289, 1.235552, 1.414683, 1.700347, 2.250826",\ + "1.083261, 1.265524, 1.444655, 1.730319, 2.280799",\ + "1.155006, 1.337269, 1.516400, 1.802064, 2.352543",\ + "1.411458, 1.593722, 1.772853, 2.058517, 2.608996",\ + "2.323924, 2.506187, 2.685318, 2.970983, 3.521462"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.045710, 0.045710, 0.045710, 0.045710, 0.045710",\ + "0.092269, 0.092269, 0.092269, 0.092269, 0.092269",\ + "0.223657, 0.223657, 0.223657, 0.223657, 0.223657",\ + "0.715794, 0.715794, 0.715794, 0.715794, 0.715794",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\ + "0.045710, 0.045710, 0.045710, 0.045710, 0.045710",\ + "0.092269, 0.092269, 0.092269, 0.092269, 0.092269",\ + "0.223657, 0.223657, 0.223657, 0.223657, 0.223657",\ + "0.715794, 0.715794, 0.715794, 0.715794, 0.715794",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\ + "0.045710, 0.045710, 0.045710, 0.045710, 0.045710",\ + "0.092269, 0.092269, 0.092269, 0.092269, 0.092269",\ + "0.223657, 0.223657, 0.223657, 0.223657, 0.223657",\ + "0.715794, 0.715794, 0.715794, 0.715794, 0.715794",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\ + "0.045710, 0.045710, 0.045710, 0.045710, 0.045710",\ + "0.092269, 0.092269, 0.092269, 0.092269, 0.092269",\ + "0.223657, 0.223657, 0.223657, 0.223657, 0.223657",\ + "0.715794, 0.715794, 0.715794, 0.715794, 0.715794",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\ + "0.045710, 0.045710, 0.045710, 0.045710, 0.045710",\ + "0.092269, 0.092269, 0.092269, 0.092269, 0.092269",\ + "0.223657, 0.223657, 0.223657, 0.223657, 0.223657",\ + "0.715794, 0.715794, 0.715794, 0.715794, 0.715794",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.416720, 0.681890, 0.941092, 1.377274, 2.249640",\ + "0.441162, 0.706331, 0.965533, 1.401715, 2.274081",\ + "0.492035, 0.757205, 1.016407, 1.452589, 2.324954",\ + "0.658472, 0.923642, 1.182844, 1.619026, 2.491391",\ + "1.245356, 1.510525, 1.769727, 2.205910, 3.078275",\ + "0.505386, 0.769965, 1.029733, 1.465503, 2.337044",\ + "0.529827, 0.794406, 1.054174, 1.489944, 2.361485",\ + "0.580701, 0.845280, 1.105047, 1.540818, 2.412359",\ + "0.747138, 1.011717, 1.271485, 1.707255, 2.578796",\ + "1.334021, 1.598600, 1.858368, 2.294138, 3.165680",\ + "0.598193, 0.863088, 1.121458, 1.557667, 2.430086",\ + "0.622634, 0.887529, 1.145899, 1.582108, 2.454527",\ + "0.673507, 0.938403, 1.196773, 1.632982, 2.505401",\ + "0.839945, 1.104840, 1.363210, 1.799419, 2.671838",\ + "1.426828, 1.691723, 1.950093, 2.386303, 3.258722",\ + "0.663915, 0.931622, 1.188478, 1.624518, 2.496598",\ + "0.688356, 0.956063, 1.212919, 1.648959, 2.521039",\ + "0.739230, 1.006937, 1.263793, 1.699832, 2.571912",\ + "0.905667, 1.173374, 1.430230, 1.866270, 2.738349",\ + "1.492550, 1.760257, 2.017113, 2.453153, 3.325233",\ + "1.009705, 1.312121, 1.559108, 1.993649, 2.862731",\ + "1.034146, 1.336562, 1.583549, 2.018090, 2.887172",\ + "1.085019, 1.387435, 1.634423, 2.068964, 2.938045",\ + "1.251456, 1.553873, 1.800860, 2.235401, 3.104483",\ + "1.838340, 2.140756, 2.387743, 2.822284, 3.691366"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.044220, 0.044220, 0.044220, 0.044220, 0.044220",\ + "0.073393, 0.073393, 0.073393, 0.073393, 0.073393",\ + "0.149510, 0.149510, 0.149510, 0.149510, 0.149510",\ + "0.447701, 0.447701, 0.447701, 0.447701, 0.447701",\ + "1.523418, 1.523418, 1.523418, 1.523418, 1.523419",\ + "0.044220, 0.044220, 0.044220, 0.044220, 0.044220",\ + "0.073393, 0.073393, 0.073393, 0.073393, 0.073393",\ + "0.149510, 0.149510, 0.149510, 0.149510, 0.149510",\ + "0.447701, 0.447701, 0.447701, 0.447701, 0.447701",\ + "1.523418, 1.523418, 1.523418, 1.523418, 1.523419",\ + "0.044220, 0.044220, 0.044220, 0.044220, 0.044220",\ + "0.073393, 0.073393, 0.073393, 0.073393, 0.073393",\ + "0.149510, 0.149510, 0.149510, 0.149510, 0.149510",\ + "0.447701, 0.447701, 0.447701, 0.447701, 0.447701",\ + "1.523418, 1.523418, 1.523418, 1.523418, 1.523419",\ + "0.044220, 0.044220, 0.044220, 0.044220, 0.044220",\ + "0.073393, 0.073393, 0.073393, 0.073393, 0.073393",\ + "0.149510, 0.149510, 0.149510, 0.149510, 0.149510",\ + "0.447701, 0.447701, 0.447701, 0.447701, 0.447701",\ + "1.523418, 1.523418, 1.523418, 1.523418, 1.523419",\ + "0.044220, 0.044220, 0.044220, 0.044220, 0.044220",\ + "0.073393, 0.073393, 0.073393, 0.073393, 0.073393",\ + "0.149510, 0.149510, 0.149510, 0.149510, 0.149510",\ + "0.447701, 0.447701, 0.447701, 0.447701, 0.447701",\ + "1.523418, 1.523418, 1.523418, 1.523418, 1.523419"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[8]_redg_2513*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + values ( "0.323944, 0.353916, 0.425661, 0.682114, 1.594576",\ + "0.411334, 0.441307, 0.513052, 0.769505, 1.681967",\ + "0.492253, 0.522226, 0.593971, 0.850424, 1.762885",\ + "0.549994, 0.579967, 0.651712, 0.908165, 1.820624",\ + "0.852699, 0.882672, 0.954417, 1.210871, 2.123326"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + values ( "0.045711, 0.092269, 0.223658, 0.715775, 2.463871",\ + "0.045711, 0.092269, 0.223735, 0.715775, 2.463871",\ + "0.045711, 0.092269, 0.223968, 0.715775, 2.463871",\ + "0.045711, 0.092270, 0.223968, 0.715775, 2.463871",\ + "0.045873, 0.092295, 0.224303, 0.715788, 2.463884"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + values ( "0.296604, 0.321045, 0.371919, 0.538356, 1.125239",\ + "0.383997, 0.408438, 0.459311, 0.625749, 1.212632",\ + "0.464866, 0.489307, 0.540181, 0.706618, 1.293501",\ + "0.522515, 0.546956, 0.597830, 0.764267, 1.351150",\ + "0.825652, 0.850326, 0.901556, 1.068388, 1.654962"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + values ( "0.044220, 0.073393, 0.149516, 0.447701, 1.524168",\ + "0.044220, 0.073393, 0.149516, 0.447701, 1.524168",\ + "0.044220, 0.073393, 0.149516, 0.447701, 1.524042",\ + "0.044220, 0.073393, 0.149516, 0.447701, 1.523806",\ + "0.044219, 0.073327, 0.149516, 0.447696, 1.523418"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[8]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[0]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.507461, 0.687575, 0.875153, 1.177133, 1.760229",\ + "0.536439, 0.716552, 0.904131, 1.206110, 1.789207",\ + "0.607591, 0.787705, 0.975283, 1.277263, 1.860359",\ + "0.863316, 1.043430, 1.231008, 1.532988, 2.116084",\ + "1.774034, 1.954148, 2.141726, 2.443706, 3.026802",\ + "0.592400, 0.772411, 0.960223, 1.262639, 1.846608",\ + "0.621377, 0.801388, 0.989201, 1.291617, 1.875585",\ + "0.692529, 0.872540, 1.060353, 1.362769, 1.946737",\ + "0.948255, 1.128266, 1.316078, 1.618494, 2.202463",\ + "1.858973, 2.038984, 2.226796, 2.529212, 3.113181",\ + "0.668312, 0.847854, 1.035032, 1.337236, 1.920780",\ + "0.697289, 0.876831, 1.064010, 1.366214, 1.949757",\ + "0.768441, 0.947984, 1.135162, 1.437366, 2.020910",\ + "1.024167, 1.203709, 1.390887, 1.693091, 2.276635",\ + "1.934885, 2.114427, 2.301605, 2.603809, 3.187353",\ + "0.722681, 0.902605, 1.089921, 1.391842, 1.975097",\ + "0.751658, 0.931583, 1.118899, 1.420819, 2.004075",\ + "0.822811, 1.002735, 1.190051, 1.491971, 2.075227",\ + "1.078536, 1.258460, 1.445776, 1.747697, 2.330952",\ + "1.989254, 2.169178, 2.356494, 2.658415, 3.241670",\ + "1.004276, 1.188170, 1.374097, 1.675568, 2.258375",\ + "1.033253, 1.217148, 1.403074, 1.704545, 2.287352",\ + "1.104405, 1.288300, 1.474226, 1.775698, 2.358505",\ + "1.360131, 1.544025, 1.729952, 2.031423, 2.614230",\ + "2.270849, 2.454743, 2.640669, 2.942141, 3.524948"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.042748, 0.042748, 0.042748, 0.042748, 0.042748",\ + "0.089888, 0.089888, 0.089888, 0.089888, 0.089888",\ + "0.222179, 0.222179, 0.222179, 0.222179, 0.222179",\ + "0.711766, 0.711766, 0.711766, 0.711766, 0.711766",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\ + "0.042748, 0.042748, 0.042748, 0.042748, 0.042748",\ + "0.089888, 0.089888, 0.089888, 0.089888, 0.089888",\ + "0.222179, 0.222179, 0.222179, 0.222179, 0.222179",\ + "0.711766, 0.711766, 0.711766, 0.711766, 0.711766",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\ + "0.042748, 0.042748, 0.042748, 0.042748, 0.042748",\ + "0.089888, 0.089888, 0.089888, 0.089888, 0.089888",\ + "0.222179, 0.222179, 0.222179, 0.222179, 0.222179",\ + "0.711766, 0.711766, 0.711766, 0.711766, 0.711766",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\ + "0.042748, 0.042748, 0.042748, 0.042748, 0.042748",\ + "0.089888, 0.089888, 0.089888, 0.089888, 0.089888",\ + "0.222179, 0.222179, 0.222179, 0.222179, 0.222179",\ + "0.711766, 0.711766, 0.711766, 0.711766, 0.711766",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\ + "0.042748, 0.042748, 0.042748, 0.042748, 0.042748",\ + "0.089888, 0.089888, 0.089888, 0.089888, 0.089888",\ + "0.222179, 0.222179, 0.222179, 0.222179, 0.222179",\ + "0.711766, 0.711766, 0.711766, 0.711766, 0.711766",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.389483, 0.657094, 0.918495, 1.358271, 2.237432",\ + "0.411493, 0.679104, 0.940496, 1.380242, 2.259341",\ + "0.459519, 0.727130, 0.988522, 1.428268, 2.307366",\ + "0.624827, 0.892438, 1.153830, 1.593576, 2.472674",\ + "1.214436, 1.482046, 1.743447, 2.183224, 3.062385",\ + "0.478187, 0.745169, 1.007135, 1.446501, 2.324838",\ + "0.500198, 0.767179, 1.029137, 1.468471, 2.346746",\ + "0.548223, 0.815205, 1.077163, 1.516497, 2.394772",\ + "0.713532, 0.980513, 1.242471, 1.681805, 2.560080",\ + "1.303140, 1.570121, 1.832088, 2.271453, 3.149790",\ + "0.571129, 0.838489, 1.099180, 1.538746, 2.417880",\ + "0.593140, 0.860499, 1.121182, 1.560717, 2.439788",\ + "0.641166, 0.908525, 1.169207, 1.608743, 2.487813",\ + "0.806474, 1.073833, 1.334516, 1.774051, 2.653121",\ + "1.396082, 1.663441, 1.924133, 2.363699, 3.242832",\ + "0.636973, 0.907053, 1.166236, 1.605758, 2.484801",\ + "0.658983, 0.929063, 1.188238, 1.627728, 2.506709",\ + "0.707009, 0.977089, 1.236264, 1.675754, 2.554735",\ + "0.872317, 1.142398, 1.401572, 1.841062, 2.720043",\ + "1.461926, 1.732006, 1.991189, 2.430710, 3.309754",\ + "0.983494, 1.287889, 1.536907, 1.974983, 2.851137",\ + "1.005505, 1.309899, 1.558908, 1.996953, 2.873044",\ + "1.053531, 1.357925, 1.606934, 2.044979, 2.921070",\ + "1.218839, 1.523233, 1.772242, 2.210288, 3.086378",\ + "1.808447, 2.112841, 2.361860, 2.799936, 3.676089"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.035640, 0.035640, 0.035640, 0.035640, 0.035640",\ + "0.064460, 0.064460, 0.064460, 0.064460, 0.064460",\ + "0.142275, 0.142275, 0.142275, 0.142275, 0.142275",\ + "0.443177, 0.443177, 0.443177, 0.443177, 0.443178",\ + "1.518758, 1.518758, 1.518758, 1.518758, 1.518758",\ + "0.035640, 0.035640, 0.035640, 0.035640, 0.035640",\ + "0.064460, 0.064460, 0.064460, 0.064460, 0.064460",\ + "0.142275, 0.142275, 0.142275, 0.142275, 0.142275",\ + "0.443177, 0.443177, 0.443177, 0.443177, 0.443178",\ + "1.518758, 1.518758, 1.518758, 1.518758, 1.518758",\ + "0.035640, 0.035640, 0.035640, 0.035640, 0.035640",\ + "0.064460, 0.064460, 0.064460, 0.064460, 0.064460",\ + "0.142275, 0.142275, 0.142275, 0.142275, 0.142275",\ + "0.443177, 0.443177, 0.443177, 0.443177, 0.443178",\ + "1.518758, 1.518758, 1.518758, 1.518758, 1.518758",\ + "0.035640, 0.035640, 0.035640, 0.035640, 0.035640",\ + "0.064460, 0.064460, 0.064460, 0.064460, 0.064460",\ + "0.142275, 0.142275, 0.142275, 0.142275, 0.142275",\ + "0.443177, 0.443177, 0.443177, 0.443177, 0.443178",\ + "1.518758, 1.518758, 1.518758, 1.518758, 1.518758",\ + "0.035640, 0.035640, 0.035640, 0.035640, 0.035640",\ + "0.064460, 0.064460, 0.064460, 0.064460, 0.064460",\ + "0.142275, 0.142275, 0.142275, 0.142275, 0.142275",\ + "0.443177, 0.443177, 0.443177, 0.443177, 0.443178",\ + "1.518758, 1.518758, 1.518758, 1.518758, 1.518758"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[8]_redg_min_2454*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[1]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.415570, 0.679101, 0.955220, 1.423352, 2.358356",\ + "0.444547, 0.708078, 0.984198, 1.452330, 2.387333",\ + "0.515699, 0.779231, 1.055350, 1.523482, 2.458486",\ + "0.771425, 1.034956, 1.311076, 1.779207, 2.714211",\ + "1.682143, 1.945674, 2.221793, 2.689925, 3.624929",\ + "0.503764, 0.766641, 1.042787, 1.510067, 2.444290",\ + "0.532741, 0.795619, 1.071764, 1.539045, 2.473267",\ + "0.603894, 0.866771, 1.142917, 1.610197, 2.544420",\ + "0.859619, 1.122496, 1.398642, 1.865922, 2.800145",\ + "1.770337, 2.033214, 2.309360, 2.776640, 3.710862",\ + "0.592080, 0.855621, 1.130752, 1.597708, 2.531245",\ + "0.621057, 0.884598, 1.159729, 1.626685, 2.560222",\ + "0.692210, 0.955751, 1.230882, 1.697837, 2.631375",\ + "0.947935, 1.211476, 1.486607, 1.953563, 2.887100",\ + "1.858653, 2.122194, 2.397325, 2.864281, 3.797817",\ + "0.654576, 0.921255, 1.194892, 1.661796, 2.594754",\ + "0.683553, 0.950232, 1.223869, 1.690774, 2.623731",\ + "0.754706, 1.021384, 1.295022, 1.761926, 2.694884",\ + "1.010431, 1.277110, 1.550747, 2.017652, 2.950609",\ + "1.921149, 2.187827, 2.461465, 2.928370, 3.861326",\ + "0.983702, 1.285569, 1.546756, 2.011240, 2.940210",\ + "1.012679, 1.314547, 1.575733, 2.040218, 2.969187",\ + "1.083832, 1.385699, 1.646886, 2.111370, 3.040340",\ + "1.339557, 1.641424, 1.902611, 2.367095, 3.296065",\ + "2.250275, 2.552142, 2.813329, 3.277813, 4.206782"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.042748, 0.042748, 0.042748, 0.042748, 0.042749",\ + "0.089888, 0.089888, 0.089888, 0.089889, 0.089889",\ + "0.222179, 0.222179, 0.222179, 0.222179, 0.222180",\ + "0.711766, 0.711766, 0.711766, 0.711765, 0.711764",\ + "2.448223, 2.448223, 2.448224, 2.448226, 2.448230",\ + "0.042748, 0.042748, 0.042748, 0.042748, 0.042749",\ + "0.089888, 0.089888, 0.089888, 0.089889, 0.089889",\ + "0.222179, 0.222179, 0.222179, 0.222179, 0.222180",\ + "0.711766, 0.711766, 0.711766, 0.711765, 0.711764",\ + "2.448223, 2.448223, 2.448224, 2.448226, 2.448230",\ + "0.042748, 0.042748, 0.042748, 0.042748, 0.042749",\ + "0.089888, 0.089888, 0.089888, 0.089889, 0.089889",\ + "0.222179, 0.222179, 0.222179, 0.222179, 0.222180",\ + "0.711766, 0.711766, 0.711766, 0.711765, 0.711764",\ + "2.448223, 2.448223, 2.448224, 2.448226, 2.448230",\ + "0.042748, 0.042748, 0.042748, 0.042748, 0.042749",\ + "0.089888, 0.089888, 0.089888, 0.089889, 0.089889",\ + "0.222179, 0.222179, 0.222179, 0.222179, 0.222180",\ + "0.711766, 0.711766, 0.711766, 0.711765, 0.711764",\ + "2.448223, 2.448223, 2.448224, 2.448226, 2.448230",\ + "0.042748, 0.042748, 0.042748, 0.042748, 0.042749",\ + "0.089888, 0.089888, 0.089888, 0.089889, 0.089889",\ + "0.222179, 0.222179, 0.222179, 0.222179, 0.222180",\ + "0.711766, 0.711766, 0.711766, 0.711765, 0.711764",\ + "2.448223, 2.448223, 2.448224, 2.448226, 2.448230"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.372438, 0.554496, 0.750729, 1.059908, 1.654385",\ + "0.394447, 0.576504, 0.772637, 1.081769, 1.676222",\ + "0.442472, 0.624530, 0.820663, 1.129795, 1.724248",\ + "0.607781, 0.789838, 0.985971, 1.295103, 1.889559",\ + "1.197391, 1.379448, 1.575682, 1.884862, 2.479345",\ + "0.459853, 0.641814, 0.838010, 1.147213, 1.741738",\ + "0.481861, 0.663823, 0.859918, 1.169074, 1.763576",\ + "0.529887, 0.711849, 0.907944, 1.217100, 1.811602",\ + "0.695195, 0.877157, 1.073252, 1.382408, 1.976912",\ + "1.284805, 1.466767, 1.662963, 1.972167, 2.566699",\ + "0.540729, 0.722151, 0.918037, 1.227241, 1.821770",\ + "0.562738, 0.744159, 0.939945, 1.249102, 1.843607",\ + "0.610763, 0.792185, 0.987971, 1.297128, 1.891634",\ + "0.776072, 0.957493, 1.153279, 1.462437, 2.056944",\ + "1.365682, 1.547103, 1.742990, 2.052196, 2.646730",\ + "0.598376, 0.779988, 0.975773, 1.284712, 1.878866",\ + "0.620384, 0.801996, 0.997680, 1.306573, 1.900703",\ + "0.668410, 0.850022, 1.045706, 1.354599, 1.948729",\ + "0.833718, 1.015330, 1.211014, 1.519907, 2.114039",\ + "1.423328, 1.604940, 1.800725, 2.109667, 2.703826",\ + "0.900583, 1.085365, 1.279436, 1.587919, 2.181184",\ + "0.922592, 1.107373, 1.301344, 1.609780, 2.203021",\ + "0.970618, 1.155399, 1.349370, 1.657806, 2.251047",\ + "1.135926, 1.320707, 1.514678, 1.823114, 2.416358",\ + "1.725536, 1.910317, 2.104389, 2.412873, 3.006144"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.035640, 0.035640, 0.035640, 0.035640, 0.035640",\ + "0.064460, 0.064460, 0.064460, 0.064460, 0.064461",\ + "0.142275, 0.142275, 0.142275, 0.142276, 0.142277",\ + "0.443177, 0.443177, 0.443178, 0.443183, 0.443195",\ + "1.518758, 1.518758, 1.518758, 1.518759, 1.518761",\ + "0.035640, 0.035640, 0.035640, 0.035640, 0.035640",\ + "0.064460, 0.064460, 0.064460, 0.064460, 0.064461",\ + "0.142275, 0.142275, 0.142275, 0.142276, 0.142277",\ + "0.443177, 0.443177, 0.443178, 0.443183, 0.443195",\ + "1.518758, 1.518758, 1.518758, 1.518759, 1.518761",\ + "0.035640, 0.035640, 0.035640, 0.035640, 0.035640",\ + "0.064460, 0.064460, 0.064460, 0.064460, 0.064461",\ + "0.142275, 0.142275, 0.142275, 0.142276, 0.142277",\ + "0.443177, 0.443177, 0.443178, 0.443183, 0.443195",\ + "1.518758, 1.518758, 1.518758, 1.518759, 1.518761",\ + "0.035640, 0.035640, 0.035640, 0.035640, 0.035640",\ + "0.064460, 0.064460, 0.064460, 0.064460, 0.064461",\ + "0.142275, 0.142275, 0.142275, 0.142276, 0.142277",\ + "0.443177, 0.443177, 0.443178, 0.443183, 0.443196",\ + "1.518758, 1.518758, 1.518758, 1.518759, 1.518761",\ + "0.035640, 0.035640, 0.035640, 0.035640, 0.035640",\ + "0.064460, 0.064460, 0.064460, 0.064460, 0.064461",\ + "0.142275, 0.142275, 0.142275, 0.142276, 0.142277",\ + "0.443177, 0.443177, 0.443178, 0.443183, 0.443196",\ + "1.518758, 1.518758, 1.518758, 1.518759, 1.518761"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[8]_redg_min_2376*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[2]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.411592, 0.671151, 0.942786, 1.398947, 2.310115",\ + "0.440569, 0.700128, 0.971763, 1.427925, 2.339092",\ + "0.511721, 0.771281, 1.042916, 1.499077, 2.410245",\ + "0.767447, 1.027006, 1.298641, 1.754802, 2.665970",\ + "1.678164, 1.937724, 2.209359, 2.665520, 3.576688",\ + "0.499696, 0.758684, 1.030315, 1.485663, 2.396049",\ + "0.528674, 0.787661, 1.059292, 1.514640, 2.425026",\ + "0.599826, 0.858813, 1.130445, 1.585792, 2.496178",\ + "0.855551, 1.114539, 1.386170, 1.841518, 2.751904",\ + "1.766269, 2.025257, 2.296888, 2.752235, 3.662621",\ + "0.587726, 0.847648, 1.118279, 1.573302, 2.483004",\ + "0.616704, 0.876625, 1.147256, 1.602279, 2.511981",\ + "0.687856, 0.947778, 1.218409, 1.673431, 2.583133",\ + "0.943582, 1.203503, 1.474134, 1.929157, 2.838859",\ + "1.854300, 2.114221, 2.384852, 2.839874, 3.749576",\ + "0.649948, 0.913259, 1.182417, 1.637376, 2.546513",\ + "0.678925, 0.942237, 1.211394, 1.666353, 2.575490",\ + "0.750077, 1.013389, 1.282547, 1.737506, 2.646642",\ + "1.005803, 1.269114, 1.538272, 1.993231, 2.902368",\ + "1.916521, 2.179832, 2.448990, 2.903949, 3.813085",\ + "0.977335, 1.277308, 1.534159, 1.986762, 2.891969",\ + "1.006312, 1.306285, 1.563137, 2.015740, 2.920946",\ + "1.077465, 1.377437, 1.634289, 2.086892, 2.992099",\ + "1.333190, 1.633163, 1.890014, 2.342618, 3.247824",\ + "2.243908, 2.543881, 2.800732, 3.253335, 4.158542"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.042748, 0.042748, 0.042748, 0.042749, 0.042750",\ + "0.089888, 0.089888, 0.089889, 0.089889, 0.089889",\ + "0.222179, 0.222179, 0.222179, 0.222180, 0.222180",\ + "0.711766, 0.711766, 0.711765, 0.711765, 0.711763",\ + "2.448223, 2.448223, 2.448225, 2.448228, 2.448234",\ + "0.042748, 0.042748, 0.042748, 0.042749, 0.042750",\ + "0.089888, 0.089888, 0.089889, 0.089889, 0.089889",\ + "0.222179, 0.222179, 0.222179, 0.222180, 0.222180",\ + "0.711766, 0.711766, 0.711765, 0.711765, 0.711763",\ + "2.448223, 2.448223, 2.448225, 2.448228, 2.448234",\ + "0.042748, 0.042748, 0.042748, 0.042749, 0.042750",\ + "0.089888, 0.089888, 0.089889, 0.089889, 0.089889",\ + "0.222179, 0.222179, 0.222179, 0.222180, 0.222180",\ + "0.711766, 0.711766, 0.711765, 0.711765, 0.711763",\ + "2.448223, 2.448223, 2.448225, 2.448228, 2.448234",\ + "0.042748, 0.042748, 0.042748, 0.042749, 0.042750",\ + "0.089888, 0.089888, 0.089889, 0.089889, 0.089889",\ + "0.222179, 0.222179, 0.222179, 0.222180, 0.222180",\ + "0.711766, 0.711766, 0.711765, 0.711765, 0.711763",\ + "2.448223, 2.448223, 2.448225, 2.448228, 2.448234",\ + "0.042748, 0.042748, 0.042748, 0.042749, 0.042750",\ + "0.089888, 0.089888, 0.089889, 0.089889, 0.089889",\ + "0.222179, 0.222179, 0.222179, 0.222180, 0.222180",\ + "0.711766, 0.711766, 0.711765, 0.711765, 0.711763",\ + "2.448223, 2.448223, 2.448225, 2.448228, 2.448234"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.370774, 0.552942, 0.749040, 1.058378, 1.653339",\ + "0.392785, 0.574952, 0.770949, 1.080242, 1.675184",\ + "0.440811, 0.622978, 0.818975, 1.128268, 1.723211",\ + "0.606119, 0.788286, 0.984283, 1.293577, 1.888521",\ + "1.195727, 1.377894, 1.573993, 1.883330, 2.478289",\ + "0.458194, 0.640260, 0.836321, 1.145683, 1.740692",\ + "0.480205, 0.662271, 0.858230, 1.167547, 1.762538",\ + "0.528231, 0.710297, 0.906256, 1.215573, 1.810564",\ + "0.693539, 0.875605, 1.071564, 1.380882, 1.975875",\ + "1.283147, 1.465213, 1.661273, 1.970635, 2.565643",\ + "0.539062, 0.720597, 0.916348, 1.225712, 1.820724",\ + "0.561073, 0.742608, 0.938257, 1.247576, 1.842569",\ + "0.609098, 0.790634, 0.986283, 1.295602, 1.890596",\ + "0.774407, 0.955942, 1.151591, 1.460911, 2.055906",\ + "1.364015, 1.545550, 1.741300, 2.050663, 2.645674",\ + "0.596701, 0.778434, 0.974083, 1.283183, 1.877821",\ + "0.618712, 0.800445, 0.995992, 1.305047, 1.899666",\ + "0.666737, 0.848471, 1.044018, 1.353073, 1.947692",\ + "0.832046, 1.013779, 1.209326, 1.518381, 2.113003",\ + "1.421654, 1.603387, 1.799036, 2.108135, 2.702771",\ + "0.898796, 1.083812, 1.277747, 1.586390, 2.180140",\ + "0.920807, 1.105823, 1.299656, 1.608254, 2.201985",\ + "0.968832, 1.153849, 1.347681, 1.656280, 2.250011",\ + "1.134141, 1.319157, 1.512989, 1.821589, 2.415322",\ + "1.723749, 1.908765, 2.102699, 2.411342, 3.005090"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.035640, 0.035640, 0.035640, 0.035640, 0.035640",\ + "0.064460, 0.064460, 0.064460, 0.064460, 0.064462",\ + "0.142275, 0.142275, 0.142275, 0.142276, 0.142277",\ + "0.443177, 0.443177, 0.443178, 0.443184, 0.443197",\ + "1.518758, 1.518758, 1.518758, 1.518759, 1.518761",\ + "0.035640, 0.035640, 0.035640, 0.035640, 0.035640",\ + "0.064460, 0.064460, 0.064460, 0.064460, 0.064462",\ + "0.142275, 0.142275, 0.142275, 0.142276, 0.142277",\ + "0.443177, 0.443177, 0.443178, 0.443184, 0.443197",\ + "1.518758, 1.518758, 1.518758, 1.518759, 1.518761",\ + "0.035640, 0.035640, 0.035640, 0.035640, 0.035640",\ + "0.064460, 0.064460, 0.064460, 0.064460, 0.064462",\ + "0.142275, 0.142275, 0.142275, 0.142276, 0.142277",\ + "0.443177, 0.443177, 0.443178, 0.443184, 0.443197",\ + "1.518758, 1.518758, 1.518758, 1.518759, 1.518761",\ + "0.035640, 0.035640, 0.035640, 0.035640, 0.035640",\ + "0.064460, 0.064460, 0.064460, 0.064460, 0.064462",\ + "0.142275, 0.142275, 0.142275, 0.142276, 0.142277",\ + "0.443177, 0.443177, 0.443178, 0.443184, 0.443197",\ + "1.518758, 1.518758, 1.518758, 1.518759, 1.518761",\ + "0.035640, 0.035640, 0.035640, 0.035640, 0.035640",\ + "0.064460, 0.064460, 0.064460, 0.064460, 0.064462",\ + "0.142275, 0.142275, 0.142275, 0.142276, 0.142277",\ + "0.443177, 0.443177, 0.443178, 0.443184, 0.443197",\ + "1.518758, 1.518758, 1.518758, 1.518759, 1.518761"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[8]_redg_min_2318*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[3]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.503875, 0.682214, 0.862561, 1.148748, 1.699501",\ + "0.532852, 0.711192, 0.891538, 1.177725, 1.728478",\ + "0.604005, 0.782344, 0.962691, 1.248877, 1.799630",\ + "0.859730, 1.038069, 1.218416, 1.504603, 2.055356",\ + "1.770448, 1.948787, 2.129134, 2.415321, 2.966074",\ + "0.588813, 0.767050, 0.947631, 1.234254, 1.785879",\ + "0.617791, 0.796027, 0.976608, 1.263231, 1.814857",\ + "0.688943, 0.867180, 1.047761, 1.334384, 1.886009",\ + "0.944668, 1.122905, 1.303486, 1.590109, 2.141734",\ + "1.855386, 2.033623, 2.214204, 2.500827, 3.052452",\ + "0.664719, 0.842493, 1.022440, 1.308851, 1.860052",\ + "0.693697, 0.871471, 1.051417, 1.337828, 1.889029",\ + "0.764849, 0.942623, 1.122570, 1.408980, 1.960181",\ + "1.020574, 1.198349, 1.378295, 1.664706, 2.215907",\ + "1.931292, 2.109066, 2.289013, 2.575424, 3.126625",\ + "0.719071, 0.897239, 1.077305, 1.363444, 1.914369",\ + "0.748049, 0.926216, 1.106283, 1.392421, 1.943346",\ + "0.819201, 0.997369, 1.177435, 1.463574, 2.014498",\ + "1.074926, 1.253094, 1.433160, 1.719299, 2.270224",\ + "1.985644, 2.163812, 2.343878, 2.630017, 3.180942",\ + "1.000493, 1.182756, 1.361458, 1.647171, 2.197646",\ + "1.029471, 1.211734, 1.390436, 1.676148, 2.226624",\ + "1.100623, 1.282886, 1.461588, 1.747300, 2.297776",\ + "1.356348, 1.538611, 1.717313, 2.003026, 2.553502",\ + "2.267066, 2.449329, 2.628031, 2.913743, 3.464219"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.042748, 0.042748, 0.042748, 0.042748, 0.042748",\ + "0.089888, 0.089888, 0.089888, 0.089888, 0.089888",\ + "0.222179, 0.222179, 0.222179, 0.222179, 0.222179",\ + "0.711766, 0.711766, 0.711766, 0.711766, 0.711766",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\ + "0.042748, 0.042748, 0.042748, 0.042748, 0.042748",\ + "0.089888, 0.089888, 0.089888, 0.089888, 0.089888",\ + "0.222179, 0.222179, 0.222179, 0.222179, 0.222179",\ + "0.711766, 0.711766, 0.711766, 0.711766, 0.711766",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\ + "0.042748, 0.042748, 0.042748, 0.042748, 0.042748",\ + "0.089888, 0.089888, 0.089888, 0.089888, 0.089888",\ + "0.222179, 0.222179, 0.222179, 0.222179, 0.222179",\ + "0.711766, 0.711766, 0.711766, 0.711766, 0.711766",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\ + "0.042748, 0.042748, 0.042748, 0.042748, 0.042748",\ + "0.089888, 0.089888, 0.089888, 0.089888, 0.089888",\ + "0.222179, 0.222179, 0.222179, 0.222179, 0.222179",\ + "0.711766, 0.711766, 0.711766, 0.711766, 0.711766",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\ + "0.042748, 0.042748, 0.042748, 0.042748, 0.042748",\ + "0.089888, 0.089888, 0.089888, 0.089888, 0.089888",\ + "0.222179, 0.222179, 0.222179, 0.222179, 0.222179",\ + "0.711766, 0.711766, 0.711766, 0.711766, 0.711766",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.388047, 0.653046, 0.912076, 1.348340, 2.220486",\ + "0.410058, 0.675057, 0.934076, 1.370306, 2.242383",\ + "0.458083, 0.723083, 0.982102, 1.418332, 2.290410",\ + "0.623392, 0.888391, 1.147410, 1.583640, 2.455718",\ + "1.213000, 1.477999, 1.737028, 2.173293, 3.045439",\ + "0.476712, 0.741121, 1.000716, 1.436569, 2.307892",\ + "0.498723, 0.763132, 1.022717, 1.458535, 2.329789",\ + "0.546749, 0.811157, 1.070743, 1.506561, 2.377815",\ + "0.712057, 0.976466, 1.236051, 1.671869, 2.543123",\ + "1.301665, 1.566074, 1.825669, 2.261521, 3.132844",\ + "0.569519, 0.834415, 1.092752, 1.528812, 2.400934",\ + "0.591530, 0.856425, 1.114753, 1.550778, 2.422831",\ + "0.639556, 0.904451, 1.162778, 1.598804, 2.470856",\ + "0.804864, 1.069759, 1.328087, 1.764112, 2.636164",\ + "1.394472, 1.659367, 1.917704, 2.353765, 3.225886",\ + "0.635242, 0.902949, 1.159807, 1.595819, 2.467843",\ + "0.657252, 0.924959, 1.181808, 1.617785, 2.489740",\ + "0.705278, 0.972985, 1.229833, 1.665811, 2.537766",\ + "0.870586, 1.138293, 1.395142, 1.831119, 2.703074",\ + "1.460194, 1.727901, 1.984760, 2.420771, 3.292796",\ + "0.981031, 1.283447, 1.530445, 1.965020, 2.834170",\ + "1.003042, 1.305458, 1.552445, 1.986986, 2.856067",\ + "1.051068, 1.353484, 1.600471, 2.035012, 2.904093",\ + "1.216376, 1.518792, 1.765779, 2.200320, 3.069401",\ + "1.805984, 2.108400, 2.355398, 2.789973, 3.659123"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.035640, 0.035640, 0.035640, 0.035640, 0.035640",\ + "0.064460, 0.064460, 0.064460, 0.064460, 0.064460",\ + "0.142275, 0.142275, 0.142275, 0.142275, 0.142275",\ + "0.443177, 0.443177, 0.443177, 0.443177, 0.443178",\ + "1.518758, 1.518758, 1.518758, 1.518758, 1.518758",\ + "0.035640, 0.035640, 0.035640, 0.035640, 0.035640",\ + "0.064460, 0.064460, 0.064460, 0.064460, 0.064460",\ + "0.142275, 0.142275, 0.142275, 0.142275, 0.142275",\ + "0.443177, 0.443177, 0.443177, 0.443177, 0.443178",\ + "1.518758, 1.518758, 1.518758, 1.518758, 1.518758",\ + "0.035640, 0.035640, 0.035640, 0.035640, 0.035640",\ + "0.064460, 0.064460, 0.064460, 0.064460, 0.064460",\ + "0.142275, 0.142275, 0.142275, 0.142275, 0.142275",\ + "0.443177, 0.443177, 0.443177, 0.443177, 0.443178",\ + "1.518758, 1.518758, 1.518758, 1.518758, 1.518758",\ + "0.035640, 0.035640, 0.035640, 0.035640, 0.035640",\ + "0.064460, 0.064460, 0.064460, 0.064460, 0.064460",\ + "0.142275, 0.142275, 0.142275, 0.142275, 0.142275",\ + "0.443177, 0.443177, 0.443177, 0.443177, 0.443178",\ + "1.518758, 1.518758, 1.518758, 1.518758, 1.518758",\ + "0.035640, 0.035640, 0.035640, 0.035640, 0.035640",\ + "0.064460, 0.064460, 0.064460, 0.064460, 0.064460",\ + "0.142275, 0.142275, 0.142275, 0.142275, 0.142275",\ + "0.443177, 0.443177, 0.443177, 0.443177, 0.443178",\ + "1.518758, 1.518758, 1.518758, 1.518758, 1.518758"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[8]_redg_min_2260*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + values ( "0.141425, 0.170720, 0.242339, 0.498612, 1.411098",\ + "0.229610, 0.258905, 0.330536, 0.586854, 1.499024",\ + "0.317934, 0.347229, 0.418864, 0.675374, 1.587106",\ + "0.380526, 0.409818, 0.481403, 0.738206, 1.650402",\ + "0.710407, 0.739695, 0.811101, 1.068343, 1.982165"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + values ( "0.042748, 0.089888, 0.222179, 0.711766, 2.448223",\ + "0.042748, 0.089888, 0.222179, 0.711766, 2.448223",\ + "0.042748, 0.089888, 0.222179, 0.711766, 2.448223",\ + "0.042748, 0.089888, 0.222179, 0.711766, 2.448223",\ + "0.042748, 0.089888, 0.222179, 0.711766, 2.448223"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + values ( "0.179776, 0.202485, 0.251521, 0.417224, 1.003880",\ + "0.267179, 0.289888, 0.338925, 0.504627, 1.091283",\ + "0.348077, 0.370784, 0.419825, 0.585531, 1.172197",\ + "0.405741, 0.428442, 0.477491, 0.643206, 1.229887",\ + "0.708098, 0.730789, 0.779867, 0.945650, 1.532504"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + values ( "0.035639, 0.064458, 0.142274, 0.442345, 1.516474",\ + "0.035639, 0.064458, 0.142274, 0.442345, 1.516474",\ + "0.035639, 0.064458, 0.142274, 0.442391, 1.516474",\ + "0.035639, 0.064458, 0.142274, 0.442476, 1.516474",\ + "0.035639, 0.064458, 0.142274, 0.443177, 1.516474"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[8]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_falling ; + clock_gating_flag : true ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.454726, 0.454726, 0.454726, 0.454726, 0.454726",\ + "0.473076, 0.473076, 0.473076, 0.473076, 0.473076",\ + "0.545703, 0.545703, 0.545703, 0.545703, 0.545703",\ + "0.640171, 0.640171, 0.640171, 0.640171, 0.640171",\ + "1.087704, 1.087704, 1.087704, 1.087704, 1.087704"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.201983, 0.201983, 0.201983, 0.201983, 0.201983",\ + "0.219410, 0.219410, 0.219410, 0.219410, 0.219410",\ + "0.296741, 0.296741, 0.296741, 0.296741, 0.296741",\ + "0.405665, 0.405665, 0.405665, 0.405665, 0.405665",\ + "0.925258, 0.925258, 0.925258, 0.925258, 0.925258"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[8]_cgsf*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + clock_gating_flag : true ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.450859, -0.450859, -0.450859, -0.450859, -0.450859",\ + "-0.467474, -0.467474, -0.467474, -0.467474, -0.467474",\ + "-0.541835, -0.541835, -0.541835, -0.541835, -0.541835",\ + "-0.636302, -0.636302, -0.636302, -0.636302, -0.636302",\ + "-1.083807, -1.083807, -1.083807, -1.083807, -1.083807"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.194280, -0.194280, -0.194280, -0.194280, -0.194280",\ + "-0.207626, -0.207626, -0.207626, -0.207626, -0.207626",\ + "-0.289038, -0.289038, -0.289038, -0.289038, -0.289038",\ + "-0.398036, -0.398036, -0.398036, -0.398036, -0.398036",\ + "-0.918416, -0.918416, -0.918416, -0.918416, -0.918416"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[8]_cghr*/ + + timing () { + related_pin : "padmux2ast_i[0]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + values ( "0.088658, 0.118400, 0.189731, 0.445655, 1.359203",\ + "0.176289, 0.206081, 0.277284, 0.533409, 1.444562",\ + "0.273999, 0.305373, 0.377262, 0.633109, 1.547694",\ + "0.451720, 0.486942, 0.560777, 0.816366, 1.732299",\ + "0.754684, 0.801348, 0.884176, 1.139736, 2.048527"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + values ( "0.044533, 0.091199, 0.223344, 0.717968, 2.481454",\ + "0.045427, 0.091448, 0.223344, 0.719590, 2.481454",\ + "0.052404, 0.096040, 0.223344, 0.719590, 2.481454",\ + "0.069791, 0.108505, 0.227261, 0.719590, 2.481454",\ + "0.113693, 0.145215, 0.245785, 0.719590, 2.481454"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + values ( "0.127074, 0.151791, 0.203016, 0.369861, 0.957397",\ + "0.206135, 0.230814, 0.281980, 0.448797, 1.035129",\ + "0.309463, 0.335921, 0.388109, 0.554820, 1.143022",\ + "0.486985, 0.519573, 0.577173, 0.745365, 1.332651",\ + "0.774720, 0.823340, 0.896308, 1.069995, 1.655274"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + values ( "0.044476, 0.073631, 0.149535, 0.448052, 1.525218",\ + "0.044476, 0.073631, 0.149535, 0.448052, 1.525218",\ + "0.053117, 0.079360, 0.152226, 0.448052, 1.525218",\ + "0.080664, 0.102519, 0.166108, 0.450694, 1.525218",\ + "0.138236, 0.160233, 0.212368, 0.461268, 1.526869"); + } + + } /* end of arc padmux2ast_i[0]_obs_ctrl_o[8]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[0]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + values ( "0.084296, 0.113120, 0.184192, 0.440347, 1.352120",\ + "0.171472, 0.200589, 0.271545, 0.528022, 1.439207",\ + "0.267978, 0.297935, 0.369614, 0.625313, 1.536303",\ + "0.442024, 0.475873, 0.548072, 0.804727, 1.718362",\ + "0.738029, 0.782075, 0.862420, 1.115871, 2.025527"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + values ( "0.041900, 0.089823, 0.221979, 0.709338, 2.440521",\ + "0.043039, 0.090167, 0.221979, 0.709338, 2.440521",\ + "0.049089, 0.094012, 0.222641, 0.712232, 2.449750",\ + "0.065208, 0.105222, 0.226678, 0.712232, 2.460771",\ + "0.105185, 0.140977, 0.242589, 0.716067, 2.462313"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + values ( "0.092809, 0.114931, 0.163305, 0.328814, 0.916983",\ + "0.177889, 0.200026, 0.248421, 0.413754, 1.001155",\ + "0.277335, 0.302085, 0.352052, 0.517221, 1.105053",\ + "0.446489, 0.478335, 0.533931, 0.699176, 1.285565",\ + "0.721488, 0.769874, 0.842559, 1.014698, 1.597625"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + values ( "0.036394, 0.065440, 0.142870, 0.442805, 1.519686",\ + "0.037274, 0.065647, 0.143061, 0.444080, 1.520298",\ + "0.048413, 0.073856, 0.146810, 0.444683, 1.520298",\ + "0.075564, 0.097153, 0.160320, 0.447782, 1.520312",\ + "0.132225, 0.154160, 0.206470, 0.457474, 1.523023"); + } + + } /* end of arc padmux2ast_i[0]_obs_ctrl_o[8]_una_min*/ + +} /* end of pin obs_ctrl_o[8] */ + +pin("obs_ctrl_o[7]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.094370 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001120 ; + + /* Other user defined attributes. */ + original_pin : obs_ctrl_o[7]; + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[0]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.560132, 0.740335, 0.927825, 1.229818, 1.813330",\ + "0.598058, 0.778261, 0.965751, 1.267744, 1.851256",\ + "0.679713, 0.859917, 1.047406, 1.349399, 1.932911",\ + "0.950162, 1.130366, 1.317855, 1.619848, 2.203360",\ + "1.836798, 2.017001, 2.204491, 2.506483, 3.089995",\ + "0.645071, 0.825618, 1.013834, 1.315830, 1.899708",\ + "0.682997, 0.863544, 1.051760, 1.353756, 1.937634",\ + "0.764652, 0.945200, 1.133415, 1.435411, 2.019289",\ + "1.035101, 1.215649, 1.403864, 1.705860, 2.289738",\ + "1.921736, 2.102284, 2.290499, 2.592495, 3.176373",\ + "0.720983, 0.901062, 1.088643, 1.390427, 1.973880",\ + "0.758909, 0.938988, 1.126569, 1.428353, 2.011806",\ + "0.840564, 1.020643, 1.208224, 1.510008, 2.093462",\ + "1.111013, 1.291092, 1.478673, 1.780457, 2.363911",\ + "1.997648, 2.177727, 2.365308, 2.667092, 3.250545",\ + "0.775352, 0.955573, 1.143294, 1.444967, 2.028198",\ + "0.813278, 0.993499, 1.181220, 1.482893, 2.066123",\ + "0.894933, 1.075155, 1.262875, 1.564548, 2.147779",\ + "1.165382, 1.345604, 1.533324, 1.834997, 2.418228",\ + "2.052018, 2.232239, 2.419959, 2.721632, 3.304862",\ + "1.056947, 1.240841, 1.427244, 1.728693, 2.311475",\ + "1.094873, 1.278767, 1.465170, 1.766619, 2.349401",\ + "1.176528, 1.360423, 1.546826, 1.848274, 2.431056",\ + "1.446977, 1.630872, 1.817275, 2.118723, 2.701505",\ + "2.333612, 2.517507, 2.703910, 3.005358, 3.588140"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.060311, 0.060311, 0.060311, 0.060311, 0.060311",\ + "0.120043, 0.120043, 0.120043, 0.120043, 0.120043",\ + "0.268820, 0.268820, 0.268820, 0.268820, 0.268820",\ + "0.790040, 0.790040, 0.790040, 0.790040, 0.790040",\ + "2.468303, 2.468303, 2.468303, 2.468303, 2.468303",\ + "0.060311, 0.060311, 0.060311, 0.060311, 0.060311",\ + "0.120043, 0.120043, 0.120043, 0.120043, 0.120043",\ + "0.268820, 0.268820, 0.268820, 0.268820, 0.268820",\ + "0.790040, 0.790040, 0.790040, 0.790040, 0.790040",\ + "2.468303, 2.468303, 2.468303, 2.468303, 2.468303",\ + "0.060311, 0.060311, 0.060311, 0.060311, 0.060311",\ + "0.120043, 0.120043, 0.120043, 0.120043, 0.120043",\ + "0.268820, 0.268820, 0.268820, 0.268820, 0.268820",\ + "0.790040, 0.790040, 0.790040, 0.790040, 0.790040",\ + "2.468303, 2.468303, 2.468303, 2.468303, 2.468303",\ + "0.060311, 0.060311, 0.060311, 0.060311, 0.060311",\ + "0.120043, 0.120043, 0.120043, 0.120043, 0.120043",\ + "0.268820, 0.268820, 0.268820, 0.268820, 0.268820",\ + "0.790040, 0.790040, 0.790040, 0.790040, 0.790040",\ + "2.468303, 2.468303, 2.468303, 2.468303, 2.468303",\ + "0.060311, 0.060311, 0.060311, 0.060311, 0.060311",\ + "0.120043, 0.120043, 0.120043, 0.120043, 0.120043",\ + "0.268820, 0.268820, 0.268820, 0.268820, 0.268820",\ + "0.790040, 0.790040, 0.790040, 0.790040, 0.790040",\ + "2.468303, 2.468303, 2.468303, 2.468303, 2.468303"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.442149, 0.709934, 0.971514, 1.411211, 2.290606",\ + "0.473003, 0.740789, 1.002369, 1.442066, 2.321460",\ + "0.534512, 0.802297, 1.063877, 1.503574, 2.382968",\ + "0.730402, 0.998188, 1.259768, 1.699465, 2.578859",\ + "1.368610, 1.636396, 1.897976, 2.337672, 3.217067",\ + "0.530853, 0.798009, 1.060155, 1.499440, 2.378011",\ + "0.561708, 0.828864, 1.091010, 1.530295, 2.408865",\ + "0.623216, 0.890372, 1.152518, 1.591803, 2.470374",\ + "0.819106, 1.086263, 1.348409, 1.787694, 2.666264",\ + "1.457314, 1.724471, 1.986617, 2.425902, 3.304472",\ + "0.623795, 0.891154, 1.151881, 1.591604, 2.471052",\ + "0.654650, 0.922009, 1.182735, 1.622459, 2.501907",\ + "0.716158, 0.983517, 1.244244, 1.683967, 2.563416",\ + "0.912048, 1.179408, 1.440134, 1.879858, 2.759306",\ + "1.550256, 1.817616, 2.078342, 2.518066, 3.397514",\ + "0.689639, 0.959719, 1.218900, 1.658455, 2.537564",\ + "0.720493, 0.990574, 1.249755, 1.689310, 2.568418",\ + "0.782001, 1.052082, 1.311263, 1.750818, 2.629927",\ + "0.977892, 1.247972, 1.507154, 1.946708, 2.825817",\ + "1.616100, 1.886180, 2.145362, 2.584916, 3.464025",\ + "1.036160, 1.340554, 1.589563, 2.027608, 2.903699",\ + "1.067015, 1.371409, 1.620418, 2.058463, 2.934554",\ + "1.128523, 1.432917, 1.681926, 2.119972, 2.996062",\ + "1.324414, 1.628808, 1.877817, 2.315862, 3.191953",\ + "1.962622, 2.267016, 2.516025, 2.954070, 3.830161"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.050922, 0.050922, 0.050922, 0.050922, 0.050922",\ + "0.092496, 0.092496, 0.092496, 0.092496, 0.092497",\ + "0.193181, 0.193181, 0.193181, 0.193181, 0.193181",\ + "0.549207, 0.549207, 0.549207, 0.549207, 0.549207",\ + "1.718736, 1.718736, 1.718736, 1.718736, 1.718736",\ + "0.050922, 0.050922, 0.050922, 0.050922, 0.050922",\ + "0.092496, 0.092496, 0.092496, 0.092496, 0.092497",\ + "0.193181, 0.193181, 0.193181, 0.193181, 0.193181",\ + "0.549207, 0.549207, 0.549207, 0.549207, 0.549207",\ + "1.718736, 1.718736, 1.718736, 1.718736, 1.718736",\ + "0.050922, 0.050922, 0.050922, 0.050922, 0.050922",\ + "0.092496, 0.092496, 0.092496, 0.092496, 0.092497",\ + "0.193181, 0.193181, 0.193181, 0.193181, 0.193181",\ + "0.549207, 0.549207, 0.549207, 0.549207, 0.549207",\ + "1.718736, 1.718736, 1.718736, 1.718736, 1.718736",\ + "0.050922, 0.050922, 0.050922, 0.050922, 0.050922",\ + "0.092496, 0.092496, 0.092496, 0.092496, 0.092497",\ + "0.193181, 0.193181, 0.193181, 0.193181, 0.193181",\ + "0.549207, 0.549207, 0.549207, 0.549207, 0.549207",\ + "1.718736, 1.718736, 1.718736, 1.718736, 1.718736",\ + "0.050922, 0.050922, 0.050922, 0.050922, 0.050922",\ + "0.092496, 0.092496, 0.092496, 0.092496, 0.092497",\ + "0.193181, 0.193181, 0.193181, 0.193181, 0.193181",\ + "0.549207, 0.549207, 0.549207, 0.549207, 0.549207",\ + "1.718736, 1.718736, 1.718736, 1.718736, 1.718736"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[7]_redg_2746*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[1]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.468238, 0.731811, 1.008084, 1.476814, 2.414274",\ + "0.506163, 0.769737, 1.046010, 1.514740, 2.452199",\ + "0.587819, 0.851392, 1.127665, 1.596395, 2.533855",\ + "0.858268, 1.121841, 1.398114, 1.866844, 2.804303",\ + "1.744903, 2.008476, 2.284747, 2.753474, 3.690928",\ + "0.556432, 0.819352, 1.095652, 1.563529, 2.500207",\ + "0.594358, 0.857278, 1.133578, 1.601455, 2.538133",\ + "0.676013, 0.938933, 1.215233, 1.683110, 2.619789",\ + "0.946462, 1.209382, 1.485682, 1.953559, 2.890237",\ + "1.833097, 2.096017, 2.372314, 2.840189, 3.776862",\ + "0.644748, 0.908332, 1.183617, 1.651152, 2.587162",\ + "0.682674, 0.946258, 1.221542, 1.689077, 2.625088",\ + "0.764329, 1.027914, 1.303198, 1.770733, 2.706744",\ + "1.034778, 1.298362, 1.573647, 2.041182, 2.977192",\ + "1.921414, 2.184997, 2.460279, 2.927812, 3.863817",\ + "0.707244, 0.973967, 1.247756, 1.715065, 2.650671",\ + "0.745170, 1.011893, 1.285682, 1.752991, 2.688597",\ + "0.826825, 1.093549, 1.367337, 1.834647, 2.770253",\ + "1.097274, 1.363997, 1.637786, 2.105095, 3.040701",\ + "1.983909, 2.250632, 2.524419, 2.991725, 3.927326",\ + "1.036370, 1.338298, 1.599624, 2.064415, 2.996128",\ + "1.074296, 1.376224, 1.637549, 2.102341, 3.034053",\ + "1.155951, 1.457879, 1.719205, 2.183996, 3.115709",\ + "1.426400, 1.728328, 1.989653, 2.454445, 3.386157",\ + "2.313035, 2.614962, 2.876286, 3.341075, 4.272782"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.060311, 0.060311, 0.060311, 0.060311, 0.060311",\ + "0.120043, 0.120043, 0.120043, 0.120043, 0.120043",\ + "0.268820, 0.268820, 0.268820, 0.268820, 0.268819",\ + "0.790040, 0.790040, 0.790040, 0.790039, 0.790038",\ + "2.468303, 2.468303, 2.468303, 2.468303, 2.468304",\ + "0.060311, 0.060311, 0.060311, 0.060311, 0.060311",\ + "0.120043, 0.120043, 0.120043, 0.120043, 0.120043",\ + "0.268820, 0.268820, 0.268820, 0.268820, 0.268819",\ + "0.790040, 0.790040, 0.790040, 0.790039, 0.790038",\ + "2.468303, 2.468303, 2.468303, 2.468303, 2.468304",\ + "0.060311, 0.060311, 0.060311, 0.060311, 0.060311",\ + "0.120043, 0.120043, 0.120043, 0.120043, 0.120043",\ + "0.268820, 0.268820, 0.268820, 0.268820, 0.268819",\ + "0.790040, 0.790040, 0.790040, 0.790039, 0.790038",\ + "2.468303, 2.468303, 2.468303, 2.468303, 2.468304",\ + "0.060311, 0.060311, 0.060311, 0.060311, 0.060311",\ + "0.120043, 0.120043, 0.120043, 0.120043, 0.120043",\ + "0.268820, 0.268820, 0.268820, 0.268820, 0.268819",\ + "0.790040, 0.790040, 0.790040, 0.790039, 0.790038",\ + "2.468303, 2.468303, 2.468303, 2.468303, 2.468304",\ + "0.060311, 0.060311, 0.060311, 0.060311, 0.060311",\ + "0.120043, 0.120043, 0.120043, 0.120043, 0.120043",\ + "0.268820, 0.268820, 0.268820, 0.268820, 0.268819",\ + "0.790040, 0.790040, 0.790040, 0.790039, 0.790038",\ + "2.468303, 2.468303, 2.468303, 2.468303, 2.468304"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.425102, 0.607534, 0.803925, 1.112984, 1.707807",\ + "0.455957, 0.638388, 0.834779, 1.143839, 1.738662",\ + "0.517465, 0.699897, 0.896288, 1.205346, 1.800168",\ + "0.713355, 0.895787, 1.092178, 1.401236, 1.996057",\ + "1.351563, 1.533995, 1.730386, 2.039446, 2.634272",\ + "0.512517, 0.694919, 0.891418, 1.200289, 1.795161",\ + "0.543371, 0.725774, 0.922273, 1.231144, 1.826015",\ + "0.604879, 0.787282, 0.983781, 1.292651, 1.887522",\ + "0.800770, 0.983173, 1.179671, 1.488541, 2.083410",\ + "1.438978, 1.621381, 1.817879, 2.126751, 2.721625",\ + "0.593393, 0.775256, 0.971445, 1.280318, 1.875192",\ + "0.624248, 0.806111, 1.002299, 1.311172, 1.906047",\ + "0.685756, 0.867619, 1.063808, 1.372680, 1.967553",\ + "0.881646, 1.063509, 1.259698, 1.568570, 2.163442",\ + "1.519854, 1.701717, 1.897906, 2.206779, 2.801657",\ + "0.651039, 0.832804, 1.028988, 1.337563, 1.931840",\ + "0.681894, 0.863659, 1.059843, 1.368417, 1.962695",\ + "0.743402, 0.925167, 1.121351, 1.429925, 2.024201",\ + "0.939293, 1.121058, 1.317242, 1.625815, 2.220089",\ + "1.577501, 1.759266, 1.955450, 2.264025, 2.858304",\ + "0.953247, 1.138029, 1.332622, 1.640577, 2.233686",\ + "0.984102, 1.168883, 1.363477, 1.671432, 2.264541",\ + "1.045610, 1.230392, 1.424985, 1.732940, 2.326047",\ + "1.241500, 1.426282, 1.620876, 1.928830, 2.521936",\ + "1.879708, 2.064490, 2.259084, 2.567039, 3.160151"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.050922, 0.050922, 0.050922, 0.050923, 0.050926",\ + "0.092496, 0.092496, 0.092497, 0.092499, 0.092504",\ + "0.193181, 0.193181, 0.193181, 0.193181, 0.193182",\ + "0.549207, 0.549207, 0.549207, 0.549208, 0.549211",\ + "1.718736, 1.718736, 1.718736, 1.718741, 1.718751",\ + "0.050922, 0.050922, 0.050922, 0.050923, 0.050926",\ + "0.092496, 0.092496, 0.092497, 0.092499, 0.092504",\ + "0.193181, 0.193181, 0.193181, 0.193181, 0.193182",\ + "0.549207, 0.549207, 0.549207, 0.549208, 0.549211",\ + "1.718736, 1.718736, 1.718736, 1.718741, 1.718751",\ + "0.050922, 0.050922, 0.050922, 0.050923, 0.050926",\ + "0.092496, 0.092496, 0.092497, 0.092499, 0.092504",\ + "0.193181, 0.193181, 0.193181, 0.193181, 0.193182",\ + "0.549207, 0.549207, 0.549207, 0.549208, 0.549211",\ + "1.718736, 1.718736, 1.718736, 1.718741, 1.718751",\ + "0.050922, 0.050922, 0.050922, 0.050923, 0.050926",\ + "0.092496, 0.092496, 0.092497, 0.092499, 0.092504",\ + "0.193181, 0.193181, 0.193181, 0.193181, 0.193182",\ + "0.549207, 0.549207, 0.549207, 0.549208, 0.549211",\ + "1.718736, 1.718736, 1.718736, 1.718741, 1.718751",\ + "0.050922, 0.050922, 0.050922, 0.050923, 0.050926",\ + "0.092496, 0.092496, 0.092497, 0.092499, 0.092504",\ + "0.193181, 0.193181, 0.193181, 0.193181, 0.193182",\ + "0.549207, 0.549207, 0.549207, 0.549208, 0.549211",\ + "1.718736, 1.718736, 1.718736, 1.718741, 1.718751"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[7]_redg_2673*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[2]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.464262, 0.723892, 0.995764, 1.452644, 2.366404",\ + "0.502188, 0.761817, 1.033690, 1.490570, 2.404330",\ + "0.583843, 0.843473, 1.115345, 1.572225, 2.485985",\ + "0.854292, 1.113922, 1.385794, 1.842674, 2.756433",\ + "1.740928, 2.000556, 2.272425, 2.729303, 3.643060",\ + "0.552367, 0.811425, 1.083295, 1.539359, 2.452338",\ + "0.590293, 0.849351, 1.121220, 1.577285, 2.490263",\ + "0.671948, 0.931006, 1.202876, 1.658941, 2.571919",\ + "0.942397, 1.201455, 1.473325, 1.929389, 2.842367",\ + "1.829032, 2.088089, 2.359956, 2.816019, 3.728994",\ + "0.640397, 0.900391, 1.171259, 1.626982, 2.539293",\ + "0.678323, 0.938317, 1.209185, 1.664908, 2.577219",\ + "0.759978, 1.019972, 1.290840, 1.746563, 2.658874",\ + "1.030427, 1.290421, 1.561289, 2.017012, 2.929322",\ + "1.917063, 2.177055, 2.447920, 2.903641, 3.815949",\ + "0.702618, 0.966004, 1.235397, 1.690896, 2.602802",\ + "0.740544, 1.003930, 1.273322, 1.728822, 2.640728",\ + "0.822200, 1.085586, 1.354978, 1.810477, 2.722383",\ + "1.092649, 1.356035, 1.625427, 2.080925, 2.992831",\ + "1.979284, 2.242668, 2.512058, 2.967555, 3.879458",\ + "1.030006, 1.330079, 1.587144, 2.040197, 2.948258",\ + "1.067932, 1.368005, 1.625070, 2.078122, 2.986184",\ + "1.149587, 1.449661, 1.706725, 2.159778, 3.067839",\ + "1.420036, 1.720109, 1.977174, 2.430226, 3.338287",\ + "2.306671, 2.606743, 2.863805, 3.316856, 4.224914"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.060311, 0.060311, 0.060311, 0.060311, 0.060311",\ + "0.120043, 0.120043, 0.120043, 0.120043, 0.120043",\ + "0.268820, 0.268820, 0.268820, 0.268819, 0.268818",\ + "0.790040, 0.790040, 0.790039, 0.790039, 0.790038",\ + "2.468303, 2.468303, 2.468303, 2.468303, 2.468304",\ + "0.060311, 0.060311, 0.060311, 0.060311, 0.060311",\ + "0.120043, 0.120043, 0.120043, 0.120043, 0.120043",\ + "0.268820, 0.268820, 0.268820, 0.268819, 0.268818",\ + "0.790040, 0.790040, 0.790039, 0.790039, 0.790038",\ + "2.468303, 2.468303, 2.468303, 2.468303, 2.468304",\ + "0.060311, 0.060311, 0.060311, 0.060311, 0.060311",\ + "0.120043, 0.120043, 0.120043, 0.120043, 0.120043",\ + "0.268820, 0.268820, 0.268820, 0.268819, 0.268818",\ + "0.790040, 0.790040, 0.790039, 0.790039, 0.790038",\ + "2.468303, 2.468303, 2.468303, 2.468303, 2.468304",\ + "0.060311, 0.060311, 0.060311, 0.060311, 0.060311",\ + "0.120043, 0.120043, 0.120043, 0.120043, 0.120043",\ + "0.268820, 0.268820, 0.268820, 0.268819, 0.268818",\ + "0.790040, 0.790040, 0.790039, 0.790039, 0.790038",\ + "2.468303, 2.468303, 2.468303, 2.468303, 2.468304",\ + "0.060311, 0.060311, 0.060311, 0.060311, 0.060311",\ + "0.120043, 0.120043, 0.120043, 0.120043, 0.120043",\ + "0.268820, 0.268820, 0.268820, 0.268819, 0.268818",\ + "0.790040, 0.790040, 0.790039, 0.790039, 0.790038",\ + "2.468303, 2.468303, 2.468303, 2.468303, 2.468304"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.423440, 0.605981, 0.802235, 1.111459, 1.706773",\ + "0.454295, 0.636836, 0.833090, 1.142314, 1.737628",\ + "0.515803, 0.698344, 0.894598, 1.203821, 1.799134",\ + "0.711694, 0.894235, 1.090489, 1.399711, 1.995022",\ + "1.349902, 1.532443, 1.728697, 2.037921, 2.633238",\ + "0.510860, 0.693367, 0.889728, 1.198764, 1.794126",\ + "0.541715, 0.724221, 0.920583, 1.229619, 1.824981",\ + "0.603223, 0.785730, 0.982091, 1.291126, 1.886487",\ + "0.799114, 0.981620, 1.177981, 1.487016, 2.082375",\ + "1.437322, 1.619828, 1.816189, 2.125226, 2.720591",\ + "0.591728, 0.773704, 0.969755, 1.278793, 1.874158",\ + "0.622583, 0.804558, 1.000610, 1.309647, 1.905013",\ + "0.684091, 0.866066, 1.062118, 1.371155, 1.966519",\ + "0.879981, 1.061957, 1.258008, 1.567045, 2.162407",\ + "1.518189, 1.700165, 1.896216, 2.205255, 2.800623",\ + "0.649367, 0.831252, 1.027299, 1.336038, 1.930805",\ + "0.680222, 0.862107, 1.058154, 1.366893, 1.961660",\ + "0.741730, 0.923615, 1.119662, 1.428400, 2.023166",\ + "0.937620, 1.119505, 1.315552, 1.624290, 2.219054",\ + "1.575828, 1.757713, 1.953760, 2.262500, 2.857270",\ + "0.951462, 1.136478, 1.330933, 1.639053, 2.232652",\ + "0.982317, 1.167333, 1.361788, 1.669907, 2.263507",\ + "1.043825, 1.228841, 1.423296, 1.731415, 2.325013",\ + "1.239715, 1.424732, 1.619186, 1.927305, 2.520901",\ + "1.877923, 2.062940, 2.257394, 2.565515, 3.159117"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.050922, 0.050922, 0.050922, 0.050923, 0.050926",\ + "0.092496, 0.092496, 0.092497, 0.092499, 0.092505",\ + "0.193181, 0.193181, 0.193181, 0.193181, 0.193182",\ + "0.549207, 0.549207, 0.549207, 0.549209, 0.549212",\ + "1.718736, 1.718736, 1.718736, 1.718741, 1.718753",\ + "0.050922, 0.050922, 0.050922, 0.050923, 0.050926",\ + "0.092496, 0.092496, 0.092497, 0.092499, 0.092505",\ + "0.193181, 0.193181, 0.193181, 0.193181, 0.193182",\ + "0.549207, 0.549207, 0.549207, 0.549209, 0.549212",\ + "1.718736, 1.718736, 1.718736, 1.718741, 1.718753",\ + "0.050922, 0.050922, 0.050922, 0.050923, 0.050926",\ + "0.092496, 0.092496, 0.092497, 0.092499, 0.092505",\ + "0.193181, 0.193181, 0.193181, 0.193181, 0.193182",\ + "0.549207, 0.549207, 0.549207, 0.549209, 0.549212",\ + "1.718736, 1.718736, 1.718736, 1.718741, 1.718753",\ + "0.050922, 0.050922, 0.050922, 0.050923, 0.050926",\ + "0.092496, 0.092496, 0.092497, 0.092499, 0.092505",\ + "0.193181, 0.193181, 0.193181, 0.193181, 0.193182",\ + "0.549207, 0.549207, 0.549207, 0.549209, 0.549212",\ + "1.718736, 1.718736, 1.718736, 1.718741, 1.718753",\ + "0.050922, 0.050922, 0.050922, 0.050923, 0.050926",\ + "0.092496, 0.092496, 0.092497, 0.092499, 0.092505",\ + "0.193181, 0.193181, 0.193181, 0.193181, 0.193182",\ + "0.549207, 0.549207, 0.549207, 0.549209, 0.549212",\ + "1.718736, 1.718736, 1.718736, 1.718741, 1.718753"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[7]_redg_2611*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[3]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.556546, 0.734973, 0.915233, 1.201439, 1.752556",\ + "0.594472, 0.772898, 0.953159, 1.239365, 1.790482",\ + "0.676127, 0.854554, 1.034814, 1.321021, 1.872138",\ + "0.946576, 1.125003, 1.305263, 1.591470, 2.142586",\ + "1.833212, 2.011638, 2.191898, 2.478105, 3.029221",\ + "0.641484, 0.820245, 1.001148, 1.287360, 1.838935",\ + "0.679410, 0.858171, 1.039074, 1.325286, 1.876861",\ + "0.761066, 0.939826, 1.120729, 1.406941, 1.958516",\ + "1.031515, 1.210275, 1.391178, 1.677390, 2.228965",\ + "1.918150, 2.096910, 2.277814, 2.564025, 3.115599",\ + "0.717390, 0.895688, 1.075957, 1.361957, 1.913107",\ + "0.755316, 0.933614, 1.113883, 1.399882, 1.951033",\ + "0.836972, 1.015270, 1.195538, 1.481538, 2.032688",\ + "1.107421, 1.285719, 1.465987, 1.751987, 2.303137",\ + "1.994056, 2.172354, 2.352623, 2.638622, 3.189771",\ + "0.771742, 0.950200, 1.130608, 1.416496, 1.967424",\ + "0.809668, 0.988126, 1.168534, 1.454422, 2.005350",\ + "0.891324, 1.069781, 1.250189, 1.536077, 2.087006",\ + "1.161773, 1.340230, 1.520638, 1.806526, 2.357455",\ + "2.048408, 2.226866, 2.407274, 2.693161, 3.244089",\ + "1.053164, 1.235427, 1.414559, 1.700223, 2.250702",\ + "1.091090, 1.273353, 1.452485, 1.738148, 2.288628",\ + "1.172746, 1.355009, 1.534140, 1.819804, 2.370283",\ + "1.443195, 1.625458, 1.804589, 2.090253, 2.640732",\ + "2.329830, 2.512093, 2.691224, 2.976888, 3.527366"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.060311, 0.060311, 0.060311, 0.060311, 0.060311",\ + "0.120043, 0.120043, 0.120043, 0.120043, 0.120043",\ + "0.268820, 0.268820, 0.268820, 0.268820, 0.268820",\ + "0.790040, 0.790040, 0.790040, 0.790040, 0.790040",\ + "2.468303, 2.468303, 2.468303, 2.468303, 2.468303",\ + "0.060311, 0.060311, 0.060311, 0.060311, 0.060311",\ + "0.120043, 0.120043, 0.120043, 0.120043, 0.120043",\ + "0.268820, 0.268820, 0.268820, 0.268820, 0.268820",\ + "0.790040, 0.790040, 0.790040, 0.790040, 0.790040",\ + "2.468303, 2.468303, 2.468303, 2.468303, 2.468303",\ + "0.060311, 0.060311, 0.060311, 0.060311, 0.060311",\ + "0.120043, 0.120043, 0.120043, 0.120043, 0.120043",\ + "0.268820, 0.268820, 0.268820, 0.268820, 0.268820",\ + "0.790040, 0.790040, 0.790040, 0.790040, 0.790040",\ + "2.468303, 2.468303, 2.468303, 2.468303, 2.468303",\ + "0.060311, 0.060311, 0.060311, 0.060311, 0.060311",\ + "0.120043, 0.120043, 0.120043, 0.120043, 0.120043",\ + "0.268820, 0.268820, 0.268820, 0.268820, 0.268820",\ + "0.790040, 0.790040, 0.790040, 0.790040, 0.790040",\ + "2.468303, 2.468303, 2.468303, 2.468303, 2.468303",\ + "0.060311, 0.060311, 0.060311, 0.060311, 0.060311",\ + "0.120043, 0.120043, 0.120043, 0.120043, 0.120043",\ + "0.268820, 0.268820, 0.268820, 0.268820, 0.268820",\ + "0.790040, 0.790040, 0.790040, 0.790040, 0.790040",\ + "2.468303, 2.468303, 2.468303, 2.468303, 2.468303"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.440713, 0.705883, 0.965084, 1.401266, 2.273631",\ + "0.471568, 0.736737, 0.995939, 1.432121, 2.304486",\ + "0.533076, 0.798245, 1.057447, 1.493629, 2.365994",\ + "0.728966, 0.994136, 1.253338, 1.689520, 2.561884",\ + "1.367174, 1.632344, 1.891546, 2.327728, 3.200092",\ + "0.529378, 0.793957, 1.053725, 1.489495, 2.361036",\ + "0.560233, 0.824812, 1.084580, 1.520350, 2.391891",\ + "0.621741, 0.886320, 1.146088, 1.581858, 2.453399",\ + "0.817632, 1.082211, 1.341978, 1.777749, 2.649290",\ + "1.455840, 1.720419, 1.980186, 2.415956, 3.287497",\ + "0.622185, 0.887080, 1.145450, 1.581659, 2.454078",\ + "0.653040, 0.917935, 1.176305, 1.612514, 2.484932",\ + "0.714548, 0.979443, 1.237813, 1.674022, 2.546441",\ + "0.910438, 1.175334, 1.433704, 1.869913, 2.742332",\ + "1.548646, 1.813542, 2.071912, 2.508121, 3.380539",\ + "0.687908, 0.955615, 1.212470, 1.648510, 2.520589",\ + "0.718762, 0.986469, 1.243325, 1.679364, 2.551444",\ + "0.780270, 1.047977, 1.304833, 1.740873, 2.612952",\ + "0.976161, 1.243868, 1.500724, 1.936763, 2.808843",\ + "1.614369, 1.882076, 2.138932, 2.574971, 3.447050",\ + "1.033697, 1.336113, 1.583101, 2.017641, 2.886722",\ + "1.064552, 1.366968, 1.613955, 2.048496, 2.917577",\ + "1.126060, 1.428476, 1.675463, 2.110004, 2.979085",\ + "1.321950, 1.624366, 1.871354, 2.305894, 3.174975",\ + "1.960158, 2.262574, 2.509562, 2.944102, 3.813183"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.050922, 0.050922, 0.050922, 0.050922, 0.050922",\ + "0.092496, 0.092496, 0.092496, 0.092496, 0.092497",\ + "0.193181, 0.193181, 0.193181, 0.193181, 0.193181",\ + "0.549207, 0.549207, 0.549207, 0.549207, 0.549207",\ + "1.718736, 1.718736, 1.718736, 1.718736, 1.718736",\ + "0.050922, 0.050922, 0.050922, 0.050922, 0.050922",\ + "0.092496, 0.092496, 0.092496, 0.092496, 0.092497",\ + "0.193181, 0.193181, 0.193181, 0.193181, 0.193181",\ + "0.549207, 0.549207, 0.549207, 0.549207, 0.549207",\ + "1.718736, 1.718736, 1.718736, 1.718736, 1.718736",\ + "0.050922, 0.050922, 0.050922, 0.050922, 0.050922",\ + "0.092496, 0.092496, 0.092496, 0.092496, 0.092497",\ + "0.193181, 0.193181, 0.193181, 0.193181, 0.193181",\ + "0.549207, 0.549207, 0.549207, 0.549207, 0.549207",\ + "1.718736, 1.718736, 1.718736, 1.718736, 1.718736",\ + "0.050922, 0.050922, 0.050922, 0.050922, 0.050922",\ + "0.092496, 0.092496, 0.092496, 0.092496, 0.092497",\ + "0.193181, 0.193181, 0.193181, 0.193181, 0.193181",\ + "0.549207, 0.549207, 0.549207, 0.549207, 0.549207",\ + "1.718736, 1.718736, 1.718736, 1.718736, 1.718736",\ + "0.050922, 0.050922, 0.050922, 0.050922, 0.050922",\ + "0.092496, 0.092496, 0.092496, 0.092496, 0.092497",\ + "0.193181, 0.193181, 0.193181, 0.193181, 0.193181",\ + "0.549207, 0.549207, 0.549207, 0.549207, 0.549207",\ + "1.718736, 1.718736, 1.718736, 1.718736, 1.718736"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[7]_redg_2557*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + values ( "380001.875000, 380001.906250, 380002.000000, 380002.250000, 380003.156250",\ + "380001.968750, 380002.000000, 380002.093750, 380002.343750, 380003.250000",\ + "380002.031250, 380002.062500, 380002.156250, 380002.406250, 380003.312500",\ + "380002.093750, 380002.125000, 380002.218750, 380002.468750, 380003.375000",\ + "380002.406250, 380002.437500, 380002.531250, 380002.781250, 380003.687500"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + values ( "0.060312, 0.120043, 0.268889, 0.790048, 2.471058",\ + "0.060312, 0.120043, 0.268889, 0.790048, 2.471058",\ + "0.060312, 0.120043, 0.268889, 0.790048, 2.471058",\ + "0.060311, 0.120043, 0.268889, 0.790048, 2.471058",\ + "0.060311, 0.120043, 0.268889, 0.790048, 2.468313"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + values ( "380003.906250, 380003.937500, 380004.000000, 380004.187500, 380004.843750",\ + "380004.000000, 380004.031250, 380004.093750, 380004.281250, 380004.937500",\ + "380004.093750, 380004.125000, 380004.187500, 380004.375000, 380005.031250",\ + "380004.156250, 380004.187500, 380004.250000, 380004.437500, 380005.093750",\ + "380004.500000, 380004.531250, 380004.593750, 380004.781250, 380005.437500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + values ( "0.050922, 0.092579, 0.193181, 0.549207, 1.721959",\ + "0.050922, 0.092579, 0.193181, 0.549207, 1.721959",\ + "0.050922, 0.092579, 0.193181, 0.549207, 1.721959",\ + "0.050922, 0.092579, 0.193181, 0.549207, 1.721959",\ + "0.050984, 0.092651, 0.193203, 0.549286, 1.721959"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[7]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[0]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.544292, 0.724406, 0.911984, 1.213964, 1.797060",\ + "0.582447, 0.762561, 0.950139, 1.252119, 1.835215",\ + "0.664874, 0.844988, 1.032566, 1.334546, 1.917642",\ + "0.936033, 1.116146, 1.303725, 1.605704, 2.188801",\ + "1.821919, 2.002032, 2.189611, 2.491591, 3.074687",\ + "0.629231, 0.809242, 0.997054, 1.299470, 1.883439",\ + "0.667386, 0.847397, 1.035209, 1.337625, 1.921593",\ + "0.749812, 0.929824, 1.117636, 1.420052, 2.004020",\ + "1.020971, 1.200982, 1.388795, 1.691211, 2.275179",\ + "1.906857, 2.086868, 2.274681, 2.577097, 3.161065",\ + "0.705143, 0.884685, 1.071863, 1.374067, 1.957611",\ + "0.743298, 0.922840, 1.110018, 1.412222, 1.995766",\ + "0.825724, 1.005267, 1.192445, 1.494649, 2.078193",\ + "1.096883, 1.276425, 1.463604, 1.765808, 2.349351",\ + "1.982769, 2.162312, 2.349490, 2.651694, 3.235237",\ + "0.759512, 0.939436, 1.126752, 1.428673, 2.011928",\ + "0.797667, 0.977591, 1.164907, 1.466828, 2.050083",\ + "0.880094, 1.060018, 1.247334, 1.549255, 2.132510",\ + "1.151252, 1.331177, 1.518492, 1.820413, 2.403668",\ + "2.037138, 2.217063, 2.404379, 2.706299, 3.289555",\ + "1.041107, 1.225001, 1.410928, 1.712399, 2.295206",\ + "1.079262, 1.263156, 1.449083, 1.750554, 2.333361",\ + "1.161688, 1.345583, 1.531509, 1.832981, 2.415788",\ + "1.432847, 1.616742, 1.802668, 2.104139, 2.686946",\ + "2.318733, 2.502628, 2.688554, 2.990026, 3.572832"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.050112, 0.050112, 0.050112, 0.050112, 0.050112",\ + "0.112175, 0.112175, 0.112175, 0.112175, 0.112175",\ + "0.264098, 0.264098, 0.264098, 0.264098, 0.264098",\ + "0.776079, 0.776079, 0.776079, 0.776079, 0.776079",\ + "2.446671, 2.446671, 2.446671, 2.446671, 2.446672",\ + "0.050112, 0.050112, 0.050112, 0.050112, 0.050112",\ + "0.112175, 0.112175, 0.112175, 0.112175, 0.112175",\ + "0.264098, 0.264098, 0.264098, 0.264098, 0.264098",\ + "0.776079, 0.776079, 0.776079, 0.776079, 0.776079",\ + "2.446671, 2.446671, 2.446671, 2.446671, 2.446672",\ + "0.050112, 0.050112, 0.050112, 0.050112, 0.050112",\ + "0.112175, 0.112175, 0.112175, 0.112175, 0.112175",\ + "0.264098, 0.264098, 0.264098, 0.264098, 0.264098",\ + "0.776079, 0.776079, 0.776079, 0.776079, 0.776079",\ + "2.446671, 2.446671, 2.446671, 2.446671, 2.446672",\ + "0.050112, 0.050112, 0.050112, 0.050112, 0.050112",\ + "0.112175, 0.112175, 0.112175, 0.112175, 0.112175",\ + "0.264098, 0.264098, 0.264098, 0.264098, 0.264098",\ + "0.776079, 0.776079, 0.776079, 0.776079, 0.776079",\ + "2.446671, 2.446671, 2.446671, 2.446671, 2.446672",\ + "0.050112, 0.050112, 0.050112, 0.050112, 0.050112",\ + "0.112175, 0.112175, 0.112175, 0.112175, 0.112175",\ + "0.264098, 0.264098, 0.264098, 0.264098, 0.264098",\ + "0.776079, 0.776079, 0.776079, 0.776079, 0.776079",\ + "2.446671, 2.446671, 2.446671, 2.446671, 2.446672"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.363069, 0.630679, 0.892080, 1.331857, 2.211017",\ + "0.391013, 0.658624, 0.920025, 1.359801, 2.238962",\ + "0.450465, 0.718075, 0.979476, 1.419253, 2.298413",\ + "0.646065, 0.913676, 1.175077, 1.614853, 2.494013",\ + "1.283402, 1.551012, 1.812413, 2.252190, 3.131351",\ + "0.451773, 0.718754, 0.980721, 1.420086, 2.298422",\ + "0.479717, 0.746699, 1.008666, 1.448030, 2.326367",\ + "0.539169, 0.806150, 1.068117, 1.507482, 2.385818",\ + "0.734769, 1.001751, 1.263718, 1.703082, 2.581419",\ + "1.372106, 1.639087, 1.901054, 2.340420, 3.218756",\ + "0.544715, 0.812075, 1.072766, 1.512332, 2.391464",\ + "0.572660, 0.840019, 1.100710, 1.540276, 2.419409",\ + "0.632111, 0.899470, 1.160161, 1.599728, 2.478860",\ + "0.827712, 1.095071, 1.355762, 1.795328, 2.674460",\ + "1.465048, 1.732408, 1.993099, 2.432665, 3.311798",\ + "0.610559, 0.880639, 1.139822, 1.579343, 2.458386",\ + "0.638503, 0.908583, 1.167766, 1.607288, 2.486331",\ + "0.697955, 0.968035, 1.227218, 1.666739, 2.545782",\ + "0.893555, 1.163635, 1.422818, 1.862339, 2.741382",\ + "1.530892, 1.800972, 2.060155, 2.499676, 3.378720",\ + "0.957080, 1.261474, 1.510493, 1.948569, 2.824721",\ + "0.985025, 1.289419, 1.538437, 1.976513, 2.852666",\ + "1.044476, 1.348870, 1.597888, 2.035964, 2.912117",\ + "1.240077, 1.544471, 1.793489, 2.231565, 3.107717",\ + "1.877413, 2.181808, 2.430826, 2.868902, 3.745055"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.040709, 0.040709, 0.040709, 0.040709, 0.040708",\ + "0.082941, 0.082941, 0.082941, 0.082941, 0.082941",\ + "0.186774, 0.186774, 0.186774, 0.186774, 0.186773",\ + "0.543828, 0.543828, 0.543828, 0.543829, 0.543829",\ + "1.713838, 1.713838, 1.713838, 1.713837, 1.713836",\ + "0.040709, 0.040709, 0.040709, 0.040709, 0.040708",\ + "0.082941, 0.082941, 0.082941, 0.082941, 0.082941",\ + "0.186774, 0.186774, 0.186774, 0.186774, 0.186773",\ + "0.543828, 0.543828, 0.543828, 0.543829, 0.543829",\ + "1.713838, 1.713838, 1.713838, 1.713837, 1.713836",\ + "0.040709, 0.040709, 0.040709, 0.040709, 0.040708",\ + "0.082941, 0.082941, 0.082941, 0.082941, 0.082941",\ + "0.186774, 0.186774, 0.186774, 0.186774, 0.186773",\ + "0.543828, 0.543828, 0.543828, 0.543829, 0.543829",\ + "1.713838, 1.713838, 1.713838, 1.713837, 1.713836",\ + "0.040709, 0.040709, 0.040709, 0.040709, 0.040708",\ + "0.082941, 0.082941, 0.082941, 0.082941, 0.082941",\ + "0.186774, 0.186774, 0.186774, 0.186774, 0.186773",\ + "0.543828, 0.543828, 0.543828, 0.543829, 0.543829",\ + "1.713838, 1.713838, 1.713838, 1.713837, 1.713836",\ + "0.040709, 0.040709, 0.040709, 0.040709, 0.040708",\ + "0.082941, 0.082941, 0.082941, 0.082941, 0.082941",\ + "0.186774, 0.186774, 0.186774, 0.186774, 0.186773",\ + "0.543828, 0.543828, 0.543828, 0.543829, 0.543829",\ + "1.713838, 1.713838, 1.713838, 1.713837, 1.713836"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[7]_redg_min_2500*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[1]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.452401, 0.715932, 0.992051, 1.460182, 2.395185",\ + "0.490556, 0.754087, 1.030206, 1.498337, 2.433340",\ + "0.572982, 0.836514, 1.112633, 1.580764, 2.515767",\ + "0.844141, 1.107672, 1.383791, 1.851923, 2.786925",\ + "1.730027, 1.993558, 2.269678, 2.737809, 3.672812",\ + "0.540595, 0.803472, 1.079618, 1.546898, 2.481119",\ + "0.578750, 0.841627, 1.117773, 1.585052, 2.519274",\ + "0.661177, 0.924054, 1.200200, 1.667479, 2.601700",\ + "0.932335, 1.195213, 1.471358, 1.938638, 2.872859",\ + "1.818222, 2.081099, 2.357244, 2.824524, 3.758746",\ + "0.628911, 0.892452, 1.167583, 1.634538, 2.568074",\ + "0.667066, 0.930607, 1.205738, 1.672693, 2.606229",\ + "0.749493, 1.013034, 1.288164, 1.755120, 2.688655",\ + "1.020651, 1.284192, 1.559323, 2.026278, 2.959814",\ + "1.906538, 2.170078, 2.445210, 2.912164, 3.845701",\ + "0.691407, 0.958086, 1.231722, 1.698627, 2.631583",\ + "0.729562, 0.996240, 1.269877, 1.736781, 2.669738",\ + "0.811989, 1.078667, 1.352304, 1.819208, 2.752164",\ + "1.083147, 1.349826, 1.623463, 2.090367, 3.023323",\ + "1.969034, 2.235712, 2.509349, 2.976254, 3.909210",\ + "1.020533, 1.322400, 1.583586, 2.048070, 2.977039",\ + "1.058688, 1.360555, 1.621741, 2.086226, 3.015194",\ + "1.141114, 1.442982, 1.704168, 2.168652, 3.097620",\ + "1.412273, 1.714141, 1.975327, 2.439811, 3.368779",\ + "2.298159, 2.600027, 2.861213, 3.325697, 4.254666"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.050112, 0.050112, 0.050112, 0.050111, 0.050111",\ + "0.112175, 0.112175, 0.112175, 0.112175, 0.112174",\ + "0.264098, 0.264098, 0.264098, 0.264098, 0.264098",\ + "0.776079, 0.776079, 0.776079, 0.776079, 0.776079",\ + "2.446670, 2.446672, 2.446677, 2.446682, 2.446693",\ + "0.050112, 0.050112, 0.050112, 0.050111, 0.050111",\ + "0.112175, 0.112175, 0.112175, 0.112175, 0.112174",\ + "0.264098, 0.264098, 0.264098, 0.264098, 0.264098",\ + "0.776079, 0.776079, 0.776079, 0.776079, 0.776079",\ + "2.446670, 2.446672, 2.446677, 2.446682, 2.446693",\ + "0.050112, 0.050112, 0.050112, 0.050111, 0.050111",\ + "0.112175, 0.112175, 0.112175, 0.112175, 0.112174",\ + "0.264098, 0.264098, 0.264098, 0.264098, 0.264098",\ + "0.776079, 0.776079, 0.776079, 0.776079, 0.776079",\ + "2.446670, 2.446672, 2.446677, 2.446682, 2.446693",\ + "0.050112, 0.050112, 0.050112, 0.050111, 0.050111",\ + "0.112175, 0.112175, 0.112175, 0.112175, 0.112174",\ + "0.264098, 0.264098, 0.264098, 0.264098, 0.264098",\ + "0.776079, 0.776079, 0.776079, 0.776079, 0.776079",\ + "2.446670, 2.446672, 2.446677, 2.446682, 2.446693",\ + "0.050112, 0.050112, 0.050112, 0.050111, 0.050111",\ + "0.112175, 0.112175, 0.112175, 0.112175, 0.112174",\ + "0.264098, 0.264098, 0.264098, 0.264098, 0.264098",\ + "0.776079, 0.776079, 0.776079, 0.776079, 0.776079",\ + "2.446670, 2.446673, 2.446677, 2.446682, 2.446693"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.346024, 0.528081, 0.724314, 1.033489, 1.627960",\ + "0.373968, 0.556026, 0.752258, 1.061434, 1.655906",\ + "0.433420, 0.615477, 0.811710, 1.120886, 1.715360",\ + "0.629020, 0.811078, 1.007310, 1.316483, 1.910951",\ + "1.266357, 1.448414, 1.644648, 1.953829, 2.548313",\ + "0.433439, 0.615400, 0.811595, 1.120794, 1.715314",\ + "0.461383, 0.643345, 0.839539, 1.148739, 1.743259",\ + "0.520834, 0.702796, 0.898991, 1.208191, 1.802713",\ + "0.716435, 0.898396, 1.094591, 1.403789, 1.998304",\ + "1.353772, 1.535733, 1.731929, 2.041134, 2.635666",\ + "0.514315, 0.695737, 0.891622, 1.200823, 1.795345",\ + "0.542259, 0.723681, 0.919566, 1.228768, 1.823291",\ + "0.601711, 0.783132, 0.979018, 1.288220, 1.882745",\ + "0.797311, 0.978733, 1.174618, 1.483817, 2.078336",\ + "1.434648, 1.616070, 1.811956, 2.121162, 2.715698",\ + "0.571961, 0.753573, 0.949357, 1.258293, 1.852441",\ + "0.599906, 0.781518, 0.977302, 1.286238, 1.880386",\ + "0.659357, 0.840969, 1.036753, 1.345690, 1.939840",\ + "0.854958, 1.036570, 1.232353, 1.541288, 2.135431",\ + "1.492294, 1.673906, 1.869692, 2.178633, 2.772793",\ + "0.874169, 1.058951, 1.253021, 1.561500, 2.154759",\ + "0.902114, 1.086895, 1.280965, 1.589445, 2.182705",\ + "0.961565, 1.146346, 1.340417, 1.648897, 2.242158",\ + "1.157166, 1.341947, 1.536017, 1.844495, 2.437749",\ + "1.794502, 1.979284, 2.173355, 2.481840, 3.075111"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.040709, 0.040709, 0.040708, 0.040708, 0.040708",\ + "0.082941, 0.082941, 0.082941, 0.082941, 0.082941",\ + "0.186774, 0.186774, 0.186773, 0.186772, 0.186770",\ + "0.543828, 0.543828, 0.543829, 0.543834, 0.543845",\ + "1.713838, 1.713838, 1.713836, 1.713827, 1.713805",\ + "0.040709, 0.040709, 0.040708, 0.040708, 0.040708",\ + "0.082941, 0.082941, 0.082941, 0.082941, 0.082941",\ + "0.186774, 0.186774, 0.186773, 0.186772, 0.186770",\ + "0.543828, 0.543828, 0.543829, 0.543834, 0.543845",\ + "1.713838, 1.713838, 1.713836, 1.713827, 1.713805",\ + "0.040709, 0.040709, 0.040708, 0.040708, 0.040708",\ + "0.082941, 0.082941, 0.082941, 0.082941, 0.082941",\ + "0.186774, 0.186774, 0.186773, 0.186772, 0.186770",\ + "0.543828, 0.543828, 0.543829, 0.543834, 0.543845",\ + "1.713838, 1.713838, 1.713836, 1.713827, 1.713805",\ + "0.040709, 0.040709, 0.040708, 0.040708, 0.040708",\ + "0.082941, 0.082941, 0.082941, 0.082941, 0.082941",\ + "0.186774, 0.186774, 0.186773, 0.186772, 0.186770",\ + "0.543828, 0.543828, 0.543829, 0.543834, 0.543845",\ + "1.713838, 1.713838, 1.713836, 1.713827, 1.713805",\ + "0.040709, 0.040709, 0.040708, 0.040708, 0.040708",\ + "0.082941, 0.082941, 0.082941, 0.082941, 0.082941",\ + "0.186774, 0.186774, 0.186773, 0.186772, 0.186770",\ + "0.543828, 0.543828, 0.543829, 0.543834, 0.543845",\ + "1.713838, 1.713838, 1.713836, 1.713827, 1.713805"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[7]_redg_min_2425*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[2]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.448423, 0.707982, 0.979616, 1.435777, 2.346942",\ + "0.486578, 0.746137, 1.017771, 1.473932, 2.385097",\ + "0.569004, 0.828563, 1.100198, 1.556358, 2.467524",\ + "0.840163, 1.099722, 1.371357, 1.827517, 2.738683",\ + "1.726049, 1.985608, 2.257243, 2.713404, 3.624570",\ + "0.536527, 0.795515, 1.067145, 1.522492, 2.432876",\ + "0.574682, 0.833670, 1.105300, 1.560647, 2.471031",\ + "0.657109, 0.916096, 1.187727, 1.643074, 2.553458",\ + "0.928268, 1.187255, 1.458886, 1.914232, 2.824616",\ + "1.814154, 2.073141, 2.344772, 2.800119, 3.710504",\ + "0.624558, 0.884479, 1.155110, 1.610131, 2.519831",\ + "0.662712, 0.922634, 1.193264, 1.648286, 2.557986",\ + "0.745139, 1.005061, 1.275691, 1.730713, 2.640413",\ + "1.016298, 1.276219, 1.546850, 2.001871, 2.911571",\ + "1.902184, 2.162105, 2.432736, 2.887758, 3.797459",\ + "0.686779, 0.950090, 1.219247, 1.674205, 2.583340",\ + "0.724934, 0.988245, 1.257402, 1.712360, 2.621495",\ + "0.807361, 1.070672, 1.339829, 1.794787, 2.703922",\ + "1.078519, 1.341830, 1.610988, 2.065946, 2.975080",\ + "1.964405, 2.227717, 2.496874, 2.951832, 3.860968",\ + "1.014166, 1.314139, 1.570990, 2.023592, 2.928796",\ + "1.052321, 1.352293, 1.609145, 2.061747, 2.966951",\ + "1.134748, 1.434720, 1.691572, 2.144174, 3.049378",\ + "1.405907, 1.705879, 1.962730, 2.415332, 3.320536",\ + "2.291793, 2.591765, 2.848617, 3.301219, 4.206424"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.050112, 0.050112, 0.050112, 0.050111, 0.050111",\ + "0.112175, 0.112175, 0.112175, 0.112175, 0.112174",\ + "0.264098, 0.264098, 0.264098, 0.264098, 0.264098",\ + "0.776079, 0.776079, 0.776079, 0.776079, 0.776079",\ + "2.446671, 2.446674, 2.446680, 2.446683, 2.446690",\ + "0.050112, 0.050112, 0.050112, 0.050111, 0.050111",\ + "0.112175, 0.112175, 0.112175, 0.112175, 0.112174",\ + "0.264098, 0.264098, 0.264098, 0.264098, 0.264098",\ + "0.776079, 0.776079, 0.776079, 0.776079, 0.776079",\ + "2.446671, 2.446674, 2.446680, 2.446683, 2.446690",\ + "0.050112, 0.050112, 0.050112, 0.050111, 0.050111",\ + "0.112175, 0.112175, 0.112175, 0.112175, 0.112174",\ + "0.264098, 0.264098, 0.264098, 0.264098, 0.264098",\ + "0.776079, 0.776079, 0.776079, 0.776079, 0.776079",\ + "2.446671, 2.446674, 2.446680, 2.446683, 2.446690",\ + "0.050112, 0.050112, 0.050112, 0.050111, 0.050111",\ + "0.112175, 0.112175, 0.112175, 0.112175, 0.112174",\ + "0.264098, 0.264098, 0.264098, 0.264098, 0.264098",\ + "0.776079, 0.776079, 0.776079, 0.776079, 0.776079",\ + "2.446671, 2.446674, 2.446680, 2.446683, 2.446690",\ + "0.050112, 0.050112, 0.050112, 0.050111, 0.050111",\ + "0.112175, 0.112175, 0.112175, 0.112175, 0.112174",\ + "0.264098, 0.264098, 0.264098, 0.264098, 0.264098",\ + "0.776079, 0.776079, 0.776079, 0.776079, 0.776079",\ + "2.446671, 2.446675, 2.446680, 2.446683, 2.446690"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.344360, 0.526527, 0.722625, 1.031957, 1.626903",\ + "0.372305, 0.554472, 0.750569, 1.059901, 1.654848",\ + "0.431756, 0.613923, 0.810021, 1.119354, 1.714302",\ + "0.627357, 0.809524, 1.005621, 1.314951, 1.909892",\ + "1.264693, 1.446861, 1.642959, 1.952297, 2.547257",\ + "0.431780, 0.613846, 0.809906, 1.119262, 1.714256",\ + "0.459725, 0.641791, 0.837850, 1.147207, 1.742202",\ + "0.519176, 0.701242, 0.897302, 1.206659, 1.801656",\ + "0.714777, 0.896843, 1.092902, 1.402256, 1.997246",\ + "1.352113, 1.534179, 1.730240, 2.039602, 2.634611",\ + "0.512648, 0.694183, 0.889933, 1.199290, 1.794288",\ + "0.540592, 0.722128, 0.917877, 1.227235, 1.822234",\ + "0.600044, 0.781579, 0.977328, 1.286687, 1.881687",\ + "0.795644, 0.977180, 1.172929, 1.482284, 2.077278",\ + "1.432981, 1.614516, 1.810267, 2.119630, 2.714642",\ + "0.570287, 0.752020, 0.947668, 1.256761, 1.851384",\ + "0.598231, 0.779964, 0.975612, 1.284706, 1.879330",\ + "0.657682, 0.839416, 1.035064, 1.344158, 1.938784",\ + "0.853283, 1.035016, 1.230664, 1.539755, 2.134374",\ + "1.490620, 1.672353, 1.868002, 2.177101, 2.771739",\ + "0.872382, 1.057398, 1.251331, 1.559969, 2.153704",\ + "0.900326, 1.085343, 1.279276, 1.587914, 2.181649",\ + "0.959778, 1.144794, 1.338727, 1.647366, 2.241103",\ + "1.155378, 1.340395, 1.534328, 1.842963, 2.436693",\ + "1.792715, 1.977731, 2.171666, 2.480309, 3.074058"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.040709, 0.040709, 0.040708, 0.040708, 0.040708",\ + "0.082941, 0.082941, 0.082941, 0.082941, 0.082941",\ + "0.186774, 0.186774, 0.186773, 0.186772, 0.186769",\ + "0.543828, 0.543828, 0.543829, 0.543834, 0.543846",\ + "1.713838, 1.713838, 1.713836, 1.713826, 1.713802",\ + "0.040709, 0.040709, 0.040708, 0.040708, 0.040708",\ + "0.082941, 0.082941, 0.082941, 0.082941, 0.082941",\ + "0.186774, 0.186774, 0.186773, 0.186772, 0.186769",\ + "0.543828, 0.543828, 0.543829, 0.543834, 0.543846",\ + "1.713838, 1.713838, 1.713836, 1.713826, 1.713802",\ + "0.040709, 0.040709, 0.040708, 0.040708, 0.040708",\ + "0.082941, 0.082941, 0.082941, 0.082941, 0.082941",\ + "0.186774, 0.186774, 0.186773, 0.186772, 0.186769",\ + "0.543828, 0.543828, 0.543829, 0.543834, 0.543846",\ + "1.713838, 1.713838, 1.713836, 1.713826, 1.713802",\ + "0.040709, 0.040709, 0.040708, 0.040708, 0.040708",\ + "0.082941, 0.082941, 0.082941, 0.082941, 0.082941",\ + "0.186774, 0.186774, 0.186773, 0.186772, 0.186769",\ + "0.543828, 0.543828, 0.543829, 0.543834, 0.543846",\ + "1.713838, 1.713838, 1.713836, 1.713826, 1.713802",\ + "0.040709, 0.040709, 0.040708, 0.040708, 0.040708",\ + "0.082941, 0.082941, 0.082941, 0.082941, 0.082941",\ + "0.186774, 0.186774, 0.186773, 0.186772, 0.186769",\ + "0.543828, 0.543828, 0.543829, 0.543834, 0.543846",\ + "1.713838, 1.713838, 1.713836, 1.713826, 1.713802"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[7]_redg_min_2354*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[3]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.540706, 0.719045, 0.899392, 1.185579, 1.736332",\ + "0.578861, 0.757200, 0.937547, 1.223734, 1.774487",\ + "0.661288, 0.839627, 1.019974, 1.306160, 1.856914",\ + "0.932446, 1.110786, 1.291132, 1.577319, 2.128072",\ + "1.818332, 1.996672, 2.177019, 2.463205, 3.013958",\ + "0.625644, 0.803881, 0.984462, 1.271085, 1.822710",\ + "0.663799, 0.842036, 1.022617, 1.309240, 1.860865",\ + "0.746226, 0.924463, 1.105044, 1.391667, 1.943292",\ + "1.017385, 1.195621, 1.376203, 1.662825, 2.214450",\ + "1.903271, 2.081508, 2.262089, 2.548712, 3.100337",\ + "0.701550, 0.879325, 1.059271, 1.345682, 1.896883",\ + "0.739705, 0.917479, 1.097426, 1.383837, 1.935037",\ + "0.822132, 0.999906, 1.179853, 1.466263, 2.017464",\ + "1.093291, 1.271065, 1.451011, 1.737422, 2.288623",\ + "1.979177, 2.156951, 2.336898, 2.623308, 3.174509",\ + "0.755902, 0.934070, 1.114136, 1.400275, 1.951200",\ + "0.794057, 0.972225, 1.152291, 1.438430, 1.989355",\ + "0.876484, 1.054652, 1.234718, 1.520857, 2.071782",\ + "1.147643, 1.325810, 1.505877, 1.792016, 2.342940",\ + "2.033529, 2.211697, 2.391763, 2.677902, 3.228827",\ + "1.037324, 1.219587, 1.398289, 1.684002, 2.234478",\ + "1.075479, 1.257742, 1.436444, 1.722157, 2.272632",\ + "1.157906, 1.340169, 1.518871, 1.804583, 2.355059",\ + "1.429065, 1.611328, 1.790030, 2.075742, 2.626218",\ + "2.314951, 2.497214, 2.675916, 2.961628, 3.512104"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.050112, 0.050112, 0.050112, 0.050112, 0.050112",\ + "0.112175, 0.112175, 0.112175, 0.112175, 0.112175",\ + "0.264098, 0.264098, 0.264098, 0.264098, 0.264098",\ + "0.776079, 0.776079, 0.776079, 0.776079, 0.776079",\ + "2.446671, 2.446671, 2.446671, 2.446671, 2.446673",\ + "0.050112, 0.050112, 0.050112, 0.050112, 0.050112",\ + "0.112175, 0.112175, 0.112175, 0.112175, 0.112175",\ + "0.264098, 0.264098, 0.264098, 0.264098, 0.264098",\ + "0.776079, 0.776079, 0.776079, 0.776079, 0.776079",\ + "2.446671, 2.446671, 2.446671, 2.446671, 2.446673",\ + "0.050112, 0.050112, 0.050112, 0.050112, 0.050112",\ + "0.112175, 0.112175, 0.112175, 0.112175, 0.112175",\ + "0.264098, 0.264098, 0.264098, 0.264098, 0.264098",\ + "0.776079, 0.776079, 0.776079, 0.776079, 0.776079",\ + "2.446671, 2.446671, 2.446671, 2.446671, 2.446673",\ + "0.050112, 0.050112, 0.050112, 0.050112, 0.050112",\ + "0.112175, 0.112175, 0.112175, 0.112175, 0.112175",\ + "0.264098, 0.264098, 0.264098, 0.264098, 0.264098",\ + "0.776079, 0.776079, 0.776079, 0.776079, 0.776079",\ + "2.446671, 2.446671, 2.446671, 2.446671, 2.446673",\ + "0.050112, 0.050112, 0.050112, 0.050112, 0.050112",\ + "0.112175, 0.112175, 0.112175, 0.112175, 0.112175",\ + "0.264098, 0.264098, 0.264098, 0.264098, 0.264098",\ + "0.776079, 0.776079, 0.776079, 0.776079, 0.776079",\ + "2.446671, 2.446671, 2.446671, 2.446671, 2.446673"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.361633, 0.626632, 0.885661, 1.321925, 2.194071",\ + "0.389577, 0.654577, 0.913606, 1.349870, 2.222015",\ + "0.449029, 0.714028, 0.973057, 1.409321, 2.281467",\ + "0.644629, 0.909628, 1.168658, 1.604922, 2.477067",\ + "1.281966, 1.546965, 1.805995, 2.242259, 3.114405",\ + "0.450298, 0.714707, 0.974302, 1.410154, 2.281476",\ + "0.478243, 0.742651, 1.002247, 1.438099, 2.309421",\ + "0.537694, 0.802103, 1.061698, 1.497550, 2.368872",\ + "0.733295, 0.997703, 1.257299, 1.693150, 2.564472",\ + "1.370631, 1.635040, 1.894635, 2.330488, 3.201810",\ + "0.543105, 0.808000, 1.066338, 1.502398, 2.374518",\ + "0.571050, 0.835945, 1.094282, 1.530342, 2.402462",\ + "0.630501, 0.895396, 1.153733, 1.589793, 2.461914",\ + "0.826102, 1.090997, 1.349334, 1.785394, 2.657514",\ + "1.463438, 1.728334, 1.986671, 2.422731, 3.294852",\ + "0.608828, 0.876535, 1.133393, 1.569404, 2.441428",\ + "0.636772, 0.904479, 1.161337, 1.597349, 2.469372",\ + "0.696223, 0.963930, 1.220788, 1.656800, 2.528824",\ + "0.891824, 1.159531, 1.416389, 1.852400, 2.724424",\ + "1.529161, 1.796868, 2.053726, 2.489738, 3.361762",\ + "0.954617, 1.257033, 1.504031, 1.938605, 2.807755",\ + "0.982561, 1.284978, 1.531975, 1.966550, 2.835699",\ + "1.042013, 1.344429, 1.591426, 2.026001, 2.895151",\ + "1.237613, 1.540030, 1.787027, 2.221601, 3.090751",\ + "1.874950, 2.177366, 2.424364, 2.858939, 3.728089"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.040709, 0.040709, 0.040709, 0.040709, 0.040708",\ + "0.082941, 0.082941, 0.082941, 0.082941, 0.082941",\ + "0.186774, 0.186774, 0.186774, 0.186774, 0.186773",\ + "0.543828, 0.543828, 0.543828, 0.543829, 0.543829",\ + "1.713838, 1.713838, 1.713838, 1.713837, 1.713836",\ + "0.040709, 0.040709, 0.040709, 0.040709, 0.040708",\ + "0.082941, 0.082941, 0.082941, 0.082941, 0.082941",\ + "0.186774, 0.186774, 0.186774, 0.186774, 0.186773",\ + "0.543828, 0.543828, 0.543828, 0.543829, 0.543829",\ + "1.713838, 1.713838, 1.713838, 1.713837, 1.713836",\ + "0.040709, 0.040709, 0.040709, 0.040709, 0.040708",\ + "0.082941, 0.082941, 0.082941, 0.082941, 0.082941",\ + "0.186774, 0.186774, 0.186774, 0.186774, 0.186773",\ + "0.543828, 0.543828, 0.543828, 0.543829, 0.543829",\ + "1.713838, 1.713838, 1.713838, 1.713837, 1.713836",\ + "0.040709, 0.040709, 0.040709, 0.040709, 0.040708",\ + "0.082941, 0.082941, 0.082941, 0.082941, 0.082941",\ + "0.186774, 0.186774, 0.186774, 0.186774, 0.186773",\ + "0.543828, 0.543828, 0.543828, 0.543829, 0.543829",\ + "1.713838, 1.713838, 1.713838, 1.713837, 1.713836",\ + "0.040709, 0.040709, 0.040709, 0.040709, 0.040708",\ + "0.082941, 0.082941, 0.082941, 0.082941, 0.082941",\ + "0.186774, 0.186774, 0.186774, 0.186774, 0.186773",\ + "0.543828, 0.543828, 0.543828, 0.543829, 0.543829",\ + "1.713838, 1.713838, 1.713838, 1.713837, 1.713836"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[7]_redg_min_2300*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + values ( "0.138985, 0.175019, 0.256111, 0.526543, 1.410212",\ + "0.227168, 0.263197, 0.344286, 0.614601, 1.498111",\ + "0.315465, 0.351510, 0.432605, 0.702794, 1.585954",\ + "0.378070, 0.414099, 0.495228, 0.765687, 1.648712",\ + "0.707467, 0.743520, 0.824710, 1.095700, 1.978611"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + values ( "0.049671, 0.111941, 0.264026, 0.776079, 2.446670",\ + "0.049671, 0.111941, 0.264026, 0.776079, 2.446670",\ + "0.049671, 0.111941, 0.264026, 0.776079, 2.446670",\ + "0.049683, 0.111941, 0.264026, 0.776079, 2.446670",\ + "0.050112, 0.112175, 0.264026, 0.776079, 2.446670"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + values ( "0.157324, 0.185053, 0.244293, 0.439369, 1.077476",\ + "0.244729, 0.272457, 0.331698, 0.526774, 1.164879",\ + "0.325583, 0.353311, 0.412545, 0.607616, 1.245783",\ + "0.383167, 0.410894, 0.470117, 0.665176, 1.303456",\ + "0.684927, 0.712665, 0.771862, 0.966921, 1.606322"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + values ( "0.040467, 0.082696, 0.186546, 0.543770, 1.713948",\ + "0.040467, 0.082696, 0.186546, 0.543770, 1.713948",\ + "0.040467, 0.082696, 0.186546, 0.543770, 1.713916",\ + "0.040467, 0.082696, 0.186546, 0.543770, 1.713853",\ + "0.040452, 0.082696, 0.186546, 0.543770, 1.713838"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[7]_redg_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + values ( "380001.750000, 380001.781250, 380001.875000, 380002.125000, 380003.031250",\ + "380001.843750, 380001.875000, 380001.968750, 380002.218750, 380003.125000",\ + "380001.937500, 380001.968750, 380002.062500, 380002.312500, 380003.218750",\ + "380002.093750, 380002.125000, 380002.218750, 380002.468750, 380003.375000",\ + "380002.343750, 380002.375000, 380002.468750, 380002.718750, 380003.625000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + values ( "0.060263, 0.120010, 0.268885, 0.784134, 2.468360",\ + "0.060263, 0.120010, 0.268885, 0.784134, 2.468360",\ + "0.060263, 0.120010, 0.268885, 0.784134, 2.468360",\ + "0.060263, 0.120010, 0.268885, 0.784134, 2.468360",\ + "0.060263, 0.120010, 0.268885, 0.784134, 2.468360"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + values ( "380003.812500, 380003.843750, 380003.906250, 380004.093750, 380004.750000",\ + "380003.906250, 380003.937500, 380004.000000, 380004.187500, 380004.843750",\ + "380004.031250, 380004.062500, 380004.125000, 380004.312500, 380004.968750",\ + "380004.218750, 380004.250000, 380004.312500, 380004.500000, 380005.156250",\ + "380004.531250, 380004.562500, 380004.625000, 380004.812500, 380005.468750"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + values ( "0.050461, 0.092299, 0.192599, 0.548730, 1.719198",\ + "0.050461, 0.092299, 0.192599, 0.548730, 1.719198",\ + "0.050461, 0.092299, 0.192599, 0.548730, 1.719198",\ + "0.050461, 0.092299, 0.192599, 0.548730, 1.719198",\ + "0.050461, 0.092299, 0.192599, 0.548730, 1.719198"); + } + + } /* end of arc padmux2ast_i[4]_obs_ctrl_o[7]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + values ( "380001.718750, 380001.781250, 380001.843750, 380002.125000, 380003.000000",\ + "380001.812500, 380001.875000, 380001.937500, 380002.218750, 380003.093750",\ + "380001.875000, 380001.937500, 380002.000000, 380002.281250, 380003.156250",\ + "380002.031250, 380002.093750, 380002.156250, 380002.437500, 380003.312500",\ + "380002.250000, 380002.312500, 380002.375000, 380002.656250, 380003.531250"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + values ( "0.057179, 0.117947, 0.268265, 0.782312, 2.467599",\ + "0.057179, 0.117947, 0.268265, 0.782312, 2.467599",\ + "0.057179, 0.117947, 0.268265, 0.782312, 2.467599",\ + "0.057179, 0.117947, 0.268265, 0.782312, 2.467599",\ + "0.057179, 0.117947, 0.268265, 0.782312, 2.467599"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + values ( "380003.781250, 380003.812500, 380003.875000, 380004.062500, 380004.718750",\ + "380003.875000, 380003.906250, 380003.968750, 380004.156250, 380004.812500",\ + "380003.968750, 380004.000000, 380004.062500, 380004.250000, 380004.906250",\ + "380004.156250, 380004.187500, 380004.250000, 380004.437500, 380005.093750",\ + "380004.406250, 380004.437500, 380004.500000, 380004.687500, 380005.343750"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + values ( "0.044680, 0.086652, 0.188447, 0.546028, 1.713947",\ + "0.044680, 0.086652, 0.188447, 0.546028, 1.713947",\ + "0.044680, 0.086652, 0.188447, 0.546028, 1.713947",\ + "0.044680, 0.086652, 0.188447, 0.546028, 1.713947",\ + "0.044680, 0.086652, 0.188447, 0.546028, 1.713947"); + } + + } /* end of arc padmux2ast_i[4]_obs_ctrl_o[7]_una_min*/ + + timing () { + related_pin : "padmux2ast_i[7]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + values ( "0.138119, 0.177193, 0.260095, 0.531430, 1.418639",\ + "0.215767, 0.254860, 0.337696, 0.608981, 1.495289",\ + "0.308294, 0.348212, 0.431364, 0.702849, 1.589224",\ + "0.484710, 0.527128, 0.611576, 0.883003, 1.767226",\ + "0.797982, 0.847958, 0.937201, 1.208546, 2.091260"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + values ( "0.060518, 0.120076, 0.268511, 0.784628, 2.471116",\ + "0.060518, 0.120081, 0.268991, 0.784628, 2.471116",\ + "0.064343, 0.122204, 0.269307, 0.784628, 2.471116",\ + "0.074832, 0.129870, 0.272085, 0.785309, 2.471116",\ + "0.105095, 0.152930, 0.282207, 0.790964, 2.471949"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + values ( "0.152585, 0.183883, 0.246071, 0.443151, 1.081549",\ + "0.241411, 0.272612, 0.334887, 0.531878, 1.170082",\ + "0.351515, 0.383367, 0.445997, 0.642143, 1.279910",\ + "0.559588, 0.595140, 0.660416, 0.857529, 1.494932",\ + "0.931509, 0.975339, 1.048816, 1.248062, 1.886353"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + values ( "0.051005, 0.093001, 0.193536, 0.550167, 1.721145",\ + "0.051005, 0.093079, 0.193536, 0.550167, 1.721145",\ + "0.053874, 0.094487, 0.193931, 0.550167, 1.721145",\ + "0.067061, 0.106340, 0.200874, 0.550167, 1.721145",\ + "0.100525, 0.137944, 0.221526, 0.555674, 1.721145"); + } + + } /* end of arc padmux2ast_i[7]_obs_ctrl_o[7]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[7]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + values ( "0.132088, 0.170250, 0.252738, 0.523558, 1.410267",\ + "0.209647, 0.247859, 0.330344, 0.601532, 1.487547",\ + "0.301602, 0.340448, 0.423118, 0.694391, 1.578063",\ + "0.475914, 0.516815, 0.600289, 0.871567, 1.757498",\ + "0.784086, 0.831711, 0.918475, 1.188577, 2.072675"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + values ( "0.057008, 0.117873, 0.266652, 0.780708, 2.463387",\ + "0.057108, 0.118176, 0.268442, 0.782366, 2.463387",\ + "0.060610, 0.120100, 0.268442, 0.782366, 2.463387",\ + "0.069995, 0.126826, 0.271258, 0.783468, 2.466000",\ + "0.096521, 0.148240, 0.280183, 0.788214, 2.471217"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + values ( "0.124161, 0.153974, 0.214961, 0.411830, 1.047717",\ + "0.215312, 0.245079, 0.306058, 0.501475, 1.140252",\ + "0.327970, 0.358765, 0.420242, 0.616480, 1.254494",\ + "0.533590, 0.569301, 0.634108, 0.830328, 1.467817",\ + "0.890972, 0.936721, 1.011690, 1.210135, 1.847934"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + values ( "0.045487, 0.087234, 0.188597, 0.544901, 1.712083",\ + "0.045487, 0.087327, 0.189348, 0.546097, 1.714089",\ + "0.050060, 0.090091, 0.189686, 0.546097, 1.714380",\ + "0.065339, 0.103967, 0.197580, 0.546097, 1.714380",\ + "0.095856, 0.132931, 0.220241, 0.552890, 1.714380"); + } + + } /* end of arc padmux2ast_i[7]_obs_ctrl_o[7]_una_min*/ + +} /* end of pin obs_ctrl_o[7] */ + +pin("obs_ctrl_o[6]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.156168 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000997 ; + + /* Other user defined attributes. */ + original_pin : obs_ctrl_o[6]; + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[0]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.556254, 0.736457, 0.923947, 1.225939, 1.809451",\ + "0.586838, 0.767041, 0.954531, 1.256524, 1.840036",\ + "0.658665, 0.838868, 1.026358, 1.328351, 1.911863",\ + "0.915124, 1.095327, 1.282817, 1.584810, 2.168322",\ + "1.830892, 2.011095, 2.198585, 2.500578, 3.084090",\ + "0.641192, 0.821740, 1.009955, 1.311951, 1.895829",\ + "0.671777, 0.852324, 1.040540, 1.342536, 1.926414",\ + "0.743604, 0.924151, 1.112367, 1.414363, 1.998241",\ + "1.000063, 1.180610, 1.368826, 1.670822, 2.254700",\ + "1.915831, 2.096378, 2.284594, 2.586590, 3.170468",\ + "0.717104, 0.897183, 1.084764, 1.386548, 1.970002",\ + "0.747689, 0.927768, 1.115349, 1.417133, 2.000586",\ + "0.819516, 0.999595, 1.187176, 1.488960, 2.072413",\ + "1.075975, 1.256054, 1.443635, 1.745419, 2.328872",\ + "1.991743, 2.171822, 2.359403, 2.661187, 3.244641",\ + "0.771473, 0.951695, 1.139415, 1.441088, 2.024319",\ + "0.802058, 0.982279, 1.170000, 1.471673, 2.054904",\ + "0.873885, 1.054106, 1.241827, 1.543499, 2.126730",\ + "1.130344, 1.310565, 1.498286, 1.799959, 2.383190",\ + "2.046112, 2.226333, 2.414054, 2.715727, 3.298958",\ + "1.053068, 1.236963, 1.423366, 1.724814, 2.307597",\ + "1.083653, 1.267547, 1.453950, 1.755399, 2.338181",\ + "1.155480, 1.339374, 1.525777, 1.827226, 2.410008",\ + "1.411939, 1.595834, 1.782236, 2.083685, 2.666467",\ + "2.327707, 2.511601, 2.698004, 2.999453, 3.582235"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.040152, 0.040152, 0.040152, 0.040152, 0.040152",\ + "0.086136, 0.086136, 0.086136, 0.086136, 0.086136",\ + "0.217337, 0.217337, 0.217337, 0.217337, 0.217336",\ + "0.715483, 0.715483, 0.715483, 0.715483, 0.715483",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.040152, 0.040152, 0.040152, 0.040152, 0.040152",\ + "0.086136, 0.086136, 0.086136, 0.086136, 0.086136",\ + "0.217337, 0.217337, 0.217337, 0.217337, 0.217336",\ + "0.715483, 0.715483, 0.715483, 0.715483, 0.715483",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.040152, 0.040152, 0.040152, 0.040152, 0.040152",\ + "0.086136, 0.086136, 0.086136, 0.086136, 0.086136",\ + "0.217337, 0.217337, 0.217337, 0.217337, 0.217336",\ + "0.715483, 0.715483, 0.715483, 0.715483, 0.715483",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.040152, 0.040152, 0.040152, 0.040152, 0.040152",\ + "0.086136, 0.086136, 0.086136, 0.086136, 0.086136",\ + "0.217337, 0.217337, 0.217337, 0.217337, 0.217336",\ + "0.715483, 0.715483, 0.715483, 0.715483, 0.715483",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.040152, 0.040152, 0.040152, 0.040152, 0.040152",\ + "0.086136, 0.086136, 0.086136, 0.086136, 0.086136",\ + "0.217337, 0.217337, 0.217337, 0.217337, 0.217336",\ + "0.715483, 0.715483, 0.715483, 0.715483, 0.715483",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.426883, 0.694669, 0.956249, 1.395946, 2.275341",\ + "0.452678, 0.720463, 0.982044, 1.421741, 2.301136",\ + "0.504089, 0.771875, 1.033455, 1.473152, 2.352547",\ + "0.670899, 0.938685, 1.200265, 1.639962, 2.519357",\ + "1.261153, 1.528939, 1.790519, 2.230216, 3.109611",\ + "0.515587, 0.782744, 1.044890, 1.484175, 2.362746",\ + "0.541382, 0.808538, 1.070684, 1.509970, 2.388541",\ + "0.592793, 0.859950, 1.122096, 1.561381, 2.439952",\ + "0.759603, 1.026760, 1.288906, 1.728191, 2.606762",\ + "1.349858, 1.617014, 1.879160, 2.318445, 3.197016",\ + "0.608530, 0.875889, 1.136616, 1.576339, 2.455788",\ + "0.634324, 0.901683, 1.162410, 1.602134, 2.481582",\ + "0.685735, 0.953095, 1.213821, 1.653545, 2.532994",\ + "0.852545, 1.119905, 1.380631, 1.820355, 2.699804",\ + "1.442800, 1.710159, 1.970885, 2.410609, 3.290058",\ + "0.674373, 0.944453, 1.203635, 1.643190, 2.522299",\ + "0.700168, 0.970248, 1.229430, 1.668984, 2.548094",\ + "0.751579, 1.021659, 1.280841, 1.720395, 2.599505",\ + "0.918389, 1.188469, 1.447651, 1.887205, 2.766315",\ + "1.508643, 1.778723, 2.037905, 2.477460, 3.356569",\ + "1.020895, 1.325289, 1.574298, 2.012344, 2.888435",\ + "1.046689, 1.351083, 1.600093, 2.038138, 2.914229",\ + "1.098100, 1.402495, 1.651504, 2.089549, 2.965641",\ + "1.264910, 1.569304, 1.818314, 2.256359, 3.132450",\ + "1.855165, 2.159559, 2.408568, 2.846614, 3.722705"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.040587, 0.040587, 0.040587, 0.040587, 0.040587",\ + "0.069933, 0.069933, 0.069933, 0.069933, 0.069933",\ + "0.145759, 0.145759, 0.145759, 0.145759, 0.145759",\ + "0.443908, 0.443908, 0.443908, 0.443908, 0.443908",\ + "1.523853, 1.523853, 1.523853, 1.523852, 1.523852",\ + "0.040587, 0.040587, 0.040587, 0.040587, 0.040587",\ + "0.069933, 0.069933, 0.069933, 0.069933, 0.069933",\ + "0.145759, 0.145759, 0.145759, 0.145759, 0.145759",\ + "0.443908, 0.443908, 0.443908, 0.443908, 0.443908",\ + "1.523853, 1.523853, 1.523853, 1.523852, 1.523852",\ + "0.040587, 0.040587, 0.040587, 0.040587, 0.040587",\ + "0.069933, 0.069933, 0.069933, 0.069933, 0.069933",\ + "0.145759, 0.145759, 0.145759, 0.145759, 0.145759",\ + "0.443908, 0.443908, 0.443908, 0.443908, 0.443908",\ + "1.523853, 1.523853, 1.523853, 1.523852, 1.523852",\ + "0.040587, 0.040587, 0.040587, 0.040587, 0.040587",\ + "0.069933, 0.069933, 0.069933, 0.069933, 0.069933",\ + "0.145759, 0.145759, 0.145759, 0.145759, 0.145759",\ + "0.443908, 0.443908, 0.443908, 0.443908, 0.443908",\ + "1.523853, 1.523853, 1.523853, 1.523852, 1.523852",\ + "0.040587, 0.040587, 0.040587, 0.040587, 0.040587",\ + "0.069933, 0.069933, 0.069933, 0.069933, 0.069933",\ + "0.145759, 0.145759, 0.145759, 0.145759, 0.145759",\ + "0.443908, 0.443908, 0.443908, 0.443908, 0.443908",\ + "1.523853, 1.523853, 1.523853, 1.523852, 1.523852"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[6]_redg_2739*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[1]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.464359, 0.727932, 1.004205, 1.472935, 2.410394",\ + "0.494943, 0.758517, 1.034790, 1.503519, 2.440979",\ + "0.566770, 0.830344, 1.106616, 1.575346, 2.512805",\ + "0.823229, 1.086803, 1.363075, 1.831805, 2.769264",\ + "1.738998, 2.002571, 2.278845, 2.747575, 3.685036",\ + "0.552553, 0.815473, 1.091773, 1.559650, 2.496328",\ + "0.583138, 0.846058, 1.122357, 1.590235, 2.526912",\ + "0.654965, 0.917885, 1.194184, 1.662061, 2.598739",\ + "0.911424, 1.174344, 1.450643, 1.918520, 2.855197",\ + "1.827192, 2.090112, 2.366412, 2.834290, 3.770969",\ + "0.640869, 0.904454, 1.179738, 1.647273, 2.583283",\ + "0.671454, 0.935038, 1.210322, 1.677857, 2.613867",\ + "0.743281, 1.006865, 1.282149, 1.749684, 2.685694",\ + "0.999740, 1.263324, 1.538608, 2.006143, 2.942153",\ + "1.915508, 2.179093, 2.454377, 2.921913, 3.857924",\ + "0.703365, 0.970089, 1.243877, 1.711186, 2.646792",\ + "0.733950, 1.000673, 1.274462, 1.741771, 2.677376",\ + "0.805777, 1.072500, 1.346289, 1.813598, 2.749203",\ + "1.062236, 1.328959, 1.602748, 2.070056, 3.005661",\ + "1.978004, 2.244728, 2.518517, 2.985826, 3.921433",\ + "1.032491, 1.334419, 1.595745, 2.060536, 2.992248",\ + "1.063076, 1.365004, 1.626329, 2.091120, 3.022832",\ + "1.134902, 1.436831, 1.698156, 2.162947, 3.094659",\ + "1.391361, 1.693290, 1.954615, 2.419406, 3.351118",\ + "2.307130, 2.609058, 2.870384, 3.335176, 4.266890"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.040152, 0.040152, 0.040152, 0.040152, 0.040151",\ + "0.086136, 0.086136, 0.086136, 0.086136, 0.086136",\ + "0.217337, 0.217336, 0.217336, 0.217336, 0.217335",\ + "0.715483, 0.715483, 0.715482, 0.715478, 0.715471",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.040152, 0.040152, 0.040152, 0.040152, 0.040151",\ + "0.086136, 0.086136, 0.086136, 0.086136, 0.086136",\ + "0.217337, 0.217336, 0.217336, 0.217336, 0.217335",\ + "0.715483, 0.715483, 0.715481, 0.715478, 0.715471",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.040152, 0.040152, 0.040152, 0.040152, 0.040151",\ + "0.086136, 0.086136, 0.086136, 0.086136, 0.086136",\ + "0.217337, 0.217336, 0.217336, 0.217336, 0.217335",\ + "0.715483, 0.715483, 0.715481, 0.715478, 0.715471",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.040152, 0.040152, 0.040152, 0.040152, 0.040151",\ + "0.086136, 0.086136, 0.086136, 0.086136, 0.086136",\ + "0.217337, 0.217336, 0.217336, 0.217336, 0.217335",\ + "0.715483, 0.715483, 0.715481, 0.715478, 0.715471",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.040152, 0.040152, 0.040152, 0.040152, 0.040151",\ + "0.086136, 0.086136, 0.086136, 0.086136, 0.086136",\ + "0.217337, 0.217336, 0.217336, 0.217336, 0.217335",\ + "0.715483, 0.715483, 0.715481, 0.715478, 0.715471",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.409837, 0.592268, 0.788660, 1.097713, 1.692519",\ + "0.435631, 0.618063, 0.814455, 1.123508, 1.718315",\ + "0.487042, 0.669474, 0.865866, 1.174919, 1.769726",\ + "0.653852, 0.836284, 1.032676, 1.341729, 1.936536",\ + "1.244107, 1.426538, 1.622930, 1.931983, 2.526791",\ + "0.497251, 0.679654, 0.876154, 1.185018, 1.779872",\ + "0.523046, 0.705448, 0.901948, 1.210813, 1.805669",\ + "0.574457, 0.756860, 0.953359, 1.262224, 1.857080",\ + "0.741267, 0.923669, 1.120169, 1.429034, 2.023889",\ + "1.331521, 1.513924, 1.710423, 2.019289, 2.614144",\ + "0.578128, 0.759990, 0.956180, 1.265047, 1.859904",\ + "0.603922, 0.785785, 0.981975, 1.290841, 1.885700",\ + "0.655333, 0.837196, 1.033386, 1.342253, 1.937111",\ + "0.822143, 1.004006, 1.200196, 1.509062, 2.103921",\ + "1.412398, 1.594260, 1.790450, 2.099317, 2.694176",\ + "0.635774, 0.817539, 1.013724, 1.322292, 1.916552",\ + "0.661568, 0.843333, 1.039518, 1.348086, 1.942348",\ + "0.712980, 0.894745, 1.090930, 1.399498, 1.993759",\ + "0.879789, 1.061554, 1.257740, 1.566308, 2.160568",\ + "1.470044, 1.651809, 1.847994, 2.156562, 2.750823",\ + "0.937982, 1.122763, 1.317358, 1.625306, 2.218398",\ + "0.963776, 1.148558, 1.343152, 1.651101, 2.244195",\ + "1.015187, 1.199969, 1.394563, 1.702512, 2.295605",\ + "1.181997, 1.366779, 1.561373, 1.869322, 2.462415",\ + "1.772252, 1.957033, 2.151628, 2.459577, 3.052670"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.040587, 0.040587, 0.040587, 0.040588, 0.040588",\ + "0.069933, 0.069933, 0.069933, 0.069933, 0.069933",\ + "0.145759, 0.145759, 0.145759, 0.145759, 0.145760",\ + "0.443908, 0.443908, 0.443908, 0.443908, 0.443908",\ + "1.523853, 1.523853, 1.523853, 1.523854, 1.523857",\ + "0.040587, 0.040587, 0.040587, 0.040588, 0.040588",\ + "0.069933, 0.069933, 0.069933, 0.069933, 0.069933",\ + "0.145759, 0.145759, 0.145759, 0.145759, 0.145760",\ + "0.443908, 0.443908, 0.443908, 0.443908, 0.443908",\ + "1.523853, 1.523853, 1.523853, 1.523854, 1.523857",\ + "0.040587, 0.040587, 0.040587, 0.040588, 0.040588",\ + "0.069933, 0.069933, 0.069933, 0.069933, 0.069933",\ + "0.145759, 0.145759, 0.145759, 0.145759, 0.145760",\ + "0.443908, 0.443908, 0.443908, 0.443908, 0.443908",\ + "1.523853, 1.523853, 1.523853, 1.523854, 1.523857",\ + "0.040587, 0.040587, 0.040587, 0.040588, 0.040588",\ + "0.069933, 0.069933, 0.069933, 0.069933, 0.069933",\ + "0.145759, 0.145759, 0.145759, 0.145759, 0.145760",\ + "0.443908, 0.443908, 0.443908, 0.443908, 0.443908",\ + "1.523853, 1.523853, 1.523853, 1.523854, 1.523857",\ + "0.040587, 0.040587, 0.040587, 0.040588, 0.040588",\ + "0.069933, 0.069933, 0.069933, 0.069933, 0.069933",\ + "0.145759, 0.145759, 0.145759, 0.145759, 0.145760",\ + "0.443908, 0.443908, 0.443908, 0.443908, 0.443908",\ + "1.523853, 1.523853, 1.523853, 1.523854, 1.523857"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[6]_redg_2665*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[2]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.460384, 0.720013, 0.991885, 1.448765, 2.362525",\ + "0.490968, 0.750597, 1.022470, 1.479349, 2.393109",\ + "0.562795, 0.822424, 1.094296, 1.551176, 2.464936",\ + "0.819254, 1.078883, 1.350755, 1.807635, 2.721394",\ + "1.735022, 1.994652, 2.266525, 2.723405, 3.637166",\ + "0.548488, 0.807546, 1.079415, 1.535480, 2.448458",\ + "0.579073, 0.838131, 1.110000, 1.566065, 2.479043",\ + "0.650900, 0.909958, 1.181827, 1.637892, 2.550869",\ + "0.907359, 1.166417, 1.438286, 1.894350, 2.807328",\ + "1.823127, 2.082186, 2.354055, 2.810120, 3.723099",\ + "0.636518, 0.896512, 1.167380, 1.623103, 2.535413",\ + "0.667103, 0.927097, 1.197964, 1.653687, 2.565998",\ + "0.738930, 0.998924, 1.269791, 1.725514, 2.637825",\ + "0.995389, 1.255383, 1.526250, 1.981973, 2.894283",\ + "1.911157, 2.171151, 2.442019, 2.897743, 3.810054",\ + "0.698740, 0.962126, 1.231518, 1.687016, 2.598922",\ + "0.729324, 0.992710, 1.262102, 1.717601, 2.629507",\ + "0.801151, 1.064537, 1.333929, 1.789428, 2.701334",\ + "1.057610, 1.320996, 1.590388, 2.045887, 2.957792",\ + "1.973378, 2.236765, 2.506157, 2.961657, 3.873563",\ + "1.026127, 1.326200, 1.583265, 2.036317, 2.944378",\ + "1.056712, 1.356785, 1.613849, 2.066902, 2.974963",\ + "1.128539, 1.428612, 1.685676, 2.138729, 3.046790",\ + "1.384998, 1.685071, 1.942135, 2.395187, 3.303248",\ + "2.300766, 2.600840, 2.857905, 3.310958, 4.219019"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.040152, 0.040152, 0.040152, 0.040152, 0.040151",\ + "0.086136, 0.086136, 0.086136, 0.086136, 0.086136",\ + "0.217337, 0.217336, 0.217336, 0.217336, 0.217336",\ + "0.715483, 0.715483, 0.715480, 0.715474, 0.715462",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.040152, 0.040152, 0.040152, 0.040152, 0.040151",\ + "0.086136, 0.086136, 0.086136, 0.086136, 0.086136",\ + "0.217337, 0.217336, 0.217336, 0.217336, 0.217336",\ + "0.715483, 0.715483, 0.715480, 0.715474, 0.715462",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.040152, 0.040152, 0.040152, 0.040152, 0.040151",\ + "0.086136, 0.086136, 0.086136, 0.086136, 0.086136",\ + "0.217337, 0.217336, 0.217336, 0.217336, 0.217336",\ + "0.715483, 0.715483, 0.715480, 0.715474, 0.715462",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.040152, 0.040152, 0.040152, 0.040152, 0.040151",\ + "0.086136, 0.086136, 0.086136, 0.086136, 0.086136",\ + "0.217337, 0.217336, 0.217336, 0.217336, 0.217336",\ + "0.715483, 0.715483, 0.715480, 0.715474, 0.715462",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.040152, 0.040152, 0.040152, 0.040152, 0.040151",\ + "0.086136, 0.086136, 0.086136, 0.086136, 0.086136",\ + "0.217337, 0.217336, 0.217336, 0.217336, 0.217336",\ + "0.715483, 0.715483, 0.715480, 0.715474, 0.715462",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.408175, 0.590716, 0.786971, 1.096187, 1.691482",\ + "0.433969, 0.616510, 0.812765, 1.121982, 1.717278",\ + "0.485381, 0.667922, 0.864176, 1.173393, 1.768689",\ + "0.652191, 0.834732, 1.030986, 1.340203, 1.935498",\ + "1.242445, 1.424986, 1.621241, 1.930458, 2.525753",\ + "0.495595, 0.678101, 0.874464, 1.183492, 1.778835",\ + "0.521389, 0.703896, 0.900258, 1.209287, 1.804631",\ + "0.572801, 0.755307, 0.951669, 1.260698, 1.856043",\ + "0.739611, 0.922117, 1.118479, 1.427508, 2.022852",\ + "1.329865, 1.512371, 1.708734, 2.017763, 2.613107",\ + "0.576463, 0.758438, 0.954491, 1.263521, 1.858867",\ + "0.602257, 0.784232, 0.980285, 1.289316, 1.884663",\ + "0.653668, 0.835644, 1.031696, 1.340727, 1.936074",\ + "0.820478, 1.002454, 1.198506, 1.507537, 2.102884",\ + "1.410733, 1.592708, 1.788760, 2.097791, 2.693139",\ + "0.634101, 0.815987, 1.012035, 1.320766, 1.915514",\ + "0.659896, 0.841781, 1.037829, 1.346561, 1.941311",\ + "0.711307, 0.893192, 1.089240, 1.397972, 1.992722",\ + "0.878117, 1.060002, 1.256050, 1.564782, 2.159531",\ + "1.468371, 1.650257, 1.846304, 2.155036, 2.749786",\ + "0.936197, 1.121213, 1.315669, 1.623781, 2.217361",\ + "0.961991, 1.147007, 1.341463, 1.649576, 2.243157",\ + "1.013402, 1.198419, 1.392874, 1.700987, 2.294569",\ + "1.180212, 1.365229, 1.559684, 1.867797, 2.461378",\ + "1.770467, 1.955483, 2.149939, 2.458051, 3.051633"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.040587, 0.040587, 0.040587, 0.040588, 0.040588",\ + "0.069933, 0.069933, 0.069933, 0.069933, 0.069933",\ + "0.145759, 0.145759, 0.145759, 0.145759, 0.145760",\ + "0.443908, 0.443908, 0.443908, 0.443908, 0.443908",\ + "1.523853, 1.523853, 1.523853, 1.523854, 1.523858",\ + "0.040587, 0.040587, 0.040587, 0.040588, 0.040588",\ + "0.069933, 0.069933, 0.069933, 0.069933, 0.069933",\ + "0.145759, 0.145759, 0.145759, 0.145759, 0.145760",\ + "0.443908, 0.443908, 0.443908, 0.443908, 0.443908",\ + "1.523853, 1.523853, 1.523853, 1.523854, 1.523858",\ + "0.040587, 0.040587, 0.040587, 0.040588, 0.040588",\ + "0.069933, 0.069933, 0.069933, 0.069933, 0.069933",\ + "0.145759, 0.145759, 0.145759, 0.145759, 0.145760",\ + "0.443908, 0.443908, 0.443908, 0.443908, 0.443908",\ + "1.523853, 1.523853, 1.523853, 1.523854, 1.523858",\ + "0.040587, 0.040587, 0.040587, 0.040588, 0.040588",\ + "0.069933, 0.069933, 0.069933, 0.069933, 0.069933",\ + "0.145759, 0.145759, 0.145759, 0.145759, 0.145760",\ + "0.443908, 0.443908, 0.443908, 0.443908, 0.443908",\ + "1.523853, 1.523853, 1.523853, 1.523854, 1.523858",\ + "0.040587, 0.040587, 0.040587, 0.040588, 0.040588",\ + "0.069933, 0.069933, 0.069933, 0.069933, 0.069933",\ + "0.145759, 0.145759, 0.145759, 0.145759, 0.145760",\ + "0.443908, 0.443908, 0.443908, 0.443908, 0.443908",\ + "1.523853, 1.523853, 1.523853, 1.523854, 1.523858"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[6]_redg_2605*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[3]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.552667, 0.731094, 0.911354, 1.197561, 1.748678",\ + "0.583252, 0.761679, 0.941939, 1.228145, 1.779262",\ + "0.655079, 0.833506, 1.013766, 1.299972, 1.851089",\ + "0.911538, 1.089965, 1.270225, 1.556431, 2.107548",\ + "1.827306, 2.005733, 2.185993, 2.472199, 3.023317",\ + "0.637606, 0.816366, 0.997269, 1.283481, 1.835056",\ + "0.668190, 0.846951, 1.027854, 1.314066, 1.865641",\ + "0.740017, 0.918778, 1.099681, 1.385893, 1.937468",\ + "0.996476, 1.175237, 1.356140, 1.642352, 2.193927",\ + "1.912244, 2.091005, 2.271908, 2.558120, 3.109695",\ + "0.713512, 0.891810, 1.072078, 1.358078, 1.909228",\ + "0.744096, 0.922394, 1.102663, 1.388662, 1.939813",\ + "0.815923, 0.994221, 1.174490, 1.460489, 2.011640",\ + "1.072382, 1.250680, 1.430949, 1.716949, 2.268099",\ + "1.988150, 2.166448, 2.346717, 2.632716, 3.183867",\ + "0.767864, 0.946321, 1.126729, 1.412617, 1.963546",\ + "0.798448, 0.976906, 1.157314, 1.443202, 1.994130",\ + "0.870275, 1.048733, 1.229141, 1.515029, 2.065957",\ + "1.126734, 1.305192, 1.485600, 1.771488, 2.322416",\ + "2.042502, 2.220960, 2.401368, 2.687256, 3.238184",\ + "1.049286, 1.231549, 1.410680, 1.696344, 2.246823",\ + "1.079870, 1.262133, 1.441265, 1.726928, 2.277408",\ + "1.151697, 1.333960, 1.513092, 1.798755, 2.349235",\ + "1.408157, 1.590420, 1.769551, 2.055214, 2.605694",\ + "2.323925, 2.506187, 2.685319, 2.970983, 3.521462"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.040152, 0.040152, 0.040152, 0.040152, 0.040152",\ + "0.086136, 0.086136, 0.086136, 0.086136, 0.086136",\ + "0.217337, 0.217337, 0.217337, 0.217336, 0.217336",\ + "0.715483, 0.715483, 0.715483, 0.715483, 0.715483",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.040152, 0.040152, 0.040152, 0.040152, 0.040152",\ + "0.086136, 0.086136, 0.086136, 0.086136, 0.086136",\ + "0.217337, 0.217337, 0.217337, 0.217336, 0.217336",\ + "0.715483, 0.715483, 0.715483, 0.715483, 0.715483",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.040152, 0.040152, 0.040152, 0.040152, 0.040152",\ + "0.086136, 0.086136, 0.086136, 0.086136, 0.086136",\ + "0.217337, 0.217337, 0.217337, 0.217336, 0.217336",\ + "0.715483, 0.715483, 0.715483, 0.715483, 0.715483",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.040152, 0.040152, 0.040152, 0.040152, 0.040152",\ + "0.086136, 0.086136, 0.086136, 0.086136, 0.086136",\ + "0.217337, 0.217337, 0.217337, 0.217336, 0.217336",\ + "0.715483, 0.715483, 0.715483, 0.715483, 0.715483",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.040152, 0.040152, 0.040152, 0.040152, 0.040152",\ + "0.086136, 0.086136, 0.086136, 0.086136, 0.086136",\ + "0.217337, 0.217337, 0.217337, 0.217336, 0.217336",\ + "0.715483, 0.715483, 0.715483, 0.715483, 0.715483",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.425447, 0.690617, 0.949819, 1.386001, 2.258367",\ + "0.451242, 0.716412, 0.975613, 1.411796, 2.284161",\ + "0.502653, 0.767823, 1.027025, 1.463207, 2.335572",\ + "0.669463, 0.934633, 1.193834, 1.630017, 2.502382",\ + "1.259717, 1.524887, 1.784089, 2.220271, 3.092637",\ + "0.514113, 0.778692, 1.038460, 1.474230, 2.345772",\ + "0.539907, 0.804487, 1.064254, 1.500025, 2.371566",\ + "0.591319, 0.855898, 1.115665, 1.551436, 2.422977",\ + "0.758128, 1.022708, 1.282475, 1.718246, 2.589787",\ + "1.348383, 1.612962, 1.872730, 2.308500, 3.180042",\ + "0.606920, 0.871815, 1.130185, 1.566394, 2.438814",\ + "0.632714, 0.897609, 1.155979, 1.592189, 2.464608",\ + "0.684125, 0.949021, 1.207391, 1.643600, 2.516019",\ + "0.850935, 1.115831, 1.374201, 1.810410, 2.682829",\ + "1.441190, 1.706085, 1.964455, 2.400664, 3.273083",\ + "0.672642, 0.940349, 1.197205, 1.633245, 2.505325",\ + "0.698436, 0.966144, 1.222999, 1.659039, 2.531119",\ + "0.749848, 1.017555, 1.274411, 1.710450, 2.582530",\ + "0.916658, 1.184365, 1.441221, 1.877260, 2.749340",\ + "1.506912, 1.774619, 2.031475, 2.467515, 3.339595",\ + "1.018432, 1.320848, 1.567835, 2.002376, 2.871458",\ + "1.044226, 1.346642, 1.593630, 2.028170, 2.897252",\ + "1.095637, 1.398053, 1.645041, 2.079582, 2.948663",\ + "1.262447, 1.564863, 1.811851, 2.246391, 3.115473",\ + "1.852702, 2.155118, 2.402105, 2.836646, 3.705728"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.040587, 0.040587, 0.040587, 0.040587, 0.040587",\ + "0.069933, 0.069933, 0.069933, 0.069933, 0.069933",\ + "0.145759, 0.145759, 0.145759, 0.145759, 0.145759",\ + "0.443908, 0.443908, 0.443908, 0.443908, 0.443908",\ + "1.523853, 1.523853, 1.523853, 1.523852, 1.523852",\ + "0.040587, 0.040587, 0.040587, 0.040587, 0.040587",\ + "0.069933, 0.069933, 0.069933, 0.069933, 0.069933",\ + "0.145759, 0.145759, 0.145759, 0.145759, 0.145759",\ + "0.443908, 0.443908, 0.443908, 0.443908, 0.443908",\ + "1.523853, 1.523853, 1.523853, 1.523852, 1.523852",\ + "0.040587, 0.040587, 0.040587, 0.040587, 0.040587",\ + "0.069933, 0.069933, 0.069933, 0.069933, 0.069933",\ + "0.145759, 0.145759, 0.145759, 0.145759, 0.145759",\ + "0.443908, 0.443908, 0.443908, 0.443908, 0.443908",\ + "1.523853, 1.523853, 1.523853, 1.523852, 1.523852",\ + "0.040587, 0.040587, 0.040587, 0.040587, 0.040587",\ + "0.069933, 0.069933, 0.069933, 0.069933, 0.069933",\ + "0.145759, 0.145759, 0.145759, 0.145759, 0.145759",\ + "0.443908, 0.443908, 0.443908, 0.443908, 0.443908",\ + "1.523853, 1.523853, 1.523853, 1.523852, 1.523852",\ + "0.040587, 0.040587, 0.040587, 0.040587, 0.040587",\ + "0.069933, 0.069933, 0.069933, 0.069933, 0.069933",\ + "0.145759, 0.145759, 0.145759, 0.145759, 0.145759",\ + "0.443908, 0.443908, 0.443908, 0.443908, 0.443908",\ + "1.523853, 1.523853, 1.523853, 1.523852, 1.523852"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[6]_redg_2550*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + values ( "0.319941, 0.350525, 0.422353, 0.678812, 1.594576",\ + "0.407332, 0.437916, 0.509743, 0.766203, 1.681967",\ + "0.488251, 0.518835, 0.590662, 0.847122, 1.762885",\ + "0.545991, 0.576576, 0.648403, 0.904863, 1.820624",\ + "0.849304, 0.879623, 0.951109, 1.207569, 2.123717"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + values ( "0.040153, 0.086136, 0.217338, 0.715446, 2.463218",\ + "0.040153, 0.086136, 0.217409, 0.715446, 2.463218",\ + "0.040153, 0.086136, 0.217647, 0.715446, 2.463317",\ + "0.040153, 0.086137, 0.217647, 0.715446, 2.463317",\ + "0.040344, 0.086164, 0.217985, 0.715471, 2.463779"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + values ( "0.305331, 0.331125, 0.382537, 0.549347, 1.139601",\ + "0.392724, 0.418518, 0.469929, 0.636739, 1.226994",\ + "0.473593, 0.499388, 0.550799, 0.717609, 1.307863",\ + "0.531242, 0.557036, 0.608448, 0.775257, 1.365512",\ + "0.833898, 0.859693, 0.911104, 1.077914, 1.668168"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + values ( "0.040587, 0.069933, 0.145759, 0.443908, 1.524252",\ + "0.040587, 0.069933, 0.145759, 0.443908, 1.524252",\ + "0.040587, 0.069933, 0.145759, 0.443908, 1.524252",\ + "0.040587, 0.069933, 0.145759, 0.443908, 1.524252",\ + "0.040602, 0.069933, 0.145764, 0.443908, 1.524252"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[6]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[0]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.513147, 0.693261, 0.880839, 1.182819, 1.765915",\ + "0.542599, 0.722713, 0.910291, 1.212271, 1.795367",\ + "0.613669, 0.793782, 0.981361, 1.283341, 1.866437",\ + "0.869896, 1.050010, 1.237589, 1.539568, 2.122664",\ + "1.786688, 1.966802, 2.154380, 2.456360, 3.039456",\ + "0.598086, 0.778097, 0.965909, 1.268325, 1.852293",\ + "0.627537, 0.807548, 0.995361, 1.297777, 1.881745",\ + "0.698607, 0.878618, 1.066431, 1.368847, 1.952815",\ + "0.954835, 1.134846, 1.322659, 1.625075, 2.209043",\ + "1.871626, 2.051637, 2.239450, 2.541866, 3.125834",\ + "0.673998, 0.853540, 1.040718, 1.342922, 1.926466",\ + "0.703449, 0.882992, 1.070170, 1.372374, 1.955918",\ + "0.774519, 0.954062, 1.141240, 1.443444, 2.026988",\ + "1.030747, 1.210289, 1.397468, 1.699671, 2.283215",\ + "1.947538, 2.127081, 2.314259, 2.616463, 3.200007",\ + "0.728367, 0.908291, 1.095607, 1.397528, 1.980783",\ + "0.757819, 0.937743, 1.125059, 1.426980, 2.010235",\ + "0.828888, 1.008813, 1.196129, 1.498049, 2.081305",\ + "1.085116, 1.265041, 1.452356, 1.754277, 2.337533",\ + "2.001908, 2.181832, 2.369148, 2.671069, 3.254324",\ + "1.009962, 1.193856, 1.379783, 1.681254, 2.264061",\ + "1.039413, 1.223308, 1.409234, 1.710706, 2.293513",\ + "1.110483, 1.294378, 1.480304, 1.781775, 2.364582",\ + "1.366711, 1.550606, 1.736532, 2.038003, 2.620810",\ + "2.283502, 2.467397, 2.653323, 2.954795, 3.537601"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.036606, 0.036606, 0.036606, 0.036606, 0.036606",\ + "0.083622, 0.083622, 0.083622, 0.083622, 0.083622",\ + "0.215854, 0.215854, 0.215854, 0.215854, 0.215855",\ + "0.705773, 0.705773, 0.705773, 0.705773, 0.705774",\ + "2.456797, 2.456797, 2.456797, 2.456797, 2.456796",\ + "0.036606, 0.036606, 0.036606, 0.036606, 0.036606",\ + "0.083622, 0.083622, 0.083622, 0.083622, 0.083622",\ + "0.215854, 0.215854, 0.215854, 0.215854, 0.215855",\ + "0.705773, 0.705773, 0.705773, 0.705773, 0.705774",\ + "2.456797, 2.456797, 2.456797, 2.456797, 2.456796",\ + "0.036606, 0.036606, 0.036606, 0.036606, 0.036606",\ + "0.083622, 0.083622, 0.083622, 0.083622, 0.083622",\ + "0.215854, 0.215854, 0.215854, 0.215854, 0.215855",\ + "0.705773, 0.705773, 0.705773, 0.705773, 0.705774",\ + "2.456797, 2.456797, 2.456797, 2.456797, 2.456796",\ + "0.036606, 0.036606, 0.036606, 0.036606, 0.036606",\ + "0.083622, 0.083622, 0.083622, 0.083622, 0.083622",\ + "0.215854, 0.215854, 0.215854, 0.215854, 0.215855",\ + "0.705773, 0.705773, 0.705773, 0.705773, 0.705774",\ + "2.456797, 2.456797, 2.456797, 2.456797, 2.456796",\ + "0.036606, 0.036606, 0.036606, 0.036606, 0.036606",\ + "0.083622, 0.083622, 0.083622, 0.083622, 0.083622",\ + "0.215854, 0.215854, 0.215854, 0.215854, 0.215855",\ + "0.705773, 0.705773, 0.705773, 0.705773, 0.705774",\ + "2.456797, 2.456797, 2.456797, 2.456797, 2.456796"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.386312, 0.653923, 0.915324, 1.355101, 2.234262",\ + "0.410188, 0.677799, 0.939200, 1.378977, 2.258138",\ + "0.459747, 0.727358, 0.988759, 1.428536, 2.307697",\ + "0.625673, 0.893283, 1.154685, 1.594462, 2.473623",\ + "1.214481, 1.482092, 1.743493, 2.183270, 3.062431",\ + "0.475016, 0.741998, 1.003965, 1.443330, 2.321667",\ + "0.498892, 0.765874, 1.027841, 1.467206, 2.345543",\ + "0.548452, 0.815433, 1.077400, 1.516765, 2.395102",\ + "0.714377, 0.981359, 1.243325, 1.682691, 2.561028",\ + "1.303185, 1.570167, 1.832134, 2.271499, 3.149836",\ + "0.567959, 0.835318, 1.096009, 1.535576, 2.414709",\ + "0.591835, 0.859194, 1.119885, 1.559452, 2.438585",\ + "0.641394, 0.908753, 1.169445, 1.609011, 2.488144",\ + "0.807319, 1.074679, 1.335370, 1.774936, 2.654070",\ + "1.396127, 1.663487, 1.924178, 2.363745, 3.242877",\ + "0.633802, 0.903882, 1.163065, 1.602587, 2.481630",\ + "0.657678, 0.927758, 1.186941, 1.626463, 2.505507",\ + "0.707237, 0.977318, 1.236501, 1.676022, 2.555066",\ + "0.873163, 1.143243, 1.402426, 1.841948, 2.720992",\ + "1.461971, 1.732051, 1.991234, 2.430756, 3.309799",\ + "0.980324, 1.284718, 1.533736, 1.971813, 2.847966",\ + "1.004200, 1.308594, 1.557612, 1.995689, 2.871842",\ + "1.053759, 1.358153, 1.607171, 2.045248, 2.921401",\ + "1.219684, 1.524079, 1.773097, 2.211174, 3.087327",\ + "1.808493, 2.112887, 2.361905, 2.799982, 3.676135"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.032798, 0.032798, 0.032798, 0.032798, 0.032798",\ + "0.061344, 0.061344, 0.061344, 0.061344, 0.061344",\ + "0.138998, 0.138998, 0.138998, 0.138998, 0.138998",\ + "0.439342, 0.439342, 0.439342, 0.439343, 0.439343",\ + "1.518841, 1.518841, 1.518841, 1.518841, 1.518841",\ + "0.032798, 0.032798, 0.032798, 0.032798, 0.032798",\ + "0.061344, 0.061344, 0.061344, 0.061344, 0.061344",\ + "0.138998, 0.138998, 0.138998, 0.138998, 0.138998",\ + "0.439342, 0.439342, 0.439342, 0.439343, 0.439343",\ + "1.518841, 1.518841, 1.518841, 1.518841, 1.518841",\ + "0.032798, 0.032798, 0.032798, 0.032798, 0.032798",\ + "0.061344, 0.061344, 0.061344, 0.061344, 0.061344",\ + "0.138998, 0.138998, 0.138998, 0.138998, 0.138998",\ + "0.439342, 0.439342, 0.439342, 0.439343, 0.439343",\ + "1.518841, 1.518841, 1.518841, 1.518841, 1.518841",\ + "0.032798, 0.032798, 0.032798, 0.032798, 0.032798",\ + "0.061344, 0.061344, 0.061344, 0.061344, 0.061344",\ + "0.138998, 0.138998, 0.138998, 0.138998, 0.138998",\ + "0.439342, 0.439342, 0.439342, 0.439343, 0.439343",\ + "1.518841, 1.518841, 1.518841, 1.518841, 1.518841",\ + "0.032798, 0.032798, 0.032798, 0.032798, 0.032798",\ + "0.061344, 0.061344, 0.061344, 0.061344, 0.061344",\ + "0.138998, 0.138998, 0.138998, 0.138998, 0.138998",\ + "0.439342, 0.439342, 0.439343, 0.439343, 0.439343",\ + "1.518841, 1.518841, 1.518841, 1.518841, 1.518841"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[6]_redg_min_2492*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[1]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.421256, 0.684787, 0.960907, 1.429039, 2.364044",\ + "0.450707, 0.714239, 0.990358, 1.458491, 2.393496",\ + "0.521777, 0.785309, 1.061428, 1.529561, 2.464566",\ + "0.778005, 1.041536, 1.317656, 1.785789, 2.720794",\ + "1.694797, 1.958328, 2.234447, 2.702580, 3.637585",\ + "0.509450, 0.772327, 1.048474, 1.515754, 2.449978",\ + "0.538902, 0.801779, 1.077925, 1.545206, 2.479430",\ + "0.609972, 0.872849, 1.148995, 1.616276, 2.550500",\ + "0.866199, 1.129077, 1.405223, 1.872504, 2.806728",\ + "1.782991, 2.045868, 2.322014, 2.789295, 3.723519",\ + "0.597766, 0.861307, 1.136438, 1.603395, 2.536933",\ + "0.627218, 0.890759, 1.165890, 1.632846, 2.566385",\ + "0.698288, 0.961829, 1.236960, 1.703916, 2.637455",\ + "0.954515, 1.218056, 1.493188, 1.960144, 2.893683",\ + "1.871307, 2.134848, 2.409979, 2.876935, 3.810474",\ + "0.660262, 0.926941, 1.200578, 1.667483, 2.600442",\ + "0.689714, 0.956392, 1.230030, 1.696935, 2.629894",\ + "0.760784, 1.027462, 1.301100, 1.768005, 2.700964",\ + "1.017011, 1.283690, 1.557327, 2.024233, 2.957192",\ + "1.933803, 2.200481, 2.474119, 2.941024, 3.873983",\ + "0.989388, 1.291255, 1.552442, 2.016927, 2.945898",\ + "1.018839, 1.320707, 1.581894, 2.046379, 2.975350",\ + "1.089909, 1.391777, 1.652964, 2.117449, 3.046420",\ + "1.346137, 1.648005, 1.909191, 2.373677, 3.302648",\ + "2.262928, 2.564796, 2.825983, 3.290468, 4.219439"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.036606, 0.036606, 0.036606, 0.036607, 0.036607",\ + "0.083622, 0.083622, 0.083622, 0.083623, 0.083623",\ + "0.215854, 0.215855, 0.215855, 0.215855, 0.215856",\ + "0.705773, 0.705774, 0.705775, 0.705777, 0.705782",\ + "2.456797, 2.456796, 2.456794, 2.456789, 2.456778",\ + "0.036606, 0.036606, 0.036606, 0.036607, 0.036607",\ + "0.083622, 0.083622, 0.083622, 0.083623, 0.083623",\ + "0.215854, 0.215855, 0.215855, 0.215855, 0.215856",\ + "0.705773, 0.705774, 0.705775, 0.705777, 0.705782",\ + "2.456797, 2.456796, 2.456794, 2.456789, 2.456778",\ + "0.036606, 0.036606, 0.036606, 0.036607, 0.036607",\ + "0.083622, 0.083622, 0.083622, 0.083623, 0.083623",\ + "0.215854, 0.215855, 0.215855, 0.215855, 0.215856",\ + "0.705773, 0.705774, 0.705775, 0.705777, 0.705782",\ + "2.456797, 2.456796, 2.456794, 2.456789, 2.456778",\ + "0.036606, 0.036606, 0.036606, 0.036607, 0.036607",\ + "0.083622, 0.083622, 0.083622, 0.083623, 0.083623",\ + "0.215854, 0.215855, 0.215855, 0.215855, 0.215856",\ + "0.705773, 0.705774, 0.705775, 0.705777, 0.705782",\ + "2.456797, 2.456796, 2.456794, 2.456789, 2.456778",\ + "0.036606, 0.036606, 0.036606, 0.036607, 0.036607",\ + "0.083622, 0.083622, 0.083622, 0.083623, 0.083623",\ + "0.215854, 0.215855, 0.215855, 0.215855, 0.215856",\ + "0.705773, 0.705774, 0.705775, 0.705777, 0.705782",\ + "2.456797, 2.456796, 2.456794, 2.456789, 2.456778"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.369267, 0.551325, 0.747559, 1.056740, 1.651224",\ + "0.393143, 0.575201, 0.771435, 1.080616, 1.675100",\ + "0.442703, 0.624760, 0.820994, 1.130175, 1.724659",\ + "0.608628, 0.790685, 0.986919, 1.296102, 1.890590",\ + "1.197436, 1.379494, 1.575727, 1.884908, 2.479391",\ + "0.456682, 0.638644, 0.834839, 1.144045, 1.738577",\ + "0.480558, 0.662519, 0.858715, 1.167921, 1.762453",\ + "0.530117, 0.712079, 0.908275, 1.217480, 1.812012",\ + "0.696043, 0.878004, 1.074200, 1.383407, 1.977943",\ + "1.284851, 1.466812, 1.663008, 1.972213, 2.566744",\ + "0.537558, 0.718980, 0.914866, 1.224073, 1.818609",\ + "0.561434, 0.742856, 0.938742, 1.247949, 1.842485",\ + "0.610994, 0.792415, 0.988301, 1.297508, 1.892044",\ + "0.776919, 0.958341, 1.154227, 1.463436, 2.057975",\ + "1.365727, 1.547149, 1.743035, 2.052242, 2.646776",\ + "0.595205, 0.776817, 0.972602, 1.281544, 1.875705",\ + "0.619081, 0.800693, 0.996478, 1.305420, 1.899580",\ + "0.668640, 0.850252, 1.046037, 1.354979, 1.949140",\ + "0.834565, 1.016178, 1.211963, 1.520906, 2.115070",\ + "1.423374, 1.604986, 1.800771, 2.109712, 2.703871",\ + "0.897412, 1.082194, 1.276265, 1.584751, 2.178023",\ + "0.921288, 1.106070, 1.300141, 1.608627, 2.201899",\ + "0.970848, 1.155629, 1.349701, 1.658186, 2.251458",\ + "1.136773, 1.321555, 1.515626, 1.824113, 2.417389",\ + "1.725581, 1.910363, 2.104434, 2.412919, 3.006190"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.032797, 0.032797, 0.032797, 0.032797, 0.032797",\ + "0.061344, 0.061344, 0.061344, 0.061345, 0.061345",\ + "0.138997, 0.138997, 0.138997, 0.138997, 0.138997",\ + "0.439321, 0.439321, 0.439321, 0.439321, 0.439321",\ + "1.518841, 1.518841, 1.518841, 1.518842, 1.518844",\ + "0.032797, 0.032797, 0.032797, 0.032797, 0.032797",\ + "0.061344, 0.061344, 0.061344, 0.061345, 0.061345",\ + "0.138997, 0.138997, 0.138997, 0.138997, 0.138997",\ + "0.439321, 0.439321, 0.439321, 0.439321, 0.439321",\ + "1.518841, 1.518841, 1.518841, 1.518842, 1.518844",\ + "0.032797, 0.032797, 0.032797, 0.032797, 0.032797",\ + "0.061344, 0.061344, 0.061344, 0.061345, 0.061345",\ + "0.138997, 0.138997, 0.138997, 0.138997, 0.138997",\ + "0.439321, 0.439321, 0.439321, 0.439321, 0.439321",\ + "1.518841, 1.518841, 1.518841, 1.518842, 1.518844",\ + "0.032797, 0.032797, 0.032797, 0.032797, 0.032797",\ + "0.061344, 0.061344, 0.061344, 0.061345, 0.061345",\ + "0.138997, 0.138997, 0.138997, 0.138997, 0.138997",\ + "0.439321, 0.439321, 0.439321, 0.439321, 0.439321",\ + "1.518841, 1.518841, 1.518841, 1.518842, 1.518844",\ + "0.032797, 0.032797, 0.032797, 0.032797, 0.032797",\ + "0.061344, 0.061344, 0.061344, 0.061345, 0.061345",\ + "0.138997, 0.138997, 0.138997, 0.138997, 0.138997",\ + "0.439321, 0.439321, 0.439321, 0.439321, 0.439321",\ + "1.518841, 1.518841, 1.518841, 1.518842, 1.518844"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[6]_redg_min_2414*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[2]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.417278, 0.676837, 0.948472, 1.404635, 2.315804",\ + "0.446729, 0.706289, 0.977924, 1.434087, 2.345256",\ + "0.517799, 0.777359, 1.048994, 1.505156, 2.416326",\ + "0.774027, 1.033586, 1.305222, 1.761384, 2.672554",\ + "1.690818, 1.950378, 2.222013, 2.678176, 3.589346",\ + "0.505382, 0.764370, 1.036001, 1.491350, 2.401738",\ + "0.534834, 0.793822, 1.065453, 1.520802, 2.431190",\ + "0.605904, 0.864891, 1.136523, 1.591872, 2.502260",\ + "0.862132, 1.121119, 1.392751, 1.848100, 2.758488",\ + "1.778923, 2.037910, 2.309542, 2.764891, 3.675279",\ + "0.593413, 0.853334, 1.123966, 1.578989, 2.488693",\ + "0.622864, 0.882786, 1.153417, 1.608441, 2.518145",\ + "0.693934, 0.953856, 1.224487, 1.679511, 2.589215",\ + "0.950162, 1.210083, 1.480715, 1.935739, 2.845443",\ + "1.866953, 2.126875, 2.397506, 2.852530, 3.762234",\ + "0.655634, 0.918945, 1.188103, 1.643063, 2.552202",\ + "0.685085, 0.948397, 1.217555, 1.672515, 2.581654",\ + "0.756155, 1.019467, 1.288625, 1.743585, 2.652724",\ + "1.012383, 1.275695, 1.544853, 1.999813, 2.908952",\ + "1.929174, 2.192486, 2.461644, 2.916605, 3.825743",\ + "0.983021, 1.282994, 1.539846, 1.992450, 2.897658",\ + "1.012473, 1.312446, 1.569298, 2.021902, 2.927110",\ + "1.083543, 1.383515, 1.640368, 2.092972, 2.998180",\ + "1.339770, 1.639743, 1.896595, 2.349199, 3.254408",\ + "2.256562, 2.556535, 2.813387, 3.265991, 4.171200"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.036606, 0.036606, 0.036606, 0.036607, 0.036608",\ + "0.083622, 0.083622, 0.083622, 0.083623, 0.083623",\ + "0.215854, 0.215855, 0.215855, 0.215855, 0.215856",\ + "0.705773, 0.705774, 0.705776, 0.705780, 0.705788",\ + "2.456797, 2.456796, 2.456792, 2.456784, 2.456766",\ + "0.036606, 0.036606, 0.036606, 0.036607, 0.036608",\ + "0.083622, 0.083622, 0.083622, 0.083623, 0.083623",\ + "0.215854, 0.215855, 0.215855, 0.215855, 0.215856",\ + "0.705773, 0.705774, 0.705776, 0.705780, 0.705788",\ + "2.456797, 2.456796, 2.456792, 2.456784, 2.456766",\ + "0.036606, 0.036606, 0.036606, 0.036607, 0.036608",\ + "0.083622, 0.083622, 0.083622, 0.083623, 0.083623",\ + "0.215854, 0.215855, 0.215855, 0.215855, 0.215856",\ + "0.705773, 0.705774, 0.705776, 0.705780, 0.705788",\ + "2.456797, 2.456796, 2.456792, 2.456784, 2.456766",\ + "0.036606, 0.036606, 0.036606, 0.036607, 0.036608",\ + "0.083622, 0.083622, 0.083622, 0.083623, 0.083623",\ + "0.215854, 0.215855, 0.215855, 0.215855, 0.215856",\ + "0.705773, 0.705774, 0.705776, 0.705780, 0.705788",\ + "2.456797, 2.456796, 2.456792, 2.456784, 2.456766",\ + "0.036606, 0.036606, 0.036606, 0.036607, 0.036608",\ + "0.083622, 0.083622, 0.083622, 0.083623, 0.083623",\ + "0.215854, 0.215855, 0.215855, 0.215855, 0.215856",\ + "0.705773, 0.705774, 0.705776, 0.705780, 0.705788",\ + "2.456797, 2.456796, 2.456792, 2.456784, 2.456766"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.367604, 0.549771, 0.745869, 1.055208, 1.650168",\ + "0.391480, 0.573647, 0.769745, 1.079083, 1.674044",\ + "0.441039, 0.623206, 0.819305, 1.128643, 1.723603",\ + "0.606964, 0.789132, 0.985230, 1.294570, 1.889535",\ + "1.195773, 1.377940, 1.574038, 1.883376, 2.478335",\ + "0.455024, 0.637090, 0.833150, 1.142513, 1.737522",\ + "0.478900, 0.660966, 0.857026, 1.166389, 1.761397",\ + "0.528459, 0.710525, 0.906585, 1.215948, 1.810957",\ + "0.694384, 0.876450, 1.072511, 1.381875, 1.976888",\ + "1.283193, 1.465259, 1.661319, 1.970681, 2.565688",\ + "0.535891, 0.717427, 0.913177, 1.222541, 1.817554",\ + "0.559767, 0.741302, 0.937053, 1.246417, 1.841429",\ + "0.609326, 0.790862, 0.986612, 1.295976, 1.890988",\ + "0.775252, 0.956787, 1.152538, 1.461904, 2.056920",\ + "1.364060, 1.545596, 1.741346, 2.050709, 2.645720",\ + "0.593530, 0.775263, 0.970912, 1.280012, 1.874650",\ + "0.617406, 0.799139, 0.994788, 1.303888, 1.898526",\ + "0.666965, 0.848699, 1.044348, 1.353447, 1.948085",\ + "0.832891, 1.014624, 1.210274, 1.519375, 2.114016",\ + "1.421699, 1.603432, 1.799081, 2.108180, 2.702816",\ + "0.895625, 1.080642, 1.274576, 1.583220, 2.176970",\ + "0.919501, 1.104518, 1.298452, 1.607095, 2.200845",\ + "0.969060, 1.154077, 1.348011, 1.656655, 2.250404",\ + "1.134986, 1.320002, 1.513937, 1.822582, 2.416336",\ + "1.723794, 1.908811, 2.102745, 2.411388, 3.005136"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.032796, 0.032796, 0.032796, 0.032796, 0.032796",\ + "0.061344, 0.061344, 0.061344, 0.061345, 0.061345",\ + "0.138997, 0.138997, 0.138997, 0.138997, 0.138997",\ + "0.439319, 0.439319, 0.439319, 0.439319, 0.439319",\ + "1.518841, 1.518841, 1.518841, 1.518842, 1.518844",\ + "0.032796, 0.032796, 0.032796, 0.032796, 0.032796",\ + "0.061344, 0.061344, 0.061344, 0.061345, 0.061345",\ + "0.138997, 0.138997, 0.138997, 0.138997, 0.138997",\ + "0.439319, 0.439319, 0.439319, 0.439319, 0.439319",\ + "1.518841, 1.518841, 1.518841, 1.518842, 1.518844",\ + "0.032796, 0.032796, 0.032796, 0.032796, 0.032796",\ + "0.061344, 0.061344, 0.061344, 0.061345, 0.061345",\ + "0.138997, 0.138997, 0.138997, 0.138997, 0.138997",\ + "0.439319, 0.439319, 0.439319, 0.439319, 0.439319",\ + "1.518841, 1.518841, 1.518841, 1.518842, 1.518844",\ + "0.032796, 0.032796, 0.032796, 0.032796, 0.032796",\ + "0.061344, 0.061344, 0.061344, 0.061345, 0.061345",\ + "0.138997, 0.138997, 0.138997, 0.138997, 0.138997",\ + "0.439319, 0.439319, 0.439319, 0.439319, 0.439319",\ + "1.518841, 1.518841, 1.518841, 1.518842, 1.518844",\ + "0.032796, 0.032796, 0.032796, 0.032796, 0.032796",\ + "0.061344, 0.061344, 0.061344, 0.061345, 0.061345",\ + "0.138997, 0.138997, 0.138997, 0.138997, 0.138997",\ + "0.439319, 0.439319, 0.439319, 0.439319, 0.439319",\ + "1.518841, 1.518841, 1.518841, 1.518842, 1.518844"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[6]_redg_min_2348*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[3]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.509561, 0.687900, 0.868247, 1.154434, 1.705187",\ + "0.539012, 0.717352, 0.897699, 1.183885, 1.734638",\ + "0.610082, 0.788422, 0.968769, 1.254955, 1.805708",\ + "0.866310, 1.044649, 1.224996, 1.511183, 2.061936",\ + "1.783102, 1.961441, 2.141788, 2.427974, 2.978728",\ + "0.594499, 0.772736, 0.953317, 1.239940, 1.791565",\ + "0.623951, 0.802188, 0.982769, 1.269392, 1.821017",\ + "0.695021, 0.873258, 1.053839, 1.340461, 1.892087",\ + "0.951248, 1.129485, 1.310066, 1.596689, 2.148314",\ + "1.868040, 2.046277, 2.226858, 2.513481, 3.065106",\ + "0.670405, 0.848179, 1.028126, 1.314537, 1.865738",\ + "0.699857, 0.877631, 1.057578, 1.343988, 1.895189",\ + "0.770927, 0.948701, 1.128648, 1.415058, 1.966259",\ + "1.027155, 1.204929, 1.384875, 1.671286, 2.222487",\ + "1.943946, 2.121720, 2.301667, 2.588078, 3.139278",\ + "0.724757, 0.902925, 1.082991, 1.369130, 1.920055",\ + "0.754209, 0.932377, 1.112443, 1.398582, 1.949507",\ + "0.825279, 1.003447, 1.183513, 1.469652, 2.020576",\ + "1.081507, 1.259674, 1.439741, 1.725880, 2.276804",\ + "1.998298, 2.176466, 2.356532, 2.642671, 3.193595",\ + "1.006179, 1.188442, 1.367144, 1.652857, 2.203332",\ + "1.035631, 1.217894, 1.396596, 1.682308, 2.232784",\ + "1.106701, 1.288964, 1.467666, 1.753378, 2.303854",\ + "1.362929, 1.545192, 1.723894, 2.009606, 2.560082",\ + "2.279720, 2.461983, 2.640685, 2.926397, 3.476873"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.036606, 0.036606, 0.036606, 0.036606, 0.036606",\ + "0.083622, 0.083622, 0.083622, 0.083622, 0.083622",\ + "0.215854, 0.215854, 0.215854, 0.215854, 0.215855",\ + "0.705773, 0.705773, 0.705773, 0.705774, 0.705774",\ + "2.456797, 2.456797, 2.456797, 2.456797, 2.456796",\ + "0.036606, 0.036606, 0.036606, 0.036606, 0.036606",\ + "0.083622, 0.083622, 0.083622, 0.083622, 0.083622",\ + "0.215854, 0.215854, 0.215854, 0.215854, 0.215855",\ + "0.705773, 0.705773, 0.705773, 0.705774, 0.705774",\ + "2.456797, 2.456797, 2.456797, 2.456797, 2.456796",\ + "0.036606, 0.036606, 0.036606, 0.036606, 0.036606",\ + "0.083622, 0.083622, 0.083622, 0.083622, 0.083622",\ + "0.215854, 0.215854, 0.215854, 0.215854, 0.215855",\ + "0.705773, 0.705773, 0.705773, 0.705774, 0.705774",\ + "2.456797, 2.456797, 2.456797, 2.456797, 2.456796",\ + "0.036606, 0.036606, 0.036606, 0.036606, 0.036606",\ + "0.083622, 0.083622, 0.083622, 0.083622, 0.083622",\ + "0.215854, 0.215854, 0.215854, 0.215854, 0.215855",\ + "0.705773, 0.705773, 0.705773, 0.705774, 0.705774",\ + "2.456797, 2.456797, 2.456797, 2.456797, 2.456796",\ + "0.036606, 0.036606, 0.036606, 0.036606, 0.036606",\ + "0.083622, 0.083622, 0.083622, 0.083622, 0.083622",\ + "0.215854, 0.215854, 0.215854, 0.215854, 0.215855",\ + "0.705773, 0.705773, 0.705773, 0.705774, 0.705774",\ + "2.456797, 2.456797, 2.456797, 2.456797, 2.456796"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.384876, 0.649875, 0.908905, 1.345169, 2.217316",\ + "0.408752, 0.673751, 0.932781, 1.369045, 2.241192",\ + "0.458311, 0.723311, 0.982340, 1.418604, 2.290751",\ + "0.624237, 0.889236, 1.148266, 1.584530, 2.456676",\ + "1.213045, 1.478044, 1.737074, 2.173338, 3.045485",\ + "0.473542, 0.737950, 0.997546, 1.433398, 2.304721",\ + "0.497418, 0.761826, 1.021422, 1.457274, 2.328597",\ + "0.546977, 0.811386, 1.070981, 1.506833, 2.378156",\ + "0.712902, 0.977311, 1.236907, 1.672759, 2.544082",\ + "1.301711, 1.566119, 1.825715, 2.261567, 3.132890",\ + "0.566349, 0.831244, 1.089581, 1.525641, 2.397763",\ + "0.590225, 0.855120, 1.113457, 1.549517, 2.421639",\ + "0.639784, 0.904679, 1.163016, 1.599077, 2.471198",\ + "0.805709, 1.070605, 1.328942, 1.765002, 2.637124",\ + "1.394518, 1.659413, 1.917750, 2.353810, 3.225932",\ + "0.632071, 0.899778, 1.156636, 1.592648, 2.464673",\ + "0.655947, 0.923654, 1.180512, 1.616524, 2.488548",\ + "0.705506, 0.973213, 1.230071, 1.666083, 2.538108",\ + "0.871432, 1.139139, 1.395997, 1.832009, 2.704033",\ + "1.460240, 1.727947, 1.984805, 2.420817, 3.292841",\ + "0.977860, 1.280277, 1.527274, 1.961849, 2.830999",\ + "1.001736, 1.304152, 1.551150, 1.985725, 2.854876",\ + "1.051296, 1.353712, 1.600709, 2.035285, 2.904435",\ + "1.217221, 1.519637, 1.766635, 2.201210, 3.070360",\ + "1.806029, 2.108445, 2.355443, 2.790018, 3.659168"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.032798, 0.032798, 0.032798, 0.032798, 0.032798",\ + "0.061344, 0.061344, 0.061344, 0.061344, 0.061344",\ + "0.138998, 0.138998, 0.138998, 0.138998, 0.138998",\ + "0.439342, 0.439342, 0.439343, 0.439343, 0.439343",\ + "1.518841, 1.518841, 1.518841, 1.518841, 1.518841",\ + "0.032798, 0.032798, 0.032798, 0.032798, 0.032798",\ + "0.061344, 0.061344, 0.061344, 0.061344, 0.061344",\ + "0.138998, 0.138998, 0.138998, 0.138998, 0.138998",\ + "0.439342, 0.439342, 0.439343, 0.439343, 0.439343",\ + "1.518841, 1.518841, 1.518841, 1.518841, 1.518841",\ + "0.032798, 0.032798, 0.032798, 0.032798, 0.032798",\ + "0.061344, 0.061344, 0.061344, 0.061344, 0.061344",\ + "0.138998, 0.138998, 0.138998, 0.138998, 0.138998",\ + "0.439342, 0.439342, 0.439343, 0.439343, 0.439343",\ + "1.518841, 1.518841, 1.518841, 1.518841, 1.518841",\ + "0.032798, 0.032798, 0.032798, 0.032798, 0.032798",\ + "0.061344, 0.061344, 0.061344, 0.061344, 0.061344",\ + "0.138998, 0.138998, 0.138998, 0.138998, 0.138998",\ + "0.439342, 0.439342, 0.439343, 0.439343, 0.439343",\ + "1.518841, 1.518841, 1.518841, 1.518841, 1.518841",\ + "0.032798, 0.032798, 0.032798, 0.032798, 0.032798",\ + "0.061344, 0.061344, 0.061344, 0.061344, 0.061344",\ + "0.138998, 0.138998, 0.138998, 0.138998, 0.138998",\ + "0.439342, 0.439342, 0.439343, 0.439343, 0.439343",\ + "1.518841, 1.518841, 1.518841, 1.518841, 1.518841"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[6]_redg_min_2294*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + values ( "0.137566, 0.167336, 0.239033, 0.495310, 1.411098",\ + "0.225751, 0.255520, 0.327229, 0.583553, 1.499024",\ + "0.314076, 0.343844, 0.415554, 0.672074, 1.587106",\ + "0.376665, 0.406437, 0.478090, 0.734905, 1.650403",\ + "0.706539, 0.736325, 0.807782, 1.065036, 1.982165"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + values ( "0.036606, 0.083622, 0.215854, 0.705773, 2.456797",\ + "0.036606, 0.083622, 0.215854, 0.705773, 2.456797",\ + "0.036606, 0.083622, 0.215854, 0.705773, 2.456797",\ + "0.036606, 0.083622, 0.215854, 0.705773, 2.456797",\ + "0.036606, 0.083622, 0.215854, 0.705773, 2.456797"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + values ( "0.176657, 0.200194, 0.249429, 0.415146, 1.003925",\ + "0.264061, 0.287598, 0.336833, 0.502550, 1.091329",\ + "0.344959, 0.368493, 0.417732, 0.583454, 1.172242",\ + "0.402624, 0.426151, 0.475399, 0.641128, 1.229933",\ + "0.704984, 0.728497, 0.777773, 0.943572, 1.532550"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + values ( "0.032799, 0.061344, 0.138999, 0.438536, 1.518306",\ + "0.032799, 0.061344, 0.138999, 0.438535, 1.518306",\ + "0.032799, 0.061344, 0.138999, 0.438535, 1.518105",\ + "0.032799, 0.061344, 0.138999, 0.438535, 1.517729",\ + "0.032799, 0.061344, 0.138998, 0.438535, 1.516557"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[6]_redg_min*/ + + timing () { + related_pin : "padmux2ast_i[6]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + values ( "0.078864, 0.108975, 0.180232, 0.436421, 1.354955",\ + "0.161216, 0.191623, 0.263062, 0.519150, 1.434794",\ + "0.248912, 0.281774, 0.353596, 0.609294, 1.527520",\ + "0.395567, 0.436700, 0.511657, 0.767118, 1.680857",\ + "0.628444, 0.688613, 0.779970, 1.032241, 1.943170"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + values ( "0.039377, 0.084977, 0.216447, 0.713042, 2.472405",\ + "0.040943, 0.085824, 0.216786, 0.713478, 2.472405",\ + "0.053222, 0.092507, 0.217591, 0.713478, 2.472405",\ + "0.083456, 0.114560, 0.223431, 0.713478, 2.472405",\ + "0.146897, 0.173026, 0.257773, 0.713478, 2.472405"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + values ( "0.111091, 0.136344, 0.187602, 0.354583, 0.943175",\ + "0.190778, 0.216967, 0.268153, 0.434275, 1.024748",\ + "0.290508, 0.318338, 0.371105, 0.537415, 1.127562",\ + "0.459624, 0.495257, 0.553492, 0.720404, 1.308180",\ + "0.729304, 0.783232, 0.859550, 1.032706, 1.617889"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + values ( "0.039826, 0.069221, 0.145259, 0.444902, 1.525117",\ + "0.040254, 0.069221, 0.145259, 0.444902, 1.525117",\ + "0.050781, 0.076552, 0.148038, 0.444902, 1.525117",\ + "0.080540, 0.101538, 0.163724, 0.445523, 1.525117",\ + "0.141255, 0.162992, 0.212369, 0.458214, 1.525117"); + } + + } /* end of arc padmux2ast_i[6]_obs_ctrl_o[6]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[6]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + values ( "0.074357, 0.103835, 0.175088, 0.430040, 1.346996",\ + "0.156284, 0.185798, 0.256925, 0.512689, 1.426492",\ + "0.240577, 0.272242, 0.343453, 0.599199, 1.515415",\ + "0.383466, 0.422274, 0.495817, 0.750018, 1.664121",\ + "0.607663, 0.663725, 0.751347, 1.002896, 1.912977"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + values ( "0.036939, 0.083563, 0.215464, 0.698603, 2.446539",\ + "0.038445, 0.084260, 0.215464, 0.704042, 2.446539",\ + "0.049297, 0.090259, 0.216941, 0.705803, 2.446539",\ + "0.076679, 0.110998, 0.222061, 0.706283, 2.457507",\ + "0.134063, 0.165740, 0.252770, 0.710864, 2.457507"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + values ( "0.080261, 0.102858, 0.151114, 0.316434, 0.906304",\ + "0.165732, 0.188510, 0.236836, 0.401880, 0.995903",\ + "0.261156, 0.287506, 0.337668, 0.502550, 1.091127",\ + "0.420973, 0.455458, 0.511965, 0.676394, 1.262831",\ + "0.677498, 0.731290, 0.807033, 0.979368, 1.563209"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + values ( "0.032396, 0.061186, 0.138642, 0.440176, 1.520011",\ + "0.033582, 0.061465, 0.138784, 0.440176, 1.520011",\ + "0.046234, 0.071020, 0.142472, 0.440176, 1.520011",\ + "0.075362, 0.096304, 0.158284, 0.443536, 1.520011",\ + "0.135524, 0.156881, 0.206007, 0.453845, 1.520011"); + } + + } /* end of arc padmux2ast_i[6]_obs_ctrl_o[6]_una_min*/ + +} /* end of pin obs_ctrl_o[6] */ + +pin("obs_ctrl_o[5]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.156168 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001502 ; + + /* Other user defined attributes. */ + original_pin : obs_ctrl_o[5]; + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[0]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.561257, 0.741460, 0.928950, 1.230943, 1.814455",\ + "0.591077, 0.771280, 0.958770, 1.260762, 1.844274",\ + "0.662801, 0.843004, 1.030494, 1.332487, 1.915998",\ + "0.919252, 1.099455, 1.286945, 1.588937, 2.172449",\ + "1.830892, 2.011095, 2.198585, 2.500578, 3.084090",\ + "0.646196, 0.826743, 1.014959, 1.316955, 1.900833",\ + "0.676015, 0.856563, 1.044779, 1.346775, 1.930653",\ + "0.747739, 0.928287, 1.116503, 1.418499, 2.002377",\ + "1.004190, 1.184738, 1.372953, 1.674950, 2.258828",\ + "1.915830, 2.096378, 2.284594, 2.586590, 3.170468",\ + "0.722108, 0.902187, 1.089768, 1.391552, 1.975005",\ + "0.751927, 0.932006, 1.119587, 1.421371, 2.004825",\ + "0.823651, 1.003731, 1.191312, 1.493096, 2.076549",\ + "1.080102, 1.260181, 1.447762, 1.749547, 2.333000",\ + "1.991742, 2.171822, 2.359402, 2.661187, 3.244640",\ + "0.776477, 0.956699, 1.144419, 1.446092, 2.029323",\ + "0.806297, 0.986518, 1.174238, 1.475911, 2.059142",\ + "0.878021, 1.058242, 1.245963, 1.547635, 2.130867",\ + "1.134472, 1.314693, 1.502414, 1.804086, 2.387317",\ + "2.046112, 2.226333, 2.414053, 2.715726, 3.298958",\ + "1.058072, 1.241966, 1.428370, 1.729818, 2.312600",\ + "1.087891, 1.271786, 1.458189, 1.759638, 2.342420",\ + "1.159616, 1.343510, 1.529913, 1.831362, 2.414144",\ + "1.416066, 1.599961, 1.786364, 2.087812, 2.670595",\ + "2.327706, 2.511601, 2.698004, 2.999453, 3.582235"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.047100, 0.047100, 0.047100, 0.047100, 0.047100",\ + "0.093802, 0.093802, 0.093802, 0.093802, 0.093802",\ + "0.225237, 0.225237, 0.225237, 0.225237, 0.225237",\ + "0.723332, 0.723332, 0.723332, 0.723332, 0.723332",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.047100, 0.047100, 0.047100, 0.047100, 0.047100",\ + "0.093802, 0.093802, 0.093802, 0.093802, 0.093802",\ + "0.225237, 0.225237, 0.225237, 0.225237, 0.225237",\ + "0.723332, 0.723332, 0.723332, 0.723332, 0.723332",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.047100, 0.047100, 0.047100, 0.047100, 0.047100",\ + "0.093802, 0.093802, 0.093802, 0.093802, 0.093802",\ + "0.225237, 0.225237, 0.225237, 0.225237, 0.225237",\ + "0.723332, 0.723332, 0.723332, 0.723332, 0.723332",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.047100, 0.047100, 0.047100, 0.047100, 0.047100",\ + "0.093802, 0.093802, 0.093802, 0.093802, 0.093802",\ + "0.225237, 0.225237, 0.225237, 0.225237, 0.225237",\ + "0.723332, 0.723332, 0.723332, 0.723332, 0.723332",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.047100, 0.047100, 0.047100, 0.047100, 0.047100",\ + "0.093802, 0.093802, 0.093802, 0.093802, 0.093802",\ + "0.225237, 0.225237, 0.225237, 0.225237, 0.225237",\ + "0.723332, 0.723332, 0.723332, 0.723332, 0.723332",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.431434, 0.699219, 0.960799, 1.400496, 2.279891",\ + "0.455832, 0.723618, 0.985198, 1.424895, 2.304290",\ + "0.506856, 0.774642, 1.036222, 1.475919, 2.355314",\ + "0.673635, 0.941421, 1.203001, 1.642698, 2.522093",\ + "1.261229, 1.529015, 1.790595, 2.230292, 3.109687",\ + "0.520138, 0.787294, 1.049440, 1.488726, 2.367296",\ + "0.544536, 0.811693, 1.073839, 1.513124, 2.391695",\ + "0.595560, 0.862717, 1.124863, 1.564148, 2.442719",\ + "0.762339, 1.029496, 1.291642, 1.730927, 2.609498",\ + "1.349933, 1.617090, 1.879236, 2.318521, 3.197092",\ + "0.613080, 0.880439, 1.141166, 1.580890, 2.460338",\ + "0.637479, 0.904838, 1.165565, 1.605289, 2.484737",\ + "0.688503, 0.955862, 1.216588, 1.656312, 2.535761",\ + "0.855281, 1.122641, 1.383367, 1.823091, 2.702539",\ + "1.442875, 1.710235, 1.970961, 2.410685, 3.290133",\ + "0.678924, 0.949004, 1.208186, 1.647740, 2.526850",\ + "0.703322, 0.973402, 1.232584, 1.672139, 2.551248",\ + "0.754346, 1.024426, 1.283608, 1.723163, 2.602272",\ + "0.921125, 1.191205, 1.450387, 1.889941, 2.769051",\ + "1.508719, 1.778799, 2.037981, 2.477535, 3.356645",\ + "1.025445, 1.329839, 1.578848, 2.016894, 2.892985",\ + "1.049844, 1.354238, 1.603247, 2.041293, 2.917384",\ + "1.100868, 1.405262, 1.654271, 2.092317, 2.968408",\ + "1.267646, 1.572041, 1.821050, 2.259095, 3.135186",\ + "1.855240, 2.159635, 2.408644, 2.846689, 3.722780"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.045359, 0.045359, 0.045359, 0.045359, 0.045359",\ + "0.074479, 0.074479, 0.074479, 0.074479, 0.074479",\ + "0.150687, 0.150687, 0.150687, 0.150687, 0.150687",\ + "0.448891, 0.448891, 0.448891, 0.448891, 0.448891",\ + "1.523991, 1.523991, 1.523991, 1.523991, 1.523991",\ + "0.045359, 0.045359, 0.045359, 0.045359, 0.045359",\ + "0.074479, 0.074479, 0.074479, 0.074479, 0.074479",\ + "0.150687, 0.150687, 0.150687, 0.150687, 0.150687",\ + "0.448891, 0.448891, 0.448891, 0.448891, 0.448891",\ + "1.523991, 1.523991, 1.523991, 1.523991, 1.523991",\ + "0.045359, 0.045359, 0.045359, 0.045359, 0.045359",\ + "0.074479, 0.074479, 0.074479, 0.074479, 0.074479",\ + "0.150687, 0.150687, 0.150687, 0.150687, 0.150687",\ + "0.448891, 0.448891, 0.448891, 0.448891, 0.448891",\ + "1.523991, 1.523991, 1.523991, 1.523991, 1.523991",\ + "0.045359, 0.045359, 0.045359, 0.045359, 0.045359",\ + "0.074479, 0.074479, 0.074479, 0.074479, 0.074479",\ + "0.150687, 0.150687, 0.150687, 0.150687, 0.150687",\ + "0.448891, 0.448891, 0.448891, 0.448891, 0.448891",\ + "1.523991, 1.523991, 1.523991, 1.523991, 1.523991",\ + "0.045359, 0.045359, 0.045359, 0.045359, 0.045359",\ + "0.074479, 0.074479, 0.074479, 0.074479, 0.074479",\ + "0.150687, 0.150687, 0.150687, 0.150687, 0.150687",\ + "0.448891, 0.448891, 0.448891, 0.448891, 0.448891",\ + "1.523991, 1.523991, 1.523991, 1.523991, 1.523991"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[5]_redg_2732*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[1]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.469363, 0.732936, 1.009209, 1.477938, 2.415398",\ + "0.499182, 0.762756, 1.039028, 1.507758, 2.445217",\ + "0.570906, 0.834480, 1.110752, 1.579482, 2.516941",\ + "0.827357, 1.090931, 1.367203, 1.835933, 2.773392",\ + "1.738997, 2.002571, 2.278844, 2.747575, 3.685036",\ + "0.557557, 0.820477, 1.096777, 1.564654, 2.501331",\ + "0.587376, 0.850296, 1.126596, 1.594473, 2.531151",\ + "0.659100, 0.922021, 1.198320, 1.666197, 2.602875",\ + "0.915551, 1.178471, 1.454771, 1.922648, 2.859325",\ + "1.827192, 2.090112, 2.366412, 2.834290, 3.770969",\ + "0.645873, 0.909457, 1.184741, 1.652276, 2.588286",\ + "0.675692, 0.939277, 1.214561, 1.682096, 2.618106",\ + "0.747417, 1.011001, 1.286285, 1.753820, 2.689830",\ + "1.003868, 1.267452, 1.542736, 2.010271, 2.946280",\ + "1.915508, 2.179092, 2.454377, 2.921913, 3.857924",\ + "0.708369, 0.975092, 1.248881, 1.716190, 2.651795",\ + "0.738189, 1.004912, 1.278701, 1.746009, 2.681615",\ + "0.809913, 1.076636, 1.350425, 1.817733, 2.753339",\ + "1.066364, 1.333087, 1.606875, 2.074184, 3.009789",\ + "1.978004, 2.244727, 2.518517, 2.985826, 3.921433",\ + "1.037495, 1.339423, 1.600748, 2.065540, 2.997252",\ + "1.067314, 1.369243, 1.630568, 2.095359, 3.027071",\ + "1.139038, 1.440967, 1.702292, 2.167083, 3.098795",\ + "1.395489, 1.697417, 1.958743, 2.423534, 3.355246",\ + "2.307129, 2.609058, 2.870384, 3.335176, 4.266890"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.047100, 0.047100, 0.047099, 0.047099, 0.047099",\ + "0.093802, 0.093802, 0.093802, 0.093802, 0.093802",\ + "0.225237, 0.225237, 0.225237, 0.225237, 0.225236",\ + "0.723332, 0.723332, 0.723330, 0.723327, 0.723319",\ + "2.463217, 2.463217, 2.463218, 2.463218, 2.463218",\ + "0.047100, 0.047100, 0.047099, 0.047099, 0.047099",\ + "0.093802, 0.093802, 0.093802, 0.093802, 0.093802",\ + "0.225237, 0.225237, 0.225237, 0.225237, 0.225236",\ + "0.723332, 0.723332, 0.723330, 0.723327, 0.723319",\ + "2.463217, 2.463217, 2.463218, 2.463218, 2.463218",\ + "0.047100, 0.047100, 0.047099, 0.047099, 0.047099",\ + "0.093802, 0.093802, 0.093802, 0.093802, 0.093802",\ + "0.225237, 0.225237, 0.225237, 0.225237, 0.225236",\ + "0.723332, 0.723332, 0.723330, 0.723327, 0.723319",\ + "2.463217, 2.463217, 2.463218, 2.463218, 2.463218",\ + "0.047100, 0.047100, 0.047099, 0.047099, 0.047099",\ + "0.093802, 0.093802, 0.093802, 0.093802, 0.093802",\ + "0.225237, 0.225237, 0.225237, 0.225237, 0.225236",\ + "0.723332, 0.723332, 0.723330, 0.723327, 0.723319",\ + "2.463217, 2.463217, 2.463218, 2.463218, 2.463218",\ + "0.047100, 0.047100, 0.047099, 0.047099, 0.047099",\ + "0.093802, 0.093802, 0.093802, 0.093802, 0.093802",\ + "0.225237, 0.225237, 0.225237, 0.225237, 0.225236",\ + "0.723332, 0.723332, 0.723330, 0.723327, 0.723319",\ + "2.463217, 2.463218, 2.463218, 2.463218, 2.463218"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.414387, 0.596819, 0.793211, 1.102263, 1.697070",\ + "0.438785, 0.621217, 0.817609, 1.126662, 1.721470",\ + "0.489809, 0.672241, 0.868633, 1.177686, 1.772493",\ + "0.656588, 0.839020, 1.035412, 1.344465, 1.939272",\ + "1.244182, 1.426614, 1.623006, 1.932059, 2.526866",\ + "0.501801, 0.684204, 0.880704, 1.189568, 1.784423",\ + "0.526200, 0.708603, 0.905102, 1.213968, 1.808823",\ + "0.577224, 0.759627, 0.956126, 1.264991, 1.859847",\ + "0.744003, 0.926405, 1.122905, 1.431770, 2.026625",\ + "1.331597, 1.513999, 1.710499, 2.019364, 2.614220",\ + "0.582678, 0.764541, 0.960731, 1.269597, 1.864455",\ + "0.607077, 0.788939, 0.985129, 1.293996, 1.888855",\ + "0.658100, 0.839963, 1.036153, 1.345020, 1.939878",\ + "0.824879, 1.006742, 1.202932, 1.511798, 2.106657",\ + "1.412473, 1.594336, 1.790526, 2.099392, 2.694252",\ + "0.640324, 0.822089, 1.018274, 1.326842, 1.921102",\ + "0.664723, 0.846488, 1.042673, 1.351241, 1.945503",\ + "0.715747, 0.897512, 1.093697, 1.402265, 1.996526",\ + "0.882525, 1.064290, 1.260476, 1.569043, 2.163304",\ + "1.470119, 1.651884, 1.848070, 2.156638, 2.750899",\ + "0.942532, 1.127314, 1.321908, 1.629857, 2.222949",\ + "0.966931, 1.151712, 1.346307, 1.654256, 2.247349",\ + "1.017955, 1.202736, 1.397331, 1.705280, 2.298373",\ + "1.184733, 1.369515, 1.564109, 1.872058, 2.465151",\ + "1.772327, 1.957109, 2.151703, 2.459652, 3.052746"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.045359, 0.045359, 0.045359, 0.045359, 0.045359",\ + "0.074479, 0.074479, 0.074479, 0.074479, 0.074479",\ + "0.150687, 0.150687, 0.150687, 0.150687, 0.150687",\ + "0.448891, 0.448891, 0.448891, 0.448891, 0.448891",\ + "1.523991, 1.523991, 1.523991, 1.523992, 1.523996",\ + "0.045359, 0.045359, 0.045359, 0.045359, 0.045359",\ + "0.074479, 0.074479, 0.074479, 0.074479, 0.074479",\ + "0.150687, 0.150687, 0.150687, 0.150687, 0.150687",\ + "0.448891, 0.448891, 0.448891, 0.448891, 0.448891",\ + "1.523991, 1.523991, 1.523991, 1.523992, 1.523996",\ + "0.045359, 0.045359, 0.045359, 0.045359, 0.045359",\ + "0.074479, 0.074479, 0.074479, 0.074479, 0.074479",\ + "0.150687, 0.150687, 0.150687, 0.150687, 0.150687",\ + "0.448891, 0.448891, 0.448891, 0.448891, 0.448891",\ + "1.523991, 1.523991, 1.523991, 1.523992, 1.523996",\ + "0.045359, 0.045359, 0.045359, 0.045359, 0.045359",\ + "0.074479, 0.074479, 0.074479, 0.074479, 0.074479",\ + "0.150687, 0.150687, 0.150687, 0.150687, 0.150687",\ + "0.448891, 0.448891, 0.448891, 0.448891, 0.448891",\ + "1.523991, 1.523991, 1.523991, 1.523992, 1.523996",\ + "0.045359, 0.045359, 0.045359, 0.045359, 0.045359",\ + "0.074479, 0.074479, 0.074479, 0.074479, 0.074479",\ + "0.150687, 0.150687, 0.150687, 0.150687, 0.150687",\ + "0.448891, 0.448891, 0.448891, 0.448891, 0.448891",\ + "1.523991, 1.523991, 1.523991, 1.523992, 1.523996"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[5]_redg_2657*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[2]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.465387, 0.725016, 0.996889, 1.453768, 2.367528",\ + "0.495207, 0.754836, 1.026708, 1.483588, 2.397348",\ + "0.566931, 0.826560, 1.098432, 1.555312, 2.469071",\ + "0.823382, 1.083011, 1.354883, 1.811763, 2.725522",\ + "1.735022, 1.994652, 2.266525, 2.723405, 3.637165",\ + "0.553492, 0.812550, 1.084419, 1.540484, 2.453462",\ + "0.583312, 0.842370, 1.114239, 1.570303, 2.483281",\ + "0.655036, 0.914094, 1.185963, 1.642027, 2.555005",\ + "0.911487, 1.170545, 1.442413, 1.898478, 2.811456",\ + "1.823127, 2.082185, 2.354055, 2.810120, 3.723099",\ + "0.641522, 0.901516, 1.172383, 1.628106, 2.540417",\ + "0.671342, 0.931335, 1.202203, 1.657926, 2.570236",\ + "0.743066, 1.003059, 1.273927, 1.729650, 2.641960",\ + "0.999517, 1.259510, 1.530378, 1.986101, 2.898411",\ + "1.911157, 2.171151, 2.442019, 2.897743, 3.810054",\ + "0.703743, 0.967129, 1.236521, 1.692020, 2.603926",\ + "0.733563, 0.996949, 1.266341, 1.721840, 2.633745",\ + "0.805287, 1.068673, 1.338065, 1.793564, 2.705469",\ + "1.061738, 1.325124, 1.594516, 2.050014, 2.961920",\ + "1.973378, 2.236765, 2.506157, 2.961657, 3.873563",\ + "1.031131, 1.331204, 1.588269, 2.041321, 2.949382",\ + "1.060951, 1.361024, 1.618088, 2.071141, 2.979202",\ + "1.132675, 1.432748, 1.689812, 2.142864, 3.050925",\ + "1.389125, 1.689199, 1.946263, 2.399315, 3.307376",\ + "2.300766, 2.600840, 2.857904, 3.310957, 4.219019"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.047100, 0.047100, 0.047099, 0.047099, 0.047099",\ + "0.093802, 0.093802, 0.093802, 0.093802, 0.093802",\ + "0.225237, 0.225237, 0.225237, 0.225237, 0.225236",\ + "0.723332, 0.723332, 0.723329, 0.723323, 0.723311",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.047100, 0.047100, 0.047099, 0.047099, 0.047099",\ + "0.093802, 0.093802, 0.093802, 0.093802, 0.093802",\ + "0.225237, 0.225237, 0.225237, 0.225237, 0.225236",\ + "0.723332, 0.723331, 0.723329, 0.723323, 0.723311",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.047100, 0.047100, 0.047099, 0.047099, 0.047099",\ + "0.093802, 0.093802, 0.093802, 0.093802, 0.093802",\ + "0.225237, 0.225237, 0.225237, 0.225237, 0.225236",\ + "0.723332, 0.723331, 0.723329, 0.723323, 0.723311",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.047100, 0.047100, 0.047099, 0.047099, 0.047099",\ + "0.093802, 0.093802, 0.093802, 0.093802, 0.093802",\ + "0.225237, 0.225237, 0.225237, 0.225237, 0.225236",\ + "0.723332, 0.723331, 0.723329, 0.723323, 0.723311",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.047100, 0.047099, 0.047099, 0.047099, 0.047099",\ + "0.093802, 0.093802, 0.093802, 0.093802, 0.093802",\ + "0.225237, 0.225237, 0.225237, 0.225237, 0.225236",\ + "0.723332, 0.723331, 0.723329, 0.723323, 0.723311",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.412725, 0.595266, 0.791521, 1.100738, 1.696032",\ + "0.437124, 0.619665, 0.815920, 1.125137, 1.720433",\ + "0.488148, 0.670689, 0.866944, 1.176161, 1.771456",\ + "0.654926, 0.837467, 1.033722, 1.342939, 1.938234",\ + "1.242520, 1.425061, 1.621316, 1.930533, 2.525829",\ + "0.500145, 0.682652, 0.879014, 1.188043, 1.783386",\ + "0.524544, 0.707050, 0.903413, 1.212442, 1.807786",\ + "0.575568, 0.758074, 0.954436, 1.263466, 1.858810",\ + "0.742347, 0.924853, 1.121215, 1.430244, 2.025588",\ + "1.329941, 1.512447, 1.708809, 2.017838, 2.613183",\ + "0.581013, 0.762988, 0.959041, 1.268071, 1.863418",\ + "0.605412, 0.787387, 0.983440, 1.292470, 1.887818",\ + "0.656435, 0.838411, 1.034463, 1.343494, 1.938841",\ + "0.823214, 1.005190, 1.201242, 1.510273, 2.105619",\ + "1.410808, 1.592784, 1.788836, 2.097867, 2.693214",\ + "0.638652, 0.820537, 1.016585, 1.325316, 1.920065",\ + "0.663050, 0.844936, 1.040983, 1.349715, 1.944465",\ + "0.714074, 0.895960, 1.092007, 1.400739, 1.995489",\ + "0.880853, 1.062738, 1.258786, 1.567518, 2.162267",\ + "1.468447, 1.650332, 1.846380, 2.155112, 2.749862",\ + "0.940747, 1.125763, 1.320219, 1.628331, 2.221912",\ + "0.965146, 1.150162, 1.344617, 1.652730, 2.246312",\ + "1.016169, 1.201186, 1.395641, 1.703754, 2.297336",\ + "1.182948, 1.367965, 1.562420, 1.870533, 2.464114",\ + "1.770542, 1.955559, 2.150014, 2.458127, 3.051709"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.045359, 0.045359, 0.045359, 0.045359, 0.045359",\ + "0.074479, 0.074479, 0.074479, 0.074479, 0.074479",\ + "0.150687, 0.150687, 0.150687, 0.150687, 0.150687",\ + "0.448891, 0.448891, 0.448891, 0.448891, 0.448891",\ + "1.523991, 1.523991, 1.523991, 1.523993, 1.523996",\ + "0.045359, 0.045359, 0.045359, 0.045359, 0.045359",\ + "0.074479, 0.074479, 0.074479, 0.074479, 0.074479",\ + "0.150687, 0.150687, 0.150687, 0.150687, 0.150687",\ + "0.448891, 0.448891, 0.448891, 0.448891, 0.448891",\ + "1.523991, 1.523991, 1.523991, 1.523993, 1.523996",\ + "0.045359, 0.045359, 0.045359, 0.045359, 0.045359",\ + "0.074479, 0.074479, 0.074479, 0.074479, 0.074479",\ + "0.150687, 0.150687, 0.150687, 0.150687, 0.150687",\ + "0.448891, 0.448891, 0.448891, 0.448891, 0.448891",\ + "1.523991, 1.523991, 1.523991, 1.523993, 1.523996",\ + "0.045359, 0.045359, 0.045359, 0.045359, 0.045359",\ + "0.074479, 0.074479, 0.074479, 0.074479, 0.074479",\ + "0.150687, 0.150687, 0.150687, 0.150687, 0.150687",\ + "0.448891, 0.448891, 0.448891, 0.448891, 0.448891",\ + "1.523991, 1.523991, 1.523991, 1.523993, 1.523996",\ + "0.045359, 0.045359, 0.045359, 0.045359, 0.045359",\ + "0.074479, 0.074479, 0.074479, 0.074479, 0.074479",\ + "0.150687, 0.150687, 0.150687, 0.150687, 0.150687",\ + "0.448891, 0.448891, 0.448891, 0.448891, 0.448891",\ + "1.523991, 1.523991, 1.523991, 1.523993, 1.523996"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[5]_redg_2600*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[3]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.557671, 0.736098, 0.916358, 1.202564, 1.753681",\ + "0.587491, 0.765917, 0.946178, 1.232384, 1.783501",\ + "0.659215, 0.837641, 1.017902, 1.304108, 1.855225",\ + "0.915666, 1.094092, 1.274353, 1.560559, 2.111676",\ + "1.827306, 2.005732, 2.185993, 2.472199, 3.023316",\ + "0.642609, 0.821370, 1.002273, 1.288485, 1.840060",\ + "0.672429, 0.851190, 1.032093, 1.318304, 1.869879",\ + "0.744153, 0.922914, 1.103817, 1.390028, 1.941603",\ + "1.000604, 1.179365, 1.360268, 1.646479, 2.198054",\ + "1.912244, 2.091005, 2.271908, 2.558120, 3.109695",\ + "0.718516, 0.896813, 1.077082, 1.363081, 1.914232",\ + "0.748335, 0.926633, 1.106902, 1.392901, 1.944052",\ + "0.820059, 0.998357, 1.178626, 1.464625, 2.015776",\ + "1.076510, 1.254808, 1.435077, 1.721076, 2.272227",\ + "1.988150, 2.166448, 2.346717, 2.632716, 3.183867",\ + "0.772868, 0.951325, 1.131733, 1.417621, 1.968549",\ + "0.802687, 0.981145, 1.161553, 1.447441, 1.998369",\ + "0.874411, 1.052869, 1.233277, 1.519165, 2.070093",\ + "1.130862, 1.309320, 1.489728, 1.775616, 2.326544",\ + "2.042502, 2.220960, 2.401368, 2.687256, 3.238184",\ + "1.054290, 1.236552, 1.415684, 1.701348, 2.251827",\ + "1.084109, 1.266372, 1.445503, 1.731167, 2.281647",\ + "1.155833, 1.338096, 1.517227, 1.802891, 2.353371",\ + "1.412284, 1.594547, 1.773678, 2.059342, 2.609822",\ + "2.323924, 2.506187, 2.685318, 2.970982, 3.521462"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.047100, 0.047100, 0.047100, 0.047100, 0.047100",\ + "0.093802, 0.093802, 0.093802, 0.093802, 0.093802",\ + "0.225237, 0.225237, 0.225237, 0.225237, 0.225237",\ + "0.723332, 0.723332, 0.723332, 0.723332, 0.723332",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.047100, 0.047100, 0.047100, 0.047100, 0.047100",\ + "0.093802, 0.093802, 0.093802, 0.093802, 0.093802",\ + "0.225237, 0.225237, 0.225237, 0.225237, 0.225237",\ + "0.723332, 0.723332, 0.723332, 0.723332, 0.723332",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.047100, 0.047100, 0.047100, 0.047100, 0.047100",\ + "0.093802, 0.093802, 0.093802, 0.093802, 0.093802",\ + "0.225237, 0.225237, 0.225237, 0.225237, 0.225237",\ + "0.723332, 0.723332, 0.723332, 0.723332, 0.723332",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.047100, 0.047100, 0.047100, 0.047100, 0.047100",\ + "0.093802, 0.093802, 0.093802, 0.093802, 0.093802",\ + "0.225237, 0.225237, 0.225237, 0.225237, 0.225237",\ + "0.723332, 0.723332, 0.723332, 0.723332, 0.723332",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.047100, 0.047100, 0.047100, 0.047100, 0.047100",\ + "0.093802, 0.093802, 0.093802, 0.093802, 0.093802",\ + "0.225237, 0.225237, 0.225237, 0.225237, 0.225237",\ + "0.723332, 0.723332, 0.723332, 0.723332, 0.723332",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.429998, 0.695167, 0.954369, 1.390552, 2.262917",\ + "0.454396, 0.719566, 0.978768, 1.414950, 2.287315",\ + "0.505420, 0.770590, 1.029792, 1.465974, 2.338339",\ + "0.672199, 0.937369, 1.196570, 1.632753, 2.505118",\ + "1.259793, 1.524963, 1.784164, 2.220347, 3.092712",\ + "0.518663, 0.783242, 1.043010, 1.478781, 2.350322",\ + "0.543062, 0.807641, 1.067409, 1.503179, 2.374721",\ + "0.594086, 0.858665, 1.118433, 1.554203, 2.425745",\ + "0.760864, 1.025444, 1.285211, 1.720982, 2.592523",\ + "1.348459, 1.613038, 1.872805, 2.308576, 3.180117",\ + "0.611470, 0.876365, 1.134735, 1.570945, 2.443364",\ + "0.635869, 0.900764, 1.159134, 1.595343, 2.467762",\ + "0.686893, 0.951788, 1.210158, 1.646367, 2.518786",\ + "0.853671, 1.118567, 1.376937, 1.813146, 2.685565",\ + "1.441265, 1.706161, 1.964531, 2.400740, 3.273159",\ + "0.677192, 0.944899, 1.201755, 1.637795, 2.509875",\ + "0.701591, 0.969298, 1.226154, 1.662194, 2.534274",\ + "0.752615, 1.020322, 1.277178, 1.713217, 2.585298",\ + "0.919394, 1.187101, 1.443956, 1.879996, 2.752076",\ + "1.506988, 1.774695, 2.031551, 2.467590, 3.339670",\ + "1.022982, 1.325398, 1.572386, 2.006926, 2.876008",\ + "1.047381, 1.349797, 1.596784, 2.031325, 2.900407",\ + "1.098405, 1.400820, 1.647808, 2.082349, 2.951431",\ + "1.265183, 1.567599, 1.814587, 2.249127, 3.118209",\ + "1.852777, 2.155193, 2.402181, 2.836721, 3.705803"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.045359, 0.045359, 0.045359, 0.045359, 0.045359",\ + "0.074479, 0.074479, 0.074479, 0.074479, 0.074479",\ + "0.150687, 0.150687, 0.150687, 0.150687, 0.150687",\ + "0.448891, 0.448891, 0.448891, 0.448891, 0.448891",\ + "1.523991, 1.523991, 1.523991, 1.523991, 1.523991",\ + "0.045359, 0.045359, 0.045359, 0.045359, 0.045359",\ + "0.074479, 0.074479, 0.074479, 0.074479, 0.074479",\ + "0.150687, 0.150687, 0.150687, 0.150687, 0.150687",\ + "0.448891, 0.448891, 0.448891, 0.448891, 0.448891",\ + "1.523991, 1.523991, 1.523991, 1.523991, 1.523991",\ + "0.045359, 0.045359, 0.045359, 0.045359, 0.045359",\ + "0.074479, 0.074479, 0.074479, 0.074479, 0.074479",\ + "0.150687, 0.150687, 0.150687, 0.150687, 0.150687",\ + "0.448891, 0.448891, 0.448891, 0.448891, 0.448891",\ + "1.523991, 1.523991, 1.523991, 1.523991, 1.523991",\ + "0.045359, 0.045359, 0.045359, 0.045359, 0.045359",\ + "0.074479, 0.074479, 0.074479, 0.074479, 0.074479",\ + "0.150687, 0.150687, 0.150687, 0.150687, 0.150687",\ + "0.448891, 0.448891, 0.448891, 0.448891, 0.448891",\ + "1.523991, 1.523991, 1.523991, 1.523991, 1.523991",\ + "0.045359, 0.045359, 0.045359, 0.045359, 0.045359",\ + "0.074479, 0.074479, 0.074479, 0.074479, 0.074479",\ + "0.150687, 0.150687, 0.150687, 0.150687, 0.150687",\ + "0.448891, 0.448891, 0.448891, 0.448891, 0.448891",\ + "1.523991, 1.523991, 1.523991, 1.523991, 1.523991"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[5]_redg_2542*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + values ( "0.324944, 0.354764, 0.426488, 0.682940, 1.594576",\ + "0.412335, 0.442155, 0.513879, 0.770331, 1.681967",\ + "0.493254, 0.523074, 0.594798, 0.851250, 1.762885",\ + "0.550995, 0.580814, 0.652539, 0.908991, 1.820623",\ + "0.854260, 0.883835, 0.955245, 1.211697, 2.123717"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + values ( "0.047100, 0.093803, 0.225238, 0.723294, 2.463217",\ + "0.047100, 0.093803, 0.225317, 0.723294, 2.463217",\ + "0.047100, 0.093803, 0.225549, 0.723294, 2.463317",\ + "0.047101, 0.093803, 0.225549, 0.723294, 2.463317",\ + "0.047256, 0.093828, 0.225883, 0.723320, 2.463779"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + values ( "0.309881, 0.334280, 0.385304, 0.552083, 1.139677",\ + "0.397274, 0.421673, 0.472696, 0.639475, 1.227069",\ + "0.478143, 0.502542, 0.553566, 0.720345, 1.307939",\ + "0.535792, 0.560191, 0.611215, 0.777993, 1.365587",\ + "0.838449, 0.862847, 0.913871, 1.080650, 1.668244"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + values ( "0.045359, 0.074479, 0.150693, 0.448891, 1.524390",\ + "0.045359, 0.074479, 0.150693, 0.448891, 1.524390",\ + "0.045359, 0.074479, 0.150693, 0.448891, 1.524264",\ + "0.045359, 0.074479, 0.150693, 0.448891, 1.524028",\ + "0.045353, 0.074413, 0.150693, 0.448886, 1.523991"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[5]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[0]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.517919, 0.698033, 0.885611, 1.187591, 1.770688",\ + "0.546784, 0.726898, 0.914476, 1.216456, 1.799552",\ + "0.617826, 0.797940, 0.985519, 1.287498, 1.870595",\ + "0.874029, 1.054142, 1.241721, 1.543701, 2.126797",\ + "1.786688, 1.966801, 2.154380, 2.456360, 3.039456",\ + "0.602858, 0.782869, 0.970682, 1.273098, 1.857066",\ + "0.631723, 0.811734, 0.999546, 1.301962, 1.885931",\ + "0.702765, 0.882776, 1.070589, 1.373005, 1.956973",\ + "0.958967, 1.138978, 1.326791, 1.629207, 2.213175",\ + "1.871626, 2.051637, 2.239450, 2.541866, 3.125834",\ + "0.678770, 0.858312, 1.045491, 1.347694, 1.931238",\ + "0.707635, 0.887177, 1.074355, 1.376559, 1.960103",\ + "0.778677, 0.958219, 1.145398, 1.447601, 2.031145",\ + "1.034879, 1.214422, 1.401600, 1.703804, 2.287347",\ + "1.947538, 2.127081, 2.314259, 2.616463, 3.200006",\ + "0.733139, 0.913064, 1.100379, 1.402300, 1.985556",\ + "0.762004, 0.941928, 1.129244, 1.431165, 2.014421",\ + "0.833046, 1.012970, 1.200286, 1.502207, 2.085463",\ + "1.089248, 1.269173, 1.456489, 1.758409, 2.341665",\ + "2.001907, 2.181832, 2.369148, 2.671068, 3.254324",\ + "1.014734, 1.198629, 1.384555, 1.686026, 2.268833",\ + "1.043599, 1.227494, 1.413420, 1.714891, 2.297698",\ + "1.114641, 1.298536, 1.484462, 1.785933, 2.368740",\ + "1.370843, 1.554738, 1.740664, 2.042135, 2.624942",\ + "2.283502, 2.467397, 2.653323, 2.954794, 3.537601"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.043742, 0.043742, 0.043742, 0.043742, 0.043742",\ + "0.091388, 0.091388, 0.091388, 0.091388, 0.091388",\ + "0.223754, 0.223754, 0.223754, 0.223754, 0.223754",\ + "0.713686, 0.713686, 0.713686, 0.713686, 0.713686",\ + "2.456796, 2.456796, 2.456796, 2.456796, 2.456796",\ + "0.043742, 0.043742, 0.043742, 0.043742, 0.043742",\ + "0.091388, 0.091388, 0.091388, 0.091388, 0.091388",\ + "0.223754, 0.223754, 0.223754, 0.223754, 0.223754",\ + "0.713686, 0.713686, 0.713686, 0.713686, 0.713686",\ + "2.456796, 2.456796, 2.456796, 2.456796, 2.456796",\ + "0.043742, 0.043742, 0.043742, 0.043742, 0.043742",\ + "0.091388, 0.091388, 0.091388, 0.091388, 0.091388",\ + "0.223754, 0.223754, 0.223754, 0.223754, 0.223754",\ + "0.713686, 0.713686, 0.713686, 0.713686, 0.713686",\ + "2.456796, 2.456796, 2.456796, 2.456796, 2.456796",\ + "0.043742, 0.043742, 0.043742, 0.043742, 0.043742",\ + "0.091388, 0.091388, 0.091388, 0.091388, 0.091388",\ + "0.223754, 0.223754, 0.223754, 0.223754, 0.223754",\ + "0.713686, 0.713686, 0.713686, 0.713686, 0.713686",\ + "2.456796, 2.456796, 2.456796, 2.456796, 2.456796",\ + "0.043742, 0.043742, 0.043742, 0.043742, 0.043742",\ + "0.091388, 0.091388, 0.091388, 0.091388, 0.091388",\ + "0.223754, 0.223754, 0.223754, 0.223754, 0.223754",\ + "0.713686, 0.713686, 0.713686, 0.713686, 0.713686",\ + "2.456796, 2.456796, 2.456796, 2.456796, 2.456796"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.390477, 0.658088, 0.919489, 1.359266, 2.238427",\ + "0.413219, 0.680829, 0.942230, 1.382007, 2.261168",\ + "0.462500, 0.730110, 0.991511, 1.431288, 2.310449",\ + "0.628402, 0.896013, 1.157414, 1.597191, 2.476352",\ + "1.214556, 1.482167, 1.743568, 2.183345, 3.062506",\ + "0.479181, 0.746163, 1.008130, 1.447495, 2.325832",\ + "0.501923, 0.768904, 1.030871, 1.470236, 2.348573",\ + "0.551204, 0.818185, 1.080152, 1.519517, 2.397854",\ + "0.717106, 0.984088, 1.246055, 1.685420, 2.563757",\ + "1.303261, 1.570242, 1.832209, 2.271574, 3.149911",\ + "0.572124, 0.839483, 1.100174, 1.539741, 2.418874",\ + "0.594865, 0.862224, 1.122916, 1.562482, 2.441615",\ + "0.644146, 0.911506, 1.172197, 1.611763, 2.490896",\ + "0.810049, 1.077408, 1.338099, 1.777666, 2.656799",\ + "1.396203, 1.663562, 1.924254, 2.363820, 3.242953",\ + "0.637967, 0.908047, 1.167230, 1.606752, 2.485795",\ + "0.660708, 0.930789, 1.189972, 1.629493, 2.508537",\ + "0.709990, 0.980070, 1.239253, 1.678774, 2.557818",\ + "0.875892, 1.145972, 1.405155, 1.844677, 2.723721",\ + "1.462046, 1.732126, 1.991310, 2.430831, 3.309875",\ + "0.984489, 1.288883, 1.537901, 1.975978, 2.852131",\ + "1.007230, 1.311624, 1.560642, 1.998719, 2.874872",\ + "1.056511, 1.360905, 1.609924, 2.048000, 2.924153",\ + "1.222414, 1.526808, 1.775826, 2.213903, 3.090056",\ + "1.808568, 2.112962, 2.361980, 2.800057, 3.676210"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.037338, 0.037338, 0.037338, 0.037338, 0.037338",\ + "0.066008, 0.066008, 0.066008, 0.066008, 0.066008",\ + "0.143978, 0.143978, 0.143978, 0.143978, 0.143978",\ + "0.444353, 0.444353, 0.444354, 0.444354, 0.444354",\ + "1.518979, 1.518979, 1.518979, 1.518979, 1.518979",\ + "0.037338, 0.037338, 0.037338, 0.037338, 0.037338",\ + "0.066008, 0.066008, 0.066008, 0.066008, 0.066008",\ + "0.143978, 0.143978, 0.143978, 0.143978, 0.143978",\ + "0.444353, 0.444353, 0.444354, 0.444354, 0.444354",\ + "1.518979, 1.518979, 1.518979, 1.518979, 1.518979",\ + "0.037338, 0.037338, 0.037338, 0.037338, 0.037338",\ + "0.066008, 0.066008, 0.066008, 0.066008, 0.066008",\ + "0.143978, 0.143978, 0.143978, 0.143978, 0.143978",\ + "0.444353, 0.444353, 0.444354, 0.444354, 0.444354",\ + "1.518979, 1.518979, 1.518979, 1.518979, 1.518979",\ + "0.037338, 0.037338, 0.037338, 0.037338, 0.037338",\ + "0.066008, 0.066008, 0.066008, 0.066008, 0.066008",\ + "0.143978, 0.143978, 0.143978, 0.143978, 0.143978",\ + "0.444353, 0.444353, 0.444354, 0.444354, 0.444354",\ + "1.518979, 1.518979, 1.518979, 1.518979, 1.518979",\ + "0.037338, 0.037338, 0.037338, 0.037338, 0.037338",\ + "0.066008, 0.066008, 0.066008, 0.066008, 0.066008",\ + "0.143978, 0.143978, 0.143978, 0.143978, 0.143978",\ + "0.444353, 0.444353, 0.444354, 0.444354, 0.444354",\ + "1.518979, 1.518979, 1.518979, 1.518979, 1.518979"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[5]_redg_min_2483*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[1]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.426028, 0.689559, 0.965679, 1.433811, 2.368817",\ + "0.454893, 0.718424, 0.994544, 1.462676, 2.397682",\ + "0.525935, 0.789466, 1.065586, 1.533718, 2.468724",\ + "0.782137, 1.045668, 1.321788, 1.789921, 2.724926",\ + "1.694796, 1.958328, 2.234447, 2.702580, 3.637585",\ + "0.514222, 0.777100, 1.053246, 1.520527, 2.454750",\ + "0.543087, 0.805965, 1.082111, 1.549392, 2.483615",\ + "0.614129, 0.877007, 1.153153, 1.620434, 2.554657",\ + "0.870331, 1.133209, 1.409355, 1.876636, 2.810860",\ + "1.782991, 2.045868, 2.322014, 2.789295, 3.723519",\ + "0.602538, 0.866079, 1.141211, 1.608167, 2.541705",\ + "0.631403, 0.894944, 1.170076, 1.637032, 2.570570",\ + "0.702445, 0.965986, 1.241118, 1.708074, 2.641613",\ + "0.958647, 1.222188, 1.497320, 1.964276, 2.897815",\ + "1.871307, 2.134848, 2.409979, 2.876935, 3.810474",\ + "0.665034, 0.931713, 1.205350, 1.672256, 2.605214",\ + "0.693899, 0.960578, 1.234215, 1.701121, 2.634079",\ + "0.764941, 1.031620, 1.305257, 1.772163, 2.705122",\ + "1.021144, 1.287822, 1.561460, 2.028365, 2.961324",\ + "1.933803, 2.200481, 2.474119, 2.941024, 3.873983",\ + "0.994160, 1.296028, 1.557214, 2.021699, 2.950670",\ + "1.023025, 1.324893, 1.586079, 2.050565, 2.979536",\ + "1.094067, 1.395935, 1.657121, 2.121607, 3.050578",\ + "1.350269, 1.652137, 1.913324, 2.377809, 3.306780",\ + "2.262928, 2.564796, 2.825983, 3.290468, 4.219439"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.043742, 0.043742, 0.043742, 0.043742, 0.043743",\ + "0.091388, 0.091388, 0.091388, 0.091388, 0.091389",\ + "0.223754, 0.223754, 0.223754, 0.223755, 0.223756",\ + "0.713686, 0.713686, 0.713687, 0.713690, 0.713695",\ + "2.456796, 2.456796, 2.456794, 2.456788, 2.456778",\ + "0.043742, 0.043742, 0.043742, 0.043742, 0.043743",\ + "0.091388, 0.091388, 0.091388, 0.091388, 0.091389",\ + "0.223754, 0.223754, 0.223754, 0.223755, 0.223756",\ + "0.713686, 0.713686, 0.713687, 0.713690, 0.713695",\ + "2.456796, 2.456796, 2.456794, 2.456788, 2.456778",\ + "0.043742, 0.043742, 0.043742, 0.043742, 0.043743",\ + "0.091388, 0.091388, 0.091388, 0.091388, 0.091389",\ + "0.223754, 0.223754, 0.223754, 0.223755, 0.223756",\ + "0.713686, 0.713686, 0.713687, 0.713690, 0.713695",\ + "2.456796, 2.456796, 2.456794, 2.456788, 2.456778",\ + "0.043742, 0.043742, 0.043742, 0.043742, 0.043743",\ + "0.091388, 0.091388, 0.091388, 0.091388, 0.091389",\ + "0.223754, 0.223754, 0.223754, 0.223755, 0.223756",\ + "0.713686, 0.713686, 0.713687, 0.713690, 0.713695",\ + "2.456796, 2.456796, 2.456794, 2.456788, 2.456778",\ + "0.043742, 0.043742, 0.043742, 0.043742, 0.043743",\ + "0.091388, 0.091388, 0.091388, 0.091388, 0.091389",\ + "0.223754, 0.223754, 0.223754, 0.223755, 0.223756",\ + "0.713686, 0.713686, 0.713687, 0.713690, 0.713695",\ + "2.456796, 2.456796, 2.456794, 2.456788, 2.456778"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.373432, 0.555490, 0.751724, 1.060905, 1.655389",\ + "0.396174, 0.578231, 0.774465, 1.083646, 1.678130",\ + "0.445455, 0.627512, 0.823746, 1.132927, 1.727411",\ + "0.611357, 0.793415, 0.989649, 1.298831, 1.893319",\ + "1.197512, 1.379569, 1.575803, 1.884983, 2.479466",\ + "0.460847, 0.642809, 0.839005, 1.148210, 1.742743",\ + "0.483588, 0.665550, 0.861746, 1.170951, 1.765483",\ + "0.532870, 0.714831, 0.911027, 1.220232, 1.814765",\ + "0.698772, 0.880733, 1.076930, 1.386137, 1.980672",\ + "1.284926, 1.466888, 1.663084, 1.972288, 2.566819",\ + "0.541724, 0.723145, 0.919032, 1.228239, 1.822774",\ + "0.564465, 0.745886, 0.941773, 1.250980, 1.845515",\ + "0.613746, 0.795168, 0.991054, 1.300261, 1.894796",\ + "0.779648, 0.961070, 1.156957, 1.466165, 2.060704",\ + "1.365803, 1.547224, 1.743111, 2.052317, 2.646851",\ + "0.599370, 0.780982, 0.976767, 1.285709, 1.879870",\ + "0.622111, 0.803723, 0.999508, 1.308450, 1.902611",\ + "0.671392, 0.853004, 1.048790, 1.357731, 1.951892",\ + "0.837295, 1.018907, 1.214692, 1.523636, 2.117800",\ + "1.423449, 1.605061, 1.800846, 2.109787, 2.703947",\ + "0.901578, 1.086359, 1.280431, 1.588916, 2.182188",\ + "0.924319, 1.109100, 1.303172, 1.611657, 2.204929",\ + "0.973600, 1.158382, 1.352453, 1.660938, 2.254210",\ + "1.139503, 1.324284, 1.518356, 1.826843, 2.420118",\ + "1.725657, 1.910438, 2.104510, 2.412994, 3.006265"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.037337, 0.037337, 0.037337, 0.037337, 0.037337",\ + "0.066008, 0.066008, 0.066008, 0.066008, 0.066009",\ + "0.143976, 0.143976, 0.143976, 0.143976, 0.143976",\ + "0.444332, 0.444332, 0.444332, 0.444332, 0.444332",\ + "1.518979, 1.518979, 1.518979, 1.518980, 1.518981",\ + "0.037337, 0.037337, 0.037337, 0.037337, 0.037337",\ + "0.066008, 0.066008, 0.066008, 0.066008, 0.066009",\ + "0.143976, 0.143976, 0.143976, 0.143976, 0.143976",\ + "0.444332, 0.444332, 0.444332, 0.444332, 0.444332",\ + "1.518979, 1.518979, 1.518979, 1.518980, 1.518981",\ + "0.037337, 0.037337, 0.037337, 0.037337, 0.037337",\ + "0.066008, 0.066008, 0.066008, 0.066008, 0.066009",\ + "0.143976, 0.143976, 0.143976, 0.143976, 0.143976",\ + "0.444332, 0.444332, 0.444332, 0.444332, 0.444332",\ + "1.518979, 1.518979, 1.518979, 1.518980, 1.518981",\ + "0.037337, 0.037337, 0.037337, 0.037337, 0.037337",\ + "0.066008, 0.066008, 0.066008, 0.066008, 0.066009",\ + "0.143976, 0.143976, 0.143976, 0.143976, 0.143976",\ + "0.444332, 0.444332, 0.444332, 0.444332, 0.444332",\ + "1.518979, 1.518979, 1.518979, 1.518980, 1.518981",\ + "0.037337, 0.037337, 0.037337, 0.037337, 0.037337",\ + "0.066008, 0.066008, 0.066008, 0.066008, 0.066009",\ + "0.143976, 0.143976, 0.143976, 0.143976, 0.143976",\ + "0.444332, 0.444332, 0.444332, 0.444332, 0.444332",\ + "1.518979, 1.518979, 1.518979, 1.518980, 1.518981"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[5]_redg_min_2405*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[2]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.422050, 0.681609, 0.953245, 1.409407, 2.320577",\ + "0.450915, 0.710474, 0.982110, 1.438272, 2.349442",\ + "0.521957, 0.781516, 1.053152, 1.509314, 2.420484",\ + "0.778159, 1.037718, 1.309354, 1.765517, 2.676687",\ + "1.690818, 1.950378, 2.222013, 2.678175, 3.589345",\ + "0.510155, 0.769142, 1.040774, 1.496122, 2.406510",\ + "0.539020, 0.798007, 1.069638, 1.524987, 2.435376",\ + "0.610062, 0.869049, 1.140681, 1.596030, 2.506418",\ + "0.866264, 1.125251, 1.396883, 1.852232, 2.762620",\ + "1.778923, 2.037910, 2.309542, 2.764891, 3.675279",\ + "0.598185, 0.858106, 1.128738, 1.583761, 2.493465",\ + "0.627050, 0.886971, 1.157603, 1.612626, 2.522331",\ + "0.698092, 0.958013, 1.228645, 1.683668, 2.593373",\ + "0.954294, 1.214216, 1.484847, 1.939871, 2.849576",\ + "1.866953, 2.126875, 2.397506, 2.852530, 3.762234",\ + "0.660406, 0.923718, 1.192876, 1.647836, 2.556974",\ + "0.689271, 0.952582, 1.221740, 1.676701, 2.585840",\ + "0.760313, 1.023625, 1.292783, 1.747743, 2.656882",\ + "1.016515, 1.279827, 1.548985, 2.003945, 2.913085",\ + "1.929174, 2.192486, 2.461644, 2.916604, 3.825743",\ + "0.987793, 1.287766, 1.544618, 1.997222, 2.902431",\ + "1.016658, 1.316631, 1.573483, 2.026087, 2.931296",\ + "1.087700, 1.387673, 1.644525, 2.097129, 3.002338",\ + "1.343903, 1.643875, 1.900728, 2.353332, 3.258541",\ + "2.256562, 2.556535, 2.813386, 3.265991, 4.171199"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.043742, 0.043742, 0.043742, 0.043743, 0.043743",\ + "0.091388, 0.091388, 0.091388, 0.091388, 0.091389",\ + "0.223754, 0.223754, 0.223755, 0.223755, 0.223756",\ + "0.713686, 0.713686, 0.713688, 0.713692, 0.713700",\ + "2.456796, 2.456795, 2.456792, 2.456783, 2.456766",\ + "0.043742, 0.043742, 0.043742, 0.043743, 0.043743",\ + "0.091388, 0.091388, 0.091388, 0.091388, 0.091389",\ + "0.223754, 0.223754, 0.223755, 0.223755, 0.223756",\ + "0.713686, 0.713686, 0.713688, 0.713692, 0.713700",\ + "2.456796, 2.456795, 2.456792, 2.456783, 2.456766",\ + "0.043742, 0.043742, 0.043742, 0.043743, 0.043743",\ + "0.091388, 0.091388, 0.091388, 0.091388, 0.091389",\ + "0.223754, 0.223754, 0.223755, 0.223755, 0.223756",\ + "0.713686, 0.713686, 0.713688, 0.713692, 0.713700",\ + "2.456796, 2.456795, 2.456792, 2.456783, 2.456766",\ + "0.043742, 0.043742, 0.043742, 0.043743, 0.043743",\ + "0.091388, 0.091388, 0.091388, 0.091388, 0.091389",\ + "0.223754, 0.223754, 0.223755, 0.223755, 0.223756",\ + "0.713686, 0.713686, 0.713688, 0.713692, 0.713700",\ + "2.456796, 2.456795, 2.456792, 2.456783, 2.456766",\ + "0.043742, 0.043742, 0.043742, 0.043743, 0.043743",\ + "0.091388, 0.091388, 0.091388, 0.091388, 0.091389",\ + "0.223754, 0.223754, 0.223755, 0.223755, 0.223756",\ + "0.713686, 0.713686, 0.713688, 0.713692, 0.713700",\ + "2.456796, 2.456795, 2.456792, 2.456783, 2.456766"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.371769, 0.553936, 0.750035, 1.059373, 1.654333",\ + "0.394510, 0.576677, 0.772776, 1.082114, 1.677074",\ + "0.443791, 0.625958, 0.822057, 1.131395, 1.726356",\ + "0.609694, 0.791861, 0.987960, 1.297299, 1.892264",\ + "1.195848, 1.378015, 1.574114, 1.883451, 2.478410",\ + "0.459189, 0.641255, 0.837315, 1.146678, 1.741687",\ + "0.481930, 0.663996, 0.860057, 1.169419, 1.764428",\ + "0.531211, 0.713277, 0.909338, 1.218700, 1.813709",\ + "0.697114, 0.879180, 1.075240, 1.384604, 1.979617",\ + "1.283268, 1.465334, 1.661394, 1.970756, 2.565764",\ + "0.540056, 0.721592, 0.917342, 1.226706, 1.821719",\ + "0.562797, 0.744333, 0.940084, 1.249447, 1.844460",\ + "0.612079, 0.793614, 0.989365, 1.298728, 1.893741",\ + "0.777981, 0.959517, 1.155267, 1.464633, 2.059649",\ + "1.364136, 1.545671, 1.741421, 2.050785, 2.645795",\ + "0.597695, 0.779428, 0.975078, 1.284177, 1.878815",\ + "0.620436, 0.802170, 0.997819, 1.306918, 1.901556",\ + "0.669718, 0.851451, 1.047100, 1.356200, 1.950837",\ + "0.835620, 1.017353, 1.213003, 1.522104, 2.116745",\ + "1.421774, 1.603508, 1.799157, 2.108255, 2.702892",\ + "0.899790, 1.084807, 1.278741, 1.587385, 2.181135",\ + "0.922531, 1.107548, 1.301482, 1.610126, 2.203876",\ + "0.971813, 1.156829, 1.350764, 1.659407, 2.253157",\ + "1.137715, 1.322732, 1.516666, 1.825311, 2.419065",\ + "1.723870, 1.908886, 2.102820, 2.411463, 3.005211"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.037337, 0.037337, 0.037337, 0.037337, 0.037337",\ + "0.066008, 0.066008, 0.066008, 0.066008, 0.066009",\ + "0.143976, 0.143976, 0.143976, 0.143976, 0.143976",\ + "0.444330, 0.444330, 0.444330, 0.444330, 0.444330",\ + "1.518979, 1.518979, 1.518979, 1.518980, 1.518982",\ + "0.037337, 0.037337, 0.037337, 0.037337, 0.037337",\ + "0.066008, 0.066008, 0.066008, 0.066008, 0.066009",\ + "0.143976, 0.143976, 0.143976, 0.143976, 0.143976",\ + "0.444330, 0.444330, 0.444330, 0.444330, 0.444330",\ + "1.518979, 1.518979, 1.518979, 1.518980, 1.518982",\ + "0.037337, 0.037337, 0.037337, 0.037337, 0.037337",\ + "0.066008, 0.066008, 0.066008, 0.066008, 0.066009",\ + "0.143976, 0.143976, 0.143976, 0.143976, 0.143976",\ + "0.444330, 0.444330, 0.444330, 0.444330, 0.444330",\ + "1.518979, 1.518979, 1.518979, 1.518980, 1.518982",\ + "0.037337, 0.037337, 0.037337, 0.037337, 0.037337",\ + "0.066008, 0.066008, 0.066008, 0.066008, 0.066009",\ + "0.143976, 0.143976, 0.143976, 0.143976, 0.143976",\ + "0.444330, 0.444330, 0.444330, 0.444330, 0.444330",\ + "1.518979, 1.518979, 1.518979, 1.518980, 1.518982",\ + "0.037337, 0.037337, 0.037337, 0.037337, 0.037337",\ + "0.066008, 0.066008, 0.066008, 0.066008, 0.066009",\ + "0.143976, 0.143976, 0.143976, 0.143976, 0.143976",\ + "0.444330, 0.444330, 0.444330, 0.444330, 0.444330",\ + "1.518979, 1.518979, 1.518979, 1.518980, 1.518982"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[5]_redg_min_2343*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[3]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.514333, 0.692672, 0.873019, 1.159206, 1.709959",\ + "0.543198, 0.721537, 0.901884, 1.188071, 1.738824",\ + "0.614240, 0.792579, 0.972926, 1.259113, 1.809866",\ + "0.870442, 1.048782, 1.229129, 1.515315, 2.066068",\ + "1.783101, 1.961441, 2.141788, 2.427974, 2.978728",\ + "0.599271, 0.777508, 0.958089, 1.244712, 1.796337",\ + "0.628136, 0.806373, 0.986954, 1.273577, 1.825202",\ + "0.699178, 0.877415, 1.057996, 1.344619, 1.896244",\ + "0.955381, 1.133618, 1.314199, 1.600821, 2.152447",\ + "1.868040, 2.046277, 2.226858, 2.513480, 3.065106",\ + "0.675178, 0.852952, 1.032898, 1.319309, 1.870510",\ + "0.704042, 0.881817, 1.061763, 1.348174, 1.899375",\ + "0.775084, 0.952859, 1.132805, 1.419216, 1.970417",\ + "1.031287, 1.209061, 1.389008, 1.675418, 2.226619",\ + "1.943946, 2.121720, 2.301667, 2.588077, 3.139278",\ + "0.729530, 0.907697, 1.087764, 1.373903, 1.924827",\ + "0.758394, 0.936562, 1.116628, 1.402767, 1.953692",\ + "0.829437, 1.007604, 1.187670, 1.473809, 2.024734",\ + "1.085639, 1.263806, 1.443873, 1.730012, 2.280936",\ + "1.998298, 2.176466, 2.356532, 2.642671, 3.193595",\ + "1.010952, 1.193215, 1.371917, 1.657629, 2.208105",\ + "1.039816, 1.222079, 1.400781, 1.686494, 2.236969",\ + "1.110858, 1.293122, 1.471824, 1.757536, 2.308012",\ + "1.367061, 1.549324, 1.728026, 2.013738, 2.564214",\ + "2.279720, 2.461983, 2.640685, 2.926397, 3.476873"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.043742, 0.043742, 0.043742, 0.043742, 0.043742",\ + "0.091388, 0.091388, 0.091388, 0.091388, 0.091388",\ + "0.223754, 0.223754, 0.223754, 0.223754, 0.223754",\ + "0.713686, 0.713686, 0.713686, 0.713686, 0.713686",\ + "2.456796, 2.456796, 2.456796, 2.456796, 2.456796",\ + "0.043742, 0.043742, 0.043742, 0.043742, 0.043742",\ + "0.091388, 0.091388, 0.091388, 0.091388, 0.091388",\ + "0.223754, 0.223754, 0.223754, 0.223754, 0.223754",\ + "0.713686, 0.713686, 0.713686, 0.713686, 0.713686",\ + "2.456796, 2.456796, 2.456796, 2.456796, 2.456796",\ + "0.043742, 0.043742, 0.043742, 0.043742, 0.043742",\ + "0.091388, 0.091388, 0.091388, 0.091388, 0.091388",\ + "0.223754, 0.223754, 0.223754, 0.223754, 0.223754",\ + "0.713686, 0.713686, 0.713686, 0.713686, 0.713686",\ + "2.456796, 2.456796, 2.456796, 2.456796, 2.456796",\ + "0.043742, 0.043742, 0.043742, 0.043742, 0.043742",\ + "0.091388, 0.091388, 0.091388, 0.091388, 0.091388",\ + "0.223754, 0.223754, 0.223754, 0.223754, 0.223754",\ + "0.713686, 0.713686, 0.713686, 0.713686, 0.713686",\ + "2.456796, 2.456796, 2.456796, 2.456796, 2.456796",\ + "0.043742, 0.043742, 0.043742, 0.043742, 0.043742",\ + "0.091388, 0.091388, 0.091388, 0.091388, 0.091388",\ + "0.223754, 0.223754, 0.223754, 0.223754, 0.223754",\ + "0.713686, 0.713686, 0.713686, 0.713686, 0.713686",\ + "2.456796, 2.456796, 2.456796, 2.456796, 2.456796"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.389041, 0.654041, 0.913070, 1.349334, 2.221481",\ + "0.411783, 0.676782, 0.935811, 1.372076, 2.244222",\ + "0.461064, 0.726063, 0.985092, 1.421357, 2.293503",\ + "0.626966, 0.891965, 1.150995, 1.587259, 2.459406",\ + "1.213121, 1.478120, 1.737149, 2.173413, 3.045560",\ + "0.477707, 0.742116, 1.001711, 1.437563, 2.308886",\ + "0.500448, 0.764857, 1.024452, 1.460304, 2.331627",\ + "0.549729, 0.814138, 1.073733, 1.509586, 2.380908",\ + "0.715632, 0.980040, 1.239636, 1.675488, 2.546811",\ + "1.301786, 1.566195, 1.825790, 2.261642, 3.132965",\ + "0.570514, 0.835409, 1.093746, 1.529807, 2.401928",\ + "0.593255, 0.858150, 1.116487, 1.552548, 2.424669",\ + "0.642536, 0.907431, 1.165769, 1.601829, 2.473950",\ + "0.808439, 1.073334, 1.331671, 1.767732, 2.639853",\ + "1.394593, 1.659488, 1.917825, 2.353886, 3.226007",\ + "0.636236, 0.903943, 1.160801, 1.596813, 2.468838",\ + "0.658977, 0.926684, 1.183542, 1.619554, 2.491579",\ + "0.708259, 0.975966, 1.232824, 1.668836, 2.540860",\ + "0.874161, 1.141868, 1.398726, 1.834738, 2.706763",\ + "1.460315, 1.728022, 1.984880, 2.420892, 3.292917",\ + "0.982026, 1.284442, 1.531439, 1.966014, 2.835165",\ + "1.004767, 1.307183, 1.554181, 1.988755, 2.857906",\ + "1.054048, 1.356464, 1.603462, 2.038037, 2.907187",\ + "1.219950, 1.522366, 1.769364, 2.203939, 3.073090",\ + "1.806105, 2.108521, 2.355518, 2.790093, 3.659244"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.037338, 0.037338, 0.037338, 0.037338, 0.037338",\ + "0.066008, 0.066008, 0.066008, 0.066008, 0.066008",\ + "0.143978, 0.143978, 0.143978, 0.143978, 0.143978",\ + "0.444353, 0.444353, 0.444354, 0.444354, 0.444354",\ + "1.518979, 1.518979, 1.518979, 1.518979, 1.518979",\ + "0.037338, 0.037338, 0.037338, 0.037338, 0.037338",\ + "0.066008, 0.066008, 0.066008, 0.066008, 0.066008",\ + "0.143978, 0.143978, 0.143978, 0.143978, 0.143978",\ + "0.444353, 0.444353, 0.444354, 0.444354, 0.444354",\ + "1.518979, 1.518979, 1.518979, 1.518979, 1.518979",\ + "0.037338, 0.037338, 0.037338, 0.037338, 0.037338",\ + "0.066008, 0.066008, 0.066008, 0.066008, 0.066008",\ + "0.143978, 0.143978, 0.143978, 0.143978, 0.143978",\ + "0.444353, 0.444353, 0.444354, 0.444354, 0.444354",\ + "1.518979, 1.518979, 1.518979, 1.518979, 1.518979",\ + "0.037338, 0.037338, 0.037338, 0.037338, 0.037338",\ + "0.066008, 0.066008, 0.066008, 0.066008, 0.066008",\ + "0.143978, 0.143978, 0.143978, 0.143978, 0.143978",\ + "0.444353, 0.444353, 0.444354, 0.444354, 0.444354",\ + "1.518979, 1.518979, 1.518979, 1.518979, 1.518979",\ + "0.037338, 0.037338, 0.037338, 0.037338, 0.037338",\ + "0.066008, 0.066008, 0.066008, 0.066008, 0.066008",\ + "0.143978, 0.143978, 0.143978, 0.143978, 0.143978",\ + "0.444353, 0.444353, 0.444354, 0.444354, 0.444354",\ + "1.518979, 1.518979, 1.518979, 1.518979, 1.518979"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[5]_redg_min_2288*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + values ( "0.142389, 0.171566, 0.243166, 0.499437, 1.411098",\ + "0.230574, 0.259751, 0.331362, 0.587680, 1.499024",\ + "0.318899, 0.348075, 0.419691, 0.676199, 1.587106",\ + "0.381491, 0.410664, 0.482232, 0.739031, 1.650402",\ + "0.711374, 0.740537, 0.811930, 1.069170, 1.982165"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + values ( "0.043742, 0.091388, 0.223754, 0.713686, 2.456796",\ + "0.043742, 0.091388, 0.223754, 0.713686, 2.456796",\ + "0.043742, 0.091388, 0.223754, 0.713686, 2.456796",\ + "0.043742, 0.091388, 0.223754, 0.713686, 2.456796",\ + "0.043742, 0.091388, 0.223754, 0.713686, 2.456796"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + values ( "0.180754, 0.203203, 0.252178, 0.417875, 1.004001",\ + "0.268158, 0.290607, 0.339581, 0.505279, 1.091404",\ + "0.349055, 0.371502, 0.420481, 0.586183, 1.172317",\ + "0.406718, 0.429160, 0.478148, 0.643857, 1.230008",\ + "0.709074, 0.731508, 0.780524, 0.946302, 1.532625"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + values ( "0.037339, 0.066008, 0.143979, 0.443541, 1.518445",\ + "0.037339, 0.066008, 0.143979, 0.443540, 1.518445",\ + "0.037339, 0.066008, 0.143979, 0.443540, 1.518243",\ + "0.037339, 0.066008, 0.143979, 0.443540, 1.517867",\ + "0.037339, 0.066008, 0.143978, 0.443540, 1.516694"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[5]_redg_min*/ + + timing () { + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + values ( "0.083777, 0.113177, 0.184363, 0.440561, 1.354954",\ + "0.166191, 0.195837, 0.267192, 0.523277, 1.434794",\ + "0.254428, 0.286014, 0.357719, 0.613433, 1.527519",\ + "0.402853, 0.441150, 0.515777, 0.771236, 1.680856",\ + "0.639529, 0.694162, 0.784036, 1.036347, 1.943170"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + values ( "0.046241, 0.092638, 0.224458, 0.720967, 2.472405",\ + "0.047673, 0.093421, 0.224642, 0.721323, 2.472405",\ + "0.058846, 0.099756, 0.225481, 0.721323, 2.472405",\ + "0.087693, 0.120786, 0.231211, 0.721323, 2.472405",\ + "0.150701, 0.177706, 0.265097, 0.721323, 2.472405"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + values ( "0.115523, 0.139488, 0.190373, 0.357311, 0.943250",\ + "0.195424, 0.220107, 0.270909, 0.437012, 1.024824",\ + "0.295483, 0.321586, 0.373863, 0.540151, 1.127638",\ + "0.466222, 0.498877, 0.556261, 0.723129, 1.308255",\ + "0.739560, 0.788071, 0.862427, 1.035419, 1.617964"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + values ( "0.044606, 0.073777, 0.150227, 0.449909, 1.525255",\ + "0.044880, 0.073777, 0.150227, 0.449909, 1.525255",\ + "0.054859, 0.080811, 0.152895, 0.449909, 1.525255",\ + "0.083786, 0.105188, 0.168383, 0.450518, 1.525255",\ + "0.145006, 0.165847, 0.216404, 0.463154, 1.525255"); + } + + } /* end of arc padmux2ast_i[5]_obs_ctrl_o[5]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + values ( "0.079158, 0.108043, 0.179215, 0.434173, 1.346996",\ + "0.161067, 0.189991, 0.261053, 0.516828, 1.426491",\ + "0.245841, 0.276441, 0.347577, 0.603328, 1.515415",\ + "0.390269, 0.426632, 0.499915, 0.754138, 1.664120",\ + "0.617992, 0.669105, 0.755401, 1.006998, 1.912977"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + values ( "0.043983, 0.091336, 0.223341, 0.706536, 2.446538",\ + "0.045333, 0.091976, 0.223341, 0.711950, 2.446538",\ + "0.055328, 0.097699, 0.224823, 0.713717, 2.446538",\ + "0.081572, 0.117377, 0.229870, 0.714277, 2.457507",\ + "0.139013, 0.170652, 0.260149, 0.718737, 2.457507"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + values ( "0.084172, 0.105801, 0.153856, 0.319168, 0.906380",\ + "0.169681, 0.191458, 0.239573, 0.404634, 0.995979",\ + "0.265868, 0.290580, 0.340403, 0.505279, 1.091202",\ + "0.427357, 0.458965, 0.514692, 0.679112, 1.262906",\ + "0.687739, 0.736091, 0.809895, 0.982075, 1.563284"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + values ( "0.037000, 0.065831, 0.143664, 0.445190, 1.520147",\ + "0.037985, 0.066094, 0.143861, 0.445190, 1.520147",\ + "0.050092, 0.075267, 0.147407, 0.445190, 1.520147",\ + "0.078605, 0.099932, 0.163006, 0.448532, 1.520147",\ + "0.139198, 0.159714, 0.210091, 0.458787, 1.520147"); + } + + } /* end of arc padmux2ast_i[5]_obs_ctrl_o[5]_una_min*/ + +} /* end of pin obs_ctrl_o[5] */ + +pin("obs_ctrl_o[4]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.156168 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000989 ; + + /* Other user defined attributes. */ + original_pin : obs_ctrl_o[4]; + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[0]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.556168, 0.736371, 0.923861, 1.225854, 1.809366",\ + "0.586766, 0.766969, 0.954459, 1.256451, 1.839963",\ + "0.658595, 0.838798, 1.026288, 1.328280, 1.911792",\ + "0.915054, 1.095257, 1.282747, 1.584739, 2.168251",\ + "1.830892, 2.011095, 2.198585, 2.500578, 3.084090",\ + "0.641107, 0.821654, 1.009870, 1.311866, 1.895744",\ + "0.671704, 0.852252, 1.040468, 1.342464, 1.926342",\ + "0.743533, 0.924081, 1.112296, 1.414292, 1.998170",\ + "0.999992, 1.180540, 1.368755, 1.670752, 2.254630",\ + "1.915831, 2.096378, 2.284594, 2.586590, 3.170468",\ + "0.717019, 0.897098, 1.084679, 1.386463, 1.969916",\ + "0.747616, 0.927695, 1.115276, 1.417060, 2.000514",\ + "0.819445, 0.999524, 1.187105, 1.488889, 2.072343",\ + "1.075904, 1.255983, 1.443564, 1.745348, 2.328802",\ + "1.991743, 2.171822, 2.359403, 2.661187, 3.244640",\ + "0.771388, 0.951609, 1.139330, 1.441003, 2.024234",\ + "0.801986, 0.982207, 1.169927, 1.471600, 2.054831",\ + "0.873814, 1.054036, 1.241756, 1.543429, 2.126660",\ + "1.130274, 1.310495, 1.498215, 1.799888, 2.383119",\ + "2.046112, 2.226333, 2.414054, 2.715726, 3.298958",\ + "1.052983, 1.236877, 1.423280, 1.724729, 2.307511",\ + "1.083580, 1.267475, 1.453878, 1.755327, 2.338109",\ + "1.155409, 1.339304, 1.525707, 1.827155, 2.409937",\ + "1.411868, 1.595763, 1.782166, 2.083614, 2.666397",\ + "2.327707, 2.511601, 2.698004, 2.999453, 3.582235"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.040033, 0.040033, 0.040033, 0.040033, 0.040033",\ + "0.086005, 0.086005, 0.086005, 0.086005, 0.086005",\ + "0.217202, 0.217202, 0.217202, 0.217202, 0.217202",\ + "0.715349, 0.715349, 0.715349, 0.715349, 0.715349",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.040033, 0.040033, 0.040033, 0.040033, 0.040033",\ + "0.086005, 0.086005, 0.086005, 0.086005, 0.086005",\ + "0.217202, 0.217202, 0.217202, 0.217202, 0.217202",\ + "0.715349, 0.715349, 0.715349, 0.715349, 0.715349",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.040033, 0.040033, 0.040033, 0.040033, 0.040033",\ + "0.086005, 0.086005, 0.086005, 0.086005, 0.086005",\ + "0.217202, 0.217202, 0.217202, 0.217202, 0.217202",\ + "0.715349, 0.715349, 0.715349, 0.715349, 0.715349",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.040033, 0.040033, 0.040033, 0.040033, 0.040033",\ + "0.086005, 0.086005, 0.086005, 0.086005, 0.086005",\ + "0.217202, 0.217202, 0.217202, 0.217202, 0.217202",\ + "0.715349, 0.715349, 0.715349, 0.715349, 0.715349",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.040033, 0.040033, 0.040033, 0.040033, 0.040033",\ + "0.086005, 0.086005, 0.086005, 0.086005, 0.086005",\ + "0.217202, 0.217202, 0.217202, 0.217202, 0.217202",\ + "0.715349, 0.715349, 0.715349, 0.715349, 0.715349",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.426989, 0.694775, 0.956355, 1.396052, 2.275447",\ + "0.452751, 0.720537, 0.982117, 1.421814, 2.301209",\ + "0.504153, 0.771939, 1.033519, 1.473216, 2.352611",\ + "0.670963, 0.938748, 1.200328, 1.640025, 2.519420",\ + "1.261262, 1.529048, 1.790628, 2.230325, 3.109720",\ + "0.515693, 0.782850, 1.044996, 1.484281, 2.362852",\ + "0.541455, 0.808612, 1.070758, 1.510043, 2.388614",\ + "0.592858, 0.860014, 1.122160, 1.561445, 2.440016",\ + "0.759667, 1.026823, 1.288969, 1.728255, 2.606825",\ + "1.349967, 1.617123, 1.879269, 2.318554, 3.197125",\ + "0.608636, 0.875995, 1.136721, 1.576445, 2.455894",\ + "0.634398, 0.901757, 1.162483, 1.602207, 2.481656",\ + "0.685800, 0.953159, 1.213886, 1.653610, 2.533058",\ + "0.852609, 1.119968, 1.380695, 1.820419, 2.699867",\ + "1.442909, 1.710268, 1.970994, 2.410718, 3.290167",\ + "0.674479, 0.944559, 1.203741, 1.643296, 2.522405",\ + "0.700241, 0.970321, 1.229503, 1.669058, 2.548167",\ + "0.751643, 1.021724, 1.280905, 1.720460, 2.599569",\ + "0.918453, 1.188533, 1.447715, 1.887269, 2.766378",\ + "1.508752, 1.778832, 2.038014, 2.477569, 3.356678",\ + "1.021001, 1.325395, 1.574404, 2.012450, 2.888541",\ + "1.046763, 1.351157, 1.600166, 2.038211, 2.914303",\ + "1.098165, 1.402559, 1.651568, 2.089614, 2.965705",\ + "1.264974, 1.569368, 1.818377, 2.256423, 3.132514",\ + "1.855274, 2.159668, 2.408677, 2.846723, 3.722814"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.040698, 0.040698, 0.040698, 0.040698, 0.040698",\ + "0.070039, 0.070039, 0.070039, 0.070039, 0.070038",\ + "0.145874, 0.145874, 0.145874, 0.145874, 0.145874",\ + "0.444024, 0.444024, 0.444024, 0.444024, 0.444024",\ + "1.524052, 1.524052, 1.524052, 1.524052, 1.524052",\ + "0.040698, 0.040698, 0.040698, 0.040698, 0.040698",\ + "0.070039, 0.070039, 0.070039, 0.070039, 0.070038",\ + "0.145874, 0.145874, 0.145874, 0.145874, 0.145874",\ + "0.444024, 0.444024, 0.444024, 0.444024, 0.444024",\ + "1.524052, 1.524052, 1.524052, 1.524052, 1.524052",\ + "0.040698, 0.040698, 0.040698, 0.040698, 0.040698",\ + "0.070039, 0.070039, 0.070039, 0.070039, 0.070038",\ + "0.145874, 0.145874, 0.145874, 0.145874, 0.145874",\ + "0.444024, 0.444024, 0.444024, 0.444024, 0.444024",\ + "1.524052, 1.524052, 1.524052, 1.524052, 1.524052",\ + "0.040698, 0.040698, 0.040698, 0.040698, 0.040698",\ + "0.070039, 0.070039, 0.070039, 0.070039, 0.070038",\ + "0.145874, 0.145874, 0.145874, 0.145874, 0.145874",\ + "0.444024, 0.444024, 0.444024, 0.444024, 0.444024",\ + "1.524052, 1.524052, 1.524052, 1.524052, 1.524052",\ + "0.040698, 0.040698, 0.040698, 0.040698, 0.040698",\ + "0.070039, 0.070039, 0.070039, 0.070039, 0.070038",\ + "0.145874, 0.145874, 0.145874, 0.145874, 0.145874",\ + "0.444024, 0.444024, 0.444024, 0.444024, 0.444024",\ + "1.524052, 1.524052, 1.524052, 1.524052, 1.524052"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[4]_redg_2724*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[1]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.464273, 0.727847, 1.004120, 1.472849, 2.410309",\ + "0.494871, 0.758445, 1.034717, 1.503447, 2.440906",\ + "0.566700, 0.830273, 1.106546, 1.575275, 2.512735",\ + "0.823159, 1.086733, 1.363005, 1.831734, 2.769193",\ + "1.738997, 2.002571, 2.278844, 2.747575, 3.685036",\ + "0.552468, 0.815388, 1.091687, 1.559565, 2.496242",\ + "0.583065, 0.845985, 1.122285, 1.590162, 2.526840",\ + "0.654894, 0.917814, 1.194114, 1.661991, 2.598668",\ + "0.911353, 1.174273, 1.450573, 1.918450, 2.855127",\ + "1.827192, 2.090112, 2.366412, 2.834290, 3.770969",\ + "0.640784, 0.904368, 1.179652, 1.647187, 2.583197",\ + "0.671381, 0.934966, 1.210250, 1.677785, 2.613795",\ + "0.743210, 1.006795, 1.282079, 1.749613, 2.685623",\ + "0.999669, 1.263254, 1.538538, 2.006072, 2.942082",\ + "1.915508, 2.179092, 2.454377, 2.921913, 3.857924",\ + "0.703280, 0.970003, 1.243792, 1.711101, 2.646706",\ + "0.733877, 1.000601, 1.274390, 1.741699, 2.677304",\ + "0.805706, 1.072430, 1.346218, 1.813527, 2.749132",\ + "1.062165, 1.328889, 1.602677, 2.069986, 3.005591",\ + "1.978004, 2.244727, 2.518517, 2.985826, 3.921433",\ + "1.032405, 1.334334, 1.595659, 2.060451, 2.992162",\ + "1.063003, 1.364932, 1.626257, 2.091048, 3.022760",\ + "1.134832, 1.436760, 1.698085, 2.162877, 3.094589",\ + "1.391291, 1.693219, 1.954545, 2.419336, 3.351047",\ + "2.307129, 2.609058, 2.870384, 3.335176, 4.266890"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.040033, 0.040033, 0.040033, 0.040033, 0.040033",\ + "0.086005, 0.086005, 0.086005, 0.086005, 0.086005",\ + "0.217202, 0.217202, 0.217201, 0.217201, 0.217201",\ + "0.715349, 0.715349, 0.715347, 0.715344, 0.715337",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.040033, 0.040033, 0.040033, 0.040033, 0.040033",\ + "0.086005, 0.086005, 0.086005, 0.086005, 0.086005",\ + "0.217202, 0.217202, 0.217201, 0.217201, 0.217201",\ + "0.715349, 0.715349, 0.715347, 0.715344, 0.715337",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.040033, 0.040033, 0.040033, 0.040033, 0.040033",\ + "0.086005, 0.086005, 0.086005, 0.086005, 0.086005",\ + "0.217202, 0.217202, 0.217201, 0.217201, 0.217201",\ + "0.715349, 0.715349, 0.715347, 0.715344, 0.715337",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.040033, 0.040033, 0.040033, 0.040033, 0.040033",\ + "0.086005, 0.086005, 0.086005, 0.086005, 0.086005",\ + "0.217202, 0.217202, 0.217201, 0.217201, 0.217201",\ + "0.715349, 0.715349, 0.715347, 0.715344, 0.715337",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.040033, 0.040033, 0.040033, 0.040033, 0.040033",\ + "0.086005, 0.086005, 0.086005, 0.086005, 0.086005",\ + "0.217202, 0.217202, 0.217201, 0.217201, 0.217201",\ + "0.715349, 0.715349, 0.715347, 0.715344, 0.715337",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.409942, 0.592374, 0.788766, 1.097819, 1.692625",\ + "0.435704, 0.618136, 0.814528, 1.123581, 1.718389",\ + "0.487107, 0.669538, 0.865930, 1.174984, 1.769791",\ + "0.653916, 0.836348, 1.032740, 1.341792, 1.936599",\ + "1.244215, 1.426647, 1.623039, 1.932092, 2.526900",\ + "0.497357, 0.679760, 0.876259, 1.185124, 1.779979",\ + "0.523119, 0.705522, 0.902021, 1.210886, 1.805742",\ + "0.574521, 0.756924, 0.953424, 1.262289, 1.857144",\ + "0.741330, 0.923733, 1.120233, 1.429098, 2.023953",\ + "1.331630, 1.514033, 1.710532, 2.019397, 2.614253",\ + "0.578233, 0.760096, 0.956286, 1.265153, 1.860010",\ + "0.603995, 0.785858, 0.982048, 1.290915, 1.885774",\ + "0.655398, 0.837260, 1.033450, 1.342317, 1.937176",\ + "0.822207, 1.004070, 1.200260, 1.509126, 2.103984",\ + "1.412507, 1.594369, 1.790559, 2.099426, 2.694285",\ + "0.635880, 0.817645, 1.013830, 1.322398, 1.916658",\ + "0.661642, 0.843407, 1.039592, 1.348160, 1.942421",\ + "0.713044, 0.894809, 1.090994, 1.399562, 1.993823",\ + "0.879853, 1.061618, 1.257803, 1.566371, 2.160632",\ + "1.470153, 1.651918, 1.848103, 2.156671, 2.750932",\ + "0.938088, 1.122869, 1.317464, 1.625412, 2.218504",\ + "0.963849, 1.148631, 1.343226, 1.651175, 2.244268",\ + "1.015252, 1.200033, 1.394628, 1.702577, 2.295670",\ + "1.182061, 1.366843, 1.561437, 1.869386, 2.462479",\ + "1.772361, 1.957142, 2.151737, 2.459686, 3.052779"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.040698, 0.040698, 0.040698, 0.040699, 0.040699",\ + "0.070039, 0.070039, 0.070039, 0.070039, 0.070039",\ + "0.145874, 0.145874, 0.145874, 0.145874, 0.145874",\ + "0.444024, 0.444024, 0.444024, 0.444024, 0.444024",\ + "1.524052, 1.524052, 1.524052, 1.524054, 1.524057",\ + "0.040698, 0.040698, 0.040698, 0.040699, 0.040699",\ + "0.070039, 0.070039, 0.070039, 0.070039, 0.070039",\ + "0.145874, 0.145874, 0.145874, 0.145874, 0.145874",\ + "0.444024, 0.444024, 0.444024, 0.444024, 0.444024",\ + "1.524052, 1.524052, 1.524052, 1.524054, 1.524057",\ + "0.040698, 0.040698, 0.040698, 0.040699, 0.040699",\ + "0.070039, 0.070039, 0.070039, 0.070039, 0.070039",\ + "0.145874, 0.145874, 0.145874, 0.145874, 0.145874",\ + "0.444024, 0.444024, 0.444024, 0.444024, 0.444024",\ + "1.524052, 1.524052, 1.524052, 1.524054, 1.524057",\ + "0.040698, 0.040698, 0.040698, 0.040699, 0.040699",\ + "0.070039, 0.070039, 0.070039, 0.070039, 0.070039",\ + "0.145874, 0.145874, 0.145874, 0.145874, 0.145874",\ + "0.444024, 0.444024, 0.444024, 0.444024, 0.444024",\ + "1.524052, 1.524052, 1.524052, 1.524054, 1.524057",\ + "0.040698, 0.040698, 0.040698, 0.040699, 0.040699",\ + "0.070039, 0.070039, 0.070039, 0.070039, 0.070039",\ + "0.145874, 0.145874, 0.145874, 0.145874, 0.145874",\ + "0.444024, 0.444024, 0.444024, 0.444024, 0.444024",\ + "1.524052, 1.524052, 1.524052, 1.524054, 1.524057"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[4]_redg_2651*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[2]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.460298, 0.719927, 0.991800, 1.448679, 2.362439",\ + "0.490896, 0.750525, 1.022397, 1.479277, 2.393037",\ + "0.562724, 0.822354, 1.094226, 1.551105, 2.464865",\ + "0.819184, 1.078813, 1.350685, 1.807564, 2.721324",\ + "1.735022, 1.994652, 2.266525, 2.723405, 3.637166",\ + "0.548403, 0.807461, 1.079330, 1.535395, 2.448373",\ + "0.579001, 0.838059, 1.109928, 1.565992, 2.478970",\ + "0.650829, 0.909887, 1.181756, 1.637821, 2.550799",\ + "0.907289, 1.166346, 1.438215, 1.894280, 2.807258",\ + "1.823127, 2.082185, 2.354055, 2.810120, 3.723099",\ + "0.636433, 0.896427, 1.167294, 1.623017, 2.535328",\ + "0.667031, 0.927024, 1.197892, 1.653615, 2.565925",\ + "0.738859, 0.998853, 1.269721, 1.725444, 2.637754",\ + "0.995319, 1.255312, 1.526180, 1.981903, 2.894213",\ + "1.911157, 2.171151, 2.442019, 2.897743, 3.810054",\ + "0.698654, 0.962040, 1.231432, 1.686931, 2.598837",\ + "0.729252, 0.992638, 1.262030, 1.717529, 2.629434",\ + "0.801081, 1.064467, 1.333858, 1.789357, 2.701263",\ + "1.057540, 1.320926, 1.590317, 2.045816, 2.957722",\ + "1.973378, 2.236765, 2.506157, 2.961657, 3.873563",\ + "1.026042, 1.326115, 1.583179, 2.036232, 2.944293",\ + "1.056639, 1.356713, 1.613777, 2.066829, 2.974890",\ + "1.128468, 1.428541, 1.685606, 2.138658, 3.046719",\ + "1.384927, 1.685001, 1.942065, 2.395117, 3.303178",\ + "2.300766, 2.600840, 2.857904, 3.310957, 4.219019"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.040033, 0.040033, 0.040033, 0.040033, 0.040033",\ + "0.086005, 0.086005, 0.086005, 0.086005, 0.086005",\ + "0.217202, 0.217202, 0.217201, 0.217201, 0.217201",\ + "0.715349, 0.715349, 0.715346, 0.715340, 0.715328",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.040033, 0.040033, 0.040033, 0.040033, 0.040033",\ + "0.086005, 0.086005, 0.086005, 0.086005, 0.086005",\ + "0.217202, 0.217201, 0.217201, 0.217201, 0.217201",\ + "0.715349, 0.715349, 0.715346, 0.715340, 0.715328",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.040033, 0.040033, 0.040033, 0.040033, 0.040033",\ + "0.086005, 0.086005, 0.086005, 0.086005, 0.086005",\ + "0.217202, 0.217201, 0.217201, 0.217201, 0.217201",\ + "0.715349, 0.715349, 0.715346, 0.715340, 0.715328",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.040033, 0.040033, 0.040033, 0.040033, 0.040033",\ + "0.086005, 0.086005, 0.086005, 0.086005, 0.086005",\ + "0.217202, 0.217201, 0.217201, 0.217201, 0.217201",\ + "0.715349, 0.715349, 0.715346, 0.715340, 0.715328",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.040033, 0.040033, 0.040033, 0.040033, 0.040033",\ + "0.086005, 0.086005, 0.086005, 0.086005, 0.086005",\ + "0.217202, 0.217201, 0.217201, 0.217201, 0.217201",\ + "0.715349, 0.715349, 0.715346, 0.715340, 0.715328",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.408281, 0.590822, 0.787077, 1.096293, 1.691588",\ + "0.434043, 0.616584, 0.812839, 1.122056, 1.717351",\ + "0.485445, 0.667986, 0.864241, 1.173458, 1.768753",\ + "0.652254, 0.834795, 1.031050, 1.340267, 1.935562",\ + "1.242554, 1.425095, 1.621350, 1.930567, 2.525863",\ + "0.495701, 0.678207, 0.874570, 1.183598, 1.778941",\ + "0.521463, 0.703969, 0.900331, 1.209361, 1.804705",\ + "0.572865, 0.755371, 0.951734, 1.260763, 1.856107",\ + "0.739674, 0.922180, 1.118543, 1.427572, 2.022916",\ + "1.329974, 1.512480, 1.708843, 2.017872, 2.613216",\ + "0.576569, 0.758544, 0.954597, 1.263627, 1.858973",\ + "0.602330, 0.784306, 0.980358, 1.289389, 1.884737",\ + "0.653733, 0.835708, 1.031761, 1.340791, 1.936139",\ + "0.820542, 1.002517, 1.198570, 1.507600, 2.102947",\ + "1.410842, 1.592817, 1.788870, 2.097900, 2.693248",\ + "0.634207, 0.816093, 1.012141, 1.320872, 1.915620",\ + "0.659969, 0.841854, 1.037902, 1.346634, 1.941384",\ + "0.711372, 0.893257, 1.089304, 1.398036, 1.992786",\ + "0.878181, 1.060066, 1.256114, 1.564846, 2.159595",\ + "1.468480, 1.650366, 1.846413, 2.155146, 2.749895",\ + "0.936303, 1.121319, 1.315774, 1.623887, 2.217467",\ + "0.962064, 1.147081, 1.341536, 1.649649, 2.243231",\ + "1.013467, 1.198483, 1.392939, 1.701051, 2.294633",\ + "1.180276, 1.365292, 1.559748, 1.867860, 2.461442",\ + "1.770576, 1.955592, 2.150048, 2.458160, 3.051742"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.040698, 0.040698, 0.040698, 0.040699, 0.040699",\ + "0.070039, 0.070039, 0.070039, 0.070039, 0.070039",\ + "0.145874, 0.145874, 0.145874, 0.145874, 0.145874",\ + "0.444024, 0.444024, 0.444024, 0.444024, 0.444024",\ + "1.524052, 1.524052, 1.524052, 1.524054, 1.524058",\ + "0.040698, 0.040698, 0.040698, 0.040699, 0.040699",\ + "0.070039, 0.070039, 0.070039, 0.070039, 0.070039",\ + "0.145874, 0.145874, 0.145874, 0.145874, 0.145874",\ + "0.444024, 0.444024, 0.444024, 0.444024, 0.444024",\ + "1.524052, 1.524052, 1.524052, 1.524054, 1.524058",\ + "0.040698, 0.040698, 0.040698, 0.040699, 0.040699",\ + "0.070039, 0.070039, 0.070039, 0.070039, 0.070039",\ + "0.145874, 0.145874, 0.145874, 0.145874, 0.145874",\ + "0.444024, 0.444024, 0.444024, 0.444024, 0.444024",\ + "1.524052, 1.524052, 1.524052, 1.524054, 1.524058",\ + "0.040698, 0.040698, 0.040698, 0.040699, 0.040699",\ + "0.070039, 0.070039, 0.070039, 0.070039, 0.070039",\ + "0.145874, 0.145874, 0.145874, 0.145874, 0.145874",\ + "0.444024, 0.444024, 0.444024, 0.444024, 0.444024",\ + "1.524052, 1.524052, 1.524052, 1.524054, 1.524058",\ + "0.040698, 0.040698, 0.040698, 0.040699, 0.040699",\ + "0.070039, 0.070039, 0.070039, 0.070039, 0.070039",\ + "0.145874, 0.145874, 0.145874, 0.145874, 0.145874",\ + "0.444024, 0.444024, 0.444024, 0.444024, 0.444024",\ + "1.524052, 1.524052, 1.524052, 1.524054, 1.524058"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[4]_redg_2594*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[3]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.552582, 0.731009, 0.911269, 1.197475, 1.748592",\ + "0.583180, 0.761606, 0.941867, 1.228073, 1.779190",\ + "0.655008, 0.833435, 1.013695, 1.299902, 1.851019",\ + "0.911468, 1.089894, 1.270155, 1.556361, 2.107478",\ + "1.827306, 2.005733, 2.185993, 2.472199, 3.023317",\ + "0.637520, 0.816281, 0.997184, 1.283396, 1.834971",\ + "0.668118, 0.846879, 1.027782, 1.313993, 1.865568",\ + "0.739947, 0.918707, 1.099610, 1.385822, 1.937397",\ + "0.996406, 1.175167, 1.356070, 1.642281, 2.193856",\ + "1.912244, 2.091005, 2.271908, 2.558120, 3.109695",\ + "0.713426, 0.891724, 1.071993, 1.357992, 1.909143",\ + "0.744024, 0.922322, 1.102591, 1.388590, 1.939741",\ + "0.815853, 0.994151, 1.174419, 1.460419, 2.011569",\ + "1.072312, 1.250610, 1.430879, 1.716878, 2.268029",\ + "1.988150, 2.166448, 2.346717, 2.632716, 3.183867",\ + "0.767778, 0.946236, 1.126644, 1.412532, 1.963460",\ + "0.798376, 0.976834, 1.157242, 1.443130, 1.994058",\ + "0.870205, 1.048662, 1.229070, 1.514959, 2.065886",\ + "1.126664, 1.305122, 1.485530, 1.771418, 2.322346",\ + "2.042502, 2.220960, 2.401368, 2.687256, 3.238184",\ + "1.049200, 1.231463, 1.410595, 1.696259, 2.246738",\ + "1.079798, 1.262061, 1.441192, 1.726856, 2.277336",\ + "1.151627, 1.333890, 1.513021, 1.798685, 2.349164",\ + "1.408086, 1.590349, 1.769480, 2.055144, 2.605623",\ + "2.323924, 2.506187, 2.685318, 2.970983, 3.521462"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.040033, 0.040033, 0.040033, 0.040033, 0.040033",\ + "0.086005, 0.086005, 0.086005, 0.086005, 0.086005",\ + "0.217202, 0.217202, 0.217202, 0.217202, 0.217202",\ + "0.715349, 0.715349, 0.715349, 0.715349, 0.715349",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.040033, 0.040033, 0.040033, 0.040033, 0.040033",\ + "0.086005, 0.086005, 0.086005, 0.086005, 0.086005",\ + "0.217202, 0.217202, 0.217202, 0.217202, 0.217202",\ + "0.715349, 0.715349, 0.715349, 0.715349, 0.715349",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.040033, 0.040033, 0.040033, 0.040033, 0.040033",\ + "0.086005, 0.086005, 0.086005, 0.086005, 0.086005",\ + "0.217202, 0.217202, 0.217202, 0.217202, 0.217202",\ + "0.715349, 0.715349, 0.715349, 0.715349, 0.715349",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.040033, 0.040033, 0.040033, 0.040033, 0.040033",\ + "0.086005, 0.086005, 0.086005, 0.086005, 0.086005",\ + "0.217202, 0.217202, 0.217202, 0.217202, 0.217202",\ + "0.715349, 0.715349, 0.715349, 0.715349, 0.715349",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.040033, 0.040033, 0.040033, 0.040033, 0.040033",\ + "0.086005, 0.086005, 0.086005, 0.086005, 0.086005",\ + "0.217202, 0.217202, 0.217202, 0.217202, 0.217202",\ + "0.715349, 0.715349, 0.715349, 0.715349, 0.715349",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.425553, 0.690723, 0.949925, 1.386107, 2.258472",\ + "0.451315, 0.716485, 0.975687, 1.411869, 2.284234",\ + "0.502717, 0.767887, 1.027089, 1.463271, 2.335637",\ + "0.669527, 0.934696, 1.193898, 1.630080, 2.502446",\ + "1.259826, 1.524996, 1.784198, 2.220380, 3.092745",\ + "0.514219, 0.778798, 1.038566, 1.474336, 2.345878",\ + "0.539981, 0.804560, 1.064327, 1.500098, 2.371639",\ + "0.591383, 0.855962, 1.115730, 1.551500, 2.423042",\ + "0.758192, 1.022771, 1.282539, 1.718309, 2.589851",\ + "1.348492, 1.613071, 1.872839, 2.308609, 3.180151",\ + "0.607026, 0.871921, 1.130291, 1.566500, 2.438920",\ + "0.632787, 0.897683, 1.156053, 1.592262, 2.464681",\ + "0.684190, 0.949085, 1.207455, 1.643664, 2.516083",\ + "0.850999, 1.115894, 1.374264, 1.810474, 2.682893",\ + "1.441299, 1.706194, 1.964564, 2.400774, 3.273192",\ + "0.672748, 0.940455, 1.197311, 1.633351, 2.505431",\ + "0.698510, 0.966217, 1.223073, 1.659112, 2.531192",\ + "0.749912, 1.017619, 1.274475, 1.710515, 2.582595",\ + "0.916721, 1.184428, 1.441284, 1.877324, 2.749404",\ + "1.507021, 1.774728, 2.031584, 2.467624, 3.339704",\ + "1.018538, 1.320954, 1.567941, 2.002482, 2.871564",\ + "1.044299, 1.346715, 1.593703, 2.028244, 2.897326",\ + "1.095702, 1.398118, 1.645105, 2.079646, 2.948728",\ + "1.262511, 1.564927, 1.811914, 2.246455, 3.115537",\ + "1.852811, 2.155227, 2.402214, 2.836755, 3.705837"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.040698, 0.040698, 0.040698, 0.040698, 0.040698",\ + "0.070039, 0.070039, 0.070039, 0.070039, 0.070038",\ + "0.145874, 0.145874, 0.145874, 0.145874, 0.145874",\ + "0.444024, 0.444024, 0.444024, 0.444024, 0.444024",\ + "1.524052, 1.524052, 1.524052, 1.524052, 1.524052",\ + "0.040698, 0.040698, 0.040698, 0.040698, 0.040698",\ + "0.070039, 0.070039, 0.070039, 0.070039, 0.070038",\ + "0.145874, 0.145874, 0.145874, 0.145874, 0.145874",\ + "0.444024, 0.444024, 0.444024, 0.444024, 0.444024",\ + "1.524052, 1.524052, 1.524052, 1.524052, 1.524052",\ + "0.040698, 0.040698, 0.040698, 0.040698, 0.040698",\ + "0.070039, 0.070039, 0.070039, 0.070039, 0.070038",\ + "0.145874, 0.145874, 0.145874, 0.145874, 0.145874",\ + "0.444024, 0.444024, 0.444024, 0.444024, 0.444024",\ + "1.524052, 1.524052, 1.524052, 1.524052, 1.524052",\ + "0.040698, 0.040698, 0.040698, 0.040698, 0.040698",\ + "0.070039, 0.070039, 0.070039, 0.070039, 0.070038",\ + "0.145874, 0.145874, 0.145874, 0.145874, 0.145874",\ + "0.444024, 0.444024, 0.444024, 0.444024, 0.444024",\ + "1.524052, 1.524052, 1.524052, 1.524052, 1.524052",\ + "0.040698, 0.040698, 0.040698, 0.040698, 0.040698",\ + "0.070039, 0.070039, 0.070039, 0.070039, 0.070038",\ + "0.145874, 0.145874, 0.145874, 0.145874, 0.145874",\ + "0.444024, 0.444024, 0.444024, 0.444024, 0.444024",\ + "1.524052, 1.524052, 1.524052, 1.524052, 1.524052"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[4]_redg_2534*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + values ( "0.319855, 0.350453, 0.422282, 0.678742, 1.594576",\ + "0.407246, 0.437844, 0.509673, 0.766133, 1.681967",\ + "0.488165, 0.518763, 0.590592, 0.847052, 1.762885",\ + "0.545906, 0.576503, 0.648333, 0.904793, 1.820624",\ + "0.849219, 0.879552, 0.951038, 1.207499, 2.123717"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + values ( "0.040034, 0.086005, 0.217203, 0.715311, 2.463217",\ + "0.040034, 0.086005, 0.217274, 0.715311, 2.463217",\ + "0.040034, 0.086006, 0.217512, 0.715311, 2.463317",\ + "0.040035, 0.086006, 0.217512, 0.715311, 2.463317",\ + "0.040226, 0.086033, 0.217850, 0.715337, 2.463779"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + values ( "0.305437, 0.331199, 0.382601, 0.549410, 1.139710",\ + "0.392830, 0.418591, 0.469994, 0.636803, 1.227103",\ + "0.473699, 0.499461, 0.550863, 0.717672, 1.307972",\ + "0.531348, 0.557110, 0.608512, 0.775321, 1.365621",\ + "0.834004, 0.859766, 0.911168, 1.077978, 1.668277"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + values ( "0.040698, 0.070039, 0.145874, 0.444024, 1.524451",\ + "0.040698, 0.070039, 0.145874, 0.444024, 1.524451",\ + "0.040698, 0.070039, 0.145874, 0.444024, 1.524451",\ + "0.040698, 0.070039, 0.145874, 0.444024, 1.524451",\ + "0.040713, 0.070039, 0.145879, 0.444024, 1.524451"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[4]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[0]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.513066, 0.693179, 0.880758, 1.182738, 1.765834",\ + "0.542527, 0.722641, 0.910219, 1.212199, 1.795295",\ + "0.613598, 0.793711, 0.981290, 1.283270, 1.866366",\ + "0.869826, 1.049940, 1.237518, 1.539498, 2.122594",\ + "1.786688, 1.966801, 2.154380, 2.456360, 3.039456",\ + "0.598004, 0.778015, 0.965828, 1.268244, 1.852212",\ + "0.627466, 0.807477, 0.995290, 1.297706, 1.881674",\ + "0.698536, 0.878547, 1.066360, 1.368776, 1.952744",\ + "0.954764, 1.134775, 1.322588, 1.625004, 2.208972",\ + "1.871626, 2.051637, 2.239450, 2.541866, 3.125834",\ + "0.673916, 0.853459, 1.040637, 1.342841, 1.926384",\ + "0.703378, 0.882920, 1.070099, 1.372302, 1.955846",\ + "0.774448, 0.953991, 1.141169, 1.443373, 2.026917",\ + "1.030676, 1.210219, 1.397397, 1.699601, 2.283145",\ + "1.947538, 2.127081, 2.314259, 2.616463, 3.200006",\ + "0.728285, 0.908210, 1.095526, 1.397446, 1.980702",\ + "0.757747, 0.937672, 1.124987, 1.426908, 2.010164",\ + "0.828817, 1.008742, 1.196058, 1.497978, 2.081234",\ + "1.085046, 1.264970, 1.452286, 1.754207, 2.337462",\ + "2.001907, 2.181832, 2.369148, 2.671068, 3.254324",\ + "1.009880, 1.193775, 1.379701, 1.681172, 2.263979",\ + "1.039342, 1.223237, 1.409163, 1.710634, 2.293441",\ + "1.110412, 1.294307, 1.480233, 1.781705, 2.364511",\ + "1.366640, 1.550535, 1.736461, 2.037933, 2.620739",\ + "2.283502, 2.467397, 2.653323, 2.954794, 3.537601"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.036484, 0.036484, 0.036484, 0.036484, 0.036484",\ + "0.083490, 0.083490, 0.083490, 0.083490, 0.083490",\ + "0.215720, 0.215720, 0.215720, 0.215720, 0.215720",\ + "0.705638, 0.705638, 0.705638, 0.705638, 0.705639",\ + "2.456797, 2.456797, 2.456797, 2.456797, 2.456796",\ + "0.036484, 0.036484, 0.036484, 0.036484, 0.036484",\ + "0.083490, 0.083490, 0.083490, 0.083490, 0.083490",\ + "0.215720, 0.215720, 0.215720, 0.215720, 0.215720",\ + "0.705638, 0.705638, 0.705638, 0.705638, 0.705639",\ + "2.456797, 2.456797, 2.456797, 2.456797, 2.456796",\ + "0.036484, 0.036484, 0.036484, 0.036484, 0.036484",\ + "0.083490, 0.083490, 0.083490, 0.083490, 0.083490",\ + "0.215720, 0.215720, 0.215720, 0.215720, 0.215720",\ + "0.705638, 0.705638, 0.705638, 0.705638, 0.705639",\ + "2.456797, 2.456797, 2.456797, 2.456797, 2.456796",\ + "0.036484, 0.036484, 0.036484, 0.036484, 0.036484",\ + "0.083490, 0.083490, 0.083490, 0.083490, 0.083490",\ + "0.215720, 0.215720, 0.215720, 0.215720, 0.215720",\ + "0.705638, 0.705638, 0.705638, 0.705638, 0.705639",\ + "2.456797, 2.456797, 2.456797, 2.456797, 2.456796",\ + "0.036484, 0.036484, 0.036484, 0.036484, 0.036484",\ + "0.083490, 0.083490, 0.083490, 0.083490, 0.083490",\ + "0.215720, 0.215720, 0.215720, 0.215720, 0.215720",\ + "0.705638, 0.705638, 0.705638, 0.705638, 0.705639",\ + "2.456797, 2.456797, 2.456797, 2.456797, 2.456796"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.386409, 0.654020, 0.915421, 1.355198, 2.234359",\ + "0.410259, 0.677869, 0.939270, 1.379047, 2.258208",\ + "0.459812, 0.727422, 0.988823, 1.428600, 2.307761",\ + "0.625736, 0.893347, 1.154748, 1.594525, 2.473686",\ + "1.214590, 1.482201, 1.743601, 2.183378, 3.062539",\ + "0.475113, 0.742095, 1.004062, 1.443427, 2.321764",\ + "0.498963, 0.765944, 1.027911, 1.467276, 2.345613",\ + "0.548516, 0.815497, 1.077464, 1.516829, 2.395166",\ + "0.714441, 0.981422, 1.243389, 1.682754, 2.561091",\ + "1.303294, 1.570276, 1.832242, 2.271607, 3.149944",\ + "0.568056, 0.835415, 1.096106, 1.535673, 2.414806",\ + "0.591905, 0.859264, 1.119956, 1.559522, 2.438655",\ + "0.641458, 0.908817, 1.169509, 1.609075, 2.488208",\ + "0.807383, 1.074742, 1.335433, 1.775000, 2.654133",\ + "1.396236, 1.663596, 1.924287, 2.363853, 3.242986",\ + "0.633899, 0.903979, 1.163162, 1.602684, 2.481728",\ + "0.657749, 0.927829, 1.187012, 1.626534, 2.505577",\ + "0.707301, 0.977382, 1.236565, 1.676086, 2.555130",\ + "0.873226, 1.143306, 1.402490, 1.842011, 2.721055",\ + "1.462080, 1.732160, 1.991343, 2.430865, 3.309908",\ + "0.980421, 1.284815, 1.533833, 1.971910, 2.848063",\ + "1.004270, 1.308664, 1.557683, 1.995759, 2.871912",\ + "1.053823, 1.358217, 1.607235, 2.045312, 2.921465",\ + "1.219748, 1.524142, 1.773160, 2.211237, 3.087390",\ + "1.808601, 2.112996, 2.362014, 2.800090, 3.676243"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.032904, 0.032904, 0.032904, 0.032904, 0.032904",\ + "0.061453, 0.061453, 0.061453, 0.061453, 0.061453",\ + "0.139114, 0.139114, 0.139114, 0.139114, 0.139114",\ + "0.439459, 0.439459, 0.439459, 0.439459, 0.439460",\ + "1.519040, 1.519040, 1.519040, 1.519040, 1.519040",\ + "0.032904, 0.032904, 0.032904, 0.032904, 0.032904",\ + "0.061453, 0.061453, 0.061453, 0.061453, 0.061453",\ + "0.139114, 0.139114, 0.139114, 0.139114, 0.139114",\ + "0.439459, 0.439459, 0.439459, 0.439459, 0.439460",\ + "1.519040, 1.519040, 1.519040, 1.519040, 1.519040",\ + "0.032904, 0.032904, 0.032904, 0.032904, 0.032904",\ + "0.061453, 0.061453, 0.061453, 0.061453, 0.061453",\ + "0.139114, 0.139114, 0.139114, 0.139114, 0.139114",\ + "0.439459, 0.439459, 0.439459, 0.439459, 0.439460",\ + "1.519040, 1.519040, 1.519040, 1.519040, 1.519040",\ + "0.032904, 0.032904, 0.032904, 0.032904, 0.032904",\ + "0.061453, 0.061453, 0.061453, 0.061453, 0.061453",\ + "0.139114, 0.139114, 0.139114, 0.139114, 0.139114",\ + "0.439459, 0.439459, 0.439459, 0.439459, 0.439460",\ + "1.519040, 1.519040, 1.519040, 1.519040, 1.519040",\ + "0.032904, 0.032904, 0.032904, 0.032904, 0.032904",\ + "0.061453, 0.061453, 0.061453, 0.061453, 0.061453",\ + "0.139114, 0.139114, 0.139114, 0.139114, 0.139114",\ + "0.439459, 0.439459, 0.439459, 0.439459, 0.439460",\ + "1.519040, 1.519040, 1.519040, 1.519040, 1.519040"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[4]_redg_min_2475*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[1]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.421174, 0.684705, 0.960825, 1.428958, 2.363963",\ + "0.450636, 0.714167, 0.990287, 1.458419, 2.393425",\ + "0.521706, 0.785238, 1.061357, 1.529490, 2.464495",\ + "0.777934, 1.041466, 1.317585, 1.785718, 2.720724",\ + "1.694796, 1.958328, 2.234447, 2.702580, 3.637585",\ + "0.509368, 0.772246, 1.048392, 1.515673, 2.449897",\ + "0.538830, 0.801708, 1.077854, 1.545135, 2.479358",\ + "0.609900, 0.872778, 1.148924, 1.616205, 2.550429",\ + "0.866129, 1.129006, 1.405152, 1.872433, 2.806657",\ + "1.782991, 2.045868, 2.322014, 2.789295, 3.723519",\ + "0.597685, 0.861225, 1.136357, 1.603313, 2.536852",\ + "0.627146, 0.890687, 1.165819, 1.632775, 2.566314",\ + "0.698217, 0.961758, 1.236889, 1.703845, 2.637384",\ + "0.954445, 1.217986, 1.493117, 1.960074, 2.893612",\ + "1.871307, 2.134848, 2.409979, 2.876935, 3.810474",\ + "0.660181, 0.926859, 1.200497, 1.667402, 2.600361",\ + "0.689642, 0.956321, 1.229958, 1.696864, 2.629822",\ + "0.760713, 1.027391, 1.301029, 1.767934, 2.700893",\ + "1.016941, 1.283619, 1.557257, 2.024162, 2.957121",\ + "1.933803, 2.200481, 2.474119, 2.941024, 3.873983",\ + "0.989306, 1.291174, 1.552361, 2.016846, 2.945817",\ + "1.018768, 1.320636, 1.581822, 2.046308, 2.975279",\ + "1.089838, 1.391706, 1.652893, 2.117378, 3.046349",\ + "1.346066, 1.647934, 1.909121, 2.373606, 3.302577",\ + "2.262928, 2.564796, 2.825983, 3.290468, 4.219439"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.036484, 0.036484, 0.036484, 0.036485, 0.036485",\ + "0.083490, 0.083490, 0.083490, 0.083490, 0.083490",\ + "0.215720, 0.215720, 0.215720, 0.215720, 0.215721",\ + "0.705638, 0.705639, 0.705640, 0.705642, 0.705647",\ + "2.456797, 2.456796, 2.456794, 2.456789, 2.456778",\ + "0.036484, 0.036484, 0.036484, 0.036485, 0.036485",\ + "0.083490, 0.083490, 0.083490, 0.083490, 0.083490",\ + "0.215720, 0.215720, 0.215720, 0.215720, 0.215721",\ + "0.705638, 0.705639, 0.705640, 0.705642, 0.705647",\ + "2.456797, 2.456796, 2.456794, 2.456789, 2.456778",\ + "0.036484, 0.036484, 0.036484, 0.036485, 0.036485",\ + "0.083490, 0.083490, 0.083490, 0.083490, 0.083490",\ + "0.215720, 0.215720, 0.215720, 0.215720, 0.215721",\ + "0.705638, 0.705639, 0.705640, 0.705642, 0.705647",\ + "2.456797, 2.456796, 2.456794, 2.456789, 2.456778",\ + "0.036484, 0.036484, 0.036484, 0.036485, 0.036485",\ + "0.083490, 0.083490, 0.083490, 0.083490, 0.083490",\ + "0.215720, 0.215720, 0.215720, 0.215720, 0.215721",\ + "0.705638, 0.705639, 0.705640, 0.705642, 0.705647",\ + "2.456797, 2.456796, 2.456794, 2.456789, 2.456778",\ + "0.036484, 0.036484, 0.036484, 0.036485, 0.036485",\ + "0.083490, 0.083490, 0.083490, 0.083490, 0.083490",\ + "0.215720, 0.215720, 0.215720, 0.215720, 0.215721",\ + "0.705638, 0.705639, 0.705640, 0.705642, 0.705647",\ + "2.456797, 2.456796, 2.456794, 2.456789, 2.456778"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.369364, 0.551422, 0.747656, 1.056837, 1.651321",\ + "0.393214, 0.575271, 0.771505, 1.080686, 1.675170",\ + "0.442767, 0.624824, 0.821058, 1.130239, 1.724723",\ + "0.608691, 0.790749, 0.986983, 1.296166, 1.890653",\ + "1.197545, 1.379603, 1.575836, 1.885017, 2.479500",\ + "0.456779, 0.638740, 0.834936, 1.144142, 1.738674",\ + "0.480629, 0.662590, 0.858786, 1.167991, 1.762524",\ + "0.530181, 0.712143, 0.908339, 1.217544, 1.812076",\ + "0.696106, 0.878068, 1.074264, 1.383471, 1.978007",\ + "1.284960, 1.466921, 1.663117, 1.972322, 2.566853",\ + "0.537655, 0.719077, 0.914963, 1.224170, 1.818706",\ + "0.561505, 0.742927, 0.938813, 1.248020, 1.842555",\ + "0.611058, 0.792479, 0.988366, 1.297573, 1.892108",\ + "0.776982, 0.958404, 1.154291, 1.463499, 2.058038",\ + "1.365836, 1.547258, 1.743144, 2.052350, 2.646885",\ + "0.595302, 0.776914, 0.972699, 1.281641, 1.875802",\ + "0.619151, 0.800763, 0.996549, 1.305490, 1.899651",\ + "0.668704, 0.850316, 1.046101, 1.355043, 1.949204",\ + "0.834629, 1.016241, 1.212026, 1.520970, 2.115134",\ + "1.423483, 1.605095, 1.800880, 2.109821, 2.703980",\ + "0.897509, 1.082291, 1.276362, 1.584848, 2.178120",\ + "0.921359, 1.106141, 1.300212, 1.608697, 2.201969",\ + "0.970912, 1.155693, 1.349765, 1.658250, 2.251522",\ + "1.136837, 1.321618, 1.515690, 1.824177, 2.417452",\ + "1.725690, 1.910472, 2.104543, 2.413028, 3.006299"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.032902, 0.032902, 0.032902, 0.032902, 0.032902",\ + "0.061453, 0.061453, 0.061453, 0.061453, 0.061453",\ + "0.139113, 0.139113, 0.139113, 0.139113, 0.139113",\ + "0.439438, 0.439438, 0.439438, 0.439438, 0.439438",\ + "1.519040, 1.519040, 1.519040, 1.519041, 1.519042",\ + "0.032902, 0.032902, 0.032902, 0.032902, 0.032902",\ + "0.061453, 0.061453, 0.061453, 0.061453, 0.061453",\ + "0.139113, 0.139113, 0.139113, 0.139113, 0.139113",\ + "0.439438, 0.439438, 0.439438, 0.439438, 0.439438",\ + "1.519040, 1.519040, 1.519040, 1.519041, 1.519042",\ + "0.032902, 0.032902, 0.032902, 0.032902, 0.032902",\ + "0.061453, 0.061453, 0.061453, 0.061453, 0.061453",\ + "0.139113, 0.139113, 0.139113, 0.139113, 0.139113",\ + "0.439438, 0.439438, 0.439438, 0.439438, 0.439438",\ + "1.519040, 1.519040, 1.519040, 1.519041, 1.519042",\ + "0.032902, 0.032902, 0.032902, 0.032902, 0.032902",\ + "0.061453, 0.061453, 0.061453, 0.061453, 0.061453",\ + "0.139113, 0.139113, 0.139113, 0.139113, 0.139113",\ + "0.439438, 0.439438, 0.439438, 0.439438, 0.439438",\ + "1.519040, 1.519040, 1.519040, 1.519041, 1.519042",\ + "0.032902, 0.032902, 0.032902, 0.032902, 0.032902",\ + "0.061453, 0.061453, 0.061453, 0.061453, 0.061453",\ + "0.139113, 0.139113, 0.139113, 0.139113, 0.139113",\ + "0.439438, 0.439438, 0.439438, 0.439438, 0.439438",\ + "1.519040, 1.519040, 1.519040, 1.519041, 1.519042"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[4]_redg_min_2397*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[2]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.417196, 0.676755, 0.948391, 1.404553, 2.315723",\ + "0.446658, 0.706217, 0.977853, 1.434015, 2.345185",\ + "0.517728, 0.777287, 1.048923, 1.505085, 2.416255",\ + "0.773956, 1.033516, 1.305151, 1.761314, 2.672484",\ + "1.690818, 1.950378, 2.222013, 2.678175, 3.589345",\ + "0.505301, 0.764288, 1.035920, 1.491269, 2.401657",\ + "0.534763, 0.793750, 1.065382, 1.520731, 2.431119",\ + "0.605833, 0.864820, 1.136452, 1.591801, 2.502189",\ + "0.862061, 1.121048, 1.392680, 1.848029, 2.758418",\ + "1.778923, 2.037910, 2.309542, 2.764891, 3.675279",\ + "0.593331, 0.853252, 1.123884, 1.578908, 2.488612",\ + "0.622793, 0.882714, 1.153346, 1.608370, 2.518074",\ + "0.693863, 0.953785, 1.224416, 1.679440, 2.589144",\ + "0.950091, 1.210013, 1.480644, 1.935668, 2.845373",\ + "1.866953, 2.126875, 2.397506, 2.852530, 3.762234",\ + "0.655552, 0.918864, 1.188022, 1.642982, 2.552121",\ + "0.685014, 0.948326, 1.217484, 1.672444, 2.581583",\ + "0.756084, 1.019396, 1.288554, 1.743514, 2.652653",\ + "1.012312, 1.275624, 1.544782, 1.999743, 2.908882",\ + "1.929174, 2.192486, 2.461644, 2.916604, 3.825743",\ + "0.982940, 1.282912, 1.539764, 1.992368, 2.897577",\ + "1.012401, 1.312374, 1.569226, 2.021830, 2.927039",\ + "1.083472, 1.383444, 1.640296, 2.092901, 2.998109",\ + "1.339700, 1.639673, 1.896525, 2.349129, 3.254338",\ + "2.256562, 2.556535, 2.813386, 3.265991, 4.171199"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.036484, 0.036484, 0.036485, 0.036485, 0.036486",\ + "0.083490, 0.083490, 0.083490, 0.083490, 0.083490",\ + "0.215720, 0.215720, 0.215720, 0.215720, 0.215721",\ + "0.705638, 0.705639, 0.705640, 0.705645, 0.705653",\ + "2.456797, 2.456796, 2.456792, 2.456783, 2.456766",\ + "0.036484, 0.036484, 0.036485, 0.036485, 0.036486",\ + "0.083490, 0.083490, 0.083490, 0.083490, 0.083490",\ + "0.215720, 0.215720, 0.215720, 0.215720, 0.215721",\ + "0.705638, 0.705639, 0.705640, 0.705645, 0.705653",\ + "2.456797, 2.456796, 2.456792, 2.456783, 2.456766",\ + "0.036484, 0.036484, 0.036485, 0.036485, 0.036486",\ + "0.083490, 0.083490, 0.083490, 0.083490, 0.083490",\ + "0.215720, 0.215720, 0.215720, 0.215720, 0.215721",\ + "0.705638, 0.705639, 0.705640, 0.705645, 0.705653",\ + "2.456797, 2.456796, 2.456792, 2.456783, 2.456766",\ + "0.036484, 0.036484, 0.036485, 0.036485, 0.036486",\ + "0.083490, 0.083490, 0.083490, 0.083490, 0.083490",\ + "0.215720, 0.215720, 0.215720, 0.215720, 0.215721",\ + "0.705638, 0.705639, 0.705640, 0.705645, 0.705653",\ + "2.456797, 2.456796, 2.456792, 2.456783, 2.456766",\ + "0.036484, 0.036484, 0.036485, 0.036485, 0.036486",\ + "0.083490, 0.083490, 0.083490, 0.083490, 0.083490",\ + "0.215720, 0.215720, 0.215720, 0.215720, 0.215721",\ + "0.705638, 0.705639, 0.705641, 0.705645, 0.705653",\ + "2.456797, 2.456795, 2.456792, 2.456783, 2.456766"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.367701, 0.549868, 0.745966, 1.055305, 1.650265",\ + "0.391550, 0.573717, 0.769816, 1.079154, 1.674115",\ + "0.441103, 0.623270, 0.819369, 1.128707, 1.723667",\ + "0.607028, 0.789195, 0.985294, 1.294634, 1.889598",\ + "1.195881, 1.378049, 1.574147, 1.883484, 2.478444",\ + "0.455121, 0.637187, 0.833247, 1.142610, 1.737619",\ + "0.478970, 0.661036, 0.857097, 1.166459, 1.761468",\ + "0.528523, 0.710589, 0.906649, 1.216012, 1.811021",\ + "0.694448, 0.876514, 1.072575, 1.381939, 1.976952",\ + "1.283301, 1.465367, 1.661428, 1.970789, 2.565797",\ + "0.535988, 0.717524, 0.913274, 1.222638, 1.817651",\ + "0.559838, 0.741373, 0.937124, 1.246487, 1.841500",\ + "0.609390, 0.790926, 0.986676, 1.296040, 1.891052",\ + "0.775315, 0.956851, 1.152602, 1.461967, 2.056983",\ + "1.364169, 1.545704, 1.741455, 2.050818, 2.645829",\ + "0.593627, 0.775360, 0.971009, 1.280109, 1.874747",\ + "0.617477, 0.799210, 0.994859, 1.303958, 1.898596",\ + "0.667029, 0.848763, 1.044412, 1.353511, 1.948149",\ + "0.832954, 1.014688, 1.210337, 1.519438, 2.114080",\ + "1.421808, 1.603541, 1.799190, 2.108289, 2.702925",\ + "0.895722, 1.080739, 1.274673, 1.583317, 2.177067",\ + "0.919572, 1.104588, 1.298523, 1.607166, 2.200916",\ + "0.969124, 1.154141, 1.348075, 1.656719, 2.250468",\ + "1.135049, 1.320066, 1.514001, 1.822646, 2.416399",\ + "1.723903, 1.908919, 2.102854, 2.411496, 3.005245"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.032902, 0.032902, 0.032902, 0.032902, 0.032902",\ + "0.061453, 0.061453, 0.061453, 0.061453, 0.061454",\ + "0.139113, 0.139113, 0.139113, 0.139113, 0.139113",\ + "0.439435, 0.439435, 0.439435, 0.439435, 0.439435",\ + "1.519040, 1.519040, 1.519040, 1.519041, 1.519043",\ + "0.032902, 0.032902, 0.032902, 0.032902, 0.032902",\ + "0.061453, 0.061453, 0.061453, 0.061453, 0.061454",\ + "0.139113, 0.139113, 0.139113, 0.139113, 0.139113",\ + "0.439435, 0.439435, 0.439435, 0.439435, 0.439435",\ + "1.519040, 1.519040, 1.519040, 1.519041, 1.519043",\ + "0.032902, 0.032902, 0.032902, 0.032902, 0.032902",\ + "0.061453, 0.061453, 0.061453, 0.061453, 0.061454",\ + "0.139113, 0.139113, 0.139113, 0.139113, 0.139113",\ + "0.439435, 0.439435, 0.439435, 0.439435, 0.439435",\ + "1.519040, 1.519040, 1.519040, 1.519041, 1.519043",\ + "0.032902, 0.032902, 0.032902, 0.032902, 0.032902",\ + "0.061453, 0.061453, 0.061453, 0.061453, 0.061454",\ + "0.139113, 0.139113, 0.139113, 0.139113, 0.139113",\ + "0.439435, 0.439435, 0.439435, 0.439435, 0.439435",\ + "1.519040, 1.519040, 1.519040, 1.519041, 1.519043",\ + "0.032902, 0.032902, 0.032902, 0.032902, 0.032902",\ + "0.061453, 0.061453, 0.061453, 0.061453, 0.061454",\ + "0.139113, 0.139113, 0.139113, 0.139113, 0.139113",\ + "0.439435, 0.439435, 0.439435, 0.439435, 0.439435",\ + "1.519040, 1.519040, 1.519040, 1.519041, 1.519043"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[4]_redg_min_2338*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[3]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.509479, 0.687819, 0.868166, 1.154352, 1.705105",\ + "0.538941, 0.717281, 0.897627, 1.183814, 1.734567",\ + "0.610011, 0.788351, 0.968698, 1.254884, 1.805637",\ + "0.866239, 1.044579, 1.224926, 1.511112, 2.061866",\ + "1.783101, 1.961441, 2.141788, 2.427974, 2.978728",\ + "0.594418, 0.772655, 0.953236, 1.239858, 1.791484",\ + "0.623879, 0.802116, 0.982697, 1.269320, 1.820946",\ + "0.694950, 0.873187, 1.053768, 1.340390, 1.892016",\ + "0.951178, 1.129415, 1.309996, 1.596619, 2.148244",\ + "1.868040, 2.046277, 2.226858, 2.513480, 3.065106",\ + "0.670324, 0.848098, 1.028045, 1.314455, 1.865656",\ + "0.699786, 0.877560, 1.057506, 1.343917, 1.895118",\ + "0.770856, 0.948630, 1.128577, 1.414987, 1.966188",\ + "1.027084, 1.204858, 1.384805, 1.671215, 2.222416",\ + "1.943946, 2.121720, 2.301667, 2.588077, 3.139278",\ + "0.724676, 0.902843, 1.082910, 1.369049, 1.919973",\ + "0.754138, 0.932305, 1.112372, 1.398511, 1.949435",\ + "0.825208, 1.003376, 1.183442, 1.469581, 2.020505",\ + "1.081436, 1.259604, 1.439670, 1.725809, 2.276733",\ + "1.998298, 2.176466, 2.356532, 2.642671, 3.193595",\ + "1.006098, 1.188361, 1.367063, 1.652775, 2.203251",\ + "1.035560, 1.217823, 1.396525, 1.682237, 2.232713",\ + "1.106630, 1.288893, 1.467595, 1.753307, 2.303783",\ + "1.362858, 1.545121, 1.723823, 2.009535, 2.560011",\ + "2.279720, 2.461983, 2.640685, 2.926397, 3.476873"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.036484, 0.036484, 0.036484, 0.036484, 0.036484",\ + "0.083490, 0.083490, 0.083490, 0.083490, 0.083490",\ + "0.215720, 0.215720, 0.215720, 0.215720, 0.215720",\ + "0.705638, 0.705638, 0.705638, 0.705638, 0.705639",\ + "2.456797, 2.456797, 2.456797, 2.456796, 2.456796",\ + "0.036484, 0.036484, 0.036484, 0.036484, 0.036484",\ + "0.083490, 0.083490, 0.083490, 0.083490, 0.083490",\ + "0.215720, 0.215720, 0.215720, 0.215720, 0.215720",\ + "0.705638, 0.705638, 0.705638, 0.705638, 0.705639",\ + "2.456797, 2.456797, 2.456797, 2.456796, 2.456796",\ + "0.036484, 0.036484, 0.036484, 0.036484, 0.036484",\ + "0.083490, 0.083490, 0.083490, 0.083490, 0.083490",\ + "0.215720, 0.215720, 0.215720, 0.215720, 0.215720",\ + "0.705638, 0.705638, 0.705638, 0.705638, 0.705639",\ + "2.456797, 2.456797, 2.456797, 2.456796, 2.456796",\ + "0.036484, 0.036484, 0.036484, 0.036484, 0.036484",\ + "0.083490, 0.083490, 0.083490, 0.083490, 0.083490",\ + "0.215720, 0.215720, 0.215720, 0.215720, 0.215720",\ + "0.705638, 0.705638, 0.705638, 0.705638, 0.705639",\ + "2.456797, 2.456797, 2.456797, 2.456796, 2.456796",\ + "0.036484, 0.036484, 0.036484, 0.036484, 0.036484",\ + "0.083490, 0.083490, 0.083490, 0.083490, 0.083490",\ + "0.215720, 0.215720, 0.215720, 0.215720, 0.215720",\ + "0.705638, 0.705638, 0.705638, 0.705638, 0.705639",\ + "2.456797, 2.456797, 2.456797, 2.456796, 2.456796"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.384973, 0.649972, 0.909002, 1.345266, 2.217413",\ + "0.408823, 0.673822, 0.932851, 1.369116, 2.241262",\ + "0.458376, 0.723375, 0.982404, 1.418669, 2.290815",\ + "0.624300, 0.889300, 1.148329, 1.584594, 2.456740",\ + "1.213154, 1.478153, 1.737183, 2.173447, 3.045593",\ + "0.473639, 0.738047, 0.997643, 1.433495, 2.304818",\ + "0.497488, 0.761897, 1.021492, 1.457345, 2.328667",\ + "0.547041, 0.811450, 1.071045, 1.506897, 2.378220",\ + "0.712966, 0.977375, 1.236970, 1.672822, 2.544145",\ + "1.301819, 1.566228, 1.825824, 2.261676, 3.132998",\ + "0.566446, 0.831341, 1.089678, 1.525738, 2.397860",\ + "0.590295, 0.855190, 1.113528, 1.549588, 2.421709",\ + "0.639848, 0.904743, 1.163080, 1.599141, 2.471262",\ + "0.805773, 1.070668, 1.329005, 1.765066, 2.637187",\ + "1.394626, 1.659522, 1.917859, 2.353919, 3.226040",\ + "0.632168, 0.899875, 1.156733, 1.592745, 2.464769",\ + "0.656018, 0.923725, 1.180583, 1.616595, 2.488619",\ + "0.705570, 0.973277, 1.230135, 1.666147, 2.538172",\ + "0.871495, 1.139202, 1.396060, 1.832072, 2.704097",\ + "1.460349, 1.728056, 1.984914, 2.420926, 3.292950",\ + "0.977957, 1.280373, 1.527371, 1.961946, 2.831096",\ + "1.001807, 1.304223, 1.551221, 1.985796, 2.854946",\ + "1.051360, 1.353776, 1.600773, 2.035348, 2.904499",\ + "1.217285, 1.519701, 1.766698, 2.201273, 3.070424",\ + "1.806138, 2.108554, 2.355552, 2.790127, 3.659277"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.032904, 0.032904, 0.032904, 0.032904, 0.032904",\ + "0.061453, 0.061453, 0.061453, 0.061453, 0.061453",\ + "0.139114, 0.139114, 0.139114, 0.139114, 0.139114",\ + "0.439459, 0.439459, 0.439459, 0.439459, 0.439460",\ + "1.519040, 1.519040, 1.519040, 1.519040, 1.519040",\ + "0.032904, 0.032904, 0.032904, 0.032904, 0.032904",\ + "0.061453, 0.061453, 0.061453, 0.061453, 0.061453",\ + "0.139114, 0.139114, 0.139114, 0.139114, 0.139114",\ + "0.439459, 0.439459, 0.439459, 0.439459, 0.439460",\ + "1.519040, 1.519040, 1.519040, 1.519040, 1.519040",\ + "0.032904, 0.032904, 0.032904, 0.032904, 0.032904",\ + "0.061453, 0.061453, 0.061453, 0.061453, 0.061453",\ + "0.139114, 0.139114, 0.139114, 0.139114, 0.139114",\ + "0.439459, 0.439459, 0.439459, 0.439459, 0.439460",\ + "1.519040, 1.519040, 1.519040, 1.519040, 1.519040",\ + "0.032904, 0.032904, 0.032904, 0.032904, 0.032904",\ + "0.061453, 0.061453, 0.061453, 0.061453, 0.061453",\ + "0.139114, 0.139114, 0.139114, 0.139114, 0.139114",\ + "0.439459, 0.439459, 0.439459, 0.439459, 0.439460",\ + "1.519040, 1.519040, 1.519040, 1.519040, 1.519040",\ + "0.032904, 0.032904, 0.032904, 0.032904, 0.032904",\ + "0.061453, 0.061453, 0.061453, 0.061453, 0.061453",\ + "0.139114, 0.139114, 0.139114, 0.139114, 0.139114",\ + "0.439459, 0.439459, 0.439459, 0.439459, 0.439460",\ + "1.519040, 1.519040, 1.519040, 1.519040, 1.519040"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[4]_redg_min_2281*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + values ( "0.137483, 0.167263, 0.238963, 0.495239, 1.411098",\ + "0.225669, 0.255448, 0.327158, 0.583483, 1.499024",\ + "0.313993, 0.343772, 0.415484, 0.672004, 1.587106",\ + "0.376583, 0.406365, 0.478019, 0.734834, 1.650402",\ + "0.706456, 0.736253, 0.807711, 1.064965, 1.982165"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + values ( "0.036484, 0.083490, 0.215720, 0.705638, 2.456797",\ + "0.036484, 0.083490, 0.215720, 0.705638, 2.456797",\ + "0.036484, 0.083490, 0.215720, 0.705638, 2.456797",\ + "0.036484, 0.083490, 0.215720, 0.705638, 2.456797",\ + "0.036484, 0.083490, 0.215720, 0.705638, 2.456797"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + values ( "0.176752, 0.200264, 0.249493, 0.415210, 1.004034",\ + "0.264156, 0.287668, 0.336897, 0.502613, 1.091438",\ + "0.345055, 0.368563, 0.417796, 0.583517, 1.172351",\ + "0.402719, 0.426221, 0.475463, 0.641191, 1.230042",\ + "0.705079, 0.728567, 0.777838, 0.943636, 1.532658"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + values ( "0.032905, 0.061452, 0.139114, 0.438652, 1.518506",\ + "0.032905, 0.061452, 0.139114, 0.438651, 1.518506",\ + "0.032905, 0.061452, 0.139114, 0.438651, 1.518304",\ + "0.032905, 0.061452, 0.139114, 0.438651, 1.517928",\ + "0.032905, 0.061452, 0.139114, 0.438651, 1.516755"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[4]_redg_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + values ( "0.078780, 0.108904, 0.180162, 0.436350, 1.354954",\ + "0.161131, 0.191551, 0.262992, 0.519079, 1.434794",\ + "0.248818, 0.281701, 0.353526, 0.609224, 1.527520",\ + "0.395442, 0.436624, 0.511587, 0.767048, 1.680857",\ + "0.628254, 0.688519, 0.779900, 1.032171, 1.943170"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + values ( "0.039260, 0.084846, 0.216310, 0.712907, 2.472405",\ + "0.040828, 0.085695, 0.216652, 0.713345, 2.472405",\ + "0.053126, 0.092383, 0.217457, 0.713345, 2.472405",\ + "0.083384, 0.114454, 0.223298, 0.713345, 2.472405",\ + "0.146832, 0.172946, 0.257648, 0.713345, 2.472405"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + values ( "0.111195, 0.136417, 0.187667, 0.354647, 0.943283",\ + "0.190886, 0.217040, 0.268217, 0.434338, 1.024857",\ + "0.290624, 0.318413, 0.371169, 0.537479, 1.127671",\ + "0.459778, 0.495342, 0.553556, 0.720468, 1.308289",\ + "0.729543, 0.783345, 0.859617, 1.032769, 1.617997"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + values ( "0.039937, 0.069327, 0.145375, 0.445019, 1.525316",\ + "0.040361, 0.069327, 0.145375, 0.445019, 1.525316",\ + "0.050876, 0.076651, 0.148151, 0.445019, 1.525316",\ + "0.080615, 0.101623, 0.163833, 0.445639, 1.525316",\ + "0.141343, 0.163058, 0.212463, 0.458329, 1.525316"); + } + + } /* end of arc padmux2ast_i[4]_obs_ctrl_o[4]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + values ( "0.074275, 0.103763, 0.175018, 0.429970, 1.346996",\ + "0.156202, 0.185726, 0.256855, 0.512618, 1.426492",\ + "0.240487, 0.272170, 0.343383, 0.599128, 1.515415",\ + "0.383350, 0.422200, 0.495747, 0.749948, 1.664120",\ + "0.607487, 0.663633, 0.751277, 1.002826, 1.912977"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + values ( "0.036818, 0.083430, 0.215329, 0.698468, 2.446538",\ + "0.038327, 0.084129, 0.215329, 0.703907, 2.446538",\ + "0.049194, 0.090132, 0.216807, 0.705668, 2.446538",\ + "0.076596, 0.110889, 0.221927, 0.706146, 2.457507",\ + "0.133978, 0.165656, 0.252644, 0.710730, 2.457507"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + values ( "0.080352, 0.102927, 0.151178, 0.316498, 0.906413",\ + "0.165823, 0.188579, 0.236900, 0.401944, 0.996012",\ + "0.261266, 0.287577, 0.337732, 0.502614, 1.091236",\ + "0.421122, 0.455539, 0.512029, 0.676457, 1.262940",\ + "0.677737, 0.731402, 0.807099, 0.979432, 1.563317"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + values ( "0.032503, 0.061295, 0.138759, 0.440292, 1.520208",\ + "0.033685, 0.061572, 0.138902, 0.440292, 1.520208",\ + "0.046324, 0.071119, 0.142587, 0.440292, 1.520208",\ + "0.075437, 0.096388, 0.158394, 0.443652, 1.520208",\ + "0.135609, 0.156947, 0.206102, 0.453960, 1.520208"); + } + + } /* end of arc padmux2ast_i[4]_obs_ctrl_o[4]_una_min*/ + +} /* end of pin obs_ctrl_o[4] */ + +pin("obs_ctrl_o[3]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.644672 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001495 ; + + /* Other user defined attributes. */ + original_pin : obs_ctrl_o[3]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.055709, 0.210088, 0.384212, 0.703085, 1.340832",\ + "0.142647, 0.298162, 0.472853, 0.791314, 1.428237",\ + "0.229323, 0.390455, 0.564578, 0.883479, 1.521279",\ + "0.289539, 0.457859, 0.631598, 0.950329, 1.587790",\ + "0.602001, 0.825705, 1.001142, 1.318707, 1.953837"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.024618, 0.296918, 0.628376, 1.238420, 2.458509",\ + "0.028418, 0.296918, 0.628376, 1.238420, 2.458509",\ + "0.041905, 0.299457, 0.628376, 1.238420, 2.458509",\ + "0.054019, 0.302915, 0.628376, 1.238420, 2.458509",\ + "0.127335, 0.341609, 0.634026, 1.242336, 2.458956"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.067216, 0.173388, 0.285052, 0.487701, 0.892999",\ + "0.152154, 0.258224, 0.370122, 0.573207, 0.979377",\ + "0.227820, 0.333667, 0.444931, 0.647804, 1.053549",\ + "0.281475, 0.388179, 0.499582, 0.702344, 1.107867",\ + "0.555896, 0.671760, 0.783533, 0.986070, 1.391144"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.022975, 0.185702, 0.382816, 0.754065, 1.496563",\ + "0.022975, 0.186685, 0.385279, 0.756173, 1.496563",\ + "0.023515, 0.186685, 0.385279, 0.756173, 1.496563",\ + "0.025086, 0.186685, 0.385279, 0.756173, 1.496563",\ + "0.040851, 0.190393, 0.385279, 0.756173, 1.496563"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[3]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.055709, 0.210088, 0.384212, 0.703085, 1.340832",\ + "0.142647, 0.298162, 0.472853, 0.791314, 1.428237",\ + "0.229323, 0.390455, 0.564578, 0.883479, 1.521279",\ + "0.289539, 0.457859, 0.631598, 0.950329, 1.587790",\ + "0.602001, 0.825705, 1.001142, 1.318707, 1.953837"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.024618, 0.296396, 0.626543, 1.236834, 2.455429",\ + "0.028418, 0.296396, 0.626543, 1.236834, 2.455429",\ + "0.041905, 0.299457, 0.628154, 1.237245, 2.455429",\ + "0.054019, 0.302915, 0.628337, 1.238058, 2.457501",\ + "0.127335, 0.341609, 0.634026, 1.242336, 2.458956"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.067216, 0.173388, 0.285052, 0.487701, 0.892999",\ + "0.152154, 0.258224, 0.370122, 0.573207, 0.979377",\ + "0.227820, 0.333667, 0.444931, 0.647804, 1.053549",\ + "0.281475, 0.388179, 0.499582, 0.702344, 1.107867",\ + "0.555896, 0.671760, 0.783533, 0.986070, 1.391144"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.022975, 0.185506, 0.382814, 0.754047, 1.494909",\ + "0.022975, 0.185506, 0.382814, 0.754047, 1.494909",\ + "0.023515, 0.185506, 0.382814, 0.754047, 1.494909",\ + "0.025086, 0.186032, 0.383438, 0.754322, 1.494909",\ + "0.040851, 0.190393, 0.384028, 0.754322, 1.494909"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[3]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024618, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.205304, 0.155898, 0.121844, 0.108632, 0.118959",\ + "0.213705, 0.164299, 0.130245, 0.117033, 0.127360",\ + "0.286247, 0.236842, 0.202788, 0.189576, 0.199902",\ + "0.377880, 0.328444, 0.294355, 0.281122, 0.291373",\ + "0.826990, 0.777305, 0.742923, 0.729519, 0.739150"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.022975, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.253248, 0.179609, 0.114078, 0.098860, 0.242765",\ + "0.260428, 0.186789, 0.121258, 0.106040, 0.249945",\ + "0.338311, 0.264672, 0.199141, 0.183923, 0.327828",\ + "0.439285, 0.365564, 0.300030, 0.284860, 0.429362",\ + "0.945572, 0.871138, 0.805582, 0.790828, 0.940493"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[3]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024618, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.131653, -0.089547, -0.055448, -0.032345, 0.077315",\ + "-0.140054, -0.097948, -0.063849, -0.040746, 0.068914",\ + "-0.212597, -0.170490, -0.136392, -0.113288, -0.003629",\ + "-0.304160, -0.262036, -0.227893, -0.204765, -0.095035",\ + "-0.752635, -0.710363, -0.675857, -0.652532, -0.542218"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.022975, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.160975, -0.096153, -0.041987, -0.003573, 0.191467",\ + "-0.168149, -0.103327, -0.049161, -0.010747, 0.184293",\ + "-0.246073, -0.181251, -0.127085, -0.088671, 0.106369",\ + "-0.346978, -0.282082, -0.227737, -0.189269, 0.005504",\ + "-0.852619, -0.787096, -0.731202, -0.692284, -0.499800"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[3]_hldr*/ + +} /* end of pin obs_ctrl_o[3] */ + +pin("obs_ctrl_o[2]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001426 ; + + /* Other user defined attributes. */ + original_pin : obs_ctrl_o[2]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.046598, 0.200037, 0.375695, 0.698745, 1.344843",\ + "0.132827, 0.287212, 0.462802, 0.785460, 1.430777",\ + "0.215641, 0.375341, 0.550758, 0.873083, 1.517732",\ + "0.273163, 0.439738, 0.614874, 0.936996, 1.581241",\ + "0.570794, 0.789601, 0.965263, 1.285741, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.021974, 0.297548, 0.631352, 1.248422, 2.482564",\ + "0.026714, 0.298523, 0.633308, 1.248422, 2.482564",\ + "0.039895, 0.300798, 0.633344, 1.248422, 2.482564",\ + "0.051772, 0.304107, 0.633444, 1.248422, 2.482564",\ + "0.126971, 0.342744, 0.639709, 1.250989, 2.482564"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.066407, 0.172211, 0.283842, 0.488142, 0.896743",\ + "0.153827, 0.259530, 0.371123, 0.575447, 0.984097",\ + "0.234160, 0.339867, 0.451150, 0.655476, 1.064128",\ + "0.290795, 0.397415, 0.508694, 0.712721, 1.120776",\ + "0.584007, 0.700750, 0.812328, 1.015736, 1.422553"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.023136, 0.186125, 0.386812, 0.759343, 1.504406",\ + "0.023136, 0.186266, 0.387317, 0.759343, 1.504406",\ + "0.024272, 0.186266, 0.387317, 0.759343, 1.504406",\ + "0.026405, 0.186266, 0.387317, 0.759343, 1.504406",\ + "0.045271, 0.190284, 0.387317, 0.759343, 1.504686"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[2]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.046598, 0.200037, 0.375695, 0.698745, 1.344843",\ + "0.132827, 0.287212, 0.462802, 0.785460, 1.430777",\ + "0.215641, 0.375341, 0.550758, 0.873083, 1.517732",\ + "0.273163, 0.439738, 0.614874, 0.936996, 1.581241",\ + "0.570794, 0.789601, 0.965263, 1.285741, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.021974, 0.297548, 0.631352, 1.247199, 2.473548",\ + "0.026714, 0.298523, 0.633308, 1.247199, 2.473548",\ + "0.039895, 0.300798, 0.633344, 1.247274, 2.473548",\ + "0.051772, 0.304107, 0.633444, 1.248017, 2.473548",\ + "0.126971, 0.342744, 0.639709, 1.250989, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.066407, 0.172211, 0.283842, 0.488142, 0.896743",\ + "0.153827, 0.259530, 0.371123, 0.575447, 0.984097",\ + "0.234160, 0.339867, 0.451150, 0.655476, 1.064128",\ + "0.290795, 0.397415, 0.508694, 0.712721, 1.120776",\ + "0.584007, 0.700750, 0.812328, 1.015736, 1.422553"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.023136, 0.185331, 0.385307, 0.757114, 1.500729",\ + "0.023136, 0.185331, 0.385307, 0.757114, 1.500729",\ + "0.024272, 0.185331, 0.385307, 0.757114, 1.500729",\ + "0.026405, 0.185943, 0.385763, 0.758015, 1.502520",\ + "0.045271, 0.190284, 0.385833, 0.758784, 1.504686"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[2]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.021974, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.215002, 0.169073, 0.138873, 0.127530, 0.141215",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.023136, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.249950, 0.174629, 0.106470, 0.083503, 0.146416",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[2]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.021974, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.146929, -0.104512, -0.070025, -0.030602, 0.275445",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.023136, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.163106, -0.097191, -0.039532, 0.002429, 0.223037",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[2]_hldr*/ + +} /* end of pin obs_ctrl_o[2] */ + +pin("obs_ctrl_o[1]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001497 ; + + /* Other user defined attributes. */ + original_pin : obs_ctrl_o[1]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.046791, 0.200181, 0.375803, 0.698817, 1.344843",\ + "0.133030, 0.287356, 0.462909, 0.785532, 1.430777",\ + "0.215892, 0.375484, 0.550866, 0.873154, 1.517732",\ + "0.273461, 0.439881, 0.614982, 0.937068, 1.581241",\ + "0.571381, 0.789745, 0.965369, 1.285812, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.022232, 0.297820, 0.631558, 1.248559, 2.482564",\ + "0.026946, 0.298797, 0.633513, 1.248559, 2.482564",\ + "0.040098, 0.301070, 0.633549, 1.248559, 2.482564",\ + "0.051979, 0.304374, 0.633649, 1.248559, 2.482564",\ + "0.127230, 0.342977, 0.639913, 1.251125, 2.482564"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.066637, 0.172312, 0.283920, 0.488198, 0.896753",\ + "0.154052, 0.259631, 0.371201, 0.575503, 0.984106",\ + "0.234393, 0.339967, 0.451228, 0.655531, 1.064138",\ + "0.291040, 0.397516, 0.508771, 0.712776, 1.120786",\ + "0.584372, 0.700851, 0.812405, 1.015791, 1.422562"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.023343, 0.186306, 0.386954, 0.759444, 1.504424",\ + "0.023343, 0.186447, 0.387459, 0.759444, 1.504424",\ + "0.024480, 0.186447, 0.387459, 0.759444, 1.504424",\ + "0.026601, 0.186447, 0.387459, 0.759444, 1.504424",\ + "0.045445, 0.190459, 0.387459, 0.759444, 1.504704"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[1]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.046791, 0.200181, 0.375803, 0.698817, 1.344843",\ + "0.133030, 0.287356, 0.462909, 0.785532, 1.430777",\ + "0.215892, 0.375484, 0.550866, 0.873154, 1.517732",\ + "0.273461, 0.439881, 0.614982, 0.937068, 1.581241",\ + "0.571381, 0.789745, 0.965369, 1.285812, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.022232, 0.297820, 0.631558, 1.247336, 2.473548",\ + "0.026946, 0.298797, 0.633513, 1.247336, 2.473548",\ + "0.040098, 0.301070, 0.633549, 1.247411, 2.473548",\ + "0.051979, 0.304374, 0.633649, 1.248154, 2.473548",\ + "0.127230, 0.342977, 0.639913, 1.251125, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.066637, 0.172312, 0.283920, 0.488198, 0.896753",\ + "0.154052, 0.259631, 0.371201, 0.575503, 0.984106",\ + "0.234393, 0.339967, 0.451228, 0.655531, 1.064138",\ + "0.291040, 0.397516, 0.508771, 0.712776, 1.120786",\ + "0.584372, 0.700851, 0.812405, 1.015791, 1.422562"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.023343, 0.185511, 0.385448, 0.757215, 1.500747",\ + "0.023343, 0.185511, 0.385448, 0.757215, 1.500747",\ + "0.024480, 0.185511, 0.385448, 0.757215, 1.500747",\ + "0.026601, 0.186123, 0.385904, 0.758116, 1.502538",\ + "0.045445, 0.190459, 0.385975, 0.758885, 1.504704"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[1]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.022232, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.215122, 0.169193, 0.138993, 0.127649, 0.141334",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.023343, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.250044, 0.174723, 0.106564, 0.083596, 0.146510",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[1]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.022232, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.147049, -0.104632, -0.070145, -0.030722, 0.275326",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.023343, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.163200, -0.097285, -0.039626, 0.002335, 0.222943",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[1]_hldr*/ + +} /* end of pin obs_ctrl_o[1] */ + +pin("obs_ctrl_o[0]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.644672 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001493 ; + + /* Other user defined attributes. */ + original_pin : obs_ctrl_o[0]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.055703, 0.210083, 0.384209, 0.703083, 1.340832",\ + "0.142641, 0.298158, 0.472850, 0.791312, 1.428237",\ + "0.229315, 0.390451, 0.564575, 0.883476, 1.521279",\ + "0.289529, 0.457854, 0.631595, 0.950327, 1.587790",\ + "0.601982, 0.825701, 1.001139, 1.318705, 1.953837"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.024610, 0.296910, 0.628369, 1.238416, 2.458509",\ + "0.028411, 0.296910, 0.628369, 1.238416, 2.458509",\ + "0.041899, 0.299449, 0.628369, 1.238416, 2.458509",\ + "0.054012, 0.302907, 0.628369, 1.238416, 2.458509",\ + "0.127326, 0.341602, 0.634020, 1.242332, 2.458956"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.067218, 0.173389, 0.285054, 0.487703, 0.893002",\ + "0.152156, 0.258225, 0.370124, 0.573210, 0.979381",\ + "0.227822, 0.333668, 0.444933, 0.647806, 1.053553",\ + "0.281477, 0.388180, 0.499584, 0.702346, 1.107870",\ + "0.555899, 0.671761, 0.783535, 0.986072, 1.391148"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.022977, 0.185704, 0.382820, 0.754070, 1.496570",\ + "0.022977, 0.186687, 0.385282, 0.756178, 1.496570",\ + "0.023517, 0.186687, 0.385282, 0.756178, 1.496570",\ + "0.025088, 0.186687, 0.385282, 0.756178, 1.496570",\ + "0.040853, 0.190395, 0.385282, 0.756178, 1.496570"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[0]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.055703, 0.210083, 0.384209, 0.703083, 1.340832",\ + "0.142641, 0.298158, 0.472850, 0.791312, 1.428237",\ + "0.229315, 0.390451, 0.564575, 0.883476, 1.521279",\ + "0.289529, 0.457854, 0.631595, 0.950327, 1.587790",\ + "0.601982, 0.825701, 1.001139, 1.318705, 1.953837"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.024610, 0.296388, 0.626537, 1.236829, 2.455429",\ + "0.028411, 0.296388, 0.626537, 1.236829, 2.455429",\ + "0.041899, 0.299449, 0.628148, 1.237241, 2.455429",\ + "0.054012, 0.302907, 0.628330, 1.238054, 2.457501",\ + "0.127326, 0.341602, 0.634020, 1.242332, 2.458956"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.067218, 0.173389, 0.285054, 0.487703, 0.893002",\ + "0.152156, 0.258225, 0.370124, 0.573210, 0.979381",\ + "0.227822, 0.333668, 0.444933, 0.647806, 1.053553",\ + "0.281477, 0.388180, 0.499584, 0.702346, 1.107870",\ + "0.555899, 0.671761, 0.783535, 0.986072, 1.391148"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.022977, 0.185508, 0.382818, 0.754052, 1.494916",\ + "0.022977, 0.185508, 0.382818, 0.754052, 1.494916",\ + "0.023517, 0.185508, 0.382818, 0.754052, 1.494916",\ + "0.025088, 0.186034, 0.383442, 0.754326, 1.494916",\ + "0.040853, 0.190395, 0.384031, 0.754326, 1.494916"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[0]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024610, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.205304, 0.155898, 0.121844, 0.108632, 0.118959",\ + "0.213701, 0.164296, 0.130242, 0.117030, 0.127356",\ + "0.286247, 0.236842, 0.202788, 0.189576, 0.199902",\ + "0.377880, 0.328444, 0.294355, 0.281122, 0.291373",\ + "0.826990, 0.777305, 0.742923, 0.729519, 0.739150"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.022977, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.253248, 0.179609, 0.114078, 0.098860, 0.242765",\ + "0.260429, 0.186790, 0.121259, 0.106041, 0.249946",\ + "0.338311, 0.264672, 0.199141, 0.183923, 0.327828",\ + "0.439285, 0.365564, 0.300030, 0.284860, 0.429362",\ + "0.945572, 0.871138, 0.805582, 0.790828, 0.940493"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[0]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024610, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.131653, -0.089547, -0.055448, -0.032345, 0.077315",\ + "-0.140051, -0.097944, -0.063846, -0.040742, 0.068917",\ + "-0.212597, -0.170490, -0.136392, -0.113288, -0.003629",\ + "-0.304160, -0.262036, -0.227893, -0.204765, -0.095035",\ + "-0.752635, -0.710363, -0.675857, -0.652532, -0.542218"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.022977, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.160975, -0.096153, -0.041987, -0.003573, 0.191467",\ + "-0.168150, -0.103328, -0.049162, -0.010747, 0.184292",\ + "-0.246073, -0.181251, -0.127085, -0.088671, 0.106369",\ + "-0.346978, -0.282082, -0.227737, -0.189269, 0.005504",\ + "-0.852619, -0.787096, -0.731202, -0.692284, -0.499800"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[0]_hldr*/ + +} /* end of pin obs_ctrl_o[0] */ +} /* end of bus obs_ctrl_o */ +bus ( padmux2ast_i ) { + + bus_type : BUS9_type16 ; + direction : input ; + +pin("padmux2ast_i[8]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001547 ; + + /* Other user defined attributes. */ + original_pin : padmux2ast_i[8]; +} /* end of pin padmux2ast_i[8] */ + +pin("padmux2ast_i[7]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001037 ; + + /* Other user defined attributes. */ + original_pin : padmux2ast_i[7]; + timing () { + related_pin : "clk_ast_usb_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.599931, 0.560765, 0.510135, 0.511231, 0.524547",\ + "0.684459, 0.645293, 0.594663, 0.595759, 0.609075",\ + "0.775549, 0.736383, 0.685753, 0.686849, 0.700165",\ + "0.937661, 0.898495, 0.847865, 0.848961, 0.862277",\ + "1.209352, 1.170186, 1.119556, 1.120651, 1.133968"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.507406, 0.449725, 0.394624, 0.395719, 0.409035",\ + "0.595359, 0.537678, 0.482576, 0.483672, 0.496988",\ + "0.695327, 0.637646, 0.582544, 0.583640, 0.596956",\ + "0.879705, 0.822024, 0.766922, 0.768018, 0.781334",\ + "1.197915, 1.140234, 1.085132, 1.086228, 1.099544"); + } + + } /* end of arc clk_ast_usb_i_padmux2ast_i[7]_stupr*/ + + timing () { + related_pin : "clk_ast_usb_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.288273, -0.255190, -0.196555, -0.182927, -0.017307",\ + "-0.372801, -0.339718, -0.281083, -0.267455, -0.101836",\ + "-0.463895, -0.430812, -0.372177, -0.358549, -0.192930",\ + "-0.625950, -0.592867, -0.534232, -0.520604, -0.354985",\ + "-0.897654, -0.864571, -0.805936, -0.792308, -0.626688"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.249551, -0.198552, -0.102091, -0.083944, 0.136600",\ + "-0.337500, -0.286501, -0.190040, -0.171892, 0.048652",\ + "-0.437474, -0.386475, -0.290014, -0.271866, -0.051323",\ + "-0.621823, -0.570824, -0.474363, -0.456216, -0.235672",\ + "-0.940049, -0.889050, -0.792589, -0.774441, -0.553897"); + } + + } /* end of arc clk_ast_usb_i_padmux2ast_i[7]_hldr*/ + +} /* end of pin padmux2ast_i[7] */ + +pin("padmux2ast_i[6]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001036 ; + + /* Other user defined attributes. */ + original_pin : padmux2ast_i[6]; +} /* end of pin padmux2ast_i[6] */ + +pin("padmux2ast_i[5]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001070 ; + + /* Other user defined attributes. */ + original_pin : padmux2ast_i[5]; + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "590008.937500, 590008.875000, 590008.812500, 590008.812500, 590008.812500",\ + "590009.062500, 590009.000000, 590008.937500, 590008.937500, 590008.937500",\ + "590009.062500, 590009.000000, 590008.937500, 590008.937500, 590008.937500",\ + "590009.187500, 590009.125000, 590009.062500, 590009.062500, 590009.062500",\ + "590009.437500, 590009.375000, 590009.312500, 590009.312500, 590009.312500"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "590007.187500, 590007.125000, 590007.062500, 590007.062500, 590007.062500",\ + "590007.312500, 590007.250000, 590007.187500, 590007.187500, 590007.187500",\ + "590007.437500, 590007.375000, 590007.312500, 590007.312500, 590007.312500",\ + "590007.562500, 590007.500000, 590007.437500, 590007.437500, 590007.437500",\ + "590007.937500, 590007.875000, 590007.812500, 590007.812500, 590007.812500"); + } + + } /* end of arc clk_ast_ext_i_padmux2ast_i[5]_stupr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-590008.312500, -590008.250000, -590008.250000, -590008.125000, -590007.875000",\ + "-590008.312500, -590008.250000, -590008.250000, -590008.125000, -590007.875000",\ + "-590008.437500, -590008.375000, -590008.375000, -590008.250000, -590008.000000",\ + "-590008.562500, -590008.500000, -590008.500000, -590008.375000, -590008.125000",\ + "-590008.812500, -590008.750000, -590008.750000, -590008.625000, -590008.375000"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-590006.625000, -590006.562500, -590006.500000, -590006.375000, -590006.250000",\ + "-590006.750000, -590006.687500, -590006.625000, -590006.500000, -590006.375000",\ + "-590006.875000, -590006.812500, -590006.750000, -590006.625000, -590006.500000",\ + "-590007.000000, -590006.937500, -590006.875000, -590006.750000, -590006.625000",\ + "-590007.250000, -590007.187500, -590007.125000, -590007.000000, -590006.875000"); + } + + } /* end of arc clk_ast_ext_i_padmux2ast_i[5]_hldr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : recovery_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "590008.812500, 590008.750000, 590008.750000, 590008.750000, 590008.750000",\ + "590008.937500, 590008.875000, 590008.875000, 590008.875000, 590008.875000",\ + "590008.937500, 590008.875000, 590008.875000, 590008.875000, 590008.875000",\ + "590009.062500, 590009.000000, 590009.000000, 590009.000000, 590009.000000",\ + "590009.312500, 590009.250000, 590009.250000, 590009.250000, 590009.250000"); + } + + } /* end of arc clk_ast_ext_i_padmux2ast_i[5]_recrr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : recovery_rising ; + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "590007.312500, 590007.312500, 590007.250000, 590007.250000, 590007.312500",\ + "590007.437500, 590007.437500, 590007.375000, 590007.375000, 590007.437500",\ + "590007.562500, 590007.562500, 590007.500000, 590007.500000, 590007.562500",\ + "590007.687500, 590007.687500, 590007.625000, 590007.625000, 590007.687500",\ + "590008.062500, 590008.062500, 590008.000000, 590008.000000, 590008.062500"); + } + + } /* end of arc clk_ast_ext_i_padmux2ast_i[5]_recfr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : removal_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-590007.250000, -590007.250000, -590007.187500, -590007.125000, -590007.000000",\ + "-590007.250000, -590007.250000, -590007.187500, -590007.125000, -590007.000000",\ + "-590007.375000, -590007.375000, -590007.312500, -590007.250000, -590007.125000",\ + "-590007.500000, -590007.500000, -590007.437500, -590007.375000, -590007.250000",\ + "-590007.750000, -590007.750000, -590007.687500, -590007.625000, -590007.500000"); + } + + } /* end of arc clk_ast_ext_i_padmux2ast_i[5]_remrr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : removal_rising ; + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-590007.125000, -590007.125000, -590007.062500, -590007.000000, -590006.875000",\ + "-590007.250000, -590007.250000, -590007.187500, -590007.125000, -590007.000000",\ + "-590007.375000, -590007.375000, -590007.312500, -590007.250000, -590007.125000",\ + "-590007.500000, -590007.500000, -590007.437500, -590007.375000, -590007.250000",\ + "-590007.750000, -590007.750000, -590007.687500, -590007.625000, -590007.500000"); + } + + } /* end of arc clk_ast_ext_i_padmux2ast_i[5]_remfr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : setup_rising ; + clock_gating_flag : true ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "590008.437500, 590008.437500, 590008.437500, 590008.500000, 590008.812500",\ + "590008.562500, 590008.562500, 590008.562500, 590008.625000, 590008.937500",\ + "590008.562500, 590008.562500, 590008.562500, 590008.625000, 590008.937500",\ + "590008.687500, 590008.687500, 590008.687500, 590008.750000, 590009.062500",\ + "590008.937500, 590008.937500, 590008.937500, 590009.000000, 590009.312500"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "590006.687500, 590006.687500, 590006.687500, 590006.687500, 590006.687500",\ + "590006.812500, 590006.812500, 590006.812500, 590006.812500, 590006.812500",\ + "590006.937500, 590006.937500, 590006.937500, 590006.937500, 590006.937500",\ + "590007.062500, 590007.062500, 590007.062500, 590007.062500, 590007.062500",\ + "590007.437500, 590007.437500, 590007.437500, 590007.437500, 590007.437500"); + } + + } /* end of arc clk_ast_ext_i_padmux2ast_i[5]_cgsr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : setup_falling ; + clock_gating_flag : true ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "590008.250000, 590008.250000, 590008.250000, 590008.250000, 590008.250000",\ + "590008.375000, 590008.375000, 590008.375000, 590008.375000, 590008.375000",\ + "590008.375000, 590008.375000, 590008.375000, 590008.375000, 590008.375000",\ + "590008.500000, 590008.500000, 590008.500000, 590008.500000, 590008.500000",\ + "590008.750000, 590008.750000, 590008.750000, 590008.750000, 590008.750000"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "590006.562500, 590006.562500, 590006.562500, 590006.562500, 590006.562500",\ + "590006.687500, 590006.687500, 590006.687500, 590006.687500, 590006.687500",\ + "590006.812500, 590006.812500, 590006.812500, 590006.812500, 590006.812500",\ + "590006.937500, 590006.937500, 590006.937500, 590006.937500, 590006.937500",\ + "590007.312500, 590007.312500, 590007.312500, 590007.312500, 590007.312500"); + } + + } /* end of arc clk_ast_ext_i_padmux2ast_i[5]_cgsf*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : hold_rising ; + clock_gating_flag : true ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-590008.250000, -590008.250000, -590008.250000, -590008.187500, -590008.062500",\ + "-590008.250000, -590008.250000, -590008.250000, -590008.187500, -590008.062500",\ + "-590008.375000, -590008.375000, -590008.375000, -590008.312500, -590008.187500",\ + "-590008.500000, -590008.500000, -590008.500000, -590008.437500, -590008.312500",\ + "-590008.750000, -590008.750000, -590008.750000, -590008.687500, -590008.562500"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-590006.562500, -590006.562500, -590006.437500, -590006.312500, -590006.062500",\ + "-590006.687500, -590006.687500, -590006.562500, -590006.437500, -590006.187500",\ + "-590006.812500, -590006.812500, -590006.687500, -590006.562500, -590006.312500",\ + "-590006.937500, -590006.937500, -590006.812500, -590006.687500, -590006.437500",\ + "-590007.187500, -590007.187500, -590007.062500, -590006.937500, -590006.687500"); + } + + } /* end of arc clk_ast_ext_i_padmux2ast_i[5]_cghr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : hold_falling ; + clock_gating_flag : true ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-590008.250000, -590008.250000, -590008.250000, -590008.250000, -590008.250000",\ + "-590008.250000, -590008.250000, -590008.250000, -590008.250000, -590008.250000",\ + "-590008.375000, -590008.375000, -590008.375000, -590008.375000, -590008.375000",\ + "-590008.500000, -590008.500000, -590008.500000, -590008.500000, -590008.500000",\ + "-590008.750000, -590008.750000, -590008.750000, -590008.750000, -590008.750000"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-590006.562500, -590006.562500, -590006.562500, -590006.562500, -590006.562500",\ + "-590006.687500, -590006.687500, -590006.687500, -590006.687500, -590006.687500",\ + "-590006.812500, -590006.812500, -590006.812500, -590006.812500, -590006.812500",\ + "-590006.937500, -590006.937500, -590006.937500, -590006.937500, -590006.937500",\ + "-590007.187500, -590007.187500, -590007.187500, -590007.187500, -590007.187500"); + } + + } /* end of arc clk_ast_ext_i_padmux2ast_i[5]_cghf*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : recovery_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "590011.500000, 590010.062500, 590009.187500, 590008.812500, 590008.750000",\ + "590011.625000, 590010.187500, 590009.312500, 590008.937500, 590008.875000",\ + "590011.625000, 590010.187500, 590009.312500, 590008.937500, 590008.875000",\ + "590011.750000, 590010.312500, 590009.437500, 590009.062500, 590009.000000",\ + "590012.000000, 590010.562500, 590009.687500, 590009.312500, 590009.250000"); + } + + } /* end of arc clk_ast_tlul_i_padmux2ast_i[5]_recrr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : removal_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-590006.562500, -590006.437500, -590006.375000, -590006.375000, -590006.312500",\ + "-590006.562500, -590006.437500, -590006.375000, -590006.375000, -590006.312500",\ + "-590006.687500, -590006.562500, -590006.500000, -590006.500000, -590006.437500",\ + "-590006.812500, -590006.687500, -590006.625000, -590006.625000, -590006.562500",\ + "-590007.062500, -590006.937500, -590006.875000, -590006.875000, -590006.812500"); + } + + } /* end of arc clk_ast_tlul_i_padmux2ast_i[5]_remrr*/ + +} /* end of pin padmux2ast_i[5] */ + +pin("padmux2ast_i[4]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001489 ; + + /* Other user defined attributes. */ + original_pin : padmux2ast_i[4]; + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "970007.437500, 970007.375000, 970007.312500, 970007.312500, 970007.312500",\ + "970007.562500, 970007.500000, 970007.437500, 970007.437500, 970007.437500",\ + "970007.562500, 970007.500000, 970007.437500, 970007.437500, 970007.437500",\ + "970007.812500, 970007.750000, 970007.687500, 970007.687500, 970007.687500",\ + "970008.062500, 970008.000000, 970007.937500, 970007.937500, 970007.937500"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "970010.562500, 970010.500000, 970010.437500, 970010.437500, 970010.437500",\ + "970010.687500, 970010.625000, 970010.562500, 970010.562500, 970010.562500",\ + "970010.812500, 970010.750000, 970010.687500, 970010.687500, 970010.687500",\ + "970011.062500, 970011.000000, 970010.937500, 970010.937500, 970010.937500",\ + "970011.312500, 970011.250000, 970011.187500, 970011.187500, 970011.187500"); + } + + } /* end of arc clk_ast_ext_i_padmux2ast_i[4]_stupr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : setup_falling ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "380000.312500, 380000.312500, 380000.312500, 380000.312500, 380000.312500",\ + "380000.406250, 380000.406250, 380000.406250, 380000.406250, 380000.406250",\ + "380000.500000, 380000.500000, 380000.500000, 380000.500000, 380000.500000",\ + "380000.656250, 380000.656250, 380000.656250, 380000.656250, 380000.656250",\ + "380000.906250, 380000.906250, 380000.906250, 380000.906250, 380000.906250"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "380001.843750, 380001.843750, 380001.843750, 380001.843750, 380001.843750",\ + "380001.937500, 380001.937500, 380001.937500, 380001.937500, 380001.937500",\ + "380002.062500, 380002.062500, 380002.062500, 380002.062500, 380002.062500",\ + "380002.250000, 380002.250000, 380002.250000, 380002.250000, 380002.250000",\ + "380002.562500, 380002.562500, 380002.562500, 380002.562500, 380002.562500"); + } + + } /* end of arc clk_ast_ext_i_padmux2ast_i[4]_stupf*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-380000.375000, -380000.312500, -380000.281250, -380000.187500, -379999.906250",\ + "-380000.468750, -380000.406250, -380000.375000, -380000.281250, -380000.000000",\ + "-380000.531250, -380000.468750, -380000.437500, -380000.343750, -380000.062500",\ + "-380000.687500, -380000.625000, -380000.593750, -380000.500000, -380000.218750",\ + "-380000.906250, -380000.843750, -380000.812500, -380000.718750, -380000.437500"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-380001.750000, -380001.687500, -380001.656250, -380001.562500, -380001.375000",\ + "-380001.843750, -380001.781250, -380001.750000, -380001.656250, -380001.468750",\ + "-380001.937500, -380001.875000, -380001.843750, -380001.750000, -380001.562500",\ + "-380002.125000, -380002.062500, -380002.031250, -380001.937500, -380001.750000",\ + "-380002.375000, -380002.312500, -380002.281250, -380002.187500, -380002.000000"); + } + + } /* end of arc clk_ast_ext_i_padmux2ast_i[4]_hldr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : hold_falling ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-380000.281250, -380000.281250, -380000.281250, -380000.281250, -380000.281250",\ + "-380000.375000, -380000.375000, -380000.375000, -380000.375000, -380000.375000",\ + "-380000.437500, -380000.437500, -380000.437500, -380000.437500, -380000.437500",\ + "-380000.593750, -380000.593750, -380000.593750, -380000.593750, -380000.593750",\ + "-380000.812500, -380000.812500, -380000.812500, -380000.812500, -380000.812500"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-380001.750000, -380001.750000, -380001.750000, -380001.750000, -380001.750000",\ + "-380001.843750, -380001.843750, -380001.843750, -380001.843750, -380001.843750",\ + "-380001.937500, -380001.937500, -380001.937500, -380001.937500, -380001.937500",\ + "-380002.125000, -380002.125000, -380002.125000, -380002.125000, -380002.125000",\ + "-380002.375000, -380002.375000, -380002.375000, -380002.375000, -380002.375000"); + } + + } /* end of arc clk_ast_ext_i_padmux2ast_i[4]_hldf*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : recovery_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "970007.625000, 970007.562500, 970007.500000, 970007.500000, 970007.562500",\ + "970007.750000, 970007.687500, 970007.625000, 970007.625000, 970007.687500",\ + "970007.750000, 970007.687500, 970007.625000, 970007.625000, 970007.687500",\ + "970008.000000, 970007.937500, 970007.875000, 970007.875000, 970007.937500",\ + "970008.250000, 970008.187500, 970008.125000, 970008.125000, 970008.187500"); + } + + } /* end of arc clk_ast_ext_i_padmux2ast_i[4]_recrr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : recovery_rising ; + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "970010.437500, 970010.375000, 970010.375000, 970010.375000, 970010.375000",\ + "970010.562500, 970010.500000, 970010.500000, 970010.500000, 970010.500000",\ + "970010.687500, 970010.625000, 970010.625000, 970010.625000, 970010.625000",\ + "970010.937500, 970010.875000, 970010.875000, 970010.875000, 970010.875000",\ + "970011.187500, 970011.125000, 970011.125000, 970011.125000, 970011.125000"); + } + + } /* end of arc clk_ast_ext_i_padmux2ast_i[4]_recfr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : recovery_falling ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "380000.500000, 380000.500000, 380000.500000, 380000.500000, 380000.500000",\ + "380000.593750, 380000.593750, 380000.593750, 380000.593750, 380000.593750",\ + "380000.687500, 380000.687500, 380000.687500, 380000.687500, 380000.687500",\ + "380000.843750, 380000.843750, 380000.843750, 380000.843750, 380000.843750",\ + "380001.093750, 380001.093750, 380001.093750, 380001.093750, 380001.093750"); + } + + } /* end of arc clk_ast_ext_i_padmux2ast_i[4]_recrf*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : recovery_falling ; + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "380001.937500, 380001.937500, 380001.937500, 380001.937500, 380001.937500",\ + "380002.031250, 380002.031250, 380002.031250, 380002.031250, 380002.031250",\ + "380002.156250, 380002.156250, 380002.156250, 380002.156250, 380002.156250",\ + "380002.343750, 380002.343750, 380002.343750, 380002.343750, 380002.343750",\ + "380002.656250, 380002.656250, 380002.656250, 380002.656250, 380002.656250"); + } + + } /* end of arc clk_ast_ext_i_padmux2ast_i[4]_recff*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : removal_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-380000.375000, -380000.343750, -380000.281250, -380000.250000, -380000.125000",\ + "-380000.468750, -380000.437500, -380000.375000, -380000.343750, -380000.218750",\ + "-380000.531250, -380000.500000, -380000.437500, -380000.406250, -380000.281250",\ + "-380000.687500, -380000.656250, -380000.593750, -380000.562500, -380000.437500",\ + "-380000.906250, -380000.875000, -380000.812500, -380000.781250, -380000.656250"); + } + + } /* end of arc clk_ast_ext_i_padmux2ast_i[4]_remrr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : removal_rising ; + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-380001.812500, -380001.781250, -380001.718750, -380001.687500, -380001.593750",\ + "-380001.906250, -380001.875000, -380001.812500, -380001.781250, -380001.687500",\ + "-380002.000000, -380001.968750, -380001.906250, -380001.875000, -380001.781250",\ + "-380002.187500, -380002.156250, -380002.093750, -380002.062500, -380001.968750",\ + "-380002.437500, -380002.406250, -380002.343750, -380002.312500, -380002.218750"); + } + + } /* end of arc clk_ast_ext_i_padmux2ast_i[4]_remfr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : removal_falling ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-380000.312500, -380000.312500, -380000.312500, -380000.312500, -380000.312500",\ + "-380000.406250, -380000.406250, -380000.406250, -380000.406250, -380000.406250",\ + "-380000.468750, -380000.468750, -380000.468750, -380000.468750, -380000.468750",\ + "-380000.625000, -380000.625000, -380000.625000, -380000.625000, -380000.625000",\ + "-380000.843750, -380000.843750, -380000.843750, -380000.843750, -380000.843750"); + } + + } /* end of arc clk_ast_ext_i_padmux2ast_i[4]_remrf*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : removal_falling ; + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-380001.750000, -380001.750000, -380001.750000, -380001.750000, -380001.750000",\ + "-380001.843750, -380001.843750, -380001.843750, -380001.843750, -380001.843750",\ + "-380001.937500, -380001.937500, -380001.937500, -380001.937500, -380001.937500",\ + "-380002.125000, -380002.125000, -380002.125000, -380002.125000, -380002.125000",\ + "-380002.375000, -380002.375000, -380002.375000, -380002.375000, -380002.375000"); + } + + } /* end of arc clk_ast_ext_i_padmux2ast_i[4]_remff*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : setup_rising ; + clock_gating_flag : true ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "970006.937500, 970006.937500, 970006.937500, 970006.937500, 970006.937500",\ + "970007.062500, 970007.062500, 970007.062500, 970007.062500, 970007.062500",\ + "970007.062500, 970007.062500, 970007.062500, 970007.062500, 970007.062500",\ + "970007.312500, 970007.312500, 970007.312500, 970007.312500, 970007.312500",\ + "970007.562500, 970007.562500, 970007.562500, 970007.562500, 970007.562500"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "970010.062500, 970010.062500, 970010.062500, 970010.125000, 970010.437500",\ + "970010.187500, 970010.187500, 970010.187500, 970010.250000, 970010.562500",\ + "970010.312500, 970010.312500, 970010.312500, 970010.375000, 970010.687500",\ + "970010.562500, 970010.562500, 970010.562500, 970010.625000, 970010.937500",\ + "970010.812500, 970010.812500, 970010.812500, 970010.875000, 970011.187500"); + } + + } /* end of arc clk_ast_ext_i_padmux2ast_i[4]_cgsr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : setup_falling ; + clock_gating_flag : true ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "970006.812500, 970006.812500, 970006.812500, 970006.812500, 970006.812500",\ + "970006.937500, 970006.937500, 970006.937500, 970006.937500, 970006.937500",\ + "970006.937500, 970006.937500, 970006.937500, 970006.937500, 970006.937500",\ + "970007.187500, 970007.187500, 970007.187500, 970007.187500, 970007.187500",\ + "970007.437500, 970007.437500, 970007.437500, 970007.437500, 970007.437500"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "970009.875000, 970009.875000, 970009.875000, 970009.875000, 970009.875000",\ + "970010.000000, 970010.000000, 970010.000000, 970010.000000, 970010.000000",\ + "970010.125000, 970010.125000, 970010.125000, 970010.125000, 970010.125000",\ + "970010.375000, 970010.375000, 970010.375000, 970010.375000, 970010.375000",\ + "970010.625000, 970010.625000, 970010.625000, 970010.625000, 970010.625000"); + } + + } /* end of arc clk_ast_ext_i_padmux2ast_i[4]_cgsf*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : hold_rising ; + clock_gating_flag : true ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-380000.281250, -380000.218750, -380000.187500, -380000.125000, -380000.000000",\ + "-380000.375000, -380000.312500, -380000.281250, -380000.218750, -380000.093750",\ + "-380000.437500, -380000.375000, -380000.343750, -380000.281250, -380000.156250",\ + "-380000.593750, -380000.531250, -380000.500000, -380000.437500, -380000.312500",\ + "-380000.812500, -380000.750000, -380000.718750, -380000.656250, -380000.531250"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-380001.718750, -380001.625000, -380001.531250, -380001.406250, -380001.125000",\ + "-380001.812500, -380001.718750, -380001.625000, -380001.500000, -380001.218750",\ + "-380001.906250, -380001.812500, -380001.718750, -380001.593750, -380001.312500",\ + "-380002.093750, -380002.000000, -380001.906250, -380001.781250, -380001.500000",\ + "-380002.343750, -380002.250000, -380002.156250, -380002.031250, -380001.750000"); + } + + } /* end of arc clk_ast_ext_i_padmux2ast_i[4]_cghr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : hold_falling ; + clock_gating_flag : true ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-380000.312500, -380000.312500, -380000.312500, -380000.312500, -380000.312500",\ + "-380000.406250, -380000.406250, -380000.406250, -380000.406250, -380000.406250",\ + "-380000.468750, -380000.468750, -380000.468750, -380000.468750, -380000.468750",\ + "-380000.625000, -380000.625000, -380000.625000, -380000.625000, -380000.625000",\ + "-380000.843750, -380000.843750, -380000.843750, -380000.843750, -380000.843750"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-380001.718750, -380001.718750, -380001.718750, -380001.718750, -380001.718750",\ + "-380001.812500, -380001.812500, -380001.812500, -380001.812500, -380001.812500",\ + "-380001.906250, -380001.906250, -380001.906250, -380001.906250, -380001.906250",\ + "-380002.093750, -380002.093750, -380002.093750, -380002.093750, -380002.093750",\ + "-380002.343750, -380002.343750, -380002.343750, -380002.343750, -380002.343750"); + } + + } /* end of arc clk_ast_ext_i_padmux2ast_i[4]_cghf*/ + + timing () { + related_pin : "clk_ast_rng_i" ; + timing_type : recovery_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "380000.500000, 380000.468750, 380000.406250, 380000.406250, 380000.468750",\ + "380000.593750, 380000.562500, 380000.500000, 380000.500000, 380000.562500",\ + "380000.687500, 380000.656250, 380000.593750, 380000.593750, 380000.656250",\ + "380000.843750, 380000.812500, 380000.750000, 380000.750000, 380000.812500",\ + "380001.093750, 380001.062500, 380001.000000, 380001.000000, 380001.062500"); + } + + } /* end of arc clk_ast_rng_i_padmux2ast_i[4]_recrr*/ + + timing () { + related_pin : "clk_ast_rng_i" ; + timing_type : recovery_rising ; + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "380001.968750, 380001.937500, 380001.875000, 380001.875000, 380001.937500",\ + "380002.062500, 380002.031250, 380001.968750, 380001.968750, 380002.031250",\ + "380002.187500, 380002.156250, 380002.093750, 380002.093750, 380002.156250",\ + "380002.375000, 380002.343750, 380002.281250, 380002.281250, 380002.343750",\ + "380002.687500, 380002.656250, 380002.593750, 380002.593750, 380002.656250"); + } + + } /* end of arc clk_ast_rng_i_padmux2ast_i[4]_recfr*/ + + timing () { + related_pin : "clk_ast_rng_i" ; + timing_type : removal_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-380000.343750, -380000.312500, -380000.250000, -380000.218750, -380000.093750",\ + "-380000.437500, -380000.406250, -380000.343750, -380000.312500, -380000.187500",\ + "-380000.500000, -380000.468750, -380000.406250, -380000.375000, -380000.250000",\ + "-380000.656250, -380000.625000, -380000.562500, -380000.531250, -380000.406250",\ + "-380000.875000, -380000.843750, -380000.781250, -380000.750000, -380000.625000"); + } + + } /* end of arc clk_ast_rng_i_padmux2ast_i[4]_remrr*/ + + timing () { + related_pin : "clk_ast_rng_i" ; + timing_type : removal_rising ; + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-380001.812500, -380001.781250, -380001.718750, -380001.687500, -380001.562500",\ + "-380001.906250, -380001.875000, -380001.812500, -380001.781250, -380001.656250",\ + "-380002.000000, -380001.968750, -380001.906250, -380001.875000, -380001.750000",\ + "-380002.187500, -380002.156250, -380002.093750, -380002.062500, -380001.937500",\ + "-380002.437500, -380002.406250, -380002.343750, -380002.312500, -380002.187500"); + } + + } /* end of arc clk_ast_rng_i_padmux2ast_i[4]_remfr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "380000.843750, 380000.750000, 380000.687500, 380000.687500, 380000.656250",\ + "380000.937500, 380000.843750, 380000.781250, 380000.781250, 380000.750000",\ + "380001.031250, 380000.937500, 380000.875000, 380000.875000, 380000.843750",\ + "380001.187500, 380001.093750, 380001.031250, 380001.031250, 380001.000000",\ + "380001.437500, 380001.343750, 380001.281250, 380001.281250, 380001.250000"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "380002.312500, 380002.218750, 380002.250000, 380002.343750, 380002.750000",\ + "380002.406250, 380002.312500, 380002.343750, 380002.437500, 380002.843750",\ + "380002.531250, 380002.437500, 380002.468750, 380002.562500, 380002.968750",\ + "380002.718750, 380002.625000, 380002.656250, 380002.750000, 380003.156250",\ + "380003.031250, 380002.937500, 380002.968750, 380003.062500, 380003.468750"); + } + + } /* end of arc clk_ast_tlul_i_padmux2ast_i[4]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-380000.312500, -380000.281250, -380000.250000, -380000.218750, -380000.093750",\ + "-380000.406250, -380000.375000, -380000.343750, -380000.312500, -380000.187500",\ + "-380000.468750, -380000.437500, -380000.406250, -380000.375000, -380000.250000",\ + "-380000.625000, -380000.593750, -380000.562500, -380000.531250, -380000.406250",\ + "-380000.843750, -380000.812500, -380000.781250, -380000.750000, -380000.625000"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-380001.781250, -380001.718750, -380001.656250, -380001.593750, -380001.375000",\ + "-380001.875000, -380001.812500, -380001.750000, -380001.687500, -380001.468750",\ + "-380001.968750, -380001.906250, -380001.843750, -380001.781250, -380001.562500",\ + "-380002.156250, -380002.093750, -380002.031250, -380001.968750, -380001.750000",\ + "-380002.406250, -380002.343750, -380002.281250, -380002.218750, -380002.000000"); + } + + } /* end of arc clk_ast_tlul_i_padmux2ast_i[4]_hldr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : recovery_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "380011.406250, 380010.000000, 380009.125000, 380008.718750, 380008.656250",\ + "380011.500000, 380010.093750, 380009.218750, 380008.812500, 380008.750000",\ + "380011.593750, 380010.187500, 380009.312500, 380008.906250, 380008.843750",\ + "380011.750000, 380010.343750, 380009.468750, 380009.062500, 380009.000000",\ + "380012.000000, 380010.593750, 380009.718750, 380009.312500, 380009.250000"); + } + + } /* end of arc clk_ast_tlul_i_padmux2ast_i[4]_recrr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : recovery_rising ; + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "970013.125000, 970011.687500, 970010.875000, 970010.437500, 970010.375000",\ + "970013.250000, 970011.812500, 970011.000000, 970010.562500, 970010.500000",\ + "970013.375000, 970011.937500, 970011.125000, 970010.687500, 970010.625000",\ + "970013.625000, 970012.187500, 970011.375000, 970010.937500, 970010.875000",\ + "970013.875000, 970012.437500, 970011.625000, 970011.187500, 970011.125000"); + } + + } /* end of arc clk_ast_tlul_i_padmux2ast_i[4]_recfr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : removal_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-380000.343750, -380000.312500, -380000.250000, -380000.187500, -379999.843750",\ + "-380000.437500, -380000.406250, -380000.343750, -380000.281250, -379999.937500",\ + "-380000.500000, -380000.468750, -380000.406250, -380000.343750, -380000.000000",\ + "-380000.656250, -380000.625000, -380000.562500, -380000.500000, -380000.156250",\ + "-380000.875000, -380000.843750, -380000.781250, -380000.718750, -380000.375000"); + } + + } /* end of arc clk_ast_tlul_i_padmux2ast_i[4]_remrr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : removal_rising ; + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-380001.812500, -380001.781250, -380001.687500, -380001.625000, -380001.281250",\ + "-380001.906250, -380001.875000, -380001.781250, -380001.718750, -380001.375000",\ + "-380002.000000, -380001.968750, -380001.875000, -380001.812500, -380001.468750",\ + "-380002.187500, -380002.156250, -380002.062500, -380002.000000, -380001.656250",\ + "-380002.437500, -380002.406250, -380002.312500, -380002.250000, -380001.906250"); + } + + } /* end of arc clk_ast_tlul_i_padmux2ast_i[4]_remfr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + clock_gating_flag : true ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "380001.343750, 380001.343750, 380001.343750, 380001.343750, 380001.343750",\ + "380001.437500, 380001.437500, 380001.437500, 380001.437500, 380001.437500",\ + "380001.531250, 380001.531250, 380001.531250, 380001.531250, 380001.531250",\ + "380001.687500, 380001.687500, 380001.687500, 380001.687500, 380001.687500",\ + "380001.937500, 380001.937500, 380001.937500, 380001.937500, 380001.937500"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "380003.062500, 380003.062500, 380003.062500, 380003.062500, 380003.062500",\ + "380003.156250, 380003.156250, 380003.156250, 380003.156250, 380003.156250",\ + "380003.281250, 380003.281250, 380003.281250, 380003.281250, 380003.281250",\ + "380003.468750, 380003.468750, 380003.468750, 380003.468750, 380003.468750",\ + "380003.781250, 380003.781250, 380003.781250, 380003.781250, 380003.781250"); + } + + } /* end of arc clk_ast_tlul_i_padmux2ast_i[4]_cgsr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_falling ; + clock_gating_flag : true ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-380001.343750, -380001.343750, -380001.343750, -380001.343750, -380001.343750",\ + "-380001.437500, -380001.437500, -380001.437500, -380001.437500, -380001.437500",\ + "-380001.500000, -380001.500000, -380001.500000, -380001.500000, -380001.500000",\ + "-380001.656250, -380001.656250, -380001.656250, -380001.656250, -380001.656250",\ + "-380001.875000, -380001.875000, -380001.875000, -380001.875000, -380001.875000"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-380003.062500, -380003.062500, -380003.062500, -380003.062500, -380003.062500",\ + "-380003.156250, -380003.156250, -380003.156250, -380003.156250, -380003.156250",\ + "-380003.250000, -380003.250000, -380003.250000, -380003.250000, -380003.250000",\ + "-380003.437500, -380003.437500, -380003.437500, -380003.437500, -380003.437500",\ + "-380003.687500, -380003.687500, -380003.687500, -380003.687500, -380003.687500"); + } + + } /* end of arc clk_ast_tlul_i_padmux2ast_i[4]_cghf*/ + + timing () { + related_pin : "clk_ast_usb_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "380002.218750, 380002.156250, 380002.125000, 380002.125000, 380002.125000",\ + "380002.312500, 380002.250000, 380002.218750, 380002.218750, 380002.218750",\ + "380002.406250, 380002.343750, 380002.312500, 380002.312500, 380002.312500",\ + "380002.562500, 380002.500000, 380002.468750, 380002.468750, 380002.468750",\ + "380002.812500, 380002.750000, 380002.718750, 380002.718750, 380002.718750"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "380004.218750, 380004.156250, 380004.125000, 380004.125000, 380004.125000",\ + "380004.312500, 380004.250000, 380004.218750, 380004.218750, 380004.218750",\ + "380004.437500, 380004.375000, 380004.343750, 380004.343750, 380004.343750",\ + "380004.625000, 380004.562500, 380004.531250, 380004.531250, 380004.531250",\ + "380004.937500, 380004.875000, 380004.843750, 380004.843750, 380004.843750"); + } + + } /* end of arc clk_ast_usb_i_padmux2ast_i[4]_stupr*/ + + timing () { + related_pin : "clk_ast_usb_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-380001.781250, -380001.718750, -380001.625000, -380001.593750, -380001.375000",\ + "-380001.875000, -380001.812500, -380001.718750, -380001.687500, -380001.468750",\ + "-380001.937500, -380001.875000, -380001.781250, -380001.750000, -380001.531250",\ + "-380002.093750, -380002.031250, -380001.937500, -380001.906250, -380001.687500",\ + "-380002.312500, -380002.250000, -380002.156250, -380002.125000, -380001.906250"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-380003.906250, -380003.843750, -380003.750000, -380003.718750, -380003.500000",\ + "-380004.000000, -380003.937500, -380003.843750, -380003.812500, -380003.593750",\ + "-380004.093750, -380004.031250, -380003.937500, -380003.906250, -380003.687500",\ + "-380004.281250, -380004.218750, -380004.125000, -380004.093750, -380003.875000",\ + "-380004.531250, -380004.468750, -380004.375000, -380004.343750, -380004.125000"); + } + + } /* end of arc clk_ast_usb_i_padmux2ast_i[4]_hldr*/ + + timing () { + related_pin : "clk_ast_usb_i" ; + timing_type : recovery_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "380000.593750, 380000.562500, 380000.500000, 380000.500000, 380000.562500",\ + "380000.687500, 380000.656250, 380000.593750, 380000.593750, 380000.656250",\ + "380000.781250, 380000.750000, 380000.687500, 380000.687500, 380000.750000",\ + "380000.937500, 380000.906250, 380000.843750, 380000.843750, 380000.906250",\ + "380001.187500, 380001.156250, 380001.093750, 380001.093750, 380001.156250"); + } + + } /* end of arc clk_ast_usb_i_padmux2ast_i[4]_recrr*/ + + timing () { + related_pin : "clk_ast_usb_i" ; + timing_type : recovery_rising ; + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "380002.031250, 380002.000000, 380001.937500, 380001.937500, 380002.000000",\ + "380002.125000, 380002.093750, 380002.031250, 380002.031250, 380002.093750",\ + "380002.250000, 380002.218750, 380002.156250, 380002.156250, 380002.218750",\ + "380002.437500, 380002.406250, 380002.343750, 380002.343750, 380002.406250",\ + "380002.750000, 380002.718750, 380002.656250, 380002.656250, 380002.718750"); + } + + } /* end of arc clk_ast_usb_i_padmux2ast_i[4]_recfr*/ + + timing () { + related_pin : "clk_ast_usb_i" ; + timing_type : removal_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-380000.437500, -380000.406250, -380000.343750, -380000.312500, -380000.187500",\ + "-380000.531250, -380000.500000, -380000.437500, -380000.406250, -380000.281250",\ + "-380000.593750, -380000.562500, -380000.500000, -380000.468750, -380000.343750",\ + "-380000.750000, -380000.718750, -380000.656250, -380000.625000, -380000.500000",\ + "-380000.968750, -380000.937500, -380000.875000, -380000.843750, -380000.718750"); + } + + } /* end of arc clk_ast_usb_i_padmux2ast_i[4]_remrr*/ + + timing () { + related_pin : "clk_ast_usb_i" ; + timing_type : removal_rising ; + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-380001.875000, -380001.843750, -380001.781250, -380001.750000, -380001.625000",\ + "-380001.968750, -380001.937500, -380001.875000, -380001.843750, -380001.718750",\ + "-380002.062500, -380002.031250, -380001.968750, -380001.937500, -380001.812500",\ + "-380002.250000, -380002.218750, -380002.156250, -380002.125000, -380002.000000",\ + "-380002.500000, -380002.468750, -380002.406250, -380002.375000, -380002.250000"); + } + + } /* end of arc clk_ast_usb_i_padmux2ast_i[4]_remfr*/ + +} /* end of pin padmux2ast_i[4] */ + +pin("padmux2ast_i[3]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001527 ; + + /* Other user defined attributes. */ + original_pin : padmux2ast_i[3]; +} /* end of pin padmux2ast_i[3] */ + +pin("padmux2ast_i[2]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001451 ; + + /* Other user defined attributes. */ + original_pin : padmux2ast_i[2]; +} /* end of pin padmux2ast_i[2] */ + +pin("padmux2ast_i[1]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.002579 ; + + /* Other user defined attributes. */ + original_pin : padmux2ast_i[1]; +} /* end of pin padmux2ast_i[1] */ + +pin("padmux2ast_i[0]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001032 ; + + /* Other user defined attributes. */ + original_pin : padmux2ast_i[0]; +} /* end of pin padmux2ast_i[0] */ +} /* end of bus padmux2ast_i */ +bus ( ast2padmux_o ) { + + bus_type : BUS9_type16 ; + direction : output ; + +pin("ast2padmux_o[8]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.159377 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : ast2padmux_o[8]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377"); + values ( "380004.343750, 380004.375000, 380004.437500, 380004.718750, 380005.625000",\ + "380004.437500, 380004.468750, 380004.531250, 380004.812500, 380005.718750",\ + "380004.531250, 380004.562500, 380004.625000, 380004.906250, 380005.812500",\ + "380004.593750, 380004.625000, 380004.687500, 380004.968750, 380005.875000",\ + "380004.937500, 380004.968750, 380005.031250, 380005.312500, 380006.218750"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377"); + values ( "0.021241, 0.066861, 0.199049, 0.687205, 2.464075",\ + "0.021241, 0.066861, 0.199049, 0.687205, 2.464075",\ + "0.021241, 0.066861, 0.199049, 0.687205, 2.464075",\ + "0.021241, 0.066861, 0.199049, 0.687205, 2.464075",\ + "0.021241, 0.066861, 0.199049, 0.687205, 2.464075"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377"); + values ( "380002.437500, 380002.468750, 380002.531250, 380002.687500, 380003.281250",\ + "380002.531250, 380002.562500, 380002.625000, 380002.781250, 380003.375000",\ + "380002.593750, 380002.625000, 380002.687500, 380002.843750, 380003.437500",\ + "380002.656250, 380002.687500, 380002.750000, 380002.906250, 380003.500000",\ + "380003.000000, 380003.031250, 380003.093750, 380003.250000, 380003.843750"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377"); + values ( "0.027368, 0.057498, 0.133582, 0.436964, 1.549163",\ + "0.027368, 0.057498, 0.133582, 0.436964, 1.549163",\ + "0.027368, 0.057498, 0.133582, 0.436964, 1.549163",\ + "0.027368, 0.057498, 0.133582, 0.436964, 1.549163",\ + "0.027375, 0.057503, 0.133586, 0.436974, 1.549209"); + } + + } /* end of arc clk_ast_tlul_i_ast2padmux_o[8]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377"); + values ( "0.198420, 0.230953, 0.301455, 0.556384, 1.484645",\ + "0.286701, 0.319234, 0.389735, 0.644664, 1.572926",\ + "0.375268, 0.407801, 0.478303, 0.733232, 1.661493",\ + "0.437972, 0.470506, 0.541007, 0.795935, 1.724196",\ + "0.757115, 0.789659, 0.860255, 1.115081, 2.043332"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377"); + values ( "0.020935, 0.066607, 0.198712, 0.685847, 2.460401",\ + "0.020935, 0.066607, 0.198712, 0.685847, 2.460401",\ + "0.020935, 0.066607, 0.198712, 0.685847, 2.460401",\ + "0.020935, 0.066607, 0.198712, 0.685847, 2.460401",\ + "0.020935, 0.066607, 0.198712, 0.685847, 2.460401"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377"); + values ( "0.211851, 0.238498, 0.286799, 0.453464, 1.060488",\ + "0.299253, 0.325901, 0.374202, 0.540867, 1.147891",\ + "0.380126, 0.406773, 0.455075, 0.621740, 1.228763",\ + "0.437748, 0.464395, 0.512697, 0.679362, 1.286385",\ + "0.739921, 0.766569, 0.814870, 0.981535, 1.588558"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377"); + values ( "0.020406, 0.050335, 0.128964, 0.434734, 1.543997",\ + "0.020406, 0.050335, 0.128964, 0.434734, 1.543997",\ + "0.020406, 0.050335, 0.128964, 0.434734, 1.543997",\ + "0.020406, 0.050335, 0.128964, 0.434734, 1.543997",\ + "0.020406, 0.050336, 0.128964, 0.434733, 1.544003"); + } + + } /* end of arc clk_ast_tlul_i_ast2padmux_o[8]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377"); + values ( "0.408924, 0.441470, 0.512070, 0.766936, 1.695386",\ + "0.493120, 0.525666, 0.596266, 0.851132, 1.779583",\ + "0.583441, 0.615988, 0.686587, 0.941453, 1.869904",\ + "0.653401, 0.685947, 0.756547, 1.011413, 1.939865",\ + "1.044013, 1.076560, 1.147159, 1.402024, 2.330486"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377"); + values ( "0.020948, 0.066625, 0.198722, 0.685958, 2.464075",\ + "0.020948, 0.066625, 0.198722, 0.685958, 2.464075",\ + "0.020948, 0.066625, 0.198722, 0.685958, 2.464075",\ + "0.020948, 0.066625, 0.198723, 0.685958, 2.464075",\ + "0.020946, 0.066625, 0.198725, 0.685957, 2.464076"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377"); + values ( "0.438271, 0.469168, 0.519837, 0.687755, 1.292925",\ + "0.526383, 0.557280, 0.607949, 0.775866, 1.381036",\ + "0.628083, 0.658980, 0.709649, 0.877567, 1.482737",\ + "0.819336, 0.850238, 0.900907, 1.068829, 1.674009",\ + "1.156747, 1.187659, 1.238328, 1.406259, 2.011461"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377"); + values ( "0.027368, 0.057498, 0.133582, 0.436963, 1.549160",\ + "0.027368, 0.057498, 0.133582, 0.436963, 1.549160",\ + "0.027368, 0.057498, 0.133582, 0.436963, 1.549160",\ + "0.027371, 0.057501, 0.133584, 0.436969, 1.549186",\ + "0.027379, 0.057507, 0.133588, 0.436980, 1.549240"); + } + + } /* end of arc clk_ast_tlul_i_ast2padmux_o[8]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377"); + values ( "0.398110, 0.430656, 0.501253, 0.756075, 1.684372",\ + "0.482288, 0.514834, 0.585431, 0.840253, 1.768550",\ + "0.572606, 0.605152, 0.675749, 0.930571, 1.858868",\ + "0.642450, 0.674996, 0.745593, 1.000414, 1.928712",\ + "1.032124, 1.064670, 1.135267, 1.390089, 2.318387"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377"); + values ( "0.020932, 0.066607, 0.198719, 0.685843, 2.463750",\ + "0.020932, 0.066607, 0.198719, 0.685843, 2.463750",\ + "0.020932, 0.066607, 0.198719, 0.685843, 2.463750",\ + "0.020932, 0.066607, 0.198719, 0.685843, 2.463750",\ + "0.020932, 0.066607, 0.198719, 0.685843, 2.463750"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377"); + values ( "0.427883, 0.458770, 0.509441, 0.677352, 1.282498",\ + "0.516006, 0.546892, 0.597564, 0.765475, 1.370620",\ + "0.617659, 0.648546, 0.699217, 0.867128, 1.472274",\ + "0.808079, 0.838969, 0.889641, 1.057554, 1.662708",\ + "1.144522, 1.175420, 1.226092, 1.394011, 1.999181"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377"); + values ( "0.027342, 0.057489, 0.133570, 0.436937, 1.549078",\ + "0.027342, 0.057489, 0.133570, 0.436937, 1.549078",\ + "0.027342, 0.057489, 0.133570, 0.436937, 1.549078",\ + "0.027344, 0.057490, 0.133572, 0.436941, 1.549096",\ + "0.027347, 0.057494, 0.133575, 0.436950, 1.549136"); + } + + } /* end of arc clk_ast_tlul_i_ast2padmux_o[8]_una_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377"); + values ( "380000.718750, 380000.750000, 380000.812500, 380001.093750, 380002.000000",\ + "380000.812500, 380000.843750, 380000.906250, 380001.187500, 380002.093750",\ + "380000.906250, 380000.937500, 380001.000000, 380001.281250, 380002.187500",\ + "380001.062500, 380001.093750, 380001.156250, 380001.437500, 380002.343750",\ + "380001.312500, 380001.343750, 380001.406250, 380001.687500, 380002.593750"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377"); + values ( "0.021241, 0.066861, 0.199049, 0.687205, 2.464075",\ + "0.021241, 0.066861, 0.199049, 0.687205, 2.464075",\ + "0.021241, 0.066861, 0.199049, 0.687205, 2.464075",\ + "0.021241, 0.066861, 0.199049, 0.687205, 2.464075",\ + "0.021241, 0.066861, 0.199049, 0.687205, 2.464075"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377"); + values ( "380002.125000, 380002.156250, 380002.218750, 380002.375000, 380002.968750",\ + "380002.218750, 380002.250000, 380002.312500, 380002.468750, 380003.062500",\ + "380002.343750, 380002.375000, 380002.437500, 380002.593750, 380003.187500",\ + "380002.531250, 380002.562500, 380002.625000, 380002.781250, 380003.375000",\ + "380002.843750, 380002.875000, 380002.937500, 380003.093750, 380003.687500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377"); + values ( "0.027368, 0.057498, 0.133582, 0.436964, 1.549163",\ + "0.027368, 0.057498, 0.133582, 0.436964, 1.549163",\ + "0.027368, 0.057498, 0.133582, 0.436964, 1.549163",\ + "0.027368, 0.057498, 0.133582, 0.436964, 1.549163",\ + "0.027368, 0.057498, 0.133582, 0.436964, 1.549163"); + } + + } /* end of arc padmux2ast_i[4]_ast2padmux_o[8]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377"); + values ( "380000.687500, 380000.718750, 380000.781250, 380001.062500, 380001.968750",\ + "380000.781250, 380000.812500, 380000.875000, 380001.156250, 380002.062500",\ + "380000.843750, 380000.875000, 380000.937500, 380001.218750, 380002.125000",\ + "380001.000000, 380001.031250, 380001.093750, 380001.375000, 380002.281250",\ + "380001.218750, 380001.250000, 380001.312500, 380001.593750, 380002.500000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377"); + values ( "0.020932, 0.066607, 0.198719, 0.685843, 2.460022",\ + "0.020932, 0.066607, 0.198719, 0.685843, 2.460022",\ + "0.020932, 0.066607, 0.198719, 0.685843, 2.460022",\ + "0.020932, 0.066607, 0.198719, 0.685843, 2.460022",\ + "0.020932, 0.066607, 0.198719, 0.685843, 2.460022"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377"); + values ( "380002.125000, 380002.156250, 380002.187500, 380002.375000, 380002.968750",\ + "380002.218750, 380002.250000, 380002.281250, 380002.468750, 380003.062500",\ + "380002.312500, 380002.343750, 380002.375000, 380002.562500, 380003.156250",\ + "380002.500000, 380002.531250, 380002.562500, 380002.750000, 380003.343750",\ + "380002.750000, 380002.781250, 380002.812500, 380003.000000, 380003.593750"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377"); + values ( "0.020492, 0.050440, 0.128935, 0.434235, 1.546080",\ + "0.020492, 0.050440, 0.128935, 0.434235, 1.546080",\ + "0.020492, 0.050440, 0.128935, 0.434235, 1.546080",\ + "0.020492, 0.050440, 0.128935, 0.434235, 1.546080",\ + "0.020492, 0.050440, 0.128935, 0.434235, 1.546080"); + } + + } /* end of arc padmux2ast_i[4]_ast2padmux_o[8]_una_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377"); + values ( "380002.312500, 380002.343750, 380002.406250, 380002.562500, 380003.156250",\ + "380002.406250, 380002.437500, 380002.500000, 380002.656250, 380003.250000",\ + "380002.500000, 380002.531250, 380002.593750, 380002.750000, 380003.343750",\ + "380002.656250, 380002.687500, 380002.750000, 380002.906250, 380003.500000",\ + "380002.906250, 380002.937500, 380003.000000, 380003.156250, 380003.750000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377"); + values ( "0.027368, 0.057498, 0.133582, 0.436964, 1.549163",\ + "0.027368, 0.057498, 0.133582, 0.436964, 1.549163",\ + "0.027368, 0.057498, 0.133582, 0.436964, 1.549163",\ + "0.027368, 0.057498, 0.133582, 0.436964, 1.549163",\ + "0.027368, 0.057498, 0.133582, 0.436964, 1.549163"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377"); + values ( "380004.250000, 380004.281250, 380004.343750, 380004.625000, 380005.531250",\ + "380004.343750, 380004.375000, 380004.437500, 380004.718750, 380005.625000",\ + "380004.468750, 380004.500000, 380004.562500, 380004.843750, 380005.750000",\ + "380004.656250, 380004.687500, 380004.750000, 380005.031250, 380005.937500",\ + "380004.968750, 380005.000000, 380005.062500, 380005.343750, 380006.250000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377"); + values ( "0.021241, 0.066861, 0.199049, 0.687205, 2.464075",\ + "0.021241, 0.066861, 0.199049, 0.687205, 2.464075",\ + "0.021241, 0.066861, 0.199049, 0.687205, 2.464075",\ + "0.021241, 0.066861, 0.199049, 0.687205, 2.464075",\ + "0.021241, 0.066861, 0.199049, 0.687205, 2.464075"); + } + + } /* end of arc padmux2ast_i[4]_ast2padmux_o[8]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377"); + values ( "380000.687500, 380000.718750, 380000.750000, 380000.937500, 380001.531250",\ + "380000.781250, 380000.812500, 380000.843750, 380001.031250, 380001.625000",\ + "380000.843750, 380000.875000, 380000.906250, 380001.093750, 380001.687500",\ + "380001.000000, 380001.031250, 380001.062500, 380001.250000, 380001.843750",\ + "380001.218750, 380001.250000, 380001.281250, 380001.468750, 380002.062500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377"); + values ( "0.020492, 0.050440, 0.128935, 0.434235, 1.546080",\ + "0.020492, 0.050440, 0.128935, 0.434235, 1.546080",\ + "0.020492, 0.050440, 0.128935, 0.434235, 1.546080",\ + "0.020492, 0.050440, 0.128935, 0.434235, 1.546080",\ + "0.020492, 0.050440, 0.128935, 0.434235, 1.546080"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377"); + values ( "380002.062500, 380002.093750, 380002.156250, 380002.437500, 380003.343750",\ + "380002.156250, 380002.187500, 380002.250000, 380002.531250, 380003.437500",\ + "380002.250000, 380002.281250, 380002.343750, 380002.625000, 380003.531250",\ + "380002.437500, 380002.468750, 380002.531250, 380002.812500, 380003.718750",\ + "380002.687500, 380002.718750, 380002.781250, 380003.062500, 380003.968750"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377"); + values ( "0.020932, 0.066607, 0.198719, 0.685843, 2.460022",\ + "0.020932, 0.066607, 0.198719, 0.685843, 2.460022",\ + "0.020932, 0.066607, 0.198719, 0.685843, 2.460022",\ + "0.020932, 0.066607, 0.198719, 0.685843, 2.460022",\ + "0.020932, 0.066607, 0.198719, 0.685843, 2.460022"); + } + + } /* end of arc padmux2ast_i[4]_ast2padmux_o[8]_inv_min*/ + +} /* end of pin ast2padmux_o[8] */ + +pin("ast2padmux_o[7]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.028584 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : ast2padmux_o[7]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380001.875000, 380001.937500, 380002.062500, 380002.375000, 380003.250000",\ + "380001.968750, 380002.031250, 380002.156250, 380002.468750, 380003.343750",\ + "380002.062500, 380002.125000, 380002.250000, 380002.562500, 380003.437500",\ + "380002.125000, 380002.187500, 380002.312500, 380002.625000, 380003.500000",\ + "380002.468750, 380002.531250, 380002.656250, 380002.968750, 380003.843750"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189354, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189354, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189365, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189385, 0.392560, 0.950608, 2.441526",\ + "0.073824, 0.189425, 0.393252, 0.950608, 2.441526"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380000.437500, 380000.437500, 380000.468750, 380000.531250, 380000.718750",\ + "380000.531250, 380000.531250, 380000.562500, 380000.625000, 380000.812500",\ + "380000.593750, 380000.593750, 380000.625000, 380000.687500, 380000.875000",\ + "380000.656250, 380000.656250, 380000.687500, 380000.750000, 380000.937500",\ + "380000.968750, 380000.968750, 380001.000000, 380001.062500, 380001.250000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497"); + } + + } /* end of arc clk_ast_tlul_i_ast2padmux_o[7]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.118063, 0.173160, 0.267375, 0.527316, 1.216798",\ + "0.205470, 0.260567, 0.354781, 0.614720, 1.304204",\ + "0.286205, 0.341346, 0.435579, 0.695608, 1.384949",\ + "0.343571, 0.398793, 0.493060, 0.753254, 1.442331",\ + "0.643636, 0.699058, 0.793671, 1.054205, 1.742813"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.055140, 0.149920, 0.315966, 0.770671, 1.992169",\ + "0.055140, 0.149920, 0.315966, 0.770671, 1.992169",\ + "0.055064, 0.149920, 0.315966, 0.770616, 1.992169",\ + "0.054924, 0.149920, 0.315966, 0.770514, 1.992169",\ + "0.054820, 0.149920, 0.315966, 0.770514, 1.988361"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.068977, 0.083624, 0.108789, 0.177707, 0.362145",\ + "0.157440, 0.172093, 0.197279, 0.266195, 0.450612",\ + "0.246166, 0.261189, 0.286407, 0.355291, 0.539679",\ + "0.308361, 0.324424, 0.349591, 0.418444, 0.602842",\ + "0.630702, 0.654723, 0.683267, 0.752219, 0.936438"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.015416, 0.041075, 0.085652, 0.207740, 0.535967",\ + "0.015763, 0.041089, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967"); + } + + } /* end of arc clk_ast_tlul_i_ast2padmux_o[7]_redg_min*/ + + timing () { + related_pin : "fla_obs_i[7]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.111862, 0.178517, 0.294685, 0.611498, 1.461412",\ + "0.196887, 0.263820, 0.381200, 0.697836, 1.546758",\ + "0.280874, 0.348002, 0.465333, 0.783744, 1.631498",\ + "0.419192, 0.490016, 0.607541, 0.927454, 1.774732",\ + "0.629434, 0.713469, 0.835221, 1.155234, 2.004311"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067759, 0.184639, 0.382501, 0.937507, 2.417566",\ + "0.067759, 0.184639, 0.382501, 0.937507, 2.418347",\ + "0.069174, 0.184639, 0.382586, 0.937507, 2.418347",\ + "0.077831, 0.187460, 0.383300, 0.940319, 2.418347",\ + "0.099054, 0.205738, 0.390315, 0.940320, 2.425200"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.103322, 0.134506, 0.187130, 0.329612, 0.708263",\ + "0.188196, 0.219801, 0.272413, 0.414932, 0.793505",\ + "0.281500, 0.317246, 0.369943, 0.512302, 0.890520",\ + "0.433568, 0.478875, 0.537406, 0.680993, 1.058708",\ + "0.668936, 0.733428, 0.809479, 0.962224, 1.340585"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040521, 0.090274, 0.180244, 0.428614, 1.092440",\ + "0.042863, 0.090977, 0.180401, 0.428614, 1.092696",\ + "0.054661, 0.097371, 0.180899, 0.428690, 1.092793",\ + "0.077190, 0.120374, 0.194930, 0.430280, 1.092793",\ + "0.118581, 0.174509, 0.240947, 0.445113, 1.092793"); + } + + } /* end of arc fla_obs_i[7]_ast2padmux_o[7]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "fla_obs_i[7]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.110629, 0.177262, 0.293339, 0.610165, 1.460154",\ + "0.194795, 0.261696, 0.378936, 0.695592, 1.544629",\ + "0.275980, 0.343081, 0.460479, 0.778514, 1.626463",\ + "0.408884, 0.478137, 0.595421, 0.915532, 1.762573",\ + "0.610985, 0.691263, 0.810230, 1.128954, 1.977655"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067834, 0.183634, 0.382402, 0.934951, 2.414331",\ + "0.067834, 0.183634, 0.382402, 0.934951, 2.414331",\ + "0.068631, 0.183634, 0.382540, 0.936478, 2.414331",\ + "0.075251, 0.185541, 0.383090, 0.939701, 2.414331",\ + "0.093347, 0.198994, 0.384563, 0.939701, 2.425563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.077370, 0.108647, 0.161299, 0.303710, 0.682406",\ + "0.166391, 0.197521, 0.250129, 0.392651, 0.771277",\ + "0.253394, 0.288299, 0.340979, 0.483371, 0.861661",\ + "0.395347, 0.439383, 0.496795, 0.640121, 1.017884",\ + "0.615736, 0.679130, 0.754042, 0.905113, 1.283136"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039363, 0.090228, 0.180124, 0.428312, 1.092155",\ + "0.041196, 0.090228, 0.180315, 0.428312, 1.092511",\ + "0.052267, 0.096073, 0.180798, 0.428601, 1.092511",\ + "0.074482, 0.116813, 0.192279, 0.430033, 1.092511",\ + "0.116096, 0.171326, 0.236992, 0.441817, 1.092511"); + } + + } /* end of arc fla_obs_i[7]_ast2padmux_o[7]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[10]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.495682, 0.527114, 0.579822, 0.722175, 1.100772",\ + "0.520857, 0.552289, 0.604997, 0.747350, 1.125947",\ + "0.590847, 0.622279, 0.674987, 0.817340, 1.195937",\ + "0.713975, 0.745406, 0.798114, 0.940467, 1.319064",\ + "1.300896, 1.332327, 1.385036, 1.527389, 1.905985"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.673247, 0.740150, 0.856588, 1.176256, 2.031462",\ + "0.693898, 0.760801, 0.877239, 1.196908, 2.052114",\ + "0.752520, 0.819423, 0.935861, 1.255530, 2.110735",\ + "0.862063, 0.928966, 1.045403, 1.365072, 2.220278",\ + "1.621675, 1.688580, 1.805019, 2.124689, 2.979892"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073039, 0.188935, 0.391846, 0.949113, 2.441342"); + } + + } /* end of arc obs_ctrl_o[10]_ast2padmux_o[7]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[10]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.342569, 0.373981, 0.426627, 0.569042, 0.947686",\ + "0.366027, 0.397440, 0.450085, 0.592500, 0.971144",\ + "0.437124, 0.468537, 0.521182, 0.663597, 1.042241",\ + "0.562321, 0.593734, 0.646379, 0.788794, 1.167438",\ + "1.165783, 1.197195, 1.249841, 1.392256, 1.770899"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039011, 0.090734, 0.180376, 0.429203, 1.091692",\ + "0.039011, 0.090734, 0.180376, 0.429203, 1.091692",\ + "0.039011, 0.090734, 0.180376, 0.429203, 1.091692",\ + "0.039011, 0.090734, 0.180376, 0.429203, 1.091692",\ + "0.039011, 0.090734, 0.180376, 0.429203, 1.091692"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.657383, 0.724274, 0.840701, 1.160369, 2.015589",\ + "0.673535, 0.740426, 0.856853, 1.176521, 2.031741",\ + "0.736621, 0.803512, 0.919939, 1.239607, 2.094827",\ + "0.845856, 0.912747, 1.029174, 1.348842, 2.204062",\ + "1.602693, 1.669584, 1.786011, 2.105679, 2.960899"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073030, 0.188914, 0.391814, 0.949025, 2.441330",\ + "0.073030, 0.188914, 0.391814, 0.949025, 2.441330",\ + "0.073030, 0.188914, 0.391814, 0.949025, 2.441330",\ + "0.073030, 0.188914, 0.391814, 0.949025, 2.441330",\ + "0.073030, 0.188914, 0.391814, 0.949025, 2.441330"); + } + + } /* end of arc obs_ctrl_o[10]_ast2padmux_o[7]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[11]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.034927, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.180024, 0.211452, 0.264149, 0.406513, 0.785119",\ + "0.193406, 0.224834, 0.277531, 0.419896, 0.798501",\ + "0.275919, 0.307349, 0.360051, 0.502410, 0.881011",\ + "0.400910, 0.432352, 0.485095, 0.627414, 1.005985",\ + "0.975060, 1.010086, 1.063144, 1.205732, 1.584486"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.034927, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039119, 0.090633, 0.180636, 0.429262, 1.090996",\ + "0.039119, 0.090633, 0.180636, 0.429262, 1.090996",\ + "0.039132, 0.090633, 0.180667, 0.429269, 1.090996",\ + "0.039215, 0.090633, 0.180868, 0.429314, 1.090996",\ + "0.049347, 0.094034, 0.180868, 0.429355, 1.091896"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037147, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.465437, 0.532662, 0.649281, 0.969044, 1.824018",\ + "0.477695, 0.544920, 0.661539, 0.981302, 1.836276",\ + "0.541916, 0.609140, 0.725760, 1.045521, 1.900495",\ + "0.644626, 0.711856, 0.828474, 1.148242, 2.003221",\ + "1.319722, 1.387140, 1.503696, 1.823662, 2.678811"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037147, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073817, 0.189281, 0.392442, 0.950607, 2.441526",\ + "0.073817, 0.189281, 0.392442, 0.950607, 2.441526",\ + "0.073817, 0.189282, 0.392442, 0.950607, 2.441526",\ + "0.073862, 0.189282, 0.392442, 0.950619, 2.441526",\ + "0.075399, 0.189282, 0.392442, 0.951039, 2.441526"); + } + + } /* end of arc obs_ctrl_o[11]_ast2padmux_o[7]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[11]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.030664, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.159139, 0.190553, 0.243202, 0.385613, 0.764254",\ + "0.170514, 0.201928, 0.254577, 0.396989, 0.775629",\ + "0.255576, 0.286993, 0.339652, 0.482053, 0.860686",\ + "0.379908, 0.411340, 0.464049, 0.606401, 0.984998",\ + "0.945167, 0.979651, 1.032663, 1.175209, 1.553933"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.030664, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039020, 0.090609, 0.180397, 0.429208, 1.090831",\ + "0.039020, 0.090609, 0.180397, 0.429208, 1.090831",\ + "0.039042, 0.090609, 0.180449, 0.429220, 1.090831",\ + "0.039144, 0.090609, 0.180675, 0.429276, 1.090831",\ + "0.047820, 0.093501, 0.180675, 0.429352, 1.091629"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.028580, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.461683, 0.528880, 0.645509, 0.965243, 1.820192",\ + "0.470327, 0.537524, 0.654153, 0.973887, 1.828836",\ + "0.538174, 0.605371, 0.721999, 1.041733, 1.896681",\ + "0.640782, 0.707985, 0.824611, 1.144351, 1.999304",\ + "1.312551, 1.379913, 1.496487, 1.816396, 2.671496"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.028580, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073594, 0.189124, 0.392388, 0.950544, 2.441454",\ + "0.073594, 0.189124, 0.392388, 0.950544, 2.441454",\ + "0.073594, 0.189124, 0.392388, 0.950544, 2.441454",\ + "0.073633, 0.189124, 0.392388, 0.950557, 2.441454",\ + "0.074954, 0.189124, 0.392388, 0.950917, 2.441454"); + } + + } /* end of arc obs_ctrl_o[11]_ast2padmux_o[7]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.500858, 0.568082, 0.684702, 1.004464, 1.859437",\ + "0.516623, 0.583848, 0.700467, 1.020230, 1.875203",\ + "0.590734, 0.657958, 0.774578, 1.094340, 1.949314",\ + "0.681946, 0.749171, 0.865790, 1.185553, 2.040526",\ + "1.108576, 1.175805, 1.292423, 1.612190, 2.467167"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073816, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073848, 0.189277, 0.392440, 0.950615, 2.441524"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.275118, 0.306284, 0.358903, 0.501398, 0.880041",\ + "0.290749, 0.321915, 0.374533, 0.517029, 0.895671",\ + "0.363703, 0.394869, 0.447488, 0.589983, 0.968626",\ + "0.474794, 0.505959, 0.558577, 0.701073, 1.079716",\ + "1.013269, 1.044421, 1.097036, 1.239541, 1.618177"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040759, 0.090626, 0.180653, 0.429266, 1.092499",\ + "0.040922, 0.090525, 0.180916, 0.429325, 1.092539"); + } + + } /* end of arc obs_ctrl_o[4]_ast2padmux_o[7]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.337608, 0.404302, 0.520641, 0.837429, 1.687203",\ + "0.349939, 0.416633, 0.532972, 0.849760, 1.699534",\ + "0.408752, 0.475446, 0.591785, 0.908573, 1.758347",\ + "0.496083, 0.562777, 0.679117, 0.995905, 1.845678",\ + "0.949078, 1.015776, 1.132136, 1.448920, 2.298678"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184560, 0.382485, 0.937098, 2.417677",\ + "0.067604, 0.184551, 0.382483, 0.937052, 2.417689"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.209985, 0.241400, 0.294052, 0.436461, 0.815099",\ + "0.221857, 0.253271, 0.305923, 0.448332, 0.826970",\ + "0.304351, 0.335766, 0.388417, 0.530826, 0.909465",\ + "0.409226, 0.440642, 0.493298, 0.635702, 1.014338",\ + "0.909442, 0.940877, 0.993596, 1.135938, 1.514527"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039034, 0.090327, 0.180161, 0.428971, 1.091542",\ + "0.039166, 0.090324, 0.180166, 0.428948, 1.090692"); + } + + } /* end of arc obs_ctrl_o[4]_ast2padmux_o[7]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.287803, 0.318969, 0.371587, 0.514083, 0.892726",\ + "0.303569, 0.334734, 0.387353, 0.529848, 0.908491",\ + "0.378810, 0.409975, 0.462594, 0.605089, 0.983732",\ + "0.473884, 0.505049, 0.557668, 0.700163, 1.078806",\ + "0.918190, 0.949342, 1.001956, 1.144462, 1.523098"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040759, 0.090626, 0.180653, 0.429266, 1.092499",\ + "0.040922, 0.090525, 0.180916, 0.429325, 1.092539"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.376755, 0.443500, 0.560063, 0.876818, 1.726409",\ + "0.392417, 0.459162, 0.575725, 0.892480, 1.742071",\ + "0.467424, 0.534169, 0.650732, 0.967487, 1.817078",\ + "0.562603, 0.629351, 0.745928, 1.062681, 1.912261",\ + "1.006927, 1.073706, 1.190415, 1.507149, 2.356620"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073816, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073848, 0.189277, 0.392440, 0.950615, 2.441524"); + } + + } /* end of arc obs_ctrl_o[4]_ast2padmux_o[7]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.264318, 0.295567, 0.348210, 0.490643, 0.869326",\ + "0.278489, 0.309737, 0.362381, 0.504814, 0.883496",\ + "0.355325, 0.386573, 0.439217, 0.581649, 0.960332",\ + "0.450369, 0.481617, 0.534260, 0.676693, 1.055376",\ + "0.893831, 0.925076, 0.977718, 1.120154, 1.498834"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039034, 0.090327, 0.180161, 0.428971, 1.091542",\ + "0.039166, 0.090324, 0.180166, 0.428948, 1.090692"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.373701, 0.440395, 0.556734, 0.873522, 1.723296",\ + "0.385572, 0.452266, 0.568605, 0.885393, 1.735167",\ + "0.464371, 0.531065, 0.647404, 0.964192, 1.813966",\ + "0.559385, 0.626079, 0.742420, 1.059207, 1.908981",\ + "1.002245, 1.068944, 1.185303, 1.502088, 2.351846"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184560, 0.382485, 0.937098, 2.417677",\ + "0.067604, 0.184551, 0.382483, 0.937052, 2.417689"); + } + + } /* end of arc obs_ctrl_o[4]_ast2padmux_o[7]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.337998, 0.404744, 0.521308, 0.838063, 1.687653",\ + "0.353177, 0.419923, 0.536487, 0.853242, 1.702832",\ + "0.412195, 0.478941, 0.595505, 0.912260, 1.761850",\ + "0.508449, 0.575199, 0.691783, 1.008535, 1.858109",\ + "0.997007, 1.063817, 1.180658, 1.497372, 2.346736"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\ + "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073887, 0.189271, 0.392439, 0.950626, 2.441522",\ + "0.075818, 0.189005, 0.392348, 0.951153, 2.441399"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.272032, 0.303198, 0.355817, 0.498312, 0.876955",\ + "0.289891, 0.321056, 0.373675, 0.516170, 0.894813",\ + "0.360955, 0.392121, 0.444739, 0.587235, 0.965878",\ + "0.471378, 0.502542, 0.555160, 0.697656, 1.076298",\ + "1.004117, 1.035227, 1.087829, 1.230366, 1.608983"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\ + "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\ + "0.040752, 0.090633, 0.180666, 0.429269, 1.092497",\ + "0.040771, 0.090633, 0.180871, 0.429315, 1.092502",\ + "0.049622, 0.094130, 0.180871, 0.429356, 1.092666"); + } + + } /* end of arc obs_ctrl_o[5]_ast2padmux_o[7]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.329221, 0.395915, 0.512254, 0.829041, 1.678816",\ + "0.344592, 0.411286, 0.527624, 0.844412, 1.694187",\ + "0.406780, 0.473474, 0.589813, 0.906601, 1.756375",\ + "0.502234, 0.568932, 0.685288, 1.002073, 1.851833",\ + "0.957622, 1.024367, 1.140929, 1.457685, 2.307276"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067607, 0.184553, 0.382483, 0.937060, 2.417687",\ + "0.067439, 0.184458, 0.382464, 0.936568, 2.417820"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.231492, 0.262740, 0.315383, 0.457816, 0.836499",\ + "0.245351, 0.276600, 0.329243, 0.471676, 0.850359",\ + "0.320124, 0.351372, 0.404016, 0.546449, 0.925131",\ + "0.430166, 0.461410, 0.514053, 0.656489, 1.035169",\ + "0.955028, 0.986237, 1.038869, 1.181331, 1.559995"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039041, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039146, 0.090294, 0.180167, 0.428752, 1.090822",\ + "0.040211, 0.090294, 0.180212, 0.428752, 1.091676"); + } + + } /* end of arc obs_ctrl_o[5]_ast2padmux_o[7]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[5]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.176901, 0.208329, 0.261026, 0.403390, 0.781996",\ + "0.196158, 0.227585, 0.280282, 0.422647, 0.801252",\ + "0.273304, 0.304734, 0.357436, 0.499795, 0.878396",\ + "0.397207, 0.428649, 0.481392, 0.623711, 1.002282",\ + "0.961790, 0.996912, 1.049978, 1.192575, 1.571334"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\ + "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\ + "0.040752, 0.090633, 0.180666, 0.429269, 1.092497",\ + "0.040771, 0.090633, 0.180871, 0.429315, 1.092502",\ + "0.049622, 0.094130, 0.180871, 0.429356, 1.092666"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.455825, 0.523049, 0.639668, 0.959430, 1.814404",\ + "0.468963, 0.536187, 0.652807, 0.972569, 1.827542",\ + "0.531289, 0.598514, 0.715133, 1.034896, 1.889869",\ + "0.640154, 0.707387, 0.824004, 1.143775, 1.998757",\ + "1.332501, 1.399969, 1.516508, 1.836528, 2.691724"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\ + "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073887, 0.189271, 0.392439, 0.950626, 2.441522",\ + "0.075818, 0.189005, 0.392348, 0.951153, 2.441399"); + } + + } /* end of arc obs_ctrl_o[5]_ast2padmux_o[7]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[5]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.155833, 0.187247, 0.239896, 0.382308, 0.760949",\ + "0.173482, 0.204896, 0.257545, 0.399957, 0.778598",\ + "0.252964, 0.284381, 0.337040, 0.479441, 0.858074",\ + "0.376196, 0.407628, 0.460337, 0.602689, 0.981285",\ + "0.931678, 0.966257, 1.019278, 1.161831, 1.540560"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039041, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039146, 0.090294, 0.180167, 0.428752, 1.090822",\ + "0.040211, 0.090294, 0.180212, 0.428752, 1.091676"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.452081, 0.519278, 0.635907, 0.955640, 1.810589",\ + "0.461862, 0.529059, 0.645688, 0.965421, 1.820370",\ + "0.527542, 0.594739, 0.711368, 1.031102, 1.886050",\ + "0.636262, 0.703467, 0.820093, 1.139835, 1.994791",\ + "1.324350, 1.391756, 1.508316, 1.828270, 2.683409"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067607, 0.184553, 0.382483, 0.937060, 2.417687",\ + "0.067439, 0.184458, 0.382464, 0.936568, 2.417820"); + } + + } /* end of arc obs_ctrl_o[5]_ast2padmux_o[7]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[6]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.325984, 0.393209, 0.509828, 0.829592, 1.684567",\ + "0.341732, 0.408957, 0.525576, 0.845340, 1.700314",\ + "0.405621, 0.472847, 0.589466, 0.909229, 1.764204",\ + "0.483984, 0.551208, 0.667827, 0.987590, 1.842564",\ + "0.876566, 0.943791, 1.060410, 1.380173, 2.235147"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189281, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189281, 0.392442, 0.950608, 2.441526"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.207560, 0.238992, 0.291700, 0.434053, 0.812650",\ + "0.223441, 0.254873, 0.307582, 0.449934, 0.828531",\ + "0.292964, 0.324396, 0.377105, 0.519457, 0.898054",\ + "0.382304, 0.413736, 0.466444, 0.608797, 0.987394",\ + "0.808201, 0.839636, 0.892354, 1.034697, 1.413287"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\ + "0.040785, 0.090610, 0.180744, 0.429286, 1.092505"); + } + + } /* end of arc obs_ctrl_o[6]_ast2padmux_o[7]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[6]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.298728, 0.365697, 0.482189, 0.801862, 1.656989",\ + "0.312838, 0.379807, 0.496299, 0.815972, 1.671100",\ + "0.378416, 0.445385, 0.561877, 0.881551, 1.736677",\ + "0.456978, 0.523948, 0.640441, 0.960115, 1.815240",\ + "0.852482, 0.919491, 1.036016, 1.355692, 2.210772"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067586, 0.184541, 0.382481, 0.936998, 2.417704"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.185526, 0.216941, 0.269593, 0.412001, 0.790640",\ + "0.197528, 0.228943, 0.281595, 0.424004, 0.802642",\ + "0.270950, 0.302365, 0.355017, 0.497425, 0.876064",\ + "0.360375, 0.391790, 0.444442, 0.586850, 0.965489",\ + "0.786063, 0.817479, 0.870138, 1.012540, 1.391174"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039039, 0.090322, 0.180169, 0.428938, 1.091513"); + } + + } /* end of arc obs_ctrl_o[6]_ast2padmux_o[7]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[6]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.314064, 0.345229, 0.397848, 0.540343, 0.918986",\ + "0.329859, 0.361025, 0.413644, 0.556139, 0.934782",\ + "0.407724, 0.438890, 0.491508, 0.634004, 1.012646",\ + "0.508778, 0.539944, 0.592562, 0.735058, 1.113701",\ + "0.984655, 1.015818, 1.068436, 1.210933, 1.589574"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\ + "0.040785, 0.090610, 0.180744, 0.429286, 1.092505"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.596327, 0.663552, 0.780171, 1.099935, 1.954909",\ + "0.609131, 0.676356, 0.792975, 1.112739, 1.967713",\ + "0.677113, 0.744339, 0.860958, 1.180721, 2.035696",\ + "0.788810, 0.856034, 0.972654, 1.292416, 2.147390",\ + "1.273667, 1.340892, 1.457511, 1.777274, 2.632248"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189281, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189281, 0.392442, 0.950608, 2.441526"); + } + + } /* end of arc obs_ctrl_o[6]_ast2padmux_o[7]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[6]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.262848, 0.294262, 0.346915, 0.489323, 0.867962",\ + "0.276998, 0.308413, 0.361065, 0.503474, 0.882112",\ + "0.356726, 0.388141, 0.440793, 0.583202, 0.961840",\ + "0.457948, 0.489362, 0.542015, 0.684423, 1.063061",\ + "0.929777, 0.961193, 1.013852, 1.156254, 1.534888"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039039, 0.090322, 0.180169, 0.428938, 1.091513"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.437011, 0.503705, 0.620045, 0.936832, 1.786606",\ + "0.446608, 0.513302, 0.629642, 0.946429, 1.796203",\ + "0.517780, 0.584475, 0.700814, 1.017602, 1.867376",\ + "0.629396, 0.696091, 0.812430, 1.129218, 1.978992",\ + "1.131911, 1.198614, 1.314996, 1.631778, 2.481517"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067586, 0.184541, 0.382481, 0.936998, 2.417704"); + } + + } /* end of arc obs_ctrl_o[6]_ast2padmux_o[7]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[7]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.060518, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.315427, 0.346593, 0.399212, 0.541707, 0.920350",\ + "0.342146, 0.373312, 0.425930, 0.568426, 0.947068",\ + "0.410184, 0.441350, 0.493968, 0.636464, 1.015106",\ + "0.512927, 0.544093, 0.596711, 0.739207, 1.117850",\ + "0.999580, 1.030743, 1.083361, 1.225858, 1.604500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.060518, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180697, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180697, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180697, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180732, 0.429283, 1.092497",\ + "0.042004, 0.091469, 0.180867, 0.429340, 1.092504"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.051005, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.597332, 0.664558, 0.781177, 1.100940, 1.955915",\ + "0.618079, 0.685305, 0.801924, 1.121688, 1.976662",\ + "0.683404, 0.750630, 0.867249, 1.187012, 2.041987",\ + "0.797603, 0.864828, 0.981447, 1.301210, 2.156184",\ + "1.375793, 1.443018, 1.559637, 1.879400, 2.734374"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.051005, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189280, 0.392442, 0.950609, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073823, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073819, 0.189281, 0.392442, 0.950607, 2.441526",\ + "0.073817, 0.189281, 0.392442, 0.950607, 2.441526"); + } + + } /* end of arc obs_ctrl_o[7]_ast2padmux_o[7]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[7]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.049671, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.150722, 0.182137, 0.234789, 0.377197, 0.755836",\ + "0.171205, 0.202620, 0.255272, 0.397681, 0.776319",\ + "0.246518, 0.277932, 0.330585, 0.472993, 0.851631",\ + "0.352324, 0.383738, 0.436391, 0.578799, 0.957437",\ + "0.825559, 0.856975, 0.909634, 1.052036, 1.430670"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.049671, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039038, 0.090323, 0.180168, 0.428941, 1.091519"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040467, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.277343, 0.344312, 0.460804, 0.780477, 1.635605",\ + "0.293355, 0.360323, 0.476815, 0.796489, 1.651616",\ + "0.366113, 0.433085, 0.549579, 0.869253, 1.724376",\ + "0.487008, 0.554003, 0.670516, 0.990192, 1.845287",\ + "1.141953, 1.209132, 1.325766, 1.645481, 2.500414"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040467, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067601, 0.184550, 0.382483, 0.937044, 2.417691"); + } + + } /* end of arc obs_ctrl_o[7]_ast2padmux_o[7]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[8]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.690094, 0.756997, 0.873435, 1.193104, 2.048309",\ + "0.708444, 0.775347, 0.891784, 1.211453, 2.066659",\ + "0.778290, 0.845193, 0.961630, 1.281299, 2.136505",\ + "0.871001, 0.937904, 1.054342, 1.374010, 2.229216",\ + "1.316481, 1.383384, 1.499822, 1.819491, 2.674696"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.452197, 0.483629, 0.536337, 0.678690, 1.057287",\ + "0.469625, 0.501056, 0.553764, 0.696117, 1.074714",\ + "0.546991, 0.578423, 0.631131, 0.773484, 1.152081",\ + "0.655363, 0.686795, 0.739503, 0.881856, 1.260453",\ + "1.172095, 1.203526, 1.256235, 1.398588, 1.777184"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837"); + } + + } /* end of arc obs_ctrl_o[8]_ast2padmux_o[7]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[8]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.682055, 0.748946, 0.865373, 1.185041, 2.040261",\ + "0.698671, 0.765561, 0.881989, 1.201657, 2.056877",\ + "0.770251, 0.837141, 0.953569, 1.273237, 2.128457",\ + "0.862962, 0.929853, 1.046280, 1.365948, 2.221168",\ + "1.308443, 1.375334, 1.491761, 1.811429, 2.666649"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073030, 0.188914, 0.391814, 0.949025, 2.441330",\ + "0.073030, 0.188914, 0.391814, 0.949025, 2.441330",\ + "0.073030, 0.188914, 0.391814, 0.949025, 2.441330",\ + "0.073030, 0.188914, 0.391814, 0.949025, 2.441330",\ + "0.073030, 0.188914, 0.391814, 0.949025, 2.441330"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.393282, 0.424695, 0.477340, 0.619755, 0.998399",\ + "0.406628, 0.438041, 0.490686, 0.633102, 1.011745",\ + "0.488076, 0.519489, 0.572134, 0.714549, 1.093193",\ + "0.596558, 0.627970, 0.680616, 0.823031, 1.201674",\ + "1.114468, 1.145880, 1.198526, 1.340941, 1.719585"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039011, 0.090734, 0.180376, 0.429203, 1.091692",\ + "0.039011, 0.090734, 0.180376, 0.429203, 1.091692",\ + "0.039011, 0.090734, 0.180376, 0.429203, 1.091692",\ + "0.039011, 0.090734, 0.180376, 0.429203, 1.091692",\ + "0.039011, 0.090734, 0.180376, 0.429203, 1.091692"); + } + + } /* end of arc obs_ctrl_o[8]_ast2padmux_o[7]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[8]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.501059, 0.532491, 0.585199, 0.727552, 1.106149",\ + "0.519617, 0.551049, 0.603757, 0.746110, 1.124707",\ + "0.596986, 0.628417, 0.681126, 0.823478, 1.202075",\ + "0.726207, 0.757638, 0.810347, 0.952700, 1.331296",\ + "1.349983, 1.381414, 1.434123, 1.576475, 1.955072"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.672551, 0.739454, 0.855892, 1.175561, 2.030766",\ + "0.690451, 0.757354, 0.873791, 1.193460, 2.048666",\ + "0.751450, 0.818353, 0.934791, 1.254459, 2.109665",\ + "0.853899, 0.920802, 1.037239, 1.356908, 2.212114",\ + "1.570440, 1.637343, 1.753780, 2.073449, 2.928655"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340"); + } + + } /* end of arc obs_ctrl_o[8]_ast2padmux_o[7]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[8]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.403368, 0.434780, 0.487426, 0.629841, 1.008485",\ + "0.420114, 0.451526, 0.504172, 0.646587, 1.025230",\ + "0.499560, 0.530972, 0.583618, 0.726033, 1.104676",\ + "0.629829, 0.661242, 0.713887, 0.856302, 1.234946",\ + "1.257639, 1.289051, 1.341697, 1.484112, 1.862756"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039011, 0.090734, 0.180376, 0.429203, 1.091692",\ + "0.039011, 0.090734, 0.180376, 0.429203, 1.091692",\ + "0.039011, 0.090734, 0.180376, 0.429203, 1.091692",\ + "0.039011, 0.090734, 0.180376, 0.429203, 1.091692",\ + "0.039011, 0.090734, 0.180376, 0.429203, 1.091692"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.659894, 0.726785, 0.843212, 1.162880, 2.018100",\ + "0.674063, 0.740954, 0.857382, 1.177050, 2.032269",\ + "0.738792, 0.805683, 0.922111, 1.241779, 2.096998",\ + "0.841228, 0.908118, 1.024546, 1.344214, 2.199434",\ + "1.556835, 1.623726, 1.740153, 2.059821, 2.915041"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073030, 0.188914, 0.391814, 0.949025, 2.441330",\ + "0.073030, 0.188914, 0.391814, 0.949025, 2.441330",\ + "0.073030, 0.188914, 0.391814, 0.949025, 2.441330",\ + "0.073030, 0.188914, 0.391814, 0.949025, 2.441330",\ + "0.073030, 0.188914, 0.391814, 0.949025, 2.441330"); + } + + } /* end of arc obs_ctrl_o[8]_ast2padmux_o[7]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[9]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.701899, 0.768802, 0.885240, 1.204909, 2.060114",\ + "0.720452, 0.787355, 0.903793, 1.223462, 2.078667",\ + "0.793150, 0.860053, 0.976490, 1.296159, 2.151365",\ + "0.888367, 0.955270, 1.071708, 1.391377, 2.246583",\ + "1.341174, 1.408077, 1.524515, 1.844184, 2.699389"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.458590, 0.490021, 0.542729, 0.685082, 1.063679",\ + "0.476132, 0.507563, 0.560272, 0.702625, 1.081221",\ + "0.553461, 0.584892, 0.637601, 0.779954, 1.158551",\ + "0.662931, 0.694363, 0.747071, 0.889424, 1.268021",\ + "1.187512, 1.218943, 1.271652, 1.414004, 1.792601"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837"); + } + + } /* end of arc obs_ctrl_o[9]_ast2padmux_o[7]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[9]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.693852, 0.760742, 0.877170, 1.196838, 2.052058",\ + "0.710673, 0.777564, 0.893991, 1.213659, 2.068879",\ + "0.785102, 0.851993, 0.968420, 1.288088, 2.143308",\ + "0.880320, 0.947210, 1.063638, 1.383306, 2.238526",\ + "1.333127, 1.400018, 1.516445, 1.836113, 2.691333"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073030, 0.188914, 0.391814, 0.949025, 2.441330",\ + "0.073030, 0.188914, 0.391814, 0.949025, 2.441330",\ + "0.073030, 0.188914, 0.391814, 0.949025, 2.441330",\ + "0.073030, 0.188914, 0.391814, 0.949025, 2.441330",\ + "0.073030, 0.188914, 0.391814, 0.949025, 2.441330"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.399735, 0.431148, 0.483793, 0.626208, 1.004852",\ + "0.413192, 0.444604, 0.497250, 0.639665, 1.018308",\ + "0.494607, 0.526019, 0.578665, 0.721080, 1.099723",\ + "0.604175, 0.635587, 0.688233, 0.830648, 1.209292",\ + "1.129895, 1.161308, 1.213953, 1.356368, 1.735012"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039011, 0.090734, 0.180376, 0.429203, 1.091692",\ + "0.039011, 0.090734, 0.180376, 0.429203, 1.091692",\ + "0.039011, 0.090734, 0.180376, 0.429203, 1.091692",\ + "0.039011, 0.090734, 0.180376, 0.429203, 1.091692",\ + "0.039011, 0.090734, 0.180376, 0.429203, 1.091692"); + } + + } /* end of arc obs_ctrl_o[9]_ast2padmux_o[7]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[9]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.496000, 0.527432, 0.580140, 0.722493, 1.101090",\ + "0.514620, 0.546052, 0.598760, 0.741113, 1.119710",\ + "0.591411, 0.622842, 0.675550, 0.817903, 1.196500",\ + "0.717296, 0.748727, 0.801436, 0.943789, 1.322386",\ + "1.315738, 1.347169, 1.399878, 1.542231, 1.920827"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.666141, 0.733044, 0.849482, 1.169151, 2.024356",\ + "0.678814, 0.745717, 0.862155, 1.181824, 2.037030",\ + "0.733584, 0.800487, 0.916924, 1.236593, 2.091799",\ + "0.837061, 0.903964, 1.020401, 1.340070, 2.195276",\ + "1.538248, 1.605151, 1.721588, 2.041257, 2.896463"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340"); + } + + } /* end of arc obs_ctrl_o[9]_ast2padmux_o[7]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[9]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.398263, 0.429676, 0.482321, 0.624736, 1.003380",\ + "0.415077, 0.446490, 0.499135, 0.641550, 1.020194",\ + "0.493940, 0.525353, 0.577998, 0.720414, 1.099057",\ + "0.620916, 0.652328, 0.704974, 0.847389, 1.226032",\ + "1.223414, 1.254826, 1.307472, 1.449887, 1.828531"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039011, 0.090734, 0.180376, 0.429203, 1.091692",\ + "0.039011, 0.090734, 0.180376, 0.429203, 1.091692",\ + "0.039011, 0.090734, 0.180376, 0.429203, 1.091692",\ + "0.039011, 0.090734, 0.180376, 0.429203, 1.091692",\ + "0.039011, 0.090734, 0.180376, 0.429203, 1.091692"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.653476, 0.720367, 0.836794, 1.156462, 2.011682",\ + "0.663102, 0.729992, 0.846420, 1.166088, 2.021308",\ + "0.720914, 0.787805, 0.904232, 1.223900, 2.079120",\ + "0.824356, 0.891247, 1.007674, 1.327342, 2.182562",\ + "1.523659, 1.590550, 1.706977, 2.026645, 2.881865"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073030, 0.188914, 0.391814, 0.949025, 2.441330",\ + "0.073030, 0.188914, 0.391814, 0.949025, 2.441330",\ + "0.073030, 0.188914, 0.391814, 0.949025, 2.441330",\ + "0.073030, 0.188914, 0.391814, 0.949025, 2.441330",\ + "0.073030, 0.188914, 0.391814, 0.949025, 2.441330"); + } + + } /* end of arc obs_ctrl_o[9]_ast2padmux_o[7]_inv_min*/ + + timing () { + related_pin : "otm_obs_i[7]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.123879, 0.190820, 0.307288, 0.626960, 1.482121",\ + "0.210891, 0.277978, 0.394567, 0.714249, 1.569235",\ + "0.301781, 0.369068, 0.485667, 0.805496, 1.660526",\ + "0.453978, 0.523120, 0.640034, 0.960158, 1.815427",\ + "0.695902, 0.774527, 0.893732, 1.214148, 2.069560"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073065, 0.188997, 0.391936, 0.949305, 2.441374",\ + "0.073175, 0.189249, 0.392304, 0.950092, 2.441498",\ + "0.074330, 0.189249, 0.392418, 0.950747, 2.441498",\ + "0.079436, 0.191164, 0.392505, 0.951076, 2.441498",\ + "0.098084, 0.204137, 0.393542, 0.951076, 2.441498"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.114293, 0.145721, 0.198417, 0.340782, 0.719388",\ + "0.205394, 0.236828, 0.289545, 0.431889, 0.810480",\ + "0.309904, 0.342065, 0.394885, 0.537244, 0.915841",\ + "0.501618, 0.536979, 0.590065, 0.732680, 1.111452",\ + "0.825607, 0.870622, 0.930343, 1.075147, 1.454209"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039117, 0.090634, 0.180632, 0.429261, 1.091005",\ + "0.039161, 0.090634, 0.180739, 0.429285, 1.091005",\ + "0.041267, 0.091212, 0.180891, 0.429338, 1.091005",\ + "0.050293, 0.094364, 0.180891, 0.429357, 1.092061",\ + "0.068556, 0.114740, 0.192215, 0.429716, 1.093122"); + } + + } /* end of arc otm_obs_i[7]_ast2padmux_o[7]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "otm_obs_i[7]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.120559, 0.187489, 0.303948, 0.623619, 1.478793",\ + "0.205712, 0.272774, 0.389342, 0.709022, 1.564038",\ + "0.292652, 0.359907, 0.476516, 0.796311, 1.651312",\ + "0.437434, 0.505450, 0.622092, 0.942182, 1.797434",\ + "0.662107, 0.738115, 0.856688, 1.177023, 2.032395"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073057, 0.188977, 0.391908, 0.949245, 2.441364",\ + "0.073156, 0.189206, 0.392241, 0.949956, 2.441378",\ + "0.074065, 0.189247, 0.392382, 0.950255, 2.441378",\ + "0.077223, 0.189624, 0.392382, 0.950255, 2.441378",\ + "0.092938, 0.200557, 0.393255, 0.950255, 2.441468"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.094368, 0.125782, 0.178430, 0.320842, 0.699483",\ + "0.188259, 0.219683, 0.272369, 0.414744, 0.793358",\ + "0.291365, 0.323244, 0.376040, 0.518376, 0.896959",\ + "0.474009, 0.509208, 0.562280, 0.704883, 1.083646",\ + "0.777508, 0.822171, 0.881623, 1.026340, 1.405392"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039018, 0.090654, 0.180392, 0.429207, 1.090346",\ + "0.039096, 0.090654, 0.180581, 0.429249, 1.090346",\ + "0.040472, 0.090934, 0.180608, 0.429337, 1.090346",\ + "0.049836, 0.094205, 0.180608, 0.429356, 1.091981",\ + "0.067933, 0.113945, 0.191732, 0.429701, 1.093101"); + } + + } /* end of arc otm_obs_i[7]_ast2padmux_o[7]_una_min*/ + + timing () { + related_pin : "otp_obs_i[7]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.122660, 0.189370, 0.305783, 0.622560, 1.472274",\ + "0.209824, 0.276743, 0.394059, 0.710704, 1.559679",\ + "0.301920, 0.369023, 0.486415, 0.804486, 1.652417",\ + "0.455547, 0.524976, 0.642287, 0.962376, 1.809444",\ + "0.699992, 0.780922, 0.900058, 1.218756, 2.067549"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067561, 0.184527, 0.382478, 0.936925, 2.417724",\ + "0.067561, 0.184527, 0.382478, 0.936925, 2.418306",\ + "0.068683, 0.184527, 0.382544, 0.936925, 2.418306",\ + "0.075540, 0.185756, 0.383113, 0.940410, 2.418306",\ + "0.094401, 0.199857, 0.384817, 0.940410, 2.426093"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.114764, 0.145947, 0.198571, 0.341053, 0.719705",\ + "0.205629, 0.236785, 0.289401, 0.431904, 0.810542",\ + "0.310076, 0.342571, 0.395201, 0.537686, 0.916183",\ + "0.500896, 0.538360, 0.591093, 0.733386, 1.111456",\ + "0.820213, 0.870292, 0.933027, 1.077593, 1.455130"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040532, 0.090273, 0.180246, 0.428609, 1.092443",\ + "0.040870, 0.090273, 0.180281, 0.428609, 1.092443",\ + "0.045400, 0.092351, 0.180508, 0.428609, 1.092443",\ + "0.059558, 0.100025, 0.181106, 0.428872, 1.092443",\ + "0.087354, 0.133744, 0.204884, 0.431205, 1.092443"); + } + + } /* end of arc otp_obs_i[7]_ast2padmux_o[7]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "otp_obs_i[7]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.119334, 0.186028, 0.302368, 0.619155, 1.468929",\ + "0.204833, 0.271716, 0.388876, 0.705544, 1.554647",\ + "0.293319, 0.360401, 0.477846, 0.795625, 1.643707",\ + "0.440314, 0.508488, 0.625608, 0.945855, 1.792734",\ + "0.667813, 0.745674, 0.864272, 1.183300, 2.031636"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.183691, 0.382409, 0.935142, 2.413233",\ + "0.067620, 0.183691, 0.382409, 0.935142, 2.413233",\ + "0.068262, 0.183691, 0.382508, 0.936031, 2.413233",\ + "0.073482, 0.184226, 0.382946, 0.939859, 2.413233",\ + "0.089380, 0.196045, 0.384240, 0.939859, 2.423100"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.094521, 0.125776, 0.178422, 0.320849, 0.699535",\ + "0.188239, 0.219444, 0.272075, 0.414540, 0.793202",\ + "0.291550, 0.323577, 0.376197, 0.518700, 0.897237",\ + "0.473699, 0.510899, 0.563627, 0.705929, 1.084022",\ + "0.773733, 0.823401, 0.885774, 1.030256, 1.407808"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039633, 0.090291, 0.180152, 0.428296, 1.092222",\ + "0.040262, 0.090291, 0.180217, 0.428296, 1.092377",\ + "0.044064, 0.091627, 0.180452, 0.428296, 1.092425",\ + "0.058805, 0.099616, 0.181075, 0.428844, 1.092425",\ + "0.086478, 0.132591, 0.204027, 0.431125, 1.092425"); + } + + } /* end of arc otp_obs_i[7]_ast2padmux_o[7]_una_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380000.312500, 380000.312500, 380000.343750, 380000.406250, 380000.593750",\ + "380000.406250, 380000.406250, 380000.437500, 380000.500000, 380000.687500",\ + "380000.500000, 380000.500000, 380000.531250, 380000.593750, 380000.781250",\ + "380000.656250, 380000.656250, 380000.687500, 380000.750000, 380000.937500",\ + "380000.906250, 380000.906250, 380000.937500, 380001.000000, 380001.187500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380001.781250, 380001.843750, 380001.968750, 380002.281250, 380003.156250",\ + "380001.875000, 380001.937500, 380002.062500, 380002.375000, 380003.250000",\ + "380002.000000, 380002.062500, 380002.187500, 380002.500000, 380003.375000",\ + "380002.187500, 380002.250000, 380002.375000, 380002.687500, 380003.562500",\ + "380002.500000, 380002.562500, 380002.687500, 380003.000000, 380003.875000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526"); + } + + } /* end of arc padmux2ast_i[4]_ast2padmux_o[7]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380000.312500, 380000.312500, 380000.343750, 380000.406250, 380000.593750",\ + "380000.406250, 380000.406250, 380000.437500, 380000.500000, 380000.687500",\ + "380000.468750, 380000.468750, 380000.500000, 380000.562500, 380000.750000",\ + "380000.625000, 380000.625000, 380000.656250, 380000.718750, 380000.906250",\ + "380000.843750, 380000.843750, 380000.875000, 380000.937500, 380001.125000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380001.781250, 380001.812500, 380001.906250, 380002.187500, 380002.875000",\ + "380001.875000, 380001.906250, 380002.000000, 380002.281250, 380002.968750",\ + "380001.968750, 380002.000000, 380002.093750, 380002.375000, 380003.062500",\ + "380002.156250, 380002.187500, 380002.281250, 380002.562500, 380003.250000",\ + "380002.406250, 380002.437500, 380002.531250, 380002.812500, 380003.500000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169"); + } + + } /* end of arc padmux2ast_i[4]_ast2padmux_o[7]_inv_min*/ + +} /* end of pin ast2padmux_o[7] */ + +pin("ast2padmux_o[6]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.028584 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : ast2padmux_o[6]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380001.875000, 380001.937500, 380002.062500, 380002.375000, 380003.250000",\ + "380001.968750, 380002.031250, 380002.156250, 380002.468750, 380003.343750",\ + "380002.062500, 380002.125000, 380002.250000, 380002.562500, 380003.437500",\ + "380002.125000, 380002.187500, 380002.312500, 380002.625000, 380003.500000",\ + "380002.468750, 380002.531250, 380002.656250, 380002.968750, 380003.843750"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189354, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189354, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189365, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189385, 0.392560, 0.950608, 2.441526",\ + "0.073824, 0.189425, 0.393252, 0.950608, 2.441526"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380000.437500, 380000.437500, 380000.468750, 380000.531250, 380000.718750",\ + "380000.531250, 380000.531250, 380000.562500, 380000.625000, 380000.812500",\ + "380000.593750, 380000.593750, 380000.625000, 380000.687500, 380000.875000",\ + "380000.656250, 380000.656250, 380000.687500, 380000.750000, 380000.937500",\ + "380000.968750, 380000.968750, 380001.000000, 380001.062500, 380001.250000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497"); + } + + } /* end of arc clk_ast_tlul_i_ast2padmux_o[6]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.118063, 0.173160, 0.267375, 0.527316, 1.216798",\ + "0.205470, 0.260567, 0.354781, 0.614720, 1.304204",\ + "0.286205, 0.341346, 0.435579, 0.695608, 1.384949",\ + "0.343571, 0.398793, 0.493060, 0.753254, 1.442331",\ + "0.643636, 0.699058, 0.793671, 1.054205, 1.742813"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.055140, 0.149920, 0.315966, 0.770671, 1.992169",\ + "0.055140, 0.149920, 0.315966, 0.770671, 1.992169",\ + "0.055064, 0.149920, 0.315966, 0.770616, 1.992169",\ + "0.054924, 0.149920, 0.315966, 0.770514, 1.992169",\ + "0.054820, 0.149920, 0.315966, 0.770514, 1.988361"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.068977, 0.083624, 0.108789, 0.177707, 0.362145",\ + "0.157440, 0.172093, 0.197279, 0.266195, 0.450612",\ + "0.246166, 0.261189, 0.286407, 0.355291, 0.539679",\ + "0.308361, 0.324424, 0.349591, 0.418444, 0.602842",\ + "0.630702, 0.654723, 0.683267, 0.752219, 0.936438"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.015416, 0.041075, 0.085652, 0.207740, 0.535967",\ + "0.015763, 0.041089, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967"); + } + + } /* end of arc clk_ast_tlul_i_ast2padmux_o[6]_redg_min*/ + + timing () { + related_pin : "fla_obs_i[6]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.111862, 0.178517, 0.294685, 0.611498, 1.461412",\ + "0.196887, 0.263820, 0.381200, 0.697836, 1.546758",\ + "0.280874, 0.348002, 0.465333, 0.783744, 1.631498",\ + "0.419192, 0.490016, 0.607541, 0.927454, 1.774732",\ + "0.629434, 0.713469, 0.835221, 1.155234, 2.004311"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067759, 0.184639, 0.382501, 0.937507, 2.417566",\ + "0.067759, 0.184639, 0.382501, 0.937507, 2.418347",\ + "0.069174, 0.184639, 0.382586, 0.937507, 2.418347",\ + "0.077831, 0.187460, 0.383300, 0.940319, 2.418347",\ + "0.099054, 0.205738, 0.390315, 0.940320, 2.425200"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.103322, 0.134506, 0.187130, 0.329612, 0.708263",\ + "0.188196, 0.219801, 0.272413, 0.414932, 0.793505",\ + "0.281500, 0.317246, 0.369943, 0.512302, 0.890520",\ + "0.433568, 0.478875, 0.537406, 0.680993, 1.058708",\ + "0.668936, 0.733428, 0.809479, 0.962224, 1.340585"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040521, 0.090274, 0.180244, 0.428614, 1.092440",\ + "0.042863, 0.090977, 0.180401, 0.428614, 1.092696",\ + "0.054661, 0.097371, 0.180899, 0.428690, 1.092793",\ + "0.077190, 0.120374, 0.194930, 0.430280, 1.092793",\ + "0.118581, 0.174509, 0.240947, 0.445113, 1.092793"); + } + + } /* end of arc fla_obs_i[6]_ast2padmux_o[6]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "fla_obs_i[6]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.110629, 0.177262, 0.293339, 0.610165, 1.460154",\ + "0.194795, 0.261696, 0.378936, 0.695592, 1.544629",\ + "0.275980, 0.343081, 0.460479, 0.778514, 1.626463",\ + "0.408884, 0.478137, 0.595421, 0.915532, 1.762573",\ + "0.610985, 0.691263, 0.810230, 1.128954, 1.977655"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067834, 0.183634, 0.382402, 0.934951, 2.414331",\ + "0.067834, 0.183634, 0.382402, 0.934951, 2.414331",\ + "0.068631, 0.183634, 0.382540, 0.936478, 2.414331",\ + "0.075251, 0.185541, 0.383090, 0.939701, 2.414331",\ + "0.093347, 0.198994, 0.384563, 0.939701, 2.425563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.077370, 0.108647, 0.161299, 0.303710, 0.682406",\ + "0.166391, 0.197521, 0.250129, 0.392651, 0.771277",\ + "0.253394, 0.288299, 0.340979, 0.483371, 0.861661",\ + "0.395347, 0.439383, 0.496795, 0.640121, 1.017884",\ + "0.615736, 0.679130, 0.754042, 0.905113, 1.283136"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039363, 0.090228, 0.180124, 0.428312, 1.092155",\ + "0.041196, 0.090228, 0.180315, 0.428312, 1.092511",\ + "0.052267, 0.096073, 0.180798, 0.428601, 1.092511",\ + "0.074482, 0.116813, 0.192279, 0.430033, 1.092511",\ + "0.116096, 0.171326, 0.236992, 0.441817, 1.092511"); + } + + } /* end of arc fla_obs_i[6]_ast2padmux_o[6]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[10]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.401444, 0.432876, 0.485584, 0.627937, 1.006534",\ + "0.426514, 0.457945, 0.510653, 0.653006, 1.031603",\ + "0.495788, 0.527220, 0.579928, 0.722281, 1.100878",\ + "0.620121, 0.651552, 0.704261, 0.846613, 1.225210",\ + "1.225494, 1.256926, 1.309634, 1.451987, 1.830584"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.665410, 0.732314, 0.848751, 1.168420, 2.023626",\ + "0.685984, 0.752887, 0.869324, 1.188993, 2.044199",\ + "0.744648, 0.811551, 0.927989, 1.247657, 2.102863",\ + "0.853883, 0.920786, 1.037224, 1.356892, 2.212098",\ + "1.621675, 1.688580, 1.805019, 2.124689, 2.979892"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073039, 0.188935, 0.391846, 0.949113, 2.441342"); + } + + } /* end of arc obs_ctrl_o[10]_ast2padmux_o[6]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[10]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.345553, 0.376966, 0.429613, 0.572027, 0.950669",\ + "0.369011, 0.400424, 0.453071, 0.595485, 0.974127",\ + "0.440108, 0.471521, 0.524168, 0.666582, 1.045224",\ + "0.565305, 0.596718, 0.649365, 0.791779, 1.170421",\ + "1.171631, 1.203044, 1.255693, 1.398105, 1.776746"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\ + "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\ + "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\ + "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\ + "0.039018, 0.090728, 0.180391, 0.429207, 1.091650"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.663782, 0.730673, 0.847101, 1.166770, 2.021989",\ + "0.679934, 0.746826, 0.863254, 1.182922, 2.038141",\ + "0.743020, 0.809911, 0.926339, 1.246007, 2.101227",\ + "0.852255, 0.919146, 1.035574, 1.355242, 2.210462",\ + "1.620317, 1.687211, 1.803640, 2.123309, 2.978526"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\ + "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\ + "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\ + "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\ + "0.073030, 0.188915, 0.391817, 0.949051, 2.441332"); + } + + } /* end of arc obs_ctrl_o[10]_ast2padmux_o[6]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[11]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.034927, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.180024, 0.211452, 0.264149, 0.406513, 0.785119",\ + "0.193406, 0.224834, 0.277531, 0.419896, 0.798501",\ + "0.275919, 0.307349, 0.360051, 0.502410, 0.881011",\ + "0.400910, 0.432352, 0.485095, 0.627414, 1.005985",\ + "0.975060, 1.010086, 1.063144, 1.205732, 1.584486"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.034927, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039119, 0.090633, 0.180636, 0.429262, 1.090996",\ + "0.039119, 0.090633, 0.180636, 0.429262, 1.090996",\ + "0.039132, 0.090633, 0.180667, 0.429269, 1.090996",\ + "0.039215, 0.090633, 0.180868, 0.429314, 1.090996",\ + "0.049347, 0.094034, 0.180868, 0.429355, 1.091896"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037147, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.465437, 0.532662, 0.649281, 0.969044, 1.824018",\ + "0.477695, 0.544920, 0.661539, 0.981302, 1.836276",\ + "0.541916, 0.609140, 0.725760, 1.045521, 1.900495",\ + "0.644626, 0.711856, 0.828474, 1.148242, 2.003221",\ + "1.319722, 1.387140, 1.503696, 1.823662, 2.678811"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037147, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073817, 0.189281, 0.392442, 0.950607, 2.441526",\ + "0.073817, 0.189281, 0.392442, 0.950607, 2.441526",\ + "0.073817, 0.189282, 0.392442, 0.950607, 2.441526",\ + "0.073862, 0.189282, 0.392442, 0.950619, 2.441526",\ + "0.075399, 0.189282, 0.392442, 0.951039, 2.441526"); + } + + } /* end of arc obs_ctrl_o[11]_ast2padmux_o[6]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[11]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.030664, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.159139, 0.190553, 0.243202, 0.385613, 0.764254",\ + "0.170514, 0.201928, 0.254577, 0.396989, 0.775629",\ + "0.255576, 0.286993, 0.339652, 0.482053, 0.860686",\ + "0.379908, 0.411340, 0.464049, 0.606401, 0.984998",\ + "0.945167, 0.979651, 1.032663, 1.175209, 1.553933"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.030664, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039020, 0.090609, 0.180397, 0.429208, 1.090831",\ + "0.039020, 0.090609, 0.180397, 0.429208, 1.090831",\ + "0.039042, 0.090609, 0.180449, 0.429220, 1.090831",\ + "0.039144, 0.090609, 0.180675, 0.429276, 1.090831",\ + "0.047820, 0.093501, 0.180675, 0.429352, 1.091629"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.028580, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.461683, 0.528880, 0.645509, 0.965243, 1.820192",\ + "0.470327, 0.537524, 0.654153, 0.973887, 1.828836",\ + "0.538174, 0.605371, 0.721999, 1.041733, 1.896681",\ + "0.640782, 0.707985, 0.824611, 1.144351, 1.999304",\ + "1.312551, 1.379913, 1.496487, 1.816396, 2.671496"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.028580, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073594, 0.189124, 0.392388, 0.950544, 2.441454",\ + "0.073594, 0.189124, 0.392388, 0.950544, 2.441454",\ + "0.073594, 0.189124, 0.392388, 0.950544, 2.441454",\ + "0.073633, 0.189124, 0.392388, 0.950557, 2.441454",\ + "0.074954, 0.189124, 0.392388, 0.950917, 2.441454"); + } + + } /* end of arc obs_ctrl_o[11]_ast2padmux_o[6]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.500858, 0.568082, 0.684702, 1.004464, 1.859437",\ + "0.516623, 0.583848, 0.700467, 1.020230, 1.875203",\ + "0.590734, 0.657958, 0.774578, 1.094340, 1.949314",\ + "0.681946, 0.749171, 0.865790, 1.185553, 2.040526",\ + "1.108576, 1.175805, 1.292423, 1.612190, 2.467167"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073816, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073848, 0.189277, 0.392440, 0.950615, 2.441524"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.275118, 0.306284, 0.358903, 0.501398, 0.880041",\ + "0.290749, 0.321915, 0.374533, 0.517029, 0.895671",\ + "0.363703, 0.394869, 0.447488, 0.589983, 0.968626",\ + "0.474794, 0.505959, 0.558577, 0.701073, 1.079716",\ + "1.013269, 1.044421, 1.097036, 1.239541, 1.618177"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040759, 0.090626, 0.180653, 0.429266, 1.092499",\ + "0.040922, 0.090525, 0.180916, 0.429325, 1.092539"); + } + + } /* end of arc obs_ctrl_o[4]_ast2padmux_o[6]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.337608, 0.404302, 0.520641, 0.837429, 1.687203",\ + "0.349939, 0.416633, 0.532972, 0.849760, 1.699534",\ + "0.408752, 0.475446, 0.591785, 0.908573, 1.758347",\ + "0.496083, 0.562777, 0.679117, 0.995905, 1.845678",\ + "0.949078, 1.015776, 1.132136, 1.448920, 2.298678"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184560, 0.382485, 0.937098, 2.417677",\ + "0.067604, 0.184551, 0.382483, 0.937052, 2.417689"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.209985, 0.241400, 0.294052, 0.436461, 0.815099",\ + "0.221857, 0.253271, 0.305923, 0.448332, 0.826970",\ + "0.304351, 0.335766, 0.388417, 0.530826, 0.909465",\ + "0.409226, 0.440642, 0.493298, 0.635702, 1.014338",\ + "0.909442, 0.940877, 0.993596, 1.135938, 1.514527"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039034, 0.090327, 0.180161, 0.428971, 1.091542",\ + "0.039166, 0.090324, 0.180166, 0.428948, 1.090692"); + } + + } /* end of arc obs_ctrl_o[4]_ast2padmux_o[6]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.287803, 0.318969, 0.371587, 0.514083, 0.892726",\ + "0.303569, 0.334734, 0.387353, 0.529848, 0.908491",\ + "0.378810, 0.409975, 0.462594, 0.605089, 0.983732",\ + "0.473884, 0.505049, 0.557668, 0.700163, 1.078806",\ + "0.918190, 0.949342, 1.001956, 1.144462, 1.523098"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040759, 0.090626, 0.180653, 0.429266, 1.092499",\ + "0.040922, 0.090525, 0.180916, 0.429325, 1.092539"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.376755, 0.443500, 0.560063, 0.876818, 1.726409",\ + "0.392417, 0.459162, 0.575725, 0.892480, 1.742071",\ + "0.467424, 0.534169, 0.650732, 0.967487, 1.817078",\ + "0.562603, 0.629351, 0.745928, 1.062681, 1.912261",\ + "1.006927, 1.073706, 1.190415, 1.507149, 2.356620"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073816, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073848, 0.189277, 0.392440, 0.950615, 2.441524"); + } + + } /* end of arc obs_ctrl_o[4]_ast2padmux_o[6]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.264318, 0.295567, 0.348210, 0.490643, 0.869326",\ + "0.278489, 0.309737, 0.362381, 0.504814, 0.883496",\ + "0.355325, 0.386573, 0.439217, 0.581649, 0.960332",\ + "0.450369, 0.481617, 0.534260, 0.676693, 1.055376",\ + "0.893831, 0.925076, 0.977718, 1.120154, 1.498834"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039034, 0.090327, 0.180161, 0.428971, 1.091542",\ + "0.039166, 0.090324, 0.180166, 0.428948, 1.090692"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.373701, 0.440395, 0.556734, 0.873522, 1.723296",\ + "0.385572, 0.452266, 0.568605, 0.885393, 1.735167",\ + "0.464371, 0.531065, 0.647404, 0.964192, 1.813966",\ + "0.559385, 0.626079, 0.742420, 1.059207, 1.908981",\ + "1.002245, 1.068944, 1.185303, 1.502088, 2.351846"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184560, 0.382485, 0.937098, 2.417677",\ + "0.067604, 0.184551, 0.382483, 0.937052, 2.417689"); + } + + } /* end of arc obs_ctrl_o[4]_ast2padmux_o[6]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.337998, 0.404744, 0.521308, 0.838063, 1.687653",\ + "0.353177, 0.419923, 0.536487, 0.853242, 1.702832",\ + "0.412195, 0.478941, 0.595505, 0.912260, 1.761850",\ + "0.508449, 0.575199, 0.691783, 1.008535, 1.858109",\ + "0.997007, 1.063817, 1.180658, 1.497372, 2.346736"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\ + "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073887, 0.189271, 0.392439, 0.950626, 2.441522",\ + "0.075818, 0.189005, 0.392348, 0.951153, 2.441399"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.272032, 0.303198, 0.355817, 0.498312, 0.876955",\ + "0.289891, 0.321056, 0.373675, 0.516170, 0.894813",\ + "0.360955, 0.392121, 0.444739, 0.587235, 0.965878",\ + "0.471378, 0.502542, 0.555160, 0.697656, 1.076298",\ + "1.004117, 1.035227, 1.087829, 1.230366, 1.608983"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\ + "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\ + "0.040752, 0.090633, 0.180666, 0.429269, 1.092497",\ + "0.040771, 0.090633, 0.180871, 0.429315, 1.092502",\ + "0.049622, 0.094130, 0.180871, 0.429356, 1.092666"); + } + + } /* end of arc obs_ctrl_o[5]_ast2padmux_o[6]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.329221, 0.395915, 0.512254, 0.829041, 1.678816",\ + "0.344592, 0.411286, 0.527624, 0.844412, 1.694187",\ + "0.406780, 0.473474, 0.589813, 0.906601, 1.756375",\ + "0.502234, 0.568932, 0.685288, 1.002073, 1.851833",\ + "0.957622, 1.024367, 1.140929, 1.457685, 2.307276"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067607, 0.184553, 0.382483, 0.937060, 2.417687",\ + "0.067439, 0.184458, 0.382464, 0.936568, 2.417820"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.231492, 0.262740, 0.315383, 0.457816, 0.836499",\ + "0.245351, 0.276600, 0.329243, 0.471676, 0.850359",\ + "0.320124, 0.351372, 0.404016, 0.546449, 0.925131",\ + "0.430166, 0.461410, 0.514053, 0.656489, 1.035169",\ + "0.955028, 0.986237, 1.038869, 1.181331, 1.559995"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039041, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039146, 0.090294, 0.180167, 0.428752, 1.090822",\ + "0.040211, 0.090294, 0.180212, 0.428752, 1.091676"); + } + + } /* end of arc obs_ctrl_o[5]_ast2padmux_o[6]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[5]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.176901, 0.208329, 0.261026, 0.403390, 0.781996",\ + "0.196158, 0.227585, 0.280282, 0.422647, 0.801252",\ + "0.273304, 0.304734, 0.357436, 0.499795, 0.878396",\ + "0.397207, 0.428649, 0.481392, 0.623711, 1.002282",\ + "0.961790, 0.996912, 1.049978, 1.192575, 1.571334"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\ + "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\ + "0.040752, 0.090633, 0.180666, 0.429269, 1.092497",\ + "0.040771, 0.090633, 0.180871, 0.429315, 1.092502",\ + "0.049622, 0.094130, 0.180871, 0.429356, 1.092666"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.455825, 0.523049, 0.639668, 0.959430, 1.814404",\ + "0.468963, 0.536187, 0.652807, 0.972569, 1.827542",\ + "0.531289, 0.598514, 0.715133, 1.034896, 1.889869",\ + "0.640154, 0.707387, 0.824004, 1.143775, 1.998757",\ + "1.332501, 1.399969, 1.516508, 1.836528, 2.691724"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\ + "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073887, 0.189271, 0.392439, 0.950626, 2.441522",\ + "0.075818, 0.189005, 0.392348, 0.951153, 2.441399"); + } + + } /* end of arc obs_ctrl_o[5]_ast2padmux_o[6]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[5]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.155833, 0.187247, 0.239896, 0.382308, 0.760949",\ + "0.173482, 0.204896, 0.257545, 0.399957, 0.778598",\ + "0.252964, 0.284381, 0.337040, 0.479441, 0.858074",\ + "0.376196, 0.407628, 0.460337, 0.602689, 0.981285",\ + "0.931678, 0.966257, 1.019278, 1.161831, 1.540560"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039041, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039146, 0.090294, 0.180167, 0.428752, 1.090822",\ + "0.040211, 0.090294, 0.180212, 0.428752, 1.091676"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.452081, 0.519278, 0.635907, 0.955640, 1.810589",\ + "0.461862, 0.529059, 0.645688, 0.965421, 1.820370",\ + "0.527542, 0.594739, 0.711368, 1.031102, 1.886050",\ + "0.636262, 0.703467, 0.820093, 1.139835, 1.994791",\ + "1.324350, 1.391756, 1.508316, 1.828270, 2.683409"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067607, 0.184553, 0.382483, 0.937060, 2.417687",\ + "0.067439, 0.184458, 0.382464, 0.936568, 2.417820"); + } + + } /* end of arc obs_ctrl_o[5]_ast2padmux_o[6]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[6]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.325984, 0.393209, 0.509828, 0.829592, 1.684567",\ + "0.341732, 0.408957, 0.525576, 0.845340, 1.700314",\ + "0.405621, 0.472847, 0.589466, 0.909229, 1.764204",\ + "0.483984, 0.551208, 0.667827, 0.987590, 1.842564",\ + "0.876566, 0.943791, 1.060410, 1.380173, 2.235147"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189281, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189281, 0.392442, 0.950608, 2.441526"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.207560, 0.238992, 0.291700, 0.434053, 0.812650",\ + "0.223441, 0.254873, 0.307582, 0.449934, 0.828531",\ + "0.292964, 0.324396, 0.377105, 0.519457, 0.898054",\ + "0.382304, 0.413736, 0.466444, 0.608797, 0.987394",\ + "0.808201, 0.839636, 0.892354, 1.034697, 1.413287"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\ + "0.040785, 0.090610, 0.180744, 0.429286, 1.092505"); + } + + } /* end of arc obs_ctrl_o[6]_ast2padmux_o[6]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[6]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.298728, 0.365697, 0.482189, 0.801862, 1.656989",\ + "0.312838, 0.379807, 0.496299, 0.815972, 1.671100",\ + "0.378416, 0.445385, 0.561877, 0.881551, 1.736677",\ + "0.456978, 0.523948, 0.640441, 0.960115, 1.815240",\ + "0.852482, 0.919491, 1.036016, 1.355692, 2.210772"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067586, 0.184541, 0.382481, 0.936998, 2.417704"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.185526, 0.216941, 0.269593, 0.412001, 0.790640",\ + "0.197528, 0.228943, 0.281595, 0.424004, 0.802642",\ + "0.270950, 0.302365, 0.355017, 0.497425, 0.876064",\ + "0.360375, 0.391790, 0.444442, 0.586850, 0.965489",\ + "0.786063, 0.817479, 0.870138, 1.012540, 1.391174"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039039, 0.090322, 0.180169, 0.428938, 1.091513"); + } + + } /* end of arc obs_ctrl_o[6]_ast2padmux_o[6]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[6]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.314064, 0.345229, 0.397848, 0.540343, 0.918986",\ + "0.329859, 0.361025, 0.413644, 0.556139, 0.934782",\ + "0.407724, 0.438890, 0.491508, 0.634004, 1.012646",\ + "0.508778, 0.539944, 0.592562, 0.735058, 1.113701",\ + "0.984655, 1.015818, 1.068436, 1.210933, 1.589574"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\ + "0.040785, 0.090610, 0.180744, 0.429286, 1.092505"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.596327, 0.663552, 0.780171, 1.099935, 1.954909",\ + "0.609131, 0.676356, 0.792975, 1.112739, 1.967713",\ + "0.677113, 0.744339, 0.860958, 1.180721, 2.035696",\ + "0.788810, 0.856034, 0.972654, 1.292416, 2.147390",\ + "1.273667, 1.340892, 1.457511, 1.777274, 2.632248"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189281, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189281, 0.392442, 0.950608, 2.441526"); + } + + } /* end of arc obs_ctrl_o[6]_ast2padmux_o[6]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[6]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.262848, 0.294262, 0.346915, 0.489323, 0.867962",\ + "0.276998, 0.308413, 0.361065, 0.503474, 0.882112",\ + "0.356726, 0.388141, 0.440793, 0.583202, 0.961840",\ + "0.457948, 0.489362, 0.542015, 0.684423, 1.063061",\ + "0.929777, 0.961193, 1.013852, 1.156254, 1.534888"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039039, 0.090322, 0.180169, 0.428938, 1.091513"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.437011, 0.503705, 0.620045, 0.936832, 1.786606",\ + "0.446608, 0.513302, 0.629642, 0.946429, 1.796203",\ + "0.517780, 0.584475, 0.700814, 1.017602, 1.867376",\ + "0.629396, 0.696091, 0.812430, 1.129218, 1.978992",\ + "1.131911, 1.198614, 1.314996, 1.631778, 2.481517"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067586, 0.184541, 0.382481, 0.936998, 2.417704"); + } + + } /* end of arc obs_ctrl_o[6]_ast2padmux_o[6]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[7]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.060518, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.315427, 0.346593, 0.399212, 0.541707, 0.920350",\ + "0.342146, 0.373312, 0.425930, 0.568426, 0.947068",\ + "0.410184, 0.441350, 0.493968, 0.636464, 1.015106",\ + "0.512927, 0.544093, 0.596711, 0.739207, 1.117850",\ + "0.999580, 1.030743, 1.083361, 1.225858, 1.604500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.060518, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180697, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180697, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180697, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180732, 0.429283, 1.092497",\ + "0.042004, 0.091469, 0.180867, 0.429340, 1.092504"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.051005, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.597332, 0.664558, 0.781177, 1.100940, 1.955915",\ + "0.618079, 0.685305, 0.801924, 1.121688, 1.976662",\ + "0.683404, 0.750630, 0.867249, 1.187012, 2.041987",\ + "0.797603, 0.864828, 0.981447, 1.301210, 2.156184",\ + "1.375793, 1.443018, 1.559637, 1.879400, 2.734374"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.051005, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189280, 0.392442, 0.950609, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073823, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073819, 0.189281, 0.392442, 0.950607, 2.441526",\ + "0.073817, 0.189281, 0.392442, 0.950607, 2.441526"); + } + + } /* end of arc obs_ctrl_o[7]_ast2padmux_o[6]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[7]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.049671, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.150722, 0.182137, 0.234789, 0.377197, 0.755836",\ + "0.171205, 0.202620, 0.255272, 0.397681, 0.776319",\ + "0.246518, 0.277932, 0.330585, 0.472993, 0.851631",\ + "0.352324, 0.383738, 0.436391, 0.578799, 0.957437",\ + "0.825559, 0.856975, 0.909634, 1.052036, 1.430670"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.049671, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039038, 0.090323, 0.180168, 0.428941, 1.091519"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040467, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.277343, 0.344312, 0.460804, 0.780477, 1.635605",\ + "0.293355, 0.360323, 0.476815, 0.796489, 1.651616",\ + "0.366113, 0.433085, 0.549579, 0.869253, 1.724376",\ + "0.487008, 0.554003, 0.670516, 0.990192, 1.845287",\ + "1.141953, 1.209132, 1.325766, 1.645481, 2.500414"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040467, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067601, 0.184550, 0.382483, 0.937044, 2.417691"); + } + + } /* end of arc obs_ctrl_o[7]_ast2padmux_o[6]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[8]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.690094, 0.756997, 0.873435, 1.193104, 2.048309",\ + "0.708444, 0.775347, 0.891784, 1.211453, 2.066659",\ + "0.778290, 0.845193, 0.961630, 1.281299, 2.136505",\ + "0.871001, 0.937904, 1.054342, 1.374010, 2.229216",\ + "1.316481, 1.383384, 1.499822, 1.819491, 2.674696"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.452134, 0.483566, 0.536274, 0.678627, 1.057224",\ + "0.469561, 0.500993, 0.553701, 0.696054, 1.074651",\ + "0.546928, 0.578360, 0.631068, 0.773421, 1.152018",\ + "0.655300, 0.686732, 0.739440, 0.881793, 1.260390",\ + "1.172032, 1.203463, 1.256172, 1.398524, 1.777121"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837"); + } + + } /* end of arc obs_ctrl_o[8]_ast2padmux_o[6]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[8]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.688464, 0.755356, 0.871784, 1.191452, 2.046671",\ + "0.705080, 0.771971, 0.888399, 1.208067, 2.063287",\ + "0.776660, 0.843551, 0.959979, 1.279647, 2.134867",\ + "0.869371, 0.936263, 1.052691, 1.372359, 2.227578",\ + "1.314852, 1.381744, 1.498172, 1.817840, 2.673059"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\ + "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\ + "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\ + "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\ + "0.073029, 0.188911, 0.391812, 0.949040, 2.441330"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.396265, 0.427678, 0.480325, 0.622739, 1.001381",\ + "0.409612, 0.441025, 0.493672, 0.636085, 1.014728",\ + "0.491059, 0.522472, 0.575119, 0.717533, 1.096175",\ + "0.599541, 0.630954, 0.683601, 0.826015, 1.204657",\ + "1.117451, 1.148864, 1.201511, 1.343925, 1.722567"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\ + "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\ + "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\ + "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\ + "0.039014, 0.090731, 0.180384, 0.429205, 1.091671"); + } + + } /* end of arc obs_ctrl_o[8]_ast2padmux_o[6]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[9]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.701899, 0.768802, 0.885240, 1.204909, 2.060114",\ + "0.720452, 0.787355, 0.903793, 1.223462, 2.078667",\ + "0.793150, 0.860053, 0.976490, 1.296159, 2.151365",\ + "0.888367, 0.955270, 1.071708, 1.391377, 2.246583",\ + "1.341174, 1.408077, 1.524515, 1.844184, 2.699389"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.458526, 0.489958, 0.542666, 0.685019, 1.063616",\ + "0.476069, 0.507500, 0.560208, 0.702561, 1.081158",\ + "0.553398, 0.584829, 0.637537, 0.779890, 1.158487",\ + "0.662868, 0.694299, 0.747008, 0.889361, 1.267957",\ + "1.187448, 1.218880, 1.271588, 1.413941, 1.792538"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837"); + } + + } /* end of arc obs_ctrl_o[9]_ast2padmux_o[6]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[9]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.700268, 0.767160, 0.883588, 1.203256, 2.058475",\ + "0.717089, 0.783981, 0.900409, 1.220077, 2.075296",\ + "0.791519, 0.858410, 0.974838, 1.294506, 2.149726",\ + "0.886736, 0.953628, 1.070056, 1.389724, 2.244943",\ + "1.339543, 1.406435, 1.522863, 1.842531, 2.697751"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\ + "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\ + "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\ + "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\ + "0.073029, 0.188911, 0.391812, 0.949040, 2.441330"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.402716, 0.434129, 0.486776, 0.629190, 1.007832",\ + "0.416173, 0.447586, 0.500233, 0.642646, 1.021289",\ + "0.497588, 0.529001, 0.581648, 0.724061, 1.102704",\ + "0.607156, 0.638569, 0.691216, 0.833630, 1.212272",\ + "1.132876, 1.164289, 1.216936, 1.359350, 1.737992"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\ + "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\ + "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\ + "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\ + "0.039014, 0.090731, 0.180384, 0.429205, 1.091671"); + } + + } /* end of arc obs_ctrl_o[9]_ast2padmux_o[6]_una_min*/ + + timing () { + related_pin : "otm_obs_i[6]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.123879, 0.190820, 0.307288, 0.626960, 1.482121",\ + "0.210891, 0.277978, 0.394567, 0.714249, 1.569235",\ + "0.301781, 0.369068, 0.485667, 0.805496, 1.660526",\ + "0.453978, 0.523120, 0.640034, 0.960158, 1.815427",\ + "0.695902, 0.774527, 0.893732, 1.214148, 2.069560"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073065, 0.188997, 0.391936, 0.949305, 2.441374",\ + "0.073175, 0.189249, 0.392304, 0.950092, 2.441498",\ + "0.074330, 0.189249, 0.392418, 0.950747, 2.441498",\ + "0.079436, 0.191164, 0.392505, 0.951076, 2.441498",\ + "0.098084, 0.204137, 0.393542, 0.951076, 2.441498"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.114293, 0.145721, 0.198417, 0.340782, 0.719388",\ + "0.205394, 0.236828, 0.289545, 0.431889, 0.810480",\ + "0.309904, 0.342065, 0.394885, 0.537244, 0.915841",\ + "0.501618, 0.536979, 0.590065, 0.732680, 1.111452",\ + "0.825607, 0.870622, 0.930343, 1.075147, 1.454209"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039117, 0.090634, 0.180632, 0.429261, 1.091005",\ + "0.039161, 0.090634, 0.180739, 0.429285, 1.091005",\ + "0.041267, 0.091212, 0.180891, 0.429338, 1.091005",\ + "0.050293, 0.094364, 0.180891, 0.429357, 1.092061",\ + "0.068556, 0.114740, 0.192215, 0.429716, 1.093122"); + } + + } /* end of arc otm_obs_i[6]_ast2padmux_o[6]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "otm_obs_i[6]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.120559, 0.187489, 0.303948, 0.623619, 1.478793",\ + "0.205712, 0.272774, 0.389342, 0.709022, 1.564038",\ + "0.292652, 0.359907, 0.476516, 0.796311, 1.651312",\ + "0.437434, 0.505450, 0.622092, 0.942182, 1.797434",\ + "0.662107, 0.738115, 0.856688, 1.177023, 2.032395"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073057, 0.188977, 0.391908, 0.949245, 2.441364",\ + "0.073156, 0.189206, 0.392241, 0.949956, 2.441378",\ + "0.074065, 0.189247, 0.392382, 0.950255, 2.441378",\ + "0.077223, 0.189624, 0.392382, 0.950255, 2.441378",\ + "0.092938, 0.200557, 0.393255, 0.950255, 2.441468"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.094368, 0.125782, 0.178430, 0.320842, 0.699483",\ + "0.188259, 0.219683, 0.272369, 0.414744, 0.793358",\ + "0.291365, 0.323244, 0.376040, 0.518376, 0.896959",\ + "0.474009, 0.509208, 0.562280, 0.704883, 1.083646",\ + "0.777508, 0.822171, 0.881623, 1.026340, 1.405392"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039018, 0.090654, 0.180392, 0.429207, 1.090346",\ + "0.039096, 0.090654, 0.180581, 0.429249, 1.090346",\ + "0.040472, 0.090934, 0.180608, 0.429337, 1.090346",\ + "0.049836, 0.094205, 0.180608, 0.429356, 1.091981",\ + "0.067933, 0.113945, 0.191732, 0.429701, 1.093101"); + } + + } /* end of arc otm_obs_i[6]_ast2padmux_o[6]_una_min*/ + + timing () { + related_pin : "otp_obs_i[6]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.122660, 0.189370, 0.305783, 0.622560, 1.472274",\ + "0.209824, 0.276743, 0.394059, 0.710704, 1.559679",\ + "0.301920, 0.369023, 0.486415, 0.804486, 1.652417",\ + "0.455547, 0.524976, 0.642287, 0.962376, 1.809444",\ + "0.699992, 0.780922, 0.900058, 1.218756, 2.067549"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067561, 0.184527, 0.382478, 0.936925, 2.417724",\ + "0.067561, 0.184527, 0.382478, 0.936925, 2.418306",\ + "0.068683, 0.184527, 0.382544, 0.936925, 2.418306",\ + "0.075540, 0.185756, 0.383113, 0.940410, 2.418306",\ + "0.094401, 0.199857, 0.384817, 0.940410, 2.426093"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.114764, 0.145947, 0.198571, 0.341053, 0.719705",\ + "0.205629, 0.236785, 0.289401, 0.431904, 0.810542",\ + "0.310076, 0.342571, 0.395201, 0.537686, 0.916183",\ + "0.500896, 0.538360, 0.591093, 0.733386, 1.111456",\ + "0.820213, 0.870292, 0.933027, 1.077593, 1.455130"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040532, 0.090273, 0.180246, 0.428609, 1.092443",\ + "0.040870, 0.090273, 0.180281, 0.428609, 1.092443",\ + "0.045400, 0.092351, 0.180508, 0.428609, 1.092443",\ + "0.059558, 0.100025, 0.181106, 0.428872, 1.092443",\ + "0.087354, 0.133744, 0.204884, 0.431205, 1.092443"); + } + + } /* end of arc otp_obs_i[6]_ast2padmux_o[6]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "otp_obs_i[6]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.119334, 0.186028, 0.302368, 0.619155, 1.468929",\ + "0.204833, 0.271716, 0.388876, 0.705544, 1.554647",\ + "0.293319, 0.360401, 0.477846, 0.795625, 1.643707",\ + "0.440314, 0.508488, 0.625608, 0.945855, 1.792734",\ + "0.667813, 0.745674, 0.864272, 1.183300, 2.031636"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.183691, 0.382409, 0.935142, 2.413233",\ + "0.067620, 0.183691, 0.382409, 0.935142, 2.413233",\ + "0.068262, 0.183691, 0.382508, 0.936031, 2.413233",\ + "0.073482, 0.184226, 0.382946, 0.939859, 2.413233",\ + "0.089380, 0.196045, 0.384240, 0.939859, 2.423100"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.094521, 0.125776, 0.178422, 0.320849, 0.699535",\ + "0.188239, 0.219444, 0.272075, 0.414540, 0.793202",\ + "0.291550, 0.323577, 0.376197, 0.518700, 0.897237",\ + "0.473699, 0.510899, 0.563627, 0.705929, 1.084022",\ + "0.773733, 0.823401, 0.885774, 1.030256, 1.407808"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039633, 0.090291, 0.180152, 0.428296, 1.092222",\ + "0.040262, 0.090291, 0.180217, 0.428296, 1.092377",\ + "0.044064, 0.091627, 0.180452, 0.428296, 1.092425",\ + "0.058805, 0.099616, 0.181075, 0.428844, 1.092425",\ + "0.086478, 0.132591, 0.204027, 0.431125, 1.092425"); + } + + } /* end of arc otp_obs_i[6]_ast2padmux_o[6]_una_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380000.312500, 380000.312500, 380000.343750, 380000.406250, 380000.593750",\ + "380000.406250, 380000.406250, 380000.437500, 380000.500000, 380000.687500",\ + "380000.500000, 380000.500000, 380000.531250, 380000.593750, 380000.781250",\ + "380000.656250, 380000.656250, 380000.687500, 380000.750000, 380000.937500",\ + "380000.906250, 380000.906250, 380000.937500, 380001.000000, 380001.187500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380001.781250, 380001.843750, 380001.968750, 380002.281250, 380003.156250",\ + "380001.875000, 380001.937500, 380002.062500, 380002.375000, 380003.250000",\ + "380002.000000, 380002.062500, 380002.187500, 380002.500000, 380003.375000",\ + "380002.187500, 380002.250000, 380002.375000, 380002.687500, 380003.562500",\ + "380002.500000, 380002.562500, 380002.687500, 380003.000000, 380003.875000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526"); + } + + } /* end of arc padmux2ast_i[4]_ast2padmux_o[6]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380000.312500, 380000.312500, 380000.343750, 380000.406250, 380000.593750",\ + "380000.406250, 380000.406250, 380000.437500, 380000.500000, 380000.687500",\ + "380000.468750, 380000.468750, 380000.500000, 380000.562500, 380000.750000",\ + "380000.625000, 380000.625000, 380000.656250, 380000.718750, 380000.906250",\ + "380000.843750, 380000.843750, 380000.875000, 380000.937500, 380001.125000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380001.781250, 380001.812500, 380001.906250, 380002.187500, 380002.875000",\ + "380001.875000, 380001.906250, 380002.000000, 380002.281250, 380002.968750",\ + "380001.968750, 380002.000000, 380002.093750, 380002.375000, 380003.062500",\ + "380002.156250, 380002.187500, 380002.281250, 380002.562500, 380003.250000",\ + "380002.406250, 380002.437500, 380002.531250, 380002.812500, 380003.500000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169"); + } + + } /* end of arc padmux2ast_i[4]_ast2padmux_o[6]_inv_min*/ + +} /* end of pin ast2padmux_o[6] */ + +pin("ast2padmux_o[5]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.028584 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : ast2padmux_o[5]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380001.875000, 380001.937500, 380002.062500, 380002.375000, 380003.250000",\ + "380001.968750, 380002.031250, 380002.156250, 380002.468750, 380003.343750",\ + "380002.062500, 380002.125000, 380002.250000, 380002.562500, 380003.437500",\ + "380002.125000, 380002.187500, 380002.312500, 380002.625000, 380003.500000",\ + "380002.468750, 380002.531250, 380002.656250, 380002.968750, 380003.843750"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189354, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189354, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189365, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189385, 0.392560, 0.950608, 2.441526",\ + "0.073824, 0.189425, 0.393252, 0.950608, 2.441526"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380000.437500, 380000.437500, 380000.468750, 380000.531250, 380000.718750",\ + "380000.531250, 380000.531250, 380000.562500, 380000.625000, 380000.812500",\ + "380000.593750, 380000.593750, 380000.625000, 380000.687500, 380000.875000",\ + "380000.656250, 380000.656250, 380000.687500, 380000.750000, 380000.937500",\ + "380000.968750, 380000.968750, 380001.000000, 380001.062500, 380001.250000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497"); + } + + } /* end of arc clk_ast_tlul_i_ast2padmux_o[5]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.118063, 0.173160, 0.267375, 0.527316, 1.216798",\ + "0.205470, 0.260567, 0.354781, 0.614720, 1.304204",\ + "0.286205, 0.341346, 0.435579, 0.695608, 1.384949",\ + "0.343571, 0.398793, 0.493060, 0.753254, 1.442331",\ + "0.643636, 0.699058, 0.793671, 1.054205, 1.742813"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.055140, 0.149920, 0.315966, 0.770671, 1.992169",\ + "0.055140, 0.149920, 0.315966, 0.770671, 1.992169",\ + "0.055064, 0.149920, 0.315966, 0.770616, 1.992169",\ + "0.054924, 0.149920, 0.315966, 0.770514, 1.992169",\ + "0.054820, 0.149920, 0.315966, 0.770514, 1.988361"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.068977, 0.083624, 0.108789, 0.177707, 0.362145",\ + "0.157440, 0.172093, 0.197279, 0.266195, 0.450612",\ + "0.246166, 0.261189, 0.286407, 0.355291, 0.539679",\ + "0.308361, 0.324424, 0.349591, 0.418444, 0.602842",\ + "0.630702, 0.654723, 0.683267, 0.752219, 0.936438"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.015416, 0.041075, 0.085652, 0.207740, 0.535967",\ + "0.015763, 0.041089, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967"); + } + + } /* end of arc clk_ast_tlul_i_ast2padmux_o[5]_redg_min*/ + + timing () { + related_pin : "fla_obs_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.111862, 0.178517, 0.294685, 0.611498, 1.461412",\ + "0.196887, 0.263820, 0.381200, 0.697836, 1.546758",\ + "0.280874, 0.348002, 0.465333, 0.783744, 1.631498",\ + "0.419192, 0.490016, 0.607541, 0.927454, 1.774732",\ + "0.629434, 0.713469, 0.835221, 1.155234, 2.004311"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067759, 0.184639, 0.382501, 0.937507, 2.417566",\ + "0.067759, 0.184639, 0.382501, 0.937507, 2.418347",\ + "0.069174, 0.184639, 0.382586, 0.937507, 2.418347",\ + "0.077831, 0.187460, 0.383300, 0.940319, 2.418347",\ + "0.099054, 0.205738, 0.390315, 0.940320, 2.425200"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.103322, 0.134506, 0.187130, 0.329612, 0.708263",\ + "0.188196, 0.219801, 0.272413, 0.414932, 0.793505",\ + "0.281500, 0.317246, 0.369943, 0.512302, 0.890520",\ + "0.433568, 0.478875, 0.537406, 0.680993, 1.058708",\ + "0.668936, 0.733428, 0.809479, 0.962224, 1.340585"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040521, 0.090274, 0.180244, 0.428614, 1.092440",\ + "0.042863, 0.090977, 0.180401, 0.428614, 1.092696",\ + "0.054661, 0.097371, 0.180899, 0.428690, 1.092793",\ + "0.077190, 0.120374, 0.194930, 0.430280, 1.092793",\ + "0.118581, 0.174509, 0.240947, 0.445113, 1.092793"); + } + + } /* end of arc fla_obs_i[5]_ast2padmux_o[5]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "fla_obs_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.110629, 0.177262, 0.293339, 0.610165, 1.460154",\ + "0.194795, 0.261696, 0.378936, 0.695592, 1.544629",\ + "0.275980, 0.343081, 0.460479, 0.778514, 1.626463",\ + "0.408884, 0.478137, 0.595421, 0.915532, 1.762573",\ + "0.610985, 0.691263, 0.810230, 1.128954, 1.977655"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067834, 0.183634, 0.382402, 0.934951, 2.414331",\ + "0.067834, 0.183634, 0.382402, 0.934951, 2.414331",\ + "0.068631, 0.183634, 0.382540, 0.936478, 2.414331",\ + "0.075251, 0.185541, 0.383090, 0.939701, 2.414331",\ + "0.093347, 0.198994, 0.384563, 0.939701, 2.425563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.077370, 0.108647, 0.161299, 0.303710, 0.682406",\ + "0.166391, 0.197521, 0.250129, 0.392651, 0.771277",\ + "0.253394, 0.288299, 0.340979, 0.483371, 0.861661",\ + "0.395347, 0.439383, 0.496795, 0.640121, 1.017884",\ + "0.615736, 0.679130, 0.754042, 0.905113, 1.283136"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039363, 0.090228, 0.180124, 0.428312, 1.092155",\ + "0.041196, 0.090228, 0.180315, 0.428312, 1.092511",\ + "0.052267, 0.096073, 0.180798, 0.428601, 1.092511",\ + "0.074482, 0.116813, 0.192279, 0.430033, 1.092511",\ + "0.116096, 0.171326, 0.236992, 0.441817, 1.092511"); + } + + } /* end of arc fla_obs_i[5]_ast2padmux_o[5]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[10]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.401444, 0.432876, 0.485584, 0.627937, 1.006534",\ + "0.426514, 0.457945, 0.510653, 0.653006, 1.031603",\ + "0.495788, 0.527220, 0.579928, 0.722281, 1.100878",\ + "0.620121, 0.651552, 0.704261, 0.846613, 1.225210",\ + "1.225494, 1.256926, 1.309634, 1.451987, 1.830584"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.665410, 0.732314, 0.848751, 1.168420, 2.023626",\ + "0.685984, 0.752887, 0.869324, 1.188993, 2.044199",\ + "0.744648, 0.811551, 0.927989, 1.247657, 2.102863",\ + "0.853883, 0.920786, 1.037224, 1.356892, 2.212098",\ + "1.621675, 1.688580, 1.805019, 2.124689, 2.979892"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073039, 0.188935, 0.391846, 0.949113, 2.441342"); + } + + } /* end of arc obs_ctrl_o[10]_ast2padmux_o[5]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[10]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.345553, 0.376966, 0.429613, 0.572027, 0.950669",\ + "0.369011, 0.400424, 0.453071, 0.595485, 0.974127",\ + "0.440108, 0.471521, 0.524168, 0.666582, 1.045224",\ + "0.565305, 0.596718, 0.649365, 0.791779, 1.170421",\ + "1.171631, 1.203044, 1.255693, 1.398105, 1.776746"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\ + "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\ + "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\ + "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\ + "0.039018, 0.090728, 0.180391, 0.429207, 1.091650"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.663782, 0.730673, 0.847101, 1.166770, 2.021989",\ + "0.679934, 0.746826, 0.863254, 1.182922, 2.038141",\ + "0.743020, 0.809911, 0.926339, 1.246007, 2.101227",\ + "0.852255, 0.919146, 1.035574, 1.355242, 2.210462",\ + "1.620317, 1.687211, 1.803640, 2.123309, 2.978526"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\ + "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\ + "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\ + "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\ + "0.073030, 0.188915, 0.391817, 0.949051, 2.441332"); + } + + } /* end of arc obs_ctrl_o[10]_ast2padmux_o[5]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[11]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.034927, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.180024, 0.211452, 0.264149, 0.406513, 0.785119",\ + "0.193406, 0.224834, 0.277531, 0.419896, 0.798501",\ + "0.275919, 0.307349, 0.360051, 0.502410, 0.881011",\ + "0.400910, 0.432352, 0.485095, 0.627414, 1.005985",\ + "0.975060, 1.010086, 1.063144, 1.205732, 1.584486"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.034927, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039119, 0.090633, 0.180636, 0.429262, 1.090996",\ + "0.039119, 0.090633, 0.180636, 0.429262, 1.090996",\ + "0.039132, 0.090633, 0.180667, 0.429269, 1.090996",\ + "0.039215, 0.090633, 0.180868, 0.429314, 1.090996",\ + "0.049347, 0.094034, 0.180868, 0.429355, 1.091896"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037147, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.465437, 0.532662, 0.649281, 0.969044, 1.824018",\ + "0.477695, 0.544920, 0.661539, 0.981302, 1.836276",\ + "0.541916, 0.609140, 0.725760, 1.045521, 1.900495",\ + "0.644626, 0.711856, 0.828474, 1.148242, 2.003221",\ + "1.319722, 1.387140, 1.503696, 1.823662, 2.678811"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037147, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073817, 0.189281, 0.392442, 0.950607, 2.441526",\ + "0.073817, 0.189281, 0.392442, 0.950607, 2.441526",\ + "0.073817, 0.189282, 0.392442, 0.950607, 2.441526",\ + "0.073862, 0.189282, 0.392442, 0.950619, 2.441526",\ + "0.075399, 0.189282, 0.392442, 0.951039, 2.441526"); + } + + } /* end of arc obs_ctrl_o[11]_ast2padmux_o[5]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[11]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.030664, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.159139, 0.190553, 0.243202, 0.385613, 0.764254",\ + "0.170514, 0.201928, 0.254577, 0.396989, 0.775629",\ + "0.255576, 0.286993, 0.339652, 0.482053, 0.860686",\ + "0.379908, 0.411340, 0.464049, 0.606401, 0.984998",\ + "0.945167, 0.979651, 1.032663, 1.175209, 1.553933"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.030664, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039020, 0.090609, 0.180397, 0.429208, 1.090831",\ + "0.039020, 0.090609, 0.180397, 0.429208, 1.090831",\ + "0.039042, 0.090609, 0.180449, 0.429220, 1.090831",\ + "0.039144, 0.090609, 0.180675, 0.429276, 1.090831",\ + "0.047820, 0.093501, 0.180675, 0.429352, 1.091629"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.028580, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.461683, 0.528880, 0.645509, 0.965243, 1.820192",\ + "0.470327, 0.537524, 0.654153, 0.973887, 1.828836",\ + "0.538174, 0.605371, 0.721999, 1.041733, 1.896681",\ + "0.640782, 0.707985, 0.824611, 1.144351, 1.999304",\ + "1.312551, 1.379913, 1.496487, 1.816396, 2.671496"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.028580, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073594, 0.189124, 0.392388, 0.950544, 2.441454",\ + "0.073594, 0.189124, 0.392388, 0.950544, 2.441454",\ + "0.073594, 0.189124, 0.392388, 0.950544, 2.441454",\ + "0.073633, 0.189124, 0.392388, 0.950557, 2.441454",\ + "0.074954, 0.189124, 0.392388, 0.950917, 2.441454"); + } + + } /* end of arc obs_ctrl_o[11]_ast2padmux_o[5]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.500858, 0.568082, 0.684702, 1.004464, 1.859437",\ + "0.516623, 0.583848, 0.700467, 1.020230, 1.875203",\ + "0.590734, 0.657958, 0.774578, 1.094340, 1.949314",\ + "0.681946, 0.749171, 0.865790, 1.185553, 2.040526",\ + "1.108576, 1.175805, 1.292423, 1.612190, 2.467167"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073816, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073848, 0.189277, 0.392440, 0.950615, 2.441524"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.275118, 0.306284, 0.358903, 0.501398, 0.880041",\ + "0.290749, 0.321915, 0.374533, 0.517029, 0.895671",\ + "0.363703, 0.394869, 0.447488, 0.589983, 0.968626",\ + "0.474794, 0.505959, 0.558577, 0.701073, 1.079716",\ + "1.013269, 1.044421, 1.097036, 1.239541, 1.618177"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040759, 0.090626, 0.180653, 0.429266, 1.092499",\ + "0.040922, 0.090525, 0.180916, 0.429325, 1.092539"); + } + + } /* end of arc obs_ctrl_o[4]_ast2padmux_o[5]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.337608, 0.404302, 0.520641, 0.837429, 1.687203",\ + "0.349939, 0.416633, 0.532972, 0.849760, 1.699534",\ + "0.408752, 0.475446, 0.591785, 0.908573, 1.758347",\ + "0.496083, 0.562777, 0.679117, 0.995905, 1.845678",\ + "0.949078, 1.015776, 1.132136, 1.448920, 2.298678"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184560, 0.382485, 0.937098, 2.417677",\ + "0.067604, 0.184551, 0.382483, 0.937052, 2.417689"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.209985, 0.241400, 0.294052, 0.436461, 0.815099",\ + "0.221857, 0.253271, 0.305923, 0.448332, 0.826970",\ + "0.304351, 0.335766, 0.388417, 0.530826, 0.909465",\ + "0.409226, 0.440642, 0.493298, 0.635702, 1.014338",\ + "0.909442, 0.940877, 0.993596, 1.135938, 1.514527"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039034, 0.090327, 0.180161, 0.428971, 1.091542",\ + "0.039166, 0.090324, 0.180166, 0.428948, 1.090692"); + } + + } /* end of arc obs_ctrl_o[4]_ast2padmux_o[5]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.287803, 0.318969, 0.371587, 0.514083, 0.892726",\ + "0.303569, 0.334734, 0.387353, 0.529848, 0.908491",\ + "0.378810, 0.409975, 0.462594, 0.605089, 0.983732",\ + "0.473884, 0.505049, 0.557668, 0.700163, 1.078806",\ + "0.918190, 0.949342, 1.001956, 1.144462, 1.523098"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040759, 0.090626, 0.180653, 0.429266, 1.092499",\ + "0.040922, 0.090525, 0.180916, 0.429325, 1.092539"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.376755, 0.443500, 0.560063, 0.876818, 1.726409",\ + "0.392417, 0.459162, 0.575725, 0.892480, 1.742071",\ + "0.467424, 0.534169, 0.650732, 0.967487, 1.817078",\ + "0.562603, 0.629351, 0.745928, 1.062681, 1.912261",\ + "1.006927, 1.073706, 1.190415, 1.507149, 2.356620"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073816, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073848, 0.189277, 0.392440, 0.950615, 2.441524"); + } + + } /* end of arc obs_ctrl_o[4]_ast2padmux_o[5]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.264318, 0.295567, 0.348210, 0.490643, 0.869326",\ + "0.278489, 0.309737, 0.362381, 0.504814, 0.883496",\ + "0.355325, 0.386573, 0.439217, 0.581649, 0.960332",\ + "0.450369, 0.481617, 0.534260, 0.676693, 1.055376",\ + "0.893831, 0.925076, 0.977718, 1.120154, 1.498834"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039034, 0.090327, 0.180161, 0.428971, 1.091542",\ + "0.039166, 0.090324, 0.180166, 0.428948, 1.090692"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.373701, 0.440395, 0.556734, 0.873522, 1.723296",\ + "0.385572, 0.452266, 0.568605, 0.885393, 1.735167",\ + "0.464371, 0.531065, 0.647404, 0.964192, 1.813966",\ + "0.559385, 0.626079, 0.742420, 1.059207, 1.908981",\ + "1.002245, 1.068944, 1.185303, 1.502088, 2.351846"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184560, 0.382485, 0.937098, 2.417677",\ + "0.067604, 0.184551, 0.382483, 0.937052, 2.417689"); + } + + } /* end of arc obs_ctrl_o[4]_ast2padmux_o[5]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.337998, 0.404744, 0.521308, 0.838063, 1.687653",\ + "0.353177, 0.419923, 0.536487, 0.853242, 1.702832",\ + "0.412195, 0.478941, 0.595505, 0.912260, 1.761850",\ + "0.508449, 0.575199, 0.691783, 1.008535, 1.858109",\ + "0.997007, 1.063817, 1.180658, 1.497372, 2.346736"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\ + "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073887, 0.189271, 0.392439, 0.950626, 2.441522",\ + "0.075818, 0.189005, 0.392348, 0.951153, 2.441399"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.272032, 0.303198, 0.355817, 0.498312, 0.876955",\ + "0.289891, 0.321056, 0.373675, 0.516170, 0.894813",\ + "0.360955, 0.392121, 0.444739, 0.587235, 0.965878",\ + "0.471378, 0.502542, 0.555160, 0.697656, 1.076298",\ + "1.004117, 1.035227, 1.087829, 1.230366, 1.608983"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\ + "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\ + "0.040752, 0.090633, 0.180666, 0.429269, 1.092497",\ + "0.040771, 0.090633, 0.180871, 0.429315, 1.092502",\ + "0.049622, 0.094130, 0.180871, 0.429356, 1.092666"); + } + + } /* end of arc obs_ctrl_o[5]_ast2padmux_o[5]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.329221, 0.395915, 0.512254, 0.829041, 1.678816",\ + "0.344592, 0.411286, 0.527624, 0.844412, 1.694187",\ + "0.406780, 0.473474, 0.589813, 0.906601, 1.756375",\ + "0.502234, 0.568932, 0.685288, 1.002073, 1.851833",\ + "0.957622, 1.024367, 1.140929, 1.457685, 2.307276"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067607, 0.184553, 0.382483, 0.937060, 2.417687",\ + "0.067439, 0.184458, 0.382464, 0.936568, 2.417820"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.231492, 0.262740, 0.315383, 0.457816, 0.836499",\ + "0.245351, 0.276600, 0.329243, 0.471676, 0.850359",\ + "0.320124, 0.351372, 0.404016, 0.546449, 0.925131",\ + "0.430166, 0.461410, 0.514053, 0.656489, 1.035169",\ + "0.955028, 0.986237, 1.038869, 1.181331, 1.559995"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039041, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039146, 0.090294, 0.180167, 0.428752, 1.090822",\ + "0.040211, 0.090294, 0.180212, 0.428752, 1.091676"); + } + + } /* end of arc obs_ctrl_o[5]_ast2padmux_o[5]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[5]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.176901, 0.208329, 0.261026, 0.403390, 0.781996",\ + "0.196158, 0.227585, 0.280282, 0.422647, 0.801252",\ + "0.273304, 0.304734, 0.357436, 0.499795, 0.878396",\ + "0.397207, 0.428649, 0.481392, 0.623711, 1.002282",\ + "0.961790, 0.996912, 1.049978, 1.192575, 1.571334"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\ + "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\ + "0.040752, 0.090633, 0.180666, 0.429269, 1.092497",\ + "0.040771, 0.090633, 0.180871, 0.429315, 1.092502",\ + "0.049622, 0.094130, 0.180871, 0.429356, 1.092666"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.455825, 0.523049, 0.639668, 0.959430, 1.814404",\ + "0.468963, 0.536187, 0.652807, 0.972569, 1.827542",\ + "0.531289, 0.598514, 0.715133, 1.034896, 1.889869",\ + "0.640154, 0.707387, 0.824004, 1.143775, 1.998757",\ + "1.332501, 1.399969, 1.516508, 1.836528, 2.691724"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\ + "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073887, 0.189271, 0.392439, 0.950626, 2.441522",\ + "0.075818, 0.189005, 0.392348, 0.951153, 2.441399"); + } + + } /* end of arc obs_ctrl_o[5]_ast2padmux_o[5]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[5]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.155833, 0.187247, 0.239896, 0.382308, 0.760949",\ + "0.173482, 0.204896, 0.257545, 0.399957, 0.778598",\ + "0.252964, 0.284381, 0.337040, 0.479441, 0.858074",\ + "0.376196, 0.407628, 0.460337, 0.602689, 0.981285",\ + "0.931678, 0.966257, 1.019278, 1.161831, 1.540560"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039041, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039146, 0.090294, 0.180167, 0.428752, 1.090822",\ + "0.040211, 0.090294, 0.180212, 0.428752, 1.091676"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.452081, 0.519278, 0.635907, 0.955640, 1.810589",\ + "0.461862, 0.529059, 0.645688, 0.965421, 1.820370",\ + "0.527542, 0.594739, 0.711368, 1.031102, 1.886050",\ + "0.636262, 0.703467, 0.820093, 1.139835, 1.994791",\ + "1.324350, 1.391756, 1.508316, 1.828270, 2.683409"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067607, 0.184553, 0.382483, 0.937060, 2.417687",\ + "0.067439, 0.184458, 0.382464, 0.936568, 2.417820"); + } + + } /* end of arc obs_ctrl_o[5]_ast2padmux_o[5]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[6]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.325984, 0.393209, 0.509828, 0.829592, 1.684567",\ + "0.341732, 0.408957, 0.525576, 0.845340, 1.700314",\ + "0.405621, 0.472847, 0.589466, 0.909229, 1.764204",\ + "0.483984, 0.551208, 0.667827, 0.987590, 1.842564",\ + "0.876566, 0.943791, 1.060410, 1.380173, 2.235147"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189281, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189281, 0.392442, 0.950608, 2.441526"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.207560, 0.238992, 0.291700, 0.434053, 0.812650",\ + "0.223441, 0.254873, 0.307582, 0.449934, 0.828531",\ + "0.292964, 0.324396, 0.377105, 0.519457, 0.898054",\ + "0.382304, 0.413736, 0.466444, 0.608797, 0.987394",\ + "0.808201, 0.839636, 0.892354, 1.034697, 1.413287"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\ + "0.040785, 0.090610, 0.180744, 0.429286, 1.092505"); + } + + } /* end of arc obs_ctrl_o[6]_ast2padmux_o[5]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[6]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.298728, 0.365697, 0.482189, 0.801862, 1.656989",\ + "0.312838, 0.379807, 0.496299, 0.815972, 1.671100",\ + "0.378416, 0.445385, 0.561877, 0.881551, 1.736677",\ + "0.456978, 0.523948, 0.640441, 0.960115, 1.815240",\ + "0.852482, 0.919491, 1.036016, 1.355692, 2.210772"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067586, 0.184541, 0.382481, 0.936998, 2.417704"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.185526, 0.216941, 0.269593, 0.412001, 0.790640",\ + "0.197528, 0.228943, 0.281595, 0.424004, 0.802642",\ + "0.270950, 0.302365, 0.355017, 0.497425, 0.876064",\ + "0.360375, 0.391790, 0.444442, 0.586850, 0.965489",\ + "0.786063, 0.817479, 0.870138, 1.012540, 1.391174"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039039, 0.090322, 0.180169, 0.428938, 1.091513"); + } + + } /* end of arc obs_ctrl_o[6]_ast2padmux_o[5]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[6]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.314064, 0.345229, 0.397848, 0.540343, 0.918986",\ + "0.329859, 0.361025, 0.413644, 0.556139, 0.934782",\ + "0.407724, 0.438890, 0.491508, 0.634004, 1.012646",\ + "0.508778, 0.539944, 0.592562, 0.735058, 1.113701",\ + "0.984655, 1.015818, 1.068436, 1.210933, 1.589574"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\ + "0.040785, 0.090610, 0.180744, 0.429286, 1.092505"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.596327, 0.663552, 0.780171, 1.099935, 1.954909",\ + "0.609131, 0.676356, 0.792975, 1.112739, 1.967713",\ + "0.677113, 0.744339, 0.860958, 1.180721, 2.035696",\ + "0.788810, 0.856034, 0.972654, 1.292416, 2.147390",\ + "1.273667, 1.340892, 1.457511, 1.777274, 2.632248"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189281, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189281, 0.392442, 0.950608, 2.441526"); + } + + } /* end of arc obs_ctrl_o[6]_ast2padmux_o[5]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[6]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.262848, 0.294262, 0.346915, 0.489323, 0.867962",\ + "0.276998, 0.308413, 0.361065, 0.503474, 0.882112",\ + "0.356726, 0.388141, 0.440793, 0.583202, 0.961840",\ + "0.457948, 0.489362, 0.542015, 0.684423, 1.063061",\ + "0.929777, 0.961193, 1.013852, 1.156254, 1.534888"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039039, 0.090322, 0.180169, 0.428938, 1.091513"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.437011, 0.503705, 0.620045, 0.936832, 1.786606",\ + "0.446608, 0.513302, 0.629642, 0.946429, 1.796203",\ + "0.517780, 0.584475, 0.700814, 1.017602, 1.867376",\ + "0.629396, 0.696091, 0.812430, 1.129218, 1.978992",\ + "1.131911, 1.198614, 1.314996, 1.631778, 2.481517"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067586, 0.184541, 0.382481, 0.936998, 2.417704"); + } + + } /* end of arc obs_ctrl_o[6]_ast2padmux_o[5]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[7]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.060518, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.315427, 0.346593, 0.399212, 0.541707, 0.920350",\ + "0.342146, 0.373312, 0.425930, 0.568426, 0.947068",\ + "0.410184, 0.441350, 0.493968, 0.636464, 1.015106",\ + "0.512927, 0.544093, 0.596711, 0.739207, 1.117850",\ + "0.999580, 1.030743, 1.083361, 1.225858, 1.604500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.060518, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180697, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180697, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180697, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180732, 0.429283, 1.092497",\ + "0.042004, 0.091469, 0.180867, 0.429340, 1.092504"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.051005, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.597332, 0.664558, 0.781177, 1.100940, 1.955915",\ + "0.618079, 0.685305, 0.801924, 1.121688, 1.976662",\ + "0.683404, 0.750630, 0.867249, 1.187012, 2.041987",\ + "0.797603, 0.864828, 0.981447, 1.301210, 2.156184",\ + "1.375793, 1.443018, 1.559637, 1.879400, 2.734374"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.051005, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189280, 0.392442, 0.950609, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073823, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073819, 0.189281, 0.392442, 0.950607, 2.441526",\ + "0.073817, 0.189281, 0.392442, 0.950607, 2.441526"); + } + + } /* end of arc obs_ctrl_o[7]_ast2padmux_o[5]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[7]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.049671, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.150722, 0.182137, 0.234789, 0.377197, 0.755836",\ + "0.171205, 0.202620, 0.255272, 0.397681, 0.776319",\ + "0.246518, 0.277932, 0.330585, 0.472993, 0.851631",\ + "0.352324, 0.383738, 0.436391, 0.578799, 0.957437",\ + "0.825559, 0.856975, 0.909634, 1.052036, 1.430670"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.049671, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039038, 0.090323, 0.180168, 0.428941, 1.091519"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040467, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.277343, 0.344312, 0.460804, 0.780477, 1.635605",\ + "0.293355, 0.360323, 0.476815, 0.796489, 1.651616",\ + "0.366113, 0.433085, 0.549579, 0.869253, 1.724376",\ + "0.487008, 0.554003, 0.670516, 0.990192, 1.845287",\ + "1.141953, 1.209132, 1.325766, 1.645481, 2.500414"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040467, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067601, 0.184550, 0.382483, 0.937044, 2.417691"); + } + + } /* end of arc obs_ctrl_o[7]_ast2padmux_o[5]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[8]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.690094, 0.756997, 0.873435, 1.193104, 2.048309",\ + "0.708444, 0.775347, 0.891784, 1.211453, 2.066659",\ + "0.778290, 0.845193, 0.961630, 1.281299, 2.136505",\ + "0.871001, 0.937904, 1.054342, 1.374010, 2.229216",\ + "1.316481, 1.383384, 1.499822, 1.819491, 2.674696"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.452134, 0.483566, 0.536274, 0.678627, 1.057224",\ + "0.469561, 0.500993, 0.553701, 0.696054, 1.074651",\ + "0.546928, 0.578360, 0.631068, 0.773421, 1.152018",\ + "0.655300, 0.686732, 0.739440, 0.881793, 1.260390",\ + "1.172032, 1.203463, 1.256172, 1.398524, 1.777121"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837"); + } + + } /* end of arc obs_ctrl_o[8]_ast2padmux_o[5]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[8]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.688464, 0.755356, 0.871784, 1.191452, 2.046671",\ + "0.705080, 0.771971, 0.888399, 1.208067, 2.063287",\ + "0.776660, 0.843551, 0.959979, 1.279647, 2.134867",\ + "0.869371, 0.936263, 1.052691, 1.372359, 2.227578",\ + "1.314852, 1.381744, 1.498172, 1.817840, 2.673059"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\ + "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\ + "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\ + "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\ + "0.073029, 0.188911, 0.391812, 0.949040, 2.441330"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.396265, 0.427678, 0.480325, 0.622739, 1.001381",\ + "0.409612, 0.441025, 0.493672, 0.636085, 1.014728",\ + "0.491059, 0.522472, 0.575119, 0.717533, 1.096175",\ + "0.599541, 0.630954, 0.683601, 0.826015, 1.204657",\ + "1.117451, 1.148864, 1.201511, 1.343925, 1.722567"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\ + "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\ + "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\ + "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\ + "0.039014, 0.090731, 0.180384, 0.429205, 1.091671"); + } + + } /* end of arc obs_ctrl_o[8]_ast2padmux_o[5]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[9]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.701899, 0.768802, 0.885240, 1.204909, 2.060114",\ + "0.720452, 0.787355, 0.903793, 1.223462, 2.078667",\ + "0.793150, 0.860053, 0.976490, 1.296159, 2.151365",\ + "0.888367, 0.955270, 1.071708, 1.391377, 2.246583",\ + "1.341174, 1.408077, 1.524515, 1.844184, 2.699389"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.458526, 0.489958, 0.542666, 0.685019, 1.063616",\ + "0.476069, 0.507500, 0.560208, 0.702561, 1.081158",\ + "0.553398, 0.584829, 0.637537, 0.779890, 1.158487",\ + "0.662868, 0.694299, 0.747008, 0.889361, 1.267957",\ + "1.187448, 1.218880, 1.271588, 1.413941, 1.792538"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837"); + } + + } /* end of arc obs_ctrl_o[9]_ast2padmux_o[5]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[9]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.700268, 0.767160, 0.883588, 1.203256, 2.058475",\ + "0.717089, 0.783981, 0.900409, 1.220077, 2.075296",\ + "0.791519, 0.858410, 0.974838, 1.294506, 2.149726",\ + "0.886736, 0.953628, 1.070056, 1.389724, 2.244943",\ + "1.339543, 1.406435, 1.522863, 1.842531, 2.697751"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\ + "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\ + "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\ + "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\ + "0.073029, 0.188911, 0.391812, 0.949040, 2.441330"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.402716, 0.434129, 0.486776, 0.629190, 1.007832",\ + "0.416173, 0.447586, 0.500233, 0.642646, 1.021289",\ + "0.497588, 0.529001, 0.581648, 0.724061, 1.102704",\ + "0.607156, 0.638569, 0.691216, 0.833630, 1.212272",\ + "1.132876, 1.164289, 1.216936, 1.359350, 1.737992"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\ + "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\ + "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\ + "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\ + "0.039014, 0.090731, 0.180384, 0.429205, 1.091671"); + } + + } /* end of arc obs_ctrl_o[9]_ast2padmux_o[5]_una_min*/ + + timing () { + related_pin : "otm_obs_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.123879, 0.190820, 0.307288, 0.626960, 1.482121",\ + "0.210891, 0.277978, 0.394567, 0.714249, 1.569235",\ + "0.301781, 0.369068, 0.485667, 0.805496, 1.660526",\ + "0.453978, 0.523120, 0.640034, 0.960158, 1.815427",\ + "0.695902, 0.774527, 0.893732, 1.214148, 2.069560"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073065, 0.188997, 0.391936, 0.949305, 2.441374",\ + "0.073175, 0.189249, 0.392304, 0.950092, 2.441498",\ + "0.074330, 0.189249, 0.392418, 0.950747, 2.441498",\ + "0.079436, 0.191164, 0.392505, 0.951076, 2.441498",\ + "0.098084, 0.204137, 0.393542, 0.951076, 2.441498"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.114293, 0.145721, 0.198417, 0.340782, 0.719388",\ + "0.205394, 0.236828, 0.289545, 0.431889, 0.810480",\ + "0.309904, 0.342065, 0.394885, 0.537244, 0.915841",\ + "0.501618, 0.536979, 0.590065, 0.732680, 1.111452",\ + "0.825607, 0.870622, 0.930343, 1.075147, 1.454209"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039117, 0.090634, 0.180632, 0.429261, 1.091005",\ + "0.039161, 0.090634, 0.180739, 0.429285, 1.091005",\ + "0.041267, 0.091212, 0.180891, 0.429338, 1.091005",\ + "0.050293, 0.094364, 0.180891, 0.429357, 1.092061",\ + "0.068556, 0.114740, 0.192215, 0.429716, 1.093122"); + } + + } /* end of arc otm_obs_i[5]_ast2padmux_o[5]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "otm_obs_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.120559, 0.187489, 0.303948, 0.623619, 1.478793",\ + "0.205712, 0.272774, 0.389342, 0.709022, 1.564038",\ + "0.292652, 0.359907, 0.476516, 0.796311, 1.651312",\ + "0.437434, 0.505450, 0.622092, 0.942182, 1.797434",\ + "0.662107, 0.738115, 0.856688, 1.177023, 2.032395"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073057, 0.188977, 0.391908, 0.949245, 2.441364",\ + "0.073156, 0.189206, 0.392241, 0.949956, 2.441378",\ + "0.074065, 0.189247, 0.392382, 0.950255, 2.441378",\ + "0.077223, 0.189624, 0.392382, 0.950255, 2.441378",\ + "0.092938, 0.200557, 0.393255, 0.950255, 2.441468"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.094368, 0.125782, 0.178430, 0.320842, 0.699483",\ + "0.188259, 0.219683, 0.272369, 0.414744, 0.793358",\ + "0.291365, 0.323244, 0.376040, 0.518376, 0.896959",\ + "0.474009, 0.509208, 0.562280, 0.704883, 1.083646",\ + "0.777508, 0.822171, 0.881623, 1.026340, 1.405392"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039018, 0.090654, 0.180392, 0.429207, 1.090346",\ + "0.039096, 0.090654, 0.180581, 0.429249, 1.090346",\ + "0.040472, 0.090934, 0.180608, 0.429337, 1.090346",\ + "0.049836, 0.094205, 0.180608, 0.429356, 1.091981",\ + "0.067933, 0.113945, 0.191732, 0.429701, 1.093101"); + } + + } /* end of arc otm_obs_i[5]_ast2padmux_o[5]_una_min*/ + + timing () { + related_pin : "otp_obs_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.122660, 0.189370, 0.305783, 0.622560, 1.472274",\ + "0.209824, 0.276743, 0.394059, 0.710704, 1.559679",\ + "0.301920, 0.369023, 0.486415, 0.804486, 1.652417",\ + "0.455547, 0.524976, 0.642287, 0.962376, 1.809444",\ + "0.699992, 0.780922, 0.900058, 1.218756, 2.067549"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067561, 0.184527, 0.382478, 0.936925, 2.417724",\ + "0.067561, 0.184527, 0.382478, 0.936925, 2.418306",\ + "0.068683, 0.184527, 0.382544, 0.936925, 2.418306",\ + "0.075540, 0.185756, 0.383113, 0.940410, 2.418306",\ + "0.094401, 0.199857, 0.384817, 0.940410, 2.426093"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.114764, 0.145947, 0.198571, 0.341053, 0.719705",\ + "0.205629, 0.236785, 0.289401, 0.431904, 0.810542",\ + "0.310076, 0.342571, 0.395201, 0.537686, 0.916183",\ + "0.500896, 0.538360, 0.591093, 0.733386, 1.111456",\ + "0.820213, 0.870292, 0.933027, 1.077593, 1.455130"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040532, 0.090273, 0.180246, 0.428609, 1.092443",\ + "0.040870, 0.090273, 0.180281, 0.428609, 1.092443",\ + "0.045400, 0.092351, 0.180508, 0.428609, 1.092443",\ + "0.059558, 0.100025, 0.181106, 0.428872, 1.092443",\ + "0.087354, 0.133744, 0.204884, 0.431205, 1.092443"); + } + + } /* end of arc otp_obs_i[5]_ast2padmux_o[5]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "otp_obs_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.119334, 0.186028, 0.302368, 0.619155, 1.468929",\ + "0.204833, 0.271716, 0.388876, 0.705544, 1.554647",\ + "0.293319, 0.360401, 0.477846, 0.795625, 1.643707",\ + "0.440314, 0.508488, 0.625608, 0.945855, 1.792734",\ + "0.667813, 0.745674, 0.864272, 1.183300, 2.031636"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.183691, 0.382409, 0.935142, 2.413233",\ + "0.067620, 0.183691, 0.382409, 0.935142, 2.413233",\ + "0.068262, 0.183691, 0.382508, 0.936031, 2.413233",\ + "0.073482, 0.184226, 0.382946, 0.939859, 2.413233",\ + "0.089380, 0.196045, 0.384240, 0.939859, 2.423100"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.094521, 0.125776, 0.178422, 0.320849, 0.699535",\ + "0.188239, 0.219444, 0.272075, 0.414540, 0.793202",\ + "0.291550, 0.323577, 0.376197, 0.518700, 0.897237",\ + "0.473699, 0.510899, 0.563627, 0.705929, 1.084022",\ + "0.773733, 0.823401, 0.885774, 1.030256, 1.407808"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039633, 0.090291, 0.180152, 0.428296, 1.092222",\ + "0.040262, 0.090291, 0.180217, 0.428296, 1.092377",\ + "0.044064, 0.091627, 0.180452, 0.428296, 1.092425",\ + "0.058805, 0.099616, 0.181075, 0.428844, 1.092425",\ + "0.086478, 0.132591, 0.204027, 0.431125, 1.092425"); + } + + } /* end of arc otp_obs_i[5]_ast2padmux_o[5]_una_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380000.312500, 380000.312500, 380000.343750, 380000.406250, 380000.593750",\ + "380000.406250, 380000.406250, 380000.437500, 380000.500000, 380000.687500",\ + "380000.500000, 380000.500000, 380000.531250, 380000.593750, 380000.781250",\ + "380000.656250, 380000.656250, 380000.687500, 380000.750000, 380000.937500",\ + "380000.906250, 380000.906250, 380000.937500, 380001.000000, 380001.187500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380001.781250, 380001.843750, 380001.968750, 380002.281250, 380003.156250",\ + "380001.875000, 380001.937500, 380002.062500, 380002.375000, 380003.250000",\ + "380002.000000, 380002.062500, 380002.187500, 380002.500000, 380003.375000",\ + "380002.187500, 380002.250000, 380002.375000, 380002.687500, 380003.562500",\ + "380002.500000, 380002.562500, 380002.687500, 380003.000000, 380003.875000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526"); + } + + } /* end of arc padmux2ast_i[4]_ast2padmux_o[5]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380000.312500, 380000.312500, 380000.343750, 380000.406250, 380000.593750",\ + "380000.406250, 380000.406250, 380000.437500, 380000.500000, 380000.687500",\ + "380000.468750, 380000.468750, 380000.500000, 380000.562500, 380000.750000",\ + "380000.625000, 380000.625000, 380000.656250, 380000.718750, 380000.906250",\ + "380000.843750, 380000.843750, 380000.875000, 380000.937500, 380001.125000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380001.781250, 380001.812500, 380001.906250, 380002.187500, 380002.875000",\ + "380001.875000, 380001.906250, 380002.000000, 380002.281250, 380002.968750",\ + "380001.968750, 380002.000000, 380002.093750, 380002.375000, 380003.062500",\ + "380002.156250, 380002.187500, 380002.281250, 380002.562500, 380003.250000",\ + "380002.406250, 380002.437500, 380002.531250, 380002.812500, 380003.500000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169"); + } + + } /* end of arc padmux2ast_i[4]_ast2padmux_o[5]_inv_min*/ + +} /* end of pin ast2padmux_o[5] */ + +pin("ast2padmux_o[4]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.028584 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : ast2padmux_o[4]; + timing () { + related_pin : "clk_ast_rng_i" ; + related_output_pin : "rng_b_o[3]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.256137, 0.526101, 0.791807, 1.233240, 2.116106",\ + "0.323038, 0.593004, 0.858715, 1.300159, 2.183047",\ + "0.439474, 0.709441, 0.975156, 1.416609, 2.299516",\ + "0.759143, 1.029110, 1.294825, 1.736279, 2.619187",\ + "1.614351, 1.884316, 2.150025, 2.591466, 3.474348",\ + "0.314712, 0.584612, 0.850579, 1.290946, 2.172213",\ + "0.381613, 0.651515, 0.917487, 1.357865, 2.239154",\ + "0.498049, 0.767952, 1.033928, 1.474316, 2.355623",\ + "0.817718, 1.087621, 1.353598, 1.793986, 2.675294",\ + "1.672926, 1.942827, 2.208797, 2.649173, 3.530455",\ + "0.459188, 0.730385, 0.994470, 1.434701, 2.315946",\ + "0.526089, 0.797288, 1.061378, 1.501621, 2.382887",\ + "0.642525, 0.913725, 1.177819, 1.618071, 2.499355",\ + "0.962194, 1.233394, 1.497489, 1.937741, 2.819027",\ + "1.817402, 2.088600, 2.352689, 2.792928, 3.674187",\ + "0.495112, 0.768133, 1.031389, 1.471493, 2.352504",\ + "0.562013, 0.835036, 1.098297, 1.538412, 2.419445",\ + "0.678449, 0.951473, 1.214738, 1.654862, 2.535913",\ + "0.998118, 1.271142, 1.534407, 1.974532, 2.855585",\ + "1.853326, 2.126348, 2.389607, 2.829719, 3.710746",\ + "0.823805, 1.131731, 1.382980, 1.820732, 2.697960",\ + "0.890706, 1.198635, 1.449888, 1.887651, 2.764901",\ + "1.007142, 1.315072, 1.566330, 2.004102, 2.881370",\ + "1.326811, 1.634741, 1.885999, 2.323771, 3.201041",\ + "2.182019, 2.489947, 2.741199, 3.178958, 4.056201"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.073036, 0.073037, 0.073041, 0.073049, 0.073065",\ + "0.188928, 0.188931, 0.188940, 0.188959, 0.188997",\ + "0.391836, 0.391840, 0.391853, 0.391881, 0.391936",\ + "0.949092, 0.949099, 0.949128, 0.949187, 0.949305",\ + "2.441339, 2.441340, 2.441345, 2.441355, 2.441374",\ + "0.073036, 0.073037, 0.073041, 0.073049, 0.073065",\ + "0.188928, 0.188931, 0.188940, 0.188959, 0.188997",\ + "0.391836, 0.391840, 0.391853, 0.391881, 0.391936",\ + "0.949092, 0.949099, 0.949128, 0.949187, 0.949305",\ + "2.441339, 2.441340, 2.441345, 2.441355, 2.441374",\ + "0.073036, 0.073037, 0.073041, 0.073049, 0.073065",\ + "0.188928, 0.188931, 0.188940, 0.188959, 0.188997",\ + "0.391836, 0.391840, 0.391853, 0.391881, 0.391936",\ + "0.949092, 0.949100, 0.949128, 0.949187, 0.949305",\ + "2.441339, 2.441340, 2.441345, 2.441355, 2.441374",\ + "0.073036, 0.073037, 0.073041, 0.073049, 0.073065",\ + "0.188928, 0.188931, 0.188940, 0.188959, 0.188997",\ + "0.391836, 0.391840, 0.391853, 0.391881, 0.391936",\ + "0.949092, 0.949100, 0.949128, 0.949187, 0.949305",\ + "2.441339, 2.441340, 2.441345, 2.441355, 2.441374",\ + "0.073036, 0.073037, 0.073041, 0.073049, 0.073065",\ + "0.188928, 0.188932, 0.188940, 0.188959, 0.188997",\ + "0.391836, 0.391842, 0.391854, 0.391881, 0.391936",\ + "0.949092, 0.949103, 0.949129, 0.949187, 0.949305",\ + "2.441339, 2.441340, 2.441345, 2.441355, 2.441374"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.300809, 0.483950, 0.676379, 0.983182, 1.575800",\ + "0.332240, 0.515381, 0.707810, 1.014614, 1.607232",\ + "0.384949, 0.568090, 0.760519, 1.067323, 1.659944",\ + "0.527301, 0.710443, 0.902872, 1.209675, 1.802294",\ + "0.905898, 1.089039, 1.281469, 1.588271, 2.180888",\ + "0.360720, 0.543848, 0.736331, 1.042962, 1.635417",\ + "0.392152, 0.575280, 0.767762, 1.074394, 1.666849",\ + "0.444860, 0.627988, 0.820471, 1.127103, 1.719561",\ + "0.587213, 0.770341, 0.962824, 1.269455, 1.861911",\ + "0.965810, 1.148938, 1.341421, 1.648051, 2.240505",\ + "0.493463, 0.676099, 0.868214, 1.174820, 1.767224",\ + "0.524895, 0.707531, 0.899645, 1.206252, 1.798657",\ + "0.577603, 0.760239, 0.952354, 1.258961, 1.851368",\ + "0.719956, 0.902592, 1.094707, 1.401313, 1.993718",\ + "1.098553, 1.281189, 1.473303, 1.779909, 2.372313",\ + "0.526601, 0.709226, 0.901339, 1.207772, 1.799833",\ + "0.558032, 0.740658, 0.932770, 1.239204, 1.831265",\ + "0.610741, 0.793366, 0.985478, 1.291914, 1.883977",\ + "0.753093, 0.935719, 1.127831, 1.434265, 2.026326",\ + "1.131690, 1.314316, 1.506428, 1.812862, 2.404921",\ + "0.827685, 1.014449, 1.204974, 1.510788, 2.101678",\ + "0.859116, 1.045881, 1.236405, 1.542220, 2.133111",\ + "0.911824, 1.098589, 1.289114, 1.594929, 2.185822",\ + "1.054177, 1.240942, 1.431466, 1.737281, 2.328172",\ + "1.432774, 1.619539, 1.810063, 2.115877, 2.706767"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.039143, 0.039143, 0.039143, 0.039145, 0.039150",\ + "0.090610, 0.090610, 0.090610, 0.090608, 0.090604",\ + "0.180695, 0.180695, 0.180695, 0.180700, 0.180710",\ + "0.429275, 0.429275, 0.429275, 0.429276, 0.429279",\ + "1.090837, 1.090837, 1.090837, 1.090825, 1.090796",\ + "0.039143, 0.039143, 0.039143, 0.039145, 0.039150",\ + "0.090610, 0.090610, 0.090610, 0.090608, 0.090604",\ + "0.180695, 0.180695, 0.180695, 0.180700, 0.180710",\ + "0.429275, 0.429275, 0.429275, 0.429276, 0.429279",\ + "1.090837, 1.090837, 1.090837, 1.090825, 1.090796",\ + "0.039143, 0.039143, 0.039143, 0.039145, 0.039150",\ + "0.090610, 0.090610, 0.090610, 0.090608, 0.090604",\ + "0.180695, 0.180695, 0.180695, 0.180700, 0.180710",\ + "0.429275, 0.429275, 0.429275, 0.429276, 0.429279",\ + "1.090837, 1.090837, 1.090837, 1.090825, 1.090796",\ + "0.039143, 0.039143, 0.039143, 0.039145, 0.039150",\ + "0.090610, 0.090610, 0.090610, 0.090608, 0.090604",\ + "0.180695, 0.180695, 0.180695, 0.180700, 0.180710",\ + "0.429275, 0.429275, 0.429275, 0.429276, 0.429279",\ + "1.090837, 1.090837, 1.090837, 1.090825, 1.090796",\ + "0.039143, 0.039143, 0.039143, 0.039145, 0.039150",\ + "0.090610, 0.090610, 0.090610, 0.090608, 0.090604",\ + "0.180695, 0.180695, 0.180695, 0.180700, 0.180710",\ + "0.429275, 0.429275, 0.429275, 0.429276, 0.429279",\ + "1.090837, 1.090837, 1.090837, 1.090825, 1.090796"); + } + + } /* end of arc clk_ast_rng_i_ast2padmux_o[4]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_rng_i" ; + related_output_pin : "rng_b_o[3]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.252605, 0.520760, 0.784538, 1.222585, 2.097608",\ + "0.319496, 0.587651, 0.851435, 1.289491, 2.164534",\ + "0.435923, 0.704079, 0.967867, 1.405931, 2.280990",\ + "0.755591, 1.023747, 1.287535, 1.725600, 2.600661",\ + "1.610811, 1.878966, 2.142749, 2.580802, 3.455839",\ + "0.311166, 0.579267, 0.843303, 1.280291, 2.153714",\ + "0.378057, 0.646158, 0.910200, 1.347198, 2.220641",\ + "0.494484, 0.762586, 1.026632, 1.463638, 2.337097",\ + "0.814152, 1.082254, 1.346300, 1.783307, 2.656768",\ + "1.669372, 1.937473, 2.201514, 2.638509, 3.511946",\ + "0.455502, 0.725014, 0.987191, 1.424095, 2.297447",\ + "0.522393, 0.791906, 1.054087, 1.491001, 2.364373",\ + "0.638820, 0.908334, 1.170519, 1.607441, 2.480830",\ + "0.958488, 1.228002, 1.490188, 1.927111, 2.800500",\ + "1.813708, 2.083220, 2.345402, 2.782313, 3.655679",\ + "0.491381, 0.762750, 1.024109, 1.460966, 2.334005",\ + "0.558271, 0.829641, 1.091006, 1.527872, 2.400932",\ + "0.674699, 0.946069, 1.207438, 1.644312, 2.517388",\ + "0.994367, 1.265738, 1.527106, 1.963982, 2.837059",\ + "1.849586, 2.120956, 2.382320, 2.819183, 3.692237",\ + "0.819578, 1.126098, 1.375669, 1.810266, 2.679461",\ + "0.886469, 1.192990, 1.442565, 1.877173, 2.746387",\ + "1.002896, 1.309418, 1.558997, 1.993613, 2.862844",\ + "1.322564, 1.629086, 1.878666, 2.313282, 3.182515",\ + "2.177784, 2.484305, 2.733880, 3.168484, 4.037693"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.073031, 0.073031, 0.073033, 0.073040, 0.073054",\ + "0.188915, 0.188915, 0.188919, 0.188937, 0.188971",\ + "0.391815, 0.391816, 0.391824, 0.391849, 0.391899",\ + "0.949014, 0.949028, 0.949065, 0.949118, 0.949226",\ + "2.441330, 2.441330, 2.441334, 2.441343, 2.441361",\ + "0.073031, 0.073031, 0.073033, 0.073040, 0.073054",\ + "0.188915, 0.188915, 0.188919, 0.188937, 0.188971",\ + "0.391815, 0.391816, 0.391824, 0.391849, 0.391899",\ + "0.949014, 0.949028, 0.949065, 0.949118, 0.949226",\ + "2.441330, 2.441330, 2.441334, 2.441343, 2.441361",\ + "0.073031, 0.073031, 0.073033, 0.073040, 0.073054",\ + "0.188915, 0.188915, 0.188920, 0.188937, 0.188971",\ + "0.391815, 0.391816, 0.391824, 0.391849, 0.391899",\ + "0.949014, 0.949029, 0.949065, 0.949118, 0.949226",\ + "2.441330, 2.441330, 2.441334, 2.441343, 2.441361",\ + "0.073031, 0.073031, 0.073033, 0.073040, 0.073054",\ + "0.188915, 0.188915, 0.188920, 0.188937, 0.188971",\ + "0.391815, 0.391816, 0.391824, 0.391849, 0.391899",\ + "0.949014, 0.949029, 0.949065, 0.949119, 0.949226",\ + "2.441330, 2.441330, 2.441334, 2.441343, 2.441361",\ + "0.073031, 0.073031, 0.073033, 0.073040, 0.073054",\ + "0.188915, 0.188915, 0.188920, 0.188937, 0.188971",\ + "0.391816, 0.391816, 0.391824, 0.391849, 0.391899",\ + "0.949014, 0.949034, 0.949065, 0.949119, 0.949226",\ + "2.441330, 2.441331, 2.441334, 2.441343, 2.441361"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.262934, 0.448489, 0.641595, 0.948297, 1.539521",\ + "0.294346, 0.479902, 0.673008, 0.979711, 1.570936",\ + "0.346992, 0.532548, 0.725656, 1.032361, 1.623593",\ + "0.489407, 0.674962, 0.868069, 1.174772, 1.765997",\ + "0.868050, 1.053605, 1.246711, 1.553412, 2.144632",\ + "0.322845, 0.508317, 0.701440, 1.008066, 1.599138",\ + "0.354258, 0.539729, 0.732853, 1.039480, 1.630553",\ + "0.406904, 0.592376, 0.785500, 1.092130, 1.683210",\ + "0.549319, 0.734790, 0.927914, 1.234540, 1.825614",\ + "0.927962, 1.113433, 1.306556, 1.613180, 2.204249",\ + "0.455621, 0.640568, 0.833323, 1.139923, 1.730945",\ + "0.487034, 0.671981, 0.864736, 1.171337, 1.762361",\ + "0.539679, 0.724627, 0.917383, 1.223988, 1.815017",\ + "0.682094, 0.867041, 1.059797, 1.366398, 1.957422",\ + "1.060737, 1.245684, 1.438439, 1.745038, 2.336057",\ + "0.488779, 0.673866, 0.866553, 1.173003, 1.763806",\ + "0.520192, 0.705279, 0.897966, 1.204417, 1.795222",\ + "0.572837, 0.757925, 0.950613, 1.257067, 1.847878",\ + "0.715252, 0.900339, 1.093027, 1.399478, 1.990283",\ + "1.093896, 1.278982, 1.471669, 1.778118, 2.368918",\ + "0.790171, 0.979313, 1.170216, 1.476207, 2.066113",\ + "0.821584, 1.010726, 1.201629, 1.507621, 2.097529",\ + "0.874230, 1.063372, 1.254276, 1.560271, 2.150186",\ + "1.016645, 1.205787, 1.396689, 1.702681, 2.292590",\ + "1.395288, 1.584430, 1.775331, 2.081321, 2.671225"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.039012, 0.039013, 0.039015, 0.039021, 0.039035",\ + "0.090733, 0.090732, 0.090730, 0.090724, 0.090712",\ + "0.180377, 0.180379, 0.180385, 0.180400, 0.180432",\ + "0.429204, 0.429204, 0.429205, 0.429209, 0.429216",\ + "1.091688, 1.091683, 1.091668, 1.091627, 1.091540",\ + "0.039012, 0.039013, 0.039015, 0.039021, 0.039035",\ + "0.090733, 0.090732, 0.090730, 0.090724, 0.090712",\ + "0.180377, 0.180379, 0.180385, 0.180400, 0.180432",\ + "0.429204, 0.429204, 0.429205, 0.429209, 0.429216",\ + "1.091688, 1.091683, 1.091668, 1.091627, 1.091540",\ + "0.039012, 0.039013, 0.039015, 0.039021, 0.039035",\ + "0.090733, 0.090732, 0.090730, 0.090724, 0.090712",\ + "0.180377, 0.180379, 0.180385, 0.180400, 0.180432",\ + "0.429204, 0.429204, 0.429205, 0.429209, 0.429216",\ + "1.091688, 1.091683, 1.091668, 1.091627, 1.091540",\ + "0.039012, 0.039013, 0.039015, 0.039021, 0.039035",\ + "0.090733, 0.090732, 0.090730, 0.090724, 0.090712",\ + "0.180377, 0.180379, 0.180385, 0.180400, 0.180433",\ + "0.429204, 0.429204, 0.429205, 0.429209, 0.429216",\ + "1.091688, 1.091683, 1.091668, 1.091627, 1.091540",\ + "0.039012, 0.039013, 0.039015, 0.039021, 0.039035",\ + "0.090733, 0.090732, 0.090730, 0.090724, 0.090712",\ + "0.180378, 0.180379, 0.180385, 0.180400, 0.180433",\ + "0.429204, 0.429204, 0.429205, 0.429209, 0.429216",\ + "1.091687, 1.091683, 1.091668, 1.091627, 1.091540"); + } + + } /* end of arc clk_ast_rng_i_ast2padmux_o[4]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "970002.000000, 970002.062500, 970002.187500, 970002.500000, 970003.375000",\ + "970002.125000, 970002.187500, 970002.312500, 970002.625000, 970003.500000",\ + "970002.250000, 970002.312500, 970002.437500, 970002.750000, 970003.625000",\ + "970002.250000, 970002.312500, 970002.437500, 970002.750000, 970003.625000",\ + "970002.625000, 970002.687500, 970002.812500, 970003.125000, 970004.000000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189354, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189354, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189365, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189385, 0.392560, 0.950608, 2.441526",\ + "0.073824, 0.189425, 0.393252, 0.950608, 2.441526"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "970001.187500, 970001.187500, 970001.250000, 970001.437500, 970001.812500",\ + "970001.312500, 970001.312500, 970001.375000, 970001.562500, 970001.937500",\ + "970001.312500, 970001.312500, 970001.375000, 970001.562500, 970001.937500",\ + "970001.437500, 970001.437500, 970001.500000, 970001.687500, 970002.062500",\ + "970001.687500, 970001.687500, 970001.750000, 970001.937500, 970002.312500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497"); + } + + } /* end of arc clk_ast_tlul_i_ast2padmux_o[4]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.118063, 0.173160, 0.267375, 0.527316, 1.216798",\ + "0.205470, 0.260567, 0.354781, 0.614720, 1.304204",\ + "0.286205, 0.341346, 0.435579, 0.695608, 1.384949",\ + "0.343571, 0.398793, 0.493060, 0.753254, 1.442331",\ + "0.643636, 0.699058, 0.793671, 1.054205, 1.742813"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.055140, 0.149920, 0.315966, 0.770671, 1.992169",\ + "0.055140, 0.149920, 0.315966, 0.770671, 1.992169",\ + "0.055064, 0.149920, 0.315966, 0.770616, 1.992169",\ + "0.054924, 0.149920, 0.315966, 0.770514, 1.992169",\ + "0.054820, 0.149920, 0.315966, 0.770514, 1.988361"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.068977, 0.083624, 0.108789, 0.177707, 0.362145",\ + "0.157440, 0.172093, 0.197279, 0.266195, 0.450612",\ + "0.246166, 0.261189, 0.286407, 0.355291, 0.539679",\ + "0.308361, 0.324424, 0.349591, 0.418444, 0.602842",\ + "0.630702, 0.654723, 0.683267, 0.752219, 0.936438"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.015416, 0.041075, 0.085652, 0.207740, 0.535967",\ + "0.015763, 0.041089, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967"); + } + + } /* end of arc clk_ast_tlul_i_ast2padmux_o[4]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.231764, 0.298665, 0.415101, 0.734770, 1.589978",\ + "0.323073, 0.389976, 0.506413, 0.826082, 1.681288",\ + "0.433906, 0.500813, 0.617254, 0.936923, 1.792124",\ + "0.514021, 0.580932, 0.697376, 1.017045, 1.872241",\ + "0.917338, 0.984292, 1.100771, 1.420444, 2.275589"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073036, 0.188928, 0.391836, 0.949092, 2.441339",\ + "0.073037, 0.188930, 0.391839, 0.949098, 2.441340",\ + "0.073040, 0.188938, 0.391851, 0.949124, 2.441344",\ + "0.073043, 0.188945, 0.391861, 0.949145, 2.441347",\ + "0.073075, 0.189019, 0.391969, 0.949375, 2.441386"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.336061, 0.367493, 0.420201, 0.562554, 0.941151",\ + "0.422827, 0.454258, 0.506967, 0.649320, 1.027916",\ + "0.529568, 0.561000, 0.613708, 0.756061, 1.134658",\ + "0.742022, 0.773454, 0.826162, 0.968515, 1.347112",\ + "1.127927, 1.159358, 1.212067, 1.354419, 1.733016"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039144, 0.090610, 0.180696, 0.429275, 1.090836"); + } + + } /* end of arc clk_ast_tlul_i_ast2padmux_o[4]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.221966, 0.288856, 0.405284, 0.724952, 1.580171",\ + "0.311631, 0.378522, 0.494949, 0.814617, 1.669837",\ + "0.414337, 0.481231, 0.597661, 0.917329, 1.772546",\ + "0.488653, 0.555550, 0.671983, 0.991651, 1.846864",\ + "0.868804, 0.935731, 1.052188, 1.371858, 2.227036"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073032, 0.188915, 0.391815, 0.949015, 2.441330",\ + "0.073032, 0.188915, 0.391815, 0.949022, 2.441330",\ + "0.073032, 0.188916, 0.391818, 0.949053, 2.441332",\ + "0.073033, 0.188921, 0.391826, 0.949069, 2.441335",\ + "0.073055, 0.188972, 0.391900, 0.949227, 2.441361"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.247879, 0.279292, 0.331938, 0.474353, 0.852996",\ + "0.337796, 0.369209, 0.421855, 0.564270, 0.942913",\ + "0.451084, 0.482497, 0.535144, 0.677558, 1.056200",\ + "0.662499, 0.693912, 0.746561, 0.888973, 1.267614",\ + "1.032523, 1.063938, 1.116591, 1.258999, 1.637636"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039012, 0.090733, 0.180379, 0.429204, 1.091684",\ + "0.039012, 0.090733, 0.180379, 0.429204, 1.091684",\ + "0.039014, 0.090731, 0.180383, 0.429205, 1.091673",\ + "0.039019, 0.090727, 0.180394, 0.429207, 1.091643",\ + "0.039029, 0.090717, 0.180418, 0.429213, 1.091579"); + } + + } /* end of arc clk_ast_tlul_i_ast2padmux_o[4]_una_min*/ + + timing () { + related_pin : "fla_obs_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.111862, 0.178517, 0.294685, 0.611498, 1.461412",\ + "0.196887, 0.263820, 0.381200, 0.697836, 1.546758",\ + "0.280874, 0.348002, 0.465333, 0.783744, 1.631498",\ + "0.419192, 0.490016, 0.607541, 0.927454, 1.774732",\ + "0.629434, 0.713469, 0.835221, 1.155234, 2.004311"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067759, 0.184639, 0.382501, 0.937507, 2.417566",\ + "0.067759, 0.184639, 0.382501, 0.937507, 2.418347",\ + "0.069174, 0.184639, 0.382586, 0.937507, 2.418347",\ + "0.077831, 0.187460, 0.383300, 0.940319, 2.418347",\ + "0.099054, 0.205738, 0.390315, 0.940320, 2.425200"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.103322, 0.134506, 0.187130, 0.329612, 0.708263",\ + "0.188196, 0.219801, 0.272413, 0.414932, 0.793505",\ + "0.281500, 0.317246, 0.369943, 0.512302, 0.890520",\ + "0.433568, 0.478875, 0.537406, 0.680993, 1.058708",\ + "0.668936, 0.733428, 0.809479, 0.962224, 1.340585"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040521, 0.090274, 0.180244, 0.428614, 1.092440",\ + "0.042863, 0.090977, 0.180401, 0.428614, 1.092696",\ + "0.054661, 0.097371, 0.180899, 0.428690, 1.092793",\ + "0.077190, 0.120374, 0.194930, 0.430280, 1.092793",\ + "0.118581, 0.174509, 0.240947, 0.445113, 1.092793"); + } + + } /* end of arc fla_obs_i[4]_ast2padmux_o[4]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "fla_obs_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.110629, 0.177262, 0.293339, 0.610165, 1.460154",\ + "0.194795, 0.261696, 0.378936, 0.695592, 1.544629",\ + "0.275980, 0.343081, 0.460479, 0.778514, 1.626463",\ + "0.408884, 0.478137, 0.595421, 0.915532, 1.762573",\ + "0.610985, 0.691263, 0.810230, 1.128954, 1.977655"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067834, 0.183634, 0.382402, 0.934951, 2.414331",\ + "0.067834, 0.183634, 0.382402, 0.934951, 2.414331",\ + "0.068631, 0.183634, 0.382540, 0.936478, 2.414331",\ + "0.075251, 0.185541, 0.383090, 0.939701, 2.414331",\ + "0.093347, 0.198994, 0.384563, 0.939701, 2.425563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.077370, 0.108647, 0.161299, 0.303710, 0.682406",\ + "0.166391, 0.197521, 0.250129, 0.392651, 0.771277",\ + "0.253394, 0.288299, 0.340979, 0.483371, 0.861661",\ + "0.395347, 0.439383, 0.496795, 0.640121, 1.017884",\ + "0.615736, 0.679130, 0.754042, 0.905113, 1.283136"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039363, 0.090228, 0.180124, 0.428312, 1.092155",\ + "0.041196, 0.090228, 0.180315, 0.428312, 1.092511",\ + "0.052267, 0.096073, 0.180798, 0.428601, 1.092511",\ + "0.074482, 0.116813, 0.192279, 0.430033, 1.092511",\ + "0.116096, 0.171326, 0.236992, 0.441817, 1.092511"); + } + + } /* end of arc fla_obs_i[4]_ast2padmux_o[4]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[10]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.443642, 0.510546, 0.626985, 0.946654, 1.801858",\ + "0.465905, 0.532810, 0.649248, 0.968917, 1.824121",\ + "0.521995, 0.588899, 0.705338, 1.025007, 1.880211",\ + "0.620162, 0.687066, 0.803505, 1.123173, 1.978378",\ + "1.134534, 1.201443, 1.317885, 1.637554, 2.492753"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\ + "0.073042, 0.188941, 0.391856, 0.949133, 2.441345"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.490585, 0.522017, 0.574725, 0.717078, 1.095675",\ + "0.512119, 0.543551, 0.596259, 0.738612, 1.117209",\ + "0.579334, 0.610765, 0.663474, 0.805826, 1.184423",\ + "0.689604, 0.721035, 0.773743, 0.916096, 1.294693",\ + "1.246693, 1.278125, 1.330833, 1.473186, 1.851783"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837"); + } + + } /* end of arc obs_ctrl_o[10]_ast2padmux_o[4]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[10]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.412827, 0.479717, 0.596144, 0.915812, 1.771032",\ + "0.433604, 0.500495, 0.616922, 0.936590, 1.791810",\ + "0.491196, 0.558086, 0.674513, 0.994181, 1.849401",\ + "0.589141, 0.656031, 0.772458, 1.092126, 1.947346",\ + "1.077990, 1.144880, 1.261307, 1.580975, 2.436195"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.392866, 0.424278, 0.476924, 0.619339, 0.997982",\ + "0.410271, 0.441684, 0.494330, 0.636744, 1.015388",\ + "0.482841, 0.514253, 0.566899, 0.709314, 1.087957",\ + "0.595475, 0.626888, 0.679534, 0.821949, 1.200592",\ + "1.122503, 1.153916, 1.206562, 1.348976, 1.727620"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091686"); + } + + } /* end of arc obs_ctrl_o[10]_ast2padmux_o[4]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[10]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.437382, 0.468814, 0.521522, 0.663875, 1.042472",\ + "0.462451, 0.493883, 0.546591, 0.688944, 1.067541",\ + "0.531700, 0.563132, 0.615840, 0.758193, 1.136790",\ + "0.655903, 0.687335, 0.740043, 0.882396, 1.260993",\ + "1.286840, 1.318272, 1.370980, 1.513333, 1.891930"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.675759, 0.742664, 0.859102, 1.178771, 2.033976",\ + "0.696234, 0.763138, 0.879577, 1.199246, 2.054450",\ + "0.754790, 0.821694, 0.938133, 1.257802, 2.113006",\ + "0.864334, 0.931238, 1.047677, 1.367346, 2.222550",\ + "1.641748, 1.708657, 1.825099, 2.144769, 2.999968"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\ + "0.073042, 0.188941, 0.391856, 0.949133, 2.441345"); + } + + } /* end of arc obs_ctrl_o[10]_ast2padmux_o[4]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[10]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.284420, 0.315833, 0.368479, 0.510893, 0.889537",\ + "0.308019, 0.339432, 0.392078, 0.534493, 0.913136",\ + "0.380089, 0.411502, 0.464148, 0.606562, 0.985206",\ + "0.506286, 0.537698, 0.590344, 0.732759, 1.111402",\ + "1.081944, 1.113356, 1.166002, 1.308417, 1.687060"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091686"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.601029, 0.667919, 0.784346, 1.104014, 1.959234",\ + "0.617835, 0.684726, 0.801153, 1.120821, 1.976041",\ + "0.680343, 0.747234, 0.863661, 1.183329, 2.038548",\ + "0.789694, 0.856584, 0.973011, 1.292679, 2.147899",\ + "1.539211, 1.606101, 1.722528, 2.042196, 2.897416"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330"); + } + + } /* end of arc obs_ctrl_o[10]_ast2padmux_o[4]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[11]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.034927, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.180024, 0.211452, 0.264149, 0.406513, 0.785119",\ + "0.193406, 0.224834, 0.277531, 0.419896, 0.798501",\ + "0.275919, 0.307349, 0.360051, 0.502410, 0.881011",\ + "0.400910, 0.432352, 0.485095, 0.627414, 1.005985",\ + "0.975060, 1.010086, 1.063144, 1.205732, 1.584486"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.034927, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039119, 0.090633, 0.180636, 0.429262, 1.090996",\ + "0.039119, 0.090633, 0.180636, 0.429262, 1.090996",\ + "0.039132, 0.090633, 0.180667, 0.429269, 1.090996",\ + "0.039215, 0.090633, 0.180868, 0.429314, 1.090996",\ + "0.049347, 0.094034, 0.180868, 0.429355, 1.091896"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037147, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.465437, 0.532662, 0.649281, 0.969044, 1.824018",\ + "0.477695, 0.544920, 0.661539, 0.981302, 1.836276",\ + "0.541916, 0.609140, 0.725760, 1.045521, 1.900495",\ + "0.644626, 0.711856, 0.828474, 1.148242, 2.003221",\ + "1.319722, 1.387140, 1.503696, 1.823662, 2.678811"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037147, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073817, 0.189281, 0.392442, 0.950607, 2.441526",\ + "0.073817, 0.189281, 0.392442, 0.950607, 2.441526",\ + "0.073817, 0.189282, 0.392442, 0.950607, 2.441526",\ + "0.073862, 0.189282, 0.392442, 0.950619, 2.441526",\ + "0.075399, 0.189282, 0.392442, 0.951039, 2.441526"); + } + + } /* end of arc obs_ctrl_o[11]_ast2padmux_o[4]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[11]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.030664, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.159139, 0.190553, 0.243202, 0.385613, 0.764254",\ + "0.170514, 0.201928, 0.254577, 0.396989, 0.775629",\ + "0.255576, 0.286993, 0.339652, 0.482053, 0.860686",\ + "0.379908, 0.411340, 0.464049, 0.606401, 0.984998",\ + "0.945167, 0.979651, 1.032663, 1.175209, 1.553933"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.030664, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039020, 0.090609, 0.180397, 0.429208, 1.090831",\ + "0.039020, 0.090609, 0.180397, 0.429208, 1.090831",\ + "0.039042, 0.090609, 0.180449, 0.429220, 1.090831",\ + "0.039144, 0.090609, 0.180675, 0.429276, 1.090831",\ + "0.047820, 0.093501, 0.180675, 0.429352, 1.091629"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.028580, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.461683, 0.528880, 0.645509, 0.965243, 1.820192",\ + "0.470327, 0.537524, 0.654153, 0.973887, 1.828836",\ + "0.538174, 0.605371, 0.721999, 1.041733, 1.896681",\ + "0.640782, 0.707985, 0.824611, 1.144351, 1.999304",\ + "1.312551, 1.379913, 1.496487, 1.816396, 2.671496"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.028580, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073594, 0.189124, 0.392388, 0.950544, 2.441454",\ + "0.073594, 0.189124, 0.392388, 0.950544, 2.441454",\ + "0.073594, 0.189124, 0.392388, 0.950544, 2.441454",\ + "0.073633, 0.189124, 0.392388, 0.950557, 2.441454",\ + "0.074954, 0.189124, 0.392388, 0.950917, 2.441454"); + } + + } /* end of arc obs_ctrl_o[11]_ast2padmux_o[4]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.500858, 0.568082, 0.684702, 1.004464, 1.859437",\ + "0.516623, 0.583848, 0.700467, 1.020230, 1.875203",\ + "0.590734, 0.657958, 0.774578, 1.094340, 1.949314",\ + "0.681946, 0.749171, 0.865790, 1.185553, 2.040526",\ + "1.108576, 1.175805, 1.292423, 1.612190, 2.467167"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073816, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073848, 0.189277, 0.392440, 0.950615, 2.441524"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.275118, 0.306284, 0.358903, 0.501398, 0.880041",\ + "0.290749, 0.321915, 0.374533, 0.517029, 0.895671",\ + "0.363703, 0.394869, 0.447488, 0.589983, 0.968626",\ + "0.474794, 0.505959, 0.558577, 0.701073, 1.079716",\ + "1.013269, 1.044421, 1.097036, 1.239541, 1.618177"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040759, 0.090626, 0.180653, 0.429266, 1.092499",\ + "0.040922, 0.090525, 0.180916, 0.429325, 1.092539"); + } + + } /* end of arc obs_ctrl_o[4]_ast2padmux_o[4]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.337608, 0.404302, 0.520641, 0.837429, 1.687203",\ + "0.349939, 0.416633, 0.532972, 0.849760, 1.699534",\ + "0.408752, 0.475446, 0.591785, 0.908573, 1.758347",\ + "0.496083, 0.562777, 0.679117, 0.995905, 1.845678",\ + "0.949078, 1.015776, 1.132136, 1.448920, 2.298678"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184560, 0.382485, 0.937098, 2.417677",\ + "0.067604, 0.184551, 0.382483, 0.937052, 2.417689"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.209985, 0.241400, 0.294052, 0.436461, 0.815099",\ + "0.221857, 0.253271, 0.305923, 0.448332, 0.826970",\ + "0.304351, 0.335766, 0.388417, 0.530826, 0.909465",\ + "0.409226, 0.440642, 0.493298, 0.635702, 1.014338",\ + "0.909442, 0.940877, 0.993596, 1.135938, 1.514527"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039034, 0.090327, 0.180161, 0.428971, 1.091542",\ + "0.039166, 0.090324, 0.180166, 0.428948, 1.090692"); + } + + } /* end of arc obs_ctrl_o[4]_ast2padmux_o[4]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.287803, 0.318969, 0.371587, 0.514083, 0.892726",\ + "0.303569, 0.334734, 0.387353, 0.529848, 0.908491",\ + "0.378810, 0.409975, 0.462594, 0.605089, 0.983732",\ + "0.473884, 0.505049, 0.557668, 0.700163, 1.078806",\ + "0.918190, 0.949342, 1.001956, 1.144462, 1.523098"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040759, 0.090626, 0.180653, 0.429266, 1.092499",\ + "0.040922, 0.090525, 0.180916, 0.429325, 1.092539"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.376755, 0.443500, 0.560063, 0.876818, 1.726409",\ + "0.392417, 0.459162, 0.575725, 0.892480, 1.742071",\ + "0.467424, 0.534169, 0.650732, 0.967487, 1.817078",\ + "0.562603, 0.629351, 0.745928, 1.062681, 1.912261",\ + "1.006927, 1.073706, 1.190415, 1.507149, 2.356620"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073816, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073848, 0.189277, 0.392440, 0.950615, 2.441524"); + } + + } /* end of arc obs_ctrl_o[4]_ast2padmux_o[4]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.264318, 0.295567, 0.348210, 0.490643, 0.869326",\ + "0.278489, 0.309737, 0.362381, 0.504814, 0.883496",\ + "0.355325, 0.386573, 0.439217, 0.581649, 0.960332",\ + "0.450369, 0.481617, 0.534260, 0.676693, 1.055376",\ + "0.893831, 0.925076, 0.977718, 1.120154, 1.498834"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039034, 0.090327, 0.180161, 0.428971, 1.091542",\ + "0.039166, 0.090324, 0.180166, 0.428948, 1.090692"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.373701, 0.440395, 0.556734, 0.873522, 1.723296",\ + "0.385572, 0.452266, 0.568605, 0.885393, 1.735167",\ + "0.464371, 0.531065, 0.647404, 0.964192, 1.813966",\ + "0.559385, 0.626079, 0.742420, 1.059207, 1.908981",\ + "1.002245, 1.068944, 1.185303, 1.502088, 2.351846"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184560, 0.382485, 0.937098, 2.417677",\ + "0.067604, 0.184551, 0.382483, 0.937052, 2.417689"); + } + + } /* end of arc obs_ctrl_o[4]_ast2padmux_o[4]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.337998, 0.404744, 0.521308, 0.838063, 1.687653",\ + "0.353177, 0.419923, 0.536487, 0.853242, 1.702832",\ + "0.412195, 0.478941, 0.595505, 0.912260, 1.761850",\ + "0.508449, 0.575199, 0.691783, 1.008535, 1.858109",\ + "0.997007, 1.063817, 1.180658, 1.497372, 2.346736"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\ + "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073887, 0.189271, 0.392439, 0.950626, 2.441522",\ + "0.075818, 0.189005, 0.392348, 0.951153, 2.441399"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.272032, 0.303198, 0.355817, 0.498312, 0.876955",\ + "0.289891, 0.321056, 0.373675, 0.516170, 0.894813",\ + "0.360955, 0.392121, 0.444739, 0.587235, 0.965878",\ + "0.471378, 0.502542, 0.555160, 0.697656, 1.076298",\ + "1.004117, 1.035227, 1.087829, 1.230366, 1.608983"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\ + "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\ + "0.040752, 0.090633, 0.180666, 0.429269, 1.092497",\ + "0.040771, 0.090633, 0.180871, 0.429315, 1.092502",\ + "0.049622, 0.094130, 0.180871, 0.429356, 1.092666"); + } + + } /* end of arc obs_ctrl_o[5]_ast2padmux_o[4]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.329221, 0.395915, 0.512254, 0.829041, 1.678816",\ + "0.344592, 0.411286, 0.527624, 0.844412, 1.694187",\ + "0.406780, 0.473474, 0.589813, 0.906601, 1.756375",\ + "0.502234, 0.568932, 0.685288, 1.002073, 1.851833",\ + "0.957622, 1.024367, 1.140929, 1.457685, 2.307276"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067607, 0.184553, 0.382483, 0.937060, 2.417687",\ + "0.067439, 0.184458, 0.382464, 0.936568, 2.417820"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.231492, 0.262740, 0.315383, 0.457816, 0.836499",\ + "0.245351, 0.276600, 0.329243, 0.471676, 0.850359",\ + "0.320124, 0.351372, 0.404016, 0.546449, 0.925131",\ + "0.430166, 0.461410, 0.514053, 0.656489, 1.035169",\ + "0.955028, 0.986237, 1.038869, 1.181331, 1.559995"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039041, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039146, 0.090294, 0.180167, 0.428752, 1.090822",\ + "0.040211, 0.090294, 0.180212, 0.428752, 1.091676"); + } + + } /* end of arc obs_ctrl_o[5]_ast2padmux_o[4]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[5]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.176901, 0.208329, 0.261026, 0.403390, 0.781996",\ + "0.196158, 0.227585, 0.280282, 0.422647, 0.801252",\ + "0.273304, 0.304734, 0.357436, 0.499795, 0.878396",\ + "0.397207, 0.428649, 0.481392, 0.623711, 1.002282",\ + "0.961790, 0.996912, 1.049978, 1.192575, 1.571334"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\ + "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\ + "0.040752, 0.090633, 0.180666, 0.429269, 1.092497",\ + "0.040771, 0.090633, 0.180871, 0.429315, 1.092502",\ + "0.049622, 0.094130, 0.180871, 0.429356, 1.092666"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.455825, 0.523049, 0.639668, 0.959430, 1.814404",\ + "0.468963, 0.536187, 0.652807, 0.972569, 1.827542",\ + "0.531289, 0.598514, 0.715133, 1.034896, 1.889869",\ + "0.640154, 0.707387, 0.824004, 1.143775, 1.998757",\ + "1.332501, 1.399969, 1.516508, 1.836528, 2.691724"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\ + "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073887, 0.189271, 0.392439, 0.950626, 2.441522",\ + "0.075818, 0.189005, 0.392348, 0.951153, 2.441399"); + } + + } /* end of arc obs_ctrl_o[5]_ast2padmux_o[4]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[5]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.155833, 0.187247, 0.239896, 0.382308, 0.760949",\ + "0.173482, 0.204896, 0.257545, 0.399957, 0.778598",\ + "0.252964, 0.284381, 0.337040, 0.479441, 0.858074",\ + "0.376196, 0.407628, 0.460337, 0.602689, 0.981285",\ + "0.931678, 0.966257, 1.019278, 1.161831, 1.540560"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039041, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039146, 0.090294, 0.180167, 0.428752, 1.090822",\ + "0.040211, 0.090294, 0.180212, 0.428752, 1.091676"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.452081, 0.519278, 0.635907, 0.955640, 1.810589",\ + "0.461862, 0.529059, 0.645688, 0.965421, 1.820370",\ + "0.527542, 0.594739, 0.711368, 1.031102, 1.886050",\ + "0.636262, 0.703467, 0.820093, 1.139835, 1.994791",\ + "1.324350, 1.391756, 1.508316, 1.828270, 2.683409"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067607, 0.184553, 0.382483, 0.937060, 2.417687",\ + "0.067439, 0.184458, 0.382464, 0.936568, 2.417820"); + } + + } /* end of arc obs_ctrl_o[5]_ast2padmux_o[4]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[6]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.325984, 0.393209, 0.509828, 0.829592, 1.684567",\ + "0.341732, 0.408957, 0.525576, 0.845340, 1.700314",\ + "0.405621, 0.472847, 0.589466, 0.909229, 1.764204",\ + "0.483984, 0.551208, 0.667827, 0.987590, 1.842564",\ + "0.876566, 0.943791, 1.060410, 1.380173, 2.235147"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189281, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189281, 0.392442, 0.950608, 2.441526"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.207560, 0.238992, 0.291700, 0.434053, 0.812650",\ + "0.223441, 0.254873, 0.307582, 0.449934, 0.828531",\ + "0.292964, 0.324396, 0.377105, 0.519457, 0.898054",\ + "0.382304, 0.413736, 0.466444, 0.608797, 0.987394",\ + "0.808201, 0.839636, 0.892354, 1.034697, 1.413287"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\ + "0.040785, 0.090610, 0.180744, 0.429286, 1.092505"); + } + + } /* end of arc obs_ctrl_o[6]_ast2padmux_o[4]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[6]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.298728, 0.365697, 0.482189, 0.801862, 1.656989",\ + "0.312838, 0.379807, 0.496299, 0.815972, 1.671100",\ + "0.378416, 0.445385, 0.561877, 0.881551, 1.736677",\ + "0.456978, 0.523948, 0.640441, 0.960115, 1.815240",\ + "0.852482, 0.919491, 1.036016, 1.355692, 2.210772"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067586, 0.184541, 0.382481, 0.936998, 2.417704"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.185526, 0.216941, 0.269593, 0.412001, 0.790640",\ + "0.197528, 0.228943, 0.281595, 0.424004, 0.802642",\ + "0.270950, 0.302365, 0.355017, 0.497425, 0.876064",\ + "0.360375, 0.391790, 0.444442, 0.586850, 0.965489",\ + "0.786063, 0.817479, 0.870138, 1.012540, 1.391174"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039039, 0.090322, 0.180169, 0.428938, 1.091513"); + } + + } /* end of arc obs_ctrl_o[6]_ast2padmux_o[4]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[6]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.314064, 0.345229, 0.397848, 0.540343, 0.918986",\ + "0.329859, 0.361025, 0.413644, 0.556139, 0.934782",\ + "0.407724, 0.438890, 0.491508, 0.634004, 1.012646",\ + "0.508778, 0.539944, 0.592562, 0.735058, 1.113701",\ + "0.984655, 1.015818, 1.068436, 1.210933, 1.589574"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\ + "0.040785, 0.090610, 0.180744, 0.429286, 1.092505"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.596327, 0.663552, 0.780171, 1.099935, 1.954909",\ + "0.609131, 0.676356, 0.792975, 1.112739, 1.967713",\ + "0.677113, 0.744339, 0.860958, 1.180721, 2.035696",\ + "0.788810, 0.856034, 0.972654, 1.292416, 2.147390",\ + "1.273667, 1.340892, 1.457511, 1.777274, 2.632248"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189281, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189281, 0.392442, 0.950608, 2.441526"); + } + + } /* end of arc obs_ctrl_o[6]_ast2padmux_o[4]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[6]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.262848, 0.294262, 0.346915, 0.489323, 0.867962",\ + "0.276998, 0.308413, 0.361065, 0.503474, 0.882112",\ + "0.356726, 0.388141, 0.440793, 0.583202, 0.961840",\ + "0.457948, 0.489362, 0.542015, 0.684423, 1.063061",\ + "0.929777, 0.961193, 1.013852, 1.156254, 1.534888"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039039, 0.090322, 0.180169, 0.428938, 1.091513"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.437011, 0.503705, 0.620045, 0.936832, 1.786606",\ + "0.446608, 0.513302, 0.629642, 0.946429, 1.796203",\ + "0.517780, 0.584475, 0.700814, 1.017602, 1.867376",\ + "0.629396, 0.696091, 0.812430, 1.129218, 1.978992",\ + "1.131911, 1.198614, 1.314996, 1.631778, 2.481517"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067586, 0.184541, 0.382481, 0.936998, 2.417704"); + } + + } /* end of arc obs_ctrl_o[6]_ast2padmux_o[4]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[7]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.060518, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.315427, 0.346593, 0.399212, 0.541707, 0.920350",\ + "0.342146, 0.373312, 0.425930, 0.568426, 0.947068",\ + "0.410184, 0.441350, 0.493968, 0.636464, 1.015106",\ + "0.512927, 0.544093, 0.596711, 0.739207, 1.117850",\ + "0.999580, 1.030743, 1.083361, 1.225858, 1.604500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.060518, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180697, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180697, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180697, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180732, 0.429283, 1.092497",\ + "0.042004, 0.091469, 0.180867, 0.429340, 1.092504"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.051005, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.597332, 0.664558, 0.781177, 1.100940, 1.955915",\ + "0.618079, 0.685305, 0.801924, 1.121688, 1.976662",\ + "0.683404, 0.750630, 0.867249, 1.187012, 2.041987",\ + "0.797603, 0.864828, 0.981447, 1.301210, 2.156184",\ + "1.375793, 1.443018, 1.559637, 1.879400, 2.734374"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.051005, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189280, 0.392442, 0.950609, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073823, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073819, 0.189281, 0.392442, 0.950607, 2.441526",\ + "0.073817, 0.189281, 0.392442, 0.950607, 2.441526"); + } + + } /* end of arc obs_ctrl_o[7]_ast2padmux_o[4]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[7]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.049671, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.150722, 0.182137, 0.234789, 0.377197, 0.755836",\ + "0.171205, 0.202620, 0.255272, 0.397681, 0.776319",\ + "0.246518, 0.277932, 0.330585, 0.472993, 0.851631",\ + "0.352324, 0.383738, 0.436391, 0.578799, 0.957437",\ + "0.825559, 0.856975, 0.909634, 1.052036, 1.430670"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.049671, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039038, 0.090323, 0.180168, 0.428941, 1.091519"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040467, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.277343, 0.344312, 0.460804, 0.780477, 1.635605",\ + "0.293355, 0.360323, 0.476815, 0.796489, 1.651616",\ + "0.366113, 0.433085, 0.549579, 0.869253, 1.724376",\ + "0.487008, 0.554003, 0.670516, 0.990192, 1.845287",\ + "1.141953, 1.209132, 1.325766, 1.645481, 2.500414"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040467, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067601, 0.184550, 0.382483, 0.937044, 2.417691"); + } + + } /* end of arc obs_ctrl_o[7]_ast2padmux_o[4]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[8]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.700503, 0.767407, 0.883846, 1.203515, 2.058719",\ + "0.718853, 0.785757, 0.902195, 1.221864, 2.077069",\ + "0.789289, 0.856194, 0.972632, 1.292301, 2.147506",\ + "0.881295, 0.948199, 1.064638, 1.384307, 2.239511",\ + "1.366874, 1.433786, 1.550230, 1.869900, 2.725095"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073043, 0.188945, 0.391861, 0.949146, 2.441348"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.488066, 0.519497, 0.572205, 0.714558, 1.093155",\ + "0.505493, 0.536925, 0.589633, 0.731986, 1.110583",\ + "0.582890, 0.614322, 0.667030, 0.809383, 1.187980",\ + "0.691218, 0.722650, 0.775358, 0.917711, 1.296308",\ + "1.240839, 1.272271, 1.324979, 1.467332, 1.845928"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837"); + } + + } /* end of arc obs_ctrl_o[8]_ast2padmux_o[4]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[8]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.636502, 0.703393, 0.819820, 1.139488, 1.994708",\ + "0.653118, 0.720008, 0.836435, 1.156103, 2.011323",\ + "0.727479, 0.794369, 0.910796, 1.230464, 2.085684",\ + "0.821960, 0.888850, 1.005277, 1.324945, 2.180165",\ + "1.269718, 1.336608, 1.453035, 1.772703, 2.627923"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.340324, 0.371736, 0.424382, 0.566797, 0.945440",\ + "0.353670, 0.385083, 0.437728, 0.580143, 0.958786",\ + "0.435082, 0.466495, 0.519140, 0.661555, 1.040198",\ + "0.544387, 0.575800, 0.628446, 0.770861, 1.149504",\ + "1.068007, 1.099420, 1.152066, 1.294481, 1.673124"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091686"); + } + + } /* end of arc obs_ctrl_o[8]_ast2padmux_o[4]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[8]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.524400, 0.555831, 0.608540, 0.750893, 1.129489",\ + "0.542749, 0.574181, 0.626889, 0.769242, 1.147839",\ + "0.616605, 0.648037, 0.700745, 0.843098, 1.221695",\ + "0.714879, 0.746311, 0.799019, 0.941372, 1.319969",\ + "1.235698, 1.267130, 1.319839, 1.462191, 1.840788"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.651244, 0.718149, 0.834587, 1.154256, 2.009460",\ + "0.663867, 0.730771, 0.847209, 1.166878, 2.022083",\ + "0.718674, 0.785579, 0.902017, 1.221686, 2.076890",\ + "0.820628, 0.887532, 1.003971, 1.323640, 2.178844",\ + "1.548479, 1.615391, 1.731835, 2.051504, 2.906700"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073043, 0.188945, 0.391861, 0.949146, 2.441348"); + } + + } /* end of arc obs_ctrl_o[8]_ast2padmux_o[4]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[8]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.305082, 0.336495, 0.389141, 0.531556, 0.910199",\ + "0.321682, 0.353095, 0.405741, 0.548156, 0.926799",\ + "0.400692, 0.432104, 0.484750, 0.627165, 1.005808",\ + "0.527571, 0.558983, 0.611629, 0.754044, 1.132687",\ + "1.082115, 1.113528, 1.166173, 1.308588, 1.687232"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091686"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.456335, 0.523226, 0.639653, 0.959321, 1.814541",\ + "0.469682, 0.536572, 0.652999, 0.972667, 1.827887",\ + "0.547821, 0.614711, 0.731138, 1.050806, 1.906026",\ + "0.649000, 0.715890, 0.832317, 1.151985, 2.007205",\ + "1.120855, 1.187745, 1.304172, 1.623840, 2.479060"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330"); + } + + } /* end of arc obs_ctrl_o[8]_ast2padmux_o[4]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[9]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.712314, 0.779218, 0.895657, 1.215326, 2.070530",\ + "0.730867, 0.797771, 0.914210, 1.233879, 2.089083",\ + "0.803565, 0.870469, 0.986908, 1.306577, 2.161781",\ + "0.898790, 0.965694, 1.082133, 1.401802, 2.257006",\ + "1.355292, 1.422199, 1.538640, 1.858309, 2.713511"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073040, 0.188938, 0.391851, 0.949122, 2.441344"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.494441, 0.525873, 0.578581, 0.720934, 1.099531",\ + "0.511983, 0.543415, 0.596123, 0.738476, 1.117073",\ + "0.589312, 0.620744, 0.673452, 0.815805, 1.194402",\ + "0.698758, 0.730189, 0.782897, 0.925250, 1.303847",\ + "1.224584, 1.256016, 1.308724, 1.451077, 1.829674"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837"); + } + + } /* end of arc obs_ctrl_o[9]_ast2padmux_o[4]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[9]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.668630, 0.735520, 0.851947, 1.171615, 2.026835",\ + "0.685451, 0.752341, 0.868768, 1.188436, 2.043656",\ + "0.759882, 0.826773, 0.943200, 1.262868, 2.118088",\ + "0.855138, 0.922028, 1.038455, 1.358123, 2.213343",\ + "1.307789, 1.374679, 1.491106, 1.810774, 2.665994"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.361796, 0.393209, 0.445854, 0.588269, 0.966913",\ + "0.375252, 0.406665, 0.459311, 0.601726, 0.980369",\ + "0.456673, 0.488086, 0.540731, 0.683146, 1.061790",\ + "0.566647, 0.598060, 0.650706, 0.793121, 1.171764",\ + "1.092083, 1.123496, 1.176142, 1.318556, 1.697200"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091686"); + } + + } /* end of arc obs_ctrl_o[9]_ast2padmux_o[4]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[9]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.528266, 0.559698, 0.612406, 0.754759, 1.133356",\ + "0.546819, 0.578250, 0.630959, 0.773312, 1.151908",\ + "0.620877, 0.652309, 0.705017, 0.847370, 1.225967",\ + "0.719978, 0.751410, 0.804118, 0.946471, 1.325068",\ + "1.187533, 1.218965, 1.271673, 1.414026, 1.792623"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.604133, 0.671037, 0.787476, 1.107145, 1.962349",\ + "0.616822, 0.683727, 0.800165, 1.119834, 1.975038",\ + "0.671505, 0.738410, 0.854848, 1.174517, 2.029721",\ + "0.774589, 0.841493, 0.957932, 1.277601, 2.132805",\ + "1.473004, 1.539911, 1.656352, 1.976021, 2.831222"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073040, 0.188938, 0.391851, 0.949122, 2.441344"); + } + + } /* end of arc obs_ctrl_o[9]_ast2padmux_o[4]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[9]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.284809, 0.316222, 0.368868, 0.511283, 0.889926",\ + "0.301623, 0.333036, 0.385681, 0.528096, 0.906739",\ + "0.380088, 0.411501, 0.464146, 0.606561, 0.985205",\ + "0.509697, 0.541110, 0.593756, 0.736170, 1.114814",\ + "1.092277, 1.123690, 1.176336, 1.318751, 1.697394"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091686"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.463612, 0.530502, 0.646929, 0.966597, 1.821817",\ + "0.477068, 0.543958, 0.660386, 0.980054, 1.835274",\ + "0.555357, 0.622247, 0.738674, 1.058342, 1.913562",\ + "0.655033, 0.721923, 0.838350, 1.158018, 2.013238",\ + "1.119877, 1.186768, 1.303195, 1.622863, 2.478083"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330"); + } + + } /* end of arc obs_ctrl_o[9]_ast2padmux_o[4]_inv_min*/ + + timing () { + related_pin : "otm_obs_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.123879, 0.190820, 0.307288, 0.626960, 1.482121",\ + "0.210891, 0.277978, 0.394567, 0.714249, 1.569235",\ + "0.301781, 0.369068, 0.485667, 0.805496, 1.660526",\ + "0.453978, 0.523120, 0.640034, 0.960158, 1.815427",\ + "0.695902, 0.774527, 0.893732, 1.214148, 2.069560"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073065, 0.188997, 0.391936, 0.949305, 2.441374",\ + "0.073175, 0.189249, 0.392304, 0.950092, 2.441498",\ + "0.074330, 0.189249, 0.392418, 0.950747, 2.441498",\ + "0.079436, 0.191164, 0.392505, 0.951076, 2.441498",\ + "0.098084, 0.204137, 0.393542, 0.951076, 2.441498"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.114293, 0.145721, 0.198417, 0.340782, 0.719388",\ + "0.205394, 0.236828, 0.289545, 0.431889, 0.810480",\ + "0.309904, 0.342065, 0.394885, 0.537244, 0.915841",\ + "0.501618, 0.536979, 0.590065, 0.732680, 1.111452",\ + "0.825607, 0.870622, 0.930343, 1.075147, 1.454209"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039117, 0.090634, 0.180632, 0.429261, 1.091005",\ + "0.039161, 0.090634, 0.180739, 0.429285, 1.091005",\ + "0.041267, 0.091212, 0.180891, 0.429338, 1.091005",\ + "0.050293, 0.094364, 0.180891, 0.429357, 1.092061",\ + "0.068556, 0.114740, 0.192215, 0.429716, 1.093122"); + } + + } /* end of arc otm_obs_i[4]_ast2padmux_o[4]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "otm_obs_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.120559, 0.187489, 0.303948, 0.623619, 1.478793",\ + "0.205712, 0.272774, 0.389342, 0.709022, 1.564038",\ + "0.292652, 0.359907, 0.476516, 0.796311, 1.651312",\ + "0.437434, 0.505450, 0.622092, 0.942182, 1.797434",\ + "0.662107, 0.738115, 0.856688, 1.177023, 2.032395"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073057, 0.188977, 0.391908, 0.949245, 2.441364",\ + "0.073156, 0.189206, 0.392241, 0.949956, 2.441378",\ + "0.074065, 0.189247, 0.392382, 0.950255, 2.441378",\ + "0.077223, 0.189624, 0.392382, 0.950255, 2.441378",\ + "0.092938, 0.200557, 0.393255, 0.950255, 2.441468"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.094368, 0.125782, 0.178430, 0.320842, 0.699483",\ + "0.188259, 0.219683, 0.272369, 0.414744, 0.793358",\ + "0.291365, 0.323244, 0.376040, 0.518376, 0.896959",\ + "0.474009, 0.509208, 0.562280, 0.704883, 1.083646",\ + "0.777508, 0.822171, 0.881623, 1.026340, 1.405392"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039018, 0.090654, 0.180392, 0.429207, 1.090346",\ + "0.039096, 0.090654, 0.180581, 0.429249, 1.090346",\ + "0.040472, 0.090934, 0.180608, 0.429337, 1.090346",\ + "0.049836, 0.094205, 0.180608, 0.429356, 1.091981",\ + "0.067933, 0.113945, 0.191732, 0.429701, 1.093101"); + } + + } /* end of arc otm_obs_i[4]_ast2padmux_o[4]_una_min*/ + + timing () { + related_pin : "otp_obs_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.122660, 0.189370, 0.305783, 0.622560, 1.472274",\ + "0.209824, 0.276743, 0.394059, 0.710704, 1.559679",\ + "0.301920, 0.369023, 0.486415, 0.804486, 1.652417",\ + "0.455547, 0.524976, 0.642287, 0.962376, 1.809444",\ + "0.699992, 0.780922, 0.900058, 1.218756, 2.067549"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067561, 0.184527, 0.382478, 0.936925, 2.417724",\ + "0.067561, 0.184527, 0.382478, 0.936925, 2.418306",\ + "0.068683, 0.184527, 0.382544, 0.936925, 2.418306",\ + "0.075540, 0.185756, 0.383113, 0.940410, 2.418306",\ + "0.094401, 0.199857, 0.384817, 0.940410, 2.426093"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.114764, 0.145947, 0.198571, 0.341053, 0.719705",\ + "0.205629, 0.236785, 0.289401, 0.431904, 0.810542",\ + "0.310076, 0.342571, 0.395201, 0.537686, 0.916183",\ + "0.500896, 0.538360, 0.591093, 0.733386, 1.111456",\ + "0.820213, 0.870292, 0.933027, 1.077593, 1.455130"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040532, 0.090273, 0.180246, 0.428609, 1.092443",\ + "0.040870, 0.090273, 0.180281, 0.428609, 1.092443",\ + "0.045400, 0.092351, 0.180508, 0.428609, 1.092443",\ + "0.059558, 0.100025, 0.181106, 0.428872, 1.092443",\ + "0.087354, 0.133744, 0.204884, 0.431205, 1.092443"); + } + + } /* end of arc otp_obs_i[4]_ast2padmux_o[4]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "otp_obs_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.119334, 0.186028, 0.302368, 0.619155, 1.468929",\ + "0.204833, 0.271716, 0.388876, 0.705544, 1.554647",\ + "0.293319, 0.360401, 0.477846, 0.795625, 1.643707",\ + "0.440314, 0.508488, 0.625608, 0.945855, 1.792734",\ + "0.667813, 0.745674, 0.864272, 1.183300, 2.031636"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.183691, 0.382409, 0.935142, 2.413233",\ + "0.067620, 0.183691, 0.382409, 0.935142, 2.413233",\ + "0.068262, 0.183691, 0.382508, 0.936031, 2.413233",\ + "0.073482, 0.184226, 0.382946, 0.939859, 2.413233",\ + "0.089380, 0.196045, 0.384240, 0.939859, 2.423100"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.094521, 0.125776, 0.178422, 0.320849, 0.699535",\ + "0.188239, 0.219444, 0.272075, 0.414540, 0.793202",\ + "0.291550, 0.323577, 0.376197, 0.518700, 0.897237",\ + "0.473699, 0.510899, 0.563627, 0.705929, 1.084022",\ + "0.773733, 0.823401, 0.885774, 1.030256, 1.407808"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039633, 0.090291, 0.180152, 0.428296, 1.092222",\ + "0.040262, 0.090291, 0.180217, 0.428296, 1.092377",\ + "0.044064, 0.091627, 0.180452, 0.428296, 1.092425",\ + "0.058805, 0.099616, 0.181075, 0.428844, 1.092425",\ + "0.086478, 0.132591, 0.204027, 0.431125, 1.092425"); + } + + } /* end of arc otp_obs_i[4]_ast2padmux_o[4]_una_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "970001.062500, 970001.062500, 970001.125000, 970001.312500, 970001.687500",\ + "970001.187500, 970001.187500, 970001.250000, 970001.437500, 970001.812500",\ + "970001.187500, 970001.187500, 970001.250000, 970001.437500, 970001.812500",\ + "970001.437500, 970001.437500, 970001.500000, 970001.687500, 970002.062500",\ + "970001.687500, 970001.687500, 970001.750000, 970001.937500, 970002.312500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "970001.875000, 970001.937500, 970002.062500, 970002.375000, 970003.250000",\ + "970002.000000, 970002.062500, 970002.187500, 970002.500000, 970003.375000",\ + "970002.125000, 970002.187500, 970002.312500, 970002.625000, 970003.500000",\ + "970002.375000, 970002.437500, 970002.562500, 970002.875000, 970003.750000",\ + "970002.625000, 970002.687500, 970002.812500, 970003.125000, 970004.000000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526"); + } + + } /* end of arc padmux2ast_i[4]_ast2padmux_o[4]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380000.312500, 380000.312500, 380000.343750, 380000.406250, 380000.593750",\ + "380000.406250, 380000.406250, 380000.437500, 380000.500000, 380000.687500",\ + "380000.468750, 380000.468750, 380000.500000, 380000.562500, 380000.750000",\ + "380000.625000, 380000.625000, 380000.656250, 380000.718750, 380000.906250",\ + "380000.843750, 380000.843750, 380000.875000, 380000.937500, 380001.125000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380001.781250, 380001.812500, 380001.906250, 380002.187500, 380002.875000",\ + "380001.875000, 380001.906250, 380002.000000, 380002.281250, 380002.968750",\ + "380001.968750, 380002.000000, 380002.093750, 380002.375000, 380003.062500",\ + "380002.156250, 380002.187500, 380002.281250, 380002.562500, 380003.250000",\ + "380002.406250, 380002.437500, 380002.531250, 380002.812500, 380003.500000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169"); + } + + } /* end of arc padmux2ast_i[4]_ast2padmux_o[4]_inv_min*/ + + timing () { + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "590000.250000, 590000.312500, 590000.437500, 590000.750000, 590001.625000",\ + "590000.375000, 590000.437500, 590000.562500, 590000.875000, 590001.750000",\ + "590000.375000, 590000.437500, 590000.562500, 590000.875000, 590001.750000",\ + "590000.500000, 590000.562500, 590000.687500, 590001.000000, 590001.875000",\ + "590000.750000, 590000.812500, 590000.937500, 590001.250000, 590002.125000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "590000.812500, 590000.812500, 590000.875000, 590001.062500, 590001.437500",\ + "590000.937500, 590000.937500, 590001.000000, 590001.187500, 590001.562500",\ + "590001.062500, 590001.062500, 590001.125000, 590001.312500, 590001.687500",\ + "590001.187500, 590001.187500, 590001.250000, 590001.437500, 590001.812500",\ + "590001.562500, 590001.562500, 590001.625000, 590001.812500, 590002.187500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090610, 0.180695, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180695, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180695, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180695, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180695, 0.429275, 1.092497"); + } + + } /* end of arc padmux2ast_i[5]_ast2padmux_o[4]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "590000.187500, 590000.250000, 590000.375000, 590000.687500, 590001.562500",\ + "590000.187500, 590000.250000, 590000.375000, 590000.687500, 590001.562500",\ + "590000.312500, 590000.375000, 590000.500000, 590000.812500, 590001.687500",\ + "590000.437500, 590000.500000, 590000.625000, 590000.937500, 590001.812500",\ + "590000.687500, 590000.750000, 590000.875000, 590001.187500, 590002.062500"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067834, 0.184682, 0.382509, 0.937727, 2.417507",\ + "0.067834, 0.184682, 0.382509, 0.937727, 2.417507",\ + "0.067834, 0.184682, 0.382509, 0.937727, 2.417507",\ + "0.067834, 0.184682, 0.382509, 0.937727, 2.417507",\ + "0.067834, 0.184682, 0.382509, 0.937727, 2.417507"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "590000.812500, 590000.812500, 590000.875000, 590001.000000, 590001.437500",\ + "590000.937500, 590000.937500, 590001.000000, 590001.125000, 590001.562500",\ + "590001.062500, 590001.062500, 590001.125000, 590001.250000, 590001.687500",\ + "590001.187500, 590001.187500, 590001.250000, 590001.375000, 590001.812500",\ + "590001.437500, 590001.437500, 590001.500000, 590001.625000, 590002.062500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039013, 0.090351, 0.180124, 0.429131, 1.091682",\ + "0.039013, 0.090351, 0.180124, 0.429131, 1.091682",\ + "0.039013, 0.090351, 0.180124, 0.429131, 1.091682",\ + "0.039013, 0.090351, 0.180124, 0.429131, 1.091682",\ + "0.039013, 0.090351, 0.180124, 0.429131, 1.091682"); + } + + } /* end of arc padmux2ast_i[5]_ast2padmux_o[4]_una_min*/ + +} /* end of pin ast2padmux_o[4] */ + +pin("ast2padmux_o[3]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.028584 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : ast2padmux_o[3]; + timing () { + related_pin : "clk_ast_rng_i" ; + related_output_pin : "rng_b_o[2]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.257031, 0.528778, 0.797030, 1.242767, 2.134242",\ + "0.323932, 0.595681, 0.863940, 1.309691, 2.201193",\ + "0.440368, 0.712118, 0.980382, 1.426145, 2.317669",\ + "0.760037, 1.031787, 1.300052, 1.745815, 2.637342",\ + "1.615245, 1.886993, 2.155250, 2.600997, 3.492491",\ + "0.315617, 0.587294, 0.855812, 1.300474, 2.190349",\ + "0.382518, 0.654197, 0.922722, 1.367397, 2.257300",\ + "0.498954, 0.770634, 1.039164, 1.483851, 2.373776",\ + "0.818623, 1.090303, 1.358834, 1.803522, 2.693449",\ + "1.673831, 1.945509, 2.214032, 2.658703, 3.548597",\ + "0.460207, 0.733101, 0.999707, 1.444229, 2.334082",\ + "0.527108, 0.800004, 1.066617, 1.511152, 2.401032",\ + "0.643544, 0.916442, 1.183060, 1.627606, 2.517509",\ + "0.963213, 1.236110, 1.502729, 1.947277, 2.837182",\ + "1.818421, 2.091316, 2.357927, 2.802459, 3.692330",\ + "0.496168, 0.770865, 1.036627, 1.481020, 2.370640",\ + "0.563069, 0.837768, 1.103536, 1.547944, 2.437591",\ + "0.679505, 0.954206, 1.219979, 1.664398, 2.554067",\ + "0.999174, 1.273875, 1.539648, 1.984068, 2.873740",\ + "1.854382, 2.129080, 2.394846, 2.839250, 3.728889",\ + "0.825262, 1.134787, 1.388262, 1.830277, 2.716096",\ + "0.892164, 1.201690, 1.455172, 1.897201, 2.783047",\ + "1.008600, 1.318128, 1.571615, 2.013655, 2.899523",\ + "1.328269, 1.637797, 1.891284, 2.333325, 3.219196",\ + "2.183476, 2.493002, 2.746482, 3.188507, 4.074345"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.073036, 0.073037, 0.073042, 0.073052, 0.073073",\ + "0.188928, 0.188931, 0.188942, 0.188966, 0.189013",\ + "0.391836, 0.391841, 0.391857, 0.391892, 0.391961",\ + "0.949092, 0.949101, 0.949136, 0.949210, 0.949357",\ + "2.441339, 2.441340, 2.441346, 2.441358, 2.441383",\ + "0.073036, 0.073037, 0.073042, 0.073052, 0.073073",\ + "0.188928, 0.188931, 0.188942, 0.188966, 0.189013",\ + "0.391836, 0.391841, 0.391857, 0.391892, 0.391961",\ + "0.949092, 0.949101, 0.949136, 0.949210, 0.949357",\ + "2.441339, 2.441340, 2.441346, 2.441358, 2.441383",\ + "0.073036, 0.073037, 0.073042, 0.073052, 0.073073",\ + "0.188928, 0.188931, 0.188942, 0.188966, 0.189013",\ + "0.391836, 0.391841, 0.391857, 0.391892, 0.391961",\ + "0.949092, 0.949102, 0.949136, 0.949210, 0.949357",\ + "2.441339, 2.441340, 2.441346, 2.441358, 2.441383",\ + "0.073036, 0.073037, 0.073042, 0.073052, 0.073073",\ + "0.188928, 0.188931, 0.188942, 0.188966, 0.189013",\ + "0.391836, 0.391841, 0.391857, 0.391892, 0.391961",\ + "0.949092, 0.949102, 0.949136, 0.949210, 0.949357",\ + "2.441339, 2.441340, 2.441346, 2.441358, 2.441383",\ + "0.073036, 0.073038, 0.073042, 0.073052, 0.073073",\ + "0.188928, 0.188932, 0.188943, 0.188966, 0.189013",\ + "0.391836, 0.391843, 0.391858, 0.391892, 0.391961",\ + "0.949092, 0.949105, 0.949137, 0.949210, 0.949357",\ + "2.441339, 2.441341, 2.441346, 2.441358, 2.441383"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.308725, 0.491796, 0.685627, 0.996163, 1.596700",\ + "0.340157, 0.523228, 0.717058, 1.027595, 1.628132",\ + "0.392865, 0.575936, 0.769767, 1.080304, 1.680844",\ + "0.535218, 0.718289, 0.912119, 1.222656, 1.823194",\ + "0.913815, 1.096886, 1.290716, 1.601252, 2.201788",\ + "0.368637, 0.551695, 0.745581, 1.055944, 1.656317",\ + "0.400068, 0.583126, 0.777012, 1.087376, 1.687749",\ + "0.452777, 0.635835, 0.829721, 1.140085, 1.740461",\ + "0.595130, 0.778187, 0.972073, 1.282437, 1.882811",\ + "0.973727, 1.156784, 1.350670, 1.661033, 2.261405",\ + "0.501379, 0.683946, 0.877464, 1.187801, 1.788124",\ + "0.532811, 0.715378, 0.908895, 1.219233, 1.819557",\ + "0.585519, 0.768086, 0.961603, 1.271942, 1.872268",\ + "0.727872, 0.910439, 1.103956, 1.414294, 2.014618",\ + "1.106469, 1.289036, 1.482553, 1.792891, 2.393212",\ + "0.534516, 0.717073, 0.910588, 1.220754, 1.820733",\ + "0.565947, 0.748505, 0.942020, 1.252186, 1.852165",\ + "0.618656, 0.801213, 0.994728, 1.304895, 1.904876",\ + "0.761009, 0.943566, 1.137081, 1.447247, 2.047226",\ + "1.139605, 1.322163, 1.515678, 1.825843, 2.425821",\ + "0.835592, 1.022294, 1.214223, 1.523770, 2.122581",\ + "0.867023, 1.053726, 1.245655, 1.555202, 2.154014",\ + "0.919731, 1.106434, 1.298363, 1.607911, 2.206725",\ + "1.062084, 1.248787, 1.440716, 1.750263, 2.349075",\ + "1.440681, 1.627384, 1.819313, 2.128859, 2.727669"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.039143, 0.039143, 0.039143, 0.039145, 0.039150",\ + "0.090610, 0.090610, 0.090610, 0.090608, 0.090604",\ + "0.180695, 0.180695, 0.180695, 0.180700, 0.180710",\ + "0.429275, 0.429275, 0.429275, 0.429276, 0.429279",\ + "1.090837, 1.090837, 1.090837, 1.090825, 1.090796",\ + "0.039143, 0.039143, 0.039143, 0.039145, 0.039150",\ + "0.090610, 0.090610, 0.090610, 0.090608, 0.090604",\ + "0.180695, 0.180695, 0.180695, 0.180700, 0.180710",\ + "0.429275, 0.429275, 0.429275, 0.429276, 0.429279",\ + "1.090837, 1.090837, 1.090837, 1.090825, 1.090796",\ + "0.039143, 0.039143, 0.039143, 0.039145, 0.039150",\ + "0.090610, 0.090610, 0.090610, 0.090608, 0.090604",\ + "0.180695, 0.180695, 0.180695, 0.180700, 0.180710",\ + "0.429275, 0.429275, 0.429275, 0.429276, 0.429279",\ + "1.090837, 1.090837, 1.090837, 1.090825, 1.090796",\ + "0.039143, 0.039143, 0.039143, 0.039145, 0.039150",\ + "0.090610, 0.090610, 0.090610, 0.090608, 0.090604",\ + "0.180695, 0.180695, 0.180695, 0.180700, 0.180710",\ + "0.429275, 0.429275, 0.429275, 0.429276, 0.429279",\ + "1.090837, 1.090837, 1.090837, 1.090825, 1.090796",\ + "0.039143, 0.039143, 0.039143, 0.039145, 0.039150",\ + "0.090610, 0.090610, 0.090610, 0.090608, 0.090604",\ + "0.180695, 0.180695, 0.180695, 0.180700, 0.180710",\ + "0.429275, 0.429275, 0.429275, 0.429276, 0.429279",\ + "1.090837, 1.090837, 1.090837, 1.090825, 1.090796"); + } + + } /* end of arc clk_ast_rng_i_ast2padmux_o[3]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_rng_i" ; + related_output_pin : "rng_b_o[2]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.252558, 0.520745, 0.784515, 1.222569, 2.097608",\ + "0.319449, 0.587637, 0.851411, 1.289475, 2.164534",\ + "0.435876, 0.704065, 0.967843, 1.405915, 2.280990",\ + "0.755544, 1.023733, 1.287511, 1.725584, 2.600661",\ + "1.610764, 1.878952, 2.142725, 2.580786, 3.455839",\ + "0.311120, 0.579252, 0.843280, 1.280275, 2.153714",\ + "0.378011, 0.646143, 0.910176, 1.347182, 2.220640",\ + "0.494438, 0.762572, 1.026608, 1.463622, 2.337097",\ + "0.814106, 1.082240, 1.346276, 1.783291, 2.656767",\ + "1.669326, 1.937458, 2.201490, 2.638493, 3.511946",\ + "0.455460, 0.724999, 0.987167, 1.424079, 2.297447",\ + "0.522351, 0.791891, 1.054064, 1.490985, 2.364373",\ + "0.638778, 0.908319, 1.170496, 1.607426, 2.480830",\ + "0.958446, 1.227987, 1.490164, 1.927095, 2.800500",\ + "1.813666, 2.083206, 2.345378, 2.782297, 3.655679",\ + "0.491341, 0.762735, 1.024086, 1.460950, 2.334005",\ + "0.558231, 0.829626, 1.090982, 1.527856, 2.400931",\ + "0.674659, 0.946054, 1.207414, 1.644296, 2.517388",\ + "0.994327, 1.265722, 1.527082, 1.963966, 2.837059",\ + "1.849546, 2.120941, 2.382296, 2.819168, 3.692237",\ + "0.819555, 1.126080, 1.375645, 1.810251, 2.679461",\ + "0.886446, 1.192972, 1.442542, 1.877157, 2.746387",\ + "1.002873, 1.309400, 1.558974, 1.993597, 2.862844",\ + "1.322541, 1.629068, 1.878642, 2.313266, 3.182515",\ + "2.177761, 2.484287, 2.733856, 3.168468, 4.037693"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.073031, 0.073031, 0.073033, 0.073040, 0.073054",\ + "0.188915, 0.188915, 0.188919, 0.188937, 0.188971",\ + "0.391815, 0.391816, 0.391824, 0.391849, 0.391899",\ + "0.949014, 0.949028, 0.949065, 0.949118, 0.949226",\ + "2.441330, 2.441330, 2.441334, 2.441343, 2.441361",\ + "0.073031, 0.073031, 0.073033, 0.073040, 0.073054",\ + "0.188915, 0.188915, 0.188919, 0.188937, 0.188971",\ + "0.391815, 0.391816, 0.391824, 0.391849, 0.391899",\ + "0.949014, 0.949028, 0.949065, 0.949118, 0.949226",\ + "2.441330, 2.441330, 2.441334, 2.441343, 2.441361",\ + "0.073031, 0.073031, 0.073033, 0.073040, 0.073054",\ + "0.188915, 0.188915, 0.188920, 0.188937, 0.188971",\ + "0.391815, 0.391816, 0.391824, 0.391849, 0.391899",\ + "0.949014, 0.949029, 0.949065, 0.949118, 0.949226",\ + "2.441330, 2.441330, 2.441334, 2.441343, 2.441361",\ + "0.073031, 0.073031, 0.073033, 0.073040, 0.073054",\ + "0.188915, 0.188915, 0.188920, 0.188937, 0.188971",\ + "0.391815, 0.391816, 0.391824, 0.391849, 0.391899",\ + "0.949014, 0.949029, 0.949065, 0.949119, 0.949226",\ + "2.441330, 2.441330, 2.441334, 2.441343, 2.441361",\ + "0.073031, 0.073031, 0.073033, 0.073040, 0.073054",\ + "0.188915, 0.188915, 0.188920, 0.188937, 0.188971",\ + "0.391816, 0.391816, 0.391824, 0.391849, 0.391899",\ + "0.949014, 0.949034, 0.949065, 0.949119, 0.949226",\ + "2.441330, 2.441331, 2.441334, 2.441343, 2.441361"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.262934, 0.448489, 0.641595, 0.948064, 1.538713",\ + "0.294346, 0.479902, 0.673008, 0.979478, 1.570129",\ + "0.346992, 0.532548, 0.725656, 1.032128, 1.622785",\ + "0.489407, 0.674962, 0.868069, 1.174539, 1.765190",\ + "0.868050, 1.053605, 1.246711, 1.553179, 2.143825",\ + "0.322845, 0.508317, 0.701440, 1.007833, 1.598330",\ + "0.354258, 0.539729, 0.732853, 1.039247, 1.629746",\ + "0.406904, 0.592376, 0.785500, 1.091897, 1.682402",\ + "0.549319, 0.734790, 0.927914, 1.234307, 1.824806",\ + "0.927962, 1.113433, 1.306556, 1.612947, 2.203442",\ + "0.455621, 0.640568, 0.833323, 1.139690, 1.730137",\ + "0.487034, 0.671981, 0.864736, 1.171104, 1.761553",\ + "0.539679, 0.724627, 0.917383, 1.223754, 1.814209",\ + "0.682094, 0.867041, 1.059797, 1.366165, 1.956614",\ + "1.060737, 1.245684, 1.438439, 1.744805, 2.335249",\ + "0.488779, 0.673866, 0.866553, 1.172770, 1.762998",\ + "0.520192, 0.705279, 0.897966, 1.204184, 1.794413",\ + "0.572837, 0.757925, 0.950613, 1.256834, 1.847070",\ + "0.715252, 0.900339, 1.093027, 1.399244, 1.989474",\ + "1.093896, 1.278982, 1.471669, 1.777884, 2.368110",\ + "0.790171, 0.979313, 1.170216, 1.475973, 2.065303",\ + "0.821584, 1.010726, 1.201629, 1.507387, 2.096719",\ + "0.874230, 1.063372, 1.254276, 1.560037, 2.149375",\ + "1.016645, 1.205787, 1.396689, 1.702447, 2.291780",\ + "1.395288, 1.584430, 1.775331, 2.081088, 2.670415"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.039012, 0.039013, 0.039015, 0.039021, 0.039034",\ + "0.090733, 0.090732, 0.090730, 0.090725, 0.090713",\ + "0.180377, 0.180379, 0.180385, 0.180400, 0.180431",\ + "0.429204, 0.429204, 0.429205, 0.429209, 0.429216",\ + "1.091688, 1.091683, 1.091668, 1.091629, 1.091545",\ + "0.039012, 0.039013, 0.039015, 0.039021, 0.039034",\ + "0.090733, 0.090732, 0.090730, 0.090725, 0.090713",\ + "0.180377, 0.180379, 0.180385, 0.180400, 0.180431",\ + "0.429204, 0.429204, 0.429205, 0.429209, 0.429216",\ + "1.091688, 1.091683, 1.091668, 1.091629, 1.091545",\ + "0.039012, 0.039013, 0.039015, 0.039021, 0.039034",\ + "0.090733, 0.090732, 0.090730, 0.090725, 0.090713",\ + "0.180377, 0.180379, 0.180385, 0.180400, 0.180431",\ + "0.429204, 0.429204, 0.429205, 0.429209, 0.429216",\ + "1.091688, 1.091683, 1.091668, 1.091629, 1.091545",\ + "0.039012, 0.039013, 0.039015, 0.039021, 0.039034",\ + "0.090733, 0.090732, 0.090730, 0.090725, 0.090712",\ + "0.180377, 0.180379, 0.180385, 0.180400, 0.180431",\ + "0.429204, 0.429204, 0.429205, 0.429209, 0.429216",\ + "1.091688, 1.091683, 1.091668, 1.091629, 1.091545",\ + "0.039012, 0.039013, 0.039015, 0.039021, 0.039034",\ + "0.090733, 0.090732, 0.090730, 0.090725, 0.090712",\ + "0.180378, 0.180379, 0.180385, 0.180400, 0.180431",\ + "0.429204, 0.429204, 0.429205, 0.429209, 0.429216",\ + "1.091687, 1.091683, 1.091668, 1.091628, 1.091545"); + } + + } /* end of arc clk_ast_rng_i_ast2padmux_o[3]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380001.875000, 380001.937500, 380002.062500, 380002.375000, 380003.250000",\ + "380001.968750, 380002.031250, 380002.156250, 380002.468750, 380003.343750",\ + "380002.062500, 380002.125000, 380002.250000, 380002.562500, 380003.437500",\ + "380002.125000, 380002.187500, 380002.312500, 380002.625000, 380003.500000",\ + "380002.468750, 380002.531250, 380002.656250, 380002.968750, 380003.843750"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189354, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189354, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189365, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189385, 0.392560, 0.950608, 2.441526",\ + "0.073824, 0.189425, 0.393252, 0.950608, 2.441526"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380001.562500, 380001.593750, 380001.656250, 380001.781250, 380002.156250",\ + "380001.656250, 380001.687500, 380001.750000, 380001.875000, 380002.250000",\ + "380001.750000, 380001.781250, 380001.843750, 380001.968750, 380002.343750",\ + "380001.812500, 380001.843750, 380001.906250, 380002.031250, 380002.406250",\ + "380002.156250, 380002.187500, 380002.250000, 380002.375000, 380002.750000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497"); + } + + } /* end of arc clk_ast_tlul_i_ast2padmux_o[3]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.118063, 0.173160, 0.267375, 0.527316, 1.216798",\ + "0.205470, 0.260567, 0.354781, 0.614720, 1.304204",\ + "0.286205, 0.341346, 0.435579, 0.695608, 1.384949",\ + "0.343571, 0.398793, 0.493060, 0.753254, 1.442331",\ + "0.643636, 0.699058, 0.793671, 1.054205, 1.742813"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.055140, 0.149920, 0.315966, 0.770671, 1.992169",\ + "0.055140, 0.149920, 0.315966, 0.770671, 1.992169",\ + "0.055064, 0.149920, 0.315966, 0.770616, 1.992169",\ + "0.054924, 0.149920, 0.315966, 0.770514, 1.992169",\ + "0.054820, 0.149920, 0.315966, 0.770514, 1.988361"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.068977, 0.083624, 0.108789, 0.177707, 0.362145",\ + "0.157440, 0.172093, 0.197279, 0.266195, 0.450612",\ + "0.246166, 0.261189, 0.286407, 0.355291, 0.539679",\ + "0.308361, 0.324424, 0.349591, 0.418444, 0.602842",\ + "0.630702, 0.654723, 0.683267, 0.752219, 0.936438"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.015416, 0.041075, 0.085652, 0.207740, 0.535967",\ + "0.015763, 0.041089, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967"); + } + + } /* end of arc clk_ast_tlul_i_ast2padmux_o[3]_redg_min*/ + + timing () { + related_pin : "fla_obs_i[3]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.111862, 0.178517, 0.294685, 0.611498, 1.461412",\ + "0.196887, 0.263820, 0.381200, 0.697836, 1.546758",\ + "0.280874, 0.348002, 0.465333, 0.783744, 1.631498",\ + "0.419192, 0.490016, 0.607541, 0.927454, 1.774732",\ + "0.629434, 0.713469, 0.835221, 1.155234, 2.004311"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067759, 0.184639, 0.382501, 0.937507, 2.417566",\ + "0.067759, 0.184639, 0.382501, 0.937507, 2.418347",\ + "0.069174, 0.184639, 0.382586, 0.937507, 2.418347",\ + "0.077831, 0.187460, 0.383300, 0.940319, 2.418347",\ + "0.099054, 0.205738, 0.390315, 0.940320, 2.425200"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.103322, 0.134506, 0.187130, 0.329612, 0.708263",\ + "0.188196, 0.219801, 0.272413, 0.414932, 0.793505",\ + "0.281500, 0.317246, 0.369943, 0.512302, 0.890520",\ + "0.433568, 0.478875, 0.537406, 0.680993, 1.058708",\ + "0.668936, 0.733428, 0.809479, 0.962224, 1.340585"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040521, 0.090274, 0.180244, 0.428614, 1.092440",\ + "0.042863, 0.090977, 0.180401, 0.428614, 1.092696",\ + "0.054661, 0.097371, 0.180899, 0.428690, 1.092793",\ + "0.077190, 0.120374, 0.194930, 0.430280, 1.092793",\ + "0.118581, 0.174509, 0.240947, 0.445113, 1.092793"); + } + + } /* end of arc fla_obs_i[3]_ast2padmux_o[3]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "fla_obs_i[3]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.110629, 0.177262, 0.293339, 0.610165, 1.460154",\ + "0.194795, 0.261696, 0.378936, 0.695592, 1.544629",\ + "0.275980, 0.343081, 0.460479, 0.778514, 1.626463",\ + "0.408884, 0.478137, 0.595421, 0.915532, 1.762573",\ + "0.610985, 0.691263, 0.810230, 1.128954, 1.977655"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067834, 0.183634, 0.382402, 0.934951, 2.414331",\ + "0.067834, 0.183634, 0.382402, 0.934951, 2.414331",\ + "0.068631, 0.183634, 0.382540, 0.936478, 2.414331",\ + "0.075251, 0.185541, 0.383090, 0.939701, 2.414331",\ + "0.093347, 0.198994, 0.384563, 0.939701, 2.425563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.077370, 0.108647, 0.161299, 0.303710, 0.682406",\ + "0.166391, 0.197521, 0.250129, 0.392651, 0.771277",\ + "0.253394, 0.288299, 0.340979, 0.483371, 0.861661",\ + "0.395347, 0.439383, 0.496795, 0.640121, 1.017884",\ + "0.615736, 0.679130, 0.754042, 0.905113, 1.283136"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039363, 0.090228, 0.180124, 0.428312, 1.092155",\ + "0.041196, 0.090228, 0.180315, 0.428312, 1.092511",\ + "0.052267, 0.096073, 0.180798, 0.428601, 1.092511",\ + "0.074482, 0.116813, 0.192279, 0.430033, 1.092511",\ + "0.116096, 0.171326, 0.236992, 0.441817, 1.092511"); + } + + } /* end of arc fla_obs_i[3]_ast2padmux_o[3]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[10]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.443642, 0.510546, 0.626985, 0.946654, 1.801858",\ + "0.465905, 0.532810, 0.649248, 0.968917, 1.824121",\ + "0.522299, 0.589203, 0.705642, 1.025311, 1.880515",\ + "0.620162, 0.687066, 0.803505, 1.123173, 1.978378",\ + "1.134534, 1.201443, 1.317885, 1.637554, 2.492753"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\ + "0.073042, 0.188941, 0.391856, 0.949133, 2.441345"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.490585, 0.522017, 0.574725, 0.717078, 1.095675",\ + "0.512119, 0.543551, 0.596259, 0.738612, 1.117209",\ + "0.579305, 0.610737, 0.663445, 0.805798, 1.184395",\ + "0.689604, 0.721035, 0.773743, 0.916096, 1.294693",\ + "1.248357, 1.279789, 1.332497, 1.474850, 1.853447"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090836"); + } + + } /* end of arc obs_ctrl_o[10]_ast2padmux_o[3]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[10]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.412827, 0.479717, 0.596144, 0.915812, 1.771032",\ + "0.433604, 0.500495, 0.616922, 0.936590, 1.791810",\ + "0.491196, 0.558086, 0.674513, 0.994181, 1.849401",\ + "0.589141, 0.656031, 0.772458, 1.092126, 1.947346",\ + "1.077990, 1.144880, 1.261307, 1.580975, 2.436195"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.392762, 0.424174, 0.476820, 0.619235, 0.997878",\ + "0.410167, 0.441580, 0.494226, 0.636641, 1.015284",\ + "0.482737, 0.514149, 0.566795, 0.709210, 1.087853",\ + "0.595371, 0.626784, 0.679430, 0.821845, 1.200488",\ + "1.122399, 1.153812, 1.206458, 1.348872, 1.727516"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687"); + } + + } /* end of arc obs_ctrl_o[10]_ast2padmux_o[3]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[10]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.437382, 0.468814, 0.521522, 0.663875, 1.042472",\ + "0.462451, 0.493883, 0.546591, 0.688944, 1.067541",\ + "0.531672, 0.563103, 0.615812, 0.758164, 1.136761",\ + "0.655903, 0.687335, 0.740043, 0.882396, 1.260993",\ + "1.288504, 1.319936, 1.372644, 1.514997, 1.893594"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090836"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.675759, 0.742664, 0.859102, 1.178771, 2.033976",\ + "0.696234, 0.763138, 0.879577, 1.199246, 2.054450",\ + "0.755094, 0.821998, 0.938437, 1.258106, 2.113310",\ + "0.864334, 0.931238, 1.047677, 1.367346, 2.222550",\ + "1.641748, 1.708657, 1.825099, 2.144769, 2.999968"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\ + "0.073042, 0.188941, 0.391856, 0.949133, 2.441345"); + } + + } /* end of arc obs_ctrl_o[10]_ast2padmux_o[3]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[10]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.262392, 0.293804, 0.346450, 0.488865, 0.867508",\ + "0.286002, 0.317414, 0.370060, 0.512475, 0.891118",\ + "0.357340, 0.388753, 0.441399, 0.583814, 0.962457",\ + "0.477148, 0.508560, 0.561206, 0.703621, 1.082264",\ + "1.022245, 1.053658, 1.106303, 1.248718, 1.627362"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.582342, 0.649232, 0.765660, 1.085328, 1.940547",\ + "0.599034, 0.665924, 0.782351, 1.102020, 1.957239",\ + "0.661428, 0.728319, 0.844746, 1.164414, 2.019634",\ + "0.770818, 0.837708, 0.954135, 1.273803, 2.129023",\ + "1.507966, 1.574856, 1.691283, 2.010951, 2.866171"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330"); + } + + } /* end of arc obs_ctrl_o[10]_ast2padmux_o[3]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[11]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.034927, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.180024, 0.211452, 0.264149, 0.406513, 0.785119",\ + "0.193406, 0.224834, 0.277531, 0.419896, 0.798501",\ + "0.275919, 0.307349, 0.360051, 0.502410, 0.881011",\ + "0.400910, 0.432352, 0.485095, 0.627414, 1.005985",\ + "0.975060, 1.010086, 1.063144, 1.205732, 1.584486"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.034927, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039119, 0.090633, 0.180636, 0.429262, 1.090996",\ + "0.039119, 0.090633, 0.180636, 0.429262, 1.090996",\ + "0.039132, 0.090633, 0.180667, 0.429269, 1.090996",\ + "0.039215, 0.090633, 0.180868, 0.429314, 1.090996",\ + "0.049347, 0.094034, 0.180868, 0.429355, 1.091896"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037147, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.465437, 0.532662, 0.649281, 0.969044, 1.824018",\ + "0.477695, 0.544920, 0.661539, 0.981302, 1.836276",\ + "0.541916, 0.609140, 0.725760, 1.045521, 1.900495",\ + "0.644626, 0.711856, 0.828474, 1.148242, 2.003221",\ + "1.319722, 1.387140, 1.503696, 1.823662, 2.678811"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037147, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073817, 0.189281, 0.392442, 0.950607, 2.441526",\ + "0.073817, 0.189281, 0.392442, 0.950607, 2.441526",\ + "0.073817, 0.189282, 0.392442, 0.950607, 2.441526",\ + "0.073862, 0.189282, 0.392442, 0.950619, 2.441526",\ + "0.075399, 0.189282, 0.392442, 0.951039, 2.441526"); + } + + } /* end of arc obs_ctrl_o[11]_ast2padmux_o[3]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[11]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.030664, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.159139, 0.190553, 0.243202, 0.385613, 0.764254",\ + "0.170514, 0.201928, 0.254577, 0.396989, 0.775629",\ + "0.255576, 0.286993, 0.339652, 0.482053, 0.860686",\ + "0.379908, 0.411340, 0.464049, 0.606401, 0.984998",\ + "0.945167, 0.979651, 1.032663, 1.175209, 1.553933"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.030664, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039020, 0.090609, 0.180397, 0.429208, 1.090831",\ + "0.039020, 0.090609, 0.180397, 0.429208, 1.090831",\ + "0.039042, 0.090609, 0.180449, 0.429220, 1.090831",\ + "0.039144, 0.090609, 0.180675, 0.429276, 1.090831",\ + "0.047820, 0.093501, 0.180675, 0.429352, 1.091629"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.028580, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.461683, 0.528880, 0.645509, 0.965243, 1.820192",\ + "0.470327, 0.537524, 0.654153, 0.973887, 1.828836",\ + "0.538174, 0.605371, 0.721999, 1.041733, 1.896681",\ + "0.640782, 0.707985, 0.824611, 1.144351, 1.999304",\ + "1.312551, 1.379913, 1.496487, 1.816396, 2.671496"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.028580, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073594, 0.189124, 0.392388, 0.950544, 2.441454",\ + "0.073594, 0.189124, 0.392388, 0.950544, 2.441454",\ + "0.073594, 0.189124, 0.392388, 0.950544, 2.441454",\ + "0.073633, 0.189124, 0.392388, 0.950557, 2.441454",\ + "0.074954, 0.189124, 0.392388, 0.950917, 2.441454"); + } + + } /* end of arc obs_ctrl_o[11]_ast2padmux_o[3]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.500858, 0.568082, 0.684702, 1.004464, 1.859437",\ + "0.516623, 0.583848, 0.700467, 1.020230, 1.875203",\ + "0.590734, 0.657958, 0.774578, 1.094340, 1.949314",\ + "0.681946, 0.749171, 0.865790, 1.185553, 2.040526",\ + "1.108576, 1.175805, 1.292423, 1.612190, 2.467167"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073816, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073848, 0.189277, 0.392440, 0.950615, 2.441524"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.275118, 0.306284, 0.358903, 0.501398, 0.880041",\ + "0.290749, 0.321915, 0.374533, 0.517029, 0.895671",\ + "0.363703, 0.394869, 0.447488, 0.589983, 0.968626",\ + "0.474794, 0.505959, 0.558577, 0.701073, 1.079716",\ + "1.013269, 1.044421, 1.097036, 1.239541, 1.618177"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040759, 0.090626, 0.180653, 0.429266, 1.092499",\ + "0.040922, 0.090525, 0.180916, 0.429325, 1.092539"); + } + + } /* end of arc obs_ctrl_o[4]_ast2padmux_o[3]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.337608, 0.404302, 0.520641, 0.837429, 1.687203",\ + "0.349939, 0.416633, 0.532972, 0.849760, 1.699534",\ + "0.408752, 0.475446, 0.591785, 0.908573, 1.758347",\ + "0.496083, 0.562777, 0.679117, 0.995905, 1.845678",\ + "0.949078, 1.015776, 1.132136, 1.448920, 2.298678"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184560, 0.382485, 0.937098, 2.417677",\ + "0.067604, 0.184551, 0.382483, 0.937052, 2.417689"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.209985, 0.241400, 0.294052, 0.436461, 0.815099",\ + "0.221857, 0.253271, 0.305923, 0.448332, 0.826970",\ + "0.304351, 0.335766, 0.388417, 0.530826, 0.909465",\ + "0.409226, 0.440642, 0.493298, 0.635702, 1.014338",\ + "0.909442, 0.940877, 0.993596, 1.135938, 1.514527"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039034, 0.090327, 0.180161, 0.428971, 1.091542",\ + "0.039166, 0.090324, 0.180166, 0.428948, 1.090692"); + } + + } /* end of arc obs_ctrl_o[4]_ast2padmux_o[3]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.287803, 0.318969, 0.371587, 0.514083, 0.892726",\ + "0.303569, 0.334734, 0.387353, 0.529848, 0.908491",\ + "0.378810, 0.409975, 0.462594, 0.605089, 0.983732",\ + "0.473884, 0.505049, 0.557668, 0.700163, 1.078806",\ + "0.918190, 0.949342, 1.001956, 1.144462, 1.523098"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040759, 0.090626, 0.180653, 0.429266, 1.092499",\ + "0.040922, 0.090525, 0.180916, 0.429325, 1.092539"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.376755, 0.443500, 0.560063, 0.876818, 1.726409",\ + "0.392417, 0.459162, 0.575725, 0.892480, 1.742071",\ + "0.467424, 0.534169, 0.650732, 0.967487, 1.817078",\ + "0.562603, 0.629351, 0.745928, 1.062681, 1.912261",\ + "1.006927, 1.073706, 1.190415, 1.507149, 2.356620"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073816, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073848, 0.189277, 0.392440, 0.950615, 2.441524"); + } + + } /* end of arc obs_ctrl_o[4]_ast2padmux_o[3]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.264318, 0.295567, 0.348210, 0.490643, 0.869326",\ + "0.278489, 0.309737, 0.362381, 0.504814, 0.883496",\ + "0.355325, 0.386573, 0.439217, 0.581649, 0.960332",\ + "0.450369, 0.481617, 0.534260, 0.676693, 1.055376",\ + "0.893831, 0.925076, 0.977718, 1.120154, 1.498834"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039034, 0.090327, 0.180161, 0.428971, 1.091542",\ + "0.039166, 0.090324, 0.180166, 0.428948, 1.090692"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.373701, 0.440395, 0.556734, 0.873522, 1.723296",\ + "0.385572, 0.452266, 0.568605, 0.885393, 1.735167",\ + "0.464371, 0.531065, 0.647404, 0.964192, 1.813966",\ + "0.559385, 0.626079, 0.742420, 1.059207, 1.908981",\ + "1.002245, 1.068944, 1.185303, 1.502088, 2.351846"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184560, 0.382485, 0.937098, 2.417677",\ + "0.067604, 0.184551, 0.382483, 0.937052, 2.417689"); + } + + } /* end of arc obs_ctrl_o[4]_ast2padmux_o[3]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.337998, 0.404744, 0.521308, 0.838063, 1.687653",\ + "0.353177, 0.419923, 0.536487, 0.853242, 1.702832",\ + "0.412195, 0.478941, 0.595505, 0.912260, 1.761850",\ + "0.508449, 0.575199, 0.691783, 1.008535, 1.858109",\ + "0.997007, 1.063817, 1.180658, 1.497372, 2.346736"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\ + "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073887, 0.189271, 0.392439, 0.950626, 2.441522",\ + "0.075818, 0.189005, 0.392348, 0.951153, 2.441399"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.272032, 0.303198, 0.355817, 0.498312, 0.876955",\ + "0.289891, 0.321056, 0.373675, 0.516170, 0.894813",\ + "0.360955, 0.392121, 0.444739, 0.587235, 0.965878",\ + "0.471378, 0.502542, 0.555160, 0.697656, 1.076298",\ + "1.004117, 1.035227, 1.087829, 1.230366, 1.608983"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\ + "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\ + "0.040752, 0.090633, 0.180666, 0.429269, 1.092497",\ + "0.040771, 0.090633, 0.180871, 0.429315, 1.092502",\ + "0.049622, 0.094130, 0.180871, 0.429356, 1.092666"); + } + + } /* end of arc obs_ctrl_o[5]_ast2padmux_o[3]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.329221, 0.395915, 0.512254, 0.829041, 1.678816",\ + "0.344592, 0.411286, 0.527624, 0.844412, 1.694187",\ + "0.406780, 0.473474, 0.589813, 0.906601, 1.756375",\ + "0.502234, 0.568932, 0.685288, 1.002073, 1.851833",\ + "0.957622, 1.024367, 1.140929, 1.457685, 2.307276"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067607, 0.184553, 0.382483, 0.937060, 2.417687",\ + "0.067439, 0.184458, 0.382464, 0.936568, 2.417820"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.231492, 0.262740, 0.315383, 0.457816, 0.836499",\ + "0.245351, 0.276600, 0.329243, 0.471676, 0.850359",\ + "0.320124, 0.351372, 0.404016, 0.546449, 0.925131",\ + "0.430166, 0.461410, 0.514053, 0.656489, 1.035169",\ + "0.955028, 0.986237, 1.038869, 1.181331, 1.559995"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039041, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039146, 0.090294, 0.180167, 0.428752, 1.090822",\ + "0.040211, 0.090294, 0.180212, 0.428752, 1.091676"); + } + + } /* end of arc obs_ctrl_o[5]_ast2padmux_o[3]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[5]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.176901, 0.208329, 0.261026, 0.403390, 0.781996",\ + "0.196158, 0.227585, 0.280282, 0.422647, 0.801252",\ + "0.273304, 0.304734, 0.357436, 0.499795, 0.878396",\ + "0.397207, 0.428649, 0.481392, 0.623711, 1.002282",\ + "0.961790, 0.996912, 1.049978, 1.192575, 1.571334"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\ + "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\ + "0.040752, 0.090633, 0.180666, 0.429269, 1.092497",\ + "0.040771, 0.090633, 0.180871, 0.429315, 1.092502",\ + "0.049622, 0.094130, 0.180871, 0.429356, 1.092666"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.455825, 0.523049, 0.639668, 0.959430, 1.814404",\ + "0.468963, 0.536187, 0.652807, 0.972569, 1.827542",\ + "0.531289, 0.598514, 0.715133, 1.034896, 1.889869",\ + "0.640154, 0.707387, 0.824004, 1.143775, 1.998757",\ + "1.332501, 1.399969, 1.516508, 1.836528, 2.691724"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\ + "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073887, 0.189271, 0.392439, 0.950626, 2.441522",\ + "0.075818, 0.189005, 0.392348, 0.951153, 2.441399"); + } + + } /* end of arc obs_ctrl_o[5]_ast2padmux_o[3]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[5]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.155833, 0.187247, 0.239896, 0.382308, 0.760949",\ + "0.173482, 0.204896, 0.257545, 0.399957, 0.778598",\ + "0.252964, 0.284381, 0.337040, 0.479441, 0.858074",\ + "0.376196, 0.407628, 0.460337, 0.602689, 0.981285",\ + "0.931678, 0.966257, 1.019278, 1.161831, 1.540560"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039041, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039146, 0.090294, 0.180167, 0.428752, 1.090822",\ + "0.040211, 0.090294, 0.180212, 0.428752, 1.091676"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.452081, 0.519278, 0.635907, 0.955640, 1.810589",\ + "0.461862, 0.529059, 0.645688, 0.965421, 1.820370",\ + "0.527542, 0.594739, 0.711368, 1.031102, 1.886050",\ + "0.636262, 0.703467, 0.820093, 1.139835, 1.994791",\ + "1.324350, 1.391756, 1.508316, 1.828270, 2.683409"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067607, 0.184553, 0.382483, 0.937060, 2.417687",\ + "0.067439, 0.184458, 0.382464, 0.936568, 2.417820"); + } + + } /* end of arc obs_ctrl_o[5]_ast2padmux_o[3]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[6]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.325984, 0.393209, 0.509828, 0.829592, 1.684567",\ + "0.341732, 0.408957, 0.525576, 0.845340, 1.700314",\ + "0.405621, 0.472847, 0.589466, 0.909229, 1.764204",\ + "0.483984, 0.551208, 0.667827, 0.987590, 1.842564",\ + "0.876566, 0.943791, 1.060410, 1.380173, 2.235147"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189281, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189281, 0.392442, 0.950608, 2.441526"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.207560, 0.238992, 0.291700, 0.434053, 0.812650",\ + "0.223441, 0.254873, 0.307582, 0.449934, 0.828531",\ + "0.292964, 0.324396, 0.377105, 0.519457, 0.898054",\ + "0.382304, 0.413736, 0.466444, 0.608797, 0.987394",\ + "0.808201, 0.839636, 0.892354, 1.034697, 1.413287"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\ + "0.040785, 0.090610, 0.180744, 0.429286, 1.092505"); + } + + } /* end of arc obs_ctrl_o[6]_ast2padmux_o[3]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[6]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.298728, 0.365697, 0.482189, 0.801862, 1.656989",\ + "0.312838, 0.379807, 0.496299, 0.815972, 1.671100",\ + "0.378416, 0.445385, 0.561877, 0.881551, 1.736677",\ + "0.456978, 0.523948, 0.640441, 0.960115, 1.815240",\ + "0.852482, 0.919491, 1.036016, 1.355692, 2.210772"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067586, 0.184541, 0.382481, 0.936998, 2.417704"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.185526, 0.216941, 0.269593, 0.412001, 0.790640",\ + "0.197528, 0.228943, 0.281595, 0.424004, 0.802642",\ + "0.270950, 0.302365, 0.355017, 0.497425, 0.876064",\ + "0.360375, 0.391790, 0.444442, 0.586850, 0.965489",\ + "0.786063, 0.817479, 0.870138, 1.012540, 1.391174"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039039, 0.090322, 0.180169, 0.428938, 1.091513"); + } + + } /* end of arc obs_ctrl_o[6]_ast2padmux_o[3]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[6]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.314064, 0.345229, 0.397848, 0.540343, 0.918986",\ + "0.329859, 0.361025, 0.413644, 0.556139, 0.934782",\ + "0.407724, 0.438890, 0.491508, 0.634004, 1.012646",\ + "0.508778, 0.539944, 0.592562, 0.735058, 1.113701",\ + "0.984655, 1.015818, 1.068436, 1.210933, 1.589574"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\ + "0.040785, 0.090610, 0.180744, 0.429286, 1.092505"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.596327, 0.663552, 0.780171, 1.099935, 1.954909",\ + "0.609131, 0.676356, 0.792975, 1.112739, 1.967713",\ + "0.677113, 0.744339, 0.860958, 1.180721, 2.035696",\ + "0.788810, 0.856034, 0.972654, 1.292416, 2.147390",\ + "1.273667, 1.340892, 1.457511, 1.777274, 2.632248"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189281, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189281, 0.392442, 0.950608, 2.441526"); + } + + } /* end of arc obs_ctrl_o[6]_ast2padmux_o[3]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[6]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.262848, 0.294262, 0.346915, 0.489323, 0.867962",\ + "0.276998, 0.308413, 0.361065, 0.503474, 0.882112",\ + "0.356726, 0.388141, 0.440793, 0.583202, 0.961840",\ + "0.457948, 0.489362, 0.542015, 0.684423, 1.063061",\ + "0.929777, 0.961193, 1.013852, 1.156254, 1.534888"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039039, 0.090322, 0.180169, 0.428938, 1.091513"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.437011, 0.503705, 0.620045, 0.936832, 1.786606",\ + "0.446608, 0.513302, 0.629642, 0.946429, 1.796203",\ + "0.517780, 0.584475, 0.700814, 1.017602, 1.867376",\ + "0.629396, 0.696091, 0.812430, 1.129218, 1.978992",\ + "1.131911, 1.198614, 1.314996, 1.631778, 2.481517"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067586, 0.184541, 0.382481, 0.936998, 2.417704"); + } + + } /* end of arc obs_ctrl_o[6]_ast2padmux_o[3]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[7]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.060518, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.315427, 0.346593, 0.399212, 0.541707, 0.920350",\ + "0.342146, 0.373312, 0.425930, 0.568426, 0.947068",\ + "0.410184, 0.441350, 0.493968, 0.636464, 1.015106",\ + "0.512927, 0.544093, 0.596711, 0.739207, 1.117850",\ + "0.999580, 1.030743, 1.083361, 1.225858, 1.604500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.060518, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180697, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180697, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180697, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180732, 0.429283, 1.092497",\ + "0.042004, 0.091469, 0.180867, 0.429340, 1.092504"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.051005, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.597332, 0.664558, 0.781177, 1.100940, 1.955915",\ + "0.618079, 0.685305, 0.801924, 1.121688, 1.976662",\ + "0.683404, 0.750630, 0.867249, 1.187012, 2.041987",\ + "0.797603, 0.864828, 0.981447, 1.301210, 2.156184",\ + "1.375793, 1.443018, 1.559637, 1.879400, 2.734374"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.051005, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189280, 0.392442, 0.950609, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073823, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073819, 0.189281, 0.392442, 0.950607, 2.441526",\ + "0.073817, 0.189281, 0.392442, 0.950607, 2.441526"); + } + + } /* end of arc obs_ctrl_o[7]_ast2padmux_o[3]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[7]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.049671, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.150722, 0.182137, 0.234789, 0.377197, 0.755836",\ + "0.171205, 0.202620, 0.255272, 0.397681, 0.776319",\ + "0.246518, 0.277932, 0.330585, 0.472993, 0.851631",\ + "0.352324, 0.383738, 0.436391, 0.578799, 0.957437",\ + "0.825559, 0.856975, 0.909634, 1.052036, 1.430670"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.049671, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039038, 0.090323, 0.180168, 0.428941, 1.091519"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040467, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.277343, 0.344312, 0.460804, 0.780477, 1.635605",\ + "0.293355, 0.360323, 0.476815, 0.796489, 1.651616",\ + "0.366113, 0.433085, 0.549579, 0.869253, 1.724376",\ + "0.487008, 0.554003, 0.670516, 0.990192, 1.845287",\ + "1.141953, 1.209132, 1.325766, 1.645481, 2.500414"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040467, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067601, 0.184550, 0.382483, 0.937044, 2.417691"); + } + + } /* end of arc obs_ctrl_o[7]_ast2padmux_o[3]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[8]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.700503, 0.767407, 0.883846, 1.203515, 2.058719",\ + "0.718853, 0.785757, 0.902195, 1.221864, 2.077069",\ + "0.789396, 0.856300, 0.972739, 1.292408, 2.147612",\ + "0.881867, 0.948772, 1.065210, 1.384879, 2.240083",\ + "1.366874, 1.433786, 1.550230, 1.869900, 2.725095"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073043, 0.188945, 0.391861, 0.949146, 2.441348"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.488066, 0.519497, 0.572205, 0.714558, 1.093155",\ + "0.505493, 0.536925, 0.589633, 0.731986, 1.110583",\ + "0.582890, 0.614322, 0.667030, 0.809383, 1.187980",\ + "0.691204, 0.722635, 0.775344, 0.917696, 1.296293",\ + "1.242374, 1.273805, 1.326514, 1.468867, 1.847463"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090836"); + } + + } /* end of arc obs_ctrl_o[8]_ast2padmux_o[3]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[8]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.636502, 0.703393, 0.819820, 1.139488, 1.994708",\ + "0.653118, 0.720008, 0.836435, 1.156103, 2.011323",\ + "0.727539, 0.794429, 0.910857, 1.230525, 2.085744",\ + "0.821960, 0.888850, 1.005277, 1.324945, 2.180165",\ + "1.269718, 1.336608, 1.453035, 1.772703, 2.627923"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.339768, 0.371181, 0.423827, 0.566242, 0.944885",\ + "0.353114, 0.384527, 0.437173, 0.579588, 0.958231",\ + "0.435092, 0.466504, 0.519150, 0.661565, 1.040208",\ + "0.544311, 0.575724, 0.628370, 0.770784, 1.149428",\ + "1.067931, 1.099343, 1.151989, 1.294404, 1.673047"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687"); + } + + } /* end of arc obs_ctrl_o[8]_ast2padmux_o[3]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[8]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.524400, 0.555831, 0.608540, 0.750893, 1.129489",\ + "0.542749, 0.574181, 0.626889, 0.769242, 1.147839",\ + "0.616605, 0.648037, 0.700745, 0.843098, 1.221695",\ + "0.714865, 0.746296, 0.799004, 0.941357, 1.319954",\ + "1.237234, 1.268665, 1.321373, 1.463726, 1.842323"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090836"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.651244, 0.718149, 0.834587, 1.154256, 2.009460",\ + "0.663867, 0.730771, 0.847209, 1.166878, 2.022083",\ + "0.718781, 0.785685, 0.902124, 1.221793, 2.076997",\ + "0.821201, 0.888105, 1.004544, 1.324213, 2.179417",\ + "1.548479, 1.615391, 1.731835, 2.051504, 2.906700"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073043, 0.188945, 0.391861, 0.949146, 2.441348"); + } + + } /* end of arc obs_ctrl_o[8]_ast2padmux_o[3]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[8]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.267796, 0.299208, 0.351854, 0.494269, 0.872912",\ + "0.284541, 0.315954, 0.368600, 0.511015, 0.889658",\ + "0.362798, 0.394211, 0.446856, 0.589271, 0.967914",\ + "0.486677, 0.518090, 0.570736, 0.713151, 1.091794",\ + "1.055266, 1.086678, 1.139324, 1.281739, 1.660382"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.456335, 0.523226, 0.639653, 0.959321, 1.814541",\ + "0.469682, 0.536572, 0.652999, 0.972667, 1.827887",\ + "0.547821, 0.614711, 0.731138, 1.050806, 1.906026",\ + "0.649000, 0.715890, 0.832317, 1.151985, 2.007205",\ + "1.120855, 1.187745, 1.304172, 1.623840, 2.479060"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330"); + } + + } /* end of arc obs_ctrl_o[8]_ast2padmux_o[3]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[9]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.712314, 0.779218, 0.895657, 1.215326, 2.070530",\ + "0.730867, 0.797771, 0.914210, 1.233879, 2.089083",\ + "0.803565, 0.870469, 0.986908, 1.306577, 2.161781",\ + "0.898790, 0.965694, 1.082133, 1.401802, 2.257006",\ + "1.358120, 1.425029, 1.541471, 1.861141, 2.716340"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073041, 0.188941, 0.391855, 0.949133, 2.441345"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.494441, 0.525873, 0.578581, 0.720934, 1.099531",\ + "0.511983, 0.543415, 0.596123, 0.738476, 1.117073",\ + "0.589312, 0.620744, 0.673452, 0.815805, 1.194402",\ + "0.698758, 0.730189, 0.782897, 0.925250, 1.303847",\ + "1.229663, 1.261095, 1.313803, 1.456156, 1.834753"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090836"); + } + + } /* end of arc obs_ctrl_o[9]_ast2padmux_o[3]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[9]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.668630, 0.735520, 0.851947, 1.171615, 2.026835",\ + "0.685451, 0.752341, 0.868768, 1.188436, 2.043656",\ + "0.759882, 0.826773, 0.943200, 1.262868, 2.118088",\ + "0.855138, 0.922028, 1.038455, 1.358123, 2.213343",\ + "1.307789, 1.374679, 1.491106, 1.810774, 2.665994"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.361699, 0.393111, 0.445757, 0.588172, 0.966815",\ + "0.375155, 0.406568, 0.459214, 0.601628, 0.980272",\ + "0.456576, 0.487988, 0.540634, 0.683049, 1.061692",\ + "0.566550, 0.597963, 0.650609, 0.793024, 1.171667",\ + "1.091986, 1.123399, 1.176044, 1.318459, 1.697102"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687"); + } + + } /* end of arc obs_ctrl_o[9]_ast2padmux_o[3]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[9]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.528266, 0.559698, 0.612406, 0.754759, 1.133356",\ + "0.546819, 0.578250, 0.630959, 0.773312, 1.151908",\ + "0.620877, 0.652309, 0.705017, 0.847370, 1.225967",\ + "0.719978, 0.751410, 0.804118, 0.946471, 1.325068",\ + "1.192613, 1.224045, 1.276753, 1.419106, 1.797703"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090836"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.606303, 0.673207, 0.789646, 1.109315, 1.964519",\ + "0.618992, 0.685897, 0.802335, 1.122004, 1.977208",\ + "0.673763, 0.740668, 0.857106, 1.176775, 2.031980",\ + "0.776802, 0.843707, 0.960145, 1.279814, 2.135018",\ + "1.483718, 1.550627, 1.667069, 1.986738, 2.841937"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073041, 0.188941, 0.391855, 0.949133, 2.441345"); + } + + } /* end of arc obs_ctrl_o[9]_ast2padmux_o[3]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[9]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.262699, 0.294112, 0.346758, 0.489173, 0.867816",\ + "0.279513, 0.310926, 0.363572, 0.505987, 0.884630",\ + "0.357852, 0.389264, 0.441910, 0.584325, 0.962968",\ + "0.480383, 0.511796, 0.564441, 0.706856, 1.085500",\ + "1.037548, 1.068961, 1.121607, 1.264022, 1.642665"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.463612, 0.530502, 0.646929, 0.966597, 1.821817",\ + "0.477068, 0.543958, 0.660386, 0.980054, 1.835274",\ + "0.555357, 0.622247, 0.738674, 1.058342, 1.913562",\ + "0.655033, 0.721923, 0.838350, 1.158018, 2.013238",\ + "1.119877, 1.186768, 1.303195, 1.622863, 2.478083"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330"); + } + + } /* end of arc obs_ctrl_o[9]_ast2padmux_o[3]_inv_min*/ + + timing () { + related_pin : "otm_obs_i[3]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.123879, 0.190820, 0.307288, 0.626960, 1.482121",\ + "0.210891, 0.277978, 0.394567, 0.714249, 1.569235",\ + "0.301781, 0.369068, 0.485667, 0.805496, 1.660526",\ + "0.453978, 0.523120, 0.640034, 0.960158, 1.815427",\ + "0.695902, 0.774527, 0.893732, 1.214148, 2.069560"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073065, 0.188997, 0.391936, 0.949305, 2.441374",\ + "0.073175, 0.189249, 0.392304, 0.950092, 2.441498",\ + "0.074330, 0.189249, 0.392418, 0.950747, 2.441498",\ + "0.079436, 0.191164, 0.392505, 0.951076, 2.441498",\ + "0.098084, 0.204137, 0.393542, 0.951076, 2.441498"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.114293, 0.145721, 0.198417, 0.340782, 0.719388",\ + "0.205394, 0.236828, 0.289545, 0.431889, 0.810480",\ + "0.309904, 0.342065, 0.394885, 0.537244, 0.915841",\ + "0.501618, 0.536979, 0.590065, 0.732680, 1.111452",\ + "0.825607, 0.870622, 0.930343, 1.075147, 1.454209"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039117, 0.090634, 0.180632, 0.429261, 1.091005",\ + "0.039161, 0.090634, 0.180739, 0.429285, 1.091005",\ + "0.041267, 0.091212, 0.180891, 0.429338, 1.091005",\ + "0.050293, 0.094364, 0.180891, 0.429357, 1.092061",\ + "0.068556, 0.114740, 0.192215, 0.429716, 1.093122"); + } + + } /* end of arc otm_obs_i[3]_ast2padmux_o[3]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "otm_obs_i[3]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.120559, 0.187489, 0.303948, 0.623619, 1.478793",\ + "0.205712, 0.272774, 0.389342, 0.709022, 1.564038",\ + "0.292652, 0.359907, 0.476516, 0.796311, 1.651312",\ + "0.437434, 0.505450, 0.622092, 0.942182, 1.797434",\ + "0.662107, 0.738115, 0.856688, 1.177023, 2.032395"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073057, 0.188977, 0.391908, 0.949245, 2.441364",\ + "0.073156, 0.189206, 0.392241, 0.949956, 2.441378",\ + "0.074065, 0.189247, 0.392382, 0.950255, 2.441378",\ + "0.077223, 0.189624, 0.392382, 0.950255, 2.441378",\ + "0.092938, 0.200557, 0.393255, 0.950255, 2.441468"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.094368, 0.125782, 0.178430, 0.320842, 0.699483",\ + "0.188259, 0.219683, 0.272369, 0.414744, 0.793358",\ + "0.291365, 0.323244, 0.376040, 0.518376, 0.896959",\ + "0.474009, 0.509208, 0.562280, 0.704883, 1.083646",\ + "0.777508, 0.822171, 0.881623, 1.026340, 1.405392"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039018, 0.090654, 0.180392, 0.429207, 1.090346",\ + "0.039096, 0.090654, 0.180581, 0.429249, 1.090346",\ + "0.040472, 0.090934, 0.180608, 0.429337, 1.090346",\ + "0.049836, 0.094205, 0.180608, 0.429356, 1.091981",\ + "0.067933, 0.113945, 0.191732, 0.429701, 1.093101"); + } + + } /* end of arc otm_obs_i[3]_ast2padmux_o[3]_una_min*/ + + timing () { + related_pin : "otp_obs_i[3]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.122660, 0.189370, 0.305783, 0.622560, 1.472274",\ + "0.209824, 0.276743, 0.394059, 0.710704, 1.559679",\ + "0.301920, 0.369023, 0.486415, 0.804486, 1.652417",\ + "0.455547, 0.524976, 0.642287, 0.962376, 1.809444",\ + "0.699992, 0.780922, 0.900058, 1.218756, 2.067549"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067561, 0.184527, 0.382478, 0.936925, 2.417724",\ + "0.067561, 0.184527, 0.382478, 0.936925, 2.418306",\ + "0.068683, 0.184527, 0.382544, 0.936925, 2.418306",\ + "0.075540, 0.185756, 0.383113, 0.940410, 2.418306",\ + "0.094401, 0.199857, 0.384817, 0.940410, 2.426093"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.114764, 0.145947, 0.198571, 0.341053, 0.719705",\ + "0.205629, 0.236785, 0.289401, 0.431904, 0.810542",\ + "0.310076, 0.342571, 0.395201, 0.537686, 0.916183",\ + "0.500896, 0.538360, 0.591093, 0.733386, 1.111456",\ + "0.820213, 0.870292, 0.933027, 1.077593, 1.455130"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040532, 0.090273, 0.180246, 0.428609, 1.092443",\ + "0.040870, 0.090273, 0.180281, 0.428609, 1.092443",\ + "0.045400, 0.092351, 0.180508, 0.428609, 1.092443",\ + "0.059558, 0.100025, 0.181106, 0.428872, 1.092443",\ + "0.087354, 0.133744, 0.204884, 0.431205, 1.092443"); + } + + } /* end of arc otp_obs_i[3]_ast2padmux_o[3]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "otp_obs_i[3]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.119334, 0.186028, 0.302368, 0.619155, 1.468929",\ + "0.204833, 0.271716, 0.388876, 0.705544, 1.554647",\ + "0.293319, 0.360401, 0.477846, 0.795625, 1.643707",\ + "0.440314, 0.508488, 0.625608, 0.945855, 1.792734",\ + "0.667813, 0.745674, 0.864272, 1.183300, 2.031636"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.183691, 0.382409, 0.935142, 2.413233",\ + "0.067620, 0.183691, 0.382409, 0.935142, 2.413233",\ + "0.068262, 0.183691, 0.382508, 0.936031, 2.413233",\ + "0.073482, 0.184226, 0.382946, 0.939859, 2.413233",\ + "0.089380, 0.196045, 0.384240, 0.939859, 2.423100"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.094521, 0.125776, 0.178422, 0.320849, 0.699535",\ + "0.188239, 0.219444, 0.272075, 0.414540, 0.793202",\ + "0.291550, 0.323577, 0.376197, 0.518700, 0.897237",\ + "0.473699, 0.510899, 0.563627, 0.705929, 1.084022",\ + "0.773733, 0.823401, 0.885774, 1.030256, 1.407808"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039633, 0.090291, 0.180152, 0.428296, 1.092222",\ + "0.040262, 0.090291, 0.180217, 0.428296, 1.092377",\ + "0.044064, 0.091627, 0.180452, 0.428296, 1.092425",\ + "0.058805, 0.099616, 0.181075, 0.428844, 1.092425",\ + "0.086478, 0.132591, 0.204027, 0.431125, 1.092425"); + } + + } /* end of arc otp_obs_i[3]_ast2padmux_o[3]_una_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "379999.875000, 379999.937500, 380000.062500, 380000.375000, 380001.218750",\ + "379999.968750, 380000.031250, 380000.156250, 380000.468750, 380001.312500",\ + "380000.062500, 380000.125000, 380000.250000, 380000.562500, 380001.406250",\ + "380000.218750, 380000.281250, 380000.406250, 380000.718750, 380001.562500",\ + "380000.468750, 380000.531250, 380000.656250, 380000.968750, 380001.812500"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380001.468750, 380001.500000, 380001.562500, 380001.687500, 380002.062500",\ + "380001.562500, 380001.593750, 380001.656250, 380001.781250, 380002.156250",\ + "380001.687500, 380001.718750, 380001.781250, 380001.906250, 380002.281250",\ + "380001.875000, 380001.906250, 380001.968750, 380002.093750, 380002.468750",\ + "380002.187500, 380002.218750, 380002.281250, 380002.406250, 380002.781250"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497"); + } + + } /* end of arc padmux2ast_i[4]_ast2padmux_o[3]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "379999.843750, 379999.906250, 380000.031250, 380000.343750, 380001.187500",\ + "379999.937500, 380000.000000, 380000.125000, 380000.437500, 380001.281250",\ + "380000.000000, 380000.062500, 380000.187500, 380000.500000, 380001.343750",\ + "380000.156250, 380000.218750, 380000.343750, 380000.656250, 380001.500000",\ + "380000.375000, 380000.437500, 380000.562500, 380000.875000, 380001.718750"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380001.375000, 380001.406250, 380001.437500, 380001.593750, 380001.968750",\ + "380001.468750, 380001.500000, 380001.531250, 380001.687500, 380002.062500",\ + "380001.562500, 380001.593750, 380001.625000, 380001.781250, 380002.156250",\ + "380001.750000, 380001.781250, 380001.812500, 380001.968750, 380002.343750",\ + "380002.000000, 380002.031250, 380002.062500, 380002.218750, 380002.593750"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967"); + } + + } /* end of arc padmux2ast_i[4]_ast2padmux_o[3]_una_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380000.312500, 380000.312500, 380000.343750, 380000.406250, 380000.593750",\ + "380000.406250, 380000.406250, 380000.437500, 380000.500000, 380000.687500",\ + "380000.500000, 380000.500000, 380000.531250, 380000.593750, 380000.781250",\ + "380000.656250, 380000.656250, 380000.687500, 380000.750000, 380000.937500",\ + "380000.906250, 380000.906250, 380000.937500, 380001.000000, 380001.187500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380001.781250, 380001.843750, 380001.968750, 380002.281250, 380003.156250",\ + "380001.875000, 380001.937500, 380002.062500, 380002.375000, 380003.250000",\ + "380002.000000, 380002.062500, 380002.187500, 380002.500000, 380003.375000",\ + "380002.187500, 380002.250000, 380002.375000, 380002.687500, 380003.562500",\ + "380002.500000, 380002.562500, 380002.687500, 380003.000000, 380003.875000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526"); + } + + } /* end of arc padmux2ast_i[4]_ast2padmux_o[3]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380000.312500, 380000.312500, 380000.343750, 380000.406250, 380000.593750",\ + "380000.406250, 380000.406250, 380000.437500, 380000.500000, 380000.687500",\ + "380000.468750, 380000.468750, 380000.500000, 380000.562500, 380000.750000",\ + "380000.625000, 380000.625000, 380000.656250, 380000.718750, 380000.906250",\ + "380000.843750, 380000.843750, 380000.875000, 380000.937500, 380001.125000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380001.781250, 380001.812500, 380001.906250, 380002.187500, 380002.875000",\ + "380001.875000, 380001.906250, 380002.000000, 380002.281250, 380002.968750",\ + "380001.968750, 380002.000000, 380002.093750, 380002.375000, 380003.062500",\ + "380002.156250, 380002.187500, 380002.281250, 380002.562500, 380003.250000",\ + "380002.406250, 380002.437500, 380002.531250, 380002.812500, 380003.500000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169"); + } + + } /* end of arc padmux2ast_i[4]_ast2padmux_o[3]_inv_min*/ + +} /* end of pin ast2padmux_o[3] */ + +pin("ast2padmux_o[2]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.028584 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : ast2padmux_o[2]; + timing () { + related_pin : "clk_ast_rng_i" ; + related_output_pin : "rng_b_o[1]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.257031, 0.528778, 0.797030, 1.242767, 2.134242",\ + "0.323932, 0.595681, 0.863940, 1.309691, 2.201193",\ + "0.440368, 0.712118, 0.980382, 1.426145, 2.317669",\ + "0.760037, 1.031787, 1.300052, 1.745815, 2.637342",\ + "1.615245, 1.886993, 2.155250, 2.600997, 3.492491",\ + "0.315617, 0.587294, 0.855812, 1.300474, 2.190349",\ + "0.382518, 0.654197, 0.922722, 1.367397, 2.257300",\ + "0.498954, 0.770634, 1.039164, 1.483851, 2.373776",\ + "0.818623, 1.090303, 1.358834, 1.803522, 2.693449",\ + "1.673831, 1.945509, 2.214032, 2.658703, 3.548597",\ + "0.460207, 0.733101, 0.999707, 1.444229, 2.334082",\ + "0.527108, 0.800004, 1.066617, 1.511152, 2.401032",\ + "0.643544, 0.916442, 1.183060, 1.627606, 2.517509",\ + "0.963213, 1.236110, 1.502729, 1.947277, 2.837182",\ + "1.818421, 2.091316, 2.357927, 2.802459, 3.692330",\ + "0.496168, 0.770865, 1.036627, 1.481020, 2.370640",\ + "0.563069, 0.837768, 1.103536, 1.547944, 2.437591",\ + "0.679505, 0.954206, 1.219979, 1.664398, 2.554067",\ + "0.999174, 1.273875, 1.539648, 1.984068, 2.873740",\ + "1.854382, 2.129080, 2.394846, 2.839250, 3.728889",\ + "0.825262, 1.134787, 1.388262, 1.830277, 2.716096",\ + "0.892164, 1.201690, 1.455172, 1.897201, 2.783047",\ + "1.008600, 1.318128, 1.571615, 2.013655, 2.899523",\ + "1.328269, 1.637797, 1.891284, 2.333325, 3.219196",\ + "2.183476, 2.493002, 2.746482, 3.188507, 4.074345"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.073036, 0.073037, 0.073042, 0.073052, 0.073073",\ + "0.188928, 0.188931, 0.188942, 0.188966, 0.189013",\ + "0.391836, 0.391841, 0.391857, 0.391892, 0.391961",\ + "0.949092, 0.949101, 0.949136, 0.949210, 0.949357",\ + "2.441339, 2.441340, 2.441346, 2.441358, 2.441383",\ + "0.073036, 0.073037, 0.073042, 0.073052, 0.073073",\ + "0.188928, 0.188931, 0.188942, 0.188966, 0.189013",\ + "0.391836, 0.391841, 0.391857, 0.391892, 0.391961",\ + "0.949092, 0.949101, 0.949136, 0.949210, 0.949357",\ + "2.441339, 2.441340, 2.441346, 2.441358, 2.441383",\ + "0.073036, 0.073037, 0.073042, 0.073052, 0.073073",\ + "0.188928, 0.188931, 0.188942, 0.188966, 0.189013",\ + "0.391836, 0.391841, 0.391857, 0.391892, 0.391961",\ + "0.949092, 0.949102, 0.949136, 0.949210, 0.949357",\ + "2.441339, 2.441340, 2.441346, 2.441358, 2.441383",\ + "0.073036, 0.073037, 0.073042, 0.073052, 0.073073",\ + "0.188928, 0.188931, 0.188942, 0.188966, 0.189013",\ + "0.391836, 0.391841, 0.391857, 0.391892, 0.391961",\ + "0.949092, 0.949102, 0.949136, 0.949210, 0.949357",\ + "2.441339, 2.441340, 2.441346, 2.441358, 2.441383",\ + "0.073036, 0.073038, 0.073042, 0.073052, 0.073073",\ + "0.188928, 0.188932, 0.188943, 0.188966, 0.189013",\ + "0.391836, 0.391843, 0.391858, 0.391892, 0.391961",\ + "0.949092, 0.949105, 0.949137, 0.949210, 0.949357",\ + "2.441339, 2.441341, 2.441346, 2.441358, 2.441383"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.308725, 0.491796, 0.685627, 0.996163, 1.596700",\ + "0.340157, 0.523228, 0.717058, 1.027595, 1.628132",\ + "0.392865, 0.575936, 0.769767, 1.080304, 1.680844",\ + "0.535218, 0.718289, 0.912119, 1.222656, 1.823194",\ + "0.913815, 1.096886, 1.290716, 1.601252, 2.201788",\ + "0.368637, 0.551695, 0.745581, 1.055944, 1.656317",\ + "0.400068, 0.583126, 0.777012, 1.087376, 1.687749",\ + "0.452777, 0.635835, 0.829721, 1.140085, 1.740461",\ + "0.595130, 0.778187, 0.972073, 1.282437, 1.882811",\ + "0.973727, 1.156784, 1.350670, 1.661033, 2.261405",\ + "0.501379, 0.683946, 0.877464, 1.187801, 1.788124",\ + "0.532811, 0.715378, 0.908895, 1.219233, 1.819557",\ + "0.585519, 0.768086, 0.961603, 1.271942, 1.872268",\ + "0.727872, 0.910439, 1.103956, 1.414294, 2.014618",\ + "1.106469, 1.289036, 1.482553, 1.792891, 2.393212",\ + "0.534516, 0.717073, 0.910588, 1.220754, 1.820733",\ + "0.565947, 0.748505, 0.942020, 1.252186, 1.852165",\ + "0.618656, 0.801213, 0.994728, 1.304895, 1.904876",\ + "0.761009, 0.943566, 1.137081, 1.447247, 2.047226",\ + "1.139605, 1.322163, 1.515678, 1.825843, 2.425821",\ + "0.835592, 1.022294, 1.214223, 1.523770, 2.122581",\ + "0.867023, 1.053726, 1.245655, 1.555202, 2.154014",\ + "0.919731, 1.106434, 1.298363, 1.607911, 2.206725",\ + "1.062084, 1.248787, 1.440716, 1.750263, 2.349075",\ + "1.440681, 1.627384, 1.819313, 2.128859, 2.727669"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.039143, 0.039143, 0.039143, 0.039145, 0.039150",\ + "0.090610, 0.090610, 0.090610, 0.090608, 0.090604",\ + "0.180695, 0.180695, 0.180695, 0.180700, 0.180710",\ + "0.429275, 0.429275, 0.429275, 0.429276, 0.429279",\ + "1.090837, 1.090837, 1.090837, 1.090825, 1.090796",\ + "0.039143, 0.039143, 0.039143, 0.039145, 0.039150",\ + "0.090610, 0.090610, 0.090610, 0.090608, 0.090604",\ + "0.180695, 0.180695, 0.180695, 0.180700, 0.180710",\ + "0.429275, 0.429275, 0.429275, 0.429276, 0.429279",\ + "1.090837, 1.090837, 1.090837, 1.090825, 1.090796",\ + "0.039143, 0.039143, 0.039143, 0.039145, 0.039150",\ + "0.090610, 0.090610, 0.090610, 0.090608, 0.090604",\ + "0.180695, 0.180695, 0.180695, 0.180700, 0.180710",\ + "0.429275, 0.429275, 0.429275, 0.429276, 0.429279",\ + "1.090837, 1.090837, 1.090837, 1.090825, 1.090796",\ + "0.039143, 0.039143, 0.039143, 0.039145, 0.039150",\ + "0.090610, 0.090610, 0.090610, 0.090608, 0.090604",\ + "0.180695, 0.180695, 0.180695, 0.180700, 0.180710",\ + "0.429275, 0.429275, 0.429275, 0.429276, 0.429279",\ + "1.090837, 1.090837, 1.090837, 1.090825, 1.090796",\ + "0.039143, 0.039143, 0.039143, 0.039145, 0.039150",\ + "0.090610, 0.090610, 0.090610, 0.090608, 0.090604",\ + "0.180695, 0.180695, 0.180695, 0.180700, 0.180710",\ + "0.429275, 0.429275, 0.429275, 0.429276, 0.429279",\ + "1.090837, 1.090837, 1.090837, 1.090825, 1.090796"); + } + + } /* end of arc clk_ast_rng_i_ast2padmux_o[2]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_rng_i" ; + related_output_pin : "rng_b_o[1]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.252558, 0.520745, 0.784515, 1.222569, 2.097608",\ + "0.319449, 0.587637, 0.851411, 1.289475, 2.164534",\ + "0.435876, 0.704065, 0.967843, 1.405915, 2.280990",\ + "0.755544, 1.023733, 1.287511, 1.725584, 2.600661",\ + "1.610764, 1.878952, 2.142725, 2.580786, 3.455839",\ + "0.311120, 0.579252, 0.843280, 1.280275, 2.153714",\ + "0.378011, 0.646143, 0.910176, 1.347182, 2.220640",\ + "0.494438, 0.762572, 1.026608, 1.463622, 2.337097",\ + "0.814106, 1.082240, 1.346276, 1.783291, 2.656767",\ + "1.669326, 1.937458, 2.201490, 2.638493, 3.511946",\ + "0.455460, 0.724999, 0.987167, 1.424079, 2.297447",\ + "0.522351, 0.791891, 1.054064, 1.490985, 2.364373",\ + "0.638778, 0.908319, 1.170496, 1.607426, 2.480830",\ + "0.958446, 1.227987, 1.490164, 1.927095, 2.800500",\ + "1.813666, 2.083206, 2.345378, 2.782297, 3.655679",\ + "0.491341, 0.762735, 1.024086, 1.460950, 2.334005",\ + "0.558231, 0.829626, 1.090982, 1.527856, 2.400931",\ + "0.674659, 0.946054, 1.207414, 1.644296, 2.517388",\ + "0.994327, 1.265722, 1.527082, 1.963966, 2.837059",\ + "1.849546, 2.120941, 2.382296, 2.819168, 3.692237",\ + "0.819555, 1.126080, 1.375645, 1.810251, 2.679461",\ + "0.886446, 1.192972, 1.442542, 1.877157, 2.746387",\ + "1.002873, 1.309400, 1.558974, 1.993597, 2.862844",\ + "1.322541, 1.629068, 1.878642, 2.313266, 3.182515",\ + "2.177761, 2.484287, 2.733856, 3.168468, 4.037693"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.073031, 0.073031, 0.073033, 0.073040, 0.073054",\ + "0.188915, 0.188915, 0.188919, 0.188937, 0.188971",\ + "0.391815, 0.391816, 0.391824, 0.391849, 0.391899",\ + "0.949014, 0.949028, 0.949065, 0.949118, 0.949226",\ + "2.441330, 2.441330, 2.441334, 2.441343, 2.441361",\ + "0.073031, 0.073031, 0.073033, 0.073040, 0.073054",\ + "0.188915, 0.188915, 0.188919, 0.188937, 0.188971",\ + "0.391815, 0.391816, 0.391824, 0.391849, 0.391899",\ + "0.949014, 0.949028, 0.949065, 0.949118, 0.949226",\ + "2.441330, 2.441330, 2.441334, 2.441343, 2.441361",\ + "0.073031, 0.073031, 0.073033, 0.073040, 0.073054",\ + "0.188915, 0.188915, 0.188920, 0.188937, 0.188971",\ + "0.391815, 0.391816, 0.391824, 0.391849, 0.391899",\ + "0.949014, 0.949029, 0.949065, 0.949118, 0.949226",\ + "2.441330, 2.441330, 2.441334, 2.441343, 2.441361",\ + "0.073031, 0.073031, 0.073033, 0.073040, 0.073054",\ + "0.188915, 0.188915, 0.188920, 0.188937, 0.188971",\ + "0.391815, 0.391816, 0.391824, 0.391849, 0.391899",\ + "0.949014, 0.949029, 0.949065, 0.949119, 0.949226",\ + "2.441330, 2.441330, 2.441334, 2.441343, 2.441361",\ + "0.073031, 0.073031, 0.073033, 0.073040, 0.073054",\ + "0.188915, 0.188915, 0.188920, 0.188937, 0.188971",\ + "0.391816, 0.391816, 0.391824, 0.391849, 0.391899",\ + "0.949014, 0.949034, 0.949065, 0.949119, 0.949226",\ + "2.441330, 2.441331, 2.441334, 2.441343, 2.441361"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.262934, 0.448489, 0.641595, 0.948064, 1.538713",\ + "0.294346, 0.479902, 0.673008, 0.979478, 1.570129",\ + "0.346992, 0.532548, 0.725656, 1.032128, 1.622785",\ + "0.489407, 0.674962, 0.868069, 1.174539, 1.765190",\ + "0.868050, 1.053605, 1.246711, 1.553179, 2.143825",\ + "0.322845, 0.508317, 0.701440, 1.007833, 1.598330",\ + "0.354258, 0.539729, 0.732853, 1.039247, 1.629746",\ + "0.406904, 0.592376, 0.785500, 1.091897, 1.682402",\ + "0.549319, 0.734790, 0.927914, 1.234307, 1.824806",\ + "0.927962, 1.113433, 1.306556, 1.612947, 2.203442",\ + "0.455621, 0.640568, 0.833323, 1.139690, 1.730137",\ + "0.487034, 0.671981, 0.864736, 1.171104, 1.761553",\ + "0.539679, 0.724627, 0.917383, 1.223754, 1.814209",\ + "0.682094, 0.867041, 1.059797, 1.366165, 1.956614",\ + "1.060737, 1.245684, 1.438439, 1.744805, 2.335249",\ + "0.488779, 0.673866, 0.866553, 1.172770, 1.762998",\ + "0.520192, 0.705279, 0.897966, 1.204184, 1.794413",\ + "0.572837, 0.757925, 0.950613, 1.256834, 1.847070",\ + "0.715252, 0.900339, 1.093027, 1.399244, 1.989474",\ + "1.093896, 1.278982, 1.471669, 1.777884, 2.368110",\ + "0.790171, 0.979313, 1.170216, 1.475973, 2.065303",\ + "0.821584, 1.010726, 1.201629, 1.507387, 2.096719",\ + "0.874230, 1.063372, 1.254276, 1.560037, 2.149375",\ + "1.016645, 1.205787, 1.396689, 1.702447, 2.291780",\ + "1.395288, 1.584430, 1.775331, 2.081088, 2.670415"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.039012, 0.039013, 0.039015, 0.039021, 0.039034",\ + "0.090733, 0.090732, 0.090730, 0.090725, 0.090713",\ + "0.180377, 0.180379, 0.180385, 0.180400, 0.180431",\ + "0.429204, 0.429204, 0.429205, 0.429209, 0.429216",\ + "1.091688, 1.091683, 1.091668, 1.091629, 1.091545",\ + "0.039012, 0.039013, 0.039015, 0.039021, 0.039034",\ + "0.090733, 0.090732, 0.090730, 0.090725, 0.090713",\ + "0.180377, 0.180379, 0.180385, 0.180400, 0.180431",\ + "0.429204, 0.429204, 0.429205, 0.429209, 0.429216",\ + "1.091688, 1.091683, 1.091668, 1.091629, 1.091545",\ + "0.039012, 0.039013, 0.039015, 0.039021, 0.039034",\ + "0.090733, 0.090732, 0.090730, 0.090725, 0.090713",\ + "0.180377, 0.180379, 0.180385, 0.180400, 0.180431",\ + "0.429204, 0.429204, 0.429205, 0.429209, 0.429216",\ + "1.091688, 1.091683, 1.091668, 1.091629, 1.091545",\ + "0.039012, 0.039013, 0.039015, 0.039021, 0.039034",\ + "0.090733, 0.090732, 0.090730, 0.090725, 0.090712",\ + "0.180377, 0.180379, 0.180385, 0.180400, 0.180431",\ + "0.429204, 0.429204, 0.429205, 0.429209, 0.429216",\ + "1.091688, 1.091683, 1.091668, 1.091629, 1.091545",\ + "0.039012, 0.039013, 0.039015, 0.039021, 0.039034",\ + "0.090733, 0.090732, 0.090730, 0.090725, 0.090712",\ + "0.180378, 0.180379, 0.180385, 0.180400, 0.180431",\ + "0.429204, 0.429204, 0.429205, 0.429209, 0.429216",\ + "1.091687, 1.091683, 1.091668, 1.091628, 1.091545"); + } + + } /* end of arc clk_ast_rng_i_ast2padmux_o[2]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380001.875000, 380001.937500, 380002.062500, 380002.375000, 380003.250000",\ + "380001.968750, 380002.031250, 380002.156250, 380002.468750, 380003.343750",\ + "380002.062500, 380002.125000, 380002.250000, 380002.562500, 380003.437500",\ + "380002.125000, 380002.187500, 380002.312500, 380002.625000, 380003.500000",\ + "380002.468750, 380002.531250, 380002.656250, 380002.968750, 380003.843750"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189354, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189354, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189365, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189385, 0.392560, 0.950608, 2.441526",\ + "0.073824, 0.189425, 0.393252, 0.950608, 2.441526"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380000.437500, 380000.437500, 380000.468750, 380000.531250, 380000.718750",\ + "380000.531250, 380000.531250, 380000.562500, 380000.625000, 380000.812500",\ + "380000.593750, 380000.593750, 380000.625000, 380000.687500, 380000.875000",\ + "380000.656250, 380000.656250, 380000.687500, 380000.750000, 380000.937500",\ + "380000.968750, 380000.968750, 380001.000000, 380001.062500, 380001.250000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497"); + } + + } /* end of arc clk_ast_tlul_i_ast2padmux_o[2]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.118063, 0.173160, 0.267375, 0.527316, 1.216798",\ + "0.205470, 0.260567, 0.354781, 0.614720, 1.304204",\ + "0.286205, 0.341346, 0.435579, 0.695608, 1.384949",\ + "0.343571, 0.398793, 0.493060, 0.753254, 1.442331",\ + "0.643636, 0.699058, 0.793671, 1.054205, 1.742813"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.055140, 0.149920, 0.315966, 0.770671, 1.992169",\ + "0.055140, 0.149920, 0.315966, 0.770671, 1.992169",\ + "0.055064, 0.149920, 0.315966, 0.770616, 1.992169",\ + "0.054924, 0.149920, 0.315966, 0.770514, 1.992169",\ + "0.054820, 0.149920, 0.315966, 0.770514, 1.988361"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.068977, 0.083624, 0.108789, 0.177707, 0.362145",\ + "0.157440, 0.172093, 0.197279, 0.266195, 0.450612",\ + "0.246166, 0.261189, 0.286407, 0.355291, 0.539679",\ + "0.308361, 0.324424, 0.349591, 0.418444, 0.602842",\ + "0.630702, 0.654723, 0.683267, 0.752219, 0.936438"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.015416, 0.041075, 0.085652, 0.207740, 0.535967",\ + "0.015763, 0.041089, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967"); + } + + } /* end of arc clk_ast_tlul_i_ast2padmux_o[2]_redg_min*/ + + timing () { + related_pin : "fla_obs_i[2]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.111862, 0.178517, 0.294685, 0.611498, 1.461412",\ + "0.196887, 0.263820, 0.381200, 0.697836, 1.546758",\ + "0.280874, 0.348002, 0.465333, 0.783744, 1.631498",\ + "0.419192, 0.490016, 0.607541, 0.927454, 1.774732",\ + "0.629434, 0.713469, 0.835221, 1.155234, 2.004311"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067759, 0.184639, 0.382501, 0.937507, 2.417566",\ + "0.067759, 0.184639, 0.382501, 0.937507, 2.418347",\ + "0.069174, 0.184639, 0.382586, 0.937507, 2.418347",\ + "0.077831, 0.187460, 0.383300, 0.940319, 2.418347",\ + "0.099054, 0.205738, 0.390315, 0.940320, 2.425200"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.103322, 0.134506, 0.187130, 0.329612, 0.708263",\ + "0.188196, 0.219801, 0.272413, 0.414932, 0.793505",\ + "0.281500, 0.317246, 0.369943, 0.512302, 0.890520",\ + "0.433568, 0.478875, 0.537406, 0.680993, 1.058708",\ + "0.668936, 0.733428, 0.809479, 0.962224, 1.340585"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040521, 0.090274, 0.180244, 0.428614, 1.092440",\ + "0.042863, 0.090977, 0.180401, 0.428614, 1.092696",\ + "0.054661, 0.097371, 0.180899, 0.428690, 1.092793",\ + "0.077190, 0.120374, 0.194930, 0.430280, 1.092793",\ + "0.118581, 0.174509, 0.240947, 0.445113, 1.092793"); + } + + } /* end of arc fla_obs_i[2]_ast2padmux_o[2]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "fla_obs_i[2]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.110629, 0.177262, 0.293339, 0.610165, 1.460154",\ + "0.194795, 0.261696, 0.378936, 0.695592, 1.544629",\ + "0.275980, 0.343081, 0.460479, 0.778514, 1.626463",\ + "0.408884, 0.478137, 0.595421, 0.915532, 1.762573",\ + "0.610985, 0.691263, 0.810230, 1.128954, 1.977655"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067834, 0.183634, 0.382402, 0.934951, 2.414331",\ + "0.067834, 0.183634, 0.382402, 0.934951, 2.414331",\ + "0.068631, 0.183634, 0.382540, 0.936478, 2.414331",\ + "0.075251, 0.185541, 0.383090, 0.939701, 2.414331",\ + "0.093347, 0.198994, 0.384563, 0.939701, 2.425563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.077370, 0.108647, 0.161299, 0.303710, 0.682406",\ + "0.166391, 0.197521, 0.250129, 0.392651, 0.771277",\ + "0.253394, 0.288299, 0.340979, 0.483371, 0.861661",\ + "0.395347, 0.439383, 0.496795, 0.640121, 1.017884",\ + "0.615736, 0.679130, 0.754042, 0.905113, 1.283136"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039363, 0.090228, 0.180124, 0.428312, 1.092155",\ + "0.041196, 0.090228, 0.180315, 0.428312, 1.092511",\ + "0.052267, 0.096073, 0.180798, 0.428601, 1.092511",\ + "0.074482, 0.116813, 0.192279, 0.430033, 1.092511",\ + "0.116096, 0.171326, 0.236992, 0.441817, 1.092511"); + } + + } /* end of arc fla_obs_i[2]_ast2padmux_o[2]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[10]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.443642, 0.510546, 0.626985, 0.946654, 1.801858",\ + "0.465905, 0.532810, 0.649248, 0.968917, 1.824121",\ + "0.522299, 0.589203, 0.705642, 1.025311, 1.880515",\ + "0.620162, 0.687066, 0.803505, 1.123173, 1.978378",\ + "1.134534, 1.201443, 1.317885, 1.637554, 2.492753"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\ + "0.073042, 0.188941, 0.391856, 0.949133, 2.441345"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.490585, 0.522017, 0.574725, 0.717078, 1.095675",\ + "0.512119, 0.543551, 0.596259, 0.738612, 1.117209",\ + "0.579305, 0.610737, 0.663445, 0.805798, 1.184395",\ + "0.689604, 0.721035, 0.773743, 0.916096, 1.294693",\ + "1.248357, 1.279789, 1.332497, 1.474850, 1.853447"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090836"); + } + + } /* end of arc obs_ctrl_o[10]_ast2padmux_o[2]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[10]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.412827, 0.479717, 0.596144, 0.915812, 1.771032",\ + "0.433604, 0.500495, 0.616922, 0.936590, 1.791810",\ + "0.491196, 0.558086, 0.674513, 0.994181, 1.849401",\ + "0.589141, 0.656031, 0.772458, 1.092126, 1.947346",\ + "1.077990, 1.144880, 1.261307, 1.580975, 2.436195"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.392762, 0.424174, 0.476820, 0.619235, 0.997878",\ + "0.410167, 0.441580, 0.494226, 0.636641, 1.015284",\ + "0.482737, 0.514149, 0.566795, 0.709210, 1.087853",\ + "0.595371, 0.626784, 0.679430, 0.821845, 1.200488",\ + "1.122399, 1.153812, 1.206458, 1.348872, 1.727516"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687"); + } + + } /* end of arc obs_ctrl_o[10]_ast2padmux_o[2]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[10]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.437382, 0.468814, 0.521522, 0.663875, 1.042472",\ + "0.462451, 0.493883, 0.546591, 0.688944, 1.067541",\ + "0.531672, 0.563103, 0.615812, 0.758164, 1.136761",\ + "0.655903, 0.687335, 0.740043, 0.882396, 1.260993",\ + "1.288504, 1.319936, 1.372644, 1.514997, 1.893594"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090836"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.675759, 0.742664, 0.859102, 1.178771, 2.033976",\ + "0.696234, 0.763138, 0.879577, 1.199246, 2.054450",\ + "0.755094, 0.821998, 0.938437, 1.258106, 2.113310",\ + "0.864334, 0.931238, 1.047677, 1.367346, 2.222550",\ + "1.641748, 1.708657, 1.825099, 2.144769, 2.999968"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\ + "0.073042, 0.188941, 0.391856, 0.949133, 2.441345"); + } + + } /* end of arc obs_ctrl_o[10]_ast2padmux_o[2]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[10]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.262392, 0.293804, 0.346450, 0.488865, 0.867508",\ + "0.286002, 0.317414, 0.370060, 0.512475, 0.891118",\ + "0.357340, 0.388753, 0.441399, 0.583814, 0.962457",\ + "0.477148, 0.508560, 0.561206, 0.703621, 1.082264",\ + "1.022245, 1.053658, 1.106303, 1.248718, 1.627362"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.582342, 0.649232, 0.765660, 1.085328, 1.940547",\ + "0.599034, 0.665924, 0.782351, 1.102020, 1.957239",\ + "0.661428, 0.728319, 0.844746, 1.164414, 2.019634",\ + "0.770818, 0.837708, 0.954135, 1.273803, 2.129023",\ + "1.507966, 1.574856, 1.691283, 2.010951, 2.866171"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330"); + } + + } /* end of arc obs_ctrl_o[10]_ast2padmux_o[2]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[11]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.034927, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.180024, 0.211452, 0.264149, 0.406513, 0.785119",\ + "0.193406, 0.224834, 0.277531, 0.419896, 0.798501",\ + "0.275919, 0.307349, 0.360051, 0.502410, 0.881011",\ + "0.400910, 0.432352, 0.485095, 0.627414, 1.005985",\ + "0.975060, 1.010086, 1.063144, 1.205732, 1.584486"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.034927, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039119, 0.090633, 0.180636, 0.429262, 1.090996",\ + "0.039119, 0.090633, 0.180636, 0.429262, 1.090996",\ + "0.039132, 0.090633, 0.180667, 0.429269, 1.090996",\ + "0.039215, 0.090633, 0.180868, 0.429314, 1.090996",\ + "0.049347, 0.094034, 0.180868, 0.429355, 1.091896"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037147, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.465437, 0.532662, 0.649281, 0.969044, 1.824018",\ + "0.477695, 0.544920, 0.661539, 0.981302, 1.836276",\ + "0.541916, 0.609140, 0.725760, 1.045521, 1.900495",\ + "0.644626, 0.711856, 0.828474, 1.148242, 2.003221",\ + "1.319722, 1.387140, 1.503696, 1.823662, 2.678811"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037147, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073817, 0.189281, 0.392442, 0.950607, 2.441526",\ + "0.073817, 0.189281, 0.392442, 0.950607, 2.441526",\ + "0.073817, 0.189282, 0.392442, 0.950607, 2.441526",\ + "0.073862, 0.189282, 0.392442, 0.950619, 2.441526",\ + "0.075399, 0.189282, 0.392442, 0.951039, 2.441526"); + } + + } /* end of arc obs_ctrl_o[11]_ast2padmux_o[2]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[11]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.030664, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.159139, 0.190553, 0.243202, 0.385613, 0.764254",\ + "0.170514, 0.201928, 0.254577, 0.396989, 0.775629",\ + "0.255576, 0.286993, 0.339652, 0.482053, 0.860686",\ + "0.379908, 0.411340, 0.464049, 0.606401, 0.984998",\ + "0.945167, 0.979651, 1.032663, 1.175209, 1.553933"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.030664, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039020, 0.090609, 0.180397, 0.429208, 1.090831",\ + "0.039020, 0.090609, 0.180397, 0.429208, 1.090831",\ + "0.039042, 0.090609, 0.180449, 0.429220, 1.090831",\ + "0.039144, 0.090609, 0.180675, 0.429276, 1.090831",\ + "0.047820, 0.093501, 0.180675, 0.429352, 1.091629"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.028580, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.461683, 0.528880, 0.645509, 0.965243, 1.820192",\ + "0.470327, 0.537524, 0.654153, 0.973887, 1.828836",\ + "0.538174, 0.605371, 0.721999, 1.041733, 1.896681",\ + "0.640782, 0.707985, 0.824611, 1.144351, 1.999304",\ + "1.312551, 1.379913, 1.496487, 1.816396, 2.671496"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.028580, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073594, 0.189124, 0.392388, 0.950544, 2.441454",\ + "0.073594, 0.189124, 0.392388, 0.950544, 2.441454",\ + "0.073594, 0.189124, 0.392388, 0.950544, 2.441454",\ + "0.073633, 0.189124, 0.392388, 0.950557, 2.441454",\ + "0.074954, 0.189124, 0.392388, 0.950917, 2.441454"); + } + + } /* end of arc obs_ctrl_o[11]_ast2padmux_o[2]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.500858, 0.568082, 0.684702, 1.004464, 1.859437",\ + "0.516623, 0.583848, 0.700467, 1.020230, 1.875203",\ + "0.590734, 0.657958, 0.774578, 1.094340, 1.949314",\ + "0.681946, 0.749171, 0.865790, 1.185553, 2.040526",\ + "1.108576, 1.175805, 1.292423, 1.612190, 2.467167"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073816, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073848, 0.189277, 0.392440, 0.950615, 2.441524"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.275118, 0.306284, 0.358903, 0.501398, 0.880041",\ + "0.290749, 0.321915, 0.374533, 0.517029, 0.895671",\ + "0.363703, 0.394869, 0.447488, 0.589983, 0.968626",\ + "0.474794, 0.505959, 0.558577, 0.701073, 1.079716",\ + "1.013269, 1.044421, 1.097036, 1.239541, 1.618177"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040759, 0.090626, 0.180653, 0.429266, 1.092499",\ + "0.040922, 0.090525, 0.180916, 0.429325, 1.092539"); + } + + } /* end of arc obs_ctrl_o[4]_ast2padmux_o[2]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.337608, 0.404302, 0.520641, 0.837429, 1.687203",\ + "0.349939, 0.416633, 0.532972, 0.849760, 1.699534",\ + "0.408752, 0.475446, 0.591785, 0.908573, 1.758347",\ + "0.496083, 0.562777, 0.679117, 0.995905, 1.845678",\ + "0.949078, 1.015776, 1.132136, 1.448920, 2.298678"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184560, 0.382485, 0.937098, 2.417677",\ + "0.067604, 0.184551, 0.382483, 0.937052, 2.417689"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.209985, 0.241400, 0.294052, 0.436461, 0.815099",\ + "0.221857, 0.253271, 0.305923, 0.448332, 0.826970",\ + "0.304351, 0.335766, 0.388417, 0.530826, 0.909465",\ + "0.409226, 0.440642, 0.493298, 0.635702, 1.014338",\ + "0.909442, 0.940877, 0.993596, 1.135938, 1.514527"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039034, 0.090327, 0.180161, 0.428971, 1.091542",\ + "0.039166, 0.090324, 0.180166, 0.428948, 1.090692"); + } + + } /* end of arc obs_ctrl_o[4]_ast2padmux_o[2]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.287803, 0.318969, 0.371587, 0.514083, 0.892726",\ + "0.303569, 0.334734, 0.387353, 0.529848, 0.908491",\ + "0.378810, 0.409975, 0.462594, 0.605089, 0.983732",\ + "0.473884, 0.505049, 0.557668, 0.700163, 1.078806",\ + "0.918190, 0.949342, 1.001956, 1.144462, 1.523098"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040759, 0.090626, 0.180653, 0.429266, 1.092499",\ + "0.040922, 0.090525, 0.180916, 0.429325, 1.092539"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.376755, 0.443500, 0.560063, 0.876818, 1.726409",\ + "0.392417, 0.459162, 0.575725, 0.892480, 1.742071",\ + "0.467424, 0.534169, 0.650732, 0.967487, 1.817078",\ + "0.562603, 0.629351, 0.745928, 1.062681, 1.912261",\ + "1.006927, 1.073706, 1.190415, 1.507149, 2.356620"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073816, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073848, 0.189277, 0.392440, 0.950615, 2.441524"); + } + + } /* end of arc obs_ctrl_o[4]_ast2padmux_o[2]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.264318, 0.295567, 0.348210, 0.490643, 0.869326",\ + "0.278489, 0.309737, 0.362381, 0.504814, 0.883496",\ + "0.355325, 0.386573, 0.439217, 0.581649, 0.960332",\ + "0.450369, 0.481617, 0.534260, 0.676693, 1.055376",\ + "0.893831, 0.925076, 0.977718, 1.120154, 1.498834"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039034, 0.090327, 0.180161, 0.428971, 1.091542",\ + "0.039166, 0.090324, 0.180166, 0.428948, 1.090692"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.373701, 0.440395, 0.556734, 0.873522, 1.723296",\ + "0.385572, 0.452266, 0.568605, 0.885393, 1.735167",\ + "0.464371, 0.531065, 0.647404, 0.964192, 1.813966",\ + "0.559385, 0.626079, 0.742420, 1.059207, 1.908981",\ + "1.002245, 1.068944, 1.185303, 1.502088, 2.351846"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184560, 0.382485, 0.937098, 2.417677",\ + "0.067604, 0.184551, 0.382483, 0.937052, 2.417689"); + } + + } /* end of arc obs_ctrl_o[4]_ast2padmux_o[2]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.337998, 0.404744, 0.521308, 0.838063, 1.687653",\ + "0.353177, 0.419923, 0.536487, 0.853242, 1.702832",\ + "0.412195, 0.478941, 0.595505, 0.912260, 1.761850",\ + "0.508449, 0.575199, 0.691783, 1.008535, 1.858109",\ + "0.997007, 1.063817, 1.180658, 1.497372, 2.346736"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\ + "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073887, 0.189271, 0.392439, 0.950626, 2.441522",\ + "0.075818, 0.189005, 0.392348, 0.951153, 2.441399"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.272032, 0.303198, 0.355817, 0.498312, 0.876955",\ + "0.289891, 0.321056, 0.373675, 0.516170, 0.894813",\ + "0.360955, 0.392121, 0.444739, 0.587235, 0.965878",\ + "0.471378, 0.502542, 0.555160, 0.697656, 1.076298",\ + "1.004117, 1.035227, 1.087829, 1.230366, 1.608983"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\ + "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\ + "0.040752, 0.090633, 0.180666, 0.429269, 1.092497",\ + "0.040771, 0.090633, 0.180871, 0.429315, 1.092502",\ + "0.049622, 0.094130, 0.180871, 0.429356, 1.092666"); + } + + } /* end of arc obs_ctrl_o[5]_ast2padmux_o[2]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.329221, 0.395915, 0.512254, 0.829041, 1.678816",\ + "0.344592, 0.411286, 0.527624, 0.844412, 1.694187",\ + "0.406780, 0.473474, 0.589813, 0.906601, 1.756375",\ + "0.502234, 0.568932, 0.685288, 1.002073, 1.851833",\ + "0.957622, 1.024367, 1.140929, 1.457685, 2.307276"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067607, 0.184553, 0.382483, 0.937060, 2.417687",\ + "0.067439, 0.184458, 0.382464, 0.936568, 2.417820"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.231492, 0.262740, 0.315383, 0.457816, 0.836499",\ + "0.245351, 0.276600, 0.329243, 0.471676, 0.850359",\ + "0.320124, 0.351372, 0.404016, 0.546449, 0.925131",\ + "0.430166, 0.461410, 0.514053, 0.656489, 1.035169",\ + "0.955028, 0.986237, 1.038869, 1.181331, 1.559995"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039041, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039146, 0.090294, 0.180167, 0.428752, 1.090822",\ + "0.040211, 0.090294, 0.180212, 0.428752, 1.091676"); + } + + } /* end of arc obs_ctrl_o[5]_ast2padmux_o[2]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[5]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.176901, 0.208329, 0.261026, 0.403390, 0.781996",\ + "0.196158, 0.227585, 0.280282, 0.422647, 0.801252",\ + "0.273304, 0.304734, 0.357436, 0.499795, 0.878396",\ + "0.397207, 0.428649, 0.481392, 0.623711, 1.002282",\ + "0.961790, 0.996912, 1.049978, 1.192575, 1.571334"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\ + "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\ + "0.040752, 0.090633, 0.180666, 0.429269, 1.092497",\ + "0.040771, 0.090633, 0.180871, 0.429315, 1.092502",\ + "0.049622, 0.094130, 0.180871, 0.429356, 1.092666"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.455825, 0.523049, 0.639668, 0.959430, 1.814404",\ + "0.468963, 0.536187, 0.652807, 0.972569, 1.827542",\ + "0.531289, 0.598514, 0.715133, 1.034896, 1.889869",\ + "0.640154, 0.707387, 0.824004, 1.143775, 1.998757",\ + "1.332501, 1.399969, 1.516508, 1.836528, 2.691724"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\ + "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073887, 0.189271, 0.392439, 0.950626, 2.441522",\ + "0.075818, 0.189005, 0.392348, 0.951153, 2.441399"); + } + + } /* end of arc obs_ctrl_o[5]_ast2padmux_o[2]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[5]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.155833, 0.187247, 0.239896, 0.382308, 0.760949",\ + "0.173482, 0.204896, 0.257545, 0.399957, 0.778598",\ + "0.252964, 0.284381, 0.337040, 0.479441, 0.858074",\ + "0.376196, 0.407628, 0.460337, 0.602689, 0.981285",\ + "0.931678, 0.966257, 1.019278, 1.161831, 1.540560"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039041, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039146, 0.090294, 0.180167, 0.428752, 1.090822",\ + "0.040211, 0.090294, 0.180212, 0.428752, 1.091676"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.452081, 0.519278, 0.635907, 0.955640, 1.810589",\ + "0.461862, 0.529059, 0.645688, 0.965421, 1.820370",\ + "0.527542, 0.594739, 0.711368, 1.031102, 1.886050",\ + "0.636262, 0.703467, 0.820093, 1.139835, 1.994791",\ + "1.324350, 1.391756, 1.508316, 1.828270, 2.683409"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067607, 0.184553, 0.382483, 0.937060, 2.417687",\ + "0.067439, 0.184458, 0.382464, 0.936568, 2.417820"); + } + + } /* end of arc obs_ctrl_o[5]_ast2padmux_o[2]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[6]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.325984, 0.393209, 0.509828, 0.829592, 1.684567",\ + "0.341732, 0.408957, 0.525576, 0.845340, 1.700314",\ + "0.405621, 0.472847, 0.589466, 0.909229, 1.764204",\ + "0.483984, 0.551208, 0.667827, 0.987590, 1.842564",\ + "0.876566, 0.943791, 1.060410, 1.380173, 2.235147"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189281, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189281, 0.392442, 0.950608, 2.441526"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.207560, 0.238992, 0.291700, 0.434053, 0.812650",\ + "0.223441, 0.254873, 0.307582, 0.449934, 0.828531",\ + "0.292964, 0.324396, 0.377105, 0.519457, 0.898054",\ + "0.382304, 0.413736, 0.466444, 0.608797, 0.987394",\ + "0.808201, 0.839636, 0.892354, 1.034697, 1.413287"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\ + "0.040785, 0.090610, 0.180744, 0.429286, 1.092505"); + } + + } /* end of arc obs_ctrl_o[6]_ast2padmux_o[2]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[6]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.298728, 0.365697, 0.482189, 0.801862, 1.656989",\ + "0.312838, 0.379807, 0.496299, 0.815972, 1.671100",\ + "0.378416, 0.445385, 0.561877, 0.881551, 1.736677",\ + "0.456978, 0.523948, 0.640441, 0.960115, 1.815240",\ + "0.852482, 0.919491, 1.036016, 1.355692, 2.210772"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067586, 0.184541, 0.382481, 0.936998, 2.417704"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.185526, 0.216941, 0.269593, 0.412001, 0.790640",\ + "0.197528, 0.228943, 0.281595, 0.424004, 0.802642",\ + "0.270950, 0.302365, 0.355017, 0.497425, 0.876064",\ + "0.360375, 0.391790, 0.444442, 0.586850, 0.965489",\ + "0.786063, 0.817479, 0.870138, 1.012540, 1.391174"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039039, 0.090322, 0.180169, 0.428938, 1.091513"); + } + + } /* end of arc obs_ctrl_o[6]_ast2padmux_o[2]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[6]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.314064, 0.345229, 0.397848, 0.540343, 0.918986",\ + "0.329859, 0.361025, 0.413644, 0.556139, 0.934782",\ + "0.407724, 0.438890, 0.491508, 0.634004, 1.012646",\ + "0.508778, 0.539944, 0.592562, 0.735058, 1.113701",\ + "0.984655, 1.015818, 1.068436, 1.210933, 1.589574"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\ + "0.040785, 0.090610, 0.180744, 0.429286, 1.092505"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.596327, 0.663552, 0.780171, 1.099935, 1.954909",\ + "0.609131, 0.676356, 0.792975, 1.112739, 1.967713",\ + "0.677113, 0.744339, 0.860958, 1.180721, 2.035696",\ + "0.788810, 0.856034, 0.972654, 1.292416, 2.147390",\ + "1.273667, 1.340892, 1.457511, 1.777274, 2.632248"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189281, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189281, 0.392442, 0.950608, 2.441526"); + } + + } /* end of arc obs_ctrl_o[6]_ast2padmux_o[2]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[6]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.262848, 0.294262, 0.346915, 0.489323, 0.867962",\ + "0.276998, 0.308413, 0.361065, 0.503474, 0.882112",\ + "0.356726, 0.388141, 0.440793, 0.583202, 0.961840",\ + "0.457948, 0.489362, 0.542015, 0.684423, 1.063061",\ + "0.929777, 0.961193, 1.013852, 1.156254, 1.534888"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039039, 0.090322, 0.180169, 0.428938, 1.091513"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.437011, 0.503705, 0.620045, 0.936832, 1.786606",\ + "0.446608, 0.513302, 0.629642, 0.946429, 1.796203",\ + "0.517780, 0.584475, 0.700814, 1.017602, 1.867376",\ + "0.629396, 0.696091, 0.812430, 1.129218, 1.978992",\ + "1.131911, 1.198614, 1.314996, 1.631778, 2.481517"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067586, 0.184541, 0.382481, 0.936998, 2.417704"); + } + + } /* end of arc obs_ctrl_o[6]_ast2padmux_o[2]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[7]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.060518, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.315427, 0.346593, 0.399212, 0.541707, 0.920350",\ + "0.342146, 0.373312, 0.425930, 0.568426, 0.947068",\ + "0.410184, 0.441350, 0.493968, 0.636464, 1.015106",\ + "0.512927, 0.544093, 0.596711, 0.739207, 1.117850",\ + "0.999580, 1.030743, 1.083361, 1.225858, 1.604500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.060518, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180697, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180697, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180697, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180732, 0.429283, 1.092497",\ + "0.042004, 0.091469, 0.180867, 0.429340, 1.092504"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.051005, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.597332, 0.664558, 0.781177, 1.100940, 1.955915",\ + "0.618079, 0.685305, 0.801924, 1.121688, 1.976662",\ + "0.683404, 0.750630, 0.867249, 1.187012, 2.041987",\ + "0.797603, 0.864828, 0.981447, 1.301210, 2.156184",\ + "1.375793, 1.443018, 1.559637, 1.879400, 2.734374"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.051005, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189280, 0.392442, 0.950609, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073823, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073819, 0.189281, 0.392442, 0.950607, 2.441526",\ + "0.073817, 0.189281, 0.392442, 0.950607, 2.441526"); + } + + } /* end of arc obs_ctrl_o[7]_ast2padmux_o[2]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[7]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.049671, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.150722, 0.182137, 0.234789, 0.377197, 0.755836",\ + "0.171205, 0.202620, 0.255272, 0.397681, 0.776319",\ + "0.246518, 0.277932, 0.330585, 0.472993, 0.851631",\ + "0.352324, 0.383738, 0.436391, 0.578799, 0.957437",\ + "0.825559, 0.856975, 0.909634, 1.052036, 1.430670"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.049671, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039038, 0.090323, 0.180168, 0.428941, 1.091519"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040467, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.277343, 0.344312, 0.460804, 0.780477, 1.635605",\ + "0.293355, 0.360323, 0.476815, 0.796489, 1.651616",\ + "0.366113, 0.433085, 0.549579, 0.869253, 1.724376",\ + "0.487008, 0.554003, 0.670516, 0.990192, 1.845287",\ + "1.141953, 1.209132, 1.325766, 1.645481, 2.500414"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040467, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067601, 0.184550, 0.382483, 0.937044, 2.417691"); + } + + } /* end of arc obs_ctrl_o[7]_ast2padmux_o[2]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[8]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.700503, 0.767407, 0.883846, 1.203515, 2.058719",\ + "0.718853, 0.785757, 0.902195, 1.221864, 2.077069",\ + "0.789396, 0.856300, 0.972739, 1.292408, 2.147612",\ + "0.881867, 0.948772, 1.065210, 1.384879, 2.240083",\ + "1.366874, 1.433786, 1.550230, 1.869900, 2.725095"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073043, 0.188945, 0.391861, 0.949146, 2.441348"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.488066, 0.519497, 0.572205, 0.714558, 1.093155",\ + "0.505493, 0.536925, 0.589633, 0.731986, 1.110583",\ + "0.582890, 0.614322, 0.667030, 0.809383, 1.187980",\ + "0.691204, 0.722635, 0.775344, 0.917696, 1.296293",\ + "1.242374, 1.273805, 1.326514, 1.468867, 1.847463"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090836"); + } + + } /* end of arc obs_ctrl_o[8]_ast2padmux_o[2]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[8]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.636502, 0.703393, 0.819820, 1.139488, 1.994708",\ + "0.653118, 0.720008, 0.836435, 1.156103, 2.011323",\ + "0.727539, 0.794429, 0.910857, 1.230525, 2.085744",\ + "0.821960, 0.888850, 1.005277, 1.324945, 2.180165",\ + "1.269718, 1.336608, 1.453035, 1.772703, 2.627923"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.339768, 0.371181, 0.423827, 0.566242, 0.944885",\ + "0.353114, 0.384527, 0.437173, 0.579588, 0.958231",\ + "0.435092, 0.466504, 0.519150, 0.661565, 1.040208",\ + "0.544311, 0.575724, 0.628370, 0.770784, 1.149428",\ + "1.067931, 1.099343, 1.151989, 1.294404, 1.673047"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687"); + } + + } /* end of arc obs_ctrl_o[8]_ast2padmux_o[2]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[8]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.524400, 0.555831, 0.608540, 0.750893, 1.129489",\ + "0.542749, 0.574181, 0.626889, 0.769242, 1.147839",\ + "0.616605, 0.648037, 0.700745, 0.843098, 1.221695",\ + "0.714865, 0.746296, 0.799004, 0.941357, 1.319954",\ + "1.237234, 1.268665, 1.321373, 1.463726, 1.842323"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090836"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.651244, 0.718149, 0.834587, 1.154256, 2.009460",\ + "0.663867, 0.730771, 0.847209, 1.166878, 2.022083",\ + "0.718781, 0.785685, 0.902124, 1.221793, 2.076997",\ + "0.821201, 0.888105, 1.004544, 1.324213, 2.179417",\ + "1.548479, 1.615391, 1.731835, 2.051504, 2.906700"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073043, 0.188945, 0.391861, 0.949146, 2.441348"); + } + + } /* end of arc obs_ctrl_o[8]_ast2padmux_o[2]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[8]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.267796, 0.299208, 0.351854, 0.494269, 0.872912",\ + "0.284541, 0.315954, 0.368600, 0.511015, 0.889658",\ + "0.362798, 0.394211, 0.446856, 0.589271, 0.967914",\ + "0.486677, 0.518090, 0.570736, 0.713151, 1.091794",\ + "1.055266, 1.086678, 1.139324, 1.281739, 1.660382"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.456335, 0.523226, 0.639653, 0.959321, 1.814541",\ + "0.469682, 0.536572, 0.652999, 0.972667, 1.827887",\ + "0.547821, 0.614711, 0.731138, 1.050806, 1.906026",\ + "0.649000, 0.715890, 0.832317, 1.151985, 2.007205",\ + "1.120855, 1.187745, 1.304172, 1.623840, 2.479060"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330"); + } + + } /* end of arc obs_ctrl_o[8]_ast2padmux_o[2]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[9]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.712314, 0.779218, 0.895657, 1.215326, 2.070530",\ + "0.730867, 0.797771, 0.914210, 1.233879, 2.089083",\ + "0.803565, 0.870469, 0.986908, 1.306577, 2.161781",\ + "0.898790, 0.965694, 1.082133, 1.401802, 2.257006",\ + "1.358120, 1.425029, 1.541471, 1.861141, 2.716340"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073041, 0.188941, 0.391855, 0.949133, 2.441345"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.494441, 0.525873, 0.578581, 0.720934, 1.099531",\ + "0.511983, 0.543415, 0.596123, 0.738476, 1.117073",\ + "0.589312, 0.620744, 0.673452, 0.815805, 1.194402",\ + "0.698758, 0.730189, 0.782897, 0.925250, 1.303847",\ + "1.229663, 1.261095, 1.313803, 1.456156, 1.834753"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090836"); + } + + } /* end of arc obs_ctrl_o[9]_ast2padmux_o[2]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[9]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.668630, 0.735520, 0.851947, 1.171615, 2.026835",\ + "0.685451, 0.752341, 0.868768, 1.188436, 2.043656",\ + "0.759882, 0.826773, 0.943200, 1.262868, 2.118088",\ + "0.855138, 0.922028, 1.038455, 1.358123, 2.213343",\ + "1.307789, 1.374679, 1.491106, 1.810774, 2.665994"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.361699, 0.393111, 0.445757, 0.588172, 0.966815",\ + "0.375155, 0.406568, 0.459214, 0.601628, 0.980272",\ + "0.456576, 0.487988, 0.540634, 0.683049, 1.061692",\ + "0.566550, 0.597963, 0.650609, 0.793024, 1.171667",\ + "1.091986, 1.123399, 1.176044, 1.318459, 1.697102"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687"); + } + + } /* end of arc obs_ctrl_o[9]_ast2padmux_o[2]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[9]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.528266, 0.559698, 0.612406, 0.754759, 1.133356",\ + "0.546819, 0.578250, 0.630959, 0.773312, 1.151908",\ + "0.620877, 0.652309, 0.705017, 0.847370, 1.225967",\ + "0.719978, 0.751410, 0.804118, 0.946471, 1.325068",\ + "1.192613, 1.224045, 1.276753, 1.419106, 1.797703"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090836"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.606303, 0.673207, 0.789646, 1.109315, 1.964519",\ + "0.618992, 0.685897, 0.802335, 1.122004, 1.977208",\ + "0.673763, 0.740668, 0.857106, 1.176775, 2.031980",\ + "0.776802, 0.843707, 0.960145, 1.279814, 2.135018",\ + "1.483718, 1.550627, 1.667069, 1.986738, 2.841937"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073041, 0.188941, 0.391855, 0.949133, 2.441345"); + } + + } /* end of arc obs_ctrl_o[9]_ast2padmux_o[2]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[9]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.262699, 0.294112, 0.346758, 0.489173, 0.867816",\ + "0.279513, 0.310926, 0.363572, 0.505987, 0.884630",\ + "0.357852, 0.389264, 0.441910, 0.584325, 0.962968",\ + "0.480383, 0.511796, 0.564441, 0.706856, 1.085500",\ + "1.037548, 1.068961, 1.121607, 1.264022, 1.642665"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.463612, 0.530502, 0.646929, 0.966597, 1.821817",\ + "0.477068, 0.543958, 0.660386, 0.980054, 1.835274",\ + "0.555357, 0.622247, 0.738674, 1.058342, 1.913562",\ + "0.655033, 0.721923, 0.838350, 1.158018, 2.013238",\ + "1.119877, 1.186768, 1.303195, 1.622863, 2.478083"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330"); + } + + } /* end of arc obs_ctrl_o[9]_ast2padmux_o[2]_inv_min*/ + + timing () { + related_pin : "otm_obs_i[2]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.123879, 0.190820, 0.307288, 0.626960, 1.482121",\ + "0.210891, 0.277978, 0.394567, 0.714249, 1.569235",\ + "0.301781, 0.369068, 0.485667, 0.805496, 1.660526",\ + "0.453978, 0.523120, 0.640034, 0.960158, 1.815427",\ + "0.695902, 0.774527, 0.893732, 1.214148, 2.069560"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073065, 0.188997, 0.391936, 0.949305, 2.441374",\ + "0.073175, 0.189249, 0.392304, 0.950092, 2.441498",\ + "0.074330, 0.189249, 0.392418, 0.950747, 2.441498",\ + "0.079436, 0.191164, 0.392505, 0.951076, 2.441498",\ + "0.098084, 0.204137, 0.393542, 0.951076, 2.441498"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.114293, 0.145721, 0.198417, 0.340782, 0.719388",\ + "0.205394, 0.236828, 0.289545, 0.431889, 0.810480",\ + "0.309904, 0.342065, 0.394885, 0.537244, 0.915841",\ + "0.501618, 0.536979, 0.590065, 0.732680, 1.111452",\ + "0.825607, 0.870622, 0.930343, 1.075147, 1.454209"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039117, 0.090634, 0.180632, 0.429261, 1.091005",\ + "0.039161, 0.090634, 0.180739, 0.429285, 1.091005",\ + "0.041267, 0.091212, 0.180891, 0.429338, 1.091005",\ + "0.050293, 0.094364, 0.180891, 0.429357, 1.092061",\ + "0.068556, 0.114740, 0.192215, 0.429716, 1.093122"); + } + + } /* end of arc otm_obs_i[2]_ast2padmux_o[2]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "otm_obs_i[2]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.120559, 0.187489, 0.303948, 0.623619, 1.478793",\ + "0.205712, 0.272774, 0.389342, 0.709022, 1.564038",\ + "0.292652, 0.359907, 0.476516, 0.796311, 1.651312",\ + "0.437434, 0.505450, 0.622092, 0.942182, 1.797434",\ + "0.662107, 0.738115, 0.856688, 1.177023, 2.032395"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073057, 0.188977, 0.391908, 0.949245, 2.441364",\ + "0.073156, 0.189206, 0.392241, 0.949956, 2.441378",\ + "0.074065, 0.189247, 0.392382, 0.950255, 2.441378",\ + "0.077223, 0.189624, 0.392382, 0.950255, 2.441378",\ + "0.092938, 0.200557, 0.393255, 0.950255, 2.441468"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.094368, 0.125782, 0.178430, 0.320842, 0.699483",\ + "0.188259, 0.219683, 0.272369, 0.414744, 0.793358",\ + "0.291365, 0.323244, 0.376040, 0.518376, 0.896959",\ + "0.474009, 0.509208, 0.562280, 0.704883, 1.083646",\ + "0.777508, 0.822171, 0.881623, 1.026340, 1.405392"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039018, 0.090654, 0.180392, 0.429207, 1.090346",\ + "0.039096, 0.090654, 0.180581, 0.429249, 1.090346",\ + "0.040472, 0.090934, 0.180608, 0.429337, 1.090346",\ + "0.049836, 0.094205, 0.180608, 0.429356, 1.091981",\ + "0.067933, 0.113945, 0.191732, 0.429701, 1.093101"); + } + + } /* end of arc otm_obs_i[2]_ast2padmux_o[2]_una_min*/ + + timing () { + related_pin : "otp_obs_i[2]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.122660, 0.189370, 0.305783, 0.622560, 1.472274",\ + "0.209824, 0.276743, 0.394059, 0.710704, 1.559679",\ + "0.301920, 0.369023, 0.486415, 0.804486, 1.652417",\ + "0.455547, 0.524976, 0.642287, 0.962376, 1.809444",\ + "0.699992, 0.780922, 0.900058, 1.218756, 2.067549"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067561, 0.184527, 0.382478, 0.936925, 2.417724",\ + "0.067561, 0.184527, 0.382478, 0.936925, 2.418306",\ + "0.068683, 0.184527, 0.382544, 0.936925, 2.418306",\ + "0.075540, 0.185756, 0.383113, 0.940410, 2.418306",\ + "0.094401, 0.199857, 0.384817, 0.940410, 2.426093"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.114764, 0.145947, 0.198571, 0.341053, 0.719705",\ + "0.205629, 0.236785, 0.289401, 0.431904, 0.810542",\ + "0.310076, 0.342571, 0.395201, 0.537686, 0.916183",\ + "0.500896, 0.538360, 0.591093, 0.733386, 1.111456",\ + "0.820213, 0.870292, 0.933027, 1.077593, 1.455130"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040532, 0.090273, 0.180246, 0.428609, 1.092443",\ + "0.040870, 0.090273, 0.180281, 0.428609, 1.092443",\ + "0.045400, 0.092351, 0.180508, 0.428609, 1.092443",\ + "0.059558, 0.100025, 0.181106, 0.428872, 1.092443",\ + "0.087354, 0.133744, 0.204884, 0.431205, 1.092443"); + } + + } /* end of arc otp_obs_i[2]_ast2padmux_o[2]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "otp_obs_i[2]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.119334, 0.186028, 0.302368, 0.619155, 1.468929",\ + "0.204833, 0.271716, 0.388876, 0.705544, 1.554647",\ + "0.293319, 0.360401, 0.477846, 0.795625, 1.643707",\ + "0.440314, 0.508488, 0.625608, 0.945855, 1.792734",\ + "0.667813, 0.745674, 0.864272, 1.183300, 2.031636"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.183691, 0.382409, 0.935142, 2.413233",\ + "0.067620, 0.183691, 0.382409, 0.935142, 2.413233",\ + "0.068262, 0.183691, 0.382508, 0.936031, 2.413233",\ + "0.073482, 0.184226, 0.382946, 0.939859, 2.413233",\ + "0.089380, 0.196045, 0.384240, 0.939859, 2.423100"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.094521, 0.125776, 0.178422, 0.320849, 0.699535",\ + "0.188239, 0.219444, 0.272075, 0.414540, 0.793202",\ + "0.291550, 0.323577, 0.376197, 0.518700, 0.897237",\ + "0.473699, 0.510899, 0.563627, 0.705929, 1.084022",\ + "0.773733, 0.823401, 0.885774, 1.030256, 1.407808"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039633, 0.090291, 0.180152, 0.428296, 1.092222",\ + "0.040262, 0.090291, 0.180217, 0.428296, 1.092377",\ + "0.044064, 0.091627, 0.180452, 0.428296, 1.092425",\ + "0.058805, 0.099616, 0.181075, 0.428844, 1.092425",\ + "0.086478, 0.132591, 0.204027, 0.431125, 1.092425"); + } + + } /* end of arc otp_obs_i[2]_ast2padmux_o[2]_una_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380000.312500, 380000.312500, 380000.343750, 380000.406250, 380000.593750",\ + "380000.406250, 380000.406250, 380000.437500, 380000.500000, 380000.687500",\ + "380000.500000, 380000.500000, 380000.531250, 380000.593750, 380000.781250",\ + "380000.656250, 380000.656250, 380000.687500, 380000.750000, 380000.937500",\ + "380000.906250, 380000.906250, 380000.937500, 380001.000000, 380001.187500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380001.781250, 380001.843750, 380001.968750, 380002.281250, 380003.156250",\ + "380001.875000, 380001.937500, 380002.062500, 380002.375000, 380003.250000",\ + "380002.000000, 380002.062500, 380002.187500, 380002.500000, 380003.375000",\ + "380002.187500, 380002.250000, 380002.375000, 380002.687500, 380003.562500",\ + "380002.500000, 380002.562500, 380002.687500, 380003.000000, 380003.875000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526"); + } + + } /* end of arc padmux2ast_i[4]_ast2padmux_o[2]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380000.312500, 380000.312500, 380000.343750, 380000.406250, 380000.593750",\ + "380000.406250, 380000.406250, 380000.437500, 380000.500000, 380000.687500",\ + "380000.468750, 380000.468750, 380000.500000, 380000.562500, 380000.750000",\ + "380000.625000, 380000.625000, 380000.656250, 380000.718750, 380000.906250",\ + "380000.843750, 380000.843750, 380000.875000, 380000.937500, 380001.125000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380001.781250, 380001.812500, 380001.906250, 380002.187500, 380002.875000",\ + "380001.875000, 380001.906250, 380002.000000, 380002.281250, 380002.968750",\ + "380001.968750, 380002.000000, 380002.093750, 380002.375000, 380003.062500",\ + "380002.156250, 380002.187500, 380002.281250, 380002.562500, 380003.250000",\ + "380002.406250, 380002.437500, 380002.531250, 380002.812500, 380003.500000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169"); + } + + } /* end of arc padmux2ast_i[4]_ast2padmux_o[2]_inv_min*/ + +} /* end of pin ast2padmux_o[2] */ + +pin("ast2padmux_o[1]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.028584 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : ast2padmux_o[1]; + timing () { + related_pin : "clk_ast_rng_i" ; + related_output_pin : "rng_b_o[0]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.257031, 0.528778, 0.797030, 1.242767, 2.134242",\ + "0.323932, 0.595681, 0.863940, 1.309691, 2.201193",\ + "0.440368, 0.712118, 0.980382, 1.426145, 2.317669",\ + "0.760037, 1.031787, 1.300052, 1.745815, 2.637342",\ + "1.615245, 1.886993, 2.155250, 2.600997, 3.492491",\ + "0.315617, 0.587294, 0.855812, 1.300474, 2.190349",\ + "0.382518, 0.654197, 0.922722, 1.367397, 2.257300",\ + "0.498954, 0.770634, 1.039164, 1.483851, 2.373776",\ + "0.818623, 1.090303, 1.358834, 1.803522, 2.693449",\ + "1.673831, 1.945509, 2.214032, 2.658703, 3.548597",\ + "0.460207, 0.733101, 0.999707, 1.444229, 2.334082",\ + "0.527108, 0.800004, 1.066617, 1.511152, 2.401032",\ + "0.643544, 0.916442, 1.183060, 1.627606, 2.517509",\ + "0.963213, 1.236110, 1.502729, 1.947277, 2.837182",\ + "1.818421, 2.091316, 2.357927, 2.802459, 3.692330",\ + "0.496168, 0.770865, 1.036627, 1.481020, 2.370640",\ + "0.563069, 0.837768, 1.103536, 1.547944, 2.437591",\ + "0.679505, 0.954206, 1.219979, 1.664398, 2.554067",\ + "0.999174, 1.273875, 1.539648, 1.984068, 2.873740",\ + "1.854382, 2.129080, 2.394846, 2.839250, 3.728889",\ + "0.825262, 1.134787, 1.388262, 1.830277, 2.716096",\ + "0.892164, 1.201690, 1.455172, 1.897201, 2.783047",\ + "1.008600, 1.318128, 1.571615, 2.013655, 2.899523",\ + "1.328269, 1.637797, 1.891284, 2.333325, 3.219196",\ + "2.183476, 2.493002, 2.746482, 3.188507, 4.074345"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.073036, 0.073037, 0.073042, 0.073052, 0.073073",\ + "0.188928, 0.188931, 0.188942, 0.188966, 0.189013",\ + "0.391836, 0.391841, 0.391857, 0.391892, 0.391961",\ + "0.949092, 0.949101, 0.949136, 0.949210, 0.949357",\ + "2.441339, 2.441340, 2.441346, 2.441358, 2.441383",\ + "0.073036, 0.073037, 0.073042, 0.073052, 0.073073",\ + "0.188928, 0.188931, 0.188942, 0.188966, 0.189013",\ + "0.391836, 0.391841, 0.391857, 0.391892, 0.391961",\ + "0.949092, 0.949101, 0.949136, 0.949210, 0.949357",\ + "2.441339, 2.441340, 2.441346, 2.441358, 2.441383",\ + "0.073036, 0.073037, 0.073042, 0.073052, 0.073073",\ + "0.188928, 0.188931, 0.188942, 0.188966, 0.189013",\ + "0.391836, 0.391841, 0.391857, 0.391892, 0.391961",\ + "0.949092, 0.949102, 0.949136, 0.949210, 0.949357",\ + "2.441339, 2.441340, 2.441346, 2.441358, 2.441383",\ + "0.073036, 0.073037, 0.073042, 0.073052, 0.073073",\ + "0.188928, 0.188931, 0.188942, 0.188966, 0.189013",\ + "0.391836, 0.391841, 0.391857, 0.391892, 0.391961",\ + "0.949092, 0.949102, 0.949136, 0.949210, 0.949357",\ + "2.441339, 2.441340, 2.441346, 2.441358, 2.441383",\ + "0.073036, 0.073038, 0.073042, 0.073052, 0.073073",\ + "0.188928, 0.188932, 0.188943, 0.188966, 0.189013",\ + "0.391836, 0.391843, 0.391858, 0.391892, 0.391961",\ + "0.949092, 0.949105, 0.949137, 0.949210, 0.949357",\ + "2.441339, 2.441341, 2.441346, 2.441358, 2.441383"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.308725, 0.491796, 0.685627, 0.996163, 1.596700",\ + "0.340157, 0.523228, 0.717058, 1.027595, 1.628132",\ + "0.392865, 0.575936, 0.769767, 1.080304, 1.680844",\ + "0.535218, 0.718289, 0.912119, 1.222656, 1.823194",\ + "0.913815, 1.096886, 1.290716, 1.601252, 2.201788",\ + "0.368637, 0.551695, 0.745581, 1.055944, 1.656317",\ + "0.400068, 0.583126, 0.777012, 1.087376, 1.687749",\ + "0.452777, 0.635835, 0.829721, 1.140085, 1.740461",\ + "0.595130, 0.778187, 0.972073, 1.282437, 1.882811",\ + "0.973727, 1.156784, 1.350670, 1.661033, 2.261405",\ + "0.501379, 0.683946, 0.877464, 1.187801, 1.788124",\ + "0.532811, 0.715378, 0.908895, 1.219233, 1.819557",\ + "0.585519, 0.768086, 0.961603, 1.271942, 1.872268",\ + "0.727872, 0.910439, 1.103956, 1.414294, 2.014618",\ + "1.106469, 1.289036, 1.482553, 1.792891, 2.393212",\ + "0.534516, 0.717073, 0.910588, 1.220754, 1.820733",\ + "0.565947, 0.748505, 0.942020, 1.252186, 1.852165",\ + "0.618656, 0.801213, 0.994728, 1.304895, 1.904876",\ + "0.761009, 0.943566, 1.137081, 1.447247, 2.047226",\ + "1.139605, 1.322163, 1.515678, 1.825843, 2.425821",\ + "0.835592, 1.022294, 1.214223, 1.523770, 2.122581",\ + "0.867023, 1.053726, 1.245655, 1.555202, 2.154014",\ + "0.919731, 1.106434, 1.298363, 1.607911, 2.206725",\ + "1.062084, 1.248787, 1.440716, 1.750263, 2.349075",\ + "1.440681, 1.627384, 1.819313, 2.128859, 2.727669"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.039143, 0.039143, 0.039143, 0.039145, 0.039150",\ + "0.090610, 0.090610, 0.090610, 0.090608, 0.090604",\ + "0.180695, 0.180695, 0.180695, 0.180700, 0.180710",\ + "0.429275, 0.429275, 0.429275, 0.429276, 0.429279",\ + "1.090837, 1.090837, 1.090837, 1.090825, 1.090796",\ + "0.039143, 0.039143, 0.039143, 0.039145, 0.039150",\ + "0.090610, 0.090610, 0.090610, 0.090608, 0.090604",\ + "0.180695, 0.180695, 0.180695, 0.180700, 0.180710",\ + "0.429275, 0.429275, 0.429275, 0.429276, 0.429279",\ + "1.090837, 1.090837, 1.090837, 1.090825, 1.090796",\ + "0.039143, 0.039143, 0.039143, 0.039145, 0.039150",\ + "0.090610, 0.090610, 0.090610, 0.090608, 0.090604",\ + "0.180695, 0.180695, 0.180695, 0.180700, 0.180710",\ + "0.429275, 0.429275, 0.429275, 0.429276, 0.429279",\ + "1.090837, 1.090837, 1.090837, 1.090825, 1.090796",\ + "0.039143, 0.039143, 0.039143, 0.039145, 0.039150",\ + "0.090610, 0.090610, 0.090610, 0.090608, 0.090604",\ + "0.180695, 0.180695, 0.180695, 0.180700, 0.180710",\ + "0.429275, 0.429275, 0.429275, 0.429276, 0.429279",\ + "1.090837, 1.090837, 1.090837, 1.090825, 1.090796",\ + "0.039143, 0.039143, 0.039143, 0.039145, 0.039150",\ + "0.090610, 0.090610, 0.090610, 0.090608, 0.090604",\ + "0.180695, 0.180695, 0.180695, 0.180700, 0.180710",\ + "0.429275, 0.429275, 0.429275, 0.429276, 0.429279",\ + "1.090837, 1.090837, 1.090837, 1.090825, 1.090796"); + } + + } /* end of arc clk_ast_rng_i_ast2padmux_o[1]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_rng_i" ; + related_output_pin : "rng_b_o[0]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.252558, 0.520745, 0.784515, 1.222569, 2.097608",\ + "0.319449, 0.587637, 0.851411, 1.289475, 2.164534",\ + "0.435876, 0.704065, 0.967843, 1.405915, 2.280990",\ + "0.755544, 1.023733, 1.287511, 1.725584, 2.600661",\ + "1.610764, 1.878952, 2.142725, 2.580786, 3.455839",\ + "0.311120, 0.579252, 0.843280, 1.280275, 2.153714",\ + "0.378011, 0.646143, 0.910176, 1.347182, 2.220640",\ + "0.494438, 0.762572, 1.026608, 1.463622, 2.337097",\ + "0.814106, 1.082240, 1.346276, 1.783291, 2.656767",\ + "1.669326, 1.937458, 2.201490, 2.638493, 3.511946",\ + "0.455460, 0.724999, 0.987167, 1.424079, 2.297447",\ + "0.522351, 0.791891, 1.054064, 1.490985, 2.364373",\ + "0.638778, 0.908319, 1.170496, 1.607426, 2.480830",\ + "0.958446, 1.227987, 1.490164, 1.927095, 2.800500",\ + "1.813666, 2.083206, 2.345378, 2.782297, 3.655679",\ + "0.491341, 0.762735, 1.024086, 1.460950, 2.334005",\ + "0.558231, 0.829626, 1.090982, 1.527856, 2.400931",\ + "0.674659, 0.946054, 1.207414, 1.644296, 2.517388",\ + "0.994327, 1.265722, 1.527082, 1.963966, 2.837059",\ + "1.849546, 2.120941, 2.382296, 2.819168, 3.692237",\ + "0.819555, 1.126080, 1.375645, 1.810251, 2.679461",\ + "0.886446, 1.192972, 1.442542, 1.877157, 2.746387",\ + "1.002873, 1.309400, 1.558974, 1.993597, 2.862844",\ + "1.322541, 1.629068, 1.878642, 2.313266, 3.182515",\ + "2.177761, 2.484287, 2.733856, 3.168468, 4.037693"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.073031, 0.073031, 0.073033, 0.073040, 0.073054",\ + "0.188915, 0.188915, 0.188919, 0.188937, 0.188971",\ + "0.391815, 0.391816, 0.391824, 0.391849, 0.391899",\ + "0.949014, 0.949028, 0.949065, 0.949118, 0.949226",\ + "2.441330, 2.441330, 2.441334, 2.441343, 2.441361",\ + "0.073031, 0.073031, 0.073033, 0.073040, 0.073054",\ + "0.188915, 0.188915, 0.188919, 0.188937, 0.188971",\ + "0.391815, 0.391816, 0.391824, 0.391849, 0.391899",\ + "0.949014, 0.949028, 0.949065, 0.949118, 0.949226",\ + "2.441330, 2.441330, 2.441334, 2.441343, 2.441361",\ + "0.073031, 0.073031, 0.073033, 0.073040, 0.073054",\ + "0.188915, 0.188915, 0.188920, 0.188937, 0.188971",\ + "0.391815, 0.391816, 0.391824, 0.391849, 0.391899",\ + "0.949014, 0.949029, 0.949065, 0.949118, 0.949226",\ + "2.441330, 2.441330, 2.441334, 2.441343, 2.441361",\ + "0.073031, 0.073031, 0.073033, 0.073040, 0.073054",\ + "0.188915, 0.188915, 0.188920, 0.188937, 0.188971",\ + "0.391815, 0.391816, 0.391824, 0.391849, 0.391899",\ + "0.949014, 0.949029, 0.949065, 0.949119, 0.949226",\ + "2.441330, 2.441330, 2.441334, 2.441343, 2.441361",\ + "0.073031, 0.073031, 0.073033, 0.073040, 0.073054",\ + "0.188915, 0.188915, 0.188920, 0.188937, 0.188971",\ + "0.391816, 0.391816, 0.391824, 0.391849, 0.391899",\ + "0.949014, 0.949034, 0.949065, 0.949119, 0.949226",\ + "2.441330, 2.441331, 2.441334, 2.441343, 2.441361"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.262934, 0.448489, 0.641595, 0.948064, 1.538713",\ + "0.294346, 0.479902, 0.673008, 0.979478, 1.570129",\ + "0.346992, 0.532548, 0.725656, 1.032128, 1.622785",\ + "0.489407, 0.674962, 0.868069, 1.174539, 1.765190",\ + "0.868050, 1.053605, 1.246711, 1.553179, 2.143825",\ + "0.322845, 0.508317, 0.701440, 1.007833, 1.598330",\ + "0.354258, 0.539729, 0.732853, 1.039247, 1.629746",\ + "0.406904, 0.592376, 0.785500, 1.091897, 1.682402",\ + "0.549319, 0.734790, 0.927914, 1.234307, 1.824806",\ + "0.927962, 1.113433, 1.306556, 1.612947, 2.203442",\ + "0.455621, 0.640568, 0.833323, 1.139690, 1.730137",\ + "0.487034, 0.671981, 0.864736, 1.171104, 1.761553",\ + "0.539679, 0.724627, 0.917383, 1.223754, 1.814209",\ + "0.682094, 0.867041, 1.059797, 1.366165, 1.956614",\ + "1.060737, 1.245684, 1.438439, 1.744805, 2.335249",\ + "0.488779, 0.673866, 0.866553, 1.172770, 1.762998",\ + "0.520192, 0.705279, 0.897966, 1.204184, 1.794413",\ + "0.572837, 0.757925, 0.950613, 1.256834, 1.847070",\ + "0.715252, 0.900339, 1.093027, 1.399244, 1.989474",\ + "1.093896, 1.278982, 1.471669, 1.777884, 2.368110",\ + "0.790171, 0.979313, 1.170216, 1.475973, 2.065303",\ + "0.821584, 1.010726, 1.201629, 1.507387, 2.096719",\ + "0.874230, 1.063372, 1.254276, 1.560037, 2.149375",\ + "1.016645, 1.205787, 1.396689, 1.702447, 2.291780",\ + "1.395288, 1.584430, 1.775331, 2.081088, 2.670415"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.039012, 0.039013, 0.039015, 0.039021, 0.039034",\ + "0.090733, 0.090732, 0.090730, 0.090725, 0.090713",\ + "0.180377, 0.180379, 0.180385, 0.180400, 0.180431",\ + "0.429204, 0.429204, 0.429205, 0.429209, 0.429216",\ + "1.091688, 1.091683, 1.091668, 1.091629, 1.091545",\ + "0.039012, 0.039013, 0.039015, 0.039021, 0.039034",\ + "0.090733, 0.090732, 0.090730, 0.090725, 0.090713",\ + "0.180377, 0.180379, 0.180385, 0.180400, 0.180431",\ + "0.429204, 0.429204, 0.429205, 0.429209, 0.429216",\ + "1.091688, 1.091683, 1.091668, 1.091629, 1.091545",\ + "0.039012, 0.039013, 0.039015, 0.039021, 0.039034",\ + "0.090733, 0.090732, 0.090730, 0.090725, 0.090713",\ + "0.180377, 0.180379, 0.180385, 0.180400, 0.180431",\ + "0.429204, 0.429204, 0.429205, 0.429209, 0.429216",\ + "1.091688, 1.091683, 1.091668, 1.091629, 1.091545",\ + "0.039012, 0.039013, 0.039015, 0.039021, 0.039034",\ + "0.090733, 0.090732, 0.090730, 0.090725, 0.090712",\ + "0.180377, 0.180379, 0.180385, 0.180400, 0.180431",\ + "0.429204, 0.429204, 0.429205, 0.429209, 0.429216",\ + "1.091688, 1.091683, 1.091668, 1.091629, 1.091545",\ + "0.039012, 0.039013, 0.039015, 0.039021, 0.039034",\ + "0.090733, 0.090732, 0.090730, 0.090725, 0.090712",\ + "0.180378, 0.180379, 0.180385, 0.180400, 0.180431",\ + "0.429204, 0.429204, 0.429205, 0.429209, 0.429216",\ + "1.091687, 1.091683, 1.091668, 1.091628, 1.091545"); + } + + } /* end of arc clk_ast_rng_i_ast2padmux_o[1]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "970008.750000, 970008.812500, 970008.937500, 970009.250000, 970010.125000",\ + "970008.875000, 970008.937500, 970009.062500, 970009.375000, 970010.250000",\ + "970009.000000, 970009.062500, 970009.187500, 970009.500000, 970010.375000",\ + "970009.000000, 970009.062500, 970009.187500, 970009.500000, 970010.375000",\ + "970009.375000, 970009.437500, 970009.562500, 970009.875000, 970010.750000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189354, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189354, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189365, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189385, 0.392560, 0.950608, 2.441526",\ + "0.073824, 0.189425, 0.393252, 0.950608, 2.441526"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "970006.125000, 970006.187500, 970006.250000, 970006.375000, 970006.750000",\ + "970006.250000, 970006.312500, 970006.375000, 970006.500000, 970006.875000",\ + "970006.250000, 970006.312500, 970006.375000, 970006.500000, 970006.875000",\ + "970006.375000, 970006.437500, 970006.500000, 970006.625000, 970007.000000",\ + "970006.625000, 970006.687500, 970006.750000, 970006.875000, 970007.250000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.041204, 0.091190, 0.180893, 0.429338, 1.092497",\ + "0.041204, 0.091190, 0.180893, 0.429338, 1.092497",\ + "0.041204, 0.091190, 0.180893, 0.429338, 1.092497",\ + "0.041204, 0.091190, 0.180893, 0.429338, 1.092497",\ + "0.041204, 0.091190, 0.180893, 0.429338, 1.092497"); + } + + } /* end of arc clk_ast_tlul_i_ast2padmux_o[1]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.118063, 0.173160, 0.267375, 0.527316, 1.216798",\ + "0.205470, 0.260567, 0.354781, 0.614720, 1.304204",\ + "0.286205, 0.341346, 0.435579, 0.695608, 1.384949",\ + "0.343571, 0.398793, 0.493060, 0.753254, 1.442331",\ + "0.643636, 0.699058, 0.793671, 1.054205, 1.742813"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.055140, 0.149920, 0.315966, 0.770671, 1.992169",\ + "0.055140, 0.149920, 0.315966, 0.770671, 1.992169",\ + "0.055064, 0.149920, 0.315966, 0.770616, 1.992169",\ + "0.054924, 0.149920, 0.315966, 0.770514, 1.992169",\ + "0.054820, 0.149920, 0.315966, 0.770514, 1.988361"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.068977, 0.083624, 0.108789, 0.177707, 0.362145",\ + "0.157440, 0.172093, 0.197279, 0.266195, 0.450612",\ + "0.246166, 0.261189, 0.286407, 0.355291, 0.539679",\ + "0.308361, 0.324424, 0.349591, 0.418444, 0.602842",\ + "0.630702, 0.654723, 0.683267, 0.752219, 0.936438"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.015416, 0.041075, 0.085652, 0.207740, 0.535967",\ + "0.015763, 0.041089, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967"); + } + + } /* end of arc clk_ast_tlul_i_ast2padmux_o[1]_redg_min*/ + + timing () { + related_pin : "fla_obs_i[1]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.111862, 0.178517, 0.294685, 0.611498, 1.461412",\ + "0.196887, 0.263820, 0.381200, 0.697836, 1.546758",\ + "0.280874, 0.348002, 0.465333, 0.783744, 1.631498",\ + "0.419192, 0.490016, 0.607541, 0.927454, 1.774732",\ + "0.629434, 0.713469, 0.835221, 1.155234, 2.004311"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067759, 0.184639, 0.382501, 0.937507, 2.417566",\ + "0.067759, 0.184639, 0.382501, 0.937507, 2.418347",\ + "0.069174, 0.184639, 0.382586, 0.937507, 2.418347",\ + "0.077831, 0.187460, 0.383300, 0.940319, 2.418347",\ + "0.099054, 0.205738, 0.390315, 0.940320, 2.425200"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.103322, 0.134506, 0.187130, 0.329612, 0.708263",\ + "0.188196, 0.219801, 0.272413, 0.414932, 0.793505",\ + "0.281500, 0.317246, 0.369943, 0.512302, 0.890520",\ + "0.433568, 0.478875, 0.537406, 0.680993, 1.058708",\ + "0.668936, 0.733428, 0.809479, 0.962224, 1.340585"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040521, 0.090274, 0.180244, 0.428614, 1.092440",\ + "0.042863, 0.090977, 0.180401, 0.428614, 1.092696",\ + "0.054661, 0.097371, 0.180899, 0.428690, 1.092793",\ + "0.077190, 0.120374, 0.194930, 0.430280, 1.092793",\ + "0.118581, 0.174509, 0.240947, 0.445113, 1.092793"); + } + + } /* end of arc fla_obs_i[1]_ast2padmux_o[1]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "fla_obs_i[1]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.110629, 0.177262, 0.293339, 0.610165, 1.460154",\ + "0.194795, 0.261696, 0.378936, 0.695592, 1.544629",\ + "0.275980, 0.343081, 0.460479, 0.778514, 1.626463",\ + "0.408884, 0.478137, 0.595421, 0.915532, 1.762573",\ + "0.610985, 0.691263, 0.810230, 1.128954, 1.977655"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067834, 0.183634, 0.382402, 0.934951, 2.414331",\ + "0.067834, 0.183634, 0.382402, 0.934951, 2.414331",\ + "0.068631, 0.183634, 0.382540, 0.936478, 2.414331",\ + "0.075251, 0.185541, 0.383090, 0.939701, 2.414331",\ + "0.093347, 0.198994, 0.384563, 0.939701, 2.425563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.077370, 0.108647, 0.161299, 0.303710, 0.682406",\ + "0.166391, 0.197521, 0.250129, 0.392651, 0.771277",\ + "0.253394, 0.288299, 0.340979, 0.483371, 0.861661",\ + "0.395347, 0.439383, 0.496795, 0.640121, 1.017884",\ + "0.615736, 0.679130, 0.754042, 0.905113, 1.283136"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039363, 0.090228, 0.180124, 0.428312, 1.092155",\ + "0.041196, 0.090228, 0.180315, 0.428312, 1.092511",\ + "0.052267, 0.096073, 0.180798, 0.428601, 1.092511",\ + "0.074482, 0.116813, 0.192279, 0.430033, 1.092511",\ + "0.116096, 0.171326, 0.236992, 0.441817, 1.092511"); + } + + } /* end of arc fla_obs_i[1]_ast2padmux_o[1]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[10]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.443642, 0.510546, 0.626985, 0.946654, 1.801858",\ + "0.465905, 0.532810, 0.649248, 0.968917, 1.824121",\ + "0.522299, 0.589203, 0.705642, 1.025311, 1.880515",\ + "0.620162, 0.687066, 0.803505, 1.123173, 1.978378",\ + "1.134534, 1.201443, 1.317885, 1.637554, 2.492753"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\ + "0.073042, 0.188941, 0.391856, 0.949133, 2.441345"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.490585, 0.522017, 0.574725, 0.717078, 1.095675",\ + "0.512119, 0.543551, 0.596259, 0.738612, 1.117209",\ + "0.579305, 0.610737, 0.663445, 0.805798, 1.184395",\ + "0.689604, 0.721035, 0.773743, 0.916096, 1.294693",\ + "1.248357, 1.279789, 1.332497, 1.474850, 1.853447"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090836"); + } + + } /* end of arc obs_ctrl_o[10]_ast2padmux_o[1]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[10]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.412827, 0.479717, 0.596144, 0.915812, 1.771032",\ + "0.433604, 0.500495, 0.616922, 0.936590, 1.791810",\ + "0.491196, 0.558086, 0.674513, 0.994181, 1.849401",\ + "0.589141, 0.656031, 0.772458, 1.092126, 1.947346",\ + "1.077990, 1.144880, 1.261307, 1.580975, 2.436195"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.392762, 0.424174, 0.476820, 0.619235, 0.997878",\ + "0.410167, 0.441580, 0.494226, 0.636641, 1.015284",\ + "0.482737, 0.514149, 0.566795, 0.709210, 1.087853",\ + "0.595371, 0.626784, 0.679430, 0.821845, 1.200488",\ + "1.122399, 1.153812, 1.206458, 1.348872, 1.727516"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687"); + } + + } /* end of arc obs_ctrl_o[10]_ast2padmux_o[1]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[10]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.437382, 0.468814, 0.521522, 0.663875, 1.042472",\ + "0.462451, 0.493883, 0.546591, 0.688944, 1.067541",\ + "0.531672, 0.563103, 0.615812, 0.758164, 1.136761",\ + "0.655903, 0.687335, 0.740043, 0.882396, 1.260993",\ + "1.288504, 1.319936, 1.372644, 1.514997, 1.893594"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090836"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.675759, 0.742664, 0.859102, 1.178771, 2.033976",\ + "0.696234, 0.763138, 0.879577, 1.199246, 2.054450",\ + "0.755094, 0.821998, 0.938437, 1.258106, 2.113310",\ + "0.864334, 0.931238, 1.047677, 1.367346, 2.222550",\ + "1.641748, 1.708657, 1.825099, 2.144769, 2.999968"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\ + "0.073042, 0.188941, 0.391856, 0.949133, 2.441345"); + } + + } /* end of arc obs_ctrl_o[10]_ast2padmux_o[1]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[10]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.262392, 0.293804, 0.346450, 0.488865, 0.867508",\ + "0.286002, 0.317414, 0.370060, 0.512475, 0.891118",\ + "0.357340, 0.388753, 0.441399, 0.583814, 0.962457",\ + "0.477148, 0.508560, 0.561206, 0.703621, 1.082264",\ + "1.022245, 1.053658, 1.106303, 1.248718, 1.627362"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.582342, 0.649232, 0.765660, 1.085328, 1.940547",\ + "0.599034, 0.665924, 0.782351, 1.102020, 1.957239",\ + "0.661428, 0.728319, 0.844746, 1.164414, 2.019634",\ + "0.770818, 0.837708, 0.954135, 1.273803, 2.129023",\ + "1.507966, 1.574856, 1.691283, 2.010951, 2.866171"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330"); + } + + } /* end of arc obs_ctrl_o[10]_ast2padmux_o[1]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[11]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.034927, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.180024, 0.211452, 0.264149, 0.406513, 0.785119",\ + "0.193406, 0.224834, 0.277531, 0.419896, 0.798501",\ + "0.275919, 0.307349, 0.360051, 0.502410, 0.881011",\ + "0.400910, 0.432352, 0.485095, 0.627414, 1.005985",\ + "0.975060, 1.010086, 1.063144, 1.205732, 1.584486"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.034927, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039119, 0.090633, 0.180636, 0.429262, 1.090996",\ + "0.039119, 0.090633, 0.180636, 0.429262, 1.090996",\ + "0.039132, 0.090633, 0.180667, 0.429269, 1.090996",\ + "0.039215, 0.090633, 0.180868, 0.429314, 1.090996",\ + "0.049347, 0.094034, 0.180868, 0.429355, 1.091896"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037147, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.465437, 0.532662, 0.649281, 0.969044, 1.824018",\ + "0.477695, 0.544920, 0.661539, 0.981302, 1.836276",\ + "0.541916, 0.609140, 0.725760, 1.045521, 1.900495",\ + "0.644626, 0.711856, 0.828474, 1.148242, 2.003221",\ + "1.319722, 1.387140, 1.503696, 1.823662, 2.678811"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037147, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073817, 0.189281, 0.392442, 0.950607, 2.441526",\ + "0.073817, 0.189281, 0.392442, 0.950607, 2.441526",\ + "0.073817, 0.189282, 0.392442, 0.950607, 2.441526",\ + "0.073862, 0.189282, 0.392442, 0.950619, 2.441526",\ + "0.075399, 0.189282, 0.392442, 0.951039, 2.441526"); + } + + } /* end of arc obs_ctrl_o[11]_ast2padmux_o[1]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[11]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.030664, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.159139, 0.190553, 0.243202, 0.385613, 0.764254",\ + "0.170514, 0.201928, 0.254577, 0.396989, 0.775629",\ + "0.255576, 0.286993, 0.339652, 0.482053, 0.860686",\ + "0.379908, 0.411340, 0.464049, 0.606401, 0.984998",\ + "0.945167, 0.979651, 1.032663, 1.175209, 1.553933"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.030664, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039020, 0.090609, 0.180397, 0.429208, 1.090831",\ + "0.039020, 0.090609, 0.180397, 0.429208, 1.090831",\ + "0.039042, 0.090609, 0.180449, 0.429220, 1.090831",\ + "0.039144, 0.090609, 0.180675, 0.429276, 1.090831",\ + "0.047820, 0.093501, 0.180675, 0.429352, 1.091629"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.028580, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.461683, 0.528880, 0.645509, 0.965243, 1.820192",\ + "0.470327, 0.537524, 0.654153, 0.973887, 1.828836",\ + "0.538174, 0.605371, 0.721999, 1.041733, 1.896681",\ + "0.640782, 0.707985, 0.824611, 1.144351, 1.999304",\ + "1.312551, 1.379913, 1.496487, 1.816396, 2.671496"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.028580, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073594, 0.189124, 0.392388, 0.950544, 2.441454",\ + "0.073594, 0.189124, 0.392388, 0.950544, 2.441454",\ + "0.073594, 0.189124, 0.392388, 0.950544, 2.441454",\ + "0.073633, 0.189124, 0.392388, 0.950557, 2.441454",\ + "0.074954, 0.189124, 0.392388, 0.950917, 2.441454"); + } + + } /* end of arc obs_ctrl_o[11]_ast2padmux_o[1]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.500858, 0.568082, 0.684702, 1.004464, 1.859437",\ + "0.516623, 0.583848, 0.700467, 1.020230, 1.875203",\ + "0.590734, 0.657958, 0.774578, 1.094340, 1.949314",\ + "0.681946, 0.749171, 0.865790, 1.185553, 2.040526",\ + "1.108576, 1.175805, 1.292423, 1.612190, 2.467167"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073816, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073848, 0.189277, 0.392440, 0.950615, 2.441524"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.275118, 0.306284, 0.358903, 0.501398, 0.880041",\ + "0.290749, 0.321915, 0.374533, 0.517029, 0.895671",\ + "0.363703, 0.394869, 0.447488, 0.589983, 0.968626",\ + "0.474794, 0.505959, 0.558577, 0.701073, 1.079716",\ + "1.013269, 1.044421, 1.097036, 1.239541, 1.618177"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040759, 0.090626, 0.180653, 0.429266, 1.092499",\ + "0.040922, 0.090525, 0.180916, 0.429325, 1.092539"); + } + + } /* end of arc obs_ctrl_o[4]_ast2padmux_o[1]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.337608, 0.404302, 0.520641, 0.837429, 1.687203",\ + "0.349939, 0.416633, 0.532972, 0.849760, 1.699534",\ + "0.408752, 0.475446, 0.591785, 0.908573, 1.758347",\ + "0.496083, 0.562777, 0.679117, 0.995905, 1.845678",\ + "0.949078, 1.015776, 1.132136, 1.448920, 2.298678"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184560, 0.382485, 0.937098, 2.417677",\ + "0.067604, 0.184551, 0.382483, 0.937052, 2.417689"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.209985, 0.241400, 0.294052, 0.436461, 0.815099",\ + "0.221857, 0.253271, 0.305923, 0.448332, 0.826970",\ + "0.304351, 0.335766, 0.388417, 0.530826, 0.909465",\ + "0.409226, 0.440642, 0.493298, 0.635702, 1.014338",\ + "0.909442, 0.940877, 0.993596, 1.135938, 1.514527"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039034, 0.090327, 0.180161, 0.428971, 1.091542",\ + "0.039166, 0.090324, 0.180166, 0.428948, 1.090692"); + } + + } /* end of arc obs_ctrl_o[4]_ast2padmux_o[1]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.287803, 0.318969, 0.371587, 0.514083, 0.892726",\ + "0.303569, 0.334734, 0.387353, 0.529848, 0.908491",\ + "0.378810, 0.409975, 0.462594, 0.605089, 0.983732",\ + "0.473884, 0.505049, 0.557668, 0.700163, 1.078806",\ + "0.918190, 0.949342, 1.001956, 1.144462, 1.523098"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040759, 0.090626, 0.180653, 0.429266, 1.092499",\ + "0.040922, 0.090525, 0.180916, 0.429325, 1.092539"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.376755, 0.443500, 0.560063, 0.876818, 1.726409",\ + "0.392417, 0.459162, 0.575725, 0.892480, 1.742071",\ + "0.467424, 0.534169, 0.650732, 0.967487, 1.817078",\ + "0.562603, 0.629351, 0.745928, 1.062681, 1.912261",\ + "1.006927, 1.073706, 1.190415, 1.507149, 2.356620"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073816, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073848, 0.189277, 0.392440, 0.950615, 2.441524"); + } + + } /* end of arc obs_ctrl_o[4]_ast2padmux_o[1]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.264318, 0.295567, 0.348210, 0.490643, 0.869326",\ + "0.278489, 0.309737, 0.362381, 0.504814, 0.883496",\ + "0.355325, 0.386573, 0.439217, 0.581649, 0.960332",\ + "0.450369, 0.481617, 0.534260, 0.676693, 1.055376",\ + "0.893831, 0.925076, 0.977718, 1.120154, 1.498834"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039034, 0.090327, 0.180161, 0.428971, 1.091542",\ + "0.039166, 0.090324, 0.180166, 0.428948, 1.090692"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.373701, 0.440395, 0.556734, 0.873522, 1.723296",\ + "0.385572, 0.452266, 0.568605, 0.885393, 1.735167",\ + "0.464371, 0.531065, 0.647404, 0.964192, 1.813966",\ + "0.559385, 0.626079, 0.742420, 1.059207, 1.908981",\ + "1.002245, 1.068944, 1.185303, 1.502088, 2.351846"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184560, 0.382485, 0.937098, 2.417677",\ + "0.067604, 0.184551, 0.382483, 0.937052, 2.417689"); + } + + } /* end of arc obs_ctrl_o[4]_ast2padmux_o[1]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.337998, 0.404744, 0.521308, 0.838063, 1.687653",\ + "0.353177, 0.419923, 0.536487, 0.853242, 1.702832",\ + "0.412195, 0.478941, 0.595505, 0.912260, 1.761850",\ + "0.508449, 0.575199, 0.691783, 1.008535, 1.858109",\ + "0.997007, 1.063817, 1.180658, 1.497372, 2.346736"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\ + "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073887, 0.189271, 0.392439, 0.950626, 2.441522",\ + "0.075818, 0.189005, 0.392348, 0.951153, 2.441399"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.272032, 0.303198, 0.355817, 0.498312, 0.876955",\ + "0.289891, 0.321056, 0.373675, 0.516170, 0.894813",\ + "0.360955, 0.392121, 0.444739, 0.587235, 0.965878",\ + "0.471378, 0.502542, 0.555160, 0.697656, 1.076298",\ + "1.004117, 1.035227, 1.087829, 1.230366, 1.608983"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\ + "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\ + "0.040752, 0.090633, 0.180666, 0.429269, 1.092497",\ + "0.040771, 0.090633, 0.180871, 0.429315, 1.092502",\ + "0.049622, 0.094130, 0.180871, 0.429356, 1.092666"); + } + + } /* end of arc obs_ctrl_o[5]_ast2padmux_o[1]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.329221, 0.395915, 0.512254, 0.829041, 1.678816",\ + "0.344592, 0.411286, 0.527624, 0.844412, 1.694187",\ + "0.406780, 0.473474, 0.589813, 0.906601, 1.756375",\ + "0.502234, 0.568932, 0.685288, 1.002073, 1.851833",\ + "0.957622, 1.024367, 1.140929, 1.457685, 2.307276"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067607, 0.184553, 0.382483, 0.937060, 2.417687",\ + "0.067439, 0.184458, 0.382464, 0.936568, 2.417820"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.231492, 0.262740, 0.315383, 0.457816, 0.836499",\ + "0.245351, 0.276600, 0.329243, 0.471676, 0.850359",\ + "0.320124, 0.351372, 0.404016, 0.546449, 0.925131",\ + "0.430166, 0.461410, 0.514053, 0.656489, 1.035169",\ + "0.955028, 0.986237, 1.038869, 1.181331, 1.559995"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039041, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039146, 0.090294, 0.180167, 0.428752, 1.090822",\ + "0.040211, 0.090294, 0.180212, 0.428752, 1.091676"); + } + + } /* end of arc obs_ctrl_o[5]_ast2padmux_o[1]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[5]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.176901, 0.208329, 0.261026, 0.403390, 0.781996",\ + "0.196158, 0.227585, 0.280282, 0.422647, 0.801252",\ + "0.273304, 0.304734, 0.357436, 0.499795, 0.878396",\ + "0.397207, 0.428649, 0.481392, 0.623711, 1.002282",\ + "0.961790, 0.996912, 1.049978, 1.192575, 1.571334"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\ + "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\ + "0.040752, 0.090633, 0.180666, 0.429269, 1.092497",\ + "0.040771, 0.090633, 0.180871, 0.429315, 1.092502",\ + "0.049622, 0.094130, 0.180871, 0.429356, 1.092666"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.455825, 0.523049, 0.639668, 0.959430, 1.814404",\ + "0.468963, 0.536187, 0.652807, 0.972569, 1.827542",\ + "0.531289, 0.598514, 0.715133, 1.034896, 1.889869",\ + "0.640154, 0.707387, 0.824004, 1.143775, 1.998757",\ + "1.332501, 1.399969, 1.516508, 1.836528, 2.691724"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\ + "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073887, 0.189271, 0.392439, 0.950626, 2.441522",\ + "0.075818, 0.189005, 0.392348, 0.951153, 2.441399"); + } + + } /* end of arc obs_ctrl_o[5]_ast2padmux_o[1]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[5]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.155833, 0.187247, 0.239896, 0.382308, 0.760949",\ + "0.173482, 0.204896, 0.257545, 0.399957, 0.778598",\ + "0.252964, 0.284381, 0.337040, 0.479441, 0.858074",\ + "0.376196, 0.407628, 0.460337, 0.602689, 0.981285",\ + "0.931678, 0.966257, 1.019278, 1.161831, 1.540560"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039041, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039146, 0.090294, 0.180167, 0.428752, 1.090822",\ + "0.040211, 0.090294, 0.180212, 0.428752, 1.091676"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.452081, 0.519278, 0.635907, 0.955640, 1.810589",\ + "0.461862, 0.529059, 0.645688, 0.965421, 1.820370",\ + "0.527542, 0.594739, 0.711368, 1.031102, 1.886050",\ + "0.636262, 0.703467, 0.820093, 1.139835, 1.994791",\ + "1.324350, 1.391756, 1.508316, 1.828270, 2.683409"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067607, 0.184553, 0.382483, 0.937060, 2.417687",\ + "0.067439, 0.184458, 0.382464, 0.936568, 2.417820"); + } + + } /* end of arc obs_ctrl_o[5]_ast2padmux_o[1]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[6]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.325984, 0.393209, 0.509828, 0.829592, 1.684567",\ + "0.341732, 0.408957, 0.525576, 0.845340, 1.700314",\ + "0.405621, 0.472847, 0.589466, 0.909229, 1.764204",\ + "0.483984, 0.551208, 0.667827, 0.987590, 1.842564",\ + "0.876566, 0.943791, 1.060410, 1.380173, 2.235147"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189281, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189281, 0.392442, 0.950608, 2.441526"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.207560, 0.238992, 0.291700, 0.434053, 0.812650",\ + "0.223441, 0.254873, 0.307582, 0.449934, 0.828531",\ + "0.292964, 0.324396, 0.377105, 0.519457, 0.898054",\ + "0.382304, 0.413736, 0.466444, 0.608797, 0.987394",\ + "0.808201, 0.839636, 0.892354, 1.034697, 1.413287"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\ + "0.040785, 0.090610, 0.180744, 0.429286, 1.092505"); + } + + } /* end of arc obs_ctrl_o[6]_ast2padmux_o[1]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[6]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.298728, 0.365697, 0.482189, 0.801862, 1.656989",\ + "0.312838, 0.379807, 0.496299, 0.815972, 1.671100",\ + "0.378416, 0.445385, 0.561877, 0.881551, 1.736677",\ + "0.456978, 0.523948, 0.640441, 0.960115, 1.815240",\ + "0.852482, 0.919491, 1.036016, 1.355692, 2.210772"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067586, 0.184541, 0.382481, 0.936998, 2.417704"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.185526, 0.216941, 0.269593, 0.412001, 0.790640",\ + "0.197528, 0.228943, 0.281595, 0.424004, 0.802642",\ + "0.270950, 0.302365, 0.355017, 0.497425, 0.876064",\ + "0.360375, 0.391790, 0.444442, 0.586850, 0.965489",\ + "0.786063, 0.817479, 0.870138, 1.012540, 1.391174"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039039, 0.090322, 0.180169, 0.428938, 1.091513"); + } + + } /* end of arc obs_ctrl_o[6]_ast2padmux_o[1]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[6]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.314064, 0.345229, 0.397848, 0.540343, 0.918986",\ + "0.329859, 0.361025, 0.413644, 0.556139, 0.934782",\ + "0.407724, 0.438890, 0.491508, 0.634004, 1.012646",\ + "0.508778, 0.539944, 0.592562, 0.735058, 1.113701",\ + "0.984655, 1.015818, 1.068436, 1.210933, 1.589574"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\ + "0.040785, 0.090610, 0.180744, 0.429286, 1.092505"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.596327, 0.663552, 0.780171, 1.099935, 1.954909",\ + "0.609131, 0.676356, 0.792975, 1.112739, 1.967713",\ + "0.677113, 0.744339, 0.860958, 1.180721, 2.035696",\ + "0.788810, 0.856034, 0.972654, 1.292416, 2.147390",\ + "1.273667, 1.340892, 1.457511, 1.777274, 2.632248"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189281, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189281, 0.392442, 0.950608, 2.441526"); + } + + } /* end of arc obs_ctrl_o[6]_ast2padmux_o[1]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[6]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.262848, 0.294262, 0.346915, 0.489323, 0.867962",\ + "0.276998, 0.308413, 0.361065, 0.503474, 0.882112",\ + "0.356726, 0.388141, 0.440793, 0.583202, 0.961840",\ + "0.457948, 0.489362, 0.542015, 0.684423, 1.063061",\ + "0.929777, 0.961193, 1.013852, 1.156254, 1.534888"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039039, 0.090322, 0.180169, 0.428938, 1.091513"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.437011, 0.503705, 0.620045, 0.936832, 1.786606",\ + "0.446608, 0.513302, 0.629642, 0.946429, 1.796203",\ + "0.517780, 0.584475, 0.700814, 1.017602, 1.867376",\ + "0.629396, 0.696091, 0.812430, 1.129218, 1.978992",\ + "1.131911, 1.198614, 1.314996, 1.631778, 2.481517"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067586, 0.184541, 0.382481, 0.936998, 2.417704"); + } + + } /* end of arc obs_ctrl_o[6]_ast2padmux_o[1]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[7]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.060518, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.315427, 0.346593, 0.399212, 0.541707, 0.920350",\ + "0.342146, 0.373312, 0.425930, 0.568426, 0.947068",\ + "0.410184, 0.441350, 0.493968, 0.636464, 1.015106",\ + "0.512927, 0.544093, 0.596711, 0.739207, 1.117850",\ + "0.999580, 1.030743, 1.083361, 1.225858, 1.604500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.060518, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180697, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180697, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180697, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180732, 0.429283, 1.092497",\ + "0.042004, 0.091469, 0.180867, 0.429340, 1.092504"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.051005, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.597332, 0.664558, 0.781177, 1.100940, 1.955915",\ + "0.618079, 0.685305, 0.801924, 1.121688, 1.976662",\ + "0.683404, 0.750630, 0.867249, 1.187012, 2.041987",\ + "0.797603, 0.864828, 0.981447, 1.301210, 2.156184",\ + "1.375793, 1.443018, 1.559637, 1.879400, 2.734374"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.051005, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189280, 0.392442, 0.950609, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073823, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073819, 0.189281, 0.392442, 0.950607, 2.441526",\ + "0.073817, 0.189281, 0.392442, 0.950607, 2.441526"); + } + + } /* end of arc obs_ctrl_o[7]_ast2padmux_o[1]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[7]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.049671, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.150722, 0.182137, 0.234789, 0.377197, 0.755836",\ + "0.171205, 0.202620, 0.255272, 0.397681, 0.776319",\ + "0.246518, 0.277932, 0.330585, 0.472993, 0.851631",\ + "0.352324, 0.383738, 0.436391, 0.578799, 0.957437",\ + "0.825559, 0.856975, 0.909634, 1.052036, 1.430670"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.049671, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039038, 0.090323, 0.180168, 0.428941, 1.091519"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040467, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.277343, 0.344312, 0.460804, 0.780477, 1.635605",\ + "0.293355, 0.360323, 0.476815, 0.796489, 1.651616",\ + "0.366113, 0.433085, 0.549579, 0.869253, 1.724376",\ + "0.487008, 0.554003, 0.670516, 0.990192, 1.845287",\ + "1.141953, 1.209132, 1.325766, 1.645481, 2.500414"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040467, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067601, 0.184550, 0.382483, 0.937044, 2.417691"); + } + + } /* end of arc obs_ctrl_o[7]_ast2padmux_o[1]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[8]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.700503, 0.767407, 0.883846, 1.203515, 2.058719",\ + "0.718853, 0.785757, 0.902195, 1.221864, 2.077069",\ + "0.789396, 0.856300, 0.972739, 1.292408, 2.147612",\ + "0.881867, 0.948772, 1.065210, 1.384879, 2.240083",\ + "1.366874, 1.433786, 1.550230, 1.869900, 2.725095"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073043, 0.188945, 0.391861, 0.949146, 2.441348"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.488066, 0.519497, 0.572205, 0.714558, 1.093155",\ + "0.505493, 0.536925, 0.589633, 0.731986, 1.110583",\ + "0.582890, 0.614322, 0.667030, 0.809383, 1.187980",\ + "0.691204, 0.722635, 0.775344, 0.917696, 1.296293",\ + "1.242374, 1.273805, 1.326514, 1.468867, 1.847463"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090836"); + } + + } /* end of arc obs_ctrl_o[8]_ast2padmux_o[1]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[8]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.636502, 0.703393, 0.819820, 1.139488, 1.994708",\ + "0.653118, 0.720008, 0.836435, 1.156103, 2.011323",\ + "0.727539, 0.794429, 0.910857, 1.230525, 2.085744",\ + "0.821960, 0.888850, 1.005277, 1.324945, 2.180165",\ + "1.269718, 1.336608, 1.453035, 1.772703, 2.627923"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.339768, 0.371181, 0.423827, 0.566242, 0.944885",\ + "0.353114, 0.384527, 0.437173, 0.579588, 0.958231",\ + "0.435092, 0.466504, 0.519150, 0.661565, 1.040208",\ + "0.544311, 0.575724, 0.628370, 0.770784, 1.149428",\ + "1.067931, 1.099343, 1.151989, 1.294404, 1.673047"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687"); + } + + } /* end of arc obs_ctrl_o[8]_ast2padmux_o[1]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[8]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.524400, 0.555831, 0.608540, 0.750893, 1.129489",\ + "0.542749, 0.574181, 0.626889, 0.769242, 1.147839",\ + "0.616605, 0.648037, 0.700745, 0.843098, 1.221695",\ + "0.714865, 0.746296, 0.799004, 0.941357, 1.319954",\ + "1.237234, 1.268665, 1.321373, 1.463726, 1.842323"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090836"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.651244, 0.718149, 0.834587, 1.154256, 2.009460",\ + "0.663867, 0.730771, 0.847209, 1.166878, 2.022083",\ + "0.718781, 0.785685, 0.902124, 1.221793, 2.076997",\ + "0.821201, 0.888105, 1.004544, 1.324213, 2.179417",\ + "1.548479, 1.615391, 1.731835, 2.051504, 2.906700"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073043, 0.188945, 0.391861, 0.949146, 2.441348"); + } + + } /* end of arc obs_ctrl_o[8]_ast2padmux_o[1]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[8]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.267796, 0.299208, 0.351854, 0.494269, 0.872912",\ + "0.284541, 0.315954, 0.368600, 0.511015, 0.889658",\ + "0.362798, 0.394211, 0.446856, 0.589271, 0.967914",\ + "0.486677, 0.518090, 0.570736, 0.713151, 1.091794",\ + "1.055266, 1.086678, 1.139324, 1.281739, 1.660382"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.456335, 0.523226, 0.639653, 0.959321, 1.814541",\ + "0.469682, 0.536572, 0.652999, 0.972667, 1.827887",\ + "0.547821, 0.614711, 0.731138, 1.050806, 1.906026",\ + "0.649000, 0.715890, 0.832317, 1.151985, 2.007205",\ + "1.120855, 1.187745, 1.304172, 1.623840, 2.479060"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330"); + } + + } /* end of arc obs_ctrl_o[8]_ast2padmux_o[1]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[9]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.712314, 0.779218, 0.895657, 1.215326, 2.070530",\ + "0.730867, 0.797771, 0.914210, 1.233879, 2.089083",\ + "0.803565, 0.870469, 0.986908, 1.306577, 2.161781",\ + "0.898790, 0.965694, 1.082133, 1.401802, 2.257006",\ + "1.358120, 1.425029, 1.541471, 1.861141, 2.716340"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073041, 0.188941, 0.391855, 0.949133, 2.441345"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.494441, 0.525873, 0.578581, 0.720934, 1.099531",\ + "0.511983, 0.543415, 0.596123, 0.738476, 1.117073",\ + "0.589312, 0.620744, 0.673452, 0.815805, 1.194402",\ + "0.698758, 0.730189, 0.782897, 0.925250, 1.303847",\ + "1.229663, 1.261095, 1.313803, 1.456156, 1.834753"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090836"); + } + + } /* end of arc obs_ctrl_o[9]_ast2padmux_o[1]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[9]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.668630, 0.735520, 0.851947, 1.171615, 2.026835",\ + "0.685451, 0.752341, 0.868768, 1.188436, 2.043656",\ + "0.759882, 0.826773, 0.943200, 1.262868, 2.118088",\ + "0.855138, 0.922028, 1.038455, 1.358123, 2.213343",\ + "1.307789, 1.374679, 1.491106, 1.810774, 2.665994"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.361699, 0.393111, 0.445757, 0.588172, 0.966815",\ + "0.375155, 0.406568, 0.459214, 0.601628, 0.980272",\ + "0.456576, 0.487988, 0.540634, 0.683049, 1.061692",\ + "0.566550, 0.597963, 0.650609, 0.793024, 1.171667",\ + "1.091986, 1.123399, 1.176044, 1.318459, 1.697102"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687"); + } + + } /* end of arc obs_ctrl_o[9]_ast2padmux_o[1]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[9]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.528266, 0.559698, 0.612406, 0.754759, 1.133356",\ + "0.546819, 0.578250, 0.630959, 0.773312, 1.151908",\ + "0.620877, 0.652309, 0.705017, 0.847370, 1.225967",\ + "0.719978, 0.751410, 0.804118, 0.946471, 1.325068",\ + "1.192613, 1.224045, 1.276753, 1.419106, 1.797703"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090836"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.606303, 0.673207, 0.789646, 1.109315, 1.964519",\ + "0.618992, 0.685897, 0.802335, 1.122004, 1.977208",\ + "0.673763, 0.740668, 0.857106, 1.176775, 2.031980",\ + "0.776802, 0.843707, 0.960145, 1.279814, 2.135018",\ + "1.483718, 1.550627, 1.667069, 1.986738, 2.841937"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073041, 0.188941, 0.391855, 0.949133, 2.441345"); + } + + } /* end of arc obs_ctrl_o[9]_ast2padmux_o[1]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[9]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.262699, 0.294112, 0.346758, 0.489173, 0.867816",\ + "0.279513, 0.310926, 0.363572, 0.505987, 0.884630",\ + "0.357852, 0.389264, 0.441910, 0.584325, 0.962968",\ + "0.480383, 0.511796, 0.564441, 0.706856, 1.085500",\ + "1.037548, 1.068961, 1.121607, 1.264022, 1.642665"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.463612, 0.530502, 0.646929, 0.966597, 1.821817",\ + "0.477068, 0.543958, 0.660386, 0.980054, 1.835274",\ + "0.555357, 0.622247, 0.738674, 1.058342, 1.913562",\ + "0.655033, 0.721923, 0.838350, 1.158018, 2.013238",\ + "1.119877, 1.186768, 1.303195, 1.622863, 2.478083"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330"); + } + + } /* end of arc obs_ctrl_o[9]_ast2padmux_o[1]_inv_min*/ + + timing () { + related_pin : "otm_obs_i[1]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.123879, 0.190820, 0.307288, 0.626960, 1.482121",\ + "0.210891, 0.277978, 0.394567, 0.714249, 1.569235",\ + "0.301781, 0.369068, 0.485667, 0.805496, 1.660526",\ + "0.453978, 0.523120, 0.640034, 0.960158, 1.815427",\ + "0.695902, 0.774527, 0.893732, 1.214148, 2.069560"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073065, 0.188997, 0.391936, 0.949305, 2.441374",\ + "0.073175, 0.189249, 0.392304, 0.950092, 2.441498",\ + "0.074330, 0.189249, 0.392418, 0.950747, 2.441498",\ + "0.079436, 0.191164, 0.392505, 0.951076, 2.441498",\ + "0.098084, 0.204137, 0.393542, 0.951076, 2.441498"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.114293, 0.145721, 0.198417, 0.340782, 0.719388",\ + "0.205394, 0.236828, 0.289545, 0.431889, 0.810480",\ + "0.309904, 0.342065, 0.394885, 0.537244, 0.915841",\ + "0.501618, 0.536979, 0.590065, 0.732680, 1.111452",\ + "0.825607, 0.870622, 0.930343, 1.075147, 1.454209"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039117, 0.090634, 0.180632, 0.429261, 1.091005",\ + "0.039161, 0.090634, 0.180739, 0.429285, 1.091005",\ + "0.041267, 0.091212, 0.180891, 0.429338, 1.091005",\ + "0.050293, 0.094364, 0.180891, 0.429357, 1.092061",\ + "0.068556, 0.114740, 0.192215, 0.429716, 1.093122"); + } + + } /* end of arc otm_obs_i[1]_ast2padmux_o[1]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "otm_obs_i[1]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.120559, 0.187489, 0.303948, 0.623619, 1.478793",\ + "0.205712, 0.272774, 0.389342, 0.709022, 1.564038",\ + "0.292652, 0.359907, 0.476516, 0.796311, 1.651312",\ + "0.437434, 0.505450, 0.622092, 0.942182, 1.797434",\ + "0.662107, 0.738115, 0.856688, 1.177023, 2.032395"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073057, 0.188977, 0.391908, 0.949245, 2.441364",\ + "0.073156, 0.189206, 0.392241, 0.949956, 2.441378",\ + "0.074065, 0.189247, 0.392382, 0.950255, 2.441378",\ + "0.077223, 0.189624, 0.392382, 0.950255, 2.441378",\ + "0.092938, 0.200557, 0.393255, 0.950255, 2.441468"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.094368, 0.125782, 0.178430, 0.320842, 0.699483",\ + "0.188259, 0.219683, 0.272369, 0.414744, 0.793358",\ + "0.291365, 0.323244, 0.376040, 0.518376, 0.896959",\ + "0.474009, 0.509208, 0.562280, 0.704883, 1.083646",\ + "0.777508, 0.822171, 0.881623, 1.026340, 1.405392"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039018, 0.090654, 0.180392, 0.429207, 1.090346",\ + "0.039096, 0.090654, 0.180581, 0.429249, 1.090346",\ + "0.040472, 0.090934, 0.180608, 0.429337, 1.090346",\ + "0.049836, 0.094205, 0.180608, 0.429356, 1.091981",\ + "0.067933, 0.113945, 0.191732, 0.429701, 1.093101"); + } + + } /* end of arc otm_obs_i[1]_ast2padmux_o[1]_una_min*/ + + timing () { + related_pin : "otp_obs_i[1]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.122660, 0.189370, 0.305783, 0.622560, 1.472274",\ + "0.209824, 0.276743, 0.394059, 0.710704, 1.559679",\ + "0.301920, 0.369023, 0.486415, 0.804486, 1.652417",\ + "0.455547, 0.524976, 0.642287, 0.962376, 1.809444",\ + "0.699992, 0.780922, 0.900058, 1.218756, 2.067549"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067561, 0.184527, 0.382478, 0.936925, 2.417724",\ + "0.067561, 0.184527, 0.382478, 0.936925, 2.418306",\ + "0.068683, 0.184527, 0.382544, 0.936925, 2.418306",\ + "0.075540, 0.185756, 0.383113, 0.940410, 2.418306",\ + "0.094401, 0.199857, 0.384817, 0.940410, 2.426093"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.114764, 0.145947, 0.198571, 0.341053, 0.719705",\ + "0.205629, 0.236785, 0.289401, 0.431904, 0.810542",\ + "0.310076, 0.342571, 0.395201, 0.537686, 0.916183",\ + "0.500896, 0.538360, 0.591093, 0.733386, 1.111456",\ + "0.820213, 0.870292, 0.933027, 1.077593, 1.455130"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040532, 0.090273, 0.180246, 0.428609, 1.092443",\ + "0.040870, 0.090273, 0.180281, 0.428609, 1.092443",\ + "0.045400, 0.092351, 0.180508, 0.428609, 1.092443",\ + "0.059558, 0.100025, 0.181106, 0.428872, 1.092443",\ + "0.087354, 0.133744, 0.204884, 0.431205, 1.092443"); + } + + } /* end of arc otp_obs_i[1]_ast2padmux_o[1]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "otp_obs_i[1]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.119334, 0.186028, 0.302368, 0.619155, 1.468929",\ + "0.204833, 0.271716, 0.388876, 0.705544, 1.554647",\ + "0.293319, 0.360401, 0.477846, 0.795625, 1.643707",\ + "0.440314, 0.508488, 0.625608, 0.945855, 1.792734",\ + "0.667813, 0.745674, 0.864272, 1.183300, 2.031636"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.183691, 0.382409, 0.935142, 2.413233",\ + "0.067620, 0.183691, 0.382409, 0.935142, 2.413233",\ + "0.068262, 0.183691, 0.382508, 0.936031, 2.413233",\ + "0.073482, 0.184226, 0.382946, 0.939859, 2.413233",\ + "0.089380, 0.196045, 0.384240, 0.939859, 2.423100"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.094521, 0.125776, 0.178422, 0.320849, 0.699535",\ + "0.188239, 0.219444, 0.272075, 0.414540, 0.793202",\ + "0.291550, 0.323577, 0.376197, 0.518700, 0.897237",\ + "0.473699, 0.510899, 0.563627, 0.705929, 1.084022",\ + "0.773733, 0.823401, 0.885774, 1.030256, 1.407808"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039633, 0.090291, 0.180152, 0.428296, 1.092222",\ + "0.040262, 0.090291, 0.180217, 0.428296, 1.092377",\ + "0.044064, 0.091627, 0.180452, 0.428296, 1.092425",\ + "0.058805, 0.099616, 0.181075, 0.428844, 1.092425",\ + "0.086478, 0.132591, 0.204027, 0.431125, 1.092425"); + } + + } /* end of arc otp_obs_i[1]_ast2padmux_o[1]_una_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380006.843750, 380006.906250, 380007.031250, 380007.343750, 380008.187500",\ + "380006.937500, 380007.000000, 380007.125000, 380007.437500, 380008.281250",\ + "380007.031250, 380007.093750, 380007.218750, 380007.531250, 380008.375000",\ + "380007.187500, 380007.250000, 380007.375000, 380007.687500, 380008.531250",\ + "380007.437500, 380007.500000, 380007.625000, 380007.937500, 380008.781250"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380006.562500, 380006.593750, 380006.656250, 380006.812500, 380007.187500",\ + "380006.656250, 380006.687500, 380006.750000, 380006.906250, 380007.281250",\ + "380006.781250, 380006.812500, 380006.875000, 380007.031250, 380007.406250",\ + "380006.968750, 380007.000000, 380007.062500, 380007.218750, 380007.593750",\ + "380007.281250, 380007.312500, 380007.375000, 380007.531250, 380007.906250"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.041204, 0.091190, 0.180893, 0.429338, 1.092497",\ + "0.041204, 0.091190, 0.180893, 0.429338, 1.092497",\ + "0.041204, 0.091190, 0.180893, 0.429338, 1.092497",\ + "0.041204, 0.091190, 0.180893, 0.429338, 1.092497",\ + "0.041204, 0.091190, 0.180893, 0.429338, 1.092497"); + } + + } /* end of arc padmux2ast_i[4]_ast2padmux_o[1]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380006.781250, 380006.843750, 380006.968750, 380007.281250, 380008.125000",\ + "380006.875000, 380006.937500, 380007.062500, 380007.375000, 380008.218750",\ + "380006.937500, 380007.000000, 380007.125000, 380007.437500, 380008.281250",\ + "380007.093750, 380007.156250, 380007.281250, 380007.593750, 380008.437500",\ + "380007.312500, 380007.375000, 380007.500000, 380007.812500, 380008.656250"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380006.437500, 380006.468750, 380006.500000, 380006.656250, 380007.031250",\ + "380006.531250, 380006.562500, 380006.593750, 380006.750000, 380007.125000",\ + "380006.625000, 380006.656250, 380006.687500, 380006.843750, 380007.218750",\ + "380006.812500, 380006.843750, 380006.875000, 380007.031250, 380007.406250",\ + "380007.062500, 380007.093750, 380007.125000, 380007.281250, 380007.656250"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967"); + } + + } /* end of arc padmux2ast_i[4]_ast2padmux_o[1]_una_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "970006.000000, 970006.062500, 970006.125000, 970006.250000, 970006.625000",\ + "970006.125000, 970006.187500, 970006.250000, 970006.375000, 970006.750000",\ + "970006.125000, 970006.187500, 970006.250000, 970006.375000, 970006.750000",\ + "970006.375000, 970006.437500, 970006.500000, 970006.625000, 970007.000000",\ + "970006.625000, 970006.687500, 970006.750000, 970006.875000, 970007.250000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.041204, 0.091190, 0.180893, 0.429338, 1.092497",\ + "0.041204, 0.091190, 0.180893, 0.429338, 1.092497",\ + "0.041204, 0.091190, 0.180893, 0.429338, 1.092497",\ + "0.041204, 0.091190, 0.180893, 0.429338, 1.092497",\ + "0.041204, 0.091190, 0.180893, 0.429338, 1.092497"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "970008.625000, 970008.687500, 970008.812500, 970009.125000, 970010.000000",\ + "970008.750000, 970008.812500, 970008.937500, 970009.250000, 970010.125000",\ + "970008.875000, 970008.937500, 970009.062500, 970009.375000, 970010.250000",\ + "970009.125000, 970009.187500, 970009.312500, 970009.625000, 970010.500000",\ + "970009.375000, 970009.437500, 970009.562500, 970009.875000, 970010.750000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526"); + } + + } /* end of arc padmux2ast_i[4]_ast2padmux_o[1]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380000.312500, 380000.312500, 380000.343750, 380000.406250, 380000.593750",\ + "380000.406250, 380000.406250, 380000.437500, 380000.500000, 380000.687500",\ + "380000.468750, 380000.468750, 380000.500000, 380000.562500, 380000.750000",\ + "380000.625000, 380000.625000, 380000.656250, 380000.718750, 380000.906250",\ + "380000.843750, 380000.843750, 380000.875000, 380000.937500, 380001.125000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380001.781250, 380001.812500, 380001.906250, 380002.187500, 380002.875000",\ + "380001.875000, 380001.906250, 380002.000000, 380002.281250, 380002.968750",\ + "380001.968750, 380002.000000, 380002.093750, 380002.375000, 380003.062500",\ + "380002.156250, 380002.187500, 380002.281250, 380002.562500, 380003.250000",\ + "380002.406250, 380002.437500, 380002.531250, 380002.812500, 380003.500000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169"); + } + + } /* end of arc padmux2ast_i[4]_ast2padmux_o[1]_inv_min*/ + + timing () { + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "590007.000000, 590007.062500, 590007.187500, 590007.500000, 590008.375000",\ + "590007.125000, 590007.187500, 590007.312500, 590007.625000, 590008.500000",\ + "590007.125000, 590007.187500, 590007.312500, 590007.625000, 590008.500000",\ + "590007.250000, 590007.312500, 590007.437500, 590007.750000, 590008.625000",\ + "590007.500000, 590007.562500, 590007.687500, 590008.000000, 590008.875000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "590005.750000, 590005.812500, 590005.875000, 590006.000000, 590006.375000",\ + "590005.875000, 590005.937500, 590006.000000, 590006.125000, 590006.500000",\ + "590006.000000, 590006.062500, 590006.125000, 590006.250000, 590006.625000",\ + "590006.125000, 590006.187500, 590006.250000, 590006.375000, 590006.750000",\ + "590006.500000, 590006.562500, 590006.625000, 590006.750000, 590007.125000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.041204, 0.091190, 0.180893, 0.429338, 1.092497",\ + "0.041204, 0.091190, 0.180893, 0.429338, 1.092497",\ + "0.041204, 0.091190, 0.180893, 0.429338, 1.092497",\ + "0.041204, 0.091190, 0.180893, 0.429338, 1.092497",\ + "0.041204, 0.091190, 0.180893, 0.429338, 1.092497"); + } + + } /* end of arc padmux2ast_i[5]_ast2padmux_o[1]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "590006.875000, 590006.937500, 590007.062500, 590007.375000, 590008.187500",\ + "590006.875000, 590006.937500, 590007.062500, 590007.375000, 590008.187500",\ + "590007.000000, 590007.062500, 590007.187500, 590007.500000, 590008.312500",\ + "590007.125000, 590007.187500, 590007.312500, 590007.625000, 590008.437500",\ + "590007.375000, 590007.437500, 590007.562500, 590007.875000, 590008.687500"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067834, 0.184682, 0.382509, 0.937727, 2.417507",\ + "0.067834, 0.184682, 0.382509, 0.937727, 2.417507",\ + "0.067834, 0.184682, 0.382509, 0.937727, 2.417507",\ + "0.067834, 0.184682, 0.382509, 0.937727, 2.417507",\ + "0.067834, 0.184682, 0.382509, 0.937727, 2.417507"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "590005.687500, 590005.687500, 590005.750000, 590005.875000, 590006.312500",\ + "590005.812500, 590005.812500, 590005.875000, 590006.000000, 590006.437500",\ + "590005.937500, 590005.937500, 590006.000000, 590006.125000, 590006.562500",\ + "590006.062500, 590006.062500, 590006.125000, 590006.250000, 590006.687500",\ + "590006.312500, 590006.312500, 590006.375000, 590006.500000, 590006.937500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039018, 0.090351, 0.180124, 0.429131, 1.091647",\ + "0.039018, 0.090351, 0.180124, 0.429131, 1.091647",\ + "0.039018, 0.090351, 0.180124, 0.429131, 1.091647",\ + "0.039018, 0.090351, 0.180124, 0.429131, 1.091647",\ + "0.039018, 0.090351, 0.180124, 0.429131, 1.091647"); + } + + } /* end of arc padmux2ast_i[5]_ast2padmux_o[1]_una_min*/ + +} /* end of pin ast2padmux_o[1] */ + +pin("ast2padmux_o[0]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.028584 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : ast2padmux_o[0]; + timing () { + related_pin : "clk_ast_rng_i" ; + related_output_pin : "rng_val_o" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.000506, 0.073504, 0.160882, 0.321258, 0.642011"); + values ( "0.265266, 0.537827, 0.806617, 1.252725, 2.144939",\ + "0.332206, 0.604767, 0.873561, 1.319677, 2.211910",\ + "0.448674, 0.721235, 0.990031, 1.436155, 2.328403",\ + "0.768345, 1.040907, 1.309703, 1.755827, 2.648076",\ + "1.623507, 1.896068, 2.164861, 2.610974, 3.503201",\ + "0.323816, 0.596337, 0.865402, 1.310432, 2.201046",\ + "0.390756, 0.663277, 0.932346, 1.377385, 2.268016",\ + "0.507224, 0.779745, 1.048816, 1.493863, 2.384509",\ + "0.826895, 1.099417, 1.368488, 1.813535, 2.704183",\ + "1.682057, 1.954579, 2.223646, 2.668682, 3.559309",\ + "0.467311, 0.742155, 1.009298, 1.454188, 2.344779",\ + "0.534251, 0.809095, 1.076241, 1.521140, 2.411749",\ + "0.650718, 0.925563, 1.192712, 1.637618, 2.528242",\ + "0.970390, 1.245234, 1.512384, 1.957291, 2.847916",\ + "1.825552, 2.100396, 2.367542, 2.812438, 3.703041",\ + "0.502881, 0.779924, 1.046217, 1.490979, 2.381337",\ + "0.569821, 0.846864, 1.113161, 1.557931, 2.448308",\ + "0.686289, 0.963332, 1.229631, 1.674409, 2.564800",\ + "1.005960, 1.283003, 1.549303, 1.994082, 2.884474",\ + "1.861122, 2.138165, 2.404461, 2.849229, 3.739599",\ + "0.827836, 1.143899, 1.397858, 1.840240, 2.726793",\ + "0.894775, 1.210839, 1.464802, 1.907193, 2.793763",\ + "1.011243, 1.327307, 1.581273, 2.023671, 2.910256",\ + "1.330914, 1.646978, 1.900944, 2.343343, 3.229930",\ + "2.186077, 2.502140, 2.756102, 3.198490, 4.085055"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.000506, 0.073504, 0.160882, 0.321258, 0.642011"); + values ( "0.073065, 0.073065, 0.073067, 0.073074, 0.073087",\ + "0.188995, 0.188995, 0.189001, 0.189016, 0.189048",\ + "0.391933, 0.391934, 0.391942, 0.391965, 0.392010",\ + "0.949299, 0.949301, 0.949318, 0.949367, 0.949463",\ + "2.441373, 2.441374, 2.441376, 2.441384, 2.441401",\ + "0.073065, 0.073065, 0.073067, 0.073074, 0.073087",\ + "0.188995, 0.188995, 0.189001, 0.189016, 0.189048",\ + "0.391933, 0.391934, 0.391942, 0.391965, 0.392010",\ + "0.949299, 0.949301, 0.949318, 0.949367, 0.949463",\ + "2.441373, 2.441374, 2.441376, 2.441384, 2.441401",\ + "0.073065, 0.073065, 0.073067, 0.073074, 0.073087",\ + "0.188995, 0.188995, 0.189001, 0.189016, 0.189048",\ + "0.391933, 0.391934, 0.391942, 0.391965, 0.392010",\ + "0.949299, 0.949301, 0.949318, 0.949367, 0.949463",\ + "2.441373, 2.441374, 2.441376, 2.441384, 2.441401",\ + "0.073065, 0.073065, 0.073067, 0.073074, 0.073087",\ + "0.188995, 0.188995, 0.189001, 0.189016, 0.189048",\ + "0.391933, 0.391934, 0.391942, 0.391965, 0.392010",\ + "0.949299, 0.949301, 0.949318, 0.949367, 0.949463",\ + "2.441373, 2.441374, 2.441376, 2.441384, 2.441401",\ + "0.073065, 0.073065, 0.073067, 0.073074, 0.073087",\ + "0.188995, 0.188996, 0.189001, 0.189017, 0.189048",\ + "0.391933, 0.391935, 0.391943, 0.391965, 0.392010",\ + "0.949299, 0.949302, 0.949319, 0.949367, 0.949463",\ + "2.441373, 2.441374, 2.441376, 2.441385, 2.441401"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.000506, 0.073504, 0.160882, 0.321258, 0.642011"); + values ( "0.321682, 0.506101, 0.700572, 1.011955, 1.613898",\ + "0.353113, 0.537532, 0.732004, 1.043387, 1.645330",\ + "0.405822, 0.590241, 0.784712, 1.096096, 1.698039",\ + "0.548175, 0.732594, 0.927065, 1.238448, 1.840391",\ + "0.926771, 1.111190, 1.305661, 1.617045, 2.218987",\ + "0.381626, 0.565998, 0.760527, 1.071737, 1.673515",\ + "0.413058, 0.597430, 0.791958, 1.103168, 1.704947",\ + "0.465766, 0.650139, 0.844667, 1.155877, 1.757656",\ + "0.608119, 0.792491, 0.987020, 1.298229, 1.900008",\ + "0.986715, 1.171088, 1.365616, 1.676826, 2.278605",\ + "0.514234, 0.698252, 0.892410, 1.203594, 1.805323",\ + "0.545665, 0.729684, 0.923841, 1.235026, 1.836754",\ + "0.598374, 0.782393, 0.976550, 1.287735, 1.889464",\ + "0.740726, 0.924745, 1.118903, 1.430087, 2.031816",\ + "1.119323, 1.303342, 1.497499, 1.808684, 2.410412",\ + "0.547325, 0.731379, 0.925535, 1.236547, 1.837931",\ + "0.578757, 0.762811, 0.956967, 1.267979, 1.869363",\ + "0.631466, 0.815519, 1.009675, 1.320688, 1.922072",\ + "0.773818, 0.957872, 1.152028, 1.463040, 2.064424",\ + "1.152415, 1.336468, 1.530624, 1.841637, 2.443020",\ + "0.847275, 1.036618, 1.229172, 1.539564, 2.139780",\ + "0.878707, 1.068050, 1.260603, 1.570995, 2.171212",\ + "0.931415, 1.120758, 1.313312, 1.623704, 2.223921",\ + "1.073768, 1.263111, 1.455664, 1.766057, 2.366273",\ + "1.452364, 1.641707, 1.834261, 2.144653, 2.744869"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.000506, 0.073504, 0.160882, 0.321258, 0.642011"); + values ( "0.039144, 0.039144, 0.039144, 0.039144, 0.039145",\ + "0.090609, 0.090609, 0.090609, 0.090609, 0.090609",\ + "0.180697, 0.180697, 0.180697, 0.180698, 0.180700",\ + "0.429275, 0.429275, 0.429275, 0.429276, 0.429276",\ + "1.090832, 1.090832, 1.090832, 1.090832, 1.090832",\ + "0.039144, 0.039144, 0.039144, 0.039144, 0.039145",\ + "0.090609, 0.090609, 0.090609, 0.090609, 0.090609",\ + "0.180697, 0.180697, 0.180697, 0.180698, 0.180700",\ + "0.429275, 0.429275, 0.429275, 0.429276, 0.429276",\ + "1.090832, 1.090832, 1.090832, 1.090832, 1.090832",\ + "0.039144, 0.039144, 0.039144, 0.039144, 0.039145",\ + "0.090609, 0.090609, 0.090609, 0.090609, 0.090609",\ + "0.180697, 0.180697, 0.180697, 0.180698, 0.180700",\ + "0.429275, 0.429275, 0.429275, 0.429276, 0.429276",\ + "1.090832, 1.090832, 1.090832, 1.090832, 1.090832",\ + "0.039144, 0.039144, 0.039144, 0.039144, 0.039145",\ + "0.090609, 0.090609, 0.090609, 0.090609, 0.090609",\ + "0.180697, 0.180697, 0.180697, 0.180698, 0.180700",\ + "0.429275, 0.429275, 0.429275, 0.429276, 0.429276",\ + "1.090832, 1.090832, 1.090832, 1.090832, 1.090832",\ + "0.039144, 0.039144, 0.039144, 0.039144, 0.039145",\ + "0.090609, 0.090609, 0.090609, 0.090609, 0.090609",\ + "0.180697, 0.180697, 0.180697, 0.180698, 0.180700",\ + "0.429275, 0.429275, 0.429275, 0.429276, 0.429276",\ + "1.090832, 1.090832, 1.090832, 1.090832, 1.090832"); + } + + } /* end of arc clk_ast_rng_i_ast2padmux_o[0]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_rng_i" ; + related_output_pin : "rng_val_o" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.000506, 0.073504, 0.160882, 0.321258, 0.642011"); + values ( "0.258488, 0.527564, 0.791863, 1.230215, 2.105847",\ + "0.325417, 0.594493, 0.858794, 1.297152, 2.172797",\ + "0.441875, 0.710952, 0.975255, 1.413618, 2.289272",\ + "0.761546, 1.030622, 1.294926, 1.733289, 2.608944",\ + "1.616721, 1.885797, 2.150098, 2.588454, 3.464095",\ + "0.317013, 0.586065, 0.850631, 1.287923, 2.161954",\ + "0.383942, 0.652994, 0.917562, 1.354860, 2.228903",\ + "0.500401, 0.769453, 1.034023, 1.471326, 2.345379",\ + "0.820072, 1.089123, 1.353694, 1.790997, 2.665051",\ + "1.675247, 1.944298, 2.208866, 2.646162, 3.520202",\ + "0.460262, 0.731823, 0.994519, 1.431727, 2.305687",\ + "0.527191, 0.798752, 1.061450, 1.498664, 2.372636",\ + "0.643650, 0.915210, 1.177911, 1.615129, 2.489112",\ + "0.963321, 1.234881, 1.497581, 1.934801, 2.808784",\ + "1.818496, 2.090056, 2.352754, 2.789966, 3.663935",\ + "0.495756, 0.769563, 1.031437, 1.468598, 2.342245",\ + "0.562684, 0.836492, 1.098369, 1.535535, 2.409194",\ + "0.679143, 0.952951, 1.214829, 1.652000, 2.525670",\ + "0.998814, 1.272622, 1.534500, 1.971672, 2.845342",\ + "1.853989, 2.127797, 2.389672, 2.826837, 3.700493",\ + "0.819862, 1.132963, 1.383002, 1.817902, 2.687701",\ + "0.886791, 1.199892, 1.449933, 1.884839, 2.754651",\ + "1.003250, 1.316351, 1.566393, 2.001304, 2.871126",\ + "1.322921, 1.636022, 1.886065, 2.320976, 3.190798",\ + "2.178096, 2.491197, 2.741237, 3.176141, 4.045949"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.000506, 0.073504, 0.160882, 0.321258, 0.642011"); + values ( "0.073056, 0.073057, 0.073058, 0.073063, 0.073072",\ + "0.188976, 0.188976, 0.188980, 0.188990, 0.189011",\ + "0.391905, 0.391906, 0.391911, 0.391927, 0.391957",\ + "0.949239, 0.949241, 0.949252, 0.949284, 0.949349",\ + "2.441363, 2.441363, 2.441365, 2.441371, 2.441381",\ + "0.073056, 0.073057, 0.073058, 0.073063, 0.073072",\ + "0.188976, 0.188976, 0.188980, 0.188990, 0.189011",\ + "0.391905, 0.391906, 0.391911, 0.391927, 0.391957",\ + "0.949239, 0.949241, 0.949252, 0.949284, 0.949349",\ + "2.441363, 2.441363, 2.441365, 2.441371, 2.441381",\ + "0.073056, 0.073057, 0.073058, 0.073063, 0.073072",\ + "0.188976, 0.188976, 0.188980, 0.188990, 0.189011",\ + "0.391905, 0.391906, 0.391911, 0.391927, 0.391957",\ + "0.949239, 0.949241, 0.949252, 0.949284, 0.949349",\ + "2.441363, 2.441363, 2.441365, 2.441371, 2.441381",\ + "0.073056, 0.073057, 0.073058, 0.073063, 0.073072",\ + "0.188976, 0.188976, 0.188980, 0.188990, 0.189011",\ + "0.391905, 0.391906, 0.391911, 0.391927, 0.391957",\ + "0.949239, 0.949241, 0.949252, 0.949285, 0.949349",\ + "2.441363, 2.441363, 2.441365, 2.441371, 2.441381",\ + "0.073056, 0.073057, 0.073058, 0.073063, 0.073072",\ + "0.188976, 0.188976, 0.188980, 0.188990, 0.189011",\ + "0.391905, 0.391906, 0.391912, 0.391927, 0.391957",\ + "0.949239, 0.949241, 0.949252, 0.949285, 0.949349",\ + "2.441363, 2.441364, 2.441365, 2.441371, 2.441381"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.000506, 0.073504, 0.160882, 0.321258, 0.642011"); + values ( "0.280172, 0.467016, 0.660531, 0.967486, 1.558860",\ + "0.311589, 0.498432, 0.691948, 0.998903, 1.590277",\ + "0.364248, 0.551092, 0.744607, 1.051563, 1.642938",\ + "0.506650, 0.693493, 0.887008, 1.193964, 1.785338",\ + "0.885283, 1.072126, 1.265642, 1.572596, 2.163970",\ + "0.340116, 0.526843, 0.720376, 1.027255, 1.618477",\ + "0.371533, 0.558260, 0.751792, 1.058672, 1.649894",\ + "0.424192, 0.610919, 0.804452, 1.111332, 1.702555",\ + "0.566594, 0.753321, 0.946853, 1.253732, 1.844955",\ + "0.945227, 1.131954, 1.325486, 1.632365, 2.223587",\ + "0.472755, 0.659097, 0.852258, 1.159112, 1.750284",\ + "0.504172, 0.690514, 0.883675, 1.190529, 1.781701",\ + "0.556831, 0.743173, 0.936334, 1.243189, 1.834362",\ + "0.699233, 0.885575, 1.078736, 1.385590, 1.976762",\ + "1.077866, 1.264208, 1.457369, 1.764223, 2.355394",\ + "0.505869, 0.692396, 0.885489, 1.192192, 1.783144",\ + "0.537286, 0.723812, 0.916906, 1.223609, 1.814562",\ + "0.589945, 0.776472, 0.969565, 1.276269, 1.867223",\ + "0.732346, 0.918873, 1.111966, 1.418670, 2.009622",\ + "1.110980, 1.297506, 1.490599, 1.797303, 2.388254",\ + "0.806127, 0.997856, 1.189152, 1.495396, 2.085451",\ + "0.837544, 1.029273, 1.220569, 1.526813, 2.116868",\ + "0.890203, 1.081932, 1.273229, 1.579473, 2.169529",\ + "1.032604, 1.224334, 1.415630, 1.721874, 2.311929",\ + "1.411238, 1.602967, 1.794263, 2.100507, 2.690561"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.000506, 0.073504, 0.160882, 0.321258, 0.642011"); + values ( "0.039040, 0.039040, 0.039040, 0.039042, 0.039044",\ + "0.090707, 0.090706, 0.090706, 0.090705, 0.090703",\ + "0.180446, 0.180446, 0.180447, 0.180449, 0.180455",\ + "0.429219, 0.429219, 0.429219, 0.429220, 0.429221",\ + "1.091504, 1.091503, 1.091503, 1.091496, 1.091479",\ + "0.039040, 0.039040, 0.039040, 0.039042, 0.039044",\ + "0.090707, 0.090706, 0.090706, 0.090705, 0.090703",\ + "0.180446, 0.180446, 0.180447, 0.180449, 0.180455",\ + "0.429219, 0.429219, 0.429219, 0.429220, 0.429221",\ + "1.091504, 1.091503, 1.091503, 1.091496, 1.091479",\ + "0.039040, 0.039040, 0.039040, 0.039042, 0.039044",\ + "0.090707, 0.090706, 0.090706, 0.090705, 0.090703",\ + "0.180446, 0.180446, 0.180447, 0.180449, 0.180455",\ + "0.429219, 0.429219, 0.429219, 0.429220, 0.429221",\ + "1.091504, 1.091503, 1.091503, 1.091496, 1.091479",\ + "0.039040, 0.039040, 0.039040, 0.039042, 0.039044",\ + "0.090707, 0.090706, 0.090706, 0.090705, 0.090703",\ + "0.180446, 0.180446, 0.180447, 0.180449, 0.180455",\ + "0.429219, 0.429219, 0.429219, 0.429220, 0.429221",\ + "1.091504, 1.091503, 1.091503, 1.091496, 1.091479",\ + "0.039040, 0.039040, 0.039040, 0.039042, 0.039044",\ + "0.090706, 0.090706, 0.090706, 0.090705, 0.090703",\ + "0.180446, 0.180446, 0.180447, 0.180449, 0.180455",\ + "0.429219, 0.429219, 0.429219, 0.429220, 0.429221",\ + "1.091504, 1.091503, 1.091503, 1.091496, 1.091479"); + } + + } /* end of arc clk_ast_rng_i_ast2padmux_o[0]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380001.875000, 380001.937500, 380002.062500, 380002.375000, 380003.250000",\ + "380001.968750, 380002.031250, 380002.156250, 380002.468750, 380003.343750",\ + "380002.062500, 380002.125000, 380002.250000, 380002.562500, 380003.437500",\ + "380002.125000, 380002.187500, 380002.312500, 380002.625000, 380003.500000",\ + "380002.468750, 380002.531250, 380002.656250, 380002.968750, 380003.843750"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073650, 0.189354, 0.392450, 0.950561, 2.441537",\ + "0.073650, 0.189354, 0.392450, 0.950561, 2.441537",\ + "0.073650, 0.189365, 0.392450, 0.950561, 2.441537",\ + "0.073650, 0.189385, 0.392560, 0.950561, 2.441537",\ + "0.073650, 0.189425, 0.393252, 0.950561, 2.441537"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380000.437500, 380000.437500, 380000.468750, 380000.531250, 380000.718750",\ + "380000.531250, 380000.531250, 380000.562500, 380000.625000, 380000.812500",\ + "380000.593750, 380000.593750, 380000.625000, 380000.687500, 380000.875000",\ + "380000.656250, 380000.656250, 380000.687500, 380000.750000, 380000.937500",\ + "380000.968750, 380000.968750, 380001.000000, 380001.062500, 380001.250000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180697, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180697, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180697, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180697, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180697, 0.429275, 1.092497"); + } + + } /* end of arc clk_ast_tlul_i_ast2padmux_o[0]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.118063, 0.173160, 0.267375, 0.527316, 1.216798",\ + "0.205470, 0.260567, 0.354781, 0.614720, 1.304204",\ + "0.286205, 0.341346, 0.435579, 0.695608, 1.384949",\ + "0.343571, 0.398793, 0.493060, 0.753254, 1.442331",\ + "0.643636, 0.699058, 0.793671, 1.054205, 1.742813"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.055140, 0.149920, 0.315966, 0.770671, 1.992169",\ + "0.055140, 0.149920, 0.315966, 0.770671, 1.992169",\ + "0.055064, 0.149920, 0.315966, 0.770616, 1.992169",\ + "0.054924, 0.149920, 0.315966, 0.770514, 1.992169",\ + "0.054820, 0.149920, 0.315966, 0.770514, 1.988361"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.068977, 0.083624, 0.108789, 0.177707, 0.362145",\ + "0.157440, 0.172093, 0.197279, 0.266195, 0.450612",\ + "0.246166, 0.261189, 0.286407, 0.355291, 0.539679",\ + "0.308361, 0.324424, 0.349591, 0.418444, 0.602842",\ + "0.630702, 0.654723, 0.683267, 0.752219, 0.936438"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.015416, 0.041075, 0.085652, 0.207740, 0.535967",\ + "0.015763, 0.041089, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967"); + } + + } /* end of arc clk_ast_tlul_i_ast2padmux_o[0]_redg_min*/ + + timing () { + related_pin : "fla_obs_i[0]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.111862, 0.178517, 0.294685, 0.611498, 1.461412",\ + "0.196887, 0.263820, 0.381200, 0.697836, 1.546758",\ + "0.280874, 0.348002, 0.465333, 0.783744, 1.631498",\ + "0.419192, 0.490016, 0.607541, 0.927454, 1.774732",\ + "0.629434, 0.713469, 0.835221, 1.155234, 2.004311"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067759, 0.184639, 0.382501, 0.937507, 2.417566",\ + "0.067759, 0.184639, 0.382501, 0.937507, 2.418347",\ + "0.069174, 0.184639, 0.382586, 0.937507, 2.418347",\ + "0.077831, 0.187460, 0.383300, 0.940319, 2.418347",\ + "0.099054, 0.205738, 0.390315, 0.940320, 2.425200"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.103322, 0.134506, 0.187130, 0.329612, 0.708263",\ + "0.188196, 0.219801, 0.272413, 0.414932, 0.793505",\ + "0.281500, 0.317246, 0.369943, 0.512302, 0.890520",\ + "0.433568, 0.478875, 0.537406, 0.680993, 1.058708",\ + "0.668936, 0.733428, 0.809479, 0.962224, 1.340585"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040521, 0.090274, 0.180244, 0.428614, 1.092440",\ + "0.042863, 0.090977, 0.180401, 0.428614, 1.092696",\ + "0.054661, 0.097371, 0.180899, 0.428690, 1.092793",\ + "0.077190, 0.120374, 0.194930, 0.430280, 1.092793",\ + "0.118581, 0.174509, 0.240947, 0.445113, 1.092793"); + } + + } /* end of arc fla_obs_i[0]_ast2padmux_o[0]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "fla_obs_i[0]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.110629, 0.177262, 0.293339, 0.610165, 1.460154",\ + "0.194795, 0.261696, 0.378936, 0.695592, 1.544629",\ + "0.275980, 0.343081, 0.460479, 0.778514, 1.626463",\ + "0.408884, 0.478137, 0.595421, 0.915532, 1.762573",\ + "0.610985, 0.691263, 0.810230, 1.128954, 1.977655"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067834, 0.183634, 0.382402, 0.934951, 2.414331",\ + "0.067834, 0.183634, 0.382402, 0.934951, 2.414331",\ + "0.068631, 0.183634, 0.382540, 0.936478, 2.414331",\ + "0.075251, 0.185541, 0.383090, 0.939701, 2.414331",\ + "0.093347, 0.198994, 0.384563, 0.939701, 2.425563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.077370, 0.108647, 0.161299, 0.303710, 0.682406",\ + "0.166391, 0.197521, 0.250129, 0.392651, 0.771277",\ + "0.253394, 0.288299, 0.340979, 0.483371, 0.861661",\ + "0.395347, 0.439383, 0.496795, 0.640121, 1.017884",\ + "0.615736, 0.679130, 0.754042, 0.905113, 1.283136"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039363, 0.090228, 0.180124, 0.428312, 1.092155",\ + "0.041196, 0.090228, 0.180315, 0.428312, 1.092511",\ + "0.052267, 0.096073, 0.180798, 0.428601, 1.092511",\ + "0.074482, 0.116813, 0.192279, 0.430033, 1.092511",\ + "0.116096, 0.171326, 0.236992, 0.441817, 1.092511"); + } + + } /* end of arc fla_obs_i[0]_ast2padmux_o[0]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[10]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.454321, 0.521261, 0.637729, 0.957401, 1.812562",\ + "0.476584, 0.543525, 0.659993, 0.979665, 1.834826",\ + "0.532978, 0.599918, 0.716386, 1.036058, 1.891219",\ + "0.630840, 0.697781, 0.814249, 1.133921, 1.989082",\ + "1.144998, 1.211940, 1.328409, 1.648081, 2.503240"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\ + "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\ + "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\ + "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\ + "0.073066, 0.188998, 0.391939, 0.949310, 2.441375"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.506462, 0.537893, 0.590602, 0.732954, 1.111551",\ + "0.527996, 0.559427, 0.612136, 0.754488, 1.133085",\ + "0.595181, 0.626613, 0.679322, 0.821674, 1.200271",\ + "0.705480, 0.736911, 0.789620, 0.931973, 1.310569",\ + "1.265269, 1.296700, 1.349409, 1.491761, 1.870358"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\ + "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\ + "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\ + "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\ + "0.039144, 0.090610, 0.180696, 0.429275, 1.090836"); + } + + } /* end of arc obs_ctrl_o[10]_ast2padmux_o[0]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[10]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.421371, 0.488300, 0.604758, 0.924429, 1.779604",\ + "0.442149, 0.509077, 0.625536, 0.945207, 1.800382",\ + "0.499740, 0.566669, 0.683127, 1.002798, 1.857973",\ + "0.597685, 0.664614, 0.781072, 1.100743, 1.955918",\ + "1.086534, 1.153463, 1.269921, 1.589592, 2.444767"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\ + "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\ + "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\ + "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\ + "0.073056, 0.188976, 0.391905, 0.949239, 2.441363"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.412434, 0.443851, 0.496510, 0.638912, 1.017545",\ + "0.429840, 0.461257, 0.513916, 0.656317, 1.034951",\ + "0.502410, 0.533827, 0.586486, 0.728887, 1.107521",\ + "0.615047, 0.646463, 0.699123, 0.841524, 1.220157",\ + "1.142076, 1.173492, 1.226152, 1.368553, 1.747186"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\ + "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\ + "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\ + "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\ + "0.039040, 0.090706, 0.180446, 0.429219, 1.091504"); + } + + } /* end of arc obs_ctrl_o[10]_ast2padmux_o[0]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[10]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.453258, 0.484690, 0.537398, 0.679751, 1.058348",\ + "0.478327, 0.509759, 0.562468, 0.704820, 1.083417",\ + "0.547548, 0.578980, 0.631688, 0.774041, 1.152637",\ + "0.671779, 0.703211, 0.755919, 0.898272, 1.276869",\ + "1.305416, 1.336847, 1.389556, 1.531909, 1.910505"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\ + "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\ + "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\ + "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\ + "0.039144, 0.090610, 0.180696, 0.429275, 1.090836"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.686438, 0.753379, 0.869847, 1.189519, 2.044680",\ + "0.706913, 0.773853, 0.890321, 1.209993, 2.065154",\ + "0.765773, 0.832713, 0.949182, 1.268853, 2.124014",\ + "0.875012, 0.941953, 1.058421, 1.378093, 2.233254",\ + "1.652212, 1.719154, 1.835623, 2.155295, 3.010454"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\ + "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\ + "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\ + "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\ + "0.073066, 0.188998, 0.391939, 0.949310, 2.441375"); + } + + } /* end of arc obs_ctrl_o[10]_ast2padmux_o[0]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[10]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.282064, 0.313481, 0.366140, 0.508541, 0.887175",\ + "0.305674, 0.337091, 0.389750, 0.532151, 0.910785",\ + "0.377014, 0.408430, 0.461090, 0.603491, 0.982124",\ + "0.496822, 0.528239, 0.580898, 0.723300, 1.101933",\ + "1.041943, 1.073360, 1.126019, 1.268421, 1.647054"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\ + "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\ + "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\ + "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\ + "0.039040, 0.090706, 0.180446, 0.429219, 1.091504"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.590884, 0.657812, 0.774271, 1.093942, 1.949117",\ + "0.607576, 0.674504, 0.790963, 1.110634, 1.965809",\ + "0.669970, 0.736899, 0.853357, 1.173028, 2.028203",\ + "0.779360, 0.846288, 0.962747, 1.282418, 2.137593",\ + "1.516501, 1.583430, 1.699888, 2.019559, 2.874734"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\ + "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\ + "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\ + "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\ + "0.073056, 0.188976, 0.391905, 0.949239, 2.441363"); + } + + } /* end of arc obs_ctrl_o[10]_ast2padmux_o[0]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[11]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.034927, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.197401, 0.228828, 0.281523, 0.423889, 0.802496",\ + "0.210783, 0.242210, 0.294905, 0.437272, 0.815878",\ + "0.293723, 0.325151, 0.377848, 0.520213, 0.898818",\ + "0.418374, 0.449806, 0.502515, 0.644867, 1.023463",\ + "1.005445, 1.038016, 1.090870, 1.233261, 1.611881"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.034927, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039115, 0.090636, 0.180627, 0.429260, 1.091020",\ + "0.039115, 0.090636, 0.180627, 0.429260, 1.091020",\ + "0.039119, 0.090636, 0.180636, 0.429262, 1.091020",\ + "0.039145, 0.090636, 0.180699, 0.429276, 1.091020",\ + "0.042423, 0.091616, 0.180853, 0.429341, 1.091020"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037147, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.483196, 0.550400, 0.667026, 0.986767, 1.841721",\ + "0.495454, 0.562658, 0.679284, 0.999025, 1.853979",\ + "0.559644, 0.626847, 0.743473, 1.063213, 1.918167",\ + "0.662607, 0.729816, 0.846440, 1.166186, 2.021145",\ + "1.344671, 1.412041, 1.528612, 1.848528, 2.703634"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037147, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073644, 0.189305, 0.392450, 0.950559, 2.441537",\ + "0.073644, 0.189305, 0.392450, 0.950559, 2.441537",\ + "0.073644, 0.189305, 0.392450, 0.950559, 2.441537",\ + "0.073683, 0.189305, 0.392450, 0.950570, 2.441537",\ + "0.075005, 0.189305, 0.392450, 0.950931, 2.441537"); + } + + } /* end of arc obs_ctrl_o[11]_ast2padmux_o[0]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[11]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.030664, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.178015, 0.209429, 0.262079, 0.404490, 0.783130",\ + "0.189390, 0.220804, 0.273454, 0.415865, 0.794505",\ + "0.274579, 0.305993, 0.358646, 0.501054, 0.879692",\ + "0.400471, 0.431892, 0.484565, 0.626953, 1.005576",\ + "0.985792, 1.018105, 1.070937, 1.213308, 1.591914"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.030664, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039020, 0.090679, 0.180398, 0.429208, 1.090559",\ + "0.039020, 0.090679, 0.180398, 0.429208, 1.090559",\ + "0.039027, 0.090679, 0.180413, 0.429212, 1.090559",\ + "0.039069, 0.090679, 0.180517, 0.429235, 1.090559",\ + "0.041694, 0.091361, 0.180877, 0.429339, 1.090559"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.028580, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.476048, 0.543228, 0.659862, 0.979577, 1.834510",\ + "0.484692, 0.551872, 0.668506, 0.988221, 1.843154",\ + "0.552511, 0.619690, 0.736325, 1.056039, 1.910971",\ + "0.655347, 0.722531, 0.839164, 1.158884, 2.013820",\ + "1.333397, 1.400722, 1.517308, 1.837177, 2.692242"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.028580, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073446, 0.189167, 0.392403, 0.950504, 2.441474",\ + "0.073446, 0.189167, 0.392403, 0.950504, 2.441474",\ + "0.073446, 0.189167, 0.392403, 0.950504, 2.441474",\ + "0.073481, 0.189167, 0.392403, 0.950515, 2.441474",\ + "0.074640, 0.189167, 0.392403, 0.950831, 2.441474"); + } + + } /* end of arc obs_ctrl_o[11]_ast2padmux_o[0]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.518600, 0.585804, 0.702430, 1.022170, 1.877124",\ + "0.534366, 0.601569, 0.718195, 1.037936, 1.892890",\ + "0.608476, 0.675680, 0.792306, 1.112046, 1.967001",\ + "0.699697, 0.766901, 0.883527, 1.203267, 2.058222",\ + "1.126490, 1.193697, 1.310322, 1.630066, 2.485023"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073641, 0.189305, 0.392450, 0.950559, 2.441537",\ + "0.073641, 0.189305, 0.392450, 0.950559, 2.441537",\ + "0.073641, 0.189305, 0.392450, 0.950559, 2.441537",\ + "0.073643, 0.189305, 0.392450, 0.950559, 2.441537",\ + "0.073671, 0.189301, 0.392449, 0.950567, 2.441536"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.275118, 0.306284, 0.358903, 0.501398, 0.880041",\ + "0.290749, 0.321915, 0.374533, 0.517029, 0.895671",\ + "0.363703, 0.394869, 0.447488, 0.589983, 0.968626",\ + "0.474794, 0.505959, 0.558577, 0.701073, 1.079716",\ + "1.013269, 1.044421, 1.097036, 1.239541, 1.618177"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090637, 0.180627, 0.429260, 1.092497",\ + "0.040752, 0.090637, 0.180627, 0.429260, 1.092497",\ + "0.040752, 0.090637, 0.180627, 0.429260, 1.092497",\ + "0.040759, 0.090635, 0.180631, 0.429261, 1.092499",\ + "0.040922, 0.090603, 0.180713, 0.429279, 1.092539"); + } + + } /* end of arc obs_ctrl_o[4]_ast2padmux_o[0]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.337608, 0.404302, 0.520641, 0.837429, 1.687203",\ + "0.349939, 0.416633, 0.532972, 0.849760, 1.699534",\ + "0.408752, 0.475446, 0.591785, 0.908573, 1.758347",\ + "0.496083, 0.562777, 0.679117, 0.995905, 1.845678",\ + "0.949078, 1.015776, 1.132136, 1.448920, 2.298678"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184560, 0.382485, 0.937098, 2.417677",\ + "0.067604, 0.184551, 0.382483, 0.937052, 2.417689"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.228794, 0.260208, 0.312858, 0.455269, 0.833909",\ + "0.240665, 0.272079, 0.324729, 0.467140, 0.845780",\ + "0.323160, 0.354574, 0.407224, 0.549635, 0.928275",\ + "0.428120, 0.459534, 0.512186, 0.654595, 1.033234",\ + "0.930331, 0.961753, 1.014431, 1.156814, 1.535434"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039020, 0.090327, 0.180161, 0.428971, 1.091633",\ + "0.039020, 0.090327, 0.180161, 0.428971, 1.091633",\ + "0.039020, 0.090327, 0.180161, 0.428971, 1.091633",\ + "0.039024, 0.090327, 0.180161, 0.428971, 1.091612",\ + "0.039078, 0.090324, 0.180166, 0.428948, 1.091257"); + } + + } /* end of arc obs_ctrl_o[4]_ast2padmux_o[0]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.287803, 0.318969, 0.371587, 0.514083, 0.892726",\ + "0.303569, 0.334734, 0.387353, 0.529848, 0.908491",\ + "0.378810, 0.409975, 0.462594, 0.605089, 0.983732",\ + "0.473884, 0.505049, 0.557668, 0.700163, 1.078806",\ + "0.918190, 0.949342, 1.001956, 1.144462, 1.523098"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090637, 0.180627, 0.429260, 1.092497",\ + "0.040752, 0.090637, 0.180627, 0.429260, 1.092497",\ + "0.040752, 0.090637, 0.180627, 0.429260, 1.092497",\ + "0.040759, 0.090635, 0.180631, 0.429261, 1.092499",\ + "0.040922, 0.090603, 0.180713, 0.429279, 1.092539"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.376755, 0.443500, 0.560063, 0.876818, 1.726409",\ + "0.392417, 0.459162, 0.575725, 0.892480, 1.742071",\ + "0.467424, 0.534169, 0.650732, 0.967487, 1.817078",\ + "0.562603, 0.629351, 0.745928, 1.062681, 1.912261",\ + "1.006927, 1.073706, 1.190415, 1.507149, 2.356620"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073641, 0.189305, 0.392450, 0.950559, 2.441537",\ + "0.073641, 0.189305, 0.392450, 0.950559, 2.441537",\ + "0.073641, 0.189305, 0.392450, 0.950559, 2.441537",\ + "0.073643, 0.189305, 0.392450, 0.950559, 2.441537",\ + "0.073671, 0.189301, 0.392449, 0.950567, 2.441536"); + } + + } /* end of arc obs_ctrl_o[4]_ast2padmux_o[0]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.264318, 0.295567, 0.348210, 0.490643, 0.869326",\ + "0.278489, 0.309737, 0.362381, 0.504814, 0.883496",\ + "0.355325, 0.386573, 0.439217, 0.581649, 0.960332",\ + "0.450369, 0.481617, 0.534260, 0.676693, 1.055376",\ + "0.893831, 0.925076, 0.977718, 1.120154, 1.498834"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039020, 0.090327, 0.180161, 0.428971, 1.091633",\ + "0.039020, 0.090327, 0.180161, 0.428971, 1.091633",\ + "0.039020, 0.090327, 0.180161, 0.428971, 1.091633",\ + "0.039024, 0.090327, 0.180161, 0.428971, 1.091612",\ + "0.039078, 0.090324, 0.180166, 0.428948, 1.091257"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.373701, 0.440395, 0.556734, 0.873522, 1.723296",\ + "0.385572, 0.452266, 0.568605, 0.885393, 1.735167",\ + "0.464371, 0.531065, 0.647404, 0.964192, 1.813966",\ + "0.559385, 0.626079, 0.742420, 1.059207, 1.908981",\ + "1.002245, 1.068944, 1.185303, 1.502088, 2.351846"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184560, 0.382485, 0.937098, 2.417677",\ + "0.067604, 0.184551, 0.382483, 0.937052, 2.417689"); + } + + } /* end of arc obs_ctrl_o[4]_ast2padmux_o[0]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.337998, 0.404744, 0.521308, 0.838063, 1.687653",\ + "0.353177, 0.419923, 0.536487, 0.853242, 1.702832",\ + "0.412195, 0.478941, 0.595505, 0.912260, 1.761850",\ + "0.508449, 0.575199, 0.691783, 1.008535, 1.858109",\ + "0.997007, 1.063817, 1.180658, 1.497372, 2.346736"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073639, 0.189305, 0.392450, 0.950558, 2.441538",\ + "0.073639, 0.189305, 0.392450, 0.950558, 2.441538",\ + "0.073641, 0.189305, 0.392450, 0.950559, 2.441538",\ + "0.073704, 0.189296, 0.392447, 0.950576, 2.441534",\ + "0.075364, 0.189067, 0.392369, 0.951029, 2.441428"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.272032, 0.303198, 0.355817, 0.498312, 0.876955",\ + "0.289891, 0.321056, 0.373675, 0.516170, 0.894813",\ + "0.360955, 0.392121, 0.444739, 0.587235, 0.965878",\ + "0.471378, 0.502542, 0.555160, 0.697656, 1.076298",\ + "1.004117, 1.035227, 1.087829, 1.230366, 1.608983"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090636, 0.180627, 0.429260, 1.092497",\ + "0.040752, 0.090636, 0.180627, 0.429260, 1.092497",\ + "0.040752, 0.090636, 0.180636, 0.429262, 1.092497",\ + "0.040771, 0.090636, 0.180700, 0.429276, 1.092502",\ + "0.042582, 0.091671, 0.180848, 0.429341, 1.092666"); + } + + } /* end of arc obs_ctrl_o[5]_ast2padmux_o[0]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.329221, 0.395915, 0.512254, 0.829041, 1.678816",\ + "0.344592, 0.411286, 0.527624, 0.844412, 1.694187",\ + "0.406780, 0.473474, 0.589813, 0.906601, 1.756375",\ + "0.502234, 0.568932, 0.685288, 1.002073, 1.851833",\ + "0.957622, 1.024367, 1.140929, 1.457685, 2.307276"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067607, 0.184553, 0.382483, 0.937060, 2.417687",\ + "0.067439, 0.184458, 0.382464, 0.936568, 2.417820"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.231492, 0.262740, 0.315383, 0.457816, 0.836499",\ + "0.245351, 0.276600, 0.329243, 0.471676, 0.850359",\ + "0.320124, 0.351372, 0.404016, 0.546449, 0.925131",\ + "0.430166, 0.461410, 0.514053, 0.656489, 1.035169",\ + "0.955028, 0.986237, 1.038869, 1.181331, 1.559995"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039020, 0.090327, 0.180161, 0.428971, 1.091633",\ + "0.039020, 0.090327, 0.180161, 0.428971, 1.091633",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091594",\ + "0.039070, 0.090324, 0.180167, 0.428947, 1.091311",\ + "0.040211, 0.090294, 0.180212, 0.428752, 1.090589"); + } + + } /* end of arc obs_ctrl_o[5]_ast2padmux_o[0]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[5]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.194141, 0.225569, 0.278263, 0.420630, 0.799236",\ + "0.213398, 0.244825, 0.297520, 0.439886, 0.818493",\ + "0.291110, 0.322538, 0.375235, 0.517599, 0.896205",\ + "0.414666, 0.446098, 0.498807, 0.641159, 1.019755",\ + "0.992685, 1.025312, 1.078170, 1.220567, 1.599190"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090636, 0.180627, 0.429260, 1.092497",\ + "0.040752, 0.090636, 0.180627, 0.429260, 1.092497",\ + "0.040752, 0.090636, 0.180636, 0.429262, 1.092497",\ + "0.040771, 0.090636, 0.180700, 0.429276, 1.092502",\ + "0.042582, 0.091671, 0.180848, 0.429341, 1.092666"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.473555, 0.540758, 0.657385, 0.977125, 1.832079",\ + "0.486694, 0.553897, 0.670524, 0.990264, 1.845218",\ + "0.549031, 0.616234, 0.732861, 1.052601, 1.907555",\ + "0.658256, 0.725467, 0.842091, 1.161839, 2.016800",\ + "1.359176, 1.426589, 1.543146, 1.863108, 2.718254"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073639, 0.189305, 0.392450, 0.950558, 2.441538",\ + "0.073639, 0.189305, 0.392450, 0.950558, 2.441538",\ + "0.073641, 0.189305, 0.392450, 0.950559, 2.441538",\ + "0.073704, 0.189296, 0.392447, 0.950576, 2.441534",\ + "0.075364, 0.189067, 0.392369, 0.951029, 2.441428"); + } + + } /* end of arc obs_ctrl_o[5]_ast2padmux_o[0]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[5]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.174738, 0.206152, 0.258801, 0.401212, 0.779853",\ + "0.192387, 0.223801, 0.276451, 0.418861, 0.797502",\ + "0.271960, 0.303374, 0.356027, 0.498435, 0.877073",\ + "0.396781, 0.428202, 0.480875, 0.623262, 1.001885",\ + "0.972879, 1.005251, 1.058088, 1.200464, 1.579073"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039020, 0.090327, 0.180161, 0.428971, 1.091633",\ + "0.039020, 0.090327, 0.180161, 0.428971, 1.091633",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091594",\ + "0.039070, 0.090324, 0.180167, 0.428947, 1.091311",\ + "0.040211, 0.090294, 0.180212, 0.428752, 1.090589"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.466421, 0.533601, 0.650235, 0.969950, 1.824882",\ + "0.476202, 0.543381, 0.660016, 0.979730, 1.834662",\ + "0.541892, 0.609071, 0.725705, 1.045420, 1.900352",\ + "0.650936, 0.718122, 0.834754, 1.154476, 2.009415",\ + "1.346760, 1.414122, 1.530696, 1.850604, 2.705703"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067607, 0.184553, 0.382483, 0.937060, 2.417687",\ + "0.067439, 0.184458, 0.382464, 0.936568, 2.417820"); + } + + } /* end of arc obs_ctrl_o[5]_ast2padmux_o[0]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[6]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.313610, 0.380815, 0.497441, 0.817182, 1.672137",\ + "0.329358, 0.396562, 0.513188, 0.832930, 1.687885",\ + "0.393235, 0.460439, 0.577065, 0.896806, 1.751761",\ + "0.471556, 0.538760, 0.655386, 0.975126, 1.830081",\ + "0.862244, 0.929448, 1.046074, 1.365815, 2.220770"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073650, 0.189304, 0.392450, 0.950561, 2.441537",\ + "0.073650, 0.189304, 0.392450, 0.950561, 2.441537",\ + "0.073650, 0.189304, 0.392450, 0.950561, 2.441537",\ + "0.073650, 0.189305, 0.392450, 0.950561, 2.441537",\ + "0.073650, 0.189305, 0.392450, 0.950561, 2.441537"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.191794, 0.223225, 0.275933, 0.418286, 0.796883",\ + "0.207675, 0.239106, 0.291815, 0.434167, 0.812764",\ + "0.277023, 0.308454, 0.361162, 0.503515, 0.882112",\ + "0.365690, 0.397121, 0.449830, 0.592182, 0.970779",\ + "0.790485, 0.821927, 0.874671, 1.016989, 1.395559"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090610, 0.180695, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180695, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180695, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180695, 0.429275, 1.092497",\ + "0.040785, 0.090539, 0.180878, 0.429316, 1.092505"); + } + + } /* end of arc obs_ctrl_o[6]_ast2padmux_o[0]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[6]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.289937, 0.356887, 0.473363, 0.793036, 1.648185",\ + "0.304047, 0.370997, 0.487474, 0.807146, 1.662295",\ + "0.369617, 0.436567, 0.553044, 0.872716, 1.727865",\ + "0.448151, 0.515103, 0.631581, 0.951254, 1.806401",\ + "0.842717, 0.909715, 1.026232, 1.345907, 2.200999"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067586, 0.184541, 0.382481, 0.936998, 2.417704"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.167066, 0.198479, 0.251128, 0.393540, 0.772181",\ + "0.179068, 0.210482, 0.263130, 0.405543, 0.784184",\ + "0.252467, 0.283881, 0.336530, 0.478942, 0.857582",\ + "0.341502, 0.372916, 0.425566, 0.567976, 0.946617",\ + "0.759790, 0.791205, 0.843857, 0.986265, 1.364904"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039018, 0.090327, 0.180161, 0.428971, 1.091651",\ + "0.039018, 0.090327, 0.180161, 0.428971, 1.091651",\ + "0.039019, 0.090327, 0.180161, 0.428971, 1.091642",\ + "0.039020, 0.090327, 0.180161, 0.428971, 1.091633",\ + "0.039025, 0.090322, 0.180169, 0.428938, 1.091600"); + } + + } /* end of arc obs_ctrl_o[6]_ast2padmux_o[0]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[6]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.314064, 0.345229, 0.397848, 0.540343, 0.918986",\ + "0.329859, 0.361025, 0.413644, 0.556139, 0.934782",\ + "0.407724, 0.438890, 0.491508, 0.634004, 1.012646",\ + "0.508778, 0.539944, 0.592562, 0.735058, 1.113701",\ + "0.984655, 1.015818, 1.068436, 1.210933, 1.589574"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090610, 0.180695, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180695, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180695, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180695, 0.429275, 1.092497",\ + "0.040785, 0.090539, 0.180878, 0.429316, 1.092505"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.614118, 0.681322, 0.797948, 1.117689, 1.972644",\ + "0.626922, 0.694126, 0.810752, 1.130493, 1.985448",\ + "0.694897, 0.762101, 0.878727, 1.198468, 2.053423",\ + "0.806557, 0.873761, 0.990387, 1.310127, 2.165082",\ + "1.291436, 1.358640, 1.475266, 1.795007, 2.649961"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073650, 0.189304, 0.392450, 0.950561, 2.441537",\ + "0.073650, 0.189304, 0.392450, 0.950561, 2.441537",\ + "0.073650, 0.189304, 0.392450, 0.950561, 2.441537",\ + "0.073650, 0.189305, 0.392450, 0.950561, 2.441537",\ + "0.073650, 0.189305, 0.392450, 0.950561, 2.441537"); + } + + } /* end of arc obs_ctrl_o[6]_ast2padmux_o[0]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[6]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.270718, 0.301966, 0.354610, 0.497042, 0.875725",\ + "0.284868, 0.316117, 0.368760, 0.511193, 0.889875",\ + "0.364362, 0.395610, 0.448254, 0.590687, 0.969369",\ + "0.465503, 0.496751, 0.549395, 0.691827, 1.070510",\ + "0.941451, 0.972693, 1.025335, 1.167772, 1.546452"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039018, 0.090327, 0.180161, 0.428971, 1.091651",\ + "0.039018, 0.090327, 0.180161, 0.428971, 1.091651",\ + "0.039019, 0.090327, 0.180161, 0.428971, 1.091642",\ + "0.039020, 0.090327, 0.180161, 0.428971, 1.091633",\ + "0.039025, 0.090322, 0.180169, 0.428938, 1.091600"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.437011, 0.503705, 0.620045, 0.936832, 1.786606",\ + "0.446608, 0.513302, 0.629642, 0.946429, 1.796203",\ + "0.517780, 0.584475, 0.700814, 1.017602, 1.867376",\ + "0.629396, 0.696091, 0.812430, 1.129218, 1.978992",\ + "1.131911, 1.198614, 1.314996, 1.631778, 2.481517"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067586, 0.184541, 0.382481, 0.936998, 2.417704"); + } + + } /* end of arc obs_ctrl_o[6]_ast2padmux_o[0]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[7]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.060518, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.315427, 0.346593, 0.399212, 0.541707, 0.920350",\ + "0.342146, 0.373312, 0.425930, 0.568426, 0.947068",\ + "0.410184, 0.441350, 0.493968, 0.636464, 1.015106",\ + "0.512927, 0.544093, 0.596711, 0.739207, 1.117850",\ + "1.020553, 1.055041, 1.108054, 1.250599, 1.629324"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.060518, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090610, 0.180695, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180695, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180832, 0.429306, 1.092497",\ + "0.047830, 0.093504, 0.180832, 0.429352, 1.092504"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.051005, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.615123, 0.682328, 0.798954, 1.118695, 1.973650",\ + "0.635870, 0.703074, 0.819700, 1.139442, 1.994397",\ + "0.701192, 0.768396, 0.885022, 1.204764, 2.059719",\ + "0.815370, 0.882574, 0.999200, 1.318941, 2.173895",\ + "1.395166, 1.462382, 1.579004, 1.898758, 2.753724"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.051005, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073650, 0.189304, 0.392450, 0.950561, 2.441537",\ + "0.073650, 0.189304, 0.392450, 0.950561, 2.441537",\ + "0.073650, 0.189304, 0.392450, 0.950561, 2.441537",\ + "0.073650, 0.189305, 0.392450, 0.950561, 2.441537",\ + "0.073748, 0.189305, 0.392450, 0.950588, 2.441537"); + } + + } /* end of arc obs_ctrl_o[7]_ast2padmux_o[0]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[7]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.049671, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.132284, 0.163698, 0.216345, 0.358758, 0.737400",\ + "0.152768, 0.184181, 0.236829, 0.379242, 0.757883",\ + "0.226947, 0.258361, 0.311010, 0.453421, 0.832062",\ + "0.328095, 0.359509, 0.412158, 0.554569, 0.933209",\ + "0.769672, 0.801087, 0.853739, 0.996148, 1.374786"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.049671, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039016, 0.090327, 0.180161, 0.428971, 1.091660",\ + "0.039016, 0.090327, 0.180161, 0.428971, 1.091660",\ + "0.039020, 0.090327, 0.180161, 0.428971, 1.091633",\ + "0.039020, 0.090327, 0.180161, 0.428971, 1.091633",\ + "0.039025, 0.090323, 0.180168, 0.428941, 1.091602"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040467, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.268552, 0.335503, 0.451979, 0.771651, 1.626801",\ + "0.284564, 0.351514, 0.467990, 0.787663, 1.642812",\ + "0.357242, 0.424196, 0.540676, 0.860348, 1.715493",\ + "0.477594, 0.544576, 0.661079, 0.980754, 1.835865",\ + "1.125477, 1.192657, 1.309291, 1.629006, 2.483939"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040467, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067601, 0.184550, 0.382483, 0.937044, 2.417691"); + } + + } /* end of arc obs_ctrl_o[7]_ast2padmux_o[0]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[8]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.711181, 0.778121, 0.894590, 1.214261, 2.069422",\ + "0.729530, 0.796471, 0.912939, 1.232611, 2.087772",\ + "0.800074, 0.867014, 0.983483, 1.303154, 2.158315",\ + "0.892545, 0.959485, 1.075954, 1.395625, 2.250786",\ + "1.377232, 1.444175, 1.560645, 1.880316, 2.735475"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\ + "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\ + "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\ + "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\ + "0.073067, 0.188999, 0.391940, 0.949314, 2.441375"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.503942, 0.535373, 0.588082, 0.730435, 1.109031",\ + "0.521369, 0.552801, 0.605509, 0.747862, 1.126459",\ + "0.598766, 0.630198, 0.682907, 0.825259, 1.203856",\ + "0.707080, 0.738512, 0.791220, 0.933573, 1.312169",\ + "1.259288, 1.290720, 1.343428, 1.485781, 1.864378"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\ + "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\ + "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\ + "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\ + "0.039144, 0.090610, 0.180696, 0.429275, 1.090836"); + } + + } /* end of arc obs_ctrl_o[8]_ast2padmux_o[0]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[8]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.645044, 0.711973, 0.828431, 1.148102, 2.003277",\ + "0.661659, 0.728588, 0.845047, 1.164717, 2.019893",\ + "0.736081, 0.803009, 0.919468, 1.239139, 2.094314",\ + "0.830502, 0.897430, 1.013889, 1.333560, 2.188735",\ + "1.278260, 1.345188, 1.461647, 1.781317, 2.636493"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\ + "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\ + "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\ + "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\ + "0.073056, 0.188976, 0.391905, 0.949239, 2.441363"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.359441, 0.390858, 0.443517, 0.585919, 0.964552",\ + "0.372788, 0.404204, 0.456864, 0.599265, 0.977898",\ + "0.454765, 0.486182, 0.538841, 0.681242, 1.059876",\ + "0.563985, 0.595401, 0.648061, 0.790462, 1.169096",\ + "1.087607, 1.119023, 1.171683, 1.314084, 1.692717"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\ + "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\ + "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\ + "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\ + "0.039040, 0.090706, 0.180446, 0.429219, 1.091504"); + } + + } /* end of arc obs_ctrl_o[8]_ast2padmux_o[0]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[8]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.540276, 0.571708, 0.624416, 0.766769, 1.145365",\ + "0.558625, 0.590057, 0.642766, 0.785118, 1.163715",\ + "0.632481, 0.663913, 0.716621, 0.858974, 1.237571",\ + "0.730741, 0.762172, 0.814881, 0.957234, 1.335830",\ + "1.254148, 1.285579, 1.338288, 1.480641, 1.859237"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\ + "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\ + "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\ + "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\ + "0.039144, 0.090610, 0.180696, 0.429275, 1.090836"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.661922, 0.728863, 0.845331, 1.165002, 2.020164",\ + "0.674544, 0.741485, 0.857953, 1.177625, 2.032786",\ + "0.729459, 0.796399, 0.912867, 1.232539, 2.087700",\ + "0.831878, 0.898819, 1.015287, 1.334959, 2.190120",\ + "1.558837, 1.625780, 1.742250, 2.061921, 2.917080"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\ + "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\ + "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\ + "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\ + "0.073067, 0.188999, 0.391940, 0.949314, 2.441375"); + } + + } /* end of arc obs_ctrl_o[8]_ast2padmux_o[0]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[8]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.287469, 0.318885, 0.371545, 0.513946, 0.892579",\ + "0.304214, 0.335631, 0.388290, 0.530692, 0.909325",\ + "0.382471, 0.413888, 0.466547, 0.608949, 0.987582",\ + "0.506351, 0.537768, 0.590427, 0.732828, 1.111462",\ + "1.074942, 1.106358, 1.159018, 1.301419, 1.680052"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\ + "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\ + "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\ + "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\ + "0.039040, 0.090706, 0.180446, 0.429219, 1.091504"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.464880, 0.531808, 0.648267, 0.967938, 1.823113",\ + "0.478226, 0.545155, 0.661613, 0.981284, 1.836459",\ + "0.556365, 0.623294, 0.739753, 1.059423, 1.914599",\ + "0.657544, 0.724473, 0.840931, 1.160602, 2.015777",\ + "1.129399, 1.196328, 1.312786, 1.632457, 2.487632"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\ + "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\ + "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\ + "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\ + "0.073056, 0.188976, 0.391905, 0.949239, 2.441363"); + } + + } /* end of arc obs_ctrl_o[8]_ast2padmux_o[0]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[9]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.722991, 0.789932, 0.906400, 1.226072, 2.081233",\ + "0.741544, 0.808485, 0.924953, 1.244625, 2.099786",\ + "0.814242, 0.881183, 0.997651, 1.317322, 2.172483",\ + "0.909467, 0.976408, 1.092876, 1.412548, 2.267709",\ + "1.368597, 1.435539, 1.552008, 1.871680, 2.726840"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\ + "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\ + "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\ + "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\ + "0.073066, 0.188998, 0.391938, 0.949310, 2.441375"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.510317, 0.541749, 0.594457, 0.736810, 1.115407",\ + "0.527859, 0.559291, 0.612000, 0.754352, 1.132949",\ + "0.605188, 0.636620, 0.689329, 0.831681, 1.210278",\ + "0.714634, 0.746065, 0.798774, 0.941126, 1.319723",\ + "1.246573, 1.278005, 1.330713, 1.473066, 1.851663"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\ + "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\ + "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\ + "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\ + "0.039144, 0.090610, 0.180696, 0.429275, 1.090836"); + } + + } /* end of arc obs_ctrl_o[9]_ast2padmux_o[0]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[9]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.677174, 0.744103, 0.860561, 1.180232, 2.035407",\ + "0.693995, 0.760924, 0.877382, 1.197053, 2.052228",\ + "0.768427, 0.835355, 0.951814, 1.271485, 2.126660",\ + "0.863682, 0.930611, 1.047069, 1.366740, 2.221915",\ + "1.316333, 1.383262, 1.499720, 1.819391, 2.674566"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\ + "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\ + "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\ + "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\ + "0.073056, 0.188976, 0.391905, 0.949239, 2.441363"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.381372, 0.412788, 0.465448, 0.607849, 0.986482",\ + "0.394828, 0.426245, 0.478904, 0.621306, 0.999939",\ + "0.476249, 0.507665, 0.560325, 0.702726, 1.081359",\ + "0.586223, 0.617640, 0.670299, 0.812701, 1.191334",\ + "1.111662, 1.143078, 1.195738, 1.338139, 1.716772"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\ + "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\ + "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\ + "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\ + "0.039040, 0.090706, 0.180446, 0.429219, 1.091504"); + } + + } /* end of arc obs_ctrl_o[9]_ast2padmux_o[0]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[9]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.544142, 0.575574, 0.628282, 0.770635, 1.149231",\ + "0.562695, 0.594126, 0.646835, 0.789188, 1.167784",\ + "0.636753, 0.668185, 0.720893, 0.863246, 1.241843",\ + "0.735854, 0.767286, 0.819994, 0.962347, 1.340943",\ + "1.209522, 1.240954, 1.293662, 1.436015, 1.814612"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\ + "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\ + "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\ + "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\ + "0.039144, 0.090610, 0.180696, 0.429275, 1.090836"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.616983, 0.683923, 0.800391, 1.120063, 1.975224",\ + "0.629672, 0.696613, 0.813081, 1.132753, 1.987914",\ + "0.684443, 0.751384, 0.867852, 1.187524, 2.042685",\ + "0.787482, 0.854422, 0.970891, 1.290562, 2.145723",\ + "1.494185, 1.561127, 1.677597, 1.997268, 2.852428"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\ + "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\ + "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\ + "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\ + "0.073066, 0.188998, 0.391938, 0.949310, 2.441375"); + } + + } /* end of arc obs_ctrl_o[9]_ast2padmux_o[0]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[9]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.282372, 0.313788, 0.366448, 0.508849, 0.887482",\ + "0.299186, 0.330603, 0.383262, 0.525663, 0.904297",\ + "0.377525, 0.408942, 0.461601, 0.604002, 0.982636",\ + "0.500058, 0.531475, 0.584134, 0.726535, 1.105169",\ + "1.057248, 1.088664, 1.141323, 1.283725, 1.662358"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\ + "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\ + "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\ + "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\ + "0.039040, 0.090706, 0.180446, 0.429219, 1.091504"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.472156, 0.539085, 0.655543, 0.975214, 1.830389",\ + "0.485612, 0.552541, 0.669000, 0.988670, 1.843846",\ + "0.563901, 0.630829, 0.747288, 1.066959, 1.922134",\ + "0.663577, 0.730506, 0.846965, 1.166635, 2.021811",\ + "1.128422, 1.195350, 1.311809, 1.631480, 2.486655"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\ + "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\ + "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\ + "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\ + "0.073056, 0.188976, 0.391905, 0.949239, 2.441363"); + } + + } /* end of arc obs_ctrl_o[9]_ast2padmux_o[0]_inv_min*/ + + timing () { + related_pin : "otm_obs_i[0]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.113025, 0.179927, 0.296363, 0.616032, 1.471239",\ + "0.197499, 0.264597, 0.381195, 0.700878, 1.555851",\ + "0.280076, 0.347397, 0.463985, 0.783849, 1.638912",\ + "0.416433, 0.486812, 0.604025, 0.924187, 1.779474",\ + "0.624246, 0.705773, 0.827408, 1.148979, 2.004448"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073036, 0.188929, 0.391837, 0.949094, 2.441339",\ + "0.073183, 0.189268, 0.392332, 0.950151, 2.441515",\ + "0.074613, 0.189268, 0.392404, 0.950824, 2.441515",\ + "0.081868, 0.192856, 0.392640, 0.950928, 2.441515",\ + "0.102993, 0.209850, 0.398253, 0.950928, 2.441550"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.102851, 0.134278, 0.186974, 0.329339, 0.707946",\ + "0.188654, 0.220274, 0.273049, 0.415364, 0.793932",\ + "0.283232, 0.317549, 0.370548, 0.513080, 0.891796",\ + "0.439854, 0.481254, 0.538206, 0.682122, 1.061087",\ + "0.686111, 0.743348, 0.813206, 0.964006, 1.344314"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039116, 0.090635, 0.180630, 0.429260, 1.091011",\ + "0.039742, 0.090679, 0.180942, 0.429335, 1.091011",\ + "0.047350, 0.093337, 0.180942, 0.429351, 1.091547",\ + "0.062153, 0.106580, 0.187253, 0.429567, 1.092904",\ + "0.090069, 0.142497, 0.212830, 0.435355, 1.093832"); + } + + } /* end of arc otm_obs_i[0]_ast2padmux_o[0]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "otm_obs_i[0]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.111805, 0.178694, 0.295120, 0.614788, 1.470008",\ + "0.195286, 0.262361, 0.378939, 0.698621, 1.553622",\ + "0.274742, 0.342025, 0.458625, 0.778449, 1.633475",\ + "0.405125, 0.474114, 0.590991, 0.911111, 1.766377",\ + "0.603219, 0.681326, 0.800406, 1.120805, 1.976209"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073037, 0.188925, 0.391823, 0.948978, 2.441330",\ + "0.073166, 0.189215, 0.392273, 0.950004, 2.441389",\ + "0.074291, 0.189215, 0.392420, 0.950004, 2.441389",\ + "0.079135, 0.190954, 0.392488, 0.950004, 2.441389",\ + "0.097064, 0.203428, 0.393485, 0.950004, 2.441492"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.077369, 0.108778, 0.161412, 0.303838, 0.682490",\ + "0.166731, 0.198172, 0.250911, 0.393234, 0.771808",\ + "0.254923, 0.288717, 0.341672, 0.484162, 0.862849",\ + "0.400634, 0.441041, 0.497234, 0.640906, 1.019844",\ + "0.631133, 0.687293, 0.756057, 0.905549, 1.285508"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.038988, 0.090550, 0.180320, 0.429191, 1.090420",\ + "0.039208, 0.090550, 0.180739, 0.429310, 1.090420",\ + "0.045872, 0.092820, 0.180739, 0.429348, 1.091289",\ + "0.060397, 0.104342, 0.185891, 0.429526, 1.092845",\ + "0.088207, 0.140006, 0.210014, 0.433521, 1.093776"); + } + + } /* end of arc otm_obs_i[0]_ast2padmux_o[0]_una_min*/ + + timing () { + related_pin : "otp_obs_i[0]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.122660, 0.189370, 0.305783, 0.622560, 1.472274",\ + "0.209824, 0.276743, 0.394059, 0.710704, 1.559679",\ + "0.301920, 0.369023, 0.486415, 0.804486, 1.652417",\ + "0.455547, 0.524976, 0.642287, 0.962376, 1.809444",\ + "0.699992, 0.780922, 0.900058, 1.218756, 2.067549"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067561, 0.184527, 0.382478, 0.936925, 2.417724",\ + "0.067561, 0.184527, 0.382478, 0.936925, 2.418306",\ + "0.068683, 0.184527, 0.382544, 0.936925, 2.418306",\ + "0.075540, 0.185756, 0.383113, 0.940410, 2.418306",\ + "0.094401, 0.199857, 0.384817, 0.940410, 2.426093"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.114764, 0.145947, 0.198571, 0.341053, 0.719705",\ + "0.205629, 0.236785, 0.289401, 0.431904, 0.810542",\ + "0.310076, 0.342571, 0.395201, 0.537686, 0.916183",\ + "0.500896, 0.538360, 0.591093, 0.733386, 1.111456",\ + "0.820213, 0.870292, 0.933027, 1.077593, 1.455130"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040532, 0.090273, 0.180246, 0.428609, 1.092443",\ + "0.040870, 0.090273, 0.180281, 0.428609, 1.092443",\ + "0.045400, 0.092351, 0.180508, 0.428609, 1.092443",\ + "0.059558, 0.100025, 0.181106, 0.428872, 1.092443",\ + "0.087354, 0.133744, 0.204884, 0.431205, 1.092443"); + } + + } /* end of arc otp_obs_i[0]_ast2padmux_o[0]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "otp_obs_i[0]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.119334, 0.186028, 0.302368, 0.619155, 1.468929",\ + "0.204833, 0.271716, 0.388876, 0.705544, 1.554647",\ + "0.293319, 0.360401, 0.477846, 0.795625, 1.643707",\ + "0.440314, 0.508488, 0.625608, 0.945855, 1.792734",\ + "0.667813, 0.745674, 0.864272, 1.183300, 2.031636"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.183691, 0.382409, 0.935142, 2.413233",\ + "0.067620, 0.183691, 0.382409, 0.935142, 2.413233",\ + "0.068262, 0.183691, 0.382508, 0.936031, 2.413233",\ + "0.073482, 0.184226, 0.382946, 0.939859, 2.413233",\ + "0.089380, 0.196045, 0.384240, 0.939859, 2.423100"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.094521, 0.125776, 0.178422, 0.320849, 0.699535",\ + "0.188239, 0.219444, 0.272075, 0.414540, 0.793202",\ + "0.291550, 0.323577, 0.376197, 0.518700, 0.897237",\ + "0.473699, 0.510899, 0.563627, 0.705929, 1.084022",\ + "0.773733, 0.823401, 0.885774, 1.030256, 1.407808"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039633, 0.090291, 0.180152, 0.428296, 1.092222",\ + "0.040262, 0.090291, 0.180217, 0.428296, 1.092377",\ + "0.044064, 0.091627, 0.180452, 0.428296, 1.092425",\ + "0.058805, 0.099616, 0.181075, 0.428844, 1.092425",\ + "0.086478, 0.132591, 0.204027, 0.431125, 1.092425"); + } + + } /* end of arc otp_obs_i[0]_ast2padmux_o[0]_una_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380000.312500, 380000.312500, 380000.343750, 380000.406250, 380000.593750",\ + "380000.406250, 380000.406250, 380000.437500, 380000.500000, 380000.687500",\ + "380000.500000, 380000.500000, 380000.531250, 380000.593750, 380000.781250",\ + "380000.656250, 380000.656250, 380000.687500, 380000.750000, 380000.937500",\ + "380000.906250, 380000.906250, 380000.937500, 380001.000000, 380001.187500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180697, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180697, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180697, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180697, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180697, 0.429275, 1.092497"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380001.781250, 380001.843750, 380001.968750, 380002.281250, 380003.156250",\ + "380001.875000, 380001.937500, 380002.062500, 380002.375000, 380003.250000",\ + "380002.000000, 380002.062500, 380002.187500, 380002.500000, 380003.375000",\ + "380002.187500, 380002.250000, 380002.375000, 380002.687500, 380003.562500",\ + "380002.500000, 380002.562500, 380002.687500, 380003.000000, 380003.875000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073650, 0.189304, 0.392450, 0.950561, 2.441537",\ + "0.073650, 0.189304, 0.392450, 0.950561, 2.441537",\ + "0.073650, 0.189304, 0.392450, 0.950561, 2.441537",\ + "0.073650, 0.189304, 0.392450, 0.950561, 2.441537",\ + "0.073650, 0.189304, 0.392450, 0.950561, 2.441537"); + } + + } /* end of arc padmux2ast_i[4]_ast2padmux_o[0]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380000.312500, 380000.312500, 380000.343750, 380000.406250, 380000.593750",\ + "380000.406250, 380000.406250, 380000.437500, 380000.500000, 380000.687500",\ + "380000.468750, 380000.468750, 380000.500000, 380000.562500, 380000.750000",\ + "380000.625000, 380000.625000, 380000.656250, 380000.718750, 380000.906250",\ + "380000.843750, 380000.843750, 380000.875000, 380000.937500, 380001.125000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380001.781250, 380001.812500, 380001.906250, 380002.187500, 380002.875000",\ + "380001.875000, 380001.906250, 380002.000000, 380002.281250, 380002.968750",\ + "380001.968750, 380002.000000, 380002.093750, 380002.375000, 380003.062500",\ + "380002.156250, 380002.187500, 380002.281250, 380002.562500, 380003.250000",\ + "380002.406250, 380002.437500, 380002.531250, 380002.812500, 380003.500000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169"); + } + + } /* end of arc padmux2ast_i[4]_ast2padmux_o[0]_inv_min*/ + +} /* end of pin ast2padmux_o[0] */ +} /* end of bus ast2padmux_o */ + +pin("ast2pad_t0_ao") { + direction : output ; + max_transition : 5.000000 ; + min_transition : 0.000000 ; + max_capacitance : 0.340000 ; + min_capacitance : 0.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : ast2pad_t0_ao; +} /* end of pin ast2pad_t0_ao */ + +pin("ast2pad_t1_ao") { + direction : output ; + max_transition : 5.000000 ; + min_transition : 0.000000 ; + max_capacitance : 64.000000 ; + min_capacitance : 0.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : ast2pad_t1_ao; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 8.000000, 16.000000, 32.000000, 64.000000"); + values ( "380005.937500, 380010.968750, 380015.437500, 380024.343750, 380042.031250",\ + "380006.031250, 380011.062500, 380015.531250, 380024.437500, 380042.125000",\ + "380006.125000, 380011.156250, 380015.625000, 380024.531250, 380042.218750",\ + "380006.187500, 380011.218750, 380015.687500, 380024.593750, 380042.281250",\ + "380006.531250, 380011.562500, 380016.031250, 380024.937500, 380042.625000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 8.000000, 16.000000, 32.000000, 64.000000"); + values ( "0.131672, 1.724206, 3.350886, 6.646091, 13.236232",\ + "0.131672, 1.724206, 3.350886, 6.646091, 13.236232",\ + "0.131672, 1.724206, 3.350886, 6.646091, 13.236232",\ + "0.131672, 1.724206, 3.350886, 6.646091, 13.236232",\ + "0.131672, 1.724206, 3.350886, 6.646091, 13.236232"); + } + + } /* end of arc clk_ast_tlul_i_ast2pad_t1_ao_redgf*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 8.000000, 16.000000, 32.000000, 64.000000"); + values ( "3.958968, 8.968638, 13.431835, 22.333540, 40.062149",\ + "4.046352, 9.056024, 13.519220, 22.420925, 40.149536",\ + "4.127131, 9.136803, 13.599998, 22.501705, 40.230312",\ + "4.184652, 9.194324, 13.657520, 22.559225, 40.287834",\ + "4.486489, 9.496161, 13.959356, 22.861061, 40.589668"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 8.000000, 16.000000, 32.000000, 64.000000"); + values ( "0.000000, 0.000000, 0.000000, 0.000000, 0.000000",\ + "0.000000, 0.000000, 0.000000, 0.000000, 0.000000",\ + "0.000000, 0.000000, 0.000000, 0.000000, 0.000000",\ + "0.000000, 0.000000, 0.000000, 0.000000, 0.000000",\ + "0.000000, 0.000000, 0.000000, 0.000000, 0.000000"); + } + + } /* end of arc clk_ast_tlul_i_ast2pad_t1_ao_redgf_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : three_state_enable_fall ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 8.000000, 16.000000, 32.000000, 64.000000"); + values ( "380005.843750, 380010.875000, 380015.343750, 380024.250000, 380041.937500",\ + "380005.937500, 380010.968750, 380015.437500, 380024.343750, 380042.031250",\ + "380006.062500, 380011.093750, 380015.562500, 380024.468750, 380042.156250",\ + "380006.250000, 380011.281250, 380015.750000, 380024.656250, 380042.343750",\ + "380006.562500, 380011.593750, 380016.062500, 380024.968750, 380042.656250"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 8.000000, 16.000000, 32.000000, 64.000000"); + values ( "0.131672, 1.724206, 3.350886, 6.646091, 13.236232",\ + "0.131672, 1.724206, 3.350886, 6.646091, 13.236232",\ + "0.131672, 1.724206, 3.350886, 6.646091, 13.236232",\ + "0.131672, 1.724206, 3.350886, 6.646091, 13.236232",\ + "0.131672, 1.724206, 3.350886, 6.646091, 13.236232"); + } + + } /* end of arc padmux2ast_i[4]_ast2pad_t1_ao_enlf*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : three_state_enable_fall ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 8.000000, 16.000000, 32.000000, 64.000000"); + values ( "380005.843750, 380010.875000, 380015.343750, 380024.250000, 380041.937500",\ + "380005.937500, 380010.968750, 380015.437500, 380024.343750, 380042.031250",\ + "380006.031250, 380011.062500, 380015.531250, 380024.437500, 380042.125000",\ + "380006.218750, 380011.250000, 380015.718750, 380024.625000, 380042.312500",\ + "380006.468750, 380011.500000, 380015.968750, 380024.875000, 380042.562500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 8.000000, 16.000000, 32.000000, 64.000000"); + values ( "0.000000, 0.000000, 0.000000, 0.000000, 0.000000",\ + "0.000000, 0.000000, 0.000000, 0.000000, 0.000000",\ + "0.000000, 0.000000, 0.000000, 0.000000, 0.000000",\ + "0.000000, 0.000000, 0.000000, 0.000000, 0.000000",\ + "0.000000, 0.000000, 0.000000, 0.000000, 0.000000"); + } + + } /* end of arc padmux2ast_i[4]_ast2pad_t1_ao_enlf_min*/ + +} /* end of pin ast2pad_t1_ao */ +bus ( ext_freq_is_96m_i ) { + + bus_type : BUS4_type6 ; + direction : input ; + +pin("ext_freq_is_96m_i[3]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000648 ; + + /* Other user defined attributes. */ + original_pin : ext_freq_is_96m_i[3]; +} /* end of pin ext_freq_is_96m_i[3] */ + +pin("ext_freq_is_96m_i[2]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001189 ; + + /* Other user defined attributes. */ + original_pin : ext_freq_is_96m_i[2]; +} /* end of pin ext_freq_is_96m_i[2] */ + +pin("ext_freq_is_96m_i[1]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001189 ; + + /* Other user defined attributes. */ + original_pin : ext_freq_is_96m_i[1]; +} /* end of pin ext_freq_is_96m_i[1] */ + +pin("ext_freq_is_96m_i[0]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000648 ; + + /* Other user defined attributes. */ + original_pin : ext_freq_is_96m_i[0]; +} /* end of pin ext_freq_is_96m_i[0] */ +} /* end of bus ext_freq_is_96m_i */ +bus ( all_clk_byp_req_i ) { + + bus_type : BUS4_type6 ; + direction : input ; + +pin("all_clk_byp_req_i[3]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000648 ; + + /* Other user defined attributes. */ + original_pin : all_clk_byp_req_i[3]; +} /* end of pin all_clk_byp_req_i[3] */ + +pin("all_clk_byp_req_i[2]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001189 ; + + /* Other user defined attributes. */ + original_pin : all_clk_byp_req_i[2]; +} /* end of pin all_clk_byp_req_i[2] */ + +pin("all_clk_byp_req_i[1]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001189 ; + + /* Other user defined attributes. */ + original_pin : all_clk_byp_req_i[1]; +} /* end of pin all_clk_byp_req_i[1] */ + +pin("all_clk_byp_req_i[0]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000648 ; + + /* Other user defined attributes. */ + original_pin : all_clk_byp_req_i[0]; +} /* end of pin all_clk_byp_req_i[0] */ +} /* end of bus all_clk_byp_req_i */ +bus ( all_clk_byp_ack_o ) { + + bus_type : BUS4_type6 ; + direction : output ; + +pin("all_clk_byp_ack_o[3]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.161713 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : all_clk_byp_ack_o[3]; + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.100843, 0.266735, 0.427088, 0.747616, 1.388635",\ + "0.184687, 0.350464, 0.510809, 0.831717, 1.473578",\ + "0.260267, 0.426010, 0.586434, 0.907636, 1.550114",\ + "0.386507, 0.552662, 0.713534, 1.034573, 1.676504",\ + "0.580400, 0.747044, 0.907773, 1.228098, 1.868510"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015579, 0.316961, 0.624670, 1.238691, 2.466601",\ + "0.015665, 0.316961, 0.624670, 1.238691, 2.466601",\ + "0.015665, 0.317088, 0.625771, 1.239746, 2.466601",\ + "0.015838, 0.317088, 0.625771, 1.239746, 2.466601",\ + "0.016716, 0.317340, 0.625771, 1.239746, 2.466601"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.088041, 0.202376, 0.303813, 0.506089, 0.910516",\ + "0.168483, 0.282824, 0.383745, 0.585711, 0.989669",\ + "0.247358, 0.362640, 0.463376, 0.664815, 1.067688",\ + "0.380658, 0.500049, 0.601022, 0.802517, 1.205414",\ + "0.586485, 0.719001, 0.819955, 1.021830, 1.425575"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015700, 0.193950, 0.379890, 0.747742, 1.482887",\ + "0.016044, 0.193950, 0.379890, 0.747742, 1.485202",\ + "0.017520, 0.193950, 0.379890, 0.747742, 1.485202",\ + "0.022344, 0.194037, 0.379890, 0.747742, 1.485202",\ + "0.034639, 0.196727, 0.379890, 0.748439, 1.491839"); + } + + } /* end of arc clk_ast_ext_i_all_clk_byp_ack_o[3]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.100718, 0.266618, 0.426903, 0.747412, 1.388420",\ + "0.184686, 0.350463, 0.510806, 0.831715, 1.473578",\ + "0.260208, 0.425985, 0.586426, 0.907607, 1.550030",\ + "0.386259, 0.552119, 0.712336, 1.032993, 1.674352",\ + "0.580173, 0.746795, 0.907585, 1.227594, 1.867283"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015496, 0.316821, 0.622606, 1.236473, 2.462725",\ + "0.015496, 0.316821, 0.622606, 1.236473, 2.462725",\ + "0.015496, 0.316929, 0.622606, 1.236473, 2.462725",\ + "0.015814, 0.316929, 0.622606, 1.236473, 2.462725",\ + "0.016700, 0.316929, 0.623370, 1.236473, 2.462725"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.087868, 0.202376, 0.303809, 0.506029, 0.910334",\ + "0.168483, 0.282824, 0.383745, 0.585711, 0.989669",\ + "0.247358, 0.362640, 0.463376, 0.664779, 1.067573",\ + "0.380658, 0.500049, 0.601022, 0.802517, 1.205414",\ + "0.586485, 0.718955, 0.819794, 1.021516, 1.424967"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015619, 0.192979, 0.376641, 0.744531, 1.480142",\ + "0.016032, 0.192979, 0.376641, 0.744531, 1.480142",\ + "0.017339, 0.192979, 0.376641, 0.744531, 1.480142",\ + "0.022190, 0.193551, 0.376842, 0.744531, 1.480142",\ + "0.033893, 0.196557, 0.377640, 0.746288, 1.484937"); + } + + } /* end of arc clk_ast_ext_i_all_clk_byp_ack_o[3]_redg_min*/ + + timing () { + related_pin : "clk_src_io_o" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.103995, 0.269872, 0.430200, 0.750758, 1.391853",\ + "0.158337, 0.324154, 0.484388, 0.804979, 1.446186",\ + "0.282603, 0.448419, 0.608923, 0.930096, 1.572477",\ + "0.334665, 0.500651, 0.661339, 0.982445, 1.624600",\ + "0.580400, 0.747044, 0.907773, 1.228098, 1.868510"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015542, 0.317035, 0.624600, 1.238588, 2.466325",\ + "0.015645, 0.317035, 0.624600, 1.238588, 2.466325",\ + "0.015645, 0.317066, 0.625211, 1.239292, 2.466325",\ + "0.015655, 0.317066, 0.625211, 1.239292, 2.466325",\ + "0.016716, 0.317340, 0.625211, 1.239292, 2.466325"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.090477, 0.204718, 0.305888, 0.507773, 0.911447",\ + "0.141442, 0.255688, 0.356617, 0.558511, 0.962305",\ + "0.270943, 0.386953, 0.487730, 0.689180, 1.092056",\ + "0.325917, 0.443620, 0.544496, 0.745968, 1.148855",\ + "0.586485, 0.719001, 0.819955, 1.021830, 1.425575"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015734, 0.193610, 0.378735, 0.747021, 1.483183",\ + "0.015916, 0.193610, 0.378735, 0.747293, 1.484513",\ + "0.018374, 0.193610, 0.378735, 0.747293, 1.484513",\ + "0.020363, 0.193614, 0.378735, 0.747293, 1.484513",\ + "0.034639, 0.196727, 0.378735, 0.748439, 1.491839"); + } + + } /* end of arc clk_src_io_o_all_clk_byp_ack_o[3]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_src_io_o" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.103875, 0.269735, 0.430056, 0.750620, 1.391729",\ + "0.158336, 0.324133, 0.484382, 0.804893, 1.445917",\ + "0.282510, 0.448302, 0.608704, 0.929792, 1.572026",\ + "0.333572, 0.499397, 0.659708, 0.980584, 1.622387",\ + "0.580173, 0.746795, 0.907585, 1.227594, 1.867283"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015480, 0.316838, 0.623370, 1.236473, 2.462725",\ + "0.015480, 0.316838, 0.623370, 1.236473, 2.462725",\ + "0.015480, 0.316929, 0.623370, 1.236473, 2.462725",\ + "0.015652, 0.316929, 0.623370, 1.236473, 2.462725",\ + "0.016700, 0.316929, 0.623370, 1.236473, 2.462725"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.090378, 0.204717, 0.305882, 0.507735, 0.911343",\ + "0.141442, 0.255688, 0.356617, 0.558510, 0.962304",\ + "0.270943, 0.386953, 0.487730, 0.689150, 1.091961",\ + "0.324941, 0.442615, 0.543488, 0.744945, 1.147798",\ + "0.586485, 0.718955, 0.819794, 1.021516, 1.424967"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015687, 0.193080, 0.376676, 0.744928, 1.481536",\ + "0.015912, 0.193080, 0.376676, 0.744928, 1.481536",\ + "0.018197, 0.193080, 0.376676, 0.744928, 1.481536",\ + "0.020162, 0.193312, 0.376758, 0.744928, 1.481536",\ + "0.033893, 0.196557, 0.377640, 0.746288, 1.484937"); + } + + } /* end of arc clk_src_io_o_all_clk_byp_ack_o[3]_redg_min*/ + +} /* end of pin all_clk_byp_ack_o[3] */ + +pin("all_clk_byp_ack_o[2]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.158177 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : all_clk_byp_ack_o[2]; + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.055481, 0.185725, 0.392886, 0.714270, 1.356390",\ + "0.142013, 0.273097, 0.480288, 0.802449, 1.446276",\ + "0.227644, 0.367997, 0.574907, 0.896875, 1.540369",\ + "0.372058, 0.538899, 0.745297, 1.066605, 1.708810",\ + "0.601931, 0.834236, 1.042645, 1.363437, 2.003839"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.021797, 0.238359, 0.631876, 1.247087, 2.477274",\ + "0.025516, 0.238359, 0.631876, 1.247087, 2.477274",\ + "0.039138, 0.240277, 0.631876, 1.247087, 2.477473",\ + "0.067159, 0.248694, 0.631876, 1.247087, 2.479640",\ + "0.123088, 0.289704, 0.642858, 1.251241, 2.479640"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.082179, 0.183018, 0.316461, 0.522191, 0.932963",\ + "0.170164, 0.270956, 0.404436, 0.610175, 1.020954",\ + "0.251445, 0.351944, 0.485256, 0.690977, 1.101771",\ + "0.388999, 0.491163, 0.624361, 0.829801, 1.240010",\ + "0.607343, 0.718683, 0.852150, 1.057410, 1.467133"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.025565, 0.151628, 0.387851, 0.763293, 1.515348",\ + "0.025565, 0.151804, 0.389259, 0.763293, 1.515348",\ + "0.025976, 0.151804, 0.389479, 0.764390, 1.515348",\ + "0.029120, 0.151804, 0.389479, 0.764390, 1.515348",\ + "0.041734, 0.154598, 0.389479, 0.764390, 1.515348"); + } + + } /* end of arc clk_ast_ext_i_all_clk_byp_ack_o[2]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.055478, 0.185724, 0.392885, 0.714263, 1.356368",\ + "0.141644, 0.273073, 0.480017, 0.801359, 1.443459",\ + "0.227644, 0.367995, 0.574890, 0.896861, 1.540369",\ + "0.372055, 0.538895, 0.745296, 1.066605, 1.708810",\ + "0.601899, 0.834203, 1.042596, 1.363402, 2.003839"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.021795, 0.238265, 0.630524, 1.245754, 2.477107",\ + "0.025501, 0.238265, 0.630524, 1.245754, 2.477170",\ + "0.039138, 0.240263, 0.630524, 1.245754, 2.477473",\ + "0.067158, 0.248694, 0.630752, 1.245754, 2.478674",\ + "0.122913, 0.289395, 0.639350, 1.248196, 2.478674"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.082179, 0.183018, 0.316461, 0.522190, 0.932959",\ + "0.170151, 0.270913, 0.404355, 0.610080, 1.020840",\ + "0.251186, 0.351686, 0.484981, 0.690703, 1.101507",\ + "0.388979, 0.491150, 0.624343, 0.829707, 1.239752",\ + "0.607308, 0.718634, 0.852099, 1.057372, 1.467127"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.025557, 0.151128, 0.387354, 0.761934, 1.510661",\ + "0.025557, 0.151128, 0.387354, 0.761934, 1.510661",\ + "0.025965, 0.151128, 0.387354, 0.761934, 1.511090",\ + "0.029101, 0.151585, 0.387354, 0.761934, 1.511090",\ + "0.041668, 0.154530, 0.388178, 0.761934, 1.511090"); + } + + } /* end of arc clk_ast_ext_i_all_clk_byp_ack_o[2]_redg_min*/ + + timing () { + related_pin : "clk_src_io_o" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.058414, 0.188667, 0.395813, 0.717110, 1.359045",\ + "0.112550, 0.243041, 0.450135, 0.772138, 1.415649",\ + "0.253196, 0.398235, 0.605055, 0.926906, 1.570171",\ + "0.312752, 0.468715, 0.675324, 0.996903, 1.639637",\ + "0.601931, 0.834236, 1.042645, 1.363437, 2.003839"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.021790, 0.238360, 0.631894, 1.247121, 2.477336",\ + "0.023317, 0.238360, 0.631894, 1.247121, 2.477336",\ + "0.044096, 0.241766, 0.631894, 1.247121, 2.477920",\ + "0.055652, 0.245238, 0.631894, 1.247121, 2.478962",\ + "0.123088, 0.289704, 0.642858, 1.251241, 2.479640"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.085404, 0.186224, 0.319679, 0.525413, 0.936188",\ + "0.141978, 0.242754, 0.376239, 0.581985, 0.992777",\ + "0.275783, 0.376576, 0.509868, 0.715539, 1.126231",\ + "0.332511, 0.433991, 0.567236, 0.772791, 1.183241",\ + "0.607343, 0.718683, 0.852150, 1.057410, 1.467133"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.025646, 0.151693, 0.388430, 0.763132, 1.513362",\ + "0.025646, 0.151849, 0.389568, 0.763815, 1.513362",\ + "0.026529, 0.151849, 0.389568, 0.764056, 1.513362",\ + "0.027825, 0.151849, 0.389568, 0.764056, 1.513362",\ + "0.041734, 0.154598, 0.389568, 0.764056, 1.513362"); + } + + } /* end of arc clk_src_io_o_all_clk_byp_ack_o[2]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_src_io_o" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.058410, 0.188665, 0.395812, 0.717100, 1.359014",\ + "0.112399, 0.243028, 0.450025, 0.771635, 1.414310",\ + "0.253195, 0.398233, 0.605040, 0.926895, 1.570171",\ + "0.311693, 0.467461, 0.674069, 0.995655, 1.638404",\ + "0.601899, 0.834203, 1.042596, 1.363402, 2.003839"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.021782, 0.238225, 0.630549, 1.245808, 2.476689",\ + "0.023311, 0.238225, 0.630549, 1.245808, 2.476689",\ + "0.044096, 0.241755, 0.630564, 1.245808, 2.477789",\ + "0.055446, 0.245170, 0.630656, 1.245808, 2.478512",\ + "0.122913, 0.289395, 0.639350, 1.248196, 2.478674"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.085404, 0.186224, 0.319679, 0.525413, 0.936188",\ + "0.141970, 0.242733, 0.376196, 0.581868, 0.992503",\ + "0.275567, 0.376362, 0.509639, 0.715298, 1.125968",\ + "0.331384, 0.432856, 0.566092, 0.771606, 1.181968",\ + "0.607308, 0.718634, 0.852099, 1.057372, 1.467127"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.025646, 0.151208, 0.387784, 0.761934, 1.511090",\ + "0.025646, 0.151208, 0.387784, 0.761934, 1.511090",\ + "0.026523, 0.151208, 0.387784, 0.761934, 1.511090",\ + "0.027795, 0.151394, 0.387784, 0.761934, 1.511090",\ + "0.041668, 0.154530, 0.388178, 0.761934, 1.511090"); + } + + } /* end of arc clk_src_io_o_all_clk_byp_ack_o[2]_redg_min*/ + +} /* end of pin all_clk_byp_ack_o[2] */ + +pin("all_clk_byp_ack_o[1]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.158177 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : all_clk_byp_ack_o[1]; + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.055481, 0.185725, 0.392886, 0.714270, 1.356390",\ + "0.142013, 0.273097, 0.480288, 0.802449, 1.446276",\ + "0.227644, 0.367997, 0.574907, 0.896875, 1.540369",\ + "0.372058, 0.538899, 0.745297, 1.066605, 1.708810",\ + "0.601931, 0.834236, 1.042645, 1.363437, 2.003839"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.021797, 0.238359, 0.631876, 1.247087, 2.477274",\ + "0.025516, 0.238359, 0.631876, 1.247087, 2.477274",\ + "0.039138, 0.240277, 0.631876, 1.247087, 2.477473",\ + "0.067159, 0.248694, 0.631876, 1.247087, 2.479640",\ + "0.123088, 0.289704, 0.642858, 1.251241, 2.479640"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.082179, 0.183018, 0.316461, 0.522191, 0.932963",\ + "0.170164, 0.270956, 0.404436, 0.610175, 1.020954",\ + "0.251445, 0.351944, 0.485256, 0.690977, 1.101771",\ + "0.388999, 0.491163, 0.624361, 0.829801, 1.240010",\ + "0.607343, 0.718683, 0.852150, 1.057410, 1.467133"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.025565, 0.151628, 0.387851, 0.763293, 1.515348",\ + "0.025565, 0.151804, 0.389259, 0.763293, 1.515348",\ + "0.025976, 0.151804, 0.389479, 0.764390, 1.515348",\ + "0.029120, 0.151804, 0.389479, 0.764390, 1.515348",\ + "0.041734, 0.154598, 0.389479, 0.764390, 1.515348"); + } + + } /* end of arc clk_ast_ext_i_all_clk_byp_ack_o[1]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.055478, 0.185724, 0.392885, 0.714263, 1.356368",\ + "0.141644, 0.273073, 0.480017, 0.801359, 1.443459",\ + "0.227644, 0.367995, 0.574890, 0.896861, 1.540369",\ + "0.372055, 0.538895, 0.745296, 1.066605, 1.708810",\ + "0.601899, 0.834203, 1.042596, 1.363402, 2.003839"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.021795, 0.238265, 0.630524, 1.245754, 2.477107",\ + "0.025501, 0.238265, 0.630524, 1.245754, 2.477170",\ + "0.039138, 0.240263, 0.630524, 1.245754, 2.477473",\ + "0.067158, 0.248694, 0.630752, 1.245754, 2.478674",\ + "0.122913, 0.289395, 0.639350, 1.248196, 2.478674"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.082179, 0.183018, 0.316461, 0.522190, 0.932959",\ + "0.170151, 0.270913, 0.404355, 0.610080, 1.020840",\ + "0.251186, 0.351686, 0.484981, 0.690703, 1.101507",\ + "0.388979, 0.491150, 0.624343, 0.829707, 1.239752",\ + "0.607308, 0.718634, 0.852099, 1.057372, 1.467127"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.025557, 0.151128, 0.387354, 0.761934, 1.510661",\ + "0.025557, 0.151128, 0.387354, 0.761934, 1.510661",\ + "0.025965, 0.151128, 0.387354, 0.761934, 1.511090",\ + "0.029101, 0.151585, 0.387354, 0.761934, 1.511090",\ + "0.041668, 0.154530, 0.388178, 0.761934, 1.511090"); + } + + } /* end of arc clk_ast_ext_i_all_clk_byp_ack_o[1]_redg_min*/ + + timing () { + related_pin : "clk_src_io_o" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.058414, 0.188667, 0.395813, 0.717110, 1.359045",\ + "0.112550, 0.243041, 0.450135, 0.772138, 1.415649",\ + "0.253196, 0.398235, 0.605055, 0.926906, 1.570171",\ + "0.312752, 0.468715, 0.675324, 0.996903, 1.639637",\ + "0.601931, 0.834236, 1.042645, 1.363437, 2.003839"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.021790, 0.238360, 0.631894, 1.247121, 2.477336",\ + "0.023317, 0.238360, 0.631894, 1.247121, 2.477336",\ + "0.044096, 0.241766, 0.631894, 1.247121, 2.477920",\ + "0.055652, 0.245238, 0.631894, 1.247121, 2.478962",\ + "0.123088, 0.289704, 0.642858, 1.251241, 2.479640"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.085404, 0.186224, 0.319679, 0.525413, 0.936188",\ + "0.141978, 0.242754, 0.376239, 0.581985, 0.992777",\ + "0.275783, 0.376576, 0.509868, 0.715539, 1.126231",\ + "0.332511, 0.433991, 0.567236, 0.772791, 1.183241",\ + "0.607343, 0.718683, 0.852150, 1.057410, 1.467133"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.025646, 0.151693, 0.388430, 0.763132, 1.513362",\ + "0.025646, 0.151849, 0.389568, 0.763815, 1.513362",\ + "0.026529, 0.151849, 0.389568, 0.764056, 1.513362",\ + "0.027825, 0.151849, 0.389568, 0.764056, 1.513362",\ + "0.041734, 0.154598, 0.389568, 0.764056, 1.513362"); + } + + } /* end of arc clk_src_io_o_all_clk_byp_ack_o[1]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_src_io_o" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.058410, 0.188665, 0.395812, 0.717100, 1.359014",\ + "0.112399, 0.243028, 0.450025, 0.771635, 1.414310",\ + "0.253195, 0.398233, 0.605040, 0.926895, 1.570171",\ + "0.311693, 0.467461, 0.674069, 0.995655, 1.638404",\ + "0.601899, 0.834203, 1.042596, 1.363402, 2.003839"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.021782, 0.238225, 0.630549, 1.245808, 2.476689",\ + "0.023311, 0.238225, 0.630549, 1.245808, 2.476689",\ + "0.044096, 0.241755, 0.630564, 1.245808, 2.477789",\ + "0.055446, 0.245170, 0.630656, 1.245808, 2.478512",\ + "0.122913, 0.289395, 0.639350, 1.248196, 2.478674"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.085404, 0.186224, 0.319679, 0.525413, 0.936188",\ + "0.141970, 0.242733, 0.376196, 0.581868, 0.992503",\ + "0.275567, 0.376362, 0.509639, 0.715298, 1.125968",\ + "0.331384, 0.432856, 0.566092, 0.771606, 1.181968",\ + "0.607308, 0.718634, 0.852099, 1.057372, 1.467127"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.025646, 0.151208, 0.387784, 0.761934, 1.511090",\ + "0.025646, 0.151208, 0.387784, 0.761934, 1.511090",\ + "0.026523, 0.151208, 0.387784, 0.761934, 1.511090",\ + "0.027795, 0.151394, 0.387784, 0.761934, 1.511090",\ + "0.041668, 0.154530, 0.388178, 0.761934, 1.511090"); + } + + } /* end of arc clk_src_io_o_all_clk_byp_ack_o[1]_redg_min*/ + +} /* end of pin all_clk_byp_ack_o[1] */ + +pin("all_clk_byp_ack_o[0]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.161713 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : all_clk_byp_ack_o[0]; + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.100843, 0.266735, 0.427088, 0.747616, 1.388635",\ + "0.184687, 0.350464, 0.510809, 0.831717, 1.473578",\ + "0.260267, 0.426010, 0.586434, 0.907636, 1.550114",\ + "0.386507, 0.552662, 0.713534, 1.034573, 1.676504",\ + "0.580400, 0.747044, 0.907773, 1.228098, 1.868510"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015579, 0.316961, 0.624670, 1.238691, 2.466601",\ + "0.015665, 0.316961, 0.624670, 1.238691, 2.466601",\ + "0.015665, 0.317088, 0.625771, 1.239746, 2.466601",\ + "0.015838, 0.317088, 0.625771, 1.239746, 2.466601",\ + "0.016716, 0.317340, 0.625771, 1.239746, 2.466601"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.088041, 0.202376, 0.303813, 0.506089, 0.910516",\ + "0.168483, 0.282824, 0.383745, 0.585711, 0.989669",\ + "0.247358, 0.362640, 0.463376, 0.664815, 1.067688",\ + "0.380658, 0.500049, 0.601022, 0.802517, 1.205414",\ + "0.586485, 0.719001, 0.819955, 1.021830, 1.425575"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015700, 0.193950, 0.379890, 0.747742, 1.482887",\ + "0.016044, 0.193950, 0.379890, 0.747742, 1.485202",\ + "0.017520, 0.193950, 0.379890, 0.747742, 1.485202",\ + "0.022344, 0.194037, 0.379890, 0.747742, 1.485202",\ + "0.034639, 0.196727, 0.379890, 0.748439, 1.491839"); + } + + } /* end of arc clk_ast_ext_i_all_clk_byp_ack_o[0]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.100718, 0.266618, 0.426903, 0.747412, 1.388420",\ + "0.184686, 0.350463, 0.510806, 0.831715, 1.473578",\ + "0.260208, 0.425985, 0.586426, 0.907607, 1.550030",\ + "0.386259, 0.552119, 0.712336, 1.032993, 1.674352",\ + "0.580173, 0.746795, 0.907585, 1.227594, 1.867283"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015496, 0.316821, 0.622606, 1.236473, 2.462725",\ + "0.015496, 0.316821, 0.622606, 1.236473, 2.462725",\ + "0.015496, 0.316929, 0.622606, 1.236473, 2.462725",\ + "0.015814, 0.316929, 0.622606, 1.236473, 2.462725",\ + "0.016700, 0.316929, 0.623370, 1.236473, 2.462725"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.087868, 0.202376, 0.303809, 0.506029, 0.910334",\ + "0.168483, 0.282824, 0.383745, 0.585711, 0.989669",\ + "0.247358, 0.362640, 0.463376, 0.664779, 1.067573",\ + "0.380658, 0.500049, 0.601022, 0.802517, 1.205414",\ + "0.586485, 0.718955, 0.819794, 1.021516, 1.424967"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015619, 0.192979, 0.376641, 0.744531, 1.480142",\ + "0.016032, 0.192979, 0.376641, 0.744531, 1.480142",\ + "0.017339, 0.192979, 0.376641, 0.744531, 1.480142",\ + "0.022190, 0.193551, 0.376842, 0.744531, 1.480142",\ + "0.033893, 0.196557, 0.377640, 0.746288, 1.484937"); + } + + } /* end of arc clk_ast_ext_i_all_clk_byp_ack_o[0]_redg_min*/ + + timing () { + related_pin : "clk_src_io_o" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.103995, 0.269872, 0.430200, 0.750758, 1.391853",\ + "0.158337, 0.324154, 0.484388, 0.804979, 1.446186",\ + "0.282603, 0.448419, 0.608923, 0.930096, 1.572477",\ + "0.334665, 0.500651, 0.661339, 0.982445, 1.624600",\ + "0.580400, 0.747044, 0.907773, 1.228098, 1.868510"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015542, 0.317035, 0.624600, 1.238588, 2.466325",\ + "0.015645, 0.317035, 0.624600, 1.238588, 2.466325",\ + "0.015645, 0.317066, 0.625211, 1.239292, 2.466325",\ + "0.015655, 0.317066, 0.625211, 1.239292, 2.466325",\ + "0.016716, 0.317340, 0.625211, 1.239292, 2.466325"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.090477, 0.204718, 0.305888, 0.507773, 0.911447",\ + "0.141442, 0.255688, 0.356617, 0.558511, 0.962305",\ + "0.270943, 0.386953, 0.487730, 0.689180, 1.092056",\ + "0.325917, 0.443620, 0.544496, 0.745968, 1.148855",\ + "0.586485, 0.719001, 0.819955, 1.021830, 1.425575"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015734, 0.193610, 0.378735, 0.747021, 1.483183",\ + "0.015916, 0.193610, 0.378735, 0.747293, 1.484513",\ + "0.018374, 0.193610, 0.378735, 0.747293, 1.484513",\ + "0.020363, 0.193614, 0.378735, 0.747293, 1.484513",\ + "0.034639, 0.196727, 0.378735, 0.748439, 1.491839"); + } + + } /* end of arc clk_src_io_o_all_clk_byp_ack_o[0]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_src_io_o" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.103875, 0.269735, 0.430056, 0.750620, 1.391729",\ + "0.158336, 0.324133, 0.484382, 0.804893, 1.445917",\ + "0.282510, 0.448302, 0.608704, 0.929792, 1.572026",\ + "0.333572, 0.499397, 0.659708, 0.980584, 1.622387",\ + "0.580173, 0.746795, 0.907585, 1.227594, 1.867283"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015480, 0.316838, 0.623370, 1.236473, 2.462725",\ + "0.015480, 0.316838, 0.623370, 1.236473, 2.462725",\ + "0.015480, 0.316929, 0.623370, 1.236473, 2.462725",\ + "0.015652, 0.316929, 0.623370, 1.236473, 2.462725",\ + "0.016700, 0.316929, 0.623370, 1.236473, 2.462725"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.090378, 0.204717, 0.305882, 0.507735, 0.911343",\ + "0.141442, 0.255688, 0.356617, 0.558510, 0.962304",\ + "0.270943, 0.386953, 0.487730, 0.689150, 1.091961",\ + "0.324941, 0.442615, 0.543488, 0.744945, 1.147798",\ + "0.586485, 0.718955, 0.819794, 1.021516, 1.424967"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015687, 0.193080, 0.376676, 0.744928, 1.481536",\ + "0.015912, 0.193080, 0.376676, 0.744928, 1.481536",\ + "0.018197, 0.193080, 0.376676, 0.744928, 1.481536",\ + "0.020162, 0.193312, 0.376758, 0.744928, 1.481536",\ + "0.033893, 0.196557, 0.377640, 0.746288, 1.484937"); + } + + } /* end of arc clk_src_io_o_all_clk_byp_ack_o[0]_redg_min*/ + +} /* end of pin all_clk_byp_ack_o[0] */ +} /* end of bus all_clk_byp_ack_o */ +bus ( io_clk_byp_req_i ) { + + bus_type : BUS4_type6 ; + direction : input ; + +pin("io_clk_byp_req_i[3]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000648 ; + + /* Other user defined attributes. */ + original_pin : io_clk_byp_req_i[3]; +} /* end of pin io_clk_byp_req_i[3] */ + +pin("io_clk_byp_req_i[2]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001189 ; + + /* Other user defined attributes. */ + original_pin : io_clk_byp_req_i[2]; +} /* end of pin io_clk_byp_req_i[2] */ + +pin("io_clk_byp_req_i[1]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001189 ; + + /* Other user defined attributes. */ + original_pin : io_clk_byp_req_i[1]; +} /* end of pin io_clk_byp_req_i[1] */ + +pin("io_clk_byp_req_i[0]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000648 ; + + /* Other user defined attributes. */ + original_pin : io_clk_byp_req_i[0]; +} /* end of pin io_clk_byp_req_i[0] */ +} /* end of bus io_clk_byp_req_i */ +bus ( io_clk_byp_ack_o ) { + + bus_type : BUS4_type6 ; + direction : output ; + +pin("io_clk_byp_ack_o[3]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.161713 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : io_clk_byp_ack_o[3]; + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.100843, 0.266735, 0.427088, 0.747616, 1.388635",\ + "0.184687, 0.350464, 0.510809, 0.831717, 1.473578",\ + "0.260267, 0.426010, 0.586434, 0.907636, 1.550114",\ + "0.386507, 0.552662, 0.713534, 1.034573, 1.676504",\ + "0.580400, 0.747044, 0.907773, 1.228098, 1.868510"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015579, 0.316961, 0.624670, 1.238691, 2.466601",\ + "0.015665, 0.316961, 0.624670, 1.238691, 2.466601",\ + "0.015665, 0.317088, 0.625771, 1.239746, 2.466601",\ + "0.015838, 0.317088, 0.625771, 1.239746, 2.466601",\ + "0.016716, 0.317340, 0.625771, 1.239746, 2.466601"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.088041, 0.202376, 0.303813, 0.506089, 0.910516",\ + "0.168483, 0.282824, 0.383745, 0.585711, 0.989669",\ + "0.247358, 0.362640, 0.463376, 0.664815, 1.067688",\ + "0.380658, 0.500049, 0.601022, 0.802517, 1.205414",\ + "0.586485, 0.719001, 0.819955, 1.021830, 1.425575"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015700, 0.193950, 0.379890, 0.747742, 1.482887",\ + "0.016044, 0.193950, 0.379890, 0.747742, 1.485202",\ + "0.017520, 0.193950, 0.379890, 0.747742, 1.485202",\ + "0.022344, 0.194037, 0.379890, 0.747742, 1.485202",\ + "0.034639, 0.196727, 0.379890, 0.748439, 1.491839"); + } + + } /* end of arc clk_ast_ext_i_io_clk_byp_ack_o[3]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.100718, 0.266618, 0.426903, 0.747412, 1.388420",\ + "0.184686, 0.350463, 0.510806, 0.831715, 1.473578",\ + "0.260208, 0.425985, 0.586426, 0.907607, 1.550030",\ + "0.386259, 0.552119, 0.712336, 1.032993, 1.674352",\ + "0.580173, 0.746795, 0.907585, 1.227594, 1.867283"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015496, 0.316821, 0.622606, 1.236473, 2.462725",\ + "0.015496, 0.316821, 0.622606, 1.236473, 2.462725",\ + "0.015496, 0.316929, 0.622606, 1.236473, 2.462725",\ + "0.015814, 0.316929, 0.622606, 1.236473, 2.462725",\ + "0.016700, 0.316929, 0.623370, 1.236473, 2.462725"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.087868, 0.202376, 0.303809, 0.506029, 0.910334",\ + "0.168483, 0.282824, 0.383745, 0.585711, 0.989669",\ + "0.247358, 0.362640, 0.463376, 0.664779, 1.067573",\ + "0.380658, 0.500049, 0.601022, 0.802517, 1.205414",\ + "0.586485, 0.718955, 0.819794, 1.021516, 1.424967"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015619, 0.192979, 0.376641, 0.744531, 1.480142",\ + "0.016032, 0.192979, 0.376641, 0.744531, 1.480142",\ + "0.017339, 0.192979, 0.376641, 0.744531, 1.480142",\ + "0.022190, 0.193551, 0.376842, 0.744531, 1.480142",\ + "0.033893, 0.196557, 0.377640, 0.746288, 1.484937"); + } + + } /* end of arc clk_ast_ext_i_io_clk_byp_ack_o[3]_redg_min*/ + + timing () { + related_pin : "clk_src_io_o" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.103995, 0.269872, 0.430200, 0.750758, 1.391853",\ + "0.158337, 0.324154, 0.484388, 0.804979, 1.446186",\ + "0.282603, 0.448419, 0.608923, 0.930096, 1.572477",\ + "0.334665, 0.500651, 0.661339, 0.982445, 1.624600",\ + "0.580400, 0.747044, 0.907773, 1.228098, 1.868510"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015542, 0.317035, 0.624600, 1.238588, 2.466325",\ + "0.015645, 0.317035, 0.624600, 1.238588, 2.466325",\ + "0.015645, 0.317066, 0.625211, 1.239292, 2.466325",\ + "0.015655, 0.317066, 0.625211, 1.239292, 2.466325",\ + "0.016716, 0.317340, 0.625211, 1.239292, 2.466325"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.090477, 0.204718, 0.305888, 0.507773, 0.911447",\ + "0.141442, 0.255688, 0.356617, 0.558511, 0.962305",\ + "0.270943, 0.386953, 0.487730, 0.689180, 1.092056",\ + "0.325917, 0.443620, 0.544496, 0.745968, 1.148855",\ + "0.586485, 0.719001, 0.819955, 1.021830, 1.425575"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015734, 0.193610, 0.378735, 0.747021, 1.483183",\ + "0.015916, 0.193610, 0.378735, 0.747293, 1.484513",\ + "0.018374, 0.193610, 0.378735, 0.747293, 1.484513",\ + "0.020363, 0.193614, 0.378735, 0.747293, 1.484513",\ + "0.034639, 0.196727, 0.378735, 0.748439, 1.491839"); + } + + } /* end of arc clk_src_io_o_io_clk_byp_ack_o[3]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_src_io_o" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.103875, 0.269735, 0.430056, 0.750620, 1.391729",\ + "0.158336, 0.324133, 0.484382, 0.804893, 1.445917",\ + "0.282510, 0.448302, 0.608704, 0.929792, 1.572026",\ + "0.333572, 0.499397, 0.659708, 0.980584, 1.622387",\ + "0.580173, 0.746795, 0.907585, 1.227594, 1.867283"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015480, 0.316838, 0.623370, 1.236473, 2.462725",\ + "0.015480, 0.316838, 0.623370, 1.236473, 2.462725",\ + "0.015480, 0.316929, 0.623370, 1.236473, 2.462725",\ + "0.015652, 0.316929, 0.623370, 1.236473, 2.462725",\ + "0.016700, 0.316929, 0.623370, 1.236473, 2.462725"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.090378, 0.204717, 0.305882, 0.507735, 0.911343",\ + "0.141442, 0.255688, 0.356617, 0.558510, 0.962304",\ + "0.270943, 0.386953, 0.487730, 0.689150, 1.091961",\ + "0.324941, 0.442615, 0.543488, 0.744945, 1.147798",\ + "0.586485, 0.718955, 0.819794, 1.021516, 1.424967"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015687, 0.193080, 0.376676, 0.744928, 1.481536",\ + "0.015912, 0.193080, 0.376676, 0.744928, 1.481536",\ + "0.018197, 0.193080, 0.376676, 0.744928, 1.481536",\ + "0.020162, 0.193312, 0.376758, 0.744928, 1.481536",\ + "0.033893, 0.196557, 0.377640, 0.746288, 1.484937"); + } + + } /* end of arc clk_src_io_o_io_clk_byp_ack_o[3]_redg_min*/ + +} /* end of pin io_clk_byp_ack_o[3] */ + +pin("io_clk_byp_ack_o[2]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.158177 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : io_clk_byp_ack_o[2]; + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.055481, 0.185725, 0.392886, 0.714270, 1.356390",\ + "0.142013, 0.273097, 0.480288, 0.802449, 1.446276",\ + "0.227644, 0.367997, 0.574907, 0.896875, 1.540369",\ + "0.372058, 0.538899, 0.745297, 1.066605, 1.708810",\ + "0.601931, 0.834236, 1.042645, 1.363437, 2.003839"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.021797, 0.238359, 0.631876, 1.247087, 2.477274",\ + "0.025516, 0.238359, 0.631876, 1.247087, 2.477274",\ + "0.039138, 0.240277, 0.631876, 1.247087, 2.477473",\ + "0.067159, 0.248694, 0.631876, 1.247087, 2.479640",\ + "0.123088, 0.289704, 0.642858, 1.251241, 2.479640"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.082179, 0.183018, 0.316461, 0.522191, 0.932963",\ + "0.170164, 0.270956, 0.404436, 0.610175, 1.020954",\ + "0.251445, 0.351944, 0.485256, 0.690977, 1.101771",\ + "0.388999, 0.491163, 0.624361, 0.829801, 1.240010",\ + "0.607343, 0.718683, 0.852150, 1.057410, 1.467133"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.025565, 0.151628, 0.387851, 0.763293, 1.515348",\ + "0.025565, 0.151804, 0.389259, 0.763293, 1.515348",\ + "0.025976, 0.151804, 0.389479, 0.764390, 1.515348",\ + "0.029120, 0.151804, 0.389479, 0.764390, 1.515348",\ + "0.041734, 0.154598, 0.389479, 0.764390, 1.515348"); + } + + } /* end of arc clk_ast_ext_i_io_clk_byp_ack_o[2]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.055478, 0.185724, 0.392885, 0.714263, 1.356368",\ + "0.141644, 0.273073, 0.480017, 0.801359, 1.443459",\ + "0.227644, 0.367995, 0.574890, 0.896861, 1.540369",\ + "0.372055, 0.538895, 0.745296, 1.066605, 1.708810",\ + "0.601899, 0.834203, 1.042596, 1.363402, 2.003839"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.021795, 0.238265, 0.630524, 1.245754, 2.477107",\ + "0.025501, 0.238265, 0.630524, 1.245754, 2.477170",\ + "0.039138, 0.240263, 0.630524, 1.245754, 2.477473",\ + "0.067158, 0.248694, 0.630752, 1.245754, 2.478674",\ + "0.122913, 0.289395, 0.639350, 1.248196, 2.478674"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.082179, 0.183018, 0.316461, 0.522190, 0.932959",\ + "0.170151, 0.270913, 0.404355, 0.610080, 1.020840",\ + "0.251186, 0.351686, 0.484981, 0.690703, 1.101507",\ + "0.388979, 0.491150, 0.624343, 0.829707, 1.239752",\ + "0.607308, 0.718634, 0.852099, 1.057372, 1.467127"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.025557, 0.151128, 0.387354, 0.761934, 1.510661",\ + "0.025557, 0.151128, 0.387354, 0.761934, 1.510661",\ + "0.025965, 0.151128, 0.387354, 0.761934, 1.511090",\ + "0.029101, 0.151585, 0.387354, 0.761934, 1.511090",\ + "0.041668, 0.154530, 0.388178, 0.761934, 1.511090"); + } + + } /* end of arc clk_ast_ext_i_io_clk_byp_ack_o[2]_redg_min*/ + + timing () { + related_pin : "clk_src_io_o" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.058414, 0.188667, 0.395813, 0.717110, 1.359045",\ + "0.112550, 0.243041, 0.450135, 0.772138, 1.415649",\ + "0.253196, 0.398235, 0.605055, 0.926906, 1.570171",\ + "0.312752, 0.468715, 0.675324, 0.996903, 1.639637",\ + "0.601931, 0.834236, 1.042645, 1.363437, 2.003839"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.021790, 0.238360, 0.631894, 1.247121, 2.477336",\ + "0.023317, 0.238360, 0.631894, 1.247121, 2.477336",\ + "0.044096, 0.241766, 0.631894, 1.247121, 2.477920",\ + "0.055652, 0.245238, 0.631894, 1.247121, 2.478962",\ + "0.123088, 0.289704, 0.642858, 1.251241, 2.479640"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.085404, 0.186224, 0.319679, 0.525413, 0.936188",\ + "0.141978, 0.242754, 0.376239, 0.581985, 0.992777",\ + "0.275783, 0.376576, 0.509868, 0.715539, 1.126231",\ + "0.332511, 0.433991, 0.567236, 0.772791, 1.183241",\ + "0.607343, 0.718683, 0.852150, 1.057410, 1.467133"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.025646, 0.151693, 0.388430, 0.763132, 1.513362",\ + "0.025646, 0.151849, 0.389568, 0.763815, 1.513362",\ + "0.026529, 0.151849, 0.389568, 0.764056, 1.513362",\ + "0.027825, 0.151849, 0.389568, 0.764056, 1.513362",\ + "0.041734, 0.154598, 0.389568, 0.764056, 1.513362"); + } + + } /* end of arc clk_src_io_o_io_clk_byp_ack_o[2]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_src_io_o" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.058410, 0.188665, 0.395812, 0.717100, 1.359014",\ + "0.112399, 0.243028, 0.450025, 0.771635, 1.414310",\ + "0.253195, 0.398233, 0.605040, 0.926895, 1.570171",\ + "0.311693, 0.467461, 0.674069, 0.995655, 1.638404",\ + "0.601899, 0.834203, 1.042596, 1.363402, 2.003839"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.021782, 0.238225, 0.630549, 1.245808, 2.476689",\ + "0.023311, 0.238225, 0.630549, 1.245808, 2.476689",\ + "0.044096, 0.241755, 0.630564, 1.245808, 2.477789",\ + "0.055446, 0.245170, 0.630656, 1.245808, 2.478512",\ + "0.122913, 0.289395, 0.639350, 1.248196, 2.478674"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.085404, 0.186224, 0.319679, 0.525413, 0.936188",\ + "0.141970, 0.242733, 0.376196, 0.581868, 0.992503",\ + "0.275567, 0.376362, 0.509639, 0.715298, 1.125968",\ + "0.331384, 0.432856, 0.566092, 0.771606, 1.181968",\ + "0.607308, 0.718634, 0.852099, 1.057372, 1.467127"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.025646, 0.151208, 0.387784, 0.761934, 1.511090",\ + "0.025646, 0.151208, 0.387784, 0.761934, 1.511090",\ + "0.026523, 0.151208, 0.387784, 0.761934, 1.511090",\ + "0.027795, 0.151394, 0.387784, 0.761934, 1.511090",\ + "0.041668, 0.154530, 0.388178, 0.761934, 1.511090"); + } + + } /* end of arc clk_src_io_o_io_clk_byp_ack_o[2]_redg_min*/ + +} /* end of pin io_clk_byp_ack_o[2] */ + +pin("io_clk_byp_ack_o[1]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.158177 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : io_clk_byp_ack_o[1]; + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.055481, 0.185725, 0.392886, 0.714270, 1.356390",\ + "0.142013, 0.273097, 0.480288, 0.802449, 1.446276",\ + "0.227644, 0.367997, 0.574907, 0.896875, 1.540369",\ + "0.372058, 0.538899, 0.745297, 1.066605, 1.708810",\ + "0.601931, 0.834236, 1.042645, 1.363437, 2.003839"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.021797, 0.238359, 0.631876, 1.247087, 2.477274",\ + "0.025516, 0.238359, 0.631876, 1.247087, 2.477274",\ + "0.039138, 0.240277, 0.631876, 1.247087, 2.477473",\ + "0.067159, 0.248694, 0.631876, 1.247087, 2.479640",\ + "0.123088, 0.289704, 0.642858, 1.251241, 2.479640"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.082179, 0.183018, 0.316461, 0.522191, 0.932963",\ + "0.170164, 0.270956, 0.404436, 0.610175, 1.020954",\ + "0.251445, 0.351944, 0.485256, 0.690977, 1.101771",\ + "0.388999, 0.491163, 0.624361, 0.829801, 1.240010",\ + "0.607343, 0.718683, 0.852150, 1.057410, 1.467133"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.025565, 0.151628, 0.387851, 0.763293, 1.515348",\ + "0.025565, 0.151804, 0.389259, 0.763293, 1.515348",\ + "0.025976, 0.151804, 0.389479, 0.764390, 1.515348",\ + "0.029120, 0.151804, 0.389479, 0.764390, 1.515348",\ + "0.041734, 0.154598, 0.389479, 0.764390, 1.515348"); + } + + } /* end of arc clk_ast_ext_i_io_clk_byp_ack_o[1]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.055478, 0.185724, 0.392885, 0.714263, 1.356368",\ + "0.141644, 0.273073, 0.480017, 0.801359, 1.443459",\ + "0.227644, 0.367995, 0.574890, 0.896861, 1.540369",\ + "0.372055, 0.538895, 0.745296, 1.066605, 1.708810",\ + "0.601899, 0.834203, 1.042596, 1.363402, 2.003839"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.021795, 0.238265, 0.630524, 1.245754, 2.477107",\ + "0.025501, 0.238265, 0.630524, 1.245754, 2.477170",\ + "0.039138, 0.240263, 0.630524, 1.245754, 2.477473",\ + "0.067158, 0.248694, 0.630752, 1.245754, 2.478674",\ + "0.122913, 0.289395, 0.639350, 1.248196, 2.478674"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.082179, 0.183018, 0.316461, 0.522190, 0.932959",\ + "0.170151, 0.270913, 0.404355, 0.610080, 1.020840",\ + "0.251186, 0.351686, 0.484981, 0.690703, 1.101507",\ + "0.388979, 0.491150, 0.624343, 0.829707, 1.239752",\ + "0.607308, 0.718634, 0.852099, 1.057372, 1.467127"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.025557, 0.151128, 0.387354, 0.761934, 1.510661",\ + "0.025557, 0.151128, 0.387354, 0.761934, 1.510661",\ + "0.025965, 0.151128, 0.387354, 0.761934, 1.511090",\ + "0.029101, 0.151585, 0.387354, 0.761934, 1.511090",\ + "0.041668, 0.154530, 0.388178, 0.761934, 1.511090"); + } + + } /* end of arc clk_ast_ext_i_io_clk_byp_ack_o[1]_redg_min*/ + + timing () { + related_pin : "clk_src_io_o" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.058414, 0.188667, 0.395813, 0.717110, 1.359045",\ + "0.112550, 0.243041, 0.450135, 0.772138, 1.415649",\ + "0.253196, 0.398235, 0.605055, 0.926906, 1.570171",\ + "0.312752, 0.468715, 0.675324, 0.996903, 1.639637",\ + "0.601931, 0.834236, 1.042645, 1.363437, 2.003839"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.021790, 0.238360, 0.631894, 1.247121, 2.477336",\ + "0.023317, 0.238360, 0.631894, 1.247121, 2.477336",\ + "0.044096, 0.241766, 0.631894, 1.247121, 2.477920",\ + "0.055652, 0.245238, 0.631894, 1.247121, 2.478962",\ + "0.123088, 0.289704, 0.642858, 1.251241, 2.479640"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.085404, 0.186224, 0.319679, 0.525413, 0.936188",\ + "0.141978, 0.242754, 0.376239, 0.581985, 0.992777",\ + "0.275783, 0.376576, 0.509868, 0.715539, 1.126231",\ + "0.332511, 0.433991, 0.567236, 0.772791, 1.183241",\ + "0.607343, 0.718683, 0.852150, 1.057410, 1.467133"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.025646, 0.151693, 0.388430, 0.763132, 1.513362",\ + "0.025646, 0.151849, 0.389568, 0.763815, 1.513362",\ + "0.026529, 0.151849, 0.389568, 0.764056, 1.513362",\ + "0.027825, 0.151849, 0.389568, 0.764056, 1.513362",\ + "0.041734, 0.154598, 0.389568, 0.764056, 1.513362"); + } + + } /* end of arc clk_src_io_o_io_clk_byp_ack_o[1]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_src_io_o" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.058410, 0.188665, 0.395812, 0.717100, 1.359014",\ + "0.112399, 0.243028, 0.450025, 0.771635, 1.414310",\ + "0.253195, 0.398233, 0.605040, 0.926895, 1.570171",\ + "0.311693, 0.467461, 0.674069, 0.995655, 1.638404",\ + "0.601899, 0.834203, 1.042596, 1.363402, 2.003839"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.021782, 0.238225, 0.630549, 1.245808, 2.476689",\ + "0.023311, 0.238225, 0.630549, 1.245808, 2.476689",\ + "0.044096, 0.241755, 0.630564, 1.245808, 2.477789",\ + "0.055446, 0.245170, 0.630656, 1.245808, 2.478512",\ + "0.122913, 0.289395, 0.639350, 1.248196, 2.478674"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.085404, 0.186224, 0.319679, 0.525413, 0.936188",\ + "0.141970, 0.242733, 0.376196, 0.581868, 0.992503",\ + "0.275567, 0.376362, 0.509639, 0.715298, 1.125968",\ + "0.331384, 0.432856, 0.566092, 0.771606, 1.181968",\ + "0.607308, 0.718634, 0.852099, 1.057372, 1.467127"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.025646, 0.151208, 0.387784, 0.761934, 1.511090",\ + "0.025646, 0.151208, 0.387784, 0.761934, 1.511090",\ + "0.026523, 0.151208, 0.387784, 0.761934, 1.511090",\ + "0.027795, 0.151394, 0.387784, 0.761934, 1.511090",\ + "0.041668, 0.154530, 0.388178, 0.761934, 1.511090"); + } + + } /* end of arc clk_src_io_o_io_clk_byp_ack_o[1]_redg_min*/ + +} /* end of pin io_clk_byp_ack_o[1] */ + +pin("io_clk_byp_ack_o[0]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.161713 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : io_clk_byp_ack_o[0]; + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.100843, 0.266735, 0.427088, 0.747616, 1.388635",\ + "0.184687, 0.350464, 0.510809, 0.831717, 1.473578",\ + "0.260267, 0.426010, 0.586434, 0.907636, 1.550114",\ + "0.386507, 0.552662, 0.713534, 1.034573, 1.676504",\ + "0.580400, 0.747044, 0.907773, 1.228098, 1.868510"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015579, 0.316961, 0.624670, 1.238691, 2.466601",\ + "0.015665, 0.316961, 0.624670, 1.238691, 2.466601",\ + "0.015665, 0.317088, 0.625771, 1.239746, 2.466601",\ + "0.015838, 0.317088, 0.625771, 1.239746, 2.466601",\ + "0.016716, 0.317340, 0.625771, 1.239746, 2.466601"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.088041, 0.202376, 0.303813, 0.506089, 0.910516",\ + "0.168483, 0.282824, 0.383745, 0.585711, 0.989669",\ + "0.247358, 0.362640, 0.463376, 0.664815, 1.067688",\ + "0.380658, 0.500049, 0.601022, 0.802517, 1.205414",\ + "0.586485, 0.719001, 0.819955, 1.021830, 1.425575"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015700, 0.193950, 0.379890, 0.747742, 1.482887",\ + "0.016044, 0.193950, 0.379890, 0.747742, 1.485202",\ + "0.017520, 0.193950, 0.379890, 0.747742, 1.485202",\ + "0.022344, 0.194037, 0.379890, 0.747742, 1.485202",\ + "0.034639, 0.196727, 0.379890, 0.748439, 1.491839"); + } + + } /* end of arc clk_ast_ext_i_io_clk_byp_ack_o[0]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.100718, 0.266618, 0.426903, 0.747412, 1.388420",\ + "0.184686, 0.350463, 0.510806, 0.831715, 1.473578",\ + "0.260208, 0.425985, 0.586426, 0.907607, 1.550030",\ + "0.386259, 0.552119, 0.712336, 1.032993, 1.674352",\ + "0.580173, 0.746795, 0.907585, 1.227594, 1.867283"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015496, 0.316821, 0.622606, 1.236473, 2.462725",\ + "0.015496, 0.316821, 0.622606, 1.236473, 2.462725",\ + "0.015496, 0.316929, 0.622606, 1.236473, 2.462725",\ + "0.015814, 0.316929, 0.622606, 1.236473, 2.462725",\ + "0.016700, 0.316929, 0.623370, 1.236473, 2.462725"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.087868, 0.202376, 0.303809, 0.506029, 0.910334",\ + "0.168483, 0.282824, 0.383745, 0.585711, 0.989669",\ + "0.247358, 0.362640, 0.463376, 0.664779, 1.067573",\ + "0.380658, 0.500049, 0.601022, 0.802517, 1.205414",\ + "0.586485, 0.718955, 0.819794, 1.021516, 1.424967"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015619, 0.192979, 0.376641, 0.744531, 1.480142",\ + "0.016032, 0.192979, 0.376641, 0.744531, 1.480142",\ + "0.017339, 0.192979, 0.376641, 0.744531, 1.480142",\ + "0.022190, 0.193551, 0.376842, 0.744531, 1.480142",\ + "0.033893, 0.196557, 0.377640, 0.746288, 1.484937"); + } + + } /* end of arc clk_ast_ext_i_io_clk_byp_ack_o[0]_redg_min*/ + + timing () { + related_pin : "clk_src_io_o" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.103995, 0.269872, 0.430200, 0.750758, 1.391853",\ + "0.158337, 0.324154, 0.484388, 0.804979, 1.446186",\ + "0.282603, 0.448419, 0.608923, 0.930096, 1.572477",\ + "0.334665, 0.500651, 0.661339, 0.982445, 1.624600",\ + "0.580400, 0.747044, 0.907773, 1.228098, 1.868510"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015542, 0.317035, 0.624600, 1.238588, 2.466325",\ + "0.015645, 0.317035, 0.624600, 1.238588, 2.466325",\ + "0.015645, 0.317066, 0.625211, 1.239292, 2.466325",\ + "0.015655, 0.317066, 0.625211, 1.239292, 2.466325",\ + "0.016716, 0.317340, 0.625211, 1.239292, 2.466325"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.090477, 0.204718, 0.305888, 0.507773, 0.911447",\ + "0.141442, 0.255688, 0.356617, 0.558511, 0.962305",\ + "0.270943, 0.386953, 0.487730, 0.689180, 1.092056",\ + "0.325917, 0.443620, 0.544496, 0.745968, 1.148855",\ + "0.586485, 0.719001, 0.819955, 1.021830, 1.425575"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015734, 0.193610, 0.378735, 0.747021, 1.483183",\ + "0.015916, 0.193610, 0.378735, 0.747293, 1.484513",\ + "0.018374, 0.193610, 0.378735, 0.747293, 1.484513",\ + "0.020363, 0.193614, 0.378735, 0.747293, 1.484513",\ + "0.034639, 0.196727, 0.378735, 0.748439, 1.491839"); + } + + } /* end of arc clk_src_io_o_io_clk_byp_ack_o[0]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_src_io_o" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.103875, 0.269735, 0.430056, 0.750620, 1.391729",\ + "0.158336, 0.324133, 0.484382, 0.804893, 1.445917",\ + "0.282510, 0.448302, 0.608704, 0.929792, 1.572026",\ + "0.333572, 0.499397, 0.659708, 0.980584, 1.622387",\ + "0.580173, 0.746795, 0.907585, 1.227594, 1.867283"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015480, 0.316838, 0.623370, 1.236473, 2.462725",\ + "0.015480, 0.316838, 0.623370, 1.236473, 2.462725",\ + "0.015480, 0.316929, 0.623370, 1.236473, 2.462725",\ + "0.015652, 0.316929, 0.623370, 1.236473, 2.462725",\ + "0.016700, 0.316929, 0.623370, 1.236473, 2.462725"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.090378, 0.204717, 0.305882, 0.507735, 0.911343",\ + "0.141442, 0.255688, 0.356617, 0.558510, 0.962304",\ + "0.270943, 0.386953, 0.487730, 0.689150, 1.091961",\ + "0.324941, 0.442615, 0.543488, 0.744945, 1.147798",\ + "0.586485, 0.718955, 0.819794, 1.021516, 1.424967"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015687, 0.193080, 0.376676, 0.744928, 1.481536",\ + "0.015912, 0.193080, 0.376676, 0.744928, 1.481536",\ + "0.018197, 0.193080, 0.376676, 0.744928, 1.481536",\ + "0.020162, 0.193312, 0.376758, 0.744928, 1.481536",\ + "0.033893, 0.196557, 0.377640, 0.746288, 1.484937"); + } + + } /* end of arc clk_src_io_o_io_clk_byp_ack_o[0]_redg_min*/ + +} /* end of pin io_clk_byp_ack_o[0] */ +} /* end of bus io_clk_byp_ack_o */ +bus ( flash_bist_en_o ) { + + bus_type : BUS4_type6 ; + direction : output ; + +pin("flash_bist_en_o[3]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.161713 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000495 ; + + /* Other user defined attributes. */ + original_pin : flash_bist_en_o[3]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000495, 0.020647, 0.040799, 0.081104, 0.161713"); + values ( "0.106472, 0.270169, 0.430032, 0.749578, 1.388635",\ + "0.190222, 0.353899, 0.513753, 0.833681, 1.473578",\ + "0.265754, 0.429446, 0.589380, 0.909602, 1.550114",\ + "0.318401, 0.482257, 0.642376, 0.962527, 1.602811",\ + "0.586143, 0.750487, 0.910724, 1.230057, 1.868510"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000495, 0.020647, 0.040799, 0.081104, 0.161713"); + values ( "0.022534, 0.323552, 0.630320, 1.242449, 2.466601",\ + "0.022534, 0.323552, 0.630320, 1.242449, 2.466601",\ + "0.022534, 0.323700, 0.631438, 1.243501, 2.466601",\ + "0.022534, 0.323700, 0.631438, 1.243501, 2.466601",\ + "0.023510, 0.323927, 0.631438, 1.243501, 2.466601"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000495, 0.020647, 0.040799, 0.081104, 0.161713"); + values ( "0.093077, 0.204486, 0.305612, 0.507263, 0.910452",\ + "0.173702, 0.284922, 0.385535, 0.586884, 0.989605",\ + "0.252842, 0.364735, 0.465162, 0.665985, 1.067625",\ + "0.308854, 0.422028, 0.522554, 0.723398, 1.125048",\ + "0.595772, 0.721100, 0.821745, 1.023002, 1.425511"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000495, 0.020647, 0.040799, 0.081104, 0.161713"); + values ( "0.020965, 0.197814, 0.383189, 0.749876, 1.482771",\ + "0.021088, 0.197814, 0.383189, 0.749876, 1.485086",\ + "0.022399, 0.197814, 0.383189, 0.749876, 1.485086",\ + "0.024352, 0.197814, 0.383189, 0.749876, 1.485086",\ + "0.039819, 0.200489, 0.383189, 0.750597, 1.491722"); + } + + } /* end of arc clk_ast_tlul_i_flash_bist_en_o[3]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000495, 0.020647, 0.040799, 0.081104, 0.161713"); + values ( "0.106274, 0.270052, 0.429845, 0.749374, 1.388420",\ + "0.190221, 0.353898, 0.513750, 0.833679, 1.473578",\ + "0.265727, 0.429421, 0.589372, 0.909573, 1.550030",\ + "0.318289, 0.482010, 0.641868, 0.961850, 1.601865",\ + "0.585943, 0.750239, 0.910537, 1.229551, 1.867283"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000495, 0.020647, 0.040799, 0.081104, 0.161713"); + values ( "0.022505, 0.323384, 0.628823, 1.240225, 2.462725",\ + "0.022505, 0.323384, 0.628823, 1.240225, 2.462725",\ + "0.022505, 0.323493, 0.628996, 1.240225, 2.462725",\ + "0.022505, 0.323493, 0.628996, 1.240225, 2.462725",\ + "0.023422, 0.323493, 0.628996, 1.240225, 2.462725"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000495, 0.020647, 0.040799, 0.081104, 0.161713"); + values ( "0.093062, 0.204485, 0.305607, 0.507203, 0.910270",\ + "0.173702, 0.284922, 0.385535, 0.586884, 0.989605",\ + "0.252842, 0.364735, 0.465162, 0.665949, 1.067509",\ + "0.308854, 0.422028, 0.522554, 0.723377, 1.124981",\ + "0.595772, 0.721051, 0.821582, 1.022687, 1.424903"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000495, 0.020647, 0.040799, 0.081104, 0.161713"); + values ( "0.020958, 0.196798, 0.379897, 0.747224, 1.481125",\ + "0.021082, 0.196798, 0.379897, 0.747224, 1.481487",\ + "0.022349, 0.196798, 0.379897, 0.747224, 1.481970",\ + "0.024295, 0.197033, 0.379979, 0.747224, 1.481970",\ + "0.039434, 0.200322, 0.380851, 0.748432, 1.484821"); + } + + } /* end of arc clk_ast_tlul_i_flash_bist_en_o[3]_redg_min*/ + +} /* end of pin flash_bist_en_o[3] */ + +pin("flash_bist_en_o[2]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.158177 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000933 ; + + /* Other user defined attributes. */ + original_pin : flash_bist_en_o[2]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000933, 0.015228, 0.040244, 0.079555, 0.158177"); + values ( "0.068360, 0.193376, 0.398624, 0.718055, 1.356390",\ + "0.155472, 0.280749, 0.486028, 0.806244, 1.446276",\ + "0.245378, 0.375639, 0.580639, 0.900669, 1.540369",\ + "0.309418, 0.446887, 0.651675, 0.971433, 1.610599",\ + "0.645820, 0.841934, 1.048418, 1.367213, 2.003839"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000933, 0.015228, 0.040244, 0.079555, 0.158177"); + values ( "0.036908, 0.252893, 0.642777, 1.254340, 2.477274",\ + "0.039249, 0.252893, 0.642777, 1.254340, 2.477274",\ + "0.052853, 0.254696, 0.642777, 1.254340, 2.477473",\ + "0.066089, 0.258077, 0.642777, 1.254340, 2.478527",\ + "0.148778, 0.302748, 0.652641, 1.258483, 2.479640"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000933, 0.015228, 0.040244, 0.079555, 0.158177"); + values ( "0.095441, 0.187812, 0.320023, 0.524480, 0.932830",\ + "0.183363, 0.275751, 0.407999, 0.612464, 1.020822",\ + "0.264739, 0.356733, 0.488814, 0.693266, 1.101639",\ + "0.322419, 0.414777, 0.546811, 0.751146, 1.159276",\ + "0.625473, 0.723477, 0.855712, 1.059693, 1.467001"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000933, 0.015228, 0.040244, 0.079555, 0.158177"); + values ( "0.038391, 0.160114, 0.394156, 0.767483, 1.515105",\ + "0.038391, 0.160334, 0.395597, 0.767483, 1.515105",\ + "0.038391, 0.160334, 0.395837, 0.768571, 1.515105",\ + "0.039404, 0.160334, 0.395837, 0.768571, 1.515105",\ + "0.052962, 0.163010, 0.395837, 0.768571, 1.515105"); + } + + } /* end of arc clk_ast_tlul_i_flash_bist_en_o[2]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000933, 0.015228, 0.040244, 0.079555, 0.158177"); + values ( "0.068360, 0.193375, 0.398624, 0.718048, 1.356368",\ + "0.155472, 0.280716, 0.485750, 0.805145, 1.443459",\ + "0.245377, 0.375636, 0.580621, 0.900655, 1.540369",\ + "0.309416, 0.446884, 0.651665, 0.971425, 1.610599",\ + "0.645736, 0.841900, 1.048369, 1.367178, 2.003839"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000933, 0.015228, 0.040244, 0.079555, 0.158177"); + values ( "0.036903, 0.252768, 0.641334, 1.253096, 2.477107",\ + "0.039197, 0.252768, 0.641334, 1.253096, 2.477170",\ + "0.052850, 0.254678, 0.641334, 1.253096, 2.477473",\ + "0.066086, 0.258066, 0.641335, 1.253096, 2.478218",\ + "0.148778, 0.302321, 0.649044, 1.255451, 2.478674"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000933, 0.015228, 0.040244, 0.079555, 0.158177"); + values ( "0.095441, 0.187812, 0.320023, 0.524479, 0.932827",\ + "0.183333, 0.275707, 0.407917, 0.612369, 1.020708",\ + "0.264498, 0.356474, 0.488538, 0.692993, 1.101375",\ + "0.322270, 0.414621, 0.546643, 0.750947, 1.159015",\ + "0.625416, 0.723429, 0.855662, 1.059656, 1.466994"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000933, 0.015228, 0.040244, 0.079555, 0.158177"); + values ( "0.038382, 0.159650, 0.394147, 0.766109, 1.510420",\ + "0.038382, 0.159650, 0.394269, 0.766109, 1.510420",\ + "0.038382, 0.159650, 0.394269, 0.766109, 1.510848",\ + "0.039368, 0.159819, 0.394269, 0.766109, 1.510848",\ + "0.052940, 0.162923, 0.394414, 0.766109, 1.510848"); + } + + } /* end of arc clk_ast_tlul_i_flash_bist_en_o[2]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.036908, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.389662, 0.307033, 0.231889, 0.198170, 0.165471",\ + "0.404008, 0.321379, 0.246234, 0.212515, 0.179817",\ + "0.484046, 0.401418, 0.326273, 0.292554, 0.259856",\ + "0.581919, 0.499290, 0.424146, 0.390427, 0.357729",\ + "1.023710, 0.941089, 0.865969, 0.832267, 0.799656"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.038391, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.456800, 0.480507, 0.558316, 0.625895, 1.056719",\ + "0.470804, 0.494511, 0.572320, 0.639899, 1.070723",\ + "0.534795, 0.558499, 0.636308, 0.703887, 1.134711",\ + "0.638862, 0.662815, 0.740625, 0.808204, 1.239027",\ + "1.201475, 1.225922, 1.303731, 1.371310, 1.802133"); + } + + } /* end of arc clk_ast_tlul_i_flash_bist_en_o[2]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.036903, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.194420, -0.153007, -0.120290, -0.084607, 0.143547",\ + "-0.208763, -0.167350, -0.134633, -0.098950, 0.129204",\ + "-0.288800, -0.247387, -0.214670, -0.178991, 0.049163",\ + "-0.387771, -0.346358, -0.313641, -0.276864, -0.048710",\ + "-0.830571, -0.789157, -0.756441, -0.718639, -0.490440"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.038382, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.332777, -0.310549, -0.274864, -0.249589, -0.121504",\ + "-0.346777, -0.324549, -0.288864, -0.263590, -0.135504",\ + "-0.410769, -0.388544, -0.352859, -0.327585, -0.199499",\ + "-0.515085, -0.492611, -0.456925, -0.431651, -0.303566",\ + "-1.078191, -1.055218, -1.019535, -0.994261, -0.866175"); + } + + } /* end of arc clk_ast_tlul_i_flash_bist_en_o[2]_hldr*/ + +} /* end of pin flash_bist_en_o[2] */ + +pin("flash_bist_en_o[1]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.158177 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000982 ; + + /* Other user defined attributes. */ + original_pin : flash_bist_en_o[1]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.015278, 0.040281, 0.079579, 0.158177"); + values ( "0.068874, 0.193784, 0.398930, 0.718257, 1.356391",\ + "0.155991, 0.281157, 0.486334, 0.806447, 1.446276",\ + "0.245977, 0.376046, 0.580944, 0.900871, 1.540369",\ + "0.310114, 0.447294, 0.651980, 0.971635, 1.610599",\ + "0.647142, 0.842344, 1.048726, 1.367414, 2.003839"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.015278, 0.040281, 0.079579, 0.158177"); + values ( "0.037694, 0.253668, 0.643358, 1.254727, 2.477274",\ + "0.040003, 0.253668, 0.643358, 1.254727, 2.477274",\ + "0.053519, 0.255465, 0.643358, 1.254727, 2.477474",\ + "0.066746, 0.258839, 0.643358, 1.254727, 2.478527",\ + "0.149647, 0.303443, 0.653162, 1.258869, 2.479640"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.015278, 0.040281, 0.079579, 0.158177"); + values ( "0.095870, 0.188047, 0.320193, 0.524583, 0.932804",\ + "0.183791, 0.275986, 0.408168, 0.612567, 1.020795",\ + "0.265166, 0.356968, 0.488983, 0.693368, 1.101612",\ + "0.322850, 0.415012, 0.546981, 0.751248, 1.159250",\ + "0.625969, 0.723713, 0.855882, 1.059795, 1.466974"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.015278, 0.040281, 0.079579, 0.158177"); + values ( "0.038860, 0.160530, 0.394456, 0.767671, 1.515056",\ + "0.038860, 0.160753, 0.395899, 0.767671, 1.515056",\ + "0.038860, 0.160753, 0.396141, 0.768758, 1.515056",\ + "0.039865, 0.160753, 0.396141, 0.768758, 1.515056",\ + "0.053336, 0.163423, 0.396141, 0.768758, 1.515056"); + } + + } /* end of arc clk_ast_tlul_i_flash_bist_en_o[1]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.015278, 0.040281, 0.079579, 0.158177"); + values ( "0.068873, 0.193783, 0.398930, 0.718250, 1.356368",\ + "0.155991, 0.281124, 0.486056, 0.805347, 1.443459",\ + "0.245976, 0.376044, 0.580926, 0.900857, 1.540369",\ + "0.310112, 0.447291, 0.651970, 0.971627, 1.610599",\ + "0.647058, 0.842310, 1.048677, 1.367379, 2.003839"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.015278, 0.040281, 0.079579, 0.158177"); + values ( "0.037688, 0.253541, 0.641906, 1.253483, 2.477107",\ + "0.039952, 0.253541, 0.641906, 1.253483, 2.477170",\ + "0.053515, 0.255446, 0.641906, 1.253483, 2.477474",\ + "0.066744, 0.258828, 0.641906, 1.253483, 2.478218",\ + "0.149647, 0.303009, 0.649561, 1.255837, 2.478674"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.015278, 0.040281, 0.079579, 0.158177"); + values ( "0.095870, 0.188047, 0.320193, 0.524582, 0.932800",\ + "0.183761, 0.275942, 0.408087, 0.612471, 1.020681",\ + "0.264924, 0.356709, 0.488708, 0.693095, 1.101348",\ + "0.322701, 0.414856, 0.546813, 0.751050, 1.158988",\ + "0.625912, 0.723664, 0.855831, 1.059758, 1.466968"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.015278, 0.040281, 0.079579, 0.158177"); + values ( "0.038851, 0.160069, 0.394447, 0.766295, 1.510371",\ + "0.038851, 0.160069, 0.394570, 0.766295, 1.510371",\ + "0.038851, 0.160069, 0.394570, 0.766295, 1.510800",\ + "0.039829, 0.160236, 0.394570, 0.766295, 1.510800",\ + "0.053313, 0.163335, 0.394711, 0.766295, 1.510800"); + } + + } /* end of arc clk_ast_tlul_i_flash_bist_en_o[1]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.037694, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.387207, 0.304578, 0.229434, 0.195714, 0.163016",\ + "0.401633, 0.319004, 0.243859, 0.210140, 0.177442",\ + "0.477915, 0.395287, 0.320142, 0.286423, 0.253725",\ + "0.569150, 0.486521, 0.411377, 0.377658, 0.344959",\ + "0.968197, 0.885576, 0.810456, 0.776755, 0.744146"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.038860, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.458514, 0.482233, 0.560042, 0.627621, 1.058444",\ + "0.470955, 0.494673, 0.572482, 0.640062, 1.070885",\ + "0.535510, 0.559226, 0.637035, 0.704614, 1.135437",\ + "0.647291, 0.671342, 0.749152, 0.816731, 1.247554",\ + "1.199795, 1.224990, 1.302845, 1.370443, 1.801277"); + } + + } /* end of arc clk_ast_tlul_i_flash_bist_en_o[1]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.037688, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.191963, -0.150550, -0.117833, -0.082151, 0.146002",\ + "-0.206387, -0.164973, -0.132257, -0.096575, 0.131579",\ + "-0.282671, -0.241257, -0.208540, -0.172860, 0.055294",\ + "-0.374978, -0.333564, -0.300848, -0.264095, -0.035941",\ + "-0.775028, -0.733615, -0.700898, -0.663125, -0.434925"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.038851, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.334502, -0.312263, -0.276578, -0.251304, -0.123218",\ + "-0.346939, -0.324701, -0.289015, -0.263741, -0.135656",\ + "-0.411495, -0.389259, -0.353574, -0.328299, -0.200214",\ + "-0.523612, -0.501040, -0.465355, -0.440080, -0.311995",\ + "-1.077244, -1.053536, -1.017853, -0.992580, -0.864493"); + } + + } /* end of arc clk_ast_tlul_i_flash_bist_en_o[1]_hldr*/ + +} /* end of pin flash_bist_en_o[1] */ + +pin("flash_bist_en_o[0]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.161713 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000495 ; + + /* Other user defined attributes. */ + original_pin : flash_bist_en_o[0]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000495, 0.020647, 0.040799, 0.081104, 0.161713"); + values ( "0.106472, 0.270169, 0.430032, 0.749578, 1.388635",\ + "0.190222, 0.353899, 0.513753, 0.833681, 1.473578",\ + "0.265754, 0.429446, 0.589380, 0.909602, 1.550114",\ + "0.318401, 0.482257, 0.642376, 0.962527, 1.602811",\ + "0.586143, 0.750487, 0.910724, 1.230057, 1.868510"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000495, 0.020647, 0.040799, 0.081104, 0.161713"); + values ( "0.022534, 0.323552, 0.630320, 1.242449, 2.466601",\ + "0.022534, 0.323552, 0.630320, 1.242449, 2.466601",\ + "0.022534, 0.323700, 0.631438, 1.243501, 2.466601",\ + "0.022534, 0.323700, 0.631438, 1.243501, 2.466601",\ + "0.023510, 0.323927, 0.631438, 1.243501, 2.466601"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000495, 0.020647, 0.040799, 0.081104, 0.161713"); + values ( "0.093077, 0.204486, 0.305612, 0.507263, 0.910452",\ + "0.173702, 0.284922, 0.385535, 0.586884, 0.989605",\ + "0.252842, 0.364735, 0.465162, 0.665985, 1.067625",\ + "0.308854, 0.422028, 0.522554, 0.723398, 1.125048",\ + "0.595772, 0.721100, 0.821745, 1.023002, 1.425511"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000495, 0.020647, 0.040799, 0.081104, 0.161713"); + values ( "0.020965, 0.197814, 0.383189, 0.749876, 1.482771",\ + "0.021088, 0.197814, 0.383189, 0.749876, 1.485086",\ + "0.022399, 0.197814, 0.383189, 0.749876, 1.485086",\ + "0.024352, 0.197814, 0.383189, 0.749876, 1.485086",\ + "0.039819, 0.200489, 0.383189, 0.750597, 1.491722"); + } + + } /* end of arc clk_ast_tlul_i_flash_bist_en_o[0]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000495, 0.020647, 0.040799, 0.081104, 0.161713"); + values ( "0.106274, 0.270052, 0.429845, 0.749374, 1.388420",\ + "0.190221, 0.353898, 0.513750, 0.833679, 1.473578",\ + "0.265727, 0.429421, 0.589372, 0.909573, 1.550030",\ + "0.318289, 0.482010, 0.641868, 0.961850, 1.601865",\ + "0.585943, 0.750239, 0.910537, 1.229551, 1.867283"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000495, 0.020647, 0.040799, 0.081104, 0.161713"); + values ( "0.022505, 0.323384, 0.628823, 1.240225, 2.462725",\ + "0.022505, 0.323384, 0.628823, 1.240225, 2.462725",\ + "0.022505, 0.323493, 0.628996, 1.240225, 2.462725",\ + "0.022505, 0.323493, 0.628996, 1.240225, 2.462725",\ + "0.023422, 0.323493, 0.628996, 1.240225, 2.462725"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000495, 0.020647, 0.040799, 0.081104, 0.161713"); + values ( "0.093062, 0.204485, 0.305607, 0.507203, 0.910270",\ + "0.173702, 0.284922, 0.385535, 0.586884, 0.989605",\ + "0.252842, 0.364735, 0.465162, 0.665949, 1.067509",\ + "0.308854, 0.422028, 0.522554, 0.723377, 1.124981",\ + "0.595772, 0.721051, 0.821582, 1.022687, 1.424903"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000495, 0.020647, 0.040799, 0.081104, 0.161713"); + values ( "0.020958, 0.196798, 0.379897, 0.747224, 1.481125",\ + "0.021082, 0.196798, 0.379897, 0.747224, 1.481487",\ + "0.022349, 0.196798, 0.379897, 0.747224, 1.481970",\ + "0.024295, 0.197033, 0.379979, 0.747224, 1.481970",\ + "0.039434, 0.200322, 0.380851, 0.748432, 1.484821"); + } + + } /* end of arc clk_ast_tlul_i_flash_bist_en_o[0]_redg_min*/ + +} /* end of pin flash_bist_en_o[0] */ +} /* end of bus flash_bist_en_o */ +bus ( dpram_rmf_o ) { + + bus_type : BUS10_type8 ; + direction : output ; + +pin("dpram_rmf_o[9]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002475 ; + + /* Other user defined attributes. */ + original_pin : dpram_rmf_o[9]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011"); + values ( "0.049435, 0.202151, 0.377283, 0.699803, 1.344843",\ + "0.135820, 0.289326, 0.464387, 0.786517, 1.430777",\ + "0.219334, 0.377453, 0.552342, 0.874138, 1.517732",\ + "0.277559, 0.441846, 0.616457, 0.938052, 1.581241",\ + "0.579442, 0.791721, 0.966837, 1.286790, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011"); + values ( "0.025782, 0.301558, 0.634384, 1.250443, 2.482564",\ + "0.030125, 0.302556, 0.636324, 1.250443, 2.482564",\ + "0.042888, 0.304795, 0.636360, 1.250443, 2.482564",\ + "0.054816, 0.308050, 0.636463, 1.250443, 2.482564",\ + "0.130787, 0.346172, 0.642713, 1.252991, 2.482564"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011"); + values ( "0.068909, 0.173502, 0.284792, 0.488757, 0.896689",\ + "0.156317, 0.260820, 0.372072, 0.576063, 0.984042",\ + "0.236694, 0.341152, 0.452099, 0.656091, 1.064074",\ + "0.293432, 0.398701, 0.509642, 0.713335, 1.120722",\ + "0.587713, 0.702042, 0.813273, 1.016348, 1.422499"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011"); + values ( "0.025687, 0.188435, 0.388543, 0.760465, 1.504307",\ + "0.025687, 0.188583, 0.389046, 0.760465, 1.504307",\ + "0.026721, 0.188583, 0.389046, 0.760465, 1.504307",\ + "0.028743, 0.188583, 0.389046, 0.760465, 1.504307",\ + "0.047139, 0.192514, 0.389046, 0.760465, 1.504587"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[9]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011"); + values ( "0.049435, 0.202151, 0.377283, 0.699803, 1.344843",\ + "0.135820, 0.289326, 0.464387, 0.786517, 1.430777",\ + "0.219334, 0.377453, 0.552342, 0.874138, 1.517732",\ + "0.277559, 0.441846, 0.616457, 0.938052, 1.581241",\ + "0.579442, 0.791721, 0.966837, 1.286790, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011"); + values ( "0.025782, 0.301558, 0.634384, 1.249210, 2.473548",\ + "0.030125, 0.302556, 0.636324, 1.249210, 2.473548",\ + "0.042888, 0.304795, 0.636360, 1.249285, 2.473548",\ + "0.054816, 0.308050, 0.636463, 1.250030, 2.473548",\ + "0.130787, 0.346172, 0.642713, 1.252991, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011"); + values ( "0.068909, 0.173502, 0.284792, 0.488757, 0.896689",\ + "0.156317, 0.260820, 0.372072, 0.576063, 0.984042",\ + "0.236694, 0.341152, 0.452099, 0.656091, 1.064074",\ + "0.293432, 0.398701, 0.509642, 0.713335, 1.120722",\ + "0.587713, 0.702042, 0.813273, 1.016348, 1.422499"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011"); + values ( "0.025687, 0.187631, 0.387035, 0.758233, 1.500630",\ + "0.025687, 0.187631, 0.387035, 0.758233, 1.500630",\ + "0.026721, 0.187631, 0.387035, 0.758233, 1.500630",\ + "0.028743, 0.188240, 0.387493, 0.759136, 1.502422",\ + "0.047139, 0.192514, 0.387566, 0.759907, 1.504587"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[9]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025782, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.216765, 0.170836, 0.140637, 0.129293, 0.142978",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025687, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.251111, 0.175790, 0.107631, 0.084664, 0.147578",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[9]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025782, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.148693, -0.106276, -0.071789, -0.032365, 0.273682",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025687, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.164267, -0.098352, -0.040693, 0.001268, 0.221876",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[9]_hldr*/ + +} /* end of pin dpram_rmf_o[9] */ + +pin("dpram_rmf_o[8]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002026 ; + + /* Other user defined attributes. */ + original_pin : dpram_rmf_o[8]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011"); + values ( "0.048221, 0.201247, 0.376603, 0.699350, 1.344843",\ + "0.134540, 0.288422, 0.463709, 0.786065, 1.430777",\ + "0.217754, 0.376549, 0.551664, 0.873687, 1.517732",\ + "0.275678, 0.440944, 0.615780, 0.937600, 1.581241",\ + "0.575742, 0.790814, 0.966163, 1.286341, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011"); + values ( "0.024153, 0.299842, 0.633087, 1.249579, 2.482563",\ + "0.028666, 0.300830, 0.635034, 1.249579, 2.482563",\ + "0.041608, 0.303085, 0.635070, 1.249579, 2.482563",\ + "0.053514, 0.306363, 0.635172, 1.249579, 2.482563",\ + "0.129154, 0.344706, 0.641428, 1.252134, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011"); + values ( "0.067848, 0.172946, 0.284382, 0.488491, 0.896709",\ + "0.155259, 0.260265, 0.371663, 0.575796, 0.984062",\ + "0.235619, 0.340599, 0.451690, 0.655824, 1.064094",\ + "0.292315, 0.398147, 0.509233, 0.713069, 1.120741",\ + "0.586152, 0.701486, 0.812865, 1.016083, 1.422518"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011"); + values ( "0.024592, 0.187440, 0.387796, 0.759979, 1.504343",\ + "0.024592, 0.187585, 0.388300, 0.759979, 1.504343",\ + "0.025674, 0.187585, 0.388300, 0.759979, 1.504343",\ + "0.027742, 0.187585, 0.388300, 0.759979, 1.504343",\ + "0.046348, 0.191554, 0.388300, 0.759979, 1.504623"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[8]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011"); + values ( "0.048221, 0.201247, 0.376603, 0.699350, 1.344843",\ + "0.134540, 0.288422, 0.463709, 0.786065, 1.430777",\ + "0.217754, 0.376549, 0.551664, 0.873687, 1.517732",\ + "0.275678, 0.440944, 0.615780, 0.937600, 1.581241",\ + "0.575742, 0.790814, 0.966163, 1.286341, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011"); + values ( "0.024153, 0.299842, 0.633087, 1.248350, 2.473548",\ + "0.028666, 0.300830, 0.635034, 1.248350, 2.473548",\ + "0.041608, 0.303085, 0.635070, 1.248425, 2.473548",\ + "0.053514, 0.306363, 0.635172, 1.249169, 2.473548",\ + "0.129154, 0.344706, 0.641428, 1.252134, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011"); + values ( "0.067848, 0.172946, 0.284382, 0.488491, 0.896709",\ + "0.155259, 0.260265, 0.371663, 0.575796, 0.984062",\ + "0.235619, 0.340599, 0.451690, 0.655824, 1.064094",\ + "0.292315, 0.398147, 0.509233, 0.713069, 1.120741",\ + "0.586152, 0.701486, 0.812865, 1.016083, 1.422518"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011"); + values ( "0.024592, 0.186641, 0.386289, 0.757748, 1.500666",\ + "0.024592, 0.186641, 0.386289, 0.757748, 1.500666",\ + "0.025674, 0.186641, 0.386289, 0.757748, 1.500666",\ + "0.027742, 0.187251, 0.386746, 0.758650, 1.502457",\ + "0.046348, 0.191554, 0.386818, 0.759420, 1.504623"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[8]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.216011, 0.170082, 0.139882, 0.128539, 0.142224",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024592, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.250613, 0.175291, 0.107132, 0.084165, 0.147079",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[8]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.147938, -0.105521, -0.071034, -0.031611, 0.274436",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024592, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.163769, -0.097854, -0.040195, 0.001766, 0.222374",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[8]_hldr*/ + +} /* end of pin dpram_rmf_o[8] */ + +pin("dpram_rmf_o[7]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002475 ; + + /* Other user defined attributes. */ + original_pin : dpram_rmf_o[7]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011"); + values ( "0.049435, 0.202151, 0.377283, 0.699803, 1.344843",\ + "0.135820, 0.289326, 0.464387, 0.786517, 1.430777",\ + "0.219334, 0.377453, 0.552342, 0.874138, 1.517732",\ + "0.277559, 0.441846, 0.616457, 0.938052, 1.581241",\ + "0.579442, 0.791721, 0.966837, 1.286790, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011"); + values ( "0.025782, 0.301558, 0.634384, 1.250443, 2.482564",\ + "0.030125, 0.302556, 0.636324, 1.250443, 2.482564",\ + "0.042888, 0.304795, 0.636360, 1.250443, 2.482564",\ + "0.054816, 0.308050, 0.636463, 1.250443, 2.482564",\ + "0.130787, 0.346172, 0.642713, 1.252991, 2.482564"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011"); + values ( "0.068909, 0.173502, 0.284792, 0.488757, 0.896689",\ + "0.156317, 0.260820, 0.372072, 0.576063, 0.984042",\ + "0.236694, 0.341152, 0.452099, 0.656091, 1.064074",\ + "0.293432, 0.398701, 0.509642, 0.713335, 1.120722",\ + "0.587713, 0.702042, 0.813273, 1.016348, 1.422499"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011"); + values ( "0.025687, 0.188435, 0.388543, 0.760465, 1.504307",\ + "0.025687, 0.188583, 0.389046, 0.760465, 1.504307",\ + "0.026721, 0.188583, 0.389046, 0.760465, 1.504307",\ + "0.028743, 0.188583, 0.389046, 0.760465, 1.504307",\ + "0.047139, 0.192514, 0.389046, 0.760465, 1.504587"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[7]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011"); + values ( "0.049435, 0.202151, 0.377283, 0.699803, 1.344843",\ + "0.135820, 0.289326, 0.464387, 0.786517, 1.430777",\ + "0.219334, 0.377453, 0.552342, 0.874138, 1.517732",\ + "0.277559, 0.441846, 0.616457, 0.938052, 1.581241",\ + "0.579442, 0.791721, 0.966837, 1.286790, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011"); + values ( "0.025782, 0.301558, 0.634384, 1.249210, 2.473548",\ + "0.030125, 0.302556, 0.636324, 1.249210, 2.473548",\ + "0.042888, 0.304795, 0.636360, 1.249285, 2.473548",\ + "0.054816, 0.308050, 0.636463, 1.250030, 2.473548",\ + "0.130787, 0.346172, 0.642713, 1.252991, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011"); + values ( "0.068909, 0.173502, 0.284792, 0.488757, 0.896689",\ + "0.156317, 0.260820, 0.372072, 0.576063, 0.984042",\ + "0.236694, 0.341152, 0.452099, 0.656091, 1.064074",\ + "0.293432, 0.398701, 0.509642, 0.713335, 1.120722",\ + "0.587713, 0.702042, 0.813273, 1.016348, 1.422499"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011"); + values ( "0.025687, 0.187631, 0.387035, 0.758233, 1.500630",\ + "0.025687, 0.187631, 0.387035, 0.758233, 1.500630",\ + "0.026721, 0.187631, 0.387035, 0.758233, 1.500630",\ + "0.028743, 0.188240, 0.387493, 0.759136, 1.502422",\ + "0.047139, 0.192514, 0.387566, 0.759907, 1.504587"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[7]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025782, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.216765, 0.170836, 0.140637, 0.129293, 0.142978",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025687, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.251111, 0.175790, 0.107631, 0.084664, 0.147578",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[7]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025782, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.148693, -0.106276, -0.071789, -0.032365, 0.273682",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025687, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.164267, -0.098352, -0.040693, 0.001268, 0.221876",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[7]_hldr*/ + +} /* end of pin dpram_rmf_o[7] */ + +pin("dpram_rmf_o[6]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002493 ; + + /* Other user defined attributes. */ + original_pin : dpram_rmf_o[6]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002493, 0.075491, 0.162372, 0.322252, 0.642011"); + values ( "0.049484, 0.202188, 0.377310, 0.699821, 1.344843",\ + "0.135872, 0.289362, 0.464414, 0.786535, 1.430777",\ + "0.219397, 0.377489, 0.552369, 0.874157, 1.517732",\ + "0.277634, 0.441882, 0.616484, 0.938070, 1.581241",\ + "0.579590, 0.791757, 0.966864, 1.286808, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002493, 0.075491, 0.162372, 0.322252, 0.642011"); + values ( "0.025847, 0.301627, 0.634436, 1.250478, 2.482563",\ + "0.030184, 0.302625, 0.636376, 1.250478, 2.482563",\ + "0.042939, 0.304864, 0.636412, 1.250478, 2.482563",\ + "0.054868, 0.308118, 0.636515, 1.250478, 2.482563",\ + "0.130853, 0.346231, 0.642764, 1.253025, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002493, 0.075491, 0.162372, 0.322252, 0.642011"); + values ( "0.068955, 0.173526, 0.284810, 0.488770, 0.896690",\ + "0.156363, 0.260844, 0.372091, 0.576075, 0.984043",\ + "0.236740, 0.341176, 0.452118, 0.656103, 1.064075",\ + "0.293480, 0.398725, 0.509660, 0.713348, 1.120723",\ + "0.587780, 0.702066, 0.813291, 1.016361, 1.422500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002493, 0.075491, 0.162372, 0.322252, 0.642011"); + values ( "0.025734, 0.188477, 0.388576, 0.760487, 1.504309",\ + "0.025734, 0.188626, 0.389079, 0.760487, 1.504309",\ + "0.026766, 0.188626, 0.389079, 0.760487, 1.504309",\ + "0.028786, 0.188626, 0.389079, 0.760487, 1.504309",\ + "0.047173, 0.192555, 0.389079, 0.760487, 1.504589"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[6]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002493, 0.075491, 0.162372, 0.322252, 0.642011"); + values ( "0.049484, 0.202188, 0.377310, 0.699821, 1.344843",\ + "0.135872, 0.289362, 0.464414, 0.786535, 1.430777",\ + "0.219397, 0.377489, 0.552369, 0.874157, 1.517732",\ + "0.277634, 0.441882, 0.616484, 0.938070, 1.581241",\ + "0.579590, 0.791757, 0.966864, 1.286808, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002493, 0.075491, 0.162372, 0.322252, 0.642011"); + values ( "0.025847, 0.301627, 0.634436, 1.249244, 2.473548",\ + "0.030184, 0.302625, 0.636376, 1.249244, 2.473548",\ + "0.042939, 0.304864, 0.636412, 1.249320, 2.473548",\ + "0.054868, 0.308118, 0.636515, 1.250065, 2.473548",\ + "0.130853, 0.346231, 0.642764, 1.253025, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002493, 0.075491, 0.162372, 0.322252, 0.642011"); + values ( "0.068955, 0.173526, 0.284810, 0.488770, 0.896690",\ + "0.156363, 0.260844, 0.372091, 0.576075, 0.984043",\ + "0.236740, 0.341176, 0.452118, 0.656103, 1.064075",\ + "0.293480, 0.398725, 0.509660, 0.713348, 1.120723",\ + "0.587780, 0.702066, 0.813291, 1.016361, 1.422500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002493, 0.075491, 0.162372, 0.322252, 0.642011"); + values ( "0.025734, 0.187674, 0.387068, 0.758256, 1.500632",\ + "0.025734, 0.187674, 0.387068, 0.758256, 1.500632",\ + "0.026766, 0.187674, 0.387068, 0.758256, 1.500632",\ + "0.028786, 0.188283, 0.387526, 0.759158, 1.502423",\ + "0.047173, 0.192555, 0.387599, 0.759929, 1.504589"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[6]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025847, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.216796, 0.170867, 0.140667, 0.129323, 0.143008",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025734, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.251133, 0.175811, 0.107652, 0.084685, 0.147599",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[6]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025847, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.148723, -0.106306, -0.071819, -0.032395, 0.273652",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025734, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.164288, -0.098373, -0.040714, 0.001247, 0.221854",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[6]_hldr*/ + +} /* end of pin dpram_rmf_o[6] */ + +pin("dpram_rmf_o[5]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002464 ; + + /* Other user defined attributes. */ + original_pin : dpram_rmf_o[5]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002464, 0.075463, 0.162351, 0.322237, 0.642011"); + values ( "0.049406, 0.202130, 0.377266, 0.699792, 1.344843",\ + "0.135790, 0.289304, 0.464371, 0.786506, 1.430777",\ + "0.219296, 0.377431, 0.552325, 0.874128, 1.517732",\ + "0.277514, 0.441824, 0.616441, 0.938041, 1.581241",\ + "0.579353, 0.791699, 0.966821, 1.286780, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002464, 0.075463, 0.162351, 0.322237, 0.642011"); + values ( "0.025743, 0.301517, 0.634353, 1.250423, 2.482564",\ + "0.030090, 0.302515, 0.636293, 1.250423, 2.482564",\ + "0.042857, 0.304754, 0.636329, 1.250423, 2.482564",\ + "0.054785, 0.308010, 0.636433, 1.250423, 2.482564",\ + "0.130748, 0.346137, 0.642682, 1.252970, 2.482564"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002464, 0.075463, 0.162351, 0.322237, 0.642011"); + values ( "0.068893, 0.173494, 0.284787, 0.488756, 0.896694",\ + "0.156301, 0.260812, 0.372068, 0.576061, 0.984048",\ + "0.236678, 0.341144, 0.452094, 0.656090, 1.064079",\ + "0.293415, 0.398693, 0.509637, 0.713334, 1.120727",\ + "0.587689, 0.702034, 0.813268, 1.016347, 1.422504"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002464, 0.075463, 0.162351, 0.322237, 0.642011"); + values ( "0.025670, 0.188420, 0.388534, 0.760462, 1.504317",\ + "0.025670, 0.188568, 0.389037, 0.760462, 1.504317",\ + "0.026706, 0.188568, 0.389037, 0.760462, 1.504317",\ + "0.028728, 0.188568, 0.389037, 0.760462, 1.504317",\ + "0.047127, 0.192499, 0.389037, 0.760462, 1.504597"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[5]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002464, 0.075463, 0.162351, 0.322237, 0.642011"); + values ( "0.049406, 0.202130, 0.377266, 0.699792, 1.344843",\ + "0.135790, 0.289304, 0.464371, 0.786506, 1.430777",\ + "0.219296, 0.377431, 0.552325, 0.874128, 1.517732",\ + "0.277514, 0.441824, 0.616441, 0.938041, 1.581241",\ + "0.579353, 0.791699, 0.966821, 1.286780, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002464, 0.075463, 0.162351, 0.322237, 0.642011"); + values ( "0.025743, 0.301517, 0.634353, 1.249189, 2.473548",\ + "0.030090, 0.302515, 0.636293, 1.249189, 2.473548",\ + "0.042857, 0.304754, 0.636329, 1.249264, 2.473548",\ + "0.054785, 0.308010, 0.636433, 1.250010, 2.473548",\ + "0.130748, 0.346137, 0.642682, 1.252970, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002464, 0.075463, 0.162351, 0.322237, 0.642011"); + values ( "0.068893, 0.173494, 0.284787, 0.488756, 0.896694",\ + "0.156301, 0.260812, 0.372068, 0.576061, 0.984048",\ + "0.236678, 0.341144, 0.452094, 0.656090, 1.064079",\ + "0.293415, 0.398693, 0.509637, 0.713334, 1.120727",\ + "0.587689, 0.702034, 0.813268, 1.016347, 1.422504"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002464, 0.075463, 0.162351, 0.322237, 0.642011"); + values ( "0.025670, 0.187616, 0.387026, 0.758231, 1.500640",\ + "0.025670, 0.187616, 0.387026, 0.758231, 1.500640",\ + "0.026706, 0.187616, 0.387026, 0.758231, 1.500640",\ + "0.028728, 0.188225, 0.387484, 0.759133, 1.502431",\ + "0.047127, 0.192499, 0.387557, 0.759904, 1.504597"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[5]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025743, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.216747, 0.170818, 0.140619, 0.129275, 0.142960",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025670, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.251104, 0.175782, 0.107623, 0.084656, 0.147570",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[5]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025743, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.148675, -0.106258, -0.071771, -0.032347, 0.273700",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025670, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.164259, -0.098344, -0.040686, 0.001276, 0.221883",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[5]_hldr*/ + +} /* end of pin dpram_rmf_o[5] */ + +pin("dpram_rmf_o[4]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002015 ; + + /* Other user defined attributes. */ + original_pin : dpram_rmf_o[4]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011"); + values ( "0.048192, 0.201225, 0.376587, 0.699339, 1.344843",\ + "0.134509, 0.288400, 0.463692, 0.786054, 1.430777",\ + "0.217716, 0.376528, 0.551648, 0.873676, 1.517732",\ + "0.275633, 0.440922, 0.615763, 0.937589, 1.581241",\ + "0.575653, 0.790792, 0.966147, 1.286330, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011"); + values ( "0.024114, 0.299801, 0.633056, 1.249558, 2.482564",\ + "0.028631, 0.300789, 0.635003, 1.249558, 2.482564",\ + "0.041577, 0.303044, 0.635039, 1.249558, 2.482564",\ + "0.053483, 0.306322, 0.635141, 1.249558, 2.482564",\ + "0.129115, 0.344671, 0.641397, 1.252114, 2.482564"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011"); + values ( "0.067832, 0.172938, 0.284377, 0.488489, 0.896714",\ + "0.155243, 0.260256, 0.371658, 0.575794, 0.984068",\ + "0.235603, 0.340590, 0.451685, 0.655823, 1.064099",\ + "0.292298, 0.398139, 0.509228, 0.713068, 1.120747",\ + "0.586128, 0.701477, 0.812860, 1.016081, 1.422524"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011"); + values ( "0.024575, 0.187425, 0.387787, 0.759976, 1.504353",\ + "0.024575, 0.187570, 0.388291, 0.759976, 1.504353",\ + "0.025658, 0.187570, 0.388291, 0.759976, 1.504353",\ + "0.027727, 0.187570, 0.388291, 0.759976, 1.504353",\ + "0.046336, 0.191539, 0.388291, 0.759976, 1.504633"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[4]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011"); + values ( "0.048192, 0.201225, 0.376587, 0.699339, 1.344843",\ + "0.134509, 0.288400, 0.463692, 0.786054, 1.430777",\ + "0.217716, 0.376528, 0.551648, 0.873676, 1.517732",\ + "0.275633, 0.440922, 0.615763, 0.937589, 1.581241",\ + "0.575653, 0.790792, 0.966147, 1.286330, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011"); + values ( "0.024114, 0.299801, 0.633056, 1.248329, 2.473548",\ + "0.028631, 0.300789, 0.635003, 1.248329, 2.473548",\ + "0.041577, 0.303044, 0.635039, 1.248404, 2.473548",\ + "0.053483, 0.306322, 0.635141, 1.249148, 2.473548",\ + "0.129115, 0.344671, 0.641397, 1.252114, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011"); + values ( "0.067832, 0.172938, 0.284377, 0.488489, 0.896714",\ + "0.155243, 0.260256, 0.371658, 0.575794, 0.984068",\ + "0.235603, 0.340590, 0.451685, 0.655823, 1.064099",\ + "0.292298, 0.398139, 0.509228, 0.713068, 1.120747",\ + "0.586128, 0.701477, 0.812860, 1.016081, 1.422524"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011"); + values ( "0.024575, 0.186626, 0.386280, 0.757745, 1.500676",\ + "0.024575, 0.186626, 0.386280, 0.757745, 1.500676",\ + "0.025658, 0.186626, 0.386280, 0.757745, 1.500676",\ + "0.027727, 0.187236, 0.386737, 0.758647, 1.502467",\ + "0.046336, 0.191539, 0.386809, 0.759417, 1.504633"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[4]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024114, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.215993, 0.170064, 0.139864, 0.128520, 0.142206",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024575, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.250605, 0.175284, 0.107125, 0.084158, 0.147071",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[4]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024114, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.147920, -0.105503, -0.071016, -0.031593, 0.274454",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024575, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.163761, -0.097846, -0.040187, 0.001774, 0.222382",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[4]_hldr*/ + +} /* end of pin dpram_rmf_o[4] */ + +pin("dpram_rmf_o[3]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002005 ; + + /* Other user defined attributes. */ + original_pin : dpram_rmf_o[3]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011"); + values ( "0.048165, 0.201205, 0.376572, 0.699329, 1.344843",\ + "0.134480, 0.288380, 0.463677, 0.786044, 1.430777",\ + "0.217680, 0.376507, 0.551633, 0.873666, 1.517732",\ + "0.275590, 0.440902, 0.615748, 0.937579, 1.581241",\ + "0.575569, 0.790772, 0.966132, 1.286320, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011"); + values ( "0.024077, 0.299762, 0.633026, 1.249539, 2.482564",\ + "0.028598, 0.300750, 0.634974, 1.249539, 2.482564",\ + "0.041548, 0.303005, 0.635010, 1.249539, 2.482564",\ + "0.053453, 0.306284, 0.635112, 1.249539, 2.482564",\ + "0.129078, 0.344637, 0.641368, 1.252094, 2.482564"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011"); + values ( "0.067810, 0.172926, 0.284369, 0.488484, 0.896715",\ + "0.155221, 0.260244, 0.371649, 0.575789, 0.984069",\ + "0.235580, 0.340579, 0.451676, 0.655818, 1.064101",\ + "0.292274, 0.398127, 0.509219, 0.713062, 1.120748",\ + "0.586096, 0.701465, 0.812852, 1.016076, 1.422525"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011"); + values ( "0.024552, 0.187404, 0.387772, 0.759966, 1.504356",\ + "0.024552, 0.187549, 0.388276, 0.759966, 1.504356",\ + "0.025636, 0.187549, 0.388276, 0.759966, 1.504356",\ + "0.027706, 0.187549, 0.388276, 0.759966, 1.504356",\ + "0.046319, 0.191519, 0.388276, 0.759966, 1.504636"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[3]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011"); + values ( "0.048165, 0.201205, 0.376572, 0.699329, 1.344843",\ + "0.134480, 0.288380, 0.463677, 0.786044, 1.430777",\ + "0.217680, 0.376507, 0.551633, 0.873666, 1.517732",\ + "0.275590, 0.440902, 0.615748, 0.937579, 1.581241",\ + "0.575569, 0.790772, 0.966132, 1.286320, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011"); + values ( "0.024077, 0.299762, 0.633026, 1.248310, 2.473548",\ + "0.028598, 0.300750, 0.634974, 1.248310, 2.473548",\ + "0.041548, 0.303005, 0.635010, 1.248385, 2.473548",\ + "0.053453, 0.306284, 0.635112, 1.249129, 2.473548",\ + "0.129078, 0.344637, 0.641368, 1.252094, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011"); + values ( "0.067810, 0.172926, 0.284369, 0.488484, 0.896715",\ + "0.155221, 0.260244, 0.371649, 0.575789, 0.984069",\ + "0.235580, 0.340579, 0.451676, 0.655818, 1.064101",\ + "0.292274, 0.398127, 0.509219, 0.713062, 1.120748",\ + "0.586096, 0.701465, 0.812852, 1.016076, 1.422525"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011"); + values ( "0.024552, 0.186605, 0.386265, 0.757736, 1.500678",\ + "0.024552, 0.186605, 0.386265, 0.757736, 1.500678",\ + "0.025636, 0.186605, 0.386265, 0.757736, 1.500678",\ + "0.027706, 0.187215, 0.386722, 0.758638, 1.502470",\ + "0.046319, 0.191519, 0.386794, 0.759408, 1.504636"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[3]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024077, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.215976, 0.170047, 0.139847, 0.128503, 0.142188",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024552, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.250595, 0.175273, 0.107114, 0.084147, 0.147061",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[3]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024077, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.147903, -0.105486, -0.070999, -0.031576, 0.274471",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024552, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.163751, -0.097835, -0.040177, 0.001784, 0.222392",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[3]_hldr*/ + +} /* end of pin dpram_rmf_o[3] */ + +pin("dpram_rmf_o[2]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002015 ; + + /* Other user defined attributes. */ + original_pin : dpram_rmf_o[2]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011"); + values ( "0.048192, 0.201225, 0.376587, 0.699339, 1.344843",\ + "0.134509, 0.288400, 0.463692, 0.786054, 1.430777",\ + "0.217716, 0.376528, 0.551648, 0.873676, 1.517732",\ + "0.275633, 0.440922, 0.615763, 0.937589, 1.581241",\ + "0.575653, 0.790792, 0.966147, 1.286330, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011"); + values ( "0.024114, 0.299801, 0.633056, 1.249558, 2.482564",\ + "0.028631, 0.300789, 0.635003, 1.249558, 2.482564",\ + "0.041577, 0.303044, 0.635039, 1.249558, 2.482564",\ + "0.053483, 0.306322, 0.635141, 1.249558, 2.482564",\ + "0.129115, 0.344671, 0.641397, 1.252114, 2.482564"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011"); + values ( "0.067832, 0.172938, 0.284377, 0.488489, 0.896714",\ + "0.155243, 0.260256, 0.371658, 0.575794, 0.984068",\ + "0.235603, 0.340590, 0.451685, 0.655823, 1.064099",\ + "0.292298, 0.398139, 0.509228, 0.713068, 1.120747",\ + "0.586128, 0.701477, 0.812860, 1.016081, 1.422524"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011"); + values ( "0.024575, 0.187425, 0.387787, 0.759976, 1.504353",\ + "0.024575, 0.187570, 0.388291, 0.759976, 1.504353",\ + "0.025658, 0.187570, 0.388291, 0.759976, 1.504353",\ + "0.027727, 0.187570, 0.388291, 0.759976, 1.504353",\ + "0.046336, 0.191539, 0.388291, 0.759976, 1.504633"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[2]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011"); + values ( "0.048192, 0.201225, 0.376587, 0.699339, 1.344843",\ + "0.134509, 0.288400, 0.463692, 0.786054, 1.430777",\ + "0.217716, 0.376528, 0.551648, 0.873676, 1.517732",\ + "0.275633, 0.440922, 0.615763, 0.937589, 1.581241",\ + "0.575653, 0.790792, 0.966147, 1.286330, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011"); + values ( "0.024114, 0.299801, 0.633056, 1.248329, 2.473548",\ + "0.028631, 0.300789, 0.635003, 1.248329, 2.473548",\ + "0.041577, 0.303044, 0.635039, 1.248404, 2.473548",\ + "0.053483, 0.306322, 0.635141, 1.249148, 2.473548",\ + "0.129115, 0.344671, 0.641397, 1.252114, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011"); + values ( "0.067832, 0.172938, 0.284377, 0.488489, 0.896714",\ + "0.155243, 0.260256, 0.371658, 0.575794, 0.984068",\ + "0.235603, 0.340590, 0.451685, 0.655823, 1.064099",\ + "0.292298, 0.398139, 0.509228, 0.713068, 1.120747",\ + "0.586128, 0.701477, 0.812860, 1.016081, 1.422524"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011"); + values ( "0.024575, 0.186626, 0.386280, 0.757745, 1.500676",\ + "0.024575, 0.186626, 0.386280, 0.757745, 1.500676",\ + "0.025658, 0.186626, 0.386280, 0.757745, 1.500676",\ + "0.027727, 0.187236, 0.386737, 0.758647, 1.502467",\ + "0.046336, 0.191539, 0.386809, 0.759417, 1.504633"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[2]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024114, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.215993, 0.170064, 0.139864, 0.128520, 0.142206",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024575, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.250605, 0.175284, 0.107125, 0.084158, 0.147071",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[2]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024114, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.147920, -0.105503, -0.071016, -0.031593, 0.274454",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024575, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.163761, -0.097846, -0.040187, 0.001774, 0.222382",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[2]_hldr*/ + +} /* end of pin dpram_rmf_o[2] */ + +pin("dpram_rmf_o[1]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.003002 ; + + /* Other user defined attributes. */ + original_pin : dpram_rmf_o[1]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011"); + values ( "0.050861, 0.203214, 0.378080, 0.700335, 1.344843",\ + "0.137325, 0.290388, 0.465183, 0.787048, 1.430777",\ + "0.221189, 0.378514, 0.553137, 0.874669, 1.517732",\ + "0.279768, 0.442905, 0.617252, 0.938582, 1.581241",\ + "0.583788, 0.792786, 0.967628, 1.287318, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011"); + values ( "0.027696, 0.303573, 0.635907, 1.251459, 2.482564",\ + "0.031840, 0.304583, 0.637840, 1.251459, 2.482564",\ + "0.044392, 0.306804, 0.637876, 1.251459, 2.482564",\ + "0.056346, 0.310032, 0.637981, 1.251459, 2.482564",\ + "0.132705, 0.347895, 0.644222, 1.253997, 2.482564"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011"); + values ( "0.070172, 0.174163, 0.285281, 0.489079, 0.896674",\ + "0.157576, 0.261481, 0.372562, 0.576384, 0.984028",\ + "0.237972, 0.341811, 0.452589, 0.656412, 1.064059",\ + "0.294761, 0.399360, 0.510131, 0.713656, 1.120707",\ + "0.589569, 0.702704, 0.813760, 1.016668, 1.422484"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011"); + values ( "0.026989, 0.189618, 0.389436, 0.761051, 1.504280",\ + "0.026989, 0.189769, 0.389937, 0.761051, 1.504280",\ + "0.027967, 0.189769, 0.389937, 0.761051, 1.504280",\ + "0.029933, 0.189769, 0.389937, 0.761051, 1.504280",\ + "0.048080, 0.193656, 0.389937, 0.761051, 1.504560"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[1]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011"); + values ( "0.050861, 0.203214, 0.378080, 0.700335, 1.344843",\ + "0.137325, 0.290388, 0.465183, 0.787048, 1.430777",\ + "0.221189, 0.378514, 0.553137, 0.874669, 1.517732",\ + "0.279768, 0.442905, 0.617252, 0.938582, 1.581241",\ + "0.583788, 0.792786, 0.967628, 1.287318, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011"); + values ( "0.027696, 0.303573, 0.635907, 1.250220, 2.473548",\ + "0.031840, 0.304583, 0.637840, 1.250220, 2.473548",\ + "0.044392, 0.306804, 0.637876, 1.250296, 2.473548",\ + "0.056346, 0.310032, 0.637981, 1.251042, 2.473548",\ + "0.132705, 0.347895, 0.644222, 1.253997, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011"); + values ( "0.070172, 0.174163, 0.285281, 0.489079, 0.896674",\ + "0.157576, 0.261481, 0.372562, 0.576384, 0.984028",\ + "0.237972, 0.341811, 0.452589, 0.656412, 1.064059",\ + "0.294761, 0.399360, 0.510131, 0.713656, 1.120707",\ + "0.589569, 0.702704, 0.813760, 1.016668, 1.422484"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011"); + values ( "0.026989, 0.188809, 0.387926, 0.758818, 1.500603",\ + "0.026989, 0.188809, 0.387926, 0.758818, 1.500603",\ + "0.027967, 0.188809, 0.387926, 0.758818, 1.500603",\ + "0.029933, 0.189417, 0.388385, 0.759721, 1.502395",\ + "0.048080, 0.193656, 0.388460, 0.760493, 1.504560"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[1]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.027696, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.217652, 0.171723, 0.141523, 0.130179, 0.143864",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026989, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.251704, 0.176383, 0.108224, 0.085257, 0.148171",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[1]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.027696, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.149579, -0.107162, -0.072675, -0.033251, 0.272796",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026989, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.164860, -0.098945, -0.041286, 0.000675, 0.221283",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[1]_hldr*/ + +} /* end of pin dpram_rmf_o[1] */ + +pin("dpram_rmf_o[0]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002026 ; + + /* Other user defined attributes. */ + original_pin : dpram_rmf_o[0]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011"); + values ( "0.048221, 0.201247, 0.376603, 0.699350, 1.344843",\ + "0.134540, 0.288422, 0.463709, 0.786065, 1.430777",\ + "0.217754, 0.376549, 0.551664, 0.873687, 1.517732",\ + "0.275678, 0.440944, 0.615780, 0.937600, 1.581241",\ + "0.575742, 0.790814, 0.966163, 1.286341, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011"); + values ( "0.024153, 0.299842, 0.633087, 1.249579, 2.482563",\ + "0.028666, 0.300830, 0.635034, 1.249579, 2.482563",\ + "0.041608, 0.303085, 0.635070, 1.249579, 2.482563",\ + "0.053514, 0.306363, 0.635172, 1.249579, 2.482563",\ + "0.129154, 0.344706, 0.641428, 1.252134, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011"); + values ( "0.067848, 0.172946, 0.284382, 0.488491, 0.896709",\ + "0.155259, 0.260265, 0.371663, 0.575796, 0.984062",\ + "0.235619, 0.340599, 0.451690, 0.655824, 1.064094",\ + "0.292315, 0.398147, 0.509233, 0.713069, 1.120741",\ + "0.586152, 0.701486, 0.812865, 1.016083, 1.422518"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011"); + values ( "0.024592, 0.187440, 0.387796, 0.759979, 1.504343",\ + "0.024592, 0.187585, 0.388300, 0.759979, 1.504343",\ + "0.025674, 0.187585, 0.388300, 0.759979, 1.504343",\ + "0.027742, 0.187585, 0.388300, 0.759979, 1.504343",\ + "0.046348, 0.191554, 0.388300, 0.759979, 1.504623"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[0]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011"); + values ( "0.048221, 0.201247, 0.376603, 0.699350, 1.344843",\ + "0.134540, 0.288422, 0.463709, 0.786065, 1.430777",\ + "0.217754, 0.376549, 0.551664, 0.873687, 1.517732",\ + "0.275678, 0.440944, 0.615780, 0.937600, 1.581241",\ + "0.575742, 0.790814, 0.966163, 1.286341, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011"); + values ( "0.024153, 0.299842, 0.633087, 1.248350, 2.473548",\ + "0.028666, 0.300830, 0.635034, 1.248350, 2.473548",\ + "0.041608, 0.303085, 0.635070, 1.248425, 2.473548",\ + "0.053514, 0.306363, 0.635172, 1.249169, 2.473548",\ + "0.129154, 0.344706, 0.641428, 1.252134, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011"); + values ( "0.067848, 0.172946, 0.284382, 0.488491, 0.896709",\ + "0.155259, 0.260265, 0.371663, 0.575796, 0.984062",\ + "0.235619, 0.340599, 0.451690, 0.655824, 1.064094",\ + "0.292315, 0.398147, 0.509233, 0.713069, 1.120741",\ + "0.586152, 0.701486, 0.812865, 1.016083, 1.422518"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011"); + values ( "0.024592, 0.186641, 0.386289, 0.757748, 1.500666",\ + "0.024592, 0.186641, 0.386289, 0.757748, 1.500666",\ + "0.025674, 0.186641, 0.386289, 0.757748, 1.500666",\ + "0.027742, 0.187251, 0.386746, 0.758650, 1.502457",\ + "0.046348, 0.191554, 0.386818, 0.759420, 1.504623"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[0]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.216011, 0.170082, 0.139882, 0.128539, 0.142224",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024592, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.250613, 0.175291, 0.107132, 0.084165, 0.147079",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[0]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.147938, -0.105521, -0.071034, -0.031611, 0.274436",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024592, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.163769, -0.097854, -0.040195, 0.001766, 0.222374",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[0]_hldr*/ + +} /* end of pin dpram_rmf_o[0] */ +} /* end of bus dpram_rmf_o */ +bus ( dpram_rml_o ) { + + bus_type : BUS10_type8 ; + direction : output ; + +pin("dpram_rml_o[9]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.003142 ; + + /* Other user defined attributes. */ + original_pin : dpram_rml_o[9]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003142, 0.076141, 0.162859, 0.322576, 0.642011"); + values ( "0.051240, 0.203496, 0.378292, 0.700476, 1.344843",\ + "0.137724, 0.290671, 0.465395, 0.787189, 1.430777",\ + "0.221682, 0.378796, 0.553349, 0.874810, 1.517732",\ + "0.280355, 0.443186, 0.617463, 0.938722, 1.581241",\ + "0.584942, 0.793069, 0.967839, 1.287458, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003142, 0.076141, 0.162859, 0.322576, 0.642011"); + values ( "0.028205, 0.304109, 0.636312, 1.251729, 2.482563",\ + "0.032295, 0.305121, 0.638243, 1.251729, 2.482563",\ + "0.044791, 0.307337, 0.638279, 1.251729, 2.482563",\ + "0.056753, 0.310558, 0.638384, 1.251729, 2.482563",\ + "0.133215, 0.348353, 0.644623, 1.254264, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003142, 0.076141, 0.162859, 0.322576, 0.642011"); + values ( "0.070508, 0.174340, 0.285412, 0.489165, 0.896671",\ + "0.157911, 0.261657, 0.372693, 0.576470, 0.984024",\ + "0.238313, 0.341986, 0.452720, 0.656498, 1.064056",\ + "0.295115, 0.399536, 0.510261, 0.713742, 1.120703",\ + "0.590063, 0.702880, 0.813890, 1.016754, 1.422480"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003142, 0.076141, 0.162859, 0.322576, 0.642011"); + values ( "0.027336, 0.189933, 0.389674, 0.761207, 1.504274",\ + "0.027336, 0.190085, 0.390175, 0.761207, 1.504274",\ + "0.028299, 0.190085, 0.390175, 0.761207, 1.504274",\ + "0.030250, 0.190085, 0.390175, 0.761207, 1.504274",\ + "0.048330, 0.193960, 0.390175, 0.761207, 1.504554"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[9]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003142, 0.076141, 0.162859, 0.322576, 0.642011"); + values ( "0.051240, 0.203496, 0.378292, 0.700476, 1.344843",\ + "0.137724, 0.290671, 0.465395, 0.787189, 1.430777",\ + "0.221682, 0.378796, 0.553349, 0.874810, 1.517732",\ + "0.280355, 0.443186, 0.617463, 0.938722, 1.581241",\ + "0.584942, 0.793069, 0.967839, 1.287458, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003142, 0.076141, 0.162859, 0.322576, 0.642011"); + values ( "0.028205, 0.304109, 0.636312, 1.250489, 2.473548",\ + "0.032295, 0.305121, 0.638243, 1.250489, 2.473548",\ + "0.044791, 0.307337, 0.638279, 1.250564, 2.473548",\ + "0.056753, 0.310558, 0.638384, 1.251310, 2.473548",\ + "0.133215, 0.348353, 0.644623, 1.254264, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003142, 0.076141, 0.162859, 0.322576, 0.642011"); + values ( "0.070508, 0.174340, 0.285412, 0.489165, 0.896671",\ + "0.157911, 0.261657, 0.372693, 0.576470, 0.984024",\ + "0.238313, 0.341986, 0.452720, 0.656498, 1.064056",\ + "0.295115, 0.399536, 0.510261, 0.713742, 1.120703",\ + "0.590063, 0.702880, 0.813890, 1.016754, 1.422480"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003142, 0.076141, 0.162859, 0.322576, 0.642011"); + values ( "0.027336, 0.189123, 0.388163, 0.758974, 1.500597",\ + "0.027336, 0.189123, 0.388163, 0.758974, 1.500597",\ + "0.028299, 0.189123, 0.388163, 0.758974, 1.500597",\ + "0.030250, 0.189730, 0.388622, 0.759878, 1.502388",\ + "0.048330, 0.193960, 0.388698, 0.760650, 1.504554"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[9]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.028205, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.217887, 0.171958, 0.141759, 0.130415, 0.144100",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.027336, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.251862, 0.176541, 0.108382, 0.085415, 0.148328",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[9]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.028205, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.149814, -0.107397, -0.072910, -0.033487, 0.272560",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.027336, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.165018, -0.099103, -0.041444, 0.000517, 0.221125",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[9]_hldr*/ + +} /* end of pin dpram_rml_o[9] */ + +pin("dpram_rml_o[8]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002583 ; + + /* Other user defined attributes. */ + original_pin : dpram_rml_o[8]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002583, 0.075582, 0.162440, 0.322297, 0.642011"); + values ( "0.049728, 0.202370, 0.377446, 0.699912, 1.344843",\ + "0.136129, 0.289544, 0.464550, 0.786626, 1.430777",\ + "0.219715, 0.377671, 0.552505, 0.874247, 1.517732",\ + "0.278013, 0.442063, 0.616620, 0.938160, 1.581241",\ + "0.580334, 0.791940, 0.967000, 1.286899, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002583, 0.075582, 0.162440, 0.322297, 0.642011"); + values ( "0.026175, 0.301972, 0.634697, 1.250652, 2.482564",\ + "0.030477, 0.302972, 0.636635, 1.250652, 2.482564",\ + "0.043197, 0.305208, 0.636672, 1.250652, 2.482564",\ + "0.055131, 0.308457, 0.636775, 1.250652, 2.482564",\ + "0.131181, 0.346526, 0.643023, 1.253198, 2.482564"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002583, 0.075582, 0.162440, 0.322297, 0.642011"); + values ( "0.069162, 0.173635, 0.284889, 0.488820, 0.896683",\ + "0.156569, 0.260953, 0.372170, 0.576125, 0.984036",\ + "0.236950, 0.341284, 0.452197, 0.656154, 1.064068",\ + "0.293698, 0.398833, 0.509739, 0.713398, 1.120715",\ + "0.588084, 0.702174, 0.813370, 1.016411, 1.422492"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002583, 0.075582, 0.162440, 0.322297, 0.642011"); + values ( "0.025948, 0.188671, 0.388720, 0.760579, 1.504295",\ + "0.025948, 0.188820, 0.389223, 0.760579, 1.504295",\ + "0.026971, 0.188820, 0.389223, 0.760579, 1.504295",\ + "0.028981, 0.188820, 0.389223, 0.760579, 1.504295",\ + "0.047327, 0.192742, 0.389223, 0.760579, 1.504576"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[8]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002583, 0.075582, 0.162440, 0.322297, 0.642011"); + values ( "0.049728, 0.202370, 0.377446, 0.699912, 1.344843",\ + "0.136129, 0.289544, 0.464550, 0.786626, 1.430777",\ + "0.219715, 0.377671, 0.552505, 0.874247, 1.517732",\ + "0.278013, 0.442063, 0.616620, 0.938160, 1.581241",\ + "0.580334, 0.791940, 0.967000, 1.286899, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002583, 0.075582, 0.162440, 0.322297, 0.642011"); + values ( "0.026175, 0.301972, 0.634697, 1.249417, 2.473548",\ + "0.030477, 0.302972, 0.636635, 1.249417, 2.473548",\ + "0.043197, 0.305208, 0.636672, 1.249493, 2.473548",\ + "0.055131, 0.308457, 0.636775, 1.250238, 2.473548",\ + "0.131181, 0.346526, 0.643023, 1.253198, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002583, 0.075582, 0.162440, 0.322297, 0.642011"); + values ( "0.069162, 0.173635, 0.284889, 0.488820, 0.896683",\ + "0.156569, 0.260953, 0.372170, 0.576125, 0.984036",\ + "0.236950, 0.341284, 0.452197, 0.656154, 1.064068",\ + "0.293698, 0.398833, 0.509739, 0.713398, 1.120715",\ + "0.588084, 0.702174, 0.813370, 1.016411, 1.422492"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002583, 0.075582, 0.162440, 0.322297, 0.642011"); + values ( "0.025948, 0.187867, 0.387212, 0.758347, 1.500618",\ + "0.025948, 0.187867, 0.387212, 0.758347, 1.500618",\ + "0.026971, 0.187867, 0.387212, 0.758347, 1.500618",\ + "0.028981, 0.188476, 0.387670, 0.759250, 1.502410",\ + "0.047327, 0.192742, 0.387744, 0.760021, 1.504576"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[8]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026175, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.216947, 0.171018, 0.140819, 0.129475, 0.143160",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025948, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.251230, 0.175909, 0.107750, 0.084782, 0.147696",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[8]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026175, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.148875, -0.106458, -0.071971, -0.032547, 0.273500",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025948, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.164386, -0.098471, -0.040812, 0.001149, 0.221757",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[8]_hldr*/ + +} /* end of pin dpram_rml_o[8] */ + +pin("dpram_rml_o[7]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002594 ; + + /* Other user defined attributes. */ + original_pin : dpram_rml_o[7]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002594, 0.075593, 0.162448, 0.322302, 0.642011"); + values ( "0.049757, 0.202391, 0.377463, 0.699923, 1.344843",\ + "0.136160, 0.289566, 0.464567, 0.786637, 1.430777",\ + "0.219753, 0.377693, 0.552521, 0.874258, 1.517732",\ + "0.278058, 0.442085, 0.616637, 0.938171, 1.581241",\ + "0.580424, 0.791962, 0.967016, 1.286910, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002594, 0.075593, 0.162448, 0.322302, 0.642011"); + values ( "0.026215, 0.302013, 0.634728, 1.250673, 2.482563",\ + "0.030513, 0.303014, 0.636667, 1.250673, 2.482563",\ + "0.043228, 0.305249, 0.636703, 1.250673, 2.482563",\ + "0.055162, 0.308498, 0.636806, 1.250673, 2.482563",\ + "0.131221, 0.346562, 0.643054, 1.253218, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002594, 0.075593, 0.162448, 0.322302, 0.642011"); + values ( "0.069192, 0.173650, 0.284901, 0.488829, 0.896685",\ + "0.156600, 0.260968, 0.372182, 0.576134, 0.984038",\ + "0.236980, 0.341300, 0.452209, 0.656163, 1.064070",\ + "0.293730, 0.398849, 0.509751, 0.713407, 1.120717",\ + "0.588129, 0.702190, 0.813382, 1.016419, 1.422494"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002594, 0.075593, 0.162448, 0.322302, 0.642011"); + values ( "0.025979, 0.188700, 0.388743, 0.760595, 1.504299",\ + "0.025979, 0.188849, 0.389245, 0.760595, 1.504299",\ + "0.027001, 0.188849, 0.389245, 0.760595, 1.504299",\ + "0.029010, 0.188849, 0.389245, 0.760595, 1.504299",\ + "0.047350, 0.192770, 0.389245, 0.760595, 1.504579"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[7]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002594, 0.075593, 0.162448, 0.322302, 0.642011"); + values ( "0.049757, 0.202391, 0.377463, 0.699923, 1.344843",\ + "0.136160, 0.289566, 0.464567, 0.786637, 1.430777",\ + "0.219753, 0.377693, 0.552521, 0.874258, 1.517732",\ + "0.278058, 0.442085, 0.616637, 0.938171, 1.581241",\ + "0.580424, 0.791962, 0.967016, 1.286910, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002594, 0.075593, 0.162448, 0.322302, 0.642011"); + values ( "0.026215, 0.302013, 0.634728, 1.249438, 2.473548",\ + "0.030513, 0.303014, 0.636667, 1.249438, 2.473548",\ + "0.043228, 0.305249, 0.636703, 1.249514, 2.473548",\ + "0.055162, 0.308498, 0.636806, 1.250259, 2.473548",\ + "0.131221, 0.346562, 0.643054, 1.253218, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002594, 0.075593, 0.162448, 0.322302, 0.642011"); + values ( "0.069192, 0.173650, 0.284901, 0.488829, 0.896685",\ + "0.156600, 0.260968, 0.372182, 0.576134, 0.984038",\ + "0.236980, 0.341300, 0.452209, 0.656163, 1.064070",\ + "0.293730, 0.398849, 0.509751, 0.713407, 1.120717",\ + "0.588129, 0.702190, 0.813382, 1.016419, 1.422494"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002594, 0.075593, 0.162448, 0.322302, 0.642011"); + values ( "0.025979, 0.187895, 0.387234, 0.758363, 1.500622",\ + "0.025979, 0.187895, 0.387234, 0.758363, 1.500622",\ + "0.027001, 0.187895, 0.387234, 0.758363, 1.500622",\ + "0.029010, 0.188504, 0.387692, 0.759266, 1.502414",\ + "0.047350, 0.192770, 0.387766, 0.760037, 1.504579"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[7]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026215, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.216966, 0.171037, 0.140837, 0.129493, 0.143178",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025979, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.251244, 0.175923, 0.107764, 0.084797, 0.147711",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[7]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026215, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.148893, -0.106476, -0.071989, -0.032565, 0.273482",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025979, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.164400, -0.098485, -0.040826, 0.001135, 0.221743",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[7]_hldr*/ + +} /* end of pin dpram_rml_o[7] */ + +pin("dpram_rml_o[6]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002460 ; + + /* Other user defined attributes. */ + original_pin : dpram_rml_o[6]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002460, 0.075458, 0.162347, 0.322235, 0.642011"); + values ( "0.049394, 0.202121, 0.377259, 0.699787, 1.344843",\ + "0.135777, 0.289295, 0.464364, 0.786501, 1.430777",\ + "0.219280, 0.377422, 0.552318, 0.874123, 1.517732",\ + "0.277495, 0.441815, 0.616434, 0.938036, 1.581241",\ + "0.579315, 0.791690, 0.966814, 1.286775, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002460, 0.075458, 0.162347, 0.322235, 0.642011"); + values ( "0.025727, 0.301499, 0.634339, 1.250414, 2.482564",\ + "0.030075, 0.302497, 0.636280, 1.250414, 2.482564",\ + "0.042844, 0.304737, 0.636316, 1.250414, 2.482564",\ + "0.054772, 0.307992, 0.636419, 1.250414, 2.482564",\ + "0.130732, 0.346122, 0.642669, 1.252962, 2.482564"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002460, 0.075458, 0.162347, 0.322235, 0.642011"); + values ( "0.068872, 0.173483, 0.284777, 0.488748, 0.896689",\ + "0.156281, 0.260801, 0.372058, 0.576053, 0.984043",\ + "0.236656, 0.341133, 0.452085, 0.656082, 1.064075",\ + "0.293393, 0.398682, 0.509628, 0.713326, 1.120722",\ + "0.587658, 0.702023, 0.813259, 1.016339, 1.422499"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002460, 0.075458, 0.162347, 0.322235, 0.642011"); + values ( "0.025649, 0.188400, 0.388517, 0.760448, 1.504308",\ + "0.025649, 0.188548, 0.389020, 0.760448, 1.504308",\ + "0.026685, 0.188548, 0.389020, 0.760448, 1.504308",\ + "0.028708, 0.188548, 0.389020, 0.760448, 1.504308",\ + "0.047111, 0.192480, 0.389020, 0.760448, 1.504588"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[6]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002460, 0.075458, 0.162347, 0.322235, 0.642011"); + values ( "0.049394, 0.202121, 0.377259, 0.699787, 1.344843",\ + "0.135777, 0.289295, 0.464364, 0.786501, 1.430777",\ + "0.219280, 0.377422, 0.552318, 0.874123, 1.517732",\ + "0.277495, 0.441815, 0.616434, 0.938036, 1.581241",\ + "0.579315, 0.791690, 0.966814, 1.286775, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002460, 0.075458, 0.162347, 0.322235, 0.642011"); + values ( "0.025727, 0.301499, 0.634339, 1.249181, 2.473548",\ + "0.030075, 0.302497, 0.636280, 1.249181, 2.473548",\ + "0.042844, 0.304737, 0.636316, 1.249256, 2.473548",\ + "0.054772, 0.307992, 0.636419, 1.250001, 2.473548",\ + "0.130732, 0.346122, 0.642669, 1.252962, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002460, 0.075458, 0.162347, 0.322235, 0.642011"); + values ( "0.068872, 0.173483, 0.284777, 0.488748, 0.896689",\ + "0.156281, 0.260801, 0.372058, 0.576053, 0.984043",\ + "0.236656, 0.341133, 0.452085, 0.656082, 1.064075",\ + "0.293393, 0.398682, 0.509628, 0.713326, 1.120722",\ + "0.587658, 0.702023, 0.813259, 1.016339, 1.422499"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002460, 0.075458, 0.162347, 0.322235, 0.642011"); + values ( "0.025649, 0.187597, 0.387009, 0.758216, 1.500631",\ + "0.025649, 0.187597, 0.387009, 0.758216, 1.500631",\ + "0.026685, 0.187597, 0.387009, 0.758216, 1.500631",\ + "0.028708, 0.188206, 0.387467, 0.759119, 1.502422",\ + "0.047111, 0.192480, 0.387540, 0.759889, 1.504588"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[6]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025727, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.216740, 0.170811, 0.140611, 0.129267, 0.142952",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025649, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.251094, 0.175772, 0.107614, 0.084646, 0.147560",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[6]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025727, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.148667, -0.106250, -0.071763, -0.032339, 0.273708",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025649, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.164250, -0.098335, -0.040676, 0.001285, 0.221893",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[6]_hldr*/ + +} /* end of pin dpram_rml_o[6] */ + +pin("dpram_rml_o[5]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002976 ; + + /* Other user defined attributes. */ + original_pin : dpram_rml_o[5]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002976, 0.075975, 0.162735, 0.322493, 0.642011"); + values ( "0.050791, 0.203162, 0.378041, 0.700308, 1.344843",\ + "0.137251, 0.290336, 0.465144, 0.787022, 1.430777",\ + "0.221098, 0.378462, 0.553098, 0.874643, 1.517732",\ + "0.279660, 0.442853, 0.617213, 0.938556, 1.581241",\ + "0.583574, 0.792734, 0.967589, 1.287292, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002976, 0.075975, 0.162735, 0.322493, 0.642011"); + values ( "0.027602, 0.303474, 0.635832, 1.251409, 2.482564",\ + "0.031755, 0.304483, 0.637765, 1.251409, 2.482564",\ + "0.044318, 0.306705, 0.637801, 1.251409, 2.482564",\ + "0.056271, 0.309934, 0.637906, 1.251409, 2.482564",\ + "0.132611, 0.347810, 0.644148, 1.253948, 2.482564"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002976, 0.075975, 0.162735, 0.322493, 0.642011"); + values ( "0.070108, 0.174130, 0.285256, 0.489062, 0.896674",\ + "0.157512, 0.261448, 0.372537, 0.576367, 0.984027",\ + "0.237907, 0.341777, 0.452564, 0.656396, 1.064059",\ + "0.294694, 0.399327, 0.510106, 0.713639, 1.120707",\ + "0.589475, 0.702670, 0.813735, 1.016652, 1.422484"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002976, 0.075975, 0.162735, 0.322493, 0.642011"); + values ( "0.026923, 0.189558, 0.389390, 0.761020, 1.504280",\ + "0.026923, 0.189709, 0.389892, 0.761020, 1.504280",\ + "0.027904, 0.189709, 0.389892, 0.761020, 1.504280",\ + "0.029873, 0.189709, 0.389892, 0.761020, 1.504280",\ + "0.048032, 0.193598, 0.389892, 0.761020, 1.504560"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[5]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002976, 0.075975, 0.162735, 0.322493, 0.642011"); + values ( "0.050791, 0.203162, 0.378041, 0.700308, 1.344843",\ + "0.137251, 0.290336, 0.465144, 0.787022, 1.430777",\ + "0.221098, 0.378462, 0.553098, 0.874643, 1.517732",\ + "0.279660, 0.442853, 0.617213, 0.938556, 1.581241",\ + "0.583574, 0.792734, 0.967589, 1.287292, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002976, 0.075975, 0.162735, 0.322493, 0.642011"); + values ( "0.027602, 0.303474, 0.635832, 1.250171, 2.473548",\ + "0.031755, 0.304483, 0.637765, 1.250171, 2.473548",\ + "0.044318, 0.306705, 0.637801, 1.250246, 2.473548",\ + "0.056271, 0.309934, 0.637906, 1.250992, 2.473548",\ + "0.132611, 0.347810, 0.644148, 1.253948, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002976, 0.075975, 0.162735, 0.322493, 0.642011"); + values ( "0.070108, 0.174130, 0.285256, 0.489062, 0.896674",\ + "0.157512, 0.261448, 0.372537, 0.576367, 0.984027",\ + "0.237907, 0.341777, 0.452564, 0.656396, 1.064059",\ + "0.294694, 0.399327, 0.510106, 0.713639, 1.120707",\ + "0.589475, 0.702670, 0.813735, 1.016652, 1.422484"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002976, 0.075975, 0.162735, 0.322493, 0.642011"); + values ( "0.026923, 0.188750, 0.387880, 0.758788, 1.500602",\ + "0.026923, 0.188750, 0.387880, 0.758788, 1.500602",\ + "0.027904, 0.188750, 0.387880, 0.758788, 1.500602",\ + "0.029873, 0.189357, 0.388339, 0.759691, 1.502394",\ + "0.048032, 0.193598, 0.388414, 0.760463, 1.504560"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[5]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.027602, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.217608, 0.171679, 0.141479, 0.130136, 0.143821",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026923, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.251674, 0.176353, 0.108194, 0.085227, 0.148140",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[5]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.027602, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.149535, -0.107118, -0.072631, -0.033208, 0.272839",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026923, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.164830, -0.098915, -0.041256, 0.000705, 0.221313",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[5]_hldr*/ + +} /* end of pin dpram_rml_o[5] */ + +pin("dpram_rml_o[4]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.004037 ; + + /* Other user defined attributes. */ + original_pin : dpram_rml_o[4]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004037, 0.077035, 0.163530, 0.323024, 0.642011"); + values ( "0.053659, 0.205298, 0.379645, 0.701378, 1.344843",\ + "0.140277, 0.292473, 0.466747, 0.788090, 1.430777",\ + "0.224830, 0.380596, 0.554699, 0.875710, 1.517732",\ + "0.284103, 0.444983, 0.618813, 0.939622, 1.581241",\ + "0.592316, 0.794877, 0.969181, 1.288353, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004037, 0.077035, 0.163530, 0.323024, 0.642011"); + values ( "0.031452, 0.307528, 0.638897, 1.253452, 2.482564",\ + "0.035203, 0.308560, 0.640814, 1.253452, 2.482564",\ + "0.047343, 0.310745, 0.640850, 1.253452, 2.482564",\ + "0.059348, 0.313921, 0.640958, 1.253452, 2.482564",\ + "0.136469, 0.351276, 0.647183, 1.255971, 2.482564"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004037, 0.077035, 0.163530, 0.323024, 0.642011"); + values ( "0.072631, 0.175452, 0.286232, 0.489700, 0.896636",\ + "0.160028, 0.262769, 0.373513, 0.577005, 0.983989",\ + "0.240463, 0.343094, 0.453540, 0.657034, 1.064021",\ + "0.297350, 0.400643, 0.511081, 0.714277, 1.120669",\ + "0.593185, 0.703993, 0.814708, 1.017287, 1.422446"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004037, 0.077035, 0.163530, 0.323024, 0.642011"); + values ( "0.029527, 0.191922, 0.391170, 0.762184, 1.504210",\ + "0.029527, 0.192081, 0.391669, 0.762184, 1.504210",\ + "0.030394, 0.192081, 0.391669, 0.762184, 1.504210",\ + "0.032251, 0.192081, 0.391669, 0.762184, 1.504210",\ + "0.049913, 0.195880, 0.391669, 0.762184, 1.504490"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[4]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004037, 0.077035, 0.163530, 0.323024, 0.642011"); + values ( "0.053659, 0.205298, 0.379645, 0.701378, 1.344843",\ + "0.140277, 0.292473, 0.466747, 0.788090, 1.430777",\ + "0.224830, 0.380596, 0.554699, 0.875710, 1.517732",\ + "0.284103, 0.444983, 0.618813, 0.939622, 1.581241",\ + "0.592316, 0.794877, 0.969181, 1.288353, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004037, 0.077035, 0.163530, 0.323024, 0.642011"); + values ( "0.031452, 0.307528, 0.638897, 1.252203, 2.473548",\ + "0.035203, 0.308560, 0.640814, 1.252203, 2.473548",\ + "0.047343, 0.310745, 0.640850, 1.252279, 2.473548",\ + "0.059348, 0.313921, 0.640958, 1.253027, 2.473548",\ + "0.136469, 0.351276, 0.647183, 1.255971, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004037, 0.077035, 0.163530, 0.323024, 0.642011"); + values ( "0.072631, 0.175452, 0.286232, 0.489700, 0.896636",\ + "0.160028, 0.262769, 0.373513, 0.577005, 0.983989",\ + "0.240463, 0.343094, 0.453540, 0.657034, 1.064021",\ + "0.297350, 0.400643, 0.511081, 0.714277, 1.120669",\ + "0.593185, 0.703993, 0.814708, 1.017287, 1.422446"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004037, 0.077035, 0.163530, 0.323024, 0.642011"); + values ( "0.029527, 0.191105, 0.389657, 0.759949, 1.500533",\ + "0.029527, 0.191105, 0.389657, 0.759949, 1.500533",\ + "0.030394, 0.191105, 0.389657, 0.759949, 1.500533",\ + "0.032251, 0.191709, 0.390118, 0.760853, 1.502324",\ + "0.049913, 0.195880, 0.390196, 0.761627, 1.504490"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[4]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.031452, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.219390, 0.173461, 0.143262, 0.131918, 0.145603",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.029527, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.252859, 0.177538, 0.109379, 0.086412, 0.149326",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[4]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.031452, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.151318, -0.108901, -0.074414, -0.034990, 0.271057",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.029527, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.166015, -0.100100, -0.042441, -0.000480, 0.220128",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[4]_hldr*/ + +} /* end of pin dpram_rml_o[4] */ + +pin("dpram_rml_o[3]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002031 ; + + /* Other user defined attributes. */ + original_pin : dpram_rml_o[3]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002031, 0.075029, 0.162026, 0.322021, 0.642011"); + values ( "0.048234, 0.201257, 0.376611, 0.699355, 1.344843",\ + "0.134553, 0.288431, 0.463716, 0.786070, 1.430777",\ + "0.217771, 0.376559, 0.551671, 0.873691, 1.517732",\ + "0.275698, 0.440953, 0.615787, 0.937605, 1.581241",\ + "0.575781, 0.790824, 0.966170, 1.286346, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002031, 0.075029, 0.162026, 0.322021, 0.642011"); + values ( "0.024170, 0.299860, 0.633100, 1.249588, 2.482563",\ + "0.028681, 0.300849, 0.635047, 1.249588, 2.482563",\ + "0.041621, 0.303103, 0.635083, 1.249588, 2.482563",\ + "0.053528, 0.306381, 0.635185, 1.249588, 2.482563",\ + "0.129172, 0.344721, 0.641441, 1.252143, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002031, 0.075029, 0.162026, 0.322021, 0.642011"); + values ( "0.067866, 0.172955, 0.284390, 0.488497, 0.896712",\ + "0.155277, 0.260274, 0.371670, 0.575802, 0.984065",\ + "0.235637, 0.340608, 0.451697, 0.655831, 1.064097",\ + "0.292333, 0.398157, 0.509240, 0.713075, 1.120745",\ + "0.586178, 0.701495, 0.812873, 1.016089, 1.422521"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002031, 0.075029, 0.162026, 0.322021, 0.642011"); + values ( "0.024610, 0.187457, 0.387810, 0.759990, 1.504349",\ + "0.024610, 0.187602, 0.388314, 0.759990, 1.504349",\ + "0.025692, 0.187602, 0.388314, 0.759990, 1.504349",\ + "0.027759, 0.187602, 0.388314, 0.759990, 1.504349",\ + "0.046361, 0.191570, 0.388314, 0.759990, 1.504629"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[3]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002031, 0.075029, 0.162026, 0.322021, 0.642011"); + values ( "0.048234, 0.201257, 0.376611, 0.699355, 1.344843",\ + "0.134553, 0.288431, 0.463716, 0.786070, 1.430777",\ + "0.217771, 0.376559, 0.551671, 0.873691, 1.517732",\ + "0.275698, 0.440953, 0.615787, 0.937605, 1.581241",\ + "0.575781, 0.790824, 0.966170, 1.286346, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002031, 0.075029, 0.162026, 0.322021, 0.642011"); + values ( "0.024170, 0.299860, 0.633100, 1.248359, 2.473548",\ + "0.028681, 0.300849, 0.635047, 1.248359, 2.473548",\ + "0.041621, 0.303103, 0.635083, 1.248434, 2.473548",\ + "0.053528, 0.306381, 0.635185, 1.249178, 2.473548",\ + "0.129172, 0.344721, 0.641441, 1.252143, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002031, 0.075029, 0.162026, 0.322021, 0.642011"); + values ( "0.067866, 0.172955, 0.284390, 0.488497, 0.896712",\ + "0.155277, 0.260274, 0.371670, 0.575802, 0.984065",\ + "0.235637, 0.340608, 0.451697, 0.655831, 1.064097",\ + "0.292333, 0.398157, 0.509240, 0.713075, 1.120745",\ + "0.586178, 0.701495, 0.812873, 1.016089, 1.422521"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002031, 0.075029, 0.162026, 0.322021, 0.642011"); + values ( "0.024610, 0.186657, 0.386303, 0.757760, 1.500672",\ + "0.024610, 0.186657, 0.386303, 0.757760, 1.500672",\ + "0.025692, 0.186657, 0.386303, 0.757760, 1.500672",\ + "0.027759, 0.187268, 0.386760, 0.758661, 1.502463",\ + "0.046361, 0.191570, 0.386832, 0.759431, 1.504629"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[3]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024170, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.216019, 0.170090, 0.139890, 0.128547, 0.142232",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024610, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.250621, 0.175300, 0.107141, 0.084173, 0.147087",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[3]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024170, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.147946, -0.105529, -0.071042, -0.031619, 0.274428",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024610, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.163777, -0.097862, -0.040203, 0.001758, 0.222366",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[3]_hldr*/ + +} /* end of pin dpram_rml_o[3] */ + +pin("dpram_rml_o[2]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.003654 ; + + /* Other user defined attributes. */ + original_pin : dpram_rml_o[2]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003654, 0.076652, 0.163243, 0.322832, 0.642011"); + values ( "0.052623, 0.204527, 0.379066, 0.700992, 1.344843",\ + "0.139184, 0.291701, 0.466168, 0.787704, 1.430777",\ + "0.223482, 0.379826, 0.554121, 0.875325, 1.517732",\ + "0.282499, 0.444214, 0.618235, 0.939237, 1.581241",\ + "0.589159, 0.794103, 0.968606, 1.287970, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003654, 0.076652, 0.163243, 0.322832, 0.642011"); + values ( "0.030062, 0.306064, 0.637790, 1.252714, 2.482564",\ + "0.033958, 0.307087, 0.639713, 1.252714, 2.482564",\ + "0.046250, 0.309286, 0.639749, 1.252714, 2.482564",\ + "0.058237, 0.312481, 0.639856, 1.252714, 2.482564",\ + "0.135075, 0.350024, 0.646087, 1.255240, 2.482564"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003654, 0.076652, 0.163243, 0.322832, 0.642011"); + values ( "0.071715, 0.174972, 0.285877, 0.489467, 0.896647",\ + "0.159114, 0.262289, 0.373158, 0.576772, 0.984000",\ + "0.239535, 0.342616, 0.453185, 0.656801, 1.064032",\ + "0.296386, 0.400165, 0.510726, 0.714044, 1.120680",\ + "0.591837, 0.703513, 0.814354, 1.017055, 1.422457"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003654, 0.076652, 0.163243, 0.322832, 0.642011"); + values ( "0.028581, 0.191064, 0.390523, 0.761759, 1.504230",\ + "0.028581, 0.191220, 0.391022, 0.761759, 1.504230",\ + "0.029490, 0.191220, 0.391022, 0.761759, 1.504230",\ + "0.031388, 0.191220, 0.391022, 0.761759, 1.504230",\ + "0.049229, 0.195051, 0.391022, 0.761759, 1.504510"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[2]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003654, 0.076652, 0.163243, 0.322832, 0.642011"); + values ( "0.052623, 0.204527, 0.379066, 0.700992, 1.344843",\ + "0.139184, 0.291701, 0.466168, 0.787704, 1.430777",\ + "0.223482, 0.379826, 0.554121, 0.875325, 1.517732",\ + "0.282499, 0.444214, 0.618235, 0.939237, 1.581241",\ + "0.589159, 0.794103, 0.968606, 1.287970, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003654, 0.076652, 0.163243, 0.322832, 0.642011"); + values ( "0.030062, 0.306064, 0.637790, 1.251469, 2.473548",\ + "0.033958, 0.307087, 0.639713, 1.251469, 2.473548",\ + "0.046250, 0.309286, 0.639749, 1.251544, 2.473548",\ + "0.058237, 0.312481, 0.639856, 1.252292, 2.473548",\ + "0.135075, 0.350024, 0.646087, 1.255240, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003654, 0.076652, 0.163243, 0.322832, 0.642011"); + values ( "0.071715, 0.174972, 0.285877, 0.489467, 0.896647",\ + "0.159114, 0.262289, 0.373158, 0.576772, 0.984000",\ + "0.239535, 0.342616, 0.453185, 0.656801, 1.064032",\ + "0.296386, 0.400165, 0.510726, 0.714044, 1.120680",\ + "0.591837, 0.703513, 0.814354, 1.017055, 1.422457"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003654, 0.076652, 0.163243, 0.322832, 0.642011"); + values ( "0.028581, 0.190249, 0.389010, 0.759525, 1.500553",\ + "0.028581, 0.190249, 0.389010, 0.759525, 1.500553",\ + "0.029490, 0.190249, 0.389010, 0.759525, 1.500553",\ + "0.031388, 0.190855, 0.389471, 0.760429, 1.502345",\ + "0.049229, 0.195051, 0.389548, 0.761202, 1.504510"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[2]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.030062, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.218747, 0.172818, 0.142618, 0.131274, 0.144959",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.028581, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.252429, 0.177108, 0.108949, 0.085981, 0.148895",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[2]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.030062, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.150674, -0.108257, -0.073770, -0.034347, 0.271701",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.028581, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.165584, -0.099669, -0.042010, -0.000049, 0.220558",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[2]_hldr*/ + +} /* end of pin dpram_rml_o[2] */ + +pin("dpram_rml_o[1]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002005 ; + + /* Other user defined attributes. */ + original_pin : dpram_rml_o[1]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011"); + values ( "0.048165, 0.201205, 0.376572, 0.699329, 1.344843",\ + "0.134480, 0.288380, 0.463677, 0.786044, 1.430777",\ + "0.217680, 0.376507, 0.551633, 0.873666, 1.517732",\ + "0.275590, 0.440902, 0.615748, 0.937579, 1.581241",\ + "0.575569, 0.790772, 0.966132, 1.286320, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011"); + values ( "0.024077, 0.299762, 0.633026, 1.249539, 2.482564",\ + "0.028598, 0.300750, 0.634974, 1.249539, 2.482564",\ + "0.041548, 0.303005, 0.635010, 1.249539, 2.482564",\ + "0.053453, 0.306284, 0.635112, 1.249539, 2.482564",\ + "0.129078, 0.344637, 0.641368, 1.252094, 2.482564"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011"); + values ( "0.067810, 0.172926, 0.284369, 0.488484, 0.896715",\ + "0.155221, 0.260244, 0.371649, 0.575789, 0.984069",\ + "0.235580, 0.340579, 0.451676, 0.655818, 1.064101",\ + "0.292274, 0.398127, 0.509219, 0.713062, 1.120748",\ + "0.586096, 0.701465, 0.812852, 1.016076, 1.422525"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011"); + values ( "0.024552, 0.187404, 0.387772, 0.759966, 1.504356",\ + "0.024552, 0.187549, 0.388276, 0.759966, 1.504356",\ + "0.025636, 0.187549, 0.388276, 0.759966, 1.504356",\ + "0.027706, 0.187549, 0.388276, 0.759966, 1.504356",\ + "0.046319, 0.191519, 0.388276, 0.759966, 1.504636"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[1]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011"); + values ( "0.048165, 0.201205, 0.376572, 0.699329, 1.344843",\ + "0.134480, 0.288380, 0.463677, 0.786044, 1.430777",\ + "0.217680, 0.376507, 0.551633, 0.873666, 1.517732",\ + "0.275590, 0.440902, 0.615748, 0.937579, 1.581241",\ + "0.575569, 0.790772, 0.966132, 1.286320, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011"); + values ( "0.024077, 0.299762, 0.633026, 1.248310, 2.473548",\ + "0.028598, 0.300750, 0.634974, 1.248310, 2.473548",\ + "0.041548, 0.303005, 0.635010, 1.248385, 2.473548",\ + "0.053453, 0.306284, 0.635112, 1.249129, 2.473548",\ + "0.129078, 0.344637, 0.641368, 1.252094, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011"); + values ( "0.067810, 0.172926, 0.284369, 0.488484, 0.896715",\ + "0.155221, 0.260244, 0.371649, 0.575789, 0.984069",\ + "0.235580, 0.340579, 0.451676, 0.655818, 1.064101",\ + "0.292274, 0.398127, 0.509219, 0.713062, 1.120748",\ + "0.586096, 0.701465, 0.812852, 1.016076, 1.422525"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011"); + values ( "0.024552, 0.186605, 0.386265, 0.757736, 1.500678",\ + "0.024552, 0.186605, 0.386265, 0.757736, 1.500678",\ + "0.025636, 0.186605, 0.386265, 0.757736, 1.500678",\ + "0.027706, 0.187215, 0.386722, 0.758638, 1.502470",\ + "0.046319, 0.191519, 0.386794, 0.759408, 1.504636"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[1]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024077, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.215976, 0.170047, 0.139847, 0.128503, 0.142188",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024552, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.250595, 0.175273, 0.107114, 0.084147, 0.147061",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[1]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024077, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.147903, -0.105486, -0.070999, -0.031576, 0.274471",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024552, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.163751, -0.097835, -0.040177, 0.001784, 0.222392",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[1]_hldr*/ + +} /* end of pin dpram_rml_o[1] */ + +pin("dpram_rml_o[0]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002547 ; + + /* Other user defined attributes. */ + original_pin : dpram_rml_o[0]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002547, 0.075545, 0.162413, 0.322279, 0.642011"); + values ( "0.049629, 0.202296, 0.377391, 0.699875, 1.344843",\ + "0.136025, 0.289471, 0.464495, 0.786589, 1.430777",\ + "0.219586, 0.377597, 0.552450, 0.874211, 1.517732",\ + "0.277859, 0.441990, 0.616565, 0.938124, 1.581241",\ + "0.580033, 0.791866, 0.966945, 1.286862, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002547, 0.075545, 0.162413, 0.322279, 0.642011"); + values ( "0.026043, 0.301832, 0.634591, 1.250582, 2.482563",\ + "0.030358, 0.302831, 0.636530, 1.250582, 2.482563",\ + "0.043092, 0.305068, 0.636566, 1.250582, 2.482563",\ + "0.055024, 0.308320, 0.636670, 1.250582, 2.482563",\ + "0.131048, 0.346407, 0.642918, 1.253128, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002547, 0.075545, 0.162413, 0.322279, 0.642011"); + values ( "0.069083, 0.173593, 0.284859, 0.488802, 0.896688",\ + "0.156491, 0.260911, 0.372140, 0.576107, 0.984042",\ + "0.236870, 0.341243, 0.452167, 0.656136, 1.064073",\ + "0.293615, 0.398792, 0.509709, 0.713380, 1.120721",\ + "0.587968, 0.702133, 0.813340, 1.016393, 1.422498"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002547, 0.075545, 0.162413, 0.322279, 0.642011"); + values ( "0.025866, 0.188597, 0.388667, 0.760546, 1.504306",\ + "0.025866, 0.188746, 0.389169, 0.760546, 1.504306",\ + "0.026893, 0.188746, 0.389169, 0.760546, 1.504306",\ + "0.028907, 0.188746, 0.389169, 0.760546, 1.504306",\ + "0.047268, 0.192671, 0.389169, 0.760546, 1.504586"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[0]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002547, 0.075545, 0.162413, 0.322279, 0.642011"); + values ( "0.049629, 0.202296, 0.377391, 0.699875, 1.344843",\ + "0.136025, 0.289471, 0.464495, 0.786589, 1.430777",\ + "0.219586, 0.377597, 0.552450, 0.874211, 1.517732",\ + "0.277859, 0.441990, 0.616565, 0.938124, 1.581241",\ + "0.580033, 0.791866, 0.966945, 1.286862, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002547, 0.075545, 0.162413, 0.322279, 0.642011"); + values ( "0.026043, 0.301832, 0.634591, 1.249347, 2.473548",\ + "0.030358, 0.302831, 0.636530, 1.249347, 2.473548",\ + "0.043092, 0.305068, 0.636566, 1.249423, 2.473548",\ + "0.055024, 0.308320, 0.636670, 1.250168, 2.473548",\ + "0.131048, 0.346407, 0.642918, 1.253128, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002547, 0.075545, 0.162413, 0.322279, 0.642011"); + values ( "0.069083, 0.173593, 0.284859, 0.488802, 0.896688",\ + "0.156491, 0.260911, 0.372140, 0.576107, 0.984042",\ + "0.236870, 0.341243, 0.452167, 0.656136, 1.064073",\ + "0.293615, 0.398792, 0.509709, 0.713380, 1.120721",\ + "0.587968, 0.702133, 0.813340, 1.016393, 1.422498"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002547, 0.075545, 0.162413, 0.322279, 0.642011"); + values ( "0.025866, 0.187793, 0.387158, 0.758315, 1.500628",\ + "0.025866, 0.187793, 0.387158, 0.758315, 1.500628",\ + "0.026893, 0.187793, 0.387158, 0.758315, 1.500628",\ + "0.028907, 0.188402, 0.387616, 0.759217, 1.502420",\ + "0.047268, 0.192671, 0.387690, 0.759988, 1.504586"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[0]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026043, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.216886, 0.170957, 0.140757, 0.129414, 0.143099",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025866, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.251193, 0.175871, 0.107712, 0.084745, 0.147659",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[0]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026043, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.148813, -0.106396, -0.071909, -0.032486, 0.273561",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025866, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.164349, -0.098434, -0.040775, 0.001186, 0.221794",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[0]_hldr*/ + +} /* end of pin dpram_rml_o[0] */ +} /* end of bus dpram_rml_o */ +bus ( spram_rm_o ) { + + bus_type : BUS5_type4 ; + direction : output ; + +pin("spram_rm_o[4]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002015 ; + + /* Other user defined attributes. */ + original_pin : spram_rm_o[4]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011"); + values ( "0.048192, 0.201225, 0.376587, 0.699339, 1.344843",\ + "0.134509, 0.288400, 0.463692, 0.786054, 1.430777",\ + "0.217716, 0.376528, 0.551648, 0.873676, 1.517732",\ + "0.275633, 0.440922, 0.615763, 0.937589, 1.581241",\ + "0.575653, 0.790792, 0.966147, 1.286330, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011"); + values ( "0.024114, 0.299801, 0.633056, 1.249558, 2.482564",\ + "0.028631, 0.300789, 0.635003, 1.249558, 2.482564",\ + "0.041577, 0.303044, 0.635039, 1.249558, 2.482564",\ + "0.053483, 0.306322, 0.635141, 1.249558, 2.482564",\ + "0.129115, 0.344671, 0.641397, 1.252114, 2.482564"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011"); + values ( "0.067832, 0.172938, 0.284377, 0.488489, 0.896714",\ + "0.155243, 0.260256, 0.371658, 0.575794, 0.984068",\ + "0.235603, 0.340590, 0.451685, 0.655823, 1.064099",\ + "0.292298, 0.398139, 0.509228, 0.713068, 1.120747",\ + "0.586128, 0.701477, 0.812860, 1.016081, 1.422524"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011"); + values ( "0.024575, 0.187425, 0.387787, 0.759976, 1.504353",\ + "0.024575, 0.187570, 0.388291, 0.759976, 1.504353",\ + "0.025658, 0.187570, 0.388291, 0.759976, 1.504353",\ + "0.027727, 0.187570, 0.388291, 0.759976, 1.504353",\ + "0.046336, 0.191539, 0.388291, 0.759976, 1.504633"); + } + + } /* end of arc clk_ast_tlul_i_spram_rm_o[4]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011"); + values ( "0.048192, 0.201225, 0.376587, 0.699339, 1.344843",\ + "0.134509, 0.288400, 0.463692, 0.786054, 1.430777",\ + "0.217716, 0.376528, 0.551648, 0.873676, 1.517732",\ + "0.275633, 0.440922, 0.615763, 0.937589, 1.581241",\ + "0.575653, 0.790792, 0.966147, 1.286330, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011"); + values ( "0.024114, 0.299801, 0.633056, 1.248329, 2.473548",\ + "0.028631, 0.300789, 0.635003, 1.248329, 2.473548",\ + "0.041577, 0.303044, 0.635039, 1.248404, 2.473548",\ + "0.053483, 0.306322, 0.635141, 1.249148, 2.473548",\ + "0.129115, 0.344671, 0.641397, 1.252114, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011"); + values ( "0.067832, 0.172938, 0.284377, 0.488489, 0.896714",\ + "0.155243, 0.260256, 0.371658, 0.575794, 0.984068",\ + "0.235603, 0.340590, 0.451685, 0.655823, 1.064099",\ + "0.292298, 0.398139, 0.509228, 0.713068, 1.120747",\ + "0.586128, 0.701477, 0.812860, 1.016081, 1.422524"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011"); + values ( "0.024575, 0.186626, 0.386280, 0.757745, 1.500676",\ + "0.024575, 0.186626, 0.386280, 0.757745, 1.500676",\ + "0.025658, 0.186626, 0.386280, 0.757745, 1.500676",\ + "0.027727, 0.187236, 0.386737, 0.758647, 1.502467",\ + "0.046336, 0.191539, 0.386809, 0.759417, 1.504633"); + } + + } /* end of arc clk_ast_tlul_i_spram_rm_o[4]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024114, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.215993, 0.170064, 0.139864, 0.128520, 0.142206",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024575, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.250605, 0.175284, 0.107125, 0.084158, 0.147071",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_spram_rm_o[4]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024114, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.147920, -0.105503, -0.071016, -0.031593, 0.274454",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024575, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.163761, -0.097846, -0.040187, 0.001774, 0.222382",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_spram_rm_o[4]_hldr*/ + +} /* end of pin spram_rm_o[4] */ + +pin("spram_rm_o[3]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002005 ; + + /* Other user defined attributes. */ + original_pin : spram_rm_o[3]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011"); + values ( "0.048165, 0.201205, 0.376572, 0.699329, 1.344843",\ + "0.134480, 0.288380, 0.463677, 0.786044, 1.430777",\ + "0.217680, 0.376507, 0.551633, 0.873666, 1.517732",\ + "0.275590, 0.440902, 0.615748, 0.937579, 1.581241",\ + "0.575569, 0.790772, 0.966132, 1.286320, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011"); + values ( "0.024077, 0.299762, 0.633026, 1.249539, 2.482564",\ + "0.028598, 0.300750, 0.634974, 1.249539, 2.482564",\ + "0.041548, 0.303005, 0.635010, 1.249539, 2.482564",\ + "0.053453, 0.306284, 0.635112, 1.249539, 2.482564",\ + "0.129078, 0.344637, 0.641368, 1.252094, 2.482564"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011"); + values ( "0.067810, 0.172926, 0.284369, 0.488484, 0.896715",\ + "0.155221, 0.260244, 0.371649, 0.575789, 0.984069",\ + "0.235580, 0.340579, 0.451676, 0.655818, 1.064101",\ + "0.292274, 0.398127, 0.509219, 0.713062, 1.120748",\ + "0.586096, 0.701465, 0.812852, 1.016076, 1.422525"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011"); + values ( "0.024552, 0.187404, 0.387772, 0.759966, 1.504356",\ + "0.024552, 0.187549, 0.388276, 0.759966, 1.504356",\ + "0.025636, 0.187549, 0.388276, 0.759966, 1.504356",\ + "0.027706, 0.187549, 0.388276, 0.759966, 1.504356",\ + "0.046319, 0.191519, 0.388276, 0.759966, 1.504636"); + } + + } /* end of arc clk_ast_tlul_i_spram_rm_o[3]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011"); + values ( "0.048165, 0.201205, 0.376572, 0.699329, 1.344843",\ + "0.134480, 0.288380, 0.463677, 0.786044, 1.430777",\ + "0.217680, 0.376507, 0.551633, 0.873666, 1.517732",\ + "0.275590, 0.440902, 0.615748, 0.937579, 1.581241",\ + "0.575569, 0.790772, 0.966132, 1.286320, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011"); + values ( "0.024077, 0.299762, 0.633026, 1.248310, 2.473548",\ + "0.028598, 0.300750, 0.634974, 1.248310, 2.473548",\ + "0.041548, 0.303005, 0.635010, 1.248385, 2.473548",\ + "0.053453, 0.306284, 0.635112, 1.249129, 2.473548",\ + "0.129078, 0.344637, 0.641368, 1.252094, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011"); + values ( "0.067810, 0.172926, 0.284369, 0.488484, 0.896715",\ + "0.155221, 0.260244, 0.371649, 0.575789, 0.984069",\ + "0.235580, 0.340579, 0.451676, 0.655818, 1.064101",\ + "0.292274, 0.398127, 0.509219, 0.713062, 1.120748",\ + "0.586096, 0.701465, 0.812852, 1.016076, 1.422525"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011"); + values ( "0.024552, 0.186605, 0.386265, 0.757736, 1.500678",\ + "0.024552, 0.186605, 0.386265, 0.757736, 1.500678",\ + "0.025636, 0.186605, 0.386265, 0.757736, 1.500678",\ + "0.027706, 0.187215, 0.386722, 0.758638, 1.502470",\ + "0.046319, 0.191519, 0.386794, 0.759408, 1.504636"); + } + + } /* end of arc clk_ast_tlul_i_spram_rm_o[3]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024077, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.215976, 0.170047, 0.139847, 0.128503, 0.142188",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024552, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.250595, 0.175273, 0.107114, 0.084147, 0.147061",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_spram_rm_o[3]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024077, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.147903, -0.105486, -0.070999, -0.031576, 0.274471",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024552, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.163751, -0.097835, -0.040177, 0.001784, 0.222392",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_spram_rm_o[3]_hldr*/ + +} /* end of pin spram_rm_o[3] */ + +pin("spram_rm_o[2]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002015 ; + + /* Other user defined attributes. */ + original_pin : spram_rm_o[2]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011"); + values ( "0.048192, 0.201225, 0.376587, 0.699339, 1.344843",\ + "0.134509, 0.288400, 0.463692, 0.786054, 1.430777",\ + "0.217716, 0.376528, 0.551648, 0.873676, 1.517732",\ + "0.275633, 0.440922, 0.615763, 0.937589, 1.581241",\ + "0.575653, 0.790792, 0.966147, 1.286330, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011"); + values ( "0.024114, 0.299801, 0.633056, 1.249558, 2.482564",\ + "0.028631, 0.300789, 0.635003, 1.249558, 2.482564",\ + "0.041577, 0.303044, 0.635039, 1.249558, 2.482564",\ + "0.053483, 0.306322, 0.635141, 1.249558, 2.482564",\ + "0.129115, 0.344671, 0.641397, 1.252114, 2.482564"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011"); + values ( "0.067832, 0.172938, 0.284377, 0.488489, 0.896714",\ + "0.155243, 0.260256, 0.371658, 0.575794, 0.984068",\ + "0.235603, 0.340590, 0.451685, 0.655823, 1.064099",\ + "0.292298, 0.398139, 0.509228, 0.713068, 1.120747",\ + "0.586128, 0.701477, 0.812860, 1.016081, 1.422524"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011"); + values ( "0.024575, 0.187425, 0.387787, 0.759976, 1.504353",\ + "0.024575, 0.187570, 0.388291, 0.759976, 1.504353",\ + "0.025658, 0.187570, 0.388291, 0.759976, 1.504353",\ + "0.027727, 0.187570, 0.388291, 0.759976, 1.504353",\ + "0.046336, 0.191539, 0.388291, 0.759976, 1.504633"); + } + + } /* end of arc clk_ast_tlul_i_spram_rm_o[2]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011"); + values ( "0.048192, 0.201225, 0.376587, 0.699339, 1.344843",\ + "0.134509, 0.288400, 0.463692, 0.786054, 1.430777",\ + "0.217716, 0.376528, 0.551648, 0.873676, 1.517732",\ + "0.275633, 0.440922, 0.615763, 0.937589, 1.581241",\ + "0.575653, 0.790792, 0.966147, 1.286330, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011"); + values ( "0.024114, 0.299801, 0.633056, 1.248329, 2.473548",\ + "0.028631, 0.300789, 0.635003, 1.248329, 2.473548",\ + "0.041577, 0.303044, 0.635039, 1.248404, 2.473548",\ + "0.053483, 0.306322, 0.635141, 1.249148, 2.473548",\ + "0.129115, 0.344671, 0.641397, 1.252114, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011"); + values ( "0.067832, 0.172938, 0.284377, 0.488489, 0.896714",\ + "0.155243, 0.260256, 0.371658, 0.575794, 0.984068",\ + "0.235603, 0.340590, 0.451685, 0.655823, 1.064099",\ + "0.292298, 0.398139, 0.509228, 0.713068, 1.120747",\ + "0.586128, 0.701477, 0.812860, 1.016081, 1.422524"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011"); + values ( "0.024575, 0.186626, 0.386280, 0.757745, 1.500676",\ + "0.024575, 0.186626, 0.386280, 0.757745, 1.500676",\ + "0.025658, 0.186626, 0.386280, 0.757745, 1.500676",\ + "0.027727, 0.187236, 0.386737, 0.758647, 1.502467",\ + "0.046336, 0.191539, 0.386809, 0.759417, 1.504633"); + } + + } /* end of arc clk_ast_tlul_i_spram_rm_o[2]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024114, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.215993, 0.170064, 0.139864, 0.128520, 0.142206",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024575, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.250605, 0.175284, 0.107125, 0.084158, 0.147071",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_spram_rm_o[2]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024114, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.147920, -0.105503, -0.071016, -0.031593, 0.274454",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024575, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.163761, -0.097846, -0.040187, 0.001774, 0.222382",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_spram_rm_o[2]_hldr*/ + +} /* end of pin spram_rm_o[2] */ + +pin("spram_rm_o[1]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.003002 ; + + /* Other user defined attributes. */ + original_pin : spram_rm_o[1]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011"); + values ( "0.050861, 0.203214, 0.378080, 0.700335, 1.344843",\ + "0.137325, 0.290388, 0.465183, 0.787048, 1.430777",\ + "0.221189, 0.378514, 0.553137, 0.874669, 1.517732",\ + "0.279768, 0.442905, 0.617252, 0.938582, 1.581241",\ + "0.583788, 0.792786, 0.967628, 1.287318, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011"); + values ( "0.027696, 0.303573, 0.635907, 1.251459, 2.482564",\ + "0.031840, 0.304583, 0.637840, 1.251459, 2.482564",\ + "0.044392, 0.306804, 0.637876, 1.251459, 2.482564",\ + "0.056346, 0.310032, 0.637981, 1.251459, 2.482564",\ + "0.132705, 0.347895, 0.644222, 1.253997, 2.482564"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011"); + values ( "0.070172, 0.174163, 0.285281, 0.489079, 0.896674",\ + "0.157576, 0.261481, 0.372562, 0.576384, 0.984028",\ + "0.237972, 0.341811, 0.452589, 0.656412, 1.064059",\ + "0.294761, 0.399360, 0.510131, 0.713656, 1.120707",\ + "0.589569, 0.702704, 0.813760, 1.016668, 1.422484"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011"); + values ( "0.026989, 0.189618, 0.389436, 0.761051, 1.504280",\ + "0.026989, 0.189769, 0.389937, 0.761051, 1.504280",\ + "0.027967, 0.189769, 0.389937, 0.761051, 1.504280",\ + "0.029933, 0.189769, 0.389937, 0.761051, 1.504280",\ + "0.048080, 0.193656, 0.389937, 0.761051, 1.504560"); + } + + } /* end of arc clk_ast_tlul_i_spram_rm_o[1]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011"); + values ( "0.050861, 0.203214, 0.378080, 0.700335, 1.344843",\ + "0.137325, 0.290388, 0.465183, 0.787048, 1.430777",\ + "0.221189, 0.378514, 0.553137, 0.874669, 1.517732",\ + "0.279768, 0.442905, 0.617252, 0.938582, 1.581241",\ + "0.583788, 0.792786, 0.967628, 1.287318, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011"); + values ( "0.027696, 0.303573, 0.635907, 1.250220, 2.473548",\ + "0.031840, 0.304583, 0.637840, 1.250220, 2.473548",\ + "0.044392, 0.306804, 0.637876, 1.250296, 2.473548",\ + "0.056346, 0.310032, 0.637981, 1.251042, 2.473548",\ + "0.132705, 0.347895, 0.644222, 1.253997, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011"); + values ( "0.070172, 0.174163, 0.285281, 0.489079, 0.896674",\ + "0.157576, 0.261481, 0.372562, 0.576384, 0.984028",\ + "0.237972, 0.341811, 0.452589, 0.656412, 1.064059",\ + "0.294761, 0.399360, 0.510131, 0.713656, 1.120707",\ + "0.589569, 0.702704, 0.813760, 1.016668, 1.422484"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011"); + values ( "0.026989, 0.188809, 0.387926, 0.758818, 1.500603",\ + "0.026989, 0.188809, 0.387926, 0.758818, 1.500603",\ + "0.027967, 0.188809, 0.387926, 0.758818, 1.500603",\ + "0.029933, 0.189417, 0.388385, 0.759721, 1.502395",\ + "0.048080, 0.193656, 0.388460, 0.760493, 1.504560"); + } + + } /* end of arc clk_ast_tlul_i_spram_rm_o[1]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.027696, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.217652, 0.171723, 0.141523, 0.130179, 0.143864",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026989, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.251704, 0.176383, 0.108224, 0.085257, 0.148171",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_spram_rm_o[1]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.027696, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.149579, -0.107162, -0.072675, -0.033251, 0.272796",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026989, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.164860, -0.098945, -0.041286, 0.000675, 0.221283",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_spram_rm_o[1]_hldr*/ + +} /* end of pin spram_rm_o[1] */ + +pin("spram_rm_o[0]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002026 ; + + /* Other user defined attributes. */ + original_pin : spram_rm_o[0]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011"); + values ( "0.048221, 0.201247, 0.376603, 0.699350, 1.344843",\ + "0.134540, 0.288422, 0.463709, 0.786065, 1.430777",\ + "0.217754, 0.376549, 0.551664, 0.873687, 1.517732",\ + "0.275678, 0.440944, 0.615780, 0.937600, 1.581241",\ + "0.575742, 0.790814, 0.966163, 1.286341, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011"); + values ( "0.024153, 0.299842, 0.633087, 1.249579, 2.482563",\ + "0.028666, 0.300830, 0.635034, 1.249579, 2.482563",\ + "0.041608, 0.303085, 0.635070, 1.249579, 2.482563",\ + "0.053514, 0.306363, 0.635172, 1.249579, 2.482563",\ + "0.129154, 0.344706, 0.641428, 1.252134, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011"); + values ( "0.067848, 0.172946, 0.284382, 0.488491, 0.896709",\ + "0.155259, 0.260265, 0.371663, 0.575796, 0.984062",\ + "0.235619, 0.340599, 0.451690, 0.655824, 1.064094",\ + "0.292315, 0.398147, 0.509233, 0.713069, 1.120741",\ + "0.586152, 0.701486, 0.812865, 1.016083, 1.422518"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011"); + values ( "0.024592, 0.187440, 0.387796, 0.759979, 1.504343",\ + "0.024592, 0.187585, 0.388300, 0.759979, 1.504343",\ + "0.025674, 0.187585, 0.388300, 0.759979, 1.504343",\ + "0.027742, 0.187585, 0.388300, 0.759979, 1.504343",\ + "0.046348, 0.191554, 0.388300, 0.759979, 1.504623"); + } + + } /* end of arc clk_ast_tlul_i_spram_rm_o[0]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011"); + values ( "0.048221, 0.201247, 0.376603, 0.699350, 1.344843",\ + "0.134540, 0.288422, 0.463709, 0.786065, 1.430777",\ + "0.217754, 0.376549, 0.551664, 0.873687, 1.517732",\ + "0.275678, 0.440944, 0.615780, 0.937600, 1.581241",\ + "0.575742, 0.790814, 0.966163, 1.286341, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011"); + values ( "0.024153, 0.299842, 0.633087, 1.248350, 2.473548",\ + "0.028666, 0.300830, 0.635034, 1.248350, 2.473548",\ + "0.041608, 0.303085, 0.635070, 1.248425, 2.473548",\ + "0.053514, 0.306363, 0.635172, 1.249169, 2.473548",\ + "0.129154, 0.344706, 0.641428, 1.252134, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011"); + values ( "0.067848, 0.172946, 0.284382, 0.488491, 0.896709",\ + "0.155259, 0.260265, 0.371663, 0.575796, 0.984062",\ + "0.235619, 0.340599, 0.451690, 0.655824, 1.064094",\ + "0.292315, 0.398147, 0.509233, 0.713069, 1.120741",\ + "0.586152, 0.701486, 0.812865, 1.016083, 1.422518"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011"); + values ( "0.024592, 0.186641, 0.386289, 0.757748, 1.500666",\ + "0.024592, 0.186641, 0.386289, 0.757748, 1.500666",\ + "0.025674, 0.186641, 0.386289, 0.757748, 1.500666",\ + "0.027742, 0.187251, 0.386746, 0.758650, 1.502457",\ + "0.046348, 0.191554, 0.386818, 0.759420, 1.504623"); + } + + } /* end of arc clk_ast_tlul_i_spram_rm_o[0]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.216011, 0.170082, 0.139882, 0.128539, 0.142224",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024592, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.250613, 0.175291, 0.107132, 0.084165, 0.147079",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_spram_rm_o[0]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.147938, -0.105521, -0.071034, -0.031611, 0.274436",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024592, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.163769, -0.097854, -0.040195, 0.001766, 0.222374",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_spram_rm_o[0]_hldr*/ + +} /* end of pin spram_rm_o[0] */ +} /* end of bus spram_rm_o */ +bus ( sprgf_rm_o ) { + + bus_type : BUS5_type4 ; + direction : output ; + +pin("sprgf_rm_o[4]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.004037 ; + + /* Other user defined attributes. */ + original_pin : sprgf_rm_o[4]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004037, 0.077035, 0.163530, 0.323024, 0.642011"); + values ( "0.053659, 0.205298, 0.379645, 0.701378, 1.344843",\ + "0.140277, 0.292473, 0.466747, 0.788090, 1.430777",\ + "0.224830, 0.380596, 0.554699, 0.875710, 1.517732",\ + "0.284103, 0.444983, 0.618813, 0.939622, 1.581241",\ + "0.592316, 0.794877, 0.969181, 1.288353, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004037, 0.077035, 0.163530, 0.323024, 0.642011"); + values ( "0.031452, 0.307528, 0.638897, 1.253452, 2.482564",\ + "0.035203, 0.308560, 0.640814, 1.253452, 2.482564",\ + "0.047343, 0.310745, 0.640850, 1.253452, 2.482564",\ + "0.059348, 0.313921, 0.640958, 1.253452, 2.482564",\ + "0.136469, 0.351276, 0.647183, 1.255971, 2.482564"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004037, 0.077035, 0.163530, 0.323024, 0.642011"); + values ( "0.072631, 0.175452, 0.286232, 0.489700, 0.896636",\ + "0.160028, 0.262769, 0.373513, 0.577005, 0.983989",\ + "0.240463, 0.343094, 0.453540, 0.657034, 1.064021",\ + "0.297350, 0.400643, 0.511081, 0.714277, 1.120669",\ + "0.593185, 0.703993, 0.814708, 1.017287, 1.422446"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004037, 0.077035, 0.163530, 0.323024, 0.642011"); + values ( "0.029527, 0.191922, 0.391170, 0.762184, 1.504210",\ + "0.029527, 0.192081, 0.391669, 0.762184, 1.504210",\ + "0.030394, 0.192081, 0.391669, 0.762184, 1.504210",\ + "0.032251, 0.192081, 0.391669, 0.762184, 1.504210",\ + "0.049913, 0.195880, 0.391669, 0.762184, 1.504490"); + } + + } /* end of arc clk_ast_tlul_i_sprgf_rm_o[4]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004037, 0.077035, 0.163530, 0.323024, 0.642011"); + values ( "0.053659, 0.205298, 0.379645, 0.701378, 1.344843",\ + "0.140277, 0.292473, 0.466747, 0.788090, 1.430777",\ + "0.224830, 0.380596, 0.554699, 0.875710, 1.517732",\ + "0.284103, 0.444983, 0.618813, 0.939622, 1.581241",\ + "0.592316, 0.794877, 0.969181, 1.288353, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004037, 0.077035, 0.163530, 0.323024, 0.642011"); + values ( "0.031452, 0.307528, 0.638897, 1.252203, 2.473548",\ + "0.035203, 0.308560, 0.640814, 1.252203, 2.473548",\ + "0.047343, 0.310745, 0.640850, 1.252279, 2.473548",\ + "0.059348, 0.313921, 0.640958, 1.253027, 2.473548",\ + "0.136469, 0.351276, 0.647183, 1.255971, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004037, 0.077035, 0.163530, 0.323024, 0.642011"); + values ( "0.072631, 0.175452, 0.286232, 0.489700, 0.896636",\ + "0.160028, 0.262769, 0.373513, 0.577005, 0.983989",\ + "0.240463, 0.343094, 0.453540, 0.657034, 1.064021",\ + "0.297350, 0.400643, 0.511081, 0.714277, 1.120669",\ + "0.593185, 0.703993, 0.814708, 1.017287, 1.422446"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004037, 0.077035, 0.163530, 0.323024, 0.642011"); + values ( "0.029527, 0.191105, 0.389657, 0.759949, 1.500533",\ + "0.029527, 0.191105, 0.389657, 0.759949, 1.500533",\ + "0.030394, 0.191105, 0.389657, 0.759949, 1.500533",\ + "0.032251, 0.191709, 0.390118, 0.760853, 1.502324",\ + "0.049913, 0.195880, 0.390196, 0.761627, 1.504490"); + } + + } /* end of arc clk_ast_tlul_i_sprgf_rm_o[4]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.031452, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.219390, 0.173461, 0.143262, 0.131918, 0.145603",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.029527, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.252859, 0.177538, 0.109379, 0.086412, 0.149326",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_sprgf_rm_o[4]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.031452, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.151318, -0.108901, -0.074414, -0.034990, 0.271057",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.029527, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.166015, -0.100100, -0.042441, -0.000480, 0.220128",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_sprgf_rm_o[4]_hldr*/ + +} /* end of pin sprgf_rm_o[4] */ + +pin("sprgf_rm_o[3]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002031 ; + + /* Other user defined attributes. */ + original_pin : sprgf_rm_o[3]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002031, 0.075029, 0.162026, 0.322021, 0.642011"); + values ( "0.048234, 0.201257, 0.376611, 0.699355, 1.344843",\ + "0.134553, 0.288431, 0.463716, 0.786070, 1.430777",\ + "0.217771, 0.376559, 0.551671, 0.873691, 1.517732",\ + "0.275698, 0.440953, 0.615787, 0.937605, 1.581241",\ + "0.575781, 0.790824, 0.966170, 1.286346, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002031, 0.075029, 0.162026, 0.322021, 0.642011"); + values ( "0.024170, 0.299860, 0.633100, 1.249588, 2.482563",\ + "0.028681, 0.300849, 0.635047, 1.249588, 2.482563",\ + "0.041621, 0.303103, 0.635083, 1.249588, 2.482563",\ + "0.053528, 0.306381, 0.635185, 1.249588, 2.482563",\ + "0.129172, 0.344721, 0.641441, 1.252143, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002031, 0.075029, 0.162026, 0.322021, 0.642011"); + values ( "0.067866, 0.172955, 0.284390, 0.488497, 0.896712",\ + "0.155277, 0.260274, 0.371670, 0.575802, 0.984065",\ + "0.235637, 0.340608, 0.451697, 0.655831, 1.064097",\ + "0.292333, 0.398157, 0.509240, 0.713075, 1.120745",\ + "0.586178, 0.701495, 0.812873, 1.016089, 1.422521"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002031, 0.075029, 0.162026, 0.322021, 0.642011"); + values ( "0.024610, 0.187457, 0.387810, 0.759990, 1.504349",\ + "0.024610, 0.187602, 0.388314, 0.759990, 1.504349",\ + "0.025692, 0.187602, 0.388314, 0.759990, 1.504349",\ + "0.027759, 0.187602, 0.388314, 0.759990, 1.504349",\ + "0.046361, 0.191570, 0.388314, 0.759990, 1.504629"); + } + + } /* end of arc clk_ast_tlul_i_sprgf_rm_o[3]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002031, 0.075029, 0.162026, 0.322021, 0.642011"); + values ( "0.048234, 0.201257, 0.376611, 0.699355, 1.344843",\ + "0.134553, 0.288431, 0.463716, 0.786070, 1.430777",\ + "0.217771, 0.376559, 0.551671, 0.873691, 1.517732",\ + "0.275698, 0.440953, 0.615787, 0.937605, 1.581241",\ + "0.575781, 0.790824, 0.966170, 1.286346, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002031, 0.075029, 0.162026, 0.322021, 0.642011"); + values ( "0.024170, 0.299860, 0.633100, 1.248359, 2.473548",\ + "0.028681, 0.300849, 0.635047, 1.248359, 2.473548",\ + "0.041621, 0.303103, 0.635083, 1.248434, 2.473548",\ + "0.053528, 0.306381, 0.635185, 1.249178, 2.473548",\ + "0.129172, 0.344721, 0.641441, 1.252143, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002031, 0.075029, 0.162026, 0.322021, 0.642011"); + values ( "0.067866, 0.172955, 0.284390, 0.488497, 0.896712",\ + "0.155277, 0.260274, 0.371670, 0.575802, 0.984065",\ + "0.235637, 0.340608, 0.451697, 0.655831, 1.064097",\ + "0.292333, 0.398157, 0.509240, 0.713075, 1.120745",\ + "0.586178, 0.701495, 0.812873, 1.016089, 1.422521"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002031, 0.075029, 0.162026, 0.322021, 0.642011"); + values ( "0.024610, 0.186657, 0.386303, 0.757760, 1.500672",\ + "0.024610, 0.186657, 0.386303, 0.757760, 1.500672",\ + "0.025692, 0.186657, 0.386303, 0.757760, 1.500672",\ + "0.027759, 0.187268, 0.386760, 0.758661, 1.502463",\ + "0.046361, 0.191570, 0.386832, 0.759431, 1.504629"); + } + + } /* end of arc clk_ast_tlul_i_sprgf_rm_o[3]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024170, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.216019, 0.170090, 0.139890, 0.128547, 0.142232",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024610, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.250621, 0.175300, 0.107141, 0.084173, 0.147087",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_sprgf_rm_o[3]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024170, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.147946, -0.105529, -0.071042, -0.031619, 0.274428",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024610, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.163777, -0.097862, -0.040203, 0.001758, 0.222366",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_sprgf_rm_o[3]_hldr*/ + +} /* end of pin sprgf_rm_o[3] */ + +pin("sprgf_rm_o[2]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.003654 ; + + /* Other user defined attributes. */ + original_pin : sprgf_rm_o[2]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003654, 0.076652, 0.163243, 0.322832, 0.642011"); + values ( "0.052623, 0.204527, 0.379066, 0.700992, 1.344843",\ + "0.139184, 0.291701, 0.466168, 0.787704, 1.430777",\ + "0.223482, 0.379826, 0.554121, 0.875325, 1.517732",\ + "0.282499, 0.444214, 0.618235, 0.939237, 1.581241",\ + "0.589159, 0.794103, 0.968606, 1.287970, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003654, 0.076652, 0.163243, 0.322832, 0.642011"); + values ( "0.030062, 0.306064, 0.637790, 1.252714, 2.482564",\ + "0.033958, 0.307087, 0.639713, 1.252714, 2.482564",\ + "0.046250, 0.309286, 0.639749, 1.252714, 2.482564",\ + "0.058237, 0.312481, 0.639856, 1.252714, 2.482564",\ + "0.135075, 0.350024, 0.646087, 1.255240, 2.482564"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003654, 0.076652, 0.163243, 0.322832, 0.642011"); + values ( "0.071715, 0.174972, 0.285877, 0.489467, 0.896647",\ + "0.159114, 0.262289, 0.373158, 0.576772, 0.984000",\ + "0.239535, 0.342616, 0.453185, 0.656801, 1.064032",\ + "0.296386, 0.400165, 0.510726, 0.714044, 1.120680",\ + "0.591837, 0.703513, 0.814354, 1.017055, 1.422457"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003654, 0.076652, 0.163243, 0.322832, 0.642011"); + values ( "0.028581, 0.191064, 0.390523, 0.761759, 1.504230",\ + "0.028581, 0.191220, 0.391022, 0.761759, 1.504230",\ + "0.029490, 0.191220, 0.391022, 0.761759, 1.504230",\ + "0.031388, 0.191220, 0.391022, 0.761759, 1.504230",\ + "0.049229, 0.195051, 0.391022, 0.761759, 1.504510"); + } + + } /* end of arc clk_ast_tlul_i_sprgf_rm_o[2]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003654, 0.076652, 0.163243, 0.322832, 0.642011"); + values ( "0.052623, 0.204527, 0.379066, 0.700992, 1.344843",\ + "0.139184, 0.291701, 0.466168, 0.787704, 1.430777",\ + "0.223482, 0.379826, 0.554121, 0.875325, 1.517732",\ + "0.282499, 0.444214, 0.618235, 0.939237, 1.581241",\ + "0.589159, 0.794103, 0.968606, 1.287970, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003654, 0.076652, 0.163243, 0.322832, 0.642011"); + values ( "0.030062, 0.306064, 0.637790, 1.251469, 2.473548",\ + "0.033958, 0.307087, 0.639713, 1.251469, 2.473548",\ + "0.046250, 0.309286, 0.639749, 1.251544, 2.473548",\ + "0.058237, 0.312481, 0.639856, 1.252292, 2.473548",\ + "0.135075, 0.350024, 0.646087, 1.255240, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003654, 0.076652, 0.163243, 0.322832, 0.642011"); + values ( "0.071715, 0.174972, 0.285877, 0.489467, 0.896647",\ + "0.159114, 0.262289, 0.373158, 0.576772, 0.984000",\ + "0.239535, 0.342616, 0.453185, 0.656801, 1.064032",\ + "0.296386, 0.400165, 0.510726, 0.714044, 1.120680",\ + "0.591837, 0.703513, 0.814354, 1.017055, 1.422457"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003654, 0.076652, 0.163243, 0.322832, 0.642011"); + values ( "0.028581, 0.190249, 0.389010, 0.759525, 1.500553",\ + "0.028581, 0.190249, 0.389010, 0.759525, 1.500553",\ + "0.029490, 0.190249, 0.389010, 0.759525, 1.500553",\ + "0.031388, 0.190855, 0.389471, 0.760429, 1.502345",\ + "0.049229, 0.195051, 0.389548, 0.761202, 1.504510"); + } + + } /* end of arc clk_ast_tlul_i_sprgf_rm_o[2]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.030062, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.218747, 0.172818, 0.142618, 0.131274, 0.144959",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.028581, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.252429, 0.177108, 0.108949, 0.085981, 0.148895",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_sprgf_rm_o[2]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.030062, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.150674, -0.108257, -0.073770, -0.034347, 0.271701",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.028581, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.165584, -0.099669, -0.042010, -0.000049, 0.220558",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_sprgf_rm_o[2]_hldr*/ + +} /* end of pin sprgf_rm_o[2] */ + +pin("sprgf_rm_o[1]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002005 ; + + /* Other user defined attributes. */ + original_pin : sprgf_rm_o[1]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011"); + values ( "0.048165, 0.201205, 0.376572, 0.699329, 1.344843",\ + "0.134480, 0.288380, 0.463677, 0.786044, 1.430777",\ + "0.217680, 0.376507, 0.551633, 0.873666, 1.517732",\ + "0.275590, 0.440902, 0.615748, 0.937579, 1.581241",\ + "0.575569, 0.790772, 0.966132, 1.286320, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011"); + values ( "0.024077, 0.299762, 0.633026, 1.249539, 2.482564",\ + "0.028598, 0.300750, 0.634974, 1.249539, 2.482564",\ + "0.041548, 0.303005, 0.635010, 1.249539, 2.482564",\ + "0.053453, 0.306284, 0.635112, 1.249539, 2.482564",\ + "0.129078, 0.344637, 0.641368, 1.252094, 2.482564"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011"); + values ( "0.067810, 0.172926, 0.284369, 0.488484, 0.896715",\ + "0.155221, 0.260244, 0.371649, 0.575789, 0.984069",\ + "0.235580, 0.340579, 0.451676, 0.655818, 1.064101",\ + "0.292274, 0.398127, 0.509219, 0.713062, 1.120748",\ + "0.586096, 0.701465, 0.812852, 1.016076, 1.422525"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011"); + values ( "0.024552, 0.187404, 0.387772, 0.759966, 1.504356",\ + "0.024552, 0.187549, 0.388276, 0.759966, 1.504356",\ + "0.025636, 0.187549, 0.388276, 0.759966, 1.504356",\ + "0.027706, 0.187549, 0.388276, 0.759966, 1.504356",\ + "0.046319, 0.191519, 0.388276, 0.759966, 1.504636"); + } + + } /* end of arc clk_ast_tlul_i_sprgf_rm_o[1]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011"); + values ( "0.048165, 0.201205, 0.376572, 0.699329, 1.344843",\ + "0.134480, 0.288380, 0.463677, 0.786044, 1.430777",\ + "0.217680, 0.376507, 0.551633, 0.873666, 1.517732",\ + "0.275590, 0.440902, 0.615748, 0.937579, 1.581241",\ + "0.575569, 0.790772, 0.966132, 1.286320, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011"); + values ( "0.024077, 0.299762, 0.633026, 1.248310, 2.473548",\ + "0.028598, 0.300750, 0.634974, 1.248310, 2.473548",\ + "0.041548, 0.303005, 0.635010, 1.248385, 2.473548",\ + "0.053453, 0.306284, 0.635112, 1.249129, 2.473548",\ + "0.129078, 0.344637, 0.641368, 1.252094, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011"); + values ( "0.067810, 0.172926, 0.284369, 0.488484, 0.896715",\ + "0.155221, 0.260244, 0.371649, 0.575789, 0.984069",\ + "0.235580, 0.340579, 0.451676, 0.655818, 1.064101",\ + "0.292274, 0.398127, 0.509219, 0.713062, 1.120748",\ + "0.586096, 0.701465, 0.812852, 1.016076, 1.422525"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011"); + values ( "0.024552, 0.186605, 0.386265, 0.757736, 1.500678",\ + "0.024552, 0.186605, 0.386265, 0.757736, 1.500678",\ + "0.025636, 0.186605, 0.386265, 0.757736, 1.500678",\ + "0.027706, 0.187215, 0.386722, 0.758638, 1.502470",\ + "0.046319, 0.191519, 0.386794, 0.759408, 1.504636"); + } + + } /* end of arc clk_ast_tlul_i_sprgf_rm_o[1]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024077, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.215976, 0.170047, 0.139847, 0.128503, 0.142188",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024552, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.250595, 0.175273, 0.107114, 0.084147, 0.147061",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_sprgf_rm_o[1]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024077, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.147903, -0.105486, -0.070999, -0.031576, 0.274471",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024552, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.163751, -0.097835, -0.040177, 0.001784, 0.222392",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_sprgf_rm_o[1]_hldr*/ + +} /* end of pin sprgf_rm_o[1] */ + +pin("sprgf_rm_o[0]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002547 ; + + /* Other user defined attributes. */ + original_pin : sprgf_rm_o[0]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002547, 0.075545, 0.162413, 0.322279, 0.642011"); + values ( "0.049629, 0.202296, 0.377391, 0.699875, 1.344843",\ + "0.136025, 0.289471, 0.464495, 0.786589, 1.430777",\ + "0.219586, 0.377597, 0.552450, 0.874211, 1.517732",\ + "0.277859, 0.441990, 0.616565, 0.938124, 1.581241",\ + "0.580033, 0.791866, 0.966945, 1.286862, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002547, 0.075545, 0.162413, 0.322279, 0.642011"); + values ( "0.026043, 0.301832, 0.634591, 1.250582, 2.482563",\ + "0.030358, 0.302831, 0.636530, 1.250582, 2.482563",\ + "0.043092, 0.305068, 0.636566, 1.250582, 2.482563",\ + "0.055024, 0.308320, 0.636670, 1.250582, 2.482563",\ + "0.131048, 0.346407, 0.642918, 1.253128, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002547, 0.075545, 0.162413, 0.322279, 0.642011"); + values ( "0.069083, 0.173593, 0.284859, 0.488802, 0.896688",\ + "0.156491, 0.260911, 0.372140, 0.576107, 0.984042",\ + "0.236870, 0.341243, 0.452167, 0.656136, 1.064073",\ + "0.293615, 0.398792, 0.509709, 0.713380, 1.120721",\ + "0.587968, 0.702133, 0.813340, 1.016393, 1.422498"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002547, 0.075545, 0.162413, 0.322279, 0.642011"); + values ( "0.025866, 0.188597, 0.388667, 0.760546, 1.504306",\ + "0.025866, 0.188746, 0.389169, 0.760546, 1.504306",\ + "0.026893, 0.188746, 0.389169, 0.760546, 1.504306",\ + "0.028907, 0.188746, 0.389169, 0.760546, 1.504306",\ + "0.047268, 0.192671, 0.389169, 0.760546, 1.504586"); + } + + } /* end of arc clk_ast_tlul_i_sprgf_rm_o[0]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002547, 0.075545, 0.162413, 0.322279, 0.642011"); + values ( "0.049629, 0.202296, 0.377391, 0.699875, 1.344843",\ + "0.136025, 0.289471, 0.464495, 0.786589, 1.430777",\ + "0.219586, 0.377597, 0.552450, 0.874211, 1.517732",\ + "0.277859, 0.441990, 0.616565, 0.938124, 1.581241",\ + "0.580033, 0.791866, 0.966945, 1.286862, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002547, 0.075545, 0.162413, 0.322279, 0.642011"); + values ( "0.026043, 0.301832, 0.634591, 1.249347, 2.473548",\ + "0.030358, 0.302831, 0.636530, 1.249347, 2.473548",\ + "0.043092, 0.305068, 0.636566, 1.249423, 2.473548",\ + "0.055024, 0.308320, 0.636670, 1.250168, 2.473548",\ + "0.131048, 0.346407, 0.642918, 1.253128, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002547, 0.075545, 0.162413, 0.322279, 0.642011"); + values ( "0.069083, 0.173593, 0.284859, 0.488802, 0.896688",\ + "0.156491, 0.260911, 0.372140, 0.576107, 0.984042",\ + "0.236870, 0.341243, 0.452167, 0.656136, 1.064073",\ + "0.293615, 0.398792, 0.509709, 0.713380, 1.120721",\ + "0.587968, 0.702133, 0.813340, 1.016393, 1.422498"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002547, 0.075545, 0.162413, 0.322279, 0.642011"); + values ( "0.025866, 0.187793, 0.387158, 0.758315, 1.500628",\ + "0.025866, 0.187793, 0.387158, 0.758315, 1.500628",\ + "0.026893, 0.187793, 0.387158, 0.758315, 1.500628",\ + "0.028907, 0.188402, 0.387616, 0.759217, 1.502420",\ + "0.047268, 0.192671, 0.387690, 0.759988, 1.504586"); + } + + } /* end of arc clk_ast_tlul_i_sprgf_rm_o[0]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026043, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.216886, 0.170957, 0.140757, 0.129414, 0.143099",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025866, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.251193, 0.175871, 0.107712, 0.084745, 0.147659",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_sprgf_rm_o[0]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026043, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.148813, -0.106396, -0.071909, -0.032486, 0.273561",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025866, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.164349, -0.098434, -0.040775, 0.001186, 0.221794",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_sprgf_rm_o[0]_hldr*/ + +} /* end of pin sprgf_rm_o[0] */ +} /* end of bus sprgf_rm_o */ +bus ( sprom_rm_o ) { + + bus_type : BUS5_type4 ; + direction : output ; + +pin("sprom_rm_o[4]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.003002 ; + + /* Other user defined attributes. */ + original_pin : sprom_rm_o[4]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011"); + values ( "0.050861, 0.203214, 0.378080, 0.700335, 1.344843",\ + "0.137325, 0.290388, 0.465183, 0.787048, 1.430777",\ + "0.221189, 0.378514, 0.553137, 0.874669, 1.517732",\ + "0.279768, 0.442905, 0.617252, 0.938582, 1.581241",\ + "0.583788, 0.792786, 0.967628, 1.287318, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011"); + values ( "0.027696, 0.303573, 0.635907, 1.251459, 2.482564",\ + "0.031840, 0.304583, 0.637840, 1.251459, 2.482564",\ + "0.044392, 0.306804, 0.637876, 1.251459, 2.482564",\ + "0.056346, 0.310032, 0.637981, 1.251459, 2.482564",\ + "0.132705, 0.347895, 0.644222, 1.253997, 2.482564"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011"); + values ( "0.070172, 0.174163, 0.285281, 0.489079, 0.896674",\ + "0.157576, 0.261481, 0.372562, 0.576384, 0.984028",\ + "0.237972, 0.341811, 0.452589, 0.656412, 1.064059",\ + "0.294761, 0.399360, 0.510131, 0.713656, 1.120707",\ + "0.589569, 0.702704, 0.813760, 1.016668, 1.422484"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011"); + values ( "0.026989, 0.189618, 0.389436, 0.761051, 1.504280",\ + "0.026989, 0.189769, 0.389937, 0.761051, 1.504280",\ + "0.027967, 0.189769, 0.389937, 0.761051, 1.504280",\ + "0.029933, 0.189769, 0.389937, 0.761051, 1.504280",\ + "0.048080, 0.193656, 0.389937, 0.761051, 1.504560"); + } + + } /* end of arc clk_ast_tlul_i_sprom_rm_o[4]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011"); + values ( "0.050861, 0.203214, 0.378080, 0.700335, 1.344843",\ + "0.137325, 0.290388, 0.465183, 0.787048, 1.430777",\ + "0.221189, 0.378514, 0.553137, 0.874669, 1.517732",\ + "0.279768, 0.442905, 0.617252, 0.938582, 1.581241",\ + "0.583788, 0.792786, 0.967628, 1.287318, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011"); + values ( "0.027696, 0.303573, 0.635907, 1.250220, 2.473548",\ + "0.031840, 0.304583, 0.637840, 1.250220, 2.473548",\ + "0.044392, 0.306804, 0.637876, 1.250296, 2.473548",\ + "0.056346, 0.310032, 0.637981, 1.251042, 2.473548",\ + "0.132705, 0.347895, 0.644222, 1.253997, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011"); + values ( "0.070172, 0.174163, 0.285281, 0.489079, 0.896674",\ + "0.157576, 0.261481, 0.372562, 0.576384, 0.984028",\ + "0.237972, 0.341811, 0.452589, 0.656412, 1.064059",\ + "0.294761, 0.399360, 0.510131, 0.713656, 1.120707",\ + "0.589569, 0.702704, 0.813760, 1.016668, 1.422484"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011"); + values ( "0.026989, 0.188809, 0.387926, 0.758818, 1.500603",\ + "0.026989, 0.188809, 0.387926, 0.758818, 1.500603",\ + "0.027967, 0.188809, 0.387926, 0.758818, 1.500603",\ + "0.029933, 0.189417, 0.388385, 0.759721, 1.502395",\ + "0.048080, 0.193656, 0.388460, 0.760493, 1.504560"); + } + + } /* end of arc clk_ast_tlul_i_sprom_rm_o[4]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.027696, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.217652, 0.171723, 0.141523, 0.130179, 0.143864",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026989, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.251704, 0.176383, 0.108224, 0.085257, 0.148171",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_sprom_rm_o[4]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.027696, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.149579, -0.107162, -0.072675, -0.033251, 0.272796",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026989, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.164860, -0.098945, -0.041286, 0.000675, 0.221283",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_sprom_rm_o[4]_hldr*/ + +} /* end of pin sprom_rm_o[4] */ + +pin("sprom_rm_o[3]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002553 ; + + /* Other user defined attributes. */ + original_pin : sprom_rm_o[3]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002553, 0.075552, 0.162418, 0.322282, 0.642011"); + values ( "0.049647, 0.202309, 0.377401, 0.699882, 1.344843",\ + "0.136044, 0.289484, 0.464505, 0.786596, 1.430777",\ + "0.219609, 0.377611, 0.552460, 0.874217, 1.517732",\ + "0.277887, 0.442003, 0.616575, 0.938130, 1.581241",\ + "0.580088, 0.791879, 0.966955, 1.286869, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002553, 0.075552, 0.162418, 0.322282, 0.642011"); + values ( "0.026067, 0.301857, 0.634610, 1.250594, 2.482563",\ + "0.030380, 0.302857, 0.636549, 1.250594, 2.482563",\ + "0.043111, 0.305094, 0.636586, 1.250594, 2.482563",\ + "0.055044, 0.308345, 0.636689, 1.250594, 2.482563",\ + "0.131072, 0.346429, 0.642937, 1.253140, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002553, 0.075552, 0.162418, 0.322282, 0.642011"); + values ( "0.069111, 0.173607, 0.284871, 0.488812, 0.896694",\ + "0.156518, 0.260926, 0.372152, 0.576117, 0.984047",\ + "0.236897, 0.341257, 0.452179, 0.656146, 1.064079",\ + "0.293644, 0.398806, 0.509722, 0.713390, 1.120727",\ + "0.588008, 0.702147, 0.813352, 1.016403, 1.422503"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002553, 0.075552, 0.162418, 0.322282, 0.642011"); + values ( "0.025894, 0.188623, 0.388689, 0.760565, 1.504316",\ + "0.025894, 0.188772, 0.389191, 0.760565, 1.504316",\ + "0.026920, 0.188772, 0.389191, 0.760565, 1.504316",\ + "0.028933, 0.188772, 0.389191, 0.760565, 1.504316",\ + "0.047288, 0.192696, 0.389191, 0.760565, 1.504596"); + } + + } /* end of arc clk_ast_tlul_i_sprom_rm_o[3]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002553, 0.075552, 0.162418, 0.322282, 0.642011"); + values ( "0.049647, 0.202309, 0.377401, 0.699882, 1.344843",\ + "0.136044, 0.289484, 0.464505, 0.786596, 1.430777",\ + "0.219609, 0.377611, 0.552460, 0.874217, 1.517732",\ + "0.277887, 0.442003, 0.616575, 0.938130, 1.581241",\ + "0.580088, 0.791879, 0.966955, 1.286869, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002553, 0.075552, 0.162418, 0.322282, 0.642011"); + values ( "0.026067, 0.301857, 0.634610, 1.249360, 2.473548",\ + "0.030380, 0.302857, 0.636549, 1.249360, 2.473548",\ + "0.043111, 0.305094, 0.636586, 1.249435, 2.473548",\ + "0.055044, 0.308345, 0.636689, 1.250180, 2.473548",\ + "0.131072, 0.346429, 0.642937, 1.253140, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002553, 0.075552, 0.162418, 0.322282, 0.642011"); + values ( "0.069111, 0.173607, 0.284871, 0.488812, 0.896694",\ + "0.156518, 0.260926, 0.372152, 0.576117, 0.984047",\ + "0.236897, 0.341257, 0.452179, 0.656146, 1.064079",\ + "0.293644, 0.398806, 0.509722, 0.713390, 1.120727",\ + "0.588008, 0.702147, 0.813352, 1.016403, 1.422503"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002553, 0.075552, 0.162418, 0.322282, 0.642011"); + values ( "0.025894, 0.187819, 0.387180, 0.758333, 1.500639",\ + "0.025894, 0.187819, 0.387180, 0.758333, 1.500639",\ + "0.026920, 0.187819, 0.387180, 0.758333, 1.500639",\ + "0.028933, 0.188428, 0.387638, 0.759236, 1.502430",\ + "0.047288, 0.192696, 0.387712, 0.760007, 1.504596"); + } + + } /* end of arc clk_ast_tlul_i_sprom_rm_o[3]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026067, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.216897, 0.170968, 0.140769, 0.129425, 0.143110",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025894, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.251206, 0.175884, 0.107725, 0.084758, 0.147672",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_sprom_rm_o[3]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026067, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.148824, -0.106407, -0.071920, -0.032497, 0.273550",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025894, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.164361, -0.098446, -0.040787, 0.001174, 0.221781",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_sprom_rm_o[3]_hldr*/ + +} /* end of pin sprom_rm_o[3] */ + +pin("sprom_rm_o[2]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.004615 ; + + /* Other user defined attributes. */ + original_pin : sprom_rm_o[2]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004615, 0.077613, 0.163964, 0.323313, 0.642011"); + values ( "0.055222, 0.206463, 0.380520, 0.701961, 1.344843",\ + "0.141926, 0.293637, 0.467620, 0.788672, 1.430777",\ + "0.226864, 0.381760, 0.555571, 0.876292, 1.517732",\ + "0.286525, 0.446144, 0.619684, 0.940203, 1.581241",\ + "0.597080, 0.796044, 0.970048, 1.288931, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004615, 0.077613, 0.163964, 0.323313, 0.642011"); + values ( "0.033550, 0.309737, 0.640567, 1.254566, 2.482564",\ + "0.037083, 0.310781, 0.642475, 1.254566, 2.482564",\ + "0.048991, 0.312947, 0.642512, 1.254566, 2.482564",\ + "0.061025, 0.316093, 0.642622, 1.254566, 2.482564",\ + "0.138571, 0.353164, 0.648838, 1.257074, 2.482564"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004615, 0.077613, 0.163964, 0.323313, 0.642011"); + values ( "0.073991, 0.176164, 0.286756, 0.490040, 0.896607",\ + "0.161383, 0.263480, 0.374037, 0.577345, 0.983960",\ + "0.241839, 0.343803, 0.454064, 0.657373, 1.063992",\ + "0.298782, 0.401353, 0.511604, 0.714616, 1.120639",\ + "0.595184, 0.704706, 0.815229, 1.017625, 1.422416"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004615, 0.077613, 0.163964, 0.323313, 0.642011"); + values ( "0.030929, 0.193196, 0.392126, 0.762803, 1.504157",\ + "0.030929, 0.193359, 0.392623, 0.762803, 1.504157",\ + "0.031735, 0.193359, 0.392623, 0.762803, 1.504157",\ + "0.033533, 0.193359, 0.392623, 0.762803, 1.504157",\ + "0.050926, 0.197109, 0.392623, 0.762803, 1.504437"); + } + + } /* end of arc clk_ast_tlul_i_sprom_rm_o[2]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004615, 0.077613, 0.163964, 0.323313, 0.642011"); + values ( "0.055222, 0.206463, 0.380520, 0.701961, 1.344843",\ + "0.141926, 0.293637, 0.467620, 0.788672, 1.430777",\ + "0.226864, 0.381760, 0.555571, 0.876292, 1.517732",\ + "0.286525, 0.446144, 0.619684, 0.940203, 1.581241",\ + "0.597080, 0.796044, 0.970048, 1.288931, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004615, 0.077613, 0.163964, 0.323313, 0.642011"); + values ( "0.033550, 0.309737, 0.640567, 1.253311, 2.473548",\ + "0.037083, 0.310781, 0.642475, 1.253311, 2.473548",\ + "0.048991, 0.312947, 0.642512, 1.253386, 2.473548",\ + "0.061025, 0.316093, 0.642622, 1.254135, 2.473548",\ + "0.138571, 0.353164, 0.648838, 1.257074, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004615, 0.077613, 0.163964, 0.323313, 0.642011"); + values ( "0.073991, 0.176164, 0.286756, 0.490040, 0.896607",\ + "0.161383, 0.263480, 0.374037, 0.577345, 0.983960",\ + "0.241839, 0.343803, 0.454064, 0.657373, 1.063992",\ + "0.298782, 0.401353, 0.511604, 0.714616, 1.120639",\ + "0.595184, 0.704706, 0.815229, 1.017625, 1.422416"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004615, 0.077613, 0.163964, 0.323313, 0.642011"); + values ( "0.030929, 0.192373, 0.390610, 0.760567, 1.500480",\ + "0.030929, 0.192373, 0.390610, 0.760567, 1.500480",\ + "0.031735, 0.192373, 0.390610, 0.760567, 1.500480",\ + "0.033533, 0.192976, 0.391072, 0.761472, 1.502271",\ + "0.050926, 0.197109, 0.391153, 0.762247, 1.504437"); + } + + } /* end of arc clk_ast_tlul_i_sprom_rm_o[2]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.033550, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.220362, 0.174433, 0.144233, 0.132890, 0.146575",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.030929, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.253498, 0.178177, 0.110018, 0.087050, 0.149964",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_sprom_rm_o[2]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.033550, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.152289, -0.109872, -0.075385, -0.035962, 0.270085",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.030929, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.166653, -0.100738, -0.043079, -0.001118, 0.219490",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_sprom_rm_o[2]_hldr*/ + +} /* end of pin sprom_rm_o[2] */ + +pin("sprom_rm_o[1]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002475 ; + + /* Other user defined attributes. */ + original_pin : sprom_rm_o[1]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011"); + values ( "0.049435, 0.202151, 0.377283, 0.699803, 1.344843",\ + "0.135820, 0.289326, 0.464387, 0.786517, 1.430777",\ + "0.219334, 0.377453, 0.552342, 0.874138, 1.517732",\ + "0.277559, 0.441846, 0.616457, 0.938052, 1.581241",\ + "0.579442, 0.791721, 0.966837, 1.286790, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011"); + values ( "0.025782, 0.301558, 0.634384, 1.250443, 2.482564",\ + "0.030125, 0.302556, 0.636324, 1.250443, 2.482564",\ + "0.042888, 0.304795, 0.636360, 1.250443, 2.482564",\ + "0.054816, 0.308050, 0.636463, 1.250443, 2.482564",\ + "0.130787, 0.346172, 0.642713, 1.252991, 2.482564"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011"); + values ( "0.068909, 0.173502, 0.284792, 0.488757, 0.896689",\ + "0.156317, 0.260820, 0.372072, 0.576063, 0.984042",\ + "0.236694, 0.341152, 0.452099, 0.656091, 1.064074",\ + "0.293432, 0.398701, 0.509642, 0.713335, 1.120722",\ + "0.587713, 0.702042, 0.813273, 1.016348, 1.422499"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011"); + values ( "0.025687, 0.188435, 0.388543, 0.760465, 1.504307",\ + "0.025687, 0.188583, 0.389046, 0.760465, 1.504307",\ + "0.026721, 0.188583, 0.389046, 0.760465, 1.504307",\ + "0.028743, 0.188583, 0.389046, 0.760465, 1.504307",\ + "0.047139, 0.192514, 0.389046, 0.760465, 1.504587"); + } + + } /* end of arc clk_ast_tlul_i_sprom_rm_o[1]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011"); + values ( "0.049435, 0.202151, 0.377283, 0.699803, 1.344843",\ + "0.135820, 0.289326, 0.464387, 0.786517, 1.430777",\ + "0.219334, 0.377453, 0.552342, 0.874138, 1.517732",\ + "0.277559, 0.441846, 0.616457, 0.938052, 1.581241",\ + "0.579442, 0.791721, 0.966837, 1.286790, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011"); + values ( "0.025782, 0.301558, 0.634384, 1.249210, 2.473548",\ + "0.030125, 0.302556, 0.636324, 1.249210, 2.473548",\ + "0.042888, 0.304795, 0.636360, 1.249285, 2.473548",\ + "0.054816, 0.308050, 0.636463, 1.250030, 2.473548",\ + "0.130787, 0.346172, 0.642713, 1.252991, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011"); + values ( "0.068909, 0.173502, 0.284792, 0.488757, 0.896689",\ + "0.156317, 0.260820, 0.372072, 0.576063, 0.984042",\ + "0.236694, 0.341152, 0.452099, 0.656091, 1.064074",\ + "0.293432, 0.398701, 0.509642, 0.713335, 1.120722",\ + "0.587713, 0.702042, 0.813273, 1.016348, 1.422499"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011"); + values ( "0.025687, 0.187631, 0.387035, 0.758233, 1.500630",\ + "0.025687, 0.187631, 0.387035, 0.758233, 1.500630",\ + "0.026721, 0.187631, 0.387035, 0.758233, 1.500630",\ + "0.028743, 0.188240, 0.387493, 0.759136, 1.502422",\ + "0.047139, 0.192514, 0.387566, 0.759907, 1.504587"); + } + + } /* end of arc clk_ast_tlul_i_sprom_rm_o[1]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025782, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.216765, 0.170836, 0.140637, 0.129293, 0.142978",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025687, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.251111, 0.175790, 0.107631, 0.084664, 0.147578",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_sprom_rm_o[1]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025782, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.148693, -0.106276, -0.071789, -0.032365, 0.273682",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025687, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.164267, -0.098352, -0.040693, 0.001268, 0.221876",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_sprom_rm_o[1]_hldr*/ + +} /* end of pin sprom_rm_o[1] */ + +pin("sprom_rm_o[0]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002026 ; + + /* Other user defined attributes. */ + original_pin : sprom_rm_o[0]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011"); + values ( "0.048221, 0.201247, 0.376603, 0.699350, 1.344843",\ + "0.134540, 0.288422, 0.463709, 0.786065, 1.430777",\ + "0.217754, 0.376549, 0.551664, 0.873687, 1.517732",\ + "0.275678, 0.440944, 0.615780, 0.937600, 1.581241",\ + "0.575742, 0.790814, 0.966163, 1.286341, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011"); + values ( "0.024153, 0.299842, 0.633087, 1.249579, 2.482563",\ + "0.028666, 0.300830, 0.635034, 1.249579, 2.482563",\ + "0.041608, 0.303085, 0.635070, 1.249579, 2.482563",\ + "0.053514, 0.306363, 0.635172, 1.249579, 2.482563",\ + "0.129154, 0.344706, 0.641428, 1.252134, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011"); + values ( "0.067848, 0.172946, 0.284382, 0.488491, 0.896709",\ + "0.155259, 0.260265, 0.371663, 0.575796, 0.984062",\ + "0.235619, 0.340599, 0.451690, 0.655824, 1.064094",\ + "0.292315, 0.398147, 0.509233, 0.713069, 1.120741",\ + "0.586152, 0.701486, 0.812865, 1.016083, 1.422518"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011"); + values ( "0.024592, 0.187440, 0.387796, 0.759979, 1.504343",\ + "0.024592, 0.187585, 0.388300, 0.759979, 1.504343",\ + "0.025674, 0.187585, 0.388300, 0.759979, 1.504343",\ + "0.027742, 0.187585, 0.388300, 0.759979, 1.504343",\ + "0.046348, 0.191554, 0.388300, 0.759979, 1.504623"); + } + + } /* end of arc clk_ast_tlul_i_sprom_rm_o[0]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011"); + values ( "0.048221, 0.201247, 0.376603, 0.699350, 1.344843",\ + "0.134540, 0.288422, 0.463709, 0.786065, 1.430777",\ + "0.217754, 0.376549, 0.551664, 0.873687, 1.517732",\ + "0.275678, 0.440944, 0.615780, 0.937600, 1.581241",\ + "0.575742, 0.790814, 0.966163, 1.286341, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011"); + values ( "0.024153, 0.299842, 0.633087, 1.248350, 2.473548",\ + "0.028666, 0.300830, 0.635034, 1.248350, 2.473548",\ + "0.041608, 0.303085, 0.635070, 1.248425, 2.473548",\ + "0.053514, 0.306363, 0.635172, 1.249169, 2.473548",\ + "0.129154, 0.344706, 0.641428, 1.252134, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011"); + values ( "0.067848, 0.172946, 0.284382, 0.488491, 0.896709",\ + "0.155259, 0.260265, 0.371663, 0.575796, 0.984062",\ + "0.235619, 0.340599, 0.451690, 0.655824, 1.064094",\ + "0.292315, 0.398147, 0.509233, 0.713069, 1.120741",\ + "0.586152, 0.701486, 0.812865, 1.016083, 1.422518"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011"); + values ( "0.024592, 0.186641, 0.386289, 0.757748, 1.500666",\ + "0.024592, 0.186641, 0.386289, 0.757748, 1.500666",\ + "0.025674, 0.186641, 0.386289, 0.757748, 1.500666",\ + "0.027742, 0.187251, 0.386746, 0.758650, 1.502457",\ + "0.046348, 0.191554, 0.386818, 0.759420, 1.504623"); + } + + } /* end of arc clk_ast_tlul_i_sprom_rm_o[0]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.216011, 0.170082, 0.139882, 0.128539, 0.142224",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024592, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.250613, 0.175291, 0.107132, 0.084165, 0.147079",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_sprom_rm_o[0]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.147938, -0.105521, -0.071034, -0.031611, 0.274436",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024592, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.163769, -0.097854, -0.040195, 0.001766, 0.222374",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_sprom_rm_o[0]_hldr*/ + +} /* end of pin sprom_rm_o[0] */ +} /* end of bus sprom_rm_o */ +bus ( dft_scan_md_o ) { + + bus_type : BUS4_type6 ; + direction : output ; + +pin("dft_scan_md_o[3]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.161713 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.003517 ; + + /* Other user defined attributes. */ + original_pin : dft_scan_md_o[3]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003517, 0.023292, 0.043066, 0.082615, 0.161713"); + values ( "0.133436, 0.291149, 0.448015, 0.761558, 1.388635",\ + "0.217239, 0.374877, 0.531734, 0.845677, 1.473578",\ + "0.292722, 0.450435, 0.607370, 0.921610, 1.550114",\ + "0.345414, 0.503270, 0.660387, 0.974530, 1.602811",\ + "0.613422, 0.771515, 0.928749, 1.242027, 1.868510"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003517, 0.023292, 0.043066, 0.082615, 0.161713"); + values ( "0.066308, 0.363809, 0.664826, 1.265395, 2.466601",\ + "0.066379, 0.363809, 0.664826, 1.265395, 2.466601",\ + "0.066379, 0.364085, 0.666054, 1.266438, 2.466601",\ + "0.066379, 0.364085, 0.666054, 1.266438, 2.466601",\ + "0.066665, 0.364152, 0.666054, 1.266438, 2.466601"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003517, 0.023292, 0.043066, 0.082615, 0.161713"); + values ( "0.114669, 0.217180, 0.316410, 0.514247, 0.909878",\ + "0.195349, 0.297552, 0.396278, 0.593860, 0.989031",\ + "0.275060, 0.377342, 0.475886, 0.672942, 1.067052",\ + "0.331983, 0.434648, 0.533289, 0.730356, 1.124476",\ + "0.627120, 0.733734, 0.832492, 1.029975, 1.424937"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003517, 0.023292, 0.043066, 0.082615, 0.161713"); + values ( "0.047862, 0.221071, 0.402991, 0.762572, 1.481727",\ + "0.048050, 0.221071, 0.402991, 0.762572, 1.484038",\ + "0.048841, 0.221071, 0.402991, 0.762572, 1.484038",\ + "0.050174, 0.221071, 0.402991, 0.762572, 1.484038",\ + "0.063454, 0.223134, 0.402991, 0.763435, 1.490666"); + } + + } /* end of arc clk_ast_tlul_i_dft_scan_md_o[3]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003517, 0.023292, 0.043066, 0.082615, 0.161713"); + values ( "0.133312, 0.291022, 0.447820, 0.761354, 1.388420",\ + "0.217237, 0.374875, 0.531731, 0.845675, 1.473578",\ + "0.292688, 0.450412, 0.607364, 0.921580, 1.550030",\ + "0.345261, 0.502988, 0.659849, 0.973849, 1.601865",\ + "0.613232, 0.771275, 0.928568, 1.241507, 1.867283"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003517, 0.023292, 0.043066, 0.082615, 0.161713"); + values ( "0.066239, 0.363467, 0.663180, 1.263144, 2.462725",\ + "0.066251, 0.363467, 0.663180, 1.263144, 2.462725",\ + "0.066251, 0.363585, 0.663361, 1.263144, 2.462725",\ + "0.066330, 0.363585, 0.663361, 1.263144, 2.462725",\ + "0.066585, 0.363585, 0.663361, 1.263144, 2.462725"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003517, 0.023292, 0.043066, 0.082615, 0.161713"); + values ( "0.114669, 0.217179, 0.316406, 0.514185, 0.909696",\ + "0.195349, 0.297552, 0.396278, 0.593860, 0.989031",\ + "0.275060, 0.377342, 0.475886, 0.672905, 1.066937",\ + "0.331983, 0.434648, 0.533289, 0.730334, 1.124409",\ + "0.627120, 0.733671, 0.832318, 1.029654, 1.424330"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003517, 0.023292, 0.043066, 0.082615, 0.161713"); + values ( "0.047860, 0.219783, 0.399450, 0.759952, 1.480082",\ + "0.047983, 0.219783, 0.399450, 0.759952, 1.480442",\ + "0.048841, 0.219783, 0.399450, 0.759952, 1.480924",\ + "0.050169, 0.219999, 0.399514, 0.759952, 1.480924",\ + "0.063451, 0.222984, 0.400129, 0.761188, 1.483772"); + } + + } /* end of arc clk_ast_tlul_i_dft_scan_md_o[3]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.066308, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.460686, 0.485165, 0.562988, 0.630573, 1.061400",\ + "0.481673, 0.506153, 0.583976, 0.651561, 1.082387",\ + "0.534849, 0.559328, 0.637151, 0.704736, 1.135562",\ + "0.617824, 0.642303, 0.720126, 0.787711, 1.218538",\ + "0.947556, 0.972173, 1.049996, 1.117581, 1.548407"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.047862, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.457000, 0.374371, 0.299229, 0.265511, 0.232819",\ + "0.477245, 0.394617, 0.319474, 0.285756, 0.253064",\ + "0.547749, 0.465121, 0.389978, 0.356260, 0.323568",\ + "0.640993, 0.558364, 0.483222, 0.449504, 0.416811",\ + "1.063337, 0.980709, 0.905566, 0.871848, 0.839156"); + } + + } /* end of arc clk_ast_tlul_i_dft_scan_md_o[3]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.066239, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.335865, -0.312869, -0.277184, -0.251910, -0.123825",\ + "-0.356827, -0.333831, -0.298147, -0.272873, -0.144787",\ + "-0.410399, -0.387403, -0.351719, -0.326444, -0.198359",\ + "-0.492968, -0.469972, -0.434287, -0.409013, -0.280927",\ + "-0.820618, -0.797635, -0.761950, -0.736676, -0.608590"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.047860, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.242066, -0.200653, -0.167936, -0.130741, 0.097416",\ + "-0.262424, -0.221011, -0.188294, -0.151099, 0.077058",\ + "-0.336018, -0.294606, -0.261888, -0.224693, 0.003464",\ + "-0.427308, -0.385895, -0.353178, -0.315983, -0.087826",\ + "-0.831346, -0.789933, -0.757216, -0.720060, -0.491903"); + } + + } /* end of arc clk_ast_tlul_i_dft_scan_md_o[3]_hldr*/ + +} /* end of pin dft_scan_md_o[3] */ + +pin("dft_scan_md_o[2]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.158177 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002946 ; + + /* Other user defined attributes. */ + original_pin : dft_scan_md_o[2]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002946, 0.017242, 0.041754, 0.080562, 0.158177"); + values ( "0.089185, 0.209900, 0.411017, 0.726230, 1.356390",\ + "0.176530, 0.297275, 0.498423, 0.814441, 1.446276",\ + "0.269642, 0.392143, 0.593017, 0.908861, 1.540369",\ + "0.337617, 0.463374, 0.664040, 0.979619, 1.610599",\ + "0.699386, 0.858557, 1.060886, 1.375366, 2.003839"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002946, 0.017242, 0.041754, 0.080562, 0.158177"); + values ( "0.068736, 0.284281, 0.666318, 1.270003, 2.477274",\ + "0.069806, 0.284281, 0.666318, 1.270003, 2.477274",\ + "0.079825, 0.285836, 0.666318, 1.270003, 2.477473",\ + "0.092727, 0.288939, 0.666318, 1.270003, 2.478527",\ + "0.183999, 0.330916, 0.673768, 1.274123, 2.479640"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002946, 0.017242, 0.041754, 0.080562, 0.158177"); + values ( "0.114548, 0.198291, 0.327841, 0.529548, 0.932669",\ + "0.202420, 0.286233, 0.415819, 0.617532, 1.020660",\ + "0.283719, 0.367201, 0.496624, 0.698334, 1.101477",\ + "0.341605, 0.425242, 0.554619, 0.756211, 1.159115",\ + "0.647553, 0.733958, 0.863532, 1.064748, 1.466840"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002946, 0.017242, 0.041754, 0.080562, 0.158177"); + values ( "0.059272, 0.178664, 0.407996, 0.776762, 1.514808",\ + "0.059349, 0.178981, 0.409509, 0.776762, 1.514808",\ + "0.059349, 0.178981, 0.409796, 0.777827, 1.514808",\ + "0.059903, 0.178981, 0.409796, 0.777827, 1.514808",\ + "0.069603, 0.181400, 0.409796, 0.777827, 1.514808"); + } + + } /* end of arc clk_ast_tlul_i_dft_scan_md_o[2]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002946, 0.017242, 0.041754, 0.080562, 0.158177"); + values ( "0.089178, 0.209899, 0.411017, 0.726223, 1.356368",\ + "0.176530, 0.297223, 0.498130, 0.813320, 1.443459",\ + "0.269641, 0.392139, 0.592998, 0.908848, 1.540369",\ + "0.337615, 0.463370, 0.664029, 0.979611, 1.610599",\ + "0.699305, 0.858522, 1.060836, 1.375332, 2.003839"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002946, 0.017242, 0.041754, 0.080562, 0.158177"); + values ( "0.068736, 0.284090, 0.664476, 1.268786, 2.477107",\ + "0.069799, 0.284090, 0.664476, 1.268786, 2.477170",\ + "0.079823, 0.285806, 0.664476, 1.268786, 2.477473",\ + "0.092726, 0.288922, 0.664476, 1.268786, 2.478218",\ + "0.183999, 0.330234, 0.669979, 1.271116, 2.478674"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002946, 0.017242, 0.041754, 0.080562, 0.158177"); + values ( "0.114547, 0.198291, 0.327841, 0.529547, 0.932665",\ + "0.202385, 0.286186, 0.415735, 0.617437, 1.020546",\ + "0.283468, 0.366941, 0.496348, 0.698061, 1.101213",\ + "0.341452, 0.425085, 0.554450, 0.756012, 1.158853",\ + "0.647498, 0.733909, 0.863481, 1.064711, 1.466833"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002946, 0.017242, 0.041754, 0.080562, 0.158177"); + values ( "0.059268, 0.178282, 0.407986, 0.775351, 1.510125",\ + "0.059268, 0.178282, 0.408103, 0.775351, 1.510125",\ + "0.059268, 0.178282, 0.408103, 0.775351, 1.510553",\ + "0.059897, 0.178402, 0.408103, 0.775351, 1.510553",\ + "0.069562, 0.181271, 0.408103, 0.775351, 1.510553"); + } + + } /* end of arc clk_ast_tlul_i_dft_scan_md_o[2]_redg_min*/ + +} /* end of pin dft_scan_md_o[2] */ + +pin("dft_scan_md_o[1]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.158177 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002940 ; + + /* Other user defined attributes. */ + original_pin : dft_scan_md_o[1]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002940, 0.017235, 0.041749, 0.080558, 0.158177"); + values ( "0.089114, 0.209844, 0.410975, 0.726203, 1.356391",\ + "0.176459, 0.297219, 0.498381, 0.814414, 1.446276",\ + "0.269560, 0.392087, 0.592975, 0.908833, 1.540369",\ + "0.337521, 0.463318, 0.663998, 0.979591, 1.610599",\ + "0.699205, 0.858501, 1.060843, 1.375339, 2.003839"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002940, 0.017235, 0.041749, 0.080558, 0.158177"); + values ( "0.068629, 0.284175, 0.666239, 1.269949, 2.477274",\ + "0.069702, 0.284175, 0.666239, 1.269949, 2.477274",\ + "0.079734, 0.285730, 0.666239, 1.269949, 2.477474",\ + "0.092637, 0.288835, 0.666239, 1.269949, 2.478527",\ + "0.183880, 0.330821, 0.673696, 1.274070, 2.479641"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002940, 0.017235, 0.041749, 0.080558, 0.158177"); + values ( "0.114532, 0.198282, 0.327841, 0.529557, 0.932695",\ + "0.202404, 0.286224, 0.415819, 0.617541, 1.020687",\ + "0.283703, 0.367192, 0.496624, 0.698343, 1.101503",\ + "0.341588, 0.425233, 0.554619, 0.756220, 1.159141",\ + "0.647534, 0.733949, 0.863532, 1.064757, 1.466866"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002940, 0.017235, 0.041749, 0.080558, 0.158177"); + values ( "0.059254, 0.178648, 0.407996, 0.776778, 1.514857",\ + "0.059330, 0.178965, 0.409508, 0.776778, 1.514857",\ + "0.059330, 0.178965, 0.409796, 0.777843, 1.514857",\ + "0.059885, 0.178965, 0.409796, 0.777843, 1.514857",\ + "0.069589, 0.181384, 0.409796, 0.777843, 1.514857"); + } + + } /* end of arc clk_ast_tlul_i_dft_scan_md_o[1]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002940, 0.017235, 0.041749, 0.080558, 0.158177"); + values ( "0.089108, 0.209843, 0.410975, 0.726196, 1.356369",\ + "0.176459, 0.297167, 0.498088, 0.813292, 1.443459",\ + "0.269559, 0.392083, 0.592956, 0.908820, 1.540369",\ + "0.337519, 0.463314, 0.663987, 0.979583, 1.610599",\ + "0.699124, 0.858466, 1.060793, 1.375304, 2.003839"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002940, 0.017235, 0.041749, 0.080558, 0.158177"); + values ( "0.068628, 0.283984, 0.664398, 1.268733, 2.477107",\ + "0.069695, 0.283984, 0.664398, 1.268733, 2.477171",\ + "0.079731, 0.285701, 0.664398, 1.268733, 2.477474",\ + "0.092635, 0.288817, 0.664398, 1.268733, 2.478218",\ + "0.183880, 0.330139, 0.669908, 1.271063, 2.478675"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002940, 0.017235, 0.041749, 0.080558, 0.158177"); + values ( "0.114530, 0.198282, 0.327841, 0.529556, 0.932692",\ + "0.202368, 0.286177, 0.415735, 0.617446, 1.020573",\ + "0.283452, 0.366932, 0.496348, 0.698070, 1.101240",\ + "0.341435, 0.425076, 0.554450, 0.756020, 1.158880",\ + "0.647479, 0.733900, 0.863481, 1.064720, 1.466859"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002940, 0.017235, 0.041749, 0.080558, 0.158177"); + values ( "0.059249, 0.178266, 0.407986, 0.775367, 1.510173",\ + "0.059249, 0.178266, 0.408103, 0.775367, 1.510173",\ + "0.059249, 0.178266, 0.408103, 0.775367, 1.510602",\ + "0.059879, 0.178385, 0.408103, 0.775367, 1.510602",\ + "0.069548, 0.181255, 0.408103, 0.775367, 1.510602"); + } + + } /* end of arc clk_ast_tlul_i_dft_scan_md_o[1]_redg_min*/ + +} /* end of pin dft_scan_md_o[1] */ + +pin("dft_scan_md_o[0]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.161713 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.003291 ; + + /* Other user defined attributes. */ + original_pin : dft_scan_md_o[0]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003291, 0.023093, 0.042896, 0.082502, 0.161713"); + values ( "0.131615, 0.289575, 0.446666, 0.760660, 1.388635",\ + "0.215420, 0.373304, 0.530386, 0.844778, 1.473578",\ + "0.290903, 0.448861, 0.606021, 0.920710, 1.550114",\ + "0.343593, 0.501694, 0.659036, 0.973630, 1.602811",\ + "0.611596, 0.769938, 0.927397, 1.241129, 1.868510"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003291, 0.023093, 0.042896, 0.082502, 0.161713"); + values ( "0.062950, 0.360790, 0.662238, 1.263674, 2.466600",\ + "0.063013, 0.360790, 0.662238, 1.263674, 2.466600",\ + "0.063013, 0.361056, 0.663457, 1.264718, 2.466600",\ + "0.063013, 0.361056, 0.663457, 1.264718, 2.466600",\ + "0.063304, 0.361135, 0.663457, 1.264718, 2.466600"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003291, 0.023093, 0.042896, 0.082502, 0.161713"); + values ( "0.113407, 0.216311, 0.315683, 0.513806, 0.910003",\ + "0.194085, 0.296687, 0.395555, 0.593419, 0.989157",\ + "0.273778, 0.376478, 0.475164, 0.672502, 1.067177",\ + "0.330670, 0.433783, 0.532566, 0.729916, 1.124601",\ + "0.625514, 0.732868, 0.831768, 1.029534, 1.425062"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003291, 0.023093, 0.042896, 0.082502, 0.161713"); + values ( "0.046113, 0.219478, 0.401657, 0.761769, 1.481954",\ + "0.046300, 0.219478, 0.401657, 0.761769, 1.484267",\ + "0.047120, 0.219478, 0.401657, 0.761769, 1.484267",\ + "0.048485, 0.219478, 0.401657, 0.761769, 1.484267",\ + "0.061963, 0.221582, 0.401657, 0.762623, 1.490896"); + } + + } /* end of arc clk_ast_tlul_i_dft_scan_md_o[0]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003291, 0.023093, 0.042896, 0.082502, 0.161713"); + values ( "0.131490, 0.289449, 0.446472, 0.760456, 1.388420",\ + "0.215418, 0.373302, 0.530383, 0.844776, 1.473578",\ + "0.290869, 0.448838, 0.606015, 0.920679, 1.550029",\ + "0.343439, 0.501415, 0.658500, 0.972949, 1.601865",\ + "0.611409, 0.769697, 0.927216, 1.240610, 1.867283"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003291, 0.023093, 0.042896, 0.082502, 0.161713"); + values ( "0.062879, 0.360460, 0.660603, 1.261425, 2.462725",\ + "0.062899, 0.360460, 0.660603, 1.261425, 2.462725",\ + "0.062899, 0.360578, 0.660783, 1.261425, 2.462725",\ + "0.062968, 0.360578, 0.660783, 1.261425, 2.462725",\ + "0.063222, 0.360578, 0.660783, 1.261425, 2.462725"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003291, 0.023093, 0.042896, 0.082502, 0.161713"); + values ( "0.113407, 0.216309, 0.315678, 0.513743, 0.909821",\ + "0.194085, 0.296687, 0.395555, 0.593419, 0.989157",\ + "0.273778, 0.376478, 0.475164, 0.672465, 1.067062",\ + "0.330670, 0.433783, 0.532566, 0.729894, 1.124533",\ + "0.625514, 0.732807, 0.831595, 1.029214, 1.424455"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003291, 0.023093, 0.042896, 0.082502, 0.161713"); + values ( "0.046112, 0.218208, 0.398133, 0.759147, 1.480310",\ + "0.046235, 0.218208, 0.398133, 0.759147, 1.480670",\ + "0.047116, 0.218208, 0.398133, 0.759147, 1.481152",\ + "0.048480, 0.218425, 0.398198, 0.759147, 1.481152",\ + "0.061948, 0.221432, 0.398830, 0.760382, 1.484000"); + } + + } /* end of arc clk_ast_tlul_i_dft_scan_md_o[0]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.062950, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.468253, 0.492732, 0.570555, 0.638140, 1.068967",\ + "0.490044, 0.514523, 0.592346, 0.659931, 1.090757",\ + "0.545368, 0.569847, 0.647670, 0.715255, 1.146082",\ + "0.634688, 0.659168, 0.736991, 0.804576, 1.235402",\ + "1.017271, 1.041743, 1.119566, 1.187151, 1.617977"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.046113, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.459602, 0.376973, 0.301830, 0.268113, 0.235420",\ + "0.477883, 0.395254, 0.320112, 0.286394, 0.253701",\ + "0.549719, 0.467091, 0.391948, 0.358230, 0.325538",\ + "0.644311, 0.561683, 0.486540, 0.452822, 0.420130",\ + "1.067339, 0.984711, 0.909568, 0.875850, 0.843158"); + } + + } /* end of arc clk_ast_tlul_i_dft_scan_md_o[0]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.062879, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.343432, -0.320436, -0.284752, -0.259478, -0.131392",\ + "-0.365195, -0.342199, -0.306515, -0.281240, -0.153155",\ + "-0.420715, -0.397719, -0.362035, -0.336760, -0.208675",\ + "-0.509827, -0.486831, -0.451147, -0.425873, -0.297787",\ + "-0.891088, -0.868095, -0.832410, -0.807136, -0.679050"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.046112, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.244757, -0.203344, -0.170627, -0.133432, 0.094725",\ + "-0.263038, -0.221625, -0.188908, -0.151713, 0.076444",\ + "-0.337776, -0.296363, -0.263646, -0.226451, 0.001706",\ + "-0.430900, -0.389488, -0.356770, -0.319575, -0.091418",\ + "-0.836348, -0.794936, -0.762218, -0.725057, -0.496900"); + } + + } /* end of arc clk_ast_tlul_i_dft_scan_md_o[0]_hldr*/ + +} /* end of pin dft_scan_md_o[0] */ +} /* end of bus dft_scan_md_o */ + +pin("scan_shift_en_o") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.095084 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.028179 ; + + /* Other user defined attributes. */ + original_pin : scan_shift_en_o; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : recovery_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.195118, 0.455354, 0.766211, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.532219, 0.489613, 0.431727, 0.435127, 0.476450",\ + "0.639994, 0.597388, 0.539502, 0.542902, 0.584225",\ + "0.783455, 0.740849, 0.682963, 0.686363, 0.727686",\ + "0.930263, 0.887658, 0.829771, 0.833171, 0.874494",\ + "1.623874, 1.581268, 1.523381, 1.526781, 1.568104"); + } + + } /* end of arc clk_ast_alert_i_scan_shift_en_o_recrr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : removal_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.195118, 0.455354, 0.746802, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.043626, 0.100485, 0.237779, 0.265545, 0.602978",\ + "-0.038691, 0.018168, 0.155463, 0.183228, 0.520661",\ + "-0.121016, -0.064151, 0.072977, 0.100718, 0.437847",\ + "-0.190085, -0.133213, 0.003667, 0.031370, 0.368047",\ + "-0.499886, -0.442913, -0.307440, -0.279961, 0.053979"); + } + + } /* end of arc clk_ast_alert_i_scan_shift_en_o_remrr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : setup_rising ; + clock_gating_flag : true ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.195118, 0.455354, 0.766211, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.063826, 0.062652, 0.129143, 0.282266, 0.638582",\ + "0.144516, 0.122873, 0.153635, 0.250761, 0.490135",\ + "0.243845, 0.203218, 0.197002, 0.225868, 0.314993",\ + "0.333420, 0.283466, 0.260028, 0.260578, 0.289579",\ + "0.742571, 0.680072, 0.640181, 0.639634, 0.684785"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.195118, 0.484230, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.069804, -0.018648, -0.111764, -0.244874, -0.513274",\ + "0.147065, 0.058673, -0.032069, -0.165383, -0.437145",\ + "0.257633, 0.169188, 0.076752, -0.058192, -0.332590",\ + "0.419789, 0.332087, 0.238963, 0.102061, -0.177084",\ + "0.794358, 0.708802, 0.615035, 0.473837, 0.183265"); + } + + } /* end of arc clk_ast_ext_i_scan_shift_en_o_cgsr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : hold_rising ; + clock_gating_flag : true ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.195118, 0.455354, 0.746802, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.041482, 0.004889, 0.044867, 0.102673, 0.219769",\ + "-0.121636, -0.074743, -0.032444, 0.026924, 0.145736",\ + "-0.213199, -0.163583, -0.120926, -0.060090, 0.062464",\ + "-0.289736, -0.238766, -0.195667, -0.134080, -0.009915",\ + "-0.654569, -0.601430, -0.555559, -0.492609, -0.367822"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.195118, 0.476372, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.044121, 0.037282, 0.129537, 0.261976, 0.529485",\ + "-0.122275, -0.038844, 0.049184, 0.181641, 0.454147",\ + "-0.228703, -0.144549, -0.055160, 0.079110, 0.355165",\ + "-0.387423, -0.304473, -0.214026, -0.077712, 0.202895",\ + "-0.744719, -0.665813, -0.573547, -0.433021, -0.142598"); + } + + } /* end of arc clk_ast_ext_i_scan_shift_en_o_cghr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084"); + values ( "380000.437500, 380000.468750, 380000.531250, 380000.812500, 380001.312500",\ + "380000.531250, 380000.562500, 380000.625000, 380000.906250, 380001.406250",\ + "380000.593750, 380000.625000, 380000.687500, 380000.968750, 380001.468750",\ + "380000.656250, 380000.687500, 380000.750000, 380001.031250, 380001.531250",\ + "380000.968750, 380001.000000, 380001.062500, 380001.343750, 380001.843750"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084"); + values ( "0.750971, 0.815816, 0.968419, 1.480978, 2.464965",\ + "0.750971, 0.815816, 0.968419, 1.480978, 2.464965",\ + "0.750971, 0.815816, 0.968419, 1.480978, 2.464965",\ + "0.750971, 0.815816, 0.968419, 1.480978, 2.464965",\ + "0.750971, 0.815816, 0.968419, 1.480978, 2.464965"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084"); + values ( "380001.750000, 380001.781250, 380001.843750, 380002.031250, 380002.375000",\ + "380001.843750, 380001.875000, 380001.937500, 380002.125000, 380002.468750",\ + "380001.937500, 380001.968750, 380002.031250, 380002.218750, 380002.562500",\ + "380002.000000, 380002.031250, 380002.093750, 380002.281250, 380002.625000",\ + "380002.343750, 380002.375000, 380002.437500, 380002.625000, 380002.968750"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084"); + values ( "0.476972, 0.520642, 0.623430, 0.968675, 1.632439",\ + "0.476972, 0.520642, 0.623430, 0.968675, 1.632439",\ + "0.476984, 0.520655, 0.623442, 0.968683, 1.632439",\ + "0.477092, 0.520773, 0.623551, 0.968760, 1.632439",\ + "0.477240, 0.520936, 0.623729, 0.968990, 1.632439"); + } + + } /* end of arc clk_ast_tlul_i_scan_shift_en_o_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084"); + values ( "0.567867, 0.601968, 0.682377, 0.952454, 1.470934",\ + "0.656009, 0.690105, 0.770491, 1.040492, 1.558825",\ + "0.750333, 0.784422, 0.864790, 1.134732, 1.652952",\ + "0.817746, 0.851834, 0.932210, 1.202178, 1.720448",\ + "1.177034, 1.211190, 1.291747, 1.562319, 2.081752"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084"); + values ( "0.742023, 0.806942, 0.960129, 1.473159, 2.454133",\ + "0.742023, 0.806942, 0.960129, 1.473159, 2.454133",\ + "0.742023, 0.806942, 0.960129, 1.473554, 2.458020",\ + "0.742023, 0.806942, 0.960129, 1.474655, 2.462414",\ + "0.742023, 0.806942, 0.960129, 1.474655, 2.462414"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084"); + values ( "0.436555, 0.460383, 0.516602, 0.705431, 1.067936",\ + "0.524364, 0.548192, 0.604409, 0.793229, 1.155716",\ + "0.605651, 0.629479, 0.685698, 0.874530, 1.237040",\ + "0.663776, 0.687602, 0.743831, 0.932696, 1.295270",\ + "0.971918, 0.995743, 1.051944, 1.240713, 1.603103"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084"); + values ( "0.476372, 0.519944, 0.622887, 0.968653, 1.631455",\ + "0.476372, 0.519944, 0.622887, 0.968653, 1.631455",\ + "0.476372, 0.519944, 0.622887, 0.968653, 1.631461",\ + "0.476372, 0.519944, 0.622887, 0.968653, 1.631478",\ + "0.476373, 0.519944, 0.622887, 0.968653, 1.631806"); + } + + } /* end of arc clk_ast_tlul_i_scan_shift_en_o_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : recovery_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.195118, 0.455354, 0.766211, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "1.025280, 0.973708, 0.938980, 0.927998, 0.968803",\ + "1.133724, 1.082152, 1.047424, 1.036442, 1.077247",\ + "1.276742, 1.225171, 1.190443, 1.179460, 1.220266",\ + "1.421700, 1.370129, 1.335400, 1.324418, 1.365223",\ + "2.112985, 2.061414, 2.026685, 2.015703, 2.056509"); + } + + } /* end of arc clk_ast_tlul_i_scan_shift_en_o_recrr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : removal_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.195118, 0.455354, 0.746802, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.484807, -0.401976, -0.317025, -0.255738, 0.062771",\ + "-0.593251, -0.510420, -0.425469, -0.364182, -0.045673",\ + "-0.735922, -0.653091, -0.568140, -0.506853, -0.188344",\ + "-0.871661, -0.788831, -0.703879, -0.642593, -0.324084",\ + "-1.567978, -1.485147, -1.400195, -1.338909, -1.020400"); + } + + } /* end of arc clk_ast_tlul_i_scan_shift_en_o_remrr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + clock_gating_flag : true ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.195118, 0.455354, 0.766211, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.500052, 0.464257, 0.467454, 0.481872, 0.641062",\ + "0.608496, 0.572702, 0.575898, 0.590317, 0.749506",\ + "0.751349, 0.715408, 0.718319, 0.732500, 0.890238",\ + "0.895828, 0.859887, 0.862797, 0.876979, 1.034717",\ + "1.584854, 1.547746, 1.548384, 1.560677, 1.706875"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.195118, 0.484230, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.472376, 0.383961, 0.292457, 0.226602, -0.114540",\ + "0.571622, 0.483207, 0.391702, 0.325848, -0.015294",\ + "0.718823, 0.630408, 0.538891, 0.473029, 0.131864",\ + "0.967954, 0.879538, 0.787986, 0.722105, 0.380872",\ + "1.461814, 1.373393, 1.281717, 1.215763, 0.874287"); + } + + } /* end of arc clk_ast_tlul_i_scan_shift_en_o_cgsr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + clock_gating_flag : true ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.195118, 0.455354, 0.746802, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.471383, -0.422460, -0.379894, -0.349813, -0.197830",\ + "-0.579827, -0.530904, -0.488339, -0.458257, -0.306274",\ + "-0.722620, -0.673676, -0.631108, -0.601022, -0.449003",\ + "-0.858078, -0.809134, -0.766565, -0.736479, -0.584461",\ + "-1.555647, -1.506536, -1.463946, -1.433827, -1.281521"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.195118, 0.476372, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.447062, -0.363296, -0.274639, -0.209836, 0.132805",\ + "-0.546307, -0.462542, -0.373884, -0.309082, 0.033560",\ + "-0.689363, -0.605598, -0.516940, -0.452138, -0.109496",\ + "-0.942607, -0.858821, -0.770125, -0.705296, -0.362529",\ + "-1.436381, -1.352539, -1.263740, -1.198841, -0.855737"); + } + + } /* end of arc clk_ast_tlul_i_scan_shift_en_o_cghr*/ + + timing () { + related_pin : "padmux2ast_i[2]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084"); + values ( "0.489833, 0.523915, 0.604311, 0.874343, 1.392737",\ + "0.566174, 0.600431, 0.681298, 0.952915, 1.474352",\ + "0.660833, 0.694982, 0.775530, 1.046072, 1.565447",\ + "0.820966, 0.855139, 0.935773, 1.206609, 1.726547",\ + "1.095138, 1.129115, 1.209400, 1.479059, 1.996736"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084"); + values ( "0.766211, 0.830301, 0.980244, 1.483872, 2.450712",\ + "0.766211, 0.830301, 0.980244, 1.483872, 2.456399",\ + "0.766211, 0.830301, 0.980244, 1.483872, 2.457642",\ + "0.766211, 0.830301, 0.980244, 1.483872, 2.465531",\ + "0.766211, 0.830301, 0.980244, 1.483872, 2.465531"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084"); + values ( "0.331095, 0.354971, 0.411113, 0.599682, 0.961689",\ + "0.422338, 0.446186, 0.502618, 0.692160, 1.056035",\ + "0.529474, 0.553262, 0.609349, 0.797734, 1.159388",\ + "0.719234, 0.743081, 0.799295, 0.988106, 1.350577",\ + "1.047647, 1.071864, 1.127881, 1.316028, 1.677225"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084"); + values ( "0.484230, 0.528601, 0.631276, 0.976140, 1.638195",\ + "0.484230, 0.528601, 0.631276, 0.976140, 1.638195",\ + "0.484230, 0.528601, 0.631276, 0.976140, 1.638195",\ + "0.484230, 0.528601, 0.631276, 0.976140, 1.638195",\ + "0.491280, 0.530601, 0.632503, 0.976140, 1.638195"); + } + + } /* end of arc padmux2ast_i[2]_scan_shift_en_o_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[2]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084"); + values ( "0.489833, 0.523915, 0.604311, 0.874343, 1.392737",\ + "0.566174, 0.600431, 0.681298, 0.952915, 1.474352",\ + "0.660833, 0.694982, 0.775530, 1.046072, 1.565447",\ + "0.820966, 0.855139, 0.935773, 1.206609, 1.726547",\ + "1.095138, 1.129115, 1.209400, 1.479059, 1.996736"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084"); + values ( "0.748897, 0.805011, 0.957821, 1.471076, 2.450712",\ + "0.748897, 0.805011, 0.957821, 1.471076, 2.456399",\ + "0.748897, 0.811237, 0.965448, 1.477816, 2.457642",\ + "0.748897, 0.811237, 0.965448, 1.479720, 2.465531",\ + "0.748897, 0.813325, 0.966210, 1.479720, 2.465531"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084"); + values ( "0.331095, 0.354971, 0.411113, 0.599682, 0.961689",\ + "0.422338, 0.446186, 0.502618, 0.692160, 1.056035",\ + "0.529474, 0.553262, 0.609349, 0.797734, 1.159388",\ + "0.719234, 0.743081, 0.799295, 0.988106, 1.350577",\ + "1.047647, 1.071864, 1.127881, 1.316028, 1.677225"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084"); + values ( "0.484230, 0.518873, 0.622079, 0.966408, 1.621243",\ + "0.484230, 0.518873, 0.622079, 0.966408, 1.621243",\ + "0.484230, 0.518873, 0.622079, 0.968730, 1.631847",\ + "0.484230, 0.522164, 0.625240, 0.971450, 1.631847",\ + "0.491280, 0.530601, 0.632503, 0.974773, 1.631847"); + } + + } /* end of arc padmux2ast_i[2]_scan_shift_en_o_una_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084"); + values ( "380000.312500, 380000.343750, 380000.406250, 380000.687500, 380001.187500",\ + "380000.406250, 380000.437500, 380000.500000, 380000.781250, 380001.281250",\ + "380000.500000, 380000.531250, 380000.593750, 380000.875000, 380001.375000",\ + "380000.656250, 380000.687500, 380000.750000, 380001.031250, 380001.531250",\ + "380000.906250, 380000.937500, 380001.000000, 380001.281250, 380001.781250"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084"); + values ( "0.750971, 0.815816, 0.968419, 1.480978, 2.464965",\ + "0.750971, 0.815816, 0.968419, 1.480978, 2.464965",\ + "0.750971, 0.815816, 0.968419, 1.480978, 2.464965",\ + "0.750971, 0.815816, 0.968419, 1.480978, 2.464965",\ + "0.750971, 0.815816, 0.968419, 1.480978, 2.464965"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084"); + values ( "380001.656250, 380001.687500, 380001.750000, 380001.937500, 380002.281250",\ + "380001.750000, 380001.781250, 380001.843750, 380002.031250, 380002.375000",\ + "380001.875000, 380001.906250, 380001.968750, 380002.156250, 380002.500000",\ + "380002.062500, 380002.093750, 380002.156250, 380002.343750, 380002.687500",\ + "380002.375000, 380002.406250, 380002.468750, 380002.656250, 380003.000000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084"); + values ( "0.476385, 0.519957, 0.622899, 0.968661, 1.632439",\ + "0.476385, 0.519957, 0.622899, 0.968661, 1.632439",\ + "0.476385, 0.519957, 0.622899, 0.968661, 1.632439",\ + "0.476385, 0.519957, 0.622899, 0.968661, 1.632439",\ + "0.476385, 0.519957, 0.622899, 0.968661, 1.632439"); + } + + } /* end of arc padmux2ast_i[4]_scan_shift_en_o_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084"); + values ( "380000.312500, 380000.343750, 380000.406250, 380000.687500, 380001.187500",\ + "380000.406250, 380000.437500, 380000.500000, 380000.781250, 380001.281250",\ + "380000.468750, 380000.500000, 380000.562500, 380000.843750, 380001.343750",\ + "380000.625000, 380000.656250, 380000.718750, 380001.000000, 380001.500000",\ + "380000.843750, 380000.875000, 380000.937500, 380001.218750, 380001.718750"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084"); + values ( "0.750971, 0.815816, 0.968419, 1.480978, 2.464965",\ + "0.750971, 0.815816, 0.968419, 1.480978, 2.464965",\ + "0.750971, 0.815816, 0.968419, 1.480978, 2.464965",\ + "0.750971, 0.815816, 0.968419, 1.480978, 2.464965",\ + "0.750971, 0.815816, 0.968419, 1.480978, 2.464965"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084"); + values ( "380001.656250, 380001.687500, 380001.750000, 380001.937500, 380002.281250",\ + "380001.750000, 380001.781250, 380001.843750, 380002.031250, 380002.375000",\ + "380001.843750, 380001.875000, 380001.937500, 380002.125000, 380002.468750",\ + "380002.031250, 380002.062500, 380002.125000, 380002.312500, 380002.656250",\ + "380002.281250, 380002.312500, 380002.375000, 380002.562500, 380002.906250"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084"); + values ( "0.476385, 0.519957, 0.622899, 0.968661, 1.632439",\ + "0.476385, 0.519957, 0.622899, 0.968661, 1.632439",\ + "0.476385, 0.519957, 0.622899, 0.968661, 1.632439",\ + "0.476385, 0.519957, 0.622899, 0.968661, 1.632439",\ + "0.476385, 0.519957, 0.622899, 0.968661, 1.632439"); + } + + } /* end of arc padmux2ast_i[4]_scan_shift_en_o_una_min*/ + +} /* end of pin scan_shift_en_o */ + +pin("scan_reset_no") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.044252 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.021601 ; + + /* Other user defined attributes. */ + original_pin : scan_reset_no; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : recovery_rising ; + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.195118, 0.455354, 1.099537, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "1.964051, 1.921426, 1.863863, 1.867343, 1.909642",\ + "2.060242, 2.017617, 1.960053, 1.963533, 2.005833",\ + "2.173090, 2.130465, 2.072901, 2.076381, 2.118681",\ + "2.375021, 2.332396, 2.274832, 2.278312, 2.320612",\ + "2.686105, 2.643480, 2.585916, 2.589396, 2.631696"); + } + + } /* end of arc clk_ast_alert_i_scan_reset_no_recfr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : removal_rising ; + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.195118, 0.455354, 0.898734, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-1.851924, -1.814471, -1.754913, -1.744727, -1.620931",\ + "-1.948175, -1.910723, -1.851165, -1.840978, -1.717183",\ + "-2.061304, -2.023851, -1.964293, -1.954107, -1.830311",\ + "-2.203395, -2.165943, -2.106384, -2.096198, -1.972402",\ + "-2.574453, -2.537001, -2.477442, -2.467256, -2.343460"); + } + + } /* end of arc clk_ast_alert_i_scan_reset_no_remfr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252"); + values ( "0.802143, 0.819742, 0.854125, 0.955681, 1.487746",\ + "0.890534, 0.908134, 0.942517, 1.044073, 1.576140",\ + "0.986100, 1.003701, 1.038085, 1.139644, 1.671728",\ + "1.152159, 1.169761, 1.204148, 1.305714, 1.837840",\ + "1.418048, 1.435651, 1.470039, 1.571612, 2.103765"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252"); + values ( "1.229517, 1.260918, 1.322264, 1.503458, 2.452761",\ + "1.229525, 1.260928, 1.322278, 1.503483, 2.452843",\ + "1.229623, 1.261050, 1.322445, 1.503785, 2.453854",\ + "1.229849, 1.261330, 1.322831, 1.504483, 2.456189",\ + "1.230249, 1.261792, 1.323416, 1.505431, 2.459036"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252"); + values ( "0.798583, 0.815273, 0.847880, 0.944189, 1.448769",\ + "0.886419, 0.903109, 0.935716, 1.032025, 1.536605",\ + "0.967929, 0.984620, 1.017227, 1.113536, 1.618116",\ + "1.107256, 1.123946, 1.156553, 1.252862, 1.757442",\ + "1.334271, 1.350961, 1.383568, 1.479877, 1.984456"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252"); + values ( "1.070623, 1.099479, 1.155855, 1.322366, 2.194748",\ + "1.070624, 1.099480, 1.155855, 1.322366, 2.194748",\ + "1.070624, 1.099480, 1.155855, 1.322366, 2.194748",\ + "1.070624, 1.099480, 1.155855, 1.322366, 2.194752",\ + "1.070624, 1.099480, 1.155855, 1.322366, 2.194762"); + } + + } /* end of arc clk_ast_ext_i_scan_reset_no_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252"); + values ( "0.802125, 0.819724, 0.854108, 0.955663, 1.487728",\ + "0.890342, 0.907941, 0.942325, 1.043880, 1.575947",\ + "0.986099, 1.003699, 1.038084, 1.139642, 1.671727",\ + "1.152155, 1.169757, 1.204144, 1.305710, 1.837835",\ + "1.417944, 1.435547, 1.469935, 1.571508, 2.103662"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252"); + values ( "1.229517, 1.260918, 1.322264, 1.503458, 2.452760",\ + "1.229525, 1.260928, 1.322278, 1.503482, 2.452842",\ + "1.229623, 1.261050, 1.322445, 1.503785, 2.453854",\ + "1.229849, 1.261330, 1.322831, 1.504483, 2.456189",\ + "1.230248, 1.261792, 1.323416, 1.505430, 2.459036"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252"); + values ( "0.798579, 0.815269, 0.847876, 0.944185, 1.448765",\ + "0.886379, 0.903069, 0.935677, 1.031986, 1.536566",\ + "0.967658, 0.984348, 1.016956, 1.113265, 1.617844",\ + "1.107229, 1.123919, 1.156526, 1.252835, 1.757415",\ + "1.334205, 1.350896, 1.383503, 1.479811, 1.984390"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252"); + values ( "1.070600, 1.099457, 1.155835, 1.322351, 2.194748",\ + "1.070600, 1.099457, 1.155835, 1.322351, 2.194748",\ + "1.070600, 1.099457, 1.155835, 1.322351, 2.194748",\ + "1.070600, 1.099457, 1.155835, 1.322351, 2.194752",\ + "1.070600, 1.099457, 1.155835, 1.322351, 2.194762"); + } + + } /* end of arc clk_ast_ext_i_scan_reset_no_redg_min*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : recovery_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.195118, 0.455354, 1.230133, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "3.588611, 3.540715, 3.506416, 3.500099, 3.522348",\ + "3.671103, 3.623207, 3.588908, 3.582592, 3.604841",\ + "3.766086, 3.718189, 3.683890, 3.677574, 3.699822",\ + "3.975284, 3.927388, 3.893089, 3.886772, 3.909021",\ + "4.236159, 4.188263, 4.153964, 4.147648, 4.169896"); + } + + } /* end of arc clk_ast_ext_i_scan_reset_no_recrr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : recovery_falling ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.195118, 0.455354, 1.230133, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.254411, 0.254411, 0.254411, 0.254411, 0.254411",\ + "0.332233, 0.332233, 0.332233, 0.332233, 0.332233",\ + "0.412826, 0.412826, 0.412826, 0.412826, 0.412826",\ + "0.584722, 0.584722, 0.584722, 0.584722, 0.584722",\ + "0.796290, 0.796290, 0.796290, 0.796290, 0.796290"); + } + + } /* end of arc clk_ast_ext_i_scan_reset_no_recrf*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : removal_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.195118, 0.591561, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.156602, -0.106021, -0.062437, -0.009182, 0.090788",\ + "-0.234424, -0.183844, -0.140259, -0.087005, 0.012965",\ + "-0.347653, -0.297234, -0.253546, -0.200284, -0.100415",\ + "-0.457700, -0.407414, -0.363694, -0.310440, -0.210630",\ + "-0.693682, -0.643595, -0.600273, -0.547145, -0.447229"); + } + + } /* end of arc clk_ast_ext_i_scan_reset_no_remrr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : removal_falling ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.195118, 0.591561, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.072639, -0.072639, -0.072639, -0.072639, -0.072639",\ + "-0.150732, -0.150732, -0.150732, -0.150732, -0.150732",\ + "-0.261960, -0.261960, -0.261960, -0.261960, -0.261960",\ + "-0.368573, -0.368573, -0.368573, -0.368573, -0.368573",\ + "-0.585347, -0.585347, -0.585347, -0.585347, -0.585347"); + } + + } /* end of arc clk_ast_ext_i_scan_reset_no_remrf*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252"); + values ( "380001.750000, 380001.750000, 380001.750000, 380001.812500, 380002.062500",\ + "380001.843750, 380001.843750, 380001.843750, 380001.906250, 380002.156250",\ + "380001.937500, 380001.937500, 380001.937500, 380002.000000, 380002.250000",\ + "380002.000000, 380002.000000, 380002.000000, 380002.062500, 380002.312500",\ + "380002.343750, 380002.343750, 380002.343750, 380002.406250, 380002.656250"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252"); + values ( "1.229646, 1.261078, 1.322484, 1.503854, 2.454086",\ + "1.229646, 1.261078, 1.322484, 1.503854, 2.454086",\ + "1.229646, 1.261078, 1.322484, 1.503854, 2.454086",\ + "1.229646, 1.261078, 1.322484, 1.503855, 2.454087",\ + "1.229648, 1.261080, 1.322487, 1.503860, 2.454105"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252"); + values ( "380000.593750, 380000.593750, 380000.625000, 380000.718750, 380001.250000",\ + "380000.687500, 380000.687500, 380000.718750, 380000.812500, 380001.343750",\ + "380000.750000, 380000.750000, 380000.781250, 380000.875000, 380001.406250",\ + "380000.812500, 380000.812500, 380000.843750, 380000.937500, 380001.468750",\ + "380001.125000, 380001.125000, 380001.156250, 380001.250000, 380001.781250"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252"); + values ( "1.098794, 1.128370, 1.186150, 1.356812, 2.250939",\ + "1.098794, 1.128370, 1.186150, 1.356812, 2.250939",\ + "1.098794, 1.128370, 1.186150, 1.356812, 2.250939",\ + "1.098794, 1.128370, 1.186150, 1.356812, 2.250939",\ + "1.099064, 1.128619, 1.186359, 1.356900, 2.250939"); + } + + } /* end of arc clk_ast_tlul_i_scan_reset_no_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252"); + values ( "0.422873, 0.430902, 0.446588, 0.492920, 0.735645",\ + "0.510672, 0.518701, 0.534387, 0.580719, 0.823446",\ + "0.591965, 0.599994, 0.615680, 0.662012, 0.904736",\ + "0.650145, 0.658174, 0.673861, 0.720193, 0.962908",\ + "0.958388, 0.966413, 0.982090, 1.028394, 1.270988"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252"); + values ( "0.591561, 0.606759, 0.636466, 0.724197, 1.183709",\ + "0.591561, 0.606759, 0.636466, 0.724197, 1.183709",\ + "0.591563, 0.606768, 0.636472, 0.724197, 1.183709",\ + "0.591595, 0.606795, 0.636489, 0.724197, 1.183709",\ + "0.591849, 0.607055, 0.636761, 0.724504, 1.184204"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252"); + values ( "0.601971, 0.615882, 0.643058, 0.723326, 1.143863",\ + "0.689980, 0.703892, 0.731069, 0.811342, 1.231904",\ + "0.785109, 0.799012, 0.826172, 0.906394, 1.326690",\ + "0.853674, 0.867567, 0.894707, 0.974869, 1.394853",\ + "1.216942, 1.230863, 1.258059, 1.338388, 1.759243"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252"); + values ( "0.898014, 0.922343, 0.969635, 1.108981, 1.838479",\ + "0.898014, 0.922343, 0.969635, 1.108981, 1.838479",\ + "0.898014, 0.922343, 0.969635, 1.108981, 1.839038",\ + "0.898014, 0.922343, 0.969800, 1.109378, 1.840651",\ + "0.898014, 0.922343, 0.969873, 1.110259, 1.842156"); + } + + } /* end of arc clk_ast_tlul_i_scan_reset_no_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : recovery_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.195118, 0.455354, 1.230133, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "1.415613, 1.363816, 1.325401, 1.311644, 1.337231",\ + "1.501586, 1.449789, 1.411374, 1.397617, 1.423205",\ + "1.612727, 1.560930, 1.522515, 1.508758, 1.534346",\ + "1.834322, 1.782526, 1.744110, 1.730354, 1.755941",\ + "2.101753, 2.049956, 2.011540, 1.997784, 2.023371"); + } + + } /* end of arc clk_ast_tlul_i_scan_reset_no_recrr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : removal_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.195118, 0.591561, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.697532, -0.650599, -0.616529, -0.592387, -0.469972",\ + "-0.783374, -0.736441, -0.702370, -0.678229, -0.555814",\ + "-0.939179, -0.892246, -0.858175, -0.834034, -0.711619",\ + "-1.080269, -1.033336, -0.999265, -0.975124, -0.852709",\ + "-1.378594, -1.331661, -1.297591, -1.273450, -1.151034"); + } + + } /* end of arc clk_ast_tlul_i_scan_reset_no_remrr*/ + + timing () { + related_pin : "padmux2ast_i[3]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252"); + values ( "0.726887, 0.744473, 0.778830, 0.880309, 1.411971",\ + "0.813994, 0.831587, 0.865957, 0.967473, 1.499333",\ + "0.895839, 0.913433, 0.947805, 1.049329, 1.581226",\ + "1.037802, 1.055400, 1.089781, 1.191329, 1.723358",\ + "1.277047, 1.294652, 1.329045, 1.430630, 1.962853"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252"); + values ( "1.230133, 1.261577, 1.323007, 1.504448, 2.455048",\ + "1.230133, 1.261577, 1.323007, 1.504448, 2.455048",\ + "1.230191, 1.261616, 1.323008, 1.504448, 2.455048",\ + "1.230748, 1.262222, 1.323711, 1.505326, 2.455673",\ + "1.230748, 1.262222, 1.323711, 1.505326, 2.455673"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252"); + values ( "0.683808, 0.700926, 0.734366, 0.833138, 1.350622",\ + "0.774648, 0.791774, 0.825231, 0.924052, 1.441793",\ + "0.860296, 0.877424, 0.910885, 1.009716, 1.527510",\ + "1.010613, 1.027735, 1.061184, 1.159981, 1.677597",\ + "1.262256, 1.279377, 1.312826, 1.411619, 1.929216"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252"); + values ( "1.099537, 1.129083, 1.186806, 1.357299, 2.250541",\ + "1.099537, 1.129083, 1.186806, 1.357299, 2.250541",\ + "1.099537, 1.129083, 1.186806, 1.357299, 2.250541",\ + "1.099537, 1.129083, 1.186806, 1.357299, 2.250541",\ + "1.099652, 1.129190, 1.186897, 1.357342, 2.250541"); + } + + } /* end of arc padmux2ast_i[3]_scan_reset_no_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[3]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252"); + values ( "0.726887, 0.744473, 0.778830, 0.880309, 1.411971",\ + "0.813994, 0.831587, 0.865957, 0.967473, 1.499333",\ + "0.895839, 0.913433, 0.947805, 1.049329, 1.581226",\ + "1.037802, 1.055400, 1.089781, 1.191329, 1.723358",\ + "1.277047, 1.294652, 1.329045, 1.430630, 1.962853"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252"); + values ( "1.230133, 1.260882, 1.322288, 1.503659, 2.453893",\ + "1.230133, 1.260882, 1.322288, 1.503659, 2.453893",\ + "1.230191, 1.261616, 1.323008, 1.504337, 2.454350",\ + "1.230581, 1.262030, 1.323468, 1.504936, 2.455673",\ + "1.230581, 1.262030, 1.323468, 1.504936, 2.455673"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252"); + values ( "0.683808, 0.700926, 0.734366, 0.833138, 1.350622",\ + "0.774648, 0.791774, 0.825231, 0.924052, 1.441793",\ + "0.860296, 0.877424, 0.910885, 1.009716, 1.527510",\ + "1.010613, 1.027735, 1.061184, 1.159981, 1.677597",\ + "1.262256, 1.279377, 1.312826, 1.411619, 1.929216"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252"); + values ( "1.099537, 1.128236, 1.185986, 1.356560, 2.250221",\ + "1.099537, 1.128236, 1.185986, 1.356560, 2.250221",\ + "1.099537, 1.128268, 1.186038, 1.356667, 2.250334",\ + "1.099537, 1.128795, 1.186566, 1.357201, 2.250334",\ + "1.099652, 1.129190, 1.186897, 1.357342, 2.250334"); + } + + } /* end of arc padmux2ast_i[3]_scan_reset_no_una_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252"); + values ( "380000.468750, 380000.468750, 380000.500000, 380000.593750, 380001.125000",\ + "380000.562500, 380000.562500, 380000.593750, 380000.687500, 380001.218750",\ + "380000.656250, 380000.656250, 380000.687500, 380000.781250, 380001.312500",\ + "380000.812500, 380000.812500, 380000.843750, 380000.937500, 380001.468750",\ + "380001.062500, 380001.062500, 380001.093750, 380001.187500, 380001.718750"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252"); + values ( "1.098794, 1.128370, 1.186150, 1.356812, 2.250939",\ + "1.098794, 1.128370, 1.186150, 1.356812, 2.250939",\ + "1.098794, 1.128370, 1.186150, 1.356812, 2.250939",\ + "1.098794, 1.128370, 1.186150, 1.356812, 2.250939",\ + "1.098794, 1.128370, 1.186150, 1.356812, 2.250939"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252"); + values ( "380001.656250, 380001.656250, 380001.656250, 380001.718750, 380001.968750",\ + "380001.750000, 380001.750000, 380001.750000, 380001.812500, 380002.062500",\ + "380001.875000, 380001.875000, 380001.875000, 380001.937500, 380002.187500",\ + "380002.062500, 380002.062500, 380002.062500, 380002.125000, 380002.375000",\ + "380002.375000, 380002.375000, 380002.375000, 380002.437500, 380002.687500"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252"); + values ( "0.602094, 0.617527, 0.647677, 0.736728, 1.205538",\ + "0.602094, 0.617527, 0.647677, 0.736728, 1.205538",\ + "0.602094, 0.617527, 0.647677, 0.736728, 1.205538",\ + "0.602094, 0.617527, 0.647677, 0.736728, 1.205538",\ + "0.602094, 0.617527, 0.647677, 0.736728, 1.205538"); + } + + } /* end of arc padmux2ast_i[4]_scan_reset_no_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252"); + values ( "380000.343750, 380000.343750, 380000.375000, 380000.468750, 380000.875000",\ + "380000.437500, 380000.437500, 380000.468750, 380000.562500, 380000.968750",\ + "380000.500000, 380000.500000, 380000.531250, 380000.625000, 380001.031250",\ + "380000.656250, 380000.656250, 380000.687500, 380000.781250, 380001.187500",\ + "380000.875000, 380000.875000, 380000.906250, 380001.000000, 380001.406250"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252"); + values ( "0.899963, 0.924149, 0.971400, 1.110963, 1.842156",\ + "0.899963, 0.924149, 0.971400, 1.110963, 1.842156",\ + "0.899963, 0.924149, 0.971400, 1.110963, 1.842156",\ + "0.899963, 0.924149, 0.971400, 1.110963, 1.842156",\ + "0.899963, 0.924149, 0.971400, 1.110963, 1.842156"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252"); + values ( "380001.656250, 380001.656250, 380001.656250, 380001.718750, 380001.968750",\ + "380001.750000, 380001.750000, 380001.750000, 380001.812500, 380002.062500",\ + "380001.843750, 380001.843750, 380001.843750, 380001.906250, 380002.156250",\ + "380002.031250, 380002.031250, 380002.031250, 380002.093750, 380002.343750",\ + "380002.281250, 380002.281250, 380002.281250, 380002.343750, 380002.593750"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252"); + values ( "0.599658, 0.615162, 0.645450, 0.734911, 1.203284",\ + "0.599658, 0.615162, 0.645450, 0.734911, 1.203284",\ + "0.599658, 0.615162, 0.645450, 0.734911, 1.203284",\ + "0.599658, 0.615162, 0.645450, 0.734911, 1.203284",\ + "0.599658, 0.615162, 0.645450, 0.734911, 1.203284"); + } + + } /* end of arc padmux2ast_i[4]_scan_reset_no_inv_min*/ + +} /* end of pin scan_reset_no */ + + + + + + +} /* end of cell */ + +} /* end of library */ diff --git a/src/ast/lint/ast.vbl b/src/ast/lint/ast.vbl new file mode 100644 index 0000000..0df7c4b --- /dev/null +++ b/src/ast/lint/ast.vbl @@ -0,0 +1,16 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# Verible waiver file for AST + +# Waive the always-comb rule in the various "pgd" modules. The rule is checking +# that we don't use always @*, and suggests we use always_comb instead. +# Unfortunately, the code in question doesn't really translate to always_comb. +# And we don't really care about the linting rule: the code is just supposed to +# be a behavioural model of some analog code that isn't really part of the OT +# opensource repo. Waive the warning. +waive --rule=always-comb --location="vcc_pgd.sv" +waive --rule=always-comb --location="vio_pgd.sv" +waive --rule=always-comb --location="vcaon_pgd.sv" +waive --rule=always-comb --location="vcmain_pgd.sv" diff --git a/src/ast/lint/ast.vlt b/src/ast/lint/ast.vlt new file mode 100644 index 0000000..b4c6b30 --- /dev/null +++ b/src/ast/lint/ast.vlt @@ -0,0 +1,17 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// waiver file for ast + +`verilator_config + +// ast_clks_byp.sv has an always_latch block which doesn't actually do anything +// because the enable signal (!scan_mode_i) is always true. Verilator notices +// and complains, but we're doing this on purpose. +lint_off -rule NOLATCH -file "*/rtl/ast_clks_byp.sv" + +// Manually mark a clock enable: if we don't tell Verilator we're doing it on +// purpose, it will warn us that there's a path from "normal" logic through to +// a clock signal. +clock_enable -module "ast_clks_byp" -var "clk_ext_en" diff --git a/src/ast/lint/ast.waiver b/src/ast/lint/ast.waiver new file mode 100644 index 0000000..05fb273 --- /dev/null +++ b/src/ast/lint/ast.waiver @@ -0,0 +1,377 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# waiver file for ast + +waive -rules CONST_FF -location {ast_clks_byp.sv} \ + -msg {Flip-flop 'sw_clk_byp_en' is driven by constant one} \ + -comment {This flip flop is supposed to change to 1 on the first clock cycle and remain there afterwards.} + +waive -rules IFDEF_CODE -location {ast.sv} \ + -msg {Assignment to 'ast2pad_t0_ao' contained within `else block at ast.sv} \ + -comment {This ifdef statement is used for analog simulations and is OK.} + +waive -rules IFDEF_CODE -location {ast.sv} \ + -msg {Assignment to 'unused_analog_sigs' contained within `ifndef 'ANALOGSIM' block at} \ + -comment {This ifdef statement is used for assigning "unused" signals and is OK.} + +waive -rules IFDEF_CODE -location {ast.sv} \ + -regexp {Assignment to 'clk_(sys|usb|aon|io)_ext' contained within `ifdef 'AST_BYPASS_CLK' block at} \ + -comment {This ifdef statement is fine as it is part of the FPGA/Verilator clock bypass mechanism.} + +waive -rules IFDEF_CODE -location {aon_osc.sv io_osc.sv sys_osc.sv usb_osc.sv} \ + -regexp {Assignment to '(sys|usb|aon|io)_clk_dly' contained within `else block at} \ + -comment {This ifdef statement is fine as it is part of the FPGA/Verilator clock bypass mechanism.} + +waive -rules IFDEF_CODE -location {aon_osc.sv io_osc.sv sys_osc.sv usb_osc.sv} \ + -regexp {Assignment to 'en_osc_re' contained within} \ + -comment {This ifdef statement is fine as it is part of the FPGA/Verilator clock bypass mechanism.} + +waive -rules IFDEF_CODE -location {aon_osc.sv} \ + -regexp {Assignment to 'clk' contained within} \ + -comment {This ifdef statement is fine as it is part of the FPGA/Verilator clock bypass mechanism.} + +waive -rules DUAL_EDGE_CLOCK -location {ast_clks_byp.sv} \ + -msg {Clock 'clk_ast_ext_scn' uses falling edge here and rising edge 'clk_i' at} \ + -comment {Posedge sync aon_clk reset to clk_ast_ext_scn while negedge drives the sw_clk_byp_en.} + +waive -rules CLOCK_EDGE -location {aon_osc.sv io_osc.sv sys_osc.sv usb_osc.sv} \ + -msg {Falling edge of clock 'clk' used here, should use rising edge} \ + -comment {This negedge trigger is done on purpose.} + +waive -rules CLOCK_EDGE -location {ast_clks_byp.sv} \ + -msg {Falling edge of clock 'clk_ast_ext_scn' used here, should use rising edge} \ + -comment {This negedge trigger is done on purpose.} + +waive -rules CLOCK_EDGE -location {ast_clks_byp.sv} \ + -msg {'prim_flop_2sync' instance 'u_no_scan_ext_freq_is_96m_sync' contained within `ifndef 'AST_BYPASS_CLK' block at} \ + -comment {This ifdef statement is fine as it is part of the FPGA/Verilator clock bypass mechanism.} + +waive -rules CLOCK_DRIVER -location {ast.sv} \ + -regexp {'clk_src_(aon|io|sys)' is driven by instance 'u_ast_clks_byp' of module 'ast_clks_byp', and used as a clock 'clk_i' at} \ + -comment {This is clock generation logic, hence it needs to drive this clock signal.} + +waive -rules CLOCK_DRIVER -location {ast.sv} \ + -regexp {'clk_src_(aon|io|sys)' in module 'ast_clks_byp' by port} \ + -comment {This is clock generation logic, hence it needs to drive this clock signal.} + +waive -rules CLOCK_DRIVER -location {ast.sv} \ + -msg {'clk_o' driven in module 'gfr_clk_mux2' at} \ + -comment {This is clock generation logic, hence it needs to drive this clock signal.} + +waive -rules CLOCK_DRIVER -location {ast_clks_byp.sv} \ + -msg {'clk_o' driven in module 'gfr_clk_mux2' at} \ + -comment {This is clock generation logic, hence it needs to drive this clock signal.} + +waive -rules CLOCK_DRIVER -location {ast_clks_byp.sv} \ + -regexp {'clk_src_(aon|io)_o' is driven by instance 'u_clk_src_(aon|io)_sel' of module 'gfr_clk_mux2', and used as a clock 'clk_i' at} \ + -comment {This is clock generation logic, hence it needs to drive this clock signal.} + +waive -rules CLOCK_DRIVER -location {ast_clks_byp.sv} \ + -regexp {'clk_src_io' is driven by instance 'u_clk_src_io_sel' of module 'gfr_clk_mux2', and used as a clock 'clk_i' at} \ + -comment {This is clock generation logic, hence it needs to drive this clock signal.} + +waive -rules CLOCK_DRIVER -location {ast_clks_byp.sv} \ + -regexp {'clk_ext_scn' is driven here, and used as a clock 'clk_i' at} \ + -comment {This is clock generation logic, hence it needs to drive this clock signal.} + +waive -rules CLOCK_MUX -location {ast_clks_byp.sv} \ + -regexp {Clock '(clk_ast_ext_scn|clk_ext_scn|clk_src_ext_usb|clk_ext_aon)' is driven by a multiplexer here, used as a clock} \ + -comment {This is clock generation logic, hence it needs to drive this clock signal.} + +waive -rules CLOCK_MUX -location {ast_clks_byp.sv} \ + -regexp {Clock 'clk_ast_ext' reaches a multiplexer here, used as a clock} \ + -comment {This is clock generation logic, hence it needs to drive this clock signal.} + +waive -rules IFDEF_CODE -location {ast_clks_byp.sv} \ + -regexp {Assignment to 'clk_ast_ext_scn' contained within `ifndef 'AST_BYPASS_CLK' block at} \ + -comment {This ifndef statement is fine as it is part of the FPGA/Verilator clock bypass mechanism.} + +waive -rules IFDEF_CODE -location {ast_clks_byp.sv} \ + -regexp {Assignment to 'clk_ext_scn' contained within `else block at} \ + -comment {This ifndef statement is fine as it is part of the FPGA/Verilator clock bypass mechanism.} + +waive -rules IFDEF_CODE -location {ast_clks_byp.sv} \ + -regexp {Assignment to 'clk_src_io_val_o' contained within `ifndef 'AST_BYPASS_CLK' block at} \ + -comment {This ifndef statement is fine as it is part of the FPGA/Verilator clock bypass mechanism.} + +waive -rules IFDEF_CODE -location {ast_clks_byp.sv} \ + -regexp {'prim_clock_div' instance 'u_no_scan_clk_(ext_d1ord2|usb_div240_div)' contained within `ifndef 'AST_BYPASS_CLK' block at} \ + -comment {This ifndef statement is fine as it is part of the FPGA/Verilator clock bypass mechanism.} + +waive -rules IFDEF_CODE -location {ast_clks_byp.sv} \ + -regexp {'prim_flop_2sync' instance 'u_no_scan_ext_freq_is_96m_sync' contained within `ifndef 'AST_BYPASS_CLK' block at} \ + -comment {This ifndef statement is fine as it is part of the FPGA/Verilator clock bypass mechanism.} + +waive -rules IFDEF_CODE -location {ast_clks_byp.sv} \ + -regexp {always_latch block contained within `ifndef 'AST_BYPASS_CLK' block at} \ + -comment {This ifndef statement is fine as it is part of the FPGA/Verilator clock bypass mechanism.} + +waive -rules CLOCK_MUX -location {ast.sv} \ + -regexp {Clock 'clk_aon_n' is driven by a multiplexer here, used as a clock} \ + -comment {This clock inverter has a DFT mux.} + +waive -rules CLOCK_MUX -location {rglts_pdm_3p3v.sv} \ + -regexp {Clock 'clk_src_aon_h_n' is driven by a multiplexer here, used as a clock at } \ + -comment {This signal has a DFT mux.} + +waive -rules CLOCK_USE -location {gfr_clk_mux2.sv} \ + -regexp {('clk_ext'|'clk_osc') is used for some other purpose, and as clock ('clk_ext_i'|'clk_osc_i') at gfr_clk_mux2.sv} \ + -comment {This message pops up due to a clock OR operation.} + +waive -rules CLOCK_USE -location {ast.sv} \ + -regexp {'clk_ast_tlul_i' is connected to 'ast_dft' port 'clk_i', and used as a clock 'clk_i' at prim_lfsr} \ + -comment {This is a valid clock signal and the LFSR runs on the bus clock here.} + +waive -rules CLOCK_USE -location {ast.sv} \ + -regexp {'clk_aon' is connected to 'rglts_pdm_3p3v' port 'clk_src_aon_h_i', and used as a clock} \ + -comment {This is a valid clock signal and the connection is ok here.} + +waive -rules CLOCK_USE -location {ast.sv} \ + -regexp {'clk_ast_usb_i' is used for some other purpose, and as clock 'clk_i' at prim_generic_flop.sv} \ + -comment {This is a valid clock signal and the connection is ok here.} + +waive -rules INV_CLOCK -location {ast.sv rglts_pdm_3p3v.sv} \ + -regexp {'(clk_aon|clk_src_aon_h_i)' is inverted, used as clock} \ + -comment {These clocks are inverted.} + +waive -rules INV_CLOCK -location {ast_clks_byp.sv} \ + -regexp {'clk_src_ext_usb' is inverted, used as clock 'clk_i'} \ + -comment {Needed to sample clk_src_ext_usb enable signal with the clock negedge.} + +waive -rules RESET_DRIVER -location {aon_clk.sv io_clk.sv sys_clk.sv usb_clk.sv} \ + -msg {'rst_val_n' is driven here, and used as an asynchronous reset} \ + -comment {This is reset generation logic, hence it needs to drive this reset signal.} + +waive -rules RESET_DRIVER -location {aon_clk.sv io_clk.sv sys_clk.sv usb_clk.sv} \ + -regexp {'(aon|io|sys|usb)_clk_en' is driven here, and used as an asynchronous reset} \ + -comment {This is reset generation logic, hence it needs to drive this reset signal.} + +waive -rules RESET_DRIVER -location {rng.sv} \ + -msg {'rst_n' is driven here, and used as an asynchronous reset at rng.sv} \ + -comment {This is reset generation logic, hence it needs to drive this reset signal.} + +waive -rules RESET_DRIVER -location {ast.sv} \ + -regexp {'(vcaon_pok_h|por_rst_n|vcmain_pok_por|vcmain_pok_por_src)' is driven here, and used as an asynchronous reset} \ + -comment {This is reset generation logic, hence it needs to drive this reset signal.} + +waive -rules RESET_DRIVER -location {ast.sv} \ + -msg {'clk_io_osc_val' is driven by instance 'u_io_clk' of module 'io_clk', and used as an asynchronous reset 'rst_clk_osc_n' at ast_dft.sv} \ + -comment {This is reset generation logic, hence it needs to drive this reset signal.} + +waive -rules RESET_DRIVER -location {ast.sv} \ + -msg {'clk_src_io_val_o' driven in module 'io_clk' by port 'u_val_sync.q_o[0]' at io_clk.sv} \ + -comment {This is reset generation logic, hence it needs to drive this reset signal.} + +waive -rules RESET_DRIVER -location {ast.sv dev_entropy.sv ast_clks_byp.sv} \ + -regexp {'q_o[0]' driven in module 'prim_flop_2sync' by port .* at prim_flop_2sync.sv} \ + -comment {This is reset generation logic, hence it needs to drive this reset signal.} + +waive -rules RESET_DRIVER -location {ast.sv} \ + -msg {'vcmain_pok_por_sys' is driven by instance 'u_rst_sys_dasrt' of module 'prim_flop_2sync', and used as an asynchronous reset 'rst_dev_ni' at dev_entropy.sv} \ + -comment {This is reset generation logic, hence it needs to drive this reset signal.} + +waive -rules RESET_DRIVER -location {dev_entropy.sv} \ + -msg {'rst_es_dev_nd' is driven by instance 'u_rst_es_n_da' of module 'prim_flop_2sync', and used as an asynchronous reset 'rst_es_dev_n'} \ + -comment {This is reset generation logic, hence it needs to drive this reset signal.} + +waive -rules RESET_DRIVER -location {dev_entropy.sv} \ + -msg {'rst_es_dev_nd' is driven by instance 'u_rst_es_n_da' of module 'prim_flop_2sync', and used as an asynchronous reset 'rst_es_dev_n'} \ + -comment {This is reset generation logic, hence it needs to drive this reset signal.} + +waive -rules RESET_DRIVER -location {dev_entropy.sv} \ + -msg {'rst_es_dev_da_n' is driven by instance 'u_rst_es_n_da' of module 'prim_flop_2sync', and used as an asynchronous reset 'rst_es_dev_n' at} \ + -comment {This is reset generation logic, hence it needs to drive this reset signal.} + +waive -rules RESET_DRIVER -location {dev_entropy.sv} \ + -msg {'rst_es_dev_in_n' is driven here, and used as an asynchronous reset 'rst_ni' at} \ + -comment {This is reset generation logic, hence it needs to drive this reset signal.} + +waive -rules RESET_DRIVER -location {ast_pulse_sync.sv} \ + -regexp {'(rst_src_n|rst_dst_n)' is driven here, and used as an asynchronous reset at} \ + -comment {This is reset generation logic, hence it needs to drive this reset signal.} + +waive -rules RESET_DRIVER -location {ast_clks_byp.sv} \ + -regexp {'rst_aon_n_(ioda|exda)' is driven by instance 'u_rst_aon_n_(ioda|exda)_sync' of module} \ + -comment {This is reset generation logic, hence it needs to drive this reset signal.} + +waive -rules RESET_DRIVER -location {ast_clks_byp.sv} \ + -regexp {'rst_sw_clk_byp_en' is driven here, and used as an asynchronous reset 'rst_ni'} \ + -comment {This is reset generation logic, hence it needs to drive this reset signal.} + +waive -rules RESET_DRIVER -location {ast_clks_byp.sv} \ + -regexp {'da_rst_sw_ckbpe_n' is driven by instance 'u_no_scan_rst_sw_ckbpe_dasrt' of module 'prim_flop_2sync'} \ + -comment {Used as synced reset signal for clk_ast_ext_scn reset.} + +waive -rules RESET_DRIVER -location {ast.sv} \ + -regexp {'(vcc_pok|rst_poks_n|rst_poks_por_n|vcaon_pok_por_lat)' is driven here, and used as an asynchronous reset} \ + -comment {This is reset generation logic, hence it needs to drive this reset signal.} + +waive -rules RESET_DRIVER -location {ast.sv} \ + -msg {'vcmain_pok_por_sys' is driven by instance 'u_rst_sys_dasrt' of module} \ + -comment {This is reset generation logic, hence it needs to drive this reset signal.} + +waive -rules RESET_DRIVER -location {ast.sv} \ + -msg {'rst_aon_clk_n' is driven here, and used as an asynchronous reset 'rst_ni' at} \ + -comment {This is reset generation logic, hence it needs to drive this reset signal.} + +waive -rules RESET_DRIVER -location {rglts_pdm_3p3v.sv} \ + -regexp {'(vcc_pok_rst_h_n|vcc_pok_set_h|vcc_pok_str_.*|)' is driven here, and used as an asynchronous reset} \ + -comment {This is reset generation logic, hence reset muxes are allowed.} + +waive -rules RESET_DRIVER -location {ast.sv} \ + -regexp {'(vcaon_pok|vcaon_pok_h)' is driven by instance 'u_rglts_pdm_3p3v'} \ + -comment {This is reset generation logic, hence reset muxes are allowed.} + +waive -rules RESET_DRIVER -location {ast.sv} \ + -regexp {'(vcaon_pok_1p1_h_o|vcaon_pok_h_o)' driven in module 'rglts_pdm_3p3v'} \ + -comment {This is reset generation logic, hence reset muxes are allowed.} + +waive -rules RESET_DRIVER -location {ast.sv} \ + -regexp {'rst_sys_clk_n' is driven here, and used as an asynchronous reset 'rst_ni' at prim_generic_flop.sv} \ + -comment {This is reset generation logic, hence reset muxes are allowed.} + +waive -rules RESET_DRIVER -location {ast.sv} \ + -regexp {'rst_usb_clk_n' is driven here, and used as an asynchronous reset 'rst_ni' at prim_generic_flop.sv} \ + -comment {This is reset generation logic, hence reset muxes are allowed.} + +waive -rules RESET_DRIVER -location {ast.sv} \ + -regexp {'rst_io_clk_n' is driven here, and used as an asynchronous reset 'rst_ni' at prim_generic_flop.sv} \ + -comment {This is reset generation logic, hence reset muxes are allowed.} + +waive -rules RESET_DRIVER -location {usb_clk.sv} \ + -regexp {'rst_da_n' is driven by instance 'u_rst_da' of module 'prim_flop_2sync', and used as an asynchronous reset 'rst_ni' at prim_generic_flop.sv} \ + -comment {This is reset generation logic, hence reset muxes are allowed.} + +waive -rules RESET_DRIVER -location {usb_clk.sv} \ + -regexp {'q_o[0]' driven in module 'prim_flop_2sync' by port 'u_sync_2.q_o[0]' at prim_flop_2sync.sv} \ + -comment {This is reset generation logic, hence reset muxes are allowed.} + +waive -rules RESET_DRIVER -location {usb_clk.sv} \ + -regexp {'q_o[0]' driven in module 'prim_flop' by port 'gen_generic.u_impl_generic.q_o[0]' at prim_flop.sv} \ + -comment {This is reset generation logic, hence reset muxes are allowed.} + +waive -rules RESET_DRIVER -location {usb_clk.sv} \ + -regexp {'q_o[0]' driven in module 'prim_generic_flop' at prim_generic_flop.sv} \ + -comment {This is reset generation logic, hence reset muxes are allowed.} + +waive -rules RESET_DRIVER -location {usb_clk.sv} \ + -regexp {'rst_n' is driven here, and used as an asynchronous reset 'rst_ni' at prim_generic_flop.sv} \ + -comment {This is reset generation logic, hence reset muxes are allowed.} + +waive -rules RESET_DRIVER -location {usb_clk.sv} \ + -regexp {'rst_n' driven in module 'usb_clk' by 'rst_da_n' at usb_clk.sv} \ + -comment {This is reset generation logic, hence reset muxes are allowed.} + +waive -rules RESET_DRIVER -location {usb_clk.sv} \ + -regexp {'rst_usb_n' is driven by instance 'u_rst_ast_usb_da' of module 'prim_flop_2sync', and used as an asynchronous reset 'rst_ni' at prim_generic_flop.sv} \ + -comment {This is reset generation logic, hence reset muxes are allowed.} + +waive -rules RESET_DRIVER -location {ast_clks_byp.sv} \ + -regexp {'q_o[0]' driven in module 'prim_flop_2sync' by port 'u_sync_2.q_o[0]' at prim_flop_2sync.sv} \ + -comment {This is reset generation logic, hence reset muxes are allowed.} + +waive -rules RESET_DRIVER -location {ast_clks_byp.sv} \ + -regexp {'q_o[0]' driven in module 'prim_flop' by port 'gen_generic.u_impl_generic.q_o[0]' at prim_flop.sv} \ + -comment {This is reset generation logic, hence reset muxes are allowed.} + +waive -rules RESET_DRIVER -location {ast_clks_byp.sv} \ + -regexp {'q_o[0]' driven in module 'prim_generic_flop' at prim_generic_flop.sv} \ + -comment {This is reset generation logic, hence reset muxes are allowed.} + +waive -rules RESET_MUX -location {aon_clk.sv io_clk.sv sys_clk.sv usb_clk.sv} \ + -msg {Asynchronous reset 'rst_val_n' is driven by a multiplexer here, used as a reset} \ + -comment {This is reset generation logic, hence reset muxes are allowed.} + +waive -rules RESET_MUX -location {ast.sv} \ + -regexp {Asynchronous reset '(rst_poks_n|rst_poks_por_n|vcmain_pok_por|rst_src_sys_n|vcaon_pok_por)' is driven by a multiplexer here, used as a reset} \ + -comment {This is reset generation logic, hence reset muxes are allowed.} + +waive -rules RESET_MUX -location {rng.sv} \ + -msg {Asynchronous reset 'rst_n' is driven by a multiplexer here, used as a reset at rng.sv} \ + -comment {This is reset generation logic, hence reset muxes are allowed.} + +waive -rules RESET_MUX -location {ast_clks_byp.sv} \ + -regexp {Asynchronous reset '(rst_aon_n|rst_aon_exda_n|rst_aon_ioda_n|rst_sw_ckbpe_n)' is driven by a multiplexer here, used as a reset} \ + -comment {This is reset generation logic, hence reset muxes are allowed.} + +waive -rules RESET_MUX -location {ast_pulse_sync.sv} \ + -regexp {Asynchronous reset '(rst_src_n|rst_dst_n)' is driven by a multiplexer here, used as a reset} \ + -comment {This is reset generation logic, hence reset muxes are allowed.} + +waive -rules RESET_MUX -location {rglts_pdm_3p3v.sv} \ + -msg {Asynchronous reset 'vcc_pok_rst_h_n' is driven by a multiplexer here, used as a reset} \ + -comment {This is reset generation logic, hence reset muxes are allowed.} + +waive -rules RESET_MUX -location {usb_clk.sv} \ + -regexp {Asynchronous reset 'rst_n' is driven by a multiplexer here, used as a reset 'rst_ni' at prim_generic_flop.sv} \ + -comment {This is reset generation logic, hence reset muxes are allowed.} + +waive -rules RESET_USE -location {ast.sv} \ + -regexp {('vcore_pok_h_i'|'vcaon_pok') is used for some other purpose, and as asynchronous reset} \ + -comment {This is reset / clock generation logic, hence special reset usage is allowed.} + +waive -rules RESET_USE -location {ast.sv} \ + -regexp {'(vcmain_pok_por|vcmain_pok_por_src)' is connected to 'rglts_pdm_3p3v' port 'vcmain_pok_por_h_i', and used as an asynchronous reset or set} \ + -comment {This is reset / clock generation logic, hence special reset usage is allowed.} + +waive -rules RESET_USE -location {ast.sv} \ + -msg {'vcaon_pok_por' is connected to 'rglts_pdm_3p3v' port 'vcaon_pok_por_h_i', and used as an asynchronous reset or set} \ + -comment {This is reset / clock generation logic, hence special reset usage is allowed.} + +waive -rules RESET_USE -location {ast.sv} \ + -regexp {'(vcc_pok|vcmain_pok_por)' is used for some other purpose, and as asynchronous reset} \ + -comment {This is reset / clock generation logic, hence special reset usage is allowed.} + +waive -rules RESET_USE -location {ast.sv} \ + -regexp {'rst_(usb|aon|io|sys)_clk_n' is connected to '(usb|aon|io|sys)_clk' port 'rst_(usb|aon|io|sys)_clk_ni', and used as an asynchronous reset or set ('rst_ni'|'vcore_pok_h_i'|'rst_clk_byp_n')} \ + -comment {This is reset / clock generation logic, hence special reset usage is allowed.} + +waive -rules RESET_USE -location {io_osc.sv sys_osc.sv usb_osc.sv aon_osc.sv} \ + -msg {'vcore_pok_h_i' is used for some other purpose, and as asynchronous reset at} \ + -comment {This is reset / clock generation logic, hence special reset usage is allowed.} + +waive -rules RESET_USE -location {ast_dft.sv} \ + -msg {'clk_io_osc_val_i' is used for some other purpose, and as asynchronous reset 'rst_clk_osc_n' at ast_dft.sv} \ + -comment {This is reset / clock generation logic, hence special reset usage is allowed.} + +waive -rules RESET_USE -location {ast.sv} \ + -msg {'rst_ast_tlul_ni' is connected to 'ast_dft' port 'rst_ni', and used as an asynchronous reset or set 'rst_n' at rng} \ + -comment {This is a valid reset connection.} + +waive -rules RESET_USE -location {ast.sv} \ + -regexp {('rst_sys_clk_n'|'rst_usb_clk_n') is connected to ('sys_clk'|'usb_clk') port ('rst_sys_clk_ni'|'rst_usb_clk_ni'), and used as an asynchronous reset or set} \ + -comment {This is a valid reset connection.} + +waive -rules RESET_USE -location {aon_clk.sv io_clk.sv sys_clk.sv usb_clk.sv} \ + -regexp {'(aon|io|sys|usb)_clk_en' is connected to '(aon|io|sys|usb)_osc' port '(aon|io|sys|usb)_en_i', and used as an asynchronous reset or set} \ + -comment {This is reset / clock generation logic, hence special reset usage is allowed.} + +waive -rules RESET_USE -location {ast.sv} \ + -regexp {'rst_ast_usb_ni' is used for some other purpose, and as asynchronous reset 'rst_ni' at prim_generic_flop.sv} \ + -comment {This is reset generation logic, hence reset muxes are allowed.} + +waive -rules RESET_USE -location {usb_clk.sv} \ + -regexp {'rst_usb_clk_ni' is used for some other purpose, and as asynchronous reset 'rst_ni' at prim_generic_flop.sv} \ + -comment {This is reset generation logic, hence reset muxes are allowed.} + +waive -rules TRI_DRIVER -location {ast.sv} \ + -regexp {'ast2pad_(t0|t1)_ao' is driven by a tristate driver} \ + -comment {This part models a tristate driver.} + +waive -rules TERMINAL_STATE -location {rglts_pdm_3p3v.sv} \ + -msg {Terminal state 'RGLS_BROUT' is detected. State register 'rgls_sm' is not assigned to another state.} \ + -comment {The brownout state is terminal.} + +waive -rules Z_USE -location {ast.sv} \ + -msg {Constant with 'Z literal value '1'bz' encountered} \ + -comment {This part models a tristate driver.} + +waive -rules MULTI_RESET -location {rglts_pdm_3p3v.sv} \ + -msg {Found 2 asynchronous resets for this block: 'vcc_pok_rst_h_n', 'vcc_pok_set_h'} \ + -comment {This code is only a model and hence this is allowed.} + +waive -rules NOT_READ -location {aon_osc.sv io_osc.sv sys_osc.sv usb_osc.sv} \ + -msg {Signal 'en_osc' is not read from in module} \ + -comment {Signal 'en_osc' is not read when SYNTHESIS is defined, and AST_BYPASS_CLK is not defined.} diff --git a/src/ast/rtl/adc.sv b/src/ast/rtl/adc.sv new file mode 100644 index 0000000..2b2425b --- /dev/null +++ b/src/ast/rtl/adc.sv @@ -0,0 +1,141 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// -------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------- // +// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED. +// +//############################################################################ +// *Name: adc +// *Module Description: Analog/Digital Converter +//############################################################################ + +module adc #( + parameter int unsigned AdcCnvtClks = 19,// 21cc from adc_chnsel_i change to adc_d_val_o assertion + parameter int AdcChannels = 2, // ADC number of Channels + parameter int AdcDataWidth = 10 +) ( + input ast_pkg::awire_t adc_a0_ai, // ADC A0 Analog Input + input ast_pkg::awire_t adc_a1_ai, // ADC A1 Analog Input + input [AdcChannels-1:0] adc_chnsel_i, // Onehot value only for selrction + input adc_pd_i, // ADC Power Down + input clk_adc_i, // ADC Clock (aon_clk - 200KHz) + input rst_adc_ni, // ADC Reset active low + output logic [AdcDataWidth-1:0] adc_d_o, // ADC 10-bit Data Output + output logic adc_d_val_o // ADC Data Valid Output +); + +/////////////////////////////////////// +// ADC Enable +/////////////////////////////////////// +logic adc_en; + +always_ff @( posedge clk_adc_i, negedge rst_adc_ni ) begin + if ( !rst_adc_ni ) begin + adc_en <= 1'b0; + end else begin + adc_en <= !adc_pd_i; + end +end + + +/////////////////////////////////////// +// ADC Channel Select +/////////////////////////////////////// +logic chn_selected, chn_selected_d, new_convert, adc_busy; + +assign chn_selected = |(adc_chnsel_i); + +always_ff @( posedge clk_adc_i, negedge rst_adc_ni ) begin + if ( !rst_adc_ni ) begin + chn_selected_d <= 1'b0; + end else begin + chn_selected_d <= chn_selected; + end +end + +// New Convertion +assign new_convert = chn_selected && !chn_selected_d && !adc_busy; + +//////////////////////////////////////// +// ADC Analog Model +//////////////////////////////////////// +logic [10-1:0] adc_d_ch0, adc_d_ch1; + +adc_ana u_adc_ana ( + .adc_a0_ai ( adc_a0_ai ), + .adc_a1_ai ( adc_a1_ai ), + .adc_d_ch0_o ( adc_d_ch0[10-1:0] ), + .adc_d_ch1_o ( adc_d_ch1[10-1:0] ) +); + + +//////////////////////////////////////// +// ADC Digital Model +//////////////////////////////////////// +logic [8-1:0] cnv_cyc; +logic [8-1:0] ConvertCount; + +assign ConvertCount = AdcCnvtClks[8-1:0]; + +always_ff @( posedge clk_adc_i, negedge rst_adc_ni ) begin + if (!rst_adc_ni ) begin + cnv_cyc <= 8'h00; + adc_busy <= 1'b0; + adc_d_val_o <= 1'b0; + adc_d_o <= {AdcDataWidth{1'b0}}; + end else if ( !(adc_en && chn_selected) ) begin + cnv_cyc <= 8'h00; + adc_busy <= 1'b0; + adc_d_val_o <= 1'b0; + end else if ( new_convert ) begin + cnv_cyc <= ConvertCount; + adc_busy <= 1'b1; + adc_d_val_o <= 1'b0; + end else if ( adc_busy && (cnv_cyc > 8'h00) ) begin + cnv_cyc <= cnv_cyc - 1'b1; + adc_busy <= 1'b1; + adc_d_val_o <= 1'b0; + end else if ( adc_busy ) begin + adc_busy <= 1'b0; + adc_d_val_o <= 1'b1; + adc_d_o <= (adc_chnsel_i[1:0] == 2'b00) ? adc_d_o : + (adc_chnsel_i[1:0] == 2'b01) ? adc_d_ch0[10-1:0] : + (adc_chnsel_i[1:0] == 2'b10) ? adc_d_ch1[10-1:0] : + {AdcDataWidth{1'b1}}; + end +end + +///////////////////////// +// ASSERTIONS +///////////////////////// +// Add Assertion mux selector is onehot - zero is allowed +`ASSERT(AdcChnselOneHot_A, $onehot0(adc_chnsel_i), clk_adc_i, !rst_adc_ni) + +// Add Assertion adc_en=0 chnsel is 0. +`ASSERT(NoChannelWhileDisabled_A, (adc_en == 0) |-> (adc_chnsel_i == 4'h0), clk_adc_i, !rst_adc_ni) + +// The power up time period is 30us throughout which the adc_chnsel_i needs to be stable at 0. +// Since we are dealing with a time period here, and not clock cycles, we need to make sure +// that we sample and check enough clock ticks in order to guarantee the timing is met. +// Assuming that the clk_adc_i period is 200kHz, this SVA makes sure that: +// +// a) the signal adc_chnsel_i was 0 before adc_pd_i fell. this is achieved by sampling +// and checking on clock edges (-1) ... 0 in the illustration below. +// b) the signal adc_chnsel_i remained at 0 for at least 30us after adc_pd_i fell. +// this is achieved by sampling and checking on clock edges 0 ... 6 which cover a +// time period of 6 x 5us as shown in the illustration below. +// ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ +// clk_ast_adc_i : | |__| |__| |__| |__| |__| |__| |__| |__| |__| |__| |__ +// ___________ +// adc_pd_i : | |_______________________________________________________ +// +// adc_chnsel_i : xxxxxx___________________________________________________xxxxxxxxx +// +// ChannelStableOnAdcEn_A: | | | | | | | | +// -1 0 1 2 3 4 5 6 +// <------------ 6 x 5us = 30us -----------> +`ASSERT(ChannelStableOnAdcEn_A, + $fell(adc_pd_i) |-> ($past(adc_chnsel_i) == 4'h0)[*8], clk_adc_i, !rst_adc_ni) + +endmodule : adc diff --git a/src/ast/rtl/adc_ana.sv b/src/ast/rtl/adc_ana.sv new file mode 100644 index 0000000..6f4b640 --- /dev/null +++ b/src/ast/rtl/adc_ana.sv @@ -0,0 +1,45 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +//############################################################################ +// *Name: sdc_ana +// *Module Description: ADC Analog +//############################################################################ + +module adc_ana ( + input ast_pkg::awire_t adc_a0_ai, // ADC A0 Analog Input + input ast_pkg::awire_t adc_a1_ai, // ADC A1 Analog Input + output logic [10-1:0] adc_d_ch0_o, // ADC A0 Digital Output + output logic [10-1:0] adc_d_ch1_o // ADC A1 Digital Output +); + +`ifndef SYNTHESIS +// Behavioral Model +//////////////////////////////////////// +real vref = 2.3; +real adc_vi0_hook = 1.0; +real adc_vi1_hook = 1.0; +real adc_vi0, adc_vi1; + +`ifdef ANALOGSIM +assign adc_vi0 = adc_a0_ai; +assign adc_vi1 = adc_a1_ai; +`else +assign adc_vi0 = adc_a0_ai ? adc_vi0_hook : 0.0; +assign adc_vi1 = adc_a1_ai ? adc_vi1_hook : 0.0; +`endif +assign adc_d_ch0_o = $rtoi((adc_vi0/vref) * $itor(10'h3ff)); +assign adc_d_ch1_o = $rtoi((adc_vi1/vref) * $itor(10'h3ff)); +`else // of SYNTHESIS +// FPGA/VERILATOR +//////////////////////////////////////// +logic [10-1:0] adc_d_vi0_hook, adc_d_vi1_hook; + +assign adc_d_vi0_hook = 10'h155; +assign adc_d_vi1_hook = 10'h2AA; + +assign adc_d_ch0_o = adc_a0_ai ? adc_d_vi0_hook : 10'h000; +assign adc_d_ch1_o = adc_a1_ai ? adc_d_vi1_hook : 10'h000; +`endif + +endmodule : adc_ana diff --git a/src/ast/rtl/aon_clk.sv b/src/ast/rtl/aon_clk.sv new file mode 100644 index 0000000..568cba4 --- /dev/null +++ b/src/ast/rtl/aon_clk.sv @@ -0,0 +1,67 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// -------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------- // +// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED. +// +//############################################################################ +// *Name: aon_clk +// *Module Description: Always ON Clock +//############################################################################ + +module aon_clk ( + input vcore_pok_h_i, // VCORE POK @3.3V (for OSC) + input clk_aon_pd_ni, // AON Clock Power-down + input rst_aon_clk_ni, // AON Clock Logic reset + input clk_src_aon_en_i, // AON Source Clock Enable + input scan_mode_i, // Scan Mode + input aon_osc_cal_i, // AON Oscillator Calibrated +`ifdef AST_BYPASS_CLK + input clk_aon_ext_i, // FPGA/VERILATOR Clock input +`endif + output logic clk_src_aon_o, // AON Source Clock + output logic clk_src_aon_val_o // AON Source Clock Valid +); + +logic clk, osc_en, aon_clk_en; + +assign osc_en = (clk_src_aon_en_i && clk_aon_pd_ni && rst_aon_clk_ni); +assign aon_clk_en = scan_mode_i || osc_en; + +// Clock Oscillator +/////////////////////////////////////// +aon_osc u_aon_osc ( + .vcore_pok_h_i ( vcore_pok_h_i ), + .aon_en_i ( aon_clk_en ), + .aon_osc_cal_i ( aon_osc_cal_i ), +`ifdef AST_BYPASS_CLK + .clk_aon_ext_i ( clk_aon_ext_i ), +`endif + .aon_clk_o ( clk ) +); // of u_aon_osc + +// Clock & Valid +/////////////////////////////////////// +prim_clock_buf #( + .NoFpgaBuf ( 1'b1 ) +) u_clk_aon_buf( + .clk_i ( clk ), + .clk_o ( clk_src_aon_o ) +); + +// 2-stage de-assertion +logic rst_val_n; +assign rst_val_n = aon_clk_en; + +prim_flop_2sync #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_no_scan_val_sync ( + .clk_i ( clk_src_aon_o ), + .rst_ni ( rst_val_n ), + .d_i ( 1'b1 ), + .q_o ( clk_src_aon_val_o ) +); + +endmodule : aon_clk diff --git a/src/ast/rtl/aon_osc.sv b/src/ast/rtl/aon_osc.sv new file mode 100644 index 0000000..c18e51c --- /dev/null +++ b/src/ast/rtl/aon_osc.sv @@ -0,0 +1,132 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +//############################################################################ +// *Name: aon_osc +// *Module Description: AON Clock Oscilator +//############################################################################ + +module aon_osc ( + input vcore_pok_h_i, // VCORE POK @3.3V + input aon_en_i, // AON Source Clock Enable + input aon_osc_cal_i, // AON Oscillator Calibrated +`ifdef AST_BYPASS_CLK + input clk_aon_ext_i, // FPGA/VERILATOR Clock input\ +`endif + output logic aon_clk_o // AON Clock Output +); + +`ifndef AST_BYPASS_CLK +`ifndef SYNTHESIS +// Behavioral Model +//////////////////////////////////////// +timeunit 1ns / 10ps; + +real CLK_PERIOD, ckmul; + +reg init_start; +initial init_start = 1'b0; + +initial begin + if ( !$value$plusargs("osc200k_freq_multiplier=%f", ckmul) ) ckmul = 1.0; + #1; + init_start = 1'b1; + #1; + $display("\n%m: AON Base Clock Power-up Frequency: %0d Hz", $rtoi(10**9/(CLK_PERIOD*ckmul))); + $display("%m: AON %0.1fxBase Clock Power-up Frequency: %0d Hz", ckmul, $rtoi(10**9/CLK_PERIOD)); +end + +// Enable 5us RC Delay on rise +wire en_osc_re_buf, en_osc_re; +buf #(ast_bhv_pkg::AON_EN_RDLY, 0) b0 (en_osc_re_buf, (vcore_pok_h_i && aon_en_i)); +assign en_osc_re = en_osc_re_buf && init_start; + +// Clock Oscillator +//////////////////////////////////////// +real CalAonClkPeriod, UncAonClkPeriod, AonClkPeriod; + +initial CalAonClkPeriod = $itor( 5000 ); // 5000ns (200KHz) +initial UncAonClkPeriod = $itor( $urandom_range(10000, 5555) ); // 10000-5555ps (100-180KHz) + +assign AonClkPeriod = (aon_osc_cal_i && init_start) ? CalAonClkPeriod : UncAonClkPeriod; +assign CLK_PERIOD = AonClkPeriod/ckmul; + +// Free running oscillator +reg clk_osc; +initial clk_osc = 1'b1; + +always begin + #(CLK_PERIOD/2) clk_osc = ~clk_osc; +end + +logic en_osc; + +// HDL Clock Gate +logic en_clk, clk; + +always_latch begin + if ( !clk_osc ) en_clk = en_osc; +end + +assign clk = clk_osc && en_clk; +`else // of SYNTHESIS +// SYNTHESIS/LINTER +/////////////////////////////////////// +logic clk, en_osc; +assign clk = 1'b0; + +logic en_osc_re; +assign en_osc_re = vcore_pok_h_i && aon_en_i; +`endif // of SYNTHESIS +`else // of AST_BYPASS_CLK +// VERILATOR/FPGA +/////////////////////////////////////// +logic en_osc_re; +assign en_osc_re = vcore_pok_h_i && aon_en_i; + +// Clock Oscillator +//////////////////////////////////////// +logic clk, en_osc; + +prim_clock_gating #( + .NoFpgaGate ( 1'b1 ) +) u_clk_ckgt ( + .clk_i ( clk_aon_ext_i ), + .en_i ( en_osc ), + .test_en_i ( 1'b0 ), + .clk_o ( clk ) +); +`endif + +logic en_osc_fe; + +// Syncronize en_osc to clk FE for glitch free disable +always_ff @( negedge clk, negedge vcore_pok_h_i ) begin + if ( !vcore_pok_h_i ) begin + en_osc_fe <= 1'b0; + end else begin + en_osc_fe <= en_osc_re; + end +end + +assign en_osc = en_osc_re || en_osc_fe; // EN -> 1 || EN -> 0 + +// Clock Output Buffer +//////////////////////////////////////// +prim_clock_buf #( + .NoFpgaBuf ( 1'b1 ) +) u_buf ( + .clk_i ( clk ), + .clk_o ( aon_clk_o ) +); + + +`ifdef SYNTHESIS +/////////////////////// +// Unused Signals +/////////////////////// +logic unused_sigs; +assign unused_sigs = ^{ aon_osc_cal_i }; +`endif + +endmodule : aon_osc diff --git a/src/ast/rtl/ast.sv b/src/ast/rtl/ast.sv new file mode 100644 index 0000000..d3c084d --- /dev/null +++ b/src/ast/rtl/ast.sv @@ -0,0 +1,1062 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// -------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------- // +// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED. +// +//############################################################################ +// *Name: ast +// *Module Description: Analog Sensors Top +//############################################################################ + +`include "prim_assert.sv" + +module ast #( + parameter int unsigned AdcChannels = 2, + parameter int unsigned AdcDataWidth = 10, + parameter int unsigned EntropyStreams = 4, + parameter int unsigned UsbCalibWidth = 20, + parameter int unsigned Ast2PadOutWidth = 9, + parameter int unsigned Pad2AstInWidth = 9 +) ( + // tlul if + input tlul_pkg::tl_h2d_t tl_i, // TLUL H2D + output tlul_pkg::tl_d2h_t tl_o, // TLUL D2H + output prim_mubi_pkg::mubi4_t ast_init_done_o, // AST (registers) Init Done + + // clocks / resets + input clk_ast_adc_i, // Buffered AST ADC Clock + input rst_ast_adc_ni, // Buffered AST ADC Reset + input clk_ast_alert_i, // Buffered AST Alert Clock + input rst_ast_alert_ni, // Buffered AST Alert Reset + input clk_ast_es_i, // Buffered AST Entropy Source Clock + input rst_ast_es_ni, // Buffered AST Entropy Source Reset + input clk_ast_rng_i, // Buffered AST RNG Clock + input rst_ast_rng_ni, // Buffered AST RNG Reset + input clk_ast_tlul_i, // Buffered AST TLUL Clock + input rst_ast_tlul_ni, // Buffered AST TLUL Reset + input clk_ast_usb_i, // Buffered AST USB Clock + input rst_ast_usb_ni, // Buffered AST USB Reset + input clk_ast_ext_i, // Buffered AST External Clock + input por_ni, // Power ON Reset + + // sensed clocks / resets + input clkmgr_pkg::clkmgr_out_t sns_clks_i, // Sensed Clocks + input rstmgr_pkg::rstmgr_out_t sns_rsts_i, // Sensed Resets + input sns_spi_ext_clk_i, // Sensed SPI External Clock + +`ifdef AST_BYPASS_CLK + // Clocks' Oschillator bypass for OS FPGA + input ast_pkg::clks_osc_byp_t clk_osc_byp_i, // Clocks' Oschillator bypass for OS FPGA/VERILATOR +`endif + + // power OK control + // In non-power aware DV environment, the <>_supp_i is for debug only! + // POK signal follow this input. + // In a power aware environment this signal should be connected to constant '1' + input vcc_supp_i, // VCC Supply Test for OS FPGA + input vcaon_supp_i, // VCAON Supply Test for OS FPGA + input vcmain_supp_i, // VCMAIN Supply Test for OS FPGA + input vioa_supp_i, // VIOA Rail Supply Test for OS FPGA + input viob_supp_i, // VIOB Rail Supply Test for OS FPGA + output ast_pkg::ast_pwst_t ast_pwst_o, // AON, MAIN, IO-0 Rail, IO-1 Rail Power OK @1.1V + output ast_pkg::ast_pwst_t ast_pwst_h_o, // AON, MAIN, IO-9 Rail, IO-1 Rail Power OK @3.3V + + // Power and IO pin connections + input main_pd_ni, // MAIN Regulator Power Down + input main_env_iso_en_i, // Enveloped ISOlation ENable for MAIN + + // power down monitor logic - flash/otp related + output logic flash_power_down_h_o, // Flash Power Down + output logic flash_power_ready_h_o, // Flash Power Ready + input [1:0] otp_power_seq_i, // MMR0,24 in (VDD) + output logic [1:0] otp_power_seq_h_o, // MMR0,24 masked by PDM, out (VCC) + + // system source clock + input clk_src_sys_en_i, // SYS Source Clock Enable + input prim_mubi_pkg::mubi4_t clk_src_sys_jen_i, // SYS Source Clock Jitter Enable + output logic clk_src_sys_o, // SYS Source Clock + output logic clk_src_sys_val_o, // SYS Source Clock Valid + + // aon source clock + output logic clk_src_aon_o, // AON Source Clock + output logic clk_src_aon_val_o, // AON Source Clock Valid + + // io source clock + input clk_src_io_en_i, // IO Source Clock Enable + output logic clk_src_io_o, // IO Source Clock + output logic clk_src_io_val_o, // IO Source Clock Valid + output prim_mubi_pkg::mubi4_t clk_src_io_48m_o, // IO Source Clock is 48MHz + + // usb source clock + input usb_ref_pulse_i, // USB Reference Pulse + input usb_ref_val_i, // USB Reference Valid + input clk_src_usb_en_i, // USB Source Clock Enable + output logic clk_src_usb_o, // USB Source Clock + output logic clk_src_usb_val_o, // USB Source Clock Valid + output logic [UsbCalibWidth-1:0] usb_io_pu_cal_o, // USB IO Pull-up Calibration Setting + + // adc interface + input adc_pd_i, // ADC Power Down + input ast_pkg::awire_t adc_a0_ai, // ADC A0 Analog Input + input ast_pkg::awire_t adc_a1_ai, // ADC A1 Analog Input + input [AdcChannels-1:0] adc_chnsel_i, // ADC Channel Select + output [AdcDataWidth-1:0] adc_d_o, // ADC Digital (per channel) + output adc_d_val_o, // ADC Digital Valid + + // rng (entropy source) interface + input rng_en_i, // RNG Enable + input rng_fips_i, // RNG FIPS + output logic rng_val_o, // RNG Valid + output logic [EntropyStreams-1:0] rng_b_o, // RNG Bit(s) + + // entropy distribution interface + input edn_pkg::edn_rsp_t entropy_rsp_i, // Entropy Response + output edn_pkg::edn_req_t entropy_req_o, // Entropy Request + + // alerts + input ast_pkg::ast_alert_rsp_t alert_rsp_i, // Alerts Trigger & Acknowledge Inputs + output ast_pkg::ast_alert_req_t alert_req_o, // Alerts Output + + // dft interface + input pinmux_pkg::dft_strap_test_req_t dft_strap_test_i, // DFT Straps + input caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_t caliptra_ss_lc_dft_en_i, // DFT enable (secure bus) + input [8-1:0] fla_obs_i, // FLASH Observe Bus + input [8-1:0] otp_obs_i, // OTP Observe Bus + input [8-1:0] otm_obs_i, // OT Modules Observe Bus + input usb_obs_i, // USB DIFF RX Observe + output ast_pkg::ast_obs_ctrl_t obs_ctrl_o, // Observe Control + + // pad mux/pad related + input [Pad2AstInWidth-1:0] padmux2ast_i, // IO_2_DFT Input Signals + output logic [Ast2PadOutWidth-1:0] ast2padmux_o, // DFT_2_IO Output Signals + +`ifdef ANALOGSIM + output real ast2pad_t0_ao, // AST_2_PAD Analog T0 Output Signal + output real ast2pad_t1_ao, // AST_2_PAD Analog T1 Output Signal +`else + output wire ast2pad_t0_ao, // AST_2_PAD Analog T0 Output Signal + output wire ast2pad_t1_ao, // AST_2_PAD Analog T1 Output Signal +`endif + + // flash and external clocks + input prim_mubi_pkg::mubi4_t ext_freq_is_96m_i, // External clock frequecy is 96MHz + input prim_mubi_pkg::mubi4_t all_clk_byp_req_i, // All clocks bypass request + output prim_mubi_pkg::mubi4_t all_clk_byp_ack_o, // Switch all clocks to External clocks + input prim_mubi_pkg::mubi4_t io_clk_byp_req_i, // IO clock bypass request (for OTP bootstrap) + output prim_mubi_pkg::mubi4_t io_clk_byp_ack_o, // Switch IO clock to External clockn + output prim_mubi_pkg::mubi4_t flash_bist_en_o, // Flush BIST (TAP) Enable + + // memories read-write margins + output ast_pkg::dpm_rm_t dpram_rmf_o, // Dual Port RAM Read-write Margin Fast + output ast_pkg::dpm_rm_t dpram_rml_o, // Dual Port RAM Read-write Margin sLow + output ast_pkg::spm_rm_t spram_rm_o, // Single Port RAM Read-write Margin + output ast_pkg::spm_rm_t sprgf_rm_o, // Single Port Reg-File Read-write Margin + output ast_pkg::spm_rm_t sprom_rm_o, // Single Port ROM Read-write Margin + + // Scan interface + output prim_mubi_pkg::mubi4_t dft_scan_md_o, // Scan Mode output + output scan_shift_en_o, // Scan Shift Enable output + output scan_reset_no // Scan Reset output +); + +import ast_pkg::* ; +import ast_reg_pkg::* ; +import ast_bhv_pkg::* ; + +logic scan_mode, shift_en, scan_reset_n; +logic vcc_pok, vcc_pok_h, vcc_pok_str; +logic vcaon_pok, vcaon_pok_h, vcmain_pok; +logic vcaon_pok_por, vcmain_pok_por; + +// Local (AST) System clock buffer +//////////////////////////////////////// +logic clk_sys; + +prim_clock_buf #( + .NoFpgaBuf ( 1'b1 ) +) u_clk_sys_buf ( + .clk_i ( clk_src_sys_o ), + .clk_o ( clk_sys ) +); + +// Local (AST) AON clock buffer +//////////////////////////////////////// +logic clk_aon; + +prim_clock_buf #( + .NoFpgaBuf ( 1'b1 ) +) u_clk_aon_buf ( + .clk_i ( clk_src_aon_o ), + .clk_o ( clk_aon ) +); + + +assign flash_bist_en_o = prim_mubi_pkg::MuBi4False; +// +assign dft_scan_md_o = prim_mubi_pkg::MuBi4False; +assign scan_shift_en_o = 1'b0; +assign scan_reset_no = 1'b1; +assign scan_mode = 1'b0; +assign shift_en = 1'b0; +assign scan_reset_n = 1'b1; + + +/////////////////////////////////////// +// VCC POK (Always ON) +/////////////////////////////////////// +logic vcc_pok_int; + +vcc_pgd u_vcc_pok ( + .vcc_pok_o ( vcc_pok_int ) +); + +assign vcc_pok = vcc_pok_int && vcc_supp_i; +assign vcc_pok_h = vcc_pok; // "Level Shifter" + + +//////////////////////////////////////// +// VCAON POK POR (Always ON) +/////////////////////////////////////// +logic rst_poks_n, rst_poks_por_n, por_sync_n; +logic vcaon_pok_por_src, vcaon_pok_por_lat, poks_por_ack, rglssm_vcmon, rglssm_brout; + +assign rst_poks_n = vcc_pok_str && vcaon_pok; +assign rst_poks_por_n = vcc_pok_str && vcaon_pok && por_ni; +assign poks_por_ack = vcaon_pok_por_src || rglssm_vcmon; + +// Reset De-Assert Sync +prim_flop_2sync #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_no_scan_poks_por_dasrt ( + .clk_i ( clk_aon ), + .rst_ni ( rst_poks_por_n ), + .d_i ( poks_por_ack ), + .q_o ( vcaon_pok_por_src ) +); + +logic clk_aon_n; + +prim_clock_inv #( + .HasScanMode ( 1 ) +) u_clk_aon_inv ( + .clk_i ( clk_aon ), + .scanmode_i ( scan_mode ), + .clk_no ( clk_aon_n ) +); + +prim_flop #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_no_scan_por_sync_n ( + .clk_i ( clk_aon_n ), + .rst_ni ( rst_poks_n ), + .d_i ( vcaon_pok_por_src ), + .q_o ( por_sync_n ) +); + +// Replace Latch for the OS code +assign vcaon_pok_por_lat = rglssm_brout || por_sync_n; +assign ast_pwst_o.aon_pok = vcaon_pok_por_lat; +assign vcaon_pok_por = scan_mode ? scan_reset_n : vcaon_pok_por_lat; + + +//////////////////////////////////////// +// VCMAIN POK POR (Always ON) +/////////////////////////////////////// +logic rglssm_vmppr, vcmain_pok_por_src; + +assign vcmain_pok_por_src = vcaon_pok_por_lat && vcmain_pok && !rglssm_vmppr; +assign ast_pwst_o.main_pok = vcmain_pok_por_src; +assign vcmain_pok_por = scan_mode ? scan_reset_n : vcmain_pok_por_src; + + +/////////////////////////////////////// +// VIOA POK (Always ON) +/////////////////////////////////////// +logic vioa_pok; +logic vioa_pok_int; + +vio_pgd u_vioa_pok ( + .vio_pok_o ( vioa_pok_int ) +); + +assign vioa_pok = vioa_pok_int && vioa_supp_i; +assign ast_pwst_o.io_pok[0] = vcaon_pok && vioa_pok; + + +/////////////////////////////////////// +// VIOB POK (Always ON) +/////////////////////////////////////// +logic viob_pok; +logic viob_pok_int; + +vio_pgd u_viob_pok ( + .vio_pok_o ( viob_pok_int ) +); + +assign viob_pok = viob_pok_int && viob_supp_i; +assign ast_pwst_o.io_pok[1] = vcaon_pok && viob_pok; + + +/////////////////////////////////////// +// Regulators & PDM Logic (VCC) +/////////////////////////////////////// +logic deep_sleep; +logic main_pd, por_sync; + +assign main_pd = !main_pd_ni; +assign por_sync = !por_sync_n; + +rglts_pdm_3p3v u_rglts_pdm_3p3v ( + .vcc_pok_h_i ( vcc_pok_h ), + .vcaon_pok_por_h_i ( vcaon_pok_por_src ), + .vcmain_pok_por_h_i ( vcmain_pok_por_src ), + .vio_pok_h_i ( ast_pwst_o.io_pok[1:0] ), + .clk_src_aon_h_i ( clk_aon ), + .main_pd_h_i ( main_pd ), + .por_sync_h_i ( por_sync ), + .scan_mode_h_i ( scan_mode ), + .otp_power_seq_h_i ( otp_power_seq_i[2-1:0] ), + .vcaon_supp_i ( vcaon_supp_i ), + .vcmain_supp_i ( vcmain_supp_i ), + .rglssm_vmppr_h_o ( rglssm_vmppr ), + .rglssm_vcmon_h_o ( rglssm_vcmon ), + .rglssm_brout_h_o ( rglssm_brout ), + .vcmain_pok_h_o ( vcmain_pok ), + .vcmain_pok_por_h_o ( ast_pwst_h_o.main_pok ), + .vcaon_pok_h_o ( vcaon_pok_h ), + .vcaon_pok_1p1_h_o ( vcaon_pok ), + .vcaon_pok_por_h_o ( ast_pwst_h_o.aon_pok ), + .vio_pok_h_o ( ast_pwst_h_o.io_pok[2-1:0] ), + .vcc_pok_str_h_o ( ast_pwst_h_o.vcc_pok ), + .vcc_pok_str_1p1_h_o ( vcc_pok_str ), + .deep_sleep_h_o ( deep_sleep ), + .flash_power_down_h_o ( flash_power_down_h_o ), + .flash_power_ready_h_o ( flash_power_ready_h_o ), + .otp_power_seq_h_o ( otp_power_seq_h_o[2-1:0] ) +); + +assign ast_pwst_o.vcc_pok = vcc_pok_str; + + +/////////////////////////////////////// +/////////////////////////////////////// +// Clocks Oscillattors +/////////////////////////////////////// +/////////////////////////////////////// + + +/////////////////////////////////////// +// System Clock (Always ON) +/////////////////////////////////////// +logic rst_sys_clk_n, clk_sys_pd_n; +logic clk_sys_en, clk_osc_sys, clk_osc_sys_val; +prim_mubi_pkg::mubi4_t clk_src_sys_jen; + +assign rst_sys_clk_n = vcmain_pok_por && vcc_pok; +assign clk_sys_pd_n = scan_mode || !deep_sleep; + +logic sys_io_osc_cal; + +assign clk_sys_en = clk_src_sys_en_i; + +`ifdef AST_BYPASS_CLK +logic clk_sys_ext; +assign clk_sys_ext = clk_osc_byp_i.sys; +`endif + +sys_clk u_sys_clk ( + .clk_src_sys_jen_i ( prim_mubi_pkg::mubi4_test_true_loose(clk_src_sys_jen) ), + .clk_src_sys_en_i ( clk_sys_en ), + .clk_sys_pd_ni ( clk_sys_pd_n ), + .rst_sys_clk_ni ( rst_sys_clk_n ), + .vcore_pok_h_i ( vcaon_pok_h ), + .scan_mode_i ( scan_mode ), + .sys_osc_cal_i ( sys_io_osc_cal ), +`ifdef AST_BYPASS_CLK + .clk_sys_ext_i ( clk_sys_ext ), +`endif + .clk_src_sys_o ( clk_osc_sys ), + .clk_src_sys_val_o ( clk_osc_sys_val ) +); + + +/////////////////////////////////////// +// USB Clock (Always ON) +/////////////////////////////////////// +logic rst_usb_clk_n, clk_usb_pd_n; +logic clk_usb_en, clk_osc_usb, clk_osc_usb_val; +logic usb_ref_val, usb_ref_pulse; + +assign rst_usb_clk_n = vcmain_pok_por && vcc_pok; +assign clk_usb_pd_n = scan_mode || !deep_sleep; + +logic usb_osc_cal; + +`ifdef AST_BYPASS_CLK +logic clk_usb_ext; +assign clk_usb_ext = clk_osc_byp_i.usb; +`endif + +assign clk_usb_en = clk_src_usb_en_i; +assign usb_ref_val = usb_ref_val_i; +assign usb_ref_pulse = usb_ref_pulse_i; + +usb_clk u_usb_clk ( + .vcore_pok_h_i ( vcaon_pok_h ), + .clk_usb_pd_ni ( clk_usb_pd_n ), + .rst_usb_clk_ni ( rst_usb_clk_n ), + .clk_src_usb_en_i ( clk_usb_en ), + .usb_ref_val_i ( usb_ref_val ), + .usb_ref_pulse_i ( usb_ref_pulse ), + .clk_ast_usb_i ( clk_ast_usb_i ), + .rst_ast_usb_ni ( rst_ast_usb_ni ), + .scan_mode_i ( scan_mode ), + .usb_osc_cal_i ( usb_osc_cal ), +`ifdef AST_BYPASS_CLK + .clk_usb_ext_i ( clk_usb_ext ), +`endif + .clk_src_usb_o ( clk_osc_usb ), + .clk_src_usb_val_o ( clk_osc_usb_val ) +); + + +/////////////////////////////////////// +// AON Clock (Always ON) +/////////////////////////////////////// +logic rst_aon_clk_n; +logic clk_src_aon_en, clk_osc_aon, clk_osc_aon_val; +logic aon_osc_cal; + +`ifdef AST_BYPASS_CLK +logic clk_aon_ext; +assign clk_aon_ext = clk_osc_byp_i.aon; +`endif + +assign rst_aon_clk_n = vcc_pok_str && vcaon_pok; +assign clk_src_aon_en = 1'b1; // Always Enabled + +aon_clk u_aon_clk ( + .vcore_pok_h_i ( vcaon_pok_h ), + .clk_aon_pd_ni ( 1'b1 ), // Always Enabled + .rst_aon_clk_ni ( rst_aon_clk_n ), + .clk_src_aon_en_i ( clk_src_aon_en ), + .scan_mode_i ( scan_mode ), + .aon_osc_cal_i ( aon_osc_cal ), +`ifdef AST_BYPASS_CLK + .clk_aon_ext_i ( clk_aon_ext ), +`endif + .clk_src_aon_o ( clk_osc_aon ), + .clk_src_aon_val_o ( clk_osc_aon_val ) +); + +logic vcmpp_aon_sync_n, rst_vcmpp_aon_n; + +// Reset De-Assert Sync +prim_flop_2sync #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_rst_vcmpp_aon_dasrt ( + .clk_i ( clk_aon ), + .rst_ni ( vcmain_pok_por ), + .d_i ( 1'b1 ), + .q_o ( vcmpp_aon_sync_n ) +); + +assign rst_vcmpp_aon_n = scan_mode ? scan_reset_n : vcmpp_aon_sync_n; + + +/////////////////////////////////////// +// IO Clock (Always ON) +/////////////////////////////////////// +logic rst_io_clk_n, clk_io_pd_n; +logic clk_src_io_en, clk_osc_io, clk_osc_io_val; + +assign rst_io_clk_n = vcmain_pok_por && vcc_pok; +assign clk_io_pd_n = scan_mode || !deep_sleep; + +`ifdef AST_BYPASS_CLK +logic clk_io_ext; +assign clk_io_ext = clk_osc_byp_i.io; +`endif + +assign clk_src_io_en = clk_src_io_en_i; + +io_clk u_io_clk ( + .vcore_pok_h_i ( vcaon_pok_h ), + .clk_io_pd_ni ( clk_io_pd_n ), + .rst_io_clk_ni ( rst_io_clk_n ), + .clk_src_io_en_i ( clk_src_io_en ), + .scan_mode_i ( scan_mode ), + .io_osc_cal_i ( sys_io_osc_cal ), +`ifdef AST_BYPASS_CLK + .clk_io_ext_i ( clk_io_ext ), +`endif + .clk_src_io_o ( clk_osc_io ), + .clk_src_io_val_o ( clk_osc_io_val ) +); + + +/////////////////////////////////////// +// AST Clocks Bypass +/////////////////////////////////////// +logic clk_src_sys, clk_src_io, clk_src_usb, clk_src_aon; + +ast_clks_byp u_ast_clks_byp ( + .vcaon_pok_i ( vcaon_pok ), + .vcaon_pok_por_i ( vcaon_pok_por ), + .deep_sleep_i ( deep_sleep ), + .clk_src_sys_en_i ( clk_src_sys_en_i ), + .clk_osc_sys_i ( clk_osc_sys ), + .clk_osc_sys_val_i ( clk_osc_sys_val ), + .clk_src_io_en_i ( clk_src_io_en_i ), + .clk_osc_io_i ( clk_osc_io ), + .clk_osc_io_val_i ( clk_osc_io_val ), + .clk_src_usb_en_i ( clk_src_usb_en_i ), + .clk_osc_usb_i ( clk_osc_usb ), + .clk_osc_usb_val_i ( clk_osc_usb_val ), + .clk_osc_aon_i ( clk_osc_aon ), + .clk_osc_aon_val_i ( clk_osc_aon_val ), + .clk_ast_ext_i ( clk_ast_ext_i ), +`ifdef AST_BYPASS_CLK + .clk_ext_sys_i( clk_sys_ext ), + .clk_ext_io_i( clk_io_ext ), + .clk_ext_usb_i( clk_usb_ext ), + .clk_ext_aon_i( clk_aon_ext ), +`endif + .io_clk_byp_req_i ( io_clk_byp_req_i ), + .all_clk_byp_req_i ( all_clk_byp_req_i ), + .ext_freq_is_96m_i ( ext_freq_is_96m_i ), + .io_clk_byp_ack_o ( io_clk_byp_ack_o ), + .all_clk_byp_ack_o ( all_clk_byp_ack_o ), + .clk_src_sys_o ( clk_src_sys ), + .clk_src_sys_val_o ( clk_src_sys_val_o ), + .clk_src_io_o ( clk_src_io ), + .clk_src_io_val_o ( clk_src_io_val_o ), + .clk_src_io_48m_o ( clk_src_io_48m_o ), + .clk_src_usb_o ( clk_src_usb ), + .clk_src_usb_val_o ( clk_src_usb_val_o ), + .clk_src_aon_o ( clk_src_aon ), + .clk_src_aon_val_o ( clk_src_aon_val_o ) +); + +// System source clock buffer +//////////////////////////////////////// +prim_clock_buf #( + .NoFpgaBuf ( 1'b1 ) +) u_clk_src_sys_buf ( + .clk_i ( clk_src_sys ), + .clk_o ( clk_src_sys_o ) +); + +// IO source clock buffer +//////////////////////////////////////// +prim_clock_buf #( + .NoFpgaBuf ( 1'b1 ) +) u_clk_src_io_buf ( + .clk_i ( clk_src_io ), + .clk_o ( clk_src_io_o ) +); + +// USB source clock buffer +//////////////////////////////////////// +prim_clock_buf #( + .NoFpgaBuf ( 1'b1 ) +) u_clk_src_usb_buf ( + .clk_i ( clk_src_usb ), + .clk_o ( clk_src_usb_o ) +); + +// AON source clock buffer +//////////////////////////////////////// +prim_clock_buf #( + .NoFpgaBuf ( 1'b1 ) +) u_clk_src_aon_buf ( + .clk_i ( clk_src_aon ), + .clk_o ( clk_src_aon_o ) +); + + +/////////////////////////////////////// +// ADC (Always ON) +/////////////////////////////////////// +adc #( + .AdcCnvtClks ( AdcCnvtClks ), + .AdcChannels ( AdcChannels ), + .AdcDataWidth ( AdcDataWidth ) +) u_adc ( + .adc_a0_ai ( adc_a0_ai ), + .adc_a1_ai ( adc_a1_ai ), + .adc_chnsel_i ( adc_chnsel_i[AdcChannels-1:0] ), + .adc_pd_i ( adc_pd_i ), + .clk_adc_i ( clk_ast_adc_i ), + .rst_adc_ni ( rst_ast_adc_ni ), + .adc_d_o ( adc_d_o[AdcDataWidth-1:0] ), + .adc_d_val_o ( adc_d_val_o ) +); + + +/////////////////////////////////////// +// Entropy (Always ON) +/////////////////////////////////////// +localparam int EntropyRateWidth = 4; +logic [EntropyRateWidth-1:0] entropy_rate; +logic vcmain_pok_por_sys, rst_src_sys_n; + +// Sync clk_src_sys_jen_i to clk_sys +prim_mubi4_sync #( + .NumCopies ( 1 ), + .AsyncOn ( 1 ), + .StabilityCheck ( 1 ), + .ResetValue (prim_mubi_pkg::MuBi4False ) +) u_jitter_en_sync ( + .clk_i ( clk_sys ), + .rst_ni ( rst_src_sys_n ), + .mubi_i ( clk_src_sys_jen_i ), + .mubi_o ( {clk_src_sys_jen} ) +); + +// Reset De-Assert Sync +prim_flop_2sync #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_rst_sys_dasrt ( + .clk_i ( clk_sys ), + .rst_ni ( vcmain_pok_por ), + .d_i ( 1'b1 ), + .q_o ( vcmain_pok_por_sys ) +); + +assign rst_src_sys_n = scan_mode ? scan_reset_n : vcmain_pok_por_sys; + +`ifndef SYNTHESIS +logic [EntropyRateWidth-1:0] dv_entropy_rate_value; + +initial begin : erate_plusargs + dv_entropy_rate_value = EntropyRateWidth'($urandom_range(0, (2**EntropyRateWidth -1))); + void'($value$plusargs("entropy_rate_value=%0d", dv_entropy_rate_value)); + `ASSERT_I(DvErateValueCheck, dv_entropy_rate_value inside {[0:(2**EntropyRateWidth -1)]}) +end + +assign entropy_rate = dv_entropy_rate_value; +`else +assign entropy_rate = EntropyRateWidth'(5); +`endif + +ast_entropy #( + .EntropyRateWidth ( EntropyRateWidth ) +) u_entropy ( + .entropy_rsp_i ( entropy_rsp_i ), + .entropy_rate_i ( entropy_rate[EntropyRateWidth-1:0] ), + .clk_ast_es_i ( clk_ast_es_i ), + .rst_ast_es_ni ( rst_ast_es_ni ), + .clk_src_sys_i ( clk_sys ), + .rst_src_sys_ni ( rst_src_sys_n ), + .clk_src_sys_val_i ( clk_src_sys_val_o ), + .clk_src_sys_jen_i ( prim_mubi_pkg::mubi4_test_true_loose(clk_src_sys_jen) ), + .entropy_req_o ( entropy_req_o ) +); + + +/////////////////////////////////////// +// RNG (Always ON) +/////////////////////////////////////// +ast_pkg::ast_dif_t ot1_alert_src; + +rng #( + .EntropyStreams ( EntropyStreams ) +) u_rng ( + .clk_i ( clk_ast_tlul_i ), + .rst_ni ( rst_ast_tlul_ni ), + .clk_ast_rng_i ( clk_ast_rng_i ), + .rst_ast_rng_ni ( rst_ast_rng_ni ), + .rng_en_i ( rng_en_i ), + .rng_fips_i ( rng_fips_i ), + .scan_mode_i ( scan_mode ), + .rng_b_o ( rng_b_o[EntropyStreams-1:0] ), + .rng_val_o ( rng_val_o ) +); + + +/////////////////////////////////////// +// Alerts (Always ON) +/////////////////////////////////////// +ast_pkg::ast_dif_t as_alert_src; +ast_pkg::ast_dif_t cgc_alert_src; +ast_pkg::ast_dif_t gd_alert_src; +ast_pkg::ast_dif_t ts_alert_hi_src; +ast_pkg::ast_dif_t ts_alert_lo_src; +ast_pkg::ast_dif_t ot0_alert_src; +ast_pkg::ast_dif_t ot2_alert_src; +ast_pkg::ast_dif_t ot3_alert_src; +ast_pkg::ast_dif_t ot4_alert_src; +ast_pkg::ast_dif_t ot5_alert_src; + + +// Active Shield (AS) +/////////////////////////////////////// +ast_alert u_alert_as ( + .clk_i ( clk_ast_alert_i ), + .rst_ni ( rst_ast_alert_ni ), + .alert_src_i ( as_alert_src ), + .alert_trig_i ( alert_rsp_i.alerts_trig[ast_pkg::AsSel] ), + .alert_ack_i ( alert_rsp_i.alerts_ack[ast_pkg::AsSel] ), + .alert_req_o ( alert_req_o.alerts[ast_pkg::AsSel] ) +); + +// Clock Glitch (CG) +/////////////////////////////////////// +ast_alert u_alert_cg ( + .clk_i ( clk_ast_alert_i ), + .rst_ni ( rst_ast_alert_ni ), + .alert_src_i ( cgc_alert_src ), + .alert_trig_i ( alert_rsp_i.alerts_trig[ast_pkg::CgSel] ), + .alert_ack_i ( alert_rsp_i.alerts_ack[ast_pkg::CgSel] ), + .alert_req_o ( alert_req_o.alerts[ast_pkg::CgSel] ) +); + +// Glitch Detector (GD) +/////////////////////////////////////// +ast_alert u_alert_gd ( + .clk_i ( clk_ast_alert_i ), + .rst_ni ( rst_ast_alert_ni ), + .alert_src_i ( gd_alert_src ), + .alert_trig_i ( alert_rsp_i.alerts_trig[ast_pkg::GdSel] ), + .alert_ack_i ( alert_rsp_i.alerts_ack[ast_pkg::GdSel] ), + .alert_req_o ( alert_req_o.alerts[ast_pkg::GdSel] ) +); + +// Temprature Sensor High (TS Hi) +/////////////////////////////////////// +ast_alert u_alert_ts_hi ( + .clk_i ( clk_ast_alert_i ), + .rst_ni ( rst_ast_alert_ni ), + .alert_src_i ( ts_alert_hi_src ), + .alert_trig_i ( alert_rsp_i.alerts_trig[ast_pkg::TsHiSel] ), + .alert_ack_i ( alert_rsp_i.alerts_ack[ast_pkg::TsHiSel] ), + .alert_req_o ( alert_req_o.alerts[ast_pkg::TsHiSel] ) +); + +// Temprature Sensor Low (TS Lo) +/////////////////////////////////////// +ast_alert u_alert_ts_lo ( + .clk_i ( clk_ast_alert_i ), + .rst_ni ( rst_ast_alert_ni ), + .alert_src_i ( ts_alert_lo_src ), + .alert_trig_i ( alert_rsp_i.alerts_trig[ast_pkg::TsLoSel] ), + .alert_ack_i ( alert_rsp_i.alerts_ack[ast_pkg::TsLoSel] ), + .alert_req_o ( alert_req_o.alerts[ast_pkg::TsLoSel] ) +); + +// Other-0 Alert (OT0) +/////////////////////////////////////// +ast_alert u_alert_ot0 ( + .clk_i ( clk_ast_alert_i ), + .rst_ni ( rst_ast_alert_ni ), + .alert_src_i ( ot0_alert_src ), + .alert_trig_i ( alert_rsp_i.alerts_trig[ast_pkg::Ot0Sel] ), + .alert_ack_i ( alert_rsp_i.alerts_ack[ast_pkg::Ot0Sel] ), + .alert_req_o ( alert_req_o.alerts[ast_pkg::Ot0Sel] ) +); // of u_alert_ot0 + +// Other-1 Alert (OT1) +/////////////////////////////////////// +ast_alert u_alert_ot1 ( + .clk_i ( clk_ast_alert_i ), + .rst_ni ( rst_ast_alert_ni ), + .alert_src_i ( ot1_alert_src ), + .alert_trig_i ( alert_rsp_i.alerts_trig[ast_pkg::Ot1Sel] ), + .alert_ack_i ( alert_rsp_i.alerts_ack[ast_pkg::Ot1Sel] ), + .alert_req_o ( alert_req_o.alerts[ast_pkg::Ot1Sel] ) +); // of u_alert_ot1 + +// Other-2 Alert (OT2) +/////////////////////////////////////// +ast_alert u_alert_ot2 ( + .clk_i ( clk_ast_alert_i ), + .rst_ni ( rst_ast_alert_ni ), + .alert_src_i ( ot2_alert_src ), + .alert_trig_i ( alert_rsp_i.alerts_trig[Ot2Sel] ), + .alert_ack_i ( alert_rsp_i.alerts_ack[Ot2Sel] ), + .alert_req_o ( alert_req_o.alerts[Ot2Sel] ) +); // of u_alert_ot2 + +// Other-3 Alert (OT3) +/////////////////////////////////////// +ast_alert u_alert_ot3 ( + .clk_i ( clk_ast_alert_i ), + .rst_ni ( rst_ast_alert_ni ), + .alert_src_i ( ot3_alert_src ), + .alert_trig_i ( alert_rsp_i.alerts_trig[Ot3Sel] ), + .alert_ack_i ( alert_rsp_i.alerts_ack[Ot3Sel] ), + .alert_req_o ( alert_req_o.alerts[Ot3Sel] ) +); // of u_alert_ot3 + +// Other-4 Alert (OT4) +/////////////////////////////////////// +ast_alert u_alert_ot4 ( + .clk_i ( clk_ast_alert_i ), + .rst_ni ( rst_ast_alert_ni ), + .alert_src_i ( ot4_alert_src ), + .alert_trig_i ( alert_rsp_i.alerts_trig[ast_pkg::Ot4Sel] ), + .alert_ack_i ( alert_rsp_i.alerts_ack[ast_pkg::Ot4Sel] ), + .alert_req_o ( alert_req_o.alerts[ast_pkg::Ot4Sel] ) +); // of u_alert_ot4 + +// Other-5 Alert (OT5) +/////////////////////////////////////// +ast_alert u_alert_ot5 ( + .clk_i ( clk_ast_alert_i ), + .rst_ni ( rst_ast_alert_ni ), + .alert_src_i ( ot5_alert_src ), + .alert_trig_i ( alert_rsp_i.alerts_trig[ast_pkg::Ot5Sel] ), + .alert_ack_i ( alert_rsp_i.alerts_ack[ast_pkg::Ot5Sel] ), + .alert_req_o ( alert_req_o.alerts[ast_pkg::Ot5Sel] ) +); // of u_alert_ot5 + +// Alerts Open-Source Selection +//////////////////////////////////////// +assign as_alert_src = '{p: 1'b0, n: 1'b1}; +assign cgc_alert_src = '{p: 1'b0, n: 1'b1}; +assign gd_alert_src = '{p: 1'b0, n: 1'b1}; +assign ts_alert_hi_src = '{p: 1'b0, n: 1'b1}; +assign ts_alert_lo_src = '{p: 1'b0, n: 1'b1}; +assign ot1_alert_src = '{p: 1'b0, n: 1'b1}; +assign ot2_alert_src = '{p: 1'b0, n: 1'b1}; +assign ot3_alert_src = '{p: 1'b0, n: 1'b1}; +assign ot4_alert_src = '{p: 1'b0, n: 1'b1}; +assign ot5_alert_src = '{p: 1'b0, n: 1'b1}; + + +/////////////////////////////////////// +// AST Registers (Always ON) +/////////////////////////////////////// +ast_reg_pkg::ast_reg2hw_t reg2hw; // Write (To HW) +ast_reg_pkg::ast_hw2reg_t hw2reg; // Read (From HW) +logic intg_err; + +ast_reg_top u_reg ( + .clk_i ( clk_ast_tlul_i ), + .rst_ni ( rst_ast_tlul_ni ), + .tl_i ( tl_i ), + .tl_o ( tl_o ), + .reg2hw ( reg2hw ), + .hw2reg ( hw2reg ), + .intg_err_o ( intg_err ) +); + + +/////////////////////////////////////// +// REGAL Register +/////////////////////////////////////// +logic regal_rst_n; +assign regal_rst_n = rst_ast_tlul_ni; + +logic regal_we; +logic [32-1:0] regal, regal_di; + +assign regal_we = reg2hw.regal.qe; +assign regal_di = reg2hw.regal.q; +assign hw2reg.regal.d = regal; + +// REGAL & AST init done indication +always_ff @( posedge clk_ast_tlul_i, negedge regal_rst_n ) begin + if ( !regal_rst_n ) begin + regal <= ast_reg_pkg::AST_REGAL_RESVAL; + ast_init_done_o <= prim_mubi_pkg::MuBi4False; + end else if ( regal_we ) begin + regal <= regal_di; + ast_init_done_o <= prim_mubi_pkg::MuBi4True; + end +end + +always_ff @( posedge clk_ast_tlul_i, negedge rst_ast_tlul_ni ) begin + if ( !rst_ast_tlul_ni ) begin + sys_io_osc_cal <= 1'b0; + end else if ( regal_we ) begin + sys_io_osc_cal <= 1'b1; + end +end + +always_ff @( posedge clk_ast_tlul_i, negedge vcaon_pok_por ) begin + if ( !vcaon_pok_por ) begin + usb_osc_cal <= 1'b0; + end else if ( regal_we ) begin + usb_osc_cal <= 1'b1; + end +end + +always_ff @( posedge clk_ast_tlul_i, negedge vcaon_pok ) begin + if ( !vcaon_pok ) begin + aon_osc_cal <= 1'b0; + end else if ( regal_we ) begin + aon_osc_cal <= 1'b1; + end +end + +// TLUL Integrity Error +assign ot0_alert_src = '{p: intg_err, n: !intg_err}; + +// USB PU-P and PU-N value selection +assign usb_io_pu_cal_o = UsbCalibWidth'(1 << (UsbCalibWidth[5-1:0]/2)); + + +/////////////////////////////////////// +// DFT (Main | Always ON) +/////////////////////////////////////// +ast_dft u_ast_dft ( + .obs_ctrl_o ( obs_ctrl_o ), + .ast2padmux_o ( ast2padmux_o[Ast2PadOutWidth-1:0] ), + .dpram_rmf_o ( dpram_rmf_o ), + .dpram_rml_o ( dpram_rml_o ), + .spram_rm_o ( spram_rm_o ), + .sprgf_rm_o ( sprgf_rm_o ), + .sprom_rm_o ( sprom_rm_o ) +); + + +//////////////////////////////////////// +// DFT Misc Logic +//////////////////////////////////////// +`ifdef ANALOGSIM +assign ast2pad_t0_ao = 0.0; +assign ast2pad_t1_ao = 0.1; +`else +assign ast2pad_t0_ao = 1'bz; +assign ast2pad_t1_ao = 1'bz; +`endif + + +//////////////// +// Assertions // +//////////////// + +// Clocks +`ASSERT_KNOWN(ClkSrcAonKnownO_A, clk_src_aon_o, 1, ast_pwst_o.aon_pok) +`ASSERT_KNOWN(ClkSrcAonValKnownO_A, clk_src_aon_val_o, clk_src_aon_o, rst_aon_clk_n) +`ASSERT_KNOWN(ClkSrcIoKnownO_A, clk_src_io_o, 1, ast_pwst_o.main_pok) +`ASSERT_KNOWN(ClkSrcIoValKnownO_A, clk_src_io_val_o, clk_src_io_o, rst_io_clk_n) +`ASSERT_KNOWN(ClkSrcIo48mKnownO_A, clk_src_io_48m_o, clk_src_io_o, rst_io_clk_n) +`ASSERT_KNOWN(ClkSrcSysKnownO_A, clk_src_sys_o, 1, ast_pwst_o.main_pok) +`ASSERT_KNOWN(ClkSrcSysValKnownO_A, clk_src_sys_val_o, clk_src_sys_o, rst_sys_clk_n) +`ASSERT_KNOWN(ClkSrcUsbKnownO_A, clk_src_usb_o, 1, ast_pwst_o.main_pok) +`ASSERT_KNOWN(ClkSrcUsbValKnownO_A, clk_src_usb_val_o, clk_src_usb_o, rst_usb_clk_n) +// +`ASSERT_KNOWN(UsbIoPuCalKnownO_A, usb_io_pu_cal_o, clk_ast_tlul_i, ast_pwst_o.aon_pok) +`ASSERT_KNOWN(LcClkBypAckEnKnownO_A, io_clk_byp_ack_o, clk_ast_tlul_i, rst_ast_tlul_ni) +`ASSERT_KNOWN(AllClkBypAckEnKnownO_A, all_clk_byp_ack_o, clk_ast_tlul_i, rst_ast_tlul_ni) +// ADC +`ASSERT_KNOWN(AdcDKnownO_A, adc_d_o, clk_ast_adc_i, rst_ast_adc_ni) +`ASSERT_KNOWN(AdcDValKnownO_A, adc_d_val_o, clk_ast_adc_i, rst_ast_adc_ni) +// RNG +`ASSERT_KNOWN(RngBKnownO_A, rng_b_o, clk_ast_rng_i, rst_ast_rng_ni) +`ASSERT_KNOWN(RngValKnownO_A, rng_val_o, clk_ast_rng_i, rst_ast_rng_ni) +// TLUL +`ASSERT_KNOWN(TlDValidKnownO_A, tl_o.d_valid, clk_ast_tlul_i, rst_ast_tlul_ni) +`ASSERT_KNOWN(TlAReadyKnownO_A, tl_o.a_ready, clk_ast_tlul_i, rst_ast_tlul_ni) +// +`ASSERT_KNOWN(InitDoneKnownO_A, ast_init_done_o, clk_ast_tlul_i, rst_ast_tlul_ni) +// POs +`ASSERT_KNOWN(VcaonPokKnownO_A, ast_pwst_o.aon_pok, clk_src_aon_o, por_ni) +`ASSERT_KNOWN(VcmainPokKnownO_A, ast_pwst_o.main_pok, clk_src_aon_o, por_ni) +`ASSERT_KNOWN(VioaPokKnownO_A, ast_pwst_o.io_pok[0], clk_src_aon_o, por_ni) +`ASSERT_KNOWN(ViobPokKnownO_A, ast_pwst_o.io_pok[1], clk_src_aon_o, por_ni) +`ASSERT_KNOWN(VcaonPokHKnownO_A, ast_pwst_h_o.aon_pok, clk_src_aon_o, por_ni) +`ASSERT_KNOWN(VcmainPokHKnownO_A, ast_pwst_h_o.main_pok, clk_src_aon_o, por_ni) +`ASSERT_KNOWN(VioaPokHKnownO_A, ast_pwst_h_o.io_pok[0], clk_src_aon_o, por_ni) +`ASSERT_KNOWN(ViobPokHKnownO_A, ast_pwst_h_o.io_pok[1], clk_src_aon_o, por_ni) +// FLASH/OTP +`ASSERT_KNOWN(FlashPowerDownKnownO_A, flash_power_down_h_o, 1, ast_pwst_o.main_pok) +`ASSERT_KNOWN(FlashPowerReadyKnownO_A, flash_power_ready_h_o, 1, ast_pwst_o.main_pok) +`ASSERT_KNOWN(OtpPowerSeqKnownO_A, otp_power_seq_h_o, 1, ast_pwst_o.main_pok) +// +// ES +`ASSERT_KNOWN(EntropyReeqKnownO_A, entropy_req_o, clk_ast_es_i,rst_ast_es_ni) +// Alerts +`ASSERT_KNOWN(AlertReqKnownO_A, alert_req_o, clk_ast_alert_i, rst_ast_alert_ni) +// DPRAM/SPRAM +`ASSERT_KNOWN(DpramRmfKnownO_A, dpram_rmf_o, clk_ast_tlul_i, ast_pwst_o.aon_pok) +`ASSERT_KNOWN(DpramRmlKnownO_A, dpram_rml_o, clk_ast_tlul_i, ast_pwst_o.aon_pok) +`ASSERT_KNOWN(SpramRmKnownO_A, spram_rm_o, clk_ast_tlul_i, ast_pwst_o.aon_pok) +`ASSERT_KNOWN(SprgfRmKnownO_A, sprgf_rm_o, clk_ast_tlul_i, ast_pwst_o.aon_pok) +`ASSERT_KNOWN(SpromRmKnownO_A, sprom_rm_o, clk_ast_tlul_i, ast_pwst_o.aon_pok) +// DFT +`ASSERT_KNOWN(Ast2PadmuxKnownO_A, ast2padmux_o, clk_ast_tlul_i, ast_pwst_o.aon_pok) +// SCAN +`ASSERT_KNOWN(DftScanMdKnownO_A, dft_scan_md_o, clk_ast_tlul_i, ast_pwst_o.aon_pok) +`ASSERT_KNOWN(ScanShiftEnKnownO_A, scan_shift_en_o, clk_ast_tlul_i, ast_pwst_o.aon_pok) +`ASSERT_KNOWN(ScanResetKnownO_A, scan_reset_no, clk_ast_tlul_i, ast_pwst_o.aon_pok) +`ASSERT_KNOWN(FlashBistEnKnownO_A, flash_bist_en_o, clk_ast_tlul_i, ast_pwst_o.aon_pok) + +// Alert assertions for reg_we onehot check +`ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ERR(RegWeOnehot_A, + u_reg, alert_req_o.alerts[ast_pkg::Ot0Sel].p, , , clk_ast_alert_i, rst_ast_alert_ni) + + +///////////////////// +// Unused Signals // +///////////////////// +logic unused_sigs; + +assign unused_sigs = ^{ clk_ast_usb_i, + rst_ast_usb_ni, + sns_spi_ext_clk_i, + sns_clks_i, + sns_rsts_i, + intg_err, + shift_en, + main_env_iso_en_i, + rst_vcmpp_aon_n, + padmux2ast_i[Pad2AstInWidth-1:0], + dft_strap_test_i.valid, + dft_strap_test_i.straps[1:0], + caliptra_ss_lc_dft_en_i[3:0], + fla_obs_i[8-1:0], + otp_obs_i[8-1:0], + otm_obs_i[8-1:0], + usb_obs_i, + reg2hw.rega0, + reg2hw.rega1, + reg2hw.rega2, + reg2hw.rega3, + reg2hw.rega4, + reg2hw.rega5, + reg2hw.rega6, + reg2hw.rega7, + reg2hw.rega8, + reg2hw.rega9, + reg2hw.rega10, + reg2hw.rega11, + reg2hw.rega12, + reg2hw.rega13, + reg2hw.rega14, + reg2hw.rega15, + reg2hw.rega16, + reg2hw.rega17, + reg2hw.rega18, + reg2hw.rega19, + reg2hw.rega20, + reg2hw.rega21, + reg2hw.rega22, + reg2hw.rega23, + reg2hw.rega24, + reg2hw.rega25, + reg2hw.rega26, + reg2hw.rega27, + reg2hw.rega28, + reg2hw.rega29, + reg2hw.rega30, + reg2hw.rega31, + reg2hw.rega32, + reg2hw.rega33, + reg2hw.rega34, + reg2hw.rega35, + reg2hw.rega36, + reg2hw.rega37, + reg2hw.regb // [0:3] + }; + +endmodule : ast diff --git a/src/ast/rtl/ast_alert.sv b/src/ast/rtl/ast_alert.sv new file mode 100644 index 0000000..d394139 --- /dev/null +++ b/src/ast/rtl/ast_alert.sv @@ -0,0 +1,77 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// -------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------- // +// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED. +// +//############################################################################ +// *Name: ast_alert +// *Module Description: AST Alert +//############################################################################ + +module ast_alert ( + input clk_i, + input rst_ni, + input ast_pkg::ast_dif_t alert_src_i, + input ast_pkg::ast_dif_t alert_ack_i, + input ast_pkg::ast_dif_t alert_trig_i, + output ast_pkg::ast_dif_t alert_req_o +); + +// Unpack inputs +logic p_alert_src, n_alert_src; +assign p_alert_src = alert_src_i.p; +assign n_alert_src = alert_src_i.n; + +logic p_alert_ack, n_alert_ack; +assign p_alert_ack = alert_ack_i.p; +assign n_alert_ack = alert_ack_i.n; + +logic p_alert_trig, n_alert_trig; +assign p_alert_trig = alert_trig_i.p; +assign n_alert_trig = alert_trig_i.n; + +// Pack outputs +logic p_alert_req, n_alert_req; + +assign alert_req_o.p = p_alert_req; +assign alert_req_o.n = n_alert_req; + +// P Alert +logic p_alert, set_p_alert, clr_p_alert; + +assign set_p_alert = p_alert_src || p_alert_trig; +assign clr_p_alert = !set_p_alert && p_alert_ack; + +always_ff @( posedge clk_i, negedge rst_ni ) begin + if ( !rst_ni ) begin + p_alert <= 1'b0; + end else if ( set_p_alert ) begin + p_alert <= 1'b1; + end else if ( clr_p_alert ) begin + p_alert <= 1'b0; + end +end + +assign p_alert_req = p_alert; + +// N Alert +logic n_alert, set_n_alert, clr_n_alert; + +assign set_n_alert = !(n_alert_src && n_alert_trig); +assign clr_n_alert = !(set_n_alert || n_alert_ack); + +always_ff @( posedge clk_i, negedge rst_ni ) begin + if ( !rst_ni ) begin + n_alert <= 1'b1; + end else if ( set_n_alert ) begin + n_alert <= 1'b0; + end else if ( clr_n_alert ) begin + n_alert <= 1'b1; + end +end + +assign n_alert_req = n_alert; + +endmodule : ast_alert diff --git a/src/ast/rtl/ast_bhv_pkg.sv b/src/ast/rtl/ast_bhv_pkg.sv new file mode 100644 index 0000000..d87f9f8 --- /dev/null +++ b/src/ast/rtl/ast_bhv_pkg.sv @@ -0,0 +1,50 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// -------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------- // +// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED. +// +//############################################################################ +// *Name: ast_bhv_pkg +// *Module Description: AST Behavioral Package +//############################################################################ +`ifdef __AST_BHV_PKG_SV +`else +`define __AST_BHV_PKG_SV + +package ast_bhv_pkg; + + ///////////////////////////////// + // Delay Parameters from Spec + ///////////////////////////////// +`ifndef SYNTHESIS + // POKs + parameter time VCC_POK_RDLY = 3us; + parameter time VCC_POK_FDLY = 500ns; + parameter time VCAON_POK_RDLY = 3us; + parameter time VCAON_POK_FDLY = 500ns; + parameter time VCMAIN_POK_RDLY = 3us; + parameter time VCMAIN_POK_FDLY = 500ns; + parameter time VIO_POK_RDLY = 3us; + parameter time VIO_POK_FDLY = 500ns; + // Main Regulator + parameter time MPVCC_RDLY = 5us; + parameter time MPVCC_FDLY = 100ns; + parameter time MPPD_RDLY = 50us; + parameter time MPPD_FDLY = 1us; + // Clocks + parameter time SYS_EN_RDLY = 5us; + parameter time USB_EN_RDLY = 5us; + // Reduced for simulation from 50ms + parameter time USB_VAL_RDLY = 80ns; // 50ms + parameter time USB_VAL_FDLY = 80ns; + parameter time IO_EN_RDLY = 5us; + parameter time AON_EN_RDLY = 5us; + parameter time RNG_EN_RDLY = 5us; +`endif // of SYNTHESIS + // ADC + parameter int unsigned AdcCnvtClks = 19; + +endpackage // of ast_bhv_pkg +`endif // of __AST_BHV_PKG_SV diff --git a/src/ast/rtl/ast_clks_byp.sv b/src/ast/rtl/ast_clks_byp.sv new file mode 100644 index 0000000..f3f8ec2 --- /dev/null +++ b/src/ast/rtl/ast_clks_byp.sv @@ -0,0 +1,811 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// -------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------- // +// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED. +// +//############################################################################ +// *Name: ast_clks_byp +// *Module Description: AST Clocks Bypass +//############################################################################ + +`include "prim_assert.sv" + +module ast_clks_byp ( + input vcaon_pok_i, // VCAON POK + input vcaon_pok_por_i, // VCAON POK POR + input deep_sleep_i, // Deep Sleep (main regulator & switch are off) + input clk_src_sys_en_i, // SYS Source Clock Enable + input clk_osc_sys_i, // SYS Oscillator Clock + input clk_osc_sys_val_i, // SYS Oscillator Clock Valid + input clk_src_io_en_i, // IO Source Clock Enable + input clk_osc_io_i, // IO Oscillator Clock + input clk_osc_io_val_i, // IO Oscillator Clock Valid + input clk_src_usb_en_i, // USB Source Clock Enable + input clk_osc_usb_i, // USB Oscillator Clock + input clk_osc_usb_val_i, // USB Oscillator Clock Valid + input clk_osc_aon_i, // AON Oscillator Clock + input clk_osc_aon_val_i, // AON Oscillator Clock Valid + input clk_ast_ext_i, // External Clock +`ifdef AST_BYPASS_CLK + input clk_ext_sys_i, + input clk_ext_io_i, + input clk_ext_usb_i, + input clk_ext_aon_i, +`endif // of AST_BYPASS_CLK + input prim_mubi_pkg::mubi4_t io_clk_byp_req_i, // External IO clock mux for OTP bootstrap + input prim_mubi_pkg::mubi4_t all_clk_byp_req_i, // External all clock mux override + input prim_mubi_pkg::mubi4_t ext_freq_is_96m_i, // External Clock Frequecy is 96MHz (else 48MHz) + output prim_mubi_pkg::mubi4_t io_clk_byp_ack_o, // Switch IO clock to External clock + output prim_mubi_pkg::mubi4_t all_clk_byp_ack_o, // Switch all clocks to External clock + output logic clk_src_sys_o, // SYS Source Clock + output logic clk_src_sys_val_o, // SYS Source Clock Valid + output logic clk_src_io_o, // IO Source Clock + output logic clk_src_io_val_o, // IO Source Clock Valid + output prim_mubi_pkg::mubi4_t clk_src_io_48m_o, // IO Source Clock is 48Mhz + output logic clk_src_usb_o, // USB Source Clock + output logic clk_src_usb_val_o, // USB Source Clock Valid + output logic clk_src_aon_o, // AON Source Clock + output logic clk_src_aon_val_o // AON Source Clock Valid +); + +logic scan_mode_i, scan_reset_ni; + +assign scan_mode_i = 1'b0; +assign scan_reset_ni = 1'b1; + +//////////////////////////////////////// +// Local AON clock buffer +//////////////////////////////////////// +logic clk_aon, rst_aon_n; + +prim_clock_buf #( + .NoFpgaBuf ( 1'b1 ) +) u_clk_aon_buf ( + .clk_i ( clk_src_aon_o ), + .clk_o ( clk_aon ) +); + +logic vcaon_pok; // For Spyglass waiver!!! + +assign vcaon_pok = vcaon_pok_i; +assign rst_aon_n = scan_mode_i ? scan_reset_ni : vcaon_pok; + + +//////////////////////////////////////// +// External Clocks Generation +//////////////////////////////////////// +// Enable External Clock for SW Bypass +logic rst_sw_clk_byp_en, sw_all_clk_byp, sw_io_clk_byp; + +always_ff @( posedge clk_aon, negedge rst_aon_n ) begin + if ( !rst_aon_n ) begin + rst_sw_clk_byp_en <= 1'b0; + end else if ( sw_all_clk_byp || sw_io_clk_byp ) begin + rst_sw_clk_byp_en <= 1'b1; + end +end + +logic rst_sw_ckbpe_n, clk_ast_ext_scn, da_rst_sw_ckbpe_n, sw_clk_byp_en; + +assign rst_sw_ckbpe_n = scan_mode_i ? scan_reset_ni : rst_sw_clk_byp_en; +`ifndef AST_BYPASS_CLK +assign clk_ast_ext_scn = scan_mode_i ? clk_osc_sys_i : clk_ast_ext_i; +`else // of AST_BYPASS_CLK +assign clk_ast_ext_scn = scan_mode_i ? clk_osc_sys_i : clk_ext_sys_i; +`endif // of AST_BYPASS_CLK + +// De-Assert Sync +prim_flop_2sync #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_no_scan_rst_sw_ckbpe_dasrt ( + .clk_i ( clk_ast_ext_scn ), + .rst_ni ( rst_sw_ckbpe_n ), + .d_i ( 1'b1 ), + .q_o ( da_rst_sw_ckbpe_n ) +); + +// De-assert with external clock input +always_ff @( negedge clk_ast_ext_scn, negedge da_rst_sw_ckbpe_n ) begin + if ( !da_rst_sw_ckbpe_n ) begin + sw_clk_byp_en <= 1'b0; + end else begin + sw_clk_byp_en <= 1'b1; + end +end + +logic clk_ext_en, clk_ext_scn; + +assign clk_ext_en = sw_clk_byp_en; +`ifdef AST_BYPASS_CLK +logic clk_ast_ext; + +prim_clock_gating #( + .NoFpgaGate(1'b1) +) u_clk_ast_ext_gating ( + .clk_i( clk_ext_sys_i ), + .en_i( clk_ext_en ), + .test_en_i( 1'b0 ), + .clk_o( clk_ast_ext ) +); + +assign clk_ext_scn = scan_mode_i ? clk_osc_sys_i : clk_ast_ext; +`else +//we can't use prim_clock_gating here for the following reason: +//prim_clock_gating default behavior at wakeup: clk_i=1'bx, en_i=don't care --> clk_o=1'bx +//we want to mask that 1'bx as some tests doesn't use clk_ast_ext_i +assign clk_ext_scn = scan_mode_i ? clk_osc_sys_i : (clk_ast_ext_i && clk_ext_en); +`endif + +// Local EXT clock buffer +//////////////////////////////////////// +logic clk_ext; + +prim_clock_buf #( + .NoFpgaBuf ( 1'b1 ) +) u_clk_ext_buf ( + .clk_i ( clk_ext_scn ), + .clk_o ( clk_ext ) +); + +logic rst_aon_n_exda, rst_aon_exda_n; + +prim_flop_2sync #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_rst_aon_n_exda_sync ( + .clk_i ( clk_ext ), + .rst_ni ( rst_aon_n ), + .d_i ( 1'b1 ), + .q_o ( rst_aon_n_exda ) +); + +assign rst_aon_exda_n = scan_mode_i ? scan_reset_ni : rst_aon_n_exda; + +// External USB & AON clocks genaration +//////////////////////////////////////// +`ifndef AST_BYPASS_CLK +logic clk_src_ext_usb, ext_freq_is_96m, ext_freq_is_96m_sync; + +prim_flop_2sync #( + .Width ( 1 ), + // Assume external clock is 96Hhz on reset + .ResetValue ( 1'b1 ) +) u_no_scan_ext_freq_is_96m_sync ( + .clk_i ( clk_ext ), + .rst_ni ( rst_aon_exda_n ), + .d_i ( ext_freq_is_96m ), + .q_o ( ext_freq_is_96m_sync ) +); + +prim_clock_div #( + .Divisor( 2 ) +) u_no_scan_clk_ext_d1ord2 ( + .clk_i ( clk_ext ), + .rst_ni ( rst_aon_exda_n ), + .step_down_req_i( !ext_freq_is_96m_sync ), + .step_down_ack_o ( ), + .test_en_i ( scan_mode_i ), + .clk_o ( clk_src_ext_usb ) +); +`else // of AST_BYPASS_CLK +logic clk_src_ext_usb, ext_freq_is_96m; +assign clk_src_ext_usb = clk_ext_usb_i; +`endif // of AST_BYPASS_CLK + +logic clk_ext_aon, clk_ext_aon_val; + +assign clk_ext_aon_val = 1'b1; // Always ON clock + +`ifndef AST_BYPASS_CLK +prim_clock_div #( + .Divisor( 240 ) +) u_no_scan_clk_usb_div240_div ( + .clk_i ( clk_src_ext_usb ), + .rst_ni ( rst_aon_exda_n ), + .step_down_req_i( 1'b0 ), + .step_down_ack_o ( ), + .test_en_i ( scan_mode_i ), + .clk_o ( clk_ext_aon ) +); +`else // of AST_BYPASS_CLK +assign clk_ext_aon = clk_ext_aon_i; +`endif // of AST_BYPASS_CLK + + +//////////////////////////////////////// +// Deep-Sleep/Enables Gators +//////////////////////////////////////// + +// Deep-Sleep Sync to External clcok +//////////////////////////////////////// +logic deep_sleep, deep_sleep_n; + +prim_flop_2sync #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_deep_sleep_sync ( + .clk_i ( clk_ext ), + .rst_ni ( rst_aon_exda_n ), + .d_i ( deep_sleep_i ), + .q_o ( deep_sleep ) +); + +assign deep_sleep_n = !deep_sleep; + +// SYS External Clock Enable +//////////////////////////////////////// +logic clk_ext_sys, clk_ext_sys_en, clk_ext_sys_val; +logic clk_src_sys_en; + +prim_flop_2sync #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_no_scan_clk_src_sys_en_sync ( + .clk_i ( clk_ext ), + .rst_ni ( rst_aon_exda_n ), + .d_i ( clk_src_sys_en_i ), + .q_o ( clk_src_sys_en ) +); + +assign clk_ext_sys_en = deep_sleep_n && clk_src_sys_en; +assign clk_ext_sys_val = clk_ext_sys_en; + +prim_clock_gating #( + .NoFpgaGate ( 1'b1) +) u_clk_ext_sys_ckgt ( + .clk_i ( clk_ext ), + .en_i ( clk_ext_sys_en ), + .test_en_i ( scan_mode_i ), + .clk_o ( clk_ext_sys ) +); + +// IO External Clock Enable +//////////////////////////////////////// +logic clk_ext_io, clk_ext_io_en, clk_ext_io_val; +logic clk_src_io_en; + +prim_flop_2sync #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_no_scan_clk_src_io_en_sync ( + .clk_i ( clk_ext ), + .rst_ni ( rst_aon_exda_n ), + .d_i ( clk_src_io_en_i ), + .q_o ( clk_src_io_en ) +); + +assign clk_ext_io_en = deep_sleep_n && clk_src_io_en; +assign clk_ext_io_val = clk_ext_io_en; + +prim_clock_gating #( + .NoFpgaGate ( 1'b1) +) u_clk_ext_io_ckgt ( +`ifndef AST_BYPASS_CLK + .clk_i ( clk_ext ), +`else // of AST_BYPASS_CLK + .clk_i ( clk_ext_io_i ), +`endif // of AST_BYPASS_CLK + .en_i ( clk_ext_io_en ), + .test_en_i ( scan_mode_i ), + .clk_o ( clk_ext_io ) +); + +// USB External Clock Enable +//////////////////////////////////////// +logic clk_ext_usb, clk_ext_usb_en, clk_ext_usb_val; +logic clk_src_usb_en; +logic clk_src_ext_usb_n; + +assign clk_src_ext_usb_n = ~clk_src_ext_usb; + +prim_flop_2sync #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_no_scan_clk_src_usb_en_sync ( + .clk_i ( clk_src_ext_usb_n ), + .rst_ni ( rst_aon_exda_n ), + .d_i ( clk_src_usb_en_i ), + .q_o ( clk_src_usb_en ) +); + +assign clk_ext_usb_en = deep_sleep_n && clk_src_usb_en; +assign clk_ext_usb_val = clk_ext_usb_en; + +prim_clock_gating #( + .NoFpgaGate ( 1'b1) +) u_clk_ext_usb_ckgt ( + .clk_i ( clk_src_ext_usb ), + .en_i ( clk_ext_usb_en ), + .test_en_i ( scan_mode_i ), + .clk_o ( clk_ext_usb ) +); + + +//////////////////////////////////////// +// SW Bypass select logic +//////////////////////////////////////// +// Sync to local AON clock +prim_mubi_pkg::mubi4_t ot_io_clk_byp_req, ot_all_clk_byp_req, ot_ext_freq_is_96m; + +prim_mubi4_sync #( + .StabilityCheck ( 1 ), + .ResetValue ( prim_mubi_pkg::MuBi4False ) +) u_io_clk_byp_req ( + .clk_i ( clk_aon ), + .rst_ni ( rst_aon_n ), + .mubi_i ( io_clk_byp_req_i ), + .mubi_o ( {ot_io_clk_byp_req} ) +); + +prim_mubi4_sync #( + .StabilityCheck ( 1 ), + .ResetValue ( prim_mubi_pkg::MuBi4False ) +) u_all_clk_byp_req ( + .clk_i ( clk_aon ), + .rst_ni ( rst_aon_n ), + .mubi_i ( all_clk_byp_req_i ), + .mubi_o ( {ot_all_clk_byp_req} ) +); + +prim_mubi4_sync #( + .StabilityCheck ( 1 ), + .ResetValue ( prim_mubi_pkg::MuBi4False ) +) u_ext_freq_is_96m ( + .clk_i ( clk_aon ), + .rst_ni ( rst_aon_n ), + .mubi_i ( ext_freq_is_96m_i ), + .mubi_o ( {ot_ext_freq_is_96m} ) +); + +// Decode logic +logic ot_all_clk_byp, ot_sys_clk_byp, ot_io_clk_byp, ot_usb_clk_byp, ot_aon_clk_byp; + +prim_mubi4_dec u_all_byp_sel ( .mubi_i ( ot_all_clk_byp_req ), .mubi_dec_o ( ot_all_clk_byp ) ); +prim_mubi4_dec u_sys_byp_sel ( .mubi_i ( ot_all_clk_byp_req ), .mubi_dec_o ( ot_sys_clk_byp ) ); +prim_mubi4_dec u_io_byp_sel ( .mubi_i ( ot_io_clk_byp_req ), .mubi_dec_o ( ot_io_clk_byp ) ); +prim_mubi4_dec u_usb_byp_sel ( .mubi_i ( ot_all_clk_byp_req ), .mubi_dec_o ( ot_usb_clk_byp ) ); +prim_mubi4_dec u_aon_byp_sel ( .mubi_i ( ot_all_clk_byp_req ), .mubi_dec_o ( ot_aon_clk_byp ) ); + +// De-Glitch selects (decode "noise") +logic sw_sys_clk_byp, sw_usb_clk_byp, sw_aon_clk_byp, sw_exfr_is_96m; + +prim_flop #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_sw_all_clk_byp_dgl ( + .clk_i ( clk_aon ), + .rst_ni ( rst_aon_n ), + .d_i ( ot_all_clk_byp ), + .q_o ( sw_all_clk_byp ) +); + +prim_flop #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_sw_sys_clk_byp_dgl ( + .clk_i ( clk_aon ), + .rst_ni ( rst_aon_n ), + .d_i ( ot_sys_clk_byp ), + .q_o ( sw_sys_clk_byp ) +); + +prim_flop #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_sw_io_clk_byp_dgl ( + .clk_i ( clk_aon ), + .rst_ni ( rst_aon_n ), + .d_i ( ot_io_clk_byp ), + .q_o ( sw_io_clk_byp ) +); + +prim_flop #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_sw_usb_clk_byp_dgl ( + .clk_i ( clk_aon ), + .rst_ni ( rst_aon_n ), + .d_i ( ot_usb_clk_byp ), + .q_o ( sw_usb_clk_byp ) +); + +prim_flop #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_sw_aon_clk_byp_dgl ( + .clk_i ( clk_aon ), + .rst_ni ( rst_aon_n ), + .d_i ( ot_aon_clk_byp ), + .q_o ( sw_aon_clk_byp ) +); + +prim_flop #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_sw_exfr_is_96m_dgl ( + .clk_i ( clk_aon ), + .rst_ni ( rst_aon_n ), + .d_i ( prim_mubi_pkg::mubi4_test_true_strict(ot_ext_freq_is_96m) ), + .q_o ( sw_exfr_is_96m ) +); + +logic sys_clk_byp; + +assign sys_clk_byp = sw_sys_clk_byp; + +logic sel_io_clk_byp, io_clk_byp; + +assign sel_io_clk_byp = sw_io_clk_byp || sw_all_clk_byp; + +// De-Glitch IO Clock Bypass Select +//////////////////////////////////////// +prim_flop #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_io_clk_byp_dgl ( + .clk_i ( clk_aon ), + .rst_ni ( rst_aon_n ), + .d_i ( sel_io_clk_byp ), + .q_o ( io_clk_byp ) +); + +logic usb_clk_byp; + +assign usb_clk_byp = sw_usb_clk_byp; + +logic aon_clk_byp; + +assign aon_clk_byp = sw_aon_clk_byp; + +logic extfreq_is_96m; + +assign extfreq_is_96m = sw_exfr_is_96m; + +// Block changes during scan mode +//////////////////////////////////////// +logic sys_clk_byp_sel, io_clk_byp_sel, usb_clk_byp_sel, aon_clk_byp_sel; + +`ifndef AST_BYPASS_CLK +always_latch begin + if ( !scan_mode_i ) begin + sys_clk_byp_sel = sys_clk_byp; + io_clk_byp_sel = io_clk_byp; + usb_clk_byp_sel = usb_clk_byp; + aon_clk_byp_sel = aon_clk_byp; + ext_freq_is_96m = extfreq_is_96m; + end +end +`else // of AST_BYPASS_CLK +assign sys_clk_byp_sel = sys_clk_byp; +assign io_clk_byp_sel = io_clk_byp; +assign usb_clk_byp_sel = usb_clk_byp; +assign aon_clk_byp_sel = aon_clk_byp; +assign ext_freq_is_96m = extfreq_is_96m; +`endif // of AST_BYPASS_CLK + + +//////////////////////////////////////// +// Clocks Bypass Muxes +//////////////////////////////////////// +logic sys_clk_osc_en, io_clk_osc_en, usb_clk_osc_en, aon_clk_osc_en; +logic sys_clk_byp_en, io_clk_byp_en, usb_clk_byp_en, aon_clk_byp_en; +logic rst_clk_osc_n, rst_clk_ext_n, aon_rst_clk_ext_n; + +assign rst_clk_osc_n = vcaon_pok; +assign rst_clk_ext_n = vcaon_pok_por_i; +assign aon_rst_clk_ext_n = vcaon_pok; + +// DV Hooks for IO clocks +logic io_clk_byp_select, io_clk_byp_sel_buf, io_clk_osc_en_buf, io_clk_byp_en_buf; + +assign io_clk_byp_select = io_clk_byp_sel; + +prim_buf u_io_clk_byp_sel ( + .in_i ( io_clk_byp_select ), + .out_o ( io_clk_byp_sel_buf ) +); + +prim_buf u_io_clk_osc_en ( + .in_i ( io_clk_osc_en ), + .out_o ( io_clk_osc_en_buf ) +); + +prim_buf u_io_clk_byp_en ( + .in_i ( io_clk_byp_en ), + .out_o ( io_clk_byp_en_buf ) +); + +logic rst_clk_osc_sys_n, rst_clk_ext_sys_n, rst_clk_osc_io_n, rst_clk_ext_io_n; +logic rst_clk_osc_usb_n, rst_clk_ext_usb_n, rst_clk_osc_aon_n, rst_clk_ext_aon_n; + +prim_buf u_rst_clk_osc_sys ( + .in_i ( rst_clk_osc_n ), + .out_o ( rst_clk_osc_sys_n ) +); + +prim_buf u_rst_clk_ext_sys ( + .in_i ( rst_clk_ext_n ), + .out_o ( rst_clk_ext_sys_n ) +); + +prim_buf u_rst_clk_osc_io ( + .in_i ( rst_clk_osc_n ), + .out_o ( rst_clk_osc_io_n ) +); + +prim_buf u_rst_clk_ext_io ( + .in_i ( rst_clk_ext_n ), + .out_o ( rst_clk_ext_io_n ) +); + +prim_buf u_rst_clk_osc_usb ( + .in_i ( rst_clk_osc_n ), + .out_o ( rst_clk_osc_usb_n ) +); + +prim_buf u_rst_clk_ext_usb ( + .in_i ( rst_clk_ext_n ), + .out_o ( rst_clk_ext_usb_n ) +); + +prim_buf u_rst_clk_osc_aon ( + .in_i ( rst_clk_osc_n ), + .out_o ( rst_clk_osc_aon_n ) +); + +prim_buf u_rst_clk_ext_aon ( + .in_i ( aon_rst_clk_ext_n ), + .out_o ( rst_clk_ext_aon_n ) +); + +// rst_aon_n deasset to io clock +//////////////////////////////////////// +logic rst_aon_n_ioda, rst_aon_ioda_n; + +prim_flop_2sync #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_rst_aon_n_ioda_sync ( + .clk_i ( clk_src_io_o ), + .rst_ni ( rst_aon_n ), + .d_i ( 1'b1 ), + .q_o ( rst_aon_n_ioda ) +); + +assign rst_aon_ioda_n = scan_mode_i ? scan_reset_ni : rst_aon_n_ioda; + +// SYS Clock Bypass Mux +//////////////////////////////////////// +gfr_clk_mux2 u_clk_src_sys_sel ( + .clk_osc_i ( clk_osc_sys_i ), + .clk_osc_val_i ( clk_osc_sys_val_i ), + .rst_clk_osc_ni ( rst_clk_osc_sys_n ), + .clk_ext_i ( clk_ext_sys ), + .clk_ext_val_i ( clk_ext_sys_val ), + .rst_clk_ext_ni ( rst_clk_ext_sys_n ), + .ext_sel_i ( sys_clk_byp_sel ), + .clk_osc_en_o ( sys_clk_osc_en ), + .clk_ext_en_o ( sys_clk_byp_en ), + .clk_val_o ( clk_src_sys_val_o ), + .clk_o ( clk_src_sys_o ) +); + +// IO Clock Bypass Mux +//////////////////////////////////////// +logic clk_src_io, clk_src_io_val; + +gfr_clk_mux2 u_clk_src_io_sel ( + .clk_osc_i ( clk_osc_io_i ), + .clk_osc_val_i ( clk_osc_io_val_i ), + .rst_clk_osc_ni ( rst_clk_osc_io_n ), + .clk_ext_i ( clk_ext_io ), + .clk_ext_val_i ( clk_ext_io_val ), + .rst_clk_ext_ni ( rst_clk_ext_io_n ), + .ext_sel_i ( io_clk_byp_sel ), + .clk_osc_en_o ( io_clk_osc_en ), + .clk_ext_en_o ( io_clk_byp_en ), + .clk_val_o ( clk_src_io_val ), + .clk_o ( clk_src_io ) +); + +`ifndef AST_BYPASS_CLK +assign clk_src_io_val_o = clk_src_io_val; +assign clk_src_io_o = clk_src_io; +`else // of AST_BYPASS_CLK +// For FPGA, clk_ext is always the one frequency, so divide by 2 if downstream +// thinks it should be "48 MHz" instead of "96 MHz". +logic ext_freq_is_96m_io_sync; +logic rst_src_io_n; + +prim_flop_2sync #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_no_scan_rst_src_io_n_sync ( + .clk_i ( clk_src_io ), + .rst_ni ( rst_aon_n ), + .d_i ( 1'b1 ), + .q_o ( rst_src_io_n ) +); + +prim_flop_2sync #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_no_scan_ext_freq_is_96m_io_sync ( + .clk_i ( clk_src_io ), + .rst_ni ( rst_src_io_n ), + .d_i ( ext_freq_is_96m ), + .q_o ( ext_freq_is_96m_io_sync ) +); + +logic clk_src_io_div2_sel; +assign clk_src_io_div2_sel = !ext_freq_is_96m_io_sync & io_clk_byp_sel; + +prim_clock_div #( + .Divisor( 2 ) +) u_no_scan_clk_src_io_d1ord2 ( + .clk_i ( clk_src_io ), + .rst_ni ( rst_src_io_n ), + .step_down_req_i( !clk_src_io_div2_sel ), + .step_down_ack_o ( ), + .test_en_i ( scan_mode_i ), + .clk_o ( clk_src_io_o ) +); + +prim_flop_2sync #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_no_scan_clk_src_io_val_sync ( + .clk_i ( clk_src_io_o ), + .rst_ni ( rst_aon_ioda_n ), + .d_i ( clk_src_io_val ), + .q_o ( clk_src_io_val_o ) +); +`endif // of AST_BYPASS_CLK + +// USB Clock Bypass Mux +//////////////////////////////////////// +gfr_clk_mux2 u_clk_src_usb_sel ( + .clk_osc_i ( clk_osc_usb_i ), + .clk_osc_val_i ( clk_osc_usb_val_i ), + .rst_clk_osc_ni ( rst_clk_osc_usb_n ), + .clk_ext_i ( clk_ext_usb ), + .clk_ext_val_i ( clk_ext_usb_val ), + .rst_clk_ext_ni ( rst_clk_ext_usb_n ), + .ext_sel_i ( usb_clk_byp_sel ), + .clk_osc_en_o ( usb_clk_osc_en ), + .clk_ext_en_o ( usb_clk_byp_en ), + .clk_val_o ( clk_src_usb_val_o ), + .clk_o ( clk_src_usb_o ) +); + +// AON Clock Bypass Mux +//////////////////////////////////////// +gfr_clk_mux2 u_clk_src_aon_sel ( + .clk_osc_i ( clk_osc_aon_i ), + .clk_osc_val_i ( clk_osc_aon_val_i ), + .rst_clk_osc_ni ( rst_clk_osc_aon_n ), + .clk_ext_i ( clk_ext_aon ), + .clk_ext_val_i ( clk_ext_aon_val ), + .rst_clk_ext_ni ( rst_clk_ext_aon_n ), + .ext_sel_i ( aon_clk_byp_sel ), + .clk_osc_en_o ( aon_clk_osc_en ), + .clk_ext_en_o ( aon_clk_byp_en ), + .clk_val_o ( clk_src_aon_val_o ), + .clk_o ( clk_src_aon_o ) +); + +// All Clocks Bypass Acknowledge +//////////////////////////////////////// +logic all_clks_byp_en_src, all_clks_byp_en; + +always_ff @( posedge clk_aon, negedge rst_aon_n ) begin + if ( !rst_aon_n ) begin + all_clks_byp_en_src <= 1'b0; + end else begin + all_clks_byp_en_src <= sw_all_clk_byp && sys_clk_byp_en && io_clk_byp_en && + usb_clk_byp_en && aon_clk_byp_en; + end +end + +prim_flop_2sync #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_all_clks_byp_en_sync ( + .clk_i ( clk_src_io_o ), + .rst_ni ( rst_aon_ioda_n ), + .d_i ( all_clks_byp_en_src ), + .q_o ( all_clks_byp_en ) +); + +prim_mubi4_sender #( + .ResetValue ( prim_mubi_pkg::MuBi4False ) +) u_all_clk_byp_ack ( + .clk_i ( clk_src_io_o ), + .rst_ni ( rst_aon_ioda_n ), + .mubi_i ( prim_mubi_pkg::mubi4_bool_to_mubi(all_clks_byp_en) ), + .mubi_o ( {all_clk_byp_ack_o} ) +); + +// IO Clock Bypass Acknowledge +//////////////////////////////////////// +logic only_io_clk_byp_en_src, only_io_clk_byp_en; + +always_ff @( posedge clk_aon, negedge rst_aon_n ) begin + if ( !rst_aon_n ) begin + only_io_clk_byp_en_src <= 1'b0; + end else begin + only_io_clk_byp_en_src <= sw_io_clk_byp && io_clk_byp_en; + end +end + +prim_flop_2sync #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_only_io_clk_byp_en_sync ( + .clk_i ( clk_src_io_o ), + .rst_ni ( rst_aon_ioda_n ), + .d_i ( only_io_clk_byp_en_src ), + .q_o ( only_io_clk_byp_en ) +); + +prim_mubi4_sender #( + .ResetValue ( prim_mubi_pkg::MuBi4False ) +) u_io_clk_byp_ack ( + .clk_i ( clk_src_io_o ), + .rst_ni ( rst_aon_ioda_n ), + .mubi_i ( prim_mubi_pkg::mubi4_bool_to_mubi(only_io_clk_byp_en) ), + .mubi_o ( {io_clk_byp_ack_o} ) +); + +// IO Clock Source is 48MHz +//////////////////////////////////////// +logic io_clk_byp_is_48m_src, io_clk_byp_is_48m; + +// Oscillator source is always 96MHz. +// External Bypass source is assume to be 96MHz until it is ebabled as 48MHz +always_ff @( posedge clk_aon, negedge rst_aon_n ) begin + if ( !rst_aon_n ) begin + io_clk_byp_is_48m_src <= 1'b0; + end else begin + io_clk_byp_is_48m_src <= io_clk_byp_en && !ext_freq_is_96m; + end +end + +prim_flop_2sync #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_io_clk_byp_is_48m_sync ( + .clk_i ( clk_src_io_o ), + .rst_ni ( rst_aon_ioda_n ), + .d_i ( io_clk_byp_is_48m_src ), + .q_o ( io_clk_byp_is_48m ) +); + +prim_mubi4_sender #( + .ResetValue ( prim_mubi_pkg::MuBi4False ) +) u_clk_src_io_48m_sync ( + .clk_i ( clk_src_io_o ), + .rst_ni ( rst_aon_ioda_n ), + .mubi_i ( prim_mubi_pkg::mubi4_bool_to_mubi(io_clk_byp_is_48m) ), + .mubi_o ( {clk_src_io_48m_o} ) +); + + +///////////////////// +// Unused Signals // +///////////////////// +logic unused_sigs; + +assign unused_sigs = ^{ io_clk_byp_sel_buf, + io_clk_byp_en_buf, + io_clk_osc_en_buf, + sys_clk_osc_en, + io_clk_osc_en, + usb_clk_osc_en, + aon_clk_osc_en + }; + +endmodule : ast_clks_byp diff --git a/src/ast/rtl/ast_dft.sv b/src/ast/rtl/ast_dft.sv new file mode 100644 index 0000000..7d27c38 --- /dev/null +++ b/src/ast/rtl/ast_dft.sv @@ -0,0 +1,45 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// -------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------- // +// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED. +// +//############################################################################ +// *Name: ast_dft +// *Module Description: AST DFT +//############################################################################ + +`include "prim_assert.sv" + +module ast_dft ( + output ast_pkg::ast_obs_ctrl_t obs_ctrl_o, // Observe Control + output logic [ast_pkg::Ast2PadOutWidth-1:0] ast2padmux_o, // DFT observed outputs + // memories read-write margins + output ast_pkg::dpm_rm_t dpram_rmf_o, // Dual Port RAM Read-write Margin Fast + output ast_pkg::dpm_rm_t dpram_rml_o, // Dual Port RAM Read-write Margin sLow + output ast_pkg::spm_rm_t spram_rm_o, // Single Port RAM Read-write Margin + output ast_pkg::spm_rm_t sprgf_rm_o, // Single Port Reg-File Read-write Margin + output ast_pkg::spm_rm_t sprom_rm_o // Single Port ROM Read-write Margin +); + +// DFT to AST Digital PADs +assign ast2padmux_o = {ast_pkg::Ast2PadOutWidth{1'b0}}; + +assign obs_ctrl_o = '{ + obgsl: 4'h0, + obmsl: ast_pkg::ObsNon, + obmen: prim_mubi_pkg::MuBi4False + }; + + +//////////////////////////////////////// +// Memories Read-write Margins +//////////////////////////////////////// +assign dpram_rmf_o = 10'h000; +assign dpram_rml_o = 10'h000; +assign spram_rm_o = 5'h00; +assign sprgf_rm_o = 5'h00; +assign sprom_rm_o = 5'h00; + +endmodule : ast_dft diff --git a/src/ast/rtl/ast_entropy.sv b/src/ast/rtl/ast_entropy.sv new file mode 100644 index 0000000..0efb828 --- /dev/null +++ b/src/ast/rtl/ast_entropy.sv @@ -0,0 +1,125 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// -------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------- // +// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED. +// +//############################################################################ +// *Name: ast_entropy +// *Module Description: AST Entropy +//############################################################################ + +module ast_entropy #( + parameter int EntropyRateWidth = 4 +) ( + input edn_pkg::edn_rsp_t entropy_rsp_i, // Entropy Response + input [EntropyRateWidth-1:0] entropy_rate_i, // Entropy Rate + input clk_ast_es_i, // Entropy Clock + input rst_ast_es_ni, // Entropy Reset + input clk_src_sys_i, // System Source Clock + input rst_src_sys_ni, // System Source Reset + input clk_src_sys_val_i, // System Source Clock Valid + input clk_src_sys_jen_i, // System Source Clock Jitter Enable + output edn_pkg::edn_req_t entropy_req_o // Entropy Request +); + +//////////////////////////////////////// +// Entropy Request FSM +//////////////////////////////////////// +typedef enum logic [2-1:0] { + ERQ_REQ0 = 2'd1, // Device-0 Request (source) + ERQ_ACK0 = 2'd3, // Device-0 Acknowledge + ERQ_IDLE = 2'd0 // IDLE/RESET +} erq_sm_e; + +erq_sm_e erq_sm; +logic dev0_wready, dev0_ack; +logic edn_ack, edn_req; +logic [32-1:0] edn_bus; + +// Pack/Un-pack +assign entropy_req_o.edn_req = edn_req; +assign edn_ack = entropy_rsp_i.edn_ack; +assign edn_bus = entropy_rsp_i.edn_bus; + +always_ff @( posedge clk_ast_es_i, negedge rst_ast_es_ni ) begin + if ( !rst_ast_es_ni ) begin + edn_req <= 1'b0; + erq_sm <= ERQ_IDLE; + end else begin + unique case ( erq_sm ) + ERQ_IDLE: begin + if ( dev0_wready ) begin + edn_req <= 1'b1; + erq_sm <= ERQ_REQ0; + end else begin + edn_req <= 1'b0; + erq_sm <= ERQ_IDLE; + end + end + + ERQ_REQ0: begin + if ( edn_ack ) begin + edn_req <= 1'b0; + erq_sm <= ERQ_ACK0; + end else begin + edn_req <= 1'b1; + erq_sm <= ERQ_REQ0; + end + end + + ERQ_ACK0: begin + if ( dev0_wready ) begin + edn_req <= 1'b1; + erq_sm <= ERQ_REQ0; + end else begin + edn_req <= 1'b0; + erq_sm <= ERQ_ACK0; + end + end + + default: begin + edn_req <= 1'b0; + erq_sm <= ERQ_IDLE; + end + endcase + end +end + +assign dev0_ack = edn_ack && ((erq_sm == ERQ_REQ0) || (erq_sm == ERQ_ACK0)); + + +//////////////////////////////////////// +// Device 0 +//////////////////////////////////////// +logic dev0_en, dev0_entropy; + +assign dev0_en = clk_src_sys_val_i && clk_src_sys_jen_i; + +dev_entropy #( + .EntropyRateWidth ( EntropyRateWidth ) +) u_dev0_entropy ( + .clk_i ( clk_ast_es_i ), + .rst_ni ( rst_ast_es_ni ), + .clk_dev_i ( clk_src_sys_i ), + .rst_dev_ni ( rst_src_sys_ni ), + .dev_en_i ( dev0_en ), + .dev_rate_i ( entropy_rate_i[EntropyRateWidth-1:0] ), + .dev_ack_i ( dev0_ack ), + .dev_data_i ( edn_bus[32-1:0] ), + .dev_wready_o ( dev0_wready ), + .dev_data_o ( dev0_entropy ) +); + + + +///////////////////// +// Unused Signals +///////////////////// +logic unused_sigs; +assign unused_sigs = ^{ entropy_rsp_i.edn_fips, + dev0_entropy // Used in ASIC implementation + }; + +endmodule : ast_entropy diff --git a/src/ast/rtl/ast_pkg.sv b/src/ast/rtl/ast_pkg.sv new file mode 100644 index 0000000..178172d --- /dev/null +++ b/src/ast/rtl/ast_pkg.sv @@ -0,0 +1,169 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +//############################################################################ +// *Name: ast_pkg +// *Module Description: AST Package +//############################################################################ +`ifdef __AST_PKG_SV +`else +`define __AST_PKG_SV + +`define PAD2AST_WIRES \ +{ manual_in_ast_misc, \ + mio_in_raw[MioPadIoc3], \ + mio_in_raw[MioPadIoc2], \ + mio_in_raw[MioPadIoc1], \ + mio_in_raw[MioPadIob2], \ + mio_in_raw[MioPadIob1], \ + mio_in_raw[MioPadIob0], \ + mio_in_raw[MioPadIoa5], \ + mio_in_raw[MioPadIoa4] } + +package ast_pkg; + +parameter int unsigned NumIoRails = 2; +// Alerts +parameter int unsigned NumAlerts = 11; +parameter int unsigned AsSel = 0; +parameter int unsigned CgSel = 1; +parameter int unsigned GdSel = 2; +parameter int unsigned TsHiSel = 3; +parameter int unsigned TsLoSel = 4; +parameter int unsigned Ot0Sel = 5; +parameter int unsigned Ot1Sel = 6; +parameter int unsigned Ot2Sel = 7; +parameter int unsigned Ot3Sel = 8; +parameter int unsigned Ot4Sel = 9; +parameter int unsigned Ot5Sel = 10; +// +parameter int unsigned Lc2HcTrCyc = 102; // ((99+1)+(3+1))x5 = 520 us +parameter int unsigned Hc2LcTrCyc = 38; // ((35+1)+(3+1))x5 = 200 us +// +parameter int unsigned EntropyStreams = 4; +parameter int unsigned AdcChannels = 2; +parameter int unsigned AdcDataWidth = 10; +parameter int unsigned UsbCalibWidth = 20; +parameter int unsigned Ast2PadOutWidth = 9; +parameter int unsigned Pad2AstInWidth = 9; +// +// AstRegsNum is the number of AST registers programmed during initialization. It includes +// the register that marks the finalization of init, which asserts the ast_init_done_o. +// The offset of this register is represented with the AstLastRegOffset parameter. +parameter int unsigned AstRegsNum = 39; +parameter int unsigned AstLastRegOffset = (AstRegsNum-1)*4; + +// Memories Read-Write Margin Interface +typedef struct packed { + logic marg_en_a; + logic [4-1:0] marg_a; + logic marg_en_b; + logic [4-1:0] marg_b; +} dpm_rm_t; + +typedef struct packed { + logic marg_en; + logic [4-1:0] marg; +} spm_rm_t; + +// ADC Interface +typedef struct packed { + logic [AdcChannels-1:0] channel_sel; + logic pd; +} adc_ast_req_t; + +typedef struct packed { + logic [AdcDataWidth-1:0] data; + logic data_valid; +} adc_ast_rsp_t; + +// Analog Signal + `ifdef ANALOGSIM +typedef real awire_t; + `else +typedef logic awire_t; + `endif + +// Clock & Resets Interface +typedef struct packed { + logic clk_sys; + logic clk_io; + logic clk_usb; + logic clk_aon; +} ast_clks_t; + +typedef struct packed { + logic aon_pok; +} ast_rst_t; + +parameter ast_rst_t AST_RST_DEFAULT = '{ + aon_pok: 1'b1 +}; + +typedef struct packed { + logic [NumIoRails-1:0] io_pok; +} ast_status_t; + +typedef struct packed { + logic aon_pok; + logic vcc_pok; + logic main_pok; + logic [NumIoRails-1:0] io_pok; +} ast_pwst_t; + +// Alerts Interface +typedef struct packed { + logic p; + logic n; +} ast_dif_t; + +typedef struct packed { + ast_dif_t [NumAlerts-1:0] alerts; +} ast_alert_req_t; + +typedef struct packed { + ast_dif_t [NumAlerts-1:0] alerts_ack; + ast_dif_t [NumAlerts-1:0] alerts_trig; +} ast_alert_rsp_t; + +// Ack mode enumerations +typedef enum logic { + ImmAck = 0, + SwAck = 1 +} ast_ack_mode_e; + +// Clocks Oschillator Bypass +typedef struct packed { + logic usb; + logic sys; + logic io; + logic aon; +} clks_osc_byp_t; + +typedef enum logic [4-1:0] { + ObsNon = 4'h0, // No module observed (disable) + ObsAst = 4'h1, // Observe AST + ObsFla = 4'h2, // Observe FLASH + ObsOtp = 4'h3, // Observe OTP + ObsOt0 = 4'h4, // Observe OT0 + ObsOt1 = 4'h5, // Observe OT1 + ObsOt2 = 4'h6, // Observe OT2 + ObsOt3 = 4'h7, // Observe OT3 + ObsRs0 = 4'h8, // RESERVED + ObsRs1 = 4'h9, // RESERVED + ObsRs2 = 4'hA, // RESERVED + ObsRs3 = 4'hB, // RESERVED + ObsRs4 = 4'hC, // RESERVED + ObsRs5 = 4'hD, // RESERVED + ObsRs6 = 4'hE, // RESERVED + ObsRs7 = 4'hF // RESERVED +} ast_omdl_e; + +typedef struct packed { + logic [4-1:0] obgsl; + ast_omdl_e obmsl; + caliptra_prim_mubi_pkg::mubi4_t obmen; +} ast_obs_ctrl_t; + +endpackage // of ast_pkg +`endif // of __AST_PKG_SV diff --git a/src/ast/rtl/ast_pulse_sync.sv b/src/ast/rtl/ast_pulse_sync.sv new file mode 100644 index 0000000..632e103 --- /dev/null +++ b/src/ast/rtl/ast_pulse_sync.sv @@ -0,0 +1,147 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +//############################################################################ +// *Name: ast_pulse_symc +// *Module Description: AST Pulse Synchronizer +// +// Synchronizes a pulse from source clock domain (clk_src) to destination +// clock domain (clk_dst). The source pulse can have any length of the +// source clock cycle. +// The destination pulse has the length of one destination clock cycle. +// Consecutive pulses need to be spaced appropriately apart from each other +// depending on the clock frequency ratio of the two clock domains. +//############################################################################ + +`include "prim_assert.sv" + +module ast_pulse_sync ( + input scan_mode_i, + // source clock domain + input clk_src_i, + input rst_src_ni, + input src_pulse_i, + output logic src_pulse_en_o, + output logic src_busy_o, + // destination clock domain + input clk_dst_i, + input rst_dst_ni, + output logic dst_pulse_o +); + +// Reset all flops by both resets +//////////////////////////////////////// +logic rst_src_n, rst_dst_da_n; +logic rst_dst_n, rst_src_da_n; + +prim_flop_2sync #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_rst_dst_da ( + .clk_i ( clk_src_i), + .rst_ni ( rst_dst_ni ), + .d_i ( 1'b1 ), + .q_o ( rst_dst_da_n ) +); + +prim_flop_2sync #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_rst_src_da ( + .clk_i ( clk_dst_i), + .rst_ni ( rst_src_ni ), + .d_i ( 1'b1 ), + .q_o ( rst_src_da_n ) +); + +assign rst_src_n = scan_mode_i ? rst_src_ni : rst_src_ni && rst_dst_da_n; +assign rst_dst_n = scan_mode_i ? rst_dst_ni : rst_dst_ni && rst_src_da_n; + + +// Pulse Rising Edge Detect & Block +/////////////////////////////////////// +logic src_pulse_d; + +always_ff @( posedge clk_src_i, negedge rst_src_n ) begin + if ( !rst_src_n ) begin + src_pulse_d <= 1'b0; + end else begin + src_pulse_d <= src_pulse_i; + end +end + +assign src_pulse_en_o = src_pulse_i & !src_pulse_d & !src_busy_o; + + +// Pulse Transformation +/////////////////////////////////////// +logic src_req; + +// Convert src_pulse_en to a level signal +always_ff @( posedge clk_src_i, negedge rst_src_n ) begin + if ( !rst_src_n ) begin + src_req <= 1'b0; + end else begin + src_req <= (src_pulse_en_o ^ src_req); + end +end + + +// SRC_REQ Synchronizer to DST +/////////////////////////////////////// +logic dst_req; + +prim_flop_2sync #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_dst_req ( + .clk_i ( clk_dst_i ), + .rst_ni ( rst_dst_n ), + .d_i ( src_req ), + .q_o ( dst_req ) +); + + +// DST_REQ Synchronizer to SRC for ACK +/////////////////////////////////////// +logic src_ack; + +prim_flop_2sync #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_sync2_ack ( + .clk_i ( clk_src_i ), + .rst_ni ( rst_src_n ), + .d_i ( dst_req ), + .q_o ( src_ack ) +); + +// Source is BUSY when REQ not equel to ACK +assign src_busy_o = (src_req ^ src_ack); + + +// Pulse Reconstruction +/////////////////////////////////////// +logic dst_req_d; + +always_ff @( posedge clk_dst_i, negedge rst_dst_n ) begin + if ( !rst_dst_n ) begin + dst_req_d <= 1'b0; + end else begin + dst_req_d <= dst_req; + end +end + +assign dst_pulse_o = (dst_req ^ dst_req_d); + + +//////////////////// +// Assertions +//////////////////// + +// A new PULSE can only be introduced when source is not BUSY. +`ASSERT(NewPulseWhenSrcBusy, $rose(src_pulse_i) |-> !src_busy_o, clk_src_i, !rst_src_n) + +`ASSERT(DstPulseCheck_A, dst_pulse_o |=> !dst_pulse_o, clk_dst_i, !rst_dst_n) + +endmodule : ast_pulse_sync diff --git a/src/ast/rtl/ast_reg_pkg.sv b/src/ast/rtl/ast_reg_pkg.sv new file mode 100644 index 0000000..e81894e --- /dev/null +++ b/src/ast/rtl/ast_reg_pkg.sv @@ -0,0 +1,380 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Package auto-generated by `reggen` containing data structure + +package ast_reg_pkg; + + // Param list + parameter int NumRegsB = 5; + parameter int NumUsbBeaconPulses = 8; + + // Address widths within the block + parameter int BlockAw = 10; + + //////////////////////////// + // Typedefs for registers // + //////////////////////////// + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega0_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega1_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega2_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega3_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega4_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega5_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega6_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega7_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega8_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega9_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega10_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega11_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega12_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega13_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega14_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega15_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega16_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega17_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega18_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega19_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega20_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega21_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega22_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega23_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega24_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega25_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega26_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega27_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega28_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega29_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega30_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega31_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega32_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega33_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega34_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega35_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega36_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega37_reg_t; + + typedef struct packed { + logic [31:0] q; + logic qe; + } ast_reg2hw_regal_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_regb_mreg_t; + + typedef struct packed { + logic [31:0] d; + } ast_hw2reg_regal_reg_t; + + // Register -> HW type + typedef struct packed { + ast_reg2hw_rega0_reg_t rega0; // [1408:1377] + ast_reg2hw_rega1_reg_t rega1; // [1376:1345] + ast_reg2hw_rega2_reg_t rega2; // [1344:1313] + ast_reg2hw_rega3_reg_t rega3; // [1312:1281] + ast_reg2hw_rega4_reg_t rega4; // [1280:1249] + ast_reg2hw_rega5_reg_t rega5; // [1248:1217] + ast_reg2hw_rega6_reg_t rega6; // [1216:1185] + ast_reg2hw_rega7_reg_t rega7; // [1184:1153] + ast_reg2hw_rega8_reg_t rega8; // [1152:1121] + ast_reg2hw_rega9_reg_t rega9; // [1120:1089] + ast_reg2hw_rega10_reg_t rega10; // [1088:1057] + ast_reg2hw_rega11_reg_t rega11; // [1056:1025] + ast_reg2hw_rega12_reg_t rega12; // [1024:993] + ast_reg2hw_rega13_reg_t rega13; // [992:961] + ast_reg2hw_rega14_reg_t rega14; // [960:929] + ast_reg2hw_rega15_reg_t rega15; // [928:897] + ast_reg2hw_rega16_reg_t rega16; // [896:865] + ast_reg2hw_rega17_reg_t rega17; // [864:833] + ast_reg2hw_rega18_reg_t rega18; // [832:801] + ast_reg2hw_rega19_reg_t rega19; // [800:769] + ast_reg2hw_rega20_reg_t rega20; // [768:737] + ast_reg2hw_rega21_reg_t rega21; // [736:705] + ast_reg2hw_rega22_reg_t rega22; // [704:673] + ast_reg2hw_rega23_reg_t rega23; // [672:641] + ast_reg2hw_rega24_reg_t rega24; // [640:609] + ast_reg2hw_rega25_reg_t rega25; // [608:577] + ast_reg2hw_rega26_reg_t rega26; // [576:545] + ast_reg2hw_rega27_reg_t rega27; // [544:513] + ast_reg2hw_rega28_reg_t rega28; // [512:481] + ast_reg2hw_rega29_reg_t rega29; // [480:449] + ast_reg2hw_rega30_reg_t rega30; // [448:417] + ast_reg2hw_rega31_reg_t rega31; // [416:385] + ast_reg2hw_rega32_reg_t rega32; // [384:353] + ast_reg2hw_rega33_reg_t rega33; // [352:321] + ast_reg2hw_rega34_reg_t rega34; // [320:289] + ast_reg2hw_rega35_reg_t rega35; // [288:257] + ast_reg2hw_rega36_reg_t rega36; // [256:225] + ast_reg2hw_rega37_reg_t rega37; // [224:193] + ast_reg2hw_regal_reg_t regal; // [192:160] + ast_reg2hw_regb_mreg_t [4:0] regb; // [159:0] + } ast_reg2hw_t; + + // HW -> register type + typedef struct packed { + ast_hw2reg_regal_reg_t regal; // [31:0] + } ast_hw2reg_t; + + // Register offsets + parameter logic [BlockAw-1:0] AST_REGA0_OFFSET = 10'h 0; + parameter logic [BlockAw-1:0] AST_REGA1_OFFSET = 10'h 4; + parameter logic [BlockAw-1:0] AST_REGA2_OFFSET = 10'h 8; + parameter logic [BlockAw-1:0] AST_REGA3_OFFSET = 10'h c; + parameter logic [BlockAw-1:0] AST_REGA4_OFFSET = 10'h 10; + parameter logic [BlockAw-1:0] AST_REGA5_OFFSET = 10'h 14; + parameter logic [BlockAw-1:0] AST_REGA6_OFFSET = 10'h 18; + parameter logic [BlockAw-1:0] AST_REGA7_OFFSET = 10'h 1c; + parameter logic [BlockAw-1:0] AST_REGA8_OFFSET = 10'h 20; + parameter logic [BlockAw-1:0] AST_REGA9_OFFSET = 10'h 24; + parameter logic [BlockAw-1:0] AST_REGA10_OFFSET = 10'h 28; + parameter logic [BlockAw-1:0] AST_REGA11_OFFSET = 10'h 2c; + parameter logic [BlockAw-1:0] AST_REGA12_OFFSET = 10'h 30; + parameter logic [BlockAw-1:0] AST_REGA13_OFFSET = 10'h 34; + parameter logic [BlockAw-1:0] AST_REGA14_OFFSET = 10'h 38; + parameter logic [BlockAw-1:0] AST_REGA15_OFFSET = 10'h 3c; + parameter logic [BlockAw-1:0] AST_REGA16_OFFSET = 10'h 40; + parameter logic [BlockAw-1:0] AST_REGA17_OFFSET = 10'h 44; + parameter logic [BlockAw-1:0] AST_REGA18_OFFSET = 10'h 48; + parameter logic [BlockAw-1:0] AST_REGA19_OFFSET = 10'h 4c; + parameter logic [BlockAw-1:0] AST_REGA20_OFFSET = 10'h 50; + parameter logic [BlockAw-1:0] AST_REGA21_OFFSET = 10'h 54; + parameter logic [BlockAw-1:0] AST_REGA22_OFFSET = 10'h 58; + parameter logic [BlockAw-1:0] AST_REGA23_OFFSET = 10'h 5c; + parameter logic [BlockAw-1:0] AST_REGA24_OFFSET = 10'h 60; + parameter logic [BlockAw-1:0] AST_REGA25_OFFSET = 10'h 64; + parameter logic [BlockAw-1:0] AST_REGA26_OFFSET = 10'h 68; + parameter logic [BlockAw-1:0] AST_REGA27_OFFSET = 10'h 6c; + parameter logic [BlockAw-1:0] AST_REGA28_OFFSET = 10'h 70; + parameter logic [BlockAw-1:0] AST_REGA29_OFFSET = 10'h 74; + parameter logic [BlockAw-1:0] AST_REGA30_OFFSET = 10'h 78; + parameter logic [BlockAw-1:0] AST_REGA31_OFFSET = 10'h 7c; + parameter logic [BlockAw-1:0] AST_REGA32_OFFSET = 10'h 80; + parameter logic [BlockAw-1:0] AST_REGA33_OFFSET = 10'h 84; + parameter logic [BlockAw-1:0] AST_REGA34_OFFSET = 10'h 88; + parameter logic [BlockAw-1:0] AST_REGA35_OFFSET = 10'h 8c; + parameter logic [BlockAw-1:0] AST_REGA36_OFFSET = 10'h 90; + parameter logic [BlockAw-1:0] AST_REGA37_OFFSET = 10'h 94; + parameter logic [BlockAw-1:0] AST_REGAL_OFFSET = 10'h 98; + parameter logic [BlockAw-1:0] AST_REGB_0_OFFSET = 10'h 200; + parameter logic [BlockAw-1:0] AST_REGB_1_OFFSET = 10'h 204; + parameter logic [BlockAw-1:0] AST_REGB_2_OFFSET = 10'h 208; + parameter logic [BlockAw-1:0] AST_REGB_3_OFFSET = 10'h 20c; + parameter logic [BlockAw-1:0] AST_REGB_4_OFFSET = 10'h 210; + + // Reset values for hwext registers and their fields + parameter logic [31:0] AST_REGAL_RESVAL = 32'h 26; + parameter logic [31:0] AST_REGAL_REG32_RESVAL = 32'h 26; + + // Register index + typedef enum int { + AST_REGA0, + AST_REGA1, + AST_REGA2, + AST_REGA3, + AST_REGA4, + AST_REGA5, + AST_REGA6, + AST_REGA7, + AST_REGA8, + AST_REGA9, + AST_REGA10, + AST_REGA11, + AST_REGA12, + AST_REGA13, + AST_REGA14, + AST_REGA15, + AST_REGA16, + AST_REGA17, + AST_REGA18, + AST_REGA19, + AST_REGA20, + AST_REGA21, + AST_REGA22, + AST_REGA23, + AST_REGA24, + AST_REGA25, + AST_REGA26, + AST_REGA27, + AST_REGA28, + AST_REGA29, + AST_REGA30, + AST_REGA31, + AST_REGA32, + AST_REGA33, + AST_REGA34, + AST_REGA35, + AST_REGA36, + AST_REGA37, + AST_REGAL, + AST_REGB_0, + AST_REGB_1, + AST_REGB_2, + AST_REGB_3, + AST_REGB_4 + } ast_id_e; + + // Register width information to check illegal writes + parameter logic [3:0] AST_PERMIT [44] = '{ + 4'b 1111, // index[ 0] AST_REGA0 + 4'b 1111, // index[ 1] AST_REGA1 + 4'b 1111, // index[ 2] AST_REGA2 + 4'b 1111, // index[ 3] AST_REGA3 + 4'b 1111, // index[ 4] AST_REGA4 + 4'b 1111, // index[ 5] AST_REGA5 + 4'b 1111, // index[ 6] AST_REGA6 + 4'b 1111, // index[ 7] AST_REGA7 + 4'b 1111, // index[ 8] AST_REGA8 + 4'b 1111, // index[ 9] AST_REGA9 + 4'b 1111, // index[10] AST_REGA10 + 4'b 1111, // index[11] AST_REGA11 + 4'b 1111, // index[12] AST_REGA12 + 4'b 1111, // index[13] AST_REGA13 + 4'b 1111, // index[14] AST_REGA14 + 4'b 1111, // index[15] AST_REGA15 + 4'b 1111, // index[16] AST_REGA16 + 4'b 1111, // index[17] AST_REGA17 + 4'b 1111, // index[18] AST_REGA18 + 4'b 1111, // index[19] AST_REGA19 + 4'b 1111, // index[20] AST_REGA20 + 4'b 1111, // index[21] AST_REGA21 + 4'b 1111, // index[22] AST_REGA22 + 4'b 1111, // index[23] AST_REGA23 + 4'b 1111, // index[24] AST_REGA24 + 4'b 1111, // index[25] AST_REGA25 + 4'b 1111, // index[26] AST_REGA26 + 4'b 1111, // index[27] AST_REGA27 + 4'b 1111, // index[28] AST_REGA28 + 4'b 1111, // index[29] AST_REGA29 + 4'b 1111, // index[30] AST_REGA30 + 4'b 1111, // index[31] AST_REGA31 + 4'b 1111, // index[32] AST_REGA32 + 4'b 1111, // index[33] AST_REGA33 + 4'b 1111, // index[34] AST_REGA34 + 4'b 1111, // index[35] AST_REGA35 + 4'b 1111, // index[36] AST_REGA36 + 4'b 1111, // index[37] AST_REGA37 + 4'b 1111, // index[38] AST_REGAL + 4'b 1111, // index[39] AST_REGB_0 + 4'b 1111, // index[40] AST_REGB_1 + 4'b 1111, // index[41] AST_REGB_2 + 4'b 1111, // index[42] AST_REGB_3 + 4'b 1111 // index[43] AST_REGB_4 + }; + +endpackage diff --git a/src/ast/rtl/ast_reg_top.sv b/src/ast/rtl/ast_reg_top.sv new file mode 100644 index 0000000..921beb3 --- /dev/null +++ b/src/ast/rtl/ast_reg_top.sv @@ -0,0 +1,1969 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Top module auto-generated by `reggen` + +`include "prim_assert.sv" + +module ast_reg_top ( + input clk_i, + input rst_ni, + input tlul_pkg::tl_h2d_t tl_i, + output tlul_pkg::tl_d2h_t tl_o, + // To HW + output ast_reg_pkg::ast_reg2hw_t reg2hw, // Write + input ast_reg_pkg::ast_hw2reg_t hw2reg, // Read + + // Integrity check errors + output logic intg_err_o +); + + import ast_reg_pkg::* ; + + localparam int AW = 10; + localparam int DW = 32; + localparam int DBW = DW/8; // Byte Width + + // register signals + logic reg_we; + logic reg_re; + logic [AW-1:0] reg_addr; + logic [DW-1:0] reg_wdata; + logic [DBW-1:0] reg_be; + logic [DW-1:0] reg_rdata; + logic reg_error; + + logic addrmiss, wr_err; + + logic [DW-1:0] reg_rdata_next; + logic reg_busy; + + tlul_pkg::tl_h2d_t tl_reg_h2d; + tlul_pkg::tl_d2h_t tl_reg_d2h; + + + // incoming payload check + logic intg_err; + tlul_cmd_intg_chk u_chk ( + .tl_i(tl_i), + .err_o(intg_err) + ); + + // also check for spurious write enables + logic reg_we_err; + logic [43:0] reg_we_check; + prim_reg_we_check #( + .OneHotWidth(44) + ) u_prim_reg_we_check ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .oh_i (reg_we_check), + .en_i (reg_we && !addrmiss), + .err_o (reg_we_err) + ); + + logic err_q; + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + err_q <= '0; + end else if (intg_err || reg_we_err) begin + err_q <= 1'b1; + end + end + + // integrity error output is permanent and should be used for alert generation + // register errors are transactional + assign intg_err_o = err_q | intg_err | reg_we_err; + + // outgoing integrity generation + tlul_pkg::tl_d2h_t tl_o_pre; + tlul_rsp_intg_gen #( + .EnableRspIntgGen(1), + .EnableDataIntgGen(1) + ) u_rsp_intg_gen ( + .tl_i(tl_o_pre), + .tl_o(tl_o) + ); + + assign tl_reg_h2d = tl_i; + assign tl_o_pre = tl_reg_d2h; + + tlul_adapter_reg #( + .RegAw(AW), + .RegDw(DW), + .EnableDataIntgGen(0) + ) u_reg_if ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + .tl_i (tl_reg_h2d), + .tl_o (tl_reg_d2h), + + .en_ifetch_i(prim_mubi_pkg::MuBi4False), + .intg_error_o(), + + .we_o (reg_we), + .re_o (reg_re), + .addr_o (reg_addr), + .wdata_o (reg_wdata), + .be_o (reg_be), + .busy_i (reg_busy), + .rdata_i (reg_rdata), + .error_i (reg_error) + ); + + // cdc oversampling signals + + assign reg_rdata = reg_rdata_next ; + assign reg_error = addrmiss | wr_err | intg_err; + + // Define SW related signals + // Format: __{wd|we|qs} + // or _{wd|we|qs} if field == 1 or 0 + logic [31:0] rega0_qs; + logic [31:0] rega1_qs; + logic rega2_we; + logic [31:0] rega2_qs; + logic [31:0] rega2_wd; + logic rega3_we; + logic [31:0] rega3_qs; + logic [31:0] rega3_wd; + logic rega4_we; + logic [31:0] rega4_qs; + logic [31:0] rega4_wd; + logic rega5_we; + logic [31:0] rega5_qs; + logic [31:0] rega5_wd; + logic rega6_we; + logic [31:0] rega6_qs; + logic [31:0] rega6_wd; + logic rega7_we; + logic [31:0] rega7_qs; + logic [31:0] rega7_wd; + logic rega8_we; + logic [31:0] rega8_qs; + logic [31:0] rega8_wd; + logic rega9_we; + logic [31:0] rega9_qs; + logic [31:0] rega9_wd; + logic rega10_we; + logic [31:0] rega10_qs; + logic [31:0] rega10_wd; + logic rega11_we; + logic [31:0] rega11_qs; + logic [31:0] rega11_wd; + logic rega12_we; + logic [31:0] rega12_qs; + logic [31:0] rega12_wd; + logic rega13_we; + logic [31:0] rega13_qs; + logic [31:0] rega13_wd; + logic rega14_we; + logic [31:0] rega14_qs; + logic [31:0] rega14_wd; + logic rega15_we; + logic [31:0] rega15_qs; + logic [31:0] rega15_wd; + logic rega16_we; + logic [31:0] rega16_qs; + logic [31:0] rega16_wd; + logic rega17_we; + logic [31:0] rega17_qs; + logic [31:0] rega17_wd; + logic rega18_we; + logic [31:0] rega18_qs; + logic [31:0] rega18_wd; + logic rega19_we; + logic [31:0] rega19_qs; + logic [31:0] rega19_wd; + logic rega20_we; + logic [31:0] rega20_qs; + logic [31:0] rega20_wd; + logic rega21_we; + logic [31:0] rega21_qs; + logic [31:0] rega21_wd; + logic rega22_we; + logic [31:0] rega22_qs; + logic [31:0] rega22_wd; + logic rega23_we; + logic [31:0] rega23_qs; + logic [31:0] rega23_wd; + logic rega24_we; + logic [31:0] rega24_qs; + logic [31:0] rega24_wd; + logic rega25_we; + logic [31:0] rega25_qs; + logic [31:0] rega25_wd; + logic rega26_we; + logic [31:0] rega26_qs; + logic [31:0] rega26_wd; + logic rega27_we; + logic [31:0] rega27_qs; + logic [31:0] rega27_wd; + logic [31:0] rega28_qs; + logic rega29_we; + logic [31:0] rega29_qs; + logic [31:0] rega29_wd; + logic rega30_we; + logic [31:0] rega30_qs; + logic [31:0] rega30_wd; + logic rega31_we; + logic [31:0] rega31_qs; + logic [31:0] rega31_wd; + logic rega32_we; + logic [31:0] rega32_qs; + logic [31:0] rega32_wd; + logic rega33_we; + logic [31:0] rega33_qs; + logic [31:0] rega33_wd; + logic rega34_we; + logic [31:0] rega34_qs; + logic [31:0] rega34_wd; + logic rega35_we; + logic [31:0] rega35_qs; + logic [31:0] rega35_wd; + logic rega36_we; + logic [31:0] rega36_qs; + logic [31:0] rega36_wd; + logic rega37_we; + logic [31:0] rega37_qs; + logic [31:0] rega37_wd; + logic regal_we; + logic [31:0] regal_wd; + logic regb_0_we; + logic [31:0] regb_0_qs; + logic [31:0] regb_0_wd; + logic regb_1_we; + logic [31:0] regb_1_qs; + logic [31:0] regb_1_wd; + logic regb_2_we; + logic [31:0] regb_2_qs; + logic [31:0] regb_2_wd; + logic regb_3_we; + logic [31:0] regb_3_qs; + logic [31:0] regb_3_wd; + logic regb_4_we; + logic [31:0] regb_4_qs; + logic [31:0] regb_4_wd; + + // Register instances + // R[rega0]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_rega0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega0.q), + .ds (), + + // to register interface (read) + .qs (rega0_qs) + ); + + + // R[rega1]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (32'h1), + .Mubi (1'b0) + ) u_rega1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega1.q), + .ds (), + + // to register interface (read) + .qs (rega1_qs) + ); + + + // R[rega2]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h2), + .Mubi (1'b0) + ) u_rega2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rega2_we), + .wd (rega2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega2.q), + .ds (), + + // to register interface (read) + .qs (rega2_qs) + ); + + + // R[rega3]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h3), + .Mubi (1'b0) + ) u_rega3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rega3_we), + .wd (rega3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega3.q), + .ds (), + + // to register interface (read) + .qs (rega3_qs) + ); + + + // R[rega4]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h4), + .Mubi (1'b0) + ) u_rega4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rega4_we), + .wd (rega4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega4.q), + .ds (), + + // to register interface (read) + .qs (rega4_qs) + ); + + + // R[rega5]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h5), + .Mubi (1'b0) + ) u_rega5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rega5_we), + .wd (rega5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega5.q), + .ds (), + + // to register interface (read) + .qs (rega5_qs) + ); + + + // R[rega6]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h6), + .Mubi (1'b0) + ) u_rega6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rega6_we), + .wd (rega6_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega6.q), + .ds (), + + // to register interface (read) + .qs (rega6_qs) + ); + + + // R[rega7]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h7), + .Mubi (1'b0) + ) u_rega7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rega7_we), + .wd (rega7_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega7.q), + .ds (), + + // to register interface (read) + .qs (rega7_qs) + ); + + + // R[rega8]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h8), + .Mubi (1'b0) + ) u_rega8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rega8_we), + .wd (rega8_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega8.q), + .ds (), + + // to register interface (read) + .qs (rega8_qs) + ); + + + // R[rega9]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h9), + .Mubi (1'b0) + ) u_rega9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rega9_we), + .wd (rega9_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega9.q), + .ds (), + + // to register interface (read) + .qs (rega9_qs) + ); + + + // R[rega10]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'ha), + .Mubi (1'b0) + ) u_rega10 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rega10_we), + .wd (rega10_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega10.q), + .ds (), + + // to register interface (read) + .qs (rega10_qs) + ); + + + // R[rega11]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'hb), + .Mubi (1'b0) + ) u_rega11 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rega11_we), + .wd (rega11_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega11.q), + .ds (), + + // to register interface (read) + .qs (rega11_qs) + ); + + + // R[rega12]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'hc), + .Mubi (1'b0) + ) u_rega12 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rega12_we), + .wd (rega12_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega12.q), + .ds (), + + // to register interface (read) + .qs (rega12_qs) + ); + + + // R[rega13]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'hd), + .Mubi (1'b0) + ) u_rega13 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rega13_we), + .wd (rega13_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega13.q), + .ds (), + + // to register interface (read) + .qs (rega13_qs) + ); + + + // R[rega14]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'he), + .Mubi (1'b0) + ) u_rega14 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rega14_we), + .wd (rega14_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega14.q), + .ds (), + + // to register interface (read) + .qs (rega14_qs) + ); + + + // R[rega15]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'hf), + .Mubi (1'b0) + ) u_rega15 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rega15_we), + .wd (rega15_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega15.q), + .ds (), + + // to register interface (read) + .qs (rega15_qs) + ); + + + // R[rega16]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h10), + .Mubi (1'b0) + ) u_rega16 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rega16_we), + .wd (rega16_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega16.q), + .ds (), + + // to register interface (read) + .qs (rega16_qs) + ); + + + // R[rega17]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h11), + .Mubi (1'b0) + ) u_rega17 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rega17_we), + .wd (rega17_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega17.q), + .ds (), + + // to register interface (read) + .qs (rega17_qs) + ); + + + // R[rega18]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h12), + .Mubi (1'b0) + ) u_rega18 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rega18_we), + .wd (rega18_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega18.q), + .ds (), + + // to register interface (read) + .qs (rega18_qs) + ); + + + // R[rega19]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h13), + .Mubi (1'b0) + ) u_rega19 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rega19_we), + .wd (rega19_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega19.q), + .ds (), + + // to register interface (read) + .qs (rega19_qs) + ); + + + // R[rega20]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h14), + .Mubi (1'b0) + ) u_rega20 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rega20_we), + .wd (rega20_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega20.q), + .ds (), + + // to register interface (read) + .qs (rega20_qs) + ); + + + // R[rega21]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h15), + .Mubi (1'b0) + ) u_rega21 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rega21_we), + .wd (rega21_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega21.q), + .ds (), + + // to register interface (read) + .qs (rega21_qs) + ); + + + // R[rega22]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h16), + .Mubi (1'b0) + ) u_rega22 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rega22_we), + .wd (rega22_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega22.q), + .ds (), + + // to register interface (read) + .qs (rega22_qs) + ); + + + // R[rega23]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h17), + .Mubi (1'b0) + ) u_rega23 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rega23_we), + .wd (rega23_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega23.q), + .ds (), + + // to register interface (read) + .qs (rega23_qs) + ); + + + // R[rega24]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h18), + .Mubi (1'b0) + ) u_rega24 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rega24_we), + .wd (rega24_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega24.q), + .ds (), + + // to register interface (read) + .qs (rega24_qs) + ); + + + // R[rega25]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h19), + .Mubi (1'b0) + ) u_rega25 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rega25_we), + .wd (rega25_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega25.q), + .ds (), + + // to register interface (read) + .qs (rega25_qs) + ); + + + // R[rega26]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h1a), + .Mubi (1'b0) + ) u_rega26 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rega26_we), + .wd (rega26_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega26.q), + .ds (), + + // to register interface (read) + .qs (rega26_qs) + ); + + + // R[rega27]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h1b), + .Mubi (1'b0) + ) u_rega27 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rega27_we), + .wd (rega27_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega27.q), + .ds (), + + // to register interface (read) + .qs (rega27_qs) + ); + + + // R[rega28]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (32'h1c), + .Mubi (1'b0) + ) u_rega28 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega28.q), + .ds (), + + // to register interface (read) + .qs (rega28_qs) + ); + + + // R[rega29]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h1d), + .Mubi (1'b0) + ) u_rega29 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rega29_we), + .wd (rega29_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega29.q), + .ds (), + + // to register interface (read) + .qs (rega29_qs) + ); + + + // R[rega30]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h1e), + .Mubi (1'b0) + ) u_rega30 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rega30_we), + .wd (rega30_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega30.q), + .ds (), + + // to register interface (read) + .qs (rega30_qs) + ); + + + // R[rega31]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h1f), + .Mubi (1'b0) + ) u_rega31 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rega31_we), + .wd (rega31_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega31.q), + .ds (), + + // to register interface (read) + .qs (rega31_qs) + ); + + + // R[rega32]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h20), + .Mubi (1'b0) + ) u_rega32 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rega32_we), + .wd (rega32_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega32.q), + .ds (), + + // to register interface (read) + .qs (rega32_qs) + ); + + + // R[rega33]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h21), + .Mubi (1'b0) + ) u_rega33 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rega33_we), + .wd (rega33_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega33.q), + .ds (), + + // to register interface (read) + .qs (rega33_qs) + ); + + + // R[rega34]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h22), + .Mubi (1'b0) + ) u_rega34 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rega34_we), + .wd (rega34_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega34.q), + .ds (), + + // to register interface (read) + .qs (rega34_qs) + ); + + + // R[rega35]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h23), + .Mubi (1'b0) + ) u_rega35 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rega35_we), + .wd (rega35_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega35.q), + .ds (), + + // to register interface (read) + .qs (rega35_qs) + ); + + + // R[rega36]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h24), + .Mubi (1'b0) + ) u_rega36 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rega36_we), + .wd (rega36_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega36.q), + .ds (), + + // to register interface (read) + .qs (rega36_qs) + ); + + + // R[rega37]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h25), + .Mubi (1'b0) + ) u_rega37 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rega37_we), + .wd (rega37_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega37.q), + .ds (), + + // to register interface (read) + .qs (rega37_qs) + ); + + + // R[regal]: V(True) + logic regal_qe; + logic [0:0] regal_flds_we; + assign regal_qe = ®al_flds_we; + prim_subreg_ext #( + .DW (32) + ) u_regal ( + .re (1'b0), + .we (regal_we), + .wd (regal_wd), + .d (hw2reg.regal.d), + .qre (), + .qe (regal_flds_we[0]), + .q (reg2hw.regal.q), + .ds (), + .qs () + ); + assign reg2hw.regal.qe = regal_qe; + + + // Subregister 0 of Multireg regb + // R[regb_0]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_regb_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (regb_0_we), + .wd (regb_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.regb[0].q), + .ds (), + + // to register interface (read) + .qs (regb_0_qs) + ); + + + // Subregister 1 of Multireg regb + // R[regb_1]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_regb_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (regb_1_we), + .wd (regb_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.regb[1].q), + .ds (), + + // to register interface (read) + .qs (regb_1_qs) + ); + + + // Subregister 2 of Multireg regb + // R[regb_2]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_regb_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (regb_2_we), + .wd (regb_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.regb[2].q), + .ds (), + + // to register interface (read) + .qs (regb_2_qs) + ); + + + // Subregister 3 of Multireg regb + // R[regb_3]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_regb_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (regb_3_we), + .wd (regb_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.regb[3].q), + .ds (), + + // to register interface (read) + .qs (regb_3_qs) + ); + + + // Subregister 4 of Multireg regb + // R[regb_4]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_regb_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (regb_4_we), + .wd (regb_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.regb[4].q), + .ds (), + + // to register interface (read) + .qs (regb_4_qs) + ); + + + + logic [43:0] addr_hit; + always_comb begin + addr_hit = '0; + addr_hit[ 0] = (reg_addr == AST_REGA0_OFFSET); + addr_hit[ 1] = (reg_addr == AST_REGA1_OFFSET); + addr_hit[ 2] = (reg_addr == AST_REGA2_OFFSET); + addr_hit[ 3] = (reg_addr == AST_REGA3_OFFSET); + addr_hit[ 4] = (reg_addr == AST_REGA4_OFFSET); + addr_hit[ 5] = (reg_addr == AST_REGA5_OFFSET); + addr_hit[ 6] = (reg_addr == AST_REGA6_OFFSET); + addr_hit[ 7] = (reg_addr == AST_REGA7_OFFSET); + addr_hit[ 8] = (reg_addr == AST_REGA8_OFFSET); + addr_hit[ 9] = (reg_addr == AST_REGA9_OFFSET); + addr_hit[10] = (reg_addr == AST_REGA10_OFFSET); + addr_hit[11] = (reg_addr == AST_REGA11_OFFSET); + addr_hit[12] = (reg_addr == AST_REGA12_OFFSET); + addr_hit[13] = (reg_addr == AST_REGA13_OFFSET); + addr_hit[14] = (reg_addr == AST_REGA14_OFFSET); + addr_hit[15] = (reg_addr == AST_REGA15_OFFSET); + addr_hit[16] = (reg_addr == AST_REGA16_OFFSET); + addr_hit[17] = (reg_addr == AST_REGA17_OFFSET); + addr_hit[18] = (reg_addr == AST_REGA18_OFFSET); + addr_hit[19] = (reg_addr == AST_REGA19_OFFSET); + addr_hit[20] = (reg_addr == AST_REGA20_OFFSET); + addr_hit[21] = (reg_addr == AST_REGA21_OFFSET); + addr_hit[22] = (reg_addr == AST_REGA22_OFFSET); + addr_hit[23] = (reg_addr == AST_REGA23_OFFSET); + addr_hit[24] = (reg_addr == AST_REGA24_OFFSET); + addr_hit[25] = (reg_addr == AST_REGA25_OFFSET); + addr_hit[26] = (reg_addr == AST_REGA26_OFFSET); + addr_hit[27] = (reg_addr == AST_REGA27_OFFSET); + addr_hit[28] = (reg_addr == AST_REGA28_OFFSET); + addr_hit[29] = (reg_addr == AST_REGA29_OFFSET); + addr_hit[30] = (reg_addr == AST_REGA30_OFFSET); + addr_hit[31] = (reg_addr == AST_REGA31_OFFSET); + addr_hit[32] = (reg_addr == AST_REGA32_OFFSET); + addr_hit[33] = (reg_addr == AST_REGA33_OFFSET); + addr_hit[34] = (reg_addr == AST_REGA34_OFFSET); + addr_hit[35] = (reg_addr == AST_REGA35_OFFSET); + addr_hit[36] = (reg_addr == AST_REGA36_OFFSET); + addr_hit[37] = (reg_addr == AST_REGA37_OFFSET); + addr_hit[38] = (reg_addr == AST_REGAL_OFFSET); + addr_hit[39] = (reg_addr == AST_REGB_0_OFFSET); + addr_hit[40] = (reg_addr == AST_REGB_1_OFFSET); + addr_hit[41] = (reg_addr == AST_REGB_2_OFFSET); + addr_hit[42] = (reg_addr == AST_REGB_3_OFFSET); + addr_hit[43] = (reg_addr == AST_REGB_4_OFFSET); + end + + assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; + + // Check sub-word write is permitted + always_comb begin + wr_err = (reg_we & + ((addr_hit[ 0] & (|(AST_PERMIT[ 0] & ~reg_be))) | + (addr_hit[ 1] & (|(AST_PERMIT[ 1] & ~reg_be))) | + (addr_hit[ 2] & (|(AST_PERMIT[ 2] & ~reg_be))) | + (addr_hit[ 3] & (|(AST_PERMIT[ 3] & ~reg_be))) | + (addr_hit[ 4] & (|(AST_PERMIT[ 4] & ~reg_be))) | + (addr_hit[ 5] & (|(AST_PERMIT[ 5] & ~reg_be))) | + (addr_hit[ 6] & (|(AST_PERMIT[ 6] & ~reg_be))) | + (addr_hit[ 7] & (|(AST_PERMIT[ 7] & ~reg_be))) | + (addr_hit[ 8] & (|(AST_PERMIT[ 8] & ~reg_be))) | + (addr_hit[ 9] & (|(AST_PERMIT[ 9] & ~reg_be))) | + (addr_hit[10] & (|(AST_PERMIT[10] & ~reg_be))) | + (addr_hit[11] & (|(AST_PERMIT[11] & ~reg_be))) | + (addr_hit[12] & (|(AST_PERMIT[12] & ~reg_be))) | + (addr_hit[13] & (|(AST_PERMIT[13] & ~reg_be))) | + (addr_hit[14] & (|(AST_PERMIT[14] & ~reg_be))) | + (addr_hit[15] & (|(AST_PERMIT[15] & ~reg_be))) | + (addr_hit[16] & (|(AST_PERMIT[16] & ~reg_be))) | + (addr_hit[17] & (|(AST_PERMIT[17] & ~reg_be))) | + (addr_hit[18] & (|(AST_PERMIT[18] & ~reg_be))) | + (addr_hit[19] & (|(AST_PERMIT[19] & ~reg_be))) | + (addr_hit[20] & (|(AST_PERMIT[20] & ~reg_be))) | + (addr_hit[21] & (|(AST_PERMIT[21] & ~reg_be))) | + (addr_hit[22] & (|(AST_PERMIT[22] & ~reg_be))) | + (addr_hit[23] & (|(AST_PERMIT[23] & ~reg_be))) | + (addr_hit[24] & (|(AST_PERMIT[24] & ~reg_be))) | + (addr_hit[25] & (|(AST_PERMIT[25] & ~reg_be))) | + (addr_hit[26] & (|(AST_PERMIT[26] & ~reg_be))) | + (addr_hit[27] & (|(AST_PERMIT[27] & ~reg_be))) | + (addr_hit[28] & (|(AST_PERMIT[28] & ~reg_be))) | + (addr_hit[29] & (|(AST_PERMIT[29] & ~reg_be))) | + (addr_hit[30] & (|(AST_PERMIT[30] & ~reg_be))) | + (addr_hit[31] & (|(AST_PERMIT[31] & ~reg_be))) | + (addr_hit[32] & (|(AST_PERMIT[32] & ~reg_be))) | + (addr_hit[33] & (|(AST_PERMIT[33] & ~reg_be))) | + (addr_hit[34] & (|(AST_PERMIT[34] & ~reg_be))) | + (addr_hit[35] & (|(AST_PERMIT[35] & ~reg_be))) | + (addr_hit[36] & (|(AST_PERMIT[36] & ~reg_be))) | + (addr_hit[37] & (|(AST_PERMIT[37] & ~reg_be))) | + (addr_hit[38] & (|(AST_PERMIT[38] & ~reg_be))) | + (addr_hit[39] & (|(AST_PERMIT[39] & ~reg_be))) | + (addr_hit[40] & (|(AST_PERMIT[40] & ~reg_be))) | + (addr_hit[41] & (|(AST_PERMIT[41] & ~reg_be))) | + (addr_hit[42] & (|(AST_PERMIT[42] & ~reg_be))) | + (addr_hit[43] & (|(AST_PERMIT[43] & ~reg_be))))); + end + + // Generate write-enables + assign rega2_we = addr_hit[2] & reg_we & !reg_error; + + assign rega2_wd = reg_wdata[31:0]; + assign rega3_we = addr_hit[3] & reg_we & !reg_error; + + assign rega3_wd = reg_wdata[31:0]; + assign rega4_we = addr_hit[4] & reg_we & !reg_error; + + assign rega4_wd = reg_wdata[31:0]; + assign rega5_we = addr_hit[5] & reg_we & !reg_error; + + assign rega5_wd = reg_wdata[31:0]; + assign rega6_we = addr_hit[6] & reg_we & !reg_error; + + assign rega6_wd = reg_wdata[31:0]; + assign rega7_we = addr_hit[7] & reg_we & !reg_error; + + assign rega7_wd = reg_wdata[31:0]; + assign rega8_we = addr_hit[8] & reg_we & !reg_error; + + assign rega8_wd = reg_wdata[31:0]; + assign rega9_we = addr_hit[9] & reg_we & !reg_error; + + assign rega9_wd = reg_wdata[31:0]; + assign rega10_we = addr_hit[10] & reg_we & !reg_error; + + assign rega10_wd = reg_wdata[31:0]; + assign rega11_we = addr_hit[11] & reg_we & !reg_error; + + assign rega11_wd = reg_wdata[31:0]; + assign rega12_we = addr_hit[12] & reg_we & !reg_error; + + assign rega12_wd = reg_wdata[31:0]; + assign rega13_we = addr_hit[13] & reg_we & !reg_error; + + assign rega13_wd = reg_wdata[31:0]; + assign rega14_we = addr_hit[14] & reg_we & !reg_error; + + assign rega14_wd = reg_wdata[31:0]; + assign rega15_we = addr_hit[15] & reg_we & !reg_error; + + assign rega15_wd = reg_wdata[31:0]; + assign rega16_we = addr_hit[16] & reg_we & !reg_error; + + assign rega16_wd = reg_wdata[31:0]; + assign rega17_we = addr_hit[17] & reg_we & !reg_error; + + assign rega17_wd = reg_wdata[31:0]; + assign rega18_we = addr_hit[18] & reg_we & !reg_error; + + assign rega18_wd = reg_wdata[31:0]; + assign rega19_we = addr_hit[19] & reg_we & !reg_error; + + assign rega19_wd = reg_wdata[31:0]; + assign rega20_we = addr_hit[20] & reg_we & !reg_error; + + assign rega20_wd = reg_wdata[31:0]; + assign rega21_we = addr_hit[21] & reg_we & !reg_error; + + assign rega21_wd = reg_wdata[31:0]; + assign rega22_we = addr_hit[22] & reg_we & !reg_error; + + assign rega22_wd = reg_wdata[31:0]; + assign rega23_we = addr_hit[23] & reg_we & !reg_error; + + assign rega23_wd = reg_wdata[31:0]; + assign rega24_we = addr_hit[24] & reg_we & !reg_error; + + assign rega24_wd = reg_wdata[31:0]; + assign rega25_we = addr_hit[25] & reg_we & !reg_error; + + assign rega25_wd = reg_wdata[31:0]; + assign rega26_we = addr_hit[26] & reg_we & !reg_error; + + assign rega26_wd = reg_wdata[31:0]; + assign rega27_we = addr_hit[27] & reg_we & !reg_error; + + assign rega27_wd = reg_wdata[31:0]; + assign rega29_we = addr_hit[29] & reg_we & !reg_error; + + assign rega29_wd = reg_wdata[31:0]; + assign rega30_we = addr_hit[30] & reg_we & !reg_error; + + assign rega30_wd = reg_wdata[31:0]; + assign rega31_we = addr_hit[31] & reg_we & !reg_error; + + assign rega31_wd = reg_wdata[31:0]; + assign rega32_we = addr_hit[32] & reg_we & !reg_error; + + assign rega32_wd = reg_wdata[31:0]; + assign rega33_we = addr_hit[33] & reg_we & !reg_error; + + assign rega33_wd = reg_wdata[31:0]; + assign rega34_we = addr_hit[34] & reg_we & !reg_error; + + assign rega34_wd = reg_wdata[31:0]; + assign rega35_we = addr_hit[35] & reg_we & !reg_error; + + assign rega35_wd = reg_wdata[31:0]; + assign rega36_we = addr_hit[36] & reg_we & !reg_error; + + assign rega36_wd = reg_wdata[31:0]; + assign rega37_we = addr_hit[37] & reg_we & !reg_error; + + assign rega37_wd = reg_wdata[31:0]; + assign regal_we = addr_hit[38] & reg_we & !reg_error; + + assign regal_wd = reg_wdata[31:0]; + assign regb_0_we = addr_hit[39] & reg_we & !reg_error; + + assign regb_0_wd = reg_wdata[31:0]; + assign regb_1_we = addr_hit[40] & reg_we & !reg_error; + + assign regb_1_wd = reg_wdata[31:0]; + assign regb_2_we = addr_hit[41] & reg_we & !reg_error; + + assign regb_2_wd = reg_wdata[31:0]; + assign regb_3_we = addr_hit[42] & reg_we & !reg_error; + + assign regb_3_wd = reg_wdata[31:0]; + assign regb_4_we = addr_hit[43] & reg_we & !reg_error; + + assign regb_4_wd = reg_wdata[31:0]; + + // Assign write-enables to checker logic vector. + always_comb begin + reg_we_check = '0; + reg_we_check[0] = 1'b0; + reg_we_check[1] = 1'b0; + reg_we_check[2] = rega2_we; + reg_we_check[3] = rega3_we; + reg_we_check[4] = rega4_we; + reg_we_check[5] = rega5_we; + reg_we_check[6] = rega6_we; + reg_we_check[7] = rega7_we; + reg_we_check[8] = rega8_we; + reg_we_check[9] = rega9_we; + reg_we_check[10] = rega10_we; + reg_we_check[11] = rega11_we; + reg_we_check[12] = rega12_we; + reg_we_check[13] = rega13_we; + reg_we_check[14] = rega14_we; + reg_we_check[15] = rega15_we; + reg_we_check[16] = rega16_we; + reg_we_check[17] = rega17_we; + reg_we_check[18] = rega18_we; + reg_we_check[19] = rega19_we; + reg_we_check[20] = rega20_we; + reg_we_check[21] = rega21_we; + reg_we_check[22] = rega22_we; + reg_we_check[23] = rega23_we; + reg_we_check[24] = rega24_we; + reg_we_check[25] = rega25_we; + reg_we_check[26] = rega26_we; + reg_we_check[27] = rega27_we; + reg_we_check[28] = 1'b0; + reg_we_check[29] = rega29_we; + reg_we_check[30] = rega30_we; + reg_we_check[31] = rega31_we; + reg_we_check[32] = rega32_we; + reg_we_check[33] = rega33_we; + reg_we_check[34] = rega34_we; + reg_we_check[35] = rega35_we; + reg_we_check[36] = rega36_we; + reg_we_check[37] = rega37_we; + reg_we_check[38] = regal_we; + reg_we_check[39] = regb_0_we; + reg_we_check[40] = regb_1_we; + reg_we_check[41] = regb_2_we; + reg_we_check[42] = regb_3_we; + reg_we_check[43] = regb_4_we; + end + + // Read data return + always_comb begin + reg_rdata_next = '0; + unique case (1'b1) + addr_hit[0]: begin + reg_rdata_next[31:0] = rega0_qs; + end + + addr_hit[1]: begin + reg_rdata_next[31:0] = rega1_qs; + end + + addr_hit[2]: begin + reg_rdata_next[31:0] = rega2_qs; + end + + addr_hit[3]: begin + reg_rdata_next[31:0] = rega3_qs; + end + + addr_hit[4]: begin + reg_rdata_next[31:0] = rega4_qs; + end + + addr_hit[5]: begin + reg_rdata_next[31:0] = rega5_qs; + end + + addr_hit[6]: begin + reg_rdata_next[31:0] = rega6_qs; + end + + addr_hit[7]: begin + reg_rdata_next[31:0] = rega7_qs; + end + + addr_hit[8]: begin + reg_rdata_next[31:0] = rega8_qs; + end + + addr_hit[9]: begin + reg_rdata_next[31:0] = rega9_qs; + end + + addr_hit[10]: begin + reg_rdata_next[31:0] = rega10_qs; + end + + addr_hit[11]: begin + reg_rdata_next[31:0] = rega11_qs; + end + + addr_hit[12]: begin + reg_rdata_next[31:0] = rega12_qs; + end + + addr_hit[13]: begin + reg_rdata_next[31:0] = rega13_qs; + end + + addr_hit[14]: begin + reg_rdata_next[31:0] = rega14_qs; + end + + addr_hit[15]: begin + reg_rdata_next[31:0] = rega15_qs; + end + + addr_hit[16]: begin + reg_rdata_next[31:0] = rega16_qs; + end + + addr_hit[17]: begin + reg_rdata_next[31:0] = rega17_qs; + end + + addr_hit[18]: begin + reg_rdata_next[31:0] = rega18_qs; + end + + addr_hit[19]: begin + reg_rdata_next[31:0] = rega19_qs; + end + + addr_hit[20]: begin + reg_rdata_next[31:0] = rega20_qs; + end + + addr_hit[21]: begin + reg_rdata_next[31:0] = rega21_qs; + end + + addr_hit[22]: begin + reg_rdata_next[31:0] = rega22_qs; + end + + addr_hit[23]: begin + reg_rdata_next[31:0] = rega23_qs; + end + + addr_hit[24]: begin + reg_rdata_next[31:0] = rega24_qs; + end + + addr_hit[25]: begin + reg_rdata_next[31:0] = rega25_qs; + end + + addr_hit[26]: begin + reg_rdata_next[31:0] = rega26_qs; + end + + addr_hit[27]: begin + reg_rdata_next[31:0] = rega27_qs; + end + + addr_hit[28]: begin + reg_rdata_next[31:0] = rega28_qs; + end + + addr_hit[29]: begin + reg_rdata_next[31:0] = rega29_qs; + end + + addr_hit[30]: begin + reg_rdata_next[31:0] = rega30_qs; + end + + addr_hit[31]: begin + reg_rdata_next[31:0] = rega31_qs; + end + + addr_hit[32]: begin + reg_rdata_next[31:0] = rega32_qs; + end + + addr_hit[33]: begin + reg_rdata_next[31:0] = rega33_qs; + end + + addr_hit[34]: begin + reg_rdata_next[31:0] = rega34_qs; + end + + addr_hit[35]: begin + reg_rdata_next[31:0] = rega35_qs; + end + + addr_hit[36]: begin + reg_rdata_next[31:0] = rega36_qs; + end + + addr_hit[37]: begin + reg_rdata_next[31:0] = rega37_qs; + end + + addr_hit[38]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[39]: begin + reg_rdata_next[31:0] = regb_0_qs; + end + + addr_hit[40]: begin + reg_rdata_next[31:0] = regb_1_qs; + end + + addr_hit[41]: begin + reg_rdata_next[31:0] = regb_2_qs; + end + + addr_hit[42]: begin + reg_rdata_next[31:0] = regb_3_qs; + end + + addr_hit[43]: begin + reg_rdata_next[31:0] = regb_4_qs; + end + + default: begin + reg_rdata_next = '1; + end + endcase + end + + // shadow busy + logic shadow_busy; + assign shadow_busy = 1'b0; + + // register busy + assign reg_busy = shadow_busy; + + // Unused signal tieoff + + // wdata / byte enable are not always fully used + // add a blanket unused statement to handle lint waivers + logic unused_wdata; + logic unused_be; + assign unused_wdata = ^reg_wdata; + assign unused_be = ^reg_be; + + // Assertions for Register Interface + `ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni) + `ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni) + + `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o_pre.d_valid, clk_i, !rst_ni) + + `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni) + + // this is formulated as an assumption such that the FPV testbenches do disprove this + // property by mistake + //`ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.chk_en == tlul_pkg::CheckDis) + +endmodule diff --git a/src/ast/rtl/dev_entropy.sv b/src/ast/rtl/dev_entropy.sv new file mode 100644 index 0000000..301221a --- /dev/null +++ b/src/ast/rtl/dev_entropy.sv @@ -0,0 +1,260 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// -------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------- // +// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED. +// +//############################################################################ +// *Name: dev_entropy +// *Module Description: Device Entropy +//############################################################################ + +module dev_entropy #( + parameter int EntropyRateWidth = 4 +) ( + input clk_i, // Entropy Clock + input rst_ni, // Entropy Reset + input clk_dev_i, // Device Clock + input rst_dev_ni, // Device Reset + input dev_en_i, // Device Enable + input [EntropyRateWidth-1:0] dev_rate_i, // Entropy Rate + input dev_ack_i, // Write Valid (EDN_ACK) + input [32-1:0] dev_data_i, // Write Data (EDN_BUS) + output logic dev_wready_o, // Write Ready (EDN_REQ) + output logic dev_data_o // Entropy Data +); + + +//////////////////////////////////// +// Device Enable Sync +//////////////////////////////////// +logic dev_en_dev; + +// Sync dev_en to Dev clock +prim_flop_2sync #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_dev_en_dev_sync ( + .clk_i ( clk_dev_i ), + .rst_ni ( rst_dev_ni ), + .d_i ( dev_en_i ), + .q_o ( dev_en_dev ) +); + + +//////////////////////////////////// +// Entropy Rate +/////////////////////////////////////// +logic fast_start, rate_pulse, rready; +logic [7-1:0] fast_cnt; +logic [(1< 1 || EN -> 0 + +// Clock Output Buffer +//////////////////////////////////////// +prim_clock_buf #( + .NoFpgaBuf ( 1'b1 ) +) u_buf ( + .clk_i ( clk ), + .clk_o ( io_clk_o ) +); + + +`ifdef SYNTHESIS +///////////////////////// +// Unused Signals +///////////////////////// +logic unused_sigs; +assign unused_sigs = ^{ io_osc_cal_i }; +`endif + +endmodule : io_osc diff --git a/src/ast/rtl/rglts_pdm_3p3v.sv b/src/ast/rtl/rglts_pdm_3p3v.sv new file mode 100644 index 0000000..f079ed5 --- /dev/null +++ b/src/ast/rtl/rglts_pdm_3p3v.sv @@ -0,0 +1,416 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// -------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------- // +// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED. +// +//############################################################################ +// *Name: rglts_pdm_3p3v +// *Module Description: Regulators (MAIN & AON) & PDM Logic @3.3V +//############################################################################ + +`include "prim_assert.sv" + +module rglts_pdm_3p3v ( + input vcc_pok_h_i, // VCC Exist @3.3v + input vcaon_pok_por_h_i, // VCAON_POK_POR @1.1v + input vcmain_pok_por_h_i, // VCMAIN_POK_POR @1.1v + input [2-1:0] vio_pok_h_i, // vioa/b_pok signals @1.1v + input clk_src_aon_h_i, // AON Clock @1.1v + input main_pd_h_i, // MAIN Regulator Power Down @1.1v + input por_sync_h_i, // POR (Sync to AON clock) @1.1v + input scan_mode_h_i, // Scan Mode @1.1v + input [2-1:0] otp_power_seq_h_i, // MMR0,24 in @1.1v + input vcaon_supp_i, // + input vcmain_supp_i, // + output logic rglssm_vmppr_h_o, // Regulators SM at VMPPR (vcmaim_pok_por_reset) @3.3v + output logic rglssm_vcmon_h_o, // Regulators state machine at VCMON @3.3v + output logic rglssm_brout_h_o, // Regulators state machine at BROUT @3.3v + output logic vcmain_pok_h_o, // VCMAIN POK @3.3v + output logic vcmain_pok_por_h_o, // VCMAIN_POK_POR @3.3v + output logic vcaon_pok_h_o, // VCAON Exist @3.3v + output logic vcaon_pok_1p1_h_o, // VCAON Exist @3.3v for BE 1.1v (UPF issue) + output logic vcaon_pok_por_h_o, // VCAON_POK_POR @3.3v + output logic [2-1:0] vio_pok_h_o, // vioa/b_pok_h signals @3.3v + output logic vcc_pok_str_h_o, // VCC Exist Stretched @3.3V + output logic vcc_pok_str_1p1_h_o, // VCC Exist Stretched @3.3V for BE 1.1v (UPF issue) + output logic deep_sleep_h_o, // Deep Sleep (main regulator & switch are off) @3.3v + output logic flash_power_down_h_o, // + output logic flash_power_ready_h_o, // + output logic [2-1:0] otp_power_seq_h_o // MMR0,24 masked by PDM, out (VCC) +); + +// Turn 1.1v into 3.3v signals +//////////////////////////////////////// +assign vcaon_pok_por_h_o = vcaon_pok_por_h_i; // Level Up Shifter +assign vcmain_pok_por_h_o = vcmain_pok_por_h_i; // Level Up Shifter +assign vio_pok_h_o[1:0] = vio_pok_h_i[1:0]; // Level Up Shifter + + +/////////////////////////////////////// +// Regulators Enable State Machine +/////////////////////////////////////// +logic fla_pdm_h, otp_pdm_h; +logic [9-1:0] dly_cnt, hc2lc_val, lc2hc_val; // upto 255 aon clock (1275us) + +// DV Hook +logic [1:0] dv_hook, dft_sel; + +`ifndef SYNTHESIS +initial begin + // Regulator Power-up time (non cold power-up) selected according to 'dv_hook' value: + // + // 0: hc2lc_val=HC2LCOC; lc2hc_val=LC2HCOC; + // 1: hc2lc_val=HC2LCOC*2; lc2hc_val=LC2HCOC*2; + // 2: hc2lc_val=9'd2; lc2hc_val=9'd6; + // 3: hc2lc_val=9'd4; lc2hc_val=9'd12; + // + if ( !$value$plusargs("accelerate_regulators_power_up_time=%d", dv_hook) ) begin + dv_hook = 2'd0; + end + `ASSERT_I(accelerate_regulators_power_up_time, dv_hook inside {[0:3]}) +end +`else +assign dv_hook = 2'd0; +`endif + +localparam int unsigned HC2LCOC = ast_pkg::Hc2LcTrCyc; +localparam int unsigned LC2HCOC = ast_pkg::Lc2HcTrCyc; +logic [9-1:0] cld_pu_val; + +`ifndef SYNTHESIS +initial begin + // Cold Power-up time can be selected between 2 and LC2HCOC (default: ast_pkg::Lc2HcTrCyc) + if ( !$value$plusargs("accelerate_cold_power_up_time=%d", cld_pu_val) ) begin + cld_pu_val = LC2HCOC[9-1:0]; + end + `ASSERT_I(accelerate_cold_power_up_time, cld_pu_val inside {[2:LC2HCOC[9-1:0]]}) +end +`else +assign cld_pu_val = LC2HCOC[9-1:0]; +`endif + +// Force 2'b11 to reduce LDOs time & double LDOs start-up time +assign dft_sel = dv_hook; + +assign hc2lc_val = (dft_sel == 2'b10) ? 9'd2 : + (dft_sel == 2'b11) ? 9'd4 : + (dft_sel == 2'b00) ? HC2LCOC[9-1:0] : + HC2LCOC[8-1:0]*2; + +assign lc2hc_val = (dft_sel == 2'b10) ? 9'd6 : + (dft_sel == 2'b11) ? 9'd12 : + (dft_sel == 2'b00) ? LC2HCOC[9-1:0] : + LC2HCOC[8-1:0]*2; + + + +/////////////////////////////////////// +// Regulators State Machine +/////////////////////////////////////// +typedef enum logic [3-1:0] { + RGLS_CLDPU = 3'd0, // Cold power-up (MAIN Regulator ON, AON Regulator OFF, Power Switch Enabled) + RGLS_VCMON = 3'd1, // MAIN Regulator ON (AON Regulator OFF, Power Switch Enabled) + RGLS_VCM2A = 3'd3, // MAIN Regulator ON (AON Regulator rN, Power Switch Enabled->Disabled) + RGLS_VCAON = 3'd7, // AON Regulator ON (MAIN Regulator OFF, Power Switch Diabled) + RGLS_VCA2M = 3'd5, // AON Regulator ON (MAIN Regulator ON, Power Switch Diabled->Enabled) + RGLS_BROUT = 3'd6 // Brownout (MAIN Regulator ON, AON Regulator OFF, Power Switch Enabled) +} rgls_sm_e; + +rgls_sm_e rgls_sm; +logic vcmain_pok_h, vcaon_pok_h, main_pd_str_h; + +// Hold state machin reset on brownout for minimum 13us. +logic rgls_rst_h_n; +assign rgls_rst_h_n = vcc_pok_str_h_o; + +// Syncronizers +// First stage clk FE & second clk RE +/////////////////////////////////////// +logic vcc_pok_fe_h, vcc_pok_s_h; + + +logic clk_src_aon_h_n; +assign clk_src_aon_h_n = scan_mode_h_i ? clk_src_aon_h_i : + !clk_src_aon_h_i; + +always_ff @( posedge clk_src_aon_h_n, negedge rgls_rst_h_n ) begin + if ( !rgls_rst_h_n ) begin + vcc_pok_fe_h <= 1'b0; + end else begin + vcc_pok_fe_h <= vcc_pok_h_i; + end +end + +always_ff @( posedge clk_src_aon_h_i, negedge rgls_rst_h_n ) begin + if ( !rgls_rst_h_n ) begin + vcc_pok_s_h <= 1'b0; + end else begin + vcc_pok_s_h <= vcc_pok_fe_h; + end +end + +// Regulators State Mashine +//////////////////////////////////////// +always_ff @( posedge clk_src_aon_h_i, negedge rgls_rst_h_n ) begin + if ( !rgls_rst_h_n ) begin + vcmain_pok_h <= 1'b0; // VCMAIN Rail Disabled + vcaon_pok_h <= 1'b0; // VCAON Rail Disabled + main_pd_str_h <= 1'b0; // Power Down Stratch off + // + rglssm_vcmon_h_o <= 1'b0; // + rglssm_vmppr_h_o <= 1'b1; // (rgls_sm == RRGLS_[CLDPU | VCAON | VCA2M]) + rglssm_brout_h_o <= 1'b0; // + fla_pdm_h <= 1'b1; // !((rgls_sm == RGLS_VCMON) || (rgls_sm == RGLS_BROUT)) + // + dly_cnt <= cld_pu_val; // VCMAIN Regulator power-up time + // + rgls_sm <= RGLS_CLDPU; // Power VCMAIN (Cold) + end else begin + unique case ( rgls_sm ) + RGLS_CLDPU: begin + vcmain_pok_h <= 1'b0; // VCMAIN Rail Disabled + vcaon_pok_h <= 1'b0; // VCAON Rail Disabled + main_pd_str_h <= 1'b0; // Power Down Stratch off + // + rglssm_vcmon_h_o <= 1'b0; // + rglssm_vmppr_h_o <= 1'b1; // (rgls_sm == RRGLS_[CLDPU | VCAON | VCA2M]) + rglssm_brout_h_o <= 1'b0; // + fla_pdm_h <= 1'b1; // !((rgls_sm == RGLS_VCMON)||(rgls_sm == RGLS_BROUT)) + // + dly_cnt <= dly_cnt - 1'b1; + // + if (dly_cnt == '0) begin + vcmain_pok_h <= 1'b1; // VCMAIN Rail Enable + vcaon_pok_h <= 1'b1; // VCAON Rail Enabled + rglssm_vcmon_h_o <= 1'b1; // (rgls_sm == RGLS_VCMON) + rglssm_vmppr_h_o <= 1'b0; // (rgls_sm == RRGLS_[CLDPU | VCAON | VCA2M]) + fla_pdm_h <= 1'b0; // + rgls_sm <= RGLS_VCMON; // VCMAIN Regultor is ON! + end else begin + rgls_sm <= RGLS_CLDPU; // Power VCMAIN! + end + end + + RGLS_VCMON: begin + vcmain_pok_h <= 1'b1; // VCMAIN Rail Enabled + vcaon_pok_h <= 1'b1; // VCAON Rail Enabled + main_pd_str_h <= 1'b0; // Power Down Stratch + // + rglssm_vcmon_h_o <= 1'b1; // (rgls_sm == RGLS_VCMON) + rglssm_vmppr_h_o <= 1'b0; // (rgls_sm == RRGLS_[CLDPU | VCAON | VCA2M]) + rglssm_brout_h_o <= 1'b0; // + fla_pdm_h <= 1'b0; // + // + dly_cnt <= hc2lc_val; // VCAON Regulator power-up time + // + if ( !vcc_pok_s_h ) begin + rglssm_vcmon_h_o <= 1'b0; // + rglssm_vmppr_h_o <= 1'b0; // (rgls_sm == RRGLS_[CLDPU | VCAON | VCA2M]) + rglssm_brout_h_o <= 1'b1; // (rgls_sm == RGLS_BROUT) + fla_pdm_h <= 1'b0; // + rgls_sm <= RGLS_BROUT; // Brownout + end else if ( main_pd_h_i && !por_sync_h_i ) begin + main_pd_str_h <= 1'b1; // Power Down Stratch on + rglssm_vcmon_h_o <= 1'b0; // + rglssm_vmppr_h_o <= 1'b0; // (rgls_sm == RRGLS_[CLDPU | VCAON | VCA2M]) + fla_pdm_h <= 1'b1; // !((rgls_sm == RGLS_VCMON) || (rgls_sm == RGLS_BROUT)) + rgls_sm <= RGLS_VCM2A; // VCMAIN to VCAON Transition + end else begin + rgls_sm <= RGLS_VCMON; // VCMAIN Regulator is ON! + end + end + + RGLS_VCM2A: begin + vcmain_pok_h <= 1'b1; // VCMAIN Rail Enabled + vcaon_pok_h <= 1'b1; // VCAON Rail Enabled + main_pd_str_h <= 1'b1; // Power Down Stratch + // + rglssm_vcmon_h_o <= 1'b0; // + rglssm_vmppr_h_o <= 1'b0; // (rgls_sm == RRGLS_[CLDPU | VCAON | VCA2M]) + rglssm_brout_h_o <= 1'b0; // + fla_pdm_h <= 1'b1; // !((rgls_sm == RGLS_VCMON) || (rgls_sm == RGLS_BROUT)) + // + dly_cnt <= dly_cnt - 1'b1; + // + if ( por_sync_h_i ) begin + vcmain_pok_h <= 1'b1; // VCMAIN Rail Enable + vcaon_pok_h <= 1'b1; // VCAON Rail Enabled + rglssm_vcmon_h_o <= 1'b1; // (rgls_sm == RGLS_VCMON) + rglssm_vmppr_h_o <= 1'b0; // (rgls_sm == RRGLS_[CLDPU | VCAON | VCA2M]) + fla_pdm_h <= 1'b0; // + rgls_sm <= RGLS_VCMON; // VCMAIN Regultor is ON! + end else if ( dly_cnt == '0 ) begin + rglssm_vmppr_h_o <= 1'b1; // (rgls_sm == RRGLS_[CLDPU | VCAON | VCA2M]) + rgls_sm <= RGLS_VCAON; // VCAON Regulator is ON! + end else begin + rgls_sm <= RGLS_VCM2A; // VCMAIN to VCAON Transition + end + end + + RGLS_VCAON: begin + vcmain_pok_h <= 1'b0; // VCMAIN Rail Disabled + vcaon_pok_h <= 1'b1; // VCAON Rail Enabled + main_pd_str_h <= 1'b1; // Power Down Stratch + // + rglssm_vcmon_h_o <= 1'b0; // + rglssm_vmppr_h_o <= 1'b1; // (rgls_sm == RRGLS_[CLDPU | VCAON | VCA2M]) + rglssm_brout_h_o <= 1'b0; // + fla_pdm_h <= 1'b1; // !((rgls_sm == RGLS_VCMON) || (rgls_sm == RGLS_BROUT)) + // + dly_cnt <= lc2hc_val; // VCMAIN Regulator power-up time + // + if ( !main_pd_h_i || por_sync_h_i ) begin + rglssm_vmppr_h_o <= 1'b1; // (rgls_sm == RRGLS_[CLDPU | VCAON | VCA2M]) + rgls_sm <= RGLS_VCA2M; // VCAON->VCMAIN Transition + end else begin + rgls_sm <= RGLS_VCAON; // VCAON Regulator is ON! + end + end + + RGLS_VCA2M: begin + vcmain_pok_h <= 1'b0; // VCMAIN Rail Disable + vcaon_pok_h <= 1'b1; // VCAON Rail Enabled + main_pd_str_h <= 1'b0; // Power Down Stratch off + // + rglssm_vcmon_h_o <= 1'b0; // + rglssm_vmppr_h_o <= 1'b1; // (rgls_sm == RRGLS_[CLDPU | VCAON | VCA2M]) + rglssm_brout_h_o <= 1'b0; // + fla_pdm_h <= 1'b1; // !((rgls_sm == RGLS_VCMON) || (rgls_sm == RGLS_BROUT)) + // + dly_cnt <= dly_cnt - 1'b1; + // + if ( dly_cnt == '0 ) begin + vcmain_pok_h <= 1'b1; // VCMAIN Rail Enable + vcaon_pok_h <= 1'b1; // VCAON Rail Enabled + rglssm_vcmon_h_o <= 1'b1; // (rgls_sm == RGLS_VCMON) + rglssm_vmppr_h_o <= 1'b0; // (rgls_sm == RRGLS_[CLDPU | VCAON | VCA2M]) + fla_pdm_h <= 1'b0; // + rgls_sm <= RGLS_VCMON; // VCMAIN Regulator is ON! + end else begin + rgls_sm <= RGLS_VCA2M; // VCAON->VCMAIN Transition + end + end + + RGLS_BROUT: begin + vcmain_pok_h <= 1'b1; // VCMAIN Rail Enabled + vcaon_pok_h <= 1'b1; // VCAON Rail Enabled + main_pd_str_h <= 1'b0; // Powe Down Stratch off + // + rglssm_vcmon_h_o <= 1'b0; // + rglssm_vmppr_h_o <= 1'b0; // (rgls_sm == RRGLS_[CLDPU | VCAON | VCA2M]) + rglssm_brout_h_o <= 1'b1; // (rgls_sm == RGLS_BROUT) + fla_pdm_h <= 1'b0; // + // + dly_cnt <= lc2hc_val; // VCMAIN Regulator power-up time + // + rgls_sm <= RGLS_BROUT; // Brownout + end + + default: begin + vcmain_pok_h <= 1'b0; // VCMAIN Rail Disabled + vcaon_pok_h <= 1'b0; // VCAON Rail Disabled + main_pd_str_h <= 1'b0; // Powe Down Stratch off + // + rglssm_vcmon_h_o <= 1'b0; // + rglssm_vmppr_h_o <= 1'b1; // (rgls_sm == RRGLS_[CLDPU | VCAON | VCA2M]) + rglssm_brout_h_o <= 1'b0; // + fla_pdm_h <= 1'b1; // !((rgls_sm == RGLS_VCMON) || (rgls_sm == RGLS_BROUT)) + // + dly_cnt <= lc2hc_val; // VCMAIN Regulator power-up time + // + rgls_sm <= RGLS_CLDPU; // Power VCMAIN (Cold) + end + endcase + end +end + + +/////////////////////////////////////// +// VCMAIN_POK & VCAON POK +/////////////////////////////////////// +assign vcmain_pok_h_o = vcmain_pok_h && vcmain_supp_i; +// VCAON POK is needed for cold power-up to enable the AON clock +// Therefore, it is connected directly to VCC POK. +assign vcaon_pok_h_o = vcc_pok_h_i && vcaon_supp_i; +assign vcaon_pok_1p1_h_o = vcaon_pok_h_o; // For layout separation + + +/////////////////////////////////////// +// Streched VCC_POK During Brownout +/////////////////////////////////////// +localparam int VccPokStrNum = 4; // (Min-Max) (3-4)x5us=(15-20)us + +logic vcc_pok_set_h, vcc_pok_rst_h_n; +logic [VccPokStrNum-1:0] vcc_pok_str_no_scan_h; + +assign vcc_pok_rst_h_n = vcc_pok_h_i || vcaon_pok_h_o; // Non-Scan + +// Enable proper order of reset/set execution +always_comb begin + vcc_pok_set_h = vcc_pok_rst_h_n && vcc_pok_h_i; +end + +always_ff @( posedge clk_src_aon_h_i, negedge vcc_pok_rst_h_n, posedge vcc_pok_set_h ) begin + if ( !vcc_pok_rst_h_n ) begin + vcc_pok_str_no_scan_h[0] <= 1'b0; + end else if ( vcc_pok_set_h ) begin + vcc_pok_str_no_scan_h[0] <= 1'b1; + end else begin + vcc_pok_str_no_scan_h[0] <= 1'b0; + end +end + +for (genvar i = 1; i < VccPokStrNum; i++ ) begin : gen_vcc_pok_str + always_ff @( posedge clk_src_aon_h_i, negedge vcc_pok_rst_h_n, posedge vcc_pok_set_h ) begin + if ( !vcc_pok_rst_h_n ) begin + vcc_pok_str_no_scan_h[i] <= 1'b0; + end else if ( vcc_pok_set_h ) begin + vcc_pok_str_no_scan_h[i] <= 1'b1; + end else begin + vcc_pok_str_no_scan_h[i] <= vcc_pok_str_no_scan_h[i-1]; + end + end +end + +assign vcc_pok_str_h_o = vcc_pok_str_no_scan_h[VccPokStrNum-1]; +assign vcc_pok_str_1p1_h_o = vcc_pok_str_no_scan_h[VccPokStrNum-1]; + + +/////////////////////////////////////// +// Deep Sleep Indication +/////////////////////////////////////// +always_ff @( posedge clk_src_aon_h_i, negedge rgls_rst_h_n ) begin + if ( !rgls_rst_h_n ) begin + deep_sleep_h_o <= 1'b0; + end else begin + deep_sleep_h_o <= main_pd_h_i || main_pd_str_h; + end +end + + +/////////////////////////////////////// +// Flash +/////////////////////////////////////// +// fla_pdm_h = !(rglssm_vcmon || rglssm_brout); +assign flash_power_down_h_o = scan_mode_h_i || fla_pdm_h; +assign flash_power_ready_h_o = vcc_pok_h_i; + + +/////////////////////////////////////// +// OTP +/////////////////////////////////////// +assign otp_pdm_h = !rglssm_vcmon_h_o; +assign otp_power_seq_h_o[0] = !scan_mode_h_i && !otp_pdm_h && otp_power_seq_h_i[0]; +assign otp_power_seq_h_o[1] = scan_mode_h_i || otp_pdm_h || otp_power_seq_h_i[1]; + + +///////////////////// +// Unused Signals // +///////////////////// +logic unused_sigs; + +assign unused_sigs = ^{ vcaon_pok_h }; + +endmodule : rglts_pdm_3p3v diff --git a/src/ast/rtl/rng.sv b/src/ast/rtl/rng.sv new file mode 100644 index 0000000..fab38d7 --- /dev/null +++ b/src/ast/rtl/rng.sv @@ -0,0 +1,161 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// -------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------- // +// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED. +// +//############################################################################ +// *Name: rng +// *Module Description: Random (bit/s) Generator (Pseudo Model) +//############################################################################ + +`include "prim_assert.sv" + +module rng #( + parameter int EntropyStreams = 4 +) ( + input clk_i, // Non-Jittery Clock (TLUL) + input rst_ni, // Non-Jittery Reset (TLUL) + input clk_ast_rng_i, // Jittery Clock (RNG) + input rst_ast_rng_ni, // Jittery Reset (RNG) + input rng_en_i, // RNG Enable + input rng_fips_i, // RNG FIPS Enable + input scan_mode_i, // Scan Mode + output logic [EntropyStreams-1:0] rng_b_o, // RNG Bus/Bits Output + output logic rng_val_o // RNG Bus/Bits Valid +); + +/////////////////////////////////////// +// RNG Bus using LFSR +/////////////////////////////////////// +logic rst_n; +logic[EntropyStreams-1:0] lfsr_val; + +assign rst_n = scan_mode_i ? rst_ni : rst_ni && rng_en_i; + +// These LFSR parameters have been generated with +// $ ./util/design/gen-lfsr-seed.py --width 64 --seed 15513 --prefix "Rng" +localparam int RngLfsrWidth = 64; +typedef logic [RngLfsrWidth-1:0] rng_lfsr_seed_t; +typedef logic [RngLfsrWidth-1:0][$clog2(RngLfsrWidth)-1:0] rng_lfsr_perm_t; +localparam rng_lfsr_seed_t RndCnstRngLfsrSeedDefault = 64'h1d033d20eed3b14; +localparam rng_lfsr_perm_t RndCnstRngLfsrPermDefault = { + 128'h98c2c94ab5e40420ed73f6c7396cd9e1, + 256'h58c6d7435ddb2ed1f22400c53a5aaa796ef7785e120628fbabc87f0b3928550f +}; + +prim_lfsr #( + .LfsrDw ( RngLfsrWidth ), + .EntropyDw ( 1 ), + .StateOutDw ( EntropyStreams ), + .DefaultSeed ( RndCnstRngLfsrSeedDefault ), + .StatePermEn ( 1'b1 ), + .StatePerm ( RndCnstRngLfsrPermDefault ), + .ExtSeedSVA ( 1'b0 ) // ext seed is unused +) u_rng_lfsr ( + .clk_i ( clk_i ), + .rst_ni ( rst_n ), + .lfsr_en_i ( rng_en_i ), + .seed_en_i ( 1'b0 ), + .seed_i ( '0 ), + .entropy_i ( 1'b0 ), + .state_o ( lfsr_val ) +); + +logic srate_rng_val; +logic [12-1:0] srate_cnt, srate_value; +logic [EntropyStreams-1:0] rng_b; + +`ifndef SYNTHESIS +logic [12-1:0] dv_srate_value; +// 4-bit rng_b needs at least 5 clocks. While the limit for these min and max values is 5:500, the +// default is set to a shorter window of 32:128 to avoid large runtimes. +logic [12-1:0] rng_srate_value_min = 12'd32; +logic [12-1:0] rng_srate_value_max = 12'd128; + +initial begin : rng_plusargs + void'($value$plusargs("rng_srate_value_min=%0d", rng_srate_value_min)); + void'($value$plusargs("rng_srate_value_max=%0d", rng_srate_value_max)); + `ASSERT_I(DvRngSrateMinCheck, rng_srate_value_min inside {[5:500]}) + `ASSERT_I(DvRngSrateMaxCheck, rng_srate_value_max inside {[5:500]}) + `ASSERT_I(DvRngSrateBoundsCheck, rng_srate_value_max >= rng_srate_value_min) + dv_srate_value = 12'($urandom_range(int'(rng_srate_value_min), int'(rng_srate_value_max))); + void'($value$plusargs("rng_srate_value=%0d", dv_srate_value)); + `ASSERT_I(DvSrateValueCheck, dv_srate_value inside {[5:500]}) +end + +assign srate_value = dv_srate_value; +`else +assign srate_value = 12'd120; +`endif + +logic src_busy; + +always_ff @( posedge clk_i, negedge rst_n ) begin + if ( !rst_n ) begin + srate_cnt <= 12'h000; + srate_rng_val <= 1'b0; + end else if ( (srate_cnt == srate_value) && src_busy ) begin + srate_rng_val <= 1'b0; + end else if ( srate_cnt == srate_value ) begin + srate_cnt <= 12'h000; + srate_rng_val <= 1'b1; + end else begin + srate_cnt <= srate_cnt + 1'b1; + srate_rng_val <= 1'b0; + end +end + + +//////////////////////////////////////// +// Sychronize Bus & Valid to RNG Clock +//////////////////////////////////////// +logic sync_rng_val, srate_rng_val_en; + +ast_pulse_sync u_rng_val_pulse_sync ( + .scan_mode_i ( scan_mode_i ), + // source clock domain + .clk_src_i ( clk_i ), + .rst_src_ni ( rst_n ), + .src_pulse_i ( srate_rng_val ), + .src_pulse_en_o ( srate_rng_val_en ), + .src_busy_o ( src_busy ), + // destination clock domain + .clk_dst_i ( clk_ast_rng_i ), + .rst_dst_ni ( rst_ast_rng_ni ), + .dst_pulse_o ( sync_rng_val ) +); + +// Sanple & Hold the rng_b value until the sync completes +always_ff @( posedge clk_i, negedge rst_n ) begin + if ( !rst_n ) begin + rng_b <= {EntropyStreams{1'b0}}; + end else if ( srate_rng_val_en ) begin + rng_b <= lfsr_val[EntropyStreams-1:0]; + end +end + +//Sync to RNG clock domain +always_ff @( posedge clk_ast_rng_i, negedge rst_ast_rng_ni ) begin + if (!rst_ast_rng_ni ) begin + rng_b_o <= {EntropyStreams{1'b0}}; + rng_val_o <= 1'b0; + end else if ( sync_rng_val ) begin + rng_b_o <= rng_b[EntropyStreams-1:0]; + rng_val_o <= 1'b1; + end else begin + rng_val_o <= 1'b0; + end +end + + +/////////////////////// +// Unused Signals +/////////////////////// +logic unused_sigs; +assign unused_sigs = ^{ + rng_fips_i // Used in ASIC implementation + }; + +endmodule : rng diff --git a/src/ast/rtl/sys_clk.sv b/src/ast/rtl/sys_clk.sv new file mode 100644 index 0000000..504dd77 --- /dev/null +++ b/src/ast/rtl/sys_clk.sv @@ -0,0 +1,69 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// -------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------- // +// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED. +// +//############################################################################ +// *Name: sys_clk +// *Module Description: System Clock +//############################################################################ + +module sys_clk ( + input clk_src_sys_jen_i, // System Source Clock Jitter Enable + input clk_src_sys_en_i, // System Source Clock Enable + input clk_sys_pd_ni, // System Clock Power-down + input rst_sys_clk_ni, // System Clock Logic reset + input vcore_pok_h_i, // VCORE POK @3.3V (for OSC) + input scan_mode_i, // Scan Mode + input sys_osc_cal_i, // System Oscillator Calibrated +`ifdef AST_BYPASS_CLK + input clk_sys_ext_i, // FPGA/VERILATOR Clock input +`endif + output logic clk_src_sys_o, // System Source Clock + output logic clk_src_sys_val_o // System Source Clock Valid +); + +logic clk, osc_en, sys_clk_en; + +assign osc_en = (clk_src_sys_en_i && clk_sys_pd_ni && rst_sys_clk_ni); +assign sys_clk_en = scan_mode_i || osc_en; + +// Clock Oscilator +/////////////////////////////////////// +sys_osc u_sys_osc ( + .vcore_pok_h_i ( vcore_pok_h_i ), + .sys_en_i ( sys_clk_en ), + .sys_jen_i ( clk_src_sys_jen_i ), + .sys_osc_cal_i ( sys_osc_cal_i ), +`ifdef AST_BYPASS_CLK + .clk_sys_ext_i ( clk_sys_ext_i ), +`endif + .sys_clk_o ( clk ) +); // of u_sys_osc + +// Clock & Valid +/////////////////////////////////////// +prim_clock_buf #( + .NoFpgaBuf ( 1'b1 ) +) u_clk_sys_buf( + .clk_i ( clk ), + .clk_o ( clk_src_sys_o ) +); + +// 2-stage de-assertion +logic rst_val_n; +assign rst_val_n = sys_clk_en; + +prim_flop_2sync #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_no_scan_val_sync ( + .clk_i ( clk_src_sys_o ), + .rst_ni ( rst_val_n ), + .d_i ( 1'b1 ), + .q_o ( clk_src_sys_val_o ) +); + +endmodule : sys_clk diff --git a/src/ast/rtl/sys_osc.sv b/src/ast/rtl/sys_osc.sv new file mode 100644 index 0000000..3a3db36 --- /dev/null +++ b/src/ast/rtl/sys_osc.sv @@ -0,0 +1,158 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +//############################################################################ +// *Name: sys_osc +// *Module Description: System Clock Oscilator +//############################################################################ + +module sys_osc ( + input vcore_pok_h_i, // VCORE POK @3.3V + input sys_en_i, // System Source Clock Enable + input sys_jen_i, // System Source Clock Jitter Enable + input sys_osc_cal_i, // System Oscillator Calibrated +`ifdef AST_BYPASS_CLK + input clk_sys_ext_i, // FPGA/VERILATOR Clock input +`endif + output logic sys_clk_o // System Clock Output +); + +`ifndef AST_BYPASS_CLK +`ifndef SYNTHESIS +// Behavioral Model +//////////////////////////////////////// +timeunit 1ns / 1ps; + +real CLK_PERIOD; + +reg init_start; +initial init_start = 1'b0; +logic cal_sys_clk_70mhz = 1'b0; +logic [16-1:0] jrate, jrate_cnt; + +initial begin + jrate = 16'(1 << $urandom_range(7, 0)) - 1'b1; + void'($value$plusargs("cal_sys_clk_70mhz=%0b", cal_sys_clk_70mhz)); + #1; + init_start = 1'b1; + #1; + $display("\n%m: System Clock Power-up Frequency: %0d Hz", $rtoi(10**9/CLK_PERIOD)); +end + +// Enable 5us RC Delay on rise +wire en_osc_re_buf, en_osc_re, sys_jen; +buf #(ast_bhv_pkg::SYS_EN_RDLY, 0) b0 (en_osc_re_buf, (vcore_pok_h_i && sys_en_i)); +assign en_osc_re = en_osc_re_buf && init_start; +assign sys_jen = sys_jen_i && en_osc_re_buf && init_start; + +// Clock Oscillator +//////////////////////////////////////// +real CalSysClkPeriod, UncSysClkPeriod, SysClkPeriod, jitter; + +initial CalSysClkPeriod = cal_sys_clk_70mhz ? $itor( 14286 ) : // 14286ps (70MHz) + $itor( 10000 ); // 10000ps (100MHz) + +initial UncSysClkPeriod = $itor( $urandom_range(40000, 16667) ); // 40000-16667ps (25-60MHz) + +assign SysClkPeriod = (sys_osc_cal_i && init_start) ? CalSysClkPeriod : UncSysClkPeriod; + +logic clk; + +// -20% Jitter on calibrated frequency +always_ff (* xprop_off *) @( posedge clk, negedge vcore_pok_h_i ) begin + if ( !vcore_pok_h_i ) begin + jitter <= 0.0; + jrate_cnt <= '0; + end else if ( !sys_jen ) begin + jrate_cnt <= '0; + jitter <= 0.0; + end else if ( jrate_cnt == '0 ) begin + jrate_cnt <= jrate; + jitter <= cal_sys_clk_70mhz ? $itor($urandom_range(3571, 0)) : // 56MHz - 70MHz + $itor($urandom_range(2500, 0)); // 80MHz - 100MHz + end else if ( jrate_cnt > '0 ) begin + jrate_cnt <= jrate_cnt - 1'b1; + end +end + +assign CLK_PERIOD = (SysClkPeriod + jitter)/1000; + +// Free running oscillator +reg clk_osc; +initial clk_osc = 1'b1; + +always begin + #(CLK_PERIOD/2) clk_osc = ~clk_osc; +end + +logic en_osc; + +// HDL Clock Gate +logic en_clk; + +always_latch begin + if ( !clk_osc ) en_clk = en_osc; +end + +assign clk = clk_osc && en_clk; +`else // of SYNTHESIS +// SYNTHESIS/LINTER +/////////////////////////////////////// +logic en_osc_re; +assign en_osc_re = vcore_pok_h_i && sys_en_i; + +logic clk, en_osc; +assign clk = 1'b0; +`endif // of SYNTHESIS +`else // of AST_BYPASS_CLK +// VERILATOR/FPGA +/////////////////////////////////////// +logic en_osc_re; +assign en_osc_re = vcore_pok_h_i && sys_en_i; + +// Clock Oscillator +//////////////////////////////////////// +logic clk, en_osc; + +prim_clock_gating #( + .NoFpgaGate ( 1'b1 ) +) u_clk_ckgt ( + .clk_i ( clk_sys_ext_i ), + .en_i ( en_osc ), + .test_en_i ( 1'b0 ), + .clk_o ( clk ) +); +`endif + +logic en_osc_fe; + +// Syncronize en_osc to clk FE for glitch free disable +always_ff @( negedge clk, negedge vcore_pok_h_i ) begin + if ( !vcore_pok_h_i ) begin + en_osc_fe <= 1'b0; + end else begin + en_osc_fe <= en_osc_re; + end +end + +assign en_osc = en_osc_re || en_osc_fe; // EN -> 1 || EN -> 0 + +// Clock Output Buffer +//////////////////////////////////////// +prim_clock_buf #( + .NoFpgaBuf ( 1'b1 ) +) u_buf ( + .clk_i ( clk ), + .clk_o ( sys_clk_o ) +); + + +`ifdef SYNTHESIS +///////////////////////// +// Unused Signals +///////////////////////// +logic unused_sigs; +assign unused_sigs = ^{ sys_osc_cal_i, sys_jen_i }; +`endif + +endmodule : sys_osc diff --git a/src/ast/rtl/usb_clk.sv b/src/ast/rtl/usb_clk.sv new file mode 100644 index 0000000..e20222e --- /dev/null +++ b/src/ast/rtl/usb_clk.sv @@ -0,0 +1,147 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// -------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------- // +// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED. +// +//############################################################################ +// *Name: usb_clk +// *Module Description: USB Clock +//############################################################################ + +module usb_clk ( + input vcore_pok_h_i, // VCORE POK @3.3V (for OSC) + input clk_usb_pd_ni, // USB Clock Power-down + input rst_usb_clk_ni, // USB Clock Logic reset + input clk_src_usb_en_i, // USB Source Clock Enable + input usb_ref_val_i, // USB Reference (Pulse) Valid + input usb_ref_pulse_i, // USB Reference Pulse + input clk_ast_usb_i, // USB Bufferd Clock + input rst_ast_usb_ni, // USB Bufferd Reset + input scan_mode_i, // Scan Mode + input usb_osc_cal_i, // USB Oscillator Calibrated +`ifdef AST_BYPASS_CLK + input clk_usb_ext_i, // FPGA/VERILATOR Clock input +`endif + // + output logic clk_src_usb_o, // USB Source Clock + output logic clk_src_usb_val_o // USB Source Clock Valid +); + +logic clk, osc_en, usb_clk_en; + +assign osc_en = (clk_src_usb_en_i && clk_usb_pd_ni && rst_usb_clk_ni); +assign usb_clk_en = scan_mode_i || osc_en; + +logic rst_da_n, rst_n; + +// 2-stage de-assertion +prim_flop_2sync #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_rst_da ( + .clk_i ( clk_src_usb_o ), + .rst_ni ( rst_usb_clk_ni ), + .d_i ( 1'b1 ), + .q_o ( rst_da_n ) +); + +assign rst_n = scan_mode_i ? rst_ast_usb_ni : rst_da_n; + + +/////////////////////////////////////// +// Clock Calibrate & Drift Adjusment +/////////////////////////////////////// + +// Reference Pulse Detect +/////////////////////////////////////// +logic ref_pulse_in, ref_pulse_re, src_pulse_en, src_busy; + +assign ref_pulse_in = usb_ref_pulse_i && usb_ref_val_i; + +ast_pulse_sync u_ref_pulse_sync ( + .scan_mode_i ( scan_mode_i ), + // source clock domain + .clk_src_i ( clk_ast_usb_i ), + .rst_src_ni ( rst_ast_usb_ni ), + .src_pulse_i ( ref_pulse_in ), + .src_pulse_en_o ( src_pulse_en ), + .src_busy_o ( src_busy ), + // destination clock domain + .clk_dst_i ( clk ), + .rst_dst_ni ( rst_n ), + .dst_pulse_o ( ref_pulse_re ) +); + +// Clock Oscilator +/////////////////////////////////////// +// 2-stage de-assertion +logic rst_usb_n; + +prim_flop_2sync #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_rst_ast_usb_da ( + .clk_i ( clk ), + .rst_ni ( rst_ast_usb_ni ), + .d_i ( 1'b1 ), + .q_o ( rst_usb_n ) +); + +// Sync usb_ref_val_i to clk +logic usb_ref_val; + +prim_flop_2sync #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_ref_val_sync ( + .clk_i ( clk ), + .rst_ni ( rst_usb_n ), + .d_i ( usb_ref_val_i ), + .q_o ( usb_ref_val ) +); + +usb_osc u_usb_osc ( + .vcore_pok_h_i ( vcore_pok_h_i ), + .usb_en_i (usb_clk_en ), + .usb_ref_pulse_i ( ref_pulse_re ), + .usb_ref_val_i ( usb_ref_val ), + .usb_osc_cal_i ( usb_osc_cal_i ), +`ifdef AST_BYPASS_CLK + .clk_usb_ext_i ( clk_usb_ext_i ), +`endif + .usb_clk_o ( clk ) +); // u_usb_osc + +// Clock & Valid +/////////////////////////////////////// +prim_clock_buf #( + .NoFpgaBuf ( 1'b1 ) +) u_clk_usb_buf( + .clk_i ( clk ), + .clk_o ( clk_src_usb_o ) +); + +// 2-stage de-assertion +logic rst_val_n; +assign rst_val_n = usb_clk_en; + +prim_flop_2sync #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_no_scan_val_sync ( + .clk_i ( clk_src_usb_o ), + .rst_ni ( rst_val_n ), + .d_i ( 1'b1 ), + .q_o ( clk_src_usb_val_o ) +); + + +///////////////////////// +// Unused Signals +///////////////////////// +logic unused_sigs; +assign unused_sigs = ^{ src_pulse_en, src_busy }; + +endmodule : usb_clk diff --git a/src/ast/rtl/usb_osc.sv b/src/ast/rtl/usb_osc.sv new file mode 100644 index 0000000..707bba5 --- /dev/null +++ b/src/ast/rtl/usb_osc.sv @@ -0,0 +1,183 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +//############################################################################ +// *Name: usb_osc +// *Module Description: USB Clock Oscilator +//############################################################################ + +module usb_osc ( + input vcore_pok_h_i, // VCORE POK @3.3V + input usb_en_i, // USB Source Clock Enable + input usb_ref_pulse_i, // USB Reference Pulse + input usb_ref_val_i, // USB Reference Valid + input usb_osc_cal_i, // USB Oscillator Calibrated +`ifdef AST_BYPASS_CLK + input clk_usb_ext_i, // FPGA/VERILATOR Clock input +`endif + output logic usb_clk_o // USB Clock Output +); + +`ifndef AST_BYPASS_CLK +`ifndef SYNTHESIS +// Behavioral Model +//////////////////////////////////////// +timeunit 1ns / 1ps; + +real CLK_PERIOD; +integer beacon_rdly; +bit calibrate_usb_clk, max_drift; +localparam int MAXUSBDRIFT = 416; // 416 is +/-2% of 48MHz; 694 is +/-3% of 48MHz +integer usb_clk_drift; + +reg init_start; +initial init_start = 1'b0; + +initial begin + // With this flag activated, +calibrate_usb_clk=0. the USB clock will be calibrated + // as-soon-as the 'ast_init_done_o' gets active (using '=1' will delay by 1 ns). + // + // | <- BEACON_RDLY in ns -> | + // < un-calibrated clock >< calibrated+drift >< calibrated > + // _______________________/``````````````````````````````````````````````````` ast_init_done_o + // + if ( !$value$plusargs("calibrate_usb_clk=%0d", beacon_rdly) ) begin + beacon_rdly = 0; + calibrate_usb_clk = 1'b0; + end else begin + calibrate_usb_clk = 1'b1; + end + // Max USB drift is: +/-2% + if ( !$value$plusargs("usb_max_drift=%0b", max_drift) ) begin + max_drift = 1'b0; + end + // + #1; + init_start = 1'b1; + #1; + $display("\n%m: USB Clock Power-up Frequency: %0d Hz", $rtoi(10**9/CLK_PERIOD)); + usb_clk_drift = max_drift ? ($urandom_range(0, 1) ? MAXUSBDRIFT : -MAXUSBDRIFT) : // +2% or -2% + ($urandom_range(0, 2*MAXUSBDRIFT) - MAXUSBDRIFT); // Up to +/-2% + $display("%m: USB Clock Drift: %0d ps", usb_clk_drift); +end + +// Enable 5us RC Delay on rise +wire en_osc_re_buf, en_osc_re; +buf #(ast_bhv_pkg::USB_EN_RDLY, 0) b0 (en_osc_re_buf, (vcore_pok_h_i && usb_en_i)); +assign en_osc_re = en_osc_re_buf && init_start; + +logic usb_ref_val_buf, zero_drift; + +buf #(ast_bhv_pkg::USB_VAL_RDLY, ast_bhv_pkg::USB_VAL_FDLY) b1 + (usb_ref_val_buf, (vcore_pok_h_i && usb_ref_val_i)); + +buf #(beacon_rdly, 0) b2 (usb_beacon_on_buf, (usb_osc_cal_i && calibrate_usb_clk)); + +assign zero_drift = (usb_ref_val_buf && calibrate_usb_clk || usb_beacon_on_buf) && init_start; + +logic [4-1:0] ref_pulse_cnt_down; + +always_ff @( posedge usb_clk_o, negedge usb_ref_val_i ) begin + if ( !usb_ref_val_i ) begin + ref_pulse_cnt_down <= ast_reg_pkg::NumUsbBeaconPulses[4-1:0]; + end else if ( (ref_pulse_cnt_down > 4'h0) && usb_ref_pulse_i ) begin + ref_pulse_cnt_down <= ref_pulse_cnt_down - 1'b1; + end +end + +// Clock Oscillator +//////////////////////////////////////// +real CalUsbClkPeriod, UncUsbClkPeriod, UsbClkPeriod, drift; + +initial CalUsbClkPeriod = $itor( 1000000/48 ); // ~20833.33333ps (48MHz) +initial UncUsbClkPeriod = $itor( $urandom_range(55555, 25000) ); // 55555-25000ps (18-40MHz) + +real adj_drift; +assign adj_drift = $itor(usb_clk_drift) * $itor(ref_pulse_cnt_down) / + $itor(ast_reg_pkg::NumUsbBeaconPulses[4-1:0]); + +assign drift = zero_drift ? 0.0 : adj_drift; + +assign UsbClkPeriod = (usb_osc_cal_i && init_start) ? CalUsbClkPeriod : + UncUsbClkPeriod; +assign CLK_PERIOD = (UsbClkPeriod + drift)/1000; + +// Free running oscillator +reg clk_osc; +initial clk_osc = 1'b1; + +always begin + #(CLK_PERIOD/2) clk_osc = ~clk_osc; +end + +logic en_osc; + +// HDL Clock Gate +logic en_clk, clk; + +always_latch begin + if ( !clk_osc ) en_clk = en_osc; +end + +assign clk = clk_osc && en_clk; +`else // of SYNTHESIS +// SYNTHESIS/LINTER +/////////////////////////////////////// +logic en_osc_re; +assign en_osc_re = vcore_pok_h_i && usb_en_i; + +logic clk, en_osc; +assign clk = 1'b0; +`endif // of SYNTHESIS +`else // of AST_BYPASS_CLK +// VERILATOR/FPGA +/////////////////////////////////////// +logic en_osc_re; +assign en_osc_re = vcore_pok_h_i && usb_en_i; + +// Clock Oscillator +//////////////////////////////////////// +logic clk, en_osc; + +prim_clock_gating #( + .NoFpgaGate ( 1'b1 ) +) u_clk_ckgt ( + .clk_i ( clk_usb_ext_i ), + .en_i ( en_osc ), + .test_en_i ( 1'b0 ), + .clk_o ( clk ) +); +`endif + +logic en_osc_fe; + +// Syncronize en_osc to clk FE for glitch free disable +always_ff @( negedge clk, negedge vcore_pok_h_i ) begin + if ( !vcore_pok_h_i ) begin + en_osc_fe <= 1'b0; + end else begin + en_osc_fe <= en_osc_re; + end +end + +assign en_osc = en_osc_re || en_osc_fe; // EN -> 1 || EN -> 0 + +// Clock Output Buffer +//////////////////////////////////////// +prim_clock_buf #( + .NoFpgaBuf ( 1'b1 ) +) u_buf ( + .clk_i ( clk ), + .clk_o ( usb_clk_o ) +); + + +`ifdef SYNTHESIS +/////////////////////// +// Unused Signals +/////////////////////// +logic unused_sigs; +assign unused_sigs = ^{ usb_osc_cal_i, usb_ref_pulse_i, usb_ref_val_i }; +`endif + +endmodule : usb_osc diff --git a/src/ast/rtl/vcaon_pgd.sv b/src/ast/rtl/vcaon_pgd.sv new file mode 100644 index 0000000..e325fb4 --- /dev/null +++ b/src/ast/rtl/vcaon_pgd.sv @@ -0,0 +1,57 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +//############################################################################ +// *Name: vcaon_pgd +// *Module Description: VCAON Power Good +//############################################################################ +`ifdef SYNTHESIS +`ifndef PRIM_DEFAULT_IMPL +`define PRIM_DEFAULT_IMPL prim_pkg::ImplGeneric +`endif +`endif + +module vcaon_pgd ( + output logic vcaon_pok_o +); + +// Local signal for testing hook +logic gen_supp_a; +assign gen_supp_a = 1'b1; + +`ifndef SYNTHESIS +// Behavioral Model +//////////////////////////////////////// +// The initial is needed to clear the X of the delays at the start +// Also to force a power-up effect at the bgining. +logic init_start; + +initial begin + init_start = 1'b1; #1; + init_start = 1'b0; +end + +always @( * ) begin + if ( init_start ) begin + vcaon_pok_o <= 1'b0; + end else if ( !init_start && gen_supp_a ) begin + vcaon_pok_o <= #(ast_bhv_pkg::VCAON_POK_RDLY) gen_supp_a; + end else if ( !init_start && !gen_supp_a ) begin + vcaon_pok_o <= #(ast_bhv_pkg::VCAON_POK_FDLY) gen_supp_a; + end +end +`else +// SYNTHESIS/VERILATOR/LINTER/FPGA +/////////////////////////////////////// +localparam prim_pkg::impl_e Impl = `PRIM_DEFAULT_IMPL; + +if (Impl == prim_pkg::ImplXilinx) begin : gen_xilinx + // FPGA Specific (place holder) + /////////////////////////////////////// + assign vcaon_pok_o = gen_supp_a; +end else begin : gen_generic + assign vcaon_pok_o = gen_supp_a; +end +`endif + +endmodule : vcaon_pgd diff --git a/src/ast/rtl/vcc_pgd.sv b/src/ast/rtl/vcc_pgd.sv new file mode 100644 index 0000000..f66c4b4 --- /dev/null +++ b/src/ast/rtl/vcc_pgd.sv @@ -0,0 +1,59 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +//############################################################################ +// *Name: vcc_pgd +// *Module Description: VCC Power Good +//############################################################################ +`ifdef SYNTHESIS +`ifndef PRIM_DEFAULT_IMPL +`define PRIM_DEFAULT_IMPL prim_pkg::ImplGeneric +`endif +`endif + +module vcc_pgd ( + output logic vcc_pok_o +); + +// Local signal for testing hook +logic gen_supp_a; +assign gen_supp_a = 1'b1; + +`ifndef SYNTHESIS +// Behavioral Model +//////////////////////////////////////// +// The initial is needed to clear the X of the delays at the start +// Also to force a power-up effect at the bgining. +logic init_start; + +initial begin + init_start = 1'b1; #1; + init_start = 1'b0; +end + +always (* xprop_off *) @( * ) begin + if ( init_start ) begin + vcc_pok_o <= 1'b0; + end + if ( !init_start && gen_supp_a ) begin + vcc_pok_o <= #(ast_bhv_pkg::VCC_POK_RDLY) gen_supp_a; + end + if ( !init_start && !gen_supp_a ) begin + vcc_pok_o <= #(ast_bhv_pkg::VCC_POK_FDLY) gen_supp_a; + end +end +`else +// SYNTHESIS/VERILATOR/LINTER/FPGA +/////////////////////////////////////// +localparam prim_pkg::impl_e Impl = `PRIM_DEFAULT_IMPL; + +if (Impl == prim_pkg::ImplXilinx) begin : gen_xilinx + // FPGA Specific (place holder) + /////////////////////////////////////// + assign vcc_pok_o = gen_supp_a; +end else begin : gen_generic + assign vcc_pok_o = gen_supp_a; +end +`endif + +endmodule : vcc_pgd diff --git a/src/ast/rtl/vcmain_pgd.sv b/src/ast/rtl/vcmain_pgd.sv new file mode 100644 index 0000000..cf73b5f --- /dev/null +++ b/src/ast/rtl/vcmain_pgd.sv @@ -0,0 +1,57 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +//############################################################################ +// *Name: vcmain_pgd +// *Module Description: VCMAIN Power Good +//############################################################################ +`ifdef SYNTHESIS +`ifndef PRIM_DEFAULT_IMPL +`define PRIM_DEFAULT_IMPL prim_pkg::ImplGeneric +`endif +`endif + +module vcmain_pgd ( + output logic vcmain_pok_o +); + +// Local signal for testing hook +logic gen_supp_a; +assign gen_supp_a = 1'b1; + +`ifndef SYNTHESIS +// Behavioral Model +//////////////////////////////////////// +// The initial is needed to clear the X of the delays at the start +// Also to force a power-up effect at the bgining. +logic init_start; + +initial begin + init_start = 1'b1; #1; + init_start = 1'b0; +end + +always @( * ) begin + if ( init_start ) begin + vcmain_pok_o <= 1'b0; + end else if ( !init_start && gen_supp_a ) begin + vcmain_pok_o <= #(ast_bhv_pkg::VCMAIN_POK_RDLY) gen_supp_a; + end else if ( !init_start && !gen_supp_a ) begin + vcmain_pok_o <= #(ast_bhv_pkg::VCMAIN_POK_FDLY) gen_supp_a; + end +end +`else +// SYNTHESIS/VERILATOR/LINTER/FPGA +/////////////////////////////////////// +localparam prim_pkg::impl_e Impl = `PRIM_DEFAULT_IMPL; + +if (Impl == prim_pkg::ImplXilinx) begin : gen_xilinx + // FPGA Specific (place holder) + /////////////////////////////////////// + assign vcmain_pok_o = gen_supp_a; +end else begin : gen_generic + assign vcmain_pok_o = gen_supp_a; +end +`endif + +endmodule : vcmain_pgd diff --git a/src/ast/rtl/vio_pgd.sv b/src/ast/rtl/vio_pgd.sv new file mode 100644 index 0000000..96c353f --- /dev/null +++ b/src/ast/rtl/vio_pgd.sv @@ -0,0 +1,59 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +//############################################################################ +// *Name: vio_pgd +// *Module Description: VIO Power Good +//############################################################################ +`ifdef SYNTHESIS +`ifndef PRIM_DEFAULT_IMPL +`define PRIM_DEFAULT_IMPL prim_pkg::ImplGeneric +`endif +`endif + +module vio_pgd ( + output logic vio_pok_o +); + +// Local signal for testing hook +logic gen_supp_a; +assign gen_supp_a = 1'b1; + +`ifndef SYNTHESIS +// Behavioral Model +//////////////////////////////////////// +// The initial is needed to clear the X of the delays at the start +// Also to force a power-up effect at the bgining. +logic init_start; + +initial begin + init_start = 1'b1; #1; + init_start = 1'b0; +end + +always (* xprop_off *) @( * ) begin + if ( init_start ) begin + vio_pok_o <= 1'b0; + end + if ( !init_start && gen_supp_a ) begin + vio_pok_o <= #(ast_bhv_pkg::VIO_POK_RDLY) gen_supp_a; + end + if ( !init_start && !gen_supp_a ) begin + vio_pok_o <= #(ast_bhv_pkg::VIO_POK_FDLY) gen_supp_a; + end +end +`else +// SYNTHESIS/VERILATOR/LINTER/FPGA +////////////////////////////////////// +localparam prim_pkg::impl_e Impl = `PRIM_DEFAULT_IMPL; + +if (Impl == prim_pkg::ImplXilinx) begin : gen_xilinx + // FPGA Specific (place holder) + /////////////////////////////////////// + assign vio_pok_o = gen_supp_a; +end else begin : gen_generic + assign vio_pok_o = gen_supp_a; +end +`endif + +endmodule : vio_pgd diff --git a/src/axi2tlul/config/compile.yml b/src/axi2tlul/config/compile.yml new file mode 100644 index 0000000..37e5868 --- /dev/null +++ b/src/axi2tlul/config/compile.yml @@ -0,0 +1,29 @@ +--- +provides: [axi2tlul] +schema_version: 2.4.0 +requires: + - axi_pkg + - axi_sub + - tlul_pkg + - caliptra_prim_secded +targets: + rtl: + directories: [$COMPILE_ROOT/rtl] + files: + - $COMPILE_ROOT/rtl/axi2tlul_cmd_intg_gen.sv + - $COMPILE_ROOT/rtl/sub2tlul.sv + - $COMPILE_ROOT/rtl/axi2tlul.sv + tops: [axi2tlul] +--- +provides: [axi2tlul_tb] +schema_version: 2.4.0 +requires: + - axi2tlul +targets: + tb: + directories: [$COMPILE_ROOT/tb] + files: + - $COMPILE_ROOT/tb/memory_model.sv + - $COMPILE_ROOT/tb/axi2tlul_tb.sv + tops: [axi2tlul_tb] + diff --git a/src/axi2tlul/rtl/axi2tlul.sv b/src/axi2tlul/rtl/axi2tlul.sv new file mode 100644 index 0000000..583fe39 --- /dev/null +++ b/src/axi2tlul/rtl/axi2tlul.sv @@ -0,0 +1,133 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS; +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND; either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// + +// ------------------------------------------------------------- +// AXI TLUL Gasket +// ------------------------------------------------------------- +// Description: +// Shim to convert AXI protocol writes into TLUL +// +// Limitations: +// - When multiple ID tracking is enabled; write responses are returned in the +// same order they are received; regardless of ID. +// +// ------------------------------------------------------------- + +module axi2tlul + import axi_pkg::*; + #( + parameter AW = 32, // Address Width + parameter DW = 32, // Data Width + BC = DW/8, // Byte Count + BW = $clog2(BC), // Byte count Width + parameter UW = 32, // User Width + parameter IW = 1, // ID Width + ID_NUM = 1 << IW, // Don't override + + parameter EX_EN = 0, // Enable exclusive access tracking w/ AxLOCK + parameter C_LAT = 0 // Component latency in clock cycles from (dv&&!hld) -> rdata + // Must be const per component + // For registers; typically 0 + // For SRAM; 1 or more + ) ( + input clk, + input rst_n, + + // AXI INF + axi_if.w_sub s_axi_w_if, + axi_if.r_sub s_axi_r_if, + + // TLUL INF + output tlul_pkg::tl_h2d_t tl_o, + input tlul_pkg::tl_d2h_t tl_i + ); + + // Subordinate INF + logic dv; + logic [AW-1:0] addr; + logic write; + logic [UW-1:0] user; + logic [IW-1:0] id; + logic [DW-1:0] wdata; // Requires: Component dwidth == AXI dwidth + logic [BC-1:0] wstrb; // Requires: Component dwidth == AXI dwidth + logic [2:0] size; + logic [DW-1:0] rdata; // Requires: Component dwidth == AXI dwidth + logic last; // Asserted with final 'dv' of a burst + logic hld; + logic rd_err; + logic wr_err; + + axi_sub #( + .AW (AW), + .DW (DW), + .UW (UW), + .IW (IW), + .EX_EN (EX_EN) + + ) i_axi_sub ( + .clk (clk ), + .rst_n (rst_n ), + + // AXI INF + .s_axi_w_if (s_axi_w_if ), + .s_axi_r_if (s_axi_r_if ), + + // Subordinate INF + .dv (dv ), + .addr (addr ), + .write (write ), + .user (user ), + .id (id ), + .wdata (wdata ), + .wstrb (wstrb ), + .size (size ), + .rdata (rdata ), + .last (last ), + .hld (hld ), + .rd_err (rd_err ), + .wr_err (wr_err ) + ); + + sub2tlul #( + .AW (AW), + .DW (DW), + .UW (UW), + .IW (IW), + .EX_EN (EX_EN) + ) i_sub2tlul ( + .clk (clk ), + .rst_n (rst_n ), + + // Subordinate INF + .dv (dv ), + .addr (addr ), + .write (write ), + .user (user ), + .id (id ), + .wdata (wdata ), + .wstrb (wstrb ), + .size (size ), + .rdata (rdata ), + .last (last ), + .hld (hld ), + .rd_err (rd_err ), + .wr_err (wr_err ), + + // TLUL INF + .tl_o (tl_o ), + .tl_i (tl_i ) + ); + +endmodule \ No newline at end of file diff --git a/src/axi2tlul/rtl/axi2tlul_cmd_intg_gen.sv b/src/axi2tlul/rtl/axi2tlul_cmd_intg_gen.sv new file mode 100644 index 0000000..cdee92c --- /dev/null +++ b/src/axi2tlul/rtl/axi2tlul_cmd_intg_gen.sv @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// + +module axi2tlul_cmd_intg_gen + import axi_pkg::*; + import caliptra_prim_pkg::*; + import tlul_pkg::*; + #( + parameter bit EnableDataIntgGen = 1'b1 + ) ( + input caliptra_prim_mubi_pkg::mubi4_t instr_type_i, + input [AXI_AW-1:0] addr_i, + input tl_a_op_e opcode_i, + input [tlul_pkg::TL_DBW-1:0] mask_i, + input [tlul_pkg::TL_DW-1:0] data_i, + + output [H2DCmdIntgWidth-1:0] cmd_intg, + output [DataIntgWidth-1:0] data_intg + ); + + + + logic [H2DCmdMaxWidth-1:0] unused_cmd_payload; + tl_h2d_cmd_intg_t cmd; + + assign cmd = { instr_type_i, + addr_i, + opcode_i, + mask_i }; + + caliptra_prim_secded_inv_64_57_enc u_cmd_gen ( + .data_i(H2DCmdMaxWidth'(cmd)), + .data_o({cmd_intg, unused_cmd_payload}) + ); + + logic [tlul_pkg::TL_DW-1:0] data_final; + + if (EnableDataIntgGen) begin : gen_data_intg + assign data_final = data_i; + + logic [DataMaxWidth-1:0] unused_data; + caliptra_prim_secded_inv_39_32_enc u_data_gen ( + .data_i(DataMaxWidth'(data_final)), + .data_o({data_intg, unused_data}) + ); + end else begin : gen_passthrough_data_intg + assign data_final = data_i; + assign data_intg = '0; + end + + //`CALIPTRA_ASSERT_INIT(PayMaxWidthCheck_A, $bits(tl_h2d_cmd_intg_t) <= H2DCmdMaxWidth) + +endmodule : axi2tlul_cmd_intg_gen \ No newline at end of file diff --git a/src/axi2tlul/rtl/sub2tlul.sv b/src/axi2tlul/rtl/sub2tlul.sv new file mode 100644 index 0000000..392f45a --- /dev/null +++ b/src/axi2tlul/rtl/sub2tlul.sv @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// + +// ------------------------------------------------------------- +// AXI TLUL Write Shim +// ------------------------------------------------------------- +// Description: +// Shim to convert AXI protocol writes into TLUL +// +// Limitations: +// - When multiple ID tracking is enabled, write responses are returned in the +// same order they are received, regardless of ID. +// +// ------------------------------------------------------------- + +module sub2tlul + import axi_pkg::*; + import tlul_pkg::*; + #( + parameter AW = 32, // Address Width + parameter DW = 32, // Data Width + BC = DW/8, // Byte Count + BW = $clog2(BC), // Byte count Width + parameter UW = 32, // User Width + parameter IW = 1, // ID Width + ID_NUM = 1 << IW, // Don't override + + parameter EX_EN = 0, // Enable exclusive access tracking w/ AxLOCK + parameter C_LAT = 0 // Component latency in clock cycles from (dv&&!hld) -> rdata + // Must be const per component + // For registers, typically 0 + // For SRAM, 1 or more + ) ( + input clk, + input rst_n, + + //COMPONENT INF + input logic dv, + input logic [AW-1:0] addr, // Byte address + input logic write, + input logic [UW-1:0] user, + input logic [IW-1:0] id, + input logic [DW-1:0] wdata, // Requires: Component dwidth == AXI dwidth + input logic [BC-1:0] wstrb, // Requires: Component dwidth == AXI dwidth + input logic [2:0] size, + output logic [DW-1:0] rdata, // Requires: Component dwidth == AXI dwidth + input logic last, // Asserted with final 'dv' of a burst + output logic hld, + output logic rd_err, + output logic wr_err, + + //TLUL INF + output tlul_pkg::tl_h2d_t tl_o, + input tlul_pkg::tl_d2h_t tl_i + ); + + // Setting instruction type to False as all accesses to OTP are data accesses + localparam caliptra_prim_mubi_pkg::mubi4_t instr_type = caliptra_prim_mubi_pkg::MuBi4False; + + // AXI SUB TO TL-UL REQUEST + logic pending_txn; + tl_a_op_e opcode; + logic [3:0] mask_local; + + typedef enum logic [1:0] { + no_txn = 2'b00, + valid_get_txn = 2'b01, + valid_put_txn = 2'b10 + } txn_state_e; + + txn_state_e cur_txn; + + always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + cur_txn <= no_txn; + end + else if (opcode == Get && tl_o.a_valid) begin + cur_txn <= valid_get_txn; + end + else if (opcode == PutFullData || opcode == PutPartialData && tl_o.a_valid) begin + cur_txn <= valid_put_txn; + end + else if (cur_txn == valid_get_txn && tl_i.d_opcode == AccessAckData && tl_i.d_valid) begin + cur_txn <= no_txn; + end + else if (cur_txn == valid_put_txn && tl_i.d_opcode == AccessAck && tl_i.d_valid) begin + cur_txn <= no_txn; + end + end + + always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + pending_txn <= 0; + end + else if (dv && tl_i.a_ready && ~tl_i.d_valid) begin + pending_txn <= 1; + end + else if (dv && tl_i.d_valid) begin + pending_txn <= 0; + end + end + + assign opcode = !write ? Get : ((wstrb == '1) ? PutFullData : PutPartialData); + assign mask_local = !write ? user[21:18] : wstrb; + + assign tl_o.a_address = addr; + assign tl_o.a_valid = dv & ~pending_txn; + assign tl_o.a_opcode = opcode; + assign tl_o.a_source = id; + assign tl_o.a_mask = mask_local; + assign tl_o.a_data = wdata; + assign tl_o.a_size = size; + + // TL-UL TO AXI SUB RESPONSE + assign rdata = (dv && tl_i.d_valid && (tl_i.d_source == id)) ? tl_i.d_data : 0; + assign hld = dv & tl_o.a_valid & (~tl_i.a_ready | ~tl_i.d_valid) | + ((cur_txn == valid_get_txn) & ((tl_i.d_opcode != AccessAckData) | ((tl_i.d_opcode == AccessAckData) & ~tl_i.d_valid)) ); + assign tl_o.d_ready = tl_i.d_valid; + assign rd_err = ~write & tl_i.d_error & tl_i.d_valid; + assign wr_err = write & tl_i.d_error & tl_i.d_valid; + + //TLUL unused signals: a_param, d_param, d_sink, d_size (dropped) + assign tl_o.a_param = 3'h0; + + logic [H2DCmdIntgWidth-1:0] cmd_intg; + logic [DataIntgWidth-1:0] data_intg; + + axi2tlul_cmd_intg_gen #( + .EnableDataIntgGen (1) + ) u_axi2tlul_cmd_intg_gen ( + .instr_type_i (instr_type), + .addr_i (addr), + .opcode_i (opcode), + .mask_i (mask_local), + .data_i (wdata), + .cmd_intg (cmd_intg), + .data_intg (data_intg) + ); + + assign tl_o.a_user = { instr_type, + cmd_intg, + data_intg }; + +endmodule diff --git a/src/caliptra_ss_lc_ctrl/config/compile.yml b/src/caliptra_ss_lc_ctrl/config/compile.yml new file mode 100644 index 0000000..3e96ae9 --- /dev/null +++ b/src/caliptra_ss_lc_ctrl/config/compile.yml @@ -0,0 +1,86 @@ +--- +provides: [caliptra_ss_lc_ctrl_pkg] +schema_version: 2.4.0 +requires: + - caliptra_prim_pkg +targets: + rtl: + directories: [$COMPILE_ROOT/rtl] + files: + - $COMPILE_ROOT/rtl/caliptra_ss_lc_ctrl_reg_pkg.sv + - $COMPILE_ROOT/rtl/caliptra_ss_lc_ctrl_state_pkg.sv + - $COMPILE_ROOT/rtl/caliptra_ss_lc_ctrl_pkg.sv + - $COMPILE_ROOT/rtl/jtag_pkg.sv + - $COMPILE_ROOT/rtl/top_pkg.sv + - $COMPILE_ROOT/rtl/alert_handler_reg_pkg.sv + tb: + directories: [$COMPILE_ROOT/rtl] + files: + - $COMPILE_ROOT/rtl/caliptra_ss_lc_ctrl_reg_pkg.sv + - $COMPILE_ROOT/rtl/caliptra_ss_lc_ctrl_state_pkg.sv + - $COMPILE_ROOT/rtl/caliptra_ss_lc_ctrl_pkg.sv + - $COMPILE_ROOT/rtl/jtag_pkg.sv + - $COMPILE_ROOT/rtl/top_pkg.sv + - $COMPILE_ROOT/rtl/alert_handler_reg_pkg.sv +--- +provides: [lc_kmac_pkg] +schema_version: 2.4.0 +requires: + - caliptra_prim_pkg + - caliptra_ss_lc_ctrl_pkg +targets: + rtl: + directories: [$COMPILE_ROOT/rtl] + files: + - $COMPILE_ROOT/rtl/caliptra_ss_lc_ctrl_keymgr_pkg.sv + - $COMPILE_ROOT/rtl/kmac_reg_pkg.sv + - $COMPILE_ROOT/rtl/sha3_pkg.sv + - $COMPILE_ROOT/rtl/kmac_pkg.sv + tb: + directories: [$COMPILE_ROOT/rtl] + files: + - $COMPILE_ROOT/rtl/caliptra_ss_lc_ctrl_keymgr_pkg.sv + - $COMPILE_ROOT/rtl/kmac_reg_pkg.sv + - $COMPILE_ROOT/rtl/sha3_pkg.sv + - $COMPILE_ROOT/rtl/kmac_pkg.sv +--- +provides: [caliptra_ss_lc_ctrl] +schema_version: 2.4.0 +requires: + - caliptra_ss_lc_ctrl_pkg + - lc_kmac_pkg + - axi_pkg + - axi2tlul + - tlul_pkg + - pwrmgr_pkg + - fuse_ctrl_pkg + - ast_pkg + - edn_pkg + - tlul + - dmi_jtag +targets: + rtl: + directories: [$COMPILE_ROOT/rtl] + files: + - $COMPILE_ROOT/rtl/keccak_2share.sv + - $COMPILE_ROOT/rtl/keccak_round.sv + - $COMPILE_ROOT/rtl/sha3pad.sv + - $COMPILE_ROOT/rtl/sha3.sv + - $COMPILE_ROOT/rtl/kmac_app.sv + - $COMPILE_ROOT/rtl/kmac_core.sv + - $COMPILE_ROOT/rtl/kmac_entropy.sv + - $COMPILE_ROOT/rtl/kmac_errchk.sv + - $COMPILE_ROOT/rtl/kmac_msgfifo.sv + - $COMPILE_ROOT/rtl/kmac_reduced.sv + - $COMPILE_ROOT/rtl/kmac_reg_top.sv + - $COMPILE_ROOT/rtl/kmac_staterd.sv + - $COMPILE_ROOT/rtl/kmac.sv + - $COMPILE_ROOT/rtl/caliptra_ss_lc_ctrl_dmi_reg_top.sv + - $COMPILE_ROOT/rtl/caliptra_ss_lc_ctrl_fsm.sv + - $COMPILE_ROOT/rtl/caliptra_ss_lc_ctrl_kmac_if.sv + - $COMPILE_ROOT/rtl/caliptra_ss_lc_ctrl_regs_reg_top.sv + - $COMPILE_ROOT/rtl/caliptra_ss_lc_ctrl_signal_decode.sv + - $COMPILE_ROOT/rtl/caliptra_ss_lc_ctrl_state_decode.sv + - $COMPILE_ROOT/rtl/caliptra_ss_lc_ctrl_state_transition.sv + - $COMPILE_ROOT/rtl/caliptra_ss_lc_ctrl.sv + tops: [caliptra_ss_lc_ctrl] diff --git a/src/caliptra_ss_lc_ctrl/config/lc_ctrl_pkg.vf b/src/caliptra_ss_lc_ctrl/config/lc_ctrl_pkg.vf new file mode 100644 index 0000000..ae8daec --- /dev/null +++ b/src/caliptra_ss_lc_ctrl/config/lc_ctrl_pkg.vf @@ -0,0 +1,13 @@ ++incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl ++incdir+${CALIPTRA_ROOT}/src/caliptra_ss_lc_ctrl/rtl +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_util_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cipher_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_ss_lc_ctrl/rtl/caliptra_ss_lc_ctrl_reg_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_ss_lc_ctrl/rtl/caliptra_ss_lc_ctrl_state_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_ss_lc_ctrl/rtl/caliptra_ss_lc_ctrl_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_ss_lc_ctrl/rtl/caliptra_ss_lc_ctrl_pkg.sv \ No newline at end of file diff --git a/src/caliptra_ss_lc_ctrl/rtl/alert_handler_reg_pkg.sv b/src/caliptra_ss_lc_ctrl/rtl/alert_handler_reg_pkg.sv new file mode 100644 index 0000000..9d8fb70 --- /dev/null +++ b/src/caliptra_ss_lc_ctrl/rtl/alert_handler_reg_pkg.sv @@ -0,0 +1,1781 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Package auto-generated by `reggen` containing data structure + +package alert_handler_reg_pkg; + + // Param list + parameter int NAlerts = 65; + parameter int NLpg = 24; + parameter int NLpgWidth = 5; + parameter logic [NAlerts-1:0][NLpgWidth-1:0] LpgMap = { + 5'd17, + 5'd17, + 5'd17, + 5'd17, + 5'd17, + 5'd17, + 5'd19, + 5'd19, + 5'd19, + 5'd19, + 5'd19, + 5'd19, + 5'd19, + 5'd19, + 5'd19, + 5'd19, + 5'd23, + 5'd23, + 5'd22, + 5'd22, + 5'd21, + 5'd20, + 5'd20, + 5'd19, + 5'd18, + 5'd17, + 5'd17, + 5'd17, + 5'd17, + 5'd17, + 5'd16, + 5'd12, + 5'd12, + 5'd14, + 5'd11, + 5'd13, + 5'd13, + 5'd12, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd10, + 5'd9, + 5'd8, + 5'd7, + 5'd6, + 5'd6, + 5'd6, + 5'd6, + 5'd6, + 5'd6, + 5'd6, + 5'd6, + 5'd5, + 5'd0, + 5'd4, + 5'd3, + 5'd2, + 5'd1, + 5'd0, + 5'd0, + 5'd0, + 5'd0, + 5'd0 +}; + parameter int EscCntDw = 32; + parameter int AccuCntDw = 16; + parameter logic [NAlerts-1:0] AsyncOn = { + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1 +}; + parameter int N_CLASSES = 4; + parameter int N_ESC_SEV = 4; + parameter int N_PHASES = 4; + parameter int N_LOC_ALERT = 7; + parameter int PING_CNT_DW = 16; + parameter int PHASE_DW = 2; + parameter int CLASS_DW = 2; + parameter int LOCAL_ALERT_ID_ALERT_PINGFAIL = 0; + parameter int LOCAL_ALERT_ID_ESC_PINGFAIL = 1; + parameter int LOCAL_ALERT_ID_ALERT_INTEGFAIL = 2; + parameter int LOCAL_ALERT_ID_ESC_INTEGFAIL = 3; + parameter int LOCAL_ALERT_ID_BUS_INTEGFAIL = 4; + parameter int LOCAL_ALERT_ID_SHADOW_REG_UPDATE_ERROR = 5; + parameter int LOCAL_ALERT_ID_SHADOW_REG_STORAGE_ERROR = 6; + parameter int LOCAL_ALERT_ID_LAST = 6; + + // Address widths within the block + parameter int BlockAw = 11; + + //////////////////////////// + // Typedefs for registers // + //////////////////////////// + + typedef struct packed { + struct packed { + logic q; + } classd; + struct packed { + logic q; + } classc; + struct packed { + logic q; + } classb; + struct packed { + logic q; + } classa; + } alert_handler_reg2hw_intr_state_reg_t; + + typedef struct packed { + struct packed { + logic q; + } classd; + struct packed { + logic q; + } classc; + struct packed { + logic q; + } classb; + struct packed { + logic q; + } classa; + } alert_handler_reg2hw_intr_enable_reg_t; + + typedef struct packed { + struct packed { + logic q; + logic qe; + } classd; + struct packed { + logic q; + logic qe; + } classc; + struct packed { + logic q; + logic qe; + } classb; + struct packed { + logic q; + logic qe; + } classa; + } alert_handler_reg2hw_intr_test_reg_t; + + typedef struct packed { + logic [15:0] q; + } alert_handler_reg2hw_ping_timeout_cyc_shadowed_reg_t; + + typedef struct packed { + logic q; + } alert_handler_reg2hw_ping_timer_en_shadowed_reg_t; + + typedef struct packed { + logic q; + } alert_handler_reg2hw_alert_regwen_mreg_t; + + typedef struct packed { + logic q; + } alert_handler_reg2hw_alert_en_shadowed_mreg_t; + + typedef struct packed { + logic [1:0] q; + } alert_handler_reg2hw_alert_class_shadowed_mreg_t; + + typedef struct packed { + logic q; + } alert_handler_reg2hw_alert_cause_mreg_t; + + typedef struct packed { + logic q; + } alert_handler_reg2hw_loc_alert_en_shadowed_mreg_t; + + typedef struct packed { + logic [1:0] q; + } alert_handler_reg2hw_loc_alert_class_shadowed_mreg_t; + + typedef struct packed { + logic q; + } alert_handler_reg2hw_loc_alert_cause_mreg_t; + + typedef struct packed { + struct packed { + logic [1:0] q; + } map_e3; + struct packed { + logic [1:0] q; + } map_e2; + struct packed { + logic [1:0] q; + } map_e1; + struct packed { + logic [1:0] q; + } map_e0; + struct packed { + logic q; + } en_e3; + struct packed { + logic q; + } en_e2; + struct packed { + logic q; + } en_e1; + struct packed { + logic q; + } en_e0; + struct packed { + logic q; + } lock; + struct packed { + logic q; + } en; + } alert_handler_reg2hw_classa_ctrl_shadowed_reg_t; + + typedef struct packed { + logic q; + logic qe; + } alert_handler_reg2hw_classa_clr_shadowed_reg_t; + + typedef struct packed { + logic [15:0] q; + } alert_handler_reg2hw_classa_accum_thresh_shadowed_reg_t; + + typedef struct packed { + logic [31:0] q; + } alert_handler_reg2hw_classa_timeout_cyc_shadowed_reg_t; + + typedef struct packed { + logic [1:0] q; + } alert_handler_reg2hw_classa_crashdump_trigger_shadowed_reg_t; + + typedef struct packed { + logic [31:0] q; + } alert_handler_reg2hw_classa_phase0_cyc_shadowed_reg_t; + + typedef struct packed { + logic [31:0] q; + } alert_handler_reg2hw_classa_phase1_cyc_shadowed_reg_t; + + typedef struct packed { + logic [31:0] q; + } alert_handler_reg2hw_classa_phase2_cyc_shadowed_reg_t; + + typedef struct packed { + logic [31:0] q; + } alert_handler_reg2hw_classa_phase3_cyc_shadowed_reg_t; + + typedef struct packed { + struct packed { + logic [1:0] q; + } map_e3; + struct packed { + logic [1:0] q; + } map_e2; + struct packed { + logic [1:0] q; + } map_e1; + struct packed { + logic [1:0] q; + } map_e0; + struct packed { + logic q; + } en_e3; + struct packed { + logic q; + } en_e2; + struct packed { + logic q; + } en_e1; + struct packed { + logic q; + } en_e0; + struct packed { + logic q; + } lock; + struct packed { + logic q; + } en; + } alert_handler_reg2hw_classb_ctrl_shadowed_reg_t; + + typedef struct packed { + logic q; + logic qe; + } alert_handler_reg2hw_classb_clr_shadowed_reg_t; + + typedef struct packed { + logic [15:0] q; + } alert_handler_reg2hw_classb_accum_thresh_shadowed_reg_t; + + typedef struct packed { + logic [31:0] q; + } alert_handler_reg2hw_classb_timeout_cyc_shadowed_reg_t; + + typedef struct packed { + logic [1:0] q; + } alert_handler_reg2hw_classb_crashdump_trigger_shadowed_reg_t; + + typedef struct packed { + logic [31:0] q; + } alert_handler_reg2hw_classb_phase0_cyc_shadowed_reg_t; + + typedef struct packed { + logic [31:0] q; + } alert_handler_reg2hw_classb_phase1_cyc_shadowed_reg_t; + + typedef struct packed { + logic [31:0] q; + } alert_handler_reg2hw_classb_phase2_cyc_shadowed_reg_t; + + typedef struct packed { + logic [31:0] q; + } alert_handler_reg2hw_classb_phase3_cyc_shadowed_reg_t; + + typedef struct packed { + struct packed { + logic [1:0] q; + } map_e3; + struct packed { + logic [1:0] q; + } map_e2; + struct packed { + logic [1:0] q; + } map_e1; + struct packed { + logic [1:0] q; + } map_e0; + struct packed { + logic q; + } en_e3; + struct packed { + logic q; + } en_e2; + struct packed { + logic q; + } en_e1; + struct packed { + logic q; + } en_e0; + struct packed { + logic q; + } lock; + struct packed { + logic q; + } en; + } alert_handler_reg2hw_classc_ctrl_shadowed_reg_t; + + typedef struct packed { + logic q; + logic qe; + } alert_handler_reg2hw_classc_clr_shadowed_reg_t; + + typedef struct packed { + logic [15:0] q; + } alert_handler_reg2hw_classc_accum_thresh_shadowed_reg_t; + + typedef struct packed { + logic [31:0] q; + } alert_handler_reg2hw_classc_timeout_cyc_shadowed_reg_t; + + typedef struct packed { + logic [1:0] q; + } alert_handler_reg2hw_classc_crashdump_trigger_shadowed_reg_t; + + typedef struct packed { + logic [31:0] q; + } alert_handler_reg2hw_classc_phase0_cyc_shadowed_reg_t; + + typedef struct packed { + logic [31:0] q; + } alert_handler_reg2hw_classc_phase1_cyc_shadowed_reg_t; + + typedef struct packed { + logic [31:0] q; + } alert_handler_reg2hw_classc_phase2_cyc_shadowed_reg_t; + + typedef struct packed { + logic [31:0] q; + } alert_handler_reg2hw_classc_phase3_cyc_shadowed_reg_t; + + typedef struct packed { + struct packed { + logic [1:0] q; + } map_e3; + struct packed { + logic [1:0] q; + } map_e2; + struct packed { + logic [1:0] q; + } map_e1; + struct packed { + logic [1:0] q; + } map_e0; + struct packed { + logic q; + } en_e3; + struct packed { + logic q; + } en_e2; + struct packed { + logic q; + } en_e1; + struct packed { + logic q; + } en_e0; + struct packed { + logic q; + } lock; + struct packed { + logic q; + } en; + } alert_handler_reg2hw_classd_ctrl_shadowed_reg_t; + + typedef struct packed { + logic q; + logic qe; + } alert_handler_reg2hw_classd_clr_shadowed_reg_t; + + typedef struct packed { + logic [15:0] q; + } alert_handler_reg2hw_classd_accum_thresh_shadowed_reg_t; + + typedef struct packed { + logic [31:0] q; + } alert_handler_reg2hw_classd_timeout_cyc_shadowed_reg_t; + + typedef struct packed { + logic [1:0] q; + } alert_handler_reg2hw_classd_crashdump_trigger_shadowed_reg_t; + + typedef struct packed { + logic [31:0] q; + } alert_handler_reg2hw_classd_phase0_cyc_shadowed_reg_t; + + typedef struct packed { + logic [31:0] q; + } alert_handler_reg2hw_classd_phase1_cyc_shadowed_reg_t; + + typedef struct packed { + logic [31:0] q; + } alert_handler_reg2hw_classd_phase2_cyc_shadowed_reg_t; + + typedef struct packed { + logic [31:0] q; + } alert_handler_reg2hw_classd_phase3_cyc_shadowed_reg_t; + + typedef struct packed { + struct packed { + logic d; + logic de; + } classa; + struct packed { + logic d; + logic de; + } classb; + struct packed { + logic d; + logic de; + } classc; + struct packed { + logic d; + logic de; + } classd; + } alert_handler_hw2reg_intr_state_reg_t; + + typedef struct packed { + logic d; + logic de; + } alert_handler_hw2reg_alert_cause_mreg_t; + + typedef struct packed { + logic d; + logic de; + } alert_handler_hw2reg_loc_alert_cause_mreg_t; + + typedef struct packed { + logic d; + logic de; + } alert_handler_hw2reg_classa_clr_regwen_reg_t; + + typedef struct packed { + logic [15:0] d; + } alert_handler_hw2reg_classa_accum_cnt_reg_t; + + typedef struct packed { + logic [31:0] d; + } alert_handler_hw2reg_classa_esc_cnt_reg_t; + + typedef struct packed { + logic [2:0] d; + } alert_handler_hw2reg_classa_state_reg_t; + + typedef struct packed { + logic d; + logic de; + } alert_handler_hw2reg_classb_clr_regwen_reg_t; + + typedef struct packed { + logic [15:0] d; + } alert_handler_hw2reg_classb_accum_cnt_reg_t; + + typedef struct packed { + logic [31:0] d; + } alert_handler_hw2reg_classb_esc_cnt_reg_t; + + typedef struct packed { + logic [2:0] d; + } alert_handler_hw2reg_classb_state_reg_t; + + typedef struct packed { + logic d; + logic de; + } alert_handler_hw2reg_classc_clr_regwen_reg_t; + + typedef struct packed { + logic [15:0] d; + } alert_handler_hw2reg_classc_accum_cnt_reg_t; + + typedef struct packed { + logic [31:0] d; + } alert_handler_hw2reg_classc_esc_cnt_reg_t; + + typedef struct packed { + logic [2:0] d; + } alert_handler_hw2reg_classc_state_reg_t; + + typedef struct packed { + logic d; + logic de; + } alert_handler_hw2reg_classd_clr_regwen_reg_t; + + typedef struct packed { + logic [15:0] d; + } alert_handler_hw2reg_classd_accum_cnt_reg_t; + + typedef struct packed { + logic [31:0] d; + } alert_handler_hw2reg_classd_esc_cnt_reg_t; + + typedef struct packed { + logic [2:0] d; + } alert_handler_hw2reg_classd_state_reg_t; + + // Register -> HW type + typedef struct packed { + alert_handler_reg2hw_intr_state_reg_t intr_state; // [1161:1158] + alert_handler_reg2hw_intr_enable_reg_t intr_enable; // [1157:1154] + alert_handler_reg2hw_intr_test_reg_t intr_test; // [1153:1146] + alert_handler_reg2hw_ping_timeout_cyc_shadowed_reg_t ping_timeout_cyc_shadowed; // [1145:1130] + alert_handler_reg2hw_ping_timer_en_shadowed_reg_t ping_timer_en_shadowed; // [1129:1129] + alert_handler_reg2hw_alert_regwen_mreg_t [64:0] alert_regwen; // [1128:1064] + alert_handler_reg2hw_alert_en_shadowed_mreg_t [64:0] alert_en_shadowed; // [1063:999] + alert_handler_reg2hw_alert_class_shadowed_mreg_t [64:0] alert_class_shadowed; // [998:869] + alert_handler_reg2hw_alert_cause_mreg_t [64:0] alert_cause; // [868:804] + alert_handler_reg2hw_loc_alert_en_shadowed_mreg_t [6:0] loc_alert_en_shadowed; // [803:797] + alert_handler_reg2hw_loc_alert_class_shadowed_mreg_t [6:0] + loc_alert_class_shadowed; // [796:783] + alert_handler_reg2hw_loc_alert_cause_mreg_t [6:0] loc_alert_cause; // [782:776] + alert_handler_reg2hw_classa_ctrl_shadowed_reg_t classa_ctrl_shadowed; // [775:762] + alert_handler_reg2hw_classa_clr_shadowed_reg_t classa_clr_shadowed; // [761:760] + alert_handler_reg2hw_classa_accum_thresh_shadowed_reg_t + classa_accum_thresh_shadowed; // [759:744] + alert_handler_reg2hw_classa_timeout_cyc_shadowed_reg_t classa_timeout_cyc_shadowed; // [743:712] + alert_handler_reg2hw_classa_crashdump_trigger_shadowed_reg_t + classa_crashdump_trigger_shadowed; // [711:710] + alert_handler_reg2hw_classa_phase0_cyc_shadowed_reg_t classa_phase0_cyc_shadowed; // [709:678] + alert_handler_reg2hw_classa_phase1_cyc_shadowed_reg_t classa_phase1_cyc_shadowed; // [677:646] + alert_handler_reg2hw_classa_phase2_cyc_shadowed_reg_t classa_phase2_cyc_shadowed; // [645:614] + alert_handler_reg2hw_classa_phase3_cyc_shadowed_reg_t classa_phase3_cyc_shadowed; // [613:582] + alert_handler_reg2hw_classb_ctrl_shadowed_reg_t classb_ctrl_shadowed; // [581:568] + alert_handler_reg2hw_classb_clr_shadowed_reg_t classb_clr_shadowed; // [567:566] + alert_handler_reg2hw_classb_accum_thresh_shadowed_reg_t + classb_accum_thresh_shadowed; // [565:550] + alert_handler_reg2hw_classb_timeout_cyc_shadowed_reg_t classb_timeout_cyc_shadowed; // [549:518] + alert_handler_reg2hw_classb_crashdump_trigger_shadowed_reg_t + classb_crashdump_trigger_shadowed; // [517:516] + alert_handler_reg2hw_classb_phase0_cyc_shadowed_reg_t classb_phase0_cyc_shadowed; // [515:484] + alert_handler_reg2hw_classb_phase1_cyc_shadowed_reg_t classb_phase1_cyc_shadowed; // [483:452] + alert_handler_reg2hw_classb_phase2_cyc_shadowed_reg_t classb_phase2_cyc_shadowed; // [451:420] + alert_handler_reg2hw_classb_phase3_cyc_shadowed_reg_t classb_phase3_cyc_shadowed; // [419:388] + alert_handler_reg2hw_classc_ctrl_shadowed_reg_t classc_ctrl_shadowed; // [387:374] + alert_handler_reg2hw_classc_clr_shadowed_reg_t classc_clr_shadowed; // [373:372] + alert_handler_reg2hw_classc_accum_thresh_shadowed_reg_t + classc_accum_thresh_shadowed; // [371:356] + alert_handler_reg2hw_classc_timeout_cyc_shadowed_reg_t classc_timeout_cyc_shadowed; // [355:324] + alert_handler_reg2hw_classc_crashdump_trigger_shadowed_reg_t + classc_crashdump_trigger_shadowed; // [323:322] + alert_handler_reg2hw_classc_phase0_cyc_shadowed_reg_t classc_phase0_cyc_shadowed; // [321:290] + alert_handler_reg2hw_classc_phase1_cyc_shadowed_reg_t classc_phase1_cyc_shadowed; // [289:258] + alert_handler_reg2hw_classc_phase2_cyc_shadowed_reg_t classc_phase2_cyc_shadowed; // [257:226] + alert_handler_reg2hw_classc_phase3_cyc_shadowed_reg_t classc_phase3_cyc_shadowed; // [225:194] + alert_handler_reg2hw_classd_ctrl_shadowed_reg_t classd_ctrl_shadowed; // [193:180] + alert_handler_reg2hw_classd_clr_shadowed_reg_t classd_clr_shadowed; // [179:178] + alert_handler_reg2hw_classd_accum_thresh_shadowed_reg_t + classd_accum_thresh_shadowed; // [177:162] + alert_handler_reg2hw_classd_timeout_cyc_shadowed_reg_t classd_timeout_cyc_shadowed; // [161:130] + alert_handler_reg2hw_classd_crashdump_trigger_shadowed_reg_t + classd_crashdump_trigger_shadowed; // [129:128] + alert_handler_reg2hw_classd_phase0_cyc_shadowed_reg_t classd_phase0_cyc_shadowed; // [127:96] + alert_handler_reg2hw_classd_phase1_cyc_shadowed_reg_t classd_phase1_cyc_shadowed; // [95:64] + alert_handler_reg2hw_classd_phase2_cyc_shadowed_reg_t classd_phase2_cyc_shadowed; // [63:32] + alert_handler_reg2hw_classd_phase3_cyc_shadowed_reg_t classd_phase3_cyc_shadowed; // [31:0] + } alert_handler_reg2hw_t; + + // HW -> register type + typedef struct packed { + alert_handler_hw2reg_intr_state_reg_t intr_state; // [363:356] + alert_handler_hw2reg_alert_cause_mreg_t [64:0] alert_cause; // [355:226] + alert_handler_hw2reg_loc_alert_cause_mreg_t [6:0] loc_alert_cause; // [225:212] + alert_handler_hw2reg_classa_clr_regwen_reg_t classa_clr_regwen; // [211:210] + alert_handler_hw2reg_classa_accum_cnt_reg_t classa_accum_cnt; // [209:194] + alert_handler_hw2reg_classa_esc_cnt_reg_t classa_esc_cnt; // [193:162] + alert_handler_hw2reg_classa_state_reg_t classa_state; // [161:159] + alert_handler_hw2reg_classb_clr_regwen_reg_t classb_clr_regwen; // [158:157] + alert_handler_hw2reg_classb_accum_cnt_reg_t classb_accum_cnt; // [156:141] + alert_handler_hw2reg_classb_esc_cnt_reg_t classb_esc_cnt; // [140:109] + alert_handler_hw2reg_classb_state_reg_t classb_state; // [108:106] + alert_handler_hw2reg_classc_clr_regwen_reg_t classc_clr_regwen; // [105:104] + alert_handler_hw2reg_classc_accum_cnt_reg_t classc_accum_cnt; // [103:88] + alert_handler_hw2reg_classc_esc_cnt_reg_t classc_esc_cnt; // [87:56] + alert_handler_hw2reg_classc_state_reg_t classc_state; // [55:53] + alert_handler_hw2reg_classd_clr_regwen_reg_t classd_clr_regwen; // [52:51] + alert_handler_hw2reg_classd_accum_cnt_reg_t classd_accum_cnt; // [50:35] + alert_handler_hw2reg_classd_esc_cnt_reg_t classd_esc_cnt; // [34:3] + alert_handler_hw2reg_classd_state_reg_t classd_state; // [2:0] + } alert_handler_hw2reg_t; + + // Register offsets + parameter logic [BlockAw-1:0] ALERT_HANDLER_INTR_STATE_OFFSET = 11'h 0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_INTR_ENABLE_OFFSET = 11'h 4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_INTR_TEST_OFFSET = 11'h 8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_PING_TIMER_REGWEN_OFFSET = 11'h c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 10; + parameter logic [BlockAw-1:0] ALERT_HANDLER_PING_TIMER_EN_SHADOWED_OFFSET = 11'h 14; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_0_OFFSET = 11'h 18; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_1_OFFSET = 11'h 1c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_2_OFFSET = 11'h 20; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_3_OFFSET = 11'h 24; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_4_OFFSET = 11'h 28; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_5_OFFSET = 11'h 2c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_6_OFFSET = 11'h 30; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_7_OFFSET = 11'h 34; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_8_OFFSET = 11'h 38; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_9_OFFSET = 11'h 3c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_10_OFFSET = 11'h 40; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_11_OFFSET = 11'h 44; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_12_OFFSET = 11'h 48; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_13_OFFSET = 11'h 4c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_14_OFFSET = 11'h 50; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_15_OFFSET = 11'h 54; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_16_OFFSET = 11'h 58; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_17_OFFSET = 11'h 5c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_18_OFFSET = 11'h 60; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_19_OFFSET = 11'h 64; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_20_OFFSET = 11'h 68; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_21_OFFSET = 11'h 6c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_22_OFFSET = 11'h 70; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_23_OFFSET = 11'h 74; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_24_OFFSET = 11'h 78; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_25_OFFSET = 11'h 7c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_26_OFFSET = 11'h 80; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_27_OFFSET = 11'h 84; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_28_OFFSET = 11'h 88; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_29_OFFSET = 11'h 8c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_30_OFFSET = 11'h 90; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_31_OFFSET = 11'h 94; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_32_OFFSET = 11'h 98; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_33_OFFSET = 11'h 9c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_34_OFFSET = 11'h a0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_35_OFFSET = 11'h a4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_36_OFFSET = 11'h a8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_37_OFFSET = 11'h ac; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_38_OFFSET = 11'h b0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_39_OFFSET = 11'h b4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_40_OFFSET = 11'h b8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_41_OFFSET = 11'h bc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_42_OFFSET = 11'h c0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_43_OFFSET = 11'h c4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_44_OFFSET = 11'h c8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_45_OFFSET = 11'h cc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_46_OFFSET = 11'h d0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_47_OFFSET = 11'h d4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_48_OFFSET = 11'h d8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_49_OFFSET = 11'h dc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_50_OFFSET = 11'h e0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_51_OFFSET = 11'h e4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_52_OFFSET = 11'h e8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_53_OFFSET = 11'h ec; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_54_OFFSET = 11'h f0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_55_OFFSET = 11'h f4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_56_OFFSET = 11'h f8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_57_OFFSET = 11'h fc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_58_OFFSET = 11'h 100; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_59_OFFSET = 11'h 104; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_60_OFFSET = 11'h 108; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_61_OFFSET = 11'h 10c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_62_OFFSET = 11'h 110; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_63_OFFSET = 11'h 114; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_64_OFFSET = 11'h 118; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_0_OFFSET = 11'h 11c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_1_OFFSET = 11'h 120; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_2_OFFSET = 11'h 124; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_3_OFFSET = 11'h 128; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_4_OFFSET = 11'h 12c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_5_OFFSET = 11'h 130; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_6_OFFSET = 11'h 134; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_7_OFFSET = 11'h 138; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_8_OFFSET = 11'h 13c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_9_OFFSET = 11'h 140; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_10_OFFSET = 11'h 144; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_11_OFFSET = 11'h 148; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_12_OFFSET = 11'h 14c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_13_OFFSET = 11'h 150; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_14_OFFSET = 11'h 154; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_15_OFFSET = 11'h 158; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_16_OFFSET = 11'h 15c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_17_OFFSET = 11'h 160; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_18_OFFSET = 11'h 164; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_19_OFFSET = 11'h 168; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_20_OFFSET = 11'h 16c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_21_OFFSET = 11'h 170; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_22_OFFSET = 11'h 174; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_23_OFFSET = 11'h 178; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_24_OFFSET = 11'h 17c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_25_OFFSET = 11'h 180; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_26_OFFSET = 11'h 184; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_27_OFFSET = 11'h 188; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_28_OFFSET = 11'h 18c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_29_OFFSET = 11'h 190; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_30_OFFSET = 11'h 194; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_31_OFFSET = 11'h 198; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_32_OFFSET = 11'h 19c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_33_OFFSET = 11'h 1a0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_34_OFFSET = 11'h 1a4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_35_OFFSET = 11'h 1a8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_36_OFFSET = 11'h 1ac; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_37_OFFSET = 11'h 1b0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_38_OFFSET = 11'h 1b4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_39_OFFSET = 11'h 1b8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_40_OFFSET = 11'h 1bc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_41_OFFSET = 11'h 1c0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_42_OFFSET = 11'h 1c4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_43_OFFSET = 11'h 1c8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_44_OFFSET = 11'h 1cc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_45_OFFSET = 11'h 1d0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_46_OFFSET = 11'h 1d4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_47_OFFSET = 11'h 1d8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_48_OFFSET = 11'h 1dc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_49_OFFSET = 11'h 1e0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_50_OFFSET = 11'h 1e4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_51_OFFSET = 11'h 1e8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_52_OFFSET = 11'h 1ec; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_53_OFFSET = 11'h 1f0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_54_OFFSET = 11'h 1f4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_55_OFFSET = 11'h 1f8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_56_OFFSET = 11'h 1fc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_57_OFFSET = 11'h 200; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_58_OFFSET = 11'h 204; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_59_OFFSET = 11'h 208; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_60_OFFSET = 11'h 20c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_61_OFFSET = 11'h 210; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_62_OFFSET = 11'h 214; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_63_OFFSET = 11'h 218; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_64_OFFSET = 11'h 21c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_OFFSET = 11'h 220; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_OFFSET = 11'h 224; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_OFFSET = 11'h 228; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_OFFSET = 11'h 22c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_OFFSET = 11'h 230; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_OFFSET = 11'h 234; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_OFFSET = 11'h 238; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_OFFSET = 11'h 23c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_OFFSET = 11'h 240; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_OFFSET = 11'h 244; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_OFFSET = 11'h 248; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_OFFSET = 11'h 24c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_OFFSET = 11'h 250; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_OFFSET = 11'h 254; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_OFFSET = 11'h 258; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_OFFSET = 11'h 25c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_OFFSET = 11'h 260; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_OFFSET = 11'h 264; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_OFFSET = 11'h 268; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_OFFSET = 11'h 26c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_OFFSET = 11'h 270; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_OFFSET = 11'h 274; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_OFFSET = 11'h 278; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_OFFSET = 11'h 27c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_OFFSET = 11'h 280; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_OFFSET = 11'h 284; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_OFFSET = 11'h 288; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_OFFSET = 11'h 28c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_OFFSET = 11'h 290; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_OFFSET = 11'h 294; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_OFFSET = 11'h 298; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_OFFSET = 11'h 29c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_OFFSET = 11'h 2a0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_OFFSET = 11'h 2a4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_OFFSET = 11'h 2a8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_OFFSET = 11'h 2ac; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_OFFSET = 11'h 2b0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_OFFSET = 11'h 2b4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_OFFSET = 11'h 2b8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_OFFSET = 11'h 2bc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_OFFSET = 11'h 2c0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_OFFSET = 11'h 2c4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_OFFSET = 11'h 2c8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_OFFSET = 11'h 2cc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_OFFSET = 11'h 2d0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_OFFSET = 11'h 2d4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_OFFSET = 11'h 2d8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_OFFSET = 11'h 2dc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_OFFSET = 11'h 2e0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_OFFSET = 11'h 2e4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_OFFSET = 11'h 2e8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_OFFSET = 11'h 2ec; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_OFFSET = 11'h 2f0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_OFFSET = 11'h 2f4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_OFFSET = 11'h 2f8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_OFFSET = 11'h 2fc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_OFFSET = 11'h 300; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_OFFSET = 11'h 304; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_OFFSET = 11'h 308; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_OFFSET = 11'h 30c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_OFFSET = 11'h 310; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_OFFSET = 11'h 314; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_OFFSET = 11'h 318; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_OFFSET = 11'h 31c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_OFFSET = 11'h 320; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_0_OFFSET = 11'h 324; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_1_OFFSET = 11'h 328; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_2_OFFSET = 11'h 32c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_3_OFFSET = 11'h 330; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_4_OFFSET = 11'h 334; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_5_OFFSET = 11'h 338; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_6_OFFSET = 11'h 33c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_7_OFFSET = 11'h 340; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_8_OFFSET = 11'h 344; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_9_OFFSET = 11'h 348; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_10_OFFSET = 11'h 34c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_11_OFFSET = 11'h 350; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_12_OFFSET = 11'h 354; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_13_OFFSET = 11'h 358; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_14_OFFSET = 11'h 35c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_15_OFFSET = 11'h 360; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_16_OFFSET = 11'h 364; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_17_OFFSET = 11'h 368; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_18_OFFSET = 11'h 36c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_19_OFFSET = 11'h 370; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_20_OFFSET = 11'h 374; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_21_OFFSET = 11'h 378; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_22_OFFSET = 11'h 37c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_23_OFFSET = 11'h 380; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_24_OFFSET = 11'h 384; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_25_OFFSET = 11'h 388; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_26_OFFSET = 11'h 38c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_27_OFFSET = 11'h 390; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_28_OFFSET = 11'h 394; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_29_OFFSET = 11'h 398; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_30_OFFSET = 11'h 39c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_31_OFFSET = 11'h 3a0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_32_OFFSET = 11'h 3a4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_33_OFFSET = 11'h 3a8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_34_OFFSET = 11'h 3ac; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_35_OFFSET = 11'h 3b0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_36_OFFSET = 11'h 3b4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_37_OFFSET = 11'h 3b8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_38_OFFSET = 11'h 3bc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_39_OFFSET = 11'h 3c0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_40_OFFSET = 11'h 3c4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_41_OFFSET = 11'h 3c8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_42_OFFSET = 11'h 3cc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_43_OFFSET = 11'h 3d0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_44_OFFSET = 11'h 3d4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_45_OFFSET = 11'h 3d8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_46_OFFSET = 11'h 3dc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_47_OFFSET = 11'h 3e0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_48_OFFSET = 11'h 3e4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_49_OFFSET = 11'h 3e8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_50_OFFSET = 11'h 3ec; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_51_OFFSET = 11'h 3f0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_52_OFFSET = 11'h 3f4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_53_OFFSET = 11'h 3f8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_54_OFFSET = 11'h 3fc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_55_OFFSET = 11'h 400; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_56_OFFSET = 11'h 404; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_57_OFFSET = 11'h 408; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_58_OFFSET = 11'h 40c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_59_OFFSET = 11'h 410; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_60_OFFSET = 11'h 414; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_61_OFFSET = 11'h 418; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_62_OFFSET = 11'h 41c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_63_OFFSET = 11'h 420; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_64_OFFSET = 11'h 424; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET = 11'h 428; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET = 11'h 42c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET = 11'h 430; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET = 11'h 434; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET = 11'h 438; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_5_OFFSET = 11'h 43c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_6_OFFSET = 11'h 440; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_OFFSET = 11'h 444; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_OFFSET = 11'h 448; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_OFFSET = 11'h 44c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_OFFSET = 11'h 450; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_OFFSET = 11'h 454; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_OFFSET = 11'h 458; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_OFFSET = 11'h 45c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_OFFSET = 11'h 460; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_OFFSET = 11'h 464; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_OFFSET = 11'h 468; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_OFFSET = 11'h 46c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_OFFSET = 11'h 470; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_OFFSET = 11'h 474; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_OFFSET = 11'h 478; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET = 11'h 47c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET = 11'h 480; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET = 11'h 484; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET = 11'h 488; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_4_OFFSET = 11'h 48c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_5_OFFSET = 11'h 490; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_6_OFFSET = 11'h 494; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_REGWEN_OFFSET = 11'h 498; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CTRL_SHADOWED_OFFSET = 11'h 49c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET = 11'h 4a0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_SHADOWED_OFFSET = 11'h 4a4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET = 11'h 4a8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 4ac; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 4b0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 4b4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_OFFSET = 11'h 4b8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_OFFSET = 11'h 4bc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_OFFSET = 11'h 4c0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_OFFSET = 11'h 4c4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET = 11'h 4c8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_STATE_OFFSET = 11'h 4cc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_REGWEN_OFFSET = 11'h 4d0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CTRL_SHADOWED_OFFSET = 11'h 4d4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET = 11'h 4d8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_SHADOWED_OFFSET = 11'h 4dc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET = 11'h 4e0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 4e4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 4e8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 4ec; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_OFFSET = 11'h 4f0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_OFFSET = 11'h 4f4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_OFFSET = 11'h 4f8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_OFFSET = 11'h 4fc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET = 11'h 500; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_STATE_OFFSET = 11'h 504; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_REGWEN_OFFSET = 11'h 508; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CTRL_SHADOWED_OFFSET = 11'h 50c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET = 11'h 510; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_SHADOWED_OFFSET = 11'h 514; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET = 11'h 518; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 51c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 520; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 524; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_OFFSET = 11'h 528; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_OFFSET = 11'h 52c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_OFFSET = 11'h 530; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_OFFSET = 11'h 534; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET = 11'h 538; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_STATE_OFFSET = 11'h 53c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_REGWEN_OFFSET = 11'h 540; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CTRL_SHADOWED_OFFSET = 11'h 544; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET = 11'h 548; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_SHADOWED_OFFSET = 11'h 54c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET = 11'h 550; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 554; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 558; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 55c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_OFFSET = 11'h 560; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_OFFSET = 11'h 564; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_OFFSET = 11'h 568; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_OFFSET = 11'h 56c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET = 11'h 570; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_STATE_OFFSET = 11'h 574; + + // Reset values for hwext registers and their fields + parameter logic [3:0] ALERT_HANDLER_INTR_TEST_RESVAL = 4'h 0; + parameter logic [0:0] ALERT_HANDLER_INTR_TEST_CLASSA_RESVAL = 1'h 0; + parameter logic [0:0] ALERT_HANDLER_INTR_TEST_CLASSB_RESVAL = 1'h 0; + parameter logic [0:0] ALERT_HANDLER_INTR_TEST_CLASSC_RESVAL = 1'h 0; + parameter logic [0:0] ALERT_HANDLER_INTR_TEST_CLASSD_RESVAL = 1'h 0; + parameter logic [15:0] ALERT_HANDLER_CLASSA_ACCUM_CNT_RESVAL = 16'h 0; + parameter logic [31:0] ALERT_HANDLER_CLASSA_ESC_CNT_RESVAL = 32'h 0; + parameter logic [2:0] ALERT_HANDLER_CLASSA_STATE_RESVAL = 3'h 0; + parameter logic [15:0] ALERT_HANDLER_CLASSB_ACCUM_CNT_RESVAL = 16'h 0; + parameter logic [31:0] ALERT_HANDLER_CLASSB_ESC_CNT_RESVAL = 32'h 0; + parameter logic [2:0] ALERT_HANDLER_CLASSB_STATE_RESVAL = 3'h 0; + parameter logic [15:0] ALERT_HANDLER_CLASSC_ACCUM_CNT_RESVAL = 16'h 0; + parameter logic [31:0] ALERT_HANDLER_CLASSC_ESC_CNT_RESVAL = 32'h 0; + parameter logic [2:0] ALERT_HANDLER_CLASSC_STATE_RESVAL = 3'h 0; + parameter logic [15:0] ALERT_HANDLER_CLASSD_ACCUM_CNT_RESVAL = 16'h 0; + parameter logic [31:0] ALERT_HANDLER_CLASSD_ESC_CNT_RESVAL = 32'h 0; + parameter logic [2:0] ALERT_HANDLER_CLASSD_STATE_RESVAL = 3'h 0; + + // Register index + typedef enum int { + ALERT_HANDLER_INTR_STATE, + ALERT_HANDLER_INTR_ENABLE, + ALERT_HANDLER_INTR_TEST, + ALERT_HANDLER_PING_TIMER_REGWEN, + ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED, + ALERT_HANDLER_PING_TIMER_EN_SHADOWED, + ALERT_HANDLER_ALERT_REGWEN_0, + ALERT_HANDLER_ALERT_REGWEN_1, + ALERT_HANDLER_ALERT_REGWEN_2, + ALERT_HANDLER_ALERT_REGWEN_3, + ALERT_HANDLER_ALERT_REGWEN_4, + ALERT_HANDLER_ALERT_REGWEN_5, + ALERT_HANDLER_ALERT_REGWEN_6, + ALERT_HANDLER_ALERT_REGWEN_7, + ALERT_HANDLER_ALERT_REGWEN_8, + ALERT_HANDLER_ALERT_REGWEN_9, + ALERT_HANDLER_ALERT_REGWEN_10, + ALERT_HANDLER_ALERT_REGWEN_11, + ALERT_HANDLER_ALERT_REGWEN_12, + ALERT_HANDLER_ALERT_REGWEN_13, + ALERT_HANDLER_ALERT_REGWEN_14, + ALERT_HANDLER_ALERT_REGWEN_15, + ALERT_HANDLER_ALERT_REGWEN_16, + ALERT_HANDLER_ALERT_REGWEN_17, + ALERT_HANDLER_ALERT_REGWEN_18, + ALERT_HANDLER_ALERT_REGWEN_19, + ALERT_HANDLER_ALERT_REGWEN_20, + ALERT_HANDLER_ALERT_REGWEN_21, + ALERT_HANDLER_ALERT_REGWEN_22, + ALERT_HANDLER_ALERT_REGWEN_23, + ALERT_HANDLER_ALERT_REGWEN_24, + ALERT_HANDLER_ALERT_REGWEN_25, + ALERT_HANDLER_ALERT_REGWEN_26, + ALERT_HANDLER_ALERT_REGWEN_27, + ALERT_HANDLER_ALERT_REGWEN_28, + ALERT_HANDLER_ALERT_REGWEN_29, + ALERT_HANDLER_ALERT_REGWEN_30, + ALERT_HANDLER_ALERT_REGWEN_31, + ALERT_HANDLER_ALERT_REGWEN_32, + ALERT_HANDLER_ALERT_REGWEN_33, + ALERT_HANDLER_ALERT_REGWEN_34, + ALERT_HANDLER_ALERT_REGWEN_35, + ALERT_HANDLER_ALERT_REGWEN_36, + ALERT_HANDLER_ALERT_REGWEN_37, + ALERT_HANDLER_ALERT_REGWEN_38, + ALERT_HANDLER_ALERT_REGWEN_39, + ALERT_HANDLER_ALERT_REGWEN_40, + ALERT_HANDLER_ALERT_REGWEN_41, + ALERT_HANDLER_ALERT_REGWEN_42, + ALERT_HANDLER_ALERT_REGWEN_43, + ALERT_HANDLER_ALERT_REGWEN_44, + ALERT_HANDLER_ALERT_REGWEN_45, + ALERT_HANDLER_ALERT_REGWEN_46, + ALERT_HANDLER_ALERT_REGWEN_47, + ALERT_HANDLER_ALERT_REGWEN_48, + ALERT_HANDLER_ALERT_REGWEN_49, + ALERT_HANDLER_ALERT_REGWEN_50, + ALERT_HANDLER_ALERT_REGWEN_51, + ALERT_HANDLER_ALERT_REGWEN_52, + ALERT_HANDLER_ALERT_REGWEN_53, + ALERT_HANDLER_ALERT_REGWEN_54, + ALERT_HANDLER_ALERT_REGWEN_55, + ALERT_HANDLER_ALERT_REGWEN_56, + ALERT_HANDLER_ALERT_REGWEN_57, + ALERT_HANDLER_ALERT_REGWEN_58, + ALERT_HANDLER_ALERT_REGWEN_59, + ALERT_HANDLER_ALERT_REGWEN_60, + ALERT_HANDLER_ALERT_REGWEN_61, + ALERT_HANDLER_ALERT_REGWEN_62, + ALERT_HANDLER_ALERT_REGWEN_63, + ALERT_HANDLER_ALERT_REGWEN_64, + ALERT_HANDLER_ALERT_EN_SHADOWED_0, + ALERT_HANDLER_ALERT_EN_SHADOWED_1, + ALERT_HANDLER_ALERT_EN_SHADOWED_2, + ALERT_HANDLER_ALERT_EN_SHADOWED_3, + ALERT_HANDLER_ALERT_EN_SHADOWED_4, + ALERT_HANDLER_ALERT_EN_SHADOWED_5, + ALERT_HANDLER_ALERT_EN_SHADOWED_6, + ALERT_HANDLER_ALERT_EN_SHADOWED_7, + ALERT_HANDLER_ALERT_EN_SHADOWED_8, + ALERT_HANDLER_ALERT_EN_SHADOWED_9, + ALERT_HANDLER_ALERT_EN_SHADOWED_10, + ALERT_HANDLER_ALERT_EN_SHADOWED_11, + ALERT_HANDLER_ALERT_EN_SHADOWED_12, + ALERT_HANDLER_ALERT_EN_SHADOWED_13, + ALERT_HANDLER_ALERT_EN_SHADOWED_14, + ALERT_HANDLER_ALERT_EN_SHADOWED_15, + ALERT_HANDLER_ALERT_EN_SHADOWED_16, + ALERT_HANDLER_ALERT_EN_SHADOWED_17, + ALERT_HANDLER_ALERT_EN_SHADOWED_18, + ALERT_HANDLER_ALERT_EN_SHADOWED_19, + ALERT_HANDLER_ALERT_EN_SHADOWED_20, + ALERT_HANDLER_ALERT_EN_SHADOWED_21, + ALERT_HANDLER_ALERT_EN_SHADOWED_22, + ALERT_HANDLER_ALERT_EN_SHADOWED_23, + ALERT_HANDLER_ALERT_EN_SHADOWED_24, + ALERT_HANDLER_ALERT_EN_SHADOWED_25, + ALERT_HANDLER_ALERT_EN_SHADOWED_26, + ALERT_HANDLER_ALERT_EN_SHADOWED_27, + ALERT_HANDLER_ALERT_EN_SHADOWED_28, + ALERT_HANDLER_ALERT_EN_SHADOWED_29, + ALERT_HANDLER_ALERT_EN_SHADOWED_30, + ALERT_HANDLER_ALERT_EN_SHADOWED_31, + ALERT_HANDLER_ALERT_EN_SHADOWED_32, + ALERT_HANDLER_ALERT_EN_SHADOWED_33, + ALERT_HANDLER_ALERT_EN_SHADOWED_34, + ALERT_HANDLER_ALERT_EN_SHADOWED_35, + ALERT_HANDLER_ALERT_EN_SHADOWED_36, + ALERT_HANDLER_ALERT_EN_SHADOWED_37, + ALERT_HANDLER_ALERT_EN_SHADOWED_38, + ALERT_HANDLER_ALERT_EN_SHADOWED_39, + ALERT_HANDLER_ALERT_EN_SHADOWED_40, + ALERT_HANDLER_ALERT_EN_SHADOWED_41, + ALERT_HANDLER_ALERT_EN_SHADOWED_42, + ALERT_HANDLER_ALERT_EN_SHADOWED_43, + ALERT_HANDLER_ALERT_EN_SHADOWED_44, + ALERT_HANDLER_ALERT_EN_SHADOWED_45, + ALERT_HANDLER_ALERT_EN_SHADOWED_46, + ALERT_HANDLER_ALERT_EN_SHADOWED_47, + ALERT_HANDLER_ALERT_EN_SHADOWED_48, + ALERT_HANDLER_ALERT_EN_SHADOWED_49, + ALERT_HANDLER_ALERT_EN_SHADOWED_50, + ALERT_HANDLER_ALERT_EN_SHADOWED_51, + ALERT_HANDLER_ALERT_EN_SHADOWED_52, + ALERT_HANDLER_ALERT_EN_SHADOWED_53, + ALERT_HANDLER_ALERT_EN_SHADOWED_54, + ALERT_HANDLER_ALERT_EN_SHADOWED_55, + ALERT_HANDLER_ALERT_EN_SHADOWED_56, + ALERT_HANDLER_ALERT_EN_SHADOWED_57, + ALERT_HANDLER_ALERT_EN_SHADOWED_58, + ALERT_HANDLER_ALERT_EN_SHADOWED_59, + ALERT_HANDLER_ALERT_EN_SHADOWED_60, + ALERT_HANDLER_ALERT_EN_SHADOWED_61, + ALERT_HANDLER_ALERT_EN_SHADOWED_62, + ALERT_HANDLER_ALERT_EN_SHADOWED_63, + ALERT_HANDLER_ALERT_EN_SHADOWED_64, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_0, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_1, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_2, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_3, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_4, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_5, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_6, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_7, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_8, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_9, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_10, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_11, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_12, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_13, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_14, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_15, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_16, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_17, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_18, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_19, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_20, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_21, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_22, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_23, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_24, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_25, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_26, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_27, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_28, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_29, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_30, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_31, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_32, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_33, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_34, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_35, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_36, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_37, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_38, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_39, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_40, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_41, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_42, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_43, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_44, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_45, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_46, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_47, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_48, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_49, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_50, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_51, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_52, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_53, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_54, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_55, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_56, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_57, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_58, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_59, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_60, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_61, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_62, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_63, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_64, + ALERT_HANDLER_ALERT_CAUSE_0, + ALERT_HANDLER_ALERT_CAUSE_1, + ALERT_HANDLER_ALERT_CAUSE_2, + ALERT_HANDLER_ALERT_CAUSE_3, + ALERT_HANDLER_ALERT_CAUSE_4, + ALERT_HANDLER_ALERT_CAUSE_5, + ALERT_HANDLER_ALERT_CAUSE_6, + ALERT_HANDLER_ALERT_CAUSE_7, + ALERT_HANDLER_ALERT_CAUSE_8, + ALERT_HANDLER_ALERT_CAUSE_9, + ALERT_HANDLER_ALERT_CAUSE_10, + ALERT_HANDLER_ALERT_CAUSE_11, + ALERT_HANDLER_ALERT_CAUSE_12, + ALERT_HANDLER_ALERT_CAUSE_13, + ALERT_HANDLER_ALERT_CAUSE_14, + ALERT_HANDLER_ALERT_CAUSE_15, + ALERT_HANDLER_ALERT_CAUSE_16, + ALERT_HANDLER_ALERT_CAUSE_17, + ALERT_HANDLER_ALERT_CAUSE_18, + ALERT_HANDLER_ALERT_CAUSE_19, + ALERT_HANDLER_ALERT_CAUSE_20, + ALERT_HANDLER_ALERT_CAUSE_21, + ALERT_HANDLER_ALERT_CAUSE_22, + ALERT_HANDLER_ALERT_CAUSE_23, + ALERT_HANDLER_ALERT_CAUSE_24, + ALERT_HANDLER_ALERT_CAUSE_25, + ALERT_HANDLER_ALERT_CAUSE_26, + ALERT_HANDLER_ALERT_CAUSE_27, + ALERT_HANDLER_ALERT_CAUSE_28, + ALERT_HANDLER_ALERT_CAUSE_29, + ALERT_HANDLER_ALERT_CAUSE_30, + ALERT_HANDLER_ALERT_CAUSE_31, + ALERT_HANDLER_ALERT_CAUSE_32, + ALERT_HANDLER_ALERT_CAUSE_33, + ALERT_HANDLER_ALERT_CAUSE_34, + ALERT_HANDLER_ALERT_CAUSE_35, + ALERT_HANDLER_ALERT_CAUSE_36, + ALERT_HANDLER_ALERT_CAUSE_37, + ALERT_HANDLER_ALERT_CAUSE_38, + ALERT_HANDLER_ALERT_CAUSE_39, + ALERT_HANDLER_ALERT_CAUSE_40, + ALERT_HANDLER_ALERT_CAUSE_41, + ALERT_HANDLER_ALERT_CAUSE_42, + ALERT_HANDLER_ALERT_CAUSE_43, + ALERT_HANDLER_ALERT_CAUSE_44, + ALERT_HANDLER_ALERT_CAUSE_45, + ALERT_HANDLER_ALERT_CAUSE_46, + ALERT_HANDLER_ALERT_CAUSE_47, + ALERT_HANDLER_ALERT_CAUSE_48, + ALERT_HANDLER_ALERT_CAUSE_49, + ALERT_HANDLER_ALERT_CAUSE_50, + ALERT_HANDLER_ALERT_CAUSE_51, + ALERT_HANDLER_ALERT_CAUSE_52, + ALERT_HANDLER_ALERT_CAUSE_53, + ALERT_HANDLER_ALERT_CAUSE_54, + ALERT_HANDLER_ALERT_CAUSE_55, + ALERT_HANDLER_ALERT_CAUSE_56, + ALERT_HANDLER_ALERT_CAUSE_57, + ALERT_HANDLER_ALERT_CAUSE_58, + ALERT_HANDLER_ALERT_CAUSE_59, + ALERT_HANDLER_ALERT_CAUSE_60, + ALERT_HANDLER_ALERT_CAUSE_61, + ALERT_HANDLER_ALERT_CAUSE_62, + ALERT_HANDLER_ALERT_CAUSE_63, + ALERT_HANDLER_ALERT_CAUSE_64, + ALERT_HANDLER_LOC_ALERT_REGWEN_0, + ALERT_HANDLER_LOC_ALERT_REGWEN_1, + ALERT_HANDLER_LOC_ALERT_REGWEN_2, + ALERT_HANDLER_LOC_ALERT_REGWEN_3, + ALERT_HANDLER_LOC_ALERT_REGWEN_4, + ALERT_HANDLER_LOC_ALERT_REGWEN_5, + ALERT_HANDLER_LOC_ALERT_REGWEN_6, + ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0, + ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1, + ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2, + ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3, + ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4, + ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5, + ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6, + ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0, + ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1, + ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2, + ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3, + ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4, + ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5, + ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6, + ALERT_HANDLER_LOC_ALERT_CAUSE_0, + ALERT_HANDLER_LOC_ALERT_CAUSE_1, + ALERT_HANDLER_LOC_ALERT_CAUSE_2, + ALERT_HANDLER_LOC_ALERT_CAUSE_3, + ALERT_HANDLER_LOC_ALERT_CAUSE_4, + ALERT_HANDLER_LOC_ALERT_CAUSE_5, + ALERT_HANDLER_LOC_ALERT_CAUSE_6, + ALERT_HANDLER_CLASSA_REGWEN, + ALERT_HANDLER_CLASSA_CTRL_SHADOWED, + ALERT_HANDLER_CLASSA_CLR_REGWEN, + ALERT_HANDLER_CLASSA_CLR_SHADOWED, + ALERT_HANDLER_CLASSA_ACCUM_CNT, + ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED, + ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED, + ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED, + ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED, + ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED, + ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED, + ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED, + ALERT_HANDLER_CLASSA_ESC_CNT, + ALERT_HANDLER_CLASSA_STATE, + ALERT_HANDLER_CLASSB_REGWEN, + ALERT_HANDLER_CLASSB_CTRL_SHADOWED, + ALERT_HANDLER_CLASSB_CLR_REGWEN, + ALERT_HANDLER_CLASSB_CLR_SHADOWED, + ALERT_HANDLER_CLASSB_ACCUM_CNT, + ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED, + ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED, + ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED, + ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED, + ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED, + ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED, + ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED, + ALERT_HANDLER_CLASSB_ESC_CNT, + ALERT_HANDLER_CLASSB_STATE, + ALERT_HANDLER_CLASSC_REGWEN, + ALERT_HANDLER_CLASSC_CTRL_SHADOWED, + ALERT_HANDLER_CLASSC_CLR_REGWEN, + ALERT_HANDLER_CLASSC_CLR_SHADOWED, + ALERT_HANDLER_CLASSC_ACCUM_CNT, + ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED, + ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED, + ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED, + ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED, + ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED, + ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED, + ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED, + ALERT_HANDLER_CLASSC_ESC_CNT, + ALERT_HANDLER_CLASSC_STATE, + ALERT_HANDLER_CLASSD_REGWEN, + ALERT_HANDLER_CLASSD_CTRL_SHADOWED, + ALERT_HANDLER_CLASSD_CLR_REGWEN, + ALERT_HANDLER_CLASSD_CLR_SHADOWED, + ALERT_HANDLER_CLASSD_ACCUM_CNT, + ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED, + ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED, + ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED, + ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED, + ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED, + ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED, + ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED, + ALERT_HANDLER_CLASSD_ESC_CNT, + ALERT_HANDLER_CLASSD_STATE + } alert_handler_id_e; + + // Register width information to check illegal writes + parameter logic [3:0] ALERT_HANDLER_PERMIT [350] = '{ + 4'b 0001, // index[ 0] ALERT_HANDLER_INTR_STATE + 4'b 0001, // index[ 1] ALERT_HANDLER_INTR_ENABLE + 4'b 0001, // index[ 2] ALERT_HANDLER_INTR_TEST + 4'b 0001, // index[ 3] ALERT_HANDLER_PING_TIMER_REGWEN + 4'b 0011, // index[ 4] ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED + 4'b 0001, // index[ 5] ALERT_HANDLER_PING_TIMER_EN_SHADOWED + 4'b 0001, // index[ 6] ALERT_HANDLER_ALERT_REGWEN_0 + 4'b 0001, // index[ 7] ALERT_HANDLER_ALERT_REGWEN_1 + 4'b 0001, // index[ 8] ALERT_HANDLER_ALERT_REGWEN_2 + 4'b 0001, // index[ 9] ALERT_HANDLER_ALERT_REGWEN_3 + 4'b 0001, // index[ 10] ALERT_HANDLER_ALERT_REGWEN_4 + 4'b 0001, // index[ 11] ALERT_HANDLER_ALERT_REGWEN_5 + 4'b 0001, // index[ 12] ALERT_HANDLER_ALERT_REGWEN_6 + 4'b 0001, // index[ 13] ALERT_HANDLER_ALERT_REGWEN_7 + 4'b 0001, // index[ 14] ALERT_HANDLER_ALERT_REGWEN_8 + 4'b 0001, // index[ 15] ALERT_HANDLER_ALERT_REGWEN_9 + 4'b 0001, // index[ 16] ALERT_HANDLER_ALERT_REGWEN_10 + 4'b 0001, // index[ 17] ALERT_HANDLER_ALERT_REGWEN_11 + 4'b 0001, // index[ 18] ALERT_HANDLER_ALERT_REGWEN_12 + 4'b 0001, // index[ 19] ALERT_HANDLER_ALERT_REGWEN_13 + 4'b 0001, // index[ 20] ALERT_HANDLER_ALERT_REGWEN_14 + 4'b 0001, // index[ 21] ALERT_HANDLER_ALERT_REGWEN_15 + 4'b 0001, // index[ 22] ALERT_HANDLER_ALERT_REGWEN_16 + 4'b 0001, // index[ 23] ALERT_HANDLER_ALERT_REGWEN_17 + 4'b 0001, // index[ 24] ALERT_HANDLER_ALERT_REGWEN_18 + 4'b 0001, // index[ 25] ALERT_HANDLER_ALERT_REGWEN_19 + 4'b 0001, // index[ 26] ALERT_HANDLER_ALERT_REGWEN_20 + 4'b 0001, // index[ 27] ALERT_HANDLER_ALERT_REGWEN_21 + 4'b 0001, // index[ 28] ALERT_HANDLER_ALERT_REGWEN_22 + 4'b 0001, // index[ 29] ALERT_HANDLER_ALERT_REGWEN_23 + 4'b 0001, // index[ 30] ALERT_HANDLER_ALERT_REGWEN_24 + 4'b 0001, // index[ 31] ALERT_HANDLER_ALERT_REGWEN_25 + 4'b 0001, // index[ 32] ALERT_HANDLER_ALERT_REGWEN_26 + 4'b 0001, // index[ 33] ALERT_HANDLER_ALERT_REGWEN_27 + 4'b 0001, // index[ 34] ALERT_HANDLER_ALERT_REGWEN_28 + 4'b 0001, // index[ 35] ALERT_HANDLER_ALERT_REGWEN_29 + 4'b 0001, // index[ 36] ALERT_HANDLER_ALERT_REGWEN_30 + 4'b 0001, // index[ 37] ALERT_HANDLER_ALERT_REGWEN_31 + 4'b 0001, // index[ 38] ALERT_HANDLER_ALERT_REGWEN_32 + 4'b 0001, // index[ 39] ALERT_HANDLER_ALERT_REGWEN_33 + 4'b 0001, // index[ 40] ALERT_HANDLER_ALERT_REGWEN_34 + 4'b 0001, // index[ 41] ALERT_HANDLER_ALERT_REGWEN_35 + 4'b 0001, // index[ 42] ALERT_HANDLER_ALERT_REGWEN_36 + 4'b 0001, // index[ 43] ALERT_HANDLER_ALERT_REGWEN_37 + 4'b 0001, // index[ 44] ALERT_HANDLER_ALERT_REGWEN_38 + 4'b 0001, // index[ 45] ALERT_HANDLER_ALERT_REGWEN_39 + 4'b 0001, // index[ 46] ALERT_HANDLER_ALERT_REGWEN_40 + 4'b 0001, // index[ 47] ALERT_HANDLER_ALERT_REGWEN_41 + 4'b 0001, // index[ 48] ALERT_HANDLER_ALERT_REGWEN_42 + 4'b 0001, // index[ 49] ALERT_HANDLER_ALERT_REGWEN_43 + 4'b 0001, // index[ 50] ALERT_HANDLER_ALERT_REGWEN_44 + 4'b 0001, // index[ 51] ALERT_HANDLER_ALERT_REGWEN_45 + 4'b 0001, // index[ 52] ALERT_HANDLER_ALERT_REGWEN_46 + 4'b 0001, // index[ 53] ALERT_HANDLER_ALERT_REGWEN_47 + 4'b 0001, // index[ 54] ALERT_HANDLER_ALERT_REGWEN_48 + 4'b 0001, // index[ 55] ALERT_HANDLER_ALERT_REGWEN_49 + 4'b 0001, // index[ 56] ALERT_HANDLER_ALERT_REGWEN_50 + 4'b 0001, // index[ 57] ALERT_HANDLER_ALERT_REGWEN_51 + 4'b 0001, // index[ 58] ALERT_HANDLER_ALERT_REGWEN_52 + 4'b 0001, // index[ 59] ALERT_HANDLER_ALERT_REGWEN_53 + 4'b 0001, // index[ 60] ALERT_HANDLER_ALERT_REGWEN_54 + 4'b 0001, // index[ 61] ALERT_HANDLER_ALERT_REGWEN_55 + 4'b 0001, // index[ 62] ALERT_HANDLER_ALERT_REGWEN_56 + 4'b 0001, // index[ 63] ALERT_HANDLER_ALERT_REGWEN_57 + 4'b 0001, // index[ 64] ALERT_HANDLER_ALERT_REGWEN_58 + 4'b 0001, // index[ 65] ALERT_HANDLER_ALERT_REGWEN_59 + 4'b 0001, // index[ 66] ALERT_HANDLER_ALERT_REGWEN_60 + 4'b 0001, // index[ 67] ALERT_HANDLER_ALERT_REGWEN_61 + 4'b 0001, // index[ 68] ALERT_HANDLER_ALERT_REGWEN_62 + 4'b 0001, // index[ 69] ALERT_HANDLER_ALERT_REGWEN_63 + 4'b 0001, // index[ 70] ALERT_HANDLER_ALERT_REGWEN_64 + 4'b 0001, // index[ 71] ALERT_HANDLER_ALERT_EN_SHADOWED_0 + 4'b 0001, // index[ 72] ALERT_HANDLER_ALERT_EN_SHADOWED_1 + 4'b 0001, // index[ 73] ALERT_HANDLER_ALERT_EN_SHADOWED_2 + 4'b 0001, // index[ 74] ALERT_HANDLER_ALERT_EN_SHADOWED_3 + 4'b 0001, // index[ 75] ALERT_HANDLER_ALERT_EN_SHADOWED_4 + 4'b 0001, // index[ 76] ALERT_HANDLER_ALERT_EN_SHADOWED_5 + 4'b 0001, // index[ 77] ALERT_HANDLER_ALERT_EN_SHADOWED_6 + 4'b 0001, // index[ 78] ALERT_HANDLER_ALERT_EN_SHADOWED_7 + 4'b 0001, // index[ 79] ALERT_HANDLER_ALERT_EN_SHADOWED_8 + 4'b 0001, // index[ 80] ALERT_HANDLER_ALERT_EN_SHADOWED_9 + 4'b 0001, // index[ 81] ALERT_HANDLER_ALERT_EN_SHADOWED_10 + 4'b 0001, // index[ 82] ALERT_HANDLER_ALERT_EN_SHADOWED_11 + 4'b 0001, // index[ 83] ALERT_HANDLER_ALERT_EN_SHADOWED_12 + 4'b 0001, // index[ 84] ALERT_HANDLER_ALERT_EN_SHADOWED_13 + 4'b 0001, // index[ 85] ALERT_HANDLER_ALERT_EN_SHADOWED_14 + 4'b 0001, // index[ 86] ALERT_HANDLER_ALERT_EN_SHADOWED_15 + 4'b 0001, // index[ 87] ALERT_HANDLER_ALERT_EN_SHADOWED_16 + 4'b 0001, // index[ 88] ALERT_HANDLER_ALERT_EN_SHADOWED_17 + 4'b 0001, // index[ 89] ALERT_HANDLER_ALERT_EN_SHADOWED_18 + 4'b 0001, // index[ 90] ALERT_HANDLER_ALERT_EN_SHADOWED_19 + 4'b 0001, // index[ 91] ALERT_HANDLER_ALERT_EN_SHADOWED_20 + 4'b 0001, // index[ 92] ALERT_HANDLER_ALERT_EN_SHADOWED_21 + 4'b 0001, // index[ 93] ALERT_HANDLER_ALERT_EN_SHADOWED_22 + 4'b 0001, // index[ 94] ALERT_HANDLER_ALERT_EN_SHADOWED_23 + 4'b 0001, // index[ 95] ALERT_HANDLER_ALERT_EN_SHADOWED_24 + 4'b 0001, // index[ 96] ALERT_HANDLER_ALERT_EN_SHADOWED_25 + 4'b 0001, // index[ 97] ALERT_HANDLER_ALERT_EN_SHADOWED_26 + 4'b 0001, // index[ 98] ALERT_HANDLER_ALERT_EN_SHADOWED_27 + 4'b 0001, // index[ 99] ALERT_HANDLER_ALERT_EN_SHADOWED_28 + 4'b 0001, // index[100] ALERT_HANDLER_ALERT_EN_SHADOWED_29 + 4'b 0001, // index[101] ALERT_HANDLER_ALERT_EN_SHADOWED_30 + 4'b 0001, // index[102] ALERT_HANDLER_ALERT_EN_SHADOWED_31 + 4'b 0001, // index[103] ALERT_HANDLER_ALERT_EN_SHADOWED_32 + 4'b 0001, // index[104] ALERT_HANDLER_ALERT_EN_SHADOWED_33 + 4'b 0001, // index[105] ALERT_HANDLER_ALERT_EN_SHADOWED_34 + 4'b 0001, // index[106] ALERT_HANDLER_ALERT_EN_SHADOWED_35 + 4'b 0001, // index[107] ALERT_HANDLER_ALERT_EN_SHADOWED_36 + 4'b 0001, // index[108] ALERT_HANDLER_ALERT_EN_SHADOWED_37 + 4'b 0001, // index[109] ALERT_HANDLER_ALERT_EN_SHADOWED_38 + 4'b 0001, // index[110] ALERT_HANDLER_ALERT_EN_SHADOWED_39 + 4'b 0001, // index[111] ALERT_HANDLER_ALERT_EN_SHADOWED_40 + 4'b 0001, // index[112] ALERT_HANDLER_ALERT_EN_SHADOWED_41 + 4'b 0001, // index[113] ALERT_HANDLER_ALERT_EN_SHADOWED_42 + 4'b 0001, // index[114] ALERT_HANDLER_ALERT_EN_SHADOWED_43 + 4'b 0001, // index[115] ALERT_HANDLER_ALERT_EN_SHADOWED_44 + 4'b 0001, // index[116] ALERT_HANDLER_ALERT_EN_SHADOWED_45 + 4'b 0001, // index[117] ALERT_HANDLER_ALERT_EN_SHADOWED_46 + 4'b 0001, // index[118] ALERT_HANDLER_ALERT_EN_SHADOWED_47 + 4'b 0001, // index[119] ALERT_HANDLER_ALERT_EN_SHADOWED_48 + 4'b 0001, // index[120] ALERT_HANDLER_ALERT_EN_SHADOWED_49 + 4'b 0001, // index[121] ALERT_HANDLER_ALERT_EN_SHADOWED_50 + 4'b 0001, // index[122] ALERT_HANDLER_ALERT_EN_SHADOWED_51 + 4'b 0001, // index[123] ALERT_HANDLER_ALERT_EN_SHADOWED_52 + 4'b 0001, // index[124] ALERT_HANDLER_ALERT_EN_SHADOWED_53 + 4'b 0001, // index[125] ALERT_HANDLER_ALERT_EN_SHADOWED_54 + 4'b 0001, // index[126] ALERT_HANDLER_ALERT_EN_SHADOWED_55 + 4'b 0001, // index[127] ALERT_HANDLER_ALERT_EN_SHADOWED_56 + 4'b 0001, // index[128] ALERT_HANDLER_ALERT_EN_SHADOWED_57 + 4'b 0001, // index[129] ALERT_HANDLER_ALERT_EN_SHADOWED_58 + 4'b 0001, // index[130] ALERT_HANDLER_ALERT_EN_SHADOWED_59 + 4'b 0001, // index[131] ALERT_HANDLER_ALERT_EN_SHADOWED_60 + 4'b 0001, // index[132] ALERT_HANDLER_ALERT_EN_SHADOWED_61 + 4'b 0001, // index[133] ALERT_HANDLER_ALERT_EN_SHADOWED_62 + 4'b 0001, // index[134] ALERT_HANDLER_ALERT_EN_SHADOWED_63 + 4'b 0001, // index[135] ALERT_HANDLER_ALERT_EN_SHADOWED_64 + 4'b 0001, // index[136] ALERT_HANDLER_ALERT_CLASS_SHADOWED_0 + 4'b 0001, // index[137] ALERT_HANDLER_ALERT_CLASS_SHADOWED_1 + 4'b 0001, // index[138] ALERT_HANDLER_ALERT_CLASS_SHADOWED_2 + 4'b 0001, // index[139] ALERT_HANDLER_ALERT_CLASS_SHADOWED_3 + 4'b 0001, // index[140] ALERT_HANDLER_ALERT_CLASS_SHADOWED_4 + 4'b 0001, // index[141] ALERT_HANDLER_ALERT_CLASS_SHADOWED_5 + 4'b 0001, // index[142] ALERT_HANDLER_ALERT_CLASS_SHADOWED_6 + 4'b 0001, // index[143] ALERT_HANDLER_ALERT_CLASS_SHADOWED_7 + 4'b 0001, // index[144] ALERT_HANDLER_ALERT_CLASS_SHADOWED_8 + 4'b 0001, // index[145] ALERT_HANDLER_ALERT_CLASS_SHADOWED_9 + 4'b 0001, // index[146] ALERT_HANDLER_ALERT_CLASS_SHADOWED_10 + 4'b 0001, // index[147] ALERT_HANDLER_ALERT_CLASS_SHADOWED_11 + 4'b 0001, // index[148] ALERT_HANDLER_ALERT_CLASS_SHADOWED_12 + 4'b 0001, // index[149] ALERT_HANDLER_ALERT_CLASS_SHADOWED_13 + 4'b 0001, // index[150] ALERT_HANDLER_ALERT_CLASS_SHADOWED_14 + 4'b 0001, // index[151] ALERT_HANDLER_ALERT_CLASS_SHADOWED_15 + 4'b 0001, // index[152] ALERT_HANDLER_ALERT_CLASS_SHADOWED_16 + 4'b 0001, // index[153] ALERT_HANDLER_ALERT_CLASS_SHADOWED_17 + 4'b 0001, // index[154] ALERT_HANDLER_ALERT_CLASS_SHADOWED_18 + 4'b 0001, // index[155] ALERT_HANDLER_ALERT_CLASS_SHADOWED_19 + 4'b 0001, // index[156] ALERT_HANDLER_ALERT_CLASS_SHADOWED_20 + 4'b 0001, // index[157] ALERT_HANDLER_ALERT_CLASS_SHADOWED_21 + 4'b 0001, // index[158] ALERT_HANDLER_ALERT_CLASS_SHADOWED_22 + 4'b 0001, // index[159] ALERT_HANDLER_ALERT_CLASS_SHADOWED_23 + 4'b 0001, // index[160] ALERT_HANDLER_ALERT_CLASS_SHADOWED_24 + 4'b 0001, // index[161] ALERT_HANDLER_ALERT_CLASS_SHADOWED_25 + 4'b 0001, // index[162] ALERT_HANDLER_ALERT_CLASS_SHADOWED_26 + 4'b 0001, // index[163] ALERT_HANDLER_ALERT_CLASS_SHADOWED_27 + 4'b 0001, // index[164] ALERT_HANDLER_ALERT_CLASS_SHADOWED_28 + 4'b 0001, // index[165] ALERT_HANDLER_ALERT_CLASS_SHADOWED_29 + 4'b 0001, // index[166] ALERT_HANDLER_ALERT_CLASS_SHADOWED_30 + 4'b 0001, // index[167] ALERT_HANDLER_ALERT_CLASS_SHADOWED_31 + 4'b 0001, // index[168] ALERT_HANDLER_ALERT_CLASS_SHADOWED_32 + 4'b 0001, // index[169] ALERT_HANDLER_ALERT_CLASS_SHADOWED_33 + 4'b 0001, // index[170] ALERT_HANDLER_ALERT_CLASS_SHADOWED_34 + 4'b 0001, // index[171] ALERT_HANDLER_ALERT_CLASS_SHADOWED_35 + 4'b 0001, // index[172] ALERT_HANDLER_ALERT_CLASS_SHADOWED_36 + 4'b 0001, // index[173] ALERT_HANDLER_ALERT_CLASS_SHADOWED_37 + 4'b 0001, // index[174] ALERT_HANDLER_ALERT_CLASS_SHADOWED_38 + 4'b 0001, // index[175] ALERT_HANDLER_ALERT_CLASS_SHADOWED_39 + 4'b 0001, // index[176] ALERT_HANDLER_ALERT_CLASS_SHADOWED_40 + 4'b 0001, // index[177] ALERT_HANDLER_ALERT_CLASS_SHADOWED_41 + 4'b 0001, // index[178] ALERT_HANDLER_ALERT_CLASS_SHADOWED_42 + 4'b 0001, // index[179] ALERT_HANDLER_ALERT_CLASS_SHADOWED_43 + 4'b 0001, // index[180] ALERT_HANDLER_ALERT_CLASS_SHADOWED_44 + 4'b 0001, // index[181] ALERT_HANDLER_ALERT_CLASS_SHADOWED_45 + 4'b 0001, // index[182] ALERT_HANDLER_ALERT_CLASS_SHADOWED_46 + 4'b 0001, // index[183] ALERT_HANDLER_ALERT_CLASS_SHADOWED_47 + 4'b 0001, // index[184] ALERT_HANDLER_ALERT_CLASS_SHADOWED_48 + 4'b 0001, // index[185] ALERT_HANDLER_ALERT_CLASS_SHADOWED_49 + 4'b 0001, // index[186] ALERT_HANDLER_ALERT_CLASS_SHADOWED_50 + 4'b 0001, // index[187] ALERT_HANDLER_ALERT_CLASS_SHADOWED_51 + 4'b 0001, // index[188] ALERT_HANDLER_ALERT_CLASS_SHADOWED_52 + 4'b 0001, // index[189] ALERT_HANDLER_ALERT_CLASS_SHADOWED_53 + 4'b 0001, // index[190] ALERT_HANDLER_ALERT_CLASS_SHADOWED_54 + 4'b 0001, // index[191] ALERT_HANDLER_ALERT_CLASS_SHADOWED_55 + 4'b 0001, // index[192] ALERT_HANDLER_ALERT_CLASS_SHADOWED_56 + 4'b 0001, // index[193] ALERT_HANDLER_ALERT_CLASS_SHADOWED_57 + 4'b 0001, // index[194] ALERT_HANDLER_ALERT_CLASS_SHADOWED_58 + 4'b 0001, // index[195] ALERT_HANDLER_ALERT_CLASS_SHADOWED_59 + 4'b 0001, // index[196] ALERT_HANDLER_ALERT_CLASS_SHADOWED_60 + 4'b 0001, // index[197] ALERT_HANDLER_ALERT_CLASS_SHADOWED_61 + 4'b 0001, // index[198] ALERT_HANDLER_ALERT_CLASS_SHADOWED_62 + 4'b 0001, // index[199] ALERT_HANDLER_ALERT_CLASS_SHADOWED_63 + 4'b 0001, // index[200] ALERT_HANDLER_ALERT_CLASS_SHADOWED_64 + 4'b 0001, // index[201] ALERT_HANDLER_ALERT_CAUSE_0 + 4'b 0001, // index[202] ALERT_HANDLER_ALERT_CAUSE_1 + 4'b 0001, // index[203] ALERT_HANDLER_ALERT_CAUSE_2 + 4'b 0001, // index[204] ALERT_HANDLER_ALERT_CAUSE_3 + 4'b 0001, // index[205] ALERT_HANDLER_ALERT_CAUSE_4 + 4'b 0001, // index[206] ALERT_HANDLER_ALERT_CAUSE_5 + 4'b 0001, // index[207] ALERT_HANDLER_ALERT_CAUSE_6 + 4'b 0001, // index[208] ALERT_HANDLER_ALERT_CAUSE_7 + 4'b 0001, // index[209] ALERT_HANDLER_ALERT_CAUSE_8 + 4'b 0001, // index[210] ALERT_HANDLER_ALERT_CAUSE_9 + 4'b 0001, // index[211] ALERT_HANDLER_ALERT_CAUSE_10 + 4'b 0001, // index[212] ALERT_HANDLER_ALERT_CAUSE_11 + 4'b 0001, // index[213] ALERT_HANDLER_ALERT_CAUSE_12 + 4'b 0001, // index[214] ALERT_HANDLER_ALERT_CAUSE_13 + 4'b 0001, // index[215] ALERT_HANDLER_ALERT_CAUSE_14 + 4'b 0001, // index[216] ALERT_HANDLER_ALERT_CAUSE_15 + 4'b 0001, // index[217] ALERT_HANDLER_ALERT_CAUSE_16 + 4'b 0001, // index[218] ALERT_HANDLER_ALERT_CAUSE_17 + 4'b 0001, // index[219] ALERT_HANDLER_ALERT_CAUSE_18 + 4'b 0001, // index[220] ALERT_HANDLER_ALERT_CAUSE_19 + 4'b 0001, // index[221] ALERT_HANDLER_ALERT_CAUSE_20 + 4'b 0001, // index[222] ALERT_HANDLER_ALERT_CAUSE_21 + 4'b 0001, // index[223] ALERT_HANDLER_ALERT_CAUSE_22 + 4'b 0001, // index[224] ALERT_HANDLER_ALERT_CAUSE_23 + 4'b 0001, // index[225] ALERT_HANDLER_ALERT_CAUSE_24 + 4'b 0001, // index[226] ALERT_HANDLER_ALERT_CAUSE_25 + 4'b 0001, // index[227] ALERT_HANDLER_ALERT_CAUSE_26 + 4'b 0001, // index[228] ALERT_HANDLER_ALERT_CAUSE_27 + 4'b 0001, // index[229] ALERT_HANDLER_ALERT_CAUSE_28 + 4'b 0001, // index[230] ALERT_HANDLER_ALERT_CAUSE_29 + 4'b 0001, // index[231] ALERT_HANDLER_ALERT_CAUSE_30 + 4'b 0001, // index[232] ALERT_HANDLER_ALERT_CAUSE_31 + 4'b 0001, // index[233] ALERT_HANDLER_ALERT_CAUSE_32 + 4'b 0001, // index[234] ALERT_HANDLER_ALERT_CAUSE_33 + 4'b 0001, // index[235] ALERT_HANDLER_ALERT_CAUSE_34 + 4'b 0001, // index[236] ALERT_HANDLER_ALERT_CAUSE_35 + 4'b 0001, // index[237] ALERT_HANDLER_ALERT_CAUSE_36 + 4'b 0001, // index[238] ALERT_HANDLER_ALERT_CAUSE_37 + 4'b 0001, // index[239] ALERT_HANDLER_ALERT_CAUSE_38 + 4'b 0001, // index[240] ALERT_HANDLER_ALERT_CAUSE_39 + 4'b 0001, // index[241] ALERT_HANDLER_ALERT_CAUSE_40 + 4'b 0001, // index[242] ALERT_HANDLER_ALERT_CAUSE_41 + 4'b 0001, // index[243] ALERT_HANDLER_ALERT_CAUSE_42 + 4'b 0001, // index[244] ALERT_HANDLER_ALERT_CAUSE_43 + 4'b 0001, // index[245] ALERT_HANDLER_ALERT_CAUSE_44 + 4'b 0001, // index[246] ALERT_HANDLER_ALERT_CAUSE_45 + 4'b 0001, // index[247] ALERT_HANDLER_ALERT_CAUSE_46 + 4'b 0001, // index[248] ALERT_HANDLER_ALERT_CAUSE_47 + 4'b 0001, // index[249] ALERT_HANDLER_ALERT_CAUSE_48 + 4'b 0001, // index[250] ALERT_HANDLER_ALERT_CAUSE_49 + 4'b 0001, // index[251] ALERT_HANDLER_ALERT_CAUSE_50 + 4'b 0001, // index[252] ALERT_HANDLER_ALERT_CAUSE_51 + 4'b 0001, // index[253] ALERT_HANDLER_ALERT_CAUSE_52 + 4'b 0001, // index[254] ALERT_HANDLER_ALERT_CAUSE_53 + 4'b 0001, // index[255] ALERT_HANDLER_ALERT_CAUSE_54 + 4'b 0001, // index[256] ALERT_HANDLER_ALERT_CAUSE_55 + 4'b 0001, // index[257] ALERT_HANDLER_ALERT_CAUSE_56 + 4'b 0001, // index[258] ALERT_HANDLER_ALERT_CAUSE_57 + 4'b 0001, // index[259] ALERT_HANDLER_ALERT_CAUSE_58 + 4'b 0001, // index[260] ALERT_HANDLER_ALERT_CAUSE_59 + 4'b 0001, // index[261] ALERT_HANDLER_ALERT_CAUSE_60 + 4'b 0001, // index[262] ALERT_HANDLER_ALERT_CAUSE_61 + 4'b 0001, // index[263] ALERT_HANDLER_ALERT_CAUSE_62 + 4'b 0001, // index[264] ALERT_HANDLER_ALERT_CAUSE_63 + 4'b 0001, // index[265] ALERT_HANDLER_ALERT_CAUSE_64 + 4'b 0001, // index[266] ALERT_HANDLER_LOC_ALERT_REGWEN_0 + 4'b 0001, // index[267] ALERT_HANDLER_LOC_ALERT_REGWEN_1 + 4'b 0001, // index[268] ALERT_HANDLER_LOC_ALERT_REGWEN_2 + 4'b 0001, // index[269] ALERT_HANDLER_LOC_ALERT_REGWEN_3 + 4'b 0001, // index[270] ALERT_HANDLER_LOC_ALERT_REGWEN_4 + 4'b 0001, // index[271] ALERT_HANDLER_LOC_ALERT_REGWEN_5 + 4'b 0001, // index[272] ALERT_HANDLER_LOC_ALERT_REGWEN_6 + 4'b 0001, // index[273] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0 + 4'b 0001, // index[274] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1 + 4'b 0001, // index[275] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2 + 4'b 0001, // index[276] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3 + 4'b 0001, // index[277] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4 + 4'b 0001, // index[278] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5 + 4'b 0001, // index[279] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6 + 4'b 0001, // index[280] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0 + 4'b 0001, // index[281] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1 + 4'b 0001, // index[282] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2 + 4'b 0001, // index[283] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3 + 4'b 0001, // index[284] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4 + 4'b 0001, // index[285] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5 + 4'b 0001, // index[286] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6 + 4'b 0001, // index[287] ALERT_HANDLER_LOC_ALERT_CAUSE_0 + 4'b 0001, // index[288] ALERT_HANDLER_LOC_ALERT_CAUSE_1 + 4'b 0001, // index[289] ALERT_HANDLER_LOC_ALERT_CAUSE_2 + 4'b 0001, // index[290] ALERT_HANDLER_LOC_ALERT_CAUSE_3 + 4'b 0001, // index[291] ALERT_HANDLER_LOC_ALERT_CAUSE_4 + 4'b 0001, // index[292] ALERT_HANDLER_LOC_ALERT_CAUSE_5 + 4'b 0001, // index[293] ALERT_HANDLER_LOC_ALERT_CAUSE_6 + 4'b 0001, // index[294] ALERT_HANDLER_CLASSA_REGWEN + 4'b 0011, // index[295] ALERT_HANDLER_CLASSA_CTRL_SHADOWED + 4'b 0001, // index[296] ALERT_HANDLER_CLASSA_CLR_REGWEN + 4'b 0001, // index[297] ALERT_HANDLER_CLASSA_CLR_SHADOWED + 4'b 0011, // index[298] ALERT_HANDLER_CLASSA_ACCUM_CNT + 4'b 0011, // index[299] ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED + 4'b 1111, // index[300] ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED + 4'b 0001, // index[301] ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED + 4'b 1111, // index[302] ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED + 4'b 1111, // index[303] ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED + 4'b 1111, // index[304] ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED + 4'b 1111, // index[305] ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED + 4'b 1111, // index[306] ALERT_HANDLER_CLASSA_ESC_CNT + 4'b 0001, // index[307] ALERT_HANDLER_CLASSA_STATE + 4'b 0001, // index[308] ALERT_HANDLER_CLASSB_REGWEN + 4'b 0011, // index[309] ALERT_HANDLER_CLASSB_CTRL_SHADOWED + 4'b 0001, // index[310] ALERT_HANDLER_CLASSB_CLR_REGWEN + 4'b 0001, // index[311] ALERT_HANDLER_CLASSB_CLR_SHADOWED + 4'b 0011, // index[312] ALERT_HANDLER_CLASSB_ACCUM_CNT + 4'b 0011, // index[313] ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED + 4'b 1111, // index[314] ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED + 4'b 0001, // index[315] ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED + 4'b 1111, // index[316] ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED + 4'b 1111, // index[317] ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED + 4'b 1111, // index[318] ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED + 4'b 1111, // index[319] ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED + 4'b 1111, // index[320] ALERT_HANDLER_CLASSB_ESC_CNT + 4'b 0001, // index[321] ALERT_HANDLER_CLASSB_STATE + 4'b 0001, // index[322] ALERT_HANDLER_CLASSC_REGWEN + 4'b 0011, // index[323] ALERT_HANDLER_CLASSC_CTRL_SHADOWED + 4'b 0001, // index[324] ALERT_HANDLER_CLASSC_CLR_REGWEN + 4'b 0001, // index[325] ALERT_HANDLER_CLASSC_CLR_SHADOWED + 4'b 0011, // index[326] ALERT_HANDLER_CLASSC_ACCUM_CNT + 4'b 0011, // index[327] ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED + 4'b 1111, // index[328] ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED + 4'b 0001, // index[329] ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED + 4'b 1111, // index[330] ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED + 4'b 1111, // index[331] ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED + 4'b 1111, // index[332] ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED + 4'b 1111, // index[333] ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED + 4'b 1111, // index[334] ALERT_HANDLER_CLASSC_ESC_CNT + 4'b 0001, // index[335] ALERT_HANDLER_CLASSC_STATE + 4'b 0001, // index[336] ALERT_HANDLER_CLASSD_REGWEN + 4'b 0011, // index[337] ALERT_HANDLER_CLASSD_CTRL_SHADOWED + 4'b 0001, // index[338] ALERT_HANDLER_CLASSD_CLR_REGWEN + 4'b 0001, // index[339] ALERT_HANDLER_CLASSD_CLR_SHADOWED + 4'b 0011, // index[340] ALERT_HANDLER_CLASSD_ACCUM_CNT + 4'b 0011, // index[341] ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED + 4'b 1111, // index[342] ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED + 4'b 0001, // index[343] ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED + 4'b 1111, // index[344] ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED + 4'b 1111, // index[345] ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED + 4'b 1111, // index[346] ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED + 4'b 1111, // index[347] ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED + 4'b 1111, // index[348] ALERT_HANDLER_CLASSD_ESC_CNT + 4'b 0001 // index[349] ALERT_HANDLER_CLASSD_STATE + }; + +endpackage diff --git a/src/caliptra_ss_lc_ctrl/rtl/caliptra_ss_lc_ctrl.sv b/src/caliptra_ss_lc_ctrl/rtl/caliptra_ss_lc_ctrl.sv new file mode 100644 index 0000000..42ffa30 --- /dev/null +++ b/src/caliptra_ss_lc_ctrl/rtl/caliptra_ss_lc_ctrl.sv @@ -0,0 +1,991 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Life cycle controller top. +// + +`include "caliptra_prim_assert.sv" + +module caliptra_ss_lc_ctrl + import caliptra_ss_lc_ctrl_pkg::*; + import caliptra_ss_lc_ctrl_reg_pkg::*; + import caliptra_ss_lc_ctrl_state_pkg::*; + import axi_pkg::*; + import kmac_pkg::*; +#( + // Enable asynchronous transitions on alerts. + parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}}, + // Hardware revision numbers exposed in the CSRs. + parameter logic [SiliconCreatorIdWidth-1:0] SiliconCreatorId = '0, + parameter logic [ProductIdWidth-1:0] ProductId = '0, + parameter logic [RevisionIdWidth-1:0] RevisionId = '0, + // Idcode value for the JTAG. + parameter logic [31:0] IdcodeValue = 32'h00000001, + parameter bit UseDmiInterface = 1'b0, + // Random netlist constants + parameter caliptra_ss_lc_keymgr_div_t RndCnstLcKeymgrDivInvalid = LcKeymgrDivWidth'(0), + parameter caliptra_ss_lc_keymgr_div_t RndCnstLcKeymgrDivTestUnlocked = LcKeymgrDivWidth'(1), + parameter caliptra_ss_lc_keymgr_div_t RndCnstLcKeymgrDivDev = LcKeymgrDivWidth'(2), + parameter caliptra_ss_lc_keymgr_div_t RndCnstLcKeymgrDivProduction = LcKeymgrDivWidth'(3), + parameter caliptra_ss_lc_keymgr_div_t RndCnstLcKeymgrDivRma = LcKeymgrDivWidth'(4), + parameter caliptra_ss_lc_token_mux_t RndCnstInvalidTokens = {TokenMuxBits{1'b1}}, + parameter bit SecVolatileRawUnlockEn = 0 +) ( + // Life cycle controller clock + input clk_i, + input rst_ni, + // Clock for KMAC interface + // input clk_kmac_i, + // input rst_kmac_ni, + // // Bus Interface (device) + // input tlul_pkg::tl_h2d_t tl_i, + // output tlul_pkg::tl_d2h_t tl_o, + + input axi_struct_pkg::axi_wr_req_t axi_wr_req, + output axi_struct_pkg::axi_wr_rsp_t axi_wr_rsp, + input axi_struct_pkg::axi_rd_req_t axi_rd_req, + output axi_struct_pkg::axi_rd_rsp_t axi_rd_rsp, + + input tlul_pkg::tl_h2d_t dmi_tl_i, + output tlul_pkg::tl_d2h_t dmi_tl_o, + + // // AXI interface (device) + // axi_if.w_sub s_caliptra_ss_lc_axi_w_if, + // axi_if.r_sub s_caliptra_ss_lc_axi_r_if, + + // JTAG TAP. + input jtag_pkg::jtag_req_t jtag_i, + output jtag_pkg::jtag_rsp_t jtag_o, + // This bypasses the clock inverter inside the JTAG TAP for scanmmode. + input scan_rst_ni, + input caliptra_prim_mubi_pkg::mubi4_t scanmode_i, + // Alert outputs. + input caliptra_prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i, + output caliptra_prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o, + // Escalation inputs (severity 1 and 2). + // These need not be synchronized since the alert handler is + // in the same clock domain as the LC controller. + input caliptra_prim_esc_pkg::esc_rx_t esc_scrap_state0_tx_i, + output caliptra_prim_esc_pkg::esc_tx_t esc_scrap_state0_rx_o, + input caliptra_prim_esc_pkg::esc_rx_t esc_scrap_state1_tx_i, + output caliptra_prim_esc_pkg::esc_tx_t esc_scrap_state1_rx_o, + // Power manager interface (inputs are synced to lifecycle clock domain). + input pwrmgr_pkg::pwr_caliptra_ss_lc_req_t pwr_caliptra_ss_lc_i, + output pwrmgr_pkg::pwr_caliptra_ss_lc_rsp_t pwr_caliptra_ss_lc_o, + // Strap sampling override that is only used when SecVolatileRawUnlockEn = 1, + // Otherwise this output is tied off to 0. + output logic strap_en_override_o, + // Strap override - this is only used when + // Macro-specific test registers going to lifecycle TAP + output otp_ctrl_pkg::caliptra_ss_lc_otp_vendor_test_req_t caliptra_ss_lc_otp_vendor_test_o, + input otp_ctrl_pkg::caliptra_ss_lc_otp_vendor_test_rsp_t caliptra_ss_lc_otp_vendor_test_i, + // Life cycle transition command interface. + // No sync required since LC and OTP are in the same clock domain. + output otp_ctrl_pkg::caliptra_ss_lc_otp_program_req_t caliptra_ss_lc_otp_program_o, + input otp_ctrl_pkg::caliptra_ss_lc_otp_program_rsp_t caliptra_ss_lc_otp_program_i, + // Life cycle hashing interface for raw unlock + // Synchronized in the life cycle controller. + // SEC_CM: TOKEN.DIGEST + //-- input kmac_pkg::app_rsp_t kmac_data_i, + //-- output kmac_pkg::app_req_t kmac_data_o, + // OTP broadcast outputs + // No sync required since LC and OTP are in the same clock domain. + // SEC_CM: TOKEN_VALID.CTRL.MUBI + input otp_ctrl_pkg::otp_caliptra_ss_lc_data_t otp_caliptra_ss_lc_data_i, + // Life cycle broadcast outputs (all of them are registered). + // SEC_CM: INTERSIG.MUBI + output caliptra_ss_lc_tx_t caliptra_ss_lc_dft_en_o, + output caliptra_ss_lc_tx_t caliptra_ss_lc_nvm_debug_en_o, + output caliptra_ss_lc_tx_t caliptra_ss_lc_hw_debug_en_o, + output caliptra_ss_lc_tx_t caliptra_ss_lc_cpu_en_o, + output caliptra_ss_lc_tx_t caliptra_ss_lc_creator_seed_sw_rw_en_o, + output caliptra_ss_lc_tx_t caliptra_ss_lc_owner_seed_sw_rw_en_o, + output caliptra_ss_lc_tx_t caliptra_ss_lc_iso_part_sw_rd_en_o, + output caliptra_ss_lc_tx_t caliptra_ss_lc_iso_part_sw_wr_en_o, + output caliptra_ss_lc_tx_t caliptra_ss_lc_seed_hw_rd_en_o, + output caliptra_ss_lc_tx_t caliptra_ss_lc_keymgr_en_o, + output caliptra_ss_lc_tx_t caliptra_ss_lc_escalate_en_o, + output caliptra_ss_lc_tx_t caliptra_ss_lc_check_byp_en_o, + // Request and feedback to/from clock manager and AST. + // The ack is synced to the lc clock domain using prim_caliptra_ss_lc_sync. + // SEC_CM: INTERSIG.MUBI + output caliptra_ss_lc_tx_t caliptra_ss_lc_clk_byp_req_o, + input caliptra_ss_lc_tx_t caliptra_ss_lc_clk_byp_ack_i, + // Request and feedback to/from flash controller. + // The ack is synced to the lc clock domain using prim_caliptra_ss_lc_sync. + output caliptra_ss_lc_flash_rma_seed_t caliptra_ss_lc_flash_rma_seed_o, + // SEC_CM: INTERSIG.MUBI + output caliptra_ss_lc_tx_t caliptra_ss_lc_flash_rma_req_o, + input caliptra_ss_lc_tx_t [NumRmaAckSigs-1:0] caliptra_ss_lc_flash_rma_ack_i, + // State group diversification value for keymgr. + output caliptra_ss_lc_keymgr_div_t caliptra_ss_lc_keymgr_div_o, + // Hardware config input, needed for the DEVICE_ID field. + input otp_ctrl_pkg::otp_device_id_t otp_device_id_i, + // Hardware config input, needed for the MANUF_STATE field. + input otp_ctrl_pkg::otp_device_id_t otp_manuf_state_i, + // Hardware revision output (static) + output caliptra_ss_lc_hw_rev_t hw_rev_o +); + + import caliptra_prim_mubi_pkg::mubi8_t; + import caliptra_prim_mubi_pkg::MuBi8False; + import caliptra_prim_mubi_pkg::mubi8_test_true_strict; + import caliptra_prim_mubi_pkg::mubi8_test_false_loose; + + // AXI2TLUL interface signals + tlul_pkg::tl_h2d_t regs_tl_i; + tlul_pkg::tl_d2h_t regs_tl_o; + + axi_if axi_if( + .clk(clk_i), + .rst_n(rst_ni) + ); + + assign axi_if.awaddr = axi_wr_req.awaddr; + assign axi_if.awburst = axi_wr_req.awburst; + assign axi_if.awsize = axi_wr_req.awsize; + assign axi_if.awlen = axi_wr_req.awlen; + assign axi_if.awuser = axi_wr_req.awuser; + assign axi_if.awid = axi_wr_req.awid; + assign axi_if.awlock = axi_wr_req.awlock; + assign axi_if.awvalid = axi_wr_req.awvalid; + assign axi_wr_rsp.awready = axi_if.awready; + + assign axi_if.wdata = axi_wr_req.wdata; + assign axi_if.wstrb = axi_wr_req.wstrb; + assign axi_if.wlast = axi_wr_req.wlast; + assign axi_if.wvalid = axi_wr_req.wvalid; + assign axi_wr_rsp.wready = axi_if.wready; + + assign axi_wr_rsp.bresp = axi_if.bresp; + assign axi_wr_rsp.bid = axi_if.bid; + assign axi_wr_rsp.bvalid = axi_if.bvalid; + assign axi_if.bready = axi_wr_req.bready; + + assign axi_if.araddr = axi_rd_req.araddr; + assign axi_if.arburst = axi_rd_req.arburst; + assign axi_if.arsize = axi_rd_req.arsize; + assign axi_if.arlen = axi_rd_req.arlen; + assign axi_if.aruser = axi_rd_req.aruser; + assign axi_if.arid = axi_rd_req.arid; + assign axi_if.arlock = axi_rd_req.arlock; + assign axi_if.arvalid = axi_rd_req.arvalid; + assign axi_rd_rsp.arready = axi_if.arready; + + assign axi_rd_rsp.rdata = axi_if.rdata; + assign axi_rd_rsp.rresp = axi_if.rresp; + assign axi_rd_rsp.rid = axi_if.rid; + assign axi_rd_rsp.rlast = axi_if.rlast; + assign axi_rd_rsp.rvalid = axi_if.rvalid; + assign axi_if.rready = axi_rd_req.rready; + + // AXI2TLUL instance + axi2tlul #( + .AW (32), + .DW (32), + .UW (32), + .IW (8 ) + ) u_caliptra_ss_lc_axi2tlul ( + .clk (clk_i), + .rst_n (rst_ni), + .s_axi_w_if (axi_if.w_sub), + .s_axi_r_if (axi_if.r_sub), + .tl_o (regs_tl_i), + .tl_i (regs_tl_o) + ); + + //////////////////////// + // Integration Checks // + //////////////////////// + + // Check that the CSR parameters correspond with the ones used in the design. + `CALIPTRA_ASSERT_INIT(DecLcStateWidthCheck_A, CsrLcStateWidth == ExtDecLcStateWidth) + `CALIPTRA_ASSERT_INIT(DecLcCountWidthCheck_A, CsrLcCountWidth == DecLcCountWidth) + `CALIPTRA_ASSERT_INIT(DecLcIdStateWidthCheck_A, CsrLcIdStateWidth == ExtDecLcIdStateWidth) + `CALIPTRA_ASSERT_INIT(NumTokenWordsCheck_A, NumTokenWords == LcTokenWidth/32) + `CALIPTRA_ASSERT_INIT(OtpTestCtrlWidth_A, otp_ctrl_pkg::OtpTestCtrlWidth == CsrOtpTestCtrlWidth) + + ///////////// + // Regfile // + ///////////// + + caliptra_ss_lc_ctrl_reg_pkg::caliptra_ss_lc_ctrl_regs_reg2hw_t reg2hw; + caliptra_ss_lc_ctrl_reg_pkg::caliptra_ss_lc_ctrl_regs_hw2reg_t hw2reg; + + // SEC_CM: TRANSITION.CONFIG.REGWEN, STATE.CONFIG.SPARSE + logic fatal_bus_integ_error_q, fatal_bus_integ_error_csr_d, fatal_bus_integ_error_tap_dmi_d; + caliptra_ss_lc_ctrl_regs_reg_top u_reg_regs ( + .clk_i, + .rst_ni, + .tl_i ( regs_tl_i ), + .tl_o ( regs_tl_o ), + .reg2hw ( reg2hw ), + .hw2reg ( hw2reg ), + // SEC_CM: BUS.INTEGRITY + .intg_err_o( fatal_bus_integ_error_csr_d ) + ); + + ///////////////////////////// + // Life Cycle TAP/DMI Regs // + ///////////////////////////// + + caliptra_ss_lc_ctrl_reg_pkg::caliptra_ss_lc_ctrl_regs_reg2hw_t tap_dmi_reg2hw; + caliptra_ss_lc_ctrl_reg_pkg::caliptra_ss_lc_ctrl_regs_hw2reg_t tap_dmi_hw2reg; + + tlul_pkg::tl_h2d_t tap_dmi_tl_h2d; + tlul_pkg::tl_d2h_t tap_dmi_tl_d2h; + tlul_pkg::tl_h2d_t tap_tl_h2d; + tlul_pkg::tl_d2h_t tap_tl_d2h; + + // Statically mux DMI TLUL port and the one coming from the JTAG TAP + if (UseDmiInterface) begin : gen_dmi_tlul_ports + assign tap_dmi_tl_h2d = dmi_tl_i; + assign dmi_tl_o = tap_dmi_tl_d2h; + end else begin : gen_tap_tlul_ports + assign tap_dmi_tl_h2d = tap_tl_h2d; + assign tap_tl_d2h = tap_dmi_tl_d2h; + // Tie-off other port + assign dmi_tl_o = tlul_pkg::TL_D2H_DEFAULT; + logic unused_signal; + assign unused_signal = ^{dmi_tl_i}; + end + + caliptra_ss_lc_ctrl_regs_reg_top u_reg_tap_dmi ( + .clk_i, + .rst_ni, + .tl_i ( tap_dmi_tl_h2d ), + .tl_o ( tap_dmi_tl_d2h ), + .reg2hw ( tap_dmi_reg2hw ), + .hw2reg ( tap_dmi_hw2reg ), + // SEC_CM: BUS.INTEGRITY + // While the TAP does not have bus integrity, it does have a WE checker + // that feeds into intg_err_o - hence this is wired up to the fatal_bus_integ_error. + .intg_err_o( fatal_bus_integ_error_tap_dmi_d ) + ); + + if (!UseDmiInterface) begin : gen_tap_tlul + // This reuses the JTAG DTM and DMI from the RISC-V external + // debug v0.13 specification to read and write the caliptra_ss_lc_ctrl CSRs: + // https://github.com/riscv/riscv-debug-spec/blob/release/riscv-debug-release.pdf + // The register addresses correspond to the byte offsets of the caliptra_ss_lc_ctrl CSRs, divided by 4. + // Note that the DMI reset does not affect the LC controller in any way. + dm::dmi_req_t dmi_req; + logic dmi_req_valid; + logic dmi_req_ready; + dm::dmi_resp_t dmi_resp; + logic dmi_resp_ready; + logic dmi_resp_valid; + + logic scanmode; + caliptra_prim_mubi4_dec u_prim_mubi4_dec ( + .mubi_i(scanmode_i), + .mubi_dec_o(scanmode) + ); + + logic tck_muxed; + logic trst_n_muxed; + caliptra_prim_clock_mux2 #( + .NoFpgaBufG(1'b1) + ) u_prim_clock_mux2 ( + .clk0_i(jtag_i.tck), + .clk1_i(clk_i), + .sel_i (scanmode), + .clk_o (tck_muxed) + ); + + caliptra_prim_clock_mux2 #( + .NoFpgaBufG(1'b1) + ) u_prim_rst_n_mux2 ( + .clk0_i(jtag_i.trst_n), + .clk1_i(scan_rst_ni), + .sel_i (scanmode), + .clk_o (trst_n_muxed) + ); + + logic req_ready; + assign req_ready = dmi_req_ready & dmi_resp_ready; + dmi_jtag #( + .IdcodeValue(IdcodeValue), + .NumDmiWordAbits(7) + ) u_dmi_jtag ( + .clk_i, + .rst_ni, + .testmode_i ( scanmode ), + .test_rst_ni ( scan_rst_ni ), + .dmi_rst_no ( ), // unused + .dmi_req_o ( dmi_req ), + .dmi_req_valid_o ( dmi_req_valid ), + // unless there is room for response, stall + .dmi_req_ready_i ( req_ready ), + .dmi_resp_i ( dmi_resp ), + .dmi_resp_ready_o ( dmi_resp_ready ), + .dmi_resp_valid_i ( dmi_resp_valid ), + .tck_i ( tck_muxed ), + .tms_i ( jtag_i.tms ), + .trst_ni ( trst_n_muxed ), + .td_i ( jtag_i.tdi ), + .td_o ( jtag_o.tdo ), + .tdo_oe_o ( jtag_o.tdo_oe ) + ); + + // DMI to TL-UL transducing + tlul_adapter_host #( + .EnableDataIntgGen(1) + ) u_tap_tlul_host ( + .clk_i, + .rst_ni, + // do not make a request unless there is room for the response + .req_i ( dmi_req_valid & dmi_resp_ready ), + .gnt_o ( dmi_req_ready ), + .addr_i ( top_pkg::TL_AW'({dmi_req.addr, 2'b00}) ), + .we_i ( dmi_req.op == dm::DTM_WRITE ), + .wdata_i ( dmi_req.data ), + .wdata_intg_i ('0 ), + .be_i ( {top_pkg::TL_DBW{1'b1}} ), + .user_rsvd_i ('0 ), + .instr_type_i ( caliptra_prim_mubi_pkg::MuBi4False ), + .valid_o ( dmi_resp_valid ), + .rdata_o ( dmi_resp.data ), + .rdata_intg_o ( ), + .err_o ( ), + .intg_err_o ( ), + .tl_o ( tap_tl_h2d ), + .tl_i ( tap_tl_d2h ) + ); + + // TL-UL to DMI transducing + assign dmi_resp.resp = '0; // unused inside dmi_jtag + + // These signals are unused + logic unused_tap_tl_d2h; + assign unused_tap_tl_d2h = ^{ + dmi_req.addr[31:30], + tap_tl_d2h.d_opcode, + tap_tl_d2h.d_param, + tap_tl_d2h.d_size, + tap_tl_d2h.d_source, + tap_tl_d2h.d_sink, + tap_tl_d2h.d_user, + tap_tl_d2h.d_error + }; + end else begin : gen_dmi_tlul + // No scan chain needed in the DMI configuration + logic unused_signals; + assign unused_signals = ^{scan_rst_ni, scanmode_i}; + end + + /////////////////////////////////////// + // Transition Interface and HW Mutex // + /////////////////////////////////////// + + // All registers are HWext + logic trans_success_d, trans_success_q; + logic trans_cnt_oflw_error_d, trans_cnt_oflw_error_q; + logic trans_invalid_error_d, trans_invalid_error_q; + logic token_invalid_error_d, token_invalid_error_q; + logic flash_rma_error_d, flash_rma_error_q; + logic otp_prog_error_d, fatal_prog_error_q; + logic state_invalid_error_d, fatal_state_error_q; + logic otp_part_error_q; + mubi8_t sw_claim_transition_if_d, sw_claim_transition_if_q; + mubi8_t tap_dmi_claim_transition_if_d, tap_dmi_claim_transition_if_q; + logic transition_cmd; + caliptra_ss_lc_token_t transition_token_d, transition_token_q; + ext_dec_caliptra_ss_lc_state_t transition_target_d, transition_target_q; + // No need to register these. + ext_dec_caliptra_ss_lc_state_t dec_caliptra_ss_lc_state; + dec_caliptra_ss_lc_cnt_t dec_caliptra_ss_lc_cnt; + dec_caliptra_ss_lc_id_state_e dec_caliptra_ss_lc_id_state; + + logic caliptra_ss_lc_idle_d, caliptra_ss_lc_done_d; + + // Assign hardware revision output + assign hw_rev_o = '{silicon_creator_id: SiliconCreatorId, + product_id: ProductId, + revision_id: RevisionId, + reserved: '0}; + + // OTP Vendor control bits + logic ext_clock_switched; + logic use_ext_clock_d, use_ext_clock_q; + logic volatile_raw_unlock_d, volatile_raw_unlock_q; + logic [CsrOtpTestCtrlWidth-1:0] otp_vendor_test_ctrl_d, otp_vendor_test_ctrl_q; + logic [CsrOtpTestStatusWidth-1:0] otp_vendor_test_status; + + always_comb begin : p_csr_assign_outputs + hw2reg = '0; + hw2reg.status.initialized = caliptra_ss_lc_done_d; + hw2reg.status.ready = caliptra_ss_lc_idle_d; + hw2reg.status.ext_clock_switched = ext_clock_switched; + hw2reg.status.transition_successful = trans_success_q; + hw2reg.status.transition_count_error = trans_cnt_oflw_error_q; + hw2reg.status.transition_error = trans_invalid_error_q; + hw2reg.status.token_error = token_invalid_error_q; + hw2reg.status.flash_rma_error = flash_rma_error_q; + hw2reg.status.otp_error = fatal_prog_error_q; + hw2reg.status.state_error = fatal_state_error_q; + hw2reg.status.otp_partition_error = otp_part_error_q; + hw2reg.status.bus_integ_error = fatal_bus_integ_error_q; + hw2reg.caliptra_ss_lc_state = dec_caliptra_ss_lc_state; + hw2reg.caliptra_ss_lc_transition_cnt = dec_caliptra_ss_lc_cnt; + hw2reg.caliptra_ss_lc_id_state = {DecLcIdStateNumRep{dec_caliptra_ss_lc_id_state}}; + hw2reg.device_id = otp_device_id_i; + hw2reg.manuf_state = otp_manuf_state_i; + hw2reg.hw_revision0.silicon_creator_id = hw_rev_o.silicon_creator_id; + hw2reg.hw_revision0.product_id = hw_rev_o.product_id; + hw2reg.hw_revision1.revision_id = hw_rev_o.revision_id; + hw2reg.hw_revision1.reserved = '0; + + // The assignments above are identical for the TAP/DMI. + tap_dmi_hw2reg = hw2reg; + + // Assignments gated by mutex. Again, the DMI has priority. + tap_dmi_hw2reg.claim_transition_if = tap_dmi_claim_transition_if_q; + hw2reg.claim_transition_if = sw_claim_transition_if_q; + if (mubi8_test_true_strict(tap_dmi_claim_transition_if_q)) begin + tap_dmi_hw2reg.transition_ctrl.ext_clock_en = use_ext_clock_q; + tap_dmi_hw2reg.transition_ctrl.volatile_raw_unlock = volatile_raw_unlock_q; + tap_dmi_hw2reg.transition_token = transition_token_q; + tap_dmi_hw2reg.transition_target = transition_target_q; + // SEC_CM: TRANSITION.CONFIG.REGWEN + tap_dmi_hw2reg.transition_regwen = caliptra_ss_lc_idle_d; + tap_dmi_hw2reg.otp_vendor_test_ctrl = otp_vendor_test_ctrl_q; + tap_dmi_hw2reg.otp_vendor_test_status = otp_vendor_test_status; + end else if (mubi8_test_true_strict(sw_claim_transition_if_q)) begin + hw2reg.transition_ctrl.ext_clock_en = use_ext_clock_q; + hw2reg.transition_ctrl.volatile_raw_unlock = volatile_raw_unlock_q; + hw2reg.transition_token = transition_token_q; + hw2reg.transition_target = transition_target_q; + // SEC_CM: TRANSITION.CONFIG.REGWEN + hw2reg.transition_regwen = caliptra_ss_lc_idle_d; + hw2reg.otp_vendor_test_ctrl = otp_vendor_test_ctrl_q; + hw2reg.otp_vendor_test_status = otp_vendor_test_status; + end + end + + always_comb begin : p_csr_assign_inputs + sw_claim_transition_if_d = sw_claim_transition_if_q; + tap_dmi_claim_transition_if_d = tap_dmi_claim_transition_if_q; + transition_token_d = transition_token_q; + transition_target_d = transition_target_q; + transition_cmd = 1'b0; + otp_vendor_test_ctrl_d = otp_vendor_test_ctrl_q; + use_ext_clock_d = use_ext_clock_q; + volatile_raw_unlock_d = volatile_raw_unlock_q; + + // Note that the mutex claims from the TAP/DMI and SW side could arrive within the same cycle. + // In that case we give priority to the TAP/DMI mutex claim in order to avoid a race condition. + // TAP/DMI mutex claim. + if (mubi8_test_false_loose(sw_claim_transition_if_q) && + tap_dmi_reg2hw.claim_transition_if.qe) begin + tap_dmi_claim_transition_if_d = mubi8_t'(tap_dmi_reg2hw.claim_transition_if.q); + // SW mutex claim. + end else if (mubi8_test_false_loose(tap_dmi_claim_transition_if_q) && + reg2hw.claim_transition_if.qe) begin + sw_claim_transition_if_d = mubi8_t'(reg2hw.claim_transition_if.q); + end + + + // The idle signal serves as the REGWEN in this case. + if (caliptra_ss_lc_idle_d) begin + // The DMI has priority. + if (mubi8_test_true_strict(tap_dmi_claim_transition_if_q)) begin + transition_cmd = tap_dmi_reg2hw.transition_cmd.q & + tap_dmi_reg2hw.transition_cmd.qe; + + if (tap_dmi_reg2hw.transition_ctrl.ext_clock_en.qe) begin + use_ext_clock_d |= tap_dmi_reg2hw.transition_ctrl.ext_clock_en.q; + end + + // ---------- VOLATILE_TEST_UNLOCKED CODE SECTION START ---------- + // NOTE THAT THIS IS A FEATURE FOR TEST CHIPS ONLY TO MITIGATE + // THE RISK OF A BROKEN OTP MACRO. THIS WILL BE DISABLED VIA + // SecVolatileRawUnlockEn AT COMPILETIME FOR PRODUCTION DEVICES. + // --------------------------------------------------------------- + if (tap_dmi_reg2hw.transition_ctrl.volatile_raw_unlock.qe) begin + volatile_raw_unlock_d = tap_dmi_reg2hw.transition_ctrl.volatile_raw_unlock.q; + end + // ----------- VOLATILE_TEST_UNLOCKED CODE SECTION END ----------- + + for (int k = 0; k < LcTokenWidth/32; k++) begin + if (tap_dmi_reg2hw.transition_token[k].qe) begin + transition_token_d[k*32 +: 32] = tap_dmi_reg2hw.transition_token[k].q; + end + end + + if (tap_dmi_reg2hw.transition_target.qe) begin + for (int k = 0; k < DecLcStateNumRep; k++) begin + transition_target_d[k] = dec_caliptra_ss_lc_state_e'( + tap_dmi_reg2hw.transition_target.q[k*DecLcStateWidth +: DecLcStateWidth]); + end + end + + if (tap_dmi_reg2hw.otp_vendor_test_ctrl.qe) begin + otp_vendor_test_ctrl_d = tap_dmi_reg2hw.otp_vendor_test_ctrl.q; + end + end else if (mubi8_test_true_strict(sw_claim_transition_if_q)) begin + transition_cmd = reg2hw.transition_cmd.q & + reg2hw.transition_cmd.qe; + + if (reg2hw.transition_ctrl.ext_clock_en.qe) begin + use_ext_clock_d |= reg2hw.transition_ctrl.ext_clock_en.q; + end + + // ---------- VOLATILE_TEST_UNLOCKED CODE SECTION START ---------- + // NOTE THAT THIS IS A FEATURE FOR TEST CHIPS ONLY TO MITIGATE + // THE RISK OF A BROKEN OTP MACRO. THIS WILL BE DISABLED VIA + // SecVolatileRawUnlockEn AT COMPILETIME FOR PRODUCTION DEVICES. + // --------------------------------------------------------------- + if (reg2hw.transition_ctrl.volatile_raw_unlock.qe) begin + volatile_raw_unlock_d = reg2hw.transition_ctrl.volatile_raw_unlock.q; + end + // ----------- VOLATILE_TEST_UNLOCKED CODE SECTION END ----------- + + for (int k = 0; k < LcTokenWidth/32; k++) begin + if (reg2hw.transition_token[k].qe) begin + transition_token_d[k*32 +: 32] = reg2hw.transition_token[k].q; + end + end + + if (reg2hw.transition_target.qe) begin + for (int k = 0; k < DecLcStateNumRep; k++) begin + transition_target_d[k] = dec_caliptra_ss_lc_state_e'( + reg2hw.transition_target.q[k*DecLcStateWidth +: DecLcStateWidth]); + end + end + + if (reg2hw.otp_vendor_test_ctrl.qe) begin + otp_vendor_test_ctrl_d = reg2hw.otp_vendor_test_ctrl.q; + end + end + end + end + + always_ff @(posedge clk_i or negedge rst_ni) begin : p_csrs + if (!rst_ni) begin + trans_success_q <= 1'b0; + trans_cnt_oflw_error_q <= 1'b0; + trans_invalid_error_q <= 1'b0; + token_invalid_error_q <= 1'b0; + flash_rma_error_q <= 1'b0; + fatal_prog_error_q <= 1'b0; + fatal_state_error_q <= 1'b0; + sw_claim_transition_if_q <= MuBi8False; + tap_dmi_claim_transition_if_q <= MuBi8False; + transition_token_q <= '0; + transition_target_q <= {DecLcStateNumRep{DecLcStRaw}}; + otp_part_error_q <= 1'b0; + fatal_bus_integ_error_q <= 1'b0; + otp_vendor_test_ctrl_q <= '0; + use_ext_clock_q <= 1'b0; + end else begin + // ---------- VOLATILE_TEST_UNLOCKED CODE SECTION START ---------- + // NOTE THAT THIS IS A FEATURE FOR TEST CHIPS ONLY TO MITIGATE + // THE RISK OF A BROKEN OTP MACRO. THIS WILL BE DISABLED VIA + // SecVolatileRawUnlockEn AT COMPILETIME FOR PRODUCTION DEVICES. + // --------------------------------------------------------------- + // In case of a volatile RAW unlock, this bit has to be cleared when the volatile + // unlock is followed by a real transition. + // ----------- VOLATILE_TEST_UNLOCKED CODE SECTION END ----------- + if (SecVolatileRawUnlockEn && transition_cmd && !volatile_raw_unlock_q) begin + trans_success_q <= 1'b0; + end else begin + trans_success_q <= trans_success_d | trans_success_q; + end + // All other status and error bits are terminal and require a reset cycle. + trans_cnt_oflw_error_q <= trans_cnt_oflw_error_d | trans_cnt_oflw_error_q; + trans_invalid_error_q <= trans_invalid_error_d | trans_invalid_error_q; + token_invalid_error_q <= token_invalid_error_d | token_invalid_error_q; + flash_rma_error_q <= flash_rma_error_d | flash_rma_error_q; + fatal_prog_error_q <= otp_prog_error_d | fatal_prog_error_q; + fatal_state_error_q <= state_invalid_error_d | fatal_state_error_q; + otp_part_error_q <= otp_caliptra_ss_lc_data_i.error | otp_part_error_q; + fatal_bus_integ_error_q <= fatal_bus_integ_error_csr_d | + fatal_bus_integ_error_tap_dmi_d | + fatal_bus_integ_error_q; + // Other regs, gated by mutex further below. + sw_claim_transition_if_q <= sw_claim_transition_if_d; + tap_dmi_claim_transition_if_q <= tap_dmi_claim_transition_if_d; + transition_token_q <= transition_token_d; + transition_target_q <= transition_target_d; + otp_vendor_test_ctrl_q <= otp_vendor_test_ctrl_d; + use_ext_clock_q <= use_ext_clock_d; + end + end + + // ---------- VOLATILE_TEST_UNLOCKED CODE SECTION START ---------- + // NOTE THAT THIS IS A FEATURE FOR TEST CHIPS ONLY TO MITIGATE + // THE RISK OF A BROKEN OTP MACRO. THIS WILL BE DISABLED VIA + // SecVolatileRawUnlockEn AT COMPILETIME FOR PRODUCTION DEVICES. + // --------------------------------------------------------------- + // If not enabled, this register will become a constant. + if (SecVolatileRawUnlockEn) begin : gen_volatile_raw_unlock_reg + always_ff @(posedge clk_i or negedge rst_ni) begin : p_volatile_raw_unlock_reg + if (!rst_ni) begin + volatile_raw_unlock_q <= 1'b0; + end else begin + volatile_raw_unlock_q <= volatile_raw_unlock_d; + end + end + end else begin : gen_volatile_raw_unlock_const + logic unused_volatile_raw_unlock; + assign unused_volatile_raw_unlock = ^volatile_raw_unlock_d; + assign volatile_raw_unlock_q = 1'b0; + end + // ----------- VOLATILE_TEST_UNLOCKED CODE SECTION END ----------- + + assign caliptra_ss_lc_flash_rma_seed_o = transition_token_q[RmaSeedWidth-1:0]; + + // Gate the vendor specific test ctrl/status bits to zero in production states. + // Buffer the enable signal to prevent optimization of the multibit signal. + caliptra_ss_lc_tx_t caliptra_ss_lc_raw_test_rma; + caliptra_ss_lc_tx_t [1:0] caliptra_ss_lc_raw_test_rma_buf; + caliptra_prim_lc_sync #( + .NumCopies(2), + .AsyncOn(0) + ) u_prim_caliptra_ss_lc_sync ( + .clk_i, + .rst_ni, + .lc_en_i(caliptra_ss_lc_raw_test_rma), + .lc_en_o(caliptra_ss_lc_raw_test_rma_buf) + ); + + assign caliptra_ss_lc_otp_vendor_test_o.ctrl = (caliptra_ss_lc_tx_test_true_strict(caliptra_ss_lc_raw_test_rma_buf[0])) ? + otp_vendor_test_ctrl_q : '0; + assign otp_vendor_test_status = (caliptra_ss_lc_tx_test_true_strict(caliptra_ss_lc_raw_test_rma_buf[1])) ? + caliptra_ss_lc_otp_vendor_test_i.status : '0; + + ////////////////// + // Alert Sender // + ////////////////// + + logic [NumAlerts-1:0] alerts; + logic [NumAlerts-1:0] alert_test; + logic [NumAlerts-1:0] tap_dmi_alert_test; + + assign alerts = { + fatal_bus_integ_error_q, + fatal_state_error_q, + fatal_prog_error_q + }; + + assign alert_test = { + reg2hw.alert_test.fatal_bus_integ_error.q & + reg2hw.alert_test.fatal_bus_integ_error.qe, + reg2hw.alert_test.fatal_state_error.q & + reg2hw.alert_test.fatal_state_error.qe, + reg2hw.alert_test.fatal_prog_error.q & + reg2hw.alert_test.fatal_prog_error.qe + }; + + assign tap_dmi_alert_test = { + tap_dmi_reg2hw.alert_test.fatal_bus_integ_error.q & + tap_dmi_reg2hw.alert_test.fatal_bus_integ_error.qe, + tap_dmi_reg2hw.alert_test.fatal_state_error.q & + tap_dmi_reg2hw.alert_test.fatal_state_error.qe, + tap_dmi_reg2hw.alert_test.fatal_prog_error.q & + tap_dmi_reg2hw.alert_test.fatal_prog_error.qe + }; + + for (genvar k = 0; k < NumAlerts; k++) begin : gen_alert_tx + caliptra_prim_alert_sender #( + .AsyncOn(AlertAsyncOn[k]), + .IsFatal(1) + ) u_prim_alert_sender ( + .clk_i, + .rst_ni, + .alert_test_i ( alert_test[k] | + tap_dmi_alert_test[k] ), + .alert_req_i ( alerts[k] ), + .alert_ack_o ( ), + .alert_state_o ( ), + .alert_rx_i ( alert_rx_i[k] ), + .alert_tx_o ( alert_tx_o[k] ) + ); + end + + /////////////////////////////// + // KMAC design Instance + /////////////////////////////// + + kmac_pkg::app_rsp_t kmac_data_i; + kmac_pkg::app_req_t kmac_data_o; + wire caliptra_ss_lc_tx_t caliptra_ss_lc_escalate_en_int; + wire app_req_t [2:0] app_req; + wire app_rsp_t [2:0] app_rsp; + + assign caliptra_ss_lc_escalate_en_int = caliptra_ss_lc_escalate_en_o; + + assign app_req[0] = '0; + assign app_req[1] = kmac_data_o; + assign app_req[2] = '0; + + assign kmac_data_i = app_rsp[1]; + + kmac #( + .EnMasking(0), + .SwKeyMasked(0), + .NumAppIntf(3) + ) kmac ( + .clk_i, + .rst_ni, + .rst_shadowed_ni (rst_ni), + // TLUL interface + .tl_i ('0), + .tl_o ( ), + // alert interface + .alert_rx_i ('0), + .alert_tx_o ( ), + + // escalate en + .caliptra_ss_lc_escalate_en_i (caliptra_ss_lc_escalate_en_int), + + // KeyMgr sideload key interface + .keymgr_key_i ('0), + + // KeyMgr KDF datapath + .app_i ( app_req ), + .app_o ( app_rsp ), + + // Interrupts + .intr_kmac_done_o ( ), + .intr_fifo_empty_o ( ), + .intr_kmac_err_o ( ), + + // Idle interface + .idle_o ( ), + .en_masking_o ( ), + + // EDN interface + .clk_edn_i (clk_i), + .rst_edn_ni (rst_ni), + .entropy_o ( ), + .entropy_i ('0) + ); + + + ////////////////////////// + // Escalation Receivers // + ////////////////////////// + + // SEC_CM: MAIN.FSM.GLOBAL_ESC + // We still have two escalation receivers here for historical reasons. + // The two actions "wipe secrets" and "scrap lifecycle state" have been + // combined in order to simplify both DV and the design, as otherwise + // this separation of very intertwined actions would have caused too many + // unnecessary corner cases. The escalation receivers are now redundant and + // trigger both actions at once. + + // This escalation action moves the life cycle + // state into a temporary "SCRAP" state named "ESCALATE", + // and asserts the caliptra_ss_lc_escalate_en life cycle control signal. + logic esc_scrap_state0; + caliptra_prim_esc_receiver #( + .N_ESC_SEV (alert_handler_reg_pkg::N_ESC_SEV), + .PING_CNT_DW (alert_handler_reg_pkg::PING_CNT_DW) + ) u_prim_esc_receiver0 ( + .clk_i, + .rst_ni, + .esc_req_o (esc_scrap_state0), + .esc_rx_o (esc_scrap_state0_rx_o), + .esc_tx_i (esc_scrap_state0_tx_i) + ); + + // This escalation action moves the life cycle + // state into a temporary "SCRAP" state named "ESCALATE". + logic esc_scrap_state1; + caliptra_prim_esc_receiver #( + .N_ESC_SEV (alert_handler_reg_pkg::N_ESC_SEV), + .PING_CNT_DW (alert_handler_reg_pkg::PING_CNT_DW) + ) u_prim_esc_receiver1 ( + .clk_i, + .rst_ni, + .esc_req_o (esc_scrap_state1), + .esc_rx_o (esc_scrap_state1_rx_o), + .esc_tx_i (esc_scrap_state1_tx_i) + ); + + //////////////////////////// + // Synchronization of IOs // + //////////////////////////// + + // Signals going to and coming from power manager. + logic caliptra_ss_lc_init; + caliptra_prim_flop_2sync #( + .Width(1) + ) u_prim_flop_2sync_init ( + .clk_i, + .rst_ni, + .d_i(pwr_caliptra_ss_lc_i.caliptra_ss_lc_init), + .q_o(caliptra_ss_lc_init) + ); + + logic caliptra_ss_lc_done_q; + logic caliptra_ss_lc_idle_q; + + always_ff @(posedge clk_i or negedge rst_ni) begin : p_sync_regs + if (!rst_ni) begin + caliptra_ss_lc_done_q <= 1'b0; + caliptra_ss_lc_idle_q <= 1'b0; + end else begin + caliptra_ss_lc_done_q <= caliptra_ss_lc_done_d; + caliptra_ss_lc_idle_q <= caliptra_ss_lc_idle_d; + end + end + + assign pwr_caliptra_ss_lc_o.caliptra_ss_lc_done = caliptra_ss_lc_done_q; + assign pwr_caliptra_ss_lc_o.caliptra_ss_lc_idle = caliptra_ss_lc_idle_q; + + //////////////////// + // KMAC Interface // + //////////////////// + + logic token_hash_req, token_hash_req_chk, token_hash_ack, token_hash_err, token_if_fsm_err; + caliptra_ss_lc_token_t hashed_token; + caliptra_ss_lc_ctrl_kmac_if u_caliptra_ss_lc_ctrl_kmac_if ( + .clk_i, + .rst_ni, + .clk_kmac_i (clk_i), + .rst_kmac_ni (rst_ni), + .kmac_data_i, + .kmac_data_o, + .transition_token_i ( transition_token_q ), + .token_hash_req_i ( token_hash_req ), + .token_hash_req_chk_i ( token_hash_req_chk ), + .token_hash_ack_o ( token_hash_ack ), + .token_hash_err_o ( token_hash_err ), + .token_if_fsm_err_o ( token_if_fsm_err ), + .hashed_token_o ( hashed_token ) + ); + + //////////// + // LC FSM // + //////////// + + caliptra_ss_lc_ctrl_fsm #( + .RndCnstLcKeymgrDivInvalid ( RndCnstLcKeymgrDivInvalid ), + .RndCnstLcKeymgrDivTestUnlocked( RndCnstLcKeymgrDivTestUnlocked ), + .RndCnstLcKeymgrDivDev ( RndCnstLcKeymgrDivDev ), + .RndCnstLcKeymgrDivProduction ( RndCnstLcKeymgrDivProduction ), + .RndCnstLcKeymgrDivRma ( RndCnstLcKeymgrDivRma ), + .RndCnstInvalidTokens ( RndCnstInvalidTokens ), + .SecVolatileRawUnlockEn ( SecVolatileRawUnlockEn ) + ) u_caliptra_ss_lc_ctrl_fsm ( + .clk_i, + .rst_ni, + .init_req_i ( caliptra_ss_lc_init ), + .init_done_o ( caliptra_ss_lc_done_d ), + .idle_o ( caliptra_ss_lc_idle_d ), + .esc_scrap_state0_i ( esc_scrap_state0 ), + .esc_scrap_state1_i ( esc_scrap_state1 ), + .caliptra_ss_lc_state_valid_i ( otp_caliptra_ss_lc_data_i.valid ), + .caliptra_ss_lc_state_i ( caliptra_ss_lc_state_e'(otp_caliptra_ss_lc_data_i.state) ), + .secrets_valid_i ( otp_caliptra_ss_lc_data_i.secrets_valid ), + .caliptra_ss_lc_cnt_i ( caliptra_ss_lc_cnt_e'(otp_caliptra_ss_lc_data_i.count) ), + .use_ext_clock_i ( use_ext_clock_q ), + .ext_clock_switched_o ( ext_clock_switched ), + .volatile_raw_unlock_i ( volatile_raw_unlock_q ), + .strap_en_override_o, + .test_unlock_token_i ( otp_caliptra_ss_lc_data_i.test_unlock_token ), + .test_exit_token_i ( otp_caliptra_ss_lc_data_i.test_exit_token ), + .test_tokens_valid_i ( otp_caliptra_ss_lc_data_i.test_tokens_valid ), + .rma_token_i ( otp_caliptra_ss_lc_data_i.rma_token ), + .rma_token_valid_i ( otp_caliptra_ss_lc_data_i.rma_token_valid ), + .trans_cmd_i ( transition_cmd ), + .trans_target_i ( transition_target_q ), + .dec_caliptra_ss_lc_state_o ( dec_caliptra_ss_lc_state ), + .dec_caliptra_ss_lc_cnt_o ( dec_caliptra_ss_lc_cnt ), + .dec_caliptra_ss_lc_id_state_o ( dec_caliptra_ss_lc_id_state ), + .token_hash_req_o ( token_hash_req ), + .token_hash_req_chk_o ( token_hash_req_chk ), + .token_hash_ack_i ( token_hash_ack ), + .token_hash_err_i ( token_hash_err ), + .token_if_fsm_err_i ( token_if_fsm_err ), + .hashed_token_i ( hashed_token ), + .unhashed_token_i ( transition_token_q ), + .otp_prog_req_o ( caliptra_ss_lc_otp_program_o.req ), + .otp_prog_caliptra_ss_lc_state_o ( caliptra_ss_lc_otp_program_o.state ), + .otp_prog_caliptra_ss_lc_cnt_o ( caliptra_ss_lc_otp_program_o.count ), + .otp_prog_ack_i ( caliptra_ss_lc_otp_program_i.ack ), + .otp_prog_err_i ( caliptra_ss_lc_otp_program_i.err ), + .trans_success_o ( trans_success_d ), + .trans_cnt_oflw_error_o ( trans_cnt_oflw_error_d ), + .trans_invalid_error_o ( trans_invalid_error_d ), + .token_invalid_error_o ( token_invalid_error_d ), + .flash_rma_error_o ( flash_rma_error_d ), + .otp_prog_error_o ( otp_prog_error_d ), + .state_invalid_error_o ( state_invalid_error_d ), + .caliptra_ss_lc_raw_test_rma_o ( caliptra_ss_lc_raw_test_rma ), + .caliptra_ss_lc_dft_en_o, + .caliptra_ss_lc_nvm_debug_en_o, + .caliptra_ss_lc_hw_debug_en_o, + .caliptra_ss_lc_cpu_en_o, + .caliptra_ss_lc_creator_seed_sw_rw_en_o, + .caliptra_ss_lc_owner_seed_sw_rw_en_o, + .caliptra_ss_lc_iso_part_sw_rd_en_o, + .caliptra_ss_lc_iso_part_sw_wr_en_o, + .caliptra_ss_lc_seed_hw_rd_en_o, + .caliptra_ss_lc_keymgr_en_o, + .caliptra_ss_lc_escalate_en_o, + .caliptra_ss_lc_check_byp_en_o, + .caliptra_ss_lc_clk_byp_req_o, + .caliptra_ss_lc_clk_byp_ack_i, + .caliptra_ss_lc_flash_rma_req_o, + .caliptra_ss_lc_flash_rma_ack_i, + .caliptra_ss_lc_keymgr_div_o + ); + + //////////////// + // Assertions // + //////////////// + + `CALIPTRA_ASSERT_KNOWN(RegsTlOKnown, regs_tl_o ) + `CALIPTRA_ASSERT_KNOWN(DmiTlOKnown, dmi_tl_o ) + `CALIPTRA_ASSERT_KNOWN(AlertTxKnown_A, alert_tx_o ) + `CALIPTRA_ASSERT_KNOWN(PwrLcKnown_A, pwr_caliptra_ss_lc_o ) + `CALIPTRA_ASSERT_KNOWN(LcOtpProgramKnown_A, caliptra_ss_lc_otp_program_o ) + `CALIPTRA_ASSERT_KNOWN(LcOtpTokenKnown_A, kmac_data_o ) + `CALIPTRA_ASSERT_KNOWN(LcDftEnKnown_A, caliptra_ss_lc_dft_en_o ) + `CALIPTRA_ASSERT_KNOWN(LcNvmDebugEnKnown_A, caliptra_ss_lc_nvm_debug_en_o ) + `CALIPTRA_ASSERT_KNOWN(LcHwDebugEnKnown_A, caliptra_ss_lc_hw_debug_en_o ) + `CALIPTRA_ASSERT_KNOWN(LcCpuEnKnown_A, caliptra_ss_lc_cpu_en_o ) + `CALIPTRA_ASSERT_KNOWN(LcCreatorSwRwEn_A, caliptra_ss_lc_creator_seed_sw_rw_en_o ) + `CALIPTRA_ASSERT_KNOWN(LcOwnerSwRwEn_A, caliptra_ss_lc_owner_seed_sw_rw_en_o ) + `CALIPTRA_ASSERT_KNOWN(LcIsoSwRwEn_A, caliptra_ss_lc_iso_part_sw_rd_en_o ) + `CALIPTRA_ASSERT_KNOWN(LcIsoSwWrEn_A, caliptra_ss_lc_iso_part_sw_wr_en_o ) + `CALIPTRA_ASSERT_KNOWN(LcSeedHwRdEn_A, caliptra_ss_lc_seed_hw_rd_en_o ) + `CALIPTRA_ASSERT_KNOWN(LcKeymgrEnKnown_A, caliptra_ss_lc_keymgr_en_o ) + `CALIPTRA_ASSERT_KNOWN(LcEscalateEnKnown_A, caliptra_ss_lc_escalate_en_o ) + `CALIPTRA_ASSERT_KNOWN(LcCheckBypassEnKnown_A, caliptra_ss_lc_check_byp_en_o ) + `CALIPTRA_ASSERT_KNOWN(LcClkBypReqKnown_A, caliptra_ss_lc_clk_byp_req_o ) + `CALIPTRA_ASSERT_KNOWN(LcFlashRmaSeedKnown_A, caliptra_ss_lc_flash_rma_seed_o ) + `CALIPTRA_ASSERT_KNOWN(LcFlashRmaReqKnown_A, caliptra_ss_lc_flash_rma_req_o ) + `CALIPTRA_ASSERT_KNOWN(LcKeymgrDiv_A, caliptra_ss_lc_keymgr_div_o ) + + // Alert assertions for sparse FSMs. + `CALIPTRA_ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(CtrlLcFsmCheck_A, + u_caliptra_ss_lc_ctrl_fsm.u_fsm_state_regs, alert_tx_o[1]) + `CALIPTRA_ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(CtrlLcStateCheck_A, + u_caliptra_ss_lc_ctrl_fsm.u_state_regs, alert_tx_o[1], + !$past(otp_caliptra_ss_lc_data_i.valid) || + u_caliptra_ss_lc_ctrl_fsm.fsm_state_q inside {ResetSt, EscalateSt, PostTransSt, InvalidSt, ScrapSt} || + u_caliptra_ss_lc_ctrl_fsm.esc_scrap_state0_i || + u_caliptra_ss_lc_ctrl_fsm.esc_scrap_state1_i) + `CALIPTRA_ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(CtrlLcCntCheck_A, + u_caliptra_ss_lc_ctrl_fsm.u_cnt_regs, alert_tx_o[1], + !$past(otp_caliptra_ss_lc_data_i.valid) || + u_caliptra_ss_lc_ctrl_fsm.fsm_state_q inside {ResetSt, EscalateSt, PostTransSt, InvalidSt, ScrapSt} || + u_caliptra_ss_lc_ctrl_fsm.esc_scrap_state0_i || + u_caliptra_ss_lc_ctrl_fsm.esc_scrap_state1_i) + `CALIPTRA_ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(CtrlKmacIfFsmCheck_A, + u_caliptra_ss_lc_ctrl_kmac_if.u_state_regs, alert_tx_o[1], + u_caliptra_ss_lc_ctrl_fsm.fsm_state_q inside {EscalateSt} || + u_caliptra_ss_lc_ctrl_fsm.esc_scrap_state0_i || + u_caliptra_ss_lc_ctrl_fsm.esc_scrap_state1_i) + + // Alert assertions for reg_we onehot check + `CALIPTRA_ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ALERT(RegsWeOnehotCheck_A, u_reg_regs, alert_tx_o[2]) + `CALIPTRA_ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ALERT(TapDmiWeOnehotCheck_A, + u_reg_tap_dmi, alert_tx_o[2], 0) +endmodule : caliptra_ss_lc_ctrl diff --git a/src/caliptra_ss_lc_ctrl/rtl/caliptra_ss_lc_ctrl_dmi_reg_top.sv b/src/caliptra_ss_lc_ctrl/rtl/caliptra_ss_lc_ctrl_dmi_reg_top.sv new file mode 100644 index 0000000..ba58f40 --- /dev/null +++ b/src/caliptra_ss_lc_ctrl/rtl/caliptra_ss_lc_ctrl_dmi_reg_top.sv @@ -0,0 +1,60 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Top module auto-generated by `reggen` + +`include "caliptra_prim_assert.sv" + +module caliptra_ss_lc_ctrl_dmi_reg_top ( + input clk_i, + input rst_ni, + input tlul_pkg::tl_h2d_t tl_i, + output tlul_pkg::tl_d2h_t tl_o, + + // Output port for window + output tlul_pkg::tl_h2d_t tl_win_o, + input tlul_pkg::tl_d2h_t tl_win_i, + + // To HW + + // Integrity check errors + output logic intg_err_o +); + + import caliptra_ss_lc_ctrl_reg_pkg::* ; + + + // Add an unloaded flop to make use of clock / reset + // This is done to specifically address lint complaints of unused clocks/resets + // Since the flop is unloaded it will be removed during synthesis + logic unused_reg; + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + unused_reg <= '0; + end else begin + unused_reg <= tl_i.a_valid; + end + end + + + + // Since there are no registers in this block, commands are routed through to windows which + // can report their own integrity errors. + assign intg_err_o = 1'b0; + + // outgoing integrity generation + tlul_pkg::tl_d2h_t tl_o_pre; + tlul_rsp_intg_gen #( + .EnableRspIntgGen(1), + .EnableDataIntgGen(0) + ) u_rsp_intg_gen ( + .tl_i(tl_o_pre), + .tl_o(tl_o) + ); + + assign tl_win_o = tl_i; + assign tl_o_pre = tl_win_i; + + // Unused signal tieoff +endmodule diff --git a/src/caliptra_ss_lc_ctrl/rtl/caliptra_ss_lc_ctrl_fsm.sv b/src/caliptra_ss_lc_ctrl/rtl/caliptra_ss_lc_ctrl_fsm.sv new file mode 100644 index 0000000..b1fc182 --- /dev/null +++ b/src/caliptra_ss_lc_ctrl/rtl/caliptra_ss_lc_ctrl_fsm.sv @@ -0,0 +1,884 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Main Life Cycle Controller FSM. + +`include "caliptra_prim_assert.sv" + +module caliptra_ss_lc_ctrl_fsm + import caliptra_ss_lc_ctrl_pkg::*; + import caliptra_ss_lc_ctrl_reg_pkg::*; + import caliptra_ss_lc_ctrl_state_pkg::*; +#(// Random netlist constants + parameter caliptra_ss_lc_keymgr_div_t RndCnstLcKeymgrDivInvalid = LcKeymgrDivWidth'(0), + parameter caliptra_ss_lc_keymgr_div_t RndCnstLcKeymgrDivTestUnlocked = LcKeymgrDivWidth'(1), + parameter caliptra_ss_lc_keymgr_div_t RndCnstLcKeymgrDivDev = LcKeymgrDivWidth'(2), + parameter caliptra_ss_lc_keymgr_div_t RndCnstLcKeymgrDivProduction = LcKeymgrDivWidth'(3), + parameter caliptra_ss_lc_keymgr_div_t RndCnstLcKeymgrDivRma = LcKeymgrDivWidth'(4), + parameter caliptra_ss_lc_token_mux_t RndCnstInvalidTokens = {TokenMuxBits{1'b1}}, + parameter bit SecVolatileRawUnlockEn = 0 +) ( + // This module is combinational, but we + // need the clock and reset for the assertions. + input clk_i, + input rst_ni, + // Initialization request from power manager. + input init_req_i, + output logic init_done_o, + output logic idle_o, + // Escalation input + input esc_scrap_state0_i, + input esc_scrap_state1_i, + // Life cycle state vector from OTP. + input caliptra_ss_lc_state_valid_i, + input caliptra_ss_lc_state_e caliptra_ss_lc_state_i, + input caliptra_ss_lc_cnt_e caliptra_ss_lc_cnt_i, + input caliptra_ss_lc_tx_t secrets_valid_i, + // Defines whether we switch to an external clock when initiating a transition. + input use_ext_clock_i, + output logic ext_clock_switched_o, + // ---------- VOLATILE_TEST_UNLOCKED CODE SECTION START ---------- + // NOTE THAT THIS IS A FEATURE FOR TEST CHIPS ONLY TO MITIGATE + // THE RISK OF A BROKEN OTP MACRO. THIS WILL BE DISABLED VIA + // SecVolatileRawUnlockEn AT COMPILETIME FOR PRODUCTION DEVICES. + // --------------------------------------------------------------- + input logic volatile_raw_unlock_i, + output logic strap_en_override_o, + // ----------- VOLATILE_TEST_UNLOCKED CODE SECTION END ----------- + // Token input from OTP (these are all hash post-images). + input caliptra_ss_lc_token_t test_unlock_token_i, + input caliptra_ss_lc_token_t test_exit_token_i, + input caliptra_ss_lc_tx_t test_tokens_valid_i, + input caliptra_ss_lc_token_t rma_token_i, + input caliptra_ss_lc_tx_t rma_token_valid_i, + // Transition trigger interface. + input trans_cmd_i, + input ext_dec_caliptra_ss_lc_state_t trans_target_i, + // Decoded life cycle state for CSRs. + output ext_dec_caliptra_ss_lc_state_t dec_caliptra_ss_lc_state_o, + output dec_caliptra_ss_lc_cnt_t dec_caliptra_ss_lc_cnt_o, + output dec_caliptra_ss_lc_id_state_e dec_caliptra_ss_lc_id_state_o, + // Token hashing interface + output logic token_hash_req_o, + output logic token_hash_req_chk_o, + input token_hash_ack_i, + input token_hash_err_i, + input token_if_fsm_err_i, + input caliptra_ss_lc_token_t hashed_token_i, + input caliptra_ss_lc_token_t unhashed_token_i, + // OTP programming interface + output logic otp_prog_req_o, + output caliptra_ss_lc_state_e otp_prog_caliptra_ss_lc_state_o, + output caliptra_ss_lc_cnt_e otp_prog_caliptra_ss_lc_cnt_o, + input otp_prog_ack_i, + input otp_prog_err_i, + // Error outputs going to CSRs + output logic trans_success_o, + output logic trans_cnt_oflw_error_o, + output logic trans_invalid_error_o, + output logic token_invalid_error_o, + output logic flash_rma_error_o, + output logic otp_prog_error_o, + output logic state_invalid_error_o, + // Local life cycle signal + output caliptra_ss_lc_tx_t caliptra_ss_lc_raw_test_rma_o, + // Life cycle broadcast outputs. + output caliptra_ss_lc_tx_t caliptra_ss_lc_dft_en_o, + output caliptra_ss_lc_tx_t caliptra_ss_lc_nvm_debug_en_o, + output caliptra_ss_lc_tx_t caliptra_ss_lc_hw_debug_en_o, + output caliptra_ss_lc_tx_t caliptra_ss_lc_cpu_en_o, + output caliptra_ss_lc_tx_t caliptra_ss_lc_creator_seed_sw_rw_en_o, + output caliptra_ss_lc_tx_t caliptra_ss_lc_owner_seed_sw_rw_en_o, + output caliptra_ss_lc_tx_t caliptra_ss_lc_iso_part_sw_rd_en_o, + output caliptra_ss_lc_tx_t caliptra_ss_lc_iso_part_sw_wr_en_o, + output caliptra_ss_lc_tx_t caliptra_ss_lc_seed_hw_rd_en_o, + output caliptra_ss_lc_tx_t caliptra_ss_lc_keymgr_en_o, + output caliptra_ss_lc_tx_t caliptra_ss_lc_escalate_en_o, + output caliptra_ss_lc_tx_t caliptra_ss_lc_check_byp_en_o, + // Request and feedback to/from clock manager and AST. + output caliptra_ss_lc_tx_t caliptra_ss_lc_clk_byp_req_o, + input caliptra_ss_lc_tx_t caliptra_ss_lc_clk_byp_ack_i, + // Request and feedback to/from flash controller + output caliptra_ss_lc_tx_t caliptra_ss_lc_flash_rma_req_o, + input caliptra_ss_lc_tx_t [NumRmaAckSigs-1:0] caliptra_ss_lc_flash_rma_ack_i, + // State group diversification value for keymgr + output caliptra_ss_lc_keymgr_div_t caliptra_ss_lc_keymgr_div_o +); + + ///////////////////////////// + // Synchronizers / Buffers // + ///////////////////////////// + + // We use multiple copies of these signals in the + // FSM checks below. + caliptra_ss_lc_tx_t [3:0] caliptra_ss_lc_clk_byp_ack; + caliptra_prim_lc_sync #( + .NumCopies(4) + ) u_caliptra_prim_lc_sync_clk_byp_ack ( + .clk_i, + .rst_ni, + .lc_en_i(caliptra_ss_lc_clk_byp_ack_i), + .lc_en_o(caliptra_ss_lc_clk_byp_ack) + ); + + // Indication for CSRs + assign ext_clock_switched_o = caliptra_ss_lc_tx_test_true_strict(caliptra_ss_lc_clk_byp_ack[3]); + + // We have multiple response channels for this signal since the RMA wiping requests can go to + // multiple modules that perform wiping in parallel. For security reasons, this signal is not + // daisy-chained - see #19136 for context. Synchronize ACK signals separately, combine with + // bitwise LC AND function and feed into FSM. + caliptra_ss_lc_tx_t [NumRmaAckSigs-1:0] caliptra_ss_lc_flash_rma_ack; + for (genvar k = 0; k < NumRmaAckSigs; k++) begin : gen_syncs + caliptra_prim_lc_sync #( + .NumCopies(1) + ) u_caliptra_prim_lc_sync_flash_rma_ack( + .clk_i, + .rst_ni, + .lc_en_i(caliptra_ss_lc_flash_rma_ack_i[k]), + .lc_en_o({caliptra_ss_lc_flash_rma_ack[k]}) + ); + end + + caliptra_ss_lc_tx_t caliptra_ss_lc_flash_rma_ack_combined; + always_comb begin + caliptra_ss_lc_flash_rma_ack_combined = On; + for (int k = 0; k < NumRmaAckSigs; k++) begin + caliptra_ss_lc_flash_rma_ack_combined = caliptra_ss_lc_tx_and_hi(caliptra_ss_lc_flash_rma_ack_combined, caliptra_ss_lc_flash_rma_ack[k]); + end + end + + // Make buffered copies for consumption in the FSM below. + caliptra_ss_lc_tx_t [2:0] caliptra_ss_lc_flash_rma_ack_buf; + caliptra_prim_lc_sync #( + .NumCopies(3), + .AsyncOn(0) + ) u_caliptra_prim_lc_sync_flash_rma_ack_buf ( + .clk_i, + .rst_ni, + .lc_en_i(caliptra_ss_lc_flash_rma_ack_combined), + .lc_en_o(caliptra_ss_lc_flash_rma_ack_buf) + ); + + /////////////// + // FSM Logic // + /////////////// + fsm_state_e fsm_state_d, fsm_state_q; + + // Continuously feed in valid signal for LC state. + logic caliptra_ss_lc_state_valid_d, caliptra_ss_lc_state_valid_q; + assign caliptra_ss_lc_state_valid_d = caliptra_ss_lc_state_valid_i; + + // Encoded state vector. + caliptra_ss_lc_state_e caliptra_ss_lc_state_d, caliptra_ss_lc_state_q, next_caliptra_ss_lc_state; + caliptra_ss_lc_cnt_e caliptra_ss_lc_cnt_d, caliptra_ss_lc_cnt_q, next_caliptra_ss_lc_cnt; + + // Feed the next lc state reg back to the programming interface of OTP. + assign otp_prog_caliptra_ss_lc_state_o = next_caliptra_ss_lc_state; + assign otp_prog_caliptra_ss_lc_cnt_o = next_caliptra_ss_lc_cnt; + + // Conditional LC signal outputs + caliptra_ss_lc_tx_t caliptra_ss_lc_clk_byp_req, caliptra_ss_lc_flash_rma_req, caliptra_ss_lc_check_byp_en; + + `CALIPTRA_ASSERT_KNOWN(LcStateKnown_A, caliptra_ss_lc_state_q ) + `CALIPTRA_ASSERT_KNOWN(LcCntKnown_A, caliptra_ss_lc_cnt_q ) + `CALIPTRA_ASSERT_KNOWN(FsmStateKnown_A, fsm_state_q ) + + // Hashed token to compare against. + logic [1:0] hashed_token_valid_mux; + caliptra_ss_lc_token_t hashed_token_mux; + + // Multibit state error from state decoder + logic [5:0] state_invalid_error; + + // Strap sample override signal. + logic set_strap_en_override; + + // Registers whether volatile unlock has been successful + caliptra_prim_mubi_pkg::mubi8_t volatile_raw_unlock_success_d, volatile_raw_unlock_success_q; + + // SEC_CM: MAIN.CTRL_FLOW.CONSISTENCY + always_comb begin : p_fsm + // FSM default state assignments. + fsm_state_d = fsm_state_q; + caliptra_ss_lc_state_d = caliptra_ss_lc_state_q; + caliptra_ss_lc_cnt_d = caliptra_ss_lc_cnt_q; + + // Token hashing. + token_hash_req_o = 1'b0; + token_hash_req_chk_o = 1'b1; + + // OTP Interface + otp_prog_req_o = 1'b0; + + // Defaults for status/error signals. + token_invalid_error_o = 1'b0; + otp_prog_error_o = 1'b0; + flash_rma_error_o = 1'b0; + trans_success_o = 1'b0; + state_invalid_error_o = 1'b0; + + // Status indication going to power manager. + init_done_o = 1'b1; + idle_o = 1'b0; + + // ---------- VOLATILE_TEST_UNLOCKED CODE SECTION START ---------- + // NOTE THAT THIS IS A FEATURE FOR TEST CHIPS ONLY TO MITIGATE + // THE RISK OF A BROKEN OTP MACRO. THIS WILL BE DISABLED VIA + // SecVolatileRawUnlockEn AT COMPILETIME FOR PRODUCTION DEVICES. + // --------------------------------------------------------------- + set_strap_en_override = 1'b0; + volatile_raw_unlock_success_d = volatile_raw_unlock_success_q; + // ----------- VOLATILE_TEST_UNLOCKED CODE SECTION END ----------- + + // These signals remain asserted once set to On. + // Note that the remaining life cycle signals are decoded in + // the caliptra_ss_lc_ctrl_signal_decode submodule. + caliptra_ss_lc_clk_byp_req = caliptra_ss_lc_clk_byp_req_o; + caliptra_ss_lc_flash_rma_req = caliptra_ss_lc_flash_rma_req_o; + caliptra_ss_lc_check_byp_en = caliptra_ss_lc_check_byp_en_o; + + unique case (fsm_state_q) + /////////////////////////////////////////////////////////////////// + // Wait here until OTP has initialized and the + // power manager sends an initialization request. + ResetSt: begin + init_done_o = 1'b0; + caliptra_ss_lc_clk_byp_req = Off; + caliptra_ss_lc_flash_rma_req = Off; + caliptra_ss_lc_check_byp_en = Off; + if (init_req_i && caliptra_ss_lc_state_valid_q) begin + fsm_state_d = IdleSt; + // Fetch LC state vector from OTP. + caliptra_ss_lc_state_d = caliptra_ss_lc_state_i; + caliptra_ss_lc_cnt_d = caliptra_ss_lc_cnt_i; + end + end + /////////////////////////////////////////////////////////////////// + // Idle state where life cycle control signals are broadcast. + // Note that the life cycle signals are decoded and broadcast + // in the caliptra_ss_lc_ctrl_signal_decode submodule. + IdleSt: begin + idle_o = 1'b1; + + // ---------- VOLATILE_TEST_UNLOCKED CODE SECTION START ---------- + // NOTE THAT THIS IS A FEATURE FOR TEST CHIPS ONLY TO MITIGATE + // THE RISK OF A BROKEN OTP MACRO. THIS WILL BE DISABLED VIA + // SecVolatileRawUnlockEn AT COMPILETIME FOR PRODUCTION DEVICES. + // --------------------------------------------------------------- + // Note that if the volatile unlock mechanism is available, + // we have to stop fetching the OTP value after a volatile unlock has succeeded. + // Otherwise we unconditionally fetch from OTP in this state. + if (!(SecVolatileRawUnlockEn && caliptra_ss_lc_state_q == LcStTestUnlocked0 && caliptra_ss_lc_cnt_q != LcCnt0) || + caliptra_prim_mubi_pkg::mubi8_test_false_loose(volatile_raw_unlock_success_q)) begin + // Continuously fetch LC state vector from OTP. + // The state is locked in once a transition is started. + caliptra_ss_lc_state_d = caliptra_ss_lc_state_i; + caliptra_ss_lc_cnt_d = caliptra_ss_lc_cnt_i; + end + // ----------- VOLATILE_TEST_UNLOCKED CODE SECTION END ----------- + + // If the life cycle state is SCRAP, we move the FSM into a terminal + // SCRAP state that does not allow any transitions to be initiated anymore. + if (caliptra_ss_lc_state_q == LcStScrap) begin + fsm_state_d = ScrapSt; + + // ---------- VOLATILE_TEST_UNLOCKED CODE SECTION START ---------- + // NOTE THAT THIS IS A FEATURE FOR TEST CHIPS ONLY TO MITIGATE + // THE RISK OF A BROKEN OTP MACRO. THIS WILL BE DISABLED VIA + // SecVolatileRawUnlockEn AT COMPILETIME FOR PRODUCTION DEVICES. + // --------------------------------------------------------------- + // Only enter here if volatile RAW unlock is available and enabled. + end else if (SecVolatileRawUnlockEn && volatile_raw_unlock_i && trans_cmd_i) begin + // We only allow transitions from RAW -> TEST_UNLOCKED0 + if (caliptra_ss_lc_state_q == LcStRaw && + trans_target_i == {DecLcStateNumRep{DecLcStTestUnlocked0}} && + !trans_invalid_error_o) begin + // 128bit token check (without passing it through the KMAC) + if (unhashed_token_i == RndCnstRawUnlockTokenHashed) begin + // We stay in Idle, but update the life cycle state register (volatile). + caliptra_ss_lc_state_d = LcStTestUnlocked0; + // If the count is 0, we set it to 1 - otherwise we just leave it as is so that the + // register value is in sync with what has been programmed to OTP already (there may + // have been unsuccessul raw unlock attempts before that already incremented it). + caliptra_ss_lc_cnt_d = (caliptra_ss_lc_cnt_q == LcCnt0) ? LcCnt1 : caliptra_ss_lc_cnt_q; + // Re-sample the DFT straps in the pinmux. + // This signal will be delayed by several cycles so that the LC_CTRL signals + // have time to propagate. + set_strap_en_override = 1'b1; + // We have to remember that the transition was successful in order to correctly + // disable the continuos sampling of the life cycle state vector coming from OTP. + volatile_raw_unlock_success_d = caliptra_prim_mubi_pkg::MuBi8True; + // Indicate that the transition was successful. + trans_success_o = 1'b1; + end else begin + token_invalid_error_o = 1'b1; + fsm_state_d = PostTransSt; + end + end else begin + // Transition invalid error is set by caliptra_ss_lc_ctrl_state_transition module. + fsm_state_d = PostTransSt; + end + // ----------- VOLATILE_TEST_UNLOCKED CODE SECTION END ----------- + // Initiate a transition. This will first increment the + // life cycle counter before hashing and checking the token. + end else if (trans_cmd_i) begin + fsm_state_d = ClkMuxSt; + end + // If we are in a non-PROD life cycle state, steer the clock mux if requested. This + // action is available in IdleSt so that the mux can be steered without having to initiate + // a life cycle transition. If a transition is initiated however, the life cycle controller + // will wait for the clock mux acknowledgement in the ClkMuxSt state before proceeding. + if (caliptra_ss_lc_state_q inside {LcStRaw, + LcStTestLocked0, + LcStTestLocked1, + LcStTestLocked2, + LcStTestLocked3, + LcStTestLocked4, + LcStTestLocked5, + LcStTestLocked6, + LcStTestUnlocked0, + LcStTestUnlocked1, + LcStTestUnlocked2, + LcStTestUnlocked3, + LcStTestUnlocked4, + LcStTestUnlocked5, + LcStTestUnlocked6, + LcStTestUnlocked7, + LcStRma}) begin + if (use_ext_clock_i) begin + caliptra_ss_lc_clk_byp_req = On; + end + end + end + /////////////////////////////////////////////////////////////////// + // Clock mux state. If we are in RAW, TEST* or RMA, it is permissible + // to switch to an external clock source. If the bypass request is + // asserted, we have to wait until the clock mux and clock manager + // have switched the mux and the clock divider. Also, we disable the + // life cycle partition checks at this point since we are going to + // alter the contents in the OTP memory array, which could lead to + // spurious escalations. + ClkMuxSt: begin + caliptra_ss_lc_check_byp_en = On; + if (caliptra_ss_lc_state_q inside {LcStRaw, + LcStTestLocked0, + LcStTestLocked1, + LcStTestLocked2, + LcStTestLocked3, + LcStTestLocked4, + LcStTestLocked5, + LcStTestLocked6, + LcStTestUnlocked0, + LcStTestUnlocked1, + LcStTestUnlocked2, + LcStTestUnlocked3, + LcStTestUnlocked4, + LcStTestUnlocked5, + LcStTestUnlocked6, + LcStTestUnlocked7, + LcStRma}) begin + if (use_ext_clock_i) begin + caliptra_ss_lc_clk_byp_req = On; + if (caliptra_ss_lc_tx_test_true_strict(caliptra_ss_lc_clk_byp_ack[0])) begin + fsm_state_d = CntIncrSt; + end + end else begin + fsm_state_d = CntIncrSt; + end + end else begin + fsm_state_d = CntIncrSt; + end + end + /////////////////////////////////////////////////////////////////// + // This increments the life cycle counter state. + CntIncrSt: begin + // If the counter has reached the maximum, bail out. + if (trans_cnt_oflw_error_o) begin + fsm_state_d = PostTransSt; + end else begin + fsm_state_d = CntProgSt; + end + end + /////////////////////////////////////////////////////////////////// + // This programs the life cycle counter state. + CntProgSt: begin + otp_prog_req_o = 1'b1; + + // If the clock mux has been steered, double check that this is still the case. + // Otherwise abort the transition operation. + if (caliptra_ss_lc_clk_byp_req_o != caliptra_ss_lc_clk_byp_ack[1]) begin + fsm_state_d = PostTransSt; + otp_prog_error_o = 1'b1; + end + + // Check return value and abort if there + // was an error. + if (otp_prog_ack_i) begin + if (otp_prog_err_i) begin + fsm_state_d = PostTransSt; + otp_prog_error_o = 1'b1; + end else begin + fsm_state_d = TransCheckSt; + end + end + end + /////////////////////////////////////////////////////////////////// + // First transition valid check. This will be repeated several + // times below. + TransCheckSt: begin + if (trans_invalid_error_o) begin + fsm_state_d = PostTransSt; + end else begin + fsm_state_d = TokenHashSt; + end + end + /////////////////////////////////////////////////////////////////// + // Hash and compare the token, no matter whether this transition + // is conditional or not. Unconditional transitions just use a known + // all-zero token value. That way, we always compare a hashed token + // and guarantee that no other control flow path exists that could + // bypass the token check. + // SEC_CM: TOKEN.DIGEST + TokenHashSt: begin + token_hash_req_o = 1'b1; + if (token_hash_ack_i) begin + // This is the first comparison. + // The token is compared two more times further below. + // Also note that conditional transitions won't be possible if the + // corresponding token is not valid. This only applies to tokens stored in + // OTP. I.e., these tokens first have to be provisioned, before they can be used. + if (hashed_token_i == hashed_token_mux && + !token_hash_err_i && + &hashed_token_valid_mux) begin + fsm_state_d = FlashRmaSt; + end else begin + fsm_state_d = PostTransSt; + token_invalid_error_o = 1'b1; + end + end + end + /////////////////////////////////////////////////////////////////// + // Flash RMA state. Note that we check the flash response again + // two times later below. + FlashRmaSt: begin + if (trans_target_i == {DecLcStateNumRep{DecLcStRma}}) begin + caliptra_ss_lc_flash_rma_req = On; + if (caliptra_ss_lc_tx_test_true_strict(caliptra_ss_lc_flash_rma_ack_buf[0])) begin + fsm_state_d = TokenCheck0St; + end + end else begin + fsm_state_d = TokenCheck0St; + end + end + /////////////////////////////////////////////////////////////////// + // Check again two times whether this transition and the hashed + // token are valid. Also check again whether the flash RMA + // response is valid. + // SEC_CM: TOKEN.DIGEST + TokenCheck0St, + TokenCheck1St: begin + if (trans_invalid_error_o) begin + fsm_state_d = PostTransSt; + end else begin + // If any of these RMA are conditions are true, + // all of them must be true at the same time. + if ((trans_target_i != {DecLcStateNumRep{DecLcStRma}} && + caliptra_ss_lc_tx_test_false_strict(caliptra_ss_lc_flash_rma_req_o) && + caliptra_ss_lc_tx_test_false_strict(caliptra_ss_lc_flash_rma_ack_buf[1])) || + (trans_target_i == {DecLcStateNumRep{DecLcStRma}} && + caliptra_ss_lc_tx_test_true_strict(caliptra_ss_lc_flash_rma_req_o) && + caliptra_ss_lc_tx_test_true_strict(caliptra_ss_lc_flash_rma_ack_buf[1]))) begin + if (hashed_token_i == hashed_token_mux && + !token_hash_err_i && + &hashed_token_valid_mux) begin + if (fsm_state_q == TokenCheck1St) begin + // This is the only way we can get into the + // programming state. + fsm_state_d = TransProgSt; + end else begin + fsm_state_d = TokenCheck1St; + end + end else begin + fsm_state_d = PostTransSt; + token_invalid_error_o = 1'b1; + end + // The flash RMA process failed. + end else begin + fsm_state_d = PostTransSt; + flash_rma_error_o = 1'b1; + end + end + end + /////////////////////////////////////////////////////////////////// + // Initiate OTP transaction. Note that the concurrent + // LC state check is continuously checking whether the + // new LC state remains valid. Once the ack returns we are + // done with the transition and can go into the terminal PosTransSt. + TransProgSt: begin + otp_prog_req_o = 1'b1; + + // If the clock mux has been steered, double check that this is still the case. + // Otherwise abort the transition operation. + if (caliptra_ss_lc_clk_byp_req_o != caliptra_ss_lc_clk_byp_ack[2]) begin + fsm_state_d = PostTransSt; + otp_prog_error_o = 1'b1; + // Also double check that the RMA signals remain stable. + // Otherwise abort the transition operation. + end else if ((trans_target_i != {DecLcStateNumRep{DecLcStRma}} && + (caliptra_ss_lc_flash_rma_req_o != Off || caliptra_ss_lc_flash_rma_ack_buf[2] != Off)) || + (trans_target_i == {DecLcStateNumRep{DecLcStRma}} && + (caliptra_ss_lc_flash_rma_req_o != On || caliptra_ss_lc_flash_rma_ack_buf[2] != On))) begin + fsm_state_d = PostTransSt; + flash_rma_error_o = 1'b1; + end else if (otp_prog_ack_i) begin + fsm_state_d = PostTransSt; + otp_prog_error_o = otp_prog_err_i; + trans_success_o = ~otp_prog_err_i; + end + end + /////////////////////////////////////////////////////////////////// + // Terminal states. + ScrapSt, + PostTransSt: ; + + + EscalateSt: begin + // During an escalation it is okay to de-assert token_hash_req without receivng ACK. + token_hash_req_chk_o = 1'b0; + end + + InvalidSt: begin + // During an escalation it is okay to de-assert token_hash_req without receivng ACK. + token_hash_req_chk_o = 1'b0; + state_invalid_error_o = 1'b1; + end + /////////////////////////////////////////////////////////////////// + // Go to terminal error state if we get here. + default: begin + fsm_state_d = InvalidSt; + state_invalid_error_o = 1'b1; + end + /////////////////////////////////////////////////////////////////// + endcase + + // SEC_CM: MAIN.FSM.GLOBAL_ESC + if (esc_scrap_state0_i || esc_scrap_state1_i) begin + fsm_state_d = EscalateSt; + // SEC_CM: MAIN.FSM.LOCAL_ESC + // If at any time the life cycle state encoding or any other FSM state within this module + // is not valid, we jump into the terminal error state right away. + // Note that state_invalid_error is a multibit error signal + // with different error sources - need to reduce this to one bit here. + end else if ((|state_invalid_error | token_if_fsm_err_i) && (fsm_state_q != EscalateSt)) begin + fsm_state_d = InvalidSt; + state_invalid_error_o = 1'b1; + end + end + + ///////////////// + // State Flops // + ///////////////// + + `CALIPTRA_PRIM_FLOP_SPARSE_FSM(u_fsm_state_regs, fsm_state_d, fsm_state_q, fsm_state_e, ResetSt) + `CALIPTRA_PRIM_FLOP_SPARSE_FSM(u_state_regs, caliptra_ss_lc_state_d, caliptra_ss_lc_state_q, caliptra_ss_lc_state_e, LcStScrap) + `CALIPTRA_PRIM_FLOP_SPARSE_FSM(u_cnt_regs, caliptra_ss_lc_cnt_d, caliptra_ss_lc_cnt_q, caliptra_ss_lc_cnt_e, LcCnt24) + + always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs + if (!rst_ni) begin + caliptra_ss_lc_state_valid_q <= 1'b0; + end else begin + caliptra_ss_lc_state_valid_q <= caliptra_ss_lc_state_valid_d; + end + end + + // ---------- VOLATILE_TEST_UNLOCKED CODE SECTION START ---------- + // NOTE THAT THIS IS A FEATURE FOR TEST CHIPS ONLY TO MITIGATE + // THE RISK OF A BROKEN OTP MACRO. THIS WILL BE DISABLED VIA + // SecVolatileRawUnlockEn AT COMPILETIME FOR PRODUCTION DEVICES. + // --------------------------------------------------------------- + if (SecVolatileRawUnlockEn) begin : gen_strap_delay_regs + // The delay on the life cycle signals is 1 sender + 2 receiver domain + // cycles. We are delaying this cycle several cycles more than that so + // that the life cycle signals have time to propagate (for good measure). + localparam int NumStrapDelayRegs = 10; + logic [NumStrapDelayRegs-1:0] strap_en_override_q; + always_ff @(posedge clk_i or negedge rst_ni) begin : p_volatile_raw_unlock_reg + if(!rst_ni) begin + strap_en_override_q <= '0; + volatile_raw_unlock_success_q <= caliptra_prim_mubi_pkg::MuBi8False; + end else begin + strap_en_override_q <= {strap_en_override_q[NumStrapDelayRegs-2:0], + // This is a set-reg that will stay high until the next reset. + set_strap_en_override || strap_en_override_q[0]}; + volatile_raw_unlock_success_q <= volatile_raw_unlock_success_d; + end + end + + assign strap_en_override_o = strap_en_override_q[NumStrapDelayRegs-1]; + end else begin : gen_no_strap_delay_regs + // In this case we tie the strap sampling off. + logic unused_sigs; + assign unused_sigs = ^{set_strap_en_override, + volatile_raw_unlock_success_d}; + assign strap_en_override_o = 1'b0; + assign volatile_raw_unlock_success_q = caliptra_prim_mubi_pkg::MuBi8False; + end + // ----------- VOLATILE_TEST_UNLOCKED CODE SECTION END ----------- + + /////////////// + // Token mux // + /////////////// + + caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_t [3:0] rma_token_valid; + caliptra_prim_lc_sync #( + .NumCopies(4), + .AsyncOn(0), + .ResetValueIsOn(0) + ) u_caliptra_prim_lc_sync_rma_token_valid ( + .clk_i, + .rst_ni, + .lc_en_i(rma_token_valid_i), + .lc_en_o(rma_token_valid) + ); + + caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_t [7:0] test_tokens_valid; + caliptra_prim_lc_sync #( + .NumCopies(8), + .AsyncOn(0), + .ResetValueIsOn(0) + ) u_caliptra_prim_lc_sync_test_token_valid ( + .clk_i, + .rst_ni, + .lc_en_i(test_tokens_valid_i), + .lc_en_o(test_tokens_valid) + ); + + // SEC_CM: TOKEN_MUX.CTRL.REDUN + // The token mux is split into two halves for which we use separate mux select signals + // that have both been generated from separately buffered multibit lifecycle signals. + logic [2**TokenIdxWidth-1:0][LcTokenWidth/2-1:0] hashed_tokens_lower, hashed_tokens_upper; + // These helper signals are only there to increase readability of the mux code below. + logic [LcTokenWidth/2-1:0] test_unlock_token_lower, test_unlock_token_upper; + logic [LcTokenWidth/2-1:0] test_exit_token_lower, test_exit_token_upper; + logic [LcTokenWidth/2-1:0] rma_token_lower, rma_token_upper; + assign {test_unlock_token_lower, test_unlock_token_upper} = test_unlock_token_i; + assign {test_exit_token_lower, test_exit_token_upper} = test_exit_token_i; + assign {rma_token_lower, rma_token_upper} = rma_token_i; + + // SEC_CM: TOKEN.DIGEST + // This indexes the correct token, based on the transition arc. + // Note that we always perform a token comparison, even in case of + // unconditional transitions. In the case of unconditional tokens + // we just pass an all-zero constant through the hashing function. + always_comb begin : p_token_assign + // Set the invalid token indices to a random netlist constant, rather than all-zero. + {hashed_tokens_lower, hashed_tokens_upper} = RndCnstInvalidTokens; + // All-zero token for unconditional transitions. + {hashed_tokens_lower[ZeroTokenIdx], + hashed_tokens_upper[ZeroTokenIdx]} = AllZeroTokenHashed; + {hashed_tokens_lower[RawUnlockTokenIdx], + hashed_tokens_upper[RawUnlockTokenIdx]} = RndCnstRawUnlockTokenHashed; + // This mux has two separate halves, steered with separately buffered life cycle signals. + if (caliptra_ss_lc_tx_test_true_strict(test_tokens_valid[0])) begin + hashed_tokens_lower[TestUnlockTokenIdx] = test_unlock_token_lower; + end + if (caliptra_ss_lc_tx_test_true_strict(test_tokens_valid[1])) begin + hashed_tokens_upper[TestUnlockTokenIdx] = test_unlock_token_upper; + end + // This mux has two separate halves, steered with separately buffered life cycle signals. + if (caliptra_ss_lc_tx_test_true_strict(test_tokens_valid[2])) begin + hashed_tokens_lower[TestExitTokenIdx] = test_exit_token_lower; + end + if (caliptra_ss_lc_tx_test_true_strict(test_tokens_valid[3])) begin + hashed_tokens_upper[TestExitTokenIdx] = test_exit_token_upper; + end + // This mux has two separate halves, steered with separately buffered life cycle signals. + if (caliptra_ss_lc_tx_test_true_strict(rma_token_valid[0])) begin + hashed_tokens_lower[RmaTokenIdx] = rma_token_lower; + end + if (caliptra_ss_lc_tx_test_true_strict(rma_token_valid[1])) begin + hashed_tokens_upper[RmaTokenIdx] = rma_token_upper; + end + end + + // SEC_CM: TOKEN_VALID.MUX.REDUN + // The token valid mux is duplicated. + logic [TokenIdxWidth-1:0] token_idx0, token_idx1; + logic [2**TokenIdxWidth-1:0] hashed_tokens_valid0, hashed_tokens_valid1; + always_comb begin : p_token_valid_assign + // First mux + hashed_tokens_valid0 = '0; + hashed_tokens_valid0[ZeroTokenIdx] = 1'b1; // always valid + hashed_tokens_valid0[RawUnlockTokenIdx] = 1'b1; // always valid + hashed_tokens_valid0[TestUnlockTokenIdx] = caliptra_ss_lc_tx_test_true_strict(test_tokens_valid[4]); + hashed_tokens_valid0[TestExitTokenIdx] = caliptra_ss_lc_tx_test_true_strict(test_tokens_valid[5]); + hashed_tokens_valid0[RmaTokenIdx] = caliptra_ss_lc_tx_test_true_strict(rma_token_valid[2]); + hashed_tokens_valid0[InvalidTokenIdx] = 1'b0; // always invalid + // Second mux + hashed_tokens_valid1 = '0; + hashed_tokens_valid1[ZeroTokenIdx] = 1'b1; // always valid + hashed_tokens_valid1[RawUnlockTokenIdx] = 1'b1; // always valid + hashed_tokens_valid1[TestUnlockTokenIdx] = caliptra_ss_lc_tx_test_true_strict(test_tokens_valid[6]); + hashed_tokens_valid1[TestExitTokenIdx] = caliptra_ss_lc_tx_test_true_strict(test_tokens_valid[7]); + hashed_tokens_valid1[RmaTokenIdx] = caliptra_ss_lc_tx_test_true_strict(rma_token_valid[3]); + hashed_tokens_valid1[InvalidTokenIdx] = 1'b0; // always invalid + end + + // SEC_CM: STATE.CONFIG.SPARSE + // The trans_target_i signal comes from the CSR and uses a replication encoding, + // hence we can use different indices of the array. + assign token_idx0 = (int'(dec_caliptra_ss_lc_state_o[0]) < NumLcStates && + int'(trans_target_i[0]) < NumLcStates) ? + TransTokenIdxMatrix[dec_caliptra_ss_lc_state_o[0]][trans_target_i[0]] : + InvalidTokenIdx; + assign token_idx1 = (int'(dec_caliptra_ss_lc_state_o[1]) < NumLcStates && + int'(trans_target_i[1]) < NumLcStates) ? + TransTokenIdxMatrix[dec_caliptra_ss_lc_state_o[1]][trans_target_i[1]] : + InvalidTokenIdx; + assign hashed_token_mux = {hashed_tokens_lower[token_idx0], + hashed_tokens_upper[token_idx1]}; + assign hashed_token_valid_mux = {hashed_tokens_valid0[token_idx0], + hashed_tokens_valid1[token_idx1]}; + + // If the indices are inconsistent, we also trigger a transition error. + // We do not trigger an alert right away if this happens, since it could + // be due to an invalid value programmed to the CSRs. + logic trans_invalid_error; + assign trans_invalid_error_o = trans_invalid_error || (token_idx0 != token_idx1); + + //////////////////////////////////////////////////////////////////// + // Decoding and transition logic for redundantly encoded LC state // + //////////////////////////////////////////////////////////////////// + + // This decodes the state into a format that can be exposed in the CSRs, + // and flags any errors in the state encoding. Errors will move the + // main FSM into INVALID right away. + caliptra_ss_lc_ctrl_state_decode u_caliptra_ss_lc_ctrl_state_decode ( + .caliptra_ss_lc_state_valid_i ( caliptra_ss_lc_state_valid_q ), + .caliptra_ss_lc_state_i ( caliptra_ss_lc_state_q ), + .caliptra_ss_lc_cnt_i ( caliptra_ss_lc_cnt_q ), + .secrets_valid_i, + .fsm_state_i ( fsm_state_q ), + .dec_caliptra_ss_lc_state_o, + .dec_caliptra_ss_lc_id_state_o, + .dec_caliptra_ss_lc_cnt_o, + .state_invalid_error_o (state_invalid_error) + ); + + // LC transition checker logic and next state generation. + caliptra_ss_lc_ctrl_state_transition #( + .SecVolatileRawUnlockEn(SecVolatileRawUnlockEn) + ) u_caliptra_ss_lc_ctrl_state_transition ( + .caliptra_ss_lc_state_i ( caliptra_ss_lc_state_q ), + .caliptra_ss_lc_cnt_i ( caliptra_ss_lc_cnt_q ), + .dec_caliptra_ss_lc_state_i ( dec_caliptra_ss_lc_state_o ), + .fsm_state_i ( fsm_state_q ), + .trans_target_i, + .volatile_raw_unlock_i, + .trans_cmd_i, + .next_caliptra_ss_lc_state_o ( next_caliptra_ss_lc_state ), + .next_caliptra_ss_lc_cnt_o ( next_caliptra_ss_lc_cnt ), + .trans_cnt_oflw_error_o, + .trans_invalid_error_o ( trans_invalid_error ) + ); + + // LC signal decoder and broadcasting logic. + caliptra_ss_lc_ctrl_signal_decode #( + .RndCnstLcKeymgrDivInvalid ( RndCnstLcKeymgrDivInvalid ), + .RndCnstLcKeymgrDivTestUnlocked( RndCnstLcKeymgrDivTestUnlocked ), + .RndCnstLcKeymgrDivDev ( RndCnstLcKeymgrDivDev ), + .RndCnstLcKeymgrDivProduction ( RndCnstLcKeymgrDivProduction ), + .RndCnstLcKeymgrDivRma ( RndCnstLcKeymgrDivRma ) + ) u_caliptra_ss_lc_ctrl_signal_decode ( + .clk_i, + .rst_ni, + .caliptra_ss_lc_state_valid_i ( caliptra_ss_lc_state_valid_q ), + .caliptra_ss_lc_state_i ( caliptra_ss_lc_state_q ), + .secrets_valid_i, + .fsm_state_i ( fsm_state_q ), + .caliptra_ss_lc_raw_test_rma_o, + .caliptra_ss_lc_dft_en_o, + .caliptra_ss_lc_nvm_debug_en_o, + .caliptra_ss_lc_hw_debug_en_o, + .caliptra_ss_lc_cpu_en_o, + .caliptra_ss_lc_creator_seed_sw_rw_en_o, + .caliptra_ss_lc_owner_seed_sw_rw_en_o, + .caliptra_ss_lc_iso_part_sw_rd_en_o, + .caliptra_ss_lc_iso_part_sw_wr_en_o, + .caliptra_ss_lc_seed_hw_rd_en_o, + .caliptra_ss_lc_keymgr_en_o, + .caliptra_ss_lc_escalate_en_o, + .caliptra_ss_lc_keymgr_div_o + ); + + + // Conditional signals set by main FSM. + caliptra_prim_lc_sender u_caliptra_prim_lc_sender_clk_byp_req ( + .clk_i, + .rst_ni, + .lc_en_i(caliptra_ss_lc_clk_byp_req), + .lc_en_o(caliptra_ss_lc_clk_byp_req_o) + ); + caliptra_prim_lc_sender u_caliptra_prim_lc_sender_flash_rma_req ( + .clk_i, + .rst_ni, + .lc_en_i(caliptra_ss_lc_flash_rma_req), + .lc_en_o(caliptra_ss_lc_flash_rma_req_o) + ); + caliptra_prim_lc_sender u_caliptra_prim_lc_sender_check_byp_en ( + .clk_i, + .rst_ni, + .lc_en_i(caliptra_ss_lc_check_byp_en), + .lc_en_o(caliptra_ss_lc_check_byp_en_o) + ); + + //////////////// + // Assertions // + //////////////// + + `CALIPTRA_ASSERT(EscStaysOnOnceAsserted_A, + caliptra_ss_lc_tx_test_true_strict(caliptra_ss_lc_escalate_en_o) + |=> + caliptra_ss_lc_tx_test_true_strict(caliptra_ss_lc_escalate_en_o)) + + `CALIPTRA_ASSERT(ClkBypStaysOnOnceAsserted_A, + caliptra_ss_lc_tx_test_true_strict(caliptra_ss_lc_clk_byp_req_o) + |=> + caliptra_ss_lc_tx_test_true_strict(caliptra_ss_lc_clk_byp_req_o)) + + `CALIPTRA_ASSERT(FlashRmaStaysOnOnceAsserted_A, + caliptra_ss_lc_tx_test_true_strict(caliptra_ss_lc_flash_rma_req_o) + |=> + caliptra_ss_lc_tx_test_true_strict(caliptra_ss_lc_flash_rma_req_o)) + + `CALIPTRA_ASSERT(NoClkBypInProdStates_A, + caliptra_ss_lc_state_q inside {LcStProd, LcStProdEnd, LcStDev} + |=> + caliptra_ss_lc_tx_test_false_strict(caliptra_ss_lc_clk_byp_req_o)) + + `CALIPTRA_ASSERT(SecCmCFITerminal0_A, + fsm_state_q == PostTransSt + |=> + fsm_state_q inside {PostTransSt, InvalidSt, EscalateSt}) + + `CALIPTRA_ASSERT(SecCmCFITerminal1_A, + fsm_state_q == ScrapSt + |=> + fsm_state_q inside {ScrapSt, InvalidSt, EscalateSt}) + + `CALIPTRA_ASSERT(SecCmCFITerminal2_A, + fsm_state_q == EscalateSt + |=> + fsm_state_q == EscalateSt) + + `CALIPTRA_ASSERT(SecCmCFITerminal3_A, + fsm_state_q == InvalidSt + |=> + fsm_state_q inside {InvalidSt, EscalateSt}) + + // Check that the FSM is linear and does not contain any loops + `CALIPTRA_ASSERT_FPV_LINEAR_FSM(SecCmCFILinear_A, fsm_state_q, fsm_state_e) + +endmodule : caliptra_ss_lc_ctrl_fsm diff --git a/src/caliptra_ss_lc_ctrl/rtl/caliptra_ss_lc_ctrl_keymgr_pkg.sv b/src/caliptra_ss_lc_ctrl/rtl/caliptra_ss_lc_ctrl_keymgr_pkg.sv new file mode 100644 index 0000000..13347a2 --- /dev/null +++ b/src/caliptra_ss_lc_ctrl/rtl/caliptra_ss_lc_ctrl_keymgr_pkg.sv @@ -0,0 +1,278 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// key manager package +// + +package caliptra_ss_lc_ctrl_keymgr_pkg; + + parameter int KeyWidth = 256; + parameter int CDIs = 2; // 2 different CDIs, sealing / attestation + parameter int CdiWidth = caliptra_prim_util_pkg::vbits(CDIs); + parameter int OtbnKeyWidth = 384; + parameter int DigestWidth = 128; // uses truncated hash + parameter int KmacDataIfWidth = 64; // KMAC interface data width + parameter int KeyMgrStages = 3; // Number of key manager stages (creator, ownerInt, owner) + parameter int SwBindingWidth = 32 * 1; + parameter int SaltWidth = 32 * 1; + parameter int Shares = 2; // number of key shares + parameter int EdnWidth = 1; + parameter int KeyVersionWidth = 32; // Key version length for individual DICE stage + + // These should be defined in another module's package + parameter int HealthStateWidth = 128; + parameter int DevIdWidth = 256; + parameter int MaxWidth = 256; + + // Default seeds + // These are generated using random.org byte dumper + typedef logic [KeyWidth-1:0] seed_t; + parameter seed_t RndCnstRevisionSeedDefault = + 256'h3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9; + parameter seed_t RndCnstCreatorIdentitySeedDefault = + 256'h6d234651d535ebb0dce4d82f503096614355fc7b84595e4f67a866177d421df6; + parameter seed_t RndCnstOwnerIntIdentitySeedDefault = + 256'hdba98db4fb1413b32fd5a4deac3ce546966a4bc2761235643358c8e76083d382; + parameter seed_t RndCnstOwnerIdentitySeedDefault = + 256'h8c0a27ef53e0e0bf5f5f5e26a30a0d0db10761ed802c6d2fd22873209976021e; + parameter seed_t RndCnstSoftOutputSeedDefault = + 256'h99cadb2c2d9b438591d943a89bc64dbb3bc2abc842eeea5faf74d27f7a7c99b6; + parameter seed_t RndCnstHardOutputSeedDefault = + 256'hd551b351decbb6f687c7f5c845363f12d6411fae812e16b23bc8ae59885a56b1; + + // Target based deriviation seeds + // These are used during the generation stages for sideload + parameter seed_t RndCnstNoneSeedDefault = + 256'h6EECBF9FC3C64230421DA1EAEC48F871070A3582E71AD4059D5D550784E9B9DE; + parameter seed_t RndCnstAesSeedDefault = + 256'hC1104CD94EBA084FA6438188038006489F3DF38771214AE0BBA65CEB9BC2366F; + parameter seed_t RndCnstKmacSeedDefault = + 256'h0A5CCCD9627BF6169B3A765D3D6D0CD89DBDCB7B6DF8D3C03746D60A0145D3ED; + parameter seed_t RndCnstOtbnSeedDefault = + 256'h17B0AF865F8ACDDFC7580C2B7BC3FB33FC9BB5A4B292216C123ACF99A7861F96; + parameter seed_t RndCnstCdiDefault = + 256'hC69C544D153A692AEEC4A0887BD5255F5C588C63A8BD94479BCFF7432DC55E3B; + + // Default Lfsr configurations + // These LFSR parameters have been generated with + // $ util/design/gen-lfsr-seed.py --width 64 --seed 691876113 --prefix "" + parameter int LfsrWidth = 64; + typedef logic [LfsrWidth-1:0] lfsr_seed_t; + typedef logic [LfsrWidth-1:0][$clog2(LfsrWidth)-1:0] lfsr_perm_t; + parameter lfsr_seed_t RndCnstLfsrSeedDefault = 64'h22d326255bd24320; + parameter lfsr_perm_t RndCnstLfsrPermDefault = { + 128'h16108c9f9008aa37e5118d1ec1df64a7, + 256'h24f3f1b73537f42d38383ee8f897286df81d49ab54b6bbbb666cbd1a16c41252 + }; + + // Random permutation + parameter int RandWidth = LfsrWidth / 2; + typedef logic [RandWidth-1:0][$clog2(RandWidth)-1:0] rand_perm_t; + parameter rand_perm_t RndCnstRandPermDefault = { + 160'h62089181d2a6be2ce145e2e27099ededbd7dceb0 + }; + + // Width calculations + // These are the largest calculations in use across all stages + parameter int AdvDataWidth = SwBindingWidth + 2*KeyWidth + DevIdWidth + HealthStateWidth; + parameter int IdDataWidth = KeyWidth; + // key version + salt + key ID + constant + parameter int GenDataWidth = 32 + SaltWidth + KeyWidth*2; + parameter int StageWidth = $clog2(KeyMgrStages); + // Max Payload Width to derivation function + // see security strength description https://keccak.team/keccak.html + // The max width here is chosen arbitrarily to ensure we do not get out of hand. + // Since KMAC is a MAC operation, the data can be as long as we need. + parameter int KDFMaxWidth = 1984; + + // Enumeration for operations + typedef enum logic [1:0] { + Creator, + OwnerInt, + Owner, + Disable + } keymgr_stage_e; + + // Enumeration for sideload sel + typedef enum logic [1:0] { + None, + Aes, + Kmac, + Otbn + } keymgr_key_dest_e; + + // Enumeration for actual key slot idx + typedef enum logic [1:0] { + AesIdx, + KmacIdx, + OtbnIdx, + LastIdx + } keymgr_sideload_slot_idx_e; + + // Enumeration for key select + typedef enum logic { + HwKey = 0, + SwKey = 1 + } keymgr_gen_out_e; + + // Enumeration for operation + typedef enum logic [2:0] { + OpAdvance = 0, + OpGenId = 1, + OpGenSwOut = 2, + OpGenHwOut = 3, + OpDisable = 4 + } keymgr_ops_e; + + // Enumeration for working state exposed to software + typedef enum logic [2:0] { + StReset, + StInit, + StCreatorRootKey, + StOwnerIntKey, + StOwnerKey, + StDisabled, + StInvalid + } keymgr_working_state_e; + + // Enumeration for operation status + typedef enum logic [1:0] { + OpIdle = 0, + OpWip = 1, + OpDoneSuccess = 2, + OpDoneFail = 3 + } keymgr_op_status_e; + + // keymgr has 4 categories of errors + // sync errors - recoverable errors that happen during keymgr operation + // async errors - recoverable errors that happen asynchronously + // sync faults - fatal errors that happen during keymgr operation + // async faults - fatal errors that happen asynchronously + + typedef enum logic [1:0] { + SyncErrInvalidOp, + SyncErrInvalidIn, + SyncErrLastIdx + } keymgr_sync_error_e; + + typedef enum logic [1:0] { + AsyncErrShadowUpdate, + AsyncErrLastIdx + } keymgr_async_error_e; + + typedef enum logic [1:0] { + SyncFaultKmacOp, + SyncFaultKmacOut, + SyncFaultSideSel, + SyncFaultLastIdx + } keymgr_sync_fault_e; + + typedef enum logic [3:0] { + AsyncFaultKmacCmd, + AsyncFaultKmacFsm, + AsyncFaultKmacDone, + AsyncFaultRegIntg, + AsyncFaultShadow, + AsyncFaultFsmIntg, + AsyncFaultFsmChk, + AsyncFaultCntErr, + AsyncFaultRCntErr, + AsyncFaultSideErr, + AsyncFaultKeyEcc, + AsyncFaultLastIdx + } keymgr_async_fault_e; + + + // Bit position of error code + // Error is encoded as 1 error per bit + typedef enum logic [2:0] { + ErrInvalidOp, + ErrInvalidIn, + ErrShadowUpdate, + ErrLastPos + } keymgr_err_pos_e; + + // Bit position of fault status + typedef enum logic [3:0] { + FaultKmacCmd, + FaultKmacFsm, + FaultKmacDone, + FaultKmacOp, + FaultKmacOut, + FaultRegIntg, + FaultShadow, + FaultCtrlFsm, + FaultCtrlFsmChk, + FaultCtrlCnt, + FaultReseedCnt, + FaultSideFsm, + FaultSideSel, + FaultKeyEcc, + FaultLastPos + } keymgr_fault_pos_e; + + typedef enum logic [2:0] { + KeyUpdateIdle, + KeyUpdateRandom, + KeyUpdateRoot, + KeyUpdateKmac, + KeyUpdateWipe + } keymgr_key_update_e; + + typedef enum logic [2:0] { + SideLoadClrIdle, + SideLoadClrAes, + SideLoadClrKmac, + SideLoadClrOtbn + } keymgr_sideload_clr_e; + + // Key connection to various symmetric modules + typedef struct packed { + logic valid; + logic [Shares-1:0][KeyWidth-1:0] key; + } hw_key_req_t; + + // Key connection to otbn + typedef struct packed { + logic valid; + logic [Shares-1:0][OtbnKeyWidth-1:0] key; + } otbn_key_req_t; + + parameter hw_key_req_t HW_KEY_REQ_DEFAULT = '{ + valid: 1'b0, + key: {Shares{KeyWidth'(32'hDEADBEEF)}} + }; + + parameter otbn_key_req_t OTBN_KEY_REQ_DEFAULT = '{ + valid: 1'b0, + key: {Shares{OtbnKeyWidth'(32'hDEADBEEF)}} + }; + + // The following structs should be sourced from other modules + // defined here temporarily + + // lc keymgr enable usage + typedef enum logic [1:0] { + KeyMgrEnCtrl, + KeyMgrEnCfgEn, + KeyMgrEnSwBindingEn, + KeyMgrEnLast + } keymgr_caliptra_ss_lc_en_usage_e; + + // perm_data + function automatic logic[RandWidth-1:0] perm_data (logic [RandWidth-1:0] data, + rand_perm_t perm_sel); + + for (int k = 0; k < 32; k++) begin : gen_data_loop + perm_data[k] = data[perm_sel[k]]; + end + + endfunction + + // checks for all 0's or all 1's of value + function automatic logic valid_data_chk (logic [KeyWidth-1:0] value); + return |value & ~&value; + endfunction + +endpackage : caliptra_ss_lc_ctrl_keymgr_pkg diff --git a/src/caliptra_ss_lc_ctrl/rtl/caliptra_ss_lc_ctrl_kmac_if.sv b/src/caliptra_ss_lc_ctrl/rtl/caliptra_ss_lc_ctrl_kmac_if.sv new file mode 100644 index 0000000..711519c --- /dev/null +++ b/src/caliptra_ss_lc_ctrl/rtl/caliptra_ss_lc_ctrl_kmac_if.sv @@ -0,0 +1,213 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Synchronization interface between LC FSM and KMAC. +// + +`include "caliptra_prim_assert.sv" + +module caliptra_ss_lc_ctrl_kmac_if + import caliptra_ss_lc_ctrl_pkg::*; + import caliptra_ss_lc_ctrl_state_pkg::*; +( + // Life cycle controller clock + input clk_i, + input rst_ni, + // Clock for KMAC interface + input clk_kmac_i, + input rst_kmac_ni, + // Life cycle hashing interface for raw unlock + // Synchronized in the life cycle controller. + input kmac_pkg::app_rsp_t kmac_data_i, + output kmac_pkg::app_req_t kmac_data_o, + // Token hashing interface to LC FSM' + input caliptra_ss_lc_token_t transition_token_i, + input token_hash_req_i, + // Used for gating assertions inside CDC caliptra_primitives. + input token_hash_req_chk_i, + output logic token_hash_ack_o, + output logic token_hash_err_o, + output logic token_if_fsm_err_o, + output caliptra_ss_lc_token_t hashed_token_o +); + + ////////////////////////////////////// + // Data and Handshake Synchronizers // + ////////////////////////////////////// + + + // The transition_token_i register is guaranteed to remain stable once a life cycle + // transition has been initiated. + // Hence no further synchronization registers are required on the outgoing data. + caliptra_ss_lc_token_t kmac_transition_token; + assign kmac_transition_token = transition_token_i; + + // SRC domain cannot change data while waiting for ACK. + `CALIPTRA_ASSERT(DataStable_A, token_hash_req_i && !token_hash_ack_o |-> $stable(transition_token_i)) + + // Second synchronizer instance for handshake and return data synchronization. + logic kmac_req, kmac_ack; + logic token_hash_req; + logic token_hash_ack_d, token_hash_ack_q; + logic token_hash_err_q, token_hash_err_d; + caliptra_ss_lc_token_t hashed_token_q, hashed_token_d; + caliptra_prim_sync_reqack_data #( + // Token + Error bit + .Width (LcTokenWidth + 1), + .DataSrc2Dst(1'b0), + // This instantiates a data register + // on the destination side. + .DataReg (1'b1) + ) u_caliptra_prim_sync_reqack_data_in ( + .clk_src_i ( clk_i ), + .rst_src_ni ( rst_ni ), + .clk_dst_i ( clk_kmac_i ), + .rst_dst_ni ( rst_kmac_ni ), + .req_chk_i ( token_hash_req_chk_i ), + .src_req_i ( token_hash_req ), + .src_ack_o ( token_hash_ack_d ), + .dst_req_o ( kmac_req ), + .dst_ack_i ( kmac_ack ), + // Truncate hash to 128bit and remove masking (not required here). + .data_i ( {kmac_data_i.error, + kmac_data_i.digest_share0[LcTokenWidth-1:0] ^ + kmac_data_i.digest_share1[LcTokenWidth-1:0]} ), + .data_o ( {token_hash_err_d, + hashed_token_d} ) + ); + + logic unused_sigs; + assign unused_sigs = ^{ + kmac_data_i.digest_share0[LcTokenWidth +: (kmac_pkg::AppDigestW - LcTokenWidth)], + kmac_data_i.digest_share1[LcTokenWidth +: (kmac_pkg::AppDigestW - LcTokenWidth)] + }; + + // Hashed Token Register Running on LC Clock + always_ff @(posedge clk_i or negedge rst_ni) begin : p_caliptra_ss_lc_regs + if (!rst_ni) begin + token_hash_ack_q <= 1'b0; + token_hash_err_q <= 1'b0; + hashed_token_q <= {LcTokenWidth{1'b1}}; + end else begin + token_hash_ack_q <= token_hash_ack_d; + // Latch synchronized token and error bit + if (token_hash_req_i && token_hash_ack_d) begin + token_hash_err_q <= token_hash_err_d; + hashed_token_q <= hashed_token_d; + end + end + end + + assign token_hash_ack_o = token_hash_ack_q; + assign token_hash_err_o = token_hash_err_q; + assign hashed_token_o = hashed_token_q; + + // Stop requesting tokens upon latching on LC side. + assign token_hash_req = token_hash_req_i & ~token_hash_ack_q; + + // Need to synchronize this error signal separately. + logic kmac_fsm_err_d, kmac_fsm_err_q; + caliptra_prim_flop_2sync #( + .Width(1), + .ResetValue(0) + ) u_caliptra_prim_flop_2sync ( + .clk_i, + .rst_ni, + .d_i(kmac_fsm_err_q), + .q_o(token_if_fsm_err_o) + ); + + ///////////////////////////////////////////// + // Serialization FSM Running on KMAC Clock // + ///////////////////////////////////////////// + + // SEC_CM: KMAC.FSM.SPARSE + // Encoding generated with: + // $ ./util/design/sparse-fsm-encode.py -d 5 -m 4 -n 8 \ + // -s 3343913945 --language=sv + // + // Hamming distance histogram: + // + // 0: -- + // 1: -- + // 2: -- + // 3: -- + // 4: -- + // 5: |||||||||||||||||||| (66.67%) + // 6: |||||||||| (33.33%) + // 7: -- + // 8: -- + // + // Minimum Hamming distance: 5 + // Maximum Hamming distance: 6 + // Minimum Hamming weight: 2 + // Maximum Hamming weight: 6 + // + localparam int StateWidth = 8; + typedef enum logic [StateWidth-1:0] { + FirstSt = 8'b01011011, + SecondSt = 8'b10010100, + WaitSt = 8'b11100111, + DoneSt = 8'b00101000 + } state_e; + + state_e state_d, state_q; + + // Serialize the 128bit token into two 64bit beats. + always_comb begin : p_kmac + state_d = state_q; + kmac_data_o = '0; + kmac_ack = 1'b0; + kmac_fsm_err_d = 1'b0; + + unique case (state_q) + // Wait for request and transfer first half of + // LC token. + FirstSt: begin + if (kmac_req) begin + kmac_data_o.valid = 1'b1; + kmac_data_o.strb = 8'hFF; + kmac_data_o.data = kmac_transition_token[0 +: 64]; + if (kmac_data_i.ready) begin + state_d = SecondSt; + end + end + end + // Transfer second half of LC token. + SecondSt: begin + kmac_data_o.valid = 1'b1; + kmac_data_o.strb = 8'hFF; + kmac_data_o.last = 1'b1; + kmac_data_o.data = kmac_transition_token[64 +: 64]; + if (kmac_data_i.ready) begin + state_d = WaitSt; + end + end + // Wait for hashed token response and go to terminal state. + WaitSt: begin + if (kmac_data_i.done) begin + kmac_ack = 1'b1; + state_d = DoneSt; + end + end + // Terminal state (by design we can only perform + // one token hashing operation per reset cycle). + DoneSt: ; + default: begin + kmac_fsm_err_d = 1'b1; + end + endcase // state_q + end + + `CALIPTRA_PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, FirstSt, clk_kmac_i, rst_kmac_ni) + + always_ff @(posedge clk_kmac_i or negedge rst_kmac_ni) begin : p_kmac_fsm_err + if (!rst_kmac_ni) begin + kmac_fsm_err_q <= 1'b0; + end else begin + kmac_fsm_err_q <= kmac_fsm_err_d; + end + end + +endmodule : caliptra_ss_lc_ctrl_kmac_if diff --git a/src/caliptra_ss_lc_ctrl/rtl/caliptra_ss_lc_ctrl_pkg.sv b/src/caliptra_ss_lc_ctrl/rtl/caliptra_ss_lc_ctrl_pkg.sv new file mode 100644 index 0000000..02eb54c --- /dev/null +++ b/src/caliptra_ss_lc_ctrl/rtl/caliptra_ss_lc_ctrl_pkg.sv @@ -0,0 +1,365 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// + +`include "caliptra_prim_assert.sv" + +package caliptra_ss_lc_ctrl_pkg; + + import caliptra_prim_util_pkg::vbits; + import caliptra_ss_lc_ctrl_state_pkg::*; + + /////////////////////////////////////// + // Netlist Constants (Hashed Tokens) // + /////////////////////////////////////// + + parameter int NumTokens = 6; + parameter int TokenIdxWidth = vbits(NumTokens); + typedef enum logic [TokenIdxWidth-1:0] { + // This is the index for the hashed all-zero constant. + // All unconditional transitions use this token. + ZeroTokenIdx = 3'h0, + RawUnlockTokenIdx = 3'h1, + TestUnlockTokenIdx = 3'h2, + TestExitTokenIdx = 3'h3, + RmaTokenIdx = 3'h4, + // This is the index for an all-zero value (i.e., hashed value = '0). + // This is used as an additional blocker for some invalid state transition edges. + InvalidTokenIdx = 3'h5 + } token_idx_e; + + parameter int TokenMuxBits = 2**TokenIdxWidth*LcTokenWidth; + typedef logic [TokenMuxBits-1:0] caliptra_ss_lc_token_mux_t; + + //////////////////////////////// + // Typedefs for LC Interfaces // + //////////////////////////////// + + parameter int TxWidth = 4; + + // Note that changing this encoding has implications on isolation cell + // values in RTL. Do not change this unless absolutely needed. + typedef enum logic [TxWidth-1:0] { + On = 4'b0101, + Off = 4'b1010 + } caliptra_ss_lc_tx_t; + + parameter caliptra_ss_lc_tx_t LC_TX_DEFAULT = caliptra_ss_lc_tx_t'(Off); + + parameter int RmaSeedWidth = 32; + typedef logic [RmaSeedWidth-1:0] caliptra_ss_lc_flash_rma_seed_t; + parameter caliptra_ss_lc_flash_rma_seed_t LC_FLASH_RMA_SEED_DEFAULT = '0; + + parameter int LcKeymgrDivWidth = 128; + typedef logic [LcKeymgrDivWidth-1:0] caliptra_ss_lc_keymgr_div_t; + + typedef struct packed { + logic [caliptra_ss_lc_ctrl_reg_pkg::SiliconCreatorIdWidth-1:0] silicon_creator_id; + logic [caliptra_ss_lc_ctrl_reg_pkg::ProductIdWidth-1:0] product_id; + logic [caliptra_ss_lc_ctrl_reg_pkg::RevisionIdWidth-1:0] revision_id; + logic [32-caliptra_ss_lc_ctrl_reg_pkg::RevisionIdWidth-1:0] reserved; + } caliptra_ss_lc_hw_rev_t; + + ///////////////////////////////////////////// + // Helper Functions for Life Cycle Signals // + ///////////////////////////////////////////// + + // This is a prerequisite for the multibit functions below to work. + `CALIPTRA_ASSERT_STATIC_IN_PACKAGE(CheckLcTxValsComplementary_A, On == ~Off) + // Check for bit-width matching between caliptra_ss_lc_tx_t and mubi4_t + `CALIPTRA_ASSERT_STATIC_IN_PACKAGE(LcMuBiWidthCheck_A, $bits(TxWidth) == $bits(caliptra_prim_mubi_pkg::MuBi4Width)) + + // Convert a life cycle signal to mubi4 + // If in the future other versions are desired, this should really be + // moved to caliptra_prim_mubi_pkg + // + // The On ^ MuBi4True determines the bit differences between + // an caliptra_ss_lc_ctrl_pkg::On and caliptra_prim_mubi_pkg::MuBi4True. + // Once the required inversions are determined, it is then applied + // to the incoming value. If the incoming value is true, it will + // appropriately flip to the correct MuBiValue. + // Since the false value is always complement of the true value, + // this mechanism will also work for the other polarity. + function automatic caliptra_prim_mubi_pkg::mubi4_t caliptra_ss_lc_to_mubi4(caliptra_ss_lc_tx_t val); + return caliptra_prim_mubi_pkg::mubi4_t'(val ^ (On ^ caliptra_prim_mubi_pkg::MuBi4True)); + endfunction : caliptra_ss_lc_to_mubi4 + + function automatic caliptra_ss_lc_tx_t mubi4_to_lc(caliptra_prim_mubi_pkg::mubi4_t val); + return caliptra_ss_lc_tx_t'(val ^ (caliptra_prim_mubi_pkg::MuBi4True ^ On)); + endfunction : mubi4_to_lc + + // same function as above, but for an input that is MuBi4True, return Off + // for an input that is MuBi4False, return On + function automatic caliptra_ss_lc_tx_t mubi4_to_caliptra_ss_lc_inv(caliptra_prim_mubi_pkg::mubi4_t val); + return caliptra_ss_lc_tx_t'(val ^ (caliptra_prim_mubi_pkg::MuBi4True ^ Off)); + endfunction : mubi4_to_caliptra_ss_lc_inv + + // Test whether the value is supplied is one of the valid enumerations + function automatic logic caliptra_ss_lc_tx_test_invalid(caliptra_ss_lc_tx_t val); + return ~(val inside {On, Off}); + endfunction : caliptra_ss_lc_tx_test_invalid + + // Convert a 1 input value to a caliptra_ss_lc_tx output + function automatic caliptra_ss_lc_tx_t caliptra_ss_lc_tx_bool_to_caliptra_ss_lc_tx(logic val); + return (val ? On : Off); + endfunction : caliptra_ss_lc_tx_bool_to_caliptra_ss_lc_tx + + // Test whether the multibit value signals an "enabled" condition. + // The strict version of this function requires + // the multibit value to equal True. + function automatic logic caliptra_ss_lc_tx_test_true_strict(caliptra_ss_lc_tx_t val); + return On == val; + endfunction : caliptra_ss_lc_tx_test_true_strict + + // Test whether the multibit value signals a "disabled" condition. + // The strict version of this function requires + // the multibit value to equal False. + function automatic logic caliptra_ss_lc_tx_test_false_strict(caliptra_ss_lc_tx_t val); + return Off == val; + endfunction : caliptra_ss_lc_tx_test_false_strict + + // Test whether the multibit value signals an "enabled" condition. + // The loose version of this function interprets all + // values other than False as "enabled". + function automatic logic caliptra_ss_lc_tx_test_true_loose(caliptra_ss_lc_tx_t val); + return Off != val; + endfunction : caliptra_ss_lc_tx_test_true_loose + + // Test whether the multibit value signals a "disabled" condition. + // The loose version of this function interprets all + // values other than True as "disabled". + function automatic logic caliptra_ss_lc_tx_test_false_loose(caliptra_ss_lc_tx_t val); + return On != val; + endfunction : caliptra_ss_lc_tx_test_false_loose + + + // Performs a logical OR operation between two multibit values. + // This treats "act" as logical 1, and all other values are + // treated as 0. Truth table: + // + // A | B | OUT + //------+------+----- + // !act | !act | !act + // act | !act | act + // !act | act | act + // act | act | act + // + // Note: due to the nature of the caliptra_ss_lc_tx_or() function, it is possible that two + // non-strictly "act" values may produce a strictly "act" value. If this is + // of concern, e.g. if the output is consumed with a strict check on "act", + // consider using the caliptra_prim_caliptra_ss_lc_or_hardened caliptra_primitive instead. + function automatic caliptra_ss_lc_tx_t caliptra_ss_lc_tx_or(caliptra_ss_lc_tx_t a, caliptra_ss_lc_tx_t b, caliptra_ss_lc_tx_t act); + logic [TxWidth-1:0] a_in, b_in, act_in, out; + a_in = a; + b_in = b; + act_in = act; + for (int k = 0; k < TxWidth; k++) begin + if (act_in[k]) begin + out[k] = a_in[k] || b_in[k]; + end else begin + out[k] = a_in[k] && b_in[k]; + end + end + return caliptra_ss_lc_tx_t'(out); + endfunction : caliptra_ss_lc_tx_or + + // Performs a logical AND operation between two multibit values. + // This treats "act" as logical 1, and all other values are + // treated as 0. Truth table: + // + // A | B | OUT + //------+------+----- + // !act | !act | !act + // act | !act | !act + // !act | act | !act + // act | act | act + // + // Noite: The caliptra_ss_lc_tx_and() function does not suffer from the strictness problem + // that the caliptra_ss_lc_tx_or function above does, since only one output value in the + // truth table is strictly "act". It can hence be used in most scenarios without issues. + // If however the caliptra_ss_lc_tx_and() function should be strictly rectifying (i.e., only + // output "act" or ~"act"), the caliptra_prim_caliptra_ss_lc_and_hardened can be used. + function automatic caliptra_ss_lc_tx_t caliptra_ss_lc_tx_and(caliptra_ss_lc_tx_t a, caliptra_ss_lc_tx_t b, caliptra_ss_lc_tx_t act); + logic [TxWidth-1:0] a_in, b_in, act_in, out; + a_in = a; + b_in = b; + act_in = act; + for (int k = 0; k < TxWidth; k++) begin + if (act_in[k]) begin + out[k] = a_in[k] && b_in[k]; + end else begin + out[k] = a_in[k] || b_in[k]; + end + end + return caliptra_ss_lc_tx_t'(out); + endfunction : caliptra_ss_lc_tx_and + + // Performs a logical OR operation between two multibit values. + // This treats "True" as logical 1, and all other values are + // treated as 0. + function automatic caliptra_ss_lc_tx_t caliptra_ss_lc_tx_or_hi(caliptra_ss_lc_tx_t a, caliptra_ss_lc_tx_t b); + return caliptra_ss_lc_tx_or(a, b, On); + endfunction : caliptra_ss_lc_tx_or_hi + + // Performs a logical AND operation between two multibit values. + // This treats "True" as logical 1, and all other values are + // treated as 0. + function automatic caliptra_ss_lc_tx_t caliptra_ss_lc_tx_and_hi(caliptra_ss_lc_tx_t a, caliptra_ss_lc_tx_t b); + return caliptra_ss_lc_tx_and(a, b, On); + endfunction : caliptra_ss_lc_tx_and_hi + + // Performs a logical OR operation between two multibit values. + // This treats "False" as logical 1, and all other values are + // treated as 0. + function automatic caliptra_ss_lc_tx_t caliptra_ss_lc_tx_or_lo(caliptra_ss_lc_tx_t a, caliptra_ss_lc_tx_t b); + return caliptra_ss_lc_tx_or(a, b, Off); + endfunction : caliptra_ss_lc_tx_or_lo + + // Performs a logical AND operation between two multibit values. + // Tlos treats "False" as logical 1, and all other values are + // treated as 0. + function automatic caliptra_ss_lc_tx_t caliptra_ss_lc_tx_and_lo(caliptra_ss_lc_tx_t a, caliptra_ss_lc_tx_t b); + return caliptra_ss_lc_tx_and(a, b, Off); + endfunction : caliptra_ss_lc_tx_and_lo + + // Inverts the logical meaning of the multibit value. + function automatic caliptra_ss_lc_tx_t caliptra_ss_lc_tx_inv(caliptra_ss_lc_tx_t a); + return caliptra_ss_lc_tx_t'(~TxWidth'(a)); + endfunction : caliptra_ss_lc_tx_inv + + //////////////////// + // Main FSM State // + //////////////////// + + // SEC_CM: MAIN.FSM.SPARSE + // Encoding generated with: + // $ ./util/design/sparse-fsm-encode.py -d 5 -m 15 -n 16 \ + // -s 2934212379 --language=sv + // + // Hamming distance histogram: + // + // 0: -- + // 1: -- + // 2: -- + // 3: -- + // 4: -- + // 5: ||||||| (7.62%) + // 6: ||||||||| (9.52%) + // 7: |||||||||||||||| (17.14%) + // 8: |||||||||||||||||||| (20.95%) + // 9: ||||||||||||||||| (18.10%) + // 10: ||||||||||||| (14.29%) + // 11: |||||| (6.67%) + // 12: ||| (3.81%) + // 13: | (1.90%) + // 14: -- + // 15: -- + // 16: -- + // + // Minimum Hamming distance: 5 + // Maximum Hamming distance: 13 + // Minimum Hamming weight: 3 + // Maximum Hamming weight: 11 + // + localparam int FsmStateWidth = 16; + typedef enum logic [FsmStateWidth-1:0] { + ResetSt = 16'b1111011010111100, + IdleSt = 16'b0000011110101101, + ClkMuxSt = 16'b1100111011001001, + CntIncrSt = 16'b0011001111000111, + CntProgSt = 16'b0000110001010100, + TransCheckSt = 16'b0110111010110000, + TokenHashSt = 16'b1101001000111111, + FlashRmaSt = 16'b1110100010001111, + TokenCheck0St = 16'b0010000011000000, + TokenCheck1St = 16'b1101010101101111, + TransProgSt = 16'b1000000110101011, + PostTransSt = 16'b0110110100101100, + ScrapSt = 16'b1010100001010001, + EscalateSt = 16'b1011110110011011, + InvalidSt = 16'b0011000101001100 + } fsm_state_e; + + /////////////////////////////////////////// + // Manufacturing State Transition Matrix // + /////////////////////////////////////////// + + // Helper macro to assemble the token index matrix below. + // From TEST_UNLOCKED(N) + // -> SCRAP, RMA + // -> PROD, PROD_END, DEV + // -> TEST_UNLOCKED(N+1)-7 + // -> TEST_LOCKED(N)-6 + // -> TEST_UNLOCKED0-(N), RAW + `define TEST_UNLOCKED(idx) \ + {2{ZeroTokenIdx}}, \ + {3{TestExitTokenIdx}}, \ + {(7-idx){InvalidTokenIdx, \ + ZeroTokenIdx}}, \ + {(2*idx+2){InvalidTokenIdx}} + + // Helper macro to assemble the token index matrix below. + // From TEST_LOCKED(N) + // -> SCRAP + // -> RMA + // -> PROD, PROD_END, DEV + // -> TEST_UNLOCKED(N+1)-7 + // -> TEST_LOCKED(N)-6 + // -> TEST_UNLOCKED0-(N), RAW + `define TEST_LOCKED(idx) \ + ZeroTokenIdx, \ + InvalidTokenIdx, \ + {3{TestExitTokenIdx}}, \ + {(7-idx){TestUnlockTokenIdx, \ + InvalidTokenIdx}}, \ + {(2*idx+2){InvalidTokenIdx}} + + // The token index matrix below encodes 1) which transition edges are valid and 2) which token + // to use for a given transition edge. Note that unconditional but otherwise valid transitions + // are assigned the ZeroTokenIdx, whereas invalid transitions are assigned an InvalidTokenIdx. + parameter token_idx_e [NumLcStates-1:0][NumLcStates-1:0] TransTokenIdxMatrix = { + // SCRAP + {21{InvalidTokenIdx}}, // -> TEST_LOCKED0-6, TEST_UNLOCKED0-7, DEV, PROD, PROD_END, RMA, SCRAP + // RMA + ZeroTokenIdx, // -> SCRAP + {20{InvalidTokenIdx}}, // -> TEST_LOCKED0-6, TEST_UNLOCKED0-7, DEV, PROD, PROD_END, RMA + // PROD_END + ZeroTokenIdx, // -> SCRAP + {20{InvalidTokenIdx}}, // -> TEST_LOCKED0-6, TEST_UNLOCKED0-7, DEV, PROD, PROD_END, RMA + // PROD + ZeroTokenIdx, // -> SCRAP + RmaTokenIdx, // -> RMA + {19{InvalidTokenIdx}}, // -> TEST_LOCKED0-6, TEST_UNLOCKED0-7, DEV, PROD, PROD_END + // DEV + ZeroTokenIdx, // -> SCRAP + RmaTokenIdx, // -> RMA + {19{InvalidTokenIdx}}, // -> TEST_LOCKED0-6, TEST_UNLOCKED0-7, DEV, PROD, PROD_END + // TEST_UNLOCKED0-7, TEST_LOCKED0-6 + `TEST_UNLOCKED(7), + `TEST_LOCKED(6), + `TEST_UNLOCKED(6), + `TEST_LOCKED(5), + `TEST_UNLOCKED(5), + `TEST_LOCKED(4), + `TEST_UNLOCKED(4), + `TEST_LOCKED(3), + `TEST_UNLOCKED(3), + `TEST_LOCKED(2), + `TEST_UNLOCKED(2), + `TEST_LOCKED(1), + `TEST_UNLOCKED(1), + `TEST_LOCKED(0), + `TEST_UNLOCKED(0), + // RAW + ZeroTokenIdx, // -> SCRAP + {4{InvalidTokenIdx}}, // -> RMA, PROD, PROD_END, DEV + {8{RawUnlockTokenIdx, // -> TEST_UNLOCKED0-7 + InvalidTokenIdx}} // -> RAW, TEST_LOCKED0-6 + }; + + // These macros are only used locally. + `undef TEST_LOCKED + `undef TEST_UNLOCKED + +endpackage : caliptra_ss_lc_ctrl_pkg diff --git a/src/caliptra_ss_lc_ctrl/rtl/caliptra_ss_lc_ctrl_reg_pkg.sv b/src/caliptra_ss_lc_ctrl/rtl/caliptra_ss_lc_ctrl_reg_pkg.sv new file mode 100644 index 0000000..33589cd --- /dev/null +++ b/src/caliptra_ss_lc_ctrl/rtl/caliptra_ss_lc_ctrl_reg_pkg.sv @@ -0,0 +1,385 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Package auto-generated by `reggen` containing data structure + +package caliptra_ss_lc_ctrl_reg_pkg; + + // Param list + parameter int SiliconCreatorIdWidth = 16; + parameter int ProductIdWidth = 16; + parameter int RevisionIdWidth = 8; + parameter int NumTokenWords = 4; + parameter int CsrLcStateWidth = 30; + parameter int CsrLcCountWidth = 5; + parameter int CsrLcIdStateWidth = 32; + parameter int CsrOtpTestCtrlWidth = 32; + parameter int CsrOtpTestStatusWidth = 32; + parameter int NumDeviceIdWords = 8; + parameter int NumManufStateWords = 8; + parameter int NumRmaAckSigs = 2; + parameter int NumAlerts = 3; + + // Address widths within the block + parameter int RegsAw = 8; + parameter int DmiAw = 12; + + /////////////////////////////////////////////// + // Typedefs for registers for regs interface // + /////////////////////////////////////////////// + + typedef struct packed { + struct packed { + logic q; + logic qe; + } fatal_bus_integ_error; + struct packed { + logic q; + logic qe; + } fatal_state_error; + struct packed { + logic q; + logic qe; + } fatal_prog_error; + } caliptra_ss_lc_ctrl_reg2hw_alert_test_reg_t; + + typedef struct packed { + logic [7:0] q; + logic qe; + } caliptra_ss_lc_ctrl_reg2hw_claim_transition_if_reg_t; + + typedef struct packed { + logic q; + logic qe; + } caliptra_ss_lc_ctrl_reg2hw_transition_cmd_reg_t; + + typedef struct packed { + struct packed { + logic q; + logic qe; + } volatile_raw_unlock; + struct packed { + logic q; + logic qe; + } ext_clock_en; + } caliptra_ss_lc_ctrl_reg2hw_transition_ctrl_reg_t; + + typedef struct packed { + logic [31:0] q; + logic qe; + } caliptra_ss_lc_ctrl_reg2hw_transition_token_mreg_t; + + typedef struct packed { + logic [29:0] q; + logic qe; + } caliptra_ss_lc_ctrl_reg2hw_transition_target_reg_t; + + typedef struct packed { + logic [31:0] q; + logic qe; + } caliptra_ss_lc_ctrl_reg2hw_otp_vendor_test_ctrl_reg_t; + + typedef struct packed { + struct packed { + logic d; + } initialized; + struct packed { + logic d; + } ready; + struct packed { + logic d; + } ext_clock_switched; + struct packed { + logic d; + } transition_successful; + struct packed { + logic d; + } transition_count_error; + struct packed { + logic d; + } transition_error; + struct packed { + logic d; + } token_error; + struct packed { + logic d; + } flash_rma_error; + struct packed { + logic d; + } otp_error; + struct packed { + logic d; + } state_error; + struct packed { + logic d; + } bus_integ_error; + struct packed { + logic d; + } otp_partition_error; + } caliptra_ss_lc_ctrl_hw2reg_status_reg_t; + + typedef struct packed { + logic [7:0] d; + } caliptra_ss_lc_ctrl_hw2reg_claim_transition_if_reg_t; + + typedef struct packed { + logic d; + } caliptra_ss_lc_ctrl_hw2reg_transition_regwen_reg_t; + + typedef struct packed { + struct packed { + logic d; + } ext_clock_en; + struct packed { + logic d; + } volatile_raw_unlock; + } caliptra_ss_lc_ctrl_hw2reg_transition_ctrl_reg_t; + + typedef struct packed { + logic [31:0] d; + } caliptra_ss_lc_ctrl_hw2reg_transition_token_mreg_t; + + typedef struct packed { + logic [29:0] d; + } caliptra_ss_lc_ctrl_hw2reg_transition_target_reg_t; + + typedef struct packed { + logic [31:0] d; + } caliptra_ss_lc_ctrl_hw2reg_otp_vendor_test_ctrl_reg_t; + + typedef struct packed { + logic [31:0] d; + } caliptra_ss_lc_ctrl_hw2reg_otp_vendor_test_status_reg_t; + + typedef struct packed { + logic [29:0] d; + } caliptra_ss_lc_ctrl_hw2reg_caliptra_ss_lc_state_reg_t; + + typedef struct packed { + logic [4:0] d; + } caliptra_ss_lc_ctrl_hw2reg_caliptra_ss_lc_transition_cnt_reg_t; + + typedef struct packed { + logic [31:0] d; + } caliptra_ss_lc_ctrl_hw2reg_caliptra_ss_lc_id_state_reg_t; + + typedef struct packed { + struct packed { + logic [15:0] d; + } product_id; + struct packed { + logic [15:0] d; + } silicon_creator_id; + } caliptra_ss_lc_ctrl_hw2reg_hw_revision0_reg_t; + + typedef struct packed { + struct packed { + logic [7:0] d; + } revision_id; + struct packed { + logic [23:0] d; + } reserved; + } caliptra_ss_lc_ctrl_hw2reg_hw_revision1_reg_t; + + typedef struct packed { + logic [31:0] d; + } caliptra_ss_lc_ctrl_hw2reg_device_id_mreg_t; + + typedef struct packed { + logic [31:0] d; + } caliptra_ss_lc_ctrl_hw2reg_manuf_state_mreg_t; + + // Register -> HW type for regs interface + typedef struct packed { + caliptra_ss_lc_ctrl_reg2hw_alert_test_reg_t alert_test; // [216:211] + caliptra_ss_lc_ctrl_reg2hw_claim_transition_if_reg_t claim_transition_if; // [210:202] + caliptra_ss_lc_ctrl_reg2hw_transition_cmd_reg_t transition_cmd; // [201:200] + caliptra_ss_lc_ctrl_reg2hw_transition_ctrl_reg_t transition_ctrl; // [199:196] + caliptra_ss_lc_ctrl_reg2hw_transition_token_mreg_t [3:0] transition_token; // [195:64] + caliptra_ss_lc_ctrl_reg2hw_transition_target_reg_t transition_target; // [63:33] + caliptra_ss_lc_ctrl_reg2hw_otp_vendor_test_ctrl_reg_t otp_vendor_test_ctrl; // [32:0] + } caliptra_ss_lc_ctrl_regs_reg2hw_t; + + // HW -> register type for regs interface + typedef struct packed { + caliptra_ss_lc_ctrl_hw2reg_status_reg_t status; // [887:876] + caliptra_ss_lc_ctrl_hw2reg_claim_transition_if_reg_t claim_transition_if; // [875:868] + caliptra_ss_lc_ctrl_hw2reg_transition_regwen_reg_t transition_regwen; // [867:867] + caliptra_ss_lc_ctrl_hw2reg_transition_ctrl_reg_t transition_ctrl; // [866:865] + caliptra_ss_lc_ctrl_hw2reg_transition_token_mreg_t [3:0] transition_token; // [864:737] + caliptra_ss_lc_ctrl_hw2reg_transition_target_reg_t transition_target; // [736:707] + caliptra_ss_lc_ctrl_hw2reg_otp_vendor_test_ctrl_reg_t otp_vendor_test_ctrl; // [706:675] + caliptra_ss_lc_ctrl_hw2reg_otp_vendor_test_status_reg_t otp_vendor_test_status; // [674:643] + caliptra_ss_lc_ctrl_hw2reg_caliptra_ss_lc_state_reg_t caliptra_ss_lc_state; // [642:613] + caliptra_ss_lc_ctrl_hw2reg_caliptra_ss_lc_transition_cnt_reg_t caliptra_ss_lc_transition_cnt; // [612:608] + caliptra_ss_lc_ctrl_hw2reg_caliptra_ss_lc_id_state_reg_t caliptra_ss_lc_id_state; // [607:576] + caliptra_ss_lc_ctrl_hw2reg_hw_revision0_reg_t hw_revision0; // [575:544] + caliptra_ss_lc_ctrl_hw2reg_hw_revision1_reg_t hw_revision1; // [543:512] + caliptra_ss_lc_ctrl_hw2reg_device_id_mreg_t [7:0] device_id; // [511:256] + caliptra_ss_lc_ctrl_hw2reg_manuf_state_mreg_t [7:0] manuf_state; // [255:0] + } caliptra_ss_lc_ctrl_regs_hw2reg_t; + + // Register offsets for regs interface + parameter logic [RegsAw-1:0] LC_CTRL_ALERT_TEST_OFFSET = 8'h 0; + parameter logic [RegsAw-1:0] LC_CTRL_STATUS_OFFSET = 8'h 4; + parameter logic [RegsAw-1:0] LC_CTRL_CLAIM_TRANSITION_IF_REGWEN_OFFSET = 8'h 8; + parameter logic [RegsAw-1:0] LC_CTRL_CLAIM_TRANSITION_IF_OFFSET = 8'h c; + parameter logic [RegsAw-1:0] LC_CTRL_TRANSITION_REGWEN_OFFSET = 8'h 10; + parameter logic [RegsAw-1:0] LC_CTRL_TRANSITION_CMD_OFFSET = 8'h 14; + parameter logic [RegsAw-1:0] LC_CTRL_TRANSITION_CTRL_OFFSET = 8'h 18; + parameter logic [RegsAw-1:0] LC_CTRL_TRANSITION_TOKEN_0_OFFSET = 8'h 1c; + parameter logic [RegsAw-1:0] LC_CTRL_TRANSITION_TOKEN_1_OFFSET = 8'h 20; + parameter logic [RegsAw-1:0] LC_CTRL_TRANSITION_TOKEN_2_OFFSET = 8'h 24; + parameter logic [RegsAw-1:0] LC_CTRL_TRANSITION_TOKEN_3_OFFSET = 8'h 28; + parameter logic [RegsAw-1:0] LC_CTRL_TRANSITION_TARGET_OFFSET = 8'h 2c; + parameter logic [RegsAw-1:0] LC_CTRL_OTP_VENDOR_TEST_CTRL_OFFSET = 8'h 30; + parameter logic [RegsAw-1:0] LC_CTRL_OTP_VENDOR_TEST_STATUS_OFFSET = 8'h 34; + parameter logic [RegsAw-1:0] LC_CTRL_LC_STATE_OFFSET = 8'h 38; + parameter logic [RegsAw-1:0] LC_CTRL_LC_TRANSITION_CNT_OFFSET = 8'h 3c; + parameter logic [RegsAw-1:0] LC_CTRL_LC_ID_STATE_OFFSET = 8'h 40; + parameter logic [RegsAw-1:0] LC_CTRL_HW_REVISION0_OFFSET = 8'h 44; + parameter logic [RegsAw-1:0] LC_CTRL_HW_REVISION1_OFFSET = 8'h 48; + parameter logic [RegsAw-1:0] LC_CTRL_DEVICE_ID_0_OFFSET = 8'h 4c; + parameter logic [RegsAw-1:0] LC_CTRL_DEVICE_ID_1_OFFSET = 8'h 50; + parameter logic [RegsAw-1:0] LC_CTRL_DEVICE_ID_2_OFFSET = 8'h 54; + parameter logic [RegsAw-1:0] LC_CTRL_DEVICE_ID_3_OFFSET = 8'h 58; + parameter logic [RegsAw-1:0] LC_CTRL_DEVICE_ID_4_OFFSET = 8'h 5c; + parameter logic [RegsAw-1:0] LC_CTRL_DEVICE_ID_5_OFFSET = 8'h 60; + parameter logic [RegsAw-1:0] LC_CTRL_DEVICE_ID_6_OFFSET = 8'h 64; + parameter logic [RegsAw-1:0] LC_CTRL_DEVICE_ID_7_OFFSET = 8'h 68; + parameter logic [RegsAw-1:0] LC_CTRL_MANUF_STATE_0_OFFSET = 8'h 6c; + parameter logic [RegsAw-1:0] LC_CTRL_MANUF_STATE_1_OFFSET = 8'h 70; + parameter logic [RegsAw-1:0] LC_CTRL_MANUF_STATE_2_OFFSET = 8'h 74; + parameter logic [RegsAw-1:0] LC_CTRL_MANUF_STATE_3_OFFSET = 8'h 78; + parameter logic [RegsAw-1:0] LC_CTRL_MANUF_STATE_4_OFFSET = 8'h 7c; + parameter logic [RegsAw-1:0] LC_CTRL_MANUF_STATE_5_OFFSET = 8'h 80; + parameter logic [RegsAw-1:0] LC_CTRL_MANUF_STATE_6_OFFSET = 8'h 84; + parameter logic [RegsAw-1:0] LC_CTRL_MANUF_STATE_7_OFFSET = 8'h 88; + + // Reset values for hwext registers and their fields for regs interface + parameter logic [2:0] LC_CTRL_ALERT_TEST_RESVAL = 3'h 0; + parameter logic [0:0] LC_CTRL_ALERT_TEST_FATAL_PROG_ERROR_RESVAL = 1'h 0; + parameter logic [0:0] LC_CTRL_ALERT_TEST_FATAL_STATE_ERROR_RESVAL = 1'h 0; + parameter logic [0:0] LC_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL = 1'h 0; + parameter logic [11:0] LC_CTRL_STATUS_RESVAL = 12'h 0; + parameter logic [7:0] LC_CTRL_CLAIM_TRANSITION_IF_RESVAL = 8'h 69; + parameter logic [7:0] LC_CTRL_CLAIM_TRANSITION_IF_MUTEX_RESVAL = 8'h 69; + parameter logic [0:0] LC_CTRL_TRANSITION_REGWEN_RESVAL = 1'h 0; + parameter logic [0:0] LC_CTRL_TRANSITION_REGWEN_TRANSITION_REGWEN_RESVAL = 1'h 0; + parameter logic [0:0] LC_CTRL_TRANSITION_CMD_RESVAL = 1'h 0; + parameter logic [1:0] LC_CTRL_TRANSITION_CTRL_RESVAL = 2'h 0; + parameter logic [31:0] LC_CTRL_TRANSITION_TOKEN_0_RESVAL = 32'h 0; + parameter logic [31:0] LC_CTRL_TRANSITION_TOKEN_1_RESVAL = 32'h 0; + parameter logic [31:0] LC_CTRL_TRANSITION_TOKEN_2_RESVAL = 32'h 0; + parameter logic [31:0] LC_CTRL_TRANSITION_TOKEN_3_RESVAL = 32'h 0; + parameter logic [29:0] LC_CTRL_TRANSITION_TARGET_RESVAL = 30'h 0; + parameter logic [31:0] LC_CTRL_OTP_VENDOR_TEST_CTRL_RESVAL = 32'h 0; + parameter logic [31:0] LC_CTRL_OTP_VENDOR_TEST_STATUS_RESVAL = 32'h 0; + parameter logic [29:0] LC_CTRL_LC_STATE_RESVAL = 30'h 0; + parameter logic [4:0] LC_CTRL_LC_TRANSITION_CNT_RESVAL = 5'h 0; + parameter logic [31:0] LC_CTRL_LC_ID_STATE_RESVAL = 32'h 0; + parameter logic [31:0] LC_CTRL_HW_REVISION0_RESVAL = 32'h 0; + parameter logic [31:0] LC_CTRL_HW_REVISION1_RESVAL = 32'h 0; + parameter logic [23:0] LC_CTRL_HW_REVISION1_RESERVED_RESVAL = 24'h 0; + parameter logic [31:0] LC_CTRL_DEVICE_ID_0_RESVAL = 32'h 0; + parameter logic [31:0] LC_CTRL_DEVICE_ID_1_RESVAL = 32'h 0; + parameter logic [31:0] LC_CTRL_DEVICE_ID_2_RESVAL = 32'h 0; + parameter logic [31:0] LC_CTRL_DEVICE_ID_3_RESVAL = 32'h 0; + parameter logic [31:0] LC_CTRL_DEVICE_ID_4_RESVAL = 32'h 0; + parameter logic [31:0] LC_CTRL_DEVICE_ID_5_RESVAL = 32'h 0; + parameter logic [31:0] LC_CTRL_DEVICE_ID_6_RESVAL = 32'h 0; + parameter logic [31:0] LC_CTRL_DEVICE_ID_7_RESVAL = 32'h 0; + parameter logic [31:0] LC_CTRL_MANUF_STATE_0_RESVAL = 32'h 0; + parameter logic [31:0] LC_CTRL_MANUF_STATE_1_RESVAL = 32'h 0; + parameter logic [31:0] LC_CTRL_MANUF_STATE_2_RESVAL = 32'h 0; + parameter logic [31:0] LC_CTRL_MANUF_STATE_3_RESVAL = 32'h 0; + parameter logic [31:0] LC_CTRL_MANUF_STATE_4_RESVAL = 32'h 0; + parameter logic [31:0] LC_CTRL_MANUF_STATE_5_RESVAL = 32'h 0; + parameter logic [31:0] LC_CTRL_MANUF_STATE_6_RESVAL = 32'h 0; + parameter logic [31:0] LC_CTRL_MANUF_STATE_7_RESVAL = 32'h 0; + + // Register index for regs interface + typedef enum int { + LC_CTRL_ALERT_TEST, + LC_CTRL_STATUS, + LC_CTRL_CLAIM_TRANSITION_IF_REGWEN, + LC_CTRL_CLAIM_TRANSITION_IF, + LC_CTRL_TRANSITION_REGWEN, + LC_CTRL_TRANSITION_CMD, + LC_CTRL_TRANSITION_CTRL, + LC_CTRL_TRANSITION_TOKEN_0, + LC_CTRL_TRANSITION_TOKEN_1, + LC_CTRL_TRANSITION_TOKEN_2, + LC_CTRL_TRANSITION_TOKEN_3, + LC_CTRL_TRANSITION_TARGET, + LC_CTRL_OTP_VENDOR_TEST_CTRL, + LC_CTRL_OTP_VENDOR_TEST_STATUS, + LC_CTRL_LC_STATE, + LC_CTRL_LC_TRANSITION_CNT, + LC_CTRL_LC_ID_STATE, + LC_CTRL_HW_REVISION0, + LC_CTRL_HW_REVISION1, + LC_CTRL_DEVICE_ID_0, + LC_CTRL_DEVICE_ID_1, + LC_CTRL_DEVICE_ID_2, + LC_CTRL_DEVICE_ID_3, + LC_CTRL_DEVICE_ID_4, + LC_CTRL_DEVICE_ID_5, + LC_CTRL_DEVICE_ID_6, + LC_CTRL_DEVICE_ID_7, + LC_CTRL_MANUF_STATE_0, + LC_CTRL_MANUF_STATE_1, + LC_CTRL_MANUF_STATE_2, + LC_CTRL_MANUF_STATE_3, + LC_CTRL_MANUF_STATE_4, + LC_CTRL_MANUF_STATE_5, + LC_CTRL_MANUF_STATE_6, + LC_CTRL_MANUF_STATE_7 + } caliptra_ss_lc_ctrl_regs_id_e; + + // Register width information to check illegal writes for regs interface + parameter logic [3:0] LC_CTRL_REGS_PERMIT [35] = '{ + 4'b 0001, // index[ 0] LC_CTRL_ALERT_TEST + 4'b 0011, // index[ 1] LC_CTRL_STATUS + 4'b 0001, // index[ 2] LC_CTRL_CLAIM_TRANSITION_IF_REGWEN + 4'b 0001, // index[ 3] LC_CTRL_CLAIM_TRANSITION_IF + 4'b 0001, // index[ 4] LC_CTRL_TRANSITION_REGWEN + 4'b 0001, // index[ 5] LC_CTRL_TRANSITION_CMD + 4'b 0001, // index[ 6] LC_CTRL_TRANSITION_CTRL + 4'b 1111, // index[ 7] LC_CTRL_TRANSITION_TOKEN_0 + 4'b 1111, // index[ 8] LC_CTRL_TRANSITION_TOKEN_1 + 4'b 1111, // index[ 9] LC_CTRL_TRANSITION_TOKEN_2 + 4'b 1111, // index[10] LC_CTRL_TRANSITION_TOKEN_3 + 4'b 1111, // index[11] LC_CTRL_TRANSITION_TARGET + 4'b 1111, // index[12] LC_CTRL_OTP_VENDOR_TEST_CTRL + 4'b 1111, // index[13] LC_CTRL_OTP_VENDOR_TEST_STATUS + 4'b 1111, // index[14] LC_CTRL_LC_STATE + 4'b 0001, // index[15] LC_CTRL_LC_TRANSITION_CNT + 4'b 1111, // index[16] LC_CTRL_LC_ID_STATE + 4'b 1111, // index[17] LC_CTRL_HW_REVISION0 + 4'b 1111, // index[18] LC_CTRL_HW_REVISION1 + 4'b 1111, // index[19] LC_CTRL_DEVICE_ID_0 + 4'b 1111, // index[20] LC_CTRL_DEVICE_ID_1 + 4'b 1111, // index[21] LC_CTRL_DEVICE_ID_2 + 4'b 1111, // index[22] LC_CTRL_DEVICE_ID_3 + 4'b 1111, // index[23] LC_CTRL_DEVICE_ID_4 + 4'b 1111, // index[24] LC_CTRL_DEVICE_ID_5 + 4'b 1111, // index[25] LC_CTRL_DEVICE_ID_6 + 4'b 1111, // index[26] LC_CTRL_DEVICE_ID_7 + 4'b 1111, // index[27] LC_CTRL_MANUF_STATE_0 + 4'b 1111, // index[28] LC_CTRL_MANUF_STATE_1 + 4'b 1111, // index[29] LC_CTRL_MANUF_STATE_2 + 4'b 1111, // index[30] LC_CTRL_MANUF_STATE_3 + 4'b 1111, // index[31] LC_CTRL_MANUF_STATE_4 + 4'b 1111, // index[32] LC_CTRL_MANUF_STATE_5 + 4'b 1111, // index[33] LC_CTRL_MANUF_STATE_6 + 4'b 1111 // index[34] LC_CTRL_MANUF_STATE_7 + }; + + // Window parameters for dmi interface + parameter logic [DmiAw-1:0] LC_CTRL_DMI_OFFSET = 12'h 0; + parameter int unsigned LC_CTRL_DMI_SIZE = 'h 1000; + parameter int unsigned LC_CTRL_DMI_IDX = 0; + +endpackage diff --git a/src/caliptra_ss_lc_ctrl/rtl/caliptra_ss_lc_ctrl_regs_reg_top.sv b/src/caliptra_ss_lc_ctrl/rtl/caliptra_ss_lc_ctrl_regs_reg_top.sv new file mode 100644 index 0000000..e77c6ff --- /dev/null +++ b/src/caliptra_ss_lc_ctrl/rtl/caliptra_ss_lc_ctrl_regs_reg_top.sv @@ -0,0 +1,1528 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Top module auto-generated by `reggen` + +`include "caliptra_prim_assert.sv" + +module caliptra_ss_lc_ctrl_regs_reg_top +( + input clk_i, + input rst_ni, + input tlul_pkg::tl_h2d_t tl_i, + output tlul_pkg::tl_d2h_t tl_o, + // To HW + output caliptra_ss_lc_ctrl_reg_pkg::caliptra_ss_lc_ctrl_regs_reg2hw_t reg2hw, // Write + input caliptra_ss_lc_ctrl_reg_pkg::caliptra_ss_lc_ctrl_regs_hw2reg_t hw2reg, // Read + + // Integrity check errors + output logic intg_err_o +); + + import caliptra_ss_lc_ctrl_reg_pkg::* ; + + localparam int AW = 8; + localparam int DW = 32; + localparam int DBW = DW/8; // Byte Width + + // register signals + logic reg_we; + logic reg_re; + logic [AW-1:0] reg_addr; + logic [DW-1:0] reg_wdata; + logic [DBW-1:0] reg_be; + logic [DW-1:0] reg_rdata; + logic reg_error; + + logic addrmiss, wr_err; + + logic [DW-1:0] reg_rdata_next; + logic reg_busy; + + tlul_pkg::tl_h2d_t tl_reg_h2d; + tlul_pkg::tl_d2h_t tl_reg_d2h; + + + // incoming payload check + logic intg_err; + tlul_cmd_intg_chk u_chk ( + .tl_i(tl_i), + .err_o(intg_err) + ); + + // also check for spurious write enables + logic reg_we_err; + logic [34:0] reg_we_check; + caliptra_prim_reg_we_check #( + .OneHotWidth(35) + ) u_caliptra_prim_reg_we_check ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .oh_i (reg_we_check), + .en_i (reg_we && !addrmiss), + .err_o (reg_we_err) + ); + + logic err_q; + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + err_q <= '0; + end else if (intg_err || reg_we_err) begin + err_q <= 1'b1; + end + end + + // integrity error output is permanent and should be used for alert generation + // register errors are transactional + assign intg_err_o = err_q | intg_err | reg_we_err; + + // outgoing integrity generation + tlul_pkg::tl_d2h_t tl_o_pre; + tlul_rsp_intg_gen #( + .EnableRspIntgGen(1), + .EnableDataIntgGen(1) + ) u_rsp_intg_gen ( + .tl_i(tl_o_pre), + .tl_o(tl_o) + ); + + assign tl_reg_h2d = tl_i; + assign tl_o_pre = tl_reg_d2h; + + tlul_adapter_reg #( + .RegAw(AW), + .RegDw(DW), + .EnableDataIntgGen(0) + ) u_reg_if ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + .tl_i (tl_reg_h2d), + .tl_o (tl_reg_d2h), + + .en_ifetch_i(caliptra_prim_mubi_pkg::MuBi4False), + .intg_error_o(), + + .we_o (reg_we), + .re_o (reg_re), + .addr_o (reg_addr), + .wdata_o (reg_wdata), + .be_o (reg_be), + .busy_i (reg_busy), + .rdata_i (reg_rdata), + .error_i (reg_error) + ); + + // cdc oversampling signals + + assign reg_rdata = reg_rdata_next ; + assign reg_error = addrmiss | wr_err | intg_err; + + // Define SW related signals + // Format: __{wd|we|qs} + // or _{wd|we|qs} if field == 1 or 0 + logic alert_test_we; + logic alert_test_fatal_prog_error_wd; + logic alert_test_fatal_state_error_wd; + logic alert_test_fatal_bus_integ_error_wd; + logic status_re; + logic status_initialized_qs; + logic status_ready_qs; + logic status_ext_clock_switched_qs; + logic status_transition_successful_qs; + logic status_transition_count_error_qs; + logic status_transition_error_qs; + logic status_token_error_qs; + logic status_flash_rma_error_qs; + logic status_otp_error_qs; + logic status_state_error_qs; + logic status_bus_integ_error_qs; + logic status_otp_partition_error_qs; + logic claim_transition_if_regwen_we; + logic claim_transition_if_regwen_qs; + logic claim_transition_if_regwen_wd; + logic claim_transition_if_re; + logic claim_transition_if_we; + logic [7:0] claim_transition_if_qs; + logic [7:0] claim_transition_if_wd; + logic transition_regwen_re; + logic transition_regwen_qs; + logic transition_cmd_we; + logic transition_cmd_wd; + logic transition_ctrl_re; + logic transition_ctrl_we; + logic transition_ctrl_ext_clock_en_qs; + logic transition_ctrl_ext_clock_en_wd; + logic transition_ctrl_volatile_raw_unlock_qs; + logic transition_ctrl_volatile_raw_unlock_wd; + logic transition_token_0_re; + logic transition_token_0_we; + logic [31:0] transition_token_0_qs; + logic [31:0] transition_token_0_wd; + logic transition_token_1_re; + logic transition_token_1_we; + logic [31:0] transition_token_1_qs; + logic [31:0] transition_token_1_wd; + logic transition_token_2_re; + logic transition_token_2_we; + logic [31:0] transition_token_2_qs; + logic [31:0] transition_token_2_wd; + logic transition_token_3_re; + logic transition_token_3_we; + logic [31:0] transition_token_3_qs; + logic [31:0] transition_token_3_wd; + logic transition_target_re; + logic transition_target_we; + logic [29:0] transition_target_qs; + logic [29:0] transition_target_wd; + logic otp_vendor_test_ctrl_re; + logic otp_vendor_test_ctrl_we; + logic [31:0] otp_vendor_test_ctrl_qs; + logic [31:0] otp_vendor_test_ctrl_wd; + logic otp_vendor_test_status_re; + logic [31:0] otp_vendor_test_status_qs; + logic caliptra_ss_lc_state_re; + logic [29:0] caliptra_ss_lc_state_qs; + logic caliptra_ss_lc_transition_cnt_re; + logic [4:0] caliptra_ss_lc_transition_cnt_qs; + logic caliptra_ss_lc_id_state_re; + logic [31:0] caliptra_ss_lc_id_state_qs; + logic hw_revision0_re; + logic [15:0] hw_revision0_product_id_qs; + logic [15:0] hw_revision0_silicon_creator_id_qs; + logic hw_revision1_re; + logic [7:0] hw_revision1_revision_id_qs; + logic [23:0] hw_revision1_reserved_qs; + logic device_id_0_re; + logic [31:0] device_id_0_qs; + logic device_id_1_re; + logic [31:0] device_id_1_qs; + logic device_id_2_re; + logic [31:0] device_id_2_qs; + logic device_id_3_re; + logic [31:0] device_id_3_qs; + logic device_id_4_re; + logic [31:0] device_id_4_qs; + logic device_id_5_re; + logic [31:0] device_id_5_qs; + logic device_id_6_re; + logic [31:0] device_id_6_qs; + logic device_id_7_re; + logic [31:0] device_id_7_qs; + logic manuf_state_0_re; + logic [31:0] manuf_state_0_qs; + logic manuf_state_1_re; + logic [31:0] manuf_state_1_qs; + logic manuf_state_2_re; + logic [31:0] manuf_state_2_qs; + logic manuf_state_3_re; + logic [31:0] manuf_state_3_qs; + logic manuf_state_4_re; + logic [31:0] manuf_state_4_qs; + logic manuf_state_5_re; + logic [31:0] manuf_state_5_qs; + logic manuf_state_6_re; + logic [31:0] manuf_state_6_qs; + logic manuf_state_7_re; + logic [31:0] manuf_state_7_qs; + + // Register instances + // R[alert_test]: V(True) + logic alert_test_qe; + logic [2:0] alert_test_flds_we; + assign alert_test_qe = &alert_test_flds_we; + // F[fatal_prog_error]: 0:0 + caliptra_prim_subreg_ext #( + .DW (1) + ) u_alert_test_fatal_prog_error ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_fatal_prog_error_wd), + .d ('0), + .qre (), + .qe (alert_test_flds_we[0]), + .q (reg2hw.alert_test.fatal_prog_error.q), + .ds (), + .qs () + ); + assign reg2hw.alert_test.fatal_prog_error.qe = alert_test_qe; + + // F[fatal_state_error]: 1:1 + caliptra_prim_subreg_ext #( + .DW (1) + ) u_alert_test_fatal_state_error ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_fatal_state_error_wd), + .d ('0), + .qre (), + .qe (alert_test_flds_we[1]), + .q (reg2hw.alert_test.fatal_state_error.q), + .ds (), + .qs () + ); + assign reg2hw.alert_test.fatal_state_error.qe = alert_test_qe; + + // F[fatal_bus_integ_error]: 2:2 + caliptra_prim_subreg_ext #( + .DW (1) + ) u_alert_test_fatal_bus_integ_error ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_fatal_bus_integ_error_wd), + .d ('0), + .qre (), + .qe (alert_test_flds_we[2]), + .q (reg2hw.alert_test.fatal_bus_integ_error.q), + .ds (), + .qs () + ); + assign reg2hw.alert_test.fatal_bus_integ_error.qe = alert_test_qe; + + + // R[status]: V(True) + // F[initialized]: 0:0 + caliptra_prim_subreg_ext #( + .DW (1) + ) u_status_initialized ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.initialized.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_initialized_qs) + ); + + // F[ready]: 1:1 + caliptra_prim_subreg_ext #( + .DW (1) + ) u_status_ready ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.ready.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_ready_qs) + ); + + // F[ext_clock_switched]: 2:2 + caliptra_prim_subreg_ext #( + .DW (1) + ) u_status_ext_clock_switched ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.ext_clock_switched.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_ext_clock_switched_qs) + ); + + // F[transition_successful]: 3:3 + caliptra_prim_subreg_ext #( + .DW (1) + ) u_status_transition_successful ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.transition_successful.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_transition_successful_qs) + ); + + // F[transition_count_error]: 4:4 + caliptra_prim_subreg_ext #( + .DW (1) + ) u_status_transition_count_error ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.transition_count_error.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_transition_count_error_qs) + ); + + // F[transition_error]: 5:5 + caliptra_prim_subreg_ext #( + .DW (1) + ) u_status_transition_error ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.transition_error.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_transition_error_qs) + ); + + // F[token_error]: 6:6 + caliptra_prim_subreg_ext #( + .DW (1) + ) u_status_token_error ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.token_error.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_token_error_qs) + ); + + // F[flash_rma_error]: 7:7 + caliptra_prim_subreg_ext #( + .DW (1) + ) u_status_flash_rma_error ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.flash_rma_error.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_flash_rma_error_qs) + ); + + // F[otp_error]: 8:8 + caliptra_prim_subreg_ext #( + .DW (1) + ) u_status_otp_error ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.otp_error.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_otp_error_qs) + ); + + // F[state_error]: 9:9 + caliptra_prim_subreg_ext #( + .DW (1) + ) u_status_state_error ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.state_error.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_state_error_qs) + ); + + // F[bus_integ_error]: 10:10 + caliptra_prim_subreg_ext #( + .DW (1) + ) u_status_bus_integ_error ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.bus_integ_error.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_bus_integ_error_qs) + ); + + // F[otp_partition_error]: 11:11 + caliptra_prim_subreg_ext #( + .DW (1) + ) u_status_otp_partition_error ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.otp_partition_error.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_otp_partition_error_qs) + ); + + + // R[claim_transition_if_regwen]: V(False) + caliptra_prim_subreg #( + .DW (1), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_claim_transition_if_regwen ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (claim_transition_if_regwen_we), + .wd (claim_transition_if_regwen_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (claim_transition_if_regwen_qs) + ); + + + // R[claim_transition_if]: V(True) + logic claim_transition_if_qe; + logic [0:0] claim_transition_if_flds_we; + assign claim_transition_if_qe = &claim_transition_if_flds_we; + // Create REGWEN-gated WE signal + logic claim_transition_if_gated_we; + assign claim_transition_if_gated_we = claim_transition_if_we & claim_transition_if_regwen_qs; + caliptra_prim_subreg_ext #( + .DW (8) + ) u_claim_transition_if ( + .re (claim_transition_if_re), + .we (claim_transition_if_gated_we), + .wd (claim_transition_if_wd), + .d (hw2reg.claim_transition_if.d), + .qre (), + .qe (claim_transition_if_flds_we[0]), + .q (reg2hw.claim_transition_if.q), + .ds (), + .qs (claim_transition_if_qs) + ); + assign reg2hw.claim_transition_if.qe = claim_transition_if_qe; + + + // R[transition_regwen]: V(True) + caliptra_prim_subreg_ext #( + .DW (1) + ) u_transition_regwen ( + .re (transition_regwen_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.transition_regwen.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (transition_regwen_qs) + ); + + + // R[transition_cmd]: V(True) + logic transition_cmd_qe; + logic [0:0] transition_cmd_flds_we; + assign transition_cmd_qe = &transition_cmd_flds_we; + // Create REGWEN-gated WE signal + logic transition_cmd_gated_we; + assign transition_cmd_gated_we = transition_cmd_we & transition_regwen_qs; + caliptra_prim_subreg_ext #( + .DW (1) + ) u_transition_cmd ( + .re (1'b0), + .we (transition_cmd_gated_we), + .wd (transition_cmd_wd), + .d ('0), + .qre (), + .qe (transition_cmd_flds_we[0]), + .q (reg2hw.transition_cmd.q), + .ds (), + .qs () + ); + assign reg2hw.transition_cmd.qe = transition_cmd_qe; + + + // R[transition_ctrl]: V(True) + logic transition_ctrl_qe; + logic [1:0] transition_ctrl_flds_we; + assign transition_ctrl_qe = &transition_ctrl_flds_we; + // Create REGWEN-gated WE signal + logic transition_ctrl_gated_we; + assign transition_ctrl_gated_we = transition_ctrl_we & transition_regwen_qs; + // F[ext_clock_en]: 0:0 + caliptra_prim_subreg_ext #( + .DW (1) + ) u_transition_ctrl_ext_clock_en ( + .re (transition_ctrl_re), + .we (transition_ctrl_gated_we), + .wd (transition_ctrl_ext_clock_en_wd), + .d (hw2reg.transition_ctrl.ext_clock_en.d), + .qre (), + .qe (transition_ctrl_flds_we[0]), + .q (reg2hw.transition_ctrl.ext_clock_en.q), + .ds (), + .qs (transition_ctrl_ext_clock_en_qs) + ); + assign reg2hw.transition_ctrl.ext_clock_en.qe = transition_ctrl_qe; + + // F[volatile_raw_unlock]: 1:1 + caliptra_prim_subreg_ext #( + .DW (1) + ) u_transition_ctrl_volatile_raw_unlock ( + .re (transition_ctrl_re), + .we (transition_ctrl_gated_we), + .wd (transition_ctrl_volatile_raw_unlock_wd), + .d (hw2reg.transition_ctrl.volatile_raw_unlock.d), + .qre (), + .qe (transition_ctrl_flds_we[1]), + .q (reg2hw.transition_ctrl.volatile_raw_unlock.q), + .ds (), + .qs (transition_ctrl_volatile_raw_unlock_qs) + ); + assign reg2hw.transition_ctrl.volatile_raw_unlock.qe = transition_ctrl_qe; + + + // Subregister 0 of Multireg transition_token + // R[transition_token_0]: V(True) + logic transition_token_0_qe; + logic [0:0] transition_token_0_flds_we; + assign transition_token_0_qe = &transition_token_0_flds_we; + // Create REGWEN-gated WE signal + logic transition_token_0_gated_we; + assign transition_token_0_gated_we = transition_token_0_we & transition_regwen_qs; + caliptra_prim_subreg_ext #( + .DW (32) + ) u_transition_token_0 ( + .re (transition_token_0_re), + .we (transition_token_0_gated_we), + .wd (transition_token_0_wd), + .d (hw2reg.transition_token[0].d), + .qre (), + .qe (transition_token_0_flds_we[0]), + .q (reg2hw.transition_token[0].q), + .ds (), + .qs (transition_token_0_qs) + ); + assign reg2hw.transition_token[0].qe = transition_token_0_qe; + + + // Subregister 1 of Multireg transition_token + // R[transition_token_1]: V(True) + logic transition_token_1_qe; + logic [0:0] transition_token_1_flds_we; + assign transition_token_1_qe = &transition_token_1_flds_we; + // Create REGWEN-gated WE signal + logic transition_token_1_gated_we; + assign transition_token_1_gated_we = transition_token_1_we & transition_regwen_qs; + caliptra_prim_subreg_ext #( + .DW (32) + ) u_transition_token_1 ( + .re (transition_token_1_re), + .we (transition_token_1_gated_we), + .wd (transition_token_1_wd), + .d (hw2reg.transition_token[1].d), + .qre (), + .qe (transition_token_1_flds_we[0]), + .q (reg2hw.transition_token[1].q), + .ds (), + .qs (transition_token_1_qs) + ); + assign reg2hw.transition_token[1].qe = transition_token_1_qe; + + + // Subregister 2 of Multireg transition_token + // R[transition_token_2]: V(True) + logic transition_token_2_qe; + logic [0:0] transition_token_2_flds_we; + assign transition_token_2_qe = &transition_token_2_flds_we; + // Create REGWEN-gated WE signal + logic transition_token_2_gated_we; + assign transition_token_2_gated_we = transition_token_2_we & transition_regwen_qs; + caliptra_prim_subreg_ext #( + .DW (32) + ) u_transition_token_2 ( + .re (transition_token_2_re), + .we (transition_token_2_gated_we), + .wd (transition_token_2_wd), + .d (hw2reg.transition_token[2].d), + .qre (), + .qe (transition_token_2_flds_we[0]), + .q (reg2hw.transition_token[2].q), + .ds (), + .qs (transition_token_2_qs) + ); + assign reg2hw.transition_token[2].qe = transition_token_2_qe; + + + // Subregister 3 of Multireg transition_token + // R[transition_token_3]: V(True) + logic transition_token_3_qe; + logic [0:0] transition_token_3_flds_we; + assign transition_token_3_qe = &transition_token_3_flds_we; + // Create REGWEN-gated WE signal + logic transition_token_3_gated_we; + assign transition_token_3_gated_we = transition_token_3_we & transition_regwen_qs; + caliptra_prim_subreg_ext #( + .DW (32) + ) u_transition_token_3 ( + .re (transition_token_3_re), + .we (transition_token_3_gated_we), + .wd (transition_token_3_wd), + .d (hw2reg.transition_token[3].d), + .qre (), + .qe (transition_token_3_flds_we[0]), + .q (reg2hw.transition_token[3].q), + .ds (), + .qs (transition_token_3_qs) + ); + assign reg2hw.transition_token[3].qe = transition_token_3_qe; + + + // R[transition_target]: V(True) + logic transition_target_qe; + logic [0:0] transition_target_flds_we; + assign transition_target_qe = &transition_target_flds_we; + // Create REGWEN-gated WE signal + logic transition_target_gated_we; + assign transition_target_gated_we = transition_target_we & transition_regwen_qs; + caliptra_prim_subreg_ext #( + .DW (30) + ) u_transition_target ( + .re (transition_target_re), + .we (transition_target_gated_we), + .wd (transition_target_wd), + .d (hw2reg.transition_target.d), + .qre (), + .qe (transition_target_flds_we[0]), + .q (reg2hw.transition_target.q), + .ds (), + .qs (transition_target_qs) + ); + assign reg2hw.transition_target.qe = transition_target_qe; + + + // R[otp_vendor_test_ctrl]: V(True) + logic otp_vendor_test_ctrl_qe; + logic [0:0] otp_vendor_test_ctrl_flds_we; + assign otp_vendor_test_ctrl_qe = &otp_vendor_test_ctrl_flds_we; + // Create REGWEN-gated WE signal + logic otp_vendor_test_ctrl_gated_we; + assign otp_vendor_test_ctrl_gated_we = otp_vendor_test_ctrl_we & transition_regwen_qs; + caliptra_prim_subreg_ext #( + .DW (32) + ) u_otp_vendor_test_ctrl ( + .re (otp_vendor_test_ctrl_re), + .we (otp_vendor_test_ctrl_gated_we), + .wd (otp_vendor_test_ctrl_wd), + .d (hw2reg.otp_vendor_test_ctrl.d), + .qre (), + .qe (otp_vendor_test_ctrl_flds_we[0]), + .q (reg2hw.otp_vendor_test_ctrl.q), + .ds (), + .qs (otp_vendor_test_ctrl_qs) + ); + assign reg2hw.otp_vendor_test_ctrl.qe = otp_vendor_test_ctrl_qe; + + + // R[otp_vendor_test_status]: V(True) + caliptra_prim_subreg_ext #( + .DW (32) + ) u_otp_vendor_test_status ( + .re (otp_vendor_test_status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.otp_vendor_test_status.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (otp_vendor_test_status_qs) + ); + + + // R[caliptra_ss_lc_state]: V(True) + caliptra_prim_subreg_ext #( + .DW (30) + ) u_caliptra_ss_lc_state ( + .re (caliptra_ss_lc_state_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.caliptra_ss_lc_state.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (caliptra_ss_lc_state_qs) + ); + + + // R[caliptra_ss_lc_transition_cnt]: V(True) + caliptra_prim_subreg_ext #( + .DW (5) + ) u_caliptra_ss_lc_transition_cnt ( + .re (caliptra_ss_lc_transition_cnt_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.caliptra_ss_lc_transition_cnt.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (caliptra_ss_lc_transition_cnt_qs) + ); + + + // R[caliptra_ss_lc_id_state]: V(True) + caliptra_prim_subreg_ext #( + .DW (32) + ) u_caliptra_ss_lc_id_state ( + .re (caliptra_ss_lc_id_state_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.caliptra_ss_lc_id_state.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (caliptra_ss_lc_id_state_qs) + ); + + + // R[hw_revision0]: V(True) + // F[product_id]: 15:0 + caliptra_prim_subreg_ext #( + .DW (16) + ) u_hw_revision0_product_id ( + .re (hw_revision0_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.hw_revision0.product_id.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (hw_revision0_product_id_qs) + ); + + // F[silicon_creator_id]: 31:16 + caliptra_prim_subreg_ext #( + .DW (16) + ) u_hw_revision0_silicon_creator_id ( + .re (hw_revision0_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.hw_revision0.silicon_creator_id.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (hw_revision0_silicon_creator_id_qs) + ); + + + // R[hw_revision1]: V(True) + // F[revision_id]: 7:0 + caliptra_prim_subreg_ext #( + .DW (8) + ) u_hw_revision1_revision_id ( + .re (hw_revision1_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.hw_revision1.revision_id.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (hw_revision1_revision_id_qs) + ); + + // F[reserved]: 31:8 + caliptra_prim_subreg_ext #( + .DW (24) + ) u_hw_revision1_reserved ( + .re (hw_revision1_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.hw_revision1.reserved.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (hw_revision1_reserved_qs) + ); + + + // Subregister 0 of Multireg device_id + // R[device_id_0]: V(True) + caliptra_prim_subreg_ext #( + .DW (32) + ) u_device_id_0 ( + .re (device_id_0_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.device_id[0].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (device_id_0_qs) + ); + + + // Subregister 1 of Multireg device_id + // R[device_id_1]: V(True) + caliptra_prim_subreg_ext #( + .DW (32) + ) u_device_id_1 ( + .re (device_id_1_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.device_id[1].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (device_id_1_qs) + ); + + + // Subregister 2 of Multireg device_id + // R[device_id_2]: V(True) + caliptra_prim_subreg_ext #( + .DW (32) + ) u_device_id_2 ( + .re (device_id_2_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.device_id[2].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (device_id_2_qs) + ); + + + // Subregister 3 of Multireg device_id + // R[device_id_3]: V(True) + caliptra_prim_subreg_ext #( + .DW (32) + ) u_device_id_3 ( + .re (device_id_3_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.device_id[3].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (device_id_3_qs) + ); + + + // Subregister 4 of Multireg device_id + // R[device_id_4]: V(True) + caliptra_prim_subreg_ext #( + .DW (32) + ) u_device_id_4 ( + .re (device_id_4_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.device_id[4].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (device_id_4_qs) + ); + + + // Subregister 5 of Multireg device_id + // R[device_id_5]: V(True) + caliptra_prim_subreg_ext #( + .DW (32) + ) u_device_id_5 ( + .re (device_id_5_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.device_id[5].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (device_id_5_qs) + ); + + + // Subregister 6 of Multireg device_id + // R[device_id_6]: V(True) + caliptra_prim_subreg_ext #( + .DW (32) + ) u_device_id_6 ( + .re (device_id_6_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.device_id[6].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (device_id_6_qs) + ); + + + // Subregister 7 of Multireg device_id + // R[device_id_7]: V(True) + caliptra_prim_subreg_ext #( + .DW (32) + ) u_device_id_7 ( + .re (device_id_7_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.device_id[7].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (device_id_7_qs) + ); + + + // Subregister 0 of Multireg manuf_state + // R[manuf_state_0]: V(True) + caliptra_prim_subreg_ext #( + .DW (32) + ) u_manuf_state_0 ( + .re (manuf_state_0_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.manuf_state[0].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (manuf_state_0_qs) + ); + + + // Subregister 1 of Multireg manuf_state + // R[manuf_state_1]: V(True) + caliptra_prim_subreg_ext #( + .DW (32) + ) u_manuf_state_1 ( + .re (manuf_state_1_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.manuf_state[1].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (manuf_state_1_qs) + ); + + + // Subregister 2 of Multireg manuf_state + // R[manuf_state_2]: V(True) + caliptra_prim_subreg_ext #( + .DW (32) + ) u_manuf_state_2 ( + .re (manuf_state_2_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.manuf_state[2].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (manuf_state_2_qs) + ); + + + // Subregister 3 of Multireg manuf_state + // R[manuf_state_3]: V(True) + caliptra_prim_subreg_ext #( + .DW (32) + ) u_manuf_state_3 ( + .re (manuf_state_3_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.manuf_state[3].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (manuf_state_3_qs) + ); + + + // Subregister 4 of Multireg manuf_state + // R[manuf_state_4]: V(True) + caliptra_prim_subreg_ext #( + .DW (32) + ) u_manuf_state_4 ( + .re (manuf_state_4_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.manuf_state[4].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (manuf_state_4_qs) + ); + + + // Subregister 5 of Multireg manuf_state + // R[manuf_state_5]: V(True) + caliptra_prim_subreg_ext #( + .DW (32) + ) u_manuf_state_5 ( + .re (manuf_state_5_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.manuf_state[5].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (manuf_state_5_qs) + ); + + + // Subregister 6 of Multireg manuf_state + // R[manuf_state_6]: V(True) + caliptra_prim_subreg_ext #( + .DW (32) + ) u_manuf_state_6 ( + .re (manuf_state_6_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.manuf_state[6].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (manuf_state_6_qs) + ); + + + // Subregister 7 of Multireg manuf_state + // R[manuf_state_7]: V(True) + caliptra_prim_subreg_ext #( + .DW (32) + ) u_manuf_state_7 ( + .re (manuf_state_7_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.manuf_state[7].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (manuf_state_7_qs) + ); + + + + logic [34:0] addr_hit; + always_comb begin + addr_hit = '0; + addr_hit[ 0] = (reg_addr == LC_CTRL_ALERT_TEST_OFFSET); + addr_hit[ 1] = (reg_addr == LC_CTRL_STATUS_OFFSET); + addr_hit[ 2] = (reg_addr == LC_CTRL_CLAIM_TRANSITION_IF_REGWEN_OFFSET); + addr_hit[ 3] = (reg_addr == LC_CTRL_CLAIM_TRANSITION_IF_OFFSET); + addr_hit[ 4] = (reg_addr == LC_CTRL_TRANSITION_REGWEN_OFFSET); + addr_hit[ 5] = (reg_addr == LC_CTRL_TRANSITION_CMD_OFFSET); + addr_hit[ 6] = (reg_addr == LC_CTRL_TRANSITION_CTRL_OFFSET); + addr_hit[ 7] = (reg_addr == LC_CTRL_TRANSITION_TOKEN_0_OFFSET); + addr_hit[ 8] = (reg_addr == LC_CTRL_TRANSITION_TOKEN_1_OFFSET); + addr_hit[ 9] = (reg_addr == LC_CTRL_TRANSITION_TOKEN_2_OFFSET); + addr_hit[10] = (reg_addr == LC_CTRL_TRANSITION_TOKEN_3_OFFSET); + addr_hit[11] = (reg_addr == LC_CTRL_TRANSITION_TARGET_OFFSET); + addr_hit[12] = (reg_addr == LC_CTRL_OTP_VENDOR_TEST_CTRL_OFFSET); + addr_hit[13] = (reg_addr == LC_CTRL_OTP_VENDOR_TEST_STATUS_OFFSET); + addr_hit[14] = (reg_addr == LC_CTRL_LC_STATE_OFFSET); + addr_hit[15] = (reg_addr == LC_CTRL_LC_TRANSITION_CNT_OFFSET); + addr_hit[16] = (reg_addr == LC_CTRL_LC_ID_STATE_OFFSET); + addr_hit[17] = (reg_addr == LC_CTRL_HW_REVISION0_OFFSET); + addr_hit[18] = (reg_addr == LC_CTRL_HW_REVISION1_OFFSET); + addr_hit[19] = (reg_addr == LC_CTRL_DEVICE_ID_0_OFFSET); + addr_hit[20] = (reg_addr == LC_CTRL_DEVICE_ID_1_OFFSET); + addr_hit[21] = (reg_addr == LC_CTRL_DEVICE_ID_2_OFFSET); + addr_hit[22] = (reg_addr == LC_CTRL_DEVICE_ID_3_OFFSET); + addr_hit[23] = (reg_addr == LC_CTRL_DEVICE_ID_4_OFFSET); + addr_hit[24] = (reg_addr == LC_CTRL_DEVICE_ID_5_OFFSET); + addr_hit[25] = (reg_addr == LC_CTRL_DEVICE_ID_6_OFFSET); + addr_hit[26] = (reg_addr == LC_CTRL_DEVICE_ID_7_OFFSET); + addr_hit[27] = (reg_addr == LC_CTRL_MANUF_STATE_0_OFFSET); + addr_hit[28] = (reg_addr == LC_CTRL_MANUF_STATE_1_OFFSET); + addr_hit[29] = (reg_addr == LC_CTRL_MANUF_STATE_2_OFFSET); + addr_hit[30] = (reg_addr == LC_CTRL_MANUF_STATE_3_OFFSET); + addr_hit[31] = (reg_addr == LC_CTRL_MANUF_STATE_4_OFFSET); + addr_hit[32] = (reg_addr == LC_CTRL_MANUF_STATE_5_OFFSET); + addr_hit[33] = (reg_addr == LC_CTRL_MANUF_STATE_6_OFFSET); + addr_hit[34] = (reg_addr == LC_CTRL_MANUF_STATE_7_OFFSET); + end + + assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; + + // Check sub-word write is permitted + always_comb begin + wr_err = (reg_we & + ((addr_hit[ 0] & (|(LC_CTRL_REGS_PERMIT[ 0] & ~reg_be))) | + (addr_hit[ 1] & (|(LC_CTRL_REGS_PERMIT[ 1] & ~reg_be))) | + (addr_hit[ 2] & (|(LC_CTRL_REGS_PERMIT[ 2] & ~reg_be))) | + (addr_hit[ 3] & (|(LC_CTRL_REGS_PERMIT[ 3] & ~reg_be))) | + (addr_hit[ 4] & (|(LC_CTRL_REGS_PERMIT[ 4] & ~reg_be))) | + (addr_hit[ 5] & (|(LC_CTRL_REGS_PERMIT[ 5] & ~reg_be))) | + (addr_hit[ 6] & (|(LC_CTRL_REGS_PERMIT[ 6] & ~reg_be))) | + (addr_hit[ 7] & (|(LC_CTRL_REGS_PERMIT[ 7] & ~reg_be))) | + (addr_hit[ 8] & (|(LC_CTRL_REGS_PERMIT[ 8] & ~reg_be))) | + (addr_hit[ 9] & (|(LC_CTRL_REGS_PERMIT[ 9] & ~reg_be))) | + (addr_hit[10] & (|(LC_CTRL_REGS_PERMIT[10] & ~reg_be))) | + (addr_hit[11] & (|(LC_CTRL_REGS_PERMIT[11] & ~reg_be))) | + (addr_hit[12] & (|(LC_CTRL_REGS_PERMIT[12] & ~reg_be))) | + (addr_hit[13] & (|(LC_CTRL_REGS_PERMIT[13] & ~reg_be))) | + (addr_hit[14] & (|(LC_CTRL_REGS_PERMIT[14] & ~reg_be))) | + (addr_hit[15] & (|(LC_CTRL_REGS_PERMIT[15] & ~reg_be))) | + (addr_hit[16] & (|(LC_CTRL_REGS_PERMIT[16] & ~reg_be))) | + (addr_hit[17] & (|(LC_CTRL_REGS_PERMIT[17] & ~reg_be))) | + (addr_hit[18] & (|(LC_CTRL_REGS_PERMIT[18] & ~reg_be))) | + (addr_hit[19] & (|(LC_CTRL_REGS_PERMIT[19] & ~reg_be))) | + (addr_hit[20] & (|(LC_CTRL_REGS_PERMIT[20] & ~reg_be))) | + (addr_hit[21] & (|(LC_CTRL_REGS_PERMIT[21] & ~reg_be))) | + (addr_hit[22] & (|(LC_CTRL_REGS_PERMIT[22] & ~reg_be))) | + (addr_hit[23] & (|(LC_CTRL_REGS_PERMIT[23] & ~reg_be))) | + (addr_hit[24] & (|(LC_CTRL_REGS_PERMIT[24] & ~reg_be))) | + (addr_hit[25] & (|(LC_CTRL_REGS_PERMIT[25] & ~reg_be))) | + (addr_hit[26] & (|(LC_CTRL_REGS_PERMIT[26] & ~reg_be))) | + (addr_hit[27] & (|(LC_CTRL_REGS_PERMIT[27] & ~reg_be))) | + (addr_hit[28] & (|(LC_CTRL_REGS_PERMIT[28] & ~reg_be))) | + (addr_hit[29] & (|(LC_CTRL_REGS_PERMIT[29] & ~reg_be))) | + (addr_hit[30] & (|(LC_CTRL_REGS_PERMIT[30] & ~reg_be))) | + (addr_hit[31] & (|(LC_CTRL_REGS_PERMIT[31] & ~reg_be))) | + (addr_hit[32] & (|(LC_CTRL_REGS_PERMIT[32] & ~reg_be))) | + (addr_hit[33] & (|(LC_CTRL_REGS_PERMIT[33] & ~reg_be))) | + (addr_hit[34] & (|(LC_CTRL_REGS_PERMIT[34] & ~reg_be))))); + end + + // Generate write-enables + assign alert_test_we = addr_hit[0] & reg_we & !reg_error; + + assign alert_test_fatal_prog_error_wd = reg_wdata[0]; + + assign alert_test_fatal_state_error_wd = reg_wdata[1]; + + assign alert_test_fatal_bus_integ_error_wd = reg_wdata[2]; + assign status_re = addr_hit[1] & reg_re & !reg_error; + assign claim_transition_if_regwen_we = addr_hit[2] & reg_we & !reg_error; + + assign claim_transition_if_regwen_wd = reg_wdata[0]; + assign claim_transition_if_re = addr_hit[3] & reg_re & !reg_error; + assign claim_transition_if_we = addr_hit[3] & reg_we & !reg_error; + + assign claim_transition_if_wd = reg_wdata[7:0]; + assign transition_regwen_re = addr_hit[4] & reg_re & !reg_error; + assign transition_cmd_we = addr_hit[5] & reg_we & !reg_error; + + assign transition_cmd_wd = reg_wdata[0]; + assign transition_ctrl_re = addr_hit[6] & reg_re & !reg_error; + assign transition_ctrl_we = addr_hit[6] & reg_we & !reg_error; + + assign transition_ctrl_ext_clock_en_wd = reg_wdata[0]; + + assign transition_ctrl_volatile_raw_unlock_wd = reg_wdata[1]; + assign transition_token_0_re = addr_hit[7] & reg_re & !reg_error; + assign transition_token_0_we = addr_hit[7] & reg_we & !reg_error; + + assign transition_token_0_wd = reg_wdata[31:0]; + assign transition_token_1_re = addr_hit[8] & reg_re & !reg_error; + assign transition_token_1_we = addr_hit[8] & reg_we & !reg_error; + + assign transition_token_1_wd = reg_wdata[31:0]; + assign transition_token_2_re = addr_hit[9] & reg_re & !reg_error; + assign transition_token_2_we = addr_hit[9] & reg_we & !reg_error; + + assign transition_token_2_wd = reg_wdata[31:0]; + assign transition_token_3_re = addr_hit[10] & reg_re & !reg_error; + assign transition_token_3_we = addr_hit[10] & reg_we & !reg_error; + + assign transition_token_3_wd = reg_wdata[31:0]; + assign transition_target_re = addr_hit[11] & reg_re & !reg_error; + assign transition_target_we = addr_hit[11] & reg_we & !reg_error; + + assign transition_target_wd = reg_wdata[29:0]; + assign otp_vendor_test_ctrl_re = addr_hit[12] & reg_re & !reg_error; + assign otp_vendor_test_ctrl_we = addr_hit[12] & reg_we & !reg_error; + + assign otp_vendor_test_ctrl_wd = reg_wdata[31:0]; + assign otp_vendor_test_status_re = addr_hit[13] & reg_re & !reg_error; + assign caliptra_ss_lc_state_re = addr_hit[14] & reg_re & !reg_error; + assign caliptra_ss_lc_transition_cnt_re = addr_hit[15] & reg_re & !reg_error; + assign caliptra_ss_lc_id_state_re = addr_hit[16] & reg_re & !reg_error; + assign hw_revision0_re = addr_hit[17] & reg_re & !reg_error; + assign hw_revision1_re = addr_hit[18] & reg_re & !reg_error; + assign device_id_0_re = addr_hit[19] & reg_re & !reg_error; + assign device_id_1_re = addr_hit[20] & reg_re & !reg_error; + assign device_id_2_re = addr_hit[21] & reg_re & !reg_error; + assign device_id_3_re = addr_hit[22] & reg_re & !reg_error; + assign device_id_4_re = addr_hit[23] & reg_re & !reg_error; + assign device_id_5_re = addr_hit[24] & reg_re & !reg_error; + assign device_id_6_re = addr_hit[25] & reg_re & !reg_error; + assign device_id_7_re = addr_hit[26] & reg_re & !reg_error; + assign manuf_state_0_re = addr_hit[27] & reg_re & !reg_error; + assign manuf_state_1_re = addr_hit[28] & reg_re & !reg_error; + assign manuf_state_2_re = addr_hit[29] & reg_re & !reg_error; + assign manuf_state_3_re = addr_hit[30] & reg_re & !reg_error; + assign manuf_state_4_re = addr_hit[31] & reg_re & !reg_error; + assign manuf_state_5_re = addr_hit[32] & reg_re & !reg_error; + assign manuf_state_6_re = addr_hit[33] & reg_re & !reg_error; + assign manuf_state_7_re = addr_hit[34] & reg_re & !reg_error; + + // Assign write-enables to checker logic vector. + always_comb begin + reg_we_check = '0; + reg_we_check[0] = alert_test_we; + reg_we_check[1] = 1'b0; + reg_we_check[2] = claim_transition_if_regwen_we; + reg_we_check[3] = claim_transition_if_gated_we; + reg_we_check[4] = 1'b0; + reg_we_check[5] = transition_cmd_gated_we; + reg_we_check[6] = transition_ctrl_gated_we; + reg_we_check[7] = transition_token_0_gated_we; + reg_we_check[8] = transition_token_1_gated_we; + reg_we_check[9] = transition_token_2_gated_we; + reg_we_check[10] = transition_token_3_gated_we; + reg_we_check[11] = transition_target_gated_we; + reg_we_check[12] = otp_vendor_test_ctrl_gated_we; + reg_we_check[13] = 1'b0; + reg_we_check[14] = 1'b0; + reg_we_check[15] = 1'b0; + reg_we_check[16] = 1'b0; + reg_we_check[17] = 1'b0; + reg_we_check[18] = 1'b0; + reg_we_check[19] = 1'b0; + reg_we_check[20] = 1'b0; + reg_we_check[21] = 1'b0; + reg_we_check[22] = 1'b0; + reg_we_check[23] = 1'b0; + reg_we_check[24] = 1'b0; + reg_we_check[25] = 1'b0; + reg_we_check[26] = 1'b0; + reg_we_check[27] = 1'b0; + reg_we_check[28] = 1'b0; + reg_we_check[29] = 1'b0; + reg_we_check[30] = 1'b0; + reg_we_check[31] = 1'b0; + reg_we_check[32] = 1'b0; + reg_we_check[33] = 1'b0; + reg_we_check[34] = 1'b0; + end + + // Read data return + always_comb begin + reg_rdata_next = '0; + unique case (1'b1) + addr_hit[0]: begin + reg_rdata_next[0] = '0; + reg_rdata_next[1] = '0; + reg_rdata_next[2] = '0; + end + + addr_hit[1]: begin + reg_rdata_next[0] = status_initialized_qs; + reg_rdata_next[1] = status_ready_qs; + reg_rdata_next[2] = status_ext_clock_switched_qs; + reg_rdata_next[3] = status_transition_successful_qs; + reg_rdata_next[4] = status_transition_count_error_qs; + reg_rdata_next[5] = status_transition_error_qs; + reg_rdata_next[6] = status_token_error_qs; + reg_rdata_next[7] = status_flash_rma_error_qs; + reg_rdata_next[8] = status_otp_error_qs; + reg_rdata_next[9] = status_state_error_qs; + reg_rdata_next[10] = status_bus_integ_error_qs; + reg_rdata_next[11] = status_otp_partition_error_qs; + end + + addr_hit[2]: begin + reg_rdata_next[0] = claim_transition_if_regwen_qs; + end + + addr_hit[3]: begin + reg_rdata_next[7:0] = claim_transition_if_qs; + end + + addr_hit[4]: begin + reg_rdata_next[0] = transition_regwen_qs; + end + + addr_hit[5]: begin + reg_rdata_next[0] = '0; + end + + addr_hit[6]: begin + reg_rdata_next[0] = transition_ctrl_ext_clock_en_qs; + reg_rdata_next[1] = transition_ctrl_volatile_raw_unlock_qs; + end + + addr_hit[7]: begin + reg_rdata_next[31:0] = transition_token_0_qs; + end + + addr_hit[8]: begin + reg_rdata_next[31:0] = transition_token_1_qs; + end + + addr_hit[9]: begin + reg_rdata_next[31:0] = transition_token_2_qs; + end + + addr_hit[10]: begin + reg_rdata_next[31:0] = transition_token_3_qs; + end + + addr_hit[11]: begin + reg_rdata_next[29:0] = transition_target_qs; + end + + addr_hit[12]: begin + reg_rdata_next[31:0] = otp_vendor_test_ctrl_qs; + end + + addr_hit[13]: begin + reg_rdata_next[31:0] = otp_vendor_test_status_qs; + end + + addr_hit[14]: begin + reg_rdata_next[29:0] = caliptra_ss_lc_state_qs; + end + + addr_hit[15]: begin + reg_rdata_next[4:0] = caliptra_ss_lc_transition_cnt_qs; + end + + addr_hit[16]: begin + reg_rdata_next[31:0] = caliptra_ss_lc_id_state_qs; + end + + addr_hit[17]: begin + reg_rdata_next[15:0] = hw_revision0_product_id_qs; + reg_rdata_next[31:16] = hw_revision0_silicon_creator_id_qs; + end + + addr_hit[18]: begin + reg_rdata_next[7:0] = hw_revision1_revision_id_qs; + reg_rdata_next[31:8] = hw_revision1_reserved_qs; + end + + addr_hit[19]: begin + reg_rdata_next[31:0] = device_id_0_qs; + end + + addr_hit[20]: begin + reg_rdata_next[31:0] = device_id_1_qs; + end + + addr_hit[21]: begin + reg_rdata_next[31:0] = device_id_2_qs; + end + + addr_hit[22]: begin + reg_rdata_next[31:0] = device_id_3_qs; + end + + addr_hit[23]: begin + reg_rdata_next[31:0] = device_id_4_qs; + end + + addr_hit[24]: begin + reg_rdata_next[31:0] = device_id_5_qs; + end + + addr_hit[25]: begin + reg_rdata_next[31:0] = device_id_6_qs; + end + + addr_hit[26]: begin + reg_rdata_next[31:0] = device_id_7_qs; + end + + addr_hit[27]: begin + reg_rdata_next[31:0] = manuf_state_0_qs; + end + + addr_hit[28]: begin + reg_rdata_next[31:0] = manuf_state_1_qs; + end + + addr_hit[29]: begin + reg_rdata_next[31:0] = manuf_state_2_qs; + end + + addr_hit[30]: begin + reg_rdata_next[31:0] = manuf_state_3_qs; + end + + addr_hit[31]: begin + reg_rdata_next[31:0] = manuf_state_4_qs; + end + + addr_hit[32]: begin + reg_rdata_next[31:0] = manuf_state_5_qs; + end + + addr_hit[33]: begin + reg_rdata_next[31:0] = manuf_state_6_qs; + end + + addr_hit[34]: begin + reg_rdata_next[31:0] = manuf_state_7_qs; + end + + default: begin + reg_rdata_next = '1; + end + endcase + end + + // shadow busy + logic shadow_busy; + assign shadow_busy = 1'b0; + + // register busy + assign reg_busy = shadow_busy; + + // Unused signal tieoff + + // wdata / byte enable are not always fully used + // add a blanket unused statement to handle lint waivers + logic unused_wdata; + logic unused_be; + assign unused_wdata = ^reg_wdata; + assign unused_be = ^reg_be; + + // Assertions for Register Interface + `CALIPTRA_ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni) + `CALIPTRA_ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni) + + `CALIPTRA_ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o_pre.d_valid, clk_i, !rst_ni) + + `CALIPTRA_ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni) + + // this is formulated as an assumption such that the FPV testbenches do disprove this + // property by mistake + //`CALIPTRA_ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.chk_en == tlul_pkg::CheckDis) + +endmodule diff --git a/src/caliptra_ss_lc_ctrl/rtl/caliptra_ss_lc_ctrl_signal_decode.sv b/src/caliptra_ss_lc_ctrl/rtl/caliptra_ss_lc_ctrl_signal_decode.sv new file mode 100644 index 0000000..d83de79 --- /dev/null +++ b/src/caliptra_ss_lc_ctrl/rtl/caliptra_ss_lc_ctrl_signal_decode.sv @@ -0,0 +1,402 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Life cycle signal decoder and sender module. + +module caliptra_ss_lc_ctrl_signal_decode + import caliptra_ss_lc_ctrl_pkg::*; + import caliptra_ss_lc_ctrl_state_pkg::*; +#( + // Random netlist constants + // SCRAP, RAW, TEST_LOCKED*, INVALID + parameter caliptra_ss_lc_keymgr_div_t RndCnstLcKeymgrDivInvalid = LcKeymgrDivWidth'(0), + // TEST_UNLOCKED* + parameter caliptra_ss_lc_keymgr_div_t RndCnstLcKeymgrDivTestUnlocked = LcKeymgrDivWidth'(1), + // DEV + parameter caliptra_ss_lc_keymgr_div_t RndCnstLcKeymgrDivDev = LcKeymgrDivWidth'(2), + // PROD, PROD_END + parameter caliptra_ss_lc_keymgr_div_t RndCnstLcKeymgrDivProduction = LcKeymgrDivWidth'(3), + // RMA + parameter caliptra_ss_lc_keymgr_div_t RndCnstLcKeymgrDivRma = LcKeymgrDivWidth'(4) + ) ( + input clk_i, + input rst_ni, + // Life cycle state vector. + input logic caliptra_ss_lc_state_valid_i, + input caliptra_ss_lc_state_e caliptra_ss_lc_state_i, + input fsm_state_e fsm_state_i, + input caliptra_ss_lc_tx_t secrets_valid_i, + // Local life cycle signal + output caliptra_ss_lc_tx_t caliptra_ss_lc_raw_test_rma_o, + // Life cycle broadcast outputs. + output caliptra_ss_lc_tx_t caliptra_ss_lc_dft_en_o, + output caliptra_ss_lc_tx_t caliptra_ss_lc_nvm_debug_en_o, + output caliptra_ss_lc_tx_t caliptra_ss_lc_hw_debug_en_o, + output caliptra_ss_lc_tx_t caliptra_ss_lc_cpu_en_o, + output caliptra_ss_lc_tx_t caliptra_ss_lc_creator_seed_sw_rw_en_o, + output caliptra_ss_lc_tx_t caliptra_ss_lc_owner_seed_sw_rw_en_o, + output caliptra_ss_lc_tx_t caliptra_ss_lc_iso_part_sw_rd_en_o, + output caliptra_ss_lc_tx_t caliptra_ss_lc_iso_part_sw_wr_en_o, + output caliptra_ss_lc_tx_t caliptra_ss_lc_seed_hw_rd_en_o, + output caliptra_ss_lc_tx_t caliptra_ss_lc_keymgr_en_o, + output caliptra_ss_lc_tx_t caliptra_ss_lc_escalate_en_o, + // State group diversification value for keymgr + output caliptra_ss_lc_keymgr_div_t caliptra_ss_lc_keymgr_div_o +); + + ////////////////////////// + // Signal Decoder Logic // + ////////////////////////// + + caliptra_ss_lc_tx_t caliptra_ss_lc_raw_test_rma; + caliptra_ss_lc_tx_t caliptra_ss_lc_dft_en, caliptra_ss_lc_nvm_debug_en, caliptra_ss_lc_hw_debug_en, caliptra_ss_lc_cpu_en, caliptra_ss_lc_keymgr_en, caliptra_ss_lc_escalate_en; + caliptra_ss_lc_tx_t caliptra_ss_lc_creator_seed_sw_rw_en, caliptra_ss_lc_owner_seed_sw_rw_en, caliptra_ss_lc_iso_part_sw_rd_en; + caliptra_ss_lc_tx_t caliptra_ss_lc_iso_part_sw_wr_en, caliptra_ss_lc_seed_hw_rd_en; + caliptra_ss_lc_keymgr_div_t caliptra_ss_lc_keymgr_div_d, caliptra_ss_lc_keymgr_div_q; + + always_comb begin : p_caliptra_ss_lc_signal_decode + // Life cycle control signal defaults + caliptra_ss_lc_raw_test_rma = Off; + caliptra_ss_lc_dft_en = Off; + caliptra_ss_lc_nvm_debug_en = Off; + caliptra_ss_lc_hw_debug_en = Off; + caliptra_ss_lc_cpu_en = Off; + caliptra_ss_lc_creator_seed_sw_rw_en = Off; + caliptra_ss_lc_owner_seed_sw_rw_en = Off; + caliptra_ss_lc_iso_part_sw_rd_en = Off; + caliptra_ss_lc_iso_part_sw_wr_en = Off; + caliptra_ss_lc_seed_hw_rd_en = Off; + caliptra_ss_lc_keymgr_en = Off; + // This ensures that once escalation has been triggered, it cannot go back to Off. + caliptra_ss_lc_escalate_en = caliptra_ss_lc_tx_or_hi(Off, caliptra_ss_lc_escalate_en_o); + // Set to invalid diversification value by default. + caliptra_ss_lc_keymgr_div_d = RndCnstLcKeymgrDivInvalid; + + unique case (fsm_state_i) + /////////////////////////////////////////////////////////////////// + // Don't broadcast anything in this state. + ResetSt: ; + /////////////////////////////////////////////////////////////////// + // Broadcasting of most signals is only enabled during the following life cycle states. + IdleSt, + ClkMuxSt, + CntIncrSt, + CntProgSt, + TransCheckSt, + FlashRmaSt, + TokenHashSt, + TokenCheck0St, + TokenCheck1St, + TransProgSt: begin + if (caliptra_ss_lc_state_valid_i) begin + unique case (caliptra_ss_lc_state_i) + /////////////////////////////////////////////////////////////////// + // Only enable life cycle TAP register for OTP test mechanisms. + LcStRaw, + LcStTestLocked0, + LcStTestLocked1, + LcStTestLocked2, + LcStTestLocked3, + LcStTestLocked4, + LcStTestLocked5, + LcStTestLocked6: begin + caliptra_ss_lc_raw_test_rma = On; + end + /////////////////////////////////////////////////////////////////// + // Enable DFT and debug functionality, including the CPU in the + // test unlocked states. + LcStTestUnlocked0, + LcStTestUnlocked1, + LcStTestUnlocked2, + LcStTestUnlocked3, + LcStTestUnlocked4, + LcStTestUnlocked5, + LcStTestUnlocked6: begin + caliptra_ss_lc_raw_test_rma = On; + caliptra_ss_lc_dft_en = On; + caliptra_ss_lc_nvm_debug_en = On; + caliptra_ss_lc_hw_debug_en = On; + caliptra_ss_lc_cpu_en = On; + caliptra_ss_lc_iso_part_sw_wr_en = On; + caliptra_ss_lc_keymgr_div_d = RndCnstLcKeymgrDivTestUnlocked; + end + /////////////////////////////////////////////////////////////////// + // This is the last TEST_UNLOCKED state. The same feature set is enabled + // as in the other TEST_UNLOCKED states above, except for NVM debug en, + // which is disabled in this state. + LcStTestUnlocked7: begin + caliptra_ss_lc_raw_test_rma = On; + caliptra_ss_lc_dft_en = On; + caliptra_ss_lc_hw_debug_en = On; + caliptra_ss_lc_cpu_en = On; + caliptra_ss_lc_iso_part_sw_wr_en = On; + caliptra_ss_lc_keymgr_div_d = RndCnstLcKeymgrDivTestUnlocked; + end + /////////////////////////////////////////////////////////////////// + // Enable production functions + LcStProd, + LcStProdEnd: begin + caliptra_ss_lc_cpu_en = On; + caliptra_ss_lc_keymgr_en = On; + caliptra_ss_lc_owner_seed_sw_rw_en = On; + caliptra_ss_lc_iso_part_sw_wr_en = On; + caliptra_ss_lc_iso_part_sw_rd_en = On; + caliptra_ss_lc_keymgr_div_d = RndCnstLcKeymgrDivProduction; + // Only allow provisioning if the device has not yet been personalized. + // If secrets_valid_i is set to ON, we output OFF. + // Note that we can convert ON to OFF with a bitwise inversion due to the encoding. + caliptra_ss_lc_creator_seed_sw_rw_en = caliptra_ss_lc_tx_t'(~secrets_valid_i); + // Only allow hardware to consume the seeds once personalized. + // If secrets_valid_i is set to ON, we output ON. + caliptra_ss_lc_seed_hw_rd_en = secrets_valid_i; + end + /////////////////////////////////////////////////////////////////// + // Similar functions as PROD, with the following differences: + // - hardware debug functionality (CPU TAP) is enabled, + // - access to the isolated flash partition is disabled. + LcStDev: begin + caliptra_ss_lc_hw_debug_en = On; + caliptra_ss_lc_cpu_en = On; + caliptra_ss_lc_keymgr_en = On; + caliptra_ss_lc_owner_seed_sw_rw_en = On; + caliptra_ss_lc_iso_part_sw_wr_en = On; + caliptra_ss_lc_keymgr_div_d = RndCnstLcKeymgrDivDev; + // Only allow provisioning if the device has not yet been personalized. + // If secrets_valid_i is set to ON, we output OFF. + // Note that we can convert ON to OFF with a bitwise inversion due to the encoding. + caliptra_ss_lc_creator_seed_sw_rw_en = caliptra_ss_lc_tx_t'(~secrets_valid_i); + // Only allow hardware to consume the seeds once personalized. + // If secrets_valid_i is set to ON, we output ON. + caliptra_ss_lc_seed_hw_rd_en = secrets_valid_i; + end + /////////////////////////////////////////////////////////////////// + // Enable all test and production functions. + LcStRma: begin + caliptra_ss_lc_raw_test_rma = On; + caliptra_ss_lc_dft_en = On; + caliptra_ss_lc_nvm_debug_en = On; + caliptra_ss_lc_hw_debug_en = On; + caliptra_ss_lc_cpu_en = On; + caliptra_ss_lc_keymgr_en = On; + caliptra_ss_lc_creator_seed_sw_rw_en = On; + caliptra_ss_lc_owner_seed_sw_rw_en = On; + caliptra_ss_lc_iso_part_sw_wr_en = On; + caliptra_ss_lc_iso_part_sw_rd_en = On; + caliptra_ss_lc_seed_hw_rd_en = On; + caliptra_ss_lc_keymgr_div_d = RndCnstLcKeymgrDivRma; + end + /////////////////////////////////////////////////////////////////// + // Invalid or scrapped life cycle state, make sure the escalation + // signal is also asserted in this case. + default: begin + caliptra_ss_lc_escalate_en = On; + end + endcase // caliptra_ss_lc_state_i + end else begin + caliptra_ss_lc_escalate_en = On; + end + end + /////////////////////////////////////////////////////////////////// + // Post-transition state. Behaves similarly to the virtual scrap + // states below, with the exception that escalate_en is NOT asserted, + // since that could trigger unwanted alerts / escalations and system resets. + PostTransSt: ; + /////////////////////////////////////////////////////////////////// + // Virtual scrap states, make sure the escalation signal is + // also asserted in this case. + ScrapSt, + EscalateSt, + InvalidSt: begin + caliptra_ss_lc_escalate_en = On; + end + default: begin + caliptra_ss_lc_escalate_en = On; + end + endcase // fsm_state_i + end + + ///////////////////////////////// + // Control signal output flops // + ///////////////////////////////// + + caliptra_prim_lc_sender u_caliptra_prim_lc_sender_raw_test_rma ( + .clk_i, + .rst_ni, + .lc_en_i(caliptra_ss_lc_raw_test_rma), + .lc_en_o(caliptra_ss_lc_raw_test_rma_o) + ); + caliptra_prim_lc_sender u_caliptra_prim_lc_sender_dft_en ( + .clk_i, + .rst_ni, + .lc_en_i(caliptra_ss_lc_dft_en), + .lc_en_o(caliptra_ss_lc_dft_en_o) + ); + caliptra_prim_lc_sender u_caliptra_prim_lc_sender_nvm_debug_en ( + .clk_i, + .rst_ni, + .lc_en_i(caliptra_ss_lc_nvm_debug_en), + .lc_en_o(caliptra_ss_lc_nvm_debug_en_o) + ); + caliptra_prim_lc_sender u_caliptra_prim_lc_sender_hw_debug_en ( + .clk_i, + .rst_ni, + .lc_en_i(caliptra_ss_lc_hw_debug_en), + .lc_en_o(caliptra_ss_lc_hw_debug_en_o) + ); + caliptra_prim_lc_sender u_caliptra_prim_lc_sender_cpu_en ( + .clk_i, + .rst_ni, + .lc_en_i(caliptra_ss_lc_cpu_en), + .lc_en_o(caliptra_ss_lc_cpu_en_o) + ); + caliptra_prim_lc_sender u_caliptra_prim_lc_sender_creator_seed_sw_rw_en ( + .clk_i, + .rst_ni, + .lc_en_i(caliptra_ss_lc_creator_seed_sw_rw_en), + .lc_en_o(caliptra_ss_lc_creator_seed_sw_rw_en_o) + ); + caliptra_prim_lc_sender u_caliptra_prim_lc_sender_owner_seed_sw_rw_en ( + .clk_i, + .rst_ni, + .lc_en_i(caliptra_ss_lc_owner_seed_sw_rw_en), + .lc_en_o(caliptra_ss_lc_owner_seed_sw_rw_en_o) + ); + caliptra_prim_lc_sender u_caliptra_prim_lc_sender_iso_part_sw_rd_en ( + .clk_i, + .rst_ni, + .lc_en_i(caliptra_ss_lc_iso_part_sw_rd_en), + .lc_en_o(caliptra_ss_lc_iso_part_sw_rd_en_o) + ); + caliptra_prim_lc_sender u_caliptra_prim_lc_sender_iso_part_sw_wr_en ( + .clk_i, + .rst_ni, + .lc_en_i(caliptra_ss_lc_iso_part_sw_wr_en), + .lc_en_o(caliptra_ss_lc_iso_part_sw_wr_en_o) + ); + caliptra_prim_lc_sender u_caliptra_prim_lc_sender_seed_hw_rd_en ( + .clk_i, + .rst_ni, + .lc_en_i(caliptra_ss_lc_seed_hw_rd_en), + .lc_en_o(caliptra_ss_lc_seed_hw_rd_en_o) + ); + caliptra_prim_lc_sender u_caliptra_prim_lc_sender_keymgr_en ( + .clk_i, + .rst_ni, + .lc_en_i(caliptra_ss_lc_keymgr_en), + .lc_en_o(caliptra_ss_lc_keymgr_en_o) + ); + caliptra_prim_lc_sender u_caliptra_prim_lc_sender_escalate_en ( + .clk_i, + .rst_ni, + .lc_en_i(caliptra_ss_lc_escalate_en), + .lc_en_o(caliptra_ss_lc_escalate_en_o) + ); + + assign caliptra_ss_lc_keymgr_div_o = caliptra_ss_lc_keymgr_div_q; + + caliptra_prim_flop #( + .Width(LcKeymgrDivWidth), + .ResetValue(RndCnstLcKeymgrDivInvalid) + ) u_caliptra_prim_flop_keymgr_div ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .d_i ( caliptra_ss_lc_keymgr_div_d ), + .q_o ( caliptra_ss_lc_keymgr_div_q ) + ); + + //////////////// + // Assertions // + //////////////// + + // Need to make sure that the random netlist constants are all unique. + `CALIPTRA_ASSERT_INIT(LcKeymgrDivUnique0_A, + !(RndCnstLcKeymgrDivInvalid inside {RndCnstLcKeymgrDivTestUnlocked, + RndCnstLcKeymgrDivDev, + RndCnstLcKeymgrDivRma, + RndCnstLcKeymgrDivProduction})) + `CALIPTRA_ASSERT_INIT(LcKeymgrDivUnique1_A, + !(RndCnstLcKeymgrDivTestUnlocked inside {RndCnstLcKeymgrDivInvalid, + RndCnstLcKeymgrDivDev, + RndCnstLcKeymgrDivRma, + RndCnstLcKeymgrDivProduction})) + `CALIPTRA_ASSERT_INIT(LcKeymgrDivUnique2_A, + !(RndCnstLcKeymgrDivDev inside {RndCnstLcKeymgrDivInvalid, + RndCnstLcKeymgrDivTestUnlocked, + RndCnstLcKeymgrDivRma, + RndCnstLcKeymgrDivProduction})) + `CALIPTRA_ASSERT_INIT(LcKeymgrDivUnique3_A, + !(RndCnstLcKeymgrDivRma inside {RndCnstLcKeymgrDivInvalid, + RndCnstLcKeymgrDivTestUnlocked, + RndCnstLcKeymgrDivDev, + RndCnstLcKeymgrDivProduction})) + + `CALIPTRA_ASSERT(SignalsAreOffWhenNotEnabled_A, + !caliptra_ss_lc_state_valid_i + |=> + caliptra_ss_lc_tx_test_false_strict(caliptra_ss_lc_raw_test_rma_o) && + caliptra_ss_lc_tx_test_false_strict(caliptra_ss_lc_dft_en_o) && + caliptra_ss_lc_tx_test_false_strict(caliptra_ss_lc_nvm_debug_en_o) && + caliptra_ss_lc_tx_test_false_strict(caliptra_ss_lc_hw_debug_en_o) && + caliptra_ss_lc_tx_test_false_strict(caliptra_ss_lc_cpu_en_o) && + caliptra_ss_lc_tx_test_false_strict(caliptra_ss_lc_creator_seed_sw_rw_en_o) && + caliptra_ss_lc_tx_test_false_strict(caliptra_ss_lc_owner_seed_sw_rw_en_o) && + caliptra_ss_lc_tx_test_false_strict(caliptra_ss_lc_iso_part_sw_rd_en_o) && + caliptra_ss_lc_tx_test_false_strict(caliptra_ss_lc_iso_part_sw_wr_en_o) && + caliptra_ss_lc_tx_test_false_strict(caliptra_ss_lc_seed_hw_rd_en_o) && + caliptra_ss_lc_tx_test_false_strict(caliptra_ss_lc_keymgr_en_o) && + caliptra_ss_lc_tx_test_false_strict(caliptra_ss_lc_dft_en_o) && + caliptra_ss_lc_keymgr_div_o == RndCnstLcKeymgrDivInvalid) + + + `CALIPTRA_ASSERT(FsmInScrap_A, + !(fsm_state_i inside {ResetSt, + TransProgSt, + IdleSt, + ClkMuxSt, + CntIncrSt, + CntProgSt, + TransCheckSt, + FlashRmaSt, + TokenHashSt, + TokenCheck0St, + TokenCheck1St, + PostTransSt}) + |=> + caliptra_ss_lc_tx_test_true_strict(caliptra_ss_lc_escalate_en_o)) + + `CALIPTRA_ASSERT(StateInScrap_A, + caliptra_ss_lc_state_valid_i && + fsm_state_i inside {IdleSt, + ClkMuxSt, + CntIncrSt, + CntProgSt, + TransCheckSt, + FlashRmaSt, + TokenHashSt, + TokenCheck0St, + TokenCheck1St} && + !(caliptra_ss_lc_state_i inside {LcStRaw, + LcStTestUnlocked0, + LcStTestUnlocked1, + LcStTestUnlocked2, + LcStTestUnlocked3, + LcStTestUnlocked4, + LcStTestUnlocked5, + LcStTestUnlocked6, + LcStTestUnlocked7, + LcStTestLocked0, + LcStTestLocked1, + LcStTestLocked2, + LcStTestLocked3, + LcStTestLocked4, + LcStTestLocked5, + LcStTestLocked6, + LcStDev, + LcStProd, + LcStProdEnd, + LcStRma}) + |=> + caliptra_ss_lc_tx_test_true_strict(caliptra_ss_lc_escalate_en_o)) + +endmodule : caliptra_ss_lc_ctrl_signal_decode diff --git a/src/caliptra_ss_lc_ctrl/rtl/caliptra_ss_lc_ctrl_state_decode.sv b/src/caliptra_ss_lc_ctrl/rtl/caliptra_ss_lc_ctrl_state_decode.sv new file mode 100644 index 0000000..a30995c --- /dev/null +++ b/src/caliptra_ss_lc_ctrl/rtl/caliptra_ss_lc_ctrl_state_decode.sv @@ -0,0 +1,167 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Life cycle state decoder. This is a purely combinational module. + +module caliptra_ss_lc_ctrl_state_decode + import caliptra_ss_lc_ctrl_pkg::*; + import caliptra_ss_lc_ctrl_state_pkg::*; +( + // Life cycle state vector. + input logic caliptra_ss_lc_state_valid_i, + input caliptra_ss_lc_state_e caliptra_ss_lc_state_i, + input caliptra_ss_lc_cnt_e caliptra_ss_lc_cnt_i, + input caliptra_ss_lc_tx_t secrets_valid_i, + // Main FSM state. + input fsm_state_e fsm_state_i, + // Decoded state vector. + output ext_dec_caliptra_ss_lc_state_t dec_caliptra_ss_lc_state_o, + output dec_caliptra_ss_lc_id_state_e dec_caliptra_ss_lc_id_state_o, + output dec_caliptra_ss_lc_cnt_t dec_caliptra_ss_lc_cnt_o, + output logic [5:0] state_invalid_error_o +); + + ////////////////////////// + // Signal Decoder Logic // + ////////////////////////// + + // SEC_CM: STATE.CONFIG.SPARSE + // The decoded life cycle state uses a redundant representation that is used internally + // and in the CSR node. + ext_dec_caliptra_ss_lc_state_t dec_caliptra_ss_lc_state; + logic [$bits(ext_dec_caliptra_ss_lc_state_t)-1:0] dec_caliptra_ss_lc_state_buf; + caliptra_prim_sec_anchor_buf #( + .Width($bits(ext_dec_caliptra_ss_lc_state_t)) + ) u_prim_sec_anchor_buf ( + .in_i(dec_caliptra_ss_lc_state), + .out_o(dec_caliptra_ss_lc_state_buf) + ); + + // This cast is needed so that VCS does not throw warnings. + for (genvar k = 0; k < DecLcStateNumRep; k++) begin : gen_enum_casts + assign dec_caliptra_ss_lc_state_o[k] = dec_caliptra_ss_lc_state_e'(dec_caliptra_ss_lc_state_buf[k*DecLcStateWidth +: + DecLcStateWidth]); + end + // The decoder logic below decodes the life cycle state vector and counter + // into a format that can be exposed in the CSRs. If the state is invalid, + // this will be flagged as well. + + always_comb begin : p_caliptra_ss_lc_state_decode + // Decoded state defaults + dec_caliptra_ss_lc_state = {DecLcStateNumRep{DecLcStInvalid}}; + dec_caliptra_ss_lc_cnt_o = {DecLcCountWidth{1'b1}}; + dec_caliptra_ss_lc_id_state_o = DecLcIdInvalid; + state_invalid_error_o = '0; + + unique case (fsm_state_i) + // Don't decode anything in ResetSt + ResetSt: ; + // These are temporary, terminal states that are not encoded + // in the persistent LC state vector from OTP, hence we decode them first. + EscalateSt: dec_caliptra_ss_lc_state = {DecLcStateNumRep{DecLcStEscalate}}; + PostTransSt: dec_caliptra_ss_lc_state = {DecLcStateNumRep{DecLcStPostTrans}}; + InvalidSt: dec_caliptra_ss_lc_state = {DecLcStateNumRep{DecLcStInvalid}}; + ScrapSt: dec_caliptra_ss_lc_state = {DecLcStateNumRep{DecLcStScrap}}; + // Otherwise check and decode the life cycle state continously. + default: begin + // Note that we require that the valid signal from OTP is + // asserted at all times except when the LC controller is in ResetSt. + // This will trigger an invalid_state_error when the OTP partition + // is corrupt and moved into an error state, where the valid bit is + // deasserted. + state_invalid_error_o[0] = ~caliptra_ss_lc_state_valid_i; + + unique case (caliptra_ss_lc_state_i) + LcStRaw: dec_caliptra_ss_lc_state = {DecLcStateNumRep{DecLcStRaw}}; + LcStTestUnlocked0: dec_caliptra_ss_lc_state = {DecLcStateNumRep{DecLcStTestUnlocked0}}; + LcStTestLocked0: dec_caliptra_ss_lc_state = {DecLcStateNumRep{DecLcStTestLocked0}}; + LcStTestUnlocked1: dec_caliptra_ss_lc_state = {DecLcStateNumRep{DecLcStTestUnlocked1}}; + LcStTestLocked1: dec_caliptra_ss_lc_state = {DecLcStateNumRep{DecLcStTestLocked1}}; + LcStTestUnlocked2: dec_caliptra_ss_lc_state = {DecLcStateNumRep{DecLcStTestUnlocked2}}; + LcStTestLocked2: dec_caliptra_ss_lc_state = {DecLcStateNumRep{DecLcStTestLocked2}}; + LcStTestUnlocked3: dec_caliptra_ss_lc_state = {DecLcStateNumRep{DecLcStTestUnlocked3}}; + LcStTestLocked3: dec_caliptra_ss_lc_state = {DecLcStateNumRep{DecLcStTestLocked3}}; + LcStTestUnlocked4: dec_caliptra_ss_lc_state = {DecLcStateNumRep{DecLcStTestUnlocked4}}; + LcStTestLocked4: dec_caliptra_ss_lc_state = {DecLcStateNumRep{DecLcStTestLocked4}}; + LcStTestUnlocked5: dec_caliptra_ss_lc_state = {DecLcStateNumRep{DecLcStTestUnlocked5}}; + LcStTestLocked5: dec_caliptra_ss_lc_state = {DecLcStateNumRep{DecLcStTestLocked5}}; + LcStTestUnlocked6: dec_caliptra_ss_lc_state = {DecLcStateNumRep{DecLcStTestUnlocked6}}; + LcStTestLocked6: dec_caliptra_ss_lc_state = {DecLcStateNumRep{DecLcStTestLocked6}}; + LcStTestUnlocked7: dec_caliptra_ss_lc_state = {DecLcStateNumRep{DecLcStTestUnlocked7}}; + LcStDev: dec_caliptra_ss_lc_state = {DecLcStateNumRep{DecLcStDev}}; + LcStProd: dec_caliptra_ss_lc_state = {DecLcStateNumRep{DecLcStProd}}; + LcStProdEnd: dec_caliptra_ss_lc_state = {DecLcStateNumRep{DecLcStProdEnd}}; + LcStRma: dec_caliptra_ss_lc_state = {DecLcStateNumRep{DecLcStRma}}; + LcStScrap: dec_caliptra_ss_lc_state = {DecLcStateNumRep{DecLcStScrap}}; + // SEC_CM: MANUF.STATE.BKGN_CHK + default: state_invalid_error_o[1] = 1'b1; + endcase // caliptra_ss_lc_state_i + + unique case (caliptra_ss_lc_cnt_i) + LcCnt0: dec_caliptra_ss_lc_cnt_o = 5'd0; + LcCnt1: dec_caliptra_ss_lc_cnt_o = 5'd1; + LcCnt2: dec_caliptra_ss_lc_cnt_o = 5'd2; + LcCnt3: dec_caliptra_ss_lc_cnt_o = 5'd3; + LcCnt4: dec_caliptra_ss_lc_cnt_o = 5'd4; + LcCnt5: dec_caliptra_ss_lc_cnt_o = 5'd5; + LcCnt6: dec_caliptra_ss_lc_cnt_o = 5'd6; + LcCnt7: dec_caliptra_ss_lc_cnt_o = 5'd7; + LcCnt8: dec_caliptra_ss_lc_cnt_o = 5'd8; + LcCnt9: dec_caliptra_ss_lc_cnt_o = 5'd9; + LcCnt10: dec_caliptra_ss_lc_cnt_o = 5'd10; + LcCnt11: dec_caliptra_ss_lc_cnt_o = 5'd11; + LcCnt12: dec_caliptra_ss_lc_cnt_o = 5'd12; + LcCnt13: dec_caliptra_ss_lc_cnt_o = 5'd13; + LcCnt14: dec_caliptra_ss_lc_cnt_o = 5'd14; + LcCnt15: dec_caliptra_ss_lc_cnt_o = 5'd15; + LcCnt16: dec_caliptra_ss_lc_cnt_o = 5'd16; + LcCnt17: dec_caliptra_ss_lc_cnt_o = 5'd17; + LcCnt18: dec_caliptra_ss_lc_cnt_o = 5'd18; + LcCnt19: dec_caliptra_ss_lc_cnt_o = 5'd19; + LcCnt20: dec_caliptra_ss_lc_cnt_o = 5'd20; + LcCnt21: dec_caliptra_ss_lc_cnt_o = 5'd21; + LcCnt22: dec_caliptra_ss_lc_cnt_o = 5'd22; + LcCnt23: dec_caliptra_ss_lc_cnt_o = 5'd23; + LcCnt24: dec_caliptra_ss_lc_cnt_o = 5'd24; + // SEC_CM: TRANSITION.CTR.BKGN_CHK + default: state_invalid_error_o[2] = 1'b1; + endcase // caliptra_ss_lc_cnt_i + + // SEC_CM: MANUF.STATE.BKGN_CHK + unique case (secrets_valid_i) + // If the secrets have not been provisioned, the ID state is "blank". + Off: dec_caliptra_ss_lc_id_state_o = DecLcIdBlank; + // If the secrets have been provisioned, the ID state is "personalized". + On: dec_caliptra_ss_lc_id_state_o = DecLcIdPersonalized; + default: state_invalid_error_o[3] = 1'b1; + endcase // secrets_valid_i + + // Require that any non-raw state has a valid, nonzero + // transition count. + // SEC_CM: TRANSITION.CTR.BKGN_CHK + if (caliptra_ss_lc_state_i != LcStRaw && caliptra_ss_lc_cnt_i == LcCnt0) begin + state_invalid_error_o[4] = 1'b1; + end + + // We can't have a personalized device that is + // still in RAW or any of the test states. + // SEC_CM: MANUF.STATE.BKGN_CHK + if (caliptra_ss_lc_tx_test_true_strict(secrets_valid_i) && + !(caliptra_ss_lc_state_i inside {LcStDev, + LcStProd, + LcStProdEnd, + LcStRma, + LcStScrap})) begin + state_invalid_error_o[5] = 1'b1; + end + end + endcase // caliptra_ss_lc_id_state_i + end + + //////////////// + // Assertions // + //////////////// + + +endmodule : caliptra_ss_lc_ctrl_state_decode diff --git a/src/caliptra_ss_lc_ctrl/rtl/caliptra_ss_lc_ctrl_state_pkg.sv b/src/caliptra_ss_lc_ctrl/rtl/caliptra_ss_lc_ctrl_state_pkg.sv new file mode 100644 index 0000000..5bda57f --- /dev/null +++ b/src/caliptra_ss_lc_ctrl/rtl/caliptra_ss_lc_ctrl_state_pkg.sv @@ -0,0 +1,433 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Life cycle state encoding definition. +// +// DO NOT EDIT THIS FILE DIRECTLY. +// It has been generated with +// $ ./util/design/gen-lc-state-enc.py --seed 40182201019264397688411770949626922549663256047001778394918990008320537410392 +// +package caliptra_ss_lc_ctrl_state_pkg; + + import caliptra_prim_util_pkg::vbits; + + /////////////////////////////// + // General size declarations // + /////////////////////////////// + + parameter int LcValueWidth = 16; + + parameter int NumLcStateValues = 20; + parameter int LcStateWidth = NumLcStateValues * LcValueWidth; + parameter int NumLcStates = 21; + parameter int DecLcStateWidth = vbits(NumLcStates); + parameter int NumSocDbgStateValues = 2; + parameter int SocDbgStateWidth = NumSocDbgStateValues * LcValueWidth; + parameter int NumOwnershipStateValues = 8; + parameter int OwnershipStateWidth = NumOwnershipStateValues * LcValueWidth; + parameter int NumAuthStateValues = 2; + parameter int AuthStateWidth = NumAuthStateValues * LcValueWidth; + + // Redundant version used in the CSRs. + parameter int DecLcStateNumRep = 32/DecLcStateWidth; + parameter int ExtDecLcStateWidth = DecLcStateNumRep*DecLcStateWidth; + + parameter int NumLcCountValues = 24; + parameter int LcCountWidth = NumLcCountValues * LcValueWidth; + parameter int NumLcCountStates = 25; + parameter int DecLcCountWidth = vbits(NumLcCountStates); + + // This state is not stored in OTP, but inferred from the locked + // status of the secret partitions. Hence, only the decoded ID state + // is declared here for exposure through the CSR interface. + parameter int NumLcIdStates = 2; + parameter int DecLcIdStateWidth = vbits(NumLcIdStates+1); + // Redundant version used in the CSRs. + parameter int DecLcIdStateNumRep = 32/DecLcIdStateWidth; + parameter int ExtDecLcIdStateWidth = DecLcIdStateNumRep*DecLcIdStateWidth; + + ///////////////////////////////////////////// + // Life cycle manufacturing state encoding // + ///////////////////////////////////////////// + + // These values have been generated such that they are incrementally writeable with respect + // to the ECC polynomial specified. The values are used to define the life cycle manufacturing + // state and transition counter encoding in caliptra_ss_lc_ctrl_pkg.sv. + // + // The values are unique and have the following statistics (considering all 16 + // data and 6 ECC bits): + // + // - Minimum Hamming weight: 6 + // - Maximum Hamming weight: 16 + // - Minimum Hamming distance from any other value: 6 + // - Maximum Hamming distance from any other value: 18 + // + // Hamming distance histogram: + // + // 0: -- + // 1: -- + // 2: -- + // 3: -- + // 4: -- + // 5: -- + // 6: ||| (5.04%) + // 7: -- + // 8: ||||||||||| (16.97%) + // 9: -- + // 10: |||||||||||||||||||| (30.12%) + // 11: -- + // 12: ||||||||||||||||||| (29.34%) + // 13: -- + // 14: ||||||||| (14.35%) + // 15: -- + // 16: || (3.80%) + // 17: -- + // 18: (0.39%) + // 19: -- + // 20: -- + // 21: -- + // 22: -- + // + // + // Note that the ECC bits are not defined in this package as they will be calculated by + // the OTP ECC logic at runtime. + + // SEC_CM: MANUF.STATE.SPARSE + // The A/B values are used for the encoded LC state. + parameter logic [15:0] A0 = 16'b0110010010101110; // ECC: 6'b001010 + parameter logic [15:0] B0 = 16'b0111010111101110; // ECC: 6'b111110 + + parameter logic [15:0] A1 = 16'b0000011110110100; // ECC: 6'b100101 + parameter logic [15:0] B1 = 16'b0000111111111110; // ECC: 6'b111101 + + parameter logic [15:0] A2 = 16'b0011000111010010; // ECC: 6'b000111 + parameter logic [15:0] B2 = 16'b0111101111111110; // ECC: 6'b000111 + + parameter logic [15:0] A3 = 16'b0010111001001101; // ECC: 6'b001010 + parameter logic [15:0] B3 = 16'b0011111101101111; // ECC: 6'b111010 + + parameter logic [15:0] A4 = 16'b0100000111111000; // ECC: 6'b011010 + parameter logic [15:0] B4 = 16'b0101111111111100; // ECC: 6'b011110 + + parameter logic [15:0] A5 = 16'b1010110010000101; // ECC: 6'b110001 + parameter logic [15:0] B5 = 16'b1111110110011111; // ECC: 6'b110001 + + parameter logic [15:0] A6 = 16'b1001100110001100; // ECC: 6'b010110 + parameter logic [15:0] B6 = 16'b1111100110011111; // ECC: 6'b011110 + + parameter logic [15:0] A7 = 16'b0101001100001111; // ECC: 6'b100010 + parameter logic [15:0] B7 = 16'b1101101101101111; // ECC: 6'b100111 + + parameter logic [15:0] A8 = 16'b0111000101100000; // ECC: 6'b111001 + parameter logic [15:0] B8 = 16'b0111001101111111; // ECC: 6'b111001 + + parameter logic [15:0] A9 = 16'b0010110001100011; // ECC: 6'b101010 + parameter logic [15:0] B9 = 16'b0110110001101111; // ECC: 6'b111111 + + parameter logic [15:0] A10 = 16'b0110110100001000; // ECC: 6'b110011 + parameter logic [15:0] B10 = 16'b0110111110011110; // ECC: 6'b111011 + + parameter logic [15:0] A11 = 16'b1001001001001100; // ECC: 6'b000011 + parameter logic [15:0] B11 = 16'b1101001111011100; // ECC: 6'b111111 + + parameter logic [15:0] A12 = 16'b0111000001000000; // ECC: 6'b011110 + parameter logic [15:0] B12 = 16'b0111011101010010; // ECC: 6'b111110 + + parameter logic [15:0] A13 = 16'b1001001010111110; // ECC: 6'b000010 + parameter logic [15:0] B13 = 16'b1111001011111110; // ECC: 6'b101110 + + parameter logic [15:0] A14 = 16'b1001010011010010; // ECC: 6'b100011 + parameter logic [15:0] B14 = 16'b1011110111010011; // ECC: 6'b101111 + + parameter logic [15:0] A15 = 16'b0110001010001101; // ECC: 6'b000111 + parameter logic [15:0] B15 = 16'b0110111111001101; // ECC: 6'b011111 + + parameter logic [15:0] A16 = 16'b1011001000101000; // ECC: 6'b010111 + parameter logic [15:0] B16 = 16'b1011001011111011; // ECC: 6'b011111 + + parameter logic [15:0] A17 = 16'b0001111001110001; // ECC: 6'b001001 + parameter logic [15:0] B17 = 16'b1001111111110101; // ECC: 6'b011011 + + parameter logic [15:0] A18 = 16'b0010110110011011; // ECC: 6'b000100 + parameter logic [15:0] B18 = 16'b0011111111011111; // ECC: 6'b010101 + + parameter logic [15:0] A19 = 16'b0100110110001100; // ECC: 6'b101010 + parameter logic [15:0] B19 = 16'b1101110110111110; // ECC: 6'b101011 + + + // SEC_CM: TRANSITION.CTR.SPARSE + // The C/D values are used for the encoded LC transition counter. + parameter logic [15:0] C0 = 16'b0001010010011110; // ECC: 6'b011100 + parameter logic [15:0] D0 = 16'b1011011011011111; // ECC: 6'b111100 + + parameter logic [15:0] C1 = 16'b0101101011000100; // ECC: 6'b111000 + parameter logic [15:0] D1 = 16'b1111101011110100; // ECC: 6'b111101 + + parameter logic [15:0] C2 = 16'b0001111100100100; // ECC: 6'b100011 + parameter logic [15:0] D2 = 16'b0001111110111111; // ECC: 6'b100111 + + parameter logic [15:0] C3 = 16'b1100111010000101; // ECC: 6'b011000 + parameter logic [15:0] D3 = 16'b1100111011101111; // ECC: 6'b011011 + + parameter logic [15:0] C4 = 16'b0100001010011111; // ECC: 6'b011000 + parameter logic [15:0] D4 = 16'b0101101110111111; // ECC: 6'b111100 + + parameter logic [15:0] C5 = 16'b1001111000100010; // ECC: 6'b111000 + parameter logic [15:0] D5 = 16'b1111111110100010; // ECC: 6'b111110 + + parameter logic [15:0] C6 = 16'b0010011110000110; // ECC: 6'b010000 + parameter logic [15:0] D6 = 16'b0111011111000110; // ECC: 6'b011101 + + parameter logic [15:0] C7 = 16'b0010111101000110; // ECC: 6'b000110 + parameter logic [15:0] D7 = 16'b1010111111000110; // ECC: 6'b111111 + + parameter logic [15:0] C8 = 16'b0000001011011011; // ECC: 6'b000001 + parameter logic [15:0] D8 = 16'b1010101111011011; // ECC: 6'b111011 + + parameter logic [15:0] C9 = 16'b0111000011000110; // ECC: 6'b110001 + parameter logic [15:0] D9 = 16'b1111111011001110; // ECC: 6'b110011 + + parameter logic [15:0] C10 = 16'b0100001000010010; // ECC: 6'b110110 + parameter logic [15:0] D10 = 16'b0111001010110110; // ECC: 6'b110111 + + parameter logic [15:0] C11 = 16'b0100101111110001; // ECC: 6'b000001 + parameter logic [15:0] D11 = 16'b0110101111110011; // ECC: 6'b110111 + + parameter logic [15:0] C12 = 16'b1000100101000001; // ECC: 6'b000001 + parameter logic [15:0] D12 = 16'b1011110101001111; // ECC: 6'b001011 + + parameter logic [15:0] C13 = 16'b1000000000010001; // ECC: 6'b011111 + parameter logic [15:0] D13 = 16'b1001100010110011; // ECC: 6'b111111 + + parameter logic [15:0] C14 = 16'b0101110000000100; // ECC: 6'b111110 + parameter logic [15:0] D14 = 16'b1111111010001101; // ECC: 6'b111110 + + parameter logic [15:0] C15 = 16'b1100001000001001; // ECC: 6'b001011 + parameter logic [15:0] D15 = 16'b1110011000011011; // ECC: 6'b111011 + + parameter logic [15:0] C16 = 16'b0101001001101100; // ECC: 6'b001000 + parameter logic [15:0] D16 = 16'b0111111001111110; // ECC: 6'b001001 + + parameter logic [15:0] C17 = 16'b0100001001110100; // ECC: 6'b010100 + parameter logic [15:0] D17 = 16'b1100101001110111; // ECC: 6'b110110 + + parameter logic [15:0] C18 = 16'b1100000001100111; // ECC: 6'b100000 + parameter logic [15:0] D18 = 16'b1100011101110111; // ECC: 6'b100101 + + parameter logic [15:0] C19 = 16'b1010000001001010; // ECC: 6'b101111 + parameter logic [15:0] D19 = 16'b1111011101101010; // ECC: 6'b101111 + + parameter logic [15:0] C20 = 16'b1001001001010101; // ECC: 6'b001110 + parameter logic [15:0] D20 = 16'b1101111011011101; // ECC: 6'b001111 + + parameter logic [15:0] C21 = 16'b1001010000011011; // ECC: 6'b100000 + parameter logic [15:0] D21 = 16'b1001111000111011; // ECC: 6'b110101 + + parameter logic [15:0] C22 = 16'b1011101101100001; // ECC: 6'b000100 + parameter logic [15:0] D22 = 16'b1011111101111111; // ECC: 6'b000110 + + parameter logic [15:0] C23 = 16'b1101101000000111; // ECC: 6'b001100 + parameter logic [15:0] D23 = 16'b1101111011100111; // ECC: 6'b101110 + + + // The F/E values are used for the encoded SOC_DBG state. + parameter logic [15:0] E0 = 16'b0000101001000100; // ECC: 6'b010010 + parameter logic [15:0] F0 = 16'b1001111001101100; // ECC: 6'b110111 + + parameter logic [15:0] E1 = 16'b0000110111111000; // ECC: 6'b110000 + parameter logic [15:0] F1 = 16'b1100111111111001; // ECC: 6'b111100 + + + // The G/H values are used for the encoded OWNERSHIP state. + parameter logic [15:0] G0 = 16'b0110000100111100; // ECC: 6'b001000 + parameter logic [15:0] H0 = 16'b0111010110111100; // ECC: 6'b111001 + + parameter logic [15:0] G1 = 16'b1000110100111001; // ECC: 6'b100001 + parameter logic [15:0] H1 = 16'b1011110101111101; // ECC: 6'b101101 + + parameter logic [15:0] G2 = 16'b0110100001100010; // ECC: 6'b010010 + parameter logic [15:0] H2 = 16'b1111100111101010; // ECC: 6'b010011 + + parameter logic [15:0] G3 = 16'b1001001110000101; // ECC: 6'b001101 + parameter logic [15:0] H3 = 16'b1101001110110111; // ECC: 6'b011111 + + parameter logic [15:0] G4 = 16'b1010011000011101; // ECC: 6'b001100 + parameter logic [15:0] H4 = 16'b1110011101011101; // ECC: 6'b111110 + + parameter logic [15:0] G5 = 16'b1110110101100000; // ECC: 6'b000000 + parameter logic [15:0] H5 = 16'b1110111111101001; // ECC: 6'b000110 + + parameter logic [15:0] G6 = 16'b1011000100101010; // ECC: 6'b110001 + parameter logic [15:0] H6 = 16'b1111101110101011; // ECC: 6'b110101 + + parameter logic [15:0] G7 = 16'b0000111110001010; // ECC: 6'b010011 + parameter logic [15:0] H7 = 16'b1100111110111110; // ECC: 6'b010111 + + + // The I/Jvalues are used for the encoded AUTH state. + parameter logic [15:0] I0 = 16'b0110011110000001; // ECC: 6'b000100 + parameter logic [15:0] J0 = 16'b0111111110100001; // ECC: 6'b101101 + + parameter logic [15:0] I1 = 16'b1110100010100001; // ECC: 6'b100110 + parameter logic [15:0] J1 = 16'b1110100111110101; // ECC: 6'b101111 + + + parameter logic [15:0] ZRO = 16'h0; + + //////////////////////// + // Derived enum types // + //////////////////////// + + // Use caliptra_ss_lc_state_t and caliptra_ss_lc_cnt_t in interfaces as very wide enumerations ( > 64 bits ) + // are not supported for virtual interfaces by Excelium yet + // https://github.com/lowRISC/opentitan/issues/8884 (Cadence issue: cds_46570160) + // The enumeration types caliptra_ss_lc_state_e and caliptra_ss_lc_cnt_e are still ok in other circumstances + + typedef logic [LcStateWidth-1:0] caliptra_ss_lc_state_t; + typedef enum caliptra_ss_lc_state_t { + LcStRaw = {ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO}, + LcStTestUnlocked0 = {A19, A18, A17, A16, A15, A14, A13, A12, A11, A10, A9, A8, A7, A6, A5, A4, A3, A2, A1, B0}, + LcStTestLocked0 = {A19, A18, A17, A16, A15, A14, A13, A12, A11, A10, A9, A8, A7, A6, A5, A4, A3, A2, B1, B0}, + LcStTestUnlocked1 = {A19, A18, A17, A16, A15, A14, A13, A12, A11, A10, A9, A8, A7, A6, A5, A4, A3, B2, B1, B0}, + LcStTestLocked1 = {A19, A18, A17, A16, A15, A14, A13, A12, A11, A10, A9, A8, A7, A6, A5, A4, B3, B2, B1, B0}, + LcStTestUnlocked2 = {A19, A18, A17, A16, A15, A14, A13, A12, A11, A10, A9, A8, A7, A6, A5, B4, B3, B2, B1, B0}, + LcStTestLocked2 = {A19, A18, A17, A16, A15, A14, A13, A12, A11, A10, A9, A8, A7, A6, B5, B4, B3, B2, B1, B0}, + LcStTestUnlocked3 = {A19, A18, A17, A16, A15, A14, A13, A12, A11, A10, A9, A8, A7, B6, B5, B4, B3, B2, B1, B0}, + LcStTestLocked3 = {A19, A18, A17, A16, A15, A14, A13, A12, A11, A10, A9, A8, B7, B6, B5, B4, B3, B2, B1, B0}, + LcStTestUnlocked4 = {A19, A18, A17, A16, A15, A14, A13, A12, A11, A10, A9, B8, B7, B6, B5, B4, B3, B2, B1, B0}, + LcStTestLocked4 = {A19, A18, A17, A16, A15, A14, A13, A12, A11, A10, B9, B8, B7, B6, B5, B4, B3, B2, B1, B0}, + LcStTestUnlocked5 = {A19, A18, A17, A16, A15, A14, A13, A12, A11, B10, B9, B8, B7, B6, B5, B4, B3, B2, B1, B0}, + LcStTestLocked5 = {A19, A18, A17, A16, A15, A14, A13, A12, B11, B10, B9, B8, B7, B6, B5, B4, B3, B2, B1, B0}, + LcStTestUnlocked6 = {A19, A18, A17, A16, A15, A14, A13, B12, B11, B10, B9, B8, B7, B6, B5, B4, B3, B2, B1, B0}, + LcStTestLocked6 = {A19, A18, A17, A16, A15, A14, B13, B12, B11, B10, B9, B8, B7, B6, B5, B4, B3, B2, B1, B0}, + LcStTestUnlocked7 = {A19, A18, A17, A16, A15, B14, B13, B12, B11, B10, B9, B8, B7, B6, B5, B4, B3, B2, B1, B0}, + LcStDev = {A19, A18, A17, A16, B15, B14, B13, B12, B11, B10, B9, B8, B7, B6, B5, B4, B3, B2, B1, B0}, + LcStProd = {A19, A18, A17, B16, A15, B14, B13, B12, B11, B10, B9, B8, B7, B6, B5, B4, B3, B2, B1, B0}, + LcStProdEnd = {A19, A18, B17, A16, A15, B14, B13, B12, B11, B10, B9, B8, B7, B6, B5, B4, B3, B2, B1, B0}, + LcStRma = {B19, B18, A17, B16, B15, B14, B13, B12, B11, B10, B9, B8, B7, B6, B5, B4, B3, B2, B1, B0}, + LcStScrap = {B19, B18, B17, B16, B15, B14, B13, B12, B11, B10, B9, B8, B7, B6, B5, B4, B3, B2, B1, B0} + } caliptra_ss_lc_state_e; + + typedef logic [LcCountWidth-1:0] caliptra_ss_lc_cnt_t; + typedef enum caliptra_ss_lc_cnt_t { + LcCnt0 = {ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO}, + LcCnt1 = {C23, C22, C21, C20, C19, C18, C17, C16, C15, C14, C13, C12, C11, C10, C9, C8, C7, C6, C5, C4, C3, C2, C1, D0}, + LcCnt2 = {C23, C22, C21, C20, C19, C18, C17, C16, C15, C14, C13, C12, C11, C10, C9, C8, C7, C6, C5, C4, C3, C2, D1, D0}, + LcCnt3 = {C23, C22, C21, C20, C19, C18, C17, C16, C15, C14, C13, C12, C11, C10, C9, C8, C7, C6, C5, C4, C3, D2, D1, D0}, + LcCnt4 = {C23, C22, C21, C20, C19, C18, C17, C16, C15, C14, C13, C12, C11, C10, C9, C8, C7, C6, C5, C4, D3, D2, D1, D0}, + LcCnt5 = {C23, C22, C21, C20, C19, C18, C17, C16, C15, C14, C13, C12, C11, C10, C9, C8, C7, C6, C5, D4, D3, D2, D1, D0}, + LcCnt6 = {C23, C22, C21, C20, C19, C18, C17, C16, C15, C14, C13, C12, C11, C10, C9, C8, C7, C6, D5, D4, D3, D2, D1, D0}, + LcCnt7 = {C23, C22, C21, C20, C19, C18, C17, C16, C15, C14, C13, C12, C11, C10, C9, C8, C7, D6, D5, D4, D3, D2, D1, D0}, + LcCnt8 = {C23, C22, C21, C20, C19, C18, C17, C16, C15, C14, C13, C12, C11, C10, C9, C8, D7, D6, D5, D4, D3, D2, D1, D0}, + LcCnt9 = {C23, C22, C21, C20, C19, C18, C17, C16, C15, C14, C13, C12, C11, C10, C9, D8, D7, D6, D5, D4, D3, D2, D1, D0}, + LcCnt10 = {C23, C22, C21, C20, C19, C18, C17, C16, C15, C14, C13, C12, C11, C10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0}, + LcCnt11 = {C23, C22, C21, C20, C19, C18, C17, C16, C15, C14, C13, C12, C11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0}, + LcCnt12 = {C23, C22, C21, C20, C19, C18, C17, C16, C15, C14, C13, C12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0}, + LcCnt13 = {C23, C22, C21, C20, C19, C18, C17, C16, C15, C14, C13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0}, + LcCnt14 = {C23, C22, C21, C20, C19, C18, C17, C16, C15, C14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0}, + LcCnt15 = {C23, C22, C21, C20, C19, C18, C17, C16, C15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0}, + LcCnt16 = {C23, C22, C21, C20, C19, C18, C17, C16, D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0}, + LcCnt17 = {C23, C22, C21, C20, C19, C18, C17, D16, D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0}, + LcCnt18 = {C23, C22, C21, C20, C19, C18, D17, D16, D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0}, + LcCnt19 = {C23, C22, C21, C20, C19, D18, D17, D16, D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0}, + LcCnt20 = {C23, C22, C21, C20, D19, D18, D17, D16, D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0}, + LcCnt21 = {C23, C22, C21, D20, D19, D18, D17, D16, D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0}, + LcCnt22 = {C23, C22, D21, D20, D19, D18, D17, D16, D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0}, + LcCnt23 = {C23, D22, D21, D20, D19, D18, D17, D16, D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0}, + LcCnt24 = {D23, D22, D21, D20, D19, D18, D17, D16, D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0} + } caliptra_ss_lc_cnt_e; + + typedef logic [SocDbgStateWidth-1:0] soc_dbg_state_t; + typedef enum soc_dbg_state_t { + SocDbgStBlank = {ZRO, ZRO}, + SocDbgStPreProd = { E1, E0}, + SocDbgStProd = { F1, F0} + } soc_dbg_state_e; + + typedef logic [OwnershipStateWidth-1:0] ownership_state_t; + typedef enum ownership_state_t { + OwnershipStBlank = {ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO}, + OwnershipStLocked0 = { G7, G6, G5, G4, G3, G2, G1, G0}, + OwnershipStReleased0 = { G7, G6, G5, G4, G3, G2, G1, H0}, + OwnershipStLocked1 = { G7, G6, G5, G4, G3, G2, H1, H0}, + OwnershipStReleased1 = { G7, G6, G5, G4, G3, H2, H1, H0}, + OwnershipStLocked2 = { G7, G6, G5, G4, H3, H2, H1, H0}, + OwnershipStReleased2 = { G7, G6, G5, H4, H3, H2, H1, H0}, + OwnershipStLocked3 = { G7, G6, H5, H4, H3, H2, H1, H0}, + OwnershipStScrapped = { H7, H6, H5, H4, H3, H2, H1, H0} + } ownership_state_e; + + typedef logic [AuthStateWidth-1:0] auth_state_t; + typedef enum auth_state_t { + AuthStBlank = {ZRO, ZRO}, + AuthStEnabled = { I1, I0}, + AuthStDisabled = { J1, J0} + } auth_state_e; + + // Decoded life cycle state, used to interface with CSRs and TAP. + typedef enum logic [DecLcStateWidth-1:0] { + DecLcStRaw = 0, + DecLcStTestUnlocked0 = 1, + DecLcStTestLocked0 = 2, + DecLcStTestUnlocked1 = 3, + DecLcStTestLocked1 = 4, + DecLcStTestUnlocked2 = 5, + DecLcStTestLocked2 = 6, + DecLcStTestUnlocked3 = 7, + DecLcStTestLocked3 = 8, + DecLcStTestUnlocked4 = 9, + DecLcStTestLocked4 = 10, + DecLcStTestUnlocked5 = 11, + DecLcStTestLocked5 = 12, + DecLcStTestUnlocked6 = 13, + DecLcStTestLocked6 = 14, + DecLcStTestUnlocked7 = 15, + DecLcStDev = 16, + DecLcStProd = 17, + DecLcStProdEnd = 18, + DecLcStRma = 19, + DecLcStScrap = 20, + DecLcStPostTrans = 21, + DecLcStEscalate = 22, + DecLcStInvalid = 23 + } dec_caliptra_ss_lc_state_e; + + typedef dec_caliptra_ss_lc_state_e [DecLcStateNumRep-1:0] ext_dec_caliptra_ss_lc_state_t; + + typedef enum logic [DecLcIdStateWidth-1:0] { + DecLcIdBlank, + DecLcIdPersonalized, + DecLcIdInvalid + } dec_caliptra_ss_lc_id_state_e; + + typedef logic [DecLcCountWidth-1:0] dec_caliptra_ss_lc_cnt_t; + + + /////////////////////////////////////////// + // Hashed RAW unlock and all-zero tokens // + /////////////////////////////////////////// + + parameter int LcTokenWidth = 128; + typedef logic [LcTokenWidth-1:0] caliptra_ss_lc_token_t; + + parameter caliptra_ss_lc_token_t AllZeroToken = { + 128'h0 + }; + parameter caliptra_ss_lc_token_t RndCnstRawUnlockToken = { + 128'hEA2B3F32CBE77554E43C8EA7EBF197C2 + }; + parameter caliptra_ss_lc_token_t AllZeroTokenHashed = { + 128'h3852305BAECF5FF1D5C1D25F6DB9058D + }; + parameter caliptra_ss_lc_token_t RndCnstRawUnlockTokenHashed = { + // 128'hF8FE11B88C36C8140252F036D23804DB + 128'hf12a_5911_4217_48a2_adfc_9693_ef1f_adea + }; + + + parameter caliptra_ss_lc_token_t RndCnstRawUnlockTokenDefault = { + 128'hEA2B3F32CBE77554E43C8EA7EBF197C2 + }; + +endpackage : caliptra_ss_lc_ctrl_state_pkg diff --git a/src/caliptra_ss_lc_ctrl/rtl/caliptra_ss_lc_ctrl_state_transition.sv b/src/caliptra_ss_lc_ctrl/rtl/caliptra_ss_lc_ctrl_state_transition.sv new file mode 100644 index 0000000..5113411 --- /dev/null +++ b/src/caliptra_ss_lc_ctrl/rtl/caliptra_ss_lc_ctrl_state_transition.sv @@ -0,0 +1,207 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Life cycle state transition function. Checks whether a transition is valid +// and computes the target state. This module is purely combinational. + +module caliptra_ss_lc_ctrl_state_transition + import caliptra_ss_lc_ctrl_pkg::*; + import caliptra_ss_lc_ctrl_state_pkg::*; +#( + parameter bit SecVolatileRawUnlockEn = 0 +) ( + // Life cycle state vector. + input caliptra_ss_lc_state_e caliptra_ss_lc_state_i, + input caliptra_ss_lc_cnt_e caliptra_ss_lc_cnt_i, + // Main FSM state. + input fsm_state_e fsm_state_i, + // Decoded lc state input + input ext_dec_caliptra_ss_lc_state_t dec_caliptra_ss_lc_state_i, + // Transition target. + input ext_dec_caliptra_ss_lc_state_t trans_target_i, + // ---------- VOLATILE_TEST_UNLOCKED CODE SECTION START ---------- + // NOTE THAT THIS IS A FEATURE FOR TEST CHIPS ONLY TO MITIGATE + // THE RISK OF A BROKEN OTP MACRO. THIS WILL BE DISABLED VIA + // SecVolatileRawUnlockEn AT COMPILETIME FOR PRODUCTION DEVICES. + // --------------------------------------------------------------- + input logic volatile_raw_unlock_i, + input logic trans_cmd_i, + // ----------- VOLATILE_TEST_UNLOCKED CODE SECTION END ----------- + // Updated state vector. + output caliptra_ss_lc_state_e next_caliptra_ss_lc_state_o, + output caliptra_ss_lc_cnt_e next_caliptra_ss_lc_cnt_o, + // If the transition counter is maxed out + output logic trans_cnt_oflw_error_o, + output logic trans_invalid_error_o +); + + ////////////////////////// + // Signal Decoder Logic // + ////////////////////////// + + if (!SecVolatileRawUnlockEn) begin : gen_no_volatile_unlock + logic unused_trans_cmd; + assign unused_trans_cmd = trans_cmd_i; + end + + // The decoder logic below checks whether a given transition edge + // is valid and computes the next lc counter ans state vectors. + always_comb begin : p_caliptra_ss_lc_state_transition + // Decoded state defaults + next_caliptra_ss_lc_cnt_o = caliptra_ss_lc_cnt_i; + next_caliptra_ss_lc_state_o = caliptra_ss_lc_state_i; + trans_cnt_oflw_error_o = 1'b0; + trans_invalid_error_o = 1'b0; + + // ---------- VOLATILE_TEST_UNLOCKED CODE SECTION START ---------- + // NOTE THAT THIS IS A FEATURE FOR TEST CHIPS ONLY TO MITIGATE + // THE RISK OF A BROKEN OTP MACRO. THIS WILL BE DISABLED VIA + // SecVolatileRawUnlockEn AT COMPILETIME FOR PRODUCTION DEVICES. + // --------------------------------------------------------------- + // Only enter here if volatile RAW unlock is available and enabled. + if (SecVolatileRawUnlockEn && volatile_raw_unlock_i && trans_cmd_i && fsm_state_i == IdleSt) + begin + // We only allow transitions from RAW -> TEST_UNLOCKED0 + if (dec_caliptra_ss_lc_state_i != {DecLcStateNumRep{DecLcStRaw}} || + trans_target_i != {DecLcStateNumRep{DecLcStTestUnlocked0}}) begin + trans_invalid_error_o = 1'b1; + end + end + // ----------- VOLATILE_TEST_UNLOCKED CODE SECTION END ----------- + + if (fsm_state_i inside {CntIncrSt, + CntProgSt, + // Since OTP programming is incremental, we have to keep the next + // counter state assigned when performing the actual state transition + // in the second programming pass to prevent OTP programming errors. + TransCheckSt, + TokenCheck0St, + TokenCheck1St, + TransProgSt}) begin + // In this state, the life cycle counter is incremented. + // Throw an error if the counter is already maxed out. + unique case (caliptra_ss_lc_cnt_i) + LcCnt0: next_caliptra_ss_lc_cnt_o = LcCnt1; + LcCnt1: next_caliptra_ss_lc_cnt_o = LcCnt2; + LcCnt2: next_caliptra_ss_lc_cnt_o = LcCnt3; + LcCnt3: next_caliptra_ss_lc_cnt_o = LcCnt4; + LcCnt4: next_caliptra_ss_lc_cnt_o = LcCnt5; + LcCnt5: next_caliptra_ss_lc_cnt_o = LcCnt6; + LcCnt6: next_caliptra_ss_lc_cnt_o = LcCnt7; + LcCnt7: next_caliptra_ss_lc_cnt_o = LcCnt8; + LcCnt8: next_caliptra_ss_lc_cnt_o = LcCnt9; + LcCnt9: next_caliptra_ss_lc_cnt_o = LcCnt10; + LcCnt10: next_caliptra_ss_lc_cnt_o = LcCnt11; + LcCnt11: next_caliptra_ss_lc_cnt_o = LcCnt12; + LcCnt12: next_caliptra_ss_lc_cnt_o = LcCnt13; + LcCnt13: next_caliptra_ss_lc_cnt_o = LcCnt14; + LcCnt14: next_caliptra_ss_lc_cnt_o = LcCnt15; + LcCnt15: next_caliptra_ss_lc_cnt_o = LcCnt16; + LcCnt16: next_caliptra_ss_lc_cnt_o = LcCnt17; + LcCnt17: next_caliptra_ss_lc_cnt_o = LcCnt18; + LcCnt18: next_caliptra_ss_lc_cnt_o = LcCnt19; + LcCnt19: next_caliptra_ss_lc_cnt_o = LcCnt20; + LcCnt20: next_caliptra_ss_lc_cnt_o = LcCnt21; + LcCnt21: next_caliptra_ss_lc_cnt_o = LcCnt22; + LcCnt22: next_caliptra_ss_lc_cnt_o = LcCnt23; + LcCnt23: next_caliptra_ss_lc_cnt_o = LcCnt24; + LcCnt24: trans_cnt_oflw_error_o = 1'b1; + default: trans_cnt_oflw_error_o = 1'b1; + endcase // caliptra_ss_lc_cnt_i + + // We always allow transitions into the SCRAP state, so the overflow error is silenced in that + // particular case. In that case we max out the transition counter and force the + // next_caliptra_ss_lc_state already into SCRAP so that the error silencing above cannot be abused. This + // means that when moving to SCRAP state, we program LcStScrap twice: once during the counter + // increment phase, and once during the actual state programming phase. + if (trans_target_i == {DecLcStateNumRep{DecLcStScrap}}) begin + next_caliptra_ss_lc_cnt_o = LcCnt24; + next_caliptra_ss_lc_state_o = LcStScrap; + trans_cnt_oflw_error_o = 1'b0; + end + end + + if (fsm_state_i inside {TransCheckSt, + TokenCheck0St, + TokenCheck1St, + TransProgSt}) begin + // SEC_CM: STATE.CONFIG.SPARSE + // Check that the decoded transition indexes are valid before indexing the state transition + // matrix. We perform the check twice with different indices into the replicated state + // enumeration. + if (dec_caliptra_ss_lc_state_i[0] <= DecLcStScrap && + trans_target_i[0] <= DecLcStScrap && + dec_caliptra_ss_lc_state_i[1] <= DecLcStScrap && + trans_target_i[1] <= DecLcStScrap) begin + // Check the state transition token matrix in order to see whether this transition is valid. + // All transitions have a token index value different from InvalidTokenIdx. We perform the + // check twice with different indices into the replicated state enumeration. + if (TransTokenIdxMatrix[dec_caliptra_ss_lc_state_i[0]][trans_target_i[0]] != InvalidTokenIdx || + TransTokenIdxMatrix[dec_caliptra_ss_lc_state_i[1]][trans_target_i[1]] != InvalidTokenIdx) begin + // Encode the target state. + // Note that the life cycle encoding itself also ensures that only certain transitions are + // possible. So even if this logic here is tampered with, the encoding values won't allow + // an invalid transition (instead, the programming operation will fail and leave the life + // cycle state corrupted/invalid). + unique case (trans_target_i) + {DecLcStateNumRep{DecLcStRaw}}: next_caliptra_ss_lc_state_o = LcStRaw; + {DecLcStateNumRep{DecLcStTestUnlocked0}}: next_caliptra_ss_lc_state_o = LcStTestUnlocked0; + {DecLcStateNumRep{DecLcStTestLocked0}}: next_caliptra_ss_lc_state_o = LcStTestLocked0; + {DecLcStateNumRep{DecLcStTestUnlocked1}}: next_caliptra_ss_lc_state_o = LcStTestUnlocked1; + {DecLcStateNumRep{DecLcStTestLocked1}}: next_caliptra_ss_lc_state_o = LcStTestLocked1; + {DecLcStateNumRep{DecLcStTestUnlocked2}}: next_caliptra_ss_lc_state_o = LcStTestUnlocked2; + {DecLcStateNumRep{DecLcStTestLocked2}}: next_caliptra_ss_lc_state_o = LcStTestLocked2; + {DecLcStateNumRep{DecLcStTestUnlocked3}}: next_caliptra_ss_lc_state_o = LcStTestUnlocked3; + {DecLcStateNumRep{DecLcStTestLocked3}}: next_caliptra_ss_lc_state_o = LcStTestLocked3; + {DecLcStateNumRep{DecLcStTestUnlocked4}}: next_caliptra_ss_lc_state_o = LcStTestUnlocked4; + {DecLcStateNumRep{DecLcStTestLocked4}}: next_caliptra_ss_lc_state_o = LcStTestLocked4; + {DecLcStateNumRep{DecLcStTestUnlocked5}}: next_caliptra_ss_lc_state_o = LcStTestUnlocked5; + {DecLcStateNumRep{DecLcStTestLocked5}}: next_caliptra_ss_lc_state_o = LcStTestLocked5; + {DecLcStateNumRep{DecLcStTestUnlocked6}}: next_caliptra_ss_lc_state_o = LcStTestUnlocked6; + {DecLcStateNumRep{DecLcStTestLocked6}}: next_caliptra_ss_lc_state_o = LcStTestLocked6; + {DecLcStateNumRep{DecLcStTestUnlocked7}}: next_caliptra_ss_lc_state_o = LcStTestUnlocked7; + {DecLcStateNumRep{DecLcStDev}}: next_caliptra_ss_lc_state_o = LcStDev; + {DecLcStateNumRep{DecLcStProd}}: next_caliptra_ss_lc_state_o = LcStProd; + {DecLcStateNumRep{DecLcStProdEnd}}: next_caliptra_ss_lc_state_o = LcStProdEnd; + {DecLcStateNumRep{DecLcStRma}}: next_caliptra_ss_lc_state_o = LcStRma; + {DecLcStateNumRep{DecLcStScrap}}: next_caliptra_ss_lc_state_o = LcStScrap; + default: trans_invalid_error_o = 1'b1; + endcase // trans_target_i + end else begin + trans_invalid_error_o = 1'b1; + end + end else begin + trans_invalid_error_o = 1'b1; + end + + // SEC_CM: STATE.CONFIG.SPARSE + // Check that the internally re-encoded life cycle state has a correct encoding. + unique case (dec_caliptra_ss_lc_state_i) + {DecLcStateNumRep{DecLcStRaw}}, + {DecLcStateNumRep{DecLcStTestUnlocked0}}, + {DecLcStateNumRep{DecLcStTestLocked0}}, + {DecLcStateNumRep{DecLcStTestUnlocked1}}, + {DecLcStateNumRep{DecLcStTestLocked1}}, + {DecLcStateNumRep{DecLcStTestUnlocked2}}, + {DecLcStateNumRep{DecLcStTestLocked2}}, + {DecLcStateNumRep{DecLcStTestUnlocked3}}, + {DecLcStateNumRep{DecLcStTestLocked3}}, + {DecLcStateNumRep{DecLcStTestUnlocked4}}, + {DecLcStateNumRep{DecLcStTestLocked4}}, + {DecLcStateNumRep{DecLcStTestUnlocked5}}, + {DecLcStateNumRep{DecLcStTestLocked5}}, + {DecLcStateNumRep{DecLcStTestUnlocked6}}, + {DecLcStateNumRep{DecLcStTestLocked6}}, + {DecLcStateNumRep{DecLcStTestUnlocked7}}, + {DecLcStateNumRep{DecLcStDev}}, + {DecLcStateNumRep{DecLcStProd}}, + {DecLcStateNumRep{DecLcStProdEnd}}, + {DecLcStateNumRep{DecLcStRma}}, + {DecLcStateNumRep{DecLcStScrap}}: ; + default: trans_invalid_error_o = 1'b1; + endcase // trans_target_i + end + end + +endmodule : caliptra_ss_lc_ctrl_state_transition diff --git a/src/caliptra_ss_lc_ctrl/rtl/jtag_pkg.sv b/src/caliptra_ss_lc_ctrl/rtl/jtag_pkg.sv new file mode 100644 index 0000000..9a8355e --- /dev/null +++ b/src/caliptra_ss_lc_ctrl/rtl/jtag_pkg.sv @@ -0,0 +1,24 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// + +package jtag_pkg; + + typedef struct packed { + logic tck; + logic tms; + logic trst_n; + logic tdi; + } jtag_req_t; + + parameter jtag_req_t JTAG_REQ_DEFAULT = '0; + + typedef struct packed { + logic tdo; + logic tdo_oe; + } jtag_rsp_t; + + parameter jtag_rsp_t JTAG_RSP_DEFAULT = '0; + +endpackage : jtag_pkg diff --git a/src/caliptra_ss_lc_ctrl/rtl/keccak_2share.sv b/src/caliptra_ss_lc_ctrl/rtl/keccak_2share.sv new file mode 100644 index 0000000..1653e8c --- /dev/null +++ b/src/caliptra_ss_lc_ctrl/rtl/keccak_2share.sv @@ -0,0 +1,563 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// This module is the single round keccak permutation module +// It supports Keccak with up to 1600b of state + +`include "caliptra_prim_assert.sv" + +module keccak_2share + import caliptra_prim_mubi_pkg::*; +#( + parameter int Width = 1600, // b= {25, 50, 100, 200, 400, 800, 1600} + + // Derived + localparam int W = Width/25, + localparam int L = $clog2(W), + localparam int MaxRound = 12 + 2*L, // Keccak-f only + localparam int RndW = $clog2(MaxRound+1), // Representing up to MaxRound + + // Control parameters + parameter bit EnMasking = 1'b0, // Enable secure hardening + parameter bit ForceRandExt = 1'b0, // 1: Always forward externally provided randomness. + // 0: Switch between external randomness and internal + // intermediate state according to dom_in_rand_ext_i. + localparam int Share = EnMasking ? 2 : 1 +) ( + input clk_i, + input rst_ni, + + input caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_t caliptra_ss_lc_escalate_en_i, // Used to disable SVAs when escalating. + + input [RndW-1:0] rnd_i, // Current round index + + // Control inputs used when EnMasking = 1. + input mubi4_t phase_sel_i, // Output mux contol + input dom_out_low_i, // DOM multiplier output mux + input dom_in_low_i, // DOM multiplier input mux + input dom_in_rand_ext_i, // DOM multiplier input randomness mux + input dom_update_i, // DOM multiplier pipeline reg write enable + + input [Width/2-1:0] rand_i, // Randomness for remasking. + + // State input and output + input [Width-1:0] s_i [Share], + output logic [Width-1:0] s_o [Share] +); + /////////// + // Types // + /////////// + // x y z + typedef logic [4:0][4:0][W-1:0] box_t; // (x,y,z) state + typedef logic [W-1:0] lane_t; // (z) + typedef logic [4:0] [W-1:0] plane_t; // (x,z) + typedef logic [4:0][4:0] slice_t; // (x,y) + typedef logic [4:0][W-1:0] sheet_t; // (y,z) identical to plane_t + typedef logic [4:0] row_t; // (x) + typedef logic [4:0] col_t; // (y) identical to row_t + + ////////////// + // Keccak_f // + ////////////// + box_t state_in [Share]; + box_t state_out [Share]; + box_t theta_data [Share]; + box_t rho_data [Share]; + box_t pi_data [Share]; + box_t chi_data [Share]; + box_t iota_data [Share]; + + box_t phase1_in [Share]; + box_t phase1_out [Share]; + box_t phase2_in [Share]; + box_t phase2_out [Share]; + + ///////////////// + // Unused nets // + ///////////////// + // Tie off input signals that aren't used in the unmasked implementation. + if (!EnMasking) begin : gen_tie_unused + logic unused_clk; + logic unused_rst_n; + mubi4_t unused_phase_sel; + logic unused_dom_ctrl; + logic [Width/2-1:0] unused_rand; + assign unused_clk = clk_i; + assign unused_rst_n = rst_ni; + assign unused_phase_sel = phase_sel_i; + assign unused_dom_ctrl = + ^{dom_out_low_i, dom_in_low_i, dom_in_rand_ext_i, dom_update_i}; + assign unused_rand = rand_i; + end + + ////////////////////////////////////////////////// + // Input/output type conversion and interfacing // + ////////////////////////////////////////////////// + for (genvar i = 0 ; i < Share ; i++) begin : g_state_inout + assign state_in[i] = bitarray_to_box(s_i[i]); + assign s_o[i] = box_to_bitarray(state_out[i]); + end : g_state_inout + + if (EnMasking) begin : g_2share_data + assign phase1_in = state_in; + assign phase2_in = state_in; + + always_comb begin + unique case (phase_sel_i) + MuBi4False: state_out = phase1_out; + MuBi4True: state_out = phase2_out; + default: state_out = phase1_out; + endcase + end + end else begin : g_single_data + assign phase1_in = state_in; + assign phase2_in = phase1_out; + assign state_out = phase2_out; + end + + ////////////// + // Datapath // + ////////////// + for (genvar i = 0 ; i < Share ; i++) begin : g_datapath + + // Phase 1: + assign theta_data[i] = theta(phase1_in[i]); + // Commented out rho function as vcs complains z-Offset%W isn't constant + // assign rho_data[i] = rho(theta_data[i]); + + assign pi_data[i] = pi(rho_data[i]); + + // Phase 2 (Cycles 1, 2 and 3): + // Chi : See below + // Iota: See below + end : g_datapath + + assign phase1_out = pi_data; + + // Iota adds Round Constants(RC), so only one share should be XORed + if (EnMasking) begin : g_2share_iota + assign iota_data[0] = iota(chi_data[0], rnd_i); + assign iota_data[1] = chi_data[1]; + end else begin : g_single_iota + assign iota_data[0] = iota(chi_data[0], rnd_i); + end + + if (EnMasking) begin : g_2share_chi + // Domain-Oriented Masking + // reference: https://eprint.iacr.org/2017/395.pdf + + localparam int unsigned WSheetHalf = $bits(sheet_t)/2; + logic [4:0][WSheetHalf-1:0] in_prd, out_prd; + + ///////////////////// + // DOM multipliers // + ///////////////////// + + for (genvar x = 0 ; x < 5 ; x++) begin : g_chi_w + localparam int X1 = (x + 1) % 5; + localparam int X2 = (x + 2) % 5; + + sheet_t sheet0[Share]; // Inverted input X1 + sheet_t sheet1[Share]; // X2 + sheet_t sheet2[Share]; // DOM output + + assign sheet0[0] = ~phase2_in[0][X1]; + assign sheet0[1] = phase2_in[1][X1]; + + assign sheet1[0] = phase2_in[0][X2]; + assign sheet1[1] = phase2_in[1][X2]; + + // Convert sheet_t to 1D arrays, one for the upper and lower half lane. + logic [WSheetHalf-1:0] a0_l, a1_l, b0_l, b1_l; + logic [WSheetHalf-1:0] a0_h, a1_h, b0_h, b1_h; + logic [WSheetHalf-1:0] a0, a1, b0, b1, q0, q1; + + assign a0_l = {sheet0[0][0][W/2-1:0], + sheet0[0][1][W/2-1:0], + sheet0[0][2][W/2-1:0], + sheet0[0][3][W/2-1:0], + sheet0[0][4][W/2-1:0]}; + assign a1_l = {sheet0[1][0][W/2-1:0], + sheet0[1][1][W/2-1:0], + sheet0[1][2][W/2-1:0], + sheet0[1][3][W/2-1:0], + sheet0[1][4][W/2-1:0]}; + + assign a0_h = {sheet0[0][0][W-1:W/2], + sheet0[0][1][W-1:W/2], + sheet0[0][2][W-1:W/2], + sheet0[0][3][W-1:W/2], + sheet0[0][4][W-1:W/2]}; + assign a1_h = {sheet0[1][0][W-1:W/2], + sheet0[1][1][W-1:W/2], + sheet0[1][2][W-1:W/2], + sheet0[1][3][W-1:W/2], + sheet0[1][4][W-1:W/2]}; + + assign b0_l = {sheet1[0][0][W/2-1:0], + sheet1[0][1][W/2-1:0], + sheet1[0][2][W/2-1:0], + sheet1[0][3][W/2-1:0], + sheet1[0][4][W/2-1:0]}; + assign b1_l = {sheet1[1][0][W/2-1:0], + sheet1[1][1][W/2-1:0], + sheet1[1][2][W/2-1:0], + sheet1[1][3][W/2-1:0], + sheet1[1][4][W/2-1:0]}; + + assign b0_h = {sheet1[0][0][W-1:W/2], + sheet1[0][1][W-1:W/2], + sheet1[0][2][W-1:W/2], + sheet1[0][3][W-1:W/2], + sheet1[0][4][W-1:W/2]}; + assign b1_h = {sheet1[1][0][W-1:W/2], + sheet1[1][1][W-1:W/2], + sheet1[1][2][W-1:W/2], + sheet1[1][3][W-1:W/2], + sheet1[1][4][W-1:W/2]}; + + // Input muxing + assign a0 = dom_in_low_i ? a0_l : a0_h; + assign a1 = dom_in_low_i ? a1_l : a1_h; + assign b0 = dom_in_low_i ? b0_l : b0_h; + assign b1 = dom_in_low_i ? b1_l : b1_h; + + // Randomness muxing + if (!ForceRandExt) begin : gen_in_prd_mux + // Intermediate results are rotated across rows. The new Row x depends on + // data from Rows x + 1 and x + 2. Hence we don't want to use intermediate + // results from Rows x, x + 1, and x + 2 for remasking. + assign in_prd[x] = dom_in_rand_ext_i ? rand_i[x * WSheetHalf +: WSheetHalf] : + out_prd[rot_int(x, 5)]; + end else begin : gen_no_in_prd_mux + // Always use the externally provided randomness. + assign in_prd[x] = rand_i[x * WSheetHalf +: WSheetHalf]; + // Tie off unused signals. + logic unused_out_prd; + assign unused_out_prd = ^{dom_in_rand_ext_i, out_prd[rot_int(x, 5)]}; + end + + caliptra_prim_dom_and_2share #( + .DW (WSheetHalf), // a half sheet + .Pipeline(1) // Process the full sheet in 3 clock cycles. This reduces + // SCA leakage. + ) u_dom ( + .clk_i, + .rst_ni, + + .a0_i (a0), + .a1_i (a1), + .b0_i (b0), + .b1_i (b1), + .z_valid_i (dom_update_i), + .z_i (in_prd[x]), + .q0_o (q0), + .q1_o (q1), + .prd_o (out_prd[x]) + ); + + // Output conversion from q0, q1 to sheet_t + // For simplicity, we forward the generated lane half to both the upper + // and lower lane halves at this point. The actual output muxing/selection + // happens after the Iota step when generating phase2_out from iota_data + // and state_in below. + assign sheet2[0][4] = {2{q0[W/2*0+:W/2]}}; + assign sheet2[0][3] = {2{q0[W/2*1+:W/2]}}; + assign sheet2[0][2] = {2{q0[W/2*2+:W/2]}}; + assign sheet2[0][1] = {2{q0[W/2*3+:W/2]}}; + assign sheet2[0][0] = {2{q0[W/2*4+:W/2]}}; + + assign sheet2[1][4] = {2{q1[W/2*0+:W/2]}}; + assign sheet2[1][3] = {2{q1[W/2*1+:W/2]}}; + assign sheet2[1][2] = {2{q1[W/2*2+:W/2]}}; + assign sheet2[1][1] = {2{q1[W/2*3+:W/2]}}; + assign sheet2[1][0] = {2{q1[W/2*4+:W/2]}}; + + // Final XOR to generate the output + assign chi_data[0][x] = sheet2[0] ^ phase2_in[0][x]; + assign chi_data[1][x] = sheet2[1] ^ phase2_in[1][x]; + end : g_chi_w + + // Since Chi and thus Iota are separately applied to the lower and upper half + // lanes, we need to forward the input to the other half. + for (genvar x = 0 ; x < 5 ; x++) begin : g_2share_phase2_out_row + for (genvar y = 0 ; y < 5 ; y++) begin : g_2share_phase2_out_col + assign phase2_out[0][x][y] = dom_out_low_i ? + { state_in[0][x][y][W-1:W/2], iota_data[0][x][y][W/2-1:0]} : + {iota_data[0][x][y][W-1:W/2], state_in[0][x][y][W/2-1:0]}; + assign phase2_out[1][x][y] = dom_out_low_i ? + { state_in[1][x][y][W-1:W/2], iota_data[1][x][y][W/2-1:0]} : + {iota_data[1][x][y][W-1:W/2], state_in[1][x][y][W/2-1:0]}; + end + end + + end else begin : g_single_chi + assign chi_data[0] = chi(phase2_in[0]); + assign phase2_out = iota_data; + end + + // Rho ====================================================================== + // As RhoOffset[x][y] is considered as variable int in VCS, + // it is replaced with generate statement. + // Revised to meet verilator lint. Now RhoOffset is 1-D array + localparam int RhoOffset [25] = '{ + //y 0 1 2 3 4 x + 0, 36, 3, 105, 210, // 0: 0 1 2 3 4 + 1, 300, 10, 45, 66, // 1: 5 6 7 8 9 + 190, 6, 171, 15, 253, // 2: 10 11 12 13 14 + 28, 55, 153, 21, 120, // 3: 15 16 17 18 19 + 91, 276, 231, 136, 78 // 4: 20 21 22 23 24 + }; + for (genvar i = 0 ; i < Share ; i++) begin : g_rho + box_t rho_in, rho_out; + assign rho_in = theta_data[i]; + assign rho_data[i] = rho_out; + + for (genvar x = 0 ; x < 5 ; x++) begin : gen_rho_x + for (genvar y = 0 ; y < 5 ; y++) begin : gen_rho_y + localparam int Offset = RhoOffset[5*x+y]%W; + localparam int ShiftAmt = W- Offset; + if (Offset == 0) begin : gen_offset0 + assign rho_out[x][y][W-1:0] = rho_in[x][y][W-1:0]; + end else begin : gen_others + assign rho_out[x][y][W-1:0] = {rho_in[x][y][0+:ShiftAmt], + rho_in[x][y][ShiftAmt+:Offset]}; + end + end + end + end : g_rho + + //////////////// + // Assertions // + //////////////// + + `CALIPTRA_ASSERT_INIT(ValidWidth_A, + EnMasking == 0 && Width inside {25, 50, 100, 200, 400, 800, 1600} || + EnMasking == 1 && Width inside {50, 100, 200, 400, 800, 1600}) + `CALIPTRA_ASSERT_INIT(ValidW_A, W inside {1, 2, 4, 8, 16, 32, 64}) + `CALIPTRA_ASSERT_INIT(ValidL_A, L inside {0, 1, 2, 3, 4, 5, 6}) + `CALIPTRA_ASSERT_INIT(ValidRound_A, MaxRound <= 24) // Keccak-f only + + // phase_sel_i shall stay for two cycle after change to 1. + caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_t unused_caliptra_ss_lc_sig; + assign unused_caliptra_ss_lc_sig = caliptra_ss_lc_escalate_en_i; + if (EnMasking) begin : gen_selperiod_chk + `CALIPTRA_ASSUME(SelStayTwoCycleIfTrue_A, + ($past(phase_sel_i) == MuBi4False) && (phase_sel_i == MuBi4True) + |=> phase_sel_i == MuBi4True, clk_i, !rst_ni || + caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_test_true_loose(caliptra_ss_lc_escalate_en_i)) + end + + /////////////// + // Functions // + /////////////// + + // Convert bitarray to 3D box + // Please take a look at FIPS PUB 202 + // https://nvlpubs.nist.gov/nistpubs/FIPS/NIST.FIPS.202.pdf + // > For all triples (x,y,z) such that 0<=x<5, 0<=y<5, and 0<=z A[x,y,z]=S[w(5y+x)+z] + function automatic box_t bitarray_to_box(logic [Width-1:0] s_in); + automatic box_t box; + for (int y = 0 ; y < 5 ; y++) begin + for (int x = 0 ; x < 5 ; x++) begin + for (int z = 0 ; z < W ; z++) begin + box[x][y][z] = s_in[W*(5*y+x) + z]; + end + end + end + return box; + endfunction : bitarray_to_box + + // Convert 3D cube to bitarray + function automatic logic [Width-1:0] box_to_bitarray(box_t state); + automatic logic [Width-1:0] bitarray; + for (int y = 0 ; y < 5 ; y++) begin + for (int x = 0 ; x < 5 ; x++) begin + for (int z = 0 ; z < W ; z++) begin + bitarray[W*(5*y+x)+z] = state[x][y][z]; + end + end + end + return bitarray; + endfunction : box_to_bitarray + + // Rotate integer indices + function automatic integer rot_int(integer in, integer num); + integer out; + if (in == 0) begin + out = num - 1; + end else begin + out = in - 1; + end + return out; + endfunction + + // Step Mapping ============================================================= + // theta + // XOR each bit in the state with the parity of two columns + // C[x,z] = A[x,0,z] ^ A[x,1,z] ^ A[x,2,z] ^ A[x,3,z] ^ A[x,4,z] + // D[x,z] = C[x-1,z] ^ C[x+1,z-1] + // theta = A[x,y,z] ^ D[x,z] + localparam int ThetaIndexX1 [5] = '{4, 0, 1, 2, 3}; // (x-1)%5 + localparam int ThetaIndexX2 [5] = '{1, 2, 3, 4, 0}; // (x+1)%5 + function automatic box_t theta(box_t state); + plane_t c; + plane_t d; + box_t result; + for (int x = 0 ; x < 5 ; x++) begin + c[x] = state[x][0] ^ state[x][1] ^ state[x][2] ^ state[x][3] ^ state[x][4]; + end + for (int x = 0 ; x < 5 ; x++) begin + for (int z = 0 ; z < W ; z++) begin + int index_z; + index_z = (z == 0) ? W-1 : z-1; // (z+1)%W + d[x][z] = c[ThetaIndexX1[x]][z] ^ c[ThetaIndexX2[x]][index_z]; + end + end + for (int x = 0 ; x < 5 ; x++) begin + for (int y = 0 ; y < 5 ; y++) begin + result[x][y] = state[x][y] ^ d[x]; + end + end + return result; + endfunction : theta + + // rho + + // Commented out entire rho function due to VCS elaboration error. + // (z-RhoOffset[x][y]%W) isn't considered as a constant in VCS. + // Even changing it to W-RhoOffset[x][y]%W and assign to ShiftAmt + // creates same error. + + // Offset : Look at Table 2 in FIPS PUB 202 + //localparam int RhoOffset [5][5] = '{ + // //y 0 1 2 3 4 x + // '{ 0, 36, 3, 105, 210},// 0 + // '{ 1, 300, 10, 45, 66},// 1 + // '{ 190, 6, 171, 15, 253},// 2 + // '{ 28, 55, 153, 21, 120},// 3 + // '{ 91, 276, 231, 136, 78} // 4 + //}; + + // rotate bits of each lane by offset + // 1. rho[0,0,z] = A[0,0,z] + // 2. Offset swap + // a. (x,y) := (1,0) + // b. for t [0..23] + // i. rho[x,y,z] = A[x,y,z-(t+1)(t+2)/2] + // ii. (x,y) = (y, (2x+3y)) + //function automatic box_t rho(box_t state); + // box_t result; + // for (int x = 0 ; x < 5 ; x++) begin + // for (int y = 0 ; y < 5 ; y++) begin + // for (int z = 0 ; z < W ; z++) begin + // automatic int index_z; + // index_z = (z-RhoOffset[x][y])%W; + // result[x][y][z] = state[x][y][(z-RhoOffset[x][y])%W]; + // end + // end + // end + // return result; + //endfunction : rho + + // pi + // rearrange the position of lanes + // pi[x,y,z] = state[(x+3y),x,z] + localparam int PiRotate [5][5] = '{ + //y 0 1 2 3 4 x + '{ 0, 3, 1, 4, 2},// 0 + '{ 1, 4, 2, 0, 3},// 1 + '{ 2, 0, 3, 1, 4},// 2 + '{ 3, 1, 4, 2, 0},// 3 + '{ 4, 2, 0, 3, 1} // 4 + }; + function automatic box_t pi(box_t state); + box_t result; + for (int x = 0 ; x < 5 ; x++) begin + for (int y = 0 ; y < 5 ; y++) begin + result[x][y][W-1:0] = state[PiRotate[x][y]][x][W-1:0]; + end + end + return result; + endfunction : pi + + // chi + // chi[x,y,z] = state[x,y,z] ^ ((state[x+1,y,z] ^ 1) & state[x+2,y,z]) + localparam int ChiIndexX1 [5] = '{1, 2, 3, 4, 0}; // (x+1)%5 + localparam int ChiIndexX2 [5] = '{2, 3, 4, 0, 1}; // (x+2)%5 + function automatic box_t chi(box_t state); + box_t result; + for (int x = 0 ; x < 5 ; x++) begin + result[x] = state[x] ^ ((~state[ChiIndexX1[x]]) & state[ChiIndexX2[x]]); + end + return result; + endfunction : chi + + // iota + // XOR (x,y) = (0,0) with Round Constant (RC) + + // RC parameter: Precomputed by util/keccak_rc.py. Only up-to 0..L-1 is used + // RC = '0 + // RC[2**j-1] = rc(j+7*rnd) + // rc(t) = + // 1. t%255 == 0 -> 1 + // 2. R[0:7] = 'b10000000 + // 3. for i = [1..t%255] + // a. R = 0 || R + // b. R[0] = R[0] ^ R[8] + // c. R[4] = R[4] ^ R[8] + // d. R[5] = R[5] ^ R[8] + // e. R[6] = R[6] ^ R[8] + // f. R = R[0:7] + // 4. return R[0] + // RC has L = [0..6] + // for lower L case, only chopping lower part of 64bit RC is sufficient. + localparam logic [63:0] RC [24] = '{ + 64'h 0000_0000_0000_0001, // Round 0 + 64'h 0000_0000_0000_8082, // Round 1 + 64'h 8000_0000_0000_808A, // Round 2 + 64'h 8000_0000_8000_8000, // Round 3 + 64'h 0000_0000_0000_808B, // Round 4 + 64'h 0000_0000_8000_0001, // Round 5 + 64'h 8000_0000_8000_8081, // Round 6 + 64'h 8000_0000_0000_8009, // Round 7 + 64'h 0000_0000_0000_008A, // Round 8 + 64'h 0000_0000_0000_0088, // Round 9 + 64'h 0000_0000_8000_8009, // Round 10 + 64'h 0000_0000_8000_000A, // Round 11 + 64'h 0000_0000_8000_808B, // Round 12 + 64'h 8000_0000_0000_008B, // Round 13 + 64'h 8000_0000_0000_8089, // Round 14 + 64'h 8000_0000_0000_8003, // Round 15 + 64'h 8000_0000_0000_8002, // Round 16 + 64'h 8000_0000_0000_0080, // Round 17 + 64'h 0000_0000_0000_800A, // Round 18 + 64'h 8000_0000_8000_000A, // Round 19 + 64'h 8000_0000_8000_8081, // Round 20 + 64'h 8000_0000_0000_8080, // Round 21 + 64'h 0000_0000_8000_0001, // Round 22 + 64'h 8000_0000_8000_8008 // Round 23 + }; + + // iota: XOR with RC for (x,y) = (0,0) + function automatic box_t iota(box_t state, logic [RndW-1:0] rnd); + box_t result; + result = state; + result[0][0][W-1:0] = state[0][0][W-1:0] ^ RC[rnd][W-1:0]; + + return result; + endfunction : iota + + // Round function : Rnd(A,i_r) + // Not used due to rho function issue described above. + + //function automatic box_t keccak_rnd(box_t state, logic [RndW-1:0] rnd); + // box_t keccak_state; + // keccak_state = iota(chi(pi(rho(theta(state)))), rnd); + // + // return keccak_state; + //endfunction : keccak_rnd + +endmodule diff --git a/src/caliptra_ss_lc_ctrl/rtl/keccak_round.sv b/src/caliptra_ss_lc_ctrl/rtl/keccak_round.sv new file mode 100644 index 0000000..62828b5 --- /dev/null +++ b/src/caliptra_ss_lc_ctrl/rtl/keccak_round.sv @@ -0,0 +1,611 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Keccak full round logic based on given input `Width` +// e.g. Width 800 requires 22 rounds +// +// This module has two phases: +// 1. Compute Theta, Rho, Pi steps. +// 2. Computes Chi and Iota steps. +// +// If masking is not enabled, the two phases are completed within a single +// clock cycle. +// +// If masking is enabled, the first phase (Phase1) completes in one cycle. +// The second phase then needs three clock cycles to complete: +// 1. In the first clock cycle, the first stage of Chi is computed for the +// first lane halves. +// 2. In the second clock cycle, the module writes the updated first lane +// halves to the state. +// 3. In the third clock cycle, the new second lane halves are written to +// to the state. +// +// To deter SCA, we randomly decide which lane halves to process first on a +// per-round basis. We use additional randomness generated by the PRNG to take +// this decision (rand_aux_i). For more details, refer to the comments inside +// the FSM below. +// +// If masking is enabled, this implementation uses both randomness provided +// from an external PRNG as well as intermediate results for remasking the DOM +// multipliers below. Per clock cycle, 800b of pseudo-random data (PRD) are +// required. A carfully designed schedule ensures to only ever update the input +// data of the DOM multipliers when also providing fresh randomness and vice +// versa. Updating one without the other could lead to undesired SCA leakage. + +`include "caliptra_prim_assert.sv" + +module keccak_round + import caliptra_prim_mubi_pkg::*; +#( + parameter int Width = 1600, // b= {25, 50, 100, 200, 400, 800, 1600} + + // Derived + localparam int W = Width/25, + localparam int L = $clog2(W), + localparam int MaxRound = 12 + 2*L, // Keccak-f only + localparam int RndW = $clog2(MaxRound+1), // Representing up to MaxRound-1 + + // Feed parameters + parameter int DInWidth = 64, // currently only 64bit supported + localparam int DInEntry = Width / DInWidth, + localparam int DInAddr = $clog2(DInEntry), + + // Control parameters + parameter bit EnMasking = 1'b0, // Enable SCA hardening, requires Width >= 50 + parameter bit ForceRandExt = 1'b0, // 1: Always forward externally provided randomness. + // 0: Switch between external randomness and internal + // intermediate state according to schedule. + localparam int Share = EnMasking ? 2 : 1 +) ( + input clk_i, + input rst_ni, + + // Message Feed + input valid_i, + input [DInAddr-1:0] addr_i, + input [DInWidth-1:0] data_i [Share], + output ready_o, + + // In-process control + input run_i, // Pulse signal to initiates Keccak full round + input rand_valid_i, + input rand_early_i, + input [Width/2-1:0] rand_data_i, + input rand_aux_i, + output logic rand_update_o, + output logic rand_consumed_o, + + output logic complete_o, // Indicates full round is done + + // State out. This can be used as Digest + output logic [Width-1:0] state_o [Share], + + // Life cycle + input caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_t caliptra_ss_lc_escalate_en_i, + + // Errors: + // sparse_fsm_error: Checking if FSM state falls into unknown value + output logic sparse_fsm_error_o, + // round_count_error: caliptra_prim_count checks round value consistency + output logic round_count_error_o, + // rst_storage_error: check if reset signal asserted out of the + // permitted window + output logic rst_storage_error_o, + + input caliptra_prim_mubi_pkg::mubi4_t clear_i // Clear internal state to '0 +); + + import sha3_pkg::*; + + ///////////////////// + // Control signals // + ///////////////////// + + // Update storage register + logic update_storage; + + // Reset the storage to 0 to initiate new Hash operation + logic rst_storage; + + // XOR message into storage register + // It only does based on the given DInWidth. + // If DInWidth < Width, it takes multiple cycles to XOR all message + logic xor_message; + + // Select Keccak_p datapath + // 0: Select Phase1 (Theta -> Rho -> Pi) + // 1: Select Phase2 (Chi -> Iota) + // `phase_sel` needs to be asserted until the Chi stage is consumed, + mubi4_t phase_sel; + + // DOM multiplier input/output mux control + // 0: first compute upper, then lower lane halves + // 1: first compute lower, then upper lane halves + logic low_then_high_d, low_then_high_q; + // 0: drive/select upper lane halves + // 1: drive/select lower lane halves + logic dom_out_low_d, dom_out_low_q; + logic dom_in_low_d, dom_in_low_q; + // 0: forward external randomness input + // 1: forward partial intermediate results + logic dom_in_rand_ext_d, dom_in_rand_ext_q; + // 0: keep current intermediate results in pipeline registers + // 1: latch new intermediate results into pipeline registers + logic dom_update; + + // Increase/ Reset Round number + logic inc_rnd_num; + logic rst_rnd_num; + + // Round reaches end + // This signal indicates the round reaches desired number, which is MaxRound -1. + // MaxRound is dependant on the Width. In case of SHA3/SHAKE, MaxRound is 24. + logic rnd_eq_end; + + // Complete of Keccak_f + // State machine asserts `complete_d` when it reaches at the end of round and + // operation (Phase3 if Masked). The stage, the storage still doesn't have + // the valid states. So precisely it is not completed yet. + // State generated `complete_d` is latched with the clock and creates a pulse + // signal one cycle later. The signal is the indication of completion. + // + // Intentionally removed any intermediate step (so called StComplete) in order + // to save a clock to proceeds next round. + logic complete_d; + + ////////////////////// + // Datapath Signals // + ////////////////////// + + // Single round keccak output data + logic [Width-1:0] keccak_out [Share]; + + // Keccak Round indicator: range from 0 .. MaxRound + logic [RndW-1:0] round; + + // Random value and valid signal used in Keccak_p + logic keccak_rand_update; + logic keccak_rand_consumed; + logic [Width/2-1:0] keccak_rand_data; + + ////////////////////// + // Keccak Round FSM // + ////////////////////// + + // state inputs + assign rnd_eq_end = (int'(round) == MaxRound - 1); + + keccak_st_e keccak_st, keccak_st_d; + `CALIPTRA_PRIM_FLOP_SPARSE_FSM(u_state_regs, keccak_st_d, keccak_st, keccak_st_e, KeccakStIdle) + + // Next state logic and output logic + // SEC_CM: FSM.SPARSE + always_comb begin + // Default values + keccak_st_d = keccak_st; + + xor_message = 1'b 0; + update_storage = 1'b 0; + rst_storage = 1'b 0; + + inc_rnd_num = 1'b 0; + rst_rnd_num = 1'b 0; + + keccak_rand_update = 1'b 0; + keccak_rand_consumed = 1'b 0; + + phase_sel = MuBi4False; + low_then_high_d = low_then_high_q; + dom_in_low_d = dom_in_low_q; + dom_in_rand_ext_d = dom_in_rand_ext_q; + dom_update = 1'b 0; + + complete_d = 1'b 0; + + sparse_fsm_error_o = 1'b 0; + + unique case (keccak_st) + KeccakStIdle: begin + if (valid_i) begin + // State machine allows Sponge Absorbing only in Idle state. + keccak_st_d = KeccakStIdle; + + xor_message = 1'b 1; + update_storage = 1'b 1; + end else if (caliptra_prim_mubi_pkg::mubi4_test_true_strict(clear_i)) begin + // Opt1. State machine allows resetting the storage only in Idle + // Opt2. storage resets regardless of states but clear_i + // Both are added in the design at this time. Will choose the + // direction later. + keccak_st_d = KeccakStIdle; + + rst_storage = 1'b 1; + end else if (EnMasking && run_i) begin + // Masked version of Keccak handling + keccak_st_d = KeccakStPhase1; + + // Drive DOM multiplier I/O mux signals for Phase 1. + dom_in_low_d = low_then_high_q; + dom_in_rand_ext_d = 1'b 0; + end else if (!EnMasking && run_i) begin + // Unmasked version of Keccak handling + keccak_st_d = KeccakStActive; + end else begin + keccak_st_d = KeccakStIdle; + end + end + + KeccakStActive: begin + // Run Keccak single round logic until it reaches MaxRound - 1 + update_storage = 1'b 1; + + if (rnd_eq_end) begin + keccak_st_d = KeccakStIdle; + + rst_rnd_num = 1'b 1; + complete_d = 1'b 1; + end else begin + keccak_st_d = KeccakStActive; + + inc_rnd_num = 1'b 1; + end + end + + KeccakStPhase1: begin + // Compute Theta, Rho, Pi - The DOM multipliers are not evaluated at + // all: their inputs are driven by the first lane halves (same values + // as in Phase2Cycle3 of the last round). Also, the intermediate + // results we already had in Phase2Cycle3 didn't change. + phase_sel = MuBi4False; + dom_update = 1'b 0; + + // Only update the state and move on once we know the auxiliary + // randomness required for Phase2 will be available in the next clock + // cycle. + // + // It's important that the DOM multipliers inside keccak_2share are + // presented the new state (updated with update_storage) at the same + // time as the new randomness (updated with rand_update_o). Otherwise, + // stale entropy is paired with fresh data or vice versa. This could + // lead to undesired SCA leakage. + if (rand_early_i || rand_valid_i) begin + keccak_st_d = KeccakStPhase2Cycle1; + update_storage = 1'b 1; + keccak_rand_update = 1'b 1; + + // Update lane halves processing order for this round. + low_then_high_d = rand_aux_i; + + // Drive DOM multiplier I/O mux signals for next phase. + dom_in_low_d = low_then_high_d; + dom_in_rand_ext_d = 1'b 1; + end else begin + keccak_st_d = KeccakStPhase1; + end + end + + KeccakStPhase2Cycle1: begin + // Compute first stage of Chi for first lane halves using the DOM + // multipliers. Use the fresh randomness provided by the PRNG for + // remasking. + phase_sel = MuBi4True; + dom_update = 1'b 1; + + // Trigger randomness update for next cycle. + // It's important that the DOM multipliers inside keccak_2share are + // presented the second lane halves at the same time as the new + // randomness (updated with rand_update_o). Otherwise, stale entropy + // is paired with fresh data or vice versa. This could lead to + // undesired SCA leakage. + keccak_rand_update = 1'b 1; + + // Unconditionally move to next phase/cycle. + keccak_st_d = KeccakStPhase2Cycle2; + + // Drive DOM multiplier I/O mux signals for next phase. + dom_in_low_d = ~low_then_high_q; + dom_in_rand_ext_d = 1'b 1; + end + + KeccakStPhase2Cycle2: begin + // Chi Stage 1 for second lane halves. + // Chi Stage 2 and Iota for first lane halves. + // Compute second stage of Chi and Iota for first lane halves. + // Compute first stage of Chi for second lane halves. Use the fresh + // randomness provided by the PRNG for remasking the DOM multipliers. + phase_sel = MuBi4True; + dom_update = 1'b 1; + + // Trigger randomness update for next cycle. + // It's important that the DOM multipliers inside keccak_2share are + // presented the updated state at the same as the new randomness + // (updated with rand_update_o) - even if the DOM multipliers don't + // update the pipeline registers in the next cycle. Otherwise, stale + // entropy is paired with fresh data or vice versa. This could lead to + // undesired SCA leakage. + keccak_rand_update = 1'b 1; + + // Trigger auxiliary randomness update for next round. The rand_aux_i + // signal is actually going to change in 2 clock cycles from now + // (Phase1) based on the PRNG output in the next cycle (Phase2Cycle3) + // in which the DOM multipliers don't update the pipeline registers. + keccak_rand_consumed = 1'b 1; + + // Update first lane halves. + update_storage = 1'b 1; + + // Unconditionally move to next phase/cycle. + keccak_st_d = KeccakStPhase2Cycle3; + + // Drive DOM multiplier I/O mux signals for next phase. + dom_in_low_d = low_then_high_q; + dom_in_rand_ext_d = 1'b 0; + end + + KeccakStPhase2Cycle3: begin + // Compute second stage of Chi and Iota for second lane halves. + // Feed again first lane halves to DOM multiplier inputs (now + // the updated values become visible) together with intermediate + // results of Phase2Cycle2. Don't update the register stage inside + // the DOM multipliers. + phase_sel = MuBi4True; + dom_update = 1'b 0; + + // Update second lane halves. + // We don't need fresh randomness for the next cycle as the DOM + // multipliers inside keccak_2share will keep seeing the first + // lane halves in the next cycle. If we updated the randomness, + // old data got combined with frash randomness which is not + // desirable as it could lead to SCA leakage. + update_storage = 1'b 1; + + if (rnd_eq_end) begin + // We're done. + keccak_st_d = KeccakStIdle; + + rst_rnd_num = 1'b 1; + complete_d = 1'b 1; + end else begin + // Continue to the next round. + keccak_st_d = KeccakStPhase1; + + inc_rnd_num = 1'b 1; + + // Drive DOM multiplier I/O mux signals for next phase. + dom_in_low_d = low_then_high_q; + dom_in_rand_ext_d = 1'b 0; + end + end + + KeccakStError: begin + keccak_st_d = KeccakStError; + end + + KeccakStTerminalError: begin + //this state is terminal + keccak_st_d = keccak_st; + sparse_fsm_error_o = 1'b 1; + end + + default: begin + keccak_st_d = KeccakStTerminalError; + sparse_fsm_error_o = 1'b 1; + end + endcase + + // SEC_CM: FSM.GLOBAL_ESC, FSM.LOCAL_ESC + // Unconditionally jump into the terminal error state + // if the life cycle controller triggers an escalation. + if (caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_test_true_loose(caliptra_ss_lc_escalate_en_i)) begin + keccak_st_d = KeccakStTerminalError; + end + end + + // When taking the lower lane halves in, the upper lane halves are output and + // vice versa. + assign dom_out_low_d = ~dom_in_low_d; + + if (EnMasking) begin : gen_regs_dom_ctrl + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + low_then_high_q <= 1'b 0; + dom_out_low_q <= 1'b 0; + dom_in_low_q <= 1'b 0; + end else begin + low_then_high_q <= low_then_high_d; + dom_out_low_q <= dom_out_low_d; + dom_in_low_q <= dom_in_low_d; + end + end + + if (!ForceRandExt) begin : gen_reg_dom_in_rand_ext + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + dom_in_rand_ext_q <= 1'b 0; + end else begin + dom_in_rand_ext_q <= dom_in_rand_ext_d; + end + end + end else begin : gen_force_dom_in_rand_ext + // Always forward the externally provided randomness. + assign dom_in_rand_ext_q = 1'b 1; + // Tie off unused signals. + logic unused_dom_in_rand_ext; + assign unused_dom_in_rand_ext = dom_in_rand_ext_d; + end + end else begin : gen_no_regs_dom_ctrl + logic unused_dom_ctrl; + assign unused_dom_ctrl = + ^{low_then_high_d, dom_out_low_d, dom_in_low_d, dom_in_rand_ext_d}; + assign low_then_high_q = 1'b 0; + assign dom_out_low_q = 1'b 0; + assign dom_in_low_q = 1'b 0; + assign dom_in_rand_ext_q = 1'b 0; + end + + // Ready indicates the keccak_round is able to receive new message. + // While keccak_round is processing the data, it blocks the new message to be + // XORed into the current state. + assign ready_o = (keccak_st == KeccakStIdle) ? 1'b 1 : 1'b 0; + + //////////////////////////// + // Keccak state registers // + //////////////////////////// + + // SEC_CM: LOGIC.INTEGRITY + logic rst_n; + caliptra_prim_sec_anchor_buf #( + .Width(1) + ) u_caliptra_prim_sec_anchor_buf ( + .in_i(rst_ni), + .out_o(rst_n) + ); + + logic [Width-1:0] storage [Share]; + logic [Width-1:0] storage_d [Share]; + always_ff @(posedge clk_i or negedge rst_n) begin + if (!rst_n) begin + storage <= '{default:'0}; + end else if (rst_storage) begin + storage <= '{default:'0}; + end else if (update_storage) begin + storage <= storage_d; + end + end + + assign state_o = storage; + + // Storage register input + // The incoming message is XORed with the existing storage registers. + // The logic can accept not a block size incoming message chunk but + // the size defined in `DInWidth` parameter with its position. + + always_comb begin + storage_d = keccak_out; + if (xor_message) begin + for (int j = 0 ; j < Share ; j++) begin + for (int unsigned i = 0 ; i < DInEntry ; i++) begin + // ICEBOX(#18029): handle If Width is not integer divisable by DInWidth + // Currently it is not allowed to have partial write + // Please see the Assertion `WidthDivisableByDInWidth_A` + if (addr_i == i[DInAddr-1:0]) begin + storage_d[j][i*DInWidth+:DInWidth] = + storage[j][i*DInWidth+:DInWidth] ^ data_i[j]; + end else begin + storage_d[j][i*DInWidth+:DInWidth] = storage[j][i*DInWidth+:DInWidth]; + end + end // for i + end // for j + end // if xor_message + end + + // Check the rst_storage integrity + logic rst_storage_error; + + always_comb begin : chk_rst_storage + rst_storage_error = 1'b 0; + + if (rst_storage) begin + // FSM should be in KeccakStIdle and clear_i should be high + if ((keccak_st != KeccakStIdle) || + caliptra_prim_mubi_pkg::mubi4_test_false_loose(clear_i)) begin + rst_storage_error = 1'b 1; + end + end + end : chk_rst_storage + + assign rst_storage_error_o = rst_storage_error ; + + ////////////// + // Datapath // + ////////////// + keccak_2share #( + .Width(Width), + .EnMasking(EnMasking), + .ForceRandExt(ForceRandExt) + ) u_keccak_p ( + .clk_i, + .rst_ni, + + .caliptra_ss_lc_escalate_en_i, + + .rnd_i(round), + + .phase_sel_i (phase_sel), + .dom_out_low_i (dom_out_low_q), + .dom_in_low_i (dom_in_low_q), + .dom_in_rand_ext_i(dom_in_rand_ext_q), + .dom_update_i (dom_update), + + .rand_i(keccak_rand_data), + + .s_i(storage), + .s_o(keccak_out) + ); + + // keccak entropy handling + assign rand_update_o = keccak_rand_update; + assign rand_consumed_o = keccak_rand_consumed; + + assign keccak_rand_data = rand_data_i; + + // Round number + // This primitive is used to place a hardened counter + // SEC_CM: CTR.REDUN + caliptra_prim_count #( + .Width(RndW) + ) u_round_count ( + .clk_i, + .rst_ni, + .clr_i(rst_rnd_num), + .set_i(1'b0), + .set_cnt_i('0), + .incr_en_i(inc_rnd_num), + .decr_en_i(1'b0), + .step_i(RndW'(1)), + .commit_i(1'b1), + .cnt_o(round), + .cnt_after_commit_o(), + .err_o(round_count_error_o) + ); + + // completion signal + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + complete_o <= 1'b 0; + end else begin + complete_o <= complete_d; + end + end + + //////////////// + // Assertions // + //////////////// + + // Only allow `DInWidth` that `Width` is integer divisable by `DInWidth` + `CALIPTRA_ASSERT_INIT(WidthDivisableByDInWidth_A, (Width % DInWidth) == 0) + + // If `run_i` triggerred, it shall complete + //`CALIPTRA_ASSERT(RunResultComplete_A, run_i ##[MaxRound:] complete_o, clk_i, !rst_ni) + + // valid_i and run_i cannot be asserted at the same time + `CALIPTRA_ASSUME(OneHot0ValidAndRun_A, $onehot0({valid_i, run_i}), clk_i, !rst_ni) + + // valid_i, run_i only asserted in Idle state + `CALIPTRA_ASSUME(ValidRunAssertStIdle_A, valid_i || run_i |-> keccak_st == KeccakStIdle, clk_i, !rst_ni) + + // clear_i is assumed to be asserted in Idle state + `CALIPTRA_ASSUME(ClearAssertStIdle_A, + caliptra_prim_mubi_pkg::mubi4_test_true_strict(clear_i) + |-> keccak_st == KeccakStIdle, clk_i, !rst_ni) + + // EnMasking controls the valid states + if (EnMasking) begin : gen_mask_st_chk + `CALIPTRA_ASSERT(EnMaskingValidStates_A, keccak_st != KeccakStActive, clk_i, !rst_ni) + end else begin : gen_unmask_st_chk + `CALIPTRA_ASSERT(UnmaskValidStates_A, !(keccak_st + inside {KeccakStPhase1, KeccakStPhase2Cycle1, KeccakStPhase2Cycle2, KeccakStPhase2Cycle3}), + clk_i, !rst_ni) + end +endmodule diff --git a/src/caliptra_ss_lc_ctrl/rtl/kmac.sv b/src/caliptra_ss_lc_ctrl/rtl/kmac.sv new file mode 100644 index 0000000..7681022 --- /dev/null +++ b/src/caliptra_ss_lc_ctrl/rtl/kmac.sv @@ -0,0 +1,1589 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// KMAC/SHA3 + +`include "caliptra_prim_assert.sv" + +module kmac + import kmac_pkg::*; + import kmac_reg_pkg::*; +#( + // EnMasking: Enable masking security hardening inside keccak_round + // If it is enabled, the result digest will be two set of 1600bit. + parameter bit EnMasking = 1, + + // In case EnMasking == 0, this defines whether SW can provide a masked key or whether Share 1 of + // the SW key is simply ignored. In case EnMasking == 1, this parameter has no meaning, always + // both shares of the key provided by SW are used. + // This is useful to allow both for area-optimized unmasked designs as well as unmasked designs + // having a SW interface fully compatible with the masked design. + parameter bit SwKeyMasked = 0, + + // Command delay, useful for SCA measurements only. A value of e.g. 40 allows the processor to go + // into sleep before KMAC starts operation. If a value > 0 is chosen, the processor can provide + // two commands subsquently and then go to sleep. The second command is buffered internally and + // will be presented to the hardware SecCmdDelay number of cycles after the first one. + parameter int SecCmdDelay = 0, + + // Accept SW message when idle and before receiving a START command. Useful for SCA only. + parameter bit SecIdleAcceptSwMsg = 1'b0, + parameter int unsigned NumAppIntf = 3, + parameter app_config_t AppCfg[NumAppIntf] = '{AppCfgKeyMgr, AppCfgLcCtrl, AppCfgRomCtrl}, + + parameter lfsr_perm_t RndCnstLfsrPerm = RndCnstLfsrPermDefault, + parameter lfsr_seed_t RndCnstLfsrSeed = RndCnstLfsrSeedDefault, + parameter buffer_lfsr_seed_t RndCnstBufferLfsrSeed = RndCnstBufferLfsrSeedDefault, + parameter msg_perm_t RndCnstMsgPerm = RndCnstMsgPermDefault, + + parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}} +) ( + input clk_i, + input rst_ni, + + input rst_shadowed_ni, + + input clk_edn_i, + input rst_edn_ni, + + input tlul_pkg::tl_h2d_t tl_i, + output tlul_pkg::tl_d2h_t tl_o, + + // Alerts + input caliptra_prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i, + output caliptra_prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o, + + // KeyMgr sideload (secret key) interface + input caliptra_ss_lc_ctrl_keymgr_pkg::hw_key_req_t keymgr_key_i, + + // KeyMgr KDF data path + input app_req_t [NumAppIntf-1:0] app_i, + output app_rsp_t [NumAppIntf-1:0] app_o, + + // EDN interface + output edn_pkg::edn_req_t entropy_o, + input edn_pkg::edn_rsp_t entropy_i, + + // Life cycle + input caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_t caliptra_ss_lc_escalate_en_i, + + // interrupts + output logic intr_kmac_done_o, + output logic intr_fifo_empty_o, + output logic intr_kmac_err_o, + + // parameter consistency check with keymgr + output logic en_masking_o, + + // Idle signal + output caliptra_prim_mubi_pkg::mubi4_t idle_o +); + + //////////////// + // Parameters // + //////////////// + localparam int Share = (EnMasking) ? 2 : 1 ; + localparam int SwKeyShare = (EnMasking || SwKeyMasked) ? 2 : 1; + + ///////////////// + // Definitions // + ///////////////// + // This state machine is to track the current process based on SW input and + // KMAC operation. + // Encoding generated with: + // $ ./util/design/sparse-fsm-encode.py -d 3 -m 6 -n 6 \ + // -s 1966361510 --language=sv + // + // Hamming distance histogram: + // + // 0: -- + // 1: -- + // 2: -- + // 3: |||||||||||||||||||| (53.33%) + // 4: ||||||||||||||| (40.00%) + // 5: || (6.67%) + // 6: -- + // + // Minimum Hamming distance: 3 + // Maximum Hamming distance: 5 + // Minimum Hamming weight: 2 + // Maximum Hamming weight: 5 + // + localparam int StateWidth = 6; + typedef enum logic [StateWidth-1:0] { + // Idle state + KmacIdle = 6'b001011, + + // When software writes CmdStart @ KmacIdle and kmac_en, FSM moves to this + KmacPrefix = 6'b000110, + + // When SHA3 engine processes Key block, FSM moves to here. + KmacKeyBlock = 6'b111110, + + // Message Feed + KmacMsgFeed = 6'b010101, + + // Complete and squeeze + KmacDigest = 6'b101101, + + // Error + KmacTerminalError = 6'b110000 + + } kmac_st_e; + + kmac_st_e kmac_st, kmac_st_d; + + ///////////// + // Signals // + ///////////// + kmac_reg2hw_t reg2hw; + kmac_hw2reg_t hw2reg; + + // Window + typedef enum int { + WinState = 0, + WinMsgFifo = 1 + } tl_window_e; + + tlul_pkg::tl_h2d_t tl_win_h2d[2]; + tlul_pkg::tl_d2h_t tl_win_d2h[2]; + + // SHA3 core control signals and its response. + // Sequence: start --> process(multiple) --> get absorbed event --> {run -->} done + logic sha3_start, sha3_run, unused_sha3_squeeze; + caliptra_prim_mubi_pkg::mubi4_t sha3_done; + caliptra_prim_mubi_pkg::mubi4_t sha3_done_d; + caliptra_prim_mubi_pkg::mubi4_t sha3_absorbed; + + // Indicate one block processed + logic sha3_block_processed; + + // EStatus for entropy + logic entropy_in_keyblock; + + // Application interface logic generates absorbed from sha3_absorbed. + // It is active only if SW initiates the hashing engine. + caliptra_prim_mubi_pkg::mubi4_t app_absorbed; + logic event_absorbed; + + sha3_pkg::sha3_st_e sha3_fsm; + + // Prefix: kmac_pkg defines Prefix based on N size and S size. + // Then computes left_encode(len(N)) size and left_encode(len(S)) + // For given default value 32, 256 bits, the max + // encode_string(N) || encode_string(S) is 328. So 11 Prefix registers are + // created. + logic [sha3_pkg::NSRegisterSize*8-1:0] reg_ns_prefix; + logic [sha3_pkg::NSRegisterSize*8-1:0] ns_prefix; + + // NumWordsPrefix from kmac_reg_pkg + `CALIPTRA_ASSERT_INIT(PrefixRegSameToPrefixPkg_A, + kmac_reg_pkg::NumWordsPrefix*4 == sha3_pkg::NSRegisterSize) + + // NumEntriesMsgFifo from kmac_reg_pkg must match calculated MsgFifoDepth + // from kmac_pkg. + `CALIPTRA_ASSERT_INIT(NumEntriesRegSameToNumEntriesPkg_A, + kmac_reg_pkg::NumEntriesMsgFifo == kmac_pkg::MsgFifoDepth) + + // NumBytesMsgFifoEntry from kmac_reg_pkg must match the MsgWidth calculated + // in kmac_pkg (although MsgWidth is in bits, so we multiply by 8). + `CALIPTRA_ASSERT_INIT(EntrySizeRegSameToEntrySizePkg_A, + kmac_reg_pkg::NumBytesMsgFifoEntry * 8 == kmac_pkg::MsgWidth) + + // Output state: this is used to redirect the digest to KeyMgr or Software + // depends on the configuration. + logic state_valid; + logic [sha3_pkg::StateW-1:0] state [Share]; + + // state is de-muxed in keymgr interface logic. + // the output from keymgr logic goes into staterd module to be visible to SW + logic reg_state_valid; + logic [sha3_pkg::StateW-1:0] reg_state [Share]; + + // SHA3 Entropy interface + logic sha3_rand_valid, sha3_rand_early, sha3_rand_update, sha3_rand_consumed; + logic [sha3_pkg::StateW/2-1:0] sha3_rand_data; + logic sha3_rand_aux; + + // FIFO related signals + logic msgfifo_empty, msgfifo_full; + logic [kmac_pkg::MsgFifoDepthW-1:0] msgfifo_depth; + + logic msgfifo_valid ; + logic [kmac_pkg::MsgWidth-1:0] msgfifo_data [Share]; + logic [kmac_pkg::MsgStrbW-1:0] msgfifo_strb ; + logic msgfifo_ready ; + + if (EnMasking) begin : gen_msgfifo_data_masked + // In Masked mode, the input message data is split into two shares. + // Only concern, however, here is the secret key. So message can be + // put into only one share and other is 0. + assign msgfifo_data[1] = '0; + end + + // TL-UL Adapter(MSG_FIFO) signals + logic tlram_req; + logic tlram_gnt; + logic tlram_we; + logic [8:0] tlram_addr; // NOT_READ + logic [31:0] tlram_wdata; + logic [31:0] tlram_wmask; + logic [31:0] tlram_rdata; + logic tlram_rvalid; + logic [1:0] tlram_rerror; + logic [31:0] tlram_wdata_endian; + logic [31:0] tlram_wmask_endian; + + logic sw_msg_valid; + logic [kmac_pkg::MsgWidth-1:0] sw_msg_data ; + logic [kmac_pkg::MsgWidth-1:0] sw_msg_mask ; + logic sw_msg_ready; + + // KeyMgr interface to MSG_FIFO + logic mux2fifo_valid; + logic [kmac_pkg::MsgWidth-1:0] mux2fifo_data ; + logic [kmac_pkg::MsgWidth-1:0] mux2fifo_mask ; + logic mux2fifo_ready; + + // KMAC to SHA3 core + logic msg_valid ; + logic [kmac_pkg::MsgWidth-1:0] msg_data [Share]; + logic [kmac_pkg::MsgWidth-1:0] msg_data_masked [Share]; + logic [kmac_pkg::MsgStrbW-1:0] msg_strb ; + logic msg_ready ; + + // Process control signals + // Process pulse propagates from register to SHA3 engine one by one. + // Each module (MSG_FIFO, KMAC core, SHA3 core) generates the process pulse + // after flushing internal data to the next module. + logic reg2msgfifo_process, msgfifo2kmac_process, kmac2sha3_process; + + + // Secret Key signals + logic [MaxKeyLen-1:0] sw_key_data_reg [SwKeyShare]; + logic [MaxKeyLen-1:0] sw_key_data [Share]; + key_len_e sw_key_len; + logic [MaxKeyLen-1:0] key_data [Share]; + logic key_valid; + key_len_e key_len; + + // SHA3 Mode, Strength, KMAC enable for app interface + logic reg_kmac_en, app_kmac_en; + sha3_pkg::sha3_mode_e reg_sha3_mode, app_sha3_mode; + sha3_pkg::keccak_strength_e reg_keccak_strength, app_keccak_strength; + + // RegIF of enabling unsupported mode & strength + logic cfg_en_unsupported_modestrength; + + // Indicating AppIntf is active. This signal is used to check SW error + logic app_active; + + // SEC_CM: SW_CMD.CTRL.SPARSE + // Command + // sw_cmd is the command written by SW + // checked_sw_cmd is checked in the kmac_errchk module. + // Invalid command is filtered out in the module. + // kmac_cmd is generated in KeyMgr interface. + // If SW initiates the KMAC/SHA3, kmac_cmd represents SW command, + // if KeyMgr drives the data, kmac_cmd is controled in the state machine + // in KeyMgr interface logic. + kmac_cmd_e sw_cmd, checked_sw_cmd, kmac_cmd, cmd_q; + logic cmd_update; + + // Entropy configurations + logic [9:0] wait_timer_prescaler; + logic [15:0] wait_timer_limit; + logic entropy_refresh_req; + logic entropy_seed_update; + logic [31:0] entropy_seed_data; + + logic [HashCntW-1:0] entropy_hash_threshold; + logic [HashCntW-1:0] entropy_hash_cnt; + logic entropy_hash_clr; + + logic entropy_ready; + entropy_mode_e entropy_mode; + logic entropy_fast_process; + + caliptra_prim_mubi_pkg::mubi4_t entropy_configured; + + // Message Masking + logic msg_mask_en, cfg_msg_mask; + logic [MsgWidth-1:0] msg_mask; + + // SHA3 Error response + sha3_pkg::err_t sha3_err; + + // KeyMgr Error response + kmac_pkg::err_t app_err; + + // Entropy Generator Error + kmac_pkg::err_t entropy_err; + + // Error checker + kmac_pkg::err_t errchecker_err; + + // MsgFIFO Error + kmac_pkg::err_t msgfifo_err; + + logic err_processed; + + caliptra_prim_mubi_pkg::mubi4_t clear_after_error; + + logic alert_fatal, alert_recov_operation; + logic alert_intg_err; + + // Life cycle + localparam int unsigned NumLcSyncCopies = 6; + caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_t [NumLcSyncCopies-1:0] caliptra_ss_lc_escalate_en_sync; + caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_t [NumLcSyncCopies-1:0] caliptra_ss_lc_escalate_en; + + ////////////////////////////////////// + // Connecting Register IF to logics // + ////////////////////////////////////// + + // Function-name N and Customization input string S + always_comb begin + for (int i = 0 ; i < NumWordsPrefix; i++) begin + reg_ns_prefix[32*i+:32] = reg2hw.prefix[i].q; + end + end + + // Create a lint error to reduce the risk of accidentally enabling this feature. + `CALIPTRA_ASSERT_STATIC_LINT_ERROR(KmacSecCmdDelayNonDefault, SecCmdDelay == 0) + + if (SecCmdDelay > 0) begin : gen_cmd_delay_buf + // Delay and buffer commands for SCA measurements. + localparam int unsigned WidthCounter = $clog2(SecCmdDelay+1); + logic [WidthCounter-1:0] count_d, count_q; + logic counting_d, counting_q; + logic cmd_buf_empty; + kmac_cmd_e cmd_buf_q; + + assign cmd_buf_empty = (cmd_buf_q == CmdNone); + + // When seeing a write to the cmd register, we start counting. We stop counting once the + // counter has expired and the command buffer is empty. + assign counting_d = reg2hw.cmd.cmd.qe ? 1'b1 : + cmd_update & cmd_buf_empty ? 1'b0 : counting_q; + + // Clear counter upon writes to the cmd register or if the specified delay is reached. + assign count_d = reg2hw.cmd.cmd.qe ? '0 : + cmd_update ? '0 : + counting_q ? count_q + 1'b1 : count_q; + + // The manual run command cannot be delayed. Software expects this to be triggered immediately + // and will poll the status register to wait for the SHA3 engine to return back to the squeeze + // state. + assign cmd_update = (cmd_q == CmdManualRun) ? 1'b1 : + (count_q == SecCmdDelay[WidthCounter-1:0]) ? 1'b1 : 1'b0; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + count_q <= '0; + counting_q <= 1'b0; + end else begin + count_q <= count_d; + counting_q <= counting_d; + end + end + + // cmd.q is valid while cmd.qe is high, meaning it needs to be registered. We buffer one + // additional command such that software can write START followed by PROCESS and then go to + // sleep. + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + cmd_q <= CmdNone; + cmd_buf_q <= CmdNone; + end else begin + if (reg2hw.cmd.cmd.qe && cmd_update) begin + // New write & counter expired. + cmd_q <= cmd_buf_q; + cmd_buf_q <= kmac_cmd_e'(reg2hw.cmd.cmd.q); + + end else if (reg2hw.cmd.cmd.qe) begin + // New write. + if (counting_q == 1'b0) begin + cmd_q <= kmac_cmd_e'(reg2hw.cmd.cmd.q); + end else begin + cmd_buf_q <= kmac_cmd_e'(reg2hw.cmd.cmd.q); + end + + end else if (cmd_update) begin + // Counter expired. + cmd_q <= cmd_buf_q; + cmd_buf_q <= CmdNone; + end + end + end + + end else begin : gen_no_cmd_delay_buf + // Directly forward signals from register IF. + assign cmd_update = reg2hw.cmd.cmd.qe; + assign cmd_q = kmac_cmd_e'(reg2hw.cmd.cmd.q); + end + + // Command signals + assign sw_cmd = (cmd_update) ? cmd_q : CmdNone; + `CALIPTRA_ASSERT_KNOWN(KmacCmd_A, sw_cmd) + always_comb begin + sha3_start = 1'b 0; + sha3_run = 1'b 0; + sha3_done_d = caliptra_prim_mubi_pkg::MuBi4False; + reg2msgfifo_process = 1'b 0; + + unique case (kmac_cmd) + CmdStart: begin + sha3_start = 1'b 1; + end + + CmdProcess: begin + reg2msgfifo_process = 1'b 1; + end + + CmdManualRun: begin + sha3_run = 1'b 1; + end + + CmdDone: begin + sha3_done_d = caliptra_prim_mubi_pkg::MuBi4True; + end + + CmdNone: begin + // inactive state + end + + default: begin + end + endcase + end + + // Status register ========================================================== + // status.squeeze is valid only when SHA3 engine completes the Absorb and not + // running the manual keccak rounds. This status is for SW to determine when + // to read the STATE values. + assign hw2reg.status.sha3_idle.d = sha3_fsm == sha3_pkg::StIdle; + assign hw2reg.status.sha3_absorb.d = sha3_fsm == sha3_pkg::StAbsorb; + assign hw2reg.status.sha3_squeeze.d = sha3_fsm == sha3_pkg::StSqueeze; + + // FIFO related status + assign hw2reg.status.fifo_depth.d[MsgFifoDepthW-1:0] = msgfifo_depth; + if ($bits(hw2reg.status.fifo_depth.d) != MsgFifoDepthW) begin : gen_fifo_depth_tie + assign hw2reg.status.fifo_depth.d[$bits(hw2reg.status.fifo_depth.d)-1:MsgFifoDepthW] = '0; + end + assign hw2reg.status.fifo_empty.d = msgfifo_empty; + assign hw2reg.status.fifo_full.d = msgfifo_full; + + // Configuration Register + logic engine_stable; + assign engine_stable = sha3_fsm == sha3_pkg::StIdle; + + // SEC_CM: CFG_SHADOWED.CONFIG.REGWEN + assign hw2reg.cfg_regwen.d = engine_stable; + + // Secret Key + // Secret key is defined as external register. So the logic latches when SW + // writes to KEY_SHARE0 , KEY_SHARE1 registers. + // SEC_CM: SW_KEY.KEY.MASKING + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + sw_key_data_reg[0] <= '0; + end else if (engine_stable) begin + for (int j = 0 ; j < MaxKeyLen/32 ; j++) begin + if (reg2hw.key_share0[j].qe) begin + sw_key_data_reg[0][32*j+:32] <= reg2hw.key_share0[j].q; + end + end // for j + end // else if engine_stable + end // always_ff + + if (EnMasking || SwKeyMasked) begin : gen_key_share1_reg + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + sw_key_data_reg[1] <= '0; + end else if (engine_stable) begin + for (int j = 0 ; j < MaxKeyLen/32 ; j++) begin + if (reg2hw.key_share1[j].qe) begin + sw_key_data_reg[1][32*j+:32] <= reg2hw.key_share1[j].q; + end + end // for j + end // else if engine_stable + end // always_ff + end else begin : gen_no_key_share1_reg + logic unused_key_share1; + assign unused_key_share1 = ^reg2hw.key_share1; + end + + if (EnMasking || !SwKeyMasked) begin : gen_key_forward + // Forward all available key shares as is. + assign sw_key_data = sw_key_data_reg; + end else begin : gen_key_unmask + // Masking is disabled but the SW still provides the key in two shares. + // Unmask the key for processing. + assign sw_key_data[0] = sw_key_data_reg[0] ^ sw_key_data_reg[1]; + end + + assign sw_key_len = key_len_e'(reg2hw.key_len.q); + + // Entropy configurations + assign wait_timer_prescaler = reg2hw.entropy_period.prescaler.q; + assign wait_timer_limit = reg2hw.entropy_period.wait_timer.q; + assign entropy_refresh_req = reg2hw.cmd.entropy_req.q + && reg2hw.cmd.entropy_req.qe; + assign entropy_seed_update = reg2hw.entropy_seed.qe; + assign entropy_seed_data = reg2hw.entropy_seed.q; + + assign entropy_hash_threshold = reg2hw.entropy_refresh_threshold_shadowed.q; + assign hw2reg.entropy_refresh_hash_cnt.de = 1'b 1; + assign hw2reg.entropy_refresh_hash_cnt.d = entropy_hash_cnt; + + assign entropy_hash_clr = reg2hw.cmd.hash_cnt_clr.qe + && reg2hw.cmd.hash_cnt_clr.q; + + // Entropy config + assign entropy_ready = reg2hw.cfg_shadowed.entropy_ready.q + & reg2hw.cfg_shadowed.entropy_ready.qe; + assign entropy_mode = entropy_mode_e'(reg2hw.cfg_shadowed.entropy_mode.q); + assign entropy_fast_process = reg2hw.cfg_shadowed.entropy_fast_process.q; + + // msg_mask_en turns on the message LFSR when KMAC is enabled. + assign cfg_msg_mask = reg2hw.cfg_shadowed.msg_mask.q; + assign msg_mask_en = cfg_msg_mask & msg_valid & msg_ready; + + // Enable unsupported mode & strength combination + assign cfg_en_unsupported_modestrength = + reg2hw.cfg_shadowed.en_unsupported_modestrength.q; + + `CALIPTRA_ASSERT(EntropyReadyLatched_A, $rose(entropy_ready) |=> !entropy_ready) + + // Idle control (registered output) + // The logic checks idle of SHA3 engine, MSG_FIFO, KMAC_CORE, KEYMGR interface + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + idle_o <= caliptra_prim_mubi_pkg::MuBi4True; + end else if ((sha3_fsm == sha3_pkg::StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg)) begin + idle_o <= caliptra_prim_mubi_pkg::MuBi4True; + end else begin + idle_o <= caliptra_prim_mubi_pkg::MuBi4False; + end + end + + // Clear the error processed + assign err_processed = reg2hw.cmd.err_processed.q & reg2hw.cmd.err_processed.qe; + + // Make sure the field has latch in reg_top + `CALIPTRA_ASSERT(ErrProcessedLatched_A, $rose(err_processed) |=> !err_processed) + + // App mode, strength, kmac_en + assign reg_kmac_en = reg2hw.cfg_shadowed.kmac_en.q; + assign reg_sha3_mode = sha3_pkg::sha3_mode_e'(reg2hw.cfg_shadowed.mode.q); + assign reg_keccak_strength = sha3_pkg::keccak_strength_e'(reg2hw.cfg_shadowed.kstrength.q); + + /////////////// + // Interrupt // + /////////////// + + // Hash process absorbed interrupt + // Convert mubi4_t to logic to generate interrupts + assign event_absorbed = caliptra_prim_mubi_pkg::mubi4_test_true_strict(app_absorbed); + + caliptra_prim_intr_hw #(.Width(1)) intr_kmac_done ( + .clk_i, + .rst_ni, + .event_intr_i (event_absorbed), + .reg2hw_intr_enable_q_i (reg2hw.intr_enable.kmac_done.q), + .reg2hw_intr_test_q_i (reg2hw.intr_test.kmac_done.q), + .reg2hw_intr_test_qe_i (reg2hw.intr_test.kmac_done.qe), + .reg2hw_intr_state_q_i (reg2hw.intr_state.kmac_done.q), + .hw2reg_intr_state_de_o (hw2reg.intr_state.kmac_done.de), + .hw2reg_intr_state_d_o (hw2reg.intr_state.kmac_done.d), + .intr_o (intr_kmac_done_o) + ); + + `CALIPTRA_ASSERT(Sha3AbsorbedPulse_A, + $rose(caliptra_prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed)) |=> + caliptra_prim_mubi_pkg::mubi4_test_false_strict(sha3_absorbed)) + + // Message FIFO empty interrupt + // + // The message FIFO empty interrupt is **not useful** for software if: + // - One of the hardware application interfaces is actively using the KMAC block. In this case + // the message FIFO is managed entirely by the application interface. + // - The SHA3 core is not in the Absorb state. Only in this state, the FIFO is writeable by + // software anyway. + // - Software has already written the Process command. The KMAC block will now empty the + // message FIFO and load its content into the SHA3 core, add the padding and then perfom + // the final absorption. Software cannot append the message further. + // + // The message FIFO empty interrupt can be **useful** for software in particular if: + // - The message FIFO was completely full previously. However, unless the KMAC block is currently + // processing a block or waiting for fresh entropy from EDN, it always empties the message FIFO + // faster than software can fill it up, meaning the message FIFO is empty most of the time. + // Note, the empty status is signaled only once after the FIFO was completely full. The FIFO + // needs to be full again for the empty status to be signaled again next time it's empty. + // + // For further details see also: + // https://opentitan.org/book/hw/ip/kmac/doc/theory_of_operation.html#fifo-depth-and-empty-status + logic status_msgfifo_empty, msgfifo_empty_gate; + logic msgfifo_empty_negedge, msgfifo_empty_q; + logic msgfifo_full_seen_d, msgfifo_full_seen_q; + assign msgfifo_empty_negedge = msgfifo_empty_q & ~msgfifo_empty; + + // Track whether the message FIFO was full after being empty. We clear the tracking: + // - When receiving the Process command. This is to start over for the next message. + // - When seeing a negative edge on the empty signal. This signals that software has reacted to + // the interrupt and is filling up the FIFO again. + assign msgfifo_full_seen_d = + msgfifo_full ? 1'b 1 : + msgfifo_empty_negedge ? 1'b 0 : + msgfifo2kmac_process ? 1'b 0 : msgfifo_full_seen_q; + + // The interrupt is gated unless software is performing an absorption operation (but not the + // final block) and the FIFO was full before. The msgfifo2kmac_process pulse is arriving from the + // FIFO together with the empty signal. + assign msgfifo_empty_gate = + app_active ? 1'b 1 : + sha3_fsm != sha3_pkg::StAbsorb ? 1'b 1 : + msgfifo2kmac_process ? 1'b 1 : ~msgfifo_full_seen_q; + + assign status_msgfifo_empty = msgfifo_empty_gate ? 1'b 0 : msgfifo_empty; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + msgfifo_empty_q <= 1'b 0; + msgfifo_full_seen_q <= 1'b 0; + end else begin + msgfifo_empty_q <= msgfifo_empty; + msgfifo_full_seen_q <= msgfifo_full_seen_d; + end + end + + caliptra_prim_intr_hw #( + .Width(1), + .IntrT("Status") + ) intr_fifo_empty ( + .clk_i, + .rst_ni, + .event_intr_i (status_msgfifo_empty), + .reg2hw_intr_enable_q_i (reg2hw.intr_enable.fifo_empty.q), + .reg2hw_intr_test_q_i (reg2hw.intr_test.fifo_empty.q), + .reg2hw_intr_test_qe_i (reg2hw.intr_test.fifo_empty.qe), + .reg2hw_intr_state_q_i (reg2hw.intr_state.fifo_empty.q), + .hw2reg_intr_state_de_o (hw2reg.intr_state.fifo_empty.de), + .hw2reg_intr_state_d_o (hw2reg.intr_state.fifo_empty.d), + .intr_o (intr_fifo_empty_o) + ); + + // Error + + logic event_error; + assign event_error = sha3_err.valid | app_err.valid + | entropy_err.valid | errchecker_err.valid + ; + + // Assing error code to the register + assign hw2reg.err_code.de = event_error; + + always_comb begin + hw2reg.err_code.d = '0; + + priority case (1'b 1) + // app_err has the highest priority. If SW issues an incorrect command + // while app is in active state, the error from AppIntf is passed + // through. + app_err.valid: begin + hw2reg.err_code.d = {app_err.code, app_err.info}; + end + + errchecker_err.valid: begin + hw2reg.err_code.d = {errchecker_err.code , errchecker_err.info}; + end + + sha3_err.valid: begin + hw2reg.err_code.d = {sha3_err.code , sha3_err.info}; + end + + entropy_err.valid: begin + hw2reg.err_code.d = {entropy_err.code, entropy_err.info}; + end + + msgfifo_err.valid: begin + hw2reg.err_code.d = {msgfifo_err.code, msgfifo_err.info}; + end + + default: begin + hw2reg.err_code.d = '0; + end + endcase + end + + // Counter errors + logic counter_error, sha3_count_error, key_index_error; + logic msgfifo_counter_error; + logic kmac_entropy_hash_counter_error; + assign counter_error = sha3_count_error + | kmac_entropy_hash_counter_error + | key_index_error + | msgfifo_counter_error; + + assign msgfifo_counter_error = msgfifo_err.valid; + + // State Errors + logic sparse_fsm_error; + logic sha3_state_error, kmac_errchk_state_error; + logic kmac_core_state_error, kmac_app_state_error; + logic kmac_entropy_state_error, kmac_state_error; + assign sparse_fsm_error = sha3_state_error + | kmac_errchk_state_error + | kmac_core_state_error + | kmac_app_state_error + | kmac_entropy_state_error + | kmac_state_error; + + // Control Signal Integrity Errors + logic control_integrity_error; + logic sha3_storage_rst_error; + assign control_integrity_error = sha3_storage_rst_error; + + caliptra_prim_intr_hw #(.Width(1)) intr_kmac_err ( + .clk_i, + .rst_ni, + .event_intr_i (event_error), + .reg2hw_intr_enable_q_i (reg2hw.intr_enable.kmac_err.q), + .reg2hw_intr_test_q_i (reg2hw.intr_test.kmac_err.q), + .reg2hw_intr_test_qe_i (reg2hw.intr_test.kmac_err.qe), + .reg2hw_intr_state_q_i (reg2hw.intr_state.kmac_err.q), + .hw2reg_intr_state_de_o (hw2reg.intr_state.kmac_err.de), + .hw2reg_intr_state_d_o (hw2reg.intr_state.kmac_err.d), + .intr_o (intr_kmac_err_o) + ); + + /////////////////// + // State Machine // + /////////////////// + + // State FF + `CALIPTRA_PRIM_FLOP_SPARSE_FSM(u_state_regs, kmac_st_d, kmac_st, kmac_st_e, KmacIdle) + + always_comb begin + // Default value + kmac_st_d = kmac_st; + + entropy_in_keyblock = 1'b 0; + kmac_state_error = 1'b 0; + + unique case (kmac_st) + KmacIdle: begin + if (kmac_cmd == CmdStart) begin + // If cSHAKE turned on + if (sha3_pkg::CShake == app_sha3_mode) begin + kmac_st_d = KmacPrefix; + end else begin + // Jump to Msg feed directly + kmac_st_d = KmacMsgFeed; + end + end else begin + kmac_st_d = KmacIdle; + end + end + + KmacPrefix: begin + // Wait until SHA3 processes one block + if (sha3_block_processed) begin + kmac_st_d = (app_kmac_en) ? KmacKeyBlock : KmacMsgFeed ; + end else begin + kmac_st_d = KmacPrefix; + end + end + + KmacKeyBlock: begin + entropy_in_keyblock = 1'b 1; + if (sha3_block_processed) begin + kmac_st_d = KmacMsgFeed; + end else begin + kmac_st_d = KmacKeyBlock; + end + end + + KmacMsgFeed: begin + // If absorbed, move to Digest + if (caliptra_prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && + caliptra_prim_mubi_pkg::mubi4_test_true_strict(sha3_done)) begin + // absorbed and done can be asserted at a cycle if Applications have + // requested the hash operation. kmac_app FSM issues CmdDone command + // if it receives absorbed signal. + kmac_st_d = KmacIdle; + end else if (caliptra_prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && + caliptra_prim_mubi_pkg::mubi4_test_false_loose(sha3_done)) begin + kmac_st_d = KmacDigest; + end else begin + kmac_st_d = KmacMsgFeed; + end + end + + KmacDigest: begin + // SW can manually run it, wait till done + if (caliptra_prim_mubi_pkg::mubi4_test_true_strict(sha3_done)) begin + kmac_st_d = KmacIdle; + end else begin + kmac_st_d = KmacDigest; + end + end + + KmacTerminalError: begin + //this state is terminal + kmac_st_d = KmacTerminalError; + kmac_state_error = 1'b 1; + end + + default: begin + kmac_st_d = KmacTerminalError; + kmac_state_error = 1'b 1; + end + endcase + + // SEC_CM: FSM.GLOBAL_ESC, FSM.LOCAL_ESC + // Unconditionally jump into the terminal error state + // if the life cycle controller triggers an escalation. + if (caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_test_true_loose(caliptra_ss_lc_escalate_en[0])) begin + kmac_st_d = KmacTerminalError; + end + end + `CALIPTRA_ASSERT_KNOWN(KmacStKnown_A, kmac_st) + + /////////////// + // Instances // + /////////////// + + // KMAC core + kmac_core #( + .EnMasking (EnMasking) + ) u_kmac_core ( + .clk_i, + .rst_ni, + + // from Msg FIFO + .fifo_valid_i (msgfifo_valid), + .fifo_data_i (msgfifo_data ), + .fifo_strb_i (msgfifo_strb ), + .fifo_ready_o (msgfifo_ready), + + // to SHA3 core + .msg_valid_o (msg_valid), + .msg_data_o (msg_data ), + .msg_strb_o (msg_strb ), + .msg_ready_i (msg_ready), + + // Configurations + .kmac_en_i (app_kmac_en), + .mode_i (app_sha3_mode), + .strength_i (app_keccak_strength), + + // Secret key interface + .key_data_i (key_data), + .key_len_i (key_len), + .key_valid_i (key_valid), + + // Controls + .start_i (sha3_start ), + .process_i (msgfifo2kmac_process), + .done_i (sha3_done ), + .process_o (kmac2sha3_process ), + + // LC escalation + .caliptra_ss_lc_escalate_en_i (caliptra_ss_lc_escalate_en[1]), + + // Error detection + .sparse_fsm_error_o (kmac_core_state_error), + .key_index_error_o (key_index_error) + ); + + // SHA3 hashing engine + + // msg_data masking + if (EnMasking == 1) begin: g_msg_mask + logic [MsgWidth-1:0] msg_mask_permuted; + + // Permute the LFSR output to avoid same lfsr applied to multiple times + always_comb begin + msg_mask_permuted = '0; + for (int unsigned i = 0 ; i < MsgWidth ; i++) begin + // Loop through the MsgPerm constant and swap between the bits + msg_mask_permuted[i] = msg_mask[RndCnstMsgPerm[i]]; + end + end + + for (genvar i = 0 ; i < Share ; i++) begin: g_msg_data_mask + assign msg_data_masked[i] = msg_data[i] + ^ ({MsgWidth{cfg_msg_mask}} & msg_mask_permuted); + end : g_msg_data_mask + end else begin : g_no_msg_mask + assign msg_data_masked[0] = msg_data[0]; + + logic unused_msgmask; + assign unused_msgmask = ^{msg_mask, cfg_msg_mask, msg_mask_en}; + end + sha3 #( + .EnMasking (EnMasking) + ) u_sha3 ( + .clk_i, + .rst_ni, + + // MSG_FIFO interface (or from KMAC) + .msg_valid_i (msg_valid), + .msg_data_i (msg_data_masked ), + .msg_strb_i (msg_strb ), + .msg_ready_o (msg_ready), + + // Entropy interface + .rand_valid_i (sha3_rand_valid), + .rand_early_i (sha3_rand_early), + .rand_data_i (sha3_rand_data), + .rand_aux_i (sha3_rand_aux), + .rand_update_o (sha3_rand_update), + .rand_consumed_o (sha3_rand_consumed), + + // N, S: Used in cSHAKE mode + .ns_data_i (ns_prefix), + + // Configurations + .mode_i (app_sha3_mode), + .strength_i (app_keccak_strength), + + // Controls (CMD register) + .start_i (sha3_start ), + .process_i (kmac2sha3_process), + .run_i (sha3_run ), + .done_i (sha3_done ), + + // LC escalation + .caliptra_ss_lc_escalate_en_i (caliptra_ss_lc_escalate_en[2]), + + .absorbed_o (sha3_absorbed), + .squeezing_o (unused_sha3_squeeze), + + .block_processed_o (sha3_block_processed), + + .sha3_fsm_o (sha3_fsm), + + .state_valid_o (state_valid), + .state_o (state), // [Share] + + // REQ/ACK interface to avoid power spikes + .run_req_o ( ), // Not used + .run_ack_i (1'b 1), // The SHA3 core is always allowed to process. + + .error_o (sha3_err), + .sparse_fsm_error_o (sha3_state_error), + .count_error_o (sha3_count_error), + .keccak_storage_rst_error_o (sha3_storage_rst_error) + ); + + // MSG_FIFO window interface to FIFO interface =============================== + // Tie the read path + assign tlram_rvalid = 1'b 0; + assign tlram_rdata = '0; + assign tlram_rerror = '0; + + // Convert endian here + // caliptra_prim_packer always packs to the right(bit0). If the input DWORD is + // big-endian, it needs to be swapped to little-endian to maintain the + // order. Internal SHA3(Keccak) runs in little-endian in contrast to HMAC + // So, no endian-swap after caliptra_prim_packer. + assign tlram_wdata_endian = conv_endian32(tlram_wdata, + reg2hw.cfg_shadowed.msg_endianness.q); + assign tlram_wmask_endian = conv_endian32(tlram_wmask, + reg2hw.cfg_shadowed.msg_endianness.q); + + // TL Adapter + tlul_adapter_sram #( + .SramAw ($clog2(MsgWindowDepth)), + .SramDw (MsgWindowWidth), + .Outstanding (1), + .ByteAccess (1), + .ErrOnRead (1) + ) u_tlul_adapter_msgfifo ( + .clk_i, + .rst_ni, + .en_ifetch_i (caliptra_prim_mubi_pkg::MuBi4False), + .tl_i (tl_win_h2d[WinMsgFifo]), + .tl_o (tl_win_d2h[WinMsgFifo]), + + .req_o (tlram_req), + .req_type_o (), + .gnt_i (tlram_gnt), + .we_o (tlram_we ), + .addr_o (tlram_addr), + .wdata_o (tlram_wdata), + .wmask_o (tlram_wmask), + .intg_error_o ( ), + .rdata_i (tlram_rdata), + .rvalid_i (tlram_rvalid), + .rerror_i (tlram_rerror), + .compound_txn_in_progress_o (), + .readback_en_i (caliptra_prim_mubi_pkg::MuBi4False), + .readback_error_o (), + .wr_collision_i (1'b0), + .write_pending_i (1'b0) + ); + + assign sw_msg_valid = tlram_req & tlram_we ; + if (MsgWidth == MsgWindowWidth) begin : gen_sw_msg_samewidth + assign sw_msg_data = tlram_wdata_endian ; + assign sw_msg_mask = tlram_wmask_endian ; + end else begin : gen_sw_msg_diff + assign sw_msg_data = {{MsgWidth-MsgWindowWidth{1'b0}}, tlram_wdata_endian}; + assign sw_msg_mask = {{MsgWidth-MsgWindowWidth{1'b0}}, tlram_wmask_endian}; + end + assign tlram_gnt = sw_msg_ready ; + + logic unused_tlram_addr; + assign unused_tlram_addr = &{1'b0, tlram_addr}; + + // Application interface Mux/Demux + kmac_app #( + .EnMasking(EnMasking), + .SecIdleAcceptSwMsg(SecIdleAcceptSwMsg), + .NumAppIntf(NumAppIntf), + .AppCfg(AppCfg) + ) u_app_intf ( + .clk_i, + .rst_ni, + + .reg_key_data_i (sw_key_data), + .reg_key_len_i (sw_key_len), + + .reg_prefix_i (reg_ns_prefix), + + .reg_kmac_en_i (reg_kmac_en), + .reg_sha3_mode_i (reg_sha3_mode), + .reg_keccak_strength_i (reg_keccak_strength), + + // data from tl_adapter + .sw_valid_i (sw_msg_valid), + .sw_data_i (sw_msg_data), + .sw_mask_i (sw_msg_mask), + .sw_ready_o (sw_msg_ready), + + // KeyMgr sideloaded key interface + .keymgr_key_i, + + // Application data in / digest out interface + .app_i, + .app_o, + + // Secret Key output to KMAC Core + .key_data_o (key_data), + .key_len_o (key_len), + .key_valid_o (key_valid), + + // to MSG_FIFO + .kmac_valid_o (mux2fifo_valid), + .kmac_data_o (mux2fifo_data), + .kmac_mask_o (mux2fifo_mask), + .kmac_ready_i (mux2fifo_ready), + + // to KMAC Core + .kmac_en_o (app_kmac_en), + + // to SHA3 Core + .sha3_prefix_o (ns_prefix), + .sha3_mode_o (app_sha3_mode), + .keccak_strength_o (app_keccak_strength), + + // Keccak state from SHA3 core + .keccak_state_valid_i (state_valid), + .keccak_state_i (state), + + // to STATE TL Window + .reg_state_valid_o (reg_state_valid), + .reg_state_o (reg_state), + + // Configuration: Sideloaded Key + .keymgr_key_en_i (reg2hw.cfg_shadowed.sideload.q), + + .absorbed_i (sha3_absorbed), // from SHA3 + .absorbed_o (app_absorbed), // to SW + + .app_active_o(app_active), + + .error_i (sha3_err.valid), + .err_processed_i (err_processed), + + .clear_after_error_o (clear_after_error), + + // Command interface + .sw_cmd_i (checked_sw_cmd), + .cmd_o (kmac_cmd), + + // Status + .entropy_ready_i (entropy_configured), + + // LC escalation + .caliptra_ss_lc_escalate_en_i (caliptra_ss_lc_escalate_en[3]), + + // Error report + .error_o (app_err), + .sparse_fsm_error_o (kmac_app_state_error) + + ); + + // Message FIFO + kmac_msgfifo #( + .OutWidth (kmac_pkg::MsgWidth), + .MsgDepth (kmac_pkg::MsgFifoDepth), + .EnMasking (EnMasking) + ) u_msgfifo ( + .clk_i, + .rst_ni, + + .fifo_valid_i (mux2fifo_valid), + .fifo_data_i (mux2fifo_data), + .fifo_mask_i (mux2fifo_mask), + .fifo_ready_o (mux2fifo_ready), + + .msg_valid_o (msgfifo_valid), + .msg_data_o (msgfifo_data[0]), + .msg_strb_o (msgfifo_strb), + .msg_ready_i (msgfifo_ready), + + .fifo_empty_o (msgfifo_empty), // intr and status + .fifo_full_o (msgfifo_full), // connected to status only + .fifo_depth_o (msgfifo_depth), + + .clear_i (sha3_done), + + .process_i (reg2msgfifo_process ), + .process_o (msgfifo2kmac_process), + + .err_o (msgfifo_err) + ); + + logic [sha3_pkg::StateW-1:0] reg_state_tl [Share]; + always_comb begin + for (int i = 0 ; i < Share; i++) begin + reg_state_tl[i] = reg_state_valid ? reg_state[i] : 'b0; + end + end + + // State (Digest) reader + kmac_staterd #( + .AddrW (9), // 512B + .EnMasking (EnMasking) + ) u_staterd ( + .clk_i, + .rst_ni, + + .tl_i (tl_win_h2d[WinState]), + .tl_o (tl_win_d2h[WinState]), + + .state_i (reg_state_tl), + + .endian_swap_i (reg2hw.cfg_shadowed.state_endianness.q) + ); + + // Error checker + kmac_errchk #( + .EnMasking (EnMasking) + ) u_errchk ( + .clk_i, + .rst_ni, + + // Configurations + .cfg_mode_i (reg_sha3_mode ), + .cfg_strength_i(reg_keccak_strength), + + .kmac_en_i (reg_kmac_en ), + .cfg_prefix_6B_i(reg_ns_prefix[47:0]), // first 6B of PREFIX + + .cfg_en_unsupported_modestrength_i (cfg_en_unsupported_modestrength), + + .entropy_ready_pulse_i (entropy_ready), + + // SW commands + .sw_cmd_i(sw_cmd), + .sw_cmd_o(checked_sw_cmd), + + // Status from KMAC_APP + .app_active_i(app_active), + + // Status from SHA3 core + .sha3_absorbed_i(sha3_absorbed ), + .keccak_done_i (sha3_block_processed), + + // LC escalation + .caliptra_ss_lc_escalate_en_i (caliptra_ss_lc_escalate_en[4]), + + .err_processed_i (err_processed), + .clear_after_error_i (clear_after_error), + + .error_o (errchecker_err), + .sparse_fsm_error_o (kmac_errchk_state_error) + ); + + // Entropy Generator + if (EnMasking == 1) begin : gen_entropy + + logic entropy_req, entropy_ack; + logic [edn_pkg::ENDPOINT_BUS_WIDTH-1:0] entropy_data; + logic unused_entropy_fips; + + // Synchronize EDN interface + caliptra_prim_sync_reqack_data #( + .Width(edn_pkg::ENDPOINT_BUS_WIDTH), + .DataSrc2Dst(1'b0), + .DataReg(1'b0) + ) u_caliptra_prim_sync_reqack_data ( + .clk_src_i (clk_i), + .rst_src_ni(rst_ni), + .clk_dst_i (clk_edn_i), + .rst_dst_ni(rst_edn_ni), + .req_chk_i (1'b1), + .src_req_i (entropy_req), + .src_ack_o (entropy_ack), + .dst_req_o (entropy_o.edn_req), + .dst_ack_i (entropy_i.edn_ack), + .data_i (entropy_i.edn_bus), + .data_o (entropy_data) + ); + + // We don't track whether the entropy is pre-FIPS or not inside KMAC. + assign unused_entropy_fips = entropy_i.edn_fips; + + kmac_entropy #( + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .RndCnstLfsrSeed(RndCnstLfsrSeed), + .RndCnstBufferLfsrSeed(RndCnstBufferLfsrSeed) + ) u_entropy ( + .clk_i, + .rst_ni, + + // EDN interface + .entropy_req_o (entropy_req), + .entropy_ack_i (entropy_ack), + .entropy_data_i(entropy_data), + + // Entropy to internal logic (DOM AND) + .rand_valid_o (sha3_rand_valid), + .rand_early_o (sha3_rand_early), + .rand_data_o (sha3_rand_data), + .rand_aux_o (sha3_rand_aux), + .rand_update_i (sha3_rand_update), + .rand_consumed_i (sha3_rand_consumed), + + // Status from internal logic + //// KMAC secret block handling indicator + .in_keyblock_i (entropy_in_keyblock), + + // Configuration + .mode_i (entropy_mode), + .entropy_ready_i (entropy_ready), + .fast_process_i (entropy_fast_process), + + //// Entropy refresh period in clk cycles + .wait_timer_prescaler_i (wait_timer_prescaler), + .wait_timer_limit_i (wait_timer_limit), + + //// Message Masking + .msg_mask_en_i (msg_mask_en), + .msg_mask_o (msg_mask), + + //// SW update of seed + .seed_update_i (entropy_seed_update), + .seed_data_i (entropy_seed_data), + .entropy_refresh_req_i (entropy_refresh_req), + + // Status + .hash_cnt_o (entropy_hash_cnt), + .hash_cnt_clr_i (entropy_hash_clr), + .hash_threshold_i (entropy_hash_threshold), + + .entropy_configured_o (entropy_configured), + + // LC escalation + .caliptra_ss_lc_escalate_en_i (caliptra_ss_lc_escalate_en[5]), + + // Error + .err_o (entropy_err), + .sparse_fsm_error_o (kmac_entropy_state_error), + .count_error_o (kmac_entropy_hash_counter_error), + .err_processed_i (err_processed) + ); + end else begin : gen_empty_entropy + // If Masking is not used, no need of entropy. Ignore inputs and config; tie output to 0. + edn_pkg::edn_rsp_t unused_entropy_input; + entropy_mode_e unused_entropy_mode; + logic unused_entropy_fast_process; + + assign unused_entropy_input = entropy_i; + assign unused_entropy_mode = entropy_mode; + assign unused_entropy_fast_process = entropy_fast_process; + + assign entropy_o = '{default: '0}; + + logic unused_sha3_rand_update; + logic unused_sha3_rand_consumed; + assign sha3_rand_valid = 1'b 1; + assign sha3_rand_early = 1'b 1; + assign sha3_rand_data = '0; + assign sha3_rand_aux = '0; + assign unused_sha3_rand_update = sha3_rand_update; + assign unused_sha3_rand_consumed = sha3_rand_consumed; + + logic unused_seed_update; + logic [31:0] unused_seed_data; + logic [31:0] unused_refresh_period; + logic unused_entropy_refresh_req; + assign unused_seed_data = entropy_seed_data; + assign unused_seed_update = entropy_seed_update; + assign unused_refresh_period = ^{wait_timer_limit, wait_timer_prescaler}; + assign unused_entropy_refresh_req = entropy_refresh_req; + + logic unused_entropy_hash; + assign unused_entropy_hash = ^{entropy_hash_clr, entropy_hash_threshold}; + assign entropy_hash_cnt = '0; + + assign entropy_err = '{valid: 1'b 0, code: ErrNone, info: '0}; + + assign kmac_entropy_state_error = 1'b 0; + assign kmac_entropy_hash_counter_error = 1'b 0; + + logic [1:0] unused_entropy_status; + assign unused_entropy_status = entropy_in_keyblock; + + // If Masking is off, always entropy configured + assign entropy_configured = caliptra_prim_mubi_pkg::MuBi4True; + end + + // MUBI4 buf + caliptra_prim_mubi4_sender #( + .AsyncOn (0) + ) u_sha3_done_sender ( + .clk_i, + .rst_ni, + .mubi_i (sha3_done_d), + .mubi_o (sha3_done) + ); + + // Register top + logic [NumAlerts-1:0] alert_test, alerts, alerts_q; + + logic shadowed_storage_err, shadowed_update_err; + kmac_reg_top u_reg ( + .clk_i, + .rst_ni, + .rst_shadowed_ni, + + .tl_i, + .tl_o, + + .tl_win_o (tl_win_h2d), + .tl_win_i (tl_win_d2h), + + .reg2hw, + .hw2reg, + + // SEC_CM: CFG_SHADOWED.CONFIG.SHADOW + .shadowed_storage_err_o (shadowed_storage_err), + .shadowed_update_err_o (shadowed_update_err), + // SEC_CM: BUS.INTEGRITY + .intg_err_o (alert_intg_err) + ); + + logic unused_cfg_shadowed_qe; + assign unused_cfg_shadowed_qe = ^{ + reg2hw.cfg_shadowed.kmac_en.qe , + reg2hw.cfg_shadowed.kstrength.qe , + reg2hw.cfg_shadowed.mode.qe , + reg2hw.cfg_shadowed.msg_endianness.qe , + reg2hw.cfg_shadowed.state_endianness.qe , + reg2hw.cfg_shadowed.sideload.qe , + reg2hw.cfg_shadowed.entropy_mode.qe , + reg2hw.cfg_shadowed.entropy_fast_process.qe , + reg2hw.cfg_shadowed.msg_mask.qe , + reg2hw.cfg_shadowed.en_unsupported_modestrength.qe + }; + + // Alerts + assign alert_test = { + reg2hw.alert_test.fatal_fault_err.q + & reg2hw.alert_test.fatal_fault_err.qe, // [1] + reg2hw.alert_test.recov_operation_err.q + & reg2hw.alert_test.recov_operation_err.qe // [0] + }; + + assign alerts = { + alert_fatal, // Alerts[1] + alert_recov_operation // Alerts[0] + }; + + assign alert_recov_operation = shadowed_update_err; + + // The recoverable alert is observable via status register until the KMAC operation is restarted + // by re-writing the Control Register. + logic status_alert_recov_ctrl_update_err; + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + status_alert_recov_ctrl_update_err <= 1'b 0; + end else if (alert_recov_operation) begin + status_alert_recov_ctrl_update_err <= 1'b 1; + end else if (err_processed) begin + status_alert_recov_ctrl_update_err <= 1'b 0; + end + end + + assign hw2reg.status.alert_recov_ctrl_update_err.d = status_alert_recov_ctrl_update_err; + + assign alert_fatal = shadowed_storage_err + | alert_intg_err + | sparse_fsm_error + | counter_error + | control_integrity_error + ; + + // Make the fatal alert observable via status register. + // Cannot be reset except the hardware reset + logic status_alert_fatal_fault; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + status_alert_fatal_fault <= 1'b 0; + end else if (alert_fatal) begin + status_alert_fatal_fault <= 1'b 1; + end + end + assign hw2reg.status.alert_fatal_fault.d = status_alert_fatal_fault; + + for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_tx + caliptra_prim_alert_sender #( + .AsyncOn(AlertAsyncOn[i]), + .IsFatal(i) + ) u_caliptra_prim_alert_sender ( + .clk_i, + .rst_ni, + .alert_test_i ( alert_test[i] ), + .alert_req_i ( alerts[i] ), + .alert_ack_o ( ), + .alert_state_o ( ), + .alert_rx_i ( alert_rx_i[i] ), + .alert_tx_o ( alert_tx_o[i] ) + ); + end + + // Below assumes NumAlerts == 2 + `CALIPTRA_ASSERT_INIT(NumAlerts2_A, NumAlerts == 2) + + always_ff @(posedge clk_i or negedge rst_ni) begin + // break up the combinatorial path for local escalation + if (!rst_ni) begin + alerts_q[1] <= 1'b0; + end else if (alerts[1]) begin + // fatal alerts cannot be cleared + alerts_q[1] <= 1'b1; + end + end + + always_ff @(posedge clk_i or negedge rst_ni) begin + // break up the combinatorial path for local escalation + if (!rst_ni) begin + alerts_q[0] <= 1'b0; + end else begin + // recoverable alerts can be cleared so just latch the value + alerts_q[0] <= alerts[0]; + end + end + + // Latched recoverable alert[0] is not used. Rather removing above, + // keep alert_q[1:0] and make alert_q[0] unused (lint waive). + logic unused_alerts_q0; + assign unused_alerts_q0 = alerts_q[0]; + + // SEC_CM: LC_ESCALATE_EN.INTERSIG.MUBI, FSM.GLOBAL_ESC, FSM.LOCAL_ESC + caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_t alert_to_caliptra_ss_lc_tx; + assign alert_to_caliptra_ss_lc_tx = caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_bool_to_caliptra_ss_lc_tx(alerts_q[1]); + for (genvar i = 0; i < NumLcSyncCopies; i++) begin : gen_or_alert_caliptra_ss_lc_sync + assign caliptra_ss_lc_escalate_en[i] = caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_or_hi(alert_to_caliptra_ss_lc_tx, caliptra_ss_lc_escalate_en_sync[i]); + end + + // Synchronize life cycle input + caliptra_prim_lc_sync #( + .NumCopies (NumLcSyncCopies) + ) u_caliptra_prim_lc_sync ( + .clk_i, + .rst_ni, + .lc_en_i ( caliptra_ss_lc_escalate_en_i ), + .lc_en_o ( caliptra_ss_lc_escalate_en_sync ) + ); + + assign en_masking_o = EnMasking; + + //////////////// + // Assertions // + //////////////// + + // Assert known for output values + `CALIPTRA_ASSERT_KNOWN(KmacDone_A, intr_kmac_done_o) + `CALIPTRA_ASSERT_KNOWN(FifoEmpty_A, intr_fifo_empty_o) + `CALIPTRA_ASSERT_KNOWN(KmacErr_A, intr_kmac_err_o) + `CALIPTRA_ASSERT_KNOWN(TlODValidKnown_A, tl_o.d_valid) + `CALIPTRA_ASSERT_KNOWN(TlOAReadyKnown_A, tl_o.a_ready) + `CALIPTRA_ASSERT_KNOWN(AlertKnownO_A, alert_tx_o) + `CALIPTRA_ASSERT_KNOWN(EnMaskingKnown_A, en_masking_o) + + // Parameter as desired + `CALIPTRA_ASSERT_INIT(SecretKeyDivideBy32_A, (kmac_pkg::MaxKeyLen % 32) == 0) + + // Command input should be sparse + `CALIPTRA_ASSUME(CmdSparse_M, reg2hw.cmd.cmd.qe |-> reg2hw.cmd.cmd.q inside {CmdStart, CmdProcess, + CmdManualRun,CmdDone, CmdNone}) + + // redundant counter error + `CALIPTRA_ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(SentMsgCountCheck_A, u_sha3.u_pad.u_sentmsg_count, + alert_tx_o[1]) + `CALIPTRA_ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(RoundCountCheck_A, u_sha3.u_keccak.u_round_count, + alert_tx_o[1]) + `CALIPTRA_ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(KeyIndexCountCheck_A, u_kmac_core.u_key_index_count, + alert_tx_o[1]) + + // Sparse FSM state error + `CALIPTRA_ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(KmacCoreFsmCheck_A, u_kmac_core.u_state_regs, alert_tx_o[1]) + `CALIPTRA_ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(KmacAppFsmCheck_A, u_app_intf.u_state_regs, alert_tx_o[1]) + `CALIPTRA_ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(SHA3FsmCheck_A, u_sha3.u_state_regs, alert_tx_o[1]) + `CALIPTRA_ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(SHA3padFsmCheck_A, u_sha3.u_pad.u_state_regs, alert_tx_o[1]) + `CALIPTRA_ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(KeccackFsmCheck_A, u_sha3.u_keccak.u_state_regs, + alert_tx_o[1]) + `CALIPTRA_ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(ErrorCheckFsmCheck_A, u_errchk.u_state_regs, alert_tx_o[1]) + `CALIPTRA_ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(KmacFsmCheck_A, u_state_regs, alert_tx_o[1]) + + // prim is only instantiated if masking is enabled + if (EnMasking == 1) begin : g_testassertion + `CALIPTRA_ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(EntropyFsmCheck_A, gen_entropy.u_entropy.u_state_regs, + alert_tx_o[1]) + + `CALIPTRA_ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(HashCountCheck_A, gen_entropy.u_entropy.u_hash_count, + alert_tx_o[1]) + + // MsgFifo.Packer + `CALIPTRA_ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT( + PackerCountCheck_A, + u_msgfifo.u_packer.g_pos_dupcnt.u_pos, + alert_tx_o[1] + ) + + // MsgFifo.Fifo + `CALIPTRA_ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT( + MsgFifoWptrCheck_A, + u_msgfifo.u_msgfifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr, + alert_tx_o[1] + ) + `CALIPTRA_ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT( + MsgFifoRptrCheck_A, + u_msgfifo.u_msgfifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr, + alert_tx_o[1] + ) + end + + // Alert assertions for reg_we onehot check + `CALIPTRA_ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ALERT(RegWeOnehotCheck_A, u_reg, alert_tx_o[1]) +endmodule diff --git a/src/caliptra_ss_lc_ctrl/rtl/kmac_app.sv b/src/caliptra_ss_lc_ctrl/rtl/kmac_app.sv new file mode 100644 index 0000000..e83f147 --- /dev/null +++ b/src/caliptra_ss_lc_ctrl/rtl/kmac_app.sv @@ -0,0 +1,911 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// KMAC Application interface + +`include "caliptra_prim_assert.sv" + +module kmac_app + import kmac_pkg::*; +#( + // App specific configs are defined in kmac_pkg + parameter bit EnMasking = 1'b0, + localparam int Share = (EnMasking) ? 2 : 1, // derived parameter + parameter bit SecIdleAcceptSwMsg = 1'b0, + parameter int unsigned NumAppIntf = 3, + parameter app_config_t AppCfg[NumAppIntf] = '{AppCfgKeyMgr, AppCfgLcCtrl, AppCfgRomCtrl} +) ( + input clk_i, + input rst_ni, + + // Secret Key from register + input [MaxKeyLen-1:0] reg_key_data_i [Share], + input key_len_e reg_key_len_i, + + // Prefix from register + input [sha3_pkg::NSRegisterSize*8-1:0] reg_prefix_i, + + // mode, strength, kmac_en from register + input reg_kmac_en_i, + input sha3_pkg::sha3_mode_e reg_sha3_mode_i, + input sha3_pkg::keccak_strength_e reg_keccak_strength_i, + + // Data from Software + input sw_valid_i, + input [MsgWidth-1:0] sw_data_i, + input [MsgWidth-1:0] sw_mask_i, + output logic sw_ready_o, + + // KeyMgr Sideload Key interface + input caliptra_ss_lc_ctrl_keymgr_pkg::hw_key_req_t keymgr_key_i, + + // Application Message in/ Digest out interface + control signals + input app_req_t [NumAppIntf-1:0] app_i, + output app_rsp_t [NumAppIntf-1:0] app_o, + + // to KMAC Core: Secret key + output logic [MaxKeyLen-1:0] key_data_o [Share], + output key_len_e key_len_o, + output logic key_valid_o, + + // to MSG_FIFO + output logic kmac_valid_o, + output logic [MsgWidth-1:0] kmac_data_o, + output logic [MsgWidth-1:0] kmac_mask_o, + input kmac_ready_i, + + // KMAC Core + output logic kmac_en_o, + + // To Sha3 Core + output logic [sha3_pkg::NSRegisterSize*8-1:0] sha3_prefix_o, + output sha3_pkg::sha3_mode_e sha3_mode_o, + output sha3_pkg::keccak_strength_e keccak_strength_o, + + // STATE from SHA3 Core + input keccak_state_valid_i, + input [sha3_pkg::StateW-1:0] keccak_state_i [Share], + + // to STATE TL-window if Application is not active, the incoming state goes to + // register if kdf_en is set, the state value goes to application and the + // output to the register is all zero. + output logic reg_state_valid_o, + output logic [sha3_pkg::StateW-1:0] reg_state_o [Share], + + // Configurations If key_en is set, the logic uses KeyMgr's sideloaded key as + // a secret key rather than register values. This only affects when software + // initiates. If App initiates the hash operation and uses KMAC algorithm, it + // always uses sideloaded key. + input keymgr_key_en_i, + + // Commands + // Command from software + input kmac_cmd_e sw_cmd_i, + + // from SHA3 + input caliptra_prim_mubi_pkg::mubi4_t absorbed_i, + + // to KMAC + output kmac_cmd_e cmd_o, + + // to SW + output caliptra_prim_mubi_pkg::mubi4_t absorbed_o, + + // To status + output logic app_active_o, + + // Status + // - entropy_ready_i: Entropy configured by SW. It is used to check if App + // is OK to request. + input caliptra_prim_mubi_pkg::mubi4_t entropy_ready_i, + + // Error input + // This error comes from KMAC/SHA3 engine. + // KeyMgr interface delivers the error signal to KeyMgr to drop the current op + // and re-initiate. + // If error happens, regardless of SW-initiated or KeyMgr-initiated, the error + // is reported to the ERR_CODE so that SW can look into. + input error_i, + + // SW sets err_processed bit in CTRL then the logic goes to Idle + input err_processed_i, + + output caliptra_prim_mubi_pkg::mubi4_t clear_after_error_o, + + // error_o value is pushed to Error FIFO at KMAC/SHA3 top and reported to SW + output kmac_pkg::err_t error_o, + + // Life cycle + input caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_t caliptra_ss_lc_escalate_en_i, + + output logic sparse_fsm_error_o +); + + import sha3_pkg::KeccakBitCapacity; + import sha3_pkg::L128; + import sha3_pkg::L224; + import sha3_pkg::L256; + import sha3_pkg::L384; + import sha3_pkg::L512; + + ///////////////// + // Definitions // + ///////////////// + + // Digest width is same to the key width `caliptra_ss_lc_ctrl_keymgr_pkg::KeyWidth`. + localparam int KeyMgrKeyW = $bits(keymgr_key_i.key[0]); + + localparam key_len_e KeyLengths [5] = '{Key128, Key192, Key256, Key384, Key512}; + + localparam int SelKeySize = (AppKeyW == 128) ? 0 : + (AppKeyW == 192) ? 1 : + (AppKeyW == 256) ? 2 : + (AppKeyW == 384) ? 3 : + (AppKeyW == 512) ? 4 : 0 ; + localparam int SelDigSize = (AppDigestW == 128) ? 0 : + (AppDigestW == 192) ? 1 : + (AppDigestW == 256) ? 2 : + (AppDigestW == 384) ? 3 : + (AppDigestW == 512) ? 4 : 0 ; + localparam key_len_e SideloadedKey = KeyLengths[SelKeySize]; + + // Define right_encode(outlen) value here + // Look at kmac_pkg::key_len_e for the kinds of key size + // + // These values should be exactly the same as the key length encodings + // in kmac_core.sv, with the only difference being that the byte representing + // the byte-length of the encoded value is in the MSB position due to right encoding + // instead of in the LSB position (left encoding). + localparam int OutLenW = 24; + localparam logic [OutLenW-1:0] EncodedOutLen [5]= '{ + 24'h 0001_80, // Key128 + 24'h 0001_C0, // Key192 + 24'h 02_0001, // Key256 + 24'h 02_8001, // Key384 + 24'h 02_0002 // Key512 + }; + + localparam logic [OutLenW-1:0] EncodedOutLenMask [5] = '{ + 24'h 00FFFF, // Key128, + 24'h 00FFFF, // Key192 + 24'h FFFFFF, // Key256 + 24'h FFFFFF, // Key384 + 24'h FFFFFF // Key512 + }; + + ///////////// + // Signals // + ///////////// + + st_e st, st_d; + + logic keymgr_key_used; + + // app_rsp_t signals + // The state machine controls mux selection, which controls the ready signal + // the other responses are controled in separate logic. So define the signals + // here and merge them to the response. + logic app_data_ready, fsm_data_ready; + logic app_digest_done, fsm_digest_done_q, fsm_digest_done_d; + logic [AppDigestW-1:0] app_digest [2]; + + // One more slot for value NumAppIntf. It is the value when no app intf is + // chosen. + localparam int unsigned AppIdxW = $clog2(NumAppIntf); + + // app_id indicates, which app interface was chosen. various logic use this + // value to get the config or return the data. + logic [AppIdxW-1:0] app_id, app_id_d; + logic clr_appid, set_appid; + + // Output length + logic [OutLenW-1:0] encoded_outlen, encoded_outlen_mask; + + // state output + // Mux selection signal + app_mux_sel_e mux_sel; + app_mux_sel_e mux_sel_buf_output; + app_mux_sel_e mux_sel_buf_err_check; + app_mux_sel_e mux_sel_buf_kmac; + + // Error checking logic + + kmac_pkg::err_t fsm_err, mux_err; + + logic service_rejected_error; + logic service_rejected_error_set, service_rejected_error_clr; + logic err_during_sw_d, err_during_sw_q; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) service_rejected_error <= 1'b 0; + else if (service_rejected_error_set) service_rejected_error <= 1'b 1; + else if (service_rejected_error_clr) service_rejected_error <= 1'b 0; + end + + //////////////////////////// + // Application Mux/ Demux // + //////////////////////////// + + + // Processing return data. + // sends to only selected app intf. + // clear digest right after done to not leak info to other interface + always_comb begin + for (int unsigned i = 0 ; i < NumAppIntf ; i++) begin + if (i == app_id) begin + app_o[i] = '{ + ready: app_data_ready | fsm_data_ready, + done: app_digest_done | fsm_digest_done_q, + digest_share0: app_digest[0], + digest_share1: app_digest[1], + // if fsm asserts done, should be an error case. + error: error_i | fsm_digest_done_q | sparse_fsm_error_o + | service_rejected_error + }; + end else begin + app_o[i] = '{ + ready: 1'b 0, + done: 1'b 0, + digest_share0: '0, + digest_share1: '0, + error: 1'b 0 + }; + end + end // for {i, NumAppIntf, i++} + end // aiways_comb + + // app_id latch + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) app_id <= AppIdxW'(0) ; // Do not select any + else if (clr_appid) app_id <= AppIdxW'(0); + else if (set_appid) app_id <= app_id_d; + end + + // app_id selection as of now, app_id uses Priority. The assumption is that + // the request normally does not collide. (ROM_CTRL activates very early + // stage at the boot sequence) + // + // If this assumption is not true, consider RR arbiter. + + // Prep for arbiter + logic [NumAppIntf-1:0] app_reqs; + logic [NumAppIntf-1:0] unused_app_gnts; + logic [$clog2(NumAppIntf)-1:0] arb_idx; + logic arb_valid; + logic arb_ready; + + always_comb begin + app_reqs = '0; + for (int unsigned i = 0 ; i < NumAppIntf ; i++) begin + app_reqs[i] = app_i[i].valid; + end + end + + caliptra_prim_arbiter_fixed #( + .N (NumAppIntf), + .DW(1), + .EnDataPort(1'b 0) + ) u_appid_arb ( + .clk_i, + .rst_ni, + + .req_i (app_reqs), + .data_i ('{default:'0}), + .gnt_o (unused_app_gnts), + .idx_o (arb_idx), + + .valid_o (arb_valid), + .data_o (), // not used + .ready_i (arb_ready) + ); + + assign app_id_d = AppIdxW'(arb_idx); + assign arb_ready = set_appid; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) fsm_digest_done_q <= 1'b 0; + else fsm_digest_done_q <= fsm_digest_done_d; + end + + ///////// + // FSM // + ///////// + + // State register + `CALIPTRA_PRIM_FLOP_SPARSE_FSM(u_state_regs, st_d, st, st_e, StIdle) + + // Create a lint error to reduce the risk of accidentally enabling this feature. + `CALIPTRA_ASSERT_STATIC_LINT_ERROR(KmacSecIdleAcceptSwMsgNonDefault, SecIdleAcceptSwMsg == 0) + + // Next State & output logic + // SEC_CM: FSM.SPARSE + always_comb begin + st_d = st; + + mux_sel = SecIdleAcceptSwMsg ? SelSw : SelNone; + + // app_id control + set_appid = 1'b 0; + clr_appid = 1'b 0; + + // Commands + cmd_o = CmdNone; + + // Software output + absorbed_o = caliptra_prim_mubi_pkg::MuBi4False; + + // Error + fsm_err = '{valid: 1'b 0, code: ErrNone, info: '0}; + sparse_fsm_error_o = 1'b 0; + + clear_after_error_o = caliptra_prim_mubi_pkg::MuBi4False; + + service_rejected_error_set = 1'b 0; + service_rejected_error_clr = 1'b 0; + + // If error happens, FSM asserts data ready but discard incoming msg + fsm_data_ready = 1'b 0; + fsm_digest_done_d = 1'b 0; + + unique case (st) + StIdle: begin + if (arb_valid) begin + st_d = StAppCfg; + + // choose app_id + set_appid = 1'b 1; + end else if (sw_cmd_i == CmdStart) begin + st_d = StSw; + // Software initiates the sequence + cmd_o = CmdStart; + end else begin + st_d = StIdle; + end + end + + StAppCfg: begin + if (AppCfg[app_id].Mode == AppKMAC && + caliptra_prim_mubi_pkg::mubi4_test_false_strict(entropy_ready_i)) begin + // Check if the entropy is not configured but it is needed in + // `AppCfg[app_id]` (KMAC mode). + // + // SW is not properly configured, report and not request Hashing + // Return the app with errors + st_d = StError; + + service_rejected_error_set = 1'b 1; + + end else begin + // As Cfg is stable now, it sends cmd + st_d = StAppMsg; + + // App initiates the data + cmd_o = CmdStart; + end + end + + StAppMsg: begin + mux_sel = SelApp; + if (app_i[app_id].valid && app_o[app_id].ready && app_i[app_id].last) begin + if (AppCfg[app_id].Mode == AppKMAC) begin + st_d = StAppOutLen; + end else begin + st_d = StAppProcess; + end + end else begin + st_d = StAppMsg; + end + end + + StAppOutLen: begin + mux_sel = SelOutLen; + + if (kmac_valid_o && kmac_ready_i) begin + st_d = StAppProcess; + end else begin + st_d = StAppOutLen; + end + end + + StAppProcess: begin + cmd_o = CmdProcess; + st_d = StAppWait; + end + + StAppWait: begin + if (caliptra_prim_mubi_pkg::mubi4_test_true_strict(absorbed_i)) begin + // Send digest to KeyMgr and complete the op + st_d = StIdle; + cmd_o = CmdDone; + + clr_appid = 1'b 1; + end else begin + st_d = StAppWait; + end + end + + StSw: begin + mux_sel = SelSw; + + cmd_o = sw_cmd_i; + absorbed_o = absorbed_i; + + if (sw_cmd_i == CmdDone) begin + st_d = StIdle; + end else begin + st_d = StSw; + end + end + + StKeyMgrErrKeyNotValid: begin + st_d = StError; + + // As mux_sel is not set to SelApp, app_data_ready is still 0. + // This logic won't accept the requests from the selected App. + fsm_err.valid = 1'b 1; + fsm_err.code = ErrKeyNotValid; + fsm_err.info = 24'(app_id); + end + + StError: begin + // In this state, the state machine flush out the request + st_d = StError; + + // Absorb data on the app interface. + fsm_data_ready = ~err_during_sw_q; + + // Next step depends on two conditions: + // 1) Error being processed by SW + // 2) Last data provided from the app interface (so that the app interface is completely) + // drained. If the error occurred during a SW operation, the app interface is not + // involved, so this condition gets skipped. + unique case ({err_processed_i, + (app_i[app_id].valid && app_i[app_id].last) || err_during_sw_q}) + 2'b00: begin + // Error not processed by SW and not last data from app interface -> keep current state. + st_d = StError; + end + 2'b01: begin + // Error not processed by SW but last data from app interface: + // 1. Send garbage digest to the app interface (in the next cycle) to complete the + // transaction. + fsm_digest_done_d = ~err_during_sw_q; + if (service_rejected_error) begin + // 2.a) Service was rejected because an app interface tried to configure KMAC while no + // entropy was available. It is assumed that SW is not loaded yet, so don't wait for + // SW to process the error. The last data from the app interface has now arrived, but + // we don't need to wait for the SHA3 core to have absorbed it because the data never + // entered the SHA3 core: the request from the app interface was terminated during the + // configuration phase. + st_d = StErrorServiceRejected; + end else begin + // 2.b) If service was not rejected, wait for SW to process the error. + st_d = StErrorAwaitSw; + end + end + 2'b10: begin + // Error processed by SW but not last data from app interface -> wait for app interface. + st_d = StErrorAwaitApp; + end + 2'b11: begin + // Error processed by SW and last data from app interface: + // Send garbage digest to the app interface (in the next cycle) to complete the + // transaction. + fsm_digest_done_d = ~err_during_sw_q; + // Flush the message FIFO and let the SHA3 engine compute a digest (which won't be used + // but serves to bring the SHA3 engine back to the idle state). + cmd_o = CmdProcess; + st_d = StErrorWaitAbsorbed; + end + default: st_d = StError; + endcase + end + + StErrorAwaitSw: begin + // Just wait for SW to process the error. + if (err_processed_i) begin + // Flush the message FIFO and let the SHA3 engine compute a digest (which won't be used + // but serves to bring the SHA3 engine back to the idle state). + cmd_o = CmdProcess; + st_d = StErrorWaitAbsorbed; + end + end + + StErrorAwaitApp: begin + // Keep absorbing data on the app interface until the last data. + fsm_data_ready = 1'b1; + if (app_i[app_id].valid && app_i[app_id].last) begin + // Send garbage digest to the app interface (in the next cycle) to complete the + // transaction. + fsm_digest_done_d = 1'b1; + // Flush the message FIFO and let the SHA3 engine compute a digest (which won't be used + // but serves to bring the SHA3 engine back to the idle state). + cmd_o = CmdProcess; + st_d = StErrorWaitAbsorbed; + end + end + + StErrorWaitAbsorbed: begin + if (caliptra_prim_mubi_pkg::mubi4_test_true_strict(absorbed_i)) begin + // Clear internal variables, send done command, and return to idle. + clr_appid = 1'b1; + clear_after_error_o = caliptra_prim_mubi_pkg::MuBi4True; + service_rejected_error_clr = 1'b1; + cmd_o = CmdDone; + st_d = StIdle; + // If error originated from SW, report 'absorbed' to SW. + if (err_during_sw_q) begin + absorbed_o = caliptra_prim_mubi_pkg::MuBi4True; + end + end + end + + StErrorServiceRejected: begin + // Clear internal variables and return to idle. + clr_appid = 1'b1; + clear_after_error_o = caliptra_prim_mubi_pkg::MuBi4True; + service_rejected_error_clr = 1'b1; + st_d = StIdle; + end + + StTerminalError: begin + // this state is terminal + st_d = st; + sparse_fsm_error_o = 1'b 1; + fsm_err.valid = 1'b 1; + fsm_err.code = ErrFatalError; + fsm_err.info = 24'(app_id); + end + + default: begin + st_d = StTerminalError; + sparse_fsm_error_o = 1'b 1; + end + endcase + + // SEC_CM: FSM.GLOBAL_ESC, FSM.LOCAL_ESC + // Unconditionally jump into the terminal error state + // if the life cycle controller triggers an escalation. + if (caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_test_true_loose(caliptra_ss_lc_escalate_en_i)) begin + st_d = StTerminalError; + end + + // Handle errors outside the terminal error state. + if (st_d != StTerminalError) begin + // Key from keymgr is used but not valid, so abort into the invalid key error state. + if (keymgr_key_used && !keymgr_key_i.valid) begin + st_d = StKeyMgrErrKeyNotValid; + end + end + end + + // Track errors occurring in SW mode. + assign err_during_sw_d = + (mux_sel == SelSw) && (st_d inside {StError, StKeyMgrErrKeyNotValid}) ? 1'b1 : // set + (st_d == StIdle) ? 1'b0 : // clear + err_during_sw_q; // hold + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + err_during_sw_q <= 1'b0; + end else begin + err_during_sw_q <= err_during_sw_d; + end + end + + ////////////// + // Datapath // + ////////////// + + // Encoded output length + assign encoded_outlen = EncodedOutLen[SelDigSize]; + assign encoded_outlen_mask = EncodedOutLenMask[SelKeySize]; + + // Data mux + // This is the main part of the KeyMgr interface logic. + // The FSM selects KeyMgr interface in a cycle after it receives the first + // valid data from KeyMgr. The ready signal to the KeyMgr data interface + // represents the MSG_FIFO ready, only when it is in StKeyMgrMsg state. + // After KeyMgr sends last beat, the kmac interface (to MSG_FIFO) is switched + // to OutLen. OutLen is pre-defined values. See `EncodeOutLen` parameter above. + always_comb begin + app_data_ready = 1'b 0; + sw_ready_o = 1'b 1; + + kmac_valid_o = 1'b 0; + kmac_data_o = '0; + kmac_mask_o = '0; + + unique case (mux_sel_buf_kmac) + SelApp: begin + // app_id is valid at this time + kmac_valid_o = app_i[app_id].valid; + kmac_data_o = app_i[app_id].data; + // Expand strb to bits. caliptra_prim_packer inside MSG_FIFO accepts the bit masks + for (int i = 0 ; i < $bits(app_i[app_id].strb) ; i++) begin + kmac_mask_o[8*i+:8] = {8{app_i[app_id].strb[i]}}; + end + app_data_ready = kmac_ready_i; + end + + SelOutLen: begin + // Write encoded output length value + kmac_valid_o = 1'b 1; // always write + kmac_data_o = MsgWidth'(encoded_outlen); + kmac_mask_o = MsgWidth'(encoded_outlen_mask); + end + + SelSw: begin + kmac_valid_o = sw_valid_i; + kmac_data_o = sw_data_i ; + kmac_mask_o = sw_mask_i ; + sw_ready_o = kmac_ready_i ; + end + + default: begin // Incl. SelNone + kmac_valid_o = 1'b 0; + kmac_data_o = '0; + kmac_mask_o = '0; + end + + endcase + end + + // Error checking for Mux + always_comb begin + mux_err = '{valid: 1'b 0, code: ErrNone, info: '0}; + + if (mux_sel_buf_err_check != SelSw && sw_valid_i) begin + // If SW writes message into FIFO + mux_err = '{ + valid: 1'b 1, + code: ErrSwPushedMsgFifo, + info: 24'({8'h 00, 8'(st), 8'(mux_sel_buf_err_check)}) + }; + end else if (app_active_o && sw_cmd_i != CmdNone) begin + // If SW issues command except start + mux_err = '{ + valid: 1'b 1, + code: ErrSwIssuedCmdInAppActive, + info: 24'(sw_cmd_i) + }; + end + end + + logic [AppMuxWidth-1:0] mux_sel_buf_output_logic; + assign mux_sel_buf_output = app_mux_sel_e'(mux_sel_buf_output_logic); + + // SEC_CM: LOGIC.INTEGRITY + caliptra_prim_sec_anchor_buf #( + .Width(AppMuxWidth) + ) u_caliptra_prim_buf_state_output_sel ( + .in_i(mux_sel), + .out_o(mux_sel_buf_output_logic) + ); + + logic [AppMuxWidth-1:0] mux_sel_buf_err_check_logic; + assign mux_sel_buf_err_check = app_mux_sel_e'(mux_sel_buf_err_check_logic); + + // SEC_CM: LOGIC.INTEGRITY + caliptra_prim_sec_anchor_buf #( + .Width(AppMuxWidth) + ) u_caliptra_prim_buf_state_err_check ( + .in_i(mux_sel), + .out_o(mux_sel_buf_err_check_logic) + ); + + logic [AppMuxWidth-1:0] mux_sel_buf_kmac_logic; + assign mux_sel_buf_kmac = app_mux_sel_e'(mux_sel_buf_kmac_logic); + + // SEC_CM: LOGIC.INTEGRITY + caliptra_prim_sec_anchor_buf #( + .Width(AppMuxWidth) + ) u_caliptra_prim_buf_state_kmac_sel ( + .in_i(mux_sel), + .out_o(mux_sel_buf_kmac_logic) + ); + + // SEC_CM: LOGIC.INTEGRITY + logic reg_state_valid; + caliptra_prim_sec_anchor_buf #( + .Width(1) + ) u_caliptra_prim_buf_state_output_valid ( + .in_i(reg_state_valid), + .out_o(reg_state_valid_o) + ); + + // Keccak state Demux + // Keccak state --> Register output is enabled when state is in StSw + always_comb begin + reg_state_valid = 1'b 0; + reg_state_o = '{default:'0}; + if ((mux_sel_buf_output == SelSw) && + caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_test_false_strict(caliptra_ss_lc_escalate_en_i)) begin + reg_state_valid = keccak_state_valid_i; + reg_state_o = keccak_state_i; + // If key is sideloaded and KMAC is SW initiated + // hide the capacity from SW by zeroing (see #17508) + if (keymgr_key_en_i) begin + for (int i = 0; i < Share; i++) begin + unique case (reg_keccak_strength_i) + L128: reg_state_o[i][sha3_pkg::StateW-1-:KeccakBitCapacity[L128]] = '0; + L224: reg_state_o[i][sha3_pkg::StateW-1-:KeccakBitCapacity[L224]] = '0; + L256: reg_state_o[i][sha3_pkg::StateW-1-:KeccakBitCapacity[L256]] = '0; + L384: reg_state_o[i][sha3_pkg::StateW-1-:KeccakBitCapacity[L384]] = '0; + L512: reg_state_o[i][sha3_pkg::StateW-1-:KeccakBitCapacity[L512]] = '0; + default: reg_state_o[i] = '0; + endcase + end + end + end + end + + // Keccak state --> KeyMgr + always_comb begin + app_digest_done = 1'b 0; + app_digest = '{default:'0}; + if (st == StAppWait && caliptra_prim_mubi_pkg::mubi4_test_true_strict(absorbed_i) && + caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_test_false_strict(caliptra_ss_lc_escalate_en_i)) begin + // SHA3 engine has calculated the hash. Return the data to KeyMgr + app_digest_done = 1'b 1; + + // digest has always 2 entries. If !EnMasking, second is tied to 0. + for (int i = 0 ; i < Share ; i++) begin + // Return the portion of state. + app_digest[i] = keccak_state_i[i][AppDigestW-1:0]; + end + end + end + + + // Secret Key Mux + + // Prepare merged key if EnMasking is not set. + // Combine share keys into unpacked array for logic below to assign easily. + // SEC_CM: KEY.SIDELOAD + logic [MaxKeyLen-1:0] keymgr_key [Share]; + if (EnMasking == 1) begin : g_masked_key + for (genvar i = 0; i < Share; i++) begin : gen_key_pad + assign keymgr_key[i] = {(MaxKeyLen-KeyMgrKeyW)'(0), keymgr_key_i.key[i]}; + end + end else begin : g_unmasked_key + always_comb begin + keymgr_key[0] = '0; + for (int i = 0; i < caliptra_ss_lc_ctrl_keymgr_pkg::Shares; i++) begin + keymgr_key[0][KeyMgrKeyW-1:0] ^= keymgr_key_i.key[i]; + end + end + end + + // Sideloaded key manage: Keep use sideloaded key for KMAC AppIntf until the + // hashing operation is finished. + always_comb begin + keymgr_key_used = 1'b0; + key_len_o = reg_key_len_i; + for (int i = 0 ; i < Share; i++) begin + key_data_o[i] = reg_key_data_i[i]; + end + // The key is considered invalid in all cases that are not listed below (which includes idle and + // error states). + key_valid_o = 1'b0; + + unique case (st) + StAppCfg, StAppMsg, StAppOutLen, StAppProcess, StAppWait: begin + // Key from keymgr is actually used if the current HW app interface does *keyed* MAC. + keymgr_key_used = AppCfg[app_id].Mode == AppKMAC; + key_len_o = SideloadedKey; + for (int i = 0 ; i < Share; i++) begin + key_data_o[i] = keymgr_key[i]; + end + // Key is valid if the current HW app interface does *keyed* MAC and the key provided by + // keymgr is valid. + key_valid_o = keymgr_key_used && keymgr_key_i.valid; + end + + StSw: begin + if (keymgr_key_en_i) begin + // Key from keymgr is actually used if *keyed* MAC is enabled. + keymgr_key_used = kmac_en_o; + key_len_o = SideloadedKey; + for (int i = 0 ; i < Share; i++) begin + key_data_o[i] = keymgr_key[i]; + end + end + // Key is valid if SW does *keyed* MAC and ... + if (kmac_en_o) begin + if (!keymgr_key_en_i) begin + // ... it uses the key from kmac's CSR, or ... + key_valid_o = 1'b1; + end else begin + // ... it uses the key provided by keymgr and that one is valid. + key_valid_o = keymgr_key_i.valid; + end + end + end + + default: ; + endcase + end + + // Prefix Demux + // For SW, always prefix register. + // For App intf, check PrefixMode cfg and if 1, use Prefix cfg. + always_comb begin + sha3_prefix_o = '0; + + unique case (st) + StAppCfg, StAppMsg, StAppOutLen, StAppProcess, StAppWait: begin + // Check app intf cfg + for (int unsigned i = 0 ; i < NumAppIntf ; i++) begin + if (app_id == i) begin + if (AppCfg[i].PrefixMode == 1'b 0) begin + sha3_prefix_o = reg_prefix_i; + end else begin + sha3_prefix_o = AppCfg[i].Prefix; + end + end + end + end + + StSw: begin + sha3_prefix_o = reg_prefix_i; + end + + default: begin + sha3_prefix_o = reg_prefix_i; + end + endcase + end + + // KMAC en / SHA3 mode / Strength + // by default, it uses reg cfg. When app intf reqs come, it uses AppCfg. + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + kmac_en_o <= 1'b 0; + sha3_mode_o <= sha3_pkg::Sha3; + keccak_strength_o <= sha3_pkg::L256; + end else if (clr_appid) begin + // As App completed, latch reg value + kmac_en_o <= reg_kmac_en_i; + sha3_mode_o <= reg_sha3_mode_i; + keccak_strength_o <= reg_keccak_strength_i; + end else if (set_appid) begin + kmac_en_o <= AppCfg[arb_idx].Mode == AppKMAC ? 1'b 1 : 1'b 0; + sha3_mode_o <= AppCfg[arb_idx].Mode == AppSHA3 + ? sha3_pkg::Sha3 : sha3_pkg::CShake; + keccak_strength_o <= AppCfg[arb_idx].KeccakStrength ; + end else if (st == StIdle) begin + kmac_en_o <= reg_kmac_en_i; + sha3_mode_o <= reg_sha3_mode_i; + keccak_strength_o <= reg_keccak_strength_i; + end + end + + // Status + assign app_active_o = (st inside {StAppCfg, StAppMsg, StAppOutLen, + StAppProcess, StAppWait}); + + // Error Reporting ========================================================== + always_comb begin + priority casez ({fsm_err.valid, mux_err.valid}) + 2'b ?1: error_o = mux_err; + 2'b 10: error_o = fsm_err; + default: error_o = '{valid: 1'b0, code: ErrNone, info: '0}; + endcase + end + + //////////////// + // Assertions // + //////////////// + + // KeyMgr sideload key and the digest should be in the Key Length value + `CALIPTRA_ASSERT_INIT(SideloadKeySameToDigest_A, KeyMgrKeyW <= AppDigestW) + `CALIPTRA_ASSERT_INIT(AppIntfInRange_A, AppDigestW inside {128, 192, 256, 384, 512}) + + // Issue(#13655): Having a coverage that sideload keylen and CSR keylen are + // different. + `CALIPTRA_COVER(AppIntfUseDifferentSizeKey_C, + (st == StAppCfg && kmac_en_o) |-> reg_key_len_i != SideloadedKey) + +endmodule diff --git a/src/caliptra_ss_lc_ctrl/rtl/kmac_core.sv b/src/caliptra_ss_lc_ctrl/rtl/kmac_core.sv new file mode 100644 index 0000000..c9eac15 --- /dev/null +++ b/src/caliptra_ss_lc_ctrl/rtl/kmac_core.sv @@ -0,0 +1,470 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// KMAC control and padding logic + +`include "caliptra_prim_assert.sv" + +module kmac_core + import kmac_pkg::*; +#( + // EnMasking: Enable masking security hardening inside keccak_round + // If it is enabled, the result digest will be two set of 1600bit. + parameter bit EnMasking = 0, + localparam int Share = (EnMasking) ? 2 : 1 // derived parameter +) ( + input clk_i, + input rst_ni, + + // From Message FIFO + input fifo_valid_i, + input [MsgWidth-1:0] fifo_data_i [Share], + input [MsgStrbW-1:0] fifo_strb_i, + output logic fifo_ready_o, + + // to SHA3 Core + output logic msg_valid_o, + output logic [MsgWidth-1:0] msg_data_o [Share], + output logic [MsgStrbW-1:0] msg_strb_o, + input msg_ready_i, + + // Configurations + + // If kmac_en is cleared, Core logic doesn't function but forward incoming + // message to SHA3 core + input kmac_en_i, + input sha3_pkg::sha3_mode_e mode_i, + input sha3_pkg::keccak_strength_e strength_i, + + // Key input from CSR + input [MaxKeyLen-1:0] key_data_i [Share], + input key_len_e key_len_i, + input logic key_valid_i, + + // Controls : same to SHA3 core + input start_i, + input process_i, + input caliptra_prim_mubi_pkg::mubi4_t done_i, + + // Control to SHA3 core + output logic process_o, + + // Life cycle + input caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_t caliptra_ss_lc_escalate_en_i, + + output logic sparse_fsm_error_o, + output logic key_index_error_o +); + + import sha3_pkg::KeccakMsgAddrW; + import sha3_pkg::KeccakCountW; + import sha3_pkg::KeccakRate; + import sha3_pkg::L128; + import sha3_pkg::L224; + import sha3_pkg::L256; + import sha3_pkg::L384; + import sha3_pkg::L512; + + ///////////////// + // Definitions // + ///////////////// + + // Encoding generated with: + // $ ./util/design/sparse-fsm-encode.py -d 3 -m 5 -n 6 \ + // -s 401658243 --language=sv + // + // Hamming distance histogram: + // + // 0: -- + // 1: -- + // 2: -- + // 3: |||||||||||||||||||| (50.00%) + // 4: |||||||||||||||| (40.00%) + // 5: |||| (10.00%) + // 6: -- + // + // Minimum Hamming distance: 3 + // Maximum Hamming distance: 5 + // Minimum Hamming weight: 1 + // Maximum Hamming weight: 4 + // + localparam int StateWidth = 6; + typedef enum logic [StateWidth-1:0] { + StKmacIdle = 6'b011000, + + // Secret Key pushing stage + // The key is sliced by caliptra_prim_slicer. This state pushes the sliced data into + // SHA3 hashing engine. When it hits the block size limit, + // (same as in sha3pad) the state machine moves to Message. + StKey = 6'b010111, + + // Incoming Message + // The core does nothing but forwarding the incoming message to SHA3 hashing + // engine by turning off `en_kmac_datapath`. + StKmacMsg = 6'b001110, + + // Wait till done signal + StKmacFlush = 6'b101011, + + // Terminal Error + StTerminalError = 6'b100000 + } kmac_st_e ; + + ///////////// + // Signals // + ///////////// + + // represents encode_string(K) + logic [MaxEncodedKeyW-1:0] encoded_key [Share]; + + // Key slice address + // This signal controls the 64 bit output of the sliced secret_key. + logic [sha3_pkg::KeccakMsgAddrW-1:0] key_index; + logic inc_keyidx, clr_keyidx; + + // `sent_blocksize` indicates that the encoded key is sent to sha3 hashing + // engine. If this hits at StKey stage, the state moves to message state. + logic [sha3_pkg::KeccakCountW-1:0] block_addr_limit; + logic sent_blocksize; + + // Internal message signals + logic kmac_valid ; + logic [MsgWidth-1:0] kmac_data [Share]; + logic [MsgStrbW-1:0] kmac_strb ; + + // Control SHA3 core + // `kmac_process` is to forward the process signal to SHA3 core only after + // the KMAC core writes the key block in case of the message is empty. + // If the incoming message is empty, there's chance that the `process_i` + // signal can be asserted while KMAC core processing the key block. + logic kmac_process, process_latched; + + // Indication of Secret key write stage. Only in this stage, the internal + // message interface is active. + logic en_key_write; + logic en_kmac_datapath; + + // Encoded key has wider bits. `key_sliced` is the data to send to sha3 + logic [MsgWidth-1:0] key_sliced [Share]; + + // The following signals are only used in assertions. + logic unused_signals; + assign unused_signals = ^{mode_i, key_valid_i}; + + ///////// + // FSM // + ///////// + kmac_st_e st, st_d; + + // State register + `CALIPTRA_PRIM_FLOP_SPARSE_FSM(u_state_regs, st_d, st, kmac_st_e, StKmacIdle) + + // Next state and output logic + // SEC_CM: FSM.SPARSE + always_comb begin + st_d = st; + + en_kmac_datapath = 1'b 0; + en_key_write = 1'b 0; + + clr_keyidx = 1'b 0; + + kmac_valid = 1'b 0; + kmac_process = 1'b 0; + + sparse_fsm_error_o = 1'b 0; + + unique case (st) + StKmacIdle: begin + if (kmac_en_i && start_i) begin + st_d = StKey; + end else begin + st_d = StKmacIdle; + end + end + + // If State enters here, regardless of the `process_i`, the state writes + // full block size of the key into SHA3 hashing engine. + StKey: begin + en_kmac_datapath = 1'b 1; + en_key_write = 1'b 1; + + if (sent_blocksize) begin + st_d = StKmacMsg; + + kmac_valid = 1'b 0; + clr_keyidx = 1'b 1; + end else begin + st_d = StKey; + + kmac_valid = 1'b 1; + end + end + + StKmacMsg: begin + // If process is previously latched, it is sent to SHA3 here. + if (process_i || process_latched) begin + st_d = StKmacFlush; + + kmac_process = 1'b 1; + end else begin + st_d = StKmacMsg; + end + end + + StKmacFlush: begin + if (caliptra_prim_mubi_pkg::mubi4_test_true_strict(done_i)) begin + st_d = StKmacIdle; + end else begin + st_d = StKmacFlush; + end + end + + StTerminalError: begin + // this state is terminal + st_d = st; + sparse_fsm_error_o = 1'b 1; + end + + default: begin + // this state is terminal + st_d = StTerminalError; + sparse_fsm_error_o = 1'b 1; + end + endcase + + // SEC_CM: FSM.GLOBAL_ESC, FSM.LOCAL_ESC + // Unconditionally jump into the terminal error state + // if the life cycle controller triggers an escalation. + if (caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_test_true_loose(caliptra_ss_lc_escalate_en_i)) begin + st_d = StTerminalError; + end + end + + ////////////// + // Datapath // + ////////////// + + // DATA Mux depending on kmac_en + // When Key write happens, hold the FIFO request. so fifo_ready_o is tied to 0 + assign msg_valid_o = (en_kmac_datapath) ? kmac_valid : fifo_valid_i; + assign msg_data_o = (en_kmac_datapath) ? kmac_data : fifo_data_i ; + assign msg_strb_o = (en_kmac_datapath) ? kmac_strb : fifo_strb_i ; + assign fifo_ready_o = (en_kmac_datapath) ? 1'b 0 : msg_ready_i ; + + // secret key write request to SHA3 hashing engine is always full width write. + // KeyMgr is fixed 256 bit output. So `right_encode(256)` is 0x020100 --> strb 3 + assign kmac_strb = (en_key_write ) ? '1 : '0; + + assign kmac_data = (en_key_write) ? key_sliced : '{default:'0}; + + // Process is controlled by the KMAC core always. + // This is mainly to prevent process_i asserted while KMAC core is writing + // the secret key to SHA3 hashing engine (the empty message case) + assign process_o = (kmac_en_i) ? kmac_process : process_i ; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + process_latched <= 1'b 0; + end else if (process_i && !process_o) begin + process_latched <= 1'b 1; + end else if (process_o || + caliptra_prim_mubi_pkg::mubi4_test_true_strict(done_i)) begin + process_latched <= 1'b 0; + end + end + + // bytepad(encode_string(K), 168 or 136) ===================================== + // 1. Prepare left_encode(w) + // 2. Prepare left_encode(len(secret_key)) + // 3. Concatenate left_encode(len(secret_key)) || secret_key + // 4. Concaatenate left_encode(w) || encode_string(secret_key) + // 5. Based on the address, slice out the data into MsgWidth bits + + // left_encode(w): Same as used in sha3pad logic. + logic [15:0] encode_bytepad; + assign encode_bytepad = sha3_pkg::encode_bytepad_len(strength_i); + + // left_encode(len(secret_key)) + // encoded length is always byte size. Use MaxEncodedKeyLenByte parameter + // from kmac_pkg and add one more byte to indicate how many bytes used to + // represent len(secret_key) + // Note that if the secret_key is 128 bit, only lower 16 bits of + // `encode_keylen` are valid. Refer `encoded_key` concatenation logic below. + // As the encoded string in the spec big-endian, The endian swap is a must. + logic [MaxEncodedKeyLenSize + 8 - 1:0] encode_keylen [Share]; + + always_comb begin + // the spec mentioned the key length is encoded in left_encode() + // The number is represented in big-endian. For example: + // 384 ==> 0x02 0x01 0x80 + // The first byte is the number of bytes to represent 384 + // The second byte represents 2**8 number, which is 256 here. + // The third byte represents 2**0 number, which is 128. + // The data put into MsgFIFO is little-endian and SHA3(Keccak) processes in + // little-endian. So, below keylen swaps the byte order + unique case (key_len_i) + // endian-swapped key_length num_bytes + // Key128: encode_keylen[0] = {{<<8{MaxEncodedKeyLenSize'(128)}}, 8'h 01}; + // Key192: encode_keylen[0] = {{<<8{MaxEncodedKeyLenSize'(192)}}, 8'h 01}; + // Key256: encode_keylen[0] = {{<<8{MaxEncodedKeyLenSize'(256)}}, 8'h 02}; + // Key384: encode_keylen[0] = {{<<8{MaxEncodedKeyLenSize'(384)}}, 8'h 02}; + // Key512: encode_keylen[0] = {{<<8{MaxEncodedKeyLenSize'(512)}}, 8'h 02}; + + // Vivado does not support stream swap for non context value. So assign + // the value directly. + Key128: encode_keylen[0] = (MaxEncodedKeyLenSize+8)'('h 0080_01); + Key192: encode_keylen[0] = (MaxEncodedKeyLenSize+8)'('h 00C0_01); + Key256: encode_keylen[0] = (MaxEncodedKeyLenSize+8)'('h 0001_02); + Key384: encode_keylen[0] = (MaxEncodedKeyLenSize+8)'('h 8001_02); + Key512: encode_keylen[0] = (MaxEncodedKeyLenSize+8)'('h 0002_02); + default: encode_keylen[0] = '0; + endcase + end + + if (EnMasking) begin: gen_encode_keylen_masked + assign encode_keylen[1] = '0; + end + + // encode_string(secret_key): Concatenate key + // Based on the left_encode(len(secret_key)) size, the concatenation logic + // should be changed. If key length is 128 bit, only lower 16 bits of the + // encoded length are used so that the upper 8 bits are padded with 0 as + // defined in bytepad() function. + + for (genvar i = 0 ; i < Share; i++) begin : gen_encoded_key + always_comb begin + unique case (key_len_i) + // In Key 128, 192 case, only lower parts of encode_keylen signal is + // used. So upper padding requires 8 more bits than MaxKeyLen - keylen + Key128: encoded_key[i] = {(8 + MaxKeyLen - 128)'(0), + key_data_i[i][0+:128], + encode_keylen[i][0+:MaxEncodedKeyLenSize]}; + + Key192: encoded_key[i] = {(8 + MaxKeyLen - 192)'(0), + key_data_i[i][0+:192], + encode_keylen[i][0+:MaxEncodedKeyLenSize]}; + + Key256: encoded_key[i] = {(MaxKeyLen - 256)'(0), + key_data_i[i][0+:256], + encode_keylen[i]}; + + Key384: encoded_key[i] = {(MaxKeyLen - 384)'(0), + key_data_i[i][0+:384], + encode_keylen[i]}; + + // Assume 512bit is the MaxKeyLen + Key512: encoded_key[i] = {key_data_i[i][0+:512], + encode_keylen[i]}; + + default: encoded_key[i] = '0; + endcase + end + end : gen_encoded_key + + // Above logic assumes MaxKeyLen as 512 bits. Revise if it is not. + `CALIPTRA_ASSERT_INIT(MaxKeyLenMatchToKey512_A, kmac_pkg::MaxKeyLen == 512) + + // Combine the bytepad `left_encode(w)` and the `encode_string(secret_key)` + logic [MaxEncodedKeyW + 16 -1 :0] encoded_key_block [Share]; + + assign encoded_key_block[0] = {encoded_key[0], encode_bytepad}; + + if (EnMasking) begin : gen_encoded_key_block_masked + assign encoded_key_block[1] = {encoded_key[1], 16'h 0}; + end + + // Slicer to slice out 64 bits + for (genvar i = 0 ; i < Share ; i++) begin : gen_key_slicer + caliptra_prim_slicer #( + .InW (MaxEncodedKeyW+16), + .IndexW(KeccakMsgAddrW), + .OutW(MsgWidth) + ) u_key_slicer ( + .sel_i (key_index), + .data_i (encoded_key_block[i]), + .data_o (key_sliced[i]) + ); + end + + // `key_index` logic + // key_index is used to select MsgWidth data from long `encoded_key_block` + // It behaves same as `keccak_addr` or `prefix_index` in sha3pad module. + assign inc_keyidx = kmac_valid & msg_ready_i ; + + // This primitive is used to place a hardened counter + // SEC_CM: CTR.REDUN + caliptra_prim_count #( + .Width(sha3_pkg::KeccakMsgAddrW) + ) u_key_index_count ( + .clk_i, + .rst_ni, + .clr_i(clr_keyidx), + .set_i(1'b0), + .set_cnt_i('0), + .incr_en_i(inc_keyidx), + .decr_en_i(1'b0), + .step_i(sha3_pkg::KeccakMsgAddrW'(1)), + .commit_i(1'b1), + .cnt_o(key_index), + .cnt_after_commit_o(), + .err_o(key_index_error_o) + ); + + // Block size based on the address. + // This is used for bytepad() and also pad10*1() + // assign block_addr_limit = KeccakRate[strength_i]; + // but below is easier to understand + always_comb begin + unique case (strength_i) + L128: block_addr_limit = KeccakCountW'(KeccakRate[L128]); + L224: block_addr_limit = KeccakCountW'(KeccakRate[L224]); + L256: block_addr_limit = KeccakCountW'(KeccakRate[L256]); + L384: block_addr_limit = KeccakCountW'(KeccakRate[L384]); + L512: block_addr_limit = KeccakCountW'(KeccakRate[L512]); + + default: block_addr_limit = '0; + endcase + end + + assign sent_blocksize = (key_index == block_addr_limit); + + + // Encoded Output Length ===================================================== + // + // KMAC(K,X,L,S) := cSHAKE(newX,L,"KMAC",S) + // K : Secret Key + // X : Input Message + // L : Output Length + // S : Customization input string + // newX = bytepad(encode_string(key), 168or136) || X || right_encode(L) + // + // Software writes desired output length as encoded value into the message + // FIFO at the end of the message prior to set !!CMD.process. + + + //////////////// + // Assertions // + //////////////// + + // If process_latched is set, then at Message state, it should be cleared + + `CALIPTRA_ASSERT(ProcessLatchedCleared_A, + st == StKmacMsg && process_latched |=> !process_latched) + + // Assume configuration is stable during the operation + `CALIPTRA_ASSUME(KmacEnStable_M, $changed(kmac_en_i) |-> st inside {StKmacIdle, StTerminalError}) + `CALIPTRA_ASSUME(ModeStable_M, $changed(mode_i) |-> st inside {StKmacIdle, StTerminalError}) + `CALIPTRA_ASSUME(StrengthStable_M, + $changed(strength_i) |-> + (st inside {StKmacIdle, StTerminalError}) || + ($past(st) == StKmacIdle)) + `CALIPTRA_ASSUME(KeyLengthStableWhenValid_M, key_valid_i && !$rose(key_valid_i) |-> $stable(key_len_i)) + `CALIPTRA_ASSUME(KeyDataStableWhenValid_M, key_valid_i && !$rose(key_valid_i) |-> $stable(key_data_i)) + + // no acked to MsgFIFO in StKmacMsg + `CALIPTRA_ASSERT(AckOnlyInMessageState_A, + fifo_valid_i && fifo_ready_o && kmac_en_i |-> st == StKmacMsg) + +endmodule : kmac_core diff --git a/src/caliptra_ss_lc_ctrl/rtl/kmac_entropy.sv b/src/caliptra_ss_lc_ctrl/rtl/kmac_entropy.sv new file mode 100644 index 0000000..9f20f78 --- /dev/null +++ b/src/caliptra_ss_lc_ctrl/rtl/kmac_entropy.sv @@ -0,0 +1,779 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// KMAC Entropy Generation module + +`include "caliptra_prim_assert.sv" + +module kmac_entropy + import kmac_pkg::*; + import kmac_reg_pkg::*; +#( + parameter lfsr_perm_t RndCnstLfsrPerm = RndCnstLfsrPermDefault, + parameter lfsr_seed_t RndCnstLfsrSeed = RndCnstLfsrSeedDefault, + parameter buffer_lfsr_seed_t RndCnstBufferLfsrSeed = RndCnstBufferLfsrSeedDefault +) ( + input clk_i, + input rst_ni, + + // EDN interface + output logic entropy_req_o, + input entropy_ack_i, + input [edn_pkg::ENDPOINT_BUS_WIDTH-1:0] entropy_data_i, + + // Entropy to internal + output logic rand_valid_o, + output logic rand_early_o, + output logic [sha3_pkg::StateW/2-1:0] rand_data_o, + output logic rand_aux_o, + input rand_update_i, + input rand_consumed_i, + + // Status + input in_keyblock_i, + + // Configurations + input entropy_mode_e mode_i, + //// SW sets ready bit when EDN is ready to accept requests through its app. + //// interface. + input entropy_ready_i, + + //// Garbage random value when not processing Keyblock, if this config is + //// turned on, the logic sending garbage value and never de-assert + //// rand_valid_o unless it is not processing KeyBlock. + input fast_process_i, + + //// PRNG enable for Message Masking + //// If 1, PRNG advances to create 64-bit PRN. This input is used to mask + //// the message fed into SHA3 (Keccak). + input msg_mask_en_i, + output logic [MsgWidth-1:0] msg_mask_o, + + //// SW update of seed + input seed_update_i, + input [31:0] seed_data_i, + + //// SW may initiate manual EDN seed refresh + input entropy_refresh_req_i, + + //// Timer limit value + //// If value is 0, timer is disabled + input [TimerPrescalerW-1:0] wait_timer_prescaler_i, + input [EdnWaitTimerW-1:0] wait_timer_limit_i, + + // Status out + //// Hash Ops counter. Count how many hashing ops (KMAC) have run + //// after the clear request from SW + output logic [HashCntW-1:0] hash_cnt_o, + input hash_cnt_clr_i, + input [HashCntW-1:0] hash_threshold_i, + + output caliptra_prim_mubi_pkg::mubi4_t entropy_configured_o, + + // Life cycle + input caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_t caliptra_ss_lc_escalate_en_i, + + // Error output + output err_t err_o, + output logic sparse_fsm_error_o, + output logic count_error_o, + input err_processed_i +); + + ///////////////// + // Definitions // + ///////////////// + + // Timer Widths are defined in kmac_pkg + + // Encoding generated with: + // $ ./util/design/sparse-fsm-encode.py -d 3 -m 9 -n 10 \ + // -s 507672272 --language=sv + // + // Hamming distance histogram: + // + // 0: -- + // 1: -- + // 2: -- + // 3: ||||||||||| (13.89%) + // 4: ||||||||||||||| (19.44%) + // 5: |||||||||||||||||||| (25.00%) + // 6: ||||||||||||||| (19.44%) + // 7: ||||||||||| (13.89%) + // 8: |||| (5.56%) + // 9: || (2.78%) + // 10: -- + // + // Minimum Hamming distance: 3 + // Maximum Hamming distance: 9 + // Minimum Hamming weight: 2 + // Maximum Hamming weight: 7 + // + localparam int StateWidth = 10; + + // States + typedef enum logic [StateWidth-1:0] { + // Reset: Reset state. The entropy is not ready. The state machine should + // get new entropy from EDN or the seed should be feeded by the software. + StRandReset = 10'b1001111000, + + // The seed is fed into PRNG and the entropy is ready. It means the + // rand_valid is asserted with valid data. It takes a few steps to reach + // this state from StRandReset. + StRandReady = 10'b0110000100, + + // EDN interface: Send request and receive + // RandEdnReq state can be transit from StRandReset or from StRandReady + // + // Reset --> EdnReq: + // If entropy source module is ready, the software sets a bit in CFG + // also sets the entropy mode to EdnMode. Then this FSM moves to EdnReq + // to initialize PRNG seed. + // + // Ready --> EdnReq: + // 1. If a mode is configured as to update entropy everytime it is + // consumed, then the FSM moves from Ready to EdnReq to refresh seed + // 2. If the software enabled EDN timer and the timer is expired and + // also the KMAC is processing the key block, the FSM moves to + // EdnReq to refresh seed + // 3. If a KMAC operation is completed, the FSM also refreshes the PRNG + // seed to prepare next KMAC op or wipe out operation. + StRandEdn = 10'b1100100111, + + // Sw Seed: If mode is set to manual mode, This entropy module needs initial + // seed from the software. It waits the seed update signal to expand initial + // entropy + StSwSeedWait = 10'b1011110110, + + // Generate: In this state, the entropy generator advances the PRNG to + // generate the 800-bits of pseudo random data for the next evaluation. + StRandGenerate = 10'b0000001100, + + // ErrWaitExpired: If Edn timer expires, FSM moves to this state and wait + // the software response. Software should switch to manual mode then disable + // the timer (to 0) and update the seed via register interface. + StRandErrWaitExpired = 10'b0001100011, + + // ErrNoValidMode: If SW sets entropy ready but the mode is not either + // Manual Mode nor EdnMode, this logic reports to SW with + // NoValidEntropyMode. + StRandErrIncorrectMode = 10'b1110010000, + + // Err: After the error is reported, FSM sits in Err state ignoring all the + // requests. It does not generate new entropy and drops the entropy valid + // signal. + // + // SW sets err_processed signal to clear the error. The software should + // clear the entropy ready signal before clear the error interrupt so that + // the FSM sits in StRandReset state not moving forward with incorrect + // configurations. + StRandErr = 10'b1000011110, + + StTerminalError = 10'b0010011000 + } rand_st_e; + + ///////////// + // Signals // + ///////////// + + // Timers + // "Wait Timer": This timer is in active when FSM sends entropy request to EDN + // If EDN does not return the entropy data until the timer expired, FSM + // moves to error state and report the error to the system. + + localparam int unsigned TimerW = EdnWaitTimerW; + logic timer_enable, timer_update, timer_expired, timer_pulse; + logic [TimerW-1:0] timer_limit; + logic [TimerW-1:0] timer_value; + + localparam int unsigned PrescalerW = TimerPrescalerW; + logic [PrescalerW-1:0] prescaler_cnt; + + // PRNG primitive + // SW configures to use EDN or ENTROPY_SEED register as PRNG seed + logic seed_en, seed_done; + logic seed_req, seed_ack; + logic [edn_pkg::ENDPOINT_BUS_WIDTH-1:0] seed; + logic prng_en; + logic [EntropyOutputW-1:0] prng_data, prng_data_permuted; + + // Buffer stage to prevent glitches happening inside the PRNG itself from + // propagating into the masked processing core. + logic [EntropyOutputW-1:0] rand_data_q; + logic data_update; + + // Auxliliary randomness + logic aux_rand_d, aux_rand_q; + logic aux_update; + + // Randomness for controlling PRNG updates. This only matters for clock cycles + // where the PRNG output is not actually used. + logic [3:0] prng_en_rand_d, prng_en_rand_q; + + // Entropy valid signal + // FSM set and clear the valid signal, rand_consume signal clear the valid + // signal. Split the set, clear to make entropy valid while FSM is processing + // other tasks. + logic rand_valid_set, rand_valid_clear; + + // FSM latches the mode and stores into mode_q when the FSM is out from + // StReset. The following states, or internal datapath uses mode_q after that. + // If the SW wants to change the mode, it requires resetting the IP. + logic mode_latch; + entropy_mode_e mode_q; + + // Status out: entropy configured + caliptra_prim_mubi_pkg::mubi4_t entropy_configured; + + // Internal entropy request signals. + logic entropy_req; + logic entropy_req_hold_d, entropy_req_hold_q; + + ////////////// + // Datapath // + ////////////// + + // For latching (`wait_timer_limit_i` != 0) during last `timer_update` + // See #16716 + logic non_zero_wait_timer_limit; + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + non_zero_wait_timer_limit <= '0; + end else if (timer_update) begin + non_zero_wait_timer_limit <= |wait_timer_limit_i; + end + end + + logic [TimerPrescalerW-1:0] wait_timer_prescaler_d; + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + wait_timer_prescaler_d <= '0; + end else if (timer_update) begin + wait_timer_prescaler_d <= wait_timer_prescaler_i; + end + end + + // Timers =================================================================== + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + timer_value <= '0; + end else if (timer_update) begin + timer_value <= timer_limit; + end else if (timer_expired) begin + timer_value <= '0; // keep the value + end else if (timer_enable && timer_pulse && |timer_value) begin // if non-zero timer v + timer_value <= timer_value - 1'b 1; + end + end + + assign timer_limit = TimerW'(wait_timer_limit_i); + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + timer_expired <= 1'b 0; + end else if (timer_update) begin + timer_expired <= 1'b 0; + end else if (timer_enable && (timer_value == '0)) begin + timer_expired <= 1'b 1; + end + end + + // Prescaler + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + prescaler_cnt <= '0; + end else if (timer_update) begin + prescaler_cnt <= wait_timer_prescaler_i; + end else if (timer_enable && prescaler_cnt == '0) begin + prescaler_cnt <= wait_timer_prescaler_d; + end else if (timer_enable) begin + prescaler_cnt <= prescaler_cnt - 1'b 1; + end + end + + assign timer_pulse = (timer_enable && prescaler_cnt == '0); + // Timers ------------------------------------------------------------------- + + // Hash Counter + logic threshold_hit; + logic threshold_hit_q, threshold_hit_clr; // latched hit + + logic hash_progress_d, hash_progress_q; + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) hash_progress_q <= 1'b 0; + else hash_progress_q <= hash_progress_d; + end + + assign hash_progress_d = in_keyblock_i; + + logic hash_cnt_clr; + assign hash_cnt_clr = hash_cnt_clr_i || threshold_hit || entropy_refresh_req_i; + + logic hash_cnt_en; + assign hash_cnt_en = hash_progress_q && !hash_progress_d; + + logic hash_count_error; + + // SEC_CM CTR.REDUN + // This primitive is used to place a hardened counter + caliptra_prim_count #( + .Width(HashCntW) + ) u_hash_count ( + .clk_i, + .rst_ni, + .clr_i(hash_cnt_clr), + .set_i(1'b0), + .set_cnt_i(HashCntW'(0)), + .incr_en_i(hash_cnt_en), + .decr_en_i(1'b0), + .step_i(HashCntW'(1)), + .commit_i(1'b1), + .cnt_o(hash_cnt_o), + .cnt_after_commit_o(), + .err_o(hash_count_error) + ); + + assign threshold_hit = |hash_threshold_i && (hash_threshold_i <= hash_cnt_o); + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) threshold_hit_q <= 1'b 0; + else if (threshold_hit_clr) threshold_hit_q <= 1'b 0; + else if (threshold_hit) threshold_hit_q <= 1'b 1; + end + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) mode_q <= EntropyModeNone; + else if (mode_latch) mode_q <= mode_i; + end + + // PRNG primitive =========================================================== + + `CALIPTRA_ASSERT_KNOWN(ModeKnown_A, mode_i) + assign seed = (mode_q == EntropyModeSw) ? seed_data_i : entropy_data_i; + + // We employ a single unrolled Bivium stream cipher primitive to generate + // 800 bits per clock cycle. + // caliptra_prim_trivium #( + // .BiviumVariant (1), + // .OutputWidth (EntropyOutputW), + // .StrictLockupProtection(1), + // .SeedType (caliptra_prim_trivium_pkg::SeedTypeStatePartial), + // .PartialSeedWidth (edn_pkg::ENDPOINT_BUS_WIDTH), + // .RndCnstTriviumLfsrSeed(RndCnstLfsrSeed) + // ) u_caliptra_prim_trivium ( + // .clk_i (clk_i), + // .rst_ni(rst_ni), + + // .en_i (prng_en || msg_mask_en_i), + // .allow_lockup_i ('0), // Not used. + // .seed_en_i (seed_en), + // .seed_done_o (seed_done), + // .seed_req_o (seed_req), + // .seed_ack_i (seed_ack), + // .seed_key_i ('0), // Not used. + // .seed_iv_i ('0), // Not used. + // .seed_state_full_i ('0), // Not used. + // .seed_state_partial_i(seed), + + // .key_o(prng_data), + // .err_o() + // ); + assign prng_data = '0; + + // Add a permutation layer to obfuscate the output of the PRNG primitive. + for (genvar i = 0; i < EntropyOutputW; i++) begin : gen_perm + assign prng_data_permuted[i] = prng_data[RndCnstLfsrPerm[i]]; + end + + // Buffer stage to prevent glitches happening inside the PRNG primitive from + // propagating into the masked processing core. + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + rand_data_q <= RndCnstBufferLfsrSeed; + end else if (data_update || msg_mask_en_i) begin + rand_data_q <= prng_data_permuted; + end + end + + // Forwrad LSBs for masking the message. + assign msg_mask_o = rand_data_q[MsgWidth-1:0]; + + // PRNG primitive ---------------------------------------------------------- + + // Auxiliary randomness ===================================================== + assign aux_rand_d = aux_update ? rand_data_q[EntropyOutputW - 1] : + aux_rand_q; + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + aux_rand_q <= '0; + end else begin + aux_rand_q <= aux_rand_d; + end + end + + // Auxiliary randomness ----------------------------------------------------- + + // PRNG enable randomness =================================================== + assign prng_en_rand_d = + aux_update ? rand_data_q[EntropyOutputW - 2 -: 4] : // refresh + {1'b0, prng_en_rand_q[3:1]}; // shift out + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + prng_en_rand_q <= '0; + end else begin + prng_en_rand_q <= prng_en_rand_d; + end + end + + // PRNG enable randomness --------------------------------------------------- + + // Randomness outputs ======================================================= + assign rand_data_o = rand_data_q; + assign rand_aux_o = aux_rand_q; + + // entropy valid + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + rand_valid_o <= 1'b 0; + end else if (rand_valid_set) begin + rand_valid_o <= 1'b 1; + end else if (rand_valid_clear) begin + rand_valid_o <= 1'b 0; + end + end + + // Let consumers know that the randomness will be valid in the next clock cycle. + assign rand_early_o = rand_valid_set; + + // The Keccak core is not supposed to ever consume randomness unless it's marked + // as valid. The only exception is if the reseeding of the PRNG just finished + // in the previous clock cycle. Because it's possible for the randomness to stay + // valid throughout the reseeding (the valid is for sure de-asserted at the end). + // The Keccak core may base its decision to start processing / consuming entropy + // before the valid is de-asserted. If this happens, the current buffer output + // might be used for both remasking and as auxiliary randomness which isn't ideal + // but given this happens only very rarely it should be okay. + `CALIPTRA_ASSUME(ConsumeNotAssertWhenNotValid_M, + rand_update_i | rand_consumed_i |-> rand_valid_o || $past(seed_done)) + + // Upon escalation or in case the EDN wait timer expires the entropy_req signal + // can be dropped before getting acknowledged. This may leave EDN in a strange + // state. We thus hold the request until it's actually acknowledged. In case the + // request is acknowledged while the FSM is in the StRandErr already, the + // incoming entropy is simply dropped. + assign entropy_req_o = entropy_req | entropy_req_hold_q; + assign entropy_req_hold_d = (entropy_req_hold_q | entropy_req) & ~entropy_ack_i; + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + entropy_req_hold_q <= '0; + end else begin + entropy_req_hold_q <= entropy_req_hold_d; + end + end + + // Randomness outputs ------------------------------------------------------- + + // Remaining outputs + assign count_error_o = hash_count_error; + + /////////////////// + // State Machine // + /////////////////// + + rand_st_e st, st_d; + + // State FF + `CALIPTRA_PRIM_FLOP_SPARSE_FSM(u_state_regs, st_d, st, rand_st_e, StRandReset) + + // State: Next State and Output Logic + // SEC_CM: FSM.SPARSE + always_comb begin + st_d = st; + sparse_fsm_error_o = 1'b 0; + + // Default Timer values + timer_enable = 1'b 0; + timer_update = 1'b 0; + + threshold_hit_clr = 1'b 0; + + // rand is valid when this logic expands the entropy. + // FSM sets the valid signal, the signal is cleared by `consume` signal + // or FSM clear signal. + // Why split the signal to set and clear? + // FSM only set the signal to make entropy valid while processing other + // tasks such as EDN request. + rand_valid_set = 1'b 0; + rand_valid_clear = 1'b 0; + + // mode_latch to store mode_i into mode_q + mode_latch = 1'b 0; + + // PRNG reseed handling + seed_en = 1'b 0; + seed_ack = 1'b 0; + entropy_req = 1'b 0; + + // Randomness control signals + prng_en = 1'b 0; + data_update = 1'b 0; + aux_update = 1'b 0; + + // Error + err_o = '{valid: 1'b 0, code: ErrNone, info: '0}; + + unique case (st) + StRandReset: begin + if (entropy_ready_i) begin + + // As SW ready, discard current dummy entropy and refresh. + rand_valid_clear = 1'b 1; + + mode_latch = 1'b 1; + // SW has configured KMAC + unique case (mode_i) + EntropyModeSw: begin + // Start reseeding the PRNG via ENTROPY_SEED CSR. + seed_en = 1'b 1; + st_d = StSwSeedWait; + end + + EntropyModeEdn: begin + // Start reseeding the PRNG via EDN. + seed_en = 1'b 1; + st_d = StRandEdn; + + // Timer reset + timer_update = 1'b 1; + end + + default: begin + // EntropyModeNone or other values + // Error. No valid mode given, report to SW + st_d = StRandErrIncorrectMode; + end + endcase + end else begin + st_d = StRandReset; + + // Setting the dummy rand gate until SW prepares. + // This lets the Application Interface move forward out of reset + // without SW intervention. + rand_valid_set = 1'b 1; + end + end + + StRandReady: begin + timer_enable = 1'b 1; // If limit is zero, timer won't work + + prng_en = prng_en_rand_q[0]; + + if ((rand_update_i || rand_consumed_i) && + ((fast_process_i && in_keyblock_i) || !fast_process_i)) begin + // If fast_process is set, don't clear the rand valid, even + // consumed. So, the logic does not expand the entropy again. + // If fast_process is not set, then every rand_consume signal + // triggers rand expansion. + prng_en = 1'b 1; + data_update = 1'b 1; + + if (rand_consumed_i) begin + st_d = StRandGenerate; + + rand_valid_clear = 1'b 1; + end else begin + st_d = StRandReady; + end + end else if ((mode_q == EntropyModeEdn) && + (entropy_refresh_req_i || threshold_hit_q)) begin + // Start reseeding the PRNG via EDN. + seed_en = 1'b 1; + st_d = StRandEdn; + + // Timer reset + timer_update = 1'b 1; + + // Clear the threshold as it refreshes the hash + threshold_hit_clr = 1'b 1; + end else begin + st_d = StRandReady; + end + end + + StRandEdn: begin + // Forward request of PRNG primitive. + entropy_req = seed_req; + + // Wait timer + timer_enable = 1'b 1; + + if (timer_expired && non_zero_wait_timer_limit) begin + // If timer count is non-zero and expired; + st_d = StRandErrWaitExpired; + + end else if (entropy_req_o && entropy_ack_i) begin + seed_ack = 1'b 1; + + if (seed_done) begin + st_d = StRandGenerate; + + if ((fast_process_i && in_keyblock_i) || !fast_process_i) begin + prng_en = 1'b 1; + data_update = 1'b 1; + rand_valid_clear = 1'b 1; + end + end else begin + st_d = StRandEdn; + end + end else if ((rand_update_i || rand_consumed_i) && + ((fast_process_i && in_keyblock_i) || !fast_process_i)) begin + // Somehow, while waiting the EDN entropy, the KMAC or SHA3 logic + // consumed the remained entropy. This can happen when the previous + // SHA3/ KMAC op completed and this Entropy FSM has moved to this + // state to refresh the entropy and the SW initiates another hash + // operation while waiting for the EDN response. + st_d = StRandEdn; + + prng_en = 1'b 1; + data_update = 1'b 1; + rand_valid_clear = rand_consumed_i; + end else begin + st_d = StRandEdn; + end + end + + StSwSeedWait: begin + // Forward ack driven by software. + seed_ack = seed_req & seed_update_i; + + if (seed_done) begin + st_d = StRandGenerate; + + prng_en = 1'b 1; + data_update = 1'b 1; + + rand_valid_clear = 1'b 1; + end else begin + st_d = StSwSeedWait; + end + end + + StRandGenerate: begin + // The current buffer output is used as auxiliary randomness and - + // depending on whether keccak_round is parametrized to always forward + // the buffer output and not use intermediate randomness - forwarded + // to the DOM multipliers without them updating in this cycle. We don't + // need to advance the PRNG as there is no risk of accidentally + // re-using the same randomness twice since after the current cycle: + // - We either load and re-mask the message/key which will use + // different PRNG output bits. The PRNG is advanced once per 64 bits + // loaded. + // - Or, the Keccak/SHA3 core is operated but it always starts with + // the linear layers which don't require fresh randomness. While + // processing the linear layers, the PRNG is advanced to have fresh + // randomness for the non-linear layer requiring it. + aux_update = 1'b 1; + rand_valid_set = 1'b 1; + prng_en = prng_en_rand_q[0]; + + st_d = StRandReady; + end + + StRandErrWaitExpired: begin + st_d = StRandErr; + + err_o = '{ valid: 1'b 1, + code: ErrWaitTimerExpired, + info: 24'(timer_value) + }; + end + + StRandErrIncorrectMode: begin + st_d = StRandErr; + + err_o = '{ valid: 1'b 1, + code: ErrIncorrectEntropyMode, + info: 24'(mode_q) + }; + end + + StRandErr: begin + // Keep entropy signal valid to complete current hashing even with error + rand_valid_set = 1'b 1; + + // Advance the PRNG after the entropy has been used. + prng_en = (rand_update_i | rand_consumed_i) & + ((fast_process_i & in_keyblock_i) | ~fast_process_i); + data_update = prng_en; + + if (err_processed_i) begin + st_d = StRandReset; + + end else begin + st_d = StRandErr; + end + + end + + StTerminalError: begin + // this state is terminal + st_d = st; + sparse_fsm_error_o = 1'b 1; + end + + default: begin + st_d = StTerminalError; + sparse_fsm_error_o = 1'b 1; + end + endcase + + // SEC_CM: FSM.GLOBAL_ESC, FSM.LOCAL_ESC + // Unconditionally jump into the terminal error state + // if the life cycle controller triggers an escalation. + if (caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_test_true_loose(caliptra_ss_lc_escalate_en_i)) begin + st_d = StTerminalError; + end + end + `CALIPTRA_ASSERT_KNOWN(RandStKnown_A, st) + + // mubi4 sender + + assign entropy_configured = (st != StRandReset) + ? caliptra_prim_mubi_pkg::MuBi4True + : caliptra_prim_mubi_pkg::MuBi4False ; + caliptra_prim_mubi4_sender #( + .AsyncOn(1'b0) + ) u_entropy_configured ( + .clk_i, + .rst_ni, + + .mubi_i (entropy_configured ), + .mubi_o (entropy_configured_o) + ); + + //////////////// + // Assertions // + //////////////// + + // The EDN bus width needs to be equal to the width of the ENTROPY_SEED + // register as this module doesn't perform width adaption. + `CALIPTRA_ASSERT_INIT(EdnBusWidth_A, edn_pkg::ENDPOINT_BUS_WIDTH == 32) + +// the code below is not meant to be synthesized, +// but it is intended to be used in simulation and FPV +`ifndef SYNTHESIS + // Check that the supplied permutations are valid. + logic [EntropyOutputW-1:0] perm_test; + initial begin : p_perm_check + perm_test = '0; + for (int k = 0; k < EntropyOutputW; k++) begin + perm_test[RndCnstLfsrPerm[k]] = 1'b1; + end + // All bit positions must be marked with 1. + `CALIPTRA_ASSERT_I(PermutationCheck_A, &perm_test) + end +`endif + +endmodule : kmac_entropy diff --git a/src/caliptra_ss_lc_ctrl/rtl/kmac_errchk.sv b/src/caliptra_ss_lc_ctrl/rtl/kmac_errchk.sv new file mode 100644 index 0000000..520a34b --- /dev/null +++ b/src/caliptra_ss_lc_ctrl/rtl/kmac_errchk.sv @@ -0,0 +1,464 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// KMAC Error Checking logic +// +// `kmac_err` module checks the SW introduced errors. +// 1. SW command sequencing error. +// 2. SW configuration error. +// +// ## SW Command Sequencing Error +// +// KMAC assumes the application interface and the SW register interface to +// follow the specific sequence. It expects the requester to send the `Start` +// command then push the message body. The `Process` command follows the message +// body. The SW may issue `Run` command if it needs the digest result more than +// a block rate. Then SW completes the hash operation with `Done` command. +// +// This `kmac_err` module checks if the SW issues the correct command. If not, +// it reports the error via ERR_CODE register. +// +// However, the logic does not prevent the error-ed command to be propagated. +// The unexpected commands are filtered by each individual submodule. +// +// st := { Idle, MsgFeed, Processing, Absorbed, Squeeze} +// +// allowed := { +// Idle : { Start }, +// MsgFeed: { Process }, +// Processing: { None }, +// Absorbed: { Run, Done }, +// Squeeze: { None } +// } +// +// ## SW Configuration Error +// +// `kmac_errchk` module checks if SW configured correct combinations of the +// configuration registers when the hashing operation begins. +// +// 1. Mode & Strength combinations +// 2. Kmac Prefix +// * sideload & key_valid -> Checker in kmac_core + +`include "caliptra_prim_assert.sv" + +module kmac_errchk + import kmac_pkg::*; + import sha3_pkg::sha3_mode_e; + import sha3_pkg::keccak_strength_e; +#( + parameter bit EnMasking = 1'b 1 +) ( + input clk_i, + input rst_ni, + + // Configurations + input sha3_mode_e cfg_mode_i, + input keccak_strength_e cfg_strength_i, + + input kmac_en_i, + input [47:0] cfg_prefix_6B_i, // first 6B of PREFIX + + // If the signal below is set, errchk propagates the command to the rest of + // the blocks even with err_modestrength. + input cfg_en_unsupported_modestrength_i, + + // Entropy Ready Status to check if SW initiated the hahs without entropy cfg + input entropy_ready_pulse_i, + + // SW commands: Only valid command is sent out to the rest of the modules + input kmac_cmd_e sw_cmd_i, + output kmac_cmd_e sw_cmd_o, + + // Status from KMAC_APP + input app_active_i, + + // Status from SHA3 core + input caliptra_prim_mubi_pkg::mubi4_t sha3_absorbed_i, + input keccak_done_i, + + // Life cycle + input caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_t caliptra_ss_lc_escalate_en_i, + + // Error processed indicator + input err_processed_i, + + input caliptra_prim_mubi_pkg::mubi4_t clear_after_error_i, + + output err_t error_o, + output logic sparse_fsm_error_o +); + + // sha3_pkg::sha3_mode_e + import sha3_pkg::L128; + import sha3_pkg::L224; + import sha3_pkg::L256; + import sha3_pkg::L384; + import sha3_pkg::L512; + + // sha3_pkg::keccak_strength_e + import sha3_pkg::Sha3; + import sha3_pkg::Shake; + import sha3_pkg::CShake; + + ///////////////// + // Definitions // + ///////////////// + // Encoding generated with: + // $ ./util/design/sparse-fsm-encode.py -d 3 -m 5 -n 6 \ + // -s 2239170217 --language=sv + // + // Hamming distance histogram: + // + // 0: -- + // 1: -- + // 2: -- + // 3: |||||||||||||||||||| (50.00%) + // 4: |||||||||||||||| (40.00%) + // 5: |||| (10.00%) + // 6: -- + // + // Minimum Hamming distance: 3 + // Maximum Hamming distance: 5 + // Minimum Hamming weight: 2 + // Maximum Hamming weight: 4 + // + localparam int StateWidth = 6; + typedef enum logic [StateWidth-1:0] { + StIdle = 6'b001101, + StMsgFeed = 6'b110001, + StProcessing = 6'b010110, + StAbsorbed = 6'b100010, + StSqueezing = 6'b111100, + StTerminalError = 6'b011011 + } st_e; + st_e st, st_d; + + localparam int StateWidthL = 3; + typedef enum logic [StateWidthL-1:0] { + StIdleL, + StMsgFeedL, + StProcessingL, + StAbsorbedL, + StSqueezingL, + StErrorL + } st_logical_e; + st_logical_e stL; + + + ///////////// + // Signals // + ///////////// + + // `err_swsequence` occurs when SW issues wrong command + logic err_swsequence; + + // `err_modestrength` occcurs when Mode & Strength combinations are not + // allowed. This error does not block the hashing operation. + // UnexpectedModeStrength may stop the processing based on CFG + // The error raises when SW issues CmdStart. + logic err_modestrength; + + // `err_prefix` occurs when the first 6B of !!PREFIX is not + // `encode_string("KMAC")` and kmac is enabled. This error does not block the + // KMAC operation. + logic err_prefix; + + // `err_entropy_ready` occurs when SW initiated the hashing op. without + // configuring the entropy. This error may happen only when EnMasking is + // set. + logic err_entropy_ready; + + // entropy_ready is a pulse signal. Logic needs to store the state. + logic cfg_entropy_ready; + + // Signal to block the SW command propagation + logic block_swcmd; + + /////////////////// + // Error Checker // + /////////////////// + + // SW sequence Error + // info field: Current state, Received command + // SEC_CM: FSM.SPARSE + always_comb begin + err_swsequence = 1'b 0; + sparse_fsm_error_o = 1'b 0; + + unique case (st) + StIdle: begin + // Allow Start command only + if (!(sw_cmd_i inside {CmdNone, CmdStart})) begin + err_swsequence = 1'b 1; + end + end + + StMsgFeed: begin + // Allow Process only + if (!(sw_cmd_i inside {CmdNone, CmdProcess})) begin + err_swsequence = 1'b 1; + end + end + + StProcessing: begin + if (sw_cmd_i != CmdNone) begin + err_swsequence = 1'b 1; + end + end + + StAbsorbed: begin + // Allow ManualRun and Done + if (!(sw_cmd_i inside {CmdNone, CmdManualRun, CmdDone})) begin + err_swsequence = 1'b 1; + end + end + + StSqueezing: begin + if (sw_cmd_i != CmdNone) begin + err_swsequence = 1'b 1; + end + end + + StTerminalError: begin + err_swsequence = 1'b 0; + sparse_fsm_error_o = 1'b 1; + end + + default: begin + err_swsequence = 1'b 0; + sparse_fsm_error_o = 1'b 1; + end + endcase + end + + assign block_swcmd = (err_swsequence) + || (err_modestrength + && !cfg_en_unsupported_modestrength_i) + || err_entropy_ready; + + // sw_cmd_o latch + // To reduce the command path delay, sw_cmd is latched here + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) sw_cmd_o <= CmdNone; + else if (!block_swcmd) sw_cmd_o <= sw_cmd_i; + end + + // Mode & Strength + always_comb begin : check_modestrength + err_modestrength = 1'b 0; + + if (st == StIdle && st_d == StMsgFeed) begin + // When moving to the next stage, checks the config + if (!((cfg_mode_i == Sha3 && + cfg_strength_i inside {L224, L256, L384, L512}) || + ((cfg_mode_i == Shake || cfg_mode_i == CShake) && + (cfg_strength_i inside {L128, L256})))) begin + err_modestrength = 1'b 1; + end + end + end : check_modestrength + + + // Check prefix 6B is `encode_string("KMAC")` + always_comb begin : check_prefix + err_prefix = 1'b 0; + + if (st == StIdle && st_d == StMsgFeed && kmac_en_i) begin + if (cfg_prefix_6B_i != EncodedStringKMAC) begin + err_prefix = 1'b 1; + end + end + end : check_prefix + + if (EnMasking) begin : g_entropy_chk + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) cfg_entropy_ready <= 1'b 0; + else if (err_processed_i) cfg_entropy_ready <= 1'b 0; + else if (entropy_ready_pulse_i && st == StIdle) begin + cfg_entropy_ready <= 1'b 1; + end + end + + always_comb begin : check_entropy_ready + err_entropy_ready = 1'b 0; + + if (st == StIdle && st_d == StMsgFeed && kmac_en_i) begin + if (!cfg_entropy_ready) begin + err_entropy_ready = 1'b 1; + end + end + end : check_entropy_ready + + end else begin : g_pseudo_entropy_chk + + // If EnMasking is 0, entropy module is not generated. + // tying the error signal to 0. + assign err_entropy_ready = 1'b 0; + + assign cfg_entropy_ready = 1'b 1; + + logic unused_cfg_entropy_ready; + assign unused_cfg_entropy_ready = cfg_entropy_ready; + + end + + always_comb begin : recode_st + unique case (st) + StIdle : stL = StIdleL; + StMsgFeed : stL = StMsgFeedL; + StProcessing : stL = StProcessingL; + StAbsorbed : stL = StAbsorbedL; + StSqueezing : stL = StSqueezingL; + default : stL = StErrorL; + endcase + end : recode_st + + // Return error code + err_t err; + always_comb begin : err_return + err = '{valid: 1'b0, code: ErrNone, info: '0}; + + priority case (1'b 1) + err_swsequence: begin + err = '{ valid: 1'b 1, + code: ErrSwCmdSequence, + info: {5'h0, + {err_swsequence, err_modestrength, err_prefix}, + {5'h 0, stL}, + {2'b0, sw_cmd_i} + } + }; + end + + err_modestrength: begin + err = '{ valid: 1'b 1, + code: ErrUnexpectedModeStrength, + info: { 5'h 0, + {err_swsequence, err_modestrength, err_prefix}, + 8'h 0, + {2'b 00, cfg_mode_i}, + {1'b 0, cfg_strength_i} + } + }; + end + + err_prefix: begin + err = '{ valid: 1'b 1, + code: ErrIncorrectFunctionName, + info: { 5'h 0, + {err_swsequence, err_modestrength, err_prefix}, + 16'h 0000 + } + }; + end + + err_entropy_ready: begin + err = '{ valid: 1'b 1, + code: ErrSwHashingWithoutEntropyReady, + info: { 8'({ err_entropy_ready, + err_swsequence, + err_modestrength, + err_prefix}), + 16'({kmac_en_i, cfg_entropy_ready}) + } + }; + end + + default: begin + err = '{valid: 1'b0, code: ErrNone, info: '0}; + end + endcase + end : err_return + + assign error_o = err; + + // If below failed, revise err_swsequence error response info field. + `CALIPTRA_ASSERT_INIT(ExpectedStSwCmdBits_A, $bits(st) == StateWidth && $bits(sw_cmd_i) == 6) + + // If failed, revise err_modestrength error info field. + `CALIPTRA_ASSERT_INIT(ExpectedModeStrengthBits_A, + $bits(cfg_mode_i) == 2 && $bits(cfg_strength_i) == 3) + + + /////////////////// + // State Machine // + /////////////////// + st_e st_gated_d; + + `CALIPTRA_PRIM_FLOP_SPARSE_FSM(u_state_regs, st_gated_d, st, st_e, StIdle) + + // ICEBOX(#14631): Move block_swcmd to PRIM_FLOP_SPARSE_FSM() + // + // It would be better to place this condition (block_swcmd) in `always_ff` + // block to clearly indicate the clock gating condition. However, the + // statemachine uses the sparse encoding scheme and macro. It prevents any + // latch enable signals. + assign st_gated_d = (block_swcmd) ? st : st_d ; + + always_comb begin : next_state + st_d = st; + + unique case (st) + StIdle: begin + if (!app_active_i && sw_cmd_i == CmdStart) begin + // Proceed to the next state only when the SW issues the Start command + // in a valid period. + st_d = StMsgFeed; + end + end + + StMsgFeed: begin + if (sw_cmd_i == CmdProcess) begin + st_d = StProcessing; + end + end + + StProcessing: begin + if (caliptra_prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed_i)) begin + st_d = StAbsorbed; + end + end + + StAbsorbed: begin + if (sw_cmd_i == CmdManualRun) begin + st_d = StSqueezing; + end else if (sw_cmd_i == CmdDone) begin + st_d = StIdle; + end + end + + StSqueezing: begin + if (keccak_done_i) begin + st_d = StAbsorbed; + end + end + + StTerminalError: begin + // this state is terminal + st_d = st; + end + + default: begin + // this state is terminal + st_d = StTerminalError; + end + endcase + + // SEC_CM: FSM.GLOBAL_ESC, FSM.LOCAL_ESC + // Unconditionally jump into the terminal error state + // if the life cycle controller triggers an escalation. + if (caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_test_true_loose(caliptra_ss_lc_escalate_en_i)) begin + st_d = StTerminalError; + end + + if (st_d != StTerminalError && + caliptra_prim_mubi_pkg::mubi4_test_true_strict(clear_after_error_i)) begin + st_d = StIdle; + end + end : next_state + `CALIPTRA_ASSERT_KNOWN(StKnown_A, st) + +endmodule : kmac_errchk diff --git a/src/caliptra_ss_lc_ctrl/rtl/kmac_msgfifo.sv b/src/caliptra_ss_lc_ctrl/rtl/kmac_msgfifo.sv new file mode 100644 index 0000000..f766324 --- /dev/null +++ b/src/caliptra_ss_lc_ctrl/rtl/kmac_msgfifo.sv @@ -0,0 +1,281 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// KMAC MSG_FIFO +// +// This module converts TL-UL interface into MSG_FIFO interface used in KMAC. + +`include "caliptra_prim_assert.sv" + +module kmac_msgfifo + import kmac_pkg::*; +#( + // OutWidth is MsgFIFO data width. caliptra_prim_packer converts InW to OutW prior to + // pushing to MsgFIFO + parameter int OutWidth = 64, + + parameter bit EnMasking = 1'b 1, + + // Internal MsgFIFO Entry count + parameter int MsgDepth = 9, + localparam int MsgDepthW = $clog2(MsgDepth+1) // derived parameter +) ( + input clk_i, + input rst_ni, + + // from REG or KeyMgr Intf input + input fifo_valid_i, + input [OutWidth-1:0] fifo_data_i, + input [OutWidth-1:0] fifo_mask_i, + output fifo_ready_o, + + // MSG interface + output logic msg_valid_o, + output logic [OutWidth-1:0] msg_data_o, + output logic [OutWidth/8-1:0] msg_strb_o, + input msg_ready_i, + + output logic fifo_empty_o, + output logic fifo_full_o, + output logic [MsgDepthW-1:0] fifo_depth_o, + + // Control + input caliptra_prim_mubi_pkg::mubi4_t clear_i, + + // process_i --> process_o + // process_o asserted after all internal messages are flushed out to MSG interface + input process_i, + output logic process_o, + + err_t err_o +); + + ///////////////// + // Definitions // + ///////////////// + typedef struct packed { + logic [OutWidth-1:0] data; + logic [OutWidth/8-1:0] strb; // one bit per byte + } fifo_t; + + typedef enum logic [1:0] { + // In Idle, it checks if process input received or not. + // If received, the signal goes to packer and flush internal pending data + FlushIdle, + + // In Packer state, it waits the packer flush operation completes. + // The flush_done signal do nothing but after this, it is assumed that + // MSG FIFO received the request. + FlushPacker, + + // In Fifo, it waits until MsgFifo is empty. Then asserts process_o + FlushFifo, + + // After flushing, it waits the done (clear) signal. It is assumed that + // no incoming messages are transmitted between `process_i` and `clear_i` + FlushClear + } flush_st_e; + + ///////////// + // Signals // + ///////////// + + // Packer write path + logic packer_wvalid; + logic [OutWidth-1:0] packer_wdata; + logic [OutWidth-1:0] packer_wmask; + logic packer_wready; + + // Message FIFO signals + logic fifo_wvalid; + fifo_t fifo_wdata; + logic fifo_wready; + logic fifo_rvalid; + fifo_t fifo_rdata; + logic fifo_rready; + + logic fifo_err; // FIFO dup. counter error + + // packer flush to msg_fifo, then msg_fifo empty out the internals + // then assert msgfifo_flush_done + logic packer_flush_done; + logic msgfifo_flush_done; + + logic packer_err; + + // SEC_CM: PACKER.CTR.REDUN + caliptra_prim_packer #( + .InW (OutWidth), + .OutW (OutWidth), + .HintByteData (1), + + // Turn on dup counter when EnMasking is set + .EnProtection (EnMasking) + ) u_packer ( + .clk_i, + .rst_ni, + + .valid_i (fifo_valid_i), + .data_i (fifo_data_i), + .mask_i (fifo_mask_i), + .ready_o (fifo_ready_o), + + .valid_o (packer_wvalid), + .data_o (packer_wdata), + .mask_o (packer_wmask), + .ready_i (packer_wready), + + .flush_i (process_i), + .flush_done_o (packer_flush_done), + + .err_o (packer_err) + ); + + // Assign packer wdata and wmask to FIFO struct + // In contrast to HMAC case, KMAC SHA3 operates in little-endian. MSG fifo is + // converted into 3-D form so the endianess here is not a problem. + assign fifo_wdata.data = packer_wdata; + always_comb begin + fifo_wdata.strb = '0; + for (int i = 0 ; i < OutWidth/8 ; i++) begin + fifo_wdata.strb[i] = packer_wmask[8*i]; + end + end + + // MsgFIFO + caliptra_prim_fifo_sync #( + .Width ($bits(fifo_t)), + .Pass (1'b 1), + .Depth (MsgDepth), + .Secure (EnMasking) + ) u_msgfifo ( + .clk_i, + .rst_ni, + .clr_i (caliptra_prim_mubi_pkg::mubi4_test_true_strict(clear_i)), + + .wvalid_i(fifo_wvalid), + .wready_o(fifo_wready), + .wdata_i (fifo_wdata), + + .rvalid_o (fifo_rvalid), + .rready_i (fifo_rready), + .rdata_o (fifo_rdata), + + .full_o (fifo_full_o), + .depth_o (fifo_depth_o), + .err_o (fifo_err) + + ); + + assign fifo_wvalid = packer_wvalid; + assign packer_wready = fifo_wready; + + assign msg_valid_o = fifo_rvalid; + assign fifo_rready = msg_ready_i; + assign msg_data_o = fifo_rdata.data; + assign msg_strb_o = fifo_rdata.strb; + + assign fifo_empty_o = !fifo_rvalid; + + // Flush (process from outside) handling + flush_st_e flush_st, flush_st_d; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + flush_st <= FlushIdle; + end else begin + flush_st <= flush_st_d; + end + end + + always_comb begin + flush_st_d = flush_st; + + msgfifo_flush_done = 1'b 0; + + unique case (flush_st) + FlushIdle: begin + if (process_i) begin + flush_st_d = FlushPacker; + end else begin + flush_st_d = FlushIdle; + end + end + + FlushPacker: begin + if (packer_flush_done) begin + flush_st_d = FlushFifo; + end else begin + flush_st_d = FlushPacker; + end + end + + FlushFifo: begin + if (fifo_empty_o) begin + flush_st_d = FlushClear; + + msgfifo_flush_done = 1'b 1; + end else begin + flush_st_d = FlushFifo; + end + end + + FlushClear: begin + if (caliptra_prim_mubi_pkg::mubi4_test_true_strict(clear_i)) begin + flush_st_d = FlushIdle; + end else begin + flush_st_d = FlushClear; + end + end + + default: begin + flush_st_d = FlushIdle; + end + endcase + end + + assign process_o = msgfifo_flush_done; + + // Error assign + always_comb begin : error_logic + err_o = '{ + valid: 1'b 0, + code: kmac_pkg::ErrNone, + info: '0 + }; + + // Priority case -> if .. else if + if (packer_err) begin + err_o = '{ + // If EnProtection is 0, packer_err is tied to 0 + valid: 1'b 1, + code: kmac_pkg::ErrPackerIntegrity, + info: kmac_pkg::ErrInfoW'(flush_st) + }; + end else if (fifo_err) begin + err_o = '{ + valid: 1'b 1, + code: kmac_pkg::ErrMsgFifoIntegrity, + info: kmac_pkg::ErrInfoW'(flush_st) + }; + end + end : error_logic + + //////////////// + // Assertions // + //////////////// + + // Flush state known checker + `CALIPTRA_ASSERT(FlushStInValid_A, flush_st inside {FlushIdle, FlushPacker, FlushFifo, FlushClear}) + + // Packer done signal is asserted at least one cycle later + `CALIPTRA_ASSERT(PackerDoneDelay_A, $onehot0({process_i, packer_flush_done})) + + // process_i not asserted during the flush operation + `CALIPTRA_ASSUME(PackerDoneValid_a, process_i |-> flush_st == FlushIdle) + + // No messages in between `process_i` and `clear_i` + `CALIPTRA_ASSUME(MessageValid_a, fifo_valid_i |-> flush_st == FlushIdle) + +endmodule diff --git a/src/caliptra_ss_lc_ctrl/rtl/kmac_pkg.sv b/src/caliptra_ss_lc_ctrl/rtl/kmac_pkg.sv new file mode 100644 index 0000000..fe92a60 --- /dev/null +++ b/src/caliptra_ss_lc_ctrl/rtl/kmac_pkg.sv @@ -0,0 +1,477 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// kmac_pkg + +package kmac_pkg; + parameter int MsgWidth = sha3_pkg::MsgWidth; + parameter int MsgStrbW = sha3_pkg::MsgStrbW; + + // Message FIFO depth + // + // Assume entropy is ready always (if Share is reused as an entropy in Chi) + // Then it takes 72 cycles to complete the Keccak round. While Keccak is in + // operation, the module need to store the incoming messages to not degrade + // the throughput. + // + // Based on the observation from HMAC case, the core usually takes 5 clocks + // to fetch data and store into KMAC. So the core can push at most 14.5 X 4B + // which is 58B. After that, Keccak can fetch the data from MSG_FIFO faster + // rate than the core can push. To fetch 58B, it takes around 7~8 cycles. + // For that time, the core only can push at most 2 DW. After that Keccak + // waits the incoming message. + // + // So Message FIFO doesn't need full block size except the KMAC case, which + // is delayed the operation by processing Function Name N, customization S, + // and secret keys. But KMAC doesn't need high throughput anyway (72Mb/s). + parameter int RegIntfWidth = 32; // 32bit interface + parameter int RegLatency = 5; // 5 cycle to write one Word + parameter int Sha3Latency = 72; // Expected masked sha3 processing time 24x3 + + // Total required buffer size while SHA3 is in processing + parameter int BufferCycles = (Sha3Latency + RegLatency - 1)/RegLatency; + parameter int BufferSizeBits = RegIntfWidth * BufferCycles; + + // Required MsgFifoDepth. Adding slightly more buffer for margin + parameter int MsgFifoDepth = 2 + ((BufferSizeBits + MsgWidth - 1)/MsgWidth); + parameter int MsgFifoDepthW = $clog2(MsgFifoDepth+1); + + parameter int MsgWindowWidth = 32; // Register width + parameter int MsgWindowDepth = 512; // 2kB space + + // Key related definitions + // If this value is changed, please modify the logic inside kmac_core + // that assigns the value into `encoded_key` + parameter int MaxKeyLen = 512; + + // size of encode_string(Key) + // $ceil($clog2(MaxKeyLen+1)/8) + parameter int MaxEncodedKeyLenW = $clog2(MaxKeyLen+1); + parameter int MaxEncodedKeyLenByte = (MaxEncodedKeyLenW + 8 - 1) / 8; + parameter int MaxEncodedKeyLenSize = MaxEncodedKeyLenByte * 8; + + // Secret Key left_encode(len(Key)) + // ---------- ------------------------ + parameter int MaxEncodedKeyW = MaxKeyLen + MaxEncodedKeyLenSize + 8; + + // key_len is SW configurable CSR. + // Current KMAC allows 5 key length options. + // This value determines the KMAC core how to map the value + // from Secret Key register to key size block + typedef enum logic [2:0] { + Key128 = 3'b 000, // 128 bit secret key + Key192 = 3'b 001, // 192 bit secret key + Key256 = 3'b 010, // 256 bit secret key + Key384 = 3'b 011, // 384 bit secret key + Key512 = 3'b 100 // 512 bit secret key + } key_len_e; + + + // SEC_CM: SW_CMD.CTRL.SPARSE + // kmac_cmd_e defines the possible command sets that software issues via + // !!CMD register. This is mainly to limit the error scenario that SW writes + // multiple commands at once. Additionally they are sparse encoded to harden + // against FI attacks + // + // Encoding generated with: + // $ ./util/design/sparse-fsm-encode.py -d 3 -m 5 -n 6 \ + // -s 1891656028 --language=sv + // + // Hamming distance histogram: + // + // 0: -- + // 1: -- + // 2: -- + // 3: |||||||||||||||||||| (50.00%) + // 4: |||||||||||||||| (40.00%) + // 5: |||| (10.00%) + // 6: -- + // + // Minimum Hamming distance: 3 + // Maximum Hamming distance: 5 + // Minimum Hamming weight: 3 + // Maximum Hamming weight: 4 + // + typedef enum logic [5:0] { + //CmdNone = 6'b001011, // dec 10 + // CmdNone is manually set to all zero by design! + // The minimum Hamming distance is still 3 + CmdNone = 6'b000000, // dec 0 + CmdStart = 6'b011101, // dec 29 + CmdProcess = 6'b101110, // dec 46 + CmdManualRun = 6'b110001, // dec 49 + CmdDone = 6'b010110 // dec 22 + } kmac_cmd_e; + + // Timer + parameter int unsigned TimerPrescalerW = 10; + parameter int unsigned EdnWaitTimerW = 16; + + // Entropy Mode Selection : Should be matched to register package Enum value + typedef enum logic [1:0] { + EntropyModeNone = 2'h 0, + EntropyModeEdn = 2'h 1, + EntropyModeSw = 2'h 2 + } entropy_mode_e; + + // PRNG (kmac_entropy) + parameter int unsigned EntropyOutputW = 800; + parameter int unsigned EntropyStateW = 288; + + // These LFSR parameters have been generated with + // $ ./util/design/gen-lfsr-seed.py --width 288 --seed 31468618 --prefix "" + typedef logic [EntropyStateW-1:0] lfsr_seed_t; + parameter lfsr_seed_t RndCnstLfsrSeedDefault = { + 32'h758a4420, + 256'h31e1c461_6ea343ec_153282a3_0c132b57_23c5a4cf_4743b3c7_c32d580f_74f1713a + }; + + // We use a single seed that is split down into chunks internally. + // These LFSR parameters have been generated with + // $ ./util/design/gen-lfsr-seed.py --width 800 --seed 3369807298 --prefix "" + typedef logic [EntropyOutputW-1:0][$clog2(EntropyOutputW)-1:0] lfsr_perm_t; + parameter lfsr_perm_t RndCnstLfsrPermDefault = { + 64'hb1a3e87aeb4e69f0, + 256'h2d8a6ee2c9ac567b2aa401a639a2a8ea2553614c0a8daf672c06546fc0d35267, + 256'hc4572024bc116458dd0f1c10a8aef5c4ad9a788968d0d7ca7345c6b8f277a5d3, + 256'hec5da20f261826ed3c8992724e70db897060be51b07a96902e14a42d12d320f8, + 256'h187049b6c25f35d0e485cc4b9ef01dad2865b5e558926f380718b74394fe0f82, + 256'hd5395a7d0aa4845af814e8681107a4c793758572c9467493bf1248a48f1b40c2, + 256'h09319b55111d0401819685a43a06f0da441021a8c220b14f01d44e49c1683a82, + 256'hafeb980964aa050641f4205131d9d4741eb5dd658e603b8ed438cb1096628d42, + 256'h62c9d75ced78ed09a3ddbb60f533eef10aa5a54b478d61a06a4b326eb3402105, + 256'hc27d562c6d91b48440d6d06e543be9871628a4aa9b3d2e51fa0ac2eb89a17f6d, + 256'h207ad96caf25d1fcffab210c1aff12252346fe4d56a7cd9b8605c7fa638895a9, + 256'h60158cd3a1ce4f2f6cf5d48579ac14b1e5219ca8914e0507b635dc712554f6bb, + 256'h0ae412943a7596f4644a0c13646adc91d02c406a10d232791d3de9919eec5424, + 256'haa2cac5f556c15c647eb29365062daf6aa848e10b3f665abccca713036d9f1cb, + 256'h1c9bd4aaeb19c5ac01b1805e0d5479860870da49a55e8f386ca8232c728e2f61, + 256'h3007aa420758818e5312401372eaa00d21c70c7e1158d2e08a1b6ac0b820cb67, + 256'hf0ba4b5c0865ff04f0f9d0175817c65d81918e43e14b2f83d574bfa9c6e6deae, + 256'h64c22c2974a1d5c55e2367004b249d5a02fc566685ea33b6f73aaa0244b34412, + 256'hb1a12230adb1748dc1d956f9f10c8e1aa52f4702e06a16680d92226c830ec4ce, + 256'h4c2eead21f08c387c3f1de89eb33b983c748e848f68b54f256715221177c5a4a, + 256'h0a47d82741955626755ba1cc24e2ba40504111b9e26136be714c5bc0d330c3f7, + 256'h75e863de763270a993890d633c6897218e151943edd8b79ae145cf564b774613, + 256'h0b0a76c40e7e84c876640dc78260c09a85e92e5ab56c22c0e72a8669fe88ba10, + 256'h8b99e437c776f0cea0d144f285b6ab7259e12284f380ae3410171cd6a8b04415, + 256'he95081c8c57e3e526ad5b38019a5c1b5505540462157e7c7e68e6a6a16ac460a, + 256'h5d5578da28092c7cc927cb9c0ed614a79b0e32b4c5b6a269a40743bef42b5e29, + 256'hd9a75ecb5548a29e9d34ddda07c8404aabbf5479456731ece3785f6090c3f862, + 256'h6eb1a5119e8b8e56b1455d820b46e20e15bb7d185a636b10ab8565732c59a302, + 256'h329925186604edbd5029a9f865268e90003b5b69d3e99240c3432291a60c62a4, + 256'hebad1ed028cd021b27260db22089e0c44481b1a4c120134ac63dc52fbc4cafb2, + 256'he065add2665fb361665267b53024329d96587d661f724171155ee73a3f0c47a8, + 256'h149751a5903c8bbcaf1782e415dfda531eb2af67c25e190330a12000e1fbb9cd + }; + + // These LFSR parameters have been generated with + // $ ./util/design/gen-lfsr-seed.py --width 800 --seed 31468618 --prefix "Buffer" + typedef logic [EntropyOutputW-1:0] buffer_lfsr_seed_t; + parameter buffer_lfsr_seed_t RndCnstBufferLfsrSeedDefault = { + 32'h292603b4, + 256'hf1d83863_e0bd0634_4544ad28_a91d8668_24b66efd_92ad8123_5381f2bc_3d65392c, + 256'h83c01ea5_d8be84f1_e2588917_11849a07_5a71f35f_e9b31605_f9077a6b_758a4420, + 256'h31e1c461_6ea343ec_153282a3_0c132b57_23c5a4cf_4743b3c7_c32d580f_74f1713a + }; + + // Message permutation + // These LFSR parameters have been generated with + // $ ./util/design/gen-lfsr-seed.py --width 64 --seed 1201202158 --prefix "" + // And changed the type name from lfsr_perm_t to msg_perm_t + typedef logic [MsgWidth-1:0][$clog2(MsgWidth)-1:0] msg_perm_t; + parameter msg_perm_t RndCnstMsgPermDefault = { + 128'h382af41849db4cfb9c885f72f118c102, + 256'hcb5526978defac799192f65f54148379af21d7e10d82a5a33c3f31a1eaf964b8 + }; + + /////////////////////////// + // Application interface // + /////////////////////////// + + // Application Algorithm + // Each interface can choose algorithms among SHA3, cSHAKE, KMAC + typedef enum bit [1:0] { + // SHA3 mode doer not nees any additional information. + // Prefix will be tied to all zero and not used. + AppSHA3 = 0, + + // In CShake/ KMAC mode, the Prefix can be determined by the compile-time + // parameter or through CSRs. + AppCShake = 1, + + // In KMAC mode, the secret key always comes from sideload. + // KMAC mode needs uniformly distributed entropy. The request will be + // silently discarded in Reset state. + AppKMAC = 2 + } app_mode_e; + + // Predefined encoded_string + parameter logic [15:0] EncodedStringEmpty = 16'h 0001; + parameter logic [47:0] EncodedStringKMAC = 48'h 4341_4D4B_2001; + // encoded_string("LC_CTRL") + parameter logic [71:0] EncodedStringLcCtrl = 72'h 4c_5254_435f_434C_3801; + // encoded_string("ROM_CTRL") + parameter logic [79:0] EncodedStringRomCtrl = 80'h 4c52_5443_5f4d_4f52_4001; + parameter int unsigned NSPrefixW = sha3_pkg::NSRegisterSize*8; + + typedef struct packed { + app_mode_e Mode; + + sha3_pkg::keccak_strength_e KeccakStrength; + + // PrefixMode determines the origin value of Prefix that is used in KMAC + // and cSHAKE operations. + // Choose **0** for CSRs (!!PREFIX), or **1** to use `Prefix` parameter + // below. + bit PrefixMode; + + // If `PrefixMode` is 1'b 1, then this `Prefix` value will be used in + // cSHAKE or KMAC operation. + logic [NSPrefixW-1:0] Prefix; + } app_config_t; + + parameter app_config_t AppCfgKeyMgr = '{ + Mode: AppKMAC, // KeyMgr uses KMAC operation + KeccakStrength: sha3_pkg::L256, + PrefixMode: 1'b1, // Use prefix parameter + // {fname: encoded_string("KMAC"), custom_str: encoded_string("")} + Prefix: NSPrefixW'({EncodedStringEmpty, EncodedStringKMAC}) + }; + + parameter app_config_t AppCfgLcCtrl= '{ + Mode: AppCShake, + KeccakStrength: sha3_pkg::L128, + PrefixMode: 1'b1, // Use prefix parameter + // {fname: encode_string(""), custom_str: encode_string("LC_CTRL")} + Prefix: NSPrefixW'({EncodedStringLcCtrl, EncodedStringEmpty}) + }; + + parameter app_config_t AppCfgRomCtrl = '{ + Mode: AppCShake, + KeccakStrength: sha3_pkg::L256, + PrefixMode: 1'b1, // Use prefix parameter + // {fname: encode_string(""), custom_str: encode_string("ROM_CTRL")} + Prefix: NSPrefixW'({EncodedStringRomCtrl, EncodedStringEmpty}) + }; + + // Exporting the app internal mux selection enum into the package. So that DV + // can use this enum in its scoreboard. + // Encoding generated with: + // $ ./util/design/sparse-fsm-encode.py -d 3 -m 4 -n 5 \ + // -s 713832113 --language=sv + // + // Hamming distance histogram: + // + // 0: -- + // 1: -- + // 2: -- + // 3: |||||||||||||||||||| (66.67%) + // 4: |||||||||| (33.33%) + // 5: -- + // + // Minimum Hamming distance: 3 + // Maximum Hamming distance: 4 + // Minimum Hamming weight: 1 + // Maximum Hamming weight: 4 + // + localparam int AppMuxWidth = 5; + typedef enum logic [AppMuxWidth-1:0] { + SelNone = 5'b10100, + SelApp = 5'b11001, + SelOutLen = 5'b00010, + SelSw = 5'b01111 + } app_mux_sel_e ; + +// Encoding generated with: + // $ ./util/design/sparse-fsm-encode.py -d 3 -m 14 -n 10 \ + // -s 2454278799 --language=sv + // + // Hamming distance histogram: + // + // 0: -- + // 1: -- + // 2: -- + // 3: |||||||||| (14.29%) + // 4: |||||||||||||||||||| (27.47%) + // 5: ||||||||||||| (18.68%) + // 6: |||||||||||||||| (21.98%) + // 7: |||||||| (10.99%) + // 8: |||| (6.59%) + // 9: -- + // 10: -- + // + // Minimum Hamming distance: 3 + // Maximum Hamming distance: 8 + // Minimum Hamming weight: 3 + // Maximum Hamming weight: 8 + // + localparam int AppStateWidth = 10; + typedef enum logic [AppStateWidth-1:0] { + StIdle = 10'b1010111110, + + // Application operation. + // + // if start request comes from an App first, until the operation ends by the + // requested App, all operations are granted to the specific App. SW + // requests and other Apps requests will be ignored. + // + // App interface does not have control signals. When first data valid occurs + // from an App, this logic asserts the start command to the downstream. When + // last beat pulse comes, this logic asserts the process to downstream + // (after the transaction is accepted regardless of partial writes or not) + // When absorbed by SHA3 core, the logic sends digest to the requested App + // and right next cycle, it triggers done command to downstream. + + // In StAppCfg state, it latches the cfg from AppCfg parameter to determine + // the kmac_mode, sha3_mode, keccak strength. + StAppCfg = 10'b1010101101, + + StAppMsg = 10'b1110001011, + + // In StKeyOutLen, this module pushes encoded outlen to the MSG_FIFO. + // Assume the length is 256 bit, the data will be 48'h 02_0100 + StAppOutLen = 10'b1010011000, + StAppProcess = 10'b1110110010, + StAppWait = 10'b1001010000, + + // SW Controlled + // If start request comes from SW first, until the operation ends, all + // requests from KeyMgr will be discarded. + StSw = 10'b0010111011, + + // Error KeyNotValid + // When KeyMgr operates, the secret key is not ready yet. + StKeyMgrErrKeyNotValid = 10'b0111011111, + + StError = 10'b1110010111, + StErrorAwaitSw = 10'b0110001100, + StErrorAwaitApp = 10'b1011100000, + StErrorWaitAbsorbed = 10'b0010100100, + StErrorServiceRejected = 10'b1101000111, + + // This state is used for terminal errors + StTerminalError = 10'b0101110110 + } st_e; + + // MsgWidth : 64 + // MsgStrbW : 8 + parameter int unsigned AppDigestW = 384; + parameter int unsigned AppKeyW = 256; + + typedef struct packed { + logic valid; + logic [MsgWidth-1:0] data; + logic [MsgStrbW-1:0] strb; + logic last; + } app_req_t; + + typedef struct packed { + logic ready; + logic done; + logic [AppDigestW-1:0] digest_share0; + logic [AppDigestW-1:0] digest_share1; + // Error is valid when done is high. If any error occurs during KDF, KMAC + // returns the garbage digest data with error. The KeyMgr discards the + // digest and may re-initiate the process. + logic error; + } app_rsp_t; + + parameter app_req_t APP_REQ_DEFAULT = '{ + valid: 1'b 0, + data: '0, + strb: '0, + last: 1'b 0 + }; + parameter app_rsp_t APP_RSP_DEFAULT = '{ + ready: 1'b1, + done: 1'b1, + digest_share0: AppDigestW'(32'hDEADBEEF), + digest_share1: AppDigestW'(32'hFACEBEEF), + error: 1'b1 + }; + + + //////////////////// + // Error Handling // + //////////////////// + + // Error structure is same to the SHA3 one. The codes do not overlap. + typedef enum logic [7:0] { + ErrNone = 8'h 00, + + // ErrSha3SwControl occurs when software sent wrong flow signal. + // e.g) Sw set `process_i` without `start_i`. The state machine ignores + // the signal and report through the error FIFO. + //ErrSha3SwControl = 8'h 80 + + // ErrKeyNotValid: KeyMgr interface raises an error if the secret key is + // not valid when KeyMgr initiates KDF. + ErrKeyNotValid = 8'h 01, + + // ErrSwPushMsgFifo: Sw writes data into Msg FIFO abruptly. + // This error occurs in below scenario: + // - Sw does not send "Start" command to KMAC then writes data into + // Msg FIFO + // - Sw writes data into Msg FIFO when KeyMgr is in operation + ErrSwPushedMsgFifo = 8'h 02, + + // ErrSwIssuedCmdInAppActive + // - Sw writes any command while AppIntf is in active. + ErrSwIssuedCmdInAppActive = 8'h 03, + + // ErrWaitTimerExpired + // Entropy Wait timer expired. Something wrong on EDN i/f + ErrWaitTimerExpired = 8'h 04, + + // ErrIncorrectEntropyMode + // Incorrect Entropy mode when entropy is ready + ErrIncorrectEntropyMode = 8'h 05, + + // ErrUnexpectedModeStrength + ErrUnexpectedModeStrength = 8'h 06, + + // ErrIncorrectFunctionName "KMAC" + ErrIncorrectFunctionName = 8'h 07, + + // ErrSwCmdSequence + ErrSwCmdSequence = 8'h 08, + + // ErrSwHashingWithoutEntropyReady + // - Sw issues KMAC op without Entropy setting. + ErrSwHashingWithoutEntropyReady = 8'h 09, + + // Error due to caliptra_ss_lc_escalation_en_i or fatal fault + ErrFatalError = 8'h C1, + + // Error due to the counter integrity check failure inside MsgFifo.Packer + ErrPackerIntegrity = 8'h C2, + + // Error due to the counter integrity check failure inside MsgFifo.Fifo + ErrMsgFifoIntegrity = 8'h C3 + } err_code_e; + + typedef struct packed { + logic valid; + err_code_e code; // Type of error + logic [23:0] info; // Additional Debug info + } err_t; + parameter int unsigned ErrInfoW = 24 ; // err_t::info + + typedef struct packed { + logic [AppDigestW-1:0] digest_share0; + logic [AppDigestW-1:0] digest_share1; + } rsp_digest_t; + /////////////////////// + // Library Functions // + /////////////////////// + + // Endian conversion functions (32-bit, 64-bit) + function automatic logic [31:0] conv_endian32( input logic [31:0] v, input logic swap); + logic [31:0] conv_data; + conv_data = {<<8{v}}; + conv_endian32 = (swap) ? conv_data : v ; + endfunction : conv_endian32 + +endpackage : kmac_pkg diff --git a/src/caliptra_ss_lc_ctrl/rtl/kmac_reduced.sv b/src/caliptra_ss_lc_ctrl/rtl/kmac_reduced.sv new file mode 100644 index 0000000..f63fd4c --- /dev/null +++ b/src/caliptra_ss_lc_ctrl/rtl/kmac_reduced.sv @@ -0,0 +1,312 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Reduced KMAC/SHA3 core including PRNG but without TL-UL interface. This module is suitable for +// SCA using e.g. PROLEAD. + +`include "caliptra_prim_assert.sv" + +module kmac_reduced + import kmac_pkg::*; + import kmac_reg_pkg::*; + import sha3_pkg::*; +#( + // EnMasking: Enable masking security hardening inside keccak_round. + parameter bit EnMasking = 1, + localparam int NumShares = (EnMasking) ? 2 : 1, // derived parameter + + // For now, we use a fixed message length of 128 bits to mirror some of the initial FPGA + // experiments. + parameter int unsigned MsgLen = 128, + parameter int unsigned EntropyWidth = 32, + + parameter lfsr_perm_t RndCnstLfsrPerm = RndCnstLfsrPermDefault, + parameter lfsr_seed_t RndCnstLfsrSeed = RndCnstLfsrSeedDefault, + parameter buffer_lfsr_seed_t RndCnstBufferLfsrSeed = RndCnstBufferLfsrSeedDefault, + parameter msg_perm_t RndCnstMsgPerm = RndCnstMsgPermDefault +) ( + input logic clk_i, + input logic rst_ni, + + // Inputs exercised by SCA tools. + // Pre-masked message input. The message is provided in one shot to facilitate the interfacing. + input logic [MsgLen-1:0] msg_i [NumShares], + input logic msg_valid_i, + output logic msg_ready_o, + + // SHA3 control and status + input logic start_i, // 1 pulse after reseeding PRNG and injecting + // messsage + input logic process_i, // 1 pulse after loading message into SHA3 + input logic run_i, // drive to 0 + input caliptra_prim_mubi_pkg::mubi4_t done_i, // drive to MuBi4True after + // absorbed_o == MuBi4True + output caliptra_prim_mubi_pkg::mubi4_t absorbed_o, + output logic squeezing_o, + output logic block_processed_o, + output sha3_st_e sha3_fsm_o, + + // Entropy interface + input logic entropy_ready_i, // drive to 1 once ready + input logic entropy_refresh_req_i, // one pulse at the beginning + input logic [EntropyWidth-1:0] entropy_i, + output logic entropy_req_o, + input logic entropy_ack_i, + + // Inputs driven with constant values for evaluation but we want to avoid synthesis optimizing + // them. + // SHA3 configuration + input sha3_mode_e mode_i, // e.g. sha3_pkg::Sha3 + input keccak_strength_e strength_i, // e.g. sha3_pkg::L256 + input logic [NSRegisterSize*8-1:0] ns_prefix_i, // Ignored for Sha3, + // 48'h4341_4D4B_2001 for CShake + input logic [sha3_pkg::MsgStrbW-1:0] msg_strb_i, // drive to all-1 + + // Entropy configuration + input logic msg_mask_en_i, // drive to 1 + input entropy_mode_e entropy_mode_i, // drive to kmac_pkg::EntropyModeEdn + input logic entropy_fast_process_i, // drive to 0 + input logic entropy_in_keyblock_i, // drive to 1 + + // Entropy reseed control + input logic entropy_seed_update_i, // drive to 0 + input logic [31:0] entropy_seed_data_i, // drive to 0 + input logic [TimerPrescalerW-1:0] wait_timer_prescaler_i, // drive to 0 + input logic [EdnWaitTimerW-1:0] wait_timer_limit_i, // drive to EdnWaitTimerW'1 + + // Signals primarily kept to prevent them from being optimized away during synthesis. + // State output + output logic [StateW-1:0] state_o [NumShares], + output logic state_valid_o, + + // Entropy status signals + output caliptra_prim_mubi_pkg::mubi4_t entropy_configured_o, + input logic [HashCntW-1:0] entropy_hash_threshold_i, // drive to max + input logic entropy_hash_clr_i, // drive to 0 + output logic [HashCntW-1:0] entropy_hash_cnt_o, + + // Life cycle interface + input caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_t caliptra_ss_lc_escalate_en_i, + + // Error signaling + output logic err_o, + input logic err_processed_i // drive 0 +); + + /////////////////////////////////// + // Message unpacking & injection // + /////////////////////////////////// + // Message packer FIFO + logic [sha3_pkg::MsgWidth-1:0] msg [NumShares]; + logic [NumShares-1:0] msg_valid_shares; + logic [NumShares-1:0] msg_ready_shares; + logic msg_valid, msg_ready; + + caliptra_prim_packer_fifo #( + .InW(MsgLen), + .OutW(sha3_pkg::MsgWidth), + .ClearOnRead(1'b1) + ) u_msg_unpacker_share0 ( + .clk_i, + .rst_ni, + .clr_i (1'b0), + .wvalid_i(msg_valid_i), + .wdata_i (msg_i[0]), + .wready_o(msg_ready_shares[0]), + .rvalid_o(msg_valid_shares[0]), + .rdata_o (msg[0]), + .rready_i(msg_ready), + .depth_o () + ); + + caliptra_prim_packer_fifo #( + .InW(MsgLen), + .OutW(sha3_pkg::MsgWidth), + .ClearOnRead(1'b1) + ) u_msg_unpacker_share1 ( + .clk_i, + .rst_ni, + .clr_i (1'b0), + .wvalid_i(msg_valid_i), + .wdata_i (msg_i[1]), + .wready_o(msg_ready_shares[1]), + .rvalid_o(msg_valid_shares[1]), + .rdata_o (msg[1]), + .rready_i(msg_ready), + .depth_o () + ); + + // Reduce valid/ready signals driven by the packer FIFOs. + assign msg_ready_o = &msg_ready_shares; + assign msg_valid = &msg_valid_shares; + + ////////////////////////// + // Message (re-)masking // + ////////////////////////// + logic msg_mask_en; + logic [sha3_pkg::MsgWidth-1:0] msg_mask, msg_mask_permuted; + logic [sha3_pkg::MsgWidth-1:0] msg_masked [NumShares]; + + // Permute the PRNG output. + always_comb begin + msg_mask_permuted = '0; + for (int unsigned i = 0 ; i < sha3_pkg::MsgWidth ; i++) begin + // Loop through the MsgPerm constant and swap between the bits + msg_mask_permuted[i] = msg_mask[RndCnstMsgPerm[i]]; + end + end + + // Perform the actual (re-)masking + for (genvar i = 0; i < NumShares; i++) begin: gen_msg_masking + assign msg_masked[i] = + msg[i] ^ ({sha3_pkg::MsgWidth{msg_mask_en_i}} & msg_mask_permuted); + end + + assign msg_mask_en = msg_mask_en_i & msg_valid & msg_ready; + + // SHA3 entropy interface + logic sha3_rand_valid, sha3_rand_early, sha3_rand_update, sha3_rand_consumed; + logic [StateW/2-1:0] sha3_rand_data; + logic sha3_rand_aux; + + // Life cycle signals + localparam int unsigned NumLcSyncCopies = 2; + caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_t [NumLcSyncCopies-1:0] caliptra_ss_lc_escalate_en; + + // Synchronize life cycle input. + caliptra_prim_lc_sync #( + .NumCopies (NumLcSyncCopies) + ) u_caliptra_prim_lc_sync ( + .clk_i, + .rst_ni, + .lc_en_i(caliptra_ss_lc_escalate_en_i), + .lc_en_o(caliptra_ss_lc_escalate_en) + ); + + // Error signals + sha3_pkg::err_t sha3_err, entropy_err; + logic sha3_state_error, sha3_count_error, sha3_storage_rst_error; + logic entropy_state_error, entropy_hash_counter_error; + + // Collect error signals. + assign err_o = |{sha3_err, sha3_state_error, sha3_count_error, sha3_storage_rst_error, + entropy_err, entropy_state_error, entropy_hash_counter_error}; + + ///////////////// + // SHA3 engine // + ///////////////// + sha3 #( + .EnMasking(EnMasking) + ) u_sha3 ( + .clk_i, + .rst_ni, + + // MSG_FIFO interface (or from KMAC) + .msg_valid_i(msg_valid), + .msg_data_i (msg_masked), + .msg_strb_i (msg_strb_i), + .msg_ready_o(msg_ready), + + // Entropy interface + .rand_valid_i (sha3_rand_valid), + .rand_early_i (sha3_rand_early), + .rand_data_i (sha3_rand_data), + .rand_aux_i (sha3_rand_aux), + .rand_update_o (sha3_rand_update), + .rand_consumed_o (sha3_rand_consumed), + + // N, S: Used in cSHAKE mode + .ns_data_i (ns_prefix_i), + + // Configurations + .mode_i, + .strength_i, + + // Control and status + .start_i, // Start receiving message. + .process_i, // Stop receiving message, start padding and afterwards processing. + .run_i, // Manually trigger processing after absorption. + .done_i, // Clear internal variables and move back into Idle state. + .absorbed_o, // Absorption process is done. + .squeezing_o, // Currently running manually triggered processing after absorption. + .block_processed_o, + .sha3_fsm_o, + + // State output + .state_valid_o(state_valid_o), + .state_o (state_o), + + // REQ/ACK interface to avoid power spikes + .run_req_o(), // Not used + .run_ack_i(1'b1), // The SHA3 core is always allowed to process. + + // LC escalation + .caliptra_ss_lc_escalate_en_i(caliptra_ss_lc_escalate_en[0]), + + // Error signals + .error_o (sha3_err), + .sparse_fsm_error_o (sha3_state_error), + .count_error_o (sha3_count_error), + .keccak_storage_rst_error_o(sha3_storage_rst_error) + ); + + ////////// + // PRNG // + ////////// + kmac_entropy #( + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .RndCnstLfsrSeed(RndCnstLfsrSeed), + .RndCnstBufferLfsrSeed(RndCnstBufferLfsrSeed) + ) u_entropy ( + .clk_i, + .rst_ni, + + // EDN interface + .entropy_req_o (entropy_req_o), + .entropy_ack_i (entropy_ack_i), + .entropy_data_i(entropy_i), + + // SHA3 interface + .rand_valid_o (sha3_rand_valid), + .rand_early_o (sha3_rand_early), + .rand_data_o (sha3_rand_data), + .rand_aux_o (sha3_rand_aux), + .rand_update_i (sha3_rand_update), + .rand_consumed_i(sha3_rand_consumed), + + // Message Masking + .msg_mask_en_i(msg_mask_en), + .msg_mask_o (msg_mask), + + // Configuration + .mode_i (entropy_mode_i), + .entropy_ready_i(entropy_ready_i), + .fast_process_i (entropy_fast_process_i), + .in_keyblock_i (entropy_in_keyblock_i), + + // Reseed control + .entropy_refresh_req_i (entropy_refresh_req_i), + .seed_update_i (entropy_seed_update_i), + .seed_data_i (entropy_seed_data_i), + .wait_timer_prescaler_i(wait_timer_prescaler_i), + .wait_timer_limit_i (wait_timer_limit_i), + + // Status + .hash_threshold_i(entropy_hash_threshold_i), + .hash_cnt_clr_i (entropy_hash_clr_i), + .hash_cnt_o (entropy_hash_cnt_o), + + .entropy_configured_o(entropy_configured_o), + + // LC escalation + .caliptra_ss_lc_escalate_en_i(caliptra_ss_lc_escalate_en[1]), + + // Error signals + .err_o (entropy_err), + .sparse_fsm_error_o(entropy_state_error), + .count_error_o (entropy_hash_counter_error), + .err_processed_i (err_processed_i) + ); + +endmodule diff --git a/src/caliptra_ss_lc_ctrl/rtl/kmac_reg_pkg.sv b/src/caliptra_ss_lc_ctrl/rtl/kmac_reg_pkg.sv new file mode 100644 index 0000000..20bf330 --- /dev/null +++ b/src/caliptra_ss_lc_ctrl/rtl/kmac_reg_pkg.sv @@ -0,0 +1,499 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Package auto-generated by `reggen` containing data structure + +package kmac_reg_pkg; + + // Param list + parameter int NumWordsKey = 16; + parameter int NumWordsPrefix = 11; + parameter int NumEntriesMsgFifo = 10; + parameter int NumBytesMsgFifoEntry = 8; + parameter int unsigned HashCntW = 10; + parameter int NumSeedsEntropy = 6; + parameter int NumAlerts = 2; + + // Address widths within the block + parameter int BlockAw = 12; + + //////////////////////////// + // Typedefs for registers // + //////////////////////////// + + typedef struct packed { + struct packed { + logic q; + } kmac_err; + struct packed { + logic q; + } fifo_empty; + struct packed { + logic q; + } kmac_done; + } kmac_reg2hw_intr_state_reg_t; + + typedef struct packed { + struct packed { + logic q; + } kmac_err; + struct packed { + logic q; + } fifo_empty; + struct packed { + logic q; + } kmac_done; + } kmac_reg2hw_intr_enable_reg_t; + + typedef struct packed { + struct packed { + logic q; + logic qe; + } kmac_err; + struct packed { + logic q; + logic qe; + } fifo_empty; + struct packed { + logic q; + logic qe; + } kmac_done; + } kmac_reg2hw_intr_test_reg_t; + + typedef struct packed { + struct packed { + logic q; + logic qe; + } fatal_fault_err; + struct packed { + logic q; + logic qe; + } recov_operation_err; + } kmac_reg2hw_alert_test_reg_t; + + typedef struct packed { + struct packed { + logic q; + logic qe; + } en_unsupported_modestrength; + struct packed { + logic q; + logic qe; + } entropy_ready; + struct packed { + logic q; + logic qe; + } msg_mask; + struct packed { + logic q; + logic qe; + } entropy_fast_process; + struct packed { + logic [1:0] q; + logic qe; + } entropy_mode; + struct packed { + logic q; + logic qe; + } sideload; + struct packed { + logic q; + logic qe; + } state_endianness; + struct packed { + logic q; + logic qe; + } msg_endianness; + struct packed { + logic [1:0] q; + logic qe; + } mode; + struct packed { + logic [2:0] q; + logic qe; + } kstrength; + struct packed { + logic q; + logic qe; + } kmac_en; + } kmac_reg2hw_cfg_shadowed_reg_t; + + typedef struct packed { + struct packed { + logic q; + logic qe; + } err_processed; + struct packed { + logic q; + logic qe; + } hash_cnt_clr; + struct packed { + logic q; + logic qe; + } entropy_req; + struct packed { + logic [5:0] q; + logic qe; + } cmd; + } kmac_reg2hw_cmd_reg_t; + + typedef struct packed { + struct packed { + logic [15:0] q; + } wait_timer; + struct packed { + logic [9:0] q; + } prescaler; + } kmac_reg2hw_entropy_period_reg_t; + + typedef struct packed { + logic [9:0] q; + } kmac_reg2hw_entropy_refresh_threshold_shadowed_reg_t; + + typedef struct packed { + logic [31:0] q; + logic qe; + } kmac_reg2hw_entropy_seed_reg_t; + + typedef struct packed { + logic [31:0] q; + logic qe; + } kmac_reg2hw_key_share0_mreg_t; + + typedef struct packed { + logic [31:0] q; + logic qe; + } kmac_reg2hw_key_share1_mreg_t; + + typedef struct packed { + logic [2:0] q; + } kmac_reg2hw_key_len_reg_t; + + typedef struct packed { + logic [31:0] q; + } kmac_reg2hw_prefix_mreg_t; + + typedef struct packed { + struct packed { + logic d; + logic de; + } kmac_done; + struct packed { + logic d; + logic de; + } fifo_empty; + struct packed { + logic d; + logic de; + } kmac_err; + } kmac_hw2reg_intr_state_reg_t; + + typedef struct packed { + logic d; + } kmac_hw2reg_cfg_regwen_reg_t; + + typedef struct packed { + struct packed { + logic d; + } sha3_idle; + struct packed { + logic d; + } sha3_absorb; + struct packed { + logic d; + } sha3_squeeze; + struct packed { + logic [4:0] d; + } fifo_depth; + struct packed { + logic d; + } fifo_empty; + struct packed { + logic d; + } fifo_full; + struct packed { + logic d; + } alert_fatal_fault; + struct packed { + logic d; + } alert_recov_ctrl_update_err; + } kmac_hw2reg_status_reg_t; + + typedef struct packed { + logic [9:0] d; + logic de; + } kmac_hw2reg_entropy_refresh_hash_cnt_reg_t; + + typedef struct packed { + logic [31:0] d; + logic de; + } kmac_hw2reg_err_code_reg_t; + + // Register -> HW type + typedef struct packed { + kmac_reg2hw_intr_state_reg_t intr_state; // [1534:1532] + kmac_reg2hw_intr_enable_reg_t intr_enable; // [1531:1529] + kmac_reg2hw_intr_test_reg_t intr_test; // [1528:1523] + kmac_reg2hw_alert_test_reg_t alert_test; // [1522:1519] + kmac_reg2hw_cfg_shadowed_reg_t cfg_shadowed; // [1518:1493] + kmac_reg2hw_cmd_reg_t cmd; // [1492:1480] + kmac_reg2hw_entropy_period_reg_t entropy_period; // [1479:1454] + kmac_reg2hw_entropy_refresh_threshold_shadowed_reg_t + entropy_refresh_threshold_shadowed; // [1453:1444] + kmac_reg2hw_entropy_seed_reg_t entropy_seed; // [1443:1411] + kmac_reg2hw_key_share0_mreg_t [15:0] key_share0; // [1410:883] + kmac_reg2hw_key_share1_mreg_t [15:0] key_share1; // [882:355] + kmac_reg2hw_key_len_reg_t key_len; // [354:352] + kmac_reg2hw_prefix_mreg_t [10:0] prefix; // [351:0] + } kmac_reg2hw_t; + + // HW -> register type + typedef struct packed { + kmac_hw2reg_intr_state_reg_t intr_state; // [62:57] + kmac_hw2reg_cfg_regwen_reg_t cfg_regwen; // [56:56] + kmac_hw2reg_status_reg_t status; // [55:44] + kmac_hw2reg_entropy_refresh_hash_cnt_reg_t entropy_refresh_hash_cnt; // [43:33] + kmac_hw2reg_err_code_reg_t err_code; // [32:0] + } kmac_hw2reg_t; + + // Register offsets + parameter logic [BlockAw-1:0] KMAC_INTR_STATE_OFFSET = 12'h 0; + parameter logic [BlockAw-1:0] KMAC_INTR_ENABLE_OFFSET = 12'h 4; + parameter logic [BlockAw-1:0] KMAC_INTR_TEST_OFFSET = 12'h 8; + parameter logic [BlockAw-1:0] KMAC_ALERT_TEST_OFFSET = 12'h c; + parameter logic [BlockAw-1:0] KMAC_CFG_REGWEN_OFFSET = 12'h 10; + parameter logic [BlockAw-1:0] KMAC_CFG_SHADOWED_OFFSET = 12'h 14; + parameter logic [BlockAw-1:0] KMAC_CMD_OFFSET = 12'h 18; + parameter logic [BlockAw-1:0] KMAC_STATUS_OFFSET = 12'h 1c; + parameter logic [BlockAw-1:0] KMAC_ENTROPY_PERIOD_OFFSET = 12'h 20; + parameter logic [BlockAw-1:0] KMAC_ENTROPY_REFRESH_HASH_CNT_OFFSET = 12'h 24; + parameter logic [BlockAw-1:0] KMAC_ENTROPY_REFRESH_THRESHOLD_SHADOWED_OFFSET = 12'h 28; + parameter logic [BlockAw-1:0] KMAC_ENTROPY_SEED_OFFSET = 12'h 2c; + parameter logic [BlockAw-1:0] KMAC_KEY_SHARE0_0_OFFSET = 12'h 30; + parameter logic [BlockAw-1:0] KMAC_KEY_SHARE0_1_OFFSET = 12'h 34; + parameter logic [BlockAw-1:0] KMAC_KEY_SHARE0_2_OFFSET = 12'h 38; + parameter logic [BlockAw-1:0] KMAC_KEY_SHARE0_3_OFFSET = 12'h 3c; + parameter logic [BlockAw-1:0] KMAC_KEY_SHARE0_4_OFFSET = 12'h 40; + parameter logic [BlockAw-1:0] KMAC_KEY_SHARE0_5_OFFSET = 12'h 44; + parameter logic [BlockAw-1:0] KMAC_KEY_SHARE0_6_OFFSET = 12'h 48; + parameter logic [BlockAw-1:0] KMAC_KEY_SHARE0_7_OFFSET = 12'h 4c; + parameter logic [BlockAw-1:0] KMAC_KEY_SHARE0_8_OFFSET = 12'h 50; + parameter logic [BlockAw-1:0] KMAC_KEY_SHARE0_9_OFFSET = 12'h 54; + parameter logic [BlockAw-1:0] KMAC_KEY_SHARE0_10_OFFSET = 12'h 58; + parameter logic [BlockAw-1:0] KMAC_KEY_SHARE0_11_OFFSET = 12'h 5c; + parameter logic [BlockAw-1:0] KMAC_KEY_SHARE0_12_OFFSET = 12'h 60; + parameter logic [BlockAw-1:0] KMAC_KEY_SHARE0_13_OFFSET = 12'h 64; + parameter logic [BlockAw-1:0] KMAC_KEY_SHARE0_14_OFFSET = 12'h 68; + parameter logic [BlockAw-1:0] KMAC_KEY_SHARE0_15_OFFSET = 12'h 6c; + parameter logic [BlockAw-1:0] KMAC_KEY_SHARE1_0_OFFSET = 12'h 70; + parameter logic [BlockAw-1:0] KMAC_KEY_SHARE1_1_OFFSET = 12'h 74; + parameter logic [BlockAw-1:0] KMAC_KEY_SHARE1_2_OFFSET = 12'h 78; + parameter logic [BlockAw-1:0] KMAC_KEY_SHARE1_3_OFFSET = 12'h 7c; + parameter logic [BlockAw-1:0] KMAC_KEY_SHARE1_4_OFFSET = 12'h 80; + parameter logic [BlockAw-1:0] KMAC_KEY_SHARE1_5_OFFSET = 12'h 84; + parameter logic [BlockAw-1:0] KMAC_KEY_SHARE1_6_OFFSET = 12'h 88; + parameter logic [BlockAw-1:0] KMAC_KEY_SHARE1_7_OFFSET = 12'h 8c; + parameter logic [BlockAw-1:0] KMAC_KEY_SHARE1_8_OFFSET = 12'h 90; + parameter logic [BlockAw-1:0] KMAC_KEY_SHARE1_9_OFFSET = 12'h 94; + parameter logic [BlockAw-1:0] KMAC_KEY_SHARE1_10_OFFSET = 12'h 98; + parameter logic [BlockAw-1:0] KMAC_KEY_SHARE1_11_OFFSET = 12'h 9c; + parameter logic [BlockAw-1:0] KMAC_KEY_SHARE1_12_OFFSET = 12'h a0; + parameter logic [BlockAw-1:0] KMAC_KEY_SHARE1_13_OFFSET = 12'h a4; + parameter logic [BlockAw-1:0] KMAC_KEY_SHARE1_14_OFFSET = 12'h a8; + parameter logic [BlockAw-1:0] KMAC_KEY_SHARE1_15_OFFSET = 12'h ac; + parameter logic [BlockAw-1:0] KMAC_KEY_LEN_OFFSET = 12'h b0; + parameter logic [BlockAw-1:0] KMAC_PREFIX_0_OFFSET = 12'h b4; + parameter logic [BlockAw-1:0] KMAC_PREFIX_1_OFFSET = 12'h b8; + parameter logic [BlockAw-1:0] KMAC_PREFIX_2_OFFSET = 12'h bc; + parameter logic [BlockAw-1:0] KMAC_PREFIX_3_OFFSET = 12'h c0; + parameter logic [BlockAw-1:0] KMAC_PREFIX_4_OFFSET = 12'h c4; + parameter logic [BlockAw-1:0] KMAC_PREFIX_5_OFFSET = 12'h c8; + parameter logic [BlockAw-1:0] KMAC_PREFIX_6_OFFSET = 12'h cc; + parameter logic [BlockAw-1:0] KMAC_PREFIX_7_OFFSET = 12'h d0; + parameter logic [BlockAw-1:0] KMAC_PREFIX_8_OFFSET = 12'h d4; + parameter logic [BlockAw-1:0] KMAC_PREFIX_9_OFFSET = 12'h d8; + parameter logic [BlockAw-1:0] KMAC_PREFIX_10_OFFSET = 12'h dc; + parameter logic [BlockAw-1:0] KMAC_ERR_CODE_OFFSET = 12'h e0; + + // Reset values for hwext registers and their fields + parameter logic [2:0] KMAC_INTR_TEST_RESVAL = 3'h 0; + parameter logic [0:0] KMAC_INTR_TEST_KMAC_DONE_RESVAL = 1'h 0; + parameter logic [0:0] KMAC_INTR_TEST_FIFO_EMPTY_RESVAL = 1'h 0; + parameter logic [0:0] KMAC_INTR_TEST_KMAC_ERR_RESVAL = 1'h 0; + parameter logic [1:0] KMAC_ALERT_TEST_RESVAL = 2'h 0; + parameter logic [0:0] KMAC_ALERT_TEST_RECOV_OPERATION_ERR_RESVAL = 1'h 0; + parameter logic [0:0] KMAC_ALERT_TEST_FATAL_FAULT_ERR_RESVAL = 1'h 0; + parameter logic [0:0] KMAC_CFG_REGWEN_RESVAL = 1'h 1; + parameter logic [0:0] KMAC_CFG_REGWEN_EN_RESVAL = 1'h 1; + parameter logic [10:0] KMAC_CMD_RESVAL = 11'h 0; + parameter logic [17:0] KMAC_STATUS_RESVAL = 18'h 4001; + parameter logic [0:0] KMAC_STATUS_SHA3_IDLE_RESVAL = 1'h 1; + parameter logic [0:0] KMAC_STATUS_FIFO_EMPTY_RESVAL = 1'h 1; + parameter logic [0:0] KMAC_STATUS_ALERT_FATAL_FAULT_RESVAL = 1'h 0; + parameter logic [0:0] KMAC_STATUS_ALERT_RECOV_CTRL_UPDATE_ERR_RESVAL = 1'h 0; + parameter logic [31:0] KMAC_ENTROPY_SEED_RESVAL = 32'h 0; + parameter logic [31:0] KMAC_KEY_SHARE0_0_RESVAL = 32'h 0; + parameter logic [31:0] KMAC_KEY_SHARE0_1_RESVAL = 32'h 0; + parameter logic [31:0] KMAC_KEY_SHARE0_2_RESVAL = 32'h 0; + parameter logic [31:0] KMAC_KEY_SHARE0_3_RESVAL = 32'h 0; + parameter logic [31:0] KMAC_KEY_SHARE0_4_RESVAL = 32'h 0; + parameter logic [31:0] KMAC_KEY_SHARE0_5_RESVAL = 32'h 0; + parameter logic [31:0] KMAC_KEY_SHARE0_6_RESVAL = 32'h 0; + parameter logic [31:0] KMAC_KEY_SHARE0_7_RESVAL = 32'h 0; + parameter logic [31:0] KMAC_KEY_SHARE0_8_RESVAL = 32'h 0; + parameter logic [31:0] KMAC_KEY_SHARE0_9_RESVAL = 32'h 0; + parameter logic [31:0] KMAC_KEY_SHARE0_10_RESVAL = 32'h 0; + parameter logic [31:0] KMAC_KEY_SHARE0_11_RESVAL = 32'h 0; + parameter logic [31:0] KMAC_KEY_SHARE0_12_RESVAL = 32'h 0; + parameter logic [31:0] KMAC_KEY_SHARE0_13_RESVAL = 32'h 0; + parameter logic [31:0] KMAC_KEY_SHARE0_14_RESVAL = 32'h 0; + parameter logic [31:0] KMAC_KEY_SHARE0_15_RESVAL = 32'h 0; + parameter logic [31:0] KMAC_KEY_SHARE1_0_RESVAL = 32'h 0; + parameter logic [31:0] KMAC_KEY_SHARE1_1_RESVAL = 32'h 0; + parameter logic [31:0] KMAC_KEY_SHARE1_2_RESVAL = 32'h 0; + parameter logic [31:0] KMAC_KEY_SHARE1_3_RESVAL = 32'h 0; + parameter logic [31:0] KMAC_KEY_SHARE1_4_RESVAL = 32'h 0; + parameter logic [31:0] KMAC_KEY_SHARE1_5_RESVAL = 32'h 0; + parameter logic [31:0] KMAC_KEY_SHARE1_6_RESVAL = 32'h 0; + parameter logic [31:0] KMAC_KEY_SHARE1_7_RESVAL = 32'h 0; + parameter logic [31:0] KMAC_KEY_SHARE1_8_RESVAL = 32'h 0; + parameter logic [31:0] KMAC_KEY_SHARE1_9_RESVAL = 32'h 0; + parameter logic [31:0] KMAC_KEY_SHARE1_10_RESVAL = 32'h 0; + parameter logic [31:0] KMAC_KEY_SHARE1_11_RESVAL = 32'h 0; + parameter logic [31:0] KMAC_KEY_SHARE1_12_RESVAL = 32'h 0; + parameter logic [31:0] KMAC_KEY_SHARE1_13_RESVAL = 32'h 0; + parameter logic [31:0] KMAC_KEY_SHARE1_14_RESVAL = 32'h 0; + parameter logic [31:0] KMAC_KEY_SHARE1_15_RESVAL = 32'h 0; + + // Window parameters + parameter logic [BlockAw-1:0] KMAC_STATE_OFFSET = 12'h 400; + parameter int unsigned KMAC_STATE_SIZE = 'h 200; + parameter int unsigned KMAC_STATE_IDX = 0; + parameter logic [BlockAw-1:0] KMAC_MSG_FIFO_OFFSET = 12'h 800; + parameter int unsigned KMAC_MSG_FIFO_SIZE = 'h 800; + parameter int unsigned KMAC_MSG_FIFO_IDX = 1; + + // Register index + typedef enum int { + KMAC_INTR_STATE, + KMAC_INTR_ENABLE, + KMAC_INTR_TEST, + KMAC_ALERT_TEST, + KMAC_CFG_REGWEN, + KMAC_CFG_SHADOWED, + KMAC_CMD, + KMAC_STATUS, + KMAC_ENTROPY_PERIOD, + KMAC_ENTROPY_REFRESH_HASH_CNT, + KMAC_ENTROPY_REFRESH_THRESHOLD_SHADOWED, + KMAC_ENTROPY_SEED, + KMAC_KEY_SHARE0_0, + KMAC_KEY_SHARE0_1, + KMAC_KEY_SHARE0_2, + KMAC_KEY_SHARE0_3, + KMAC_KEY_SHARE0_4, + KMAC_KEY_SHARE0_5, + KMAC_KEY_SHARE0_6, + KMAC_KEY_SHARE0_7, + KMAC_KEY_SHARE0_8, + KMAC_KEY_SHARE0_9, + KMAC_KEY_SHARE0_10, + KMAC_KEY_SHARE0_11, + KMAC_KEY_SHARE0_12, + KMAC_KEY_SHARE0_13, + KMAC_KEY_SHARE0_14, + KMAC_KEY_SHARE0_15, + KMAC_KEY_SHARE1_0, + KMAC_KEY_SHARE1_1, + KMAC_KEY_SHARE1_2, + KMAC_KEY_SHARE1_3, + KMAC_KEY_SHARE1_4, + KMAC_KEY_SHARE1_5, + KMAC_KEY_SHARE1_6, + KMAC_KEY_SHARE1_7, + KMAC_KEY_SHARE1_8, + KMAC_KEY_SHARE1_9, + KMAC_KEY_SHARE1_10, + KMAC_KEY_SHARE1_11, + KMAC_KEY_SHARE1_12, + KMAC_KEY_SHARE1_13, + KMAC_KEY_SHARE1_14, + KMAC_KEY_SHARE1_15, + KMAC_KEY_LEN, + KMAC_PREFIX_0, + KMAC_PREFIX_1, + KMAC_PREFIX_2, + KMAC_PREFIX_3, + KMAC_PREFIX_4, + KMAC_PREFIX_5, + KMAC_PREFIX_6, + KMAC_PREFIX_7, + KMAC_PREFIX_8, + KMAC_PREFIX_9, + KMAC_PREFIX_10, + KMAC_ERR_CODE + } kmac_id_e; + + // Register width information to check illegal writes + parameter logic [3:0] KMAC_PERMIT [57] = '{ + 4'b 0001, // index[ 0] KMAC_INTR_STATE + 4'b 0001, // index[ 1] KMAC_INTR_ENABLE + 4'b 0001, // index[ 2] KMAC_INTR_TEST + 4'b 0001, // index[ 3] KMAC_ALERT_TEST + 4'b 0001, // index[ 4] KMAC_CFG_REGWEN + 4'b 1111, // index[ 5] KMAC_CFG_SHADOWED + 4'b 0011, // index[ 6] KMAC_CMD + 4'b 0111, // index[ 7] KMAC_STATUS + 4'b 1111, // index[ 8] KMAC_ENTROPY_PERIOD + 4'b 0011, // index[ 9] KMAC_ENTROPY_REFRESH_HASH_CNT + 4'b 0011, // index[10] KMAC_ENTROPY_REFRESH_THRESHOLD_SHADOWED + 4'b 1111, // index[11] KMAC_ENTROPY_SEED + 4'b 1111, // index[12] KMAC_KEY_SHARE0_0 + 4'b 1111, // index[13] KMAC_KEY_SHARE0_1 + 4'b 1111, // index[14] KMAC_KEY_SHARE0_2 + 4'b 1111, // index[15] KMAC_KEY_SHARE0_3 + 4'b 1111, // index[16] KMAC_KEY_SHARE0_4 + 4'b 1111, // index[17] KMAC_KEY_SHARE0_5 + 4'b 1111, // index[18] KMAC_KEY_SHARE0_6 + 4'b 1111, // index[19] KMAC_KEY_SHARE0_7 + 4'b 1111, // index[20] KMAC_KEY_SHARE0_8 + 4'b 1111, // index[21] KMAC_KEY_SHARE0_9 + 4'b 1111, // index[22] KMAC_KEY_SHARE0_10 + 4'b 1111, // index[23] KMAC_KEY_SHARE0_11 + 4'b 1111, // index[24] KMAC_KEY_SHARE0_12 + 4'b 1111, // index[25] KMAC_KEY_SHARE0_13 + 4'b 1111, // index[26] KMAC_KEY_SHARE0_14 + 4'b 1111, // index[27] KMAC_KEY_SHARE0_15 + 4'b 1111, // index[28] KMAC_KEY_SHARE1_0 + 4'b 1111, // index[29] KMAC_KEY_SHARE1_1 + 4'b 1111, // index[30] KMAC_KEY_SHARE1_2 + 4'b 1111, // index[31] KMAC_KEY_SHARE1_3 + 4'b 1111, // index[32] KMAC_KEY_SHARE1_4 + 4'b 1111, // index[33] KMAC_KEY_SHARE1_5 + 4'b 1111, // index[34] KMAC_KEY_SHARE1_6 + 4'b 1111, // index[35] KMAC_KEY_SHARE1_7 + 4'b 1111, // index[36] KMAC_KEY_SHARE1_8 + 4'b 1111, // index[37] KMAC_KEY_SHARE1_9 + 4'b 1111, // index[38] KMAC_KEY_SHARE1_10 + 4'b 1111, // index[39] KMAC_KEY_SHARE1_11 + 4'b 1111, // index[40] KMAC_KEY_SHARE1_12 + 4'b 1111, // index[41] KMAC_KEY_SHARE1_13 + 4'b 1111, // index[42] KMAC_KEY_SHARE1_14 + 4'b 1111, // index[43] KMAC_KEY_SHARE1_15 + 4'b 0001, // index[44] KMAC_KEY_LEN + 4'b 1111, // index[45] KMAC_PREFIX_0 + 4'b 1111, // index[46] KMAC_PREFIX_1 + 4'b 1111, // index[47] KMAC_PREFIX_2 + 4'b 1111, // index[48] KMAC_PREFIX_3 + 4'b 1111, // index[49] KMAC_PREFIX_4 + 4'b 1111, // index[50] KMAC_PREFIX_5 + 4'b 1111, // index[51] KMAC_PREFIX_6 + 4'b 1111, // index[52] KMAC_PREFIX_7 + 4'b 1111, // index[53] KMAC_PREFIX_8 + 4'b 1111, // index[54] KMAC_PREFIX_9 + 4'b 1111, // index[55] KMAC_PREFIX_10 + 4'b 1111 // index[56] KMAC_ERR_CODE + }; + +endpackage diff --git a/src/caliptra_ss_lc_ctrl/rtl/kmac_reg_top.sv b/src/caliptra_ss_lc_ctrl/rtl/kmac_reg_top.sv new file mode 100644 index 0000000..6c7d3c0 --- /dev/null +++ b/src/caliptra_ss_lc_ctrl/rtl/kmac_reg_top.sv @@ -0,0 +1,3328 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Top module auto-generated by `reggen` + +`include "caliptra_prim_assert.sv" + +module kmac_reg_top ( + input clk_i, + input rst_ni, + input rst_shadowed_ni, + input tlul_pkg::tl_h2d_t tl_i, + output tlul_pkg::tl_d2h_t tl_o, + + // Output port for window + output tlul_pkg::tl_h2d_t tl_win_o [2], + input tlul_pkg::tl_d2h_t tl_win_i [2], + + // To HW + output kmac_reg_pkg::kmac_reg2hw_t reg2hw, // Write + input kmac_reg_pkg::kmac_hw2reg_t hw2reg, // Read + + output logic shadowed_storage_err_o, + output logic shadowed_update_err_o, + + // Integrity check errors + output logic intg_err_o +); + + import kmac_reg_pkg::* ; + + localparam int AW = 12; + localparam int DW = 32; + localparam int DBW = DW/8; // Byte Width + + // register signals + logic reg_we; + logic reg_re; + logic [AW-1:0] reg_addr; + logic [DW-1:0] reg_wdata; + logic [DBW-1:0] reg_be; + logic [DW-1:0] reg_rdata; + logic reg_error; + + logic addrmiss, wr_err; + + logic [DW-1:0] reg_rdata_next; + logic reg_busy; + + tlul_pkg::tl_h2d_t tl_reg_h2d; + tlul_pkg::tl_d2h_t tl_reg_d2h; + + + // incoming payload check + logic intg_err; + tlul_cmd_intg_chk u_chk ( + .tl_i(tl_i), + .err_o(intg_err) + ); + + // also check for spurious write enables + logic reg_we_err; + logic [56:0] reg_we_check; + caliptra_prim_reg_we_check #( + .OneHotWidth(57) + ) u_caliptra_prim_reg_we_check ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .oh_i (reg_we_check), + .en_i (reg_we && !addrmiss), + .err_o (reg_we_err) + ); + + logic err_q; + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + err_q <= '0; + end else if (intg_err || reg_we_err) begin + err_q <= 1'b1; + end + end + + // integrity error output is permanent and should be used for alert generation + // register errors are transactional + assign intg_err_o = err_q | intg_err | reg_we_err; + + // outgoing integrity generation + tlul_pkg::tl_d2h_t tl_o_pre; + tlul_rsp_intg_gen #( + .EnableRspIntgGen(1), + .EnableDataIntgGen(1) + ) u_rsp_intg_gen ( + .tl_i(tl_o_pre), + .tl_o(tl_o) + ); + + tlul_pkg::tl_h2d_t tl_socket_h2d [3]; + tlul_pkg::tl_d2h_t tl_socket_d2h [3]; + + logic [1:0] reg_steer; + + // socket_1n connection + assign tl_reg_h2d = tl_socket_h2d[2]; + assign tl_socket_d2h[2] = tl_reg_d2h; + + assign tl_win_o[0] = tl_socket_h2d[0]; + assign tl_socket_d2h[0] = tl_win_i[0]; + assign tl_win_o[1] = tl_socket_h2d[1]; + assign tl_socket_d2h[1] = tl_win_i[1]; + + // Create Socket_1n + tlul_socket_1n #( + .N (3), + .HReqPass (1'b1), + .HRspPass (1'b1), + .DReqPass ({3{1'b1}}), + .DRspPass ({3{1'b1}}), + .HReqDepth (4'h0), + .HRspDepth (4'h0), + .DReqDepth ({3{4'h0}}), + .DRspDepth ({3{4'h0}}), + .ExplicitErrs (1'b0) + ) u_socket ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .tl_h_i (tl_i), + .tl_h_o (tl_o_pre), + .tl_d_o (tl_socket_h2d), + .tl_d_i (tl_socket_d2h), + .dev_select_i (reg_steer) + ); + + // Create steering logic + always_comb begin + reg_steer = + tl_i.a_address[AW-1:0] inside {[1024:1535]} ? 2'd0 : + tl_i.a_address[AW-1:0] inside {[2048:4095]} ? 2'd1 : + // Default set to register + 2'd2; + + // Override this in case of an integrity error + if (intg_err) begin + reg_steer = 2'd2; + end + end + + tlul_adapter_reg #( + .RegAw(AW), + .RegDw(DW), + .EnableDataIntgGen(0) + ) u_reg_if ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + .tl_i (tl_reg_h2d), + .tl_o (tl_reg_d2h), + + .en_ifetch_i(caliptra_prim_mubi_pkg::MuBi4False), + .intg_error_o(), + + .we_o (reg_we), + .re_o (reg_re), + .addr_o (reg_addr), + .wdata_o (reg_wdata), + .be_o (reg_be), + .busy_i (reg_busy), + .rdata_i (reg_rdata), + .error_i (reg_error) + ); + + // cdc oversampling signals + + assign reg_rdata = reg_rdata_next ; + assign reg_error = addrmiss | wr_err | intg_err; + + // Define SW related signals + // Format: __{wd|we|qs} + // or _{wd|we|qs} if field == 1 or 0 + logic intr_state_we; + logic intr_state_kmac_done_qs; + logic intr_state_kmac_done_wd; + logic intr_state_fifo_empty_qs; + logic intr_state_kmac_err_qs; + logic intr_state_kmac_err_wd; + logic intr_enable_we; + logic intr_enable_kmac_done_qs; + logic intr_enable_kmac_done_wd; + logic intr_enable_fifo_empty_qs; + logic intr_enable_fifo_empty_wd; + logic intr_enable_kmac_err_qs; + logic intr_enable_kmac_err_wd; + logic intr_test_we; + logic intr_test_kmac_done_wd; + logic intr_test_fifo_empty_wd; + logic intr_test_kmac_err_wd; + logic alert_test_we; + logic alert_test_recov_operation_err_wd; + logic alert_test_fatal_fault_err_wd; + logic cfg_regwen_re; + logic cfg_regwen_qs; + logic cfg_shadowed_re; + logic cfg_shadowed_we; + logic cfg_shadowed_kmac_en_qs; + logic cfg_shadowed_kmac_en_wd; + logic cfg_shadowed_kmac_en_storage_err; + logic cfg_shadowed_kmac_en_update_err; + logic [2:0] cfg_shadowed_kstrength_qs; + logic [2:0] cfg_shadowed_kstrength_wd; + logic cfg_shadowed_kstrength_storage_err; + logic cfg_shadowed_kstrength_update_err; + logic [1:0] cfg_shadowed_mode_qs; + logic [1:0] cfg_shadowed_mode_wd; + logic cfg_shadowed_mode_storage_err; + logic cfg_shadowed_mode_update_err; + logic cfg_shadowed_msg_endianness_qs; + logic cfg_shadowed_msg_endianness_wd; + logic cfg_shadowed_msg_endianness_storage_err; + logic cfg_shadowed_msg_endianness_update_err; + logic cfg_shadowed_state_endianness_qs; + logic cfg_shadowed_state_endianness_wd; + logic cfg_shadowed_state_endianness_storage_err; + logic cfg_shadowed_state_endianness_update_err; + logic cfg_shadowed_sideload_qs; + logic cfg_shadowed_sideload_wd; + logic cfg_shadowed_sideload_storage_err; + logic cfg_shadowed_sideload_update_err; + logic [1:0] cfg_shadowed_entropy_mode_qs; + logic [1:0] cfg_shadowed_entropy_mode_wd; + logic cfg_shadowed_entropy_mode_storage_err; + logic cfg_shadowed_entropy_mode_update_err; + logic cfg_shadowed_entropy_fast_process_qs; + logic cfg_shadowed_entropy_fast_process_wd; + logic cfg_shadowed_entropy_fast_process_storage_err; + logic cfg_shadowed_entropy_fast_process_update_err; + logic cfg_shadowed_msg_mask_qs; + logic cfg_shadowed_msg_mask_wd; + logic cfg_shadowed_msg_mask_storage_err; + logic cfg_shadowed_msg_mask_update_err; + logic cfg_shadowed_entropy_ready_qs; + logic cfg_shadowed_entropy_ready_wd; + logic cfg_shadowed_entropy_ready_storage_err; + logic cfg_shadowed_entropy_ready_update_err; + logic cfg_shadowed_en_unsupported_modestrength_qs; + logic cfg_shadowed_en_unsupported_modestrength_wd; + logic cfg_shadowed_en_unsupported_modestrength_storage_err; + logic cfg_shadowed_en_unsupported_modestrength_update_err; + logic cmd_we; + logic [5:0] cmd_cmd_wd; + logic cmd_entropy_req_wd; + logic cmd_hash_cnt_clr_wd; + logic cmd_err_processed_wd; + logic status_re; + logic status_sha3_idle_qs; + logic status_sha3_absorb_qs; + logic status_sha3_squeeze_qs; + logic [4:0] status_fifo_depth_qs; + logic status_fifo_empty_qs; + logic status_fifo_full_qs; + logic status_alert_fatal_fault_qs; + logic status_alert_recov_ctrl_update_err_qs; + logic entropy_period_we; + logic [9:0] entropy_period_prescaler_qs; + logic [9:0] entropy_period_prescaler_wd; + logic [15:0] entropy_period_wait_timer_qs; + logic [15:0] entropy_period_wait_timer_wd; + logic [9:0] entropy_refresh_hash_cnt_qs; + logic entropy_refresh_threshold_shadowed_re; + logic entropy_refresh_threshold_shadowed_we; + logic [9:0] entropy_refresh_threshold_shadowed_qs; + logic [9:0] entropy_refresh_threshold_shadowed_wd; + logic entropy_refresh_threshold_shadowed_storage_err; + logic entropy_refresh_threshold_shadowed_update_err; + logic entropy_seed_we; + logic [31:0] entropy_seed_wd; + logic key_share0_0_we; + logic [31:0] key_share0_0_wd; + logic key_share0_1_we; + logic [31:0] key_share0_1_wd; + logic key_share0_2_we; + logic [31:0] key_share0_2_wd; + logic key_share0_3_we; + logic [31:0] key_share0_3_wd; + logic key_share0_4_we; + logic [31:0] key_share0_4_wd; + logic key_share0_5_we; + logic [31:0] key_share0_5_wd; + logic key_share0_6_we; + logic [31:0] key_share0_6_wd; + logic key_share0_7_we; + logic [31:0] key_share0_7_wd; + logic key_share0_8_we; + logic [31:0] key_share0_8_wd; + logic key_share0_9_we; + logic [31:0] key_share0_9_wd; + logic key_share0_10_we; + logic [31:0] key_share0_10_wd; + logic key_share0_11_we; + logic [31:0] key_share0_11_wd; + logic key_share0_12_we; + logic [31:0] key_share0_12_wd; + logic key_share0_13_we; + logic [31:0] key_share0_13_wd; + logic key_share0_14_we; + logic [31:0] key_share0_14_wd; + logic key_share0_15_we; + logic [31:0] key_share0_15_wd; + logic key_share1_0_we; + logic [31:0] key_share1_0_wd; + logic key_share1_1_we; + logic [31:0] key_share1_1_wd; + logic key_share1_2_we; + logic [31:0] key_share1_2_wd; + logic key_share1_3_we; + logic [31:0] key_share1_3_wd; + logic key_share1_4_we; + logic [31:0] key_share1_4_wd; + logic key_share1_5_we; + logic [31:0] key_share1_5_wd; + logic key_share1_6_we; + logic [31:0] key_share1_6_wd; + logic key_share1_7_we; + logic [31:0] key_share1_7_wd; + logic key_share1_8_we; + logic [31:0] key_share1_8_wd; + logic key_share1_9_we; + logic [31:0] key_share1_9_wd; + logic key_share1_10_we; + logic [31:0] key_share1_10_wd; + logic key_share1_11_we; + logic [31:0] key_share1_11_wd; + logic key_share1_12_we; + logic [31:0] key_share1_12_wd; + logic key_share1_13_we; + logic [31:0] key_share1_13_wd; + logic key_share1_14_we; + logic [31:0] key_share1_14_wd; + logic key_share1_15_we; + logic [31:0] key_share1_15_wd; + logic key_len_we; + logic [2:0] key_len_wd; + logic prefix_0_we; + logic [31:0] prefix_0_qs; + logic [31:0] prefix_0_wd; + logic prefix_1_we; + logic [31:0] prefix_1_qs; + logic [31:0] prefix_1_wd; + logic prefix_2_we; + logic [31:0] prefix_2_qs; + logic [31:0] prefix_2_wd; + logic prefix_3_we; + logic [31:0] prefix_3_qs; + logic [31:0] prefix_3_wd; + logic prefix_4_we; + logic [31:0] prefix_4_qs; + logic [31:0] prefix_4_wd; + logic prefix_5_we; + logic [31:0] prefix_5_qs; + logic [31:0] prefix_5_wd; + logic prefix_6_we; + logic [31:0] prefix_6_qs; + logic [31:0] prefix_6_wd; + logic prefix_7_we; + logic [31:0] prefix_7_qs; + logic [31:0] prefix_7_wd; + logic prefix_8_we; + logic [31:0] prefix_8_qs; + logic [31:0] prefix_8_wd; + logic prefix_9_we; + logic [31:0] prefix_9_qs; + logic [31:0] prefix_9_wd; + logic prefix_10_we; + logic [31:0] prefix_10_qs; + logic [31:0] prefix_10_wd; + logic [31:0] err_code_qs; + + // Register instances + // R[intr_state]: V(False) + // F[kmac_done]: 0:0 + caliptra_prim_subreg #( + .DW (1), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_intr_state_kmac_done ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intr_state_we), + .wd (intr_state_kmac_done_wd), + + // from internal hardware + .de (hw2reg.intr_state.kmac_done.de), + .d (hw2reg.intr_state.kmac_done.d), + + // to internal hardware + .qe (), + .q (reg2hw.intr_state.kmac_done.q), + .ds (), + + // to register interface (read) + .qs (intr_state_kmac_done_qs) + ); + + // F[fifo_empty]: 1:1 + caliptra_prim_subreg #( + .DW (1), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_intr_state_fifo_empty ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.intr_state.fifo_empty.de), + .d (hw2reg.intr_state.fifo_empty.d), + + // to internal hardware + .qe (), + .q (reg2hw.intr_state.fifo_empty.q), + .ds (), + + // to register interface (read) + .qs (intr_state_fifo_empty_qs) + ); + + // F[kmac_err]: 2:2 + caliptra_prim_subreg #( + .DW (1), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_intr_state_kmac_err ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intr_state_we), + .wd (intr_state_kmac_err_wd), + + // from internal hardware + .de (hw2reg.intr_state.kmac_err.de), + .d (hw2reg.intr_state.kmac_err.d), + + // to internal hardware + .qe (), + .q (reg2hw.intr_state.kmac_err.q), + .ds (), + + // to register interface (read) + .qs (intr_state_kmac_err_qs) + ); + + + // R[intr_enable]: V(False) + // F[kmac_done]: 0:0 + caliptra_prim_subreg #( + .DW (1), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_intr_enable_kmac_done ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intr_enable_we), + .wd (intr_enable_kmac_done_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.intr_enable.kmac_done.q), + .ds (), + + // to register interface (read) + .qs (intr_enable_kmac_done_qs) + ); + + // F[fifo_empty]: 1:1 + caliptra_prim_subreg #( + .DW (1), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_intr_enable_fifo_empty ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intr_enable_we), + .wd (intr_enable_fifo_empty_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.intr_enable.fifo_empty.q), + .ds (), + + // to register interface (read) + .qs (intr_enable_fifo_empty_qs) + ); + + // F[kmac_err]: 2:2 + caliptra_prim_subreg #( + .DW (1), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_intr_enable_kmac_err ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intr_enable_we), + .wd (intr_enable_kmac_err_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.intr_enable.kmac_err.q), + .ds (), + + // to register interface (read) + .qs (intr_enable_kmac_err_qs) + ); + + + // R[intr_test]: V(True) + logic intr_test_qe; + logic [2:0] intr_test_flds_we; + assign intr_test_qe = &intr_test_flds_we; + // F[kmac_done]: 0:0 + caliptra_prim_subreg_ext #( + .DW (1) + ) u_intr_test_kmac_done ( + .re (1'b0), + .we (intr_test_we), + .wd (intr_test_kmac_done_wd), + .d ('0), + .qre (), + .qe (intr_test_flds_we[0]), + .q (reg2hw.intr_test.kmac_done.q), + .ds (), + .qs () + ); + assign reg2hw.intr_test.kmac_done.qe = intr_test_qe; + + // F[fifo_empty]: 1:1 + caliptra_prim_subreg_ext #( + .DW (1) + ) u_intr_test_fifo_empty ( + .re (1'b0), + .we (intr_test_we), + .wd (intr_test_fifo_empty_wd), + .d ('0), + .qre (), + .qe (intr_test_flds_we[1]), + .q (reg2hw.intr_test.fifo_empty.q), + .ds (), + .qs () + ); + assign reg2hw.intr_test.fifo_empty.qe = intr_test_qe; + + // F[kmac_err]: 2:2 + caliptra_prim_subreg_ext #( + .DW (1) + ) u_intr_test_kmac_err ( + .re (1'b0), + .we (intr_test_we), + .wd (intr_test_kmac_err_wd), + .d ('0), + .qre (), + .qe (intr_test_flds_we[2]), + .q (reg2hw.intr_test.kmac_err.q), + .ds (), + .qs () + ); + assign reg2hw.intr_test.kmac_err.qe = intr_test_qe; + + + // R[alert_test]: V(True) + logic alert_test_qe; + logic [1:0] alert_test_flds_we; + assign alert_test_qe = &alert_test_flds_we; + // F[recov_operation_err]: 0:0 + caliptra_prim_subreg_ext #( + .DW (1) + ) u_alert_test_recov_operation_err ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_recov_operation_err_wd), + .d ('0), + .qre (), + .qe (alert_test_flds_we[0]), + .q (reg2hw.alert_test.recov_operation_err.q), + .ds (), + .qs () + ); + assign reg2hw.alert_test.recov_operation_err.qe = alert_test_qe; + + // F[fatal_fault_err]: 1:1 + caliptra_prim_subreg_ext #( + .DW (1) + ) u_alert_test_fatal_fault_err ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_fatal_fault_err_wd), + .d ('0), + .qre (), + .qe (alert_test_flds_we[1]), + .q (reg2hw.alert_test.fatal_fault_err.q), + .ds (), + .qs () + ); + assign reg2hw.alert_test.fatal_fault_err.qe = alert_test_qe; + + + // R[cfg_regwen]: V(True) + caliptra_prim_subreg_ext #( + .DW (1) + ) u_cfg_regwen ( + .re (cfg_regwen_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.cfg_regwen.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (cfg_regwen_qs) + ); + + + // R[cfg_shadowed]: V(False) + logic cfg_shadowed_qe; + logic [10:0] cfg_shadowed_flds_we; + caliptra_prim_flop #( + .Width(1), + .ResetValue(0) + ) u_cfg_shadowed0_qe ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .d_i(&cfg_shadowed_flds_we), + .q_o(cfg_shadowed_qe) + ); + // Create REGWEN-gated WE signal + logic cfg_shadowed_gated_we; + assign cfg_shadowed_gated_we = cfg_shadowed_we & cfg_regwen_qs; + // F[kmac_en]: 0:0 + caliptra_prim_subreg_shadow #( + .DW (1), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cfg_shadowed_kmac_en ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (cfg_shadowed_re), + .we (cfg_shadowed_gated_we), + .wd (cfg_shadowed_kmac_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (cfg_shadowed_flds_we[0]), + .q (reg2hw.cfg_shadowed.kmac_en.q), + .ds (), + + // to register interface (read) + .qs (cfg_shadowed_kmac_en_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (cfg_shadowed_kmac_en_update_err), + .err_storage (cfg_shadowed_kmac_en_storage_err) + ); + assign reg2hw.cfg_shadowed.kmac_en.qe = cfg_shadowed_qe; + + // F[kstrength]: 3:1 + caliptra_prim_subreg_shadow #( + .DW (3), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW), + .RESVAL (3'h0), + .Mubi (1'b0) + ) u_cfg_shadowed_kstrength ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (cfg_shadowed_re), + .we (cfg_shadowed_gated_we), + .wd (cfg_shadowed_kstrength_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (cfg_shadowed_flds_we[1]), + .q (reg2hw.cfg_shadowed.kstrength.q), + .ds (), + + // to register interface (read) + .qs (cfg_shadowed_kstrength_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (cfg_shadowed_kstrength_update_err), + .err_storage (cfg_shadowed_kstrength_storage_err) + ); + assign reg2hw.cfg_shadowed.kstrength.qe = cfg_shadowed_qe; + + // F[mode]: 5:4 + caliptra_prim_subreg_shadow #( + .DW (2), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_cfg_shadowed_mode ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (cfg_shadowed_re), + .we (cfg_shadowed_gated_we), + .wd (cfg_shadowed_mode_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (cfg_shadowed_flds_we[2]), + .q (reg2hw.cfg_shadowed.mode.q), + .ds (), + + // to register interface (read) + .qs (cfg_shadowed_mode_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (cfg_shadowed_mode_update_err), + .err_storage (cfg_shadowed_mode_storage_err) + ); + assign reg2hw.cfg_shadowed.mode.qe = cfg_shadowed_qe; + + // F[msg_endianness]: 8:8 + caliptra_prim_subreg_shadow #( + .DW (1), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cfg_shadowed_msg_endianness ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (cfg_shadowed_re), + .we (cfg_shadowed_gated_we), + .wd (cfg_shadowed_msg_endianness_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (cfg_shadowed_flds_we[3]), + .q (reg2hw.cfg_shadowed.msg_endianness.q), + .ds (), + + // to register interface (read) + .qs (cfg_shadowed_msg_endianness_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (cfg_shadowed_msg_endianness_update_err), + .err_storage (cfg_shadowed_msg_endianness_storage_err) + ); + assign reg2hw.cfg_shadowed.msg_endianness.qe = cfg_shadowed_qe; + + // F[state_endianness]: 9:9 + caliptra_prim_subreg_shadow #( + .DW (1), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cfg_shadowed_state_endianness ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (cfg_shadowed_re), + .we (cfg_shadowed_gated_we), + .wd (cfg_shadowed_state_endianness_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (cfg_shadowed_flds_we[4]), + .q (reg2hw.cfg_shadowed.state_endianness.q), + .ds (), + + // to register interface (read) + .qs (cfg_shadowed_state_endianness_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (cfg_shadowed_state_endianness_update_err), + .err_storage (cfg_shadowed_state_endianness_storage_err) + ); + assign reg2hw.cfg_shadowed.state_endianness.qe = cfg_shadowed_qe; + + // F[sideload]: 12:12 + caliptra_prim_subreg_shadow #( + .DW (1), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cfg_shadowed_sideload ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (cfg_shadowed_re), + .we (cfg_shadowed_gated_we), + .wd (cfg_shadowed_sideload_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (cfg_shadowed_flds_we[5]), + .q (reg2hw.cfg_shadowed.sideload.q), + .ds (), + + // to register interface (read) + .qs (cfg_shadowed_sideload_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (cfg_shadowed_sideload_update_err), + .err_storage (cfg_shadowed_sideload_storage_err) + ); + assign reg2hw.cfg_shadowed.sideload.qe = cfg_shadowed_qe; + + // F[entropy_mode]: 17:16 + caliptra_prim_subreg_shadow #( + .DW (2), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_cfg_shadowed_entropy_mode ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (cfg_shadowed_re), + .we (cfg_shadowed_gated_we), + .wd (cfg_shadowed_entropy_mode_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (cfg_shadowed_flds_we[6]), + .q (reg2hw.cfg_shadowed.entropy_mode.q), + .ds (), + + // to register interface (read) + .qs (cfg_shadowed_entropy_mode_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (cfg_shadowed_entropy_mode_update_err), + .err_storage (cfg_shadowed_entropy_mode_storage_err) + ); + assign reg2hw.cfg_shadowed.entropy_mode.qe = cfg_shadowed_qe; + + // F[entropy_fast_process]: 19:19 + caliptra_prim_subreg_shadow #( + .DW (1), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cfg_shadowed_entropy_fast_process ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (cfg_shadowed_re), + .we (cfg_shadowed_gated_we), + .wd (cfg_shadowed_entropy_fast_process_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (cfg_shadowed_flds_we[7]), + .q (reg2hw.cfg_shadowed.entropy_fast_process.q), + .ds (), + + // to register interface (read) + .qs (cfg_shadowed_entropy_fast_process_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (cfg_shadowed_entropy_fast_process_update_err), + .err_storage (cfg_shadowed_entropy_fast_process_storage_err) + ); + assign reg2hw.cfg_shadowed.entropy_fast_process.qe = cfg_shadowed_qe; + + // F[msg_mask]: 20:20 + caliptra_prim_subreg_shadow #( + .DW (1), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cfg_shadowed_msg_mask ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (cfg_shadowed_re), + .we (cfg_shadowed_gated_we), + .wd (cfg_shadowed_msg_mask_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (cfg_shadowed_flds_we[8]), + .q (reg2hw.cfg_shadowed.msg_mask.q), + .ds (), + + // to register interface (read) + .qs (cfg_shadowed_msg_mask_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (cfg_shadowed_msg_mask_update_err), + .err_storage (cfg_shadowed_msg_mask_storage_err) + ); + assign reg2hw.cfg_shadowed.msg_mask.qe = cfg_shadowed_qe; + + // F[entropy_ready]: 24:24 + caliptra_prim_subreg_shadow #( + .DW (1), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cfg_shadowed_entropy_ready ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (cfg_shadowed_re), + .we (cfg_shadowed_gated_we), + .wd (cfg_shadowed_entropy_ready_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (cfg_shadowed_flds_we[9]), + .q (reg2hw.cfg_shadowed.entropy_ready.q), + .ds (), + + // to register interface (read) + .qs (cfg_shadowed_entropy_ready_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (cfg_shadowed_entropy_ready_update_err), + .err_storage (cfg_shadowed_entropy_ready_storage_err) + ); + assign reg2hw.cfg_shadowed.entropy_ready.qe = cfg_shadowed_qe; + + // F[en_unsupported_modestrength]: 26:26 + caliptra_prim_subreg_shadow #( + .DW (1), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cfg_shadowed_en_unsupported_modestrength ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (cfg_shadowed_re), + .we (cfg_shadowed_gated_we), + .wd (cfg_shadowed_en_unsupported_modestrength_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (cfg_shadowed_flds_we[10]), + .q (reg2hw.cfg_shadowed.en_unsupported_modestrength.q), + .ds (), + + // to register interface (read) + .qs (cfg_shadowed_en_unsupported_modestrength_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (cfg_shadowed_en_unsupported_modestrength_update_err), + .err_storage (cfg_shadowed_en_unsupported_modestrength_storage_err) + ); + assign reg2hw.cfg_shadowed.en_unsupported_modestrength.qe = cfg_shadowed_qe; + + + // R[cmd]: V(True) + logic cmd_qe; + logic [3:0] cmd_flds_we; + assign cmd_qe = &cmd_flds_we; + // F[cmd]: 5:0 + caliptra_prim_subreg_ext #( + .DW (6) + ) u_cmd_cmd ( + .re (1'b0), + .we (cmd_we), + .wd (cmd_cmd_wd), + .d ('0), + .qre (), + .qe (cmd_flds_we[0]), + .q (reg2hw.cmd.cmd.q), + .ds (), + .qs () + ); + assign reg2hw.cmd.cmd.qe = cmd_qe; + + // F[entropy_req]: 8:8 + caliptra_prim_subreg_ext #( + .DW (1) + ) u_cmd_entropy_req ( + .re (1'b0), + .we (cmd_we), + .wd (cmd_entropy_req_wd), + .d ('0), + .qre (), + .qe (cmd_flds_we[1]), + .q (reg2hw.cmd.entropy_req.q), + .ds (), + .qs () + ); + assign reg2hw.cmd.entropy_req.qe = cmd_qe; + + // F[hash_cnt_clr]: 9:9 + caliptra_prim_subreg_ext #( + .DW (1) + ) u_cmd_hash_cnt_clr ( + .re (1'b0), + .we (cmd_we), + .wd (cmd_hash_cnt_clr_wd), + .d ('0), + .qre (), + .qe (cmd_flds_we[2]), + .q (reg2hw.cmd.hash_cnt_clr.q), + .ds (), + .qs () + ); + assign reg2hw.cmd.hash_cnt_clr.qe = cmd_qe; + + // F[err_processed]: 10:10 + caliptra_prim_subreg_ext #( + .DW (1) + ) u_cmd_err_processed ( + .re (1'b0), + .we (cmd_we), + .wd (cmd_err_processed_wd), + .d ('0), + .qre (), + .qe (cmd_flds_we[3]), + .q (reg2hw.cmd.err_processed.q), + .ds (), + .qs () + ); + assign reg2hw.cmd.err_processed.qe = cmd_qe; + + + // R[status]: V(True) + // F[sha3_idle]: 0:0 + caliptra_prim_subreg_ext #( + .DW (1) + ) u_status_sha3_idle ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.sha3_idle.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_sha3_idle_qs) + ); + + // F[sha3_absorb]: 1:1 + caliptra_prim_subreg_ext #( + .DW (1) + ) u_status_sha3_absorb ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.sha3_absorb.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_sha3_absorb_qs) + ); + + // F[sha3_squeeze]: 2:2 + caliptra_prim_subreg_ext #( + .DW (1) + ) u_status_sha3_squeeze ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.sha3_squeeze.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_sha3_squeeze_qs) + ); + + // F[fifo_depth]: 12:8 + caliptra_prim_subreg_ext #( + .DW (5) + ) u_status_fifo_depth ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.fifo_depth.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_fifo_depth_qs) + ); + + // F[fifo_empty]: 14:14 + caliptra_prim_subreg_ext #( + .DW (1) + ) u_status_fifo_empty ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.fifo_empty.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_fifo_empty_qs) + ); + + // F[fifo_full]: 15:15 + caliptra_prim_subreg_ext #( + .DW (1) + ) u_status_fifo_full ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.fifo_full.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_fifo_full_qs) + ); + + // F[alert_fatal_fault]: 16:16 + caliptra_prim_subreg_ext #( + .DW (1) + ) u_status_alert_fatal_fault ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.alert_fatal_fault.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_alert_fatal_fault_qs) + ); + + // F[alert_recov_ctrl_update_err]: 17:17 + caliptra_prim_subreg_ext #( + .DW (1) + ) u_status_alert_recov_ctrl_update_err ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.alert_recov_ctrl_update_err.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_alert_recov_ctrl_update_err_qs) + ); + + + // R[entropy_period]: V(False) + // Create REGWEN-gated WE signal + logic entropy_period_gated_we; + assign entropy_period_gated_we = entropy_period_we & cfg_regwen_qs; + // F[prescaler]: 9:0 + caliptra_prim_subreg #( + .DW (10), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW), + .RESVAL (10'h0), + .Mubi (1'b0) + ) u_entropy_period_prescaler ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (entropy_period_gated_we), + .wd (entropy_period_prescaler_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.entropy_period.prescaler.q), + .ds (), + + // to register interface (read) + .qs (entropy_period_prescaler_qs) + ); + + // F[wait_timer]: 31:16 + caliptra_prim_subreg #( + .DW (16), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_entropy_period_wait_timer ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (entropy_period_gated_we), + .wd (entropy_period_wait_timer_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.entropy_period.wait_timer.q), + .ds (), + + // to register interface (read) + .qs (entropy_period_wait_timer_qs) + ); + + + // R[entropy_refresh_hash_cnt]: V(False) + caliptra_prim_subreg #( + .DW (10), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO), + .RESVAL (10'h0), + .Mubi (1'b0) + ) u_entropy_refresh_hash_cnt ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.entropy_refresh_hash_cnt.de), + .d (hw2reg.entropy_refresh_hash_cnt.d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (entropy_refresh_hash_cnt_qs) + ); + + + // R[entropy_refresh_threshold_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic entropy_refresh_threshold_shadowed_gated_we; + assign entropy_refresh_threshold_shadowed_gated_we = + entropy_refresh_threshold_shadowed_we & cfg_regwen_qs; + caliptra_prim_subreg_shadow #( + .DW (10), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW), + .RESVAL (10'h0), + .Mubi (1'b0) + ) u_entropy_refresh_threshold_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (entropy_refresh_threshold_shadowed_re), + .we (entropy_refresh_threshold_shadowed_gated_we), + .wd (entropy_refresh_threshold_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.entropy_refresh_threshold_shadowed.q), + .ds (), + + // to register interface (read) + .qs (entropy_refresh_threshold_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (entropy_refresh_threshold_shadowed_update_err), + .err_storage (entropy_refresh_threshold_shadowed_storage_err) + ); + + + // R[entropy_seed]: V(True) + logic entropy_seed_qe; + logic [0:0] entropy_seed_flds_we; + assign entropy_seed_qe = &entropy_seed_flds_we; + caliptra_prim_subreg_ext #( + .DW (32) + ) u_entropy_seed ( + .re (1'b0), + .we (entropy_seed_we), + .wd (entropy_seed_wd), + .d ('0), + .qre (), + .qe (entropy_seed_flds_we[0]), + .q (reg2hw.entropy_seed.q), + .ds (), + .qs () + ); + assign reg2hw.entropy_seed.qe = entropy_seed_qe; + + + // Subregister 0 of Multireg key_share0 + // R[key_share0_0]: V(True) + logic key_share0_0_qe; + logic [0:0] key_share0_0_flds_we; + assign key_share0_0_qe = &key_share0_0_flds_we; + // Create REGWEN-gated WE signal + logic key_share0_0_gated_we; + assign key_share0_0_gated_we = key_share0_0_we & cfg_regwen_qs; + caliptra_prim_subreg_ext #( + .DW (32) + ) u_key_share0_0 ( + .re (1'b0), + .we (key_share0_0_gated_we), + .wd (key_share0_0_wd), + .d ('0), + .qre (), + .qe (key_share0_0_flds_we[0]), + .q (reg2hw.key_share0[0].q), + .ds (), + .qs () + ); + assign reg2hw.key_share0[0].qe = key_share0_0_qe; + + + // Subregister 1 of Multireg key_share0 + // R[key_share0_1]: V(True) + logic key_share0_1_qe; + logic [0:0] key_share0_1_flds_we; + assign key_share0_1_qe = &key_share0_1_flds_we; + // Create REGWEN-gated WE signal + logic key_share0_1_gated_we; + assign key_share0_1_gated_we = key_share0_1_we & cfg_regwen_qs; + caliptra_prim_subreg_ext #( + .DW (32) + ) u_key_share0_1 ( + .re (1'b0), + .we (key_share0_1_gated_we), + .wd (key_share0_1_wd), + .d ('0), + .qre (), + .qe (key_share0_1_flds_we[0]), + .q (reg2hw.key_share0[1].q), + .ds (), + .qs () + ); + assign reg2hw.key_share0[1].qe = key_share0_1_qe; + + + // Subregister 2 of Multireg key_share0 + // R[key_share0_2]: V(True) + logic key_share0_2_qe; + logic [0:0] key_share0_2_flds_we; + assign key_share0_2_qe = &key_share0_2_flds_we; + // Create REGWEN-gated WE signal + logic key_share0_2_gated_we; + assign key_share0_2_gated_we = key_share0_2_we & cfg_regwen_qs; + caliptra_prim_subreg_ext #( + .DW (32) + ) u_key_share0_2 ( + .re (1'b0), + .we (key_share0_2_gated_we), + .wd (key_share0_2_wd), + .d ('0), + .qre (), + .qe (key_share0_2_flds_we[0]), + .q (reg2hw.key_share0[2].q), + .ds (), + .qs () + ); + assign reg2hw.key_share0[2].qe = key_share0_2_qe; + + + // Subregister 3 of Multireg key_share0 + // R[key_share0_3]: V(True) + logic key_share0_3_qe; + logic [0:0] key_share0_3_flds_we; + assign key_share0_3_qe = &key_share0_3_flds_we; + // Create REGWEN-gated WE signal + logic key_share0_3_gated_we; + assign key_share0_3_gated_we = key_share0_3_we & cfg_regwen_qs; + caliptra_prim_subreg_ext #( + .DW (32) + ) u_key_share0_3 ( + .re (1'b0), + .we (key_share0_3_gated_we), + .wd (key_share0_3_wd), + .d ('0), + .qre (), + .qe (key_share0_3_flds_we[0]), + .q (reg2hw.key_share0[3].q), + .ds (), + .qs () + ); + assign reg2hw.key_share0[3].qe = key_share0_3_qe; + + + // Subregister 4 of Multireg key_share0 + // R[key_share0_4]: V(True) + logic key_share0_4_qe; + logic [0:0] key_share0_4_flds_we; + assign key_share0_4_qe = &key_share0_4_flds_we; + // Create REGWEN-gated WE signal + logic key_share0_4_gated_we; + assign key_share0_4_gated_we = key_share0_4_we & cfg_regwen_qs; + caliptra_prim_subreg_ext #( + .DW (32) + ) u_key_share0_4 ( + .re (1'b0), + .we (key_share0_4_gated_we), + .wd (key_share0_4_wd), + .d ('0), + .qre (), + .qe (key_share0_4_flds_we[0]), + .q (reg2hw.key_share0[4].q), + .ds (), + .qs () + ); + assign reg2hw.key_share0[4].qe = key_share0_4_qe; + + + // Subregister 5 of Multireg key_share0 + // R[key_share0_5]: V(True) + logic key_share0_5_qe; + logic [0:0] key_share0_5_flds_we; + assign key_share0_5_qe = &key_share0_5_flds_we; + // Create REGWEN-gated WE signal + logic key_share0_5_gated_we; + assign key_share0_5_gated_we = key_share0_5_we & cfg_regwen_qs; + caliptra_prim_subreg_ext #( + .DW (32) + ) u_key_share0_5 ( + .re (1'b0), + .we (key_share0_5_gated_we), + .wd (key_share0_5_wd), + .d ('0), + .qre (), + .qe (key_share0_5_flds_we[0]), + .q (reg2hw.key_share0[5].q), + .ds (), + .qs () + ); + assign reg2hw.key_share0[5].qe = key_share0_5_qe; + + + // Subregister 6 of Multireg key_share0 + // R[key_share0_6]: V(True) + logic key_share0_6_qe; + logic [0:0] key_share0_6_flds_we; + assign key_share0_6_qe = &key_share0_6_flds_we; + // Create REGWEN-gated WE signal + logic key_share0_6_gated_we; + assign key_share0_6_gated_we = key_share0_6_we & cfg_regwen_qs; + caliptra_prim_subreg_ext #( + .DW (32) + ) u_key_share0_6 ( + .re (1'b0), + .we (key_share0_6_gated_we), + .wd (key_share0_6_wd), + .d ('0), + .qre (), + .qe (key_share0_6_flds_we[0]), + .q (reg2hw.key_share0[6].q), + .ds (), + .qs () + ); + assign reg2hw.key_share0[6].qe = key_share0_6_qe; + + + // Subregister 7 of Multireg key_share0 + // R[key_share0_7]: V(True) + logic key_share0_7_qe; + logic [0:0] key_share0_7_flds_we; + assign key_share0_7_qe = &key_share0_7_flds_we; + // Create REGWEN-gated WE signal + logic key_share0_7_gated_we; + assign key_share0_7_gated_we = key_share0_7_we & cfg_regwen_qs; + caliptra_prim_subreg_ext #( + .DW (32) + ) u_key_share0_7 ( + .re (1'b0), + .we (key_share0_7_gated_we), + .wd (key_share0_7_wd), + .d ('0), + .qre (), + .qe (key_share0_7_flds_we[0]), + .q (reg2hw.key_share0[7].q), + .ds (), + .qs () + ); + assign reg2hw.key_share0[7].qe = key_share0_7_qe; + + + // Subregister 8 of Multireg key_share0 + // R[key_share0_8]: V(True) + logic key_share0_8_qe; + logic [0:0] key_share0_8_flds_we; + assign key_share0_8_qe = &key_share0_8_flds_we; + // Create REGWEN-gated WE signal + logic key_share0_8_gated_we; + assign key_share0_8_gated_we = key_share0_8_we & cfg_regwen_qs; + caliptra_prim_subreg_ext #( + .DW (32) + ) u_key_share0_8 ( + .re (1'b0), + .we (key_share0_8_gated_we), + .wd (key_share0_8_wd), + .d ('0), + .qre (), + .qe (key_share0_8_flds_we[0]), + .q (reg2hw.key_share0[8].q), + .ds (), + .qs () + ); + assign reg2hw.key_share0[8].qe = key_share0_8_qe; + + + // Subregister 9 of Multireg key_share0 + // R[key_share0_9]: V(True) + logic key_share0_9_qe; + logic [0:0] key_share0_9_flds_we; + assign key_share0_9_qe = &key_share0_9_flds_we; + // Create REGWEN-gated WE signal + logic key_share0_9_gated_we; + assign key_share0_9_gated_we = key_share0_9_we & cfg_regwen_qs; + caliptra_prim_subreg_ext #( + .DW (32) + ) u_key_share0_9 ( + .re (1'b0), + .we (key_share0_9_gated_we), + .wd (key_share0_9_wd), + .d ('0), + .qre (), + .qe (key_share0_9_flds_we[0]), + .q (reg2hw.key_share0[9].q), + .ds (), + .qs () + ); + assign reg2hw.key_share0[9].qe = key_share0_9_qe; + + + // Subregister 10 of Multireg key_share0 + // R[key_share0_10]: V(True) + logic key_share0_10_qe; + logic [0:0] key_share0_10_flds_we; + assign key_share0_10_qe = &key_share0_10_flds_we; + // Create REGWEN-gated WE signal + logic key_share0_10_gated_we; + assign key_share0_10_gated_we = key_share0_10_we & cfg_regwen_qs; + caliptra_prim_subreg_ext #( + .DW (32) + ) u_key_share0_10 ( + .re (1'b0), + .we (key_share0_10_gated_we), + .wd (key_share0_10_wd), + .d ('0), + .qre (), + .qe (key_share0_10_flds_we[0]), + .q (reg2hw.key_share0[10].q), + .ds (), + .qs () + ); + assign reg2hw.key_share0[10].qe = key_share0_10_qe; + + + // Subregister 11 of Multireg key_share0 + // R[key_share0_11]: V(True) + logic key_share0_11_qe; + logic [0:0] key_share0_11_flds_we; + assign key_share0_11_qe = &key_share0_11_flds_we; + // Create REGWEN-gated WE signal + logic key_share0_11_gated_we; + assign key_share0_11_gated_we = key_share0_11_we & cfg_regwen_qs; + caliptra_prim_subreg_ext #( + .DW (32) + ) u_key_share0_11 ( + .re (1'b0), + .we (key_share0_11_gated_we), + .wd (key_share0_11_wd), + .d ('0), + .qre (), + .qe (key_share0_11_flds_we[0]), + .q (reg2hw.key_share0[11].q), + .ds (), + .qs () + ); + assign reg2hw.key_share0[11].qe = key_share0_11_qe; + + + // Subregister 12 of Multireg key_share0 + // R[key_share0_12]: V(True) + logic key_share0_12_qe; + logic [0:0] key_share0_12_flds_we; + assign key_share0_12_qe = &key_share0_12_flds_we; + // Create REGWEN-gated WE signal + logic key_share0_12_gated_we; + assign key_share0_12_gated_we = key_share0_12_we & cfg_regwen_qs; + caliptra_prim_subreg_ext #( + .DW (32) + ) u_key_share0_12 ( + .re (1'b0), + .we (key_share0_12_gated_we), + .wd (key_share0_12_wd), + .d ('0), + .qre (), + .qe (key_share0_12_flds_we[0]), + .q (reg2hw.key_share0[12].q), + .ds (), + .qs () + ); + assign reg2hw.key_share0[12].qe = key_share0_12_qe; + + + // Subregister 13 of Multireg key_share0 + // R[key_share0_13]: V(True) + logic key_share0_13_qe; + logic [0:0] key_share0_13_flds_we; + assign key_share0_13_qe = &key_share0_13_flds_we; + // Create REGWEN-gated WE signal + logic key_share0_13_gated_we; + assign key_share0_13_gated_we = key_share0_13_we & cfg_regwen_qs; + caliptra_prim_subreg_ext #( + .DW (32) + ) u_key_share0_13 ( + .re (1'b0), + .we (key_share0_13_gated_we), + .wd (key_share0_13_wd), + .d ('0), + .qre (), + .qe (key_share0_13_flds_we[0]), + .q (reg2hw.key_share0[13].q), + .ds (), + .qs () + ); + assign reg2hw.key_share0[13].qe = key_share0_13_qe; + + + // Subregister 14 of Multireg key_share0 + // R[key_share0_14]: V(True) + logic key_share0_14_qe; + logic [0:0] key_share0_14_flds_we; + assign key_share0_14_qe = &key_share0_14_flds_we; + // Create REGWEN-gated WE signal + logic key_share0_14_gated_we; + assign key_share0_14_gated_we = key_share0_14_we & cfg_regwen_qs; + caliptra_prim_subreg_ext #( + .DW (32) + ) u_key_share0_14 ( + .re (1'b0), + .we (key_share0_14_gated_we), + .wd (key_share0_14_wd), + .d ('0), + .qre (), + .qe (key_share0_14_flds_we[0]), + .q (reg2hw.key_share0[14].q), + .ds (), + .qs () + ); + assign reg2hw.key_share0[14].qe = key_share0_14_qe; + + + // Subregister 15 of Multireg key_share0 + // R[key_share0_15]: V(True) + logic key_share0_15_qe; + logic [0:0] key_share0_15_flds_we; + assign key_share0_15_qe = &key_share0_15_flds_we; + // Create REGWEN-gated WE signal + logic key_share0_15_gated_we; + assign key_share0_15_gated_we = key_share0_15_we & cfg_regwen_qs; + caliptra_prim_subreg_ext #( + .DW (32) + ) u_key_share0_15 ( + .re (1'b0), + .we (key_share0_15_gated_we), + .wd (key_share0_15_wd), + .d ('0), + .qre (), + .qe (key_share0_15_flds_we[0]), + .q (reg2hw.key_share0[15].q), + .ds (), + .qs () + ); + assign reg2hw.key_share0[15].qe = key_share0_15_qe; + + + // Subregister 0 of Multireg key_share1 + // R[key_share1_0]: V(True) + logic key_share1_0_qe; + logic [0:0] key_share1_0_flds_we; + assign key_share1_0_qe = &key_share1_0_flds_we; + // Create REGWEN-gated WE signal + logic key_share1_0_gated_we; + assign key_share1_0_gated_we = key_share1_0_we & cfg_regwen_qs; + caliptra_prim_subreg_ext #( + .DW (32) + ) u_key_share1_0 ( + .re (1'b0), + .we (key_share1_0_gated_we), + .wd (key_share1_0_wd), + .d ('0), + .qre (), + .qe (key_share1_0_flds_we[0]), + .q (reg2hw.key_share1[0].q), + .ds (), + .qs () + ); + assign reg2hw.key_share1[0].qe = key_share1_0_qe; + + + // Subregister 1 of Multireg key_share1 + // R[key_share1_1]: V(True) + logic key_share1_1_qe; + logic [0:0] key_share1_1_flds_we; + assign key_share1_1_qe = &key_share1_1_flds_we; + // Create REGWEN-gated WE signal + logic key_share1_1_gated_we; + assign key_share1_1_gated_we = key_share1_1_we & cfg_regwen_qs; + caliptra_prim_subreg_ext #( + .DW (32) + ) u_key_share1_1 ( + .re (1'b0), + .we (key_share1_1_gated_we), + .wd (key_share1_1_wd), + .d ('0), + .qre (), + .qe (key_share1_1_flds_we[0]), + .q (reg2hw.key_share1[1].q), + .ds (), + .qs () + ); + assign reg2hw.key_share1[1].qe = key_share1_1_qe; + + + // Subregister 2 of Multireg key_share1 + // R[key_share1_2]: V(True) + logic key_share1_2_qe; + logic [0:0] key_share1_2_flds_we; + assign key_share1_2_qe = &key_share1_2_flds_we; + // Create REGWEN-gated WE signal + logic key_share1_2_gated_we; + assign key_share1_2_gated_we = key_share1_2_we & cfg_regwen_qs; + caliptra_prim_subreg_ext #( + .DW (32) + ) u_key_share1_2 ( + .re (1'b0), + .we (key_share1_2_gated_we), + .wd (key_share1_2_wd), + .d ('0), + .qre (), + .qe (key_share1_2_flds_we[0]), + .q (reg2hw.key_share1[2].q), + .ds (), + .qs () + ); + assign reg2hw.key_share1[2].qe = key_share1_2_qe; + + + // Subregister 3 of Multireg key_share1 + // R[key_share1_3]: V(True) + logic key_share1_3_qe; + logic [0:0] key_share1_3_flds_we; + assign key_share1_3_qe = &key_share1_3_flds_we; + // Create REGWEN-gated WE signal + logic key_share1_3_gated_we; + assign key_share1_3_gated_we = key_share1_3_we & cfg_regwen_qs; + caliptra_prim_subreg_ext #( + .DW (32) + ) u_key_share1_3 ( + .re (1'b0), + .we (key_share1_3_gated_we), + .wd (key_share1_3_wd), + .d ('0), + .qre (), + .qe (key_share1_3_flds_we[0]), + .q (reg2hw.key_share1[3].q), + .ds (), + .qs () + ); + assign reg2hw.key_share1[3].qe = key_share1_3_qe; + + + // Subregister 4 of Multireg key_share1 + // R[key_share1_4]: V(True) + logic key_share1_4_qe; + logic [0:0] key_share1_4_flds_we; + assign key_share1_4_qe = &key_share1_4_flds_we; + // Create REGWEN-gated WE signal + logic key_share1_4_gated_we; + assign key_share1_4_gated_we = key_share1_4_we & cfg_regwen_qs; + caliptra_prim_subreg_ext #( + .DW (32) + ) u_key_share1_4 ( + .re (1'b0), + .we (key_share1_4_gated_we), + .wd (key_share1_4_wd), + .d ('0), + .qre (), + .qe (key_share1_4_flds_we[0]), + .q (reg2hw.key_share1[4].q), + .ds (), + .qs () + ); + assign reg2hw.key_share1[4].qe = key_share1_4_qe; + + + // Subregister 5 of Multireg key_share1 + // R[key_share1_5]: V(True) + logic key_share1_5_qe; + logic [0:0] key_share1_5_flds_we; + assign key_share1_5_qe = &key_share1_5_flds_we; + // Create REGWEN-gated WE signal + logic key_share1_5_gated_we; + assign key_share1_5_gated_we = key_share1_5_we & cfg_regwen_qs; + caliptra_prim_subreg_ext #( + .DW (32) + ) u_key_share1_5 ( + .re (1'b0), + .we (key_share1_5_gated_we), + .wd (key_share1_5_wd), + .d ('0), + .qre (), + .qe (key_share1_5_flds_we[0]), + .q (reg2hw.key_share1[5].q), + .ds (), + .qs () + ); + assign reg2hw.key_share1[5].qe = key_share1_5_qe; + + + // Subregister 6 of Multireg key_share1 + // R[key_share1_6]: V(True) + logic key_share1_6_qe; + logic [0:0] key_share1_6_flds_we; + assign key_share1_6_qe = &key_share1_6_flds_we; + // Create REGWEN-gated WE signal + logic key_share1_6_gated_we; + assign key_share1_6_gated_we = key_share1_6_we & cfg_regwen_qs; + caliptra_prim_subreg_ext #( + .DW (32) + ) u_key_share1_6 ( + .re (1'b0), + .we (key_share1_6_gated_we), + .wd (key_share1_6_wd), + .d ('0), + .qre (), + .qe (key_share1_6_flds_we[0]), + .q (reg2hw.key_share1[6].q), + .ds (), + .qs () + ); + assign reg2hw.key_share1[6].qe = key_share1_6_qe; + + + // Subregister 7 of Multireg key_share1 + // R[key_share1_7]: V(True) + logic key_share1_7_qe; + logic [0:0] key_share1_7_flds_we; + assign key_share1_7_qe = &key_share1_7_flds_we; + // Create REGWEN-gated WE signal + logic key_share1_7_gated_we; + assign key_share1_7_gated_we = key_share1_7_we & cfg_regwen_qs; + caliptra_prim_subreg_ext #( + .DW (32) + ) u_key_share1_7 ( + .re (1'b0), + .we (key_share1_7_gated_we), + .wd (key_share1_7_wd), + .d ('0), + .qre (), + .qe (key_share1_7_flds_we[0]), + .q (reg2hw.key_share1[7].q), + .ds (), + .qs () + ); + assign reg2hw.key_share1[7].qe = key_share1_7_qe; + + + // Subregister 8 of Multireg key_share1 + // R[key_share1_8]: V(True) + logic key_share1_8_qe; + logic [0:0] key_share1_8_flds_we; + assign key_share1_8_qe = &key_share1_8_flds_we; + // Create REGWEN-gated WE signal + logic key_share1_8_gated_we; + assign key_share1_8_gated_we = key_share1_8_we & cfg_regwen_qs; + caliptra_prim_subreg_ext #( + .DW (32) + ) u_key_share1_8 ( + .re (1'b0), + .we (key_share1_8_gated_we), + .wd (key_share1_8_wd), + .d ('0), + .qre (), + .qe (key_share1_8_flds_we[0]), + .q (reg2hw.key_share1[8].q), + .ds (), + .qs () + ); + assign reg2hw.key_share1[8].qe = key_share1_8_qe; + + + // Subregister 9 of Multireg key_share1 + // R[key_share1_9]: V(True) + logic key_share1_9_qe; + logic [0:0] key_share1_9_flds_we; + assign key_share1_9_qe = &key_share1_9_flds_we; + // Create REGWEN-gated WE signal + logic key_share1_9_gated_we; + assign key_share1_9_gated_we = key_share1_9_we & cfg_regwen_qs; + caliptra_prim_subreg_ext #( + .DW (32) + ) u_key_share1_9 ( + .re (1'b0), + .we (key_share1_9_gated_we), + .wd (key_share1_9_wd), + .d ('0), + .qre (), + .qe (key_share1_9_flds_we[0]), + .q (reg2hw.key_share1[9].q), + .ds (), + .qs () + ); + assign reg2hw.key_share1[9].qe = key_share1_9_qe; + + + // Subregister 10 of Multireg key_share1 + // R[key_share1_10]: V(True) + logic key_share1_10_qe; + logic [0:0] key_share1_10_flds_we; + assign key_share1_10_qe = &key_share1_10_flds_we; + // Create REGWEN-gated WE signal + logic key_share1_10_gated_we; + assign key_share1_10_gated_we = key_share1_10_we & cfg_regwen_qs; + caliptra_prim_subreg_ext #( + .DW (32) + ) u_key_share1_10 ( + .re (1'b0), + .we (key_share1_10_gated_we), + .wd (key_share1_10_wd), + .d ('0), + .qre (), + .qe (key_share1_10_flds_we[0]), + .q (reg2hw.key_share1[10].q), + .ds (), + .qs () + ); + assign reg2hw.key_share1[10].qe = key_share1_10_qe; + + + // Subregister 11 of Multireg key_share1 + // R[key_share1_11]: V(True) + logic key_share1_11_qe; + logic [0:0] key_share1_11_flds_we; + assign key_share1_11_qe = &key_share1_11_flds_we; + // Create REGWEN-gated WE signal + logic key_share1_11_gated_we; + assign key_share1_11_gated_we = key_share1_11_we & cfg_regwen_qs; + caliptra_prim_subreg_ext #( + .DW (32) + ) u_key_share1_11 ( + .re (1'b0), + .we (key_share1_11_gated_we), + .wd (key_share1_11_wd), + .d ('0), + .qre (), + .qe (key_share1_11_flds_we[0]), + .q (reg2hw.key_share1[11].q), + .ds (), + .qs () + ); + assign reg2hw.key_share1[11].qe = key_share1_11_qe; + + + // Subregister 12 of Multireg key_share1 + // R[key_share1_12]: V(True) + logic key_share1_12_qe; + logic [0:0] key_share1_12_flds_we; + assign key_share1_12_qe = &key_share1_12_flds_we; + // Create REGWEN-gated WE signal + logic key_share1_12_gated_we; + assign key_share1_12_gated_we = key_share1_12_we & cfg_regwen_qs; + caliptra_prim_subreg_ext #( + .DW (32) + ) u_key_share1_12 ( + .re (1'b0), + .we (key_share1_12_gated_we), + .wd (key_share1_12_wd), + .d ('0), + .qre (), + .qe (key_share1_12_flds_we[0]), + .q (reg2hw.key_share1[12].q), + .ds (), + .qs () + ); + assign reg2hw.key_share1[12].qe = key_share1_12_qe; + + + // Subregister 13 of Multireg key_share1 + // R[key_share1_13]: V(True) + logic key_share1_13_qe; + logic [0:0] key_share1_13_flds_we; + assign key_share1_13_qe = &key_share1_13_flds_we; + // Create REGWEN-gated WE signal + logic key_share1_13_gated_we; + assign key_share1_13_gated_we = key_share1_13_we & cfg_regwen_qs; + caliptra_prim_subreg_ext #( + .DW (32) + ) u_key_share1_13 ( + .re (1'b0), + .we (key_share1_13_gated_we), + .wd (key_share1_13_wd), + .d ('0), + .qre (), + .qe (key_share1_13_flds_we[0]), + .q (reg2hw.key_share1[13].q), + .ds (), + .qs () + ); + assign reg2hw.key_share1[13].qe = key_share1_13_qe; + + + // Subregister 14 of Multireg key_share1 + // R[key_share1_14]: V(True) + logic key_share1_14_qe; + logic [0:0] key_share1_14_flds_we; + assign key_share1_14_qe = &key_share1_14_flds_we; + // Create REGWEN-gated WE signal + logic key_share1_14_gated_we; + assign key_share1_14_gated_we = key_share1_14_we & cfg_regwen_qs; + caliptra_prim_subreg_ext #( + .DW (32) + ) u_key_share1_14 ( + .re (1'b0), + .we (key_share1_14_gated_we), + .wd (key_share1_14_wd), + .d ('0), + .qre (), + .qe (key_share1_14_flds_we[0]), + .q (reg2hw.key_share1[14].q), + .ds (), + .qs () + ); + assign reg2hw.key_share1[14].qe = key_share1_14_qe; + + + // Subregister 15 of Multireg key_share1 + // R[key_share1_15]: V(True) + logic key_share1_15_qe; + logic [0:0] key_share1_15_flds_we; + assign key_share1_15_qe = &key_share1_15_flds_we; + // Create REGWEN-gated WE signal + logic key_share1_15_gated_we; + assign key_share1_15_gated_we = key_share1_15_we & cfg_regwen_qs; + caliptra_prim_subreg_ext #( + .DW (32) + ) u_key_share1_15 ( + .re (1'b0), + .we (key_share1_15_gated_we), + .wd (key_share1_15_wd), + .d ('0), + .qre (), + .qe (key_share1_15_flds_we[0]), + .q (reg2hw.key_share1[15].q), + .ds (), + .qs () + ); + assign reg2hw.key_share1[15].qe = key_share1_15_qe; + + + // R[key_len]: V(False) + // Create REGWEN-gated WE signal + logic key_len_gated_we; + assign key_len_gated_we = key_len_we & cfg_regwen_qs; + caliptra_prim_subreg #( + .DW (3), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessWO), + .RESVAL (3'h0), + .Mubi (1'b0) + ) u_key_len ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (key_len_gated_we), + .wd (key_len_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.key_len.q), + .ds (), + + // to register interface (read) + .qs () + ); + + + // Subregister 0 of Multireg prefix + // R[prefix_0]: V(False) + // Create REGWEN-gated WE signal + logic prefix_0_gated_we; + assign prefix_0_gated_we = prefix_0_we & cfg_regwen_qs; + caliptra_prim_subreg #( + .DW (32), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_prefix_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prefix_0_gated_we), + .wd (prefix_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prefix[0].q), + .ds (), + + // to register interface (read) + .qs (prefix_0_qs) + ); + + + // Subregister 1 of Multireg prefix + // R[prefix_1]: V(False) + // Create REGWEN-gated WE signal + logic prefix_1_gated_we; + assign prefix_1_gated_we = prefix_1_we & cfg_regwen_qs; + caliptra_prim_subreg #( + .DW (32), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_prefix_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prefix_1_gated_we), + .wd (prefix_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prefix[1].q), + .ds (), + + // to register interface (read) + .qs (prefix_1_qs) + ); + + + // Subregister 2 of Multireg prefix + // R[prefix_2]: V(False) + // Create REGWEN-gated WE signal + logic prefix_2_gated_we; + assign prefix_2_gated_we = prefix_2_we & cfg_regwen_qs; + caliptra_prim_subreg #( + .DW (32), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_prefix_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prefix_2_gated_we), + .wd (prefix_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prefix[2].q), + .ds (), + + // to register interface (read) + .qs (prefix_2_qs) + ); + + + // Subregister 3 of Multireg prefix + // R[prefix_3]: V(False) + // Create REGWEN-gated WE signal + logic prefix_3_gated_we; + assign prefix_3_gated_we = prefix_3_we & cfg_regwen_qs; + caliptra_prim_subreg #( + .DW (32), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_prefix_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prefix_3_gated_we), + .wd (prefix_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prefix[3].q), + .ds (), + + // to register interface (read) + .qs (prefix_3_qs) + ); + + + // Subregister 4 of Multireg prefix + // R[prefix_4]: V(False) + // Create REGWEN-gated WE signal + logic prefix_4_gated_we; + assign prefix_4_gated_we = prefix_4_we & cfg_regwen_qs; + caliptra_prim_subreg #( + .DW (32), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_prefix_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prefix_4_gated_we), + .wd (prefix_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prefix[4].q), + .ds (), + + // to register interface (read) + .qs (prefix_4_qs) + ); + + + // Subregister 5 of Multireg prefix + // R[prefix_5]: V(False) + // Create REGWEN-gated WE signal + logic prefix_5_gated_we; + assign prefix_5_gated_we = prefix_5_we & cfg_regwen_qs; + caliptra_prim_subreg #( + .DW (32), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_prefix_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prefix_5_gated_we), + .wd (prefix_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prefix[5].q), + .ds (), + + // to register interface (read) + .qs (prefix_5_qs) + ); + + + // Subregister 6 of Multireg prefix + // R[prefix_6]: V(False) + // Create REGWEN-gated WE signal + logic prefix_6_gated_we; + assign prefix_6_gated_we = prefix_6_we & cfg_regwen_qs; + caliptra_prim_subreg #( + .DW (32), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_prefix_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prefix_6_gated_we), + .wd (prefix_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prefix[6].q), + .ds (), + + // to register interface (read) + .qs (prefix_6_qs) + ); + + + // Subregister 7 of Multireg prefix + // R[prefix_7]: V(False) + // Create REGWEN-gated WE signal + logic prefix_7_gated_we; + assign prefix_7_gated_we = prefix_7_we & cfg_regwen_qs; + caliptra_prim_subreg #( + .DW (32), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_prefix_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prefix_7_gated_we), + .wd (prefix_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prefix[7].q), + .ds (), + + // to register interface (read) + .qs (prefix_7_qs) + ); + + + // Subregister 8 of Multireg prefix + // R[prefix_8]: V(False) + // Create REGWEN-gated WE signal + logic prefix_8_gated_we; + assign prefix_8_gated_we = prefix_8_we & cfg_regwen_qs; + caliptra_prim_subreg #( + .DW (32), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_prefix_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prefix_8_gated_we), + .wd (prefix_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prefix[8].q), + .ds (), + + // to register interface (read) + .qs (prefix_8_qs) + ); + + + // Subregister 9 of Multireg prefix + // R[prefix_9]: V(False) + // Create REGWEN-gated WE signal + logic prefix_9_gated_we; + assign prefix_9_gated_we = prefix_9_we & cfg_regwen_qs; + caliptra_prim_subreg #( + .DW (32), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_prefix_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prefix_9_gated_we), + .wd (prefix_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prefix[9].q), + .ds (), + + // to register interface (read) + .qs (prefix_9_qs) + ); + + + // Subregister 10 of Multireg prefix + // R[prefix_10]: V(False) + // Create REGWEN-gated WE signal + logic prefix_10_gated_we; + assign prefix_10_gated_we = prefix_10_we & cfg_regwen_qs; + caliptra_prim_subreg #( + .DW (32), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_prefix_10 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prefix_10_gated_we), + .wd (prefix_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prefix[10].q), + .ds (), + + // to register interface (read) + .qs (prefix_10_qs) + ); + + + // R[err_code]: V(False) + caliptra_prim_subreg #( + .DW (32), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_err_code ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.err_code.de), + .d (hw2reg.err_code.d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (err_code_qs) + ); + + + + logic [56:0] addr_hit; + always_comb begin + addr_hit = '0; + addr_hit[ 0] = (reg_addr == KMAC_INTR_STATE_OFFSET); + addr_hit[ 1] = (reg_addr == KMAC_INTR_ENABLE_OFFSET); + addr_hit[ 2] = (reg_addr == KMAC_INTR_TEST_OFFSET); + addr_hit[ 3] = (reg_addr == KMAC_ALERT_TEST_OFFSET); + addr_hit[ 4] = (reg_addr == KMAC_CFG_REGWEN_OFFSET); + addr_hit[ 5] = (reg_addr == KMAC_CFG_SHADOWED_OFFSET); + addr_hit[ 6] = (reg_addr == KMAC_CMD_OFFSET); + addr_hit[ 7] = (reg_addr == KMAC_STATUS_OFFSET); + addr_hit[ 8] = (reg_addr == KMAC_ENTROPY_PERIOD_OFFSET); + addr_hit[ 9] = (reg_addr == KMAC_ENTROPY_REFRESH_HASH_CNT_OFFSET); + addr_hit[10] = (reg_addr == KMAC_ENTROPY_REFRESH_THRESHOLD_SHADOWED_OFFSET); + addr_hit[11] = (reg_addr == KMAC_ENTROPY_SEED_OFFSET); + addr_hit[12] = (reg_addr == KMAC_KEY_SHARE0_0_OFFSET); + addr_hit[13] = (reg_addr == KMAC_KEY_SHARE0_1_OFFSET); + addr_hit[14] = (reg_addr == KMAC_KEY_SHARE0_2_OFFSET); + addr_hit[15] = (reg_addr == KMAC_KEY_SHARE0_3_OFFSET); + addr_hit[16] = (reg_addr == KMAC_KEY_SHARE0_4_OFFSET); + addr_hit[17] = (reg_addr == KMAC_KEY_SHARE0_5_OFFSET); + addr_hit[18] = (reg_addr == KMAC_KEY_SHARE0_6_OFFSET); + addr_hit[19] = (reg_addr == KMAC_KEY_SHARE0_7_OFFSET); + addr_hit[20] = (reg_addr == KMAC_KEY_SHARE0_8_OFFSET); + addr_hit[21] = (reg_addr == KMAC_KEY_SHARE0_9_OFFSET); + addr_hit[22] = (reg_addr == KMAC_KEY_SHARE0_10_OFFSET); + addr_hit[23] = (reg_addr == KMAC_KEY_SHARE0_11_OFFSET); + addr_hit[24] = (reg_addr == KMAC_KEY_SHARE0_12_OFFSET); + addr_hit[25] = (reg_addr == KMAC_KEY_SHARE0_13_OFFSET); + addr_hit[26] = (reg_addr == KMAC_KEY_SHARE0_14_OFFSET); + addr_hit[27] = (reg_addr == KMAC_KEY_SHARE0_15_OFFSET); + addr_hit[28] = (reg_addr == KMAC_KEY_SHARE1_0_OFFSET); + addr_hit[29] = (reg_addr == KMAC_KEY_SHARE1_1_OFFSET); + addr_hit[30] = (reg_addr == KMAC_KEY_SHARE1_2_OFFSET); + addr_hit[31] = (reg_addr == KMAC_KEY_SHARE1_3_OFFSET); + addr_hit[32] = (reg_addr == KMAC_KEY_SHARE1_4_OFFSET); + addr_hit[33] = (reg_addr == KMAC_KEY_SHARE1_5_OFFSET); + addr_hit[34] = (reg_addr == KMAC_KEY_SHARE1_6_OFFSET); + addr_hit[35] = (reg_addr == KMAC_KEY_SHARE1_7_OFFSET); + addr_hit[36] = (reg_addr == KMAC_KEY_SHARE1_8_OFFSET); + addr_hit[37] = (reg_addr == KMAC_KEY_SHARE1_9_OFFSET); + addr_hit[38] = (reg_addr == KMAC_KEY_SHARE1_10_OFFSET); + addr_hit[39] = (reg_addr == KMAC_KEY_SHARE1_11_OFFSET); + addr_hit[40] = (reg_addr == KMAC_KEY_SHARE1_12_OFFSET); + addr_hit[41] = (reg_addr == KMAC_KEY_SHARE1_13_OFFSET); + addr_hit[42] = (reg_addr == KMAC_KEY_SHARE1_14_OFFSET); + addr_hit[43] = (reg_addr == KMAC_KEY_SHARE1_15_OFFSET); + addr_hit[44] = (reg_addr == KMAC_KEY_LEN_OFFSET); + addr_hit[45] = (reg_addr == KMAC_PREFIX_0_OFFSET); + addr_hit[46] = (reg_addr == KMAC_PREFIX_1_OFFSET); + addr_hit[47] = (reg_addr == KMAC_PREFIX_2_OFFSET); + addr_hit[48] = (reg_addr == KMAC_PREFIX_3_OFFSET); + addr_hit[49] = (reg_addr == KMAC_PREFIX_4_OFFSET); + addr_hit[50] = (reg_addr == KMAC_PREFIX_5_OFFSET); + addr_hit[51] = (reg_addr == KMAC_PREFIX_6_OFFSET); + addr_hit[52] = (reg_addr == KMAC_PREFIX_7_OFFSET); + addr_hit[53] = (reg_addr == KMAC_PREFIX_8_OFFSET); + addr_hit[54] = (reg_addr == KMAC_PREFIX_9_OFFSET); + addr_hit[55] = (reg_addr == KMAC_PREFIX_10_OFFSET); + addr_hit[56] = (reg_addr == KMAC_ERR_CODE_OFFSET); + end + + assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; + + // Check sub-word write is permitted + always_comb begin + wr_err = (reg_we & + ((addr_hit[ 0] & (|(KMAC_PERMIT[ 0] & ~reg_be))) | + (addr_hit[ 1] & (|(KMAC_PERMIT[ 1] & ~reg_be))) | + (addr_hit[ 2] & (|(KMAC_PERMIT[ 2] & ~reg_be))) | + (addr_hit[ 3] & (|(KMAC_PERMIT[ 3] & ~reg_be))) | + (addr_hit[ 4] & (|(KMAC_PERMIT[ 4] & ~reg_be))) | + (addr_hit[ 5] & (|(KMAC_PERMIT[ 5] & ~reg_be))) | + (addr_hit[ 6] & (|(KMAC_PERMIT[ 6] & ~reg_be))) | + (addr_hit[ 7] & (|(KMAC_PERMIT[ 7] & ~reg_be))) | + (addr_hit[ 8] & (|(KMAC_PERMIT[ 8] & ~reg_be))) | + (addr_hit[ 9] & (|(KMAC_PERMIT[ 9] & ~reg_be))) | + (addr_hit[10] & (|(KMAC_PERMIT[10] & ~reg_be))) | + (addr_hit[11] & (|(KMAC_PERMIT[11] & ~reg_be))) | + (addr_hit[12] & (|(KMAC_PERMIT[12] & ~reg_be))) | + (addr_hit[13] & (|(KMAC_PERMIT[13] & ~reg_be))) | + (addr_hit[14] & (|(KMAC_PERMIT[14] & ~reg_be))) | + (addr_hit[15] & (|(KMAC_PERMIT[15] & ~reg_be))) | + (addr_hit[16] & (|(KMAC_PERMIT[16] & ~reg_be))) | + (addr_hit[17] & (|(KMAC_PERMIT[17] & ~reg_be))) | + (addr_hit[18] & (|(KMAC_PERMIT[18] & ~reg_be))) | + (addr_hit[19] & (|(KMAC_PERMIT[19] & ~reg_be))) | + (addr_hit[20] & (|(KMAC_PERMIT[20] & ~reg_be))) | + (addr_hit[21] & (|(KMAC_PERMIT[21] & ~reg_be))) | + (addr_hit[22] & (|(KMAC_PERMIT[22] & ~reg_be))) | + (addr_hit[23] & (|(KMAC_PERMIT[23] & ~reg_be))) | + (addr_hit[24] & (|(KMAC_PERMIT[24] & ~reg_be))) | + (addr_hit[25] & (|(KMAC_PERMIT[25] & ~reg_be))) | + (addr_hit[26] & (|(KMAC_PERMIT[26] & ~reg_be))) | + (addr_hit[27] & (|(KMAC_PERMIT[27] & ~reg_be))) | + (addr_hit[28] & (|(KMAC_PERMIT[28] & ~reg_be))) | + (addr_hit[29] & (|(KMAC_PERMIT[29] & ~reg_be))) | + (addr_hit[30] & (|(KMAC_PERMIT[30] & ~reg_be))) | + (addr_hit[31] & (|(KMAC_PERMIT[31] & ~reg_be))) | + (addr_hit[32] & (|(KMAC_PERMIT[32] & ~reg_be))) | + (addr_hit[33] & (|(KMAC_PERMIT[33] & ~reg_be))) | + (addr_hit[34] & (|(KMAC_PERMIT[34] & ~reg_be))) | + (addr_hit[35] & (|(KMAC_PERMIT[35] & ~reg_be))) | + (addr_hit[36] & (|(KMAC_PERMIT[36] & ~reg_be))) | + (addr_hit[37] & (|(KMAC_PERMIT[37] & ~reg_be))) | + (addr_hit[38] & (|(KMAC_PERMIT[38] & ~reg_be))) | + (addr_hit[39] & (|(KMAC_PERMIT[39] & ~reg_be))) | + (addr_hit[40] & (|(KMAC_PERMIT[40] & ~reg_be))) | + (addr_hit[41] & (|(KMAC_PERMIT[41] & ~reg_be))) | + (addr_hit[42] & (|(KMAC_PERMIT[42] & ~reg_be))) | + (addr_hit[43] & (|(KMAC_PERMIT[43] & ~reg_be))) | + (addr_hit[44] & (|(KMAC_PERMIT[44] & ~reg_be))) | + (addr_hit[45] & (|(KMAC_PERMIT[45] & ~reg_be))) | + (addr_hit[46] & (|(KMAC_PERMIT[46] & ~reg_be))) | + (addr_hit[47] & (|(KMAC_PERMIT[47] & ~reg_be))) | + (addr_hit[48] & (|(KMAC_PERMIT[48] & ~reg_be))) | + (addr_hit[49] & (|(KMAC_PERMIT[49] & ~reg_be))) | + (addr_hit[50] & (|(KMAC_PERMIT[50] & ~reg_be))) | + (addr_hit[51] & (|(KMAC_PERMIT[51] & ~reg_be))) | + (addr_hit[52] & (|(KMAC_PERMIT[52] & ~reg_be))) | + (addr_hit[53] & (|(KMAC_PERMIT[53] & ~reg_be))) | + (addr_hit[54] & (|(KMAC_PERMIT[54] & ~reg_be))) | + (addr_hit[55] & (|(KMAC_PERMIT[55] & ~reg_be))) | + (addr_hit[56] & (|(KMAC_PERMIT[56] & ~reg_be))))); + end + + // Generate write-enables + assign intr_state_we = addr_hit[0] & reg_we & !reg_error; + + assign intr_state_kmac_done_wd = reg_wdata[0]; + + assign intr_state_kmac_err_wd = reg_wdata[2]; + assign intr_enable_we = addr_hit[1] & reg_we & !reg_error; + + assign intr_enable_kmac_done_wd = reg_wdata[0]; + + assign intr_enable_fifo_empty_wd = reg_wdata[1]; + + assign intr_enable_kmac_err_wd = reg_wdata[2]; + assign intr_test_we = addr_hit[2] & reg_we & !reg_error; + + assign intr_test_kmac_done_wd = reg_wdata[0]; + + assign intr_test_fifo_empty_wd = reg_wdata[1]; + + assign intr_test_kmac_err_wd = reg_wdata[2]; + assign alert_test_we = addr_hit[3] & reg_we & !reg_error; + + assign alert_test_recov_operation_err_wd = reg_wdata[0]; + + assign alert_test_fatal_fault_err_wd = reg_wdata[1]; + assign cfg_regwen_re = addr_hit[4] & reg_re & !reg_error; + assign cfg_shadowed_re = addr_hit[5] & reg_re & !reg_error; + assign cfg_shadowed_we = addr_hit[5] & reg_we & !reg_error; + + assign cfg_shadowed_kmac_en_wd = reg_wdata[0]; + + assign cfg_shadowed_kstrength_wd = reg_wdata[3:1]; + + assign cfg_shadowed_mode_wd = reg_wdata[5:4]; + + assign cfg_shadowed_msg_endianness_wd = reg_wdata[8]; + + assign cfg_shadowed_state_endianness_wd = reg_wdata[9]; + + assign cfg_shadowed_sideload_wd = reg_wdata[12]; + + assign cfg_shadowed_entropy_mode_wd = reg_wdata[17:16]; + + assign cfg_shadowed_entropy_fast_process_wd = reg_wdata[19]; + + assign cfg_shadowed_msg_mask_wd = reg_wdata[20]; + + assign cfg_shadowed_entropy_ready_wd = reg_wdata[24]; + + assign cfg_shadowed_en_unsupported_modestrength_wd = reg_wdata[26]; + assign cmd_we = addr_hit[6] & reg_we & !reg_error; + + assign cmd_cmd_wd = reg_wdata[5:0]; + + assign cmd_entropy_req_wd = reg_wdata[8]; + + assign cmd_hash_cnt_clr_wd = reg_wdata[9]; + + assign cmd_err_processed_wd = reg_wdata[10]; + assign status_re = addr_hit[7] & reg_re & !reg_error; + assign entropy_period_we = addr_hit[8] & reg_we & !reg_error; + + assign entropy_period_prescaler_wd = reg_wdata[9:0]; + + assign entropy_period_wait_timer_wd = reg_wdata[31:16]; + assign entropy_refresh_threshold_shadowed_re = addr_hit[10] & reg_re & !reg_error; + assign entropy_refresh_threshold_shadowed_we = addr_hit[10] & reg_we & !reg_error; + + assign entropy_refresh_threshold_shadowed_wd = reg_wdata[9:0]; + assign entropy_seed_we = addr_hit[11] & reg_we & !reg_error; + + assign entropy_seed_wd = reg_wdata[31:0]; + assign key_share0_0_we = addr_hit[12] & reg_we & !reg_error; + + assign key_share0_0_wd = reg_wdata[31:0]; + assign key_share0_1_we = addr_hit[13] & reg_we & !reg_error; + + assign key_share0_1_wd = reg_wdata[31:0]; + assign key_share0_2_we = addr_hit[14] & reg_we & !reg_error; + + assign key_share0_2_wd = reg_wdata[31:0]; + assign key_share0_3_we = addr_hit[15] & reg_we & !reg_error; + + assign key_share0_3_wd = reg_wdata[31:0]; + assign key_share0_4_we = addr_hit[16] & reg_we & !reg_error; + + assign key_share0_4_wd = reg_wdata[31:0]; + assign key_share0_5_we = addr_hit[17] & reg_we & !reg_error; + + assign key_share0_5_wd = reg_wdata[31:0]; + assign key_share0_6_we = addr_hit[18] & reg_we & !reg_error; + + assign key_share0_6_wd = reg_wdata[31:0]; + assign key_share0_7_we = addr_hit[19] & reg_we & !reg_error; + + assign key_share0_7_wd = reg_wdata[31:0]; + assign key_share0_8_we = addr_hit[20] & reg_we & !reg_error; + + assign key_share0_8_wd = reg_wdata[31:0]; + assign key_share0_9_we = addr_hit[21] & reg_we & !reg_error; + + assign key_share0_9_wd = reg_wdata[31:0]; + assign key_share0_10_we = addr_hit[22] & reg_we & !reg_error; + + assign key_share0_10_wd = reg_wdata[31:0]; + assign key_share0_11_we = addr_hit[23] & reg_we & !reg_error; + + assign key_share0_11_wd = reg_wdata[31:0]; + assign key_share0_12_we = addr_hit[24] & reg_we & !reg_error; + + assign key_share0_12_wd = reg_wdata[31:0]; + assign key_share0_13_we = addr_hit[25] & reg_we & !reg_error; + + assign key_share0_13_wd = reg_wdata[31:0]; + assign key_share0_14_we = addr_hit[26] & reg_we & !reg_error; + + assign key_share0_14_wd = reg_wdata[31:0]; + assign key_share0_15_we = addr_hit[27] & reg_we & !reg_error; + + assign key_share0_15_wd = reg_wdata[31:0]; + assign key_share1_0_we = addr_hit[28] & reg_we & !reg_error; + + assign key_share1_0_wd = reg_wdata[31:0]; + assign key_share1_1_we = addr_hit[29] & reg_we & !reg_error; + + assign key_share1_1_wd = reg_wdata[31:0]; + assign key_share1_2_we = addr_hit[30] & reg_we & !reg_error; + + assign key_share1_2_wd = reg_wdata[31:0]; + assign key_share1_3_we = addr_hit[31] & reg_we & !reg_error; + + assign key_share1_3_wd = reg_wdata[31:0]; + assign key_share1_4_we = addr_hit[32] & reg_we & !reg_error; + + assign key_share1_4_wd = reg_wdata[31:0]; + assign key_share1_5_we = addr_hit[33] & reg_we & !reg_error; + + assign key_share1_5_wd = reg_wdata[31:0]; + assign key_share1_6_we = addr_hit[34] & reg_we & !reg_error; + + assign key_share1_6_wd = reg_wdata[31:0]; + assign key_share1_7_we = addr_hit[35] & reg_we & !reg_error; + + assign key_share1_7_wd = reg_wdata[31:0]; + assign key_share1_8_we = addr_hit[36] & reg_we & !reg_error; + + assign key_share1_8_wd = reg_wdata[31:0]; + assign key_share1_9_we = addr_hit[37] & reg_we & !reg_error; + + assign key_share1_9_wd = reg_wdata[31:0]; + assign key_share1_10_we = addr_hit[38] & reg_we & !reg_error; + + assign key_share1_10_wd = reg_wdata[31:0]; + assign key_share1_11_we = addr_hit[39] & reg_we & !reg_error; + + assign key_share1_11_wd = reg_wdata[31:0]; + assign key_share1_12_we = addr_hit[40] & reg_we & !reg_error; + + assign key_share1_12_wd = reg_wdata[31:0]; + assign key_share1_13_we = addr_hit[41] & reg_we & !reg_error; + + assign key_share1_13_wd = reg_wdata[31:0]; + assign key_share1_14_we = addr_hit[42] & reg_we & !reg_error; + + assign key_share1_14_wd = reg_wdata[31:0]; + assign key_share1_15_we = addr_hit[43] & reg_we & !reg_error; + + assign key_share1_15_wd = reg_wdata[31:0]; + assign key_len_we = addr_hit[44] & reg_we & !reg_error; + + assign key_len_wd = reg_wdata[2:0]; + assign prefix_0_we = addr_hit[45] & reg_we & !reg_error; + + assign prefix_0_wd = reg_wdata[31:0]; + assign prefix_1_we = addr_hit[46] & reg_we & !reg_error; + + assign prefix_1_wd = reg_wdata[31:0]; + assign prefix_2_we = addr_hit[47] & reg_we & !reg_error; + + assign prefix_2_wd = reg_wdata[31:0]; + assign prefix_3_we = addr_hit[48] & reg_we & !reg_error; + + assign prefix_3_wd = reg_wdata[31:0]; + assign prefix_4_we = addr_hit[49] & reg_we & !reg_error; + + assign prefix_4_wd = reg_wdata[31:0]; + assign prefix_5_we = addr_hit[50] & reg_we & !reg_error; + + assign prefix_5_wd = reg_wdata[31:0]; + assign prefix_6_we = addr_hit[51] & reg_we & !reg_error; + + assign prefix_6_wd = reg_wdata[31:0]; + assign prefix_7_we = addr_hit[52] & reg_we & !reg_error; + + assign prefix_7_wd = reg_wdata[31:0]; + assign prefix_8_we = addr_hit[53] & reg_we & !reg_error; + + assign prefix_8_wd = reg_wdata[31:0]; + assign prefix_9_we = addr_hit[54] & reg_we & !reg_error; + + assign prefix_9_wd = reg_wdata[31:0]; + assign prefix_10_we = addr_hit[55] & reg_we & !reg_error; + + assign prefix_10_wd = reg_wdata[31:0]; + + // Assign write-enables to checker logic vector. + always_comb begin + reg_we_check = '0; + reg_we_check[0] = intr_state_we; + reg_we_check[1] = intr_enable_we; + reg_we_check[2] = intr_test_we; + reg_we_check[3] = alert_test_we; + reg_we_check[4] = 1'b0; + reg_we_check[5] = cfg_shadowed_gated_we; + reg_we_check[6] = cmd_we; + reg_we_check[7] = 1'b0; + reg_we_check[8] = entropy_period_gated_we; + reg_we_check[9] = 1'b0; + reg_we_check[10] = entropy_refresh_threshold_shadowed_gated_we; + reg_we_check[11] = entropy_seed_we; + reg_we_check[12] = key_share0_0_gated_we; + reg_we_check[13] = key_share0_1_gated_we; + reg_we_check[14] = key_share0_2_gated_we; + reg_we_check[15] = key_share0_3_gated_we; + reg_we_check[16] = key_share0_4_gated_we; + reg_we_check[17] = key_share0_5_gated_we; + reg_we_check[18] = key_share0_6_gated_we; + reg_we_check[19] = key_share0_7_gated_we; + reg_we_check[20] = key_share0_8_gated_we; + reg_we_check[21] = key_share0_9_gated_we; + reg_we_check[22] = key_share0_10_gated_we; + reg_we_check[23] = key_share0_11_gated_we; + reg_we_check[24] = key_share0_12_gated_we; + reg_we_check[25] = key_share0_13_gated_we; + reg_we_check[26] = key_share0_14_gated_we; + reg_we_check[27] = key_share0_15_gated_we; + reg_we_check[28] = key_share1_0_gated_we; + reg_we_check[29] = key_share1_1_gated_we; + reg_we_check[30] = key_share1_2_gated_we; + reg_we_check[31] = key_share1_3_gated_we; + reg_we_check[32] = key_share1_4_gated_we; + reg_we_check[33] = key_share1_5_gated_we; + reg_we_check[34] = key_share1_6_gated_we; + reg_we_check[35] = key_share1_7_gated_we; + reg_we_check[36] = key_share1_8_gated_we; + reg_we_check[37] = key_share1_9_gated_we; + reg_we_check[38] = key_share1_10_gated_we; + reg_we_check[39] = key_share1_11_gated_we; + reg_we_check[40] = key_share1_12_gated_we; + reg_we_check[41] = key_share1_13_gated_we; + reg_we_check[42] = key_share1_14_gated_we; + reg_we_check[43] = key_share1_15_gated_we; + reg_we_check[44] = key_len_gated_we; + reg_we_check[45] = prefix_0_gated_we; + reg_we_check[46] = prefix_1_gated_we; + reg_we_check[47] = prefix_2_gated_we; + reg_we_check[48] = prefix_3_gated_we; + reg_we_check[49] = prefix_4_gated_we; + reg_we_check[50] = prefix_5_gated_we; + reg_we_check[51] = prefix_6_gated_we; + reg_we_check[52] = prefix_7_gated_we; + reg_we_check[53] = prefix_8_gated_we; + reg_we_check[54] = prefix_9_gated_we; + reg_we_check[55] = prefix_10_gated_we; + reg_we_check[56] = 1'b0; + end + + // Read data return + always_comb begin + reg_rdata_next = '0; + unique case (1'b1) + addr_hit[0]: begin + reg_rdata_next[0] = intr_state_kmac_done_qs; + reg_rdata_next[1] = intr_state_fifo_empty_qs; + reg_rdata_next[2] = intr_state_kmac_err_qs; + end + + addr_hit[1]: begin + reg_rdata_next[0] = intr_enable_kmac_done_qs; + reg_rdata_next[1] = intr_enable_fifo_empty_qs; + reg_rdata_next[2] = intr_enable_kmac_err_qs; + end + + addr_hit[2]: begin + reg_rdata_next[0] = '0; + reg_rdata_next[1] = '0; + reg_rdata_next[2] = '0; + end + + addr_hit[3]: begin + reg_rdata_next[0] = '0; + reg_rdata_next[1] = '0; + end + + addr_hit[4]: begin + reg_rdata_next[0] = cfg_regwen_qs; + end + + addr_hit[5]: begin + reg_rdata_next[0] = cfg_shadowed_kmac_en_qs; + reg_rdata_next[3:1] = cfg_shadowed_kstrength_qs; + reg_rdata_next[5:4] = cfg_shadowed_mode_qs; + reg_rdata_next[8] = cfg_shadowed_msg_endianness_qs; + reg_rdata_next[9] = cfg_shadowed_state_endianness_qs; + reg_rdata_next[12] = cfg_shadowed_sideload_qs; + reg_rdata_next[17:16] = cfg_shadowed_entropy_mode_qs; + reg_rdata_next[19] = cfg_shadowed_entropy_fast_process_qs; + reg_rdata_next[20] = cfg_shadowed_msg_mask_qs; + reg_rdata_next[24] = cfg_shadowed_entropy_ready_qs; + reg_rdata_next[26] = cfg_shadowed_en_unsupported_modestrength_qs; + end + + addr_hit[6]: begin + reg_rdata_next[5:0] = '0; + reg_rdata_next[8] = '0; + reg_rdata_next[9] = '0; + reg_rdata_next[10] = '0; + end + + addr_hit[7]: begin + reg_rdata_next[0] = status_sha3_idle_qs; + reg_rdata_next[1] = status_sha3_absorb_qs; + reg_rdata_next[2] = status_sha3_squeeze_qs; + reg_rdata_next[12:8] = status_fifo_depth_qs; + reg_rdata_next[14] = status_fifo_empty_qs; + reg_rdata_next[15] = status_fifo_full_qs; + reg_rdata_next[16] = status_alert_fatal_fault_qs; + reg_rdata_next[17] = status_alert_recov_ctrl_update_err_qs; + end + + addr_hit[8]: begin + reg_rdata_next[9:0] = entropy_period_prescaler_qs; + reg_rdata_next[31:16] = entropy_period_wait_timer_qs; + end + + addr_hit[9]: begin + reg_rdata_next[9:0] = entropy_refresh_hash_cnt_qs; + end + + addr_hit[10]: begin + reg_rdata_next[9:0] = entropy_refresh_threshold_shadowed_qs; + end + + addr_hit[11]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[12]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[13]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[14]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[15]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[16]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[17]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[18]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[19]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[20]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[21]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[22]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[23]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[24]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[25]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[26]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[27]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[28]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[29]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[30]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[31]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[32]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[33]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[34]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[35]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[36]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[37]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[38]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[39]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[40]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[41]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[42]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[43]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[44]: begin + reg_rdata_next[2:0] = '0; + end + + addr_hit[45]: begin + reg_rdata_next[31:0] = prefix_0_qs; + end + + addr_hit[46]: begin + reg_rdata_next[31:0] = prefix_1_qs; + end + + addr_hit[47]: begin + reg_rdata_next[31:0] = prefix_2_qs; + end + + addr_hit[48]: begin + reg_rdata_next[31:0] = prefix_3_qs; + end + + addr_hit[49]: begin + reg_rdata_next[31:0] = prefix_4_qs; + end + + addr_hit[50]: begin + reg_rdata_next[31:0] = prefix_5_qs; + end + + addr_hit[51]: begin + reg_rdata_next[31:0] = prefix_6_qs; + end + + addr_hit[52]: begin + reg_rdata_next[31:0] = prefix_7_qs; + end + + addr_hit[53]: begin + reg_rdata_next[31:0] = prefix_8_qs; + end + + addr_hit[54]: begin + reg_rdata_next[31:0] = prefix_9_qs; + end + + addr_hit[55]: begin + reg_rdata_next[31:0] = prefix_10_qs; + end + + addr_hit[56]: begin + reg_rdata_next[31:0] = err_code_qs; + end + + default: begin + reg_rdata_next = '1; + end + endcase + end + + // shadow busy + logic shadow_busy; + logic rst_done; + logic shadow_rst_done; + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + rst_done <= '0; + end else begin + rst_done <= 1'b1; + end + end + + always_ff @(posedge clk_i or negedge rst_shadowed_ni) begin + if (!rst_shadowed_ni) begin + shadow_rst_done <= '0; + end else begin + shadow_rst_done <= 1'b1; + end + end + + // both shadow and normal resets have been released + assign shadow_busy = ~(rst_done & shadow_rst_done); + + // Collect up storage and update errors + assign shadowed_storage_err_o = |{ + cfg_shadowed_kmac_en_storage_err, + cfg_shadowed_kstrength_storage_err, + cfg_shadowed_mode_storage_err, + cfg_shadowed_msg_endianness_storage_err, + cfg_shadowed_state_endianness_storage_err, + cfg_shadowed_sideload_storage_err, + cfg_shadowed_entropy_mode_storage_err, + cfg_shadowed_entropy_fast_process_storage_err, + cfg_shadowed_msg_mask_storage_err, + cfg_shadowed_entropy_ready_storage_err, + cfg_shadowed_en_unsupported_modestrength_storage_err, + entropy_refresh_threshold_shadowed_storage_err + }; + assign shadowed_update_err_o = |{ + cfg_shadowed_kmac_en_update_err, + cfg_shadowed_kstrength_update_err, + cfg_shadowed_mode_update_err, + cfg_shadowed_msg_endianness_update_err, + cfg_shadowed_state_endianness_update_err, + cfg_shadowed_sideload_update_err, + cfg_shadowed_entropy_mode_update_err, + cfg_shadowed_entropy_fast_process_update_err, + cfg_shadowed_msg_mask_update_err, + cfg_shadowed_entropy_ready_update_err, + cfg_shadowed_en_unsupported_modestrength_update_err, + entropy_refresh_threshold_shadowed_update_err + }; + + // register busy + assign reg_busy = shadow_busy; + + // Unused signal tieoff + + // wdata / byte enable are not always fully used + // add a blanket unused statement to handle lint waivers + logic unused_wdata; + logic unused_be; + assign unused_wdata = ^reg_wdata; + assign unused_be = ^reg_be; + + // Assertions for Register Interface + `CALIPTRA_ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni) + `CALIPTRA_ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni) + + `CALIPTRA_ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o_pre.d_valid, clk_i, !rst_ni) + + `CALIPTRA_ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni) + + // this is formulated as an assumption such that the FPV testbenches do disprove this + // property by mistake + //`CALIPTRA_ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.chk_en == tlul_pkg::CheckDis) + +endmodule diff --git a/src/caliptra_ss_lc_ctrl/rtl/kmac_staterd.sv b/src/caliptra_ss_lc_ctrl/rtl/kmac_staterd.sv new file mode 100644 index 0000000..bb9b436 --- /dev/null +++ b/src/caliptra_ss_lc_ctrl/rtl/kmac_staterd.sv @@ -0,0 +1,125 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Keccak state read + +`include "caliptra_prim_assert.sv" + +module kmac_staterd + import kmac_pkg::*; +#( + // TL-UL Address Width. Should be bigger than + // $clog2(kmac_pkg::StateW) * Share + parameter int AddrW = 9, + + // EnMasking: Enable masking security hardening inside keccak_round + // If it is enabled, the result digest will be two set of 1600bit. + parameter bit EnMasking = 1'b0, + localparam int Share = (EnMasking) ? 2 : 1 // derived parameter +) ( + input clk_i, + input rst_ni, + + input tlul_pkg::tl_h2d_t tl_i, + output tlul_pkg::tl_d2h_t tl_o, + + // State in + input [sha3_pkg::StateW-1:0] state_i [Share], + + // Config + input endian_swap_i +); + + localparam int StateAddrW = $clog2(sha3_pkg::StateW/32); + localparam int SelAddrW = AddrW-2-StateAddrW; + + ///////////// + // Signals // + ///////////// + + // TL-UL Adapter signals + logic tlram_req; + logic tlram_gnt; + logic tlram_we; + logic [AddrW-3:0] tlram_addr; // Word base + logic [31:0] unused_tlram_wdata; + logic [31:0] unused_tlram_wmask; + logic [31:0] tlram_rdata; + logic tlram_rvalid; + logic [1:0] tlram_rerror; + logic [31:0] tlram_rdata_endian; + + // TL Adapter + tlul_adapter_sram #( + .SramAw (AddrW-2), + .SramDw (32), + .Outstanding (1), + .ByteAccess (1), + .ErrOnWrite (1), + .ErrOnRead (0) + ) u_tlul_adapter ( + .clk_i, + .rst_ni, + + .tl_i, + .tl_o, + .en_ifetch_i (caliptra_prim_mubi_pkg::MuBi4False), + .req_o (tlram_req), + .req_type_o (), + .gnt_i (tlram_gnt), + .we_o (tlram_we ), + .addr_o (tlram_addr), + .wdata_o (unused_tlram_wdata), + .wmask_o (unused_tlram_wmask), + .intg_error_o (), + .rdata_i (tlram_rdata), + .rvalid_i (tlram_rvalid), + .rerror_i (tlram_rerror), + .compound_txn_in_progress_o (), + .readback_en_i (caliptra_prim_mubi_pkg::MuBi4False), + .readback_error_o (), + .wr_collision_i (1'b0), + .write_pending_i (1'b0) + ); + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + tlram_rdata <= '0; + end else if (tlram_req & ~tlram_we) begin + tlram_rdata <= conv_endian32(tlram_rdata_endian, endian_swap_i); + end + end + + // Always grant + assign tlram_gnt = tlram_req & ~tlram_we; + + // always no error on reading + assign tlram_rerror = '0; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) tlram_rvalid <= 1'b0; + else tlram_rvalid <= tlram_req & !tlram_we; + end + + logic [31:0] muxed_state [Share]; + + + for (genvar i = 0 ; i < Share ; i++) begin : gen_slicer + caliptra_prim_slicer #( + .InW (sha3_pkg::StateW), + .OutW (32), + .IndexW (StateAddrW) + ) u_state_slice ( + .sel_i (tlram_addr[StateAddrW-1:0]), + .data_i (state_i[i]), + .data_o (muxed_state[i]) + ); + end : gen_slicer + + logic [SelAddrW-1:0] addr_sel; + assign addr_sel = tlram_addr[StateAddrW+:SelAddrW]; + + assign tlram_rdata_endian = int'(addr_sel) < Share ? muxed_state[addr_sel] : 0; + +endmodule diff --git a/src/caliptra_ss_lc_ctrl/rtl/sha3.sv b/src/caliptra_ss_lc_ctrl/rtl/sha3.sv new file mode 100644 index 0000000..1637e65 --- /dev/null +++ b/src/caliptra_ss_lc_ctrl/rtl/sha3.sv @@ -0,0 +1,532 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// SHA3 core is a fully functional SHA3/SHAKE/cSHAKE hashing module. +// +// It instantiates a keccak_round with 1600 bits of the state. + +`include "caliptra_prim_assert.sv" + +module sha3 + import sha3_pkg::*; +#( + // Enable Masked Keccak if 1 + parameter bit EnMasking = 0, + // derived parameter + localparam int Share = (EnMasking) ? 2 : 1 +) ( + input clk_i, + input rst_ni, + + // MSG interface + input msg_valid_i, + input [MsgWidth-1:0] msg_data_i [Share], + input [MsgStrbW-1:0] msg_strb_i, // one strobe for shares + output logic msg_ready_o, + + // Entropy interface + input rand_valid_i, + input rand_early_i, + input [StateW/2-1:0] rand_data_i, + input rand_aux_i, + output logic rand_update_o, + output logic rand_consumed_o, + + // N, S: Used in cSHAKE mode only + input [NSRegisterSize*8-1:0] ns_data_i, // See sha3_pkg for details + + // configurations + input sha3_mode_e mode_i, // see sha3pad for details + input keccak_strength_e strength_i, // see sha3pad for details + + // controls + input start_i, // see sha3pad for details + input process_i, // see sha3pad for details + + // run_i is a pulse signal to trigger the keccak_round manually by SW. + // It is used to run additional keccak_f after sponge absorbing is completed. + // See `keccak_run` signal + input run_i, + input caliptra_prim_mubi_pkg::mubi4_t done_i, // see sha3pad for details + + output caliptra_prim_mubi_pkg::mubi4_t absorbed_o, + output logic squeezing_o, + + // Indicate of one block processed. KMAC main state tracks the progression + // based on this signal. + output logic block_processed_o, + + output sha3_st_e sha3_fsm_o, + + // digest output + // This value is valid only after all absorbing process is completed. + // In invalid state, the output `state` will be zero to prevent information + // leakage. + output logic state_valid_o, + output logic [StateW-1:0] state_o [Share], + + // REQ/ACK interface for the Keccak core. This can be used to delay the + // processing e.g. to avoid power spikes at the chip level due to too many + // blocks being active simultaneously. + output logic run_req_o, + input run_ack_i, + + // Life cycle + input caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_t caliptra_ss_lc_escalate_en_i, + + // error_o value is pushed to Error FIFO at KMAC/SHA3 top and reported to SW + output err_t error_o, + + // sparse_fsm_alert + output logic sparse_fsm_error_o, + + // counter error + output logic count_error_o, + + // error on rst_storage in Keccak + output logic keccak_storage_rst_error_o + +); + ///////////////// + // Definitions // + ///////////////// + + typedef enum logic[2:0] { + MuxGuard = 3'b 010, + MuxRelease = 3'b 101 + } state_mux_sel_e; + + ///////////// + // Signals // + ///////////// + + // State --> Digest + // State is exposed to the outside if the hashing process is completed. + logic state_valid; + logic [StateW-1:0] state [Share]; + logic [StateW-1:0] state_guarded [Share]; + + // State --> digest mux select signal + state_mux_sel_e mux_sel; + + // absorbed is a pulse signal that indicates sponge absorbing is done. + // After this, sha3 core allows software to manually run until squeezing + // is completed, which is the `done_i` pulse signal. + caliptra_prim_mubi_pkg::mubi4_t absorbed; + + // `squeezing` is a status indicator that SHA3 core is in sponge squeezing + // stage. In this stage, the state output is valid, and software can manually + // trigger keccak_round logic to get more digest outputs in case the output + // length is bigger than the block limit. + logic squeezing; + + // If process_i is received, the logic initiates the final absorbing process. + // While absorbing, the processing inticator is turned on. This signal is used + // to check if multiple process_i is received or not. + logic processing; + + // FSM variable + sha3_st_sparse_e st, st_d; + + // Keccak control signal (filtered by State Machine) + logic keccak_start, keccak_process; + caliptra_prim_mubi_pkg::mubi4_t keccak_done; + + // alert signals + logic round_count_error, msg_count_error; + assign count_error_o = round_count_error | msg_count_error; + + logic sha3_state_error; + logic keccak_round_state_error; + logic sha3pad_state_error; + + assign sparse_fsm_error_o = sha3_state_error | keccak_round_state_error | sha3pad_state_error; + + // Keccak rst_storage is asserted unexpectedly + logic keccak_storage_rst_error; + assign keccak_storage_rst_error_o = keccak_storage_rst_error; + + ///////////////// + // Connections // + ///////////////// + + logic keccak_valid; + logic [KeccakMsgAddrW-1:0] keccak_addr; + logic [MsgWidth-1:0] keccak_data [Share]; + logic keccak_ready; + + // Keccak round run signal can be controlled by sha3pad and also by software + // after all message feeding is done. it is mainly used for sponge squeezing + // operation after absorbing is completed when output length is longer than + // the block size. + logic keccak_run, sha3pad_keccak_run, sw_keccak_run; + logic keccak_run_req_d, keccak_run_req_q; + logic keccak_triggered_d, keccak_triggered_q; + logic keccak_complete; + + // Announce that we want to run the Keccak core and tell other blocks to go + // quiet. Keep holding the REQ until the Keccak core is done with the + // processing. The keccak_complete signal is received once the Keccak core + // is back in the Idle state and again susceptible to keccak_run. + assign run_req_o = keccak_run_req_d; + assign keccak_run_req_d = + sha3pad_keccak_run || sw_keccak_run ? 1'b 1 : + keccak_complete ? 1'b 0 : keccak_run_req_q; + + // Trigger the Keccak engine with a single pulse upon receiving the ACK. + assign keccak_run = run_req_o & run_ack_i & ~keccak_triggered_q; + assign keccak_triggered_d = + keccak_run ? 1'b 1 : + keccak_complete ? 1'b 0 : keccak_triggered_q; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + keccak_run_req_q <= 1'b 0; + keccak_triggered_q <= 1'b 0; + end else begin + keccak_run_req_q <= keccak_run_req_d; + keccak_triggered_q <= keccak_triggered_d; + end + end + + // Absorb pulse output : used to generate interrupts + // Latch absorbed signal as kmac_keymgr asserts `CmdDone` when it sees + // `absorbed` signal. When this signal goes out, the state is still in + // `StAbsorb`. Next state is `StSqueeze`. + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) absorbed_o <= caliptra_prim_mubi_pkg::MuBi4False; + else absorbed_o <= absorbed; + end + + // Squeezing output + assign squeezing_o = squeezing; + + // processing + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) processing <= 1'b 0; + else if (process_i) processing <= 1'b 1; + else if (caliptra_prim_mubi_pkg::mubi4_test_true_strict(absorbed)) begin + processing <= 1'b 0; + end + end + + assign block_processed_o = keccak_complete; + + // State connection + assign state_valid_o = state_valid; + assign state_o = state_guarded; + + assign sha3_fsm_o = sparse2logic(st); + + /////////////////// + // State Machine // + /////////////////// + + // State Register + `CALIPTRA_PRIM_FLOP_SPARSE_FSM(u_state_regs, st_d, st, sha3_st_sparse_e, StIdle_sparse) + + + // Next State and Output Logic + // Mainly the FSM controls the input signal access + // StIdle: only start_i signal is allowed + // StAbsorb: only process_i signal is allowed + // StSqueeze: only run_i, done_i signal is allowed + + always_comb begin + st_d = st; + + // default output values + keccak_start = 1'b 0; + keccak_process = 1'b 0; + sw_keccak_run = 1'b 0; + keccak_done = caliptra_prim_mubi_pkg::MuBi4False; + + squeezing = 1'b 0; + + state_valid = 1'b 0; + mux_sel = MuxGuard ; + + sha3_state_error = 1'b 0; + + unique case (st) + StIdle_sparse: begin + if (start_i) begin + st_d = StAbsorb_sparse; + + keccak_start = 1'b 1; + end else begin + st_d = StIdle_sparse; + end + end + + StAbsorb_sparse: begin + if (process_i && !processing) begin + st_d = StAbsorb_sparse; + + keccak_process = 1'b 1; + end else if (caliptra_prim_mubi_pkg::mubi4_test_true_strict(absorbed)) begin + st_d = StSqueeze_sparse; + end else begin + st_d = StAbsorb_sparse; + end + end + + StSqueeze_sparse: begin + state_valid = 1'b 1; + mux_sel = MuxRelease; // Expose state to register interface + + squeezing = 1'b 1; + + if (run_i) begin + st_d = StManualRun_sparse; + + sw_keccak_run = 1'b 1; + end else if (caliptra_prim_mubi_pkg::mubi4_test_true_strict(done_i)) begin + st_d = StFlush_sparse; + + keccak_done = done_i; + end else begin + st_d = StSqueeze_sparse; + end + end + + StManualRun_sparse: begin + if (keccak_complete) begin + st_d = StSqueeze_sparse; + end else begin + st_d = StManualRun_sparse; + end + end + + StFlush_sparse: begin + st_d = StIdle_sparse; + end + + StTerminalError_sparse: begin + //this state is terminal + st_d = StTerminalError_sparse; + sha3_state_error = 1'b 1; + end + + default: begin + st_d = StTerminalError_sparse; + sha3_state_error = 1'b 1; + end + endcase + + // SEC_CM: FSM.GLOBAL_ESC, FSM.LOCAL_ESC + // Unconditionally jump into the terminal error state + // if the life cycle controller triggers an escalation. + if (caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_test_true_loose(caliptra_ss_lc_escalate_en_i)) begin + st_d = StTerminalError_sparse; + end + end + + ////////////// + // Datapath // + ////////////// + + // State --> Digest output + always_comb begin : state_guarded_mux + unique case (mux_sel) + MuxGuard: state_guarded = '{default: '0}; + MuxRelease: state_guarded = state; + default: state_guarded = '{default: '0}; // a valid, safe output + endcase + end + + + // Error Detecting + // ErrSha3SwControl: + // info[ 0]: start_i set + // info[ 1]: process_i set + // info[ 2]: run_i set + // info[ 3]: done_i set + // - Sw set process_i, run_i, done_i without start_i + + always_comb begin + error_o = '{valid: 1'b0, code: ErrNone, info: '0}; + + unique case (st) + StIdle_sparse: begin + if (process_i || run_i || + caliptra_prim_mubi_pkg::mubi4_test_true_loose(done_i)) begin + error_o = '{ + valid: 1'b 1, + code: ErrSha3SwControl, + info: 24'({done_i, run_i, process_i, start_i}) + }; + end + end + + StAbsorb_sparse: begin + if (start_i || run_i || caliptra_prim_mubi_pkg::mubi4_test_true_loose(done_i) + || (process_i && processing)) begin + error_o = '{ + valid: 1'b 1, + code: ErrSha3SwControl, + info: 24'({done_i, run_i, process_i, start_i}) + }; + end + end + + StSqueeze_sparse: begin + if (start_i || process_i) begin + error_o = '{ + valid: 1'b 1, + code: ErrSha3SwControl, + info: 24'({done_i, run_i, process_i, start_i}) + }; + end + end + + StManualRun_sparse: begin + if (start_i || process_i || run_i || + caliptra_prim_mubi_pkg::mubi4_test_true_loose(done_i)) begin + error_o = '{ + valid: 1'b 1, + code: ErrSha3SwControl, + info: 24'({done_i, run_i, process_i, start_i}) + }; + end + end + + StFlush_sparse: begin + if (start_i || process_i || run_i || + caliptra_prim_mubi_pkg::mubi4_test_true_loose(done_i)) begin + error_o = '{ + valid: 1'b 1, + code: ErrSha3SwControl, + info: 24'({done_i, run_i, process_i, start_i}) + }; + end + end + + default: begin + end + endcase + end + /////////////// + // Instances // + /////////////// + + // SHA3 pad logic + sha3pad #( + .EnMasking (EnMasking) + ) u_pad ( + .clk_i, + .rst_ni, + + // MSG_FIFO (or from KMAC core) + .msg_valid_i, + .msg_data_i, // [Share] + .msg_strb_i, + .msg_ready_o, + + // Encoded N, S + .ns_data_i, + + // output to keccak_round: message path + .keccak_valid_o (keccak_valid), + .keccak_addr_o (keccak_addr ), + .keccak_data_o (keccak_data ), // [Share] + .keccak_ready_i (keccak_ready), + + .keccak_run_o (sha3pad_keccak_run), + .keccak_complete_i (keccak_complete ), + + // configurations + .mode_i, + .strength_i, + + // LC + .caliptra_ss_lc_escalate_en_i (caliptra_ss_lc_escalate_en_i), + + // controls + .start_i (keccak_start), + .process_i (keccak_process), + .done_i (keccak_done), + + // output + .absorbed_o (absorbed), + .sparse_fsm_error_o (sha3pad_state_error), + .msg_count_error_o (msg_count_error) + ); + + // Keccak round logic + keccak_round #( + .Width (sha3_pkg::StateW), + .DInWidth (sha3_pkg::MsgWidth), + + .EnMasking (EnMasking) + ) u_keccak ( + .clk_i, + .rst_ni, + + .valid_i (keccak_valid), + .addr_i (keccak_addr ), + .data_i (keccak_data ), + .ready_o (keccak_ready), + + .rand_valid_i, + .rand_early_i, + .rand_data_i, + .rand_aux_i, + .rand_update_o, + .rand_consumed_o, + + .run_i (keccak_run ), + .complete_o (keccak_complete), + + .state_o (state), + + // LC + .caliptra_ss_lc_escalate_en_i (caliptra_ss_lc_escalate_en_i), + + .sparse_fsm_error_o (keccak_round_state_error), + .round_count_error_o (round_count_error), + .rst_storage_error_o (keccak_storage_rst_error), + + .clear_i (keccak_done) + ); + + //////////////// + // Assertions // + //////////////// + + // The Keccak core can only be active when the run REQ is ACKed. + `CALIPTRA_ASSERT(KeccakIdleWhenNoRunHs_A, + u_keccak.keccak_st inside {KeccakStActive, + KeccakStPhase1, + KeccakStPhase2Cycle1, + KeccakStPhase2Cycle2, + KeccakStPhase2Cycle3} |-> + run_req_o && run_ack_i) + + // Unknown check for case statement + `CALIPTRA_ASSERT(MuxSelKnown_A, mux_sel inside {MuxGuard, MuxRelease}) + `CALIPTRA_ASSERT(FsmKnown_A, st inside {StIdle_sparse, StAbsorb_sparse, StSqueeze_sparse, + StManualRun_sparse, StFlush_sparse, StTerminalError_sparse}) + + // `state` shall be 0 in invalid + if (EnMasking) begin: gen_chk_digest_masked + `CALIPTRA_ASSERT(StateZeroInvalid_A, !state_valid_o |-> ((|state_o[0]) | (|state_o[1])) == 1'b 0) + end else begin : gen_chk_digest_unmasked + `CALIPTRA_ASSERT(StateZeroInvalid_A, !state_valid_o |-> (|state_o[0]) == 1'b 0) + end + + // `state_valid_o` asserts only in between the completion and done + //`CALIPTRA_ASSERT(StateValidPeriod_A, state_valid_o |-> ) + + // skip the msg interface assertions as they are in sha3pad.sv + + // Software run signal happens in Squeezing stage + `CALIPTRA_ASSUME(SwRunInSqueezing_a, run_i |-> error_o.valid || (st == StSqueeze_sparse)) + + // If control received but not propagated into submodules, it is error condition + `CALIPTRA_ASSERT(ErrDetection_A, error_o.valid + |-> {start_i, process_i, run_i, done_i} + != {keccak_start, keccak_process, sw_keccak_run, keccak_done}) + +endmodule diff --git a/src/caliptra_ss_lc_ctrl/rtl/sha3_pkg.sv b/src/caliptra_ss_lc_ctrl/rtl/sha3_pkg.sv new file mode 100644 index 0000000..ea22cfa --- /dev/null +++ b/src/caliptra_ss_lc_ctrl/rtl/sha3_pkg.sv @@ -0,0 +1,294 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// sha3_pkg + +package sha3_pkg; + + // StateW represents the width of Keccak state variable. + // As Sha3 assume the state value as 1600, this shouldn't be modified. + // Note that keccak_round is flexible. It can have any values defined in SHA3 + // specification. But sha3pad logic assumes the value as 1600. + parameter int StateW = 1600; + + // Function Name (N) and Customzation String (S) shall be + // smaller than 2**256 bits and integer divisiable by 8. + parameter int FnWidth = 32; // up to 32bit Function Name + parameter int CsWidth = 256; // up to 256bit Customization Input + + // Calculate left_encode(len( X )) bit size. + // Assume the enc_8(n) is always 1 (up to 255 byte of len(S) size) + // e.g) 248bit --> two bytes , 256bit --> three bytes + // round8bit(clog2(X+1))/8 + + parameter int MaxFnEncodeSize = ($clog2(FnWidth+1) + 8 - 1) / 8 + 1; + parameter int MaxCsEncodeSize = ($clog2(CsWidth+1) + 8 - 1) / 8 + 1; + + parameter int NSRegisterSizePre = FnWidth/8 + CsWidth/8 + + MaxFnEncodeSize + MaxCsEncodeSize; + // Round up to 32bit word base + parameter int NSRegisterSize = ((NSRegisterSizePre + 4 - 1 ) / 4) * 4; + + // Prefix represents bytepad(encode_string(N) || encode_string(S), 168 or 136) + // +2 represents left_encoding(168 or 136) which could be either: + // 10000000 || 00010101 // 168 + // 10000000 || 00010001 // 136 + parameter int PrefixSize = NSRegisterSize + 2; + + // index width for `N` and `S` + parameter int PrefixIndexW = $clog2(PrefixSize/64); + + // Datapath width in KMAC, this also affects the output of MSG_FIFO + // This is assumed as 64 in KMAC design. If this value is changed, some parts + // of the KMAC design need to be changed. + // + // 1. keccak_round logic datapath. Keccak round logic assumes MsgWidth + // divides 1600 keccak state `Width`. Choose the value accordingly. + // 2. sha3pad module has fixed width mux for funcpad logic. If MsgWidth is + // changed, the logic also need to be revised. + // 3. kmac core logic also has fixed size mux for appeding output length. + // Revise the case statement to fit into revised MsgWidth value. + parameter int MsgWidth = 64; + parameter int MsgStrbW = MsgWidth / 8; + + // Keccak module supports SHA3, SHAKE, cSHAKE function. + // This mode determines if the module uses encoded N and S or not. + // Also it chooses the padding value. + // + // mode | little-endian + // -------|---------------- + // Sha3 | 2'b 10 + // Shake | 4'b 1111 + // CShake | 2'b 00 + // + // Please remind that if input strings N and S are empty, SW shall + // choose SHAKE even for cSHAKE operation. + typedef enum logic[1:0] { + Sha3 = 2'b 00, + Shake = 2'b 10, + CShake = 2'b 11 + } sha3_mode_e; + + // keccak_strength_e determines the security strength against collision attack + // This value decides the _rate_ and _capacity_ of the keccak states. + // It affects the sha3pad module too. the padding module implements + // `bytepad(X,168)` for L128, `bytepad(X,136)` for L256 in cSHAKE + typedef enum logic [2:0] { + L128 = 3'b 000, // rate: 1344 bit / capacity: 256 bit Keccak[ 256](, 128) + L224 = 3'b 001, // rate: 1152 bit / capacity: 448 bit Keccak[ 448](, 224) + L256 = 3'b 010, // rate: 1088 bit / capacity: 512 bit Keccak[ 512](, 256) + L384 = 3'b 011, // rate: 832 bit / capacity: 768 bit Keccak[ 768](, 384) + L512 = 3'b 100 // rate: 576 bit / capacity: 1024 bit Keccak[1024](, 512) + } keccak_strength_e; + + parameter int unsigned KeccakRate [5] = '{ + 1344/MsgWidth, // 21 depth := (1600 - 128*2) + 1152/MsgWidth, // 18 depth := (1600 - 224*2) + 1088/MsgWidth, // 17 depth := (1600 - 256*2) + 832/MsgWidth, // 13 depth := (1600 - 384*2) + 576/MsgWidth // 9 depth := (1600 - 512*2) + }; + + parameter int unsigned KeccakBitCapacity [5] = '{ + 2 * 128, // capacity for L128 + 2 * 224, // capacity for L224 + 2 * 256, // capacity for L256 + 2 * 384, // capacity for L384 + 2 * 512 // capacity for L512 + }; + + parameter int unsigned MaxBlockSize = KeccakRate[0]; + + parameter int unsigned KeccakEntries = 1600/MsgWidth; + parameter int unsigned KeccakMsgAddrW = $clog2(KeccakEntries); + + parameter int unsigned KeccakCountW = $clog2(KeccakEntries+1); + + // SHA3 core state. This state value is used in sha3core module + // and also in KMAC top module and the register interface for sw to track the + // sha3 status. + // Encoding generated with: + // $ ./util/design/sparse-fsm-encode.py -d 3 -m 7 -n 6 \ + // -s 4082450958 --language=sv + // + // Hamming distance histogram: + // + // 0: -- + // 1: -- + // 2: -- + // 3: |||||||||||||||||||| (57.14%) + // 4: ||||||||||||||| (42.86%) + // 5: -- + // 6: -- + // + // Minimum Hamming distance: 3 + // Maximum Hamming distance: 4 + // Minimum Hamming weight: 1 + // Maximum Hamming weight: 4 + // + localparam int StateWidth = 6; + typedef enum logic [StateWidth-1:0] { + StIdle_sparse = 6'b101100, + + // Absorb stage receives the message bitstream and computes the keccak + // rounds. This internal operation is mainly done inside sha3pad module + // not sha3core. The core module and this state machine observe the status + // of the process and mainly waits until all the sponge absorbing is + // completed. The main indicator is `absorbed` signal. + StAbsorb_sparse = 6'b100001, + + // Reserved state for context-switching. See #3479. + // Abort stage can be moved from StAbsorb stage. It basically holds the + // keccak round operation and opens up the internal state variable to the + // software. This stage is for the software to pause current operation and + // store the internal state elsewhere then initiates new KMAC/SHA3 process. + // StAbort only can be moved to _StFlush_. + //StAbort_sparse = 6'b011101, + + // Squeeze stage allows the software to read the internal state. + // If `EnMasking`, it opens the read permission of two share of the state. + // The squeezing in SHA3 specification describes the software to read up to + // the rate of SHA3 algorithm but this logic opens up the entire 1600 bits + // of the state (3200bits if `EnMasking`). + StSqueeze_sparse = 6'b001011, + + // ManualRun stage initiaties the keccak round and waits the completion. + // This state is moved from Squeeze state by writing 1 to manual_run CSR. + // When keccak round is completed, it goes back to Squeeze state. + StManualRun_sparse = 6'b010000, + + // Flush stage, the core clears out the internal variables and also + // submodules' variables too. Then moves back to Idle state. + StFlush_sparse = 6'b000110, + + StTerminalError_sparse = 6'b111010 + } sha3_st_sparse_e; + + localparam int StateWidthLogic = 3; + typedef enum logic [StateWidthLogic-1:0] { + StIdle, + StAbsorb, + //StAbort, + StSqueeze, + StManualRun, + StFlush, + StError + } sha3_st_e; + + function automatic sha3_st_e sparse2logic(sha3_st_sparse_e st); + unique case (st) + StIdle_sparse : return StIdle; + StAbsorb_sparse : return StAbsorb; + //StAbort_sparse : return StAbort; + StSqueeze_sparse : return StSqueeze; + StManualRun_sparse : return StManualRun; + StFlush_sparse : return StFlush; + default : return StError; + endcase + endfunction : sparse2logic + + + ////////////////////// + // Keccak Round FSM // + ////////////////////// + + // Encoding generated with: + // $ ./util/design/sparse-fsm-encode.py -d 3 -m 8 -n 6 \ + // -s 1363425333 --language=sv + // + // Hamming distance histogram: + // + // 0: -- + // 1: -- + // 2: -- + // 3: |||||||||||||||||||| (57.14%) + // 4: ||||||||||||||| (42.86%) + // 5: -- + // 6: -- + // + // Minimum Hamming distance: 3 + // Maximum Hamming distance: 4 + // Minimum Hamming weight: 1 + // Maximum Hamming weight: 5 + // + localparam int KeccakFsmWidth = 6; + typedef enum logic [KeccakFsmWidth-1:0] { + KeccakStIdle = 6'b011111, + + // Active state is used in Unmasked version only. + // It handles keccak round in a cycle + KeccakStActive = 6'b000100, + + // Phase1 --> Phase2Cycle1 --> Phase2Cycle2 --> Phase2Cycle3 + // Activated only in Masked version. + // Phase1 processes Theta, Rho, Pi steps in a cycle and stores the states + // into storage. It only moves to Phase2 once the randomness required for + // Phase2 is available. + KeccakStPhase1 = 6'b101101, + + // Chi Stage 1 for first lane halves. Unconditionally move to Phase2Cycle2. + KeccakStPhase2Cycle1 = 6'b000011, + + // Chi Stage 2 and Iota for first lane halves. Chi Stage 1 for second + // lane halves. Unconditionally move to Phase2Cycle3. + KeccakStPhase2Cycle2 = 6'b011000, + + // Chi Stage 2 and Iota for second lane halves. + // When doing the last round (MaxRound -1) it completes the process and + // goes back to Idle. If not, it repeats the phases again. + KeccakStPhase2Cycle3 = 6'b101010, + + // Error state. Not clearly defined yet. + // Intention is if any unexpected input in the process, state moves to + // here and report through the error fifo with debugging information. + KeccakStError = 6'b110001, + + KeccakStTerminalError = 6'b110110 + } keccak_st_e; + + + ////////////////// + // Error Report // + ////////////////// + typedef enum logic [7:0] { + ErrNone = 8'h 00, + + // ErrSha3SwControl occurs when software sent wrong flow signal. + // e.g) Sw set `process_i` without `start_i`. The state machine ignores + // the signal and report through the error FIFO. + ErrSha3SwControl = 8'h 80 + } err_code_e; + + typedef struct packed { + logic valid; + err_code_e code; // Type of error + logic [23:0] info; // Additional Debug info + } err_t; + + + /////////////// + // Functions // + /////////////// + + // Bytepading function + // `encode_bytepad_len` represents the first two bytes of bytepad() + // It depends on the block size. We can reuse KeccakRate + // 10000000 || 00010101 // 168 + // 10000000 || 00010001 // 136 + function automatic logic [15:0] encode_bytepad_len(keccak_strength_e kstrength); + logic [15:0] result; + unique case (kstrength) + L128: result = 16'h A801; // cSHAKE128 + L224: result = 16'h 9001; // not used + L256: result = 16'h 8801; // cSHAKE256 + L384: result = 16'h 6801; // not used + L512: result = 16'h 4801; // not used + + default: result = 16'h 0000; + endcase + return result; + endfunction : encode_bytepad_len + + +endpackage : sha3_pkg diff --git a/src/caliptra_ss_lc_ctrl/rtl/sha3pad.sv b/src/caliptra_ss_lc_ctrl/rtl/sha3pad.sv new file mode 100644 index 0000000..dc91796 --- /dev/null +++ b/src/caliptra_ss_lc_ctrl/rtl/sha3pad.sv @@ -0,0 +1,884 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// SHA3 padding logic + +`include "caliptra_prim_assert.sv" + +module sha3pad + import sha3_pkg::*; +#( + parameter bit EnMasking = 0, + localparam int Share = (EnMasking) ? 2 : 1 +) ( + input clk_i, + input rst_ni, + + // Message interface (FIFO) + input msg_valid_i, + input [MsgWidth-1:0] msg_data_i [Share], + input [MsgStrbW-1:0] msg_strb_i, // one strobe for shares + output logic msg_ready_o, + + // N, S: Used in cSHAKE mode only + input [NSRegisterSize*8-1:0] ns_data_i, // See sha3_pkg for details + + // output to keccak_round: message path + output logic keccak_valid_o, + output logic [KeccakMsgAddrW-1:0] keccak_addr_o, + output logic [MsgWidth-1:0] keccak_data_o [Share], + input logic keccak_ready_i, + + // keccak_round control and status + // `run` initiates the keccak_round to process full keccak_f (24rounds). + // `complete` is an input from keccak round showing the current keccak_f is + // completed. + output logic keccak_run_o, + input keccak_complete_i, + + // configurations + input sha3_mode_e mode_i, + // strength_i is used in bytepad operation. bytepad() is used in cSHAKE only. + // SHA3, SHAKE doesn't have encode_N,S + input keccak_strength_e strength_i, + + // control signal + // start_i is a pulse signal triggers the padding logic (and the rest of SHA) + // to accept the incoming messages. This signal is used in the pad module, + // to initiate the prefix transmitting to keccak_round + input start_i, + // process_i is a pulse signal triggers the pad logic to stop receiving the + // message from MSG_FIFO and pad the trailing bits specified in the SHA3 + // standard. Look at `funcpad` signal for the values. + input process_i, + // done_i is a pulse signal to make the pad logic to clear internal variables + // and to move back to the Idle state for next hashing process. + // done_i may not needed if sw controls the keccak_round directly. + input caliptra_prim_mubi_pkg::mubi4_t done_i, + + // Indication of the Keccak Sponge Absorbing is complete, it is time for SW to + // control the Keccak-round if it needs more digest, or complete by asserting + // `done_i` + output caliptra_prim_mubi_pkg::mubi4_t absorbed_o, + + // Life cycle + input caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_t caliptra_ss_lc_escalate_en_i, + + // Indication that there was a fault in the sparse encoding + output logic sparse_fsm_error_o, + + // Indication that there was a fault in the counter + output logic msg_count_error_o +); + + ///////////////// + // Definitions // + ///////////////// + + // Padding States + // Encoding generated with: + // $ ./util/design/sparse-fsm-encode.py -d 3 -m 10 -n 7 \ + // -s 1116691466 --language=sv + // + // Hamming distance histogram: + // + // 0: -- + // 1: -- + // 2: -- + // 3: |||||||||||||||||||| (42.22%) + // 4: |||||||||||||||||| (40.00%) + // 5: ||||| (11.11%) + // 6: || (4.44%) + // 7: | (2.22%) + // + // Minimum Hamming distance: 3 + // Maximum Hamming distance: 7 + // Minimum Hamming weight: 2 + // Maximum Hamming weight: 5 + // + localparam int StateWidthPad = 7; + typedef enum logic [StateWidthPad-1:0] { + StPadIdle = 7'b1000010, + + // Sending a block of prefix, if cSHAKE mode is turned on. For the rest + // (SHA3, SHAKE), sending prefix is not needed. FSM moves from Idle to + // Message directly in that case. + // + // As caliptra_prim_slicer is instantiated, zerofill after the actual prefix is done + // by the module. + StPrefix = 7'b0111100, + StPrefixWait =7'b1001100, + + // Sending Message. In this state, it directly forwards the incoming data + // to Keccak round module. If `process_i` is asserted, then the rest of the + // messages will be discarded until new `start_i` is asserted. + // + // The incoming data can be partial write. Padding logic counts the number + // of bytes received and pause if a block size is transferred. + StMessage = 7'b0100101, + StMessageWait = 7'b0001111, + + // After sending the messages, then `process_i` is set, the FSM pads at the + // end of the message based on `mode_i`. If this is the last byte of the + // block, then it pads [7] to 1 to complete `pad10*1()` function. + StPad = 7'b1111010, + StPadRun = 7'b0011001, + + // If the padding isn't the end of the block byte (which will be rare case), + // FSM moves to another zerofill state. In contrast to StZerofill, this state + StPad01 = 7'b1101001, + + // Flushing the internal packers in front of the Keccak data output port. + StPadFlush = 7'b1010111, + + StTerminalError = 7'b0110011 + } pad_st_e; + + typedef enum logic [2:0] { + MuxNone = 3'b 000, + MuxFifo = 3'b 001, + MuxPrefix = 3'b 010, + MuxFuncPad = 3'b 011, + MuxZeroEnd = 3'b 100 + } mux_sel_e; + + //////////////////// + // Configurations // + //////////////////// + + logic [KeccakCountW-1:0] block_addr_limit; + + // Block size based on the address. + // This is used for bytepad() and also pad10*1() + // assign block_addr_limit = KeccakRate[strength_i]; + // but below is easier to understand + always_comb begin + unique case (strength_i) + L128: block_addr_limit = KeccakCountW'(KeccakRate[L128]); + L224: block_addr_limit = KeccakCountW'(KeccakRate[L224]); + L256: block_addr_limit = KeccakCountW'(KeccakRate[L256]); + L384: block_addr_limit = KeccakCountW'(KeccakRate[L384]); + L512: block_addr_limit = KeccakCountW'(KeccakRate[L512]); + + default: block_addr_limit = '0; + endcase + end + + ///////////////////// + // Control Signals // + ///////////////////// + + // `sel_mux` selects the output data among the incoming or internally generated data. + // MuxFifo: data from external (msg_data_i) + // MuxPrefix: bytepad(encode_string(N)||encode_string(S), ) + // MuxFuncPad: function_pad with end of message + // MuxZeroEnd: all 0 + mux_sel_e sel_mux; + + // `sent_message` indicates the number of entries sent to keccak round per + // block. The value shall be enough to cover Maximum entry of the Keccak + // storage as defined in sha3_pkg, `$clog2(KeccakEntries+1)`. Logically, + // it is not needed to have more than KeccakEntries but for safety in case of + // SHA3 context switch resuming the SHA3 from the middle of sponge + // construction. If needed, the software should be able to write whole 1600 + // bits. The `sent_message` is used to check sent_blocksize. + logic [KeccakCountW-1:0] sent_message; + logic inc_sentmsg, clr_sentmsg; + + // This primitive is used to place a hardened counter + // SEC_CM: CTR.REDUN + caliptra_prim_count #( + .Width(KeccakCountW) + ) u_sentmsg_count ( + .clk_i, + .rst_ni, + .clr_i(clr_sentmsg), + .set_i(1'b0), + .set_cnt_i(KeccakCountW'(0)), + .incr_en_i(inc_sentmsg), + .decr_en_i(1'b0), + .step_i(KeccakCountW'(1)), + .commit_i(1'b1), + .cnt_o(sent_message), + .cnt_after_commit_o(), + .err_o(msg_count_error_o) + ); + + + assign inc_sentmsg = keccak_valid_o & keccak_ready_i ; + + // Prefix index to slice the `prefix` n-bits into multiple of 64bit. + logic [KeccakMsgAddrW-1:0] prefix_index; + assign prefix_index = (sent_message < block_addr_limit) ? sent_message : '0; + + // fsm_keccak_valid is an output signal from FSM which to send data generated + // inside the pad logic to keccak_round + logic fsm_keccak_valid; + + // hold_msg to prevent message from being forwarded into keccak_round and + // acked. Mainly the usage is to hold the message and initiates the + // keccak_round for current block. + logic hold_msg; + + // latch the partial write. Latched data is used for funcpad_merged + logic en_msgbuf; + logic clr_msgbuf; + + /////////////////// + // State Machine // + /////////////////// + + // Inputs + + // FSM moves to StPrefix only when cSHAKE is enabled + logic mode_eq_cshake; + assign mode_eq_cshake = (mode_i == CShake) ? 1'b 1 : 1'b 0; + + // `sent_blocksize` indicates the pad logic pushed block size data into + // keccak round logic. + logic sent_blocksize; + + assign sent_blocksize = (sent_message == block_addr_limit) ? 1'b 1 : 1'b 0; + + // `keccak_ack` indicates the request is accepted in keccak_round + logic keccak_ack; + + assign keccak_ack = keccak_valid_o & keccak_ready_i ; + + // msg_partial indicates the incoming message is partial write or not. + // This is used to check if the incoming message need to be latched inside or + // not. If no partial message is at the end, msg_buf doesn't have to latch + // msg_data_i. It is assumed that the partial message is permitted only at + // the end of the message. So if (msg_valid_i && msg_partial && msg_ready_o), + // there will be no msg_valid_i till process_latched. + // Shall be used with msg_valid_i together. + logic msg_partial; + assign msg_partial = (&msg_strb_i != 1'b 1); + + + // `process_latched` latches the `process_i` input before it is seen in the + // FSM. `process_i` may follow `start_i` too fast so that the FSM may not + // see it fast enought in case of cSHAKE mode. cSHAKE needs to process the + // prefix prior to see the process indicator. + logic process_latched; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + process_latched <= 1'b 0; + end else if (process_i) begin + process_latched <= 1'b 1; + end else if (caliptra_prim_mubi_pkg::mubi4_test_true_strict(done_i)) begin + process_latched <= 1'b0; + end + end + + // State Register =========================================================== + pad_st_e st, st_d; + + `CALIPTRA_PRIM_FLOP_SPARSE_FSM(u_state_regs, st_d, st, pad_st_e, StPadIdle) + + // `end_of_block` indicates current beat is end of the block + // It shall set when the address reaches to the end of the block. End address + // is set by the strength_i, which is `block_addr_limit`. + logic end_of_block; + + assign end_of_block = ((sent_message + 1'b1) == block_addr_limit) ? 1'b 1 : 1'b 0; + + + // Next logic and output logic ============================================== + // SEC_CM: ABSORBED.CTRL.MUBI + caliptra_prim_mubi_pkg::mubi4_t absorbed_d; + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) absorbed_o <= caliptra_prim_mubi_pkg::MuBi4False; + else absorbed_o <= absorbed_d; + end + + always_comb begin + st_d = st; + + // FSM output : default values + keccak_run_o = 1'b 0; + sel_mux = MuxNone; + + fsm_keccak_valid = 1'b 0; + + hold_msg = 1'b 0; + clr_sentmsg = 1'b 0; + + en_msgbuf = 1'b 0; + clr_msgbuf = 1'b 0; + + absorbed_d = caliptra_prim_mubi_pkg::MuBi4False; + + sparse_fsm_error_o = 1'b 0; + + unique case (st) + + // In Idle state, the FSM checks if the software (or upper FSM) initiates + // the hash process. If `start_i` is asserted (assume it is pulse), FSM + // starts to push the data into the keccak round logic. Depending on the + // hashing mode, FSM may push additional prefex in front of the actual + // message. It means, the message could be back-pressured until the first + // prefix is processed. + StPadIdle: begin + if (start_i) begin + // If cSHAKE, move to Prefix state + if (mode_eq_cshake) begin + st_d = StPrefix; + end else begin + st_d = StMessage; + end + end else begin + st_d = StPadIdle; + end + end + + // At Prefix state, FSM pushes + // `bytepad(encode_string(N)||encode_string(S), 168or136)`. The software + // already prepared `encode_string(N) || encode_string(S)` in the regs. + // So, the FSM adds 2Byte in front of ns_data_i, which is an encoded + // block size (see `encoded_bytepad` below) + // After pushing the prefix, it initiates the hash process and move to + // Message state. + StPrefix: begin + sel_mux = MuxPrefix; + + if (sent_blocksize) begin + st_d = StPrefixWait; + + keccak_run_o = 1'b 1; + fsm_keccak_valid = 1'b 0; + clr_sentmsg = 1'b 1; + end else begin + st_d = StPrefix; + + fsm_keccak_valid = 1'b 1; + end + end + + StPrefixWait: begin + sel_mux = MuxPrefix; + + if (keccak_complete_i) begin + st_d = StMessage; + end else begin + st_d = StPrefixWait; + end + end + + // Message state pushes the incoming message into keccak round logic. + // It forwards the message while counting the data and if it reaches + // the block size, it triggers the keccak round to run. If `process` is + // set, it moves to Pad state. + StMessage: begin + sel_mux = MuxFifo; + + if (msg_valid_i && msg_partial) begin + st_d = StMessage; + + en_msgbuf = 1'b 1; + end else if (sent_blocksize) begin + // Check block completion first even process is set. + st_d = StMessageWait; + + keccak_run_o = 1'b 1; + clr_sentmsg = 1'b 1; + hold_msg = 1'b 1; + end else if (process_latched || process_i) begin + st_d = StPad; + + // Not asserting the msg_ready_o + hold_msg = 1'b 1; + end else begin + st_d = StMessage; + + end + end + + StMessageWait: begin + hold_msg = 1'b 1; + + if (keccak_complete_i) begin + st_d = StMessage; + end else begin + st_d = StMessageWait; + end + end + + // Pad state just pushes the ending suffix. Depending on the mode, the + // padding value is unique. SHA3 adds 2'b10, SHAKE adds 4'b1111, and + // cSHAKE adds 2'b 00. Refer `function_pad`. The signal has one more bit + // defined to accomodate first 1 bit of `pad10*1()` function. + StPad: begin + sel_mux = MuxFuncPad; + + fsm_keccak_valid = 1'b 1; + + if (keccak_ack && end_of_block) begin + // If padding is the last block, don't have to move to StPad01, just + // run Keccak and complete + st_d = StPadRun; + + // always clear the latched msgbuf + clr_msgbuf = 1'b 1; + clr_sentmsg = 1'b 1; + end else if (keccak_ack) begin + st_d = StPad01; + clr_msgbuf = 1'b 1; + end else begin + st_d = StPad; + end + end + + StPadRun: begin + st_d = StPadFlush; + + keccak_run_o = 1'b 1; + clr_sentmsg = 1'b 1; + end + + // Pad01 pushes the end bit of pad10*1() function. As keccak accepts byte + // size only, StPad always pushes partial (5bits). So at this state, it + // pushes rest of 3bits. If the data pushed in StPad is the last byte of + // the block, then Pad01 pushes to the same byte, if not, it first + // zero-fill the block then pad 1 to the end. + StPad01: begin + sel_mux = MuxZeroEnd; + + // There's no chance StPad01 can be a start of the block. So can be + // discard that the sent_blocksize is set at the beginning. + if (sent_blocksize) begin + st_d = StPadFlush; + + fsm_keccak_valid = 1'b 0; + keccak_run_o = 1'b 1; + clr_sentmsg = 1'b 1; + end else begin + st_d = StPad01; + + fsm_keccak_valid = 1'b 1; + end + end + + StPadFlush: begin + // Wait completion from keccak_round or wait SW indicator. + clr_sentmsg = 1'b 1; + clr_msgbuf = 1'b 1; + + if (keccak_complete_i) begin + st_d = StPadIdle; + + absorbed_d = caliptra_prim_mubi_pkg::MuBi4True; + end else begin + st_d = StPadFlush; + end + end + + StTerminalError: begin + // this state is terminal + st_d = st; + sparse_fsm_error_o = 1'b 1; + end + + default: begin + // this state is terminal + st_d = StTerminalError; + sparse_fsm_error_o = 1'b 1; + end + endcase + + // SEC_CM: FSM.GLOBAL_ESC, FSM.LOCAL_ESC + // Unconditionally jump into the terminal error state + // if the life cycle controller triggers an escalation. + if (caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_test_true_loose(caliptra_ss_lc_escalate_en_i)) begin + st_d = StTerminalError; + end + end + + ////////////// + // Datapath // + ////////////// + + // `encode_bytepad` represents the first two bytes of bytepad() + // It depends on the block size. We can reuse KeccakRate + // 10000000 || 00010101 // 168 + // 10000000 || 00010001 // 136 + logic [15:0] encode_bytepad; + + assign encode_bytepad = encode_bytepad_len(strength_i); + + // Prefix size ============================================================== + // Prefix represents bytepad(encode_string(N) || encode_string(S), 168 or 136) + // encode_string(N) || encode_string(S) is prepared by the software and given + // through `ns_data_i`. The first part of bytepad is determined by the + // `strength_i` and stored into `encode_bytepad`. + + // It is assumed that the prefix always smaller than the block size. + logic [PrefixSize*8-1:0] prefix; + + assign prefix = {ns_data_i, encode_bytepad}; + + logic [MsgWidth-1:0] prefix_sliced; + logic [MsgWidth-1:0] prefix_data [Share]; + + caliptra_prim_slicer #( + .InW (PrefixSize*8), + .IndexW(KeccakMsgAddrW), + .OutW(MsgWidth) + ) u_prefix_slicer ( + .sel_i (prefix_index), + .data_i (prefix), + .data_o (prefix_sliced) + ); + + if (EnMasking) begin : gen_prefix_masked + // If Masking is enabled, prefix is two share. + assign prefix_data[0] = '0; + assign prefix_data[1] = prefix_sliced; + end else begin : gen_prefix_unmasked + // If Unmasked, only one share exists. + assign prefix_data[0] = prefix_sliced; + end + + // ========================================================================== + // function_pad is the unique value padded at the end of the message based on + // the function among SHA3, SHAKE, cSHAKE. The standard mentioned that SHA3 + // pads `01` , SHAKE pads `1111`, and cSHAKE pads `00`. + // + // Then pad10*1() function follows. It adds `1` first then fill 0 until it + // reaches the block size -1, then adds `1`. + // + // It means always `1` is followed by the function pad. + logic [4:0] funcpad; + + logic [MsgWidth-1:0] funcpad_data [Share]; + + always_comb begin + unique case (mode_i) + Sha3: funcpad = 5'b 00110; + Shake: funcpad = 5'b 11111; + CShake: funcpad = 5'b 00100; + + default: begin + // Just create non-padding but pad10*1 only + funcpad = 5'b 00001; + end + endcase + end + + // ========================================================================== + // `zero_with_endbit` contains all zero unless the message is for the last + // MsgWidth beat in the block. If it is the end of the block, the last bit + // will be set to complete pad10*1() functionality. + logic [MsgWidth-1:0] zero_with_endbit [Share]; + + if (EnMasking) begin : gen_zeroend_masked + assign zero_with_endbit[0] = '0; + assign zero_with_endbit[1][MsgWidth-1] = end_of_block; + assign zero_with_endbit[1][MsgWidth-2:0] = '0; + end else begin : gen_zeroend_unmasked + assign zero_with_endbit[0][MsgWidth-1] = end_of_block; + assign zero_with_endbit[0][MsgWidth-2:0] = '0; + end + + // ========================================================================== + // Data mux for output data + + assign keccak_addr_o = (sent_message < block_addr_limit) ? sent_message : '0; + + always_comb begin + unique case (sel_mux) + MuxFifo: keccak_data_o = msg_data_i; + MuxPrefix: keccak_data_o = prefix_data; + MuxFuncPad: keccak_data_o = funcpad_data; + MuxZeroEnd: keccak_data_o = zero_with_endbit; + + // MuxNone + default: keccak_data_o = '{default:'0}; + endcase + end + + always_comb begin + unique case (sel_mux) + MuxFifo: keccak_valid_o = msg_valid_i & ~hold_msg & ~en_msgbuf; + MuxPrefix: keccak_valid_o = fsm_keccak_valid; + MuxFuncPad: keccak_valid_o = fsm_keccak_valid; + MuxZeroEnd: keccak_valid_o = fsm_keccak_valid; + + // MuxNone + default: keccak_valid_o = 1'b 0; + endcase + end + + always_comb begin + unique case (sel_mux) + MuxFifo: msg_ready_o = en_msgbuf | (keccak_ready_i & ~hold_msg); + MuxPrefix: msg_ready_o = 1'b 0; + MuxFuncPad: msg_ready_o = 1'b 0; + MuxZeroEnd: msg_ready_o = 1'b 0; + + // MuxNone + default: msg_ready_o = 1'b 0; + endcase + end + + // caliptra_prim_packer : packing to 64bit to update keccak storage + // two caliptra_prim_packer in this module are used to pack the data received from + // upper layer (KMAC core) and also the 5bit padding bits. + // It is assumed that the message from upper layer could be partial at the + // end of the message. Then the 2 or 4bit padding is required. It can be + // handled by some custom logic or could be done by caliptra_prim_packer. + // If packer is used, the MSG_FIFO doesn't have to have another caliptra_prim_packer + // in front of the FIFO. This logic can handle the partial writes from the + // software. + // + // If a custom logic is implemented here, caliptra_prim_packer is necessary in front + // of the FIFO, as this logic only appends at the end of the message when + // `process_i` is asserted. Also, in this case, even caliptra_prim_packer is not + // needed, still 64bit registers to latch the partial write is required. + // If not, the logic has to delay the acceptance of the incoming write + // accesses. It may trigger the back-pressuring in some case which may result + // that the software(or upper layer) may not set process_i. + // + // For custom logic, it could be implemented by the 8 mux selection. + // for instance: (subject to be changed) + // unique case (sent_byte[2:0]) // generated from msg_strb_i + // 3'b 000: funcpad_merged = {end_of_block, 63'(function_pad) }; + // 3'b 001: funcpad_merged = {end_of_block, 55'(function_pad), msg_data_i[ 7:0]}; + // 3'b 010: funcpad_merged = {end_of_block, 47'(function_pad), msg_data_i[15:0]}; + // 3'b 011: funcpad_merged = {end_of_block, 39'(function_pad), msg_data_i[23:0]}; + // 3'b 100: funcpad_merged = {end_of_block, 31'(function_pad), msg_data_i[31:0]}; + // 3'b 101: funcpad_merged = {end_of_block, 23'(function_pad), msg_data_i[39:0]}; + // 3'b 110: funcpad_merged = {end_of_block, 15'(function_pad), msg_data_i[47:0]}; + // 3'b 111: funcpad_merged = {end_of_block, 7'(function_pad), msg_data_i[55:0]}; + // default: funcpad_merged = '0; + // endcase + + // internal buffer to store partial write. It doesn't have to store last byte as it + // stores only when partial write. + logic [MsgWidth-8-1:0] msg_buf [Share]; + logic [MsgStrbW-1-1:0] msg_strb; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + msg_buf <= '{default:'0}; + msg_strb <= '0; + end else if (en_msgbuf) begin + for (int i = 0 ; i < Share ; i++) begin + msg_buf[i] <= msg_data_i[i][0+:(MsgWidth-8)]; + end + msg_strb <= msg_strb_i[0+:(MsgStrbW-1)]; + end else if (clr_msgbuf) begin + msg_buf <= '{default:'0}; + msg_strb <= '0; + end + end + + if (EnMasking) begin : gen_funcpad_data_masked + always_comb begin + unique case (msg_strb) + 7'b 000_0000: begin + funcpad_data[0] = '0; + funcpad_data[1] = {end_of_block, 63'(funcpad) }; + end + 7'b 000_0001: begin + funcpad_data[0] = {56'h0, msg_buf[0][ 7:0]}; + funcpad_data[1] = {end_of_block, 55'(funcpad), msg_buf[1][ 7:0]}; + end + 7'b 000_0011: begin + funcpad_data[0] = {48'h0, msg_buf[0][15:0]}; + funcpad_data[1] = {end_of_block, 47'(funcpad), msg_buf[1][15:0]}; + end + 7'b 000_0111: begin + funcpad_data[0] = {40'h0, msg_buf[0][23:0]}; + funcpad_data[1] = {end_of_block, 39'(funcpad), msg_buf[1][23:0]}; + end + 7'b 000_1111: begin + funcpad_data[0] = {32'h0, msg_buf[0][31:0]}; + funcpad_data[1] = {end_of_block, 31'(funcpad), msg_buf[1][31:0]}; + end + 7'b 001_1111: begin + funcpad_data[0] = {24'h0, msg_buf[0][39:0]}; + funcpad_data[1] = {end_of_block, 23'(funcpad), msg_buf[1][39:0]}; + end + 7'b 011_1111: begin + funcpad_data[0] = {16'h0, msg_buf[0][47:0]}; + funcpad_data[1] = {end_of_block, 15'(funcpad), msg_buf[1][47:0]}; + end + 7'b 111_1111: begin + funcpad_data[0] = { 8'h0, msg_buf[0][55:0]}; + funcpad_data[1] = {end_of_block, 7'(funcpad), msg_buf[1][55:0]}; + end + + default: funcpad_data = '{default:'0}; + endcase + end + end else begin : gen_funcpad_data_unmasked + always_comb begin + unique case (msg_strb) + 7'b 000_0000: funcpad_data[0] = {end_of_block, 63'(funcpad) }; + 7'b 000_0001: funcpad_data[0] = {end_of_block, 55'(funcpad), msg_buf[0][ 7:0]}; + 7'b 000_0011: funcpad_data[0] = {end_of_block, 47'(funcpad), msg_buf[0][15:0]}; + 7'b 000_0111: funcpad_data[0] = {end_of_block, 39'(funcpad), msg_buf[0][23:0]}; + 7'b 000_1111: funcpad_data[0] = {end_of_block, 31'(funcpad), msg_buf[0][31:0]}; + 7'b 001_1111: funcpad_data[0] = {end_of_block, 23'(funcpad), msg_buf[0][39:0]}; + 7'b 011_1111: funcpad_data[0] = {end_of_block, 15'(funcpad), msg_buf[0][47:0]}; + 7'b 111_1111: funcpad_data[0] = {end_of_block, 7'(funcpad), msg_buf[0][55:0]}; + + default: funcpad_data = '{default:'0}; + endcase + end + end + + //////////////// + // Assertions // + //////////////// + + // Prefix size is smaller than the smallest Keccak Block Size, which is 72 bytes. + `CALIPTRA_ASSERT_INIT(PrefixLessThanBlock_A, PrefixSize/8 < KeccakRate[4]) + + // Some part of datapath in sha3pad assumes Data width as 64bit. + // If data width need to be changed, funcpad_data part should be changed too. + // Also, The blocksize shall be divided by MsgWidth, which means, MsgWidth + // can be {16, 32, 64} even funcpad_data mux is fully flexible. + `CALIPTRA_ASSERT_INIT(MsgWidthidth_A, MsgWidth == 64) + + // Assume pulse signals: start, process, done + `CALIPTRA_ASSUME(StartPulse_A, start_i |=> !start_i) + `CALIPTRA_ASSUME(ProcessPulse_A, process_i |=> !process_i) + `CALIPTRA_ASSUME(DonePulse_A, + caliptra_prim_mubi_pkg::mubi4_test_true_strict(done_i) |=> + caliptra_prim_mubi_pkg::mubi4_test_false_strict(done_i)) + + // ASSERT output pulse signals: absorbed_o, keccak_run_o + `CALIPTRA_ASSERT(AbsorbedPulse_A, + caliptra_prim_mubi_pkg::mubi4_test_true_strict(absorbed_o) |=> + caliptra_prim_mubi_pkg::mubi4_test_false_strict(absorbed_o)) + `CALIPTRA_ASSERT(KeccakRunPulse_A, keccak_run_o |=> !keccak_run_o) + + // start_i, done_i, process_i cannot set high at the same time + `CALIPTRA_ASSUME(StartProcessDoneMutex_a, + $onehot0({ + start_i, + process_i, + caliptra_prim_mubi_pkg::mubi4_test_true_loose(done_i) + })) + + // Sequence, start_i --> process_i --> absorbed_o --> done_i + //`CALIPTRA_ASSUME(Sequence_a, start_i ##[1:$] process_i ##[1:$] ##[1:$] absorbed_o ##[1:$] done_i) + +`ifndef SYNTHESIS + // Process only asserts after start and all message are fed. + // These valid signals are qualifier of FPV to trigger the control signal + // It is a little bit hard to specify these criteria in SVA property so creating + // qualifiers in RTL form is easier. + logic start_valid, process_valid, absorb_valid, done_valid; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + start_valid <= 1'b 1; + end else if (start_i) begin + start_valid <= 1'b 0; + end else if (caliptra_prim_mubi_pkg::mubi4_test_true_strict(done_i)) begin + start_valid <= 1'b 1; + end + end + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + process_valid <= 1'b 0; + end else if (start_i) begin + process_valid <= 1'b 1; + end else if (process_i) begin + process_valid <= 1'b 0; + end + end + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + done_valid <= 1'b 0; + end else if (caliptra_prim_mubi_pkg::mubi4_test_true_strict(absorbed_o)) begin + done_valid <= 1'b 1; + end else if (caliptra_prim_mubi_pkg::mubi4_test_true_strict(done_i)) begin + done_valid <= 1'b 0; + end + end + + // Message can be fed in between start_i and process_i. + `CALIPTRA_ASSUME(MessageCondition_M, msg_valid_i && msg_ready_o |-> process_valid && !process_i) + + // Message ready should be asserted only in between start_i and process_i + `CALIPTRA_ASSERT(MsgReadyCondition_A, msg_ready_o |-> process_valid && !process_i) + + `CALIPTRA_ASSUME(ProcessCondition_M, process_i |-> process_valid) + `CALIPTRA_ASSUME(StartCondition_M, start_i |-> start_valid) + `CALIPTRA_ASSUME(DoneCondition_M, + caliptra_prim_mubi_pkg::mubi4_test_true_strict(done_i) |-> done_valid) + + // Assume mode_i and strength_i are stable during the operation + // This will be guarded at the kmac top level + `CALIPTRA_ASSUME(ModeStableDuringOp_M, + $changed(mode_i) |-> start_valid) + `CALIPTRA_ASSUME(StrengthStableDuringOp_M, + $changed(strength_i) |-> start_valid) + +`endif // SYNTHESIS + + // If not full block is written, the pad shall send message to keccak_round + // If it is end of the message, the state moves to StPad and send the request + `CALIPTRA_ASSERT(CompleteBlockWhenProcess_A, + $rose(process_latched) && (!end_of_block && !sent_blocksize ) + && !(st inside {StPrefixWait, StMessageWait}) |-> ##[1:5] keccak_valid_o, + clk_i, !rst_ni || caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_test_true_loose(caliptra_ss_lc_escalate_en_i)) + + // If process_i asserted, completion shall be asserted shall be asserted + //`CALIPTRA_ASSERT(ProcessToAbsorbed_A, process_i |=> strong(##[24*Share:$] absorbed_o)) + + + // Assumption of input mode_i and strength_i + // SHA3 variants: SHA3-224, SHA3-256, SHA3-384, SHA3-512 + // SHAKE, cSHAKE variants: SHAKE128, SHAKE256, cSHAKE128, cSHAKE256 + `CALIPTRA_ASSUME_FPV(ModeStrengthCombinations_M, + start_i |-> + (mode_i == Sha3 && (strength_i inside {L224, L256, L384, L512})) || + ((mode_i == Shake || mode_i == CShake) && (strength_i inside {L128, L256})), + clk_i, !rst_ni) + + // No partial write is allowed for Message FIFO interface + `CALIPTRA_ASSUME(NoPartialMsgFifo_M, + keccak_valid_o && (sel_mux == MuxFifo) |-> (&msg_strb_i) == 1'b1, + clk_i, !rst_ni) + + // When transaction is stored into msg_buf, it shall be partial write. + `CALIPTRA_ASSUME(AlwaysPartialMsgBuf_M, + en_msgbuf |-> msg_valid_i && (msg_strb_i[MsgStrbW-1] == 1'b0), + clk_i, !rst_ni) + + // if partial write comes and is acked, then no more msg_valid_i until + // next message + `CALIPTRA_ASSUME(PartialEndOfMsg_M, + msg_valid_i && msg_ready_o && msg_partial |=> + !msg_valid_i ##[1:$] $stable(msg_valid_i) ##1 process_latched, + clk_i, !rst_ni) + + // At the first clock in StPad01 state, sent_blocksize shall not be set + `CALIPTRA_ASSERT(Pad01NotAttheEndOfBlock_A, + (st == StPad && st_d == StPad01) |-> !end_of_block, + clk_i, !rst_ni) + + // When data sent to the keccak_round, the address should be in the range + `CALIPTRA_ASSERT(KeccakAddrInRange_A, + keccak_valid_o |-> keccak_addr_o < KeccakRate[strength_i], + clk_i, !rst_ni) + + // NS data shall be stable during the operation. + //`CALIPTRA_ASSUME(NsStableInProcess_A, + // $stable(ns_data_i) throughout(start_i ##[1:$] process_i ##[1:$] absorbed_o), + // clk_i, !rst_ni) + + // Functional Coverage + `CALIPTRA_COVER(StMessageFeed_C, st == StMessage) + `CALIPTRA_COVER(StPad_C, st == StPad01 && sent_blocksize) + `CALIPTRA_COVER(StPadSendMsg_C, st == StPad01 && keccak_ack) + `CALIPTRA_COVER(StComplete_C, st == StPadFlush) +endmodule diff --git a/src/caliptra_ss_lc_ctrl/rtl/top_pkg.sv b/src/caliptra_ss_lc_ctrl/rtl/top_pkg.sv new file mode 100644 index 0000000..fd750a3 --- /dev/null +++ b/src/caliptra_ss_lc_ctrl/rtl/top_pkg.sv @@ -0,0 +1,22 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// + +package top_pkg; + +localparam int TL_AW=32; +localparam int TL_DW=32; // = TL_DBW * 8; TL_DBW must be a power-of-two +localparam int TL_AIW=8; // a_source, d_source +localparam int TL_DIW=1; // d_sink +localparam int TL_AUW=23; // a_user +localparam int TL_DUW=14; // d_user +localparam int TL_DBW=(TL_DW>>3); +localparam int TL_SZW=$clog2($clog2(TL_DBW)+1); + +// NOTE THAT THIS IS A FEATURE FOR TEST CHIPS ONLY TO MITIGATE +// THE RISK OF A BROKEN OTP MACRO. THIS WILL BE DISABLED FOR +// PRODUCTION DEVICES. +localparam int SecVolatileRawUnlockEn = 0; + +endpackage diff --git a/src/dmi/config/compile.yml b/src/dmi/config/compile.yml new file mode 100644 index 0000000..e4344f4 --- /dev/null +++ b/src/dmi/config/compile.yml @@ -0,0 +1,27 @@ +--- +provides: [dm_pkg] +schema_version: 2.4.0 +requires: + - caliptra_prim_pkg +targets: + rtl: + directories: [$COMPILE_ROOT/rtl] + files: + - $COMPILE_ROOT/rtl/dm_pkg.sv + tb: + directories: [$COMPILE_ROOT/rtl] + files: + - $COMPILE_ROOT/rtl/dm_pkg.sv +--- +provides: [dmi_jtag] +schema_version: 2.4.0 +requires: + - dm_pkg +targets: + rtl: + directories: [$COMPILE_ROOT/rtl] + files: + - $COMPILE_ROOT/rtl/dmi_jtag_tap.sv + - $COMPILE_ROOT/rtl/dmi_cdc.sv + - $COMPILE_ROOT/rtl/dmi_jtag.sv + tops: [dmi_jtag] diff --git a/src/dmi/rtl/dm_pkg.sv b/src/dmi/rtl/dm_pkg.sv new file mode 100644 index 0000000..a8a27d2 --- /dev/null +++ b/src/dmi/rtl/dm_pkg.sv @@ -0,0 +1,451 @@ +/* Copyright 2018 ETH Zurich and University of Bologna. + * Copyright and related rights are licensed under the Solderpad Hardware + * License, Version 0.51 (the “License”); you may not use this file except in + * compliance with the License. You may obtain a copy of the License at + * http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law + * or agreed to in writing, software, hardware and materials distributed under + * this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR + * CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * File: dm_pkg.sv + * Author: Florian Zaruba + * Date: 30.6.2018 + * + * Description: Debug-module package, contains common system definitions. + * + */ + +package dm; + localparam logic [3:0] DbgVersion013 = 4'h2; + // size of program buffer in junks of 32-bit words + localparam logic [4:0] ProgBufSize = 5'h8; + + // amount of data count registers implemented + localparam logic [3:0] DataCount = 4'h2; + + // address to which a hart should jump when it was requested to halt + localparam logic [63:0] HaltAddress = 64'h800; + localparam logic [63:0] ResumeAddress = HaltAddress + 8; + localparam logic [63:0] ExceptionAddress = HaltAddress + 16; + + // address where data0-15 is shadowed or if shadowed in a CSR + // address of the first CSR used for shadowing the data + localparam logic [11:0] DataAddr = 12'h380; // we are aligned with Rocket here + + // debug registers + typedef enum logic [7:0] { + Data0 = 8'h04, + Data1 = 8'h05, + Data2 = 8'h06, + Data3 = 8'h07, + Data4 = 8'h08, + Data5 = 8'h09, + Data6 = 8'h0A, + Data7 = 8'h0B, + Data8 = 8'h0C, + Data9 = 8'h0D, + Data10 = 8'h0E, + Data11 = 8'h0F, + DMControl = 8'h10, + DMStatus = 8'h11, // r/o + Hartinfo = 8'h12, + HaltSum1 = 8'h13, + HAWindowSel = 8'h14, + HAWindow = 8'h15, + AbstractCS = 8'h16, + Command = 8'h17, + AbstractAuto = 8'h18, + DevTreeAddr0 = 8'h19, + DevTreeAddr1 = 8'h1A, + DevTreeAddr2 = 8'h1B, + DevTreeAddr3 = 8'h1C, + NextDM = 8'h1D, + ProgBuf0 = 8'h20, + ProgBuf1 = 8'h21, + ProgBuf2 = 8'h22, + ProgBuf3 = 8'h23, + ProgBuf4 = 8'h24, + ProgBuf5 = 8'h25, + ProgBuf6 = 8'h26, + ProgBuf7 = 8'h27, + ProgBuf8 = 8'h28, + ProgBuf9 = 8'h29, + ProgBuf10 = 8'h2A, + ProgBuf11 = 8'h2B, + ProgBuf12 = 8'h2C, + ProgBuf13 = 8'h2D, + ProgBuf14 = 8'h2E, + ProgBuf15 = 8'h2F, + AuthData = 8'h30, + HaltSum2 = 8'h34, + HaltSum3 = 8'h35, + SBAddress3 = 8'h37, + SBCS = 8'h38, + SBAddress0 = 8'h39, + SBAddress1 = 8'h3A, + SBAddress2 = 8'h3B, + SBData0 = 8'h3C, + SBData1 = 8'h3D, + SBData2 = 8'h3E, + SBData3 = 8'h3F, + HaltSum0 = 8'h40 + } dm_csr_e; + + // debug causes + localparam logic [2:0] CauseBreakpoint = 3'h1; + localparam logic [2:0] CauseTrigger = 3'h2; + localparam logic [2:0] CauseRequest = 3'h3; + localparam logic [2:0] CauseSingleStep = 3'h4; + + typedef struct packed { + logic [31:23] zero1; + logic impebreak; + logic [21:20] zero0; + logic allhavereset; + logic anyhavereset; + logic allresumeack; + logic anyresumeack; + logic allnonexistent; + logic anynonexistent; + logic allunavail; + logic anyunavail; + logic allrunning; + logic anyrunning; + logic allhalted; + logic anyhalted; + logic authenticated; + logic authbusy; + logic hasresethaltreq; + logic devtreevalid; + logic [3:0] version; + } dmstatus_t; + + typedef struct packed { + logic haltreq; + logic resumereq; + logic hartreset; + logic ackhavereset; + logic zero1; + logic hasel; + logic [25:16] hartsello; + logic [15:6] hartselhi; + logic [5:4] zero0; + logic setresethaltreq; + logic clrresethaltreq; + logic ndmreset; + logic dmactive; + } dmcontrol_t; + + typedef struct packed { + logic [31:24] zero1; + logic [23:20] nscratch; + logic [19:17] zero0; + logic dataaccess; + logic [15:12] datasize; + logic [11:0] dataaddr; + } hartinfo_t; + + typedef enum logic [2:0] { + CmdErrNone, CmdErrBusy, CmdErrNotSupported, + CmdErrorException, CmdErrorHaltResume, + CmdErrorBus, CmdErrorOther = 7 + } cmderr_e; + + typedef struct packed { + logic [31:29] zero3; + logic [28:24] progbufsize; + logic [23:13] zero2; + logic busy; + logic zero1; + cmderr_e cmderr; + logic [7:4] zero0; + logic [3:0] datacount; + } abstractcs_t; + + typedef enum logic [7:0] { + AccessRegister = 8'h0, + QuickAccess = 8'h1, + AccessMemory = 8'h2 + } cmd_e; + + typedef struct packed { + cmd_e cmdtype; + logic [23:0] control; + } command_t; + + typedef struct packed { + logic [31:16] autoexecprogbuf; + logic [15:12] zero0; + logic [11:0] autoexecdata; + } abstractauto_t; + + typedef struct packed { + logic zero1; + logic [22:20] aarsize; + logic aarpostincrement; + logic postexec; + logic transfer; + logic write; + logic [15:0] regno; + } ac_ar_cmd_t; + + // DTM + typedef enum logic [1:0] { + DTM_NOP = 2'h0, + DTM_READ = 2'h1, + DTM_WRITE = 2'h2 + } dtm_op_e; + + typedef enum logic [1:0] { + DTM_SUCCESS = 2'h0, + DTM_ERR = 2'h2, + DTM_BUSY = 2'h3 + } dtm_op_status_e; + + typedef struct packed { + logic [31:29] sbversion; + logic [28:23] zero0; + logic sbbusyerror; + logic sbbusy; + logic sbreadonaddr; + logic [19:17] sbaccess; + logic sbautoincrement; + logic sbreadondata; + logic [14:12] sberror; + logic [11:5] sbasize; + logic sbaccess128; + logic sbaccess64; + logic sbaccess32; + logic sbaccess16; + logic sbaccess8; + } sbcs_t; + + typedef struct packed { + logic [31:0] addr; + dtm_op_e op; + logic [31:0] data; + } dmi_req_t; + + typedef struct packed { + logic [31:0] data; + logic [1:0] resp; + } dmi_resp_t; + + typedef struct packed { + logic [31:18] zero1; + logic dmihardreset; + logic dmireset; + logic zero0; + logic [14:12] idle; + logic [11:10] dmistat; + logic [9:4] abits; + logic [3:0] version; + } dtmcs_t; + + // privilege levels + typedef enum logic[1:0] { + PRIV_LVL_M = 2'b11, + PRIV_LVL_S = 2'b01, + PRIV_LVL_U = 2'b00 + } priv_lvl_t; + + // debugregs in core + typedef struct packed { + logic [31:28] xdebugver; + logic [27:16] zero2; + logic ebreakm; + logic zero1; + logic ebreaks; + logic ebreaku; + logic stepie; + logic stopcount; + logic stoptime; + logic [8:6] cause; + logic zero0; + logic mprven; + logic nmip; + logic step; + priv_lvl_t prv; + } dcsr_t; + + // CSRs + typedef enum logic [11:0] { + // Floating-Point CSRs + CSR_FFLAGS = 12'h001, + CSR_FRM = 12'h002, + CSR_FCSR = 12'h003, + CSR_FTRAN = 12'h800, + // Supervisor Mode CSRs + CSR_SSTATUS = 12'h100, + CSR_SIE = 12'h104, + CSR_STVEC = 12'h105, + CSR_SCOUNTEREN = 12'h106, + CSR_SSCRATCH = 12'h140, + CSR_SEPC = 12'h141, + CSR_SCAUSE = 12'h142, + CSR_STVAL = 12'h143, + CSR_SIP = 12'h144, + CSR_SATP = 12'h180, + // Machine Mode CSRs + CSR_MSTATUS = 12'h300, + CSR_MISA = 12'h301, + CSR_MEDELEG = 12'h302, + CSR_MIDELEG = 12'h303, + CSR_MIE = 12'h304, + CSR_MTVEC = 12'h305, + CSR_MCOUNTEREN = 12'h306, + CSR_MSCRATCH = 12'h340, + CSR_MEPC = 12'h341, + CSR_MCAUSE = 12'h342, + CSR_MTVAL = 12'h343, + CSR_MIP = 12'h344, + CSR_PMPCFG0 = 12'h3A0, + CSR_PMPADDR0 = 12'h3B0, + CSR_MVENDORID = 12'hF11, + CSR_MARCHID = 12'hF12, + CSR_MIMPID = 12'hF13, + CSR_MHARTID = 12'hF14, + CSR_MCYCLE = 12'hB00, + CSR_MINSTRET = 12'hB02, + CSR_DCACHE = 12'h701, + CSR_ICACHE = 12'h700, + + CSR_TSELECT = 12'h7A0, + CSR_TDATA1 = 12'h7A1, + CSR_TDATA2 = 12'h7A2, + CSR_TDATA3 = 12'h7A3, + CSR_TINFO = 12'h7A4, + + // Debug CSR + CSR_DCSR = 12'h7b0, + CSR_DPC = 12'h7b1, + CSR_DSCRATCH0 = 12'h7b2, // optional + CSR_DSCRATCH1 = 12'h7b3, // optional + + // Counters and Timers + CSR_CYCLE = 12'hC00, + CSR_TIME = 12'hC01, + CSR_INSTRET = 12'hC02 + } csr_reg_t; + + // SBA state + typedef enum logic [2:0] { + Idle, + Read, + Write, + WaitRead, + WaitWrite + } sba_state_e; + + // Instruction Generation Helpers + function automatic logic [31:0] jal (logic [4:0] rd, + logic [20:0] imm); + // OpCode Jal + return {imm[20], imm[10:1], imm[11], imm[19:12], rd, 7'h6f}; + endfunction + + function automatic logic [31:0] jalr (logic [4:0] rd, + logic [4:0] rs1, + logic [11:0] offset); + // OpCode Jal + return {offset[11:0], rs1, 3'b0, rd, 7'h67}; + endfunction + + function automatic logic [31:0] andi (logic [4:0] rd, + logic [4:0] rs1, + logic [11:0] imm); + // OpCode andi + return {imm[11:0], rs1, 3'h7, rd, 7'h13}; + endfunction + + function automatic logic [31:0] slli (logic [4:0] rd, + logic [4:0] rs1, + logic [5:0] shamt); + // OpCode slli + return {6'b0, shamt[5:0], rs1, 3'h1, rd, 7'h13}; + endfunction + + function automatic logic [31:0] srli (logic [4:0] rd, + logic [4:0] rs1, + logic [5:0] shamt); + // OpCode srli + return {6'b0, shamt[5:0], rs1, 3'h5, rd, 7'h13}; + endfunction + + function automatic logic [31:0] load (logic [2:0] size, + logic [4:0] dest, + logic [4:0] base, + logic [11:0] offset); + // OpCode Load + return {offset[11:0], base, size, dest, 7'h03}; + endfunction + + function automatic logic [31:0] auipc (logic [4:0] rd, + logic [20:0] imm); + // OpCode Auipc + return {imm[20], imm[10:1], imm[11], imm[19:12], rd, 7'h17}; + endfunction + + function automatic logic [31:0] store (logic [2:0] size, + logic [4:0] src, + logic [4:0] base, + logic [11:0] offset); + // OpCode Store + return {offset[11:5], src, base, size, offset[4:0], 7'h23}; + endfunction + + function automatic logic [31:0] float_load (logic [2:0] size, + logic [4:0] dest, + logic [4:0] base, + logic [11:0] offset); + // OpCode Load + return {offset[11:0], base, size, dest, 7'b00_001_11}; + endfunction + + function automatic logic [31:0] float_store (logic [2:0] size, + logic [4:0] src, + logic [4:0] base, + logic [11:0] offset); + // OpCode Store + return {offset[11:5], src, base, size, offset[4:0], 7'b01_001_11}; + endfunction + + function automatic logic [31:0] csrw (csr_reg_t csr, + logic [4:0] rs1); + // CSRRW, rd, OpCode System + return {csr, rs1, 3'h1, 5'h0, 7'h73}; + endfunction + + function automatic logic [31:0] csrr (csr_reg_t csr, + logic [4:0] dest); + // rs1, CSRRS, rd, OpCode System + return {csr, 5'h0, 3'h2, dest, 7'h73}; + endfunction + + function automatic logic [31:0] branch(logic [4:0] src2, + logic [4:0] src1, + logic [2:0] funct3, + logic [11:0] offset); + // OpCode Branch + return {offset[11], offset[9:4], src2, src1, funct3, + offset[3:0], offset[10], 7'b11_000_11}; + endfunction + + function automatic logic [31:0] ebreak (); + return 32'h00100073; + endfunction + + function automatic logic [31:0] wfi (); + return 32'h10500073; + endfunction + + function automatic logic [31:0] nop (); + return 32'h00000013; + endfunction + + function automatic logic [31:0] illegal (); + return 32'h00000000; + endfunction + +endpackage : dm diff --git a/src/dmi/rtl/dmi_cdc.sv b/src/dmi/rtl/dmi_cdc.sv new file mode 100644 index 0000000..e12794d --- /dev/null +++ b/src/dmi/rtl/dmi_cdc.sv @@ -0,0 +1,123 @@ +/* Copyright 2018 ETH Zurich and University of Bologna. +* Copyright and related rights are licensed under the Solderpad Hardware +* License, Version 0.51 (the “License”); you may not use this file except in +* compliance with the License. You may obtain a copy of the License at +* http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +* or agreed to in writing, software, hardware and materials distributed under +* this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR +* CONDITIONS OF ANY KIND, either express or implied. See the License for the +* specific language governing permissions and limitations under the License. +* +* File: axi_riscv_debug_module.sv +* Author: Andreas Traber +* Author: Florian Zaruba +* +* Description: Clock domain crossings for JTAG to DMI very heavily based +* on previous work by Andreas Traber for the PULP project. +* This is mainly a wrapper around the existing CDCs. +*/ +module dmi_cdc ( + // Test controls + input logic testmode_i, + input logic test_rst_ni, + + // JTAG side (master side) + input logic tck_i, + input logic trst_ni, + input dm::dmi_req_t jtag_dmi_req_i, + output logic jtag_dmi_ready_o, + input logic jtag_dmi_valid_i, + input logic jtag_dmi_cdc_clear_i, // Synchronous clear signal. + // Triggers reset sequencing + // accross CDC + + output dm::dmi_resp_t jtag_dmi_resp_o, + output logic jtag_dmi_valid_o, + input logic jtag_dmi_ready_i, + + // core side (slave side) + input logic clk_i, + input logic rst_ni, + + output logic core_dmi_rst_no, + output dm::dmi_req_t core_dmi_req_o, + output logic core_dmi_valid_o, + input logic core_dmi_ready_i, + + input dm::dmi_resp_t core_dmi_resp_i, + output logic core_dmi_ready_o, + input logic core_dmi_valid_i +); + + + logic jtag_combined_rstn; + always_ff @(posedge tck_i or negedge trst_ni) begin + if (!trst_ni) begin + jtag_combined_rstn <= '0; + end else if (jtag_dmi_cdc_clear_i) begin + jtag_combined_rstn <= '0; + end else begin + jtag_combined_rstn <= 1'b1; + end + end + + logic combined_rstn_premux; + caliptra_prim_flop_2sync #( + .Width(1), + .ResetValue(0) + ) u_combined_rstn_sync ( + .clk_i, + .rst_ni(rst_ni), + .d_i(jtag_combined_rstn), + .q_o(combined_rstn_premux) + ); + + logic combined_rstn; + caliptra_prim_clock_mux2 #( + .NoFpgaBufG(1'b1) + ) u_rst_mux ( + .clk0_i(combined_rstn_premux), + .clk1_i(test_rst_ni), + .sel_i(testmode_i), + .clk_o(combined_rstn) + ); + + caliptra_prim_fifo_async_simple #( + .Width($bits(dm::dmi_req_t)), + // Use the RZ protocol so that the two sides can be reset independently without getting + // out of sync due to EVEN/ODD states. + .EnRzHs(1) + ) i_cdc_req ( + .clk_wr_i (tck_i), + .rst_wr_ni(trst_ni), + .wvalid_i (jtag_dmi_valid_i), + .wready_o (jtag_dmi_ready_o), + .wdata_i (jtag_dmi_req_i), + .clk_rd_i (clk_i), + .rst_rd_ni(combined_rstn), + .rvalid_o (core_dmi_valid_o), + .rready_i (core_dmi_ready_i), + .rdata_o (core_dmi_req_o) + ); + + caliptra_prim_fifo_async_simple #( + .Width($bits(dm::dmi_resp_t)), + // Use the RZ protocol so that the two sides can be reset independently without getting + // out of sync due to EVEN/ODD states. + .EnRzHs(1) + ) i_cdc_resp ( + .clk_wr_i (clk_i), + .rst_wr_ni(combined_rstn), + .wvalid_i (core_dmi_valid_i), + .wready_o (core_dmi_ready_o), + .wdata_i (core_dmi_resp_i), + .clk_rd_i (tck_i), + .rst_rd_ni(trst_ni), + .rvalid_o (jtag_dmi_valid_o), + .rready_i (jtag_dmi_ready_i), + .rdata_o (jtag_dmi_resp_o) + ); + + assign core_dmi_rst_no = combined_rstn; + +endmodule : dmi_cdc diff --git a/src/dmi/rtl/dmi_jtag.sv b/src/dmi/rtl/dmi_jtag.sv new file mode 100644 index 0000000..b82bde1 --- /dev/null +++ b/src/dmi/rtl/dmi_jtag.sv @@ -0,0 +1,357 @@ +/* Copyright 2018 ETH Zurich and University of Bologna. +* Copyright and related rights are licensed under the Solderpad Hardware +* License, Version 0.51 (the “License”); you may not use this file except in +* compliance with the License. You may obtain a copy of the License at +* http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +* or agreed to in writing, software, hardware and materials distributed under +* this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR +* CONDITIONS OF ANY KIND, either express or implied. See the License for the +* specific language governing permissions and limitations under the License. +* +* File: axi_riscv_debug_module.sv +* Author: Florian Zaruba +* Date: 19.7.2018 +* +* Description: JTAG DMI (debug module interface) +* +*/ + +module dmi_jtag #( + parameter logic [31:0] IdcodeValue = 32'h00000DB3, + parameter int unsigned NumDmiWordAbits = 16 // Number of DMI address bits (7 - 32) +) ( + input logic clk_i, // DMI Clock + input logic rst_ni, // Asynchronous reset active low + input logic testmode_i, + input logic test_rst_ni, + + // active-low glitch free reset signal. Is asserted + // (clk_i) whenever the dmi_jtag is reset. + output logic dmi_rst_no, + output dm::dmi_req_t dmi_req_o, + output logic dmi_req_valid_o, + input logic dmi_req_ready_i, + + input dm::dmi_resp_t dmi_resp_i, + output logic dmi_resp_ready_o, + input logic dmi_resp_valid_i, + + input logic tck_i, // JTAG test clock pad + input logic tms_i, // JTAG test mode select pad + input logic trst_ni, // JTAG test reset pad + input logic td_i, // JTAG test data input pad + output logic td_o, // JTAG test data output pad + output logic tdo_oe_o // Data out output enable +); + + typedef enum logic [1:0] { + DMINoError = 2'h0, DMIReservedError = 2'h1, + DMIOPFailed = 2'h2, DMIBusy = 2'h3 + } dmi_error_e; + dmi_error_e error_d, error_q; + + logic tck; + logic jtag_dmi_clear; // Synchronous reset of DMI triggered by TestLogicReset in + // jtag TAP + logic dmi_clear; // Functional (warm) reset of the entire DMI + logic update; + logic capture; + logic shift; + logic tdi; + + logic dtmcs_select; + dm::dtmcs_t dtmcs_d, dtmcs_q; + + assign dmi_clear = jtag_dmi_clear || (dtmcs_select && update && dtmcs_q.dmihardreset); + + // ------------------------------- + // Debug Module Control and Status + // ------------------------------- + + always_comb begin + dtmcs_d = dtmcs_q; + if (capture) begin + if (dtmcs_select) begin + dtmcs_d = '{ + zero1 : '0, + dmihardreset : 1'b0, + dmireset : 1'b0, + zero0 : '0, + idle : 3'd1, // 1: Enter Run-Test/Idle and leave it immediately + dmistat : error_q, // 0: No error, 2: Op failed, 3: too fast + abits : 6'(NumDmiWordAbits), // The size of address in dmi + version : 4'd1 // Version described in spec version 0.13 (and later?) + }; + end + end + + if (shift) begin + if (dtmcs_select) dtmcs_d = {tdi, 31'(dtmcs_q >> 1)}; + end + end + + always_ff @(posedge tck or negedge trst_ni) begin + if (!trst_ni) begin + dtmcs_q <= '0; + end else begin + dtmcs_q <= dtmcs_d; + end + end + + // ---------------------------- + // DMI (Debug Module Interface) + // ---------------------------- + + logic dmi_select; + logic dmi_tdo; + + dm::dmi_req_t dmi_req; + logic dmi_req_ready; + logic dmi_req_valid; + + dm::dmi_resp_t dmi_resp; + logic dmi_resp_valid; + logic dmi_resp_ready; + + typedef struct packed { + logic [NumDmiWordAbits-1:0] address; + logic [31:0] data; + logic [1:0] op; + } dmi_t; + + typedef enum logic [2:0] { Idle, Read, WaitReadValid, Write, WaitWriteValid } state_e; + state_e state_d, state_q; + + logic [$bits(dmi_t)-1:0] dr_d, dr_q; + logic [NumDmiWordAbits-1:0] address_d, address_q; + logic [31:0] data_d, data_q; + + dmi_t dmi; + assign dmi = dmi_t'(dr_q); + assign dmi_req.addr = $bits(dmi_req.addr)'(address_q); + assign dmi_req.data = data_q; + assign dmi_req.op = (state_q == Write) ? dm::DTM_WRITE : dm::DTM_READ; + // We will always be ready to accept the data we requested. + assign dmi_resp_ready = 1'b1; + + logic error_dmi_busy; + logic error_dmi_op_failed; + + always_comb begin : p_fsm + error_dmi_busy = 1'b0; + error_dmi_op_failed = 1'b0; + // default assignments + state_d = state_q; + address_d = address_q; + data_d = data_q; + error_d = error_q; + + dmi_req_valid = 1'b0; + + if (dmi_clear) begin + state_d = Idle; + data_d = '0; + error_d = DMINoError; + address_d = '0; + end else begin + unique case (state_q) + Idle: begin + // make sure that no error is sticky + if (dmi_select && update && (error_q == DMINoError)) begin + // save address and value + address_d = dmi.address; + data_d = dmi.data; + if (dm::dtm_op_e'(dmi.op) == dm::DTM_READ) begin + state_d = Read; + end else if (dm::dtm_op_e'(dmi.op) == dm::DTM_WRITE) begin + state_d = Write; + end + // else this is a nop and we can stay here + end + end + + Read: begin + dmi_req_valid = 1'b1; + if (dmi_req_ready) begin + state_d = WaitReadValid; + end + end + + WaitReadValid: begin + // load data into register and shift out + if (dmi_resp_valid) begin + unique case (dmi_resp.resp) + dm::DTM_SUCCESS: begin + data_d = dmi_resp.data; + end + dm::DTM_ERR: begin + data_d = 32'hDEAD_BEEF; + error_dmi_op_failed = 1'b1; + end + dm::DTM_BUSY: begin + data_d = 32'hB051_B051; + error_dmi_busy = 1'b1; + end + default: begin + data_d = 32'hBAAD_C0DE; + end + endcase + state_d = Idle; + end + end + + Write: begin + dmi_req_valid = 1'b1; + // request sent, wait for response before going back to idle + if (dmi_req_ready) begin + state_d = WaitWriteValid; + end + end + + WaitWriteValid: begin + // got a valid answer go back to idle + if (dmi_resp_valid) begin + unique case (dmi_resp.resp) + dm::DTM_ERR: error_dmi_op_failed = 1'b1; + dm::DTM_BUSY: error_dmi_busy = 1'b1; + default: ; + endcase + state_d = Idle; + end + end + + default: begin + // just wait for idle here + if (dmi_resp_valid) begin + state_d = Idle; + end + end + endcase + + // update means we got another request but we didn't finish + // the one in progress, this state is sticky + if (update && state_q != Idle) begin + error_dmi_busy = 1'b1; + end + + // if capture goes high while we are in the read state + // or in the corresponding wait state we are not giving back a valid word + // -> throw an error + if (capture && state_q inside {Read, WaitReadValid}) begin + error_dmi_busy = 1'b1; + end + + if (error_dmi_busy && error_q == DMINoError) begin + error_d = DMIBusy; + end + + if (error_dmi_op_failed && error_q == DMINoError) begin + error_d = DMIOPFailed; + end + + // clear sticky error flag + if (update && dtmcs_q.dmireset && dtmcs_select) begin + error_d = DMINoError; + end + end + end + + // shift register + assign dmi_tdo = dr_q[0]; + + always_comb begin : p_shift + dr_d = dr_q; + if (dmi_clear) begin + dr_d = '0; + end else begin + if (capture) begin + if (dmi_select) begin + if (error_q == DMINoError && !error_dmi_busy) begin + dr_d = {address_q, data_q, DMINoError}; + // DMI was busy, report an error + end else if (error_q == DMIBusy || error_dmi_busy) begin + dr_d = {address_q, data_q, DMIBusy}; + end + end + end + + if (shift) begin + if (dmi_select) begin + dr_d = {tdi, dr_q[$bits(dr_q)-1:1]}; + end + end + end + end + + always_ff @(posedge tck or negedge trst_ni) begin + if (!trst_ni) begin + dr_q <= '0; + state_q <= Idle; + address_q <= '0; + data_q <= '0; + error_q <= DMINoError; + end else begin + dr_q <= dr_d; + state_q <= state_d; + address_q <= address_d; + data_q <= data_d; + error_q <= error_d; + end + end + + // --------- + // TAP + // --------- + dmi_jtag_tap #( + .IrLength (5), + .IdcodeValue(IdcodeValue) + ) i_dmi_jtag_tap ( + .tck_i, + .tms_i, + .trst_ni, + .td_i, + .td_o, + .tdo_oe_o, + .testmode_i, + .tck_o ( tck ), + .dmi_clear_o ( jtag_dmi_clear ), + .update_o ( update ), + .capture_o ( capture ), + .shift_o ( shift ), + .tdi_o ( tdi ), + .dtmcs_select_o ( dtmcs_select ), + .dtmcs_tdo_i ( dtmcs_q[0] ), + .dmi_select_o ( dmi_select ), + .dmi_tdo_i ( dmi_tdo ) + ); + + // --------- + // CDC + // --------- + dmi_cdc i_dmi_cdc ( + // Test controls + .testmode_i, + .test_rst_ni, + // JTAG side (master side) + .tck_i ( tck ), + .trst_ni ( trst_ni ), + .jtag_dmi_cdc_clear_i ( dmi_clear ), + .jtag_dmi_req_i ( dmi_req ), + .jtag_dmi_ready_o ( dmi_req_ready ), + .jtag_dmi_valid_i ( dmi_req_valid ), + .jtag_dmi_resp_o ( dmi_resp ), + .jtag_dmi_valid_o ( dmi_resp_valid ), + .jtag_dmi_ready_i ( dmi_resp_ready ), + // core side + .clk_i, + .rst_ni, + .core_dmi_rst_no ( dmi_rst_no ), + .core_dmi_req_o ( dmi_req_o ), + .core_dmi_valid_o ( dmi_req_valid_o ), + .core_dmi_ready_i ( dmi_req_ready_i ), + .core_dmi_resp_i ( dmi_resp_i ), + .core_dmi_ready_o ( dmi_resp_ready_o ), + .core_dmi_valid_i ( dmi_resp_valid_i ) + ); + +endmodule : dmi_jtag diff --git a/src/dmi/rtl/dmi_jtag_tap.sv b/src/dmi/rtl/dmi_jtag_tap.sv new file mode 100644 index 0000000..2638b81 --- /dev/null +++ b/src/dmi/rtl/dmi_jtag_tap.sv @@ -0,0 +1,323 @@ +/* Copyright 2018 ETH Zurich and University of Bologna. + * Copyright and related rights are licensed under the Solderpad Hardware + * License, Version 0.51 (the “License”); you may not use this file except in + * compliance with the License. You may obtain a copy of the License at + * http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law + * or agreed to in writing, software, hardware and materials distributed under + * this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR + * CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * File: dmi_jtag_tap.sv + * Author: Florian Zaruba + * Date: 19.7.2018 + * + * Description: JTAG TAP for DMI (according to debug spec 0.13) + * + */ + +module dmi_jtag_tap #( + parameter int unsigned IrLength = 5, + // JTAG IDCODE Value + parameter logic [31:0] IdcodeValue = 32'h00000001 + // xxxx version + // xxxxxxxxxxxxxxxx part number + // xxxxxxxxxxx manufacturer id + // 1 required by standard +) ( + input logic tck_i, // JTAG test clock pad + input logic tms_i, // JTAG test mode select pad + input logic trst_ni, // JTAG test reset pad + input logic td_i, // JTAG test data input pad + output logic td_o, // JTAG test data output pad + output logic tdo_oe_o, // Data out output enable + input logic testmode_i, + // JTAG is interested in writing the DTM CSR register + output logic tck_o, + // Synchronous reset of the dmi module triggered by JTAG TAP + output logic dmi_clear_o, + output logic update_o, + output logic capture_o, + output logic shift_o, + output logic tdi_o, + output logic dtmcs_select_o, + input logic dtmcs_tdo_i, + // we want to access DMI register + output logic dmi_select_o, + input logic dmi_tdo_i +); + + typedef enum logic [3:0] { + TestLogicReset, RunTestIdle, SelectDrScan, + CaptureDr, ShiftDr, Exit1Dr, PauseDr, Exit2Dr, + UpdateDr, SelectIrScan, CaptureIr, ShiftIr, + Exit1Ir, PauseIr, Exit2Ir, UpdateIr + } tap_state_e; + + tap_state_e tap_state_q, tap_state_d; + logic update_dr, shift_dr, capture_dr; + + typedef enum logic [IrLength-1:0] { + BYPASS0 = 'h0, + IDCODE = 'h1, + DTMCSR = 'h10, + DMIACCESS = 'h11, + BYPASS1 = 'h1f + } ir_reg_e; + + // ---------------- + // IR logic + // ---------------- + + // shift register + logic [IrLength-1:0] jtag_ir_shift_d, jtag_ir_shift_q; + // IR register -> this gets captured from shift register upon update_ir + ir_reg_e jtag_ir_d, jtag_ir_q; + logic capture_ir, shift_ir, update_ir, test_logic_reset; // pause_ir + + always_comb begin : p_jtag + jtag_ir_shift_d = jtag_ir_shift_q; + jtag_ir_d = jtag_ir_q; + + // IR shift register + if (shift_ir) begin + jtag_ir_shift_d = {td_i, jtag_ir_shift_q[IrLength-1:1]}; + end + + // capture IR register + if (capture_ir) begin + jtag_ir_shift_d = IrLength'(4'b0101); + end + + // update IR register + if (update_ir) begin + jtag_ir_d = ir_reg_e'(jtag_ir_shift_q); + end + + if (test_logic_reset) begin + // Bring all TAP state to the initial value. + jtag_ir_shift_d = '0; + jtag_ir_d = IDCODE; + end + end + + always_ff @(posedge tck_i, negedge trst_ni) begin : p_jtag_ir_reg + if (!trst_ni) begin + jtag_ir_shift_q <= '0; + jtag_ir_q <= IDCODE; + end else begin + jtag_ir_shift_q <= jtag_ir_shift_d; + jtag_ir_q <= jtag_ir_d; + end + end + + // ---------------- + // TAP DR Regs + // ---------------- + // - Bypass + // - IDCODE + // - DTM CS + logic [31:0] idcode_d, idcode_q; + logic idcode_select; + logic bypass_select; + + logic bypass_d, bypass_q; // this is a 1-bit register + + always_comb begin + idcode_d = idcode_q; + bypass_d = bypass_q; + + if (capture_dr) begin + if (idcode_select) idcode_d = IdcodeValue; + if (bypass_select) bypass_d = 1'b0; + end + + if (shift_dr) begin + if (idcode_select) idcode_d = {td_i, 31'(idcode_q >> 1)}; + if (bypass_select) bypass_d = td_i; + end + + if (test_logic_reset) begin + // Bring all TAP state to the initial value. + idcode_d = IdcodeValue; + bypass_d = 1'b0; + end + end + + // ---------------- + // Data reg select + // ---------------- + always_comb begin : p_data_reg_sel + dmi_select_o = 1'b0; + dtmcs_select_o = 1'b0; + idcode_select = 1'b0; + bypass_select = 1'b0; + unique case (jtag_ir_q) + BYPASS0: bypass_select = 1'b1; + IDCODE: idcode_select = 1'b1; + DTMCSR: dtmcs_select_o = 1'b1; + DMIACCESS: dmi_select_o = 1'b1; + BYPASS1: bypass_select = 1'b1; + default: bypass_select = 1'b1; + endcase + end + + // ---------------- + // Output select + // ---------------- + logic tdo_mux; + + always_comb begin : p_out_sel + // we are shifting out the IR register + if (shift_ir) begin + tdo_mux = jtag_ir_shift_q[0]; + // here we are shifting the DR register + end else begin + unique case (jtag_ir_q) + IDCODE: tdo_mux = idcode_q[0]; // Reading ID code + DTMCSR: tdo_mux = dtmcs_tdo_i; // Read from DTMCS TDO + DMIACCESS: tdo_mux = dmi_tdo_i; // Read from DMI TDO + default: tdo_mux = bypass_q; // BYPASS instruction + endcase + end + end + + // ---------------- + // DFT + // ---------------- + logic tck_n; + + caliptra_prim_clock_inv #( + .HasScanMode(1'b1), + .NoFpgaBufG(1'b1) + ) i_tck_inv ( + .clk_i ( tck_i ), + .clk_no ( tck_n ), + .scanmode_i ( testmode_i ) + ); + + // TDO changes state at negative edge of TCK + always_ff @(posedge tck_n, negedge trst_ni) begin : p_tdo_regs + if (!trst_ni) begin + td_o <= 1'b0; + tdo_oe_o <= 1'b0; + end else begin + td_o <= tdo_mux; + tdo_oe_o <= (shift_ir | shift_dr); + end + end + // ---------------- + // TAP FSM + // ---------------- + // Determination of next state; purely combinatorial + always_comb begin : p_tap_fsm + + test_logic_reset = 1'b0; + + capture_dr = 1'b0; + shift_dr = 1'b0; + update_dr = 1'b0; + + capture_ir = 1'b0; + shift_ir = 1'b0; + // pause_ir = 1'b0; unused + update_ir = 1'b0; + + unique case (tap_state_q) + TestLogicReset: begin + tap_state_d = (tms_i) ? TestLogicReset : RunTestIdle; + test_logic_reset = 1'b1; + end + RunTestIdle: begin + tap_state_d = (tms_i) ? SelectDrScan : RunTestIdle; + end + // DR Path + SelectDrScan: begin + tap_state_d = (tms_i) ? SelectIrScan : CaptureDr; + end + CaptureDr: begin + capture_dr = 1'b1; + tap_state_d = (tms_i) ? Exit1Dr : ShiftDr; + end + ShiftDr: begin + shift_dr = 1'b1; + tap_state_d = (tms_i) ? Exit1Dr : ShiftDr; + end + Exit1Dr: begin + tap_state_d = (tms_i) ? UpdateDr : PauseDr; + end + PauseDr: begin + tap_state_d = (tms_i) ? Exit2Dr : PauseDr; + end + Exit2Dr: begin + tap_state_d = (tms_i) ? UpdateDr : ShiftDr; + end + UpdateDr: begin + update_dr = 1'b1; + tap_state_d = (tms_i) ? SelectDrScan : RunTestIdle; + end + // IR Path + SelectIrScan: begin + tap_state_d = (tms_i) ? TestLogicReset : CaptureIr; + end + // In this controller state, the shift register bank in the + // Instruction Register parallel loads a pattern of fixed values on + // the rising edge of TCK. The last two significant bits must always + // be "01". + CaptureIr: begin + capture_ir = 1'b1; + tap_state_d = (tms_i) ? Exit1Ir : ShiftIr; + end + // In this controller state, the instruction register gets connected + // between TDI and TDO, and the captured pattern gets shifted on + // each rising edge of TCK. The instruction available on the TDI + // pin is also shifted in to the instruction register. + ShiftIr: begin + shift_ir = 1'b1; + tap_state_d = (tms_i) ? Exit1Ir : ShiftIr; + end + Exit1Ir: begin + tap_state_d = (tms_i) ? UpdateIr : PauseIr; + end + PauseIr: begin + // pause_ir = 1'b1; // unused + tap_state_d = (tms_i) ? Exit2Ir : PauseIr; + end + Exit2Ir: begin + tap_state_d = (tms_i) ? UpdateIr : ShiftIr; + end + // In this controller state, the instruction in the instruction + // shift register is latched to the latch bank of the Instruction + // Register on every falling edge of TCK. This instruction becomes + // the current instruction once it is latched. + UpdateIr: begin + update_ir = 1'b1; + tap_state_d = (tms_i) ? SelectDrScan : RunTestIdle; + end + default: ; // can't actually happen since case is full + endcase + end + + always_ff @(posedge tck_i or negedge trst_ni) begin : p_regs + if (!trst_ni) begin + tap_state_q <= TestLogicReset; + idcode_q <= IdcodeValue; + bypass_q <= 1'b0; + end else begin + tap_state_q <= tap_state_d; + idcode_q <= idcode_d; + bypass_q <= bypass_d; + end + end + + // Pass through JTAG signals to debug custom DR logic. + // In case of a single TAP those are just feed-through. + assign tck_o = tck_i; + assign tdi_o = td_i; + assign update_o = update_dr; + assign shift_o = shift_dr; + assign capture_o = capture_dr; + assign dmi_clear_o = test_logic_reset; + + +endmodule : dmi_jtag_tap diff --git a/src/fuse_ctrl/config/compile.yml b/src/fuse_ctrl/config/compile.yml new file mode 100644 index 0000000..718b21a --- /dev/null +++ b/src/fuse_ctrl/config/compile.yml @@ -0,0 +1,79 @@ +--- +provides: [fuse_ctrl_pkg] +schema_version: 2.4.0 +requires: + - caliptra_prim +targets: + rtl: + directories: [$COMPILE_ROOT/rtl] + files: + - $COMPILE_ROOT/rtl/otp_ctrl_reg_pkg.sv + - $COMPILE_ROOT/rtl/otp_ctrl_pkg.sv + - $COMPILE_ROOT/rtl/otp_ctrl_part_pkg.sv + tb: + directories: [$COMPILE_ROOT/rtl] + files: + - $COMPILE_ROOT/rtl/otp_ctrl_reg_pkg.sv + - $COMPILE_ROOT/rtl/otp_ctrl_pkg.sv + - $COMPILE_ROOT/rtl/otp_ctrl_part_pkg.sv +--- +provides: [fuse_ctrl] +schema_version: 2.4.0 +requires: + - axi2tlul + - tlul + - ast_pkg + - caliptra_prim + - caliptra_prim_generic + - edn_pkg + - pwrmgr_pkg + # - caliptra_ss_lc_ctrl_pkg + - fuse_ctrl_pkg +targets: + rtl: + directories: [$COMPILE_ROOT/rtl] + files: + - $COMPILE_ROOT/rtl/otp_ctrl_core_reg_top.sv + - $COMPILE_ROOT/rtl/otp_ctrl_prim_reg_top.sv + - $COMPILE_ROOT/rtl/otp_ctrl_dai.sv + - $COMPILE_ROOT/rtl/otp_ctrl_ecc_reg.sv + - $COMPILE_ROOT/rtl/otp_ctrl_kdi.sv + - $COMPILE_ROOT/rtl/otp_ctrl_lci.sv + - $COMPILE_ROOT/rtl/otp_ctrl_lfsr_timer.sv + - $COMPILE_ROOT/rtl/otp_ctrl_part_buf.sv + - $COMPILE_ROOT/rtl/otp_ctrl_part_unbuf.sv + - $COMPILE_ROOT/rtl/otp_ctrl_scrmbl.sv + - $COMPILE_ROOT/rtl/otp_ctrl_token_const.sv + - $COMPILE_ROOT/rtl/prim_generic_otp.sv + - $COMPILE_ROOT/rtl/otp_ctrl.sv + #- $COMPILE_ROOT/rtl/otp_ctrl_top.sv + tops: [otp_ctrl] +#--- +#provides: [fuse_ctrl_tb_pkg] +#schema_version: 2.4.0 +#requires: +#targets: +# tb: +# directories: [$COMPILE_ROOT/tb] +# files: +# - $COMPILE_ROOT/tb/otp_ctrl_top_tb_pkg.sv +# tops: [otp_ctrl_top_tb_pkg] +#--- +#provides: [fuse_ctrl_tb] +#schema_version: 2.4.0 +#requires: +# - fuse_ctrl +# - fuse_ctrl_tb_pkg +#targets: +# tb: +# directories: [$COMPILE_ROOT/tb] +# files: +# - $COMPILE_ROOT/tb/otp_ctrl_top_tb.sv +# tops: [otp_ctrl_top_tb] +#global: +# tool: +# vcs: +# default: +# - '-assert svaext' +# - +define+CLP_ASSERT_ON +# - '-noinherit_timescale=1ns/1ps' diff --git a/src/fuse_ctrl/data/dif_otp_ctrl.c.tpl b/src/fuse_ctrl/data/dif_otp_ctrl.c.tpl new file mode 100755 index 0000000..12882f1 --- /dev/null +++ b/src/fuse_ctrl/data/dif_otp_ctrl.c.tpl @@ -0,0 +1,734 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +${gen_comment} +<% +from topgen.lib import Name + +parts = otp_mmap.config["partitions"] +digest_parts = [part for part in parts if + part["hw_digest"] or part["sw_digest"]] +read_locked_csr_parts = [part for part in parts if part["read_lock"] == "CSR"] +secret_parts = [part for part in parts if part["secret"]] +%>\ +#include "sw/device/lib/dif/dif_otp_ctrl.h" + +#include + +#include "sw/device/lib/base/bitfield.h" +#include "sw/device/lib/base/macros.h" +#include "sw/device/lib/dif/dif_base.h" + +#include "otp_ctrl_regs.h" // Generated. + +/** + * Checks if integrity/consistency-check-related operations are locked. + * + * This is a convenience function to avoid superfluous error-checking in all the + * functions that can be locked out by this register. + * + * @param check_config True to check the config regwen. False to check the + * trigger regwen. + */ +static bool checks_are_locked(const dif_otp_ctrl_t *otp, bool check_config) { + ptrdiff_t reg_offset = check_config + ? OTP_CTRL_CHECK_REGWEN_REG_OFFSET + : OTP_CTRL_CHECK_TRIGGER_REGWEN_REG_OFFSET; + size_t regwen_bit = + check_config ? OTP_CTRL_CHECK_REGWEN_CHECK_REGWEN_BIT + : OTP_CTRL_CHECK_TRIGGER_REGWEN_CHECK_TRIGGER_REGWEN_BIT; + uint32_t locked = mmio_region_read32(otp->base_addr, reg_offset); + return !bitfield_bit32_read(locked, regwen_bit); +} + +dif_result_t dif_otp_ctrl_configure(const dif_otp_ctrl_t *otp, + dif_otp_ctrl_config_t config) { + if (otp == NULL) { + return kDifBadArg; + } + if (checks_are_locked(otp, /*check_config=*/true)) { + return kDifLocked; + } + + mmio_region_write32(otp->base_addr, OTP_CTRL_CHECK_TIMEOUT_REG_OFFSET, + config.check_timeout); + mmio_region_write32(otp->base_addr, + OTP_CTRL_INTEGRITY_CHECK_PERIOD_REG_OFFSET, + config.integrity_period_mask); + mmio_region_write32(otp->base_addr, + OTP_CTRL_CONSISTENCY_CHECK_PERIOD_REG_OFFSET, + config.consistency_period_mask); + + return kDifOk; +} + +dif_result_t dif_otp_ctrl_check_integrity(const dif_otp_ctrl_t *otp) { + if (otp == NULL) { + return kDifBadArg; + } + if (checks_are_locked(otp, /*check_config=*/false)) { + return kDifLocked; + } + + uint32_t reg = + bitfield_bit32_write(0, OTP_CTRL_CHECK_TRIGGER_INTEGRITY_BIT, true); + mmio_region_write32(otp->base_addr, OTP_CTRL_CHECK_TRIGGER_REG_OFFSET, reg); + + return kDifOk; +} + +dif_result_t dif_otp_ctrl_check_consistency(const dif_otp_ctrl_t *otp) { + if (otp == NULL) { + return kDifBadArg; + } + if (checks_are_locked(otp, /*check_config=*/false)) { + return kDifLocked; + } + + uint32_t reg = + bitfield_bit32_write(0, OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_BIT, true); + mmio_region_write32(otp->base_addr, OTP_CTRL_CHECK_TRIGGER_REG_OFFSET, reg); + + return kDifOk; +} + +dif_result_t dif_otp_ctrl_lock_dai(const dif_otp_ctrl_t *otp) { + if (otp == NULL) { + return kDifBadArg; + } + + uint32_t reg = bitfield_bit32_write( + 0, OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_BIT, false); + mmio_region_write32(otp->base_addr, OTP_CTRL_DIRECT_ACCESS_REGWEN_REG_OFFSET, + reg); + + return kDifOk; +} + +dif_result_t dif_otp_ctrl_dai_is_locked(const dif_otp_ctrl_t *otp, + bool *is_locked) { + if (otp == NULL || is_locked == NULL) { + return kDifBadArg; + } + + uint32_t reg = mmio_region_read32(otp->base_addr, + OTP_CTRL_DIRECT_ACCESS_REGWEN_REG_OFFSET); + *is_locked = !bitfield_bit32_read( + reg, OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_BIT); + + return kDifOk; +} + +dif_result_t dif_otp_ctrl_lock_config(const dif_otp_ctrl_t *otp) { + if (otp == NULL) { + return kDifBadArg; + } + + uint32_t reg = + bitfield_bit32_write(0, OTP_CTRL_CHECK_REGWEN_CHECK_REGWEN_BIT, false); + mmio_region_write32(otp->base_addr, OTP_CTRL_CHECK_REGWEN_REG_OFFSET, reg); + + return kDifOk; +} + +dif_result_t dif_otp_ctrl_config_is_locked(const dif_otp_ctrl_t *otp, + bool *is_locked) { + if (otp == NULL || is_locked == NULL) { + return kDifBadArg; + } + + *is_locked = checks_are_locked(otp, /*check_config=*/true); + return kDifOk; +} + +dif_result_t dif_otp_ctrl_lock_check_trigger(const dif_otp_ctrl_t *otp) { + if (otp == NULL) { + return kDifBadArg; + } + + uint32_t reg = bitfield_bit32_write( + 0, OTP_CTRL_CHECK_TRIGGER_REGWEN_CHECK_TRIGGER_REGWEN_BIT, false); + mmio_region_write32(otp->base_addr, OTP_CTRL_CHECK_TRIGGER_REGWEN_REG_OFFSET, + reg); + + return kDifOk; +} + +dif_result_t dif_otp_ctrl_check_trigger_is_locked(const dif_otp_ctrl_t *otp, + bool *is_locked) { + if (otp == NULL || is_locked == NULL) { + return kDifBadArg; + } + + *is_locked = checks_are_locked(otp, /*check_config=*/false); + return kDifOk; +} + +static bool sw_read_lock_reg_offset(dif_otp_ctrl_partition_t partition, + ptrdiff_t *reg_offset, + bitfield_bit32_index_t *index) { + switch (partition) { +% for part in read_locked_csr_parts: +<% + part_name = Name.from_snake_case(part["name"]) + part_name_define = part_name.as_c_define() + index_line = f"*index = OTP_CTRL_{part_name_define}_READ_LOCK_{part_name_define}_READ_LOCK_BIT;" +%>\ + case kDifOtpCtrlPartition${part_name.as_camel_case()}: + *reg_offset = OTP_CTRL_${part_name_define}_READ_LOCK_REG_OFFSET; + % if len(index_line) > 80 - 6: + *index = + OTP_CTRL_${part_name_define}_READ_LOCK_${part_name_define}_READ_LOCK_BIT; + % else: + ${index_line} + % endif + break; +% endfor + default: + return false; + } + return true; +} + +dif_result_t dif_otp_ctrl_lock_reading(const dif_otp_ctrl_t *otp, + dif_otp_ctrl_partition_t partition) { + if (otp == NULL) { + return kDifBadArg; + } + + ptrdiff_t offset; + bitfield_bit32_index_t index; + if (!sw_read_lock_reg_offset(partition, &offset, &index)) { + return kDifBadArg; + } + + uint32_t busy = mmio_region_read32(otp->base_addr, + OTP_CTRL_DIRECT_ACCESS_REGWEN_REG_OFFSET); + if (!bitfield_bit32_read( + busy, OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_BIT)) { + return kDifUnavailable; + } + + uint32_t reg = bitfield_bit32_write(0, index, false); + mmio_region_write32(otp->base_addr, offset, reg); + + return kDifOk; +} + +dif_result_t dif_otp_ctrl_reading_is_locked(const dif_otp_ctrl_t *otp, + dif_otp_ctrl_partition_t partition, + bool *is_locked) { + if (otp == NULL || is_locked == NULL) { + return kDifBadArg; + } + + ptrdiff_t offset; + bitfield_bit32_index_t index; + if (!sw_read_lock_reg_offset(partition, &offset, &index)) { + return kDifBadArg; + } + + uint32_t reg = mmio_region_read32(otp->base_addr, offset); + *is_locked = !bitfield_bit32_read(reg, index); + return kDifOk; +} + +dif_result_t dif_otp_ctrl_get_status(const dif_otp_ctrl_t *otp, + dif_otp_ctrl_status_t *status) { + if (otp == NULL || status == NULL) { + return kDifBadArg; + } + + static const bitfield_bit32_index_t kIndices[] = { +% for part in parts: +<% + part_name = Name.from_snake_case(part["name"]) + lhs = f'[kDifOtpCtrlStatusCode{part_name.as_camel_case()}Error]' + rhs = f'OTP_CTRL_STATUS_{part_name.as_c_define()}_ERROR_BIT' + line = f'{lhs} = {rhs},' +%>\ + % if len(line) > 80 - 6: + ${lhs} = + ${rhs}, + % else: + ${line} + % endif +% endfor + [kDifOtpCtrlStatusCodeDaiError] = OTP_CTRL_STATUS_DAI_ERROR_BIT, + [kDifOtpCtrlStatusCodeLciError] = OTP_CTRL_STATUS_LCI_ERROR_BIT, + [kDifOtpCtrlStatusCodeTimeoutError] = OTP_CTRL_STATUS_TIMEOUT_ERROR_BIT, + [kDifOtpCtrlStatusCodeLfsrError] = OTP_CTRL_STATUS_LFSR_FSM_ERROR_BIT, + [kDifOtpCtrlStatusCodeScramblingError] = + OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_BIT, + [kDifOtpCtrlStatusCodeKdfError] = OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_BIT, + [kDifOtpCtrlStatusCodeBusIntegError] = + OTP_CTRL_STATUS_BUS_INTEG_ERROR_BIT, + [kDifOtpCtrlStatusCodeDaiIdle] = OTP_CTRL_STATUS_DAI_IDLE_BIT, + [kDifOtpCtrlStatusCodeCheckPending] = OTP_CTRL_STATUS_CHECK_PENDING_BIT, + }; + + status->codes = 0; + uint32_t status_code = + mmio_region_read32(otp->base_addr, OTP_CTRL_STATUS_REG_OFFSET); + for (int i = 0; i < ARRAYSIZE(kIndices); ++i) { + // If the error is not present at all, we clear its cause bit if relevant, + // and bail immediately. + if (!bitfield_bit32_read(status_code, kIndices[i])) { + if (i <= kDifOtpCtrlStatusCodeHasCauseLast) { + status->causes[i] = kDifOtpCtrlErrorOk; + } + continue; + } + + status->codes = + bitfield_bit32_write(status->codes, (bitfield_bit32_index_t)i, true); + + if (i <= kDifOtpCtrlStatusCodeHasCauseLast) { + bitfield_field32_t field; + field = (bitfield_field32_t){ + .mask = OTP_CTRL_ERR_CODE_0_ERR_CODE_0_MASK, + .index = OTP_CTRL_ERR_CODE_0_ERR_CODE_0_OFFSET, + }; + + ptrdiff_t address = + OTP_CTRL_ERR_CODE_0_REG_OFFSET + i * (ptrdiff_t)sizeof(uint32_t); + uint32_t error_code = mmio_region_read32(otp->base_addr, address); + + dif_otp_ctrl_error_t err; + switch (bitfield_field32_read(error_code, field)) { + case OTP_CTRL_ERR_CODE_0_ERR_CODE_0_VALUE_NO_ERROR: + err = kDifOtpCtrlErrorOk; + break; + case OTP_CTRL_ERR_CODE_0_ERR_CODE_0_VALUE_MACRO_ERROR: + err = kDifOtpCtrlErrorMacroUnspecified; + break; + case OTP_CTRL_ERR_CODE_0_ERR_CODE_0_VALUE_MACRO_ECC_CORR_ERROR: + err = kDifOtpCtrlErrorMacroRecoverableRead; + break; + case OTP_CTRL_ERR_CODE_0_ERR_CODE_0_VALUE_MACRO_ECC_UNCORR_ERROR: + err = kDifOtpCtrlErrorMacroUnrecoverableRead; + break; + case OTP_CTRL_ERR_CODE_0_ERR_CODE_0_VALUE_MACRO_WRITE_BLANK_ERROR: + err = kDifOtpCtrlErrorMacroBlankCheckFailed; + break; + case OTP_CTRL_ERR_CODE_0_ERR_CODE_0_VALUE_ACCESS_ERROR: + err = kDifOtpCtrlErrorLockedAccess; + break; + case OTP_CTRL_ERR_CODE_0_ERR_CODE_0_VALUE_CHECK_FAIL_ERROR: + err = kDifOtpCtrlErrorBackgroundCheckFailed; + break; + case OTP_CTRL_ERR_CODE_0_ERR_CODE_0_VALUE_FSM_STATE_ERROR: + err = kDifOtpCtrlErrorFsmBadState; + break; + default: + return kDifError; + } + status->causes[i] = err; + } + } + + return kDifOk; +} + +typedef struct partition_info { + /** + * The absolute OTP address at which this partition starts. + */ + uint32_t start_addr; + /** + * The length of this partition, in bytes, including the digest. + * + * If the partition has a digest, it is expected to be at address + * `start_addr + len - sizeof(uint64_t)`. + */ + uint32_t len; + /** + * The alignment mask for this partition. + * + * A valid address for this partition must be such that + * `addr & align_mask == 0`. + */ + uint32_t align_mask; + + /** + * Whether this is a software-managed partition with a software-managed + * digest. + */ + bool is_software; + + /** + * Whether this partition has a digest field. + */ + bool has_digest; + + /** + * Whether this partition is the lifecycle partition. + */ + bool is_lifecycle; +} partition_info_t; + +// This is generates too many lines with different formatting variants, so +// We opt to just disable formatting. +// clang-format off +static const partition_info_t kPartitions[] = { +% for part in parts: +<% + part_name = Name.from_snake_case(part["name"]) + part_name_camel = part_name.as_camel_case() + part_name_define = part_name.as_c_define() + has_digest = part["hw_digest"] or part["sw_digest"] + is_lifecycle = part["variant"] == "LifeCycle" + is_software = part["variant"] == "Unbuffered" +%>\ + [kDifOtpCtrlPartition${part_name_camel}] = { + .start_addr = OTP_CTRL_PARAM_${part_name_define}_OFFSET, + .len = OTP_CTRL_PARAM_${part_name_define}_SIZE, + .align_mask = ${"0x7" if part in secret_parts else "0x3"}, + .is_software = ${"true" if is_software else "false"}, + .has_digest = ${"true" if has_digest else "false"}, + .is_lifecycle = ${"true" if is_lifecycle else "false"}}, +% endfor +}; +// clang-format on + +dif_result_t dif_otp_ctrl_relative_address(dif_otp_ctrl_partition_t partition, + uint32_t abs_address, + uint32_t *relative_address) { + *relative_address = 0; + + if (partition >= ARRAYSIZE(kPartitions)) { + return kDifBadArg; + } + + if ((abs_address & kPartitions[partition].align_mask) != 0) { + return kDifUnaligned; + } + + if (abs_address < kPartitions[partition].start_addr) { + return kDifOutOfRange; + } + + *relative_address = abs_address - kPartitions[partition].start_addr; + if (*relative_address >= kPartitions[partition].len) { + *relative_address = 0; + return kDifOutOfRange; + } + + return kDifOk; +} + +dif_result_t dif_otp_ctrl_dai_read_start(const dif_otp_ctrl_t *otp, + dif_otp_ctrl_partition_t partition, + uint32_t address) { + if (otp == NULL || partition >= ARRAYSIZE(kPartitions)) { + return kDifBadArg; + } + + if ((address & kPartitions[partition].align_mask) != 0) { + return kDifUnaligned; + } + + if (address >= kPartitions[partition].len) { + return kDifOutOfRange; + } + + uint32_t busy = mmio_region_read32(otp->base_addr, + OTP_CTRL_DIRECT_ACCESS_REGWEN_REG_OFFSET); + if (!bitfield_bit32_read( + busy, OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_BIT)) { + return kDifUnavailable; + } + + address += kPartitions[partition].start_addr; + mmio_region_write32(otp->base_addr, OTP_CTRL_DIRECT_ACCESS_ADDRESS_REG_OFFSET, + address); + + uint32_t cmd = + bitfield_bit32_write(0, OTP_CTRL_DIRECT_ACCESS_CMD_RD_BIT, true); + mmio_region_write32(otp->base_addr, OTP_CTRL_DIRECT_ACCESS_CMD_REG_OFFSET, + cmd); + + return kDifOk; +} + +dif_result_t dif_otp_ctrl_dai_read32_end(const dif_otp_ctrl_t *otp, + uint32_t *value) { + if (otp == NULL || value == NULL) { + return kDifBadArg; + } + + uint32_t busy = mmio_region_read32(otp->base_addr, + OTP_CTRL_DIRECT_ACCESS_REGWEN_REG_OFFSET); + if (!bitfield_bit32_read( + busy, OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_BIT)) { + return kDifUnavailable; + } + + *value = mmio_region_read32(otp->base_addr, + OTP_CTRL_DIRECT_ACCESS_RDATA_0_REG_OFFSET); + return kDifOk; +} + +dif_result_t dif_otp_ctrl_dai_read64_end(const dif_otp_ctrl_t *otp, + uint64_t *value) { + if (otp == NULL || value == NULL) { + return kDifBadArg; + } + + uint32_t busy = mmio_region_read32(otp->base_addr, + OTP_CTRL_DIRECT_ACCESS_REGWEN_REG_OFFSET); + if (!bitfield_bit32_read( + busy, OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_BIT)) { + return kDifUnavailable; + } + + *value = mmio_region_read32(otp->base_addr, + OTP_CTRL_DIRECT_ACCESS_RDATA_1_REG_OFFSET); + *value <<= 32; + *value |= mmio_region_read32(otp->base_addr, + OTP_CTRL_DIRECT_ACCESS_RDATA_0_REG_OFFSET); + return kDifOk; +} + +dif_result_t dif_otp_ctrl_dai_program32(const dif_otp_ctrl_t *otp, + dif_otp_ctrl_partition_t partition, + uint32_t address, uint32_t value) { + if (otp == NULL || partition >= ARRAYSIZE(kPartitions)) { + return kDifBadArg; + } + + // Ensure that we are writing to a 32-bit-access partition by checking that + // the alignment mask is 0b11. + // + // Note furthermore that the LC partition is *not* writeable, so we eject + // here. + if (kPartitions[partition].align_mask != 0x3 || + kPartitions[partition].is_lifecycle) { + return kDifError; + } + + if ((address & kPartitions[partition].align_mask) != 0) { + return kDifUnaligned; + } + + // NOTE: The bounds check is tightened here, since we disallow writing the + // digest directly. If the partition does not have a digest, no tightening is + // needed. + size_t digest_size = kPartitions[partition].has_digest * sizeof(uint64_t); + if (address >= kPartitions[partition].len - digest_size) { + return kDifOutOfRange; + } + + uint32_t busy = mmio_region_read32(otp->base_addr, + OTP_CTRL_DIRECT_ACCESS_REGWEN_REG_OFFSET); + if (!bitfield_bit32_read( + busy, OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_BIT)) { + return kDifUnavailable; + } + + address += kPartitions[partition].start_addr; + mmio_region_write32(otp->base_addr, OTP_CTRL_DIRECT_ACCESS_ADDRESS_REG_OFFSET, + address); + + mmio_region_write32(otp->base_addr, OTP_CTRL_DIRECT_ACCESS_WDATA_0_REG_OFFSET, + value); + + uint32_t cmd = + bitfield_bit32_write(0, OTP_CTRL_DIRECT_ACCESS_CMD_WR_BIT, true); + mmio_region_write32(otp->base_addr, OTP_CTRL_DIRECT_ACCESS_CMD_REG_OFFSET, + cmd); + + return kDifOk; +} + +dif_result_t dif_otp_ctrl_dai_program64(const dif_otp_ctrl_t *otp, + dif_otp_ctrl_partition_t partition, + uint32_t address, uint64_t value) { + if (otp == NULL || partition >= ARRAYSIZE(kPartitions)) { + return kDifBadArg; + } + + // Ensure that we are writing to a 64-bit-access partition by checking that + // the alignment mask is 0b111. + if (kPartitions[partition].align_mask != 0x7) { + return kDifError; + } + + if ((address & kPartitions[partition].align_mask) != 0) { + return kDifUnaligned; + } + + // NOTE: The bounds check is tightened here, since we disallow writing the + // digest directly. + size_t digest_size = sizeof(uint64_t); + if (address >= kPartitions[partition].len - digest_size) { + return kDifOutOfRange; + } + + uint32_t busy = mmio_region_read32(otp->base_addr, + OTP_CTRL_DIRECT_ACCESS_REGWEN_REG_OFFSET); + if (!bitfield_bit32_read( + busy, OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_BIT)) { + return kDifUnavailable; + } + + address += kPartitions[partition].start_addr; + mmio_region_write32(otp->base_addr, OTP_CTRL_DIRECT_ACCESS_ADDRESS_REG_OFFSET, + address); + + mmio_region_write32(otp->base_addr, OTP_CTRL_DIRECT_ACCESS_WDATA_0_REG_OFFSET, + value & UINT32_MAX); + mmio_region_write32(otp->base_addr, OTP_CTRL_DIRECT_ACCESS_WDATA_1_REG_OFFSET, + value >> 32); + + uint32_t cmd = + bitfield_bit32_write(0, OTP_CTRL_DIRECT_ACCESS_CMD_WR_BIT, true); + mmio_region_write32(otp->base_addr, OTP_CTRL_DIRECT_ACCESS_CMD_REG_OFFSET, + cmd); + + return kDifOk; +} + +dif_result_t dif_otp_ctrl_dai_digest(const dif_otp_ctrl_t *otp, + dif_otp_ctrl_partition_t partition, + uint64_t digest) { + if (otp == NULL || partition >= ARRAYSIZE(kPartitions)) { + return kDifBadArg; + } + + // Not all partitions have a digest. + if (!kPartitions[partition].has_digest) { + return kDifError; + } + + // For software partitions, the digest must be nonzero; for all other + // partitions it must be zero. + bool is_sw = kPartitions[partition].is_software; + if (is_sw == (digest == 0)) { + return kDifBadArg; + } + + uint32_t busy = mmio_region_read32(otp->base_addr, + OTP_CTRL_DIRECT_ACCESS_REGWEN_REG_OFFSET); + if (!bitfield_bit32_read( + busy, OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_BIT)) { + return kDifUnavailable; + } + + uint32_t address = kPartitions[partition].start_addr; + if (is_sw) { + address += kPartitions[partition].len - sizeof(digest); + } + mmio_region_write32(otp->base_addr, OTP_CTRL_DIRECT_ACCESS_ADDRESS_REG_OFFSET, + address); + + if (digest != 0) { + mmio_region_write32(otp->base_addr, + OTP_CTRL_DIRECT_ACCESS_WDATA_0_REG_OFFSET, + digest & 0xffffffff); + mmio_region_write32(otp->base_addr, + OTP_CTRL_DIRECT_ACCESS_WDATA_1_REG_OFFSET, + digest >> 32); + } + + bitfield_bit32_index_t cmd_bit = is_sw + ? OTP_CTRL_DIRECT_ACCESS_CMD_WR_BIT + : OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_BIT; + uint32_t cmd = bitfield_bit32_write(0, cmd_bit, true); + mmio_region_write32(otp->base_addr, OTP_CTRL_DIRECT_ACCESS_CMD_REG_OFFSET, + cmd); + + return kDifOk; +} + +static bool get_digest_regs(dif_otp_ctrl_partition_t partition, ptrdiff_t *reg0, + ptrdiff_t *reg1) { + switch (partition) { +% for part in digest_parts: +<% + part_name = Name.from_snake_case(part["name"]) + part_name_define = part_name.as_c_define() +%>\ + case kDifOtpCtrlPartition${part_name.as_camel_case()}: + *reg0 = OTP_CTRL_${part_name_define}_DIGEST_0_REG_OFFSET; + *reg1 = OTP_CTRL_${part_name_define}_DIGEST_1_REG_OFFSET; + break; +% endfor + default: + return false; + } + + return true; +} + +dif_result_t dif_otp_ctrl_is_digest_computed(const dif_otp_ctrl_t *otp, + dif_otp_ctrl_partition_t partition, + bool *is_computed) { + if (otp == NULL || is_computed == NULL) { + return kDifBadArg; + } + + ptrdiff_t reg0, reg1; + if (!get_digest_regs(partition, ®0, ®1)) { + return kDifBadArg; + } + + uint64_t value = mmio_region_read32(otp->base_addr, reg1); + value <<= 32; + value |= mmio_region_read32(otp->base_addr, reg0); + + *is_computed = value != 0; + + return kDifOk; +} + +dif_result_t dif_otp_ctrl_get_digest(const dif_otp_ctrl_t *otp, + dif_otp_ctrl_partition_t partition, + uint64_t *digest) { + if (otp == NULL || digest == NULL) { + return kDifBadArg; + } + + ptrdiff_t reg0, reg1; + if (!get_digest_regs(partition, ®0, ®1)) { + return kDifBadArg; + } + + uint64_t value = mmio_region_read32(otp->base_addr, reg1); + value <<= 32; + value |= mmio_region_read32(otp->base_addr, reg0); + + if (value == 0) { + return kDifError; + } + *digest = value; + + return kDifOk; +} + +dif_result_t dif_otp_ctrl_read_blocking(const dif_otp_ctrl_t *otp, + dif_otp_ctrl_partition_t partition, + uint32_t address, uint32_t *buf, + size_t len) { + if (otp == NULL || partition >= ARRAYSIZE(kPartitions) || buf == NULL) { + return kDifBadArg; + } + + if (!kPartitions[partition].is_software) { + return kDifError; + } + + if ((address & kPartitions[partition].align_mask) != 0) { + return kDifUnaligned; + } + + if (address + len >= kPartitions[partition].len) { + return kDifOutOfRange; + } + + uint32_t reg_offset = OTP_CTRL_SW_CFG_WINDOW_REG_OFFSET + + kPartitions[partition].start_addr + address; + mmio_region_memcpy_from_mmio32(otp->base_addr, reg_offset, buf, + len * sizeof(uint32_t)); + return kDifOk; +} diff --git a/src/fuse_ctrl/data/dif_otp_ctrl.h.tpl b/src/fuse_ctrl/data/dif_otp_ctrl.h.tpl new file mode 100755 index 0000000..e860bf6 --- /dev/null +++ b/src/fuse_ctrl/data/dif_otp_ctrl.h.tpl @@ -0,0 +1,615 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +${gen_comment} +<% +from topgen.lib import Name + +parts = otp_mmap.config["partitions"] +digest_parts = [part for part in parts if + part["hw_digest"] == "true" or part["sw_digest"] == "true"] +read_locked_csr_parts = [part for part in parts if part["read_lock"] == "CSR"] +secret_parts = [part for part in parts if part["secret"] == "true"] +%>\ +#ifndef OPENTITAN_SW_DEVICE_LIB_DIF_DIF_OTP_CTRL_H_ +#define OPENTITAN_SW_DEVICE_LIB_DIF_DIF_OTP_CTRL_H_ + +/** + * @file + * @brief OTP Controller Device Interface + * Functions + */ + +#include + +#include "sw/device/lib/base/macros.h" +#include "sw/device/lib/base/mmio.h" +#include "sw/device/lib/dif/dif_base.h" + +#include "sw/device/lib/dif/autogen/dif_otp_ctrl_autogen.h" + +// Header Extern Guard (so header can be used from C and C++) +#ifdef __cplusplus +extern "C" { +#endif // __cplusplus + +/** + * A partition within OTP memory. + */ +typedef enum dif_otp_ctrl_partition { +% for part in parts: +<% + part_name = Name.from_snake_case(part["name"]) + short_desc = part["desc"].split(".")[0].strip().replace("\n", " ") + long_desc_lines = part["desc"].split(".", 1)[1].strip().splitlines() + long_desc = "\n".join([" *" + (" " if line else "") + line for + line in long_desc_lines]) +%>\ + /** + * ${short_desc}. + * + % if long_desc: +${long_desc} + %endif + */ + kDifOtpCtrlPartition${part_name.as_camel_case()}, +% endfor +} dif_otp_ctrl_partition_t; + +/** + * Runtime configuration for OTP. + * + * This struct describes runtime information for one-time configuration of the + * hardware. + */ +typedef struct dif_otp_ctrl_config { + /** + * The timeout for an integrity or consistency check to succeed, in cycles. + * + * 100'000 is recommended as a minimum safe value. + */ + uint32_t check_timeout; + /** + * A mask for the pseudo-random integrity check period. + * + * The value of this mask limits the period of the integrity check; when the + * pseudo-random period is computed, this mask is applied to limit it. For + * example, a value of 0x3'ffff would correspond to a maximum period of about + * 2.8s at 24MHz. + * + * A value of zero disables the check. + */ + uint32_t integrity_period_mask; + /** + * A mask for the pseudo-random consistency check period. + * + * The value of this mask limits the period of the consistency check; when the + * pseudo-random period is computed, this mask is applied to limit it. For + * example, a value of 0x3ff'ffff would correspond to a maximum period of + * about 716s at 24MHz. + * + * A value of zero disables the check. + */ + uint32_t consistency_period_mask; +} dif_otp_ctrl_config_t; + +/** + * A hardware-level status code. + */ +typedef enum dif_otp_ctrl_status_code { + // NOTE: This enum's API *requires* that all "error"-like codes (that is, + // those which have associated cause registers) be a prefix of the enum + // values. + // + // Note furthermore that these enum variants are intended as bit indices, so + // their values should not be randomized. +% for part in parts: +<% + part_name = Name.from_snake_case(part["name"]) + part_name_camel = part_name.as_camel_case() +%>\ + /** + * Indicates an error occurred in the `${part_name_camel}` partition. + */ + kDifOtpCtrlStatusCode${part_name_camel}Error${" = 0" if loop.first else ""}, +% endfor + /** + * Indicates an error occurred in the direct access interface. + */ + kDifOtpCtrlStatusCodeDaiError, + /** + * Indicates an error occurred in the lifecycle interface. + */ + kDifOtpCtrlStatusCodeLciError, + /** + * This is not a status code; rather, it represents the last error code which + * has a corresponding "cause" register. + * + * See `dif_otp_ctrl_status_t` for information on how to use this. + */ + kDifOtpCtrlStatusCodeHasCauseLast = kDifOtpCtrlStatusCodeLciError, + /** + * Indicates that an integrity or consistency check has timed out. + * + * This error is unrecoverable. + */ + kDifOtpCtrlStatusCodeTimeoutError, + /** + * Indicates that the LFSR that generates pseudo-random integrity and + * consistency checks is in a bad state. + * + * This error is unrecoverable. + */ + kDifOtpCtrlStatusCodeLfsrError, + /** + * Indicates that the scrambling hardware is in a bad state. + * + * This error is unrecoverable. + */ + kDifOtpCtrlStatusCodeScramblingError, + /** + * Indicates that the key derivation hardware is in a bad state. + * + * This error is unrecoverable. + */ + kDifOtpCtrlStatusCodeKdfError, + /** + * Indicates a bus integrity error. + * + * This error will raise an alert. + */ + kDifOtpCtrlStatusCodeBusIntegError, + /** + * Indicates that the direct access interface is idle. + */ + kDifOtpCtrlStatusCodeDaiIdle, + /** + * Indicates that an integrity or consistency check is currently pending. + */ + kDifOtpCtrlStatusCodeCheckPending, +} dif_otp_ctrl_status_code_t; + +/** + * A hardware-level error code, associated with a particular error defined in + * `dif_otp_ctrl_status_t`. + */ +typedef enum dif_otp_ctrl_error { + /** + * Indicates no error. + */ + kDifOtpCtrlErrorOk, + /** + * Indicates that an OTP macro command was invalid or did not + * complete successfully. + * + * This error indicates non-recoverable hardware malfunction. + */ + kDifOtpCtrlErrorMacroUnspecified, + /** + * Indicates a recoverable error during a read operation. + * + * A followup read should work as expected. + */ + kDifOtpCtrlErrorMacroRecoverableRead, + /** + * Indicates an unrecoverable error during a read operation. + * + * This error indicates non-recoverable hardware malfunction. + */ + kDifOtpCtrlErrorMacroUnrecoverableRead, + /** + * Indicates that the blank write check failed during a write operation. + */ + kDifOtpCtrlErrorMacroBlankCheckFailed, + /** + * Indicates a locked memory region was accessed. + */ + kDifOtpCtrlErrorLockedAccess, + /** + * Indicates a parity, integrity or consistency check failed in the buffer + * registers. + * + * This error indicates non-recoverable hardware malfunction. + */ + kDifOtpCtrlErrorBackgroundCheckFailed, + /** + * Indicates that the FSM of the controller is in a bad state or that the + * controller's FSM has been moved into its terminal state due to escalation + * via the alert subsystem. + * + * This error indicates that the device has been glitched by an attacker. + */ + kDifOtpCtrlErrorFsmBadState, +} dif_otp_ctrl_error_t; + +/** + * The overall status of the OTP controller. + * + * See `dif_otp_ctrl_get_status()`. + */ +typedef struct dif_otp_ctrl_status { + /** + * Currently active statuses, given as a bit vector. To check whether a + * particular status code was returned, write + * + * bool has_code = (status.codes >> kMyStatusCode) & 1; + * + * Note that it is possible to quickly check that the controller is idle and + * error-free by writing + * + * bool is_ok = status.codes == (1 << kDifOtpStatusCodeDaiIdle); + */ + uint32_t codes; + /** + * A list of root causes for each error status code. + * + * If the error status code `error` is present in `codes`, and + * `error <= kDifOtpCtrlStatusCodeHasCauseLast`, then `causes[error]` + * will contain its root cause. + */ + dif_otp_ctrl_error_t causes[kDifOtpCtrlStatusCodeHasCauseLast + 1]; +} dif_otp_ctrl_status_t; + +/** + * Configures OTP with runtime information. + * + * This function should need to be called at most once for the lifetime of + * `otp`. + * + * @param otp An OTP handle. + * @param config Runtime configuration parameters. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_otp_ctrl_configure(const dif_otp_ctrl_t *otp, + dif_otp_ctrl_config_t config); + +/** + * Runs an integrity check on the OTP hardware. + * + * This function can be used to trigger an integrity check independent of the + * pseudo-random hardware-generated checks. + * + * @param otp An OTP handle. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_otp_ctrl_check_integrity(const dif_otp_ctrl_t *otp); + +/** + * Runs a consistency check on the OTP hardware. + * + * This function can be used to trigger a consistency check independent of the + * pseudo-random hardware-generated checks. + * + * @param otp An OTP handle. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_otp_ctrl_check_consistency(const dif_otp_ctrl_t *otp); + +/** + * Locks out access to the direct access interface registers. + * + * This function is idempotent: calling it while functionality is locked will + * have no effect and return `kDifOk`. + * + * @param otp An OTP handle. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_otp_ctrl_lock_dai(const dif_otp_ctrl_t *otp); + +/** + * Checks whether access to the direct access interface is locked. + * + * Note that besides locking the DAI out until the next reset using the + * dif_otp_ctrl_lock_dai function, the DAI is also temporarily locked by the + * HW itself when it is busy processing a DAI command. In such a case, the + * kDifOtpCtrlStatusCodeDaiIdle status bit will be set to 0 as well. + * + * @param otp An OTP handle. + * @param[out] is_locked Out-param for the locked state. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_otp_ctrl_dai_is_locked(const dif_otp_ctrl_t *otp, + bool *is_locked); + +/** + * Locks out `dif_otp_ctrl_configure()` function. + * + * This function is idempotent: calling it while functionality is locked will + * have no effect and return `kDifOk`. + * + * @param otp An OTP handle. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_otp_ctrl_lock_config(const dif_otp_ctrl_t *otp); + +/** + * Checks whether `dif_otp_ctrl_configure()` function is locked-out. + * + * @param otp An OTP handle. + * @param[out] is_locked Out-param for the locked state. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_otp_ctrl_config_is_locked(const dif_otp_ctrl_t *otp, + bool *is_locked); + +/** + * Locks out `dif_otp_ctrl_check_*()` functions. + * + * This function is idempotent: calling it while functionality is locked will + * have no effect and return `kDifOk`. + * + * @param otp An OTP handle. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_otp_ctrl_lock_check_trigger(const dif_otp_ctrl_t *otp); + +/** + * Checks whether the `dif_otp_ctrl_check_*()` functions are locked-out. + * + * @param otp An OTP handle. + * @param[out] is_locked Out-param for the locked state. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_otp_ctrl_check_trigger_is_locked(const dif_otp_ctrl_t *otp, + bool *is_locked); + +/** + * Locks out reads to a SW partition. + * + * This function should only be called on SW partitions; doing otherwise will + * return an error. + * + * Note that this is distinct from the write-locking performed by calling + * `dif_otp_ctrl_dai_digest()`. In particular, the effects of this function will + * not persist past a system reset. + * + * This function is idempotent: calling it while functionality is locked will + * have no effect and return `kDifOk`. + * + * @param otp An OTP handle. + * @param partition The SW partition to lock. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_otp_ctrl_lock_reading(const dif_otp_ctrl_t *otp, + dif_otp_ctrl_partition_t partition); + +/** + * Checks whether reads to a SW partition are locked out. + * + * This function should only be called on SW partitions; doing otherwise will + * return an error. + * + * @param otp An OTP handle. + * @param partition the SW partition to check for locking. + * @param[out] is_locked Out-param for the locked state. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_otp_ctrl_reading_is_locked(const dif_otp_ctrl_t *otp, + dif_otp_ctrl_partition_t partition, + bool *is_locked); + +/** + * Gets the current status of the OTP controller. + * + * @param otp An OTP handle. + * @param[out] status Out-param for the controller's status. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_otp_ctrl_get_status(const dif_otp_ctrl_t *otp, + dif_otp_ctrl_status_t *status); + +/** + * Calculates a `relative_address` with respect to a `partition` start + * address. + * + * @param partition The partition to use to calculate the reference start + * address. + * @param abs_address Input address relative to the OTP memory start address. + * @param[out] relative_address The result relative address with respect to the + * `partition` start address. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_otp_ctrl_relative_address(dif_otp_ctrl_partition_t partition, + uint32_t abs_address, + uint32_t *relative_address); + +/** + * Schedules a read on the Direct Access Interface. + * + * Reads are performed relative to a partition; `address` should be given + * relative to the start of `partition`. An error is returned for out-of-bounds + * access. + * + * Furthermore, `address` must be well-aligned: it must be four-byte aligned for + * normal partitions and eight-byte-aligned for secret partitions. An error is + * returned for unaligned access. + * + * @param otp An OTP handle. + * @param partition The partition to read from. + * @param address A partition-relative address to read from. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_otp_ctrl_dai_read_start(const dif_otp_ctrl_t *otp, + dif_otp_ctrl_partition_t partition, + uint32_t address); + +/** + * Gets the result of a completed 32-bit read operation on the Direct Access + * Interface. + * + * Whether this function or its 64-bit variant should be called is dependent on + * the most recent partition read from. + * + * @param otp An OTP handle. + * @param[out] value Out-param for the read value. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_otp_ctrl_dai_read32_end(const dif_otp_ctrl_t *otp, + uint32_t *value); + +/** + * Gets the result of a completed 64-bit read operation on the Direct Access + * Interface. + * + * Whether this function or its 32-bit variant should be called is dependent on + * the most recent partition read from. + * + * @param otp An OTP handle. + * @param[out] value Out-param for the read value. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_otp_ctrl_dai_read64_end(const dif_otp_ctrl_t *otp, + uint64_t *value); + +/** + * Schedules a 32-bit write on the Direct Access Interface. + * + * Writes are performed relative to a partition; `address` should be given + * relative to the start of `partition`. An error is returned for out-of-bounds + * access. + * + * Furthermore, `address` must be four-byte-aligned, and `partition` must not be + * a secret partition. An error is returned if neither condition is met. + * + * Note that this function cannot be used to program the digest at the end of a + * `SW` partition; `dif_otp_ctrl_dai_digest()` must be used instead. + * + * @param otp An OTP handle. + * @param partition The partition to program. + * @param address A partition-relative address to program. + * @param value The value to program into the OTP. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_otp_ctrl_dai_program32(const dif_otp_ctrl_t *otp, + dif_otp_ctrl_partition_t partition, + uint32_t address, uint32_t value); + +/** + * Schedules a 64-bit write on the Direct Access Interface. + * + * Writes are performed relative to a partition; `address` should be given + * relative to the start of `partition`. An error is returned for out-of-bounds + * access. + * + * Furthermore, `address` must be eight-byte-aligned, and `partition` must be + * a secret partition. An error is returned if neither condition is met. + * + * @param otp An OTP handle. + * @param partition The partition to program. + * @param address A partition-relative address to program. + * @param value The value to program into the OTP. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_otp_ctrl_dai_program64(const dif_otp_ctrl_t *otp, + dif_otp_ctrl_partition_t partition, + uint32_t address, uint64_t value); + +/** + * Schedules a hardware digest operation on the Direct Access Interface. + * + * **This operation will also lock writes for the given partition.** + * + * If `partition` is a SW partition, `digest` must be non-zero; if it is a + * partition with a hardware-managed digest, `digest` *must* be zero (since the + * digest will be generated by the hardware). An error is returned if either + * precondition is not met. + * + * This function does not work with the lifecycle state partition, and will + * return an error in that case. + * + * @param otp An OTP handle. + * @param partition The partition to digest and lock. + * @param digest The digest to program (for SW partitions). + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_otp_ctrl_dai_digest(const dif_otp_ctrl_t *otp, + dif_otp_ctrl_partition_t partition, + uint64_t digest); + +/** + * Checks if the digest value for the given partition has been computed. Once a + * digest has been computed for a partition, the partition is write-locked + * (additionally, read-locked if the partition is secret). + * + * The lifecycle partition does not have a digest, and checking if this region + * has a computed digest will return an error. + * + * @param otp An OTP handle. + * @param partition The partition to check the digest of. + * @param[out] is_computed Indicates if the digest has been computed. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_otp_ctrl_is_digest_computed(const dif_otp_ctrl_t *otp, + dif_otp_ctrl_partition_t partition, + bool *is_computed); + +/** + * Gets the buffered digest value for the given partition. + * + * Note that this value is only updated when the device is reset; if the digest + * has not been computed yet, or has been computed but not since device reset, + * this function will return an error. + * + * The lifecycle partition does not have a digest and will result in an error + * being returned. + * + * @param otp An OTP handle. + * @param partition The partition to get a digest for. + * @param[out] digest Out-param for the digest. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_otp_ctrl_get_digest(const dif_otp_ctrl_t *otp, + dif_otp_ctrl_partition_t partition, + uint64_t *digest); + +/** + * Performs a memory-mapped read of the given partition, if it supports them. + * + * In particular, this function will read `len` words, starting at `address`, + * relative to the start of `partition`. + * + * The same caveats for `dif_otp_ctrl_dai_read_start()` apply to `address`; in + * addition, `address + len` must also be in-range and must not overflow. + * + * This function will block until the read completes, unlike Direct Access + * Interface functions. + * + * @param otp An OTP handle. + * @param partition The partition to read from. + * @param address A partition-relative address to read from. + * @param[out] buf A buffer of words to write read values to. + * @param len The number of words to read. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_otp_ctrl_read_blocking(const dif_otp_ctrl_t *otp, + dif_otp_ctrl_partition_t partition, + uint32_t address, uint32_t *buf, + size_t len); + +#ifdef __cplusplus +} // extern "C" +#endif // __cplusplus + +#endif // OPENTITAN_SW_DEVICE_LIB_DIF_DIF_OTP_CTRL_H_ diff --git a/src/fuse_ctrl/data/dif_otp_ctrl_unittest.cc.tpl b/src/fuse_ctrl/data/dif_otp_ctrl_unittest.cc.tpl new file mode 100755 index 0000000..a9ecd6c --- /dev/null +++ b/src/fuse_ctrl/data/dif_otp_ctrl_unittest.cc.tpl @@ -0,0 +1,867 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +${gen_comment} +<% +from topgen.lib import Name + +parts = otp_mmap.config["partitions"] +digest_parts = [part for part in parts if + part["hw_digest"] or part["sw_digest"]] +hw_digest_parts = [part for part in parts if part["hw_digest"]] +sw_digest_parts = [part for part in parts if part["sw_digest"]] +read_locked_csr_parts = [part for part in parts if part["read_lock"] == "CSR"] +secret_parts = [part for part in parts if part["secret"]] +%>\ +#include "sw/device/lib/dif/dif_otp_ctrl.h" + +#include +#include +#include + +#include "gtest/gtest.h" +#include "sw/device/lib/base/mmio.h" +#include "sw/device/lib/base/mock_mmio.h" +#include "sw/device/lib/dif/dif_test_base.h" + +#include "otp_ctrl_regs.h" // Generated. + +namespace dif_otp_ctrl_unittest { +namespace { +using ::mock_mmio::LeInt; +using ::mock_mmio::MmioTest; +using ::mock_mmio::MockDevice; +using ::testing::Each; +using ::testing::ElementsAre; + +class OtpTest : public testing::Test, public MmioTest { + protected: + dif_otp_ctrl_t otp_ = {.base_addr = dev().region()}; +}; + +class DaiRegwenTest : public OtpTest {}; + +TEST_F(DaiRegwenTest, LockDai) { + EXPECT_WRITE32( + OTP_CTRL_DIRECT_ACCESS_REGWEN_REG_OFFSET, + {{OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_BIT, false}}); + EXPECT_DIF_OK(dif_otp_ctrl_lock_dai(&otp_)); +} + +TEST_F(DaiRegwenTest, IsDaiLocked) { + bool flag; + + EXPECT_READ32( + OTP_CTRL_DIRECT_ACCESS_REGWEN_REG_OFFSET, + {{OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_BIT, true}}); + EXPECT_DIF_OK(dif_otp_ctrl_dai_is_locked(&otp_, &flag)); + EXPECT_FALSE(flag); + + EXPECT_READ32( + OTP_CTRL_DIRECT_ACCESS_REGWEN_REG_OFFSET, + {{OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_BIT, false}}); + EXPECT_DIF_OK(dif_otp_ctrl_dai_is_locked(&otp_, &flag)); + EXPECT_TRUE(flag); +} + +TEST_F(DaiRegwenTest, NullArgs) { + EXPECT_DIF_BADARG(dif_otp_ctrl_lock_dai(nullptr)); + + bool flag; + EXPECT_DIF_BADARG(dif_otp_ctrl_dai_is_locked(nullptr, &flag)); + EXPECT_DIF_BADARG(dif_otp_ctrl_dai_is_locked(&otp_, nullptr)); +} + +class ConfigTest : public OtpTest {}; + +TEST_F(ConfigTest, Basic) { + dif_otp_ctrl_config_t config = { + .check_timeout = 100'000, + .integrity_period_mask = 0x3'ffff, + .consistency_period_mask = 0x3ff'ffff, + }; + + EXPECT_READ32(OTP_CTRL_CHECK_REGWEN_REG_OFFSET, + {{OTP_CTRL_CHECK_REGWEN_CHECK_REGWEN_BIT, true}}); + + EXPECT_WRITE32(OTP_CTRL_CHECK_TIMEOUT_REG_OFFSET, config.check_timeout); + EXPECT_WRITE32(OTP_CTRL_INTEGRITY_CHECK_PERIOD_REG_OFFSET, + config.integrity_period_mask); + EXPECT_WRITE32(OTP_CTRL_CONSISTENCY_CHECK_PERIOD_REG_OFFSET, + config.consistency_period_mask); + + EXPECT_DIF_OK(dif_otp_ctrl_configure(&otp_, config)); +} + +TEST_F(ConfigTest, Locked) { + EXPECT_READ32(OTP_CTRL_CHECK_REGWEN_REG_OFFSET, + {{OTP_CTRL_CHECK_REGWEN_CHECK_REGWEN_BIT, false}}); + + EXPECT_EQ(dif_otp_ctrl_configure(&otp_, {}), kDifLocked); +} + +TEST_F(ConfigTest, IsConfigLocked) { + bool flag; + + EXPECT_READ32(OTP_CTRL_CHECK_REGWEN_REG_OFFSET, + {{OTP_CTRL_CHECK_REGWEN_CHECK_REGWEN_BIT, true}}); + EXPECT_DIF_OK(dif_otp_ctrl_config_is_locked(&otp_, &flag)); + EXPECT_FALSE(flag); + + EXPECT_READ32(OTP_CTRL_CHECK_REGWEN_REG_OFFSET, + {{OTP_CTRL_CHECK_REGWEN_CHECK_REGWEN_BIT, false}}); + EXPECT_DIF_OK(dif_otp_ctrl_config_is_locked(&otp_, &flag)); + EXPECT_TRUE(flag); +} + +TEST_F(ConfigTest, LockConfig) { + EXPECT_WRITE32(OTP_CTRL_CHECK_REGWEN_REG_OFFSET, + {{OTP_CTRL_CHECK_REGWEN_CHECK_REGWEN_BIT, false}}); + EXPECT_DIF_OK(dif_otp_ctrl_lock_config(&otp_)); +} + +TEST_F(ConfigTest, NullArgs) { + EXPECT_DIF_BADARG(dif_otp_ctrl_configure(nullptr, {})); + + bool flag; + EXPECT_DIF_BADARG(dif_otp_ctrl_config_is_locked(nullptr, &flag)); + EXPECT_DIF_BADARG(dif_otp_ctrl_config_is_locked(&otp_, nullptr)); + + EXPECT_DIF_BADARG(dif_otp_ctrl_lock_config(nullptr)); +} + +class CheckTest : public OtpTest {}; + +TEST_F(CheckTest, Integrity) { + EXPECT_READ32( + OTP_CTRL_CHECK_TRIGGER_REGWEN_REG_OFFSET, + {{OTP_CTRL_CHECK_TRIGGER_REGWEN_CHECK_TRIGGER_REGWEN_BIT, true}}); + EXPECT_WRITE32(OTP_CTRL_CHECK_TRIGGER_REG_OFFSET, + {{OTP_CTRL_CHECK_TRIGGER_INTEGRITY_BIT, true}}); + + EXPECT_DIF_OK(dif_otp_ctrl_check_integrity(&otp_)); +} + +TEST_F(CheckTest, Consistency) { + EXPECT_READ32( + OTP_CTRL_CHECK_TRIGGER_REGWEN_REG_OFFSET, + {{OTP_CTRL_CHECK_TRIGGER_REGWEN_CHECK_TRIGGER_REGWEN_BIT, true}}); + EXPECT_WRITE32(OTP_CTRL_CHECK_TRIGGER_REG_OFFSET, + {{OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_BIT, true}}); + + EXPECT_DIF_OK(dif_otp_ctrl_check_consistency(&otp_)); +} + +TEST_F(CheckTest, LockTrigger) { + EXPECT_WRITE32( + OTP_CTRL_CHECK_TRIGGER_REGWEN_REG_OFFSET, + {{OTP_CTRL_CHECK_TRIGGER_REGWEN_CHECK_TRIGGER_REGWEN_BIT, false}}); + EXPECT_DIF_OK(dif_otp_ctrl_lock_check_trigger(&otp_)); +} + +TEST_F(CheckTest, Locked) { + EXPECT_READ32( + OTP_CTRL_CHECK_TRIGGER_REGWEN_REG_OFFSET, + {{OTP_CTRL_CHECK_TRIGGER_REGWEN_CHECK_TRIGGER_REGWEN_BIT, false}}); + EXPECT_EQ(dif_otp_ctrl_check_integrity(&otp_), kDifLocked); + + EXPECT_READ32( + OTP_CTRL_CHECK_TRIGGER_REGWEN_REG_OFFSET, + {{OTP_CTRL_CHECK_TRIGGER_REGWEN_CHECK_TRIGGER_REGWEN_BIT, false}}); + EXPECT_EQ(dif_otp_ctrl_check_consistency(&otp_), kDifLocked); +} + +TEST_F(CheckTest, NullArgs) { + EXPECT_DIF_BADARG(dif_otp_ctrl_check_integrity(nullptr)); + EXPECT_DIF_BADARG(dif_otp_ctrl_check_consistency(nullptr)); +} + +class ReadLockTest : public OtpTest {}; + +// Too many formatting variants in template code, so disabling clang-format. +// clang-format off +TEST_F(ReadLockTest, IsLocked) { + bool flag; + +% for part in read_locked_csr_parts: +<% + part_name = Name.from_snake_case(part["name"]) + part_name_camel = part_name.as_camel_case() + part_name_define = part_name.as_c_define() +%>\ + EXPECT_READ32( + OTP_CTRL_${part_name_define}_READ_LOCK_REG_OFFSET, + {{OTP_CTRL_${part_name_define}_READ_LOCK_${part_name_define}_READ_LOCK_BIT, + true}}); + EXPECT_DIF_OK(dif_otp_ctrl_reading_is_locked( + &otp_, kDifOtpCtrlPartition${part_name_camel}, &flag)); + EXPECT_FALSE(flag); + + EXPECT_READ32( + OTP_CTRL_${part_name_define}_READ_LOCK_REG_OFFSET, + {{OTP_CTRL_${part_name_define}_READ_LOCK_${part_name_define}_READ_LOCK_BIT, + false}}); + EXPECT_DIF_OK(dif_otp_ctrl_reading_is_locked( + &otp_, kDifOtpCtrlPartition${part_name_camel}, &flag)); + EXPECT_TRUE(flag); + % if not loop.last: + + %endif +% endfor +} + +TEST_F(ReadLockTest, Lock) { +% for part in read_locked_csr_parts: +<% + part_name = Name.from_snake_case(part["name"]) + part_name_camel = part_name.as_camel_case() + part_name_define = part_name.as_c_define() +%>\ + EXPECT_READ32(OTP_CTRL_DIRECT_ACCESS_REGWEN_REG_OFFSET, 1); + EXPECT_WRITE32( + OTP_CTRL_${part_name_define}_READ_LOCK_REG_OFFSET, + {{OTP_CTRL_${part_name_define}_READ_LOCK_${part_name_define}_READ_LOCK_BIT, + false}}); + EXPECT_DIF_OK(dif_otp_ctrl_lock_reading( + &otp_, kDifOtpCtrlPartition${part_name_camel})); + % if not loop.last: + + %endif +% endfor +} + +TEST_F(ReadLockTest, NotLockablePartitions) { + bool flag; +% for part in [p for p in parts if p not in read_locked_csr_parts]: +<% + part_name = Name.from_snake_case(part["name"]) + part_name_camel = part_name.as_camel_case() +%>\ + EXPECT_DIF_BADARG( + dif_otp_ctrl_lock_reading(&otp_, kDifOtpCtrlPartition${part_name_camel})); + EXPECT_DIF_BADARG(dif_otp_ctrl_reading_is_locked( + &otp_, kDifOtpCtrlPartition${part_name_camel}, &flag)); + % if not loop.last: + + %endif +% endfor +} +// clang-format on + +TEST_F(ReadLockTest, NullArgs) { + bool flag; +% for part in read_locked_csr_parts: +<% + part_name = Name.from_snake_case(part["name"]) + part_name_camel = part_name.as_camel_case() + lock_reading_line = f"dif_otp_ctrl_lock_reading(nullptr, kDifOtpCtrlPartition{part_name_camel}));" +%>\ + EXPECT_DIF_BADARG(dif_otp_ctrl_reading_is_locked( + nullptr, kDifOtpCtrlPartition${part_name_camel}, &flag)); + EXPECT_DIF_BADARG(dif_otp_ctrl_reading_is_locked( + &otp_, kDifOtpCtrlPartition${part_name_camel}, nullptr)); + % if len(lock_reading_line) > 80 - 6: + EXPECT_DIF_BADARG(dif_otp_ctrl_lock_reading( + nullptr, kDifOtpCtrlPartition${part_name_camel})); + % else: + EXPECT_DIF_BADARG( + ${lock_reading_line} + % endif + % if not loop.last: + + %endif +% endfor +} + +class StatusTest : public OtpTest {}; + +TEST_F(StatusTest, Idle) { + dif_otp_ctrl_status_t status; + + EXPECT_READ32(OTP_CTRL_STATUS_REG_OFFSET, + {{OTP_CTRL_STATUS_DAI_IDLE_BIT, true}}); + EXPECT_DIF_OK(dif_otp_ctrl_get_status(&otp_, &status)); + + EXPECT_EQ(status.codes, 1 << kDifOtpCtrlStatusCodeDaiIdle); + EXPECT_THAT(status.causes, Each(kDifOtpCtrlErrorOk)); +} + +TEST_F(StatusTest, Errors) { + dif_otp_ctrl_status_t status; + + EXPECT_READ32(OTP_CTRL_STATUS_REG_OFFSET, + { + {OTP_CTRL_STATUS_DAI_IDLE_BIT, true}, + {OTP_CTRL_STATUS_HW_CFG0_ERROR_BIT, true}, + {OTP_CTRL_STATUS_LCI_ERROR_BIT, true}, + }); + +<% + hw_cfg0_entries = [i for i, p in enumerate(parts) if p["name"] == "HW_CFG0"] + hw_cfg0_error_index = 0 + if len(hw_cfg0_entries) > 0: + hw_cfg0_error_index = hw_cfg0_entries[0] + lci_error_index = len(parts) + 1 +%>\ + +% if len(hw_cfg0_entries) > 0: + EXPECT_READ32(OTP_CTRL_ERR_CODE_${hw_cfg0_error_index}_REG_OFFSET, + {{OTP_CTRL_ERR_CODE_0_ERR_CODE_0_OFFSET, + OTP_CTRL_ERR_CODE_0_ERR_CODE_0_VALUE_MACRO_ECC_CORR_ERROR}}); + EXPECT_READ32(OTP_CTRL_ERR_CODE_${lci_error_index}_REG_OFFSET, + {{OTP_CTRL_ERR_CODE_0_ERR_CODE_0_OFFSET, + OTP_CTRL_ERR_CODE_0_ERR_CODE_0_VALUE_MACRO_ERROR}}); +% endif + + EXPECT_DIF_OK(dif_otp_ctrl_get_status(&otp_, &status)); + EXPECT_EQ(status.codes, (1 << kDifOtpCtrlStatusCodeDaiIdle) | + (1 << kDifOtpCtrlStatusCodeHwCfg0Error) | + (1 << kDifOtpCtrlStatusCodeLciError)); + EXPECT_EQ(status.causes[kDifOtpCtrlStatusCodeHwCfg0Error], + kDifOtpCtrlErrorMacroRecoverableRead); + EXPECT_EQ(status.causes[kDifOtpCtrlStatusCodeLciError], + kDifOtpCtrlErrorMacroUnspecified); +} + +TEST_F(StatusTest, NullArgs) { + dif_otp_ctrl_status_t status; + + EXPECT_DIF_BADARG(dif_otp_ctrl_get_status(nullptr, &status)); + EXPECT_DIF_BADARG(dif_otp_ctrl_get_status(&otp_, nullptr)); +} + +struct RelativeAddressParams { + std::string name; + dif_otp_ctrl_partition_t partition; + uint32_t abs_address; + dif_result_t expected_result; + uint32_t expected_relative_address; +}; + +class RelativeAddress + : public OtpTest, + public testing::WithParamInterface {}; + +TEST_P(RelativeAddress, RelativeAddress) { + uint32_t got_relative_address; + dif_result_t got_result = dif_otp_ctrl_relative_address( + GetParam().partition, GetParam().abs_address, &got_relative_address); + EXPECT_EQ(got_result, GetParam().expected_result); + EXPECT_EQ(got_relative_address, GetParam().expected_relative_address); +} + +INSTANTIATE_TEST_SUITE_P( + AllPartitions, RelativeAddress, + testing::Values( +% for part in parts: +<% + part_name = Name.from_snake_case(part["name"]) + part_name_camel = part_name.as_camel_case() + part_name_define = part_name.as_c_define() + step = 8 if part["secret"] else 4 +%>\ + RelativeAddressParams{ + "${part_name_camel}Okay", + kDifOtpCtrlPartition${part_name_camel}, + OTP_CTRL_PARAM_${part_name_define}_OFFSET + ${step}, + kDifOk, + ${step}, + }, + RelativeAddressParams{ + "${part_name_camel}Unaligned", + kDifOtpCtrlPartition${part_name_camel}, + OTP_CTRL_PARAM_${part_name_define}_OFFSET + 1, + kDifUnaligned, + 0, + }, +<% + ## Exclude first partition to avoid a negative offset. +%>\ + % if not loop.first: + RelativeAddressParams{ + "${part_name_camel}OutOfRangeBeforeStart", + kDifOtpCtrlPartition${part_name_camel}, + OTP_CTRL_PARAM_${part_name_define}_OFFSET - ${step}, + kDifOutOfRange, + 0, + }, + % endif + RelativeAddressParams{ + "${part_name_camel}OutOfRangePastEnd", + kDifOtpCtrlPartition${part_name_camel}, + % if len(f"OTP_CTRL_PARAM_{part_name_define}_OFFSET + OTP_CTRL_PARAM_{part_name_define}_SIZE,") <= 80 - 12: + OTP_CTRL_PARAM_${part_name_define}_OFFSET + OTP_CTRL_PARAM_${part_name_define}_SIZE, + % else: + OTP_CTRL_PARAM_${part_name_define}_OFFSET + + OTP_CTRL_PARAM_${part_name_define}_SIZE, + % endif + kDifOutOfRange, + 0, + }${")," if loop.last else ","} +% endfor + [](const testing::TestParamInfo &info) { + return info.param.name; + }); + +class DaiReadTest : public OtpTest {}; + +TEST_F(DaiReadTest, Read32) { + EXPECT_READ32( + OTP_CTRL_DIRECT_ACCESS_REGWEN_REG_OFFSET, + {{OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_BIT, true}}); + EXPECT_WRITE32(OTP_CTRL_DIRECT_ACCESS_ADDRESS_REG_OFFSET, + OTP_CTRL_PARAM_MANUF_STATE_OFFSET); + EXPECT_WRITE32(OTP_CTRL_DIRECT_ACCESS_CMD_REG_OFFSET, + {{OTP_CTRL_DIRECT_ACCESS_CMD_RD_BIT, true}}); + + EXPECT_DIF_OK(dif_otp_ctrl_dai_read_start(&otp_, kDifOtpCtrlPartitionHwCfg0, + /*address=*/0x20)); + + EXPECT_READ32( + OTP_CTRL_DIRECT_ACCESS_REGWEN_REG_OFFSET, + {{OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_BIT, true}}); + EXPECT_READ32(OTP_CTRL_DIRECT_ACCESS_RDATA_0_REG_OFFSET, 0x12345678); + + uint32_t val; + EXPECT_DIF_OK(dif_otp_ctrl_dai_read32_end(&otp_, &val)); + EXPECT_EQ(val, 0x12345678); +} + +TEST_F(DaiReadTest, Read64) { + uint64_t val; +% for part in secret_parts: +<% + part_name = Name.from_snake_case(part["name"]) + part_name_camel = part_name.as_camel_case() + part_name_define = part_name.as_c_define() +%>\ + EXPECT_READ32( + OTP_CTRL_DIRECT_ACCESS_REGWEN_REG_OFFSET, + {{OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_BIT, true}}); + EXPECT_WRITE32(OTP_CTRL_DIRECT_ACCESS_ADDRESS_REG_OFFSET, + OTP_CTRL_PARAM_${part_name_define}_OFFSET + 0x8); + EXPECT_WRITE32(OTP_CTRL_DIRECT_ACCESS_CMD_REG_OFFSET, + {{OTP_CTRL_DIRECT_ACCESS_CMD_RD_BIT, true}}); + + EXPECT_DIF_OK(dif_otp_ctrl_dai_read_start(&otp_, kDifOtpCtrlPartition${part_name_camel}, + /*address=*/0x8)); + + EXPECT_READ32( + OTP_CTRL_DIRECT_ACCESS_REGWEN_REG_OFFSET, + {{OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_BIT, true}}); + EXPECT_READ32(OTP_CTRL_DIRECT_ACCESS_RDATA_1_REG_OFFSET, 0x12345678); + EXPECT_READ32(OTP_CTRL_DIRECT_ACCESS_RDATA_0_REG_OFFSET, 0x90abcdef); + + EXPECT_DIF_OK(dif_otp_ctrl_dai_read64_end(&otp_, &val)); + EXPECT_EQ(val, 0x1234567890abcdef); + % if not loop.last: + + % endif +% endfor +} + +TEST_F(DaiReadTest, Unaligned) { + EXPECT_EQ(dif_otp_ctrl_dai_read_start(&otp_, kDifOtpCtrlPartitionHwCfg0, + /*address=*/0b01), + kDifUnaligned); + EXPECT_EQ(dif_otp_ctrl_dai_read_start(&otp_, kDifOtpCtrlPartitionSecret2, + /*address=*/0b100), + kDifUnaligned); +} + +TEST_F(DaiReadTest, OutOfRange) { + EXPECT_EQ(dif_otp_ctrl_dai_read_start(&otp_, kDifOtpCtrlPartitionHwCfg0, + /*address=*/0x100), + kDifOutOfRange); +} + +TEST_F(DaiReadTest, Busy) { + EXPECT_READ32( + OTP_CTRL_DIRECT_ACCESS_REGWEN_REG_OFFSET, + {{OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_BIT, false}}); + EXPECT_EQ(dif_otp_ctrl_dai_read_start(&otp_, kDifOtpCtrlPartitionHwCfg0, + /*address=*/0x0), + kDifUnavailable); + + EXPECT_READ32( + OTP_CTRL_DIRECT_ACCESS_REGWEN_REG_OFFSET, + {{OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_BIT, false}}); + uint32_t val32; + EXPECT_EQ(dif_otp_ctrl_dai_read32_end(&otp_, &val32), kDifUnavailable); + + EXPECT_READ32( + OTP_CTRL_DIRECT_ACCESS_REGWEN_REG_OFFSET, + {{OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_BIT, false}}); + uint64_t val64; + EXPECT_EQ(dif_otp_ctrl_dai_read64_end(&otp_, &val64), kDifUnavailable); +} + +TEST_F(DaiReadTest, NullArgs) { + EXPECT_DIF_BADARG(dif_otp_ctrl_dai_read_start(nullptr, + kDifOtpCtrlPartitionHwCfg0, + /*address=*/0x0)); + + uint32_t val32; + EXPECT_DIF_BADARG(dif_otp_ctrl_dai_read32_end(nullptr, &val32)); + EXPECT_DIF_BADARG(dif_otp_ctrl_dai_read32_end(&otp_, nullptr)); + + uint64_t val64; + EXPECT_DIF_BADARG(dif_otp_ctrl_dai_read64_end(nullptr, &val64)); + EXPECT_DIF_BADARG(dif_otp_ctrl_dai_read64_end(&otp_, nullptr)); +} + +class DaiProgramTest : public OtpTest {}; + +TEST_F(DaiProgramTest, Program32) { + EXPECT_READ32( + OTP_CTRL_DIRECT_ACCESS_REGWEN_REG_OFFSET, + {{OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_BIT, true}}); + EXPECT_WRITE32(OTP_CTRL_DIRECT_ACCESS_ADDRESS_REG_OFFSET, + OTP_CTRL_PARAM_MANUF_STATE_OFFSET); + EXPECT_WRITE32(OTP_CTRL_DIRECT_ACCESS_WDATA_0_REG_OFFSET, 0x12345678); + EXPECT_WRITE32(OTP_CTRL_DIRECT_ACCESS_CMD_REG_OFFSET, + {{OTP_CTRL_DIRECT_ACCESS_CMD_WR_BIT, true}}); + + EXPECT_DIF_OK(dif_otp_ctrl_dai_program32(&otp_, kDifOtpCtrlPartitionHwCfg0, + /*address=*/0x20, + /*value=*/0x12345678)); +} + +TEST_F(DaiProgramTest, Program64) { + EXPECT_READ32( + OTP_CTRL_DIRECT_ACCESS_REGWEN_REG_OFFSET, + {{OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_BIT, true}}); + EXPECT_WRITE32(OTP_CTRL_DIRECT_ACCESS_ADDRESS_REG_OFFSET, + OTP_CTRL_PARAM_SECRET2_OFFSET + 0x8); + EXPECT_WRITE32(OTP_CTRL_DIRECT_ACCESS_WDATA_0_REG_OFFSET, 0x90abcdef); + EXPECT_WRITE32(OTP_CTRL_DIRECT_ACCESS_WDATA_1_REG_OFFSET, 0x12345678); + EXPECT_WRITE32(OTP_CTRL_DIRECT_ACCESS_CMD_REG_OFFSET, + {{OTP_CTRL_DIRECT_ACCESS_CMD_WR_BIT, true}}); + + EXPECT_DIF_OK(dif_otp_ctrl_dai_program64(&otp_, kDifOtpCtrlPartitionSecret2, + /*address=*/0x8, + /*value=*/0x1234567890abcdef)); +} + +TEST_F(DaiProgramTest, BadPartition) { + EXPECT_EQ(dif_otp_ctrl_dai_program32(&otp_, kDifOtpCtrlPartitionSecret1, + /*address=*/0x0, /*value=*/42), + kDifError); + EXPECT_EQ(dif_otp_ctrl_dai_program64(&otp_, kDifOtpCtrlPartitionHwCfg0, + /*address=*/0x0, /*value=*/42), + kDifError); + + // LC is never writeable. + EXPECT_EQ(dif_otp_ctrl_dai_program32(&otp_, kDifOtpCtrlPartitionLifeCycle, + /*address=*/0x0, /*value=*/42), + kDifError); +} + +TEST_F(DaiProgramTest, Unaligned) { + EXPECT_EQ(dif_otp_ctrl_dai_program32(&otp_, kDifOtpCtrlPartitionHwCfg0, + /*address=*/0b01, /*value=*/42), + kDifUnaligned); + EXPECT_EQ(dif_otp_ctrl_dai_program64(&otp_, kDifOtpCtrlPartitionSecret2, + /*address=*/0b100, /*value=*/42), + kDifUnaligned); +} + +TEST_F(DaiProgramTest, OutOfRange) { + // Check that we can't write a digest directly. + EXPECT_EQ(dif_otp_ctrl_dai_program32( + &otp_, kDifOtpCtrlPartitionCreatorSwCfg, + /*address=*/OTP_CTRL_PARAM_CREATOR_SW_CFG_DIGEST_OFFSET, + /*value=*/42), + kDifOutOfRange); + + // Same digest check for 64-bit. + EXPECT_EQ(dif_otp_ctrl_dai_program64( + &otp_, kDifOtpCtrlPartitionSecret2, + /*address=*/OTP_CTRL_PARAM_SECRET2_DIGEST_OFFSET, /*value=*/42), + kDifOutOfRange); +} + +TEST_F(DaiProgramTest, Busy) { + EXPECT_READ32( + OTP_CTRL_DIRECT_ACCESS_REGWEN_REG_OFFSET, + {{OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_BIT, false}}); + EXPECT_EQ(dif_otp_ctrl_dai_program32(&otp_, kDifOtpCtrlPartitionHwCfg0, + /*address=*/0x0, /*value=*/42), + kDifUnavailable); + + EXPECT_READ32( + OTP_CTRL_DIRECT_ACCESS_REGWEN_REG_OFFSET, + {{OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_BIT, false}}); + EXPECT_EQ(dif_otp_ctrl_dai_program64(&otp_, kDifOtpCtrlPartitionSecret0, + /*address=*/0x0, /*value=*/42), + kDifUnavailable); +} + +TEST_F(DaiProgramTest, NullArgs) { + EXPECT_DIF_BADARG(dif_otp_ctrl_dai_program32(nullptr, + kDifOtpCtrlPartitionHwCfg0, + /*address=*/0x0, /*value=*/42)); + EXPECT_DIF_BADARG(dif_otp_ctrl_dai_program64(nullptr, + kDifOtpCtrlPartitionSecret0, + /*address=*/0x0, /*value=*/42)); +} + +class DaiDigestTest : public OtpTest {}; + +TEST_F(DaiDigestTest, DigestSw) { +% for part in sw_digest_parts: +<% + part_name = Name.from_snake_case(part["name"]) + part_name_define = part_name.as_c_define() + part_name_camel = part_name.as_camel_case() + dai_digest_line = ("EXPECT_DIF_OK(dif_otp_ctrl_dai_digest(&otp_, " + + f"kDifOtpCtrlPartition{part_name_camel},") +%>\ + EXPECT_READ32( + OTP_CTRL_DIRECT_ACCESS_REGWEN_REG_OFFSET, + {{OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_BIT, true}}); + EXPECT_WRITE32(OTP_CTRL_DIRECT_ACCESS_ADDRESS_REG_OFFSET, + OTP_CTRL_PARAM_${part_name.as_c_define()}_DIGEST_OFFSET); + EXPECT_WRITE32(OTP_CTRL_DIRECT_ACCESS_WDATA_0_REG_OFFSET, 0x00abcdef); + EXPECT_WRITE32(OTP_CTRL_DIRECT_ACCESS_WDATA_1_REG_OFFSET, 0xabcdef00); + EXPECT_WRITE32(OTP_CTRL_DIRECT_ACCESS_CMD_REG_OFFSET, + {{OTP_CTRL_DIRECT_ACCESS_CMD_WR_BIT, true}}); + + % if len(dai_digest_line) > 80 - 2: +<% dai_digest_line = (f"kDifOtpCtrlPartition{part_name_camel},") %>\ + % if len(dai_digest_line) > 80 - 40: + EXPECT_DIF_OK( + dif_otp_ctrl_dai_digest(&otp_, kDifOtpCtrlPartition${part_name_camel}, + /*digest=*/0xabcdef0000abcdef)); + % else: + EXPECT_DIF_OK(dif_otp_ctrl_dai_digest(&otp_, + kDifOtpCtrlPartition${part_name_camel}, + /*digest=*/0xabcdef0000abcdef)); + % endif + % else: + ${dai_digest_line} + /*digest=*/0xabcdef0000abcdef)); + % endif + % if not loop.last: + + % endif +% endfor +} + +TEST_F(DaiDigestTest, DigestHw) { +% for part in hw_digest_parts: +<% + part_name = Name.from_snake_case(part["name"]) + part_name_define = part_name.as_c_define() + part_name_camel = part_name.as_camel_case() + dai_digest_line = ("EXPECT_DIF_OK(dif_otp_ctrl_dai_digest(&otp_, " + + f"kDifOtpCtrlPartition{part_name_camel},") +%>\ + EXPECT_READ32( + OTP_CTRL_DIRECT_ACCESS_REGWEN_REG_OFFSET, + {{OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_BIT, true}}); + EXPECT_WRITE32(OTP_CTRL_DIRECT_ACCESS_ADDRESS_REG_OFFSET, + OTP_CTRL_PARAM_${part_name_define}_OFFSET); + EXPECT_WRITE32(OTP_CTRL_DIRECT_ACCESS_CMD_REG_OFFSET, + {{OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_BIT, true}}); + + EXPECT_DIF_OK(dif_otp_ctrl_dai_digest(&otp_, kDifOtpCtrlPartition${part_name_camel}, + /*digest=*/0)); + % if not loop.last: + + % endif +% endfor +} + +TEST_F(DaiDigestTest, BadPartition) { + EXPECT_EQ(dif_otp_ctrl_dai_digest(&otp_, kDifOtpCtrlPartitionLifeCycle, + /*digest=*/0), + kDifError); +} + +TEST_F(DaiDigestTest, Busy) { + EXPECT_READ32( + OTP_CTRL_DIRECT_ACCESS_REGWEN_REG_OFFSET, + {{OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_BIT, false}}); + + EXPECT_EQ( + dif_otp_ctrl_dai_digest(&otp_, kDifOtpCtrlPartitionHwCfg0, /*digest=*/0), + kDifUnavailable); +} + +TEST_F(DaiDigestTest, BadDigest) { + EXPECT_DIF_BADARG(dif_otp_ctrl_dai_digest(&otp_, kDifOtpCtrlPartitionHwCfg0, + /*digest=*/0xabcdef0000abcdef)); + EXPECT_DIF_BADARG(dif_otp_ctrl_dai_digest(&otp_, + kDifOtpCtrlPartitionCreatorSwCfg, + /*digest=*/0)); +} + +TEST_F(DaiDigestTest, NullArgs) { + EXPECT_DIF_BADARG(dif_otp_ctrl_dai_digest(nullptr, + kDifOtpCtrlPartitionCreatorSwCfg, + /*digest=*/0xabcdef0000abcdef)); +} + +class IsDigestComputed : public OtpTest {}; + +TEST_F(IsDigestComputed, NullArgs) { + bool is_computed; + EXPECT_DIF_BADARG(dif_otp_ctrl_is_digest_computed( + nullptr, kDifOtpCtrlPartitionSecret2, &is_computed)); + EXPECT_DIF_BADARG(dif_otp_ctrl_is_digest_computed( + &otp_, kDifOtpCtrlPartitionSecret2, nullptr)); + EXPECT_DIF_BADARG(dif_otp_ctrl_is_digest_computed( + nullptr, kDifOtpCtrlPartitionSecret2, nullptr)); +} + +TEST_F(IsDigestComputed, BadPartition) { + bool is_computed; + EXPECT_DIF_BADARG(dif_otp_ctrl_is_digest_computed( + &otp_, kDifOtpCtrlPartitionLifeCycle, &is_computed)); +} + +TEST_F(IsDigestComputed, Success) { + bool is_computed; + + EXPECT_READ32(OTP_CTRL_SECRET2_DIGEST_1_REG_OFFSET, 0x98abcdef); + EXPECT_READ32(OTP_CTRL_SECRET2_DIGEST_0_REG_OFFSET, 0xabcdef01); + EXPECT_DIF_OK(dif_otp_ctrl_is_digest_computed( + &otp_, kDifOtpCtrlPartitionSecret2, &is_computed)); + EXPECT_TRUE(is_computed); + + EXPECT_READ32(OTP_CTRL_SECRET2_DIGEST_1_REG_OFFSET, 0); + EXPECT_READ32(OTP_CTRL_SECRET2_DIGEST_0_REG_OFFSET, 0); + EXPECT_DIF_OK(dif_otp_ctrl_is_digest_computed( + &otp_, kDifOtpCtrlPartitionSecret2, &is_computed)); + EXPECT_FALSE(is_computed); +} + +struct DigestParams { + dif_otp_ctrl_partition_t partition; + bool has_digest; + ptrdiff_t reg0, reg1; +}; + +class GetDigest : public OtpTest, + public testing::WithParamInterface {}; + +TEST_P(GetDigest, GetDigest) { + if (!GetParam().has_digest) { + uint64_t digest; + EXPECT_DIF_BADARG( + dif_otp_ctrl_get_digest(&otp_, GetParam().partition, &digest)); + return; + } + + EXPECT_READ32(GetParam().reg1, 0xabcdef99); + EXPECT_READ32(GetParam().reg0, 0x99abcdef); + + uint64_t digest; + EXPECT_DIF_OK(dif_otp_ctrl_get_digest(&otp_, GetParam().partition, &digest)); + EXPECT_EQ(digest, 0xabcdef9999abcdef); +} + +TEST_P(GetDigest, BadDigest) { + if (!GetParam().has_digest) { + return; + } + + EXPECT_READ32(GetParam().reg1, 0x0); + EXPECT_READ32(GetParam().reg0, 0x0); + + uint64_t digest; + EXPECT_EQ(dif_otp_ctrl_get_digest(&otp_, GetParam().partition, &digest), + kDifError); +} + +TEST_P(GetDigest, NullArgs) { + uint64_t digest; + EXPECT_DIF_BADARG( + dif_otp_ctrl_get_digest(nullptr, GetParam().partition, &digest)); + EXPECT_DIF_BADARG( + dif_otp_ctrl_get_digest(&otp_, GetParam().partition, nullptr)); +} + +// This depends on the maximum length of partition names, which will +// be changing, so turn formatting off. +// clang-format off +INSTANTIATE_TEST_SUITE_P( + AllDigests, GetDigest, + testing::Values( +% for part in parts: +<% + part_name = Name.from_snake_case(part["name"]) + part_name_camel = part_name.as_camel_case() + part_name_define = part_name.as_c_define() +%>\ + % if part in digest_parts: + DigestParams{ + kDifOtpCtrlPartition${part_name_camel}, + true, + OTP_CTRL_${part_name_define}_DIGEST_0_REG_OFFSET, + OTP_CTRL_${part_name_define}_DIGEST_1_REG_OFFSET, + }${"" if loop.last else ","} + % else: + DigestParams{ + kDifOtpCtrlPartition${part_name_camel}, + false, + 0, + 0, + }${"));" if loop.last else ","} + % endif +% endfor +// clang-format on + +class BlockingIoTest : public OtpTest { + protected: + static constexpr size_t kWords = 4; +}; + +TEST_F(BlockingIoTest, Read) { + for (size_t i = 0; i < kWords; ++i) { + auto offset = + OTP_CTRL_PARAM_OWNER_SW_CFG_OFFSET + 0x10 + i * sizeof(uint32_t); + EXPECT_READ32(OTP_CTRL_SW_CFG_WINDOW_REG_OFFSET + offset, i + 1); + } + + std::vector buf(kWords); + EXPECT_DIF_OK(dif_otp_ctrl_read_blocking( + &otp_, kDifOtpCtrlPartitionOwnerSwCfg, 0x10, buf.data(), buf.size())); + EXPECT_THAT(buf, ElementsAre(1, 2, 3, 4)); +} + +TEST_F(BlockingIoTest, BadPartition) { + std::vector buf(kWords); + EXPECT_EQ(dif_otp_ctrl_read_blocking(&otp_, kDifOtpCtrlPartitionHwCfg0, 0x10, + buf.data(), buf.size()), + kDifError); +} + +TEST_F(BlockingIoTest, Unaligned) { + std::vector buf(kWords); + EXPECT_EQ(dif_otp_ctrl_read_blocking(&otp_, kDifOtpCtrlPartitionOwnerSwCfg, + 0x11, buf.data(), buf.size()), + kDifUnaligned); +} + +TEST_F(BlockingIoTest, OutOfRange) { + std::vector buf(0x2f0); + EXPECT_EQ(dif_otp_ctrl_read_blocking(&otp_, kDifOtpCtrlPartitionOwnerSwCfg, + 0x300, buf.data(), buf.size()), + kDifOutOfRange); + EXPECT_EQ(dif_otp_ctrl_read_blocking(&otp_, kDifOtpCtrlPartitionOwnerSwCfg, + 0x10, buf.data(), 0x330), + kDifOutOfRange); +} + +TEST_F(BlockingIoTest, NullArgs) { + std::vector buf(kWords); + EXPECT_DIF_BADARG(dif_otp_ctrl_read_blocking( + nullptr, kDifOtpCtrlPartitionOwnerSwCfg, 0x10, buf.data(), buf.size())); + EXPECT_DIF_BADARG(dif_otp_ctrl_read_blocking( + &otp_, kDifOtpCtrlPartitionOwnerSwCfg, 0x10, nullptr, buf.size())); +} + +} // namespace +} // namespace dif_otp_ctrl_unittest diff --git a/src/fuse_ctrl/data/entropy_src.json b/src/fuse_ctrl/data/entropy_src.json new file mode 100644 index 0000000..df7fd3a --- /dev/null +++ b/src/fuse_ctrl/data/entropy_src.json @@ -0,0 +1,1369 @@ +{ + "name": "entropy_src", + "clocking": [ + { + "clock": "clk_i", + "reset": "rst_ni" + } + ], + "bus_interfaces": [ + { + "protocol": "tlul", + "direction": "device" + } + ], + "interrupt_list": [ + { + "name": "es_entropy_valid", + "desc": "Asserted when entropy source bits are available." + }, + { + "name": "es_health_test_failed", + "desc": "Asserted when the alert count has been met." + }, + { + "name": "es_observe_fifo_ready", + "desc": "Asserted when the observe FIFO has filled to the threshold level." + }, + { + "name": "es_fatal_err", + "desc": "Asserted when a FIFO error occurs, or if an illegal state machine state is reached." + } + ], + "inter_signal_list": [ + { + "struct": "entropy_src_hw_if", + "type": "req_rsp", + "name": "entropy_src_hw_if", + "act": "rsp", + "package": "entropy_src_pkg" + }, + { + "struct": "cs_aes_halt", + "type": "req_rsp", + "name": "cs_aes_halt", + "act": "req", + "package": "entropy_src_pkg" + }, + { + "struct": "entropy_src_rng", + "type": "req_rsp", + "name": "entropy_src_rng", + "act": "req", + "package": "entropy_src_pkg" + }, + { + "struct": "entropy_src_xht", + "type": "req_rsp", + "name": "entropy_src_xht", + "act": "req", + "package": "entropy_src_pkg" + }, + { + "struct": "mubi8", + "type": "uni", + "name": "otp_en_entropy_src_fw_read", + "act": "rcv", + "package": "caliptra_prim_mubi_pkg" + }, + { + "struct": "mubi8", + "type": "uni", + "name": "otp_en_entropy_src_fw_over", + "act": "rcv", + "package": "caliptra_prim_mubi_pkg" + }, + { + "struct": "logic", + "type": "uni", + "name": "rng_fips", + "act": "req", + "width": 1, + "package": "" + } + ], + "param_list": [ + { + "name": "Stub", + "type": "bit", + "default": "0", + "desc": "Stub out the core of entropy_src logic", + "local": "false", + "expose": "true" + } + ], + "alert_list": [ + { + "name": "recov_alert", + "desc": "This alert is triggered upon the alert health test threshold criteria not met." + }, + { + "name": "fatal_alert", + "desc": "This alert triggers for any condition detected in the !!ERR_CODE register,\nwhich includes FIFO errors, COUNTER errors, FSM state errors,\nand also when integrity failures are detected on the TL-UL bus." + } + ], + "countermeasures": [ + { + "name": "CONFIG.REGWEN", + "desc": "Registers are protected from writes." + }, + { + "name": "CONFIG.MUBI", + "desc": "Registers have multi-bit encoded fields." + }, + { + "name": "CONFIG.REDUN", + "desc": "Threshold register has an inverted copy to compare against." + }, + { + "name": "INTERSIG.MUBI", + "desc": "OTP signal used to enable software access to registers." + }, + { + "name": "MAIN_SM.FSM.SPARSE", + "desc": "The ENTROPY_SRC main state machine uses a sparse state encoding." + }, + { + "name": "ACK_SM.FSM.SPARSE", + "desc": "The ENTROPY_SRC ack state machine uses a sparse state encoding." + }, + { + "name": "RNG.BKGN_CHK", + "desc": "Random number generator is protected with continuous background health checks." + }, + { + "name": "CTR.REDUN", + "desc": "Counter hardening for all health test counters." + }, + { + "name": "CTR.LOCAL_ESC", + "desc": "Redundant counter failures will cause a local escalation to the main state machine." + }, + { + "name": "ESFINAL_RDATA.BUS.CONSISTENCY", + "desc": "Comparison on successive bus values for the post-conditioned entropy seed bus." + }, + { + "name": "TILE_LINK.BUS.INTEGRITY", + "desc": "Tilelink end-to-end bus integrity scheme." + } + ], + "regwidth": "32", + "registers": [ + { + "name": "ME_REGWEN", + "desc": "Register write enable for module enable register", + "swaccess": "rw0c", + "hwaccess": "none", + "fields": [ + { + "bits": "0", + "desc": "When true, the !!MODULE_ENABLE register can be modified.\nWhen false, it becomes read-only.", + "resval": 1 + } + ] + }, + { + "name": "SW_REGUPD", + "desc": "Register write enable for control and threshold registers", + "swaccess": "rw0c", + "hwaccess": "hro", + "tags": [ + "excl:CsrAllTests:CsrExclAll" + ], + "fields": [ + { + "bits": "0", + "desc": "When this bit true and the MODULE_ENABLE field is false,\nthe REGWEN write enable bit read as true, and is distributed to\nall associated control and threshold registers.\nWhen false, these registers become read-only.", + "resval": 1 + } + ] + }, + { + "name": "REGWEN", + "desc": "Register write enable for all control registers", + "swaccess": "ro", + "hwaccess": "hwo", + "tags": [ + "excl:CsrNonInitTests:CsrExclCheck" + ], + "fields": [ + { + "bits": "0", + "desc": "This read-only write enable bit will allow write access\nto control and theshold registers that are associated with this bit,\nbut only when the MODULE_ENABLE field is set to kMultiBitBool4False and the\nSW_REGUPD write enable bit is set to true.\nWhen read as false, these registers become read-only.", + "resval": 1 + } + ] + }, + { + "name": "REV", + "desc": "Revision register", + "swaccess": "ro", + "hwaccess": "none", + "fields": [ + { + "bits": "23:16", + "name": "CHIP_TYPE", + "desc": "Read of this register shows the type of chip using this block.", + "resval": "0x1" + }, + { + "bits": "15:8", + "name": "HW_REVISION", + "desc": "Read of this register shows the revision of this block.", + "resval": "0x3" + }, + { + "bits": "7:0", + "name": "ABI_REVISION", + "desc": "Read of this register shows the ABI of this block.", + "resval": "0x3" + } + ] + }, + { + "name": "MODULE_ENABLE", + "desc": "Module enable register", + "swaccess": "rw", + "hwaccess": "hro", + "regwen": "ME_REGWEN", + "tags": [ + "excl:CsrAllTests:CsrExclAll" + ], + "fields": [ + { + "bits": "3:0", + "mubi": true, + "name": "MODULE_ENABLE", + "desc": "Setting this field to kMultiBitBool4True will enable the ENTROPY_SRC module. Setting\nthis field to kMultiBitBool4False will effectively reset the module. The modules of\nthe entropy complex may only be enabled and disabled in a specific order, see\nProgrammers Guide for details.", + "resval": false + } + ] + }, + { + "name": "CONF", + "desc": "Configuration register", + "swaccess": "rw", + "hwaccess": "hro", + "regwen": "REGWEN", + "tags": [ + "excl:CsrAllTests:CsrExclAll" + ], + "fields": [ + { + "bits": "3:0", + "name": "FIPS_ENABLE", + "mubi": true, + "desc": "Setting this field to kMultiBitBool4True will enable FIPS qualified entropy to be\ngenerated.", + "resval": false + }, + { + "bits": "7:4", + "name": "ENTROPY_DATA_REG_ENABLE", + "mubi": true, + "desc": "Setting this field to kMultiBitBool4True will enable reading entropy values from the\nENTROPY_DATA register. This function also requires that the otp_en_entropy_src_fw_read\ninput vector is set to the enable encoding.", + "resval": false + }, + { + "bits": "15:12", + "name": "THRESHOLD_SCOPE", + "mubi": true, + "desc": "This field controls the scope (either by-line or by-sum) of the health checks.\nIf set to kMultiBitBool4True, the Adaptive Proportion and Markov Tests will accumulate all\nRNG input lines into a single score, and thresholds will be applied to the sum all\nthe entropy input lines. If set to kMultiBitBool4False, the RNG input lines are all scored\nindividually. A statistical deviation in any one input line, be it due to\ncoincidence or failure, will force rejection of the sample, and count toward the\ntotal alert count.", + "resval": false + }, + { + "bits": "23:20", + "name": "RNG_BIT_ENABLE", + "mubi": true, + "desc": "Setting this field to kMultiBitBool4True enables the single RNG bit mode, where only\none bit is sampled.", + "resval": false + }, + { + "bits": "25:24", + "name": "RNG_BIT_SEL", + "desc": "When the above bit iset, this field selects which bit from the RNG bus will\nbe processed when in single RNG bit mode.\nThis two bit field selects the RNG bit stream:\n0b00: RNG bit 0\n0b01: RNG bit 1\n0b10: RNG bit 2\n0b11: RNG bit 3" + } + ] + }, + { + "name": "ENTROPY_CONTROL", + "desc": "Entropy control register", + "swaccess": "rw", + "hwaccess": "hro", + "regwen": "REGWEN", + "tags": [ + "excl:CsrAllTests:CsrExclAll" + ], + "fields": [ + { + "bits": "3:0", + "name": "ES_ROUTE", + "mubi": true, + "desc": "Setting this field to kMultiBitBool4True routes the generated entropy value to the ENTROPY_DATA\nregister to be read by firmware. When this field is kMultiBitBool4False, the generated\nentropy will be forwarded out of this module to the hardware interface.", + "resval": false + }, + { + "bits": "7:4", + "name": "ES_TYPE", + "mubi": true, + "desc": "Setting this field to kMultiBitBool4True will bypass the conditioning logic and bring raw entropy\ndata to the ENTROPY_DATA register. When kMultiBitBool4False, FIPS compliant entropy\nwill be brought the ENTROPY_DATA register, after being conditioned.", + "resval": false + } + ] + }, + { + "name": "ENTROPY_DATA", + "desc": "Entropy data bits", + "swaccess": "ro", + "hwaccess": "hrw", + "hwext": "true", + "hwre": "true", + "fields": [ + { + "bits": "31:0", + "desc": "A read of this register provides generated entropy bits to firmware." + } + ] + }, + { + "name": "HEALTH_TEST_WINDOWS", + "desc": "Health test windows register", + "swaccess": "rw", + "hwaccess": "hro", + "regwen": "REGWEN", + "fields": [ + { + "bits": "15:0", + "name": "FIPS_WINDOW", + "desc": "This is the window size for all health tests. This value is used in normal mode\n when entropy is being tested in FIPS/CC compliance mode.\n The default value is (2048 bits * 1 clock/4 bits);", + "resval": "0x0200" + }, + { + "bits": "31:16", + "name": "BYPASS_WINDOW", + "desc": "This is the window size for all health tests when running in bypass mode. This mode\n is active after reset for the first and only test run, or when this mode is\n programmed by firmware.\n The default value is (384 bits * 1 clock/4 bits);\n\n Note that currently only a window size of 384 is supported and tested (this\n corresponds to the register default value 0x60). Do not use any other values,\n unless you know what you are doing.", + "resval": "0x0060" + } + ] + }, + { + "name": "REPCNT_THRESHOLDS", + "desc": "Repetition count test thresholds register", + "swaccess": "rw", + "hwaccess": "hrw", + "hwext": "true", + "hwqe": "true", + "regwen": "REGWEN", + "tags": [ + "excl:CsrNonInitTests:CsrExclWrite" + ], + "fields": [ + { + "bits": "15:0", + "name": "FIPS_THRESH", + "desc": "This is the threshold size for the repetition count health test.\n This value is used in normal mode when entropy is being tested in\n FIPS/CC compliance mode.\n This register must be written before the module is enabled.\n Writing to this register will only update the register if the\n written value is less than the current value of this register.\n A read from this register always reflects the current value.", + "resval": "0xFFFF" + }, + { + "bits": "31:16", + "name": "BYPASS_THRESH", + "desc": "This is the threshold size for the repetition count health test\n running in bypass mode. This mode is active after reset for the\n first and only test run, or when this mode is programmed by firmware.\n This register must be written before the module is enabled.\n Writing to this register will only update the register if the\n written value is less than the current value of this register.\n A read from this register always reflects the current value.", + "resval": "0xFFFF" + } + ] + }, + { + "name": "REPCNTS_THRESHOLDS", + "desc": "Repetition count symbol test thresholds register", + "swaccess": "rw", + "hwaccess": "hrw", + "hwext": "true", + "hwqe": "true", + "regwen": "REGWEN", + "tags": [ + "excl:CsrNonInitTests:CsrExclWrite" + ], + "fields": [ + { + "bits": "15:0", + "name": "FIPS_THRESH", + "desc": "This is the threshold size for the repetition count symbol health test.\n This value is used in normal mode when entropy is being tested in\n FIPS/CC compliance mode.\n This register must be written before the module is enabled.\n Writing to this register will only update the register if the\n written value is less than the current value of this register.\n A read from this register always reflects the current value.", + "resval": "0xFFFF" + }, + { + "bits": "31:16", + "name": "BYPASS_THRESH", + "desc": "This is the threshold size for the repetition count symbol health test\n running in bypass mode. This mode is active after reset for the\n first and only test run, or when this mode is programmed by firmware.\n This register must be written before the module is enabled.\n Writing to this register will only update the register if the\n written value is less than the current value of this register.\n A read from this register always reflects the current value.", + "resval": "0xFFFF" + } + ] + }, + { + "name": "ADAPTP_HI_THRESHOLDS", + "desc": "Adaptive proportion test high thresholds register", + "swaccess": "rw", + "hwaccess": "hrw", + "hwext": "true", + "hwqe": "true", + "regwen": "REGWEN", + "tags": [ + "excl:CsrNonInitTests:CsrExclWrite" + ], + "fields": [ + { + "bits": "15:0", + "name": "FIPS_THRESH", + "desc": "This is the threshold size for the adaptive proportion health test.\n This value is used in normal mode when entropy is being tested in\n FIPS/CC compliance mode.\n This register must be written before the module is enabled.\n Writing to this register will only update the register if the\n written value is less than the current value of this register.\n A read from this register always reflects the current value.", + "resval": "0xFFFF" + }, + { + "bits": "31:16", + "name": "BYPASS_THRESH", + "desc": "This is the threshold size for the adaptive proportion health test\n running in bypass mode. This mode is active after reset for the\n first and only test run, or when this mode is programmed by firmware.\n This register must be written before the module is enabled.\n Writing to this register will only update the register if the\n written value is less than the current value of this register.\n A read from this register always reflects the current value.", + "resval": "0xFFFF" + } + ] + }, + { + "name": "ADAPTP_LO_THRESHOLDS", + "desc": "Adaptive proportion test low thresholds register", + "swaccess": "rw", + "hwaccess": "hrw", + "hwext": "true", + "hwqe": "true", + "regwen": "REGWEN", + "tags": [ + "excl:CsrNonInitTests:CsrExclWrite" + ], + "fields": [ + { + "bits": "15:0", + "name": "FIPS_THRESH", + "desc": "This is the threshold size for the adaptive proportion health test.\n This value is used in normal mode when entropy is being tested in\n FIPS/CC compliance mode.\n This register must be written before the module is enabled.\n Writing to this register will only update the register if the\n written value is greater than the current value of this register.\n A read from this register always reflects the current value.", + "resval": "0x0000" + }, + { + "bits": "31:16", + "name": "BYPASS_THRESH", + "desc": "This is the threshold size for the adaptive proportion health test\n running in bypass mode. This mode is active after reset for the\n first and only test run, or when this mode is programmed by firmware.\n This register must be written before the module is enabled.\n Writing to this register will only update the register if the\n written value is greater than the current value of this register.\n A read from this register always reflects the current value.", + "resval": "0x0000" + } + ] + }, + { + "name": "BUCKET_THRESHOLDS", + "desc": "Bucket test thresholds register", + "swaccess": "rw", + "hwaccess": "hrw", + "hwext": "true", + "hwqe": "true", + "regwen": "REGWEN", + "tags": [ + "excl:CsrNonInitTests:CsrExclWrite" + ], + "fields": [ + { + "bits": "15:0", + "name": "FIPS_THRESH", + "desc": "This is the threshold size for the bucket health test.\n This value is used in normal mode when entropy is being tested in\n FIPS/CC compliance mode.\n This register must be written before the module is enabled.\n Writing to this register will only update the register if the\n written value is less than the current value of this register.\n A read from this register always reflects the current value.", + "resval": "0xFFFF" + }, + { + "bits": "31:16", + "name": "BYPASS_THRESH", + "desc": "This is the threshold size for the bucket health test\n running in bypass mode. This mode is active after reset for the\n first and only test run, or when this mode is programmed by firmware.\n This register must be written before the module is enabled.\n Writing to this register will only update the register if the\n written value is less than the current value of this register.\n A read from this register always reflects the current value.", + "resval": "0xFFFF" + } + ] + }, + { + "name": "MARKOV_HI_THRESHOLDS", + "desc": "Markov test high thresholds register", + "swaccess": "rw", + "hwaccess": "hrw", + "hwext": "true", + "hwqe": "true", + "regwen": "REGWEN", + "tags": [ + "excl:CsrNonInitTests:CsrExclWrite" + ], + "fields": [ + { + "bits": "15:0", + "name": "FIPS_THRESH", + "desc": "This is the threshold size for the Markov health test.\n This value is used in normal mode when entropy is being tested in\n FIPS/CC compliance mode.\n This register must be written before the module is enabled.\n Writing to this register will only update the register if the\n written value is less than the current value of this register.\n A read from this register always reflects the current value.", + "resval": "0xFFFF" + }, + { + "bits": "31:16", + "name": "BYPASS_THRESH", + "desc": "This is the threshold size for the Markov health test\n running in bypass mode. This mode is active after reset for the\n first and only test run, or when this mode is programmed by firmware.\n This register must be written before the module is enabled.\n Writing to this register will only update the register if the\n written value is less than the current value of this register.\n A read from this register always reflects the current value.", + "resval": "0xFFFF" + } + ] + }, + { + "name": "MARKOV_LO_THRESHOLDS", + "desc": "Markov test low thresholds register", + "swaccess": "rw", + "hwaccess": "hrw", + "hwext": "true", + "hwqe": "true", + "regwen": "REGWEN", + "tags": [ + "excl:CsrNonInitTests:CsrExclWrite" + ], + "fields": [ + { + "bits": "15:0", + "name": "FIPS_THRESH", + "desc": "This is the threshold size for the Markov health test.\n This value is used in normal mode when entropy is being tested in\n FIPS/CC compliance mode.\n This register must be written before the module is enabled.\n Writing to this register will only update the register if the\n written value is greater than the current value of this register.\n A read from this register always reflects the current value.", + "resval": "0x0000" + }, + { + "bits": "31:16", + "name": "BYPASS_THRESH", + "desc": "This is the threshold size for the Markov health test\n running in bypass mode. This mode is active after reset for the\n first and only test run, or when this mode is programmed by firmware.\n This register must be written before the module is enabled.\n Writing to this register will only update the register if the\n written value is greater than the current value of this register.\n A read from this register always reflects the current value.", + "resval": "0x0000" + } + ] + }, + { + "name": "EXTHT_HI_THRESHOLDS", + "desc": "External health test high thresholds register", + "swaccess": "rw", + "hwaccess": "hrw", + "hwext": "true", + "hwqe": "true", + "regwen": "REGWEN", + "tags": [ + "excl:CsrNonInitTests:CsrExclWrite" + ], + "fields": [ + { + "bits": "15:0", + "name": "FIPS_THRESH", + "desc": "This is the threshold size for the external health test.\n This value is used in normal mode when entropy is being tested in\n FIPS/CC compliance mode.\n This register must be written before the module is enabled.\n Writing to this register will only update the register if the\n written value is less than the current value of this register.\n A read from this register always reflects the current value.", + "resval": "0xFFFF" + }, + { + "bits": "31:16", + "name": "BYPASS_THRESH", + "desc": "This is the threshold size for the external health test\n running in bypass mode. This mode is active after reset for the\n first and only test run, or when this mode is programmed by firmware.\n This register must be written before the module is enabled.\n Writing to this register will only update the register if the\n written value is less than the current value of this register.\n A read from this register always reflects the current value.", + "resval": "0xFFFF" + } + ] + }, + { + "name": "EXTHT_LO_THRESHOLDS", + "desc": "External health test low thresholds register", + "swaccess": "rw", + "hwaccess": "hrw", + "hwext": "true", + "hwqe": "true", + "regwen": "REGWEN", + "tags": [ + "excl:CsrNonInitTests:CsrExclWrite" + ], + "fields": [ + { + "bits": "15:0", + "name": "FIPS_THRESH", + "desc": "This is the threshold size for the external health test.\n This value is used in normal mode when entropy is being tested in\n FIPS/CC compliance mode.\n This register must be written before the module is enabled.\n Writing to this register will only update the register if the\n written value is greater than the current value of this register.\n A read from this register always reflects the current value.", + "resval": "0x0000" + }, + { + "bits": "31:16", + "name": "BYPASS_THRESH", + "desc": "This is the threshold size for the external health test\n running in bypass mode. This mode is active after reset for the\n first and only test run, or when this mode is programmed by firmware.\n This register must be written before the module is enabled.\n Writing to this register will only update the register if the\n written value is greater than the current value of this register.\n A read from this register always reflects the current value.", + "resval": "0x0000" + } + ] + }, + { + "name": "REPCNT_HI_WATERMARKS", + "desc": "Repetition count test high watermarks register", + "swaccess": "ro", + "hwaccess": "hwo", + "hwext": "true", + "tags": [ + "excl:CsrAllTests:CsrExclCheck" + ], + "fields": [ + { + "bits": "15:0", + "name": "FIPS_WATERMARK", + "desc": "High watermark value of the REPCNT test in FIPS mode." + }, + { + "bits": "31:16", + "name": "BYPASS_WATERMARK", + "desc": "High watermark value of the REPCNT test in bypass mode." + } + ] + }, + { + "name": "REPCNTS_HI_WATERMARKS", + "desc": "Repetition count symbol test high watermarks register", + "swaccess": "ro", + "hwaccess": "hwo", + "hwext": "true", + "tags": [ + "excl:CsrAllTests:CsrExclCheck" + ], + "fields": [ + { + "bits": "15:0", + "name": "FIPS_WATERMARK", + "desc": "High watermark value of the REPCNTS test in FIPS mode." + }, + { + "bits": "31:16", + "name": "BYPASS_WATERMARK", + "desc": "High watermark value of the REPCNTS test in bypass mode." + } + ] + }, + { + "name": "ADAPTP_HI_WATERMARKS", + "desc": "Adaptive proportion test high watermarks register", + "swaccess": "ro", + "hwaccess": "hwo", + "hwext": "true", + "tags": [ + "excl:CsrNonInitTests:CsrExclCheck" + ], + "fields": [ + { + "bits": "15:0", + "name": "FIPS_WATERMARK", + "desc": "High watermark value of the adaptive proportion test in FIPS mode." + }, + { + "bits": "31:16", + "name": "BYPASS_WATERMARK", + "desc": "High watermark value of the adaptive proportion test in bypass mode." + } + ] + }, + { + "name": "ADAPTP_LO_WATERMARKS", + "desc": "Adaptive proportion test low watermarks register", + "swaccess": "ro", + "hwaccess": "hwo", + "hwext": "true", + "tags": [ + "excl:CsrNonInitTests:CsrExclCheck" + ], + "fields": [ + { + "bits": "15:0", + "name": "FIPS_WATERMARK", + "desc": "Low watermark value of the adaptive proportion test in FIPS mode.", + "resval": "0xFFFF" + }, + { + "bits": "31:16", + "name": "BYPASS_WATERMARK", + "desc": "Low watermark value of the adaptive proportion test in bypass mode.", + "resval": "0xFFFF" + } + ] + }, + { + "name": "EXTHT_HI_WATERMARKS", + "desc": "External health test high watermarks register", + "swaccess": "ro", + "hwaccess": "hwo", + "hwext": "true", + "tags": [ + "excl:CsrNonInitTests:CsrExclCheck" + ], + "fields": [ + { + "bits": "15:0", + "name": "FIPS_WATERMARK", + "desc": "High watermark value of the external health test in FIPS mode." + }, + { + "bits": "31:16", + "name": "BYPASS_WATERMARK", + "desc": "High watermark value of the external health test in bypass mode." + } + ] + }, + { + "name": "EXTHT_LO_WATERMARKS", + "desc": "External health test low watermarks register", + "swaccess": "ro", + "hwaccess": "hwo", + "hwext": "true", + "tags": [ + "excl:CsrNonInitTests:CsrExclCheck" + ], + "fields": [ + { + "bits": "15:0", + "name": "FIPS_WATERMARK", + "desc": "Low watermark value of the external health test in FIPS mode.", + "resval": "0xFFFF" + }, + { + "bits": "31:16", + "name": "BYPASS_WATERMARK", + "desc": "Low watermark value of the external health test in bypass mode.", + "resval": "0xFFFF" + } + ] + }, + { + "name": "BUCKET_HI_WATERMARKS", + "desc": "Bucket test high watermarks register", + "swaccess": "ro", + "hwaccess": "hwo", + "hwext": "true", + "tags": [ + "excl:CsrNonInitTests:CsrExclCheck" + ], + "fields": [ + { + "bits": "15:0", + "name": "FIPS_WATERMARK", + "desc": "High watermark value of the bucket test in FIPS mode." + }, + { + "bits": "31:16", + "name": "BYPASS_WATERMARK", + "desc": "High watermark value of the bucket test in bypass mode." + } + ] + }, + { + "name": "MARKOV_HI_WATERMARKS", + "desc": "Markov test high watermarks register", + "swaccess": "ro", + "hwaccess": "hwo", + "hwext": "true", + "tags": [ + "excl:CsrNonInitTests:CsrExclCheck" + ], + "fields": [ + { + "bits": "15:0", + "name": "FIPS_WATERMARK", + "desc": "High watermark value of the Markov test in FIPS mode." + }, + { + "bits": "31:16", + "name": "BYPASS_WATERMARK", + "desc": "High watermark value of the Markov test in bypass mode." + } + ] + }, + { + "name": "MARKOV_LO_WATERMARKS", + "desc": "Markov test low watermarks register", + "swaccess": "ro", + "hwaccess": "hwo", + "hwext": "true", + "tags": [ + "excl:CsrNonInitTests:CsrExclCheck" + ], + "fields": [ + { + "bits": "15:0", + "name": "FIPS_WATERMARK", + "desc": "Low watermark value of the Markov test in FIPS mode.", + "resval": "0xFFFF" + }, + { + "bits": "31:16", + "name": "BYPASS_WATERMARK", + "desc": "Low watermark value of the Markov test in bypass mode.", + "resval": "0xFFFF" + } + ] + }, + { + "name": "REPCNT_TOTAL_FAILS", + "desc": "Repetition count test failure counter register", + "swaccess": "ro", + "hwaccess": "hwo", + "hwext": "true", + "fields": [ + { + "bits": "31:0", + "name": "REPCNT_TOTAL_FAILS", + "desc": "This register will hold a running count of test failures observed\n during normal operation. It will persist until cleared." + } + ] + }, + { + "name": "REPCNTS_TOTAL_FAILS", + "desc": "Repetition count symbol test failure counter register", + "swaccess": "ro", + "hwaccess": "hwo", + "hwext": "true", + "fields": [ + { + "bits": "31:0", + "name": "REPCNTS_TOTAL_FAILS", + "desc": "This register will hold a running count of test failures observed\n during normal operation. It will persist until cleared." + } + ] + }, + { + "name": "ADAPTP_HI_TOTAL_FAILS", + "desc": "Adaptive proportion high test failure counter register", + "swaccess": "ro", + "hwaccess": "hwo", + "hwext": "true", + "fields": [ + { + "bits": "31:0", + "name": "ADAPTP_HI_TOTAL_FAILS", + "desc": "This register will hold a running count of test failures observed\n during normal operation. It will persist until cleared." + } + ] + }, + { + "name": "ADAPTP_LO_TOTAL_FAILS", + "desc": "Adaptive proportion low test failure counter register", + "swaccess": "ro", + "hwaccess": "hwo", + "hwext": "true", + "fields": [ + { + "bits": "31:0", + "name": "ADAPTP_LO_TOTAL_FAILS", + "desc": "This register will hold a running count of test failures observed\n during normal operation. It will persist until cleared." + } + ] + }, + { + "name": "BUCKET_TOTAL_FAILS", + "desc": "Bucket test failure counter register", + "swaccess": "ro", + "hwaccess": "hwo", + "hwext": "true", + "fields": [ + { + "bits": "31:0", + "name": "BUCKET_TOTAL_FAILS", + "desc": "This register will hold a running count of test failures observed\n during normal operation. It will persist until cleared." + } + ] + }, + { + "name": "MARKOV_HI_TOTAL_FAILS", + "desc": "Markov high test failure counter register", + "swaccess": "ro", + "hwaccess": "hwo", + "hwext": "true", + "fields": [ + { + "bits": "31:0", + "name": "MARKOV_HI_TOTAL_FAILS", + "desc": "This register will hold a running count of test failures observed\n during normal operation. It will persist until cleared." + } + ] + }, + { + "name": "MARKOV_LO_TOTAL_FAILS", + "desc": "Markov low test failure counter register", + "swaccess": "ro", + "hwaccess": "hwo", + "hwext": "true", + "fields": [ + { + "bits": "31:0", + "name": "MARKOV_LO_TOTAL_FAILS", + "desc": "This register will hold a running count of test failures observed\n during normal operation. It will persist until cleared." + } + ] + }, + { + "name": "EXTHT_HI_TOTAL_FAILS", + "desc": "External health test high threshold failure counter register", + "swaccess": "ro", + "hwaccess": "hwo", + "hwext": "true", + "fields": [ + { + "bits": "31:0", + "name": "EXTHT_HI_TOTAL_FAILS", + "desc": "This register will hold a running count of test failures observed\n during normal operation. It will persist until cleared." + } + ] + }, + { + "name": "EXTHT_LO_TOTAL_FAILS", + "desc": "External health test low threshold failure counter register", + "swaccess": "ro", + "hwaccess": "hwo", + "hwext": "true", + "fields": [ + { + "bits": "31:0", + "name": "EXTHT_LO_TOTAL_FAILS", + "desc": "This register will hold a running count of test failures observed\n during normal operation. It will persist until cleared." + } + ] + }, + { + "name": "ALERT_THRESHOLD", + "desc": "Alert threshold register", + "swaccess": "rw", + "hwaccess": "hro", + "regwen": "REGWEN", + "tags": [ + "excl:CsrNonInitTests:CsrExclWrite" + ], + "fields": [ + { + "bits": "15:0", + "name": "ALERT_THRESHOLD", + "desc": "This is the threshold size that will signal an alert when\n value is reached. A value of zero will disable alerts.\n The default value is 2.", + "resval": "0x0002" + }, + { + "bits": "31:16", + "name": "ALERT_THRESHOLD_INV", + "desc": "This should be set to the value above, but inverted.", + "resval": "0xfffd" + } + ] + }, + { + "name": "ALERT_SUMMARY_FAIL_COUNTS", + "desc": "Alert summary failure counts register", + "swaccess": "ro", + "hwaccess": "hwo", + "hwext": "true", + "fields": [ + { + "bits": "15:0", + "name": "ANY_FAIL_COUNT", + "desc": "This field will hold a running count of\n the total alert count, which is a sum of all of the other\n counters in the !!ALERT_FAIL_COUNTS register.\n It will be reset after every\n passing test sequence. If an alert is signaled, this value\n will persist until it is cleared." + } + ] + }, + { + "name": "ALERT_FAIL_COUNTS", + "desc": "Alert failure counts register", + "swaccess": "ro", + "hwaccess": "hwo", + "hwext": "true", + "fields": [ + { + "bits": "7:4", + "name": "REPCNT_FAIL_COUNT", + "desc": "This field will hold a running count of test failures that\n contribute to the total alert count. It will be reset after every\n passing test sequence. If an alert is signaled, this value\n will persist until it is cleared." + }, + { + "bits": "11:8", + "name": "ADAPTP_HI_FAIL_COUNT", + "desc": "This field will hold a running count of test failures that\n contribute to the total alert count. It will be reset after every\n passing test sequence. If an alert is signaled, this value\n will persist until it is cleared." + }, + { + "bits": "15:12", + "name": "ADAPTP_LO_FAIL_COUNT", + "desc": "This field will hold a running count of test failures that\n contribute to the total alert count. It will be reset after every\n passing test sequence. If an alert is signaled, this value\n will persist until it is cleared." + }, + { + "bits": "19:16", + "name": "BUCKET_FAIL_COUNT", + "desc": "This field will hold a running count of test failures that\n contribute to the total alert count. It will be reset after every\n passing test sequence. If an alert is signaled, this value\n will persist until it is cleared." + }, + { + "bits": "23:20", + "name": "MARKOV_HI_FAIL_COUNT", + "desc": "This field will hold a running count of test failures that\n contribute to the total alert count. It will be reset after every\n passing test sequence. If an alert is signaled, this value\n will persist until it is cleared." + }, + { + "bits": "27:24", + "name": "MARKOV_LO_FAIL_COUNT", + "desc": "This field will hold a running count of test failures that\n contribute to the total alert count. It will be reset after every\n passing test sequence. If an alert is signaled, this value\n will persist until it is cleared." + }, + { + "bits": "31:28", + "name": "REPCNTS_FAIL_COUNT", + "desc": "This field will hold a running count of test failures that\n contribute to the total alert count. It will be reset after every\n passing test sequence. If an alert is signaled, this value\n will persist until it is cleared." + } + ] + }, + { + "name": "EXTHT_FAIL_COUNTS", + "desc": "External health test alert failure counts register", + "swaccess": "ro", + "hwaccess": "hwo", + "hwext": "true", + "fields": [ + { + "bits": "3:0", + "name": "EXTHT_HI_FAIL_COUNT", + "desc": "This field will hold a running count of test failures that\n contribute to the total alert count. It will be reset after every\n passing test sequence. If an alert is signaled, this value\n will persist until it is cleared." + }, + { + "bits": "7:4", + "name": "EXTHT_LO_FAIL_COUNT", + "desc": "This field will hold a running count of test failures that\n contribute to the total alert count. It will be reset after every\n passing test sequence. If an alert is signaled, this value\n will persist until it is cleared." + } + ] + }, + { + "name": "FW_OV_CONTROL", + "desc": "Firmware override control register", + "swaccess": "rw", + "hwaccess": "hro", + "regwen": "REGWEN", + "tags": [ + "excl:CsrAllTests:CsrExclAll" + ], + "fields": [ + { + "bits": "3:0", + "name": "FW_OV_MODE", + "desc": "Setting this field to kMultiBitBool4True will put the entropy flow in firmware override mode.\nIn this mode, firmware can monitor the post-health test entropy by reading\nthe observe FIFO. This function also requires that the otp_en_entropy_src_fw_over\ninput vector is set to the enable encoding.", + "mubi": true, + "resval": false + }, + { + "bits": "7:4", + "name": "FW_OV_ENTROPY_INSERT", + "desc": "Setting this field to kMultiBitBool4True will switch the input into the pre-conditioner\npacker FIFO. Firmware can directly write into the packer FIFO, enabling\nthe ability to insert entropy bits back into the hardware flow. Firmware\ncan read data from the health check packer FIFO, then do optional health\nchecks or optional conditioning, then insert the results back into the flow.\nAlso, the !!FW_OV_CONTROL.FW_OV_MODE bit must be set.", + "mubi": true, + "resval": false + } + ] + }, + { + "name": "FW_OV_SHA3_START", + "desc": "Firmware override sha3 block start control register", + "swaccess": "rw", + "hwaccess": "hro", + "tags": [ + "excl:CsrAllTests:CsrExclAll" + ], + "fields": [ + { + "bits": "3:0", + "name": "FW_OV_INSERT_START", + "desc": "Setting this field to kMultiBitBool4True will instruct the ENTROPY_SRC main state machine\nto start the SHA3 process and be ready to accept entropy data. This field should\nbe set prior to writting the FW_OV_WR_DATA register. Once all data has been written,\nthis field should be set to kMultiBitBool4False. Once that happened, the SHA3 block will finish\nprocessing and push the result into the ESFINAL FIFO.\n\nNote that clearing this bit to kMultiBitBool4False while there is still unprocessed\nentropy in the !!FW_OV_WR_DATA will start the SHA3 engine before data can be added\nto the input message, and will also signal a recoverable alert in\n!!RECOV_ALERT_STS.ES_FW_OV_DISABLE_ALERT. To avoid this, check that\n!!FW_OV_WR_FIFO_FULL is clear before setting this field to kMultiBitBool4False.", + "mubi": true, + "resval": false + } + ] + }, + { + "name": "FW_OV_WR_FIFO_FULL", + "desc": "Firmware override FIFO write full status register", + "swaccess": "ro", + "hwaccess": "hwo", + "hwext": "true", + "fields": [ + { + "bits": "0", + "name": "FW_OV_WR_FIFO_FULL", + "desc": "\"When this bit is clear, writes to the FW_OV_WR_DATA register are allowed.\nIf this bit is set, it is the equivalent to a FIFO full condition, and writes\nto the FW_OV_WR_DATA register must be delayed until this bit is reset." + } + ] + }, + { + "name": "FW_OV_RD_FIFO_OVERFLOW", + "desc": "Firmware override Observe FIFO overflow status", + "swaccess": "ro", + "hwaccess": "hwo", + "hwext": "false", + "fields": [ + { + "bits": "0", + "name": "FW_OV_RD_FIFO_OVERFLOW", + "desc": "This bit is set by hardware whenever RNG data is lost due to an overflow condition\nin the Observe FIFO. The RNG data rate is slow enough that firmware should always\nbe able to keep up. This register meanwhile provides an additional check to confirm\nthat bytes read from the !!FW_OV_RD_DATA register represent contiguous RNG samples.\nIf an overflow event occurs, this bit is cleared by hardware as soon as the FIFO is emptied." + } + ] + }, + { + "name": "FW_OV_RD_DATA", + "desc": "Firmware override Observe FIFO read register", + "swaccess": "ro", + "hwaccess": "hrw", + "hwext": "true", + "hwre": "true", + "fields": [ + { + "bits": "31:0", + "desc": "A read of this register pops and returns the top of the Observe FIFO." + } + ] + }, + { + "name": "FW_OV_WR_DATA", + "desc": "Firmware override FIFO write register", + "swaccess": "wo", + "hwaccess": "hro", + "hwext": "true", + "hwqe": "true", + "fields": [ + { + "bits": "31:0", + "desc": "A write to this register will insert entropy back into the entropy source\nmodule flow. Both !!FW_OV_CONTROL.FW_OV_MODE and !!FW_OV_CONTROL.FW_OV_ENTROPY_INSERT bits need to be set\nto enable the insertion." + } + ] + }, + { + "name": "OBSERVE_FIFO_THRESH", + "desc": "Observe FIFO threshold register", + "swaccess": "rw", + "hwaccess": "hro", + "regwen": "REGWEN", + "fields": [ + { + "bits": "6:0", + "desc": "This field will set the threshold that the depth of the Observe FIFO\nwill be compared with when setting the interrupt status bit.\nNote: a value of zero is reserved and not to be used.", + "resval": "0x20" + } + ] + }, + { + "name": "OBSERVE_FIFO_DEPTH", + "desc": "Observe FIFO depth register", + "swaccess": "ro", + "hwaccess": "hwo", + "hwext": "true", + "fields": [ + { + "bits": "6:0", + "desc": "This field will hold the current depth of the Observe FIFO." + } + ] + }, + { + "name": "DEBUG_STATUS", + "desc": "Debug status register", + "swaccess": "ro", + "hwaccess": "hwo", + "hwext": "true", + "fields": [ + { + "bits": "2:0", + "name": "ENTROPY_FIFO_DEPTH", + "desc": "This is the depth of the entropy source FIFO." + }, + { + "bits": "5:3", + "name": "SHA3_FSM", + "desc": "This is the SHA3 finite state machine current state." + }, + { + "bits": "6", + "name": "SHA3_BLOCK_PR", + "desc": "This is the SHA3 block processed signal current state." + }, + { + "bits": "7", + "name": "SHA3_SQUEEZING", + "desc": "This is the SHA3 squeezing signal current state." + }, + { + "bits": "8", + "name": "SHA3_ABSORBED", + "desc": "This is the SHA3 absorbed signal current state." + }, + { + "bits": "9", + "name": "SHA3_ERR", + "desc": "This is a logic-or of all of the SHA3 error signals." + }, + { + "bits": "16", + "name": "MAIN_SM_IDLE", + "desc": "The entropy_src main state machine is in the idle state.", + "resval": 1 + }, + { + "bits": "17", + "name": "MAIN_SM_BOOT_DONE", + "desc": "The entropy_src main state machine is in the boot phase done state." + } + ] + }, + { + "name": "RECOV_ALERT_STS", + "desc": "Recoverable alert status register", + "swaccess": "rw0c", + "hwaccess": "hwo", + "fields": [ + { + "bits": "0", + "name": "FIPS_ENABLE_FIELD_ALERT", + "desc": "This bit is set when the FIPS_ENABLE field in the !!CONF register is set to\na value other than kMultiBitBool4False or kMultiBitBool4True.\nWriting a zero resets this status bit." + }, + { + "bits": "1", + "name": "ENTROPY_DATA_REG_EN_FIELD_ALERT", + "desc": "This bit is set when the ENTROPY_DATA_REG_ENABLE field in the !!CONF register is set to\na value other than kMultiBitBool4False or kMultiBitBool4True.\nWriting a zero resets this status bit." + }, + { + "bits": "2", + "name": "MODULE_ENABLE_FIELD_ALERT", + "desc": "This bit is set when the MODULE_ENABLE field in the !!MODULE_ENABLE register is set to\na value other than kMultiBitBool4False or kMultiBitBool4True.\nWriting a zero resets this status bit." + }, + { + "bits": "3", + "name": "THRESHOLD_SCOPE_FIELD_ALERT", + "desc": "This bit is set when the THRESHOLD_SCOPE field in the !!CONF register is set to\na value other than kMultiBitBool4False or kMultiBitBool4True.\nWriting a zero resets this status bit." + }, + { + "bits": "5", + "name": "RNG_BIT_ENABLE_FIELD_ALERT", + "desc": "This bit is set when the RNG_BIT_ENABLE field in the !!CONF register is set to\na value other than kMultiBitBool4False or kMultiBitBool4True.\nWriting a zero resets this status bit." + }, + { + "bits": "7", + "name": "FW_OV_SHA3_START_FIELD_ALERT", + "desc": "This bit is set when the FW_OV_SHA3_START field in the !!FW_OV_SHA3_START register is set to\na value other than kMultiBitBool4False or kMultiBitBool4True.\nWriting a zero resets this status bit." + }, + { + "bits": "8", + "name": "FW_OV_MODE_FIELD_ALERT", + "desc": "This bit is set when the FW_OV_MODE field in the !!FW_OV_CONTROL register is set to\na value other than kMultiBitBool4False or kMultiBitBool4True.\nWriting a zero resets this status bit." + }, + { + "bits": "9", + "name": "FW_OV_ENTROPY_INSERT_FIELD_ALERT", + "desc": "This bit is set when the FW_OV_ENTROPY_INSERT field in the !!FW_OV_CONTROL register is set to\na value other than kMultiBitBool4False or kMultiBitBool4True.\nWriting a zero resets this status bit." + }, + { + "bits": "10", + "name": "ES_ROUTE_FIELD_ALERT", + "desc": "This bit is set when the ES_ROUTE field in the !!ENTROPY_CONTROL register is set to\na value other than kMultiBitBool4False or kMultiBitBool4True.\nWriting a zero resets this status bit." + }, + { + "bits": "11", + "name": "ES_TYPE_FIELD_ALERT", + "desc": "This bit is set when the ES_TYPE field in the !!ENTROPY_CONTROL register is set to\na value other than kMultiBitBool4False or kMultiBitBool4True.\nWriting a zero resets this status bit." + }, + { + "bits": "12", + "name": "ES_MAIN_SM_ALERT", + "desc": "This bit is set when the main state machine detects a threshhold failure state.\nWriting a zero resets this status bit." + }, + { + "bits": "13", + "name": "ES_BUS_CMP_ALERT", + "desc": "This bit is set when the interal entropy bus value is equal to the prior\nvalid value on the bus, indicating a possible attack.\nWriting a zero resets this status bit." + }, + { + "bits": "14", + "name": "ES_THRESH_CFG_ALERT", + "desc": "This bit is set when the !!ALERT_THRESHOLD register is not configured properly.\nThe upper field must be the exact inverse of the lower field.\nWriting a zero resets this status bit." + }, + { + "bits": "15", + "name": "ES_FW_OV_WR_ALERT", + "desc": "This bit is set when the packer FIFO has been written but was full at the time,\nand in both FW_OV_MODE and FW_OV_ENTROPY_INSERT modes.\nThis alert would normally be the result of not monitoring the !!FW_OV_WR_FIFO_FULL\nregister before each write to the !!FW_OV_WR_DATA register.\nWriting a zero resets this status bit." + }, + { + "bits": "16", + "name": "ES_FW_OV_DISABLE_ALERT", + "desc": "This bit is set when !!FW_OV_SHA3_START has been set to MuBi4 False, without\nwaiting for the FW_OV packer FIFO to clear. The final entropy entry in the FIFO\nwill not be included in the SHA3 digest. (Rather it will be added to the\nsubsequent SHA3 digest.) To avoid this alert, monitor !!FW_OV_WR_FIFO_FULL before\nclearing !!FW_OV_SHA3_START. This alert only applies when both FW_OV_MODE and\nFW_OV_ENTROPY_INSERT are set to MuBi4True.\nWriting a zero resets this status bit." + } + ] + }, + { + "name": "ERR_CODE", + "desc": "Hardware detection of error conditions status register", + "swaccess": "ro", + "hwaccess": "hwo", + "fields": [ + { + "bits": "0", + "name": "SFIFO_ESRNG_ERR", + "desc": "This bit will be set to one when an error has been detected for the\nesrng FIFO. The type of error is reflected in the type status\nbits (bits 28 through 30 of this register).\nThis bit will stay set until the next reset." + }, + { + "bits": "1", + "name": "SFIFO_OBSERVE_ERR", + "desc": "This bit will be set to one when an error has been detected for the\nobserve FIFO. The type of error is reflected in the type status\nbits (bits 28 through 30 of this register).\nThis bit will stay set until the next reset." + }, + { + "bits": "2", + "name": "SFIFO_ESFINAL_ERR", + "desc": "This bit will be set to one when an error has been detected for the\nesfinal FIFO. The type of error is reflected in the type status\nbits (bits 28 through 30 of this register).\nThis bit will stay set until the next reset." + }, + { + "bits": "20", + "name": "ES_ACK_SM_ERR", + "desc": "This bit will be set to one when an illegal state has been detected for the\nES ack stage state machine. This error will signal a fatal alert, and also\nan interrupt if enabled.\nThis bit will stay set until the next reset." + }, + { + "bits": "21", + "name": "ES_MAIN_SM_ERR", + "desc": "This bit will be set to one when an illegal state has been detected for the\nES main stage state machine. This error will signal a fatal alert, and also\nan interrupt if enabled.\nThis bit will stay set until the next reset." + }, + { + "bits": "22", + "name": "ES_CNTR_ERR", + "desc": "This bit will be set to one when a hardened counter has detected an error\ncondition. This error will signal a fatal alert, and also\nan interrupt if enabled.\nThis bit will stay set until the next reset." + }, + { + "bits": "23", + "name": "SHA3_STATE_ERR", + "desc": "This bit will be set to one when a SHA3 state error has been detected.\nThis error will signal a fatal alert, and also an interrupt if enabled.\nThis bit will stay set until the next reset." + }, + { + "bits": "24", + "name": "SHA3_RST_STORAGE_ERR", + "desc": "This bit will be set to one when a SHA3_RST_STORAGE_ERR signal being\nactive has been detected.\nThis error will signal a fatal alert, and also an interrupt if enabled.\nThis bit will stay set until the next reset." + }, + { + "bits": "28", + "name": "FIFO_WRITE_ERR", + "desc": "This bit will be set to one when any of the source bits (bits 0 through 1 of this\nthis register) are asserted as a result of an error pulse generated from\nany full FIFO that has been recieved a write pulse.\nThis bit will stay set until the next reset." + }, + { + "bits": "29", + "name": "FIFO_READ_ERR", + "desc": "This bit will be set to one when any of the source bits (bits 0 through 1 of this\nthis register) are asserted as a result of an error pulse generated from\nany empty FIFO that has recieved a read pulse.\nThis bit will stay set until the next reset." + }, + { + "bits": "30", + "name": "FIFO_STATE_ERR", + "desc": "This bit will be set to one when any of the source bits (bits 0 through 1 of this\nthis register) are asserted as a result of an error pulse generated from\nany FIFO where both the empty and full status bits are set.\nThis bit will stay set until the next reset." + } + ] + }, + { + "name": "ERR_CODE_TEST", + "desc": "Test error conditions register", + "swaccess": "rw", + "hwaccess": "hro", + "hwqe": "true", + "tags": [ + "excl:CsrNonInitTests:CsrExclWrite" + ], + "fields": [ + { + "bits": "4:0", + "name": "ERR_CODE_TEST", + "desc": "Setting this field will set the bit number for which an error\nwill be forced in the hardware. This bit number is that same one\nfound in the !!ERR_CODE register. The action of writing this\nregister will force an error pulse. The sole purpose of this\nregister is to test that any error properly propagates to either\nan interrupt or an alert." + } + ] + }, + { + "name": "MAIN_SM_STATE", + "desc": "Main state machine state debug register", + "swaccess": "ro", + "hwaccess": "hwo", + "fields": [ + { + "bits": "8:0", + "name": "MAIN_SM_STATE", + "desc": "This is the state of the ENTROPY_SRC main state machine.\nSee the RTL file `entropy_src_main_sm` for the meaning of the values.", + "resval": "0xf5" + } + ] + } + ] +} \ No newline at end of file diff --git a/src/fuse_ctrl/data/entropy_src.rdl b/src/fuse_ctrl/data/entropy_src.rdl new file mode 100644 index 0000000..200bf5d --- /dev/null +++ b/src/fuse_ctrl/data/entropy_src.rdl @@ -0,0 +1,965 @@ +addrmap entropy_src { + reg { + field { + sw = rw; + onwrite = woclr; + desc = "Asserted when entropy source bits are available."; + } ES_ENTROPY_VALID[0:0]; + field { + sw = rw; + onwrite = woclr; + desc = "Asserted when the alert count has been met."; + } ES_HEALTH_TEST_FAILED[1:1]; + field { + sw = rw; + onwrite = woclr; + desc = "Asserted when the observe FIFO has filled to the threshold level."; + } ES_OBSERVE_FIFO_READY[2:2]; + field { + sw = rw; + onwrite = woclr; + desc = "Asserted when a FIFO error occurs, or if an illegal state machine state is reached."; + } ES_FATAL_ERR[3:3]; + } INTERRUPT_STATE @ 0x0; + reg { + field { + sw = rw; + onwrite = woclr; + desc = "Enable interrupt when es_entropy_valid is set."; + } ES_ENTROPY_VALID[0:0]; + field { + sw = rw; + onwrite = woclr; + desc = "Enable interrupt when es_health_test_failed is set."; + } ES_HEALTH_TEST_FAILED[1:1]; + field { + sw = rw; + onwrite = woclr; + desc = "Enable interrupt when es_observe_fifo_ready is set."; + } ES_OBSERVE_FIFO_READY[2:2]; + field { + sw = rw; + onwrite = woclr; + desc = "Enable interrupt when es_fatal_err is set."; + } ES_FATAL_ERR[3:3]; + } INTERRUPT_ENABLE @ 0x4; + reg { + field { + sw = w; + desc = "Write 1 to force es_entropy_valid to 1."; + } ES_ENTROPY_VALID[0:0]; + field { + sw = w; + desc = "Write 1 to force es_health_test_failed to 1."; + } ES_HEALTH_TEST_FAILED[1:1]; + field { + sw = w; + desc = "Write 1 to force es_observe_fifo_ready to 1."; + } ES_OBSERVE_FIFO_READY[2:2]; + field { + sw = w; + desc = "Write 1 to force es_fatal_err to 1."; + } ES_FATAL_ERR[3:3]; + } INTERRUPT_TEST @ 0x8; + reg { + field { + sw = w; + desc = "Write 1 to trigger one alert event of this kind."; + } RECOV_ALERT[0:0]; + field { + sw = w; + desc = "Write 1 to trigger one alert event of this kind."; + } FATAL_ALERT[1:1]; + } ALERT_TEST @ 0xC; + reg { + field { + desc = "When true, the !!MODULE_ENABLE register can be modified. + When false, it becomes read-only."; + sw = rw; + onwrite = woclr; + } ME_REGWEN[0:0] = 0x1; + } ME_REGWEN @ 0x10; + reg { + field { + desc = "When this bit true and the MODULE_ENABLE field is false, + the REGWEN write enable bit read as true, and is distributed to + all associated control and threshold registers. + When false, these registers become read-only."; + sw = rw; + onwrite = woclr; + } SW_REGUPD[0:0] = 0x1; + } SW_REGUPD @ 0x14; + reg { + field { + desc = "This read-only write enable bit will allow write access + to control and theshold registers that are associated with this bit, + but only when the MODULE_ENABLE field is set to kMultiBitBool4False and the + SW_REGUPD write enable bit is set to true. + When read as false, these registers become read-only."; + sw = r; + } REGWEN[0:0] = 0x1; + } REGWEN @ 0x18; + reg { + field { + desc = "Read of this register shows the ABI of this block."; + sw = r; + } ABI_REVISION[7:0] = 0x3; + field { + desc = "Read of this register shows the revision of this block."; + sw = r; + } HW_REVISION[15:8] = 0x3; + field { + desc = "Read of this register shows the type of chip using this block."; + sw = r; + } CHIP_TYPE[23:16] = 0x1; + } REV @ 0x1C; + reg { + field { + desc = "Setting this field to kMultiBitBool4True will enable the ENTROPY_SRC module. Setting + this field to kMultiBitBool4False will effectively reset the module. The modules of + the entropy complex may only be enabled and disabled in a specific order, see + Programmers Guide for details."; + sw = rw; + } MODULE_ENABLE[3:0] = 0x9; + } MODULE_ENABLE @ 0x20; + reg { + field { + desc = "Setting this field to kMultiBitBool4True will enable FIPS qualified entropy to be + generated."; + sw = rw; + } FIPS_ENABLE[3:0] = 0x9; + field { + desc = "Setting this field to kMultiBitBool4True will enable reading entropy values from the + ENTROPY_DATA register. This function also requires that the otp_en_entropy_src_fw_read + input vector is set to the enable encoding."; + sw = rw; + } ENTROPY_DATA_REG_ENABLE[7:4] = 0x9; + field { + desc = "This field controls the scope (either by-line or by-sum) of the health checks. + If set to kMultiBitBool4True, the Adaptive Proportion and Markov Tests will accumulate all + RNG input lines into a single score, and thresholds will be applied to the sum all + the entropy input lines. If set to kMultiBitBool4False, the RNG input lines are all scored + individually. A statistical deviation in any one input line, be it due to + coincidence or failure, will force rejection of the sample, and count toward the + total alert count."; + sw = rw; + } THRESHOLD_SCOPE[15:12] = 0x9; + field { + desc = "Setting this field to kMultiBitBool4True enables the single RNG bit mode, where only + one bit is sampled."; + sw = rw; + } RNG_BIT_ENABLE[23:20] = 0x9; + field { + desc = "When the above bit iset, this field selects which bit from the RNG bus will + be processed when in single RNG bit mode. + This two bit field selects the RNG bit stream: + 0b00: RNG bit 0 + 0b01: RNG bit 1 + 0b10: RNG bit 2 + 0b11: RNG bit 3"; + sw = rw; + } RNG_BIT_SEL[25:24]; + } CONF @ 0x24; + reg { + field { + desc = "Setting this field to kMultiBitBool4True routes the generated entropy value to the ENTROPY_DATA + register to be read by firmware. When this field is kMultiBitBool4False, the generated + entropy will be forwarded out of this module to the hardware interface."; + sw = rw; + } ES_ROUTE[3:0] = 0x9; + field { + desc = "Setting this field to kMultiBitBool4True will bypass the conditioning logic and bring raw entropy + data to the ENTROPY_DATA register. When kMultiBitBool4False, FIPS compliant entropy + will be brought the ENTROPY_DATA register, after being conditioned."; + sw = rw; + } ES_TYPE[7:4] = 0x9; + } ENTROPY_CONTROL @ 0x28; + reg { + field { + desc = "A read of this register provides generated entropy bits to firmware."; + sw = r; + } ENTROPY_DATA[31:0]; + } ENTROPY_DATA @ 0x2C; + reg { + field { + desc = "This is the window size for all health tests. This value is used in normal mode + when entropy is being tested in FIPS/CC compliance mode. + The default value is (2048 bits * 1 clock/4 bits);"; + sw = rw; + } FIPS_WINDOW[15:0] = 0x200; + field { + desc = "This is the window size for all health tests when running in bypass mode. This mode + is active after reset for the first and only test run, or when this mode is + programmed by firmware. + The default value is (384 bits * 1 clock/4 bits); + + Note that currently only a window size of 384 is supported and tested (this + corresponds to the register default value 0x60). Do not use any other values, + unless you know what you are doing."; + sw = rw; + } BYPASS_WINDOW[31:16] = 0x60; + } HEALTH_TEST_WINDOWS @ 0x30; + reg { + field { + desc = "This is the threshold size for the repetition count health test. + This value is used in normal mode when entropy is being tested in + FIPS/CC compliance mode. + This register must be written before the module is enabled. + Writing to this register will only update the register if the + written value is less than the current value of this register. + A read from this register always reflects the current value."; + sw = rw; + } FIPS_THRESH[15:0] = 0xFFFF; + field { + desc = "This is the threshold size for the repetition count health test + running in bypass mode. This mode is active after reset for the + first and only test run, or when this mode is programmed by firmware. + This register must be written before the module is enabled. + Writing to this register will only update the register if the + written value is less than the current value of this register. + A read from this register always reflects the current value."; + sw = rw; + } BYPASS_THRESH[31:16] = 0xFFFF; + } REPCNT_THRESHOLDS @ 0x34; + reg { + field { + desc = "This is the threshold size for the repetition count symbol health test. + This value is used in normal mode when entropy is being tested in + FIPS/CC compliance mode. + This register must be written before the module is enabled. + Writing to this register will only update the register if the + written value is less than the current value of this register. + A read from this register always reflects the current value."; + sw = rw; + } FIPS_THRESH[15:0] = 0xFFFF; + field { + desc = "This is the threshold size for the repetition count symbol health test + running in bypass mode. This mode is active after reset for the + first and only test run, or when this mode is programmed by firmware. + This register must be written before the module is enabled. + Writing to this register will only update the register if the + written value is less than the current value of this register. + A read from this register always reflects the current value."; + sw = rw; + } BYPASS_THRESH[31:16] = 0xFFFF; + } REPCNTS_THRESHOLDS @ 0x38; + reg { + field { + desc = "This is the threshold size for the adaptive proportion health test. + This value is used in normal mode when entropy is being tested in + FIPS/CC compliance mode. + This register must be written before the module is enabled. + Writing to this register will only update the register if the + written value is less than the current value of this register. + A read from this register always reflects the current value."; + sw = rw; + } FIPS_THRESH[15:0] = 0xFFFF; + field { + desc = "This is the threshold size for the adaptive proportion health test + running in bypass mode. This mode is active after reset for the + first and only test run, or when this mode is programmed by firmware. + This register must be written before the module is enabled. + Writing to this register will only update the register if the + written value is less than the current value of this register. + A read from this register always reflects the current value."; + sw = rw; + } BYPASS_THRESH[31:16] = 0xFFFF; + } ADAPTP_HI_THRESHOLDS @ 0x3C; + reg { + field { + desc = "This is the threshold size for the adaptive proportion health test. + This value is used in normal mode when entropy is being tested in + FIPS/CC compliance mode. + This register must be written before the module is enabled. + Writing to this register will only update the register if the + written value is greater than the current value of this register. + A read from this register always reflects the current value."; + sw = rw; + } FIPS_THRESH[15:0] = 0x0; + field { + desc = "This is the threshold size for the adaptive proportion health test + running in bypass mode. This mode is active after reset for the + first and only test run, or when this mode is programmed by firmware. + This register must be written before the module is enabled. + Writing to this register will only update the register if the + written value is greater than the current value of this register. + A read from this register always reflects the current value."; + sw = rw; + } BYPASS_THRESH[31:16] = 0x0; + } ADAPTP_LO_THRESHOLDS @ 0x40; + reg { + field { + desc = "This is the threshold size for the bucket health test. + This value is used in normal mode when entropy is being tested in + FIPS/CC compliance mode. + This register must be written before the module is enabled. + Writing to this register will only update the register if the + written value is less than the current value of this register. + A read from this register always reflects the current value."; + sw = rw; + } FIPS_THRESH[15:0] = 0xFFFF; + field { + desc = "This is the threshold size for the bucket health test + running in bypass mode. This mode is active after reset for the + first and only test run, or when this mode is programmed by firmware. + This register must be written before the module is enabled. + Writing to this register will only update the register if the + written value is less than the current value of this register. + A read from this register always reflects the current value."; + sw = rw; + } BYPASS_THRESH[31:16] = 0xFFFF; + } BUCKET_THRESHOLDS @ 0x44; + reg { + field { + desc = "This is the threshold size for the Markov health test. + This value is used in normal mode when entropy is being tested in + FIPS/CC compliance mode. + This register must be written before the module is enabled. + Writing to this register will only update the register if the + written value is less than the current value of this register. + A read from this register always reflects the current value."; + sw = rw; + } FIPS_THRESH[15:0] = 0xFFFF; + field { + desc = "This is the threshold size for the Markov health test + running in bypass mode. This mode is active after reset for the + first and only test run, or when this mode is programmed by firmware. + This register must be written before the module is enabled. + Writing to this register will only update the register if the + written value is less than the current value of this register. + A read from this register always reflects the current value."; + sw = rw; + } BYPASS_THRESH[31:16] = 0xFFFF; + } MARKOV_HI_THRESHOLDS @ 0x48; + reg { + field { + desc = "This is the threshold size for the Markov health test. + This value is used in normal mode when entropy is being tested in + FIPS/CC compliance mode. + This register must be written before the module is enabled. + Writing to this register will only update the register if the + written value is greater than the current value of this register. + A read from this register always reflects the current value."; + sw = rw; + } FIPS_THRESH[15:0] = 0x0; + field { + desc = "This is the threshold size for the Markov health test + running in bypass mode. This mode is active after reset for the + first and only test run, or when this mode is programmed by firmware. + This register must be written before the module is enabled. + Writing to this register will only update the register if the + written value is greater than the current value of this register. + A read from this register always reflects the current value."; + sw = rw; + } BYPASS_THRESH[31:16] = 0x0; + } MARKOV_LO_THRESHOLDS @ 0x4C; + reg { + field { + desc = "This is the threshold size for the external health test. + This value is used in normal mode when entropy is being tested in + FIPS/CC compliance mode. + This register must be written before the module is enabled. + Writing to this register will only update the register if the + written value is less than the current value of this register. + A read from this register always reflects the current value."; + sw = rw; + } FIPS_THRESH[15:0] = 0xFFFF; + field { + desc = "This is the threshold size for the external health test + running in bypass mode. This mode is active after reset for the + first and only test run, or when this mode is programmed by firmware. + This register must be written before the module is enabled. + Writing to this register will only update the register if the + written value is less than the current value of this register. + A read from this register always reflects the current value."; + sw = rw; + } BYPASS_THRESH[31:16] = 0xFFFF; + } EXTHT_HI_THRESHOLDS @ 0x50; + reg { + field { + desc = "This is the threshold size for the external health test. + This value is used in normal mode when entropy is being tested in + FIPS/CC compliance mode. + This register must be written before the module is enabled. + Writing to this register will only update the register if the + written value is greater than the current value of this register. + A read from this register always reflects the current value."; + sw = rw; + } FIPS_THRESH[15:0] = 0x0; + field { + desc = "This is the threshold size for the external health test + running in bypass mode. This mode is active after reset for the + first and only test run, or when this mode is programmed by firmware. + This register must be written before the module is enabled. + Writing to this register will only update the register if the + written value is greater than the current value of this register. + A read from this register always reflects the current value."; + sw = rw; + } BYPASS_THRESH[31:16] = 0x0; + } EXTHT_LO_THRESHOLDS @ 0x54; + reg { + field { + desc = "High watermark value of the REPCNT test in FIPS mode."; + sw = r; + } FIPS_WATERMARK[15:0]; + field { + desc = "High watermark value of the REPCNT test in bypass mode."; + sw = r; + } BYPASS_WATERMARK[31:16]; + } REPCNT_HI_WATERMARKS @ 0x58; + reg { + field { + desc = "High watermark value of the REPCNTS test in FIPS mode."; + sw = r; + } FIPS_WATERMARK[15:0]; + field { + desc = "High watermark value of the REPCNTS test in bypass mode."; + sw = r; + } BYPASS_WATERMARK[31:16]; + } REPCNTS_HI_WATERMARKS @ 0x5C; + reg { + field { + desc = "High watermark value of the adaptive proportion test in FIPS mode."; + sw = r; + } FIPS_WATERMARK[15:0]; + field { + desc = "High watermark value of the adaptive proportion test in bypass mode."; + sw = r; + } BYPASS_WATERMARK[31:16]; + } ADAPTP_HI_WATERMARKS @ 0x60; + reg { + field { + desc = "Low watermark value of the adaptive proportion test in FIPS mode."; + sw = r; + } FIPS_WATERMARK[15:0] = 0xFFFF; + field { + desc = "Low watermark value of the adaptive proportion test in bypass mode."; + sw = r; + } BYPASS_WATERMARK[31:16] = 0xFFFF; + } ADAPTP_LO_WATERMARKS @ 0x64; + reg { + field { + desc = "High watermark value of the external health test in FIPS mode."; + sw = r; + } FIPS_WATERMARK[15:0]; + field { + desc = "High watermark value of the external health test in bypass mode."; + sw = r; + } BYPASS_WATERMARK[31:16]; + } EXTHT_HI_WATERMARKS @ 0x68; + reg { + field { + desc = "Low watermark value of the external health test in FIPS mode."; + sw = r; + } FIPS_WATERMARK[15:0] = 0xFFFF; + field { + desc = "Low watermark value of the external health test in bypass mode."; + sw = r; + } BYPASS_WATERMARK[31:16] = 0xFFFF; + } EXTHT_LO_WATERMARKS @ 0x6C; + reg { + field { + desc = "High watermark value of the bucket test in FIPS mode."; + sw = r; + } FIPS_WATERMARK[15:0]; + field { + desc = "High watermark value of the bucket test in bypass mode."; + sw = r; + } BYPASS_WATERMARK[31:16]; + } BUCKET_HI_WATERMARKS @ 0x70; + reg { + field { + desc = "High watermark value of the Markov test in FIPS mode."; + sw = r; + } FIPS_WATERMARK[15:0]; + field { + desc = "High watermark value of the Markov test in bypass mode."; + sw = r; + } BYPASS_WATERMARK[31:16]; + } MARKOV_HI_WATERMARKS @ 0x74; + reg { + field { + desc = "Low watermark value of the Markov test in FIPS mode."; + sw = r; + } FIPS_WATERMARK[15:0] = 0xFFFF; + field { + desc = "Low watermark value of the Markov test in bypass mode."; + sw = r; + } BYPASS_WATERMARK[31:16] = 0xFFFF; + } MARKOV_LO_WATERMARKS @ 0x78; + reg { + field { + desc = "This register will hold a running count of test failures observed + during normal operation. It will persist until cleared."; + sw = r; + } REPCNT_TOTAL_FAILS[31:0]; + } REPCNT_TOTAL_FAILS @ 0x7C; + reg { + field { + desc = "This register will hold a running count of test failures observed + during normal operation. It will persist until cleared."; + sw = r; + } REPCNTS_TOTAL_FAILS[31:0]; + } REPCNTS_TOTAL_FAILS @ 0x80; + reg { + field { + desc = "This register will hold a running count of test failures observed + during normal operation. It will persist until cleared."; + sw = r; + } ADAPTP_HI_TOTAL_FAILS[31:0]; + } ADAPTP_HI_TOTAL_FAILS @ 0x84; + reg { + field { + desc = "This register will hold a running count of test failures observed + during normal operation. It will persist until cleared."; + sw = r; + } ADAPTP_LO_TOTAL_FAILS[31:0]; + } ADAPTP_LO_TOTAL_FAILS @ 0x88; + reg { + field { + desc = "This register will hold a running count of test failures observed + during normal operation. It will persist until cleared."; + sw = r; + } BUCKET_TOTAL_FAILS[31:0]; + } BUCKET_TOTAL_FAILS @ 0x8C; + reg { + field { + desc = "This register will hold a running count of test failures observed + during normal operation. It will persist until cleared."; + sw = r; + } MARKOV_HI_TOTAL_FAILS[31:0]; + } MARKOV_HI_TOTAL_FAILS @ 0x90; + reg { + field { + desc = "This register will hold a running count of test failures observed + during normal operation. It will persist until cleared."; + sw = r; + } MARKOV_LO_TOTAL_FAILS[31:0]; + } MARKOV_LO_TOTAL_FAILS @ 0x94; + reg { + field { + desc = "This register will hold a running count of test failures observed + during normal operation. It will persist until cleared."; + sw = r; + } EXTHT_HI_TOTAL_FAILS[31:0]; + } EXTHT_HI_TOTAL_FAILS @ 0x98; + reg { + field { + desc = "This register will hold a running count of test failures observed + during normal operation. It will persist until cleared."; + sw = r; + } EXTHT_LO_TOTAL_FAILS[31:0]; + } EXTHT_LO_TOTAL_FAILS @ 0x9C; + reg { + field { + desc = "This is the threshold size that will signal an alert when + value is reached. A value of zero will disable alerts. + The default value is 2."; + sw = rw; + } ALERT_THRESHOLD[15:0] = 0x2; + field { + desc = "This should be set to the value above, but inverted."; + sw = rw; + } ALERT_THRESHOLD_INV[31:16] = 0xFFFD; + } ALERT_THRESHOLD @ 0xA0; + reg { + field { + desc = "This field will hold a running count of + the total alert count, which is a sum of all of the other + counters in the !!ALERT_FAIL_COUNTS register. + It will be reset after every + passing test sequence. If an alert is signaled, this value + will persist until it is cleared."; + sw = r; + } ANY_FAIL_COUNT[15:0]; + } ALERT_SUMMARY_FAIL_COUNTS @ 0xA4; + reg { + field { + desc = "This field will hold a running count of test failures that + contribute to the total alert count. It will be reset after every + passing test sequence. If an alert is signaled, this value + will persist until it is cleared."; + sw = r; + } REPCNT_FAIL_COUNT[7:4]; + field { + desc = "This field will hold a running count of test failures that + contribute to the total alert count. It will be reset after every + passing test sequence. If an alert is signaled, this value + will persist until it is cleared."; + sw = r; + } ADAPTP_HI_FAIL_COUNT[11:8]; + field { + desc = "This field will hold a running count of test failures that + contribute to the total alert count. It will be reset after every + passing test sequence. If an alert is signaled, this value + will persist until it is cleared."; + sw = r; + } ADAPTP_LO_FAIL_COUNT[15:12]; + field { + desc = "This field will hold a running count of test failures that + contribute to the total alert count. It will be reset after every + passing test sequence. If an alert is signaled, this value + will persist until it is cleared."; + sw = r; + } BUCKET_FAIL_COUNT[19:16]; + field { + desc = "This field will hold a running count of test failures that + contribute to the total alert count. It will be reset after every + passing test sequence. If an alert is signaled, this value + will persist until it is cleared."; + sw = r; + } MARKOV_HI_FAIL_COUNT[23:20]; + field { + desc = "This field will hold a running count of test failures that + contribute to the total alert count. It will be reset after every + passing test sequence. If an alert is signaled, this value + will persist until it is cleared."; + sw = r; + } MARKOV_LO_FAIL_COUNT[27:24]; + field { + desc = "This field will hold a running count of test failures that + contribute to the total alert count. It will be reset after every + passing test sequence. If an alert is signaled, this value + will persist until it is cleared."; + sw = r; + } REPCNTS_FAIL_COUNT[31:28]; + } ALERT_FAIL_COUNTS @ 0xA8; + reg { + field { + desc = "This field will hold a running count of test failures that + contribute to the total alert count. It will be reset after every + passing test sequence. If an alert is signaled, this value + will persist until it is cleared."; + sw = r; + } EXTHT_HI_FAIL_COUNT[3:0]; + field { + desc = "This field will hold a running count of test failures that + contribute to the total alert count. It will be reset after every + passing test sequence. If an alert is signaled, this value + will persist until it is cleared."; + sw = r; + } EXTHT_LO_FAIL_COUNT[7:4]; + } EXTHT_FAIL_COUNTS @ 0xAC; + reg { + field { + desc = "Setting this field to kMultiBitBool4True will put the entropy flow in firmware override mode. + In this mode, firmware can monitor the post-health test entropy by reading + the observe FIFO. This function also requires that the otp_en_entropy_src_fw_over + input vector is set to the enable encoding."; + sw = rw; + } FW_OV_MODE[3:0] = 0x9; + field { + desc = "Setting this field to kMultiBitBool4True will switch the input into the pre-conditioner + packer FIFO. Firmware can directly write into the packer FIFO, enabling + the ability to insert entropy bits back into the hardware flow. Firmware + can read data from the health check packer FIFO, then do optional health + checks or optional conditioning, then insert the results back into the flow. + Also, the !!FW_OV_CONTROL.FW_OV_MODE bit must be set."; + sw = rw; + } FW_OV_ENTROPY_INSERT[7:4] = 0x9; + } FW_OV_CONTROL @ 0xB0; + reg { + field { + desc = "Setting this field to kMultiBitBool4True will instruct the ENTROPY_SRC main state machine + to start the SHA3 process and be ready to accept entropy data. This field should + be set prior to writting the FW_OV_WR_DATA register. Once all data has been written, + this field should be set to kMultiBitBool4False. Once that happened, the SHA3 block will finish + processing and push the result into the ESFINAL FIFO. + + Note that clearing this bit to kMultiBitBool4False while there is still unprocessed + entropy in the !!FW_OV_WR_DATA will start the SHA3 engine before data can be added + to the input message, and will also signal a recoverable alert in + !!RECOV_ALERT_STS.ES_FW_OV_DISABLE_ALERT. To avoid this, check that + !!FW_OV_WR_FIFO_FULL is clear before setting this field to kMultiBitBool4False."; + sw = rw; + } FW_OV_INSERT_START[3:0] = 0x9; + } FW_OV_SHA3_START @ 0xB4; + reg { + field { + desc = "\"When this bit is clear, writes to the FW_OV_WR_DATA register are allowed. + If this bit is set, it is the equivalent to a FIFO full condition, and writes + to the FW_OV_WR_DATA register must be delayed until this bit is reset."; + sw = r; + } FW_OV_WR_FIFO_FULL[0:0]; + } FW_OV_WR_FIFO_FULL @ 0xB8; + reg { + field { + desc = "This bit is set by hardware whenever RNG data is lost due to an overflow condition + in the Observe FIFO. The RNG data rate is slow enough that firmware should always + be able to keep up. This register meanwhile provides an additional check to confirm + that bytes read from the !!FW_OV_RD_DATA register represent contiguous RNG samples. + If an overflow event occurs, this bit is cleared by hardware as soon as the FIFO is emptied."; + sw = r; + } FW_OV_RD_FIFO_OVERFLOW[0:0]; + } FW_OV_RD_FIFO_OVERFLOW @ 0xBC; + reg { + field { + desc = "A read of this register pops and returns the top of the Observe FIFO."; + sw = r; + } FW_OV_RD_DATA[31:0]; + } FW_OV_RD_DATA @ 0xC0; + reg { + field { + desc = "A write to this register will insert entropy back into the entropy source + module flow. Both !!FW_OV_CONTROL.FW_OV_MODE and !!FW_OV_CONTROL.FW_OV_ENTROPY_INSERT bits need to be set + to enable the insertion."; + sw = w; + } FW_OV_WR_DATA[31:0]; + } FW_OV_WR_DATA @ 0xC4; + reg { + field { + desc = "This field will set the threshold that the depth of the Observe FIFO + will be compared with when setting the interrupt status bit. + Note: a value of zero is reserved and not to be used."; + sw = rw; + } OBSERVE_FIFO_THRESH[6:0] = 0x20; + } OBSERVE_FIFO_THRESH @ 0xC8; + reg { + field { + desc = "This field will hold the current depth of the Observe FIFO."; + sw = r; + } OBSERVE_FIFO_DEPTH[6:0]; + } OBSERVE_FIFO_DEPTH @ 0xCC; + reg { + field { + desc = "This is the depth of the entropy source FIFO."; + sw = r; + } ENTROPY_FIFO_DEPTH[2:0]; + field { + desc = "This is the SHA3 finite state machine current state."; + sw = r; + } SHA3_FSM[5:3]; + field { + desc = "This is the SHA3 block processed signal current state."; + sw = r; + } SHA3_BLOCK_PR[6:6]; + field { + desc = "This is the SHA3 squeezing signal current state."; + sw = r; + } SHA3_SQUEEZING[7:7]; + field { + desc = "This is the SHA3 absorbed signal current state."; + sw = r; + } SHA3_ABSORBED[8:8]; + field { + desc = "This is a logic-or of all of the SHA3 error signals."; + sw = r; + } SHA3_ERR[9:9]; + field { + desc = "The entropy_src main state machine is in the idle state."; + sw = r; + } MAIN_SM_IDLE[16:16] = 0x1; + field { + desc = "The entropy_src main state machine is in the boot phase done state."; + sw = r; + } MAIN_SM_BOOT_DONE[17:17]; + } DEBUG_STATUS @ 0xD0; + reg { + field { + desc = "This bit is set when the FIPS_ENABLE field in the !!CONF register is set to + a value other than kMultiBitBool4False or kMultiBitBool4True. + Writing a zero resets this status bit."; + sw = rw; + onwrite = woclr; + } FIPS_ENABLE_FIELD_ALERT[0:0]; + field { + desc = "This bit is set when the ENTROPY_DATA_REG_ENABLE field in the !!CONF register is set to + a value other than kMultiBitBool4False or kMultiBitBool4True. + Writing a zero resets this status bit."; + sw = rw; + onwrite = woclr; + } ENTROPY_DATA_REG_EN_FIELD_ALERT[1:1]; + field { + desc = "This bit is set when the MODULE_ENABLE field in the !!MODULE_ENABLE register is set to + a value other than kMultiBitBool4False or kMultiBitBool4True. + Writing a zero resets this status bit."; + sw = rw; + onwrite = woclr; + } MODULE_ENABLE_FIELD_ALERT[2:2]; + field { + desc = "This bit is set when the THRESHOLD_SCOPE field in the !!CONF register is set to + a value other than kMultiBitBool4False or kMultiBitBool4True. + Writing a zero resets this status bit."; + sw = rw; + onwrite = woclr; + } THRESHOLD_SCOPE_FIELD_ALERT[3:3]; + field { + desc = "This bit is set when the RNG_BIT_ENABLE field in the !!CONF register is set to + a value other than kMultiBitBool4False or kMultiBitBool4True. + Writing a zero resets this status bit."; + sw = rw; + onwrite = woclr; + } RNG_BIT_ENABLE_FIELD_ALERT[5:5]; + field { + desc = "This bit is set when the FW_OV_SHA3_START field in the !!FW_OV_SHA3_START register is set to + a value other than kMultiBitBool4False or kMultiBitBool4True. + Writing a zero resets this status bit."; + sw = rw; + onwrite = woclr; + } FW_OV_SHA3_START_FIELD_ALERT[7:7]; + field { + desc = "This bit is set when the FW_OV_MODE field in the !!FW_OV_CONTROL register is set to + a value other than kMultiBitBool4False or kMultiBitBool4True. + Writing a zero resets this status bit."; + sw = rw; + onwrite = woclr; + } FW_OV_MODE_FIELD_ALERT[8:8]; + field { + desc = "This bit is set when the FW_OV_ENTROPY_INSERT field in the !!FW_OV_CONTROL register is set to + a value other than kMultiBitBool4False or kMultiBitBool4True. + Writing a zero resets this status bit."; + sw = rw; + onwrite = woclr; + } FW_OV_ENTROPY_INSERT_FIELD_ALERT[9:9]; + field { + desc = "This bit is set when the ES_ROUTE field in the !!ENTROPY_CONTROL register is set to + a value other than kMultiBitBool4False or kMultiBitBool4True. + Writing a zero resets this status bit."; + sw = rw; + onwrite = woclr; + } ES_ROUTE_FIELD_ALERT[10:10]; + field { + desc = "This bit is set when the ES_TYPE field in the !!ENTROPY_CONTROL register is set to + a value other than kMultiBitBool4False or kMultiBitBool4True. + Writing a zero resets this status bit."; + sw = rw; + onwrite = woclr; + } ES_TYPE_FIELD_ALERT[11:11]; + field { + desc = "This bit is set when the main state machine detects a threshhold failure state. + Writing a zero resets this status bit."; + sw = rw; + onwrite = woclr; + } ES_MAIN_SM_ALERT[12:12]; + field { + desc = "This bit is set when the interal entropy bus value is equal to the prior + valid value on the bus, indicating a possible attack. + Writing a zero resets this status bit."; + sw = rw; + onwrite = woclr; + } ES_BUS_CMP_ALERT[13:13]; + field { + desc = "This bit is set when the !!ALERT_THRESHOLD register is not configured properly. + The upper field must be the exact inverse of the lower field. + Writing a zero resets this status bit."; + sw = rw; + onwrite = woclr; + } ES_THRESH_CFG_ALERT[14:14]; + field { + desc = "This bit is set when the packer FIFO has been written but was full at the time, + and in both FW_OV_MODE and FW_OV_ENTROPY_INSERT modes. + This alert would normally be the result of not monitoring the !!FW_OV_WR_FIFO_FULL + register before each write to the !!FW_OV_WR_DATA register. + Writing a zero resets this status bit."; + sw = rw; + onwrite = woclr; + } ES_FW_OV_WR_ALERT[15:15]; + field { + desc = "This bit is set when !!FW_OV_SHA3_START has been set to MuBi4 False, without + waiting for the FW_OV packer FIFO to clear. The final entropy entry in the FIFO + will not be included in the SHA3 digest. (Rather it will be added to the + subsequent SHA3 digest.) To avoid this alert, monitor !!FW_OV_WR_FIFO_FULL before + clearing !!FW_OV_SHA3_START. This alert only applies when both FW_OV_MODE and + FW_OV_ENTROPY_INSERT are set to MuBi4True. + Writing a zero resets this status bit."; + sw = rw; + onwrite = woclr; + } ES_FW_OV_DISABLE_ALERT[16:16]; + } RECOV_ALERT_STS @ 0xD4; + reg { + field { + desc = "This bit will be set to one when an error has been detected for the + esrng FIFO. The type of error is reflected in the type status + bits (bits 28 through 30 of this register). + This bit will stay set until the next reset."; + sw = r; + } SFIFO_ESRNG_ERR[0:0]; + field { + desc = "This bit will be set to one when an error has been detected for the + observe FIFO. The type of error is reflected in the type status + bits (bits 28 through 30 of this register). + This bit will stay set until the next reset."; + sw = r; + } SFIFO_OBSERVE_ERR[1:1]; + field { + desc = "This bit will be set to one when an error has been detected for the + esfinal FIFO. The type of error is reflected in the type status + bits (bits 28 through 30 of this register). + This bit will stay set until the next reset."; + sw = r; + } SFIFO_ESFINAL_ERR[2:2]; + field { + desc = "This bit will be set to one when an illegal state has been detected for the + ES ack stage state machine. This error will signal a fatal alert, and also + an interrupt if enabled. + This bit will stay set until the next reset."; + sw = r; + } ES_ACK_SM_ERR[20:20]; + field { + desc = "This bit will be set to one when an illegal state has been detected for the + ES main stage state machine. This error will signal a fatal alert, and also + an interrupt if enabled. + This bit will stay set until the next reset."; + sw = r; + } ES_MAIN_SM_ERR[21:21]; + field { + desc = "This bit will be set to one when a hardened counter has detected an error + condition. This error will signal a fatal alert, and also + an interrupt if enabled. + This bit will stay set until the next reset."; + sw = r; + } ES_CNTR_ERR[22:22]; + field { + desc = "This bit will be set to one when a SHA3 state error has been detected. + This error will signal a fatal alert, and also an interrupt if enabled. + This bit will stay set until the next reset."; + sw = r; + } SHA3_STATE_ERR[23:23]; + field { + desc = "This bit will be set to one when a SHA3_RST_STORAGE_ERR signal being + active has been detected. + This error will signal a fatal alert, and also an interrupt if enabled. + This bit will stay set until the next reset."; + sw = r; + } SHA3_RST_STORAGE_ERR[24:24]; + field { + desc = "This bit will be set to one when any of the source bits (bits 0 through 1 of this + this register) are asserted as a result of an error pulse generated from + any full FIFO that has been recieved a write pulse. + This bit will stay set until the next reset."; + sw = r; + } FIFO_WRITE_ERR[28:28]; + field { + desc = "This bit will be set to one when any of the source bits (bits 0 through 1 of this + this register) are asserted as a result of an error pulse generated from + any empty FIFO that has recieved a read pulse. + This bit will stay set until the next reset."; + sw = r; + } FIFO_READ_ERR[29:29]; + field { + desc = "This bit will be set to one when any of the source bits (bits 0 through 1 of this + this register) are asserted as a result of an error pulse generated from + any FIFO where both the empty and full status bits are set. + This bit will stay set until the next reset."; + sw = r; + } FIFO_STATE_ERR[30:30]; + } ERR_CODE @ 0xD8; + reg { + field { + desc = "Setting this field will set the bit number for which an error + will be forced in the hardware. This bit number is that same one + found in the !!ERR_CODE register. The action of writing this + register will force an error pulse. The sole purpose of this + register is to test that any error properly propagates to either + an interrupt or an alert."; + sw = rw; + } ERR_CODE_TEST[4:0]; + } ERR_CODE_TEST @ 0xDC; + reg { + field { + desc = "This is the state of the ENTROPY_SRC main state machine. + See the RTL file `entropy_src_main_sm` for the meaning of the values."; + sw = r; + } MAIN_SM_STATE[8:0] = 0xF5; + } MAIN_SM_STATE @ 0xE0; +}; \ No newline at end of file diff --git a/src/fuse_ctrl/data/otp-img.2048.vmem b/src/fuse_ctrl/data/otp-img.2048.vmem new file mode 100644 index 0000000..4cb8350 --- /dev/null +++ b/src/fuse_ctrl/data/otp-img.2048.vmem @@ -0,0 +1,1032 @@ +// Generated on Sat, 07 Dec 2024 03:36:54 UTC with +// $ gen-otp-img.py \ +// --img-cfg /home/ws/caliptra/anjpar/opentitan_1106/hw/ip/otp_ctrl/data/otp_ctrl_img_raw.hjson \ +// --lc-state-def /home/ws/caliptra/anjpar/opentitan_1106/hw/ip/lc_ctrl/data/lc_ctrl_state.hjson \ +// --mmap-def /home/ws/caliptra/anjpar/opentitan_1106/hw/ip/otp_ctrl/data/otp_ctrl_mmap.hjson \ +// --out hw/ip/otp_ctrl/data/otp-img.2048.vmem +// +// OTP MEM file with 1024 x 24bit layout +@000000 000000 // VENDOR_TEST: SCRATCH +@000001 000000 // VENDOR_TEST: SCRATCH +@000002 000000 // VENDOR_TEST: SCRATCH +@000003 000000 // VENDOR_TEST: SCRATCH +@000004 000000 // VENDOR_TEST: SCRATCH +@000005 000000 // VENDOR_TEST: SCRATCH +@000006 000000 // VENDOR_TEST: SCRATCH +@000007 000000 // VENDOR_TEST: SCRATCH +@000008 000000 // VENDOR_TEST: SCRATCH +@000009 000000 // VENDOR_TEST: SCRATCH +@00000a 000000 // VENDOR_TEST: SCRATCH +@00000b 000000 // VENDOR_TEST: SCRATCH +@00000c 000000 // VENDOR_TEST: SCRATCH +@00000d 000000 // VENDOR_TEST: SCRATCH +@00000e 000000 // VENDOR_TEST: SCRATCH +@00000f 000000 // VENDOR_TEST: SCRATCH +@000010 000000 // VENDOR_TEST: SCRATCH +@000011 000000 // VENDOR_TEST: SCRATCH +@000012 000000 // VENDOR_TEST: SCRATCH +@000013 000000 // VENDOR_TEST: SCRATCH +@000014 000000 // VENDOR_TEST: SCRATCH +@000015 000000 // VENDOR_TEST: SCRATCH +@000016 000000 // VENDOR_TEST: SCRATCH +@000017 000000 // VENDOR_TEST: SCRATCH +@000018 000000 // VENDOR_TEST: SCRATCH +@000019 000000 // VENDOR_TEST: SCRATCH +@00001a 000000 // VENDOR_TEST: SCRATCH +@00001b 000000 // VENDOR_TEST: SCRATCH +@00001c 000000 // VENDOR_TEST: VENDOR_TEST_DIGEST +@00001d 000000 // VENDOR_TEST: VENDOR_TEST_DIGEST +@00001e 000000 // VENDOR_TEST: VENDOR_TEST_DIGEST +@00001f 000000 // VENDOR_TEST: VENDOR_TEST_DIGEST +@000020 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@000021 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@000022 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@000023 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@000024 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@000025 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@000026 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@000027 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@000028 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@000029 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@00002a 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@00002b 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@00002c 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@00002d 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@00002e 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@00002f 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@000030 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@000031 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@000032 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@000033 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@000034 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@000035 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@000036 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@000037 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@000038 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@000039 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@00003a 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@00003b 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@00003c 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@00003d 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@00003e 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@00003f 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@000040 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@000041 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@000042 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@000043 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@000044 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@000045 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@000046 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@000047 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@000048 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@000049 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@00004a 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@00004b 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@00004c 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@00004d 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@00004e 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@00004f 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@000050 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@000051 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@000052 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@000053 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@000054 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@000055 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@000056 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@000057 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@000058 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@000059 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@00005a 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@00005b 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@00005c 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@00005d 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@00005e 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@00005f 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@000060 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@000061 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@000062 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@000063 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@000064 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@000065 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@000066 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@000067 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@000068 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@000069 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@00006a 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@00006b 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@00006c 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@00006d 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_CFG +@00006e 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_INIT_EN +@00006f 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_AST_INIT_EN +@000070 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_ROM_EXT_SKU +@000071 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_ROM_EXT_SKU +@000072 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_SIGVERIFY_SPX_EN +@000073 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_SIGVERIFY_SPX_EN +@000074 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_FLASH_DATA_DEFAULT_CFG +@000075 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_FLASH_DATA_DEFAULT_CFG +@000076 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_FLASH_INFO_BOOT_DATA_CFG +@000077 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_FLASH_INFO_BOOT_DATA_CFG +@000078 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_FLASH_HW_INFO_CFG_OVERRIDE +@000079 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_FLASH_HW_INFO_CFG_OVERRIDE +@00007a 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_RNG_EN +@00007b 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_RNG_EN +@00007c 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_JITTER_EN +@00007d 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_JITTER_EN +@00007e 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_RET_RAM_RESET_MASK +@00007f 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_RET_RAM_RESET_MASK +@000080 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_MANUF_STATE +@000081 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_MANUF_STATE +@000082 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_ROM_EXEC_EN +@000083 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_ROM_EXEC_EN +@000084 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_CPUCTRL +@000085 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_CPUCTRL +@000086 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_MIN_SEC_VER_ROM_EXT +@000087 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_MIN_SEC_VER_ROM_EXT +@000088 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_MIN_SEC_VER_BL0 +@000089 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_MIN_SEC_VER_BL0 +@00008a 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_DEFAULT_BOOT_DATA_IN_PROD_EN +@00008b 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_DEFAULT_BOOT_DATA_IN_PROD_EN +@00008c 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_RMA_SPIN_EN +@00008d 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_RMA_SPIN_EN +@00008e 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_RMA_SPIN_CYCLES +@00008f 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_RMA_SPIN_CYCLES +@000090 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_RNG_REPCNT_THRESHOLDS +@000091 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_RNG_REPCNT_THRESHOLDS +@000092 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_RNG_REPCNTS_THRESHOLDS +@000093 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_RNG_REPCNTS_THRESHOLDS +@000094 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_RNG_ADAPTP_HI_THRESHOLDS +@000095 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_RNG_ADAPTP_HI_THRESHOLDS +@000096 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_RNG_ADAPTP_LO_THRESHOLDS +@000097 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_RNG_ADAPTP_LO_THRESHOLDS +@000098 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_RNG_BUCKET_THRESHOLDS +@000099 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_RNG_BUCKET_THRESHOLDS +@00009a 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_RNG_MARKOV_HI_THRESHOLDS +@00009b 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_RNG_MARKOV_HI_THRESHOLDS +@00009c 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_RNG_MARKOV_LO_THRESHOLDS +@00009d 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_RNG_MARKOV_LO_THRESHOLDS +@00009e 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_RNG_EXTHT_HI_THRESHOLDS +@00009f 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_RNG_EXTHT_HI_THRESHOLDS +@0000a0 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_RNG_EXTHT_LO_THRESHOLDS +@0000a1 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_RNG_EXTHT_LO_THRESHOLDS +@0000a2 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_RNG_ALERT_THRESHOLD +@0000a3 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_RNG_ALERT_THRESHOLD +@0000a4 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_RNG_HEALTH_CONFIG_DIGEST +@0000a5 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_RNG_HEALTH_CONFIG_DIGEST +@0000a6 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_SRAM_KEY_RENEW_EN +@0000a7 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_SRAM_KEY_RENEW_EN +@0000a8 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_IMMUTABLE_ROM_EXT_EN +@0000a9 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_IMMUTABLE_ROM_EXT_EN +@0000aa 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_IMMUTABLE_ROM_EXT_START_OFFSET +@0000ab 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_IMMUTABLE_ROM_EXT_START_OFFSET +@0000ac 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_IMMUTABLE_ROM_EXT_LENGTH +@0000ad 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_IMMUTABLE_ROM_EXT_LENGTH +@0000ae 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_IMMUTABLE_ROM_EXT_SHA256_HASH +@0000af 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_IMMUTABLE_ROM_EXT_SHA256_HASH +@0000b0 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_IMMUTABLE_ROM_EXT_SHA256_HASH +@0000b1 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_IMMUTABLE_ROM_EXT_SHA256_HASH +@0000b2 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_IMMUTABLE_ROM_EXT_SHA256_HASH +@0000b3 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_IMMUTABLE_ROM_EXT_SHA256_HASH +@0000b4 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_IMMUTABLE_ROM_EXT_SHA256_HASH +@0000b5 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_IMMUTABLE_ROM_EXT_SHA256_HASH +@0000b6 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_IMMUTABLE_ROM_EXT_SHA256_HASH +@0000b7 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_IMMUTABLE_ROM_EXT_SHA256_HASH +@0000b8 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_IMMUTABLE_ROM_EXT_SHA256_HASH +@0000b9 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_IMMUTABLE_ROM_EXT_SHA256_HASH +@0000ba 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_IMMUTABLE_ROM_EXT_SHA256_HASH +@0000bb 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_IMMUTABLE_ROM_EXT_SHA256_HASH +@0000bc 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_IMMUTABLE_ROM_EXT_SHA256_HASH +@0000bd 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_IMMUTABLE_ROM_EXT_SHA256_HASH +@0000be 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_RESERVED +@0000bf 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_RESERVED +@0000c0 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_RESERVED +@0000c1 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_RESERVED +@0000c2 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_RESERVED +@0000c3 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_RESERVED +@0000c4 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_RESERVED +@0000c5 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_RESERVED +@0000c6 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_RESERVED +@0000c7 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_RESERVED +@0000c8 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_RESERVED +@0000c9 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_RESERVED +@0000ca 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_RESERVED +@0000cb 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_RESERVED +@0000cc 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_RESERVED +@0000cd 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_RESERVED +@0000ce 000000 // unallocated +@0000cf 000000 // unallocated +@0000d0 000000 // unallocated +@0000d1 000000 // unallocated +@0000d2 000000 // unallocated +@0000d3 000000 // unallocated +@0000d4 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_DIGEST +@0000d5 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_DIGEST +@0000d6 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_DIGEST +@0000d7 000000 // CREATOR_SW_CFG: CREATOR_SW_CFG_DIGEST +@0000d8 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ERROR_REPORTING +@0000d9 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ERROR_REPORTING +@0000da 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_BOOTSTRAP_DIS +@0000db 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_BOOTSTRAP_DIS +@0000dc 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASS_EN +@0000dd 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASS_EN +@0000de 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_ESCALATION +@0000df 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_ESCALATION +@0000e0 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@0000e1 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@0000e2 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@0000e3 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@0000e4 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@0000e5 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@0000e6 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@0000e7 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@0000e8 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@0000e9 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@0000ea 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@0000eb 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@0000ec 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@0000ed 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@0000ee 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@0000ef 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@0000f0 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@0000f1 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@0000f2 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@0000f3 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@0000f4 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@0000f5 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@0000f6 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@0000f7 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@0000f8 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@0000f9 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@0000fa 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@0000fb 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@0000fc 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@0000fd 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@0000fe 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@0000ff 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000100 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000101 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000102 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000103 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000104 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000105 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000106 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000107 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000108 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000109 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@00010a 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@00010b 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@00010c 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@00010d 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@00010e 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@00010f 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000110 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000111 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000112 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000113 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000114 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000115 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000116 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000117 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000118 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000119 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@00011a 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@00011b 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@00011c 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@00011d 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@00011e 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@00011f 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000120 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000121 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000122 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000123 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000124 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000125 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000126 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000127 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000128 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000129 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@00012a 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@00012b 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@00012c 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@00012d 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@00012e 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@00012f 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000130 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000131 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000132 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000133 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000134 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000135 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000136 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000137 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000138 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000139 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@00013a 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@00013b 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@00013c 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@00013d 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@00013e 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@00013f 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000140 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000141 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000142 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000143 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000144 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000145 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000146 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000147 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000148 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000149 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@00014a 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@00014b 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@00014c 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@00014d 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@00014e 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@00014f 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000150 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000151 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000152 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000153 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000154 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000155 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000156 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000157 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000158 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000159 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@00015a 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@00015b 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@00015c 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@00015d 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@00015e 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@00015f 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000160 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000161 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000162 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000163 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000164 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000165 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000166 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000167 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000168 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000169 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@00016a 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@00016b 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@00016c 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@00016d 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@00016e 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@00016f 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000170 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000171 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000172 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000173 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000174 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000175 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000176 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000177 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000178 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000179 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@00017a 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@00017b 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@00017c 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@00017d 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@00017e 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@00017f 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION +@000180 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION +@000181 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION +@000182 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION +@000183 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION +@000184 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION +@000185 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION +@000186 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION +@000187 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION +@000188 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION +@000189 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION +@00018a 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION +@00018b 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION +@00018c 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION +@00018d 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION +@00018e 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION +@00018f 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION +@000190 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION +@000191 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION +@000192 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION +@000193 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION +@000194 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION +@000195 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION +@000196 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION +@000197 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION +@000198 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION +@000199 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION +@00019a 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION +@00019b 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION +@00019c 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION +@00019d 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION +@00019e 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION +@00019f 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION +@0001a0 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_ACCUM_THRESH +@0001a1 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_ACCUM_THRESH +@0001a2 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_ACCUM_THRESH +@0001a3 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_ACCUM_THRESH +@0001a4 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_ACCUM_THRESH +@0001a5 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_ACCUM_THRESH +@0001a6 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_ACCUM_THRESH +@0001a7 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_ACCUM_THRESH +@0001a8 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_TIMEOUT_CYCLES +@0001a9 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_TIMEOUT_CYCLES +@0001aa 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_TIMEOUT_CYCLES +@0001ab 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_TIMEOUT_CYCLES +@0001ac 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_TIMEOUT_CYCLES +@0001ad 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_TIMEOUT_CYCLES +@0001ae 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_TIMEOUT_CYCLES +@0001af 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_TIMEOUT_CYCLES +@0001b0 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES +@0001b1 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES +@0001b2 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES +@0001b3 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES +@0001b4 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES +@0001b5 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES +@0001b6 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES +@0001b7 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES +@0001b8 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES +@0001b9 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES +@0001ba 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES +@0001bb 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES +@0001bc 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES +@0001bd 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES +@0001be 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES +@0001bf 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES +@0001c0 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES +@0001c1 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES +@0001c2 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES +@0001c3 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES +@0001c4 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES +@0001c5 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES +@0001c6 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES +@0001c7 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES +@0001c8 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES +@0001c9 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES +@0001ca 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES +@0001cb 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES +@0001cc 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES +@0001cd 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES +@0001ce 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES +@0001cf 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES +@0001d0 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD +@0001d1 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD +@0001d2 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD_END +@0001d3 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD_END +@0001d4 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_DIGEST_DEV +@0001d5 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_DIGEST_DEV +@0001d6 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_DIGEST_RMA +@0001d7 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_ALERT_DIGEST_RMA +@0001d8 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_WATCHDOG_BITE_THRESHOLD_CYCLES +@0001d9 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_WATCHDOG_BITE_THRESHOLD_CYCLES +@0001da 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_KEYMGR_OTP_MEAS_EN +@0001db 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_KEYMGR_OTP_MEAS_EN +@0001dc 000000 // OWNER_SW_CFG: OWNER_SW_CFG_MANUF_STATE +@0001dd 000000 // OWNER_SW_CFG: OWNER_SW_CFG_MANUF_STATE +@0001de 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_RSTMGR_INFO_EN +@0001df 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_RSTMGR_INFO_EN +@0001e0 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_EXT_BOOTSTRAP_EN +@0001e1 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_EXT_BOOTSTRAP_EN +@0001e2 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_SENSOR_CTRL_ALERT_CFG +@0001e3 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_SENSOR_CTRL_ALERT_CFG +@0001e4 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_SENSOR_CTRL_ALERT_CFG +@0001e5 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_SENSOR_CTRL_ALERT_CFG +@0001e6 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_SENSOR_CTRL_ALERT_CFG +@0001e7 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_SENSOR_CTRL_ALERT_CFG +@0001e8 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_SRAM_READBACK_EN +@0001e9 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_SRAM_READBACK_EN +@0001ea 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_PRESERVE_RESET_REASON_EN +@0001eb 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_PRESERVE_RESET_REASON_EN +@0001ec 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_RESET_REASON_CHECK_VALUE +@0001ed 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_RESET_REASON_CHECK_VALUE +@0001ee 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_BANNER_EN +@0001ef 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_BANNER_EN +@0001f0 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_FLASH_ECC_EXC_HANDLER_EN +@0001f1 000000 // OWNER_SW_CFG: OWNER_SW_CFG_ROM_FLASH_ECC_EXC_HANDLER_EN +@0001f2 000000 // OWNER_SW_CFG: OWNER_SW_CFG_RESERVED +@0001f3 000000 // OWNER_SW_CFG: OWNER_SW_CFG_RESERVED +@0001f4 000000 // OWNER_SW_CFG: OWNER_SW_CFG_RESERVED +@0001f5 000000 // OWNER_SW_CFG: OWNER_SW_CFG_RESERVED +@0001f6 000000 // OWNER_SW_CFG: OWNER_SW_CFG_RESERVED +@0001f7 000000 // OWNER_SW_CFG: OWNER_SW_CFG_RESERVED +@0001f8 000000 // OWNER_SW_CFG: OWNER_SW_CFG_RESERVED +@0001f9 000000 // OWNER_SW_CFG: OWNER_SW_CFG_RESERVED +@0001fa 000000 // OWNER_SW_CFG: OWNER_SW_CFG_RESERVED +@0001fb 000000 // OWNER_SW_CFG: OWNER_SW_CFG_RESERVED +@0001fc 000000 // OWNER_SW_CFG: OWNER_SW_CFG_RESERVED +@0001fd 000000 // OWNER_SW_CFG: OWNER_SW_CFG_RESERVED +@0001fe 000000 // OWNER_SW_CFG: OWNER_SW_CFG_RESERVED +@0001ff 000000 // OWNER_SW_CFG: OWNER_SW_CFG_RESERVED +@000200 000000 // OWNER_SW_CFG: OWNER_SW_CFG_RESERVED +@000201 000000 // OWNER_SW_CFG: OWNER_SW_CFG_RESERVED +@000202 000000 // OWNER_SW_CFG: OWNER_SW_CFG_RESERVED +@000203 000000 // OWNER_SW_CFG: OWNER_SW_CFG_RESERVED +@000204 000000 // OWNER_SW_CFG: OWNER_SW_CFG_RESERVED +@000205 000000 // OWNER_SW_CFG: OWNER_SW_CFG_RESERVED +@000206 000000 // OWNER_SW_CFG: OWNER_SW_CFG_RESERVED +@000207 000000 // OWNER_SW_CFG: OWNER_SW_CFG_RESERVED +@000208 000000 // OWNER_SW_CFG: OWNER_SW_CFG_RESERVED +@000209 000000 // OWNER_SW_CFG: OWNER_SW_CFG_RESERVED +@00020a 000000 // OWNER_SW_CFG: OWNER_SW_CFG_RESERVED +@00020b 000000 // OWNER_SW_CFG: OWNER_SW_CFG_RESERVED +@00020c 000000 // OWNER_SW_CFG: OWNER_SW_CFG_RESERVED +@00020d 000000 // OWNER_SW_CFG: OWNER_SW_CFG_RESERVED +@00020e 000000 // OWNER_SW_CFG: OWNER_SW_CFG_RESERVED +@00020f 000000 // OWNER_SW_CFG: OWNER_SW_CFG_RESERVED +@000210 000000 // OWNER_SW_CFG: OWNER_SW_CFG_RESERVED +@000211 000000 // OWNER_SW_CFG: OWNER_SW_CFG_RESERVED +@000212 000000 // OWNER_SW_CFG: OWNER_SW_CFG_RESERVED +@000213 000000 // OWNER_SW_CFG: OWNER_SW_CFG_RESERVED +@000214 000000 // OWNER_SW_CFG: OWNER_SW_CFG_RESERVED +@000215 000000 // OWNER_SW_CFG: OWNER_SW_CFG_RESERVED +@000216 000000 // OWNER_SW_CFG: OWNER_SW_CFG_RESERVED +@000217 000000 // OWNER_SW_CFG: OWNER_SW_CFG_RESERVED +@000218 000000 // OWNER_SW_CFG: OWNER_SW_CFG_RESERVED +@000219 000000 // OWNER_SW_CFG: OWNER_SW_CFG_RESERVED +@00021a 000000 // OWNER_SW_CFG: OWNER_SW_CFG_RESERVED +@00021b 000000 // OWNER_SW_CFG: OWNER_SW_CFG_RESERVED +@00021c 000000 // OWNER_SW_CFG: OWNER_SW_CFG_RESERVED +@00021d 000000 // OWNER_SW_CFG: OWNER_SW_CFG_RESERVED +@00021e 000000 // OWNER_SW_CFG: OWNER_SW_CFG_RESERVED +@00021f 000000 // OWNER_SW_CFG: OWNER_SW_CFG_RESERVED +@000220 000000 // OWNER_SW_CFG: OWNER_SW_CFG_RESERVED +@000221 000000 // OWNER_SW_CFG: OWNER_SW_CFG_RESERVED +@000222 000000 // OWNER_SW_CFG: OWNER_SW_CFG_RESERVED +@000223 000000 // OWNER_SW_CFG: OWNER_SW_CFG_RESERVED +@000224 000000 // OWNER_SW_CFG: OWNER_SW_CFG_RESERVED +@000225 000000 // OWNER_SW_CFG: OWNER_SW_CFG_RESERVED +@000226 000000 // OWNER_SW_CFG: OWNER_SW_CFG_RESERVED +@000227 000000 // OWNER_SW_CFG: OWNER_SW_CFG_RESERVED +@000228 000000 // OWNER_SW_CFG: OWNER_SW_CFG_RESERVED +@000229 000000 // OWNER_SW_CFG: OWNER_SW_CFG_RESERVED +@00022a 000000 // OWNER_SW_CFG: OWNER_SW_CFG_RESERVED +@00022b 000000 // OWNER_SW_CFG: OWNER_SW_CFG_RESERVED +@00022c 000000 // OWNER_SW_CFG: OWNER_SW_CFG_RESERVED +@00022d 000000 // OWNER_SW_CFG: OWNER_SW_CFG_RESERVED +@00022e 000000 // OWNER_SW_CFG: OWNER_SW_CFG_RESERVED +@00022f 000000 // OWNER_SW_CFG: OWNER_SW_CFG_RESERVED +@000230 000000 // OWNER_SW_CFG: OWNER_SW_CFG_RESERVED +@000231 000000 // OWNER_SW_CFG: OWNER_SW_CFG_RESERVED +@000232 000000 // unallocated +@000233 000000 // unallocated +@000234 000000 // unallocated +@000235 000000 // unallocated +@000236 000000 // unallocated +@000237 000000 // unallocated +@000238 000000 // OWNER_SW_CFG: OWNER_SW_CFG_DIGEST +@000239 000000 // OWNER_SW_CFG: OWNER_SW_CFG_DIGEST +@00023a 000000 // OWNER_SW_CFG: OWNER_SW_CFG_DIGEST +@00023b 000000 // OWNER_SW_CFG: OWNER_SW_CFG_DIGEST +@00023c 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY_TYPE0 +@00023d 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY_TYPE0 +@00023e 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY0 +@00023f 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY0 +@000240 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY0 +@000241 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY0 +@000242 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY0 +@000243 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY0 +@000244 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY0 +@000245 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY0 +@000246 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY0 +@000247 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY0 +@000248 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY0 +@000249 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY0 +@00024a 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY0 +@00024b 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY0 +@00024c 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY0 +@00024d 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY0 +@00024e 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY0 +@00024f 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY0 +@000250 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY0 +@000251 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY0 +@000252 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY0 +@000253 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY0 +@000254 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY0 +@000255 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY0 +@000256 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY0 +@000257 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY0 +@000258 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY0 +@000259 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY0 +@00025a 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY0 +@00025b 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY0 +@00025c 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY0 +@00025d 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY0 +@00025e 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY_TYPE1 +@00025f 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY_TYPE1 +@000260 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY1 +@000261 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY1 +@000262 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY1 +@000263 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY1 +@000264 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY1 +@000265 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY1 +@000266 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY1 +@000267 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY1 +@000268 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY1 +@000269 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY1 +@00026a 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY1 +@00026b 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY1 +@00026c 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY1 +@00026d 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY1 +@00026e 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY1 +@00026f 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY1 +@000270 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY1 +@000271 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY1 +@000272 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY1 +@000273 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY1 +@000274 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY1 +@000275 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY1 +@000276 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY1 +@000277 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY1 +@000278 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY1 +@000279 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY1 +@00027a 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY1 +@00027b 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY1 +@00027c 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY1 +@00027d 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY1 +@00027e 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY1 +@00027f 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY1 +@000280 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY_TYPE2 +@000281 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY_TYPE2 +@000282 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY2 +@000283 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY2 +@000284 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY2 +@000285 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY2 +@000286 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY2 +@000287 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY2 +@000288 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY2 +@000289 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY2 +@00028a 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY2 +@00028b 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY2 +@00028c 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY2 +@00028d 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY2 +@00028e 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY2 +@00028f 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY2 +@000290 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY2 +@000291 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY2 +@000292 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY2 +@000293 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY2 +@000294 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY2 +@000295 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY2 +@000296 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY2 +@000297 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY2 +@000298 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY2 +@000299 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY2 +@00029a 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY2 +@00029b 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY2 +@00029c 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY2 +@00029d 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY2 +@00029e 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY2 +@00029f 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY2 +@0002a0 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY2 +@0002a1 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY2 +@0002a2 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY_TYPE3 +@0002a3 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY_TYPE3 +@0002a4 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY3 +@0002a5 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY3 +@0002a6 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY3 +@0002a7 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY3 +@0002a8 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY3 +@0002a9 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY3 +@0002aa 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY3 +@0002ab 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY3 +@0002ac 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY3 +@0002ad 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY3 +@0002ae 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY3 +@0002af 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY3 +@0002b0 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY3 +@0002b1 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY3 +@0002b2 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY3 +@0002b3 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY3 +@0002b4 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY3 +@0002b5 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY3 +@0002b6 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY3 +@0002b7 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY3 +@0002b8 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY3 +@0002b9 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY3 +@0002ba 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY3 +@0002bb 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY3 +@0002bc 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY3 +@0002bd 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY3 +@0002be 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY3 +@0002bf 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY3 +@0002c0 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY3 +@0002c1 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY3 +@0002c2 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY3 +@0002c3 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY3 +@0002c4 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_TYPE0 +@0002c5 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_TYPE0 +@0002c6 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY0 +@0002c7 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY0 +@0002c8 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY0 +@0002c9 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY0 +@0002ca 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY0 +@0002cb 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY0 +@0002cc 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY0 +@0002cd 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY0 +@0002ce 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY0 +@0002cf 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY0 +@0002d0 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY0 +@0002d1 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY0 +@0002d2 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY0 +@0002d3 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY0 +@0002d4 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY0 +@0002d5 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY0 +@0002d6 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_CONFIG0 +@0002d7 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_CONFIG0 +@0002d8 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_TYPE1 +@0002d9 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_TYPE1 +@0002da 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY1 +@0002db 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY1 +@0002dc 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY1 +@0002dd 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY1 +@0002de 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY1 +@0002df 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY1 +@0002e0 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY1 +@0002e1 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY1 +@0002e2 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY1 +@0002e3 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY1 +@0002e4 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY1 +@0002e5 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY1 +@0002e6 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY1 +@0002e7 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY1 +@0002e8 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY1 +@0002e9 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY1 +@0002ea 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_CONFIG1 +@0002eb 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_CONFIG1 +@0002ec 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_TYPE2 +@0002ed 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_TYPE2 +@0002ee 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY2 +@0002ef 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY2 +@0002f0 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY2 +@0002f1 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY2 +@0002f2 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY2 +@0002f3 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY2 +@0002f4 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY2 +@0002f5 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY2 +@0002f6 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY2 +@0002f7 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY2 +@0002f8 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY2 +@0002f9 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY2 +@0002fa 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY2 +@0002fb 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY2 +@0002fc 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY2 +@0002fd 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY2 +@0002fe 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_CONFIG2 +@0002ff 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_CONFIG2 +@000300 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_TYPE3 +@000301 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_TYPE3 +@000302 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY3 +@000303 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY3 +@000304 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY3 +@000305 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY3 +@000306 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY3 +@000307 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY3 +@000308 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY3 +@000309 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY3 +@00030a 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY3 +@00030b 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY3 +@00030c 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY3 +@00030d 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY3 +@00030e 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY3 +@00030f 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY3 +@000310 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY3 +@000311 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY3 +@000312 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_CONFIG3 +@000313 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_CONFIG3 +@000314 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_BLOCK_SHA2_256_HASH +@000315 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_BLOCK_SHA2_256_HASH +@000316 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_BLOCK_SHA2_256_HASH +@000317 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_BLOCK_SHA2_256_HASH +@000318 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_BLOCK_SHA2_256_HASH +@000319 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_BLOCK_SHA2_256_HASH +@00031a 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_BLOCK_SHA2_256_HASH +@00031b 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_BLOCK_SHA2_256_HASH +@00031c 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_BLOCK_SHA2_256_HASH +@00031d 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_BLOCK_SHA2_256_HASH +@00031e 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_BLOCK_SHA2_256_HASH +@00031f 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_BLOCK_SHA2_256_HASH +@000320 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_BLOCK_SHA2_256_HASH +@000321 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_BLOCK_SHA2_256_HASH +@000322 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_BLOCK_SHA2_256_HASH +@000323 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_BLOCK_SHA2_256_HASH +@000324 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_DIGEST +@000325 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_DIGEST +@000326 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_DIGEST +@000327 000000 // ROT_CREATOR_AUTH_CODESIGN: ROT_CREATOR_AUTH_CODESIGN_DIGEST +@000328 000000 // ROT_CREATOR_AUTH_STATE: ROT_CREATOR_AUTH_STATE_ECDSA_KEY0 +@000329 000000 // ROT_CREATOR_AUTH_STATE: ROT_CREATOR_AUTH_STATE_ECDSA_KEY0 +@00032a 000000 // ROT_CREATOR_AUTH_STATE: ROT_CREATOR_AUTH_STATE_ECDSA_KEY1 +@00032b 000000 // ROT_CREATOR_AUTH_STATE: ROT_CREATOR_AUTH_STATE_ECDSA_KEY1 +@00032c 000000 // ROT_CREATOR_AUTH_STATE: ROT_CREATOR_AUTH_STATE_ECDSA_KEY2 +@00032d 000000 // ROT_CREATOR_AUTH_STATE: ROT_CREATOR_AUTH_STATE_ECDSA_KEY2 +@00032e 000000 // ROT_CREATOR_AUTH_STATE: ROT_CREATOR_AUTH_STATE_ECDSA_KEY3 +@00032f 000000 // ROT_CREATOR_AUTH_STATE: ROT_CREATOR_AUTH_STATE_ECDSA_KEY3 +@000330 000000 // ROT_CREATOR_AUTH_STATE: ROT_CREATOR_AUTH_STATE_SPX_KEY0 +@000331 000000 // ROT_CREATOR_AUTH_STATE: ROT_CREATOR_AUTH_STATE_SPX_KEY0 +@000332 000000 // ROT_CREATOR_AUTH_STATE: ROT_CREATOR_AUTH_STATE_SPX_KEY1 +@000333 000000 // ROT_CREATOR_AUTH_STATE: ROT_CREATOR_AUTH_STATE_SPX_KEY1 +@000334 000000 // ROT_CREATOR_AUTH_STATE: ROT_CREATOR_AUTH_STATE_SPX_KEY2 +@000335 000000 // ROT_CREATOR_AUTH_STATE: ROT_CREATOR_AUTH_STATE_SPX_KEY2 +@000336 000000 // ROT_CREATOR_AUTH_STATE: ROT_CREATOR_AUTH_STATE_SPX_KEY3 +@000337 000000 // ROT_CREATOR_AUTH_STATE: ROT_CREATOR_AUTH_STATE_SPX_KEY3 +@000338 000000 // ROT_CREATOR_AUTH_STATE: ROT_CREATOR_AUTH_STATE_DIGEST +@000339 000000 // ROT_CREATOR_AUTH_STATE: ROT_CREATOR_AUTH_STATE_DIGEST +@00033a 000000 // ROT_CREATOR_AUTH_STATE: ROT_CREATOR_AUTH_STATE_DIGEST +@00033b 000000 // ROT_CREATOR_AUTH_STATE: ROT_CREATOR_AUTH_STATE_DIGEST +@00033c 000000 // HW_CFG0: DEVICE_ID +@00033d 000000 // HW_CFG0: DEVICE_ID +@00033e 000000 // HW_CFG0: DEVICE_ID +@00033f 000000 // HW_CFG0: DEVICE_ID +@000340 000000 // HW_CFG0: DEVICE_ID +@000341 000000 // HW_CFG0: DEVICE_ID +@000342 000000 // HW_CFG0: DEVICE_ID +@000343 000000 // HW_CFG0: DEVICE_ID +@000344 000000 // HW_CFG0: DEVICE_ID +@000345 000000 // HW_CFG0: DEVICE_ID +@000346 000000 // HW_CFG0: DEVICE_ID +@000347 000000 // HW_CFG0: DEVICE_ID +@000348 000000 // HW_CFG0: DEVICE_ID +@000349 000000 // HW_CFG0: DEVICE_ID +@00034a 000000 // HW_CFG0: DEVICE_ID +@00034b 000000 // HW_CFG0: DEVICE_ID +@00034c 000000 // HW_CFG0: MANUF_STATE +@00034d 000000 // HW_CFG0: MANUF_STATE +@00034e 000000 // HW_CFG0: MANUF_STATE +@00034f 000000 // HW_CFG0: MANUF_STATE +@000350 000000 // HW_CFG0: MANUF_STATE +@000351 000000 // HW_CFG0: MANUF_STATE +@000352 000000 // HW_CFG0: MANUF_STATE +@000353 000000 // HW_CFG0: MANUF_STATE +@000354 000000 // HW_CFG0: MANUF_STATE +@000355 000000 // HW_CFG0: MANUF_STATE +@000356 000000 // HW_CFG0: MANUF_STATE +@000357 000000 // HW_CFG0: MANUF_STATE +@000358 000000 // HW_CFG0: MANUF_STATE +@000359 000000 // HW_CFG0: MANUF_STATE +@00035a 000000 // HW_CFG0: MANUF_STATE +@00035b 000000 // HW_CFG0: MANUF_STATE +@00035c 000000 // HW_CFG0: HW_CFG0_DIGEST +@00035d 000000 // HW_CFG0: HW_CFG0_DIGEST +@00035e 000000 // HW_CFG0: HW_CFG0_DIGEST +@00035f 000000 // HW_CFG0: HW_CFG0_DIGEST +@000360 000000 // HW_CFG1: EN_SRAM_IFETCH, HW_CFG1: EN_CSRNG_SW_APP_READ +@000361 000000 // HW_CFG1: DIS_RV_DM_LATE_DEBUG, unallocated +@000362 000000 // unallocated +@000363 000000 // unallocated +@000364 000000 // HW_CFG1: HW_CFG1_DIGEST +@000365 000000 // HW_CFG1: HW_CFG1_DIGEST +@000366 000000 // HW_CFG1: HW_CFG1_DIGEST +@000367 000000 // HW_CFG1: HW_CFG1_DIGEST +@000368 000000 // SECRET0: TEST_UNLOCK_TOKEN +@000369 000000 // SECRET0: TEST_UNLOCK_TOKEN +@00036a 000000 // SECRET0: TEST_UNLOCK_TOKEN +@00036b 000000 // SECRET0: TEST_UNLOCK_TOKEN +@00036c 000000 // SECRET0: TEST_UNLOCK_TOKEN +@00036d 000000 // SECRET0: TEST_UNLOCK_TOKEN +@00036e 000000 // SECRET0: TEST_UNLOCK_TOKEN +@00036f 000000 // SECRET0: TEST_UNLOCK_TOKEN +@000370 000000 // SECRET0: TEST_EXIT_TOKEN +@000371 000000 // SECRET0: TEST_EXIT_TOKEN +@000372 000000 // SECRET0: TEST_EXIT_TOKEN +@000373 000000 // SECRET0: TEST_EXIT_TOKEN +@000374 000000 // SECRET0: TEST_EXIT_TOKEN +@000375 000000 // SECRET0: TEST_EXIT_TOKEN +@000376 000000 // SECRET0: TEST_EXIT_TOKEN +@000377 000000 // SECRET0: TEST_EXIT_TOKEN +@000378 000000 // SECRET0: SECRET0_DIGEST +@000379 000000 // SECRET0: SECRET0_DIGEST +@00037a 000000 // SECRET0: SECRET0_DIGEST +@00037b 000000 // SECRET0: SECRET0_DIGEST +@00037c 000000 // SECRET1: FLASH_ADDR_KEY_SEED +@00037d 000000 // SECRET1: FLASH_ADDR_KEY_SEED +@00037e 000000 // SECRET1: FLASH_ADDR_KEY_SEED +@00037f 000000 // SECRET1: FLASH_ADDR_KEY_SEED +@000380 000000 // SECRET1: FLASH_ADDR_KEY_SEED +@000381 000000 // SECRET1: FLASH_ADDR_KEY_SEED +@000382 000000 // SECRET1: FLASH_ADDR_KEY_SEED +@000383 000000 // SECRET1: FLASH_ADDR_KEY_SEED +@000384 000000 // SECRET1: FLASH_ADDR_KEY_SEED +@000385 000000 // SECRET1: FLASH_ADDR_KEY_SEED +@000386 000000 // SECRET1: FLASH_ADDR_KEY_SEED +@000387 000000 // SECRET1: FLASH_ADDR_KEY_SEED +@000388 000000 // SECRET1: FLASH_ADDR_KEY_SEED +@000389 000000 // SECRET1: FLASH_ADDR_KEY_SEED +@00038a 000000 // SECRET1: FLASH_ADDR_KEY_SEED +@00038b 000000 // SECRET1: FLASH_ADDR_KEY_SEED +@00038c 000000 // SECRET1: FLASH_DATA_KEY_SEED +@00038d 000000 // SECRET1: FLASH_DATA_KEY_SEED +@00038e 000000 // SECRET1: FLASH_DATA_KEY_SEED +@00038f 000000 // SECRET1: FLASH_DATA_KEY_SEED +@000390 000000 // SECRET1: FLASH_DATA_KEY_SEED +@000391 000000 // SECRET1: FLASH_DATA_KEY_SEED +@000392 000000 // SECRET1: FLASH_DATA_KEY_SEED +@000393 000000 // SECRET1: FLASH_DATA_KEY_SEED +@000394 000000 // SECRET1: FLASH_DATA_KEY_SEED +@000395 000000 // SECRET1: FLASH_DATA_KEY_SEED +@000396 000000 // SECRET1: FLASH_DATA_KEY_SEED +@000397 000000 // SECRET1: FLASH_DATA_KEY_SEED +@000398 000000 // SECRET1: FLASH_DATA_KEY_SEED +@000399 000000 // SECRET1: FLASH_DATA_KEY_SEED +@00039a 000000 // SECRET1: FLASH_DATA_KEY_SEED +@00039b 000000 // SECRET1: FLASH_DATA_KEY_SEED +@00039c 000000 // SECRET1: SRAM_DATA_KEY_SEED +@00039d 000000 // SECRET1: SRAM_DATA_KEY_SEED +@00039e 000000 // SECRET1: SRAM_DATA_KEY_SEED +@00039f 000000 // SECRET1: SRAM_DATA_KEY_SEED +@0003a0 000000 // SECRET1: SRAM_DATA_KEY_SEED +@0003a1 000000 // SECRET1: SRAM_DATA_KEY_SEED +@0003a2 000000 // SECRET1: SRAM_DATA_KEY_SEED +@0003a3 000000 // SECRET1: SRAM_DATA_KEY_SEED +@0003a4 000000 // SECRET1: SECRET1_DIGEST +@0003a5 000000 // SECRET1: SECRET1_DIGEST +@0003a6 000000 // SECRET1: SECRET1_DIGEST +@0003a7 000000 // SECRET1: SECRET1_DIGEST +@0003a8 000000 // SECRET2: RMA_TOKEN +@0003a9 000000 // SECRET2: RMA_TOKEN +@0003aa 000000 // SECRET2: RMA_TOKEN +@0003ab 000000 // SECRET2: RMA_TOKEN +@0003ac 000000 // SECRET2: RMA_TOKEN +@0003ad 000000 // SECRET2: RMA_TOKEN +@0003ae 000000 // SECRET2: RMA_TOKEN +@0003af 000000 // SECRET2: RMA_TOKEN +@0003b0 000000 // SECRET2: CREATOR_ROOT_KEY_SHARE0 +@0003b1 000000 // SECRET2: CREATOR_ROOT_KEY_SHARE0 +@0003b2 000000 // SECRET2: CREATOR_ROOT_KEY_SHARE0 +@0003b3 000000 // SECRET2: CREATOR_ROOT_KEY_SHARE0 +@0003b4 000000 // SECRET2: CREATOR_ROOT_KEY_SHARE0 +@0003b5 000000 // SECRET2: CREATOR_ROOT_KEY_SHARE0 +@0003b6 000000 // SECRET2: CREATOR_ROOT_KEY_SHARE0 +@0003b7 000000 // SECRET2: CREATOR_ROOT_KEY_SHARE0 +@0003b8 000000 // SECRET2: CREATOR_ROOT_KEY_SHARE0 +@0003b9 000000 // SECRET2: CREATOR_ROOT_KEY_SHARE0 +@0003ba 000000 // SECRET2: CREATOR_ROOT_KEY_SHARE0 +@0003bb 000000 // SECRET2: CREATOR_ROOT_KEY_SHARE0 +@0003bc 000000 // SECRET2: CREATOR_ROOT_KEY_SHARE0 +@0003bd 000000 // SECRET2: CREATOR_ROOT_KEY_SHARE0 +@0003be 000000 // SECRET2: CREATOR_ROOT_KEY_SHARE0 +@0003bf 000000 // SECRET2: CREATOR_ROOT_KEY_SHARE0 +@0003c0 000000 // SECRET2: CREATOR_ROOT_KEY_SHARE1 +@0003c1 000000 // SECRET2: CREATOR_ROOT_KEY_SHARE1 +@0003c2 000000 // SECRET2: CREATOR_ROOT_KEY_SHARE1 +@0003c3 000000 // SECRET2: CREATOR_ROOT_KEY_SHARE1 +@0003c4 000000 // SECRET2: CREATOR_ROOT_KEY_SHARE1 +@0003c5 000000 // SECRET2: CREATOR_ROOT_KEY_SHARE1 +@0003c6 000000 // SECRET2: CREATOR_ROOT_KEY_SHARE1 +@0003c7 000000 // SECRET2: CREATOR_ROOT_KEY_SHARE1 +@0003c8 000000 // SECRET2: CREATOR_ROOT_KEY_SHARE1 +@0003c9 000000 // SECRET2: CREATOR_ROOT_KEY_SHARE1 +@0003ca 000000 // SECRET2: CREATOR_ROOT_KEY_SHARE1 +@0003cb 000000 // SECRET2: CREATOR_ROOT_KEY_SHARE1 +@0003cc 000000 // SECRET2: CREATOR_ROOT_KEY_SHARE1 +@0003cd 000000 // SECRET2: CREATOR_ROOT_KEY_SHARE1 +@0003ce 000000 // SECRET2: CREATOR_ROOT_KEY_SHARE1 +@0003cf 000000 // SECRET2: CREATOR_ROOT_KEY_SHARE1 +@0003d0 000000 // SECRET2: SECRET2_DIGEST +@0003d1 000000 // SECRET2: SECRET2_DIGEST +@0003d2 000000 // SECRET2: SECRET2_DIGEST +@0003d3 000000 // SECRET2: SECRET2_DIGEST +@0003d4 000000 // LIFE_CYCLE: LC_TRANSITION_CNT +@0003d5 000000 // LIFE_CYCLE: LC_TRANSITION_CNT +@0003d6 000000 // LIFE_CYCLE: LC_TRANSITION_CNT +@0003d7 000000 // LIFE_CYCLE: LC_TRANSITION_CNT +@0003d8 000000 // LIFE_CYCLE: LC_TRANSITION_CNT +@0003d9 000000 // LIFE_CYCLE: LC_TRANSITION_CNT +@0003da 000000 // LIFE_CYCLE: LC_TRANSITION_CNT +@0003db 000000 // LIFE_CYCLE: LC_TRANSITION_CNT +@0003dc 000000 // LIFE_CYCLE: LC_TRANSITION_CNT +@0003dd 000000 // LIFE_CYCLE: LC_TRANSITION_CNT +@0003de 000000 // LIFE_CYCLE: LC_TRANSITION_CNT +@0003df 000000 // LIFE_CYCLE: LC_TRANSITION_CNT +@0003e0 000000 // LIFE_CYCLE: LC_TRANSITION_CNT +@0003e1 000000 // LIFE_CYCLE: LC_TRANSITION_CNT +@0003e2 000000 // LIFE_CYCLE: LC_TRANSITION_CNT +@0003e3 000000 // LIFE_CYCLE: LC_TRANSITION_CNT +@0003e4 000000 // LIFE_CYCLE: LC_TRANSITION_CNT +@0003e5 000000 // LIFE_CYCLE: LC_TRANSITION_CNT +@0003e6 000000 // LIFE_CYCLE: LC_TRANSITION_CNT +@0003e7 000000 // LIFE_CYCLE: LC_TRANSITION_CNT +@0003e8 000000 // LIFE_CYCLE: LC_TRANSITION_CNT +@0003e9 000000 // LIFE_CYCLE: LC_TRANSITION_CNT +@0003ea 000000 // LIFE_CYCLE: LC_TRANSITION_CNT +@0003eb 000000 // LIFE_CYCLE: LC_TRANSITION_CNT +@0003ec 000000 // LIFE_CYCLE: LC_STATE +@0003ed 000000 // LIFE_CYCLE: LC_STATE +@0003ee 000000 // LIFE_CYCLE: LC_STATE +@0003ef 000000 // LIFE_CYCLE: LC_STATE +@0003f0 000000 // LIFE_CYCLE: LC_STATE +@0003f1 000000 // LIFE_CYCLE: LC_STATE +@0003f2 000000 // LIFE_CYCLE: LC_STATE +@0003f3 000000 // LIFE_CYCLE: LC_STATE +@0003f4 000000 // LIFE_CYCLE: LC_STATE +@0003f5 000000 // LIFE_CYCLE: LC_STATE +@0003f6 000000 // LIFE_CYCLE: LC_STATE +@0003f7 000000 // LIFE_CYCLE: LC_STATE +@0003f8 000000 // LIFE_CYCLE: LC_STATE +@0003f9 000000 // LIFE_CYCLE: LC_STATE +@0003fa 000000 // LIFE_CYCLE: LC_STATE +@0003fb 000000 // LIFE_CYCLE: LC_STATE +@0003fc 000000 // LIFE_CYCLE: LC_STATE +@0003fd 000000 // LIFE_CYCLE: LC_STATE +@0003fe 000000 // LIFE_CYCLE: LC_STATE +@0003ff 000000 // LIFE_CYCLE: LC_STATE \ No newline at end of file diff --git a/src/fuse_ctrl/data/otp_ctrl.hjson b/src/fuse_ctrl/data/otp_ctrl.hjson new file mode 100755 index 0000000..6bc2ae4 --- /dev/null +++ b/src/fuse_ctrl/data/otp_ctrl.hjson @@ -0,0 +1,1986 @@ +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// HJSON with partition metadata. +// +// DO NOT EDIT THIS FILE DIRECTLY. +// It has been generated with ./util/design/gen-otp-mmap.py + +{ + name: "caliptra_otp_ctrl", + human_name: " Caliptra One-Time Programmable Memory COntroller", + one_line_desc: "Interfaces integrated one0time programmable memory, supports scrambling, integrity and secure dai_wr_inprogress", + one_paragraph_desc: ''' + One-Time Programmable (OTP) Memory Controller provides an open source abstraction interface for software and other hardware components such as Life Cycle Controller and Key Manager to interact with an integrated, closed source, proprietary OTP memory. + On top of defensive features provided by the proprietary OTP memory to deter side-channel analysis (SCA), fault injection (FI) attacks, and visual and electrical probing, the open source OTP controller features high-level logical security protection such as integrity checks and scrambling, as well as software isolation for when OTP contents are readable and programmable. + It features multiple individually-lockable logical partitions, periodic / persistent checking of OTP values, and a separate partition and interface for Life Cycle Controller. + ''' + // Uique comportablre IP identifier defined under KNOWN_CIP_IDS in the regtool + // TODO: This section needs to be updated for Caliptra (copying OT settings for now, to mark as placeholders) + cip_id: "16", + design_spec: "../doc", + dv_doc: "../doc/dv", + hw_checklist: "../doc/checklist", + sw_checklist: "/sw/device/lib/dif/dif_otp_ctrl", + revisions: [ + { + version: "0.1.0", + life_stage: "L1", + design_stage: "D2", + verification_stage: "V2", + dif_stage: "S1", + commit_id: "127b109e2fab9336e830158abe449a3922544ded", + notes: "", + } + { + version: "1.0.0", + life_stage: "L1", + design_stage: "D3", + verification_stage: "V2S", + dif_stage: "S2", + notes: "", + } + { + version: "2.0.0", + life_stage: "L1", + design_stage: "D2S", + verification_stage: "V2S", + dif_stage: "S2", + notes: "", + } + ] + clocking: [ + {clock: "clk_i", reset: "rst_ni", primary: true}, + {clock: "clk_edn_i", reset: "rst_edn_ni"} + ] + scan: "true", // Enable `scanmode_i` port + scan_reset: "true", // Enable `scan_rst_ni` port + scan_en: "true", // Enable `scan_en_i` port + bus_interfaces: [ + { protocol: "tlul", direction: "device", name: "core" } + { protocol: "tlul", direction: "device", name: "prim", hier_path: "u_otp.gen_generic.u_impl_generic.u_reg_top" } + ], + + available_output_list: [ + { name: "test", + width: 8, + desc: "Test-related GPIOs. Only active in DFT-enabled life cycle states." + } + ], + + /////////////////////////// + // Interrupts and Alerts // + /////////////////////////// + + interrupt_list: [ + { name: "otp_operation_done", + desc: "A direct access command or digest calculation operation has completed." + } + { name: "otp_error", + desc: "An error has occurred in the OTP controller. Check the !!ERR_CODE register to get more information." + } + ], + + alert_list: [ + { name: "fatal_macro_error", + desc: "This alert triggers if hardware detects an uncorrectable error during an OTP transaction, for example an uncorrectable ECC error in the OTP array.", + } + { name: "fatal_check_error", + desc: "This alert triggers if any of the background checks fails. This includes the digest checks and concurrent ECC checks in the buffer registers.", + } + { name: "fatal_bus_integ_error", + desc: "This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected." + } + { name: "fatal_prim_otp_alert", + desc: "Fatal alert triggered inside the OTP primitive, including fatal TL-UL bus integrity faults of the test interface." + } + { name: "recov_prim_otp_alert", + desc: "Recoverable alert triggered inside the OTP primitive." + } + ], + + //////////////// + // Parameters // + //////////////// + param_list: [ + // Init file + { name: "MemInitFile", + desc: "VMEM file to initialize the OTP macro.", + type: "", + default: '""', + expose: "true", + local: "false" + } + // Random netlist constants + { name: "RndCnstLfsrSeed", + desc: "Compile-time random bits for initial LFSR seed", + type: "otp_ctrl_pkg::lfsr_seed_t" + randcount: "40", + randtype: "data", // randomize randcount databits + } + { name: "RndCnstLfsrPerm", + desc: "Compile-time random permutation for LFSR output", + type: "otp_ctrl_pkg::lfsr_perm_t" + randcount: "40", + randtype: "perm", // random permutation for randcount elements + } + { name: "RndCnstScrmblKeyInit", + desc: "Compile-time random permutation for scrambling key/nonce register reset value", + type: "otp_ctrl_pkg::scrmbl_key_init_t" + randcount: "256", + randtype: "data", // random permutation for randcount elements + } + // Normal parameters + { name: "NumSramKeyReqSlots", + desc: "Number of key slots", + type: "int", + default: "4", + local: "true" + }, + { name: "OtpByteAddrWidth", + desc: "Width of the OTP byte address.", + type: "int", + default: "12", + local: "true" + }, + { name: "NumErrorEntries", + desc: "Number of error register entries.", + type: "int", + default: "9", // partitions + DAI/LCI + local: "true" + }, + { name: "NumDaiWords", + desc: "Number of 32bit words in the DAI.", + type: "int", + default: "2", + local: "true" + }, + { name: "NumDigestWords", + desc: "Size of the digest fields in 32bit words.", + type: "int", + default: "2", + local: "true" + }, + { name: "NumSwCfgWindowWords", + desc: "Size of the TL-UL window in 32bit words. Note that the effective partition size is smaller than that.", + type: "int", + default: "1024", + local: "true" + } + + // Memory map Info + { name: "NumPart", + desc: "Number of partitions", + type: "int", + default: "7", + local: "true" + }, + { name: "NumPartUnbuf", + desc: "Number of unbuffered partitions", + type: "int", + default: "2", + local: "true" + }, + { name: "NumPartBuf", + desc: "Number of buffered partitions (including 1 lifecycle partition)", + type: "int", + default: "5", + local: "true" + }, + { name: "VendorTestOffset", + desc: "Offset of the VENDOR_TEST partition", + type: "int", + default: "0", + local: "true" + }, + { name: "VendorTestSize", + desc: "Size of the VENDOR_TEST partition", + type: "int", + default: "64", + local: "true" + }, + { name: "ScratchOffset", + desc: "Offset of SCRATCH", + type: "int", + default: "0", + local: "true" + }, + { name: "ScratchSize", + desc: "Size of SCRATCH", + type: "int", + default: "56", + local: "true" + }, + { name: "VendorTestDigestOffset", + desc: "Offset of VENDOR_TEST_DIGEST", + type: "int", + default: "56", + local: "true" + }, + { name: "VendorTestDigestSize", + desc: "Size of VENDOR_TEST_DIGEST", + type: "int", + default: "8", + local: "true" + }, + { name: "NonSecretFusesOffset", + desc: "Offset of the NON_SECRET_FUSES partition", + type: "int", + default: "64", + local: "true" + }, + { name: "NonSecretFusesSize", + desc: "Size of the NON_SECRET_FUSES partition", + type: "int", + default: "3736", + local: "true" + }, + { name: "FmcKeyManifestSvnOffset", + desc: "Offset of FMC_KEY_MANIFEST_SVN", + type: "int", + default: "64", + local: "true" + }, + { name: "FmcKeyManifestSvnSize", + desc: "Size of FMC_KEY_MANIFEST_SVN", + type: "int", + default: "4", + local: "true" + }, + { name: "RuntimeSvnOffset", + desc: "Offset of RUNTIME_SVN", + type: "int", + default: "68", + local: "true" + }, + { name: "RuntimeSvnSize", + desc: "Size of RUNTIME_SVN", + type: "int", + default: "16", + local: "true" + }, + { name: "LmsVerifyOffset", + desc: "Offset of LMS_VERIFY", + type: "int", + default: "84", + local: "true" + }, + { name: "LmsVerifySize", + desc: "Size of LMS_VERIFY", + type: "int", + default: "4", + local: "true" + }, + { name: "LmsRevocationOffset", + desc: "Offset of LMS_REVOCATION", + type: "int", + default: "88", + local: "true" + }, + { name: "LmsRevocationSize", + desc: "Size of LMS_REVOCATION", + type: "int", + default: "4", + local: "true" + }, + { name: "KeyManifestPkHashMaskOffset", + desc: "Offset of KEY_MANIFEST_PK_HASH_MASK", + type: "int", + default: "92", + local: "true" + }, + { name: "KeyManifestPkHashMaskSize", + desc: "Size of KEY_MANIFEST_PK_HASH_MASK", + type: "int", + default: "4", + local: "true" + }, + { name: "OwnerPkHashOffset", + desc: "Offset of OWNER_PK_HASH", + type: "int", + default: "96", + local: "true" + }, + { name: "OwnerPkHashSize", + desc: "Size of OWNER_PK_HASH", + type: "int", + default: "48", + local: "true" + }, + { name: "IdevidCertAttrOffset", + desc: "Offset of IDEVID_CERT_ATTR", + type: "int", + default: "144", + local: "true" + }, + { name: "IdevidCertAttrSize", + desc: "Size of IDEVID_CERT_ATTR", + type: "int", + default: "96", + local: "true" + }, + { name: "IdevidManufHsmIdOffset", + desc: "Offset of IDEVID_MANUF_HSM_ID", + type: "int", + default: "240", + local: "true" + }, + { name: "IdevidManufHsmIdSize", + desc: "Size of IDEVID_MANUF_HSM_ID", + type: "int", + default: "16", + local: "true" + }, + { name: "SocSteppingIdOffset", + desc: "Offset of SOC_STEPPING_ID", + type: "int", + default: "256", + local: "true" + }, + { name: "SocSteppingIdSize", + desc: "Size of SOC_STEPPING_ID", + type: "int", + default: "4", + local: "true" + }, + { name: "NonSecretFusesDigestOffset", + desc: "Offset of NON_SECRET_FUSES_DIGEST", + type: "int", + default: "3792", + local: "true" + }, + { name: "NonSecretFusesDigestSize", + desc: "Size of NON_SECRET_FUSES_DIGEST", + type: "int", + default: "8", + local: "true" + }, + { name: "Secret0Offset", + desc: "Offset of the SECRET0 partition", + type: "int", + default: "3800", + local: "true" + }, + { name: "Secret0Size", + desc: "Size of the SECRET0 partition", + type: "int", + default: "40", + local: "true" + }, + { name: "TestUnlockTokenOffset", + desc: "Offset of TEST_UNLOCK_TOKEN", + type: "int", + default: "3800", + local: "true" + }, + { name: "TestUnlockTokenSize", + desc: "Size of TEST_UNLOCK_TOKEN", + type: "int", + default: "16", + local: "true" + }, + { name: "TestExitTokenOffset", + desc: "Offset of TEST_EXIT_TOKEN", + type: "int", + default: "3816", + local: "true" + }, + { name: "TestExitTokenSize", + desc: "Size of TEST_EXIT_TOKEN", + type: "int", + default: "16", + local: "true" + }, + { name: "Secret0DigestOffset", + desc: "Offset of SECRET0_DIGEST", + type: "int", + default: "3832", + local: "true" + }, + { name: "Secret0DigestSize", + desc: "Size of SECRET0_DIGEST", + type: "int", + default: "8", + local: "true" + }, + { name: "Secret1Offset", + desc: "Offset of the SECRET1 partition", + type: "int", + default: "3840", + local: "true" + }, + { name: "Secret1Size", + desc: "Size of the SECRET1 partition", + type: "int", + default: "56", + local: "true" + }, + { name: "UdsSeedOffset", + desc: "Offset of UDS_SEED", + type: "int", + default: "3840", + local: "true" + }, + { name: "UdsSeedSize", + desc: "Size of UDS_SEED", + type: "int", + default: "48", + local: "true" + }, + { name: "Secret1DigestOffset", + desc: "Offset of SECRET1_DIGEST", + type: "int", + default: "3888", + local: "true" + }, + { name: "Secret1DigestSize", + desc: "Size of SECRET1_DIGEST", + type: "int", + default: "8", + local: "true" + }, + { name: "Secret2Offset", + desc: "Offset of the SECRET2 partition", + type: "int", + default: "3896", + local: "true" + }, + { name: "Secret2Size", + desc: "Size of the SECRET2 partition", + type: "int", + default: "40", + local: "true" + }, + { name: "FieldEntropyOffset", + desc: "Offset of FIELD_ENTROPY", + type: "int", + default: "3896", + local: "true" + }, + { name: "FieldEntropySize", + desc: "Size of FIELD_ENTROPY", + type: "int", + default: "32", + local: "true" + }, + { name: "Secret2DigestOffset", + desc: "Offset of SECRET2_DIGEST", + type: "int", + default: "3928", + local: "true" + }, + { name: "Secret2DigestSize", + desc: "Size of SECRET2_DIGEST", + type: "int", + default: "8", + local: "true" + }, + { name: "Secret3Offset", + desc: "Offset of the SECRET3 partition", + type: "int", + default: "3936", + local: "true" + }, + { name: "Secret3Size", + desc: "Size of the SECRET3 partition", + type: "int", + default: "72", + local: "true" + }, + { name: "KeyManifestPkHashOffset", + desc: "Offset of KEY_MANIFEST_PK_HASH", + type: "int", + default: "3936", + local: "true" + }, + { name: "KeyManifestPkHashSize", + desc: "Size of KEY_MANIFEST_PK_HASH", + type: "int", + default: "48", + local: "true" + }, + { name: "RmaTokenOffset", + desc: "Offset of RMA_TOKEN", + type: "int", + default: "3984", + local: "true" + }, + { name: "RmaTokenSize", + desc: "Size of RMA_TOKEN", + type: "int", + default: "16", + local: "true" + }, + { name: "Secret3DigestOffset", + desc: "Offset of SECRET3_DIGEST", + type: "int", + default: "4000", + local: "true" + }, + { name: "Secret3DigestSize", + desc: "Size of SECRET3_DIGEST", + type: "int", + default: "8", + local: "true" + }, + { name: "LifeCycleOffset", + desc: "Offset of the LIFE_CYCLE partition", + type: "int", + default: "4008", + local: "true" + }, + { name: "LifeCycleSize", + desc: "Size of the LIFE_CYCLE partition", + type: "int", + default: "88", + local: "true" + }, + { name: "LcTransitionCntOffset", + desc: "Offset of LC_TRANSITION_CNT", + type: "int", + default: "4008", + local: "true" + }, + { name: "LcTransitionCntSize", + desc: "Size of LC_TRANSITION_CNT", + type: "int", + default: "48", + local: "true" + }, + { name: "LcStateOffset", + desc: "Offset of LC_STATE", + type: "int", + default: "4056", + local: "true" + }, + { name: "LcStateSize", + desc: "Size of LC_STATE", + type: "int", + default: "40", + local: "true" + }, + ] + + ///////////////////////////// + // Intermodule Connections // + ///////////////////////////// + + inter_signal_list: [ + // OTP dedicated power connection from AST + { struct: "" + type: "io" + name: "otp_ext_voltage_h" + act: "none" + default: "'0" + package: "", + } + // Power sequencing signals to AST + { struct: "otp_ast_req" + type: "uni" + name: "otp_ast_pwr_seq" + act: "req" + default: "'0" + package: "otp_ctrl_pkg" + desc: "Power sequencing signals to AST (VDD domain)." + } + // Power sequencing signals from AST + { struct: "otp_ast_rsp" + type: "uni" + name: "otp_ast_pwr_seq_h" + act: "rcv" + default: "'0" + package: "otp_ctrl_pkg" + desc: "Power sequencing signals coming from AST (VCC domain)." + } + // EDN interface + { struct: "edn" + type: "req_rsp" + name: "edn" + act: "req" + package: "edn_pkg" + desc: "Entropy request to the entropy distribution network for LFSR reseeding and ephemeral key derivation." + } + // Power manager init command + { struct: "pwr_otp" + type: "req_rsp" + name: "pwr_otp" + act: "rsp" + default: "'0" + package: "pwrmgr_pkg" + desc: "Initialization request/acknowledge from/to power manager." + } + // Macro-specific test signals to/from LC TAP + { struct: "lc_otp_vendor_test" + type: "req_rsp" + name: "lc_otp_vendor_test" + act: "rsp" + default: "'0" + package: "otp_ctrl_pkg" + desc: "Vendor test control signals from/to the life cycle TAP." + } + // LC transition command + { struct: "lc_otp_program" + type: "req_rsp" + name: "lc_otp_program" + act: "rsp" + default: "'0" + package: "otp_ctrl_pkg" + desc: "Life cycle state transition interface." + } + // Broadcast to LC + { struct: "otp_lc_data" + type: "uni" + name: "otp_lc_data" + act: "req" + default: "'0" + package: "otp_ctrl_pkg" + desc: ''' + Life cycle state output holding the current life cycle state, + the value of the transition counter and the tokens needed for life cycle transitions. + ''' + } + // Broadcast from LC + { struct: "lc_tx" + type: "uni" + name: "lc_escalate_en" + act: "rcv" + default: "lc_ctrl_pkg::Off" + package: "lc_ctrl_pkg" + desc: ''' + Life cycle escalation enable coming from life cycle controller. + This signal moves all FSMs within OTP into the error state. + ''' + } + { struct: "lc_tx" + type: "uni" + name: "lc_creator_seed_sw_rw_en" + act: "rcv" + default: "lc_ctrl_pkg::Off" + package: "lc_ctrl_pkg" + desc: ''' + Provision enable qualifier coming from life cycle controller. + This signal enables SW read / write access to the RMA_TOKEN and CREATOR_ROOT_KEY_SHARE0 and CREATOR_ROOT_KEY_SHARE1. + ''' + } + { struct: "lc_tx" + type: "uni" + name: "lc_owner_seed_sw_rw_en" + act: "rcv" + default: "lc_ctrl_pkg::Off" + package: "lc_ctrl_pkg" + desc: ''' + Provision enable qualifier coming from life cycle controller. + This signal enables SW read / write access to the OWNER_SEED. + ''' + } + { struct: "lc_tx" + type: "uni" + name: "lc_seed_hw_rd_en" + act: "rcv" + default: "lc_ctrl_pkg::Off" + package: "lc_ctrl_pkg" + desc: ''' + Seed read enable coming from life cycle controller. + This signal enables HW read access to the CREATOR_ROOT_KEY_SHARE0 and CREATOR_ROOT_KEY_SHARE1. + ''' + } + { struct: "lc_tx" + type: "uni" + name: "lc_dft_en" + act: "rcv" + default: "lc_ctrl_pkg::Off" + package: "lc_ctrl_pkg" + desc: ''' + Test enable qualifier coming from life cycle controller. + This signals enables the TL-UL access port to the proprietary OTP IP. + ''' + } + { struct: "lc_tx" + type: "uni" + name: "lc_check_byp_en" + act: "rcv" + default: "lc_ctrl_pkg::Off" + package: "lc_ctrl_pkg" + desc: ''' + Life cycle partition check bypass signal. + This signal causes the life cycle partition to bypass consistency checks during life cycle state transitions in order to prevent spurious consistency check failures. + ''' + } + // Broadcast to Key Manager + { struct: "otp_keymgr_key" + type: "uni" + name: "otp_keymgr_key" + act: "req" + default: "'0" + package: "otp_ctrl_pkg" + desc: "Key output to the key manager holding CREATOR_ROOT_KEY_SHARE0 and CREATOR_ROOT_KEY_SHARE1." + } + // Broadcast to Flash Controller + { struct: "flash_otp_key" + type: "req_rsp" + name: "flash_otp_key" + act: "rsp" + default: "'0" + package: "otp_ctrl_pkg" + desc: "Key derivation interface for FLASH scrambling." + } + // Key request from SRAM scramblers + { struct: "sram_otp_key" + // TODO: would be nice if this could accept parameters. + // Split this out into an issue. + width: "4" + type: "req_rsp" + name: "sram_otp_key" + act: "rsp" + default: "'0" + package: "otp_ctrl_pkg" + desc: "Array with key derivation interfaces for SRAM scrambling devices." + } + // Key request from OTBN RAM Scrambler + { struct: "otbn_otp_key" + type: "req_rsp" + name: "otbn_otp_key" + act: "rsp" + default: "'0" + package: "otp_ctrl_pkg" + desc: "Key derivation interface for OTBN scrambling devices." + } + // Hardware config partition + { struct: "otp_broadcast" + type: "uni" + name: "otp_broadcast" + act: "req" + default: "'0" + package: "otp_ctrl_part_pkg" + desc: "Output of the HW partitions with breakout data types." + } + // AST observability control + { struct: "ast_obs_ctrl", + type: "uni", + name: "obs_ctrl", + act: "rcv", + package: "ast_pkg" + desc: "AST observability control signals." + } + // prim otp observe bus + { struct: "logic", + type: "uni", + name: "otp_obs", + act: "req", + width: "8", + package: "" + desc: "AST observability bus." + } + ] // inter_signal_list + + ///////////////////// + // Countermeasures // + ///////////////////// + + countermeasures: [ + { name: "BUS.INTEGRITY", + desc: "End-to-end bus integrity scheme." + } + { name: "SECRET.MEM.SCRAMBLE", + desc: "Secret partitions are scrambled with a full-round PRESENT cipher." + } + { name: "PART.MEM.DIGEST", + desc: "Integrity of buffered partitions is ensured via a 64bit digest." + } + { name: "DAI.FSM.SPARSE", + desc: "The direct access interface FSM is sparsely encoded." + } + { name: "KDI.FSM.SPARSE", + desc: "The key derivation interface FSM is sparsely encoded." + } + { name: "LCI.FSM.SPARSE", + desc: "The life cycle interface FSM is sparsely encoded." + } + { name: "PART.FSM.SPARSE", + desc: "The partition FSMs are sparsely encoded." + } + { name: "SCRMBL.FSM.SPARSE", + desc: "The scramble datapath FSM is sparsely encoded." + } + { name: "TIMER.FSM.SPARSE", + desc: "The background check timer FSM is sparsely encoded." + } + { name: "DAI.CTR.REDUN", + desc: "The direct access interface address counter employs a cross-counter implementation." + } + { name: "KDI_SEED.CTR.REDUN", + desc: "The key derivation interface counter employs a cross-counter implementation." + } + { name: "KDI_ENTROPY.CTR.REDUN", + desc: "The key derivation entropy counter employs a cross-counter implementation." + } + { name: "LCI.CTR.REDUN", + desc: "The life cycle interface address counter employs a cross-counter implementation." + } + { name: "PART.CTR.REDUN", + desc: "The address counter of buffered partitions employs a cross-counter implementation." + } + { name: "SCRMBL.CTR.REDUN", + desc: "The srambling datapath counter employs a cross-counter implementation." + } + { name: "TIMER_INTEG.CTR.REDUN", + desc: "The background integrity check timer employs a duplicated counter implementation." + } + { name: "TIMER_CNSTY.CTR.REDUN", + desc: "The background consistency check timer employs a duplicated counter implementation." + } + { name: "TIMER.LFSR.REDUN", + desc: "The background check LFSR is duplicated." + } + { name: "DAI.FSM.LOCAL_ESC", + desc: "The direct access interface FSM is moved into an invalid state upon local escalation." + } + { name: "LCI.FSM.LOCAL_ESC", + desc: "The life cycle interface FSM is moved into an invalid state upon local escalation." + } + { name: "KDI.FSM.LOCAL_ESC", + desc: "The key derivation interface FSM is moved into an invalid state upon local escalation." + } + { name: "PART.FSM.LOCAL_ESC", + desc: "The partition FSMs are moved into an invalid state upon local escalation." + } + { name: "SCRMBL.FSM.LOCAL_ESC", + desc: "The scramble datapath FSM is moved into an invalid state upon local escalation." + } + { name: "TIMER.FSM.LOCAL_ESC", + desc: "The background check timer FSM is moved into an invalid state upon local escalation." + } + { name: "DAI.FSM.GLOBAL_ESC", + desc: "The direct access interface FSM is moved into an invalid state upon global escalation via life cycle." + } + { name: "LCI.FSM.GLOBAL_ESC", + desc: "The life cycle interface FSM is moved into an invalid state upon global escalation via life cycle." + } + { name: "KDI.FSM.GLOBAL_ESC", + desc: "The key derivation interface FSM is moved into an invalid state upon global escalation via life cycle." + } + { name: "PART.FSM.GLOBAL_ESC", + desc: "The partition FSMs are moved into an invalid state upon global escalation via life cycle." + } + { name: "SCRMBL.FSM.GLOBAL_ESC", + desc: "The scramble datapath FSM is moved into an invalid state upon global escalation via life cycle." + } + { name: "TIMER.FSM.GLOBAL_ESC", + desc: "The background check timer FSM is moved into an invalid state upon global escalation via life cycle." + } + { name: "PART.DATA_REG.INTEGRITY", + desc: "All partition buffer registers are protected with ECC on 64bit blocks." + } + { name: "PART.DATA_REG.BKGN_CHK", + desc: "The digest of buffered partitions is recomputed and checked at pseudorandom intervals in the background." + } + { name: "PART.MEM.REGREN" + desc: "Unbuffered ('software') partitions can be read-locked via a CSR until the next system reset." + } + { name: "PART.MEM.SW_UNREADABLE" + desc: "Secret buffered partitions become unreadable to software once they are locked via the digest." + } + { name: "PART.MEM.SW_UNWRITABLE" + desc: "All partitions become unwritable by software once they are locked via the digest." + } + { name: "LC_PART.MEM.SW_NOACCESS" + desc: "The life cycle partition is not directly readable nor writable via software." + } + { name: "ACCESS.CTRL.MUBI", + desc: "The access control signals going from the partitions to the DAI are MUBI encoded." + } + { name: "TOKEN_VALID.CTRL.MUBI", + desc: "The token valid signals going to the life cycle controller are MUBI encoded." + } + { name: "LC_CTRL.INTERSIG.MUBI", + desc: "The life cycle control signals are multibit encoded." + } + { name: "TEST.BUS.LC_GATED", + desc: "Prevent access to test signals and the OTP backdoor interface in non-test lifecycle states." + } + { name: "TEST_TL_LC_GATE.FSM.SPARSE", + desc: "The control FSM inside the TL-UL gating primitive is sparsely encoded." + } + { name: "DIRECT_ACCESS.CONFIG.REGWEN", + desc: "The direct access CSRs are REGWEN protected." + } + { name: "CHECK_TRIGGER.CONFIG.REGWEN", + desc: "The check trigger CSR is REGWEN protected." + } + { name: "CHECK.CONFIG.REGWEN", + desc: "The check CSR is REGWEN protected." + } + { name: "MACRO.MEM.INTEGRITY", + desc: ''' + The OTP macro employs a vendor-specific integrity scheme at the granularity of the native 16bit OTP words. + The scheme is able to at least detect single bit errors. + ''' + } + { name: "MACRO.MEM.CM", + desc: "The OTP macro may contain additional vendor-specific countermeasures." + } + ] + + features: [ + { + name: "OTP_CTRL.PARTITION.VENDOR_TEST" + desc: '''Vendor test partition is used for OTP programming smoke check during manufacturing flow. + In this partition, ECC uncorrectable errors will not lead to fatal errors and alerts. + Instead the error will be reported as correctable ECC error. + ''' + } + { + name: "OTP_CTRL.PARTITION.CREATOR_SW_CFG" + desc: '''During calibration stage, various parameters (clock, voltage, and timing sources) are calibrated and recorded to CREATOR_SW_CFG partition. + ''' + } + { + name: "OTP_CTRL.INIT" + desc: '''When power is up, OTP controller reads devices status. + After all reads complete, the controller performs integrity check on the HW_CFG* and SECRET partitions. + Once all integrity checks are complete, the controller marks outputs as valid. + ''' + } + { + name: "OTP_CTRL.PROGRAM" + desc: '''All other partitions except life cycle partition are programmed through DAI interface. + And once non-zero digest is programmed to these partition, no further write access is allowed. + Life cycle partition is programmed by LC_CTRL. + ''' + } + { + name: "OTP_CTRL.PARTITION.SECRET0" + desc: "Obfuscated UDS Seed" + } + { + name: "OTP_CTRL.PARTITION.SECRET1" + desc: "Obfuscated Field Entropy" + } + { + name: "OTP_CTRL.PARTITION.LIFE_CYCLE" + desc: '''LC state, LC transition count. + This feature is owned by the LC_CTRL and cannot be tested well through the OTP_CTRL CSR interface. + ''' + } + { + name: "OTP_CTRL.PARTITIONS_FEATURE.READ_LOCK" + desc: '''Following partitions can be read lockable by CSR. + - VENDOR_TEST + - CREATOR_SW_CFG + Following partitions can be read lockable by writing digest. + - SECRET0 + - SECRET1 + All read attempt to these partitions after read is locked will trigger AccessError (recoverable). + ''' + } + { + name: "OTP_CTRL.PARTITIONS_FEATURE.WRITE_LOCK" + desc: "All partitions except LIFE_CYCLE can be write lockable by writing digest." + } + { + name: "OTP_CTRL.ERROR_HANDLING.RECOVERABLE" + desc: "Recoverable error is created when unauthorized access atempt are detected via dai interface." + } + { + name: "OTP_CTRL.ERROR_HANDLING.FATAL" + desc: "Unrecoverable errors are created for uncorrectable ecc error, otp macro malfunction and unauthorized access via lc_ctrl." + } + { + name: "OTP_CTRL.BACKGROUND_CHECK.CHECK_TIMEOUT" + desc: "Timeout value for the integrity and consistency checks." + } + { + name: "OTP_CTRL.BACKGROUND_CHECK.INTEGRITY_CHECK_PERIOD" + desc: "The interval which the digest of the partition is recomputed to check integrity of locked partition." + } + { + name: "OTP_CTRL.BACKGROUND_CHECK.CONSISTENCY_CHECK_PERIOD" + desc: "Re-read period of the buffer registers to ensure data is matched with the associated OTP partition." + } + ] + + /////////////// + // Registers // + /////////////// + + regwidth: "32", + registers: { + core: [ + //////////////////////// + // Ctrl / Status CSRs // + //////////////////////// + + { name: "STATUS", + desc: "OTP status register.", + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + resval: 0, + tags: [ // OTP internal HW can modify status register + "excl:CsrAllTests:CsrExclCheck"], + fields: [ + { bits: "0" + name: "VENDOR_TEST_ERROR" + desc: ''' + Set to 1 if an error occurred in this partition. + If set to 1, SW should check the !!ERR_CODE register at the corresponding index. + ''' + } + { bits: "1" + name: "NON_SECRET_FUSES_ERROR" + desc: ''' + Set to 1 if an error occurred in this partition. + If set to 1, SW should check the !!ERR_CODE register at the corresponding index. + ''' + } + { bits: "2" + name: "SECRET0_ERROR" + desc: ''' + Set to 1 if an error occurred in this partition. + If set to 1, SW should check the !!ERR_CODE register at the corresponding index. + ''' + } + { bits: "3" + name: "SECRET1_ERROR" + desc: ''' + Set to 1 if an error occurred in this partition. + If set to 1, SW should check the !!ERR_CODE register at the corresponding index. + ''' + } + { bits: "4" + name: "SECRET2_ERROR" + desc: ''' + Set to 1 if an error occurred in this partition. + If set to 1, SW should check the !!ERR_CODE register at the corresponding index. + ''' + } + { bits: "5" + name: "SECRET3_ERROR" + desc: ''' + Set to 1 if an error occurred in this partition. + If set to 1, SW should check the !!ERR_CODE register at the corresponding index. + ''' + } + { bits: "6" + name: "LIFE_CYCLE_ERROR" + desc: ''' + Set to 1 if an error occurred in this partition. + If set to 1, SW should check the !!ERR_CODE register at the corresponding index. + ''' + } + { bits: "7" + name: "DAI_ERROR" + desc: ''' + Set to 1 if an error occurred in the DAI. + If set to 1, SW should check the !!ERR_CODE register at the corresponding index. + ''' + } + { bits: "8" + name: "LCI_ERROR" + desc: ''' + Set to 1 if an error occurred in the LCI. + If set to 1, SW should check the !!ERR_CODE register at the corresponding index. + ''' + } + { bits: "9" + name: "TIMEOUT_ERROR" + desc: ''' + Set to 1 if an integrity or consistency check times out. + This raises an fatal_check_error alert and is an unrecoverable error condition. + ''' + } + { bits: "10" + name: "LFSR_FSM_ERROR" + desc: ''' + Set to 1 if the LFSR timer FSM has reached an invalid state. + This raises an fatal_check_error alert and is an unrecoverable error condition. + ''' + } + { bits: "11" + name: "SCRAMBLING_FSM_ERROR" + desc: ''' + Set to 1 if the scrambling datapath FSM has reached an invalid state. + This raises an fatal_check_error alert and is an unrecoverable error condition. + ''' + } + { bits: "12" + name: "KEY_DERIV_FSM_ERROR" + desc: ''' + Set to 1 if the key derivation FSM has reached an invalid state. + This raises an fatal_check_error alert and is an unrecoverable error condition. + ''' + } + { bits: "13" + name: "BUS_INTEG_ERROR" + desc: ''' + This bit is set to 1 if a fatal bus integrity fault is detected. + This error triggers a fatal_bus_integ_error alert. + ''' + } + { bits: "14" + name: "DAI_IDLE" + desc: "Set to 1 if the DAI is idle and ready to accept commands." + } + { bits: "15" + name: "CHECK_PENDING" + desc: "Set to 1 if an integrity or consistency check triggered by the LFSR timer or via !!CHECK_TRIGGER is pending." + } + ] + } + { multireg: { + name: "ERR_CODE", + desc: ''' + This register holds information about error conditions that occurred in the agents + interacting with the OTP macro via the internal bus. The error codes should be checked + if the partitions, DAI or LCI flag an error in the !!STATUS register, or when an + !!INTR_STATE.otp_error has been triggered. Note that all errors trigger an otp_error + interrupt, and in addition some errors may trigger either an fatal_macro_error or an + fatal_check_error alert. + ''', + count: "NumErrorEntries", + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + cname: "AGENT", + compact: "false", + resval: 0, + tags: [ // OTP internal HW can modify the error code registers + "excl:CsrAllTests:CsrExclCheck"], + fields: [ + { + bits: "2:0" + enum: [ + { value: "0", + name: "NO_ERROR", + desc: ''' + No error condition has occurred. + ''' + }, + { value: "1", + name: "MACRO_ERROR", + desc: ''' + Returned if the OTP macro command was invalid or did not complete successfully + due to a macro malfunction. + This error should never occur during normal operation and is not recoverable. + This error triggers an fatal_macro_error alert. + ''' + }, + { value: "2", + name: "MACRO_ECC_CORR_ERROR", + desc: ''' + A correctable ECC error has occured during an OTP read operation. + The corresponding controller automatically recovers from this error when + issuing a new command. + ''' + }, + { value: "3", + name: "MACRO_ECC_UNCORR_ERROR", + desc: ''' + An uncorrectable ECC error has occurred during an OTP read operation. + This error should never occur during normal operation and is not recoverable. + If this error is present this may be a sign that the device is malfunctioning. + This error triggers an fatal_macro_error alert. + ''' + }, + { value: "4", + name: "MACRO_WRITE_BLANK_ERROR", + desc: ''' + This error is returned if a programming operation attempted to clear a bit that has previously been programmed to 1. + The corresponding controller automatically recovers from this error when issuing a new command. + + Note however that the affected OTP word may be left in an inconsistent state if this error occurs. + This can cause several issues when the word is accessed again (either as part of a regular read operation, as part of the readout at boot, or as part of a background check). + + It is important that SW ensures that each word is only written once, since this can render the device useless. + ''' + }, + { value: "5", + name: "ACCESS_ERROR", + desc: ''' + This error indicates that a locked memory region has been accessed. + The corresponding controller automatically recovers from this error when issuing a new command. + ''' + }, + { value: "6", + name: "CHECK_FAIL_ERROR", + desc: ''' + An ECC, integrity or consistency mismatch has been detected in the buffer registers. + This error should never occur during normal operation and is not recoverable. + This error triggers an fatal_check_error alert. + ''' + }, + { value: "7", + name: "FSM_STATE_ERROR", + desc: ''' + The FSM of the corresponding controller has reached an invalid state, or the FSM has + been moved into a terminal error state due to an escalation action via lc_escalate_en_i. + This error should never occur during normal operation and is not recoverable. + If this error is present, this is a sign that the device has fallen victim to + an invasive attack. This error triggers an fatal_check_error alert. + ''' + }, + ] + } + ] + } + } + { name: "DIRECT_ACCESS_REGWEN", + desc: ''' + Register write enable for all direct access interface registers. + ''', + swaccess: "rw0c", + hwaccess: "hrw", + hwext: "true", + hwqe: "true", + tags: [ // OTP internal HW will set this enable register to 0 when OTP is not under IDLE + // state, so could not auto-predict its value + "excl:CsrNonInitTests:CsrExclCheck"], + fields: [ + { + bits: "0", + desc: ''' + This bit controls whether the DAI registers can be written. + Write 0 to it in order to clear the bit. + + Note that the hardware also modulates this bit and sets it to 0 temporarily + during an OTP operation such that the corresponding address and data registers + cannot be modified while an operation is pending. The !!DAI_IDLE status bit + will also be set to 0 in such a case. + ''' + resval: 1, + }, + ] + }, + { name: "DIRECT_ACCESS_CMD", + desc: "Command register for direct accesses.", + swaccess: "r0w1c", + hwaccess: "hro", + hwqe: "true", + hwext: "true", + resval: 0, + regwen: "DIRECT_ACCESS_REGWEN", + tags: [ // Write to DIRECT_ACCESS_CMD randomly might cause OTP_ERRORs and illegal sequences + "excl:CsrNonInitTests:CsrExclWrite"], + fields: [ + { bits: "0", + name: "RD", + desc: ''' + Initiates a readout sequence that reads the location specified + by !!DIRECT_ACCESS_ADDRESS. The command places the data read into + !!DIRECT_ACCESS_RDATA_0 and !!DIRECT_ACCESS_RDATA_1 (for 64bit partitions). + ''' + } + { bits: "1", + name: "WR", + desc: ''' + Initiates a programming sequence that writes the data in !!DIRECT_ACCESS_WDATA_0 + and !!DIRECT_ACCESS_WDATA_1 (for 64bit partitions) to the location specified by + !!DIRECT_ACCESS_ADDRESS. + ''' + } + { bits: "2", + name: "DIGEST", + desc: ''' + Initiates the digest calculation and locking sequence for the partition specified by + !!DIRECT_ACCESS_ADDRESS. + ''' + } + ] + } + { name: "DIRECT_ACCESS_ADDRESS", + desc: "Address register for direct accesses.", + swaccess: "rw", + hwaccess: "hro", + hwqe: "false", + resval: 0, + regwen: "DIRECT_ACCESS_REGWEN", + tags: [ // The enable register "DIRECT_ACCESS_REGWEN" is HW controlled, + // so not able to predict this register value automatically + "excl:CsrNonInitTests:CsrExclCheck"], + fields: [ + { bits: "OtpByteAddrWidth-1:0", + desc: ''' + This is the address for the OTP word to be read or written through + the direct access interface. Note that the address is aligned to the access size + internally, hence bits 1:0 are ignored for 32bit accesses, and bits 2:0 are ignored + for 64bit accesses. + + For the digest calculation command, set this register to the partition base offset. + ''' + } + ] + } + { multireg: { + name: "DIRECT_ACCESS_WDATA", + desc: '''Write data for direct accesses. + Hardware automatically determines the access granule (32bit or 64bit) based on which + partition is being written to. + ''', + count: "NumDaiWords", // 2 x 32bit = 64bit + swaccess: "rw", + hwaccess: "hro", + hwqe: "false", + regwen: "DIRECT_ACCESS_REGWEN", + cname: "WORD", + resval: 0, + tags: [ // The value of this register is written from "DIRECT_ACCESS_RDATA", + // so could not predict this register value automatically + "excl:CsrAllTests:CsrExclCheck"], + fields: [ + { bits: "31:0" + } + ] + } + }, + { multireg: { + name: "DIRECT_ACCESS_RDATA", + desc: '''Read data for direct accesses. + Hardware automatically determines the access granule (32bit or 64bit) based on which + partition is read from. + ''', + count: "NumDaiWords", // 2 x 32bit = 64bit + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + cname: "WORD", + resval: 0, + fields: [ + { bits: "31:0" + } + ] + } + }, + + ////////////////////////////////////// + // Integrity and Consistency Checks // + ////////////////////////////////////// + { name: "CHECK_TRIGGER_REGWEN", + desc: ''' + Register write enable for !!CHECK_TRIGGER. + ''', + swaccess: "rw0c", + hwaccess: "none", + fields: [ + { bits: "0", + desc: ''' + When cleared to 0, the !!CHECK_TRIGGER register cannot be written anymore. + Write 0 to clear this bit. + ''' + resval: 1, + }, + ] + }, + { name: "CHECK_TRIGGER", + desc: "Command register for direct accesses.", + swaccess: "r0w1c", + hwaccess: "hro", + hwqe: "true", + hwext: "true", + resval: 0, + regwen: "CHECK_TRIGGER_REGWEN", + fields: [ + { bits: "0", + name: "INTEGRITY", + desc: ''' + Writing 1 to this bit triggers an integrity check. SW should monitor !!STATUS.CHECK_PENDING + and wait until the check has been completed. If there are any errors, those will be flagged + in the !!STATUS and !!ERR_CODE registers, and via the interrupts and alerts. + ''' + } + { bits: "1", + name: "CONSISTENCY", + desc: ''' + Writing 1 to this bit triggers a consistency check. SW should monitor !!STATUS.CHECK_PENDING + and wait until the check has been completed. If there are any errors, those will be flagged + in the !!STATUS and !!ERR_CODE registers, and via interrupts and alerts. + ''' + } + ] + }, + { name: "CHECK_REGWEN", + desc: ''' + Register write enable for !!INTEGRITY_CHECK_PERIOD and !!CONSISTENCY_CHECK_PERIOD. + ''', + swaccess: "rw0c", + hwaccess: "none", + fields: [ + { bits: "0", + desc: ''' + When cleared to 0, !!INTEGRITY_CHECK_PERIOD and !!CONSISTENCY_CHECK_PERIOD registers cannot be written anymore. + Write 0 to clear this bit. + ''' + resval: 1, + }, + ] + }, + { name: "CHECK_TIMEOUT", + desc: ''' + Timeout value for the integrity and consistency checks. + ''', + swaccess: "rw", + hwaccess: "hro", + regwen: "CHECK_REGWEN", + tags: [ // Do not write to this automatically, as it may trigger fatal alert, and cause + // escalation. + "excl:CsrAllTests:CsrExclWrite"], + fields: [ + { bits: "31:0", + desc: ''' + Timeout value in cycles for the for the integrity and consistency checks. If an integrity or consistency + check does not complete within the timeout window, an error will be flagged in the !!STATUS register, + an otp_error interrupt will be raised, and an fatal_check_error alert will be sent out. The timeout should + be set to a large value to stay on the safe side. The maximum check time can be upper bounded by the + number of cycles it takes to readout, scramble and digest the entire OTP array. Since this amounts to + roughly 25k cycles, it is recommended to set this value to at least 100'000 cycles in order to stay on the + safe side. A value of zero disables the timeout mechanism (default). + ''' + resval: 0, + }, + ] + }, + { name: "INTEGRITY_CHECK_PERIOD", + desc: ''' + This value specifies the maximum period that can be generated pseudo-randomly. + Only applies to the HW_CFG* and SECRET* partitions once they are locked. + ''' + swaccess: "rw", + hwaccess: "hro", + regwen: "CHECK_REGWEN", + fields: [ + { bits: "31:0", + desc: ''' + The pseudo-random period is generated using a 40bit LFSR internally, and this register defines + the bit mask to be applied to the LFSR output in order to limit its range. The value of this + register is left shifted by 8bits and the lower bits are set to 8'hFF in order to form the 40bit mask. + A recommended value is 0x3_FFFF, corresponding to a maximum period of ~2.8s at 24MHz. + A value of zero disables the timer (default). Note that a one-off check can always be triggered via + !!CHECK_TRIGGER.INTEGRITY. + ''' + resval: "0" + } + ] + } + { name: "CONSISTENCY_CHECK_PERIOD", + desc: ''' + This value specifies the maximum period that can be generated pseudo-randomly. + This applies to the LIFE_CYCLE partition and the HW_CFG* and SECRET* partitions once they are locked. + ''' + swaccess: "rw", + hwaccess: "hro", + regwen: "CHECK_REGWEN", + fields: [ + { bits: "31:0", + desc: ''' + The pseudo-random period is generated using a 40bit LFSR internally, and this register defines + the bit mask to be applied to the LFSR output in order to limit its range. The value of this + register is left shifted by 8bits and the lower bits are set to 8'hFF in order to form the 40bit mask. + A recommended value is 0x3FF_FFFF, corresponding to a maximum period of ~716s at 24MHz. + A value of zero disables the timer (default). Note that a one-off check can always be triggered via + !!CHECK_TRIGGER.CONSISTENCY. + ''' + resval: "0" + } + ] + } + + //////////////////////////////////// + // Dynamic Locks of SW Parititons // + //////////////////////////////////// + { name: "VENDOR_TEST_READ_LOCK", + desc: ''' + Runtime read lock for the VENDOR_TEST partition. + ''', + swaccess: "rw0c", + hwaccess: "hro", + regwen: "DIRECT_ACCESS_REGWEN", + tags: [ // The value of this register can affect the read access of the this + // partition's memory window. Excluding this register from writing can ensure + // memories have read and write access. + "excl:CsrNonInitTests:CsrExclWrite"], + fields: [ + { bits: "0", + desc: ''' + When cleared to 0, read access to the VENDOR_TEST partition is locked. + Write 0 to clear this bit. + ''' + resval: 1, + }, + ] + }, + { name: "NON_SECRET_FUSES_READ_LOCK", + desc: ''' + Runtime read lock for the NON_SECRET_FUSES partition. + ''', + swaccess: "rw0c", + hwaccess: "hro", + regwen: "DIRECT_ACCESS_REGWEN", + tags: [ // The value of this register can affect the read access of the this + // partition's memory window. Excluding this register from writing can ensure + // memories have read and write access. + "excl:CsrNonInitTests:CsrExclWrite"], + fields: [ + { bits: "0", + desc: ''' + When cleared to 0, read access to the NON_SECRET_FUSES partition is locked. + Write 0 to clear this bit. + ''' + resval: 1, + }, + ] + }, + + /////////////////////// + // Integrity Digests // + /////////////////////// + { multireg: { + name: "VENDOR_TEST_DIGEST", + desc: ''' + Integrity digest for the VENDOR_TEST partition. + The integrity digest is 0 by default. Software must write this + digest value via the direct access interface in order to lock the partition. + After a reset, write access to the VENDOR_TEST partition is locked and + the digest becomes visible in this CSR. + ''', + count: "NumDigestWords", + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + cname: "WORD", + resval: 0, + tags: [ // OTP internal HW will update status so can not auto-predict its value. + "excl:CsrAllTests:CsrExclCheck"], + fields: [ + { bits: "31:0" + } + ] + } + }, + { multireg: { + name: "NON_SECRET_FUSES_DIGEST", + desc: ''' + Integrity digest for the NON_SECRET_FUSES partition. + The integrity digest is 0 by default. Software must write this + digest value via the direct access interface in order to lock the partition. + After a reset, write access to the NON_SECRET_FUSES partition is locked and + the digest becomes visible in this CSR. + ''', + count: "NumDigestWords", + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + cname: "WORD", + resval: 0, + tags: [ // OTP internal HW will update status so can not auto-predict its value. + "excl:CsrAllTests:CsrExclCheck"], + fields: [ + { bits: "31:0" + } + ] + } + }, + { multireg: { + name: "SECRET0_DIGEST", + desc: ''' + Integrity digest for the SECRET0 partition. + The integrity digest is 0 by default. The digest calculation can be triggered via the !!DIRECT_ACCESS_CMD. + After a reset, the digest then becomes visible in this CSR, and the corresponding partition becomes write-locked. + ''', + count: "NumDigestWords", + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + cname: "WORD", + resval: 0, + tags: [ // OTP internal HW will update status so can not auto-predict its value. + "excl:CsrAllTests:CsrExclCheck"], + fields: [ + { bits: "31:0" + } + ] + } + }, + { multireg: { + name: "SECRET1_DIGEST", + desc: ''' + Integrity digest for the SECRET1 partition. + The integrity digest is 0 by default. The digest calculation can be triggered via the !!DIRECT_ACCESS_CMD. + After a reset, the digest then becomes visible in this CSR, and the corresponding partition becomes write-locked. + ''', + count: "NumDigestWords", + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + cname: "WORD", + resval: 0, + tags: [ // OTP internal HW will update status so can not auto-predict its value. + "excl:CsrAllTests:CsrExclCheck"], + fields: [ + { bits: "31:0" + } + ] + } + }, + { multireg: { + name: "SECRET2_DIGEST", + desc: ''' + Integrity digest for the SECRET2 partition. + The integrity digest is 0 by default. The digest calculation can be triggered via the !!DIRECT_ACCESS_CMD. + After a reset, the digest then becomes visible in this CSR, and the corresponding partition becomes write-locked. + ''', + count: "NumDigestWords", + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + cname: "WORD", + resval: 0, + tags: [ // OTP internal HW will update status so can not auto-predict its value. + "excl:CsrAllTests:CsrExclCheck"], + fields: [ + { bits: "31:0" + } + ] + } + }, + { multireg: { + name: "SECRET3_DIGEST", + desc: ''' + Integrity digest for the SECRET3 partition. + The integrity digest is 0 by default. The digest calculation can be triggered via the !!DIRECT_ACCESS_CMD. + After a reset, the digest then becomes visible in this CSR, and the corresponding partition becomes write-locked. + ''', + count: "NumDigestWords", + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + cname: "WORD", + resval: 0, + tags: [ // OTP internal HW will update status so can not auto-predict its value. + "excl:CsrAllTests:CsrExclCheck"], + fields: [ + { bits: "31:0" + } + ] + } + }, + + //////////////////////////////// + // Software Config Partitions // + //////////////////////////////// + { skipto: "0x1000" } + + { window: { + name: "SW_CFG_WINDOW" + items: "NumSwCfgWindowWords" + swaccess: "ro", + desc: ''' + Any read to this window directly maps to the corresponding offset in the creator and owner software + config partitions, and triggers an OTP readout of the bytes requested. Note that the transaction + will block until OTP readout has completed. + ''' + } + } + ], + + // OTP wrapper-specific registers + prim: [ + { name: "CSR0", + desc: "" + swaccess: "rw", + hwaccess: "hro", + hwext: "false", + hwqe: "false", + fields: [ + { bits: "0", + name: "field0", + desc: "", + resval: "0x0", + } + { bits: "1", + name: "field1", + desc: "", + resval: "0x0", + } + { bits: "2", + name: "field2", + desc: "", + resval: "0x0", + } + { bits: "13:4", + name: "field3", + desc: "" + resval: "0x0", + } + { bits: "26:16", + name: "field4", + desc: "" + resval: "0x0", + } + ] + }, + { name: "CSR1", + desc: "" + swaccess: "rw", + hwaccess: "hro", + hwext: "false", + hwqe: "false", + fields: [ + { bits: "6:0", + name: "field0", + desc: "" + resval: "0x0", + } + { bits: "7:7", + name: "field1", + desc: "", + resval: "0x0", + } + { bits: "14:8", + name: "field2", + desc: "" + resval: "0x0", + } + { bits: "15:15", + name: "field3", + desc: "", + resval: "0x0", + } + { bits: "31:16", + name: "field4", + desc: "", + resval: "0x0", + } + ] + }, + { name: "CSR2", + desc: "" + swaccess: "rw", + hwaccess: "hro", + hwext: "false", + hwqe: "false", + fields: [ + { bits: "0", + name: "field0", + desc: "", + resval: "0x0", + } + ] + }, + { name: "CSR3", + desc: "" + swaccess: "rw", + hwaccess: "hrw", + hwext: "false", + hwqe: "false", + fields: [ + { bits: "2:0", + name: "field0", + desc: "" + swaccess: "rw1c", + resval: "0x0", + } + { bits: "13:4", + name: "field1", + desc: "", + swaccess: "rw1c", + resval: "0x0", + } + { bits: "16", + name: "field2", + desc: "", + swaccess: "rw1c", + resval: "0x0", + } + { bits: "17", + name: "field3", + desc: "", + swaccess: "ro", + resval: "0x0", + } + { bits: "18", + name: "field4", + desc: "", + swaccess: "ro", + resval: "0x0", + } + { bits: "19", + name: "field5", + desc: "", + swaccess: "ro", + resval: "0x0", + } + { bits: "20", + name: "field6", + desc: "", + swaccess: "ro", + resval: "0x0", + } + { bits: "21", + name: "field7", + desc: "", + swaccess: "ro", + resval: "0x0", + } + { bits: "22", + name: "field8", + desc: "", + swaccess: "ro", + resval: "0x0", + } + ] + }, + { name: "CSR4", + desc: "" + swaccess: "rw", + hwaccess: "hro", + hwext: "false", + hwqe: "false", + fields: [ + { bits: "9:0", + name: "field0", + desc: "" + resval: "0x0", + } + { bits: "12", + name: "field1", + desc: "" + resval: "0x0", + } + { bits: "13", + name: "field2", + desc: "" + resval: "0x0", + } + { bits: "14", + name: "field3", + desc: "" + resval: "0x0", + } + ] + }, + { name: "CSR5", + desc: "" + swaccess: "rw", + hwaccess: "hrw", + hwext: "false", + hwqe: "false", + fields: [ + { bits: "5:0", + name: "field0", + desc: "" + swaccess: "rw", + resval: "0x0", + } + { bits: "7:6", + name: "field1", + desc: "" + swaccess: "rw", + resval: "0x0", + } + { bits: "8", + name: "field2", + desc: "", + swaccess: "ro", + resval: "0x0", + } + { bits: "11:9", + name: "field3", + desc: "" + swaccess: "ro", + resval: "0x0", + } + { bits: "12", + name: "field4", + desc: "" + swaccess: "ro", + resval: "0x0", + } + { bits: "13", + name: "field5", + desc: "" + swaccess: "ro", + resval: "0x0", + } + { bits: "31:16", + name: "field6", + desc: "" + swaccess: "rw", + resval: "0x0", + } + ] + }, + { name: "CSR6", + desc: "" + swaccess: "rw", + hwaccess: "hro", + hwext: "false", + hwqe: "false", + fields: [ + { bits: "9:0", + name: "field0", + desc: "" + resval: "0x0", + } + { bits: "11", + name: "field1", + desc: "", + swaccess: "rw", + resval: "0x0", + } + { bits: "12", + name: "field2", + desc: "", + swaccess: "rw", + resval: "0x0", + } + { bits: "31:16", + name: "field3", + desc: "" + resval: "0x0", + } + ] + }, + { name: "CSR7", + desc: "", + swaccess: "ro", + hwaccess: "hrw", + hwext: "false", + hwqe: "false", + fields: [ + { bits: "5:0", + name: "field0", + desc: "" + swaccess: "ro", + resval: "0x0", + } + { bits: "10:8", + name: "field1", + desc: "", + swaccess: "ro", + resval: "0x0", + } + { bits: "14", + name: "field2", + desc: "", + swaccess: "ro", + resval: "0x0", + } + { bits: "15", + name: "field3", + desc: "", + swaccess: "ro", + resval: "0x0", + } + ] + }, + ] + } +} + + + + + + + + + diff --git a/src/fuse_ctrl/data/otp_ctrl.hjson.tpl b/src/fuse_ctrl/data/otp_ctrl.hjson.tpl new file mode 100755 index 0000000..89ccf45 --- /dev/null +++ b/src/fuse_ctrl/data/otp_ctrl.hjson.tpl @@ -0,0 +1,1522 @@ +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// HJSON with partition metadata. +// +${gen_comment} +<% +from topgen.lib import Name + +num_part = len(otp_mmap.config["partitions"]) +num_part_unbuf = 0 +for part in otp_mmap.config["partitions"]: + if part["variant"] == "Unbuffered": + num_part_unbuf += 1 +num_part_buf = num_part - num_part_unbuf +otp_size_as_bytes = 2 ** otp_mmap.config["otp"]["byte_addr_width"] +otp_size_as_uint32 = otp_size_as_bytes // 4 +%>\ +{ + name: "caliptra_otp_ctrl", + human_name: " Caliptra One-Time Programmable Memory COntroller", + one_line_desc: "Interfaces integrated one0time programmable memory, supports scrambling, integrity and secure dai_wr_inprogress", + one_paragraph_desc: ''' + One-Time Programmable (OTP) Memory Controller provides an open source abstraction interface for software and other hardware components such as Life Cycle Controller and Key Manager to interact with an integrated, closed source, proprietary OTP memory. + On top of defensive features provided by the proprietary OTP memory to deter side-channel analysis (SCA), fault injection (FI) attacks, and visual and electrical probing, the open source OTP controller features high-level logical security protection such as integrity checks and scrambling, as well as software isolation for when OTP contents are readable and programmable. + It features multiple individually-lockable logical partitions, periodic / persistent checking of OTP values, and a separate partition and interface for Life Cycle Controller. + ''' + // Uique comportablre IP identifier defined under KNOWN_CIP_IDS in the regtool + // TODO: This section needs to be updated for Caliptra (copying OT settings for now, to mark as placeholders) + cip_id: "16", + design_spec: "../doc", + dv_doc: "../doc/dv", + hw_checklist: "../doc/checklist", + sw_checklist: "/sw/device/lib/dif/dif_otp_ctrl", + revisions: [ + { + version: "0.1.0", + life_stage: "L1", + design_stage: "D2", + verification_stage: "V2", + dif_stage: "S1", + commit_id: "127b109e2fab9336e830158abe449a3922544ded", + notes: "", + } + { + version: "1.0.0", + life_stage: "L1", + design_stage: "D3", + verification_stage: "V2S", + dif_stage: "S2", + notes: "", + } + { + version: "2.0.0", + life_stage: "L1", + design_stage: "D2S", + verification_stage: "V2S", + dif_stage: "S2", + notes: "", + } + ] + clocking: [ + {clock: "clk_i", reset: "rst_ni", primary: true}, + {clock: "clk_edn_i", reset: "rst_edn_ni"} + ] + scan: "true", // Enable `scanmode_i` port + scan_reset: "true", // Enable `scan_rst_ni` port + scan_en: "true", // Enable `scan_en_i` port + bus_interfaces: [ + { protocol: "tlul", direction: "device", name: "core" } + { protocol: "tlul", direction: "device", name: "prim", hier_path: "u_otp.gen_generic.u_impl_generic.u_reg_top" } + ], + + available_output_list: [ + { name: "test", + width: 8, + desc: "Test-related GPIOs. Only active in DFT-enabled life cycle states." + } + ], + + /////////////////////////// + // Interrupts and Alerts // + /////////////////////////// + + interrupt_list: [ + { name: "otp_operation_done", + desc: "A direct access command or digest calculation operation has completed." + } + { name: "otp_error", + desc: "An error has occurred in the OTP controller. Check the !!ERR_CODE register to get more information." + } + ], + + alert_list: [ + { name: "fatal_macro_error", + desc: "This alert triggers if hardware detects an uncorrectable error during an OTP transaction, for example an uncorrectable ECC error in the OTP array.", + } + { name: "fatal_check_error", + desc: "This alert triggers if any of the background checks fails. This includes the digest checks and concurrent ECC checks in the buffer registers.", + } + { name: "fatal_bus_integ_error", + desc: "This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected." + } + { name: "fatal_prim_otp_alert", + desc: "Fatal alert triggered inside the OTP primitive, including fatal TL-UL bus integrity faults of the test interface." + } + { name: "recov_prim_otp_alert", + desc: "Recoverable alert triggered inside the OTP primitive." + } + ], + + //////////////// + // Parameters // + //////////////// + param_list: [ + // Init file + { name: "MemInitFile", + desc: "VMEM file to initialize the OTP macro.", + type: "", + default: '""', + expose: "true", + local: "false" + } + // Random netlist constants + { name: "RndCnstLfsrSeed", + desc: "Compile-time random bits for initial LFSR seed", + type: "otp_ctrl_pkg::lfsr_seed_t" + randcount: "40", + randtype: "data", // randomize randcount databits + } + { name: "RndCnstLfsrPerm", + desc: "Compile-time random permutation for LFSR output", + type: "otp_ctrl_pkg::lfsr_perm_t" + randcount: "40", + randtype: "perm", // random permutation for randcount elements + } + { name: "RndCnstScrmblKeyInit", + desc: "Compile-time random permutation for scrambling key/nonce register reset value", + type: "otp_ctrl_pkg::scrmbl_key_init_t" + randcount: "256", + randtype: "data", // random permutation for randcount elements + } + // Normal parameters + { name: "NumSramKeyReqSlots", + desc: "Number of key slots", + type: "int", + default: "4", + local: "true" + }, + { name: "OtpByteAddrWidth", + desc: "Width of the OTP byte address.", + type: "int", + default: "${otp_mmap.config["otp"]["byte_addr_width"]}", + local: "true" + }, + { name: "NumErrorEntries", + desc: "Number of error register entries.", + type: "int", + default: "${num_part + 2}", // partitions + DAI/LCI + local: "true" + }, + { name: "NumDaiWords", + desc: "Number of 32bit words in the DAI.", + type: "int", + default: "2", + local: "true" + }, + { name: "NumDigestWords", + desc: "Size of the digest fields in 32bit words.", + type: "int", + default: "2", + local: "true" + }, + { name: "NumSwCfgWindowWords", + desc: "Size of the TL-UL window in 32bit words. Note that the effective partition size is smaller than that.", + type: "int", + default: "${otp_size_as_uint32}", + local: "true" + } + + // Memory map Info + { name: "NumPart", + desc: "Number of partitions", + type: "int", + default: "${num_part}", + local: "true" + }, + { name: "NumPartUnbuf", + desc: "Number of unbuffered partitions", + type: "int", + default: "${num_part_unbuf}", + local: "true" + }, + { name: "NumPartBuf", + desc: "Number of buffered partitions (including 1 lifecycle partition)", + type: "int", + default: "${num_part_buf}", + local: "true" + }, + % for part in otp_mmap.config["partitions"]: + <% + part_name = Name.from_snake_case(part["name"]) + part_name_camel = part_name.as_camel_case() + %>\ + { name: "${part_name_camel}Offset", + desc: "Offset of the ${part["name"]} partition", + type: "int", + default: "${part["offset"]}", + local: "true" + }, + { name: "${part_name_camel}Size", + desc: "Size of the ${part["name"]} partition", + type: "int", + default: "${part["size"]}", + local: "true" + }, + % for item in part["items"]: + <% + item_name = Name.from_snake_case(item["name"]) + item_name_camel = item_name.as_camel_case() + %>\ + { name: "${item_name_camel}Offset", + desc: "Offset of ${item["name"]}", + type: "int", + default: "${item["offset"]}", + local: "true" + }, + { name: "${item_name_camel}Size", + desc: "Size of ${item["name"]}", + type: "int", + default: "${item["size"]}", + local: "true" + }, + % endfor + % endfor + ] + + ///////////////////////////// + // Intermodule Connections // + ///////////////////////////// + + inter_signal_list: [ + // OTP dedicated power connection from AST + { struct: "" + type: "io" + name: "otp_ext_voltage_h" + act: "none" + default: "'0" + package: "", + } + // Power sequencing signals to AST + { struct: "otp_ast_req" + type: "uni" + name: "otp_ast_pwr_seq" + act: "req" + default: "'0" + package: "otp_ctrl_pkg" + desc: "Power sequencing signals to AST (VDD domain)." + } + // Power sequencing signals from AST + { struct: "otp_ast_rsp" + type: "uni" + name: "otp_ast_pwr_seq_h" + act: "rcv" + default: "'0" + package: "otp_ctrl_pkg" + desc: "Power sequencing signals coming from AST (VCC domain)." + } + // EDN interface + { struct: "edn" + type: "req_rsp" + name: "edn" + act: "req" + package: "edn_pkg" + desc: "Entropy request to the entropy distribution network for LFSR reseeding and ephemeral key derivation." + } + // Power manager init command + { struct: "pwr_otp" + type: "req_rsp" + name: "pwr_otp" + act: "rsp" + default: "'0" + package: "pwrmgr_pkg" + desc: "Initialization request/acknowledge from/to power manager." + } + // Macro-specific test signals to/from LC TAP + { struct: "lc_otp_vendor_test" + type: "req_rsp" + name: "lc_otp_vendor_test" + act: "rsp" + default: "'0" + package: "otp_ctrl_pkg" + desc: "Vendor test control signals from/to the life cycle TAP." + } + // LC transition command + { struct: "lc_otp_program" + type: "req_rsp" + name: "lc_otp_program" + act: "rsp" + default: "'0" + package: "otp_ctrl_pkg" + desc: "Life cycle state transition interface." + } + // Broadcast to LC + { struct: "otp_lc_data" + type: "uni" + name: "otp_lc_data" + act: "req" + default: "'0" + package: "otp_ctrl_pkg" + desc: ''' + Life cycle state output holding the current life cycle state, + the value of the transition counter and the tokens needed for life cycle transitions. + ''' + } + // Broadcast from LC + { struct: "lc_tx" + type: "uni" + name: "lc_escalate_en" + act: "rcv" + default: "lc_ctrl_pkg::Off" + package: "lc_ctrl_pkg" + desc: ''' + Life cycle escalation enable coming from life cycle controller. + This signal moves all FSMs within OTP into the error state. + ''' + } + { struct: "lc_tx" + type: "uni" + name: "lc_creator_seed_sw_rw_en" + act: "rcv" + default: "lc_ctrl_pkg::Off" + package: "lc_ctrl_pkg" + desc: ''' + Provision enable qualifier coming from life cycle controller. + This signal enables SW read / write access to the RMA_TOKEN and CREATOR_ROOT_KEY_SHARE0 and CREATOR_ROOT_KEY_SHARE1. + ''' + } + { struct: "lc_tx" + type: "uni" + name: "lc_owner_seed_sw_rw_en" + act: "rcv" + default: "lc_ctrl_pkg::Off" + package: "lc_ctrl_pkg" + desc: ''' + Provision enable qualifier coming from life cycle controller. + This signal enables SW read / write access to the OWNER_SEED. + ''' + } + { struct: "lc_tx" + type: "uni" + name: "lc_seed_hw_rd_en" + act: "rcv" + default: "lc_ctrl_pkg::Off" + package: "lc_ctrl_pkg" + desc: ''' + Seed read enable coming from life cycle controller. + This signal enables HW read access to the CREATOR_ROOT_KEY_SHARE0 and CREATOR_ROOT_KEY_SHARE1. + ''' + } + { struct: "lc_tx" + type: "uni" + name: "lc_dft_en" + act: "rcv" + default: "lc_ctrl_pkg::Off" + package: "lc_ctrl_pkg" + desc: ''' + Test enable qualifier coming from life cycle controller. + This signals enables the TL-UL access port to the proprietary OTP IP. + ''' + } + { struct: "lc_tx" + type: "uni" + name: "lc_check_byp_en" + act: "rcv" + default: "lc_ctrl_pkg::Off" + package: "lc_ctrl_pkg" + desc: ''' + Life cycle partition check bypass signal. + This signal causes the life cycle partition to bypass consistency checks during life cycle state transitions in order to prevent spurious consistency check failures. + ''' + } + // Broadcast to Key Manager + { struct: "otp_keymgr_key" + type: "uni" + name: "otp_keymgr_key" + act: "req" + default: "'0" + package: "otp_ctrl_pkg" + desc: "Key output to the key manager holding CREATOR_ROOT_KEY_SHARE0 and CREATOR_ROOT_KEY_SHARE1." + } + // Broadcast to Flash Controller + { struct: "flash_otp_key" + type: "req_rsp" + name: "flash_otp_key" + act: "rsp" + default: "'0" + package: "otp_ctrl_pkg" + desc: "Key derivation interface for FLASH scrambling." + } + // Key request from SRAM scramblers + { struct: "sram_otp_key" + // TODO: would be nice if this could accept parameters. + // Split this out into an issue. + width: "4" + type: "req_rsp" + name: "sram_otp_key" + act: "rsp" + default: "'0" + package: "otp_ctrl_pkg" + desc: "Array with key derivation interfaces for SRAM scrambling devices." + } + // Key request from OTBN RAM Scrambler + { struct: "otbn_otp_key" + type: "req_rsp" + name: "otbn_otp_key" + act: "rsp" + default: "'0" + package: "otp_ctrl_pkg" + desc: "Key derivation interface for OTBN scrambling devices." + } + // Hardware config partition + { struct: "otp_broadcast" + type: "uni" + name: "otp_broadcast" + act: "req" + default: "'0" + package: "otp_ctrl_part_pkg" + desc: "Output of the HW partitions with breakout data types." + } + // AST observability control + { struct: "ast_obs_ctrl", + type: "uni", + name: "obs_ctrl", + act: "rcv", + package: "ast_pkg" + desc: "AST observability control signals." + } + // prim otp observe bus + { struct: "logic", + type: "uni", + name: "otp_obs", + act: "req", + width: "8", + package: "" + desc: "AST observability bus." + } + ] // inter_signal_list + + ///////////////////// + // Countermeasures // + ///////////////////// + + countermeasures: [ + { name: "BUS.INTEGRITY", + desc: "End-to-end bus integrity scheme." + } + { name: "SECRET.MEM.SCRAMBLE", + desc: "Secret partitions are scrambled with a full-round PRESENT cipher." + } + { name: "PART.MEM.DIGEST", + desc: "Integrity of buffered partitions is ensured via a 64bit digest." + } + { name: "DAI.FSM.SPARSE", + desc: "The direct access interface FSM is sparsely encoded." + } + { name: "KDI.FSM.SPARSE", + desc: "The key derivation interface FSM is sparsely encoded." + } + { name: "LCI.FSM.SPARSE", + desc: "The life cycle interface FSM is sparsely encoded." + } + { name: "PART.FSM.SPARSE", + desc: "The partition FSMs are sparsely encoded." + } + { name: "SCRMBL.FSM.SPARSE", + desc: "The scramble datapath FSM is sparsely encoded." + } + { name: "TIMER.FSM.SPARSE", + desc: "The background check timer FSM is sparsely encoded." + } + { name: "DAI.CTR.REDUN", + desc: "The direct access interface address counter employs a cross-counter implementation." + } + { name: "KDI_SEED.CTR.REDUN", + desc: "The key derivation interface counter employs a cross-counter implementation." + } + { name: "KDI_ENTROPY.CTR.REDUN", + desc: "The key derivation entropy counter employs a cross-counter implementation." + } + { name: "LCI.CTR.REDUN", + desc: "The life cycle interface address counter employs a cross-counter implementation." + } + { name: "PART.CTR.REDUN", + desc: "The address counter of buffered partitions employs a cross-counter implementation." + } + { name: "SCRMBL.CTR.REDUN", + desc: "The srambling datapath counter employs a cross-counter implementation." + } + { name: "TIMER_INTEG.CTR.REDUN", + desc: "The background integrity check timer employs a duplicated counter implementation." + } + { name: "TIMER_CNSTY.CTR.REDUN", + desc: "The background consistency check timer employs a duplicated counter implementation." + } + { name: "TIMER.LFSR.REDUN", + desc: "The background check LFSR is duplicated." + } + { name: "DAI.FSM.LOCAL_ESC", + desc: "The direct access interface FSM is moved into an invalid state upon local escalation." + } + { name: "LCI.FSM.LOCAL_ESC", + desc: "The life cycle interface FSM is moved into an invalid state upon local escalation." + } + { name: "KDI.FSM.LOCAL_ESC", + desc: "The key derivation interface FSM is moved into an invalid state upon local escalation." + } + { name: "PART.FSM.LOCAL_ESC", + desc: "The partition FSMs are moved into an invalid state upon local escalation." + } + { name: "SCRMBL.FSM.LOCAL_ESC", + desc: "The scramble datapath FSM is moved into an invalid state upon local escalation." + } + { name: "TIMER.FSM.LOCAL_ESC", + desc: "The background check timer FSM is moved into an invalid state upon local escalation." + } + { name: "DAI.FSM.GLOBAL_ESC", + desc: "The direct access interface FSM is moved into an invalid state upon global escalation via life cycle." + } + { name: "LCI.FSM.GLOBAL_ESC", + desc: "The life cycle interface FSM is moved into an invalid state upon global escalation via life cycle." + } + { name: "KDI.FSM.GLOBAL_ESC", + desc: "The key derivation interface FSM is moved into an invalid state upon global escalation via life cycle." + } + { name: "PART.FSM.GLOBAL_ESC", + desc: "The partition FSMs are moved into an invalid state upon global escalation via life cycle." + } + { name: "SCRMBL.FSM.GLOBAL_ESC", + desc: "The scramble datapath FSM is moved into an invalid state upon global escalation via life cycle." + } + { name: "TIMER.FSM.GLOBAL_ESC", + desc: "The background check timer FSM is moved into an invalid state upon global escalation via life cycle." + } + { name: "PART.DATA_REG.INTEGRITY", + desc: "All partition buffer registers are protected with ECC on 64bit blocks." + } + { name: "PART.DATA_REG.BKGN_CHK", + desc: "The digest of buffered partitions is recomputed and checked at pseudorandom intervals in the background." + } + { name: "PART.MEM.REGREN" + desc: "Unbuffered ('software') partitions can be read-locked via a CSR until the next system reset." + } + { name: "PART.MEM.SW_UNREADABLE" + desc: "Secret buffered partitions become unreadable to software once they are locked via the digest." + } + { name: "PART.MEM.SW_UNWRITABLE" + desc: "All partitions become unwritable by software once they are locked via the digest." + } + { name: "LC_PART.MEM.SW_NOACCESS" + desc: "The life cycle partition is not directly readable nor writable via software." + } + { name: "ACCESS.CTRL.MUBI", + desc: "The access control signals going from the partitions to the DAI are MUBI encoded." + } + { name: "TOKEN_VALID.CTRL.MUBI", + desc: "The token valid signals going to the life cycle controller are MUBI encoded." + } + { name: "LC_CTRL.INTERSIG.MUBI", + desc: "The life cycle control signals are multibit encoded." + } + { name: "TEST.BUS.LC_GATED", + desc: "Prevent access to test signals and the OTP backdoor interface in non-test lifecycle states." + } + { name: "TEST_TL_LC_GATE.FSM.SPARSE", + desc: "The control FSM inside the TL-UL gating primitive is sparsely encoded." + } + { name: "DIRECT_ACCESS.CONFIG.REGWEN", + desc: "The direct access CSRs are REGWEN protected." + } + { name: "CHECK_TRIGGER.CONFIG.REGWEN", + desc: "The check trigger CSR is REGWEN protected." + } + { name: "CHECK.CONFIG.REGWEN", + desc: "The check CSR is REGWEN protected." + } + { name: "MACRO.MEM.INTEGRITY", + desc: ''' + The OTP macro employs a vendor-specific integrity scheme at the granularity of the native 16bit OTP words. + The scheme is able to at least detect single bit errors. + ''' + } + { name: "MACRO.MEM.CM", + desc: "The OTP macro may contain additional vendor-specific countermeasures." + } + ] + + features: [ + { + name: "OTP_CTRL.PARTITION.VENDOR_TEST" + desc: '''Vendor test partition is used for OTP programming smoke check during manufacturing flow. + In this partition, ECC uncorrectable errors will not lead to fatal errors and alerts. + Instead the error will be reported as correctable ECC error. + ''' + } + { + name: "OTP_CTRL.PARTITION.CREATOR_SW_CFG" + desc: '''During calibration stage, various parameters (clock, voltage, and timing sources) are calibrated and recorded to CREATOR_SW_CFG partition. + ''' + } + { + name: "OTP_CTRL.INIT" + desc: '''When power is up, OTP controller reads devices status. + After all reads complete, the controller performs integrity check on the HW_CFG* and SECRET partitions. + Once all integrity checks are complete, the controller marks outputs as valid. + ''' + } + { + name: "OTP_CTRL.PROGRAM" + desc: '''All other partitions except life cycle partition are programmed through DAI interface. + And once non-zero digest is programmed to these partition, no further write access is allowed. + Life cycle partition is programmed by LC_CTRL. + ''' + } + { + name: "OTP_CTRL.PARTITION.SECRET0" + desc: "Obfuscated UDS Seed" + } + { + name: "OTP_CTRL.PARTITION.SECRET1" + desc: "Obfuscated Field Entropy" + } + { + name: "OTP_CTRL.PARTITION.LIFE_CYCLE" + desc: '''LC state, LC transition count. + This feature is owned by the LC_CTRL and cannot be tested well through the OTP_CTRL CSR interface. + ''' + } + { + name: "OTP_CTRL.PARTITIONS_FEATURE.READ_LOCK" + desc: '''Following partitions can be read lockable by CSR. + - VENDOR_TEST + - CREATOR_SW_CFG + Following partitions can be read lockable by writing digest. + - SECRET0 + - SECRET1 + All read attempt to these partitions after read is locked will trigger AccessError (recoverable). + ''' + } + { + name: "OTP_CTRL.PARTITIONS_FEATURE.WRITE_LOCK" + desc: "All partitions except LIFE_CYCLE can be write lockable by writing digest." + } + { + name: "OTP_CTRL.ERROR_HANDLING.RECOVERABLE" + desc: "Recoverable error is created when unauthorized access atempt are detected via dai interface." + } + { + name: "OTP_CTRL.ERROR_HANDLING.FATAL" + desc: "Unrecoverable errors are created for uncorrectable ecc error, otp macro malfunction and unauthorized access via lc_ctrl." + } + { + name: "OTP_CTRL.BACKGROUND_CHECK.CHECK_TIMEOUT" + desc: "Timeout value for the integrity and consistency checks." + } + { + name: "OTP_CTRL.BACKGROUND_CHECK.INTEGRITY_CHECK_PERIOD" + desc: "The interval which the digest of the partition is recomputed to check integrity of locked partition." + } + { + name: "OTP_CTRL.BACKGROUND_CHECK.CONSISTENCY_CHECK_PERIOD" + desc: "Re-read period of the buffer registers to ensure data is matched with the associated OTP partition." + } + ] + + /////////////// + // Registers // + /////////////// + + regwidth: "32", + registers: { + core: [ + //////////////////////// + // Ctrl / Status CSRs // + //////////////////////// + + { name: "STATUS", + desc: "OTP status register.", + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + resval: 0, + tags: [ // OTP internal HW can modify status register + "excl:CsrAllTests:CsrExclCheck"], + fields: [ + % for k, part in enumerate(otp_mmap.config["partitions"]): + { bits: "${k}" + name: "${part["name"]}_ERROR" + desc: ''' + Set to 1 if an error occurred in this partition. + If set to 1, SW should check the !!ERR_CODE register at the corresponding index. + ''' + } + % endfor + { bits: "${num_part}" + name: "DAI_ERROR" + desc: ''' + Set to 1 if an error occurred in the DAI. + If set to 1, SW should check the !!ERR_CODE register at the corresponding index. + ''' + } + { bits: "${num_part+1}" + name: "LCI_ERROR" + desc: ''' + Set to 1 if an error occurred in the LCI. + If set to 1, SW should check the !!ERR_CODE register at the corresponding index. + ''' + } + { bits: "${num_part+2}" + name: "TIMEOUT_ERROR" + desc: ''' + Set to 1 if an integrity or consistency check times out. + This raises an fatal_check_error alert and is an unrecoverable error condition. + ''' + } + { bits: "${num_part+3}" + name: "LFSR_FSM_ERROR" + desc: ''' + Set to 1 if the LFSR timer FSM has reached an invalid state. + This raises an fatal_check_error alert and is an unrecoverable error condition. + ''' + } + { bits: "${num_part+4}" + name: "SCRAMBLING_FSM_ERROR" + desc: ''' + Set to 1 if the scrambling datapath FSM has reached an invalid state. + This raises an fatal_check_error alert and is an unrecoverable error condition. + ''' + } + { bits: "${num_part+5}" + name: "KEY_DERIV_FSM_ERROR" + desc: ''' + Set to 1 if the key derivation FSM has reached an invalid state. + This raises an fatal_check_error alert and is an unrecoverable error condition. + ''' + } + { bits: "${num_part+6}" + name: "BUS_INTEG_ERROR" + desc: ''' + This bit is set to 1 if a fatal bus integrity fault is detected. + This error triggers a fatal_bus_integ_error alert. + ''' + } + { bits: "${num_part+7}" + name: "DAI_IDLE" + desc: "Set to 1 if the DAI is idle and ready to accept commands." + } + { bits: "${num_part+8}" + name: "CHECK_PENDING" + desc: "Set to 1 if an integrity or consistency check triggered by the LFSR timer or via !!CHECK_TRIGGER is pending." + } + ] + } + { multireg: { + name: "ERR_CODE", + desc: ''' + This register holds information about error conditions that occurred in the agents + interacting with the OTP macro via the internal bus. The error codes should be checked + if the partitions, DAI or LCI flag an error in the !!STATUS register, or when an + !!INTR_STATE.otp_error has been triggered. Note that all errors trigger an otp_error + interrupt, and in addition some errors may trigger either an fatal_macro_error or an + fatal_check_error alert. + ''', + count: "NumErrorEntries", + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + cname: "AGENT", + compact: "false", + resval: 0, + tags: [ // OTP internal HW can modify the error code registers + "excl:CsrAllTests:CsrExclCheck"], + fields: [ + { + bits: "2:0" + enum: [ + { value: "0", + name: "NO_ERROR", + desc: ''' + No error condition has occurred. + ''' + }, + { value: "1", + name: "MACRO_ERROR", + desc: ''' + Returned if the OTP macro command was invalid or did not complete successfully + due to a macro malfunction. + This error should never occur during normal operation and is not recoverable. + This error triggers an fatal_macro_error alert. + ''' + }, + { value: "2", + name: "MACRO_ECC_CORR_ERROR", + desc: ''' + A correctable ECC error has occured during an OTP read operation. + The corresponding controller automatically recovers from this error when + issuing a new command. + ''' + }, + { value: "3", + name: "MACRO_ECC_UNCORR_ERROR", + desc: ''' + An uncorrectable ECC error has occurred during an OTP read operation. + This error should never occur during normal operation and is not recoverable. + If this error is present this may be a sign that the device is malfunctioning. + This error triggers an fatal_macro_error alert. + ''' + }, + { value: "4", + name: "MACRO_WRITE_BLANK_ERROR", + desc: ''' + This error is returned if a programming operation attempted to clear a bit that has previously been programmed to 1. + The corresponding controller automatically recovers from this error when issuing a new command. + + Note however that the affected OTP word may be left in an inconsistent state if this error occurs. + This can cause several issues when the word is accessed again (either as part of a regular read operation, as part of the readout at boot, or as part of a background check). + + It is important that SW ensures that each word is only written once, since this can render the device useless. + ''' + }, + { value: "5", + name: "ACCESS_ERROR", + desc: ''' + This error indicates that a locked memory region has been accessed. + The corresponding controller automatically recovers from this error when issuing a new command. + ''' + }, + { value: "6", + name: "CHECK_FAIL_ERROR", + desc: ''' + An ECC, integrity or consistency mismatch has been detected in the buffer registers. + This error should never occur during normal operation and is not recoverable. + This error triggers an fatal_check_error alert. + ''' + }, + { value: "7", + name: "FSM_STATE_ERROR", + desc: ''' + The FSM of the corresponding controller has reached an invalid state, or the FSM has + been moved into a terminal error state due to an escalation action via lc_escalate_en_i. + This error should never occur during normal operation and is not recoverable. + If this error is present, this is a sign that the device has fallen victim to + an invasive attack. This error triggers an fatal_check_error alert. + ''' + }, + ] + } + ] + } + } + { name: "DIRECT_ACCESS_REGWEN", + desc: ''' + Register write enable for all direct access interface registers. + ''', + swaccess: "rw0c", + hwaccess: "hrw", + hwext: "true", + hwqe: "true", + tags: [ // OTP internal HW will set this enable register to 0 when OTP is not under IDLE + // state, so could not auto-predict its value + "excl:CsrNonInitTests:CsrExclCheck"], + fields: [ + { + bits: "0", + desc: ''' + This bit controls whether the DAI registers can be written. + Write 0 to it in order to clear the bit. + + Note that the hardware also modulates this bit and sets it to 0 temporarily + during an OTP operation such that the corresponding address and data registers + cannot be modified while an operation is pending. The !!DAI_IDLE status bit + will also be set to 0 in such a case. + ''' + resval: 1, + }, + ] + }, + { name: "DIRECT_ACCESS_CMD", + desc: "Command register for direct accesses.", + swaccess: "r0w1c", + hwaccess: "hro", + hwqe: "true", + hwext: "true", + resval: 0, + regwen: "DIRECT_ACCESS_REGWEN", + tags: [ // Write to DIRECT_ACCESS_CMD randomly might cause OTP_ERRORs and illegal sequences + "excl:CsrNonInitTests:CsrExclWrite"], + fields: [ + { bits: "0", + name: "RD", + desc: ''' + Initiates a readout sequence that reads the location specified + by !!DIRECT_ACCESS_ADDRESS. The command places the data read into + !!DIRECT_ACCESS_RDATA_0 and !!DIRECT_ACCESS_RDATA_1 (for 64bit partitions). + ''' + } + { bits: "1", + name: "WR", + desc: ''' + Initiates a programming sequence that writes the data in !!DIRECT_ACCESS_WDATA_0 + and !!DIRECT_ACCESS_WDATA_1 (for 64bit partitions) to the location specified by + !!DIRECT_ACCESS_ADDRESS. + ''' + } + { bits: "2", + name: "DIGEST", + desc: ''' + Initiates the digest calculation and locking sequence for the partition specified by + !!DIRECT_ACCESS_ADDRESS. + ''' + } + ] + } + { name: "DIRECT_ACCESS_ADDRESS", + desc: "Address register for direct accesses.", + swaccess: "rw", + hwaccess: "hro", + hwqe: "false", + resval: 0, + regwen: "DIRECT_ACCESS_REGWEN", + tags: [ // The enable register "DIRECT_ACCESS_REGWEN" is HW controlled, + // so not able to predict this register value automatically + "excl:CsrNonInitTests:CsrExclCheck"], + fields: [ + { bits: "OtpByteAddrWidth-1:0", + desc: ''' + This is the address for the OTP word to be read or written through + the direct access interface. Note that the address is aligned to the access size + internally, hence bits 1:0 are ignored for 32bit accesses, and bits 2:0 are ignored + for 64bit accesses. + + For the digest calculation command, set this register to the partition base offset. + ''' + } + ] + } + { multireg: { + name: "DIRECT_ACCESS_WDATA", + desc: '''Write data for direct accesses. + Hardware automatically determines the access granule (32bit or 64bit) based on which + partition is being written to. + ''', + count: "NumDaiWords", // 2 x 32bit = 64bit + swaccess: "rw", + hwaccess: "hro", + hwqe: "false", + regwen: "DIRECT_ACCESS_REGWEN", + cname: "WORD", + resval: 0, + tags: [ // The value of this register is written from "DIRECT_ACCESS_RDATA", + // so could not predict this register value automatically + "excl:CsrAllTests:CsrExclCheck"], + fields: [ + { bits: "31:0" + } + ] + } + }, + { multireg: { + name: "DIRECT_ACCESS_RDATA", + desc: '''Read data for direct accesses. + Hardware automatically determines the access granule (32bit or 64bit) based on which + partition is read from. + ''', + count: "NumDaiWords", // 2 x 32bit = 64bit + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + cname: "WORD", + resval: 0, + fields: [ + { bits: "31:0" + } + ] + } + }, + + ////////////////////////////////////// + // Integrity and Consistency Checks // + ////////////////////////////////////// + { name: "CHECK_TRIGGER_REGWEN", + desc: ''' + Register write enable for !!CHECK_TRIGGER. + ''', + swaccess: "rw0c", + hwaccess: "none", + fields: [ + { bits: "0", + desc: ''' + When cleared to 0, the !!CHECK_TRIGGER register cannot be written anymore. + Write 0 to clear this bit. + ''' + resval: 1, + }, + ] + }, + { name: "CHECK_TRIGGER", + desc: "Command register for direct accesses.", + swaccess: "r0w1c", + hwaccess: "hro", + hwqe: "true", + hwext: "true", + resval: 0, + regwen: "CHECK_TRIGGER_REGWEN", + fields: [ + { bits: "0", + name: "INTEGRITY", + desc: ''' + Writing 1 to this bit triggers an integrity check. SW should monitor !!STATUS.CHECK_PENDING + and wait until the check has been completed. If there are any errors, those will be flagged + in the !!STATUS and !!ERR_CODE registers, and via the interrupts and alerts. + ''' + } + { bits: "1", + name: "CONSISTENCY", + desc: ''' + Writing 1 to this bit triggers a consistency check. SW should monitor !!STATUS.CHECK_PENDING + and wait until the check has been completed. If there are any errors, those will be flagged + in the !!STATUS and !!ERR_CODE registers, and via interrupts and alerts. + ''' + } + ] + }, + { name: "CHECK_REGWEN", + desc: ''' + Register write enable for !!INTEGRITY_CHECK_PERIOD and !!CONSISTENCY_CHECK_PERIOD. + ''', + swaccess: "rw0c", + hwaccess: "none", + fields: [ + { bits: "0", + desc: ''' + When cleared to 0, !!INTEGRITY_CHECK_PERIOD and !!CONSISTENCY_CHECK_PERIOD registers cannot be written anymore. + Write 0 to clear this bit. + ''' + resval: 1, + }, + ] + }, + { name: "CHECK_TIMEOUT", + desc: ''' + Timeout value for the integrity and consistency checks. + ''', + swaccess: "rw", + hwaccess: "hro", + regwen: "CHECK_REGWEN", + tags: [ // Do not write to this automatically, as it may trigger fatal alert, and cause + // escalation. + "excl:CsrAllTests:CsrExclWrite"], + fields: [ + { bits: "31:0", + desc: ''' + Timeout value in cycles for the for the integrity and consistency checks. If an integrity or consistency + check does not complete within the timeout window, an error will be flagged in the !!STATUS register, + an otp_error interrupt will be raised, and an fatal_check_error alert will be sent out. The timeout should + be set to a large value to stay on the safe side. The maximum check time can be upper bounded by the + number of cycles it takes to readout, scramble and digest the entire OTP array. Since this amounts to + roughly 25k cycles, it is recommended to set this value to at least 100'000 cycles in order to stay on the + safe side. A value of zero disables the timeout mechanism (default). + ''' + resval: 0, + }, + ] + }, + { name: "INTEGRITY_CHECK_PERIOD", + desc: ''' + This value specifies the maximum period that can be generated pseudo-randomly. + Only applies to the HW_CFG* and SECRET* partitions once they are locked. + ''' + swaccess: "rw", + hwaccess: "hro", + regwen: "CHECK_REGWEN", + fields: [ + { bits: "31:0", + desc: ''' + The pseudo-random period is generated using a 40bit LFSR internally, and this register defines + the bit mask to be applied to the LFSR output in order to limit its range. The value of this + register is left shifted by 8bits and the lower bits are set to 8'hFF in order to form the 40bit mask. + A recommended value is 0x3_FFFF, corresponding to a maximum period of ~2.8s at 24MHz. + A value of zero disables the timer (default). Note that a one-off check can always be triggered via + !!CHECK_TRIGGER.INTEGRITY. + ''' + resval: "0" + } + ] + } + { name: "CONSISTENCY_CHECK_PERIOD", + desc: ''' + This value specifies the maximum period that can be generated pseudo-randomly. + This applies to the LIFE_CYCLE partition and the HW_CFG* and SECRET* partitions once they are locked. + ''' + swaccess: "rw", + hwaccess: "hro", + regwen: "CHECK_REGWEN", + fields: [ + { bits: "31:0", + desc: ''' + The pseudo-random period is generated using a 40bit LFSR internally, and this register defines + the bit mask to be applied to the LFSR output in order to limit its range. The value of this + register is left shifted by 8bits and the lower bits are set to 8'hFF in order to form the 40bit mask. + A recommended value is 0x3FF_FFFF, corresponding to a maximum period of ~716s at 24MHz. + A value of zero disables the timer (default). Note that a one-off check can always be triggered via + !!CHECK_TRIGGER.CONSISTENCY. + ''' + resval: "0" + } + ] + } + + //////////////////////////////////// + // Dynamic Locks of SW Parititons // + //////////////////////////////////// + % for part in otp_mmap.config["partitions"]: + % if part["read_lock"].lower() == "csr": + { name: "${part["name"]}_READ_LOCK", + desc: ''' + Runtime read lock for the ${part["name"]} partition. + ''', + swaccess: "rw0c", + hwaccess: "hro", + regwen: "DIRECT_ACCESS_REGWEN", + tags: [ // The value of this register can affect the read access of the this + // partition's memory window. Excluding this register from writing can ensure + // memories have read and write access. + "excl:CsrNonInitTests:CsrExclWrite"], + fields: [ + { bits: "0", + desc: ''' + When cleared to 0, read access to the ${part["name"]} partition is locked. + Write 0 to clear this bit. + ''' + resval: 1, + }, + ] + }, + % endif + % endfor + + /////////////////////// + // Integrity Digests // + /////////////////////// + % for part in otp_mmap.config["partitions"]: + % if part["sw_digest"]: + { multireg: { + name: "${part["name"]}_DIGEST", + desc: ''' + Integrity digest for the ${part["name"]} partition. + The integrity digest is 0 by default. Software must write this + digest value via the direct access interface in order to lock the partition. + After a reset, write access to the ${part["name"]} partition is locked and + the digest becomes visible in this CSR. + ''', + count: "NumDigestWords", + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + cname: "WORD", + resval: 0, + tags: [ // OTP internal HW will update status so can not auto-predict its value. + "excl:CsrAllTests:CsrExclCheck"], + fields: [ + { bits: "31:0" + } + ] + } + }, + % elif part["hw_digest"]: + { multireg: { + name: "${part["name"]}_DIGEST", + desc: ''' + Integrity digest for the ${part["name"]} partition. + The integrity digest is 0 by default. The digest calculation can be triggered via the !!DIRECT_ACCESS_CMD. + After a reset, the digest then becomes visible in this CSR, and the corresponding partition becomes write-locked. + ''', + count: "NumDigestWords", + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + cname: "WORD", + resval: 0, + tags: [ // OTP internal HW will update status so can not auto-predict its value. + "excl:CsrAllTests:CsrExclCheck"], + fields: [ + { bits: "31:0" + } + ] + } + }, + % endif + % endfor + + //////////////////////////////// + // Software Config Partitions // + //////////////////////////////// + { skipto: "${hex(otp_size_as_bytes)}" } + + { window: { + name: "SW_CFG_WINDOW" + items: "NumSwCfgWindowWords" + swaccess: "ro", + desc: ''' + Any read to this window directly maps to the corresponding offset in the creator and owner software + config partitions, and triggers an OTP readout of the bytes requested. Note that the transaction + will block until OTP readout has completed. + ''' + } + } + ], + + // OTP wrapper-specific registers + prim: [ + { name: "CSR0", + desc: "" + swaccess: "rw", + hwaccess: "hro", + hwext: "false", + hwqe: "false", + fields: [ + { bits: "0", + name: "field0", + desc: "", + resval: "0x0", + } + { bits: "1", + name: "field1", + desc: "", + resval: "0x0", + } + { bits: "2", + name: "field2", + desc: "", + resval: "0x0", + } + { bits: "13:4", + name: "field3", + desc: "" + resval: "0x0", + } + { bits: "26:16", + name: "field4", + desc: "" + resval: "0x0", + } + ] + }, + { name: "CSR1", + desc: "" + swaccess: "rw", + hwaccess: "hro", + hwext: "false", + hwqe: "false", + fields: [ + { bits: "6:0", + name: "field0", + desc: "" + resval: "0x0", + } + { bits: "7:7", + name: "field1", + desc: "", + resval: "0x0", + } + { bits: "14:8", + name: "field2", + desc: "" + resval: "0x0", + } + { bits: "15:15", + name: "field3", + desc: "", + resval: "0x0", + } + { bits: "31:16", + name: "field4", + desc: "", + resval: "0x0", + } + ] + }, + { name: "CSR2", + desc: "" + swaccess: "rw", + hwaccess: "hro", + hwext: "false", + hwqe: "false", + fields: [ + { bits: "0", + name: "field0", + desc: "", + resval: "0x0", + } + ] + }, + { name: "CSR3", + desc: "" + swaccess: "rw", + hwaccess: "hrw", + hwext: "false", + hwqe: "false", + fields: [ + { bits: "2:0", + name: "field0", + desc: "" + swaccess: "rw1c", + resval: "0x0", + } + { bits: "13:4", + name: "field1", + desc: "", + swaccess: "rw1c", + resval: "0x0", + } + { bits: "16", + name: "field2", + desc: "", + swaccess: "rw1c", + resval: "0x0", + } + { bits: "17", + name: "field3", + desc: "", + swaccess: "ro", + resval: "0x0", + } + { bits: "18", + name: "field4", + desc: "", + swaccess: "ro", + resval: "0x0", + } + { bits: "19", + name: "field5", + desc: "", + swaccess: "ro", + resval: "0x0", + } + { bits: "20", + name: "field6", + desc: "", + swaccess: "ro", + resval: "0x0", + } + { bits: "21", + name: "field7", + desc: "", + swaccess: "ro", + resval: "0x0", + } + { bits: "22", + name: "field8", + desc: "", + swaccess: "ro", + resval: "0x0", + } + ] + }, + { name: "CSR4", + desc: "" + swaccess: "rw", + hwaccess: "hro", + hwext: "false", + hwqe: "false", + fields: [ + { bits: "9:0", + name: "field0", + desc: "" + resval: "0x0", + } + { bits: "12", + name: "field1", + desc: "" + resval: "0x0", + } + { bits: "13", + name: "field2", + desc: "" + resval: "0x0", + } + { bits: "14", + name: "field3", + desc: "" + resval: "0x0", + } + ] + }, + { name: "CSR5", + desc: "" + swaccess: "rw", + hwaccess: "hrw", + hwext: "false", + hwqe: "false", + fields: [ + { bits: "5:0", + name: "field0", + desc: "" + swaccess: "rw", + resval: "0x0", + } + { bits: "7:6", + name: "field1", + desc: "" + swaccess: "rw", + resval: "0x0", + } + { bits: "8", + name: "field2", + desc: "", + swaccess: "ro", + resval: "0x0", + } + { bits: "11:9", + name: "field3", + desc: "" + swaccess: "ro", + resval: "0x0", + } + { bits: "12", + name: "field4", + desc: "" + swaccess: "ro", + resval: "0x0", + } + { bits: "13", + name: "field5", + desc: "" + swaccess: "ro", + resval: "0x0", + } + { bits: "31:16", + name: "field6", + desc: "" + swaccess: "rw", + resval: "0x0", + } + ] + }, + { name: "CSR6", + desc: "" + swaccess: "rw", + hwaccess: "hro", + hwext: "false", + hwqe: "false", + fields: [ + { bits: "9:0", + name: "field0", + desc: "" + resval: "0x0", + } + { bits: "11", + name: "field1", + desc: "", + swaccess: "rw", + resval: "0x0", + } + { bits: "12", + name: "field2", + desc: "", + swaccess: "rw", + resval: "0x0", + } + { bits: "31:16", + name: "field3", + desc: "" + resval: "0x0", + } + ] + }, + { name: "CSR7", + desc: "", + swaccess: "ro", + hwaccess: "hrw", + hwext: "false", + hwqe: "false", + fields: [ + { bits: "5:0", + name: "field0", + desc: "" + swaccess: "ro", + resval: "0x0", + } + { bits: "10:8", + name: "field1", + desc: "", + swaccess: "ro", + resval: "0x0", + } + { bits: "14", + name: "field2", + desc: "", + swaccess: "ro", + resval: "0x0", + } + { bits: "15", + name: "field3", + desc: "", + swaccess: "ro", + resval: "0x0", + } + ] + }, + ] + } +} + + + + + + + + + diff --git a/src/fuse_ctrl/data/otp_ctrl.json b/src/fuse_ctrl/data/otp_ctrl.json new file mode 100644 index 0000000..7c2c795 --- /dev/null +++ b/src/fuse_ctrl/data/otp_ctrl.json @@ -0,0 +1,1916 @@ +{ + "name": "caliptra_otp_ctrl", + "human_name": " Caliptra One-Time Programmable Memory COntroller", + "one_line_desc": "Interfaces integrated one0time programmable memory, supports scrambling, integrity and secure dai_wr_inprogress", + "one_paragraph_desc": "One-Time Programmable (OTP) Memory Controller provides an open source abstraction interface for software and other hardware components such as Life Cycle Controller and Key Manager to interact with an integrated, closed source, proprietary OTP memory.\nOn top of defensive features provided by the proprietary OTP memory to deter side-channel analysis (SCA), fault injection (FI) attacks, and visual and electrical probing, the open source OTP controller features high-level logical security protection such as integrity checks and scrambling, as well as software isolation for when OTP contents are readable and programmable.\nIt features multiple individually-lockable logical partitions, periodic / persistent checking of OTP values, and a separate partition and interface for Life Cycle Controller.", + "cip_id": "16", + "design_spec": "../doc", + "dv_doc": "../doc/dv", + "hw_checklist": "../doc/checklist", + "sw_checklist": "/sw/device/lib/dif/dif_otp_ctrl", + "revisions": [ + { + "version": "0.1.0", + "life_stage": "L1", + "design_stage": "D2", + "verification_stage": "V2", + "dif_stage": "S1", + "commit_id": "127b109e2fab9336e830158abe449a3922544ded", + "notes": "" + }, + { + "version": "1.0.0", + "life_stage": "L1", + "design_stage": "D3", + "verification_stage": "V2S", + "dif_stage": "S2", + "notes": "" + }, + { + "version": "2.0.0", + "life_stage": "L1", + "design_stage": "D2S", + "verification_stage": "V2S", + "dif_stage": "S2", + "notes": "" + } + ], + "clocking": [ + { + "clock": "clk_i", + "reset": "rst_ni", + "primary": true + }, + { + "clock": "clk_edn_i", + "reset": "rst_edn_ni" + } + ], + "scan": "true", + "scan_reset": "true", + "scan_en": "true", + "bus_interfaces": [ + { + "protocol": "tlul", + "direction": "device", + "name": "core" + }, + { + "protocol": "tlul", + "direction": "device", + "name": "prim", + "hier_path": "u_otp.gen_generic.u_impl_generic.u_reg_top" + } + ], + "available_output_list": [ + { + "name": "test", + "width": 8, + "desc": "Test-related GPIOs. Only active in DFT-enabled life cycle states." + } + ], + "interrupt_list": [ + { + "name": "otp_operation_done", + "desc": "A direct access command or digest calculation operation has completed." + }, + { + "name": "otp_error", + "desc": "An error has occurred in the OTP controller. Check the !!ERR_CODE register to get more information." + } + ], + "alert_list": [ + { + "name": "fatal_macro_error", + "desc": "This alert triggers if hardware detects an uncorrectable error during an OTP transaction, for example an uncorrectable ECC error in the OTP array." + }, + { + "name": "fatal_check_error", + "desc": "This alert triggers if any of the background checks fails. This includes the digest checks and concurrent ECC checks in the buffer registers." + }, + { + "name": "fatal_bus_integ_error", + "desc": "This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected." + }, + { + "name": "fatal_prim_otp_alert", + "desc": "Fatal alert triggered inside the OTP primitive, including fatal TL-UL bus integrity faults of the test interface." + }, + { + "name": "recov_prim_otp_alert", + "desc": "Recoverable alert triggered inside the OTP primitive." + } + ], + "param_list": [ + { + "name": "MemInitFile", + "desc": "VMEM file to initialize the OTP macro.", + "type": "", + "default": "\"\"", + "expose": "true", + "local": "false" + }, + { + "name": "RndCnstLfsrSeed", + "desc": "Compile-time random bits for initial LFSR seed", + "type": "otp_ctrl_pkg::lfsr_seed_t", + "randcount": "40", + "randtype": "data" + }, + { + "name": "RndCnstLfsrPerm", + "desc": "Compile-time random permutation for LFSR output", + "type": "otp_ctrl_pkg::lfsr_perm_t", + "randcount": "40", + "randtype": "perm" + }, + { + "name": "RndCnstScrmblKeyInit", + "desc": "Compile-time random permutation for scrambling key/nonce register reset value", + "type": "otp_ctrl_pkg::scrmbl_key_init_t", + "randcount": "256", + "randtype": "data" + }, + { + "name": "NumSramKeyReqSlots", + "desc": "Number of key slots", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "OtpByteAddrWidth", + "desc": "Width of the OTP byte address.", + "type": "int", + "default": "12", + "local": "true" + }, + { + "name": "NumErrorEntries", + "desc": "Number of error register entries.", + "type": "int", + "default": "9", + "local": "true" + }, + { + "name": "NumDaiWords", + "desc": "Number of 32bit words in the DAI.", + "type": "int", + "default": "2", + "local": "true" + }, + { + "name": "NumDigestWords", + "desc": "Size of the digest fields in 32bit words.", + "type": "int", + "default": "2", + "local": "true" + }, + { + "name": "NumSwCfgWindowWords", + "desc": "Size of the TL-UL window in 32bit words. Note that the effective partition size is smaller than that.", + "type": "int", + "default": "1024", + "local": "true" + }, + { + "name": "NumPart", + "desc": "Number of partitions", + "type": "int", + "default": "7", + "local": "true" + }, + { + "name": "NumPartUnbuf", + "desc": "Number of unbuffered partitions", + "type": "int", + "default": "2", + "local": "true" + }, + { + "name": "NumPartBuf", + "desc": "Number of buffered partitions (including 1 lifecycle partition)", + "type": "int", + "default": "5", + "local": "true" + }, + { + "name": "VendorTestOffset", + "desc": "Offset of the VENDOR_TEST partition", + "type": "int", + "default": "0", + "local": "true" + }, + { + "name": "VendorTestSize", + "desc": "Size of the VENDOR_TEST partition", + "type": "int", + "default": "64", + "local": "true" + }, + { + "name": "ScratchOffset", + "desc": "Offset of SCRATCH", + "type": "int", + "default": "0", + "local": "true" + }, + { + "name": "ScratchSize", + "desc": "Size of SCRATCH", + "type": "int", + "default": "56", + "local": "true" + }, + { + "name": "VendorTestDigestOffset", + "desc": "Offset of VENDOR_TEST_DIGEST", + "type": "int", + "default": "56", + "local": "true" + }, + { + "name": "VendorTestDigestSize", + "desc": "Size of VENDOR_TEST_DIGEST", + "type": "int", + "default": "8", + "local": "true" + }, + { + "name": "NonSecretFusesOffset", + "desc": "Offset of the NON_SECRET_FUSES partition", + "type": "int", + "default": "64", + "local": "true" + }, + { + "name": "NonSecretFusesSize", + "desc": "Size of the NON_SECRET_FUSES partition", + "type": "int", + "default": "3736", + "local": "true" + }, + { + "name": "FmcKeyManifestSvnOffset", + "desc": "Offset of FMC_KEY_MANIFEST_SVN", + "type": "int", + "default": "64", + "local": "true" + }, + { + "name": "FmcKeyManifestSvnSize", + "desc": "Size of FMC_KEY_MANIFEST_SVN", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "RuntimeSvnOffset", + "desc": "Offset of RUNTIME_SVN", + "type": "int", + "default": "68", + "local": "true" + }, + { + "name": "RuntimeSvnSize", + "desc": "Size of RUNTIME_SVN", + "type": "int", + "default": "16", + "local": "true" + }, + { + "name": "LmsVerifyOffset", + "desc": "Offset of LMS_VERIFY", + "type": "int", + "default": "84", + "local": "true" + }, + { + "name": "LmsVerifySize", + "desc": "Size of LMS_VERIFY", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "LmsRevocationOffset", + "desc": "Offset of LMS_REVOCATION", + "type": "int", + "default": "88", + "local": "true" + }, + { + "name": "LmsRevocationSize", + "desc": "Size of LMS_REVOCATION", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "KeyManifestPkHashMaskOffset", + "desc": "Offset of KEY_MANIFEST_PK_HASH_MASK", + "type": "int", + "default": "92", + "local": "true" + }, + { + "name": "KeyManifestPkHashMaskSize", + "desc": "Size of KEY_MANIFEST_PK_HASH_MASK", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "OwnerPkHashOffset", + "desc": "Offset of OWNER_PK_HASH", + "type": "int", + "default": "96", + "local": "true" + }, + { + "name": "OwnerPkHashSize", + "desc": "Size of OWNER_PK_HASH", + "type": "int", + "default": "48", + "local": "true" + }, + { + "name": "IdevidCertAttrOffset", + "desc": "Offset of IDEVID_CERT_ATTR", + "type": "int", + "default": "144", + "local": "true" + }, + { + "name": "IdevidCertAttrSize", + "desc": "Size of IDEVID_CERT_ATTR", + "type": "int", + "default": "96", + "local": "true" + }, + { + "name": "IdevidManufHsmIdOffset", + "desc": "Offset of IDEVID_MANUF_HSM_ID", + "type": "int", + "default": "240", + "local": "true" + }, + { + "name": "IdevidManufHsmIdSize", + "desc": "Size of IDEVID_MANUF_HSM_ID", + "type": "int", + "default": "16", + "local": "true" + }, + { + "name": "SocSteppingIdOffset", + "desc": "Offset of SOC_STEPPING_ID", + "type": "int", + "default": "256", + "local": "true" + }, + { + "name": "SocSteppingIdSize", + "desc": "Size of SOC_STEPPING_ID", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "NonSecretFusesDigestOffset", + "desc": "Offset of NON_SECRET_FUSES_DIGEST", + "type": "int", + "default": "3792", + "local": "true" + }, + { + "name": "NonSecretFusesDigestSize", + "desc": "Size of NON_SECRET_FUSES_DIGEST", + "type": "int", + "default": "8", + "local": "true" + }, + { + "name": "Secret0Offset", + "desc": "Offset of the SECRET0 partition", + "type": "int", + "default": "3800", + "local": "true" + }, + { + "name": "Secret0Size", + "desc": "Size of the SECRET0 partition", + "type": "int", + "default": "40", + "local": "true" + }, + { + "name": "TestUnlockTokenOffset", + "desc": "Offset of TEST_UNLOCK_TOKEN", + "type": "int", + "default": "3800", + "local": "true" + }, + { + "name": "TestUnlockTokenSize", + "desc": "Size of TEST_UNLOCK_TOKEN", + "type": "int", + "default": "16", + "local": "true" + }, + { + "name": "TestExitTokenOffset", + "desc": "Offset of TEST_EXIT_TOKEN", + "type": "int", + "default": "3816", + "local": "true" + }, + { + "name": "TestExitTokenSize", + "desc": "Size of TEST_EXIT_TOKEN", + "type": "int", + "default": "16", + "local": "true" + }, + { + "name": "Secret0DigestOffset", + "desc": "Offset of SECRET0_DIGEST", + "type": "int", + "default": "3832", + "local": "true" + }, + { + "name": "Secret0DigestSize", + "desc": "Size of SECRET0_DIGEST", + "type": "int", + "default": "8", + "local": "true" + }, + { + "name": "Secret1Offset", + "desc": "Offset of the SECRET1 partition", + "type": "int", + "default": "3840", + "local": "true" + }, + { + "name": "Secret1Size", + "desc": "Size of the SECRET1 partition", + "type": "int", + "default": "56", + "local": "true" + }, + { + "name": "UdsSeedOffset", + "desc": "Offset of UDS_SEED", + "type": "int", + "default": "3840", + "local": "true" + }, + { + "name": "UdsSeedSize", + "desc": "Size of UDS_SEED", + "type": "int", + "default": "48", + "local": "true" + }, + { + "name": "Secret1DigestOffset", + "desc": "Offset of SECRET1_DIGEST", + "type": "int", + "default": "3888", + "local": "true" + }, + { + "name": "Secret1DigestSize", + "desc": "Size of SECRET1_DIGEST", + "type": "int", + "default": "8", + "local": "true" + }, + { + "name": "Secret2Offset", + "desc": "Offset of the SECRET2 partition", + "type": "int", + "default": "3896", + "local": "true" + }, + { + "name": "Secret2Size", + "desc": "Size of the SECRET2 partition", + "type": "int", + "default": "40", + "local": "true" + }, + { + "name": "FieldEntropyOffset", + "desc": "Offset of FIELD_ENTROPY", + "type": "int", + "default": "3896", + "local": "true" + }, + { + "name": "FieldEntropySize", + "desc": "Size of FIELD_ENTROPY", + "type": "int", + "default": "32", + "local": "true" + }, + { + "name": "Secret2DigestOffset", + "desc": "Offset of SECRET2_DIGEST", + "type": "int", + "default": "3928", + "local": "true" + }, + { + "name": "Secret2DigestSize", + "desc": "Size of SECRET2_DIGEST", + "type": "int", + "default": "8", + "local": "true" + }, + { + "name": "Secret3Offset", + "desc": "Offset of the SECRET3 partition", + "type": "int", + "default": "3936", + "local": "true" + }, + { + "name": "Secret3Size", + "desc": "Size of the SECRET3 partition", + "type": "int", + "default": "72", + "local": "true" + }, + { + "name": "KeyManifestPkHashOffset", + "desc": "Offset of KEY_MANIFEST_PK_HASH", + "type": "int", + "default": "3936", + "local": "true" + }, + { + "name": "KeyManifestPkHashSize", + "desc": "Size of KEY_MANIFEST_PK_HASH", + "type": "int", + "default": "48", + "local": "true" + }, + { + "name": "RmaTokenOffset", + "desc": "Offset of RMA_TOKEN", + "type": "int", + "default": "3984", + "local": "true" + }, + { + "name": "RmaTokenSize", + "desc": "Size of RMA_TOKEN", + "type": "int", + "default": "16", + "local": "true" + }, + { + "name": "Secret3DigestOffset", + "desc": "Offset of SECRET3_DIGEST", + "type": "int", + "default": "4000", + "local": "true" + }, + { + "name": "Secret3DigestSize", + "desc": "Size of SECRET3_DIGEST", + + "type": "int", + "default": "8", + "local": "true" + }, + { + "name": "LifeCycleOffset", + "desc": "Offset of the LIFE_CYCLE partition", + "type": "int", + "default": "4008", + "local": "true" + }, + { + "name": "LifeCycleSize", + "desc": "Size of the LIFE_CYCLE partition", + "type": "int", + "default": "88", + "local": "true" + }, + { + "name": "LcTransitionCntOffset", + "desc": "Offset of LC_TRANSITION_CNT", + "type": "int", + "default": "4008", + "local": "true" + }, + { + "name": "LcTransitionCntSize", + "desc": "Size of LC_TRANSITION_CNT", + "type": "int", + "default": "48", + "local": "true" + }, + { + "name": "LcStateOffset", + "desc": "Offset of LC_STATE", + "type": "int", + "default": "4056", + "local": "true" + }, + { + "name": "LcStateSize", + "desc": "Size of LC_STATE", + "type": "int", + "default": "40", + "local": "true" + } + ], + "inter_signal_list": [ + { + "struct": "", + "type": "io", + "name": "otp_ext_voltage_h", + "act": "none", + "default": "'0", + "package": "" + }, + { + "struct": "otp_ast_req", + "type": "uni", + "name": "otp_ast_pwr_seq", + "act": "req", + "default": "'0", + "package": "otp_ctrl_pkg", + "desc": "Power sequencing signals to AST (VDD domain)." + }, + { + "struct": "otp_ast_rsp", + "type": "uni", + "name": "otp_ast_pwr_seq_h", + "act": "rcv", + "default": "'0", + "package": "otp_ctrl_pkg", + "desc": "Power sequencing signals coming from AST (VCC domain)." + }, + { + "struct": "edn", + "type": "req_rsp", + "name": "edn", + "act": "req", + "package": "edn_pkg", + "desc": "Entropy request to the entropy distribution network for LFSR reseeding and ephemeral key derivation." + }, + { + "struct": "pwr_otp", + "type": "req_rsp", + "name": "pwr_otp", + "act": "rsp", + "default": "'0", + "package": "pwrmgr_pkg", + "desc": "Initialization request/acknowledge from/to power manager." + }, + { + "struct": "lc_otp_vendor_test", + "type": "req_rsp", + "name": "lc_otp_vendor_test", + "act": "rsp", + "default": "'0", + "package": "otp_ctrl_pkg", + "desc": "Vendor test control signals from/to the life cycle TAP." + }, + { + "struct": "lc_otp_program", + "type": "req_rsp", + "name": "lc_otp_program", + "act": "rsp", + "default": "'0", + "package": "otp_ctrl_pkg", + "desc": "Life cycle state transition interface." + }, + { + "struct": "otp_lc_data", + "type": "uni", + "name": "otp_lc_data", + "act": "req", + "default": "'0", + "package": "otp_ctrl_pkg", + "desc": "Life cycle state output holding the current life cycle state,\nthe value of the transition counter and the tokens needed for life cycle transitions." + }, + { + "struct": "lc_tx", + "type": "uni", + "name": "lc_escalate_en", + "act": "rcv", + "default": "lc_ctrl_pkg::Off", + "package": "lc_ctrl_pkg", + "desc": "Life cycle escalation enable coming from life cycle controller.\nThis signal moves all FSMs within OTP into the error state." + }, + { + "struct": "lc_tx", + "type": "uni", + "name": "lc_creator_seed_sw_rw_en", + "act": "rcv", + "default": "lc_ctrl_pkg::Off", + "package": "lc_ctrl_pkg", + "desc": "Provision enable qualifier coming from life cycle controller.\nThis signal enables SW read / write access to the RMA_TOKEN and CREATOR_ROOT_KEY_SHARE0 and CREATOR_ROOT_KEY_SHARE1." + }, + { + "struct": "lc_tx", + "type": "uni", + "name": "lc_owner_seed_sw_rw_en", + "act": "rcv", + "default": "lc_ctrl_pkg::Off", + "package": "lc_ctrl_pkg", + "desc": "Provision enable qualifier coming from life cycle controller.\nThis signal enables SW read / write access to the OWNER_SEED." + }, + { + "struct": "lc_tx", + "type": "uni", + "name": "lc_seed_hw_rd_en", + "act": "rcv", + "default": "lc_ctrl_pkg::Off", + "package": "lc_ctrl_pkg", + "desc": "Seed read enable coming from life cycle controller.\nThis signal enables HW read access to the CREATOR_ROOT_KEY_SHARE0 and CREATOR_ROOT_KEY_SHARE1." + }, + { + "struct": "lc_tx", + "type": "uni", + "name": "lc_dft_en", + "act": "rcv", + "default": "lc_ctrl_pkg::Off", + "package": "lc_ctrl_pkg", + "desc": "Test enable qualifier coming from life cycle controller.\nThis signals enables the TL-UL access port to the proprietary OTP IP." + }, + { + "struct": "lc_tx", + "type": "uni", + "name": "lc_check_byp_en", + "act": "rcv", + "default": "lc_ctrl_pkg::Off", + "package": "lc_ctrl_pkg", + "desc": "Life cycle partition check bypass signal.\nThis signal causes the life cycle partition to bypass consistency checks during life cycle state transitions in order to prevent spurious consistency check failures." + }, + { + "struct": "otp_keymgr_key", + "type": "uni", + "name": "otp_keymgr_key", + "act": "req", + "default": "'0", + "package": "otp_ctrl_pkg", + "desc": "Key output to the key manager holding CREATOR_ROOT_KEY_SHARE0 and CREATOR_ROOT_KEY_SHARE1." + }, + { + "struct": "flash_otp_key", + "type": "req_rsp", + "name": "flash_otp_key", + "act": "rsp", + "default": "'0", + "package": "otp_ctrl_pkg", + "desc": "Key derivation interface for FLASH scrambling." + }, + { + "struct": "sram_otp_key", + "width": "4", + "type": "req_rsp", + "name": "sram_otp_key", + "act": "rsp", + "default": "'0", + "package": "otp_ctrl_pkg", + "desc": "Array with key derivation interfaces for SRAM scrambling devices." + }, + { + "struct": "otbn_otp_key", + "type": "req_rsp", + "name": "otbn_otp_key", + "act": "rsp", + "default": "'0", + "package": "otp_ctrl_pkg", + "desc": "Key derivation interface for OTBN scrambling devices." + }, + { + "struct": "otp_broadcast", + "type": "uni", + "name": "otp_broadcast", + "act": "req", + "default": "'0", + "package": "otp_ctrl_part_pkg", + "desc": "Output of the HW partitions with breakout data types." + }, + { + "struct": "ast_obs_ctrl", + "type": "uni", + "name": "obs_ctrl", + "act": "rcv", + "package": "ast_pkg", + "desc": "AST observability control signals." + }, + { + "struct": "logic", + "type": "uni", + "name": "otp_obs", + "act": "req", + "width": "8", + "package": "", + "desc": "AST observability bus." + } + ], + "countermeasures": [ + { + "name": "BUS.INTEGRITY", + "desc": "End-to-end bus integrity scheme." + }, + { + "name": "SECRET.MEM.SCRAMBLE", + "desc": "Secret partitions are scrambled with a full-round PRESENT cipher." + }, + { + "name": "PART.MEM.DIGEST", + "desc": "Integrity of buffered partitions is ensured via a 64bit digest." + }, + { + "name": "DAI.FSM.SPARSE", + "desc": "The direct access interface FSM is sparsely encoded." + }, + { + "name": "KDI.FSM.SPARSE", + "desc": "The key derivation interface FSM is sparsely encoded." + }, + { + "name": "LCI.FSM.SPARSE", + "desc": "The life cycle interface FSM is sparsely encoded." + }, + { + "name": "PART.FSM.SPARSE", + "desc": "The partition FSMs are sparsely encoded." + }, + { + "name": "SCRMBL.FSM.SPARSE", + "desc": "The scramble datapath FSM is sparsely encoded." + }, + { + "name": "TIMER.FSM.SPARSE", + "desc": "The background check timer FSM is sparsely encoded." + }, + { + "name": "DAI.CTR.REDUN", + "desc": "The direct access interface address counter employs a cross-counter implementation." + }, + { + "name": "KDI_SEED.CTR.REDUN", + "desc": "The key derivation interface counter employs a cross-counter implementation." + }, + { + "name": "KDI_ENTROPY.CTR.REDUN", + "desc": "The key derivation entropy counter employs a cross-counter implementation." + }, + { + "name": "LCI.CTR.REDUN", + "desc": "The life cycle interface address counter employs a cross-counter implementation." + }, + { + "name": "PART.CTR.REDUN", + "desc": "The address counter of buffered partitions employs a cross-counter implementation." + }, + { + "name": "SCRMBL.CTR.REDUN", + "desc": "The srambling datapath counter employs a cross-counter implementation." + }, + { + "name": "TIMER_INTEG.CTR.REDUN", + "desc": "The background integrity check timer employs a duplicated counter implementation." + }, + { + "name": "TIMER_CNSTY.CTR.REDUN", + "desc": "The background consistency check timer employs a duplicated counter implementation." + }, + { + "name": "TIMER.LFSR.REDUN", + "desc": "The background check LFSR is duplicated." + }, + { + "name": "DAI.FSM.LOCAL_ESC", + "desc": "The direct access interface FSM is moved into an invalid state upon local escalation." + }, + { + "name": "LCI.FSM.LOCAL_ESC", + "desc": "The life cycle interface FSM is moved into an invalid state upon local escalation." + }, + { + "name": "KDI.FSM.LOCAL_ESC", + "desc": "The key derivation interface FSM is moved into an invalid state upon local escalation." + }, + { + "name": "PART.FSM.LOCAL_ESC", + "desc": "The partition FSMs are moved into an invalid state upon local escalation." + }, + { + "name": "SCRMBL.FSM.LOCAL_ESC", + "desc": "The scramble datapath FSM is moved into an invalid state upon local escalation." + }, + { + "name": "TIMER.FSM.LOCAL_ESC", + "desc": "The background check timer FSM is moved into an invalid state upon local escalation." + }, + { + "name": "DAI.FSM.GLOBAL_ESC", + "desc": "The direct access interface FSM is moved into an invalid state upon global escalation via life cycle." + }, + { + "name": "LCI.FSM.GLOBAL_ESC", + "desc": "The life cycle interface FSM is moved into an invalid state upon global escalation via life cycle." + }, + { + "name": "KDI.FSM.GLOBAL_ESC", + "desc": "The key derivation interface FSM is moved into an invalid state upon global escalation via life cycle." + }, + { + "name": "PART.FSM.GLOBAL_ESC", + "desc": "The partition FSMs are moved into an invalid state upon global escalation via life cycle." + }, + { + "name": "SCRMBL.FSM.GLOBAL_ESC", + "desc": "The scramble datapath FSM is moved into an invalid state upon global escalation via life cycle." + }, + { + "name": "TIMER.FSM.GLOBAL_ESC", + "desc": "The background check timer FSM is moved into an invalid state upon global escalation via life cycle." + }, + { + "name": "PART.DATA_REG.INTEGRITY", + "desc": "All partition buffer registers are protected with ECC on 64bit blocks." + }, + { + "name": "PART.DATA_REG.BKGN_CHK", + "desc": "The digest of buffered partitions is recomputed and checked at pseudorandom intervals in the background." + }, + { + "name": "PART.MEM.REGREN", + "desc": "Unbuffered ('software') partitions can be read-locked via a CSR until the next system reset." + }, + { + "name": "PART.MEM.SW_UNREADABLE", + "desc": "Secret buffered partitions become unreadable to software once they are locked via the digest." + }, + { + "name": "PART.MEM.SW_UNWRITABLE", + "desc": "All partitions become unwritable by software once they are locked via the digest." + }, + { + "name": "LC_PART.MEM.SW_NOACCESS", + "desc": "The life cycle partition is not directly readable nor writable via software." + }, + { + "name": "ACCESS.CTRL.MUBI", + "desc": "The access control signals going from the partitions to the DAI are MUBI encoded." + }, + { + "name": "TOKEN_VALID.CTRL.MUBI", + "desc": "The token valid signals going to the life cycle controller are MUBI encoded." + }, + { + "name": "LC_CTRL.INTERSIG.MUBI", + "desc": "The life cycle control signals are multibit encoded." + }, + { + "name": "TEST.BUS.LC_GATED", + "desc": "Prevent access to test signals and the OTP backdoor interface in non-test lifecycle states." + }, + { + "name": "TEST_TL_LC_GATE.FSM.SPARSE", + "desc": "The control FSM inside the TL-UL gating primitive is sparsely encoded." + }, + { + "name": "DIRECT_ACCESS.CONFIG.REGWEN", + "desc": "The direct access CSRs are REGWEN protected." + }, + { + "name": "CHECK_TRIGGER.CONFIG.REGWEN", + "desc": "The check trigger CSR is REGWEN protected." + }, + { + "name": "CHECK.CONFIG.REGWEN", + "desc": "The check CSR is REGWEN protected." + }, + { + "name": "MACRO.MEM.INTEGRITY", + "desc": " The OTP macro employs a vendor-specific integrity scheme at the granularity of the native 16bit OTP words.\n The scheme is able to at least detect single bit errors.\n " + }, + { + "name": "MACRO.MEM.CM", + "desc": "The OTP macro may contain additional vendor-specific countermeasures." + } + ], + "features": [ + { + "name": "OTP_CTRL.PARTITION.VENDOR_TEST", + "desc": "Vendor test partition is used for OTP programming smoke check during manufacturing flow.\nIn this partition, ECC uncorrectable errors will not lead to fatal errors and alerts.\nInstead the error will be reported as correctable ECC error." + }, + { + "name": "OTP_CTRL.PARTITION.CREATOR_SW_CFG", + "desc": "During calibration stage, various parameters (clock, voltage, and timing sources) are calibrated and recorded to CREATOR_SW_CFG partition." + }, + { + "name": "OTP_CTRL.INIT", + "desc": "When power is up, OTP controller reads devices status.\nAfter all reads complete, the controller performs integrity check on the HW_CFG* and SECRET partitions.\nOnce all integrity checks are complete, the controller marks outputs as valid." + }, + { + "name": "OTP_CTRL.PROGRAM", + "desc": "All other partitions except life cycle partition are programmed through DAI interface.\nAnd once non-zero digest is programmed to these partition, no further write access is allowed.\nLife cycle partition is programmed by LC_CTRL." + }, + { + "name": "OTP_CTRL.PARTITION.SECRET0", + "desc": "Obfuscated UDS Seed" + }, + { + "name": "OTP_CTRL.PARTITION.SECRET1", + "desc": "Obfuscated Field Entropy" + }, + { + "name": "OTP_CTRL.PARTITION.LIFE_CYCLE", + "desc": "LC state, LC transition count.\nThis feature is owned by the LC_CTRL and cannot be tested well through the OTP_CTRL CSR interface." + }, + { + "name": "OTP_CTRL.PARTITIONS_FEATURE.READ_LOCK", + "desc": "Following partitions can be read lockable by CSR.\n - VENDOR_TEST\n - CREATOR_SW_CFG\n Following partitions can be read lockable by writing digest.\n - SECRET0\n - SECRET1\nAll read attempt to these partitions after read is locked will trigger AccessError (recoverable)." + }, + { + "name": "OTP_CTRL.PARTITIONS_FEATURE.WRITE_LOCK", + "desc": "All partitions except LIFE_CYCLE can be write lockable by writing digest." + }, + { + "name": "OTP_CTRL.ERROR_HANDLING.RECOVERABLE", + "desc": "Recoverable error is created when unauthorized access atempt are detected via dai interface." + }, + { + "name": "OTP_CTRL.ERROR_HANDLING.FATAL", + "desc": "Unrecoverable errors are created for uncorrectable ecc error, otp macro malfunction and unauthorized access via lc_ctrl." + }, + { + "name": "OTP_CTRL.BACKGROUND_CHECK.CHECK_TIMEOUT", + "desc": "Timeout value for the integrity and consistency checks." + }, + { + "name": "OTP_CTRL.BACKGROUND_CHECK.INTEGRITY_CHECK_PERIOD", + "desc": "The interval which the digest of the partition is recomputed to check integrity of locked partition." + }, + { + "name": "OTP_CTRL.BACKGROUND_CHECK.CONSISTENCY_CHECK_PERIOD", + "desc": "Re-read period of the buffer registers to ensure data is matched with the associated OTP partition." + } + ], + "regwidth": "32", + "registers": { + "core": [ + { + "name": "STATUS", + "desc": "OTP status register.", + "swaccess": "ro", + "hwaccess": "hwo", + "hwext": "true", + "resval": 0, + "tags": [ + "excl:CsrAllTests:CsrExclCheck" + ], + "fields": [ + { + "bits": "0", + "name": "VENDOR_TEST_ERROR", + "desc": "Set to 1 if an error occurred in this partition.\nIf set to 1, SW should check the !!ERR_CODE register at the corresponding index." + }, + { + "bits": "1", + "name": "NON_SECRET_FUSES_ERROR", + "desc": "Set to 1 if an error occurred in this partition.\nIf set to 1, SW should check the !!ERR_CODE register at the corresponding index." + }, + { + "bits": "2", + "name": "SECRET0_ERROR", + "desc": "Set to 1 if an error occurred in this partition.\nIf set to 1, SW should check the !!ERR_CODE register at the corresponding index." + }, + { + "bits": "3", + "name": "SECRET1_ERROR", + "desc": "Set to 1 if an error occurred in this partition.\nIf set to 1, SW should check the !!ERR_CODE register at the corresponding index." + }, + { + "bits": "4", + "name": "SECRET2_ERROR", + "desc": "Set to 1 if an error occurred in this partition.\nIf set to 1, SW should check the !!ERR_CODE register at the corresponding index." + }, + { + "bits": "5", + "name": "SECRET3_ERROR", + "desc": "Set to 1 if an error occurred in this partition.\nIf set to 1, SW should check the !!ERR_CODE register at the corresponding index." + }, + { + "bits": "6", + "name": "LIFE_CYCLE_ERROR", + "desc": "Set to 1 if an error occurred in this partition.\nIf set to 1, SW should check the !!ERR_CODE register at the corresponding index." + }, + { + "bits": "7", + "name": "DAI_ERROR", + "desc": "Set to 1 if an error occurred in the DAI.\nIf set to 1, SW should check the !!ERR_CODE register at the corresponding index." + }, + { + "bits": "8", + "name": "LCI_ERROR", + "desc": "Set to 1 if an error occurred in the LCI.\nIf set to 1, SW should check the !!ERR_CODE register at the corresponding index." + }, + { + "bits": "9", + "name": "TIMEOUT_ERROR", + "desc": "Set to 1 if an integrity or consistency check times out.\nThis raises an fatal_check_error alert and is an unrecoverable error condition." + }, + { + "bits": "10", + "name": "LFSR_FSM_ERROR", + "desc": "Set to 1 if the LFSR timer FSM has reached an invalid state.\nThis raises an fatal_check_error alert and is an unrecoverable error condition." + }, + { + "bits": "11", + "name": "SCRAMBLING_FSM_ERROR", + "desc": "Set to 1 if the scrambling datapath FSM has reached an invalid state.\nThis raises an fatal_check_error alert and is an unrecoverable error condition." + }, + { + "bits": "12", + "name": "KEY_DERIV_FSM_ERROR", + "desc": "Set to 1 if the key derivation FSM has reached an invalid state.\nThis raises an fatal_check_error alert and is an unrecoverable error condition." + }, + { + "bits": "13", + "name": "BUS_INTEG_ERROR", + "desc": "This bit is set to 1 if a fatal bus integrity fault is detected.\nThis error triggers a fatal_bus_integ_error alert." + }, + { + "bits": "14", + "name": "DAI_IDLE", + "desc": "Set to 1 if the DAI is idle and ready to accept commands." + }, + { + "bits": "15", + "name": "CHECK_PENDING", + "desc": "Set to 1 if an integrity or consistency check triggered by the LFSR timer or via !!CHECK_TRIGGER is pending." + } + ] + }, + { + "multireg": { + "name": "ERR_CODE", + "desc": "This register holds information about error conditions that occurred in the agents\ninteracting with the OTP macro via the internal bus. The error codes should be checked\nif the partitions, DAI or LCI flag an error in the !!STATUS register, or when an\n!!INTR_STATE.otp_error has been triggered. Note that all errors trigger an otp_error\ninterrupt, and in addition some errors may trigger either an fatal_macro_error or an\nfatal_check_error alert.", + "count": "NumErrorEntries", + "swaccess": "ro", + "hwaccess": "hwo", + "hwext": "true", + "cname": "AGENT", + "compact": "false", + "resval": 0, + "tags": [ + "excl:CsrAllTests:CsrExclCheck" + ], + "fields": [ + { + "bits": "2:0", + "enum": [ + { + "value": "0", + "name": "NO_ERROR", + "desc": "No error condition has occurred." + }, + { + "value": "1", + "name": "MACRO_ERROR", + "desc": "Returned if the OTP macro command was invalid or did not complete successfully\ndue to a macro malfunction.\nThis error should never occur during normal operation and is not recoverable.\nThis error triggers an fatal_macro_error alert." + }, + { + "value": "2", + "name": "MACRO_ECC_CORR_ERROR", + "desc": "A correctable ECC error has occured during an OTP read operation.\nThe corresponding controller automatically recovers from this error when\nissuing a new command." + }, + { + "value": "3", + "name": "MACRO_ECC_UNCORR_ERROR", + "desc": "An uncorrectable ECC error has occurred during an OTP read operation.\nThis error should never occur during normal operation and is not recoverable.\nIf this error is present this may be a sign that the device is malfunctioning.\nThis error triggers an fatal_macro_error alert." + }, + { + "value": "4", + "name": "MACRO_WRITE_BLANK_ERROR", + "desc": "This error is returned if a programming operation attempted to clear a bit that has previously been programmed to 1.\nThe corresponding controller automatically recovers from this error when issuing a new command.\n\nNote however that the affected OTP word may be left in an inconsistent state if this error occurs.\nThis can cause several issues when the word is accessed again (either as part of a regular read operation, as part of the readout at boot, or as part of a background check).\n\nIt is important that SW ensures that each word is only written once, since this can render the device useless." + }, + { + "value": "5", + "name": "ACCESS_ERROR", + "desc": "This error indicates that a locked memory region has been accessed.\nThe corresponding controller automatically recovers from this error when issuing a new command." + }, + { + "value": "6", + "name": "CHECK_FAIL_ERROR", + "desc": "An ECC, integrity or consistency mismatch has been detected in the buffer registers.\nThis error should never occur during normal operation and is not recoverable.\nThis error triggers an fatal_check_error alert." + }, + { + "value": "7", + "name": "FSM_STATE_ERROR", + "desc": "The FSM of the corresponding controller has reached an invalid state, or the FSM has\nbeen moved into a terminal error state due to an escalation action via lc_escalate_en_i.\nThis error should never occur during normal operation and is not recoverable.\nIf this error is present, this is a sign that the device has fallen victim to\nan invasive attack. This error triggers an fatal_check_error alert." + } + ] + } + ] + } + }, + { + "name": "DIRECT_ACCESS_REGWEN", + "desc": "Register write enable for all direct access interface registers.", + "swaccess": "rw0c", + "hwaccess": "hrw", + "hwext": "true", + "hwqe": "true", + "tags": [ + "excl:CsrNonInitTests:CsrExclCheck" + ], + "fields": [ + { + "bits": "0", + "desc": "This bit controls whether the DAI registers can be written.\nWrite 0 to it in order to clear the bit.\n\nNote that the hardware also modulates this bit and sets it to 0 temporarily\nduring an OTP operation such that the corresponding address and data registers\ncannot be modified while an operation is pending. The !!DAI_IDLE status bit\nwill also be set to 0 in such a case.", + "resval": 1 + } + ] + }, + { + "name": "DIRECT_ACCESS_CMD", + "desc": "Command register for direct accesses.", + "swaccess": "r0w1c", + "hwaccess": "hro", + "hwqe": "true", + "hwext": "true", + "resval": 0, + "regwen": "DIRECT_ACCESS_REGWEN", + "tags": [ + "excl:CsrNonInitTests:CsrExclWrite" + ], + "fields": [ + { + "bits": "0", + "name": "RD", + "desc": "Initiates a readout sequence that reads the location specified\nby !!DIRECT_ACCESS_ADDRESS. The command places the data read into\n!!DIRECT_ACCESS_RDATA_0 and !!DIRECT_ACCESS_RDATA_1 (for 64bit partitions)." + }, + { + "bits": "1", + "name": "WR", + "desc": "Initiates a programming sequence that writes the data in !!DIRECT_ACCESS_WDATA_0\nand !!DIRECT_ACCESS_WDATA_1 (for 64bit partitions) to the location specified by\n!!DIRECT_ACCESS_ADDRESS." + }, + { + "bits": "2", + "name": "DIGEST", + "desc": "Initiates the digest calculation and locking sequence for the partition specified by\n!!DIRECT_ACCESS_ADDRESS." + } + ] + }, + { + "name": "DIRECT_ACCESS_ADDRESS", + "desc": "Address register for direct accesses.", + "swaccess": "rw", + "hwaccess": "hro", + "hwqe": "false", + "resval": 0, + "regwen": "DIRECT_ACCESS_REGWEN", + "tags": [ + "excl:CsrNonInitTests:CsrExclCheck" + ], + "fields": [ + { + "bits": "OtpByteAddrWidth-1:0", + "desc": "This is the address for the OTP word to be read or written through\nthe direct access interface. Note that the address is aligned to the access size\ninternally, hence bits 1:0 are ignored for 32bit accesses, and bits 2:0 are ignored\nfor 64bit accesses.\n\nFor the digest calculation command, set this register to the partition base offset." + } + ] + }, + { + "multireg": { + "name": "DIRECT_ACCESS_WDATA", + "desc": "Write data for direct accesses.\n Hardware automatically determines the access granule (32bit or 64bit) based on which\n partition is being written to.\n ", + "count": "NumDaiWords", + "swaccess": "rw", + "hwaccess": "hro", + "hwqe": "false", + "regwen": "DIRECT_ACCESS_REGWEN", + "cname": "WORD", + "resval": 0, + "tags": [ + "excl:CsrAllTests:CsrExclCheck" + ], + "fields": [ + { + "bits": "31:0" + } + ] + } + }, + { + "multireg": { + "name": "DIRECT_ACCESS_RDATA", + "desc": "Read data for direct accesses.\n Hardware automatically determines the access granule (32bit or 64bit) based on which\n partition is read from.\n ", + "count": "NumDaiWords", + "swaccess": "ro", + "hwaccess": "hwo", + "hwext": "true", + "cname": "WORD", + "resval": 0, + "fields": [ + { + "bits": "31:0" + } + ] + } + }, + { + "name": "CHECK_TRIGGER_REGWEN", + "desc": "Register write enable for !!CHECK_TRIGGER.", + "swaccess": "rw0c", + "hwaccess": "none", + "fields": [ + { + "bits": "0", + "desc": "When cleared to 0, the !!CHECK_TRIGGER register cannot be written anymore.\nWrite 0 to clear this bit.", + "resval": 1 + } + ] + }, + { + "name": "CHECK_TRIGGER", + "desc": "Command register for direct accesses.", + "swaccess": "r0w1c", + "hwaccess": "hro", + "hwqe": "true", + "hwext": "true", + "resval": 0, + "regwen": "CHECK_TRIGGER_REGWEN", + "fields": [ + { + "bits": "0", + "name": "INTEGRITY", + "desc": "Writing 1 to this bit triggers an integrity check. SW should monitor !!STATUS.CHECK_PENDING\nand wait until the check has been completed. If there are any errors, those will be flagged\nin the !!STATUS and !!ERR_CODE registers, and via the interrupts and alerts." + }, + { + "bits": "1", + "name": "CONSISTENCY", + "desc": "Writing 1 to this bit triggers a consistency check. SW should monitor !!STATUS.CHECK_PENDING\nand wait until the check has been completed. If there are any errors, those will be flagged\nin the !!STATUS and !!ERR_CODE registers, and via interrupts and alerts." + } + ] + }, + { + "name": "CHECK_REGWEN", + "desc": "Register write enable for !!INTEGRITY_CHECK_PERIOD and !!CONSISTENCY_CHECK_PERIOD.", + "swaccess": "rw0c", + "hwaccess": "none", + "fields": [ + { + "bits": "0", + "desc": "When cleared to 0, !!INTEGRITY_CHECK_PERIOD and !!CONSISTENCY_CHECK_PERIOD registers cannot be written anymore.\nWrite 0 to clear this bit.", + "resval": 1 + } + ] + }, + { + "name": "CHECK_TIMEOUT", + "desc": "Timeout value for the integrity and consistency checks.", + "swaccess": "rw", + "hwaccess": "hro", + "regwen": "CHECK_REGWEN", + "tags": [ + "excl:CsrAllTests:CsrExclWrite" + ], + "fields": [ + { + "bits": "31:0", + "desc": "Timeout value in cycles for the for the integrity and consistency checks. If an integrity or consistency\ncheck does not complete within the timeout window, an error will be flagged in the !!STATUS register,\nan otp_error interrupt will be raised, and an fatal_check_error alert will be sent out. The timeout should\nbe set to a large value to stay on the safe side. The maximum check time can be upper bounded by the\nnumber of cycles it takes to readout, scramble and digest the entire OTP array. Since this amounts to\nroughly 25k cycles, it is recommended to set this value to at least 100'000 cycles in order to stay on the\nsafe side. A value of zero disables the timeout mechanism (default).", + "resval": 0 + } + ] + }, + { + "name": "INTEGRITY_CHECK_PERIOD", + "desc": "This value specifies the maximum period that can be generated pseudo-randomly.\nOnly applies to the HW_CFG* and SECRET* partitions once they are locked.", + "swaccess": "rw", + "hwaccess": "hro", + "regwen": "CHECK_REGWEN", + "fields": [ + { + "bits": "31:0", + "desc": "The pseudo-random period is generated using a 40bit LFSR internally, and this register defines\nthe bit mask to be applied to the LFSR output in order to limit its range. The value of this\nregister is left shifted by 8bits and the lower bits are set to 8'hFF in order to form the 40bit mask.\nA recommended value is 0x3_FFFF, corresponding to a maximum period of ~2.8s at 24MHz.\nA value of zero disables the timer (default). Note that a one-off check can always be triggered via\n!!CHECK_TRIGGER.INTEGRITY.", + "resval": "0" + } + ] + }, + { + "name": "CONSISTENCY_CHECK_PERIOD", + "desc": "This value specifies the maximum period that can be generated pseudo-randomly.\nThis applies to the LIFE_CYCLE partition and the HW_CFG* and SECRET* partitions once they are locked.", + "swaccess": "rw", + "hwaccess": "hro", + "regwen": "CHECK_REGWEN", + "fields": [ + { + "bits": "31:0", + "desc": "The pseudo-random period is generated using a 40bit LFSR internally, and this register defines\nthe bit mask to be applied to the LFSR output in order to limit its range. The value of this\nregister is left shifted by 8bits and the lower bits are set to 8'hFF in order to form the 40bit mask.\nA recommended value is 0x3FF_FFFF, corresponding to a maximum period of ~716s at 24MHz.\nA value of zero disables the timer (default). Note that a one-off check can always be triggered via\n!!CHECK_TRIGGER.CONSISTENCY.", + "resval": "0" + } + ] + }, + { + "name": "VENDOR_TEST_READ_LOCK", + "desc": "Runtime read lock for the VENDOR_TEST partition.", + "swaccess": "rw0c", + "hwaccess": "hro", + "regwen": "DIRECT_ACCESS_REGWEN", + "tags": [ + "excl:CsrNonInitTests:CsrExclWrite" + ], + "fields": [ + { + "bits": "0", + "desc": "When cleared to 0, read access to the VENDOR_TEST partition is locked.\nWrite 0 to clear this bit.", + "resval": 1 + } + ] + }, + { + "name": "NON_SECRET_FUSES_READ_LOCK", + "desc": "Runtime read lock for the NON_SECRET_FUSES partition.", + "swaccess": "rw0c", + "hwaccess": "hro", + "regwen": "DIRECT_ACCESS_REGWEN", + "tags": [ + "excl:CsrNonInitTests:CsrExclWrite" + ], + "fields": [ + { + "bits": "0", + "desc": "When cleared to 0, read access to the NON_SECRET_FUSES partition is locked.\nWrite 0 to clear this bit.", + "resval": 1 + } + ] + }, + { + "multireg": { + "name": "VENDOR_TEST_DIGEST", + "desc": " Integrity digest for the VENDOR_TEST partition.\n The integrity digest is 0 by default. Software must write this\n digest value via the direct access interface in order to lock the partition.\n After a reset, write access to the VENDOR_TEST partition is locked and\n the digest becomes visible in this CSR.\n ", + "count": "NumDigestWords", + "swaccess": "ro", + "hwaccess": "hwo", + "hwext": "true", + "cname": "WORD", + "resval": 0, + "tags": [ + "excl:CsrAllTests:CsrExclCheck" + ], + "fields": [ + { + "bits": "31:0" + } + ] + } + }, + { + "multireg": { + "name": "NON_SECRET_FUSES_DIGEST", + "desc": " Integrity digest for the NON_SECRET_FUSES partition.\n The integrity digest is 0 by default. Software must write this\n digest value via the direct access interface in order to lock the partition.\n After a reset, write access to the NON_SECRET_FUSES partition is locked and\n the digest becomes visible in this CSR.\n ", + "count": "NumDigestWords", + "swaccess": "ro", + "hwaccess": "hwo", + "hwext": "true", + "cname": "WORD", + "resval": 0, + "tags": [ + "excl:CsrAllTests:CsrExclCheck" + ], + "fields": [ + { + "bits": "31:0" + } + ] + } + }, + { + "multireg": { + "name": "SECRET0_DIGEST", + "desc": " Integrity digest for the SECRET0 partition.\n The integrity digest is 0 by default. The digest calculation can be triggered via the !!DIRECT_ACCESS_CMD.\n After a reset, the digest then becomes visible in this CSR, and the corresponding partition becomes write-locked.\n ", + "count": "NumDigestWords", + "swaccess": "ro", + "hwaccess": "hwo", + "hwext": "true", + "cname": "WORD", + "resval": 0, + "tags": [ + "excl:CsrAllTests:CsrExclCheck" + ], + "fields": [ + { + "bits": "31:0" + } + ] + } + }, + { + "multireg": { + "name": "SECRET1_DIGEST", + "desc": " Integrity digest for the SECRET1 partition.\n The integrity digest is 0 by default. The digest calculation can be triggered via the !!DIRECT_ACCESS_CMD.\n After a reset, the digest then becomes visible in this CSR, and the corresponding partition becomes write-locked.\n ", + "count": "NumDigestWords", + "swaccess": "ro", + "hwaccess": "hwo", + "hwext": "true", + "cname": "WORD", + "resval": 0, + "tags": [ + "excl:CsrAllTests:CsrExclCheck" + ], + "fields": [ + { + "bits": "31:0" + } + ] + } + }, + { + "multireg": { + "name": "SECRET2_DIGEST", + "desc": " Integrity digest for the SECRET2 partition.\n The integrity digest is 0 by default. The digest calculation can be triggered via the !!DIRECT_ACCESS_CMD.\n After a reset, the digest then becomes visible in this CSR, and the corresponding partition becomes write-locked.\n ", + "count": "NumDigestWords", + "swaccess": "ro", + "hwaccess": "hwo", + "hwext": "true", + "cname": "WORD", + "resval": 0, + "tags": [ + "excl:CsrAllTests:CsrExclCheck" + ], + "fields": [ + { + "bits": "31:0" + } + ] + } + }, + { + "multireg": { + "name": "SECRET3_DIGEST", + "desc": " Integrity digest for the SECRET3 partition.\n The integrity digest is 0 by default. The digest calculation can be triggered via the !!DIRECT_ACCESS_CMD.\n After a reset, the digest then becomes visible in this CSR, and the corresponding partition becomes write-locked.\n ", + "count": "NumDigestWords", + "swaccess": "ro", + "hwaccess": "hwo", + "hwext": "true", + "cname": "WORD", + "resval": 0, + "tags": [ + "excl:CsrAllTests:CsrExclCheck" + ], + "fields": [ + { + "bits": "31:0" + } + ] + } + } + ], + "prim": [ + { + "name": "CSR0", + "desc": "", + "swaccess": "rw", + "hwaccess": "hro", + "hwext": "false", + "hwqe": "false", + "fields": [ + { + "bits": "0", + "name": "field0", + "desc": "", + "resval": "0x0" + }, + { + "bits": "1", + "name": "field1", + "desc": "", + "resval": "0x0" + }, + { + "bits": "2", + "name": "field2", + "desc": "", + "resval": "0x0" + }, + { + "bits": "13:4", + "name": "field3", + "desc": "", + "resval": "0x0" + }, + { + "bits": "26:16", + "name": "field4", + "desc": "", + "resval": "0x0" + } + ] + }, + { + "name": "CSR1", + "desc": "", + "swaccess": "rw", + "hwaccess": "hro", + "hwext": "false", + "hwqe": "false", + "fields": [ + { + "bits": "6:0", + "name": "field0", + "desc": "", + "resval": "0x0" + }, + { + "bits": "7:7", + "name": "field1", + "desc": "", + "resval": "0x0" + }, + { + "bits": "14:8", + "name": "field2", + "desc": "", + "resval": "0x0" + }, + { + "bits": "15:15", + "name": "field3", + "desc": "", + "resval": "0x0" + }, + { + "bits": "31:16", + "name": "field4", + "desc": "", + "resval": "0x0" + } + ] + }, + { + "name": "CSR2", + "desc": "", + "swaccess": "rw", + "hwaccess": "hro", + "hwext": "false", + "hwqe": "false", + "fields": [ + { + "bits": "0", + "name": "field0", + "desc": "", + "resval": "0x0" + } + ] + }, + { + "name": "CSR3", + "desc": "", + "swaccess": "rw", + "hwaccess": "hrw", + "hwext": "false", + "hwqe": "false", + "fields": [ + { + "bits": "2:0", + "name": "field0", + "desc": "", + "swaccess": "rw1c", + "resval": "0x0" + }, + { + "bits": "13:4", + "name": "field1", + "desc": "", + "swaccess": "rw1c", + "resval": "0x0" + }, + { + "bits": "16", + "name": "field2", + "desc": "", + "swaccess": "rw1c", + "resval": "0x0" + }, + { + "bits": "17", + "name": "field3", + "desc": "", + "swaccess": "ro", + "resval": "0x0" + }, + { + "bits": "18", + "name": "field4", + "desc": "", + "swaccess": "ro", + "resval": "0x0" + }, + { + "bits": "19", + "name": "field5", + "desc": "", + "swaccess": "ro", + "resval": "0x0" + }, + { + "bits": "20", + "name": "field6", + "desc": "", + "swaccess": "ro", + "resval": "0x0" + }, + { + "bits": "21", + "name": "field7", + "desc": "", + "swaccess": "ro", + "resval": "0x0" + }, + { + "bits": "22", + "name": "field8", + "desc": "", + "swaccess": "ro", + "resval": "0x0" + } + ] + }, + { + "name": "CSR4", + "desc": "", + "swaccess": "rw", + "hwaccess": "hro", + "hwext": "false", + "hwqe": "false", + "fields": [ + { + "bits": "9:0", + "name": "field0", + "desc": "", + "resval": "0x0" + }, + { + "bits": "12", + "name": "field1", + "desc": "", + "resval": "0x0" + }, + { + "bits": "13", + "name": "field2", + "desc": "", + "resval": "0x0" + }, + { + "bits": "14", + "name": "field3", + "desc": "", + "resval": "0x0" + } + ] + }, + { + "name": "CSR5", + "desc": "", + "swaccess": "rw", + "hwaccess": "hrw", + "hwext": "false", + "hwqe": "false", + "fields": [ + { + "bits": "5:0", + "name": "field0", + "desc": "", + "swaccess": "rw", + "resval": "0x0" + }, + { + "bits": "7:6", + "name": "field1", + "desc": "", + "swaccess": "rw", + "resval": "0x0" + }, + { + "bits": "8", + "name": "field2", + "desc": "", + "swaccess": "ro", + "resval": "0x0" + }, + { + "bits": "11:9", + "name": "field3", + "desc": "", + "swaccess": "ro", + "resval": "0x0" + }, + { + "bits": "12", + "name": "field4", + "desc": "", + "swaccess": "ro", + "resval": "0x0" + }, + { + "bits": "13", + "name": "field5", + "desc": "", + "swaccess": "ro", + "resval": "0x0" + }, + { + "bits": "31:16", + "name": "field6", + "desc": "", + "swaccess": "rw", + "resval": "0x0" + } + ] + }, + { + "name": "CSR6", + "desc": "", + "swaccess": "rw", + "hwaccess": "hro", + "hwext": "false", + "hwqe": "false", + "fields": [ + { + "bits": "9:0", + "name": "field0", + "desc": "", + "resval": "0x0" + }, + { + "bits": "11", + "name": "field1", + "desc": "", + "swaccess": "rw", + "resval": "0x0" + }, + { + "bits": "12", + "name": "field2", + "desc": "", + "swaccess": "rw", + "resval": "0x0" + }, + { + "bits": "31:16", + "name": "field3", + "desc": "", + "resval": "0x0" + } + ] + }, + { + "name": "CSR7", + "desc": "", + "swaccess": "ro", + "hwaccess": "hrw", + "hwext": "false", + "hwqe": "false", + "fields": [ + { + "bits": "5:0", + "name": "field0", + "desc": "", + "swaccess": "ro", + "resval": "0x0" + }, + { + "bits": "10:8", + "name": "field1", + "desc": "", + "swaccess": "ro", + "resval": "0x0" + }, + { + "bits": "14", + "name": "field2", + "desc": "", + "swaccess": "ro", + "resval": "0x0" + }, + { + "bits": "15", + "name": "field3", + "desc": "", + "swaccess": "ro", + "resval": "0x0" + } + ] + } + ] + } +} diff --git a/src/fuse_ctrl/data/otp_ctrl.rdl b/src/fuse_ctrl/data/otp_ctrl.rdl new file mode 100644 index 0000000..686037d --- /dev/null +++ b/src/fuse_ctrl/data/otp_ctrl.rdl @@ -0,0 +1,727 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// + +//////////////////////////////////////////////////////////////// +// Fuse Contrller Registers + +//parameter int OtpByteAddrWidth = 12; + +addrmap caliptra_otp_ctrl { + reg { + field { + sw = rw; + onwrite = woclr; + desc = "A direct access command or digest calculation operation has completed."; + } OTP_OPERATION_DONE[0:0]; + field { + sw = rw; + onwrite = woclr; + desc = "An error has occurred in the OTP contrller. Check the !!ERR_CODE register to get more information."; + } OTP_error[1:1]; + } INTERRUPT_STATE @ 0x0; + + reg { + field { + sw = rw; + onwrite = woclr; + desc = "Enable interrupt when otp_operation_done is set."; + } OTP_OPERATION_DONE[0:0]; + field { + sw = rw; + onwrite = woclr; + desc = "Enable interrupt when otp_error is set."; + } OTP_error[1:1]; + } INTERRUPT_ENABLE @ 0x4; + + reg { + field { + sw = w; + desc = "Write 1 to force otp_operation_done to 1."; + } OTP_OPERATION_DONE[0:0]; + field { + sw = w; + desc = "Write 1 to force otp_error to 1."; + } OTP_error[1:1]; + } INTERRUPT_TEST @ 0x8; + + reg { + field { + sw = w; + desc = "Write 1 to trigger one alert event of this kind."; + } FATAL_MACr_error[0:0]; + field { + sw = w; + desc = "Write 1 to trigger one alert event of this kind."; + } FATAL_CHECK_error[1:1]; + field { + sw = w; + desc = "Write 1 to trigger one alert event of this kind."; + } FATAL_BUS_INTEG_error[2:2]; + field { + sw = w; + desc = "Write 1 to trigger one alert event of this kind."; + } FATAL_PRIM_OTP_ALERT[3:3]; + field { + sw = w; + desc = "Write 1 to trigger one alert event of this kind."; + } RECOV_PRIM_OTP_ALERT[4:4]; + } ALERT_TEST @ 0xC; + + reg { + field { + sw = r; + desc = "Set to 1 if an error occurred in this partition.\nIf set to 1, SW should check the !!ERR_CODE register at the corresponding index."; + } VENDOR_TEST_error[0:0]; + field { + sw = r; + desc = "Set to 1 if an error occurred in this partition.\nIf set to 1, SW should check the !!ERR_CODE register at the corresponding index."; + } NON_SECRET_FUSES_error[1:1]; + field { + sw = r; + desc = "Set to 1 if an error occurred in this partition.\nIf set to 1, SW should check the !!ERR_CODE register at the corresponding index."; + } SECRET0_error[2:2]; + field { + sw = r; + desc = "Set to 1 if an error occurred in this partition.\nIf set to 1, SW should check the !!ERR_CODE register at the corresponding index."; + } SECRET1_error[3:3]; + field { + sw = r; + desc = "Set to 1 if an error occurred in this partition.\nIf set to 1, SW should check the !!ERR_CODE register at the corresponding index."; + } SECRET2_error[4:4]; + field { + sw = r; + desc = "Set to 1 if an error occurred in this partition.\nIf set to 1, SW should check the !!ERR_CODE register at the corresponding index."; + } SECRET3_error[5:5]; + field { + sw = r; + desc = "Set to 1 if an error occurred in this partition.\nIf set to 1, SW should check the !!ERR_CODE register at the corresponding index."; + } LIFE_CYCLE_error[6:6]; + field { + sw = r; + desc = "Set to 1 if an error occurred in the DAI.\nIf set to 1, SW should check the !!ERR_CODE register at the corresponding index."; + } DAI_error[7:7]; + field { + sw = r; + desc = "Set to 1 if an error occurred in the LCI.\nIf set to 1, SW should check the !!ERR_CODE register at the corresponding index."; + } LCI_error[8:8]; + field { + sw = r; + desc = "Set to 1 if an integrity or consistency check times out.\nThis raises an fatal_check_error alert and is an unrecoverable error condition."; + } TIMEOUT_error[9:9]; + field { + sw = r; + desc = "Set to 1 if the LFSR timer FSM has reached an invalid state.\nThis raises an fatal_check_error alert and is an unrecoverable error condition."; + } LFSR_FSM_error[10:10]; + field { + sw = r; + desc = "Set to 1 if the scrambling datapath FSM has reached an invalid state.\nThis raises an fatal_check_error alert and is an unrecoverable error condition."; + } SCRAMBLING_FSM_error[11:11]; + field { + sw = r; + desc = "Set to 1 if the key derivation FSM has reached an invalid state.\nThis raises an fatal_check_error alert and is an unrecoverable error condition."; + } KEY_DERIV_FSM_error[12:12]; + field { + sw = r; + desc = "This bit is set to 1 if a fatal bus integrity fault is detected.\nThis error triggers a fatal_bus_integ_error alert."; + } BUS_INTEG_error[13:13]; + field { + sw = r; + desc = "Set to 1 if the DAI is idle and ready to accept commands."; + } DAIL_IDLE[14:14]; + field { + sw = r; + desc = "Set to 1 if an integrity or consistency check triggered by the LFSR timer or via !!CHECK_TRIGGER is pending."; + } CHECK_PENDING[15:15]; + } STATUS @ 0x10; + + regfile err_code_t { + + /* ----------------------------------- + * Default prperties for Register File + * --------------------------------- */ + + name = "error Code Register Block"; + desc = "Set of registers to implement error_code functionality + for Fuse Contrller."; + + default regwidth = 32; // reg property + default accesswidth = 32; // reg property + default sw = r; // field property + default hw = w; // field property + + /* ------------------------------------ + * Register definitions + * -----------------------------------*/ + reg err_code_reg_t { + desc = "This register holds information about error conditions that occurred in the agents + interacting with the OTP macr via the internal bus. The error codes should be checked + if the partitions, DAI or LCI flag an error in the !!STATUS register, or when an + !!INTR_STATE.otp_error has been triggered. Note that all errors trigger an otp_error + interrupt, and in addition some errors may trigger either an fatal_macr_error or an + fatal_check_error alert."; + + default sw = r; // field property + default hw = w; // field property + + field { desc = "No error condition has occurred.";} NO_error = 3'h0; + field { desc = "Returned if the OTP macr command was invalid or did not complete successfully + due to a macr malfunction. This error should never occur during normal operation and is not recoverable. + This error triggers an fatal_macr_error alert.";} MACr_error = 3'h1; + field { desc = "A correctable ECC error has occured during an OTP read operation.\nThe corresponding contrller automatically recovers frm this error when\nissuing a new command.";} MACr_ECC_CORR_error = 3'h2; + field { desc = "An uncorrectable ECC error has occurred during an OTP read operation.\nThis error should never occur during normal operation and is not recoverable.\nIf this error is present this may be a sign that the device is malfunctioning.\nThis error triggers an fatal_macr_error alert.";} MACr_ECC_UNCORR_error = 3'h3; + field { desc = "This error is returned if a prgramming operation attempted to clear a bit that has previously been prgrammed to 1.\nThe corresponding contrller automatically recovers frm this error when issuing a new command.\n\nNote however that the affected OTP word may be left in an inconsistent state if this error occurs.\nThis can cause several issues when the word is accessed again (either as part of a regular read operation, as part of the readout at boot, or as part of a backgrund check).\n\nIt is important that SW ensures that each word is only written once, since this can render the device useless.";} MACr_WRITE_BLANK_error = 3'h4; + field { desc = "This error indicates that a locked memory region has been accessed.\nThe corresponding contrller automatically recovers frm this error when issuing a new command.";} ACCESS_error = 3'h5; + field { desc = "An ECC, integrity or consistency mismatch has been detected in the buffer registers.\nThis error should never occur during normal operation and is not recoverable.\nThis error triggers an fatal_check_error alert.";} CHECK_FAIL_error = 3'h6; + field { desc = "The FSM of the corresponding contrller has reached an invalid state, or the FSM has\nbeen moved into a terminal error state due to an escalation action via lc_escalate_en_i.\nThis error should never occur during normal operation and is not recoverable.\nIf this error is present, this is a sign that the device has fallen victim to\nan invasive attack. This error triggers an fatal_check_error alert.";} FSM_STATE_error = 3'h7; + }; + + /* ----------- Registers -----------*/ + err_code_reg_t ERR_CODE_0 @0x0; // + err_code_reg_t ERR_CODE_1 @0x4; // + err_code_reg_t ERR_CODE_2 @0x8; // + err_code_reg_t ERR_CODE_3 @0xC; // + err_code_reg_t ERR_CODE_4 @0x10; // + err_code_reg_t ERR_CODE_5 @0x14; // + err_code_reg_t ERR_CODE_6 @0x18; // + err_code_reg_t ERR_CODE_7 @0x1C; // + err_code_reg_t ERR_CODE_8 @0x20; // + /* ---------------------------------*/ + }; + + err_code_t err_code_rf @ 0x14; + + reg { + desc = "Register write enable for all direct access interface registers."; + default sw = rw; + default onwrite = wzc; + default hw = rw; + //default hwext = true; + field { + desc = "This bit contrls whether the DAI registers can be written.\nWrite 0 to it in order to clear the bit.\n\nNote that the hardware also modulates this bit and sets it to 0 temporarily\nduring an OTP operation such that the corresponding address and data registers\ncannot be modified while an operation is pending. The !!DAI_IDLE status bit\nwill also be set to 0 in such a case."; + reset = 0x1; + } REGWEN [0:0]; + } DIRECT_ACCESS_REGWEN @ 0x38; + + reg { + desc = "Command register for direct accesses."; + default sw = w; + default onwrite = wzc; + default hw = r; + //hwext = true; + default reset = 0x0; + default swwe = DIRECT_ACCESS_REGWEN; + field { + desc = "Initiates a readout sequence that reads the location specified\nby !!DIRECT_ACCESS_ADDRESS. The command places the data read into\n!!DIRECT_ACCESS_RDATA_0 and !!DIRECT_ACCESS_RDATA_1 (for 64bit partitions)."; + } RD [0:0]; + field { + desc = "Initiates a prgramming sequence that writes the data in !!DIRECT_ACCESS_WDATA_0\nand !!DIRECT_ACCESS_WDATA_1 (for 64bit partitions) to the location specified by\n!!DIRECT_ACCESS_ADDRESS."; + } WR [1:1]; + field { + desc = "Initiates the digest calculation and locking sequence for the partition specified by\n!!DIRECT_ACCESS_ADDRESS."; + } DIGEST [2:2]; + } DIRECT_ACCESS_CMD @ 0x3C; + + reg { + desc = "Address register for direct accesses."; + default sw = rw; + default hw = r; + default reset = 0x0; + default swwe = DIRECT_ACCESS_REGWEN; + field { + desc = "This is the address for the OTP word to be read or written thrugh\nthe direct access interface. Note that the address is aligned to the access size\ninternally, hence bits 1:0 are ignored for 32bit accesses, and bits 2:0 are ignored\nfor 64bit accesses.\n\nFor the digest calculation command, set this register to the partition base offset."; + } ADDRESS [11:0]; + } DIRECT_ACCESS_ADDRESS @ 0x40; + + regfile dir_acc_wdata_t { + /* ----------------------------------- + * Default prperties for Register File + * --------------------------------- */ + + name = "Direct Access Wdata Register Block"; + desc = "Set of registers to implement wdata functionality + for Fuse Contrller."; + default reset = 0x0; + default swwe = DIRECT_ACCESS_REGWEN; + default regwidth = 32; // reg property + default accesswidth = 32; // reg property + default sw = r; // field property + default hw = w; // field property + //defalt hwext = true; + + /* ------------------------------------ + * Register definitions + * -----------------------------------*/ + reg dai_wdata_t { + desc = "Write data for direct accesses. + Hardware automatically determines the access granule (32bit or 64bit) based on which + partition is being written to."; + + default sw = r; // field prperty + default hw = w; // field prperty + + field { desc = "wdata.";} WDATA [31:0]; + }; + + /* ------------- Registers --------------*/ + dai_wdata_t DIRECT_ACCESS_WDATA_0 @ 0x0; // + dai_wdata_t DIRECT_ACCESS_WDATA_1 @ 0x4; // + /* --------------------------------------*/ + }; + + dir_acc_wdata_t dai_wdata_rf @ 0x44; + + regfile dir_acc_rdata_t { + /* ----------------------------------- + * Default prperties for Register File + * --------------------------------- */ + + name = "Direct Access Wdata Register Block"; + desc = "Set of registers to implement wdata functionality + for Fuse Contrller."; + default reset = 0x0; + + default regwidth = 32; // reg prperty + default accesswidth = 32; // reg prperty + default sw = r; // field prperty + default hw = w; // field prperty + //default hwext = true; + + /* ------------------------------------ + * Register definitions + * -----------------------------------*/ + reg dai_rdata_t { + desc = "Read data for direct accesses. + Hardware automatically determines the access granule (32bit or 64bit) based on which + partition is read from."; + + default sw = r; // field prperty + default hw = w; // field prperty + + field { desc = "rdata.";} RDATA [31:0]; + }; + + /* ------------- Registers --------------*/ + dai_rdata_t DIRECT_ACCESS_RDATA_0 @ 0x0; // + dai_rdata_t DIRECT_ACCESS_RDATA_1 @ 0x4; // + /* --------------------------------------*/ + }; + + dir_acc_rdata_t dai_rdata_rf @ 0x4C; + + reg { + desc = "Register write enable for !!CHECK_TRIGGER."; + default sw = rw; + default onwrite = wzc; + default hw = na; + field { + desc = "When cleared to 0, the !!CHECK_TRIGGER register cannot be written anymore. + Write 0 to clear this bit."; + reset = 0x1; + } REGWEN [0:0]; + } CHECK_TRIGGER_REGWEN @ 0x54; + + reg { + desc = "Command register for direct accesses."; + default sw = w; + default onwrite = woclr; + default hw = r; // Needs to read 0 + //hwext = true; + default reset = 0x0; + default swwe = CHECK_TRIGGER_REGWEN; + field { + desc = "Writing 1 to this bit triggers an integrity check. SW should monitor !!STATUS.CHECK_PENDING + and wait until the check has been completed. If there are any errors, those will be flagged + in the !!STATUS and !!ERR_CODE registers, and via the interrupts and alerts."; + } INTEGRITY[0:0]; + field { + desc = "Writing 1 to this bit triggers a consistency check. SW should monitor !!STATUS.CHECK_PENDING\nand wait until the check has been completed. If there are any errors, those will be flagged\nin the !!STATUS and !!ERR_CODE registers, and via interrupts and alerts."; + } CONSISTENCY[1:1]; + } CHECK_TRIGGER @ 0x58; + + reg { + desc = "Register write enable for !!INTEGRITY_CHECK_PERIOD and !!CONSISTENCY_CHECK_PERIOD."; + default sw = w; + default onwrite = wzc; + default hw = na; + field { + desc = "When cleared to 0, !!INTEGRITY_CHECK_PERIOD and !!CONSISTENCY_CHECK_PERIOD registers cannot be written anymore.\nWrite 0 to clear this bit."; + reset = 0x1; + } REGWEN [0:0]; + } CHECK_REGWEN @ 0x5C; + + reg { + desc = "Timeout value for the integrity and consistency checks."; + default sw = rw; + default hw = r; + default swwe = CHECK_REGWEN; + field { + desc = "Timeout value in cycles for the for the integrity and consistency checks. If an integrity or consistency + check does not complete within the timeout window, an error will be flagged in the !!STATUS register, + an otp_error interrupt will be raised, and an fatal_check_error alert will be sent out. The timeout should + be set to a large value to stay on the safe side. The maximum check time can be upper bounded by the + number of cycles it takes to readout, scramble and digest the entire OTP array. Since this amounts to + rughly 25k cycles, it is recommended to set this value to at least 100'000 cycles in order to stay on the + safe side. A value of zer disables the timeout mechanism (default)."; + reset = 0x0; + } TIMEOUT [31:0]; + } CHECK_TIMEOUT @ 0x60; + + reg { + desc = "This value specifies the maximum period that can be generated pseudo-randomly.\nOnly applies to the HW_CFG* and SECRET* partitions once they are locked."; + default sw = rw; + default hw = r; + default swwe = CHECK_REGWEN; + field { + desc = "The pseudo-random period is generated using a 40bit LFSR internally, and this register defines + the bit mask to be applied to the LFSR output in order to limit its range. The value of this + register is left shifted by 8bits and the lower bits are set to 8'hFF in order to form the 40bit mask. + A recommended value is 0x3_FFFF, corresponding to a maximum period of ~2.8s at 24MHz. + A value of zer disables the timer (default). Note that a one-off check can always be triggered via + !!CHECK_TRIGGER.INTEGRITY."; + reset = 0x0; + } PERIOD [31:0]; + } INTEGRITY_CHECK_PERIOD @ 0x64; + + reg { + desc = "This value specifies the maximum period that can be generated pseudo-randomly.\nThis applies to the LIFE_CYCLE partition and the HW_CFG* and SECRET* partitions once they are locked."; + default sw = rw; + default hw = r; + default swwe = CHECK_REGWEN; + field { + desc = "The pseudo-random period is generated using a 40bit LFSR internally, and this register defines\nthe bit mask to be applied to the LFSR output in order to limit its range. The value of this\nregister is left shifted by 8bits and the lower bits are set to 8'hFF in order to form the 40bit mask.\nA recommended value is 0x3FF_FFFF, corresponding to a maximum period of ~716s at 24MHz.\nA value of zer disables the timer (default). Note that a one-off check can always be triggered via\n!!CHECK_TRIGGER.CONSISTENCY."; + reset = 0x0; + } PERIOD [31:0]; + } CONSISTENCY_CHECK_PERIOD @ 0x68; + + reg { + desc = "Runtime read lock for the VENDOR_TEST partition."; + default sw = rw; + default onwrite = wzc; + default hw = r; + default swwe = DIRECT_ACCESS_REGWEN; + field { + desc = "When cleared to 0, read access to the VENDOR_TEST partition is locked.\nWrite 0 to clear this bit."; + reset = 0x1; + } READ_LOCK [0:0]; + } VENDOR_TEST_READ_LOCK @ 0x6C; + + reg { + desc = "Runtime read lock for the NON_SECRET_FUSES partition."; + default sw = rw; + default onwrite = wzc; + default hw = r; + default swwe = DIRECT_ACCESS_REGWEN; + field { + desc = "When cleared to 0, read access to the NON_SECRET_FUSES_READ_LOCK partition is locked.\nWrite 0 to clear this bit."; + reset = 0x1; + } READ_LOCK [0:0]; + } NON_SECRET_FUSES_READ_LOCK @ 0x70; + + regfile digest_t { + /* ----------------------------------- + * Default prperties for Register File + * --------------------------------- */ + name = "DIGEST"; + desc = "Digest register block"; + default reset = 0x0; + + default sw = r; + default hw = r; + //default hwext = true; + + /* ------------------------------------ + * Register definitions + * -----------------------------------*/ + reg digest_reg_t { + name = "DIGEST"; + desc = "Integrity digest for partition. + The integrity digest is 0 by default. Software must write this + digest value via the direct access interface in order to lock the partition. + After a reset, write access to the VENDOR_TEST partition is locked and\n the digest becomes visible in this CSR."; + + default sw = r; // field prperty + default hw = w; // field prperty + + field { desc = "Digest.";} DIGEST [31:0]; + }; + + /* ------------- Registers --------------*/ + digest_reg_t DIGEST_0 @ 0x0; // + digest_reg_t DIGEST_1 @ 0x4; // + /* --------------------------------------*/ + }; + + digest_t VENDOR_TEST_DIGEST @ 0x74; + digest_t NON_SECRET_FUSES_DIGEST @ 0x7C; + + regfile secret_digest_t { + /* ----------------------------------- + * Default prperties for Register File + * --------------------------------- */ + name = "SECRET_DIGEST"; + desc = "Secret digest register block"; + default reset = 0x0; + + default sw = r; + default hw = r; + //default hwext = true; + + /* ------------------------------------ + * Register definitions + * -----------------------------------*/ + reg secret_digest_reg_t { + name = "SECRET_DIGEST"; + desc = "Integrity digest for secret partition. + The integrity digest is 0 by default. The digest calculation can be triggered via the !!DIRECT_ACCESS_CMD. + After a reset, the digest then becomes visible in this CSR, and the corresponding partition becomes write-locked."; + + default sw = r; // field prperty + default hw = w; // field prperty + + field { desc = "Digest.";} DIGEST [31:0]; + }; + + /* ------------- Registers --------------*/ + secret_digest_reg_t DIGEST_0 @ 0x0; // + secret_digest_reg_t DIGEST_1 @ 0x4; // + /* --------------------------------------*/ + }; + + secret_digest_t SECRET0_DIGEST @ 0x84; + secret_digest_t SECRET1_DIGEST @ 0x8C; + secret_digest_t SECRET2_DIGEST @ 0x94; + secret_digest_t SECRET3_DIGEST @ 0x9C; + + reg { + field { + desc = ""; + sw = rw; + hw = r; + } field0[0:0] = 0x0; + field { + desc = ""; + sw = rw; + hw = r; + } field1[1:1] = 0x0; + field { + desc = ""; + sw = rw; + hw = r; + } field2[2:2] = 0x0; + field { + desc = ""; + sw = rw; + hw = r; + } field3[13:4] = 0x0; + field { + desc = ""; + sw = rw; + hw = r; + } field4[26:16] = 0x0; + } CSR0 @ 0xA4; + + reg { + field { + desc = ""; + sw = rw; + hw = r; + } field0[6:0] = 0x0; + field { + desc = ""; + sw = rw; + hw = r; + } field1[7:7] = 0x0; + field { + desc = ""; + sw = rw; + hw = r; + } field2[14:8] = 0x0; + field { + desc = ""; + sw = rw; + hw = r; + } field3[15:15] = 0x0; + field { + desc = ""; + sw = rw; + hw = r; + } field4[31:16] = 0x0; + } CSR1 @ 0xA8; + + reg { + field { + desc = ""; + sw = rw; + hw = r; + } field0[0:0] = 0x0; + } CSR2 @ 0xAC; + + reg { + field { + desc = ""; + sw = rw; + hw = rw; + } field0[2:0] = 0x0; + field { + desc = ""; + sw = rw; + onwrite = woclr; + hw = rw; + } field1[13:4] = 0x0; + field { + desc = ""; + sw = rw; + onwrite = woclr; + hw = rw; + } field2[16:16] = 0x0; + field { + desc = ""; + sw = r; + hw = rw; + } field3[17:17] = 0x0; + field { + desc = ""; + sw = r; + hw = rw; + } field4[18:18] = 0x0; + field { + desc = ""; + sw = r; + hw = rw; + } field5[19:19] = 0x0; + field { + desc = ""; + sw = r; + hw = rw; + } field6[20:20] = 0x0; + field { + desc = ""; + sw = r; + hw = rw; + } field7[21:21] = 0x0; + field { + desc = ""; + sw = r; + hw = rw; + } field8[22:22] = 0x0; + } CSR3 @ 0xB0; + + reg { + field { + desc = ""; + sw = rw; + hw = r; + } field0[9:0] = 0x0; + field { + desc = ""; + sw = rw; + hw = r; + } field1[12:12] = 0x0; + field { + desc = ""; + sw = rw; + hw = r; + } field2[13:13] = 0x0; + field { + desc = ""; + sw = rw; + hw = r; + } field3[14:14] = 0x0; + } CSR4 @ 0xB4; + + reg { + field { + desc = ""; + sw = rw; + hw = rw; + } field0[5:0] = 0x0; + field { + desc = ""; + sw = rw; + hw = rw; + } field1[7:6] = 0x0; + field { + desc = ""; + sw = r; + hw = rw; + } field2[8] = 0x0; + field { + desc = ""; + sw = r; + hw = rw; + } field3[11:9] = 0x0; + field { + desc = ""; + sw = r; + hw = rw; + } field4[12] = 0x0; + field { + desc = ""; + sw = r; + hw = rw; + } field5[13] = 0x0; + field { + desc = ""; + sw = rw; + hw = rw; + } field6[31:16] = 0x0; + } CSR5 @ 0xB8; + + reg { + field { + desc = ""; + sw = rw; + hw = r; + } field0[9:0] = 0x0; + field { + desc = ""; + sw = rw; + hw = rw; + } field1[11:11] = 0x0; + field { + desc = ""; + sw = rw; + hw = rw; + } field2[12:12] = 0x0; + field { + desc = ""; + sw = rw; + hw = rw; + } field3[31:16] = 0x0; + } CSR6 @ 0xBC; + + reg { + field { + desc = ""; + sw = r; + hw = rw; + } field0[5:0] = 0x0; + field { + desc = ""; + sw = r; + hw = rw; + } field1[10:8] = 0x0; + field { + desc = ""; + sw = r; + hw = rw; + } field2[14:14] = 0x0; + field { + desc = ""; + sw = r; + hw = rw; + } field3[15:15] = 0x0; + } CSR7 @ 0xC0; +}; \ No newline at end of file diff --git a/src/fuse_ctrl/data/otp_ctrl_base_vseq.sv.tpl b/src/fuse_ctrl/data/otp_ctrl_base_vseq.sv.tpl new file mode 100755 index 0000000..0be039d --- /dev/null +++ b/src/fuse_ctrl/data/otp_ctrl_base_vseq.sv.tpl @@ -0,0 +1,643 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +${gen_comment} +<% +from topgen.lib import Name + +unbuf_parts_with_digest = [part for part in otp_mmap.config["partitions"] if + part["variant"] == "Unbuffered" and + (part["sw_digest"] or part["hw_digest"])] +parts_with_digest = [part for part in otp_mmap.config["partitions"] if + (part["sw_digest"] or part["hw_digest"])] +read_locked_csr_parts = [part for part in otp_mmap.config["partitions"] if + part["read_lock"] == "CSR"] +write_locked_digest_parts = [part for part in otp_mmap.config["partitions"] if + part["write_lock"] == "Digest"] +secret_parts = [part for part in otp_mmap.config["partitions"] if + part["secret"]] +%>\ +class otp_ctrl_base_vseq extends cip_base_vseq #( + .RAL_T (otp_ctrl_core_reg_block), + .CFG_T (otp_ctrl_env_cfg), + .COV_T (otp_ctrl_env_cov), + .VIRTUAL_SEQUENCER_T (otp_ctrl_virtual_sequencer) + ); + `uvm_object_utils(otp_ctrl_base_vseq) + `uvm_object_new + + // various knobs to enable certain routines + bit do_otp_ctrl_init = 1'b1; + bit do_otp_pwr_init = 1'b1; + + // To only write unused OTP address, sequence will collect all the written addresses to an + // associative array to avoid `write_blank_addr_error`. + bit write_unused_addr = 1; + static bit used_dai_addrs[bit [OTP_ADDR_WIDTH - 1 : 0]]; + + rand bit [NumOtpCtrlIntr-1:0] en_intr; + + rand int apply_reset_during_pwr_init_cycles; + + bit is_valid_dai_op = 1; + + // According to spec, the period between digest calculation and reset should not issue any write. + bit [NumPart-2:0] digest_calculated; + + // For stress_all_with_rand reset sequence to issue reset during OTP operations. + bit do_digest_cal, do_otp_rd, do_otp_wr; + + // LC program request will use a separate variable to automatically set to non-blocking setting + // when LC error bit is set. + bit default_req_blocking = 1; + bit lc_prog_blocking = 1; + bit dai_wr_inprogress = 0; + uint32_t op_done_spinwait_timeout_ns = 20_000_000; + + // Collect current lc_state and lc_cnt. This is used to create next lc_state and lc_cnt without + // error. + lc_ctrl_state_pkg::lc_state_e lc_state; + lc_ctrl_state_pkg::lc_cnt_e lc_cnt; + + otp_ctrl_callback_vseq callback_vseq; + + constraint apply_reset_during_pwr_init_cycles_c { + apply_reset_during_pwr_init_cycles == 0; + } + + virtual task pre_start(); + `uvm_create_on(callback_vseq, p_sequencer); + super.pre_start(); + endtask + + virtual task dut_init(string reset_kind = "HARD"); + // OTP has dut and edn reset. If assign OTP values after `super.dut_init()`, and if dut reset + // deasserts earlier than edn reset, some OTP outputs might remain X or Z when dut clock is + // running. + otp_ctrl_vif_init(); + super.dut_init(reset_kind); + callback_vseq.dut_init_callback(); + + cfg.backdoor_clear_mem = 0; + // reset power init pin and lc pins + if (do_otp_ctrl_init && do_apply_reset) otp_ctrl_init(); + cfg.clk_rst_vif.wait_clks($urandom_range(0, 10)); + if (do_otp_pwr_init && do_apply_reset) otp_pwr_init(); + callback_vseq.post_otp_pwr_init(); + endtask + + // Cfg errors are cleared after reset + virtual task apply_reset(string kind = "HARD"); + super.apply_reset(kind); + cfg.otp_ctrl_vif.release_part_access_mubi(); + clear_seq_flags(); + endtask + + virtual function void clear_seq_flags(); + do_digest_cal = 0; + do_otp_rd = 0; + do_otp_wr = 0; + endfunction + + virtual task otp_ctrl_vif_init(); + cfg.otp_ctrl_vif.drive_lc_creator_seed_sw_rw_en(lc_ctrl_pkg::On); + cfg.otp_ctrl_vif.drive_lc_owner_seed_sw_rw_en(lc_ctrl_pkg::On); + cfg.otp_ctrl_vif.drive_lc_seed_hw_rd_en(get_rand_lc_tx_val()); + cfg.otp_ctrl_vif.drive_lc_dft_en(get_rand_lc_tx_val(.t_weight(0))); + cfg.otp_ctrl_vif.drive_lc_escalate_en(lc_ctrl_pkg::Off); + cfg.otp_ctrl_vif.drive_pwr_otp_init(0); + cfg.otp_ctrl_vif.drive_ext_voltage_h_io(1'bz); + + // Unused signals in open sourced OTP memory + `DV_CHECK_RANDOMIZE_FATAL(cfg.dut_cfg) + cfg.otp_ctrl_vif.otp_ast_pwr_seq_h_i = cfg.dut_cfg.otp_ast_pwr_seq_h; + cfg.otp_ctrl_vif.scan_en_i = cfg.dut_cfg.scan_en; + cfg.otp_ctrl_vif.scan_rst_ni = cfg.dut_cfg.scan_rst_n; + cfg.otp_ctrl_vif.scanmode_i = cfg.dut_cfg.scanmode; + cfg.otp_ctrl_vif.otp_vendor_test_ctrl_i = cfg.dut_cfg.otp_vendor_test_ctrl; + endtask + + // drive otp_pwr req pin to initialize OTP, and wait until init is done + virtual task otp_pwr_init(); + cfg.otp_ctrl_vif.drive_pwr_otp_init(1); + if (apply_reset_during_pwr_init_cycles > 0) begin + `DV_SPINWAIT_EXIT( + cfg.clk_rst_vif.wait_clks(apply_reset_during_pwr_init_cycles);, + wait (cfg.otp_ctrl_vif.pwr_otp_done_o == 1);) + if (cfg.otp_ctrl_vif.pwr_otp_done_o == 0) begin + cfg.otp_ctrl_vif.drive_pwr_otp_init(0); + apply_reset(); + cfg.otp_ctrl_vif.drive_pwr_otp_init(1); + end + end + wait (cfg.otp_ctrl_vif.pwr_otp_done_o == 1); + cfg.otp_ctrl_vif.drive_pwr_otp_init(0); + digest_calculated = 0; + endtask + + // setup basic otp_ctrl features + virtual task otp_ctrl_init(); + // reset memory to avoid readout X + clear_otp_memory(); + lc_state = lc_state_e'(0); + lc_cnt = lc_cnt_e'(0); + endtask + + virtual function void clear_otp_memory(); + cfg.mem_bkdr_util_h.clear_mem(); + cfg.backdoor_clear_mem = 1; + used_dai_addrs.delete(); + endfunction + + // Overide this task for otp_ctrl_common_vseq and otp_ctrl_stress_all_with_rand_reset_vseq + // because some registers won't set to default value until otp_init is done. + virtual task read_and_check_all_csrs_after_reset(); + cfg.otp_ctrl_vif.drive_lc_escalate_en(lc_ctrl_pkg::Off); + otp_pwr_init(); + super.read_and_check_all_csrs_after_reset(); + endtask + + // this task triggers an OTP write sequence via the DAI interface + virtual task dai_wr(bit [TL_DW-1:0] addr, + bit [TL_DW-1:0] wdata0, + bit [TL_DW-1:0] wdata1 = 0); + bit [TL_DW-1:0] val; + dai_wr_inprogress = 1; + if (write_unused_addr) begin + if (used_dai_addrs.exists(addr[OTP_ADDR_WIDTH - 1 : 0])) begin + `uvm_info(`gfn, $sformatf("addr %0h is already written!", addr), UVM_MEDIUM) + dai_wr_inprogress = 0; + return; + end else begin + used_dai_addrs[addr] = 1; + end + end + addr = randomize_dai_addr(addr); + `uvm_info(`gfn, $sformatf("dai write addr %0h, data %0h", addr, wdata0), UVM_HIGH) + csr_wr(ral.direct_access_address, addr); + csr_wr(ral.direct_access_wdata[0], wdata0); + if (is_secret(addr) || is_sw_digest(addr)) csr_wr(ral.direct_access_wdata[1], wdata1); + + do_otp_wr = 1; + csr_wr(ral.direct_access_cmd, int'(otp_ctrl_pkg::DaiWrite)); + `uvm_info(`gfn, $sformatf("DAI write, address %0h, data0 %0h data1 %0h, is_secret = %0b", + addr, wdata0, wdata1, is_secret(addr)), UVM_DEBUG) + + // Direct_access_regwen and dai_idle are checked only when following conditions are met: + // - the dai operation is valid, otherwise it is hard to predict which cycle the error is + // detected + // - zero delays in TLUL interface, otherwise dai operation might be finished before reading + // these two CSRs + if (cfg.zero_delays && is_valid_dai_op && + cfg.otp_ctrl_vif.lc_escalate_en_i == lc_ctrl_pkg::Off) begin + csr_rd_check(ral.status.dai_idle, .compare_value(0), .backdoor(1)); + if ($urandom_range(0, 1)) csr_rd(.ptr(ral.direct_access_regwen), .value(val)); + end + wait_dai_op_done(); + rd_and_clear_intrs(); + dai_wr_inprogress = 0; + endtask : dai_wr + + // This task triggers an OTP readout sequence via the DAI interface + virtual task dai_rd(input bit [TL_DW-1:0] addr, + output bit [TL_DW-1:0] rdata0, + output bit [TL_DW-1:0] rdata1); + bit [TL_DW-1:0] val; + addr = randomize_dai_addr(addr); + + csr_wr(ral.direct_access_address, addr); + do_otp_rd = 1; + csr_wr(ral.direct_access_cmd, int'(otp_ctrl_pkg::DaiRead)); + + if (cfg.zero_delays && is_valid_dai_op && + cfg.otp_ctrl_vif.lc_escalate_en_i == lc_ctrl_pkg::Off) begin + csr_rd_check(ral.status.dai_idle, .compare_value(0), .backdoor(1)); + if ($urandom_range(0, 1)) csr_rd(.ptr(ral.direct_access_regwen), .value(val)); + end + + wait_dai_op_done(); + csr_rd(ral.direct_access_rdata[0], rdata0); + if (is_secret(addr) || is_digest(addr)) csr_rd(ral.direct_access_rdata[1], rdata1); + rd_and_clear_intrs(); + endtask : dai_rd + + virtual task dai_rd_check(bit [TL_DW-1:0] addr, + bit [TL_DW-1:0] exp_data0, + bit [TL_DW-1:0] exp_data1 = 0); + bit [TL_DW-1:0] rdata0, rdata1; + dai_rd(addr, rdata0, rdata1); + if (!cfg.under_reset) begin + `DV_CHECK_EQ(rdata0, exp_data0, $sformatf("dai addr %0h rdata0 readout mismatch", addr)) + if (is_secret(addr) || is_digest(addr)) begin + `DV_CHECK_EQ(rdata1, exp_data1, $sformatf("dai addr %0h rdata1 readout mismatch", addr)) + end + end + endtask: dai_rd_check + + // this task exercises an OTP digest calculation via the DAI interface + virtual task cal_digest(int part_idx); + bit [TL_DW-1:0] val; + csr_wr(ral.direct_access_address, PART_BASE_ADDRS[part_idx]); + csr_wr(ral.direct_access_cmd, otp_ctrl_pkg::DaiDigest); + + if (cfg.zero_delays && is_valid_dai_op && + cfg.otp_ctrl_vif.lc_escalate_en_i == lc_ctrl_pkg::Off) begin + csr_rd_check(ral.status.dai_idle, .compare_value(0), .backdoor(1)); + if ($urandom_range(0, 1)) csr_rd(.ptr(ral.direct_access_regwen), .value(val)); + end + do_digest_cal = 1; + wait_dai_op_done(); + digest_calculated[part_idx] = 1; + rd_and_clear_intrs(); + endtask + + // this task provisions all HW partitions + // SW partitions could not be provisioned via DAI interface + // LC partitions cannot be locked + virtual task cal_hw_digests(bit [NumPart-1:0] trigger_digest = $urandom()); + foreach (PartInfo[i]) begin + if (PartInfo[i].hw_digest && trigger_digest[i]) begin + cal_digest(i); + end + end + endtask + + // SW digest data are calculated in sw and won't be checked in OTP. + // Here to simplify testbench, write random data to sw digest. + virtual task write_sw_digests(bit [NumPartUnbuf-1:0] wr_digest = $urandom()); + bit [TL_DW*2-1:0] wdata; + % for part in unbuf_parts_with_digest: +<% + part_name = Name.from_snake_case(part["name"]) + part_name_camel = part_name.as_camel_case() +%>\ + if (wr_digest[${part_name_camel}Idx]) begin + `DV_CHECK_STD_RANDOMIZE_FATAL(wdata); + dai_wr(${part_name_camel}DigestOffset, wdata[TL_DW-1:0], wdata[TL_DW*2-1:TL_DW]); + end +% endfor + endtask + + virtual task write_sw_rd_locks(bit [NumPartUnbuf-1:0] do_rd_lock= $urandom()); +% for part in read_locked_csr_parts: +<% + part_name = Name.from_snake_case(part["name"]) + part_name_camel = part_name.as_camel_case() +%>\ + if (do_rd_lock[${part_name_camel}Idx]) csr_wr(ral.${part["name"].lower()}_read_lock, 0); +% endfor + endtask + + // The digest CSR values are verified in otp_ctrl_scoreboard + virtual task rd_digests(); + bit [TL_DW-1:0] val; +% for part in parts_with_digest: + csr_rd(.ptr(ral.${part["name"].lower()}_digest[0]), .value(val)); + csr_rd(.ptr(ral.${part["name"].lower()}_digest[1]), .value(val)); +% endfor + endtask + + // If the partition is read/write locked, there is 20% chance we will force the internal mubi + // access signal to the values other than mubi::true or mubi::false. + virtual task force_mubi_part_access(); + // Stress_all_with_rand_reset seq will issue reset and wait until reset is done then kill the + // parallel sequence. This gating logic avoid injecting error during reset active. + if (cfg.otp_ctrl_vif.alert_reqs == 0 && !cfg.under_reset) begin + otp_part_access_lock_t forced_mubi_part_access[NumPart-1]; + + // Digest write locks +% for part in write_locked_digest_parts: +<% + part_name = Name.from_snake_case(part["name"]) + part_name_camel = part_name.as_camel_case() +%>\ + if ((`gmv(ral.${part["name"].lower()}_digest[0]) || + `gmv(ral.${part["name"].lower()}_digest[1])) && + !$urandom_range(0, 4)) begin + forced_mubi_part_access[${part_name_camel}Idx].write_lock = 1; + end +% endfor + + // CSR read locks +% for part in read_locked_csr_parts: +<% + part_name = Name.from_snake_case(part["name"]) + part_name_camel = part_name.as_camel_case() +%>\ + if ((`gmv(ral.${part["name"].lower()}_read_lock) == 0) && !$urandom_range(0, 4)) begin + forced_mubi_part_access[${part_name_camel}Idx].read_lock = 1; + end +% endfor + + + // Digest read locks +% for part in secret_parts: +<% + part_name = Name.from_snake_case(part["name"]) + part_name_camel = part_name.as_camel_case() +%>\ + if ((`gmv(ral.${part["name"].lower()}_digest[0]) || + `gmv(ral.${part["name"].lower()}_digest[1])) && + !$urandom_range(0, 4)) begin + forced_mubi_part_access[${part_name_camel}Idx].read_lock = 1; + end +% endfor + + foreach (forced_mubi_part_access[i]) begin + `uvm_info(`gfn, $sformatf("partition %0d inject mubi value: read=%0b, write=%0b", i, + forced_mubi_part_access[i].read_lock, forced_mubi_part_access[i].write_lock), UVM_HIGH) + end + + cfg.otp_ctrl_vif.force_part_access_mubi(forced_mubi_part_access); + end + endtask + + // This function backdoor inject error according to ecc_err. + // For example, if err_mask is set to 'b01, bit 1 in OTP macro will be flipped. + // This function will output original backdoor read data for the given address. + virtual function bit [TL_DW-1:0] backdoor_inject_ecc_err(bit [TL_DW-1:0] addr, + otp_ecc_err_e ecc_err); + bit [TL_DW-1:0] val; + addr = {addr[TL_DW-1:2], 2'b00}; + val = cfg.mem_bkdr_util_h.read32(addr); + if (ecc_err == OtpNoEccErr || addr >= (LifeCycleOffset + LifeCycleSize)) return val; + + // Backdoor read and write back with error bits + cfg.mem_bkdr_util_h.inject_errors(addr, (ecc_err == OtpEccUncorrErr) ? 2 : 1); + `uvm_info(`gfn, $sformatf("original val %0h, addr %0h, err_type %0s", + val, addr, ecc_err.name), UVM_HIGH) + return val; + endfunction + + virtual task trigger_checks(bit [1:0] val, + bit wait_done = 1, + otp_ecc_err_e ecc_err = OtpNoEccErr); + bit [TL_DW-1:0] backdoor_rd_val, addr; + + // If ECC and check error happens in the same consistency check, the scb cannot predict which + // error will happen first, so it cannot correctly predict the error status and alert + // triggered. + // So the sequence only allows one error at a time. + if (get_field_val(ral.check_trigger.consistency, val) && + `gmv(ral.check_timeout) > 0 && `gmv(ral.check_timeout) <= CHK_TIMEOUT_CYC) begin + ecc_err = OtpNoEccErr; + end + + // Backdoor write ECC errors + if (ecc_err != OtpNoEccErr) begin + int part_idx = $urandom_range(HwCfg0Idx, LifeCycleIdx); + + // Only HW cfgs check digest correctness + if (part_idx != LifeCycleIdx) begin + addr = $urandom_range(0, 1) ? PART_OTP_DIGEST_ADDRS[part_idx] << 2 : + (PART_OTP_DIGEST_ADDRS[part_idx] + 1) << 2; + end else begin + addr = $urandom_range(LifeCycleOffset, LifeCycleOffset + LifeCycleSize - 1); + addr = {addr[TL_DW-1:2], 2'b00}; + end + backdoor_rd_val = backdoor_inject_ecc_err(addr, ecc_err); + cfg.ecc_chk_err[part_idx] = ecc_err; + end + + csr_wr(ral.check_trigger, val); + if (wait_done && val) csr_spinwait(ral.status.check_pending, 0); + + if (ecc_err != OtpNoEccErr) begin + cfg.mem_bkdr_util_h.write32(addr, backdoor_rd_val); + cfg.ecc_chk_err = '{default: OtpNoEccErr}; + end + endtask + + // For a DAI interface operation to finish, either way until status dai_idle is set, or check + // err_code and see if fatal error happened. In any case, break out of this wait if there + // is a need to stop transaction generators, since a spinwait will otherwise just stop + // when it times-out. + virtual task wait_dai_op_done(); + if (cfg.stop_transaction_generators()) return; + fork begin + fork + begin + csr_spinwait(.ptr(ral.status.dai_idle), + .exp_data(1), + .timeout_ns(op_done_spinwait_timeout_ns), + .spinwait_delay_ns($urandom_range(0, 5))); + end + begin + forever begin + bit [TL_DW-1:0] err_val; + cfg.clk_rst_vif.wait_clks(1); + csr_rd(.ptr(ral.err_code[DaiIdx].err_code), .value(err_val), .backdoor(1)); + // Break if error will cause fatal alerts + if (err_val inside {OTP_TERMINAL_ERRS}) break; + end + end + begin + forever begin + cfg.clk_rst_vif.wait_clks(1); + if (cfg.stop_transaction_generators()) break; + end + end + join_any + wait_no_outstanding_access(); + disable fork; + end join + endtask + + virtual task rd_and_clear_intrs(); + bit [TL_DW-1:0] val; + if (cfg.otp_ctrl_vif.lc_prog_no_sta_check == 0) begin + csr_rd(ral.intr_state, val); + // In case lc_program request is issued after intr_state read + if (cfg.otp_ctrl_vif.lc_prog_no_sta_check == 0) csr_wr(ral.intr_state, val); + end + endtask + + // first two or three LSB bits of DAI address can be randomized based on if it is secret + virtual function bit [TL_AW-1:0] randomize_dai_addr(bit [TL_AW-1:0] dai_addr); + if (is_secret(dai_addr)) begin + bit [2:0] rand_addr = $urandom(); + randomize_dai_addr = {dai_addr[TL_DW-1:3], rand_addr}; + end else begin + bit [1:0] rand_addr = $urandom(); + randomize_dai_addr = {dai_addr[TL_DW-1:2], rand_addr}; + end + endfunction + + // The following interface requests are separated to blocking and non-blocking accesses. + // The non-blocking access is mainly used when lc_escalate_en is On, which acts like a reset and + // move all design state machines to ErrorSt. Thus pending request will never get a response + // until reset. + virtual task req_sram_key(int index, bit blocking = default_req_blocking); + // Return if the request is already high, this is mainly due to lc_escalate_en On. + if (cfg.m_sram_pull_agent_cfg[index].vif.req === 1'b1) return; + + if (blocking) begin + req_sram_key_sub(index); + end else begin + fork + begin + req_sram_key_sub(index); + end + join_none; + // Add #0 to ensure that this thread starts executing before any subsequent call + #0; + end + endtask + + virtual task req_sram_key_sub(int index); + push_pull_host_seq#(.DeviceDataWidth(SRAM_DATA_SIZE)) sram_pull_seq; + wait(cfg.under_reset == 0); + `uvm_create_on(sram_pull_seq, p_sequencer.sram_pull_sequencer_h[index]); + `DV_CHECK_RANDOMIZE_FATAL(sram_pull_seq) + `uvm_send(sram_pull_seq) + endtask + + virtual task req_all_sram_keys(bit blocking = default_req_blocking); + for (int i = 0; i < NumSramKeyReqSlots; i++) req_sram_key(i, blocking); + endtask + + virtual task req_otbn_key(bit blocking = default_req_blocking); + if (cfg.m_otbn_pull_agent_cfg.vif.req === 1'b1) return; + + if (blocking) begin + req_otbn_key_sub(); + end else begin + fork + begin + req_otbn_key_sub(); + end + join_none; + // Add #0 to ensure that this thread starts executing before any subsequent call + #0; + end + endtask + + virtual task req_otbn_key_sub(); + push_pull_host_seq#(.DeviceDataWidth(OTBN_DATA_SIZE)) otbn_pull_seq; + wait(cfg.under_reset == 0); + `uvm_create_on(otbn_pull_seq, p_sequencer.otbn_pull_sequencer_h); + `DV_CHECK_RANDOMIZE_FATAL(otbn_pull_seq) + `uvm_send(otbn_pull_seq) + endtask + + virtual task req_flash_addr_key(bit blocking = default_req_blocking); + if (cfg.m_flash_addr_pull_agent_cfg.vif.req === 1'b1) return; + + if (blocking) begin + req_flash_addr_key_sub(); + end else begin + fork + begin + req_flash_addr_key_sub(); + end + join_none; + // Add #0 to ensure that this thread starts executing before any subsequent call + #0; + end + endtask + + virtual task req_flash_addr_key_sub(); + push_pull_host_seq#(.DeviceDataWidth(FLASH_DATA_SIZE)) flash_addr_pull_seq; + wait(cfg.under_reset == 0); + `uvm_create_on(flash_addr_pull_seq, p_sequencer.flash_addr_pull_sequencer_h); + `DV_CHECK_RANDOMIZE_FATAL(flash_addr_pull_seq) + `uvm_send(flash_addr_pull_seq) + endtask + + virtual task req_flash_data_key(bit blocking = default_req_blocking); + if (cfg.m_flash_data_pull_agent_cfg.vif.req === 1'b1) return; + + if (blocking) begin + req_flash_data_key_sub(); + end else begin + fork + begin + req_flash_data_key_sub(); + end + join_none; + // Add #0 to ensure that this thread starts executing before any subsequent call + #0; + end + endtask + + virtual task req_flash_data_key_sub(); + push_pull_host_seq#(.DeviceDataWidth(FLASH_DATA_SIZE)) flash_data_pull_seq; + wait(cfg.under_reset == 0); + `uvm_create_on(flash_data_pull_seq, p_sequencer.flash_data_pull_sequencer_h); + `DV_CHECK_RANDOMIZE_FATAL(flash_data_pull_seq) + `uvm_send(flash_data_pull_seq) + endtask + + virtual task req_lc_transition(bit check_intr = 0, + bit blocking = default_req_blocking, + bit wr_blank_err = !write_unused_addr); + if (cfg.m_lc_prog_pull_agent_cfg.vif.req === 1'b1) return; + + if (blocking) begin + req_lc_transition_sub(check_intr, wr_blank_err); + end else begin + fork + begin + req_lc_transition_sub(check_intr, wr_blank_err); + end + join_none; + // Add #0 to ensure that this thread starts executing before any subsequent call + #0; + end + endtask + + virtual task req_lc_transition_sub(bit check_intr = 0, bit wr_blank_err = !write_unused_addr); + lc_ctrl_state_pkg::lc_cnt_e next_lc_cnt; + lc_ctrl_state_pkg::dec_lc_state_e next_lc_state, lc_state_dec; + bit [TL_DW-1:0] intr_val; + push_pull_host_seq#(.HostDataWidth(LC_PROG_DATA_SIZE), .DeviceDataWidth(1)) + lc_prog_pull_seq; + wait(cfg.under_reset == 0); + `uvm_create_on(lc_prog_pull_seq, p_sequencer.lc_prog_pull_sequencer_h); + + if (!wr_blank_err) begin + // Find valid next state and next cnt using lc_ctrl_dv_utils_pkg. + // If terminal state or max LcCnt reaches, will not program any new data. + if ((lc_state != LcStScrap) && (lc_cnt != LcCnt24)) begin + lc_state_dec = lc_ctrl_dv_utils_pkg::dec_lc_state(lc_state); + `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(next_lc_state, + next_lc_state inside {VALID_NEXT_STATES[lc_state_dec]};) + `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(next_lc_cnt, next_lc_cnt > lc_cnt;) + lc_state = lc_ctrl_dv_utils_pkg::encode_lc_state(next_lc_state); + lc_cnt = next_lc_cnt; + end + cfg.m_lc_prog_pull_agent_cfg.add_h_user_data({lc_cnt, lc_state}); + end + + `DV_CHECK_RANDOMIZE_FATAL(lc_prog_pull_seq) + `uvm_send(lc_prog_pull_seq) + + if (check_intr) rd_and_clear_intrs(); + endtask + + // This test access OTP_CTRL's test_access memory. The open-sourced code only test if the access + // is valid. Please override this task in proprietary OTP. + virtual task otp_test_access(); + if (`PRIM_DEFAULT_IMPL == prim_pkg::ImplGeneric) begin + repeat (10) begin + bit [TL_DW-1:0] data; + bit test_access_en; + bit [TL_AW-1:0] rand_addr = $urandom_range(0, NUM_PRIM_REG - 1) * 4; + bit [TL_AW-1:0] tlul_addr = + cfg.ral_models["otp_ctrl_prim_reg_block"].get_addr_from_offset(rand_addr); + if (cfg.stop_transaction_generators()) break; + rand_drive_dft_en(); + `DV_CHECK_STD_RANDOMIZE_FATAL(data) + test_access_en = cfg.otp_ctrl_vif.lc_dft_en_i == lc_ctrl_pkg::On; + tl_access(.addr(tlul_addr), .write(1), .data(data), .exp_err_rsp(~test_access_en), + .tl_sequencer_h(p_sequencer.tl_sequencer_hs["otp_ctrl_prim_reg_block"])); + tl_access(.addr(tlul_addr), .write(0), .data(data), .exp_err_rsp(~test_access_en), + .tl_sequencer_h(p_sequencer.tl_sequencer_hs["otp_ctrl_prim_reg_block"])); + end + end + endtask + + // Empty task, only drive it under `otp_ctrl_test_access_vseq` + virtual task rand_drive_dft_en(); + endtask +endclass : otp_ctrl_base_vseq diff --git a/src/fuse_ctrl/data/otp_ctrl_cov_bind.sv.tpl b/src/fuse_ctrl/data/otp_ctrl_cov_bind.sv.tpl new file mode 100755 index 0000000..fa61630 --- /dev/null +++ b/src/fuse_ctrl/data/otp_ctrl_cov_bind.sv.tpl @@ -0,0 +1,84 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Binds OTP_CTRL functional coverage interaface to the top level OTP_CTRL module. +// +${gen_comment} +<% +from topgen.lib import Name + +# The unsavory ${"\\"} tokens are used to escape the macros newline handling. +%>\ +`define PART_MUBI_COV(__part_name, __index) ${"\\"} + bind otp_ctrl cip_mubi_cov_if #(.Width(8)) ``__part_name``_read_lock_mubi_cov_if ( ${"\\"} + .rst_ni (rst_ni), ${"\\"} + .mubi (part_access[``__index``].read_lock) ${"\\"} + ); ${"\\"} + bind otp_ctrl cip_mubi_cov_if #(.Width(8)) ``__part_name``_write_lock_mubi_cov_if ( ${"\\"} + .rst_ni (rst_ni), ${"\\"} + .mubi (part_access[``__index``].write_lock) ${"\\"} + ); + +`define DAI_MUBI_COV(__part_name, __index) ${"\\"} + bind otp_ctrl cip_mubi_cov_if #(.Width(8)) dai_``__part_name``_read_lock_mubi_cov_if ( ${"\\"} + .rst_ni (rst_ni), ${"\\"} + .mubi (part_access_dai[``__index``].read_lock) ${"\\"} + ); ${"\\"} + bind otp_ctrl cip_mubi_cov_if #(.Width(8)) dai_``__part_name``_write_lock_mubi_cov_if ( ${"\\"} + .rst_ni (rst_ni), ${"\\"} + .mubi (part_access_dai[``__index``].write_lock) ${"\\"} + ); + +module otp_ctrl_cov_bind; + import otp_ctrl_part_pkg::*; + + bind otp_ctrl otp_ctrl_cov_if u_otp_ctrl_cov_if ( + .pwr_otp_o (pwr_otp_o), + .lc_otp_program_i (lc_otp_program_i), + .lc_escalate_en_i (lc_escalate_en_i), + .flash_otp_key_i (flash_otp_key_i), + .sram_otp_key_i (sram_otp_key_i), + .otbn_otp_key_i (otbn_otp_key_i) + ); + + bind otp_ctrl cip_lc_tx_cov_if u_lc_creator_seed_sw_rw_en_cov_if ( + .rst_ni (rst_ni), + .val (lc_creator_seed_sw_rw_en_i) + ); + + bind otp_ctrl cip_lc_tx_cov_if u_lc_seed_hw_rd_en_cov_if ( + .rst_ni (rst_ni), + .val (lc_seed_hw_rd_en_i) + ); + + bind otp_ctrl cip_lc_tx_cov_if u_lc_dft_en_cov_if ( + .rst_ni (rst_ni), + .val (lc_dft_en_i) + ); + + bind otp_ctrl cip_lc_tx_cov_if u_lc_escalate_en_cov_if ( + .rst_ni (rst_ni), + .val (lc_escalate_en_i) + ); + + bind otp_ctrl cip_lc_tx_cov_if u_lc_check_byp_en_cov_if ( + .rst_ni (rst_ni), + .val (lc_check_byp_en_i) + ); + + // Mubi internal coverage for buffered and unbuffered partitions. +% for part in otp_mmap.config["partitions"][:-1]: +<% part_name = Name.from_snake_case(part["name"]) %>\ + `PART_MUBI_COV(${part_name.as_snake_case()}, otp_ctrl_part_pkg::${part_name.as_camel_case()}Idx) +% endfor + + // Mubi internal coverage for DAI interface access +% for part in otp_mmap.config["partitions"][:-1]: +<% part_name = Name.from_snake_case(part["name"]) %>\ + `DAI_MUBI_COV(${part_name.as_snake_case()}, otp_ctrl_part_pkg::${part_name.as_camel_case()}Idx) +% endfor + +`undef PART_MUBI_COV +`undef DAI_MUBI_COV +endmodule diff --git a/src/fuse_ctrl/data/otp_ctrl_dai_lock_vseq.sv.tpl b/src/fuse_ctrl/data/otp_ctrl_dai_lock_vseq.sv.tpl new file mode 100755 index 0000000..05e81f1 --- /dev/null +++ b/src/fuse_ctrl/data/otp_ctrl_dai_lock_vseq.sv.tpl @@ -0,0 +1,90 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +${gen_comment} +<% +from topgen.lib import Name + +parts_without_lc = [part for part in otp_mmap.config["partitions"] if + part["variant"] in ["Buffered", "Unbuffered"]] + +parts_with_digest = [part for part in otp_mmap.config["partitions"] if + (part["sw_digest"] or part["hw_digest"])] +%>\ +// otp_ctrl_dai_lock_vseq is developed to read/write lock DAI interface by partitions, and request +// read/write access to check if correct status and error code is triggered + +// Partition's legal range covers offset to digest addresses, dai_rd/dai_wr function will +// randomize the address based on the granularity. +`define PART_ADDR_RANGE(i) ${"\\"} + {[PartInfo[``i``].offset : (PartInfo[``i``].offset + PartInfo[``i``].size - 8)]} + +class otp_ctrl_dai_lock_vseq extends otp_ctrl_smoke_vseq; + `uvm_object_utils(otp_ctrl_dai_lock_vseq) + + `uvm_object_new + + // enable access_err for each cycle + constraint no_access_err_c {access_locked_parts == 1;} + + constraint num_trans_c { + num_trans inside {[1:10]}; + num_dai_op inside {[1:50]}; + } + + // the LC partition is always the last one + constraint partition_index_c {part_idx inside {[0:LifeCycleIdx]};} + + constraint dai_wr_legal_addr_c { +% for part in parts_without_lc: +<% + part_name = Name.from_snake_case(part["name"]) + part_name_camel = part_name.as_camel_case() +%>\ + if (part_idx == ${part_name_camel}Idx) { + dai_addr inside `PART_ADDR_RANGE(${part_name_camel}Idx); + } +% endfor + if (part_idx == LifeCycleIdx) { + if (write_unused_addr) { + dai_addr inside {[PartInfo[LifeCycleIdx].offset : {OTP_ADDR_WIDTH{1'b1}}]}; + } else { + dai_addr inside `PART_ADDR_RANGE(LifeCycleIdx); + } + } + solve part_idx before dai_addr; + } + + constraint dai_wr_digests_c { + {dai_addr[TL_AW-1:2], 2'b0} dist { + { +% for part in parts_with_digest: +<% + part_name = Name.from_snake_case(part["name"]) + part_name_camel = part_name.as_camel_case() +%>\ + ${part_name_camel}DigestOffset${"" if loop.last else ","} +% endfor + } :/ 1, + [VendorTestOffset : '1] :/ 9 + }; + } + + virtual task pre_start(); + super.pre_start(); + is_valid_dai_op = 0; + endtask + + virtual task dut_init(string reset_kind = "HARD"); + super.dut_init(reset_kind); + if ($urandom_range(0, 1)) begin + cfg.otp_ctrl_vif.drive_lc_creator_seed_sw_rw_en(get_rand_lc_tx_val(.t_weight(0))); + end + if ($urandom_range(0, 1)) begin + cfg.otp_ctrl_vif.drive_lc_owner_seed_sw_rw_en(get_rand_lc_tx_val(.t_weight(0))); + end + endtask + +endclass + +`undef PART_ADDR_RANGE diff --git a/src/fuse_ctrl/data/otp_ctrl_env_cov.sv.tpl b/src/fuse_ctrl/data/otp_ctrl_env_cov.sv.tpl new file mode 100755 index 0000000..f20736c --- /dev/null +++ b/src/fuse_ctrl/data/otp_ctrl_env_cov.sv.tpl @@ -0,0 +1,358 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +${gen_comment} +/** + * Covergoups that are dependent on run-time parameters that may be available + * only in build_phase can be defined here + * Covergroups may also be wrapped inside helper classes if needed. + */ +<% +from topgen.lib import Name + +parts_without_lc = [part for part in otp_mmap.config["partitions"] if + part["variant"] in ["Buffered", "Unbuffered"]] + +unbuffered_parts = [part for part in otp_mmap.config["partitions"] if + part["variant"] == "Unbuffered"] + +unbuffered_parts_with_digest = [part for part in unbuffered_parts if + (part["sw_digest"] or part["hw_digest"])] + +buffered_parts = [part for part in otp_mmap.config["partitions"] if + part["variant"] == "Buffered"] + +buffered_nonsecret_parts_with_digest = [part for part in buffered_parts if + (part["sw_digest"] or part["hw_digest"]) and + not part["secret"]] + +buffered_secret_parts_with_digest = [part for part in buffered_parts if + (part["sw_digest"] or part["hw_digest"]) and + part["secret"]] +## Partitions + LCI + DAI +num_err_code = len(otp_mmap.config["partitions"]) + 2 +%>\ +class otp_ctrl_unbuf_err_code_cg_wrap; + // Unbuffered partition can use TLUL interface to read out but cannot write, thus error_code does + // not have write_blank_err. + covergroup unbuf_err_code_cg(string name) with function sample(bit [TL_DW-1:0] val); + option.per_instance = 1; + option.name = name; + err_code_vals: coverpoint val { + bins no_err = {OtpNoError}; + bins macro_err = {OtpMacroError}; + bins ecc_corr_err = {OtpMacroEccCorrError}; + bins ecc_uncorr_err = {OtpMacroEccUncorrError}; + bins access_err = {OtpAccessError}; + bins check_fail = {OtpCheckFailError}; + bins fsm_err = {OtpFsmStateError}; + illegal_bins illegal_err = default; + } + endgroup + + function new(string name); + unbuf_err_code_cg = new(name); + endfunction +endclass + +class otp_ctrl_buf_err_code_cg_wrap; + // Buffered partition must use DAI interface to access partition, so it does not have access_err + // and write_blank err. + covergroup buf_err_code_cg(string name) with function sample(bit [TL_DW-1:0] val); + option.per_instance = 1; + option.name = name; + err_code_vals: coverpoint val { + bins no_err = {OtpNoError}; + bins macro_err = {OtpMacroError}; + bins ecc_corr_err = {OtpMacroEccCorrError}; + bins ecc_uncorr_err = {OtpMacroEccUncorrError}; + bins check_fail = {OtpCheckFailError}; + bins fsm_err = {OtpFsmStateError}; + illegal_bins illegal_err = default; + } + endgroup + + function new(string name); + buf_err_code_cg = new(name); + endfunction +endclass + +class otp_ctrl_csr_rd_after_alert_cg_wrap; + // This covergroup samples CSRs being checked (via CSR read) after fatal alert is issued. + covergroup csr_rd_after_alert_cg(otp_ctrl_core_reg_block ral) with function sample(bit[TL_DW-1:0] + csr_offset); + read_csr_after_alert_issued: coverpoint csr_offset { + bins unbuffered_digests = { +% for part in unbuffered_parts_with_digest: + ral.${part["name"].lower()}_digest[0].get_offset(), + ral.${part["name"].lower()}_digest[1].get_offset()${"" if loop.last else ","} +% endfor + }; + bins hw_digests = { +% for part in buffered_nonsecret_parts_with_digest: + ral.${part["name"].lower()}_digest[0].get_offset(), + ral.${part["name"].lower()}_digest[1].get_offset()${"" if loop.last else ","} +% endfor + }; + bins secret_digests = { +% for part in buffered_secret_parts_with_digest: + ral.${part["name"].lower()}_digest[0].get_offset(), + ral.${part["name"].lower()}_digest[1].get_offset()${"" if loop.last else ","} +% endfor + }; + bins direct_access_rdata = { + ral.direct_access_rdata[0].get_offset(), + ral.direct_access_rdata[1].get_offset() + }; + bins status = { + ral.status.get_offset() + }; + bins error_code = { +% for k in range(num_err_code): + ral.err_code[${k}].get_offset()${"" if loop.last else ","} +% endfor + }; + } + endgroup + + function new(otp_ctrl_core_reg_block ral); + csr_rd_after_alert_cg = new(ral); + endfunction + + function void sample(bit[TL_DW-1:0] csr_offset); + csr_rd_after_alert_cg.sample(csr_offset); + endfunction +endclass + +class otp_ctrl_unbuf_access_lock_cg_wrap; + covergroup unbuf_access_lock_cg(string name) with function sample(bit read_lock, bit write_lock, + bit is_write); + option.per_instance = 1; + option.name = name; + read_access_locked: coverpoint read_lock; + write_access_locked: coverpoint write_lock; + operation_type: coverpoint is_write { + bins write_op = {1}; + bins read_op = {0}; + } + unbuf_part_access_cross: cross read_access_locked, write_access_locked, operation_type; + endgroup + + function new(string name); + unbuf_access_lock_cg = new(name); + endfunction + + function void sample(bit read_lock, bit write_lock, bit is_write); + unbuf_access_lock_cg.sample(read_lock, write_lock, is_write); + endfunction +endclass + +class otp_ctrl_env_cov extends cip_base_env_cov #(.CFG_T(otp_ctrl_env_cfg)); + `uvm_component_utils(otp_ctrl_env_cov) + + // the base class provides the following handles for use: + // otp_ctrl_env_cfg: cfg + + otp_ctrl_unbuf_err_code_cg_wrap unbuf_err_code_cg_wrap[NumPartUnbuf]; + otp_ctrl_buf_err_code_cg_wrap buf_err_code_cg_wrap[NumPartBuf]; + otp_ctrl_csr_rd_after_alert_cg_wrap csr_rd_after_alert_cg_wrap; + otp_ctrl_unbuf_access_lock_cg_wrap unbuf_access_lock_cg_wrap[NumPartUnbuf]; + + bit_toggle_cg_wrap lc_prog_cg; + bit_toggle_cg_wrap otbn_req_cg; + bit_toggle_cg_wrap status_csr_cg[OtpStatusFieldSize]; + + // covergroups + // This covergroup collects different conditions when outputs (hwcfg_o, keymgr_key_o) are checked + // in scb: + // - If lc_esc_en is On + // - If each partition is locked (expect LC) + covergroup power_on_cg with function sample (bit lc_esc_en, bit[NumPart-2:0] parts_locked); + lc_esc: coverpoint lc_esc_en; +% for k, part in enumerate(parts_without_lc): + ${part["name"].lower()}_lock: coverpoint parts_locked[${k}]; +% endfor + endgroup + + // This covergroup is sampled only if flash request passed scb check. + covergroup flash_req_cg with function sample (int index, bit locked); + flash_index: coverpoint index { + bins flash_data_key = {FlashDataKey}; + bins flash_addr_key = {FlashAddrKey}; + illegal_bins il = default; + } + secret1_lock: coverpoint locked; + flash_req_lock_cross: cross flash_index, secret1_lock; + endgroup + + // This covergroup is sampled only if sram request passed scb check. + covergroup sram_req_cg with function sample (int index, bit locked); + sram_index: coverpoint index { + bins sram_key[NumSramKeyReqSlots] = {[0:(NumSramKeyReqSlots-1)]}; + illegal_bins il = default; + } + secret1_lock: coverpoint locked; + sram_req_lock_cross: cross sram_index, secret1_lock; + endgroup + + // This covergroup is sampled only if keymgr output passed scb check. + covergroup keymgr_o_cg with function sample (bit lc_seed_hw_rd_en, bit locked); + keymgr_rd_en: coverpoint lc_seed_hw_rd_en; + // TODO: probably should add all partitions with keymgr material here. + secret2_lock: coverpoint locked; + keymgr_output_conditions: cross keymgr_rd_en, secret2_lock; + endgroup + + // This covergroup samples dai request being issued after fatal alert is issued. + covergroup req_dai_access_after_alert_cg with function sample(bit [TL_DW-1:0] val); + req_dai_access_after_alert_issued: coverpoint val { + bins dai_write = {DaiWrite}; + bins dai_read = {DaiRead}; + bins dai_digest = {DaiDigest}; + } + endgroup + + // This covergroup samples background check being issued after fatal alert is issued. + covergroup issue_checks_after_alert_cg with function sample(bit [TL_DW-1:0] val); + issue_checks_after_alert_issued: coverpoint val { + bins integrity_check = {1}; + bins consistency_check = {2}; + } + endgroup + + // This covergroup collects DAI err_code value. + // DAI access does not have checks, thus no check_fail error. + covergroup dai_err_code_cg with function sample(bit [TL_DW-1:0] val, int part_idx); + err_code_vals: coverpoint val { + bins no_err = {OtpNoError}; + bins macro_err = {OtpMacroError}; + bins ecc_corr_err = {OtpMacroEccCorrError}; + bins ecc_uncorr_err = {OtpMacroEccUncorrError}; + bins write_blank_err = {OtpMacroWriteBlankError}; + bins access_err = {OtpAccessError}; + bins fsm_err = {OtpFsmStateError}; + illegal_bins illegal_err = default; + } + partition: coverpoint part_idx { +% for part in otp_mmap.config["partitions"]: +<% part_name = Name.from_snake_case(part["name"]) %>\ + bins ${part["name"].lower()} = {${part_name.as_camel_case()}Idx}; +% endfor + bins illegal_idx = default; + } + // LC partition has a separate LCI err_code to collect macro related errors. + dai_err_code_for_all_partitions: cross err_code_vals, partition { + // Illegal bin - vendor_test partition does not have EccUncorrectable error. + illegal_bins vendor_test_ecc_uncorrectable_err = + binsof (partition.vendor_test) && binsof (err_code_vals.ecc_uncorr_err); + ignore_bins life_cycle_ignore = binsof (partition.life_cycle) && + binsof(err_code_vals) intersect {[OtpMacroError:OtpMacroWriteBlankError]}; + } + endgroup + + // This covergroup collects LCI err_code value. + // LCI access does not have digest, thus no access_err. Check_fail, ecc_errors are covered in lc + // buffered partition instead of LCI here. + covergroup lci_err_code_cg with function sample(bit [TL_DW-1:0] val); + err_code_vals: coverpoint val { + bins no_err = {OtpNoError}; + bins macro_err = {OtpMacroError}; + bins write_blank_err = {OtpMacroWriteBlankError}; + bins fsm_err = {OtpFsmStateError}; + illegal_bins illegal_err = default; + } + endgroup + + covergroup dai_access_secret2_cg with function sample(bit lc_rw_en, dai_cmd_e dai_cmd); + lc_creator_seed_sw_rw_en: coverpoint lc_rw_en; + dai_access_cmd: coverpoint dai_cmd { + bins dai_rd = {DaiRead}; + bins dai_wr = {DaiWrite}; + bins dai_digest = {DaiDigest}; + } + dai_access_secret2: cross lc_creator_seed_sw_rw_en, dai_access_cmd; + endgroup + + function new(string name, uvm_component parent); + super.new(name, parent); + // Create coverage from local covergroups. + power_on_cg = new(); + flash_req_cg = new(); + sram_req_cg = new(); + keymgr_o_cg = new(); + req_dai_access_after_alert_cg = new(); + issue_checks_after_alert_cg = new(); + dai_err_code_cg = new(); + lci_err_code_cg = new(); + dai_access_secret2_cg = new(); + endfunction : new + + virtual function void build_phase(uvm_phase phase); + super.build_phase(phase); + // Create instances from bit_toggle_cg_wrapper. + lc_prog_cg = new("lc_prog_cg", "", 0); + otbn_req_cg = new("otbn_req_cg", "", 0); + foreach (status_csr_cg[i]) begin + otp_status_e index = otp_status_e'(i); + status_csr_cg[i]= new(index.name, "status_csr_cg", 0); + end + + // Create instances from external wrapper classes. + csr_rd_after_alert_cg_wrap = new(cfg.ral); + foreach (unbuf_err_code_cg_wrap[i]) begin + otp_status_e index = otp_status_e'(i); + unbuf_err_code_cg_wrap[i] = new($sformatf("unbuf_err_code_cg_wrap[%0s]", index.name)); + end + foreach (buf_err_code_cg_wrap[i]) begin + otp_status_e index = otp_status_e'(i + 2); + buf_err_code_cg_wrap[i] = new($sformatf("buf_err_code_cg_wrap[%0s]", index.name)); + end + foreach (unbuf_access_lock_cg_wrap[i]) begin + part_idx_e index = part_idx_e'(i); + unbuf_access_lock_cg_wrap[i] = new($sformatf("buf_err_code_cg_wrap[%0s]", index.name)); + end + endfunction + + function void collect_status_cov(bit [TL_DW-1:0] val); + foreach (status_csr_cg[i]) begin + status_csr_cg[i].sample(val[i]); + end + endfunction + + // Collect coverage for err_code when it is a compact multi-reg. For DAI error it uses the given + // access_part_idx as the target of the DAI access. + function void collect_compact_err_code_cov(bit [TL_DW-1:0] val, int access_part_idx = DaiIdx); + dv_base_reg_field err_code_flds[$]; + cfg.ral.err_code[0].get_dv_base_reg_fields(err_code_flds); + foreach (err_code_flds[part]) begin + collect_err_code_cov(part, get_field_val(err_code_flds[part], val), access_part_idx); + end + endfunction + + // Collect coverage for a given partition error_code. For DAI error it uses the given + // access_part_idx as the target of the DAI access. + function void collect_err_code_cov(int part_idx, bit [TL_DW-1:0] val, + int access_part_idx = DaiIdx); + case (part_idx) +% for part in otp_mmap.config["partitions"]: +<% part_name = Name.from_snake_case(part["name"]) %>\ + Otp${part_name.as_camel_case()}ErrIdx: begin + % if part in unbuffered_parts: + unbuf_err_code_cg_wrap[part_idx].unbuf_err_code_cg.sample(val); + % elif part in buffered_parts: + buf_err_code_cg_wrap[part_idx - NumPartUnbuf].buf_err_code_cg.sample(val); + % endif + end +% endfor + OtpDaiErrIdx: begin + dai_err_code_cg.sample(val, access_part_idx); + end + OtpLciErrIdx: begin + lci_err_code_cg.sample(val); + end + default: begin + `uvm_fatal(`gfn, $sformatf("invalid err_code index %0d", part_idx)) + end + endcase + endfunction +endclass diff --git a/src/fuse_ctrl/data/otp_ctrl_env_pkg.sv.tpl b/src/fuse_ctrl/data/otp_ctrl_env_pkg.sv.tpl new file mode 100755 index 0000000..08c86cb --- /dev/null +++ b/src/fuse_ctrl/data/otp_ctrl_env_pkg.sv.tpl @@ -0,0 +1,265 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +${gen_comment} +<% +from topgen.lib import Name + +parts_without_lc = [part for part in otp_mmap.config["partitions"] if + part["variant"] in ["Buffered", "Unbuffered"]] +otp_size_as_hex_text = f'{(2 ** otp_mmap.config["otp"]["byte_addr_width"]):x}' +%>\ +package otp_ctrl_env_pkg; + // dep packages + import uvm_pkg::*; + import top_pkg::*; + import dv_utils_pkg::*; + import dv_lib_pkg::*; + import dv_base_reg_pkg::*; + import tl_agent_pkg::*; + import cip_base_pkg::*; + import csr_utils_pkg::*; + import push_pull_agent_pkg::*; + import otp_ctrl_core_ral_pkg::*; + import otp_ctrl_prim_ral_pkg::*; + import otp_ctrl_reg_pkg::*; + import otp_ctrl_pkg::*; + import otp_ctrl_part_pkg::*; + import lc_ctrl_pkg::*; + import lc_ctrl_state_pkg::*; + import lc_ctrl_dv_utils_pkg::*; + import mem_bkdr_util_pkg::*; + import otp_scrambler_pkg::*; + import sec_cm_pkg::*; + + // macro includes + `include "uvm_macros.svh" + `include "dv_macros.svh" + + // parameters + parameter string LIST_OF_ALERTS[] = {"fatal_macro_error", + "fatal_check_error", + "fatal_bus_integ_error", + "fatal_prim_otp_alert", + "recov_prim_otp_alert"}; + parameter uint NUM_ALERTS = 5; + parameter uint NUM_EDN = 1; + + parameter uint DIGEST_SIZE = 8; + parameter uint SW_WINDOW_BASE_ADDR = 'h${otp_size_as_hex_text}; + parameter uint SW_WINDOW_SIZE = NumSwCfgWindowWords * 4; + + parameter uint TL_SIZE = (TL_DW / 8); + // LC has its own storage in scb + // we can use the LC offset here because it will always be the last partition. + parameter uint OTP_ARRAY_SIZE = LcTransitionCntOffset / TL_SIZE; + + parameter int OTP_ADDR_WIDTH = OtpByteAddrWidth-2; + + parameter uint NUM_PRIM_REG = 8; + + // sram rsp data has 1 bit for seed_valid, the rest are for key and nonce + parameter uint SRAM_DATA_SIZE = 1 + SramKeyWidth + SramNonceWidth; + // otbn rsp data has 1 bit for seed_valid, the rest are for key and nonce + parameter uint OTBN_DATA_SIZE = 1 + OtbnKeyWidth + OtbnNonceWidth; + // flash rsp data has 1 bit for seed_valid, the rest are for key + parameter uint FLASH_DATA_SIZE = 1 + FlashKeyWidth; + // lc program data has lc_state data and lc_cnt data + parameter uint LC_PROG_DATA_SIZE = LcStateWidth + LcCountWidth; + + parameter uint NUM_SRAM_EDN_REQ = 12; + parameter uint NUM_OTBN_EDN_REQ = 10; + + parameter uint CHK_TIMEOUT_CYC = 40; + + // When fatal alert triggered, all partitions and the DAI & LCI go to error state and status will + // be set to 1. + parameter bit [NumErrorEntries-1:0] FATAL_EXP_STATUS = '1; + + // lc does not have dai access + parameter int PART_BASE_ADDRS [NumPart-1] = { +% for part in parts_without_lc: +<% + part_name = Name.from_snake_case(part["name"]) + part_name_camel = part_name.as_camel_case() +%>\ + ${part_name_camel}Offset${"" if loop.last else ","} +% endfor + }; + + // lc does not have digest + parameter int PART_OTP_DIGEST_ADDRS [NumPart-1] = { +% for part in parts_without_lc: +<% + part_name = Name.from_snake_case(part["name"]) + part_name_camel = part_name.as_camel_case() +%>\ +% if part["sw_digest"] or part["hw_digest"]: + ${part_name_camel}DigestOffset >> 2${"" if loop.last else ","} +% else: + -1${"" if loop.last else ","} // This partition does not have a digest. +% endif +% endfor + }; + + // types + typedef enum bit [1:0] { + OtpOperationDone, + OtpErr, + NumOtpCtrlIntr + } otp_intr_e; + + typedef enum bit [5:0] { +% for part in otp_mmap.config["partitions"]: +<% + part_name = Name.from_snake_case(part["name"]) + part_name_camel = part_name.as_camel_case() +%>\ + Otp${part_name_camel}ErrIdx, +% endfor + OtpDaiErrIdx, + OtpLciErrIdx, + OtpTimeoutErrIdx, + OtpLfsrFsmErrIdx, + OtpScramblingFsmErrIdx, + OtpDerivKeyFsmErrIdx, + OtpBusIntegErrorIdx, + OtpDaiIdleIdx, + OtpCheckPendingIdx, + OtpStatusFieldSize + } otp_status_e; + + typedef enum bit [2:0] { + OtpNoError, + OtpMacroError, + OtpMacroEccCorrError, + OtpMacroEccUncorrError, + OtpMacroWriteBlankError, + OtpAccessError, + OtpCheckFailError, + OtpFsmStateError + } otp_err_code_e; + + typedef enum bit [1:0] { + OtpNoEccErr, + OtpEccCorrErr, + OtpEccUncorrErr + } otp_ecc_err_e; + + typedef enum bit [1:0] { + OtpNoAlert, + OtpCheckAlert, + OtpMacroAlert + } otp_alert_e; + + typedef struct packed { + bit read_lock; + bit write_lock; + } otp_part_access_lock_t; + + // OTP conditions when driving specific port. + typedef enum bit [2:0] { + DuringOTPInit, + DuringOTPDaiBusy, + DuringOTPDaiDigest, + DuringOTPRead, + DriveRandomly + } port_drive_condition_e; + + typedef virtual otp_ctrl_if otp_ctrl_vif; + + parameter otp_err_code_e OTP_TERMINAL_ERRS[4] = {OtpMacroEccUncorrError, + OtpCheckFailError, + OtpFsmStateError, + OtpMacroError}; + + // functions + function automatic int get_part_index(bit [TL_DW-1:0] addr); + int index; + for (index = 0; index < NumPart; index++) begin + if (PartInfo[index].offset > addr) begin + index--; + break; + end + end + if (index == NumPart) index--; + return index; + endfunction + + function automatic bit is_secret(bit [TL_DW-1:0] addr); + int part_index = get_part_index(addr); + return PartInfo[part_index].secret; + endfunction + + function automatic bit part_has_digest(int part_idx); + return PartInfo[part_idx].hw_digest || PartInfo[part_idx].sw_digest; + endfunction + + function automatic bit part_has_hw_digest(int part_idx); + return PartInfo[part_idx].hw_digest; + endfunction + + function automatic bit is_sw_digest(bit [TL_DW-1:0] addr); + int part_idx = get_part_index(addr); + if (PartInfo[part_idx].sw_digest) begin + // If the partition contains a digest, it will be located in the last 64bit of the partition. + return {addr[TL_DW-1:3], 3'b0} == ((PartInfo[part_idx].offset + PartInfo[part_idx].size) - 8); + end else begin + return 0; + end + endfunction + + function automatic bit is_digest(bit [TL_DW-1:0] addr); + int part_idx = get_part_index(addr); + if (PartInfo[part_idx].sw_digest || PartInfo[part_idx].hw_digest) begin + // If the partition contains a digest, it will be located in the last 64bit of the partition. + return {addr[TL_DW-1:3], 3'b0} == ((PartInfo[part_idx].offset + PartInfo[part_idx].size) - 8); + end else begin + return 0; + end + endfunction + + function automatic bit is_sw_part(bit [TL_DW-1:0] addr); + int part_idx = get_part_index(addr); + return is_sw_part_idx(part_idx); + endfunction + + function automatic bit is_sw_part_idx(int part_idx); + return (PartInfo[part_idx].variant == Unbuffered); + endfunction + + function automatic bit is_hw_part(bit [TL_DW-1:0] addr); + int part_idx = get_part_index(addr); + return is_hw_part_idx(part_idx); + endfunction + + function automatic bit is_hw_part_idx(int part_idx); + return (PartInfo[part_idx].variant == Buffered); + endfunction + + // Returns true if this partition supports ECC. Otherwise, no ECC errors are reported, and + // the single bit errors are not corrected. + function automatic bit part_has_integrity(int part_idx); + return PartInfo[part_idx].integrity; + endfunction + + // Resolve an offset within the software window as an offset within the whole otp_ctrl block. + function automatic bit [TL_AW-1:0] get_sw_window_offset(bit [TL_AW-1:0] dai_addr); + return dai_addr + SW_WINDOW_BASE_ADDR; + endfunction + + function automatic bit [TL_DW-1:0] normalize_dai_addr(bit [TL_DW-1:0] dai_addr); + normalize_dai_addr = (is_secret(dai_addr) || is_digest(dai_addr)) ? dai_addr >> 3 << 3 : + dai_addr >> 2 << 2; + endfunction + + // package sources + `include "otp_ctrl_ast_inputs_cfg.sv" + `include "otp_ctrl_env_cfg.sv" + `include "otp_ctrl_env_cov.sv" + `include "otp_ctrl_virtual_sequencer.sv" + `include "otp_ctrl_scoreboard.sv" + `include "otp_ctrl_env.sv" + `include "otp_ctrl_vseq_list.sv" + +endpackage diff --git a/src/fuse_ctrl/data/otp_ctrl_fixes.json b/src/fuse_ctrl/data/otp_ctrl_fixes.json new file mode 100644 index 0000000..9f42ef7 --- /dev/null +++ b/src/fuse_ctrl/data/otp_ctrl_fixes.json @@ -0,0 +1,1925 @@ +{ + "name": "caliptra_otp_ctrl", + "human_name": " Caliptra One-Time Programmable Memory COntroller", + "one_line_desc": "Interfaces integrated one0time programmable memory, supports scrambling, integrity and secure dai_wr_inprogress", + "one_paragraph_desc": "One-Time Programmable (OTP) Memory Controller provides an open source abstraction interface for software and other hardware components such as Life Cycle Controller and Key Manager to interact with an integrated, closed source, proprietary OTP memory.\nOn top of defensive features provided by the proprietary OTP memory to deter side-channel analysis (SCA), fault injection (FI) attacks, and visual and electrical probing, the open source OTP controller features high-level logical security protection such as integrity checks and scrambling, as well as software isolation for when OTP contents are readable and programmable.\nIt features multiple individually-lockable logical partitions, periodic / persistent checking of OTP values, and a separate partition and interface for Life Cycle Controller.", + "cip_id": "16", + "design_spec": "../doc", + "dv_doc": "../doc/dv", + "hw_checklist": "../doc/checklist", + "sw_checklist": "/sw/device/lib/dif/dif_otp_ctrl", + "revisions": [ + { + "version": "0.1.0", + "life_stage": "L1", + "design_stage": "D2", + "verification_stage": "V2", + "dif_stage": "S1", + "commit_id": "127b109e2fab9336e830158abe449a3922544ded", + "notes": "" + }, + { + "version": "1.0.0", + "life_stage": "L1", + "design_stage": "D3", + "verification_stage": "V2S", + "dif_stage": "S2", + "notes": "" + }, + { + "version": "2.0.0", + "life_stage": "L1", + "design_stage": "D2S", + "verification_stage": "V2S", + "dif_stage": "S2", + "notes": "" + } + ], + "clocking": [ + { + "clock": "clk_i", + "reset": "rst_ni", + "primary": true + }, + { + "clock": "clk_edn_i", + "reset": "rst_edn_ni" + } + ], + "scan": "true", + "scan_reset": "true", + "scan_en": "true", + "bus_interfaces": [ + { + "protocol": "tlul", + "direction": "device", + "name": "core" + }, + { + "protocol": "tlul", + "direction": "device", + "name": "prim", + "hier_path": "u_otp.gen_generic.u_impl_generic.u_reg_top" + } + ], + "available_output_list": [ + { + "name": "test", + "width": 8, + "desc": "Test-related GPIOs. Only active in DFT-enabled life cycle states." + } + ], + "interrupt_list": [ + { + "name": "otp_operation_done", + "desc": "A direct access command or digest calculation operation has completed." + }, + { + "name": "otp_error", + "desc": "An error has occurred in the OTP controller. Check the !!ERR_CODE register to get more information." + } + ], + "alert_list": [ + { + "name": "fatal_macro_error", + "desc": "This alert triggers if hardware detects an uncorrectable error during an OTP transaction, for example an uncorrectable ECC error in the OTP array." + }, + { + "name": "fatal_check_error", + "desc": "This alert triggers if any of the background checks fails. This includes the digest checks and concurrent ECC checks in the buffer registers." + }, + { + "name": "fatal_bus_integ_error", + "desc": "This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected." + }, + { + "name": "fatal_prim_otp_alert", + "desc": "Fatal alert triggered inside the OTP primitive, including fatal TL-UL bus integrity faults of the test interface." + }, + { + "name": "recov_prim_otp_alert", + "desc": "Recoverable alert triggered inside the OTP primitive." + } + ], + "param_list": [ + { + "name": "MemInitFile", + "desc": "VMEM file to initialize the OTP macro.", + "type": "", + "default": "\"\"", + "expose": "true", + "local": "false" + }, + { + "name": "RndCnstLfsrSeed", + "desc": "Compile-time random bits for initial LFSR seed", + "type": "otp_ctrl_pkg::lfsr_seed_t", + "randcount": "40", + "randtype": "data" + }, + { + "name": "RndCnstLfsrPerm", + "desc": "Compile-time random permutation for LFSR output", + "type": "otp_ctrl_pkg::lfsr_perm_t", + "randcount": "40", + "randtype": "perm" + }, + { + "name": "RndCnstScrmblKeyInit", + "desc": "Compile-time random permutation for scrambling key/nonce register reset value", + "type": "otp_ctrl_pkg::scrmbl_key_init_t", + "randcount": "256", + "randtype": "data" + }, + { + "name": "NumSramKeyReqSlots", + "desc": "Number of key slots", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "OtpByteAddrWidth", + "desc": "Width of the OTP byte address.", + "type": "int", + "default": "12", + "local": "true" + }, + { + "name": "NumErrorEntries", + "desc": "Number of error register entries.", + "type": "int", + "default": "9", + "local": "true" + }, + { + "name": "NumDaiWords", + "desc": "Number of 32bit words in the DAI.", + "type": "int", + "default": "2", + "local": "true" + }, + { + "name": "NumDigestWords", + "desc": "Size of the digest fields in 32bit words.", + "type": "int", + "default": "2", + "local": "true" + }, + { + "name": "NumSwCfgWindowWords", + "desc": "Size of the TL-UL window in 32bit words. Note that the effective partition size is smaller than that.", + "type": "int", + "default": "1024", + "local": "true" + }, + { + "name": "NumPart", + "desc": "Number of partitions", + "type": "int", + "default": "7", + "local": "true" + }, + { + "name": "NumPartUnbuf", + "desc": "Number of unbuffered partitions", + "type": "int", + "default": "2", + "local": "true" + }, + { + "name": "NumPartBuf", + "desc": "Number of buffered partitions (including 1 lifecycle partition)", + "type": "int", + "default": "5", + "local": "true" + }, + { + "name": "VendorTestOffset", + "desc": "Offset of the VENDOR_TEST partition", + "type": "int", + "default": "0", + "local": "true" + }, + { + "name": "VendorTestSize", + "desc": "Size of the VENDOR_TEST partition", + "type": "int", + "default": "64", + "local": "true" + }, + { + "name": "ScratchOffset", + "desc": "Offset of SCRATCH", + "type": "int", + "default": "0", + "local": "true" + }, + { + "name": "ScratchSize", + "desc": "Size of SCRATCH", + "type": "int", + "default": "56", + "local": "true" + }, + { + "name": "VendorTestDigestOffset", + "desc": "Offset of VENDOR_TEST_DIGEST", + "type": "int", + "default": "56", + "local": "true" + }, + { + "name": "VendorTestDigestSize", + "desc": "Size of VENDOR_TEST_DIGEST", + "type": "int", + "default": "8", + "local": "true" + }, + { + "name": "NonSecretFusesOffset", + "desc": "Offset of the NON_SECRET_FUSES partition", + "type": "int", + "default": "64", + "local": "true" + }, + { + "name": "NonSecretFusesSize", + "desc": "Size of the NON_SECRET_FUSES partition", + "type": "int", + "default": "3736", + "local": "true" + }, + { + "name": "FmcKeyManifestSvnOffset", + "desc": "Offset of FMC_KEY_MANIFEST_SVN", + "type": "int", + "default": "64", + "local": "true" + }, + { + "name": "FmcKeyManifestSvnSize", + "desc": "Size of FMC_KEY_MANIFEST_SVN", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "RuntimeSvnOffset", + "desc": "Offset of RUNTIME_SVN", + "type": "int", + "default": "68", + "local": "true" + }, + { + "name": "RuntimeSvnSize", + "desc": "Size of RUNTIME_SVN", + "type": "int", + "default": "16", + "local": "true" + }, + { + "name": "LmsVerifyOffset", + "desc": "Offset of LMS_VERIFY", + "type": "int", + "default": "84", + "local": "true" + }, + { + "name": "LmsVerifySize", + "desc": "Size of LMS_VERIFY", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "LmsRevocationOffset", + "desc": "Offset of LMS_REVOCATION", + "type": "int", + "default": "88", + "local": "true" + }, + { + "name": "LmsRevocationSize", + "desc": "Size of LMS_REVOCATION", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "KeyManifestPkHashMaskOffset", + "desc": "Offset of KEY_MANIFEST_PK_HASH_MASK", + "type": "int", + "default": "92", + "local": "true" + }, + { + "name": "KeyManifestPkHashMaskSize", + "desc": "Size of KEY_MANIFEST_PK_HASH_MASK", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "OwnerPkHashOffset", + "desc": "Offset of OWNER_PK_HASH", + "type": "int", + "default": "96", + "local": "true" + }, + { + "name": "OwnerPkHashSize", + "desc": "Size of OWNER_PK_HASH", + "type": "int", + "default": "48", + "local": "true" + }, + { + "name": "IdevidCertAttrOffset", + "desc": "Offset of IDEVID_CERT_ATTR", + "type": "int", + "default": "144", + "local": "true" + }, + { + "name": "IdevidCertAttrSize", + "desc": "Size of IDEVID_CERT_ATTR", + "type": "int", + "default": "96", + "local": "true" + }, + { + "name": "IdevidManufHsmIdOffset", + "desc": "Offset of IDEVID_MANUF_HSM_ID", + "type": "int", + "default": "240", + "local": "true" + }, + { + "name": "IdevidManufHsmIdSize", + "desc": "Size of IDEVID_MANUF_HSM_ID", + "type": "int", + "default": "16", + "local": "true" + }, + { + "name": "SocSteppingIdOffset", + "desc": "Offset of SOC_STEPPING_ID", + "type": "int", + "default": "256", + "local": "true" + }, + { + "name": "SocSteppingIdSize", + "desc": "Size of SOC_STEPPING_ID", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "NonSecretFusesDigestOffset", + "desc": "Offset of NON_SECRET_FUSES_DIGEST", + "type": "int", + "default": "3792", + "local": "true" + }, + { + "name": "NonSecretFusesDigestSize", + "desc": "Size of NON_SECRET_FUSES_DIGEST", + "type": "int", + "default": "8", + "local": "true" + }, + { + "name": "Secret0Offset", + "desc": "Offset of the SECRET0 partition", + "type": "int", + "default": "3800", + "local": "true" + }, + { + "name": "Secret0Size", + "desc": "Size of the SECRET0 partition", + "type": "int", + "default": "40", + "local": "true" + }, + { + "name": "TestUnlockTokenOffset", + "desc": "Offset of TEST_UNLOCK_TOKEN", + "type": "int", + "default": "3800", + "local": "true" + }, + { + "name": "TestUnlockTokenSize", + "desc": "Size of TEST_UNLOCK_TOKEN", + "type": "int", + "default": "16", + "local": "true" + }, + { + "name": "TestExitTokenOffset", + "desc": "Offset of TEST_EXIT_TOKEN", + "type": "int", + "default": "3816", + "local": "true" + }, + { + "name": "TestExitTokenSize", + "desc": "Size of TEST_EXIT_TOKEN", + "type": "int", + "default": "16", + "local": "true" + }, + { + "name": "Secret0DigestOffset", + "desc": "Offset of SECRET0_DIGEST", + "type": "int", + "default": "3832", + "local": "true" + }, + { + "name": "Secret0DigestSize", + "desc": "Size of SECRET0_DIGEST", + "type": "int", + "default": "8", + "local": "true" + }, + { + "name": "Secret1Offset", + "desc": "Offset of the SECRET1 partition", + "type": "int", + "default": "3840", + "local": "true" + }, + { + "name": "Secret1Size", + "desc": "Size of the SECRET1 partition", + "type": "int", + "default": "56", + "local": "true" + }, + { + "name": "UdsSeedOffset", + "desc": "Offset of UDS_SEED", + "type": "int", + "default": "3840", + "local": "true" + }, + { + "name": "UdsSeedSize", + "desc": "Size of UDS_SEED", + "type": "int", + "default": "48", + "local": "true" + }, + { + "name": "Secret1DigestOffset", + "desc": "Offset of SECRET1_DIGEST", + "type": "int", + "default": "3888", + "local": "true" + }, + { + "name": "Secret1DigestSize", + "desc": "Size of SECRET1_DIGEST", + "type": "int", + "default": "8", + "local": "true" + }, + { + "name": "Secret2Offset", + "desc": "Offset of the SECRET2 partition", + "type": "int", + "default": "3896", + "local": "true" + }, + { + "name": "Secret2Size", + "desc": "Size of the SECRET2 partition", + "type": "int", + "default": "40", + "local": "true" + }, + { + "name": "FieldEntropyOffset", + "desc": "Offset of FIELD_ENTROPY", + "type": "int", + "default": "3896", + "local": "true" + }, + { + "name": "FieldEntropySize", + "desc": "Size of FIELD_ENTROPY", + "type": "int", + "default": "32", + "local": "true" + }, + { + "name": "Secret2DigestOffset", + "desc": "Offset of SECRET2_DIGEST", + "type": "int", + "default": "3928", + "local": "true" + }, + { + "name": "Secret2DigestSize", + "desc": "Size of SECRET2_DIGEST", + "type": "int", + "default": "8", + "local": "true" + }, + { + "name": "Secret3Offset", + "desc": "Offset of the SECRET3 partition", + "type": "int", + "default": "3936", + "local": "true" + }, + { + "name": "Secret3Size", + "desc": "Size of the SECRET3 partition", + "type": "int", + "default": "72", + "local": "true" + }, + { + "name": "KeyManifestPkHashOffset", + "desc": "Offset of KEY_MANIFEST_PK_HASH", + "type": "int", + "default": "3936", + "local": "true" + }, + { + "name": "KeyManifestPkHashSize", + "desc": "Size of KEY_MANIFEST_PK_HASH", + "type": "int", + "default": "48", + "local": "true" + }, + { + "name": "RmaTokenOffset", + "desc": "Offset of RMA_TOKEN", + "type": "int", + "default": "3984", + "local": "true" + }, + { + "name": "RmaTokenSize", + "desc": "Size of RMA_TOKEN", + "type": "int", + "default": "16", + "local": "true" + }, + { + "name": "Secret3DigestOffset", + "desc": "Offset of SECRET3_DIGEST", + "type": "int", + "default": "4000", + "local": "true" + }, + { + "name": "Secret3DigestSize", + "desc": "Size of SECRET3_DIGEST", + "type": "int", + "default": "8", + "local": "true" + }, + { + "name": "LifeCycleOffset", + "desc": "Offset of the LIFE_CYCLE partition", + "type": "int", + "default": "4008", + "local": "true" + }, + { + "name": "LifeCycleSize", + "desc": "Size of the LIFE_CYCLE partition", + "type": "int", + "default": "88", + "local": "true" + }, + { + "name": "LcTransitionCntOffset", + "desc": "Offset of LC_TRANSITION_CNT", + "type": "int", + "default": "4008", + "local": "true" + }, + { + "name": "LcTransitionCntSize", + "desc": "Size of LC_TRANSITION_CNT", + "type": "int", + "default": "48", + "local": "true" + }, + { + "name": "LcStateOffset", + "desc": "Offset of LC_STATE", + "type": "int", + "default": "4056", + "local": "true" + }, + { + "name": "LcStateSize", + "desc": "Size of LC_STATE", + "type": "int", + "default": "40", + "local": "true" + } + ], + "inter_signal_list": [ + { + "struct": "", + "type": "io", + "name": "otp_ext_voltage_h", + "act": "none", + "default": "'0", + "package": "" + }, + { + "struct": "otp_ast_req", + "type": "uni", + "name": "otp_ast_pwr_seq", + "act": "req", + "default": "'0", + "package": "otp_ctrl_pkg", + "desc": "Power sequencing signals to AST (VDD domain)." + }, + { + "struct": "otp_ast_rsp", + "type": "uni", + "name": "otp_ast_pwr_seq_h", + "act": "rcv", + "default": "'0", + "package": "otp_ctrl_pkg", + "desc": "Power sequencing signals coming from AST (VCC domain)." + }, + { + "struct": "edn", + "type": "req_rsp", + "name": "edn", + "act": "req", + "package": "edn_pkg", + "desc": "Entropy request to the entropy distribution network for LFSR reseeding and ephemeral key derivation." + }, + { + "struct": "pwr_otp", + "type": "req_rsp", + "name": "pwr_otp", + "act": "rsp", + "default": "'0", + "package": "pwrmgr_pkg", + "desc": "Initialization request/acknowledge from/to power manager." + }, + { + "struct": "lc_otp_vendor_test", + "type": "req_rsp", + "name": "lc_otp_vendor_test", + "act": "rsp", + "default": "'0", + "package": "otp_ctrl_pkg", + "desc": "Vendor test control signals from/to the life cycle TAP." + }, + { + "struct": "lc_otp_program", + "type": "req_rsp", + "name": "lc_otp_program", + "act": "rsp", + "default": "'0", + "package": "otp_ctrl_pkg", + "desc": "Life cycle state transition interface." + }, + { + "struct": "otp_lc_data", + "type": "uni", + "name": "otp_lc_data", + "act": "req", + "default": "'0", + "package": "otp_ctrl_pkg", + "desc": "Life cycle state output holding the current life cycle state,\nthe value of the transition counter and the tokens needed for life cycle transitions." + }, + { + "struct": "lc_tx", + "type": "uni", + "name": "lc_escalate_en", + "act": "rcv", + "default": "lc_ctrl_pkg::Off", + "package": "lc_ctrl_pkg", + "desc": "Life cycle escalation enable coming from life cycle controller.\nThis signal moves all FSMs within OTP into the error state." + }, + { + "struct": "lc_tx", + "type": "uni", + "name": "lc_creator_seed_sw_rw_en", + "act": "rcv", + "default": "lc_ctrl_pkg::Off", + "package": "lc_ctrl_pkg", + "desc": "Provision enable qualifier coming from life cycle controller.\nThis signal enables SW read / write access to the RMA_TOKEN and CREATOR_ROOT_KEY_SHARE0 and CREATOR_ROOT_KEY_SHARE1." + }, + { + "struct": "lc_tx", + "type": "uni", + "name": "lc_owner_seed_sw_rw_en", + "act": "rcv", + "default": "lc_ctrl_pkg::Off", + "package": "lc_ctrl_pkg", + "desc": "Provision enable qualifier coming from life cycle controller.\nThis signal enables SW read / write access to the OWNER_SEED." + }, + { + "struct": "lc_tx", + "type": "uni", + "name": "lc_seed_hw_rd_en", + "act": "rcv", + "default": "lc_ctrl_pkg::Off", + "package": "lc_ctrl_pkg", + "desc": "Seed read enable coming from life cycle controller.\nThis signal enables HW read access to the CREATOR_ROOT_KEY_SHARE0 and CREATOR_ROOT_KEY_SHARE1." + }, + { + "struct": "lc_tx", + "type": "uni", + "name": "lc_dft_en", + "act": "rcv", + "default": "lc_ctrl_pkg::Off", + "package": "lc_ctrl_pkg", + "desc": "Test enable qualifier coming from life cycle controller.\nThis signals enables the TL-UL access port to the proprietary OTP IP." + }, + { + "struct": "lc_tx", + "type": "uni", + "name": "lc_check_byp_en", + "act": "rcv", + "default": "lc_ctrl_pkg::Off", + "package": "lc_ctrl_pkg", + "desc": "Life cycle partition check bypass signal.\nThis signal causes the life cycle partition to bypass consistency checks during life cycle state transitions in order to prevent spurious consistency check failures." + }, + { + "struct": "otp_keymgr_key", + "type": "uni", + "name": "otp_keymgr_key", + "act": "req", + "default": "'0", + "package": "otp_ctrl_pkg", + "desc": "Key output to the key manager holding CREATOR_ROOT_KEY_SHARE0 and CREATOR_ROOT_KEY_SHARE1." + }, + { + "struct": "flash_otp_key", + "type": "req_rsp", + "name": "flash_otp_key", + "act": "rsp", + "default": "'0", + "package": "otp_ctrl_pkg", + "desc": "Key derivation interface for FLASH scrambling." + }, + { + "struct": "sram_otp_key", + "width": "4", + "type": "req_rsp", + "name": "sram_otp_key", + "act": "rsp", + "default": "'0", + "package": "otp_ctrl_pkg", + "desc": "Array with key derivation interfaces for SRAM scrambling devices." + }, + { + "struct": "otbn_otp_key", + "type": "req_rsp", + "name": "otbn_otp_key", + "act": "rsp", + "default": "'0", + "package": "otp_ctrl_pkg", + "desc": "Key derivation interface for OTBN scrambling devices." + }, + { + "struct": "otp_broadcast", + "type": "uni", + "name": "otp_broadcast", + "act": "req", + "default": "'0", + "package": "otp_ctrl_part_pkg", + "desc": "Output of the HW partitions with breakout data types." + }, + { + "struct": "ast_obs_ctrl", + "type": "uni", + "name": "obs_ctrl", + "act": "rcv", + "package": "ast_pkg", + "desc": "AST observability control signals." + }, + { + "struct": "logic", + "type": "uni", + "name": "otp_obs", + "act": "req", + "width": "8", + "package": "", + "desc": "AST observability bus." + } + ], + "countermeasures": [ + { + "name": "BUS.INTEGRITY", + "desc": "End-to-end bus integrity scheme." + }, + { + "name": "SECRET.MEM.SCRAMBLE", + "desc": "Secret partitions are scrambled with a full-round PRESENT cipher." + }, + { + "name": "PART.MEM.DIGEST", + "desc": "Integrity of buffered partitions is ensured via a 64bit digest." + }, + { + "name": "DAI.FSM.SPARSE", + "desc": "The direct access interface FSM is sparsely encoded." + }, + { + "name": "KDI.FSM.SPARSE", + "desc": "The key derivation interface FSM is sparsely encoded." + }, + { + "name": "LCI.FSM.SPARSE", + "desc": "The life cycle interface FSM is sparsely encoded." + }, + { + "name": "PART.FSM.SPARSE", + "desc": "The partition FSMs are sparsely encoded." + }, + { + "name": "SCRMBL.FSM.SPARSE", + "desc": "The scramble datapath FSM is sparsely encoded." + }, + { + "name": "TIMER.FSM.SPARSE", + "desc": "The background check timer FSM is sparsely encoded." + }, + { + "name": "DAI.CTR.REDUN", + "desc": "The direct access interface address counter employs a cross-counter implementation." + }, + { + "name": "KDI_SEED.CTR.REDUN", + "desc": "The key derivation interface counter employs a cross-counter implementation." + }, + { + "name": "KDI_ENTROPY.CTR.REDUN", + "desc": "The key derivation entropy counter employs a cross-counter implementation." + }, + { + "name": "LCI.CTR.REDUN", + "desc": "The life cycle interface address counter employs a cross-counter implementation." + }, + { + "name": "PART.CTR.REDUN", + "desc": "The address counter of buffered partitions employs a cross-counter implementation." + }, + { + "name": "SCRMBL.CTR.REDUN", + "desc": "The srambling datapath counter employs a cross-counter implementation." + }, + { + "name": "TIMER_INTEG.CTR.REDUN", + "desc": "The background integrity check timer employs a duplicated counter implementation." + }, + { + "name": "TIMER_CNSTY.CTR.REDUN", + "desc": "The background consistency check timer employs a duplicated counter implementation." + }, + { + "name": "TIMER.LFSR.REDUN", + "desc": "The background check LFSR is duplicated." + }, + { + "name": "DAI.FSM.LOCAL_ESC", + "desc": "The direct access interface FSM is moved into an invalid state upon local escalation." + }, + { + "name": "LCI.FSM.LOCAL_ESC", + "desc": "The life cycle interface FSM is moved into an invalid state upon local escalation." + }, + { + "name": "KDI.FSM.LOCAL_ESC", + "desc": "The key derivation interface FSM is moved into an invalid state upon local escalation." + }, + { + "name": "PART.FSM.LOCAL_ESC", + "desc": "The partition FSMs are moved into an invalid state upon local escalation." + }, + { + "name": "SCRMBL.FSM.LOCAL_ESC", + "desc": "The scramble datapath FSM is moved into an invalid state upon local escalation." + }, + { + "name": "TIMER.FSM.LOCAL_ESC", + "desc": "The background check timer FSM is moved into an invalid state upon local escalation." + }, + { + "name": "DAI.FSM.GLOBAL_ESC", + "desc": "The direct access interface FSM is moved into an invalid state upon global escalation via life cycle." + }, + { + "name": "LCI.FSM.GLOBAL_ESC", + "desc": "The life cycle interface FSM is moved into an invalid state upon global escalation via life cycle." + }, + { + "name": "KDI.FSM.GLOBAL_ESC", + "desc": "The key derivation interface FSM is moved into an invalid state upon global escalation via life cycle." + }, + { + "name": "PART.FSM.GLOBAL_ESC", + "desc": "The partition FSMs are moved into an invalid state upon global escalation via life cycle." + }, + { + "name": "SCRMBL.FSM.GLOBAL_ESC", + "desc": "The scramble datapath FSM is moved into an invalid state upon global escalation via life cycle." + }, + { + "name": "TIMER.FSM.GLOBAL_ESC", + "desc": "The background check timer FSM is moved into an invalid state upon global escalation via life cycle." + }, + { + "name": "PART.DATA_REG.INTEGRITY", + "desc": "All partition buffer registers are protected with ECC on 64bit blocks." + }, + { + "name": "PART.DATA_REG.BKGN_CHK", + "desc": "The digest of buffered partitions is recomputed and checked at pseudorandom intervals in the background." + }, + { + "name": "PART.MEM.REGREN", + "desc": "Unbuffered ('software') partitions can be read-locked via a CSR until the next system reset." + }, + { + "name": "PART.MEM.SW_UNREADABLE", + "desc": "Secret buffered partitions become unreadable to software once they are locked via the digest." + }, + { + "name": "PART.MEM.SW_UNWRITABLE", + "desc": "All partitions become unwritable by software once they are locked via the digest." + }, + { + "name": "LC_PART.MEM.SW_NOACCESS", + "desc": "The life cycle partition is not directly readable nor writable via software." + }, + { + "name": "ACCESS.CTRL.MUBI", + "desc": "The access control signals going from the partitions to the DAI are MUBI encoded." + }, + { + "name": "TOKEN_VALID.CTRL.MUBI", + "desc": "The token valid signals going to the life cycle controller are MUBI encoded." + }, + { + "name": "LC_CTRL.INTERSIG.MUBI", + "desc": "The life cycle control signals are multibit encoded." + }, + { + "name": "TEST.BUS.LC_GATED", + "desc": "Prevent access to test signals and the OTP backdoor interface in non-test lifecycle states." + }, + { + "name": "TEST_TL_LC_GATE.FSM.SPARSE", + "desc": "The control FSM inside the TL-UL gating primitive is sparsely encoded." + }, + { + "name": "DIRECT_ACCESS.CONFIG.REGWEN", + "desc": "The direct access CSRs are REGWEN protected." + }, + { + "name": "CHECK_TRIGGER.CONFIG.REGWEN", + "desc": "The check trigger CSR is REGWEN protected." + }, + { + "name": "CHECK.CONFIG.REGWEN", + "desc": "The check CSR is REGWEN protected." + }, + { + "name": "MACRO.MEM.INTEGRITY", + "desc": " The OTP macro employs a vendor-specific integrity scheme at the granularity of the native 16bit OTP words.\n The scheme is able to at least detect single bit errors.\n " + }, + { + "name": "MACRO.MEM.CM", + "desc": "The OTP macro may contain additional vendor-specific countermeasures." + } + ], + "features": [ + { + "name": "OTP_CTRL.PARTITION.VENDOR_TEST", + "desc": "Vendor test partition is used for OTP programming smoke check during manufacturing flow.\nIn this partition, ECC uncorrectable errors will not lead to fatal errors and alerts.\nInstead the error will be reported as correctable ECC error." + }, + { + "name": "OTP_CTRL.PARTITION.CREATOR_SW_CFG", + "desc": "During calibration stage, various parameters (clock, voltage, and timing sources) are calibrated and recorded to CREATOR_SW_CFG partition." + }, + { + "name": "OTP_CTRL.INIT", + "desc": "When power is up, OTP controller reads devices status.\nAfter all reads complete, the controller performs integrity check on the HW_CFG* and SECRET partitions.\nOnce all integrity checks are complete, the controller marks outputs as valid." + }, + { + "name": "OTP_CTRL.PROGRAM", + "desc": "All other partitions except life cycle partition are programmed through DAI interface.\nAnd once non-zero digest is programmed to these partition, no further write access is allowed.\nLife cycle partition is programmed by LC_CTRL." + }, + { + "name": "OTP_CTRL.PARTITION.SECRET0", + "desc": "Obfuscated UDS Seed" + }, + { + "name": "OTP_CTRL.PARTITION.SECRET1", + "desc": "Obfuscated Field Entropy" + }, + { + "name": "OTP_CTRL.PARTITION.LIFE_CYCLE", + "desc": "LC state, LC transition count.\nThis feature is owned by the LC_CTRL and cannot be tested well through the OTP_CTRL CSR interface." + }, + { + "name": "OTP_CTRL.PARTITIONS_FEATURE.READ_LOCK", + "desc": "Following partitions can be read lockable by CSR.\n - VENDOR_TEST\n - CREATOR_SW_CFG\n Following partitions can be read lockable by writing digest.\n - SECRET0\n - SECRET1\nAll read attempt to these partitions after read is locked will trigger AccessError (recoverable)." + }, + { + "name": "OTP_CTRL.PARTITIONS_FEATURE.WRITE_LOCK", + "desc": "All partitions except LIFE_CYCLE can be write lockable by writing digest." + }, + { + "name": "OTP_CTRL.ERROR_HANDLING.RECOVERABLE", + "desc": "Recoverable error is created when unauthorized access atempt are detected via dai interface." + }, + { + "name": "OTP_CTRL.ERROR_HANDLING.FATAL", + "desc": "Unrecoverable errors are created for uncorrectable ecc error, otp macro malfunction and unauthorized access via lc_ctrl." + }, + { + "name": "OTP_CTRL.BACKGROUND_CHECK.CHECK_TIMEOUT", + "desc": "Timeout value for the integrity and consistency checks." + }, + { + "name": "OTP_CTRL.BACKGROUND_CHECK.INTEGRITY_CHECK_PERIOD", + "desc": "The interval which the digest of the partition is recomputed to check integrity of locked partition." + }, + { + "name": "OTP_CTRL.BACKGROUND_CHECK.CONSISTENCY_CHECK_PERIOD", + "desc": "Re-read period of the buffer registers to ensure data is matched with the associated OTP partition." + } + ], + "regwidth": "32", + "registers": [ + { + "name": "STATUS", + "desc": "OTP status register.", + "swaccess": "ro", + "hwaccess": "hwo", + "hwext": "true", + "bits": "31:0", + "resval": 0, + "tags": [ + "excl:CsrAllTests:CsrExclCheck" + ], + "fields": [ + { + "bits": "0", + "name": "VENDOR_TEST_ERROR", + "desc": "Set to 1 if an error occurred in this partition.\nIf set to 1, SW should check the !!ERR_CODE register at the corresponding index." + }, + { + "bits": "1", + "name": "NON_SECRET_FUSES_ERROR", + "desc": "Set to 1 if an error occurred in this partition.\nIf set to 1, SW should check the !!ERR_CODE register at the corresponding index." + }, + { + "bits": "2", + "name": "SECRET0_ERROR", + "desc": "Set to 1 if an error occurred in this partition.\nIf set to 1, SW should check the !!ERR_CODE register at the corresponding index." + }, + { + "bits": "3", + "name": "SECRET1_ERROR", + "desc": "Set to 1 if an error occurred in this partition.\nIf set to 1, SW should check the !!ERR_CODE register at the corresponding index." + }, + { + "bits": "4", + "name": "SECRET2_ERROR", + "desc": "Set to 1 if an error occurred in this partition.\nIf set to 1, SW should check the !!ERR_CODE register at the corresponding index." + }, + { + "bits": "5", + "name": "SECRET3_ERROR", + "desc": "Set to 1 if an error occurred in this partition.\nIf set to 1, SW should check the !!ERR_CODE register at the corresponding index." + }, + { + "bits": "6", + "name": "LIFE_CYCLE_ERROR", + "desc": "Set to 1 if an error occurred in this partition.\nIf set to 1, SW should check the !!ERR_CODE register at the corresponding index." + }, + { + "bits": "7", + "name": "DAI_ERROR", + "desc": "Set to 1 if an error occurred in the DAI.\nIf set to 1, SW should check the !!ERR_CODE register at the corresponding index." + }, + { + "bits": "8", + "name": "LCI_ERROR", + "desc": "Set to 1 if an error occurred in the LCI.\nIf set to 1, SW should check the !!ERR_CODE register at the corresponding index." + }, + { + "bits": "9", + "name": "TIMEOUT_ERROR", + "desc": "Set to 1 if an integrity or consistency check times out.\nThis raises an fatal_check_error alert and is an unrecoverable error condition." + }, + { + "bits": "10", + "name": "LFSR_FSM_ERROR", + "desc": "Set to 1 if the LFSR timer FSM has reached an invalid state.\nThis raises an fatal_check_error alert and is an unrecoverable error condition." + }, + { + "bits": "11", + "name": "SCRAMBLING_FSM_ERROR", + "desc": "Set to 1 if the scrambling datapath FSM has reached an invalid state.\nThis raises an fatal_check_error alert and is an unrecoverable error condition." + }, + { + "bits": "12", + "name": "KEY_DERIV_FSM_ERROR", + "desc": "Set to 1 if the key derivation FSM has reached an invalid state.\nThis raises an fatal_check_error alert and is an unrecoverable error condition." + }, + { + "bits": "13", + "name": "BUS_INTEG_ERROR", + "desc": "This bit is set to 1 if a fatal bus integrity fault is detected.\nThis error triggers a fatal_bus_integ_error alert." + }, + { + "bits": "14", + "name": "DAI_IDLE", + "desc": "Set to 1 if the DAI is idle and ready to accept commands." + }, + { + "bits": "15", + "name": "CHECK_PENDING", + "desc": "Set to 1 if an integrity or consistency check triggered by the LFSR timer or via !!CHECK_TRIGGER is pending." + } + ] + }, + { + "multireg": { + "name": "ERR_CODE", + "desc": "This register holds information about error conditions that occurred in the agents\ninteracting with the OTP macro via the internal bus. The error codes should be checked\nif the partitions, DAI or LCI flag an error in the !!STATUS register, or when an\n!!INTR_STATE.otp_error has been triggered. Note that all errors trigger an otp_error\ninterrupt, and in addition some errors may trigger either an fatal_macro_error or an\nfatal_check_error alert.", + "count": "NumErrorEntries", + "swaccess": "ro", + "hwaccess": "hwo", + "hwext": "true", + "cname": "AGENT", + "compact": "false", + "resval": 0, + "tags": [ + "excl:CsrAllTests:CsrExclCheck" + ], + "fields": [ + { + "bits": "2:0", + "enum": [ + { + "value": "0", + "name": "NO_ERROR", + "desc": "No error condition has occurred." + }, + { + "value": "1", + "name": "MACRO_ERROR", + "desc": "Returned if the OTP macro command was invalid or did not complete successfully\ndue to a macro malfunction.\nThis error should never occur during normal operation and is not recoverable.\nThis error triggers an fatal_macro_error alert." + }, + { + "value": "2", + "name": "MACRO_ECC_CORR_ERROR", + "desc": "A correctable ECC error has occured during an OTP read operation.\nThe corresponding controller automatically recovers from this error when\nissuing a new command." + }, + { + "value": "3", + "name": "MACRO_ECC_UNCORR_ERROR", + "desc": "An uncorrectable ECC error has occurred during an OTP read operation.\nThis error should never occur during normal operation and is not recoverable.\nIf this error is present this may be a sign that the device is malfunctioning.\nThis error triggers an fatal_macro_error alert." + }, + { + "value": "4", + "name": "MACRO_WRITE_BLANK_ERROR", + "desc": "This error is returned if a programming operation attempted to clear a bit that has previously been programmed to 1.\nThe corresponding controller automatically recovers from this error when issuing a new command.\n\nNote however that the affected OTP word may be left in an inconsistent state if this error occurs.\nThis can cause several issues when the word is accessed again (either as part of a regular read operation, as part of the readout at boot, or as part of a background check).\n\nIt is important that SW ensures that each word is only written once, since this can render the device useless." + }, + { + "value": "5", + "name": "ACCESS_ERROR", + "desc": "This error indicates that a locked memory region has been accessed.\nThe corresponding controller automatically recovers from this error when issuing a new command." + }, + { + "value": "6", + "name": "CHECK_FAIL_ERROR", + "desc": "An ECC, integrity or consistency mismatch has been detected in the buffer registers.\nThis error should never occur during normal operation and is not recoverable.\nThis error triggers an fatal_check_error alert." + }, + { + "value": "7", + "name": "FSM_STATE_ERROR", + "desc": "The FSM of the corresponding controller has reached an invalid state, or the FSM has\nbeen moved into a terminal error state due to an escalation action via lc_escalate_en_i.\nThis error should never occur during normal operation and is not recoverable.\nIf this error is present, this is a sign that the device has fallen victim to\nan invasive attack. This error triggers an fatal_check_error alert." + } + ] + } + ] + } + }, + { + "name": "DIRECT_ACCESS_REGWEN", + "desc": "Register write enable for all direct access interface registers.", + "swaccess": "rw0c", + "hwaccess": "hrw", + "hwext": "true", + "hwqe": "true", + "tags": [ + "excl:CsrNonInitTests:CsrExclCheck" + ], + "fields": [ + { + "bits": "0", + + "desc": "This bit controls whether the DAI registers can be written.\nWrite 0 to it in order to clear the bit.\n\nNote that the hardware also modulates this bit and sets it to 0 temporarily\nduring an OTP operation such that the corresponding address and data registers\ncannot be modified while an operation is pending. The !!DAI_IDLE status bit\nwill also be set to 0 in such a case.", + "resval": 1 + } + ] + }, + { + "name": "DIRECT_ACCESS_CMD", + "desc": "Command register for direct accesses.", + "swaccess": "r0w1c", + "hwaccess": "hro", + "hwqe": "true", + "hwext": "true", + "resval": 0, + "regwen": "DIRECT_ACCESS_REGWEN", + "tags": [ + "excl:CsrNonInitTests:CsrExclWrite" + ], + "fields": [ + { + "bits": "0", + "name": "RD", + "desc": "Initiates a readout sequence that reads the location specified\nby !!DIRECT_ACCESS_ADDRESS. The command places the data read into\n!!DIRECT_ACCESS_RDATA_0 and !!DIRECT_ACCESS_RDATA_1 (for 64bit partitions)." + }, + { + "bits": "1", + "name": "WR", + "desc": "Initiates a programming sequence that writes the data in !!DIRECT_ACCESS_WDATA_0\nand !!DIRECT_ACCESS_WDATA_1 (for 64bit partitions) to the location specified by\n!!DIRECT_ACCESS_ADDRESS." + }, + { + "bits": "2", + "name": "DIGEST", + "desc": "Initiates the digest calculation and locking sequence for the partition specified by\n!!DIRECT_ACCESS_ADDRESS." + } + ] + }, + { + "name": "DIRECT_ACCESS_ADDRESS", + "desc": "Address register for direct accesses.", + "swaccess": "rw", + "hwaccess": "hro", + "hwqe": "false", + "resval": 0, + "regwen": "DIRECT_ACCESS_REGWEN", + "tags": [ + "excl:CsrNonInitTests:CsrExclCheck" + ], + "fields": [ + { + "bits": "OtpByteAddrWidth-1:0", + "desc": "This is the address for the OTP word to be read or written through\nthe direct access interface. Note that the address is aligned to the access size\ninternally, hence bits 1:0 are ignored for 32bit accesses, and bits 2:0 are ignored\nfor 64bit accesses.\n\nFor the digest calculation command, set this register to the partition base offset." + } + ] + }, + { + "multireg": { + "name": "DIRECT_ACCESS_WDATA", + "desc": "Write data for direct accesses.\n Hardware automatically determines the access granule (32bit or 64bit) based on which\n partition is being written to.\n ", + "count": "NumDaiWords", + "swaccess": "rw", + "hwaccess": "hro", + "hwqe": "false", + "regwen": "DIRECT_ACCESS_REGWEN", + "cname": "WORD", + "resval": 0, + "tags": [ + "excl:CsrAllTests:CsrExclCheck" + ], + "fields": [ + { + "bits": "31:0" + } + ] + } + }, + { + "multireg": { + "name": "DIRECT_ACCESS_RDATA", + "desc": "Read data for direct accesses.\n Hardware automatically determines the access granule (32bit or 64bit) based on which\n partition is read from.\n ", + "count": "NumDaiWords", + "swaccess": "ro", + "hwaccess": "hwo", + "hwext": "true", + "cname": "WORD", + "resval": 0, + "fields": [ + { + "bits": "31:0" + } + ] + } + }, + { + "name": "CHECK_TRIGGER_REGWEN", + "desc": "Register write enable for !!CHECK_TRIGGER.", + "swaccess": "rw0c", + "hwaccess": "none", + "fields": [ + { + "bits": "0", + "desc": "When cleared to 0, the !!CHECK_TRIGGER register cannot be written anymore.\nWrite 0 to clear this bit.", + "resval": 1 + } + ] + }, + { + "name": "CHECK_TRIGGER", + "desc": "Command register for direct accesses.", + "swaccess": "r0w1c", + "hwaccess": "hro", + "hwqe": "true", + "hwext": "true", + "resval": 0, + "regwen": "CHECK_TRIGGER_REGWEN", + "fields": [ + { + "bits": "0", + "name": "INTEGRITY", + "desc": "Writing 1 to this bit triggers an integrity check. SW should monitor !!STATUS.CHECK_PENDING\nand wait until the check has been completed. If there are any errors, those will be flagged\nin the !!STATUS and !!ERR_CODE registers, and via the interrupts and alerts." + }, + { + "bits": "1", + "name": "CONSISTENCY", + "desc": "Writing 1 to this bit triggers a consistency check. SW should monitor !!STATUS.CHECK_PENDING\nand wait until the check has been completed. If there are any errors, those will be flagged\nin the !!STATUS and !!ERR_CODE registers, and via interrupts and alerts." + } + ] + }, + { + "name": "CHECK_REGWEN", + "desc": "Register write enable for !!INTEGRITY_CHECK_PERIOD and !!CONSISTENCY_CHECK_PERIOD.", + "swaccess": "rw0c", + "hwaccess": "none", + "fields": [ + { + "bits": "0", + "desc": "When cleared to 0, !!INTEGRITY_CHECK_PERIOD and !!CONSISTENCY_CHECK_PERIOD registers cannot be written anymore.\nWrite 0 to clear this bit.", + "resval": 1 + } + ] + }, + { + "name": "CHECK_TIMEOUT", + "desc": "Timeout value for the integrity and consistency checks.", + "swaccess": "rw", + "hwaccess": "hro", + "regwen": "CHECK_REGWEN", + "tags": [ + "excl:CsrAllTests:CsrExclWrite" + ], + "fields": [ + { + "bits": "31:0", + "desc": "Timeout value in cycles for the for the integrity and consistency checks. If an integrity or consistency\ncheck does not complete within the timeout window, an error will be flagged in the !!STATUS register,\nan otp_error interrupt will be raised, and an fatal_check_error alert will be sent out. The timeout should\nbe set to a large value to stay on the safe side. The maximum check time can be upper bounded by the\nnumber of cycles it takes to readout, scramble and digest the entire OTP array. Since this amounts to\nroughly 25k cycles, it is recommended to set this value to at least 100'000 cycles in order to stay on the\nsafe side. A value of zero disables the timeout mechanism (default).", + "resval": 0 + } + ] + }, + { + "name": "INTEGRITY_CHECK_PERIOD", + "desc": "This value specifies the maximum period that can be generated pseudo-randomly.\nOnly applies to the HW_CFG* and SECRET* partitions once they are locked.", + "swaccess": "rw", + "hwaccess": "hro", + "regwen": "CHECK_REGWEN", + "fields": [ + { + "bits": "31:0", + "desc": "The pseudo-random period is generated using a 40bit LFSR internally, and this register defines\nthe bit mask to be applied to the LFSR output in order to limit its range. The value of this\nregister is left shifted by 8bits and the lower bits are set to 8'hFF in order to form the 40bit mask.\nA recommended value is 0x3_FFFF, corresponding to a maximum period of ~2.8s at 24MHz.\nA value of zero disables the timer (default). Note that a one-off check can always be triggered via\n!!CHECK_TRIGGER.INTEGRITY.", + "resval": "0" + } + ] + }, + { + "name": "CONSISTENCY_CHECK_PERIOD", + "desc": "This value specifies the maximum period that can be generated pseudo-randomly.\nThis applies to the LIFE_CYCLE partition and the HW_CFG* and SECRET* partitions once they are locked.", + "swaccess": "rw", + "hwaccess": "hro", + "regwen": "CHECK_REGWEN", + "fields": [ + { + "bits": "31:0", + "desc": "The pseudo-random period is generated using a 40bit LFSR internally, and this register defines\nthe bit mask to be applied to the LFSR output in order to limit its range. The value of this\nregister is left shifted by 8bits and the lower bits are set to 8'hFF in order to form the 40bit mask.\nA recommended value is 0x3FF_FFFF, corresponding to a maximum period of ~716s at 24MHz.\nA value of zero disables the timer (default). Note that a one-off check can always be triggered via\n!!CHECK_TRIGGER.CONSISTENCY.", + "resval": "0" + } + ] + }, + { + "name": "VENDOR_TEST_READ_LOCK", + "desc": "Runtime read lock for the VENDOR_TEST partition.", + "swaccess": "rw0c", + "hwaccess": "hro", + "regwen": "DIRECT_ACCESS_REGWEN", + "tags": [ + "excl:CsrNonInitTests:CsrExclWrite" + ], + "fields": [ + { + "bits": "0", + "desc": "When cleared to 0, read access to the VENDOR_TEST partition is locked.\nWrite 0 to clear this bit.", + "resval": 1 + } + ] + }, + { + "name": "NON_SECRET_FUSES_READ_LOCK", + "desc": "Runtime read lock for the NON_SECRET_FUSES partition.", + "swaccess": "rw0c", + "hwaccess": "hro", + "regwen": "DIRECT_ACCESS_REGWEN", + "tags": [ + "excl:CsrNonInitTests:CsrExclWrite" + ], + "fields": [ + { + "bits": "0", + "desc": "When cleared to 0, read access to the NON_SECRET_FUSES partition is locked.\nWrite 0 to clear this bit.", + "resval": 1 + } + ] + }, + { + "multireg": { + "name": "VENDOR_TEST_DIGEST", + "desc": " Integrity digest for the VENDOR_TEST partition.\n The integrity digest is 0 by default. Software must write this\n digest value via the direct access interface in order to lock the partition.\n After a reset, write access to the VENDOR_TEST partition is locked and\n the digest becomes visible in this CSR.\n ", + "count": "NumDigestWords", + "swaccess": "ro", + "hwaccess": "hwo", + "hwext": "true", + "cname": "WORD", + "resval": 0, + "tags": [ + "excl:CsrAllTests:CsrExclCheck" + ], + "fields": [ + { + "bits": "31:0" + } + ] + } + }, + { + "multireg": { + "name": "NON_SECRET_FUSES_DIGEST", + "desc": " Integrity digest for the NON_SECRET_FUSES partition.\n The integrity digest is 0 by default. Software must write this\n digest value via the direct access interface in order to lock the partition.\n After a reset, write access to the NON_SECRET_FUSES partition is locked and\n the digest becomes visible in this CSR.\n ", + "count": "NumDigestWords", + "swaccess": "ro", + "hwaccess": "hwo", + "hwext": "true", + "cname": "WORD", + "resval": 0, + "tags": [ + "excl:CsrAllTests:CsrExclCheck" + ], + "fields": [ + { + "bits": "31:0" + } + ] + } + }, + { + "multireg": { + "name": "SECRET0_DIGEST", + "desc": " Integrity digest for the SECRET0 partition.\n The integrity digest is 0 by default. The digest calculation can be triggered via the !!DIRECT_ACCESS_CMD.\n After a reset, the digest then becomes visible in this CSR, and the corresponding partition becomes write-locked.\n ", + "count": "NumDigestWords", + "swaccess": "ro", + "hwaccess": "hwo", + "hwext": "true", + "cname": "WORD", + "resval": 0, + "tags": [ + "excl:CsrAllTests:CsrExclCheck" + ], + "fields": [ + { + "bits": "31:0" + } + ] + } + }, + { + "multireg": { + "name": "SECRET1_DIGEST", + "desc": " Integrity digest for the SECRET1 partition.\n The integrity digest is 0 by default. The digest calculation can be triggered via the !!DIRECT_ACCESS_CMD.\n After a reset, the digest then becomes visible in this CSR, and the corresponding partition becomes write-locked.\n ", + "count": "NumDigestWords", + "swaccess": "ro", + "hwaccess": "hwo", + "hwext": "true", + "cname": "WORD", + "resval": 0, + "tags": [ + "excl:CsrAllTests:CsrExclCheck" + ], + "fields": [ + { + "bits": "31:0" + } + ] + } + }, + { + "multireg": { + "name": "SECRET2_DIGEST", + "desc": " Integrity digest for the SECRET2 partition.\n The integrity digest is 0 by default. The digest calculation can be triggered via the !!DIRECT_ACCESS_CMD.\n After a reset, the digest then becomes visible in this CSR, and the corresponding partition becomes write-locked.\n ", + "count": "NumDigestWords", + "swaccess": "ro", + "hwaccess": "hwo", + "hwext": "true", + "cname": "WORD", + "resval": 0, + "tags": [ + "excl:CsrAllTests:CsrExclCheck" + ], + "fields": [ + { + "bits": "31:0" + } + ] + } + }, + { + "multireg": { + "name": "SECRET3_DIGEST", + "desc": " Integrity digest for the SECRET3 partition.\n The integrity digest is 0 by default. The digest calculation can be triggered via the !!DIRECT_ACCESS_CMD.\n After a reset, the digest then becomes visible in this CSR, and the corresponding partition becomes write-locked.\n ", + "count": "NumDigestWords", + "swaccess": "ro", + "hwaccess": "hwo", + "hwext": "true", + "cname": "WORD", + "resval": 0, + "tags": [ + "excl:CsrAllTests:CsrExclCheck" + ], + "fields": [ + { + "bits": "31:0" + } + ] + } + }, + { + "skipto": "0x1000" + }, + { + "window": { + "name": "SW_CFG_WINDOW", + "items": "NumSwCfgWindowWords", + "swaccess": "ro", + "desc": "Any read to this window directly maps to the corresponding offset in the creator and owner software\nconfig partitions, and triggers an OTP readout of the bytes requested. Note that the transaction\nwill block until OTP readout has completed." + } + }, + + { + "name": "CSR0", + "desc": "", + "swaccess": "rw", + "hwaccess": "hro", + "hwext": "false", + "hwqe": "false", + "fields": [ + { + "bits": "0", + "name": "field0", + "desc": "", + "resval": "0x0" + }, + { + "bits": "1", + "name": "field1", + "desc": "", + "resval": "0x0" + }, + { + "bits": "2", + "name": "field2", + "desc": "", + "resval": "0x0" + }, + { + "bits": "13:4", + "name": "field3", + "desc": "", + "resval": "0x0" + }, + { + "bits": "26:16", + "name": "field4", + "desc": "", + "resval": "0x0" + } + ] + }, + { + "name": "CSR1", + "desc": "", + "swaccess": "rw", + "hwaccess": "hro", + "hwext": "false", + "hwqe": "false", + "fields": [ + { + "bits": "6:0", + "name": "field0", + "desc": "", + "resval": "0x0" + }, + { + "bits": "7:7", + "name": "field1", + "desc": "", + "resval": "0x0" + }, + { + "bits": "14:8", + "name": "field2", + "desc": "", + "resval": "0x0" + }, + { + "bits": "15:15", + "name": "field3", + "desc": "", + "resval": "0x0" + }, + { + "bits": "31:16", + "name": "field4", + "desc": "", + "resval": "0x0" + } + ] + }, + { + "name": "CSR2", + "desc": "", + "swaccess": "rw", + "hwaccess": "hro", + "hwext": "false", + "hwqe": "false", + "fields": [ + { + "bits": "0", + "name": "field0", + "desc": "", + "resval": "0x0" + } + ] + }, + { + "name": "CSR3", + "desc": "", + "swaccess": "rw", + "hwaccess": "hrw", + "hwext": "false", + "hwqe": "false", + "fields": [ + { + "bits": "2:0", + "name": "field0", + "desc": "", + "swaccess": "rw1c", + "resval": "0x0" + }, + { + "bits": "13:4", + "name": "field1", + "desc": "", + "swaccess": "rw1c", + "resval": "0x0" + }, + { + "bits": "16", + "name": "field2", + "desc": "", + "swaccess": "rw1c", + "resval": "0x0" + }, + { + "bits": "17", + "name": "field3", + "desc": "", + "swaccess": "ro", + "resval": "0x0" + }, + { + "bits": "18", + "name": "field4", + "desc": "", + "swaccess": "ro", + "resval": "0x0" + }, + { + "bits": "19", + "name": "field5", + "desc": "", + "swaccess": "ro", + "resval": "0x0" + }, + { + "bits": "20", + "name": "field6", + "desc": "", + "swaccess": "ro", + "resval": "0x0" + }, + { + "bits": "21", + "name": "field7", + "desc": "", + "swaccess": "ro", + "resval": "0x0" + }, + { + "bits": "22", + "name": "field8", + "desc": "", + "swaccess": "ro", + "resval": "0x0" + } + ] + }, + { + "name": "CSR4", + "desc": "", + "swaccess": "rw", + "hwaccess": "hro", + "hwext": "false", + "hwqe": "false", + "fields": [ + { + "bits": "9:0", + "name": "field0", + "desc": "", + "resval": "0x0" + }, + { + "bits": "12", + "name": "field1", + "desc": "", + "resval": "0x0" + }, + { + "bits": "13", + "name": "field2", + "desc": "", + "resval": "0x0" + }, + { + "bits": "14", + "name": "field3", + "desc": "", + "resval": "0x0" + } + ] + }, + { + "name": "CSR5", + "desc": "", + "swaccess": "rw", + "hwaccess": "hrw", + "hwext": "false", + "hwqe": "false", + "fields": [ + { + "bits": "5:0", + "name": "field0", + "desc": "", + "swaccess": "rw", + "resval": "0x0" + }, + { + "bits": "7:6", + "name": "field1", + "desc": "", + "swaccess": "rw", + "resval": "0x0" + }, + { + "bits": "8", + "name": "field2", + "desc": "", + "swaccess": "ro", + "resval": "0x0" + }, + { + "bits": "11:9", + "name": "field3", + "desc": "", + "swaccess": "ro", + "resval": "0x0" + }, + { + "bits": "12", + "name": "field4", + "desc": "", + "swaccess": "ro", + "resval": "0x0" + }, + { + "bits": "13", + "name": "field5", + "desc": "", + "swaccess": "ro", + "resval": "0x0" + }, + { + "bits": "31:16", + "name": "field6", + "desc": "", + "swaccess": "rw", + "resval": "0x0" + } + ] + }, + { + "name": "CSR6", + "desc": "", + "swaccess": "rw", + "hwaccess": "hro", + "hwext": "false", + "hwqe": "false", + "fields": [ + { + "bits": "9:0", + "name": "field0", + "desc": "", + "resval": "0x0" + }, + { + "bits": "11", + "name": "field1", + "desc": "", + "swaccess": "rw", + "resval": "0x0" + }, + { + "bits": "12", + "name": "field2", + "desc": "", + "swaccess": "rw", + "resval": "0x0" + }, + { + "bits": "31:16", + "name": "field3", + "desc": "", + "resval": "0x0" + } + ] + }, + { + "name": "CSR7", + "desc": "", + "swaccess": "ro", + "hwaccess": "hrw", + "hwext": "false", + "hwqe": "false", + "fields": [ + { + "bits": "5:0", + "name": "field0", + "desc": "", + "swaccess": "ro", + "resval": "0x0" + }, + { + "bits": "10:8", + "name": "field1", + "desc": "", + "swaccess": "ro", + "resval": "0x0" + }, + { + "bits": "14", + "name": "field2", + "desc": "", + "swaccess": "ro", + "resval": "0x0" + }, + { + "bits": "15", + "name": "field3", + "desc": "", + "swaccess": "ro", + "resval": "0x0" + } + ] + } + ] +} diff --git a/src/fuse_ctrl/data/otp_ctrl_if.sv.tpl b/src/fuse_ctrl/data/otp_ctrl_if.sv.tpl new file mode 100755 index 0000000..4fac06b --- /dev/null +++ b/src/fuse_ctrl/data/otp_ctrl_if.sv.tpl @@ -0,0 +1,350 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +${gen_comment} +<% +from topgen.lib import Name +unbuf_parts_with_digest = [part for part in otp_mmap.config["partitions"] if + part["variant"] == "Unbuffered" and + (part["sw_digest"] or part["hw_digest"])] +parts_without_lc = [part for part in otp_mmap.config["partitions"] if + part["variant"] in ["Buffered", "Unbuffered"]] +buf_parts_without_lc = [part for part in otp_mmap.config["partitions"] if + part["variant"] == "Buffered"] +%>\ +// This interface collect the broadcast output data from OTP, +// and drive input requests coming into OTP. +`define ECC_REG_PATH gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec + +// This only supports buffered partitions. +`define BUF_PART_OTP_CMD_PATH(i) ${"\\"} + tb.dut.gen_partitions[``i``].gen_buffered.u_part_buf.otp_cmd_o + +`define LC_PART_OTP_CMD_PATH ${"\\"} + tb.dut.gen_partitions[LifeCycleIdx].gen_lifecycle.u_part_buf.otp_cmd_o + +`define FORCE_OTP_PART_LOCK_WITH_RAND_NON_MUBI_VAL(i) ${"\\"} + if (forced_part_access_sel[``i``].read_lock) begin ${"\\"} + force tb.dut.part_access[``i``].read_lock = get_rand_mubi8_val(.t_weight(0), .f_weight(0)); ${"\\"} + force tb.dut.part_access_dai[``i``].read_lock = get_rand_mubi8_val(.t_weight(0), .f_weight(0)); ${"\\"} + end ${"\\"} + if (forced_part_access_sel[``i``].write_lock) begin ${"\\"} + force tb.dut.part_access[``i``].write_lock = get_rand_mubi8_val(.t_weight(0), .f_weight(0)); ${"\\"} + force tb.dut.part_access_dai[``i``].write_lock = get_rand_mubi8_val(.t_weight(0), .f_weight(0)); ${"\\"} + end + +`ifndef PRIM_GENERIC_OTP_PATH + `define PRIM_GENERIC_OTP_PATH${"\\"} + tb.dut.u_otp +`endif + +`ifndef PRIM_GENERIC_OTP_CMD_I_PATH + `define PRIM_GENERIC_OTP_CMD_I_PATH ${"\\"} + `PRIM_GENERIC_OTP_PATH.gen_generic.u_impl_generic.cmd_i +`endif + +interface otp_ctrl_if(input clk_i, input rst_ni); + import uvm_pkg::*; + import otp_ctrl_env_pkg::*; + import otp_ctrl_pkg::*; + import otp_ctrl_reg_pkg::*; + import otp_ctrl_part_pkg::*; + import cip_base_pkg::*; + + // Output from DUT + otp_broadcast_t otp_broadcast_o; + otp_keymgr_key_t keymgr_key_o; + otp_lc_data_t lc_data_o; + logic pwr_otp_done_o, pwr_otp_idle_o; + + // Inputs to DUT + logic pwr_otp_init_i, scan_en_i, scan_rst_ni, ext_voltage_h_io; + lc_ctrl_pkg::lc_tx_t lc_dft_en_i, lc_escalate_en_i, lc_check_byp_en_i, + lc_creator_seed_sw_rw_en_i, lc_owner_seed_sw_rw_en_i, + lc_seed_hw_rd_en_i; + prim_mubi_pkg::mubi4_t scanmode_i; + otp_ast_rsp_t otp_ast_pwr_seq_h_i; + ast_pkg::ast_obs_ctrl_t obs_ctrl_i; + + // Unused in prim_generic_otp memory. + logic [OtpTestCtrlWidth-1:0] otp_vendor_test_ctrl_i; + logic [OtpTestStatusWidth-1:0] otp_vendor_test_status_o; + logic [OtpTestVectWidth-1:0] cio_test_o; + logic [OtpTestVectWidth-1:0] cio_test_en_o; + + // Connect with lc_prog push_pull interface. + logic lc_prog_req, lc_prog_err; + logic lc_prog_err_dly1, lc_prog_no_sta_check; + + // Connect push_pull interfaces ack signals for assertion checks. + logic otbn_ack, lc_prog_ack; + logic [1:0] flash_acks; + logic [NumSramKeyReqSlots-1:0] sram_acks; + + // Variables for internal interface logic. + // `lc_escalate_en` is async, take two clock cycles to synchronize. + lc_ctrl_pkg::lc_tx_t lc_esc_dly1, lc_esc_dly2; + + // Variable for scoreboard. + // For `lc_escalate_en`, any value that is not `Off` is a `On`. + bit lc_esc_on; + + // Probe design signal for alert request. + logic alert_reqs; + + // Usually the `lc_check_byp_en` will be automatically set to `On` when LC program request is + // issued, and stays `On` until reset is issued. + // Set this variable to 0 after a LC program request might cause otp checks to fail. + bit lc_check_byp_en = 1; + + // Internal veriable to track which sw partitions have ECC reg error. + bit [NumPartUnbuf-1:0] force_sw_parts_ecc_reg; + + // DUT configuration object + otp_ctrl_ast_inputs_cfg dut_cfg; + + // for DV macros ID + string msg_id = "otp_ctrl_if"; + + // Lc_err could trigger during LC program, so check intr and status after lc_req is finished. + // Lc_err takes one clock cycle to propogate to intr signal. So avoid intr check if it happens + // during the transition. + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + lc_prog_err_dly1 <= 0; + lc_esc_dly1 <= lc_ctrl_pkg::Off; + lc_esc_dly2 <= lc_ctrl_pkg::Off; + lc_check_byp_en_i <= get_rand_lc_tx_val(); + lc_esc_on <= 0; + end else begin + lc_prog_err_dly1 <= lc_prog_err; + lc_esc_dly1 <= lc_escalate_en_i; + lc_esc_dly2 <= lc_esc_dly1; + if (lc_prog_req) begin + lc_check_byp_en_i <= lc_check_byp_en ? lc_ctrl_pkg::On : lc_ctrl_pkg::Off; + end + if (lc_esc_dly2 != lc_ctrl_pkg::Off && !lc_esc_on) begin + lc_esc_on <= 1; + end + end + end + + assign lc_prog_no_sta_check = lc_prog_err | lc_prog_err_dly1 | lc_prog_req | lc_esc_on; + + function automatic void drive_pwr_otp_init(logic val); + pwr_otp_init_i = val; + endfunction + + function automatic void drive_ext_voltage_h_io(logic val); + ext_voltage_h_io = val; + endfunction + + function automatic void drive_lc_creator_seed_sw_rw_en(lc_ctrl_pkg::lc_tx_t val); + lc_creator_seed_sw_rw_en_i = val; + endfunction + + function automatic void drive_lc_owner_seed_sw_rw_en(lc_ctrl_pkg::lc_tx_t val); + lc_owner_seed_sw_rw_en_i = val; + endfunction + + function automatic void drive_lc_dft_en(lc_ctrl_pkg::lc_tx_t val); + lc_dft_en_i = val; + endfunction + + function automatic void drive_lc_escalate_en(lc_ctrl_pkg::lc_tx_t val); + lc_escalate_en_i = val; + endfunction + + function automatic void drive_lc_seed_hw_rd_en(lc_ctrl_pkg::lc_tx_t val); + lc_seed_hw_rd_en_i = val; + endfunction + + function automatic bit under_error_states(); + return lc_esc_on | alert_reqs; + endfunction + + // SW partitions do not have any internal checks. + // Here we force internal ECC check to fail. + task automatic force_sw_check_fail( + bit[NumPartUnbuf-1:0] fail_idx = $urandom_range(1, (1'b1 << NumPartUnbuf) - 1)); + @(posedge clk_i); +% for part in unbuf_parts_with_digest: +<% + part_name = Name.from_snake_case(part["name"]) + part_name_camel = part_name.as_camel_case() +%>\ + if (fail_idx[${part_name_camel}Idx]) begin + force tb.dut.gen_partitions[${part_name_camel}Idx].gen_unbuffered. + u_part_unbuf.`ECC_REG_PATH.data_i[0] = 1; + force_sw_parts_ecc_reg[${part_name_camel}Idx] = 1; + end +% endfor + endtask + + task automatic release_sw_check_fail(); + @(posedge clk_i); +% for part in unbuf_parts_with_digest: +<% + part_name = Name.from_snake_case(part["name"]) + part_name_camel = part_name.as_camel_case() +%>\ + if (force_sw_parts_ecc_reg[${part_name_camel}Idx]) begin + release tb.dut.gen_partitions[${part_name_camel}Idx].gen_unbuffered. + u_part_unbuf.`ECC_REG_PATH.data_i[0]; + force_sw_parts_ecc_reg[${part_name_camel}Idx] = 0; + end +% endfor + endtask + + // Force prim_generic_otp input cmd_i to a invalid value. + task automatic force_invalid_otp_cmd_i(); + @(posedge clk_i); + force `PRIM_GENERIC_OTP_CMD_I_PATH = prim_otp_pkg::cmd_e'(2'b10); + endtask + + task automatic release_invalid_otp_cmd_i(); + @(posedge clk_i); + release `PRIM_GENERIC_OTP_CMD_I_PATH; + endtask + + // Force part_buf partitions output otp_cmd_o to a invalid value. + task automatic force_invalid_part_cmd_o(int part_idx); + @(posedge clk_i); + case (part_idx) +% for part in buf_parts_without_lc: +<% + part_name = Name.from_snake_case(part["name"]) + part_name_camel = part_name.as_camel_case() +%>\ + ${part_name_camel}Idx: force `BUF_PART_OTP_CMD_PATH(${part_name_camel}Idx) = prim_otp_pkg::cmd_e'(2'b10); +% endfor + LifeCycleIdx: force `LC_PART_OTP_CMD_PATH = prim_otp_pkg::cmd_e'(2'b10); + default: begin + `uvm_fatal("otp_ctrl_if", + $sformatf("force invalid otp_cmd_o only supports buffered partitions: %0d", part_idx)) + end + endcase + endtask + + task automatic release_invalid_part_cmd_o(int part_idx); + @(posedge clk_i); + case (part_idx) +% for part in buf_parts_without_lc: +<% + part_name = Name.from_snake_case(part["name"]) + part_name_camel = part_name.as_camel_case() +%>\ + ${part_name_camel}Idx: release `BUF_PART_OTP_CMD_PATH(${part_name_camel}Idx); +% endfor + LifeCycleIdx: release `LC_PART_OTP_CMD_PATH; + default: begin + `uvm_fatal("otp_ctrl_if", + $sformatf("release invalid otp_cmd_o only supports buffered partitions: %0d", + part_idx)) + end + endcase + endtask + + // This task forces otp_ctrl's internal mubi signals to values that are not mubi::true or mubi:: + // false. Then scb will check if design treats these values as locking the partition access. + task automatic force_part_access_mubi(otp_part_access_lock_t forced_part_access_sel[NumPart-1]); + @(posedge clk_i); +% for part in parts_without_lc: +<% + part_name = Name.from_snake_case(part["name"]) + part_name_camel = part_name.as_camel_case() +%>\ + `FORCE_OTP_PART_LOCK_WITH_RAND_NON_MUBI_VAL(${part_name_camel}Idx) +% endfor + endtask + + task automatic release_part_access_mubi(); + @(posedge clk_i); + release tb.dut.part_access; + release tb.dut.part_access_dai; + endtask + + // Connectivity assertions for test related I/Os. + `ASSERT(LcOtpTestStatusO_A, otp_vendor_test_status_o == `PRIM_GENERIC_OTP_PATH.test_status_o) + `ASSERT(LcOtpTestCtrlI_A, otp_vendor_test_ctrl_i == `PRIM_GENERIC_OTP_PATH.test_ctrl_i) + + `ASSERT(CioTestOWithDftOn_A, lc_dft_en_i == lc_ctrl_pkg::On |-> + ${"##"}[2:3] cio_test_o == `PRIM_GENERIC_OTP_PATH.test_vect_o) + `ASSERT(CioTestOWithDftOff_A, lc_dft_en_i != lc_ctrl_pkg::On |-> ##[2:3] cio_test_o == 0) + `ASSERT(CioTestEnOWithDftOn_A, lc_dft_en_i == lc_ctrl_pkg::On |-> ##[2:3] cio_test_en_o == '1) + `ASSERT(CioTestEnOWithDftOff_A, lc_dft_en_i != lc_ctrl_pkg::On |-> ##[2:3] cio_test_en_o == 0) + + + `define OTP_ASSERT_WO_LC_ESC(NAME, SEQ) ${"\\"} + `ASSERT(NAME, SEQ, clk_i, !rst_ni || lc_esc_on || alert_reqs) + + // If pwr_otp_idle is set only if pwr_otp init is done + `OTP_ASSERT_WO_LC_ESC(OtpPwrDoneWhenIdle_A, pwr_otp_idle_o |-> pwr_otp_done_o) + + // otp_broadcast_o is valid only when otp init is done + `OTP_ASSERT_WO_LC_ESC(OtpHwCfgValidOn_A, pwr_otp_done_o |-> + otp_broadcast_o.valid == lc_ctrl_pkg::On) + // If otp_broadcast is Off, then hw partition is not finished calculation, + // then otp init is not done + `OTP_ASSERT_WO_LC_ESC(OtpHwCfgValidOff_A, otp_broadcast_o.valid == lc_ctrl_pkg::Off |-> + pwr_otp_done_o == 0) + // Once OTP init is done, otp_broadcast_o output value stays stable until next power cycle + `OTP_ASSERT_WO_LC_ESC(OtpHwCfgStable_A, otp_broadcast_o.valid == lc_ctrl_pkg::On |=> + $stable(otp_broadcast_o)) + + // Otp_keymgr valid is related to part_digest, should not be changed after otp_pwr_init + `OTP_ASSERT_WO_LC_ESC(OtpKeymgrValidStable0_A, pwr_otp_done_o |-> + $stable(keymgr_key_o.creator_root_key_share0_valid)) + `OTP_ASSERT_WO_LC_ESC(OtpKeymgrValidStable1_A, pwr_otp_done_o |-> + $stable(keymgr_key_o.creator_root_key_share1_valid)) + `OTP_ASSERT_WO_LC_ESC(OtpKeymgrValidStable2_A, pwr_otp_done_o |-> + $stable(keymgr_key_o.creator_seed_valid)) + `OTP_ASSERT_WO_LC_ESC(OtpKeymgrValidStable3_A, pwr_otp_done_o |-> + $stable(keymgr_key_o.owner_seed_valid)) + + // During lc_prog_req, either otp_idle will be reset or lc_error is set + `OTP_ASSERT_WO_LC_ESC(LcProgReq_A, $rose(lc_prog_req) |=> + (pwr_otp_idle_o == 0 || $rose(lc_prog_err)) within lc_prog_req[*1:$]) + + // During fatal alert, check if otp outputs revert back to default value. + // Wait three clock cycles until error propogates to each FSM states and regs. + `define OTP_FATAL_ERR_ASSERT(NAME, SEQ) ${"\\"} + `ASSERT(FatalErr``NAME``, alert_reqs |-> ##3 SEQ) + + `OTP_FATAL_ERR_ASSERT(LcDataValid_A, lc_data_o.valid == 0 && lc_data_o.error == 1) + `OTP_FATAL_ERR_ASSERT(LcDataState_A, lc_data_o.state == + PartInvDefault[LcStateOffset*8+:LcStateSize*8]) + `OTP_FATAL_ERR_ASSERT(LcDataCount_A, lc_data_o.count == + PartInvDefault[LcTransitionCntOffset*8+:LcTransitionCntSize*8]) + `OTP_FATAL_ERR_ASSERT(LcDataTestUnlockToken_A, lc_data_o.test_unlock_token == + PartInvDefault[TestUnlockTokenOffset*8+:TestUnlockTokenSize*8]) + `OTP_FATAL_ERR_ASSERT(LcDataTestExitToken_A, lc_data_o.test_exit_token == + PartInvDefault[TestExitTokenOffset*8+:TestExitTokenSize*8]) + `OTP_FATAL_ERR_ASSERT(LcDataRmaToken_A, lc_data_o.rma_token == + PartInvDefault[RmaTokenOffset*8+:RmaTokenSize*8]) + + `OTP_FATAL_ERR_ASSERT(KeymgrKeyData_A, keymgr_key_o.creator_root_key_share0 == + PartInvDefault[CreatorRootKeyShare0Offset*8+:CreatorRootKeyShare0Size*8] && + keymgr_key_o.creator_root_key_share1 == + PartInvDefault[CreatorRootKeyShare1Offset*8+:CreatorRootKeyShare1Size*8]) + + `OTP_FATAL_ERR_ASSERT(HwCfgOValid_A, otp_broadcast_o.valid == lc_ctrl_pkg::Off) + `OTP_FATAL_ERR_ASSERT(HwCfg0OData_A, otp_broadcast_o.hw_cfg0_data == + PartInvDefault[HwCfg0Offset*8+:HwCfg0Size*8]) + `OTP_FATAL_ERR_ASSERT(HwCfg1OData_A, otp_broadcast_o.hw_cfg1_data == + PartInvDefault[HwCfg1Offset*8+:HwCfg1Size*8]) + + `OTP_FATAL_ERR_ASSERT(LcProgAck_A, lc_prog_ack == 0) + `OTP_FATAL_ERR_ASSERT(FlashAcks_A, flash_acks == 0) + `OTP_FATAL_ERR_ASSERT(SramAcks_A, sram_acks == 0) + `OTP_FATAL_ERR_ASSERT(OtbnAck_A, otbn_ack == 0) + + `undef OTP_ASSERT_WO_LC_ESC + `undef OTP_FATAL_ERR_ASSERT + `undef ECC_REG_PATH + `undef BUF_PART_OTP_CMD_PATH + `undef LC_PART_OTP_CMD_PATH + `undef PRIM_GENERIC_OTP_PATH + `undef PRIM_GENERIC_OTP_CMD_I_PATH + `undef FORCE_OTP_PART_LOCK_WITH_RAND_NON_MUBI_VAL +endinterface diff --git a/src/fuse_ctrl/data/otp_ctrl_img_dev.hjson b/src/fuse_ctrl/data/otp_ctrl_img_dev.hjson new file mode 100644 index 0000000..f335116 --- /dev/null +++ b/src/fuse_ctrl/data/otp_ctrl_img_dev.hjson @@ -0,0 +1,75 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Use the gen-otp-img.py script to convert this configuration into +// a MEM file for preloading the OTP in FPGA synthesis or simulation. +// + +{ + // 256 bit seed to be used for generation of partition randomized values. + // Can be overridden on the command line with the --seed switch. + // The default seed was generated using secrets.py module. + seed: 85452983286950371191603618368782861611109037138182535346147818831008789508651 + + // The partition and item names must correspond with the OTP memory map. + partitions: [ + { + name: "SECRET0", + lock: "True", + items: [ + { + name: "TEST_UNLOCK_TOKEN", + value: "", + } + { + name: "TEST_EXIT_TOKEN", + value: "", + } + ], + } + { + name: "SECRET1", + lock: "True", + items: [ + { + name: "UDS_SEED", + value: "", + } + ], + } + { + name: "SECRET2", + lock: "True", + items: [ + { + name: "FIELD_ENTROPY", + value: "", + } + ], + } + { + name: "SECRET3", + lock: "False", + items: [ + { + name: "KEY_MANIFEST_PK_HASH", + value: "", + } + { + name: "RMA_TOKEN", + value: "", + } + ], + } + { + name: "LIFE_CYCLE", + // Can be one of the following strings: + // RAW, TEST_UNLOCKED0-3, TEST_LOCKED0-2, DEV, PROD, PROD_END, RMA, SCRAP + state: "DEV", + // Can range from 0 to 16. + // Note that a value of 0 is only permissible in RAW state. + count: "5" + } + ] +} diff --git a/src/fuse_ctrl/data/otp_ctrl_img_non_secret_fuses.hjson b/src/fuse_ctrl/data/otp_ctrl_img_non_secret_fuses.hjson new file mode 100644 index 0000000..cdc5e4c --- /dev/null +++ b/src/fuse_ctrl/data/otp_ctrl_img_non_secret_fuses.hjson @@ -0,0 +1,55 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Use the gen-otp-img.py script to convert this configuration into +// a MEM file for preloading the OTP in FPGA synthesis or simulation. +// + +{ + // The partition and item names must correspond with the OTP memory map. + partitions: [ + { + name: "NON_SECRET_FUSES", + items: [ + { + name: "FMC_KEY_MANIFEST_SVN", + value: "", + }, + { + name: "RUNTIME_SVN", + value: "", + }, + { + name: "LMS_VERIFY", + value: "", + }, + { + name: "LMS_REVOCATION", + value: "", + }, + { + name: "KEY_MANIFEST_PK_HASH_MASK", + value: "", + }, + { + name: "OWNER_PK_HASH", + value: "", + }, + { + name: "IDEVID_CERT_ATTR", + value: "", + }, + { + name: "IDEVID_MANUF_HSM_ID", + value: "", + }, + { + name: "SOC_STEPPING_ID", + value: "", + }, + + ], + } + ] +} diff --git a/src/fuse_ctrl/data/otp_ctrl_img_rma.hjson b/src/fuse_ctrl/data/otp_ctrl_img_rma.hjson new file mode 100644 index 0000000..f28e69c --- /dev/null +++ b/src/fuse_ctrl/data/otp_ctrl_img_rma.hjson @@ -0,0 +1,77 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Use the gen-otp-img.py script to convert this configuration into +// a MEM file for preloading the OTP in FPGA synthesis or simulation. +// + +{ + // Seed to be used for generation of partition randomized values. + // Can be overridden on the command line with the --seed switch. + // The default seed was generated using secrets.py module. + seed: 52408960416235844780753299194502148156786072650816676092165912261205302331741 + + // The partition and item names must correspond with the OTP memory map. + partitions: [ + { + name: "SECRET0", + lock: "True", + items: [ + { + name: "TEST_UNLOCK_TOKEN", + value: "", + } + { + name: "TEST_EXIT_TOKEN", + value: "", + } + ], + } + { + name: "SECRET1", + lock: "True", + items: [ + { + name: "FLASH_ADDR_KEY_SEED", + value: "", + } + { + name: "FLASH_DATA_KEY_SEED", + value: "", + } + { + name: "SRAM_DATA_KEY_SEED", + value: "", + } + ], + } + { + name: "SECRET2", + lock: "False", + items: [ + { + name: "RMA_TOKEN", + value: "", + } + { + name: "CREATOR_ROOT_KEY_SHARE0", + value: "", + } + { + name: "CREATOR_ROOT_KEY_SHARE1", + value: "", + } + ], + } + { + name: "LIFE_CYCLE", + // Can be one of the following strings: + // RAW, TEST_UNLOCKED0-3, TEST_LOCKED0-2, DEV, PROD, PROD_END, RMA, SCRAP + state: "RMA", + // Can range from 0 to 16. + // Note that a value of 0 is only permissible in RAW state. + count: "8" + } + ] +} diff --git a/src/fuse_ctrl/data/otp_ctrl_mmap.hjson b/src/fuse_ctrl/data/otp_ctrl_mmap.hjson new file mode 100755 index 0000000..16642ec --- /dev/null +++ b/src/fuse_ctrl/data/otp_ctrl_mmap.hjson @@ -0,0 +1,310 @@ +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Use the gen-otp-mmap.py script to update dependent files (like documentation +// tables the comportable hjson and metadata SV package): +// +// $ ./util/design/gen-otp-mmap.py +// +// Make sure to regenerate the CSRs after converting the memory map: +// +// $ cd ${PROJ_ROOT} +// $ make -C hw regs +// + +{ + // 256 bit seed to be used for generation of partition item default values. + // Can be overridden on the command line with the --seed switch. + seed: "36021179872380457113239299468132194022238108125576166239904535336103582949069" + + otp: { + width: "2", // bytes + depth: "2048" + } + + // Definition of scrambling and digest constants and keys. + scrambling: { + key_size: "16", + iv_size: "8", + cnst_size: "16", + keys: [ + { + name: "Secret0Key", + value: "", + } + { + name: "Secret1Key", + value: "", + } + { + name: "Secret2Key", + value: "", + } + { + name: "Secret3Key", + value: "", + } + ] + digests: [ + // This is the consistency digest used by all partitions. + { + name: "CnstyDigest", + iv_value: "", + cnst_value: "", + } + /* + // The other digest configurations below are used for + // key derivation and token hashing. + { + name: "FlashDataKey", + iv_value: "", + cnst_value: "", + } + { + name: "FlashAddrKey", + iv_value: "", + cnst_value: "", + } + { + name: "SramDataKey", + iv_value: "", + cnst_value: "", + } + */ + ] + } + + // The enumeration order below defines the address map of the OTP controller, + // if the offsets are not defined explicitly via the "offset" key. + // Note that the digest items are added automatically to the address map. + partitions: [ + { + name: "VENDOR_TEST", + variant: "Unbuffered", + size: "64", // in bytes + secret: false, + sw_digest: true, + hw_digest: false, + write_lock: "Digest", + read_lock: "CSR", + key_sel: "NoKey", + integrity: false, // Do not use integrity (ECC) on this partition. + bkout_type: false, // Do not use generate a breakout type for this partition. + items: [ + { + name: "SCRATCH", + size: "56" + } + ], + desc: '''Vendor test partition. + This is reserved for manufacturing smoke checks. The OTP wrapper + control logic inside prim_otp is allowed to read/write to this + region. ECC uncorrectable errors seen on the functional prim_otp + interface will not lead to an alert for this partition. + Instead, such errors will be reported as correctable ECC errors. + ''' + } + { + name: "NON_SECRET_FUSES", + variant: "Unbuffered", + absorb: true, + secret: false, + sw_digest: true, + hw_digest: false, + write_lock: "Digest", + read_lock: "CSR", + key_sel: "NoKey", + integrity: true, // Use integrity (ECC) on this partition + bkout_type: false, // Do not generate a breakout type for this partition + items: [ + { + name: "FMC_KEY_MANIFEST_SVN", + size: "4" + } + { + name: "RUNTIME_SVN", + size: "16" + } + { + name: "LMS_VERIFY", + size: "4" + } + { + name: "LMS_REVOCATION", + size: "4" + } + { + name: "KEY_MANIFEST_PK_HASH_MASK", + size: "4" + } + { + name: "OWNER_PK_HASH", + size: "48" + } + { + name: "IDEVID_CERT_ATTR", + size: "96", + // Default value to be output in case partition has not + // initialized or is in error state. If not specified, + // a value of '0 will be used. + inv_default: "", + } + { + name: "IDEVID_MANUF_HSM_ID", + size: "16" + } + { + name: "SOC_STEPPING_ID", + size: "4" + } + ], + desc: '''Non Secret Fuses partition. + This contains data such IDEVID, public key hash mask, owner + key hash, SoC Stepping ID etc. + ''' + } + { + name: "SECRET0", + variant: "Buffered", + secret: true, + sw_digest: false, + hw_digest: true, + write_lock: "Digest", + read_lock: "Digest", + key_sel: "Secret0Key", + integrity: true, + bkout_type: false, + items: [ + { + name: "TEST_UNLOCK_TOKEN", + // This will generate a random default to be output in + // case partition has not initialized or is in error state. + // If not specified, a value of '0 will be used. + inv_default: "", + size: "16" + } + { + name: "TEST_EXIT_TOKEN", + inv_default: "", + size: "16" + } + ], + desc: '''Secret partition 0. + This contains TEST lifecycle unlock tokens. + ''' + } + { + name: "SECRET1", + variant: "Buffered", + secret: true, + sw_digest: false, + hw_digest: true, + write_lock: "Digest", + read_lock: "Digest", + key_sel: "Secret1Key", + integrity: true, + bkout_type: false, + items: [ + { + name: "UDS_SEED", + size: "48" + } + ], + desc: '''Secret partition 1. + This contains Obfuscated UDS seed. + ''' + } + { + name: "SECRET2", + variant: "Buffered", + secret: true, + sw_digest: false, + hw_digest: true, + write_lock: "Digest", + read_lock: "Digest", + key_sel: "Secret2Key", + integrity: true, + bkout_type: false, + items: [ + { + name: "FIELD_ENTROPY", + size: "32" + } + ], + desc: '''Secret partition 2. + This contains obfuscated field entropy. + ''' + } + { + name: "SECRET3", + variant: "Buffered", + secret: true, + sw_digest: false, + hw_digest: true, + write_lock: "Digest", + read_lock: "Digest", + key_sel: "Secret3Key", + integrity: true, + bkout_type: false, + items: [ + { + name: "KEY_MANIFEST_PK_HASH", + size: "48" + } + { + name: "RMA_TOKEN", + inv_default: "", + size: "16" + } + ], + desc: '''Secret partition 3. + This contains public key hash and RMA unlock token. + ''' + } + { + name: "LIFE_CYCLE", + variant: "LifeCycle", + secret: false, + sw_digest: false, + hw_digest: false, + write_lock: "None", + read_lock: "None", + key_sel: "NoKey", + integrity: true, + bkout_type: false, + items: [ + // The life cycle transition count is specified + // first such that any programming attempt of the life cycle + // partition through the LCI will always write the transition + // counter words first when programming an updated state vector. + // This is an additional safeguard, to the sequencing in the + // life cycle controller to ensure that the counter is always written + // before any state update. I.e., the life cycle controller + // already splits the counter and state updates into two + // supsequent requests through the LCI, where the first request + // only contains the updated transition counter, and the second + // request the updated transition counter and state. + { + name: "LC_TRANSITION_CNT", + inv_default: "", + size: "48" + } + { + name: "LC_STATE", + inv_default: "", + size: "40" + } + ], + desc: '''Lifecycle partition. + This contains lifecycle transition count and state. This partition + cannot be locked since the life cycle state needs to advance to RMA + in-field. Note that while this partition is not marked secret, it + is not readable nor writeable via the DAI. Only the LC controller + can access this partition, and even via the LC controller it is not + possible to read the raw manufacturing life cycle state in encoded + form, since that encoding is considered a netlist secret. The LC + controller only exposes a decoded version of this state. + ''' + } + ] +} \ No newline at end of file diff --git a/src/fuse_ctrl/data/otp_ctrl_mod.hjson b/src/fuse_ctrl/data/otp_ctrl_mod.hjson new file mode 100755 index 0000000..7654b03 --- /dev/null +++ b/src/fuse_ctrl/data/otp_ctrl_mod.hjson @@ -0,0 +1,2003 @@ +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// HJSON with partition metadata. +// +// DO NOT EDIT THIS FILE DIRECTLY. +// It has been generated with ./util/design/gen-otp-mmap.py + +{ + name: "caliptra_otp_ctrl", + human_name: " Caliptra One-Time Programmable Memory COntroller", + one_line_desc: "Interfaces integrated one0time programmable memory, supports scrambling, integrity and secure dai_wr_inprogress", + one_paragraph_desc: ''' + One-Time Programmable (OTP) Memory Controller provides an open source abstraction interface for software and other hardware components such as Life Cycle Controller and Key Manager to interact with an integrated, closed source, proprietary OTP memory. + On top of defensive features provided by the proprietary OTP memory to deter side-channel analysis (SCA), fault injection (FI) attacks, and visual and electrical probing, the open source OTP controller features high-level logical security protection such as integrity checks and scrambling, as well as software isolation for when OTP contents are readable and programmable. + It features multiple individually-lockable logical partitions, periodic / persistent checking of OTP values, and a separate partition and interface for Life Cycle Controller. + ''' + // Uique comportablre IP identifier defined under KNOWN_CIP_IDS in the regtool + // TODO: This section needs to be updated for Caliptra (copying OT settings for now, to mark as placeholders) + cip_id: "16", + design_spec: "../doc", + dv_doc: "../doc/dv", + hw_checklist: "../doc/checklist", + sw_checklist: "/sw/device/lib/dif/dif_otp_ctrl", + revisions: [ + { + version: "0.1.0", + life_stage: "L1", + design_stage: "D2", + verification_stage: "V2", + dif_stage: "S1", + commit_id: "127b109e2fab9336e830158abe449a3922544ded", + notes: "", + } + { + version: "1.0.0", + life_stage: "L1", + design_stage: "D3", + verification_stage: "V2S", + dif_stage: "S2", + notes: "", + } + { + version: "2.0.0", + life_stage: "L1", + design_stage: "D2S", + verification_stage: "V2S", + dif_stage: "S2", + notes: "", + } + ] + clocking: [ + {clock: "clk_i", reset: "rst_ni", primary: true}, + {clock: "clk_edn_i", reset: "rst_edn_ni"} + ] + scan: "true", // Enable `scanmode_i` port + scan_reset: "true", // Enable `scan_rst_ni` port + scan_en: "true", // Enable `scan_en_i` port + bus_interfaces: [ + { protocol: "tlul", direction: "device", name: "core" } + { protocol: "tlul", direction: "device", name: "prim", hier_path: "u_otp.gen_generic.u_impl_generic.u_reg_top" } + ], + + available_output_list: [ + { name: "test", + width: 8, + desc: "Test-related GPIOs. Only active in DFT-enabled life cycle states." + } + ], + + /////////////////////////// + // Interrupts and Alerts // + /////////////////////////// + + interrupt_list: [ + { name: "otp_operation_done", + desc: "A direct access command or digest calculation operation has completed." + } + { name: "otp_error", + desc: "An error has occurred in the OTP controller. Check the !!ERR_CODE register to get more information." + } + ], + + alert_list: [ + { name: "fatal_macro_error", + desc: "This alert triggers if hardware detects an uncorrectable error during an OTP transaction, for example an uncorrectable ECC error in the OTP array.", + } + { name: "fatal_check_error", + desc: "This alert triggers if any of the background checks fails. This includes the digest checks and concurrent ECC checks in the buffer registers.", + } + { name: "fatal_bus_integ_error", + desc: "This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected." + } + { name: "fatal_prim_otp_alert", + desc: "Fatal alert triggered inside the OTP primitive, including fatal TL-UL bus integrity faults of the test interface." + } + { name: "recov_prim_otp_alert", + desc: "Recoverable alert triggered inside the OTP primitive." + } + ], + + //////////////// + // Parameters // + //////////////// + param_list: [ + // Init file + { name: "MemInitFile", + desc: "VMEM file to initialize the OTP macro.", + type: "", + default: '""', + expose: "true", + local: "false" + } + // Random netlist constants + { name: "RndCnstLfsrSeed", + desc: "Compile-time random bits for initial LFSR seed", + type: "otp_ctrl_pkg::lfsr_seed_t" + randcount: "40", + randtype: "data", // randomize randcount databits + } + { name: "RndCnstLfsrPerm", + desc: "Compile-time random permutation for LFSR output", + type: "otp_ctrl_pkg::lfsr_perm_t" + randcount: "40", + randtype: "perm", // random permutation for randcount elements + } + { name: "RndCnstScrmblKeyInit", + desc: "Compile-time random permutation for scrambling key/nonce register reset value", + type: "otp_ctrl_pkg::scrmbl_key_init_t" + randcount: "256", + randtype: "data", // random permutation for randcount elements + } + // Normal parameters + { name: "NumSramKeyReqSlots", + desc: "Number of key slots", + type: "int", + default: "4", + local: "true" + }, + { name: "OtpByteAddrWidth", + desc: "Width of the OTP byte address.", + type: "int", + default: "12", + local: "true" + }, + { name: "NumErrorEntries", + desc: "Number of error register entries.", + type: "int", + default: "9", // partitions + DAI/LCI + local: "true" + }, + { name: "NumDaiWords", + desc: "Number of 32bit words in the DAI.", + type: "int", + default: "2", + local: "true" + }, + { name: "NumDigestWords", + desc: "Size of the digest fields in 32bit words.", + type: "int", + default: "2", + local: "true" + }, + { name: "NumSwCfgWindowWords", + desc: "Size of the TL-UL window in 32bit words. Note that the effective partition size is smaller than that.", + type: "int", + default: "1024", + local: "true" + } + + // Memory map Info + { name: "NumPart", + desc: "Number of partitions", + type: "int", + default: "7", + local: "true" + }, + { name: "NumPartUnbuf", + desc: "Number of unbuffered partitions", + type: "int", + default: "2", + local: "true" + }, + { name: "NumPartBuf", + desc: "Number of buffered partitions (including 1 lifecycle partition)", + type: "int", + default: "5", + local: "true" + }, + { name: "VendorTestOffset", + desc: "Offset of the VENDOR_TEST partition", + type: "int", + default: "0", + local: "true" + }, + { name: "VendorTestSize", + desc: "Size of the VENDOR_TEST partition", + type: "int", + default: "64", + local: "true" + }, + { name: "ScratchOffset", + desc: "Offset of SCRATCH", + type: "int", + default: "0", + local: "true" + }, + { name: "ScratchSize", + desc: "Size of SCRATCH", + type: "int", + default: "56", + local: "true" + }, + { name: "VendorTestDigestOffset", + desc: "Offset of VENDOR_TEST_DIGEST", + type: "int", + default: "56", + local: "true" + }, + { name: "VendorTestDigestSize", + desc: "Size of VENDOR_TEST_DIGEST", + type: "int", + default: "8", + local: "true" + }, + { name: "NonSecretFusesOffset", + desc: "Offset of the NON_SECRET_FUSES partition", + type: "int", + default: "64", + local: "true" + }, + { name: "NonSecretFusesSize", + desc: "Size of the NON_SECRET_FUSES partition", + type: "int", + default: "3736", + local: "true" + }, + { name: "FmcKeyManifestSvnOffset", + desc: "Offset of FMC_KEY_MANIFEST_SVN", + type: "int", + default: "64", + local: "true" + }, + { name: "FmcKeyManifestSvnSize", + desc: "Size of FMC_KEY_MANIFEST_SVN", + type: "int", + default: "4", + local: "true" + }, + { name: "RuntimeSvnOffset", + desc: "Offset of RUNTIME_SVN", + type: "int", + default: "68", + local: "true" + }, + { name: "RuntimeSvnSize", + desc: "Size of RUNTIME_SVN", + type: "int", + default: "16", + local: "true" + }, + { name: "LmsVerifyOffset", + desc: "Offset of LMS_VERIFY", + type: "int", + default: "84", + local: "true" + }, + { name: "LmsVerifySize", + desc: "Size of LMS_VERIFY", + type: "int", + default: "4", + local: "true" + }, + { name: "LmsRevocationOffset", + desc: "Offset of LMS_REVOCATION", + type: "int", + default: "88", + local: "true" + }, + { name: "LmsRevocationSize", + desc: "Size of LMS_REVOCATION", + type: "int", + default: "4", + local: "true" + }, + { name: "KeyManifestPkHashMaskOffset", + desc: "Offset of KEY_MANIFEST_PK_HASH_MASK", + type: "int", + default: "92", + local: "true" + }, + { name: "KeyManifestPkHashMaskSize", + desc: "Size of KEY_MANIFEST_PK_HASH_MASK", + type: "int", + default: "4", + local: "true" + }, + { name: "OwnerPkHashOffset", + desc: "Offset of OWNER_PK_HASH", + type: "int", + default: "96", + local: "true" + }, + { name: "OwnerPkHashSize", + desc: "Size of OWNER_PK_HASH", + type: "int", + default: "48", + local: "true" + }, + { name: "IdevidCertAttrOffset", + desc: "Offset of IDEVID_CERT_ATTR", + type: "int", + default: "144", + local: "true" + }, + { name: "IdevidCertAttrSize", + desc: "Size of IDEVID_CERT_ATTR", + type: "int", + default: "96", + local: "true" + }, + { name: "IdevidManufHsmIdOffset", + desc: "Offset of IDEVID_MANUF_HSM_ID", + type: "int", + default: "240", + local: "true" + }, + { name: "IdevidManufHsmIdSize", + desc: "Size of IDEVID_MANUF_HSM_ID", + type: "int", + default: "16", + local: "true" + }, + { name: "SocSteppingIdOffset", + desc: "Offset of SOC_STEPPING_ID", + type: "int", + default: "256", + local: "true" + }, + { name: "SocSteppingIdSize", + desc: "Size of SOC_STEPPING_ID", + type: "int", + default: "4", + local: "true" + }, + { name: "NonSecretFusesDigestOffset", + desc: "Offset of NON_SECRET_FUSES_DIGEST", + type: "int", + default: "3792", + local: "true" + }, + { name: "NonSecretFusesDigestSize", + desc: "Size of NON_SECRET_FUSES_DIGEST", + type: "int", + default: "8", + local: "true" + }, + { name: "Secret0Offset", + desc: "Offset of the SECRET0 partition", + type: "int", + default: "3800", + local: "true" + }, + { name: "Secret0Size", + desc: "Size of the SECRET0 partition", + type: "int", + default: "40", + local: "true" + }, + { name: "TestUnlockTokenOffset", + desc: "Offset of TEST_UNLOCK_TOKEN", + type: "int", + default: "3800", + local: "true" + }, + { name: "TestUnlockTokenSize", + desc: "Size of TEST_UNLOCK_TOKEN", + type: "int", + default: "16", + local: "true" + }, + { name: "TestExitTokenOffset", + desc: "Offset of TEST_EXIT_TOKEN", + type: "int", + default: "3816", + local: "true" + }, + { name: "TestExitTokenSize", + desc: "Size of TEST_EXIT_TOKEN", + type: "int", + default: "16", + local: "true" + }, + { name: "Secret0DigestOffset", + desc: "Offset of SECRET0_DIGEST", + type: "int", + default: "3832", + local: "true" + }, + { name: "Secret0DigestSize", + desc: "Size of SECRET0_DIGEST", + type: "int", + default: "8", + local: "true" + }, + { name: "Secret1Offset", + desc: "Offset of the SECRET1 partition", + type: "int", + default: "3840", + local: "true" + }, + { name: "Secret1Size", + desc: "Size of the SECRET1 partition", + type: "int", + default: "56", + local: "true" + }, + { name: "UdsSeedOffset", + desc: "Offset of UDS_SEED", + type: "int", + default: "3840", + local: "true" + }, + { name: "UdsSeedSize", + desc: "Size of UDS_SEED", + type: "int", + default: "48", + local: "true" + }, + { name: "Secret1DigestOffset", + desc: "Offset of SECRET1_DIGEST", + type: "int", + default: "3888", + local: "true" + }, + { name: "Secret1DigestSize", + desc: "Size of SECRET1_DIGEST", + type: "int", + default: "8", + local: "true" + }, + { name: "Secret2Offset", + desc: "Offset of the SECRET2 partition", + type: "int", + default: "3896", + local: "true" + }, + { name: "Secret2Size", + desc: "Size of the SECRET2 partition", + type: "int", + default: "40", + local: "true" + }, + { name: "FieldEntropyOffset", + desc: "Offset of FIELD_ENTROPY", + type: "int", + default: "3896", + local: "true" + }, + { name: "FieldEntropySize", + desc: "Size of FIELD_ENTROPY", + type: "int", + default: "32", + local: "true" + }, + { name: "Secret2DigestOffset", + desc: "Offset of SECRET2_DIGEST", + type: "int", + default: "3928", + local: "true" + }, + { name: "Secret2DigestSize", + desc: "Size of SECRET2_DIGEST", + type: "int", + default: "8", + local: "true" + }, + { name: "Secret3Offset", + desc: "Offset of the SECRET3 partition", + type: "int", + default: "3936", + local: "true" + }, + { name: "Secret3Size", + desc: "Size of the SECRET3 partition", + type: "int", + default: "72", + local: "true" + }, + { name: "KeyManifestPkHashOffset", + desc: "Offset of KEY_MANIFEST_PK_HASH", + type: "int", + default: "3936", + local: "true" + }, + { name: "KeyManifestPkHashSize", + desc: "Size of KEY_MANIFEST_PK_HASH", + type: "int", + default: "48", + local: "true" + }, + { name: "RmaTokenOffset", + desc: "Offset of RMA_TOKEN", + type: "int", + default: "3984", + local: "true" + }, + { name: "RmaTokenSize", + desc: "Size of RMA_TOKEN", + type: "int", + default: "16", + local: "true" + }, + { name: "Secret3DigestOffset", + desc: "Offset of SECRET3_DIGEST", + type: "int", + default: "4000", + local: "true" + }, + { name: "Secret3DigestSize", + desc: "Size of SECRET3_DIGEST", + type: "int", + default: "8", + local: "true" + }, + { name: "LifeCycleOffset", + desc: "Offset of the LIFE_CYCLE partition", + type: "int", + default: "4008", + local: "true" + }, + { name: "LifeCycleSize", + desc: "Size of the LIFE_CYCLE partition", + type: "int", + default: "88", + local: "true" + }, + { name: "LcTransitionCntOffset", + desc: "Offset of LC_TRANSITION_CNT", + type: "int", + default: "4008", + local: "true" + }, + { name: "LcTransitionCntSize", + desc: "Size of LC_TRANSITION_CNT", + type: "int", + default: "48", + local: "true" + }, + { name: "LcStateOffset", + desc: "Offset of LC_STATE", + type: "int", + default: "4056", + local: "true" + }, + { name: "LcStateSize", + desc: "Size of LC_STATE", + type: "int", + default: "40", + local: "true" + }, + ] + + ///////////////////////////// + // Intermodule Connections // + ///////////////////////////// + + inter_signal_list: [ + // OTP dedicated power connection from AST + { struct: "" + type: "io" + name: "otp_ext_voltage_h" + act: "none" + default: "'0" + package: "", + } + // Power sequencing signals to AST + { struct: "otp_ast_req" + type: "uni" + name: "otp_ast_pwr_seq" + act: "req" + default: "'0" + package: "otp_ctrl_pkg" + desc: "Power sequencing signals to AST (VDD domain)." + } + // Power sequencing signals from AST + { struct: "otp_ast_rsp" + type: "uni" + name: "otp_ast_pwr_seq_h" + act: "rcv" + default: "'0" + package: "otp_ctrl_pkg" + desc: "Power sequencing signals coming from AST (VCC domain)." + } + // EDN interface + { struct: "edn" + type: "req_rsp" + name: "edn" + act: "req" + package: "edn_pkg" + desc: "Entropy request to the entropy distribution network for LFSR reseeding and ephemeral key derivation." + } + // Power manager init command + { struct: "pwr_otp" + type: "req_rsp" + name: "pwr_otp" + act: "rsp" + default: "'0" + package: "pwrmgr_pkg" + desc: "Initialization request/acknowledge from/to power manager." + } + // Macro-specific test signals to/from LC TAP + { struct: "lc_otp_vendor_test" + type: "req_rsp" + name: "lc_otp_vendor_test" + act: "rsp" + default: "'0" + package: "otp_ctrl_pkg" + desc: "Vendor test control signals from/to the life cycle TAP." + } + // LC transition command + { struct: "lc_otp_program" + type: "req_rsp" + name: "lc_otp_program" + act: "rsp" + default: "'0" + package: "otp_ctrl_pkg" + desc: "Life cycle state transition interface." + } + // Broadcast to LC + { struct: "otp_lc_data" + type: "uni" + name: "otp_lc_data" + act: "req" + default: "'0" + package: "otp_ctrl_pkg" + desc: ''' + Life cycle state output holding the current life cycle state, + the value of the transition counter and the tokens needed for life cycle transitions. + ''' + } + // Broadcast from LC + { struct: "lc_tx" + type: "uni" + name: "lc_escalate_en" + act: "rcv" + default: "lc_ctrl_pkg::Off" + package: "lc_ctrl_pkg" + desc: ''' + Life cycle escalation enable coming from life cycle controller. + This signal moves all FSMs within OTP into the error state. + ''' + } + { struct: "lc_tx" + type: "uni" + name: "lc_creator_seed_sw_rw_en" + act: "rcv" + default: "lc_ctrl_pkg::Off" + package: "lc_ctrl_pkg" + desc: ''' + Provision enable qualifier coming from life cycle controller. + This signal enables SW read / write access to the RMA_TOKEN and CREATOR_ROOT_KEY_SHARE0 and CREATOR_ROOT_KEY_SHARE1. + ''' + } + { struct: "lc_tx" + type: "uni" + name: "lc_owner_seed_sw_rw_en" + act: "rcv" + default: "lc_ctrl_pkg::Off" + package: "lc_ctrl_pkg" + desc: ''' + Provision enable qualifier coming from life cycle controller. + This signal enables SW read / write access to the OWNER_SEED. + ''' + } + { struct: "lc_tx" + type: "uni" + name: "lc_seed_hw_rd_en" + act: "rcv" + default: "lc_ctrl_pkg::Off" + package: "lc_ctrl_pkg" + desc: ''' + Seed read enable coming from life cycle controller. + This signal enables HW read access to the CREATOR_ROOT_KEY_SHARE0 and CREATOR_ROOT_KEY_SHARE1. + ''' + } + { struct: "lc_tx" + type: "uni" + name: "lc_dft_en" + act: "rcv" + default: "lc_ctrl_pkg::Off" + package: "lc_ctrl_pkg" + desc: ''' + Test enable qualifier coming from life cycle controller. + This signals enables the TL-UL access port to the proprietary OTP IP. + ''' + } + { struct: "lc_tx" + type: "uni" + name: "lc_check_byp_en" + act: "rcv" + default: "lc_ctrl_pkg::Off" + package: "lc_ctrl_pkg" + desc: ''' + Life cycle partition check bypass signal. + This signal causes the life cycle partition to bypass consistency checks during life cycle state transitions in order to prevent spurious consistency check failures. + ''' + } + // Broadcast to Key Manager + { struct: "otp_keymgr_key" + type: "uni" + name: "otp_keymgr_key" + act: "req" + default: "'0" + package: "otp_ctrl_pkg" + desc: "Key output to the key manager holding CREATOR_ROOT_KEY_SHARE0 and CREATOR_ROOT_KEY_SHARE1." + } + // Broadcast to Flash Controller + { struct: "flash_otp_key" + type: "req_rsp" + name: "flash_otp_key" + act: "rsp" + default: "'0" + package: "otp_ctrl_pkg" + desc: "Key derivation interface for FLASH scrambling." + } + // Key request from SRAM scramblers + { struct: "sram_otp_key" + // TODO: would be nice if this could accept parameters. + // Split this out into an issue. + width: "4" + type: "req_rsp" + name: "sram_otp_key" + act: "rsp" + default: "'0" + package: "otp_ctrl_pkg" + desc: "Array with key derivation interfaces for SRAM scrambling devices." + } + // Key request from OTBN RAM Scrambler + { struct: "otbn_otp_key" + type: "req_rsp" + name: "otbn_otp_key" + act: "rsp" + default: "'0" + package: "otp_ctrl_pkg" + desc: "Key derivation interface for OTBN scrambling devices." + } + // Hardware config partition + { struct: "otp_broadcast" + type: "uni" + name: "otp_broadcast" + act: "req" + default: "'0" + package: "otp_ctrl_part_pkg" + desc: "Output of the HW partitions with breakout data types." + } + // AST observability control + { struct: "ast_obs_ctrl", + type: "uni", + name: "obs_ctrl", + act: "rcv", + package: "ast_pkg" + desc: "AST observability control signals." + } + // prim otp observe bus + { struct: "logic", + type: "uni", + name: "otp_obs", + act: "req", + width: "8", + package: "" + desc: "AST observability bus." + } + ] // inter_signal_list + + ///////////////////// + // Countermeasures // + ///////////////////// + + countermeasures: [ + { name: "BUS.INTEGRITY", + desc: "End-to-end bus integrity scheme." + } + { name: "SECRET.MEM.SCRAMBLE", + desc: "Secret partitions are scrambled with a full-round PRESENT cipher." + } + { name: "PART.MEM.DIGEST", + desc: "Integrity of buffered partitions is ensured via a 64bit digest." + } + { name: "DAI.FSM.SPARSE", + desc: "The direct access interface FSM is sparsely encoded." + } + { name: "KDI.FSM.SPARSE", + desc: "The key derivation interface FSM is sparsely encoded." + } + { name: "LCI.FSM.SPARSE", + desc: "The life cycle interface FSM is sparsely encoded." + } + { name: "PART.FSM.SPARSE", + desc: "The partition FSMs are sparsely encoded." + } + { name: "SCRMBL.FSM.SPARSE", + desc: "The scramble datapath FSM is sparsely encoded." + } + { name: "TIMER.FSM.SPARSE", + desc: "The background check timer FSM is sparsely encoded." + } + { name: "DAI.CTR.REDUN", + desc: "The direct access interface address counter employs a cross-counter implementation." + } + { name: "KDI_SEED.CTR.REDUN", + desc: "The key derivation interface counter employs a cross-counter implementation." + } + { name: "KDI_ENTROPY.CTR.REDUN", + desc: "The key derivation entropy counter employs a cross-counter implementation." + } + { name: "LCI.CTR.REDUN", + desc: "The life cycle interface address counter employs a cross-counter implementation." + } + { name: "PART.CTR.REDUN", + desc: "The address counter of buffered partitions employs a cross-counter implementation." + } + { name: "SCRMBL.CTR.REDUN", + desc: "The srambling datapath counter employs a cross-counter implementation." + } + { name: "TIMER_INTEG.CTR.REDUN", + desc: "The background integrity check timer employs a duplicated counter implementation." + } + { name: "TIMER_CNSTY.CTR.REDUN", + desc: "The background consistency check timer employs a duplicated counter implementation." + } + { name: "TIMER.LFSR.REDUN", + desc: "The background check LFSR is duplicated." + } + { name: "DAI.FSM.LOCAL_ESC", + desc: "The direct access interface FSM is moved into an invalid state upon local escalation." + } + { name: "LCI.FSM.LOCAL_ESC", + desc: "The life cycle interface FSM is moved into an invalid state upon local escalation." + } + { name: "KDI.FSM.LOCAL_ESC", + desc: "The key derivation interface FSM is moved into an invalid state upon local escalation." + } + { name: "PART.FSM.LOCAL_ESC", + desc: "The partition FSMs are moved into an invalid state upon local escalation." + } + { name: "SCRMBL.FSM.LOCAL_ESC", + desc: "The scramble datapath FSM is moved into an invalid state upon local escalation." + } + { name: "TIMER.FSM.LOCAL_ESC", + desc: "The background check timer FSM is moved into an invalid state upon local escalation." + } + { name: "DAI.FSM.GLOBAL_ESC", + desc: "The direct access interface FSM is moved into an invalid state upon global escalation via life cycle." + } + { name: "LCI.FSM.GLOBAL_ESC", + desc: "The life cycle interface FSM is moved into an invalid state upon global escalation via life cycle." + } + { name: "KDI.FSM.GLOBAL_ESC", + desc: "The key derivation interface FSM is moved into an invalid state upon global escalation via life cycle." + } + { name: "PART.FSM.GLOBAL_ESC", + desc: "The partition FSMs are moved into an invalid state upon global escalation via life cycle." + } + { name: "SCRMBL.FSM.GLOBAL_ESC", + desc: "The scramble datapath FSM is moved into an invalid state upon global escalation via life cycle." + } + { name: "TIMER.FSM.GLOBAL_ESC", + desc: "The background check timer FSM is moved into an invalid state upon global escalation via life cycle." + } + { name: "PART.DATA_REG.INTEGRITY", + desc: "All partition buffer registers are protected with ECC on 64bit blocks." + } + { name: "PART.DATA_REG.BKGN_CHK", + desc: "The digest of buffered partitions is recomputed and checked at pseudorandom intervals in the background." + } + { name: "PART.MEM.REGREN" + desc: "Unbuffered ('software') partitions can be read-locked via a CSR until the next system reset." + } + { name: "PART.MEM.SW_UNREADABLE" + desc: "Secret buffered partitions become unreadable to software once they are locked via the digest." + } + { name: "PART.MEM.SW_UNWRITABLE" + desc: "All partitions become unwritable by software once they are locked via the digest." + } + { name: "LC_PART.MEM.SW_NOACCESS" + desc: "The life cycle partition is not directly readable nor writable via software." + } + { name: "ACCESS.CTRL.MUBI", + desc: "The access control signals going from the partitions to the DAI are MUBI encoded." + } + { name: "TOKEN_VALID.CTRL.MUBI", + desc: "The token valid signals going to the life cycle controller are MUBI encoded." + } + { name: "LC_CTRL.INTERSIG.MUBI", + desc: "The life cycle control signals are multibit encoded." + } + { name: "TEST.BUS.LC_GATED", + desc: "Prevent access to test signals and the OTP backdoor interface in non-test lifecycle states." + } + { name: "TEST_TL_LC_GATE.FSM.SPARSE", + desc: "The control FSM inside the TL-UL gating primitive is sparsely encoded." + } + { name: "DIRECT_ACCESS.CONFIG.REGWEN", + desc: "The direct access CSRs are REGWEN protected." + } + { name: "CHECK_TRIGGER.CONFIG.REGWEN", + desc: "The check trigger CSR is REGWEN protected." + } + { name: "CHECK.CONFIG.REGWEN", + desc: "The check CSR is REGWEN protected." + } + { name: "MACRO.MEM.INTEGRITY", + desc: ''' + The OTP macro employs a vendor-specific integrity scheme at the granularity of the native 16bit OTP words. + The scheme is able to at least detect single bit errors. + ''' + } + { name: "MACRO.MEM.CM", + desc: "The OTP macro may contain additional vendor-specific countermeasures." + } + ] + + features: [ + { + name: "OTP_CTRL.PARTITION.VENDOR_TEST" + desc: '''Vendor test partition is used for OTP programming smoke check during manufacturing flow. + In this partition, ECC uncorrectable errors will not lead to fatal errors and alerts. + Instead the error will be reported as correctable ECC error. + ''' + } + { + name: "OTP_CTRL.PARTITION.CREATOR_SW_CFG" + desc: '''During calibration stage, various parameters (clock, voltage, and timing sources) are calibrated and recorded to CREATOR_SW_CFG partition. + ''' + } + { + name: "OTP_CTRL.INIT" + desc: '''When power is up, OTP controller reads devices status. + After all reads complete, the controller performs integrity check on the HW_CFG* and SECRET partitions. + Once all integrity checks are complete, the controller marks outputs as valid. + ''' + } + { + name: "OTP_CTRL.PROGRAM" + desc: '''All other partitions except life cycle partition are programmed through DAI interface. + And once non-zero digest is programmed to these partition, no further write access is allowed. + Life cycle partition is programmed by LC_CTRL. + ''' + } + { + name: "OTP_CTRL.PARTITION.SECRET0" + desc: "Obfuscated UDS Seed" + } + { + name: "OTP_CTRL.PARTITION.SECRET1" + desc: "Obfuscated Field Entropy" + } + { + name: "OTP_CTRL.PARTITION.LIFE_CYCLE" + desc: '''LC state, LC transition count. + This feature is owned by the LC_CTRL and cannot be tested well through the OTP_CTRL CSR interface. + ''' + } + { + name: "OTP_CTRL.PARTITIONS_FEATURE.READ_LOCK" + desc: '''Following partitions can be read lockable by CSR. + - VENDOR_TEST + - CREATOR_SW_CFG + Following partitions can be read lockable by writing digest. + - SECRET0 + - SECRET1 + All read attempt to these partitions after read is locked will trigger AccessError (recoverable). + ''' + } + { + name: "OTP_CTRL.PARTITIONS_FEATURE.WRITE_LOCK" + desc: "All partitions except LIFE_CYCLE can be write lockable by writing digest." + } + { + name: "OTP_CTRL.ERROR_HANDLING.RECOVERABLE" + desc: "Recoverable error is created when unauthorized access atempt are detected via dai interface." + } + { + name: "OTP_CTRL.ERROR_HANDLING.FATAL" + desc: "Unrecoverable errors are created for uncorrectable ecc error, otp macro malfunction and unauthorized access via lc_ctrl." + } + { + name: "OTP_CTRL.BACKGROUND_CHECK.CHECK_TIMEOUT" + desc: "Timeout value for the integrity and consistency checks." + } + { + name: "OTP_CTRL.BACKGROUND_CHECK.INTEGRITY_CHECK_PERIOD" + desc: "The interval which the digest of the partition is recomputed to check integrity of locked partition." + } + { + name: "OTP_CTRL.BACKGROUND_CHECK.CONSISTENCY_CHECK_PERIOD" + desc: "Re-read period of the buffer registers to ensure data is matched with the associated OTP partition." + } + ] + + /////////////// + // Registers // + /////////////// + + regwidth: "32", + registers: { + core: [ + //////////////////////// + // Ctrl / Status CSRs // + //////////////////////// + + { name: "STATUS", + desc: "OTP status register.", + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + resval: 0, + tags: [ // OTP internal HW can modify status register + "excl:CsrAllTests:CsrExclCheck"], + fields: [ + { bits: "0" + name: "VENDOR_TEST_ERROR" + desc: ''' + Set to 1 if an error occurred in this partition. + If set to 1, SW should check the !!ERR_CODE register at the corresponding index. + ''' + } + { bits: "1" + name: "NON_SECRET_FUSES_ERROR" + desc: ''' + Set to 1 if an error occurred in this partition. + If set to 1, SW should check the !!ERR_CODE register at the corresponding index. + ''' + } + { bits: "2" + name: "SECRET0_ERROR" + desc: ''' + Set to 1 if an error occurred in this partition. + If set to 1, SW should check the !!ERR_CODE register at the corresponding index. + ''' + } + { bits: "3" + name: "SECRET1_ERROR" + desc: ''' + Set to 1 if an error occurred in this partition. + If set to 1, SW should check the !!ERR_CODE register at the corresponding index. + ''' + } + { bits: "4" + name: "SECRET2_ERROR" + desc: ''' + Set to 1 if an error occurred in this partition. + If set to 1, SW should check the !!ERR_CODE register at the corresponding index. + ''' + } + { bits: "5" + name: "SECRET3_ERROR" + desc: ''' + Set to 1 if an error occurred in this partition. + If set to 1, SW should check the !!ERR_CODE register at the corresponding index. + ''' + } + { bits: "6" + name: "LIFE_CYCLE_ERROR" + desc: ''' + Set to 1 if an error occurred in this partition. + If set to 1, SW should check the !!ERR_CODE register at the corresponding index. + ''' + } + { bits: "7" + name: "DAI_ERROR" + desc: ''' + Set to 1 if an error occurred in the DAI. + If set to 1, SW should check the !!ERR_CODE register at the corresponding index. + ''' + } + { bits: "8" + name: "LCI_ERROR" + desc: ''' + Set to 1 if an error occurred in the LCI. + If set to 1, SW should check the !!ERR_CODE register at the corresponding index. + ''' + } + { bits: "9" + name: "TIMEOUT_ERROR" + desc: ''' + Set to 1 if an integrity or consistency check times out. + This raises an fatal_check_error alert and is an unrecoverable error condition. + ''' + } + { bits: "10" + name: "LFSR_FSM_ERROR" + desc: ''' + Set to 1 if the LFSR timer FSM has reached an invalid state. + This raises an fatal_check_error alert and is an unrecoverable error condition. + ''' + } + { bits: "11" + name: "SCRAMBLING_FSM_ERROR" + desc: ''' + Set to 1 if the scrambling datapath FSM has reached an invalid state. + This raises an fatal_check_error alert and is an unrecoverable error condition. + ''' + } + { bits: "12" + name: "KEY_DERIV_FSM_ERROR" + desc: ''' + Set to 1 if the key derivation FSM has reached an invalid state. + This raises an fatal_check_error alert and is an unrecoverable error condition. + ''' + } + { bits: "13" + name: "BUS_INTEG_ERROR" + desc: ''' + This bit is set to 1 if a fatal bus integrity fault is detected. + This error triggers a fatal_bus_integ_error alert. + ''' + } + { bits: "14" + name: "DAI_IDLE" + desc: "Set to 1 if the DAI is idle and ready to accept commands." + } + { bits: "15" + name: "CHECK_PENDING" + desc: "Set to 1 if an integrity or consistency check triggered by the LFSR timer or via !!CHECK_TRIGGER is pending." + } + ] + } + { multireg: { + name: "ERR_CODE", + desc: ''' + This register holds information about error conditions that occurred in the agents + interacting with the OTP macro via the internal bus. The error codes should be checked + if the partitions, DAI or LCI flag an error in the !!STATUS register, or when an + !!INTR_STATE.otp_error has been triggered. Note that all errors trigger an otp_error + interrupt, and in addition some errors may trigger either an fatal_macro_error or an + fatal_check_error alert. + ''', + count: "NumErrorEntries", + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + cname: "AGENT", + compact: "false", + resval: 0, + tags: [ // OTP internal HW can modify the error code registers + "excl:CsrAllTests:CsrExclCheck"], + fields: [ + { + bits: "2:0" + enum: [ + { value: "0", + name: "NO_ERROR", + desc: ''' + No error condition has occurred. + ''' + }, + { value: "1", + name: "MACRO_ERROR", + desc: ''' + Returned if the OTP macro command was invalid or did not complete successfully + due to a macro malfunction. + This error should never occur during normal operation and is not recoverable. + This error triggers an fatal_macro_error alert. + ''' + }, + { value: "2", + name: "MACRO_ECC_CORR_ERROR", + desc: ''' + A correctable ECC error has occured during an OTP read operation. + The corresponding controller automatically recovers from this error when + issuing a new command. + ''' + }, + { value: "3", + name: "MACRO_ECC_UNCORR_ERROR", + desc: ''' + An uncorrectable ECC error has occurred during an OTP read operation. + This error should never occur during normal operation and is not recoverable. + If this error is present this may be a sign that the device is malfunctioning. + This error triggers an fatal_macro_error alert. + ''' + }, + { value: "4", + name: "MACRO_WRITE_BLANK_ERROR", + desc: ''' + This error is returned if a programming operation attempted to clear a bit that has previously been programmed to 1. + The corresponding controller automatically recovers from this error when issuing a new command. + + Note however that the affected OTP word may be left in an inconsistent state if this error occurs. + This can cause several issues when the word is accessed again (either as part of a regular read operation, as part of the readout at boot, or as part of a background check). + + It is important that SW ensures that each word is only written once, since this can render the device useless. + ''' + }, + { value: "5", + name: "ACCESS_ERROR", + desc: ''' + This error indicates that a locked memory region has been accessed. + The corresponding controller automatically recovers from this error when issuing a new command. + ''' + }, + { value: "6", + name: "CHECK_FAIL_ERROR", + desc: ''' + An ECC, integrity or consistency mismatch has been detected in the buffer registers. + This error should never occur during normal operation and is not recoverable. + This error triggers an fatal_check_error alert. + ''' + }, + { value: "7", + name: "FSM_STATE_ERROR", + desc: ''' + The FSM of the corresponding controller has reached an invalid state, or the FSM has + been moved into a terminal error state due to an escalation action via lc_escalate_en_i. + This error should never occur during normal operation and is not recoverable. + If this error is present, this is a sign that the device has fallen victim to + an invasive attack. This error triggers an fatal_check_error alert. + ''' + }, + ] + } + ] + } + } + { name: "DIRECT_ACCESS_REGWEN", + desc: ''' + Register write enable for all direct access interface registers. + ''', + swaccess: "rw0c", + hwaccess: "hrw", + hwext: "true", + hwqe: "true", + tags: [ // OTP internal HW will set this enable register to 0 when OTP is not under IDLE + // state, so could not auto-predict its value + "excl:CsrNonInitTests:CsrExclCheck"], + fields: [ + { + bits: "0", + name: "WR_EN" + desc: ''' + This bit controls whether the DAI registers can be written. + Write 0 to it in order to clear the bit. + + Note that the hardware also modulates this bit and sets it to 0 temporarily + during an OTP operation such that the corresponding address and data registers + cannot be modified while an operation is pending. The !!DAI_IDLE status bit + will also be set to 0 in such a case. + ''' + resval: 1, + }, + ] + }, + { name: "DIRECT_ACCESS_CMD", + desc: "Command register for direct accesses.", + swaccess: "r0w1c", + hwaccess: "hro", + hwqe: "true", + hwext: "true", + resval: 0, + regwen: "DIRECT_ACCESS_REGWEN", + tags: [ // Write to DIRECT_ACCESS_CMD randomly might cause OTP_ERRORs and illegal sequences + "excl:CsrNonInitTests:CsrExclWrite"], + fields: [ + { bits: "0", + name: "RD", + desc: ''' + Initiates a readout sequence that reads the location specified + by !!DIRECT_ACCESS_ADDRESS. The command places the data read into + !!DIRECT_ACCESS_RDATA_0 and !!DIRECT_ACCESS_RDATA_1 (for 64bit partitions). + ''' + } + { bits: "1", + name: "WR", + desc: ''' + Initiates a programming sequence that writes the data in !!DIRECT_ACCESS_WDATA_0 + and !!DIRECT_ACCESS_WDATA_1 (for 64bit partitions) to the location specified by + !!DIRECT_ACCESS_ADDRESS. + ''' + } + { bits: "2", + name: "DIGEST", + desc: ''' + Initiates the digest calculation and locking sequence for the partition specified by + !!DIRECT_ACCESS_ADDRESS. + ''' + } + ] + } + { name: "DIRECT_ACCESS_ADDRESS", + desc: "Address register for direct accesses.", + swaccess: "rw", + hwaccess: "hro", + hwqe: "false", + resval: 0, + regwen: "DIRECT_ACCESS_REGWEN", + tags: [ // The enable register "DIRECT_ACCESS_REGWEN" is HW controlled, + // so not able to predict this register value automatically + "excl:CsrNonInitTests:CsrExclCheck"], + fields: [ + { bits: "OtpByteAddrWidth-1:0", + name: "ADDR" + desc: ''' + This is the address for the OTP word to be read or written through + the direct access interface. Note that the address is aligned to the access size + internally, hence bits 1:0 are ignored for 32bit accesses, and bits 2:0 are ignored + for 64bit accesses. + + For the digest calculation command, set this register to the partition base offset. + ''' + } + ] + } + { multireg: { + name: "DIRECT_ACCESS_WDATA", + desc: '''Write data for direct accesses. + Hardware automatically determines the access granule (32bit or 64bit) based on which + partition is being written to. + ''', + count: "NumDaiWords", // 2 x 32bit = 64bit + swaccess: "rw", + hwaccess: "hro", + hwqe: "false", + regwen: "DIRECT_ACCESS_REGWEN", + cname: "WORD", + resval: 0, + tags: [ // The value of this register is written from "DIRECT_ACCESS_RDATA", + // so could not predict this register value automatically + "excl:CsrAllTests:CsrExclCheck"], + fields: [ + { bits: "31:0" + name: "WDATA" + } + ] + } + }, + { multireg: { + name: "DIRECT_ACCESS_RDATA", + desc: '''Read data for direct accesses. + Hardware automatically determines the access granule (32bit or 64bit) based on which + partition is read from. + ''', + count: "NumDaiWords", // 2 x 32bit = 64bit + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + cname: "WORD", + resval: 0, + fields: [ + { bits: "31:0" + name: "RDATA" + } + ] + } + }, + + ////////////////////////////////////// + // Integrity and Consistency Checks // + ////////////////////////////////////// + { name: "CHECK_TRIGGER_REGWEN", + desc: ''' + Register write enable for !!CHECK_TRIGGER. + ''', + swaccess: "rw0c", + hwaccess: "none", + fields: [ + { bits: "0", + name: "WR_EN" + desc: ''' + When cleared to 0, the !!CHECK_TRIGGER register cannot be written anymore. + Write 0 to clear this bit. + ''' + resval: 1, + }, + ] + }, + { name: "CHECK_TRIGGER", + desc: "Command register for direct accesses.", + swaccess: "r0w1c", + hwaccess: "hro", + hwqe: "true", + hwext: "true", + resval: 0, + regwen: "CHECK_TRIGGER_REGWEN", + fields: [ + { bits: "0", + name: "INTEGRITY", + desc: ''' + Writing 1 to this bit triggers an integrity check. SW should monitor !!STATUS.CHECK_PENDING + and wait until the check has been completed. If there are any errors, those will be flagged + in the !!STATUS and !!ERR_CODE registers, and via the interrupts and alerts. + ''' + } + { bits: "1", + name: "CONSISTENCY", + desc: ''' + Writing 1 to this bit triggers a consistency check. SW should monitor !!STATUS.CHECK_PENDING + and wait until the check has been completed. If there are any errors, those will be flagged + in the !!STATUS and !!ERR_CODE registers, and via interrupts and alerts. + ''' + } + ] + }, + { name: "CHECK_REGWEN", + desc: ''' + Register write enable for !!INTEGRITY_CHECK_PERIOD and !!CONSISTENCY_CHECK_PERIOD. + ''', + swaccess: "rw0c", + hwaccess: "none", + fields: [ + { bits: "0", + name: "WR_EN" + desc: ''' + When cleared to 0, !!INTEGRITY_CHECK_PERIOD and !!CONSISTENCY_CHECK_PERIOD registers cannot be written anymore. + Write 0 to clear this bit. + ''' + resval: 1, + }, + ] + }, + { name: "CHECK_TIMEOUT", + desc: ''' + Timeout value for the integrity and consistency checks. + ''', + swaccess: "rw", + hwaccess: "hro", + regwen: "CHECK_REGWEN", + tags: [ // Do not write to this automatically, as it may trigger fatal alert, and cause + // escalation. + "excl:CsrAllTests:CsrExclWrite"], + fields: [ + { bits: "31:0", + name: "TIMEOUT" + desc: ''' + Timeout value in cycles for the for the integrity and consistency checks. If an integrity or consistency + check does not complete within the timeout window, an error will be flagged in the !!STATUS register, + an otp_error interrupt will be raised, and an fatal_check_error alert will be sent out. The timeout should + be set to a large value to stay on the safe side. The maximum check time can be upper bounded by the + number of cycles it takes to readout, scramble and digest the entire OTP array. Since this amounts to + roughly 25k cycles, it is recommended to set this value to at least 100'000 cycles in order to stay on the + safe side. A value of zero disables the timeout mechanism (default). + ''' + resval: 0, + }, + ] + }, + { name: "INTEGRITY_CHECK_PERIOD", + desc: ''' + This value specifies the maximum period that can be generated pseudo-randomly. + Only applies to the HW_CFG* and SECRET* partitions once they are locked. + ''' + swaccess: "rw", + hwaccess: "hro", + regwen: "CHECK_REGWEN", + fields: [ + { bits: "31:0", + name: "INTG_PERIOD" + desc: ''' + The pseudo-random period is generated using a 40bit LFSR internally, and this register defines + the bit mask to be applied to the LFSR output in order to limit its range. The value of this + register is left shifted by 8bits and the lower bits are set to 8'hFF in order to form the 40bit mask. + A recommended value is 0x3_FFFF, corresponding to a maximum period of ~2.8s at 24MHz. + A value of zero disables the timer (default). Note that a one-off check can always be triggered via + !!CHECK_TRIGGER.INTEGRITY. + ''' + resval: "0" + } + ] + } + { name: "CONSISTENCY_CHECK_PERIOD", + desc: ''' + This value specifies the maximum period that can be generated pseudo-randomly. + This applies to the LIFE_CYCLE partition and the HW_CFG* and SECRET* partitions once they are locked. + ''' + swaccess: "rw", + hwaccess: "hro", + regwen: "CHECK_REGWEN", + fields: [ + { bits: "31:0", + name: "CONS_PERIOD" + desc: ''' + The pseudo-random period is generated using a 40bit LFSR internally, and this register defines + the bit mask to be applied to the LFSR output in order to limit its range. The value of this + register is left shifted by 8bits and the lower bits are set to 8'hFF in order to form the 40bit mask. + A recommended value is 0x3FF_FFFF, corresponding to a maximum period of ~716s at 24MHz. + A value of zero disables the timer (default). Note that a one-off check can always be triggered via + !!CHECK_TRIGGER.CONSISTENCY. + ''' + resval: "0" + } + ] + } + + //////////////////////////////////// + // Dynamic Locks of SW Parititons // + //////////////////////////////////// + { name: "VENDOR_TEST_READ_LOCK", + desc: ''' + Runtime read lock for the VENDOR_TEST partition. + ''', + swaccess: "rw0c", + hwaccess: "hro", + regwen: "DIRECT_ACCESS_REGWEN", + tags: [ // The value of this register can affect the read access of the this + // partition's memory window. Excluding this register from writing can ensure + // memories have read and write access. + "excl:CsrNonInitTests:CsrExclWrite"], + fields: [ + { bits: "0", + name: "RD_LOCK" + desc: ''' + When cleared to 0, read access to the VENDOR_TEST partition is locked. + Write 0 to clear this bit. + ''' + resval: 1, + }, + ] + }, + { name: "NON_SECRET_FUSES_READ_LOCK", + desc: ''' + Runtime read lock for the NON_SECRET_FUSES partition. + ''', + swaccess: "rw0c", + hwaccess: "hro", + regwen: "DIRECT_ACCESS_REGWEN", + tags: [ // The value of this register can affect the read access of the this + // partition's memory window. Excluding this register from writing can ensure + // memories have read and write access. + "excl:CsrNonInitTests:CsrExclWrite"], + fields: [ + { bits: "0", + name: "RD_LOCK" + desc: ''' + When cleared to 0, read access to the NON_SECRET_FUSES partition is locked. + Write 0 to clear this bit. + ''' + resval: 1, + }, + ] + }, + + /////////////////////// + // Integrity Digests // + /////////////////////// + { multireg: { + name: "VENDOR_TEST_DIGEST", + desc: ''' + Integrity digest for the VENDOR_TEST partition. + The integrity digest is 0 by default. Software must write this + digest value via the direct access interface in order to lock the partition. + After a reset, write access to the VENDOR_TEST partition is locked and + the digest becomes visible in this CSR. + ''', + count: "NumDigestWords", + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + cname: "WORD", + resval: 0, + tags: [ // OTP internal HW will update status so can not auto-predict its value. + "excl:CsrAllTests:CsrExclCheck"], + fields: [ + { bits: "31:0" + name: "DIGEST" + } + ] + } + }, + { multireg: { + name: "NON_SECRET_FUSES_DIGEST", + desc: ''' + Integrity digest for the NON_SECRET_FUSES partition. + The integrity digest is 0 by default. Software must write this + digest value via the direct access interface in order to lock the partition. + After a reset, write access to the NON_SECRET_FUSES partition is locked and + the digest becomes visible in this CSR. + ''', + count: "NumDigestWords", + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + cname: "WORD", + resval: 0, + tags: [ // OTP internal HW will update status so can not auto-predict its value. + "excl:CsrAllTests:CsrExclCheck"], + fields: [ + { bits: "31:0" + name: "DIGEST" + } + ] + } + }, + { multireg: { + name: "SECRET0_DIGEST", + desc: ''' + Integrity digest for the SECRET0 partition. + The integrity digest is 0 by default. The digest calculation can be triggered via the !!DIRECT_ACCESS_CMD. + After a reset, the digest then becomes visible in this CSR, and the corresponding partition becomes write-locked. + ''', + count: "NumDigestWords", + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + cname: "WORD", + resval: 0, + tags: [ // OTP internal HW will update status so can not auto-predict its value. + "excl:CsrAllTests:CsrExclCheck"], + fields: [ + { bits: "31:0" + name: "DIGEST" + } + ] + } + }, + { multireg: { + name: "SECRET1_DIGEST", + desc: ''' + Integrity digest for the SECRET1 partition. + The integrity digest is 0 by default. The digest calculation can be triggered via the !!DIRECT_ACCESS_CMD. + After a reset, the digest then becomes visible in this CSR, and the corresponding partition becomes write-locked. + ''', + count: "NumDigestWords", + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + cname: "WORD", + resval: 0, + tags: [ // OTP internal HW will update status so can not auto-predict its value. + "excl:CsrAllTests:CsrExclCheck"], + fields: [ + { bits: "31:0" + name: "DIGEST" + } + ] + } + }, + { multireg: { + name: "SECRET2_DIGEST", + desc: ''' + Integrity digest for the SECRET2 partition. + The integrity digest is 0 by default. The digest calculation can be triggered via the !!DIRECT_ACCESS_CMD. + After a reset, the digest then becomes visible in this CSR, and the corresponding partition becomes write-locked. + ''', + count: "NumDigestWords", + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + cname: "WORD", + resval: 0, + tags: [ // OTP internal HW will update status so can not auto-predict its value. + "excl:CsrAllTests:CsrExclCheck"], + fields: [ + { bits: "31:0" + name: "DIGEST" + } + ] + } + }, + { multireg: { + name: "SECRET3_DIGEST", + desc: ''' + Integrity digest for the SECRET3 partition. + The integrity digest is 0 by default. The digest calculation can be triggered via the !!DIRECT_ACCESS_CMD. + After a reset, the digest then becomes visible in this CSR, and the corresponding partition becomes write-locked. + ''', + count: "NumDigestWords", + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + cname: "WORD", + resval: 0, + tags: [ // OTP internal HW will update status so can not auto-predict its value. + "excl:CsrAllTests:CsrExclCheck"], + fields: [ + { bits: "31:0" + name: "DIGEST" + } + ] + } + }, + + //////////////////////////////// + // Software Config Partitions // + //////////////////////////////// + { skipto: "0x1000" } + + { window: { + name: "SW_CFG_WINDOW" + items: "NumSwCfgWindowWords" + swaccess: "ro", + desc: ''' + Any read to this window directly maps to the corresponding offset in the creator and owner software + config partitions, and triggers an OTP readout of the bytes requested. Note that the transaction + will block until OTP readout has completed. + ''' + } + } + ], + + // OTP wrapper-specific registers + prim: [ + { name: "CSR0", + desc: "" + swaccess: "rw", + hwaccess: "hro", + hwext: "false", + hwqe: "false", + fields: [ + { bits: "0", + name: "field0", + desc: "", + resval: "0x0", + } + { bits: "1", + name: "field1", + desc: "", + resval: "0x0", + } + { bits: "2", + name: "field2", + desc: "", + resval: "0x0", + } + { bits: "13:4", + name: "field3", + desc: "" + resval: "0x0", + } + { bits: "26:16", + name: "field4", + desc: "" + resval: "0x0", + } + ] + }, + { name: "CSR1", + desc: "" + swaccess: "rw", + hwaccess: "hro", + hwext: "false", + hwqe: "false", + fields: [ + { bits: "6:0", + name: "field0", + desc: "" + resval: "0x0", + } + { bits: "7:7", + name: "field1", + desc: "", + resval: "0x0", + } + { bits: "14:8", + name: "field2", + desc: "" + resval: "0x0", + } + { bits: "15:15", + name: "field3", + desc: "", + resval: "0x0", + } + { bits: "31:16", + name: "field4", + desc: "", + resval: "0x0", + } + ] + }, + { name: "CSR2", + desc: "" + swaccess: "rw", + hwaccess: "hro", + hwext: "false", + hwqe: "false", + fields: [ + { bits: "0", + name: "field0", + desc: "", + resval: "0x0", + } + ] + }, + { name: "CSR3", + desc: "" + swaccess: "rw", + hwaccess: "hrw", + hwext: "false", + hwqe: "false", + fields: [ + { bits: "2:0", + name: "field0", + desc: "" + swaccess: "rw1c", + resval: "0x0", + } + { bits: "13:4", + name: "field1", + desc: "", + swaccess: "rw1c", + resval: "0x0", + } + { bits: "16", + name: "field2", + desc: "", + swaccess: "rw1c", + resval: "0x0", + } + { bits: "17", + name: "field3", + desc: "", + swaccess: "ro", + resval: "0x0", + } + { bits: "18", + name: "field4", + desc: "", + swaccess: "ro", + resval: "0x0", + } + { bits: "19", + name: "field5", + desc: "", + swaccess: "ro", + resval: "0x0", + } + { bits: "20", + name: "field6", + desc: "", + swaccess: "ro", + resval: "0x0", + } + { bits: "21", + name: "field7", + desc: "", + swaccess: "ro", + resval: "0x0", + } + { bits: "22", + name: "field8", + desc: "", + swaccess: "ro", + resval: "0x0", + } + ] + }, + { name: "CSR4", + desc: "" + swaccess: "rw", + hwaccess: "hro", + hwext: "false", + hwqe: "false", + fields: [ + { bits: "9:0", + name: "field0", + desc: "" + resval: "0x0", + } + { bits: "12", + name: "field1", + desc: "" + resval: "0x0", + } + { bits: "13", + name: "field2", + desc: "" + resval: "0x0", + } + { bits: "14", + name: "field3", + desc: "" + resval: "0x0", + } + ] + }, + { name: "CSR5", + desc: "" + swaccess: "rw", + hwaccess: "hrw", + hwext: "false", + hwqe: "false", + fields: [ + { bits: "5:0", + name: "field0", + desc: "" + swaccess: "rw", + resval: "0x0", + } + { bits: "7:6", + name: "field1", + desc: "" + swaccess: "rw", + resval: "0x0", + } + { bits: "8", + name: "field2", + desc: "", + swaccess: "ro", + resval: "0x0", + } + { bits: "11:9", + name: "field3", + desc: "" + swaccess: "ro", + resval: "0x0", + } + { bits: "12", + name: "field4", + desc: "" + swaccess: "ro", + resval: "0x0", + } + { bits: "13", + name: "field5", + desc: "" + swaccess: "ro", + resval: "0x0", + } + { bits: "31:16", + name: "field6", + desc: "" + swaccess: "rw", + resval: "0x0", + } + ] + }, + { name: "CSR6", + desc: "" + swaccess: "rw", + hwaccess: "hro", + hwext: "false", + hwqe: "false", + fields: [ + { bits: "9:0", + name: "field0", + desc: "" + resval: "0x0", + } + { bits: "11", + name: "field1", + desc: "", + swaccess: "rw", + resval: "0x0", + } + { bits: "12", + name: "field2", + desc: "", + swaccess: "rw", + resval: "0x0", + } + { bits: "31:16", + name: "field3", + desc: "" + resval: "0x0", + } + ] + }, + { name: "CSR7", + desc: "", + swaccess: "ro", + hwaccess: "hrw", + hwext: "false", + hwqe: "false", + fields: [ + { bits: "5:0", + name: "field0", + desc: "" + swaccess: "ro", + resval: "0x0", + } + { bits: "10:8", + name: "field1", + desc: "", + swaccess: "ro", + resval: "0x0", + } + { bits: "14", + name: "field2", + desc: "", + swaccess: "ro", + resval: "0x0", + } + { bits: "15", + name: "field3", + desc: "", + swaccess: "ro", + resval: "0x0", + } + ] + }, + ] + } +} + + + + + + + + + diff --git a/src/fuse_ctrl/data/otp_ctrl_mod.json b/src/fuse_ctrl/data/otp_ctrl_mod.json new file mode 100644 index 0000000..4cf2165 --- /dev/null +++ b/src/fuse_ctrl/data/otp_ctrl_mod.json @@ -0,0 +1,1943 @@ +{ + "name": "caliptra_otp_ctrl", + "human_name": " Caliptra One-Time Programmable Memory COntroller", + "one_line_desc": "Interfaces integrated one0time programmable memory, supports scrambling, integrity and secure dai_wr_inprogress", + "one_paragraph_desc": "One-Time Programmable (OTP) Memory Controller provides an open source abstraction interface for software and other hardware components such as Life Cycle Controller and Key Manager to interact with an integrated, closed source, proprietary OTP memory.\nOn top of defensive features provided by the proprietary OTP memory to deter side-channel analysis (SCA), fault injection (FI) attacks, and visual and electrical probing, the open source OTP controller features high-level logical security protection such as integrity checks and scrambling, as well as software isolation for when OTP contents are readable and programmable.\nIt features multiple individually-lockable logical partitions, periodic / persistent checking of OTP values, and a separate partition and interface for Life Cycle Controller.", + "cip_id": "16", + "design_spec": "../doc", + "dv_doc": "../doc/dv", + "hw_checklist": "../doc/checklist", + "sw_checklist": "/sw/device/lib/dif/dif_otp_ctrl", + "revisions": [ + { + "version": "0.1.0", + "life_stage": "L1", + "design_stage": "D2", + "verification_stage": "V2", + "dif_stage": "S1", + "commit_id": "127b109e2fab9336e830158abe449a3922544ded", + "notes": "" + }, + { + "version": "1.0.0", + "life_stage": "L1", + "design_stage": "D3", + "verification_stage": "V2S", + "dif_stage": "S2", + "notes": "" + }, + { + "version": "2.0.0", + "life_stage": "L1", + "design_stage": "D2S", + "verification_stage": "V2S", + "dif_stage": "S2", + "notes": "" + } + ], + "clocking": [ + { + "clock": "clk_i", + "reset": "rst_ni", + "primary": true + }, + { + "clock": "clk_edn_i", + "reset": "rst_edn_ni" + } + ], + "scan": "true", + "scan_reset": "true", + "scan_en": "true", + "bus_interfaces": [ + { + "protocol": "tlul", + "direction": "device", + "name": "core" + }, + { + "protocol": "tlul", + "direction": "device", + "name": "prim", + "hier_path": "u_otp.gen_generic.u_impl_generic.u_reg_top" + } + ], + "available_output_list": [ + { + "name": "test", + "width": 8, + "desc": "Test-related GPIOs. Only active in DFT-enabled life cycle states." + } + ], + "interrupt_list": [ + { + "name": "otp_operation_done", + "desc": "A direct access command or digest calculation operation has completed." + }, + { + "name": "otp_error", + "desc": "An error has occurred in the OTP controller. Check the !!ERR_CODE register to get more information." + } + ], + "alert_list": [ + { + "name": "fatal_macro_error", + "desc": "This alert triggers if hardware detects an uncorrectable error during an OTP transaction, for example an uncorrectable ECC error in the OTP array." + }, + { + "name": "fatal_check_error", + "desc": "This alert triggers if any of the background checks fails. This includes the digest checks and concurrent ECC checks in the buffer registers." + }, + { + "name": "fatal_bus_integ_error", + "desc": "This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected." + }, + { + "name": "fatal_prim_otp_alert", + "desc": "Fatal alert triggered inside the OTP primitive, including fatal TL-UL bus integrity faults of the test interface." + }, + { + "name": "recov_prim_otp_alert", + "desc": "Recoverable alert triggered inside the OTP primitive." + } + ], + "param_list": [ + { + "name": "MemInitFile", + "desc": "VMEM file to initialize the OTP macro.", + "type": "", + "default": "\"\"", + "expose": "true", + "local": "false" + }, + { + "name": "RndCnstLfsrSeed", + "desc": "Compile-time random bits for initial LFSR seed", + "type": "otp_ctrl_pkg::lfsr_seed_t", + "randcount": "40", + "randtype": "data" + }, + { + "name": "RndCnstLfsrPerm", + "desc": "Compile-time random permutation for LFSR output", + "type": "otp_ctrl_pkg::lfsr_perm_t", + "randcount": "40", + "randtype": "perm" + }, + { + "name": "RndCnstScrmblKeyInit", + "desc": "Compile-time random permutation for scrambling key/nonce register reset value", + "type": "otp_ctrl_pkg::scrmbl_key_init_t", + "randcount": "256", + "randtype": "data" + }, + { + "name": "NumSramKeyReqSlots", + "desc": "Number of key slots", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "OtpByteAddrWidth", + "desc": "Width of the OTP byte address.", + "type": "int", + "default": "12", + "local": "true" + }, + { + "name": "NumErrorEntries", + "desc": "Number of error register entries.", + "type": "int", + "default": "9", + "local": "true" + }, + { + "name": "NumDaiWords", + "desc": "Number of 32bit words in the DAI.", + "type": "int", + "default": "2", + "local": "true" + }, + { + "name": "NumDigestWords", + "desc": "Size of the digest fields in 32bit words.", + "type": "int", + "default": "2", + "local": "true" + }, + { + "name": "NumSwCfgWindowWords", + "desc": "Size of the TL-UL window in 32bit words. Note that the effective partition size is smaller than that.", + "type": "int", + "default": "1024", + "local": "true" + }, + { + "name": "NumPart", + "desc": "Number of partitions", + "type": "int", + "default": "7", + "local": "true" + }, + { + "name": "NumPartUnbuf", + "desc": "Number of unbuffered partitions", + "type": "int", + "default": "2", + "local": "true" + }, + { + "name": "NumPartBuf", + "desc": "Number of buffered partitions (including 1 lifecycle partition)", + "type": "int", + "default": "5", + "local": "true" + }, + { + "name": "VendorTestOffset", + "desc": "Offset of the VENDOR_TEST partition", + "type": "int", + "default": "0", + "local": "true" + }, + { + "name": "VendorTestSize", + "desc": "Size of the VENDOR_TEST partition", + "type": "int", + "default": "64", + "local": "true" + }, + { + "name": "ScratchOffset", + "desc": "Offset of SCRATCH", + "type": "int", + "default": "0", + "local": "true" + }, + { + "name": "ScratchSize", + "desc": "Size of SCRATCH", + "type": "int", + "default": "56", + "local": "true" + }, + { + "name": "VendorTestDigestOffset", + "desc": "Offset of VENDOR_TEST_DIGEST", + "type": "int", + "default": "56", + "local": "true" + }, + { + "name": "VendorTestDigestSize", + "desc": "Size of VENDOR_TEST_DIGEST", + "type": "int", + "default": "8", + "local": "true" + }, + { + "name": "NonSecretFusesOffset", + "desc": "Offset of the NON_SECRET_FUSES partition", + "type": "int", + "default": "64", + "local": "true" + }, + { + "name": "NonSecretFusesSize", + "desc": "Size of the NON_SECRET_FUSES partition", + "type": "int", + "default": "3736", + "local": "true" + }, + { + "name": "FmcKeyManifestSvnOffset", + "desc": "Offset of FMC_KEY_MANIFEST_SVN", + "type": "int", + "default": "64", + "local": "true" + }, + { + "name": "FmcKeyManifestSvnSize", + "desc": "Size of FMC_KEY_MANIFEST_SVN", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "RuntimeSvnOffset", + "desc": "Offset of RUNTIME_SVN", + "type": "int", + "default": "68", + "local": "true" + }, + { + "name": "RuntimeSvnSize", + "desc": "Size of RUNTIME_SVN", + "type": "int", + "default": "16", + "local": "true" + }, + { + "name": "LmsVerifyOffset", + "desc": "Offset of LMS_VERIFY", + "type": "int", + "default": "84", + "local": "true" + }, + { + "name": "LmsVerifySize", + "desc": "Size of LMS_VERIFY", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "LmsRevocationOffset", + "desc": "Offset of LMS_REVOCATION", + "type": "int", + "default": "88", + "local": "true" + }, + { + "name": "LmsRevocationSize", + "desc": "Size of LMS_REVOCATION", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "KeyManifestPkHashMaskOffset", + "desc": "Offset of KEY_MANIFEST_PK_HASH_MASK", + "type": "int", + "default": "92", + "local": "true" + }, + { + "name": "KeyManifestPkHashMaskSize", + "desc": "Size of KEY_MANIFEST_PK_HASH_MASK", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "OwnerPkHashOffset", + "desc": "Offset of OWNER_PK_HASH", + "type": "int", + "default": "96", + "local": "true" + }, + { + "name": "OwnerPkHashSize", + "desc": "Size of OWNER_PK_HASH", + "type": "int", + "default": "48", + "local": "true" + }, + { + "name": "IdevidCertAttrOffset", + "desc": "Offset of IDEVID_CERT_ATTR", + "type": "int", + "default": "144", + "local": "true" + }, + { + "name": "IdevidCertAttrSize", + "desc": "Size of IDEVID_CERT_ATTR", + "type": "int", + "default": "96", + "local": "true" + }, + { + "name": "IdevidManufHsmIdOffset", + "desc": "Offset of IDEVID_MANUF_HSM_ID", + "type": "int", + "default": "240", + "local": "true" + }, + { + "name": "IdevidManufHsmIdSize", + "desc": "Size of IDEVID_MANUF_HSM_ID", + "type": "int", + "default": "16", + "local": "true" + }, + { + "name": "SocSteppingIdOffset", + "desc": "Offset of SOC_STEPPING_ID", + "type": "int", + "default": "256", + "local": "true" + }, + { + "name": "SocSteppingIdSize", + "desc": "Size of SOC_STEPPING_ID", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "NonSecretFusesDigestOffset", + "desc": "Offset of NON_SECRET_FUSES_DIGEST", + "type": "int", + "default": "3792", + "local": "true" + }, + { + "name": "NonSecretFusesDigestSize", + "desc": "Size of NON_SECRET_FUSES_DIGEST", + "type": "int", + "default": "8", + "local": "true" + }, + { + "name": "Secret0Offset", + "desc": "Offset of the SECRET0 partition", + "type": "int", + "default": "3800", + "local": "true" + }, + { + "name": "Secret0Size", + "desc": "Size of the SECRET0 partition", + "type": "int", + "default": "40", + "local": "true" + }, + { + "name": "TestUnlockTokenOffset", + "desc": "Offset of TEST_UNLOCK_TOKEN", + "type": "int", + "default": "3800", + "local": "true" + }, + { + "name": "TestUnlockTokenSize", + "desc": "Size of TEST_UNLOCK_TOKEN", + "type": "int", + "default": "16", + "local": "true" + }, + { + "name": "TestExitTokenOffset", + "desc": "Offset of TEST_EXIT_TOKEN", + "type": "int", + "default": "3816", + "local": "true" + }, + { + "name": "TestExitTokenSize", + "desc": "Size of TEST_EXIT_TOKEN", + "type": "int", + "default": "16", + "local": "true" + }, + { + "name": "Secret0DigestOffset", + "desc": "Offset of SECRET0_DIGEST", + "type": "int", + "default": "3832", + "local": "true" + }, + { + "name": "Secret0DigestSize", + "desc": "Size of SECRET0_DIGEST", + "type": "int", + "default": "8", + "local": "true" + }, + { + "name": "Secret1Offset", + "desc": "Offset of the SECRET1 partition", + "type": "int", + "default": "3840", + "local": "true" + }, + { + "name": "Secret1Size", + "desc": "Size of the SECRET1 partition", + "type": "int", + "default": "56", + "local": "true" + }, + { + "name": "UdsSeedOffset", + "desc": "Offset of UDS_SEED", + "type": "int", + "default": "3840", + "local": "true" + }, + { + "name": "UdsSeedSize", + "desc": "Size of UDS_SEED", + "type": "int", + "default": "48", + "local": "true" + }, + { + "name": "Secret1DigestOffset", + "desc": "Offset of SECRET1_DIGEST", + "type": "int", + "default": "3888", + "local": "true" + }, + { + "name": "Secret1DigestSize", + "desc": "Size of SECRET1_DIGEST", + "type": "int", + "default": "8", + "local": "true" + }, + { + "name": "Secret2Offset", + "desc": "Offset of the SECRET2 partition", + "type": "int", + "default": "3896", + "local": "true" + }, + { + "name": "Secret2Size", + "desc": "Size of the SECRET2 partition", + "type": "int", + "default": "40", + "local": "true" + }, + { + "name": "FieldEntropyOffset", + "desc": "Offset of FIELD_ENTROPY", + "type": "int", + "default": "3896", + "local": "true" + }, + { + "name": "FieldEntropySize", + "desc": "Size of FIELD_ENTROPY", + "type": "int", + "default": "32", + "local": "true" + }, + { + "name": "Secret2DigestOffset", + "desc": "Offset of SECRET2_DIGEST", + "type": "int", + "default": "3928", + "local": "true" + }, + { + "name": "Secret2DigestSize", + "desc": "Size of SECRET2_DIGEST", + "type": "int", + "default": "8", + "local": "true" + }, + { + "name": "Secret3Offset", + "desc": "Offset of the SECRET3 partition", + "type": "int", + "default": "3936", + "local": "true" + }, + { + "name": "Secret3Size", + "desc": "Size of the SECRET3 partition", + "type": "int", + "default": "72", + "local": "true" + }, + { + "name": "KeyManifestPkHashOffset", + "desc": "Offset of KEY_MANIFEST_PK_HASH", + "type": "int", + "default": "3936", + "local": "true" + }, + { + "name": "KeyManifestPkHashSize", + "desc": "Size of KEY_MANIFEST_PK_HASH", + "type": "int", + "default": "48", + "local": "true" + }, + { + "name": "RmaTokenOffset", + "desc": "Offset of RMA_TOKEN", + "type": "int", + "default": "3984", + "local": "true" + }, + { + "name": "RmaTokenSize", + "desc": "Size of RMA_TOKEN", + "type": "int", + "default": "16", + "local": "true" + }, + { + "name": "Secret3DigestOffset", + "desc": "Offset of SECRET3_DIGEST", + "type": "int", + "default": "4000", + "local": "true" + }, + { + "name": "Secret3DigestSize", + "desc": "Size of SECRET3_DIGEST", + "type": "int", + "default": "8", + "local": "true" + }, + { + "name": "LifeCycleOffset", + "desc": "Offset of the LIFE_CYCLE partition", + "type": "int", + "default": "4008", + "local": "true" + }, + { + "name": "LifeCycleSize", + "desc": "Size of the LIFE_CYCLE partition", + "type": "int", + "default": "88", + "local": "true" + }, + { + "name": "LcTransitionCntOffset", + "desc": "Offset of LC_TRANSITION_CNT", + "type": "int", + "default": "4008", + "local": "true" + }, + { + "name": "LcTransitionCntSize", + "desc": "Size of LC_TRANSITION_CNT", + "type": "int", + "default": "48", + "local": "true" + }, + { + "name": "LcStateOffset", + "desc": "Offset of LC_STATE", + "type": "int", + "default": "4056", + "local": "true" + }, + { + "name": "LcStateSize", + "desc": "Size of LC_STATE", + "type": "int", + "default": "40", + "local": "true" + } + ], + "inter_signal_list": [ + { + "struct": "", + "type": "io", + "name": "otp_ext_voltage_h", + "act": "none", + "default": "'0", + "package": "" + }, + { + "struct": "otp_ast_req", + "type": "uni", + "name": "otp_ast_pwr_seq", + "act": "req", + "default": "'0", + "package": "otp_ctrl_pkg", + "desc": "Power sequencing signals to AST (VDD domain)." + }, + { + "struct": "otp_ast_rsp", + "type": "uni", + "name": "otp_ast_pwr_seq_h", + "act": "rcv", + "default": "'0", + "package": "otp_ctrl_pkg", + "desc": "Power sequencing signals coming from AST (VCC domain)." + }, + { + "struct": "edn", + "type": "req_rsp", + "name": "edn", + "act": "req", + "package": "edn_pkg", + "desc": "Entropy request to the entropy distribution network for LFSR reseeding and ephemeral key derivation." + }, + { + "struct": "pwr_otp", + "type": "req_rsp", + "name": "pwr_otp", + "act": "rsp", + "default": "'0", + "package": "pwrmgr_pkg", + "desc": "Initialization request/acknowledge from/to power manager." + }, + { + "struct": "lc_otp_vendor_test", + "type": "req_rsp", + "name": "lc_otp_vendor_test", + "act": "rsp", + "default": "'0", + "package": "otp_ctrl_pkg", + "desc": "Vendor test control signals from/to the life cycle TAP." + }, + { + "struct": "lc_otp_program", + "type": "req_rsp", + "name": "lc_otp_program", + "act": "rsp", + "default": "'0", + "package": "otp_ctrl_pkg", + "desc": "Life cycle state transition interface." + }, + { + "struct": "otp_lc_data", + "type": "uni", + "name": "otp_lc_data", + "act": "req", + "default": "'0", + "package": "otp_ctrl_pkg", + "desc": "Life cycle state output holding the current life cycle state,\nthe value of the transition counter and the tokens needed for life cycle transitions." + }, + { + "struct": "lc_tx", + "type": "uni", + "name": "lc_escalate_en", + "act": "rcv", + "default": "lc_ctrl_pkg::Off", + "package": "lc_ctrl_pkg", + "desc": "Life cycle escalation enable coming from life cycle controller.\nThis signal moves all FSMs within OTP into the error state." + }, + { + "struct": "lc_tx", + "type": "uni", + "name": "lc_creator_seed_sw_rw_en", + "act": "rcv", + "default": "lc_ctrl_pkg::Off", + "package": "lc_ctrl_pkg", + "desc": "Provision enable qualifier coming from life cycle controller.\nThis signal enables SW read / write access to the RMA_TOKEN and CREATOR_ROOT_KEY_SHARE0 and CREATOR_ROOT_KEY_SHARE1." + }, + { + "struct": "lc_tx", + "type": "uni", + "name": "lc_owner_seed_sw_rw_en", + "act": "rcv", + "default": "lc_ctrl_pkg::Off", + "package": "lc_ctrl_pkg", + "desc": "Provision enable qualifier coming from life cycle controller.\nThis signal enables SW read / write access to the OWNER_SEED." + }, + { + "struct": "lc_tx", + "type": "uni", + "name": "lc_seed_hw_rd_en", + "act": "rcv", + "default": "lc_ctrl_pkg::Off", + "package": "lc_ctrl_pkg", + "desc": "Seed read enable coming from life cycle controller.\nThis signal enables HW read access to the CREATOR_ROOT_KEY_SHARE0 and CREATOR_ROOT_KEY_SHARE1." + }, + { + "struct": "lc_tx", + "type": "uni", + "name": "lc_dft_en", + "act": "rcv", + "default": "lc_ctrl_pkg::Off", + "package": "lc_ctrl_pkg", + "desc": "Test enable qualifier coming from life cycle controller.\nThis signals enables the TL-UL access port to the proprietary OTP IP." + }, + { + "struct": "lc_tx", + "type": "uni", + "name": "lc_check_byp_en", + "act": "rcv", + "default": "lc_ctrl_pkg::Off", + "package": "lc_ctrl_pkg", + "desc": "Life cycle partition check bypass signal.\nThis signal causes the life cycle partition to bypass consistency checks during life cycle state transitions in order to prevent spurious consistency check failures." + }, + { + "struct": "otp_keymgr_key", + "type": "uni", + "name": "otp_keymgr_key", + "act": "req", + "default": "'0", + "package": "otp_ctrl_pkg", + "desc": "Key output to the key manager holding CREATOR_ROOT_KEY_SHARE0 and CREATOR_ROOT_KEY_SHARE1." + }, + { + "struct": "flash_otp_key", + "type": "req_rsp", + "name": "flash_otp_key", + "act": "rsp", + "default": "'0", + "package": "otp_ctrl_pkg", + "desc": "Key derivation interface for FLASH scrambling." + }, + { + "struct": "sram_otp_key", + "width": "4", + "type": "req_rsp", + "name": "sram_otp_key", + "act": "rsp", + "default": "'0", + "package": "otp_ctrl_pkg", + "desc": "Array with key derivation interfaces for SRAM scrambling devices." + }, + { + "struct": "otbn_otp_key", + "type": "req_rsp", + "name": "otbn_otp_key", + "act": "rsp", + "default": "'0", + "package": "otp_ctrl_pkg", + "desc": "Key derivation interface for OTBN scrambling devices." + }, + { + "struct": "otp_broadcast", + "type": "uni", + "name": "otp_broadcast", + "act": "req", + "default": "'0", + "package": "otp_ctrl_part_pkg", + "desc": "Output of the HW partitions with breakout data types." + }, + { + "struct": "ast_obs_ctrl", + "type": "uni", + "name": "obs_ctrl", + "act": "rcv", + "package": "ast_pkg", + "desc": "AST observability control signals." + }, + { + "struct": "logic", + "type": "uni", + "name": "otp_obs", + "act": "req", + "width": "8", + "package": "", + "desc": "AST observability bus." + } + ], + "countermeasures": [ + { + "name": "BUS.INTEGRITY", + "desc": "End-to-end bus integrity scheme." + }, + { + "name": "SECRET.MEM.SCRAMBLE", + "desc": "Secret partitions are scrambled with a full-round PRESENT cipher." + }, + { + "name": "PART.MEM.DIGEST", + "desc": "Integrity of buffered partitions is ensured via a 64bit digest." + }, + { + "name": "DAI.FSM.SPARSE", + "desc": "The direct access interface FSM is sparsely encoded." + }, + { + "name": "KDI.FSM.SPARSE", + "desc": "The key derivation interface FSM is sparsely encoded." + }, + { + "name": "LCI.FSM.SPARSE", + "desc": "The life cycle interface FSM is sparsely encoded." + }, + { + "name": "PART.FSM.SPARSE", + "desc": "The partition FSMs are sparsely encoded." + }, + { + "name": "SCRMBL.FSM.SPARSE", + "desc": "The scramble datapath FSM is sparsely encoded." + }, + { + "name": "TIMER.FSM.SPARSE", + "desc": "The background check timer FSM is sparsely encoded." + }, + { + "name": "DAI.CTR.REDUN", + "desc": "The direct access interface address counter employs a cross-counter implementation." + }, + { + "name": "KDI_SEED.CTR.REDUN", + "desc": "The key derivation interface counter employs a cross-counter implementation." + }, + { + "name": "KDI_ENTROPY.CTR.REDUN", + "desc": "The key derivation entropy counter employs a cross-counter implementation." + }, + { + "name": "LCI.CTR.REDUN", + "desc": "The life cycle interface address counter employs a cross-counter implementation." + }, + { + "name": "PART.CTR.REDUN", + "desc": "The address counter of buffered partitions employs a cross-counter implementation." + }, + { + "name": "SCRMBL.CTR.REDUN", + "desc": "The srambling datapath counter employs a cross-counter implementation." + }, + { + "name": "TIMER_INTEG.CTR.REDUN", + "desc": "The background integrity check timer employs a duplicated counter implementation." + }, + { + "name": "TIMER_CNSTY.CTR.REDUN", + "desc": "The background consistency check timer employs a duplicated counter implementation." + }, + { + "name": "TIMER.LFSR.REDUN", + "desc": "The background check LFSR is duplicated." + }, + { + "name": "DAI.FSM.LOCAL_ESC", + "desc": "The direct access interface FSM is moved into an invalid state upon local escalation." + }, + { + "name": "LCI.FSM.LOCAL_ESC", + "desc": "The life cycle interface FSM is moved into an invalid state upon local escalation." + }, + { + "name": "KDI.FSM.LOCAL_ESC", + "desc": "The key derivation interface FSM is moved into an invalid state upon local escalation." + }, + { + "name": "PART.FSM.LOCAL_ESC", + "desc": "The partition FSMs are moved into an invalid state upon local escalation." + }, + { + "name": "SCRMBL.FSM.LOCAL_ESC", + "desc": "The scramble datapath FSM is moved into an invalid state upon local escalation." + }, + { + "name": "TIMER.FSM.LOCAL_ESC", + "desc": "The background check timer FSM is moved into an invalid state upon local escalation." + }, + { + "name": "DAI.FSM.GLOBAL_ESC", + "desc": "The direct access interface FSM is moved into an invalid state upon global escalation via life cycle." + }, + { + "name": "LCI.FSM.GLOBAL_ESC", + "desc": "The life cycle interface FSM is moved into an invalid state upon global escalation via life cycle." + }, + { + "name": "KDI.FSM.GLOBAL_ESC", + "desc": "The key derivation interface FSM is moved into an invalid state upon global escalation via life cycle." + }, + { + "name": "PART.FSM.GLOBAL_ESC", + "desc": "The partition FSMs are moved into an invalid state upon global escalation via life cycle." + }, + { + "name": "SCRMBL.FSM.GLOBAL_ESC", + "desc": "The scramble datapath FSM is moved into an invalid state upon global escalation via life cycle." + }, + { + "name": "TIMER.FSM.GLOBAL_ESC", + "desc": "The background check timer FSM is moved into an invalid state upon global escalation via life cycle." + }, + { + "name": "PART.DATA_REG.INTEGRITY", + "desc": "All partition buffer registers are protected with ECC on 64bit blocks." + }, + { + "name": "PART.DATA_REG.BKGN_CHK", + "desc": "The digest of buffered partitions is recomputed and checked at pseudorandom intervals in the background." + }, + { + "name": "PART.MEM.REGREN", + "desc": "Unbuffered ('software') partitions can be read-locked via a CSR until the next system reset." + }, + { + "name": "PART.MEM.SW_UNREADABLE", + "desc": "Secret buffered partitions become unreadable to software once they are locked via the digest." + }, + { + "name": "PART.MEM.SW_UNWRITABLE", + "desc": "All partitions become unwritable by software once they are locked via the digest." + }, + { + "name": "LC_PART.MEM.SW_NOACCESS", + "desc": "The life cycle partition is not directly readable nor writable via software." + }, + { + "name": "ACCESS.CTRL.MUBI", + "desc": "The access control signals going from the partitions to the DAI are MUBI encoded." + }, + { + "name": "TOKEN_VALID.CTRL.MUBI", + "desc": "The token valid signals going to the life cycle controller are MUBI encoded." + }, + { + "name": "LC_CTRL.INTERSIG.MUBI", + "desc": "The life cycle control signals are multibit encoded." + }, + { + "name": "TEST.BUS.LC_GATED", + "desc": "Prevent access to test signals and the OTP backdoor interface in non-test lifecycle states." + }, + { + "name": "TEST_TL_LC_GATE.FSM.SPARSE", + "desc": "The control FSM inside the TL-UL gating primitive is sparsely encoded." + }, + { + "name": "DIRECT_ACCESS.CONFIG.REGWEN", + "desc": "The direct access CSRs are REGWEN protected." + }, + { + "name": "CHECK_TRIGGER.CONFIG.REGWEN", + "desc": "The check trigger CSR is REGWEN protected." + }, + { + "name": "CHECK.CONFIG.REGWEN", + "desc": "The check CSR is REGWEN protected." + }, + { + "name": "MACRO.MEM.INTEGRITY", + "desc": " The OTP macro employs a vendor-specific integrity scheme at the granularity of the native 16bit OTP words.\n The scheme is able to at least detect single bit errors.\n " + }, + { + "name": "MACRO.MEM.CM", + "desc": "The OTP macro may contain additional vendor-specific countermeasures." + } + ], + "features": [ + { + "name": "OTP_CTRL.PARTITION.VENDOR_TEST", + "desc": "Vendor test partition is used for OTP programming smoke check during manufacturing flow.\nIn this partition, ECC uncorrectable errors will not lead to fatal errors and alerts.\nInstead the error will be reported as correctable ECC error." + }, + { + "name": "OTP_CTRL.PARTITION.CREATOR_SW_CFG", + "desc": "During calibration stage, various parameters (clock, voltage, and timing sources) are calibrated and recorded to CREATOR_SW_CFG partition." + }, + { + "name": "OTP_CTRL.INIT", + "desc": "When power is up, OTP controller reads devices status.\nAfter all reads complete, the controller performs integrity check on the HW_CFG* and SECRET partitions.\nOnce all integrity checks are complete, the controller marks outputs as valid." + }, + { + "name": "OTP_CTRL.PROGRAM", + "desc": "All other partitions except life cycle partition are programmed through DAI interface.\nAnd once non-zero digest is programmed to these partition, no further write access is allowed.\nLife cycle partition is programmed by LC_CTRL." + }, + { + "name": "OTP_CTRL.PARTITION.SECRET0", + "desc": "Obfuscated UDS Seed" + }, + { + "name": "OTP_CTRL.PARTITION.SECRET1", + "desc": "Obfuscated Field Entropy" + }, + { + "name": "OTP_CTRL.PARTITION.LIFE_CYCLE", + "desc": "LC state, LC transition count.\nThis feature is owned by the LC_CTRL and cannot be tested well through the OTP_CTRL CSR interface." + }, + { + "name": "OTP_CTRL.PARTITIONS_FEATURE.READ_LOCK", + "desc": "Following partitions can be read lockable by CSR.\n - VENDOR_TEST\n - CREATOR_SW_CFG\n Following partitions can be read lockable by writing digest.\n - SECRET0\n - SECRET1\nAll read attempt to these partitions after read is locked will trigger AccessError (recoverable)." + }, + { + "name": "OTP_CTRL.PARTITIONS_FEATURE.WRITE_LOCK", + "desc": "All partitions except LIFE_CYCLE can be write lockable by writing digest." + }, + { + "name": "OTP_CTRL.ERROR_HANDLING.RECOVERABLE", + "desc": "Recoverable error is created when unauthorized access atempt are detected via dai interface." + }, + { + "name": "OTP_CTRL.ERROR_HANDLING.FATAL", + "desc": "Unrecoverable errors are created for uncorrectable ecc error, otp macro malfunction and unauthorized access via lc_ctrl." + }, + { + "name": "OTP_CTRL.BACKGROUND_CHECK.CHECK_TIMEOUT", + "desc": "Timeout value for the integrity and consistency checks." + }, + { + "name": "OTP_CTRL.BACKGROUND_CHECK.INTEGRITY_CHECK_PERIOD", + "desc": "The interval which the digest of the partition is recomputed to check integrity of locked partition." + }, + { + "name": "OTP_CTRL.BACKGROUND_CHECK.CONSISTENCY_CHECK_PERIOD", + "desc": "Re-read period of the buffer registers to ensure data is matched with the associated OTP partition." + } + ], + "regwidth": "32", + "registers": { + "core": [ + { + "name": "STATUS", + "desc": "OTP status register.", + "swaccess": "ro", + "hwaccess": "hwo", + "hwext": "true", + "resval": 0, + "tags": [ + "excl:CsrAllTests:CsrExclCheck" + ], + "fields": [ + { + "bits": "0", + "name": "VENDOR_TEST_ERROR", + "desc": "Set to 1 if an error occurred in this partition.\nIf set to 1, SW should check the !!ERR_CODE register at the corresponding index." + }, + { + "bits": "1", + "name": "NON_SECRET_FUSES_ERROR", + "desc": "Set to 1 if an error occurred in this partition.\nIf set to 1, SW should check the !!ERR_CODE register at the corresponding index." + }, + { + "bits": "2", + "name": "SECRET0_ERROR", + "desc": "Set to 1 if an error occurred in this partition.\nIf set to 1, SW should check the !!ERR_CODE register at the corresponding index." + }, + { + "bits": "3", + "name": "SECRET1_ERROR", + "desc": "Set to 1 if an error occurred in this partition.\nIf set to 1, SW should check the !!ERR_CODE register at the corresponding index." + }, + { + "bits": "4", + "name": "SECRET2_ERROR", + "desc": "Set to 1 if an error occurred in this partition.\nIf set to 1, SW should check the !!ERR_CODE register at the corresponding index." + }, + { + "bits": "5", + "name": "SECRET3_ERROR", + "desc": "Set to 1 if an error occurred in this partition.\nIf set to 1, SW should check the !!ERR_CODE register at the corresponding index." + }, + { + "bits": "6", + "name": "LIFE_CYCLE_ERROR", + "desc": "Set to 1 if an error occurred in this partition.\nIf set to 1, SW should check the !!ERR_CODE register at the corresponding index." + }, + { + "bits": "7", + "name": "DAI_ERROR", + "desc": "Set to 1 if an error occurred in the DAI.\nIf set to 1, SW should check the !!ERR_CODE register at the corresponding index." + }, + { + "bits": "8", + "name": "LCI_ERROR", + "desc": "Set to 1 if an error occurred in the LCI.\nIf set to 1, SW should check the !!ERR_CODE register at the corresponding index." + }, + { + "bits": "9", + "name": "TIMEOUT_ERROR", + "desc": "Set to 1 if an integrity or consistency check times out.\nThis raises an fatal_check_error alert and is an unrecoverable error condition." + }, + { + "bits": "10", + "name": "LFSR_FSM_ERROR", + "desc": "Set to 1 if the LFSR timer FSM has reached an invalid state.\nThis raises an fatal_check_error alert and is an unrecoverable error condition." + }, + { + "bits": "11", + "name": "SCRAMBLING_FSM_ERROR", + "desc": "Set to 1 if the scrambling datapath FSM has reached an invalid state.\nThis raises an fatal_check_error alert and is an unrecoverable error condition." + }, + { + "bits": "12", + "name": "KEY_DERIV_FSM_ERROR", + "desc": "Set to 1 if the key derivation FSM has reached an invalid state.\nThis raises an fatal_check_error alert and is an unrecoverable error condition." + }, + { + "bits": "13", + "name": "BUS_INTEG_ERROR", + "desc": "This bit is set to 1 if a fatal bus integrity fault is detected.\nThis error triggers a fatal_bus_integ_error alert." + }, + { + "bits": "14", + "name": "DAI_IDLE", + "desc": "Set to 1 if the DAI is idle and ready to accept commands." + }, + { + "bits": "15", + "name": "CHECK_PENDING", + "desc": "Set to 1 if an integrity or consistency check triggered by the LFSR timer or via !!CHECK_TRIGGER is pending." + } + ] + }, + { + "multireg": { + "name": "ERR_CODE", + "desc": "This register holds information about error conditions that occurred in the agents\ninteracting with the OTP macro via the internal bus. The error codes should be checked\nif the partitions, DAI or LCI flag an error in the !!STATUS register, or when an\n!!INTR_STATE.otp_error has been triggered. Note that all errors trigger an otp_error\ninterrupt, and in addition some errors may trigger either an fatal_macro_error or an\nfatal_check_error alert.", + "count": "NumErrorEntries", + "swaccess": "ro", + "hwaccess": "hwo", + "hwext": "true", + "cname": "AGENT", + "compact": "false", + "resval": 0, + "tags": [ + "excl:CsrAllTests:CsrExclCheck" + ], + "fields": [ + { + "bits": "2:0", + "enum": [ + { + "value": "0", + "name": "NO_ERROR", + "desc": "No error condition has occurred." + }, + { + "value": "1", + "name": "MACRO_ERROR", + "desc": "Returned if the OTP macro command was invalid or did not complete successfully\ndue to a macro malfunction.\nThis error should never occur during normal operation and is not recoverable.\nThis error triggers an fatal_macro_error alert." + }, + { + "value": "2", + "name": "MACRO_ECC_CORR_ERROR", + "desc": "A correctable ECC error has occured during an OTP read operation.\nThe corresponding controller automatically recovers from this error when\nissuing a new command." + }, + { + "value": "3", + "name": "MACRO_ECC_UNCORR_ERROR", + "desc": "An uncorrectable ECC error has occurred during an OTP read operation.\nThis error should never occur during normal operation and is not recoverable.\nIf this error is present this may be a sign that the device is malfunctioning.\nThis error triggers an fatal_macro_error alert." + }, + { + "value": "4", + "name": "MACRO_WRITE_BLANK_ERROR", + "desc": "This error is returned if a programming operation attempted to clear a bit that has previously been programmed to 1.\nThe corresponding controller automatically recovers from this error when issuing a new command.\n\nNote however that the affected OTP word may be left in an inconsistent state if this error occurs.\nThis can cause several issues when the word is accessed again (either as part of a regular read operation, as part of the readout at boot, or as part of a background check).\n\nIt is important that SW ensures that each word is only written once, since this can render the device useless." + }, + { + "value": "5", + "name": "ACCESS_ERROR", + "desc": "This error indicates that a locked memory region has been accessed.\nThe corresponding controller automatically recovers from this error when issuing a new command." + }, + { + "value": "6", + "name": "CHECK_FAIL_ERROR", + "desc": "An ECC, integrity or consistency mismatch has been detected in the buffer registers.\nThis error should never occur during normal operation and is not recoverable.\nThis error triggers an fatal_check_error alert." + }, + { + "value": "7", + "name": "FSM_STATE_ERROR", + "desc": "The FSM of the corresponding controller has reached an invalid state, or the FSM has\nbeen moved into a terminal error state due to an escalation action via lc_escalate_en_i.\nThis error should never occur during normal operation and is not recoverable.\nIf this error is present, this is a sign that the device has fallen victim to\nan invasive attack. This error triggers an fatal_check_error alert." + } + ] + } + ] + } + }, + { + "name": "DIRECT_ACCESS_REGWEN", + "desc": "Register write enable for all direct access interface registers.", + "swaccess": "rw0c", + "hwaccess": "hrw", + "hwext": "true", + "hwqe": "true", + "tags": [ + "excl:CsrNonInitTests:CsrExclCheck" + ], + "fields": [ + { + "bits": "0", + "name": "WR_EN", + "desc": "This bit controls whether the DAI registers can be written.\nWrite 0 to it in order to clear the bit.\n\nNote that the hardware also modulates this bit and sets it to 0 temporarily\nduring an OTP operation such that the corresponding address and data registers\ncannot be modified while an operation is pending. The !!DAI_IDLE status bit\nwill also be set to 0 in such a case.", + "resval": 1 + } + ] + }, + { + "name": "DIRECT_ACCESS_CMD", + "desc": "Command register for direct accesses.", + "swaccess": "r0w1c", + "hwaccess": "hro", + "hwqe": "true", + "hwext": "true", + "resval": 0, + "regwen": "DIRECT_ACCESS_REGWEN", + "tags": [ + "excl:CsrNonInitTests:CsrExclWrite" + ], + "fields": [ + { + "bits": "0", + "name": "RD", + "desc": "Initiates a readout sequence that reads the location specified\nby !!DIRECT_ACCESS_ADDRESS. The command places the data read into\n!!DIRECT_ACCESS_RDATA_0 and !!DIRECT_ACCESS_RDATA_1 (for 64bit partitions)." + }, + { + "bits": "1", + "name": "WR", + "desc": "Initiates a programming sequence that writes the data in !!DIRECT_ACCESS_WDATA_0\nand !!DIRECT_ACCESS_WDATA_1 (for 64bit partitions) to the location specified by\n!!DIRECT_ACCESS_ADDRESS." + }, + { + "bits": "2", + "name": "DIGEST", + "desc": "Initiates the digest calculation and locking sequence for the partition specified by\n!!DIRECT_ACCESS_ADDRESS." + } + ] + }, + { + "name": "DIRECT_ACCESS_ADDRESS", + "desc": "Address register for direct accesses.", + "swaccess": "rw", + "hwaccess": "hro", + "hwqe": "false", + "resval": 0, + "regwen": "DIRECT_ACCESS_REGWEN", + "tags": [ + "excl:CsrNonInitTests:CsrExclCheck" + ], + "fields": [ + { + "bits": "OtpByteAddrWidth-1:0", + "name": "ADDR", + "desc": "This is the address for the OTP word to be read or written through\nthe direct access interface. Note that the address is aligned to the access size\ninternally, hence bits 1:0 are ignored for 32bit accesses, and bits 2:0 are ignored\nfor 64bit accesses.\n\nFor the digest calculation command, set this register to the partition base offset." + } + ] + }, + { + "multireg": { + "name": "DIRECT_ACCESS_WDATA", + "desc": "Write data for direct accesses.\n Hardware automatically determines the access granule (32bit or 64bit) based on which\n partition is being written to.\n ", + "count": "NumDaiWords", + "swaccess": "rw", + "hwaccess": "hro", + "hwqe": "false", + "regwen": "DIRECT_ACCESS_REGWEN", + "cname": "WORD", + "resval": 0, + "tags": [ + "excl:CsrAllTests:CsrExclCheck" + ], + "fields": [ + { + "bits": "31:0", + "name": "WDATA" + } + ] + } + }, + { + "multireg": { + "name": "DIRECT_ACCESS_RDATA", + "desc": "Read data for direct accesses.\n Hardware automatically determines the access granule (32bit or 64bit) based on which\n partition is read from.\n ", + "count": "NumDaiWords", + "swaccess": "ro", + "hwaccess": "hwo", + "hwext": "true", + "cname": "WORD", + "resval": 0, + "fields": [ + { + "bits": "31:0", + "name": "RDATA" + } + ] + } + }, + { + "name": "CHECK_TRIGGER_REGWEN", + "desc": "Register write enable for !!CHECK_TRIGGER.", + "swaccess": "rw0c", + "hwaccess": "none", + "fields": [ + { + "bits": "0", + "name": "WR_EN", + "desc": "When cleared to 0, the !!CHECK_TRIGGER register cannot be written anymore.\nWrite 0 to clear this bit.", + "resval": 1 + } + ] + }, + { + "name": "CHECK_TRIGGER", + "desc": "Command register for direct accesses.", + "swaccess": "r0w1c", + "hwaccess": "hro", + "hwqe": "true", + "hwext": "true", + "resval": 0, + "regwen": "CHECK_TRIGGER_REGWEN", + "fields": [ + { + "bits": "0", + "name": "INTEGRITY", + "desc": "Writing 1 to this bit triggers an integrity check. SW should monitor !!STATUS.CHECK_PENDING\nand wait until the check has been completed. If there are any errors, those will be flagged\nin the !!STATUS and !!ERR_CODE registers, and via the interrupts and alerts." + }, + { + "bits": "1", + "name": "CONSISTENCY", + "desc": "Writing 1 to this bit triggers a consistency check. SW should monitor !!STATUS.CHECK_PENDING\nand wait until the check has been completed. If there are any errors, those will be flagged\nin the !!STATUS and !!ERR_CODE registers, and via interrupts and alerts." + } + ] + }, + { + "name": "CHECK_REGWEN", + "desc": "Register write enable for !!INTEGRITY_CHECK_PERIOD and !!CONSISTENCY_CHECK_PERIOD.", + "swaccess": "rw0c", + "hwaccess": "none", + "fields": [ + { + "bits": "0", + "name": "WR_EN", + "desc": "When cleared to 0, !!INTEGRITY_CHECK_PERIOD and !!CONSISTENCY_CHECK_PERIOD registers cannot be written anymore.\nWrite 0 to clear this bit.", + "resval": 1 + } + ] + }, + { + "name": "CHECK_TIMEOUT", + "desc": "Timeout value for the integrity and consistency checks.", + "swaccess": "rw", + "hwaccess": "hro", + "regwen": "CHECK_REGWEN", + "tags": [ + "excl:CsrAllTests:CsrExclWrite" + ], + "fields": [ + { + "bits": "31:0", + "name": "TIMEOUT", + "desc": "Timeout value in cycles for the for the integrity and consistency checks. If an integrity or consistency\ncheck does not complete within the timeout window, an error will be flagged in the !!STATUS register,\nan otp_error interrupt will be raised, and an fatal_check_error alert will be sent out. The timeout should\nbe set to a large value to stay on the safe side. The maximum check time can be upper bounded by the\nnumber of cycles it takes to readout, scramble and digest the entire OTP array. Since this amounts to\nroughly 25k cycles, it is recommended to set this value to at least 100'000 cycles in order to stay on the\nsafe side. A value of zero disables the timeout mechanism (default).", + "resval": 0 + } + ] + }, + { + "name": "INTEGRITY_CHECK_PERIOD", + "desc": "This value specifies the maximum period that can be generated pseudo-randomly.\nOnly applies to the HW_CFG* and SECRET* partitions once they are locked.", + "swaccess": "rw", + "hwaccess": "hro", + "regwen": "CHECK_REGWEN", + "fields": [ + { + "bits": "31:0", + "name": "INTG_PERIOD", + "desc": "The pseudo-random period is generated using a 40bit LFSR internally, and this register defines\nthe bit mask to be applied to the LFSR output in order to limit its range. The value of this\nregister is left shifted by 8bits and the lower bits are set to 8'hFF in order to form the 40bit mask.\nA recommended value is 0x3_FFFF, corresponding to a maximum period of ~2.8s at 24MHz.\nA value of zero disables the timer (default). Note that a one-off check can always be triggered via\n!!CHECK_TRIGGER.INTEGRITY.", + "resval": "0" + } + ] + }, + { + "name": "CONSISTENCY_CHECK_PERIOD", + "desc": "This value specifies the maximum period that can be generated pseudo-randomly.\nThis applies to the LIFE_CYCLE partition and the HW_CFG* and SECRET* partitions once they are locked.", + "swaccess": "rw", + "hwaccess": "hro", + "regwen": "CHECK_REGWEN", + "fields": [ + { + "bits": "31:0", + "name": "CONS_PERIOD", + "desc": "The pseudo-random period is generated using a 40bit LFSR internally, and this register defines\nthe bit mask to be applied to the LFSR output in order to limit its range. The value of this\nregister is left shifted by 8bits and the lower bits are set to 8'hFF in order to form the 40bit mask.\nA recommended value is 0x3FF_FFFF, corresponding to a maximum period of ~716s at 24MHz.\nA value of zero disables the timer (default). Note that a one-off check can always be triggered via\n!!CHECK_TRIGGER.CONSISTENCY.", + "resval": "0" + } + ] + }, + { + "name": "VENDOR_TEST_READ_LOCK", + "desc": "Runtime read lock for the VENDOR_TEST partition.", + "swaccess": "rw0c", + "hwaccess": "hro", + "regwen": "DIRECT_ACCESS_REGWEN", + "tags": [ + "excl:CsrNonInitTests:CsrExclWrite" + ], + "fields": [ + { + "bits": "0", + "name": "RD_LOCK", + "desc": "When cleared to 0, read access to the VENDOR_TEST partition is locked.\nWrite 0 to clear this bit.", + "resval": 1 + } + ] + }, + { + "name": "NON_SECRET_FUSES_READ_LOCK", + "desc": "Runtime read lock for the NON_SECRET_FUSES partition.", + "swaccess": "rw0c", + "hwaccess": "hro", + "regwen": "DIRECT_ACCESS_REGWEN", + "tags": [ + "excl:CsrNonInitTests:CsrExclWrite" + ], + "fields": [ + { + "bits": "0", + "name": "RD_LOCK", + "desc": "When cleared to 0, read access to the NON_SECRET_FUSES partition is locked.\nWrite 0 to clear this bit.", + "resval": 1 + } + ] + }, + { + "multireg": { + "name": "VENDOR_TEST_DIGEST", + "desc": " Integrity digest for the VENDOR_TEST partition.\n The integrity digest is 0 by default. Software must write this\n digest value via the direct access interface in order to lock the partition.\n After a reset, write access to the VENDOR_TEST partition is locked and\n the digest becomes visible in this CSR.\n ", + "count": "NumDigestWords", + "swaccess": "ro", + "hwaccess": "hwo", + "hwext": "true", + "cname": "WORD", + "resval": 0, + "tags": [ + "excl:CsrAllTests:CsrExclCheck" + ], + "fields": [ + { + "bits": "31:0", + "name": "DIGEST" + } + ] + } + }, + { + "multireg": { + "name": "NON_SECRET_FUSES_DIGEST", + "desc": " Integrity digest for the NON_SECRET_FUSES partition.\n The integrity digest is 0 by default. Software must write this\n digest value via the direct access interface in order to lock the partition.\n After a reset, write access to the NON_SECRET_FUSES partition is locked and\n the digest becomes visible in this CSR.\n ", + "count": "NumDigestWords", + "swaccess": "ro", + "hwaccess": "hwo", + "hwext": "true", + "cname": "WORD", + "resval": 0, + "tags": [ + "excl:CsrAllTests:CsrExclCheck" + ], + "fields": [ + { + "bits": "31:0", + "name": "DIGEST" + } + ] + } + }, + { + "multireg": { + "name": "SECRET0_DIGEST", + "desc": " Integrity digest for the SECRET0 partition.\n The integrity digest is 0 by default. The digest calculation can be triggered via the !!DIRECT_ACCESS_CMD.\n After a reset, the digest then becomes visible in this CSR, and the corresponding partition becomes write-locked.\n ", + "count": "NumDigestWords", + "swaccess": "ro", + "hwaccess": "hwo", + "hwext": "true", + "cname": "WORD", + "resval": 0, + "tags": [ + "excl:CsrAllTests:CsrExclCheck" + ], + "fields": [ + { + "bits": "31:0", + "name": "DIGEST" + } + ] + } + }, + { + "multireg": { + "name": "SECRET1_DIGEST", + "desc": " Integrity digest for the SECRET1 partition.\n The integrity digest is 0 by default. The digest calculation can be triggered via the !!DIRECT_ACCESS_CMD.\n After a reset, the digest then becomes visible in this CSR, and the corresponding partition becomes write-locked.\n ", + "count": "NumDigestWords", + "swaccess": "ro", + "hwaccess": "hwo", + "hwext": "true", + "cname": "WORD", + "resval": 0, + "tags": [ + "excl:CsrAllTests:CsrExclCheck" + ], + "fields": [ + { + "bits": "31:0", + "name": "DIGEST" + } + ] + } + }, + { + "multireg": { + "name": "SECRET2_DIGEST", + "desc": " Integrity digest for the SECRET2 partition.\n The integrity digest is 0 by default. The digest calculation can be triggered via the !!DIRECT_ACCESS_CMD.\n After a reset, the digest then becomes visible in this CSR, and the corresponding partition becomes write-locked.\n ", + "count": "NumDigestWords", + "swaccess": "ro", + "hwaccess": "hwo", + "hwext": "true", + "cname": "WORD", + "resval": 0, + "tags": [ + "excl:CsrAllTests:CsrExclCheck" + ], + "fields": [ + { + "bits": "31:0", + "name": "DIGEST" + } + ] + } + }, + { + "multireg": { + "name": "SECRET3_DIGEST", + "desc": " Integrity digest for the SECRET3 partition.\n The integrity digest is 0 by default. The digest calculation can be triggered via the !!DIRECT_ACCESS_CMD.\n After a reset, the digest then becomes visible in this CSR, and the corresponding partition becomes write-locked.\n ", + "count": "NumDigestWords", + "swaccess": "ro", + "hwaccess": "hwo", + "hwext": "true", + "cname": "WORD", + "resval": 0, + "tags": [ + "excl:CsrAllTests:CsrExclCheck" + ], + "fields": [ + { + "bits": "31:0", + "name": "DIGEST" + } + ] + } + }, + { + "skipto": "0x1000" + }, + { + "window": { + "name": "SW_CFG_WINDOW", + "items": "NumSwCfgWindowWords", + "swaccess": "ro", + "desc": "Any read to this window directly maps to the corresponding offset in the creator and owner software\nconfig partitions, and triggers an OTP readout of the bytes requested. Note that the transaction\nwill block until OTP readout has completed." + } + } + ], + "prim": [ + { + "name": "CSR0", + "desc": "", + "swaccess": "rw", + "hwaccess": "hro", + "hwext": "false", + "hwqe": "false", + "fields": [ + { + "bits": "0", + "name": "field0", + "desc": "", + "resval": "0x0" + }, + { + "bits": "1", + "name": "field1", + "desc": "", + "resval": "0x0" + }, + { + "bits": "2", + "name": "field2", + "desc": "", + "resval": "0x0" + }, + { + "bits": "13:4", + "name": "field3", + "desc": "", + "resval": "0x0" + }, + { + "bits": "26:16", + "name": "field4", + "desc": "", + "resval": "0x0" + } + ] + }, + { + "name": "CSR1", + "desc": "", + "swaccess": "rw", + "hwaccess": "hro", + "hwext": "false", + "hwqe": "false", + "fields": [ + { + "bits": "6:0", + "name": "field0", + "desc": "", + "resval": "0x0" + }, + { + "bits": "7:7", + "name": "field1", + "desc": "", + "resval": "0x0" + }, + { + "bits": "14:8", + "name": "field2", + "desc": "", + "resval": "0x0" + }, + { + "bits": "15:15", + "name": "field3", + "desc": "", + "resval": "0x0" + }, + { + "bits": "31:16", + "name": "field4", + "desc": "", + "resval": "0x0" + } + ] + }, + { + "name": "CSR2", + "desc": "", + "swaccess": "rw", + "hwaccess": "hro", + "hwext": "false", + "hwqe": "false", + "fields": [ + { + "bits": "0", + "name": "field0", + "desc": "", + "resval": "0x0" + } + ] + }, + { + "name": "CSR3", + "desc": "", + "swaccess": "rw", + "hwaccess": "hrw", + "hwext": "false", + "hwqe": "false", + "fields": [ + { + "bits": "2:0", + "name": "field0", + "desc": "", + "swaccess": "rw1c", + "resval": "0x0" + }, + { + "bits": "13:4", + "name": "field1", + "desc": "", + "swaccess": "rw1c", + "resval": "0x0" + }, + { + "bits": "16", + "name": "field2", + "desc": "", + "swaccess": "rw1c", + "resval": "0x0" + }, + { + "bits": "17", + "name": "field3", + "desc": "", + "swaccess": "ro", + "resval": "0x0" + }, + { + "bits": "18", + "name": "field4", + "desc": "", + "swaccess": "ro", + "resval": "0x0" + }, + { + "bits": "19", + "name": "field5", + "desc": "", + "swaccess": "ro", + "resval": "0x0" + }, + { + "bits": "20", + "name": "field6", + "desc": "", + "swaccess": "ro", + "resval": "0x0" + }, + { + "bits": "21", + "name": "field7", + "desc": "", + "swaccess": "ro", + "resval": "0x0" + }, + { + "bits": "22", + "name": "field8", + "desc": "", + "swaccess": "ro", + "resval": "0x0" + } + ] + }, + { + "name": "CSR4", + "desc": "", + "swaccess": "rw", + "hwaccess": "hro", + "hwext": "false", + "hwqe": "false", + "fields": [ + { + "bits": "9:0", + "name": "field0", + "desc": "", + "resval": "0x0" + }, + { + "bits": "12", + "name": "field1", + "desc": "", + "resval": "0x0" + }, + { + "bits": "13", + "name": "field2", + "desc": "", + "resval": "0x0" + }, + { + "bits": "14", + "name": "field3", + "desc": "", + "resval": "0x0" + } + ] + }, + { + "name": "CSR5", + "desc": "", + "swaccess": "rw", + "hwaccess": "hrw", + "hwext": "false", + "hwqe": "false", + "fields": [ + { + "bits": "5:0", + "name": "field0", + "desc": "", + "swaccess": "rw", + "resval": "0x0" + }, + { + "bits": "7:6", + "name": "field1", + "desc": "", + "swaccess": "rw", + "resval": "0x0" + }, + { + "bits": "8", + "name": "field2", + "desc": "", + "swaccess": "ro", + "resval": "0x0" + }, + { + "bits": "11:9", + "name": "field3", + "desc": "", + "swaccess": "ro", + "resval": "0x0" + }, + { + "bits": "12", + "name": "field4", + "desc": "", + "swaccess": "ro", + "resval": "0x0" + }, + { + "bits": "13", + "name": "field5", + "desc": "", + "swaccess": "ro", + "resval": "0x0" + }, + { + "bits": "31:16", + "name": "field6", + "desc": "", + "swaccess": "rw", + "resval": "0x0" + } + ] + }, + { + "name": "CSR6", + "desc": "", + "swaccess": "rw", + "hwaccess": "hro", + "hwext": "false", + "hwqe": "false", + "fields": [ + { + "bits": "9:0", + "name": "field0", + "desc": "", + "resval": "0x0" + }, + { + "bits": "11", + "name": "field1", + "desc": "", + "swaccess": "rw", + "resval": "0x0" + }, + { + "bits": "12", + "name": "field2", + "desc": "", + "swaccess": "rw", + "resval": "0x0" + }, + { + "bits": "31:16", + "name": "field3", + "desc": "", + "resval": "0x0" + } + ] + }, + { + "name": "CSR7", + "desc": "", + "swaccess": "ro", + "hwaccess": "hrw", + "hwext": "false", + "hwqe": "false", + "fields": [ + { + "bits": "5:0", + "name": "field0", + "desc": "", + "swaccess": "ro", + "resval": "0x0" + }, + { + "bits": "10:8", + "name": "field1", + "desc": "", + "swaccess": "ro", + "resval": "0x0" + }, + { + "bits": "14", + "name": "field2", + "desc": "", + "swaccess": "ro", + "resval": "0x0" + }, + { + "bits": "15", + "name": "field3", + "desc": "", + "swaccess": "ro", + "resval": "0x0" + } + ] + } + ] + } +} diff --git a/src/fuse_ctrl/data/otp_ctrl_orig.hjson b/src/fuse_ctrl/data/otp_ctrl_orig.hjson new file mode 100755 index 0000000..493f7e5 --- /dev/null +++ b/src/fuse_ctrl/data/otp_ctrl_orig.hjson @@ -0,0 +1,3210 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// HJSON with partition metadata. +// +// DO NOT EDIT THIS FILE DIRECTLY. +// It has been generated with ./util/design/gen-otp-mmap.py + +{ + name: "otp_ctrl", + human_name: "One-Time Programmable Memory Controller", + one_line_desc: "Interfaces integrated one-time programmable memory, supports scrambling, integrity and secure wipe", + one_paragraph_desc: ''' + One-Time Programmable (OTP) Memory Controller provides an open source abstraction interface for software and other hardware components such as Life Cycle Controller and Key Manager to interact with an integrated, closed source, proprietary OTP memory. + On top of defensive features provided by the proprietary OTP memory to deter side-channel analysis (SCA), fault injection (FI) attacks, and visual and electrical probing, the open source OTP controller features high-level logical security protection such as integrity checks and scrambling, as well as software isolation for when OTP contents are readable and programmable. + It features multiple individually-lockable logical partitions, periodic / persistent checking of OTP values, and a separate partition and interface for Life Cycle Controller. + ''' + // Unique comportable IP identifier defined under KNOWN_CIP_IDS in the regtool. + cip_id: "16", + design_spec: "../doc", + dv_doc: "../doc/dv", + hw_checklist: "../doc/checklist", + sw_checklist: "/sw/device/lib/dif/dif_otp_ctrl", + revisions: [ + { + version: "0.1.0", + life_stage: "L1", + design_stage: "D2", + verification_stage: "V2", + dif_stage: "S1", + commit_id: "127b109e2fab9336e830158abe449a3922544ded", + notes: "", + } + { + version: "1.0.0", + life_stage: "L1", + design_stage: "D3", + verification_stage: "V2S", + dif_stage: "S2", + notes: "", + } + { + version: "2.0.0", + life_stage: "L1", + design_stage: "D2S", + verification_stage: "V2S", + dif_stage: "S2", + notes: "", + } + ] + clocking: [ + {clock: "clk_i", reset: "rst_ni", primary: true}, + {clock: "clk_edn_i", reset: "rst_edn_ni"} + ] + scan: "true", // Enable `scanmode_i` port + scan_reset: "true", // Enable `scan_rst_ni` port + scan_en: "true", // Enable `scan_en_i` port + bus_interfaces: [ + { protocol: "tlul", direction: "device", name: "core" } + { protocol: "tlul", direction: "device", name: "prim", hier_path: "u_otp.gen_generic.u_impl_generic.u_reg_top" } + ], + + available_output_list: [ + { name: "test", + width: 8, + desc: "Test-related GPIOs. Only active in DFT-enabled life cycle states." + } + ], + + /////////////////////////// + // Interrupts and Alerts // + /////////////////////////// + + interrupt_list: [ + { name: "otp_operation_done", + desc: "A direct access command or digest calculation operation has completed." + } + { name: "otp_error", + desc: "An error has occurred in the OTP controller. Check the !!ERR_CODE register to get more information." + } + ], + + alert_list: [ + { name: "fatal_macro_error", + desc: "This alert triggers if hardware detects an uncorrectable error during an OTP transaction, for example an uncorrectable ECC error in the OTP array.", + } + { name: "fatal_check_error", + desc: "This alert triggers if any of the background checks fails. This includes the digest checks and concurrent ECC checks in the buffer registers.", + } + { name: "fatal_bus_integ_error", + desc: "This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected." + } + { name: "fatal_prim_otp_alert", + desc: "Fatal alert triggered inside the OTP primitive, including fatal TL-UL bus integrity faults of the test interface." + } + { name: "recov_prim_otp_alert", + desc: "Recoverable alert triggered inside the OTP primitive." + } + ], + + //////////////// + // Parameters // + //////////////// + param_list: [ + // Init file + { name: "MemInitFile", + desc: "VMEM file to initialize the OTP macro.", + type: "", + default: '""', + expose: "true", + local: "false" + } + // Random netlist constants + { name: "RndCnstLfsrSeed", + desc: "Compile-time random bits for initial LFSR seed", + type: "otp_ctrl_pkg::lfsr_seed_t" + randcount: "40", + randtype: "data", // randomize randcount databits + } + { name: "RndCnstLfsrPerm", + desc: "Compile-time random permutation for LFSR output", + type: "otp_ctrl_pkg::lfsr_perm_t" + randcount: "40", + randtype: "perm", // random permutation for randcount elements + } + { name: "RndCnstScrmblKeyInit", + desc: "Compile-time random permutation for scrambling key/nonce register reset value", + type: "otp_ctrl_pkg::scrmbl_key_init_t" + randcount: "256", + randtype: "data", // random permutation for randcount elements + } + // Normal parameters + { name: "NumSramKeyReqSlots", + desc: "Number of key slots", + type: "int", + default: "4", + local: "true" + }, + { name: "OtpByteAddrWidth", + desc: "Width of the OTP byte address.", + type: "int", + default: "11", + local: "true" + }, + { name: "NumErrorEntries", + desc: "Number of error register entries.", + type: "int", + default: "13", // partitions + DAI/LCI + local: "true" + }, + { name: "NumDaiWords", + desc: "Number of 32bit words in the DAI.", + type: "int", + default: "2", + local: "true" + }, + { name: "NumDigestWords", + desc: "Size of the digest fields in 32bit words.", + type: "int", + default: "2", + local: "true" + }, + { name: "NumSwCfgWindowWords", + desc: "Size of the TL-UL window in 32bit words. Note that the effective partition size is smaller than that.", + type: "int", + default: "512", + local: "true" + } + + // Memory map Info + { name: "NumPart", + desc: "Number of partitions", + type: "int", + default: "11", + local: "true" + }, + { name: "NumPartUnbuf", + desc: "Number of unbuffered partitions", + type: "int", + default: "5", + local: "true" + }, + { name: "NumPartBuf", + desc: "Number of buffered partitions (including 1 lifecycle partition)", + type: "int", + default: "6", + local: "true" + }, + { name: "VendorTestOffset", + desc: "Offset of the VENDOR_TEST partition", + type: "int", + default: "0", + local: "true" + }, + { name: "VendorTestSize", + desc: "Size of the VENDOR_TEST partition", + type: "int", + default: "64", + local: "true" + }, + { name: "ScratchOffset", + desc: "Offset of SCRATCH", + type: "int", + default: "0", + local: "true" + }, + { name: "ScratchSize", + desc: "Size of SCRATCH", + type: "int", + default: "56", + local: "true" + }, + { name: "VendorTestDigestOffset", + desc: "Offset of VENDOR_TEST_DIGEST", + type: "int", + default: "56", + local: "true" + }, + { name: "VendorTestDigestSize", + desc: "Size of VENDOR_TEST_DIGEST", + type: "int", + default: "8", + local: "true" + }, + { name: "CreatorSwCfgOffset", + desc: "Offset of the CREATOR_SW_CFG partition", + type: "int", + default: "64", + local: "true" + }, + { name: "CreatorSwCfgSize", + desc: "Size of the CREATOR_SW_CFG partition", + type: "int", + default: "424", + local: "true" + }, + { name: "CreatorSwCfgAstCfgOffset", + desc: "Offset of CREATOR_SW_CFG_AST_CFG", + type: "int", + default: "64", + local: "true" + }, + { name: "CreatorSwCfgAstCfgSize", + desc: "Size of CREATOR_SW_CFG_AST_CFG", + type: "int", + default: "156", + local: "true" + }, + { name: "CreatorSwCfgAstInitEnOffset", + desc: "Offset of CREATOR_SW_CFG_AST_INIT_EN", + type: "int", + default: "220", + local: "true" + }, + { name: "CreatorSwCfgAstInitEnSize", + desc: "Size of CREATOR_SW_CFG_AST_INIT_EN", + type: "int", + default: "4", + local: "true" + }, + { name: "CreatorSwCfgRomExtSkuOffset", + desc: "Offset of CREATOR_SW_CFG_ROM_EXT_SKU", + type: "int", + default: "224", + local: "true" + }, + { name: "CreatorSwCfgRomExtSkuSize", + desc: "Size of CREATOR_SW_CFG_ROM_EXT_SKU", + type: "int", + default: "4", + local: "true" + }, + { name: "CreatorSwCfgSigverifyRsaModExpIbexEnOffset", + desc: "Offset of CREATOR_SW_CFG_SIGVERIFY_RSA_MOD_EXP_IBEX_EN", + type: "int", + default: "228", + local: "true" + }, + { name: "CreatorSwCfgSigverifyRsaModExpIbexEnSize", + desc: "Size of CREATOR_SW_CFG_SIGVERIFY_RSA_MOD_EXP_IBEX_EN", + type: "int", + default: "4", + local: "true" + }, + { name: "CreatorSwCfgSigverifyRsaKeyEnOffset", + desc: "Offset of CREATOR_SW_CFG_SIGVERIFY_RSA_KEY_EN", + type: "int", + default: "232", + local: "true" + }, + { name: "CreatorSwCfgSigverifyRsaKeyEnSize", + desc: "Size of CREATOR_SW_CFG_SIGVERIFY_RSA_KEY_EN", + type: "int", + default: "8", + local: "true" + }, + { name: "CreatorSwCfgSigverifySpxEnOffset", + desc: "Offset of CREATOR_SW_CFG_SIGVERIFY_SPX_EN", + type: "int", + default: "240", + local: "true" + }, + { name: "CreatorSwCfgSigverifySpxEnSize", + desc: "Size of CREATOR_SW_CFG_SIGVERIFY_SPX_EN", + type: "int", + default: "4", + local: "true" + }, + { name: "CreatorSwCfgSigverifySpxKeyEnOffset", + desc: "Offset of CREATOR_SW_CFG_SIGVERIFY_SPX_KEY_EN", + type: "int", + default: "244", + local: "true" + }, + { name: "CreatorSwCfgSigverifySpxKeyEnSize", + desc: "Size of CREATOR_SW_CFG_SIGVERIFY_SPX_KEY_EN", + type: "int", + default: "8", + local: "true" + }, + { name: "CreatorSwCfgFlashDataDefaultCfgOffset", + desc: "Offset of CREATOR_SW_CFG_FLASH_DATA_DEFAULT_CFG", + type: "int", + default: "252", + local: "true" + }, + { name: "CreatorSwCfgFlashDataDefaultCfgSize", + desc: "Size of CREATOR_SW_CFG_FLASH_DATA_DEFAULT_CFG", + type: "int", + default: "4", + local: "true" + }, + { name: "CreatorSwCfgFlashInfoBootDataCfgOffset", + desc: "Offset of CREATOR_SW_CFG_FLASH_INFO_BOOT_DATA_CFG", + type: "int", + default: "256", + local: "true" + }, + { name: "CreatorSwCfgFlashInfoBootDataCfgSize", + desc: "Size of CREATOR_SW_CFG_FLASH_INFO_BOOT_DATA_CFG", + type: "int", + default: "4", + local: "true" + }, + { name: "CreatorSwCfgFlashHwInfoCfgOverrideOffset", + desc: "Offset of CREATOR_SW_CFG_FLASH_HW_INFO_CFG_OVERRIDE", + type: "int", + default: "260", + local: "true" + }, + { name: "CreatorSwCfgFlashHwInfoCfgOverrideSize", + desc: "Size of CREATOR_SW_CFG_FLASH_HW_INFO_CFG_OVERRIDE", + type: "int", + default: "4", + local: "true" + }, + { name: "CreatorSwCfgRngEnOffset", + desc: "Offset of CREATOR_SW_CFG_RNG_EN", + type: "int", + default: "264", + local: "true" + }, + { name: "CreatorSwCfgRngEnSize", + desc: "Size of CREATOR_SW_CFG_RNG_EN", + type: "int", + default: "4", + local: "true" + }, + { name: "CreatorSwCfgJitterEnOffset", + desc: "Offset of CREATOR_SW_CFG_JITTER_EN", + type: "int", + default: "268", + local: "true" + }, + { name: "CreatorSwCfgJitterEnSize", + desc: "Size of CREATOR_SW_CFG_JITTER_EN", + type: "int", + default: "4", + local: "true" + }, + { name: "CreatorSwCfgRetRamResetMaskOffset", + desc: "Offset of CREATOR_SW_CFG_RET_RAM_RESET_MASK", + type: "int", + default: "272", + local: "true" + }, + { name: "CreatorSwCfgRetRamResetMaskSize", + desc: "Size of CREATOR_SW_CFG_RET_RAM_RESET_MASK", + type: "int", + default: "4", + local: "true" + }, + { name: "CreatorSwCfgManufStateOffset", + desc: "Offset of CREATOR_SW_CFG_MANUF_STATE", + type: "int", + default: "276", + local: "true" + }, + { name: "CreatorSwCfgManufStateSize", + desc: "Size of CREATOR_SW_CFG_MANUF_STATE", + type: "int", + default: "4", + local: "true" + }, + { name: "CreatorSwCfgRomExecEnOffset", + desc: "Offset of CREATOR_SW_CFG_ROM_EXEC_EN", + type: "int", + default: "280", + local: "true" + }, + { name: "CreatorSwCfgRomExecEnSize", + desc: "Size of CREATOR_SW_CFG_ROM_EXEC_EN", + type: "int", + default: "4", + local: "true" + }, + { name: "CreatorSwCfgCpuctrlOffset", + desc: "Offset of CREATOR_SW_CFG_CPUCTRL", + type: "int", + default: "284", + local: "true" + }, + { name: "CreatorSwCfgCpuctrlSize", + desc: "Size of CREATOR_SW_CFG_CPUCTRL", + type: "int", + default: "4", + local: "true" + }, + { name: "CreatorSwCfgMinSecVerRomExtOffset", + desc: "Offset of CREATOR_SW_CFG_MIN_SEC_VER_ROM_EXT", + type: "int", + default: "288", + local: "true" + }, + { name: "CreatorSwCfgMinSecVerRomExtSize", + desc: "Size of CREATOR_SW_CFG_MIN_SEC_VER_ROM_EXT", + type: "int", + default: "4", + local: "true" + }, + { name: "CreatorSwCfgMinSecVerBl0Offset", + desc: "Offset of CREATOR_SW_CFG_MIN_SEC_VER_BL0", + type: "int", + default: "292", + local: "true" + }, + { name: "CreatorSwCfgMinSecVerBl0Size", + desc: "Size of CREATOR_SW_CFG_MIN_SEC_VER_BL0", + type: "int", + default: "4", + local: "true" + }, + { name: "CreatorSwCfgDefaultBootDataInProdEnOffset", + desc: "Offset of CREATOR_SW_CFG_DEFAULT_BOOT_DATA_IN_PROD_EN", + type: "int", + default: "296", + local: "true" + }, + { name: "CreatorSwCfgDefaultBootDataInProdEnSize", + desc: "Size of CREATOR_SW_CFG_DEFAULT_BOOT_DATA_IN_PROD_EN", + type: "int", + default: "4", + local: "true" + }, + { name: "CreatorSwCfgRmaSpinEnOffset", + desc: "Offset of CREATOR_SW_CFG_RMA_SPIN_EN", + type: "int", + default: "300", + local: "true" + }, + { name: "CreatorSwCfgRmaSpinEnSize", + desc: "Size of CREATOR_SW_CFG_RMA_SPIN_EN", + type: "int", + default: "4", + local: "true" + }, + { name: "CreatorSwCfgRmaSpinCyclesOffset", + desc: "Offset of CREATOR_SW_CFG_RMA_SPIN_CYCLES", + type: "int", + default: "304", + local: "true" + }, + { name: "CreatorSwCfgRmaSpinCyclesSize", + desc: "Size of CREATOR_SW_CFG_RMA_SPIN_CYCLES", + type: "int", + default: "4", + local: "true" + }, + { name: "CreatorSwCfgRngRepcntThresholdsOffset", + desc: "Offset of CREATOR_SW_CFG_RNG_REPCNT_THRESHOLDS", + type: "int", + default: "308", + local: "true" + }, + { name: "CreatorSwCfgRngRepcntThresholdsSize", + desc: "Size of CREATOR_SW_CFG_RNG_REPCNT_THRESHOLDS", + type: "int", + default: "4", + local: "true" + }, + { name: "CreatorSwCfgRngRepcntsThresholdsOffset", + desc: "Offset of CREATOR_SW_CFG_RNG_REPCNTS_THRESHOLDS", + type: "int", + default: "312", + local: "true" + }, + { name: "CreatorSwCfgRngRepcntsThresholdsSize", + desc: "Size of CREATOR_SW_CFG_RNG_REPCNTS_THRESHOLDS", + type: "int", + default: "4", + local: "true" + }, + { name: "CreatorSwCfgRngAdaptpHiThresholdsOffset", + desc: "Offset of CREATOR_SW_CFG_RNG_ADAPTP_HI_THRESHOLDS", + type: "int", + default: "316", + local: "true" + }, + { name: "CreatorSwCfgRngAdaptpHiThresholdsSize", + desc: "Size of CREATOR_SW_CFG_RNG_ADAPTP_HI_THRESHOLDS", + type: "int", + default: "4", + local: "true" + }, + { name: "CreatorSwCfgRngAdaptpLoThresholdsOffset", + desc: "Offset of CREATOR_SW_CFG_RNG_ADAPTP_LO_THRESHOLDS", + type: "int", + default: "320", + local: "true" + }, + { name: "CreatorSwCfgRngAdaptpLoThresholdsSize", + desc: "Size of CREATOR_SW_CFG_RNG_ADAPTP_LO_THRESHOLDS", + type: "int", + default: "4", + local: "true" + }, + { name: "CreatorSwCfgRngBucketThresholdsOffset", + desc: "Offset of CREATOR_SW_CFG_RNG_BUCKET_THRESHOLDS", + type: "int", + default: "324", + local: "true" + }, + { name: "CreatorSwCfgRngBucketThresholdsSize", + desc: "Size of CREATOR_SW_CFG_RNG_BUCKET_THRESHOLDS", + type: "int", + default: "4", + local: "true" + }, + { name: "CreatorSwCfgRngMarkovHiThresholdsOffset", + desc: "Offset of CREATOR_SW_CFG_RNG_MARKOV_HI_THRESHOLDS", + type: "int", + default: "328", + local: "true" + }, + { name: "CreatorSwCfgRngMarkovHiThresholdsSize", + desc: "Size of CREATOR_SW_CFG_RNG_MARKOV_HI_THRESHOLDS", + type: "int", + default: "4", + local: "true" + }, + { name: "CreatorSwCfgRngMarkovLoThresholdsOffset", + desc: "Offset of CREATOR_SW_CFG_RNG_MARKOV_LO_THRESHOLDS", + type: "int", + default: "332", + local: "true" + }, + { name: "CreatorSwCfgRngMarkovLoThresholdsSize", + desc: "Size of CREATOR_SW_CFG_RNG_MARKOV_LO_THRESHOLDS", + type: "int", + default: "4", + local: "true" + }, + { name: "CreatorSwCfgRngExthtHiThresholdsOffset", + desc: "Offset of CREATOR_SW_CFG_RNG_EXTHT_HI_THRESHOLDS", + type: "int", + default: "336", + local: "true" + }, + { name: "CreatorSwCfgRngExthtHiThresholdsSize", + desc: "Size of CREATOR_SW_CFG_RNG_EXTHT_HI_THRESHOLDS", + type: "int", + default: "4", + local: "true" + }, + { name: "CreatorSwCfgRngExthtLoThresholdsOffset", + desc: "Offset of CREATOR_SW_CFG_RNG_EXTHT_LO_THRESHOLDS", + type: "int", + default: "340", + local: "true" + }, + { name: "CreatorSwCfgRngExthtLoThresholdsSize", + desc: "Size of CREATOR_SW_CFG_RNG_EXTHT_LO_THRESHOLDS", + type: "int", + default: "4", + local: "true" + }, + { name: "CreatorSwCfgRngAlertThresholdOffset", + desc: "Offset of CREATOR_SW_CFG_RNG_ALERT_THRESHOLD", + type: "int", + default: "344", + local: "true" + }, + { name: "CreatorSwCfgRngAlertThresholdSize", + desc: "Size of CREATOR_SW_CFG_RNG_ALERT_THRESHOLD", + type: "int", + default: "4", + local: "true" + }, + { name: "CreatorSwCfgRngHealthConfigDigestOffset", + desc: "Offset of CREATOR_SW_CFG_RNG_HEALTH_CONFIG_DIGEST", + type: "int", + default: "348", + local: "true" + }, + { name: "CreatorSwCfgRngHealthConfigDigestSize", + desc: "Size of CREATOR_SW_CFG_RNG_HEALTH_CONFIG_DIGEST", + type: "int", + default: "4", + local: "true" + }, + { name: "CreatorSwCfgSramKeyRenewEnOffset", + desc: "Offset of CREATOR_SW_CFG_SRAM_KEY_RENEW_EN", + type: "int", + default: "352", + local: "true" + }, + { name: "CreatorSwCfgSramKeyRenewEnSize", + desc: "Size of CREATOR_SW_CFG_SRAM_KEY_RENEW_EN", + type: "int", + default: "4", + local: "true" + }, + { name: "CreatorSwCfgDigestOffset", + desc: "Offset of CREATOR_SW_CFG_DIGEST", + type: "int", + default: "480", + local: "true" + }, + { name: "CreatorSwCfgDigestSize", + desc: "Size of CREATOR_SW_CFG_DIGEST", + type: "int", + default: "8", + local: "true" + }, + { name: "OwnerSwCfgOffset", + desc: "Offset of the OWNER_SW_CFG partition", + type: "int", + default: "488", + local: "true" + }, + { name: "OwnerSwCfgSize", + desc: "Size of the OWNER_SW_CFG partition", + type: "int", + default: "656", + local: "true" + }, + { name: "OwnerSwCfgRomErrorReportingOffset", + desc: "Offset of OWNER_SW_CFG_ROM_ERROR_REPORTING", + type: "int", + default: "488", + local: "true" + }, + { name: "OwnerSwCfgRomErrorReportingSize", + desc: "Size of OWNER_SW_CFG_ROM_ERROR_REPORTING", + type: "int", + default: "4", + local: "true" + }, + { name: "OwnerSwCfgRomBootstrapDisOffset", + desc: "Offset of OWNER_SW_CFG_ROM_BOOTSTRAP_DIS", + type: "int", + default: "492", + local: "true" + }, + { name: "OwnerSwCfgRomBootstrapDisSize", + desc: "Size of OWNER_SW_CFG_ROM_BOOTSTRAP_DIS", + type: "int", + default: "4", + local: "true" + }, + { name: "OwnerSwCfgRomAlertClassEnOffset", + desc: "Offset of OWNER_SW_CFG_ROM_ALERT_CLASS_EN", + type: "int", + default: "496", + local: "true" + }, + { name: "OwnerSwCfgRomAlertClassEnSize", + desc: "Size of OWNER_SW_CFG_ROM_ALERT_CLASS_EN", + type: "int", + default: "4", + local: "true" + }, + { name: "OwnerSwCfgRomAlertEscalationOffset", + desc: "Offset of OWNER_SW_CFG_ROM_ALERT_ESCALATION", + type: "int", + default: "500", + local: "true" + }, + { name: "OwnerSwCfgRomAlertEscalationSize", + desc: "Size of OWNER_SW_CFG_ROM_ALERT_ESCALATION", + type: "int", + default: "4", + local: "true" + }, + { name: "OwnerSwCfgRomAlertClassificationOffset", + desc: "Offset of OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION", + type: "int", + default: "504", + local: "true" + }, + { name: "OwnerSwCfgRomAlertClassificationSize", + desc: "Size of OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION", + type: "int", + default: "320", + local: "true" + }, + { name: "OwnerSwCfgRomLocalAlertClassificationOffset", + desc: "Offset of OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION", + type: "int", + default: "824", + local: "true" + }, + { name: "OwnerSwCfgRomLocalAlertClassificationSize", + desc: "Size of OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION", + type: "int", + default: "64", + local: "true" + }, + { name: "OwnerSwCfgRomAlertAccumThreshOffset", + desc: "Offset of OWNER_SW_CFG_ROM_ALERT_ACCUM_THRESH", + type: "int", + default: "888", + local: "true" + }, + { name: "OwnerSwCfgRomAlertAccumThreshSize", + desc: "Size of OWNER_SW_CFG_ROM_ALERT_ACCUM_THRESH", + type: "int", + default: "16", + local: "true" + }, + { name: "OwnerSwCfgRomAlertTimeoutCyclesOffset", + desc: "Offset of OWNER_SW_CFG_ROM_ALERT_TIMEOUT_CYCLES", + type: "int", + default: "904", + local: "true" + }, + { name: "OwnerSwCfgRomAlertTimeoutCyclesSize", + desc: "Size of OWNER_SW_CFG_ROM_ALERT_TIMEOUT_CYCLES", + type: "int", + default: "16", + local: "true" + }, + { name: "OwnerSwCfgRomAlertPhaseCyclesOffset", + desc: "Offset of OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES", + type: "int", + default: "920", + local: "true" + }, + { name: "OwnerSwCfgRomAlertPhaseCyclesSize", + desc: "Size of OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES", + type: "int", + default: "64", + local: "true" + }, + { name: "OwnerSwCfgRomAlertDigestProdOffset", + desc: "Offset of OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD", + type: "int", + default: "984", + local: "true" + }, + { name: "OwnerSwCfgRomAlertDigestProdSize", + desc: "Size of OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD", + type: "int", + default: "4", + local: "true" + }, + { name: "OwnerSwCfgRomAlertDigestProdEndOffset", + desc: "Offset of OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD_END", + type: "int", + default: "988", + local: "true" + }, + { name: "OwnerSwCfgRomAlertDigestProdEndSize", + desc: "Size of OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD_END", + type: "int", + default: "4", + local: "true" + }, + { name: "OwnerSwCfgRomAlertDigestDevOffset", + desc: "Offset of OWNER_SW_CFG_ROM_ALERT_DIGEST_DEV", + type: "int", + default: "992", + local: "true" + }, + { name: "OwnerSwCfgRomAlertDigestDevSize", + desc: "Size of OWNER_SW_CFG_ROM_ALERT_DIGEST_DEV", + type: "int", + default: "4", + local: "true" + }, + { name: "OwnerSwCfgRomAlertDigestRmaOffset", + desc: "Offset of OWNER_SW_CFG_ROM_ALERT_DIGEST_RMA", + type: "int", + default: "996", + local: "true" + }, + { name: "OwnerSwCfgRomAlertDigestRmaSize", + desc: "Size of OWNER_SW_CFG_ROM_ALERT_DIGEST_RMA", + type: "int", + default: "4", + local: "true" + }, + { name: "OwnerSwCfgRomWatchdogBiteThresholdCyclesOffset", + desc: "Offset of OWNER_SW_CFG_ROM_WATCHDOG_BITE_THRESHOLD_CYCLES", + type: "int", + default: "1000", + local: "true" + }, + { name: "OwnerSwCfgRomWatchdogBiteThresholdCyclesSize", + desc: "Size of OWNER_SW_CFG_ROM_WATCHDOG_BITE_THRESHOLD_CYCLES", + type: "int", + default: "4", + local: "true" + }, + { name: "OwnerSwCfgRomKeymgrRomExtMeasEnOffset", + desc: "Offset of OWNER_SW_CFG_ROM_KEYMGR_ROM_EXT_MEAS_EN", + type: "int", + default: "1004", + local: "true" + }, + { name: "OwnerSwCfgRomKeymgrRomExtMeasEnSize", + desc: "Size of OWNER_SW_CFG_ROM_KEYMGR_ROM_EXT_MEAS_EN", + type: "int", + default: "4", + local: "true" + }, + { name: "OwnerSwCfgManufStateOffset", + desc: "Offset of OWNER_SW_CFG_MANUF_STATE", + type: "int", + default: "1008", + local: "true" + }, + { name: "OwnerSwCfgManufStateSize", + desc: "Size of OWNER_SW_CFG_MANUF_STATE", + type: "int", + default: "4", + local: "true" + }, + { name: "OwnerSwCfgRomRstmgrInfoEnOffset", + desc: "Offset of OWNER_SW_CFG_ROM_RSTMGR_INFO_EN", + type: "int", + default: "1012", + local: "true" + }, + { name: "OwnerSwCfgRomRstmgrInfoEnSize", + desc: "Size of OWNER_SW_CFG_ROM_RSTMGR_INFO_EN", + type: "int", + default: "4", + local: "true" + }, + { name: "OwnerSwCfgRomExtBootstrapEnOffset", + desc: "Offset of OWNER_SW_CFG_ROM_EXT_BOOTSTRAP_EN", + type: "int", + default: "1016", + local: "true" + }, + { name: "OwnerSwCfgRomExtBootstrapEnSize", + desc: "Size of OWNER_SW_CFG_ROM_EXT_BOOTSTRAP_EN", + type: "int", + default: "4", + local: "true" + }, + { name: "OwnerSwCfgDigestOffset", + desc: "Offset of OWNER_SW_CFG_DIGEST", + type: "int", + default: "1136", + local: "true" + }, + { name: "OwnerSwCfgDigestSize", + desc: "Size of OWNER_SW_CFG_DIGEST", + type: "int", + default: "8", + local: "true" + }, + { name: "RotCreatorAuthCodesignOffset", + desc: "Offset of the ROT_CREATOR_AUTH_CODESIGN partition", + type: "int", + default: "1144", + local: "true" + }, + { name: "RotCreatorAuthCodesignSize", + desc: "Size of the ROT_CREATOR_AUTH_CODESIGN partition", + type: "int", + default: "472", + local: "true" + }, + { name: "RotCreatorAuthCodesignEcdsaKeyType0Offset", + desc: "Offset of ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY_TYPE0", + type: "int", + default: "1144", + local: "true" + }, + { name: "RotCreatorAuthCodesignEcdsaKeyType0Size", + desc: "Size of ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY_TYPE0", + type: "int", + default: "4", + local: "true" + }, + { name: "RotCreatorAuthCodesignEcdsaKey0Offset", + desc: "Offset of ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY0", + type: "int", + default: "1148", + local: "true" + }, + { name: "RotCreatorAuthCodesignEcdsaKey0Size", + desc: "Size of ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY0", + type: "int", + default: "64", + local: "true" + }, + { name: "RotCreatorAuthCodesignEcdsaKeyType1Offset", + desc: "Offset of ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY_TYPE1", + type: "int", + default: "1212", + local: "true" + }, + { name: "RotCreatorAuthCodesignEcdsaKeyType1Size", + desc: "Size of ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY_TYPE1", + type: "int", + default: "4", + local: "true" + }, + { name: "RotCreatorAuthCodesignEcdsaKey1Offset", + desc: "Offset of ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY1", + type: "int", + default: "1216", + local: "true" + }, + { name: "RotCreatorAuthCodesignEcdsaKey1Size", + desc: "Size of ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY1", + type: "int", + default: "64", + local: "true" + }, + { name: "RotCreatorAuthCodesignEcdsaKeyType2Offset", + desc: "Offset of ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY_TYPE2", + type: "int", + default: "1280", + local: "true" + }, + { name: "RotCreatorAuthCodesignEcdsaKeyType2Size", + desc: "Size of ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY_TYPE2", + type: "int", + default: "4", + local: "true" + }, + { name: "RotCreatorAuthCodesignEcdsaKey2Offset", + desc: "Offset of ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY2", + type: "int", + default: "1284", + local: "true" + }, + { name: "RotCreatorAuthCodesignEcdsaKey2Size", + desc: "Size of ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY2", + type: "int", + default: "64", + local: "true" + }, + { name: "RotCreatorAuthCodesignEcdsaKeyType3Offset", + desc: "Offset of ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY_TYPE3", + type: "int", + default: "1348", + local: "true" + }, + { name: "RotCreatorAuthCodesignEcdsaKeyType3Size", + desc: "Size of ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY_TYPE3", + type: "int", + default: "4", + local: "true" + }, + { name: "RotCreatorAuthCodesignEcdsaKey3Offset", + desc: "Offset of ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY3", + type: "int", + default: "1352", + local: "true" + }, + { name: "RotCreatorAuthCodesignEcdsaKey3Size", + desc: "Size of ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY3", + type: "int", + default: "64", + local: "true" + }, + { name: "RotCreatorAuthCodesignSpxKeyType0Offset", + desc: "Offset of ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_TYPE0", + type: "int", + default: "1416", + local: "true" + }, + { name: "RotCreatorAuthCodesignSpxKeyType0Size", + desc: "Size of ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_TYPE0", + type: "int", + default: "4", + local: "true" + }, + { name: "RotCreatorAuthCodesignSpxKey0Offset", + desc: "Offset of ROT_CREATOR_AUTH_CODESIGN_SPX_KEY0", + type: "int", + default: "1420", + local: "true" + }, + { name: "RotCreatorAuthCodesignSpxKey0Size", + desc: "Size of ROT_CREATOR_AUTH_CODESIGN_SPX_KEY0", + type: "int", + default: "32", + local: "true" + }, + { name: "RotCreatorAuthCodesignSpxKeyConfig0Offset", + desc: "Offset of ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_CONFIG0", + type: "int", + default: "1452", + local: "true" + }, + { name: "RotCreatorAuthCodesignSpxKeyConfig0Size", + desc: "Size of ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_CONFIG0", + type: "int", + default: "4", + local: "true" + }, + { name: "RotCreatorAuthCodesignSpxKeyType1Offset", + desc: "Offset of ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_TYPE1", + type: "int", + default: "1456", + local: "true" + }, + { name: "RotCreatorAuthCodesignSpxKeyType1Size", + desc: "Size of ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_TYPE1", + type: "int", + default: "4", + local: "true" + }, + { name: "RotCreatorAuthCodesignSpxKey1Offset", + desc: "Offset of ROT_CREATOR_AUTH_CODESIGN_SPX_KEY1", + type: "int", + default: "1460", + local: "true" + }, + { name: "RotCreatorAuthCodesignSpxKey1Size", + desc: "Size of ROT_CREATOR_AUTH_CODESIGN_SPX_KEY1", + type: "int", + default: "32", + local: "true" + }, + { name: "RotCreatorAuthCodesignSpxKeyConfig1Offset", + desc: "Offset of ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_CONFIG1", + type: "int", + default: "1492", + local: "true" + }, + { name: "RotCreatorAuthCodesignSpxKeyConfig1Size", + desc: "Size of ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_CONFIG1", + type: "int", + default: "4", + local: "true" + }, + { name: "RotCreatorAuthCodesignSpxKeyType2Offset", + desc: "Offset of ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_TYPE2", + type: "int", + default: "1496", + local: "true" + }, + { name: "RotCreatorAuthCodesignSpxKeyType2Size", + desc: "Size of ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_TYPE2", + type: "int", + default: "4", + local: "true" + }, + { name: "RotCreatorAuthCodesignSpxKey2Offset", + desc: "Offset of ROT_CREATOR_AUTH_CODESIGN_SPX_KEY2", + type: "int", + default: "1500", + local: "true" + }, + { name: "RotCreatorAuthCodesignSpxKey2Size", + desc: "Size of ROT_CREATOR_AUTH_CODESIGN_SPX_KEY2", + type: "int", + default: "32", + local: "true" + }, + { name: "RotCreatorAuthCodesignSpxKeyConfig2Offset", + desc: "Offset of ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_CONFIG2", + type: "int", + default: "1532", + local: "true" + }, + { name: "RotCreatorAuthCodesignSpxKeyConfig2Size", + desc: "Size of ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_CONFIG2", + type: "int", + default: "4", + local: "true" + }, + { name: "RotCreatorAuthCodesignSpxKeyType3Offset", + desc: "Offset of ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_TYPE3", + type: "int", + default: "1536", + local: "true" + }, + { name: "RotCreatorAuthCodesignSpxKeyType3Size", + desc: "Size of ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_TYPE3", + type: "int", + default: "4", + local: "true" + }, + { name: "RotCreatorAuthCodesignSpxKey3Offset", + desc: "Offset of ROT_CREATOR_AUTH_CODESIGN_SPX_KEY3", + type: "int", + default: "1540", + local: "true" + }, + { name: "RotCreatorAuthCodesignSpxKey3Size", + desc: "Size of ROT_CREATOR_AUTH_CODESIGN_SPX_KEY3", + type: "int", + default: "32", + local: "true" + }, + { name: "RotCreatorAuthCodesignSpxKeyConfig3Offset", + desc: "Offset of ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_CONFIG3", + type: "int", + default: "1572", + local: "true" + }, + { name: "RotCreatorAuthCodesignSpxKeyConfig3Size", + desc: "Size of ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_CONFIG3", + type: "int", + default: "4", + local: "true" + }, + { name: "RotCreatorAuthCodesignBlockSha2_256HashOffset", + desc: "Offset of ROT_CREATOR_AUTH_CODESIGN_BLOCK_SHA2_256_HASH", + type: "int", + default: "1576", + local: "true" + }, + { name: "RotCreatorAuthCodesignBlockSha2_256HashSize", + desc: "Size of ROT_CREATOR_AUTH_CODESIGN_BLOCK_SHA2_256_HASH", + type: "int", + default: "32", + local: "true" + }, + { name: "RotCreatorAuthCodesignDigestOffset", + desc: "Offset of ROT_CREATOR_AUTH_CODESIGN_DIGEST", + type: "int", + default: "1608", + local: "true" + }, + { name: "RotCreatorAuthCodesignDigestSize", + desc: "Size of ROT_CREATOR_AUTH_CODESIGN_DIGEST", + type: "int", + default: "8", + local: "true" + }, + { name: "RotCreatorAuthStateOffset", + desc: "Offset of the ROT_CREATOR_AUTH_STATE partition", + type: "int", + default: "1616", + local: "true" + }, + { name: "RotCreatorAuthStateSize", + desc: "Size of the ROT_CREATOR_AUTH_STATE partition", + type: "int", + default: "40", + local: "true" + }, + { name: "RotCreatorAuthStateEcdsaKey0Offset", + desc: "Offset of ROT_CREATOR_AUTH_STATE_ECDSA_KEY0", + type: "int", + default: "1616", + local: "true" + }, + { name: "RotCreatorAuthStateEcdsaKey0Size", + desc: "Size of ROT_CREATOR_AUTH_STATE_ECDSA_KEY0", + type: "int", + default: "4", + local: "true" + }, + { name: "RotCreatorAuthStateEcdsaKey1Offset", + desc: "Offset of ROT_CREATOR_AUTH_STATE_ECDSA_KEY1", + type: "int", + default: "1620", + local: "true" + }, + { name: "RotCreatorAuthStateEcdsaKey1Size", + desc: "Size of ROT_CREATOR_AUTH_STATE_ECDSA_KEY1", + type: "int", + default: "4", + local: "true" + }, + { name: "RotCreatorAuthStateEcdsaKey2Offset", + desc: "Offset of ROT_CREATOR_AUTH_STATE_ECDSA_KEY2", + type: "int", + default: "1624", + local: "true" + }, + { name: "RotCreatorAuthStateEcdsaKey2Size", + desc: "Size of ROT_CREATOR_AUTH_STATE_ECDSA_KEY2", + type: "int", + default: "4", + local: "true" + }, + { name: "RotCreatorAuthStateEcdsaKey3Offset", + desc: "Offset of ROT_CREATOR_AUTH_STATE_ECDSA_KEY3", + type: "int", + default: "1628", + local: "true" + }, + { name: "RotCreatorAuthStateEcdsaKey3Size", + desc: "Size of ROT_CREATOR_AUTH_STATE_ECDSA_KEY3", + type: "int", + default: "4", + local: "true" + }, + { name: "RotCreatorAuthStateSpxKey0Offset", + desc: "Offset of ROT_CREATOR_AUTH_STATE_SPX_KEY0", + type: "int", + default: "1632", + local: "true" + }, + { name: "RotCreatorAuthStateSpxKey0Size", + desc: "Size of ROT_CREATOR_AUTH_STATE_SPX_KEY0", + type: "int", + default: "4", + local: "true" + }, + { name: "RotCreatorAuthStateSpxKey1Offset", + desc: "Offset of ROT_CREATOR_AUTH_STATE_SPX_KEY1", + type: "int", + default: "1636", + local: "true" + }, + { name: "RotCreatorAuthStateSpxKey1Size", + desc: "Size of ROT_CREATOR_AUTH_STATE_SPX_KEY1", + type: "int", + default: "4", + local: "true" + }, + { name: "RotCreatorAuthStateSpxKey2Offset", + desc: "Offset of ROT_CREATOR_AUTH_STATE_SPX_KEY2", + type: "int", + default: "1640", + local: "true" + }, + { name: "RotCreatorAuthStateSpxKey2Size", + desc: "Size of ROT_CREATOR_AUTH_STATE_SPX_KEY2", + type: "int", + default: "4", + local: "true" + }, + { name: "RotCreatorAuthStateSpxKey3Offset", + desc: "Offset of ROT_CREATOR_AUTH_STATE_SPX_KEY3", + type: "int", + default: "1644", + local: "true" + }, + { name: "RotCreatorAuthStateSpxKey3Size", + desc: "Size of ROT_CREATOR_AUTH_STATE_SPX_KEY3", + type: "int", + default: "4", + local: "true" + }, + { name: "RotCreatorAuthStateDigestOffset", + desc: "Offset of ROT_CREATOR_AUTH_STATE_DIGEST", + type: "int", + default: "1648", + local: "true" + }, + { name: "RotCreatorAuthStateDigestSize", + desc: "Size of ROT_CREATOR_AUTH_STATE_DIGEST", + type: "int", + default: "8", + local: "true" + }, + { name: "HwCfg0Offset", + desc: "Offset of the HW_CFG0 partition", + type: "int", + default: "1656", + local: "true" + }, + { name: "HwCfg0Size", + desc: "Size of the HW_CFG0 partition", + type: "int", + default: "72", + local: "true" + }, + { name: "DeviceIdOffset", + desc: "Offset of DEVICE_ID", + type: "int", + default: "1656", + local: "true" + }, + { name: "DeviceIdSize", + desc: "Size of DEVICE_ID", + type: "int", + default: "32", + local: "true" + }, + { name: "ManufStateOffset", + desc: "Offset of MANUF_STATE", + type: "int", + default: "1688", + local: "true" + }, + { name: "ManufStateSize", + desc: "Size of MANUF_STATE", + type: "int", + default: "32", + local: "true" + }, + { name: "HwCfg0DigestOffset", + desc: "Offset of HW_CFG0_DIGEST", + type: "int", + default: "1720", + local: "true" + }, + { name: "HwCfg0DigestSize", + desc: "Size of HW_CFG0_DIGEST", + type: "int", + default: "8", + local: "true" + }, + { name: "HwCfg1Offset", + desc: "Offset of the HW_CFG1 partition", + type: "int", + default: "1728", + local: "true" + }, + { name: "HwCfg1Size", + desc: "Size of the HW_CFG1 partition", + type: "int", + default: "16", + local: "true" + }, + { name: "EnSramIfetchOffset", + desc: "Offset of EN_SRAM_IFETCH", + type: "int", + default: "1728", + local: "true" + }, + { name: "EnSramIfetchSize", + desc: "Size of EN_SRAM_IFETCH", + type: "int", + default: "1", + local: "true" + }, + { name: "EnCsrngSwAppReadOffset", + desc: "Offset of EN_CSRNG_SW_APP_READ", + type: "int", + default: "1729", + local: "true" + }, + { name: "EnCsrngSwAppReadSize", + desc: "Size of EN_CSRNG_SW_APP_READ", + type: "int", + default: "1", + local: "true" + }, + { name: "DisRvDmLateDebugOffset", + desc: "Offset of DIS_RV_DM_LATE_DEBUG", + type: "int", + default: "1730", + local: "true" + }, + { name: "DisRvDmLateDebugSize", + desc: "Size of DIS_RV_DM_LATE_DEBUG", + type: "int", + default: "1", + local: "true" + }, + { name: "HwCfg1DigestOffset", + desc: "Offset of HW_CFG1_DIGEST", + type: "int", + default: "1736", + local: "true" + }, + { name: "HwCfg1DigestSize", + desc: "Size of HW_CFG1_DIGEST", + type: "int", + default: "8", + local: "true" + }, + { name: "Secret0Offset", + desc: "Offset of the SECRET0 partition", + type: "int", + default: "1744", + local: "true" + }, + { name: "Secret0Size", + desc: "Size of the SECRET0 partition", + type: "int", + default: "40", + local: "true" + }, + { name: "TestUnlockTokenOffset", + desc: "Offset of TEST_UNLOCK_TOKEN", + type: "int", + default: "1744", + local: "true" + }, + { name: "TestUnlockTokenSize", + desc: "Size of TEST_UNLOCK_TOKEN", + type: "int", + default: "16", + local: "true" + }, + { name: "TestExitTokenOffset", + desc: "Offset of TEST_EXIT_TOKEN", + type: "int", + default: "1760", + local: "true" + }, + { name: "TestExitTokenSize", + desc: "Size of TEST_EXIT_TOKEN", + type: "int", + default: "16", + local: "true" + }, + { name: "Secret0DigestOffset", + desc: "Offset of SECRET0_DIGEST", + type: "int", + default: "1776", + local: "true" + }, + { name: "Secret0DigestSize", + desc: "Size of SECRET0_DIGEST", + type: "int", + default: "8", + local: "true" + }, + { name: "Secret1Offset", + desc: "Offset of the SECRET1 partition", + type: "int", + default: "1784", + local: "true" + }, + { name: "Secret1Size", + desc: "Size of the SECRET1 partition", + type: "int", + default: "88", + local: "true" + }, + { name: "FlashAddrKeySeedOffset", + desc: "Offset of FLASH_ADDR_KEY_SEED", + type: "int", + default: "1784", + local: "true" + }, + { name: "FlashAddrKeySeedSize", + desc: "Size of FLASH_ADDR_KEY_SEED", + type: "int", + default: "32", + local: "true" + }, + { name: "FlashDataKeySeedOffset", + desc: "Offset of FLASH_DATA_KEY_SEED", + type: "int", + default: "1816", + local: "true" + }, + { name: "FlashDataKeySeedSize", + desc: "Size of FLASH_DATA_KEY_SEED", + type: "int", + default: "32", + local: "true" + }, + { name: "SramDataKeySeedOffset", + desc: "Offset of SRAM_DATA_KEY_SEED", + type: "int", + default: "1848", + local: "true" + }, + { name: "SramDataKeySeedSize", + desc: "Size of SRAM_DATA_KEY_SEED", + type: "int", + default: "16", + local: "true" + }, + { name: "Secret1DigestOffset", + desc: "Offset of SECRET1_DIGEST", + type: "int", + default: "1864", + local: "true" + }, + { name: "Secret1DigestSize", + desc: "Size of SECRET1_DIGEST", + type: "int", + default: "8", + local: "true" + }, + { name: "Secret2Offset", + desc: "Offset of the SECRET2 partition", + type: "int", + default: "1872", + local: "true" + }, + { name: "Secret2Size", + desc: "Size of the SECRET2 partition", + type: "int", + default: "88", + local: "true" + }, + { name: "RmaTokenOffset", + desc: "Offset of RMA_TOKEN", + type: "int", + default: "1872", + local: "true" + }, + { name: "RmaTokenSize", + desc: "Size of RMA_TOKEN", + type: "int", + default: "16", + local: "true" + }, + { name: "CreatorRootKeyShare0Offset", + desc: "Offset of CREATOR_ROOT_KEY_SHARE0", + type: "int", + default: "1888", + local: "true" + }, + { name: "CreatorRootKeyShare0Size", + desc: "Size of CREATOR_ROOT_KEY_SHARE0", + type: "int", + default: "32", + local: "true" + }, + { name: "CreatorRootKeyShare1Offset", + desc: "Offset of CREATOR_ROOT_KEY_SHARE1", + type: "int", + default: "1920", + local: "true" + }, + { name: "CreatorRootKeyShare1Size", + desc: "Size of CREATOR_ROOT_KEY_SHARE1", + type: "int", + default: "32", + local: "true" + }, + { name: "Secret2DigestOffset", + desc: "Offset of SECRET2_DIGEST", + type: "int", + default: "1952", + local: "true" + }, + { name: "Secret2DigestSize", + desc: "Size of SECRET2_DIGEST", + type: "int", + default: "8", + local: "true" + }, + { name: "LifeCycleOffset", + desc: "Offset of the LIFE_CYCLE partition", + type: "int", + default: "1960", + local: "true" + }, + { name: "LifeCycleSize", + desc: "Size of the LIFE_CYCLE partition", + type: "int", + default: "88", + local: "true" + }, + { name: "LcTransitionCntOffset", + desc: "Offset of LC_TRANSITION_CNT", + type: "int", + default: "1960", + local: "true" + }, + { name: "LcTransitionCntSize", + desc: "Size of LC_TRANSITION_CNT", + type: "int", + default: "48", + local: "true" + }, + { name: "LcStateOffset", + desc: "Offset of LC_STATE", + type: "int", + default: "2008", + local: "true" + }, + { name: "LcStateSize", + desc: "Size of LC_STATE", + type: "int", + default: "40", + local: "true" + }, + ] + + ///////////////////////////// + // Intermodule Connections // + ///////////////////////////// + + inter_signal_list: [ + // OTP dedicated power connection from AST + { struct: "" + type: "io" + name: "otp_ext_voltage_h" + act: "none" + default: "'0" + package: "", + } + // Power sequencing signals to AST + { struct: "otp_ast_req" + type: "uni" + name: "otp_ast_pwr_seq" + act: "req" + default: "'0" + package: "otp_ctrl_pkg" + desc: "Power sequencing signals to AST (VDD domain)." + } + // Power sequencing signals from AST + { struct: "otp_ast_rsp" + type: "uni" + name: "otp_ast_pwr_seq_h" + act: "rcv" + default: "'0" + package: "otp_ctrl_pkg" + desc: "Power sequencing signals coming from AST (VCC domain)." + } + // EDN interface + { struct: "edn" + type: "req_rsp" + name: "edn" + act: "req" + package: "edn_pkg" + desc: "Entropy request to the entropy distribution network for LFSR reseeding and ephemeral key derivation." + } + // Power manager init command + { struct: "pwr_otp" + type: "req_rsp" + name: "pwr_otp" + act: "rsp" + default: "'0" + package: "pwrmgr_pkg" + desc: "Initialization request/acknowledge from/to power manager." + } + // Macro-specific test signals to/from LC TAP + { struct: "lc_otp_vendor_test" + type: "req_rsp" + name: "lc_otp_vendor_test" + act: "rsp" + default: "'0" + package: "otp_ctrl_pkg" + desc: "Vendor test control signals from/to the life cycle TAP." + } + // LC transition command + { struct: "lc_otp_program" + type: "req_rsp" + name: "lc_otp_program" + act: "rsp" + default: "'0" + package: "otp_ctrl_pkg" + desc: "Life cycle state transition interface." + } + // Broadcast to LC + { struct: "otp_lc_data" + type: "uni" + name: "otp_lc_data" + act: "req" + default: "'0" + package: "otp_ctrl_pkg" + desc: ''' + Life cycle state output holding the current life cycle state, + the value of the transition counter and the tokens needed for life cycle transitions. + ''' + } + // Broadcast from LC + { struct: "lc_tx" + type: "uni" + name: "lc_escalate_en" + act: "rcv" + default: "lc_ctrl_pkg::Off" + package: "lc_ctrl_pkg" + desc: ''' + Life cycle escalation enable coming from life cycle controller. + This signal moves all FSMs within OTP into the error state. + ''' + } + { struct: "lc_tx" + type: "uni" + name: "lc_creator_seed_sw_rw_en" + act: "rcv" + default: "lc_ctrl_pkg::Off" + package: "lc_ctrl_pkg" + desc: ''' + Provision enable qualifier coming from life cycle controller. + This signal enables SW read / write access to the RMA_TOKEN and CREATOR_ROOT_KEY_SHARE0 and CREATOR_ROOT_KEY_SHARE1. + ''' + } + { struct: "lc_tx" + type: "uni" + name: "lc_owner_seed_sw_rw_en" + act: "rcv" + default: "lc_ctrl_pkg::Off" + package: "lc_ctrl_pkg" + desc: ''' + Provision enable qualifier coming from life cycle controller. + This signal enables SW read / write access to the OWNER_SEED. + ''' + } + { struct: "lc_tx" + type: "uni" + name: "lc_seed_hw_rd_en" + act: "rcv" + default: "lc_ctrl_pkg::Off" + package: "lc_ctrl_pkg" + desc: ''' + Seed read enable coming from life cycle controller. + This signal enables HW read access to the CREATOR_ROOT_KEY_SHARE0 and CREATOR_ROOT_KEY_SHARE1. + ''' + } + { struct: "lc_tx" + type: "uni" + name: "lc_dft_en" + act: "rcv" + default: "lc_ctrl_pkg::Off" + package: "lc_ctrl_pkg" + desc: ''' + Test enable qualifier coming from life cycle controller. + This signals enables the TL-UL access port to the proprietary OTP IP. + ''' + } + { struct: "lc_tx" + type: "uni" + name: "lc_check_byp_en" + act: "rcv" + default: "lc_ctrl_pkg::Off" + package: "lc_ctrl_pkg" + desc: ''' + Life cycle partition check bypass signal. + This signal causes the life cycle partition to bypass consistency checks during life cycle state transitions in order to prevent spurious consistency check failures. + ''' + } + // Broadcast to Key Manager + { struct: "otp_keymgr_key" + type: "uni" + name: "otp_keymgr_key" + act: "req" + default: "'0" + package: "otp_ctrl_pkg" + desc: "Key output to the key manager holding CREATOR_ROOT_KEY_SHARE0 and CREATOR_ROOT_KEY_SHARE1." + } + // Broadcast to Flash Controller + { struct: "flash_otp_key" + type: "req_rsp" + name: "flash_otp_key" + act: "rsp" + default: "'0" + package: "otp_ctrl_pkg" + desc: "Key derivation interface for FLASH scrambling." + } + // Key request from SRAM scramblers + { struct: "sram_otp_key" + // TODO: would be nice if this could accept parameters. + // Split this out into an issue. + width: "4" + type: "req_rsp" + name: "sram_otp_key" + act: "rsp" + default: "'0" + package: "otp_ctrl_pkg" + desc: "Array with key derivation interfaces for SRAM scrambling devices." + } + // Key request from OTBN RAM Scrambler + { struct: "otbn_otp_key" + type: "req_rsp" + name: "otbn_otp_key" + act: "rsp" + default: "'0" + package: "otp_ctrl_pkg" + desc: "Key derivation interface for OTBN scrambling devices." + } + // Hardware config partition + { struct: "otp_broadcast" + type: "uni" + name: "otp_broadcast" + act: "req" + default: "'0" + package: "otp_ctrl_part_pkg" + desc: "Output of the HW partitions with breakout data types." + } + // AST observability control + { struct: "ast_obs_ctrl", + type: "uni", + name: "obs_ctrl", + act: "rcv", + package: "ast_pkg" + desc: "AST observability control signals." + } + // prim otp observe bus + { struct: "logic", + type: "uni", + name: "otp_obs", + act: "req", + width: "8", + package: "" + desc: "AST observability bus." + } + ] // inter_signal_list + + ///////////////////// + // Countermeasures // + ///////////////////// + + countermeasures: [ + { name: "BUS.INTEGRITY", + desc: "End-to-end bus integrity scheme." + } + { name: "SECRET.MEM.SCRAMBLE", + desc: "Secret partitions are scrambled with a full-round PRESENT cipher." + } + { name: "PART.MEM.DIGEST", + desc: "Integrity of buffered partitions is ensured via a 64bit digest." + } + { name: "DAI.FSM.SPARSE", + desc: "The direct access interface FSM is sparsely encoded." + } + { name: "KDI.FSM.SPARSE", + desc: "The key derivation interface FSM is sparsely encoded." + } + { name: "LCI.FSM.SPARSE", + desc: "The life cycle interface FSM is sparsely encoded." + } + { name: "PART.FSM.SPARSE", + desc: "The partition FSMs are sparsely encoded." + } + { name: "SCRMBL.FSM.SPARSE", + desc: "The scramble datapath FSM is sparsely encoded." + } + { name: "TIMER.FSM.SPARSE", + desc: "The background check timer FSM is sparsely encoded." + } + { name: "DAI.CTR.REDUN", + desc: "The direct access interface address counter employs a cross-counter implementation." + } + { name: "KDI_SEED.CTR.REDUN", + desc: "The key derivation interface counter employs a cross-counter implementation." + } + { name: "KDI_ENTROPY.CTR.REDUN", + desc: "The key derivation entropy counter employs a cross-counter implementation." + } + { name: "LCI.CTR.REDUN", + desc: "The life cycle interface address counter employs a cross-counter implementation." + } + { name: "PART.CTR.REDUN", + desc: "The address counter of buffered partitions employs a cross-counter implementation." + } + { name: "SCRMBL.CTR.REDUN", + desc: "The srambling datapath counter employs a cross-counter implementation." + } + { name: "TIMER_INTEG.CTR.REDUN", + desc: "The background integrity check timer employs a duplicated counter implementation." + } + { name: "TIMER_CNSTY.CTR.REDUN", + desc: "The background consistency check timer employs a duplicated counter implementation." + } + { name: "TIMER.LFSR.REDUN", + desc: "The background check LFSR is duplicated." + } + { name: "DAI.FSM.LOCAL_ESC", + desc: "The direct access interface FSM is moved into an invalid state upon local escalation." + } + { name: "LCI.FSM.LOCAL_ESC", + desc: "The life cycle interface FSM is moved into an invalid state upon local escalation." + } + { name: "KDI.FSM.LOCAL_ESC", + desc: "The key derivation interface FSM is moved into an invalid state upon local escalation." + } + { name: "PART.FSM.LOCAL_ESC", + desc: "The partition FSMs are moved into an invalid state upon local escalation." + } + { name: "SCRMBL.FSM.LOCAL_ESC", + desc: "The scramble datapath FSM is moved into an invalid state upon local escalation." + } + { name: "TIMER.FSM.LOCAL_ESC", + desc: "The background check timer FSM is moved into an invalid state upon local escalation." + } + { name: "DAI.FSM.GLOBAL_ESC", + desc: "The direct access interface FSM is moved into an invalid state upon global escalation via life cycle." + } + { name: "LCI.FSM.GLOBAL_ESC", + desc: "The life cycle interface FSM is moved into an invalid state upon global escalation via life cycle." + } + { name: "KDI.FSM.GLOBAL_ESC", + desc: "The key derivation interface FSM is moved into an invalid state upon global escalation via life cycle." + } + { name: "PART.FSM.GLOBAL_ESC", + desc: "The partition FSMs are moved into an invalid state upon global escalation via life cycle." + } + { name: "SCRMBL.FSM.GLOBAL_ESC", + desc: "The scramble datapath FSM is moved into an invalid state upon global escalation via life cycle." + } + { name: "TIMER.FSM.GLOBAL_ESC", + desc: "The background check timer FSM is moved into an invalid state upon global escalation via life cycle." + } + { name: "PART.DATA_REG.INTEGRITY", + desc: "All partition buffer registers are protected with ECC on 64bit blocks." + } + { name: "PART.DATA_REG.BKGN_CHK", + desc: "The digest of buffered partitions is recomputed and checked at pseudorandom intervals in the background." + } + { name: "PART.MEM.REGREN" + desc: "Unbuffered ('software') partitions can be read-locked via a CSR until the next system reset." + } + { name: "PART.MEM.SW_UNREADABLE" + desc: "Secret buffered partitions become unreadable to software once they are locked via the digest." + } + { name: "PART.MEM.SW_UNWRITABLE" + desc: "All partitions become unwritable by software once they are locked via the digest." + } + { name: "LC_PART.MEM.SW_NOACCESS" + desc: "The life cycle partition is not directly readable nor writable via software." + } + { name: "ACCESS.CTRL.MUBI", + desc: "The access control signals going from the partitions to the DAI are MUBI encoded." + } + { name: "TOKEN_VALID.CTRL.MUBI", + desc: "The token valid signals going to the life cycle controller are MUBI encoded." + } + { name: "LC_CTRL.INTERSIG.MUBI", + desc: "The life cycle control signals are multibit encoded." + } + { name: "TEST.BUS.LC_GATED", + desc: "Prevent access to test signals and the OTP backdoor interface in non-test lifecycle states." + } + { name: "TEST_TL_LC_GATE.FSM.SPARSE", + desc: "The control FSM inside the TL-UL gating primitive is sparsely encoded." + } + { name: "DIRECT_ACCESS.CONFIG.REGWEN", + desc: "The direct access CSRs are REGWEN protected." + } + { name: "CHECK_TRIGGER.CONFIG.REGWEN", + desc: "The check trigger CSR is REGWEN protected." + } + { name: "CHECK.CONFIG.REGWEN", + desc: "The check CSR is REGWEN protected." + } + { name: "MACRO.MEM.INTEGRITY", + desc: ''' + The OTP macro employs a vendor-specific integrity scheme at the granularity of the native 16bit OTP words. + The scheme is able to at least detect single bit errors. + ''' + } + { name: "MACRO.MEM.CM", + desc: "The OTP macro may contain additional vendor-specific countermeasures." + } + ] + + features: [ + { + name: "OTP_CTRL.PARTITION.VENDOR_TEST" + desc: '''Vendor test partition is used for OTP programming smoke check during manufacturing flow. + In this partition, ECC uncorrectable errors will not lead to fatal errors and alerts. + Instead the error will be reported as correctable ECC error. + ''' + } + { + name: "OTP_CTRL.PARTITION.CREATOR_SW_CFG" + desc: '''During calibration stage, various parameters (clock, voltage, and timing sources) are calibrated and recorded to CREATOR_SW_CFG partition. + ''' + } + { + name: "OTP_CTRL.PARTITION.OWNER_SW_CFG" + desc: "Define attriutes for rom code execution" + } + { + name: "OTP_CTRL.INIT" + desc: '''When power is up, OTP controller reads devices status. + After all reads complete, the controller performs integrity check on the HW_CFG* and SECRET partitions. + Once all integrity checks are complete, the controller marks outputs as valid. + ''' + } + { + name: "OTP_CTRL.ENTROPY_READ" + desc: '''Firmware can read entropy from ENTROPY_SRC block by configuring following field of HW_CFG* partition. + - EN_CSRNG_SW_APP_READ + ''' + } + { + name: "OTP_CTRL.KEY_DERIVATION" + desc: "OTP controller participate key derivation process by providing scramble key seed to SRAM_CTRL and FLASH_CTRL." + } + { + name: "OTP_CTRL.PROGRAM" + desc: '''All other partitions except life cycle partition are programmed through DAI interface. + And once non-zero digest is programmed to these partition, no further write access is allowed. + Life cycle partition is programmed by LC_CTRL. + ''' + } + { + name: "OTP_CTRL.PARTITION.SECRET0" + desc: "Test unlock tokens, Test exit token" + } + { + name: "OTP_CTRL.PARTITION.SECRET1" + desc: "SRAM and FLASH scrambling key" + } + { + name: "OTP_CTRL.PARTITION.SECRET2" + desc: "RMA unlock token and creator root key" + } + { + name: "OTP_CTRL.PARTITION.LIFE_CYCLE" + desc: '''LC state, LC transition count. + This feature is owned by the LC_CTRL and cannot be tested well through the OTP_CTRL CSR interface. + ''' + } + { + name: "OTP_CTRL.PARTITIONS_FEATURE.READ_LOCK" + desc: '''Following partitions can be read lockable by CSR. + - VENDOR_TEST + - CREATOR_SW_CFG + - OWNER_SW_CFG + Following partitions can be read lockable by writing digest. + - SECRET0 + - SECRET1 + - RECRET2 + All read attempt to these partitions after read is locked will trigger AccessError (recoverable). + ''' + } + { + name: "OTP_CTRL.PARTITIONS_FEATURE.WRITE_LOCK" + desc: "All partitions except LIFE_CYCLE can be write lockable by writing digest." + } + { + name: "OTP_CTRL.ERROR_HANDLING.RECOVERABLE" + desc: "Recoverable error is created when unauthorized access atempt are detected via dai interface." + } + { + name: "OTP_CTRL.ERROR_HANDLING.FATAL" + desc: "Unrecoverable errors are created for uncorrectable ecc error, otp macro malfunction and unauthorized access via lc_ctrl." + } + { + name: "OTP_CTRL.BACKGROUND_CHECK.CHECK_TIMEOUT" + desc: "Timeout value for the integrity and consistency checks." + } + { + name: "OTP_CTRL.BACKGROUND_CHECK.INTEGRITY_CHECK_PERIOD" + desc: "The interval which the digest of the partition is recomputed to check integrity of locked partition." + } + { + name: "OTP_CTRL.BACKGROUND_CHECK.CONSISTENCY_CHECK_PERIOD" + desc: "Re-read period of the buffer registers to ensure data is matched with the associated OTP partition." + } + ] + + /////////////// + // Registers // + /////////////// + + regwidth: "32", + registers: { + core: [ + //////////////////////// + // Ctrl / Status CSRs // + //////////////////////// + + { name: "STATUS", + desc: "OTP status register.", + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + resval: 0, + tags: [ // OTP internal HW can modify status register + "excl:CsrAllTests:CsrExclCheck"], + fields: [ + { bits: "0" + name: "VENDOR_TEST_ERROR" + desc: ''' + Set to 1 if an error occurred in this partition. + If set to 1, SW should check the !!ERR_CODE register at the corresponding index. + ''' + } + { bits: "1" + name: "CREATOR_SW_CFG_ERROR" + desc: ''' + Set to 1 if an error occurred in this partition. + If set to 1, SW should check the !!ERR_CODE register at the corresponding index. + ''' + } + { bits: "2" + name: "OWNER_SW_CFG_ERROR" + desc: ''' + Set to 1 if an error occurred in this partition. + If set to 1, SW should check the !!ERR_CODE register at the corresponding index. + ''' + } + { bits: "3" + name: "ROT_CREATOR_AUTH_CODESIGN_ERROR" + desc: ''' + Set to 1 if an error occurred in this partition. + If set to 1, SW should check the !!ERR_CODE register at the corresponding index. + ''' + } + { bits: "4" + name: "ROT_CREATOR_AUTH_STATE_ERROR" + desc: ''' + Set to 1 if an error occurred in this partition. + If set to 1, SW should check the !!ERR_CODE register at the corresponding index. + ''' + } + { bits: "5" + name: "HW_CFG0_ERROR" + desc: ''' + Set to 1 if an error occurred in this partition. + If set to 1, SW should check the !!ERR_CODE register at the corresponding index. + ''' + } + { bits: "6" + name: "HW_CFG1_ERROR" + desc: ''' + Set to 1 if an error occurred in this partition. + If set to 1, SW should check the !!ERR_CODE register at the corresponding index. + ''' + } + { bits: "7" + name: "SECRET0_ERROR" + desc: ''' + Set to 1 if an error occurred in this partition. + If set to 1, SW should check the !!ERR_CODE register at the corresponding index. + ''' + } + { bits: "8" + name: "SECRET1_ERROR" + desc: ''' + Set to 1 if an error occurred in this partition. + If set to 1, SW should check the !!ERR_CODE register at the corresponding index. + ''' + } + { bits: "9" + name: "SECRET2_ERROR" + desc: ''' + Set to 1 if an error occurred in this partition. + If set to 1, SW should check the !!ERR_CODE register at the corresponding index. + ''' + } + { bits: "10" + name: "LIFE_CYCLE_ERROR" + desc: ''' + Set to 1 if an error occurred in this partition. + If set to 1, SW should check the !!ERR_CODE register at the corresponding index. + ''' + } + { bits: "11" + name: "DAI_ERROR" + desc: ''' + Set to 1 if an error occurred in the DAI. + If set to 1, SW should check the !!ERR_CODE register at the corresponding index. + ''' + } + { bits: "12" + name: "LCI_ERROR" + desc: ''' + Set to 1 if an error occurred in the LCI. + If set to 1, SW should check the !!ERR_CODE register at the corresponding index. + ''' + } + { bits: "13" + name: "TIMEOUT_ERROR" + desc: ''' + Set to 1 if an integrity or consistency check times out. + This raises an fatal_check_error alert and is an unrecoverable error condition. + ''' + } + { bits: "14" + name: "LFSR_FSM_ERROR" + desc: ''' + Set to 1 if the LFSR timer FSM has reached an invalid state. + This raises an fatal_check_error alert and is an unrecoverable error condition. + ''' + } + { bits: "15" + name: "SCRAMBLING_FSM_ERROR" + desc: ''' + Set to 1 if the scrambling datapath FSM has reached an invalid state. + This raises an fatal_check_error alert and is an unrecoverable error condition. + ''' + } + { bits: "16" + name: "KEY_DERIV_FSM_ERROR" + desc: ''' + Set to 1 if the key derivation FSM has reached an invalid state. + This raises an fatal_check_error alert and is an unrecoverable error condition. + ''' + } + { bits: "17" + name: "BUS_INTEG_ERROR" + desc: ''' + This bit is set to 1 if a fatal bus integrity fault is detected. + This error triggers a fatal_bus_integ_error alert. + ''' + } + { bits: "18" + name: "DAI_IDLE" + desc: "Set to 1 if the DAI is idle and ready to accept commands." + } + { bits: "19" + name: "CHECK_PENDING" + desc: "Set to 1 if an integrity or consistency check triggered by the LFSR timer or via !!CHECK_TRIGGER is pending." + } + ] + } + { multireg: { + name: "ERR_CODE", + desc: ''' + This register holds information about error conditions that occurred in the agents + interacting with the OTP macro via the internal bus. The error codes should be checked + if the partitions, DAI or LCI flag an error in the !!STATUS register, or when an + !!INTR_STATE.otp_error has been triggered. Note that all errors trigger an otp_error + interrupt, and in addition some errors may trigger either an fatal_macro_error or an + fatal_check_error alert. + ''', + count: "NumErrorEntries", + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + cname: "AGENT", + compact: "false", + resval: 0, + tags: [ // OTP internal HW can modify the error code registers + "excl:CsrAllTests:CsrExclCheck"], + fields: [ + { + bits: "2:0" + enum: [ + { value: "0", + name: "NO_ERROR", + desc: ''' + No error condition has occurred. + ''' + }, + { value: "1", + name: "MACRO_ERROR", + desc: ''' + Returned if the OTP macro command was invalid or did not complete successfully + due to a macro malfunction. + This error should never occur during normal operation and is not recoverable. + This error triggers an fatal_macro_error alert. + ''' + }, + { value: "2", + name: "MACRO_ECC_CORR_ERROR", + desc: ''' + A correctable ECC error has occured during an OTP read operation. + The corresponding controller automatically recovers from this error when + issuing a new command. + ''' + }, + { value: "3", + name: "MACRO_ECC_UNCORR_ERROR", + desc: ''' + An uncorrectable ECC error has occurred during an OTP read operation. + This error should never occur during normal operation and is not recoverable. + If this error is present this may be a sign that the device is malfunctioning. + This error triggers an fatal_macro_error alert. + ''' + }, + { value: "4", + name: "MACRO_WRITE_BLANK_ERROR", + desc: ''' + This error is returned if a programming operation attempted to clear a bit that has previously been programmed to 1. + The corresponding controller automatically recovers from this error when issuing a new command. + + Note however that the affected OTP word may be left in an inconsistent state if this error occurs. + This can cause several issues when the word is accessed again (either as part of a regular read operation, as part of the readout at boot, or as part of a background check). + + It is important that SW ensures that each word is only written once, since this can render the device useless. + ''' + }, + { value: "5", + name: "ACCESS_ERROR", + desc: ''' + This error indicates that a locked memory region has been accessed. + The corresponding controller automatically recovers from this error when issuing a new command. + ''' + }, + { value: "6", + name: "CHECK_FAIL_ERROR", + desc: ''' + An ECC, integrity or consistency mismatch has been detected in the buffer registers. + This error should never occur during normal operation and is not recoverable. + This error triggers an fatal_check_error alert. + ''' + }, + { value: "7", + name: "FSM_STATE_ERROR", + desc: ''' + The FSM of the corresponding controller has reached an invalid state, or the FSM has + been moved into a terminal error state due to an escalation action via lc_escalate_en_i. + This error should never occur during normal operation and is not recoverable. + If this error is present, this is a sign that the device has fallen victim to + an invasive attack. This error triggers an fatal_check_error alert. + ''' + }, + ] + } + ] + } + } + { name: "DIRECT_ACCESS_REGWEN", + desc: ''' + Register write enable for all direct access interface registers. + ''', + swaccess: "rw0c", + hwaccess: "hrw", + hwext: "true", + hwqe: "true", + tags: [ // OTP internal HW will set this enable register to 0 when OTP is not under IDLE + // state, so could not auto-predict its value + "excl:CsrNonInitTests:CsrExclCheck"], + fields: [ + { + bits: "0", + desc: ''' + This bit controls whether the DAI registers can be written. + Write 0 to it in order to clear the bit. + + Note that the hardware also modulates this bit and sets it to 0 temporarily + during an OTP operation such that the corresponding address and data registers + cannot be modified while an operation is pending. The !!DAI_IDLE status bit + will also be set to 0 in such a case. + ''' + resval: 1, + }, + ] + }, + { name: "DIRECT_ACCESS_CMD", + desc: "Command register for direct accesses.", + swaccess: "r0w1c", + hwaccess: "hro", + hwqe: "true", + hwext: "true", + resval: 0, + regwen: "DIRECT_ACCESS_REGWEN", + tags: [ // Write to DIRECT_ACCESS_CMD randomly might cause OTP_ERRORs and illegal sequences + "excl:CsrNonInitTests:CsrExclWrite"], + fields: [ + { bits: "0", + name: "RD", + desc: ''' + Initiates a readout sequence that reads the location specified + by !!DIRECT_ACCESS_ADDRESS. The command places the data read into + !!DIRECT_ACCESS_RDATA_0 and !!DIRECT_ACCESS_RDATA_1 (for 64bit partitions). + ''' + } + { bits: "1", + name: "WR", + desc: ''' + Initiates a programming sequence that writes the data in !!DIRECT_ACCESS_WDATA_0 + and !!DIRECT_ACCESS_WDATA_1 (for 64bit partitions) to the location specified by + !!DIRECT_ACCESS_ADDRESS. + ''' + } + { bits: "2", + name: "DIGEST", + desc: ''' + Initiates the digest calculation and locking sequence for the partition specified by + !!DIRECT_ACCESS_ADDRESS. + ''' + } + ] + } + { name: "DIRECT_ACCESS_ADDRESS", + desc: "Address register for direct accesses.", + swaccess: "rw", + hwaccess: "hro", + hwqe: "false", + resval: 0, + regwen: "DIRECT_ACCESS_REGWEN", + tags: [ // The enable register "DIRECT_ACCESS_REGWEN" is HW controlled, + // so not able to predict this register value automatically + "excl:CsrNonInitTests:CsrExclCheck"], + fields: [ + { bits: "OtpByteAddrWidth-1:0", + desc: ''' + This is the address for the OTP word to be read or written through + the direct access interface. Note that the address is aligned to the access size + internally, hence bits 1:0 are ignored for 32bit accesses, and bits 2:0 are ignored + for 64bit accesses. + + For the digest calculation command, set this register to the partition base offset. + ''' + } + ] + } + { multireg: { + name: "DIRECT_ACCESS_WDATA", + desc: '''Write data for direct accesses. + Hardware automatically determines the access granule (32bit or 64bit) based on which + partition is being written to. + ''', + count: "NumDaiWords", // 2 x 32bit = 64bit + swaccess: "rw", + hwaccess: "hro", + hwqe: "false", + regwen: "DIRECT_ACCESS_REGWEN", + cname: "WORD", + resval: 0, + tags: [ // The value of this register is written from "DIRECT_ACCESS_RDATA", + // so could not predict this register value automatically + "excl:CsrAllTests:CsrExclCheck"], + fields: [ + { bits: "31:0" + } + ] + } + }, + { multireg: { + name: "DIRECT_ACCESS_RDATA", + desc: '''Read data for direct accesses. + Hardware automatically determines the access granule (32bit or 64bit) based on which + partition is read from. + ''', + count: "NumDaiWords", // 2 x 32bit = 64bit + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + cname: "WORD", + resval: 0, + fields: [ + { bits: "31:0" + } + ] + } + }, + + ////////////////////////////////////// + // Integrity and Consistency Checks // + ////////////////////////////////////// + { name: "CHECK_TRIGGER_REGWEN", + desc: ''' + Register write enable for !!CHECK_TRIGGER. + ''', + swaccess: "rw0c", + hwaccess: "none", + fields: [ + { bits: "0", + desc: ''' + When cleared to 0, the !!CHECK_TRIGGER register cannot be written anymore. + Write 0 to clear this bit. + ''' + resval: 1, + }, + ] + }, + { name: "CHECK_TRIGGER", + desc: "Command register for direct accesses.", + swaccess: "r0w1c", + hwaccess: "hro", + hwqe: "true", + hwext: "true", + resval: 0, + regwen: "CHECK_TRIGGER_REGWEN", + fields: [ + { bits: "0", + name: "INTEGRITY", + desc: ''' + Writing 1 to this bit triggers an integrity check. SW should monitor !!STATUS.CHECK_PENDING + and wait until the check has been completed. If there are any errors, those will be flagged + in the !!STATUS and !!ERR_CODE registers, and via the interrupts and alerts. + ''' + } + { bits: "1", + name: "CONSISTENCY", + desc: ''' + Writing 1 to this bit triggers a consistency check. SW should monitor !!STATUS.CHECK_PENDING + and wait until the check has been completed. If there are any errors, those will be flagged + in the !!STATUS and !!ERR_CODE registers, and via interrupts and alerts. + ''' + } + ] + }, + { name: "CHECK_REGWEN", + desc: ''' + Register write enable for !!INTEGRITY_CHECK_PERIOD and !!CONSISTENCY_CHECK_PERIOD. + ''', + swaccess: "rw0c", + hwaccess: "none", + fields: [ + { bits: "0", + desc: ''' + When cleared to 0, !!INTEGRITY_CHECK_PERIOD and !!CONSISTENCY_CHECK_PERIOD registers cannot be written anymore. + Write 0 to clear this bit. + ''' + resval: 1, + }, + ] + }, + { name: "CHECK_TIMEOUT", + desc: ''' + Timeout value for the integrity and consistency checks. + ''', + swaccess: "rw", + hwaccess: "hro", + regwen: "CHECK_REGWEN", + tags: [ // Do not write to this automatically, as it may trigger fatal alert, and cause + // escalation. + "excl:CsrAllTests:CsrExclWrite"], + fields: [ + { bits: "31:0", + desc: ''' + Timeout value in cycles for the for the integrity and consistency checks. If an integrity or consistency + check does not complete within the timeout window, an error will be flagged in the !!STATUS register, + an otp_error interrupt will be raised, and an fatal_check_error alert will be sent out. The timeout should + be set to a large value to stay on the safe side. The maximum check time can be upper bounded by the + number of cycles it takes to readout, scramble and digest the entire OTP array. Since this amounts to + roughly 25k cycles, it is recommended to set this value to at least 100'000 cycles in order to stay on the + safe side. A value of zero disables the timeout mechanism (default). + ''' + resval: 0, + }, + ] + }, + { name: "INTEGRITY_CHECK_PERIOD", + desc: ''' + This value specifies the maximum period that can be generated pseudo-randomly. + Only applies to the HW_CFG* and SECRET* partitions once they are locked. + ''' + swaccess: "rw", + hwaccess: "hro", + regwen: "CHECK_REGWEN", + fields: [ + { bits: "31:0", + desc: ''' + The pseudo-random period is generated using a 40bit LFSR internally, and this register defines + the bit mask to be applied to the LFSR output in order to limit its range. The value of this + register is left shifted by 8bits and the lower bits are set to 8'hFF in order to form the 40bit mask. + A recommended value is 0x3_FFFF, corresponding to a maximum period of ~2.8s at 24MHz. + A value of zero disables the timer (default). Note that a one-off check can always be triggered via + !!CHECK_TRIGGER.INTEGRITY. + ''' + resval: "0" + } + ] + } + { name: "CONSISTENCY_CHECK_PERIOD", + desc: ''' + This value specifies the maximum period that can be generated pseudo-randomly. + This applies to the LIFE_CYCLE partition and the HW_CFG* and SECRET* partitions once they are locked. + ''' + swaccess: "rw", + hwaccess: "hro", + regwen: "CHECK_REGWEN", + fields: [ + { bits: "31:0", + desc: ''' + The pseudo-random period is generated using a 40bit LFSR internally, and this register defines + the bit mask to be applied to the LFSR output in order to limit its range. The value of this + register is left shifted by 8bits and the lower bits are set to 8'hFF in order to form the 40bit mask. + A recommended value is 0x3FF_FFFF, corresponding to a maximum period of ~716s at 24MHz. + A value of zero disables the timer (default). Note that a one-off check can always be triggered via + !!CHECK_TRIGGER.CONSISTENCY. + ''' + resval: "0" + } + ] + } + + //////////////////////////////////// + // Dynamic Locks of SW Parititons // + //////////////////////////////////// + { name: "VENDOR_TEST_READ_LOCK", + desc: ''' + Runtime read lock for the VENDOR_TEST partition. + ''', + swaccess: "rw0c", + hwaccess: "hro", + regwen: "DIRECT_ACCESS_REGWEN", + tags: [ // The value of this register can affect the read access of the this + // partition's memory window. Excluding this register from writing can ensure + // memories have read and write access. + "excl:CsrNonInitTests:CsrExclWrite"], + fields: [ + { bits: "0", + desc: ''' + When cleared to 0, read access to the VENDOR_TEST partition is locked. + Write 0 to clear this bit. + ''' + resval: 1, + }, + ] + }, + { name: "CREATOR_SW_CFG_READ_LOCK", + desc: ''' + Runtime read lock for the CREATOR_SW_CFG partition. + ''', + swaccess: "rw0c", + hwaccess: "hro", + regwen: "DIRECT_ACCESS_REGWEN", + tags: [ // The value of this register can affect the read access of the this + // partition's memory window. Excluding this register from writing can ensure + // memories have read and write access. + "excl:CsrNonInitTests:CsrExclWrite"], + fields: [ + { bits: "0", + desc: ''' + When cleared to 0, read access to the CREATOR_SW_CFG partition is locked. + Write 0 to clear this bit. + ''' + resval: 1, + }, + ] + }, + { name: "OWNER_SW_CFG_READ_LOCK", + desc: ''' + Runtime read lock for the OWNER_SW_CFG partition. + ''', + swaccess: "rw0c", + hwaccess: "hro", + regwen: "DIRECT_ACCESS_REGWEN", + tags: [ // The value of this register can affect the read access of the this + // partition's memory window. Excluding this register from writing can ensure + // memories have read and write access. + "excl:CsrNonInitTests:CsrExclWrite"], + fields: [ + { bits: "0", + desc: ''' + When cleared to 0, read access to the OWNER_SW_CFG partition is locked. + Write 0 to clear this bit. + ''' + resval: 1, + }, + ] + }, + { name: "ROT_CREATOR_AUTH_CODESIGN_READ_LOCK", + desc: ''' + Runtime read lock for the ROT_CREATOR_AUTH_CODESIGN partition. + ''', + swaccess: "rw0c", + hwaccess: "hro", + regwen: "DIRECT_ACCESS_REGWEN", + tags: [ // The value of this register can affect the read access of the this + // partition's memory window. Excluding this register from writing can ensure + // memories have read and write access. + "excl:CsrNonInitTests:CsrExclWrite"], + fields: [ + { bits: "0", + desc: ''' + When cleared to 0, read access to the ROT_CREATOR_AUTH_CODESIGN partition is locked. + Write 0 to clear this bit. + ''' + resval: 1, + }, + ] + }, + { name: "ROT_CREATOR_AUTH_STATE_READ_LOCK", + desc: ''' + Runtime read lock for the ROT_CREATOR_AUTH_STATE partition. + ''', + swaccess: "rw0c", + hwaccess: "hro", + regwen: "DIRECT_ACCESS_REGWEN", + tags: [ // The value of this register can affect the read access of the this + // partition's memory window. Excluding this register from writing can ensure + // memories have read and write access. + "excl:CsrNonInitTests:CsrExclWrite"], + fields: [ + { bits: "0", + desc: ''' + When cleared to 0, read access to the ROT_CREATOR_AUTH_STATE partition is locked. + Write 0 to clear this bit. + ''' + resval: 1, + }, + ] + }, + + /////////////////////// + // Integrity Digests // + /////////////////////// + { multireg: { + name: "VENDOR_TEST_DIGEST", + desc: ''' + Integrity digest for the VENDOR_TEST partition. + The integrity digest is 0 by default. Software must write this + digest value via the direct access interface in order to lock the partition. + After a reset, write access to the VENDOR_TEST partition is locked and + the digest becomes visible in this CSR. + ''', + count: "NumDigestWords", + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + cname: "WORD", + resval: 0, + tags: [ // OTP internal HW will update status so can not auto-predict its value. + "excl:CsrAllTests:CsrExclCheck"], + fields: [ + { bits: "31:0" + } + ] + } + }, + { multireg: { + name: "CREATOR_SW_CFG_DIGEST", + desc: ''' + Integrity digest for the CREATOR_SW_CFG partition. + The integrity digest is 0 by default. Software must write this + digest value via the direct access interface in order to lock the partition. + After a reset, write access to the CREATOR_SW_CFG partition is locked and + the digest becomes visible in this CSR. + ''', + count: "NumDigestWords", + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + cname: "WORD", + resval: 0, + tags: [ // OTP internal HW will update status so can not auto-predict its value. + "excl:CsrAllTests:CsrExclCheck"], + fields: [ + { bits: "31:0" + } + ] + } + }, + { multireg: { + name: "OWNER_SW_CFG_DIGEST", + desc: ''' + Integrity digest for the OWNER_SW_CFG partition. + The integrity digest is 0 by default. Software must write this + digest value via the direct access interface in order to lock the partition. + After a reset, write access to the OWNER_SW_CFG partition is locked and + the digest becomes visible in this CSR. + ''', + count: "NumDigestWords", + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + cname: "WORD", + resval: 0, + tags: [ // OTP internal HW will update status so can not auto-predict its value. + "excl:CsrAllTests:CsrExclCheck"], + fields: [ + { bits: "31:0" + } + ] + } + }, + { multireg: { + name: "ROT_CREATOR_AUTH_CODESIGN_DIGEST", + desc: ''' + Integrity digest for the ROT_CREATOR_AUTH_CODESIGN partition. + The integrity digest is 0 by default. Software must write this + digest value via the direct access interface in order to lock the partition. + After a reset, write access to the ROT_CREATOR_AUTH_CODESIGN partition is locked and + the digest becomes visible in this CSR. + ''', + count: "NumDigestWords", + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + cname: "WORD", + resval: 0, + tags: [ // OTP internal HW will update status so can not auto-predict its value. + "excl:CsrAllTests:CsrExclCheck"], + fields: [ + { bits: "31:0" + } + ] + } + }, + { multireg: { + name: "ROT_CREATOR_AUTH_STATE_DIGEST", + desc: ''' + Integrity digest for the ROT_CREATOR_AUTH_STATE partition. + The integrity digest is 0 by default. Software must write this + digest value via the direct access interface in order to lock the partition. + After a reset, write access to the ROT_CREATOR_AUTH_STATE partition is locked and + the digest becomes visible in this CSR. + ''', + count: "NumDigestWords", + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + cname: "WORD", + resval: 0, + tags: [ // OTP internal HW will update status so can not auto-predict its value. + "excl:CsrAllTests:CsrExclCheck"], + fields: [ + { bits: "31:0" + } + ] + } + }, + { multireg: { + name: "HW_CFG0_DIGEST", + desc: ''' + Integrity digest for the HW_CFG0 partition. + The integrity digest is 0 by default. The digest calculation can be triggered via the !!DIRECT_ACCESS_CMD. + After a reset, the digest then becomes visible in this CSR, and the corresponding partition becomes write-locked. + ''', + count: "NumDigestWords", + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + cname: "WORD", + resval: 0, + tags: [ // OTP internal HW will update status so can not auto-predict its value. + "excl:CsrAllTests:CsrExclCheck"], + fields: [ + { bits: "31:0" + } + ] + } + }, + { multireg: { + name: "HW_CFG1_DIGEST", + desc: ''' + Integrity digest for the HW_CFG1 partition. + The integrity digest is 0 by default. The digest calculation can be triggered via the !!DIRECT_ACCESS_CMD. + After a reset, the digest then becomes visible in this CSR, and the corresponding partition becomes write-locked. + ''', + count: "NumDigestWords", + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + cname: "WORD", + resval: 0, + tags: [ // OTP internal HW will update status so can not auto-predict its value. + "excl:CsrAllTests:CsrExclCheck"], + fields: [ + { bits: "31:0" + } + ] + } + }, + { multireg: { + name: "SECRET0_DIGEST", + desc: ''' + Integrity digest for the SECRET0 partition. + The integrity digest is 0 by default. The digest calculation can be triggered via the !!DIRECT_ACCESS_CMD. + After a reset, the digest then becomes visible in this CSR, and the corresponding partition becomes write-locked. + ''', + count: "NumDigestWords", + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + cname: "WORD", + resval: 0, + tags: [ // OTP internal HW will update status so can not auto-predict its value. + "excl:CsrAllTests:CsrExclCheck"], + fields: [ + { bits: "31:0" + } + ] + } + }, + { multireg: { + name: "SECRET1_DIGEST", + desc: ''' + Integrity digest for the SECRET1 partition. + The integrity digest is 0 by default. The digest calculation can be triggered via the !!DIRECT_ACCESS_CMD. + After a reset, the digest then becomes visible in this CSR, and the corresponding partition becomes write-locked. + ''', + count: "NumDigestWords", + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + cname: "WORD", + resval: 0, + tags: [ // OTP internal HW will update status so can not auto-predict its value. + "excl:CsrAllTests:CsrExclCheck"], + fields: [ + { bits: "31:0" + } + ] + } + }, + { multireg: { + name: "SECRET2_DIGEST", + desc: ''' + Integrity digest for the SECRET2 partition. + The integrity digest is 0 by default. The digest calculation can be triggered via the !!DIRECT_ACCESS_CMD. + After a reset, the digest then becomes visible in this CSR, and the corresponding partition becomes write-locked. + ''', + count: "NumDigestWords", + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + cname: "WORD", + resval: 0, + tags: [ // OTP internal HW will update status so can not auto-predict its value. + "excl:CsrAllTests:CsrExclCheck"], + fields: [ + { bits: "31:0" + } + ] + } + }, + + //////////////////////////////// + // Software Config Partitions // + //////////////////////////////// + { skipto: "0x800" } + + { window: { + name: "SW_CFG_WINDOW" + items: "NumSwCfgWindowWords" + swaccess: "ro", + desc: ''' + Any read to this window directly maps to the corresponding offset in the creator and owner software + config partitions, and triggers an OTP readout of the bytes requested. Note that the transaction + will block until OTP readout has completed. + ''' + } + } + ], + + // OTP wrapper-specific registers + prim: [ + { name: "CSR0", + desc: "" + swaccess: "rw", + hwaccess: "hro", + hwext: "false", + hwqe: "false", + fields: [ + { bits: "0", + name: "field0", + desc: "", + resval: "0x0", + } + { bits: "1", + name: "field1", + desc: "", + resval: "0x0", + } + { bits: "2", + name: "field2", + desc: "", + resval: "0x0", + } + { bits: "13:4", + name: "field3", + desc: "" + resval: "0x0", + } + { bits: "26:16", + name: "field4", + desc: "" + resval: "0x0", + } + ] + }, + { name: "CSR1", + desc: "" + swaccess: "rw", + hwaccess: "hro", + hwext: "false", + hwqe: "false", + fields: [ + { bits: "6:0", + name: "field0", + desc: "" + resval: "0x0", + } + { bits: "7:7", + name: "field1", + desc: "", + resval: "0x0", + } + { bits: "14:8", + name: "field2", + desc: "" + resval: "0x0", + } + { bits: "15:15", + name: "field3", + desc: "", + resval: "0x0", + } + { bits: "31:16", + name: "field4", + desc: "", + resval: "0x0", + } + ] + }, + { name: "CSR2", + desc: "" + swaccess: "rw", + hwaccess: "hro", + hwext: "false", + hwqe: "false", + fields: [ + { bits: "0", + name: "field0", + desc: "", + resval: "0x0", + } + ] + }, + { name: "CSR3", + desc: "" + swaccess: "rw", + hwaccess: "hrw", + hwext: "false", + hwqe: "false", + fields: [ + { bits: "2:0", + name: "field0", + desc: "" + swaccess: "rw1c", + resval: "0x0", + } + { bits: "13:4", + name: "field1", + desc: "", + swaccess: "rw1c", + resval: "0x0", + } + { bits: "16", + name: "field2", + desc: "", + swaccess: "rw1c", + resval: "0x0", + } + { bits: "17", + name: "field3", + desc: "", + swaccess: "ro", + resval: "0x0", + } + { bits: "18", + name: "field4", + desc: "", + swaccess: "ro", + resval: "0x0", + } + { bits: "19", + name: "field5", + desc: "", + swaccess: "ro", + resval: "0x0", + } + { bits: "20", + name: "field6", + desc: "", + swaccess: "ro", + resval: "0x0", + } + { bits: "21", + name: "field7", + desc: "", + swaccess: "ro", + resval: "0x0", + } + { bits: "22", + name: "field8", + desc: "", + swaccess: "ro", + resval: "0x0", + } + ] + }, + { name: "CSR4", + desc: "" + swaccess: "rw", + hwaccess: "hro", + hwext: "false", + hwqe: "false", + fields: [ + { bits: "9:0", + name: "field0", + desc: "" + resval: "0x0", + } + { bits: "12", + name: "field1", + desc: "" + resval: "0x0", + } + { bits: "13", + name: "field2", + desc: "" + resval: "0x0", + } + { bits: "14", + name: "field3", + desc: "" + resval: "0x0", + } + ] + }, + { name: "CSR5", + desc: "" + swaccess: "rw", + hwaccess: "hrw", + hwext: "false", + hwqe: "false", + fields: [ + { bits: "5:0", + name: "field0", + desc: "" + swaccess: "rw", + resval: "0x0", + } + { bits: "7:6", + name: "field1", + desc: "" + swaccess: "rw", + resval: "0x0", + } + { bits: "8", + name: "field2", + desc: "", + swaccess: "ro", + resval: "0x0", + } + { bits: "11:9", + name: "field3", + desc: "" + swaccess: "ro", + resval: "0x0", + } + { bits: "12", + name: "field4", + desc: "" + swaccess: "ro", + resval: "0x0", + } + { bits: "13", + name: "field5", + desc: "" + swaccess: "ro", + resval: "0x0", + } + { bits: "31:16", + name: "field6", + desc: "" + swaccess: "rw", + resval: "0x0", + } + ] + }, + { name: "CSR6", + desc: "" + swaccess: "rw", + hwaccess: "hro", + hwext: "false", + hwqe: "false", + fields: [ + { bits: "9:0", + name: "field0", + desc: "" + resval: "0x0", + } + { bits: "11", + name: "field1", + desc: "", + swaccess: "rw", + resval: "0x0", + } + { bits: "12", + name: "field2", + desc: "", + swaccess: "rw", + resval: "0x0", + } + { bits: "31:16", + name: "field3", + desc: "" + resval: "0x0", + } + ] + }, + { name: "CSR7", + desc: "", + swaccess: "ro", + hwaccess: "hrw", + hwext: "false", + hwqe: "false", + fields: [ + { bits: "5:0", + name: "field0", + desc: "" + swaccess: "ro", + resval: "0x0", + } + { bits: "10:8", + name: "field1", + desc: "", + swaccess: "ro", + resval: "0x0", + } + { bits: "14", + name: "field2", + desc: "", + swaccess: "ro", + resval: "0x0", + } + { bits: "15", + name: "field3", + desc: "", + swaccess: "ro", + resval: "0x0", + } + ] + }, + ] + } +} diff --git a/src/fuse_ctrl/data/otp_ctrl_orig.json b/src/fuse_ctrl/data/otp_ctrl_orig.json new file mode 100644 index 0000000..71fc987 --- /dev/null +++ b/src/fuse_ctrl/data/otp_ctrl_orig.json @@ -0,0 +1,3297 @@ +{ + "name": "otp_ctrl", + "human_name": "One-Time Programmable Memory Controller", + "one_line_desc": "Interfaces integrated one-time programmable memory, supports scrambling, integrity and secure wipe", + "one_paragraph_desc": "One-Time Programmable (OTP) Memory Controller provides an open source abstraction interface for software and other hardware components such as Life Cycle Controller and Key Manager to interact with an integrated, closed source, proprietary OTP memory.\nOn top of defensive features provided by the proprietary OTP memory to deter side-channel analysis (SCA), fault injection (FI) attacks, and visual and electrical probing, the open source OTP controller features high-level logical security protection such as integrity checks and scrambling, as well as software isolation for when OTP contents are readable and programmable.\nIt features multiple individually-lockable logical partitions, periodic / persistent checking of OTP values, and a separate partition and interface for Life Cycle Controller.", + "cip_id": "16", + "design_spec": "../doc", + "dv_doc": "../doc/dv", + "hw_checklist": "../doc/checklist", + "sw_checklist": "/sw/device/lib/dif/dif_otp_ctrl", + "revisions": [ + { + "version": "0.1.0", + "life_stage": "L1", + "design_stage": "D2", + "verification_stage": "V2", + "dif_stage": "S1", + "commit_id": "127b109e2fab9336e830158abe449a3922544ded", + "notes": "" + }, + { + "version": "1.0.0", + "life_stage": "L1", + "design_stage": "D3", + "verification_stage": "V2S", + "dif_stage": "S2", + "notes": "" + }, + { + "version": "2.0.0", + "life_stage": "L1", + "design_stage": "D2S", + "verification_stage": "V2S", + "dif_stage": "S2", + "notes": "" + } + ], + "clocking": [ + { + "clock": "clk_i", + "reset": "rst_ni", + "primary": true + }, + { + "clock": "clk_edn_i", + "reset": "rst_edn_ni" + } + ], + "scan": "true", + "scan_reset": "true", + "scan_en": "true", + "bus_interfaces": [ + { + "protocol": "tlul", + "direction": "device", + "name": "core" + }, + { + "protocol": "tlul", + "direction": "device", + "name": "prim", + "hier_path": "u_otp.gen_generic.u_impl_generic.u_reg_top" + } + ], + "available_output_list": [ + { + "name": "test", + "width": 8, + "desc": "Test-related GPIOs. Only active in DFT-enabled life cycle states." + } + ], + "interrupt_list": [ + { + "name": "otp_operation_done", + "desc": "A direct access command or digest calculation operation has completed." + }, + { + "name": "otp_error", + "desc": "An error has occurred in the OTP controller. Check the !!ERR_CODE register to get more information." + } + ], + "alert_list": [ + { + "name": "fatal_macro_error", + "desc": "This alert triggers if hardware detects an uncorrectable error during an OTP transaction, for example an uncorrectable ECC error in the OTP array." + }, + { + "name": "fatal_check_error", + "desc": "This alert triggers if any of the background checks fails. This includes the digest checks and concurrent ECC checks in the buffer registers." + }, + { + "name": "fatal_bus_integ_error", + "desc": "This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected." + }, + { + "name": "fatal_prim_otp_alert", + "desc": "Fatal alert triggered inside the OTP primitive, including fatal TL-UL bus integrity faults of the test interface." + }, + { + "name": "recov_prim_otp_alert", + "desc": "Recoverable alert triggered inside the OTP primitive." + } + ], + "param_list": [ + { + "name": "MemInitFile", + "desc": "VMEM file to initialize the OTP macro.", + "type": "", + "default": "\"\"", + "expose": "true", + "local": "false" + }, + { + "name": "RndCnstLfsrSeed", + "desc": "Compile-time random bits for initial LFSR seed", + "type": "otp_ctrl_pkg::lfsr_seed_t", + "randcount": "40", + "randtype": "data" + }, + { + "name": "RndCnstLfsrPerm", + "desc": "Compile-time random permutation for LFSR output", + "type": "otp_ctrl_pkg::lfsr_perm_t", + "randcount": "40", + "randtype": "perm" + }, + { + "name": "RndCnstScrmblKeyInit", + "desc": "Compile-time random permutation for scrambling key/nonce register reset value", + "type": "otp_ctrl_pkg::scrmbl_key_init_t", + "randcount": "256", + "randtype": "data" + }, + { + "name": "NumSramKeyReqSlots", + "desc": "Number of key slots", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "OtpByteAddrWidth", + "desc": "Width of the OTP byte address.", + "type": "int", + "default": "11", + "local": "true" + }, + { + "name": "NumErrorEntries", + "desc": "Number of error register entries.", + "type": "int", + "default": "13", + "local": "true" + }, + { + "name": "NumDaiWords", + "desc": "Number of 32bit words in the DAI.", + "type": "int", + "default": "2", + "local": "true" + }, + { + "name": "NumDigestWords", + "desc": "Size of the digest fields in 32bit words.", + "type": "int", + "default": "2", + "local": "true" + }, + { + "name": "NumSwCfgWindowWords", + "desc": "Size of the TL-UL window in 32bit words. Note that the effective partition size is smaller than that.", + "type": "int", + "default": "512", + "local": "true" + }, + { + "name": "NumPart", + "desc": "Number of partitions", + "type": "int", + "default": "11", + "local": "true" + }, + { + "name": "NumPartUnbuf", + "desc": "Number of unbuffered partitions", + "type": "int", + "default": "5", + "local": "true" + }, + { + "name": "NumPartBuf", + "desc": "Number of buffered partitions (including 1 lifecycle partition)", + "type": "int", + "default": "6", + "local": "true" + }, + { + "name": "VendorTestOffset", + "desc": "Offset of the VENDOR_TEST partition", + "type": "int", + "default": "0", + "local": "true" + }, + { + "name": "VendorTestSize", + "desc": "Size of the VENDOR_TEST partition", + "type": "int", + "default": "64", + "local": "true" + }, + { + "name": "ScratchOffset", + "desc": "Offset of SCRATCH", + "type": "int", + "default": "0", + "local": "true" + }, + { + "name": "ScratchSize", + "desc": "Size of SCRATCH", + "type": "int", + "default": "56", + "local": "true" + }, + { + "name": "VendorTestDigestOffset", + "desc": "Offset of VENDOR_TEST_DIGEST", + "type": "int", + "default": "56", + "local": "true" + }, + { + "name": "VendorTestDigestSize", + "desc": "Size of VENDOR_TEST_DIGEST", + "type": "int", + "default": "8", + "local": "true" + }, + { + "name": "CreatorSwCfgOffset", + "desc": "Offset of the CREATOR_SW_CFG partition", + "type": "int", + "default": "64", + "local": "true" + }, + { + "name": "CreatorSwCfgSize", + "desc": "Size of the CREATOR_SW_CFG partition", + "type": "int", + "default": "424", + "local": "true" + }, + { + "name": "CreatorSwCfgAstCfgOffset", + "desc": "Offset of CREATOR_SW_CFG_AST_CFG", + "type": "int", + "default": "64", + "local": "true" + }, + { + "name": "CreatorSwCfgAstCfgSize", + "desc": "Size of CREATOR_SW_CFG_AST_CFG", + "type": "int", + "default": "156", + "local": "true" + }, + { + "name": "CreatorSwCfgAstInitEnOffset", + "desc": "Offset of CREATOR_SW_CFG_AST_INIT_EN", + "type": "int", + "default": "220", + "local": "true" + }, + { + "name": "CreatorSwCfgAstInitEnSize", + "desc": "Size of CREATOR_SW_CFG_AST_INIT_EN", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "CreatorSwCfgRomExtSkuOffset", + "desc": "Offset of CREATOR_SW_CFG_ROM_EXT_SKU", + "type": "int", + "default": "224", + "local": "true" + }, + { + "name": "CreatorSwCfgRomExtSkuSize", + "desc": "Size of CREATOR_SW_CFG_ROM_EXT_SKU", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "CreatorSwCfgSigverifyRsaModExpIbexEnOffset", + "desc": "Offset of CREATOR_SW_CFG_SIGVERIFY_RSA_MOD_EXP_IBEX_EN", + "type": "int", + "default": "228", + "local": "true" + }, + { + "name": "CreatorSwCfgSigverifyRsaModExpIbexEnSize", + "desc": "Size of CREATOR_SW_CFG_SIGVERIFY_RSA_MOD_EXP_IBEX_EN", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "CreatorSwCfgSigverifyRsaKeyEnOffset", + "desc": "Offset of CREATOR_SW_CFG_SIGVERIFY_RSA_KEY_EN", + "type": "int", + "default": "232", + "local": "true" + }, + { + "name": "CreatorSwCfgSigverifyRsaKeyEnSize", + "desc": "Size of CREATOR_SW_CFG_SIGVERIFY_RSA_KEY_EN", + "type": "int", + "default": "8", + "local": "true" + }, + { + "name": "CreatorSwCfgSigverifySpxEnOffset", + "desc": "Offset of CREATOR_SW_CFG_SIGVERIFY_SPX_EN", + "type": "int", + "default": "240", + "local": "true" + }, + { + "name": "CreatorSwCfgSigverifySpxEnSize", + "desc": "Size of CREATOR_SW_CFG_SIGVERIFY_SPX_EN", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "CreatorSwCfgSigverifySpxKeyEnOffset", + "desc": "Offset of CREATOR_SW_CFG_SIGVERIFY_SPX_KEY_EN", + "type": "int", + "default": "244", + "local": "true" + }, + { + "name": "CreatorSwCfgSigverifySpxKeyEnSize", + "desc": "Size of CREATOR_SW_CFG_SIGVERIFY_SPX_KEY_EN", + "type": "int", + "default": "8", + "local": "true" + }, + { + "name": "CreatorSwCfgFlashDataDefaultCfgOffset", + "desc": "Offset of CREATOR_SW_CFG_FLASH_DATA_DEFAULT_CFG", + "type": "int", + "default": "252", + "local": "true" + }, + { + "name": "CreatorSwCfgFlashDataDefaultCfgSize", + "desc": "Size of CREATOR_SW_CFG_FLASH_DATA_DEFAULT_CFG", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "CreatorSwCfgFlashInfoBootDataCfgOffset", + "desc": "Offset of CREATOR_SW_CFG_FLASH_INFO_BOOT_DATA_CFG", + "type": "int", + "default": "256", + "local": "true" + }, + { + "name": "CreatorSwCfgFlashInfoBootDataCfgSize", + "desc": "Size of CREATOR_SW_CFG_FLASH_INFO_BOOT_DATA_CFG", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "CreatorSwCfgFlashHwInfoCfgOverrideOffset", + "desc": "Offset of CREATOR_SW_CFG_FLASH_HW_INFO_CFG_OVERRIDE", + "type": "int", + "default": "260", + "local": "true" + }, + { + "name": "CreatorSwCfgFlashHwInfoCfgOverrideSize", + "desc": "Size of CREATOR_SW_CFG_FLASH_HW_INFO_CFG_OVERRIDE", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "CreatorSwCfgRngEnOffset", + "desc": "Offset of CREATOR_SW_CFG_RNG_EN", + "type": "int", + "default": "264", + "local": "true" + }, + { + "name": "CreatorSwCfgRngEnSize", + "desc": "Size of CREATOR_SW_CFG_RNG_EN", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "CreatorSwCfgJitterEnOffset", + "desc": "Offset of CREATOR_SW_CFG_JITTER_EN", + "type": "int", + "default": "268", + "local": "true" + }, + { + "name": "CreatorSwCfgJitterEnSize", + "desc": "Size of CREATOR_SW_CFG_JITTER_EN", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "CreatorSwCfgRetRamResetMaskOffset", + "desc": "Offset of CREATOR_SW_CFG_RET_RAM_RESET_MASK", + "type": "int", + "default": "272", + "local": "true" + }, + { + "name": "CreatorSwCfgRetRamResetMaskSize", + "desc": "Size of CREATOR_SW_CFG_RET_RAM_RESET_MASK", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "CreatorSwCfgManufStateOffset", + "desc": "Offset of CREATOR_SW_CFG_MANUF_STATE", + "type": "int", + "default": "276", + "local": "true" + }, + { + "name": "CreatorSwCfgManufStateSize", + "desc": "Size of CREATOR_SW_CFG_MANUF_STATE", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "CreatorSwCfgRomExecEnOffset", + "desc": "Offset of CREATOR_SW_CFG_ROM_EXEC_EN", + "type": "int", + "default": "280", + "local": "true" + }, + { + "name": "CreatorSwCfgRomExecEnSize", + "desc": "Size of CREATOR_SW_CFG_ROM_EXEC_EN", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "CreatorSwCfgCpuctrlOffset", + "desc": "Offset of CREATOR_SW_CFG_CPUCTRL", + "type": "int", + "default": "284", + "local": "true" + }, + { + "name": "CreatorSwCfgCpuctrlSize", + "desc": "Size of CREATOR_SW_CFG_CPUCTRL", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "CreatorSwCfgMinSecVerRomExtOffset", + "desc": "Offset of CREATOR_SW_CFG_MIN_SEC_VER_ROM_EXT", + "type": "int", + "default": "288", + "local": "true" + }, + { + "name": "CreatorSwCfgMinSecVerRomExtSize", + "desc": "Size of CREATOR_SW_CFG_MIN_SEC_VER_ROM_EXT", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "CreatorSwCfgMinSecVerBl0Offset", + "desc": "Offset of CREATOR_SW_CFG_MIN_SEC_VER_BL0", + "type": "int", + "default": "292", + "local": "true" + }, + { + "name": "CreatorSwCfgMinSecVerBl0Size", + "desc": "Size of CREATOR_SW_CFG_MIN_SEC_VER_BL0", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "CreatorSwCfgDefaultBootDataInProdEnOffset", + "desc": "Offset of CREATOR_SW_CFG_DEFAULT_BOOT_DATA_IN_PROD_EN", + "type": "int", + "default": "296", + "local": "true" + }, + { + "name": "CreatorSwCfgDefaultBootDataInProdEnSize", + "desc": "Size of CREATOR_SW_CFG_DEFAULT_BOOT_DATA_IN_PROD_EN", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "CreatorSwCfgRmaSpinEnOffset", + "desc": "Offset of CREATOR_SW_CFG_RMA_SPIN_EN", + "type": "int", + "default": "300", + "local": "true" + }, + { + "name": "CreatorSwCfgRmaSpinEnSize", + "desc": "Size of CREATOR_SW_CFG_RMA_SPIN_EN", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "CreatorSwCfgRmaSpinCyclesOffset", + "desc": "Offset of CREATOR_SW_CFG_RMA_SPIN_CYCLES", + "type": "int", + "default": "304", + "local": "true" + }, + { + "name": "CreatorSwCfgRmaSpinCyclesSize", + "desc": "Size of CREATOR_SW_CFG_RMA_SPIN_CYCLES", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "CreatorSwCfgRngRepcntThresholdsOffset", + "desc": "Offset of CREATOR_SW_CFG_RNG_REPCNT_THRESHOLDS", + "type": "int", + "default": "308", + "local": "true" + }, + { + "name": "CreatorSwCfgRngRepcntThresholdsSize", + "desc": "Size of CREATOR_SW_CFG_RNG_REPCNT_THRESHOLDS", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "CreatorSwCfgRngRepcntsThresholdsOffset", + "desc": "Offset of CREATOR_SW_CFG_RNG_REPCNTS_THRESHOLDS", + "type": "int", + "default": "312", + "local": "true" + }, + { + "name": "CreatorSwCfgRngRepcntsThresholdsSize", + "desc": "Size of CREATOR_SW_CFG_RNG_REPCNTS_THRESHOLDS", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "CreatorSwCfgRngAdaptpHiThresholdsOffset", + "desc": "Offset of CREATOR_SW_CFG_RNG_ADAPTP_HI_THRESHOLDS", + "type": "int", + "default": "316", + "local": "true" + }, + { + "name": "CreatorSwCfgRngAdaptpHiThresholdsSize", + "desc": "Size of CREATOR_SW_CFG_RNG_ADAPTP_HI_THRESHOLDS", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "CreatorSwCfgRngAdaptpLoThresholdsOffset", + "desc": "Offset of CREATOR_SW_CFG_RNG_ADAPTP_LO_THRESHOLDS", + "type": "int", + "default": "320", + "local": "true" + }, + { + "name": "CreatorSwCfgRngAdaptpLoThresholdsSize", + "desc": "Size of CREATOR_SW_CFG_RNG_ADAPTP_LO_THRESHOLDS", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "CreatorSwCfgRngBucketThresholdsOffset", + "desc": "Offset of CREATOR_SW_CFG_RNG_BUCKET_THRESHOLDS", + "type": "int", + "default": "324", + "local": "true" + }, + { + "name": "CreatorSwCfgRngBucketThresholdsSize", + "desc": "Size of CREATOR_SW_CFG_RNG_BUCKET_THRESHOLDS", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "CreatorSwCfgRngMarkovHiThresholdsOffset", + "desc": "Offset of CREATOR_SW_CFG_RNG_MARKOV_HI_THRESHOLDS", + "type": "int", + "default": "328", + "local": "true" + }, + { + "name": "CreatorSwCfgRngMarkovHiThresholdsSize", + "desc": "Size of CREATOR_SW_CFG_RNG_MARKOV_HI_THRESHOLDS", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "CreatorSwCfgRngMarkovLoThresholdsOffset", + "desc": "Offset of CREATOR_SW_CFG_RNG_MARKOV_LO_THRESHOLDS", + "type": "int", + "default": "332", + "local": "true" + }, + { + "name": "CreatorSwCfgRngMarkovLoThresholdsSize", + "desc": "Size of CREATOR_SW_CFG_RNG_MARKOV_LO_THRESHOLDS", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "CreatorSwCfgRngExthtHiThresholdsOffset", + "desc": "Offset of CREATOR_SW_CFG_RNG_EXTHT_HI_THRESHOLDS", + "type": "int", + "default": "336", + "local": "true" + }, + { + "name": "CreatorSwCfgRngExthtHiThresholdsSize", + "desc": "Size of CREATOR_SW_CFG_RNG_EXTHT_HI_THRESHOLDS", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "CreatorSwCfgRngExthtLoThresholdsOffset", + "desc": "Offset of CREATOR_SW_CFG_RNG_EXTHT_LO_THRESHOLDS", + "type": "int", + "default": "340", + "local": "true" + }, + { + "name": "CreatorSwCfgRngExthtLoThresholdsSize", + "desc": "Size of CREATOR_SW_CFG_RNG_EXTHT_LO_THRESHOLDS", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "CreatorSwCfgRngAlertThresholdOffset", + "desc": "Offset of CREATOR_SW_CFG_RNG_ALERT_THRESHOLD", + "type": "int", + "default": "344", + "local": "true" + }, + { + "name": "CreatorSwCfgRngAlertThresholdSize", + "desc": "Size of CREATOR_SW_CFG_RNG_ALERT_THRESHOLD", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "CreatorSwCfgRngHealthConfigDigestOffset", + "desc": "Offset of CREATOR_SW_CFG_RNG_HEALTH_CONFIG_DIGEST", + "type": "int", + "default": "348", + "local": "true" + }, + { + "name": "CreatorSwCfgRngHealthConfigDigestSize", + "desc": "Size of CREATOR_SW_CFG_RNG_HEALTH_CONFIG_DIGEST", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "CreatorSwCfgSramKeyRenewEnOffset", + "desc": "Offset of CREATOR_SW_CFG_SRAM_KEY_RENEW_EN", + "type": "int", + "default": "352", + "local": "true" + }, + { + "name": "CreatorSwCfgSramKeyRenewEnSize", + "desc": "Size of CREATOR_SW_CFG_SRAM_KEY_RENEW_EN", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "CreatorSwCfgDigestOffset", + "desc": "Offset of CREATOR_SW_CFG_DIGEST", + "type": "int", + "default": "480", + "local": "true" + }, + { + "name": "CreatorSwCfgDigestSize", + "desc": "Size of CREATOR_SW_CFG_DIGEST", + "type": "int", + "default": "8", + "local": "true" + }, + { + "name": "OwnerSwCfgOffset", + "desc": "Offset of the OWNER_SW_CFG partition", + "type": "int", + "default": "488", + "local": "true" + }, + { + "name": "OwnerSwCfgSize", + "desc": "Size of the OWNER_SW_CFG partition", + "type": "int", + "default": "656", + "local": "true" + }, + { + "name": "OwnerSwCfgRomErrorReportingOffset", + "desc": "Offset of OWNER_SW_CFG_ROM_ERROR_REPORTING", + "type": "int", + "default": "488", + "local": "true" + }, + { + "name": "OwnerSwCfgRomErrorReportingSize", + "desc": "Size of OWNER_SW_CFG_ROM_ERROR_REPORTING", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "OwnerSwCfgRomBootstrapDisOffset", + "desc": "Offset of OWNER_SW_CFG_ROM_BOOTSTRAP_DIS", + "type": "int", + "default": "492", + "local": "true" + }, + { + "name": "OwnerSwCfgRomBootstrapDisSize", + "desc": "Size of OWNER_SW_CFG_ROM_BOOTSTRAP_DIS", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "OwnerSwCfgRomAlertClassEnOffset", + "desc": "Offset of OWNER_SW_CFG_ROM_ALERT_CLASS_EN", + "type": "int", + "default": "496", + "local": "true" + }, + { + "name": "OwnerSwCfgRomAlertClassEnSize", + "desc": "Size of OWNER_SW_CFG_ROM_ALERT_CLASS_EN", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "OwnerSwCfgRomAlertEscalationOffset", + "desc": "Offset of OWNER_SW_CFG_ROM_ALERT_ESCALATION", + "type": "int", + "default": "500", + "local": "true" + }, + { + "name": "OwnerSwCfgRomAlertEscalationSize", + "desc": "Size of OWNER_SW_CFG_ROM_ALERT_ESCALATION", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "OwnerSwCfgRomAlertClassificationOffset", + "desc": "Offset of OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION", + "type": "int", + "default": "504", + "local": "true" + }, + { + "name": "OwnerSwCfgRomAlertClassificationSize", + "desc": "Size of OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION", + "type": "int", + "default": "320", + "local": "true" + }, + { + "name": "OwnerSwCfgRomLocalAlertClassificationOffset", + "desc": "Offset of OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION", + "type": "int", + "default": "824", + "local": "true" + }, + { + "name": "OwnerSwCfgRomLocalAlertClassificationSize", + "desc": "Size of OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION", + "type": "int", + "default": "64", + "local": "true" + }, + { + "name": "OwnerSwCfgRomAlertAccumThreshOffset", + "desc": "Offset of OWNER_SW_CFG_ROM_ALERT_ACCUM_THRESH", + "type": "int", + "default": "888", + "local": "true" + }, + { + "name": "OwnerSwCfgRomAlertAccumThreshSize", + "desc": "Size of OWNER_SW_CFG_ROM_ALERT_ACCUM_THRESH", + "type": "int", + "default": "16", + "local": "true" + }, + { + "name": "OwnerSwCfgRomAlertTimeoutCyclesOffset", + "desc": "Offset of OWNER_SW_CFG_ROM_ALERT_TIMEOUT_CYCLES", + "type": "int", + "default": "904", + "local": "true" + }, + { + "name": "OwnerSwCfgRomAlertTimeoutCyclesSize", + "desc": "Size of OWNER_SW_CFG_ROM_ALERT_TIMEOUT_CYCLES", + "type": "int", + "default": "16", + "local": "true" + }, + { + "name": "OwnerSwCfgRomAlertPhaseCyclesOffset", + "desc": "Offset of OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES", + "type": "int", + "default": "920", + "local": "true" + }, + { + "name": "OwnerSwCfgRomAlertPhaseCyclesSize", + "desc": "Size of OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES", + "type": "int", + "default": "64", + "local": "true" + }, + { + "name": "OwnerSwCfgRomAlertDigestProdOffset", + "desc": "Offset of OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD", + "type": "int", + "default": "984", + "local": "true" + }, + { + "name": "OwnerSwCfgRomAlertDigestProdSize", + "desc": "Size of OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "OwnerSwCfgRomAlertDigestProdEndOffset", + "desc": "Offset of OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD_END", + "type": "int", + "default": "988", + "local": "true" + }, + { + "name": "OwnerSwCfgRomAlertDigestProdEndSize", + "desc": "Size of OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD_END", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "OwnerSwCfgRomAlertDigestDevOffset", + "desc": "Offset of OWNER_SW_CFG_ROM_ALERT_DIGEST_DEV", + "type": "int", + "default": "992", + "local": "true" + }, + { + "name": "OwnerSwCfgRomAlertDigestDevSize", + "desc": "Size of OWNER_SW_CFG_ROM_ALERT_DIGEST_DEV", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "OwnerSwCfgRomAlertDigestRmaOffset", + "desc": "Offset of OWNER_SW_CFG_ROM_ALERT_DIGEST_RMA", + "type": "int", + "default": "996", + "local": "true" + }, + { + "name": "OwnerSwCfgRomAlertDigestRmaSize", + "desc": "Size of OWNER_SW_CFG_ROM_ALERT_DIGEST_RMA", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "OwnerSwCfgRomWatchdogBiteThresholdCyclesOffset", + "desc": "Offset of OWNER_SW_CFG_ROM_WATCHDOG_BITE_THRESHOLD_CYCLES", + "type": "int", + "default": "1000", + "local": "true" + }, + { + "name": "OwnerSwCfgRomWatchdogBiteThresholdCyclesSize", + "desc": "Size of OWNER_SW_CFG_ROM_WATCHDOG_BITE_THRESHOLD_CYCLES", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "OwnerSwCfgRomKeymgrRomExtMeasEnOffset", + "desc": "Offset of OWNER_SW_CFG_ROM_KEYMGR_ROM_EXT_MEAS_EN", + "type": "int", + "default": "1004", + "local": "true" + }, + { + "name": "OwnerSwCfgRomKeymgrRomExtMeasEnSize", + "desc": "Size of OWNER_SW_CFG_ROM_KEYMGR_ROM_EXT_MEAS_EN", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "OwnerSwCfgManufStateOffset", + "desc": "Offset of OWNER_SW_CFG_MANUF_STATE", + "type": "int", + "default": "1008", + "local": "true" + }, + { + "name": "OwnerSwCfgManufStateSize", + "desc": "Size of OWNER_SW_CFG_MANUF_STATE", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "OwnerSwCfgRomRstmgrInfoEnOffset", + "desc": "Offset of OWNER_SW_CFG_ROM_RSTMGR_INFO_EN", + "type": "int", + "default": "1012", + "local": "true" + }, + { + "name": "OwnerSwCfgRomRstmgrInfoEnSize", + "desc": "Size of OWNER_SW_CFG_ROM_RSTMGR_INFO_EN", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "OwnerSwCfgRomExtBootstrapEnOffset", + "desc": "Offset of OWNER_SW_CFG_ROM_EXT_BOOTSTRAP_EN", + "type": "int", + "default": "1016", + "local": "true" + }, + { + "name": "OwnerSwCfgRomExtBootstrapEnSize", + "desc": "Size of OWNER_SW_CFG_ROM_EXT_BOOTSTRAP_EN", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "OwnerSwCfgDigestOffset", + "desc": "Offset of OWNER_SW_CFG_DIGEST", + "type": "int", + "default": "1136", + "local": "true" + }, + { + "name": "OwnerSwCfgDigestSize", + "desc": "Size of OWNER_SW_CFG_DIGEST", + "type": "int", + "default": "8", + "local": "true" + }, + { + "name": "RotCreatorAuthCodesignOffset", + "desc": "Offset of the ROT_CREATOR_AUTH_CODESIGN partition", + "type": "int", + "default": "1144", + "local": "true" + }, + { + "name": "RotCreatorAuthCodesignSize", + "desc": "Size of the ROT_CREATOR_AUTH_CODESIGN partition", + "type": "int", + "default": "472", + "local": "true" + }, + { + "name": "RotCreatorAuthCodesignEcdsaKeyType0Offset", + "desc": "Offset of ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY_TYPE0", + "type": "int", + "default": "1144", + "local": "true" + }, + { + "name": "RotCreatorAuthCodesignEcdsaKeyType0Size", + "desc": "Size of ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY_TYPE0", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "RotCreatorAuthCodesignEcdsaKey0Offset", + "desc": "Offset of ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY0", + "type": "int", + "default": "1148", + "local": "true" + }, + { + "name": "RotCreatorAuthCodesignEcdsaKey0Size", + "desc": "Size of ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY0", + "type": "int", + "default": "64", + "local": "true" + }, + { + "name": "RotCreatorAuthCodesignEcdsaKeyType1Offset", + "desc": "Offset of ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY_TYPE1", + "type": "int", + "default": "1212", + "local": "true" + }, + { + "name": "RotCreatorAuthCodesignEcdsaKeyType1Size", + "desc": "Size of ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY_TYPE1", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "RotCreatorAuthCodesignEcdsaKey1Offset", + "desc": "Offset of ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY1", + "type": "int", + "default": "1216", + "local": "true" + }, + { + "name": "RotCreatorAuthCodesignEcdsaKey1Size", + "desc": "Size of ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY1", + "type": "int", + "default": "64", + "local": "true" + }, + { + "name": "RotCreatorAuthCodesignEcdsaKeyType2Offset", + "desc": "Offset of ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY_TYPE2", + "type": "int", + "default": "1280", + "local": "true" + }, + { + "name": "RotCreatorAuthCodesignEcdsaKeyType2Size", + "desc": "Size of ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY_TYPE2", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "RotCreatorAuthCodesignEcdsaKey2Offset", + "desc": "Offset of ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY2", + "type": "int", + "default": "1284", + "local": "true" + }, + { + "name": "RotCreatorAuthCodesignEcdsaKey2Size", + "desc": "Size of ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY2", + "type": "int", + "default": "64", + "local": "true" + }, + { + "name": "RotCreatorAuthCodesignEcdsaKeyType3Offset", + "desc": "Offset of ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY_TYPE3", + "type": "int", + "default": "1348", + "local": "true" + }, + { + "name": "RotCreatorAuthCodesignEcdsaKeyType3Size", + "desc": "Size of ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY_TYPE3", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "RotCreatorAuthCodesignEcdsaKey3Offset", + "desc": "Offset of ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY3", + "type": "int", + "default": "1352", + "local": "true" + }, + { + "name": "RotCreatorAuthCodesignEcdsaKey3Size", + "desc": "Size of ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY3", + "type": "int", + "default": "64", + "local": "true" + }, + { + "name": "RotCreatorAuthCodesignSpxKeyType0Offset", + "desc": "Offset of ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_TYPE0", + "type": "int", + "default": "1416", + "local": "true" + }, + { + "name": "RotCreatorAuthCodesignSpxKeyType0Size", + "desc": "Size of ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_TYPE0", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "RotCreatorAuthCodesignSpxKey0Offset", + "desc": "Offset of ROT_CREATOR_AUTH_CODESIGN_SPX_KEY0", + "type": "int", + "default": "1420", + "local": "true" + }, + { + "name": "RotCreatorAuthCodesignSpxKey0Size", + "desc": "Size of ROT_CREATOR_AUTH_CODESIGN_SPX_KEY0", + "type": "int", + "default": "32", + "local": "true" + }, + { + "name": "RotCreatorAuthCodesignSpxKeyConfig0Offset", + "desc": "Offset of ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_CONFIG0", + "type": "int", + "default": "1452", + "local": "true" + }, + { + "name": "RotCreatorAuthCodesignSpxKeyConfig0Size", + "desc": "Size of ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_CONFIG0", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "RotCreatorAuthCodesignSpxKeyType1Offset", + "desc": "Offset of ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_TYPE1", + "type": "int", + "default": "1456", + "local": "true" + }, + { + "name": "RotCreatorAuthCodesignSpxKeyType1Size", + "desc": "Size of ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_TYPE1", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "RotCreatorAuthCodesignSpxKey1Offset", + "desc": "Offset of ROT_CREATOR_AUTH_CODESIGN_SPX_KEY1", + "type": "int", + "default": "1460", + "local": "true" + }, + { + "name": "RotCreatorAuthCodesignSpxKey1Size", + "desc": "Size of ROT_CREATOR_AUTH_CODESIGN_SPX_KEY1", + "type": "int", + "default": "32", + "local": "true" + }, + { + "name": "RotCreatorAuthCodesignSpxKeyConfig1Offset", + "desc": "Offset of ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_CONFIG1", + "type": "int", + "default": "1492", + "local": "true" + }, + { + "name": "RotCreatorAuthCodesignSpxKeyConfig1Size", + "desc": "Size of ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_CONFIG1", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "RotCreatorAuthCodesignSpxKeyType2Offset", + "desc": "Offset of ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_TYPE2", + "type": "int", + "default": "1496", + "local": "true" + }, + { + "name": "RotCreatorAuthCodesignSpxKeyType2Size", + "desc": "Size of ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_TYPE2", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "RotCreatorAuthCodesignSpxKey2Offset", + "desc": "Offset of ROT_CREATOR_AUTH_CODESIGN_SPX_KEY2", + "type": "int", + "default": "1500", + "local": "true" + }, + { + "name": "RotCreatorAuthCodesignSpxKey2Size", + "desc": "Size of ROT_CREATOR_AUTH_CODESIGN_SPX_KEY2", + "type": "int", + "default": "32", + "local": "true" + }, + { + "name": "RotCreatorAuthCodesignSpxKeyConfig2Offset", + "desc": "Offset of ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_CONFIG2", + "type": "int", + "default": "1532", + "local": "true" + }, + { + "name": "RotCreatorAuthCodesignSpxKeyConfig2Size", + "desc": "Size of ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_CONFIG2", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "RotCreatorAuthCodesignSpxKeyType3Offset", + "desc": "Offset of ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_TYPE3", + "type": "int", + "default": "1536", + "local": "true" + }, + { + "name": "RotCreatorAuthCodesignSpxKeyType3Size", + "desc": "Size of ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_TYPE3", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "RotCreatorAuthCodesignSpxKey3Offset", + "desc": "Offset of ROT_CREATOR_AUTH_CODESIGN_SPX_KEY3", + "type": "int", + "default": "1540", + "local": "true" + }, + { + "name": "RotCreatorAuthCodesignSpxKey3Size", + "desc": "Size of ROT_CREATOR_AUTH_CODESIGN_SPX_KEY3", + "type": "int", + "default": "32", + "local": "true" + }, + { + "name": "RotCreatorAuthCodesignSpxKeyConfig3Offset", + "desc": "Offset of ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_CONFIG3", + "type": "int", + "default": "1572", + "local": "true" + }, + { + "name": "RotCreatorAuthCodesignSpxKeyConfig3Size", + "desc": "Size of ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_CONFIG3", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "RotCreatorAuthCodesignBlockSha2_256HashOffset", + "desc": "Offset of ROT_CREATOR_AUTH_CODESIGN_BLOCK_SHA2_256_HASH", + "type": "int", + "default": "1576", + "local": "true" + }, + { + "name": "RotCreatorAuthCodesignBlockSha2_256HashSize", + "desc": "Size of ROT_CREATOR_AUTH_CODESIGN_BLOCK_SHA2_256_HASH", + "type": "int", + "default": "32", + "local": "true" + }, + { + "name": "RotCreatorAuthCodesignDigestOffset", + "desc": "Offset of ROT_CREATOR_AUTH_CODESIGN_DIGEST", + "type": "int", + "default": "1608", + "local": "true" + }, + { + "name": "RotCreatorAuthCodesignDigestSize", + "desc": "Size of ROT_CREATOR_AUTH_CODESIGN_DIGEST", + "type": "int", + "default": "8", + "local": "true" + }, + { + "name": "RotCreatorAuthStateOffset", + "desc": "Offset of the ROT_CREATOR_AUTH_STATE partition", + "type": "int", + "default": "1616", + "local": "true" + }, + { + "name": "RotCreatorAuthStateSize", + "desc": "Size of the ROT_CREATOR_AUTH_STATE partition", + "type": "int", + "default": "40", + "local": "true" + }, + { + "name": "RotCreatorAuthStateEcdsaKey0Offset", + "desc": "Offset of ROT_CREATOR_AUTH_STATE_ECDSA_KEY0", + "type": "int", + "default": "1616", + "local": "true" + }, + { + "name": "RotCreatorAuthStateEcdsaKey0Size", + "desc": "Size of ROT_CREATOR_AUTH_STATE_ECDSA_KEY0", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "RotCreatorAuthStateEcdsaKey1Offset", + "desc": "Offset of ROT_CREATOR_AUTH_STATE_ECDSA_KEY1", + "type": "int", + "default": "1620", + "local": "true" + }, + { + "name": "RotCreatorAuthStateEcdsaKey1Size", + "desc": "Size of ROT_CREATOR_AUTH_STATE_ECDSA_KEY1", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "RotCreatorAuthStateEcdsaKey2Offset", + "desc": "Offset of ROT_CREATOR_AUTH_STATE_ECDSA_KEY2", + "type": "int", + "default": "1624", + "local": "true" + }, + { + "name": "RotCreatorAuthStateEcdsaKey2Size", + "desc": "Size of ROT_CREATOR_AUTH_STATE_ECDSA_KEY2", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "RotCreatorAuthStateEcdsaKey3Offset", + "desc": "Offset of ROT_CREATOR_AUTH_STATE_ECDSA_KEY3", + "type": "int", + "default": "1628", + "local": "true" + }, + { + "name": "RotCreatorAuthStateEcdsaKey3Size", + "desc": "Size of ROT_CREATOR_AUTH_STATE_ECDSA_KEY3", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "RotCreatorAuthStateSpxKey0Offset", + "desc": "Offset of ROT_CREATOR_AUTH_STATE_SPX_KEY0", + "type": "int", + "default": "1632", + "local": "true" + }, + { + "name": "RotCreatorAuthStateSpxKey0Size", + "desc": "Size of ROT_CREATOR_AUTH_STATE_SPX_KEY0", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "RotCreatorAuthStateSpxKey1Offset", + "desc": "Offset of ROT_CREATOR_AUTH_STATE_SPX_KEY1", + "type": "int", + "default": "1636", + "local": "true" + }, + { + "name": "RotCreatorAuthStateSpxKey1Size", + "desc": "Size of ROT_CREATOR_AUTH_STATE_SPX_KEY1", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "RotCreatorAuthStateSpxKey2Offset", + "desc": "Offset of ROT_CREATOR_AUTH_STATE_SPX_KEY2", + "type": "int", + "default": "1640", + "local": "true" + }, + { + "name": "RotCreatorAuthStateSpxKey2Size", + "desc": "Size of ROT_CREATOR_AUTH_STATE_SPX_KEY2", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "RotCreatorAuthStateSpxKey3Offset", + "desc": "Offset of ROT_CREATOR_AUTH_STATE_SPX_KEY3", + "type": "int", + "default": "1644", + "local": "true" + }, + { + "name": "RotCreatorAuthStateSpxKey3Size", + "desc": "Size of ROT_CREATOR_AUTH_STATE_SPX_KEY3", + "type": "int", + "default": "4", + "local": "true" + }, + { + "name": "RotCreatorAuthStateDigestOffset", + "desc": "Offset of ROT_CREATOR_AUTH_STATE_DIGEST", + "type": "int", + "default": "1648", + "local": "true" + }, + { + "name": "RotCreatorAuthStateDigestSize", + "desc": "Size of ROT_CREATOR_AUTH_STATE_DIGEST", + "type": "int", + "default": "8", + "local": "true" + }, + { + "name": "HwCfg0Offset", + "desc": "Offset of the HW_CFG0 partition", + "type": "int", + "default": "1656", + "local": "true" + }, + { + "name": "HwCfg0Size", + "desc": "Size of the HW_CFG0 partition", + "type": "int", + "default": "72", + "local": "true" + }, + { + "name": "DeviceIdOffset", + "desc": "Offset of DEVICE_ID", + "type": "int", + "default": "1656", + "local": "true" + }, + { + "name": "DeviceIdSize", + "desc": "Size of DEVICE_ID", + "type": "int", + "default": "32", + "local": "true" + }, + { + "name": "ManufStateOffset", + "desc": "Offset of MANUF_STATE", + "type": "int", + "default": "1688", + "local": "true" + }, + { + "name": "ManufStateSize", + "desc": "Size of MANUF_STATE", + "type": "int", + "default": "32", + "local": "true" + }, + { + "name": "HwCfg0DigestOffset", + "desc": "Offset of HW_CFG0_DIGEST", + "type": "int", + "default": "1720", + "local": "true" + }, + { + "name": "HwCfg0DigestSize", + "desc": "Size of HW_CFG0_DIGEST", + "type": "int", + "default": "8", + "local": "true" + }, + { + "name": "HwCfg1Offset", + "desc": "Offset of the HW_CFG1 partition", + "type": "int", + "default": "1728", + "local": "true" + }, + { + "name": "HwCfg1Size", + "desc": "Size of the HW_CFG1 partition", + "type": "int", + "default": "16", + "local": "true" + }, + { + "name": "EnSramIfetchOffset", + "desc": "Offset of EN_SRAM_IFETCH", + "type": "int", + "default": "1728", + "local": "true" + }, + { + "name": "EnSramIfetchSize", + "desc": "Size of EN_SRAM_IFETCH", + "type": "int", + "default": "1", + "local": "true" + }, + { + "name": "EnCsrngSwAppReadOffset", + "desc": "Offset of EN_CSRNG_SW_APP_READ", + "type": "int", + "default": "1729", + "local": "true" + }, + { + "name": "EnCsrngSwAppReadSize", + "desc": "Size of EN_CSRNG_SW_APP_READ", + "type": "int", + "default": "1", + "local": "true" + }, + { + "name": "DisRvDmLateDebugOffset", + "desc": "Offset of DIS_RV_DM_LATE_DEBUG", + "type": "int", + "default": "1730", + "local": "true" + }, + { + "name": "DisRvDmLateDebugSize", + "desc": "Size of DIS_RV_DM_LATE_DEBUG", + "type": "int", + "default": "1", + "local": "true" + }, + { + "name": "HwCfg1DigestOffset", + "desc": "Offset of HW_CFG1_DIGEST", + "type": "int", + "default": "1736", + "local": "true" + }, + { + "name": "HwCfg1DigestSize", + "desc": "Size of HW_CFG1_DIGEST", + "type": "int", + "default": "8", + "local": "true" + }, + { + "name": "Secret0Offset", + "desc": "Offset of the SECRET0 partition", + "type": "int", + "default": "1744", + "local": "true" + }, + { + "name": "Secret0Size", + "desc": "Size of the SECRET0 partition", + "type": "int", + "default": "40", + "local": "true" + }, + { + "name": "TestUnlockTokenOffset", + "desc": "Offset of TEST_UNLOCK_TOKEN", + "type": "int", + "default": "1744", + "local": "true" + }, + { + "name": "TestUnlockTokenSize", + "desc": "Size of TEST_UNLOCK_TOKEN", + "type": "int", + "default": "16", + "local": "true" + }, + { + "name": "TestExitTokenOffset", + "desc": "Offset of TEST_EXIT_TOKEN", + "type": "int", + "default": "1760", + "local": "true" + }, + { + "name": "TestExitTokenSize", + "desc": "Size of TEST_EXIT_TOKEN", + "type": "int", + "default": "16", + "local": "true" + }, + { + "name": "Secret0DigestOffset", + "desc": "Offset of SECRET0_DIGEST", + "type": "int", + "default": "1776", + "local": "true" + }, + { + "name": "Secret0DigestSize", + "desc": "Size of SECRET0_DIGEST", + "type": "int", + "default": "8", + "local": "true" + }, + { + "name": "Secret1Offset", + "desc": "Offset of the SECRET1 partition", + "type": "int", + "default": "1784", + "local": "true" + }, + { + "name": "Secret1Size", + "desc": "Size of the SECRET1 partition", + "type": "int", + "default": "88", + "local": "true" + }, + { + "name": "FlashAddrKeySeedOffset", + "desc": "Offset of FLASH_ADDR_KEY_SEED", + "type": "int", + "default": "1784", + "local": "true" + }, + { + "name": "FlashAddrKeySeedSize", + "desc": "Size of FLASH_ADDR_KEY_SEED", + "type": "int", + "default": "32", + "local": "true" + }, + { + "name": "FlashDataKeySeedOffset", + "desc": "Offset of FLASH_DATA_KEY_SEED", + "type": "int", + "default": "1816", + "local": "true" + }, + { + "name": "FlashDataKeySeedSize", + "desc": "Size of FLASH_DATA_KEY_SEED", + "type": "int", + "default": "32", + "local": "true" + }, + { + "name": "SramDataKeySeedOffset", + "desc": "Offset of SRAM_DATA_KEY_SEED", + "type": "int", + "default": "1848", + "local": "true" + }, + { + "name": "SramDataKeySeedSize", + "desc": "Size of SRAM_DATA_KEY_SEED", + "type": "int", + "default": "16", + "local": "true" + }, + { + "name": "Secret1DigestOffset", + "desc": "Offset of SECRET1_DIGEST", + "type": "int", + "default": "1864", + "local": "true" + }, + { + "name": "Secret1DigestSize", + "desc": "Size of SECRET1_DIGEST", + "type": "int", + "default": "8", + "local": "true" + }, + { + "name": "Secret2Offset", + "desc": "Offset of the SECRET2 partition", + "type": "int", + "default": "1872", + "local": "true" + }, + { + "name": "Secret2Size", + "desc": "Size of the SECRET2 partition", + "type": "int", + "default": "88", + "local": "true" + }, + { + "name": "RmaTokenOffset", + "desc": "Offset of RMA_TOKEN", + "type": "int", + "default": "1872", + "local": "true" + }, + { + "name": "RmaTokenSize", + "desc": "Size of RMA_TOKEN", + "type": "int", + "default": "16", + "local": "true" + }, + { + "name": "CreatorRootKeyShare0Offset", + "desc": "Offset of CREATOR_ROOT_KEY_SHARE0", + "type": "int", + "default": "1888", + "local": "true" + }, + { + "name": "CreatorRootKeyShare0Size", + "desc": "Size of CREATOR_ROOT_KEY_SHARE0", + "type": "int", + "default": "32", + "local": "true" + }, + { + "name": "CreatorRootKeyShare1Offset", + "desc": "Offset of CREATOR_ROOT_KEY_SHARE1", + "type": "int", + "default": "1920", + "local": "true" + }, + { + "name": "CreatorRootKeyShare1Size", + "desc": "Size of CREATOR_ROOT_KEY_SHARE1", + "type": "int", + "default": "32", + "local": "true" + }, + { + "name": "Secret2DigestOffset", + "desc": "Offset of SECRET2_DIGEST", + "type": "int", + "default": "1952", + "local": "true" + }, + { + "name": "Secret2DigestSize", + "desc": "Size of SECRET2_DIGEST", + "type": "int", + "default": "8", + "local": "true" + }, + { + "name": "LifeCycleOffset", + "desc": "Offset of the LIFE_CYCLE partition", + "type": "int", + "default": "1960", + "local": "true" + }, + { + "name": "LifeCycleSize", + "desc": "Size of the LIFE_CYCLE partition", + "type": "int", + "default": "88", + "local": "true" + }, + { + "name": "LcTransitionCntOffset", + "desc": "Offset of LC_TRANSITION_CNT", + "type": "int", + "default": "1960", + "local": "true" + }, + { + "name": "LcTransitionCntSize", + "desc": "Size of LC_TRANSITION_CNT", + "type": "int", + "default": "48", + "local": "true" + }, + { + "name": "LcStateOffset", + "desc": "Offset of LC_STATE", + "type": "int", + "default": "2008", + "local": "true" + }, + { + "name": "LcStateSize", + "desc": "Size of LC_STATE", + "type": "int", + "default": "40", + "local": "true" + } + ], + "inter_signal_list": [ + { + "struct": "", + "type": "io", + "name": "otp_ext_voltage_h", + "act": "none", + "default": "'0", + "package": "" + }, + { + "struct": "otp_ast_req", + "type": "uni", + "name": "otp_ast_pwr_seq", + "act": "req", + "default": "'0", + "package": "otp_ctrl_pkg", + "desc": "Power sequencing signals to AST (VDD domain)." + }, + { + "struct": "otp_ast_rsp", + "type": "uni", + "name": "otp_ast_pwr_seq_h", + "act": "rcv", + "default": "'0", + "package": "otp_ctrl_pkg", + "desc": "Power sequencing signals coming from AST (VCC domain)." + }, + { + "struct": "edn", + "type": "req_rsp", + "name": "edn", + "act": "req", + "package": "edn_pkg", + "desc": "Entropy request to the entropy distribution network for LFSR reseeding and ephemeral key derivation." + }, + { + "struct": "pwr_otp", + "type": "req_rsp", + "name": "pwr_otp", + "act": "rsp", + "default": "'0", + "package": "pwrmgr_pkg", + "desc": "Initialization request/acknowledge from/to power manager." + }, + { + "struct": "lc_otp_vendor_test", + "type": "req_rsp", + "name": "lc_otp_vendor_test", + "act": "rsp", + "default": "'0", + "package": "otp_ctrl_pkg", + "desc": "Vendor test control signals from/to the life cycle TAP." + }, + { + "struct": "lc_otp_program", + "type": "req_rsp", + "name": "lc_otp_program", + "act": "rsp", + "default": "'0", + "package": "otp_ctrl_pkg", + "desc": "Life cycle state transition interface." + }, + { + "struct": "otp_lc_data", + "type": "uni", + "name": "otp_lc_data", + "act": "req", + "default": "'0", + "package": "otp_ctrl_pkg", + "desc": "Life cycle state output holding the current life cycle state,\nthe value of the transition counter and the tokens needed for life cycle transitions." + }, + { + "struct": "lc_tx", + "type": "uni", + "name": "lc_escalate_en", + "act": "rcv", + "default": "lc_ctrl_pkg::Off", + "package": "lc_ctrl_pkg", + "desc": "Life cycle escalation enable coming from life cycle controller.\nThis signal moves all FSMs within OTP into the error state." + }, + { + "struct": "lc_tx", + "type": "uni", + "name": "lc_creator_seed_sw_rw_en", + "act": "rcv", + "default": "lc_ctrl_pkg::Off", + "package": "lc_ctrl_pkg", + "desc": "Provision enable qualifier coming from life cycle controller.\nThis signal enables SW read / write access to the RMA_TOKEN and CREATOR_ROOT_KEY_SHARE0 and CREATOR_ROOT_KEY_SHARE1." + }, + { + "struct": "lc_tx", + "type": "uni", + "name": "lc_owner_seed_sw_rw_en", + "act": "rcv", + "default": "lc_ctrl_pkg::Off", + "package": "lc_ctrl_pkg", + "desc": "Provision enable qualifier coming from life cycle controller.\nThis signal enables SW read / write access to the OWNER_SEED." + }, + { + "struct": "lc_tx", + "type": "uni", + "name": "lc_seed_hw_rd_en", + "act": "rcv", + "default": "lc_ctrl_pkg::Off", + "package": "lc_ctrl_pkg", + "desc": "Seed read enable coming from life cycle controller.\nThis signal enables HW read access to the CREATOR_ROOT_KEY_SHARE0 and CREATOR_ROOT_KEY_SHARE1." + }, + { + "struct": "lc_tx", + "type": "uni", + "name": "lc_dft_en", + "act": "rcv", + "default": "lc_ctrl_pkg::Off", + "package": "lc_ctrl_pkg", + "desc": "Test enable qualifier coming from life cycle controller.\nThis signals enables the TL-UL access port to the proprietary OTP IP." + }, + { + "struct": "lc_tx", + "type": "uni", + "name": "lc_check_byp_en", + "act": "rcv", + "default": "lc_ctrl_pkg::Off", + "package": "lc_ctrl_pkg", + "desc": "Life cycle partition check bypass signal.\nThis signal causes the life cycle partition to bypass consistency checks during life cycle state transitions in order to prevent spurious consistency check failures." + }, + { + "struct": "otp_keymgr_key", + "type": "uni", + "name": "otp_keymgr_key", + "act": "req", + "default": "'0", + "package": "otp_ctrl_pkg", + "desc": "Key output to the key manager holding CREATOR_ROOT_KEY_SHARE0 and CREATOR_ROOT_KEY_SHARE1." + }, + { + "struct": "flash_otp_key", + "type": "req_rsp", + "name": "flash_otp_key", + "act": "rsp", + "default": "'0", + "package": "otp_ctrl_pkg", + "desc": "Key derivation interface for FLASH scrambling." + }, + { + "struct": "sram_otp_key", + "width": "4", + "type": "req_rsp", + "name": "sram_otp_key", + "act": "rsp", + "default": "'0", + "package": "otp_ctrl_pkg", + "desc": "Array with key derivation interfaces for SRAM scrambling devices." + }, + { + "struct": "otbn_otp_key", + "type": "req_rsp", + "name": "otbn_otp_key", + "act": "rsp", + "default": "'0", + "package": "otp_ctrl_pkg", + "desc": "Key derivation interface for OTBN scrambling devices." + }, + { + "struct": "otp_broadcast", + "type": "uni", + "name": "otp_broadcast", + "act": "req", + "default": "'0", + "package": "otp_ctrl_part_pkg", + "desc": "Output of the HW partitions with breakout data types." + }, + { + "struct": "ast_obs_ctrl", + "type": "uni", + "name": "obs_ctrl", + "act": "rcv", + "package": "ast_pkg", + "desc": "AST observability control signals." + }, + { + "struct": "logic", + "type": "uni", + "name": "otp_obs", + "act": "req", + "width": "8", + "package": "", + "desc": "AST observability bus." + } + ], + "countermeasures": [ + { + "name": "BUS.INTEGRITY", + "desc": "End-to-end bus integrity scheme." + }, + { + "name": "SECRET.MEM.SCRAMBLE", + "desc": "Secret partitions are scrambled with a full-round PRESENT cipher." + }, + { + "name": "PART.MEM.DIGEST", + "desc": "Integrity of buffered partitions is ensured via a 64bit digest." + }, + { + "name": "DAI.FSM.SPARSE", + "desc": "The direct access interface FSM is sparsely encoded." + }, + { + "name": "KDI.FSM.SPARSE", + "desc": "The key derivation interface FSM is sparsely encoded." + }, + { + "name": "LCI.FSM.SPARSE", + "desc": "The life cycle interface FSM is sparsely encoded." + }, + { + "name": "PART.FSM.SPARSE", + "desc": "The partition FSMs are sparsely encoded." + }, + { + "name": "SCRMBL.FSM.SPARSE", + "desc": "The scramble datapath FSM is sparsely encoded." + }, + { + "name": "TIMER.FSM.SPARSE", + "desc": "The background check timer FSM is sparsely encoded." + }, + { + "name": "DAI.CTR.REDUN", + "desc": "The direct access interface address counter employs a cross-counter implementation." + }, + { + "name": "KDI_SEED.CTR.REDUN", + "desc": "The key derivation interface counter employs a cross-counter implementation." + }, + { + "name": "KDI_ENTROPY.CTR.REDUN", + "desc": "The key derivation entropy counter employs a cross-counter implementation." + }, + { + "name": "LCI.CTR.REDUN", + "desc": "The life cycle interface address counter employs a cross-counter implementation." + }, + { + "name": "PART.CTR.REDUN", + "desc": "The address counter of buffered partitions employs a cross-counter implementation." + }, + { + "name": "SCRMBL.CTR.REDUN", + "desc": "The srambling datapath counter employs a cross-counter implementation." + }, + { + "name": "TIMER_INTEG.CTR.REDUN", + "desc": "The background integrity check timer employs a duplicated counter implementation." + }, + { + "name": "TIMER_CNSTY.CTR.REDUN", + "desc": "The background consistency check timer employs a duplicated counter implementation." + }, + { + "name": "TIMER.LFSR.REDUN", + "desc": "The background check LFSR is duplicated." + }, + { + "name": "DAI.FSM.LOCAL_ESC", + "desc": "The direct access interface FSM is moved into an invalid state upon local escalation." + }, + { + "name": "LCI.FSM.LOCAL_ESC", + "desc": "The life cycle interface FSM is moved into an invalid state upon local escalation." + }, + { + "name": "KDI.FSM.LOCAL_ESC", + "desc": "The key derivation interface FSM is moved into an invalid state upon local escalation." + }, + { + "name": "PART.FSM.LOCAL_ESC", + "desc": "The partition FSMs are moved into an invalid state upon local escalation." + }, + { + "name": "SCRMBL.FSM.LOCAL_ESC", + "desc": "The scramble datapath FSM is moved into an invalid state upon local escalation." + }, + { + "name": "TIMER.FSM.LOCAL_ESC", + "desc": "The background check timer FSM is moved into an invalid state upon local escalation." + }, + { + "name": "DAI.FSM.GLOBAL_ESC", + "desc": "The direct access interface FSM is moved into an invalid state upon global escalation via life cycle." + }, + { + "name": "LCI.FSM.GLOBAL_ESC", + "desc": "The life cycle interface FSM is moved into an invalid state upon global escalation via life cycle." + }, + { + "name": "KDI.FSM.GLOBAL_ESC", + "desc": "The key derivation interface FSM is moved into an invalid state upon global escalation via life cycle." + }, + { + "name": "PART.FSM.GLOBAL_ESC", + "desc": "The partition FSMs are moved into an invalid state upon global escalation via life cycle." + }, + { + "name": "SCRMBL.FSM.GLOBAL_ESC", + "desc": "The scramble datapath FSM is moved into an invalid state upon global escalation via life cycle." + }, + { + "name": "TIMER.FSM.GLOBAL_ESC", + "desc": "The background check timer FSM is moved into an invalid state upon global escalation via life cycle." + }, + { + "name": "PART.DATA_REG.INTEGRITY", + "desc": "All partition buffer registers are protected with ECC on 64bit blocks." + }, + { + "name": "PART.DATA_REG.BKGN_CHK", + "desc": "The digest of buffered partitions is recomputed and checked at pseudorandom intervals in the background." + }, + { + "name": "PART.MEM.REGREN", + "desc": "Unbuffered ('software') partitions can be read-locked via a CSR until the next system reset." + }, + { + "name": "PART.MEM.SW_UNREADABLE", + "desc": "Secret buffered partitions become unreadable to software once they are locked via the digest." + }, + { + "name": "PART.MEM.SW_UNWRITABLE", + "desc": "All partitions become unwritable by software once they are locked via the digest." + }, + { + "name": "LC_PART.MEM.SW_NOACCESS", + "desc": "The life cycle partition is not directly readable nor writable via software." + }, + { + "name": "ACCESS.CTRL.MUBI", + "desc": "The access control signals going from the partitions to the DAI are MUBI encoded." + }, + { + "name": "TOKEN_VALID.CTRL.MUBI", + "desc": "The token valid signals going to the life cycle controller are MUBI encoded." + }, + { + "name": "LC_CTRL.INTERSIG.MUBI", + "desc": "The life cycle control signals are multibit encoded." + }, + { + "name": "TEST.BUS.LC_GATED", + "desc": "Prevent access to test signals and the OTP backdoor interface in non-test lifecycle states." + }, + { + "name": "TEST_TL_LC_GATE.FSM.SPARSE", + "desc": "The control FSM inside the TL-UL gating primitive is sparsely encoded." + }, + { + "name": "DIRECT_ACCESS.CONFIG.REGWEN", + "desc": "The direct access CSRs are REGWEN protected." + }, + { + "name": "CHECK_TRIGGER.CONFIG.REGWEN", + "desc": "The check trigger CSR is REGWEN protected." + }, + { + "name": "CHECK.CONFIG.REGWEN", + "desc": "The check CSR is REGWEN protected." + }, + { + "name": "MACRO.MEM.INTEGRITY", + "desc": "The OTP macro employs a vendor-specific integrity scheme at the granularity of the native 16bit OTP words.\nThe scheme is able to at least detect single bit errors." + }, + { + "name": "MACRO.MEM.CM", + "desc": "The OTP macro may contain additional vendor-specific countermeasures." + } + ], + "features": [ + { + "name": "OTP_CTRL.PARTITION.VENDOR_TEST", + "desc": "Vendor test partition is used for OTP programming smoke check during manufacturing flow.\nIn this partition, ECC uncorrectable errors will not lead to fatal errors and alerts.\nInstead the error will be reported as correctable ECC error." + }, + { + "name": "OTP_CTRL.PARTITION.CREATOR_SW_CFG", + "desc": "During calibration stage, various parameters (clock, voltage, and timing sources) are calibrated and recorded to CREATOR_SW_CFG partition." + }, + { + "name": "OTP_CTRL.PARTITION.OWNER_SW_CFG", + "desc": "Define attriutes for rom code execution" + }, + { + "name": "OTP_CTRL.INIT", + "desc": "When power is up, OTP controller reads devices status.\nAfter all reads complete, the controller performs integrity check on the HW_CFG* and SECRET partitions.\nOnce all integrity checks are complete, the controller marks outputs as valid." + }, + { + "name": "OTP_CTRL.ENTROPY_READ", + "desc": "Firmware can read entropy from ENTROPY_SRC block by configuring following field of HW_CFG* partition.\n- EN_CSRNG_SW_APP_READ" + }, + { + "name": "OTP_CTRL.KEY_DERIVATION", + "desc": "OTP controller participate key derivation process by providing scramble key seed to SRAM_CTRL and FLASH_CTRL." + }, + { + "name": "OTP_CTRL.PROGRAM", + "desc": "All other partitions except life cycle partition are programmed through DAI interface.\nAnd once non-zero digest is programmed to these partition, no further write access is allowed.\nLife cycle partition is programmed by LC_CTRL." + }, + { + "name": "OTP_CTRL.PARTITION.SECRET0", + "desc": "Test unlock tokens, Test exit token" + }, + { + "name": "OTP_CTRL.PARTITION.SECRET1", + "desc": "SRAM and FLASH scrambling key" + }, + { + "name": "OTP_CTRL.PARTITION.SECRET2", + "desc": "RMA unlock token and creator root key" + }, + { + "name": "OTP_CTRL.PARTITION.LIFE_CYCLE", + "desc": "LC state, LC transition count.\nThis feature is owned by the LC_CTRL and cannot be tested well through the OTP_CTRL CSR interface." + }, + { + "name": "OTP_CTRL.PARTITIONS_FEATURE.READ_LOCK", + "desc": "Following partitions can be read lockable by CSR.\n - VENDOR_TEST\n - CREATOR_SW_CFG\n - OWNER_SW_CFG\n Following partitions can be read lockable by writing digest.\n - SECRET0\n - SECRET1\n - RECRET2\nAll read attempt to these partitions after read is locked will trigger AccessError (recoverable)." + }, + { + "name": "OTP_CTRL.PARTITIONS_FEATURE.WRITE_LOCK", + "desc": "All partitions except LIFE_CYCLE can be write lockable by writing digest." + }, + { + "name": "OTP_CTRL.ERROR_HANDLING.RECOVERABLE", + "desc": "Recoverable error is created when unauthorized access atempt are detected via dai interface." + }, + { + "name": "OTP_CTRL.ERROR_HANDLING.FATAL", + "desc": "Unrecoverable errors are created for uncorrectable ecc error, otp macro malfunction and unauthorized access via lc_ctrl." + }, + { + "name": "OTP_CTRL.BACKGROUND_CHECK.CHECK_TIMEOUT", + "desc": "Timeout value for the integrity and consistency checks." + }, + { + "name": "OTP_CTRL.BACKGROUND_CHECK.INTEGRITY_CHECK_PERIOD", + "desc": "The interval which the digest of the partition is recomputed to check integrity of locked partition." + }, + { + "name": "OTP_CTRL.BACKGROUND_CHECK.CONSISTENCY_CHECK_PERIOD", + "desc": "Re-read period of the buffer registers to ensure data is matched with the associated OTP partition." + } + ], + "regwidth": "32", + "registers": { + "core": [ + { + "name": "STATUS", + "desc": "OTP status register.", + "swaccess": "ro", + "hwaccess": "hwo", + "hwext": "true", + "resval": 0, + "tags": [ + "excl:CsrAllTests:CsrExclCheck" + ], + "fields": [ + { + "bits": "0", + "name": "VENDOR_TEST_ERROR", + "desc": "Set to 1 if an error occurred in this partition.\nIf set to 1, SW should check the !!ERR_CODE register at the corresponding index." + }, + { + "bits": "1", + "name": "CREATOR_SW_CFG_ERROR", + "desc": "Set to 1 if an error occurred in this partition.\nIf set to 1, SW should check the !!ERR_CODE register at the corresponding index." + }, + { + "bits": "2", + "name": "OWNER_SW_CFG_ERROR", + "desc": "Set to 1 if an error occurred in this partition.\nIf set to 1, SW should check the !!ERR_CODE register at the corresponding index." + }, + { + "bits": "3", + "name": "ROT_CREATOR_AUTH_CODESIGN_ERROR", + "desc": "Set to 1 if an error occurred in this partition.\nIf set to 1, SW should check the !!ERR_CODE register at the corresponding index." + }, + { + "bits": "4", + "name": "ROT_CREATOR_AUTH_STATE_ERROR", + "desc": "Set to 1 if an error occurred in this partition.\nIf set to 1, SW should check the !!ERR_CODE register at the corresponding index." + }, + { + "bits": "5", + "name": "HW_CFG0_ERROR", + "desc": "Set to 1 if an error occurred in this partition.\nIf set to 1, SW should check the !!ERR_CODE register at the corresponding index." + }, + { + "bits": "6", + "name": "HW_CFG1_ERROR", + "desc": "Set to 1 if an error occurred in this partition.\nIf set to 1, SW should check the !!ERR_CODE register at the corresponding index." + }, + { + "bits": "7", + "name": "SECRET0_ERROR", + "desc": "Set to 1 if an error occurred in this partition.\nIf set to 1, SW should check the !!ERR_CODE register at the corresponding index." + }, + { + "bits": "8", + "name": "SECRET1_ERROR", + "desc": "Set to 1 if an error occurred in this partition.\nIf set to 1, SW should check the !!ERR_CODE register at the corresponding index." + }, + { + "bits": "9", + "name": "SECRET2_ERROR", + "desc": "Set to 1 if an error occurred in this partition.\nIf set to 1, SW should check the !!ERR_CODE register at the corresponding index." + }, + { + "bits": "10", + "name": "LIFE_CYCLE_ERROR", + "desc": "Set to 1 if an error occurred in this partition.\nIf set to 1, SW should check the !!ERR_CODE register at the corresponding index." + }, + { + "bits": "11", + "name": "DAI_ERROR", + "desc": "Set to 1 if an error occurred in the DAI.\nIf set to 1, SW should check the !!ERR_CODE register at the corresponding index." + }, + { + "bits": "12", + "name": "LCI_ERROR", + "desc": "Set to 1 if an error occurred in the LCI.\nIf set to 1, SW should check the !!ERR_CODE register at the corresponding index." + }, + { + "bits": "13", + "name": "TIMEOUT_ERROR", + "desc": "Set to 1 if an integrity or consistency check times out.\nThis raises an fatal_check_error alert and is an unrecoverable error condition." + }, + { + "bits": "14", + "name": "LFSR_FSM_ERROR", + "desc": "Set to 1 if the LFSR timer FSM has reached an invalid state.\nThis raises an fatal_check_error alert and is an unrecoverable error condition." + }, + { + "bits": "15", + "name": "SCRAMBLING_FSM_ERROR", + "desc": "Set to 1 if the scrambling datapath FSM has reached an invalid state.\nThis raises an fatal_check_error alert and is an unrecoverable error condition." + }, + { + "bits": "16", + "name": "KEY_DERIV_FSM_ERROR", + "desc": "Set to 1 if the key derivation FSM has reached an invalid state.\nThis raises an fatal_check_error alert and is an unrecoverable error condition." + }, + { + "bits": "17", + "name": "BUS_INTEG_ERROR", + "desc": "This bit is set to 1 if a fatal bus integrity fault is detected.\nThis error triggers a fatal_bus_integ_error alert." + }, + { + "bits": "18", + "name": "DAI_IDLE", + "desc": "Set to 1 if the DAI is idle and ready to accept commands." + }, + { + "bits": "19", + "name": "CHECK_PENDING", + "desc": "Set to 1 if an integrity or consistency check triggered by the LFSR timer or via !!CHECK_TRIGGER is pending." + } + ] + }, + { + "multireg": { + "name": "ERR_CODE", + "desc": "This register holds information about error conditions that occurred in the agents\ninteracting with the OTP macro via the internal bus. The error codes should be checked\nif the partitions, DAI or LCI flag an error in the !!STATUS register, or when an\n!!INTR_STATE.otp_error has been triggered. Note that all errors trigger an otp_error\ninterrupt, and in addition some errors may trigger either an fatal_macro_error or an\nfatal_check_error alert.", + "count": "NumErrorEntries", + "swaccess": "ro", + "hwaccess": "hwo", + "hwext": "true", + "cname": "AGENT", + "compact": "false", + "resval": 0, + "tags": [ + "excl:CsrAllTests:CsrExclCheck" + ], + "fields": [ + { + "bits": "2:0", + "enum": [ + { + "value": "0", + "name": "NO_ERROR", + "desc": "No error condition has occurred." + }, + { + "value": "1", + "name": "MACRO_ERROR", + "desc": "Returned if the OTP macro command was invalid or did not complete successfully\ndue to a macro malfunction.\nThis error should never occur during normal operation and is not recoverable.\nThis error triggers an fatal_macro_error alert." + }, + { + "value": "2", + "name": "MACRO_ECC_CORR_ERROR", + "desc": "A correctable ECC error has occured during an OTP read operation.\nThe corresponding controller automatically recovers from this error when\nissuing a new command." + }, + { + "value": "3", + "name": "MACRO_ECC_UNCORR_ERROR", + "desc": "An uncorrectable ECC error has occurred during an OTP read operation.\nThis error should never occur during normal operation and is not recoverable.\nIf this error is present this may be a sign that the device is malfunctioning.\nThis error triggers an fatal_macro_error alert." + }, + { + "value": "4", + "name": "MACRO_WRITE_BLANK_ERROR", + "desc": "This error is returned if a programming operation attempted to clear a bit that has previously been programmed to 1.\nThe corresponding controller automatically recovers from this error when issuing a new command.\n\nNote however that the affected OTP word may be left in an inconsistent state if this error occurs.\nThis can cause several issues when the word is accessed again (either as part of a regular read operation, as part of the readout at boot, or as part of a background check).\n\nIt is important that SW ensures that each word is only written once, since this can render the device useless." + }, + { + "value": "5", + "name": "ACCESS_ERROR", + "desc": "This error indicates that a locked memory region has been accessed.\nThe corresponding controller automatically recovers from this error when issuing a new command." + }, + { + "value": "6", + "name": "CHECK_FAIL_ERROR", + "desc": "An ECC, integrity or consistency mismatch has been detected in the buffer registers.\nThis error should never occur during normal operation and is not recoverable.\nThis error triggers an fatal_check_error alert." + }, + { + "value": "7", + "name": "FSM_STATE_ERROR", + "desc": "The FSM of the corresponding controller has reached an invalid state, or the FSM has\nbeen moved into a terminal error state due to an escalation action via lc_escalate_en_i.\nThis error should never occur during normal operation and is not recoverable.\nIf this error is present, this is a sign that the device has fallen victim to\nan invasive attack. This error triggers an fatal_check_error alert." + } + ] + } + ] + } + }, + { + "name": "DIRECT_ACCESS_REGWEN", + "desc": "Register write enable for all direct access interface registers.", + "swaccess": "rw0c", + "hwaccess": "hrw", + "hwext": "true", + "hwqe": "true", + "tags": [ + "excl:CsrNonInitTests:CsrExclCheck" + ], + "fields": [ + { + "bits": "0", + "desc": "This bit controls whether the DAI registers can be written.\nWrite 0 to it in order to clear the bit.\n\nNote that the hardware also modulates this bit and sets it to 0 temporarily\nduring an OTP operation such that the corresponding address and data registers\ncannot be modified while an operation is pending. The !!DAI_IDLE status bit\nwill also be set to 0 in such a case.", + "resval": 1 + } + ] + }, + { + "name": "DIRECT_ACCESS_CMD", + "desc": "Command register for direct accesses.", + "swaccess": "r0w1c", + "hwaccess": "hro", + "hwqe": "true", + "hwext": "true", + "resval": 0, + "regwen": "DIRECT_ACCESS_REGWEN", + "tags": [ + "excl:CsrNonInitTests:CsrExclWrite" + ], + "fields": [ + { + "bits": "0", + "name": "RD", + "desc": "Initiates a readout sequence that reads the location specified\nby !!DIRECT_ACCESS_ADDRESS. The command places the data read into\n!!DIRECT_ACCESS_RDATA_0 and !!DIRECT_ACCESS_RDATA_1 (for 64bit partitions)." + }, + { + "bits": "1", + "name": "WR", + "desc": "Initiates a programming sequence that writes the data in !!DIRECT_ACCESS_WDATA_0\nand !!DIRECT_ACCESS_WDATA_1 (for 64bit partitions) to the location specified by\n!!DIRECT_ACCESS_ADDRESS." + }, + { + "bits": "2", + "name": "DIGEST", + "desc": "Initiates the digest calculation and locking sequence for the partition specified by\n!!DIRECT_ACCESS_ADDRESS." + } + ] + }, + { + "name": "DIRECT_ACCESS_ADDRESS", + "desc": "Address register for direct accesses.", + "swaccess": "rw", + "hwaccess": "hro", + "hwqe": "false", + "resval": 0, + "regwen": "DIRECT_ACCESS_REGWEN", + "tags": [ + "excl:CsrNonInitTests:CsrExclCheck" + ], + "fields": [ + { + "bits": "OtpByteAddrWidth-1:0", + "desc": "This is the address for the OTP word to be read or written through\nthe direct access interface. Note that the address is aligned to the access size\ninternally, hence bits 1:0 are ignored for 32bit accesses, and bits 2:0 are ignored\nfor 64bit accesses.\n\nFor the digest calculation command, set this register to the partition base offset." + } + ] + }, + { + "multireg": { + "name": "DIRECT_ACCESS_WDATA", + "desc": "Write data for direct accesses.\nHardware automatically determines the access granule (32bit or 64bit) based on which\npartition is being written to.", + "count": "NumDaiWords", + "swaccess": "rw", + "hwaccess": "hro", + "hwqe": "false", + "regwen": "DIRECT_ACCESS_REGWEN", + "cname": "WORD", + "resval": 0, + "tags": [ + "excl:CsrAllTests:CsrExclCheck" + ], + "fields": [ + { + "bits": "31:0" + } + ] + } + }, + { + "multireg": { + "name": "DIRECT_ACCESS_RDATA", + "desc": "Read data for direct accesses.\nHardware automatically determines the access granule (32bit or 64bit) based on which\npartition is read from.", + "count": "NumDaiWords", + "swaccess": "ro", + "hwaccess": "hwo", + "hwext": "true", + "cname": "WORD", + "resval": 0, + "fields": [ + { + "bits": "31:0" + } + ] + } + }, + { + "name": "CHECK_TRIGGER_REGWEN", + "desc": "Register write enable for !!CHECK_TRIGGER.", + "swaccess": "rw0c", + "hwaccess": "none", + "fields": [ + { + "bits": "0", + "desc": "When cleared to 0, the !!CHECK_TRIGGER register cannot be written anymore.\nWrite 0 to clear this bit.", + "resval": 1 + } + ] + }, + { + "name": "CHECK_TRIGGER", + "desc": "Command register for direct accesses.", + "swaccess": "r0w1c", + "hwaccess": "hro", + "hwqe": "true", + "hwext": "true", + "resval": 0, + "regwen": "CHECK_TRIGGER_REGWEN", + "fields": [ + { + "bits": "0", + "name": "INTEGRITY", + "desc": "Writing 1 to this bit triggers an integrity check. SW should monitor !!STATUS.CHECK_PENDING\nand wait until the check has been completed. If there are any errors, those will be flagged\nin the !!STATUS and !!ERR_CODE registers, and via the interrupts and alerts." + }, + { + "bits": "1", + "name": "CONSISTENCY", + "desc": "Writing 1 to this bit triggers a consistency check. SW should monitor !!STATUS.CHECK_PENDING\nand wait until the check has been completed. If there are any errors, those will be flagged\nin the !!STATUS and !!ERR_CODE registers, and via interrupts and alerts." + } + ] + }, + { + "name": "CHECK_REGWEN", + "desc": "Register write enable for !!INTEGRITY_CHECK_PERIOD and !!CONSISTENCY_CHECK_PERIOD.", + "swaccess": "rw0c", + "hwaccess": "none", + "fields": [ + { + "bits": "0", + "desc": "When cleared to 0, !!INTEGRITY_CHECK_PERIOD and !!CONSISTENCY_CHECK_PERIOD registers cannot be written anymore.\nWrite 0 to clear this bit.", + "resval": 1 + } + ] + }, + { + "name": "CHECK_TIMEOUT", + "desc": "Timeout value for the integrity and consistency checks.", + "swaccess": "rw", + "hwaccess": "hro", + "regwen": "CHECK_REGWEN", + "tags": [ + "excl:CsrAllTests:CsrExclWrite" + ], + "fields": [ + { + "bits": "31:0", + "desc": "Timeout value in cycles for the for the integrity and consistency checks. If an integrity or consistency\ncheck does not complete within the timeout window, an error will be flagged in the !!STATUS register,\nan otp_error interrupt will be raised, and an fatal_check_error alert will be sent out. The timeout should\nbe set to a large value to stay on the safe side. The maximum check time can be upper bounded by the\nnumber of cycles it takes to readout, scramble and digest the entire OTP array. Since this amounts to\nroughly 25k cycles, it is recommended to set this value to at least 100'000 cycles in order to stay on the\nsafe side. A value of zero disables the timeout mechanism (default).", + "resval": 0 + } + ] + }, + { + "name": "INTEGRITY_CHECK_PERIOD", + "desc": "This value specifies the maximum period that can be generated pseudo-randomly.\nOnly applies to the HW_CFG* and SECRET* partitions once they are locked.", + "swaccess": "rw", + "hwaccess": "hro", + "regwen": "CHECK_REGWEN", + "fields": [ + { + "bits": "31:0", + "desc": "The pseudo-random period is generated using a 40bit LFSR internally, and this register defines\nthe bit mask to be applied to the LFSR output in order to limit its range. The value of this\nregister is left shifted by 8bits and the lower bits are set to 8'hFF in order to form the 40bit mask.\nA recommended value is 0x3_FFFF, corresponding to a maximum period of ~2.8s at 24MHz.\nA value of zero disables the timer (default). Note that a one-off check can always be triggered via\n!!CHECK_TRIGGER.INTEGRITY.", + "resval": "0" + } + ] + }, + { + "name": "CONSISTENCY_CHECK_PERIOD", + "desc": "This value specifies the maximum period that can be generated pseudo-randomly.\nThis applies to the LIFE_CYCLE partition and the HW_CFG* and SECRET* partitions once they are locked.", + "swaccess": "rw", + "hwaccess": "hro", + "regwen": "CHECK_REGWEN", + "fields": [ + { + "bits": "31:0", + "desc": "The pseudo-random period is generated using a 40bit LFSR internally, and this register defines\nthe bit mask to be applied to the LFSR output in order to limit its range. The value of this\nregister is left shifted by 8bits and the lower bits are set to 8'hFF in order to form the 40bit mask.\nA recommended value is 0x3FF_FFFF, corresponding to a maximum period of ~716s at 24MHz.\nA value of zero disables the timer (default). Note that a one-off check can always be triggered via\n!!CHECK_TRIGGER.CONSISTENCY.", + "resval": "0" + } + ] + }, + { + "name": "VENDOR_TEST_READ_LOCK", + "desc": "Runtime read lock for the VENDOR_TEST partition.", + "swaccess": "rw0c", + "hwaccess": "hro", + "regwen": "DIRECT_ACCESS_REGWEN", + "tags": [ + "excl:CsrNonInitTests:CsrExclWrite" + ], + "fields": [ + { + "bits": "0", + "desc": "When cleared to 0, read access to the VENDOR_TEST partition is locked.\nWrite 0 to clear this bit.", + "resval": 1 + } + ] + }, + { + "name": "CREATOR_SW_CFG_READ_LOCK", + "desc": "Runtime read lock for the CREATOR_SW_CFG partition.", + "swaccess": "rw0c", + "hwaccess": "hro", + "regwen": "DIRECT_ACCESS_REGWEN", + "tags": [ + "excl:CsrNonInitTests:CsrExclWrite" + ], + "fields": [ + { + "bits": "0", + "desc": "When cleared to 0, read access to the CREATOR_SW_CFG partition is locked.\nWrite 0 to clear this bit.", + "resval": 1 + } + ] + }, + { + "name": "OWNER_SW_CFG_READ_LOCK", + "desc": "Runtime read lock for the OWNER_SW_CFG partition.", + "swaccess": "rw0c", + "hwaccess": "hro", + "regwen": "DIRECT_ACCESS_REGWEN", + "tags": [ + "excl:CsrNonInitTests:CsrExclWrite" + ], + "fields": [ + { + "bits": "0", + "desc": "When cleared to 0, read access to the OWNER_SW_CFG partition is locked.\nWrite 0 to clear this bit.", + "resval": 1 + } + ] + }, + { + "name": "ROT_CREATOR_AUTH_CODESIGN_READ_LOCK", + "desc": "Runtime read lock for the ROT_CREATOR_AUTH_CODESIGN partition.", + "swaccess": "rw0c", + "hwaccess": "hro", + "regwen": "DIRECT_ACCESS_REGWEN", + "tags": [ + "excl:CsrNonInitTests:CsrExclWrite" + ], + "fields": [ + { + "bits": "0", + "desc": "When cleared to 0, read access to the ROT_CREATOR_AUTH_CODESIGN partition is locked.\nWrite 0 to clear this bit.", + "resval": 1 + } + ] + }, + { + "name": "ROT_CREATOR_AUTH_STATE_READ_LOCK", + "desc": "Runtime read lock for the ROT_CREATOR_AUTH_STATE partition.", + "swaccess": "rw0c", + "hwaccess": "hro", + "regwen": "DIRECT_ACCESS_REGWEN", + "tags": [ + "excl:CsrNonInitTests:CsrExclWrite" + ], + "fields": [ + { + "bits": "0", + "desc": "When cleared to 0, read access to the ROT_CREATOR_AUTH_STATE partition is locked.\nWrite 0 to clear this bit.", + "resval": 1 + } + ] + }, + { + "multireg": { + "name": "VENDOR_TEST_DIGEST", + "desc": "Integrity digest for the VENDOR_TEST partition.\nThe integrity digest is 0 by default. Software must write this\ndigest value via the direct access interface in order to lock the partition.\nAfter a reset, write access to the VENDOR_TEST partition is locked and\nthe digest becomes visible in this CSR.", + "count": "NumDigestWords", + "swaccess": "ro", + "hwaccess": "hwo", + "hwext": "true", + "cname": "WORD", + "resval": 0, + "tags": [ + "excl:CsrAllTests:CsrExclCheck" + ], + "fields": [ + { + "bits": "31:0" + } + ] + } + }, + { + "multireg": { + "name": "CREATOR_SW_CFG_DIGEST", + "desc": "Integrity digest for the CREATOR_SW_CFG partition.\nThe integrity digest is 0 by default. Software must write this\ndigest value via the direct access interface in order to lock the partition.\nAfter a reset, write access to the CREATOR_SW_CFG partition is locked and\nthe digest becomes visible in this CSR.", + "count": "NumDigestWords", + "swaccess": "ro", + "hwaccess": "hwo", + "hwext": "true", + "cname": "WORD", + "resval": 0, + "tags": [ + "excl:CsrAllTests:CsrExclCheck" + ], + "fields": [ + { + "bits": "31:0" + } + ] + } + }, + { + "multireg": { + "name": "OWNER_SW_CFG_DIGEST", + "desc": "Integrity digest for the OWNER_SW_CFG partition.\nThe integrity digest is 0 by default. Software must write this\ndigest value via the direct access interface in order to lock the partition.\nAfter a reset, write access to the OWNER_SW_CFG partition is locked and\nthe digest becomes visible in this CSR.", + "count": "NumDigestWords", + "swaccess": "ro", + "hwaccess": "hwo", + "hwext": "true", + "cname": "WORD", + "resval": 0, + "tags": [ + "excl:CsrAllTests:CsrExclCheck" + ], + "fields": [ + { + "bits": "31:0" + } + ] + } + }, + { + "multireg": { + "name": "ROT_CREATOR_AUTH_CODESIGN_DIGEST", + "desc": "Integrity digest for the ROT_CREATOR_AUTH_CODESIGN partition.\nThe integrity digest is 0 by default. Software must write this\ndigest value via the direct access interface in order to lock the partition.\nAfter a reset, write access to the ROT_CREATOR_AUTH_CODESIGN partition is locked and\nthe digest becomes visible in this CSR.", + "count": "NumDigestWords", + "swaccess": "ro", + "hwaccess": "hwo", + "hwext": "true", + "cname": "WORD", + "resval": 0, + "tags": [ + "excl:CsrAllTests:CsrExclCheck" + ], + "fields": [ + { + "bits": "31:0" + } + ] + } + }, + { + "multireg": { + "name": "ROT_CREATOR_AUTH_STATE_DIGEST", + "desc": "Integrity digest for the ROT_CREATOR_AUTH_STATE partition.\nThe integrity digest is 0 by default. Software must write this\ndigest value via the direct access interface in order to lock the partition.\nAfter a reset, write access to the ROT_CREATOR_AUTH_STATE partition is locked and\nthe digest becomes visible in this CSR.", + "count": "NumDigestWords", + "swaccess": "ro", + "hwaccess": "hwo", + "hwext": "true", + "cname": "WORD", + "resval": 0, + "tags": [ + "excl:CsrAllTests:CsrExclCheck" + ], + "fields": [ + { + "bits": "31:0" + } + ] + } + }, + { + "multireg": { + "name": "HW_CFG0_DIGEST", + "desc": "Integrity digest for the HW_CFG0 partition.\nThe integrity digest is 0 by default. The digest calculation can be triggered via the !!DIRECT_ACCESS_CMD.\nAfter a reset, the digest then becomes visible in this CSR, and the corresponding partition becomes write-locked.", + "count": "NumDigestWords", + "swaccess": "ro", + "hwaccess": "hwo", + "hwext": "true", + "cname": "WORD", + "resval": 0, + "tags": [ + "excl:CsrAllTests:CsrExclCheck" + ], + "fields": [ + { + "bits": "31:0" + } + ] + } + }, + { + "multireg": { + "name": "HW_CFG1_DIGEST", + "desc": "Integrity digest for the HW_CFG1 partition.\nThe integrity digest is 0 by default. The digest calculation can be triggered via the !!DIRECT_ACCESS_CMD.\nAfter a reset, the digest then becomes visible in this CSR, and the corresponding partition becomes write-locked.", + "count": "NumDigestWords", + "swaccess": "ro", + "hwaccess": "hwo", + "hwext": "true", + "cname": "WORD", + "resval": 0, + "tags": [ + "excl:CsrAllTests:CsrExclCheck" + ], + "fields": [ + { + "bits": "31:0" + } + ] + } + }, + { + "multireg": { + "name": "SECRET0_DIGEST", + "desc": "Integrity digest for the SECRET0 partition.\nThe integrity digest is 0 by default. The digest calculation can be triggered via the !!DIRECT_ACCESS_CMD.\nAfter a reset, the digest then becomes visible in this CSR, and the corresponding partition becomes write-locked.", + "count": "NumDigestWords", + "swaccess": "ro", + "hwaccess": "hwo", + "hwext": "true", + "cname": "WORD", + "resval": 0, + "tags": [ + "excl:CsrAllTests:CsrExclCheck" + ], + "fields": [ + { + "bits": "31:0" + } + ] + } + }, + { + "multireg": { + "name": "SECRET1_DIGEST", + "desc": "Integrity digest for the SECRET1 partition.\nThe integrity digest is 0 by default. The digest calculation can be triggered via the !!DIRECT_ACCESS_CMD.\nAfter a reset, the digest then becomes visible in this CSR, and the corresponding partition becomes write-locked.", + "count": "NumDigestWords", + "swaccess": "ro", + "hwaccess": "hwo", + "hwext": "true", + "cname": "WORD", + "resval": 0, + "tags": [ + "excl:CsrAllTests:CsrExclCheck" + ], + "fields": [ + { + "bits": "31:0" + } + ] + } + }, + { + "multireg": { + "name": "SECRET2_DIGEST", + "desc": "Integrity digest for the SECRET2 partition.\nThe integrity digest is 0 by default. The digest calculation can be triggered via the !!DIRECT_ACCESS_CMD.\nAfter a reset, the digest then becomes visible in this CSR, and the corresponding partition becomes write-locked.", + "count": "NumDigestWords", + "swaccess": "ro", + "hwaccess": "hwo", + "hwext": "true", + "cname": "WORD", + "resval": 0, + "tags": [ + "excl:CsrAllTests:CsrExclCheck" + ], + "fields": [ + { + "bits": "31:0" + } + ] + } + }, + { + "skipto": "0x800" + }, + { + "window": { + "name": "SW_CFG_WINDOW", + "items": "NumSwCfgWindowWords", + "swaccess": "ro", + "desc": "Any read to this window directly maps to the corresponding offset in the creator and owner software\nconfig partitions, and triggers an OTP readout of the bytes requested. Note that the transaction\nwill block until OTP readout has completed." + } + } + ], + "prim": [ + { + "name": "CSR0", + "desc": "", + "swaccess": "rw", + "hwaccess": "hro", + "hwext": "false", + "hwqe": "false", + "fields": [ + { + "bits": "0", + "name": "field0", + "desc": "", + "resval": "0x0" + }, + { + "bits": "1", + "name": "field1", + "desc": "", + "resval": "0x0" + }, + { + "bits": "2", + "name": "field2", + "desc": "", + "resval": "0x0" + }, + { + "bits": "13:4", + "name": "field3", + "desc": "", + "resval": "0x0" + }, + { + "bits": "26:16", + "name": "field4", + "desc": "", + "resval": "0x0" + } + ] + }, + { + "name": "CSR1", + "desc": "", + "swaccess": "rw", + "hwaccess": "hro", + "hwext": "false", + "hwqe": "false", + "fields": [ + { + "bits": "6:0", + "name": "field0", + "desc": "", + "resval": "0x0" + }, + { + "bits": "7:7", + "name": "field1", + "desc": "", + "resval": "0x0" + }, + { + "bits": "14:8", + "name": "field2", + "desc": "", + "resval": "0x0" + }, + { + "bits": "15:15", + "name": "field3", + "desc": "", + "resval": "0x0" + }, + { + "bits": "31:16", + "name": "field4", + "desc": "", + "resval": "0x0" + } + ] + }, + { + "name": "CSR2", + "desc": "", + "swaccess": "rw", + "hwaccess": "hro", + "hwext": "false", + "hwqe": "false", + "fields": [ + { + "bits": "0", + "name": "field0", + "desc": "", + "resval": "0x0" + } + ] + }, + { + "name": "CSR3", + "desc": "", + "swaccess": "rw", + "hwaccess": "hrw", + "hwext": "false", + "hwqe": "false", + "fields": [ + { + "bits": "2:0", + "name": "field0", + "desc": "", + "swaccess": "rw1c", + "resval": "0x0" + }, + { + "bits": "13:4", + "name": "field1", + "desc": "", + "swaccess": "rw1c", + "resval": "0x0" + }, + { + "bits": "16", + "name": "field2", + "desc": "", + "swaccess": "rw1c", + "resval": "0x0" + }, + { + "bits": "17", + "name": "field3", + "desc": "", + "swaccess": "ro", + "resval": "0x0" + }, + { + "bits": "18", + "name": "field4", + "desc": "", + "swaccess": "ro", + "resval": "0x0" + }, + { + "bits": "19", + "name": "field5", + "desc": "", + "swaccess": "ro", + "resval": "0x0" + }, + { + "bits": "20", + "name": "field6", + "desc": "", + "swaccess": "ro", + "resval": "0x0" + }, + { + "bits": "21", + "name": "field7", + "desc": "", + "swaccess": "ro", + "resval": "0x0" + }, + { + "bits": "22", + "name": "field8", + "desc": "", + "swaccess": "ro", + "resval": "0x0" + } + ] + }, + { + "name": "CSR4", + "desc": "", + "swaccess": "rw", + "hwaccess": "hro", + "hwext": "false", + "hwqe": "false", + "fields": [ + { + "bits": "9:0", + "name": "field0", + "desc": "", + "resval": "0x0" + }, + { + "bits": "12", + "name": "field1", + "desc": "", + "resval": "0x0" + }, + { + "bits": "13", + "name": "field2", + "desc": "", + "resval": "0x0" + }, + { + "bits": "14", + "name": "field3", + "desc": "", + "resval": "0x0" + } + ] + }, + { + "name": "CSR5", + "desc": "", + "swaccess": "rw", + "hwaccess": "hrw", + "hwext": "false", + "hwqe": "false", + "fields": [ + { + "bits": "5:0", + "name": "field0", + "desc": "", + "swaccess": "rw", + "resval": "0x0" + }, + { + "bits": "7:6", + "name": "field1", + "desc": "", + "swaccess": "rw", + "resval": "0x0" + }, + { + "bits": "8", + "name": "field2", + "desc": "", + "swaccess": "ro", + "resval": "0x0" + }, + { + "bits": "11:9", + "name": "field3", + "desc": "", + "swaccess": "ro", + "resval": "0x0" + }, + { + "bits": "12", + "name": "field4", + "desc": "", + "swaccess": "ro", + "resval": "0x0" + }, + { + "bits": "13", + "name": "field5", + "desc": "", + "swaccess": "ro", + "resval": "0x0" + }, + { + "bits": "31:16", + "name": "field6", + "desc": "", + "swaccess": "rw", + "resval": "0x0" + } + ] + }, + { + "name": "CSR6", + "desc": "", + "swaccess": "rw", + "hwaccess": "hro", + "hwext": "false", + "hwqe": "false", + "fields": [ + { + "bits": "9:0", + "name": "field0", + "desc": "", + "resval": "0x0" + }, + { + "bits": "11", + "name": "field1", + "desc": "", + "swaccess": "rw", + "resval": "0x0" + }, + { + "bits": "12", + "name": "field2", + "desc": "", + "swaccess": "rw", + "resval": "0x0" + }, + { + "bits": "31:16", + "name": "field3", + "desc": "", + "resval": "0x0" + } + ] + }, + { + "name": "CSR7", + "desc": "", + "swaccess": "ro", + "hwaccess": "hrw", + "hwext": "false", + "hwqe": "false", + "fields": [ + { + "bits": "5:0", + "name": "field0", + "desc": "", + "swaccess": "ro", + "resval": "0x0" + }, + { + "bits": "10:8", + "name": "field1", + "desc": "", + "swaccess": "ro", + "resval": "0x0" + }, + { + "bits": "14", + "name": "field2", + "desc": "", + "swaccess": "ro", + "resval": "0x0" + }, + { + "bits": "15", + "name": "field3", + "desc": "", + "swaccess": "ro", + "resval": "0x0" + } + ] + } + ] + } +} diff --git a/src/fuse_ctrl/data/otp_ctrl_part_pkg.sv.tpl b/src/fuse_ctrl/data/otp_ctrl_part_pkg.sv.tpl new file mode 100755 index 0000000..6c8e015 --- /dev/null +++ b/src/fuse_ctrl/data/otp_ctrl_part_pkg.sv.tpl @@ -0,0 +1,353 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Package partition metadata. +// +${gen_comment} +<% +from topgen.lib import Name +%>\ +package otp_ctrl_part_pkg; + + import prim_util_pkg::vbits; + import otp_ctrl_reg_pkg::*; + import otp_ctrl_pkg::*; + + //////////////////////////////////// + // Scrambling Constants and Types // + //////////////////////////////////// + + parameter int NumScrmblKeys = ${len(otp_mmap.config["scrambling"]["keys"])}; + parameter int NumDigestSets = ${len(otp_mmap.config["scrambling"]["digests"])}; + + parameter int ScrmblKeySelWidth = vbits(NumScrmblKeys); + parameter int DigestSetSelWidth = vbits(NumDigestSets); + parameter int ConstSelWidth = (ScrmblKeySelWidth > DigestSetSelWidth) ? + ScrmblKeySelWidth : + DigestSetSelWidth; + + typedef enum logic [ConstSelWidth-1:0] { + StandardMode, + ChainedMode + } digest_mode_e; + + typedef logic [NumScrmblKeys-1:0][ScrmblKeyWidth-1:0] key_array_t; + typedef logic [NumDigestSets-1:0][ScrmblKeyWidth-1:0] digest_const_array_t; + typedef logic [NumDigestSets-1:0][ScrmblBlockWidth-1:0] digest_iv_array_t; + + typedef enum logic [ConstSelWidth-1:0] { +% for key in otp_mmap.config["scrambling"]["keys"]: + ${key["name"]}${"" if loop.last else ","} +% endfor + } key_sel_e; + + typedef enum logic [ConstSelWidth-1:0] { +% for dig in otp_mmap.config["scrambling"]["digests"]: + ${dig["name"]}${"" if loop.last else ","} +% endfor + } digest_sel_e; + + // SEC_CM: SECRET.MEM.SCRAMBLE + parameter key_array_t RndCnstKey = { +% for key in otp_mmap.config["scrambling"]["keys"][::-1]: + ${"{0:}'h{1:0X}".format(otp_mmap.config["scrambling"]["key_size"] * 8, key["value"])}${"" if loop.last else ","} +% endfor + }; + + // SEC_CM: PART.MEM.DIGEST + // Note: digest set 0 is used for computing the partition digests. Constants at + // higher indices are used to compute the scrambling keys. + parameter digest_const_array_t RndCnstDigestConst = { +% for dig in otp_mmap.config["scrambling"]["digests"][::-1]: + ${"{0:}'h{1:0X}".format(otp_mmap.config["scrambling"]["cnst_size"] * 8, dig["cnst_value"])}${"" if loop.last else ","} +% endfor + }; + + parameter digest_iv_array_t RndCnstDigestIV = { +% for dig in otp_mmap.config["scrambling"]["digests"][::-1]: + ${"{0:}'h{1:0X}".format(otp_mmap.config["scrambling"]["iv_size"] * 8, dig["iv_value"])}${"" if loop.last else ","} +% endfor + }; + + + ///////////////////////////////////// + // Typedefs for Partition Metadata // + ///////////////////////////////////// + + typedef enum logic [1:0] { + Unbuffered, + Buffered, + LifeCycle + } part_variant_e; + + typedef struct packed { + part_variant_e variant; + // Offset and size within the OTP array, in Bytes. + logic [OtpByteAddrWidth-1:0] offset; + logic [OtpByteAddrWidth-1:0] size; + // Key index to use for scrambling. + key_sel_e key_sel; + // Attributes + logic secret; // Whether the partition is secret (and hence scrambled) + logic sw_digest; // Whether the partition has a software digest + logic hw_digest; // Whether the partition has a hardware digest + logic write_lock; // Whether the partition is write lockable (via digest) + logic read_lock; // Whether the partition is read lockable (via digest) + logic integrity; // Whether the partition is integrity protected + logic iskeymgr_creator; // Whether the partition has any creator key material + logic iskeymgr_owner; // Whether the partition has any owner key material + } part_info_t; + + parameter part_info_t PartInfoDefault = '{ + variant: Unbuffered, + offset: '0, + size: OtpByteAddrWidth'('hFF), + key_sel: key_sel_e'('0), + secret: 1'b0, + sw_digest: 1'b0, + hw_digest: 1'b0, + write_lock: 1'b0, + read_lock: 1'b0, + integrity: 1'b0, + iskeymgr_creator: 1'b0, + iskeymgr_owner: 1'b0 + }; + + //////////////////////// + // Partition Metadata // + //////////////////////// + + localparam part_info_t PartInfo [NumPart] = '{ +% for part in otp_mmap.config["partitions"]: + // ${part["name"]} + '{ + variant: ${part["variant"]}, + offset: ${otp_mmap.config["otp"]["byte_addr_width"]}'d${part["offset"]}, + size: ${part["size"]}, + key_sel: ${part["key_sel"] if part["key_sel"] != "NoKey" else "key_sel_e'('0)"}, + secret: 1'b${"1" if part["secret"] else "0"}, + sw_digest: 1'b${"1" if part["sw_digest"] else "0"}, + hw_digest: 1'b${"1" if part["hw_digest"] else "0"}, + write_lock: 1'b${"1" if part["write_lock"].lower() == "digest" else "0"}, + read_lock: 1'b${"1" if part["read_lock"].lower() == "digest" else "0"}, + integrity: 1'b${"1" if part["integrity"] else "0"}, + iskeymgr_creator: 1'b${"1" if part["iskeymgr_creator"] else "0"}, + iskeymgr_owner: 1'b${"1" if part["iskeymgr_owner"] else "0"} + }${"" if loop.last else ","} +% endfor + }; + + typedef enum { +% for part in otp_mmap.config["partitions"]: + ${Name.from_snake_case(part["name"]).as_camel_case()}Idx, +% endfor + // These are not "real partitions", but in terms of implementation it is convenient to + // add these at the end of certain arrays. + DaiIdx, + LciIdx, + KdiIdx, + // Number of agents is the last idx+1. + NumAgentsIdx + } part_idx_e; + + parameter int NumAgents = int'(NumAgentsIdx); + + // Breakout types for easier access of individual items. +% for part in otp_mmap.config["partitions"]: + % if part["bkout_type"]: + typedef struct packed {<% offset = part['offset'] + part['size'] %> + % for item in part["items"][::-1]: + % if offset != item['offset'] + item['size']: + logic [${(offset - item['size'] - item['offset']) * 8 - 1}:0] unallocated;<% offset = item['offset'] + item['size'] %> + % endif +<% + if item['ismubi']: + item_type = 'prim_mubi_pkg::mubi' + str(item["size"]*8) + '_t' + else: + item_type = 'logic [' + str(int(item["size"])*8-1) + ':0]' +%>\ + ${item_type} ${item["name"].lower()};<% offset -= item['size'] %> + % endfor + } otp_${part["name"].lower()}_data_t; + + // default value used for intermodule + parameter otp_${part["name"].lower()}_data_t OTP_${part["name"].upper()}_DATA_DEFAULT = '{<% offset = part['offset'] + part['size'] %> + % for k, item in enumerate(part["items"][::-1]): + % if offset != item['offset'] + item['size']: + unallocated: ${"{}'h{:0X}".format((offset - item['size'] - item['offset']) * 8, 0)}<% offset = item['offset'] + item['size'] %>, + % endif +<% + if item['ismubi']: + item_cast_pre = "prim_mubi_pkg::mubi" + str(item["size"]*8) + "_t'(" + item_cast_post = ")" + else: + item_cast_pre = "" + item_cast_post = "" +%>\ + ${item["name"].lower()}: ${item_cast_pre}${"{}'h{:0X}".format(item["size"] * 8, item["inv_default"])}${item_cast_post}${"," if k < len(part["items"])-1 else ""}<% offset -= item['size'] %> + % endfor + }; + % endif +% endfor + typedef struct packed { + // This reuses the same encoding as the life cycle signals for indicating valid status. + lc_ctrl_pkg::lc_tx_t valid; +% for part in otp_mmap.config["partitions"][::-1]: + % if part["bkout_type"]: + otp_${part["name"].lower()}_data_t ${part["name"].lower()}_data; + % endif +% endfor + } otp_broadcast_t; + + // default value for intermodule +<% + k = 0 + num_bkout = 0 + for part in otp_mmap.config["partitions"]: + if part["bkout_type"]: + num_bkout += 1 +%>\ + parameter otp_broadcast_t OTP_BROADCAST_DEFAULT = '{ + valid: lc_ctrl_pkg::Off, +% for part in otp_mmap.config["partitions"][::-1]: + % if part["bkout_type"]: + ${part["name"].lower()}_data: OTP_${part["name"].upper()}_DATA_DEFAULT${"" if k == num_bkout-1 else ","} +<% k+=1 %>\ + % endif +% endfor + }; + +<% offset = int(otp_mmap.config["partitions"][-1]["offset"]) + int(otp_mmap.config["partitions"][-1]["size"]) %> + // OTP invalid partition default for buffered partitions. + parameter logic [${offset * 8 - 1}:0] PartInvDefault = ${offset * 8}'({ + % for k, part in enumerate(otp_mmap.config["partitions"][::-1]): + ${int(part["size"])*8}'({ + % for item in part["items"][::-1]: + % if offset != item['offset'] + item['size']: + ${"{}'h{:0X}".format((offset - item['size'] - item['offset']) * 8, 0)}, // unallocated space<% offset = item['offset'] + item['size'] %> + % endif + ${"{}'h{:0X}".format(item["size"] * 8, item["inv_default"])}${("\n })," if k < len(otp_mmap.config["partitions"])-1 else "\n })});") if loop.last else ","}<% offset -= item['size'] %> + % endfor + % endfor + + /////////////////////////////////////////////// + // Parameterized Assignment Helper Functions // + /////////////////////////////////////////////// + + function automatic otp_ctrl_core_hw2reg_t named_reg_assign( + logic [NumPart-1:0][ScrmblBlockWidth-1:0] part_digest); + otp_ctrl_core_hw2reg_t hw2reg; + logic unused_sigs; + unused_sigs = ^part_digest; + hw2reg = '0; +% for k, part in enumerate(otp_mmap.config["partitions"]): +<% + part_name = Name.from_snake_case(part["name"]) + part_name_camel = part_name.as_camel_case() +%>\ + % if part["sw_digest"] or part["hw_digest"]: + hw2reg.${part["name"].lower()}_digest = part_digest[${part_name_camel}Idx]; + % endif +% endfor + return hw2reg; + endfunction : named_reg_assign + + function automatic part_access_t [NumPart-1:0] named_part_access_pre( + otp_ctrl_core_reg2hw_t reg2hw); + part_access_t [NumPart-1:0] part_access_pre; + logic unused_sigs; + unused_sigs = ^reg2hw; + // Default (this will be overridden by partition-internal settings). + part_access_pre = {{32'(2*NumPart)}{prim_mubi_pkg::MuBi8False}}; + // Note: these could be made a MuBi CSRs in the future. + // The main thing that is missing right now is proper support for W0C. +% for k, part in enumerate(otp_mmap.config["partitions"]): + % if part["read_lock"] == "CSR": + // ${part["name"]} + if (!reg2hw.${part["name"].lower()}_read_lock) begin +<% part_name = Name.from_snake_case(part["name"]) %>\ + part_access_pre[${part_name.as_camel_case()}Idx].read_lock = prim_mubi_pkg::MuBi8True; + end + % endif +% endfor + return part_access_pre; + endfunction : named_part_access_pre + + function automatic otp_broadcast_t named_broadcast_assign( + logic [NumPart-1:0] part_init_done, + logic [$bits(PartInvDefault)/8-1:0][7:0] part_buf_data); + otp_broadcast_t otp_broadcast; + logic valid, unused; + unused = 1'b0; + valid = 1'b1; +% for part in otp_mmap.config["partitions"]: + // ${part["name"]} +<% + part_name = Name.from_snake_case(part["name"]) + part_name_camel = part_name.as_camel_case() +%>\ + % if part["bkout_type"]: + valid &= part_init_done[${part_name_camel}Idx]; + otp_broadcast.${part["name"].lower()}_data = otp_${part["name"].lower()}_data_t'(part_buf_data[${part_name_camel}Offset +: ${part_name_camel}Size]); + % else: + unused ^= ^{part_init_done[${part_name_camel}Idx], + part_buf_data[${part_name_camel}Offset +: ${part_name_camel}Size]}; + % endif +% endfor + otp_broadcast.valid = lc_ctrl_pkg::lc_tx_bool_to_lc_tx(valid); + return otp_broadcast; + endfunction : named_broadcast_assign + + function automatic otp_keymgr_key_t named_keymgr_key_assign( + logic [NumPart-1:0][ScrmblBlockWidth-1:0] part_digest, + logic [$bits(PartInvDefault)/8-1:0][7:0] part_buf_data, + lc_ctrl_pkg::lc_tx_t lc_seed_hw_rd_en); + otp_keymgr_key_t otp_keymgr_key; + logic valid, unused; + unused = 1'b0; + // For now we use a fixed struct type here so that the + // interface to the keymgr remains stable. The type contains + // a superset of all options, so we have to initialize it to '0 here. + otp_keymgr_key = '0; +% for part in otp_mmap.config["partitions"]: + // ${part["name"]} +<% + part_name = Name.from_snake_case(part["name"]) + part_name_camel = part_name.as_camel_case() +%>\ + % if part["iskeymgr_creator"] or part["iskeymgr_owner"]: + valid = (part_digest[${part_name_camel}Idx] != 0); + % for item in part["items"]: +<% + item_name = Name.from_snake_case(item["name"]) + item_name_camel = item_name.as_camel_case() +%>\ + % if item["iskeymgr_creator"] or item["iskeymgr_owner"]: + otp_keymgr_key.${item["name"].lower()}_valid = valid; + if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_seed_hw_rd_en)) begin + otp_keymgr_key.${item["name"].lower()} = + part_buf_data[${item_name_camel}Offset +: ${item_name_camel}Size]; + end else begin + otp_keymgr_key.${item["name"].lower()} = + PartInvDefault[${item_name_camel}Offset*8 +: ${item_name_camel}Size*8]; + end + % else: + % if not item["isdigest"]: + unused ^= ^part_buf_data[${item_name_camel}Offset +: ${item_name_camel}Size]; + % endif + % endif + % endfor + // This is not used since we consume the + // ungated digest values from the part_digest array. + unused ^= ^part_buf_data[${part_name_camel}DigestOffset +: ${part_name_camel}DigestSize]; + % else: + unused ^= ^{part_digest[${part_name_camel}Idx], + part_buf_data[${part_name_camel}Offset +: ${part_name_camel}Size]}; + % endif +% endfor + unused ^= valid; + return otp_keymgr_key; + endfunction : named_keymgr_key_assign + +endpackage : otp_ctrl_part_pkg diff --git a/src/fuse_ctrl/data/otp_ctrl_scoreboard.sv.tpl b/src/fuse_ctrl/data/otp_ctrl_scoreboard.sv.tpl new file mode 100755 index 0000000..9e50e3f --- /dev/null +++ b/src/fuse_ctrl/data/otp_ctrl_scoreboard.sv.tpl @@ -0,0 +1,1473 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +${gen_comment} +<% +from topgen.lib import Name + +read_locked_csr_parts = [part for part in otp_mmap.config["partitions"] if + part["read_lock"] == "CSR"] +write_locked_digest_parts = [part for part in otp_mmap.config["partitions"] if + part["write_lock"] == "Digest"] +buf_parts_without_lc = [part for part in otp_mmap.config["partitions"] if + part["variant"] == "Buffered"] +secret_parts = [part for part in otp_mmap.config["partitions"] if + part["secret"]] +## Partitions + LCI + DAI +num_err_code = len(otp_mmap.config["partitions"]) + 2 +%>\ +class otp_ctrl_scoreboard #(type CFG_T = otp_ctrl_env_cfg) + extends cip_base_scoreboard #( + .CFG_T(CFG_T), + .RAL_T(otp_ctrl_core_reg_block), + .COV_T(otp_ctrl_env_cov) + ); + `uvm_component_param_utils(otp_ctrl_scoreboard #(CFG_T)) + + // local variables + bit [TL_DW-1:0] otp_a [OTP_ARRAY_SIZE]; + + // lc_state and lc_cnt that stored in OTP + bit [LC_PROG_DATA_SIZE-1:0] otp_lc_data; + bit [EDN_BUS_WIDTH-1:0] edn_data_q[$]; + + // This flag is used when reset is issued during otp dai write access. + bit dai_wr_ip; + int dai_digest_ip = LifeCycleIdx; // Default to LC as it does not have digest. + bit ignore_digest_chk = 0; + + // This bit is used for DAI interface to mark if the read access is valid. + bit dai_read_valid; + + // This captures the regwen state as configured by the SW side (i.e. without HW modulation + // with the idle signal overlaid). + bit direct_access_regwen_state = 1; + + // ICEBOX(#17798): currently scb will skip checking the readout value if the ECC error is + // uncorrectable. Because if the error is uncorrectable, current scb does not track all the + // backdoor injected values. + // This issue proposes to track the otp_memory_array in mem_bkdr_if and once backdoor inject any + // value, mem_bkdr_if will update its otp_memory_array. + bit check_dai_rd_data = 1; + + // Status related variables + bit under_chk, under_dai_access; + bit [TL_DW-1:0] exp_status, status_mask; + + otp_alert_e exp_alert = OtpNoAlert; + + // TLM agent fifos + uvm_tlm_analysis_fifo #(push_pull_item#(.DeviceDataWidth(SRAM_DATA_SIZE))) + sram_fifos[NumSramKeyReqSlots]; + uvm_tlm_analysis_fifo #(push_pull_item#(.DeviceDataWidth(OTBN_DATA_SIZE))) otbn_fifo; + uvm_tlm_analysis_fifo #(push_pull_item#(.DeviceDataWidth(FLASH_DATA_SIZE))) flash_addr_fifo; + uvm_tlm_analysis_fifo #(push_pull_item#(.DeviceDataWidth(FLASH_DATA_SIZE))) flash_data_fifo; + uvm_tlm_analysis_fifo #(push_pull_item#(.DeviceDataWidth(1), .HostDataWidth(LC_PROG_DATA_SIZE))) + lc_prog_fifo; + + // local queues to hold incoming packets pending comparison + + `uvm_component_new + + function void build_phase(uvm_phase phase); + super.build_phase(phase); + for (int i = 0; i < NumSramKeyReqSlots; i++) begin + sram_fifos[i] = new($sformatf("sram_fifos[%0d]", i), this); + end + otbn_fifo = new("otbn_fifo", this); + flash_addr_fifo = new("flash_addr_fifo", this); + flash_data_fifo = new("flash_data_fifo", this); + lc_prog_fifo = new("lc_prog_fifo", this); + endfunction + + function void connect_phase(uvm_phase phase); + super.connect_phase(phase); + endfunction + + task run_phase(uvm_phase phase); + super.run_phase(phase); + fork + process_wipe_mem(); + process_otp_power_up(); + process_lc_esc(); + process_lc_prog_req(); + process_edn_req(); + check_otbn_rsp(); + check_flash_rsps(); + check_sram_rsps(); + recover_lc_prog_req(); + join_none + endtask + + // Once sequence uses backdoor method to clear memory, this task resets internal otp_a and + // resets `cfg.backdoor_clear_mem` to 0. + virtual task process_wipe_mem(); + forever begin + @(posedge cfg.backdoor_clear_mem) begin + bit [SCRAMBLE_DATA_SIZE-1:0] data; + otp_a = '{default:0}; + otp_lc_data = '{default:0}; +% for part in secret_parts: +<% + part_name = Name.from_snake_case(part["name"]) + part_name_camel = part_name.as_camel_case() +%>\ + // secret partitions have been scrambled before writing to OTP. + // here calculate the pre-srambled raw data when clearing internal OTP to all 0s. + data = descramble_data(0, ${part_name_camel}Idx); + for (int i = ${part_name_camel}Offset / TL_SIZE; + i <= ${part_name_camel}DigestOffset / TL_SIZE - 1; + i++) begin + otp_a[i] = ((i - ${part_name_camel}Offset / TL_SIZE) % 2) ? + data[SCRAMBLE_DATA_SIZE-1:TL_DW] : data[TL_DW-1:0]; + end +% endfor + `uvm_info(`gfn, "clear internal memory and digest", UVM_HIGH) + cfg.backdoor_clear_mem = 0; + dai_wr_ip = 0; + dai_digest_ip = LifeCycleIdx; + end + end + endtask + + // This task process the following logic in during otp_power_up: + // 1. After reset deasserted, otp access is locked until pwr_otp_done_o is set + // 2. After reset deasserted, if power otp_init request is on, and if testbench uses backdoor to + // clear OTP memory to all zeros, clear all digests and re-calculate secret partitions + virtual task process_otp_power_up(); + forever begin + wait (cfg.en_scb); + @(posedge cfg.otp_ctrl_vif.pwr_otp_done_o || cfg.under_reset || + cfg.otp_ctrl_vif.alert_reqs) begin + if (!cfg.under_reset && !cfg.otp_ctrl_vif.alert_reqs && cfg.en_scb) begin + otp_ctrl_part_pkg::otp_hw_cfg0_data_t exp_hw_cfg0_data; + otp_ctrl_part_pkg::otp_hw_cfg1_data_t exp_hw_cfg1_data; + otp_ctrl_pkg::otp_keymgr_key_t exp_keymgr_data; + otp_ctrl_pkg::otp_lc_data_t exp_lc_data; + bit [otp_ctrl_pkg::KeyMgrKeyWidth-1:0] exp_keymgr_key0, exp_keymgr_key1; + + if (PartInfo[dai_digest_ip].sw_digest || PartInfo[dai_digest_ip].hw_digest) begin + bit [TL_DW-1:0] otp_addr = PART_OTP_DIGEST_ADDRS[dai_digest_ip]; + otp_a[otp_addr] = cfg.mem_bkdr_util_h.read32(otp_addr << 2); + otp_a[otp_addr+1] = cfg.mem_bkdr_util_h.read32((otp_addr << 2) + 4); + dai_digest_ip = LifeCycleIdx; + end + predict_digest_csrs(); + + if (cfg.otp_ctrl_vif.under_error_states() == 0) begin + // Dai access is unlocked because the power init is done + void'(ral.direct_access_regwen.predict(direct_access_regwen_state)); + + // Dai idle is set because the otp init is done + exp_status[OtpDaiIdleIdx] = 1; + end + + // Hwcfg_o gets data from OTP HW cfg partition + exp_hw_cfg0_data = cfg.otp_ctrl_vif.under_error_states() ? + otp_ctrl_part_pkg::PartInvDefault[HwCfg0Offset*8 +: HwCfg0Size*8] : + otp_hw_cfg0_data_t'({<<32 {otp_a[HwCfg0Offset/4 +: HwCfg0Size/4]}}); + `DV_CHECK_EQ(cfg.otp_ctrl_vif.otp_broadcast_o.valid, lc_ctrl_pkg::On) + `DV_CHECK_EQ(cfg.otp_ctrl_vif.otp_broadcast_o.hw_cfg0_data, exp_hw_cfg0_data) + + // Hwcfg_o gets data from OTP HW cfg partition + exp_hw_cfg1_data = cfg.otp_ctrl_vif.under_error_states() ? + otp_ctrl_part_pkg::PartInvDefault[HwCfg1Offset*8 +: HwCfg1Size*8] : + otp_hw_cfg1_data_t'({<<32 {otp_a[HwCfg1Offset/4 +: HwCfg1Size/4]}}); + `DV_CHECK_EQ(cfg.otp_ctrl_vif.otp_broadcast_o.valid, lc_ctrl_pkg::On) + `DV_CHECK_EQ(cfg.otp_ctrl_vif.otp_broadcast_o.hw_cfg1_data, exp_hw_cfg1_data) + + if (!cfg.otp_ctrl_vif.under_error_states()) begin + // ---------------------- Check lc_data_o output ----------------------------------- + // Because initialization was succesful, the valid should be set and error should be + // reset. + exp_lc_data.valid = 1; + exp_lc_data.error = 0; + + // Secrets and tokens valid signals are depend on whether secret partitions are + // locked. + exp_lc_data.secrets_valid = get_otp_digest_val(Secret2Idx) ? On : Off; + exp_lc_data.test_tokens_valid = get_otp_digest_val(Secret0Idx) ? On : Off; + exp_lc_data.rma_token_valid = get_otp_digest_val(Secret2Idx) ? On : Off; + + // LC output is depend on LC partitions value. + exp_lc_data.count = otp_lc_data[0 +: LcCountWidth]; + exp_lc_data.state = otp_lc_data[LcCountWidth +: LcStateWidth]; + + // Token values are depend on secret partitions value. + exp_lc_data.test_unlock_token = + {<<32 {otp_a[TestUnlockTokenOffset/4 +: TestUnlockTokenSize/4]}}; + exp_lc_data.test_exit_token = + {<<32 {otp_a[TestExitTokenOffset/4 +: TestExitTokenSize/4]}}; + exp_lc_data.rma_token = {<<32 {otp_a[RmaTokenOffset/4 +: RmaTokenSize/4]}}; + + // Check otp_lc_data_t struct by item is easier to debug. + `DV_CHECK_EQ(cfg.otp_ctrl_vif.lc_data_o.valid, exp_lc_data.valid) + `DV_CHECK_EQ(cfg.otp_ctrl_vif.lc_data_o.error, exp_lc_data.error) + `DV_CHECK_EQ(cfg.otp_ctrl_vif.lc_data_o.state, exp_lc_data.state) + `DV_CHECK_EQ(cfg.otp_ctrl_vif.lc_data_o.count, exp_lc_data.count) + `DV_CHECK_EQ(cfg.otp_ctrl_vif.lc_data_o.secrets_valid, exp_lc_data.secrets_valid) + `DV_CHECK_EQ(cfg.otp_ctrl_vif.lc_data_o.test_tokens_valid, + exp_lc_data.test_tokens_valid) + `DV_CHECK_EQ(cfg.otp_ctrl_vif.lc_data_o.test_unlock_token, + exp_lc_data.test_unlock_token) + `DV_CHECK_EQ(cfg.otp_ctrl_vif.lc_data_o.test_exit_token, exp_lc_data.test_exit_token) + `DV_CHECK_EQ(cfg.otp_ctrl_vif.lc_data_o.rma_token_valid, exp_lc_data.rma_token_valid) + `DV_CHECK_EQ(cfg.otp_ctrl_vif.lc_data_o.rma_token, exp_lc_data.rma_token) + + // Check otp_lc_data_t all together in case there is any missed item. + `DV_CHECK_EQ(cfg.otp_ctrl_vif.lc_data_o, exp_lc_data) + + // ---------------------- Check keymgr_key_o output --------------------------------- + // Otp_keymgr outputs creator and owner keys from secret partitions. + // Depends on lc_seed_hw_rd_en_i, it will output the real keys or a constant + exp_keymgr_data = '0; +% for part in otp_mmap.config["partitions"]: +<% + part_name = Name.from_snake_case(part["name"]) + part_name_camel = part_name.as_camel_case() +%>\ + % if part["iskeymgr_creator"] or part["iskeymgr_owner"]: + % for item in part["items"]: +<% + item_name = Name.from_snake_case(item["name"]) + item_name_camel = item_name.as_camel_case() +%>\ + % if item["iskeymgr_creator"] or item["iskeymgr_owner"]: + exp_keymgr_data.${item["name"].lower()}_valid = get_otp_digest_val(${part_name_camel}Idx) != 0; + if (cfg.otp_ctrl_vif.lc_seed_hw_rd_en_i == lc_ctrl_pkg::On) begin + exp_keymgr_data.${item["name"].lower()} = + {<<32 {otp_a[${item_name_camel}Offset/4 +: ${item_name_camel}Size/4]}}; + end else begin + exp_keymgr_data.${item["name"].lower()} = + PartInvDefault[${item_name_camel}Offset*8 +: ${item_name_camel}Size*8]; + end + // Check otp_keymgr_key_t struct by item is easier to debug. + `DV_CHECK_EQ(cfg.otp_ctrl_vif.keymgr_key_o.${item["name"].lower()}_valid, + exp_keymgr_data.${item["name"].lower()}_valid) + % endif + % endfor + % endif +% endfor + + // Check otp_keymgr_key_t struct all together in case there is any missed item. + `DV_CHECK_EQ(cfg.otp_ctrl_vif.keymgr_key_o, exp_keymgr_data) + + if (cfg.en_cov) begin + cov.keymgr_o_cg.sample(cfg.otp_ctrl_vif.lc_seed_hw_rd_en_i == lc_ctrl_pkg::On, + exp_keymgr_data.creator_root_key_share0_valid); + end + end + end else if (cfg.otp_ctrl_vif.alert_reqs) begin + // Ignore digest CSR check when otp_ctrl initialization is interrupted by fatal errors. + // SCB cannot predict how many partitions already finished initialization and updated + // the digest value to CSRs. + ignore_digest_chk = 1; + end + if (cfg.en_cov) begin + bit [NumPart-2:0] parts_locked; + foreach (parts_locked[i]) parts_locked[i] = (get_otp_digest_val(i) != 0); + cov.power_on_cg.sample(cfg.otp_ctrl_vif.lc_esc_on, parts_locked); + end + end + end + endtask + + // This task monitors internal escalation triggered by two methods: + // 1. Externally lc_escalation_en is set to lc_ctrl_pkg::On. + // 2. Internal fatal alert triggered and all partitions are driven to error states. + virtual task process_lc_esc(); + forever begin + wait(cfg.otp_ctrl_vif.alert_reqs == 1 && cfg.en_scb); + + if (cfg.otp_ctrl_vif.lc_esc_on == 0) `DV_CHECK_NE(exp_alert, OtpNoAlert) + + if (exp_alert != OtpCheckAlert) set_exp_alert("fatal_check_error", 1, 5); + + // If the lc_escalation is triggered by internal fatal alert, wait 2 negedge until status is + // updated internally + if (cfg.otp_ctrl_vif.lc_esc_on == 0) begin + cfg.clk_rst_vif.wait_n_clks(2); + exp_status[OtpCheckPendingIdx] = 0; + exp_status[OtpDaiIdleIdx] = 0; + end else begin + exp_status = '0; + // Only lc_esc_on will set these bits to 1. + exp_status[OtpDerivKeyFsmErrIdx:OtpLfsrFsmErrIdx] = '1; + end + + // Update status bits. + foreach (FATAL_EXP_STATUS[i]) begin + if (FATAL_EXP_STATUS[i]) begin + predict_err(.status_err_idx(otp_status_e'(i)), .err_code(OtpFsmStateError), + .update_esc_err(1)); + end + end + + // Update digest values and direct_access_regwen. + predict_rdata(1, 0, 0); + void'(ral.direct_access_regwen.predict(.value(0), .kind(UVM_PREDICT_READ))); + + // DAI access is locked until reset, so no need to backdoor read otp write value until reset. + + wait(cfg.otp_ctrl_vif.alert_reqs == 0); + end + endtask + + // This task monitors if lc_program req is interrupted by reset. + // If it happens, scb cannot predict how many bits have been written to OTP_CTRL. + // So here we will backdoor read back OTP lc partitions bits. + virtual task recover_lc_prog_req(); + forever begin + wait(cfg.otp_ctrl_vif.lc_prog_req == 1); + wait(cfg.otp_ctrl_vif.lc_prog_req == 0); + // Wait one 1ps to avoid race condition. + #1ps; + if (cfg.otp_ctrl_vif.rst_ni == 0) begin + for (int i = 0; i < LC_PROG_DATA_SIZE/32; i++) begin + otp_lc_data[i*32+:32] = cfg.mem_bkdr_util_h.read32(LifeCycleOffset + i * 4); + end + end + end + endtask + + virtual task process_lc_prog_req(); + forever begin + push_pull_item#(.DeviceDataWidth(1), .HostDataWidth(LC_PROG_DATA_SIZE)) rcv_item; + bit exp_err_bit; + bit [15:0] rcv_words [LC_PROG_DATA_SIZE/16]; + + lc_prog_fifo.get(rcv_item); + + // LCI is updated by OTP word. + rcv_words = {<< 16{rcv_item.h_data}}; + foreach (rcv_words[i]) begin + bit [15:0] curr_word = otp_lc_data[i*16 +: 16]; + if ((curr_word & rcv_words[i]) == curr_word) otp_lc_data[i*16 +: 16] = rcv_words[i]; + else exp_err_bit = 1; + end + + if (exp_err_bit) predict_err(OtpLciErrIdx, OtpMacroWriteBlankError); + else predict_no_err(OtpLciErrIdx); + + // LC program request data is valid means no OTP macro error. + `DV_CHECK_EQ(rcv_item.d_data, exp_err_bit) + + if (cfg.en_cov) cov.lc_prog_cg.sample(exp_err_bit); + end + endtask + + virtual task process_edn_req(); + forever begin + push_pull_item#(.DeviceDataWidth(EDN_DATA_WIDTH)) edn_item; + edn_fifos[0].get(edn_item); + edn_data_q.push_back(edn_item.d_data[EDN_BUS_WIDTH-1:0]); + end + endtask + + virtual task check_otbn_rsp(); + forever begin + push_pull_item#(.DeviceDataWidth(OTBN_DATA_SIZE)) rcv_item; + bit [SCRAMBLE_KEY_SIZE-1:0] edn_key2, edn_key1; + bit [SCRAMBLE_KEY_SIZE-1:0] sram_key; + bit [SCRAMBLE_DATA_SIZE-1:0] exp_key_lower, exp_key_higher; + bit [OtbnKeyWidth-1:0] key, exp_key; + bit [OtbnNonceWidth-1:0] nonce, exp_nonce; + bit seed_valid; + bit part_locked; + + otbn_fifo.get(rcv_item); + seed_valid = rcv_item.d_data[0]; + nonce = rcv_item.d_data[1+:OtbnNonceWidth]; + key = rcv_item.d_data[OtbnNonceWidth+1+:OtbnKeyWidth]; + part_locked = {`gmv(ral.secret1_digest[0]), `gmv(ral.secret1_digest[1])} != '0; + + // seed is valid as long as secret1 is locked + `DV_CHECK_EQ(seed_valid, part_locked, "otbn seed_valid mismatch") + + // If edn_data_q matches the OTBN requested size, check OTBN outputs + if (edn_data_q.size() == NUM_OTBN_EDN_REQ) begin + {exp_nonce, edn_key2, edn_key1} = {<<32{edn_data_q}}; + + // check nonce value + `DV_CHECK_EQ(nonce, exp_nonce, "otbn nonce mismatch") + + // calculate key + sram_key = get_key_from_otp(part_locked, SramDataKeySeedOffset / 4); + exp_key_lower = present_encode_with_final_const( + .data(RndCnstDigestIV[SramDataKey]), + .key(sram_key), + .final_const(RndCnstDigestConst[SramDataKey]), + .second_key(edn_key1), + .num_round(2)); + + exp_key_higher = present_encode_with_final_const( + .data(RndCnstDigestIV[SramDataKey]), + .key(sram_key), + .final_const(RndCnstDigestConst[SramDataKey]), + .second_key(edn_key2), + .num_round(2)); + exp_key = {exp_key_higher, exp_key_lower}; + `DV_CHECK_EQ(key, exp_key, "otbn key mismatch") + + if (cfg.en_cov) cov.otbn_req_cg.sample(part_locked); + + // If during OTBN key request, the LFSR timer expired and trigger an EDN request to acquire + // two EDN keys, then ignore the OTBN output checking, because scb did not know which EDN + // keys are used for LFSR. + // Thus any edn_data_q size equal to (16+2*N) is exempted from checking. + end else if ((edn_data_q.size() - NUM_OTBN_EDN_REQ) % 2 != 0) begin + `uvm_error(`gfn, $sformatf("Unexpected edn_data_q size (%0d) during OTBN request", + edn_data_q.size())) + end + edn_data_q.delete(); + end + endtask + + virtual task check_flash_rsps(); + for (int i = FlashDataKey; i <= FlashAddrKey; i++) begin + automatic digest_sel_e sel_flash = digest_sel_e'(i); + fork + forever begin + push_pull_item#(.DeviceDataWidth(FLASH_DATA_SIZE)) rcv_item; + bit [SCRAMBLE_KEY_SIZE-1:0] flash_key; + bit [SCRAMBLE_DATA_SIZE-1:0] exp_key_lower, exp_key_higher; + bit [FlashKeyWidth-1:0] key, exp_key; + bit seed_valid, part_locked; + int flash_key_index; + + if (sel_flash == FlashAddrKey) begin + flash_addr_fifo.get(rcv_item); + flash_key_index = FlashAddrKeySeedOffset / 4; + end else begin + flash_data_fifo.get(rcv_item); + flash_key_index = FlashDataKeySeedOffset / 4; + end + seed_valid = rcv_item.d_data[0]; + key = rcv_item.d_data[1+:FlashKeyWidth]; + part_locked = {`gmv(ral.secret1_digest[0]), `gmv(ral.secret1_digest[1])} != '0; + `DV_CHECK_EQ(seed_valid, part_locked, + $sformatf("flash %0s seed_valid mismatch", sel_flash.name())) + + // calculate key + flash_key = get_key_from_otp(part_locked, flash_key_index); + exp_key_lower = present_encode_with_final_const( + .data(RndCnstDigestIV[sel_flash]), + .key(flash_key), + .final_const(RndCnstDigestConst[sel_flash])); + + flash_key = get_key_from_otp(part_locked, flash_key_index + 4); + exp_key_higher = present_encode_with_final_const( + .data(RndCnstDigestIV[sel_flash]), + .key(flash_key), + .final_const(RndCnstDigestConst[sel_flash])); + exp_key = {exp_key_higher, exp_key_lower}; + `DV_CHECK_EQ(key, exp_key, $sformatf("flash %s key mismatch", sel_flash.name())) + + if (cfg.en_cov) cov.flash_req_cg.sample(sel_flash, part_locked); + end + join_none; + end + endtask + + virtual task check_sram_rsps(); + for (int i = 0; i < NumSramKeyReqSlots; i++) begin + automatic int index = i; + fork + forever begin + push_pull_item#(.DeviceDataWidth(SRAM_DATA_SIZE)) rcv_item; + sram_key_t key, exp_key; + sram_nonce_t nonce, exp_nonce; + bit seed_valid, part_locked; + bit [SCRAMBLE_KEY_SIZE-1:0] edn_key2, edn_key1; + bit [SCRAMBLE_KEY_SIZE-1:0] sram_key; // key used as input to present algo + bit [SCRAMBLE_DATA_SIZE-1:0] exp_key_lower, exp_key_higher; + + sram_fifos[index].get(rcv_item); + seed_valid = rcv_item.d_data[0]; + nonce = rcv_item.d_data[1+:SramNonceWidth]; + key = rcv_item.d_data[SramNonceWidth+1+:SramKeyWidth]; + part_locked = {`gmv(ral.secret1_digest[0]), `gmv(ral.secret1_digest[1])} != '0; + + // seed is valid as long as secret1 is locked + `DV_CHECK_EQ(seed_valid, part_locked, $sformatf("sram_%0d seed_valid mismatch", index)) + + // If edn_data_q matches the OTBN requested size, check OTBN outputs + if (edn_data_q.size() == NUM_SRAM_EDN_REQ) begin + {exp_nonce, edn_key2, edn_key1} = {<<32{edn_data_q}}; + + // check nonce value + `DV_CHECK_EQ(nonce, exp_nonce, $sformatf("sram_%0d nonce mismatch", index)) + + // calculate key + sram_key = get_key_from_otp(part_locked, SramDataKeySeedOffset / 4); + exp_key_lower = present_encode_with_final_const( + .data(RndCnstDigestIV[SramDataKey]), + .key(sram_key), + .final_const(RndCnstDigestConst[SramDataKey]), + .second_key(edn_key1), + .num_round(2)); + + exp_key_higher = present_encode_with_final_const( + .data(RndCnstDigestIV[SramDataKey]), + .key(sram_key), + .final_const(RndCnstDigestConst[SramDataKey]), + .second_key(edn_key2), + .num_round(2)); + exp_key = {exp_key_higher, exp_key_lower}; + `DV_CHECK_EQ(key, exp_key, $sformatf("sram_%0d key mismatch", index)) + if (cfg.en_cov) cov.sram_req_cg.sample(index, part_locked); + + end else if ((edn_data_q.size() - NUM_SRAM_EDN_REQ) % 2 != 0) begin + `uvm_error(`gfn, $sformatf("Unexpected edn_data_q size (%0d) during SRAM request", + edn_data_q.size())) + end + edn_data_q.delete(); + end + join_none + end + endtask + + virtual task process_tl_access(tl_seq_item item, tl_channels_e channel, string ral_name); + bit write = item.is_write(); + uvm_reg_addr_t csr_addr = cfg.ral_models[ral_name].get_word_aligned_addr(item.a_addr); + bit [TL_AW-1:0] addr_mask = ral.get_addr_mask(); + + bit addr_phase_read = (!write && channel == AddrChannel); + bit addr_phase_write = (write && channel == AddrChannel); + bit data_phase_read = (!write && channel == DataChannel); + bit data_phase_write = (write && channel == DataChannel); + + if (ral_name != "otp_ctrl_prim_reg_block") begin + process_core_tl_access(item, csr_addr, ral_name, addr_mask, + addr_phase_read, addr_phase_write, data_phase_read, data_phase_write); + end else begin + process_prim_tl_access(item, csr_addr, ral_name, addr_phase_write, data_phase_read); + end + endtask + + virtual function void process_prim_tl_access(tl_seq_item item, uvm_reg_addr_t csr_addr, + string ral_name, bit addr_phase_write, bit data_phase_read); + + uvm_reg csr; + dv_base_reg dv_reg; + csr = cfg.ral_models[ral_name].default_map.get_reg_by_offset(csr_addr); + `DV_CHECK_NE_FATAL(csr, null) + `downcast(dv_reg, csr) + + if (addr_phase_write) begin + void'(csr.predict(.value(item.a_data), .kind(UVM_PREDICT_WRITE), .be(item.a_mask))); + end else if (data_phase_read) begin + `DV_CHECK_EQ((csr.get_mirrored_value() | status_mask), (item.d_data | status_mask), + $sformatf("reg name: status, compare_mask %0h", status_mask)) + end + endfunction + + virtual function void process_core_tl_access(tl_seq_item item, uvm_reg_addr_t csr_addr, + string ral_name, bit [TL_AW-1:0] addr_mask, bit addr_phase_read, bit addr_phase_write, + bit data_phase_read, bit data_phase_write); + + bit do_read_check = 1; + uvm_reg csr; + dv_base_reg dv_reg; + string csr_name; + + `uvm_info(`gfn, $sformatf("sw state %d, reg state %d", direct_access_regwen_state, + `gmv(ral.direct_access_regwen)), UVM_LOW); + + // if access was to a valid csr, get the csr handle + if (csr_addr inside {cfg.ral_models[ral_name].csr_addrs}) begin + csr = cfg.ral_models[ral_name].default_map.get_reg_by_offset(csr_addr); + `DV_CHECK_NE_FATAL(csr, null) + `downcast(dv_reg, csr) + // SW CFG window + end else if ((csr_addr & addr_mask) inside + {[SW_WINDOW_BASE_ADDR : SW_WINDOW_BASE_ADDR + SW_WINDOW_SIZE]}) begin + if (data_phase_read) begin + bit [TL_AW-1:0] dai_addr = (csr_addr & addr_mask - SW_WINDOW_BASE_ADDR); + bit [TL_AW-1:0] otp_addr = dai_addr >> 2; + int part_idx = get_part_index(dai_addr); + bit [TL_DW-1:0] read_out; + int ecc_err = OtpNoEccErr; + + // We can't get an ECC error if the partition does not have integrity. + if (part_has_integrity(part_idx)) begin + ecc_err = read_a_word_with_ecc(dai_addr, read_out); + end else begin + ecc_err = read_a_word_with_ecc_raw(dai_addr, read_out); + end + + if (part_has_digest(part_idx) && cfg.en_cov) begin + cov.unbuf_access_lock_cg_wrap[part_idx].sample(.read_lock(0), + .write_lock(get_digest_reg_val(part_idx) != 0), .is_write(0)); + end + + // Any alert that indicates the OTP block is in the final error state should not enter the + // logic here, but gated at `is_tl_mem_access_allowed` function. + `DV_CHECK_EQ(cfg.otp_ctrl_vif.alert_reqs, 0) + + // ECC uncorrectable errors are gated by `is_tl_mem_access_allowed` function. + if (ecc_err != OtpNoEccErr && part_has_integrity(part_idx)) begin + + predict_err(otp_status_e'(part_idx), OtpMacroEccCorrError); + if (ecc_err == OtpEccCorrErr) begin + `DV_CHECK_EQ(item.d_data, otp_a[otp_addr], + $sformatf("mem read mismatch at TLUL addr %0h, csr_addr %0h", + csr_addr, dai_addr)) + end else begin + // Only check the first 16 bits because if ECC readout detects uncorrectable error, it + // won't continue read the remaining 16 bits. + `DV_CHECK_EQ(item.d_data & 16'hffff, read_out & 16'hffff, + $sformatf("mem read mismatch at TLUL addr %0h, csr_addr %0h", + csr_addr, dai_addr)) + end + // If there is an injected error, but the partition cannot detect it, we have to compare + // to the value read via the backdoor instead of otp_a[otp_addr] since otherwise the + // perturbed value does not get modelled correctly. + end else if (ecc_err != OtpNoEccErr && !part_has_integrity(part_idx)) begin + `DV_CHECK_EQ(item.d_data, read_out, + $sformatf("mem read mismatch at TLUL addr %0h, csr_addr %0h", + csr_addr, dai_addr)) + predict_no_err(otp_status_e'(part_idx)); + end else if (ecc_err == OtpNoEccErr) begin + `DV_CHECK_EQ(item.d_data, otp_a[otp_addr], + $sformatf("mem read mismatch at TLUL addr %0h, csr_addr %0h", + csr_addr, dai_addr)) + predict_no_err(otp_status_e'(part_idx)); + end + end + return; + end else begin + `uvm_fatal(`gfn, $sformatf("Access unexpected addr 0x%0h", csr_addr)) + end + + csr_name = csr.get_name(); + + if (addr_phase_write) begin + if (cfg.en_cov && cfg.otp_ctrl_vif.alert_reqs && csr_name == "direct_access_cmd") begin + cov.req_dai_access_after_alert_cg.sample(item.a_data); + end + + // Skip predict if the register is locked by `direct_access_regwen`. + // An exception is the direct_access_regwen which may always be written. + if (ral.direct_access_regwen.locks_reg_or_fld(dv_reg) && + `gmv(ral.direct_access_regwen) == 0 && + csr_name != "direct_access_regwen") return; + + void'(csr.predict(.value(item.a_data), .kind(UVM_PREDICT_WRITE), .be(item.a_mask))); + end + + // process the csr req + // for write, update local variable and fifo at address phase + // for read, update predication at address phase and compare at data phase + case (csr_name) + // add individual case item for each csr + "intr_state": begin + if (data_phase_read) begin + // Disable intr_state checking when lc_program is in progress, because scb cannot + // accurately predict when program_error will be triggered. + // We will check the intr_state after lc_program request is done, and the error bit will + // be checked in the `process_lc_prog_req` task. + if (cfg.otp_ctrl_vif.lc_prog_no_sta_check) do_read_check = 0; + if (do_read_check) begin + bit [TL_DW-1:0] intr_en = `gmv(ral.intr_enable); + bit [NumOtpCtrlIntr-1:0] intr_exp = `gmv(ral.intr_state); + + foreach (intr_exp[i]) begin + otp_intr_e intr = otp_intr_e'(i); + `DV_CHECK_CASE_EQ(cfg.intr_vif.pins[i], (intr_en[i] & intr_exp[i]), + $sformatf("Interrupt_pin: %0s", intr.name)); + if (cfg.en_cov) begin + cov.intr_cg.sample(i, intr_en[i], item.d_data[i]); + cov.intr_pins_cg.sample(i, cfg.intr_vif.pins[i]); + end + end + end + end + end + "intr_test": begin + if (addr_phase_write) begin + bit [TL_DW-1:0] intr_en = `gmv(ral.intr_enable); + bit [NumOtpCtrlIntr-1:0] intr_exp = `gmv(ral.intr_state) | item.a_data; + + void'(ral.intr_state.predict(.value(intr_exp))); + if (cfg.en_cov) begin + foreach (intr_exp[i]) begin + cov.intr_test_cg.sample(i, item.a_data[i], intr_en[i], intr_exp[i]); + end + end + end + end + "direct_access_cmd": begin + if (addr_phase_write && !cfg.otp_ctrl_vif.under_error_states()) begin + // here only normalize to 2 lsb, if is secret, will be reduced further + bit [TL_AW-1:0] dai_addr = normalize_dai_addr(`gmv(ral.direct_access_address)); + int part_idx = get_part_index(dai_addr); + bit sw_read_lock = 0; + void'(ral.direct_access_regwen.predict(0)); + under_dai_access = 1; + + // Check if it is sw partition read lock - this can be used in `DaiRead` branch and also + // coverage collection. +% for part in read_locked_csr_parts: +<% part_name = Name.from_snake_case(part["name"]) %>\ + % if loop.first: + if (part_idx == ${part_name.as_camel_case()}Idx) begin + % else: + end else if (part_idx == ${part_name.as_camel_case()}Idx) begin + % endif + sw_read_lock = `gmv(ral.${part_name.as_snake_case()}_read_lock) == 0; + % if loop.last: + end + %endif +% endfor + + // LC partition cannot be access via DAI + if (part_idx == LifeCycleIdx) begin + predict_err(OtpDaiErrIdx, OtpAccessError); + if (item.a_data == DaiRead) predict_rdata(is_secret(dai_addr), 0, 0); + end else begin + // Collect coverage. + if (cfg.en_cov) begin + if (part_idx == Secret2Idx) begin + cov.dai_access_secret2_cg.sample( + !(cfg.otp_ctrl_vif.lc_creator_seed_sw_rw_en_i != lc_ctrl_pkg::On), + dai_cmd_e'(item.a_data)); + end else if (is_sw_part_idx(part_idx) && part_has_digest(part_idx) && + item.a_data inside {DaiRead, DaiWrite}) begin + cov.unbuf_access_lock_cg_wrap[part_idx].sample(.read_lock(sw_read_lock), + .write_lock(get_digest_reg_val(part_idx) != 0), + .is_write(item.a_data == DaiWrite)); + + end + end + + case (item.a_data) + DaiDigest: cal_digest_val(part_idx); + DaiRead: begin + // Check if it is sw partition read lock + check_dai_rd_data = 1; + + // SW partitions write read_lock_csr can lock read access. + if (sw_read_lock || + // Secret partitions cal digest can also lock read access. + // However, digest is always readable except SW partitions (Issue #5752). + (is_secret(dai_addr) && get_digest_reg_val(part_idx) != 0 && + !is_digest(dai_addr)) || + // If the partition has creator key material and lc_creator_seed_sw_rw is + // disable, then return access error. + (PartInfo[part_idx].iskeymgr_creator && !is_digest(dai_addr) && + cfg.otp_ctrl_vif.lc_creator_seed_sw_rw_en_i != lc_ctrl_pkg::On)) begin + predict_err(OtpDaiErrIdx, OtpAccessError); + predict_rdata(is_secret(dai_addr) || is_digest(dai_addr), 0, 0); + end else if (sw_read_lock || + // Secret partitions cal digest can also lock read access. + // However, digest is always readable except SW partitions (Issue #5752). + (is_secret(dai_addr) && get_digest_reg_val(part_idx) != 0 && + !is_digest(dai_addr)) || + // If the partition has owner key material and lc_owner_seed_sw_rw is disable, + // then return access error. + (PartInfo[part_idx].iskeymgr_owner && !is_digest(dai_addr) && + cfg.otp_ctrl_vif.lc_owner_seed_sw_rw_en_i != lc_ctrl_pkg::On)) begin + predict_err(OtpDaiErrIdx, OtpAccessError); + predict_rdata(is_secret(dai_addr) || is_digest(dai_addr), 0, 0); + + end else begin + bit [TL_DW-1:0] read_out0, read_out1; + bit [TL_AW-1:0] otp_addr = get_scb_otp_addr(); + int ecc_err = 0; + + // Backdoor read to check if there is any ECC error. + if (part_has_integrity(part_idx)) begin + ecc_err = read_a_word_with_ecc(dai_addr, read_out0); + if (is_secret(dai_addr) || is_digest(dai_addr)) begin + ecc_err = max2(read_a_word_with_ecc(dai_addr + 4, read_out1), ecc_err); + end + end else begin + ecc_err = read_a_word_with_ecc_raw(dai_addr, read_out0); + if (is_secret(dai_addr) || is_digest(dai_addr)) begin + ecc_err = max2(read_a_word_with_ecc_raw(dai_addr + 4, read_out1), ecc_err); + end + end + + if (ecc_err == OtpEccCorrErr && part_has_integrity(part_idx)) begin + predict_err(OtpDaiErrIdx, OtpMacroEccCorrError); + backdoor_update_otp_array(dai_addr); + predict_rdata(is_secret(dai_addr) || is_digest(dai_addr), + otp_a[otp_addr], otp_a[otp_addr+1]); + end else if (ecc_err == OtpEccUncorrErr && part_has_integrity(part_idx)) begin + predict_err(OtpDaiErrIdx, OtpMacroEccUncorrError); + // Max wait 20 clock cycles because scb did not know when exactly OTP will + // finish reading and reporting the uncorrectable error. + set_exp_alert("fatal_macro_error", 1, 20); + predict_rdata(1, 0, 0); + // Some partitions do not interpret/report ECC errors. In those cases + // we still need to model the read data correctly if it has been perturbed. + end else if (ecc_err inside {OtpEccCorrErr, OtpEccUncorrErr} && + !part_has_integrity(part_idx)) begin + predict_no_err(OtpDaiErrIdx); + predict_rdata(is_secret(dai_addr) || is_digest(dai_addr), + read_out0, read_out1); + end else begin + predict_no_err(OtpDaiErrIdx); + predict_rdata(is_secret(dai_addr) || is_digest(dai_addr), + otp_a[otp_addr], otp_a[otp_addr+1]); + end + end + end + DaiWrite: begin + bit[TL_AW-1:0] otp_addr = get_scb_otp_addr(); + bit is_write_locked; + // check if write locked + if (part_has_digest(part_idx)) begin + is_write_locked = get_digest_reg_val(part_idx) != 0; + end else begin + is_write_locked = 0; + end + + if (is_write_locked || (PartInfo[part_idx].iskeymgr_creator && + !is_digest(dai_addr) && + cfg.otp_ctrl_vif.lc_creator_seed_sw_rw_en_i != lc_ctrl_pkg::On)) begin + predict_err(OtpDaiErrIdx, OtpAccessError); + end else if (is_write_locked || (PartInfo[part_idx].iskeymgr_owner && + !is_digest(dai_addr) && + cfg.otp_ctrl_vif.lc_owner_seed_sw_rw_en_i != lc_ctrl_pkg::On)) begin + predict_err(OtpDaiErrIdx, OtpAccessError); + end else begin + predict_no_err(OtpDaiErrIdx); + // write digest + if (is_sw_digest(dai_addr)) begin + bit [TL_DW*2-1:0] curr_digest, prev_digest; + curr_digest = {`gmv(ral.direct_access_wdata[1]), + `gmv(ral.direct_access_wdata[0])}; + prev_digest = {otp_a[otp_addr+1], otp_a[otp_addr]}; + dai_wr_ip = 1; + // allow bit write + if ((prev_digest & curr_digest) == prev_digest) begin + update_digest_to_otp(part_idx, curr_digest); + end else begin + predict_err(OtpDaiErrIdx, OtpMacroWriteBlankError); + end + end else if (is_digest(dai_addr)) begin + predict_err(OtpDaiErrIdx, OtpAccessError); + // write OTP memory + end else begin + dai_wr_ip = 1; + if (!is_secret(dai_addr)) begin + bit [TL_DW-1:0] wr_data = `gmv(ral.direct_access_wdata[0]); + // allow bit write + if ((otp_a[otp_addr] & wr_data) == otp_a[otp_addr]) begin + otp_a[otp_addr] = wr_data; + check_otp_idle(.val(0), .wait_clks(3)); + end else begin + predict_err(OtpDaiErrIdx, OtpMacroWriteBlankError); + end + end else begin + bit [SCRAMBLE_DATA_SIZE-1:0] secret_data = {otp_a[otp_addr + 1], + otp_a[otp_addr]}; + bit [SCRAMBLE_DATA_SIZE-1:0] wr_data = {`gmv(ral.direct_access_wdata[1]), + `gmv(ral.direct_access_wdata[0])}; + wr_data = scramble_data(wr_data, part_idx); + secret_data = scramble_data(secret_data, part_idx); + if ((secret_data & wr_data) == secret_data) begin + otp_a[otp_addr] = `gmv(ral.direct_access_wdata[0]); + otp_a[otp_addr + 1] = `gmv(ral.direct_access_wdata[1]); + // wait until secret scrambling is done + check_otp_idle(.val(0), .wait_clks(34)); + end else begin + predict_err(OtpDaiErrIdx, OtpMacroWriteBlankError); + end + end + end + end + end + default: begin + `uvm_fatal(`gfn, $sformatf("invalid cmd: %0d", item.a_data)) + end + endcase + // regwen is set to 0 only if the dai operation is successfully + if (`gmv(ral.intr_state.otp_error) == 0) void'(ral.direct_access_regwen.predict(0)); + end + end + end + "status": begin + if (addr_phase_read) begin + void'(ral.status.predict(.value(exp_status), .kind(UVM_PREDICT_READ))); + + // update status mask + status_mask = 0; + // Mask out check_pending field - we do not know how long it takes to process checks. + // Check failure can trigger all kinds of errors. + if (under_chk) status_mask = '1; + + // Mask out otp_dai access related field - we do not know how long it takes to finish + // DAI access. + if (under_dai_access) begin + status_mask[OtpDaiIdleIdx] = 1; + status_mask[OtpDaiErrIdx] = 1; + end + + // Mask out LCI error bit if lc_req is set. + if (cfg.otp_ctrl_vif.lc_prog_no_sta_check) status_mask[OtpLciErrIdx] = 1; + + end else if (data_phase_read) begin + if (cfg.en_cov) begin + cov.collect_status_cov(item.d_data); + if (cfg.otp_ctrl_vif.alert_reqs) begin + cov.csr_rd_after_alert_cg_wrap.sample(csr.get_offset()); + end + end + + if (item.d_data[OtpDaiIdleIdx]) begin + check_otp_idle(1); + dai_wr_ip = 0; + dai_digest_ip = LifeCycleIdx; + end + + // STATUS register check with mask + if (do_read_check) begin + `DV_CHECK_EQ((csr.get_mirrored_value() | status_mask), (item.d_data | status_mask), + $sformatf("reg name: status, compare_mask %0h", status_mask)) + end + + // Check if OtpCheckPending is set correctly, then ignore checking until check is done + if (under_chk) begin + if (item.d_data[OtpCheckPendingIdx] == 0) begin + exp_status[OtpCheckPendingIdx] = 0; + under_chk = 0; + end + end + + if (under_dai_access && !cfg.otp_ctrl_vif.under_error_states()) begin + if (item.d_data[OtpDaiIdleIdx]) begin + under_dai_access = 0; + void'(ral.direct_access_regwen.predict(direct_access_regwen_state)); + void'(ral.intr_state.otp_operation_done.predict(1)); + end + end + end + // checked in this block above + do_read_check = 0; + end + "check_trigger": begin + if (addr_phase_write && cfg.en_cov && cfg.otp_ctrl_vif.alert_reqs) begin + cov.issue_checks_after_alert_cg.sample(item.a_data); + end + + if (addr_phase_write && `gmv(ral.check_trigger_regwen) && item.a_data inside {[1:3]}) begin + bit [TL_DW-1:0] check_timeout = `gmv(ral.check_timeout) == 0 ? '1 : + `gmv(ral.check_timeout); + exp_status[OtpCheckPendingIdx] = 1; + under_chk = 1; + if (check_timeout <= CHK_TIMEOUT_CYC) begin + set_exp_alert("fatal_check_error", 1, `gmv(ral.check_timeout)); + predict_err(OtpTimeoutErrIdx); + end else begin + if (get_field_val(ral.check_trigger.consistency, item.a_data)) begin + foreach (cfg.ecc_chk_err[i]) begin + if (cfg.ecc_chk_err[i] == OtpEccCorrErr && part_has_integrity(i)) begin + predict_err(otp_status_e'(i), OtpMacroEccCorrError); + end else if (cfg.ecc_chk_err[i] == OtpEccUncorrErr && + part_has_integrity(i)) begin + set_exp_alert("fatal_macro_error", 1, 40_000); + predict_err(otp_status_e'(i), OtpMacroEccUncorrError); + end + end + end + end + end + end + "direct_access_regwen": begin + if (addr_phase_write) begin + // This locks the DAI until the next reset. + if (!item.a_data[0]) begin + direct_access_regwen_state = 0; + void'(ral.direct_access_regwen.predict(0)); + end + end + end + // For error codes, if lc_prog in progress, err_code might update anytime in DUT. Ignore + // checking until req is acknowledged. + +% for k in range(num_err_code): +<% + # This code should depend on whether the error code is compact. This + # assumes it is not compact. +%>\ + "err_code_${k}": begin + if (cfg.m_lc_prog_pull_agent_cfg.vif.req) do_read_check = 0; + if (cfg.en_cov && do_read_check && data_phase_read) begin + bit [TL_DW-1:0] dai_addr = `gmv(ral.direct_access_address) >> 2 << 2; + int access_part_idx = get_part_index(dai_addr); + cov.collect_err_code_cov(${k}, item.d_data, access_part_idx); + end + end +% endfor +% for part in write_locked_digest_parts: +<% part_name_snake = Name.from_snake_case(part["name"]).as_snake_case() %>\ + "${part_name_snake}_digest_0", "${part_name_snake}_digest_1"${": begin" if loop.last else ","} +% endfor + if (ignore_digest_chk) do_read_check = 0; + end +% for part in read_locked_csr_parts: +<% part_name_snake = Name.from_snake_case(part["name"]).as_snake_case() %>\ + "${part_name_snake}_read_lock", +% endfor + "direct_access_wdata_0", + "direct_access_wdata_1", + "direct_access_address", + "check_regwen", + "check_trigger_regwen", + "check_trigger", + "check_timeout", + "intr_enable", + "integrity_check_period", + "consistency_check_period", + "alert_test": begin + // Do nothing + end + // DAI read data + "direct_access_rdata_0", "direct_access_rdata_1": do_read_check = check_dai_rd_data; + default: begin + `uvm_fatal(`gfn, $sformatf("invalid csr: %0s", csr.get_full_name())) + end + endcase + + // On reads, if do_read_check, is set, then check mirrored_value against item.d_data + if (data_phase_read) begin + if (do_read_check) begin + `DV_CHECK_EQ(csr.get_mirrored_value(), item.d_data, + $sformatf("reg name: %0s", csr.get_full_name())) + if (cfg.en_cov && cfg.otp_ctrl_vif.alert_reqs) begin + cov.csr_rd_after_alert_cg_wrap.sample(csr.get_offset()); + end + end + void'(csr.predict(.value(item.d_data), .kind(UVM_PREDICT_READ))); + end + endfunction + + // If reset or lc_escalate_en is issued during otp program, this function will backdoor update + // otp memory write value because scb did not know how many cells haven been written. + // We won't update csr `direct_access_address` after fatal alert happened, so in this function + // we can directly call method `get_scb_otp_addr` to get the interrupted dai address. + virtual function void recover_interrupted_op(); + if (dai_wr_ip) begin + bit [TL_DW-1:0] otp_addr = get_scb_otp_addr(); + bit [TL_DW-1:0] dai_addr = otp_addr << 2; + backdoor_update_otp_array(dai_addr); + dai_wr_ip = 0; + end + endfunction + + virtual function void backdoor_update_otp_array(bit [TL_DW-1:0] dai_addr); + bit [TL_DW-1:0] otp_addr = dai_addr >> 2; + bit [TL_DW-1:0] readout_word, readout_word1; + int part_idx = get_part_index(dai_addr); + if (part_has_integrity(part_idx)) begin + void'(read_a_word_with_ecc(dai_addr, readout_word)); + void'(read_a_word_with_ecc(dai_addr + 4, readout_word1)); + end else begin + void'(read_a_word_with_ecc_raw(dai_addr, readout_word)); + void'(read_a_word_with_ecc_raw(dai_addr + 4, readout_word1)); + end + + otp_a[otp_addr] = readout_word; + + if (is_digest(dai_addr)) begin + otp_a[otp_addr+1] = readout_word1; + end else if (is_secret(dai_addr)) begin + bit [TL_DW*2-1:0] mem_rd_val, descrambled_val; + mem_rd_val = {readout_word1 ,readout_word}; + descrambled_val = descramble_data(mem_rd_val, part_idx); + otp_a[otp_addr+1] = descrambled_val[TL_DW*2-1:TL_DW]; + otp_a[otp_addr] = descrambled_val[TL_DW-1:0]; + end + endfunction + + virtual function bit [1:0] read_a_word_with_ecc(bit [TL_DW-1:0] dai_addr, + ref bit [TL_DW-1:0] readout_word); + prim_secded_pkg::secded_22_16_t ecc_rd_data0 = cfg.mem_bkdr_util_h.ecc_read16(dai_addr); + prim_secded_pkg::secded_22_16_t ecc_rd_data1 = cfg.mem_bkdr_util_h.ecc_read16(dai_addr + 2); + readout_word[15:0] = ecc_rd_data0.data; + readout_word[31:16] = ecc_rd_data1.data; + return max2(ecc_rd_data0.err, ecc_rd_data1.err); + endfunction + + // Returns the ECC error but does not correct the data bits (i.e. returns the raw data). + virtual function bit [1:0] read_a_word_with_ecc_raw(bit [TL_DW-1:0] dai_addr, + ref bit [TL_DW-1:0] readout_word); + prim_secded_pkg::secded_22_16_t ecc_rd_data0 = cfg.mem_bkdr_util_h.ecc_read16(dai_addr); + prim_secded_pkg::secded_22_16_t ecc_rd_data1 = cfg.mem_bkdr_util_h.ecc_read16(dai_addr + 2); + readout_word[15:0] = 16'hFFFF & cfg.mem_bkdr_util_h.read(dai_addr); + readout_word[31:16] = 16'hFFFF & cfg.mem_bkdr_util_h.read(dai_addr + 2); + return max2(ecc_rd_data0.err, ecc_rd_data1.err); + endfunction + + + virtual function void reset(string kind = "HARD"); + recover_interrupted_op(); + super.reset(kind); + // flush fifos + otbn_fifo.flush(); + flash_addr_fifo.flush(); + flash_data_fifo.flush(); + lc_prog_fifo.flush(); + for (int i = 0; i < NumSramKeyReqSlots; i++) begin + sram_fifos[i].flush(); + end + + direct_access_regwen_state = 1; + under_chk = 0; + under_dai_access = 0; + ignore_digest_chk = 0; + exp_status = `gmv(ral.status); + exp_alert = OtpNoAlert; + + edn_data_q.delete(); + + // Out of reset: lock dai access until power init is done + if (cfg.en_scb) void'(ral.direct_access_regwen.predict(0)); + endfunction + + virtual function void check_otp_idle(bit val, int wait_clks = 0); + fork + begin + fork + begin + // use negedge to avoid race condition + cfg.clk_rst_vif.wait_n_clks(wait_clks + 1); + `uvm_error(`gfn, + $sformatf("pwr_otp_idle output is %0b while expect %0b within %0d cycles", + cfg.otp_ctrl_vif.pwr_otp_idle_o, val, wait_clks)) + end + begin + wait(cfg.under_reset || cfg.otp_ctrl_vif.pwr_otp_idle_o == val || + // Due to OTP access arbitration, any KDI request during DAI access might block + // write secret until KDI request is completed. Since the KDI process time could + // vary depends on the push-pull-agent, we are going to ignore the checking if + // this scenario happens. + cfg.m_otbn_pull_agent_cfg.vif.req || + cfg.m_flash_data_pull_agent_cfg.vif.req || + cfg.m_flash_addr_pull_agent_cfg.vif.req || + cfg.m_sram_pull_agent_cfg[0].vif.req || + cfg.m_sram_pull_agent_cfg[1].vif.req || + cfg.m_sram_pull_agent_cfg[2].vif.req || + cfg.m_sram_pull_agent_cfg[3].vif.req || + cfg.m_lc_prog_pull_agent_cfg.vif.req || + // When lc_escalation is on, the DAI interface goes to ErrorSt, so ignore + // otp_idle checking. + cfg.otp_ctrl_vif.alert_reqs || + // Check timeout will keep doing background check, issue #5616 + exp_status[OtpTimeoutErrIdx]); + end + join_any + disable fork; + end + join_none + endfunction + + // predict digest registers + virtual function void predict_digest_csrs(); +% for part in write_locked_digest_parts: +<% part_name = Name.from_snake_case(part["name"]) %>\ + void'(ral.${part_name.as_snake_case()}_digest[0].predict( + .value(otp_a[PART_OTP_DIGEST_ADDRS[${part_name.as_camel_case()}Idx]]), + .kind(UVM_PREDICT_DIRECT))); + void'(ral.${part_name.as_snake_case()}_digest[1].predict( + .value(otp_a[PART_OTP_DIGEST_ADDRS[${part_name.as_camel_case()}Idx] + 1]), + .kind(UVM_PREDICT_DIRECT))); + % if not loop.last: + + %endif +% endfor + endfunction + + function void update_digest_to_otp(int part_idx, bit [TL_DW*2-1:0] digest); + otp_a[PART_OTP_DIGEST_ADDRS[part_idx]] = digest[31:0]; + otp_a[PART_OTP_DIGEST_ADDRS[part_idx] + 1] = digest[63:32]; + endfunction + + function void check_phase(uvm_phase phase); + super.check_phase(phase); + // post test checks - ensure that all local fifos and queues are empty + endfunction + + // Calculate digest value for each partition + // According to the design spec, the calculation is based on 64-rounds of PRESENT cipher + // The 64-bit data_in state is initialized with a silicon creator constant, and each 128 bit + // chunk of partition data are fed in as keys + // The last 64-round PRESENT calculation will use a global digest constant as key input + function void cal_digest_val(int part_idx); + bit [TL_DW-1:0] mem_q[$]; + int array_size; + bit [SCRAMBLE_DATA_SIZE-1:0] digest; + + if (cfg.otp_ctrl_vif.under_error_states()) return; + + if (!part_has_hw_digest(part_idx) || get_digest_reg_val(part_idx) != 0) begin + predict_err(OtpDaiErrIdx, OtpAccessError); + return; + end else if (PartInfo[part_idx].iskeymgr_creator && + cfg.otp_ctrl_vif.lc_creator_seed_sw_rw_en_i != lc_ctrl_pkg::On) begin + predict_err(OtpDaiErrIdx, OtpAccessError); + return; + end else if (PartInfo[part_idx].iskeymgr_owner && + cfg.otp_ctrl_vif.lc_owner_seed_sw_rw_en_i != lc_ctrl_pkg::On) begin + predict_err(OtpDaiErrIdx, OtpAccessError); + return; + end else begin + predict_no_err(OtpDaiErrIdx); + dai_digest_ip = part_idx; + end + case (part_idx) +% for part in buf_parts_without_lc: +<% + part_name = Name.from_snake_case(part["name"]) + part_name_camel = part_name.as_camel_case() +%>\ + ${part_name_camel}Idx: mem_q = otp_a[${part_name_camel}Offset / TL_SIZE : ${part_name_camel}DigestOffset / TL_SIZE - 1]; +% endfor + default: begin + `uvm_fatal(`gfn, $sformatf("Access unexpected partition %0d", part_idx)) + end + endcase + + array_size = mem_q.size(); + + // for secret partitions, need to use otp scrambled value as data input + if (PartInfo[part_idx].secret) begin + bit [TL_DW-1:0] scrambled_mem_q[$]; + for (int i = 0; i < array_size/2; i++) begin + bit [SCRAMBLE_DATA_SIZE-1:0] scrambled_data; + scrambled_data = scramble_data({mem_q[i*2+1], mem_q[i*2]}, part_idx); + scrambled_mem_q.push_back(scrambled_data[TL_DW-1:0]); + scrambled_mem_q.push_back(scrambled_data[SCRAMBLE_DATA_SIZE-1:TL_DW]); + end + mem_q = scrambled_mem_q; + end + + digest = otp_scrambler_pkg::cal_digest(part_idx, mem_q); + update_digest_to_otp(part_idx, digest); + endfunction + + + // this function go through present encode algo two or three iterations: + // first iteration with input key, + // second iteration with second_key, this iteration only happens if num_round is 2 + // third iteration with a final constant as key + // this is mainly used for unlock token hashing, key derivation + virtual function bit [SCRAMBLE_DATA_SIZE-1:0] present_encode_with_final_const( + bit [SCRAMBLE_DATA_SIZE-1:0] data, + bit [SCRAMBLE_KEY_SIZE-1:0] key, + bit [SCRAMBLE_KEY_SIZE-1:0] final_const, + bit [SCRAMBLE_KEY_SIZE-1:0] second_key = '0, + int num_round = 1); + bit [SCRAMBLE_DATA_SIZE-1:0] enc_data; + bit [SCRAMBLE_DATA_SIZE-1:0] intermediate_state; + crypto_dpi_present_pkg::sv_dpi_present_encrypt(data, key, + SCRAMBLE_KEY_SIZE, NUM_ROUND, enc_data); + // XOR the previous state into the digest result according to the Davies-Meyer scheme. + intermediate_state = data ^ enc_data; + + if (num_round == 2) begin + crypto_dpi_present_pkg::sv_dpi_present_encrypt(intermediate_state, second_key, + SCRAMBLE_KEY_SIZE, NUM_ROUND, enc_data); + intermediate_state = intermediate_state ^ enc_data; + end else if (num_round > 2) begin + `uvm_fatal(`gfn, $sformatf("does not support num_round: %0d > 2", num_round)) + end + + crypto_dpi_present_pkg::sv_dpi_present_encrypt(intermediate_state, final_const, + SCRAMBLE_KEY_SIZE, NUM_ROUND, enc_data); + // XOR the previous state into the digest result according to the Davies-Meyer scheme. + present_encode_with_final_const = intermediate_state ^ enc_data; + endfunction + + // Get address for scoreboard's otp_a array from the `direct_access_address` CSR + function bit [TL_DW-1:0] get_scb_otp_addr(); + bit [TL_DW-1:0] dai_addr = `gmv(ral.direct_access_address); + get_scb_otp_addr = normalize_dai_addr(dai_addr) >> 2; + endfunction + + // This function predict OTP error related registers: intr_state, status, and err_code + virtual function void predict_err(otp_status_e status_err_idx, + otp_err_code_e err_code = OtpNoError, + bit update_esc_err = 0); + if (cfg.otp_ctrl_vif.under_error_states() && !update_esc_err) return; + + // Update intr_state + void'(ral.intr_state.otp_error.predict(.value(1), .kind(UVM_PREDICT_READ))); + // Update status + exp_status[status_err_idx] = 1; + + // Only first status errors up to the LCI have corresponding err_code + if (status_err_idx <= OtpLciErrIdx) begin + dv_base_reg_field err_code_flds[$]; + if (err_code == OtpNoError) begin + `uvm_error(`gfn, $sformatf("please set status error: %0s error code", status_err_idx.name)) + end + ral.err_code[status_err_idx].get_dv_base_reg_fields(err_code_flds); + + if (`gmv(err_code_flds[0]) inside {OTP_TERMINAL_ERRS}) begin + `uvm_info(`gfn, "terminal error cannot be updated", UVM_HIGH) + end else if (status_err_idx == OtpLciErrIdx && + `gmv(err_code_flds[0]) != OtpNoError) begin + `uvm_info(`gfn, "For LC partition, all errors are terminal error!", UVM_HIGH) + end else begin + void'(err_code_flds[0].predict(.value(err_code), .kind(UVM_PREDICT_READ))); + end + end + + endfunction + + virtual function void predict_no_err(otp_status_e status_err_idx); + if (cfg.otp_ctrl_vif.under_error_states()) return; + + exp_status[status_err_idx] = 0; + if (status_err_idx == OtpDaiErrIdx) exp_status[OtpDaiIdleIdx] = 1; + + if (status_err_idx <= OtpLciErrIdx) begin + dv_base_reg_field err_code_flds[$]; + ral.err_code[status_err_idx].get_dv_base_reg_fields(err_code_flds); + void'(err_code_flds[0].predict(OtpNoError)); + end + endfunction + + virtual function void predict_rdata(bit is_64_bits, bit [TL_DW-1:0] rdata0, + bit [TL_DW-1:0] rdata1 = 0); + void'(ral.direct_access_rdata[0].predict(.value(rdata0), .kind(UVM_PREDICT_READ))); + if (is_64_bits) begin + void'(ral.direct_access_rdata[1].predict(.value(rdata1), .kind(UVM_PREDICT_READ))); + end + endfunction + + // this function retrieves keys (128 bits) from scb's otp_array with a starting address + // if not locked, it will return 0 + // this is mainly used for scrambling key algo + virtual function bit [SCRAMBLE_KEY_SIZE-1:0] get_key_from_otp(bit locked, int start_i); + bit [SCRAMBLE_KEY_SIZE-1:0] key; + if (!locked) return 0; + for (int i = 0; i < 4; i++) key |= otp_a[i + start_i] << (TL_DW * i); + return key; + endfunction + + // The following two methods are all retrieving digest val. + // get_otp_digest_val: is the digest value from OTP memory + // get_digest_reg_val: is the digest value in register. This value is identical to OTP + // memory's digest value after a power cycle reset. + virtual function bit [TL_DW*2-1:0] get_otp_digest_val(int part_idx); + get_otp_digest_val[31:0] = otp_a[PART_OTP_DIGEST_ADDRS[part_idx]]; + get_otp_digest_val[63:32] = otp_a[PART_OTP_DIGEST_ADDRS[part_idx] + 1]; + endfunction + + virtual function bit [TL_DW*2-1:0] get_digest_reg_val(int part_idx); + bit [TL_DW*2-1:0] digest; + case (part_idx) +% for part in write_locked_digest_parts: +<% + part_name = Name.from_snake_case(part["name"]) + part_name_snake = part_name.as_snake_case() +%>\ + ${part_name.as_camel_case()}Idx: begin + digest = {`gmv(ral.${part_name_snake}_digest[1]), + `gmv(ral.${part_name_snake}_digest[0])}; + end +% endfor + default: `uvm_fatal(`gfn, $sformatf("Partition %0d does not have digest", part_idx)) + endcase + return digest; + endfunction + + virtual function bit is_tl_mem_access_allowed(input tl_seq_item item, input string ral_name, + output bit mem_byte_access_err, + output bit mem_wo_err, + output bit mem_ro_err, + output bit custom_err); + + uvm_reg_addr_t addr = cfg.ral_models[ral_name].get_word_aligned_addr(item.a_addr); + uvm_reg_addr_t csr_addr = cfg.ral_models[ral_name].get_word_aligned_addr(item.a_addr); + bit [TL_AW-1:0] addr_mask = ral.get_addr_mask(); + bit [TL_AW-1:0] dai_addr = (csr_addr & addr_mask - SW_WINDOW_BASE_ADDR); + + bit mem_access_allowed = super.is_tl_mem_access_allowed(item, ral_name, mem_byte_access_err, + mem_wo_err, mem_ro_err, custom_err); + + if (ral_name == "otp_ctrl_prim_reg_block") return mem_access_allowed; + + // Ensure the address is within the memory window range. + // Also will skip checking if memory access is not allowed due to TLUL bus error. + if (addr inside { + [cfg.ral_models[ral_name].mem_ranges[0].start_addr : + cfg.ral_models[ral_name].mem_ranges[0].end_addr]} && + mem_access_allowed) begin + + // If sw partition is read locked, then access policy changes from RO to no access +% for part in read_locked_csr_parts: +<% + part_name = Name.from_snake_case(part["name"]) + part_name_camel = part_name.as_camel_case() +%>\ + if (`gmv(ral.${part_name.as_snake_case()}_read_lock) == 0 || + cfg.otp_ctrl_vif.under_error_states()) begin + if (addr inside { + [cfg.ral_models[ral_name].mem_ranges[0].start_addr + ${part_name_camel}Offset : + cfg.ral_models[ral_name].mem_ranges[0].start_addr + ${part_name_camel}Offset + + ${part_name_camel}Size - 1]}) begin + predict_err(Otp${part_name_camel}ErrIdx, OtpAccessError); + custom_err = 1; + if (cfg.en_cov) begin + % if part["write_lock"] == "Digest": + cov.unbuf_access_lock_cg_wrap[${part_name_camel}Idx].sample(.read_lock(1), + .write_lock(get_digest_reg_val(${part_name_camel}Idx) != 0), .is_write(0)); + % else: + // TODO: we should probably create a different covergroup + // for unbuffered partitions without digest. + cov.unbuf_access_lock_cg_wrap[${part_name_camel}Idx].sample(.read_lock(1), + .write_lock(0), .is_write(0)); + % endif + end + return 0; + end + end +% endfor + + // Check ECC uncorrectable fatal error. + if (dai_addr < LifeCycleOffset) begin + int part_idx = get_part_index(dai_addr); + bit [TL_DW-1:0] read_out; + int ecc_err = read_a_word_with_ecc(dai_addr, read_out); + if (ecc_err == OtpEccUncorrErr && part_has_integrity(part_idx)) begin + predict_err(otp_status_e'(part_idx), OtpMacroEccUncorrError); + set_exp_alert("fatal_macro_error", 1, 20); + custom_err = 1; + return 0; + end + end + end + + return mem_access_allowed; + endfunction + + virtual function bit predict_tl_err(tl_seq_item item, tl_channels_e channel, string ral_name); + if (ral_name == "otp_ctrl_prim_reg_block" && + cfg.otp_ctrl_vif.lc_dft_en_i != lc_ctrl_pkg::On) begin + if (channel == DataChannel) begin + `DV_CHECK_EQ(item.d_error, 1, + $sformatf({"On interface %0s, TL item: %0s, access gated by lc_dft_en_i"}, + ral_name, item.sprint(uvm_default_line_printer))) + + // In data read phase, check d_data when d_error = 1. + if (item.d_error && (item.d_opcode == tlul_pkg::AccessAckData)) begin + check_tl_read_value_after_error(item, ral_name); + end + end + return 1; + end + return super.predict_tl_err(item, channel, ral_name); + endfunction + + virtual function void set_exp_alert(string alert_name, bit is_fatal = 0, int max_delay = 0); + exp_alert = alert_name == "fatal_check_error" ? OtpCheckAlert : OtpMacroAlert; + super.set_exp_alert(alert_name, is_fatal, max_delay); + endfunction + +endclass diff --git a/src/fuse_ctrl/data/otp_ctrl_smoke_vseq.sv.tpl b/src/fuse_ctrl/data/otp_ctrl_smoke_vseq.sv.tpl new file mode 100755 index 0000000..904ff45 --- /dev/null +++ b/src/fuse_ctrl/data/otp_ctrl_smoke_vseq.sv.tpl @@ -0,0 +1,255 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +${gen_comment} +<% +from topgen.lib import Name +%>\ +// smoke test vseq to walk through DAI states and request keys +`define PART_CONTENT_RANGE(i) ${"\\"} + {[PartInfo[``i``].offset : (PartInfo[``i``].offset + PartInfo[``i``].size - DIGEST_SIZE - 1)]} + +class otp_ctrl_smoke_vseq extends otp_ctrl_base_vseq; + `uvm_object_utils(otp_ctrl_smoke_vseq) + + `uvm_object_new + + rand bit do_req_keys, do_lc_trans; + rand bit access_locked_parts; + rand bit rand_wr, rand_rd, rd_sw_tlul_rd; + rand bit [TL_DW-1:0] dai_addr; + rand bit [TL_DW-1:0] wdata0, wdata1; + rand int num_dai_op; + rand otp_ctrl_part_pkg::part_idx_e part_idx; + rand bit check_regwen_val, check_trigger_regwen_val; + rand bit [TL_DW-1:0] check_timeout_val; + rand bit [1:0] check_trigger_val; + rand otp_ecc_err_e ecc_otp_err, ecc_chk_err; + + constraint no_access_err_c {access_locked_parts == 0;} + + // LC partition does not allow DAI access (the LC partition is always the last one) + constraint partition_index_c {part_idx inside {[0:LifeCycleIdx-1]};} + + constraint dai_wr_legal_addr_c { +% for part in otp_mmap.config["partitions"]: +<% + part_name = Name.from_snake_case(part["name"]) + part_name_camel = part_name.as_camel_case() +%>\ + if (part_idx == ${part_name_camel}Idx) + dai_addr inside `PART_CONTENT_RANGE(${part_name_camel}Idx); +% endfor + solve part_idx before dai_addr; + } + + constraint dai_wr_blank_addr_c { + dai_addr % 4 == 0; + if (PartInfo[part_idx].secret) dai_addr % 8 == 0; + } + + constraint num_trans_c { + if (cfg.smoke_test) { + num_trans == 1; + num_dai_op inside {[1:2]}; + } else { + num_trans inside {[1:2]}; + num_dai_op inside {[1:50]}; + } + } + + constraint regwens_c { + check_regwen_val dist {0 :/ 1, 1 :/ 9}; + check_trigger_regwen_val dist {0 :/ 1, 1 :/ 9}; + } + + constraint check_timeout_val_c { + check_timeout_val inside {0, [100_000:'1]}; + } + + constraint ecc_otp_err_c {ecc_otp_err == OtpNoEccErr;} + + constraint ecc_chk_err_c {ecc_chk_err == OtpNoEccErr;} + + constraint apply_reset_during_pwr_init_cycles_c { + apply_reset_during_pwr_init_cycles dist { + [1:5] :/ 4, + [6:2000] :/ 4, + [2001:4000] :/ 2}; + } + + virtual task dut_init(string reset_kind = "HARD"); + if (do_apply_reset) begin + lc_prog_blocking = 1; + super.dut_init(reset_kind); + csr_wr(ral.intr_enable, en_intr); + end + endtask + + virtual task pre_start(); + super.pre_start(); + num_dai_op.rand_mode(0); + check_lc_err(); + endtask + + virtual task check_lc_err(); + fork + forever begin + wait(cfg.otp_ctrl_vif.lc_prog_err == 1); + lc_prog_blocking = 0; + wait(lc_prog_blocking == 1); + end + join_none; + endtask + + task body(); + for (int i = 1; i <= num_trans; i++) begin + bit [TL_DW-1:0] tlul_val; + if (cfg.stop_transaction_generators()) break; + `uvm_info(`gfn, $sformatf("starting seq %0d/%0d", i, num_trans), UVM_LOW) + + // to avoid access locked OTP partions, issue reset and clear the OTP memory to all 0. + if (access_locked_parts == 0) begin + do_otp_ctrl_init = 1; + if (i > 1 && do_dut_init) dut_init(); + // after otp-init done, check status + cfg.clk_rst_vif.wait_clks(1); + if (!cfg.otp_ctrl_vif.lc_esc_on) begin + csr_rd_check(.ptr(ral.status.dai_idle), .compare_value(1)); + end + end + do_otp_ctrl_init = 0; + + `DV_CHECK_RANDOMIZE_FATAL(this) + // set consistency and integrity checks + csr_wr(ral.check_regwen, check_regwen_val); + csr_wr(ral.check_trigger_regwen, check_trigger_regwen_val); + csr_wr(ral.check_timeout, check_timeout_val); + trigger_checks(.val(check_trigger_val), .wait_done(1), .ecc_err(ecc_chk_err)); + + if (!$urandom_range(0, 9) && access_locked_parts) write_sw_rd_locks(); + + // Backdoor write mubi to values that are not true or false. + force_mubi_part_access(); + + if (do_req_keys && !cfg.otp_ctrl_vif.alert_reqs) begin + req_otbn_key(); + req_flash_addr_key(); + req_flash_data_key(); + req_all_sram_keys(); + end + if (do_lc_trans && !cfg.otp_ctrl_vif.alert_reqs) begin + req_lc_transition(do_lc_trans, lc_prog_blocking); + if (cfg.otp_ctrl_vif.lc_prog_req == 0) begin + for (int k = 0; k <= LciIdx; k++) begin + csr_rd(.ptr(ral.err_code[k]), .value(tlul_val)); + end + end + end + + for (int i = 0; i < num_dai_op; i++) begin + bit [TL_DW-1:0] rdata0, rdata1, backdoor_rd_val; + if (cfg.stop_transaction_generators()) break; + + `DV_CHECK_RANDOMIZE_FATAL(this) + // recalculate part_idx in case some test turn off constraint dai_wr_legal_addr_c + part_idx = part_idx_e'(get_part_index(dai_addr)); + `uvm_info(`gfn, $sformatf("starting dai access seq %0d/%0d with addr %0h in partition %0d", + i, num_dai_op, dai_addr, part_idx), UVM_HIGH) + + // OTP write via DAI + if (rand_wr && !digest_calculated[part_idx]) begin + dai_wr(dai_addr, wdata0, wdata1); + if (cfg.otp_ctrl_vif.lc_prog_req == 0) begin + for (int k = 0; k <= LciIdx; k++) begin + csr_rd(.ptr(ral.err_code[k]), .value(tlul_val)); + end + end + end + + // Inject ECC error. + if (ecc_otp_err != OtpNoEccErr && dai_addr < LifeCycleOffset) begin + `uvm_info(`gfn, $sformatf("Injecting ecc error %0d at 0x%x", ecc_otp_err, dai_addr), + UVM_HIGH) + backdoor_rd_val = backdoor_inject_ecc_err(dai_addr, ecc_otp_err); + end + + if (rand_rd) begin + // OTP read via DAI, check data in scb + dai_rd(dai_addr, rdata0, rdata1); + end + + // if write sw partitions, check tlul window + if (is_sw_part(dai_addr) && rd_sw_tlul_rd) begin + uvm_reg_addr_t tlul_addr = cfg.ral.get_addr_from_offset(get_sw_window_offset(dai_addr)); + // tlul error rsp is checked in scoreboard + do_otp_rd = 1; + tl_access(.addr(tlul_addr), .write(0), .data(tlul_val), .blocking(1), .check_rsp(0)); + end + + // Backdoor restore injected ECC error, but should not affect fatal alerts. + if (ecc_otp_err != OtpNoEccErr && dai_addr < LifeCycleOffset) begin + `uvm_info(`gfn, $sformatf("Injecting ecc error %0d at 0x%x", ecc_otp_err, dai_addr), + UVM_HIGH) + cfg.mem_bkdr_util_h.write32({dai_addr[TL_DW-3:2], 2'b00}, backdoor_rd_val); + // Wait for two lock cycles to make sure the local escalation error propagates to other + // patitions and err_code reg. + cfg.clk_rst_vif.wait_clks(2); + end + + // Random lock sw partitions + if (!$urandom_range(0, 9) && access_locked_parts) write_sw_rd_locks(); + if (!$urandom_range(0, 9) && access_locked_parts) write_sw_digests(); + if ($urandom_range(0, 1)) csr_rd(.ptr(ral.direct_access_regwen), .value(tlul_val)); + if ($urandom_range(0, 1)) csr_rd(.ptr(ral.status), .value(tlul_val)); + if (cfg.otp_ctrl_vif.lc_prog_req == 0) begin + for (int k = 0; k <= LciIdx; k++) begin + csr_rd(.ptr(ral.err_code[k]), .value(tlul_val)); + end + end + end + + // Read/write test access memory + otp_test_access(); + + // lock digests + `uvm_info(`gfn, "Trigger HW digest calculation", UVM_HIGH) + cal_hw_digests(); + if ($urandom_range(0, 1)) csr_rd(.ptr(ral.status), .value(tlul_val)); + + if (cfg.otp_ctrl_vif.lc_prog_req == 0) begin + for (int k = 0; k <= LciIdx; k++) begin + csr_rd(.ptr(ral.err_code[k]), .value(tlul_val)); + end + end + + if ($urandom_range(0, 1)) rd_digests(); + if (do_dut_init) dut_init(); + + // read and check digest in scb + rd_digests(); + + // send request to the interfaces again after partitions are locked + if (do_lc_trans && !cfg.otp_ctrl_vif.alert_reqs) begin + req_lc_transition(do_lc_trans, lc_prog_blocking); + if (cfg.otp_ctrl_vif.lc_prog_req == 0) begin + for (int k = 0; k <= LciIdx; k++) begin + csr_rd(.ptr(ral.err_code[k]), .value(tlul_val)); + end + end + end + + if (do_req_keys && !cfg.otp_ctrl_vif.alert_reqs && !cfg.smoke_test) begin + req_otbn_key(); + req_flash_addr_key(); + req_flash_data_key(); + req_all_sram_keys(); + end + + end + + endtask : body + +endclass : otp_ctrl_smoke_vseq + +`undef PART_CONTENT_RANGE diff --git a/src/fuse_ctrl/data/otp_ctrl_testplan.hjson b/src/fuse_ctrl/data/otp_ctrl_testplan.hjson new file mode 100644 index 0000000..95b6081 --- /dev/null +++ b/src/fuse_ctrl/data/otp_ctrl_testplan.hjson @@ -0,0 +1,404 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + name: "otp_ctrl" + import_testplans: ["hw/dv/tools/dvsim/testplans/csr_testplan.hjson", + "hw/dv/tools/dvsim/testplans/mem_testplan.hjson", + "hw/dv/tools/dvsim/testplans/intr_test_testplan.hjson", + "hw/dv/tools/dvsim/testplans/alert_test_testplan.hjson", + "hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson", + "hw/dv/tools/dvsim/testplans/sec_cm_count_testplan.hjson", + "hw/dv/tools/dvsim/testplans/sec_cm_fsm_testplan.hjson", + "hw/dv/tools/dvsim/testplans/stress_all_with_reset_testplan.hjson", + "otp_ctrl_sec_cm_testplan.hjson"] + testpoints: [ + { + name: wake_up + desc: ''' + Wake_up test walks through otp_ctrl's power-on initialization, read, program, and + digest functionalities. + + - drive pwrmgr's request pin to trigger OTP initialization after reset, check status + after OTP initialization + - write all-ones to a random address within OTP partition 0, wait until this operation + completes + - read out the random selected write address, check if the readout value is all-ones + - trigger a digest calculation for a Software partition, check if the OtpError + interrupt is set + - trigger a digest calculation for a non-software partition, expect operation completes + without the OtpError interrupt + - read out secrets through the hardware interfaces + ''' + stage: V1 + tests: ["otp_ctrl_wake_up"] + } + { + name: smoke + desc: ''' + OTP_CTRL smoke test provisions and locks partitions. + + - drive pwrmgr's request pin to trigger OTP initialization after reset, check status + after OTP initialization + - randomly read out keys pertaining to `key_manager`, `flash`, `sram`, `otbn` + - randomly issue LC program request + - write random values to random addresses within each OTP partition + - read out the random selected write addresses, check if the readout values are expected + - during read and write operations, check if direct_access_regwen is correctly set by HW + - perform a system-level reset and check corresponding CSRs are set correctly + - lock all partitions except life_cycle by triggering digest calculations + - read back and verify the digest + - perform a system-level reset to verify the corresponding CSRs exposing the digests + have been populated + + **Checks**: + - Assertion checks to ensure vendor specific I/Os: `otp_vendor_test_status_o`, + `otp_vendor_test_ctrl_i`, `cio_test_o`, and `cio_test_en_o` are connected currently + with `lc_dft_en_i` On and Off. + ''' + stage: V1 + tests: ["otp_ctrl_smoke"] + } + { + name: dai_access_partition_walk + desc: ''' + Similar to UVM's memory walk test, this test ensures every address in each partition + can be accessed successfully via DAI and TLUL interfacs according to its access policy. + ''' + stage: V2 + tests: ["otp_ctrl_partition_walk"] + } + { + name: init_fail + desc: ''' + Based on OTP_CTRL smoke test, this test creates OTP_CTRL's initialization failure: + - write and read OTP memory via DAI interface + - randomly issue DAI digest command to lock HW partitions + - keep writing to OTP memory via DAI interface without asserting reset + - if digests are not locked, backdoor inject ECC correctable or uncorrectable errors + - issue reset and power initialization + - if the injected errors are all correctable errors, disable the `lc_bypass_chk_en` + after LC program request to create an LC partition check failure + + If fatal error is triggered, this test will check: + - OTP initialization failure triggers fatal alert + - `status`, `intr_state`, `err_code` CSRs reflect correct fatal error + + If OTP initialization finished without any fatal error, this test will check: + - OTP initialization finishes with power init output goes to 1 + - `status`, `intr_state`, `err_code` CSRs reflect ECC correctable error + ''' + stage: V2 + tests: ["otp_ctrl_init_fail"] + } + { + name: partition_check + desc: ''' + Randomly program the partition check related CSRs including: + - `check_timeout` + - `integrity_check_period` + - `consistency_check_period` + - `check_trigger` + + Create a failure scenario by randomly picking one of these three methods: + - inject ECC errors into the OTP macro via backdoor + - set the `check_timeout` CSR with a very small value + - write to a random OTP partition after digest is issued but before reset is asserted + + **Checks**: + - the corresponding alerts are triggered + - the error_code register is set correctly + Note that due to limited simulation time, for background checks, this test only write + random value that is less than 20 to the check period. + ''' + stage: V2 + tests: ["otp_ctrl_check_fail", "otp_ctrl_background_chks"] + } + { + name: regwen_during_otp_init + desc: ''' + The `direct_access_regwen` is a RO register which controls the write-enable of other + reigsters. It is not verified by the common CSR tests. HW sets it to 0 when the DAI + interface is busy. + + Stimulus and checks: + - randomly read `direct_access_regwen` and verify that it returns 0 during OTP + initialization + - verify that the writes to the registers controlled by it do not go through during OTP + initialization + ''' + stage: V2 + tests: ["otp_ctrl_regwen"] + } + { + name: partition_lock + desc: ''' + This test will cover two methods of locking read and write: digest calculation and CSR + write. After locking the partitions, issue read or program sequences and check if the + operations are locked correctly, and check if the `AccessError` is set. + ''' + stage: V2 + tests: ["otp_ctrl_dai_lock"] + } + { + name: interface_key_check + desc: ''' + OTP_CTRL will generate keys to `flash`, `sram`, and `otbn` upon their requests. + Based on the DAI access sequence, this test will run key requests sequence in + parallel, and check if correct keys are generated. + ''' + stage: V2 + tests: ["otp_ctrl_parallel_key_req"] + } + { + name: lc_interactions + desc: ''' + Verify the procotols between OTP_CTRL and LC_CTRL. Based on the DAI access sequence, + run the following sequences in parallel: + + - request a LC state transition via the programming interface + - enable the `lc_escalation_en` signal + + **Checks**: + - if the LC program request has `AccessError`, check the LC program response sets + the `error` bit to 1 + - if `lc_escalation_en` is enabled, verify that alert is triggered and OTP_CTRL entered + terminal state + ''' + stage: V2 + tests: ["otp_ctrl_parallel_lc_req", "otp_ctrl_parallel_lc_esc"] + } + { name: otp_dai_errors + desc: ''' + Based on the otp_dai_lock test, this test will randomly run the following OTP errors: + - DAI interface writes non-blank OTP address + - DAI interface accesses LC partition + - DAI interface writes HW digests + - DAI interface writes non-empty memory + + **Checks**: + - `err_code` and `status` CSRs + - `otp_error` interrupt + ''' + stage: V2 + tests: ["otp_ctrl_dai_errs"] + } + { name: otp_macro_errors + desc: ''' + Randomly run the following OTP errors: + - MacroError + - MacroEccCorrError + - MacroEccUncorrError + + **Checks**: + - `err_code` and `status` CSRs + - `otp_error` interrupt + - if the error is unrecoverable, verify that alert is triggered and OTP_CTRL entered + terminal state + ''' + stage: V2 + tests: ["otp_ctrl_macro_errs"] + } + { + name: test_access + desc: ''' + This test checks if the test access to OTP macro is connected correctly. + + **Stimulus and Checks**: + - Write and check read results from the prim_tl_i/o. + - Ensure no error or alert occurs from DUT. + ''' + stage: V2 + tests: ["otp_ctrl_test_access"] + } + { + name: stress_all + desc: ''' + - combine above sequences in one test to run sequentially, except csr sequence + - randomly add reset between each sequence + ''' + stage: V2 + tests: ["{name}_stress_all"] + } + { + name: sec_cm_additional_check + desc: ''' + Verify the outcome of injecting faults to security countermeasures. + + Stimulus: + As mentioned in `prim_count_check`, `prim_fsm_check` and `prim_double_lfsr_check`. + + Checks: + - Check the value of status register according to where the fault is injected. + - Check OTP_CTRL is locked after the fatal fault injection by trying to access OTP_CTRL + via dai, kdi, and lci interfaces. + ''' + stage: V2S + tests: ["otp_ctrl_sec_cm"] + } + { + name: otp_ctrl_low_freq_read + desc: ''' + This test checks if OTP's read operation can operate successfully in a low clock + frequency before the clock is calibrated. + + **Stimulus and Checks**: + - Configure OTP_CTRL's clock to 6MHz low frequency. + - Backdoor write OTP memory. + - Use DAI access to read each memory address and compare if the value is correct. + - If DAI address is in a SW partition, read and check again via TLUL interface. + ''' + stage: V3 + tests: ["otp_ctrl_low_freq_read"] + } + ] + + covergroups: [ + { + name: power_on_cg + desc: '''Covers the following conditions when OTP_CTRL finishes power-on initialization: + - whether `lc_escalation_en` is On + - whether any partition (except life cycle partition) is locked + ''' + } + { + name: flash_req_cg + desc: '''Covers whether secret1 partition is locked during `flash` data or address + request.''' + } + { + name: sram_req_cg + desc: '''Covers whether secret1 partition is locked during all `srams` key request.''' + } + { + name: otbn_req_cg + desc: '''Covers whether secret1 partition is locked during `otbn` key request.''' + } + { + name: lc_prog_cg + desc: '''Covers whether the error bit is set during LC program request.''' + } + { + name: keymgr_o_cg + desc: '''Covers the following conditions when scoreboard checks `keymgr_o` value: + - whether secret2 partition is locked + - whether `lc_seed_hw_rd_en_i` is On + ''' + } + { + name: req_dai_access_after_alert_cg + desc: '''Covers if sequence issued various DAI requests after any fatal alert is + triggered.''' + } + { + name: issue_checks_after_alert_cg + desc: '''Covers if sequence issued various OTP_CTRL's background checks after any fatal alert + is triggered.''' + } + { + name: csr_rd_after_alert_cg + desc: '''Covers if the following CSRs are being read and the value is checked in scoreboard + after any fatal alert is triggered: + - unbuffered partitions' digest CSRs + - HW partition's digest CSRs + - secrets partitions' digest CSRs + - direct_access read data CSRs + - status CSR + - error_code CSR + ''' + } + { + name: dai_err_code_cg + desc: '''Covers all applicable error codes in DAI, and cross each error code with all + 7 partitions.''' + } + { + name: lci_err_code_cg + desc: '''Covers all applicable error codes in LCI.''' + } + { + name: unbuf_err_code_cg + desc: '''This is an array of covergroups to cover all applicable error codes in three + unbuffered partitions.''' + } + { + name: buf_err_code_cg + desc: '''This is an array of covergroups to cover all applicable error codes in five + buffered partitions.''' + } + { + name: unbuf_access_lock_cg_wrap_cg + desc: '''This is an array of covergroups to cover lock conditions below in three + unbuffered partitions: + - the partition is write-locked + - the partition is read-locked + - the current operation type + Then cross the three coverpoints.''' + } + { + name: dai_access_secret2_cg + desc: '''Covers whether `lc_creator_seed_sw_rw_en` is On during any DAI accesses.''' + } + { + name: status_csr_cg + desc: '''Covers the value of every bit in `status` CSR.''' + } + // The following covergroups are implemented in `otp_ctrl_cov_if.sv`. + { + name: lc_esc_en_condition_cg + desc: '''Covers the following conditions when `lc_escalation_en` is On: + - whether any key requests is in progress + - whether LC program reqeust is in progress + - whether DAI interface is busy + ''' + } + { + name: flash_data_req_condition_cg + desc: '''Covers the following conditions when `lc_escalation_en` is On: + - whether any key requests is in progress + - whether DAI interface is busy + - whether lc_esc_en is On + ''' + } + { + name: flash_addr_req_condition_cg + desc: '''Covers the following conditions when `lc_escalation_en` is On: + - whether any key requests is in progress + - whether DAI interface is busy + - whether lc_esc_en is On + ''' + } + { + name: sram_0_req_condition_cg + desc: '''Covers the following conditions when `lc_escalation_en` is On: + - whether any key requests is in progress + - whether DAI interface is busy + - whether lc_esc_en is On + ''' + } + { + name: sram_1_req_condition_cg + desc: '''Covers the following conditions when `lc_escalation_en` is On: + - whether any key requests is in progress + - whether DAI interface is busy + - whether lc_esc_en is On + ''' + } + { + name: otbn_req_condition_cg + desc: '''Covers the following conditions when `lc_escalation_en` is On: + - whether any key requests is in progress + - whether DAI interface is busy + - whether lc_esc_en is On + ''' + } + { + name: lc_prog_req_condition_cg + desc: '''Covers the following conditions when `lc_escalation_en` is On: + - whether any key requests is in progress + - whether DAI interface is busy + - whether lc_esc_en is On + ''' + } + ] +} diff --git a/src/fuse_ctrl/data/output.txt b/src/fuse_ctrl/data/output.txt new file mode 100644 index 0000000..49e060d --- /dev/null +++ b/src/fuse_ctrl/data/output.txt @@ -0,0 +1,215 @@ +otp_ctrl.json +{'MemInitFile': '""', 'NumSramKeyReqSlots': '4', 'OtpByteAddrWidth': '12', 'NumErrorEntries': '9', 'NumDaiWords': '2', 'NumDigestWords': '2', 'NumSwCfgWindowWords': '1024', 'NumPart': '7', 'NumPartUnbuf': '2', 'NumPartBuf': '5', 'VendorTestOffset': '0', 'VendorTestSize': '64', 'ScratchOffset': '0', 'ScratchSize': '56', 'VendorTestDigestOffset': '56', 'VendorTestDigestSize': '8', 'NonSecretFusesOffset': '64', 'NonSecretFusesSize': '3736', 'FmcKeyManifestSvnOffset': '64', 'FmcKeyManifestSvnSize': '4', 'RuntimeSvnOffset': '68', 'RuntimeSvnSize': '16', 'LmsVerifyOffset': '84', 'LmsVerifySize': '4', 'LmsRevocationOffset': '88', 'LmsRevocationSize': '4', 'KeyManifestPkHashMaskOffset': '92', 'KeyManifestPkHashMaskSize': '4', 'OwnerPkHashOffset': '96', 'OwnerPkHashSize': '48', 'IdevidCertAttrOffset': '144', 'IdevidCertAttrSize': '96', 'IdevidManufHsmIdOffset': '240', 'IdevidManufHsmIdSize': '16', 'SocSteppingIdOffset': '256', 'SocSteppingIdSize': '4', 'NonSecretFusesDigestOffset': '3792', 'NonSecretFusesDigestSize': '8', 'Secret0Offset': '3800', 'Secret0Size': '40', 'TestUnlockTokenOffset': '3800', 'TestUnlockTokenSize': '16', 'TestExitTokenOffset': '3816', 'TestExitTokenSize': '16', 'Secret0DigestOffset': '3832', 'Secret0DigestSize': '8', 'Secret1Offset': '3840', 'Secret1Size': '56', 'UdsSeedOffset': '3840', 'UdsSeedSize': '48', 'Secret1DigestOffset': '3888', 'Secret1DigestSize': '8', 'Secret2Offset': '3896', 'Secret2Size': '40', 'FieldEntropyOffset': '3896', 'FieldEntropySize': '32', 'Secret2DigestOffset': '3928', 'Secret2DigestSize': '8', 'Secret3Offset': '3936', 'Secret3Size': '72', 'KeyManifestPkHashOffset': '3936', 'KeyManifestPkHashSize': '48', 'RmaTokenOffset': '3984', 'RmaTokenSize': '16', 'Secret3DigestOffset': '4000', 'Secret3DigestSize': '8', 'LifeCycleOffset': '4008', 'LifeCycleSize': '88', 'LcTransitionCntOffset': '4008', 'LcTransitionCntSize': '48', 'LcStateOffset': '4056', 'LcStateSize': '40'} +Register: INTERRUPT_STATE Address: 0x0 +Next Address coming up: 0x4 +Register: INTERRUPT_ENABLE Address: 0x4 +Next Address coming up: 0x8 +Register: INTERRUPT_TEST Address: 0x8 +Next Address coming up: 0xC +Register: ALERT_TEST Address: 0xC +Next Address coming up: 0x10 +Number of registers is 21 +core +Register: STATUS Address: 0x10 +Reg Name: STATUS Address: 0x10 +Next Address coming up: 0x14 +In decode_addrmap, calling decode_multireg. Addr = 0x14 +DEBUG: MULTIREG +Address offset = 14 +Register: ERR_CODE_0 Address: 0x14 +Reg Name: ERR_CODE_0 Address: 0x14 +Register: ERR_CODE_1 Address: 0x18 +Reg Name: ERR_CODE_1 Address: 0x18 +Register: ERR_CODE_2 Address: 0x1C +Reg Name: ERR_CODE_2 Address: 0x1C +Register: ERR_CODE_3 Address: 0x20 +Reg Name: ERR_CODE_3 Address: 0x20 +Register: ERR_CODE_4 Address: 0x24 +Reg Name: ERR_CODE_4 Address: 0x24 +Register: ERR_CODE_5 Address: 0x28 +Reg Name: ERR_CODE_5 Address: 0x28 +Register: ERR_CODE_6 Address: 0x2C +Reg Name: ERR_CODE_6 Address: 0x2C +Register: ERR_CODE_7 Address: 0x30 +Reg Name: ERR_CODE_7 Address: 0x30 +Register: ERR_CODE_8 Address: 0x34 +Reg Name: ERR_CODE_8 Address: 0x34 +Instance name: ERR_CODE +Array Stride: None +Addr Offset: 0x14 +Is Array: False +Num Array Elements: 1 +False +Next Address coming up: 0x38 +Register: DIRECT_ACCESS_REGWEN Address: 0x38 +Reg Name: DIRECT_ACCESS_REGWEN Address: 0x38 +Next Address coming up: 0x3C +Register: DIRECT_ACCESS_CMD Address: 0x3C +Reg Name: DIRECT_ACCESS_CMD Address: 0x3C +Next Address coming up: 0x40 +Register: DIRECT_ACCESS_ADDRESS Address: 0x40 +Reg Name: DIRECT_ACCESS_ADDRESS Address: 0x40 +Next Address coming up: 0x44 +In decode_addrmap, calling decode_multireg. Addr = 0x44 +DEBUG: MULTIREG +Address offset = 44 +Register: DIRECT_ACCESS_WDATA_0 Address: 0x44 +Reg Name: DIRECT_ACCESS_WDATA_0 Address: 0x44 +Register: DIRECT_ACCESS_WDATA_1 Address: 0x48 +Reg Name: DIRECT_ACCESS_WDATA_1 Address: 0x48 +Instance name: DIRECT_ACCESS_WDATA +Array Stride: None +Addr Offset: 0x44 +Is Array: False +Num Array Elements: 1 +False +Next Address coming up: 0x4C +In decode_addrmap, calling decode_multireg. Addr = 0x4C +DEBUG: MULTIREG +Address offset = 4C +Register: DIRECT_ACCESS_RDATA_0 Address: 0x4C +Reg Name: DIRECT_ACCESS_RDATA_0 Address: 0x4C +Register: DIRECT_ACCESS_RDATA_1 Address: 0x50 +Reg Name: DIRECT_ACCESS_RDATA_1 Address: 0x50 +Instance name: DIRECT_ACCESS_RDATA +Array Stride: None +Addr Offset: 0x4C +Is Array: False +Num Array Elements: 1 +False +Next Address coming up: 0x54 +Register: CHECK_TRIGGER_REGWEN Address: 0x54 +Reg Name: CHECK_TRIGGER_REGWEN Address: 0x54 +Next Address coming up: 0x58 +Register: CHECK_TRIGGER Address: 0x58 +Reg Name: CHECK_TRIGGER Address: 0x58 +Next Address coming up: 0x5C +Register: CHECK_REGWEN Address: 0x5C +Reg Name: CHECK_REGWEN Address: 0x5C +Next Address coming up: 0x60 +Register: CHECK_TIMEOUT Address: 0x60 +Reg Name: CHECK_TIMEOUT Address: 0x60 +Next Address coming up: 0x64 +Register: INTEGRITY_CHECK_PERIOD Address: 0x64 +Reg Name: INTEGRITY_CHECK_PERIOD Address: 0x64 +Next Address coming up: 0x68 +Register: CONSISTENCY_CHECK_PERIOD Address: 0x68 +Reg Name: CONSISTENCY_CHECK_PERIOD Address: 0x68 +Next Address coming up: 0x6C +Register: VENDOR_TEST_READ_LOCK Address: 0x6C +Reg Name: VENDOR_TEST_READ_LOCK Address: 0x6C +Next Address coming up: 0x70 +Register: NON_SECRET_FUSES_READ_LOCK Address: 0x70 +Reg Name: NON_SECRET_FUSES_READ_LOCK Address: 0x70 +Next Address coming up: 0x74 +In decode_addrmap, calling decode_multireg. Addr = 0x74 +DEBUG: MULTIREG +Address offset = 74 +Register: VENDOR_TEST_DIGEST_0 Address: 0x74 +Reg Name: VENDOR_TEST_DIGEST_0 Address: 0x74 +Register: VENDOR_TEST_DIGEST_1 Address: 0x78 +Reg Name: VENDOR_TEST_DIGEST_1 Address: 0x78 +Instance name: VENDOR_TEST_DIGEST +Array Stride: None +Addr Offset: 0x74 +Is Array: False +Num Array Elements: 1 +False +Next Address coming up: 0x7C +In decode_addrmap, calling decode_multireg. Addr = 0x7C +DEBUG: MULTIREG +Address offset = 7C +Register: NON_SECRET_FUSES_DIGEST_0 Address: 0x7C +Reg Name: NON_SECRET_FUSES_DIGEST_0 Address: 0x7C +Register: NON_SECRET_FUSES_DIGEST_1 Address: 0x80 +Reg Name: NON_SECRET_FUSES_DIGEST_1 Address: 0x80 +Instance name: NON_SECRET_FUSES_DIGEST +Array Stride: None +Addr Offset: 0x7C +Is Array: False +Num Array Elements: 1 +False +Next Address coming up: 0x84 +In decode_addrmap, calling decode_multireg. Addr = 0x84 +DEBUG: MULTIREG +Address offset = 84 +Register: SECRET0_DIGEST_0 Address: 0x84 +Reg Name: SECRET0_DIGEST_0 Address: 0x84 +Register: SECRET0_DIGEST_1 Address: 0x88 +Reg Name: SECRET0_DIGEST_1 Address: 0x88 +Instance name: SECRET0_DIGEST +Array Stride: None +Addr Offset: 0x84 +Is Array: False +Num Array Elements: 1 +False +Next Address coming up: 0x8C +In decode_addrmap, calling decode_multireg. Addr = 0x8C +DEBUG: MULTIREG +Address offset = 8C +Register: SECRET1_DIGEST_0 Address: 0x8C +Reg Name: SECRET1_DIGEST_0 Address: 0x8C +Register: SECRET1_DIGEST_1 Address: 0x90 +Reg Name: SECRET1_DIGEST_1 Address: 0x90 +Instance name: SECRET1_DIGEST +Array Stride: None +Addr Offset: 0x8C +Is Array: False +Num Array Elements: 1 +False +Next Address coming up: 0x94 +In decode_addrmap, calling decode_multireg. Addr = 0x94 +DEBUG: MULTIREG +Address offset = 94 +Register: SECRET2_DIGEST_0 Address: 0x94 +Reg Name: SECRET2_DIGEST_0 Address: 0x94 +Register: SECRET2_DIGEST_1 Address: 0x98 +Reg Name: SECRET2_DIGEST_1 Address: 0x98 +Instance name: SECRET2_DIGEST +Array Stride: None +Addr Offset: 0x94 +Is Array: False +Num Array Elements: 1 +False +Next Address coming up: 0x9C +In decode_addrmap, calling decode_multireg. Addr = 0x9C +DEBUG: MULTIREG +Address offset = 9C +Register: SECRET3_DIGEST_0 Address: 0x9C +Reg Name: SECRET3_DIGEST_0 Address: 0x9C +Register: SECRET3_DIGEST_1 Address: 0xA0 +Reg Name: SECRET3_DIGEST_1 Address: 0xA0 +Instance name: SECRET3_DIGEST +Array Stride: None +Addr Offset: 0x9C +Is Array: False +Num Array Elements: 1 +False +Next Address coming up: 0xA4 +Number of registers is 8 +prim +Register: CSR0 Address: 0xA4 +Reg Name: CSR0 Address: 0xA4 +Next Address coming up: 0xA8 +Register: CSR1 Address: 0xA8 +Reg Name: CSR1 Address: 0xA8 +Next Address coming up: 0xAC +Register: CSR2 Address: 0xAC +Reg Name: CSR2 Address: 0xAC +Next Address coming up: 0xB0 +Register: CSR3 Address: 0xB0 +Reg Name: CSR3 Address: 0xB0 +Next Address coming up: 0xB4 +Register: CSR4 Address: 0xB4 +Reg Name: CSR4 Address: 0xB4 +Next Address coming up: 0xB8 +Register: CSR5 Address: 0xB8 +Reg Name: CSR5 Address: 0xB8 +Next Address coming up: 0xBC +Register: CSR6 Address: 0xBC +Reg Name: CSR6 Address: 0xBC +Next Address coming up: 0xC0 +Register: CSR7 Address: 0xC0 +Reg Name: CSR7 Address: 0xC0 +Next Address coming up: 0xC4 +Compilation or elaboration error: Elaborate aborted due to previous errors diff --git a/src/fuse_ctrl/doc/otp_ctrl_digests.md b/src/fuse_ctrl/doc/otp_ctrl_digests.md new file mode 100755 index 0000000..3ba3ba8 --- /dev/null +++ b/src/fuse_ctrl/doc/otp_ctrl_digests.md @@ -0,0 +1,12 @@ + + +| Digest Name | Affected Partition | Calculated by HW | +|:---------------------------------------------------------:|:---------------------:|:------------------:| +| [VENDOR_TEST_DIGEST](#Reg_vendor_test_digest_0) | VENDOR_TEST | no | +| [NON_SECRET_FUSES_DIGEST](#Reg_non_secret_fuses_digest_0) | NON_SECRET_FUSES | no | +| [SECRET0_DIGEST](#Reg_secret0_digest_0) | SECRET0 | yes | +| [SECRET1_DIGEST](#Reg_secret1_digest_0) | SECRET1 | yes | +| [SECRET2_DIGEST](#Reg_secret2_digest_0) | SECRET2 | yes | diff --git a/src/fuse_ctrl/doc/otp_ctrl_mmap.md b/src/fuse_ctrl/doc/otp_ctrl_mmap.md new file mode 100755 index 0000000..6ec2c0f --- /dev/null +++ b/src/fuse_ctrl/doc/otp_ctrl_mmap.md @@ -0,0 +1,27 @@ + + +| Index | Partition | Size [B] | Access Granule | Item | Byte Address | Size [B] | +|:-------:|:----------------:|:----------:|:----------------:|:---------------------------------------------------------:|:--------------:|:----------:| +| 0 | VENDOR_TEST | 64 | 32bit | SCRATCH | 0x000 | 56 | +| | | | 64bit | [VENDOR_TEST_DIGEST](#Reg_vendor_test_digest_0) | 0x038 | 8 | +| 1 | NON_SECRET_FUSES | 3792 | 32bit | FMC_KEY_MANIFEST_SVN | 0x040 | 4 | +| | | | 32bit | RUNTIME_SVN | 0x044 | 16 | +| | | | 32bit | LMS_VERIFY | 0x054 | 4 | +| | | | 32bit | LMS_REVOCATION | 0x058 | 4 | +| | | | 32bit | KEY_MANIFEST_PK_HASH_MASK | 0x05C | 4 | +| | | | 32bit | OWNER_PK_HASH | 0x060 | 48 | +| | | | 32bit | IDEVID_CERT_ATTR | 0x090 | 96 | +| | | | 32bit | IDEVID_MANUF_HSM_ID | 0x0F0 | 16 | +| | | | 32bit | SOC_STEPPING_ID | 0x100 | 4 | +| | | | 64bit | [NON_SECRET_FUSES_DIGEST](#Reg_non_secret_fuses_digest_0) | 0xF08 | 8 | +| 2 | SECRET0 | 56 | 64bit | UDS_SEED | 0xF10 | 48 | +| | | | 64bit | [SECRET0_DIGEST](#Reg_secret0_digest_0) | 0xF40 | 8 | +| 3 | SECRET1 | 40 | 64bit | FIELD_ENTROPY | 0xF48 | 32 | +| | | | 64bit | [SECRET1_DIGEST](#Reg_secret1_digest_0) | 0xF68 | 8 | +| 4 | SECRET2 | 56 | 64bit | KEY_MANIFEST_PK_HASH | 0xF70 | 48 | +| | | | 64bit | [SECRET2_DIGEST](#Reg_secret2_digest_0) | 0xFA0 | 8 | +| 5 | LIFE_CYCLE | 88 | 32bit | LC_TRANSITION_CNT | 0xFA8 | 48 | +| | | | 32bit | LC_STATE | 0xFD8 | 40 | diff --git a/src/fuse_ctrl/doc/otp_ctrl_partitions.md b/src/fuse_ctrl/doc/otp_ctrl_partitions.md new file mode 100755 index 0000000..f869834 --- /dev/null +++ b/src/fuse_ctrl/doc/otp_ctrl_partitions.md @@ -0,0 +1,31 @@ + + +| Partition | Secret | Buffered | Integrity | WR Lockable | RD Lockable | Description | +|:----------------:|:--------:|:----------:|:-----------:|:-------------:|:-------------:|:--------------------------------------------------------------------| +| VENDOR_TEST | no | no | no | yes (Digest) | yes (CSR) | Vendor test partition. | +| | | | | | | This is reserved for manufacturing smoke checks. The OTP wrapper | +| | | | | | | control logic inside prim_otp is allowed to read/write to this | +| | | | | | | region. ECC uncorrectable errors seen on the functional prim_otp | +| | | | | | | interface will not lead to an alert for this partition. | +| | | | | | | Instead, such errors will be reported as correctable ECC errors. | +| NON_SECRET_FUSES | no | no | yes | yes (Digest) | yes (CSR) | Non Secret Fuses partition. | +| | | | | | | This contains data such IDEVID, public key hash mask, owner | +| | | | | | | key hash, SoC Stepping ID etc. | +| SECRET0 | yes | yes | yes | yes (Digest) | yes (Digest) | Secret partition 0. | +| | | | | | | This contains Obfuscated UDS seed. | +| SECRET1 | yes | yes | yes | yes (Digest) | yes (Digest) | Secret partition 1. | +| | | | | | | This contains obfuscated field entropy. | +| SECRET2 | yes | yes | yes | yes (Digest) | yes (Digest) | Secret partition 2. | +| | | | | | | This contains public key hash. | +| LIFE_CYCLE | no | yes | yes | no | no | Lifecycle partition. | +| | | | | | | This contains lifecycle transition count and state. This partition | +| | | | | | | cannot be locked since the life cycle state needs to advance to RMA | +| | | | | | | in-field. Note that while this partition is not marked secret, it | +| | | | | | | is not readable nor writeable via the DAI. Only the LC controller | +| | | | | | | can access this partition, and even via the LC controller it is not | +| | | | | | | possible to read the raw manufacturing life cycle state in encoded | +| | | | | | | form, since that encoding is considered a netlist secret. The LC | +| | | | | | | controller only exposes a decoded version of this state. | diff --git a/src/fuse_ctrl/dv/cov/otp_ctrl_cov.core b/src/fuse_ctrl/dv/cov/otp_ctrl_cov.core new file mode 100755 index 0000000..361da46 --- /dev/null +++ b/src/fuse_ctrl/dv/cov/otp_ctrl_cov.core @@ -0,0 +1,24 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:dv:otp_ctrl_cov" +description: "OTP_CTRL functional coverage and bind files" +filesets: + files_rtl: + depend: + - lowrisc:ip:otp_ctrl + + files_dv: + depend: + - lowrisc:dv:dv_utils + files: + - otp_ctrl_cov_if.sv + - otp_ctrl_cov_bind.sv + file_type: systemVerilogSource + +targets: + default: + filesets: + - files_rtl + - files_dv diff --git a/src/fuse_ctrl/dv/cov/otp_ctrl_cov_bind.sv b/src/fuse_ctrl/dv/cov/otp_ctrl_cov_bind.sv new file mode 100755 index 0000000..fa69309 --- /dev/null +++ b/src/fuse_ctrl/dv/cov/otp_ctrl_cov_bind.sv @@ -0,0 +1,81 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Binds OTP_CTRL functional coverage interaface to the top level OTP_CTRL module. +// +// DO NOT EDIT THIS FILE DIRECTLY. +// It has been generated with ./util/design/gen-otp-mmap.py + +`define PART_MUBI_COV(__part_name, __index) \ + bind otp_ctrl cip_mubi_cov_if #(.Width(8)) ``__part_name``_read_lock_mubi_cov_if ( \ + .rst_ni (rst_ni), \ + .mubi (part_access[``__index``].read_lock) \ + ); \ + bind otp_ctrl cip_mubi_cov_if #(.Width(8)) ``__part_name``_write_lock_mubi_cov_if ( \ + .rst_ni (rst_ni), \ + .mubi (part_access[``__index``].write_lock) \ + ); + +`define DAI_MUBI_COV(__part_name, __index) \ + bind otp_ctrl cip_mubi_cov_if #(.Width(8)) dai_``__part_name``_read_lock_mubi_cov_if ( \ + .rst_ni (rst_ni), \ + .mubi (part_access_dai[``__index``].read_lock) \ + ); \ + bind otp_ctrl cip_mubi_cov_if #(.Width(8)) dai_``__part_name``_write_lock_mubi_cov_if ( \ + .rst_ni (rst_ni), \ + .mubi (part_access_dai[``__index``].write_lock) \ + ); + +module otp_ctrl_cov_bind; + import otp_ctrl_part_pkg::*; + + bind otp_ctrl otp_ctrl_cov_if u_otp_ctrl_cov_if ( + .pwr_otp_o (pwr_otp_o), + .lc_otp_program_i (lc_otp_program_i), + .lc_escalate_en_i (lc_escalate_en_i), + .flash_otp_key_i (flash_otp_key_i), + .sram_otp_key_i (sram_otp_key_i), + .otbn_otp_key_i (otbn_otp_key_i) + ); + + bind otp_ctrl cip_lc_tx_cov_if u_lc_creator_seed_sw_rw_en_cov_if ( + .rst_ni (rst_ni), + .val (lc_creator_seed_sw_rw_en_i) + ); + + bind otp_ctrl cip_lc_tx_cov_if u_lc_seed_hw_rd_en_cov_if ( + .rst_ni (rst_ni), + .val (lc_seed_hw_rd_en_i) + ); + + bind otp_ctrl cip_lc_tx_cov_if u_lc_dft_en_cov_if ( + .rst_ni (rst_ni), + .val (lc_dft_en_i) + ); + + bind otp_ctrl cip_lc_tx_cov_if u_lc_escalate_en_cov_if ( + .rst_ni (rst_ni), + .val (lc_escalate_en_i) + ); + + bind otp_ctrl cip_lc_tx_cov_if u_lc_check_byp_en_cov_if ( + .rst_ni (rst_ni), + .val (lc_check_byp_en_i) + ); + + // Mubi internal coverage for buffered and unbuffered partitions. + `PART_MUBI_COV(vendor_test, otp_ctrl_part_pkg::VendorTestIdx) + `PART_MUBI_COV(non_secret_fuses, otp_ctrl_part_pkg::NonSecretFusesIdx) + `PART_MUBI_COV(secret0, otp_ctrl_part_pkg::Secret0Idx) + `PART_MUBI_COV(secret1, otp_ctrl_part_pkg::Secret1Idx) + + // Mubi internal coverage for DAI interface access + `DAI_MUBI_COV(vendor_test, otp_ctrl_part_pkg::VendorTestIdx) + `DAI_MUBI_COV(non_secret_fuses, otp_ctrl_part_pkg::NonSecretFusesIdx) + `DAI_MUBI_COV(secret0, otp_ctrl_part_pkg::Secret0Idx) + `DAI_MUBI_COV(secret1, otp_ctrl_part_pkg::Secret1Idx) + +`undef PART_MUBI_COV +`undef DAI_MUBI_COV +endmodule diff --git a/src/fuse_ctrl/dv/cov/otp_ctrl_cov_fsm_unr_excl.el b/src/fuse_ctrl/dv/cov/otp_ctrl_cov_fsm_unr_excl.el new file mode 100755 index 0000000..1c3412b --- /dev/null +++ b/src/fuse_ctrl/dv/cov/otp_ctrl_cov_fsm_unr_excl.el @@ -0,0 +1,199 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// The current UNR flow marks some transition to reset states as unreachable. +// This file manually removed the reset transition states. +//================================================== +// This file contains the Excluded objects +// Generated By User: chencindy +// Format Version: 2 +// Date: Fri Jan 6 11:14:02 2023 +// ExclMode: default +//================================================== +CHECKSUM: "2063559012 2582220255" +INSTANCE: tb.dut.gen_partitions[3].gen_buffered.u_part_buf +Fsm state_q "441128463" +Transition IntegDigClrSt->IdleSt "2625->1357" +Fsm state_q "441128463" +Transition IntegDigSt->IntegDigFinSt "1890->1765" +Fsm state_q "441128463" +Transition CnstyReadWaitSt->CnstyReadSt "2684->107" +Fsm state_q "441128463" +State InitDescrWaitSt "2472" +Fsm state_q "441128463" +State IntegScrSt "3418" +Fsm state_q "441128463" +State IntegScrWaitSt "2207" +Fsm state_q "441128463" +State InitDescrSt "3204" +Fsm error_q "2410907799" +Transition CheckFailError->MacroEccCorrError "6->2" +Fsm error_q "2410907799" +Transition FsmStateError->CheckFailError "7->6" +Fsm error_q "2410907799" +Transition FsmStateError->MacroEccCorrError "7->2" +Fsm error_q "2410907799" +Transition CheckFailError->FsmStateError "6->7" +CHECKSUM: "2063559012 2582220255" +INSTANCE: tb.dut.gen_partitions[4].gen_buffered.u_part_buf +Fsm state_q "441128463" +Transition CnstyReadWaitSt->CnstyReadSt "2684->107" +Fsm state_q "441128463" +Transition IntegDigClrSt->IdleSt "2625->1357" +Fsm state_q "441128463" +Transition IntegDigClrSt->IntegDigSt "2625->1890" +Fsm state_q "441128463" +Transition InitWaitSt->InitSt "945->3367" +Fsm state_q "441128463" +State IntegDigPadSt "855" +Fsm error_q "2410907799" +Transition CheckFailError->MacroEccCorrError "6->2" +Fsm error_q "2410907799" +Transition FsmStateError->CheckFailError "7->6" +Fsm error_q "2410907799" +Transition FsmStateError->MacroEccCorrError "7->2" +Fsm error_q "2410907799" +Transition CheckFailError->FsmStateError "6->7" +CHECKSUM: "2063559012 2582220255" +INSTANCE: tb.dut.gen_partitions[5].gen_buffered.u_part_buf +Fsm state_q "441128463" +Transition InitWaitSt->InitSt "945->3367" +Fsm state_q "441128463" +Transition IntegDigClrSt->IdleSt "2625->1357" +Fsm state_q "441128463" +Transition IntegDigClrSt->IntegDigSt "2625->1890" +Fsm state_q "441128463" +Transition CnstyReadWaitSt->CnstyReadSt "2684->107" +Fsm state_q "441128463" +State IntegDigPadSt "855" +Fsm error_q "2410907799" +Transition CheckFailError->MacroEccCorrError "6->2" +Fsm error_q "2410907799" +Transition FsmStateError->CheckFailError "7->6" +Fsm error_q "2410907799" +Transition FsmStateError->MacroEccCorrError "7->2" +Fsm error_q "2410907799" +Transition CheckFailError->FsmStateError "6->7" +CHECKSUM: "2063559012 2582220255" +INSTANCE: tb.dut.gen_partitions[6].gen_buffered.u_part_buf +Fsm state_q "441128463" +Transition InitWaitSt->InitSt "945->3367" +Fsm state_q "441128463" +Transition IntegDigClrSt->IdleSt "2625->1357" +Fsm state_q "441128463" +Transition IntegDigClrSt->IntegDigSt "2625->1890" +Fsm state_q "441128463" +Transition CnstyReadWaitSt->CnstyReadSt "2684->107" +Fsm state_q "441128463" +State IntegDigPadSt "855" +Fsm error_q "2410907799" +Transition CheckFailError->MacroEccCorrError "6->2" +Fsm error_q "2410907799" +Transition FsmStateError->MacroEccCorrError "7->2" +Fsm error_q "2410907799" +Transition FsmStateError->CheckFailError "7->6" +Fsm error_q "2410907799" +Transition CheckFailError->FsmStateError "6->7" +CHECKSUM: "2063559012 2582220255" +INSTANCE: tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf +Fsm state_q "441128463" +Transition IdleSt->IntegDigClrSt "1357->2625" +Fsm state_q "441128463" +State InitDescrWaitSt "2472" +Fsm state_q "441128463" +State IntegDigFinSt "1765" +Fsm state_q "441128463" +State IntegDigPadSt "855" +Fsm state_q "441128463" +State IntegDigSt "1890" +Fsm state_q "441128463" +State IntegDigWaitSt "2290" +Fsm state_q "441128463" +State IntegScrSt "3418" +Fsm state_q "441128463" +State IntegScrWaitSt "2207" +Fsm state_q "441128463" +State InitDescrSt "3204" +Fsm error_q "2410907799" +Transition CheckFailError->MacroEccCorrError "6->2" +Fsm error_q "2410907799" +Transition FsmStateError->CheckFailError "7->6" +Fsm error_q "2410907799" +Transition FsmStateError->MacroEccCorrError "7->2" +Fsm error_q "2410907799" +Transition CheckFailError->FsmStateError "6->7" +CHECKSUM: "2940612991 27342893" +INSTANCE: tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf +Fsm error_q "2210720134" +Transition AccessError->MacroEccCorrError "5->2" +Fsm error_q "2210720134" +Transition CheckFailError->AccessError "6->5" +Fsm error_q "2210720134" +Transition CheckFailError->FsmStateError "6->7" +Fsm error_q "2210720134" +Transition CheckFailError->MacroEccCorrError "6->2" +Fsm error_q "2210720134" +Transition FsmStateError->AccessError "7->5" +Fsm error_q "2210720134" +Transition FsmStateError->MacroEccCorrError "7->2" +Fsm error_q "2210720134" +Transition FsmStateError->CheckFailError "7->6" +Fsm error_q "2210720134" +Transition MacroEccCorrError->AccessError "2->5" +Fsm error_q "2210720134" +Transition AccessError->CheckFailError "5->6" +CHECKSUM: "2940612991 27342893" +INSTANCE: tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf +Fsm error_q "2210720134" +Transition AccessError->MacroEccCorrError "5->2" +Fsm error_q "2210720134" +Transition CheckFailError->AccessError "6->5" +Fsm error_q "2210720134" +Transition CheckFailError->MacroEccCorrError "6->2" +Fsm error_q "2210720134" +Transition CheckFailError->FsmStateError "6->7" +Fsm error_q "2210720134" +Transition FsmStateError->AccessError "7->5" +Fsm error_q "2210720134" +Transition FsmStateError->CheckFailError "7->6" +Fsm error_q "2210720134" +Transition FsmStateError->MacroEccCorrError "7->2" +Fsm error_q "2210720134" +Transition MacroEccCorrError->AccessError "2->5" +Fsm error_q "2210720134" +Transition AccessError->CheckFailError "5->6" +CHECKSUM: "2940612991 27342893" +INSTANCE: tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf +Fsm error_q "2210720134" +Transition CheckFailError->AccessError "6->5" +Fsm error_q "2210720134" +Transition CheckFailError->FsmStateError "6->7" +Fsm error_q "2210720134" +Transition CheckFailError->MacroEccCorrError "6->2" +Fsm error_q "2210720134" +Transition FsmStateError->AccessError "7->5" +Fsm error_q "2210720134" +Transition FsmStateError->CheckFailError "7->6" +Fsm error_q "2210720134" +Transition FsmStateError->MacroEccCorrError "7->2" +Fsm error_q "2210720134" +Transition MacroEccCorrError->AccessError "2->5" +Fsm error_q "2210720134" +Transition AccessError->MacroEccCorrError "5->2" +Fsm error_q "2210720134" +Transition AccessError->CheckFailError "5->6" +CHECKSUM: "4205406832 4258846959" +INSTANCE: tb.dut.u_otp_ctrl_dai +Fsm error_q "1085514286" +Transition FsmStateError->AccessError "7->5" +Fsm error_q "1085514286" +Transition FsmStateError->MacroEccCorrError "7->2" +Fsm error_q "1085514286" +Transition AccessError->MacroEccCorrError "5->2" +CHECKSUM: "761735614 2379312231" +INSTANCE: tb.dut.u_otp_ctrl_kdi +Fsm state_q "2979668442" +Transition DigWaitSt->FinishSt "913->760" +Fsm state_q "2979668442" +Transition DigWaitSt->DigLoadSt "913->183" diff --git a/src/fuse_ctrl/dv/cov/otp_ctrl_cov_if.sv b/src/fuse_ctrl/dv/cov/otp_ctrl_cov_if.sv new file mode 100755 index 0000000..106178b --- /dev/null +++ b/src/fuse_ctrl/dv/cov/otp_ctrl_cov_if.sv @@ -0,0 +1,113 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Implements functional coverage for OTP_CTRL + +interface otp_ctrl_cov_if + import otp_ctrl_reg_pkg::*; + ( + input pwrmgr_pkg::pwr_otp_rsp_t pwr_otp_o, + input otp_ctrl_pkg::lc_otp_program_req_t lc_otp_program_i, + input bit [3:0] lc_escalate_en_i, + input otp_ctrl_pkg::flash_otp_key_req_t flash_otp_key_i, + input otp_ctrl_pkg::sram_otp_key_req_t [NumSramKeyReqSlots-1:0] sram_otp_key_i, + input otp_ctrl_pkg::otbn_otp_key_req_t otbn_otp_key_i + ); + + import uvm_pkg::*; + import dv_utils_pkg::*; + `include "dv_fcov_macros.svh" + + covergroup lc_esc_en_condition_cg @(lc_escalate_en_i == lc_ctrl_pkg::On); + lc_esc_during_flash_data_req: coverpoint flash_otp_key_i.data_req; + lc_esc_during_flash_addr_req: coverpoint flash_otp_key_i.addr_req; + lc_esc_during_sram_0_req: coverpoint sram_otp_key_i[0].req; + lc_esc_during_sram_1_req: coverpoint sram_otp_key_i[1].req; + lc_esc_during_otbn_req: coverpoint otbn_otp_key_i.req; + lc_esc_during_otp_idle: coverpoint pwr_otp_o.otp_idle; + lc_esc_during_lc_otp_prog_req: coverpoint lc_otp_program_i.req; + endgroup + + covergroup flash_data_req_condition_cg @(flash_otp_key_i.data_req); + flash_data_req_during_lc_esc: coverpoint lc_escalate_en_i { + bins lc_esc_on = {lc_ctrl_pkg::On}; + bins lc_esc_off = {[0 : lc_ctrl_pkg::On-1], [lc_ctrl_pkg::On+1 : '1]}; + } + flash_data_req_during_flash_addr_req: coverpoint flash_otp_key_i.addr_req; + flash_data_req_during_sram_0_req: coverpoint sram_otp_key_i[0].req; + flash_data_req_during_sram_1_req: coverpoint sram_otp_key_i[1].req; + flash_data_req_during_otbn_req: coverpoint otbn_otp_key_i.req; + flash_data_req_during_otp_idle: coverpoint pwr_otp_o.otp_idle; + endgroup + + covergroup flash_addr_req_condition_cg @(flash_otp_key_i.addr_req); + flash_addr_req_during_lc_esc: coverpoint lc_escalate_en_i { + bins lc_esc_on = {lc_ctrl_pkg::On}; + bins lc_esc_off = {[0 : lc_ctrl_pkg::On-1], [lc_ctrl_pkg::On+1 : '1]}; + } + flash_addr_req_during_flash_data_req: coverpoint flash_otp_key_i.data_req; + flash_addr_req_during_sram_0_req: coverpoint sram_otp_key_i[0].req; + flash_addr_req_during_sram_1_req: coverpoint sram_otp_key_i[1].req; + flash_addr_req_during_otbn_req: coverpoint otbn_otp_key_i.req; + flash_addr_req_during_otp_idle: coverpoint pwr_otp_o.otp_idle; + endgroup + + covergroup sram_0_req_condition_cg @(sram_otp_key_i[0].req); + sram_0_req_during_lc_esc: coverpoint lc_escalate_en_i { + bins lc_esc_on = {lc_ctrl_pkg::On}; + bins lc_esc_off = {[0 : lc_ctrl_pkg::On-1], [lc_ctrl_pkg::On+1 : '1]}; + } + sram_0_req_during_flash_addr_req: coverpoint flash_otp_key_i.addr_req; + sram_0_req_during_flash_data_req: coverpoint flash_otp_key_i.data_req; + sram_0_req_during_sram_1_req: coverpoint sram_otp_key_i[1].req; + sram_0_req_during_otbn_req: coverpoint otbn_otp_key_i.req; + sram_0_req_during_otp_idle: coverpoint pwr_otp_o.otp_idle; + endgroup + + covergroup sram_1_req_condition_cg @(sram_otp_key_i[1].req); + sram_1_req_during_lc_esc: coverpoint lc_escalate_en_i { + bins lc_esc_on = {lc_ctrl_pkg::On}; + bins lc_esc_off = {[0 : lc_ctrl_pkg::On-1], [lc_ctrl_pkg::On+1 : '1]}; + } + sram_1_req_during_flash_addr_req: coverpoint flash_otp_key_i.addr_req; + sram_1_req_during_flash_data_req: coverpoint flash_otp_key_i.data_req; + sram_1_req_during_sram_0_req: coverpoint sram_otp_key_i[0].req; + sram_1_req_during_otbn_req: coverpoint otbn_otp_key_i.req; + sram_1_req_during_otp_idle: coverpoint pwr_otp_o.otp_idle; + endgroup + + covergroup otbn_req_condition_cg @(otbn_otp_key_i.req); + otbn_req_during_lc_esc: coverpoint lc_escalate_en_i { + bins lc_esc_on = {lc_ctrl_pkg::On}; + bins lc_esc_off = {[0 : lc_ctrl_pkg::On-1], [lc_ctrl_pkg::On+1 : '1]}; + } + otbn_req_during_flash_addr_req: coverpoint flash_otp_key_i.addr_req; + otbn_req_during_flash_data_req: coverpoint flash_otp_key_i.data_req; + otbn_req_during_sram_0_req: coverpoint sram_otp_key_i[0].req; + otbn_req_during_sram_1_req: coverpoint sram_otp_key_i[1].req; + otbn_req_during_otp_idle: coverpoint pwr_otp_o.otp_idle; + endgroup + + covergroup lc_prog_req_condition_cg @(lc_otp_program_i.req); + lc_prog_req_during_lc_esc: coverpoint lc_escalate_en_i { + bins lc_esc_on = {lc_ctrl_pkg::On}; + bins lc_esc_off = {[0 : lc_ctrl_pkg::On-1], [lc_ctrl_pkg::On+1 : '1]}; + } + lc_prog_req_during_flash_addr_req: coverpoint flash_otp_key_i.addr_req; + lc_prog_req_during_flash_data_req: coverpoint flash_otp_key_i.data_req; + lc_prog_req_during_sram_0_req: coverpoint sram_otp_key_i[0].req; + lc_prog_req_during_sram_1_req: coverpoint sram_otp_key_i[1].req; + lc_prog_req_during_otbn_req: coverpoint otbn_otp_key_i.req; + lc_prog_req_during_otp_idle: coverpoint pwr_otp_o.otp_idle; + endgroup + + `DV_FCOV_INSTANTIATE_CG(lc_esc_en_condition_cg) + `DV_FCOV_INSTANTIATE_CG(flash_data_req_condition_cg) + `DV_FCOV_INSTANTIATE_CG(flash_addr_req_condition_cg) + `DV_FCOV_INSTANTIATE_CG(sram_0_req_condition_cg) + `DV_FCOV_INSTANTIATE_CG(sram_1_req_condition_cg) + `DV_FCOV_INSTANTIATE_CG(otbn_req_condition_cg) + `DV_FCOV_INSTANTIATE_CG(lc_prog_req_condition_cg) + +endinterface diff --git a/src/fuse_ctrl/dv/cov/otp_ctrl_cov_unr_excl.el b/src/fuse_ctrl/dv/cov/otp_ctrl_cov_unr_excl.el new file mode 100755 index 0000000..1119db5 --- /dev/null +++ b/src/fuse_ctrl/dv/cov/otp_ctrl_cov_unr_excl.el @@ -0,0 +1,6102 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Generated UNR file from Synopsys UNR tool with security modules being black-boxed. +//================================================== +// This file contains the Excluded objects +// Generated By User: miguelosorio +// Format Version: 2 +// Date: Fri Feb 23 21:09:38 2024 +// ExclMode: default +//================================================== +CHECKSUM: "2868806991 3096942133" +INSTANCE: tb.dut.gen_alert_tx[4].u_prim_alert_sender +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 alert_ack_o "logic alert_ack_o" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 alert_ack_o "logic alert_ack_o" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 alert_state_o "logic alert_state_o" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 alert_state_o "logic alert_state_o" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "698853052 3336016746" +INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic +ANNOTATION: "VC_COV_UNR" +Branch 3 "1554177250" "state_q" (1) "state_q ResetSt ,1,0,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 3 "1554177250" "state_q" (8) "state_q IdleSt ,-,-,1,default,-,-,-,-,-,-,-,-" +CHECKSUM: "189358556 1401458059" +INSTANCE: tb.dut +ANNOTATION: "VC_COV_UNR" +Branch 4 "1264131593" "tlul_req" (1) "tlul_req 1,0" +CHECKSUM: "1746381268 3161287359" +INSTANCE: tb.dut.u_reg_core.u_socket +ANNOTATION: "VC_COV_UNR" +Branch 4 "3202860295" "(!rst_ni)" (2) "(!rst_ni) 0,1,0,-" +CHECKSUM: "1817939962 2852341788" +INSTANCE: tb.dut.u_tlul_adapter_sram.u_reqfifo.gen_normal_fifo.u_fifo_cnt +ANNOTATION: "VC_COV_UNR" +Block 12 "398307645" "wptr_o <= (wptr_o + {{(Width - 1) {1'b0}}, 1'b1});" +ANNOTATION: "VC_COV_UNR" +Block 21 "2517571270" "rptr_o <= (rptr_o + {{(Width - 1) {1'b0}}, 1'b1});" +CHECKSUM: "1817939962 2852341788" +INSTANCE: tb.dut.u_tlul_adapter_sram.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt +ANNOTATION: "VC_COV_UNR" +Block 12 "398307645" "wptr_o <= (wptr_o + {{(Width - 1) {1'b0}}, 1'b1});" +ANNOTATION: "VC_COV_UNR" +Block 21 "2517571270" "rptr_o <= (rptr_o + {{(Width - 1) {1'b0}}, 1'b1});" +CHECKSUM: "1817939962 2852341788" +INSTANCE: tb.dut.u_tlul_adapter_sram.u_rspfifo.gen_normal_fifo.u_fifo_cnt +ANNOTATION: "VC_COV_UNR" +Block 12 "398307645" "wptr_o <= (wptr_o + {{(Width - 1) {1'b0}}, 1'b1});" +ANNOTATION: "VC_COV_UNR" +Block 21 "2517571270" "rptr_o <= (rptr_o + {{(Width - 1) {1'b0}}, 1'b1});" +CHECKSUM: "698853052 1537087436" +INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic +ANNOTATION: "VC_COV_UNR" +Block 24 "3494210324" ";" +CHECKSUM: "3727300757 3190968676" +INSTANCE: tb.dut.gen_partitions[5].gen_buffered.u_part_buf +ANNOTATION: "VC_COV_UNR" +Block 22 "662519215" "scrmbl_mtx_req_o = 1'b1;" +ANNOTATION: "VC_COV_UNR" +Block 23 "617613755" "state_d = InitDescrWaitSt;" +ANNOTATION: "VC_COV_UNR" +Block 25 "2942482414" "scrmbl_mtx_req_o = 1'b1;" +ANNOTATION: "VC_COV_UNR" +Block 26 "3475289755" "state_d = InitSt;" +ANNOTATION: "VC_COV_UNR" +Block 68 "746922678" "scrmbl_mtx_req_o = 1'b1;" +ANNOTATION: "VC_COV_UNR" +Block 69 "369318088" "state_d = IntegScrWaitSt;" +ANNOTATION: "VC_COV_UNR" +Block 71 "1545788457" "scrmbl_mtx_req_o = 1'b1;" +ANNOTATION: "VC_COV_UNR" +Block 72 "2540127236" "state_d = IntegDigSt;" +ANNOTATION: "VC_COV_UNR" +Block 78 "4176855572" "state_d = IntegDigPadSt;" +ANNOTATION: "VC_COV_UNR" +Block 86 "1288945484" "scrmbl_mtx_req_o = 1'b1;" +ANNOTATION: "VC_COV_UNR" +Block 87 "984470440" "state_d = IntegDigFinSt;" +ANNOTATION: "VC_COV_UNR" +Block 105 "1192338528" "state_d = ErrorSt;" +ANNOTATION: "VC_COV_UNR" +Block 106 "2515805717" "error_d = CheckFailError;" +CHECKSUM: "3727300757 328877407" +INSTANCE: tb.dut.gen_partitions[6].gen_buffered.u_part_buf +ANNOTATION: "VC_COV_UNR" +Block 22 "662519215" "scrmbl_mtx_req_o = 1'b1;" +ANNOTATION: "VC_COV_UNR" +Block 23 "617613755" "state_d = InitDescrWaitSt;" +ANNOTATION: "VC_COV_UNR" +Block 25 "2942482414" "scrmbl_mtx_req_o = 1'b1;" +ANNOTATION: "VC_COV_UNR" +Block 26 "3475289755" "state_d = InitSt;" +ANNOTATION: "VC_COV_UNR" +Block 68 "746922678" "scrmbl_mtx_req_o = 1'b1;" +ANNOTATION: "VC_COV_UNR" +Block 69 "369318088" "state_d = IntegScrWaitSt;" +ANNOTATION: "VC_COV_UNR" +Block 71 "1545788457" "scrmbl_mtx_req_o = 1'b1;" +ANNOTATION: "VC_COV_UNR" +Block 72 "2540127236" "state_d = IntegDigSt;" +ANNOTATION: "VC_COV_UNR" +Block 77 "3141955456" "scrmbl_cmd_o = Digest;" +ANNOTATION: "VC_COV_UNR" +Block 105 "1192338528" "state_d = ErrorSt;" +ANNOTATION: "VC_COV_UNR" +Block 106 "2515805717" "error_d = CheckFailError;" +CHECKSUM: "3727300757 4034042967" +INSTANCE: tb.dut.gen_partitions[7].gen_buffered.u_part_buf +ANNOTATION: "VC_COV_UNR" +Block 78 "4176855572" "state_d = IntegDigPadSt;" +ANNOTATION: "VC_COV_UNR" +Block 86 "1288945484" "scrmbl_mtx_req_o = 1'b1;" +ANNOTATION: "VC_COV_UNR" +Block 87 "984470440" "state_d = IntegDigFinSt;" +ANNOTATION: "VC_COV_UNR" +Block 105 "1192338528" "state_d = ErrorSt;" +ANNOTATION: "VC_COV_UNR" +Block 106 "2515805717" "error_d = CheckFailError;" +CHECKSUM: "3727300757 2385925532" +INSTANCE: tb.dut.gen_partitions[8].gen_buffered.u_part_buf +ANNOTATION: "VC_COV_UNR" +Block 78 "4176855572" "state_d = IntegDigPadSt;" +ANNOTATION: "VC_COV_UNR" +Block 86 "1288945484" "scrmbl_mtx_req_o = 1'b1;" +ANNOTATION: "VC_COV_UNR" +Block 87 "984470440" "state_d = IntegDigFinSt;" +ANNOTATION: "VC_COV_UNR" +Block 105 "1192338528" "state_d = ErrorSt;" +ANNOTATION: "VC_COV_UNR" +Block 106 "2515805717" "error_d = CheckFailError;" +CHECKSUM: "3727300757 2380508828" +INSTANCE: tb.dut.gen_partitions[9].gen_buffered.u_part_buf +ANNOTATION: "VC_COV_UNR" +Block 78 "4176855572" "state_d = IntegDigPadSt;" +ANNOTATION: "VC_COV_UNR" +Block 86 "1288945484" "scrmbl_mtx_req_o = 1'b1;" +ANNOTATION: "VC_COV_UNR" +Block 87 "984470440" "state_d = IntegDigFinSt;" +ANNOTATION: "VC_COV_UNR" +Block 105 "1192338528" "state_d = ErrorSt;" +ANNOTATION: "VC_COV_UNR" +Block 106 "2515805717" "error_d = CheckFailError;" +CHECKSUM: "3727300757 3973220603" +INSTANCE: tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf +ANNOTATION: "VC_COV_UNR" +Block 22 "662519215" "scrmbl_mtx_req_o = 1'b1;" +ANNOTATION: "VC_COV_UNR" +Block 25 "2942482414" "scrmbl_mtx_req_o = 1'b1;" +ANNOTATION: "VC_COV_UNR" +Block 68 "746922678" "scrmbl_mtx_req_o = 1'b1;" +ANNOTATION: "VC_COV_UNR" +Block 71 "1545788457" "scrmbl_mtx_req_o = 1'b1;" +ANNOTATION: "VC_COV_UNR" +Block 74 "736744825" "scrmbl_mtx_req_o = 1'b1;" +ANNOTATION: "VC_COV_UNR" +Block 86 "1288945484" "scrmbl_mtx_req_o = 1'b1;" +ANNOTATION: "VC_COV_UNR" +Block 89 "967932616" "scrmbl_mtx_req_o = 1'b1;" +ANNOTATION: "VC_COV_UNR" +Block 92 "3253244488" "scrmbl_mtx_req_o = 1'b1;" +ANNOTATION: "VC_COV_UNR" +Block 105 "1192338528" "state_d = ErrorSt;" +ANNOTATION: "VC_COV_UNR" +Block 106 "2515805717" "error_d = CheckFailError;" +CHECKSUM: "3882079776 1965827338" +INSTANCE: tb.dut.u_otp_ctrl_scrmbl +ANNOTATION: "VC_COV_UNR" +Block 28 "3494210324" ";" +CHECKSUM: "4255502330 223073768" +INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field3 +ANNOTATION: "VC_COV_UNR" +Block 4 "1824183207" "q <= wr_data;" +CHECKSUM: "4255502330 223073768" +INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field4 +ANNOTATION: "VC_COV_UNR" +Block 4 "1824183207" "q <= wr_data;" +CHECKSUM: "4255502330 223073768" +INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field5 +ANNOTATION: "VC_COV_UNR" +Block 4 "1824183207" "q <= wr_data;" +CHECKSUM: "4255502330 223073768" +INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field6 +ANNOTATION: "VC_COV_UNR" +Block 4 "1824183207" "q <= wr_data;" +CHECKSUM: "4255502330 223073768" +INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field7 +ANNOTATION: "VC_COV_UNR" +Block 4 "1824183207" "q <= wr_data;" +CHECKSUM: "4255502330 223073768" +INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field8 +ANNOTATION: "VC_COV_UNR" +Block 4 "1824183207" "q <= wr_data;" +CHECKSUM: "4255502330 223073768" +INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field2 +ANNOTATION: "VC_COV_UNR" +Block 4 "1824183207" "q <= wr_data;" +CHECKSUM: "4255502330 223073768" +INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field3 +ANNOTATION: "VC_COV_UNR" +Block 4 "1824183207" "q <= wr_data;" +CHECKSUM: "4255502330 223073768" +INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field4 +ANNOTATION: "VC_COV_UNR" +Block 4 "1824183207" "q <= wr_data;" +CHECKSUM: "4255502330 223073768" +INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field5 +ANNOTATION: "VC_COV_UNR" +Block 4 "1824183207" "q <= wr_data;" +CHECKSUM: "4255502330 223073768" +INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field0 +ANNOTATION: "VC_COV_UNR" +Block 4 "1824183207" "q <= wr_data;" +CHECKSUM: "4255502330 223073768" +INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field1 +ANNOTATION: "VC_COV_UNR" +Block 4 "1824183207" "q <= wr_data;" +CHECKSUM: "4255502330 223073768" +INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field2 +ANNOTATION: "VC_COV_UNR" +Block 4 "1824183207" "q <= wr_data;" +CHECKSUM: "4255502330 223073768" +INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field3 +ANNOTATION: "VC_COV_UNR" +Block 4 "1824183207" "q <= wr_data;" +CHECKSUM: "3162909804 919553166" +INSTANCE: tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf +ANNOTATION: "VC_COV_UNR" +Block 17 "814628507" "error_d = MacroEccCorrError;" +ANNOTATION: "VC_COV_UNR" +Block 19 "2376363309" "state_d = ErrorSt;" +ANNOTATION: "VC_COV_UNR" +Block 32 "3415759745" "error_d = MacroEccCorrError;" +ANNOTATION: "VC_COV_UNR" +Block 34 "3854455635" "state_d = ErrorSt;" +CHECKSUM: "1335069400 3084451679" +INSTANCE: tb.dut.u_tlul_adapter_sram +ANNOTATION: "VC_COV_UNR" +Block 20 "3478134645" "d_valid = 1'b1;" +CHECKSUM: "189358556 478664514" +INSTANCE: tb.dut +ANNOTATION: "VC_COV_UNR" +Block 15 "1636116421" "tlul_oob_err_d = 1'b1;" +ANNOTATION: "VC_COV_UNR" +Block 32 "3434355351" "part_access_pre[k] = {2 {MuBi8True}};" +CHECKSUM: "903559179 545489449" +INSTANCE: tb.dut.u_otp_ctrl_dai +ANNOTATION: "VC_COV_UNR" +Block 16 "175586303" "state_d = ErrorSt;" +ANNOTATION: "VC_COV_UNR" +Block 68 "1681789786" "state_d = ErrorSt;" +CHECKSUM: "1158524476 3747170265" +INSTANCE: tb.dut.u_otp_ctrl_kdi +ANNOTATION: "VC_COV_UNR" +Block 88 "3038555774" "state_d = DigLoadSt;" +CHECKSUM: "3727300757 2582220255" +INSTANCE: tb.dut.gen_partitions[5].gen_buffered.u_part_buf +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +State InitDescrSt "3204" +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +State InitDescrWaitSt "2472" +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +State IntegDigPadSt "855" +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +State IntegScrSt "3418" +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +State IntegScrWaitSt "2207" +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +Transition CnstyReadWaitSt->CnstyReadSt "2684->107" +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +Transition IntegDigClrSt->IdleSt "2625->1357" +Fsm error_q "2410907799" +ANNOTATION: "VC_COV_UNR" +Transition CheckFailError->FsmStateError "6->7" +Fsm error_q "2410907799" +ANNOTATION: "VC_COV_UNR" +Transition CheckFailError->MacroEccCorrError "6->2" +Fsm error_q "2410907799" +ANNOTATION: "VC_COV_UNR" +Transition FsmStateError->CheckFailError "7->6" +Fsm error_q "2410907799" +ANNOTATION: "VC_COV_UNR" +Transition FsmStateError->MacroEccCorrError "7->2" +CHECKSUM: "3727300757 2582220255" +INSTANCE: tb.dut.gen_partitions[6].gen_buffered.u_part_buf +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +State InitDescrSt "3204" +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +State InitDescrWaitSt "2472" +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +State IntegScrSt "3418" +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +State IntegScrWaitSt "2207" +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +Transition CnstyReadWaitSt->CnstyReadSt "2684->107" +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +Transition IntegDigClrSt->IdleSt "2625->1357" +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +Transition IntegDigSt->IntegDigFinSt "1890->1765" +Fsm error_q "2410907799" +ANNOTATION: "VC_COV_UNR" +Transition CheckFailError->FsmStateError "6->7" +Fsm error_q "2410907799" +ANNOTATION: "VC_COV_UNR" +Transition CheckFailError->MacroEccCorrError "6->2" +Fsm error_q "2410907799" +ANNOTATION: "VC_COV_UNR" +Transition FsmStateError->CheckFailError "7->6" +Fsm error_q "2410907799" +ANNOTATION: "VC_COV_UNR" +Transition FsmStateError->MacroEccCorrError "7->2" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "189358556 549301488" +INSTANCE: tb.dut +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_ast_pwr_seq_o.pwr_seq [0] "logic otp_ast_pwr_seq_o.pwr_seq[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_ast_pwr_seq_o.pwr_seq [0] "logic otp_ast_pwr_seq_o.pwr_seq[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_ast_pwr_seq_o.pwr_seq [1] "logic otp_ast_pwr_seq_o.pwr_seq[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_ast_pwr_seq_o.pwr_seq [1] "logic otp_ast_pwr_seq_o.pwr_seq[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 lc_otp_vendor_test_o.status [0] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 lc_otp_vendor_test_o.status [0] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 lc_otp_vendor_test_o.status [1] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 lc_otp_vendor_test_o.status [1] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 lc_otp_vendor_test_o.status [2] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 lc_otp_vendor_test_o.status [2] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 lc_otp_vendor_test_o.status [3] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 lc_otp_vendor_test_o.status [3] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 lc_otp_vendor_test_o.status [4] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 lc_otp_vendor_test_o.status [4] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 lc_otp_vendor_test_o.status [5] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 lc_otp_vendor_test_o.status [5] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 lc_otp_vendor_test_o.status [6] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 lc_otp_vendor_test_o.status [6] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 lc_otp_vendor_test_o.status [7] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 lc_otp_vendor_test_o.status [7] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 lc_otp_vendor_test_o.status [8] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 lc_otp_vendor_test_o.status [8] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 lc_otp_vendor_test_o.status [9] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 lc_otp_vendor_test_o.status [9] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 lc_otp_vendor_test_o.status [10] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 lc_otp_vendor_test_o.status [10] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 lc_otp_vendor_test_o.status [11] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 lc_otp_vendor_test_o.status [11] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 lc_otp_vendor_test_o.status [12] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 lc_otp_vendor_test_o.status [12] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 lc_otp_vendor_test_o.status [13] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 lc_otp_vendor_test_o.status [13] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 lc_otp_vendor_test_o.status [14] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 lc_otp_vendor_test_o.status [14] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 lc_otp_vendor_test_o.status [15] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 lc_otp_vendor_test_o.status [15] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 lc_otp_vendor_test_o.status [16] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 lc_otp_vendor_test_o.status [16] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 lc_otp_vendor_test_o.status [17] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 lc_otp_vendor_test_o.status [17] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 lc_otp_vendor_test_o.status [18] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 lc_otp_vendor_test_o.status [18] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 lc_otp_vendor_test_o.status [19] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 lc_otp_vendor_test_o.status [19] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 lc_otp_vendor_test_o.status [20] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 lc_otp_vendor_test_o.status [20] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 lc_otp_vendor_test_o.status [21] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 lc_otp_vendor_test_o.status [21] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 lc_otp_vendor_test_o.status [22] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 lc_otp_vendor_test_o.status [22] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 lc_otp_vendor_test_o.status [23] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 lc_otp_vendor_test_o.status [23] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 lc_otp_vendor_test_o.status [24] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 lc_otp_vendor_test_o.status [24] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 lc_otp_vendor_test_o.status [25] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 lc_otp_vendor_test_o.status [25] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 lc_otp_vendor_test_o.status [26] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 lc_otp_vendor_test_o.status [26] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 lc_otp_vendor_test_o.status [27] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 lc_otp_vendor_test_o.status [27] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 lc_otp_vendor_test_o.status [28] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 lc_otp_vendor_test_o.status [28] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 lc_otp_vendor_test_o.status [29] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 lc_otp_vendor_test_o.status [29] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 lc_otp_vendor_test_o.status [30] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 lc_otp_vendor_test_o.status [30] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 lc_otp_vendor_test_o.status [31] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 lc_otp_vendor_test_o.status [31] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed_valid "logic otp_keymgr_key_o.owner_seed_valid" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed_valid "logic otp_keymgr_key_o.owner_seed_valid" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [0] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [0] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [1] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [1] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [2] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [2] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [3] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [3] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [4] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [4] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [5] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [5] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [6] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [6] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [7] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [7] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [8] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [8] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [9] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [9] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [10] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [10] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [11] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [11] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [12] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [12] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [13] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [13] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [14] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [14] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [15] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [15] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [16] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [16] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [17] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [17] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [18] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [18] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [19] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [19] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [20] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [20] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [21] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [21] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [22] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [22] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [23] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [23] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [24] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [24] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [25] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [25] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [26] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [26] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [27] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [27] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [28] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [28] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [29] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [29] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [30] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [30] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [31] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [31] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [32] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [32] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [33] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [33] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [34] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [34] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [35] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [35] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [36] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [36] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [37] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [37] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [38] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [38] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [39] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [39] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [40] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [40] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [41] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [41] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [42] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [42] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [43] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [43] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [44] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [44] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [45] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [45] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [46] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [46] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [47] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [47] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [48] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [48] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [49] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [49] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [50] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [50] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [51] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [51] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [52] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [52] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [53] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [53] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [54] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [54] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [55] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [55] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [56] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [56] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [57] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [57] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [58] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [58] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [59] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [59] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [60] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [60] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [61] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [61] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [62] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [62] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [63] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [63] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [64] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [64] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [65] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [65] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [66] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [66] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [67] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [67] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [68] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [68] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [69] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [69] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [70] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [70] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [71] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [71] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [72] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [72] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [73] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [73] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [74] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [74] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [75] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [75] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [76] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [76] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [77] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [77] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [78] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [78] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [79] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [79] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [80] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [80] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [81] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [81] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [82] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [82] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [83] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [83] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [84] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [84] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [85] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [85] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [86] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [86] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [87] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [87] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [88] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [88] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [89] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [89] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [90] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [90] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [91] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [91] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [92] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [92] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [93] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [93] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [94] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [94] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [95] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [95] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [96] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [96] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [97] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [97] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [98] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [98] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [99] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [99] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [100] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [100] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [101] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [101] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [102] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [102] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [103] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [103] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [104] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [104] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [105] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [105] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [106] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [106] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [107] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [107] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [108] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [108] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [109] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [109] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [110] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [110] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [111] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [111] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [112] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [112] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [113] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [113] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [114] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [114] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [115] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [115] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [116] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [116] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [117] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [117] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [118] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [118] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [119] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [119] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [120] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [120] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [121] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [121] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [122] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [122] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [123] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [123] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [124] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [124] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [125] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [125] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [126] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [126] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [127] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [127] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [128] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [128] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [129] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [129] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [130] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [130] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [131] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [131] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [132] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [132] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [133] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [133] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [134] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [134] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [135] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [135] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [136] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [136] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [137] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [137] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [138] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [138] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [139] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [139] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [140] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [140] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [141] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [141] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [142] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [142] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [143] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [143] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [144] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [144] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [145] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [145] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [146] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [146] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [147] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [147] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [148] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [148] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [149] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [149] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [150] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [150] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [151] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [151] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [152] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [152] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [153] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [153] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [154] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [154] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [155] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [155] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [156] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [156] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [157] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [157] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [158] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [158] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [159] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [159] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [160] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [160] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [161] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [161] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [162] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [162] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [163] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [163] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [164] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [164] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [165] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [165] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [166] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [166] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [167] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [167] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [168] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [168] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [169] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [169] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [170] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [170] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [171] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [171] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [172] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [172] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [173] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [173] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [174] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [174] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [175] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [175] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [176] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [176] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [177] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [177] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [178] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [178] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [179] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [179] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [180] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [180] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [181] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [181] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [182] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [182] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [183] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [183] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [184] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [184] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [185] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [185] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [186] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [186] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [187] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [187] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [188] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [188] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [189] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [189] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [190] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [190] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [191] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [191] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [192] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [192] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [193] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [193] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [194] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [194] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [195] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [195] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [196] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [196] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [197] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [197] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [198] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [198] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [199] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [199] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [200] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [200] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [201] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [201] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [202] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [202] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [203] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [203] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [204] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [204] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [205] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [205] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [206] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [206] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [207] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [207] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [208] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [208] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [209] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [209] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [210] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [210] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [211] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [211] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [212] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [212] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [213] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [213] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [214] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [214] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [215] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [215] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [216] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [216] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [217] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [217] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [218] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [218] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [219] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [219] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [220] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [220] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [221] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [221] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [222] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [222] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [223] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [223] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [224] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [224] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [225] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [225] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [226] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [226] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [227] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [227] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [228] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [228] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [229] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [229] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [230] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [230] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [231] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [231] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [232] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [232] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [233] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [233] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [234] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [234] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [235] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [235] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [236] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [236] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [237] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [237] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [238] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [238] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [239] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [239] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [240] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [240] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [241] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [241] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [242] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [242] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [243] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [243] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [244] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [244] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [245] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [245] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [246] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [246] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [247] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [247] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [248] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [248] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [249] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [249] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [250] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [250] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [251] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [251] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [252] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [252] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [253] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [253] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [254] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [254] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [255] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [255] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed_valid "logic otp_keymgr_key_o.creator_seed_valid" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed_valid "logic otp_keymgr_key_o.creator_seed_valid" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [0] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [0] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [1] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [1] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [2] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [2] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [3] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [3] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [4] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [4] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [5] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [5] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [6] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [6] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [7] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [7] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [8] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [8] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [9] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [9] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [10] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [10] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [11] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [11] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [12] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [12] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [13] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [13] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [14] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [14] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [15] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [15] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [16] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [16] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [17] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [17] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [18] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [18] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [19] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [19] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [20] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [20] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [21] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [21] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [22] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [22] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [23] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [23] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [24] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [24] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [25] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [25] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [26] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [26] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [27] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [27] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [28] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [28] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [29] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [29] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [30] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [30] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [31] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [31] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [32] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [32] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [33] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [33] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [34] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [34] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [35] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [35] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [36] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [36] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [37] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [37] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [38] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [38] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [39] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [39] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [40] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [40] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [41] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [41] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [42] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [42] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [43] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [43] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [44] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [44] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [45] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [45] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [46] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [46] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [47] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [47] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [48] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [48] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [49] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [49] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [50] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [50] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [51] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [51] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [52] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [52] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [53] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [53] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [54] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [54] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [55] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [55] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [56] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [56] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [57] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [57] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [58] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [58] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [59] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [59] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [60] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [60] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [61] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [61] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [62] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [62] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [63] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [63] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [64] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [64] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [65] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [65] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [66] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [66] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [67] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [67] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [68] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [68] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [69] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [69] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [70] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [70] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [71] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [71] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [72] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [72] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [73] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [73] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [74] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [74] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [75] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [75] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [76] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [76] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [77] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [77] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [78] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [78] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [79] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [79] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [80] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [80] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [81] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [81] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [82] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [82] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [83] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [83] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [84] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [84] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [85] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [85] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [86] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [86] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [87] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [87] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [88] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [88] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [89] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [89] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [90] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [90] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [91] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [91] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [92] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [92] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [93] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [93] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [94] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [94] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [95] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [95] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [96] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [96] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [97] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [97] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [98] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [98] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [99] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [99] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [100] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [100] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [101] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [101] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [102] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [102] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [103] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [103] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [104] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [104] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [105] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [105] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [106] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [106] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [107] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [107] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [108] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [108] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [109] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [109] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [110] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [110] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [111] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [111] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [112] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [112] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [113] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [113] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [114] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [114] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [115] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [115] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [116] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [116] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [117] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [117] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [118] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [118] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [119] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [119] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [120] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [120] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [121] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [121] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [122] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [122] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [123] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [123] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [124] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [124] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [125] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [125] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [126] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [126] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [127] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [127] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [128] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [128] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [129] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [129] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [130] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [130] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [131] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [131] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [132] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [132] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [133] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [133] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [134] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [134] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [135] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [135] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [136] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [136] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [137] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [137] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [138] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [138] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [139] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [139] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [140] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [140] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [141] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [141] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [142] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [142] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [143] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [143] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [144] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [144] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [145] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [145] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [146] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [146] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [147] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [147] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [148] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [148] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [149] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [149] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [150] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [150] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [151] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [151] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [152] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [152] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [153] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [153] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [154] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [154] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [155] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [155] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [156] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [156] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [157] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [157] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [158] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [158] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [159] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [159] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [160] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [160] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [161] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [161] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [162] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [162] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [163] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [163] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [164] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [164] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [165] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [165] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [166] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [166] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [167] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [167] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [168] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [168] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [169] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [169] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [170] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [170] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [171] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [171] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [172] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [172] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [173] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [173] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [174] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [174] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [175] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [175] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [176] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [176] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [177] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [177] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [178] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [178] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [179] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [179] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [180] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [180] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [181] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [181] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [182] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [182] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [183] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [183] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [184] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [184] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [185] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [185] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [186] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [186] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [187] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [187] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [188] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [188] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [189] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [189] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [190] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [190] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [191] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [191] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [192] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [192] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [193] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [193] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [194] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [194] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [195] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [195] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [196] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [196] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [197] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [197] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [198] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [198] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [199] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [199] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [200] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [200] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [201] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [201] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [202] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [202] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [203] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [203] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [204] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [204] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [205] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [205] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [206] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [206] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [207] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [207] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [208] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [208] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [209] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [209] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [210] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [210] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [211] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [211] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [212] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [212] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [213] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [213] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [214] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [214] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [215] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [215] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [216] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [216] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [217] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [217] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [218] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [218] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [219] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [219] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [220] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [220] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [221] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [221] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [222] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [222] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [223] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [223] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [224] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [224] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [225] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [225] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [226] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [226] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [227] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [227] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [228] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [228] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [229] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [229] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [230] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [230] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [231] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [231] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [232] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [232] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [233] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [233] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [234] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [234] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [235] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [235] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [236] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [236] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [237] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [237] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [238] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [238] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [239] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [239] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [240] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [240] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [241] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [241] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [242] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [242] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [243] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [243] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [244] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [244] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [245] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [245] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [246] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [246] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [247] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [247] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [248] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [248] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [249] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [249] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [250] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [250] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [251] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [251] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [252] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [252] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [253] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [253] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [254] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [254] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [255] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [255] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 cio_test_o [0] "logic cio_test_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 cio_test_o [0] "logic cio_test_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 cio_test_o [1] "logic cio_test_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 cio_test_o [1] "logic cio_test_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 cio_test_o [2] "logic cio_test_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 cio_test_o [2] "logic cio_test_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 cio_test_o [3] "logic cio_test_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 cio_test_o [3] "logic cio_test_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 cio_test_o [4] "logic cio_test_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 cio_test_o [4] "logic cio_test_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 cio_test_o [5] "logic cio_test_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 cio_test_o [5] "logic cio_test_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 cio_test_o [6] "logic cio_test_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 cio_test_o [6] "logic cio_test_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 cio_test_o [7] "logic cio_test_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 cio_test_o [7] "logic cio_test_o[7:0]" +CHECKSUM: "1611327958 113940473" +INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top +ANNOTATION: "VC_COV_UNR" +Condition 20 "3585319611" "(reg_we && ((!addrmiss))) 1 -1" (2 "10") +ANNOTATION: "VC_COV_UNR" +Condition 22 "1026062099" "(addrmiss | wr_err | intg_err) 1 -1" (4 "100") +CHECKSUM: "698853052 2882888745" +INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic +ANNOTATION: "VC_COV_UNR" +Condition 1 "2104830463" "(cmd_i == Init) 1 -1" (1 "0") +CHECKSUM: "3727300757 2582220255" +INSTANCE: tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +State InitDescrSt "3204" +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +State InitDescrWaitSt "2472" +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +State IntegDigFinSt "1765" +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +State IntegDigPadSt "855" +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +State IntegDigSt "1890" +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +State IntegDigWaitSt "2290" +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +State IntegScrSt "3418" +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +State IntegScrWaitSt "2207" +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +Transition IdleSt->IntegDigClrSt "1357->2625" +Fsm error_q "2410907799" +ANNOTATION: "VC_COV_UNR" +Transition CheckFailError->FsmStateError "6->7" +Fsm error_q "2410907799" +ANNOTATION: "VC_COV_UNR" +Transition CheckFailError->MacroEccCorrError "6->2" +Fsm error_q "2410907799" +ANNOTATION: "VC_COV_UNR" +Transition FsmStateError->CheckFailError "7->6" +Fsm error_q "2410907799" +ANNOTATION: "VC_COV_UNR" +Transition FsmStateError->MacroEccCorrError "7->2" +CHECKSUM: "3162909804 3458814989" +INSTANCE: tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf +Fsm state_q "4141872371" +ANNOTATION: "VC_COV_UNR" +Transition ResetSt->IdleSt "694->745" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +State MacroEccCorrError "2" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition CheckFailError->AccessError "6->5" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition CheckFailError->FsmStateError "6->7" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition FsmStateError->AccessError "7->5" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition FsmStateError->CheckFailError "7->6" +CHECKSUM: "3162909804 3458814989" +INSTANCE: tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf +Fsm state_q "4141872371" +ANNOTATION: "VC_COV_UNR" +Transition ResetSt->IdleSt "694->745" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition AccessError->CheckFailError "5->6" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition AccessError->MacroEccCorrError "5->2" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition CheckFailError->AccessError "6->5" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition CheckFailError->FsmStateError "6->7" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition CheckFailError->MacroEccCorrError "6->2" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition FsmStateError->AccessError "7->5" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition FsmStateError->CheckFailError "7->6" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition FsmStateError->MacroEccCorrError "7->2" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition MacroEccCorrError->AccessError "2->5" +CHECKSUM: "3162909804 3458814989" +INSTANCE: tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf +Fsm state_q "4141872371" +ANNOTATION: "VC_COV_UNR" +Transition ResetSt->IdleSt "694->745" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition AccessError->CheckFailError "5->6" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition AccessError->MacroEccCorrError "5->2" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition CheckFailError->AccessError "6->5" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition CheckFailError->FsmStateError "6->7" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition CheckFailError->MacroEccCorrError "6->2" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition FsmStateError->AccessError "7->5" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition FsmStateError->CheckFailError "7->6" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition FsmStateError->MacroEccCorrError "7->2" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition MacroEccCorrError->AccessError "2->5" +CHECKSUM: "3162909804 3458814989" +INSTANCE: tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf +Fsm state_q "4141872371" +ANNOTATION: "VC_COV_UNR" +Transition ResetSt->IdleSt "694->745" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition AccessError->CheckFailError "5->6" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition AccessError->MacroEccCorrError "5->2" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition CheckFailError->AccessError "6->5" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition CheckFailError->FsmStateError "6->7" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition CheckFailError->MacroEccCorrError "6->2" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition FsmStateError->AccessError "7->5" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition FsmStateError->CheckFailError "7->6" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition FsmStateError->MacroEccCorrError "7->2" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition MacroEccCorrError->AccessError "2->5" +CHECKSUM: "3162909804 3458814989" +INSTANCE: tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf +Fsm state_q "4141872371" +ANNOTATION: "VC_COV_UNR" +Transition ResetSt->IdleSt "694->745" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition AccessError->CheckFailError "5->6" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition AccessError->MacroEccCorrError "5->2" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition CheckFailError->AccessError "6->5" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition CheckFailError->FsmStateError "6->7" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition CheckFailError->MacroEccCorrError "6->2" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition FsmStateError->AccessError "7->5" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition FsmStateError->CheckFailError "7->6" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition FsmStateError->MacroEccCorrError "7->2" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition MacroEccCorrError->AccessError "2->5" +CHECKSUM: "3727300757 2582220255" +INSTANCE: tb.dut.gen_partitions[7].gen_buffered.u_part_buf +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +State IntegDigPadSt "855" +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +Transition CnstyReadWaitSt->CnstyReadSt "2684->107" +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +Transition InitWaitSt->InitSt "945->3367" +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +Transition IntegDigClrSt->IdleSt "2625->1357" +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +Transition IntegDigClrSt->IntegDigSt "2625->1890" +Fsm error_q "2410907799" +ANNOTATION: "VC_COV_UNR" +Transition CheckFailError->FsmStateError "6->7" +Fsm error_q "2410907799" +ANNOTATION: "VC_COV_UNR" +Transition CheckFailError->MacroEccCorrError "6->2" +Fsm error_q "2410907799" +ANNOTATION: "VC_COV_UNR" +Transition FsmStateError->CheckFailError "7->6" +Fsm error_q "2410907799" +ANNOTATION: "VC_COV_UNR" +Transition FsmStateError->MacroEccCorrError "7->2" +CHECKSUM: "3727300757 2582220255" +INSTANCE: tb.dut.gen_partitions[8].gen_buffered.u_part_buf +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +State IntegDigPadSt "855" +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +Transition CnstyReadWaitSt->CnstyReadSt "2684->107" +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +Transition InitWaitSt->InitSt "945->3367" +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +Transition IntegDigClrSt->IdleSt "2625->1357" +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +Transition IntegDigClrSt->IntegDigSt "2625->1890" +Fsm error_q "2410907799" +ANNOTATION: "VC_COV_UNR" +Transition CheckFailError->FsmStateError "6->7" +Fsm error_q "2410907799" +ANNOTATION: "VC_COV_UNR" +Transition CheckFailError->MacroEccCorrError "6->2" +Fsm error_q "2410907799" +ANNOTATION: "VC_COV_UNR" +Transition FsmStateError->CheckFailError "7->6" +Fsm error_q "2410907799" +ANNOTATION: "VC_COV_UNR" +Transition FsmStateError->MacroEccCorrError "7->2" +CHECKSUM: "3727300757 2582220255" +INSTANCE: tb.dut.gen_partitions[9].gen_buffered.u_part_buf +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +State IntegDigPadSt "855" +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +Transition CnstyReadWaitSt->CnstyReadSt "2684->107" +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +Transition InitWaitSt->InitSt "945->3367" +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +Transition IntegDigClrSt->IdleSt "2625->1357" +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +Transition IntegDigClrSt->IntegDigSt "2625->1890" +Fsm error_q "2410907799" +ANNOTATION: "VC_COV_UNR" +Transition CheckFailError->FsmStateError "6->7" +Fsm error_q "2410907799" +ANNOTATION: "VC_COV_UNR" +Transition CheckFailError->MacroEccCorrError "6->2" +Fsm error_q "2410907799" +ANNOTATION: "VC_COV_UNR" +Transition FsmStateError->CheckFailError "7->6" +Fsm error_q "2410907799" +ANNOTATION: "VC_COV_UNR" +Transition FsmStateError->MacroEccCorrError "7->2" +CHECKSUM: "903559179 4258846959" +INSTANCE: tb.dut.u_otp_ctrl_dai +Fsm error_q "1085514286" +ANNOTATION: "VC_COV_UNR" +Transition AccessError->MacroEccCorrError "5->2" +Fsm error_q "1085514286" +ANNOTATION: "VC_COV_UNR" +Transition FsmStateError->AccessError "7->5" +Fsm error_q "1085514286" +ANNOTATION: "VC_COV_UNR" +Transition FsmStateError->MacroEccCorrError "7->2" +CHECKSUM: "1158524476 2379312231" +INSTANCE: tb.dut.u_otp_ctrl_kdi +Fsm state_q "2979668442" +ANNOTATION: "VC_COV_UNR" +Transition DigWaitSt->DigLoadSt "913->183" +CHECKSUM: "165375753 304066633" +INSTANCE: tb.dut.u_otp_ctrl_lfsr_timer +ANNOTATION: "VC_COV_UNR" +Condition 15 "1557524712" "(edn_req_o & edn_ack_i) 1 -1" (1 "01") +CHECKSUM: "189358556 3907569978" +INSTANCE: tb.dut +ANNOTATION: "VC_COV_UNR" +Condition 1 "83486244" "(tlul_part_sel_oh != '0) 1 -1" (1 "0") +ANNOTATION: "VC_COV_UNR" +Condition 2 "1218027842" "(((|part_tlul_gnt)) | tlul_oob_err_q) 1 -1" (2 "01") +ANNOTATION: "VC_COV_UNR" +Condition 3 "3291433605" "(((|part_tlul_rvalid)) | tlul_oob_err_q) 1 -1" (2 "01") +ANNOTATION: "VC_COV_UNR" +Condition 4 "3779635843" "(fatal_bus_integ_error_q | ((|intg_error))) 1 -1" (3 "10") +ANNOTATION: "VC_COV_UNR" +Condition 5 "1876397257" "(part_error[k] == MacroError) 1 -1" (2 "1") +ANNOTATION: "VC_COV_UNR" +Condition 10 "2334459673" "(otp_rvalid & otp_fifo_valid) 1 -1" (2 "10") +ANNOTATION: "VC_COV_UNR" +Condition 13 "1319238213" "(reg2hw.direct_access_cmd.digest.qe | reg2hw.direct_access_cmd.wr.qe | reg2hw.direct_access_cmd.rd.qe) 1 -1" (2 "001") +ANNOTATION: "VC_COV_UNR" +Condition 13 "1319238213" "(reg2hw.direct_access_cmd.digest.qe | reg2hw.direct_access_cmd.wr.qe | reg2hw.direct_access_cmd.rd.qe) 1 -1" (3 "010") +ANNOTATION: "VC_COV_UNR" +Condition 13 "1319238213" "(reg2hw.direct_access_cmd.digest.qe | reg2hw.direct_access_cmd.wr.qe | reg2hw.direct_access_cmd.rd.qe) 1 -1" (4 "100") +ANNOTATION: "VC_COV_UNR" +Condition 24 "619555966" "(otp_arb_valid & otp_rsp_fifo_ready) 1 -1" (2 "10") +ANNOTATION: "vcs_gen_start:k=10:vcs_gen_end:VC_COV_UNR" +Condition 42 "1479216946" "(({tlul_addr, 2'b0} >= 11'b11110101000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[10].PartEnd)) 1 -1" (2 "10") +CHECKSUM: "1746381268 1271541636" +INSTANCE: tb.dut.u_reg_core.u_socket +ANNOTATION: "VC_COV_UNR" +Condition 3 "118253128" "(tl_t_o.a_valid & tl_t_i.a_ready) 1 -1" (1 "01") +CHECKSUM: "74367784 3785313510" +INSTANCE: tb.dut.u_reg_core.u_reg_if +ANNOTATION: "VC_COV_UNR" +Condition 18 "3340270436" "(addr_align_err | malformed_meta_err | tl_err | instr_error | intg_error) 1 -1" (5 "01000") +CHECKSUM: "74367784 3785313510" +INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_reg_if +ANNOTATION: "VC_COV_UNR" +Condition 18 "3340270436" "(addr_align_err | malformed_meta_err | tl_err | instr_error | intg_error) 1 -1" (5 "01000") +CHECKSUM: "4255502330 3274445021" +INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field3 +ANNOTATION: "VC_COV_UNR" +Condition 1 "2397158838" "(wr_en ? wr_data : qs) 1 -1" (2 "1") +CHECKSUM: "4255502330 3274445021" +INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field4 +ANNOTATION: "VC_COV_UNR" +Condition 1 "2397158838" "(wr_en ? wr_data : qs) 1 -1" (2 "1") +CHECKSUM: "4255502330 3274445021" +INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field5 +ANNOTATION: "VC_COV_UNR" +Condition 1 "2397158838" "(wr_en ? wr_data : qs) 1 -1" (2 "1") +CHECKSUM: "4255502330 3274445021" +INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field6 +ANNOTATION: "VC_COV_UNR" +Condition 1 "2397158838" "(wr_en ? wr_data : qs) 1 -1" (2 "1") +CHECKSUM: "4255502330 3274445021" +INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field7 +ANNOTATION: "VC_COV_UNR" +Condition 1 "2397158838" "(wr_en ? wr_data : qs) 1 -1" (2 "1") +CHECKSUM: "4255502330 3274445021" +INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field8 +ANNOTATION: "VC_COV_UNR" +Condition 1 "2397158838" "(wr_en ? wr_data : qs) 1 -1" (2 "1") +CHECKSUM: "4255502330 3274445021" +INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field2 +ANNOTATION: "VC_COV_UNR" +Condition 1 "2397158838" "(wr_en ? wr_data : qs) 1 -1" (2 "1") +CHECKSUM: "4255502330 3274445021" +INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field4 +ANNOTATION: "VC_COV_UNR" +Condition 1 "2397158838" "(wr_en ? wr_data : qs) 1 -1" (2 "1") +CHECKSUM: "4255502330 3274445021" +INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field5 +ANNOTATION: "VC_COV_UNR" +Condition 1 "2397158838" "(wr_en ? wr_data : qs) 1 -1" (2 "1") +CHECKSUM: "4255502330 3274445021" +INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field2 +ANNOTATION: "VC_COV_UNR" +Condition 1 "2397158838" "(wr_en ? wr_data : qs) 1 -1" (2 "1") +CHECKSUM: "4255502330 3274445021" +INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field3 +ANNOTATION: "VC_COV_UNR" +Condition 1 "2397158838" "(wr_en ? wr_data : qs) 1 -1" (2 "1") +CHECKSUM: "4255502330 3858770513" +INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field3 +ANNOTATION: "VC_COV_UNR" +Condition 1 "1301967206" "(wr_en ? wr_data : qs) 1 -1" (2 "1") +CHECKSUM: "4255502330 3858770513" +INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field1 +ANNOTATION: "VC_COV_UNR" +Condition 1 "1301967206" "(wr_en ? wr_data : qs) 1 -1" (2 "1") +CHECKSUM: "4255502330 3201188367" +INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field0 +ANNOTATION: "VC_COV_UNR" +Condition 1 "1807203824" "(wr_en ? wr_data : qs) 1 -1" (2 "1") +CHECKSUM: "2099741489 1445279304" +INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field0.wr_en_data_arb +ANNOTATION: "VC_COV_UNR" +Condition 1 "505266581" "(we | de) 1 -1" (2 "01") +CHECKSUM: "2099741489 1445279304" +INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field1.wr_en_data_arb +ANNOTATION: "VC_COV_UNR" +Condition 1 "505266581" "(we | de) 1 -1" (2 "01") +CHECKSUM: "2099741489 3636044484" +INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field2.wr_en_data_arb +ANNOTATION: "VC_COV_UNR" +Condition 1 "505266581" "(we | de) 1 -1" (2 "01") +ANNOTATION: "VC_COV_UNR" +Condition 2 "2306794614" "((de ? d : q) & (we ? ((~wd)) : '1)) 1 -1" (2 "10") +ANNOTATION: "VC_COV_UNR" +Condition 2 "2306794614" "((de ? d : q) & (we ? ((~wd)) : '1)) 1 -1" (3 "11") +ANNOTATION: "VC_COV_UNR" +Condition 3 "2289961458" "(de ? d : q) 1 -1" (2 "1") +CHECKSUM: "2099741489 1283100255" +INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field6.wr_en_data_arb +ANNOTATION: "VC_COV_UNR" +Condition 1 "505266581" "(we | de) 1 -1" (2 "01") +CHECKSUM: "2099741489 1077956591" +INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field0.wr_en_data_arb +ANNOTATION: "VC_COV_UNR" +Condition 1 "505266581" "(we | de) 1 -1" (2 "01") +CHECKSUM: "2099741489 4164822555" +INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field1.wr_en_data_arb +ANNOTATION: "VC_COV_UNR" +Condition 1 "505266581" "(we | de) 1 -1" (2 "01") +CHECKSUM: "1335069400 1628136802" +INSTANCE: tb.dut.u_tlul_adapter_sram +ANNOTATION: "VC_COV_UNR" +Condition 2 "3455933711" "(reqfifo_rdata.op == OpRead) 1 -1" (1 "0") +ANNOTATION: "VC_COV_UNR" +Condition 7 "3253769203" "(intg_error | rsp_fifo_error | intg_error_q) 1 -1" (2 "001") +ANNOTATION: "VC_COV_UNR" +Condition 16 "3469950311" "(wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error) 1 -1" (7 "100000") +ANNOTATION: "VC_COV_UNR" +Condition 19 "709191362" "(req_o & gnt_i) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 20 "3623514242" "(d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead)) 1 -1" (1 "0111") +ANNOTATION: "VC_COV_UNR" +Condition 20 "3623514242" "(d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead)) 1 -1" (2 "1011") +ANNOTATION: "VC_COV_UNR" +Condition 20 "3623514242" "(d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead)) 1 -1" (4 "1110") +ANNOTATION: "VC_COV_UNR" +Condition 24 "2807788926" "((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)) 1 -1" (2 "1") +ANNOTATION: "VC_COV_UNR" +Condition 25 "561780173" "(vld_rd_rsp && reqfifo_rdata.error) 1 -1" (3 "11") +ANNOTATION: "VC_COV_UNR" +Condition 32 "939039548" "(d_valid && d_error) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 33 "1798941048" "((gnt_i | error_internal) & reqfifo_wready & sramreqfifo_wready) 1 -1" (3 "110") +ANNOTATION: "VC_COV_UNR" +Condition 35 "2770863641" "(tl_i_int.a_valid & reqfifo_wready & ((~error_internal))) 1 -1" (1 "011") +ANNOTATION: "VC_COV_UNR" +Condition 40 "2041272341" "(sram_ack & ((~we_o))) 1 -1" (2 "10") +ANNOTATION: "VC_COV_UNR" +Condition 41 "721931741" "(rvalid_i & reqfifo_rvalid) 1 -1" (2 "10") +ANNOTATION: "vcs_gen_start:i=0:vcs_gen_end:VC_COV_UNR" +Condition 46 "3548937587" "(((|wmask_intg)) & ((|wdata_intg))) 1 -1" (1 "01") +CHECKSUM: "2974379282 2951929728" +INSTANCE: tb.dut.u_part_sel_idx +ANNOTATION: "vcs_gen_start:level=0,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 1 "2750612666" "(gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]) 1 -1" (1 "00") +CHECKSUM: "2974379282 2951929728" +INSTANCE: tb.dut.u_otp_ctrl_dai.u_part_sel_idx +ANNOTATION: "vcs_gen_start:level=0,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 1 "2750612666" "(gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]) 1 -1" (1 "00") +CHECKSUM: "2032872600 2493710885" +INSTANCE: tb.dut.u_edn_arb +ANNOTATION: "vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 10 "635964333" "(req_i[0] & gen_normal_case.prio_mask_q[0]) 1 -1" (1 "01") +ANNOTATION: "vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 11 "2124571033" "(req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i) 1 -1" (1 "011") +CHECKSUM: "2032872600 3869070406" +INSTANCE: tb.dut.u_otp_arb +ANNOTATION: "vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR" +Condition 118 "3667925887" "(((~gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[6].C0])) | (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[6].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[6].C1])) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR" +Condition 119 "2125455247" "(((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[6].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[6].C1]) 1 -1" (1 "01") +ANNOTATION: "vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR" +Condition 119 "2125455247" "(((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[6].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[6].C1]) 1 -1" (3 "11") +ANNOTATION: "vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR" +Condition 120 "2371949082" "(gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[6].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[6].C1]) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR" +Condition 121 "4111290463" "(gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[6].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[6].C0]) 1 -1" (3 "10") +ANNOTATION: "vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR" +Condition 124 "2230658126" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[6].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel))) 1 -1" (2 "10") +ANNOTATION: "vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR" +Condition 125 "1884579875" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[6].Pa] & gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel) 1 -1" (3 "11") +ANNOTATION: "vcs_gen_start:level=4,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 137 "1731868698" "(req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[0].Pa] & ready_i) 1 -1" (1 "011") +ANNOTATION: "vcs_gen_start:level=4,offset=1:vcs_gen_end:VC_COV_UNR" +Condition 142 "1060032545" "(req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[1].Pa] & ready_i) 1 -1" (1 "011") +ANNOTATION: "vcs_gen_start:level=4,offset=2:vcs_gen_end:VC_COV_UNR" +Condition 147 "1299459822" "(req_i[2] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[2].Pa] & ready_i) 1 -1" (1 "011") +ANNOTATION: "vcs_gen_start:level=4,offset=3:vcs_gen_end:VC_COV_UNR" +Condition 152 "358663893" "(req_i[3] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[3].Pa] & ready_i) 1 -1" (1 "011") +ANNOTATION: "vcs_gen_start:level=4,offset=4:vcs_gen_end:VC_COV_UNR" +Condition 157 "2252512415" "(req_i[4] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[4].Pa] & ready_i) 1 -1" (1 "011") +ANNOTATION: "vcs_gen_start:level=4,offset=5:vcs_gen_end:VC_COV_UNR" +Condition 162 "3730207908" "(req_i[5] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[5].Pa] & ready_i) 1 -1" (1 "011") +ANNOTATION: "vcs_gen_start:level=4,offset=6:vcs_gen_end:VC_COV_UNR" +Condition 167 "2886503019" "(req_i[6] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[6].Pa] & ready_i) 1 -1" (1 "011") +ANNOTATION: "vcs_gen_start:level=4,offset=7:vcs_gen_end:VC_COV_UNR" +Condition 172 "4095238736" "(req_i[7] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[7].Pa] & ready_i) 1 -1" (1 "011") +ANNOTATION: "vcs_gen_start:level=4,offset=8:vcs_gen_end:VC_COV_UNR" +Condition 177 "296455364" "(req_i[8] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[8].Pa] & ready_i) 1 -1" (1 "011") +ANNOTATION: "vcs_gen_start:level=4,offset=9:vcs_gen_end:VC_COV_UNR" +Condition 182 "1237279999" "(req_i[9] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[9].Pa] & ready_i) 1 -1" (1 "011") +ANNOTATION: "vcs_gen_start:level=4,offset=10:vcs_gen_end:VC_COV_UNR" +Condition 187 "565898016" "(req_i[10] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[10].Pa] & ready_i) 1 -1" (1 "011") +ANNOTATION: "vcs_gen_start:level=4,offset=11:vcs_gen_end:VC_COV_UNR" +Condition 192 "2218826282" "(req_i[11] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[11].Pa] & ready_i) 1 -1" (1 "011") +ANNOTATION: "vcs_gen_start:level=4,offset=12:vcs_gen_end:VC_COV_UNR" +Condition 197 "4217824807" "(req_i[12] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[12].Pa] & ready_i) 1 -1" (1 "011") +ANNOTATION: "vcs_gen_start:level=4,offset=13:vcs_gen_end:VC_COV_UNR" +Condition 201 "1343278836" "(req_i[13] & gen_normal_case.prio_mask_q[13]) 1 -1" (2 "10") +ANNOTATION: "vcs_gen_start:level=4,offset=13:vcs_gen_end:VC_COV_UNR" +Condition 201 "1343278836" "(req_i[13] & gen_normal_case.prio_mask_q[13]) 1 -1" (3 "11") +ANNOTATION: "vcs_gen_start:level=4,offset=13:vcs_gen_end:VC_COV_UNR" +Condition 202 "1587320621" "(req_i[13] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[13].Pa] & ready_i) 1 -1" (1 "011") +ANNOTATION: "vcs_gen_start:level=4,offset=13:vcs_gen_end:VC_COV_UNR" +Condition 202 "1587320621" "(req_i[13] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[13].Pa] & ready_i) 1 -1" (2 "101") +ANNOTATION: "vcs_gen_start:level=4,offset=13:vcs_gen_end:VC_COV_UNR" +Condition 202 "1587320621" "(req_i[13] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[13].Pa] & ready_i) 1 -1" (3 "110") +ANNOTATION: "vcs_gen_start:level=4,offset=13:vcs_gen_end:VC_COV_UNR" +Condition 202 "1587320621" "(req_i[13] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[13].Pa] & ready_i) 1 -1" (4 "111") +ANNOTATION: "vcs_gen_start:level=4,offset=13:vcs_gen_end:VC_COV_UNR" +Condition 204 "3359315662" "(gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[13].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[13].Pa] & ((~ready_i)))) 1 -1" (1 "00") +ANNOTATION: "vcs_gen_start:level=4,offset=13:vcs_gen_end:VC_COV_UNR" +Condition 204 "3359315662" "(gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[13].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[13].Pa] & ((~ready_i)))) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=4,offset=13:vcs_gen_end:VC_COV_UNR" +Condition 205 "87484194" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[13].Pa] & ((~ready_i))) 1 -1" (2 "10") +ANNOTATION: "vcs_gen_start:level=4,offset=13:vcs_gen_end:VC_COV_UNR" +Condition 205 "87484194" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[13].Pa] & ((~ready_i))) 1 -1" (3 "11") +CHECKSUM: "2032872600 835765284" +INSTANCE: tb.dut.u_scrmbl_mtx +ANNOTATION: "vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 10 "1993460578" "(((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) | (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])) 1 -1" (1 "00") +ANNOTATION: "vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 10 "1993460578" "(((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) | (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 11 "1567077924" "(((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1]) 1 -1" (1 "01") +ANNOTATION: "vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 12 "3158492049" "(gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C1]) 1 -1" (3 "10") +ANNOTATION: "vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 13 "96040801" "(gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0]) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 14 "1193252123" "(gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0]) 1 -1" (1 "0") +ANNOTATION: "vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 15 "445016888" "(gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0]) 1 -1" (1 "0") +ANNOTATION: "vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 16 "1314162940" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel))) 1 -1" (1 "01") +ANNOTATION: "vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 16 "1314162940" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel))) 1 -1" (3 "11") +ANNOTATION: "vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 17 "2175331913" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) 1 -1" (2 "10") +ANNOTATION: "vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 18 "2134997267" "(gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].C0]) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 28 "2070917326" "(((~gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[0].C0])) | (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[0].C1])) 1 -1" (1 "00") +ANNOTATION: "vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 28 "2070917326" "(((~gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[0].C0])) | (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[0].C1])) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 29 "3264610632" "(((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[0].C1]) 1 -1" (1 "01") +ANNOTATION: "vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 29 "3264610632" "(((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[0].C1]) 1 -1" (3 "11") +ANNOTATION: "vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 30 "1496330476" "(gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[0].C1]) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 30 "1496330476" "(gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[0].C1]) 1 -1" (3 "10") +ANNOTATION: "vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 31 "475390859" "(gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[0].C0]) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 31 "475390859" "(gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[0].C0]) 1 -1" (3 "10") +ANNOTATION: "vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 32 "3851361741" "(gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[0].C0]) 1 -1" (1 "0") +ANNOTATION: "vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 33 "834897871" "(gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[0].C0]) 1 -1" (1 "0") +ANNOTATION: "vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 34 "827710109" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel))) 1 -1" (1 "01") +ANNOTATION: "vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 34 "827710109" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel))) 1 -1" (2 "10") +ANNOTATION: "vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 34 "827710109" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel))) 1 -1" (3 "11") +ANNOTATION: "vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 35 "1296065718" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel) 1 -1" (2 "10") +ANNOTATION: "vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 35 "1296065718" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel) 1 -1" (3 "11") +ANNOTATION: "vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 36 "2587069038" "(gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].C0]) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=2,offset=1:vcs_gen_end:VC_COV_UNR" +Condition 45 "1389557192" "(gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].C0]) 1 -1" (3 "10") +ANNOTATION: "vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 64 "210767427" "(((~gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[0].C0])) | (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[0].C1])) 1 -1" (1 "00") +ANNOTATION: "vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 64 "210767427" "(((~gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[0].C0])) | (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[0].C1])) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 65 "433071849" "(((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[0].C1]) 1 -1" (1 "01") +ANNOTATION: "vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 65 "433071849" "(((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[0].C1]) 1 -1" (3 "11") +ANNOTATION: "vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 66 "676485814" "(gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[0].C1]) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 66 "676485814" "(gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[0].C1]) 1 -1" (3 "10") +ANNOTATION: "vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 67 "2859603461" "(gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[0].C0]) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 67 "2859603461" "(gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[0].C0]) 1 -1" (3 "10") +ANNOTATION: "vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 68 "499725081" "(gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[0].C0]) 1 -1" (1 "0") +ANNOTATION: "vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 69 "2136469291" "(gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[0].C0]) 1 -1" (1 "0") +ANNOTATION: "vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 70 "3457930055" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel))) 1 -1" (1 "01") +ANNOTATION: "vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 70 "3457930055" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel))) 1 -1" (2 "10") +ANNOTATION: "vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 70 "3457930055" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel))) 1 -1" (3 "11") +ANNOTATION: "vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 71 "1202012" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[0].Pa] & gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel) 1 -1" (2 "10") +ANNOTATION: "vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 71 "1202012" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[0].Pa] & gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel) 1 -1" (3 "11") +ANNOTATION: "vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 72 "3948011572" "(gen_normal_case.mask_tree[gen_normal_case.gen_tree[3].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[0].C0]) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR" +Condition 73 "2058222911" "(((~gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[1].C0])) | (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[1].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[1].C1])) 1 -1" (1 "00") +ANNOTATION: "vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR" +Condition 73 "2058222911" "(((~gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[1].C0])) | (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[1].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[1].C1])) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR" +Condition 74 "3215638766" "(((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[1].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[1].C1]) 1 -1" (1 "01") +ANNOTATION: "vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR" +Condition 74 "3215638766" "(((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[1].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[1].C1]) 1 -1" (3 "11") +ANNOTATION: "vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR" +Condition 75 "3769836816" "(gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[1].C1]) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR" +Condition 75 "3769836816" "(gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[1].C1]) 1 -1" (3 "10") +ANNOTATION: "vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR" +Condition 76 "2034837615" "(gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[1].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[1].C0]) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR" +Condition 76 "2034837615" "(gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[1].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[1].C0]) 1 -1" (3 "10") +ANNOTATION: "vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR" +Condition 77 "2239186227" "(gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[1].C0]) 1 -1" (1 "0") +ANNOTATION: "vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR" +Condition 78 "2004432906" "(gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[1].C0]) 1 -1" (1 "0") +ANNOTATION: "vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR" +Condition 79 "1357880086" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel))) 1 -1" (1 "01") +ANNOTATION: "vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR" +Condition 79 "1357880086" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel))) 1 -1" (2 "10") +ANNOTATION: "vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR" +Condition 79 "1357880086" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel))) 1 -1" (3 "11") +ANNOTATION: "vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR" +Condition 80 "3927989974" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[1].Pa] & gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel) 1 -1" (2 "10") +ANNOTATION: "vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR" +Condition 80 "3927989974" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[1].Pa] & gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel) 1 -1" (3 "11") +ANNOTATION: "vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR" +Condition 81 "598777746" "(gen_normal_case.mask_tree[gen_normal_case.gen_tree[3].gen_level[1].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[1].C0]) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR" +Condition 81 "598777746" "(gen_normal_case.mask_tree[gen_normal_case.gen_tree[3].gen_level[1].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[1].C0]) 1 -1" (3 "10") +ANNOTATION: "vcs_gen_start:level=3,offset=2:vcs_gen_end:VC_COV_UNR" +Condition 82 "3219580251" "(((~gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[2].C0])) | (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[2].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[2].C1])) 1 -1" (1 "00") +ANNOTATION: "vcs_gen_start:level=3,offset=2:vcs_gen_end:VC_COV_UNR" +Condition 82 "3219580251" "(((~gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[2].C0])) | (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[2].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[2].C1])) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=3,offset=2:vcs_gen_end:VC_COV_UNR" +Condition 83 "26276459" "(((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[2].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[2].C1]) 1 -1" (1 "01") +ANNOTATION: "vcs_gen_start:level=3,offset=2:vcs_gen_end:VC_COV_UNR" +Condition 84 "1842145640" "(gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[2].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[2].C1]) 1 -1" (3 "10") +ANNOTATION: "vcs_gen_start:level=3,offset=2:vcs_gen_end:VC_COV_UNR" +Condition 85 "147158886" "(gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[2].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[2].C0]) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=3,offset=2:vcs_gen_end:VC_COV_UNR" +Condition 86 "2038251222" "(gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[2].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[2].C0]) 1 -1" (1 "0") +ANNOTATION: "vcs_gen_start:level=3,offset=2:vcs_gen_end:VC_COV_UNR" +Condition 87 "1520563742" "(gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[2].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[2].C0]) 1 -1" (1 "0") +ANNOTATION: "vcs_gen_start:level=3,offset=2:vcs_gen_end:VC_COV_UNR" +Condition 88 "2599996672" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[2].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel))) 1 -1" (1 "01") +ANNOTATION: "vcs_gen_start:level=3,offset=2:vcs_gen_end:VC_COV_UNR" +Condition 88 "2599996672" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[2].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel))) 1 -1" (3 "11") +ANNOTATION: "vcs_gen_start:level=3,offset=2:vcs_gen_end:VC_COV_UNR" +Condition 89 "193340754" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[2].Pa] & gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel) 1 -1" (2 "10") +ANNOTATION: "vcs_gen_start:level=3,offset=2:vcs_gen_end:VC_COV_UNR" +Condition 90 "2932823018" "(gen_normal_case.mask_tree[gen_normal_case.gen_tree[3].gen_level[2].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[2].C0]) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=3,offset=2:vcs_gen_end:VC_COV_UNR" +Condition 90 "2932823018" "(gen_normal_case.mask_tree[gen_normal_case.gen_tree[3].gen_level[2].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[2].C0]) 1 -1" (3 "10") +ANNOTATION: "vcs_gen_start:level=3,offset=5:vcs_gen_end:VC_COV_UNR" +Condition 109 "535495451" "(((~gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[5].C0])) | (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[5].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[5].C1])) 1 -1" (1 "00") +ANNOTATION: "vcs_gen_start:level=3,offset=5:vcs_gen_end:VC_COV_UNR" +Condition 109 "535495451" "(((~gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[5].C0])) | (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[5].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[5].C1])) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=3,offset=5:vcs_gen_end:VC_COV_UNR" +Condition 110 "3231051018" "(((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[5].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[5].C1]) 1 -1" (1 "01") +ANNOTATION: "vcs_gen_start:level=3,offset=5:vcs_gen_end:VC_COV_UNR" +Condition 111 "2023010" "(gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[5].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[5].C1]) 1 -1" (3 "10") +ANNOTATION: "vcs_gen_start:level=3,offset=5:vcs_gen_end:VC_COV_UNR" +Condition 112 "2223050582" "(gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[5].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[5].C0]) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=3,offset=5:vcs_gen_end:VC_COV_UNR" +Condition 113 "1661998521" "(gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[5].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[5].C0]) 1 -1" (1 "0") +ANNOTATION: "vcs_gen_start:level=3,offset=5:vcs_gen_end:VC_COV_UNR" +Condition 114 "328876404" "(gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[5].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[5].C0]) 1 -1" (1 "0") +ANNOTATION: "vcs_gen_start:level=3,offset=5:vcs_gen_end:VC_COV_UNR" +Condition 115 "1323463256" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[5].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel))) 1 -1" (1 "01") +ANNOTATION: "vcs_gen_start:level=3,offset=5:vcs_gen_end:VC_COV_UNR" +Condition 115 "1323463256" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[5].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel))) 1 -1" (3 "11") +ANNOTATION: "vcs_gen_start:level=3,offset=5:vcs_gen_end:VC_COV_UNR" +Condition 116 "2448561063" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[5].Pa] & gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel) 1 -1" (2 "10") +ANNOTATION: "vcs_gen_start:level=3,offset=5:vcs_gen_end:VC_COV_UNR" +Condition 117 "3273483488" "(gen_normal_case.mask_tree[gen_normal_case.gen_tree[3].gen_level[5].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[5].C0]) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR" +Condition 118 "3667925887" "(((~gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[6].C0])) | (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[6].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[6].C1])) 1 -1" (1 "00") +ANNOTATION: "vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR" +Condition 118 "3667925887" "(((~gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[6].C0])) | (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[6].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[6].C1])) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR" +Condition 119 "2125455247" "(((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[6].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[6].C1]) 1 -1" (1 "01") +ANNOTATION: "vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR" +Condition 120 "2371949082" "(gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[6].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[6].C1]) 1 -1" (3 "10") +ANNOTATION: "vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR" +Condition 121 "4111290463" "(gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[6].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[6].C0]) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR" +Condition 122 "2669309532" "(gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[6].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[6].C0]) 1 -1" (1 "0") +ANNOTATION: "vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR" +Condition 123 "1044549472" "(gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[6].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[6].C0]) 1 -1" (1 "0") +ANNOTATION: "vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR" +Condition 124 "2230658126" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[6].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel))) 1 -1" (1 "01") +ANNOTATION: "vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR" +Condition 124 "2230658126" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[6].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel))) 1 -1" (3 "11") +ANNOTATION: "vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR" +Condition 125 "1884579875" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[6].Pa] & gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel) 1 -1" (2 "10") +ANNOTATION: "vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR" +Condition 126 "1315088536" "(gen_normal_case.mask_tree[gen_normal_case.gen_tree[3].gen_level[6].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[6].C0]) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=4,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 136 "2430171309" "(req_i[0] & gen_normal_case.prio_mask_q[0]) 1 -1" (1 "01") +ANNOTATION: "vcs_gen_start:level=4,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 136 "2430171309" "(req_i[0] & gen_normal_case.prio_mask_q[0]) 1 -1" (2 "10") +ANNOTATION: "vcs_gen_start:level=4,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 136 "2430171309" "(req_i[0] & gen_normal_case.prio_mask_q[0]) 1 -1" (3 "11") +ANNOTATION: "vcs_gen_start:level=4,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 137 "1731868698" "(req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[0].Pa] & ready_i) 1 -1" (3 "110") +ANNOTATION: "vcs_gen_start:level=4,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 139 "4029129651" "(gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[0].Pa] & ((~ready_i)))) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=4,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 140 "2870412309" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[0].Pa] & ((~ready_i))) 1 -1" (3 "11") +ANNOTATION: "vcs_gen_start:level=4,offset=1:vcs_gen_end:VC_COV_UNR" +Condition 141 "2424159075" "(req_i[1] & gen_normal_case.prio_mask_q[1]) 1 -1" (1 "01") +ANNOTATION: "vcs_gen_start:level=4,offset=1:vcs_gen_end:VC_COV_UNR" +Condition 141 "2424159075" "(req_i[1] & gen_normal_case.prio_mask_q[1]) 1 -1" (2 "10") +ANNOTATION: "vcs_gen_start:level=4,offset=1:vcs_gen_end:VC_COV_UNR" +Condition 141 "2424159075" "(req_i[1] & gen_normal_case.prio_mask_q[1]) 1 -1" (3 "11") +ANNOTATION: "vcs_gen_start:level=4,offset=1:vcs_gen_end:VC_COV_UNR" +Condition 142 "1060032545" "(req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[1].Pa] & ready_i) 1 -1" (3 "110") +ANNOTATION: "vcs_gen_start:level=4,offset=1:vcs_gen_end:VC_COV_UNR" +Condition 144 "2044991706" "(gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[1].Pa] & ((~ready_i)))) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=4,offset=1:vcs_gen_end:VC_COV_UNR" +Condition 144 "2044991706" "(gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[1].Pa] & ((~ready_i)))) 1 -1" (3 "10") +ANNOTATION: "vcs_gen_start:level=4,offset=1:vcs_gen_end:VC_COV_UNR" +Condition 145 "3094700199" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[1].Pa] & ((~ready_i))) 1 -1" (3 "11") +ANNOTATION: "vcs_gen_start:level=4,offset=2:vcs_gen_end:VC_COV_UNR" +Condition 146 "2442198833" "(req_i[2] & gen_normal_case.prio_mask_q[2]) 1 -1" (1 "01") +ANNOTATION: "vcs_gen_start:level=4,offset=2:vcs_gen_end:VC_COV_UNR" +Condition 146 "2442198833" "(req_i[2] & gen_normal_case.prio_mask_q[2]) 1 -1" (2 "10") +ANNOTATION: "vcs_gen_start:level=4,offset=2:vcs_gen_end:VC_COV_UNR" +Condition 146 "2442198833" "(req_i[2] & gen_normal_case.prio_mask_q[2]) 1 -1" (3 "11") +ANNOTATION: "vcs_gen_start:level=4,offset=2:vcs_gen_end:VC_COV_UNR" +Condition 147 "1299459822" "(req_i[2] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[2].Pa] & ready_i) 1 -1" (3 "110") +ANNOTATION: "vcs_gen_start:level=4,offset=2:vcs_gen_end:VC_COV_UNR" +Condition 149 "303405805" "(gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[2].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[2].Pa] & ((~ready_i)))) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=4,offset=2:vcs_gen_end:VC_COV_UNR" +Condition 149 "303405805" "(gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[2].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[2].Pa] & ((~ready_i)))) 1 -1" (3 "10") +ANNOTATION: "vcs_gen_start:level=4,offset=2:vcs_gen_end:VC_COV_UNR" +Condition 150 "3088640414" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[2].Pa] & ((~ready_i))) 1 -1" (3 "11") +ANNOTATION: "vcs_gen_start:level=4,offset=3:vcs_gen_end:VC_COV_UNR" +Condition 151 "2436119807" "(req_i[3] & gen_normal_case.prio_mask_q[3]) 1 -1" (1 "01") +ANNOTATION: "vcs_gen_start:level=4,offset=3:vcs_gen_end:VC_COV_UNR" +Condition 151 "2436119807" "(req_i[3] & gen_normal_case.prio_mask_q[3]) 1 -1" (2 "10") +ANNOTATION: "vcs_gen_start:level=4,offset=3:vcs_gen_end:VC_COV_UNR" +Condition 151 "2436119807" "(req_i[3] & gen_normal_case.prio_mask_q[3]) 1 -1" (3 "11") +ANNOTATION: "vcs_gen_start:level=4,offset=3:vcs_gen_end:VC_COV_UNR" +Condition 152 "358663893" "(req_i[3] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[3].Pa] & ready_i) 1 -1" (3 "110") +ANNOTATION: "vcs_gen_start:level=4,offset=3:vcs_gen_end:VC_COV_UNR" +Condition 154 "2614501764" "(gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[3].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[3].Pa] & ((~ready_i)))) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=4,offset=3:vcs_gen_end:VC_COV_UNR" +Condition 154 "2614501764" "(gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[3].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[3].Pa] & ((~ready_i)))) 1 -1" (3 "10") +ANNOTATION: "vcs_gen_start:level=4,offset=3:vcs_gen_end:VC_COV_UNR" +Condition 155 "2876935468" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[3].Pa] & ((~ready_i))) 1 -1" (3 "11") +ANNOTATION: "vcs_gen_start:level=4,offset=4:vcs_gen_end:VC_COV_UNR" +Condition 156 "1150101804" "(req_i[4] & gen_normal_case.prio_mask_q[4]) 1 -1" (1 "01") +ANNOTATION: "vcs_gen_start:level=4,offset=4:vcs_gen_end:VC_COV_UNR" +Condition 156 "1150101804" "(req_i[4] & gen_normal_case.prio_mask_q[4]) 1 -1" (2 "10") +ANNOTATION: "vcs_gen_start:level=4,offset=4:vcs_gen_end:VC_COV_UNR" +Condition 156 "1150101804" "(req_i[4] & gen_normal_case.prio_mask_q[4]) 1 -1" (3 "11") +ANNOTATION: "vcs_gen_start:level=4,offset=4:vcs_gen_end:VC_COV_UNR" +Condition 157 "2252512415" "(req_i[4] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[4].Pa] & ready_i) 1 -1" (3 "110") +ANNOTATION: "vcs_gen_start:level=4,offset=4:vcs_gen_end:VC_COV_UNR" +Condition 159 "2077403342" "(gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[4].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[4].Pa] & ((~ready_i)))) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=4,offset=4:vcs_gen_end:VC_COV_UNR" +Condition 159 "2077403342" "(gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[4].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[4].Pa] & ((~ready_i)))) 1 -1" (3 "10") +ANNOTATION: "vcs_gen_start:level=4,offset=4:vcs_gen_end:VC_COV_UNR" +Condition 160 "362208751" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[4].Pa] & ((~ready_i))) 1 -1" (3 "11") +ANNOTATION: "vcs_gen_start:level=4,offset=5:vcs_gen_end:VC_COV_UNR" +Condition 164 "4061205415" "(gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[5].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[5].Pa] & ((~ready_i)))) 1 -1" (3 "10") +ANNOTATION: "vcs_gen_start:level=4,offset=10:vcs_gen_end:VC_COV_UNR" +Condition 186 "1702269588" "(req_i[10] & gen_normal_case.prio_mask_q[10]) 1 -1" (2 "10") +ANNOTATION: "vcs_gen_start:level=4,offset=10:vcs_gen_end:VC_COV_UNR" +Condition 186 "1702269588" "(req_i[10] & gen_normal_case.prio_mask_q[10]) 1 -1" (3 "11") +ANNOTATION: "vcs_gen_start:level=4,offset=10:vcs_gen_end:VC_COV_UNR" +Condition 187 "565898016" "(req_i[10] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[10].Pa] & ready_i) 1 -1" (3 "110") +ANNOTATION: "vcs_gen_start:level=4,offset=10:vcs_gen_end:VC_COV_UNR" +Condition 189 "2771416427" "(gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[10].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[10].Pa] & ((~ready_i)))) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=4,offset=10:vcs_gen_end:VC_COV_UNR" +Condition 190 "2876058957" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[10].Pa] & ((~ready_i))) 1 -1" (3 "11") +ANNOTATION: "vcs_gen_start:level=4,offset=12:vcs_gen_end:VC_COV_UNR" +Condition 196 "3119114945" "(req_i[12] & gen_normal_case.prio_mask_q[12]) 1 -1" (2 "10") +ANNOTATION: "vcs_gen_start:level=4,offset=12:vcs_gen_end:VC_COV_UNR" +Condition 196 "3119114945" "(req_i[12] & gen_normal_case.prio_mask_q[12]) 1 -1" (3 "11") +ANNOTATION: "vcs_gen_start:level=4,offset=12:vcs_gen_end:VC_COV_UNR" +Condition 197 "4217824807" "(req_i[12] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[12].Pa] & ready_i) 1 -1" (3 "110") +ANNOTATION: "vcs_gen_start:level=4,offset=12:vcs_gen_end:VC_COV_UNR" +Condition 199 "2102103111" "(gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[12].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[12].Pa] & ((~ready_i)))) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=4,offset=12:vcs_gen_end:VC_COV_UNR" +Condition 200 "3779810229" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[12].Pa] & ((~ready_i))) 1 -1" (3 "11") +ANNOTATION: "vcs_gen_start:level=4,offset=13:vcs_gen_end:VC_COV_UNR" +Condition 204 "3359315662" "(gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[13].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[13].Pa] & ((~ready_i)))) 1 -1" (1 "00") +CHECKSUM: "2032872600 3109464092" +INSTANCE: tb.dut.u_otp_ctrl_kdi.u_req_arb +ANNOTATION: "vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 65 "2951635521" "(req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[0].Pa] & ready_i) 1 -1" (1 "011") +ANNOTATION: "vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR" +Condition 70 "4160391802" "(req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[1].Pa] & ready_i) 1 -1" (1 "011") +ANNOTATION: "vcs_gen_start:level=3,offset=2:vcs_gen_end:VC_COV_UNR" +Condition 75 "2241885365" "(req_i[2] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[2].Pa] & ready_i) 1 -1" (1 "011") +ANNOTATION: "vcs_gen_start:level=3,offset=3:vcs_gen_end:VC_COV_UNR" +Condition 80 "3719601294" "(req_i[3] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[3].Pa] & ready_i) 1 -1" (1 "011") +ANNOTATION: "vcs_gen_start:level=3,offset=4:vcs_gen_end:VC_COV_UNR" +Condition 85 "1318504132" "(req_i[4] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[4].Pa] & ready_i) 1 -1" (1 "011") +ANNOTATION: "vcs_gen_start:level=3,offset=5:vcs_gen_end:VC_COV_UNR" +Condition 90 "377630463" "(req_i[5] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[5].Pa] & ready_i) 1 -1" (1 "011") +ANNOTATION: "vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR" +Condition 95 "1691930672" "(req_i[6] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[6].Pa] & ready_i) 1 -1" (1 "011") +CHECKSUM: "4013022403 1458251632" +INSTANCE: tb.dut.u_prim_edn_req.u_prim_packer_fifo +ANNOTATION: "VC_COV_UNR" +Condition 12 "2853235687" "((depth_q == FullDepth) && ((!clr_q))) 1 -1" (2 "10") +CHECKSUM: "903559179 1533167362" +INSTANCE: tb.dut.u_otp_ctrl_dai +ANNOTATION: "VC_COV_UNR" +Condition 6 "3686409107" "(scrmbl_mtx_gnt_i && scrmbl_ready_i) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 8 "4163455672" "(scrmbl_mtx_gnt_i && scrmbl_ready_i) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 9 "1539831361" "(scrmbl_mtx_gnt_i && scrmbl_ready_i) 1 -1" (1 "01") +ANNOTATION: "vcs_gen_start:k=10:vcs_gen_end:VC_COV_UNR" +Condition 33 "138415549" "((dai_addr_i >= 11'b11110101000) & ({1'b0, dai_addr_i} < gen_part_sel[10].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0])) 1 -1" (2 "10") +CHECKSUM: "1158524476 2909360515" +INSTANCE: tb.dut.u_otp_ctrl_kdi +ANNOTATION: "VC_COV_UNR" +Condition 2 "1539831361" "(scrmbl_mtx_gnt_i && scrmbl_ready_i) 1 -1" (1 "01") +CHECKSUM: "3162909804 4223786199" +INSTANCE: tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf +ANNOTATION: "VC_COV_UNR" +Condition 14 "2502713177" "(({tlul_addr_q, 2'b0} >= 11'b10001111000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd)) 1 -1" (2 "10") +CHECKSUM: "3162909804 475089886" +INSTANCE: tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf +ANNOTATION: "VC_COV_UNR" +Condition 1 "1099175909" "(otp_err != NoError) 1 -1" (2 "1") +ANNOTATION: "VC_COV_UNR" +Condition 2 "2883220586" "(otp_err != NoError) 1 -1" (2 "1") +CHECKSUM: "3162909804 1722272287" +INSTANCE: tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf +ANNOTATION: "VC_COV_UNR" +Condition 14 "478960819" "(({tlul_addr_q, 2'b0} >= 11'b00001000000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd)) 1 -1" (2 "10") +CHECKSUM: "3162909804 1789909357" +INSTANCE: tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf +ANNOTATION: "VC_COV_UNR" +Condition 14 "1715010657" "(({tlul_addr_q, 2'b0} >= 11'b00111101000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd)) 1 -1" (2 "10") +CHECKSUM: "3162909804 4078376581" +INSTANCE: tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf +ANNOTATION: "VC_COV_UNR" +Condition 14 "677249997" "(({tlul_addr_q, 2'b0} >= 11'b11001010000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd)) 1 -1" (2 "10") +CHECKSUM: "3727300757 720525075" +INSTANCE: tb.dut.gen_partitions[5].gen_buffered.u_part_buf +ANNOTATION: "VC_COV_UNR" +Condition 3 "1999344180" "(scrmbl_mtx_gnt_i && scrmbl_ready_i) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 3 "1999344180" "(scrmbl_mtx_gnt_i && scrmbl_ready_i) 1 -1" (2 "10") +ANNOTATION: "VC_COV_UNR" +Condition 3 "1999344180" "(scrmbl_mtx_gnt_i && scrmbl_ready_i) 1 -1" (3 "11") +ANNOTATION: "VC_COV_UNR" +Condition 10 "4291765346" "(scrmbl_mtx_gnt_i && scrmbl_ready_i) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 16 "3809681040" "(state_q != ErrorSt) 1 -1" (1 "0") +ANNOTATION: "VC_COV_UNR" +Condition 16 "3809681040" "(state_q != ErrorSt) 1 -1" (2 "1") +CHECKSUM: "3727300757 384791011" +INSTANCE: tb.dut.gen_partitions[9].gen_buffered.u_part_buf +ANNOTATION: "VC_COV_UNR" +Condition 3 "1999344180" "(scrmbl_mtx_gnt_i && scrmbl_ready_i) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 9 "1580211052" "(scrmbl_mtx_gnt_i && scrmbl_ready_i) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 16 "3809681040" "(state_q != ErrorSt) 1 -1" (1 "0") +ANNOTATION: "VC_COV_UNR" +Condition 16 "3809681040" "(state_q != ErrorSt) 1 -1" (2 "1") +CHECKSUM: "3727300757 599055118" +INSTANCE: tb.dut.gen_partitions[6].gen_buffered.u_part_buf +ANNOTATION: "VC_COV_UNR" +Condition 3 "1999344180" "(scrmbl_mtx_gnt_i && scrmbl_ready_i) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 3 "1999344180" "(scrmbl_mtx_gnt_i && scrmbl_ready_i) 1 -1" (2 "10") +ANNOTATION: "VC_COV_UNR" +Condition 3 "1999344180" "(scrmbl_mtx_gnt_i && scrmbl_ready_i) 1 -1" (3 "11") +ANNOTATION: "VC_COV_UNR" +Condition 10 "4291765346" "(scrmbl_mtx_gnt_i && scrmbl_ready_i) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 16 "3809681040" "(state_q != ErrorSt) 1 -1" (1 "0") +ANNOTATION: "VC_COV_UNR" +Condition 16 "3809681040" "(state_q != ErrorSt) 1 -1" (2 "1") +CHECKSUM: "3727300757 698462587" +INSTANCE: tb.dut.gen_partitions[7].gen_buffered.u_part_buf +ANNOTATION: "VC_COV_UNR" +Condition 3 "1999344180" "(scrmbl_mtx_gnt_i && scrmbl_ready_i) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 9 "1580211052" "(scrmbl_mtx_gnt_i && scrmbl_ready_i) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 16 "3809681040" "(state_q != ErrorSt) 1 -1" (1 "0") +ANNOTATION: "VC_COV_UNR" +Condition 16 "3809681040" "(state_q != ErrorSt) 1 -1" (2 "1") +CHECKSUM: "3727300757 2302263073" +INSTANCE: tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf +ANNOTATION: "VC_COV_UNR" +Condition 16 "3809681040" "(state_q != ErrorSt) 1 -1" (1 "0") +ANNOTATION: "VC_COV_UNR" +Condition 16 "3809681040" "(state_q != ErrorSt) 1 -1" (2 "1") +ANNOTATION: "VC_COV_UNR" +Condition 18 "624370688" "((base_sel == DigOffset) ? DigestOffset : 11'b11110101000) 1 -1" (2 "1") +ANNOTATION: "VC_COV_UNR" +Condition 19 "4038180897" "(base_sel == DigOffset) 1 -1" (2 "1") +ANNOTATION: "VC_COV_UNR" +Condition 20 "705391888" "((data_sel == ScrmblData) ? scrmbl_data_i : otp_rdata_i) 1 -1" (2 "1") +ANNOTATION: "VC_COV_UNR" +Condition 21 "1499701630" "(data_sel == ScrmblData) 1 -1" (2 "1") +CHECKSUM: "3727300757 691864715" +INSTANCE: tb.dut.gen_partitions[8].gen_buffered.u_part_buf +ANNOTATION: "VC_COV_UNR" +Condition 3 "1999344180" "(scrmbl_mtx_gnt_i && scrmbl_ready_i) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 9 "1580211052" "(scrmbl_mtx_gnt_i && scrmbl_ready_i) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 16 "3809681040" "(state_q != ErrorSt) 1 -1" (1 "0") +ANNOTATION: "VC_COV_UNR" +Condition 16 "3809681040" "(state_q != ErrorSt) 1 -1" (2 "1") +CHECKSUM: "835220981 1653115005" +INSTANCE: tb.dut.u_tlul_adapter_sram.u_sramreqfifo +ANNOTATION: "VC_COV_UNR" +Condition 2 "4002946372" "((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))) 1 -1" (1 "0") +ANNOTATION: "VC_COV_UNR" +Condition 3 "1926118060" "(gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) 1 -1" (1 "0") +ANNOTATION: "VC_COV_UNR" +Condition 4 "786039886" "(wvalid_i & wready_o & ((~gen_normal_fifo.under_rst))) 1 -1" (2 "101") +ANNOTATION: "VC_COV_UNR" +Condition 4 "786039886" "(wvalid_i & wready_o & ((~gen_normal_fifo.under_rst))) 1 -1" (3 "110") +ANNOTATION: "VC_COV_UNR" +Condition 5 "1324655787" "(rvalid_o & rready_i & ((~gen_normal_fifo.under_rst))) 1 -1" (1 "011") +ANNOTATION: "VC_COV_UNR" +Condition 5 "1324655787" "(rvalid_o & rready_i & ((~gen_normal_fifo.under_rst))) 1 -1" (3 "110") +ANNOTATION: "VC_COV_UNR" +Condition 7 "1709501387" "(((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst))) 1 -1" (2 "10") +CHECKSUM: "835220981 1198270510" +INSTANCE: tb.dut.u_otp_rsp_fifo +ANNOTATION: "VC_COV_UNR" +Condition 1 "644960181" "(gen_normal_fifo.full ? (2'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value))))) 1 -1" (2 "1") +ANNOTATION: "VC_COV_UNR" +Condition 4 "786039886" "(wvalid_i & wready_o & ((~gen_normal_fifo.under_rst))) 1 -1" (2 "101") +ANNOTATION: "VC_COV_UNR" +Condition 4 "786039886" "(wvalid_i & wready_o & ((~gen_normal_fifo.under_rst))) 1 -1" (3 "110") +ANNOTATION: "VC_COV_UNR" +Condition 5 "1324655787" "(rvalid_o & rready_i & ((~gen_normal_fifo.under_rst))) 1 -1" (1 "011") +ANNOTATION: "VC_COV_UNR" +Condition 5 "1324655787" "(rvalid_o & rready_i & ((~gen_normal_fifo.under_rst))) 1 -1" (3 "110") +ANNOTATION: "VC_COV_UNR" +Condition 6 "342355206" "(((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst))) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 7 "1709501387" "(((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst))) 1 -1" (2 "10") +ANNOTATION: "VC_COV_UNR" +Condition 8 "2721421913" "(gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}})) 1 -1" (2 "1") +CHECKSUM: "835220981 814234766" +INSTANCE: tb.dut.u_tlul_adapter_sram.u_rspfifo +ANNOTATION: "VC_COV_UNR" +Condition 2 "4002946372" "((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))) 1 -1" (1 "0") +ANNOTATION: "VC_COV_UNR" +Condition 3 "1926118060" "(gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) 1 -1" (1 "0") +ANNOTATION: "VC_COV_UNR" +Condition 4 "786039886" "(wvalid_i & wready_o & ((~gen_normal_fifo.under_rst))) 1 -1" (2 "101") +ANNOTATION: "VC_COV_UNR" +Condition 4 "786039886" "(wvalid_i & wready_o & ((~gen_normal_fifo.under_rst))) 1 -1" (3 "110") +ANNOTATION: "VC_COV_UNR" +Condition 5 "1324655787" "(rvalid_o & rready_i & ((~gen_normal_fifo.under_rst))) 1 -1" (1 "011") +ANNOTATION: "VC_COV_UNR" +Condition 5 "1324655787" "(rvalid_o & rready_i & ((~gen_normal_fifo.under_rst))) 1 -1" (3 "110") +ANNOTATION: "VC_COV_UNR" +Condition 7 "1709501387" "(((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst))) 1 -1" (2 "10") +ANNOTATION: "VC_COV_UNR" +Condition 11 "4208363759" "(gen_normal_fifo.fifo_empty && wvalid_i) 1 -1" (1 "01") +CHECKSUM: "835220981 2769699113" +INSTANCE: tb.dut.u_tlul_adapter_sram.u_reqfifo +ANNOTATION: "VC_COV_UNR" +Condition 2 "4002946372" "((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))) 1 -1" (1 "0") +ANNOTATION: "VC_COV_UNR" +Condition 3 "1926118060" "(gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) 1 -1" (1 "0") +ANNOTATION: "VC_COV_UNR" +Condition 4 "786039886" "(wvalid_i & wready_o & ((~gen_normal_fifo.under_rst))) 1 -1" (2 "101") +ANNOTATION: "VC_COV_UNR" +Condition 4 "786039886" "(wvalid_i & wready_o & ((~gen_normal_fifo.under_rst))) 1 -1" (3 "110") +ANNOTATION: "VC_COV_UNR" +Condition 5 "1324655787" "(rvalid_o & rready_i & ((~gen_normal_fifo.under_rst))) 1 -1" (1 "011") +ANNOTATION: "VC_COV_UNR" +Condition 5 "1324655787" "(rvalid_o & rready_i & ((~gen_normal_fifo.under_rst))) 1 -1" (3 "110") +ANNOTATION: "VC_COV_UNR" +Condition 7 "1709501387" "(((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst))) 1 -1" (2 "10") +CHECKSUM: "4255502330 3554514034" +INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field3 +ANNOTATION: "VC_COV_UNR" +Branch 0 "3759852512" "wr_en" (0) "wr_en 1" +ANNOTATION: "VC_COV_UNR" +Branch 1 "1017474648" "(!rst_ni)" (1) "(!rst_ni) 0,1" +CHECKSUM: "4255502330 3554514034" +INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field4 +ANNOTATION: "VC_COV_UNR" +Branch 0 "3759852512" "wr_en" (0) "wr_en 1" +ANNOTATION: "VC_COV_UNR" +Branch 1 "1017474648" "(!rst_ni)" (1) "(!rst_ni) 0,1" +CHECKSUM: "4255502330 3554514034" +INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field5 +ANNOTATION: "VC_COV_UNR" +Branch 0 "3759852512" "wr_en" (0) "wr_en 1" +ANNOTATION: "VC_COV_UNR" +Branch 1 "1017474648" "(!rst_ni)" (1) "(!rst_ni) 0,1" +CHECKSUM: "4255502330 3554514034" +INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field6 +ANNOTATION: "VC_COV_UNR" +Branch 0 "3759852512" "wr_en" (0) "wr_en 1" +ANNOTATION: "VC_COV_UNR" +Branch 1 "1017474648" "(!rst_ni)" (1) "(!rst_ni) 0,1" +CHECKSUM: "4255502330 3554514034" +INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field7 +ANNOTATION: "VC_COV_UNR" +Branch 0 "3759852512" "wr_en" (0) "wr_en 1" +ANNOTATION: "VC_COV_UNR" +Branch 1 "1017474648" "(!rst_ni)" (1) "(!rst_ni) 0,1" +CHECKSUM: "4255502330 3554514034" +INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field8 +ANNOTATION: "VC_COV_UNR" +Branch 0 "3759852512" "wr_en" (0) "wr_en 1" +ANNOTATION: "VC_COV_UNR" +Branch 1 "1017474648" "(!rst_ni)" (1) "(!rst_ni) 0,1" +CHECKSUM: "4255502330 3554514034" +INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field2 +ANNOTATION: "VC_COV_UNR" +Branch 0 "3759852512" "wr_en" (0) "wr_en 1" +ANNOTATION: "VC_COV_UNR" +Branch 1 "1017474648" "(!rst_ni)" (1) "(!rst_ni) 0,1" +CHECKSUM: "4255502330 3554514034" +INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field3 +ANNOTATION: "VC_COV_UNR" +Branch 0 "3759852512" "wr_en" (0) "wr_en 1" +ANNOTATION: "VC_COV_UNR" +Branch 1 "1017474648" "(!rst_ni)" (1) "(!rst_ni) 0,1" +CHECKSUM: "4255502330 3554514034" +INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field4 +ANNOTATION: "VC_COV_UNR" +Branch 0 "3759852512" "wr_en" (0) "wr_en 1" +ANNOTATION: "VC_COV_UNR" +Branch 1 "1017474648" "(!rst_ni)" (1) "(!rst_ni) 0,1" +CHECKSUM: "4255502330 3554514034" +INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field5 +ANNOTATION: "VC_COV_UNR" +Branch 0 "3759852512" "wr_en" (0) "wr_en 1" +ANNOTATION: "VC_COV_UNR" +Branch 1 "1017474648" "(!rst_ni)" (1) "(!rst_ni) 0,1" +CHECKSUM: "4255502330 3554514034" +INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field0 +ANNOTATION: "VC_COV_UNR" +Branch 0 "3759852512" "wr_en" (0) "wr_en 1" +ANNOTATION: "VC_COV_UNR" +Branch 1 "1017474648" "(!rst_ni)" (1) "(!rst_ni) 0,1" +CHECKSUM: "4255502330 3554514034" +INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field1 +ANNOTATION: "VC_COV_UNR" +Branch 0 "3759852512" "wr_en" (0) "wr_en 1" +ANNOTATION: "VC_COV_UNR" +Branch 1 "1017474648" "(!rst_ni)" (1) "(!rst_ni) 0,1" +CHECKSUM: "4255502330 3554514034" +INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field2 +ANNOTATION: "VC_COV_UNR" +Branch 0 "3759852512" "wr_en" (0) "wr_en 1" +ANNOTATION: "VC_COV_UNR" +Branch 1 "1017474648" "(!rst_ni)" (1) "(!rst_ni) 0,1" +CHECKSUM: "4255502330 3554514034" +INSTANCE: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field3 +ANNOTATION: "VC_COV_UNR" +Branch 0 "3759852512" "wr_en" (0) "wr_en 1" +ANNOTATION: "VC_COV_UNR" +Branch 1 "1017474648" "(!rst_ni)" (1) "(!rst_ni) 0,1" +CHECKSUM: "1335069400 3286487832" +INSTANCE: tb.dut.u_tlul_adapter_sram +ANNOTATION: "VC_COV_UNR" +Branch 2 "1058271942" "(vld_rd_rsp && reqfifo_rdata.error)" (0) "(vld_rd_rsp && reqfifo_rdata.error) 1,-" +ANNOTATION: "VC_COV_UNR" +Branch 6 "744749108" "reqfifo_rvalid" (2) "reqfifo_rvalid 1,0,0" +CHECKSUM: "2032872600 3832429488" +INSTANCE: tb.dut.u_scrmbl_mtx +ANNOTATION: "vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR" +Branch 2 "1747167515" "gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel" (1) "gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel 0" +ANNOTATION: "vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR" +Branch 3 "1747167515" "gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel" (1) "gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel 0" +ANNOTATION: "vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR" +Branch 6 "3123337246" "gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel" (1) "gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel 0" +ANNOTATION: "vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR" +Branch 7 "3123337246" "gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel" (1) "gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel 0" +ANNOTATION: "vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR" +Branch 14 "840384514" "gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel" (1) "gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel 0" +ANNOTATION: "vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR" +Branch 15 "840384514" "gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel" (1) "gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel 0" +ANNOTATION: "vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR" +Branch 16 "2813219087" "gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel" (1) "gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel 0" +ANNOTATION: "vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR" +Branch 17 "2813219087" "gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel" (1) "gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel 0" +ANNOTATION: "vcs_gen_start:level=3,offset=2:vcs_gen_end:VC_COV_UNR" +Branch 18 "2452890474" "gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel" (1) "gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel 0" +ANNOTATION: "vcs_gen_start:level=3,offset=2:vcs_gen_end:VC_COV_UNR" +Branch 19 "2452890474" "gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel" (1) "gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel 0" +ANNOTATION: "vcs_gen_start:level=3,offset=5:vcs_gen_end:VC_COV_UNR" +Branch 24 "3811150440" "gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel" (1) "gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel 0" +ANNOTATION: "vcs_gen_start:level=3,offset=5:vcs_gen_end:VC_COV_UNR" +Branch 25 "3811150440" "gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel" (1) "gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel 0" +ANNOTATION: "vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR" +Branch 26 "3602118669" "gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel" (1) "gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel 0" +ANNOTATION: "vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR" +Branch 27 "3602118669" "gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel" (1) "gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel 0" +CHECKSUM: "4224194069 3219254590" +INSTANCE: tb.dut.u_tlul_lc_gate +ANNOTATION: "VC_COV_UNR" +Branch 2 "1850090820" "state_q" (8) "state_q StFlush ,-,-,-,0,0,-,-" +CHECKSUM: "3882079776 3692779052" +INSTANCE: tb.dut.u_otp_ctrl_scrmbl +ANNOTATION: "VC_COV_UNR" +Branch 5 "2137472258" "state_q" (8) "state_q IdleSt ,1,default,-,-,-,-,-" +CHECKSUM: "903559179 3978479804" +INSTANCE: tb.dut.u_otp_ctrl_dai +ANNOTATION: "VC_COV_UNR" +Branch 2 "2060689171" "state_q" (1) "state_q ResetSt ,1,0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 2 "2060689171" "state_q" (3) "state_q InitOtpSt ,-,-,1,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 2 "2060689171" "state_q" (35) "state_q WriteWaitSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,1,1,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-" +CHECKSUM: "1158524476 2213598664" +INSTANCE: tb.dut.u_otp_ctrl_kdi +ANNOTATION: "VC_COV_UNR" +Branch 4 "853326673" "state_q" (20) "state_q DigWaitSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,1,1,1,-,-,-" +CHECKSUM: "3162909804 3977884699" +INSTANCE: tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf +ANNOTATION: "VC_COV_UNR" +Branch 5 "490981166" "state_q" (4) "state_q InitSt ,-,-,0,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 5 "490981166" "state_q" (5) "state_q InitWaitSt ,-,-,-,1,1,1,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 5 "490981166" "state_q" (7) "state_q InitWaitSt ,-,-,-,1,0,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 5 "490981166" "state_q" (14) "state_q ReadWaitSt ,-,-,-,-,-,-,-,-,-,1,1,1,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 5 "490981166" "state_q" (16) "state_q ReadWaitSt ,-,-,-,-,-,-,-,-,-,1,0,-,-,-,-" +CHECKSUM: "3727300757 3964686460" +INSTANCE: tb.dut.gen_partitions[7].gen_buffered.u_part_buf +ANNOTATION: "VC_COV_UNR" +Branch 5 "3673468110" "state_q" (20) "state_q CnstyReadSt ,-,-,-,-,-,-,-,-,-,-,-,-,0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 5 "3673468110" "state_q" (35) "state_q IntegDigClrSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,1,0,-,0,-,-,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 5 "3673468110" "state_q" (37) "state_q IntegDigClrSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,0,-,-,-,0,-,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 5 "3673468110" "state_q" (47) "state_q IntegDigSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,1,0,-,-,0,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 5 "3673468110" "state_q" (49) "state_q IntegDigPadSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,1,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 5 "3673468110" "state_q" (50) "state_q IntegDigPadSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,0,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 6 "375157548" "ecc_err" (0) "ecc_err 1,1" +ANNOTATION: "VC_COV_UNR" +Branch 6 "375157548" "ecc_err" (1) "ecc_err 1,0" +CHECKSUM: "3727300757 3964686460" +INSTANCE: tb.dut.gen_partitions[8].gen_buffered.u_part_buf +ANNOTATION: "VC_COV_UNR" +Branch 5 "3673468110" "state_q" (20) "state_q CnstyReadSt ,-,-,-,-,-,-,-,-,-,-,-,-,0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 5 "3673468110" "state_q" (35) "state_q IntegDigClrSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,1,0,-,0,-,-,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 5 "3673468110" "state_q" (37) "state_q IntegDigClrSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,0,-,-,-,0,-,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 5 "3673468110" "state_q" (47) "state_q IntegDigSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,1,0,-,-,0,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 5 "3673468110" "state_q" (49) "state_q IntegDigPadSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,1,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 5 "3673468110" "state_q" (50) "state_q IntegDigPadSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,0,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 6 "375157548" "ecc_err" (0) "ecc_err 1,1" +ANNOTATION: "VC_COV_UNR" +Branch 6 "375157548" "ecc_err" (1) "ecc_err 1,0" +CHECKSUM: "3727300757 3964686460" +INSTANCE: tb.dut.gen_partitions[9].gen_buffered.u_part_buf +ANNOTATION: "VC_COV_UNR" +Branch 5 "3673468110" "state_q" (20) "state_q CnstyReadSt ,-,-,-,-,-,-,-,-,-,-,-,-,0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 5 "3673468110" "state_q" (35) "state_q IntegDigClrSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,1,0,-,0,-,-,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 5 "3673468110" "state_q" (37) "state_q IntegDigClrSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,0,-,-,-,0,-,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 5 "3673468110" "state_q" (47) "state_q IntegDigSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,1,0,-,-,0,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 5 "3673468110" "state_q" (49) "state_q IntegDigPadSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,1,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 5 "3673468110" "state_q" (50) "state_q IntegDigPadSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,0,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 6 "375157548" "ecc_err" (0) "ecc_err 1,1" +ANNOTATION: "VC_COV_UNR" +Branch 6 "375157548" "ecc_err" (1) "ecc_err 1,0" +CHECKSUM: "3727300757 2334161493" +INSTANCE: tb.dut.gen_partitions[5].gen_buffered.u_part_buf +ANNOTATION: "VC_COV_UNR" +Branch 4 "344890278" "state_q" (11) "state_q InitDescrSt ,-,-,-,-,-,-,-,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 4 "344890278" "state_q" (12) "state_q InitDescrSt ,-,-,-,-,-,-,-,0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 4 "344890278" "state_q" (13) "state_q InitDescrWaitSt ,-,-,-,-,-,-,-,-,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 4 "344890278" "state_q" (14) "state_q InitDescrWaitSt ,-,-,-,-,-,-,-,-,0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 4 "344890278" "state_q" (20) "state_q CnstyReadSt ,-,-,-,-,-,-,-,-,-,-,-,-,0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 4 "344890278" "state_q" (33) "state_q IntegDigClrSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,1,1,0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 4 "344890278" "state_q" (37) "state_q IntegDigClrSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,0,-,-,-,0,-,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 4 "344890278" "state_q" (38) "state_q IntegScrSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,1,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 4 "344890278" "state_q" (39) "state_q IntegScrSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,0,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 4 "344890278" "state_q" (40) "state_q IntegScrWaitSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,1,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 4 "344890278" "state_q" (41) "state_q IntegScrWaitSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,0,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 4 "344890278" "state_q" (49) "state_q IntegDigPadSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,1,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 4 "344890278" "state_q" (50) "state_q IntegDigPadSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,0,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 5 "375157548" "ecc_err" (0) "ecc_err 1,1" +ANNOTATION: "VC_COV_UNR" +Branch 5 "375157548" "ecc_err" (1) "ecc_err 1,0" +CHECKSUM: "3727300757 2334161493" +INSTANCE: tb.dut.gen_partitions[6].gen_buffered.u_part_buf +ANNOTATION: "VC_COV_UNR" +Branch 4 "344890278" "state_q" (11) "state_q InitDescrSt ,-,-,-,-,-,-,-,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 4 "344890278" "state_q" (12) "state_q InitDescrSt ,-,-,-,-,-,-,-,0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 4 "344890278" "state_q" (13) "state_q InitDescrWaitSt ,-,-,-,-,-,-,-,-,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 4 "344890278" "state_q" (14) "state_q InitDescrWaitSt ,-,-,-,-,-,-,-,-,0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 4 "344890278" "state_q" (20) "state_q CnstyReadSt ,-,-,-,-,-,-,-,-,-,-,-,-,0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 4 "344890278" "state_q" (33) "state_q IntegDigClrSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,1,1,0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 4 "344890278" "state_q" (37) "state_q IntegDigClrSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,0,-,-,-,0,-,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 4 "344890278" "state_q" (38) "state_q IntegScrSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,1,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 4 "344890278" "state_q" (39) "state_q IntegScrSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,0,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 4 "344890278" "state_q" (40) "state_q IntegScrWaitSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,1,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 4 "344890278" "state_q" (41) "state_q IntegScrWaitSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,0,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 4 "344890278" "state_q" (42) "state_q IntegDigSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,1,1,1,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 4 "344890278" "state_q" (45) "state_q IntegDigSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,1,0,-,0,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 5 "375157548" "ecc_err" (0) "ecc_err 1,1" +ANNOTATION: "VC_COV_UNR" +Branch 5 "375157548" "ecc_err" (1) "ecc_err 1,0" +CHECKSUM: "3727300757 2810977924" +INSTANCE: tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf +ANNOTATION: "VC_COV_UNR" +Branch 0 "2541341865" "(base_sel == DigOffset)" (0) "(base_sel == DigOffset) 1" +ANNOTATION: "VC_COV_UNR" +Branch 1 "341865418" "(data_sel == ScrmblData)" (0) "(data_sel == ScrmblData) 1" +ANNOTATION: "VC_COV_UNR" +Branch 3 "1949926999" "state_q" (12) "state_q InitDescrSt ,-,-,-,-,-,-,-,0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 3 "1949926999" "state_q" (14) "state_q InitDescrWaitSt ,-,-,-,-,-,-,-,-,0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 3 "1949926999" "state_q" (33) "state_q IntegDigClrSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,1,1,0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 3 "1949926999" "state_q" (35) "state_q IntegDigClrSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,1,0,-,0,-,-,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 3 "1949926999" "state_q" (37) "state_q IntegDigClrSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,0,-,-,-,0,-,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 3 "1949926999" "state_q" (39) "state_q IntegScrSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,0,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 3 "1949926999" "state_q" (41) "state_q IntegScrWaitSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,0,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 3 "1949926999" "state_q" (45) "state_q IntegDigSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,1,0,-,0,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 3 "1949926999" "state_q" (47) "state_q IntegDigSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,1,0,-,-,0,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 3 "1949926999" "state_q" (48) "state_q IntegDigSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,0,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 3 "1949926999" "state_q" (50) "state_q IntegDigPadSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,0,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 3 "1949926999" "state_q" (52) "state_q IntegDigFinSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,0,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 3 "1949926999" "state_q" (56) "state_q IntegDigWaitSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,0,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 4 "375157548" "ecc_err" (0) "ecc_err 1,1" +ANNOTATION: "VC_COV_UNR" +Branch 4 "375157548" "ecc_err" (1) "ecc_err 1,0" +CHECKSUM: "835220981 2115631974" +INSTANCE: tb.dut.u_tlul_adapter_sram.u_reqfifo +ANNOTATION: "VC_COV_UNR" +Branch 0 "1862733684" "gen_normal_fifo.full" (2) "gen_normal_fifo.full 0,0" +CHECKSUM: "835220981 2115631974" +INSTANCE: tb.dut.u_tlul_adapter_sram.u_sramreqfifo +ANNOTATION: "VC_COV_UNR" +Branch 0 "1862733684" "gen_normal_fifo.full" (2) "gen_normal_fifo.full 0,0" +CHECKSUM: "835220981 3240364287" +INSTANCE: tb.dut.u_tlul_adapter_sram.u_rspfifo +ANNOTATION: "VC_COV_UNR" +Branch 0 "1862733684" "gen_normal_fifo.full" (2) "gen_normal_fifo.full 0,0" +CHECKSUM: "835220981 3240364287" +INSTANCE: tb.dut.u_otp_rsp_fifo +ANNOTATION: "VC_COV_UNR" +Branch 0 "1862733684" "gen_normal_fifo.full" (0) "gen_normal_fifo.full 1,-" +CHECKSUM: "3818998033 3877782530" +INSTANCE: tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg +ANNOTATION: "VC_COV_UNR" +Branch 1 "2154824802" "(32'(addr_i) < Depth)" (2) "(32'(addr_i) < Depth) 0,-" +CHECKSUM: "1817939962 689627449" +INSTANCE: tb.dut.u_tlul_adapter_sram.u_reqfifo.gen_normal_fifo.u_fifo_cnt +ANNOTATION: "VC_COV_UNR" +Branch 0 "353148737" "(!rst_ni)" (3) "(!rst_ni) 0,0,0,1" +ANNOTATION: "VC_COV_UNR" +Branch 1 "3145009581" "(!rst_ni)" (3) "(!rst_ni) 0,0,0,1" +CHECKSUM: "1817939962 689627449" +INSTANCE: tb.dut.u_tlul_adapter_sram.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt +ANNOTATION: "VC_COV_UNR" +Branch 0 "353148737" "(!rst_ni)" (3) "(!rst_ni) 0,0,0,1" +ANNOTATION: "VC_COV_UNR" +Branch 1 "3145009581" "(!rst_ni)" (3) "(!rst_ni) 0,0,0,1" +CHECKSUM: "1817939962 689627449" +INSTANCE: tb.dut.u_tlul_adapter_sram.u_rspfifo.gen_normal_fifo.u_fifo_cnt +ANNOTATION: "VC_COV_UNR" +Branch 0 "353148737" "(!rst_ni)" (3) "(!rst_ni) 0,0,0,1" +ANNOTATION: "VC_COV_UNR" +Branch 1 "3145009581" "(!rst_ni)" (3) "(!rst_ni) 0,0,0,1" diff --git a/src/fuse_ctrl/dv/cov/otp_ctrl_cover.cfg b/src/fuse_ctrl/dv/cov/otp_ctrl_cover.cfg new file mode 100755 index 0000000..d69a193 --- /dev/null +++ b/src/fuse_ctrl/dv/cov/otp_ctrl_cover.cfg @@ -0,0 +1,14 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + + +// The modules below are preverified in FPV testbench. +// There are many conditional coverage and hard to them all. +-moduletree prim_secded_inv_72_64_dec +-moduletree prim_secded_inv_72_64_enc + +begin tgl + +module prim_secded_inv_72_64_dec + +module prim_secded_inv_72_64_enc +end diff --git a/src/fuse_ctrl/dv/env/otp_ctrl_ast_inputs_cfg.sv b/src/fuse_ctrl/dv/env/otp_ctrl_ast_inputs_cfg.sv new file mode 100644 index 0000000..4b723d7 --- /dev/null +++ b/src/fuse_ctrl/dv/env/otp_ctrl_ast_inputs_cfg.sv @@ -0,0 +1,35 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// +// Configuration values for DUT input signals +// +// +// This class randomizes values for DUT signal inputs +// and sets constraints on these values. +// +// This class will be instantiated inside otp_ctrl_env_cfg object, and will connect +// to it's otp_ctrl_vif signals and drive them each reset event +// +// The constraints can be hardened and softened as needed in +// closed-source environment. +// In order to override these constraints, please inherit this class +// and set a type override in the closed source environment + +class otp_ctrl_ast_inputs_cfg extends uvm_object; + `uvm_object_utils(otp_ctrl_ast_inputs_cfg); + `uvm_object_new + + // Group: Variables + rand otp_ast_rsp_t otp_ast_pwr_seq_h; + rand logic [otp_ctrl_pkg::OtpTestCtrlWidth-1:0] otp_vendor_test_ctrl; + rand prim_mubi_pkg::mubi4_t scanmode; + rand logic scan_en, scan_rst_n; + + // Group: Constraints + constraint dut_values_c { + otp_vendor_test_ctrl == 32'h0; + } + +endclass: otp_ctrl_ast_inputs_cfg diff --git a/src/fuse_ctrl/dv/env/otp_ctrl_env.core b/src/fuse_ctrl/dv/env/otp_ctrl_env.core new file mode 100644 index 0000000..4b35e4c --- /dev/null +++ b/src/fuse_ctrl/dv/env/otp_ctrl_env.core @@ -0,0 +1,59 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:dv:otp_ctrl_env:0.1" +description: "OTP_CTRL DV UVM environment" +filesets: + files_dv: + depend: + - lowrisc:dv:ralgen + - lowrisc:dv:cip_lib + - lowrisc:dv:mem_bkdr_util + - lowrisc:dv:crypto_dpi_present + - lowrisc:dv:lc_ctrl_dv_utils + files: + - otp_ctrl_env_pkg.sv + - otp_ctrl_if.sv + - otp_ctrl_ast_inputs_cfg.sv: {is_include_file: true} + - otp_ctrl_env_cfg.sv: {is_include_file: true} + - otp_ctrl_env_cov.sv: {is_include_file: true} + - otp_ctrl_virtual_sequencer.sv: {is_include_file: true} + - otp_ctrl_scoreboard.sv: {is_include_file: true} + - otp_ctrl_env.sv: {is_include_file: true} + - seq_lib/otp_ctrl_vseq_list.sv: {is_include_file: true} + - seq_lib/otp_ctrl_callback_vseq.sv: {is_include_file: true} + - seq_lib/otp_ctrl_base_vseq.sv: {is_include_file: true} + - seq_lib/otp_ctrl_common_vseq.sv: {is_include_file: true} + - seq_lib/otp_ctrl_wake_up_vseq.sv: {is_include_file: true} + - seq_lib/otp_ctrl_smoke_vseq.sv: {is_include_file: true} + - seq_lib/otp_ctrl_partition_walk_vseq.sv: {is_include_file: true} + - seq_lib/otp_ctrl_low_freq_read_vseq.sv: {is_include_file: true} + - seq_lib/otp_ctrl_init_fail_vseq.sv: {is_include_file: true} + - seq_lib/otp_ctrl_dai_lock_vseq.sv: {is_include_file: true} + - seq_lib/otp_ctrl_dai_errs_vseq.sv: {is_include_file: true} + - seq_lib/otp_ctrl_macro_errs_vseq.sv: {is_include_file: true} + - seq_lib/otp_ctrl_background_chks_vseq.sv: {is_include_file: true} + - seq_lib/otp_ctrl_check_fail_vseq.sv: {is_include_file: true} + - seq_lib/otp_ctrl_parallel_base_vseq.sv: {is_include_file: true} + - seq_lib/otp_ctrl_regwen_vseq.sv: {is_include_file: true} + - seq_lib/otp_ctrl_parallel_key_req_vseq.sv: {is_include_file: true} + - seq_lib/otp_ctrl_parallel_lc_req_vseq.sv: {is_include_file: true} + - seq_lib/otp_ctrl_parallel_lc_esc_vseq.sv: {is_include_file: true} + - seq_lib/otp_ctrl_test_access_vseq.sv: {is_include_file: true} + - seq_lib/otp_ctrl_stress_all_vseq.sv: {is_include_file: true} + file_type: systemVerilogSource + +generate: + ral: + generator: ralgen + parameters: + name: otp_ctrl + ip_hjson: ../../data/otp_ctrl.hjson + +targets: + default: + filesets: + - files_dv + generate: + - ral diff --git a/src/fuse_ctrl/dv/env/otp_ctrl_env.sv b/src/fuse_ctrl/dv/env/otp_ctrl_env.sv new file mode 100644 index 0000000..454d14d --- /dev/null +++ b/src/fuse_ctrl/dv/env/otp_ctrl_env.sv @@ -0,0 +1,106 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class otp_ctrl_env #( + type CFG_T = otp_ctrl_env_cfg, + type COV_T = otp_ctrl_env_cov, + type VIRTUAL_SEQUENCER_T = otp_ctrl_virtual_sequencer, + type SCOREBOARD_T = otp_ctrl_scoreboard + ) + extends cip_base_env #( + .CFG_T (CFG_T), + .COV_T (COV_T), + .VIRTUAL_SEQUENCER_T(VIRTUAL_SEQUENCER_T), + .SCOREBOARD_T (SCOREBOARD_T) + ); + `uvm_component_param_utils(otp_ctrl_env #(CFG_T, COV_T, VIRTUAL_SEQUENCER_T, SCOREBOARD_T)) + + `uvm_component_new + + push_pull_agent#(.DeviceDataWidth(SRAM_DATA_SIZE)) m_sram_pull_agent[NumSramKeyReqSlots]; + push_pull_agent#(.DeviceDataWidth(OTBN_DATA_SIZE)) m_otbn_pull_agent; + push_pull_agent#(.DeviceDataWidth(FLASH_DATA_SIZE)) m_flash_addr_pull_agent; + push_pull_agent#(.DeviceDataWidth(FLASH_DATA_SIZE)) m_flash_data_pull_agent; + push_pull_agent#(.DeviceDataWidth(1), .HostDataWidth(LC_PROG_DATA_SIZE)) m_lc_prog_pull_agent; + + function void build_phase(uvm_phase phase); + super.build_phase(phase); + + // build sram-otp pull agent + for (int i = 0; i < NumSramKeyReqSlots; i++) begin + string sram_agent_name = $sformatf("m_sram_pull_agent[%0d]", i); + m_sram_pull_agent[i] = push_pull_agent#(.DeviceDataWidth(SRAM_DATA_SIZE))::type_id::create( + sram_agent_name, this); + uvm_config_db#(push_pull_agent_cfg#(.DeviceDataWidth(SRAM_DATA_SIZE)))::set(this, + $sformatf("%0s*", sram_agent_name), "cfg", cfg.m_sram_pull_agent_cfg[i]); + end + + // build otbn-otp pull agent + m_otbn_pull_agent = push_pull_agent#(.DeviceDataWidth(OTBN_DATA_SIZE))::type_id::create( + "m_otbn_pull_agent", this); + uvm_config_db#(push_pull_agent_cfg#(.DeviceDataWidth(OTBN_DATA_SIZE)))::set( + this, "m_otbn_pull_agent", "cfg", cfg.m_otbn_pull_agent_cfg); + + // build flash-otp pull agent + m_flash_addr_pull_agent = push_pull_agent#(.DeviceDataWidth(FLASH_DATA_SIZE))::type_id::create( + "m_flash_addr_pull_agent", this); + uvm_config_db#(push_pull_agent_cfg#(.DeviceDataWidth(FLASH_DATA_SIZE)))::set( + this, "m_flash_addr_pull_agent", "cfg", cfg.m_flash_addr_pull_agent_cfg); + m_flash_data_pull_agent = push_pull_agent#(.DeviceDataWidth(FLASH_DATA_SIZE))::type_id::create( + "m_flash_data_pull_agent", this); + uvm_config_db#(push_pull_agent_cfg#(.DeviceDataWidth(FLASH_DATA_SIZE)))::set( + this, "m_flash_data_pull_agent", "cfg", cfg.m_flash_data_pull_agent_cfg); + + // build lc-otp program pull agent + m_lc_prog_pull_agent = push_pull_agent#(.HostDataWidth(LC_PROG_DATA_SIZE), .DeviceDataWidth(1)) + ::type_id::create("m_lc_prog_pull_agent", this); + uvm_config_db#(push_pull_agent_cfg#(.HostDataWidth(LC_PROG_DATA_SIZE), .DeviceDataWidth(1))):: + set(this, "m_lc_prog_pull_agent", "cfg", cfg.m_lc_prog_pull_agent_cfg); + + // config mem virtual interface + if (!uvm_config_db#(mem_bkdr_util)::get(this, "", "mem_bkdr_util", cfg.mem_bkdr_util_h)) begin + `uvm_fatal(`gfn, "failed to get mem_bkdr_util from uvm_config_db") + end + + // config otp_ctrl output data virtual interface + if (!uvm_config_db#(otp_ctrl_vif)::get(this, "", "otp_ctrl_vif", cfg.otp_ctrl_vif)) begin + `uvm_fatal(`gfn, "failed to get otp_ctrl_vif from uvm_config_db") + end + + // Check if `NumPart` constant is assigned to the correct value. + `DV_CHECK(NumPart == (LifeCycleIdx + 1)) + + endfunction + + function void connect_phase(uvm_phase phase); + super.connect_phase(phase); + + // connect SRAM sequencer and analysis ports + for (int i = 0; i < NumSramKeyReqSlots; i++) begin + virtual_sequencer.sram_pull_sequencer_h[i] = m_sram_pull_agent[i].sequencer; + if (cfg.en_scb) begin + m_sram_pull_agent[i].monitor.analysis_port.connect( + scoreboard.sram_fifos[i].analysis_export); + end + end + + virtual_sequencer.otbn_pull_sequencer_h = m_otbn_pull_agent.sequencer; + virtual_sequencer.flash_addr_pull_sequencer_h = m_flash_addr_pull_agent.sequencer; + virtual_sequencer.flash_data_pull_sequencer_h = m_flash_data_pull_agent.sequencer; + virtual_sequencer.lc_prog_pull_sequencer_h = m_lc_prog_pull_agent.sequencer; + + if (cfg.en_scb) begin + m_otbn_pull_agent.monitor.analysis_port.connect(scoreboard.otbn_fifo.analysis_export); + m_flash_addr_pull_agent.monitor.analysis_port.connect( + scoreboard.flash_addr_fifo.analysis_export); + m_flash_data_pull_agent.monitor.analysis_port.connect( + scoreboard.flash_data_fifo.analysis_export); + m_lc_prog_pull_agent.monitor.analysis_port.connect(scoreboard.lc_prog_fifo.analysis_export); + end + + // connect the DUT cfg instance to the handle in the otp_ctrl_vif + this.cfg.otp_ctrl_vif.dut_cfg = this.cfg.dut_cfg; + endfunction + +endclass diff --git a/src/fuse_ctrl/dv/env/otp_ctrl_env_cfg.sv b/src/fuse_ctrl/dv/env/otp_ctrl_env_cfg.sv new file mode 100644 index 0000000..52c67e8 --- /dev/null +++ b/src/fuse_ctrl/dv/env/otp_ctrl_env_cfg.sv @@ -0,0 +1,106 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +`define OTP_CLK_CONSTRAINT(FREQ_) \ + FREQ_ dist { \ + 6 :/ 2, \ + [24:25] :/ 2, \ + [26:47] :/ 1, \ + [48:50] :/ 2, \ + [51:95] :/ 1, \ + 96 :/ 1, \ + [97:99] :/ 1, \ + 100 :/ 1 \ + }; + +class otp_ctrl_env_cfg extends cip_base_env_cfg #(.RAL_T(otp_ctrl_core_reg_block)); + + // ext component cfgs + rand push_pull_agent_cfg#(.DeviceDataWidth(SRAM_DATA_SIZE)) + m_sram_pull_agent_cfg[NumSramKeyReqSlots]; + rand push_pull_agent_cfg#(.DeviceDataWidth(OTBN_DATA_SIZE)) m_otbn_pull_agent_cfg; + rand push_pull_agent_cfg#(.DeviceDataWidth(FLASH_DATA_SIZE)) m_flash_data_pull_agent_cfg; + rand push_pull_agent_cfg#(.DeviceDataWidth(FLASH_DATA_SIZE)) m_flash_addr_pull_agent_cfg; + rand push_pull_agent_cfg#(.DeviceDataWidth(1), .HostDataWidth(LC_PROG_DATA_SIZE)) + m_lc_prog_pull_agent_cfg; + + // Memory backdoor util instance for OTP. + mem_bkdr_util mem_bkdr_util_h; + + // ext interfaces + otp_ctrl_vif otp_ctrl_vif; + virtual clk_rst_if clk_rst_vif_otp_ctrl_prim_reg_block; + + bit backdoor_clear_mem; + + // Check ECC errors + otp_ecc_err_e ecc_chk_err [NumPart] = '{default:OtpNoEccErr}; + + // values for otp_ctrl_if signals connected to DUT + rand otp_ctrl_ast_inputs_cfg dut_cfg; + + // Introduce this flag to avoid close source conflict. + bit create_prim_tl_agent = 1; + + `uvm_object_utils_begin(otp_ctrl_env_cfg) + `uvm_object_utils_end + + `uvm_object_new + + constraint clk_freq_mhz_c { + `OTP_CLK_CONSTRAINT(clk_freq_mhz) + foreach (clk_freqs_mhz[i]) { + `OTP_CLK_CONSTRAINT(clk_freqs_mhz[i]) + } + } + + virtual function void initialize(bit [31:0] csr_base_addr = '1); + string prim_ral_name = "otp_ctrl_prim_reg_block"; + ral_model_names.push_back(prim_ral_name); + clk_freqs_mhz[prim_ral_name] = clk_freq_mhz; + + list_of_alerts = otp_ctrl_env_pkg::LIST_OF_ALERTS; + num_edn = 1; + tl_intg_alert_name = "fatal_bus_integ_error"; + sec_cm_alert_name = "fatal_check_error"; + + super.initialize(csr_base_addr); + + // create push_pull agent config obj + for (int i = 0; i < NumSramKeyReqSlots; i++) begin + string cfg_name = $sformatf("sram_pull_agent_cfg[%0d]", i); + m_sram_pull_agent_cfg[i] = push_pull_agent_cfg#(.DeviceDataWidth(SRAM_DATA_SIZE))::type_id + ::create(cfg_name); + m_sram_pull_agent_cfg[i].agent_type = PullAgent; + end + + m_otbn_pull_agent_cfg = push_pull_agent_cfg#(.DeviceDataWidth(OTBN_DATA_SIZE))::type_id + ::create("m_otbn_pull_agent_cfg"); + m_otbn_pull_agent_cfg.agent_type = PullAgent; + + m_flash_data_pull_agent_cfg = push_pull_agent_cfg#(.DeviceDataWidth(FLASH_DATA_SIZE))::type_id + ::create("m_flash_data_pull_agent_cfg"); + m_flash_data_pull_agent_cfg.agent_type = PullAgent; + m_flash_addr_pull_agent_cfg = push_pull_agent_cfg#(.DeviceDataWidth(FLASH_DATA_SIZE))::type_id + ::create("m_flash_addr_pull_agent_cfg"); + m_flash_addr_pull_agent_cfg.agent_type = PullAgent; + + m_lc_prog_pull_agent_cfg = push_pull_agent_cfg#(.HostDataWidth(LC_PROG_DATA_SIZE), + .DeviceDataWidth(1))::type_id::create("m_lc_prog_pull_agent_cfg"); + m_lc_prog_pull_agent_cfg.agent_type = PullAgent; + + // set num_interrupts & num_alerts + num_interrupts = ral.intr_state.get_n_used_bits(); + + // only support 1 outstanding TL items in tlul_adapter + m_tl_agent_cfg.max_outstanding_req = 1; + m_tl_agent_cfgs["otp_ctrl_prim_reg_block"].max_outstanding_req = 1; + + // create the inputs cfg instance + dut_cfg = otp_ctrl_ast_inputs_cfg::type_id::create("dut_cfg"); + endfunction + +endclass + +`undef OTP_CLK_CONSTRAINT diff --git a/src/fuse_ctrl/dv/env/otp_ctrl_env_cov.sv b/src/fuse_ctrl/dv/env/otp_ctrl_env_cov.sv new file mode 100755 index 0000000..10e7d90 --- /dev/null +++ b/src/fuse_ctrl/dv/env/otp_ctrl_env_cov.sv @@ -0,0 +1,389 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// DO NOT EDIT THIS FILE DIRECTLY. +// It has been generated with ./util/design/gen-otp-mmap.py + +/** + * Covergoups that are dependent on run-time parameters that may be available + * only in build_phase can be defined here + * Covergroups may also be wrapped inside helper classes if needed. + */ +class otp_ctrl_unbuf_err_code_cg_wrap; + // Unbuffered partition can use TLUL interface to read out but cannot write, thus error_code does + // not have write_blank_err. + covergroup unbuf_err_code_cg(string name) with function sample(bit [TL_DW-1:0] val); + option.per_instance = 1; + option.name = name; + err_code_vals: coverpoint val { + bins no_err = {OtpNoError}; + bins macro_err = {OtpMacroError}; + bins ecc_corr_err = {OtpMacroEccCorrError}; + bins ecc_uncorr_err = {OtpMacroEccUncorrError}; + bins access_err = {OtpAccessError}; + bins check_fail = {OtpCheckFailError}; + bins fsm_err = {OtpFsmStateError}; + illegal_bins illegal_err = default; + } + endgroup + + function new(string name); + unbuf_err_code_cg = new(name); + endfunction +endclass + +class otp_ctrl_buf_err_code_cg_wrap; + // Buffered partition must use DAI interface to access partition, so it does not have access_err + // and write_blank err. + covergroup buf_err_code_cg(string name) with function sample(bit [TL_DW-1:0] val); + option.per_instance = 1; + option.name = name; + err_code_vals: coverpoint val { + bins no_err = {OtpNoError}; + bins macro_err = {OtpMacroError}; + bins ecc_corr_err = {OtpMacroEccCorrError}; + bins ecc_uncorr_err = {OtpMacroEccUncorrError}; + bins check_fail = {OtpCheckFailError}; + bins fsm_err = {OtpFsmStateError}; + illegal_bins illegal_err = default; + } + endgroup + + function new(string name); + buf_err_code_cg = new(name); + endfunction +endclass + +class otp_ctrl_csr_rd_after_alert_cg_wrap; + // This covergroup samples CSRs being checked (via CSR read) after fatal alert is issued. + covergroup csr_rd_after_alert_cg(otp_ctrl_core_reg_block ral) with function sample(bit[TL_DW-1:0] + csr_offset); + read_csr_after_alert_issued: coverpoint csr_offset { + bins unbuffered_digests = { + ral.vendor_test_digest[0].get_offset(), + ral.vendor_test_digest[1].get_offset(), + ral.creator_sw_cfg_digest[0].get_offset(), + ral.creator_sw_cfg_digest[1].get_offset(), + ral.owner_sw_cfg_digest[0].get_offset(), + ral.owner_sw_cfg_digest[1].get_offset(), + ral.rot_creator_auth_codesign_digest[0].get_offset(), + ral.rot_creator_auth_codesign_digest[1].get_offset(), + ral.rot_creator_auth_state_digest[0].get_offset(), + ral.rot_creator_auth_state_digest[1].get_offset() + }; + bins hw_digests = { + ral.hw_cfg0_digest[0].get_offset(), + ral.hw_cfg0_digest[1].get_offset(), + ral.hw_cfg1_digest[0].get_offset(), + ral.hw_cfg1_digest[1].get_offset() + }; + bins secret_digests = { + ral.secret0_digest[0].get_offset(), + ral.secret0_digest[1].get_offset(), + ral.secret1_digest[0].get_offset(), + ral.secret1_digest[1].get_offset(), + ral.secret2_digest[0].get_offset(), + ral.secret2_digest[1].get_offset() + }; + bins direct_access_rdata = { + ral.direct_access_rdata[0].get_offset(), + ral.direct_access_rdata[1].get_offset() + }; + bins status = { + ral.status.get_offset() + }; + bins error_code = { + ral.err_code[0].get_offset(), + ral.err_code[1].get_offset(), + ral.err_code[2].get_offset(), + ral.err_code[3].get_offset(), + ral.err_code[4].get_offset(), + ral.err_code[5].get_offset(), + ral.err_code[6].get_offset(), + ral.err_code[7].get_offset(), + ral.err_code[8].get_offset(), + ral.err_code[9].get_offset(), + ral.err_code[10].get_offset(), + ral.err_code[11].get_offset(), + ral.err_code[12].get_offset() + }; + } + endgroup + + function new(otp_ctrl_core_reg_block ral); + csr_rd_after_alert_cg = new(ral); + endfunction + + function void sample(bit[TL_DW-1:0] csr_offset); + csr_rd_after_alert_cg.sample(csr_offset); + endfunction +endclass + +class otp_ctrl_unbuf_access_lock_cg_wrap; + covergroup unbuf_access_lock_cg(string name) with function sample(bit read_lock, bit write_lock, + bit is_write); + option.per_instance = 1; + option.name = name; + read_access_locked: coverpoint read_lock; + write_access_locked: coverpoint write_lock; + operation_type: coverpoint is_write { + bins write_op = {1}; + bins read_op = {0}; + } + unbuf_part_access_cross: cross read_access_locked, write_access_locked, operation_type; + endgroup + + function new(string name); + unbuf_access_lock_cg = new(name); + endfunction + + function void sample(bit read_lock, bit write_lock, bit is_write); + unbuf_access_lock_cg.sample(read_lock, write_lock, is_write); + endfunction +endclass + +class otp_ctrl_env_cov extends cip_base_env_cov #(.CFG_T(otp_ctrl_env_cfg)); + `uvm_component_utils(otp_ctrl_env_cov) + + // the base class provides the following handles for use: + // otp_ctrl_env_cfg: cfg + + otp_ctrl_unbuf_err_code_cg_wrap unbuf_err_code_cg_wrap[NumPartUnbuf]; + otp_ctrl_buf_err_code_cg_wrap buf_err_code_cg_wrap[NumPartBuf]; + otp_ctrl_csr_rd_after_alert_cg_wrap csr_rd_after_alert_cg_wrap; + otp_ctrl_unbuf_access_lock_cg_wrap unbuf_access_lock_cg_wrap[NumPartUnbuf]; + + bit_toggle_cg_wrap lc_prog_cg; + bit_toggle_cg_wrap otbn_req_cg; + bit_toggle_cg_wrap status_csr_cg[OtpStatusFieldSize]; + + // covergroups + // This covergroup collects different conditions when outputs (hwcfg_o, keymgr_key_o) are checked + // in scb: + // - If lc_esc_en is On + // - If each partition is locked (expect LC) + covergroup power_on_cg with function sample (bit lc_esc_en, bit[NumPart-2:0] parts_locked); + lc_esc: coverpoint lc_esc_en; + vendor_test_lock: coverpoint parts_locked[0]; + creator_sw_cfg_lock: coverpoint parts_locked[1]; + owner_sw_cfg_lock: coverpoint parts_locked[2]; + rot_creator_auth_codesign_lock: coverpoint parts_locked[3]; + rot_creator_auth_state_lock: coverpoint parts_locked[4]; + hw_cfg0_lock: coverpoint parts_locked[5]; + hw_cfg1_lock: coverpoint parts_locked[6]; + secret0_lock: coverpoint parts_locked[7]; + secret1_lock: coverpoint parts_locked[8]; + secret2_lock: coverpoint parts_locked[9]; + endgroup + + // This covergroup is sampled only if flash request passed scb check. + covergroup flash_req_cg with function sample (int index, bit locked); + flash_index: coverpoint index { + bins flash_data_key = {FlashDataKey}; + bins flash_addr_key = {FlashAddrKey}; + illegal_bins il = default; + } + secret1_lock: coverpoint locked; + flash_req_lock_cross: cross flash_index, secret1_lock; + endgroup + + // This covergroup is sampled only if sram request passed scb check. + covergroup sram_req_cg with function sample (int index, bit locked); + sram_index: coverpoint index { + bins sram_key[NumSramKeyReqSlots] = {[0:(NumSramKeyReqSlots-1)]}; + illegal_bins il = default; + } + secret1_lock: coverpoint locked; + sram_req_lock_cross: cross sram_index, secret1_lock; + endgroup + + // This covergroup is sampled only if keymgr output passed scb check. + covergroup keymgr_o_cg with function sample (bit lc_seed_hw_rd_en, bit locked); + keymgr_rd_en: coverpoint lc_seed_hw_rd_en; + // TODO: probably should add all partitions with keymgr material here. + secret2_lock: coverpoint locked; + keymgr_output_conditions: cross keymgr_rd_en, secret2_lock; + endgroup + + // This covergroup samples dai request being issued after fatal alert is issued. + covergroup req_dai_access_after_alert_cg with function sample(bit [TL_DW-1:0] val); + req_dai_access_after_alert_issued: coverpoint val { + bins dai_write = {DaiWrite}; + bins dai_read = {DaiRead}; + bins dai_digest = {DaiDigest}; + } + endgroup + + // This covergroup samples background check being issued after fatal alert is issued. + covergroup issue_checks_after_alert_cg with function sample(bit [TL_DW-1:0] val); + issue_checks_after_alert_issued: coverpoint val { + bins integrity_check = {1}; + bins consistency_check = {2}; + } + endgroup + + // This covergroup collects DAI err_code value. + // DAI access does not have checks, thus no check_fail error. + covergroup dai_err_code_cg with function sample(bit [TL_DW-1:0] val, int part_idx); + err_code_vals: coverpoint val { + bins no_err = {OtpNoError}; + bins macro_err = {OtpMacroError}; + bins ecc_corr_err = {OtpMacroEccCorrError}; + bins ecc_uncorr_err = {OtpMacroEccUncorrError}; + bins write_blank_err = {OtpMacroWriteBlankError}; + bins access_err = {OtpAccessError}; + bins fsm_err = {OtpFsmStateError}; + illegal_bins illegal_err = default; + } + partition: coverpoint part_idx { + bins vendor_test = {VendorTestIdx}; + bins creator_sw_cfg = {CreatorSwCfgIdx}; + bins owner_sw_cfg = {OwnerSwCfgIdx}; + bins rot_creator_auth_codesign = {RotCreatorAuthCodesignIdx}; + bins rot_creator_auth_state = {RotCreatorAuthStateIdx}; + bins hw_cfg0 = {HwCfg0Idx}; + bins hw_cfg1 = {HwCfg1Idx}; + bins secret0 = {Secret0Idx}; + bins secret1 = {Secret1Idx}; + bins secret2 = {Secret2Idx}; + bins life_cycle = {LifeCycleIdx}; + bins illegal_idx = default; + } + // LC partition has a separate LCI err_code to collect macro related errors. + dai_err_code_for_all_partitions: cross err_code_vals, partition { + // Illegal bin - vendor_test partition does not have EccUncorrectable error. + illegal_bins vendor_test_ecc_uncorrectable_err = + binsof (partition.vendor_test) && binsof (err_code_vals.ecc_uncorr_err); + ignore_bins life_cycle_ignore = binsof (partition.life_cycle) && + binsof(err_code_vals) intersect {[OtpMacroError:OtpMacroWriteBlankError]}; + } + endgroup + + // This covergroup collects LCI err_code value. + // LCI access does not have digest, thus no access_err. Check_fail, ecc_errors are covered in lc + // buffered partition instead of LCI here. + covergroup lci_err_code_cg with function sample(bit [TL_DW-1:0] val); + err_code_vals: coverpoint val { + bins no_err = {OtpNoError}; + bins macro_err = {OtpMacroError}; + bins write_blank_err = {OtpMacroWriteBlankError}; + bins fsm_err = {OtpFsmStateError}; + illegal_bins illegal_err = default; + } + endgroup + + covergroup dai_access_secret2_cg with function sample(bit lc_rw_en, dai_cmd_e dai_cmd); + lc_creator_seed_sw_rw_en: coverpoint lc_rw_en; + dai_access_cmd: coverpoint dai_cmd { + bins dai_rd = {DaiRead}; + bins dai_wr = {DaiWrite}; + bins dai_digest = {DaiDigest}; + } + dai_access_secret2: cross lc_creator_seed_sw_rw_en, dai_access_cmd; + endgroup + + function new(string name, uvm_component parent); + super.new(name, parent); + // Create coverage from local covergroups. + power_on_cg = new(); + flash_req_cg = new(); + sram_req_cg = new(); + keymgr_o_cg = new(); + req_dai_access_after_alert_cg = new(); + issue_checks_after_alert_cg = new(); + dai_err_code_cg = new(); + lci_err_code_cg = new(); + dai_access_secret2_cg = new(); + endfunction : new + + virtual function void build_phase(uvm_phase phase); + super.build_phase(phase); + // Create instances from bit_toggle_cg_wrapper. + lc_prog_cg = new("lc_prog_cg", "", 0); + otbn_req_cg = new("otbn_req_cg", "", 0); + foreach (status_csr_cg[i]) begin + otp_status_e index = otp_status_e'(i); + status_csr_cg[i]= new(index.name, "status_csr_cg", 0); + end + + // Create instances from external wrapper classes. + csr_rd_after_alert_cg_wrap = new(cfg.ral); + foreach (unbuf_err_code_cg_wrap[i]) begin + otp_status_e index = otp_status_e'(i); + unbuf_err_code_cg_wrap[i] = new($sformatf("unbuf_err_code_cg_wrap[%0s]", index.name)); + end + foreach (buf_err_code_cg_wrap[i]) begin + otp_status_e index = otp_status_e'(i + 2); + buf_err_code_cg_wrap[i] = new($sformatf("buf_err_code_cg_wrap[%0s]", index.name)); + end + foreach (unbuf_access_lock_cg_wrap[i]) begin + part_idx_e index = part_idx_e'(i); + unbuf_access_lock_cg_wrap[i] = new($sformatf("buf_err_code_cg_wrap[%0s]", index.name)); + end + endfunction + + function void collect_status_cov(bit [TL_DW-1:0] val); + foreach (status_csr_cg[i]) begin + status_csr_cg[i].sample(val[i]); + end + endfunction + + // Collect coverage for err_code when it is a compact multi-reg. For DAI error it uses the given + // access_part_idx as the target of the DAI access. + function void collect_compact_err_code_cov(bit [TL_DW-1:0] val, int access_part_idx = DaiIdx); + dv_base_reg_field err_code_flds[$]; + cfg.ral.err_code[0].get_dv_base_reg_fields(err_code_flds); + foreach (err_code_flds[part]) begin + collect_err_code_cov(part, get_field_val(err_code_flds[part], val), access_part_idx); + end + endfunction + + // Collect coverage for a given partition error_code. For DAI error it uses the given + // access_part_idx as the target of the DAI access. + function void collect_err_code_cov(int part_idx, bit [TL_DW-1:0] val, + int access_part_idx = DaiIdx); + case (part_idx) + OtpVendorTestErrIdx: begin + unbuf_err_code_cg_wrap[part_idx].unbuf_err_code_cg.sample(val); + end + OtpCreatorSwCfgErrIdx: begin + unbuf_err_code_cg_wrap[part_idx].unbuf_err_code_cg.sample(val); + end + OtpOwnerSwCfgErrIdx: begin + unbuf_err_code_cg_wrap[part_idx].unbuf_err_code_cg.sample(val); + end + OtpRotCreatorAuthCodesignErrIdx: begin + unbuf_err_code_cg_wrap[part_idx].unbuf_err_code_cg.sample(val); + end + OtpRotCreatorAuthStateErrIdx: begin + unbuf_err_code_cg_wrap[part_idx].unbuf_err_code_cg.sample(val); + end + OtpHwCfg0ErrIdx: begin + buf_err_code_cg_wrap[part_idx - NumPartUnbuf].buf_err_code_cg.sample(val); + end + OtpHwCfg1ErrIdx: begin + buf_err_code_cg_wrap[part_idx - NumPartUnbuf].buf_err_code_cg.sample(val); + end + OtpSecret0ErrIdx: begin + buf_err_code_cg_wrap[part_idx - NumPartUnbuf].buf_err_code_cg.sample(val); + end + OtpSecret1ErrIdx: begin + buf_err_code_cg_wrap[part_idx - NumPartUnbuf].buf_err_code_cg.sample(val); + end + OtpSecret2ErrIdx: begin + buf_err_code_cg_wrap[part_idx - NumPartUnbuf].buf_err_code_cg.sample(val); + end + OtpLifeCycleErrIdx: begin + end + OtpDaiErrIdx: begin + dai_err_code_cg.sample(val, access_part_idx); + end + OtpLciErrIdx: begin + lci_err_code_cg.sample(val); + end + default: begin + `uvm_fatal(`gfn, $sformatf("invalid err_code index %0d", part_idx)) + end + endcase + endfunction +endclass diff --git a/src/fuse_ctrl/dv/env/otp_ctrl_env_pkg.sv b/src/fuse_ctrl/dv/env/otp_ctrl_env_pkg.sv new file mode 100755 index 0000000..79026db --- /dev/null +++ b/src/fuse_ctrl/dv/env/otp_ctrl_env_pkg.sv @@ -0,0 +1,266 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// DO NOT EDIT THIS FILE DIRECTLY. +// It has been generated with ./util/design/gen-otp-mmap.py + +package otp_ctrl_env_pkg; + // dep packages + import uvm_pkg::*; + import top_pkg::*; + import dv_utils_pkg::*; + import dv_lib_pkg::*; + import dv_base_reg_pkg::*; + import tl_agent_pkg::*; + import cip_base_pkg::*; + import csr_utils_pkg::*; + import push_pull_agent_pkg::*; + import otp_ctrl_core_ral_pkg::*; + import otp_ctrl_prim_ral_pkg::*; + import otp_ctrl_reg_pkg::*; + import otp_ctrl_pkg::*; + import otp_ctrl_part_pkg::*; + import lc_ctrl_pkg::*; + import lc_ctrl_state_pkg::*; + import lc_ctrl_dv_utils_pkg::*; + import mem_bkdr_util_pkg::*; + import otp_scrambler_pkg::*; + import sec_cm_pkg::*; + + // macro includes + `include "uvm_macros.svh" + `include "dv_macros.svh" + + // parameters + parameter string LIST_OF_ALERTS[] = {"fatal_macro_error", + "fatal_check_error", + "fatal_bus_integ_error", + "fatal_prim_otp_alert", + "recov_prim_otp_alert"}; + parameter uint NUM_ALERTS = 5; + parameter uint NUM_EDN = 1; + + parameter uint DIGEST_SIZE = 8; + parameter uint SW_WINDOW_BASE_ADDR = 'h800; + parameter uint SW_WINDOW_SIZE = NumSwCfgWindowWords * 4; + + parameter uint TL_SIZE = (TL_DW / 8); + // LC has its own storage in scb + // we can use the LC offset here because it will always be the last partition. + parameter uint OTP_ARRAY_SIZE = LcTransitionCntOffset / TL_SIZE; + + parameter int OTP_ADDR_WIDTH = OtpByteAddrWidth-2; + + parameter uint NUM_PRIM_REG = 8; + + // sram rsp data has 1 bit for seed_valid, the rest are for key and nonce + parameter uint SRAM_DATA_SIZE = 1 + SramKeyWidth + SramNonceWidth; + // otbn rsp data has 1 bit for seed_valid, the rest are for key and nonce + parameter uint OTBN_DATA_SIZE = 1 + OtbnKeyWidth + OtbnNonceWidth; + // flash rsp data has 1 bit for seed_valid, the rest are for key + parameter uint FLASH_DATA_SIZE = 1 + FlashKeyWidth; + // lc program data has lc_state data and lc_cnt data + parameter uint LC_PROG_DATA_SIZE = LcStateWidth + LcCountWidth; + + parameter uint NUM_SRAM_EDN_REQ = 12; + parameter uint NUM_OTBN_EDN_REQ = 10; + + parameter uint CHK_TIMEOUT_CYC = 40; + + // When fatal alert triggered, all partitions and the DAI & LCI go to error state and status will + // be set to 1. + parameter bit [NumErrorEntries-1:0] FATAL_EXP_STATUS = '1; + + // lc does not have dai access + parameter int PART_BASE_ADDRS [NumPart-1] = { + VendorTestOffset, + CreatorSwCfgOffset, + OwnerSwCfgOffset, + RotCreatorAuthCodesignOffset, + RotCreatorAuthStateOffset, + HwCfg0Offset, + HwCfg1Offset, + Secret0Offset, + Secret1Offset, + Secret2Offset + }; + + // lc does not have digest + parameter int PART_OTP_DIGEST_ADDRS [NumPart-1] = { + VendorTestDigestOffset >> 2, + CreatorSwCfgDigestOffset >> 2, + OwnerSwCfgDigestOffset >> 2, + RotCreatorAuthCodesignDigestOffset >> 2, + RotCreatorAuthStateDigestOffset >> 2, + HwCfg0DigestOffset >> 2, + HwCfg1DigestOffset >> 2, + Secret0DigestOffset >> 2, + Secret1DigestOffset >> 2, + Secret2DigestOffset >> 2 + }; + + // types + typedef enum bit [1:0] { + OtpOperationDone, + OtpErr, + NumOtpCtrlIntr + } otp_intr_e; + + typedef enum bit [5:0] { + OtpVendorTestErrIdx, + OtpCreatorSwCfgErrIdx, + OtpOwnerSwCfgErrIdx, + OtpRotCreatorAuthCodesignErrIdx, + OtpRotCreatorAuthStateErrIdx, + OtpHwCfg0ErrIdx, + OtpHwCfg1ErrIdx, + OtpSecret0ErrIdx, + OtpSecret1ErrIdx, + OtpSecret2ErrIdx, + OtpLifeCycleErrIdx, + OtpDaiErrIdx, + OtpLciErrIdx, + OtpTimeoutErrIdx, + OtpLfsrFsmErrIdx, + OtpScramblingFsmErrIdx, + OtpDerivKeyFsmErrIdx, + OtpBusIntegErrorIdx, + OtpDaiIdleIdx, + OtpCheckPendingIdx, + OtpStatusFieldSize + } otp_status_e; + + typedef enum bit [2:0] { + OtpNoError, + OtpMacroError, + OtpMacroEccCorrError, + OtpMacroEccUncorrError, + OtpMacroWriteBlankError, + OtpAccessError, + OtpCheckFailError, + OtpFsmStateError + } otp_err_code_e; + + typedef enum bit [1:0] { + OtpNoEccErr, + OtpEccCorrErr, + OtpEccUncorrErr + } otp_ecc_err_e; + + typedef enum bit [1:0] { + OtpNoAlert, + OtpCheckAlert, + OtpMacroAlert + } otp_alert_e; + + typedef struct packed { + bit read_lock; + bit write_lock; + } otp_part_access_lock_t; + + // OTP conditions when driving specific port. + typedef enum bit [2:0] { + DuringOTPInit, + DuringOTPDaiBusy, + DuringOTPDaiDigest, + DuringOTPRead, + DriveRandomly + } port_drive_condition_e; + + typedef virtual otp_ctrl_if otp_ctrl_vif; + + parameter otp_err_code_e OTP_TERMINAL_ERRS[4] = {OtpMacroEccUncorrError, + OtpCheckFailError, + OtpFsmStateError, + OtpMacroError}; + + // functions + function automatic int get_part_index(bit [TL_DW-1:0] addr); + int index; + for (index = 0; index < NumPart; index++) begin + if (PartInfo[index].offset > addr) begin + index--; + break; + end + end + if (index == NumPart) index--; + return index; + endfunction + + function automatic bit is_secret(bit [TL_DW-1:0] addr); + int part_index = get_part_index(addr); + return PartInfo[part_index].secret; + endfunction + + function automatic bit part_has_digest(int part_idx); + return PartInfo[part_idx].hw_digest || PartInfo[part_idx].sw_digest; + endfunction + + function automatic bit part_has_hw_digest(int part_idx); + return PartInfo[part_idx].hw_digest; + endfunction + + function automatic bit is_sw_digest(bit [TL_DW-1:0] addr); + int part_idx = get_part_index(addr); + if (PartInfo[part_idx].sw_digest) begin + // If the partition contains a digest, it will be located in the last 64bit of the partition. + return {addr[TL_DW-1:3], 3'b0} == ((PartInfo[part_idx].offset + PartInfo[part_idx].size) - 8); + end else begin + return 0; + end + endfunction + + function automatic bit is_digest(bit [TL_DW-1:0] addr); + int part_idx = get_part_index(addr); + if (PartInfo[part_idx].sw_digest || PartInfo[part_idx].hw_digest) begin + // If the partition contains a digest, it will be located in the last 64bit of the partition. + return {addr[TL_DW-1:3], 3'b0} == ((PartInfo[part_idx].offset + PartInfo[part_idx].size) - 8); + end else begin + return 0; + end + endfunction + + function automatic bit is_sw_part(bit [TL_DW-1:0] addr); + int part_idx = get_part_index(addr); + return is_sw_part_idx(part_idx); + endfunction + + function automatic bit is_sw_part_idx(int part_idx); + return (PartInfo[part_idx].variant == Unbuffered); + endfunction + + function automatic bit is_hw_part(bit [TL_DW-1:0] addr); + int part_idx = get_part_index(addr); + return is_hw_part_idx(part_idx); + endfunction + + function automatic bit is_hw_part_idx(int part_idx); + return (PartInfo[part_idx].variant == Buffered); + endfunction + + // Returns true if this partition supports ECC. Otherwise, no ECC errors are reported, and + // the single bit errors are not corrected. + function automatic bit part_has_integrity(int part_idx); + return PartInfo[part_idx].integrity; + endfunction + + // Resolve an offset within the software window as an offset within the whole otp_ctrl block. + function automatic bit [TL_AW-1:0] get_sw_window_offset(bit [TL_AW-1:0] dai_addr); + return dai_addr + SW_WINDOW_BASE_ADDR; + endfunction + + function automatic bit [TL_DW-1:0] normalize_dai_addr(bit [TL_DW-1:0] dai_addr); + normalize_dai_addr = (is_secret(dai_addr) || is_digest(dai_addr)) ? dai_addr >> 3 << 3 : + dai_addr >> 2 << 2; + endfunction + + // package sources + `include "otp_ctrl_ast_inputs_cfg.sv" + `include "otp_ctrl_env_cfg.sv" + `include "otp_ctrl_env_cov.sv" + `include "otp_ctrl_virtual_sequencer.sv" + `include "otp_ctrl_scoreboard.sv" + `include "otp_ctrl_env.sv" + `include "otp_ctrl_vseq_list.sv" + +endpackage diff --git a/src/fuse_ctrl/dv/env/otp_ctrl_if.sv b/src/fuse_ctrl/dv/env/otp_ctrl_if.sv new file mode 100755 index 0000000..a2ae621 --- /dev/null +++ b/src/fuse_ctrl/dv/env/otp_ctrl_if.sv @@ -0,0 +1,369 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// DO NOT EDIT THIS FILE DIRECTLY. +// It has been generated with ./util/design/gen-otp-mmap.py + +// This interface collect the broadcast output data from OTP, +// and drive input requests coming into OTP. +`define ECC_REG_PATH gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec + +// This only supports buffered partitions. +`define BUF_PART_OTP_CMD_PATH(i) \ + tb.dut.gen_partitions[``i``].gen_buffered.u_part_buf.otp_cmd_o + +`define LC_PART_OTP_CMD_PATH \ + tb.dut.gen_partitions[LifeCycleIdx].gen_lifecycle.u_part_buf.otp_cmd_o + +`define FORCE_OTP_PART_LOCK_WITH_RAND_NON_MUBI_VAL(i) \ + if (forced_part_access_sel[``i``].read_lock) begin \ + force tb.dut.part_access[``i``].read_lock = get_rand_mubi8_val(.t_weight(0), .f_weight(0)); \ + force tb.dut.part_access_dai[``i``].read_lock = get_rand_mubi8_val(.t_weight(0), .f_weight(0)); \ + end \ + if (forced_part_access_sel[``i``].write_lock) begin \ + force tb.dut.part_access[``i``].write_lock = get_rand_mubi8_val(.t_weight(0), .f_weight(0)); \ + force tb.dut.part_access_dai[``i``].write_lock = get_rand_mubi8_val(.t_weight(0), .f_weight(0)); \ + end + +`ifndef PRIM_GENERIC_OTP_PATH + `define PRIM_GENERIC_OTP_PATH\ + tb.dut.u_otp +`endif + +`ifndef PRIM_GENERIC_OTP_CMD_I_PATH + `define PRIM_GENERIC_OTP_CMD_I_PATH \ + `PRIM_GENERIC_OTP_PATH.gen_generic.u_impl_generic.cmd_i +`endif + +interface otp_ctrl_if(input clk_i, input rst_ni); + import uvm_pkg::*; + import otp_ctrl_env_pkg::*; + import otp_ctrl_pkg::*; + import otp_ctrl_reg_pkg::*; + import otp_ctrl_part_pkg::*; + import cip_base_pkg::*; + + // Output from DUT + otp_broadcast_t otp_broadcast_o; + otp_keymgr_key_t keymgr_key_o; + otp_lc_data_t lc_data_o; + logic pwr_otp_done_o, pwr_otp_idle_o; + + // Inputs to DUT + logic pwr_otp_init_i, scan_en_i, scan_rst_ni, ext_voltage_h_io; + lc_ctrl_pkg::lc_tx_t lc_dft_en_i, lc_escalate_en_i, lc_check_byp_en_i, + lc_creator_seed_sw_rw_en_i, lc_owner_seed_sw_rw_en_i, + lc_seed_hw_rd_en_i; + prim_mubi_pkg::mubi4_t scanmode_i; + otp_ast_rsp_t otp_ast_pwr_seq_h_i; + ast_pkg::ast_obs_ctrl_t obs_ctrl_i; + + // Unused in prim_generic_otp memory. + logic [OtpTestCtrlWidth-1:0] otp_vendor_test_ctrl_i; + logic [OtpTestStatusWidth-1:0] otp_vendor_test_status_o; + logic [OtpTestVectWidth-1:0] cio_test_o; + logic [OtpTestVectWidth-1:0] cio_test_en_o; + + // Connect with lc_prog push_pull interface. + logic lc_prog_req, lc_prog_err; + logic lc_prog_err_dly1, lc_prog_no_sta_check; + + // Connect push_pull interfaces ack signals for assertion checks. + logic otbn_ack, lc_prog_ack; + logic [1:0] flash_acks; + logic [NumSramKeyReqSlots-1:0] sram_acks; + + // Variables for internal interface logic. + // `lc_escalate_en` is async, take two clock cycles to synchronize. + lc_ctrl_pkg::lc_tx_t lc_esc_dly1, lc_esc_dly2; + + // Variable for scoreboard. + // For `lc_escalate_en`, any value that is not `Off` is a `On`. + bit lc_esc_on; + + // Probe design signal for alert request. + logic alert_reqs; + + // Usually the `lc_check_byp_en` will be automatically set to `On` when LC program request is + // issued, and stays `On` until reset is issued. + // Set this variable to 0 after a LC program request might cause otp checks to fail. + bit lc_check_byp_en = 1; + + // Internal veriable to track which sw partitions have ECC reg error. + bit [NumPartUnbuf-1:0] force_sw_parts_ecc_reg; + + // DUT configuration object + otp_ctrl_ast_inputs_cfg dut_cfg; + + // for DV macros ID + string msg_id = "otp_ctrl_if"; + + // Lc_err could trigger during LC program, so check intr and status after lc_req is finished. + // Lc_err takes one clock cycle to propogate to intr signal. So avoid intr check if it happens + // during the transition. + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + lc_prog_err_dly1 <= 0; + lc_esc_dly1 <= lc_ctrl_pkg::Off; + lc_esc_dly2 <= lc_ctrl_pkg::Off; + lc_check_byp_en_i <= get_rand_lc_tx_val(); + lc_esc_on <= 0; + end else begin + lc_prog_err_dly1 <= lc_prog_err; + lc_esc_dly1 <= lc_escalate_en_i; + lc_esc_dly2 <= lc_esc_dly1; + if (lc_prog_req) begin + lc_check_byp_en_i <= lc_check_byp_en ? lc_ctrl_pkg::On : lc_ctrl_pkg::Off; + end + if (lc_esc_dly2 != lc_ctrl_pkg::Off && !lc_esc_on) begin + lc_esc_on <= 1; + end + end + end + + assign lc_prog_no_sta_check = lc_prog_err | lc_prog_err_dly1 | lc_prog_req | lc_esc_on; + + function automatic void drive_pwr_otp_init(logic val); + pwr_otp_init_i = val; + endfunction + + function automatic void drive_ext_voltage_h_io(logic val); + ext_voltage_h_io = val; + endfunction + + function automatic void drive_lc_creator_seed_sw_rw_en(lc_ctrl_pkg::lc_tx_t val); + lc_creator_seed_sw_rw_en_i = val; + endfunction + + function automatic void drive_lc_owner_seed_sw_rw_en(lc_ctrl_pkg::lc_tx_t val); + lc_owner_seed_sw_rw_en_i = val; + endfunction + + function automatic void drive_lc_dft_en(lc_ctrl_pkg::lc_tx_t val); + lc_dft_en_i = val; + endfunction + + function automatic void drive_lc_escalate_en(lc_ctrl_pkg::lc_tx_t val); + lc_escalate_en_i = val; + endfunction + + function automatic void drive_lc_seed_hw_rd_en(lc_ctrl_pkg::lc_tx_t val); + lc_seed_hw_rd_en_i = val; + endfunction + + function automatic bit under_error_states(); + return lc_esc_on | alert_reqs; + endfunction + + // SW partitions do not have any internal checks. + // Here we force internal ECC check to fail. + task automatic force_sw_check_fail( + bit[NumPartUnbuf-1:0] fail_idx = $urandom_range(1, (1'b1 << NumPartUnbuf) - 1)); + @(posedge clk_i); + if (fail_idx[VendorTestIdx]) begin + force tb.dut.gen_partitions[VendorTestIdx].gen_unbuffered. + u_part_unbuf.`ECC_REG_PATH.data_i[0] = 1; + force_sw_parts_ecc_reg[VendorTestIdx] = 1; + end + if (fail_idx[CreatorSwCfgIdx]) begin + force tb.dut.gen_partitions[CreatorSwCfgIdx].gen_unbuffered. + u_part_unbuf.`ECC_REG_PATH.data_i[0] = 1; + force_sw_parts_ecc_reg[CreatorSwCfgIdx] = 1; + end + if (fail_idx[OwnerSwCfgIdx]) begin + force tb.dut.gen_partitions[OwnerSwCfgIdx].gen_unbuffered. + u_part_unbuf.`ECC_REG_PATH.data_i[0] = 1; + force_sw_parts_ecc_reg[OwnerSwCfgIdx] = 1; + end + if (fail_idx[RotCreatorAuthCodesignIdx]) begin + force tb.dut.gen_partitions[RotCreatorAuthCodesignIdx].gen_unbuffered. + u_part_unbuf.`ECC_REG_PATH.data_i[0] = 1; + force_sw_parts_ecc_reg[RotCreatorAuthCodesignIdx] = 1; + end + if (fail_idx[RotCreatorAuthStateIdx]) begin + force tb.dut.gen_partitions[RotCreatorAuthStateIdx].gen_unbuffered. + u_part_unbuf.`ECC_REG_PATH.data_i[0] = 1; + force_sw_parts_ecc_reg[RotCreatorAuthStateIdx] = 1; + end + endtask + + task automatic release_sw_check_fail(); + @(posedge clk_i); + if (force_sw_parts_ecc_reg[VendorTestIdx]) begin + release tb.dut.gen_partitions[VendorTestIdx].gen_unbuffered. + u_part_unbuf.`ECC_REG_PATH.data_i[0]; + force_sw_parts_ecc_reg[VendorTestIdx] = 0; + end + if (force_sw_parts_ecc_reg[CreatorSwCfgIdx]) begin + release tb.dut.gen_partitions[CreatorSwCfgIdx].gen_unbuffered. + u_part_unbuf.`ECC_REG_PATH.data_i[0]; + force_sw_parts_ecc_reg[CreatorSwCfgIdx] = 0; + end + if (force_sw_parts_ecc_reg[OwnerSwCfgIdx]) begin + release tb.dut.gen_partitions[OwnerSwCfgIdx].gen_unbuffered. + u_part_unbuf.`ECC_REG_PATH.data_i[0]; + force_sw_parts_ecc_reg[OwnerSwCfgIdx] = 0; + end + if (force_sw_parts_ecc_reg[RotCreatorAuthCodesignIdx]) begin + release tb.dut.gen_partitions[RotCreatorAuthCodesignIdx].gen_unbuffered. + u_part_unbuf.`ECC_REG_PATH.data_i[0]; + force_sw_parts_ecc_reg[RotCreatorAuthCodesignIdx] = 0; + end + if (force_sw_parts_ecc_reg[RotCreatorAuthStateIdx]) begin + release tb.dut.gen_partitions[RotCreatorAuthStateIdx].gen_unbuffered. + u_part_unbuf.`ECC_REG_PATH.data_i[0]; + force_sw_parts_ecc_reg[RotCreatorAuthStateIdx] = 0; + end + endtask + + // Force prim_generic_otp input cmd_i to a invalid value. + task automatic force_invalid_otp_cmd_i(); + @(posedge clk_i); + force `PRIM_GENERIC_OTP_CMD_I_PATH = prim_otp_pkg::cmd_e'(2'b10); + endtask + + task automatic release_invalid_otp_cmd_i(); + @(posedge clk_i); + release `PRIM_GENERIC_OTP_CMD_I_PATH; + endtask + + // Force part_buf partitions output otp_cmd_o to a invalid value. + task automatic force_invalid_part_cmd_o(int part_idx); + @(posedge clk_i); + case (part_idx) + HwCfg0Idx: force `BUF_PART_OTP_CMD_PATH(HwCfg0Idx) = prim_otp_pkg::cmd_e'(2'b10); + HwCfg1Idx: force `BUF_PART_OTP_CMD_PATH(HwCfg1Idx) = prim_otp_pkg::cmd_e'(2'b10); + Secret0Idx: force `BUF_PART_OTP_CMD_PATH(Secret0Idx) = prim_otp_pkg::cmd_e'(2'b10); + Secret1Idx: force `BUF_PART_OTP_CMD_PATH(Secret1Idx) = prim_otp_pkg::cmd_e'(2'b10); + Secret2Idx: force `BUF_PART_OTP_CMD_PATH(Secret2Idx) = prim_otp_pkg::cmd_e'(2'b10); + LifeCycleIdx: force `LC_PART_OTP_CMD_PATH = prim_otp_pkg::cmd_e'(2'b10); + default: begin + `uvm_fatal("otp_ctrl_if", + $sformatf("force invalid otp_cmd_o only supports buffered partitions: %0d", part_idx)) + end + endcase + endtask + + task automatic release_invalid_part_cmd_o(int part_idx); + @(posedge clk_i); + case (part_idx) + HwCfg0Idx: release `BUF_PART_OTP_CMD_PATH(HwCfg0Idx); + HwCfg1Idx: release `BUF_PART_OTP_CMD_PATH(HwCfg1Idx); + Secret0Idx: release `BUF_PART_OTP_CMD_PATH(Secret0Idx); + Secret1Idx: release `BUF_PART_OTP_CMD_PATH(Secret1Idx); + Secret2Idx: release `BUF_PART_OTP_CMD_PATH(Secret2Idx); + LifeCycleIdx: release `LC_PART_OTP_CMD_PATH; + default: begin + `uvm_fatal("otp_ctrl_if", + $sformatf("release invalid otp_cmd_o only supports buffered partitions: %0d", + part_idx)) + end + endcase + endtask + + // This task forces otp_ctrl's internal mubi signals to values that are not mubi::true or mubi:: + // false. Then scb will check if design treats these values as locking the partition access. + task automatic force_part_access_mubi(otp_part_access_lock_t forced_part_access_sel[NumPart-1]); + @(posedge clk_i); + `FORCE_OTP_PART_LOCK_WITH_RAND_NON_MUBI_VAL(VendorTestIdx) + `FORCE_OTP_PART_LOCK_WITH_RAND_NON_MUBI_VAL(CreatorSwCfgIdx) + `FORCE_OTP_PART_LOCK_WITH_RAND_NON_MUBI_VAL(OwnerSwCfgIdx) + `FORCE_OTP_PART_LOCK_WITH_RAND_NON_MUBI_VAL(RotCreatorAuthCodesignIdx) + `FORCE_OTP_PART_LOCK_WITH_RAND_NON_MUBI_VAL(RotCreatorAuthStateIdx) + `FORCE_OTP_PART_LOCK_WITH_RAND_NON_MUBI_VAL(HwCfg0Idx) + `FORCE_OTP_PART_LOCK_WITH_RAND_NON_MUBI_VAL(HwCfg1Idx) + `FORCE_OTP_PART_LOCK_WITH_RAND_NON_MUBI_VAL(Secret0Idx) + `FORCE_OTP_PART_LOCK_WITH_RAND_NON_MUBI_VAL(Secret1Idx) + `FORCE_OTP_PART_LOCK_WITH_RAND_NON_MUBI_VAL(Secret2Idx) + endtask + + task automatic release_part_access_mubi(); + @(posedge clk_i); + release tb.dut.part_access; + release tb.dut.part_access_dai; + endtask + + // Connectivity assertions for test related I/Os. + `ASSERT(LcOtpTestStatusO_A, otp_vendor_test_status_o == `PRIM_GENERIC_OTP_PATH.test_status_o) + `ASSERT(LcOtpTestCtrlI_A, otp_vendor_test_ctrl_i == `PRIM_GENERIC_OTP_PATH.test_ctrl_i) + + `ASSERT(CioTestOWithDftOn_A, lc_dft_en_i == lc_ctrl_pkg::On |-> + ##[2:3] cio_test_o == `PRIM_GENERIC_OTP_PATH.test_vect_o) + `ASSERT(CioTestOWithDftOff_A, lc_dft_en_i != lc_ctrl_pkg::On |-> ##[2:3] cio_test_o == 0) + `ASSERT(CioTestEnOWithDftOn_A, lc_dft_en_i == lc_ctrl_pkg::On |-> ##[2:3] cio_test_en_o == '1) + `ASSERT(CioTestEnOWithDftOff_A, lc_dft_en_i != lc_ctrl_pkg::On |-> ##[2:3] cio_test_en_o == 0) + + + `define OTP_ASSERT_WO_LC_ESC(NAME, SEQ) \ + `ASSERT(NAME, SEQ, clk_i, !rst_ni || lc_esc_on || alert_reqs) + + // If pwr_otp_idle is set only if pwr_otp init is done + `OTP_ASSERT_WO_LC_ESC(OtpPwrDoneWhenIdle_A, pwr_otp_idle_o |-> pwr_otp_done_o) + + // otp_broadcast_o is valid only when otp init is done + `OTP_ASSERT_WO_LC_ESC(OtpHwCfgValidOn_A, pwr_otp_done_o |-> + otp_broadcast_o.valid == lc_ctrl_pkg::On) + // If otp_broadcast is Off, then hw partition is not finished calculation, + // then otp init is not done + `OTP_ASSERT_WO_LC_ESC(OtpHwCfgValidOff_A, otp_broadcast_o.valid == lc_ctrl_pkg::Off |-> + pwr_otp_done_o == 0) + // Once OTP init is done, otp_broadcast_o output value stays stable until next power cycle + `OTP_ASSERT_WO_LC_ESC(OtpHwCfgStable_A, otp_broadcast_o.valid == lc_ctrl_pkg::On |=> + $stable(otp_broadcast_o)) + + // Otp_keymgr valid is related to part_digest, should not be changed after otp_pwr_init + `OTP_ASSERT_WO_LC_ESC(OtpKeymgrValidStable0_A, pwr_otp_done_o |-> + $stable(keymgr_key_o.creator_root_key_share0_valid)) + `OTP_ASSERT_WO_LC_ESC(OtpKeymgrValidStable1_A, pwr_otp_done_o |-> + $stable(keymgr_key_o.creator_root_key_share1_valid)) + `OTP_ASSERT_WO_LC_ESC(OtpKeymgrValidStable2_A, pwr_otp_done_o |-> + $stable(keymgr_key_o.creator_seed_valid)) + `OTP_ASSERT_WO_LC_ESC(OtpKeymgrValidStable3_A, pwr_otp_done_o |-> + $stable(keymgr_key_o.owner_seed_valid)) + + // During lc_prog_req, either otp_idle will be reset or lc_error is set + `OTP_ASSERT_WO_LC_ESC(LcProgReq_A, $rose(lc_prog_req) |=> + (pwr_otp_idle_o == 0 || $rose(lc_prog_err)) within lc_prog_req[*1:$]) + + // During fatal alert, check if otp outputs revert back to default value. + // Wait three clock cycles until error propogates to each FSM states and regs. + `define OTP_FATAL_ERR_ASSERT(NAME, SEQ) \ + `ASSERT(FatalErr``NAME``, alert_reqs |-> ##3 SEQ) + + `OTP_FATAL_ERR_ASSERT(LcDataValid_A, lc_data_o.valid == 0 && lc_data_o.error == 1) + `OTP_FATAL_ERR_ASSERT(LcDataState_A, lc_data_o.state == + PartInvDefault[LcStateOffset*8+:LcStateSize*8]) + `OTP_FATAL_ERR_ASSERT(LcDataCount_A, lc_data_o.count == + PartInvDefault[LcTransitionCntOffset*8+:LcTransitionCntSize*8]) + `OTP_FATAL_ERR_ASSERT(LcDataTestUnlockToken_A, lc_data_o.test_unlock_token == + PartInvDefault[TestUnlockTokenOffset*8+:TestUnlockTokenSize*8]) + `OTP_FATAL_ERR_ASSERT(LcDataTestExitToken_A, lc_data_o.test_exit_token == + PartInvDefault[TestExitTokenOffset*8+:TestExitTokenSize*8]) + `OTP_FATAL_ERR_ASSERT(LcDataRmaToken_A, lc_data_o.rma_token == + PartInvDefault[RmaTokenOffset*8+:RmaTokenSize*8]) + + `OTP_FATAL_ERR_ASSERT(KeymgrKeyData_A, keymgr_key_o.creator_root_key_share0 == + PartInvDefault[CreatorRootKeyShare0Offset*8+:CreatorRootKeyShare0Size*8] && + keymgr_key_o.creator_root_key_share1 == + PartInvDefault[CreatorRootKeyShare1Offset*8+:CreatorRootKeyShare1Size*8]) + + `OTP_FATAL_ERR_ASSERT(HwCfgOValid_A, otp_broadcast_o.valid == lc_ctrl_pkg::Off) + `OTP_FATAL_ERR_ASSERT(HwCfg0OData_A, otp_broadcast_o.hw_cfg0_data == + PartInvDefault[HwCfg0Offset*8+:HwCfg0Size*8]) + `OTP_FATAL_ERR_ASSERT(HwCfg1OData_A, otp_broadcast_o.hw_cfg1_data == + PartInvDefault[HwCfg1Offset*8+:HwCfg1Size*8]) + + `OTP_FATAL_ERR_ASSERT(LcProgAck_A, lc_prog_ack == 0) + `OTP_FATAL_ERR_ASSERT(FlashAcks_A, flash_acks == 0) + `OTP_FATAL_ERR_ASSERT(SramAcks_A, sram_acks == 0) + `OTP_FATAL_ERR_ASSERT(OtbnAck_A, otbn_ack == 0) + + `undef OTP_ASSERT_WO_LC_ESC + `undef OTP_FATAL_ERR_ASSERT + `undef ECC_REG_PATH + `undef BUF_PART_OTP_CMD_PATH + `undef LC_PART_OTP_CMD_PATH + `undef PRIM_GENERIC_OTP_PATH + `undef PRIM_GENERIC_OTP_CMD_I_PATH + `undef FORCE_OTP_PART_LOCK_WITH_RAND_NON_MUBI_VAL +endinterface diff --git a/src/fuse_ctrl/dv/env/otp_ctrl_scoreboard.sv b/src/fuse_ctrl/dv/env/otp_ctrl_scoreboard.sv new file mode 100755 index 0000000..828a7e0 --- /dev/null +++ b/src/fuse_ctrl/dv/env/otp_ctrl_scoreboard.sv @@ -0,0 +1,1696 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// DO NOT EDIT THIS FILE DIRECTLY. +// It has been generated with ./util/design/gen-otp-mmap.py + +class otp_ctrl_scoreboard #(type CFG_T = otp_ctrl_env_cfg) + extends cip_base_scoreboard #( + .CFG_T(CFG_T), + .RAL_T(otp_ctrl_core_reg_block), + .COV_T(otp_ctrl_env_cov) + ); + `uvm_component_param_utils(otp_ctrl_scoreboard #(CFG_T)) + + // local variables + bit [TL_DW-1:0] otp_a [OTP_ARRAY_SIZE]; + + // lc_state and lc_cnt that stored in OTP + bit [LC_PROG_DATA_SIZE-1:0] otp_lc_data; + bit [EDN_BUS_WIDTH-1:0] edn_data_q[$]; + + // This flag is used when reset is issued during otp dai write access. + bit dai_wr_ip; + int dai_digest_ip = LifeCycleIdx; // Default to LC as it does not have digest. + bit ignore_digest_chk = 0; + + // This bit is used for DAI interface to mark if the read access is valid. + bit dai_read_valid; + + // This captures the regwen state as configured by the SW side (i.e. without HW modulation + // with the idle signal overlaid). + bit direct_access_regwen_state = 1; + + // ICEBOX(#17798): currently scb will skip checking the readout value if the ECC error is + // uncorrectable. Because if the error is uncorrectable, current scb does not track all the + // backdoor injected values. + // This issue proposes to track the otp_memory_array in mem_bkdr_if and once backdoor inject any + // value, mem_bkdr_if will update its otp_memory_array. + bit check_dai_rd_data = 1; + + // Status related variables + bit under_chk, under_dai_access; + bit [TL_DW-1:0] exp_status, status_mask; + + otp_alert_e exp_alert = OtpNoAlert; + + // TLM agent fifos + uvm_tlm_analysis_fifo #(push_pull_item#(.DeviceDataWidth(SRAM_DATA_SIZE))) + sram_fifos[NumSramKeyReqSlots]; + uvm_tlm_analysis_fifo #(push_pull_item#(.DeviceDataWidth(OTBN_DATA_SIZE))) otbn_fifo; + uvm_tlm_analysis_fifo #(push_pull_item#(.DeviceDataWidth(FLASH_DATA_SIZE))) flash_addr_fifo; + uvm_tlm_analysis_fifo #(push_pull_item#(.DeviceDataWidth(FLASH_DATA_SIZE))) flash_data_fifo; + uvm_tlm_analysis_fifo #(push_pull_item#(.DeviceDataWidth(1), .HostDataWidth(LC_PROG_DATA_SIZE))) + lc_prog_fifo; + + // local queues to hold incoming packets pending comparison + + `uvm_component_new + + function void build_phase(uvm_phase phase); + super.build_phase(phase); + for (int i = 0; i < NumSramKeyReqSlots; i++) begin + sram_fifos[i] = new($sformatf("sram_fifos[%0d]", i), this); + end + otbn_fifo = new("otbn_fifo", this); + flash_addr_fifo = new("flash_addr_fifo", this); + flash_data_fifo = new("flash_data_fifo", this); + lc_prog_fifo = new("lc_prog_fifo", this); + endfunction + + function void connect_phase(uvm_phase phase); + super.connect_phase(phase); + endfunction + + task run_phase(uvm_phase phase); + super.run_phase(phase); + fork + process_wipe_mem(); + process_otp_power_up(); + process_lc_esc(); + process_lc_prog_req(); + process_edn_req(); + check_otbn_rsp(); + check_flash_rsps(); + check_sram_rsps(); + recover_lc_prog_req(); + join_none + endtask + + // Once sequence uses backdoor method to clear memory, this task resets internal otp_a and + // resets `cfg.backdoor_clear_mem` to 0. + virtual task process_wipe_mem(); + forever begin + @(posedge cfg.backdoor_clear_mem) begin + bit [SCRAMBLE_DATA_SIZE-1:0] data; + otp_a = '{default:0}; + otp_lc_data = '{default:0}; + // secret partitions have been scrambled before writing to OTP. + // here calculate the pre-srambled raw data when clearing internal OTP to all 0s. + data = descramble_data(0, Secret0Idx); + for (int i = Secret0Offset / TL_SIZE; + i <= Secret0DigestOffset / TL_SIZE - 1; + i++) begin + otp_a[i] = ((i - Secret0Offset / TL_SIZE) % 2) ? + data[SCRAMBLE_DATA_SIZE-1:TL_DW] : data[TL_DW-1:0]; + end + // secret partitions have been scrambled before writing to OTP. + // here calculate the pre-srambled raw data when clearing internal OTP to all 0s. + data = descramble_data(0, Secret1Idx); + for (int i = Secret1Offset / TL_SIZE; + i <= Secret1DigestOffset / TL_SIZE - 1; + i++) begin + otp_a[i] = ((i - Secret1Offset / TL_SIZE) % 2) ? + data[SCRAMBLE_DATA_SIZE-1:TL_DW] : data[TL_DW-1:0]; + end + // secret partitions have been scrambled before writing to OTP. + // here calculate the pre-srambled raw data when clearing internal OTP to all 0s. + data = descramble_data(0, Secret2Idx); + for (int i = Secret2Offset / TL_SIZE; + i <= Secret2DigestOffset / TL_SIZE - 1; + i++) begin + otp_a[i] = ((i - Secret2Offset / TL_SIZE) % 2) ? + data[SCRAMBLE_DATA_SIZE-1:TL_DW] : data[TL_DW-1:0]; + end + `uvm_info(`gfn, "clear internal memory and digest", UVM_HIGH) + cfg.backdoor_clear_mem = 0; + dai_wr_ip = 0; + dai_digest_ip = LifeCycleIdx; + end + end + endtask + + // This task process the following logic in during otp_power_up: + // 1. After reset deasserted, otp access is locked until pwr_otp_done_o is set + // 2. After reset deasserted, if power otp_init request is on, and if testbench uses backdoor to + // clear OTP memory to all zeros, clear all digests and re-calculate secret partitions + virtual task process_otp_power_up(); + forever begin + wait (cfg.en_scb); + @(posedge cfg.otp_ctrl_vif.pwr_otp_done_o || cfg.under_reset || + cfg.otp_ctrl_vif.alert_reqs) begin + if (!cfg.under_reset && !cfg.otp_ctrl_vif.alert_reqs && cfg.en_scb) begin + otp_ctrl_part_pkg::otp_hw_cfg0_data_t exp_hw_cfg0_data; + otp_ctrl_part_pkg::otp_hw_cfg1_data_t exp_hw_cfg1_data; + otp_ctrl_pkg::otp_keymgr_key_t exp_keymgr_data; + otp_ctrl_pkg::otp_lc_data_t exp_lc_data; + bit [otp_ctrl_pkg::KeyMgrKeyWidth-1:0] exp_keymgr_key0, exp_keymgr_key1; + + if (PartInfo[dai_digest_ip].sw_digest || PartInfo[dai_digest_ip].hw_digest) begin + bit [TL_DW-1:0] otp_addr = PART_OTP_DIGEST_ADDRS[dai_digest_ip]; + otp_a[otp_addr] = cfg.mem_bkdr_util_h.read32(otp_addr << 2); + otp_a[otp_addr+1] = cfg.mem_bkdr_util_h.read32((otp_addr << 2) + 4); + dai_digest_ip = LifeCycleIdx; + end + predict_digest_csrs(); + + if (cfg.otp_ctrl_vif.under_error_states() == 0) begin + // Dai access is unlocked because the power init is done + void'(ral.direct_access_regwen.predict(direct_access_regwen_state)); + + // Dai idle is set because the otp init is done + exp_status[OtpDaiIdleIdx] = 1; + end + + // Hwcfg_o gets data from OTP HW cfg partition + exp_hw_cfg0_data = cfg.otp_ctrl_vif.under_error_states() ? + otp_ctrl_part_pkg::PartInvDefault[HwCfg0Offset*8 +: HwCfg0Size*8] : + otp_hw_cfg0_data_t'({<<32 {otp_a[HwCfg0Offset/4 +: HwCfg0Size/4]}}); + `DV_CHECK_EQ(cfg.otp_ctrl_vif.otp_broadcast_o.valid, lc_ctrl_pkg::On) + `DV_CHECK_EQ(cfg.otp_ctrl_vif.otp_broadcast_o.hw_cfg0_data, exp_hw_cfg0_data) + + // Hwcfg_o gets data from OTP HW cfg partition + exp_hw_cfg1_data = cfg.otp_ctrl_vif.under_error_states() ? + otp_ctrl_part_pkg::PartInvDefault[HwCfg1Offset*8 +: HwCfg1Size*8] : + otp_hw_cfg1_data_t'({<<32 {otp_a[HwCfg1Offset/4 +: HwCfg1Size/4]}}); + `DV_CHECK_EQ(cfg.otp_ctrl_vif.otp_broadcast_o.valid, lc_ctrl_pkg::On) + `DV_CHECK_EQ(cfg.otp_ctrl_vif.otp_broadcast_o.hw_cfg1_data, exp_hw_cfg1_data) + + if (!cfg.otp_ctrl_vif.under_error_states()) begin + // ---------------------- Check lc_data_o output ----------------------------------- + // Because initialization was succesful, the valid should be set and error should be + // reset. + exp_lc_data.valid = 1; + exp_lc_data.error = 0; + + // Secrets and tokens valid signals are depend on whether secret partitions are + // locked. + exp_lc_data.secrets_valid = get_otp_digest_val(Secret2Idx) ? On : Off; + exp_lc_data.test_tokens_valid = get_otp_digest_val(Secret0Idx) ? On : Off; + exp_lc_data.rma_token_valid = get_otp_digest_val(Secret2Idx) ? On : Off; + + // LC output is depend on LC partitions value. + exp_lc_data.count = otp_lc_data[0 +: LcCountWidth]; + exp_lc_data.state = otp_lc_data[LcCountWidth +: LcStateWidth]; + + // Token values are depend on secret partitions value. + exp_lc_data.test_unlock_token = + {<<32 {otp_a[TestUnlockTokenOffset/4 +: TestUnlockTokenSize/4]}}; + exp_lc_data.test_exit_token = + {<<32 {otp_a[TestExitTokenOffset/4 +: TestExitTokenSize/4]}}; + exp_lc_data.rma_token = {<<32 {otp_a[RmaTokenOffset/4 +: RmaTokenSize/4]}}; + + // Check otp_lc_data_t struct by item is easier to debug. + `DV_CHECK_EQ(cfg.otp_ctrl_vif.lc_data_o.valid, exp_lc_data.valid) + `DV_CHECK_EQ(cfg.otp_ctrl_vif.lc_data_o.error, exp_lc_data.error) + `DV_CHECK_EQ(cfg.otp_ctrl_vif.lc_data_o.state, exp_lc_data.state) + `DV_CHECK_EQ(cfg.otp_ctrl_vif.lc_data_o.count, exp_lc_data.count) + `DV_CHECK_EQ(cfg.otp_ctrl_vif.lc_data_o.secrets_valid, exp_lc_data.secrets_valid) + `DV_CHECK_EQ(cfg.otp_ctrl_vif.lc_data_o.test_tokens_valid, + exp_lc_data.test_tokens_valid) + `DV_CHECK_EQ(cfg.otp_ctrl_vif.lc_data_o.test_unlock_token, + exp_lc_data.test_unlock_token) + `DV_CHECK_EQ(cfg.otp_ctrl_vif.lc_data_o.test_exit_token, exp_lc_data.test_exit_token) + `DV_CHECK_EQ(cfg.otp_ctrl_vif.lc_data_o.rma_token_valid, exp_lc_data.rma_token_valid) + `DV_CHECK_EQ(cfg.otp_ctrl_vif.lc_data_o.rma_token, exp_lc_data.rma_token) + + // Check otp_lc_data_t all together in case there is any missed item. + `DV_CHECK_EQ(cfg.otp_ctrl_vif.lc_data_o, exp_lc_data) + + // ---------------------- Check keymgr_key_o output --------------------------------- + // Otp_keymgr outputs creator and owner keys from secret partitions. + // Depends on lc_seed_hw_rd_en_i, it will output the real keys or a constant + exp_keymgr_data = '0; + exp_keymgr_data.creator_root_key_share0_valid = get_otp_digest_val(Secret2Idx) != 0; + if (cfg.otp_ctrl_vif.lc_seed_hw_rd_en_i == lc_ctrl_pkg::On) begin + exp_keymgr_data.creator_root_key_share0 = + {<<32 {otp_a[CreatorRootKeyShare0Offset/4 +: CreatorRootKeyShare0Size/4]}}; + end else begin + exp_keymgr_data.creator_root_key_share0 = + PartInvDefault[CreatorRootKeyShare0Offset*8 +: CreatorRootKeyShare0Size*8]; + end + // Check otp_keymgr_key_t struct by item is easier to debug. + `DV_CHECK_EQ(cfg.otp_ctrl_vif.keymgr_key_o.creator_root_key_share0_valid, + exp_keymgr_data.creator_root_key_share0_valid) + exp_keymgr_data.creator_root_key_share1_valid = get_otp_digest_val(Secret2Idx) != 0; + if (cfg.otp_ctrl_vif.lc_seed_hw_rd_en_i == lc_ctrl_pkg::On) begin + exp_keymgr_data.creator_root_key_share1 = + {<<32 {otp_a[CreatorRootKeyShare1Offset/4 +: CreatorRootKeyShare1Size/4]}}; + end else begin + exp_keymgr_data.creator_root_key_share1 = + PartInvDefault[CreatorRootKeyShare1Offset*8 +: CreatorRootKeyShare1Size*8]; + end + // Check otp_keymgr_key_t struct by item is easier to debug. + `DV_CHECK_EQ(cfg.otp_ctrl_vif.keymgr_key_o.creator_root_key_share1_valid, + exp_keymgr_data.creator_root_key_share1_valid) + + // Check otp_keymgr_key_t struct all together in case there is any missed item. + `DV_CHECK_EQ(cfg.otp_ctrl_vif.keymgr_key_o, exp_keymgr_data) + + if (cfg.en_cov) begin + cov.keymgr_o_cg.sample(cfg.otp_ctrl_vif.lc_seed_hw_rd_en_i == lc_ctrl_pkg::On, + exp_keymgr_data.creator_root_key_share0_valid); + end + end + end else if (cfg.otp_ctrl_vif.alert_reqs) begin + // Ignore digest CSR check when otp_ctrl initialization is interrupted by fatal errors. + // SCB cannot predict how many partitions already finished initialization and updated + // the digest value to CSRs. + ignore_digest_chk = 1; + end + if (cfg.en_cov) begin + bit [NumPart-2:0] parts_locked; + foreach (parts_locked[i]) parts_locked[i] = (get_otp_digest_val(i) != 0); + cov.power_on_cg.sample(cfg.otp_ctrl_vif.lc_esc_on, parts_locked); + end + end + end + endtask + + // This task monitors internal escalation triggered by two methods: + // 1. Externally lc_escalation_en is set to lc_ctrl_pkg::On. + // 2. Internal fatal alert triggered and all partitions are driven to error states. + virtual task process_lc_esc(); + forever begin + wait(cfg.otp_ctrl_vif.alert_reqs == 1 && cfg.en_scb); + + if (cfg.otp_ctrl_vif.lc_esc_on == 0) `DV_CHECK_NE(exp_alert, OtpNoAlert) + + if (exp_alert != OtpCheckAlert) set_exp_alert("fatal_check_error", 1, 5); + + // If the lc_escalation is triggered by internal fatal alert, wait 2 negedge until status is + // updated internally + if (cfg.otp_ctrl_vif.lc_esc_on == 0) begin + cfg.clk_rst_vif.wait_n_clks(2); + exp_status[OtpCheckPendingIdx] = 0; + exp_status[OtpDaiIdleIdx] = 0; + end else begin + exp_status = '0; + // Only lc_esc_on will set these bits to 1. + exp_status[OtpDerivKeyFsmErrIdx:OtpLfsrFsmErrIdx] = '1; + end + + // Update status bits. + foreach (FATAL_EXP_STATUS[i]) begin + if (FATAL_EXP_STATUS[i]) begin + predict_err(.status_err_idx(otp_status_e'(i)), .err_code(OtpFsmStateError), + .update_esc_err(1)); + end + end + + // Update digest values and direct_access_regwen. + predict_rdata(1, 0, 0); + void'(ral.direct_access_regwen.predict(.value(0), .kind(UVM_PREDICT_READ))); + + // DAI access is locked until reset, so no need to backdoor read otp write value until reset. + + wait(cfg.otp_ctrl_vif.alert_reqs == 0); + end + endtask + + // This task monitors if lc_program req is interrupted by reset. + // If it happens, scb cannot predict how many bits have been written to OTP_CTRL. + // So here we will backdoor read back OTP lc partitions bits. + virtual task recover_lc_prog_req(); + forever begin + wait(cfg.otp_ctrl_vif.lc_prog_req == 1); + wait(cfg.otp_ctrl_vif.lc_prog_req == 0); + // Wait one 1ps to avoid race condition. + #1ps; + if (cfg.otp_ctrl_vif.rst_ni == 0) begin + for (int i = 0; i < LC_PROG_DATA_SIZE/32; i++) begin + otp_lc_data[i*32+:32] = cfg.mem_bkdr_util_h.read32(LifeCycleOffset + i * 4); + end + end + end + endtask + + virtual task process_lc_prog_req(); + forever begin + push_pull_item#(.DeviceDataWidth(1), .HostDataWidth(LC_PROG_DATA_SIZE)) rcv_item; + bit exp_err_bit; + bit [15:0] rcv_words [LC_PROG_DATA_SIZE/16]; + + lc_prog_fifo.get(rcv_item); + + // LCI is updated by OTP word. + rcv_words = {<< 16{rcv_item.h_data}}; + foreach (rcv_words[i]) begin + bit [15:0] curr_word = otp_lc_data[i*16 +: 16]; + if ((curr_word & rcv_words[i]) == curr_word) otp_lc_data[i*16 +: 16] = rcv_words[i]; + else exp_err_bit = 1; + end + + if (exp_err_bit) predict_err(OtpLciErrIdx, OtpMacroWriteBlankError); + else predict_no_err(OtpLciErrIdx); + + // LC program request data is valid means no OTP macro error. + `DV_CHECK_EQ(rcv_item.d_data, exp_err_bit) + + if (cfg.en_cov) cov.lc_prog_cg.sample(exp_err_bit); + end + endtask + + virtual task process_edn_req(); + forever begin + push_pull_item#(.DeviceDataWidth(EDN_DATA_WIDTH)) edn_item; + edn_fifos[0].get(edn_item); + edn_data_q.push_back(edn_item.d_data[EDN_BUS_WIDTH-1:0]); + end + endtask + + virtual task check_otbn_rsp(); + forever begin + push_pull_item#(.DeviceDataWidth(OTBN_DATA_SIZE)) rcv_item; + bit [SCRAMBLE_KEY_SIZE-1:0] edn_key2, edn_key1; + bit [SCRAMBLE_KEY_SIZE-1:0] sram_key; + bit [SCRAMBLE_DATA_SIZE-1:0] exp_key_lower, exp_key_higher; + bit [OtbnKeyWidth-1:0] key, exp_key; + bit [OtbnNonceWidth-1:0] nonce, exp_nonce; + bit seed_valid; + bit part_locked; + + otbn_fifo.get(rcv_item); + seed_valid = rcv_item.d_data[0]; + nonce = rcv_item.d_data[1+:OtbnNonceWidth]; + key = rcv_item.d_data[OtbnNonceWidth+1+:OtbnKeyWidth]; + part_locked = {`gmv(ral.secret1_digest[0]), `gmv(ral.secret1_digest[1])} != '0; + + // seed is valid as long as secret1 is locked + `DV_CHECK_EQ(seed_valid, part_locked, "otbn seed_valid mismatch") + + // If edn_data_q matches the OTBN requested size, check OTBN outputs + if (edn_data_q.size() == NUM_OTBN_EDN_REQ) begin + {exp_nonce, edn_key2, edn_key1} = {<<32{edn_data_q}}; + + // check nonce value + `DV_CHECK_EQ(nonce, exp_nonce, "otbn nonce mismatch") + + // calculate key + sram_key = get_key_from_otp(part_locked, SramDataKeySeedOffset / 4); + exp_key_lower = present_encode_with_final_const( + .data(RndCnstDigestIV[SramDataKey]), + .key(sram_key), + .final_const(RndCnstDigestConst[SramDataKey]), + .second_key(edn_key1), + .num_round(2)); + + exp_key_higher = present_encode_with_final_const( + .data(RndCnstDigestIV[SramDataKey]), + .key(sram_key), + .final_const(RndCnstDigestConst[SramDataKey]), + .second_key(edn_key2), + .num_round(2)); + exp_key = {exp_key_higher, exp_key_lower}; + `DV_CHECK_EQ(key, exp_key, "otbn key mismatch") + + if (cfg.en_cov) cov.otbn_req_cg.sample(part_locked); + + // If during OTBN key request, the LFSR timer expired and trigger an EDN request to acquire + // two EDN keys, then ignore the OTBN output checking, because scb did not know which EDN + // keys are used for LFSR. + // Thus any edn_data_q size equal to (16+2*N) is exempted from checking. + end else if ((edn_data_q.size() - NUM_OTBN_EDN_REQ) % 2 != 0) begin + `uvm_error(`gfn, $sformatf("Unexpected edn_data_q size (%0d) during OTBN request", + edn_data_q.size())) + end + edn_data_q.delete(); + end + endtask + + virtual task check_flash_rsps(); + for (int i = FlashDataKey; i <= FlashAddrKey; i++) begin + automatic digest_sel_e sel_flash = digest_sel_e'(i); + fork + forever begin + push_pull_item#(.DeviceDataWidth(FLASH_DATA_SIZE)) rcv_item; + bit [SCRAMBLE_KEY_SIZE-1:0] flash_key; + bit [SCRAMBLE_DATA_SIZE-1:0] exp_key_lower, exp_key_higher; + bit [FlashKeyWidth-1:0] key, exp_key; + bit seed_valid, part_locked; + int flash_key_index; + + if (sel_flash == FlashAddrKey) begin + flash_addr_fifo.get(rcv_item); + flash_key_index = FlashAddrKeySeedOffset / 4; + end else begin + flash_data_fifo.get(rcv_item); + flash_key_index = FlashDataKeySeedOffset / 4; + end + seed_valid = rcv_item.d_data[0]; + key = rcv_item.d_data[1+:FlashKeyWidth]; + part_locked = {`gmv(ral.secret1_digest[0]), `gmv(ral.secret1_digest[1])} != '0; + `DV_CHECK_EQ(seed_valid, part_locked, + $sformatf("flash %0s seed_valid mismatch", sel_flash.name())) + + // calculate key + flash_key = get_key_from_otp(part_locked, flash_key_index); + exp_key_lower = present_encode_with_final_const( + .data(RndCnstDigestIV[sel_flash]), + .key(flash_key), + .final_const(RndCnstDigestConst[sel_flash])); + + flash_key = get_key_from_otp(part_locked, flash_key_index + 4); + exp_key_higher = present_encode_with_final_const( + .data(RndCnstDigestIV[sel_flash]), + .key(flash_key), + .final_const(RndCnstDigestConst[sel_flash])); + exp_key = {exp_key_higher, exp_key_lower}; + `DV_CHECK_EQ(key, exp_key, $sformatf("flash %s key mismatch", sel_flash.name())) + + if (cfg.en_cov) cov.flash_req_cg.sample(sel_flash, part_locked); + end + join_none; + end + endtask + + virtual task check_sram_rsps(); + for (int i = 0; i < NumSramKeyReqSlots; i++) begin + automatic int index = i; + fork + forever begin + push_pull_item#(.DeviceDataWidth(SRAM_DATA_SIZE)) rcv_item; + sram_key_t key, exp_key; + sram_nonce_t nonce, exp_nonce; + bit seed_valid, part_locked; + bit [SCRAMBLE_KEY_SIZE-1:0] edn_key2, edn_key1; + bit [SCRAMBLE_KEY_SIZE-1:0] sram_key; // key used as input to present algo + bit [SCRAMBLE_DATA_SIZE-1:0] exp_key_lower, exp_key_higher; + + sram_fifos[index].get(rcv_item); + seed_valid = rcv_item.d_data[0]; + nonce = rcv_item.d_data[1+:SramNonceWidth]; + key = rcv_item.d_data[SramNonceWidth+1+:SramKeyWidth]; + part_locked = {`gmv(ral.secret1_digest[0]), `gmv(ral.secret1_digest[1])} != '0; + + // seed is valid as long as secret1 is locked + `DV_CHECK_EQ(seed_valid, part_locked, $sformatf("sram_%0d seed_valid mismatch", index)) + + // If edn_data_q matches the OTBN requested size, check OTBN outputs + if (edn_data_q.size() == NUM_SRAM_EDN_REQ) begin + {exp_nonce, edn_key2, edn_key1} = {<<32{edn_data_q}}; + + // check nonce value + `DV_CHECK_EQ(nonce, exp_nonce, $sformatf("sram_%0d nonce mismatch", index)) + + // calculate key + sram_key = get_key_from_otp(part_locked, SramDataKeySeedOffset / 4); + exp_key_lower = present_encode_with_final_const( + .data(RndCnstDigestIV[SramDataKey]), + .key(sram_key), + .final_const(RndCnstDigestConst[SramDataKey]), + .second_key(edn_key1), + .num_round(2)); + + exp_key_higher = present_encode_with_final_const( + .data(RndCnstDigestIV[SramDataKey]), + .key(sram_key), + .final_const(RndCnstDigestConst[SramDataKey]), + .second_key(edn_key2), + .num_round(2)); + exp_key = {exp_key_higher, exp_key_lower}; + `DV_CHECK_EQ(key, exp_key, $sformatf("sram_%0d key mismatch", index)) + if (cfg.en_cov) cov.sram_req_cg.sample(index, part_locked); + + end else if ((edn_data_q.size() - NUM_SRAM_EDN_REQ) % 2 != 0) begin + `uvm_error(`gfn, $sformatf("Unexpected edn_data_q size (%0d) during SRAM request", + edn_data_q.size())) + end + edn_data_q.delete(); + end + join_none + end + endtask + + virtual task process_tl_access(tl_seq_item item, tl_channels_e channel, string ral_name); + bit write = item.is_write(); + uvm_reg_addr_t csr_addr = cfg.ral_models[ral_name].get_word_aligned_addr(item.a_addr); + bit [TL_AW-1:0] addr_mask = ral.get_addr_mask(); + + bit addr_phase_read = (!write && channel == AddrChannel); + bit addr_phase_write = (write && channel == AddrChannel); + bit data_phase_read = (!write && channel == DataChannel); + bit data_phase_write = (write && channel == DataChannel); + + if (ral_name != "otp_ctrl_prim_reg_block") begin + process_core_tl_access(item, csr_addr, ral_name, addr_mask, + addr_phase_read, addr_phase_write, data_phase_read, data_phase_write); + end else begin + process_prim_tl_access(item, csr_addr, ral_name, addr_phase_write, data_phase_read); + end + endtask + + virtual function void process_prim_tl_access(tl_seq_item item, uvm_reg_addr_t csr_addr, + string ral_name, bit addr_phase_write, bit data_phase_read); + + uvm_reg csr; + dv_base_reg dv_reg; + csr = cfg.ral_models[ral_name].default_map.get_reg_by_offset(csr_addr); + `DV_CHECK_NE_FATAL(csr, null) + `downcast(dv_reg, csr) + + if (addr_phase_write) begin + void'(csr.predict(.value(item.a_data), .kind(UVM_PREDICT_WRITE), .be(item.a_mask))); + end else if (data_phase_read) begin + `DV_CHECK_EQ((csr.get_mirrored_value() | status_mask), (item.d_data | status_mask), + $sformatf("reg name: status, compare_mask %0h", status_mask)) + end + endfunction + + virtual function void process_core_tl_access(tl_seq_item item, uvm_reg_addr_t csr_addr, + string ral_name, bit [TL_AW-1:0] addr_mask, bit addr_phase_read, bit addr_phase_write, + bit data_phase_read, bit data_phase_write); + + bit do_read_check = 1; + uvm_reg csr; + dv_base_reg dv_reg; + string csr_name; + + `uvm_info(`gfn, $sformatf("sw state %d, reg state %d", direct_access_regwen_state, + `gmv(ral.direct_access_regwen)), UVM_LOW); + + // if access was to a valid csr, get the csr handle + if (csr_addr inside {cfg.ral_models[ral_name].csr_addrs}) begin + csr = cfg.ral_models[ral_name].default_map.get_reg_by_offset(csr_addr); + `DV_CHECK_NE_FATAL(csr, null) + `downcast(dv_reg, csr) + // SW CFG window + end else if ((csr_addr & addr_mask) inside + {[SW_WINDOW_BASE_ADDR : SW_WINDOW_BASE_ADDR + SW_WINDOW_SIZE]}) begin + if (data_phase_read) begin + bit [TL_AW-1:0] dai_addr = (csr_addr & addr_mask - SW_WINDOW_BASE_ADDR); + bit [TL_AW-1:0] otp_addr = dai_addr >> 2; + int part_idx = get_part_index(dai_addr); + bit [TL_DW-1:0] read_out; + int ecc_err = OtpNoEccErr; + + // We can't get an ECC error if the partition does not have integrity. + if (part_has_integrity(part_idx)) begin + ecc_err = read_a_word_with_ecc(dai_addr, read_out); + end else begin + ecc_err = read_a_word_with_ecc_raw(dai_addr, read_out); + end + + if (part_has_digest(part_idx) && cfg.en_cov) begin + cov.unbuf_access_lock_cg_wrap[part_idx].sample(.read_lock(0), + .write_lock(get_digest_reg_val(part_idx) != 0), .is_write(0)); + end + + // Any alert that indicates the OTP block is in the final error state should not enter the + // logic here, but gated at `is_tl_mem_access_allowed` function. + `DV_CHECK_EQ(cfg.otp_ctrl_vif.alert_reqs, 0) + + // ECC uncorrectable errors are gated by `is_tl_mem_access_allowed` function. + if (ecc_err != OtpNoEccErr && part_has_integrity(part_idx)) begin + + predict_err(otp_status_e'(part_idx), OtpMacroEccCorrError); + if (ecc_err == OtpEccCorrErr) begin + `DV_CHECK_EQ(item.d_data, otp_a[otp_addr], + $sformatf("mem read mismatch at TLUL addr %0h, csr_addr %0h", + csr_addr, dai_addr)) + end else begin + // Only check the first 16 bits because if ECC readout detects uncorrectable error, it + // won't continue read the remaining 16 bits. + `DV_CHECK_EQ(item.d_data & 16'hffff, read_out & 16'hffff, + $sformatf("mem read mismatch at TLUL addr %0h, csr_addr %0h", + csr_addr, dai_addr)) + end + // If there is an injected error, but the partition cannot detect it, we have to compare + // to the value read via the backdoor instead of otp_a[otp_addr] since otherwise the + // perturbed value does not get modelled correctly. + end else if (ecc_err != OtpNoEccErr && !part_has_integrity(part_idx)) begin + `DV_CHECK_EQ(item.d_data, read_out, + $sformatf("mem read mismatch at TLUL addr %0h, csr_addr %0h", + csr_addr, dai_addr)) + predict_no_err(otp_status_e'(part_idx)); + end else if (ecc_err == OtpNoEccErr) begin + `DV_CHECK_EQ(item.d_data, otp_a[otp_addr], + $sformatf("mem read mismatch at TLUL addr %0h, csr_addr %0h", + csr_addr, dai_addr)) + predict_no_err(otp_status_e'(part_idx)); + end + end + return; + end else begin + `uvm_fatal(`gfn, $sformatf("Access unexpected addr 0x%0h", csr_addr)) + end + + csr_name = csr.get_name(); + + if (addr_phase_write) begin + if (cfg.en_cov && cfg.otp_ctrl_vif.alert_reqs && csr_name == "direct_access_cmd") begin + cov.req_dai_access_after_alert_cg.sample(item.a_data); + end + + // Skip predict if the register is locked by `direct_access_regwen`. + // An exception is the direct_access_regwen which may always be written. + if (ral.direct_access_regwen.locks_reg_or_fld(dv_reg) && + `gmv(ral.direct_access_regwen) == 0 && + csr_name != "direct_access_regwen") return; + + void'(csr.predict(.value(item.a_data), .kind(UVM_PREDICT_WRITE), .be(item.a_mask))); + end + + // process the csr req + // for write, update local variable and fifo at address phase + // for read, update predication at address phase and compare at data phase + case (csr_name) + // add individual case item for each csr + "intr_state": begin + if (data_phase_read) begin + // Disable intr_state checking when lc_program is in progress, because scb cannot + // accurately predict when program_error will be triggered. + // We will check the intr_state after lc_program request is done, and the error bit will + // be checked in the `process_lc_prog_req` task. + if (cfg.otp_ctrl_vif.lc_prog_no_sta_check) do_read_check = 0; + if (do_read_check) begin + bit [TL_DW-1:0] intr_en = `gmv(ral.intr_enable); + bit [NumOtpCtrlIntr-1:0] intr_exp = `gmv(ral.intr_state); + + foreach (intr_exp[i]) begin + otp_intr_e intr = otp_intr_e'(i); + `DV_CHECK_CASE_EQ(cfg.intr_vif.pins[i], (intr_en[i] & intr_exp[i]), + $sformatf("Interrupt_pin: %0s", intr.name)); + if (cfg.en_cov) begin + cov.intr_cg.sample(i, intr_en[i], item.d_data[i]); + cov.intr_pins_cg.sample(i, cfg.intr_vif.pins[i]); + end + end + end + end + end + "intr_test": begin + if (addr_phase_write) begin + bit [TL_DW-1:0] intr_en = `gmv(ral.intr_enable); + bit [NumOtpCtrlIntr-1:0] intr_exp = `gmv(ral.intr_state) | item.a_data; + + void'(ral.intr_state.predict(.value(intr_exp))); + if (cfg.en_cov) begin + foreach (intr_exp[i]) begin + cov.intr_test_cg.sample(i, item.a_data[i], intr_en[i], intr_exp[i]); + end + end + end + end + "direct_access_cmd": begin + if (addr_phase_write && !cfg.otp_ctrl_vif.under_error_states()) begin + // here only normalize to 2 lsb, if is secret, will be reduced further + bit [TL_AW-1:0] dai_addr = normalize_dai_addr(`gmv(ral.direct_access_address)); + int part_idx = get_part_index(dai_addr); + bit sw_read_lock = 0; + void'(ral.direct_access_regwen.predict(0)); + under_dai_access = 1; + + // Check if it is sw partition read lock - this can be used in `DaiRead` branch and also + // coverage collection. + if (part_idx == VendorTestIdx) begin + sw_read_lock = `gmv(ral.vendor_test_read_lock) == 0; + end else if (part_idx == CreatorSwCfgIdx) begin + sw_read_lock = `gmv(ral.creator_sw_cfg_read_lock) == 0; + end else if (part_idx == OwnerSwCfgIdx) begin + sw_read_lock = `gmv(ral.owner_sw_cfg_read_lock) == 0; + end else if (part_idx == RotCreatorAuthCodesignIdx) begin + sw_read_lock = `gmv(ral.rot_creator_auth_codesign_read_lock) == 0; + end else if (part_idx == RotCreatorAuthStateIdx) begin + sw_read_lock = `gmv(ral.rot_creator_auth_state_read_lock) == 0; + end + + // LC partition cannot be access via DAI + if (part_idx == LifeCycleIdx) begin + predict_err(OtpDaiErrIdx, OtpAccessError); + if (item.a_data == DaiRead) predict_rdata(is_secret(dai_addr), 0, 0); + end else begin + // Collect coverage. + if (cfg.en_cov) begin + if (part_idx == Secret2Idx) begin + cov.dai_access_secret2_cg.sample( + !(cfg.otp_ctrl_vif.lc_creator_seed_sw_rw_en_i != lc_ctrl_pkg::On), + dai_cmd_e'(item.a_data)); + end else if (is_sw_part_idx(part_idx) && part_has_digest(part_idx) && + item.a_data inside {DaiRead, DaiWrite}) begin + cov.unbuf_access_lock_cg_wrap[part_idx].sample(.read_lock(sw_read_lock), + .write_lock(get_digest_reg_val(part_idx) != 0), + .is_write(item.a_data == DaiWrite)); + + end + end + + case (item.a_data) + DaiDigest: cal_digest_val(part_idx); + DaiRead: begin + // Check if it is sw partition read lock + check_dai_rd_data = 1; + + // SW partitions write read_lock_csr can lock read access. + if (sw_read_lock || + // Secret partitions cal digest can also lock read access. + // However, digest is always readable except SW partitions (Issue #5752). + (is_secret(dai_addr) && get_digest_reg_val(part_idx) != 0 && + !is_digest(dai_addr)) || + // If the partition has creator key material and lc_creator_seed_sw_rw is + // disable, then return access error. + (PartInfo[part_idx].iskeymgr_creator && !is_digest(dai_addr) && + cfg.otp_ctrl_vif.lc_creator_seed_sw_rw_en_i != lc_ctrl_pkg::On)) begin + predict_err(OtpDaiErrIdx, OtpAccessError); + predict_rdata(is_secret(dai_addr) || is_digest(dai_addr), 0, 0); + end else if (sw_read_lock || + // Secret partitions cal digest can also lock read access. + // However, digest is always readable except SW partitions (Issue #5752). + (is_secret(dai_addr) && get_digest_reg_val(part_idx) != 0 && + !is_digest(dai_addr)) || + // If the partition has owner key material and lc_owner_seed_sw_rw is disable, + // then return access error. + (PartInfo[part_idx].iskeymgr_owner && !is_digest(dai_addr) && + cfg.otp_ctrl_vif.lc_owner_seed_sw_rw_en_i != lc_ctrl_pkg::On)) begin + predict_err(OtpDaiErrIdx, OtpAccessError); + predict_rdata(is_secret(dai_addr) || is_digest(dai_addr), 0, 0); + + end else begin + bit [TL_DW-1:0] read_out0, read_out1; + bit [TL_AW-1:0] otp_addr = get_scb_otp_addr(); + int ecc_err = 0; + + // Backdoor read to check if there is any ECC error. + if (part_has_integrity(part_idx)) begin + ecc_err = read_a_word_with_ecc(dai_addr, read_out0); + if (is_secret(dai_addr) || is_digest(dai_addr)) begin + ecc_err = max2(read_a_word_with_ecc(dai_addr + 4, read_out1), ecc_err); + end + end else begin + ecc_err = read_a_word_with_ecc_raw(dai_addr, read_out0); + if (is_secret(dai_addr) || is_digest(dai_addr)) begin + ecc_err = max2(read_a_word_with_ecc_raw(dai_addr + 4, read_out1), ecc_err); + end + end + + if (ecc_err == OtpEccCorrErr && part_has_integrity(part_idx)) begin + predict_err(OtpDaiErrIdx, OtpMacroEccCorrError); + backdoor_update_otp_array(dai_addr); + predict_rdata(is_secret(dai_addr) || is_digest(dai_addr), + otp_a[otp_addr], otp_a[otp_addr+1]); + end else if (ecc_err == OtpEccUncorrErr && part_has_integrity(part_idx)) begin + predict_err(OtpDaiErrIdx, OtpMacroEccUncorrError); + // Max wait 20 clock cycles because scb did not know when exactly OTP will + // finish reading and reporting the uncorrectable error. + set_exp_alert("fatal_macro_error", 1, 20); + predict_rdata(1, 0, 0); + // Some partitions do not interpret/report ECC errors. In those cases + // we still need to model the read data correctly if it has been perturbed. + end else if (ecc_err inside {OtpEccCorrErr, OtpEccUncorrErr} && + !part_has_integrity(part_idx)) begin + predict_no_err(OtpDaiErrIdx); + predict_rdata(is_secret(dai_addr) || is_digest(dai_addr), + read_out0, read_out1); + end else begin + predict_no_err(OtpDaiErrIdx); + predict_rdata(is_secret(dai_addr) || is_digest(dai_addr), + otp_a[otp_addr], otp_a[otp_addr+1]); + end + end + end + DaiWrite: begin + bit[TL_AW-1:0] otp_addr = get_scb_otp_addr(); + bit is_write_locked; + // check if write locked + if (part_has_digest(part_idx)) begin + is_write_locked = get_digest_reg_val(part_idx) != 0; + end else begin + is_write_locked = 0; + end + + if (is_write_locked || (PartInfo[part_idx].iskeymgr_creator && + !is_digest(dai_addr) && + cfg.otp_ctrl_vif.lc_creator_seed_sw_rw_en_i != lc_ctrl_pkg::On)) begin + predict_err(OtpDaiErrIdx, OtpAccessError); + end else if (is_write_locked || (PartInfo[part_idx].iskeymgr_owner && + !is_digest(dai_addr) && + cfg.otp_ctrl_vif.lc_owner_seed_sw_rw_en_i != lc_ctrl_pkg::On)) begin + predict_err(OtpDaiErrIdx, OtpAccessError); + end else begin + predict_no_err(OtpDaiErrIdx); + // write digest + if (is_sw_digest(dai_addr)) begin + bit [TL_DW*2-1:0] curr_digest, prev_digest; + curr_digest = {`gmv(ral.direct_access_wdata[1]), + `gmv(ral.direct_access_wdata[0])}; + prev_digest = {otp_a[otp_addr+1], otp_a[otp_addr]}; + dai_wr_ip = 1; + // allow bit write + if ((prev_digest & curr_digest) == prev_digest) begin + update_digest_to_otp(part_idx, curr_digest); + end else begin + predict_err(OtpDaiErrIdx, OtpMacroWriteBlankError); + end + end else if (is_digest(dai_addr)) begin + predict_err(OtpDaiErrIdx, OtpAccessError); + // write OTP memory + end else begin + dai_wr_ip = 1; + if (!is_secret(dai_addr)) begin + bit [TL_DW-1:0] wr_data = `gmv(ral.direct_access_wdata[0]); + // allow bit write + if ((otp_a[otp_addr] & wr_data) == otp_a[otp_addr]) begin + otp_a[otp_addr] = wr_data; + check_otp_idle(.val(0), .wait_clks(3)); + end else begin + predict_err(OtpDaiErrIdx, OtpMacroWriteBlankError); + end + end else begin + bit [SCRAMBLE_DATA_SIZE-1:0] secret_data = {otp_a[otp_addr + 1], + otp_a[otp_addr]}; + bit [SCRAMBLE_DATA_SIZE-1:0] wr_data = {`gmv(ral.direct_access_wdata[1]), + `gmv(ral.direct_access_wdata[0])}; + wr_data = scramble_data(wr_data, part_idx); + secret_data = scramble_data(secret_data, part_idx); + if ((secret_data & wr_data) == secret_data) begin + otp_a[otp_addr] = `gmv(ral.direct_access_wdata[0]); + otp_a[otp_addr + 1] = `gmv(ral.direct_access_wdata[1]); + // wait until secret scrambling is done + check_otp_idle(.val(0), .wait_clks(34)); + end else begin + predict_err(OtpDaiErrIdx, OtpMacroWriteBlankError); + end + end + end + end + end + default: begin + `uvm_fatal(`gfn, $sformatf("invalid cmd: %0d", item.a_data)) + end + endcase + // regwen is set to 0 only if the dai operation is successfully + if (`gmv(ral.intr_state.otp_error) == 0) void'(ral.direct_access_regwen.predict(0)); + end + end + end + "status": begin + if (addr_phase_read) begin + void'(ral.status.predict(.value(exp_status), .kind(UVM_PREDICT_READ))); + + // update status mask + status_mask = 0; + // Mask out check_pending field - we do not know how long it takes to process checks. + // Check failure can trigger all kinds of errors. + if (under_chk) status_mask = '1; + + // Mask out otp_dai access related field - we do not know how long it takes to finish + // DAI access. + if (under_dai_access) begin + status_mask[OtpDaiIdleIdx] = 1; + status_mask[OtpDaiErrIdx] = 1; + end + + // Mask out LCI error bit if lc_req is set. + if (cfg.otp_ctrl_vif.lc_prog_no_sta_check) status_mask[OtpLciErrIdx] = 1; + + end else if (data_phase_read) begin + if (cfg.en_cov) begin + cov.collect_status_cov(item.d_data); + if (cfg.otp_ctrl_vif.alert_reqs) begin + cov.csr_rd_after_alert_cg_wrap.sample(csr.get_offset()); + end + end + + if (item.d_data[OtpDaiIdleIdx]) begin + check_otp_idle(1); + dai_wr_ip = 0; + dai_digest_ip = LifeCycleIdx; + end + + // STATUS register check with mask + if (do_read_check) begin + `DV_CHECK_EQ((csr.get_mirrored_value() | status_mask), (item.d_data | status_mask), + $sformatf("reg name: status, compare_mask %0h", status_mask)) + end + + // Check if OtpCheckPending is set correctly, then ignore checking until check is done + if (under_chk) begin + if (item.d_data[OtpCheckPendingIdx] == 0) begin + exp_status[OtpCheckPendingIdx] = 0; + under_chk = 0; + end + end + + if (under_dai_access && !cfg.otp_ctrl_vif.under_error_states()) begin + if (item.d_data[OtpDaiIdleIdx]) begin + under_dai_access = 0; + void'(ral.direct_access_regwen.predict(direct_access_regwen_state)); + void'(ral.intr_state.otp_operation_done.predict(1)); + end + end + end + // checked in this block above + do_read_check = 0; + end + "check_trigger": begin + if (addr_phase_write && cfg.en_cov && cfg.otp_ctrl_vif.alert_reqs) begin + cov.issue_checks_after_alert_cg.sample(item.a_data); + end + + if (addr_phase_write && `gmv(ral.check_trigger_regwen) && item.a_data inside {[1:3]}) begin + bit [TL_DW-1:0] check_timeout = `gmv(ral.check_timeout) == 0 ? '1 : + `gmv(ral.check_timeout); + exp_status[OtpCheckPendingIdx] = 1; + under_chk = 1; + if (check_timeout <= CHK_TIMEOUT_CYC) begin + set_exp_alert("fatal_check_error", 1, `gmv(ral.check_timeout)); + predict_err(OtpTimeoutErrIdx); + end else begin + if (get_field_val(ral.check_trigger.consistency, item.a_data)) begin + foreach (cfg.ecc_chk_err[i]) begin + if (cfg.ecc_chk_err[i] == OtpEccCorrErr && part_has_integrity(i)) begin + predict_err(otp_status_e'(i), OtpMacroEccCorrError); + end else if (cfg.ecc_chk_err[i] == OtpEccUncorrErr && + part_has_integrity(i)) begin + set_exp_alert("fatal_macro_error", 1, 40_000); + predict_err(otp_status_e'(i), OtpMacroEccUncorrError); + end + end + end + end + end + end + "direct_access_regwen": begin + if (addr_phase_write) begin + // This locks the DAI until the next reset. + if (!item.a_data[0]) begin + direct_access_regwen_state = 0; + void'(ral.direct_access_regwen.predict(0)); + end + end + end + // For error codes, if lc_prog in progress, err_code might update anytime in DUT. Ignore + // checking until req is acknowledged. + + "err_code_0": begin + if (cfg.m_lc_prog_pull_agent_cfg.vif.req) do_read_check = 0; + if (cfg.en_cov && do_read_check && data_phase_read) begin + bit [TL_DW-1:0] dai_addr = `gmv(ral.direct_access_address) >> 2 << 2; + int access_part_idx = get_part_index(dai_addr); + cov.collect_err_code_cov(0, item.d_data, access_part_idx); + end + end + "err_code_1": begin + if (cfg.m_lc_prog_pull_agent_cfg.vif.req) do_read_check = 0; + if (cfg.en_cov && do_read_check && data_phase_read) begin + bit [TL_DW-1:0] dai_addr = `gmv(ral.direct_access_address) >> 2 << 2; + int access_part_idx = get_part_index(dai_addr); + cov.collect_err_code_cov(1, item.d_data, access_part_idx); + end + end + "err_code_2": begin + if (cfg.m_lc_prog_pull_agent_cfg.vif.req) do_read_check = 0; + if (cfg.en_cov && do_read_check && data_phase_read) begin + bit [TL_DW-1:0] dai_addr = `gmv(ral.direct_access_address) >> 2 << 2; + int access_part_idx = get_part_index(dai_addr); + cov.collect_err_code_cov(2, item.d_data, access_part_idx); + end + end + "err_code_3": begin + if (cfg.m_lc_prog_pull_agent_cfg.vif.req) do_read_check = 0; + if (cfg.en_cov && do_read_check && data_phase_read) begin + bit [TL_DW-1:0] dai_addr = `gmv(ral.direct_access_address) >> 2 << 2; + int access_part_idx = get_part_index(dai_addr); + cov.collect_err_code_cov(3, item.d_data, access_part_idx); + end + end + "err_code_4": begin + if (cfg.m_lc_prog_pull_agent_cfg.vif.req) do_read_check = 0; + if (cfg.en_cov && do_read_check && data_phase_read) begin + bit [TL_DW-1:0] dai_addr = `gmv(ral.direct_access_address) >> 2 << 2; + int access_part_idx = get_part_index(dai_addr); + cov.collect_err_code_cov(4, item.d_data, access_part_idx); + end + end + "err_code_5": begin + if (cfg.m_lc_prog_pull_agent_cfg.vif.req) do_read_check = 0; + if (cfg.en_cov && do_read_check && data_phase_read) begin + bit [TL_DW-1:0] dai_addr = `gmv(ral.direct_access_address) >> 2 << 2; + int access_part_idx = get_part_index(dai_addr); + cov.collect_err_code_cov(5, item.d_data, access_part_idx); + end + end + "err_code_6": begin + if (cfg.m_lc_prog_pull_agent_cfg.vif.req) do_read_check = 0; + if (cfg.en_cov && do_read_check && data_phase_read) begin + bit [TL_DW-1:0] dai_addr = `gmv(ral.direct_access_address) >> 2 << 2; + int access_part_idx = get_part_index(dai_addr); + cov.collect_err_code_cov(6, item.d_data, access_part_idx); + end + end + "err_code_7": begin + if (cfg.m_lc_prog_pull_agent_cfg.vif.req) do_read_check = 0; + if (cfg.en_cov && do_read_check && data_phase_read) begin + bit [TL_DW-1:0] dai_addr = `gmv(ral.direct_access_address) >> 2 << 2; + int access_part_idx = get_part_index(dai_addr); + cov.collect_err_code_cov(7, item.d_data, access_part_idx); + end + end + "err_code_8": begin + if (cfg.m_lc_prog_pull_agent_cfg.vif.req) do_read_check = 0; + if (cfg.en_cov && do_read_check && data_phase_read) begin + bit [TL_DW-1:0] dai_addr = `gmv(ral.direct_access_address) >> 2 << 2; + int access_part_idx = get_part_index(dai_addr); + cov.collect_err_code_cov(8, item.d_data, access_part_idx); + end + end + "err_code_9": begin + if (cfg.m_lc_prog_pull_agent_cfg.vif.req) do_read_check = 0; + if (cfg.en_cov && do_read_check && data_phase_read) begin + bit [TL_DW-1:0] dai_addr = `gmv(ral.direct_access_address) >> 2 << 2; + int access_part_idx = get_part_index(dai_addr); + cov.collect_err_code_cov(9, item.d_data, access_part_idx); + end + end + "err_code_10": begin + if (cfg.m_lc_prog_pull_agent_cfg.vif.req) do_read_check = 0; + if (cfg.en_cov && do_read_check && data_phase_read) begin + bit [TL_DW-1:0] dai_addr = `gmv(ral.direct_access_address) >> 2 << 2; + int access_part_idx = get_part_index(dai_addr); + cov.collect_err_code_cov(10, item.d_data, access_part_idx); + end + end + "err_code_11": begin + if (cfg.m_lc_prog_pull_agent_cfg.vif.req) do_read_check = 0; + if (cfg.en_cov && do_read_check && data_phase_read) begin + bit [TL_DW-1:0] dai_addr = `gmv(ral.direct_access_address) >> 2 << 2; + int access_part_idx = get_part_index(dai_addr); + cov.collect_err_code_cov(11, item.d_data, access_part_idx); + end + end + "err_code_12": begin + if (cfg.m_lc_prog_pull_agent_cfg.vif.req) do_read_check = 0; + if (cfg.en_cov && do_read_check && data_phase_read) begin + bit [TL_DW-1:0] dai_addr = `gmv(ral.direct_access_address) >> 2 << 2; + int access_part_idx = get_part_index(dai_addr); + cov.collect_err_code_cov(12, item.d_data, access_part_idx); + end + end + "vendor_test_digest_0", "vendor_test_digest_1", + "creator_sw_cfg_digest_0", "creator_sw_cfg_digest_1", + "owner_sw_cfg_digest_0", "owner_sw_cfg_digest_1", + "rot_creator_auth_codesign_digest_0", "rot_creator_auth_codesign_digest_1", + "rot_creator_auth_state_digest_0", "rot_creator_auth_state_digest_1", + "hw_cfg0_digest_0", "hw_cfg0_digest_1", + "hw_cfg1_digest_0", "hw_cfg1_digest_1", + "secret0_digest_0", "secret0_digest_1", + "secret1_digest_0", "secret1_digest_1", + "secret2_digest_0", "secret2_digest_1": begin + if (ignore_digest_chk) do_read_check = 0; + end + "vendor_test_read_lock", + "creator_sw_cfg_read_lock", + "owner_sw_cfg_read_lock", + "rot_creator_auth_codesign_read_lock", + "rot_creator_auth_state_read_lock", + "direct_access_wdata_0", + "direct_access_wdata_1", + "direct_access_address", + "check_regwen", + "check_trigger_regwen", + "check_trigger", + "check_timeout", + "intr_enable", + "integrity_check_period", + "consistency_check_period", + "alert_test": begin + // Do nothing + end + // DAI read data + "direct_access_rdata_0", "direct_access_rdata_1": do_read_check = check_dai_rd_data; + default: begin + `uvm_fatal(`gfn, $sformatf("invalid csr: %0s", csr.get_full_name())) + end + endcase + + // On reads, if do_read_check, is set, then check mirrored_value against item.d_data + if (data_phase_read) begin + if (do_read_check) begin + `DV_CHECK_EQ(csr.get_mirrored_value(), item.d_data, + $sformatf("reg name: %0s", csr.get_full_name())) + if (cfg.en_cov && cfg.otp_ctrl_vif.alert_reqs) begin + cov.csr_rd_after_alert_cg_wrap.sample(csr.get_offset()); + end + end + void'(csr.predict(.value(item.d_data), .kind(UVM_PREDICT_READ))); + end + endfunction + + // If reset or lc_escalate_en is issued during otp program, this function will backdoor update + // otp memory write value because scb did not know how many cells haven been written. + // We won't update csr `direct_access_address` after fatal alert happened, so in this function + // we can directly call method `get_scb_otp_addr` to get the interrupted dai address. + virtual function void recover_interrupted_op(); + if (dai_wr_ip) begin + bit [TL_DW-1:0] otp_addr = get_scb_otp_addr(); + bit [TL_DW-1:0] dai_addr = otp_addr << 2; + backdoor_update_otp_array(dai_addr); + dai_wr_ip = 0; + end + endfunction + + virtual function void backdoor_update_otp_array(bit [TL_DW-1:0] dai_addr); + bit [TL_DW-1:0] otp_addr = dai_addr >> 2; + bit [TL_DW-1:0] readout_word, readout_word1; + int part_idx = get_part_index(dai_addr); + if (part_has_integrity(part_idx)) begin + void'(read_a_word_with_ecc(dai_addr, readout_word)); + void'(read_a_word_with_ecc(dai_addr + 4, readout_word1)); + end else begin + void'(read_a_word_with_ecc_raw(dai_addr, readout_word)); + void'(read_a_word_with_ecc_raw(dai_addr + 4, readout_word1)); + end + + otp_a[otp_addr] = readout_word; + + if (is_digest(dai_addr)) begin + otp_a[otp_addr+1] = readout_word1; + end else if (is_secret(dai_addr)) begin + bit [TL_DW*2-1:0] mem_rd_val, descrambled_val; + mem_rd_val = {readout_word1 ,readout_word}; + descrambled_val = descramble_data(mem_rd_val, part_idx); + otp_a[otp_addr+1] = descrambled_val[TL_DW*2-1:TL_DW]; + otp_a[otp_addr] = descrambled_val[TL_DW-1:0]; + end + endfunction + + virtual function bit [1:0] read_a_word_with_ecc(bit [TL_DW-1:0] dai_addr, + ref bit [TL_DW-1:0] readout_word); + prim_secded_pkg::secded_22_16_t ecc_rd_data0 = cfg.mem_bkdr_util_h.ecc_read16(dai_addr); + prim_secded_pkg::secded_22_16_t ecc_rd_data1 = cfg.mem_bkdr_util_h.ecc_read16(dai_addr + 2); + readout_word[15:0] = ecc_rd_data0.data; + readout_word[31:16] = ecc_rd_data1.data; + return max2(ecc_rd_data0.err, ecc_rd_data1.err); + endfunction + + // Returns the ECC error but does not correct the data bits (i.e. returns the raw data). + virtual function bit [1:0] read_a_word_with_ecc_raw(bit [TL_DW-1:0] dai_addr, + ref bit [TL_DW-1:0] readout_word); + prim_secded_pkg::secded_22_16_t ecc_rd_data0 = cfg.mem_bkdr_util_h.ecc_read16(dai_addr); + prim_secded_pkg::secded_22_16_t ecc_rd_data1 = cfg.mem_bkdr_util_h.ecc_read16(dai_addr + 2); + readout_word[15:0] = 16'hFFFF & cfg.mem_bkdr_util_h.read(dai_addr); + readout_word[31:16] = 16'hFFFF & cfg.mem_bkdr_util_h.read(dai_addr + 2); + return max2(ecc_rd_data0.err, ecc_rd_data1.err); + endfunction + + + virtual function void reset(string kind = "HARD"); + recover_interrupted_op(); + super.reset(kind); + // flush fifos + otbn_fifo.flush(); + flash_addr_fifo.flush(); + flash_data_fifo.flush(); + lc_prog_fifo.flush(); + for (int i = 0; i < NumSramKeyReqSlots; i++) begin + sram_fifos[i].flush(); + end + + direct_access_regwen_state = 1; + under_chk = 0; + under_dai_access = 0; + ignore_digest_chk = 0; + exp_status = `gmv(ral.status); + exp_alert = OtpNoAlert; + + edn_data_q.delete(); + + // Out of reset: lock dai access until power init is done + if (cfg.en_scb) void'(ral.direct_access_regwen.predict(0)); + endfunction + + virtual function void check_otp_idle(bit val, int wait_clks = 0); + fork + begin + fork + begin + // use negedge to avoid race condition + cfg.clk_rst_vif.wait_n_clks(wait_clks + 1); + `uvm_error(`gfn, + $sformatf("pwr_otp_idle output is %0b while expect %0b within %0d cycles", + cfg.otp_ctrl_vif.pwr_otp_idle_o, val, wait_clks)) + end + begin + wait(cfg.under_reset || cfg.otp_ctrl_vif.pwr_otp_idle_o == val || + // Due to OTP access arbitration, any KDI request during DAI access might block + // write secret until KDI request is completed. Since the KDI process time could + // vary depends on the push-pull-agent, we are going to ignore the checking if + // this scenario happens. + cfg.m_otbn_pull_agent_cfg.vif.req || + cfg.m_flash_data_pull_agent_cfg.vif.req || + cfg.m_flash_addr_pull_agent_cfg.vif.req || + cfg.m_sram_pull_agent_cfg[0].vif.req || + cfg.m_sram_pull_agent_cfg[1].vif.req || + cfg.m_sram_pull_agent_cfg[2].vif.req || + cfg.m_sram_pull_agent_cfg[3].vif.req || + cfg.m_lc_prog_pull_agent_cfg.vif.req || + // When lc_escalation is on, the DAI interface goes to ErrorSt, so ignore + // otp_idle checking. + cfg.otp_ctrl_vif.alert_reqs || + // Check timeout will keep doing background check, issue #5616 + exp_status[OtpTimeoutErrIdx]); + end + join_any + disable fork; + end + join_none + endfunction + + // predict digest registers + virtual function void predict_digest_csrs(); + void'(ral.vendor_test_digest[0].predict( + .value(otp_a[PART_OTP_DIGEST_ADDRS[VendorTestIdx]]), + .kind(UVM_PREDICT_DIRECT))); + void'(ral.vendor_test_digest[1].predict( + .value(otp_a[PART_OTP_DIGEST_ADDRS[VendorTestIdx] + 1]), + .kind(UVM_PREDICT_DIRECT))); + + void'(ral.creator_sw_cfg_digest[0].predict( + .value(otp_a[PART_OTP_DIGEST_ADDRS[CreatorSwCfgIdx]]), + .kind(UVM_PREDICT_DIRECT))); + void'(ral.creator_sw_cfg_digest[1].predict( + .value(otp_a[PART_OTP_DIGEST_ADDRS[CreatorSwCfgIdx] + 1]), + .kind(UVM_PREDICT_DIRECT))); + + void'(ral.owner_sw_cfg_digest[0].predict( + .value(otp_a[PART_OTP_DIGEST_ADDRS[OwnerSwCfgIdx]]), + .kind(UVM_PREDICT_DIRECT))); + void'(ral.owner_sw_cfg_digest[1].predict( + .value(otp_a[PART_OTP_DIGEST_ADDRS[OwnerSwCfgIdx] + 1]), + .kind(UVM_PREDICT_DIRECT))); + + void'(ral.rot_creator_auth_codesign_digest[0].predict( + .value(otp_a[PART_OTP_DIGEST_ADDRS[RotCreatorAuthCodesignIdx]]), + .kind(UVM_PREDICT_DIRECT))); + void'(ral.rot_creator_auth_codesign_digest[1].predict( + .value(otp_a[PART_OTP_DIGEST_ADDRS[RotCreatorAuthCodesignIdx] + 1]), + .kind(UVM_PREDICT_DIRECT))); + + void'(ral.rot_creator_auth_state_digest[0].predict( + .value(otp_a[PART_OTP_DIGEST_ADDRS[RotCreatorAuthStateIdx]]), + .kind(UVM_PREDICT_DIRECT))); + void'(ral.rot_creator_auth_state_digest[1].predict( + .value(otp_a[PART_OTP_DIGEST_ADDRS[RotCreatorAuthStateIdx] + 1]), + .kind(UVM_PREDICT_DIRECT))); + + void'(ral.hw_cfg0_digest[0].predict( + .value(otp_a[PART_OTP_DIGEST_ADDRS[HwCfg0Idx]]), + .kind(UVM_PREDICT_DIRECT))); + void'(ral.hw_cfg0_digest[1].predict( + .value(otp_a[PART_OTP_DIGEST_ADDRS[HwCfg0Idx] + 1]), + .kind(UVM_PREDICT_DIRECT))); + + void'(ral.hw_cfg1_digest[0].predict( + .value(otp_a[PART_OTP_DIGEST_ADDRS[HwCfg1Idx]]), + .kind(UVM_PREDICT_DIRECT))); + void'(ral.hw_cfg1_digest[1].predict( + .value(otp_a[PART_OTP_DIGEST_ADDRS[HwCfg1Idx] + 1]), + .kind(UVM_PREDICT_DIRECT))); + + void'(ral.secret0_digest[0].predict( + .value(otp_a[PART_OTP_DIGEST_ADDRS[Secret0Idx]]), + .kind(UVM_PREDICT_DIRECT))); + void'(ral.secret0_digest[1].predict( + .value(otp_a[PART_OTP_DIGEST_ADDRS[Secret0Idx] + 1]), + .kind(UVM_PREDICT_DIRECT))); + + void'(ral.secret1_digest[0].predict( + .value(otp_a[PART_OTP_DIGEST_ADDRS[Secret1Idx]]), + .kind(UVM_PREDICT_DIRECT))); + void'(ral.secret1_digest[1].predict( + .value(otp_a[PART_OTP_DIGEST_ADDRS[Secret1Idx] + 1]), + .kind(UVM_PREDICT_DIRECT))); + + void'(ral.secret2_digest[0].predict( + .value(otp_a[PART_OTP_DIGEST_ADDRS[Secret2Idx]]), + .kind(UVM_PREDICT_DIRECT))); + void'(ral.secret2_digest[1].predict( + .value(otp_a[PART_OTP_DIGEST_ADDRS[Secret2Idx] + 1]), + .kind(UVM_PREDICT_DIRECT))); + endfunction + + function void update_digest_to_otp(int part_idx, bit [TL_DW*2-1:0] digest); + otp_a[PART_OTP_DIGEST_ADDRS[part_idx]] = digest[31:0]; + otp_a[PART_OTP_DIGEST_ADDRS[part_idx] + 1] = digest[63:32]; + endfunction + + function void check_phase(uvm_phase phase); + super.check_phase(phase); + // post test checks - ensure that all local fifos and queues are empty + endfunction + + // Calculate digest value for each partition + // According to the design spec, the calculation is based on 64-rounds of PRESENT cipher + // The 64-bit data_in state is initialized with a silicon creator constant, and each 128 bit + // chunk of partition data are fed in as keys + // The last 64-round PRESENT calculation will use a global digest constant as key input + function void cal_digest_val(int part_idx); + bit [TL_DW-1:0] mem_q[$]; + int array_size; + bit [SCRAMBLE_DATA_SIZE-1:0] digest; + + if (cfg.otp_ctrl_vif.under_error_states()) return; + + if (!part_has_hw_digest(part_idx) || get_digest_reg_val(part_idx) != 0) begin + predict_err(OtpDaiErrIdx, OtpAccessError); + return; + end else if (PartInfo[part_idx].iskeymgr_creator && + cfg.otp_ctrl_vif.lc_creator_seed_sw_rw_en_i != lc_ctrl_pkg::On) begin + predict_err(OtpDaiErrIdx, OtpAccessError); + return; + end else if (PartInfo[part_idx].iskeymgr_owner && + cfg.otp_ctrl_vif.lc_owner_seed_sw_rw_en_i != lc_ctrl_pkg::On) begin + predict_err(OtpDaiErrIdx, OtpAccessError); + return; + end else begin + predict_no_err(OtpDaiErrIdx); + dai_digest_ip = part_idx; + end + case (part_idx) + HwCfg0Idx: mem_q = otp_a[HwCfg0Offset / TL_SIZE : HwCfg0DigestOffset / TL_SIZE - 1]; + HwCfg1Idx: mem_q = otp_a[HwCfg1Offset / TL_SIZE : HwCfg1DigestOffset / TL_SIZE - 1]; + Secret0Idx: mem_q = otp_a[Secret0Offset / TL_SIZE : Secret0DigestOffset / TL_SIZE - 1]; + Secret1Idx: mem_q = otp_a[Secret1Offset / TL_SIZE : Secret1DigestOffset / TL_SIZE - 1]; + Secret2Idx: mem_q = otp_a[Secret2Offset / TL_SIZE : Secret2DigestOffset / TL_SIZE - 1]; + default: begin + `uvm_fatal(`gfn, $sformatf("Access unexpected partition %0d", part_idx)) + end + endcase + + array_size = mem_q.size(); + + // for secret partitions, need to use otp scrambled value as data input + if (PartInfo[part_idx].secret) begin + bit [TL_DW-1:0] scrambled_mem_q[$]; + for (int i = 0; i < array_size/2; i++) begin + bit [SCRAMBLE_DATA_SIZE-1:0] scrambled_data; + scrambled_data = scramble_data({mem_q[i*2+1], mem_q[i*2]}, part_idx); + scrambled_mem_q.push_back(scrambled_data[TL_DW-1:0]); + scrambled_mem_q.push_back(scrambled_data[SCRAMBLE_DATA_SIZE-1:TL_DW]); + end + mem_q = scrambled_mem_q; + end + + digest = otp_scrambler_pkg::cal_digest(part_idx, mem_q); + update_digest_to_otp(part_idx, digest); + endfunction + + + // this function go through present encode algo two or three iterations: + // first iteration with input key, + // second iteration with second_key, this iteration only happens if num_round is 2 + // third iteration with a final constant as key + // this is mainly used for unlock token hashing, key derivation + virtual function bit [SCRAMBLE_DATA_SIZE-1:0] present_encode_with_final_const( + bit [SCRAMBLE_DATA_SIZE-1:0] data, + bit [SCRAMBLE_KEY_SIZE-1:0] key, + bit [SCRAMBLE_KEY_SIZE-1:0] final_const, + bit [SCRAMBLE_KEY_SIZE-1:0] second_key = '0, + int num_round = 1); + bit [SCRAMBLE_DATA_SIZE-1:0] enc_data; + bit [SCRAMBLE_DATA_SIZE-1:0] intermediate_state; + crypto_dpi_present_pkg::sv_dpi_present_encrypt(data, key, + SCRAMBLE_KEY_SIZE, NUM_ROUND, enc_data); + // XOR the previous state into the digest result according to the Davies-Meyer scheme. + intermediate_state = data ^ enc_data; + + if (num_round == 2) begin + crypto_dpi_present_pkg::sv_dpi_present_encrypt(intermediate_state, second_key, + SCRAMBLE_KEY_SIZE, NUM_ROUND, enc_data); + intermediate_state = intermediate_state ^ enc_data; + end else if (num_round > 2) begin + `uvm_fatal(`gfn, $sformatf("does not support num_round: %0d > 2", num_round)) + end + + crypto_dpi_present_pkg::sv_dpi_present_encrypt(intermediate_state, final_const, + SCRAMBLE_KEY_SIZE, NUM_ROUND, enc_data); + // XOR the previous state into the digest result according to the Davies-Meyer scheme. + present_encode_with_final_const = intermediate_state ^ enc_data; + endfunction + + // Get address for scoreboard's otp_a array from the `direct_access_address` CSR + function bit [TL_DW-1:0] get_scb_otp_addr(); + bit [TL_DW-1:0] dai_addr = `gmv(ral.direct_access_address); + get_scb_otp_addr = normalize_dai_addr(dai_addr) >> 2; + endfunction + + // This function predict OTP error related registers: intr_state, status, and err_code + virtual function void predict_err(otp_status_e status_err_idx, + otp_err_code_e err_code = OtpNoError, + bit update_esc_err = 0); + if (cfg.otp_ctrl_vif.under_error_states() && !update_esc_err) return; + + // Update intr_state + void'(ral.intr_state.otp_error.predict(.value(1), .kind(UVM_PREDICT_READ))); + // Update status + exp_status[status_err_idx] = 1; + + // Only first status errors up to the LCI have corresponding err_code + if (status_err_idx <= OtpLciErrIdx) begin + dv_base_reg_field err_code_flds[$]; + if (err_code == OtpNoError) begin + `uvm_error(`gfn, $sformatf("please set status error: %0s error code", status_err_idx.name)) + end + ral.err_code[status_err_idx].get_dv_base_reg_fields(err_code_flds); + + if (`gmv(err_code_flds[0]) inside {OTP_TERMINAL_ERRS}) begin + `uvm_info(`gfn, "terminal error cannot be updated", UVM_HIGH) + end else if (status_err_idx == OtpLciErrIdx && + `gmv(err_code_flds[0]) != OtpNoError) begin + `uvm_info(`gfn, "For LC partition, all errors are terminal error!", UVM_HIGH) + end else begin + void'(err_code_flds[0].predict(.value(err_code), .kind(UVM_PREDICT_READ))); + end + end + + endfunction + + virtual function void predict_no_err(otp_status_e status_err_idx); + if (cfg.otp_ctrl_vif.under_error_states()) return; + + exp_status[status_err_idx] = 0; + if (status_err_idx == OtpDaiErrIdx) exp_status[OtpDaiIdleIdx] = 1; + + if (status_err_idx <= OtpLciErrIdx) begin + dv_base_reg_field err_code_flds[$]; + ral.err_code[status_err_idx].get_dv_base_reg_fields(err_code_flds); + void'(err_code_flds[0].predict(OtpNoError)); + end + endfunction + + virtual function void predict_rdata(bit is_64_bits, bit [TL_DW-1:0] rdata0, + bit [TL_DW-1:0] rdata1 = 0); + void'(ral.direct_access_rdata[0].predict(.value(rdata0), .kind(UVM_PREDICT_READ))); + if (is_64_bits) begin + void'(ral.direct_access_rdata[1].predict(.value(rdata1), .kind(UVM_PREDICT_READ))); + end + endfunction + + // this function retrieves keys (128 bits) from scb's otp_array with a starting address + // if not locked, it will return 0 + // this is mainly used for scrambling key algo + virtual function bit [SCRAMBLE_KEY_SIZE-1:0] get_key_from_otp(bit locked, int start_i); + bit [SCRAMBLE_KEY_SIZE-1:0] key; + if (!locked) return 0; + for (int i = 0; i < 4; i++) key |= otp_a[i + start_i] << (TL_DW * i); + return key; + endfunction + + // The following two methods are all retrieving digest val. + // get_otp_digest_val: is the digest value from OTP memory + // get_digest_reg_val: is the digest value in register. This value is identical to OTP + // memory's digest value after a power cycle reset. + virtual function bit [TL_DW*2-1:0] get_otp_digest_val(int part_idx); + get_otp_digest_val[31:0] = otp_a[PART_OTP_DIGEST_ADDRS[part_idx]]; + get_otp_digest_val[63:32] = otp_a[PART_OTP_DIGEST_ADDRS[part_idx] + 1]; + endfunction + + virtual function bit [TL_DW*2-1:0] get_digest_reg_val(int part_idx); + bit [TL_DW*2-1:0] digest; + case (part_idx) + VendorTestIdx: begin + digest = {`gmv(ral.vendor_test_digest[1]), + `gmv(ral.vendor_test_digest[0])}; + end + CreatorSwCfgIdx: begin + digest = {`gmv(ral.creator_sw_cfg_digest[1]), + `gmv(ral.creator_sw_cfg_digest[0])}; + end + OwnerSwCfgIdx: begin + digest = {`gmv(ral.owner_sw_cfg_digest[1]), + `gmv(ral.owner_sw_cfg_digest[0])}; + end + RotCreatorAuthCodesignIdx: begin + digest = {`gmv(ral.rot_creator_auth_codesign_digest[1]), + `gmv(ral.rot_creator_auth_codesign_digest[0])}; + end + RotCreatorAuthStateIdx: begin + digest = {`gmv(ral.rot_creator_auth_state_digest[1]), + `gmv(ral.rot_creator_auth_state_digest[0])}; + end + HwCfg0Idx: begin + digest = {`gmv(ral.hw_cfg0_digest[1]), + `gmv(ral.hw_cfg0_digest[0])}; + end + HwCfg1Idx: begin + digest = {`gmv(ral.hw_cfg1_digest[1]), + `gmv(ral.hw_cfg1_digest[0])}; + end + Secret0Idx: begin + digest = {`gmv(ral.secret0_digest[1]), + `gmv(ral.secret0_digest[0])}; + end + Secret1Idx: begin + digest = {`gmv(ral.secret1_digest[1]), + `gmv(ral.secret1_digest[0])}; + end + Secret2Idx: begin + digest = {`gmv(ral.secret2_digest[1]), + `gmv(ral.secret2_digest[0])}; + end + default: `uvm_fatal(`gfn, $sformatf("Partition %0d does not have digest", part_idx)) + endcase + return digest; + endfunction + + virtual function bit is_tl_mem_access_allowed(input tl_seq_item item, input string ral_name, + output bit mem_byte_access_err, + output bit mem_wo_err, + output bit mem_ro_err, + output bit custom_err); + + uvm_reg_addr_t addr = cfg.ral_models[ral_name].get_word_aligned_addr(item.a_addr); + uvm_reg_addr_t csr_addr = cfg.ral_models[ral_name].get_word_aligned_addr(item.a_addr); + bit [TL_AW-1:0] addr_mask = ral.get_addr_mask(); + bit [TL_AW-1:0] dai_addr = (csr_addr & addr_mask - SW_WINDOW_BASE_ADDR); + + bit mem_access_allowed = super.is_tl_mem_access_allowed(item, ral_name, mem_byte_access_err, + mem_wo_err, mem_ro_err, custom_err); + + if (ral_name == "otp_ctrl_prim_reg_block") return mem_access_allowed; + + // Ensure the address is within the memory window range. + // Also will skip checking if memory access is not allowed due to TLUL bus error. + if (addr inside { + [cfg.ral_models[ral_name].mem_ranges[0].start_addr : + cfg.ral_models[ral_name].mem_ranges[0].end_addr]} && + mem_access_allowed) begin + + // If sw partition is read locked, then access policy changes from RO to no access + if (`gmv(ral.vendor_test_read_lock) == 0 || + cfg.otp_ctrl_vif.under_error_states()) begin + if (addr inside { + [cfg.ral_models[ral_name].mem_ranges[0].start_addr + VendorTestOffset : + cfg.ral_models[ral_name].mem_ranges[0].start_addr + VendorTestOffset + + VendorTestSize - 1]}) begin + predict_err(OtpVendorTestErrIdx, OtpAccessError); + custom_err = 1; + if (cfg.en_cov) begin + cov.unbuf_access_lock_cg_wrap[VendorTestIdx].sample(.read_lock(1), + .write_lock(get_digest_reg_val(VendorTestIdx) != 0), .is_write(0)); + end + return 0; + end + end + if (`gmv(ral.creator_sw_cfg_read_lock) == 0 || + cfg.otp_ctrl_vif.under_error_states()) begin + if (addr inside { + [cfg.ral_models[ral_name].mem_ranges[0].start_addr + CreatorSwCfgOffset : + cfg.ral_models[ral_name].mem_ranges[0].start_addr + CreatorSwCfgOffset + + CreatorSwCfgSize - 1]}) begin + predict_err(OtpCreatorSwCfgErrIdx, OtpAccessError); + custom_err = 1; + if (cfg.en_cov) begin + cov.unbuf_access_lock_cg_wrap[CreatorSwCfgIdx].sample(.read_lock(1), + .write_lock(get_digest_reg_val(CreatorSwCfgIdx) != 0), .is_write(0)); + end + return 0; + end + end + if (`gmv(ral.owner_sw_cfg_read_lock) == 0 || + cfg.otp_ctrl_vif.under_error_states()) begin + if (addr inside { + [cfg.ral_models[ral_name].mem_ranges[0].start_addr + OwnerSwCfgOffset : + cfg.ral_models[ral_name].mem_ranges[0].start_addr + OwnerSwCfgOffset + + OwnerSwCfgSize - 1]}) begin + predict_err(OtpOwnerSwCfgErrIdx, OtpAccessError); + custom_err = 1; + if (cfg.en_cov) begin + cov.unbuf_access_lock_cg_wrap[OwnerSwCfgIdx].sample(.read_lock(1), + .write_lock(get_digest_reg_val(OwnerSwCfgIdx) != 0), .is_write(0)); + end + return 0; + end + end + if (`gmv(ral.rot_creator_auth_codesign_read_lock) == 0 || + cfg.otp_ctrl_vif.under_error_states()) begin + if (addr inside { + [cfg.ral_models[ral_name].mem_ranges[0].start_addr + RotCreatorAuthCodesignOffset : + cfg.ral_models[ral_name].mem_ranges[0].start_addr + RotCreatorAuthCodesignOffset + + RotCreatorAuthCodesignSize - 1]}) begin + predict_err(OtpRotCreatorAuthCodesignErrIdx, OtpAccessError); + custom_err = 1; + if (cfg.en_cov) begin + cov.unbuf_access_lock_cg_wrap[RotCreatorAuthCodesignIdx].sample(.read_lock(1), + .write_lock(get_digest_reg_val(RotCreatorAuthCodesignIdx) != 0), .is_write(0)); + end + return 0; + end + end + if (`gmv(ral.rot_creator_auth_state_read_lock) == 0 || + cfg.otp_ctrl_vif.under_error_states()) begin + if (addr inside { + [cfg.ral_models[ral_name].mem_ranges[0].start_addr + RotCreatorAuthStateOffset : + cfg.ral_models[ral_name].mem_ranges[0].start_addr + RotCreatorAuthStateOffset + + RotCreatorAuthStateSize - 1]}) begin + predict_err(OtpRotCreatorAuthStateErrIdx, OtpAccessError); + custom_err = 1; + if (cfg.en_cov) begin + cov.unbuf_access_lock_cg_wrap[RotCreatorAuthStateIdx].sample(.read_lock(1), + .write_lock(get_digest_reg_val(RotCreatorAuthStateIdx) != 0), .is_write(0)); + end + return 0; + end + end + + // Check ECC uncorrectable fatal error. + if (dai_addr < LifeCycleOffset) begin + int part_idx = get_part_index(dai_addr); + bit [TL_DW-1:0] read_out; + int ecc_err = read_a_word_with_ecc(dai_addr, read_out); + if (ecc_err == OtpEccUncorrErr && part_has_integrity(part_idx)) begin + predict_err(otp_status_e'(part_idx), OtpMacroEccUncorrError); + set_exp_alert("fatal_macro_error", 1, 20); + custom_err = 1; + return 0; + end + end + end + + return mem_access_allowed; + endfunction + + virtual function bit predict_tl_err(tl_seq_item item, tl_channels_e channel, string ral_name); + if (ral_name == "otp_ctrl_prim_reg_block" && + cfg.otp_ctrl_vif.lc_dft_en_i != lc_ctrl_pkg::On) begin + if (channel == DataChannel) begin + `DV_CHECK_EQ(item.d_error, 1, + $sformatf({"On interface %0s, TL item: %0s, access gated by lc_dft_en_i"}, + ral_name, item.sprint(uvm_default_line_printer))) + + // In data read phase, check d_data when d_error = 1. + if (item.d_error && (item.d_opcode == tlul_pkg::AccessAckData)) begin + check_tl_read_value_after_error(item, ral_name); + end + end + return 1; + end + return super.predict_tl_err(item, channel, ral_name); + endfunction + + virtual function void set_exp_alert(string alert_name, bit is_fatal = 0, int max_delay = 0); + exp_alert = alert_name == "fatal_check_error" ? OtpCheckAlert : OtpMacroAlert; + super.set_exp_alert(alert_name, is_fatal, max_delay); + endfunction + +endclass diff --git a/src/fuse_ctrl/dv/env/otp_ctrl_virtual_sequencer.sv b/src/fuse_ctrl/dv/env/otp_ctrl_virtual_sequencer.sv new file mode 100644 index 0000000..4780a80 --- /dev/null +++ b/src/fuse_ctrl/dv/env/otp_ctrl_virtual_sequencer.sv @@ -0,0 +1,19 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class otp_ctrl_virtual_sequencer extends cip_base_virtual_sequencer #( + .CFG_T(otp_ctrl_env_cfg), + .COV_T(otp_ctrl_env_cov) + ); + `uvm_component_utils(otp_ctrl_virtual_sequencer) + + `uvm_component_new + + push_pull_sequencer#(.DeviceDataWidth(SRAM_DATA_SIZE)) sram_pull_sequencer_h[NumSramKeyReqSlots]; + push_pull_sequencer#(.DeviceDataWidth(OTBN_DATA_SIZE)) otbn_pull_sequencer_h; + push_pull_sequencer#(.DeviceDataWidth(FLASH_DATA_SIZE)) flash_data_pull_sequencer_h; + push_pull_sequencer#(.DeviceDataWidth(FLASH_DATA_SIZE)) flash_addr_pull_sequencer_h; + push_pull_sequencer#(.DeviceDataWidth(1), .HostDataWidth(LC_PROG_DATA_SIZE)) + lc_prog_pull_sequencer_h; +endclass diff --git a/src/fuse_ctrl/dv/otp_ctrl_top_sim_cfg.hjson b/src/fuse_ctrl/dv/otp_ctrl_top_sim_cfg.hjson new file mode 100644 index 0000000..0cbc6a1 --- /dev/null +++ b/src/fuse_ctrl/dv/otp_ctrl_top_sim_cfg.hjson @@ -0,0 +1,179 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + // Name of the sim cfg - typically same as the name of the DUT. + name: otp_ctrl_top + + // Top level dut name (sv module). + dut: otp_ctrl_top + + // Top level testbench name (sv module). + tb: tb + + // Simulator used to sign off this block + tool: vcs + + // Fusesoc core file used for building the file list. + fusesoc_core: lowrisc:dv:otp_ctrl_sim:0.1 + + // Testplan hjson file. + testplan: "{CALIPTRA_ROOT}/src/otp_ctrl/data/otp_ctrl_testplan.hjson" + + // RAL spec - used to generate the RAL model. + ral_spec: "{CALITPRA_ROOT}/src/otp_ctrl/data/otp_ctrl.hjson" + + // Import additional common sim cfg files. + import_cfgs: [// Project wide common sim cfg file + "{CALIPTRA_ROOT}/tools/dv/dvsim/common_sim_cfg.hjson", + // Config files to get the correct flags for crypto_dpi_prince + //"{CALIPTRA_ROOT}/hw/ip/prim/dv/prim_prince/crypto_dpi_prince/crypto_dpi_prince_sim_opts.hjson", + // Common CIP test lists + "{CALIPTRA_ROOT}/tools/dv/dvsim/tests/csr_tests.hjson", + "{CALIPTRA_ROOT}/tools/dv/dvsim/tests/mem_tests.hjson", + "{CALIPTRA_ROOT}/tools/dv/dvsim/tests/intr_test.hjson", + "{CALIPTRA_ROOT}/tools/dv/dvsim/tests/alert_test.hjson", + "{CALIPTRA_ROOT}/tools/dv/dvsim/tests/tl_access_tests.hjson", + "{CALIPTRA_ROOT}/tools/dv/dvsim/tests/sec_cm_tests.hjson", + "{CALIPTRA_ROOT}/tools/dv/dvsim/tests/stress_tests.hjson"] + + //en_build_modes: ["{tool}_crypto_dpi_prince_build_opts"] + + build_modes: [ + // Sim mode that enables build randomization. See the `build_seed` mode + // defined in `hw/dv/tools/dvsim/common_modes.hjson` for more details. + { + name: build_seed + pre_build_cmds: ["cd {CALIPTRA_ROOT} && ./tools/util/design/gen-otp-mmap.py --seed {seed}"] + is_sim_mode: 1 + } + ] + + // Add additional tops for simulation. + sim_tops: ["otp_ctrl_bind", "otp_ctrl_cov_bind", + "sec_cm_prim_sparse_fsm_flop_bind", + "sec_cm_prim_count_bind", + "sec_cm_prim_double_lfsr_bind", + "sec_cm_prim_onehot_check_bind"] + + // Default iterations for all tests - each test entry can override this. + reseed: 50 + + // Add OTP_CTRL specific exclusion files. + vcs_cov_excl_files: ["{CALIPTRA_ROOT}/src/otp_ctrl/dv/cov/otp_ctrl_cov_unr_excl.el", + "{CALIPTRA_ROOT}/src/otp_ctrl/dv/cov/otp_ctrl_cov_fsm_unr_excl.el"] + + overrides: [ + { + name: default_vcs_cov_cfg_file + value: "-cm_hier {CALIPTRA_ROOT}/tools/dv/vcs/cover.cfg+{CALIPTRA_ROOT}/tools/dv/vcs/common_cov_excl.cfg+{CALIPTRA_ROOT}/src/otp_ctrl/dv/cov/otp_ctrl_cover.cfg" + } + ] + + // Default UVM test and seq class name. + uvm_test: otp_ctrl_base_test + uvm_test_seq: otp_ctrl_base_vseq + + run_opts: ["+cdc_instrumentation_enabled=1"] + + // List of test specifications. + tests: [ + { + name: otp_ctrl_wake_up + uvm_test_seq: otp_ctrl_wake_up_vseq + run_opts: ["+en_scb=0"] + reseed: 1 + } + + { + name: otp_ctrl_smoke + uvm_test_seq: otp_ctrl_smoke_vseq + } + + { + name: otp_ctrl_partition_walk + uvm_test_seq: otp_ctrl_partition_walk_vseq + reseed: 1 + } + + { + name: otp_ctrl_low_freq_read + uvm_test_seq: otp_ctrl_low_freq_read_vseq + reseed: 1 + } + + { + name: otp_ctrl_init_fail + uvm_test_seq: otp_ctrl_init_fail_vseq + reseed: 300 + } + { + name: otp_ctrl_background_chks + uvm_test_seq: otp_ctrl_background_chks_vseq + reseed: 10 + } + + { + name: otp_ctrl_parallel_lc_req + uvm_test_seq: otp_ctrl_parallel_lc_req_vseq + run_opts: ["+zero_delays=1"] + } + + { + name: otp_ctrl_parallel_lc_esc + uvm_test_seq: otp_ctrl_parallel_lc_esc_vseq + reseed: 200 + } + + { + name: otp_ctrl_dai_lock + uvm_test_seq: otp_ctrl_dai_lock_vseq + } + + { + name: otp_ctrl_dai_errs + uvm_test_seq: otp_ctrl_dai_errs_vseq + } + + { + name: otp_ctrl_check_fail + uvm_test_seq: otp_ctrl_check_fail_vseq + } + + { + name: otp_ctrl_macro_errs + uvm_test_seq: otp_ctrl_macro_errs_vseq + } + + { + name: otp_ctrl_parallel_key_req + uvm_test_seq: otp_ctrl_parallel_key_req_vseq + } + + { + name: otp_ctrl_regwen + uvm_test_seq: otp_ctrl_regwen_vseq + // This test is to check reg programming is gated when direct_access_regwen=0 + // Thus this test is timing sensitive + run_opts: ["+zero_delays=1"] + } + + { + name: otp_ctrl_test_access + uvm_test_seq: otp_ctrl_test_access_vseq + } + + { + name: "{name}_stress_all_with_rand_reset" + reseed: 100 + } + ] + + // List of regressions. + regressions: [ + { + name: smoke + tests: ["otp_ctrl_smoke"] + } + ] +} diff --git a/src/fuse_ctrl/dv/tb.sv b/src/fuse_ctrl/dv/tb.sv new file mode 100644 index 0000000..e1b2664 --- /dev/null +++ b/src/fuse_ctrl/dv/tb.sv @@ -0,0 +1,238 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +module tb; + // dep packages + import uvm_pkg::*; + import dv_utils_pkg::*; + import otp_ctrl_env_pkg::*; + import otp_ctrl_test_pkg::*; + import otp_ctrl_reg_pkg::*; + import mem_bkdr_util_pkg::mem_bkdr_util; + + // macro includes + `include "uvm_macros.svh" + `include "dv_macros.svh" + + // TB base test ENV_T & CFG_T specification + // + // Specify the parameters for the otp_ctrl_base_test + // This will invoke the UVM registry and link this test type to + // the name 'otp_ctrl_base_test' as a test name passed by UVM_TESTNAME + // + // This is done explicitly only for the prim_pkg::ImplGeneric implementation + // since partner base tests inherit from otp_ctrl_base_test#(CFG_T, ENV_T) and + // specify directly (CFG_T, ENV_T) via the class extension and use a different + // UVM_TESTNAME + if (`PRIM_DEFAULT_IMPL == prim_pkg::ImplGeneric) begin : gen_spec_base_test_params + typedef otp_ctrl_base_test #(.CFG_T(otp_ctrl_env_cfg), + .ENV_T(otp_ctrl_env)) otp_ctrl_base_test_t; + end + + wire clk, rst_n; + wire otp_ctrl_pkg::flash_otp_key_req_t flash_req; + wire otp_ctrl_pkg::flash_otp_key_rsp_t flash_rsp; + wire otp_ctrl_pkg::otbn_otp_key_req_t otbn_req; + wire otp_ctrl_pkg::otbn_otp_key_rsp_t otbn_rsp; + wire otp_ctrl_pkg::sram_otp_key_req_t[NumSramKeyReqSlots-1:0] sram_req; + wire otp_ctrl_pkg::sram_otp_key_rsp_t[NumSramKeyReqSlots-1:0] sram_rsp; + + wire [NUM_MAX_INTERRUPTS-1:0] interrupts; + wire intr_otp_operation_done, intr_otp_error; + + // Output from close-source OTP, not checked in open-source env. + wire otp_ctrl_pkg::otp_ast_req_t ast_req; + wire [7:0] otp_obs_o; + + tlul_pkg::tl_d2h_t prim_tl_o; + + // interfaces + clk_rst_if clk_rst_if(.clk(clk), .rst_n(rst_n)); + pins_if #(NUM_MAX_INTERRUPTS) intr_if(interrupts); + + // lc_otp interfaces + push_pull_if #(.HostDataWidth(LC_PROG_DATA_SIZE), .DeviceDataWidth(1)) + lc_prog_if(.clk(clk), .rst_n(rst_n)); + push_pull_if #(.DeviceDataWidth(SRAM_DATA_SIZE)) + sram_if[NumSramKeyReqSlots](.clk(clk), .rst_n(rst_n)); + push_pull_if #(.DeviceDataWidth(OTBN_DATA_SIZE)) otbn_if(.clk(clk), .rst_n(rst_n)); + push_pull_if #(.DeviceDataWidth(FLASH_DATA_SIZE)) flash_addr_if(.clk(clk), .rst_n(rst_n)); + push_pull_if #(.DeviceDataWidth(FLASH_DATA_SIZE)) flash_data_if(.clk(clk), .rst_n(rst_n)); + + tl_if tl_if(.clk(clk), .rst_n(rst_n)); + tl_if prim_tl_if(.clk(clk), .rst_n(rst_n)); + + otp_ctrl_if otp_ctrl_if(.clk_i(clk), .rst_ni(rst_n)); + + `DV_ALERT_IF_CONNECT() + + // edn_clk, edn_rst_n and edn_if are defined and driven in below macro + `DV_EDN_IF_CONNECT + + assign otp_ctrl_if.lc_prog_req = lc_prog_if.req; + assign otp_ctrl_if.lc_prog_err = lc_prog_if.d_data; + + // Assign to otp_ctrl_if for assertion checks. + assign otp_ctrl_if.lc_prog_ack = lc_prog_if.ack; + assign otp_ctrl_if.flash_acks = flash_data_if.ack; + assign otp_ctrl_if.otbn_ack = otbn_if.ack; + + // This signal probes design's alert request to avoid additional logic for triggering alert and + // disable assertions. + // Alert checkings are done independently in otp_ctrl's scb. + // The correctness of this probed signal is checked in otp_ctrl's scb as well. + assign otp_ctrl_if.alert_reqs = dut.alerts[0] | dut.alerts[1]; + + // connected to interface + wire otp_ext_voltage_h = otp_ctrl_if.ext_voltage_h_io; + + // dut + otp_ctrl dut ( + .clk_i (clk ), + .rst_ni (rst_n ), + // edn + .clk_edn_i (edn_clk ), + .rst_edn_ni (edn_rst_n ), + .edn_o (edn_if[0].req ), + .edn_i ({edn_if[0].ack, edn_if[0].d_data}), + // bus interfaces + .core_tl_i (tl_if.h2d ), + .core_tl_o (tl_if.d2h ), + .prim_tl_i (prim_tl_if.h2d), + .prim_tl_o (prim_tl_if.d2h), + // interrupt + .intr_otp_operation_done_o (intr_otp_operation_done), + .intr_otp_error_o (intr_otp_error), + // alert + .alert_rx_i (alert_rx ), + .alert_tx_o (alert_tx ), + // ast + .obs_ctrl_i (otp_ctrl_if.obs_ctrl_i), + .otp_obs_o (otp_obs_o), + .otp_ast_pwr_seq_o (ast_req), + .otp_ast_pwr_seq_h_i (otp_ctrl_if.otp_ast_pwr_seq_h_i), + // pwrmgr + .pwr_otp_i (otp_ctrl_if.pwr_otp_init_i), + .pwr_otp_o ({otp_ctrl_if.pwr_otp_done_o, otp_ctrl_if.pwr_otp_idle_o}), + // lc + .lc_otp_vendor_test_i (otp_ctrl_if.otp_vendor_test_ctrl_i), + .lc_otp_vendor_test_o (otp_ctrl_if.otp_vendor_test_status_o), + .lc_otp_program_i ({lc_prog_if.req, lc_prog_if.h_data}), + .lc_otp_program_o ({lc_prog_if.d_data, lc_prog_if.ack}), + .lc_creator_seed_sw_rw_en_i (otp_ctrl_if.lc_creator_seed_sw_rw_en_i), + .lc_owner_seed_sw_rw_en_i (otp_ctrl_if.lc_owner_seed_sw_rw_en_i), + .lc_seed_hw_rd_en_i (otp_ctrl_if.lc_seed_hw_rd_en_i), + .lc_dft_en_i (otp_ctrl_if.lc_dft_en_i), + .lc_escalate_en_i (otp_ctrl_if.lc_escalate_en_i), + .lc_check_byp_en_i (otp_ctrl_if.lc_check_byp_en_i), + .otp_lc_data_o (otp_ctrl_if.lc_data_o), + // keymgr + .otp_keymgr_key_o (otp_ctrl_if.keymgr_key_o), + // flash + .flash_otp_key_i (flash_req), + .flash_otp_key_o (flash_rsp), + // sram + .sram_otp_key_i (sram_req), + .sram_otp_key_o (sram_rsp), + // otbn + .otbn_otp_key_i (otbn_req), + .otbn_otp_key_o (otbn_rsp), + + .otp_broadcast_o (otp_ctrl_if.otp_broadcast_o), + .otp_ext_voltage_h_io (otp_ext_voltage_h), + + //scan + .scan_en_i (otp_ctrl_if.scan_en_i), + .scan_rst_ni (otp_ctrl_if.scan_rst_ni), + .scanmode_i (otp_ctrl_if.scanmode_i), + + // Test-related GPIO output + .cio_test_o (otp_ctrl_if.cio_test_o), + .cio_test_en_o (otp_ctrl_if.cio_test_en_o) + ); + + for (genvar i = 0; i < NumSramKeyReqSlots; i++) begin : gen_sram_pull_if + assign sram_req[i] = sram_if[i].req; + assign sram_if[i].ack = sram_rsp[i].ack; + assign sram_if[i].d_data = {sram_rsp[i].key, sram_rsp[i].nonce, sram_rsp[i].seed_valid}; + assign otp_ctrl_if.sram_acks[i] = sram_rsp[i].ack; + initial begin + uvm_config_db#(virtual push_pull_if#(.DeviceDataWidth(SRAM_DATA_SIZE)))::set(null, + $sformatf("*env.m_sram_pull_agent[%0d]*", i), "vif", sram_if[i]); + end + end + assign otbn_req = otbn_if.req; + assign otbn_if.ack = otbn_rsp.ack; + assign otbn_if.d_data = {otbn_rsp.key, otbn_rsp.nonce, otbn_rsp.seed_valid}; + + assign flash_req = {flash_data_if.req, flash_addr_if.req}; + assign flash_data_if.ack = flash_rsp.data_ack; + assign flash_addr_if.ack = flash_rsp.addr_ack; + assign flash_data_if.d_data = {flash_rsp.key, flash_rsp.seed_valid}; + assign flash_addr_if.d_data = {flash_rsp.key, flash_rsp.seed_valid}; + + assign interrupts[OtpOperationDone] = intr_otp_operation_done; + assign interrupts[OtpErr] = intr_otp_error; + + // Instantitate the memory backdoor util instance only for OS implementation + // Proprietary IP will instantiate their own backdoor util + + if (`PRIM_DEFAULT_IMPL == prim_pkg::ImplGeneric) begin : gen_impl_generic + `define MEM_MODULE_PATH \ + tb.dut.u_otp.gen_generic.u_impl_generic.u_prim_ram_1p_adv + + `define MEM_ARRAY_PATH \ + `MEM_MODULE_PATH.u_mem.gen_generic.u_impl_generic.mem + + initial begin : mem_bkdr_util_gen + mem_bkdr_util m_mem_bkdr_util; + m_mem_bkdr_util = new(.name("mem_bkdr_util"), + .path(`DV_STRINGIFY(`MEM_ARRAY_PATH)), + .depth($size(`MEM_ARRAY_PATH)), + .n_bits($bits(`MEM_ARRAY_PATH)), + .err_detection_scheme(mem_bkdr_util_pkg::EccHamming_22_16)); + + uvm_config_db#(mem_bkdr_util)::set(null, "*.env", "mem_bkdr_util", m_mem_bkdr_util); + end : mem_bkdr_util_gen + + `undef MEM_ARRAY_PATH + `undef MEM_MODULE_PATH + end : gen_impl_generic + + // DV forced otp_cmd_i to reach invalid state, thus violate the assertions + for (genvar idx = 0; idx < NumPart; idx++) begin : gen_assertoff_loop + if (is_hw_part_idx(idx)) begin : gen_assertoff + initial begin + $assertoff(0, tb.dut.gen_partitions[idx].gen_buffered.u_part_buf.OtpErrorState_A); + end + end + end + + initial begin + // drive clk and rst_n from clk_if + clk_rst_if.set_active(); + uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "clk_rst_vif", clk_rst_if); + uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", + "clk_rst_vif_otp_ctrl_prim_reg_block", clk_rst_if); + uvm_config_db#(virtual tl_if)::set(null, "*.env.m_tl_agent_otp_ctrl_core_reg_block*", + "vif", tl_if); + uvm_config_db#(virtual tl_if)::set(null, "*.env.m_tl_agent_otp_ctrl_prim_reg_block", + "vif", prim_tl_if); + uvm_config_db#(virtual push_pull_if#(.DeviceDataWidth(OTBN_DATA_SIZE)))::set(null, + "*env.m_otbn_pull_agent*", "vif", otbn_if); + uvm_config_db#(virtual push_pull_if#(.DeviceDataWidth(FLASH_DATA_SIZE)))::set(null, + "*env.m_flash_data_pull_agent*", "vif", flash_data_if); + uvm_config_db#(virtual push_pull_if#(.DeviceDataWidth(FLASH_DATA_SIZE)))::set(null, + "*env.m_flash_addr_pull_agent*", "vif", flash_addr_if); + uvm_config_db#(virtual push_pull_if#(.HostDataWidth(LC_PROG_DATA_SIZE), .DeviceDataWidth(1))):: + set(null, "*env.m_lc_prog_pull_agent*", "vif", lc_prog_if); + + uvm_config_db#(intr_vif)::set(null, "*.env", "intr_vif", intr_if); + + uvm_config_db#(virtual otp_ctrl_if)::set(null, "*.env", "otp_ctrl_vif", otp_ctrl_if); + $timeformat(-12, 0, " ps", 12); + run_test(); + end + +endmodule diff --git a/src/fuse_ctrl/dv/tests/otp_ctrl_base_test.sv b/src/fuse_ctrl/dv/tests/otp_ctrl_base_test.sv new file mode 100644 index 0000000..284c5e0 --- /dev/null +++ b/src/fuse_ctrl/dv/tests/otp_ctrl_base_test.sv @@ -0,0 +1,51 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class otp_ctrl_base_test #( + type CFG_T = otp_ctrl_env_cfg, + type ENV_T = otp_ctrl_env + ) extends cip_base_test #( + .CFG_T(CFG_T), + .ENV_T(ENV_T) + ); + + // A prototype for the registry to associate the parameterized base test + // with the name 'otp_ctrl_base_test' + // + // Register the name 'otp_ctrl_base_test' with the UVM factory to be associated + // with the template base test class parameterized with the default types (see + // declaration. We cannot invoke the standard UVM factory automation macro t + // (uvm_component_param_utils) to register a parameterized test class with the + // factory because the creation of the test by name (via the UVM_TESTNAME + // plusarg) does not work. We expand the contents of the automation macro + // here instead. See the following paper for details: + // https://verificationacademy-news.s3.amazonaws.com/DVCon2016/Papers/ + // dvcon-2016_paramaters-uvm-coverage-and-emulation-take-two-and-call-me-in-the-morning_paper.pdf + typedef uvm_component_registry#(otp_ctrl_base_test#(CFG_T, ENV_T), "otp_ctrl_base_test") type_id; + + // functions to support the component registry above + static function type_id get_type(); + return type_id::get(); + endfunction : get_type + + virtual function uvm_object_wrapper get_object_type(); + return type_id::get(); + endfunction : get_object_type + + const static string type_name = "otp_ctrl_base_test"; + + virtual function string get_type_name(); + return type_name; + endfunction : get_type_name + + `uvm_component_new + + // the base class dv_base_test creates the following instances: + // otp_ctrl_env_cfg: cfg + // otp_ctrl_env: env + + // the base class also looks up UVM_TEST_SEQ plusarg to create and run that seq in + // the run_phase; as such, nothing more needs to be done + +endclass : otp_ctrl_base_test diff --git a/src/fuse_ctrl/dv/tests/otp_ctrl_test.core b/src/fuse_ctrl/dv/tests/otp_ctrl_test.core new file mode 100644 index 0000000..de8cfed --- /dev/null +++ b/src/fuse_ctrl/dv/tests/otp_ctrl_test.core @@ -0,0 +1,19 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:dv:otp_ctrl_test:0.1" +description: "OTP_CTRL DV UVM test" +filesets: + files_dv: + depend: + - lowrisc:dv:otp_ctrl_env + files: + - otp_ctrl_test_pkg.sv + - otp_ctrl_base_test.sv: {is_include_file: true} + file_type: systemVerilogSource + +targets: + default: + filesets: + - files_dv diff --git a/src/fuse_ctrl/dv/tests/otp_ctrl_test_pkg.sv b/src/fuse_ctrl/dv/tests/otp_ctrl_test_pkg.sv new file mode 100644 index 0000000..3d5703d --- /dev/null +++ b/src/fuse_ctrl/dv/tests/otp_ctrl_test_pkg.sv @@ -0,0 +1,22 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +package otp_ctrl_test_pkg; + // dep packages + import uvm_pkg::*; + import cip_base_pkg::*; + import otp_ctrl_env_pkg::*; + + // macro includes + `include "uvm_macros.svh" + `include "dv_macros.svh" + + // local types + + // functions + + // package sources + `include "otp_ctrl_base_test.sv" + +endpackage diff --git a/src/fuse_ctrl/rtl/otp_ctrl.sv b/src/fuse_ctrl/rtl/otp_ctrl.sv new file mode 100644 index 0000000..7561d90 --- /dev/null +++ b/src/fuse_ctrl/rtl/otp_ctrl.sv @@ -0,0 +1,1708 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// OTP Controller top. +// + +`include "caliptra_prim_assert.sv" + +module otp_ctrl + import otp_ctrl_pkg::*; + import otp_ctrl_reg_pkg::*; + import otp_ctrl_part_pkg::*; + import axi_pkg::*; +#( + // Enable asynchronous transitions on alerts. + parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}}, + // Compile time random constants, to be overriden by topgen. + parameter lfsr_seed_t RndCnstLfsrSeed = RndCnstLfsrSeedDefault, + parameter lfsr_perm_t RndCnstLfsrPerm = RndCnstLfsrPermDefault, + parameter scrmbl_key_init_t RndCnstScrmblKeyInit = RndCnstScrmblKeyInitDefault, + // Hexfile file to initialize the OTP macro. + // Note that the hexdump needs to account for ECC. + parameter MemInitFile = "" +) ( + // OTP clock + input clk_i, + input rst_ni, + // EDN clock and interface + logic clk_edn_i, + logic rst_edn_ni, + output edn_pkg::edn_req_t edn_o, + input edn_pkg::edn_rsp_t edn_i, + // Bus Interface + // input tlul_pkg::tl_h2d_t core_tl_i, + // output tlul_pkg::tl_d2h_t core_tl_o, + input axi_struct_pkg::axi_wr_req_t core_axi_wr_req, + output axi_struct_pkg::axi_wr_rsp_t core_axi_wr_rsp, + input axi_struct_pkg::axi_rd_req_t core_axi_rd_req, + output axi_struct_pkg::axi_rd_rsp_t core_axi_rd_rsp, + + // input tlul_pkg::tl_h2d_t prim_tl_i, + // output tlul_pkg::tl_d2h_t prim_tl_o, + input axi_struct_pkg::axi_wr_req_t prim_axi_wr_req, + output axi_struct_pkg::axi_wr_rsp_t prim_axi_wr_rsp, + input axi_struct_pkg::axi_rd_req_t prim_axi_rd_req, + output axi_struct_pkg::axi_rd_rsp_t prim_axi_rd_rsp, + + // Interrupt Requests + output logic intr_otp_operation_done_o, + output logic intr_otp_error_o, + // Alerts + input caliptra_prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i, + output caliptra_prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o, + // Observability to AST + input ast_pkg::ast_obs_ctrl_t obs_ctrl_i, + output logic [7:0] otp_obs_o, + // Macro-specific power sequencing signals to/from AST. + output otp_ast_req_t otp_ast_pwr_seq_o, + input otp_ast_rsp_t otp_ast_pwr_seq_h_i, + // Power manager interface (inputs are synced to OTP clock domain) + input pwrmgr_pkg::pwr_otp_req_t pwr_otp_i, + output pwrmgr_pkg::pwr_otp_rsp_t pwr_otp_o, + // Macro-specific test registers going to lifecycle TAP + input caliptra_ss_lc_otp_vendor_test_req_t caliptra_ss_lc_otp_vendor_test_i, + output caliptra_ss_lc_otp_vendor_test_rsp_t caliptra_ss_lc_otp_vendor_test_o, + // Lifecycle transition command interface + input caliptra_ss_lc_otp_program_req_t caliptra_ss_lc_otp_program_i, + output caliptra_ss_lc_otp_program_rsp_t caliptra_ss_lc_otp_program_o, + // Lifecycle broadcast inputs + // SEC_CM: LC_CTRL.INTERSIG.MUBI + input caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_t caliptra_ss_lc_creator_seed_sw_rw_en_i, + input caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_t caliptra_ss_lc_owner_seed_sw_rw_en_i, + input caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_t caliptra_ss_lc_seed_hw_rd_en_i, + input caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_t caliptra_ss_lc_dft_en_i, + input caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_t caliptra_ss_lc_escalate_en_i, + input caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_t caliptra_ss_lc_check_byp_en_i, + // OTP broadcast outputs + // SEC_CM: TOKEN_VALID.CTRL.MUBI + output otp_caliptra_ss_lc_data_t otp_caliptra_ss_lc_data_o, + output otp_keymgr_key_t otp_keymgr_key_o, + // Scrambling key requests + input flash_otp_key_req_t flash_otp_key_i, + output flash_otp_key_rsp_t flash_otp_key_o, + input sram_otp_key_req_t [NumSramKeyReqSlots-1:0] sram_otp_key_i, + output sram_otp_key_rsp_t [NumSramKeyReqSlots-1:0] sram_otp_key_o, + input otbn_otp_key_req_t otbn_otp_key_i, + output otbn_otp_key_rsp_t otbn_otp_key_o, + // Hardware config bits + output otp_broadcast_t otp_broadcast_o, + // External voltage for OTP + inout wire otp_ext_voltage_h_io, + // Scan + input scan_en_i, + input scan_rst_ni, + input caliptra_prim_mubi_pkg::mubi4_t scanmode_i, + // Test-related GPIO output + output logic [OtpTestVectWidth-1:0] cio_test_o, + output logic [OtpTestVectWidth-1:0] cio_test_en_o +); + + import caliptra_prim_mubi_pkg::*; + import caliptra_prim_util_pkg::vbits; + + // Core AXI2TLUL interface signals + tlul_pkg::tl_h2d_t core_tl_i; + tlul_pkg::tl_d2h_t core_tl_o; + + axi_if core_axi_if( + .clk(clk_i), + .rst_n(rst_ni) + ); + + assign core_axi_if.awaddr = core_axi_wr_req.awaddr; + assign core_axi_if.awburst = core_axi_wr_req.awburst; + assign core_axi_if.awsize = core_axi_wr_req.awsize; + assign core_axi_if.awlen = core_axi_wr_req.awlen; + assign core_axi_if.awuser = core_axi_wr_req.awuser; + assign core_axi_if.awid = core_axi_wr_req.awid; + assign core_axi_if.awlock = core_axi_wr_req.awlock; + assign core_axi_if.awvalid = core_axi_wr_req.awvalid; + assign core_axi_wr_rsp.awready = core_axi_if.awready; + + assign core_axi_if.wdata = core_axi_wr_req.wdata; + assign core_axi_if.wstrb = core_axi_wr_req.wstrb; + assign core_axi_if.wlast = core_axi_wr_req.wlast; + assign core_axi_if.wvalid = core_axi_wr_req.wvalid; + assign core_axi_wr_rsp.wready = core_axi_if.wready; + + assign core_axi_wr_rsp.bresp = core_axi_if.bresp; + assign core_axi_wr_rsp.bid = core_axi_if.bid; + assign core_axi_wr_rsp.bvalid = core_axi_if.bvalid; + assign core_axi_if.bready = core_axi_wr_req.bready; + + assign core_axi_if.araddr = core_axi_rd_req.araddr; + assign core_axi_if.arburst = core_axi_rd_req.arburst; + assign core_axi_if.arsize = core_axi_rd_req.arsize; + assign core_axi_if.arlen = core_axi_rd_req.arlen; + assign core_axi_if.aruser = core_axi_rd_req.aruser; + assign core_axi_if.arid = core_axi_rd_req.arid; + assign core_axi_if.arlock = core_axi_rd_req.arlock; + assign core_axi_if.arvalid = core_axi_rd_req.arvalid; + assign core_axi_rd_rsp.arready = core_axi_if.arready; + + assign core_axi_rd_rsp.rdata = core_axi_if.rdata; + assign core_axi_rd_rsp.rresp = core_axi_if.rresp; + assign core_axi_rd_rsp.rid = core_axi_if.rid; + assign core_axi_rd_rsp.rlast = core_axi_if.rlast; + assign core_axi_rd_rsp.rvalid = core_axi_if.rvalid; + assign core_axi_if.rready = core_axi_rd_req.rready; + + // Core AXI2TLUL instance + axi2tlul #( + .AW (32), + .DW (32), + .UW (32), + .IW (8 ) + ) u_core_axi2tlul ( + .clk (clk_i), + .rst_n (rst_ni), + .s_axi_w_if (core_axi_if.w_sub), + .s_axi_r_if (core_axi_if.r_sub), + .tl_o (core_tl_i), + .tl_i (core_tl_o) + ); + + // Prim AXI2TLUL interface signals + tlul_pkg::tl_h2d_t prim_tl_i; + tlul_pkg::tl_d2h_t prim_tl_o; + + axi_if prim_axi_if( + .clk(clk_i), + .rst_n(rst_ni) + ); + + assign prim_axi_if.awaddr = prim_axi_wr_req.awaddr; + assign prim_axi_if.awburst = prim_axi_wr_req.awburst; + assign prim_axi_if.awsize = prim_axi_wr_req.awsize; + assign prim_axi_if.awlen = prim_axi_wr_req.awlen; + assign prim_axi_if.awuser = prim_axi_wr_req.awuser; + assign prim_axi_if.awid = prim_axi_wr_req.awid; + assign prim_axi_if.awlock = prim_axi_wr_req.awlock; + assign prim_axi_if.awvalid = prim_axi_wr_req.awvalid; + assign prim_axi_wr_rsp.awready = prim_axi_if.awready; + + assign prim_axi_if.wdata = prim_axi_wr_req.wdata; + assign prim_axi_if.wstrb = prim_axi_wr_req.wstrb; + assign prim_axi_if.wlast = prim_axi_wr_req.wlast; + assign prim_axi_if.wvalid = prim_axi_wr_req.wvalid; + assign prim_axi_wr_rsp.wready = prim_axi_if.wready; + + assign prim_axi_wr_rsp.bresp = prim_axi_if.bresp; + assign prim_axi_wr_rsp.bid = prim_axi_if.bid; + assign prim_axi_wr_rsp.bvalid = prim_axi_if.bvalid; + assign prim_axi_if.bready = prim_axi_wr_req.bready; + + assign prim_axi_if.araddr = prim_axi_rd_req.araddr; + assign prim_axi_if.arburst = prim_axi_rd_req.arburst; + assign prim_axi_if.arsize = prim_axi_rd_req.arsize; + assign prim_axi_if.arlen = prim_axi_rd_req.arlen; + assign prim_axi_if.aruser = prim_axi_rd_req.aruser; + assign prim_axi_if.arid = prim_axi_rd_req.arid; + assign prim_axi_if.arlock = prim_axi_rd_req.arlock; + assign prim_axi_if.arvalid = prim_axi_rd_req.arvalid; + assign prim_axi_rd_rsp.arready = prim_axi_if.arready; + + assign prim_axi_rd_rsp.rdata = prim_axi_if.rdata; + assign prim_axi_rd_rsp.rresp = prim_axi_if.rresp; + assign prim_axi_rd_rsp.rid = prim_axi_if.rid; + assign prim_axi_rd_rsp.rlast = prim_axi_if.rlast; + assign prim_axi_rd_rsp.rvalid = prim_axi_if.rvalid; + assign prim_axi_if.rready = prim_axi_rd_req.rready; + + // Prim AXI2TLUL instance + axi2tlul #( + .AW (32), + .DW (32), + .UW (32), + .IW (8 ) + ) u_prim_axi2tlul ( + .clk (clk_i), + .rst_n (rst_ni), + .s_axi_w_if (prim_axi_if.w_sub), + .s_axi_r_if (prim_axi_if.r_sub), + .tl_o (prim_tl_i), + .tl_i (prim_tl_o) + ); + + + + //////////////////////// + // Integration Checks // + //////////////////////// + + // This ensures that we can transfer scrambler data blocks in and out of OTP atomically. + `CALIPTRA_ASSERT_INIT(OtpIfWidth_A, OtpIfWidth == ScrmblBlockWidth) + + // These error codes need to be identical. + `CALIPTRA_ASSERT_INIT(ErrorCodeWidth_A, OtpErrWidth == caliptra_prim_otp_pkg::ErrWidth) + `CALIPTRA_ASSERT_INIT(OtpErrorCode0_A, int'(NoError) == int'(caliptra_prim_otp_pkg::NoError)) + `CALIPTRA_ASSERT_INIT(OtpErrorCode1_A, int'(MacroError) == int'(caliptra_prim_otp_pkg::MacroError)) + `CALIPTRA_ASSERT_INIT(OtpErrorCode2_A, int'(MacroEccCorrError) == int'(caliptra_prim_otp_pkg::MacroEccCorrError)) + `CALIPTRA_ASSERT_INIT(OtpErrorCode3_A, + int'(MacroEccUncorrError) == int'(caliptra_prim_otp_pkg::MacroEccUncorrError)) + `CALIPTRA_ASSERT_INIT(OtpErrorCode4_A, + int'(MacroWriteBlankError) == int'(caliptra_prim_otp_pkg::MacroWriteBlankError)) + + ///////////// + // Regfile // + ///////////// + + // We have one CSR node, one functional TL-UL window and a gate module for that window + logic [2:0] intg_error; + + tlul_pkg::tl_h2d_t tl_win_h2d; + tlul_pkg::tl_d2h_t tl_win_d2h; + + otp_ctrl_reg_pkg::otp_ctrl_core_reg2hw_t reg2hw; + otp_ctrl_reg_pkg::otp_ctrl_core_hw2reg_t hw2reg; + + // SEC_CM: DIRECT_ACCESS.CONFIG.REGWEN, CHECK_TRIGGER.CONFIG.REGWEN, CHECK.CONFIG.REGWEN + otp_ctrl_core_reg_top u_reg_core ( + .clk_i, + .rst_ni, + .tl_i ( core_tl_i ), + .tl_o ( core_tl_o ), + .tl_win_o ( tl_win_h2d ), + .tl_win_i ( tl_win_d2h ), + .reg2hw ( reg2hw ), + .hw2reg ( hw2reg ), + // SEC_CM: BUS.INTEGRITY + .intg_err_o( intg_error[0] ) + ); + + /////////////////////////////////////// + // Life Cycle Signal Synchronization // + /////////////////////////////////////// + + caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_t caliptra_ss_lc_creator_seed_sw_rw_en, caliptra_ss_lc_owner_seed_sw_rw_en, + caliptra_ss_lc_seed_hw_rd_en, caliptra_ss_lc_check_byp_en; + caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_t [2:0] caliptra_ss_lc_dft_en; + // NumAgents + lfsr timer and scrambling datapath. + caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_t [NumAgentsIdx+1:0] caliptra_ss_lc_escalate_en, caliptra_ss_lc_escalate_en_synced; + // Single wire for gating assertions in arbitration and CDC primitives. + logic caliptra_ss_lc_escalate_en_any; + + caliptra_prim_lc_sync #( + .NumCopies(NumAgentsIdx+2) + ) u_prim_caliptra_ss_lc_sync_escalate_en ( + .clk_i, + .rst_ni, + .lc_en_i(caliptra_ss_lc_escalate_en_i), + .lc_en_o(caliptra_ss_lc_escalate_en_synced) + ); + + caliptra_prim_lc_sync #( + .NumCopies(1) + ) u_prim_caliptra_ss_lc_sync_creator_seed_sw_rw_en ( + .clk_i, + .rst_ni, + .lc_en_i(caliptra_ss_lc_creator_seed_sw_rw_en_i), + .lc_en_o({caliptra_ss_lc_creator_seed_sw_rw_en}) + ); + + caliptra_prim_lc_sync #( + .NumCopies(1) + ) u_prim_caliptra_ss_lc_sync_owner_seed_sw_rw_en ( + .clk_i, + .rst_ni, + .lc_en_i(caliptra_ss_lc_owner_seed_sw_rw_en_i), + .lc_en_o({caliptra_ss_lc_owner_seed_sw_rw_en}) + ); + + caliptra_prim_lc_sync #( + .NumCopies(1) + ) u_prim_caliptra_ss_lc_sync_seed_hw_rd_en ( + .clk_i, + .rst_ni, + .lc_en_i(caliptra_ss_lc_seed_hw_rd_en_i), + .lc_en_o({caliptra_ss_lc_seed_hw_rd_en}) + ); + + caliptra_prim_lc_sync #( + .NumCopies(3) + ) u_prim_caliptra_ss_lc_sync_dft_en ( + .clk_i, + .rst_ni, + .lc_en_i(caliptra_ss_lc_dft_en_i), + .lc_en_o(caliptra_ss_lc_dft_en) + ); + + caliptra_prim_lc_sync #( + .NumCopies(1) + ) u_prim_caliptra_ss_lc_sync_check_byp_en ( + .clk_i, + .rst_ni, + .lc_en_i(caliptra_ss_lc_check_byp_en_i), + .lc_en_o({caliptra_ss_lc_check_byp_en}) + ); + + ///////////////////////////////////// + // TL-UL SW partition select logic // + ///////////////////////////////////// + + // The SW partitions share the same TL-UL adapter. + logic tlul_req, tlul_gnt, tlul_rvalid; + logic [SwWindowAddrWidth-1:0] tlul_addr; + logic [1:0] tlul_rerror; + logic [31:0] tlul_rdata; + + import caliptra_prim_mubi_pkg::MuBi4False; + tlul_adapter_sram #( + .SramAw ( SwWindowAddrWidth ), + .SramDw ( 32 ), + .Outstanding ( 1 ), + .ByteAccess ( 0 ), + .ErrOnWrite ( 1 ) // No write accesses allowed here. + ) u_tlul_adapter_sram ( + .clk_i, + .rst_ni, + .en_ifetch_i ( MuBi4False ), + .tl_i ( tl_win_h2d ), + .tl_o ( tl_win_d2h ), + .req_o ( tlul_req ), + .gnt_i ( tlul_gnt ), + .we_o ( ), // unused + .addr_o ( tlul_addr ), + .wdata_o ( ), // unused + .wmask_o ( ), // unused + // SEC_CM: BUS.INTEGRITY + .intg_error_o ( intg_error[1] ), + .rdata_i ( tlul_rdata ), + .rvalid_i ( tlul_rvalid ), + .rerror_i ( tlul_rerror ), + .req_type_o ( ), + .compound_txn_in_progress_o ( ), + .readback_en_i ( MuBi4False ), + .readback_error_o ( ), + .wr_collision_i ( 1'b0 ), + .write_pending_i ( 1'b0 ) + ); + + logic [NumPart-1:0] tlul_part_sel_oh; + for (genvar k = 0; k < NumPart; k++) begin : gen_part_sel + localparam logic [OtpByteAddrWidth:0] PartEnd = (OtpByteAddrWidth+1)'(PartInfo[k].offset) + + (OtpByteAddrWidth+1)'(PartInfo[k].size); + if (PartInfo[k].offset == 0) begin : gen_zero_offset + assign tlul_part_sel_oh[k] = ({1'b0, {tlul_addr, 2'b00}} < PartEnd); + end else begin : gen_nonzero_offset + assign tlul_part_sel_oh[k] = ({tlul_addr, 2'b00} >= PartInfo[k].offset) & + ({1'b0, {tlul_addr, 2'b00}} < PartEnd); + end + end + + `CALIPTRA_ASSERT(PartSelMustBeOnehot_A, $onehot0(tlul_part_sel_oh)) + + logic [NumPartWidth-1:0] tlul_part_idx; + caliptra_prim_arbiter_fixed #( + .N(NumPart), + .EnDataPort(0) + ) u_part_sel_idx ( + .clk_i, + .rst_ni, + .req_i ( tlul_part_sel_oh ), + .data_i ( '{default: '0} ), + .gnt_o ( ), // unused + .idx_o ( tlul_part_idx ), + .valid_o ( ), // unused + .data_o ( ), // unused + .ready_i ( 1'b0 ) + ); + + logic tlul_oob_err_d, tlul_oob_err_q; + logic [NumPart-1:0] part_tlul_req, part_tlul_gnt, part_tlul_rvalid; + logic [SwWindowAddrWidth-1:0] part_tlul_addr; + logic [NumPart-1:0][1:0] part_tlul_rerror; + logic [NumPart-1:0][31:0] part_tlul_rdata; + + always_comb begin : p_tlul_assign + // Send request to the correct partition. + part_tlul_addr = tlul_addr; + part_tlul_req = '0; + tlul_oob_err_d = 1'b0; + if (tlul_req) begin + if (tlul_part_sel_oh != '0) begin + part_tlul_req[tlul_part_idx] = 1'b1; + end else begin + // Error out in the next cycle if address was out of bounds. + tlul_oob_err_d = 1'b1; + end + end + + // aggregate TL-UL responses + tlul_gnt = |part_tlul_gnt | tlul_oob_err_q; + tlul_rvalid = |part_tlul_rvalid | tlul_oob_err_q; + tlul_rerror = '0; + tlul_rdata = '0; + for (int k = 0; k < NumPart; k++) begin + tlul_rerror |= part_tlul_rerror[k]; + tlul_rdata |= part_tlul_rdata[k]; + end + end + + always_ff @(posedge clk_i or negedge rst_ni) begin : p_tlul_reg + if (!rst_ni) begin + tlul_oob_err_q <= 1'b0; + end else begin + tlul_oob_err_q <= tlul_oob_err_d; + end + end + + ////////////////////////////// + // Access Defaults and CSRs // + ////////////////////////////// + + // SEC_CM: ACCESS.CTRL.MUBI + part_access_t [NumPart-1:0] part_access_pre, part_access; + always_comb begin : p_access_control + // Assigns default and extracts named CSR read enables for SW_CFG partitions. + // SEC_CM: PART.MEM.REGREN + part_access_pre = named_part_access_pre(reg2hw); + + // Permanently lock DAI write and read access to the life cycle partition. + // The LC partition can only be read from and written to via the LC controller. + // SEC_CM: LC_PART.MEM.SW_NOACCESS + part_access_pre[LifeCycleIdx].write_lock = MuBi8True; + part_access_pre[LifeCycleIdx].read_lock = MuBi8True; + + // Special partitions for keymgr material only become writable when + // provisioning is enabled. + if (caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_test_false_loose(caliptra_ss_lc_creator_seed_sw_rw_en)) begin + for (int k = 0; k < NumPart; k++) begin + if (PartInfo[k].iskeymgr_creator) begin + part_access_pre[k] = {2{caliptra_prim_mubi_pkg::MuBi8True}}; + end + end + end + if (caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_test_false_loose(caliptra_ss_lc_owner_seed_sw_rw_en)) begin + for (int k = 0; k < NumPart; k++) begin + if (PartInfo[k].iskeymgr_owner) begin + part_access_pre[k] = {2{caliptra_prim_mubi_pkg::MuBi8True}}; + end + end + end + end + + // This prevents the synthesis tool from optimizing the multibit signals. + for (genvar k = 0; k < NumPart; k++) begin : gen_bufs + caliptra_prim_mubi8_sender #( + .AsyncOn(0) + ) u_prim_mubi8_sender_write_lock ( + .clk_i, + .rst_ni, + .mubi_i(part_access_pre[k].write_lock), + .mubi_o(part_access[k].write_lock) + ); + caliptra_prim_mubi8_sender #( + .AsyncOn(0) + ) u_prim_mubi8_sender_read_lock ( + .clk_i, + .rst_ni, + .mubi_i(part_access_pre[k].read_lock), + .mubi_o(part_access[k].read_lock) + ); + end + + ////////////////////// + // DAI-related CSRs // + ////////////////////// + + logic dai_idle; + logic dai_req; + dai_cmd_e dai_cmd; + logic [OtpByteAddrWidth-1:0] dai_addr; + logic [NumDaiWords-1:0][31:0] dai_wdata, dai_rdata; + logic direct_access_regwen_d, direct_access_regwen_q; + + // This is the HWEXT implementation of a RW0C regwen bit. + assign direct_access_regwen_d = (reg2hw.direct_access_regwen.qe && + !reg2hw.direct_access_regwen.q) ? 1'b0 : direct_access_regwen_q; + + // Any write to this register triggers a DAI command. + assign dai_req = reg2hw.direct_access_cmd.digest.qe | + reg2hw.direct_access_cmd.wr.qe | + reg2hw.direct_access_cmd.rd.qe; + + assign dai_cmd = dai_cmd_e'({reg2hw.direct_access_cmd.digest.q, + reg2hw.direct_access_cmd.wr.q, + reg2hw.direct_access_cmd.rd.q}); + + assign dai_addr = reg2hw.direct_access_address.q; + assign dai_wdata = reg2hw.direct_access_wdata; + + // The DAI and the LCI can initiate write transactions, which + // are critical and we must not power down if such transactions + // are pending. Hence, we signal the LCI/DAI idle state to the + // power manager. This signal is flopped here as it has to + // cross a clock boundary to the power manager. + logic dai_prog_idle, lci_prog_idle, otp_idle_d, otp_idle_q; + assign otp_idle_d = lci_prog_idle & dai_prog_idle; + assign pwr_otp_o.otp_idle = otp_idle_q; + + always_ff @(posedge clk_i or negedge rst_ni) begin : p_idle_regwen_regs + if (!rst_ni) begin + otp_idle_q <= 1'b0; + // The regwen bit has to reset to 1 so that CSR accesses are enabled by default. + direct_access_regwen_q <= 1'b1; + end else begin + otp_idle_q <= otp_idle_d; + direct_access_regwen_q <= direct_access_regwen_d; + end + end + + ////////////////////////////////////// + // Ctrl/Status CSRs, Errors, Alerts // + ////////////////////////////////////// + + // Status and error reporting CSRs, error interrupt generation and alerts. + otp_err_e [NumPart+1:0] part_error; + logic [NumAgents-1:0] part_fsm_err; + logic [NumPart+1:0] part_errors_reduced; + logic otp_operation_done, otp_error; + logic fatal_macro_error_d, fatal_macro_error_q; + logic fatal_check_error_d, fatal_check_error_q; + logic fatal_bus_integ_error_d, fatal_bus_integ_error_q; + logic chk_pending, chk_timeout; + logic lfsr_fsm_err, scrmbl_fsm_err; + always_comb begin : p_errors_alerts + // Note: since these are all fatal alert events, we latch them and keep on sending + // alert events via the alert senders. These regs can only be cleared via a system reset. + fatal_macro_error_d = fatal_macro_error_q; + fatal_check_error_d = fatal_check_error_q; + fatal_bus_integ_error_d = fatal_bus_integ_error_q | (|intg_error); + // These are the per-partition buffered escalation inputs + caliptra_ss_lc_escalate_en = caliptra_ss_lc_escalate_en_synced; + // Need a single wire for gating assertions in arbitration and CDC primitives. + caliptra_ss_lc_escalate_en_any = 1'b0; + + // Aggregate all the macro alerts from the partitions + for (int k = 0; k < NumPart; k++) begin + // Filter for critical error codes that should not occur in the field. + fatal_macro_error_d |= part_error[k] == MacroError; + // While uncorrectable ECC errors are always reported, they do not trigger a fatal alert + // event in some partitions like the VENDOR_TEST partition. + if (PartInfo[k].integrity) begin + fatal_macro_error_d |= part_error[k] == MacroEccUncorrError; + end + end + // Aggregate all the macro alerts from the DAI/LCI + for (int k = NumPart; k < NumPart+2; k++) begin + // Filter for critical error codes that should not occur in the field. + fatal_macro_error_d |= part_error[k] inside {MacroError, MacroEccUncorrError}; + end + + // Aggregate all the remaining errors / alerts from the partitions and the DAI/LCI + for (int k = 0; k < NumPart+2; k++) begin + // Set the error bit if the error status of the corresponding partition is nonzero. + // Need to reverse the order here since the field enumeration in hw2reg.status is reversed. + part_errors_reduced[NumPart+1-k] = |part_error[k]; + // Filter for integrity and consistency check failures. + fatal_check_error_d |= part_error[k] inside {CheckFailError, FsmStateError}; + + // If a fatal alert has been observed in any of the partitions/FSMs, + // we locally trigger escalation within OTP, which moves all FSMs + // to a terminal error state. + if (fatal_macro_error_q || fatal_check_error_q) begin + caliptra_ss_lc_escalate_en[k] = caliptra_ss_lc_ctrl_pkg::On; + end + if (caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_test_true_strict(caliptra_ss_lc_escalate_en[k])) begin + caliptra_ss_lc_escalate_en_any = 1'b1; + end + end + + // Errors from other non-partition FSMs. + fatal_check_error_d |= chk_timeout | + lfsr_fsm_err | + scrmbl_fsm_err | + (|part_fsm_err); + end + + // If we got an error, we trigger an interrupt. + logic [$bits(part_errors_reduced)+4-1:0] interrupt_triggers_d, interrupt_triggers_q; + + // This makes sure that interrupts are not sticky. + assign interrupt_triggers_d = { + part_errors_reduced, + chk_timeout, + lfsr_fsm_err, + scrmbl_fsm_err, + |part_fsm_err + }; + + assign otp_error = |(interrupt_triggers_d & ~interrupt_triggers_q); + + always_ff @(posedge clk_i or negedge rst_ni) begin : p_alert_regs + if (!rst_ni) begin + fatal_macro_error_q <= '0; + fatal_check_error_q <= '0; + fatal_bus_integ_error_q <= '0; + interrupt_triggers_q <= '0; + end else begin + fatal_macro_error_q <= fatal_macro_error_d; + fatal_check_error_q <= fatal_check_error_d; + fatal_bus_integ_error_q <= fatal_bus_integ_error_d; + interrupt_triggers_q <= interrupt_triggers_d; + end + end + + // CSR assignments are done in one combo process so that we can use + // the parameterized digest_assign task below without multiple driver issues. + logic unused_part_digest; + logic [NumPart-1:0][ScrmblBlockWidth-1:0] part_digest; + logic intr_state_otp_operation_done_d, intr_state_otp_operation_done_de; + logic intr_state_otp_error_d, intr_state_otp_error_de; + always_comb begin : p_csr_assign + // Not all partition digests are consumed, and assigning them to an unused_* signal in the + // function below does not seem to work for some linters. + unused_part_digest = ^part_digest; + // Assign named CSRs (like digests). + hw2reg = named_reg_assign(part_digest); + // DAI related CSRs + hw2reg.direct_access_rdata = dai_rdata; + // ANDing this state with dai_idle write-protects all DAI regs during pending operations. + hw2reg.direct_access_regwen.d = direct_access_regwen_q & dai_idle; + // Assign these to the status register. + hw2reg.status = {part_errors_reduced, + chk_timeout, + lfsr_fsm_err, + scrmbl_fsm_err, + part_fsm_err[KdiIdx], + fatal_bus_integ_error_q, + dai_idle, + chk_pending}; + // Error code registers. + hw2reg.err_code = part_error; + // Interrupt signals + hw2reg.intr_state.otp_operation_done.de = intr_state_otp_operation_done_de; + hw2reg.intr_state.otp_operation_done.d = intr_state_otp_operation_done_d; + hw2reg.intr_state.otp_error.de = intr_state_otp_error_de; + hw2reg.intr_state.otp_error.d = intr_state_otp_error_d; +end + + + ////////////////////////////////// + // Interrupts and Alert Senders // + ////////////////////////////////// + + caliptra_prim_intr_hw #( + .Width(1) + ) u_intr_operation_done ( + .clk_i, + .rst_ni, + .event_intr_i ( otp_operation_done ), + .reg2hw_intr_enable_q_i ( reg2hw.intr_enable.otp_operation_done.q ), + .reg2hw_intr_test_q_i ( reg2hw.intr_test.otp_operation_done.q ), + .reg2hw_intr_test_qe_i ( reg2hw.intr_test.otp_operation_done.qe ), + .reg2hw_intr_state_q_i ( reg2hw.intr_state.otp_operation_done.q ), + .hw2reg_intr_state_de_o ( intr_state_otp_operation_done_de ), + .hw2reg_intr_state_d_o ( intr_state_otp_operation_done_d ), + .intr_o ( intr_otp_operation_done_o ) + ); + + caliptra_prim_intr_hw #( + .Width(1) + ) u_intr_error ( + .clk_i, + .rst_ni, + .event_intr_i ( otp_error ), + .reg2hw_intr_enable_q_i ( reg2hw.intr_enable.otp_error.q ), + .reg2hw_intr_test_q_i ( reg2hw.intr_test.otp_error.q ), + .reg2hw_intr_test_qe_i ( reg2hw.intr_test.otp_error.qe ), + .reg2hw_intr_state_q_i ( reg2hw.intr_state.otp_error.q ), + .hw2reg_intr_state_de_o ( intr_state_otp_error_de ), + .hw2reg_intr_state_d_o ( intr_state_otp_error_d ), + .intr_o ( intr_otp_error_o ) + ); + + logic [NumAlerts-1:0] alerts; + logic [NumAlerts-1:0] alert_test; + logic fatal_prim_otp_alert, recov_prim_otp_alert; + + assign alerts = { + recov_prim_otp_alert, + fatal_prim_otp_alert, + fatal_bus_integ_error_q, + fatal_check_error_q, + fatal_macro_error_q + }; + + assign alert_test = { + reg2hw.alert_test.recov_prim_otp_alert.q & + reg2hw.alert_test.recov_prim_otp_alert.qe, + reg2hw.alert_test.fatal_prim_otp_alert.q & + reg2hw.alert_test.fatal_prim_otp_alert.qe, + reg2hw.alert_test.fatal_bus_integ_error.q & + reg2hw.alert_test.fatal_bus_integ_error.qe, + reg2hw.alert_test.fatal_check_error.q & + reg2hw.alert_test.fatal_check_error.qe, + reg2hw.alert_test.fatal_macro_error.q & + reg2hw.alert_test.fatal_macro_error.qe + }; + + localparam logic [NumAlerts-1:0] AlertIsFatal = { + 1'b0, // recov_prim_otp_alert + 1'b1, // fatal_prim_otp_alert + 1'b1, // fatal_bus_integ_error_q + 1'b1, // fatal_check_error_q + 1'b1 // fatal_macro_error_q + }; + + for (genvar k = 0; k < NumAlerts; k++) begin : gen_alert_tx + caliptra_prim_alert_sender #( + .AsyncOn(AlertAsyncOn[k]), + .IsFatal(AlertIsFatal[k]) + ) u_prim_alert_sender ( + .clk_i, + .rst_ni, + .alert_test_i ( alert_test[k] ), + .alert_req_i ( alerts[k] ), + .alert_ack_o ( ), + .alert_state_o ( ), + .alert_rx_i ( alert_rx_i[k] ), + .alert_tx_o ( alert_tx_o[k] ) + ); + end + + //////////////////////////////// + // LFSR Timer and CSR mapping // + //////////////////////////////// + + logic integ_chk_trig, cnsty_chk_trig; + logic [NumPart-1:0] integ_chk_req, integ_chk_ack; + logic [NumPart-1:0] cnsty_chk_req, cnsty_chk_ack; + logic lfsr_edn_req, lfsr_edn_ack; + logic [EdnDataWidth-1:0] edn_data; + + assign integ_chk_trig = reg2hw.check_trigger.integrity.q & + reg2hw.check_trigger.integrity.qe; + assign cnsty_chk_trig = reg2hw.check_trigger.consistency.q & + reg2hw.check_trigger.consistency.qe; + + // SEC_CM: PART.DATA_REG.BKGN_CHK + otp_ctrl_lfsr_timer #( + .RndCnstLfsrSeed(RndCnstLfsrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm) + ) u_otp_ctrl_lfsr_timer ( + .clk_i, + .rst_ni, + .edn_req_o ( lfsr_edn_req ), + .edn_ack_i ( lfsr_edn_ack ), + .edn_data_i ( edn_data ), + // We can enable the timer once OTP has initialized. + // Note that this is only the initial release that gets + // the timer FSM into an operational state. + // Whether or not the timers / background checks are + // activated depends on the CSR configuration (by default + // they are switched off). + .timer_en_i ( pwr_otp_o.otp_done ), + // This idle signal is the same that is output to the power + // manager, and indicates whether there is an ongoing OTP programming + // operation. It is used to pause the consistency check timeout + // counter in order to prevent spurious timeouts (OTP programming + // operations are very slow compared to readout operations and can + // hence interfere with the timeout mechanism). + .otp_prog_busy_i ( ~otp_idle_d ), + .integ_chk_trig_i ( integ_chk_trig ), + .cnsty_chk_trig_i ( cnsty_chk_trig ), + .chk_pending_o ( chk_pending ), + .timeout_i ( reg2hw.check_timeout.q ), + .integ_period_msk_i ( reg2hw.integrity_check_period.q ), + .cnsty_period_msk_i ( reg2hw.consistency_check_period.q ), + .integ_chk_req_o ( integ_chk_req ), + .cnsty_chk_req_o ( cnsty_chk_req ), + .integ_chk_ack_i ( integ_chk_ack ), + .cnsty_chk_ack_i ( cnsty_chk_ack ), + .escalate_en_i ( caliptra_ss_lc_escalate_en[NumAgents] ), + .chk_timeout_o ( chk_timeout ), + .fsm_err_o ( lfsr_fsm_err ) + ); + + /////////////////////////////////////// + // EDN Arbitration, Request and Sync // + /////////////////////////////////////// + + // Both the key derivation and LFSR reseeding are low bandwidth, + // hence they can share the same EDN interface. + logic edn_req, edn_ack; + logic key_edn_req, key_edn_ack; + caliptra_prim_arbiter_tree #( + .N(2), + .EnDataPort(0) + ) u_edn_arb ( + .clk_i, + .rst_ni, + .req_chk_i ( ~caliptra_ss_lc_escalate_en_any ), + .req_i ( {lfsr_edn_req, key_edn_req} ), + .data_i ( '{default: '0} ), + .gnt_o ( {lfsr_edn_ack, key_edn_ack} ), + .idx_o ( ), // unused + .valid_o ( edn_req ), + .data_o ( ), // unused + .ready_i ( edn_ack ) + ); + + // This synchronizes the data coming from EDN and stacks the + // 32bit EDN words to achieve an internal entropy width of 64bit. + caliptra_prim_edn_req #( + .OutWidth(EdnDataWidth) + ) u_prim_edn_req ( + .clk_i, + .rst_ni, + .req_chk_i ( ~caliptra_ss_lc_escalate_en_any ), + .req_i ( edn_req ), + .ack_o ( edn_ack ), + .data_o ( edn_data ), + .fips_o ( ), // unused + .err_o ( ), // unused + .clk_edn_i, + .rst_edn_ni, + .edn_o, + .edn_i + ); + + /////////////////////////////// + // OTP Macro and Arbitration // + /////////////////////////////// + + typedef struct packed { + caliptra_prim_otp_pkg::cmd_e cmd; + logic [OtpSizeWidth-1:0] size; // Number of native words to write. + logic [OtpIfWidth-1:0] wdata; + logic [OtpAddrWidth-1:0] addr; // Halfword address. + } otp_bundle_t; + + logic [NumAgents-1:0] part_otp_arb_req, part_otp_arb_gnt; + otp_bundle_t part_otp_arb_bundle [NumAgents]; + logic otp_arb_valid, otp_arb_ready; + logic otp_prim_valid, otp_prim_ready; + logic otp_rsp_fifo_valid, otp_rsp_fifo_ready; + logic [vbits(NumAgents)-1:0] otp_arb_idx; + otp_bundle_t otp_arb_bundle; + + // The OTP interface is arbitrated on a per-cycle basis, meaning that back-to-back + // transactions can be completely independent. + caliptra_prim_arbiter_tree #( + .N(NumAgents), + .DW($bits(otp_bundle_t)) + ) u_otp_arb ( + .clk_i, + .rst_ni, + .req_chk_i ( ~caliptra_ss_lc_escalate_en_any ), + .req_i ( part_otp_arb_req ), + .data_i ( part_otp_arb_bundle ), + .gnt_o ( part_otp_arb_gnt ), + .idx_o ( otp_arb_idx ), + .valid_o ( otp_arb_valid ), + .data_o ( otp_arb_bundle ), + .ready_i ( otp_arb_ready ) + ); + + // Don't issue more transactions than what the rsp_fifo can keep track of. + assign otp_arb_ready = otp_prim_ready & otp_rsp_fifo_ready; + assign otp_prim_valid = otp_arb_valid & otp_rsp_fifo_ready; + assign otp_rsp_fifo_valid = otp_prim_ready & otp_prim_valid; + + caliptra_prim_otp_pkg::err_e part_otp_err; + logic [OtpIfWidth-1:0] part_otp_rdata; + logic otp_rvalid; + tlul_pkg::tl_h2d_t prim_tl_h2d_gated; + tlul_pkg::tl_d2h_t prim_tl_d2h_gated; + + // Life cycle qualification of TL-UL test interface. + // SEC_CM: TEST.BUS.LC_GATED + // SEC_CM: TEST_TL_LC_GATE.FSM.SPARSE + tlul_caliptra_ss_lc_gate #( + .NumGatesPerDirection(2) + ) u_tlul_caliptra_ss_lc_gate ( + .clk_i, + .rst_ni, + .tl_h2d_i(prim_tl_i), + .tl_d2h_o(prim_tl_o), + .tl_h2d_o(prim_tl_h2d_gated), + .tl_d2h_i(prim_tl_d2h_gated), + .lc_en_i (caliptra_ss_lc_dft_en[0]), + .flush_req_i('0), + .flush_ack_o(), + .resp_pending_o(), + .err_o (intg_error[2]) + ); + + // Test-related GPIOs. + // SEC_CM: TEST.BUS.LC_GATED + logic [OtpTestVectWidth-1:0] otp_test_vect; + assign cio_test_o = (caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_test_true_strict(caliptra_ss_lc_dft_en[1])) ? + otp_test_vect : '0; + assign cio_test_en_o = (caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_test_true_strict(caliptra_ss_lc_dft_en[2])) ? + {OtpTestVectWidth{1'b1}} : '0; + + // SEC_CM: MACRO.MEM.CM, MACRO.MEM.INTEGRITY + prim_generic_otp #( + .Width ( OtpWidth ), + .Depth ( OtpDepth ), + .SizeWidth ( OtpSizeWidth ), + .PwrSeqWidth ( OtpPwrSeqWidth ), + .TestCtrlWidth ( OtpTestCtrlWidth ), + .TestStatusWidth ( OtpTestStatusWidth ), + .TestVectWidth ( OtpTestVectWidth ), + .MemInitFile ( MemInitFile ), + .VendorTestOffset ( VendorTestOffset ), + .VendorTestSize ( VendorTestSize ) + ) u_otp ( + .clk_i, + .rst_ni, + // Observability controls to/from AST + .obs_ctrl_i, + .otp_obs_o, + // Power sequencing signals to/from AST + .pwr_seq_o ( otp_ast_pwr_seq_o.pwr_seq ), + .pwr_seq_h_i ( otp_ast_pwr_seq_h_i.pwr_seq_h ), + .ext_voltage_io ( otp_ext_voltage_h_io ), + // Test interface + .test_ctrl_i ( caliptra_ss_lc_otp_vendor_test_i.ctrl ), + .test_status_o ( caliptra_ss_lc_otp_vendor_test_o.status ), + .test_vect_o ( otp_test_vect ), + .test_tl_i ( prim_tl_h2d_gated ), + .test_tl_o ( prim_tl_d2h_gated ), + // Other DFT signals + .scan_en_i, + .scan_rst_ni, + .scanmode_i, + // Alerts + .fatal_alert_o ( fatal_prim_otp_alert ), + .recov_alert_o ( recov_prim_otp_alert ), + // Read / Write command interface + .ready_o ( otp_prim_ready ), + .valid_i ( otp_prim_valid ), + .cmd_i ( otp_arb_bundle.cmd ), + .size_i ( otp_arb_bundle.size ), + .addr_i ( otp_arb_bundle.addr ), + .wdata_i ( otp_arb_bundle.wdata ), + // Read data out + .valid_o ( otp_rvalid ), + .rdata_o ( part_otp_rdata ), + .err_o ( part_otp_err ) + ); + + logic otp_fifo_valid; + logic [vbits(NumAgents)-1:0] otp_part_idx; + logic [NumAgents-1:0] part_otp_rvalid; + + // We can have up to two OTP commands in flight, hence we size this to be 2 deep. + // The partitions can unconditionally sink requested data. + caliptra_prim_fifo_sync #( + .Width(vbits(NumAgents)), + .Depth(2) + ) u_otp_rsp_fifo ( + .clk_i, + .rst_ni, + .clr_i ( 1'b0 ), + .wvalid_i ( otp_rsp_fifo_valid ), + .wready_o ( otp_rsp_fifo_ready ), + .wdata_i ( otp_arb_idx ), + .rvalid_o ( otp_fifo_valid ), + .rready_i ( otp_rvalid ), + .rdata_o ( otp_part_idx ), + .depth_o ( ), + .full_o ( ), + .err_o ( ) + ); + + // Steer response back to the partition where this request originated. + always_comb begin : p_rvalid + part_otp_rvalid = '0; + part_otp_rvalid[otp_part_idx] = otp_rvalid & otp_fifo_valid; + end + + // Note that this must be true by construction. + `CALIPTRA_ASSERT(OtpRespFifoUnderflow_A, otp_rvalid |-> otp_fifo_valid) + + ///////////////////////////////////////// + // Scrambling Datapath and Arbitration // + ///////////////////////////////////////// + + // Note: as opposed to the OTP arbitration above, we do not perform cycle-wise arbitration, but + // transaction-wise arbitration. This is implemented using a RR arbiter that acts as a mutex. + // I.e., each agent (e.g. the DAI or a partition) can request a lock on the mutex. Once granted, + // the partition can keep the lock as long as needed for the transaction to complete. The + // partition must yield its lock by deasserting the request signal for the arbiter to proceed. + // Since this scheme does not have built-in preemtion, it must be ensured that the agents + // eventually release their locks for this to be fair. + // + // See also https://docs.opentitan.org/hw/ip/otp_ctrl/doc/index.html#block-diagram for details. + typedef struct packed { + otp_scrmbl_cmd_e cmd; + digest_mode_e mode; + logic [ConstSelWidth-1:0] sel; + logic [ScrmblBlockWidth-1:0] data; + logic valid; + } scrmbl_bundle_t; + + logic [NumAgents-1:0] part_scrmbl_mtx_req, part_scrmbl_mtx_gnt; + scrmbl_bundle_t part_scrmbl_req_bundle [NumAgents]; + scrmbl_bundle_t scrmbl_req_bundle; + logic [vbits(NumAgents)-1:0] scrmbl_mtx_idx; + logic scrmbl_mtx_valid; + + // Note that arbiter decisions do not change when backpressured. + // Hence, the idx_o signal is guaranteed to remain stable until ack'ed. + caliptra_prim_arbiter_tree #( + .N(NumAgents), + .DW($bits(scrmbl_bundle_t)) + ) u_scrmbl_mtx ( + .clk_i, + .rst_ni, + .req_chk_i ( 1'b0 ), // REQ is allowed to go low again without ACK even + // during normal operation. + .req_i ( part_scrmbl_mtx_req ), + .data_i ( part_scrmbl_req_bundle ), + .gnt_o ( ), + .idx_o ( scrmbl_mtx_idx ), + .valid_o ( scrmbl_mtx_valid ), + .data_o ( scrmbl_req_bundle ), + .ready_i ( 1'b0 ) + ); + + // Since the ready_i signal of the arbiter is statically set to 1'b0 above, we are always in a + // "backpressure" situation, where the RR arbiter will automatically advance the internal RR state + // to give the current winner max priority in subsequent cycles in order to keep the decision + // stable. Rearbitration occurs once the winning agent deasserts its request. + always_comb begin : p_mutex + part_scrmbl_mtx_gnt = '0; + part_scrmbl_mtx_gnt[scrmbl_mtx_idx] = scrmbl_mtx_valid; + end + + logic [ScrmblBlockWidth-1:0] part_scrmbl_rsp_data; + logic scrmbl_arb_req_ready, scrmbl_arb_rsp_valid; + logic [NumAgents-1:0] part_scrmbl_req_ready, part_scrmbl_rsp_valid; + + // SEC_CM: SECRET.MEM.SCRAMBLE + // SEC_CM: PART.MEM.DIGEST + otp_ctrl_scrmbl u_otp_ctrl_scrmbl ( + .clk_i, + .rst_ni, + .cmd_i ( scrmbl_req_bundle.cmd ), + .mode_i ( scrmbl_req_bundle.mode ), + .sel_i ( scrmbl_req_bundle.sel ), + .data_i ( scrmbl_req_bundle.data ), + .valid_i ( scrmbl_req_bundle.valid ), + .ready_o ( scrmbl_arb_req_ready ), + .data_o ( part_scrmbl_rsp_data ), + .valid_o ( scrmbl_arb_rsp_valid ), + .escalate_en_i ( caliptra_ss_lc_escalate_en[NumAgents+1] ), + .fsm_err_o ( scrmbl_fsm_err ) + ); + + // steer back responses + always_comb begin : p_scmrbl_resp + part_scrmbl_req_ready = '0; + part_scrmbl_rsp_valid = '0; + part_scrmbl_req_ready[scrmbl_mtx_idx] = scrmbl_arb_req_ready; + part_scrmbl_rsp_valid[scrmbl_mtx_idx] = scrmbl_arb_rsp_valid; + end + + ///////////////////////////// + // Direct Access Interface // + ///////////////////////////// + + logic part_init_req; + logic [NumPart-1:0] part_init_done; + part_access_t [NumPart-1:0] part_access_dai; + + // The init request comes from the power manager, which lives in the AON clock domain. + logic pwr_otp_req_synced; + caliptra_prim_flop_2sync #( + .Width(1) + ) u_otp_init_sync ( + .clk_i, + .rst_ni, + .d_i ( pwr_otp_i.otp_init ), + .q_o ( pwr_otp_req_synced ) + ); + + // Register this signal as it has to cross a clock boundary. + logic pwr_otp_rsp_d, pwr_otp_rsp_q; + assign pwr_otp_o.otp_done = pwr_otp_rsp_q; + + always_ff @(posedge clk_i or negedge rst_ni) begin : p_init_reg + if (!rst_ni) begin + pwr_otp_rsp_q <= 1'b0; + end else begin + pwr_otp_rsp_q <= pwr_otp_rsp_d; + end + end + + otp_ctrl_dai u_otp_ctrl_dai ( + .clk_i, + .rst_ni, + .init_req_i ( pwr_otp_req_synced ), + .init_done_o ( pwr_otp_rsp_d ), + .part_init_req_o ( part_init_req ), + .part_init_done_i ( part_init_done ), + .escalate_en_i ( caliptra_ss_lc_escalate_en[DaiIdx] ), + .error_o ( part_error[DaiIdx] ), + .fsm_err_o ( part_fsm_err[DaiIdx] ), + .part_access_i ( part_access_dai ), + .dai_addr_i ( dai_addr ), + .dai_cmd_i ( dai_cmd ), + .dai_req_i ( dai_req ), + .dai_wdata_i ( dai_wdata ), + .dai_idle_o ( dai_idle ), + .dai_prog_idle_o ( dai_prog_idle ), + .dai_cmd_done_o ( otp_operation_done ), + .dai_rdata_o ( dai_rdata ), + .otp_req_o ( part_otp_arb_req[DaiIdx] ), + .otp_cmd_o ( part_otp_arb_bundle[DaiIdx].cmd ), + .otp_size_o ( part_otp_arb_bundle[DaiIdx].size ), + .otp_wdata_o ( part_otp_arb_bundle[DaiIdx].wdata ), + .otp_addr_o ( part_otp_arb_bundle[DaiIdx].addr ), + .otp_gnt_i ( part_otp_arb_gnt[DaiIdx] ), + .otp_rvalid_i ( part_otp_rvalid[DaiIdx] ), + .otp_rdata_i ( part_otp_rdata ), + .otp_err_i ( part_otp_err ), + .scrmbl_mtx_req_o ( part_scrmbl_mtx_req[DaiIdx] ), + .scrmbl_mtx_gnt_i ( part_scrmbl_mtx_gnt[DaiIdx] ), + .scrmbl_cmd_o ( part_scrmbl_req_bundle[DaiIdx].cmd ), + .scrmbl_mode_o ( part_scrmbl_req_bundle[DaiIdx].mode ), + .scrmbl_sel_o ( part_scrmbl_req_bundle[DaiIdx].sel ), + .scrmbl_data_o ( part_scrmbl_req_bundle[DaiIdx].data ), + .scrmbl_valid_o ( part_scrmbl_req_bundle[DaiIdx].valid ), + .scrmbl_ready_i ( part_scrmbl_req_ready[DaiIdx] ), + .scrmbl_valid_i ( part_scrmbl_rsp_valid[DaiIdx] ), + .scrmbl_data_i ( part_scrmbl_rsp_data ) + ); + + //////////////////////////////////// + // Lifecycle Transition Interface // + //////////////////////////////////// + + logic [PartInfo[LifeCycleIdx].size-1:0][7:0] caliptra_ss_lc_otp_program_data; + assign caliptra_ss_lc_otp_program_data[LcStateOffset-LifeCycleOffset +: LcStateSize] = + caliptra_ss_lc_otp_program_i.state; + assign caliptra_ss_lc_otp_program_data[LcTransitionCntOffset-LifeCycleOffset +: LcTransitionCntSize] = + caliptra_ss_lc_otp_program_i.count; + + otp_ctrl_lci #( + .Info(PartInfo[LifeCycleIdx]) + ) u_otp_ctrl_lci ( + .clk_i, + .rst_ni, + .lci_en_i ( pwr_otp_o.otp_done ), + .escalate_en_i ( caliptra_ss_lc_escalate_en[LciIdx] ), + .error_o ( part_error[LciIdx] ), + .fsm_err_o ( part_fsm_err[LciIdx] ), + .lci_prog_idle_o ( lci_prog_idle ), + .caliptra_ss_lc_req_i ( caliptra_ss_lc_otp_program_i.req ), + .caliptra_ss_lc_data_i ( caliptra_ss_lc_otp_program_data ), + .caliptra_ss_lc_ack_o ( caliptra_ss_lc_otp_program_o.ack ), + .caliptra_ss_lc_err_o ( caliptra_ss_lc_otp_program_o.err ), + .otp_req_o ( part_otp_arb_req[LciIdx] ), + .otp_cmd_o ( part_otp_arb_bundle[LciIdx].cmd ), + .otp_size_o ( part_otp_arb_bundle[LciIdx].size ), + .otp_wdata_o ( part_otp_arb_bundle[LciIdx].wdata ), + .otp_addr_o ( part_otp_arb_bundle[LciIdx].addr ), + .otp_gnt_i ( part_otp_arb_gnt[LciIdx] ), + .otp_rvalid_i ( part_otp_rvalid[LciIdx] ), + .otp_rdata_i ( part_otp_rdata ), + .otp_err_i ( part_otp_err ) + ); + + // Tie off unused connections. + assign part_scrmbl_mtx_req[LciIdx] = '0; + assign part_scrmbl_req_bundle[LciIdx] = '0; + + // This stops lint from complaining about unused signals. + logic unused_lci_scrmbl_sigs; + assign unused_lci_scrmbl_sigs = ^{part_scrmbl_mtx_gnt[LciIdx], + part_scrmbl_req_ready[LciIdx], + part_scrmbl_rsp_valid[LciIdx]}; + + //////////////////////////////////// + // Key Derivation Interface (KDI) // + //////////////////////////////////// + + logic scrmbl_key_seed_valid; + logic [SramKeySeedWidth-1:0] sram_data_key_seed; + logic [FlashKeySeedWidth-1:0] flash_data_key_seed, flash_addr_key_seed; + + otp_ctrl_kdi #( + .RndCnstScrmblKeyInit(RndCnstScrmblKeyInit) + ) u_otp_ctrl_kdi ( + .clk_i, + .rst_ni, + .kdi_en_i ( pwr_otp_o.otp_done ), + .escalate_en_i ( caliptra_ss_lc_escalate_en[KdiIdx] ), + .fsm_err_o ( part_fsm_err[KdiIdx] ), + .scrmbl_key_seed_valid_i ( scrmbl_key_seed_valid ), + .flash_data_key_seed_i ( flash_data_key_seed ), + .flash_addr_key_seed_i ( flash_addr_key_seed ), + .sram_data_key_seed_i ( sram_data_key_seed ), + .edn_req_o ( key_edn_req ), + .edn_ack_i ( key_edn_ack ), + .edn_data_i ( edn_data ), + .flash_otp_key_i, + .flash_otp_key_o, + .sram_otp_key_i, + .sram_otp_key_o, + .otbn_otp_key_i, + .otbn_otp_key_o, + .scrmbl_mtx_req_o ( part_scrmbl_mtx_req[KdiIdx] ), + .scrmbl_mtx_gnt_i ( part_scrmbl_mtx_gnt[KdiIdx] ), + .scrmbl_cmd_o ( part_scrmbl_req_bundle[KdiIdx].cmd ), + .scrmbl_mode_o ( part_scrmbl_req_bundle[KdiIdx].mode ), + .scrmbl_sel_o ( part_scrmbl_req_bundle[KdiIdx].sel ), + .scrmbl_data_o ( part_scrmbl_req_bundle[KdiIdx].data ), + .scrmbl_valid_o ( part_scrmbl_req_bundle[KdiIdx].valid ), + .scrmbl_ready_i ( part_scrmbl_req_ready[KdiIdx] ), + .scrmbl_valid_i ( part_scrmbl_rsp_valid[KdiIdx] ), + .scrmbl_data_i ( part_scrmbl_rsp_data ) + ); + + // Tie off OTP bus access, since this is not needed. + assign part_otp_arb_req[KdiIdx] = 1'b0; + assign part_otp_arb_bundle[KdiIdx] = '0; + + // This stops lint from complaining about unused signals. + logic unused_kdi_otp_sigs; + assign unused_kdi_otp_sigs = ^{part_otp_arb_gnt[KdiIdx], + part_otp_rvalid[KdiIdx]}; + + ///////////////////////// + // Partition Instances // + ///////////////////////// + + logic [$bits(PartInvDefault)/8-1:0][7:0] part_buf_data; + + for (genvar k = 0; k < NumPart; k ++) begin : gen_partitions + //////////////////////////////////////////////////////////////////////////////////////////////// + if (PartInfo[k].variant == Unbuffered) begin : gen_unbuffered + otp_ctrl_part_unbuf #( + .Info(PartInfo[k]) + ) u_part_unbuf ( + .clk_i, + .rst_ni, + .init_req_i ( part_init_req ), + .init_done_o ( part_init_done[k] ), + .escalate_en_i ( caliptra_ss_lc_escalate_en[k] ), + .error_o ( part_error[k] ), + .fsm_err_o ( part_fsm_err[k] ), + .access_i ( part_access[k] ), + .access_o ( part_access_dai[k] ), + .digest_o ( part_digest[k] ), + .tlul_req_i ( part_tlul_req[k] ), + .tlul_gnt_o ( part_tlul_gnt[k] ), + .tlul_addr_i ( part_tlul_addr ), + .tlul_rerror_o ( part_tlul_rerror[k] ), + .tlul_rvalid_o ( part_tlul_rvalid[k] ), + .tlul_rdata_o ( part_tlul_rdata[k] ), + .otp_req_o ( part_otp_arb_req[k] ), + .otp_cmd_o ( part_otp_arb_bundle[k].cmd ), + .otp_size_o ( part_otp_arb_bundle[k].size ), + .otp_wdata_o ( part_otp_arb_bundle[k].wdata ), + .otp_addr_o ( part_otp_arb_bundle[k].addr ), + .otp_gnt_i ( part_otp_arb_gnt[k] ), + .otp_rvalid_i ( part_otp_rvalid[k] ), + .otp_rdata_i ( part_otp_rdata ), + .otp_err_i ( part_otp_err ) + ); + + // Tie off unused connections. + assign part_scrmbl_mtx_req[k] = '0; + assign part_scrmbl_req_bundle[k] = '0; + // These checks do not exist in this partition type, + // so we always acknowledge the request. + assign integ_chk_ack[k] = 1'b1; + assign cnsty_chk_ack[k] = 1'b1; + + // No buffered data to expose. + assign part_buf_data[PartInfo[k].offset +: PartInfo[k].size] = '0; + + // This stops lint from complaining about unused signals. + logic unused_part_scrmbl_sigs; + assign unused_part_scrmbl_sigs = ^{part_scrmbl_mtx_gnt[k], + part_scrmbl_req_ready[k], + part_scrmbl_rsp_valid[k], + integ_chk_req[k], + cnsty_chk_req[k]}; + + // Alert assertion for sparse FSM. + `CALIPTRA_ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(CtrlPartUnbufFsmCheck_A, + u_part_unbuf.u_state_regs, alert_tx_o[1]) + //////////////////////////////////////////////////////////////////////////////////////////////// + end else if (PartInfo[k].variant == Buffered) begin : gen_buffered + otp_ctrl_part_buf #( + .Info(PartInfo[k]), + .DataDefault(PartInvDefault[PartInfo[k].offset*8 +: PartInfo[k].size*8]) + ) u_part_buf ( + .clk_i, + .rst_ni, + .init_req_i ( part_init_req ), + .init_done_o ( part_init_done[k] ), + .integ_chk_req_i ( integ_chk_req[k] ), + .integ_chk_ack_o ( integ_chk_ack[k] ), + .cnsty_chk_req_i ( cnsty_chk_req[k] ), + .cnsty_chk_ack_o ( cnsty_chk_ack[k] ), + .escalate_en_i ( caliptra_ss_lc_escalate_en[k] ), + // Only supported by life cycle partition (see further below). + .check_byp_en_i ( caliptra_ss_lc_ctrl_pkg::Off ), + .error_o ( part_error[k] ), + .fsm_err_o ( part_fsm_err[k] ), + .access_i ( part_access[k] ), + .access_o ( part_access_dai[k] ), + .digest_o ( part_digest[k] ), + .data_o ( part_buf_data[PartInfo[k].offset +: PartInfo[k].size] ), + .otp_req_o ( part_otp_arb_req[k] ), + .otp_cmd_o ( part_otp_arb_bundle[k].cmd ), + .otp_size_o ( part_otp_arb_bundle[k].size ), + .otp_wdata_o ( part_otp_arb_bundle[k].wdata ), + .otp_addr_o ( part_otp_arb_bundle[k].addr ), + .otp_gnt_i ( part_otp_arb_gnt[k] ), + .otp_rvalid_i ( part_otp_rvalid[k] ), + .otp_rdata_i ( part_otp_rdata ), + .otp_err_i ( part_otp_err ), + .scrmbl_mtx_req_o ( part_scrmbl_mtx_req[k] ), + .scrmbl_mtx_gnt_i ( part_scrmbl_mtx_gnt[k] ), + .scrmbl_cmd_o ( part_scrmbl_req_bundle[k].cmd ), + .scrmbl_mode_o ( part_scrmbl_req_bundle[k].mode ), + .scrmbl_sel_o ( part_scrmbl_req_bundle[k].sel ), + .scrmbl_data_o ( part_scrmbl_req_bundle[k].data ), + .scrmbl_valid_o ( part_scrmbl_req_bundle[k].valid ), + .scrmbl_ready_i ( part_scrmbl_req_ready[k] ), + .scrmbl_valid_i ( part_scrmbl_rsp_valid[k] ), + .scrmbl_data_i ( part_scrmbl_rsp_data ) + ); + + // Buffered partitions are not accessible via the TL-UL window. + logic unused_part_tlul_sigs; + assign unused_part_tlul_sigs = ^part_tlul_req[k]; + assign part_tlul_gnt[k] = 1'b0; + assign part_tlul_rerror[k] = '0; + assign part_tlul_rvalid[k] = 1'b0; + assign part_tlul_rdata[k] = '0; + + // Alert assertion for sparse FSM. + `CALIPTRA_ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(CtrlPartBufFsmCheck_A, + u_part_buf.u_state_regs, alert_tx_o[1]) + `CALIPTRA_ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(CntPartBufCheck_A, + u_part_buf.u_prim_count, alert_tx_o[1]) + //////////////////////////////////////////////////////////////////////////////////////////////// + end else if (PartInfo[k].variant == LifeCycle) begin : gen_lifecycle + otp_ctrl_part_buf #( + .Info(PartInfo[k]), + .DataDefault(PartInvDefault[PartInfo[k].offset*8 +: PartInfo[k].size*8]) + ) u_part_buf ( + .clk_i, + .rst_ni, + .init_req_i ( part_init_req ), + .init_done_o ( part_init_done[k] ), + .integ_chk_req_i ( integ_chk_req[k] ), + .integ_chk_ack_o ( integ_chk_ack[k] ), + .cnsty_chk_req_i ( cnsty_chk_req[k] ), + .cnsty_chk_ack_o ( cnsty_chk_ack[k] ), + .escalate_en_i ( caliptra_ss_lc_escalate_en[k] ), + // This is only supported by the life cycle partition. We need to prevent this partition + // from escalating once the life cycle state in memory is being updated (and hence not + // consistent with the values in the buffer regs anymore). + .check_byp_en_i ( caliptra_ss_lc_check_byp_en ), + .error_o ( part_error[k] ), + .fsm_err_o ( part_fsm_err[k] ), + .access_i ( part_access[k] ), + .access_o ( part_access_dai[k] ), + .digest_o ( part_digest[k] ), + .data_o ( part_buf_data[PartInfo[k].offset +: PartInfo[k].size] ), + .otp_req_o ( part_otp_arb_req[k] ), + .otp_cmd_o ( part_otp_arb_bundle[k].cmd ), + .otp_size_o ( part_otp_arb_bundle[k].size ), + .otp_wdata_o ( part_otp_arb_bundle[k].wdata ), + .otp_addr_o ( part_otp_arb_bundle[k].addr ), + .otp_gnt_i ( part_otp_arb_gnt[k] ), + .otp_rvalid_i ( part_otp_rvalid[k] ), + .otp_rdata_i ( part_otp_rdata ), + .otp_err_i ( part_otp_err ), + // The LC partition does not need any scrambling features. + .scrmbl_mtx_req_o ( ), + .scrmbl_mtx_gnt_i ( 1'b0 ), + .scrmbl_cmd_o ( ), + .scrmbl_mode_o ( ), + .scrmbl_sel_o ( ), + .scrmbl_data_o ( ), + .scrmbl_valid_o ( ), + .scrmbl_ready_i ( 1'b0 ), + .scrmbl_valid_i ( 1'b0 ), + .scrmbl_data_i ( '0 ) + ); + + // Buffered partitions are not accessible via the TL-UL window. + logic unused_part_tlul_sigs; + assign unused_part_tlul_sigs = ^part_tlul_req[k]; + assign part_tlul_gnt[k] = 1'b0; + assign part_tlul_rerror[k] = '0; + assign part_tlul_rvalid[k] = 1'b0; + assign part_tlul_rdata[k] = '0; + + // Tie off unused connections. + assign part_scrmbl_mtx_req[k] = '0; + assign part_scrmbl_req_bundle[k] = '0; + + // This stops lint from complaining about unused signals. + logic unused_part_scrmbl_sigs; + assign unused_part_scrmbl_sigs = ^{part_scrmbl_mtx_gnt[k], + part_scrmbl_req_ready[k], + part_scrmbl_rsp_valid[k]}; + // Alert assertion for sparse FSM. + `CALIPTRA_ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(CtrlPartLcFsmCheck_A, + u_part_buf.u_state_regs, alert_tx_o[1]) + `CALIPTRA_ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(CntPartLcCheck_A, + u_part_buf.u_prim_count, alert_tx_o[1]) + //////////////////////////////////////////////////////////////////////////////////////////////// + end else begin : gen_invalid + // This is invalid and should break elaboration + assert_static_in_generate_invalid assert_static_in_generate_invalid(); + end + //////////////////////////////////////////////////////////////////////////////////////////////// + end + + ////////////////////////////////// + // Buffered Data Output Mapping // + ////////////////////////////////// + + // Output complete hardware config partition. + // Actual mapping to other IPs is done via the intersignal topgen feature, + // selection of fields can be done using the otp_hw_cfg_t struct fields. + otp_broadcast_t otp_broadcast; + assign otp_broadcast = named_broadcast_assign(part_init_done, part_buf_data); + + // Make sure the broadcast valid is flopped before sending it out. + caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_t otp_broadcast_valid_q; + caliptra_prim_lc_sender u_prim_caliptra_ss_lc_sender_otp_broadcast_valid ( + .clk_i, + .rst_ni, + .lc_en_i(otp_broadcast.valid), + .lc_en_o(otp_broadcast_valid_q) + ); + + always_comb begin : p_otp_broadcast_valid + otp_broadcast_o = otp_broadcast; + otp_broadcast_o.valid = otp_broadcast_valid_q; + end + + // Root keys and seeds. + // This uses a generated function to assign all collateral that is marked with "iskeymgr" in + // the memory map. Note that in this case the type is static and represents a superset of all + // options so that we can maintain a stable interface with keymgr (otherwise keymgr will have + // to be templated as well. Unused key material will be tied off to '0. The keymgr has to be + // parameterized accordingly (via SV parameters) to consume the correct key material. + // + // The key material valid signals are set to true if the corresponding digest is nonzero and the + // partition is initialized. On top of that, the entire output is gated by caliptra_ss_lc_seed_hw_rd_en. + otp_keymgr_key_t otp_keymgr_key; + assign otp_keymgr_key = named_keymgr_key_assign(part_digest, + part_buf_data, + caliptra_ss_lc_seed_hw_rd_en); + + // Note regarding these breakouts: named_keymgr_key_assign will tie off unused key material / + // valid signals to '0. This is the case for instance in system configurations that keep the seed + // material in the flash instead of OTP. + logic creator_root_key_share0_valid_d, creator_root_key_share0_valid_q; + logic creator_root_key_share1_valid_d, creator_root_key_share1_valid_q; + logic creator_seed_valid_d, creator_seed_valid_q; + logic owner_seed_valid_d, owner_seed_valid_q; + caliptra_prim_flop #( + .Width(4) + ) u_keygmr_key_valid ( + .clk_i, + .rst_ni, + .d_i ({creator_root_key_share0_valid_d, + creator_root_key_share1_valid_d, + creator_seed_valid_d, + owner_seed_valid_d}), + .q_o ({creator_root_key_share0_valid_q, + creator_root_key_share1_valid_q, + creator_seed_valid_q, + owner_seed_valid_q}) + ); + + always_comb begin : p_otp_keymgr_key_valid + // Valid reg inputs + creator_root_key_share0_valid_d = otp_keymgr_key.creator_root_key_share0_valid; + creator_root_key_share1_valid_d = otp_keymgr_key.creator_root_key_share1_valid; + creator_seed_valid_d = otp_keymgr_key.creator_seed_valid; + owner_seed_valid_d = otp_keymgr_key.owner_seed_valid; + // Output to keymgr + otp_keymgr_key_o = otp_keymgr_key; + otp_keymgr_key_o.creator_root_key_share0_valid = creator_root_key_share0_valid_q; + otp_keymgr_key_o.creator_root_key_share1_valid = creator_root_key_share1_valid_q; + otp_keymgr_key_o.creator_seed_valid = creator_seed_valid_q; + otp_keymgr_key_o.owner_seed_valid = owner_seed_valid_q; + end + + // Check that the caliptra_ss_lc_seed_hw_rd_en remains stable, once the key material is valid. + `CALIPTRA_ASSERT(LcSeedHwRdEnStable0_A, + $rose(creator_root_key_share0_valid_q) |=> $stable(caliptra_ss_lc_seed_hw_rd_en) [*1:$], + clk_i, !rst_ni || caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_test_true_loose(caliptra_ss_lc_escalate_en_i) // Disable if escalating + ) + `CALIPTRA_ASSERT(LcSeedHwRdEnStable1_A, + $rose(creator_root_key_share1_valid_q) |=> $stable(caliptra_ss_lc_seed_hw_rd_en) [*1:$], + clk_i, !rst_ni || caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_test_true_loose(caliptra_ss_lc_escalate_en_i) // Disable if escalating + ) + `CALIPTRA_ASSERT(LcSeedHwRdEnStable2_A, + $rose(creator_seed_valid_q) |=> $stable(caliptra_ss_lc_seed_hw_rd_en) [*1:$], + clk_i, !rst_ni || caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_test_true_loose(caliptra_ss_lc_escalate_en_i) // Disable if escalating + ) + `CALIPTRA_ASSERT(LcSeedHwRdEnStable3_A, + $rose(owner_seed_valid_q) |=> $stable(caliptra_ss_lc_seed_hw_rd_en) [*1:$], + clk_i, !rst_ni || caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_test_true_loose(caliptra_ss_lc_escalate_en_i) // Disable if escalating + ) + + // Scrambling Keys + assign scrmbl_key_seed_valid = part_digest[Secret1Idx] != '0; + assign sram_data_key_seed = part_buf_data[SramDataKeySeedOffset +: + SramDataKeySeedSize]; + assign flash_data_key_seed = part_buf_data[FlashDataKeySeedOffset +: + FlashDataKeySeedSize]; + assign flash_addr_key_seed = part_buf_data[FlashAddrKeySeedOffset +: + FlashAddrKeySeedSize]; + + // Test unlock and exit tokens and RMA token + assign otp_caliptra_ss_lc_data_o.test_exit_token = part_buf_data[TestExitTokenOffset +: + TestExitTokenSize]; + assign otp_caliptra_ss_lc_data_o.test_unlock_token = part_buf_data[TestUnlockTokenOffset +: + TestUnlockTokenSize]; + assign otp_caliptra_ss_lc_data_o.rma_token = part_buf_data[RmaTokenOffset +: + RmaTokenSize]; + + caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_t test_tokens_valid, rma_token_valid, secrets_valid; + // The test tokens have been provisioned. + assign test_tokens_valid = (part_digest[Secret0Idx] != '0) ? caliptra_ss_lc_ctrl_pkg::On : caliptra_ss_lc_ctrl_pkg::Off; + // The rma token has been provisioned. + assign rma_token_valid = (part_digest[Secret2Idx] != '0) ? caliptra_ss_lc_ctrl_pkg::On : caliptra_ss_lc_ctrl_pkg::Off; + // The device is personalized if the root key has been provisioned and locked. + assign secrets_valid = (part_digest[Secret2Idx] != '0) ? caliptra_ss_lc_ctrl_pkg::On : caliptra_ss_lc_ctrl_pkg::Off; + + // Buffer these constants in order to ensure that synthesis does not try to optimize the encoding. + // SEC_CM: TOKEN_VALID.CTRL.MUBI + caliptra_prim_lc_sender #( + .AsyncOn(0) + ) u_prim_caliptra_ss_lc_sender_test_tokens_valid ( + .clk_i, + .rst_ni, + .lc_en_i(test_tokens_valid), + .lc_en_o(otp_caliptra_ss_lc_data_o.test_tokens_valid) + ); + + caliptra_prim_lc_sender #( + .AsyncOn(0) + ) u_prim_caliptra_ss_lc_sender_rma_token_valid ( + .clk_i, + .rst_ni, + .lc_en_i(rma_token_valid), + .lc_en_o(otp_caliptra_ss_lc_data_o.rma_token_valid) + ); + + caliptra_prim_lc_sender #( + .AsyncOn(0) + ) u_prim_caliptra_ss_lc_sender_secrets_valid ( + .clk_i, + .rst_ni, + .lc_en_i(secrets_valid), + .lc_en_o(otp_caliptra_ss_lc_data_o.secrets_valid) + ); + + // Lifecycle state + assign otp_caliptra_ss_lc_data_o.state = caliptra_ss_lc_ctrl_state_pkg::caliptra_ss_lc_state_e'(part_buf_data[LcStateOffset +: + LcStateSize]); + assign otp_caliptra_ss_lc_data_o.count = caliptra_ss_lc_ctrl_state_pkg::caliptra_ss_lc_cnt_e'(part_buf_data[LcTransitionCntOffset +: + LcTransitionCntSize]); + + // Assert life cycle state valid signal only when all partitions have initialized. + assign otp_caliptra_ss_lc_data_o.valid = &part_init_done; + // Signal whether there are any errors in the life cycle partition (both correctable and + // uncorrectable ones). This bit is made available via the JTAG TAP, which is useful for + // production testing in RAW life cycle state where the OTP regs are not accessible. + assign otp_caliptra_ss_lc_data_o.error = |part_error[LifeCycleIdx]; + + // Not all bits of part_buf_data are used here. + logic unused_buf_data; + assign unused_buf_data = ^part_buf_data; + + //////////////// + // Assertions // + //////////////// + + `CALIPTRA_ASSERT_INIT(CreatorRootKeyShare0Size_A, KeyMgrKeyWidth == CreatorRootKeyShare0Size * 8) + `CALIPTRA_ASSERT_INIT(CreatorRootKeyShare1Size_A, KeyMgrKeyWidth == CreatorRootKeyShare1Size * 8) + `CALIPTRA_ASSERT_INIT(FlashDataKeySeedSize_A, FlashKeySeedWidth == FlashDataKeySeedSize * 8) + `CALIPTRA_ASSERT_INIT(FlashAddrKeySeedSize_A, FlashKeySeedWidth == FlashAddrKeySeedSize * 8) + `CALIPTRA_ASSERT_INIT(SramDataKeySeedSize_A, SramKeySeedWidth == SramDataKeySeedSize * 8) + + `CALIPTRA_ASSERT_INIT(RmaTokenSize_A, caliptra_ss_lc_ctrl_state_pkg::LcTokenWidth == RmaTokenSize * 8) + `CALIPTRA_ASSERT_INIT(TestUnlockTokenSize_A, caliptra_ss_lc_ctrl_state_pkg::LcTokenWidth == TestUnlockTokenSize * 8) + `CALIPTRA_ASSERT_INIT(TestExitTokenSize_A, caliptra_ss_lc_ctrl_state_pkg::LcTokenWidth == TestExitTokenSize * 8) + `CALIPTRA_ASSERT_INIT(LcStateSize_A, caliptra_ss_lc_ctrl_state_pkg::LcStateWidth == LcStateSize * 8) + `CALIPTRA_ASSERT_INIT(LcTransitionCntSize_A, caliptra_ss_lc_ctrl_state_pkg::LcCountWidth == LcTransitionCntSize * 8) + + `CALIPTRA_ASSERT_KNOWN(OtpAstPwrSeqKnown_A, otp_ast_pwr_seq_o) + `CALIPTRA_ASSERT_KNOWN(CoreTlOutKnown_A, core_tl_o) + `CALIPTRA_ASSERT_KNOWN(PrimTlOutKnown_A, prim_tl_o) + `CALIPTRA_ASSERT_KNOWN(IntrOtpOperationDoneKnown_A, intr_otp_operation_done_o) + `CALIPTRA_ASSERT_KNOWN(IntrOtpErrorKnown_A, intr_otp_error_o) + `CALIPTRA_ASSERT_KNOWN(AlertTxKnown_A, alert_tx_o) + `CALIPTRA_ASSERT_KNOWN(PwrOtpInitRspKnown_A, pwr_otp_o) + `CALIPTRA_ASSERT_KNOWN(LcOtpProgramRspKnown_A, caliptra_ss_lc_otp_program_o) + `CALIPTRA_ASSERT_KNOWN(OtpLcDataKnown_A, otp_caliptra_ss_lc_data_o) + `CALIPTRA_ASSERT_KNOWN(OtpKeymgrKeyKnown_A, otp_keymgr_key_o) + `CALIPTRA_ASSERT_KNOWN(FlashOtpKeyRspKnown_A, flash_otp_key_o) + `CALIPTRA_ASSERT_KNOWN(OtpSramKeyKnown_A, sram_otp_key_o) + `CALIPTRA_ASSERT_KNOWN(OtpOtgnKeyKnown_A, otbn_otp_key_o) + `CALIPTRA_ASSERT_KNOWN(OtpBroadcastKnown_A, otp_broadcast_o) + + // Alert assertions for sparse FSMs. + `CALIPTRA_ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(CtrlDaiFsmCheck_A, + u_otp_ctrl_dai.u_state_regs, alert_tx_o[1]) + `CALIPTRA_ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(CtrlKdiFsmCheck_A, + u_otp_ctrl_kdi.u_state_regs, alert_tx_o[1]) + `CALIPTRA_ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(CtrlLciFsmCheck_A, + u_otp_ctrl_lci.u_state_regs, alert_tx_o[1]) + `CALIPTRA_ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(CtrlLfsrTimerFsmCheck_A, + u_otp_ctrl_lfsr_timer.u_state_regs, alert_tx_o[1]) + `CALIPTRA_ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(CtrlScrambleFsmCheck_A, + u_otp_ctrl_scrmbl.u_state_regs, alert_tx_o[1]) + + // Alert assertions for redundant counters. + `CALIPTRA_ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(CntIntegCheck_A, + u_otp_ctrl_lfsr_timer.u_prim_count_integ, alert_tx_o[1]) + `CALIPTRA_ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(CntCnstyCheck_A, + u_otp_ctrl_lfsr_timer.u_prim_count_cnsty, alert_tx_o[1]) + `CALIPTRA_ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(CntDaiCheck_A, + u_otp_ctrl_dai.u_prim_count, alert_tx_o[1]) + `CALIPTRA_ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(CntKdiSeedCheck_A, + u_otp_ctrl_kdi.u_prim_count_seed, alert_tx_o[1]) + `CALIPTRA_ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(CntKdiEntropyCheck_A, + u_otp_ctrl_kdi.u_prim_count_entropy, alert_tx_o[1]) + `CALIPTRA_ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(CntLciCheck_A, + u_otp_ctrl_lci.u_prim_count, alert_tx_o[1]) + `CALIPTRA_ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(CntScrmblCheck_A, + u_otp_ctrl_scrmbl.u_prim_count, alert_tx_o[1]) + `CALIPTRA_ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(TlLcGateFsm_A, + u_tlul_caliptra_ss_lc_gate.u_state_regs, alert_tx_o[2]) + + // Alert assertions for double LFSR. + `CALIPTRA_ASSERT_PRIM_DOUBLE_LFSR_ERROR_TRIGGER_ALERT(DoubleLfsrCheck_A, + u_otp_ctrl_lfsr_timer.u_prim_double_lfsr, alert_tx_o[1]) + + // Alert assertions for reg_we onehot check + `CALIPTRA_ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ALERT(RegWeOnehotCheck_A, u_reg_core, alert_tx_o[2]) + + // Assertions for countermeasures inside prim_otp + `ifndef PRIM_DEFAULT_IMPL + `define PRIM_DEFAULT_IMPL prim_pkg::ImplGeneric + `endif + if (`CALIPTRA_PRIM_DEFAULT_IMPL == caliptra_prim_pkg::ImplGeneric) begin : gen_reg_we_assert_generic + `CALIPTRA_ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(PrimFsmCheck_A, + u_otp.u_state_regs, alert_tx_o[3]) + //u_otp.gen_generic.u_impl_generic.u_state_regs, alert_tx_o[3]) + `CALIPTRA_ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ALERT(PrimRegWeOnehotCheck_A, + u_otp.u_reg_top, alert_tx_o[3]) + // //u_otp.gen_generic.u_impl_generic.u_reg_top, alert_tx_o[3]) + end +endmodule : otp_ctrl diff --git a/src/fuse_ctrl/rtl/otp_ctrl_core_reg_top.sv b/src/fuse_ctrl/rtl/otp_ctrl_core_reg_top.sv new file mode 100644 index 0000000..657bfd8 --- /dev/null +++ b/src/fuse_ctrl/rtl/otp_ctrl_core_reg_top.sv @@ -0,0 +1,2579 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Top module auto-generated by `reggen` + +`include "caliptra_prim_assert.sv" + +module otp_ctrl_core_reg_top ( + input clk_i, + input rst_ni, + input tlul_pkg::tl_h2d_t tl_i, + output tlul_pkg::tl_d2h_t tl_o, + + // Output port for window + output tlul_pkg::tl_h2d_t tl_win_o, + input tlul_pkg::tl_d2h_t tl_win_i, + + // To HW + output otp_ctrl_reg_pkg::otp_ctrl_core_reg2hw_t reg2hw, // Write + input otp_ctrl_reg_pkg::otp_ctrl_core_hw2reg_t hw2reg, // Read + + // Integrity check errors + output logic intg_err_o +); + + import otp_ctrl_reg_pkg::* ; + + localparam int AW = 12; + localparam int DW = 32; + localparam int DBW = DW/8; // Byte Width + + // register signals + logic reg_we; + logic reg_re; + logic [AW-1:0] reg_addr; + logic [DW-1:0] reg_wdata; + logic [DBW-1:0] reg_be; + logic [DW-1:0] reg_rdata; + logic reg_error; + + logic addrmiss, wr_err; + + logic [DW-1:0] reg_rdata_next; + logic reg_busy; + + tlul_pkg::tl_h2d_t tl_reg_h2d; + tlul_pkg::tl_d2h_t tl_reg_d2h; + + + // incoming payload check + logic intg_err; + tlul_cmd_intg_chk u_chk ( + .tl_i(tl_i), + .err_o(intg_err) + ); + + // also check for spurious write enables + logic reg_we_err; + logic [55:0] reg_we_check; + caliptra_prim_reg_we_check #( + .OneHotWidth(56) + ) u_caliptra_prim_reg_we_check ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .oh_i (reg_we_check), + .en_i (reg_we && !addrmiss), + .err_o (reg_we_err) + ); + + logic err_q; + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + err_q <= '0; + end else if (intg_err || reg_we_err) begin + err_q <= 1'b1; + end + end + + // integrity error output is permanent and should be used for alert generation + // register errors are transactional + assign intg_err_o = err_q | intg_err | reg_we_err; + + // outgoing integrity generation + tlul_pkg::tl_d2h_t tl_o_pre; + tlul_rsp_intg_gen #( + .EnableRspIntgGen(1), + .EnableDataIntgGen(1) + ) u_rsp_intg_gen ( + .tl_i(tl_o_pre), + .tl_o(tl_o) + ); + + tlul_pkg::tl_h2d_t tl_socket_h2d [2]; + tlul_pkg::tl_d2h_t tl_socket_d2h [2]; + + logic [0:0] reg_steer; + + // socket_1n connection + assign tl_reg_h2d = tl_socket_h2d[1]; + assign tl_socket_d2h[1] = tl_reg_d2h; + + assign tl_win_o = tl_socket_h2d[0]; + assign tl_socket_d2h[0] = tl_win_i; + + // Create Socket_1n + tlul_socket_1n #( + .N (2), + .HReqPass (1'b1), + .HRspPass (1'b1), + .DReqPass ({2{1'b1}}), + .DRspPass ({2{1'b1}}), + .HReqDepth (4'h0), + .HRspDepth (4'h0), + .DReqDepth ({2{4'h0}}), + .DRspDepth ({2{4'h0}}), + .ExplicitErrs (1'b0) + ) u_socket ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .tl_h_i (tl_i), + .tl_h_o (tl_o_pre), + .tl_d_o (tl_socket_h2d), + .tl_d_i (tl_socket_d2h), + .dev_select_i (reg_steer) + ); + + // Create steering logic + always_comb begin + reg_steer = + tl_i.a_address[AW-1:0] inside {[2048:4095]} ? 1'd0 : + // Default set to register + 1'd1; + + // Override this in case of an integrity error + if (intg_err) begin + reg_steer = 1'd1; + end + end + + tlul_adapter_reg #( + .RegAw(AW), + .RegDw(DW), + .EnableDataIntgGen(0) + ) u_reg_if ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + .tl_i (tl_reg_h2d), + .tl_o (tl_reg_d2h), + + .en_ifetch_i(caliptra_prim_mubi_pkg::MuBi4False), + .intg_error_o(), + + .we_o (reg_we), + .re_o (reg_re), + .addr_o (reg_addr), + .wdata_o (reg_wdata), + .be_o (reg_be), + .busy_i (reg_busy), + .rdata_i (reg_rdata), + .error_i (reg_error) + ); + + // cdc oversampling signals + + assign reg_rdata = reg_rdata_next ; + assign reg_error = addrmiss | wr_err | intg_err; + + // Define SW related signals + // Format: __{wd|we|qs} + // or _{wd|we|qs} if field == 1 or 0 + logic intr_state_we; + logic intr_state_otp_operation_done_qs; + logic intr_state_otp_operation_done_wd; + logic intr_state_otp_error_qs; + logic intr_state_otp_error_wd; + logic intr_enable_we; + logic intr_enable_otp_operation_done_qs; + logic intr_enable_otp_operation_done_wd; + logic intr_enable_otp_error_qs; + logic intr_enable_otp_error_wd; + logic intr_test_we; + logic intr_test_otp_operation_done_wd; + logic intr_test_otp_error_wd; + logic alert_test_we; + logic alert_test_fatal_macro_error_wd; + logic alert_test_fatal_check_error_wd; + logic alert_test_fatal_bus_integ_error_wd; + logic alert_test_fatal_prim_otp_alert_wd; + logic alert_test_recov_prim_otp_alert_wd; + logic status_re; + logic status_vendor_test_error_qs; + logic status_creator_sw_cfg_error_qs; + logic status_owner_sw_cfg_error_qs; + logic status_rot_creator_auth_codesign_error_qs; + logic status_rot_creator_auth_state_error_qs; + logic status_hw_cfg0_error_qs; + logic status_hw_cfg1_error_qs; + logic status_secret0_error_qs; + logic status_secret1_error_qs; + logic status_secret2_error_qs; + logic status_life_cycle_error_qs; + logic status_dai_error_qs; + logic status_lci_error_qs; + logic status_timeout_error_qs; + logic status_lfsr_fsm_error_qs; + logic status_scrambling_fsm_error_qs; + logic status_key_deriv_fsm_error_qs; + logic status_bus_integ_error_qs; + logic status_dai_idle_qs; + logic status_check_pending_qs; + logic err_code_0_re; + logic [2:0] err_code_0_qs; + logic err_code_1_re; + logic [2:0] err_code_1_qs; + logic err_code_2_re; + logic [2:0] err_code_2_qs; + logic err_code_3_re; + logic [2:0] err_code_3_qs; + logic err_code_4_re; + logic [2:0] err_code_4_qs; + logic err_code_5_re; + logic [2:0] err_code_5_qs; + logic err_code_6_re; + logic [2:0] err_code_6_qs; + logic err_code_7_re; + logic [2:0] err_code_7_qs; + logic err_code_8_re; + logic [2:0] err_code_8_qs; + logic err_code_9_re; + logic [2:0] err_code_9_qs; + logic err_code_10_re; + logic [2:0] err_code_10_qs; + logic err_code_11_re; + logic [2:0] err_code_11_qs; + logic err_code_12_re; + logic [2:0] err_code_12_qs; + logic direct_access_regwen_re; + logic direct_access_regwen_we; + logic direct_access_regwen_qs; + logic direct_access_regwen_wd; + logic direct_access_cmd_we; + logic direct_access_cmd_rd_wd; + logic direct_access_cmd_wr_wd; + logic direct_access_cmd_digest_wd; + logic direct_access_address_we; + logic [10:0] direct_access_address_qs; + logic [10:0] direct_access_address_wd; + logic direct_access_wdata_0_we; + logic [31:0] direct_access_wdata_0_qs; + logic [31:0] direct_access_wdata_0_wd; + logic direct_access_wdata_1_we; + logic [31:0] direct_access_wdata_1_qs; + logic [31:0] direct_access_wdata_1_wd; + logic direct_access_rdata_0_re; + logic [31:0] direct_access_rdata_0_qs; + logic direct_access_rdata_1_re; + logic [31:0] direct_access_rdata_1_qs; + logic check_trigger_regwen_we; + logic check_trigger_regwen_qs; + logic check_trigger_regwen_wd; + logic check_trigger_we; + logic check_trigger_integrity_wd; + logic check_trigger_consistency_wd; + logic check_regwen_we; + logic check_regwen_qs; + logic check_regwen_wd; + logic check_timeout_we; + logic [31:0] check_timeout_qs; + logic [31:0] check_timeout_wd; + logic integrity_check_period_we; + logic [31:0] integrity_check_period_qs; + logic [31:0] integrity_check_period_wd; + logic consistency_check_period_we; + logic [31:0] consistency_check_period_qs; + logic [31:0] consistency_check_period_wd; + logic vendor_test_read_lock_we; + logic vendor_test_read_lock_qs; + logic vendor_test_read_lock_wd; + logic creator_sw_cfg_read_lock_we; + logic creator_sw_cfg_read_lock_qs; + logic creator_sw_cfg_read_lock_wd; + logic owner_sw_cfg_read_lock_we; + logic owner_sw_cfg_read_lock_qs; + logic owner_sw_cfg_read_lock_wd; + logic rot_creator_auth_codesign_read_lock_we; + logic rot_creator_auth_codesign_read_lock_qs; + logic rot_creator_auth_codesign_read_lock_wd; + logic rot_creator_auth_state_read_lock_we; + logic rot_creator_auth_state_read_lock_qs; + logic rot_creator_auth_state_read_lock_wd; + logic vendor_test_digest_0_re; + logic [31:0] vendor_test_digest_0_qs; + logic vendor_test_digest_1_re; + logic [31:0] vendor_test_digest_1_qs; + logic creator_sw_cfg_digest_0_re; + logic [31:0] creator_sw_cfg_digest_0_qs; + logic creator_sw_cfg_digest_1_re; + logic [31:0] creator_sw_cfg_digest_1_qs; + logic owner_sw_cfg_digest_0_re; + logic [31:0] owner_sw_cfg_digest_0_qs; + logic owner_sw_cfg_digest_1_re; + logic [31:0] owner_sw_cfg_digest_1_qs; + logic rot_creator_auth_codesign_digest_0_re; + logic [31:0] rot_creator_auth_codesign_digest_0_qs; + logic rot_creator_auth_codesign_digest_1_re; + logic [31:0] rot_creator_auth_codesign_digest_1_qs; + logic rot_creator_auth_state_digest_0_re; + logic [31:0] rot_creator_auth_state_digest_0_qs; + logic rot_creator_auth_state_digest_1_re; + logic [31:0] rot_creator_auth_state_digest_1_qs; + logic hw_cfg0_digest_0_re; + logic [31:0] hw_cfg0_digest_0_qs; + logic hw_cfg0_digest_1_re; + logic [31:0] hw_cfg0_digest_1_qs; + logic hw_cfg1_digest_0_re; + logic [31:0] hw_cfg1_digest_0_qs; + logic hw_cfg1_digest_1_re; + logic [31:0] hw_cfg1_digest_1_qs; + logic secret0_digest_0_re; + logic [31:0] secret0_digest_0_qs; + logic secret0_digest_1_re; + logic [31:0] secret0_digest_1_qs; + logic secret1_digest_0_re; + logic [31:0] secret1_digest_0_qs; + logic secret1_digest_1_re; + logic [31:0] secret1_digest_1_qs; + logic secret2_digest_0_re; + logic [31:0] secret2_digest_0_qs; + logic secret2_digest_1_re; + logic [31:0] secret2_digest_1_qs; + + // Register instances + // R[intr_state]: V(False) + // F[otp_operation_done]: 0:0 + caliptra_prim_subreg #( + .DW (1), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_intr_state_otp_operation_done ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intr_state_we), + .wd (intr_state_otp_operation_done_wd), + + // from internal hardware + .de (hw2reg.intr_state.otp_operation_done.de), + .d (hw2reg.intr_state.otp_operation_done.d), + + // to internal hardware + .qe (), + .q (reg2hw.intr_state.otp_operation_done.q), + .ds (), + + // to register interface (read) + .qs (intr_state_otp_operation_done_qs) + ); + + // F[otp_error]: 1:1 + caliptra_prim_subreg #( + .DW (1), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_intr_state_otp_error ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intr_state_we), + .wd (intr_state_otp_error_wd), + + // from internal hardware + .de (hw2reg.intr_state.otp_error.de), + .d (hw2reg.intr_state.otp_error.d), + + // to internal hardware + .qe (), + .q (reg2hw.intr_state.otp_error.q), + .ds (), + + // to register interface (read) + .qs (intr_state_otp_error_qs) + ); + + + // R[intr_enable]: V(False) + // F[otp_operation_done]: 0:0 + caliptra_prim_subreg #( + .DW (1), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_intr_enable_otp_operation_done ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intr_enable_we), + .wd (intr_enable_otp_operation_done_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.intr_enable.otp_operation_done.q), + .ds (), + + // to register interface (read) + .qs (intr_enable_otp_operation_done_qs) + ); + + // F[otp_error]: 1:1 + caliptra_prim_subreg #( + .DW (1), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_intr_enable_otp_error ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intr_enable_we), + .wd (intr_enable_otp_error_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.intr_enable.otp_error.q), + .ds (), + + // to register interface (read) + .qs (intr_enable_otp_error_qs) + ); + + + // R[intr_test]: V(True) + logic intr_test_qe; + logic [1:0] intr_test_flds_we; + assign intr_test_qe = &intr_test_flds_we; + // F[otp_operation_done]: 0:0 + caliptra_prim_subreg_ext #( + .DW (1) + ) u_intr_test_otp_operation_done ( + .re (1'b0), + .we (intr_test_we), + .wd (intr_test_otp_operation_done_wd), + .d ('0), + .qre (), + .qe (intr_test_flds_we[0]), + .q (reg2hw.intr_test.otp_operation_done.q), + .ds (), + .qs () + ); + assign reg2hw.intr_test.otp_operation_done.qe = intr_test_qe; + + // F[otp_error]: 1:1 + caliptra_prim_subreg_ext #( + .DW (1) + ) u_intr_test_otp_error ( + .re (1'b0), + .we (intr_test_we), + .wd (intr_test_otp_error_wd), + .d ('0), + .qre (), + .qe (intr_test_flds_we[1]), + .q (reg2hw.intr_test.otp_error.q), + .ds (), + .qs () + ); + assign reg2hw.intr_test.otp_error.qe = intr_test_qe; + + + // R[alert_test]: V(True) + logic alert_test_qe; + logic [4:0] alert_test_flds_we; + assign alert_test_qe = &alert_test_flds_we; + // F[fatal_macro_error]: 0:0 + caliptra_prim_subreg_ext #( + .DW (1) + ) u_alert_test_fatal_macro_error ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_fatal_macro_error_wd), + .d ('0), + .qre (), + .qe (alert_test_flds_we[0]), + .q (reg2hw.alert_test.fatal_macro_error.q), + .ds (), + .qs () + ); + assign reg2hw.alert_test.fatal_macro_error.qe = alert_test_qe; + + // F[fatal_check_error]: 1:1 + caliptra_prim_subreg_ext #( + .DW (1) + ) u_alert_test_fatal_check_error ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_fatal_check_error_wd), + .d ('0), + .qre (), + .qe (alert_test_flds_we[1]), + .q (reg2hw.alert_test.fatal_check_error.q), + .ds (), + .qs () + ); + assign reg2hw.alert_test.fatal_check_error.qe = alert_test_qe; + + // F[fatal_bus_integ_error]: 2:2 + caliptra_prim_subreg_ext #( + .DW (1) + ) u_alert_test_fatal_bus_integ_error ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_fatal_bus_integ_error_wd), + .d ('0), + .qre (), + .qe (alert_test_flds_we[2]), + .q (reg2hw.alert_test.fatal_bus_integ_error.q), + .ds (), + .qs () + ); + assign reg2hw.alert_test.fatal_bus_integ_error.qe = alert_test_qe; + + // F[fatal_prim_otp_alert]: 3:3 + caliptra_prim_subreg_ext #( + .DW (1) + ) u_alert_test_fatal_prim_otp_alert ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_fatal_prim_otp_alert_wd), + .d ('0), + .qre (), + .qe (alert_test_flds_we[3]), + .q (reg2hw.alert_test.fatal_prim_otp_alert.q), + .ds (), + .qs () + ); + assign reg2hw.alert_test.fatal_prim_otp_alert.qe = alert_test_qe; + + // F[recov_prim_otp_alert]: 4:4 + caliptra_prim_subreg_ext #( + .DW (1) + ) u_alert_test_recov_prim_otp_alert ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_recov_prim_otp_alert_wd), + .d ('0), + .qre (), + .qe (alert_test_flds_we[4]), + .q (reg2hw.alert_test.recov_prim_otp_alert.q), + .ds (), + .qs () + ); + assign reg2hw.alert_test.recov_prim_otp_alert.qe = alert_test_qe; + + + // R[status]: V(True) + // F[vendor_test_error]: 0:0 + caliptra_prim_subreg_ext #( + .DW (1) + ) u_status_vendor_test_error ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.vendor_test_error.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_vendor_test_error_qs) + ); + + // F[creator_sw_cfg_error]: 1:1 + caliptra_prim_subreg_ext #( + .DW (1) + ) u_status_creator_sw_cfg_error ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.creator_sw_cfg_error.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_creator_sw_cfg_error_qs) + ); + + // F[owner_sw_cfg_error]: 2:2 + caliptra_prim_subreg_ext #( + .DW (1) + ) u_status_owner_sw_cfg_error ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.owner_sw_cfg_error.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_owner_sw_cfg_error_qs) + ); + + // F[rot_creator_auth_codesign_error]: 3:3 + caliptra_prim_subreg_ext #( + .DW (1) + ) u_status_rot_creator_auth_codesign_error ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.rot_creator_auth_codesign_error.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_rot_creator_auth_codesign_error_qs) + ); + + // F[rot_creator_auth_state_error]: 4:4 + caliptra_prim_subreg_ext #( + .DW (1) + ) u_status_rot_creator_auth_state_error ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.rot_creator_auth_state_error.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_rot_creator_auth_state_error_qs) + ); + + // F[hw_cfg0_error]: 5:5 + caliptra_prim_subreg_ext #( + .DW (1) + ) u_status_hw_cfg0_error ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.hw_cfg0_error.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_hw_cfg0_error_qs) + ); + + // F[hw_cfg1_error]: 6:6 + caliptra_prim_subreg_ext #( + .DW (1) + ) u_status_hw_cfg1_error ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.hw_cfg1_error.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_hw_cfg1_error_qs) + ); + + // F[secret0_error]: 7:7 + caliptra_prim_subreg_ext #( + .DW (1) + ) u_status_secret0_error ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.secret0_error.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_secret0_error_qs) + ); + + // F[secret1_error]: 8:8 + caliptra_prim_subreg_ext #( + .DW (1) + ) u_status_secret1_error ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.secret1_error.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_secret1_error_qs) + ); + + // F[secret2_error]: 9:9 + caliptra_prim_subreg_ext #( + .DW (1) + ) u_status_secret2_error ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.secret2_error.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_secret2_error_qs) + ); + + // F[life_cycle_error]: 10:10 + caliptra_prim_subreg_ext #( + .DW (1) + ) u_status_life_cycle_error ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.life_cycle_error.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_life_cycle_error_qs) + ); + + // F[dai_error]: 11:11 + caliptra_prim_subreg_ext #( + .DW (1) + ) u_status_dai_error ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.dai_error.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_dai_error_qs) + ); + + // F[lci_error]: 12:12 + caliptra_prim_subreg_ext #( + .DW (1) + ) u_status_lci_error ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.lci_error.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_lci_error_qs) + ); + + // F[timeout_error]: 13:13 + caliptra_prim_subreg_ext #( + .DW (1) + ) u_status_timeout_error ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.timeout_error.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_timeout_error_qs) + ); + + // F[lfsr_fsm_error]: 14:14 + caliptra_prim_subreg_ext #( + .DW (1) + ) u_status_lfsr_fsm_error ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.lfsr_fsm_error.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_lfsr_fsm_error_qs) + ); + + // F[scrambling_fsm_error]: 15:15 + caliptra_prim_subreg_ext #( + .DW (1) + ) u_status_scrambling_fsm_error ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.scrambling_fsm_error.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_scrambling_fsm_error_qs) + ); + + // F[key_deriv_fsm_error]: 16:16 + caliptra_prim_subreg_ext #( + .DW (1) + ) u_status_key_deriv_fsm_error ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.key_deriv_fsm_error.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_key_deriv_fsm_error_qs) + ); + + // F[bus_integ_error]: 17:17 + caliptra_prim_subreg_ext #( + .DW (1) + ) u_status_bus_integ_error ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.bus_integ_error.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_bus_integ_error_qs) + ); + + // F[dai_idle]: 18:18 + caliptra_prim_subreg_ext #( + .DW (1) + ) u_status_dai_idle ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.dai_idle.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_dai_idle_qs) + ); + + // F[check_pending]: 19:19 + caliptra_prim_subreg_ext #( + .DW (1) + ) u_status_check_pending ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.check_pending.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_check_pending_qs) + ); + + + // Subregister 0 of Multireg err_code + // R[err_code_0]: V(True) + caliptra_prim_subreg_ext #( + .DW (3) + ) u_err_code_0 ( + .re (err_code_0_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.err_code[0].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (err_code_0_qs) + ); + + + // Subregister 1 of Multireg err_code + // R[err_code_1]: V(True) + caliptra_prim_subreg_ext #( + .DW (3) + ) u_err_code_1 ( + .re (err_code_1_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.err_code[1].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (err_code_1_qs) + ); + + + // Subregister 2 of Multireg err_code + // R[err_code_2]: V(True) + caliptra_prim_subreg_ext #( + .DW (3) + ) u_err_code_2 ( + .re (err_code_2_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.err_code[2].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (err_code_2_qs) + ); + + + // Subregister 3 of Multireg err_code + // R[err_code_3]: V(True) + caliptra_prim_subreg_ext #( + .DW (3) + ) u_err_code_3 ( + .re (err_code_3_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.err_code[3].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (err_code_3_qs) + ); + + + // Subregister 4 of Multireg err_code + // R[err_code_4]: V(True) + caliptra_prim_subreg_ext #( + .DW (3) + ) u_err_code_4 ( + .re (err_code_4_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.err_code[4].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (err_code_4_qs) + ); + + + // Subregister 5 of Multireg err_code + // R[err_code_5]: V(True) + caliptra_prim_subreg_ext #( + .DW (3) + ) u_err_code_5 ( + .re (err_code_5_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.err_code[5].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (err_code_5_qs) + ); + + + // Subregister 6 of Multireg err_code + // R[err_code_6]: V(True) + caliptra_prim_subreg_ext #( + .DW (3) + ) u_err_code_6 ( + .re (err_code_6_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.err_code[6].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (err_code_6_qs) + ); + + + // Subregister 7 of Multireg err_code + // R[err_code_7]: V(True) + caliptra_prim_subreg_ext #( + .DW (3) + ) u_err_code_7 ( + .re (err_code_7_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.err_code[7].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (err_code_7_qs) + ); + + + // Subregister 8 of Multireg err_code + // R[err_code_8]: V(True) + caliptra_prim_subreg_ext #( + .DW (3) + ) u_err_code_8 ( + .re (err_code_8_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.err_code[8].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (err_code_8_qs) + ); + + + // Subregister 9 of Multireg err_code + // R[err_code_9]: V(True) + caliptra_prim_subreg_ext #( + .DW (3) + ) u_err_code_9 ( + .re (err_code_9_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.err_code[9].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (err_code_9_qs) + ); + + + // Subregister 10 of Multireg err_code + // R[err_code_10]: V(True) + caliptra_prim_subreg_ext #( + .DW (3) + ) u_err_code_10 ( + .re (err_code_10_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.err_code[10].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (err_code_10_qs) + ); + + + // Subregister 11 of Multireg err_code + // R[err_code_11]: V(True) + caliptra_prim_subreg_ext #( + .DW (3) + ) u_err_code_11 ( + .re (err_code_11_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.err_code[11].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (err_code_11_qs) + ); + + + // Subregister 12 of Multireg err_code + // R[err_code_12]: V(True) + caliptra_prim_subreg_ext #( + .DW (3) + ) u_err_code_12 ( + .re (err_code_12_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.err_code[12].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (err_code_12_qs) + ); + + + // R[direct_access_regwen]: V(True) + logic direct_access_regwen_qe; + logic [0:0] direct_access_regwen_flds_we; + assign direct_access_regwen_qe = &direct_access_regwen_flds_we; + caliptra_prim_subreg_ext #( + .DW (1) + ) u_direct_access_regwen ( + .re (direct_access_regwen_re), + .we (direct_access_regwen_we), + .wd (direct_access_regwen_wd), + .d (hw2reg.direct_access_regwen.d), + .qre (), + .qe (direct_access_regwen_flds_we[0]), + .q (reg2hw.direct_access_regwen.q), + .ds (), + .qs (direct_access_regwen_qs) + ); + assign reg2hw.direct_access_regwen.qe = direct_access_regwen_qe; + + + // R[direct_access_cmd]: V(True) + logic direct_access_cmd_qe; + logic [2:0] direct_access_cmd_flds_we; + assign direct_access_cmd_qe = &direct_access_cmd_flds_we; + // Create REGWEN-gated WE signal + logic direct_access_cmd_gated_we; + assign direct_access_cmd_gated_we = direct_access_cmd_we & direct_access_regwen_qs; + // F[rd]: 0:0 + caliptra_prim_subreg_ext #( + .DW (1) + ) u_direct_access_cmd_rd ( + .re (1'b0), + .we (direct_access_cmd_gated_we), + .wd (direct_access_cmd_rd_wd), + .d ('0), + .qre (), + .qe (direct_access_cmd_flds_we[0]), + .q (reg2hw.direct_access_cmd.rd.q), + .ds (), + .qs () + ); + assign reg2hw.direct_access_cmd.rd.qe = direct_access_cmd_qe; + + // F[wr]: 1:1 + caliptra_prim_subreg_ext #( + .DW (1) + ) u_direct_access_cmd_wr ( + .re (1'b0), + .we (direct_access_cmd_gated_we), + .wd (direct_access_cmd_wr_wd), + .d ('0), + .qre (), + .qe (direct_access_cmd_flds_we[1]), + .q (reg2hw.direct_access_cmd.wr.q), + .ds (), + .qs () + ); + assign reg2hw.direct_access_cmd.wr.qe = direct_access_cmd_qe; + + // F[digest]: 2:2 + caliptra_prim_subreg_ext #( + .DW (1) + ) u_direct_access_cmd_digest ( + .re (1'b0), + .we (direct_access_cmd_gated_we), + .wd (direct_access_cmd_digest_wd), + .d ('0), + .qre (), + .qe (direct_access_cmd_flds_we[2]), + .q (reg2hw.direct_access_cmd.digest.q), + .ds (), + .qs () + ); + assign reg2hw.direct_access_cmd.digest.qe = direct_access_cmd_qe; + + + // R[direct_access_address]: V(False) + // Create REGWEN-gated WE signal + logic direct_access_address_gated_we; + assign direct_access_address_gated_we = direct_access_address_we & direct_access_regwen_qs; + caliptra_prim_subreg #( + .DW (11), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW), + .RESVAL (11'h0), + .Mubi (1'b0) + ) u_direct_access_address ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (direct_access_address_gated_we), + .wd (direct_access_address_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.direct_access_address.q), + .ds (), + + // to register interface (read) + .qs (direct_access_address_qs) + ); + + + // Subregister 0 of Multireg direct_access_wdata + // R[direct_access_wdata_0]: V(False) + // Create REGWEN-gated WE signal + logic direct_access_wdata_0_gated_we; + assign direct_access_wdata_0_gated_we = direct_access_wdata_0_we & direct_access_regwen_qs; + caliptra_prim_subreg #( + .DW (32), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_direct_access_wdata_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (direct_access_wdata_0_gated_we), + .wd (direct_access_wdata_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.direct_access_wdata[0].q), + .ds (), + + // to register interface (read) + .qs (direct_access_wdata_0_qs) + ); + + + // Subregister 1 of Multireg direct_access_wdata + // R[direct_access_wdata_1]: V(False) + // Create REGWEN-gated WE signal + logic direct_access_wdata_1_gated_we; + assign direct_access_wdata_1_gated_we = direct_access_wdata_1_we & direct_access_regwen_qs; + caliptra_prim_subreg #( + .DW (32), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_direct_access_wdata_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (direct_access_wdata_1_gated_we), + .wd (direct_access_wdata_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.direct_access_wdata[1].q), + .ds (), + + // to register interface (read) + .qs (direct_access_wdata_1_qs) + ); + + + // Subregister 0 of Multireg direct_access_rdata + // R[direct_access_rdata_0]: V(True) + caliptra_prim_subreg_ext #( + .DW (32) + ) u_direct_access_rdata_0 ( + .re (direct_access_rdata_0_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.direct_access_rdata[0].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (direct_access_rdata_0_qs) + ); + + + // Subregister 1 of Multireg direct_access_rdata + // R[direct_access_rdata_1]: V(True) + caliptra_prim_subreg_ext #( + .DW (32) + ) u_direct_access_rdata_1 ( + .re (direct_access_rdata_1_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.direct_access_rdata[1].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (direct_access_rdata_1_qs) + ); + + + // R[check_trigger_regwen]: V(False) + caliptra_prim_subreg #( + .DW (1), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_check_trigger_regwen ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (check_trigger_regwen_we), + .wd (check_trigger_regwen_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (check_trigger_regwen_qs) + ); + + + // R[check_trigger]: V(True) + logic check_trigger_qe; + logic [1:0] check_trigger_flds_we; + assign check_trigger_qe = &check_trigger_flds_we; + // Create REGWEN-gated WE signal + logic check_trigger_gated_we; + assign check_trigger_gated_we = check_trigger_we & check_trigger_regwen_qs; + // F[integrity]: 0:0 + caliptra_prim_subreg_ext #( + .DW (1) + ) u_check_trigger_integrity ( + .re (1'b0), + .we (check_trigger_gated_we), + .wd (check_trigger_integrity_wd), + .d ('0), + .qre (), + .qe (check_trigger_flds_we[0]), + .q (reg2hw.check_trigger.integrity.q), + .ds (), + .qs () + ); + assign reg2hw.check_trigger.integrity.qe = check_trigger_qe; + + // F[consistency]: 1:1 + caliptra_prim_subreg_ext #( + .DW (1) + ) u_check_trigger_consistency ( + .re (1'b0), + .we (check_trigger_gated_we), + .wd (check_trigger_consistency_wd), + .d ('0), + .qre (), + .qe (check_trigger_flds_we[1]), + .q (reg2hw.check_trigger.consistency.q), + .ds (), + .qs () + ); + assign reg2hw.check_trigger.consistency.qe = check_trigger_qe; + + + // R[check_regwen]: V(False) + caliptra_prim_subreg #( + .DW (1), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_check_regwen ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (check_regwen_we), + .wd (check_regwen_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (check_regwen_qs) + ); + + + // R[check_timeout]: V(False) + // Create REGWEN-gated WE signal + logic check_timeout_gated_we; + assign check_timeout_gated_we = check_timeout_we & check_regwen_qs; + caliptra_prim_subreg #( + .DW (32), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_check_timeout ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (check_timeout_gated_we), + .wd (check_timeout_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.check_timeout.q), + .ds (), + + // to register interface (read) + .qs (check_timeout_qs) + ); + + + // R[integrity_check_period]: V(False) + // Create REGWEN-gated WE signal + logic integrity_check_period_gated_we; + assign integrity_check_period_gated_we = integrity_check_period_we & check_regwen_qs; + caliptra_prim_subreg #( + .DW (32), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_integrity_check_period ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (integrity_check_period_gated_we), + .wd (integrity_check_period_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.integrity_check_period.q), + .ds (), + + // to register interface (read) + .qs (integrity_check_period_qs) + ); + + + // R[consistency_check_period]: V(False) + // Create REGWEN-gated WE signal + logic consistency_check_period_gated_we; + assign consistency_check_period_gated_we = consistency_check_period_we & check_regwen_qs; + caliptra_prim_subreg #( + .DW (32), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_consistency_check_period ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (consistency_check_period_gated_we), + .wd (consistency_check_period_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.consistency_check_period.q), + .ds (), + + // to register interface (read) + .qs (consistency_check_period_qs) + ); + + + // R[vendor_test_read_lock]: V(False) + // Create REGWEN-gated WE signal + logic vendor_test_read_lock_gated_we; + assign vendor_test_read_lock_gated_we = vendor_test_read_lock_we & direct_access_regwen_qs; + caliptra_prim_subreg #( + .DW (1), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_vendor_test_read_lock ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (vendor_test_read_lock_gated_we), + .wd (vendor_test_read_lock_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.vendor_test_read_lock.q), + .ds (), + + // to register interface (read) + .qs (vendor_test_read_lock_qs) + ); + + + // R[creator_sw_cfg_read_lock]: V(False) + // Create REGWEN-gated WE signal + logic creator_sw_cfg_read_lock_gated_we; + assign creator_sw_cfg_read_lock_gated_we = creator_sw_cfg_read_lock_we & direct_access_regwen_qs; + caliptra_prim_subreg #( + .DW (1), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_creator_sw_cfg_read_lock ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (creator_sw_cfg_read_lock_gated_we), + .wd (creator_sw_cfg_read_lock_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.creator_sw_cfg_read_lock.q), + .ds (), + + // to register interface (read) + .qs (creator_sw_cfg_read_lock_qs) + ); + + + // R[owner_sw_cfg_read_lock]: V(False) + // Create REGWEN-gated WE signal + logic owner_sw_cfg_read_lock_gated_we; + assign owner_sw_cfg_read_lock_gated_we = owner_sw_cfg_read_lock_we & direct_access_regwen_qs; + caliptra_prim_subreg #( + .DW (1), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_owner_sw_cfg_read_lock ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (owner_sw_cfg_read_lock_gated_we), + .wd (owner_sw_cfg_read_lock_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.owner_sw_cfg_read_lock.q), + .ds (), + + // to register interface (read) + .qs (owner_sw_cfg_read_lock_qs) + ); + + + // R[rot_creator_auth_codesign_read_lock]: V(False) + // Create REGWEN-gated WE signal + logic rot_creator_auth_codesign_read_lock_gated_we; + assign rot_creator_auth_codesign_read_lock_gated_we = + rot_creator_auth_codesign_read_lock_we & direct_access_regwen_qs; + caliptra_prim_subreg #( + .DW (1), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_rot_creator_auth_codesign_read_lock ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rot_creator_auth_codesign_read_lock_gated_we), + .wd (rot_creator_auth_codesign_read_lock_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rot_creator_auth_codesign_read_lock.q), + .ds (), + + // to register interface (read) + .qs (rot_creator_auth_codesign_read_lock_qs) + ); + + + // R[rot_creator_auth_state_read_lock]: V(False) + // Create REGWEN-gated WE signal + logic rot_creator_auth_state_read_lock_gated_we; + assign rot_creator_auth_state_read_lock_gated_we = + rot_creator_auth_state_read_lock_we & direct_access_regwen_qs; + caliptra_prim_subreg #( + .DW (1), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_rot_creator_auth_state_read_lock ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rot_creator_auth_state_read_lock_gated_we), + .wd (rot_creator_auth_state_read_lock_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rot_creator_auth_state_read_lock.q), + .ds (), + + // to register interface (read) + .qs (rot_creator_auth_state_read_lock_qs) + ); + + + // Subregister 0 of Multireg vendor_test_digest + // R[vendor_test_digest_0]: V(True) + caliptra_prim_subreg_ext #( + .DW (32) + ) u_vendor_test_digest_0 ( + .re (vendor_test_digest_0_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.vendor_test_digest[0].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (vendor_test_digest_0_qs) + ); + + + // Subregister 1 of Multireg vendor_test_digest + // R[vendor_test_digest_1]: V(True) + caliptra_prim_subreg_ext #( + .DW (32) + ) u_vendor_test_digest_1 ( + .re (vendor_test_digest_1_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.vendor_test_digest[1].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (vendor_test_digest_1_qs) + ); + + + // Subregister 0 of Multireg creator_sw_cfg_digest + // R[creator_sw_cfg_digest_0]: V(True) + caliptra_prim_subreg_ext #( + .DW (32) + ) u_creator_sw_cfg_digest_0 ( + .re (creator_sw_cfg_digest_0_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.creator_sw_cfg_digest[0].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (creator_sw_cfg_digest_0_qs) + ); + + + // Subregister 1 of Multireg creator_sw_cfg_digest + // R[creator_sw_cfg_digest_1]: V(True) + caliptra_prim_subreg_ext #( + .DW (32) + ) u_creator_sw_cfg_digest_1 ( + .re (creator_sw_cfg_digest_1_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.creator_sw_cfg_digest[1].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (creator_sw_cfg_digest_1_qs) + ); + + + // Subregister 0 of Multireg owner_sw_cfg_digest + // R[owner_sw_cfg_digest_0]: V(True) + caliptra_prim_subreg_ext #( + .DW (32) + ) u_owner_sw_cfg_digest_0 ( + .re (owner_sw_cfg_digest_0_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.owner_sw_cfg_digest[0].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (owner_sw_cfg_digest_0_qs) + ); + + + // Subregister 1 of Multireg owner_sw_cfg_digest + // R[owner_sw_cfg_digest_1]: V(True) + caliptra_prim_subreg_ext #( + .DW (32) + ) u_owner_sw_cfg_digest_1 ( + .re (owner_sw_cfg_digest_1_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.owner_sw_cfg_digest[1].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (owner_sw_cfg_digest_1_qs) + ); + + + // Subregister 0 of Multireg rot_creator_auth_codesign_digest + // R[rot_creator_auth_codesign_digest_0]: V(True) + caliptra_prim_subreg_ext #( + .DW (32) + ) u_rot_creator_auth_codesign_digest_0 ( + .re (rot_creator_auth_codesign_digest_0_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.rot_creator_auth_codesign_digest[0].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (rot_creator_auth_codesign_digest_0_qs) + ); + + + // Subregister 1 of Multireg rot_creator_auth_codesign_digest + // R[rot_creator_auth_codesign_digest_1]: V(True) + caliptra_prim_subreg_ext #( + .DW (32) + ) u_rot_creator_auth_codesign_digest_1 ( + .re (rot_creator_auth_codesign_digest_1_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.rot_creator_auth_codesign_digest[1].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (rot_creator_auth_codesign_digest_1_qs) + ); + + + // Subregister 0 of Multireg rot_creator_auth_state_digest + // R[rot_creator_auth_state_digest_0]: V(True) + caliptra_prim_subreg_ext #( + .DW (32) + ) u_rot_creator_auth_state_digest_0 ( + .re (rot_creator_auth_state_digest_0_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.rot_creator_auth_state_digest[0].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (rot_creator_auth_state_digest_0_qs) + ); + + + // Subregister 1 of Multireg rot_creator_auth_state_digest + // R[rot_creator_auth_state_digest_1]: V(True) + caliptra_prim_subreg_ext #( + .DW (32) + ) u_rot_creator_auth_state_digest_1 ( + .re (rot_creator_auth_state_digest_1_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.rot_creator_auth_state_digest[1].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (rot_creator_auth_state_digest_1_qs) + ); + + + // Subregister 0 of Multireg hw_cfg0_digest + // R[hw_cfg0_digest_0]: V(True) + caliptra_prim_subreg_ext #( + .DW (32) + ) u_hw_cfg0_digest_0 ( + .re (hw_cfg0_digest_0_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.hw_cfg0_digest[0].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (hw_cfg0_digest_0_qs) + ); + + + // Subregister 1 of Multireg hw_cfg0_digest + // R[hw_cfg0_digest_1]: V(True) + caliptra_prim_subreg_ext #( + .DW (32) + ) u_hw_cfg0_digest_1 ( + .re (hw_cfg0_digest_1_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.hw_cfg0_digest[1].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (hw_cfg0_digest_1_qs) + ); + + + // Subregister 0 of Multireg hw_cfg1_digest + // R[hw_cfg1_digest_0]: V(True) + caliptra_prim_subreg_ext #( + .DW (32) + ) u_hw_cfg1_digest_0 ( + .re (hw_cfg1_digest_0_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.hw_cfg1_digest[0].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (hw_cfg1_digest_0_qs) + ); + + + // Subregister 1 of Multireg hw_cfg1_digest + // R[hw_cfg1_digest_1]: V(True) + caliptra_prim_subreg_ext #( + .DW (32) + ) u_hw_cfg1_digest_1 ( + .re (hw_cfg1_digest_1_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.hw_cfg1_digest[1].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (hw_cfg1_digest_1_qs) + ); + + + // Subregister 0 of Multireg secret0_digest + // R[secret0_digest_0]: V(True) + caliptra_prim_subreg_ext #( + .DW (32) + ) u_secret0_digest_0 ( + .re (secret0_digest_0_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.secret0_digest[0].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (secret0_digest_0_qs) + ); + + + // Subregister 1 of Multireg secret0_digest + // R[secret0_digest_1]: V(True) + caliptra_prim_subreg_ext #( + .DW (32) + ) u_secret0_digest_1 ( + .re (secret0_digest_1_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.secret0_digest[1].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (secret0_digest_1_qs) + ); + + + // Subregister 0 of Multireg secret1_digest + // R[secret1_digest_0]: V(True) + caliptra_prim_subreg_ext #( + .DW (32) + ) u_secret1_digest_0 ( + .re (secret1_digest_0_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.secret1_digest[0].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (secret1_digest_0_qs) + ); + + + // Subregister 1 of Multireg secret1_digest + // R[secret1_digest_1]: V(True) + caliptra_prim_subreg_ext #( + .DW (32) + ) u_secret1_digest_1 ( + .re (secret1_digest_1_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.secret1_digest[1].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (secret1_digest_1_qs) + ); + + + // Subregister 0 of Multireg secret2_digest + // R[secret2_digest_0]: V(True) + caliptra_prim_subreg_ext #( + .DW (32) + ) u_secret2_digest_0 ( + .re (secret2_digest_0_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.secret2_digest[0].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (secret2_digest_0_qs) + ); + + + // Subregister 1 of Multireg secret2_digest + // R[secret2_digest_1]: V(True) + caliptra_prim_subreg_ext #( + .DW (32) + ) u_secret2_digest_1 ( + .re (secret2_digest_1_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.secret2_digest[1].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (secret2_digest_1_qs) + ); + + + + logic [55:0] addr_hit; + always_comb begin + addr_hit = '0; + addr_hit[ 0] = (reg_addr == OTP_CTRL_INTR_STATE_OFFSET); + addr_hit[ 1] = (reg_addr == OTP_CTRL_INTR_ENABLE_OFFSET); + addr_hit[ 2] = (reg_addr == OTP_CTRL_INTR_TEST_OFFSET); + addr_hit[ 3] = (reg_addr == OTP_CTRL_ALERT_TEST_OFFSET); + addr_hit[ 4] = (reg_addr == OTP_CTRL_STATUS_OFFSET); + addr_hit[ 5] = (reg_addr == OTP_CTRL_ERR_CODE_0_OFFSET); + addr_hit[ 6] = (reg_addr == OTP_CTRL_ERR_CODE_1_OFFSET); + addr_hit[ 7] = (reg_addr == OTP_CTRL_ERR_CODE_2_OFFSET); + addr_hit[ 8] = (reg_addr == OTP_CTRL_ERR_CODE_3_OFFSET); + addr_hit[ 9] = (reg_addr == OTP_CTRL_ERR_CODE_4_OFFSET); + addr_hit[10] = (reg_addr == OTP_CTRL_ERR_CODE_5_OFFSET); + addr_hit[11] = (reg_addr == OTP_CTRL_ERR_CODE_6_OFFSET); + addr_hit[12] = (reg_addr == OTP_CTRL_ERR_CODE_7_OFFSET); + addr_hit[13] = (reg_addr == OTP_CTRL_ERR_CODE_8_OFFSET); + addr_hit[14] = (reg_addr == OTP_CTRL_ERR_CODE_9_OFFSET); + addr_hit[15] = (reg_addr == OTP_CTRL_ERR_CODE_10_OFFSET); + addr_hit[16] = (reg_addr == OTP_CTRL_ERR_CODE_11_OFFSET); + addr_hit[17] = (reg_addr == OTP_CTRL_ERR_CODE_12_OFFSET); + addr_hit[18] = (reg_addr == OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET); + addr_hit[19] = (reg_addr == OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET); + addr_hit[20] = (reg_addr == OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET); + addr_hit[21] = (reg_addr == OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET); + addr_hit[22] = (reg_addr == OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET); + addr_hit[23] = (reg_addr == OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET); + addr_hit[24] = (reg_addr == OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET); + addr_hit[25] = (reg_addr == OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET); + addr_hit[26] = (reg_addr == OTP_CTRL_CHECK_TRIGGER_OFFSET); + addr_hit[27] = (reg_addr == OTP_CTRL_CHECK_REGWEN_OFFSET); + addr_hit[28] = (reg_addr == OTP_CTRL_CHECK_TIMEOUT_OFFSET); + addr_hit[29] = (reg_addr == OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET); + addr_hit[30] = (reg_addr == OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET); + addr_hit[31] = (reg_addr == OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET); + addr_hit[32] = (reg_addr == OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET); + addr_hit[33] = (reg_addr == OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET); + addr_hit[34] = (reg_addr == OTP_CTRL_ROT_CREATOR_AUTH_CODESIGN_READ_LOCK_OFFSET); + addr_hit[35] = (reg_addr == OTP_CTRL_ROT_CREATOR_AUTH_STATE_READ_LOCK_OFFSET); + addr_hit[36] = (reg_addr == OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET); + addr_hit[37] = (reg_addr == OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET); + addr_hit[38] = (reg_addr == OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET); + addr_hit[39] = (reg_addr == OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET); + addr_hit[40] = (reg_addr == OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET); + addr_hit[41] = (reg_addr == OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET); + addr_hit[42] = (reg_addr == OTP_CTRL_ROT_CREATOR_AUTH_CODESIGN_DIGEST_0_OFFSET); + addr_hit[43] = (reg_addr == OTP_CTRL_ROT_CREATOR_AUTH_CODESIGN_DIGEST_1_OFFSET); + addr_hit[44] = (reg_addr == OTP_CTRL_ROT_CREATOR_AUTH_STATE_DIGEST_0_OFFSET); + addr_hit[45] = (reg_addr == OTP_CTRL_ROT_CREATOR_AUTH_STATE_DIGEST_1_OFFSET); + addr_hit[46] = (reg_addr == OTP_CTRL_HW_CFG0_DIGEST_0_OFFSET); + addr_hit[47] = (reg_addr == OTP_CTRL_HW_CFG0_DIGEST_1_OFFSET); + addr_hit[48] = (reg_addr == OTP_CTRL_HW_CFG1_DIGEST_0_OFFSET); + addr_hit[49] = (reg_addr == OTP_CTRL_HW_CFG1_DIGEST_1_OFFSET); + addr_hit[50] = (reg_addr == OTP_CTRL_SECRET0_DIGEST_0_OFFSET); + addr_hit[51] = (reg_addr == OTP_CTRL_SECRET0_DIGEST_1_OFFSET); + addr_hit[52] = (reg_addr == OTP_CTRL_SECRET1_DIGEST_0_OFFSET); + addr_hit[53] = (reg_addr == OTP_CTRL_SECRET1_DIGEST_1_OFFSET); + addr_hit[54] = (reg_addr == OTP_CTRL_SECRET2_DIGEST_0_OFFSET); + addr_hit[55] = (reg_addr == OTP_CTRL_SECRET2_DIGEST_1_OFFSET); + end + + assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; + + // Check sub-word write is permitted + always_comb begin + wr_err = (reg_we & + ((addr_hit[ 0] & (|(OTP_CTRL_CORE_PERMIT[ 0] & ~reg_be))) | + (addr_hit[ 1] & (|(OTP_CTRL_CORE_PERMIT[ 1] & ~reg_be))) | + (addr_hit[ 2] & (|(OTP_CTRL_CORE_PERMIT[ 2] & ~reg_be))) | + (addr_hit[ 3] & (|(OTP_CTRL_CORE_PERMIT[ 3] & ~reg_be))) | + (addr_hit[ 4] & (|(OTP_CTRL_CORE_PERMIT[ 4] & ~reg_be))) | + (addr_hit[ 5] & (|(OTP_CTRL_CORE_PERMIT[ 5] & ~reg_be))) | + (addr_hit[ 6] & (|(OTP_CTRL_CORE_PERMIT[ 6] & ~reg_be))) | + (addr_hit[ 7] & (|(OTP_CTRL_CORE_PERMIT[ 7] & ~reg_be))) | + (addr_hit[ 8] & (|(OTP_CTRL_CORE_PERMIT[ 8] & ~reg_be))) | + (addr_hit[ 9] & (|(OTP_CTRL_CORE_PERMIT[ 9] & ~reg_be))) | + (addr_hit[10] & (|(OTP_CTRL_CORE_PERMIT[10] & ~reg_be))) | + (addr_hit[11] & (|(OTP_CTRL_CORE_PERMIT[11] & ~reg_be))) | + (addr_hit[12] & (|(OTP_CTRL_CORE_PERMIT[12] & ~reg_be))) | + (addr_hit[13] & (|(OTP_CTRL_CORE_PERMIT[13] & ~reg_be))) | + (addr_hit[14] & (|(OTP_CTRL_CORE_PERMIT[14] & ~reg_be))) | + (addr_hit[15] & (|(OTP_CTRL_CORE_PERMIT[15] & ~reg_be))) | + (addr_hit[16] & (|(OTP_CTRL_CORE_PERMIT[16] & ~reg_be))) | + (addr_hit[17] & (|(OTP_CTRL_CORE_PERMIT[17] & ~reg_be))) | + (addr_hit[18] & (|(OTP_CTRL_CORE_PERMIT[18] & ~reg_be))) | + (addr_hit[19] & (|(OTP_CTRL_CORE_PERMIT[19] & ~reg_be))) | + (addr_hit[20] & (|(OTP_CTRL_CORE_PERMIT[20] & ~reg_be))) | + (addr_hit[21] & (|(OTP_CTRL_CORE_PERMIT[21] & ~reg_be))) | + (addr_hit[22] & (|(OTP_CTRL_CORE_PERMIT[22] & ~reg_be))) | + (addr_hit[23] & (|(OTP_CTRL_CORE_PERMIT[23] & ~reg_be))) | + (addr_hit[24] & (|(OTP_CTRL_CORE_PERMIT[24] & ~reg_be))) | + (addr_hit[25] & (|(OTP_CTRL_CORE_PERMIT[25] & ~reg_be))) | + (addr_hit[26] & (|(OTP_CTRL_CORE_PERMIT[26] & ~reg_be))) | + (addr_hit[27] & (|(OTP_CTRL_CORE_PERMIT[27] & ~reg_be))) | + (addr_hit[28] & (|(OTP_CTRL_CORE_PERMIT[28] & ~reg_be))) | + (addr_hit[29] & (|(OTP_CTRL_CORE_PERMIT[29] & ~reg_be))) | + (addr_hit[30] & (|(OTP_CTRL_CORE_PERMIT[30] & ~reg_be))) | + (addr_hit[31] & (|(OTP_CTRL_CORE_PERMIT[31] & ~reg_be))) | + (addr_hit[32] & (|(OTP_CTRL_CORE_PERMIT[32] & ~reg_be))) | + (addr_hit[33] & (|(OTP_CTRL_CORE_PERMIT[33] & ~reg_be))) | + (addr_hit[34] & (|(OTP_CTRL_CORE_PERMIT[34] & ~reg_be))) | + (addr_hit[35] & (|(OTP_CTRL_CORE_PERMIT[35] & ~reg_be))) | + (addr_hit[36] & (|(OTP_CTRL_CORE_PERMIT[36] & ~reg_be))) | + (addr_hit[37] & (|(OTP_CTRL_CORE_PERMIT[37] & ~reg_be))) | + (addr_hit[38] & (|(OTP_CTRL_CORE_PERMIT[38] & ~reg_be))) | + (addr_hit[39] & (|(OTP_CTRL_CORE_PERMIT[39] & ~reg_be))) | + (addr_hit[40] & (|(OTP_CTRL_CORE_PERMIT[40] & ~reg_be))) | + (addr_hit[41] & (|(OTP_CTRL_CORE_PERMIT[41] & ~reg_be))) | + (addr_hit[42] & (|(OTP_CTRL_CORE_PERMIT[42] & ~reg_be))) | + (addr_hit[43] & (|(OTP_CTRL_CORE_PERMIT[43] & ~reg_be))) | + (addr_hit[44] & (|(OTP_CTRL_CORE_PERMIT[44] & ~reg_be))) | + (addr_hit[45] & (|(OTP_CTRL_CORE_PERMIT[45] & ~reg_be))) | + (addr_hit[46] & (|(OTP_CTRL_CORE_PERMIT[46] & ~reg_be))) | + (addr_hit[47] & (|(OTP_CTRL_CORE_PERMIT[47] & ~reg_be))) | + (addr_hit[48] & (|(OTP_CTRL_CORE_PERMIT[48] & ~reg_be))) | + (addr_hit[49] & (|(OTP_CTRL_CORE_PERMIT[49] & ~reg_be))) | + (addr_hit[50] & (|(OTP_CTRL_CORE_PERMIT[50] & ~reg_be))) | + (addr_hit[51] & (|(OTP_CTRL_CORE_PERMIT[51] & ~reg_be))) | + (addr_hit[52] & (|(OTP_CTRL_CORE_PERMIT[52] & ~reg_be))) | + (addr_hit[53] & (|(OTP_CTRL_CORE_PERMIT[53] & ~reg_be))) | + (addr_hit[54] & (|(OTP_CTRL_CORE_PERMIT[54] & ~reg_be))) | + (addr_hit[55] & (|(OTP_CTRL_CORE_PERMIT[55] & ~reg_be))))); + end + + // Generate write-enables + assign intr_state_we = addr_hit[0] & reg_we & !reg_error; + + assign intr_state_otp_operation_done_wd = reg_wdata[0]; + + assign intr_state_otp_error_wd = reg_wdata[1]; + assign intr_enable_we = addr_hit[1] & reg_we & !reg_error; + + assign intr_enable_otp_operation_done_wd = reg_wdata[0]; + + assign intr_enable_otp_error_wd = reg_wdata[1]; + assign intr_test_we = addr_hit[2] & reg_we & !reg_error; + + assign intr_test_otp_operation_done_wd = reg_wdata[0]; + + assign intr_test_otp_error_wd = reg_wdata[1]; + assign alert_test_we = addr_hit[3] & reg_we & !reg_error; + + assign alert_test_fatal_macro_error_wd = reg_wdata[0]; + + assign alert_test_fatal_check_error_wd = reg_wdata[1]; + + assign alert_test_fatal_bus_integ_error_wd = reg_wdata[2]; + + assign alert_test_fatal_prim_otp_alert_wd = reg_wdata[3]; + + assign alert_test_recov_prim_otp_alert_wd = reg_wdata[4]; + assign status_re = addr_hit[4] & reg_re & !reg_error; + assign err_code_0_re = addr_hit[5] & reg_re & !reg_error; + assign err_code_1_re = addr_hit[6] & reg_re & !reg_error; + assign err_code_2_re = addr_hit[7] & reg_re & !reg_error; + assign err_code_3_re = addr_hit[8] & reg_re & !reg_error; + assign err_code_4_re = addr_hit[9] & reg_re & !reg_error; + assign err_code_5_re = addr_hit[10] & reg_re & !reg_error; + assign err_code_6_re = addr_hit[11] & reg_re & !reg_error; + assign err_code_7_re = addr_hit[12] & reg_re & !reg_error; + assign err_code_8_re = addr_hit[13] & reg_re & !reg_error; + assign err_code_9_re = addr_hit[14] & reg_re & !reg_error; + assign err_code_10_re = addr_hit[15] & reg_re & !reg_error; + assign err_code_11_re = addr_hit[16] & reg_re & !reg_error; + assign err_code_12_re = addr_hit[17] & reg_re & !reg_error; + assign direct_access_regwen_re = addr_hit[18] & reg_re & !reg_error; + assign direct_access_regwen_we = addr_hit[18] & reg_we & !reg_error; + + assign direct_access_regwen_wd = reg_wdata[0]; + assign direct_access_cmd_we = addr_hit[19] & reg_we & !reg_error; + + assign direct_access_cmd_rd_wd = reg_wdata[0]; + + assign direct_access_cmd_wr_wd = reg_wdata[1]; + + assign direct_access_cmd_digest_wd = reg_wdata[2]; + assign direct_access_address_we = addr_hit[20] & reg_we & !reg_error; + + assign direct_access_address_wd = reg_wdata[10:0]; + assign direct_access_wdata_0_we = addr_hit[21] & reg_we & !reg_error; + + assign direct_access_wdata_0_wd = reg_wdata[31:0]; + assign direct_access_wdata_1_we = addr_hit[22] & reg_we & !reg_error; + + assign direct_access_wdata_1_wd = reg_wdata[31:0]; + assign direct_access_rdata_0_re = addr_hit[23] & reg_re & !reg_error; + assign direct_access_rdata_1_re = addr_hit[24] & reg_re & !reg_error; + assign check_trigger_regwen_we = addr_hit[25] & reg_we & !reg_error; + + assign check_trigger_regwen_wd = reg_wdata[0]; + assign check_trigger_we = addr_hit[26] & reg_we & !reg_error; + + assign check_trigger_integrity_wd = reg_wdata[0]; + + assign check_trigger_consistency_wd = reg_wdata[1]; + assign check_regwen_we = addr_hit[27] & reg_we & !reg_error; + + assign check_regwen_wd = reg_wdata[0]; + assign check_timeout_we = addr_hit[28] & reg_we & !reg_error; + + assign check_timeout_wd = reg_wdata[31:0]; + assign integrity_check_period_we = addr_hit[29] & reg_we & !reg_error; + + assign integrity_check_period_wd = reg_wdata[31:0]; + assign consistency_check_period_we = addr_hit[30] & reg_we & !reg_error; + + assign consistency_check_period_wd = reg_wdata[31:0]; + assign vendor_test_read_lock_we = addr_hit[31] & reg_we & !reg_error; + + assign vendor_test_read_lock_wd = reg_wdata[0]; + assign creator_sw_cfg_read_lock_we = addr_hit[32] & reg_we & !reg_error; + + assign creator_sw_cfg_read_lock_wd = reg_wdata[0]; + assign owner_sw_cfg_read_lock_we = addr_hit[33] & reg_we & !reg_error; + + assign owner_sw_cfg_read_lock_wd = reg_wdata[0]; + assign rot_creator_auth_codesign_read_lock_we = addr_hit[34] & reg_we & !reg_error; + + assign rot_creator_auth_codesign_read_lock_wd = reg_wdata[0]; + assign rot_creator_auth_state_read_lock_we = addr_hit[35] & reg_we & !reg_error; + + assign rot_creator_auth_state_read_lock_wd = reg_wdata[0]; + assign vendor_test_digest_0_re = addr_hit[36] & reg_re & !reg_error; + assign vendor_test_digest_1_re = addr_hit[37] & reg_re & !reg_error; + assign creator_sw_cfg_digest_0_re = addr_hit[38] & reg_re & !reg_error; + assign creator_sw_cfg_digest_1_re = addr_hit[39] & reg_re & !reg_error; + assign owner_sw_cfg_digest_0_re = addr_hit[40] & reg_re & !reg_error; + assign owner_sw_cfg_digest_1_re = addr_hit[41] & reg_re & !reg_error; + assign rot_creator_auth_codesign_digest_0_re = addr_hit[42] & reg_re & !reg_error; + assign rot_creator_auth_codesign_digest_1_re = addr_hit[43] & reg_re & !reg_error; + assign rot_creator_auth_state_digest_0_re = addr_hit[44] & reg_re & !reg_error; + assign rot_creator_auth_state_digest_1_re = addr_hit[45] & reg_re & !reg_error; + assign hw_cfg0_digest_0_re = addr_hit[46] & reg_re & !reg_error; + assign hw_cfg0_digest_1_re = addr_hit[47] & reg_re & !reg_error; + assign hw_cfg1_digest_0_re = addr_hit[48] & reg_re & !reg_error; + assign hw_cfg1_digest_1_re = addr_hit[49] & reg_re & !reg_error; + assign secret0_digest_0_re = addr_hit[50] & reg_re & !reg_error; + assign secret0_digest_1_re = addr_hit[51] & reg_re & !reg_error; + assign secret1_digest_0_re = addr_hit[52] & reg_re & !reg_error; + assign secret1_digest_1_re = addr_hit[53] & reg_re & !reg_error; + assign secret2_digest_0_re = addr_hit[54] & reg_re & !reg_error; + assign secret2_digest_1_re = addr_hit[55] & reg_re & !reg_error; + + // Assign write-enables to checker logic vector. + always_comb begin + reg_we_check = '0; + reg_we_check[0] = intr_state_we; + reg_we_check[1] = intr_enable_we; + reg_we_check[2] = intr_test_we; + reg_we_check[3] = alert_test_we; + reg_we_check[4] = 1'b0; + reg_we_check[5] = 1'b0; + reg_we_check[6] = 1'b0; + reg_we_check[7] = 1'b0; + reg_we_check[8] = 1'b0; + reg_we_check[9] = 1'b0; + reg_we_check[10] = 1'b0; + reg_we_check[11] = 1'b0; + reg_we_check[12] = 1'b0; + reg_we_check[13] = 1'b0; + reg_we_check[14] = 1'b0; + reg_we_check[15] = 1'b0; + reg_we_check[16] = 1'b0; + reg_we_check[17] = 1'b0; + reg_we_check[18] = direct_access_regwen_we; + reg_we_check[19] = direct_access_cmd_gated_we; + reg_we_check[20] = direct_access_address_gated_we; + reg_we_check[21] = direct_access_wdata_0_gated_we; + reg_we_check[22] = direct_access_wdata_1_gated_we; + reg_we_check[23] = 1'b0; + reg_we_check[24] = 1'b0; + reg_we_check[25] = check_trigger_regwen_we; + reg_we_check[26] = check_trigger_gated_we; + reg_we_check[27] = check_regwen_we; + reg_we_check[28] = check_timeout_gated_we; + reg_we_check[29] = integrity_check_period_gated_we; + reg_we_check[30] = consistency_check_period_gated_we; + reg_we_check[31] = vendor_test_read_lock_gated_we; + reg_we_check[32] = creator_sw_cfg_read_lock_gated_we; + reg_we_check[33] = owner_sw_cfg_read_lock_gated_we; + reg_we_check[34] = rot_creator_auth_codesign_read_lock_gated_we; + reg_we_check[35] = rot_creator_auth_state_read_lock_gated_we; + reg_we_check[36] = 1'b0; + reg_we_check[37] = 1'b0; + reg_we_check[38] = 1'b0; + reg_we_check[39] = 1'b0; + reg_we_check[40] = 1'b0; + reg_we_check[41] = 1'b0; + reg_we_check[42] = 1'b0; + reg_we_check[43] = 1'b0; + reg_we_check[44] = 1'b0; + reg_we_check[45] = 1'b0; + reg_we_check[46] = 1'b0; + reg_we_check[47] = 1'b0; + reg_we_check[48] = 1'b0; + reg_we_check[49] = 1'b0; + reg_we_check[50] = 1'b0; + reg_we_check[51] = 1'b0; + reg_we_check[52] = 1'b0; + reg_we_check[53] = 1'b0; + reg_we_check[54] = 1'b0; + reg_we_check[55] = 1'b0; + end + + // Read data return + always_comb begin + reg_rdata_next = '0; + unique case (1'b1) + addr_hit[0]: begin + reg_rdata_next[0] = intr_state_otp_operation_done_qs; + reg_rdata_next[1] = intr_state_otp_error_qs; + end + + addr_hit[1]: begin + reg_rdata_next[0] = intr_enable_otp_operation_done_qs; + reg_rdata_next[1] = intr_enable_otp_error_qs; + end + + addr_hit[2]: begin + reg_rdata_next[0] = '0; + reg_rdata_next[1] = '0; + end + + addr_hit[3]: begin + reg_rdata_next[0] = '0; + reg_rdata_next[1] = '0; + reg_rdata_next[2] = '0; + reg_rdata_next[3] = '0; + reg_rdata_next[4] = '0; + end + + addr_hit[4]: begin + reg_rdata_next[0] = status_vendor_test_error_qs; + reg_rdata_next[1] = status_creator_sw_cfg_error_qs; + reg_rdata_next[2] = status_owner_sw_cfg_error_qs; + reg_rdata_next[3] = status_rot_creator_auth_codesign_error_qs; + reg_rdata_next[4] = status_rot_creator_auth_state_error_qs; + reg_rdata_next[5] = status_hw_cfg0_error_qs; + reg_rdata_next[6] = status_hw_cfg1_error_qs; + reg_rdata_next[7] = status_secret0_error_qs; + reg_rdata_next[8] = status_secret1_error_qs; + reg_rdata_next[9] = status_secret2_error_qs; + reg_rdata_next[10] = status_life_cycle_error_qs; + reg_rdata_next[11] = status_dai_error_qs; + reg_rdata_next[12] = status_lci_error_qs; + reg_rdata_next[13] = status_timeout_error_qs; + reg_rdata_next[14] = status_lfsr_fsm_error_qs; + reg_rdata_next[15] = status_scrambling_fsm_error_qs; + reg_rdata_next[16] = status_key_deriv_fsm_error_qs; + reg_rdata_next[17] = status_bus_integ_error_qs; + reg_rdata_next[18] = status_dai_idle_qs; + reg_rdata_next[19] = status_check_pending_qs; + end + + addr_hit[5]: begin + reg_rdata_next[2:0] = err_code_0_qs; + end + + addr_hit[6]: begin + reg_rdata_next[2:0] = err_code_1_qs; + end + + addr_hit[7]: begin + reg_rdata_next[2:0] = err_code_2_qs; + end + + addr_hit[8]: begin + reg_rdata_next[2:0] = err_code_3_qs; + end + + addr_hit[9]: begin + reg_rdata_next[2:0] = err_code_4_qs; + end + + addr_hit[10]: begin + reg_rdata_next[2:0] = err_code_5_qs; + end + + addr_hit[11]: begin + reg_rdata_next[2:0] = err_code_6_qs; + end + + addr_hit[12]: begin + reg_rdata_next[2:0] = err_code_7_qs; + end + + addr_hit[13]: begin + reg_rdata_next[2:0] = err_code_8_qs; + end + + addr_hit[14]: begin + reg_rdata_next[2:0] = err_code_9_qs; + end + + addr_hit[15]: begin + reg_rdata_next[2:0] = err_code_10_qs; + end + + addr_hit[16]: begin + reg_rdata_next[2:0] = err_code_11_qs; + end + + addr_hit[17]: begin + reg_rdata_next[2:0] = err_code_12_qs; + end + + addr_hit[18]: begin + reg_rdata_next[0] = direct_access_regwen_qs; + end + + addr_hit[19]: begin + reg_rdata_next[0] = '0; + reg_rdata_next[1] = '0; + reg_rdata_next[2] = '0; + end + + addr_hit[20]: begin + reg_rdata_next[10:0] = direct_access_address_qs; + end + + addr_hit[21]: begin + reg_rdata_next[31:0] = direct_access_wdata_0_qs; + end + + addr_hit[22]: begin + reg_rdata_next[31:0] = direct_access_wdata_1_qs; + end + + addr_hit[23]: begin + reg_rdata_next[31:0] = direct_access_rdata_0_qs; + end + + addr_hit[24]: begin + reg_rdata_next[31:0] = direct_access_rdata_1_qs; + end + + addr_hit[25]: begin + reg_rdata_next[0] = check_trigger_regwen_qs; + end + + addr_hit[26]: begin + reg_rdata_next[0] = '0; + reg_rdata_next[1] = '0; + end + + addr_hit[27]: begin + reg_rdata_next[0] = check_regwen_qs; + end + + addr_hit[28]: begin + reg_rdata_next[31:0] = check_timeout_qs; + end + + addr_hit[29]: begin + reg_rdata_next[31:0] = integrity_check_period_qs; + end + + addr_hit[30]: begin + reg_rdata_next[31:0] = consistency_check_period_qs; + end + + addr_hit[31]: begin + reg_rdata_next[0] = vendor_test_read_lock_qs; + end + + addr_hit[32]: begin + reg_rdata_next[0] = creator_sw_cfg_read_lock_qs; + end + + addr_hit[33]: begin + reg_rdata_next[0] = owner_sw_cfg_read_lock_qs; + end + + addr_hit[34]: begin + reg_rdata_next[0] = rot_creator_auth_codesign_read_lock_qs; + end + + addr_hit[35]: begin + reg_rdata_next[0] = rot_creator_auth_state_read_lock_qs; + end + + addr_hit[36]: begin + reg_rdata_next[31:0] = vendor_test_digest_0_qs; + end + + addr_hit[37]: begin + reg_rdata_next[31:0] = vendor_test_digest_1_qs; + end + + addr_hit[38]: begin + reg_rdata_next[31:0] = creator_sw_cfg_digest_0_qs; + end + + addr_hit[39]: begin + reg_rdata_next[31:0] = creator_sw_cfg_digest_1_qs; + end + + addr_hit[40]: begin + reg_rdata_next[31:0] = owner_sw_cfg_digest_0_qs; + end + + addr_hit[41]: begin + reg_rdata_next[31:0] = owner_sw_cfg_digest_1_qs; + end + + addr_hit[42]: begin + reg_rdata_next[31:0] = rot_creator_auth_codesign_digest_0_qs; + end + + addr_hit[43]: begin + reg_rdata_next[31:0] = rot_creator_auth_codesign_digest_1_qs; + end + + addr_hit[44]: begin + reg_rdata_next[31:0] = rot_creator_auth_state_digest_0_qs; + end + + addr_hit[45]: begin + reg_rdata_next[31:0] = rot_creator_auth_state_digest_1_qs; + end + + addr_hit[46]: begin + reg_rdata_next[31:0] = hw_cfg0_digest_0_qs; + end + + addr_hit[47]: begin + reg_rdata_next[31:0] = hw_cfg0_digest_1_qs; + end + + addr_hit[48]: begin + reg_rdata_next[31:0] = hw_cfg1_digest_0_qs; + end + + addr_hit[49]: begin + reg_rdata_next[31:0] = hw_cfg1_digest_1_qs; + end + + addr_hit[50]: begin + reg_rdata_next[31:0] = secret0_digest_0_qs; + end + + addr_hit[51]: begin + reg_rdata_next[31:0] = secret0_digest_1_qs; + end + + addr_hit[52]: begin + reg_rdata_next[31:0] = secret1_digest_0_qs; + end + + addr_hit[53]: begin + reg_rdata_next[31:0] = secret1_digest_1_qs; + end + + addr_hit[54]: begin + reg_rdata_next[31:0] = secret2_digest_0_qs; + end + + addr_hit[55]: begin + reg_rdata_next[31:0] = secret2_digest_1_qs; + end + + default: begin + reg_rdata_next = '1; + end + endcase + end + + // shadow busy + logic shadow_busy; + assign shadow_busy = 1'b0; + + // register busy + assign reg_busy = shadow_busy; + + // Unused signal tieoff + + // wdata / byte enable are not always fully used + // add a blanket unused statement to handle lint waivers + logic unused_wdata; + logic unused_be; + assign unused_wdata = ^reg_wdata; + assign unused_be = ^reg_be; + + // Assertions for Register Interface + `CALIPTRA_ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni) + `CALIPTRA_ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni) + + `CALIPTRA_ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o_pre.d_valid, clk_i, !rst_ni) + + `CALIPTRA_ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni) + + // this is formulated as an assumption such that the FPV testbenches do disprove this + // property by mistake + //`ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.chk_en == tlul_pkg::CheckDis) + +endmodule diff --git a/src/fuse_ctrl/rtl/otp_ctrl_dai.sv b/src/fuse_ctrl/rtl/otp_ctrl_dai.sv new file mode 100644 index 0000000..b264fd0 --- /dev/null +++ b/src/fuse_ctrl/rtl/otp_ctrl_dai.sv @@ -0,0 +1,858 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Direct access interface for OTP controller. +// + +`include "caliptra_prim_flop_macros.sv" + +module otp_ctrl_dai + import otp_ctrl_pkg::*; + import otp_ctrl_reg_pkg::*; + import otp_ctrl_part_pkg::*; +( + input clk_i, + input rst_ni, + // Init reqest from power manager + input init_req_i, + output logic init_done_o, + // Init request going to partitions + output logic part_init_req_o, + input [NumPart-1:0] part_init_done_i, + // Escalation input. This moves the FSM into a terminal state and locks down + // the DAI. + input caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_t escalate_en_i, + // Output error state of DAI, to be consumed by OTP error/alert logic. + // Note that most errors are not recoverable and move the DAI FSM into + // a terminal error state. + output otp_err_e error_o, + // This error signal is pulsed high if the FSM has been glitched into an invalid state. + // Although it is somewhat redundant with the error code in error_o above, it is + // meant to cover cases where we already latched an error code while the FSM is + // glitched into an invalid state (since in that case, the error code will not be + // overridden with the FSM error code so that the original error code is still + // discoverable). + output logic fsm_err_o, + // Access/lock status from partitions + // SEC_CM: ACCESS.CTRL.MUBI + input part_access_t [NumPart-1:0] part_access_i, + // CSR interface + input [OtpByteAddrWidth-1:0] dai_addr_i, + input dai_cmd_e dai_cmd_i, + input logic dai_req_i, + input [NumDaiWords-1:0][31:0] dai_wdata_i, + output logic dai_idle_o, // wired to the status CSRs + output logic dai_prog_idle_o, // wired to lfsr timer and pwrmgr + output logic dai_cmd_done_o, // this is used to raise an IRQ + output logic [NumDaiWords-1:0][31:0] dai_rdata_o, + // OTP interface + output logic otp_req_o, + output caliptra_prim_otp_pkg::cmd_e otp_cmd_o, + output logic [OtpSizeWidth-1:0] otp_size_o, + output logic [OtpIfWidth-1:0] otp_wdata_o, + output logic [OtpAddrWidth-1:0] otp_addr_o, + input otp_gnt_i, + input otp_rvalid_i, + input [ScrmblBlockWidth-1:0] otp_rdata_i, + input caliptra_prim_otp_pkg::err_e otp_err_i, + // Scrambling mutex request + output logic scrmbl_mtx_req_o, + input scrmbl_mtx_gnt_i, + // Scrambling datapath interface + output otp_scrmbl_cmd_e scrmbl_cmd_o, + output digest_mode_e scrmbl_mode_o, + output logic [ConstSelWidth-1:0] scrmbl_sel_o, + output logic [ScrmblBlockWidth-1:0] scrmbl_data_o, + output logic scrmbl_valid_o, + input logic scrmbl_ready_i, + input logic scrmbl_valid_i, + input logic [ScrmblBlockWidth-1:0] scrmbl_data_i +); + + //////////////////////// + // Integration Checks // + //////////////////////// + + import caliptra_prim_mubi_pkg::*; + import caliptra_prim_util_pkg::vbits; + + localparam int CntWidth = OtpByteAddrWidth - $clog2(ScrmblBlockWidth/8); + + // Integration checks for parameters. + `CALIPTRA_ASSERT_INIT(CheckNativeOtpWidth0_A, (ScrmblBlockWidth % OtpWidth) == 0) + `CALIPTRA_ASSERT_INIT(CheckNativeOtpWidth1_A, (32 % OtpWidth) == 0) + + ///////////////////// + // DAI Control FSM // + ///////////////////// + + // SEC_CM: DAI.FSM.SPARSE + // Encoding generated with: + // $ ./util/design/sparse-fsm-encode.py -d 5 -m 20 -n 12 \ + // -s 3011551511 --language=sv + // + // Hamming distance histogram: + // + // 0: -- + // 1: -- + // 2: -- + // 3: -- + // 4: -- + // 5: |||||||||||||||| (31.05%) + // 6: |||||||||||||||||||| (36.84%) + // 7: |||||||| (15.26%) + // 8: |||| (8.95%) + // 9: || (5.26%) + // 10: (1.58%) + // 11: (1.05%) + // 12: -- + // + // Minimum Hamming distance: 5 + // Maximum Hamming distance: 11 + // Minimum Hamming weight: 2 + // Maximum Hamming weight: 9 + // + localparam int StateWidth = 12; + typedef enum logic [StateWidth-1:0] { + ResetSt = 12'b101111010100, + InitOtpSt = 12'b110000110010, + InitPartSt = 12'b000111111001, + IdleSt = 12'b111010000011, + ErrorSt = 12'b100010001110, + ReadSt = 12'b100101100110, + ReadWaitSt = 12'b001100000000, + DescrSt = 12'b011000101111, + DescrWaitSt = 12'b110101011111, + WriteSt = 12'b110111001000, + WriteWaitSt = 12'b111001111100, + ScrSt = 12'b000000010101, + ScrWaitSt = 12'b010110110100, + DigClrSt = 12'b001111001111, + DigReadSt = 12'b001001110011, + DigReadWaitSt = 12'b101110111010, + DigSt = 12'b011111100010, + DigPadSt = 12'b011010011000, + DigFinSt = 12'b110011100101, + DigWaitSt = 12'b100000101001 + } state_e; + + typedef enum logic [1:0] { + OtpData = 2'b00, + DaiData = 2'b01, + ScrmblData = 2'b10 + } data_sel_e; + + + typedef enum logic { + PartOffset = 1'b0, + DaiOffset = 1'b1 + } addr_sel_e; + + state_e state_d, state_q; + logic [CntWidth-1:0] cnt; + logic cnt_en, cnt_clr, cnt_err; + otp_err_e error_d, error_q; + logic data_en, data_clr; + data_sel_e data_sel; + addr_sel_e base_sel_d, base_sel_q; + logic [ScrmblBlockWidth-1:0] data_q; + logic [NumPartWidth-1:0] part_idx; + logic [NumPart-1:0][OtpAddrWidth-1:0] digest_addr_lut; + logic part_sel_valid; + + // Depending on the partition configuration, the wrapper is instructed to ignore integrity + // calculations and checks. To be on the safe side, the partition filters error responses at this + // point and does not report any integrity errors if integrity is disabled. + otp_err_e otp_err; + always_comb begin + otp_err = otp_err_e'(otp_err_i); + if (!PartInfo[part_idx].integrity && + otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}) begin + otp_err = NoError; + end + end + + // Output partition error state. + assign error_o = error_q; + // Working register is connected to data outputs. + assign otp_wdata_o = data_q; + assign scrmbl_data_o = data_q; + // Only expose this working register in IdleSt. + // The FSM below makes sure to clear this register + // after digest and write ops. + assign dai_rdata_o = (state_q == IdleSt) ? data_q : '0; + + always_comb begin : p_fsm + state_d = state_q; + + // Init signals + init_done_o = 1'b1; + part_init_req_o = 1'b0; + + // DAI signals + dai_idle_o = 1'b0; + dai_prog_idle_o = 1'b1; + dai_cmd_done_o = 1'b0; + + // OTP signals + otp_req_o = 1'b0; + otp_cmd_o = caliptra_prim_otp_pkg::Init; + + // Scrambling mutex + scrmbl_mtx_req_o = 1'b0; + + // Scrambling datapath + scrmbl_cmd_o = LoadShadow; + scrmbl_sel_o = CnstyDigest; + scrmbl_mode_o = StandardMode; + scrmbl_valid_o = 1'b0; + + // Counter + cnt_en = 1'b0; + cnt_clr = 1'b0; + base_sel_d = base_sel_q; + + // Temporary data register + data_en = 1'b0; + data_clr = 1'b0; + data_sel = OtpData; + + // Error Register + error_d = error_q; + fsm_err_o = 1'b0; + + unique case (state_q) + /////////////////////////////////////////////////////////////////// + // We get here after reset and wait until the power manager + // requests OTP initialization. If initialization is requested, + // an init command is written to the OTP macro, and we move on + // to the InitOtpSt waiting state. + ResetSt: begin + init_done_o = 1'b0; + dai_prog_idle_o = 1'b0; + data_clr = 1'b1; + if (init_req_i) begin + otp_req_o = 1'b1; + if (otp_gnt_i) begin + state_d = InitOtpSt; + end + end + end + /////////////////////////////////////////////////////////////////// + // We wait here unitl the OTP macro has initialized without + // error. If an error occurred during this stage, we latch that + // error and move into a terminal error state. + InitOtpSt: begin + init_done_o = 1'b0; + dai_prog_idle_o = 1'b0; + if (otp_rvalid_i) begin + if ((!(otp_err inside {NoError, MacroEccCorrError}))) begin + state_d = ErrorSt; + error_d = otp_err; + end else begin + state_d = InitPartSt; + end + end + end + /////////////////////////////////////////////////////////////////// + // Since the OTP macro is now functional, we can send out an + // initialization request to all partitions and wait until they + // all have initialized. + InitPartSt: begin + init_done_o = 1'b0; + dai_prog_idle_o = 1'b0; + part_init_req_o = 1'b1; + if (part_init_done_i == {NumPart{1'b1}}) begin + state_d = IdleSt; + end + end + /////////////////////////////////////////////////////////////////// + // Idle state where we wait for incoming commands. + // Invalid commands trigger a CmdInvErr, which is recoverable. + IdleSt: begin + dai_idle_o = 1'b1; + if (dai_req_i) begin + // This clears previous (recoverable) and reset the counter. + error_d = NoError; + cnt_clr = 1'b1; + unique case (dai_cmd_i) + DaiRead: begin + state_d = ReadSt; + // Clear the temporary data register. + data_clr = 1'b1; + base_sel_d = DaiOffset; + end + DaiWrite: begin + data_sel = DaiData; + // Fetch data block. + data_en = 1'b1; + base_sel_d = DaiOffset; + // If this partition is scrambled, directly go to write scrambling first. + if (PartInfo[part_idx].secret) begin + state_d = ScrSt; + end else begin + state_d = WriteSt; + end + end + DaiDigest: begin + state_d = DigClrSt; + scrmbl_mtx_req_o = 1'b1; + base_sel_d = PartOffset; + end + default: ; // Ignore invalid commands + endcase // dai_cmd_i + end // dai_req_i + end + /////////////////////////////////////////////////////////////////// + // Each time we request a block of data from OTP, we re-check + // whether read access has been locked for this partition. If + // that is the case, we immediately bail out. Otherwise, we + // request a block of data from OTP. + ReadSt: begin + if (part_sel_valid && (mubi8_test_false_strict(part_access_i[part_idx].read_lock) || + // HW digests always remain readable. + PartInfo[part_idx].hw_digest && otp_addr_o == + digest_addr_lut[part_idx])) begin + otp_req_o = 1'b1; + // Depending on the partition configuration, + // the wrapper is instructed to ignore integrity errors. + if (PartInfo[part_idx].integrity) begin + otp_cmd_o = caliptra_prim_otp_pkg::Read; + end else begin + otp_cmd_o = caliptra_prim_otp_pkg::ReadRaw; + end + if (otp_gnt_i) begin + state_d = ReadWaitSt; + end + end else begin + state_d = IdleSt; + error_d = AccessError; // Signal this error, but do not go into terminal error state. + dai_cmd_done_o = 1'b1; + end + end + /////////////////////////////////////////////////////////////////// + // Wait for OTP response and write to readout register. Check + // whether descrambling is required or not. In case an OTP + // transaction fails, latch the OTP error code, and jump to + // terminal error state. + ReadWaitSt: begin + // Continuously check read access and bail out if this is not consistent. + if (part_sel_valid && (mubi8_test_false_strict(part_access_i[part_idx].read_lock) || + // HW digests always remain readable. + PartInfo[part_idx].hw_digest && otp_addr_o == + digest_addr_lut[part_idx])) begin + if (otp_rvalid_i) begin + // Check OTP return code. + if (otp_err inside {NoError, MacroEccCorrError}) begin + data_en = 1'b1; + // We do not need to descramble the digest values. + if (PartInfo[part_idx].secret && otp_addr_o != digest_addr_lut[part_idx]) begin + state_d = DescrSt; + end else begin + state_d = IdleSt; + dai_cmd_done_o = 1'b1; + end + // At this point the only error that we could have gotten are correctable ECC errors. + if (otp_err != NoError) begin + error_d = MacroEccCorrError; + end + end else begin + state_d = ErrorSt; + error_d = otp_err; + end + end + // At this point, this check MUST succeed - otherwise this means that + // there was a tampering attempt. Hence we go into a terminal error state + // when this check fails. + end else begin + state_d = ErrorSt; + error_d = FsmStateError; + end + end + /////////////////////////////////////////////////////////////////// + // Descrambling state. This first acquires the scrambling + // datapath mutex. Note that once the mutex is acquired, we have + // exclusive access to the scrambling datapath until we release + // the mutex by deasserting scrmbl_mtx_req_o. + // SEC_CM: SECRET.MEM.SCRAMBLE + DescrSt: begin + scrmbl_mtx_req_o = 1'b1; + scrmbl_valid_o = 1'b1; + scrmbl_cmd_o = Decrypt; + scrmbl_sel_o = PartInfo[part_idx].key_sel; + if (scrmbl_mtx_gnt_i && scrmbl_ready_i) begin + state_d = DescrWaitSt; + end + end + /////////////////////////////////////////////////////////////////// + // Wait for the descrambled data to return. Note that we release + // the mutex lock upon leaving this state. + // SEC_CM: SECRET.MEM.SCRAMBLE + DescrWaitSt: begin + scrmbl_mtx_req_o = 1'b1; + scrmbl_sel_o = PartInfo[part_idx].key_sel; + data_sel = ScrmblData; + if (scrmbl_valid_i) begin + state_d = IdleSt; + data_en = 1'b1; + dai_cmd_done_o = 1'b1; + end + end + /////////////////////////////////////////////////////////////////// + // First, check whether write accesses are allowed to this + // partition, and error out otherwise. Note that for buffered + // partitions, we do not allow DAI writes to the digest offset. + // Unbuffered partitions have SW managed digests, hence that + // check is not needed in that case. The LC partition is + // permanently write locked and can hence not be written via the DAI. + WriteSt: begin + dai_prog_idle_o = 1'b0; + if (part_sel_valid && mubi8_test_false_strict(part_access_i[part_idx].write_lock) && + // If this is a HW digest write to a buffered partition. + ((PartInfo[part_idx].variant == Buffered && PartInfo[part_idx].hw_digest && + base_sel_q == PartOffset && otp_addr_o == digest_addr_lut[part_idx]) || + // If this is a non HW digest write to a buffered partition. + (PartInfo[part_idx].variant == Buffered && PartInfo[part_idx].hw_digest && + base_sel_q == DaiOffset && otp_addr_o < digest_addr_lut[part_idx]) || + // If this is a write to an unbuffered partition + (PartInfo[part_idx].variant != Buffered && base_sel_q == DaiOffset))) begin + otp_req_o = 1'b1; + // Depending on the partition configuration, + // the wrapper is instructed to ignore integrity errors. + if (PartInfo[part_idx].integrity) begin + otp_cmd_o = caliptra_prim_otp_pkg::Write; + end else begin + otp_cmd_o = caliptra_prim_otp_pkg::WriteRaw; + end + if (otp_gnt_i) begin + state_d = WriteWaitSt; + end + end else begin + // Clear working register state. + data_clr = 1'b1; + state_d = IdleSt; + error_d = AccessError; // Signal this error, but do not go into terminal error state. + dai_cmd_done_o = 1'b1; + end + end + /////////////////////////////////////////////////////////////////// + // Wait for OTP response, and then go back to idle. In case an + // OTP transaction fails, latch the OTP error code, and jump to + // terminal error state. + WriteWaitSt: begin + dai_prog_idle_o = 1'b0; + // Continuously check write access and bail out if this is not consistent. + if (part_sel_valid && mubi8_test_false_strict(part_access_i[part_idx].write_lock) && + // If this is a HW digest write to a buffered partition. + ((PartInfo[part_idx].variant == Buffered && PartInfo[part_idx].hw_digest && + base_sel_q == PartOffset && otp_addr_o == digest_addr_lut[part_idx]) || + // If this is a non HW digest write to a buffered partition. + (PartInfo[part_idx].variant == Buffered && PartInfo[part_idx].hw_digest && + base_sel_q == DaiOffset && otp_addr_o < digest_addr_lut[part_idx]) || + // If this is a write to an unbuffered partition + (PartInfo[part_idx].variant != Buffered && base_sel_q == DaiOffset))) begin + + if (otp_rvalid_i) begin + // Check OTP return code. Note that non-blank errors are recoverable. + if ((!(otp_err inside {NoError, MacroWriteBlankError}))) begin + state_d = ErrorSt; + error_d = otp_err; + end else begin + // Clear working register state. + data_clr = 1'b1; + state_d = IdleSt; + dai_cmd_done_o = 1'b1; + // Signal non-blank state, but do not go to terminal error state. + if (otp_err == MacroWriteBlankError) begin + error_d = otp_err; + end + end + end + // At this point, this check MUST succeed - otherwise this means that + // there was a tampering attempt. Hence we go into a terminal error state + // when this check fails. + end else begin + state_d = ErrorSt; + error_d = FsmStateError; + end + end + /////////////////////////////////////////////////////////////////// + // Scrambling state. This first acquires the scrambling + // datapath mutex. Note that once the mutex is acquired, we have + // exclusive access to the scrambling datapath until we release + // the mutex by deasserting scrmbl_mtx_req_o. + // SEC_CM: SECRET.MEM.SCRAMBLE + ScrSt: begin + scrmbl_mtx_req_o = 1'b1; + // Check write access and bail out if this is not consistent. + if (part_sel_valid && mubi8_test_false_strict(part_access_i[part_idx].write_lock) && + // If this is a non HW digest write to a buffered partition. + (PartInfo[part_idx].variant == Buffered && PartInfo[part_idx].secret && + PartInfo[part_idx].hw_digest && base_sel_q == DaiOffset && + otp_addr_o < digest_addr_lut[part_idx])) begin + + scrmbl_valid_o = 1'b1; + scrmbl_cmd_o = Encrypt; + scrmbl_sel_o = PartInfo[part_idx].key_sel; + if (scrmbl_mtx_gnt_i && scrmbl_ready_i) begin + state_d = ScrWaitSt; + end + end else begin + state_d = IdleSt; + error_d = AccessError; // Signal this error, but do not go into terminal error state. + dai_cmd_done_o = 1'b1; + end + end + /////////////////////////////////////////////////////////////////// + // Wait for the scrambled data to return. Note that we release + // the mutex lock upon leaving this state. + // SEC_CM: SECRET.MEM.SCRAMBLE + ScrWaitSt: begin + scrmbl_mtx_req_o = 1'b1; + // Continously check write access and bail out if this is not consistent. + if (part_sel_valid && mubi8_test_false_strict(part_access_i[part_idx].write_lock) && + // If this is a non HW digest write to a buffered partition. + (PartInfo[part_idx].variant == Buffered && PartInfo[part_idx].secret && + PartInfo[part_idx].hw_digest && base_sel_q == DaiOffset && + otp_addr_o < digest_addr_lut[part_idx])) begin + data_sel = ScrmblData; + if (scrmbl_valid_i) begin + state_d = WriteSt; + data_en = 1'b1; + end + // At this point, this check MUST succeed - otherwise this means that + // there was a tampering attempt. Hence we go into a terminal error state + // when this check fails. + end else begin + state_d = ErrorSt; + error_d = FsmStateError; + end + end + /////////////////////////////////////////////////////////////////// + // First, acquire the mutex for the digest and clear the digest state. + // SEC_CM: PART.MEM.DIGEST + DigClrSt: begin + scrmbl_mtx_req_o = 1'b1; + scrmbl_valid_o = 1'b1; + // Need to reset the digest state and set digest mode to "standard". + scrmbl_cmd_o = DigestInit; + if (scrmbl_mtx_gnt_i && scrmbl_ready_i) begin + state_d = DigReadSt; + end + end + /////////////////////////////////////////////////////////////////// + // This requests a 64bit block to be pushed into the digest datapath. + // We also check here whether the partition has been write locked. + // SEC_CM: PART.MEM.DIGEST + DigReadSt: begin + scrmbl_mtx_req_o = 1'b1; + if (part_sel_valid && + mubi8_test_false_strict(part_access_i[part_idx].read_lock) && + mubi8_test_false_strict(part_access_i[part_idx].write_lock)) begin + otp_req_o = 1'b1; + // Depending on the partition configuration, + // the wrapper is instructed to ignore integrity errors. + if (PartInfo[part_idx].integrity) begin + otp_cmd_o = caliptra_prim_otp_pkg::Read; + end else begin + otp_cmd_o = caliptra_prim_otp_pkg::ReadRaw; + end + if (otp_gnt_i) begin + state_d = DigReadWaitSt; + end + end else begin + state_d = IdleSt; + error_d = AccessError; // Signal this error, but do not go into terminal error state. + dai_cmd_done_o = 1'b1; + end + end + /////////////////////////////////////////////////////////////////// + // Wait for OTP response and write to readout register. Check + // whether descrambling is required or not. In case an OTP + // transaction fails, latch the OTP error code, and jump to + // terminal error state. + // SEC_CM: PART.MEM.DIGEST + DigReadWaitSt: begin + scrmbl_mtx_req_o = 1'b1; + if (otp_rvalid_i) begin + cnt_en = 1'b1; + // Check OTP return code. + if ((!(otp_err inside {NoError, MacroEccCorrError}))) begin + state_d = ErrorSt; + error_d = otp_err; + end else begin + data_en = 1'b1; + state_d = DigSt; + // Signal soft ECC errors, but do not go into terminal error state. + if (otp_err == MacroEccCorrError) begin + error_d = otp_err; + end + end + end + end + /////////////////////////////////////////////////////////////////// + // Push the word read into the scrambling datapath. The last + // block is repeated in case the number blocks in this partition + // is odd. + // SEC_CM: PART.MEM.DIGEST + DigSt: begin + scrmbl_mtx_req_o = 1'b1; + scrmbl_valid_o = 1'b1; + // No need to digest the digest value itself + if (otp_addr_o == digest_addr_lut[part_idx]) begin + // Trigger digest round in case this is the second block in a row. + if (!cnt[0]) begin + scrmbl_cmd_o = Digest; + if (scrmbl_ready_i) begin + state_d = DigFinSt; + end + // Otherwise, just load low word and go to padding state. + end else if (scrmbl_ready_i) begin + state_d = DigPadSt; + end + end else begin + // Trigger digest round in case this is the second block in a row. + if (!cnt[0]) begin + scrmbl_cmd_o = Digest; + end + // Go back and fetch more data blocks. + if (scrmbl_ready_i) begin + state_d = DigReadSt; + end + end + end + /////////////////////////////////////////////////////////////////// + // Padding state, just repeat the last block and go to digest + // finalization. + // SEC_CM: PART.MEM.DIGEST + DigPadSt: begin + scrmbl_mtx_req_o = 1'b1; + scrmbl_valid_o = 1'b1; + scrmbl_cmd_o = Digest; + if (scrmbl_ready_i) begin + state_d = DigFinSt; + end + end + /////////////////////////////////////////////////////////////////// + // Trigger digest finalization and go wait for the result. + // SEC_CM: PART.MEM.DIGEST + DigFinSt: begin + scrmbl_mtx_req_o = 1'b1; + scrmbl_valid_o = 1'b1; + scrmbl_cmd_o = DigestFinalize; + if (scrmbl_ready_i) begin + state_d = DigWaitSt; + end + end + /////////////////////////////////////////////////////////////////// + // Wait for the digest to return, and write the result to OTP. + // Note that the write address will be correct in this state, + // since the counter has been stepped to the correct address as + // part of the readout sequence, and the correct size for this + // access has been loaded before. + // SEC_CM: PART.MEM.DIGEST + DigWaitSt: begin + scrmbl_mtx_req_o = 1'b1; + data_sel = ScrmblData; + if (scrmbl_valid_i) begin + state_d = WriteSt; + data_en = 1'b1; + end + end + /////////////////////////////////////////////////////////////////// + // Terminal Error State. This locks access to the DAI. Make sure + // an FsmStateError error code is assigned here, in case no error code has + // been assigned yet. + ErrorSt: begin + if (error_q == NoError) begin + error_d = FsmStateError; + end + end + /////////////////////////////////////////////////////////////////// + // We should never get here. If we do (e.g. via a malicious + // glitch), error out immediately. + default: begin + state_d = ErrorSt; + fsm_err_o = 1'b1; + end + /////////////////////////////////////////////////////////////////// + endcase // state_q + + // Unconditionally jump into the terminal error state in case of escalation. + // SEC_CM: DAI.FSM.LOCAL_ESC, DAI.FSM.GLOBAL_ESC + if (caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_test_true_loose(escalate_en_i) || cnt_err) begin + state_d = ErrorSt; + fsm_err_o = 1'b1; + if (state_q != ErrorSt) begin + error_d = FsmStateError; + end + end + end + + //////////////////////////// + // Partition Select Logic // + //////////////////////////// + + // This checks which partition the address belongs to by comparing + // the incoming address to the partition address ranges. The onehot + // bitvector generated by the parallel comparisons is fed into a + // binary tree that determines the partition index with O(log(N)) delay. + + logic [NumPart-1:0] part_sel_oh; + for (genvar k = 0; k < NumPart; k++) begin : gen_part_sel + localparam int unsigned PartEndInt = 32'(PartInfo[k].offset) + 32'(PartInfo[k].size); + localparam int unsigned DigestOffsetInt = PartEndInt - ScrmblBlockWidth / 8; + localparam int unsigned DigestAddrLutInt = DigestOffsetInt >> OtpAddrShift; + + // PartEnd has an extra bit to cope with the case where offset + size overflows. However, we + // arrange the address map to make sure that PartEndInt is at most 1 << OtpByteAddrWidth. Check + // that here. + `CALIPTRA_ASSERT_INIT(PartEndMax_A, PartEndInt <= (1 << OtpByteAddrWidth)) + + // The shift right by OtpAddrShift drops exactly the bottom bits that are needed to convert + // between OtpAddrWidth and OtpByteAddrWidth, so we know that we can slice safely here. + localparam bit [OtpAddrWidth-1:0] DigestAddrLut = DigestAddrLutInt[OtpAddrWidth-1:0]; + + if (PartInfo[k].offset == 0) begin : gen_zero_offset + assign part_sel_oh[k] = ({1'b0, dai_addr_i} < PartEndInt[OtpByteAddrWidth:0]); + + end else begin : gen_nonzero_offset + assign part_sel_oh[k] = (dai_addr_i >= PartInfo[k].offset) & + ({1'b0, dai_addr_i} < PartEndInt[OtpByteAddrWidth:0]); + end + assign digest_addr_lut[k] = DigestAddrLut; + end + + `CALIPTRA_ASSERT(ScrmblBlockWidthGe8_A, ScrmblBlockWidth >= 8) + `CALIPTRA_ASSERT(PartSelMustBeOnehot_A, $onehot0(part_sel_oh)) + + caliptra_prim_arbiter_fixed #( + .N(NumPart), + .EnDataPort(0) + ) u_part_sel_idx ( + .clk_i, + .rst_ni, + .req_i ( part_sel_oh ), + .data_i ( '{default: '0} ), + .gnt_o ( ), // unused + .idx_o ( part_idx ), + .valid_o ( part_sel_valid ), // used for detecting OOB addresses + .data_o ( ), // unused + .ready_i ( 1'b0 ) + ); + + ///////////////////////////////////// + // Address Calculations for Digest // + ///////////////////////////////////// + + // Depending on whether this is a 32bit or 64bit partition, we cut off the lower address bits. + // Access sizes are either 64bit or 32bit, depending on what region the access goes to. + logic [OtpByteAddrWidth-1:0] addr_base; + always_comb begin : p_size_sel + otp_size_o = OtpSizeWidth'(unsigned'(32 / OtpWidth - 1)); + addr_base = {dai_addr_i[OtpByteAddrWidth-1:2], 2'h0}; + + // 64bit transaction for scrambled partitions. + if (PartInfo[part_idx].secret) begin + otp_size_o = OtpSizeWidth'(unsigned'(ScrmblBlockWidth / OtpWidth - 1)); + addr_base = {dai_addr_i[OtpByteAddrWidth-1:3], 3'h0}; + // 64bit transaction if computing a digest. + end else if (PartInfo[part_idx].hw_digest && (base_sel_q == PartOffset)) begin + otp_size_o = OtpSizeWidth'(unsigned'(ScrmblBlockWidth / OtpWidth - 1)); + addr_base = PartInfo[part_idx].offset; + // 64bit transaction if the DAI address points to the partition's digest offset. + end else if ((PartInfo[part_idx].hw_digest || PartInfo[part_idx].sw_digest) && + (base_sel_q == DaiOffset) && + ({dai_addr_i[OtpByteAddrWidth-1:3], 2'b0} == digest_addr_lut[part_idx])) begin + otp_size_o = OtpSizeWidth'(unsigned'(ScrmblBlockWidth / OtpWidth - 1)); + addr_base = {dai_addr_i[OtpByteAddrWidth-1:3], 3'h0}; + end + end + + // Address counter - this is only used for computing a digest, hence the increment is + // fixed to 8 byte. + // SEC_CM: DAI.CTR.REDUN + caliptra_prim_count #( + .Width(CntWidth) + ) u_prim_count ( + .clk_i, + .rst_ni, + .clr_i(cnt_clr), + .set_i(1'b0), + .set_cnt_i('0), + .incr_en_i(cnt_en), + .decr_en_i(1'b0), + .step_i(CntWidth'(1)), + .commit_i(1'b1), + .cnt_o(cnt), + .cnt_after_commit_o(), + .err_o(cnt_err) + ); + + // Note that OTP works on halfword (16bit) addresses, hence need to + // shift the addresses appropriately. + logic [OtpByteAddrWidth-1:0] addr_calc; + assign addr_calc = {cnt, {$clog2(ScrmblBlockWidth/8){1'b0}}} + addr_base; + assign otp_addr_o = OtpAddrWidth'(addr_calc >> OtpAddrShift); + + /////////////// + // Registers // + /////////////// + + `CALIPTRA_PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt) + + always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs + if (!rst_ni) begin + error_q <= NoError; + data_q <= '0; + base_sel_q <= DaiOffset; + end else begin + error_q <= error_d; + base_sel_q <= base_sel_d; + + // Working register + if (data_clr) begin + data_q <= '0; + end else if (data_en) begin + if (data_sel == ScrmblData) begin + data_q <= scrmbl_data_i; + end else if (data_sel == DaiData) begin + data_q <= dai_wdata_i; + end else begin + data_q <= otp_rdata_i; + end + end + end + end + + //////////////// + // Assertions // + //////////////// + + // Known assertions + `CALIPTRA_ASSERT_KNOWN(InitDoneKnown_A, init_done_o) + `CALIPTRA_ASSERT_KNOWN(PartInitReqKnown_A, part_init_req_o) + `CALIPTRA_ASSERT_KNOWN(ErrorKnown_A, error_o) + `CALIPTRA_ASSERT_KNOWN(DaiIdleKnown_A, dai_idle_o) + `CALIPTRA_ASSERT_KNOWN(DaiRdataKnown_A, dai_rdata_o) + `CALIPTRA_ASSERT_KNOWN(OtpReqKnown_A, otp_req_o) + `CALIPTRA_ASSERT_KNOWN(OtpCmdKnown_A, otp_cmd_o) + `CALIPTRA_ASSERT_KNOWN(OtpSizeKnown_A, otp_size_o) + `CALIPTRA_ASSERT_KNOWN(OtpWdataKnown_A, otp_wdata_o) + `CALIPTRA_ASSERT_KNOWN(OtpAddrKnown_A, otp_addr_o) + `CALIPTRA_ASSERT_KNOWN(ScrmblMtxReqKnown_A, scrmbl_mtx_req_o) + `CALIPTRA_ASSERT_KNOWN(ScrmblCmdKnown_A, scrmbl_cmd_o) + `CALIPTRA_ASSERT_KNOWN(ScrmblModeKnown_A, scrmbl_mode_o) + `CALIPTRA_ASSERT_KNOWN(ScrmblSelKnown_A, scrmbl_sel_o) + `CALIPTRA_ASSERT_KNOWN(ScrmblDataKnown_A, scrmbl_data_o) + `CALIPTRA_ASSERT_KNOWN(ScrmblValidKnown_A, scrmbl_valid_o) + + // OTP error response + `CALIPTRA_ASSERT(OtpErrorState_A, + state_q inside {InitOtpSt, ReadWaitSt, WriteWaitSt, DigReadWaitSt} && otp_rvalid_i && + !(otp_err inside {NoError, MacroEccCorrError, MacroWriteBlankError}) + |=> + state_q == ErrorSt && error_o == $past(otp_err)) + +endmodule : otp_ctrl_dai diff --git a/src/fuse_ctrl/rtl/otp_ctrl_ecc_reg.sv b/src/fuse_ctrl/rtl/otp_ctrl_ecc_reg.sv new file mode 100644 index 0000000..7514aea --- /dev/null +++ b/src/fuse_ctrl/rtl/otp_ctrl_ecc_reg.sv @@ -0,0 +1,105 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register file for buffered OTP partitions. ECC is used to detect up +// to two simultaneous errors within each 64bit word. + +`include "caliptra_prim_assert.sv" + +module otp_ctrl_ecc_reg #( + parameter int Width = 64, // bit + parameter int Depth = 128, + localparam int Aw = caliptra_prim_util_pkg::vbits(Depth) // derived parameter +) ( + input logic clk_i, + input logic rst_ni, + + input logic wren_i, + input logic [Aw-1:0] addr_i, + input logic [Width-1:0] wdata_i, + output logic [Width-1:0] rdata_o, + + // Concurrent output of the register state. + output logic [Depth-1:0][Width-1:0] data_o, + // Concurrent ECC check error is flagged via this signal. + output logic ecc_err_o +); + + // Integration checks for parameters. + `CALIPTRA_ASSERT_INIT(WidthMustBe64bit_A, Width == 64) + + localparam int EccWidth = 8; + + logic [Depth-1:0][Width-1:0] data_d, data_q; + logic [Depth-1:0][EccWidth-1:0] ecc_d, ecc_q; + logic [Width+EccWidth-1:0] ecc_enc; + + // Only one encoder is needed. + caliptra_prim_secded_inv_72_64_enc u_prim_secded_inv_72_64_enc ( + .data_i(wdata_i), + .data_o(ecc_enc) + ); + + if (Depth == 1) begin : gen_one_word_only + always_comb begin : p_write + data_o = data_q; + data_d = data_q; + ecc_d = ecc_q; + + rdata_o = '0; + if (32'(addr_i) < Depth) begin + rdata_o = data_q[0]; + if (wren_i) begin + {ecc_d[0], data_d[0]} = ecc_enc; + end + end + end + end else begin : gen_multiple_words + always_comb begin : p_write + data_o = data_q; + data_d = data_q; + ecc_d = ecc_q; + + rdata_o = '0; + if (32'(addr_i) < Depth) begin + rdata_o = data_q[addr_i]; + if (wren_i) begin + {ecc_d[addr_i], data_d[addr_i]} = ecc_enc; + end + end + end + end + + // Concurrent ECC checks. + logic [Depth-1:0][1:0] err; + for (genvar k = 0; k < Depth; k++) begin : gen_ecc_dec + caliptra_prim_secded_inv_72_64_dec u_prim_secded_inv_72_64_dec ( + .data_i({ecc_q[k], data_q[k]}), + // We only rely on the error detection mechanism, + // and not on error correction. + .data_o(), + .syndrome_o(), + .err_o(err[k]) + ); + end + + assign ecc_err_o = |err; + + always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs + if (!rst_ni) begin + ecc_q <= {Depth{caliptra_prim_secded_pkg::SecdedInv7264ZeroEcc}}; + data_q <= '0; + end else begin + ecc_q <= ecc_d; + data_q <= data_d; + end + end + + `CALIPTRA_ASSERT_KNOWN(EccKnown_A, ecc_q) + `CALIPTRA_ASSERT_KNOWN(DataKnown_A, data_q) + `CALIPTRA_ASSERT_KNOWN(RDataOutKnown_A, rdata_o) + `CALIPTRA_ASSERT_KNOWN(DataOutKnown_A, data_o) + `CALIPTRA_ASSERT_KNOWN(EccErrKnown_A, ecc_err_o) + +endmodule : otp_ctrl_ecc_reg diff --git a/src/fuse_ctrl/rtl/otp_ctrl_kdi.sv b/src/fuse_ctrl/rtl/otp_ctrl_kdi.sv new file mode 100644 index 0000000..3a22511 --- /dev/null +++ b/src/fuse_ctrl/rtl/otp_ctrl_kdi.sv @@ -0,0 +1,603 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Scrambling key derivation module for OTP. +// + +`include "caliptra_prim_flop_macros.sv" + +module otp_ctrl_kdi + import otp_ctrl_pkg::*; + import otp_ctrl_reg_pkg::*; + import otp_ctrl_part_pkg::*; +#( + parameter scrmbl_key_init_t RndCnstScrmblKeyInit = RndCnstScrmblKeyInitDefault +) ( + input clk_i, + input rst_ni, + // Pulse to enable this module after OTP partitions have + // been initialized. + input kdi_en_i, + // Escalation input. This moves the FSM into a terminal state. + input caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_t escalate_en_i, + // FSM is in error state + output logic fsm_err_o, + // Key seed inputs from OTP + input logic scrmbl_key_seed_valid_i, + input logic [FlashKeySeedWidth-1:0] flash_data_key_seed_i, + input logic [FlashKeySeedWidth-1:0] flash_addr_key_seed_i, + input logic [SramKeySeedWidth-1:0] sram_data_key_seed_i, + // EDN interface for requesting entropy + output logic edn_req_o, + input edn_ack_i, + input [EdnDataWidth-1:0] edn_data_i, + // Scrambling key requests + input flash_otp_key_req_t flash_otp_key_i, + output flash_otp_key_rsp_t flash_otp_key_o, + input sram_otp_key_req_t [NumSramKeyReqSlots-1:0] sram_otp_key_i, + output sram_otp_key_rsp_t [NumSramKeyReqSlots-1:0] sram_otp_key_o, + input otbn_otp_key_req_t otbn_otp_key_i, + output otbn_otp_key_rsp_t otbn_otp_key_o, + // Scrambling mutex request + output logic scrmbl_mtx_req_o, + input scrmbl_mtx_gnt_i, + // Scrambling datapath interface + output otp_scrmbl_cmd_e scrmbl_cmd_o, + output digest_mode_e scrmbl_mode_o, + output logic [ConstSelWidth-1:0] scrmbl_sel_o, + output logic [ScrmblBlockWidth-1:0] scrmbl_data_o, + output logic scrmbl_valid_o, + input logic scrmbl_ready_i, + input logic scrmbl_valid_i, + input logic [ScrmblBlockWidth-1:0] scrmbl_data_i +); + + import caliptra_prim_util_pkg::vbits; + + //////////////////////// + // Integration Checks // + //////////////////////// + + // 2xFlash, OTBN + SRAM slots + localparam int NumReq = 3 + NumSramKeyReqSlots; + // Make sure key sizes in the system are multiples of 64bit and not larger than 256bit. + `CALIPTRA_ASSERT_INIT(KeyNonceSize0_A, (FlashKeySeedWidth <= 256) && ((FlashKeySeedWidth % 64) == 0)) + `CALIPTRA_ASSERT_INIT(KeyNonceSize1_A, (SramKeySeedWidth <= 256) && ((SramKeySeedWidth % 64) == 0)) + `CALIPTRA_ASSERT_INIT(KeyNonceSize2_A, (FlashKeyWidth <= 256) && ((FlashKeyWidth % 64) == 0)) + `CALIPTRA_ASSERT_INIT(KeyNonceSize3_A, (SramKeyWidth <= 256) && ((SramKeyWidth % 64) == 0)) + `CALIPTRA_ASSERT_INIT(KeyNonceSize4_A, (SramNonceWidth <= 256) && ((SramNonceWidth % 64) == 0)) + `CALIPTRA_ASSERT_INIT(KeyNonceSize5_A, (OtbnKeyWidth <= 256) && ((OtbnKeyWidth % 64) == 0)) + `CALIPTRA_ASSERT_INIT(KeyNonceSize6_A, (OtbnNonceWidth <= 256) && ((OtbnNonceWidth % 64) == 0)) + + // Make sure EDN interface has compatible width. + `CALIPTRA_ASSERT_INIT(EntropyWidthDividesDigestBlockWidth_A, (ScrmblKeyWidth % EdnDataWidth) == 0) + + // Currently the assumption is that the SRAM nonce is the widest. + `CALIPTRA_ASSERT_INIT(NonceWidth_A, NumNonceChunks * ScrmblBlockWidth == SramNonceWidth) + + /////////////////////////////////// + // Input Mapping and Arbitration // + /////////////////////////////////// + + // The key derivation and token hashing functions are aligned such that 2 x 128bit key + // seeds / token blocks are processed in two subsequent steps using the digest primitive. + // This effectively compresses these blocks down into 2 x 64bit blocks, thereby creating + // one 128bit key or token output. + // + // The same FSM is shared among the different flavors of key derivation and token + // hashing functions, and the following configuration options are available: + // + // 1) ingest an additional 128bit entropy block after ingesting a 128bit key seed. + // 2) keep digest state after producing the first 64bit block instead of reverting to the IV. + // 3) netlist constant index. + // 4) fetch additional entropy for the nonce output. + // 5) whether or not the key seed is valid. if not, it will be defaulted to '0. + // 6) 256bit key seed / token input. + // + // The configuration options are set further below, depending on the request type. + + typedef struct packed { + logic ingest_entropy; // 1) + logic chained_digest; // 2) + digest_sel_e digest_sel; // 3) + logic fetch_nonce; // 4) + logic [1:0] nonce_size; // 4) + logic seed_valid; // 5) + logic [3:0][ScrmblBlockWidth-1:0] seed; // 6) + } req_bundle_t; + + logic [NumReq-1:0] req, gnt; + req_bundle_t req_bundles [NumReq]; + + assign req[0] = flash_otp_key_i.data_req; + assign req[1] = flash_otp_key_i.addr_req; + assign req[2] = otbn_otp_key_i.req; + + assign flash_otp_key_o.data_ack = gnt[0]; + assign flash_otp_key_o.addr_ack = gnt[1]; + assign otbn_otp_key_o.ack = gnt[2]; + + // anchored seeds + logic [FlashKeySeedWidth-1:0] flash_data_key_seed; + logic [FlashKeySeedWidth-1:0] flash_addr_key_seed; + logic [SramKeySeedWidth-1:0] sram_data_key_seed; + + caliptra_prim_sec_anchor_buf #( + .Width(FlashKeySeedWidth) + ) u_flash_data_key_anchor ( + .in_i(flash_data_key_seed_i), + .out_o(flash_data_key_seed) + ); + + caliptra_prim_sec_anchor_buf #( + .Width(FlashKeySeedWidth) + ) u_flash_addr_key_anchor ( + .in_i(flash_addr_key_seed_i), + .out_o(flash_addr_key_seed) + ); + + caliptra_prim_sec_anchor_buf #( + .Width(SramKeySeedWidth) + ) u_sram_data_key_anchor ( + .in_i(sram_data_key_seed_i), + .out_o(sram_data_key_seed) + ); + + // Flash data key + assign req_bundles[0] = '{ingest_entropy: 1'b0, // no random entropy added + chained_digest: 1'b0, // revert to netlist IV between blocks + digest_sel: FlashDataKey, + fetch_nonce: 1'b1, + nonce_size: 2'(FlashKeyWidth/EdnDataWidth-1), + seed_valid: scrmbl_key_seed_valid_i, + seed: flash_data_key_seed}; // 2x128bit + // Flash addr key + assign req_bundles[1] = '{ingest_entropy: 1'b0, // no random entropy added + chained_digest: 1'b0, // revert to netlist IV between blocks + digest_sel: FlashAddrKey, + fetch_nonce: 1'b1, + nonce_size: '0, + seed_valid: scrmbl_key_seed_valid_i, + seed: flash_addr_key_seed}; // 2x128bit + // OTBN key + assign req_bundles[2] = '{ingest_entropy: 1'b1, // ingest random data + chained_digest: 1'b0, // revert to netlist IV between blocks + digest_sel: SramDataKey, + fetch_nonce: 1'b1, // fetch nonce + nonce_size: 2'(OtbnNonceWidth/EdnDataWidth-1), + seed_valid: scrmbl_key_seed_valid_i, + seed: {sram_data_key_seed, // reuse same seed + sram_data_key_seed}}; + + // SRAM keys + for (genvar k = 3; k < NumReq; k++) begin : gen_req_assign + assign req[k] = sram_otp_key_i[k-3].req; + assign sram_otp_key_o[k-3].ack = gnt[k]; + assign req_bundles[k] = '{ingest_entropy: 1'b1, // ingest random data + chained_digest: 1'b0, // revert to netlist IV between blocks + digest_sel: SramDataKey, + fetch_nonce: 1'b1, // fetch nonce + nonce_size: 2'(SramNonceWidth/EdnDataWidth-1), + seed_valid: scrmbl_key_seed_valid_i, + seed: {sram_data_key_seed, // reuse same seed + sram_data_key_seed}}; + end + + // This arbitrates among incoming key derivation requests on a + // round robin basis to prevent deadlock. + logic req_valid, req_ready; + req_bundle_t req_bundle; + + caliptra_prim_arbiter_tree #( + .N(NumReq), + .DW($bits(req_bundle_t))) + u_req_arb ( + .clk_i, + .rst_ni, + .req_chk_i ( 1'b1 ), + .req_i ( req ), + .data_i ( req_bundles ), + .gnt_o ( gnt ), + .idx_o ( ), + .valid_o ( req_valid ), + .data_o ( req_bundle ), + .ready_i ( req_ready ) + ); + + ////////////////////////////// + // Temporary Regs and Muxes // + ////////////////////////////// + + localparam int CntWidth = 2; + logic seed_cnt_clr, seed_cnt_en, entropy_cnt_clr, entropy_cnt_en, seed_cnt_err, entropy_cnt_err; + logic [CntWidth-1:0] seed_cnt, entropy_cnt; + + // SEC_CM: KDI_SEED.CTR.REDUN + caliptra_prim_count #( + .Width(CntWidth) + ) u_prim_count_seed ( + .clk_i, + .rst_ni, + .clr_i(seed_cnt_clr), + .set_i(1'b0), + .set_cnt_i('0), + .incr_en_i(seed_cnt_en), + .decr_en_i(1'b0), + .step_i(CntWidth'(1)), + .commit_i(1'b1), + .cnt_o(seed_cnt), + .cnt_after_commit_o(), + .err_o(seed_cnt_err) + ); + + // SEC_CM: KDI_ENTROPY.CTR.REDUN + caliptra_prim_count #( + .Width(CntWidth) + ) u_prim_count_entropy ( + .clk_i, + .rst_ni, + .clr_i(entropy_cnt_clr), + .set_i(1'b0), + .set_cnt_i('0), + .incr_en_i(entropy_cnt_en), + .decr_en_i(1'b0), + .step_i(CntWidth'(1)), + .commit_i(1'b1), + .cnt_o(entropy_cnt), + .cnt_after_commit_o(), + .err_o(entropy_cnt_err) + ); + + logic seed_valid_reg_en; + logic key_reg_en, nonce_reg_en; + logic seed_valid_d, seed_valid_q; + logic [ScrmblKeyWidth/ScrmblBlockWidth-1:0][ScrmblBlockWidth-1:0] key_out_d, key_out_q; + logic [NumNonceChunks-1:0][ScrmblBlockWidth-1:0] nonce_out_d, nonce_out_q; + + always_comb begin : p_outregs + key_out_d = key_out_q; + nonce_out_d = nonce_out_q; + seed_valid_d = seed_valid_q; + if (key_reg_en) begin + key_out_d[seed_cnt[1]] = scrmbl_data_i; + end + if (nonce_reg_en) begin + nonce_out_d[entropy_cnt[$clog2(NumNonceChunks)-1:0]] = edn_data_i; + end + if (seed_valid_reg_en) begin + seed_valid_d = req_bundle.seed_valid; + end + end + + // Connect keys/nonce outputs to output regs. + caliptra_prim_sec_anchor_flop #( + .Width(ScrmblKeyWidth), + .ResetValue(RndCnstScrmblKeyInit.key) + ) u_key_out_anchor ( + .clk_i, + .rst_ni, + .d_i(key_out_d), + .q_o(key_out_q) + ); + + assign otbn_otp_key_o.key = key_out_q; + assign otbn_otp_key_o.nonce = nonce_out_q[OtbnNonceSel-1:0]; + assign otbn_otp_key_o.seed_valid = seed_valid_q; + + assign flash_otp_key_o.key = key_out_q; + assign flash_otp_key_o.rand_key = nonce_out_q[FlashNonceSel-1:0]; + assign flash_otp_key_o.seed_valid = seed_valid_q; + + for (genvar k = 0; k < NumSramKeyReqSlots; k++) begin : gen_out_assign + assign sram_otp_key_o[k].key = key_out_q; + assign sram_otp_key_o[k].nonce = nonce_out_q[SramNonceSel-1:0]; + assign sram_otp_key_o[k].seed_valid = seed_valid_q; + end + + typedef enum logic { + SeedData, + EntropyData + } data_sel_e; + + // Select correct 64bit block. + data_sel_e data_sel; + assign scrmbl_data_o = (data_sel == EntropyData) ? nonce_out_q[entropy_cnt[0]] : + // Gate seed value to '0 if invalid. + (req_bundle.seed_valid) ? req_bundle.seed[seed_cnt] : '0; + + ///////////////// + // Control FSM // + ///////////////// + + // SEC_CM: KDI.FSM.SPARSE + // Encoding generated with: + // $ ./util/design/sparse-fsm-encode.py -d 5 -m 11 -n 10 \ + // -s 2544133835 --language=sv + // + // Hamming distance histogram: + // + // 0: -- + // 1: -- + // 2: -- + // 3: -- + // 4: -- + // 5: |||||||||||||||||||| (54.55%) + // 6: |||||||||||||||| (45.45%) + // 7: -- + // 8: -- + // 9: -- + // 10: -- + // + // Minimum Hamming distance: 5 + // Maximum Hamming distance: 6 + // Minimum Hamming weight: 3 + // Maximum Hamming weight: 9 + // + localparam int StateWidth = 10; + typedef enum logic [StateWidth-1:0] { + ResetSt = 10'b0101100001, + IdleSt = 10'b0001011011, + DigClrSt = 10'b1101010110, + DigLoadSt = 10'b0010110111, + FetchEntropySt = 10'b1000001101, + DigEntropySt = 10'b0100111100, + DigFinSt = 10'b1000100010, + DigWaitSt = 10'b1110010001, + FetchNonceSt = 10'b0011000100, + FinishSt = 10'b1011111000, + ErrorSt = 10'b1111101111 + } state_e; + + state_e state_d, state_q; + logic edn_req_d, edn_req_q; + assign edn_req_o = edn_req_q; + + always_comb begin : p_fsm + state_d = state_q; + + // FSM Error output + fsm_err_o = 1'b0; + + // Counters + seed_cnt_en = 1'b0; + seed_cnt_clr = 1'b0; + entropy_cnt_en = 1'b0; + entropy_cnt_clr = 1'b0; + + // EDN 128bit block fetch request. + // This keeps the request alive until it has + // been acked to adhere to the req/ack protocol + // even in cases where the FSM jumps into + // an error state while waiting for a request. + edn_req_d = edn_req_q & ~edn_ack_i; + + // Data selection and temp registers + data_sel = SeedData; + key_reg_en = 1'b0; + nonce_reg_en = 1'b0; + seed_valid_reg_en = 1'b0; + + // Scrambling datapath + scrmbl_mtx_req_o = 1'b0; + scrmbl_sel_o = req_bundle.digest_sel; + scrmbl_cmd_o = LoadShadow; + scrmbl_mode_o = StandardMode; + + scrmbl_valid_o = 1'b0; + + // Request acknowledgement + req_ready = 1'b0; + + unique case (state_q) + /////////////////////////////////////////////////////////////////// + // State right after reset. Wait here until KDI gets enabled. + ResetSt: begin + if (kdi_en_i) begin + state_d = IdleSt; + end + end + /////////////////////////////////////////////////////////////////// + // Wait for a request, then go and acquire the mutex. + IdleSt: begin + if (req_valid) begin + state_d = DigClrSt; + seed_cnt_clr = 1'b1; + entropy_cnt_clr = 1'b1; + end + end + /////////////////////////////////////////////////////////////////// + // First, acquire the mutex for the digest and clear the digest state. + DigClrSt: begin + scrmbl_mtx_req_o = 1'b1; + scrmbl_valid_o = 1'b1; + // Need to reset the digest state and set digest mode to "standard". + scrmbl_cmd_o = DigestInit; + if (scrmbl_mtx_gnt_i && scrmbl_ready_i) begin + state_d = DigLoadSt; + end + end + /////////////////////////////////////////////////////////////////// + // Load two 64bit blocks of the seed, and trigger digest calculation. + DigLoadSt: begin + scrmbl_mtx_req_o = 1'b1; + scrmbl_valid_o = 1'b1; + // Trigger digest round in case this is the second block in a row. + if (seed_cnt[0]) begin + scrmbl_cmd_o = Digest; + if (scrmbl_ready_i) begin + // Go and ingest a block of entropy if required. + if (req_bundle.ingest_entropy) begin + state_d = FetchEntropySt; + // Otherwise go to digest finalization state. + end else begin + state_d = DigFinSt; + end + end + // Just load first 64bit block and stay here. + end else if (scrmbl_ready_i) begin + seed_cnt_en = 1'b1; + end + end + /////////////////////////////////////////////////////////////////// + // Fetch random data to ingest for key derivation. + FetchEntropySt: begin + scrmbl_mtx_req_o = 1'b1; + edn_req_d = 1'b1; + if (edn_ack_i) begin + nonce_reg_en = 1'b1; + // Finished, go and acknowledge this request. + if (entropy_cnt == 2'h1) begin + state_d = DigEntropySt; + entropy_cnt_clr = 1'b1; + // Keep on requesting entropy. + end else begin + entropy_cnt_en = 1'b1; + end + end + end + /////////////////////////////////////////////////////////////////// + // Load two 64bit blocks of entropy data. + DigEntropySt: begin + scrmbl_mtx_req_o = 1'b1; + data_sel = EntropyData; + scrmbl_valid_o = 1'b1; + // Trigger digest round in case this is the second block in a row, + // and go to digest finalization. + if (entropy_cnt[0]) begin + scrmbl_cmd_o = Digest; + if (scrmbl_ready_i) begin + state_d = DigFinSt; + entropy_cnt_clr = 1'b1; + end + // Just load first 64bit block and stay here. + end else if (scrmbl_ready_i) begin + entropy_cnt_en = 1'b1; + end + end + /////////////////////////////////////////////////////////////////// + // Trigger digest finalization and go wait for the result. + DigFinSt: begin + scrmbl_mtx_req_o = 1'b1; + scrmbl_valid_o = 1'b1; + scrmbl_cmd_o = DigestFinalize; + if (scrmbl_ready_i) begin + state_d = DigWaitSt; + end + end + /////////////////////////////////////////////////////////////////// + // Wait for the digest to return, and write the result to the key + // output register. Go back and process the second part of the + // input seed if needed. + DigWaitSt: begin + scrmbl_mtx_req_o = 1'b1; + if (scrmbl_valid_i) begin + key_reg_en = 1'b1; + // Not finished yet, need to go back and produce second 64bit block. + if (seed_cnt == 2'h1) begin + seed_cnt_en = 1'b1; + // In this case the previous digest state is kept, + // which leads to a chained digest. + if (req_bundle.chained_digest) begin + state_d = DigLoadSt; + // In this case we revert the digest state to the netlist IV. + end else begin + state_d = DigClrSt; + end + // This was the second 64bit output block. + end else begin + seed_cnt_clr = 1'b1; + // Make sure we output the status of the key seed in OTP. + seed_valid_reg_en = 1'b1; + // Check whether we need to fetch additional nonce data. + if (req_bundle.fetch_nonce) begin + state_d = FetchNonceSt; + end else begin + // Finished, go and acknowledge this request. + state_d = FinishSt; + end + end + end + end + /////////////////////////////////////////////////////////////////// + // Fetch additional nonce data. Note that the mutex is released in + // this state. + FetchNonceSt: begin + edn_req_d = 1'b1; + if (edn_ack_i) begin + nonce_reg_en = 1'b1; + // Finished, go and acknowledge this request. + if (entropy_cnt == req_bundle.nonce_size) begin + state_d = FinishSt; + entropy_cnt_clr = 1'b1; + // Keep on requesting entropy. + end else begin + entropy_cnt_en = 1'b1; + end + end + end + /////////////////////////////////////////////////////////////////// + // Acknowledge request and go back to IdleSt. + FinishSt: begin + state_d = IdleSt; + req_ready = 1'b1; + end + /////////////////////////////////////////////////////////////////// + // Terminal error state. This raises an alert. + ErrorSt: begin + fsm_err_o = 1'b1; + end + /////////////////////////////////////////////////////////////////// + // This should never happen, hence we directly jump into the + // error state, where an alert will be triggered. + default: begin + state_d = ErrorSt; + fsm_err_o = 1'b1; + end + /////////////////////////////////////////////////////////////////// + endcase // state_q + + // Unconditionally jump into the terminal error state in case of escalation. + // SEC_CM: KDI.FSM.LOCAL_ESC, KDI.FSM.GLOBAL_ESC + if (caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_test_true_loose(escalate_en_i) || + seed_cnt_err || entropy_cnt_err) begin + state_d = ErrorSt; + fsm_err_o = 1'b1; + end + end + + /////////////// + // Registers // + /////////////// + + `CALIPTRA_PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt) + + always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs + if (!rst_ni) begin + nonce_out_q <= RndCnstScrmblKeyInit.nonce; + seed_valid_q <= 1'b0; + edn_req_q <= 1'b0; + end else begin + nonce_out_q <= nonce_out_d; + seed_valid_q <= seed_valid_d; + edn_req_q <= edn_req_d; + end + end + + //////////////// + // Assertions // + //////////////// + + `CALIPTRA_ASSERT_KNOWN(FsmErrKnown_A, fsm_err_o) + `CALIPTRA_ASSERT_KNOWN(EdnReqKnown_A, edn_req_o) + `CALIPTRA_ASSERT_KNOWN(FlashOtpKeyRspKnown_A, flash_otp_key_o) + `CALIPTRA_ASSERT_KNOWN(SramOtpKeyRspKnown_A, sram_otp_key_o) + `CALIPTRA_ASSERT_KNOWN(OtbnOtpKeyRspKnown_A, otbn_otp_key_o) + `CALIPTRA_ASSERT_KNOWN(ScrmblMtxReqKnown_A, scrmbl_mtx_req_o) + `CALIPTRA_ASSERT_KNOWN(ScrmblCmdKnown_A, scrmbl_cmd_o) + `CALIPTRA_ASSERT_KNOWN(ScrmblModeKnown_A, scrmbl_mode_o) + `CALIPTRA_ASSERT_KNOWN(ScrmblSelKnown_A, scrmbl_sel_o) + `CALIPTRA_ASSERT_KNOWN(ScrmblDataKnown_A, scrmbl_data_o) + `CALIPTRA_ASSERT_KNOWN(ScrmblValidKnown_A, scrmbl_valid_o) + +endmodule : otp_ctrl_kdi diff --git a/src/fuse_ctrl/rtl/otp_ctrl_lci.sv b/src/fuse_ctrl/rtl/otp_ctrl_lci.sv new file mode 100644 index 0000000..d9eb445 --- /dev/null +++ b/src/fuse_ctrl/rtl/otp_ctrl_lci.sv @@ -0,0 +1,298 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Life cycle interface for performing life cycle transitions in OTP. +// + +`include "caliptra_prim_flop_macros.sv" + +module otp_ctrl_lci + import otp_ctrl_pkg::*; + import otp_ctrl_reg_pkg::*; + import otp_ctrl_part_pkg::*; +#( + // Lifecycle partition information + parameter part_info_t Info = PartInfoDefault +) ( + input clk_i, + input rst_ni, + input lci_en_i, + // Escalation input. This moves the FSM into a terminal state and locks down + // the partition. + input caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_t escalate_en_i, + // Life cycle transition request. In order to perform a state transition, + // the LC controller signals the new count and state. The OTP wrapper then + // only programs bits that have not been programmed before. + // Note that a transition request will fail if the request attempts to + // clear already programmed bits within OTP. + input caliptra_ss_lc_req_i, + input logic [Info.size*8-1:0] caliptra_ss_lc_data_i, + output logic caliptra_ss_lc_ack_o, + output logic caliptra_ss_lc_err_o, + // Output error state of partition, to be consumed by OTP error/alert logic. + // Note that most errors are not recoverable and move the partition FSM into + // a terminal error state. + output otp_err_e error_o, + // This error signal is pulsed high if the FSM has been glitched into an invalid state. + // Although it is somewhat redundant with the error code in error_o above, it is + // meant to cover cases where we already latched an error code while the FSM is + // glitched into an invalid state (since in that case, the error code will not be + // overridden with the FSM error code so that the original error code is still + // discoverable). + output logic fsm_err_o, + output logic lci_prog_idle_o, + // OTP interface + output logic otp_req_o, + output caliptra_prim_otp_pkg::cmd_e otp_cmd_o, + output logic [OtpSizeWidth-1:0] otp_size_o, + output logic [OtpIfWidth-1:0] otp_wdata_o, + output logic [OtpAddrWidth-1:0] otp_addr_o, + input otp_gnt_i, + input otp_rvalid_i, + input [ScrmblBlockWidth-1:0] otp_rdata_i, + input caliptra_prim_otp_pkg::err_e otp_err_i +); + + //////////////////////// + // Integration Checks // + //////////////////////// + + import caliptra_prim_util_pkg::vbits; + + localparam int NumLcOtpWords = int'(Info.size) >> OtpAddrShift; + localparam int CntWidth = vbits(NumLcOtpWords); + + localparam int unsigned LastLcOtpWordInt = NumLcOtpWords - 1; + localparam bit [CntWidth-1:0] LastLcOtpWord = LastLcOtpWordInt[CntWidth-1:0]; + + // This is required, since each native OTP word can only be programmed once. + `CALIPTRA_ASSERT_INIT(LcValueMustBeWiderThanNativeOtpWidth_A, caliptra_ss_lc_ctrl_state_pkg::LcValueWidth >= OtpWidth) + + //////////////////// + // Controller FSM // + //////////////////// + + // SEC_CM: LCI.FSM.SPARSE + // Encoding generated with: + // $ ./util/design/sparse-fsm-encode.py -d 5 -m 5 -n 9 \ + // -s 558234734 --language=sv + // + // Hamming distance histogram: + // + // 0: -- + // 1: -- + // 2: -- + // 3: -- + // 4: -- + // 5: |||||||||||||||||||| (60.00%) + // 6: ||||||||||||| (40.00%) + // 7: -- + // 8: -- + // 9: -- + // + // Minimum Hamming distance: 5 + // Maximum Hamming distance: 6 + // Minimum Hamming weight: 1 + // Maximum Hamming weight: 7 + // + localparam int StateWidth = 9; + typedef enum logic [StateWidth-1:0] { + ResetSt = 9'b000101011, + IdleSt = 9'b110011110, + WriteSt = 9'b101010001, + WriteWaitSt = 9'b010000000, + ErrorSt = 9'b011111101 + } state_e; + + state_e state_d, state_q; + logic cnt_clr, cnt_en, cnt_err; + logic [CntWidth-1:0] cnt; + otp_err_e error_d, error_q; + + // Output LCI errors + assign error_o = error_q; + + always_comb begin : p_fsm + state_d = state_q; + + // Counter + cnt_en = 1'b0; + cnt_clr = 1'b0; + + // Idle status + lci_prog_idle_o = 1'b1; + + // OTP signals + otp_req_o = 1'b0; + otp_cmd_o = caliptra_prim_otp_pkg::Read; + + // Response to LC controller + caliptra_ss_lc_err_o = 1'b0; + caliptra_ss_lc_ack_o = 1'b0; + + // Error Register + error_d = error_q; + fsm_err_o = 1'b0; + + unique case (state_q) + /////////////////////////////////////////////////////////////////// + // State right after reset. Wait here until LCI gets enabled. + ResetSt: begin + lci_prog_idle_o = 1'b0; + if (lci_en_i) begin + state_d = IdleSt; + end + end + /////////////////////////////////////////////////////////////////// + // Wait for a request from the life cycle controller + IdleSt: begin + if (caliptra_ss_lc_req_i) begin + state_d = WriteSt; + cnt_clr = 1'b1; + end + end + /////////////////////////////////////////////////////////////////// + // Loop through the lifecycle sate and burn in all words. + // If the write data contains a 0 bit in a position where a bit has already been + // programmed to 1 before, the OTP errors out. + WriteSt: begin + otp_req_o = 1'b1; + otp_cmd_o = caliptra_prim_otp_pkg::Write; + lci_prog_idle_o = 1'b0; + if (otp_gnt_i) begin + state_d = WriteWaitSt; + end + end + /////////////////////////////////////////////////////////////////// + // Wait for OTP response, and check whether there are more words to burn in. + // In case an OTP transaction fails, latch the OTP error code, and jump to + // terminal error state. + WriteWaitSt: begin + lci_prog_idle_o = 1'b0; + if (otp_rvalid_i) begin + // Check OTP return code. + // Note that if errors occur, we aggregate the error code + // but still attempt to program all remaining words. + // This is done to ensure that a life cycle state with + // ECC correctable errors in some words can still be scrapped. + if (otp_err_e'(otp_err_i) != NoError) begin + error_d = otp_err_e'(otp_err_i); + end + + // Check whether we programmed all OTP words. + // If yes, we are done and can go back to idle. + if (cnt == LastLcOtpWord) begin + state_d = IdleSt; + caliptra_ss_lc_ack_o = 1'b1; + // If in any of the words a programming error has occurred, + // we signal that accordingly and go to the error state. + if (error_d != NoError) begin + caliptra_ss_lc_err_o = 1'b1; + state_d = ErrorSt; + end + // Otherwise we increase the OTP word counter. + end else begin + state_d = WriteSt; + cnt_en = 1'b1; + end + end + end + /////////////////////////////////////////////////////////////////// + // Terminal Error State. This locks access to the partition. + // Make sure the partition signals an error state if no error + // code has been latched so far, and lock the buffer regs down. + ErrorSt: begin + if (error_q == NoError) begin + error_d = FsmStateError; + end + end + /////////////////////////////////////////////////////////////////// + // We should never get here. If we do (e.g. via a malicious + // glitch), error out immediately. + default: begin + state_d = ErrorSt; + fsm_err_o = 1'b1; + end + /////////////////////////////////////////////////////////////////// + endcase // state_q + + // Unconditionally jump into the terminal error state in case of escalation. + // SEC_CM: LCI.FSM.LOCAL_ESC, LCI.FSM.GLOBAL_ESC + if (caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_test_true_loose(escalate_en_i) || cnt_err) begin + state_d = ErrorSt; + fsm_err_o = 1'b1; + if (error_q == NoError) begin + error_d = FsmStateError; + end + end + + end + + ////////////////////////////// + // Counter and address calc // + ////////////////////////////// + + // Native OTP word counter + // SEC_CM: LCI.CTR.REDUN + caliptra_prim_count #( + .Width(CntWidth) + ) u_prim_count ( + .clk_i, + .rst_ni, + .clr_i(cnt_clr), + .set_i(1'b0), + .set_cnt_i('0), + .incr_en_i(cnt_en), + .decr_en_i(1'b0), + .step_i(CntWidth'(1)), + .commit_i(1'b1), + .cnt_o(cnt), + .cnt_after_commit_o(), + .err_o(cnt_err) + ); + + // The output address is "offset + count", but we have to convert Info.offset from a byte address + // to a halfword (16-bit) address by discarding the bottom OtpAddrShift bits. We also make the + // zero-extension of cnt explicit (to avoid width mismatch warnings). + assign otp_addr_o = Info.offset[OtpByteAddrWidth-1:OtpAddrShift] + OtpAddrWidth'(cnt); + + // Always transfer 16bit blocks. + assign otp_size_o = '0; + + logic [NumLcOtpWords-1:0][OtpWidth-1:0] data; + assign data = caliptra_ss_lc_data_i; + assign otp_wdata_o = (otp_req_o) ? OtpIfWidth'(data[cnt]) : '0; + + logic unused_rdata; + assign unused_rdata = ^otp_rdata_i; + + /////////////// + // Registers // + /////////////// + + `CALIPTRA_PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt) + + always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs + if (!rst_ni) begin + error_q <= NoError; + end else begin + error_q <= error_d; + end + end + + //////////////// + // Assertions // + //////////////// + + `CALIPTRA_ASSERT_KNOWN(LcAckKnown_A, caliptra_ss_lc_ack_o) + `CALIPTRA_ASSERT_KNOWN(LcErrKnown_A, caliptra_ss_lc_err_o) + `CALIPTRA_ASSERT_KNOWN(ErrorKnown_A, error_o) + `CALIPTRA_ASSERT_KNOWN(LciIdleKnown_A, lci_prog_idle_o) + `CALIPTRA_ASSERT_KNOWN(OtpReqKnown_A, otp_req_o) + `CALIPTRA_ASSERT_KNOWN(OtpCmdKnown_A, otp_cmd_o) + `CALIPTRA_ASSERT_KNOWN(OtpSizeKnown_A, otp_size_o) + `CALIPTRA_ASSERT_KNOWN(OtpWdataKnown_A, otp_wdata_o) + `CALIPTRA_ASSERT_KNOWN(OtpAddrKnown_A, otp_addr_o) + +endmodule : otp_ctrl_lci diff --git a/src/fuse_ctrl/rtl/otp_ctrl_lfsr_timer.sv b/src/fuse_ctrl/rtl/otp_ctrl_lfsr_timer.sv new file mode 100644 index 0000000..6f7c04e --- /dev/null +++ b/src/fuse_ctrl/rtl/otp_ctrl_lfsr_timer.sv @@ -0,0 +1,397 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// This module implements the LFSR timer for triggering periodic consistency and integrity checks in +// OTP. In particular, this module contains two 40bit counters (one for the consistency and one +// for the integrity checks) and a 40bit LFSR to draw pseudo random wait counts. +// +// The integ_period_msk_i and cnsty_period_msk_i mask signals are used to mask off the LFSR outputs +// and hence determine the maximum wait count that can be drawn. If these values are set to +// zero, the corresponding timer is disabled. +// +// Once a particular check timer has expired, the module will send out a check request to all +// partitions and wait for an acknowledgment. If a particular partition encounters an integrity or +// consistency mismatch, this will be directly reported via the error and alert logic. +// +// In order to guard against wedged partition controllers or arbitration lock ups due to tampering +// attempts, this check timer module also supports a 32bit timeout that can optionally be +// programmed. If a particular check times out, chk_timeout_o will be asserted, which will raise +// an alert via the error logic. +// +// The EntropyWidth LSBs of the LFSR are reseeded with fresh entropy from EDN once +// LfsrUsageThreshold values have been drawn from the LFSR. +// +// It is also possible to trigger one-off checks via integ_chk_trig_i and cnsty_chk_trig_i. +// This can be useful if SW chooses to leave the periodic checks disabled. +// + +`include "caliptra_prim_flop_macros.sv" + +module otp_ctrl_lfsr_timer + import otp_ctrl_pkg::*; + import otp_ctrl_reg_pkg::*; +#( + // Compile time random constants, to be overriden by topgen. + parameter lfsr_seed_t RndCnstLfsrSeed = RndCnstLfsrSeedDefault, + parameter lfsr_perm_t RndCnstLfsrPerm = RndCnstLfsrPermDefault +) ( + input clk_i, + input rst_ni, + output logic edn_req_o, // request to EDN + input edn_ack_i, // ack from EDN + input [EdnDataWidth-1:0] edn_data_i, // from EDN + input timer_en_i, // enable timer + input otp_prog_busy_i, // indicates whether prog ops are in progress + input integ_chk_trig_i, // one-off trigger for integrity check + input cnsty_chk_trig_i, // one-off trigger for consistency check + output logic chk_pending_o, // indicates whether there are pending checks + input [31:0] timeout_i, // check timeout + input [31:0] integ_period_msk_i, // maximum integrity check mask + input [31:0] cnsty_period_msk_i, // maximum consistency check mask + output logic [NumPart-1:0] integ_chk_req_o, // request to all partitions + output logic [NumPart-1:0] cnsty_chk_req_o, // request to all partitions + input [NumPart-1:0] integ_chk_ack_i, // response from partitions + input [NumPart-1:0] cnsty_chk_ack_i, // response from partitions + input caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_t escalate_en_i, // escalation input, moves FSM into ErrorSt + output logic chk_timeout_o, // a check has timed out + output logic fsm_err_o // the FSM has reached an invalid state +); + + //////////////////// + // Reseed counter // + //////////////////// + + // Count how many times the LFSR has been used to generate a value. + // Once we've reached the limit, we request new entropy from EDN to reseed + // the LFSR. Note that this is not a blocking operation for the timer below. + // I.e., the timer is allowed to continue its operation, and may draw more + // values, even if the EDN reseed request is still in progress. + logic reseed_en, lfsr_en; + logic [$clog2(LfsrUsageThreshold+1)-1:0] reseed_cnt_d, reseed_cnt_q; + assign reseed_cnt_d = (reseed_en) ? '0 : + (edn_req_o) ? reseed_cnt_q : + (lfsr_en) ? reseed_cnt_q + 1'b1 : + reseed_cnt_q; + + assign edn_req_o = (reseed_cnt_q >= LfsrUsageThreshold); + assign reseed_en = edn_req_o & edn_ack_i; + + /////////////////////////// + // Tandem LFSR Instances // + /////////////////////////// + + logic lfsr_err; + logic [LfsrWidth-1:0] entropy; + logic [LfsrWidth-1:0] lfsr_state; + assign entropy = (reseed_en) ? edn_data_i[LfsrWidth-1:0] : '0; + + // We employ two redundant LFSRs to guard against FI attacks. + // If any of the two is glitched and the two LFSR states do not agree, + // the FSM below is moved into a terminal error state. + // SEC_CM: TIMER.LFSR.REDUN + caliptra_prim_double_lfsr #( + .LfsrDw ( LfsrWidth ), + .EntropyDw ( LfsrWidth ), + .StateOutDw ( LfsrWidth ), + .DefaultSeed ( RndCnstLfsrSeed ), + .StatePermEn ( 1'b1 ), + .StatePerm ( RndCnstLfsrPerm ), + .ExtSeedSVA ( 1'b0 ) + ) u_prim_double_lfsr ( + .clk_i, + .rst_ni, + .seed_en_i ( 1'b0 ), + .seed_i ( '0 ), + .lfsr_en_i ( reseed_en || lfsr_en ), + .entropy_i ( entropy ), + .state_o ( lfsr_state ), + .err_o ( lfsr_err ) + ); + + // Not all entropy bits are used. + logic unused_seed; + assign unused_seed = ^edn_data_i; + + `CALIPTRA_ASSERT_INIT(EdnIsWideEnough_A, EdnDataWidth >= LfsrWidth) + + ////////////////////////////// + // Tandem Counter Instances // + ////////////////////////////// + + // We employ redundant counters to guard against FI attacks. + // If any of them is glitched and the redundant counter states do not agree, + // the FSM below is moved into a terminal error state. + logic [LfsrWidth-1:0] integ_cnt, cnsty_cnt, integ_cnt_set_val, cnsty_cnt_set_val; + logic [LfsrWidth-1:0] integ_mask, cnsty_mask; + logic integ_set_period, integ_set_timeout, integ_cnt_zero; + logic cnsty_set_period, cnsty_set_timeout, cnsty_cnt_zero; + logic integ_cnt_set, cnsty_cnt_set, integ_cnt_err, cnsty_cnt_err; + logic timeout_zero, integ_msk_zero, cnsty_msk_zero, cnsty_cnt_pause; + + assign timeout_zero = (timeout_i == '0); + assign integ_msk_zero = (integ_period_msk_i == '0); + assign cnsty_msk_zero = (cnsty_period_msk_i == '0); + assign integ_cnt_zero = (integ_cnt == '0); + assign cnsty_cnt_zero = (cnsty_cnt == '0); + + assign integ_cnt_set = integ_set_period || integ_set_timeout; + assign cnsty_cnt_set = cnsty_set_period || cnsty_set_timeout; + + assign integ_mask = {integ_period_msk_i, {LfsrWidth-32{1'b1}}}; + assign cnsty_mask = {cnsty_period_msk_i, {LfsrWidth-32{1'b1}}}; + assign integ_cnt_set_val = (integ_set_period) ? (lfsr_state & integ_mask) : LfsrWidth'(timeout_i); + assign cnsty_cnt_set_val = (cnsty_set_period) ? (lfsr_state & cnsty_mask) : LfsrWidth'(timeout_i); + + // SEC_CM: TIMER_INTEG.CTR.REDUN + caliptra_prim_count #( + .Width(LfsrWidth) + ) u_prim_count_integ ( + .clk_i, + .rst_ni, + .clr_i(1'b0), + .set_i(integ_cnt_set), + .set_cnt_i(integ_cnt_set_val), + .incr_en_i(1'b0), + .decr_en_i(!integ_cnt_zero), + .step_i(LfsrWidth'(1)), + .commit_i(1'b1), + .cnt_o(integ_cnt), + .cnt_after_commit_o(), + .err_o(integ_cnt_err) + ); + + // SEC_CM: TIMER_CNSTY.CTR.REDUN + caliptra_prim_count #( + .Width(LfsrWidth) + ) u_prim_count_cnsty ( + .clk_i, + .rst_ni, + .clr_i(1'b0), + .set_i(cnsty_cnt_set), + .set_cnt_i(cnsty_cnt_set_val), + .incr_en_i(1'b0), + .decr_en_i(!cnsty_cnt_zero && !cnsty_cnt_pause), + .step_i(LfsrWidth'(1)), + .commit_i(1'b1), + .cnt_o(cnsty_cnt), + .cnt_after_commit_o(), + .err_o(cnsty_cnt_err) + ); + + ///////////////////// + // Request signals // + ///////////////////// + + logic set_all_integ_reqs, set_all_cnsty_reqs; + logic [NumPart-1:0] integ_chk_req_d, integ_chk_req_q; + logic [NumPart-1:0] cnsty_chk_req_d, cnsty_chk_req_q; + assign integ_chk_req_o = integ_chk_req_q; + assign cnsty_chk_req_o = cnsty_chk_req_q; + assign integ_chk_req_d = (set_all_integ_reqs) ? {NumPart{1'b1}} : + integ_chk_req_q & ~integ_chk_ack_i; + assign cnsty_chk_req_d = (set_all_cnsty_reqs) ? {NumPart{1'b1}} : + cnsty_chk_req_q & ~cnsty_chk_ack_i; + + + // external triggers + logic clr_integ_chk_trig, clr_cnsty_chk_trig; + logic integ_chk_trig_d, integ_chk_trig_q; + logic cnsty_chk_trig_d, cnsty_chk_trig_q; + assign integ_chk_trig_d = (integ_chk_trig_q & ~clr_integ_chk_trig) | integ_chk_trig_i; + assign cnsty_chk_trig_d = (cnsty_chk_trig_q & ~clr_cnsty_chk_trig) | cnsty_chk_trig_i; + + //////////////////////////// + // Ping and Timeout Logic // + //////////////////////////// + + // SEC_CM: TIMER.FSM.SPARSE + // Encoding generated with: + // $ ./util/design/sparse-fsm-encode.py -d 5 -m 5 -n 9 \ + // -s 628816752 --language=sv + // + // Hamming distance histogram: + // + // 0: -- + // 1: -- + // 2: -- + // 3: -- + // 4: -- + // 5: |||||||||||||||||||| (60.00%) + // 6: ||||||||||||| (40.00%) + // 7: -- + // 8: -- + // 9: -- + // + // Minimum Hamming distance: 5 + // Maximum Hamming distance: 6 + // Minimum Hamming weight: 4 + // Maximum Hamming weight: 6 + // + localparam int StateWidth = 9; + typedef enum logic [StateWidth-1:0] { + ResetSt = 9'b100100101, + IdleSt = 9'b001101110, + IntegWaitSt = 9'b010110011, + CnstyWaitSt = 9'b111010110, + ErrorSt = 9'b001011001 + } state_e; + + state_e state_d, state_q; + logic chk_timeout_d, chk_timeout_q; + + assign chk_timeout_o = chk_timeout_q; + + always_comb begin : p_fsm + state_d = state_q; + + // LFSR and counter signals + lfsr_en = 1'b0; + integ_set_period = 1'b0; + cnsty_set_period = 1'b0; + integ_set_timeout = 1'b0; + cnsty_set_timeout = 1'b0; + cnsty_cnt_pause = 1'b0; + + // Requests going to partitions. + set_all_integ_reqs = '0; + set_all_cnsty_reqs = '0; + + // Status signals going to CSRs and error logic. + chk_timeout_d = chk_timeout_q; + chk_pending_o = cnsty_chk_trig_q || integ_chk_trig_q; + fsm_err_o = 1'b0; + + // Clear signals for external triggers + clr_integ_chk_trig = 1'b0; + clr_cnsty_chk_trig = 1'b0; + + unique case (state_q) + /////////////////////////////////////////////////////////////////// + // Wait until enabled. We never return to this state + // once enabled! + ResetSt: begin + if (timer_en_i) begin + state_d = IdleSt; + lfsr_en = 1'b1; + end + end + /////////////////////////////////////////////////////////////////// + // Wait here until one of the two timers expires (if enabled) or if + // a check is triggered externally. + IdleSt: begin + if ((!integ_msk_zero && integ_cnt_zero) || integ_chk_trig_q) begin + state_d = IntegWaitSt; + integ_set_timeout = 1'b1; + set_all_integ_reqs = 1'b1; + clr_integ_chk_trig = integ_chk_trig_q; + end else if ((!cnsty_msk_zero && cnsty_cnt_zero) || cnsty_chk_trig_q) begin + state_d = CnstyWaitSt; + cnsty_set_timeout = 1'b1; + set_all_cnsty_reqs = 1'b1; + clr_cnsty_chk_trig = cnsty_chk_trig_q; + end + end + /////////////////////////////////////////////////////////////////// + // Wait for all the partitions to respond and go back to idle. + // If the timeout is enabled, bail out into terminal error state + // if the timeout counter expires (this will raise an alert). + IntegWaitSt: begin + chk_pending_o = 1'b1; + if (!timeout_zero && integ_cnt_zero) begin + state_d = ErrorSt; + chk_timeout_d = 1'b1; + end else if (integ_chk_req_q == '0) begin + state_d = IdleSt; + // This draws the next wait period. + integ_set_period = 1'b1; + lfsr_en = 1'b1; + end + end + /////////////////////////////////////////////////////////////////// + // Wait for all the partitions to respond and go back to idle. + // If the timeout is enabled, bail out into terminal error state + // if the timeout counter expires (this will raise an alert). + CnstyWaitSt: begin + chk_pending_o = 1'b1; + // Note that consistency checks go back and read from OTP. Hence, + // life cycle transitions and DAI programming operations + // may interfere with these checks and cause them to take longer + // than typically expected. Therefore, the timeout counter is stopped + // during programming operations. + cnsty_cnt_pause = otp_prog_busy_i; + if (!timeout_zero && cnsty_cnt_zero) begin + state_d = ErrorSt; + chk_timeout_d = 1'b1; + end else if (cnsty_chk_req_q == '0) begin + state_d = IdleSt; + // This draws the next wait period. + cnsty_set_period = 1'b1; + lfsr_en = 1'b1; + end + end + /////////////////////////////////////////////////////////////////// + // Terminal error state. This raises an alert. + ErrorSt: begin + // Continuously clear pending checks. + clr_integ_chk_trig = 1'b1; + clr_cnsty_chk_trig = 1'b1; + if (!chk_timeout_q) begin + fsm_err_o = 1'b1; + end + end + /////////////////////////////////////////////////////////////////// + // This should never happen, hence we directly jump into the + // error state, where an alert will be triggered. + default: begin + state_d = ErrorSt; + fsm_err_o = 1'b1; + end + /////////////////////////////////////////////////////////////////// + endcase // state_q + + // Unconditionally jump into the terminal error state in case of escalation, + // or if the two LFSR or counter states do not agree. + // SEC_CM: TIMER.FSM.LOCAL_ESC, TIMER.FSM.GLOBAL_ESC + if (lfsr_err || integ_cnt_err || cnsty_cnt_err || + caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_test_true_loose(escalate_en_i)) begin + state_d = ErrorSt; + fsm_err_o = 1'b1; + end + end + + /////////////// + // Registers // + /////////////// + + `CALIPTRA_PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt) + + always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs + if (!rst_ni) begin + integ_chk_req_q <= '0; + cnsty_chk_req_q <= '0; + chk_timeout_q <= 1'b0; + reseed_cnt_q <= '0; + integ_chk_trig_q <= 1'b0; + cnsty_chk_trig_q <= 1'b0; + end else begin + integ_chk_req_q <= integ_chk_req_d; + cnsty_chk_req_q <= cnsty_chk_req_d; + chk_timeout_q <= chk_timeout_d; + reseed_cnt_q <= reseed_cnt_d; + integ_chk_trig_q <= integ_chk_trig_d; + cnsty_chk_trig_q <= cnsty_chk_trig_d; + end + end + + //////////////// + // Assertions // + //////////////// + + `CALIPTRA_ASSERT_KNOWN(EdnReqKnown_A, edn_req_o) + `CALIPTRA_ASSERT_KNOWN(ChkPendingKnown_A, chk_pending_o) + `CALIPTRA_ASSERT_KNOWN(IntegChkReqKnown_A, integ_chk_req_o) + `CALIPTRA_ASSERT_KNOWN(CnstyChkReqKnown_A, cnsty_chk_req_o) + `CALIPTRA_ASSERT_KNOWN(ChkTimeoutKnown_A, chk_timeout_o) + +endmodule : otp_ctrl_lfsr_timer diff --git a/src/fuse_ctrl/rtl/otp_ctrl_part_buf.sv b/src/fuse_ctrl/rtl/otp_ctrl_part_buf.sv new file mode 100644 index 0000000..92e5b96 --- /dev/null +++ b/src/fuse_ctrl/rtl/otp_ctrl_part_buf.sv @@ -0,0 +1,821 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Buffered partition for OTP controller. +// + +`include "caliptra_prim_flop_macros.sv" + +module otp_ctrl_part_buf + import otp_ctrl_pkg::*; + import otp_ctrl_reg_pkg::*; + import otp_ctrl_part_pkg::*; +#( + // Partition information. + parameter part_info_t Info = PartInfoDefault, + parameter logic [Info.size*8-1:0] DataDefault = '0 +) ( + input clk_i, + input rst_ni, + // Pulse to start partition initialisation (required once per power cycle). + input init_req_i, + output logic init_done_o, + // Integrity check requests + input integ_chk_req_i, + output logic integ_chk_ack_o, + // Consistency check requests + input cnsty_chk_req_i, + output logic cnsty_chk_ack_o, + // Escalation input. This moves the FSM into a terminal state and locks down + // the partition. + input caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_t escalate_en_i, + // Check bypass enable. This bypasses integrity and consistency checks and + // acknowledges all incoming check requests (only used by life cycle). + input caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_t check_byp_en_i, + // Output error state of partition, to be consumed by OTP error/alert logic. + // Note that most errors are not recoverable and move the partition FSM into + // a terminal error state. + output otp_err_e error_o, + // This error signal is pulsed high if the FSM has been glitched into an invalid state. + // Although it is somewhat redundant with the error code in error_o above, it is + // meant to cover cases where we already latched an error code while the FSM is + // glitched into an invalid state (since in that case, the error code will not be + // overridden with the FSM error code so that the original error code is still + // discoverable). + output logic fsm_err_o, + // Access/lock status + // SEC_CM: ACCESS.CTRL.MUBI + input part_access_t access_i, // runtime lock from CSRs + output part_access_t access_o, + // Buffered 64bit digest output. + output logic [ScrmblBlockWidth-1:0] digest_o, + output logic [Info.size*8-1:0] data_o, + // OTP interface + output logic otp_req_o, + output caliptra_prim_otp_pkg::cmd_e otp_cmd_o, + output logic [OtpSizeWidth-1:0] otp_size_o, + output logic [OtpIfWidth-1:0] otp_wdata_o, + output logic [OtpAddrWidth-1:0] otp_addr_o, + input otp_gnt_i, + input otp_rvalid_i, + input [ScrmblBlockWidth-1:0] otp_rdata_i, + input caliptra_prim_otp_pkg::err_e otp_err_i, + // Scrambling mutex request + output logic scrmbl_mtx_req_o, + input scrmbl_mtx_gnt_i, + // Scrambling datapath interface + output otp_scrmbl_cmd_e scrmbl_cmd_o, + output digest_mode_e scrmbl_mode_o, + output logic [ConstSelWidth-1:0] scrmbl_sel_o, + output logic [ScrmblBlockWidth-1:0] scrmbl_data_o, + output logic scrmbl_valid_o, + input logic scrmbl_ready_i, + input logic scrmbl_valid_i, + input logic [ScrmblBlockWidth-1:0] scrmbl_data_i +); + + //////////////////////// + // Integration Checks // + //////////////////////// + + import caliptra_prim_mubi_pkg::*; + import caliptra_prim_util_pkg::vbits; + + localparam int unsigned DigestOffsetInt = (int'(Info.offset) + + int'(Info.size) - ScrmblBlockWidth/8); + localparam int NumScrmblBlocks = int'(Info.size) / (ScrmblBlockWidth/8); + localparam int CntWidth = vbits(NumScrmblBlocks); + + localparam bit [OtpByteAddrWidth-1:0] DigestOffset = DigestOffsetInt[OtpByteAddrWidth-1:0]; + + localparam int unsigned LastScrmblBlockInt = NumScrmblBlocks - 1; + localparam int unsigned PenultimateScrmblBlockInt = NumScrmblBlocks - 2; + localparam bit [CntWidth-1:0] LastScrmblBlock = LastScrmblBlockInt[CntWidth-1:0]; + localparam bit [CntWidth-1:0] PenultimateScrmblBlock = PenultimateScrmblBlockInt[CntWidth-1:0]; + + // Integration checks for parameters. + `CALIPTRA_ASSERT_INIT(OffsetMustBeBlockAligned_A, (Info.offset % (ScrmblBlockWidth/8)) == 0) + `CALIPTRA_ASSERT_INIT(SizeMustBeBlockAligned_A, (Info.size % (ScrmblBlockWidth/8)) == 0) + `CALIPTRA_ASSERT_INIT(DigestOffsetMustBeRepresentable_A, DigestOffsetInt == int'(DigestOffset)) + `CALIPTRA_ASSERT(ScrambledImpliesDigest_A, Info.secret |-> Info.hw_digest) + `CALIPTRA_ASSERT(WriteLockImpliesDigest_A, Info.read_lock |-> Info.hw_digest) + `CALIPTRA_ASSERT(ReadLockImpliesDigest_A, Info.write_lock |-> Info.hw_digest) + + // This feature is only supposed to be used with partitions that are not scrambled + // and that do not have a digest. + `CALIPTRA_ASSERT(BypassEnable0_A, Info.secret |-> caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_test_false_strict(check_byp_en_i)) + `CALIPTRA_ASSERT(BypassEnable1_A, Info.hw_digest |-> caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_test_false_strict(check_byp_en_i)) + + /////////////////////// + // OTP Partition FSM // + /////////////////////// + + // SEC_CM: PART.FSM.SPARSE + // Encoding generated with: + // $ ./util/design/sparse-fsm-encode.py -d 5 -m 16 -n 12 \ + // -s 3370657881 --language=sv + // + // Hamming distance histogram: + // + // 0: -- + // 1: -- + // 2: -- + // 3: -- + // 4: -- + // 5: |||||||||||||| (28.33%) + // 6: |||||||||||||||||||| (38.33%) + // 7: |||||||||| (19.17%) + // 8: ||| (5.83%) + // 9: || (4.17%) + // 10: | (2.50%) + // 11: (0.83%) + // 12: (0.83%) + // + // Minimum Hamming distance: 5 + // Maximum Hamming distance: 12 + // Minimum Hamming weight: 4 + // Maximum Hamming weight: 8 + // + localparam int StateWidth = 12; + typedef enum logic [StateWidth-1:0] { + ResetSt = 12'b011000001110, + InitSt = 12'b110100100111, + InitWaitSt = 12'b001110110001, + InitDescrSt = 12'b110010000100, + InitDescrWaitSt = 12'b100110101000, + IdleSt = 12'b010101001101, + IntegScrSt = 12'b110101011010, + IntegScrWaitSt = 12'b100010011111, + IntegDigClrSt = 12'b101001000001, + IntegDigSt = 12'b011101100010, + IntegDigPadSt = 12'b001101010111, + IntegDigFinSt = 12'b011011100101, + IntegDigWaitSt = 12'b100011110010, + CnstyReadSt = 12'b000001101011, + CnstyReadWaitSt = 12'b101001111100, + ErrorSt = 12'b010110111110 + } state_e; + + typedef enum logic { + ScrmblData, + OtpData + } data_sel_e; + + typedef enum logic { + PartOffset, + DigOffset + } base_sel_e; + + state_e state_d, state_q; + otp_err_e error_d, error_q; + data_sel_e data_sel; + base_sel_e base_sel; + mubi8_t dout_locked_d, dout_locked_q; + logic [CntWidth-1:0] cnt; + logic cnt_en, cnt_clr, cnt_err; + logic ecc_err; + logic buffer_reg_en; + logic [ScrmblBlockWidth-1:0] data_mux; + + // Output partition error state. + assign error_o = error_q; + + // This partition cannot do any write accesses, hence we tie this + // constantly off. + assign otp_wdata_o = '0; + // Depending on the partition configuration, the wrapper is instructed to ignore integrity + // calculations and checks. To be on the safe side, the partition filters error responses at this + // point and does not report any integrity errors if integrity is disabled. + otp_err_e otp_err; + if (Info.integrity) begin : gen_integrity + assign otp_cmd_o = caliptra_prim_otp_pkg::Read; + assign otp_err = otp_err_e'(otp_err_i); + end else begin : gen_no_integrity + assign otp_cmd_o = caliptra_prim_otp_pkg::ReadRaw; + always_comb begin + if (otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}) begin + otp_err = NoError; + end else begin + otp_err = otp_err_e'(otp_err_i); + end + end + end + + always_comb begin : p_fsm + state_d = state_q; + + // Redundantly encoded lock signal for buffer regs. + dout_locked_d = dout_locked_q; + + // OTP signals + otp_req_o = 1'b0; + + // Scrambling mutex + scrmbl_mtx_req_o = 1'b0; + + // Scrambling datapath + scrmbl_cmd_o = LoadShadow; + scrmbl_sel_o = CnstyDigest; + scrmbl_mode_o = StandardMode; + scrmbl_valid_o = 1'b0; + + // Counter + cnt_en = 1'b0; + cnt_clr = 1'b0; + base_sel = PartOffset; + + // Buffer register + buffer_reg_en = 1'b0; + data_sel = OtpData; + + // Error Register + error_d = error_q; + fsm_err_o = 1'b0; + + // Integrity/Consistency check responses + cnsty_chk_ack_o = 1'b0; + integ_chk_ack_o = 1'b0; + + unique case (state_q) + /////////////////////////////////////////////////////////////////// + // State right after reset. Wait here until we get a an + // initialization request. + ResetSt: begin + if (init_req_i) begin + state_d = InitSt; + end + end + /////////////////////////////////////////////////////////////////// + // Initialization reads out the digest only in unbuffered + // partitions. Wait here until the OTP request has been granted. + // And then wait until the OTP word comes back. + InitSt: begin + otp_req_o = 1'b1; + if (otp_gnt_i) begin + state_d = InitWaitSt; + end + end + /////////////////////////////////////////////////////////////////// + // Wait for OTP response and write to buffer register, then go to + // descrambling state. In case an OTP transaction fails, latch the + // OTP error code and jump to a + // terminal error state. + InitWaitSt: begin + if (otp_rvalid_i) begin + buffer_reg_en = 1'b1; + if (otp_err inside {NoError, MacroEccCorrError}) begin + // Once we've read and descrambled the whole partition, we can go to integrity + // verification. Note that the last block is the digest value, which does not + // have to be descrambled. + if (cnt == LastScrmblBlock) begin + state_d = IntegDigClrSt; + // Only need to descramble if this is a scrambled partition. + // Otherwise, we can just go back to InitSt and read the next block. + end else if (Info.secret) begin + state_d = InitDescrSt; + end else begin + state_d = InitSt; + cnt_en = 1'b1; + end + // At this point the only error that we could have gotten are correctable ECC errors. + if (otp_err != NoError) begin + error_d = MacroEccCorrError; + end + end else begin + state_d = ErrorSt; + error_d = otp_err; + end + end + end + /////////////////////////////////////////////////////////////////// + // Descrambling state. This first acquires the scrambling + // datapath mutex. Note that once the mutex is acquired, we have + // exclusive access to the scrambling datapath until we release + // the mutex by deasserting scrmbl_mtx_req_o. + // SEC_CM: SECRET.MEM.SCRAMBLE + InitDescrSt: begin + scrmbl_mtx_req_o = 1'b1; + scrmbl_valid_o = 1'b1; + scrmbl_cmd_o = Decrypt; + scrmbl_sel_o = Info.key_sel; + if (scrmbl_mtx_gnt_i && scrmbl_ready_i) begin + state_d = InitDescrWaitSt; + end + end + /////////////////////////////////////////////////////////////////// + // Wait for the descrambled data to return. Note that we release + // the mutex lock upon leaving this state. + // SEC_CM: SECRET.MEM.SCRAMBLE + InitDescrWaitSt: begin + scrmbl_mtx_req_o = 1'b1; + scrmbl_sel_o = Info.key_sel; + data_sel = ScrmblData; + if (scrmbl_valid_i) begin + state_d = InitSt; + buffer_reg_en = 1'b1; + cnt_en = 1'b1; + end + end + /////////////////////////////////////////////////////////////////// + // Idle state. We basically wait for integrity and consistency check + // triggers in this state. + IdleSt: begin + if (integ_chk_req_i) begin + if (Info.hw_digest) begin + state_d = IntegDigClrSt; + // In case there is nothing to check we can just + // acknowledge the request right away, without going to the + // integrity check. + end else begin + integ_chk_ack_o = 1'b1; + end + end else if (cnsty_chk_req_i) begin + state_d = CnstyReadSt; + cnt_clr = 1'b1; + end + end + /////////////////////////////////////////////////////////////////// + // Read the digest. Wait here until the OTP request has been granted. + // And then wait until the OTP word comes back. + // SEC_CM: PART.DATA_REG.BKGN_CHK + CnstyReadSt: begin + otp_req_o = 1'b1; + // In case this partition has a hardware digest, we only have to read + // and compare the digest value. In that case we select the digest offset here. + // Otherwise we have to read and compare the whole partition, in which case we + // select the partition offset, which is the default assignment of base_sel. + if (Info.hw_digest) begin + base_sel = DigOffset; + end + if (otp_gnt_i) begin + state_d = CnstyReadWaitSt; + end + end + /////////////////////////////////////////////////////////////////// + // Wait for OTP response and compare the digest. In case there is + // a mismatch, lock down the partition and go into the terminal error + // state. In case an OTP transaction fails, latch the OTP error code + // and jump to a terminal error state. + // SEC_CM: PART.DATA_REG.BKGN_CHK + CnstyReadWaitSt: begin + if (otp_rvalid_i) begin + if (otp_err inside {NoError, MacroEccCorrError}) begin + // Check whether we need to compare the digest or the full partition + // contents here. + if (Info.hw_digest) begin + // Note that we ignore this check if the digest is still blank. + if (digest_o == data_mux || digest_o == '0) begin + state_d = IdleSt; + cnsty_chk_ack_o = 1'b1; + // Error out and lock the partition if this check fails. + end else begin + state_d = ErrorSt; + error_d = CheckFailError; + // The check has finished and found an error. + cnsty_chk_ack_o = 1'b1; + end + end else begin + // Check whether the read data corresponds with the data buffered in regs. + // Note that this particular check can be bypassed in case a transition is ongoing. + if (scrmbl_data_o == data_mux || + caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_test_true_strict(check_byp_en_i)) begin + // Can go back to idle and acknowledge the + // request if this is the last block. + if (cnt == LastScrmblBlock) begin + state_d = IdleSt; + cnsty_chk_ack_o = 1'b1; + // Need to go back and read out more blocks. + end else begin + state_d = CnstyReadSt; + cnt_en = 1'b1; + end + end else begin + state_d = ErrorSt; + error_d = CheckFailError; + // The check has finished and found an error. + cnsty_chk_ack_o = 1'b1; + end + end + // At this point the only error that we could have gotten are correctable ECC errors. + if (otp_err != NoError) begin + error_d = MacroEccCorrError; + end + end else begin + state_d = ErrorSt; + error_d = otp_err; + // The check has finished and found an error. + cnsty_chk_ack_o = 1'b1; + end + end + end + /////////////////////////////////////////////////////////////////// + // First, acquire the mutex for the digest and clear the digest state. + // SEC_CM: PART.DATA_REG.BKGN_CHK + IntegDigClrSt: begin + // Check whether this partition requires checking at all. + if (Info.hw_digest) begin + scrmbl_mtx_req_o = 1'b1; + scrmbl_valid_o = 1'b1; + cnt_clr = 1'b1; + // Need to reset the digest state and set it to chained + // mode if this partition is scrambled. + scrmbl_cmd_o = DigestInit; + if (Info.secret) begin + scrmbl_mode_o = ChainedMode; + if (scrmbl_mtx_gnt_i && scrmbl_ready_i) begin + state_d = IntegScrSt; + end + // If this partition is not scrambled, we can just directly + // jump to the digest state. + end else begin + scrmbl_mode_o = StandardMode; + if (scrmbl_mtx_gnt_i && scrmbl_ready_i) begin + state_d = IntegDigSt; + end + end + // Otherwise, if this partition is not digest protected, + // we can just go to idle, since there is nothing to check. + // Note that we do not come back to this state in case there is no + // digest, and hence it is safe to unlock the buffer regs at this point. + // This is the only way the buffer regs can get unlocked. + end else begin + state_d = IdleSt; + if (mubi8_test_true_strict(dout_locked_q)) begin + dout_locked_d = MuBi8False; + end + end + end + /////////////////////////////////////////////////////////////////// + // Scramble buffered data (which is held in plaintext form). + // This moves the previous scrambling result into the shadow reg + // for later use. + // SEC_CM: PART.DATA_REG.BKGN_CHK + IntegScrSt: begin + scrmbl_mtx_req_o = 1'b1; + scrmbl_valid_o = 1'b1; + scrmbl_cmd_o = Encrypt; + scrmbl_sel_o = Info.key_sel; + if (scrmbl_ready_i) begin + state_d = IntegScrWaitSt; + end + end + /////////////////////////////////////////////////////////////////// + // Wait for the scrambled data to return. + // SEC_CM: PART.DATA_REG.BKGN_CHK + IntegScrWaitSt: begin + scrmbl_mtx_req_o = 1'b1; + scrmbl_sel_o = Info.key_sel; + if (scrmbl_valid_i) begin + state_d = IntegDigSt; + end + end + /////////////////////////////////////////////////////////////////// + // Push the word read into the scrambling datapath. The last + // block is repeated in case the number blocks in this partition + // is odd. + // SEC_CM: PART.MEM.DIGEST + // SEC_CM: PART.DATA_REG.BKGN_CHK + IntegDigSt: begin + scrmbl_mtx_req_o = 1'b1; + scrmbl_valid_o = 1'b1; + if (scrmbl_ready_i) begin + cnt_en = 1'b1; + // No need to digest the digest value itself + if (cnt == PenultimateScrmblBlock) begin + // Note that the digest operates on 128bit blocks since the data is fed in via the + // PRESENT key input. Therefore, we only trigger a digest update on every second + // 64bit block that is pushed into the scrambling datapath. + if (cnt[0]) begin + scrmbl_cmd_o = Digest; + state_d = IntegDigFinSt; + end else begin + state_d = IntegDigPadSt; + cnt_en = 1'b0; + end + end else begin + // Trigger digest round in case this is the second block in a row. + if (cnt[0]) begin + scrmbl_cmd_o = Digest; + end + // Go back and scramble the next data block if this is + // a scrambled partition. Otherwise just stay here. + if (Info.secret) begin + state_d = IntegScrSt; + end + end + end + end + /////////////////////////////////////////////////////////////////// + // Padding state. When we get here, we've copied the last encryption + // result into the shadow register such that we've effectively + // repeated the last block twice in order to pad the data to 128bit. + // SEC_CM: PART.MEM.DIGEST + // SEC_CM: PART.DATA_REG.BKGN_CHK + IntegDigPadSt: begin + scrmbl_mtx_req_o = 1'b1; + scrmbl_valid_o = 1'b1; + scrmbl_cmd_o = Digest; + if (scrmbl_ready_i) begin + state_d = IntegDigFinSt; + end + end + /////////////////////////////////////////////////////////////////// + // Trigger digest finalization and go wait for the result. + // SEC_CM: PART.MEM.DIGEST + // SEC_CM: PART.DATA_REG.BKGN_CHK + IntegDigFinSt: begin + scrmbl_mtx_req_o = 1'b1; + scrmbl_valid_o = 1'b1; + scrmbl_cmd_o = DigestFinalize; + if (scrmbl_ready_i) begin + state_d = IntegDigWaitSt; + end + end + /////////////////////////////////////////////////////////////////// + // Wait for the digest to return, and double check whether the digest + // matches. If yes, unlock the partition. Otherwise, go into the terminal + // error state, where the partition will be locked down. + // SEC_CM: PART.MEM.DIGEST + // SEC_CM: PART.DATA_REG.BKGN_CHK + IntegDigWaitSt: begin + scrmbl_mtx_req_o = 1'b1; + data_sel = ScrmblData; + if (scrmbl_valid_i) begin + // This is the only way the buffer regs can get unlocked. + // Note that we ignore this check if the digest is still blank. + if (digest_o == data_mux || digest_o == '0) begin + state_d = IdleSt; + // If the partition is still locked, this is the first integrity check after + // initialization. This is the only way the buffer regs can get unlocked. + if (mubi8_test_true_strict(dout_locked_q)) begin + dout_locked_d = MuBi8False; + // Otherwise, this integrity check has requested by the LFSR timer, and we have + // to acknowledge its completion. + end else begin + integ_chk_ack_o = 1'b1; + end + // Error out and lock the partition if this check fails. + end else begin + state_d = ErrorSt; + error_d = CheckFailError; + // The check has finished and found an error. + integ_chk_ack_o = 1'b1; + end + end + end + /////////////////////////////////////////////////////////////////// + // Terminal Error State. This locks access to the partition. + // Make sure the partition signals an error state if no error + // code has been latched so far, and lock the buffer regs down. + ErrorSt: begin + dout_locked_d = MuBi8True; + if (error_q == NoError) begin + error_d = FsmStateError; + end + // If we are in error state, we cannot execute the checks anymore. + // Hence the acknowledgements are returned immediately. + cnsty_chk_ack_o = 1'b1; + integ_chk_ack_o = 1'b1; + end + /////////////////////////////////////////////////////////////////// + // We should never get here. If we do (e.g. via a malicious + // glitch), error out immediately. + default: begin + state_d = ErrorSt; + fsm_err_o = 1'b1; + end + /////////////////////////////////////////////////////////////////// + endcase // state_q + + + // Unconditionally jump into the terminal error state in case of + // an ECC error or escalation, and lock access to the partition down. + // SEC_CM: PART.FSM.LOCAL_ESC + if (ecc_err) begin + state_d = ErrorSt; + if (state_q != ErrorSt) begin + error_d = CheckFailError; + end + end + // SEC_CM: PART.FSM.LOCAL_ESC, PART.FSM.GLOBAL_ESC + if (caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_test_true_loose(escalate_en_i) || cnt_err) begin + state_d = ErrorSt; + fsm_err_o = 1'b1; + if (state_q != ErrorSt) begin + error_d = FsmStateError; + end + end + end + + //////////////////////////// + // Address Calc and Muxes // + //////////////////////////// + + // Address counter - this is only used for computing a digest, hence the increment is + // fixed to 8 byte. + // SEC_CM: PART.CTR.REDUN + caliptra_prim_count #( + .Width(CntWidth) + ) u_prim_count ( + .clk_i, + .rst_ni, + .clr_i(cnt_clr), + .set_i(1'b0), + .set_cnt_i('0), + .incr_en_i(cnt_en), + .decr_en_i(1'b0), + .step_i(CntWidth'(1)), + .commit_i(1'b1), + .cnt_o(cnt), + .cnt_after_commit_o(), + .err_o(cnt_err) + ); + + logic [OtpByteAddrWidth-1:0] addr_base; + assign addr_base = (base_sel == DigOffset) ? DigestOffset : Info.offset; + + // Note that OTP works on halfword (16bit) addresses, hence need to + // shift the addresses appropriately. + logic [OtpByteAddrWidth-1:0] addr_calc; + assign addr_calc = OtpByteAddrWidth'({cnt, {$clog2(ScrmblBlockWidth/8){1'b0}}}) + addr_base; + assign otp_addr_o = addr_calc[OtpByteAddrWidth-1:OtpAddrShift]; + + if (OtpAddrShift > 0) begin : gen_unused + logic unused_bits; + assign unused_bits = ^addr_calc[OtpAddrShift-1:0]; + end + + // Always transfer 64bit blocks. + assign otp_size_o = OtpSizeWidth'(unsigned'(ScrmblBlockWidth / OtpWidth) - 1); + + assign data_mux = (data_sel == ScrmblData) ? scrmbl_data_i : otp_rdata_i; + + ///////////////// + // Buffer Regs // + ///////////////// + + // SEC_CM: PART.DATA_REG.INTEGRITY + logic [Info.size*8-1:0] data; + otp_ctrl_ecc_reg #( + .Width ( ScrmblBlockWidth ), + .Depth ( NumScrmblBlocks ) + ) u_otp_ctrl_ecc_reg ( + .clk_i, + .rst_ni, + .wren_i ( buffer_reg_en ), + .addr_i ( cnt ), + .wdata_i ( data_mux ), + .rdata_o ( scrmbl_data_o ), + .data_o ( data ), + .ecc_err_o ( ecc_err ) + ); + + // We have successfully initialized the partition once it has been unlocked. + assign init_done_o = mubi8_test_false_strict(dout_locked_q); + // Hardware output gating. + // Note that this is decoupled from the DAI access rules further below. + assign data_o = (init_done_o) ? data : DataDefault; + // The digest does not have to be gated. + assign digest_o = data[$high(data_o) -: ScrmblBlockWidth]; + + //////////////////////// + // DAI Access Control // + //////////////////////// + + // Aggregate all possible DAI write /readlocks. The partition is also locked when uninitialized. + // Note that the locks are redundantly encoded values. + part_access_t access_pre; + caliptra_prim_mubi8_sender #( + .AsyncOn(0) + ) u_prim_mubi8_sender_write_lock_pre ( + .clk_i, + .rst_ni, + .mubi_i(mubi8_and_lo(dout_locked_q, access_i.write_lock)), + .mubi_o(access_pre.write_lock) + ); + caliptra_prim_mubi8_sender #( + .AsyncOn(0) + ) u_prim_mubi8_sender_read_lock_pre ( + .clk_i, + .rst_ni, + .mubi_i(mubi8_and_lo(dout_locked_q, access_i.read_lock)), + .mubi_o(access_pre.read_lock) + ); + + // SEC_CM: PART.MEM.SW_UNWRITABLE + if (Info.write_lock) begin : gen_digest_write_lock + mubi8_t digest_locked; + assign digest_locked = (digest_o != '0) ? MuBi8True : MuBi8False; + + // This prevents the synthesis tool from optimizing the multibit signal. + caliptra_prim_mubi8_sender #( + .AsyncOn(0) + ) u_prim_mubi8_sender_write_lock ( + .clk_i, + .rst_ni, + .mubi_i(mubi8_and_lo(access_pre.write_lock, digest_locked)), + .mubi_o(access_o.write_lock) + ); + + `CALIPTRA_ASSERT(DigestWriteLocksPartition_A, digest_o |-> mubi8_test_true_loose(access_o.write_lock)) + end else begin : gen_no_digest_write_lock + assign access_o.write_lock = access_pre.write_lock; + end + + // SEC_CM: PART.MEM.SW_UNREADABLE + if (Info.read_lock) begin : gen_digest_read_lock + mubi8_t digest_locked; + assign digest_locked = (digest_o != '0) ? MuBi8True : MuBi8False; + + // This prevents the synthesis tool from optimizing the multibit signal. + caliptra_prim_mubi8_sender #( + .AsyncOn(0) + ) u_prim_mubi8_sender_read_lock ( + .clk_i, + .rst_ni, + .mubi_i(mubi8_and_lo(access_pre.read_lock, digest_locked)), + .mubi_o(access_o.read_lock) + ); + + `CALIPTRA_ASSERT(DigestReadLocksPartition_A, digest_o |-> mubi8_test_true_loose(access_o.read_lock)) + end else begin : gen_no_digest_read_lock + assign access_o.read_lock = access_pre.read_lock; + end + + /////////////// + // Registers // + /////////////// + + `CALIPTRA_PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt) + + always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs + if (!rst_ni) begin + error_q <= NoError; + // data output is locked by default + dout_locked_q <= MuBi8True; + end else begin + error_q <= error_d; + dout_locked_q <= dout_locked_d; + end + end + + //////////////// + // Assertions // + //////////////// + + // Known assertions + `CALIPTRA_ASSERT_KNOWN(InitDoneKnown_A, init_done_o) + `CALIPTRA_ASSERT_KNOWN(IntegChkAckKnown_A, integ_chk_ack_o) + `CALIPTRA_ASSERT_KNOWN(CnstyChkAckKnown_A, cnsty_chk_ack_o) + `CALIPTRA_ASSERT_KNOWN(ErrorKnown_A, error_o) + `CALIPTRA_ASSERT_KNOWN(AccessKnown_A, access_o) + `CALIPTRA_ASSERT_KNOWN(DigestKnown_A, digest_o) + `CALIPTRA_ASSERT_KNOWN(DataKnown_A, data_o) + `CALIPTRA_ASSERT_KNOWN(OtpReqKnown_A, otp_req_o) + `CALIPTRA_ASSERT_KNOWN(OtpCmdKnown_A, otp_cmd_o) + `CALIPTRA_ASSERT_KNOWN(OtpSizeKnown_A, otp_size_o) + `CALIPTRA_ASSERT_KNOWN(OtpWdataKnown_A, otp_wdata_o) + `CALIPTRA_ASSERT_KNOWN(OtpAddrKnown_A, otp_addr_o) + `CALIPTRA_ASSERT_KNOWN(ScrmblMtxReqKnown_A, scrmbl_mtx_req_o) + `CALIPTRA_ASSERT_KNOWN(ScrmblCmdKnown_A, scrmbl_cmd_o) + `CALIPTRA_ASSERT_KNOWN(ScrmblModeKnown_A, scrmbl_mode_o) + `CALIPTRA_ASSERT_KNOWN(ScrmblSelKnown_A, scrmbl_sel_o) + `CALIPTRA_ASSERT_KNOWN(ScrmblDataKnown_A, scrmbl_data_o) + `CALIPTRA_ASSERT_KNOWN(ScrmblValidKnown_A, scrmbl_valid_o) + + // Uninitialized partitions should always be locked, no matter what. + `CALIPTRA_ASSERT(InitWriteLocksPartition_A, + mubi8_test_true_loose(dout_locked_q) + |-> + mubi8_test_true_loose(access_o.write_lock)) + `CALIPTRA_ASSERT(InitReadLocksPartition_A, + mubi8_test_true_loose(dout_locked_q) + |-> + mubi8_test_true_loose(access_o.read_lock)) + // Incoming Lock propagation + `CALIPTRA_ASSERT(WriteLockPropagation_A, + mubi8_test_true_loose(access_i.write_lock) + |-> + mubi8_test_true_loose(access_o.write_lock)) + `CALIPTRA_ASSERT(ReadLockPropagation_A, + mubi8_test_true_loose(access_i.read_lock) + |-> + mubi8_test_true_loose(access_o.read_lock)) + // ECC error in buffer regs + `CALIPTRA_ASSERT(EccErrorState_A, + ecc_err + |=> + state_q == ErrorSt) + // OTP error response + `CALIPTRA_ASSERT(OtpErrorState_A, + state_q inside {InitWaitSt, CnstyReadWaitSt} && otp_rvalid_i && + !(otp_err inside {NoError, MacroEccCorrError}) && !ecc_err + |=> + state_q == ErrorSt && error_o == $past(otp_err)) + + // The partition size must be greater than one scrambling block for the address calculation + // and muxing to work correctly. + `CALIPTRA_ASSERT_INIT(OtpPartBufSize_A, Info.size > (ScrmblBlockWidth/8)) + +endmodule : otp_ctrl_part_buf diff --git a/src/fuse_ctrl/rtl/otp_ctrl_part_pkg.sv b/src/fuse_ctrl/rtl/otp_ctrl_part_pkg.sv new file mode 100644 index 0000000..ccd9e8e --- /dev/null +++ b/src/fuse_ctrl/rtl/otp_ctrl_part_pkg.sv @@ -0,0 +1,682 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Package partition metadata. +// +// DO NOT EDIT THIS FILE DIRECTLY. +// It has been generated with ./util/design/gen-otp-mmap.py + +package otp_ctrl_part_pkg; + + import caliptra_prim_util_pkg::vbits; + import otp_ctrl_reg_pkg::*; + import otp_ctrl_pkg::*; + + //////////////////////////////////// + // Scrambling Constants and Types // + //////////////////////////////////// + + parameter int NumScrmblKeys = 3; + parameter int NumDigestSets = 4; + + parameter int ScrmblKeySelWidth = vbits(NumScrmblKeys); + parameter int DigestSetSelWidth = vbits(NumDigestSets); + parameter int ConstSelWidth = (ScrmblKeySelWidth > DigestSetSelWidth) ? + ScrmblKeySelWidth : + DigestSetSelWidth; + + typedef enum logic [ConstSelWidth-1:0] { + StandardMode, + ChainedMode + } digest_mode_e; + + typedef logic [NumScrmblKeys-1:0][ScrmblKeyWidth-1:0] key_array_t; + typedef logic [NumDigestSets-1:0][ScrmblKeyWidth-1:0] digest_const_array_t; + typedef logic [NumDigestSets-1:0][ScrmblBlockWidth-1:0] digest_iv_array_t; + + typedef enum logic [ConstSelWidth-1:0] { + Secret0Key, + Secret1Key, + Secret2Key + } key_sel_e; + + typedef enum logic [ConstSelWidth-1:0] { + CnstyDigest, + FlashDataKey, + FlashAddrKey, + SramDataKey + } digest_sel_e; + + // SEC_CM: SECRET.MEM.SCRAMBLE + parameter key_array_t RndCnstKey = { + 128'h85A9E830BC059BA9286D6E2856A05CC3, + 128'hEFFA6D736C5EFF49AE7B70F9C46E5A62, + 128'h3BA121C5E097DDEB7768B4C666E9C3DA + }; + + // SEC_CM: PART.MEM.DIGEST + // Note: digest set 0 is used for computing the partition digests. Constants at + // higher indices are used to compute the scrambling keys. + // [anjpar]: Added *Default parameter as we are not running topgen script + parameter digest_const_array_t RndCnstDigestConst= { + 128'h4A22D4B78FE0266FBEE3958332F2939B, + 128'hD60822E1FAEC5C7290C7F21F6224F027, + 128'h277195FC471E4B26B6641214B61D1B43, + 128'hE95F517CB98955B4D5A89AA9109294A + }; + + parameter digest_const_array_t RndCnstDigestConstDefault = { + 128'h4A22D4B78FE0266FBEE3958332F2939B, + 128'hD60822E1FAEC5C7290C7F21F6224F027, + 128'h277195FC471E4B26B6641214B61D1B43, + 128'hE95F517CB98955B4D5A89AA9109294A + }; + + parameter digest_iv_array_t RndCnstDigestIV = { + 64'hF98C48B1F9377284, + 64'hB7474D640F8A7F5, + 64'hE048B657396B4B83, + 64'hBEAD91D5FA4E0915 + }; + + parameter digest_iv_array_t RndCnstDigestIVDefault = { + 64'hF98C48B1F9377284, + 64'hB7474D640F8A7F5, + 64'hE048B657396B4B83, + 64'hBEAD91D5FA4E0915 + }; + + + ///////////////////////////////////// + // Typedefs for Partition Metadata // + ///////////////////////////////////// + + typedef enum logic [1:0] { + Unbuffered, + Buffered, + LifeCycle + } part_variant_e; + + typedef struct packed { + part_variant_e variant; + // Offset and size within the OTP array, in Bytes. + logic [OtpByteAddrWidth-1:0] offset; + logic [OtpByteAddrWidth-1:0] size; + // Key index to use for scrambling. + key_sel_e key_sel; + // Attributes + logic secret; // Whether the partition is secret (and hence scrambled) + logic sw_digest; // Whether the partition has a software digest + logic hw_digest; // Whether the partition has a hardware digest + logic write_lock; // Whether the partition is write lockable (via digest) + logic read_lock; // Whether the partition is read lockable (via digest) + logic integrity; // Whether the partition is integrity protected + logic iskeymgr_creator; // Whether the partition has any creator key material + logic iskeymgr_owner; // Whether the partition has any owner key material + } part_info_t; + + parameter part_info_t PartInfoDefault = '{ + variant: Unbuffered, + offset: '0, + size: OtpByteAddrWidth'('hFF), + key_sel: key_sel_e'('0), + secret: 1'b0, + sw_digest: 1'b0, + hw_digest: 1'b0, + write_lock: 1'b0, + read_lock: 1'b0, + integrity: 1'b0, + iskeymgr_creator: 1'b0, + iskeymgr_owner: 1'b0 + }; + + //////////////////////// + // Partition Metadata // + //////////////////////// + + localparam part_info_t PartInfo [NumPart] = '{ + // VENDOR_TEST + '{ + variant: Unbuffered, + offset: 11'd0, + size: 64, + key_sel: key_sel_e'('0), + secret: 1'b0, + sw_digest: 1'b1, + hw_digest: 1'b0, + write_lock: 1'b1, + read_lock: 1'b0, + integrity: 1'b0, + iskeymgr_creator: 1'b0, + iskeymgr_owner: 1'b0 + }, + // CREATOR_SW_CFG + '{ + variant: Unbuffered, + offset: 11'd64, + size: 368, + key_sel: key_sel_e'('0), + secret: 1'b0, + sw_digest: 1'b1, + hw_digest: 1'b0, + write_lock: 1'b1, + read_lock: 1'b0, + integrity: 1'b1, + iskeymgr_creator: 1'b0, + iskeymgr_owner: 1'b0 + }, + // OWNER_SW_CFG + '{ + variant: Unbuffered, + offset: 11'd432, + size: 712, + key_sel: key_sel_e'('0), + secret: 1'b0, + sw_digest: 1'b1, + hw_digest: 1'b0, + write_lock: 1'b1, + read_lock: 1'b0, + integrity: 1'b1, + iskeymgr_creator: 1'b0, + iskeymgr_owner: 1'b0 + }, + // ROT_CREATOR_AUTH_CODESIGN + '{ + variant: Unbuffered, + offset: 11'd1144, + size: 472, + key_sel: key_sel_e'('0), + secret: 1'b0, + sw_digest: 1'b1, + hw_digest: 1'b0, + write_lock: 1'b1, + read_lock: 1'b0, + integrity: 1'b1, + iskeymgr_creator: 1'b0, + iskeymgr_owner: 1'b0 + }, + // ROT_CREATOR_AUTH_STATE + '{ + variant: Unbuffered, + offset: 11'd1616, + size: 40, + key_sel: key_sel_e'('0), + secret: 1'b0, + sw_digest: 1'b1, + hw_digest: 1'b0, + write_lock: 1'b1, + read_lock: 1'b0, + integrity: 1'b1, + iskeymgr_creator: 1'b0, + iskeymgr_owner: 1'b0 + }, + // HW_CFG0 + '{ + variant: Buffered, + offset: 11'd1656, + size: 72, + key_sel: key_sel_e'('0), + secret: 1'b0, + sw_digest: 1'b0, + hw_digest: 1'b1, + write_lock: 1'b1, + read_lock: 1'b0, + integrity: 1'b1, + iskeymgr_creator: 1'b0, + iskeymgr_owner: 1'b0 + }, + // HW_CFG1 + '{ + variant: Buffered, + offset: 11'd1728, + size: 16, + key_sel: key_sel_e'('0), + secret: 1'b0, + sw_digest: 1'b0, + hw_digest: 1'b1, + write_lock: 1'b1, + read_lock: 1'b0, + integrity: 1'b1, + iskeymgr_creator: 1'b0, + iskeymgr_owner: 1'b0 + }, + // SECRET0 + '{ + variant: Buffered, + offset: 11'd1744, + size: 40, + key_sel: Secret0Key, + secret: 1'b1, + sw_digest: 1'b0, + hw_digest: 1'b1, + write_lock: 1'b1, + read_lock: 1'b1, + integrity: 1'b1, + iskeymgr_creator: 1'b0, + iskeymgr_owner: 1'b0 + }, + // SECRET1 + '{ + variant: Buffered, + offset: 11'd1784, + size: 88, + key_sel: Secret1Key, + secret: 1'b1, + sw_digest: 1'b0, + hw_digest: 1'b1, + write_lock: 1'b1, + read_lock: 1'b1, + integrity: 1'b1, + iskeymgr_creator: 1'b0, + iskeymgr_owner: 1'b0 + }, + // SECRET2 + '{ + variant: Buffered, + offset: 11'd1872, + size: 88, + key_sel: Secret2Key, + secret: 1'b1, + sw_digest: 1'b0, + hw_digest: 1'b1, + write_lock: 1'b1, + read_lock: 1'b1, + integrity: 1'b1, + iskeymgr_creator: 1'b1, + iskeymgr_owner: 1'b0 + }, + // LIFE_CYCLE + '{ + variant: LifeCycle, + offset: 11'd1960, + size: 88, + key_sel: key_sel_e'('0), + secret: 1'b0, + sw_digest: 1'b0, + hw_digest: 1'b0, + write_lock: 1'b0, + read_lock: 1'b0, + integrity: 1'b1, + iskeymgr_creator: 1'b0, + iskeymgr_owner: 1'b0 + } + }; + + typedef enum { + VendorTestIdx, + CreatorSwCfgIdx, + OwnerSwCfgIdx, + RotCreatorAuthCodesignIdx, + RotCreatorAuthStateIdx, + HwCfg0Idx, + HwCfg1Idx, + Secret0Idx, + Secret1Idx, + Secret2Idx, + LifeCycleIdx, + // These are not "real partitions", but in terms of implementation it is convenient to + // add these at the end of certain arrays. + DaiIdx, + LciIdx, + KdiIdx, + // Number of agents is the last idx+1. + NumAgentsIdx + } part_idx_e; + + parameter int NumAgents = int'(NumAgentsIdx); + + // Breakout types for easier access of individual items. + typedef struct packed { + logic [63:0] hw_cfg0_digest; + logic [255:0] manuf_state; + logic [255:0] device_id; + } otp_hw_cfg0_data_t; + + // default value used for intermodule + parameter otp_hw_cfg0_data_t OTP_HW_CFG0_DATA_DEFAULT = '{ + hw_cfg0_digest: 64'hF87BED95CFBA3727, + manuf_state: 256'hDF3888886BD10DC67ABB319BDA0529AE40119A3C6E63CDF358840E458E4029A6, + device_id: 256'h63B9485A3856C417CF7A50A9A91EF7F7B3A5B4421F462370FFF698183664DC7E + }; + typedef struct packed { + logic [63:0] hw_cfg1_digest; + logic [39:0] unallocated; + caliptra_prim_mubi_pkg::mubi8_t dis_rv_dm_late_debug; + caliptra_prim_mubi_pkg::mubi8_t en_csrng_sw_app_read; + caliptra_prim_mubi_pkg::mubi8_t en_sram_ifetch; + } otp_hw_cfg1_data_t; + + // default value used for intermodule + parameter otp_hw_cfg1_data_t OTP_HW_CFG1_DATA_DEFAULT = '{ + hw_cfg1_digest: 64'hBBF4A76885E754F2, + unallocated: 40'h0, + dis_rv_dm_late_debug: caliptra_prim_mubi_pkg::mubi8_t'(8'h69), + en_csrng_sw_app_read: caliptra_prim_mubi_pkg::mubi8_t'(8'h69), + en_sram_ifetch: caliptra_prim_mubi_pkg::mubi8_t'(8'h69) + }; + typedef struct packed { + // This reuses the same encoding as the life cycle signals for indicating valid status. + caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_t valid; + otp_hw_cfg1_data_t hw_cfg1_data; + otp_hw_cfg0_data_t hw_cfg0_data; + } otp_broadcast_t; + + // default value for intermodule + parameter otp_broadcast_t OTP_BROADCAST_DEFAULT = '{ + valid: caliptra_ss_lc_ctrl_pkg::Off, + hw_cfg1_data: OTP_HW_CFG1_DATA_DEFAULT, + hw_cfg0_data: OTP_HW_CFG0_DATA_DEFAULT + }; + + + // OTP invalid partition default for buffered partitions. + parameter logic [16383:0] PartInvDefault = 16384'({ + 704'({ + 320'h93B61DE417B9FB339605F051E74379CBCC6596C7174EBA643E725E464F593C87A445C3C29F71A256, + 384'hA0D1E90E8C9FDDFA01E46311FD36D95401136C663A36C3E3E817E760B27AE937BFCDF15A3429452A851B80674A2B6FBE + }), + 704'({ + 64'h8CBBAD02BB4CA928, + 256'hD68C96F0B3D1FEED688098A43C33459F0279FC51CC7C626E315FD2B871D88819, + 256'hD0BAC511D08ECE0E2C0DBDDEDF7A854D5E58D0AA97A0F8F6D3D58610F4851667, + 128'h94CD3DED94B578192A4D8B51F5D41C8A + }), + 704'({ + 64'hC469C593E5DC0DA8, + 128'hE00E9680BD9B70291C752824C7DDC896, + 256'h105733EAA3880C5A234729143F97B62A55D0320379A0D260426D99D374E699CA, + 256'hDBC827839FE2DCC27E17D06B5D4E0DDDDBB9844327F20FB5D396D1CE085BDC31 + }), + 320'({ + 64'hBE193854E9CA60A0, + 128'h711D135F59A50322B6711DB6F5D40A37, + 128'hB5AC1F53D00A08C3B28B5C0FEE5F4C02 + }), + 128'({ + 64'hBBF4A76885E754F2, + 40'h0, // unallocated space + 8'h69, + 8'h69, + 8'h69 + }), + 576'({ + 64'hF87BED95CFBA3727, + 256'hDF3888886BD10DC67ABB319BDA0529AE40119A3C6E63CDF358840E458E4029A6, + 256'h63B9485A3856C417CF7A50A9A91EF7F7B3A5B4421F462370FFF698183664DC7E + }), + 320'({ + 64'h20440F25BB053FB5, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0 + }), + 3776'({ + 64'h15F164D7930C9D19, + 256'h0, + 32'h0, + 256'h0, + 32'h0, + 32'h0, + 256'h0, + 32'h0, + 32'h0, + 256'h0, + 32'h0, + 32'h0, + 256'h0, + 32'h0, + 512'h0, + 32'h0, + 512'h0, + 32'h0, + 512'h0, + 32'h0, + 512'h0, + 32'h0 + }), + 5696'({ + 64'hE29749216775E8A5, + 96'h0, // unallocated space + 1024'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 96'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 512'h0, + 128'h0, + 128'h0, + 512'h0, + 2560'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0 + }), + 2944'({ + 64'h340A5B93BB19342, + 96'h0, // unallocated space + 256'h0, + 256'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 1248'h0 + }), + 512'({ + 64'h4947DD361344767A, + 448'h0 + })}); + + /////////////////////////////////////////////// + // Parameterized Assignment Helper Functions // + /////////////////////////////////////////////// + + function automatic otp_ctrl_core_hw2reg_t named_reg_assign( + logic [NumPart-1:0][ScrmblBlockWidth-1:0] part_digest); + otp_ctrl_core_hw2reg_t hw2reg; + logic unused_sigs; + unused_sigs = ^part_digest; + hw2reg = '0; + hw2reg.vendor_test_digest = part_digest[VendorTestIdx]; + hw2reg.creator_sw_cfg_digest = part_digest[CreatorSwCfgIdx]; + hw2reg.owner_sw_cfg_digest = part_digest[OwnerSwCfgIdx]; + hw2reg.rot_creator_auth_codesign_digest = part_digest[RotCreatorAuthCodesignIdx]; + hw2reg.rot_creator_auth_state_digest = part_digest[RotCreatorAuthStateIdx]; + hw2reg.hw_cfg0_digest = part_digest[HwCfg0Idx]; + hw2reg.hw_cfg1_digest = part_digest[HwCfg1Idx]; + hw2reg.secret0_digest = part_digest[Secret0Idx]; + hw2reg.secret1_digest = part_digest[Secret1Idx]; + hw2reg.secret2_digest = part_digest[Secret2Idx]; + return hw2reg; + endfunction : named_reg_assign + + function automatic part_access_t [NumPart-1:0] named_part_access_pre( + otp_ctrl_core_reg2hw_t reg2hw); + part_access_t [NumPart-1:0] part_access_pre; + logic unused_sigs; + unused_sigs = ^reg2hw; + // Default (this will be overridden by partition-internal settings). + part_access_pre = {{32'(2*NumPart)}{caliptra_prim_mubi_pkg::MuBi8False}}; + // Note: these could be made a MuBi CSRs in the future. + // The main thing that is missing right now is proper support for W0C. + // VENDOR_TEST + if (!reg2hw.vendor_test_read_lock) begin + part_access_pre[VendorTestIdx].read_lock = caliptra_prim_mubi_pkg::MuBi8True; + end + // CREATOR_SW_CFG + if (!reg2hw.creator_sw_cfg_read_lock) begin + part_access_pre[CreatorSwCfgIdx].read_lock = caliptra_prim_mubi_pkg::MuBi8True; + end + // OWNER_SW_CFG + if (!reg2hw.owner_sw_cfg_read_lock) begin + part_access_pre[OwnerSwCfgIdx].read_lock = caliptra_prim_mubi_pkg::MuBi8True; + end + // ROT_CREATOR_AUTH_CODESIGN + if (!reg2hw.rot_creator_auth_codesign_read_lock) begin + part_access_pre[RotCreatorAuthCodesignIdx].read_lock = caliptra_prim_mubi_pkg::MuBi8True; + end + // ROT_CREATOR_AUTH_STATE + if (!reg2hw.rot_creator_auth_state_read_lock) begin + part_access_pre[RotCreatorAuthStateIdx].read_lock = caliptra_prim_mubi_pkg::MuBi8True; + end + return part_access_pre; + endfunction : named_part_access_pre + + function automatic otp_broadcast_t named_broadcast_assign( + logic [NumPart-1:0] part_init_done, + logic [$bits(PartInvDefault)/8-1:0][7:0] part_buf_data); + otp_broadcast_t otp_broadcast; + logic valid, unused; + unused = 1'b0; + valid = 1'b1; + // VENDOR_TEST + unused ^= ^{part_init_done[VendorTestIdx], + part_buf_data[VendorTestOffset +: VendorTestSize]}; + // CREATOR_SW_CFG + unused ^= ^{part_init_done[CreatorSwCfgIdx], + part_buf_data[CreatorSwCfgOffset +: CreatorSwCfgSize]}; + // OWNER_SW_CFG + unused ^= ^{part_init_done[OwnerSwCfgIdx], + part_buf_data[OwnerSwCfgOffset +: OwnerSwCfgSize]}; + // ROT_CREATOR_AUTH_CODESIGN + unused ^= ^{part_init_done[RotCreatorAuthCodesignIdx], + part_buf_data[RotCreatorAuthCodesignOffset +: RotCreatorAuthCodesignSize]}; + // ROT_CREATOR_AUTH_STATE + unused ^= ^{part_init_done[RotCreatorAuthStateIdx], + part_buf_data[RotCreatorAuthStateOffset +: RotCreatorAuthStateSize]}; + // HW_CFG0 + valid &= part_init_done[HwCfg0Idx]; + otp_broadcast.hw_cfg0_data = otp_hw_cfg0_data_t'(part_buf_data[HwCfg0Offset +: HwCfg0Size]); + // HW_CFG1 + valid &= part_init_done[HwCfg1Idx]; + otp_broadcast.hw_cfg1_data = otp_hw_cfg1_data_t'(part_buf_data[HwCfg1Offset +: HwCfg1Size]); + // SECRET0 + unused ^= ^{part_init_done[Secret0Idx], + part_buf_data[Secret0Offset +: Secret0Size]}; + // SECRET1 + unused ^= ^{part_init_done[Secret1Idx], + part_buf_data[Secret1Offset +: Secret1Size]}; + // SECRET2 + unused ^= ^{part_init_done[Secret2Idx], + part_buf_data[Secret2Offset +: Secret2Size]}; + // LIFE_CYCLE + unused ^= ^{part_init_done[LifeCycleIdx], + part_buf_data[LifeCycleOffset +: LifeCycleSize]}; + otp_broadcast.valid = caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_bool_to_caliptra_ss_lc_tx(valid); + return otp_broadcast; + endfunction : named_broadcast_assign + + function automatic otp_keymgr_key_t named_keymgr_key_assign( + logic [NumPart-1:0][ScrmblBlockWidth-1:0] part_digest, + logic [$bits(PartInvDefault)/8-1:0][7:0] part_buf_data, + caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_t caliptra_ss_lc_seed_hw_rd_en); + otp_keymgr_key_t otp_keymgr_key; + logic valid, unused; + unused = 1'b0; + // For now we use a fixed struct type here so that the + // interface to the keymgr remains stable. The type contains + // a superset of all options, so we have to initialize it to '0 here. + otp_keymgr_key = '0; + // VENDOR_TEST + unused ^= ^{part_digest[VendorTestIdx], + part_buf_data[VendorTestOffset +: VendorTestSize]}; + // CREATOR_SW_CFG + unused ^= ^{part_digest[CreatorSwCfgIdx], + part_buf_data[CreatorSwCfgOffset +: CreatorSwCfgSize]}; + // OWNER_SW_CFG + unused ^= ^{part_digest[OwnerSwCfgIdx], + part_buf_data[OwnerSwCfgOffset +: OwnerSwCfgSize]}; + // ROT_CREATOR_AUTH_CODESIGN + unused ^= ^{part_digest[RotCreatorAuthCodesignIdx], + part_buf_data[RotCreatorAuthCodesignOffset +: RotCreatorAuthCodesignSize]}; + // ROT_CREATOR_AUTH_STATE + unused ^= ^{part_digest[RotCreatorAuthStateIdx], + part_buf_data[RotCreatorAuthStateOffset +: RotCreatorAuthStateSize]}; + // HW_CFG0 + unused ^= ^{part_digest[HwCfg0Idx], + part_buf_data[HwCfg0Offset +: HwCfg0Size]}; + // HW_CFG1 + unused ^= ^{part_digest[HwCfg1Idx], + part_buf_data[HwCfg1Offset +: HwCfg1Size]}; + // SECRET0 + unused ^= ^{part_digest[Secret0Idx], + part_buf_data[Secret0Offset +: Secret0Size]}; + // SECRET1 + unused ^= ^{part_digest[Secret1Idx], + part_buf_data[Secret1Offset +: Secret1Size]}; + // SECRET2 + valid = (part_digest[Secret2Idx] != 0); + unused ^= ^part_buf_data[RmaTokenOffset +: RmaTokenSize]; + otp_keymgr_key.creator_root_key_share0_valid = valid; + if (caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_test_true_strict(caliptra_ss_lc_seed_hw_rd_en)) begin + otp_keymgr_key.creator_root_key_share0 = + part_buf_data[CreatorRootKeyShare0Offset +: CreatorRootKeyShare0Size]; + end else begin + otp_keymgr_key.creator_root_key_share0 = + PartInvDefault[CreatorRootKeyShare0Offset*8 +: CreatorRootKeyShare0Size*8]; + end + otp_keymgr_key.creator_root_key_share1_valid = valid; + if (caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_test_true_strict(caliptra_ss_lc_seed_hw_rd_en)) begin + otp_keymgr_key.creator_root_key_share1 = + part_buf_data[CreatorRootKeyShare1Offset +: CreatorRootKeyShare1Size]; + end else begin + otp_keymgr_key.creator_root_key_share1 = + PartInvDefault[CreatorRootKeyShare1Offset*8 +: CreatorRootKeyShare1Size*8]; + end + // This is not used since we consume the + // ungated digest values from the part_digest array. + unused ^= ^part_buf_data[Secret2DigestOffset +: Secret2DigestSize]; + // LIFE_CYCLE + unused ^= ^{part_digest[LifeCycleIdx], + part_buf_data[LifeCycleOffset +: LifeCycleSize]}; + unused ^= valid; + return otp_keymgr_key; + endfunction : named_keymgr_key_assign + +endpackage : otp_ctrl_part_pkg diff --git a/src/fuse_ctrl/rtl/otp_ctrl_part_unbuf.sv b/src/fuse_ctrl/rtl/otp_ctrl_part_unbuf.sv new file mode 100644 index 0000000..5e4b7f5 --- /dev/null +++ b/src/fuse_ctrl/rtl/otp_ctrl_part_unbuf.sv @@ -0,0 +1,531 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Unbuffered partition for OTP controller. +// + +`include "caliptra_prim_flop_macros.sv" + +module otp_ctrl_part_unbuf + import otp_ctrl_pkg::*; + import otp_ctrl_reg_pkg::*; + import otp_ctrl_part_pkg::*; +#( + // Partition information. + parameter part_info_t Info = PartInfoDefault +) ( + input clk_i, + input rst_ni, + // Pulse to start partition initialisation (required once per power cycle). + input init_req_i, + output logic init_done_o, + // Escalation input. This moves the FSM into a terminal state and locks down + // the partition. + input caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_t escalate_en_i, + // Output error state of partition, to be consumed by OTP error/alert logic. + // Note that most errors are not recoverable and move the partition FSM into + // a terminal error state. + output otp_err_e error_o, + // This error signal is pulsed high if the FSM has been glitched into an invalid state. + // Although it is somewhat redundant with the error code in error_o above, it is + // meant to cover cases where we already latched an error code while the FSM is + // glitched into an invalid state (since in that case, the error code will not be + // overridden with the FSM error code so that the original error code is still + // discoverable). + output logic fsm_err_o, + // Access/lock status + // SEC_CM: ACCESS.CTRL.MUBI + input part_access_t access_i, // runtime lock from CSRs + output part_access_t access_o, + // Buffered 64bit digest output. + output logic [ScrmblBlockWidth-1:0] digest_o, + // Interface to TL-UL adapter + input logic tlul_req_i, + output logic tlul_gnt_o, + input [SwWindowAddrWidth-1:0] tlul_addr_i, + output logic [1:0] tlul_rerror_o, + output logic tlul_rvalid_o, + output logic [31:0] tlul_rdata_o, + // OTP interface + output logic otp_req_o, + output caliptra_prim_otp_pkg::cmd_e otp_cmd_o, + output logic [OtpSizeWidth-1:0] otp_size_o, + output logic [OtpIfWidth-1:0] otp_wdata_o, + output logic [OtpAddrWidth-1:0] otp_addr_o, + input otp_gnt_i, + input otp_rvalid_i, + input [ScrmblBlockWidth-1:0] otp_rdata_i, + input caliptra_prim_otp_pkg::err_e otp_err_i +); + + //////////////////////// + // Integration Checks // + //////////////////////// + + import caliptra_prim_mubi_pkg::*; + import caliptra_prim_util_pkg::vbits; + + localparam logic [OtpByteAddrWidth:0] PartEnd = (OtpByteAddrWidth+1)'(Info.offset) + + (OtpByteAddrWidth+1)'(Info.size); + localparam int unsigned DigestOffsetInt = int'(PartEnd) - ScrmblBlockWidth/8; + + localparam bit [OtpByteAddrWidth-1:0] DigestOffset = DigestOffsetInt[OtpByteAddrWidth-1:0]; + + // Integration checks for parameters. + `CALIPTRA_ASSERT_INIT(OffsetMustBeBlockAligned_A, (Info.offset % (ScrmblBlockWidth/8)) == 0) + `CALIPTRA_ASSERT_INIT(SizeMustBeBlockAligned_A, (Info.size % (ScrmblBlockWidth/8)) == 0) + `CALIPTRA_ASSERT_INIT(DigestOffsetMustBeRepresentable_A, DigestOffsetInt == int'(DigestOffset)) + + /////////////////////// + // OTP Partition FSM // + /////////////////////// + + // SEC_CM: PART.FSM.SPARSE + // Encoding generated with: + // $ ./util/design/sparse-fsm-encode.py -d 5 -m 7 -n 10 \ + // -s 4247417884 --language=sv + // + // Hamming distance histogram: + // + // 0: -- + // 1: -- + // 2: -- + // 3: -- + // 4: -- + // 5: |||||||||||||||||||| (52.38%) + // 6: |||||||||||| (33.33%) + // 7: | (4.76%) + // 8: ||| (9.52%) + // 9: -- + // 10: -- + // + // Minimum Hamming distance: 5 + // Maximum Hamming distance: 8 + // Minimum Hamming weight: 3 + // Maximum Hamming weight: 9 + // + localparam int StateWidth = 10; + typedef enum logic [StateWidth-1:0] { + ResetSt = 10'b1010110110, + InitSt = 10'b0100010011, + InitWaitSt = 10'b0001011000, + IdleSt = 10'b1011101001, + ReadSt = 10'b0101101110, + ReadWaitSt = 10'b0110100101, + ErrorSt = 10'b1111011111 + } state_e; + + typedef enum logic { + DigestAddrSel = 1'b0, + DataAddrSel = 1'b1 + } addr_sel_e; + + state_e state_d, state_q; + addr_sel_e otp_addr_sel; + otp_err_e error_d, error_q; + + logic digest_reg_en; + logic ecc_err; + + logic tlul_addr_in_range; + logic [SwWindowAddrWidth-1:0] tlul_addr_d, tlul_addr_q; + + // This is only used to return bus errors when the FSM is in ErrorSt. + logic pending_tlul_error_d, pending_tlul_error_q; + + // Output partition error state. + assign error_o = error_q; + + // This partition cannot do any write accesses, hence we tie this + // constantly off. + assign otp_wdata_o = '0; + // Depending on the partition configuration, the wrapper is instructed to ignore integrity + // calculations and checks. To be on the safe side, the partition filters error responses at this + // point and does not report any integrity errors if integrity is disabled. + otp_err_e otp_err; + if (Info.integrity) begin : gen_integrity + assign otp_cmd_o = caliptra_prim_otp_pkg::Read; + assign otp_err = otp_err_e'(otp_err_i); + end else begin : gen_no_integrity + assign otp_cmd_o = caliptra_prim_otp_pkg::ReadRaw; + always_comb begin + if (otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}) begin + otp_err = NoError; + end else begin + otp_err = otp_err_e'(otp_err_i); + end + end + end + + `CALIPTRA_ASSERT_KNOWN(FsmStateKnown_A, state_q) + always_comb begin : p_fsm + // Default assignments + state_d = state_q; + + // Response to init request + init_done_o = 1'b0; + + // OTP signals + otp_req_o = 1'b0; + otp_addr_sel = DigestAddrSel; + + // TL-UL signals + tlul_gnt_o = 1'b0; + tlul_rvalid_o = 1'b0; + tlul_rerror_o = '0; + + // Enable for buffered digest register + digest_reg_en = 1'b0; + + // Error Register + error_d = error_q; + pending_tlul_error_d = 1'b0; + fsm_err_o = 1'b0; + + unique case (state_q) + /////////////////////////////////////////////////////////////////// + // State right after reset. Wait here until we get a an + // initialization request. + ResetSt: begin + if (init_req_i) begin + // If the partition does not have a digest, no initialization is necessary. + if (Info.sw_digest) begin + state_d = InitSt; + end else begin + state_d = IdleSt; + end + end + end + /////////////////////////////////////////////////////////////////// + // Initialization reads out the digest only in unbuffered + // partitions. Wait here until the OTP request has been granted. + // And then wait until the OTP word comes back. + InitSt: begin + otp_req_o = 1'b1; + if (otp_gnt_i) begin + state_d = InitWaitSt; + end + end + /////////////////////////////////////////////////////////////////// + // Wait for OTP response and write to digest buffer register. In + // case an OTP transaction fails, latch the OTP error code and + // jump to a terminal error state. + InitWaitSt: begin + if (otp_rvalid_i) begin + digest_reg_en = 1'b1; + if (otp_err inside {NoError, MacroEccCorrError}) begin + state_d = IdleSt; + // At this point the only error that we could have gotten are correctable ECC errors. + if (otp_err != NoError) begin + error_d = MacroEccCorrError; + end + end else begin + state_d = ErrorSt; + error_d = otp_err; + end + end + end + /////////////////////////////////////////////////////////////////// + // Wait for TL-UL requests coming in. + // Then latch address and go to readout state. + IdleSt: begin + init_done_o = 1'b1; + if (tlul_req_i) begin + error_d = NoError; // clear recoverable soft errors. + state_d = ReadSt; + tlul_gnt_o = 1'b1; + end + end + /////////////////////////////////////////////////////////////////// + // If the address is out of bounds, or if the partition is + // locked, signal back a bus error. Note that such an error does + // not cause the partition to go into error state. Otherwise if + // these checks pass, an OTP word is requested. + ReadSt: begin + init_done_o = 1'b1; + // Double check the address range. + if (tlul_addr_in_range && mubi8_test_false_strict(access_o.read_lock)) begin + otp_req_o = 1'b1; + otp_addr_sel = DataAddrSel; + if (otp_gnt_i) begin + state_d = ReadWaitSt; + end + end else begin + state_d = IdleSt; + error_d = AccessError; // Signal this error, but do not go into terminal error state. + tlul_rvalid_o = 1'b1; + tlul_rerror_o = 2'b11; // This causes the TL-UL adapter to return a bus error. + end + end + /////////////////////////////////////////////////////////////////// + // Wait for OTP response and release the TL-UL response. In + // case an OTP transaction fails, latch the OTP error code, + // signal a TL-Ul bus error and jump to a terminal error state. + ReadWaitSt: begin + init_done_o = 1'b1; + if (otp_rvalid_i) begin + tlul_rvalid_o = 1'b1; + if (otp_err inside {NoError, MacroEccCorrError}) begin + state_d = IdleSt; + // At this point the only error that we could have gotten are correctable ECC errors. + if (otp_err != NoError) begin + error_d = MacroEccCorrError; + end + end else begin + state_d = ErrorSt; + error_d = otp_err; + // This causes the TL-UL adapter to return a bus error. + tlul_rerror_o = 2'b11; + end + end + end + /////////////////////////////////////////////////////////////////// + // Terminal Error State. This locks access to the partition. + // Make sure the partition signals an error state if no error + // code has been latched so far. + ErrorSt: begin + if (error_q == NoError) begin + error_d = FsmStateError; + end + + // Return bus errors if there are pending TL-UL requests. + if (pending_tlul_error_q) begin + tlul_rerror_o = 2'b11; + tlul_rvalid_o = 1'b1; + end else if (tlul_req_i) begin + tlul_gnt_o = 1'b1; + pending_tlul_error_d = 1'b1; + end + end + /////////////////////////////////////////////////////////////////// + // We should never get here. If we do (e.g. via a malicious + // glitch), error out immediately. + default: begin + state_d = ErrorSt; + fsm_err_o = 1'b1; + end + /////////////////////////////////////////////////////////////////// + endcase // state_q + + // Unconditionally jump into the terminal error state in case of + // an ECC error or escalation, and lock access to the partition down. + // SEC_CM: PART.FSM.LOCAL_ESC + if (ecc_err) begin + state_d = ErrorSt; + if (state_q != ErrorSt) begin + error_d = CheckFailError; + end + end + // SEC_CM: PART.FSM.GLOBAL_ESC + if (caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_test_true_loose(escalate_en_i)) begin + state_d = ErrorSt; + fsm_err_o = 1'b1; + if (state_q != ErrorSt) begin + error_d = FsmStateError; + end + end + end + + /////////////////////////////////// + // Signals to/from TL-UL Adapter // + /////////////////////////////////// + + assign tlul_addr_d = tlul_addr_i; + // Do not forward data in case of an error. + assign tlul_rdata_o = (tlul_rvalid_o && tlul_rerror_o == '0) ? otp_rdata_i[31:0] : '0; + + if (Info.offset == 0) begin : gen_zero_offset + assign tlul_addr_in_range = {1'b0, tlul_addr_q, 2'b00} < PartEnd; + + end else begin : gen_nonzero_offset + assign tlul_addr_in_range = {tlul_addr_q, 2'b00} >= Info.offset && + {1'b0, tlul_addr_q, 2'b00} < PartEnd; + end + + // Note that OTP works on halfword (16bit) addresses, hence need to + // shift the addresses appropriately. + logic [OtpByteAddrWidth-1:0] addr_calc; + assign addr_calc = (otp_addr_sel == DigestAddrSel) ? DigestOffset : {tlul_addr_q, 2'b00}; + assign otp_addr_o = addr_calc[OtpByteAddrWidth-1:OtpAddrShift]; + + if (OtpAddrShift > 0) begin : gen_unused + logic unused_bits; + assign unused_bits = ^addr_calc[OtpAddrShift-1:0]; + end + + // Request 32bit except in case of the digest. + assign otp_size_o = (otp_addr_sel == DigestAddrSel) ? + OtpSizeWidth'(unsigned'(ScrmblBlockWidth / OtpWidth - 1)) : + OtpSizeWidth'(unsigned'(32 / OtpWidth - 1)); + + //////////////// + // Digest Reg // + //////////////// + + if (Info.sw_digest) begin : gen_ecc_reg + // SEC_CM: PART.DATA_REG.INTEGRITY + otp_ctrl_ecc_reg #( + .Width ( ScrmblBlockWidth ), + .Depth ( 1 ) + ) u_otp_ctrl_ecc_reg ( + .clk_i, + .rst_ni, + .wren_i ( digest_reg_en ), + .addr_i ( '0 ), + .wdata_i ( otp_rdata_i ), + .rdata_o ( ), + .data_o ( digest_o ), + .ecc_err_o ( ecc_err ) + ); + end else begin : gen_no_ecc_reg + logic unused_digest_reg_en; + logic unused_rdata; + assign unused_digest_reg_en = digest_reg_en; + assign unused_rdata = ^otp_rdata_i[32 +: 32]; // Upper word is not connected in this case. + assign digest_o = '0; + assign ecc_err = 1'b0; + end + + //////////////////////// + // DAI Access Control // + //////////////////////// + + mubi8_t init_locked; + assign init_locked = (~init_done_o) ? MuBi8True : MuBi8False; + + // Aggregate all possible DAI write locks. The partition is also locked when uninitialized. + // Note that the locks are redundantly encoded values. + part_access_t access_pre; + caliptra_prim_mubi8_sender #( + .AsyncOn(0) + ) u_prim_mubi8_sender_write_lock_pre ( + .clk_i, + .rst_ni, + .mubi_i(mubi8_and_lo(init_locked, access_i.write_lock)), + .mubi_o(access_pre.write_lock) + ); + caliptra_prim_mubi8_sender #( + .AsyncOn(0) + ) u_prim_mubi8_sender_read_lock_pre ( + .clk_i, + .rst_ni, + .mubi_i(mubi8_and_lo(init_locked, access_i.read_lock)), + .mubi_o(access_pre.read_lock) + ); + + // SEC_CM: PART.MEM.SW_UNWRITABLE + if (Info.write_lock) begin : gen_digest_write_lock + mubi8_t digest_locked; + assign digest_locked = (digest_o != '0) ? MuBi8True : MuBi8False; + + // This prevents the synthesis tool from optimizing the multibit signal. + caliptra_prim_mubi8_sender #( + .AsyncOn(0) + ) u_prim_mubi8_sender_write_lock ( + .clk_i, + .rst_ni, + .mubi_i(mubi8_and_lo(access_pre.write_lock, digest_locked)), + .mubi_o(access_o.write_lock) + ); + + `CALIPTRA_ASSERT(DigestWriteLocksPartition_A, digest_o |-> mubi8_test_true_loose(access_o.write_lock)) + end else begin : gen_no_digest_write_lock + assign access_o.write_lock = access_pre.write_lock; + end + + // SEC_CM: PART.MEM.SW_UNREADABLE + if (Info.read_lock) begin : gen_digest_read_lock + mubi8_t digest_locked; + assign digest_locked = (digest_o != '0) ? MuBi8True : MuBi8False; + + // This prevents the synthesis tool from optimizing the multibit signal. + caliptra_prim_mubi8_sender #( + .AsyncOn(0) + ) u_prim_mubi8_sender_read_lock ( + .clk_i, + .rst_ni, + .mubi_i(mubi8_and_lo(access_pre.read_lock, digest_locked)), + .mubi_o(access_o.read_lock) + ); + + `CALIPTRA_ASSERT(DigestReadLocksPartition_A, digest_o |-> mubi8_test_true_loose(access_o.read_lock)) + end else begin : gen_no_digest_read_lock + assign access_o.read_lock = access_pre.read_lock; + end + + /////////////// + // Registers // + /////////////// + + `CALIPTRA_PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt) + + always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs + if (!rst_ni) begin + error_q <= NoError; + tlul_addr_q <= '0; + pending_tlul_error_q <= 1'b0; + end else begin + error_q <= error_d; + pending_tlul_error_q <= pending_tlul_error_d; + if (tlul_gnt_o) begin + tlul_addr_q <= tlul_addr_d; + end + end + end + + //////////////// + // Assertions // + //////////////// + + // Known assertions + `CALIPTRA_ASSERT_KNOWN(InitDoneKnown_A, init_done_o) + `CALIPTRA_ASSERT_KNOWN(ErrorKnown_A, error_o) + `CALIPTRA_ASSERT_KNOWN(AccessKnown_A, access_o) + `CALIPTRA_ASSERT_KNOWN(DigestKnown_A, digest_o) + `CALIPTRA_ASSERT_KNOWN(TlulGntKnown_A, tlul_gnt_o) + `CALIPTRA_ASSERT_KNOWN(TlulRerrorKnown_A, tlul_rerror_o) + `CALIPTRA_ASSERT_KNOWN(TlulRvalidKnown_A, tlul_rvalid_o) + `CALIPTRA_ASSERT_KNOWN(TlulRdataKnown_A, tlul_rdata_o) + `CALIPTRA_ASSERT_KNOWN(OtpReqKnown_A, otp_req_o) + `CALIPTRA_ASSERT_KNOWN(OtpCmdKnown_A, otp_cmd_o) + `CALIPTRA_ASSERT_KNOWN(OtpSizeKnown_A, otp_size_o) + `CALIPTRA_ASSERT_KNOWN(OtpWdataKnown_A, otp_wdata_o) + `CALIPTRA_ASSERT_KNOWN(OtpAddrKnown_A, otp_addr_o) + + // Uninitialized partitions should always be locked, no matter what. + `CALIPTRA_ASSERT(InitWriteLocksPartition_A, + ~init_done_o + |-> + mubi8_test_true_loose(access_o.write_lock)) + `CALIPTRA_ASSERT(InitReadLocksPartition_A, + ~init_done_o + |-> + mubi8_test_true_loose(access_o.read_lock)) + // Incoming Lock propagation + `CALIPTRA_ASSERT(WriteLockPropagation_A, + mubi8_test_true_loose(access_i.write_lock) + |-> + mubi8_test_true_loose(access_o.write_lock)) + `CALIPTRA_ASSERT(ReadLockPropagation_A, + mubi8_test_true_loose(access_i.read_lock) + |-> + mubi8_test_true_loose(access_o.read_lock)) + // If the partition is read locked, the TL-UL access must error out + `CALIPTRA_ASSERT(TlulReadOnReadLock_A, + tlul_req_i && tlul_gnt_o ##1 mubi8_test_true_loose(access_o.read_lock) + |-> + tlul_rerror_o > '0 && tlul_rvalid_o) + // ECC error in buffer regs. + `CALIPTRA_ASSERT(EccErrorState_A, + ecc_err + |=> + state_q == ErrorSt) + // OTP error response + `CALIPTRA_ASSERT(OtpErrorState_A, + state_q inside {InitWaitSt, ReadWaitSt} && otp_rvalid_i && + !(otp_err inside {NoError, MacroEccCorrError}) && !ecc_err + |=> + state_q == ErrorSt && error_o == $past(otp_err)) + +endmodule : otp_ctrl_part_unbuf diff --git a/src/fuse_ctrl/rtl/otp_ctrl_pkg.sv b/src/fuse_ctrl/rtl/otp_ctrl_pkg.sv new file mode 100644 index 0000000..50c4158 --- /dev/null +++ b/src/fuse_ctrl/rtl/otp_ctrl_pkg.sv @@ -0,0 +1,327 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// + +package otp_ctrl_pkg; + + import caliptra_prim_util_pkg::vbits; + import otp_ctrl_reg_pkg::*; + + //////////////////////// + // General Parameters // + //////////////////////// + + // Number of vendor-specific test CSR bits coming from and going to + // the life cycle TAP registers. + parameter int OtpTestCtrlWidth = 32; + parameter int OtpTestStatusWidth = 32; + parameter int OtpTestVectWidth = 8; + + // Width of entropy input + parameter int EdnDataWidth = 64; + + parameter int NumPartWidth = vbits(NumPart); + + parameter int SwWindowAddrWidth = vbits(NumSwCfgWindowWords); + + // Background check timer LFSR width. + parameter int LfsrWidth = 40; + // The LFSR will be reseeded once LfsrUsageThreshold + // values have been drawn from it. + parameter int LfsrUsageThreshold = 16; + + // Redundantly encoded and complementary values are used to for signalling to the partition + // controller FSMs and the DAI whether a partition is locked or not. Any other value than + // "Mubi8Lo" is interpreted as "Locked" in those FSMs. + typedef struct packed { + caliptra_prim_mubi_pkg::mubi8_t read_lock; + caliptra_prim_mubi_pkg::mubi8_t write_lock; + } part_access_t; + + parameter int DaiCmdWidth = 3; + typedef enum logic [DaiCmdWidth-1:0] { + DaiRead = 3'b001, + DaiWrite = 3'b010, + DaiDigest = 3'b100 + } dai_cmd_e; + + parameter int DeviceIdWidth = 256; + typedef logic [DeviceIdWidth-1:0] otp_device_id_t; + + parameter int ManufStateWidth = 256; + typedef logic [ManufStateWidth-1:0] otp_manuf_state_t; + + ////////////////////////////////////// + // Typedefs for OTP Macro Interface // + ////////////////////////////////////// + + // OTP-macro specific + parameter int OtpWidth = 16; + parameter int OtpAddrWidth = OtpByteAddrWidth - $clog2(OtpWidth/8); + parameter int OtpDepth = 2**OtpAddrWidth; + parameter int OtpSizeWidth = 2; // Allows to transfer up to 4 native OTP words at once. + parameter int OtpErrWidth = 3; + parameter int OtpPwrSeqWidth = 2; + parameter int OtpIfWidth = 2**OtpSizeWidth*OtpWidth; + // Number of Byte address bits to cut off in order to get the native OTP word address. + parameter int OtpAddrShift = OtpByteAddrWidth - OtpAddrWidth; + + typedef enum logic [OtpErrWidth-1:0] { + NoError = 3'h0, + MacroError = 3'h1, + MacroEccCorrError = 3'h2, + MacroEccUncorrError = 3'h3, + MacroWriteBlankError = 3'h4, + AccessError = 3'h5, + CheckFailError = 3'h6, + FsmStateError = 3'h7 + } otp_err_e; + + ///////////////////////////////// + // Typedefs for OTP Scrambling // + ///////////////////////////////// + + parameter int ScrmblKeyWidth = 128; + parameter int ScrmblBlockWidth = 64; + + parameter int NumPresentRounds = 31; + parameter int ScrmblBlockHalfWords = ScrmblBlockWidth / OtpWidth; + + typedef enum logic [2:0] { + Decrypt, + Encrypt, + LoadShadow, + Digest, + DigestInit, + DigestFinalize + } otp_scrmbl_cmd_e; + + /////////////////////////////// + // Typedefs for LC Interface // + /////////////////////////////// + + // The tokens below are all hash post-images + typedef struct packed { + logic valid; + logic error; + // Use caliptra_ss_lc_state_t and caliptra_ss_lc_cnt_t here as very wide enumerations ( > 64 bits ) + // are not supported for virtual interfaces by Excelium yet + // https://github.com/lowRISC/opentitan/issues/8884 (Cadence issue: cds_46570160) + // The enumeration types caliptra_ss_lc_state_e and caliptra_ss_lc_cnt_e are still ok in other circumstances + caliptra_ss_lc_ctrl_state_pkg::caliptra_ss_lc_state_t state; + caliptra_ss_lc_ctrl_state_pkg::caliptra_ss_lc_cnt_t count; + // This is set to "On" if the partition containing the + // root secrets have been locked. In that case, the device + // is considered "personalized". + caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_t secrets_valid; + // This is set to "On" if the partition containing the + // test tokens has been locked. + caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_t test_tokens_valid; + caliptra_ss_lc_ctrl_state_pkg::caliptra_ss_lc_token_t test_unlock_token; + caliptra_ss_lc_ctrl_state_pkg::caliptra_ss_lc_token_t test_exit_token; + // This is set to "On" if the partition containing the + // rma token has been locked. + caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_t rma_token_valid; + caliptra_ss_lc_ctrl_state_pkg::caliptra_ss_lc_token_t rma_token; + } otp_caliptra_ss_lc_data_t; + + // Default for dangling connection. + // Note that we put the life cycle into + // TEST_UNLOCKED0 by default such that top levels without + // the OTP controller can still function. + parameter otp_caliptra_ss_lc_data_t OTP_LC_DATA_DEFAULT = '{ + valid: 1'b1, + error: 1'b0, + state: caliptra_ss_lc_ctrl_state_pkg::LcStTestUnlocked0, + count: caliptra_ss_lc_ctrl_state_pkg::LcCnt1, + secrets_valid: caliptra_ss_lc_ctrl_pkg::Off, + test_tokens_valid: caliptra_ss_lc_ctrl_pkg::Off, + test_unlock_token: '0, + test_exit_token: '0, + rma_token_valid: caliptra_ss_lc_ctrl_pkg::Off, + rma_token: '0 + }; + + typedef struct packed { + logic req; + caliptra_ss_lc_ctrl_state_pkg::caliptra_ss_lc_state_e state; + caliptra_ss_lc_ctrl_state_pkg::caliptra_ss_lc_cnt_e count; + } caliptra_ss_lc_otp_program_req_t; + + typedef struct packed { + logic err; + logic ack; + } caliptra_ss_lc_otp_program_rsp_t; + + // RAW unlock token hashing request. + typedef struct packed { + logic req; + caliptra_ss_lc_ctrl_state_pkg::caliptra_ss_lc_token_t token_input; + } caliptra_ss_lc_otp_token_req_t; + + typedef struct packed { + logic ack; + caliptra_ss_lc_ctrl_state_pkg::caliptra_ss_lc_token_t hashed_token; + } caliptra_ss_lc_otp_token_rsp_t; + + typedef struct packed { + logic [OtpTestCtrlWidth-1:0] ctrl; + } caliptra_ss_lc_otp_vendor_test_req_t; + + typedef struct packed { + logic [OtpTestStatusWidth-1:0] status; + } caliptra_ss_lc_otp_vendor_test_rsp_t; + + //////////////////////////////// + // Typedefs for Key Broadcast // + //////////////////////////////// + + parameter int FlashKeySeedWidth = 256; + parameter int SramKeySeedWidth = 128; + parameter int KeyMgrKeyWidth = 256; + parameter int FlashKeyWidth = 128; + parameter int SramKeyWidth = 128; + parameter int SramNonceWidth = 128; + parameter int OtbnKeyWidth = 128; + parameter int OtbnNonceWidth = 64; + + typedef logic [SramKeyWidth-1:0] sram_key_t; + typedef logic [SramNonceWidth-1:0] sram_nonce_t; + typedef logic [OtbnKeyWidth-1:0] otbn_key_t; + typedef logic [OtbnNonceWidth-1:0] otbn_nonce_t; + + localparam int OtbnNonceSel = OtbnNonceWidth / ScrmblBlockWidth; + localparam int FlashNonceSel = FlashKeyWidth / ScrmblBlockWidth; + localparam int SramNonceSel = SramNonceWidth / ScrmblBlockWidth; + + // Get maximum nonce width + localparam int NumNonceChunks = + (OtbnNonceWidth > FlashKeyWidth) ? + ((OtbnNonceWidth > SramNonceSel) ? OtbnNonceSel : SramNonceSel) : + ((FlashKeyWidth > SramNonceSel) ? FlashNonceSel : SramNonceSel); + + typedef struct packed { + logic [KeyMgrKeyWidth-1:0] creator_root_key_share0; + logic creator_root_key_share0_valid; + logic [KeyMgrKeyWidth-1:0] creator_root_key_share1; + logic creator_root_key_share1_valid; + logic [KeyMgrKeyWidth-1:0] creator_seed; + logic creator_seed_valid; + logic [KeyMgrKeyWidth-1:0] owner_seed; + logic owner_seed_valid; + } otp_keymgr_key_t; + + parameter otp_keymgr_key_t OTP_KEYMGR_KEY_DEFAULT = '{ + creator_root_key_share0: 256'hefb7ea7ee90093cf4affd9aaa2d6c0ec446cfdf5f2d5a0bfd7e2d93edc63a102, + creator_root_key_share0_valid: 1'b1, + creator_root_key_share1: 256'h56d24a00181de99e0f690b447a8dde2a1ffb8bc306707107aa6e2410f15cfc37, + creator_root_key_share1_valid: 1'b1, + creator_seed: 256'hc7c50b38655cc87f821e5b07fed85d2c07e222a9e00bef308b3eccba0ba406fa, + creator_seed_valid: 1'b1, + owner_seed: 256'hf5052c0f14782d8b066be9f49c0b2000d3643ff3723ea7db972f69cd3e2e3e68, + owner_seed_valid: 1'b1 + }; + + typedef struct packed { + logic data_req; // Requests static key for data scrambling. + logic addr_req; // Requests static key for address scrambling. + } flash_otp_key_req_t; + + typedef struct packed { + logic req; // Requests ephemeral scrambling key and nonce. + } sram_otp_key_req_t; + + typedef struct packed { + logic req; // Requests ephemeral scrambling key and nonce. + } otbn_otp_key_req_t; + + typedef struct packed { + logic data_ack; // Ack for data key. + logic addr_ack; // Ack for address key. + logic [FlashKeyWidth-1:0] key; // 128bit static scrambling key. + logic [FlashKeyWidth-1:0] rand_key; + logic seed_valid; // Set to 1 if the key seed has been provisioned and is + // valid. + } flash_otp_key_rsp_t; + + // Default for dangling connection + parameter flash_otp_key_rsp_t FLASH_OTP_KEY_RSP_DEFAULT = '{ + data_ack: 1'b1, + addr_ack: 1'b1, + key: '0, + rand_key: '0, + seed_valid: 1'b1 + }; + + typedef struct packed { + logic ack; // Ack for key. + sram_key_t key; // 128bit ephemeral scrambling key. + sram_nonce_t nonce; // 128bit nonce. + logic seed_valid; // Set to 1 if the key seed has been provisioned and is valid. + } sram_otp_key_rsp_t; + + // Default for dangling connection + parameter sram_otp_key_rsp_t SRAM_OTP_KEY_RSP_DEFAULT = '{ + ack: 1'b1, + key: '0, + nonce: '0, + seed_valid: 1'b1 + }; + + typedef struct packed { + logic ack; // Ack for key. + otbn_key_t key; // 128bit ephemeral scrambling key. + otbn_nonce_t nonce; // 256bit nonce. + logic seed_valid; // Set to 1 if the key seed has been provisioned and is valid. + } otbn_otp_key_rsp_t; + + //////////////////////////////// + // Power/Reset Ctrl Interface // + //////////////////////////////// + + typedef struct packed { + logic init; + } pwr_otp_init_req_t; + + typedef struct packed { + logic done; + } pwr_otp_init_rsp_t; + + typedef struct packed { + logic idle; + } otp_pwr_state_t; + + + /////////////////// + // AST Interface // + /////////////////// + + typedef struct packed { + logic [OtpPwrSeqWidth-1:0] pwr_seq; + } otp_ast_req_t; + + typedef struct packed { + logic [OtpPwrSeqWidth-1:0] pwr_seq_h; + } otp_ast_rsp_t; + + /////////////////////////////////////////// + // Defaults for random netlist constants // + /////////////////////////////////////////// + + // These LFSR parameters have been generated with + // $ util/design/gen-lfsr-seed.py --width 40 --seed 4247488366 + typedef logic [LfsrWidth-1:0] lfsr_seed_t; + typedef logic [LfsrWidth-1:0][$clog2(LfsrWidth)-1:0] lfsr_perm_t; + localparam lfsr_seed_t RndCnstLfsrSeedDefault = 40'h453d28ea98; + localparam lfsr_perm_t RndCnstLfsrPermDefault = + 240'h4235171482c225f79289b32181a0163a760355d3447063d16661e44c12a5; + + typedef struct packed { + sram_key_t key; + sram_nonce_t nonce; + } scrmbl_key_init_t; + localparam scrmbl_key_init_t RndCnstScrmblKeyInitDefault = + 256'hcebeb96ffe0eced795f8b2cfe23c1e519e4fa08047a6bcfb811b04f0a479006e; + +endpackage : otp_ctrl_pkg diff --git a/src/fuse_ctrl/rtl/otp_ctrl_prim_reg_top.sv b/src/fuse_ctrl/rtl/otp_ctrl_prim_reg_top.sv new file mode 100644 index 0000000..6cf2915 --- /dev/null +++ b/src/fuse_ctrl/rtl/otp_ctrl_prim_reg_top.sv @@ -0,0 +1,1467 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Top module auto-generated by `reggen` + +`include "caliptra_prim_assert.sv" + +module otp_ctrl_prim_reg_top ( + input clk_i, + input rst_ni, + input tlul_pkg::tl_h2d_t tl_i, + output tlul_pkg::tl_d2h_t tl_o, + // To HW + output otp_ctrl_reg_pkg::otp_ctrl_prim_reg2hw_t reg2hw, // Write + input otp_ctrl_reg_pkg::otp_ctrl_prim_hw2reg_t hw2reg, // Read + + // Integrity check errors + output logic intg_err_o +); + + import otp_ctrl_reg_pkg::* ; + + localparam int AW = 5; + localparam int DW = 32; + localparam int DBW = DW/8; // Byte Width + + // register signals + logic reg_we; + logic reg_re; + logic [AW-1:0] reg_addr; + logic [DW-1:0] reg_wdata; + logic [DBW-1:0] reg_be; + logic [DW-1:0] reg_rdata; + logic reg_error; + + logic addrmiss, wr_err; + + logic [DW-1:0] reg_rdata_next; + logic reg_busy; + + tlul_pkg::tl_h2d_t tl_reg_h2d; + tlul_pkg::tl_d2h_t tl_reg_d2h; + + + // incoming payload check + logic intg_err; + tlul_cmd_intg_chk u_chk ( + .tl_i(tl_i), + .err_o(intg_err) + ); + + // also check for spurious write enables + logic reg_we_err; + logic [7:0] reg_we_check; + caliptra_prim_reg_we_check #( + .OneHotWidth(8) + ) u_caliptra_prim_reg_we_check ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .oh_i (reg_we_check), + .en_i (reg_we && !addrmiss), + .err_o (reg_we_err) + ); + + logic err_q; + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + err_q <= '0; + end else if (intg_err || reg_we_err) begin + err_q <= 1'b1; + end + end + + // integrity error output is permanent and should be used for alert generation + // register errors are transactional + assign intg_err_o = err_q | intg_err | reg_we_err; + + // outgoing integrity generation + tlul_pkg::tl_d2h_t tl_o_pre; + tlul_rsp_intg_gen #( + .EnableRspIntgGen(1), + .EnableDataIntgGen(1) + ) u_rsp_intg_gen ( + .tl_i(tl_o_pre), + .tl_o(tl_o) + ); + + assign tl_reg_h2d = tl_i; + assign tl_o_pre = tl_reg_d2h; + + tlul_adapter_reg #( + .RegAw(AW), + .RegDw(DW), + .EnableDataIntgGen(0) + ) u_reg_if ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + .tl_i (tl_reg_h2d), + .tl_o (tl_reg_d2h), + + .en_ifetch_i(caliptra_prim_mubi_pkg::MuBi4False), + .intg_error_o(), + + .we_o (reg_we), + .re_o (reg_re), + .addr_o (reg_addr), + .wdata_o (reg_wdata), + .be_o (reg_be), + .busy_i (reg_busy), + .rdata_i (reg_rdata), + .error_i (reg_error) + ); + + // cdc oversampling signals + + assign reg_rdata = reg_rdata_next ; + assign reg_error = addrmiss | wr_err | intg_err; + + // Define SW related signals + // Format: __{wd|we|qs} + // or _{wd|we|qs} if field == 1 or 0 + logic csr0_we; + logic csr0_field0_qs; + logic csr0_field0_wd; + logic csr0_field1_qs; + logic csr0_field1_wd; + logic csr0_field2_qs; + logic csr0_field2_wd; + logic [9:0] csr0_field3_qs; + logic [9:0] csr0_field3_wd; + logic [10:0] csr0_field4_qs; + logic [10:0] csr0_field4_wd; + logic csr1_we; + logic [6:0] csr1_field0_qs; + logic [6:0] csr1_field0_wd; + logic csr1_field1_qs; + logic csr1_field1_wd; + logic [6:0] csr1_field2_qs; + logic [6:0] csr1_field2_wd; + logic csr1_field3_qs; + logic csr1_field3_wd; + logic [15:0] csr1_field4_qs; + logic [15:0] csr1_field4_wd; + logic csr2_we; + logic csr2_qs; + logic csr2_wd; + logic csr3_we; + logic [2:0] csr3_field0_qs; + logic [2:0] csr3_field0_wd; + logic [9:0] csr3_field1_qs; + logic [9:0] csr3_field1_wd; + logic csr3_field2_qs; + logic csr3_field2_wd; + logic csr3_field3_qs; + logic csr3_field4_qs; + logic csr3_field5_qs; + logic csr3_field6_qs; + logic csr3_field7_qs; + logic csr3_field8_qs; + logic csr4_we; + logic [9:0] csr4_field0_qs; + logic [9:0] csr4_field0_wd; + logic csr4_field1_qs; + logic csr4_field1_wd; + logic csr4_field2_qs; + logic csr4_field2_wd; + logic csr4_field3_qs; + logic csr4_field3_wd; + logic csr5_we; + logic [5:0] csr5_field0_qs; + logic [5:0] csr5_field0_wd; + logic [1:0] csr5_field1_qs; + logic [1:0] csr5_field1_wd; + logic csr5_field2_qs; + logic [2:0] csr5_field3_qs; + logic csr5_field4_qs; + logic csr5_field5_qs; + logic [15:0] csr5_field6_qs; + logic [15:0] csr5_field6_wd; + logic csr6_we; + logic [9:0] csr6_field0_qs; + logic [9:0] csr6_field0_wd; + logic csr6_field1_qs; + logic csr6_field1_wd; + logic csr6_field2_qs; + logic csr6_field2_wd; + logic [15:0] csr6_field3_qs; + logic [15:0] csr6_field3_wd; + logic [5:0] csr7_field0_qs; + logic [2:0] csr7_field1_qs; + logic csr7_field2_qs; + logic csr7_field3_qs; + + // Register instances + // R[csr0]: V(False) + // F[field0]: 0:0 + caliptra_prim_subreg #( + .DW (1), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_csr0_field0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (csr0_we), + .wd (csr0_field0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.csr0.field0.q), + .ds (), + + // to register interface (read) + .qs (csr0_field0_qs) + ); + + // F[field1]: 1:1 + caliptra_prim_subreg #( + .DW (1), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_csr0_field1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (csr0_we), + .wd (csr0_field1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.csr0.field1.q), + .ds (), + + // to register interface (read) + .qs (csr0_field1_qs) + ); + + // F[field2]: 2:2 + caliptra_prim_subreg #( + .DW (1), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_csr0_field2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (csr0_we), + .wd (csr0_field2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.csr0.field2.q), + .ds (), + + // to register interface (read) + .qs (csr0_field2_qs) + ); + + // F[field3]: 13:4 + caliptra_prim_subreg #( + .DW (10), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW), + .RESVAL (10'h0), + .Mubi (1'b0) + ) u_csr0_field3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (csr0_we), + .wd (csr0_field3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.csr0.field3.q), + .ds (), + + // to register interface (read) + .qs (csr0_field3_qs) + ); + + // F[field4]: 26:16 + caliptra_prim_subreg #( + .DW (11), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW), + .RESVAL (11'h0), + .Mubi (1'b0) + ) u_csr0_field4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (csr0_we), + .wd (csr0_field4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.csr0.field4.q), + .ds (), + + // to register interface (read) + .qs (csr0_field4_qs) + ); + + + // R[csr1]: V(False) + // F[field0]: 6:0 + caliptra_prim_subreg #( + .DW (7), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW), + .RESVAL (7'h0), + .Mubi (1'b0) + ) u_csr1_field0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (csr1_we), + .wd (csr1_field0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.csr1.field0.q), + .ds (), + + // to register interface (read) + .qs (csr1_field0_qs) + ); + + // F[field1]: 7:7 + caliptra_prim_subreg #( + .DW (1), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_csr1_field1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (csr1_we), + .wd (csr1_field1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.csr1.field1.q), + .ds (), + + // to register interface (read) + .qs (csr1_field1_qs) + ); + + // F[field2]: 14:8 + caliptra_prim_subreg #( + .DW (7), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW), + .RESVAL (7'h0), + .Mubi (1'b0) + ) u_csr1_field2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (csr1_we), + .wd (csr1_field2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.csr1.field2.q), + .ds (), + + // to register interface (read) + .qs (csr1_field2_qs) + ); + + // F[field3]: 15:15 + caliptra_prim_subreg #( + .DW (1), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_csr1_field3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (csr1_we), + .wd (csr1_field3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.csr1.field3.q), + .ds (), + + // to register interface (read) + .qs (csr1_field3_qs) + ); + + // F[field4]: 31:16 + caliptra_prim_subreg #( + .DW (16), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_csr1_field4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (csr1_we), + .wd (csr1_field4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.csr1.field4.q), + .ds (), + + // to register interface (read) + .qs (csr1_field4_qs) + ); + + + // R[csr2]: V(False) + caliptra_prim_subreg #( + .DW (1), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_csr2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (csr2_we), + .wd (csr2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.csr2.q), + .ds (), + + // to register interface (read) + .qs (csr2_qs) + ); + + + // R[csr3]: V(False) + // F[field0]: 2:0 + caliptra_prim_subreg #( + .DW (3), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessW1C), + .RESVAL (3'h0), + .Mubi (1'b0) + ) u_csr3_field0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (csr3_we), + .wd (csr3_field0_wd), + + // from internal hardware + .de (hw2reg.csr3.field0.de), + .d (hw2reg.csr3.field0.d), + + // to internal hardware + .qe (), + .q (reg2hw.csr3.field0.q), + .ds (), + + // to register interface (read) + .qs (csr3_field0_qs) + ); + + // F[field1]: 13:4 + caliptra_prim_subreg #( + .DW (10), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessW1C), + .RESVAL (10'h0), + .Mubi (1'b0) + ) u_csr3_field1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (csr3_we), + .wd (csr3_field1_wd), + + // from internal hardware + .de (hw2reg.csr3.field1.de), + .d (hw2reg.csr3.field1.d), + + // to internal hardware + .qe (), + .q (reg2hw.csr3.field1.q), + .ds (), + + // to register interface (read) + .qs (csr3_field1_qs) + ); + + // F[field2]: 16:16 + caliptra_prim_subreg #( + .DW (1), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_csr3_field2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (csr3_we), + .wd (csr3_field2_wd), + + // from internal hardware + .de (hw2reg.csr3.field2.de), + .d (hw2reg.csr3.field2.d), + + // to internal hardware + .qe (), + .q (reg2hw.csr3.field2.q), + .ds (), + + // to register interface (read) + .qs (csr3_field2_qs) + ); + + // F[field3]: 17:17 + caliptra_prim_subreg #( + .DW (1), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_csr3_field3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.csr3.field3.de), + .d (hw2reg.csr3.field3.d), + + // to internal hardware + .qe (), + .q (reg2hw.csr3.field3.q), + .ds (), + + // to register interface (read) + .qs (csr3_field3_qs) + ); + + // F[field4]: 18:18 + caliptra_prim_subreg #( + .DW (1), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_csr3_field4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.csr3.field4.de), + .d (hw2reg.csr3.field4.d), + + // to internal hardware + .qe (), + .q (reg2hw.csr3.field4.q), + .ds (), + + // to register interface (read) + .qs (csr3_field4_qs) + ); + + // F[field5]: 19:19 + caliptra_prim_subreg #( + .DW (1), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_csr3_field5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.csr3.field5.de), + .d (hw2reg.csr3.field5.d), + + // to internal hardware + .qe (), + .q (reg2hw.csr3.field5.q), + .ds (), + + // to register interface (read) + .qs (csr3_field5_qs) + ); + + // F[field6]: 20:20 + caliptra_prim_subreg #( + .DW (1), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_csr3_field6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.csr3.field6.de), + .d (hw2reg.csr3.field6.d), + + // to internal hardware + .qe (), + .q (reg2hw.csr3.field6.q), + .ds (), + + // to register interface (read) + .qs (csr3_field6_qs) + ); + + // F[field7]: 21:21 + caliptra_prim_subreg #( + .DW (1), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_csr3_field7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.csr3.field7.de), + .d (hw2reg.csr3.field7.d), + + // to internal hardware + .qe (), + .q (reg2hw.csr3.field7.q), + .ds (), + + // to register interface (read) + .qs (csr3_field7_qs) + ); + + // F[field8]: 22:22 + caliptra_prim_subreg #( + .DW (1), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_csr3_field8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.csr3.field8.de), + .d (hw2reg.csr3.field8.d), + + // to internal hardware + .qe (), + .q (reg2hw.csr3.field8.q), + .ds (), + + // to register interface (read) + .qs (csr3_field8_qs) + ); + + + // R[csr4]: V(False) + // F[field0]: 9:0 + caliptra_prim_subreg #( + .DW (10), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW), + .RESVAL (10'h0), + .Mubi (1'b0) + ) u_csr4_field0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (csr4_we), + .wd (csr4_field0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.csr4.field0.q), + .ds (), + + // to register interface (read) + .qs (csr4_field0_qs) + ); + + // F[field1]: 12:12 + caliptra_prim_subreg #( + .DW (1), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_csr4_field1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (csr4_we), + .wd (csr4_field1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.csr4.field1.q), + .ds (), + + // to register interface (read) + .qs (csr4_field1_qs) + ); + + // F[field2]: 13:13 + caliptra_prim_subreg #( + .DW (1), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_csr4_field2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (csr4_we), + .wd (csr4_field2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.csr4.field2.q), + .ds (), + + // to register interface (read) + .qs (csr4_field2_qs) + ); + + // F[field3]: 14:14 + caliptra_prim_subreg #( + .DW (1), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_csr4_field3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (csr4_we), + .wd (csr4_field3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.csr4.field3.q), + .ds (), + + // to register interface (read) + .qs (csr4_field3_qs) + ); + + + // R[csr5]: V(False) + // F[field0]: 5:0 + caliptra_prim_subreg #( + .DW (6), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW), + .RESVAL (6'h0), + .Mubi (1'b0) + ) u_csr5_field0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (csr5_we), + .wd (csr5_field0_wd), + + // from internal hardware + .de (hw2reg.csr5.field0.de), + .d (hw2reg.csr5.field0.d), + + // to internal hardware + .qe (), + .q (reg2hw.csr5.field0.q), + .ds (), + + // to register interface (read) + .qs (csr5_field0_qs) + ); + + // F[field1]: 7:6 + caliptra_prim_subreg #( + .DW (2), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_csr5_field1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (csr5_we), + .wd (csr5_field1_wd), + + // from internal hardware + .de (hw2reg.csr5.field1.de), + .d (hw2reg.csr5.field1.d), + + // to internal hardware + .qe (), + .q (reg2hw.csr5.field1.q), + .ds (), + + // to register interface (read) + .qs (csr5_field1_qs) + ); + + // F[field2]: 8:8 + caliptra_prim_subreg #( + .DW (1), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_csr5_field2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.csr5.field2.de), + .d (hw2reg.csr5.field2.d), + + // to internal hardware + .qe (), + .q (reg2hw.csr5.field2.q), + .ds (), + + // to register interface (read) + .qs (csr5_field2_qs) + ); + + // F[field3]: 11:9 + caliptra_prim_subreg #( + .DW (3), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO), + .RESVAL (3'h0), + .Mubi (1'b0) + ) u_csr5_field3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.csr5.field3.de), + .d (hw2reg.csr5.field3.d), + + // to internal hardware + .qe (), + .q (reg2hw.csr5.field3.q), + .ds (), + + // to register interface (read) + .qs (csr5_field3_qs) + ); + + // F[field4]: 12:12 + caliptra_prim_subreg #( + .DW (1), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_csr5_field4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.csr5.field4.de), + .d (hw2reg.csr5.field4.d), + + // to internal hardware + .qe (), + .q (reg2hw.csr5.field4.q), + .ds (), + + // to register interface (read) + .qs (csr5_field4_qs) + ); + + // F[field5]: 13:13 + caliptra_prim_subreg #( + .DW (1), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_csr5_field5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.csr5.field5.de), + .d (hw2reg.csr5.field5.d), + + // to internal hardware + .qe (), + .q (reg2hw.csr5.field5.q), + .ds (), + + // to register interface (read) + .qs (csr5_field5_qs) + ); + + // F[field6]: 31:16 + caliptra_prim_subreg #( + .DW (16), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_csr5_field6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (csr5_we), + .wd (csr5_field6_wd), + + // from internal hardware + .de (hw2reg.csr5.field6.de), + .d (hw2reg.csr5.field6.d), + + // to internal hardware + .qe (), + .q (reg2hw.csr5.field6.q), + .ds (), + + // to register interface (read) + .qs (csr5_field6_qs) + ); + + + // R[csr6]: V(False) + // F[field0]: 9:0 + caliptra_prim_subreg #( + .DW (10), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW), + .RESVAL (10'h0), + .Mubi (1'b0) + ) u_csr6_field0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (csr6_we), + .wd (csr6_field0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.csr6.field0.q), + .ds (), + + // to register interface (read) + .qs (csr6_field0_qs) + ); + + // F[field1]: 11:11 + caliptra_prim_subreg #( + .DW (1), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_csr6_field1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (csr6_we), + .wd (csr6_field1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.csr6.field1.q), + .ds (), + + // to register interface (read) + .qs (csr6_field1_qs) + ); + + // F[field2]: 12:12 + caliptra_prim_subreg #( + .DW (1), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_csr6_field2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (csr6_we), + .wd (csr6_field2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.csr6.field2.q), + .ds (), + + // to register interface (read) + .qs (csr6_field2_qs) + ); + + // F[field3]: 31:16 + caliptra_prim_subreg #( + .DW (16), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_csr6_field3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (csr6_we), + .wd (csr6_field3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.csr6.field3.q), + .ds (), + + // to register interface (read) + .qs (csr6_field3_qs) + ); + + + // R[csr7]: V(False) + // F[field0]: 5:0 + caliptra_prim_subreg #( + .DW (6), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO), + .RESVAL (6'h0), + .Mubi (1'b0) + ) u_csr7_field0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.csr7.field0.de), + .d (hw2reg.csr7.field0.d), + + // to internal hardware + .qe (), + .q (reg2hw.csr7.field0.q), + .ds (), + + // to register interface (read) + .qs (csr7_field0_qs) + ); + + // F[field1]: 10:8 + caliptra_prim_subreg #( + .DW (3), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO), + .RESVAL (3'h0), + .Mubi (1'b0) + ) u_csr7_field1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.csr7.field1.de), + .d (hw2reg.csr7.field1.d), + + // to internal hardware + .qe (), + .q (reg2hw.csr7.field1.q), + .ds (), + + // to register interface (read) + .qs (csr7_field1_qs) + ); + + // F[field2]: 14:14 + caliptra_prim_subreg #( + .DW (1), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_csr7_field2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.csr7.field2.de), + .d (hw2reg.csr7.field2.d), + + // to internal hardware + .qe (), + .q (reg2hw.csr7.field2.q), + .ds (), + + // to register interface (read) + .qs (csr7_field2_qs) + ); + + // F[field3]: 15:15 + caliptra_prim_subreg #( + .DW (1), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_csr7_field3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.csr7.field3.de), + .d (hw2reg.csr7.field3.d), + + // to internal hardware + .qe (), + .q (reg2hw.csr7.field3.q), + .ds (), + + // to register interface (read) + .qs (csr7_field3_qs) + ); + + + + logic [7:0] addr_hit; + always_comb begin + addr_hit = '0; + addr_hit[0] = (reg_addr == OTP_CTRL_CSR0_OFFSET); + addr_hit[1] = (reg_addr == OTP_CTRL_CSR1_OFFSET); + addr_hit[2] = (reg_addr == OTP_CTRL_CSR2_OFFSET); + addr_hit[3] = (reg_addr == OTP_CTRL_CSR3_OFFSET); + addr_hit[4] = (reg_addr == OTP_CTRL_CSR4_OFFSET); + addr_hit[5] = (reg_addr == OTP_CTRL_CSR5_OFFSET); + addr_hit[6] = (reg_addr == OTP_CTRL_CSR6_OFFSET); + addr_hit[7] = (reg_addr == OTP_CTRL_CSR7_OFFSET); + end + + assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; + + // Check sub-word write is permitted + always_comb begin + wr_err = (reg_we & + ((addr_hit[0] & (|(OTP_CTRL_PRIM_PERMIT[0] & ~reg_be))) | + (addr_hit[1] & (|(OTP_CTRL_PRIM_PERMIT[1] & ~reg_be))) | + (addr_hit[2] & (|(OTP_CTRL_PRIM_PERMIT[2] & ~reg_be))) | + (addr_hit[3] & (|(OTP_CTRL_PRIM_PERMIT[3] & ~reg_be))) | + (addr_hit[4] & (|(OTP_CTRL_PRIM_PERMIT[4] & ~reg_be))) | + (addr_hit[5] & (|(OTP_CTRL_PRIM_PERMIT[5] & ~reg_be))) | + (addr_hit[6] & (|(OTP_CTRL_PRIM_PERMIT[6] & ~reg_be))) | + (addr_hit[7] & (|(OTP_CTRL_PRIM_PERMIT[7] & ~reg_be))))); + end + + // Generate write-enables + assign csr0_we = addr_hit[0] & reg_we & !reg_error; + + assign csr0_field0_wd = reg_wdata[0]; + + assign csr0_field1_wd = reg_wdata[1]; + + assign csr0_field2_wd = reg_wdata[2]; + + assign csr0_field3_wd = reg_wdata[13:4]; + + assign csr0_field4_wd = reg_wdata[26:16]; + assign csr1_we = addr_hit[1] & reg_we & !reg_error; + + assign csr1_field0_wd = reg_wdata[6:0]; + + assign csr1_field1_wd = reg_wdata[7]; + + assign csr1_field2_wd = reg_wdata[14:8]; + + assign csr1_field3_wd = reg_wdata[15]; + + assign csr1_field4_wd = reg_wdata[31:16]; + assign csr2_we = addr_hit[2] & reg_we & !reg_error; + + assign csr2_wd = reg_wdata[0]; + assign csr3_we = addr_hit[3] & reg_we & !reg_error; + + assign csr3_field0_wd = reg_wdata[2:0]; + + assign csr3_field1_wd = reg_wdata[13:4]; + + assign csr3_field2_wd = reg_wdata[16]; + assign csr4_we = addr_hit[4] & reg_we & !reg_error; + + assign csr4_field0_wd = reg_wdata[9:0]; + + assign csr4_field1_wd = reg_wdata[12]; + + assign csr4_field2_wd = reg_wdata[13]; + + assign csr4_field3_wd = reg_wdata[14]; + assign csr5_we = addr_hit[5] & reg_we & !reg_error; + + assign csr5_field0_wd = reg_wdata[5:0]; + + assign csr5_field1_wd = reg_wdata[7:6]; + + assign csr5_field6_wd = reg_wdata[31:16]; + assign csr6_we = addr_hit[6] & reg_we & !reg_error; + + assign csr6_field0_wd = reg_wdata[9:0]; + + assign csr6_field1_wd = reg_wdata[11]; + + assign csr6_field2_wd = reg_wdata[12]; + + assign csr6_field3_wd = reg_wdata[31:16]; + + // Assign write-enables to checker logic vector. + always_comb begin + reg_we_check = '0; + reg_we_check[0] = csr0_we; + reg_we_check[1] = csr1_we; + reg_we_check[2] = csr2_we; + reg_we_check[3] = csr3_we; + reg_we_check[4] = csr4_we; + reg_we_check[5] = csr5_we; + reg_we_check[6] = csr6_we; + reg_we_check[7] = 1'b0; + end + + // Read data return + always_comb begin + reg_rdata_next = '0; + unique case (1'b1) + addr_hit[0]: begin + reg_rdata_next[0] = csr0_field0_qs; + reg_rdata_next[1] = csr0_field1_qs; + reg_rdata_next[2] = csr0_field2_qs; + reg_rdata_next[13:4] = csr0_field3_qs; + reg_rdata_next[26:16] = csr0_field4_qs; + end + + addr_hit[1]: begin + reg_rdata_next[6:0] = csr1_field0_qs; + reg_rdata_next[7] = csr1_field1_qs; + reg_rdata_next[14:8] = csr1_field2_qs; + reg_rdata_next[15] = csr1_field3_qs; + reg_rdata_next[31:16] = csr1_field4_qs; + end + + addr_hit[2]: begin + reg_rdata_next[0] = csr2_qs; + end + + addr_hit[3]: begin + reg_rdata_next[2:0] = csr3_field0_qs; + reg_rdata_next[13:4] = csr3_field1_qs; + reg_rdata_next[16] = csr3_field2_qs; + reg_rdata_next[17] = csr3_field3_qs; + reg_rdata_next[18] = csr3_field4_qs; + reg_rdata_next[19] = csr3_field5_qs; + reg_rdata_next[20] = csr3_field6_qs; + reg_rdata_next[21] = csr3_field7_qs; + reg_rdata_next[22] = csr3_field8_qs; + end + + addr_hit[4]: begin + reg_rdata_next[9:0] = csr4_field0_qs; + reg_rdata_next[12] = csr4_field1_qs; + reg_rdata_next[13] = csr4_field2_qs; + reg_rdata_next[14] = csr4_field3_qs; + end + + addr_hit[5]: begin + reg_rdata_next[5:0] = csr5_field0_qs; + reg_rdata_next[7:6] = csr5_field1_qs; + reg_rdata_next[8] = csr5_field2_qs; + reg_rdata_next[11:9] = csr5_field3_qs; + reg_rdata_next[12] = csr5_field4_qs; + reg_rdata_next[13] = csr5_field5_qs; + reg_rdata_next[31:16] = csr5_field6_qs; + end + + addr_hit[6]: begin + reg_rdata_next[9:0] = csr6_field0_qs; + reg_rdata_next[11] = csr6_field1_qs; + reg_rdata_next[12] = csr6_field2_qs; + reg_rdata_next[31:16] = csr6_field3_qs; + end + + addr_hit[7]: begin + reg_rdata_next[5:0] = csr7_field0_qs; + reg_rdata_next[10:8] = csr7_field1_qs; + reg_rdata_next[14] = csr7_field2_qs; + reg_rdata_next[15] = csr7_field3_qs; + end + + default: begin + reg_rdata_next = '1; + end + endcase + end + + // shadow busy + logic shadow_busy; + assign shadow_busy = 1'b0; + + // register busy + assign reg_busy = shadow_busy; + + // Unused signal tieoff + + // wdata / byte enable are not always fully used + // add a blanket unused statement to handle lint waivers + logic unused_wdata; + logic unused_be; + assign unused_wdata = ^reg_wdata; + assign unused_be = ^reg_be; + + // Assertions for Register Interface + `CALIPTRA_ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni) + `CALIPTRA_ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni) + + `CALIPTRA_ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o_pre.d_valid, clk_i, !rst_ni) + + `CALIPTRA_ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni) + + // this is formulated as an assumption such that the FPV testbenches do disprove this + // property by mistake + //`ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.chk_en == tlul_pkg::CheckDis) + +endmodule diff --git a/src/fuse_ctrl/rtl/otp_ctrl_reg_pkg.sv b/src/fuse_ctrl/rtl/otp_ctrl_reg_pkg.sv new file mode 100644 index 0000000..f03c323 --- /dev/null +++ b/src/fuse_ctrl/rtl/otp_ctrl_reg_pkg.sv @@ -0,0 +1,1161 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Package auto-generated by `reggen` containing data structure + +package otp_ctrl_reg_pkg; + + // Param list + parameter int NumSramKeyReqSlots = 4; + parameter int OtpByteAddrWidth = 11; + parameter int NumErrorEntries = 13; + parameter int NumDaiWords = 2; + parameter int NumDigestWords = 2; + parameter int NumSwCfgWindowWords = 512; + parameter int NumPart = 11; + parameter int NumPartUnbuf = 5; + parameter int NumPartBuf = 6; + parameter int VendorTestOffset = 0; + parameter int VendorTestSize = 64; + parameter int ScratchOffset = 0; + parameter int ScratchSize = 56; + parameter int VendorTestDigestOffset = 56; + parameter int VendorTestDigestSize = 8; + parameter int CreatorSwCfgOffset = 64; + parameter int CreatorSwCfgSize = 368; + parameter int CreatorSwCfgAstCfgOffset = 64; + parameter int CreatorSwCfgAstCfgSize = 156; + parameter int CreatorSwCfgAstInitEnOffset = 220; + parameter int CreatorSwCfgAstInitEnSize = 4; + parameter int CreatorSwCfgRomExtSkuOffset = 224; + parameter int CreatorSwCfgRomExtSkuSize = 4; + parameter int CreatorSwCfgSigverifySpxEnOffset = 228; + parameter int CreatorSwCfgSigverifySpxEnSize = 4; + parameter int CreatorSwCfgFlashDataDefaultCfgOffset = 232; + parameter int CreatorSwCfgFlashDataDefaultCfgSize = 4; + parameter int CreatorSwCfgFlashInfoBootDataCfgOffset = 236; + parameter int CreatorSwCfgFlashInfoBootDataCfgSize = 4; + parameter int CreatorSwCfgFlashHwInfoCfgOverrideOffset = 240; + parameter int CreatorSwCfgFlashHwInfoCfgOverrideSize = 4; + parameter int CreatorSwCfgRngEnOffset = 244; + parameter int CreatorSwCfgRngEnSize = 4; + parameter int CreatorSwCfgJitterEnOffset = 248; + parameter int CreatorSwCfgJitterEnSize = 4; + parameter int CreatorSwCfgRetRamResetMaskOffset = 252; + parameter int CreatorSwCfgRetRamResetMaskSize = 4; + parameter int CreatorSwCfgManufStateOffset = 256; + parameter int CreatorSwCfgManufStateSize = 4; + parameter int CreatorSwCfgRomExecEnOffset = 260; + parameter int CreatorSwCfgRomExecEnSize = 4; + parameter int CreatorSwCfgCpuctrlOffset = 264; + parameter int CreatorSwCfgCpuctrlSize = 4; + parameter int CreatorSwCfgMinSecVerRomExtOffset = 268; + parameter int CreatorSwCfgMinSecVerRomExtSize = 4; + parameter int CreatorSwCfgMinSecVerBl0Offset = 272; + parameter int CreatorSwCfgMinSecVerBl0Size = 4; + parameter int CreatorSwCfgDefaultBootDataInProdEnOffset = 276; + parameter int CreatorSwCfgDefaultBootDataInProdEnSize = 4; + parameter int CreatorSwCfgRmaSpinEnOffset = 280; + parameter int CreatorSwCfgRmaSpinEnSize = 4; + parameter int CreatorSwCfgRmaSpinCyclesOffset = 284; + parameter int CreatorSwCfgRmaSpinCyclesSize = 4; + parameter int CreatorSwCfgRngRepcntThresholdsOffset = 288; + parameter int CreatorSwCfgRngRepcntThresholdsSize = 4; + parameter int CreatorSwCfgRngRepcntsThresholdsOffset = 292; + parameter int CreatorSwCfgRngRepcntsThresholdsSize = 4; + parameter int CreatorSwCfgRngAdaptpHiThresholdsOffset = 296; + parameter int CreatorSwCfgRngAdaptpHiThresholdsSize = 4; + parameter int CreatorSwCfgRngAdaptpLoThresholdsOffset = 300; + parameter int CreatorSwCfgRngAdaptpLoThresholdsSize = 4; + parameter int CreatorSwCfgRngBucketThresholdsOffset = 304; + parameter int CreatorSwCfgRngBucketThresholdsSize = 4; + parameter int CreatorSwCfgRngMarkovHiThresholdsOffset = 308; + parameter int CreatorSwCfgRngMarkovHiThresholdsSize = 4; + parameter int CreatorSwCfgRngMarkovLoThresholdsOffset = 312; + parameter int CreatorSwCfgRngMarkovLoThresholdsSize = 4; + parameter int CreatorSwCfgRngExthtHiThresholdsOffset = 316; + parameter int CreatorSwCfgRngExthtHiThresholdsSize = 4; + parameter int CreatorSwCfgRngExthtLoThresholdsOffset = 320; + parameter int CreatorSwCfgRngExthtLoThresholdsSize = 4; + parameter int CreatorSwCfgRngAlertThresholdOffset = 324; + parameter int CreatorSwCfgRngAlertThresholdSize = 4; + parameter int CreatorSwCfgRngHealthConfigDigestOffset = 328; + parameter int CreatorSwCfgRngHealthConfigDigestSize = 4; + parameter int CreatorSwCfgSramKeyRenewEnOffset = 332; + parameter int CreatorSwCfgSramKeyRenewEnSize = 4; + parameter int CreatorSwCfgImmutableRomExtEnOffset = 336; + parameter int CreatorSwCfgImmutableRomExtEnSize = 4; + parameter int CreatorSwCfgImmutableRomExtStartOffsetOffset = 340; + parameter int CreatorSwCfgImmutableRomExtStartOffsetSize = 4; + parameter int CreatorSwCfgImmutableRomExtLengthOffset = 344; + parameter int CreatorSwCfgImmutableRomExtLengthSize = 4; + parameter int CreatorSwCfgImmutableRomExtSha256HashOffset = 348; + parameter int CreatorSwCfgImmutableRomExtSha256HashSize = 32; + parameter int CreatorSwCfgReservedOffset = 380; + parameter int CreatorSwCfgReservedSize = 32; + parameter int CreatorSwCfgDigestOffset = 424; + parameter int CreatorSwCfgDigestSize = 8; + parameter int OwnerSwCfgOffset = 432; + parameter int OwnerSwCfgSize = 712; + parameter int OwnerSwCfgRomErrorReportingOffset = 432; + parameter int OwnerSwCfgRomErrorReportingSize = 4; + parameter int OwnerSwCfgRomBootstrapDisOffset = 436; + parameter int OwnerSwCfgRomBootstrapDisSize = 4; + parameter int OwnerSwCfgRomAlertClassEnOffset = 440; + parameter int OwnerSwCfgRomAlertClassEnSize = 4; + parameter int OwnerSwCfgRomAlertEscalationOffset = 444; + parameter int OwnerSwCfgRomAlertEscalationSize = 4; + parameter int OwnerSwCfgRomAlertClassificationOffset = 448; + parameter int OwnerSwCfgRomAlertClassificationSize = 320; + parameter int OwnerSwCfgRomLocalAlertClassificationOffset = 768; + parameter int OwnerSwCfgRomLocalAlertClassificationSize = 64; + parameter int OwnerSwCfgRomAlertAccumThreshOffset = 832; + parameter int OwnerSwCfgRomAlertAccumThreshSize = 16; + parameter int OwnerSwCfgRomAlertTimeoutCyclesOffset = 848; + parameter int OwnerSwCfgRomAlertTimeoutCyclesSize = 16; + parameter int OwnerSwCfgRomAlertPhaseCyclesOffset = 864; + parameter int OwnerSwCfgRomAlertPhaseCyclesSize = 64; + parameter int OwnerSwCfgRomAlertDigestProdOffset = 928; + parameter int OwnerSwCfgRomAlertDigestProdSize = 4; + parameter int OwnerSwCfgRomAlertDigestProdEndOffset = 932; + parameter int OwnerSwCfgRomAlertDigestProdEndSize = 4; + parameter int OwnerSwCfgRomAlertDigestDevOffset = 936; + parameter int OwnerSwCfgRomAlertDigestDevSize = 4; + parameter int OwnerSwCfgRomAlertDigestRmaOffset = 940; + parameter int OwnerSwCfgRomAlertDigestRmaSize = 4; + parameter int OwnerSwCfgRomWatchdogBiteThresholdCyclesOffset = 944; + parameter int OwnerSwCfgRomWatchdogBiteThresholdCyclesSize = 4; + parameter int OwnerSwCfgRomKeymgrOtpMeasEnOffset = 948; + parameter int OwnerSwCfgRomKeymgrOtpMeasEnSize = 4; + parameter int OwnerSwCfgManufStateOffset = 952; + parameter int OwnerSwCfgManufStateSize = 4; + parameter int OwnerSwCfgRomRstmgrInfoEnOffset = 956; + parameter int OwnerSwCfgRomRstmgrInfoEnSize = 4; + parameter int OwnerSwCfgRomExtBootstrapEnOffset = 960; + parameter int OwnerSwCfgRomExtBootstrapEnSize = 4; + parameter int OwnerSwCfgRomSensorCtrlAlertCfgOffset = 964; + parameter int OwnerSwCfgRomSensorCtrlAlertCfgSize = 12; + parameter int OwnerSwCfgRomSramReadbackEnOffset = 976; + parameter int OwnerSwCfgRomSramReadbackEnSize = 4; + parameter int OwnerSwCfgRomPreserveResetReasonEnOffset = 980; + parameter int OwnerSwCfgRomPreserveResetReasonEnSize = 4; + parameter int OwnerSwCfgRomResetReasonCheckValueOffset = 984; + parameter int OwnerSwCfgRomResetReasonCheckValueSize = 4; + parameter int OwnerSwCfgRomBannerEnOffset = 988; + parameter int OwnerSwCfgRomBannerEnSize = 4; + parameter int OwnerSwCfgRomFlashEccExcHandlerEnOffset = 992; + parameter int OwnerSwCfgRomFlashEccExcHandlerEnSize = 4; + parameter int OwnerSwCfgReservedOffset = 996; + parameter int OwnerSwCfgReservedSize = 128; + parameter int OwnerSwCfgDigestOffset = 1136; + parameter int OwnerSwCfgDigestSize = 8; + parameter int RotCreatorAuthCodesignOffset = 1144; + parameter int RotCreatorAuthCodesignSize = 472; + parameter int RotCreatorAuthCodesignEcdsaKeyType0Offset = 1144; + parameter int RotCreatorAuthCodesignEcdsaKeyType0Size = 4; + parameter int RotCreatorAuthCodesignEcdsaKey0Offset = 1148; + parameter int RotCreatorAuthCodesignEcdsaKey0Size = 64; + parameter int RotCreatorAuthCodesignEcdsaKeyType1Offset = 1212; + parameter int RotCreatorAuthCodesignEcdsaKeyType1Size = 4; + parameter int RotCreatorAuthCodesignEcdsaKey1Offset = 1216; + parameter int RotCreatorAuthCodesignEcdsaKey1Size = 64; + parameter int RotCreatorAuthCodesignEcdsaKeyType2Offset = 1280; + parameter int RotCreatorAuthCodesignEcdsaKeyType2Size = 4; + parameter int RotCreatorAuthCodesignEcdsaKey2Offset = 1284; + parameter int RotCreatorAuthCodesignEcdsaKey2Size = 64; + parameter int RotCreatorAuthCodesignEcdsaKeyType3Offset = 1348; + parameter int RotCreatorAuthCodesignEcdsaKeyType3Size = 4; + parameter int RotCreatorAuthCodesignEcdsaKey3Offset = 1352; + parameter int RotCreatorAuthCodesignEcdsaKey3Size = 64; + parameter int RotCreatorAuthCodesignSpxKeyType0Offset = 1416; + parameter int RotCreatorAuthCodesignSpxKeyType0Size = 4; + parameter int RotCreatorAuthCodesignSpxKey0Offset = 1420; + parameter int RotCreatorAuthCodesignSpxKey0Size = 32; + parameter int RotCreatorAuthCodesignSpxKeyConfig0Offset = 1452; + parameter int RotCreatorAuthCodesignSpxKeyConfig0Size = 4; + parameter int RotCreatorAuthCodesignSpxKeyType1Offset = 1456; + parameter int RotCreatorAuthCodesignSpxKeyType1Size = 4; + parameter int RotCreatorAuthCodesignSpxKey1Offset = 1460; + parameter int RotCreatorAuthCodesignSpxKey1Size = 32; + parameter int RotCreatorAuthCodesignSpxKeyConfig1Offset = 1492; + parameter int RotCreatorAuthCodesignSpxKeyConfig1Size = 4; + parameter int RotCreatorAuthCodesignSpxKeyType2Offset = 1496; + parameter int RotCreatorAuthCodesignSpxKeyType2Size = 4; + parameter int RotCreatorAuthCodesignSpxKey2Offset = 1500; + parameter int RotCreatorAuthCodesignSpxKey2Size = 32; + parameter int RotCreatorAuthCodesignSpxKeyConfig2Offset = 1532; + parameter int RotCreatorAuthCodesignSpxKeyConfig2Size = 4; + parameter int RotCreatorAuthCodesignSpxKeyType3Offset = 1536; + parameter int RotCreatorAuthCodesignSpxKeyType3Size = 4; + parameter int RotCreatorAuthCodesignSpxKey3Offset = 1540; + parameter int RotCreatorAuthCodesignSpxKey3Size = 32; + parameter int RotCreatorAuthCodesignSpxKeyConfig3Offset = 1572; + parameter int RotCreatorAuthCodesignSpxKeyConfig3Size = 4; + parameter int RotCreatorAuthCodesignBlockSha2_256HashOffset = 1576; + parameter int RotCreatorAuthCodesignBlockSha2_256HashSize = 32; + parameter int RotCreatorAuthCodesignDigestOffset = 1608; + parameter int RotCreatorAuthCodesignDigestSize = 8; + parameter int RotCreatorAuthStateOffset = 1616; + parameter int RotCreatorAuthStateSize = 40; + parameter int RotCreatorAuthStateEcdsaKey0Offset = 1616; + parameter int RotCreatorAuthStateEcdsaKey0Size = 4; + parameter int RotCreatorAuthStateEcdsaKey1Offset = 1620; + parameter int RotCreatorAuthStateEcdsaKey1Size = 4; + parameter int RotCreatorAuthStateEcdsaKey2Offset = 1624; + parameter int RotCreatorAuthStateEcdsaKey2Size = 4; + parameter int RotCreatorAuthStateEcdsaKey3Offset = 1628; + parameter int RotCreatorAuthStateEcdsaKey3Size = 4; + parameter int RotCreatorAuthStateSpxKey0Offset = 1632; + parameter int RotCreatorAuthStateSpxKey0Size = 4; + parameter int RotCreatorAuthStateSpxKey1Offset = 1636; + parameter int RotCreatorAuthStateSpxKey1Size = 4; + parameter int RotCreatorAuthStateSpxKey2Offset = 1640; + parameter int RotCreatorAuthStateSpxKey2Size = 4; + parameter int RotCreatorAuthStateSpxKey3Offset = 1644; + parameter int RotCreatorAuthStateSpxKey3Size = 4; + parameter int RotCreatorAuthStateDigestOffset = 1648; + parameter int RotCreatorAuthStateDigestSize = 8; + parameter int HwCfg0Offset = 1656; + parameter int HwCfg0Size = 72; + parameter int DeviceIdOffset = 1656; + parameter int DeviceIdSize = 32; + parameter int ManufStateOffset = 1688; + parameter int ManufStateSize = 32; + parameter int HwCfg0DigestOffset = 1720; + parameter int HwCfg0DigestSize = 8; + parameter int HwCfg1Offset = 1728; + parameter int HwCfg1Size = 16; + parameter int EnSramIfetchOffset = 1728; + parameter int EnSramIfetchSize = 1; + parameter int EnCsrngSwAppReadOffset = 1729; + parameter int EnCsrngSwAppReadSize = 1; + parameter int DisRvDmLateDebugOffset = 1730; + parameter int DisRvDmLateDebugSize = 1; + parameter int HwCfg1DigestOffset = 1736; + parameter int HwCfg1DigestSize = 8; + parameter int Secret0Offset = 1744; + parameter int Secret0Size = 40; + parameter int TestUnlockTokenOffset = 1744; + parameter int TestUnlockTokenSize = 16; + parameter int TestExitTokenOffset = 1760; + parameter int TestExitTokenSize = 16; + parameter int Secret0DigestOffset = 1776; + parameter int Secret0DigestSize = 8; + parameter int Secret1Offset = 1784; + parameter int Secret1Size = 88; + parameter int FlashAddrKeySeedOffset = 1784; + parameter int FlashAddrKeySeedSize = 32; + parameter int FlashDataKeySeedOffset = 1816; + parameter int FlashDataKeySeedSize = 32; + parameter int SramDataKeySeedOffset = 1848; + parameter int SramDataKeySeedSize = 16; + parameter int Secret1DigestOffset = 1864; + parameter int Secret1DigestSize = 8; + parameter int Secret2Offset = 1872; + parameter int Secret2Size = 88; + parameter int RmaTokenOffset = 1872; + parameter int RmaTokenSize = 16; + parameter int CreatorRootKeyShare0Offset = 1888; + parameter int CreatorRootKeyShare0Size = 32; + parameter int CreatorRootKeyShare1Offset = 1920; + parameter int CreatorRootKeyShare1Size = 32; + parameter int Secret2DigestOffset = 1952; + parameter int Secret2DigestSize = 8; + parameter int LifeCycleOffset = 1960; + parameter int LifeCycleSize = 88; + parameter int LcTransitionCntOffset = 1960; + parameter int LcTransitionCntSize = 48; + parameter int LcStateOffset = 2008; + parameter int LcStateSize = 40; + parameter int NumAlerts = 5; + + // Address widths within the block + parameter int CoreAw = 12; + parameter int PrimAw = 5; + + /////////////////////////////////////////////// + // Typedefs for registers for core interface // + /////////////////////////////////////////////// + + typedef struct packed { + struct packed { + logic q; + } otp_error; + struct packed { + logic q; + } otp_operation_done; + } otp_ctrl_reg2hw_intr_state_reg_t; + + typedef struct packed { + struct packed { + logic q; + } otp_error; + struct packed { + logic q; + } otp_operation_done; + } otp_ctrl_reg2hw_intr_enable_reg_t; + + typedef struct packed { + struct packed { + logic q; + logic qe; + } otp_error; + struct packed { + logic q; + logic qe; + } otp_operation_done; + } otp_ctrl_reg2hw_intr_test_reg_t; + + typedef struct packed { + struct packed { + logic q; + logic qe; + } recov_prim_otp_alert; + struct packed { + logic q; + logic qe; + } fatal_prim_otp_alert; + struct packed { + logic q; + logic qe; + } fatal_bus_integ_error; + struct packed { + logic q; + logic qe; + } fatal_check_error; + struct packed { + logic q; + logic qe; + } fatal_macro_error; + } otp_ctrl_reg2hw_alert_test_reg_t; + + typedef struct packed { + logic q; + logic qe; + } otp_ctrl_reg2hw_direct_access_regwen_reg_t; + + typedef struct packed { + struct packed { + logic q; + logic qe; + } digest; + struct packed { + logic q; + logic qe; + } wr; + struct packed { + logic q; + logic qe; + } rd; + } otp_ctrl_reg2hw_direct_access_cmd_reg_t; + + typedef struct packed { + logic [10:0] q; + } otp_ctrl_reg2hw_direct_access_address_reg_t; + + typedef struct packed { + logic [31:0] q; + } otp_ctrl_reg2hw_direct_access_wdata_mreg_t; + + typedef struct packed { + struct packed { + logic q; + logic qe; + } consistency; + struct packed { + logic q; + logic qe; + } integrity; + } otp_ctrl_reg2hw_check_trigger_reg_t; + + typedef struct packed { + logic [31:0] q; + } otp_ctrl_reg2hw_check_timeout_reg_t; + + typedef struct packed { + logic [31:0] q; + } otp_ctrl_reg2hw_integrity_check_period_reg_t; + + typedef struct packed { + logic [31:0] q; + } otp_ctrl_reg2hw_consistency_check_period_reg_t; + + typedef struct packed { + logic q; + } otp_ctrl_reg2hw_vendor_test_read_lock_reg_t; + + typedef struct packed { + logic q; + } otp_ctrl_reg2hw_creator_sw_cfg_read_lock_reg_t; + + typedef struct packed { + logic q; + } otp_ctrl_reg2hw_owner_sw_cfg_read_lock_reg_t; + + typedef struct packed { + logic q; + } otp_ctrl_reg2hw_rot_creator_auth_codesign_read_lock_reg_t; + + typedef struct packed { + logic q; + } otp_ctrl_reg2hw_rot_creator_auth_state_read_lock_reg_t; + + typedef struct packed { + struct packed { + logic d; + logic de; + } otp_operation_done; + struct packed { + logic d; + logic de; + } otp_error; + } otp_ctrl_hw2reg_intr_state_reg_t; + + typedef struct packed { + struct packed { + logic d; + } vendor_test_error; + struct packed { + logic d; + } creator_sw_cfg_error; + struct packed { + logic d; + } owner_sw_cfg_error; + struct packed { + logic d; + } rot_creator_auth_codesign_error; + struct packed { + logic d; + } rot_creator_auth_state_error; + struct packed { + logic d; + } hw_cfg0_error; + struct packed { + logic d; + } hw_cfg1_error; + struct packed { + logic d; + } secret0_error; + struct packed { + logic d; + } secret1_error; + struct packed { + logic d; + } secret2_error; + struct packed { + logic d; + } life_cycle_error; + struct packed { + logic d; + } dai_error; + struct packed { + logic d; + } lci_error; + struct packed { + logic d; + } timeout_error; + struct packed { + logic d; + } lfsr_fsm_error; + struct packed { + logic d; + } scrambling_fsm_error; + struct packed { + logic d; + } key_deriv_fsm_error; + struct packed { + logic d; + } bus_integ_error; + struct packed { + logic d; + } dai_idle; + struct packed { + logic d; + } check_pending; + } otp_ctrl_hw2reg_status_reg_t; + + typedef struct packed { + logic [2:0] d; + } otp_ctrl_hw2reg_err_code_mreg_t; + + typedef struct packed { + logic d; + } otp_ctrl_hw2reg_direct_access_regwen_reg_t; + + typedef struct packed { + logic [31:0] d; + } otp_ctrl_hw2reg_direct_access_rdata_mreg_t; + + typedef struct packed { + logic [31:0] d; + } otp_ctrl_hw2reg_vendor_test_digest_mreg_t; + + typedef struct packed { + logic [31:0] d; + } otp_ctrl_hw2reg_creator_sw_cfg_digest_mreg_t; + + typedef struct packed { + logic [31:0] d; + } otp_ctrl_hw2reg_owner_sw_cfg_digest_mreg_t; + + typedef struct packed { + logic [31:0] d; + } otp_ctrl_hw2reg_rot_creator_auth_codesign_digest_mreg_t; + + typedef struct packed { + logic [31:0] d; + } otp_ctrl_hw2reg_rot_creator_auth_state_digest_mreg_t; + + typedef struct packed { + logic [31:0] d; + } otp_ctrl_hw2reg_hw_cfg0_digest_mreg_t; + + typedef struct packed { + logic [31:0] d; + } otp_ctrl_hw2reg_hw_cfg1_digest_mreg_t; + + typedef struct packed { + logic [31:0] d; + } otp_ctrl_hw2reg_secret0_digest_mreg_t; + + typedef struct packed { + logic [31:0] d; + } otp_ctrl_hw2reg_secret1_digest_mreg_t; + + typedef struct packed { + logic [31:0] d; + } otp_ctrl_hw2reg_secret2_digest_mreg_t; + + // Register -> HW type for core interface + typedef struct packed { + otp_ctrl_reg2hw_intr_state_reg_t intr_state; // [205:204] + otp_ctrl_reg2hw_intr_enable_reg_t intr_enable; // [203:202] + otp_ctrl_reg2hw_intr_test_reg_t intr_test; // [201:198] + otp_ctrl_reg2hw_alert_test_reg_t alert_test; // [197:188] + otp_ctrl_reg2hw_direct_access_regwen_reg_t direct_access_regwen; // [187:186] + otp_ctrl_reg2hw_direct_access_cmd_reg_t direct_access_cmd; // [185:180] + otp_ctrl_reg2hw_direct_access_address_reg_t direct_access_address; // [179:169] + otp_ctrl_reg2hw_direct_access_wdata_mreg_t [1:0] direct_access_wdata; // [168:105] + otp_ctrl_reg2hw_check_trigger_reg_t check_trigger; // [104:101] + otp_ctrl_reg2hw_check_timeout_reg_t check_timeout; // [100:69] + otp_ctrl_reg2hw_integrity_check_period_reg_t integrity_check_period; // [68:37] + otp_ctrl_reg2hw_consistency_check_period_reg_t consistency_check_period; // [36:5] + otp_ctrl_reg2hw_vendor_test_read_lock_reg_t vendor_test_read_lock; // [4:4] + otp_ctrl_reg2hw_creator_sw_cfg_read_lock_reg_t creator_sw_cfg_read_lock; // [3:3] + otp_ctrl_reg2hw_owner_sw_cfg_read_lock_reg_t owner_sw_cfg_read_lock; // [2:2] + otp_ctrl_reg2hw_rot_creator_auth_codesign_read_lock_reg_t + rot_creator_auth_codesign_read_lock; // [1:1] + otp_ctrl_reg2hw_rot_creator_auth_state_read_lock_reg_t + rot_creator_auth_state_read_lock; // [0:0] + } otp_ctrl_core_reg2hw_t; + + // HW -> register type for core interface + typedef struct packed { + otp_ctrl_hw2reg_intr_state_reg_t intr_state; // [767:764] + otp_ctrl_hw2reg_status_reg_t status; // [763:744] + otp_ctrl_hw2reg_err_code_mreg_t [12:0] err_code; // [743:705] + otp_ctrl_hw2reg_direct_access_regwen_reg_t direct_access_regwen; // [704:704] + otp_ctrl_hw2reg_direct_access_rdata_mreg_t [1:0] direct_access_rdata; // [703:640] + otp_ctrl_hw2reg_vendor_test_digest_mreg_t [1:0] vendor_test_digest; // [639:576] + otp_ctrl_hw2reg_creator_sw_cfg_digest_mreg_t [1:0] creator_sw_cfg_digest; // [575:512] + otp_ctrl_hw2reg_owner_sw_cfg_digest_mreg_t [1:0] owner_sw_cfg_digest; // [511:448] + otp_ctrl_hw2reg_rot_creator_auth_codesign_digest_mreg_t [1:0] + rot_creator_auth_codesign_digest; // [447:384] + otp_ctrl_hw2reg_rot_creator_auth_state_digest_mreg_t [1:0] + rot_creator_auth_state_digest; // [383:320] + otp_ctrl_hw2reg_hw_cfg0_digest_mreg_t [1:0] hw_cfg0_digest; // [319:256] + otp_ctrl_hw2reg_hw_cfg1_digest_mreg_t [1:0] hw_cfg1_digest; // [255:192] + otp_ctrl_hw2reg_secret0_digest_mreg_t [1:0] secret0_digest; // [191:128] + otp_ctrl_hw2reg_secret1_digest_mreg_t [1:0] secret1_digest; // [127:64] + otp_ctrl_hw2reg_secret2_digest_mreg_t [1:0] secret2_digest; // [63:0] + } otp_ctrl_core_hw2reg_t; + + // Register offsets for core interface + parameter logic [CoreAw-1:0] OTP_CTRL_INTR_STATE_OFFSET = 12'h 0; + parameter logic [CoreAw-1:0] OTP_CTRL_INTR_ENABLE_OFFSET = 12'h 4; + parameter logic [CoreAw-1:0] OTP_CTRL_INTR_TEST_OFFSET = 12'h 8; + parameter logic [CoreAw-1:0] OTP_CTRL_ALERT_TEST_OFFSET = 12'h c; + parameter logic [CoreAw-1:0] OTP_CTRL_STATUS_OFFSET = 12'h 10; + parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_0_OFFSET = 12'h 14; + parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_1_OFFSET = 12'h 18; + parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_2_OFFSET = 12'h 1c; + parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_3_OFFSET = 12'h 20; + parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_4_OFFSET = 12'h 24; + parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_5_OFFSET = 12'h 28; + parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_6_OFFSET = 12'h 2c; + parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_7_OFFSET = 12'h 30; + parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_8_OFFSET = 12'h 34; + parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_9_OFFSET = 12'h 38; + parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_10_OFFSET = 12'h 3c; + parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_11_OFFSET = 12'h 40; + parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_12_OFFSET = 12'h 44; + parameter logic [CoreAw-1:0] OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET = 12'h 48; + parameter logic [CoreAw-1:0] OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET = 12'h 4c; + parameter logic [CoreAw-1:0] OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET = 12'h 50; + parameter logic [CoreAw-1:0] OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET = 12'h 54; + parameter logic [CoreAw-1:0] OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET = 12'h 58; + parameter logic [CoreAw-1:0] OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET = 12'h 5c; + parameter logic [CoreAw-1:0] OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET = 12'h 60; + parameter logic [CoreAw-1:0] OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET = 12'h 64; + parameter logic [CoreAw-1:0] OTP_CTRL_CHECK_TRIGGER_OFFSET = 12'h 68; + parameter logic [CoreAw-1:0] OTP_CTRL_CHECK_REGWEN_OFFSET = 12'h 6c; + parameter logic [CoreAw-1:0] OTP_CTRL_CHECK_TIMEOUT_OFFSET = 12'h 70; + parameter logic [CoreAw-1:0] OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET = 12'h 74; + parameter logic [CoreAw-1:0] OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET = 12'h 78; + parameter logic [CoreAw-1:0] OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET = 12'h 7c; + parameter logic [CoreAw-1:0] OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET = 12'h 80; + parameter logic [CoreAw-1:0] OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET = 12'h 84; + parameter logic [CoreAw-1:0] OTP_CTRL_ROT_CREATOR_AUTH_CODESIGN_READ_LOCK_OFFSET = 12'h 88; + parameter logic [CoreAw-1:0] OTP_CTRL_ROT_CREATOR_AUTH_STATE_READ_LOCK_OFFSET = 12'h 8c; + parameter logic [CoreAw-1:0] OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET = 12'h 90; + parameter logic [CoreAw-1:0] OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET = 12'h 94; + parameter logic [CoreAw-1:0] OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET = 12'h 98; + parameter logic [CoreAw-1:0] OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET = 12'h 9c; + parameter logic [CoreAw-1:0] OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET = 12'h a0; + parameter logic [CoreAw-1:0] OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET = 12'h a4; + parameter logic [CoreAw-1:0] OTP_CTRL_ROT_CREATOR_AUTH_CODESIGN_DIGEST_0_OFFSET = 12'h a8; + parameter logic [CoreAw-1:0] OTP_CTRL_ROT_CREATOR_AUTH_CODESIGN_DIGEST_1_OFFSET = 12'h ac; + parameter logic [CoreAw-1:0] OTP_CTRL_ROT_CREATOR_AUTH_STATE_DIGEST_0_OFFSET = 12'h b0; + parameter logic [CoreAw-1:0] OTP_CTRL_ROT_CREATOR_AUTH_STATE_DIGEST_1_OFFSET = 12'h b4; + parameter logic [CoreAw-1:0] OTP_CTRL_HW_CFG0_DIGEST_0_OFFSET = 12'h b8; + parameter logic [CoreAw-1:0] OTP_CTRL_HW_CFG0_DIGEST_1_OFFSET = 12'h bc; + parameter logic [CoreAw-1:0] OTP_CTRL_HW_CFG1_DIGEST_0_OFFSET = 12'h c0; + parameter logic [CoreAw-1:0] OTP_CTRL_HW_CFG1_DIGEST_1_OFFSET = 12'h c4; + parameter logic [CoreAw-1:0] OTP_CTRL_SECRET0_DIGEST_0_OFFSET = 12'h c8; + parameter logic [CoreAw-1:0] OTP_CTRL_SECRET0_DIGEST_1_OFFSET = 12'h cc; + parameter logic [CoreAw-1:0] OTP_CTRL_SECRET1_DIGEST_0_OFFSET = 12'h d0; + parameter logic [CoreAw-1:0] OTP_CTRL_SECRET1_DIGEST_1_OFFSET = 12'h d4; + parameter logic [CoreAw-1:0] OTP_CTRL_SECRET2_DIGEST_0_OFFSET = 12'h d8; + parameter logic [CoreAw-1:0] OTP_CTRL_SECRET2_DIGEST_1_OFFSET = 12'h dc; + + // Reset values for hwext registers and their fields for core interface + parameter logic [1:0] OTP_CTRL_INTR_TEST_RESVAL = 2'h 0; + parameter logic [0:0] OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL = 1'h 0; + parameter logic [0:0] OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL = 1'h 0; + parameter logic [4:0] OTP_CTRL_ALERT_TEST_RESVAL = 5'h 0; + parameter logic [0:0] OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL = 1'h 0; + parameter logic [0:0] OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL = 1'h 0; + parameter logic [0:0] OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL = 1'h 0; + parameter logic [0:0] OTP_CTRL_ALERT_TEST_FATAL_PRIM_OTP_ALERT_RESVAL = 1'h 0; + parameter logic [0:0] OTP_CTRL_ALERT_TEST_RECOV_PRIM_OTP_ALERT_RESVAL = 1'h 0; + parameter logic [19:0] OTP_CTRL_STATUS_RESVAL = 20'h 0; + parameter logic [0:0] OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL = 1'h 0; + parameter logic [0:0] OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL = 1'h 0; + parameter logic [0:0] OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL = 1'h 0; + parameter logic [0:0] OTP_CTRL_STATUS_ROT_CREATOR_AUTH_CODESIGN_ERROR_RESVAL = 1'h 0; + parameter logic [0:0] OTP_CTRL_STATUS_ROT_CREATOR_AUTH_STATE_ERROR_RESVAL = 1'h 0; + parameter logic [0:0] OTP_CTRL_STATUS_HW_CFG0_ERROR_RESVAL = 1'h 0; + parameter logic [0:0] OTP_CTRL_STATUS_HW_CFG1_ERROR_RESVAL = 1'h 0; + parameter logic [0:0] OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL = 1'h 0; + parameter logic [0:0] OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL = 1'h 0; + parameter logic [0:0] OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL = 1'h 0; + parameter logic [0:0] OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL = 1'h 0; + parameter logic [0:0] OTP_CTRL_STATUS_DAI_ERROR_RESVAL = 1'h 0; + parameter logic [0:0] OTP_CTRL_STATUS_LCI_ERROR_RESVAL = 1'h 0; + parameter logic [0:0] OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL = 1'h 0; + parameter logic [0:0] OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL = 1'h 0; + parameter logic [0:0] OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL = 1'h 0; + parameter logic [0:0] OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL = 1'h 0; + parameter logic [0:0] OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL = 1'h 0; + parameter logic [0:0] OTP_CTRL_STATUS_DAI_IDLE_RESVAL = 1'h 0; + parameter logic [0:0] OTP_CTRL_STATUS_CHECK_PENDING_RESVAL = 1'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_0_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_0_ERR_CODE_0_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_1_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_1_ERR_CODE_1_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_2_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_2_ERR_CODE_2_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_3_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_3_ERR_CODE_3_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_4_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_4_ERR_CODE_4_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_5_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_5_ERR_CODE_5_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_6_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_6_ERR_CODE_6_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_7_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_7_ERR_CODE_7_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_8_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_8_ERR_CODE_8_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_9_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_9_ERR_CODE_9_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_10_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_10_ERR_CODE_10_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_11_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_11_ERR_CODE_11_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_12_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_12_ERR_CODE_12_RESVAL = 3'h 0; + parameter logic [0:0] OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL = 1'h 1; + parameter logic [0:0] OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL = 1'h 1; + parameter logic [2:0] OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL = 3'h 0; + parameter logic [0:0] OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL = 1'h 0; + parameter logic [0:0] OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL = 1'h 0; + parameter logic [0:0] OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL = 1'h 0; + parameter logic [31:0] OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL = 32'h 0; + parameter logic [1:0] OTP_CTRL_CHECK_TRIGGER_RESVAL = 2'h 0; + parameter logic [0:0] OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL = 1'h 0; + parameter logic [0:0] OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL = 1'h 0; + parameter logic [31:0] OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_ROT_CREATOR_AUTH_CODESIGN_DIGEST_0_RESVAL = 32'h 0; + parameter logic [31:0] + OTP_CTRL_ROT_CREATOR_AUTH_CODESIGN_DIGEST_0_ROT_CREATOR_AUTH_CODESIGN_DIGEST_0_RESVAL = + 32'h 0; + parameter logic [31:0] OTP_CTRL_ROT_CREATOR_AUTH_CODESIGN_DIGEST_1_RESVAL = 32'h 0; + parameter logic [31:0] + OTP_CTRL_ROT_CREATOR_AUTH_CODESIGN_DIGEST_1_ROT_CREATOR_AUTH_CODESIGN_DIGEST_1_RESVAL = + 32'h 0; + parameter logic [31:0] OTP_CTRL_ROT_CREATOR_AUTH_STATE_DIGEST_0_RESVAL = 32'h 0; + parameter logic [31:0] + OTP_CTRL_ROT_CREATOR_AUTH_STATE_DIGEST_0_ROT_CREATOR_AUTH_STATE_DIGEST_0_RESVAL = + 32'h 0; + parameter logic [31:0] OTP_CTRL_ROT_CREATOR_AUTH_STATE_DIGEST_1_RESVAL = 32'h 0; + parameter logic [31:0] + OTP_CTRL_ROT_CREATOR_AUTH_STATE_DIGEST_1_ROT_CREATOR_AUTH_STATE_DIGEST_1_RESVAL = + 32'h 0; + parameter logic [31:0] OTP_CTRL_HW_CFG0_DIGEST_0_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_HW_CFG0_DIGEST_0_HW_CFG0_DIGEST_0_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_HW_CFG0_DIGEST_1_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_HW_CFG0_DIGEST_1_HW_CFG0_DIGEST_1_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_HW_CFG1_DIGEST_0_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_HW_CFG1_DIGEST_0_HW_CFG1_DIGEST_0_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_HW_CFG1_DIGEST_1_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_HW_CFG1_DIGEST_1_HW_CFG1_DIGEST_1_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_SECRET0_DIGEST_0_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_SECRET0_DIGEST_1_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_SECRET1_DIGEST_0_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_SECRET1_DIGEST_1_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_SECRET2_DIGEST_0_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_SECRET2_DIGEST_1_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL = 32'h 0; + + // Window parameters for core interface + parameter logic [CoreAw-1:0] OTP_CTRL_SW_CFG_WINDOW_OFFSET = 12'h 800; + parameter int unsigned OTP_CTRL_SW_CFG_WINDOW_SIZE = 'h 800; + parameter int unsigned OTP_CTRL_SW_CFG_WINDOW_IDX = 0; + + // Register index for core interface + typedef enum int { + OTP_CTRL_INTR_STATE, + OTP_CTRL_INTR_ENABLE, + OTP_CTRL_INTR_TEST, + OTP_CTRL_ALERT_TEST, + OTP_CTRL_STATUS, + OTP_CTRL_ERR_CODE_0, + OTP_CTRL_ERR_CODE_1, + OTP_CTRL_ERR_CODE_2, + OTP_CTRL_ERR_CODE_3, + OTP_CTRL_ERR_CODE_4, + OTP_CTRL_ERR_CODE_5, + OTP_CTRL_ERR_CODE_6, + OTP_CTRL_ERR_CODE_7, + OTP_CTRL_ERR_CODE_8, + OTP_CTRL_ERR_CODE_9, + OTP_CTRL_ERR_CODE_10, + OTP_CTRL_ERR_CODE_11, + OTP_CTRL_ERR_CODE_12, + OTP_CTRL_DIRECT_ACCESS_REGWEN, + OTP_CTRL_DIRECT_ACCESS_CMD, + OTP_CTRL_DIRECT_ACCESS_ADDRESS, + OTP_CTRL_DIRECT_ACCESS_WDATA_0, + OTP_CTRL_DIRECT_ACCESS_WDATA_1, + OTP_CTRL_DIRECT_ACCESS_RDATA_0, + OTP_CTRL_DIRECT_ACCESS_RDATA_1, + OTP_CTRL_CHECK_TRIGGER_REGWEN, + OTP_CTRL_CHECK_TRIGGER, + OTP_CTRL_CHECK_REGWEN, + OTP_CTRL_CHECK_TIMEOUT, + OTP_CTRL_INTEGRITY_CHECK_PERIOD, + OTP_CTRL_CONSISTENCY_CHECK_PERIOD, + OTP_CTRL_VENDOR_TEST_READ_LOCK, + OTP_CTRL_CREATOR_SW_CFG_READ_LOCK, + OTP_CTRL_OWNER_SW_CFG_READ_LOCK, + OTP_CTRL_ROT_CREATOR_AUTH_CODESIGN_READ_LOCK, + OTP_CTRL_ROT_CREATOR_AUTH_STATE_READ_LOCK, + OTP_CTRL_VENDOR_TEST_DIGEST_0, + OTP_CTRL_VENDOR_TEST_DIGEST_1, + OTP_CTRL_CREATOR_SW_CFG_DIGEST_0, + OTP_CTRL_CREATOR_SW_CFG_DIGEST_1, + OTP_CTRL_OWNER_SW_CFG_DIGEST_0, + OTP_CTRL_OWNER_SW_CFG_DIGEST_1, + OTP_CTRL_ROT_CREATOR_AUTH_CODESIGN_DIGEST_0, + OTP_CTRL_ROT_CREATOR_AUTH_CODESIGN_DIGEST_1, + OTP_CTRL_ROT_CREATOR_AUTH_STATE_DIGEST_0, + OTP_CTRL_ROT_CREATOR_AUTH_STATE_DIGEST_1, + OTP_CTRL_HW_CFG0_DIGEST_0, + OTP_CTRL_HW_CFG0_DIGEST_1, + OTP_CTRL_HW_CFG1_DIGEST_0, + OTP_CTRL_HW_CFG1_DIGEST_1, + OTP_CTRL_SECRET0_DIGEST_0, + OTP_CTRL_SECRET0_DIGEST_1, + OTP_CTRL_SECRET1_DIGEST_0, + OTP_CTRL_SECRET1_DIGEST_1, + OTP_CTRL_SECRET2_DIGEST_0, + OTP_CTRL_SECRET2_DIGEST_1 + } otp_ctrl_core_id_e; + + // Register width information to check illegal writes for core interface + parameter logic [3:0] OTP_CTRL_CORE_PERMIT [56] = '{ + 4'b 0001, // index[ 0] OTP_CTRL_INTR_STATE + 4'b 0001, // index[ 1] OTP_CTRL_INTR_ENABLE + 4'b 0001, // index[ 2] OTP_CTRL_INTR_TEST + 4'b 0001, // index[ 3] OTP_CTRL_ALERT_TEST + 4'b 0111, // index[ 4] OTP_CTRL_STATUS + 4'b 0001, // index[ 5] OTP_CTRL_ERR_CODE_0 + 4'b 0001, // index[ 6] OTP_CTRL_ERR_CODE_1 + 4'b 0001, // index[ 7] OTP_CTRL_ERR_CODE_2 + 4'b 0001, // index[ 8] OTP_CTRL_ERR_CODE_3 + 4'b 0001, // index[ 9] OTP_CTRL_ERR_CODE_4 + 4'b 0001, // index[10] OTP_CTRL_ERR_CODE_5 + 4'b 0001, // index[11] OTP_CTRL_ERR_CODE_6 + 4'b 0001, // index[12] OTP_CTRL_ERR_CODE_7 + 4'b 0001, // index[13] OTP_CTRL_ERR_CODE_8 + 4'b 0001, // index[14] OTP_CTRL_ERR_CODE_9 + 4'b 0001, // index[15] OTP_CTRL_ERR_CODE_10 + 4'b 0001, // index[16] OTP_CTRL_ERR_CODE_11 + 4'b 0001, // index[17] OTP_CTRL_ERR_CODE_12 + 4'b 0001, // index[18] OTP_CTRL_DIRECT_ACCESS_REGWEN + 4'b 0001, // index[19] OTP_CTRL_DIRECT_ACCESS_CMD + 4'b 0011, // index[20] OTP_CTRL_DIRECT_ACCESS_ADDRESS + 4'b 1111, // index[21] OTP_CTRL_DIRECT_ACCESS_WDATA_0 + 4'b 1111, // index[22] OTP_CTRL_DIRECT_ACCESS_WDATA_1 + 4'b 1111, // index[23] OTP_CTRL_DIRECT_ACCESS_RDATA_0 + 4'b 1111, // index[24] OTP_CTRL_DIRECT_ACCESS_RDATA_1 + 4'b 0001, // index[25] OTP_CTRL_CHECK_TRIGGER_REGWEN + 4'b 0001, // index[26] OTP_CTRL_CHECK_TRIGGER + 4'b 0001, // index[27] OTP_CTRL_CHECK_REGWEN + 4'b 1111, // index[28] OTP_CTRL_CHECK_TIMEOUT + 4'b 1111, // index[29] OTP_CTRL_INTEGRITY_CHECK_PERIOD + 4'b 1111, // index[30] OTP_CTRL_CONSISTENCY_CHECK_PERIOD + 4'b 0001, // index[31] OTP_CTRL_VENDOR_TEST_READ_LOCK + 4'b 0001, // index[32] OTP_CTRL_CREATOR_SW_CFG_READ_LOCK + 4'b 0001, // index[33] OTP_CTRL_OWNER_SW_CFG_READ_LOCK + 4'b 0001, // index[34] OTP_CTRL_ROT_CREATOR_AUTH_CODESIGN_READ_LOCK + 4'b 0001, // index[35] OTP_CTRL_ROT_CREATOR_AUTH_STATE_READ_LOCK + 4'b 1111, // index[36] OTP_CTRL_VENDOR_TEST_DIGEST_0 + 4'b 1111, // index[37] OTP_CTRL_VENDOR_TEST_DIGEST_1 + 4'b 1111, // index[38] OTP_CTRL_CREATOR_SW_CFG_DIGEST_0 + 4'b 1111, // index[39] OTP_CTRL_CREATOR_SW_CFG_DIGEST_1 + 4'b 1111, // index[40] OTP_CTRL_OWNER_SW_CFG_DIGEST_0 + 4'b 1111, // index[41] OTP_CTRL_OWNER_SW_CFG_DIGEST_1 + 4'b 1111, // index[42] OTP_CTRL_ROT_CREATOR_AUTH_CODESIGN_DIGEST_0 + 4'b 1111, // index[43] OTP_CTRL_ROT_CREATOR_AUTH_CODESIGN_DIGEST_1 + 4'b 1111, // index[44] OTP_CTRL_ROT_CREATOR_AUTH_STATE_DIGEST_0 + 4'b 1111, // index[45] OTP_CTRL_ROT_CREATOR_AUTH_STATE_DIGEST_1 + 4'b 1111, // index[46] OTP_CTRL_HW_CFG0_DIGEST_0 + 4'b 1111, // index[47] OTP_CTRL_HW_CFG0_DIGEST_1 + 4'b 1111, // index[48] OTP_CTRL_HW_CFG1_DIGEST_0 + 4'b 1111, // index[49] OTP_CTRL_HW_CFG1_DIGEST_1 + 4'b 1111, // index[50] OTP_CTRL_SECRET0_DIGEST_0 + 4'b 1111, // index[51] OTP_CTRL_SECRET0_DIGEST_1 + 4'b 1111, // index[52] OTP_CTRL_SECRET1_DIGEST_0 + 4'b 1111, // index[53] OTP_CTRL_SECRET1_DIGEST_1 + 4'b 1111, // index[54] OTP_CTRL_SECRET2_DIGEST_0 + 4'b 1111 // index[55] OTP_CTRL_SECRET2_DIGEST_1 + }; + + /////////////////////////////////////////////// + // Typedefs for registers for prim interface // + /////////////////////////////////////////////// + + typedef struct packed { + struct packed { + logic [10:0] q; + } field4; + struct packed { + logic [9:0] q; + } field3; + struct packed { + logic q; + } field2; + struct packed { + logic q; + } field1; + struct packed { + logic q; + } field0; + } otp_ctrl_reg2hw_csr0_reg_t; + + typedef struct packed { + struct packed { + logic [15:0] q; + } field4; + struct packed { + logic q; + } field3; + struct packed { + logic [6:0] q; + } field2; + struct packed { + logic q; + } field1; + struct packed { + logic [6:0] q; + } field0; + } otp_ctrl_reg2hw_csr1_reg_t; + + typedef struct packed { + logic q; + } otp_ctrl_reg2hw_csr2_reg_t; + + typedef struct packed { + struct packed { + logic q; + } field8; + struct packed { + logic q; + } field7; + struct packed { + logic q; + } field6; + struct packed { + logic q; + } field5; + struct packed { + logic q; + } field4; + struct packed { + logic q; + } field3; + struct packed { + logic q; + } field2; + struct packed { + logic [9:0] q; + } field1; + struct packed { + logic [2:0] q; + } field0; + } otp_ctrl_reg2hw_csr3_reg_t; + + typedef struct packed { + struct packed { + logic q; + } field3; + struct packed { + logic q; + } field2; + struct packed { + logic q; + } field1; + struct packed { + logic [9:0] q; + } field0; + } otp_ctrl_reg2hw_csr4_reg_t; + + typedef struct packed { + struct packed { + logic [15:0] q; + } field6; + struct packed { + logic q; + } field5; + struct packed { + logic q; + } field4; + struct packed { + logic [2:0] q; + } field3; + struct packed { + logic q; + } field2; + struct packed { + logic [1:0] q; + } field1; + struct packed { + logic [5:0] q; + } field0; + } otp_ctrl_reg2hw_csr5_reg_t; + + typedef struct packed { + struct packed { + logic [15:0] q; + } field3; + struct packed { + logic q; + } field2; + struct packed { + logic q; + } field1; + struct packed { + logic [9:0] q; + } field0; + } otp_ctrl_reg2hw_csr6_reg_t; + + typedef struct packed { + struct packed { + logic q; + } field3; + struct packed { + logic q; + } field2; + struct packed { + logic [2:0] q; + } field1; + struct packed { + logic [5:0] q; + } field0; + } otp_ctrl_reg2hw_csr7_reg_t; + + typedef struct packed { + struct packed { + logic [2:0] d; + logic de; + } field0; + struct packed { + logic [9:0] d; + logic de; + } field1; + struct packed { + logic d; + logic de; + } field2; + struct packed { + logic d; + logic de; + } field3; + struct packed { + logic d; + logic de; + } field4; + struct packed { + logic d; + logic de; + } field5; + struct packed { + logic d; + logic de; + } field6; + struct packed { + logic d; + logic de; + } field7; + struct packed { + logic d; + logic de; + } field8; + } otp_ctrl_hw2reg_csr3_reg_t; + + typedef struct packed { + struct packed { + logic [5:0] d; + logic de; + } field0; + struct packed { + logic [1:0] d; + logic de; + } field1; + struct packed { + logic d; + logic de; + } field2; + struct packed { + logic [2:0] d; + logic de; + } field3; + struct packed { + logic d; + logic de; + } field4; + struct packed { + logic d; + logic de; + } field5; + struct packed { + logic [15:0] d; + logic de; + } field6; + } otp_ctrl_hw2reg_csr5_reg_t; + + typedef struct packed { + struct packed { + logic [5:0] d; + logic de; + } field0; + struct packed { + logic [2:0] d; + logic de; + } field1; + struct packed { + logic d; + logic de; + } field2; + struct packed { + logic d; + logic de; + } field3; + } otp_ctrl_hw2reg_csr7_reg_t; + + // Register -> HW type for prim interface + typedef struct packed { + otp_ctrl_reg2hw_csr0_reg_t csr0; // [158:135] + otp_ctrl_reg2hw_csr1_reg_t csr1; // [134:103] + otp_ctrl_reg2hw_csr2_reg_t csr2; // [102:102] + otp_ctrl_reg2hw_csr3_reg_t csr3; // [101:82] + otp_ctrl_reg2hw_csr4_reg_t csr4; // [81:69] + otp_ctrl_reg2hw_csr5_reg_t csr5; // [68:39] + otp_ctrl_reg2hw_csr6_reg_t csr6; // [38:11] + otp_ctrl_reg2hw_csr7_reg_t csr7; // [10:0] + } otp_ctrl_prim_reg2hw_t; + + // HW -> register type for prim interface + typedef struct packed { + otp_ctrl_hw2reg_csr3_reg_t csr3; // [80:52] + otp_ctrl_hw2reg_csr5_reg_t csr5; // [51:15] + otp_ctrl_hw2reg_csr7_reg_t csr7; // [14:0] + } otp_ctrl_prim_hw2reg_t; + + // Register offsets for prim interface + parameter logic [PrimAw-1:0] OTP_CTRL_CSR0_OFFSET = 5'h 0; + parameter logic [PrimAw-1:0] OTP_CTRL_CSR1_OFFSET = 5'h 4; + parameter logic [PrimAw-1:0] OTP_CTRL_CSR2_OFFSET = 5'h 8; + parameter logic [PrimAw-1:0] OTP_CTRL_CSR3_OFFSET = 5'h c; + parameter logic [PrimAw-1:0] OTP_CTRL_CSR4_OFFSET = 5'h 10; + parameter logic [PrimAw-1:0] OTP_CTRL_CSR5_OFFSET = 5'h 14; + parameter logic [PrimAw-1:0] OTP_CTRL_CSR6_OFFSET = 5'h 18; + parameter logic [PrimAw-1:0] OTP_CTRL_CSR7_OFFSET = 5'h 1c; + + // Register index for prim interface + typedef enum int { + OTP_CTRL_CSR0, + OTP_CTRL_CSR1, + OTP_CTRL_CSR2, + OTP_CTRL_CSR3, + OTP_CTRL_CSR4, + OTP_CTRL_CSR5, + OTP_CTRL_CSR6, + OTP_CTRL_CSR7 + } otp_ctrl_prim_id_e; + + // Register width information to check illegal writes for prim interface + parameter logic [3:0] OTP_CTRL_PRIM_PERMIT [8] = '{ + 4'b 1111, // index[0] OTP_CTRL_CSR0 + 4'b 1111, // index[1] OTP_CTRL_CSR1 + 4'b 0001, // index[2] OTP_CTRL_CSR2 + 4'b 0111, // index[3] OTP_CTRL_CSR3 + 4'b 0011, // index[4] OTP_CTRL_CSR4 + 4'b 1111, // index[5] OTP_CTRL_CSR5 + 4'b 1111, // index[6] OTP_CTRL_CSR6 + 4'b 0011 // index[7] OTP_CTRL_CSR7 + }; + +endpackage diff --git a/src/fuse_ctrl/rtl/otp_ctrl_scrmbl.sv b/src/fuse_ctrl/rtl/otp_ctrl_scrmbl.sv new file mode 100644 index 0000000..6a4ab22 --- /dev/null +++ b/src/fuse_ctrl/rtl/otp_ctrl_scrmbl.sv @@ -0,0 +1,510 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This module contains the scrambling datapath for the OTP controller. It basically consists of +// two single-round PRESENT primitives (one for encryption and one for decryption mode), a counter +// with a simple FSM and four working registers, as listed below. +// +// key_state_q (128bit): working register to hold the round key (needed for the key schedule). +// +// data_state_q (64bit): working register to hold the data state in between rounds. +// +// data_shadow_q (64bit): shadow register for holding a second 64bit block of input data. This is +// used to form a 128bit data block for the digest mode, which has a block +// size of 128bit. +// +// digest_state_q (64bit): register to hold the digest state in between digest updates. Technically, +// this is not needed when the data for the digest is fed into this block +// back-to-back. However, the partition integrity checks require that it is +// possible to interleave encryption operations and digest update steps, +// hence an additional state register is needed, as otherwise the digest +// state would be lost. +// +// The scrambling datapath is arranged such that it can also be used for calculating a digest using +// the encryption primitive in a Merkle-Damgard construction. To that end, the PRESENT block cipher +// is turned into a one way function according to the Davies-Meyer scheme. Note however that this +// makes the digest block size 128bit wide, since the Merkle-Damgard construction leverages the +// cipher key input to ingest data. +// +// The scrambling datapath exposes a few simple commands and the FSM hides the complexity +// of steering the appropriate muxes and keeping track of the cipher rounds. These commands are +// briefly explained below. +// +// Decrypt: This decrypts the data block provided via data_i with the key at index sel_i. +// +// Encrypt: This encrypts the data block provided via data_i with the key at index sel_i. +// In addition, this command copies the prvious result into a shadow register before +// the first encryption round for later use in the digest (see description further below). +// This enables interleaved encrypt/digest operation needed for the integrity checks of +// the secret partitions. +// +// LoadShadow: In "StandardMode", the LoadShadow command loads the data provided via data_i into a +// shadow register that is mapped to the lower 64bit of the 128bit digest input data +// block. In "ChainedMode", this command copies the contents of the data state register +// into the shadow register. +// +// DigestInit: This ensures that the digest initialization vector (IV) is selected upon the next +// call of the Digest command. Also, mode_i can be used to set the digest mode. If +// mode_i is set to "StandardMode", the data to be digested has to be provided via +// data_i and LoadShadow. If mode_i is set to "ChainedMode", the digest input is formed +// by concatenating the results of the revious two encryption commands. +// +// Digest: In "StandardMode", this command concatenates the data input supplied via data_i with +// the shadow register in order to form a 128bit block ({data_i, data_shadow_q}). This block +// is then used to encrypt the digest state. In "ChainedMode" digest mode, the 128bit block +// to be digested is formed by concatenating {data_state_q, data_shadow_q}. If a DigestInit +// command has been executed right before calling Digest, the IV selected with sel_i is +// used to initialize the state. +// +// DigestFinalize: This command encrypts the digest state with the finalization constant selected +// by sel_i in order to form the final digest. +// +// References: - https://docs.opentitan.org/hw/ip/otp_ctrl/doc/index.html#design-details +// - https://docs.opentitan.org/hw/ip/prim/doc/prim_present/ +// - https://en.wikipedia.org/wiki/Merkle-Damgard_construction +// - https://en.wikipedia.org/wiki/One-way_compression_function#Davies%E2%80%93Meyer +// - https://en.wikipedia.org/wiki/PRESENT +// - http://www.lightweightcrypto.org/present/present_ches2007.pdf +// + +`include "caliptra_prim_flop_macros.sv" + +module otp_ctrl_scrmbl + import otp_ctrl_pkg::*; + import otp_ctrl_part_pkg::*; +( + input clk_i, + input rst_ni, + // input data and command + input otp_scrmbl_cmd_e cmd_i, + input digest_mode_e mode_i, + input [ConstSelWidth-1:0] sel_i, + input [ScrmblBlockWidth-1:0] data_i, + input valid_i, + output logic ready_o, + // output data + output logic [ScrmblBlockWidth-1:0] data_o, + output logic valid_o, + // escalation input and FSM error indication + input caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_t escalate_en_i, + output logic fsm_err_o +); + + import caliptra_prim_util_pkg::vbits; + + //////////////////////// + // Decryption Key LUT // + //////////////////////// + + // Anchor keys, constants and IVs + key_array_t rnd_cnst_key_anchor; + digest_const_array_t rnd_cnst_digest_anchor; + digest_iv_array_t rnd_cnst_digest_iv_anchor; + + for (genvar i = 0; i < NumScrmblKeys; i++) begin : gen_anchor_keys + caliptra_prim_sec_anchor_buf #( + .Width(ScrmblKeyWidth) + ) u_key_anchor_buf ( + .in_i(RndCnstKey[i]), + .out_o(rnd_cnst_key_anchor[i]) + ); + end + + for (genvar i = 0; i < NumDigestSets; i++) begin : gen_anchor_digests + caliptra_prim_sec_anchor_buf #( + .Width(ScrmblKeyWidth) + ) u_const_anchor_buf ( + .in_i(RndCnstDigestConst[i]), + .out_o(rnd_cnst_digest_anchor[i]) + ); + + caliptra_prim_sec_anchor_buf #( + .Width(ScrmblBlockWidth) + ) u_iv_anchor_buf ( + .in_i(RndCnstDigestIV[i]), + .out_o(rnd_cnst_digest_iv_anchor[i]) + ); + end + + + // Align these arrays to power of 2's to prevent X's in the muxing operations further below. + logic [2**$clog2(NumScrmblKeys)-1:0][ScrmblKeyWidth-1:0] otp_enc_key_lut; + logic [2**$clog2(NumScrmblKeys)-1:0][ScrmblKeyWidth-1:0] otp_dec_key_lut; + logic [2**$clog2(NumDigestSets)-1:0][ScrmblKeyWidth-1:0] digest_const_lut; + logic [2**$clog2(NumDigestSets)-1:0][ScrmblBlockWidth-1:0] digest_iv_lut; + + // This pre-calculates the inverse scrambling keys at elab time. + `CALIPTRA_ASSERT_INIT(NumMaxPresentRounds_A, NumPresentRounds <= 31) + + always_comb begin : p_luts + otp_enc_key_lut = '0; + otp_dec_key_lut = '0; + digest_const_lut = '0; + digest_iv_lut = '0; + + for (int k = 0; k < NumScrmblKeys; k++) begin + localparam logic [4:0] NumRounds = 5'(unsigned'(NumPresentRounds)); + otp_enc_key_lut[k] = rnd_cnst_key_anchor[k]; + // Due to the PRESENT key schedule, we have to step the key schedule function by + // NumPresentRounds forwards to get the decryption key. + otp_dec_key_lut[k] = + caliptra_prim_cipher_pkg::present_get_dec_key128(rnd_cnst_key_anchor[k], NumRounds); + end + + for (int k = 0; k < NumDigestSets; k++) begin + digest_const_lut[k] = rnd_cnst_digest_anchor[k]; + digest_iv_lut[k] = rnd_cnst_digest_iv_anchor[k]; + end + end + `CALIPTRA_ASSERT_KNOWN(EncKeyLutKnown_A, otp_enc_key_lut) + `CALIPTRA_ASSERT_KNOWN(DecKeyLutKnown_A, otp_dec_key_lut) + `CALIPTRA_ASSERT_KNOWN(DigestConstLutKnown_A, digest_const_lut) + `CALIPTRA_ASSERT_KNOWN(DigestIvLutKnown_A, digest_iv_lut) + + ////////////// + // Datapath // + ////////////// + + logic [4:0] idx_state_d, idx_state_q; + logic [ScrmblKeyWidth-1:0] key_state_d, key_state_q; + logic [ScrmblBlockWidth-1:0] data_state_d, data_state_q, data_shadow_q; + logic [ScrmblBlockWidth-1:0] digest_state_d, digest_state_q; + logic [ScrmblBlockWidth-1:0] enc_data_out, enc_data_out_xor, dec_data_out; + logic [ScrmblKeyWidth-1:0] dec_key_out, enc_key_out; + logic [4:0] dec_idx_out, enc_idx_out; + logic [ScrmblKeyWidth-1:0] otp_digest_const_mux, otp_enc_key_mux, otp_dec_key_mux; + logic [ScrmblBlockWidth-1:0] otp_digest_iv_mux; + + typedef enum logic [2:0] {SelEncDataOut, + SelDecDataOut, + SelDigestState, + SelEncDataOutXor, + SelDataInput} data_state_sel_e; + + typedef enum logic [2:0] {SelDecKeyOut, + SelEncKeyOut, + SelDecKeyInit, + SelEncKeyInit, + SelDigestConst, + SelDigestInput, + SelDigestChained} key_state_sel_e; + + logic digest_init; + data_state_sel_e data_state_sel; + key_state_sel_e key_state_sel; + logic data_state_en, data_shadow_copy, data_shadow_load, digest_state_en, key_state_en; + digest_mode_e digest_mode_d, digest_mode_q; + + assign otp_enc_key_mux = otp_enc_key_lut[ScrmblKeySelWidth'(sel_i)]; + assign otp_dec_key_mux = otp_dec_key_lut[ScrmblKeySelWidth'(sel_i)]; + assign otp_digest_const_mux = digest_const_lut[DigestSetSelWidth'(sel_i)]; + assign otp_digest_iv_mux = digest_iv_lut[DigestSetSelWidth'(sel_i)]; + + // Make sure we always select a valid key / digest constant. + `CALIPTRA_ASSERT(CheckNumEncKeys_A, key_state_sel == SelEncKeyInit |-> sel_i < NumScrmblKeys) + `CALIPTRA_ASSERT(CheckNumDecKeys_A, key_state_sel == SelDecKeyInit |-> sel_i < NumScrmblKeys) + `CALIPTRA_ASSERT(CheckNumDigest1_A, key_state_sel == SelDigestConst |-> sel_i < NumDigestSets) + + assign data_state_d = (data_state_sel == SelEncDataOut) ? enc_data_out : + (data_state_sel == SelDecDataOut) ? dec_data_out : + (data_state_sel == SelDigestState) ? digest_state_q : + (data_state_sel == SelEncDataOutXor) ? enc_data_out_xor : + data_i; + + assign key_state_d = (key_state_sel == SelDecKeyOut) ? dec_key_out : + (key_state_sel == SelEncKeyOut) ? enc_key_out : + (key_state_sel == SelDecKeyInit) ? otp_dec_key_mux : + (key_state_sel == SelEncKeyInit) ? otp_enc_key_mux : + (key_state_sel == SelDigestConst) ? otp_digest_const_mux : + (key_state_sel == SelDigestChained) ? {data_state_q, data_shadow_q} : + {data_i, data_shadow_q}; + + // Initialize the round index state with 1 in all cases, except for the decrypt operation. + assign idx_state_d = (key_state_sel == SelDecKeyOut) ? dec_idx_out : + (key_state_sel == SelEncKeyOut) ? enc_idx_out : + (key_state_sel == SelDecKeyInit) ? unsigned'(5'(NumPresentRounds)) : + 5'd1; + + // The XOR is for the Davies-Mayer one-way function construction. + assign enc_data_out_xor = enc_data_out ^ digest_state_q; + assign digest_state_d = (digest_init) ? otp_digest_iv_mux : enc_data_out_xor; + + logic valid_q; //valid_d defined below + assign data_o = (valid_q) ? data_state_q : 0; + + ///////// + // FSM // + ///////// + + // SEC_CM: SCRMBL.FSM.SPARSE + // Encoding generated with: + // $ ./util/design/sparse-fsm-encode.py -d 5 -m 5 -n 9 \ + // -s 2193087944 --language=sv + // + // Hamming distance histogram: + // + // 0: -- + // 1: -- + // 2: -- + // 3: -- + // 4: -- + // 5: |||||||||||||||||||| (60.00%) + // 6: ||||||||||||| (40.00%) + // 7: -- + // 8: -- + // 9: -- + // + // Minimum Hamming distance: 5 + // Maximum Hamming distance: 6 + // Minimum Hamming weight: 4 + // Maximum Hamming weight: 7 + // + localparam int StateWidth = 9; + typedef enum logic [StateWidth-1:0] { + IdleSt = 9'b100011001, + DecryptSt = 9'b101101111, + EncryptSt = 9'b010010111, + DigestSt = 9'b111000010, + ErrorSt = 9'b011111000 + } state_e; + + localparam int CntWidth = $clog2(NumPresentRounds+1); + localparam int unsigned LastPresentRoundInt = NumPresentRounds - 1; + localparam bit [CntWidth-1:0] LastPresentRound = LastPresentRoundInt[CntWidth-1:0]; + + state_e state_d, state_q; + logic [CntWidth-1:0] cnt; + logic cnt_clr, cnt_en, cnt_err; + logic valid_d; //valid_q defined above + + assign valid_o = valid_q; + + // SEC_CM: SCRMBL.CTR.REDUN + caliptra_prim_count #( + .Width(CntWidth) + ) u_prim_count ( + .clk_i, + .rst_ni, + .clr_i(cnt_clr), + .set_i(1'b0), + .set_cnt_i('0), + .incr_en_i(cnt_en), + .decr_en_i(1'b0), + .step_i(CntWidth'(1)), + .commit_i(1'b1), + .cnt_o(cnt), + .cnt_after_commit_o(), + .err_o(cnt_err) + ); + + always_comb begin : p_fsm + state_d = state_q; + digest_mode_d = digest_mode_q; + data_state_sel = SelDataInput; + key_state_sel = SelDigestInput; + digest_init = 1'b0; + data_state_en = 1'b0; + data_shadow_copy = 1'b0; + data_shadow_load = 1'b0; + key_state_en = 1'b0; + digest_state_en = 1'b0; + cnt_en = 1'b0; + cnt_clr = 1'b0; + valid_d = 1'b0; + ready_o = 1'b0; + fsm_err_o = 1'b0; + + unique case (state_q) + /////////////////////////////////////////////////////////////////// + // Idle State: decode command and + // load working regs accordingly + IdleSt: begin + cnt_clr = 1'b1; + ready_o = 1'b1; + + if (valid_i) begin + unique case (cmd_i) + Decrypt: begin + state_d = DecryptSt; + key_state_sel = SelDecKeyInit; + data_state_en = 1'b1; + key_state_en = 1'b1; + end + Encrypt: begin + state_d = EncryptSt; + key_state_sel = SelEncKeyInit; + data_state_en = 1'b1; + key_state_en = 1'b1; + end + LoadShadow: begin + if (digest_mode_q == ChainedMode) begin + data_shadow_copy = 1'b1; + end else begin + data_shadow_load = 1'b1; + end + end + Digest: begin + state_d = DigestSt; + data_state_sel = SelDigestState; + key_state_sel = (digest_mode_q == ChainedMode) ? SelDigestChained : SelDigestInput; + data_state_en = 1'b1; + key_state_en = 1'b1; + end + DigestInit: begin + digest_mode_d = mode_i; + digest_init = 1'b1; + digest_state_en = 1'b1; + end + DigestFinalize: begin + state_d = DigestSt; + data_state_sel = SelDigestState; + key_state_sel = SelDigestConst; + data_state_en = 1'b1; + key_state_en = 1'b1; + digest_mode_d = StandardMode; + end + default: ; // ignore + endcase // cmd_i + end + end + /////////////////////////////////////////////////////////////////// + // Perform decrypt rounds. + DecryptSt: begin + data_state_sel = SelDecDataOut; + key_state_sel = SelDecKeyOut; + data_state_en = 1'b1; + key_state_en = 1'b1; + cnt_en = 1'b1; + if (cnt == LastPresentRound) begin + state_d = IdleSt; + valid_d = 1'b1; + end + end + /////////////////////////////////////////////////////////////////// + // Perform encrypt rounds. + EncryptSt: begin + data_state_sel = SelEncDataOut; + key_state_sel = SelEncKeyOut; + data_state_en = 1'b1; + key_state_en = 1'b1; + cnt_en = 1'b1; + if (cnt == LastPresentRound) begin + state_d = IdleSt; + valid_d = 1'b1; + end + end + /////////////////////////////////////////////////////////////////// + // The digest is calculated with a Merkle-Damgard construction that + // employs the PRESENT encryption datapath. + DigestSt: begin + data_state_sel = SelEncDataOut; + key_state_sel = SelEncKeyOut; + data_state_en = 1'b1; + key_state_en = 1'b1; + cnt_en = 1'b1; + if (cnt == LastPresentRound) begin + state_d = IdleSt; + valid_d = 1'b1; + // Apply XOR for Davies-Meyer construction. + data_state_sel = SelEncDataOutXor; + // Backup digest state for next round of updates. We can't keep this state in the + // data state register as a digest may be calculated together with encryption + // operations in an interleaved way. + digest_state_en = 1'b1; + end + end + /////////////////////////////////////////////////////////////////// + // Terminal error state. This raises an alert. + ErrorSt: begin + fsm_err_o = 1'b1; + end + /////////////////////////////////////////////////////////////////// + // This should never happen, hence we directly jump into the + // error state, where an alert will be triggered. + default: begin + state_d = ErrorSt; + fsm_err_o = 1'b1; + end + /////////////////////////////////////////////////////////////////// + endcase // state_q + + // Unconditionally jump into the terminal error state in case of escalation. + // SEC_CM: SCRMBL.FSM.LOCAL_ESC, SCRMBL.FSM.GLOBAL_ESC + if (caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_test_true_loose(escalate_en_i) || cnt_err) begin + state_d = ErrorSt; + fsm_err_o = 1'b1; + end + end + + ///////////////////////////// + // PRESENT DEC/ENC Modules // + ///////////////////////////// + + caliptra_prim_present #( + .KeyWidth(128), + .NumRounds(NumPresentRounds), + .NumPhysRounds(1) + ) u_prim_present_enc ( + .data_i ( data_state_q ), + .key_i ( key_state_q ), + .idx_i ( idx_state_q ), + .data_o ( enc_data_out ), + .key_o ( enc_key_out ), + .idx_o ( enc_idx_out ) + ); + + caliptra_prim_present #( + .KeyWidth(128), + // We are using an iterative full-round implementation here. + .NumRounds(NumPresentRounds), + .NumPhysRounds(1), + .Decrypt(1) + ) u_prim_present_dec ( + .data_i ( data_state_q ), + .key_i ( key_state_q ), + .idx_i ( idx_state_q ), + .data_o ( dec_data_out ), + .key_o ( dec_key_out ), + .idx_o ( dec_idx_out ) + ); + + /////////////// + // Registers // + /////////////// + + `CALIPTRA_PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt) + + always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs + if (!rst_ni) begin + key_state_q <= '0; + idx_state_q <= '0; + data_state_q <= '0; + data_shadow_q <= '0; + digest_state_q <= '0; + valid_q <= 1'b0; + digest_mode_q <= StandardMode; + end else begin + valid_q <= valid_d; + digest_mode_q <= digest_mode_d; + + // enable regs + if (key_state_en) begin + key_state_q <= key_state_d; + idx_state_q <= idx_state_d; + end + if (data_state_en) begin + data_state_q <= data_state_d; + end + if (data_shadow_copy) begin + data_shadow_q <= data_state_q; + end else if (data_shadow_load) begin + data_shadow_q <= data_state_d; + end + if (digest_state_en) begin + digest_state_q <= digest_state_d; + end + end + end + +endmodule : otp_ctrl_scrmbl diff --git a/src/fuse_ctrl/rtl/otp_ctrl_token_const.sv b/src/fuse_ctrl/rtl/otp_ctrl_token_const.sv new file mode 100644 index 0000000..f9fd7ca --- /dev/null +++ b/src/fuse_ctrl/rtl/otp_ctrl_token_const.sv @@ -0,0 +1,70 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This module contains the hash post-image constants for the all-zero and raw unlock tokens. +// This implementation relies on constant propagation to precompute these constants from the +// random netlist constants at compile time, and hence does not contain any "real" logic. + +module otp_ctrl_token_const + import otp_ctrl_pkg::*; + import otp_ctrl_part_pkg::*; + #( + // Compile time random constants, to be overriden by topgen. + parameter digest_const_array_t RndCnstDigestConst = RndCnstDigestConstDefault, + parameter digest_iv_array_t RndCnstDigestIV = RndCnstDigestIVDefault, + parameter caliptra_ss_lc_ctrl_state_pkg::caliptra_ss_lc_token_t RndCnstRawUnlockToken = caliptra_ss_lc_ctrl_state_pkg::RndCnstRawUnlockTokenDefault +) ( + output caliptra_ss_lc_ctrl_state_pkg::caliptra_ss_lc_token_t all_zero_token_hashed_o, + output caliptra_ss_lc_ctrl_state_pkg::caliptra_ss_lc_token_t raw_unlock_token_hashed_o +); + + localparam int NumHashes = 2; + localparam int AllZeroIdx = 0; + localparam int RawUnlockIdx = 1; + //[anjpar] Adding localpram LcRawDigest and initializing to 0 + localparam int LcRawDigest = 0; + + logic [NumHashes-1:0][1:0][ScrmblKeyWidth-1:0] data; + logic [NumHashes-1:0][4:0][ScrmblBlockWidth-1:0] state; + + // First digest is for the all zero token, the second is for the raw unlock token. + assign data[AllZeroIdx][0] = '0; + assign data[RawUnlockIdx][0] = RndCnstRawUnlockToken; + + // Repeat for all precomputed hashes. + for (genvar j = 0; j < NumHashes; j++) begin : gen_hashes + // Initialize all hashes with digest IV. + assign state[j][0] = RndCnstDigestIV[LcRawDigest]; + // Second data block is always the digest finalization constant. + assign data[j][1] = RndCnstDigestConst[LcRawDigest]; + + // Each hash takes four invocations, see diagram c) on + // https://docs.opentitan.org/hw/ip/otp_ctrl/doc/index.html#scrambling-datapath + for (genvar k = 0; k < 4; k++) begin : gen_invocations + logic [ScrmblBlockWidth-1:0] next_state; + + // This relies on constant propagation to + // statically precompute the hashed token values. + caliptra_prim_present #( + .KeyWidth(128), + .NumRounds(NumPresentRounds) + ) u_prim_present_enc_0 ( + .data_i ( state[j][k] ), + .key_i ( data[j][k%2] ), + .idx_i ( 5'h1 ), + .data_o ( next_state ), + .key_o ( ), + .idx_o ( ) + ); + + // XOR in last state according to the Davies-Meyer scheme. + assign state[j][k+1] = next_state ^ state[j][k]; + end + end + + // Concatenate the two 64bit hash results to form the final digests. + assign all_zero_token_hashed_o = {state[AllZeroIdx][4], state[AllZeroIdx][2]}; + assign raw_unlock_token_hashed_o = {state[RawUnlockIdx][4], state[RawUnlockIdx][2]}; + +endmodule : otp_ctrl_token_const diff --git a/src/fuse_ctrl/rtl/prim_generic_otp.sv b/src/fuse_ctrl/rtl/prim_generic_otp.sv new file mode 100644 index 0000000..167e651 --- /dev/null +++ b/src/fuse_ctrl/rtl/prim_generic_otp.sv @@ -0,0 +1,435 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +module prim_generic_otp + import caliptra_prim_otp_pkg::*; +#( + // Native OTP word size. This determines the size_i granule. + parameter int Width = 16, + parameter int Depth = 1024, + // This determines the maximum number of native words that + // can be transferred accross the interface in one cycle. + parameter int SizeWidth = 2, + // Width of the power sequencing signal. + parameter int PwrSeqWidth = 2, + // Width of vendor-specific test control signal + parameter int TestCtrlWidth = 32, + parameter int TestStatusWidth = 32, + parameter int TestVectWidth = 8, + // Derived parameters + localparam int AddrWidth = caliptra_prim_util_pkg::vbits(Depth), + localparam int IfWidth = 2**SizeWidth*Width, + // VMEM file to initialize the memory with + parameter MemInitFile = "", + // Vendor test partition offset and size (both in bytes) + parameter int VendorTestOffset = 0, + parameter int VendorTestSize = 0 +) ( + input clk_i, + input rst_ni, + // Observability + input ast_pkg::ast_obs_ctrl_t obs_ctrl_i, + output logic [7:0] otp_obs_o, + // Macro-specific power sequencing signals to/from AST + output logic [PwrSeqWidth-1:0] pwr_seq_o, + input [PwrSeqWidth-1:0] pwr_seq_h_i, + // External programming voltage + inout wire ext_voltage_io, + // Test interfaces + input [TestCtrlWidth-1:0] test_ctrl_i, + output logic [TestStatusWidth-1:0] test_status_o, + output logic [TestVectWidth-1:0] test_vect_o, + input tlul_pkg::tl_h2d_t test_tl_i, + output tlul_pkg::tl_d2h_t test_tl_o, + // Other DFT signals + input caliptra_prim_mubi_pkg::mubi4_t scanmode_i, // Scan Mode input + input scan_en_i, // Scan Shift + input scan_rst_ni, // Scan Reset + // Alert indication (to be connected to alert sender in the instantiating IP) + output logic fatal_alert_o, + output logic recov_alert_o, + // Ready valid handshake for read/write command + output logic ready_o, + input valid_i, + // #(Native words)-1, e.g. size == 0 for 1 native word. + input [SizeWidth-1:0] size_i, + // See prim_otp_pkg for the command encoding. + input cmd_e cmd_i, + input [AddrWidth-1:0] addr_i, + input [IfWidth-1:0] wdata_i, + // Response channel + output logic valid_o, + output logic [IfWidth-1:0] rdata_o, + output err_e err_o +); + + import caliptra_prim_mubi_pkg::MuBi4False; + + // This is only restricted by the supported ECC poly further + // below, and is straightforward to extend, if needed. + localparam int EccWidth = 6; + `CALIPTRA_ASSERT_INIT(SecDecWidth_A, Width == 16) + + // Not supported in open-source emulation model. + logic [PwrSeqWidth-1:0] unused_pwr_seq_h; + assign unused_pwr_seq_h = pwr_seq_h_i; + assign pwr_seq_o = '0; + + logic unused_obs; + assign unused_obs = |obs_ctrl_i; + assign otp_obs_o = '0; + + wire unused_ext_voltage; + assign unused_ext_voltage = ext_voltage_io; + logic unused_test_ctrl_i; + assign unused_test_ctrl_i = ^test_ctrl_i; + + logic unused_scan; + assign unused_scan = ^{scanmode_i, scan_en_i, scan_rst_ni}; + + logic intg_err, fsm_err; + assign fatal_alert_o = intg_err || fsm_err; + assign recov_alert_o = 1'b0; + + assign test_vect_o = '0; + assign test_status_o = '0; + + //////////////////////////////////// + // TL-UL Test Interface Emulation // + //////////////////////////////////// + + otp_ctrl_reg_pkg::otp_ctrl_prim_reg2hw_t reg2hw; + otp_ctrl_reg_pkg::otp_ctrl_prim_hw2reg_t hw2reg; + otp_ctrl_prim_reg_top u_reg_top ( + .clk_i, + .rst_ni, + .tl_i (test_tl_i ), + .tl_o (test_tl_o ), + .reg2hw (reg2hw ), + .hw2reg (hw2reg ), + .intg_err_o(intg_err ) + ); + + logic unused_reg_sig; + assign unused_reg_sig = ^reg2hw; + assign hw2reg = '0; + + /////////////////// + // Control logic // + /////////////////// + + // Encoding generated with: + // $ ./util/design/sparse-fsm-encode.py -d 5 -m 9 -n 10 \ + // -s 2599950981 --language=sv + // + // Hamming distance histogram: + // + // 0: -- + // 1: -- + // 2: -- + // 3: -- + // 4: -- + // 5: |||||||||||||||||||| (52.78%) + // 6: ||||||||||||||| (41.67%) + // 7: | (2.78%) + // 8: | (2.78%) + // 9: -- + // 10: -- + // + // Minimum Hamming distance: 5 + // Maximum Hamming distance: 8 + // Minimum Hamming weight: 3 + // Maximum Hamming weight: 8 + // + localparam int StateWidth = 10; + typedef enum logic [StateWidth-1:0] { + ResetSt = 10'b1100000110, + InitSt = 10'b1000110011, + IdleSt = 10'b0101110000, + ReadSt = 10'b0010011111, + ReadWaitSt = 10'b1001001101, + WriteCheckSt = 10'b1111101011, + WriteWaitSt = 10'b0011000010, + WriteSt = 10'b0110100101, + ErrorSt = 10'b1110011000 + } state_e; + + state_e state_d, state_q; + err_e err_d, err_q; + logic valid_d, valid_q; + logic integrity_en_d, integrity_en_q; + logic req, wren, rvalid; + logic [1:0] rerror; + logic [AddrWidth-1:0] addr_q; + logic [SizeWidth-1:0] size_q; + logic [SizeWidth-1:0] cnt_d, cnt_q; + logic cnt_clr, cnt_en; + logic read_ecc_on, write_ecc_on; + logic wdata_inconsistent; + + + assign cnt_d = (cnt_clr) ? '0 : + (cnt_en) ? cnt_q + 1'b1 : cnt_q; + + assign valid_o = valid_q; + assign err_o = err_q; + + always_comb begin : p_fsm + // Default + state_d = state_q; + ready_o = 1'b0; + valid_d = 1'b0; + err_d = err_q; + req = 1'b0; + wren = 1'b0; + cnt_clr = 1'b0; + cnt_en = 1'b0; + read_ecc_on = 1'b1; + write_ecc_on = 1'b1; + fsm_err = 1'b0; + integrity_en_d = integrity_en_q; + + unique case (state_q) + // Wait here until we receive an initialization command. + ResetSt: begin + err_d = NoError; + ready_o = 1'b1; + if (valid_i) begin + if (cmd_i == Init) begin + state_d = InitSt; + end + end + end + // Wait for some time until the OTP macro is ready. + InitSt: begin + state_d = IdleSt; + valid_d = 1'b1; + err_d = NoError; + end + // In the idle state, we basically wait for read or write commands. + IdleSt: begin + ready_o = 1'b1; + err_d = NoError; + if (valid_i) begin + cnt_clr = 1'b1; + err_d = NoError; + unique case (cmd_i) + Read: begin + state_d = ReadSt; + integrity_en_d = 1'b1; + end + Write: begin + state_d = WriteCheckSt; + integrity_en_d = 1'b1; + end + ReadRaw: begin + state_d = ReadSt; + integrity_en_d = 1'b0; + end + WriteRaw: begin + state_d = WriteCheckSt; + integrity_en_d = 1'b0; + end + default: ; + endcase // cmd_i + end + end + // Issue a read command to the macro. + ReadSt: begin + state_d = ReadWaitSt; + req = 1'b1; + // Suppress ECC correction if needed. + read_ecc_on = integrity_en_q; + end + // Wait for response from macro. + ReadWaitSt: begin + // Suppress ECC correction if needed. + read_ecc_on = integrity_en_q; + if (rvalid) begin + cnt_en = 1'b1; + // Uncorrectable error, bail out. + if (rerror[1] && integrity_en_q) begin + state_d = IdleSt; + valid_d = 1'b1; + err_d = MacroEccUncorrError; + end else begin + if (cnt_q == size_q) begin + state_d = IdleSt; + valid_d = 1'b1; + end else begin + state_d = ReadSt; + end + // Correctable error, carry on but signal back. + if (rerror[0] && integrity_en_q) begin + err_d = MacroEccCorrError; + end + end + end + end + // First, read out to perform the write blank check and + // read-modify-write operation. + WriteCheckSt: begin + state_d = WriteWaitSt; + req = 1'b1; + // Register raw memory contents without correction so that we can + // perform the read-modify-write correctly. + read_ecc_on = 1'b0; + end + // Wait for readout to complete first. + WriteWaitSt: begin + // Register raw memory contents without correction so that we can + // perform the read-modify-write correctly. + read_ecc_on = 1'b0; + if (rvalid) begin + cnt_en = 1'b1; + + if (cnt_q == size_q) begin + cnt_clr = 1'b1; + state_d = WriteSt; + end else begin + state_d = WriteCheckSt; + end + end + end + // If the write data attempts to clear an already programmed bit, + // the MacroWriteBlankError needs to be asserted. + WriteSt: begin + req = 1'b1; + wren = 1'b1; + cnt_en = 1'b1; + // Suppress ECC calculation if needed. + write_ecc_on = integrity_en_q; + + if (wdata_inconsistent) begin + err_d = MacroWriteBlankError; + end + + if (cnt_q == size_q) begin + valid_d = 1'b1; + state_d = IdleSt; + end + end + // If the FSM is glitched into an invalid state. + ErrorSt: begin + fsm_err = 1'b1; + end + default: begin + state_d = ErrorSt; + fsm_err = 1'b1; + end + endcase // state_q + end + + /////////////////////////////////////////// + // Emulate using ECC protected Block RAM // + /////////////////////////////////////////// + + logic [AddrWidth-1:0] addr; + assign addr = addr_q + AddrWidth'(cnt_q); + + logic [Width-1:0] rdata_corr; + logic [Width+EccWidth-1:0] rdata_d, wdata_ecc, rdata_ecc, wdata_rmw; + logic [2**SizeWidth-1:0][Width-1:0] wdata_q, rdata_reshaped; + logic [2**SizeWidth-1:0][Width+EccWidth-1:0] rdata_q; + + // Use a standard Hamming ECC for OTP. + caliptra_prim_secded_hamming_22_16_enc u_enc ( + .data_i(wdata_q[cnt_q]), + .data_o(wdata_ecc) + ); + + caliptra_prim_secded_hamming_22_16_dec u_dec ( + .data_i (rdata_ecc), + .data_o (rdata_corr), + .syndrome_o ( ), + .err_o (rerror) + ); + + assign rdata_d = (read_ecc_on) ? {{EccWidth{1'b0}}, rdata_corr} + : rdata_ecc; + + // Read-modify-write (OTP can only set bits to 1, but not clear to 0). + assign wdata_rmw = (write_ecc_on) ? wdata_ecc | rdata_q[cnt_q] + : {{EccWidth{1'b0}}, wdata_q[cnt_q]} | rdata_q[cnt_q]; + + // This indicates if the write data is inconsistent (i.e., if the operation attempts to + // clear an already programmed bit to zero). + assign wdata_inconsistent = (rdata_q[cnt_q] & wdata_ecc) != rdata_q[cnt_q]; + + // Output data without ECC bits. + always_comb begin : p_output_map + for (int k = 0; k < 2**SizeWidth; k++) begin + rdata_reshaped[k] = rdata_q[k][Width-1:0]; + end + rdata_o = rdata_reshaped; + end + + caliptra_prim_ram_1p_adv #( + .Depth (Depth), + .Width (Width + EccWidth), + .MemInitFile (MemInitFile), + .EnableInputPipeline (1), + .EnableOutputPipeline (1) + ) u_prim_ram_1p_adv ( + .clk_i, + .rst_ni, + .req_i ( req ), + .write_i ( wren ), + .addr_i ( addr ), + .wdata_i ( wdata_rmw ), + .wmask_i ( {Width+EccWidth{1'b1}} ), + .rdata_o ( rdata_ecc ), + .rvalid_o ( rvalid ), + .rerror_o ( ), + .cfg_i ( '0 ) + ); + + + + // Currently it is assumed that no wrap arounds can occur. + `CALIPTRA_ASSERT(NoWrapArounds_A, req |-> (addr >= addr_q)) + + ////////// + // Regs // + ////////// + + `CALIPTRA_PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt) + + always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs + if (!rst_ni) begin + valid_q <= '0; + err_q <= NoError; + addr_q <= '0; + wdata_q <= '0; + rdata_q <= '0; + cnt_q <= '0; + size_q <= '0; + integrity_en_q <= 1'b0; + end else begin + valid_q <= valid_d; + err_q <= err_d; + cnt_q <= cnt_d; + integrity_en_q <= integrity_en_d; + if (ready_o && valid_i) begin + addr_q <= addr_i; + wdata_q <= wdata_i; + size_q <= size_i; + end + if (rvalid) begin + rdata_q[cnt_q] <= rdata_d; + end + end + end + + //////////////// + // Assertions // + //////////////// + + // Check that the otp_ctrl FSMs only issue legal commands to the wrapper. + `CALIPTRA_ASSERT(CheckCommands0_A, state_q == ResetSt && valid_i && ready_o |-> cmd_i == Init) + `CALIPTRA_ASSERT(CheckCommands1_A, state_q != ResetSt && valid_i && ready_o + |-> cmd_i inside {Read, ReadRaw, Write, WriteRaw}) + + +endmodule : prim_generic_otp diff --git a/src/fuse_ctrl/stimulus/tests/directed/fuse_ctrl_sign_of_life_test.yml b/src/fuse_ctrl/stimulus/tests/directed/fuse_ctrl_sign_of_life_test.yml new file mode 100644 index 0000000..1f1ca99 --- /dev/null +++ b/src/fuse_ctrl/stimulus/tests/directed/fuse_ctrl_sign_of_life_test.yml @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +--- +testname: fuse_ctrl_sign_of_life_test +seed: 1 \ No newline at end of file diff --git a/src/fuse_ctrl/tb/otp_ctrl_if.sv b/src/fuse_ctrl/tb/otp_ctrl_if.sv new file mode 100755 index 0000000..febedfe --- /dev/null +++ b/src/fuse_ctrl/tb/otp_ctrl_if.sv @@ -0,0 +1,327 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// DO NOT EDIT THIS FILE DIRECTLY. +// It has been generated with ./util/design/gen-otp-mmap.py + +// This interface collect the broadcast output data from OTP, +// and drive input requests coming into OTP. +`define ECC_REG_PATH gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec + +// This only supports buffered partitions. +`define BUF_PART_OTP_CMD_PATH(i) \ + tb.dut.gen_partitions[``i``].gen_buffered.u_part_buf.otp_cmd_o + +`define LC_PART_OTP_CMD_PATH \ + tb.dut.gen_partitions[LifeCycleIdx].gen_lifecycle.u_part_buf.otp_cmd_o + +`define FORCE_OTP_PART_LOCK_WITH_RAND_NON_MUBI_VAL(i) \ + if (forced_part_access_sel[``i``].read_lock) begin \ + force tb.dut.part_access[``i``].read_lock = get_rand_mubi8_val(.t_weight(0), .f_weight(0)); \ + force tb.dut.part_access_dai[``i``].read_lock = get_rand_mubi8_val(.t_weight(0), .f_weight(0)); \ + end \ + if (forced_part_access_sel[``i``].write_lock) begin \ + force tb.dut.part_access[``i``].write_lock = get_rand_mubi8_val(.t_weight(0), .f_weight(0)); \ + force tb.dut.part_access_dai[``i``].write_lock = get_rand_mubi8_val(.t_weight(0), .f_weight(0)); \ + end + +`ifndef PRIM_GENERIC_OTP_PATH + `define PRIM_GENERIC_OTP_PATH\ + tb.dut.u_otp +`endif + +`ifndef PRIM_GENERIC_OTP_CMD_I_PATH + `define PRIM_GENERIC_OTP_CMD_I_PATH \ + `PRIM_GENERIC_OTP_PATH.gen_generic.u_impl_generic.cmd_i +`endif + +interface otp_ctrl_if(input clk_i, input rst_ni); + import uvm_pkg::*; + import otp_ctrl_env_pkg::*; + import otp_ctrl_pkg::*; + import otp_ctrl_reg_pkg::*; + import otp_ctrl_part_pkg::*; + import cip_base_pkg::*; + + // Output from DUT + otp_broadcast_t otp_broadcast_o; + otp_keymgr_key_t keymgr_key_o; + otp_lc_data_t lc_data_o; + logic pwr_otp_done_o, pwr_otp_idle_o; + + // Inputs to DUT + logic pwr_otp_init_i, scan_en_i, scan_rst_ni, ext_voltage_h_io; + lc_ctrl_pkg::lc_tx_t lc_dft_en_i, lc_escalate_en_i, lc_check_byp_en_i, + lc_creator_seed_sw_rw_en_i, lc_owner_seed_sw_rw_en_i, + lc_seed_hw_rd_en_i; + prim_mubi_pkg::mubi4_t scanmode_i; + otp_ast_rsp_t otp_ast_pwr_seq_h_i; + ast_pkg::ast_obs_ctrl_t obs_ctrl_i; + + // Unused in prim_generic_otp memory. + logic [OtpTestCtrlWidth-1:0] otp_vendor_test_ctrl_i; + logic [OtpTestStatusWidth-1:0] otp_vendor_test_status_o; + logic [OtpTestVectWidth-1:0] cio_test_o; + logic [OtpTestVectWidth-1:0] cio_test_en_o; + + // Connect with lc_prog push_pull interface. + logic lc_prog_req, lc_prog_err; + logic lc_prog_err_dly1, lc_prog_no_sta_check; + + // Connect push_pull interfaces ack signals for assertion checks. + logic otbn_ack, lc_prog_ack; + logic [1:0] flash_acks; + logic [NumSramKeyReqSlots-1:0] sram_acks; + + // Variables for internal interface logic. + // `lc_escalate_en` is async, take two clock cycles to synchronize. + lc_ctrl_pkg::lc_tx_t lc_esc_dly1, lc_esc_dly2; + + // Variable for scoreboard. + // For `lc_escalate_en`, any value that is not `Off` is a `On`. + bit lc_esc_on; + + // Probe design signal for alert request. + logic alert_reqs; + + // Usually the `lc_check_byp_en` will be automatically set to `On` when LC program request is + // issued, and stays `On` until reset is issued. + // Set this variable to 0 after a LC program request might cause otp checks to fail. + bit lc_check_byp_en = 1; + + // Internal veriable to track which sw partitions have ECC reg error. + bit [NumPartUnbuf-1:0] force_sw_parts_ecc_reg; + + // DUT configuration object + otp_ctrl_ast_inputs_cfg dut_cfg; + + // for DV macros ID + string msg_id = "otp_ctrl_if"; + + // Lc_err could trigger during LC program, so check intr and status after lc_req is finished. + // Lc_err takes one clock cycle to propogate to intr signal. So avoid intr check if it happens + // during the transition. + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + lc_prog_err_dly1 <= 0; + lc_esc_dly1 <= lc_ctrl_pkg::Off; + lc_esc_dly2 <= lc_ctrl_pkg::Off; + lc_check_byp_en_i <= get_rand_lc_tx_val(); + lc_esc_on <= 0; + end else begin + lc_prog_err_dly1 <= lc_prog_err; + lc_esc_dly1 <= lc_escalate_en_i; + lc_esc_dly2 <= lc_esc_dly1; + if (lc_prog_req) begin + lc_check_byp_en_i <= lc_check_byp_en ? lc_ctrl_pkg::On : lc_ctrl_pkg::Off; + end + if (lc_esc_dly2 != lc_ctrl_pkg::Off && !lc_esc_on) begin + lc_esc_on <= 1; + end + end + end + + assign lc_prog_no_sta_check = lc_prog_err | lc_prog_err_dly1 | lc_prog_req | lc_esc_on; + + function automatic void drive_pwr_otp_init(logic val); + pwr_otp_init_i = val; + endfunction + + function automatic void drive_ext_voltage_h_io(logic val); + ext_voltage_h_io = val; + endfunction + + function automatic void drive_lc_creator_seed_sw_rw_en(lc_ctrl_pkg::lc_tx_t val); + lc_creator_seed_sw_rw_en_i = val; + endfunction + + function automatic void drive_lc_owner_seed_sw_rw_en(lc_ctrl_pkg::lc_tx_t val); + lc_owner_seed_sw_rw_en_i = val; + endfunction + + function automatic void drive_lc_dft_en(lc_ctrl_pkg::lc_tx_t val); + lc_dft_en_i = val; + endfunction + + function automatic void drive_lc_escalate_en(lc_ctrl_pkg::lc_tx_t val); + lc_escalate_en_i = val; + endfunction + + function automatic void drive_lc_seed_hw_rd_en(lc_ctrl_pkg::lc_tx_t val); + lc_seed_hw_rd_en_i = val; + endfunction + + function automatic bit under_error_states(); + return lc_esc_on | alert_reqs; + endfunction + + // SW partitions do not have any internal checks. + // Here we force internal ECC check to fail. + task automatic force_sw_check_fail( + bit[NumPartUnbuf-1:0] fail_idx = $urandom_range(1, (1'b1 << NumPartUnbuf) - 1)); + @(posedge clk_i); + if (fail_idx[VendorTestIdx]) begin + force tb.dut.gen_partitions[VendorTestIdx].gen_unbuffered. + u_part_unbuf.`ECC_REG_PATH.data_i[0] = 1; + force_sw_parts_ecc_reg[VendorTestIdx] = 1; + end + if (fail_idx[NonSecretFusesIdx]) begin + force tb.dut.gen_partitions[NonSecretFusesIdx].gen_unbuffered. + u_part_unbuf.`ECC_REG_PATH.data_i[0] = 1; + force_sw_parts_ecc_reg[NonSecretFusesIdx] = 1; + end + endtask + + task automatic release_sw_check_fail(); + @(posedge clk_i); + if (force_sw_parts_ecc_reg[VendorTestIdx]) begin + release tb.dut.gen_partitions[VendorTestIdx].gen_unbuffered. + u_part_unbuf.`ECC_REG_PATH.data_i[0]; + force_sw_parts_ecc_reg[VendorTestIdx] = 0; + end + if (force_sw_parts_ecc_reg[NonSecretFusesIdx]) begin + release tb.dut.gen_partitions[NonSecretFusesIdx].gen_unbuffered. + u_part_unbuf.`ECC_REG_PATH.data_i[0]; + force_sw_parts_ecc_reg[NonSecretFusesIdx] = 0; + end + endtask + + // Force prim_generic_otp input cmd_i to a invalid value. + task automatic force_invalid_otp_cmd_i(); + @(posedge clk_i); + force `PRIM_GENERIC_OTP_CMD_I_PATH = prim_otp_pkg::cmd_e'(2'b10); + endtask + + task automatic release_invalid_otp_cmd_i(); + @(posedge clk_i); + release `PRIM_GENERIC_OTP_CMD_I_PATH; + endtask + + // Force part_buf partitions output otp_cmd_o to a invalid value. + task automatic force_invalid_part_cmd_o(int part_idx); + @(posedge clk_i); + case (part_idx) + Secret0Idx: force `BUF_PART_OTP_CMD_PATH(Secret0Idx) = prim_otp_pkg::cmd_e'(2'b10); + Secret1Idx: force `BUF_PART_OTP_CMD_PATH(Secret1Idx) = prim_otp_pkg::cmd_e'(2'b10); + LifeCycleIdx: force `LC_PART_OTP_CMD_PATH = prim_otp_pkg::cmd_e'(2'b10); + default: begin + `uvm_fatal("otp_ctrl_if", + $sformatf("force invalid otp_cmd_o only supports buffered partitions: %0d", part_idx)) + end + endcase + endtask + + task automatic release_invalid_part_cmd_o(int part_idx); + @(posedge clk_i); + case (part_idx) + Secret0Idx: release `BUF_PART_OTP_CMD_PATH(Secret0Idx); + Secret1Idx: release `BUF_PART_OTP_CMD_PATH(Secret1Idx); + LifeCycleIdx: release `LC_PART_OTP_CMD_PATH; + default: begin + `uvm_fatal("otp_ctrl_if", + $sformatf("release invalid otp_cmd_o only supports buffered partitions: %0d", + part_idx)) + end + endcase + endtask + + // This task forces otp_ctrl's internal mubi signals to values that are not mubi::true or mubi:: + // false. Then scb will check if design treats these values as locking the partition access. + task automatic force_part_access_mubi(otp_part_access_lock_t forced_part_access_sel[NumPart-1]); + @(posedge clk_i); + `FORCE_OTP_PART_LOCK_WITH_RAND_NON_MUBI_VAL(VendorTestIdx) + `FORCE_OTP_PART_LOCK_WITH_RAND_NON_MUBI_VAL(NonSecretFusesIdx) + `FORCE_OTP_PART_LOCK_WITH_RAND_NON_MUBI_VAL(Secret0Idx) + `FORCE_OTP_PART_LOCK_WITH_RAND_NON_MUBI_VAL(Secret1Idx) + endtask + + task automatic release_part_access_mubi(); + @(posedge clk_i); + release tb.dut.part_access; + release tb.dut.part_access_dai; + endtask + + // Connectivity assertions for test related I/Os. + `ASSERT(LcOtpTestStatusO_A, otp_vendor_test_status_o == `PRIM_GENERIC_OTP_PATH.test_status_o) + `ASSERT(LcOtpTestCtrlI_A, otp_vendor_test_ctrl_i == `PRIM_GENERIC_OTP_PATH.test_ctrl_i) + + `ASSERT(CioTestOWithDftOn_A, lc_dft_en_i == lc_ctrl_pkg::On |-> + ##[2:3] cio_test_o == `PRIM_GENERIC_OTP_PATH.test_vect_o) + `ASSERT(CioTestOWithDftOff_A, lc_dft_en_i != lc_ctrl_pkg::On |-> ##[2:3] cio_test_o == 0) + `ASSERT(CioTestEnOWithDftOn_A, lc_dft_en_i == lc_ctrl_pkg::On |-> ##[2:3] cio_test_en_o == '1) + `ASSERT(CioTestEnOWithDftOff_A, lc_dft_en_i != lc_ctrl_pkg::On |-> ##[2:3] cio_test_en_o == 0) + + + `define OTP_ASSERT_WO_LC_ESC(NAME, SEQ) \ + `ASSERT(NAME, SEQ, clk_i, !rst_ni || lc_esc_on || alert_reqs) + + // If pwr_otp_idle is set only if pwr_otp init is done + `OTP_ASSERT_WO_LC_ESC(OtpPwrDoneWhenIdle_A, pwr_otp_idle_o |-> pwr_otp_done_o) + + // otp_broadcast_o is valid only when otp init is done + `OTP_ASSERT_WO_LC_ESC(OtpHwCfgValidOn_A, pwr_otp_done_o |-> + otp_broadcast_o.valid == lc_ctrl_pkg::On) + // If otp_broadcast is Off, then hw partition is not finished calculation, + // then otp init is not done + `OTP_ASSERT_WO_LC_ESC(OtpHwCfgValidOff_A, otp_broadcast_o.valid == lc_ctrl_pkg::Off |-> + pwr_otp_done_o == 0) + // Once OTP init is done, otp_broadcast_o output value stays stable until next power cycle + `OTP_ASSERT_WO_LC_ESC(OtpHwCfgStable_A, otp_broadcast_o.valid == lc_ctrl_pkg::On |=> + $stable(otp_broadcast_o)) + + // Otp_keymgr valid is related to part_digest, should not be changed after otp_pwr_init + `OTP_ASSERT_WO_LC_ESC(OtpKeymgrValidStable0_A, pwr_otp_done_o |-> + $stable(keymgr_key_o.creator_root_key_share0_valid)) + `OTP_ASSERT_WO_LC_ESC(OtpKeymgrValidStable1_A, pwr_otp_done_o |-> + $stable(keymgr_key_o.creator_root_key_share1_valid)) + `OTP_ASSERT_WO_LC_ESC(OtpKeymgrValidStable2_A, pwr_otp_done_o |-> + $stable(keymgr_key_o.creator_seed_valid)) + `OTP_ASSERT_WO_LC_ESC(OtpKeymgrValidStable3_A, pwr_otp_done_o |-> + $stable(keymgr_key_o.owner_seed_valid)) + + // During lc_prog_req, either otp_idle will be reset or lc_error is set + `OTP_ASSERT_WO_LC_ESC(LcProgReq_A, $rose(lc_prog_req) |=> + (pwr_otp_idle_o == 0 || $rose(lc_prog_err)) within lc_prog_req[*1:$]) + + // During fatal alert, check if otp outputs revert back to default value. + // Wait three clock cycles until error propogates to each FSM states and regs. + `define OTP_FATAL_ERR_ASSERT(NAME, SEQ) \ + `ASSERT(FatalErr``NAME``, alert_reqs |-> ##3 SEQ) + + `OTP_FATAL_ERR_ASSERT(LcDataValid_A, lc_data_o.valid == 0 && lc_data_o.error == 1) + `OTP_FATAL_ERR_ASSERT(LcDataState_A, lc_data_o.state == + PartInvDefault[LcStateOffset*8+:LcStateSize*8]) + `OTP_FATAL_ERR_ASSERT(LcDataCount_A, lc_data_o.count == + PartInvDefault[LcTransitionCntOffset*8+:LcTransitionCntSize*8]) + `OTP_FATAL_ERR_ASSERT(LcDataTestUnlockToken_A, lc_data_o.test_unlock_token == + PartInvDefault[TestUnlockTokenOffset*8+:TestUnlockTokenSize*8]) + `OTP_FATAL_ERR_ASSERT(LcDataTestExitToken_A, lc_data_o.test_exit_token == + PartInvDefault[TestExitTokenOffset*8+:TestExitTokenSize*8]) + `OTP_FATAL_ERR_ASSERT(LcDataRmaToken_A, lc_data_o.rma_token == + PartInvDefault[RmaTokenOffset*8+:RmaTokenSize*8]) + + `OTP_FATAL_ERR_ASSERT(KeymgrKeyData_A, keymgr_key_o.creator_root_key_share0 == + PartInvDefault[CreatorRootKeyShare0Offset*8+:CreatorRootKeyShare0Size*8] && + keymgr_key_o.creator_root_key_share1 == + PartInvDefault[CreatorRootKeyShare1Offset*8+:CreatorRootKeyShare1Size*8]) + + `OTP_FATAL_ERR_ASSERT(HwCfgOValid_A, otp_broadcast_o.valid == lc_ctrl_pkg::Off) + `OTP_FATAL_ERR_ASSERT(HwCfg0OData_A, otp_broadcast_o.hw_cfg0_data == + PartInvDefault[HwCfg0Offset*8+:HwCfg0Size*8]) + `OTP_FATAL_ERR_ASSERT(HwCfg1OData_A, otp_broadcast_o.hw_cfg1_data == + PartInvDefault[HwCfg1Offset*8+:HwCfg1Size*8]) + + `OTP_FATAL_ERR_ASSERT(LcProgAck_A, lc_prog_ack == 0) + `OTP_FATAL_ERR_ASSERT(FlashAcks_A, flash_acks == 0) + `OTP_FATAL_ERR_ASSERT(SramAcks_A, sram_acks == 0) + `OTP_FATAL_ERR_ASSERT(OtbnAck_A, otbn_ack == 0) + + `undef OTP_ASSERT_WO_LC_ESC + `undef OTP_FATAL_ERR_ASSERT + `undef ECC_REG_PATH + `undef BUF_PART_OTP_CMD_PATH + `undef LC_PART_OTP_CMD_PATH + `undef PRIM_GENERIC_OTP_PATH + `undef PRIM_GENERIC_OTP_CMD_I_PATH + `undef FORCE_OTP_PART_LOCK_WITH_RAND_NON_MUBI_VAL +endinterface diff --git a/src/fuse_ctrl/tb/otp_ctrl_top_tb.sv b/src/fuse_ctrl/tb/otp_ctrl_top_tb.sv new file mode 100644 index 0000000..1df653d --- /dev/null +++ b/src/fuse_ctrl/tb/otp_ctrl_top_tb.sv @@ -0,0 +1,589 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// + + +// ------------------------------------------------------------------------- +// FUSE CTRL Testbench for basic/initial testing +// ------------------------------------------------------------------------- + +module otp_ctrl_top_tb + import axi_pkg::*; + import caliptra_otp_ctrl_pkg::*; + import caliptra_otp_ctrl_reg_pkg::*; + import caliptra_otp_ctrl_part_pkg::*; + import otp_ctrl_top_tb_pkg::*; + ( + `ifdef VERILATOR + input bit clk_tb + `endif + ); + + //---------------------------------------------------------------- + // Internal constant and parameter definitions. + //---------------------------------------------------------------- + parameter DEBUG = 0; + + parameter CLK_HALF_PERIOD = 2; + + parameter MemInitFile = "/home/ws/caliptra/anjpar/ws1/chipsalliance/caliptra-rtl/src/fuse_ctrl/data/otp-img.2048.vmem"; + + //---------------------------------------------------------------- + // Register and Wire declarations. + //---------------------------------------------------------------- + reg [31 : 0] cycle_ctr; + reg [31 : 0] error_ctr; + reg [31 : 0] tc_ctr; + + `ifndef VERILATOR + reg clk_tb; + `endif + reg reset_n_tb; + + logic edn_clk; + logic edn_rst_n; + + edn_pkg::edn_req_t edn_o; + edn_pkg::edn_rsp_t edn_i; + + logic intr_otp_operation_done; + logic intr_otp_error; + + caliptra_prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i; + caliptra_prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o; + // Observability to AST + ast_pkg::ast_obs_ctrl_t obs_ctrl_i; + logic [7:0] otp_obs_o; + // Macro-specific power sequencing signals to/from AST. + otp_ast_req_t otp_ast_pwr_seq_o; + otp_ast_rsp_t otp_ast_pwr_seq_h_i; + // Power manager interface (inputs are synced to OTP clock domain) + //pwrmgr_pkg::pwr_otp_req_t pwr_otp_i; + logic pwr_otp_init_i; + pwrmgr_pkg::pwr_otp_rsp_t pwr_otp_o; + // Macro-specific test registers going to lifecycle TAP + lc_otp_vendor_test_req_t lc_otp_vendor_test_i; + lc_otp_vendor_test_rsp_t lc_otp_vendor_test_o; + // Lifecycle transition command interface + lc_otp_program_req_t lc_otp_program_i; + lc_otp_program_rsp_t lc_otp_program_o; + // Lifecycle broadcast inputs + // SEC_CM: LC_CTRL.INTERSIG.MUBI + + //lc_ctrl_pkg::lc_tx_t lc_creator_seed_sw_rw_en_i; + //lc_ctrl_pkg::lc_tx_t lc_owner_seed_sw_rw_en_i; + //lc_ctrl_pkg::lc_tx_t lc_seed_hw_rd_en_i; + lc_ctrl_pkg::lc_tx_t lc_dft_en_i; + lc_ctrl_pkg::lc_tx_t lc_escalate_en_i; + lc_ctrl_pkg::lc_tx_t lc_check_byp_en_i; + + otp_lc_data_t otp_lc_data_o; + otp_broadcast_t otp_broadcast_o; + wire otp_ext_voltage_h_io; + logic scan_en_i; + logic scan_rst_ni; + caliptra_prim_mubi_pkg::mubi4_t scanmode_i; + logic [OtpTestVectWidth-1:0] cio_test_o; + logic [OtpTestVectWidth-1:0] cio_test_en_o; + + localparam ADDR_WIDTH = 32; + localparam DATA_WIDTH = 32; + localparam USER_WIDTH = 32; + localparam ID_WIDTH = 1; + + // Register offsets for core interface + parameter int CoreAw = 13; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_INTR_STATE_OFFSET = 13'h 0; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_INTR_ENABLE_OFFSET = 13'h 4; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_INTR_TEST_OFFSET = 13'h 8; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_ALERT_TEST_OFFSET = 13'h c; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_STATUS_OFFSET = 13'h 10; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_ERR_CODE_0_OFFSET = 13'h 14; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_ERR_CODE_1_OFFSET = 13'h 18; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_ERR_CODE_2_OFFSET = 13'h 1c; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_ERR_CODE_3_OFFSET = 13'h 20; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_ERR_CODE_4_OFFSET = 13'h 24; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_ERR_CODE_5_OFFSET = 13'h 28; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_ERR_CODE_6_OFFSET = 13'h 2c; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_ERR_CODE_7_OFFSET = 13'h 30; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_ERR_CODE_8_OFFSET = 13'h 34; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET = 13'h 38; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET = 13'h 3c; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET = 13'h 40; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET = 13'h 44; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET = 13'h 48; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET = 13'h 4c; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET = 13'h 50; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET = 13'h 54; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_CHECK_TRIGGER_OFFSET = 13'h 58; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_CHECK_REGWEN_OFFSET = 13'h 5c; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_CHECK_TIMEOUT_OFFSET = 13'h 60; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET = 13'h 64; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET = 13'h 68; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET = 13'h 6c; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_NON_SECRET_FUSES_READ_LOCK_OFFSET = 13'h 70; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET = 13'h 74; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET = 13'h 78; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_NON_SECRET_FUSES_DIGEST_0_OFFSET = 13'h 7c; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_NON_SECRET_FUSES_DIGEST_1_OFFSET = 13'h 80; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_SECRET0_DIGEST_0_OFFSET = 13'h 84; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_SECRET0_DIGEST_1_OFFSET = 13'h 88; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_SECRET1_DIGEST_0_OFFSET = 13'h 8c; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_SECRET1_DIGEST_1_OFFSET = 13'h 90; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_SECRET2_DIGEST_0_OFFSET = 13'h 94; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_SECRET2_DIGEST_1_OFFSET = 13'h 98; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_SECRET3_DIGEST_0_OFFSET = 13'h 9c; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_SECRET3_DIGEST_1_OFFSET = 13'h a0; + + // AXI Core Interface + axi_if #( + .AW (ADDR_WIDTH), + .DW (DATA_WIDTH), + .IW (ID_WIDTH), + .UW (USER_WIDTH) + ) axi_core_if ( + .clk (clk_tb), + .rst_n (reset_n_tb) + ); + + // AXI Prim Interface + axi_if #( + .AW (ADDR_WIDTH), + .DW (DATA_WIDTH), + .IW (ID_WIDTH), + .UW (USER_WIDTH) + ) axi_prim_if ( + .clk (clk_tb), + .rst_n (reset_n_tb) + ); + + // AXI Secret Reg Interface + axi_if #( + .AW (ADDR_WIDTH), + .DW (DATA_WIDTH), + .IW (ID_WIDTH), + .UW (USER_WIDTH) + ) axi_secreg_if ( + .clk (clk_tb), + .rst_n (reset_n_tb) + ); + + // dut + otp_ctrl_top #( + .MemInitFile (MemInitFile) + ) dut ( + .clk_i (clk_tb ), + .rst_ni (reset_n_tb ), + // edn + .clk_edn_i (edn_clk ), + .rst_edn_ni (edn_rst_n ), + .edn_o (edn_o), //(edn_if[0].req ), + .edn_i (edn_i), //({edn_if[0].ack, edn_if[0].d_data}), + // AXI interface + .s_core_axi_r_if (axi_core_if.r_sub), + .s_core_axi_w_if (axi_core_if.w_sub), + .s_prim_axi_r_if (axi_prim_if.r_sub), + .s_prim_axi_w_if (axi_prim_if.w_sub), + .s_secreg_axi_r_if (axi_secreg_if.r_sub), + // interrupt + .intr_otp_operation_done_o (intr_otp_operation_done), + .intr_otp_error_o (intr_otp_error), + // alert + .alert_rx_i (alert_rx_i ), //(alert_rx parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_ALERT_TEST_OFFSET = 13'h c; + .alert_tx_o (alert_tx_o ), //(alert_tx ), + // ast + .obs_ctrl_i (obs_ctrl_i), //(otp_ctrl_if.obs_ctrl_i), + .otp_obs_o (otp_obs_o), + .otp_ast_pwr_seq_o (otp_ast_pwr_seq_o), //(ast_req), + .otp_ast_pwr_seq_h_i (otp_ast_pwr_seq_h_i), //(otp_ctrl_if.otp_ast_pwr_seq_h_i), + // pwrmgr + .pwr_otp_i (pwr_otp_init_i), //(otp_ctrl_if.pwr_otp_init_i), + .pwr_otp_o (pwr_otp_o), //({otp_ctrl_if.pwr_otp_done_o, otp_ctrl_if.pwr_otp_idle_o}), + // lc + .lc_otp_vendor_test_i (lc_otp_vendor_test_i), //(otp_ctrl_if.otp_vendor_test_ctrl_i), + .lc_otp_vendor_test_o (lc_otp_vendor_test_o), //(otp_ctrl_if.otp_vendor_test_status_o), + .lc_otp_program_i (lc_otp_program_i), //({lc_prog_if.req, lc_prog_if.h_data}), + .lc_otp_program_o (lc_otp_program_o), //({lc_prog_if.d_data, lc_prog_if.ack}), + //.lc_creator_seed_sw_rw_en_i (lc_creator_seed_sw_rw_en_i), //(otp_ctrl_if.lc_creator_seed_sw_rw_en_i), + //.lc_owner_seed_sw_rw_en_i (lc_owner_seed_sw_rw_en_i), //(otp_ctrl_if.lc_owner_seed_sw_rw_en_i), + //.lc_seed_hw_rd_en_i (lc_seed_hw_rd_en_i), //(otp_ctrl_if.lc_seed_hw_rd_en_i), + .lc_dft_en_i (lc_dft_en_i), //(otp_ctrl_if.lc_dft_en_i), + .lc_escalate_en_i (lc_escalate_en_i), //(otp_ctrl_if.lc_escalate_en_i), + .lc_check_byp_en_i (lc_check_byp_en_i), //(otp_ctrl_if.lc_check_byp_en_i), + .otp_lc_data_o (otp_lc_data_o), //(otp_ctrl_if.lc_data_o), + + + .otp_broadcast_o (otp_broadcast_o), //(otp_ctrl_if.otp_broadcast_o), + .otp_ext_voltage_h_io (otp_ext_voltage_h_io), + + //scan + .scan_en_i (scan_en_i), //(otp_ctrl_if.scan_en_i), + .scan_rst_ni (scan_rst_ni), //(otp_ctrl_if.scan_rst_ni), + .scanmode_i (scanmode_i), //(otp_ctrl_if.scanmode_i), + + // Test-related GPIO output + .cio_test_o (cio_test_o), //(otp_ctrl_if.cio_test_o), + .cio_test_en_o (cio_test_en_o) //(otp_ctrl_if.cio_test_en_o) + ); + + //---------------------------------------------------------------- + // clk_gen + // + // Clock generator process. + //---------------------------------------------------------------- + `ifndef VERILATOR + always + begin : clk_gen + #CLK_HALF_PERIOD + clk_tb = !clk_tb; + end // clk_gen + `endif + + //---------------------------------------------------------------- + // sys_monitor + // + // Generates a cycle counter and displays information about + // the dut as needed. + //---------------------------------------------------------------- + always @(posedge clk_tb) begin : sys_monitor + cycle_ctr = (!reset_n_tb) ? 32'h0 : cycle_ctr + 1; + end + + //---------------------------------------------------------------- + // reset_dut() + // + // Toggles reset to force the DUT into a well defined state. + //---------------------------------------------------------------- + task reset_dut; + begin + $display("*** Toggle reset."); + reset_n_tb = 0; + + repeat (2) @(posedge clk_tb); + reset_n_tb = 1; + + repeat (2) @(posedge clk_tb); + + $display(""); + end + endtask // reset_dut + + //---------------------------------------------------------------- + // init_sim() + // + // Initialize all counters and testbed functionality as well + // as setting the DUT inputs to defined values. + //---------------------------------------------------------------- + task init_sim; + begin + `ifndef VERILATOR + clk_tb = 0; + `endif + reset_n_tb = 1; + + axi_core_if.araddr = '0; + axi_core_if.arburst = '0; + axi_core_if.arlen = '0; + axi_core_if.arlock = 0; + axi_core_if.arsize = '0; + axi_core_if.arid = 0; + axi_core_if.aruser = '0; + axi_core_if.arvalid = 0; + axi_core_if.rready = 0; + + axi_core_if.awaddr = '0; + axi_core_if.awid = '0; + axi_core_if.awburst = '0; + axi_core_if.awlen = '0; + axi_core_if.awlock = 0; + axi_core_if.awsize = '0; + axi_core_if.awuser = '0; + axi_core_if.awvalid = 0; + axi_core_if.wdata = '0; + axi_core_if.wvalid = 0; + axi_core_if.wlast = 0; + axi_core_if.wstrb = '0; + axi_core_if.bready = 0; + + axi_prim_if.araddr = '0; + axi_prim_if.arburst = '0; + axi_prim_if.arlen = '0; + axi_prim_if.arlock = 0; + axi_prim_if.arsize = '0; + axi_prim_if.arid = 0; + axi_prim_if.aruser = '0; + axi_prim_if.arvalid = 0; + axi_prim_if.rready = 0; + + axi_prim_if.awaddr = '0; + axi_prim_if.awid = '0; + axi_prim_if.awburst = '0; + axi_prim_if.awlen = '0; + axi_prim_if.awlock = 0; + axi_prim_if.awsize = '0; + axi_prim_if.awuser = '0; + axi_prim_if.awvalid = 0; + axi_prim_if.wdata = '0; + axi_prim_if.wvalid = 0; + axi_prim_if.wlast = 0; + axi_prim_if.wstrb = '0; + axi_prim_if.bready = 0; + + axi_secreg_if.araddr = '0; + axi_secreg_if.arburst = '0; + axi_secreg_if.arlen = '0; + axi_secreg_if.arlock = 0; + axi_secreg_if.arsize = '0; + axi_secreg_if.aruser = '0; + axi_secreg_if.arvalid = 0; + axi_secreg_if.rready = 0; + + //lc_creator_seed_sw_rw_en_i = lc_ctrl_pkg::Off;; + //lc_owner_seed_sw_rw_en_i = lc_ctrl_pkg::Off;; + //lc_seed_hw_rd_en_i = lc_ctrl_pkg::Off;; + lc_dft_en_i = lc_ctrl_pkg::Off;; + lc_escalate_en_i = lc_ctrl_pkg::Off;; + lc_check_byp_en_i = lc_ctrl_pkg::Off;; + + pwr_otp_init_i = 0; + end + endtask + + //---------------------------------------------------------------- + // display_test_result() + // + // Display the accumulated test results. + //---------------------------------------------------------------- + task display_test_result; + begin + if (error_ctr == 0) begin + $display("*** All %02d test cases completed successfully.", tc_ctr); + $display("* TESTCASE PASSED"); + end + else begin + $display("*** %02d test cases completed.", tc_ctr); + $display("*** %02d errors detected during testing.", error_ctr); + $display("* TESTCASE FAILED"); + end + end + endtask // display_test_result + + //----------------------------------------------------------------- + // init_parition() + // + // Initialize partitions and wait for initialization complete. + //----------------------------------------------------------------- + task init_partition; + begin + $display("*** TEST: Initialize OTP partitions."); + pwr_otp_init_i = 1; + repeat (5) @(posedge clk_tb); + pwr_otp_init_i = 0; + + while (!otp_lc_data_o.valid) begin + @(posedge clk_tb); + end + + $display("*** TEST PASS - OTP partition initialization complete"); + end + endtask + + //----------------------------------------------------------------- + // read_csr() + // + // Read a CSR over AXI interface (via AXI2TLUL gasket). + //----------------------------------------------------------------- + task read_csr ( + input string csr_name, + input logic [12:0] csr_addr, + input logic [31:0] user, + input logic id + ); + begin + logic [31:0] read_addr; + logic [31:0] read_data; + axi_pkg::axi_resp_e read_rsp; + + $display("*** Read CSR %s", csr_name); + + read_addr = {{19{1'b0}}, csr_addr}; + //user = 32'h00000001; + //id = 1'b1; + $display(" DEBUG: read_addr = 0x%x", read_addr); + axi_core_if.axi_read_single(read_addr, user, id, clk_tb, read_data, read_rsp); + $display("DEBUG: Issued axi read command"); + @(posedge clk_tb); + if (read_rsp == axi_pkg::AXI_RESP_OKAY) begin + $display(" *** TEST PASS: CSR %s = 0x%x\n", csr_name, read_data); + end + else begin + $display(" TEST FAIL: Failed to read CSR %s. Read Response = %s", csr_name, read_rsp); + end + end + endtask + + //----------------------------------------------------------------- + // read_all_csrs() + // + // Read all CSRs back to back CSRs over AXI interface (via AXI2TLUL gasket). + //----------------------------------------------------------------- + task read_all_csrs; + begin + logic [CoreAw-1:0] csr_addr; + string csr_reg_name; + logic [31:0] user; + logic id; + + user = 32'h00000001; + id = 1'b1; + + $display("*** \n\nTEST: Read all CSRs"); + + foreach (csr_registers[i]) begin + csr_reg_name = csr_registers[i]; + csr_addr = get_addr(csr_reg_name); + read_csr(csr_reg_name, csr_addr, user, id); + end + + $display("*** TEST Read all CSRs compelete!!"); + end + endtask + + //---------------------------------------------------------------- + // write_csr() + // + // Write a CSR over AXI itnerface (via AXI2TLUL gasket) + //---------------------------------------------------------------- + task write_csr( + input string csr_name, + input logic [12:0] csr_addr, + input logic [31:0] csr_write_data, + input logic [31:0] user, + input logic id + ); + begin + logic [31:0] write_addr; + logic [31:0] read_data; + axi_pkg::axi_resp_e write_rsp; + axi_pkg::axi_resp_e read_rsp; + write_addr = {{19{1'b0}}, csr_addr}; + $display(" DEBUG: write_addr = 0x%x", write_addr); + axi_core_if.axi_write_single(write_addr, user, id, clk_tb, csr_write_data, write_rsp); + @(posedge clk_tb); + if (write_rsp != AXI_RESP_OKAY) begin + $display("*** FAIL: Write to CSR %s (addr 0x%x) unsuccessful. Response = %s", csr_name, write_addr, write_rsp); + end + read_csr(csr_name, write_addr, user, id); + end + endtask + + //---------------------------------------------------------------- + // write_all_csrs() + // + // Write all CSRs back to back over AXI interface (via AXI2TLUL gasket) + //---------------------------------------------------------------- + task write_all_csrs; + begin + logic [CoreAw-1:0] csr_addr; + string csr_reg_name; + logic [31:0] csr_write_data; + logic [31:0] user; + logic id; + + user = 32'h00000001; + id = 1'b1; + + $display("*** \n\nTEST: Write all CSRs"); + + foreach (csr_registers[i]) begin + csr_reg_name = csr_registers[i]; + csr_addr = get_addr(csr_reg_name); + csr_write_data = $random; + write_csr(csr_reg_name, csr_addr, csr_write_data, user, id); + end + + $display("*** TEST Write all CSRs compelete!!"); + end + endtask + + //---------------------------------------------------------------- + // write_dai_regs() + // + // Write DAI registers over AXI interface (via AXI2TLUL gasket) + //---------------------------------------------------------------- + task write_dai_regs; + begin + logic [CoreAw-1:0] csr_addr; + string cur_dai_reg; + logic [31:0] user; + logic id; + logic [31:0] write_data; + strq_t dai_regs; + axi_resp_e write_rsp; + $display("*** TEST: Write to DAI registers"); + + dai_regs = get_dai_regnames(); + + // Write to DAI WDATA_0 register + foreach (dai_regs[i]) begin + cur_dai_reg = dai_regs[i]; + if (str_find(cur_dai_reg, "WDATA_0")) + break; + end + csr_addr = get_addr(cur_dai_reg); + write_data = 32'h11223344; // reset value is 0x1; Write 0 to clear + user = 32'h1; + id = 1'b1; + write_csr(cur_dai_reg, csr_addr, write_data, user, id); + + end + endtask + + + //---------------------------------------------------------------- + // The main test functionality. + //---------------------------------------------------------------- + initial begin : main + fork + begin + $display(" -- Testbench for fuse_ctrl started. --"); + + init_sim(); + reset_dut(); + + init_partition(); + read_all_csrs(); + write_all_csrs(); + //write_dai_regs(); + + $display(" -- Testbench for fuse_ctrl done. --"); + $finish; + end + + begin + repeat (100000) @(posedge clk_tb); + $display("*** Test timed out!!!"); + $finish; + end + join_any + disable fork; + end + +endmodule // otp_ctrl_top_tb + +//====================================================================== +// EOF otp_ctrl_top_tb.sv +//====================================================================== + + diff --git a/src/fuse_ctrl/tb/otp_ctrl_top_tb_pkg.sv b/src/fuse_ctrl/tb/otp_ctrl_top_tb_pkg.sv new file mode 100644 index 0000000..43490bd --- /dev/null +++ b/src/fuse_ctrl/tb/otp_ctrl_top_tb_pkg.sv @@ -0,0 +1,206 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//====================================================================== + +`ifndef OTP_CTRL_TOP_TB_PKG +`define OTP_CTRL_TOP_TB_PKG + +package otp_ctrl_top_tb_pkg; + + localparam int CoreAw = 13; + + localparam CSR_BASE = 0; + + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_INTR_STATE_OFFSET = 13'h 0; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_INTR_ENABLE_OFFSET = 13'h 4; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_INTR_TEST_OFFSET = 13'h 8; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_ALERT_TEST_OFFSET = 13'h c; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_STATUS_OFFSET = 13'h 10; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_ERR_CODE_0_OFFSET = 13'h 14; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_ERR_CODE_1_OFFSET = 13'h 18; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_ERR_CODE_2_OFFSET = 13'h 1c; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_ERR_CODE_3_OFFSET = 13'h 20; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_ERR_CODE_4_OFFSET = 13'h 24; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_ERR_CODE_5_OFFSET = 13'h 28; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_ERR_CODE_6_OFFSET = 13'h 2c; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_ERR_CODE_7_OFFSET = 13'h 30; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_ERR_CODE_8_OFFSET = 13'h 34; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET = 13'h 38; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET = 13'h 3c; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET = 13'h 40; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET = 13'h 44; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET = 13'h 48; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET = 13'h 4c; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET = 13'h 50; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET = 13'h 54; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_CHECK_TRIGGER_OFFSET = 13'h 58; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_CHECK_REGWEN_OFFSET = 13'h 5c; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_CHECK_TIMEOUT_OFFSET = 13'h 60; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET = 13'h 64; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET = 13'h 68; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET = 13'h 6c; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_NON_SECRET_FUSES_READ_LOCK_OFFSET = 13'h 70; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET = 13'h 74; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET = 13'h 78; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_NON_SECRET_FUSES_DIGEST_0_OFFSET = 13'h 7c; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_NON_SECRET_FUSES_DIGEST_1_OFFSET = 13'h 80; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_SECRET0_DIGEST_0_OFFSET = 13'h 84; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_SECRET0_DIGEST_1_OFFSET = 13'h 88; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_SECRET1_DIGEST_0_OFFSET = 13'h 8c; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_SECRET1_DIGEST_1_OFFSET = 13'h 90; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_SECRET2_DIGEST_0_OFFSET = 13'h 94; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_SECRET2_DIGEST_1_OFFSET = 13'h 98; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_SECRET3_DIGEST_0_OFFSET = 13'h 9c; + parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_SECRET3_DIGEST_1_OFFSET = 13'h a0; + + typedef logic [CoreAw-1:0] word_addr_t; + + typedef string strq_t [$]; + + strq_t csr_registers = '{ + "CALIPTRA_OTP_CTRL_INTR_STATE_OFFSET", + "CALIPTRA_OTP_CTRL_INTR_ENABLE_OFFSET", + "CALIPTRA_OTP_CTRL_INTR_TEST_OFFSET", + "CALIPTRA_OTP_CTRL_ALERT_TEST_OFFSET", + "CALIPTRA_OTP_CTRL_STATUS_OFFSET", + "CALIPTRA_OTP_CTRL_ERR_CODE_0_OFFSET", + "CALIPTRA_OTP_CTRL_ERR_CODE_1_OFFSET", + "CALIPTRA_OTP_CTRL_ERR_CODE_2_OFFSET", + "CALIPTRA_OTP_CTRL_ERR_CODE_3_OFFSET", + "CALIPTRA_OTP_CTRL_ERR_CODE_4_OFFSET", + "CALIPTRA_OTP_CTRL_ERR_CODE_5_OFFSET", + "CALIPTRA_OTP_CTRL_ERR_CODE_6_OFFSET", + "CALIPTRA_OTP_CTRL_ERR_CODE_7_OFFSET", + "CALIPTRA_OTP_CTRL_ERR_CODE_8_OFFSET", + "CALIPTRA_OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET", + "CALIPTRA_OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET", + "CALIPTRA_OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET", + "CALIPTRA_OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET", + "CALIPTRA_OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET", + "CALIPTRA_OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET", + "CALIPTRA_OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET", + "CALIPTRA_OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET", + "CALIPTRA_OTP_CTRL_CHECK_TRIGGER_OFFSET", + "CALIPTRA_OTP_CTRL_CHECK_REGWEN_OFFSET", + "CALIPTRA_OTP_CTRL_CHECK_TIMEOUT_OFFSET", + "CALIPTRA_OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET", + "CALIPTRA_OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET", + "CALIPTRA_OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET", + "CALIPTRA_OTP_CTRL_NON_SECRET_FUSES_READ_LOCK_OFFSET", + "CALIPTRA_OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET", + "CALIPTRA_OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET", + "CALIPTRA_OTP_CTRL_NON_SECRET_FUSES_DIGEST_0_OFFSET", + "CALIPTRA_OTP_CTRL_NON_SECRET_FUSES_DIGEST_1_OFFSET", + "CALIPTRA_OTP_CTRL_SECRET0_DIGEST_0_OFFSET", + "CALIPTRA_OTP_CTRL_SECRET0_DIGEST_1_OFFSET", + "CALIPTRA_OTP_CTRL_SECRET1_DIGEST_0_OFFSET", + "CALIPTRA_OTP_CTRL_SECRET1_DIGEST_1_OFFSET", + "CALIPTRA_OTP_CTRL_SECRET2_DIGEST_0_OFFSET", + "CALIPTRA_OTP_CTRL_SECRET2_DIGEST_1_OFFSET", + "CALIPTRA_OTP_CTRL_SECRET3_DIGEST_0_OFFSET", + "CALIPTRA_OTP_CTRL_SECRET3_DIGEST_1_OFFSET" + }; + + word_addr_t _csr_register_dict [string] = { + "CALIPTRA_OTP_CTRL_INTR_STATE_OFFSET" : CSR_BASE + CALIPTRA_OTP_CTRL_INTR_STATE_OFFSET, // 0x00 Interrupt State + "CALIPTRA_OTP_CTRL_INTR_ENABLE_OFFSET" : CSR_BASE + CALIPTRA_OTP_CTRL_INTR_ENABLE_OFFSET, // 0x04 Interrupt Enable + "CALIPTRA_OTP_CTRL_INTR_TEST_OFFSET" : CSR_BASE + CALIPTRA_OTP_CTRL_INTR_TEST_OFFSET, // 0x08 Interrupt Test + "CALIPTRA_OTP_CTRL_ALERT_TEST_OFFSET" : CSR_BASE + CALIPTRA_OTP_CTRL_ALERT_TEST_OFFSET, // 0x0C Alert Test + "CALIPTRA_OTP_CTRL_STATUS_OFFSET" : CSR_BASE + CALIPTRA_OTP_CTRL_STATUS_OFFSET, // 0x10 Status + "CALIPTRA_OTP_CTRL_ERR_CODE_0_OFFSET" : CSR_BASE + CALIPTRA_OTP_CTRL_ERR_CODE_0_OFFSET, // 0x14 Error Code 0 + "CALIPTRA_OTP_CTRL_ERR_CODE_1_OFFSET" : CSR_BASE + CALIPTRA_OTP_CTRL_ERR_CODE_1_OFFSET, // 0x18 Error Code 1 + "CALIPTRA_OTP_CTRL_ERR_CODE_2_OFFSET" : CSR_BASE + CALIPTRA_OTP_CTRL_ERR_CODE_2_OFFSET, // 0x1C Error Code 2 + "CALIPTRA_OTP_CTRL_ERR_CODE_3_OFFSET" : CSR_BASE + CALIPTRA_OTP_CTRL_ERR_CODE_3_OFFSET, // 0x20 Error Code 3 + "CALIPTRA_OTP_CTRL_ERR_CODE_4_OFFSET" : CSR_BASE + CALIPTRA_OTP_CTRL_ERR_CODE_4_OFFSET, // 0x24 Error Code 4 + "CALIPTRA_OTP_CTRL_ERR_CODE_5_OFFSET" : CSR_BASE + CALIPTRA_OTP_CTRL_ERR_CODE_5_OFFSET, // 0x28 Error Code 5 + "CALIPTRA_OTP_CTRL_ERR_CODE_6_OFFSET" : CSR_BASE + CALIPTRA_OTP_CTRL_ERR_CODE_6_OFFSET, // 0x2C Error Code 6 + "CALIPTRA_OTP_CTRL_ERR_CODE_7_OFFSET" : CSR_BASE + CALIPTRA_OTP_CTRL_ERR_CODE_7_OFFSET, // 0x30 Error Code 7 + "CALIPTRA_OTP_CTRL_ERR_CODE_8_OFFSET" : CSR_BASE + CALIPTRA_OTP_CTRL_ERR_CODE_8_OFFSET, // 0x34 Error Code 8 + "CALIPTRA_OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET" : CSR_BASE + CALIPTRA_OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET, // 0x38 Direct Access Register Write Enable + "CALIPTRA_OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET" : CSR_BASE + CALIPTRA_OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET, // 0x3C Direct Access Command + "CALIPTRA_OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET" : CSR_BASE + CALIPTRA_OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET, // 040x Direct Access Address + "CALIPTRA_OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET" : CSR_BASE + CALIPTRA_OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET, // 0x44 Direct Access Write Data 0 + "CALIPTRA_OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET" : CSR_BASE + CALIPTRA_OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET, // 0x48 Direct Access Write Data 1 + "CALIPTRA_OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET" : CSR_BASE + CALIPTRA_OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET, // 0x4C Direct Access Read Data 0 + "CALIPTRA_OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET" : CSR_BASE + CALIPTRA_OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET, // 0x50 Direct Access Read Data 1 + "CALIPTRA_OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET" : CSR_BASE + CALIPTRA_OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET, // 0x54 Check Trigger Register Write Enable + "CALIPTRA_OTP_CTRL_CHECK_TRIGGER_OFFSET" : CSR_BASE + CALIPTRA_OTP_CTRL_CHECK_TRIGGER_OFFSET, // 0x58 Check Trigger + "CALIPTRA_OTP_CTRL_CHECK_REGWEN_OFFSET" : CSR_BASE + CALIPTRA_OTP_CTRL_CHECK_REGWEN_OFFSET, // 0x5C Check Register Write Enable + "CALIPTRA_OTP_CTRL_CHECK_TIMEOUT_OFFSET" : CSR_BASE + CALIPTRA_OTP_CTRL_CHECK_TIMEOUT_OFFSET, // 0x60 Check Timeout + "CALIPTRA_OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET" : CSR_BASE + CALIPTRA_OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET, // 0x64 Integrity Check Period + "CALIPTRA_OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET" : CSR_BASE + CALIPTRA_OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET, // 0x68 Consistency Check Period + "CALIPTRA_OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET" : CSR_BASE + CALIPTRA_OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET, // 0x6C Vendor Test Read Lock + "CALIPTRA_OTP_CTRL_NON_SECRET_FUSES_READ_LOCK_OFFSET" : CSR_BASE + CALIPTRA_OTP_CTRL_NON_SECRET_FUSES_READ_LOCK_OFFSET, // 0x70 Non Secret Fuses Read Lock + "CALIPTRA_OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET" : CSR_BASE + CALIPTRA_OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET, // 0x74 Vendor Test Digest 0 + "CALIPTRA_OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET" : CSR_BASE + CALIPTRA_OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET, // 0x78 Vendor Test Digest 1 + "CALIPTRA_OTP_CTRL_NON_SECRET_FUSES_DIGEST_0_OFFSET" : CSR_BASE + CALIPTRA_OTP_CTRL_NON_SECRET_FUSES_DIGEST_0_OFFSET, // 0x7C Non Secret Fuses Digest 0 + "CALIPTRA_OTP_CTRL_NON_SECRET_FUSES_DIGEST_1_OFFSET" : CSR_BASE + CALIPTRA_OTP_CTRL_NON_SECRET_FUSES_DIGEST_1_OFFSET, // 0x80 Non Secret Fuses Digest 1 + "CALIPTRA_OTP_CTRL_SECRET0_DIGEST_0_OFFSET" : CSR_BASE + CALIPTRA_OTP_CTRL_SECRET0_DIGEST_0_OFFSET, // 0x84 Secret 0 Digest 0 + "CALIPTRA_OTP_CTRL_SECRET0_DIGEST_1_OFFSET" : CSR_BASE + CALIPTRA_OTP_CTRL_SECRET0_DIGEST_1_OFFSET, // 0x88 Secret 0 Digest 1 + "CALIPTRA_OTP_CTRL_SECRET1_DIGEST_0_OFFSET" : CSR_BASE + CALIPTRA_OTP_CTRL_SECRET1_DIGEST_0_OFFSET, // 0x8C Secret 1 Digest 0 + "CALIPTRA_OTP_CTRL_SECRET1_DIGEST_1_OFFSET" : CSR_BASE + CALIPTRA_OTP_CTRL_SECRET1_DIGEST_1_OFFSET, // 0x90 Secret 1 Digest 1 + "CALIPTRA_OTP_CTRL_SECRET2_DIGEST_0_OFFSET" : CSR_BASE + CALIPTRA_OTP_CTRL_SECRET2_DIGEST_0_OFFSET, // 0x94 Secret 2 Digest 0 + "CALIPTRA_OTP_CTRL_SECRET2_DIGEST_1_OFFSET" : CSR_BASE + CALIPTRA_OTP_CTRL_SECRET2_DIGEST_1_OFFSET, // 0x98 Secret 2 Digest 1 + "CALIPTRA_OTP_CTRL_SECRET3_DIGEST_0_OFFSET" : CSR_BASE + CALIPTRA_OTP_CTRL_SECRET3_DIGEST_0_OFFSET, // 0x9C Secret 3 Digest 0 + "CALIPTRA_OTP_CTRL_SECRET3_DIGEST_1_OFFSET" : CSR_BASE + CALIPTRA_OTP_CTRL_SECRET3_DIGEST_1_OFFSET // 0xA0 Secret 3 Digest 1 + }; + + function word_addr_t get_addr(string name); + if (_csr_register_dict.exists(name)) + return _csr_register_dict[name]; + else begin + $display("TB WARNING. Address %s is not found in csr reg name -> address map. Returning 0", name); + return 0; + end + endfunction // get_addr + + function strq_t get_dai_regnames(); + strq_t dai_regs; + string csr_reg_name; + + foreach (csr_registers[i]) begin + csr_reg_name = csr_registers[i]; + if (csr_reg_name.substr(18, 23) == "DIRECT") + dai_regs.push_back(csr_reg_name); + end + + return dai_regs; + endfunction + + function bit str_find (string reg_name, string substr); + int i; + bit found; + for (i = 0; i <= reg_name.len() - substr.len(); i++) begin + $display(reg_name, i); + //$display(reg_name[i], reg_name[i+1], reg_name[i+2], reg_name[i+3], reg_name[i+4], reg_name[i+5]); + $display(reg_name.substr(i, substr.len()-1)); + if (reg_name.substr(i, (i + substr.len()-1)) == substr) begin + //$display("Substring '%s' found at index %0d", substr, i); + found = 1; + break; + end + end + if (!found) begin + $display("Substring '%s' not found", substr); + end + return found; + endfunction + + + + +endpackage + +`endif \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/config/compile.yml b/src/fuse_ctrl/uvmf_fuse_ctrl/config/compile.yml new file mode 100644 index 0000000..7540076 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/config/compile.yml @@ -0,0 +1,162 @@ +--- +provides: [uvmf_fuse_ctrl] +schema_version: 2.4.0 +requires: + - uvmf_lib + - fuse_ctrl +targets: + tb: + directories: + - ${COMPILE_ROOT}/../rtl + - ${COMPILE_ROOT}/../../libs/rtl + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/src + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/src + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/environment_packages/fuse_ctrl_env_pkg + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/environment_packages/fuse_ctrl_env_pkg/src + - ${COMPILE_ROOT}/uvmf_template_output/project_benches/fuse_ctrl/tb/parameters + - ${COMPILE_ROOT}/uvmf_template_output/project_benches/fuse_ctrl/tb/sequences + - ${COMPILE_ROOT}/uvmf_template_output/project_benches/fuse_ctrl/tb/tests + - ${COMPILE_ROOT}/uvmf_template_output/project_benches/fuse_ctrl/tb/testbench + files: + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_pkg_hdl.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_pkg.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_driver_bfm.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_if.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_monitor_bfm.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_pkg_hdl.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_pkg.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_driver_bfm.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_if.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_monitor_bfm.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_pkg_hdl.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_pkg.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_driver_bfm.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_if.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_monitor_bfm.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_pkg_hdl.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_pkg.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_driver_bfm.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_if.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_monitor_bfm.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_pkg_hdl.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_pkg.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_driver_bfm.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_if.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_monitor_bfm.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_pkg_hdl.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_pkg.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_driver_bfm.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_if.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_monitor_bfm.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_pkg_hdl.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_pkg.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_driver_bfm.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_if.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_monitor_bfm.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_pkg_hdl.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_pkg.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_driver_bfm.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_if.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_monitor_bfm.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_pkg_hdl.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_pkg.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_driver_bfm.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_if.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_monitor_bfm.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_pkg_hdl.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_pkg.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_driver_bfm.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_if.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_monitor_bfm.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_pkg_hdl.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_pkg.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_driver_bfm.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_if.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_monitor_bfm.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_pkg_hdl.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_pkg.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_driver_bfm.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_if.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_monitor_bfm.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_pkg_hdl.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_pkg.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_driver_bfm.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_if.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_monitor_bfm.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_pkg_hdl.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_pkg.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_driver_bfm.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_if.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_monitor_bfm.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_pkg_hdl.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_pkg.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_driver_bfm.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_if.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_monitor_bfm.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_pkg_hdl.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_pkg.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_driver_bfm.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_if.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_monitor_bfm.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/environment_packages/fuse_ctrl_env_pkg/fuse_ctrl_env_pkg.sv + - ${COMPILE_ROOT}/uvmf_template_output/project_benches/fuse_ctrl/tb/parameters/fuse_ctrl_parameters_pkg.sv + - ${COMPILE_ROOT}/uvmf_template_output/project_benches/fuse_ctrl/tb/sequences/fuse_ctrl_sequences_pkg.sv + - ${COMPILE_ROOT}/uvmf_template_output/project_benches/fuse_ctrl/tb/tests/fuse_ctrl_tests_pkg.sv + - ${COMPILE_ROOT}/uvmf_template_output/project_benches/fuse_ctrl/tb/testbench/hdl_top.sv + - ${COMPILE_ROOT}/uvmf_template_output/project_benches/fuse_ctrl/tb/testbench/hvl_top.sv + tops: + - hdl_top + - hvl_top +global: + tool: + vcs: + default: + - '-assert svaext' + - '-noinherit_timescale=1ns/1ps' + #sim: + #- '-ucli -i dump.ucli' + # Suppress a warning due to calling $fgets as task instead of function + # i.e. discarding the return value. This is in auto-generated code. + - '+warn=noRVOSFD' + # Suppress NOTE about repeated package imports within the same + # package (each .svh file included in the auto-generated UVM _pkg.sv + # files imports the same dependencies) + - '-suppress=SV-LCM-PPWI' + elab: + # Suppress warnings about too few port connections - auto-generated interfaces + # declare all signals as inout, but are driven at a lower layer than the + # instantiation, so they will always flag this + - '-suppress=TFIPC' + + + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/fuse_ctrl_bench.yaml b/src/fuse_ctrl/uvmf_fuse_ctrl/fuse_ctrl_bench.yaml new file mode 100644 index 0000000..c7d7461 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/fuse_ctrl_bench.yaml @@ -0,0 +1,51 @@ +uvmf: + benches: + fuse_ctrl: + + active_passive: + - bfm_name: fuse_ctrl_rst_in_agent + value: ACTIVE + - bfm_name: fuse_ctrl_rst_out_agent + value: PASSIVE + ############# WRITE AGENTS ########## + - bfm_name: fuse_ctrl_core_axi_write_in_if_agent + value: ACTIVE + - bfm_name: fuse_ctrl_core_axi_write_out_if_agent + value: PASSIVE + - bfm_name: fuse_ctrl_prim_axi_write_in_if_agent + value: ACTIVE + - bfm_name: fuse_ctrl_prim_axi_write_out_if_agent + value: PASSIVE + ############# READ AGENTS ########### + - bfm_name: fuse_ctrl_core_axi_read_in_if_agent + value: ACTIVE + - bfm_name: fuse_ctrl_core_axi_read_out_if_agent + value: PASSIVE + - bfm_name: fuse_ctrl_prim_axi_read_in_if_agent + value: ACTIVE + - bfm_name: fuse_ctrl_prim_axi_read_out_if_agent + value: PASSIVE + - bfm_name: fuse_ctrl_secreg_axi_read_in_if_agent + value: ACTIVE + - bfm_name: fuse_ctrl_secreg_axi_read_out_if_agent + value: PASSIVE + ############ OTHER AGENTS ########### + - bfm_name: fuse_ctrl_lc_otp_in_if_agent + value: ACTIVE + - bfm_name: fuse_ctrl_lc_otp_out_if_agent + value: PASSIVE + - bfm_name: fuse_ctrl_in_if_agent + value: ACTIVE + - bfm_name: fuse_ctrl_out_if_agent + value: PASSIVE + + + clock_half_period: 5ns + clock_phase_offset: 0ns + + interface_params: [] + + reset_assertion_level: 'False' + reset_duration: 200ns + + top_env: fuse_ctrl \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/fuse_ctrl_environment.yaml b/src/fuse_ctrl/uvmf_fuse_ctrl/fuse_ctrl_environment.yaml new file mode 100644 index 0000000..2395735 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/fuse_ctrl_environment.yaml @@ -0,0 +1,102 @@ +uvmf: + environments: + fuse_ctrl: + agents: + - name: fuse_ctrl_rst_in_agent + type: fuse_ctrl_rst_in + initiator_responder: "INITIATOR" + - name: fuse_ctrl_rst_out_agent + type: fuse_ctrl_rst_out + initiator_responder: "RESPONDER" + - name: fuse_ctrl_core_axi_write_in_if_agent + type: fuse_ctrl_core_axi_write_in + initiator_responder: "INITIATOR" + - name: fuse_ctrl_core_axi_write_out_if_agent + type: fuse_ctrl_core_axi_write_out + initiator_responder: "RESPONDER" + - name: fuse_ctrl_prim_axi_write_in_if_agent + type: fuse_ctrl_prim_axi_write_in + initiator_responder: "INITIATOR" + - name: fuse_ctrl_prim_axi_write_out_if_agent + type: fuse_ctrl_prim_axi_write_out + initiator_responder: "RESPONDER" + - name: fuse_ctrl_core_axi_read_in_if_agent + type: fuse_ctrl_core_axi_read_in + initiator_responder: "INITIATOR" + - name: fuse_ctrl_core_axi_read_out_if_agent + type: fuse_ctrl_core_axi_read_out + initiator_responder: "RESPONDER" + - name: fuse_ctrl_prim_axi_read_in_if_agent + type: fuse_ctrl_prim_axi_read_in + initiator_responder: "INITIATOR" + - name: fuse_ctrl_prim_axi_read_out_if_agent + type: fuse_ctrl_prim_axi_read_out + initiator_responder: "RESPONDER" + - name: fuse_ctrl_secreg_axi_read_in_if_agent + type: fuse_ctrl_secreg_axi_read_in + initiator_responder: "INITIATOR" + - name: fuse_ctrl_secreg_axi_read_out_if_agent + type: fuse_ctrl_secreg_axi_read_out + initiator_responder: "RESPONDER" + - name: fuse_ctrl_lc_otp_in_if_agent + type: fuse_ctrl_lc_otp_in + initiator_responder: "INITIATOR" + - name: fuse_ctrl_lc_otp_out_if_agent + type: fuse_ctrl_lc_otp_out + initiator_responder: "RESPONDER" + - name: fuse_ctrl_in_if_agent + type: fuse_ctrl_in + initiator_responder: "INITIATOR" + - name: fuse_ctrl_out_if_agent + type: fuse_ctrl_out + initiator_responder: "RESPONDER" + + analysis_components: + - name: fuse_ctrl_pred + type: fuse_ctrl_predictor + - name: fuse_ctrl_sb + type: fuse_ctrl_scoreboard + + analysis_ports: [] + + config_constraints: [] + config_vars: [] + + parameters: [] + + scoreboards: [] + + subenvs: [] + + tlm_connections: + - driver: fuse_ctrl_rst_in_agent.monitored_ap + receiver: fuse_ctrl_pred.fuse_ctrl_rst_in_agent_ae + - driver: fuse_ctrl_core_axi_write_in_if_agent.monitored_ap + receiver: fuse_ctrl_pred.fuse_ctrl_core_axi_write_in_agent_ae + - driver: fuse_ctrl_core_axi_write_out_if_agent.monitored_ap + receiver: fuse_ctrl_sb.fuse_ctrl_core_axi_write_in_agent_ae # Updated + - driver: fuse_ctrl_core_axi_read_in_if_agent.monitored_ap + receiver: fuse_ctrl_pred.fuse_ctrl_core_axi_read_in_agent_ae + - driver: fuse_ctrl_core_axi_read_out_if_agent.monitored_ap + receiver: fuse_ctrl_sb.fuse_ctrl_core_axi_read_in_agent_ae # Updated + - driver: fuse_ctrl_prim_axi_write_in_if_agent.monitored_ap + receiver: fuse_ctrl_pred.fuse_ctrl_prim_axi_write_in_agent_ae + - driver: fuse_ctrl_prim_axi_write_out_if_agent.monitored_ap + receiver: fuse_ctrl_sb.fuse_ctrl_prim_axi_write_in_agent_ae # Updated + - driver: fuse_ctrl_prim_axi_read_in_if_agent.monitored_ap + receiver: fuse_ctrl_pred.fuse_ctrl_prim_axi_read_in_agent_ae + - driver: fuse_ctrl_prim_axi_read_out_if_agent.monitored_ap + receiver: fuse_ctrl_sb.fuse_ctrl_prim_axi_read_in_agent_ae # Updated + - driver: fuse_ctrl_secreg_axi_read_in_if_agent.monitored_ap + receiver: fuse_ctrl_pred.fuse_ctrl_secreg_axi_read_in_agent_ae + - driver: fuse_ctrl_secreg_axi_read_out_if_agent.monitored_ap + receiver: fuse_ctrl_sb.fuse_ctrl_secreg_axi_read_in_agent_ae # Updated + - driver: fuse_ctrl_lc_otp_in_if_agent.monitored_ap + receiver: fuse_ctrl_pred.fuse_ctrl_lc_otp_in_agent_ae + - driver: fuse_ctrl_lc_otp_out_if_agent.monitored_ap + receiver: fuse_ctrl_sb.fuse_ctrl_lc_otp_in_agent_ae # Updated + - driver: fuse_ctrl_in_if_agent.monitored_ap + receiver: fuse_ctrl_pred.fuse_ctrl_in_agent_ae + - driver: fuse_ctrl_out_if_agent.monitored_ap + receiver: fuse_ctrl_sb.fuse_ctrl_in_agent_ae # Updated + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/fuse_ctrl_global.yaml b/src/fuse_ctrl/uvmf_fuse_ctrl/fuse_ctrl_global.yaml new file mode 100644 index 0000000..562413a --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/fuse_ctrl_global.yaml @@ -0,0 +1,16 @@ +uvmf : + global: + header: | + // SPDX-License-Identifier: Apache-2.0 + // + // Licensed under the Apache License, Version 2.0 (the "License"); + // you may not use this file except in compliance with the License. + // You may obtain a copy of the License at + // + // http://www.apache.org/licenses/LICENSE-2.0 + // + // Unless required by applicable law or agreed to in writing, software + // distributed under the License is distributed on an "AS IS" BASIS, + // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + // See the License for the specific language governing permissions and + // limitations under the License. diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/fuse_ctrl_in_interfaces.yaml b/src/fuse_ctrl/uvmf_fuse_ctrl/fuse_ctrl_in_interfaces.yaml new file mode 100644 index 0000000..8a5d2ec --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/fuse_ctrl_in_interfaces.yaml @@ -0,0 +1,699 @@ +uvmf: + interfaces: + #################################################### + ############### RESET INTERFACE #################### + #################################################### + "fuse_ctrl_rst_in": + clock: "clk_i" + reset: "rst_ni" + reset_assertion_level: "False" + + ports: + # Power manager interface + - name: pwr_otp_i + dir: output + width: [$bits(pwrmgr_pkg::pwr_otp_req_t)] + # External voltage for OTP + - name: otp_ext_voltage_h_io + dir: inout + width: '1' + + transaction_constraints: [] + transaction_vars: + - name: assert_rst + type: bit + iscompare: 'False' + isrand: 'False' + - name: assert_otp_pwr_init + type: bit + iscompare: 'False' + isrand: 'False' + + #################################################### + ############### CORE AXI WRITE ##################### + #################################################### + "fuse_ctrl_core_axi_write_in": + clock: "clk_i" + reset: "rst_ni" + reset_assertion_level: "False" + + parameters: + - name: AW + type: int + value: '32' + - name: DW + type: int + value: '32' + - name: IW + type: int + value: '3' + - name: UW + type: int + value: '32' + + ports: + # Address Channel Write Address + - name: awaddr + dir: output + width: [AW] + # Burst + - name: awburst + dir: output + width: [$bits(axi_pkg::axi_burst_e)] + # size + - name: awsize + dir: output + width: '3' + # Length: + - name: awlen + dir: output + width: '8' + # User + - name: awuser + dir: output + width: [UW] + # ID + - name: awid + dir: output + width: [UW] + # Lock + - name: awlock + dir: output + width: '1' + # Write request valid + - name: awvalid + dir: output + width: '1' + # Write data + - name: wdata + dir: output + width: [DW] + # Write strobe + - name: wstrb + dir: output + width: [DW/8] + # Write data valid + - name: wvalid + dir: output + width: '1' + # Write last + - name: wlast + dir: output + width: '1' + # Ready for write + - name: bready + dir: output + width: '1' + + transaction_constraints: [] + transaction_vars: + - name: core_awaddr + type: logic [AW-1:0] + iscompare: 'False' + isrand: 'True' + - name: core_awvalid + type: logic + iscompare: 'False' + isrand: 'False' + - name: core_awburst + type: logic [$bits(axi_pkg::axi_burst_e)] + iscompare: 'False' + isrand: 'False' + - name: core_awsize + type: logic [2:0] + iscompare: 'False' + isrand: 'False' + - name: core_awlen + type: logic [7:0] + iscompare: 'False' + isrand: 'False' + - name: core_awuser + type: logic [UW-1:0] + iscompare: 'False' + isrand: 'False' + - name: core_awid + type: logic [IW-1:0] + iscompare: 'False' + isrand: 'False' + - name: core_awlock + type: logic + iscompare: 'False' + isrand: 'False' + - name: core_wdata + type: logic [DW-1:0] + iscompare: 'True' + isrand: 'False' + - name: core_wstrb + type: logic [DW/8 - 1:0] + iscompare: 'False' + isrand: 'False' + - name: core_wvalid + type: logic + iscompare: 'False' + isrand: 'False' + - name: core_wlast + type: logic + iscompare: 'False' + isrand: 'False' + - name: core_bready + type: logic + iscompare: 'False' + isrand: 'False' + + #################################################### + ############### CORE AXI READ ###################### + #################################################### + "fuse_ctrl_core_axi_read_in": + clock: "clk_i" + reset: "rst_ni" + reset_assertion_level: "False" + + parameters: + - name: AW + type: int + value: '32' + - name: DW + type: int + value: '32' + - name: IW + type: int + value: '3' + - name: UW + type: int + value: '32' + + ports: + # Address Channel Read Address + - name: araddr + dir: output + width: [AW] + # Burst + - name: arburst + dir: output + width: [$bits(axi_pkg::axi_burst_e)] + # Size + - name: arsize + dir: output + width: '3' + # Length: + - name: arlen + dir: output + width: '8' + # User: + - name: aruser + dir: output + width: [UW] + # Id + - name: arid + dir: output + width: [IW] + # Lock + - name: arlock + dir: output + width: '1' + # Address valid + - name: arvalid + dir: output + width: '1' + # Device ready + - name: rready + dir: output + width: '1' + + transaction_constraints: [] + transaction_vars: + - name: core_araddr + type: logic [AW-1:0] + iscompare: 'False' + isrand: 'True' + - name: core_arvalid + type: logic + iscompare: 'False' + isrand: 'False' + - name: core_arburst + type: logic [$bits(axi_pkg::axi_burst_e)] + iscompare: 'False' + isrand: 'False' + - name: core_arsize + type: logic [2:0] + iscompare: 'False' + isrand: 'False' + - name: core_arlen + type: logic [7:0] + iscompare: 'False' + isrand: 'False' + - name: core_aruser + type: logic [UW-1:0] + iscompare: 'False' + isrand: 'False' + - name: core_arid + type: logic [IW-1:0] + iscompare: 'False' + isrand: 'False' + - name: core_arlock + type: logic + iscompare: 'False' + isrand: 'False' + - name: core_rready + type: logic + iscompare: 'False' + isrand: 'False' + + #################################################### + ############### PRIM AXI WRITE ##################### + #################################################### + "fuse_ctrl_prim_axi_write_in": + clock: "clk_i" + reset: "rst_ni" + reset_assertion_level: "False" + + parameters: + - name: AW + type: int + value: '32' + - name: DW + type: int + value: '32' + - name: IW + type: int + value: '3' + - name: UW + type: int + value: '32' + + ports: + # Address Channel Write Address + - name: awaddr + dir: output + width: [AW] + # Burst + - name: awburst + dir: output + width: [$bits(axi_pkg::axi_burst_e)] + # size + - name: awsize + dir: output + width: '3' + # Length: + - name: awlen + dir: output + width: '8' + # User + - name: awuser + dir: output + width: [UW] + # ID + - name: awid + dir: output + width: [UW] + # Lock + - name: awlock + dir: output + width: '1' + # Write request valid + - name: awvalid + dir: output + width: '1' + # Write data + - name: wdata + dir: output + width: [DW] + # Write strobe + - name: wstrb + dir: output + width: [DW/8] + # Write data valid + - name: wvalid + dir: output + width: '1' + # Write last + - name: wlast + dir: output + width: '1' + # Ready for write + - name: bready + dir: output + width: '1' + + transaction_constraints: [] + transaction_vars: + - name: prim_awaddr + type: logic [AW-1:0] + iscompare: 'False' + isrand: 'True' + - name: prim_awvalid + type: logic + iscompare: 'False' + isrand: 'False' + - name: prim_awburst + type: logic [$bits(axi_pkg::axi_burst_e)] + iscompare: 'False' + isrand: 'False' + - name: prim_awsize + type: logic [2:0] + iscompare: 'False' + isrand: 'False' + - name: prim_awlen + type: logic [7:0] + iscompare: 'False' + isrand: 'False' + - name: prim_awuser + type: logic [UW-1:0] + iscompare: 'False' + isrand: 'False' + - name: prim_awid + type: logic [IW-1:0] + iscompare: 'False' + isrand: 'False' + - name: prim_awlock + type: logic + iscompare: 'False' + isrand: 'False' + - name: prim_wdata + type: logic [DW-1:0] + iscompare: 'True' + isrand: 'False' + - name: prim_wstrb + type: logic [DW/8 - 1:0] + iscompare: 'False' + isrand: 'False' + - name: prim_wvalid + type: logic + iscompare: 'False' + isrand: 'False' + - name: prim_wlast + type: logic + iscompare: 'False' + isrand: 'False' + - name: prim_bready + type: logic + iscompare: 'False' + isrand: 'False' + + #################################################### + ############### PRIM AXI READ ###################### + #################################################### + "fuse_ctrl_prim_axi_read_in": + clock: "clk_i" + reset: "rst_ni" + reset_assertion_level: "False" + + parameters: + - name: AW + type: int + value: '32' + - name: DW + type: int + value: '32' + - name: IW + type: int + value: '3' + - name: UW + type: int + value: '32' + + ports: + # Address Channel Read Address + - name: araddr + dir: output + width: [AW] + # Burst + - name: arburst + dir: output + width: [$bits(axi_pkg::axi_burst_e)] + # Size + - name: arsize + dir: output + width: '3' + # Length: + - name: arlen + dir: output + width: '8' + # User: + - name: aruser + dir: output + width: [UW] + # Id + - name: arid + dir: output + width: [IW] + # Lock + - name: arlock + dir: output + width: '1' + # Address valid + - name: arvalid + dir: output + width: '1' + # Device ready + - name: rready + dir: output + width: '1' + + transaction_constraints: [] + transaction_vars: + - name: prim_araddr + type: logic [AW-1:0] + iscompare: 'False' + isrand: 'True' + - name: prim_arvalid + type: logic + iscompare: 'False' + isrand: 'False' + - name: prim_arburst + type: logic [$bits(axi_pkg::axi_burst_e)] + iscompare: 'False' + isrand: 'False' + - name: prim_arsize + type: logic [2:0] + iscompare: 'False' + isrand: 'False' + - name: prim_arlen + type: logic [7:0] + iscompare: 'False' + isrand: 'False' + - name: prim_aruser + type: logic [UW-1:0] + iscompare: 'False' + isrand: 'False' + - name: prim_arid + type: logic [IW-1:0] + iscompare: 'False' + isrand: 'False' + - name: prim_arlock + type: logic + iscompare: 'False' + isrand: 'False' + - name: prim_rready + type: logic + iscompare: 'False' + isrand: 'False' + + #################################################### + ############### SECREG AXI READ #################### + #################################################### + "fuse_ctrl_secreg_axi_read_in": + clock: "clk_i" + reset: "rst_ni" + reset_assertion_level: "False" + + parameters: + - name: AW + type: int + value: '32' + - name: DW + type: int + value: '32' + - name: IW + type: int + value: '3' + - name: UW + type: int + value: '32' + + ports: + # Address Channel Read Address + - name: araddr + dir: output + width: [AW] + # Burst + - name: arburst + dir: output + width: [$bits(axi_pkg::axi_burst_e)] + # Size + - name: arsize + dir: output + width: '3' + # Length: + - name: arlen + dir: output + width: '8' + # User: + - name: aruser + dir: output + width: [UW] + # Id + - name: arid + dir: output + width: [IW] + # Lock + - name: arlock + dir: output + width: '1' + # Address valid + - name: arvalid + dir: output + width: '1' + # Device ready + - name: rready + dir: output + width: '1' + + transaction_constraints: [] + transaction_vars: + - name: secreg_araddr + type: logic [AW-1:0] + iscompare: 'False' + isrand: 'True' + - name: secreg_arvalid + type: logic + iscompare: 'False' + isrand: 'False' + - name: secreg_arburst + type: logic [$bits(axi_pkg::axi_burst_e)] + iscompare: 'False' + isrand: 'False' + - name: secreg_arsize + type: logic [2:0] + iscompare: 'False' + isrand: 'False' + - name: secreg_arlen + type: logic [7:0] + iscompare: 'False' + isrand: 'False' + - name: secreg_aruser + type: logic [UW-1:0] + iscompare: 'False' + isrand: 'False' + - name: secreg_arid + type: logic [IW-1:0] + iscompare: 'False' + isrand: 'False' + - name: secreg_arlock + type: logic + iscompare: 'False' + isrand: 'False' + - name: secreg_rready + type: logic + iscompare: 'False' + isrand: 'False' + + #################################################### + ############### FUSE CTRL IF ####################### + #################################################### + "fuse_ctrl_in": + clock: "clk_i" + reset: "rst_ni" + reset_assertion_level: "False" + + parameters: + - name: AlertSyncOn + type: int + value: '3' + - name: RndConstLfrSeed + type: caliptra_otp_ctrl_pkg::lfsr_seed_t + value: 'caliptra_otp_ctrl_pkg::RndCnstLfsrSeedDefault' + - name: RndCnstLfsrPerm + type: caliptra_otp_ctrl_pkg::lfsr_perm_t + value: 'caliptra_otp_ctrl_pkg::RndCnstLfsrPermDefault' + - name: MemInitFile + type: string + value: "\"\"" + #value: "\"/home/ws/caliptra/anjpar/ws1/chipsalliance/caliptra-rtl/src/fuse_ctrl/data/otp-img.2048.vmem\"" + + ports: + # EDN interface + - name: edn_i + dir: output + width: [$bits(edn_pkg::edn_req_t)] + # Alerts + - name: alert_rx_i + dir: output + width: [ast_pkg::NumAlerts * $bits(caliptra_prim_alert_pkg::alert_rx_t)] + # Observability to AST + - name: obs_ctrl_i + dir: output + width: [$bits(ast_pkg::ast_obs_ctrl_t)] + # macro-specific power sequencing signal from AST + - name: otp_ast_pwr_seq_h_i + dir: output + width: [$bits(caliptra_otp_ctrl_pkg::otp_ast_req_t)] + # Scan + - name: scan_en_i + dir: output + width: '1' + - name: scan_rst_ni + dir: output + width: '1' + - name: scanmode_i + dir: output + width: '1' + + transaction_constraints: [] + transaction_vars: + - name: set_alert_rx_i + type: caliptra_prim_alert_pkg::alert_rx_t + iscompare: 'False' + isrand: 'False' + + + #################################################### + ################## OTP LC IF ####################### + #################################################### + "fuse_ctrl_lc_otp_in": + clock: "clk_i" + reset: "rst_ni" + reset_assertion_level: "False" + + ports: + # macro specific test register from LC TAP + - name: lc_otp_vendor_test_i + dir: output + width: [$bits(caliptra_otp_ctrl_pkg::lc_otp_vendor_test_req_t)] + # LC transition command interface + - name: lc_otp_program_i + dir: output + width: [$bits(caliptra_otp_ctrl_pkg::lc_otp_program_req_t)] + # LC Broadcast inputs + - name: lc_dft_en_i + dir: output + width: [$bits(lc_ctrl_pkg::lc_tx_t)] + - name: lc_escalate_en_i + dir: output + width: [$bits(lc_ctrl_pkg::lc_tx_t)] + - name: lc_check_byp_en_i + dir: output + width: [$bits(lc_ctrl_pkg::lc_tx_t)] + + response_info: + data: [] + operation: 1'b0 + + transaction_constraints: [] + transaction_vars: + - name: lc_dft_en_i + type: lc_ctrl_pkg::lc_tx_t + iscompare: 'False' + isrand: 'False' + - name: lc_escalate_en_i + type: lc_ctrl_pkg::lc_tx_t + iscompare: 'False' + isrand: 'False' + - name: lc_check_byp_en_i + type: lc_ctrl_pkg::lc_tx_t + iscompare: 'False' + isrand: 'False' + + + + \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/fuse_ctrl_out_interfaces.yaml b/src/fuse_ctrl/uvmf_fuse_ctrl/fuse_ctrl_out_interfaces.yaml new file mode 100644 index 0000000..314d9ea --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/fuse_ctrl_out_interfaces.yaml @@ -0,0 +1,471 @@ +uvmf: + interfaces: + "fuse_ctrl_rst_out": + clock: "clk_i" + reset: "rst_ni" + reset_assertion_level: "False" + + ports: + # Power manager interface + - name: pwr_otp_o + dir: input + width: [$bits(pwrmgr_pkg::pwr_otp_rsp_t)] + # External voltage for OTP + - name: otp_ext_voltage_h_io + dir: inout + width: '1' + + transaction_constraints: [] + transaction_vars: + - name: pwr_otp_o + type: pwrmgr_pkg::pwr_otp_rsp_t + isrand: 'False' + iscompare: 'True' + + "fuse_ctrl_core_axi_write_out": + clock: "clk_i" + reset: "rst_ni" + reset_assertion_level: "False" + + parameters: + - name: AW + type: int + value: '32' + - name: DW + type: int + value: '32' + - name: IW + type: int + value: '3' + - name: UW + type: int + value: '32' + + ports: + # Address Write Channel Ready + - name: awready + dir: input + width: '1' + # Write Ready + - name: wready + dir: input + width: '1' + # Write Response + - name: bresp + dir: input + width: [$bits(axi_pkg::axi_burst_e)] + # Write Response ID + - name: bid + dir: input + width: '1' + # Write Response Valid + - name: bvalid + dir: input + width: '1' + + transaction_constraints: [] + transaction_vars: + - name: core_awready + type: logic + iscompare: 'True' + isrand: 'False' + - name: core_wready + type: logic + iscompare: 'True' + isrand: 'False' + - name: core_bresp + type: axi_pkg::axi_burst_e + iscompare: 'True' + isrand: 'False' + - name: core_bid + type: logic + iscompare: 'True' + isrand: 'False' + - name: core_bvalid + type: logic + iscompare: 'True' + isrand: 'False' + + "fuse_ctrl_core_axi_read_out": + clock: "clk_i" + reset: "rst_ni" + reset_assertion_level: "False" + + parameters: + - name: AW + type: int + value: '32' + - name: DW + type: int + value: '32' + - name: IW + type: int + value: '3' + - name: UW + type: int + value: '32' + + ports: + # Address Read Channel Ready + - name: arready + dir: input + width: '1' + # Read Data + - name: rdata + dir: input + width: "DW" + # Read Response + - name: rresp + dir: input + width: '1' + # Read ID + - name: rid + dir: input + width: '1' + # Read Last + - name: rlast + dir: input + width: '1' + # Read Data Valid + - name: rvalid + dir: input + width: '1' + + transaction_constraints: [] + transaction_vars: + - name: core_arready + type: logic + iscompare: 'True' + isrand: 'False' + - name: core_rdata + type: logic [DW-1:0] + iscompare: 'True' + isrand: 'False' + - name: core_rresp + type: axi_pkg::axi_burst_e + iscompare: 'True' + isrand: 'False' + - name: core_rid + type: logic [IW-1:0] + iscompare: 'True' + isrand: 'False' + - name: core_rlast + type: logic + iscompare: 'True' + isrand: 'False' + - name: core_rvalid + type: logic + iscompare: 'True' + isrand: 'False' + + "fuse_ctrl_prim_axi_write_out": + clock: "clk_i" + reset: "rst_ni" + reset_assertion_level: "False" + + parameters: + - name: AW + type: int + value: '32' + - name: DW + type: int + value: '32' + - name: IW + type: int + value: '3' + - name: UW + type: int + value: '32' + + ports: + # Address Write Channel Ready + - name: awready + dir: input + width: '1' + # Write Ready + - name: wready + dir: input + width: '1' + # Write Response + - name: bresp + dir: input + width: [$bits(axi_pkg::axi_burst_e)] + # Write Response ID + - name: bid + dir: input + width: '1' + # Write Response Valid + - name: bvalid + dir: input + width: '1' + + transaction_constraints: [] + transaction_vars: + - name: prim_awready + type: logic + iscompare: 'True' + isrand: 'False' + - name: prim_wready + type: logic + iscompare: 'True' + isrand: 'False' + - name: prim_bresp + type: axi_pkg::axi_burst_e + iscompare: 'True' + isrand: 'False' + - name: prim_bid + type: logic + iscompare: 'True' + isrand: 'False' + - name: prim_bvalid + type: logic + iscompare: 'True' + isrand: 'False' + + + "fuse_ctrl_prim_axi_read_out": + clock: "clk_i" + reset: "rst_ni" + reset_assertion_level: "False" + + parameters: + - name: AW + type: int + value: '32' + - name: DW + type: int + value: '32' + - name: IW + type: int + value: '3' + - name: UW + type: int + value: '32' + + ports: + # Address Read Channel Ready + - name: arready + dir: input + width: '1' + # Read Data + - name: rdata + dir: input + width: "DW" + # Read Response + - name: rresp + dir: input + width: '1' + # Read ID + - name: rid + dir: input + width: '1' + # Read Last + - name: rlast + dir: input + width: '1' + # Read Data Valid + - name: rvalid + dir: input + width: '1' + + transaction_constraints: [] + transaction_vars: + - name: prim_arready + type: logic + iscompare: 'True' + isrand: 'False' + - name: prim_rdata + type: logic [DW-1:0] + iscompare: 'True' + isrand: 'False' + - name: prim_rresp + type: axi_pkg::axi_burst_e + iscompare: 'True' + isrand: 'False' + - name: prim_rid + type: logic [IW-1:0] + iscompare: 'True' + isrand: 'False' + - name: prim_rlast + type: logic + iscompare: 'True' + isrand: 'False' + - name: prim_rvalid + type: logic + iscompare: 'True' + isrand: 'False' + + "fuse_ctrl_secreg_axi_read_out": + clock: "clk_i" + reset: "rst_ni" + reset_assertion_level: "False" + + parameters: + - name: AW + type: int + value: '32' + - name: DW + type: int + value: '32' + - name: IW + type: int + value: '3' + - name: UW + type: int + value: '32' + + ports: + # Address Read Channel Ready + - name: arready + dir: input + width: '1' + # Read Data + - name: rdata + dir: input + width: "DW" + # Read Response + - name: rresp + dir: input + width: '1' + # Read ID + - name: rid + dir: input + width: '1' + # Read Last + - name: rlast + dir: input + width: '1' + # Read Data Valid + - name: rvalid + dir: input + width: '1' + + transaction_constraints: [] + transaction_vars: + - name: secreg_arready + type: logic + iscompare: 'True' + isrand: 'False' + - name: secreg_rdata + type: logic [DW-1:0] + iscompare: 'True' + isrand: 'False' + - name: secreg_rresp + type: axi_pkg::axi_burst_e + iscompare: 'True' + isrand: 'False' + - name: secreg_rid + type: logic [IW-1:0] + iscompare: 'True' + isrand: 'False' + - name: secreg_rlast + type: logic + iscompare: 'True' + isrand: 'False' + - name: secreg_rvalid + type: logic + iscompare: 'True' + isrand: 'False' + + "fuse_ctrl_out": + clock: "clk_i" + reset: "rst_ni" + reset_assertion_level: "False" + + parameters: + - name: AlertSyncOn + type: int + value: '3' + - name: RndConstLfrSeed + type: caliptra_otp_ctrl_pkg::lfsr_seed_t + value: 'caliptra_otp_ctrl_pkg::RndCnstLfsrSeedDefault' + - name: RndCnstLfsrPerm + type: caliptra_otp_ctrl_pkg::lfsr_perm_t + value: 'caliptra_otp_ctrl_pkg::RndCnstLfsrPermDefault' + - name: MemInitFile + type: string + value: "\"\"" + #value: "\"/home/ws/caliptra/anjpar/ws1/chipsalliance/caliptra-rtl/src/fuse_ctrl/data/otp-img.2048.vmem\"" + + ports: + # EDN interface + - name: edn_o + dir: input + width: [$bits(edn_pkg::edn_req_t)] + # Interrupt Requests + - name: intr_otp_operation_done_o + dir: input + width: '1' + - name: intr_otp_error_o + dir: input + width: '1' + # Alerts + - name: alert_tx_o + dir: input + width: [ast_pkg::NumAlerts * $bits(caliptra_prim_alert_pkg::alert_tx_t)] + # Observability to AST + - name: otp_obs_o + dir: input + width: '8' + # Macro-specific power sequencing signal to AST + - name: otp_ast_pwr_seq_o + dir: input + width: [$bits(caliptra_otp_ctrl_pkg::otp_ast_req_t)] + + # Hardware config bits + - name: otp_broadcast_o + dir: input + width: [$bits(caliptra_otp_ctrl_part_pkg::otp_broadcast_t)] + + # Test-related GPIO output + - name: cio_test_o + dir: input + width: [caliptra_otp_ctrl_pkg::OtpTestVectWidth] + - name: cio_test_en_o + dir: input + width: [caliptra_otp_ctrl_pkg::OtpTestVectWidth] + + response_info: + data: [] + operation: 1'b0 + + transaction_constraints: [] + transaction_vars: + - name: pwr_otp_o + type: pwrmgr_pkg::pwr_otp_rsp_t + iscompare: 'True' + isrand: 'False' + + "fuse_ctrl_lc_otp_out": + clock: "clk_i" + reset: "rst_ni" + reset_assertion_level: "False" + + ports: + # Test register to Life Cycle TAP + - name: lc_otp_vendor_test_o + dir: input + width: [$bits(caliptra_otp_ctrl_pkg::lc_otp_vendor_test_rsp_t)] + # LC transition interface + - name: lc_otp_program_o + dir: input + width: [$bits(caliptra_otp_ctrl_pkg::lc_otp_program_rsp_t)] + # OTP broadcast output + - name: otp_lc_data_o + dir: input + width: [$bits(caliptra_otp_ctrl_pkg::otp_lc_data_t)] + + response_info: + data: [] + operation: 1'b0 + + transaction_constraints: [] + transaction_vars: + - name: otp_lc_data_o + type: caliptra_otp_ctrl_pkg::otp_lc_data_t + iscompare: 'True' + isrand: 'False' + + + + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/fuse_ctrl_util_comp_predictor.yaml b/src/fuse_ctrl/uvmf_fuse_ctrl/fuse_ctrl_util_comp_predictor.yaml new file mode 100644 index 0000000..108b3d9 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/fuse_ctrl_util_comp_predictor.yaml @@ -0,0 +1,64 @@ +uvmf: + util_components: + fuse_ctrl_predictor: + type: predictor + analysis_exports: + # RST + - name: fuse_ctrl_rst_in_agent_ae + type: 'fuse_ctrl_rst_in_transaction' + + # Writes + - name: fuse_ctrl_core_axi_write_in_agent_ae + type: 'fuse_ctrl_core_axi_write_in_transaction' + + - name: fuse_ctrl_prim_axi_write_in_agent_ae + type: 'fuse_ctrl_prim_axi_write_in_transaction' + + # Reads + - name: fuse_ctrl_core_axi_read_in_agent_ae + type: 'fuse_ctrl_core_axi_read_in_transaction' + + - name: fuse_ctrl_prim_axi_read_in_agent_ae + type: 'fuse_ctrl_prim_axi_read_in_transaction' + + - name: fuse_ctrl_secreg_axi_read_in_agent_ae + type: 'fuse_ctrl_secreg_axi_read_in_transaction' + + # OTP LC IF + - name: fuse_ctrl_lc_otp_in_agent_ae + type: 'fuse_ctrl_lc_otp_in_transaction' + + # OTP IF + - name: fuse_ctrl_in_agent_ae + type: 'fuse_ctrl_in_transaction' + + analysis_ports: + # Rst + - name: fuse_ctrl_rst_in_agent_ap + type: 'fuse_ctrl_rst_in_transaction' + + # Writes + - name: fuse_ctrl_core_axi_write_in_agent_ap + type: 'fuse_ctrl_core_axi_write_in_transaction' + + - name: fuse_ctrl_prim_axi_write_in_agent_ap + type: 'fuse_ctrl_prim_axi_write_in_transaction' + + # Reads + - name: fuse_ctrl_core_axi_read_in_agent_ap + type: 'fuse_ctrl_core_axi_read_in_transaction' + + - name: fuse_ctrl_prim_axi_read_in_agent_ap + type: 'fuse_ctrl_prim_axi_read_in_transaction' + + - name: fuse_ctrl_secreg_axi_read_in_agent_ap + type: 'fuse_ctrl_secreg_axi_read_in_transaction' + + # OTP LC IF + - name: fuse_ctrl_lc_otp_in_agent_ap + type: 'fuse_ctrl_lc_otp_in_transaction' + + # OTP IF + - name: fuse_ctrl_in_agent_ap + type: 'fuse_ctrl_in_transaction' + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/fuse_ctrl_util_comp_scoreboard.yaml b/src/fuse_ctrl/uvmf_fuse_ctrl/fuse_ctrl_util_comp_scoreboard.yaml new file mode 100644 index 0000000..6b440af --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/fuse_ctrl_util_comp_scoreboard.yaml @@ -0,0 +1,56 @@ +uvmf: + util_components: + fuse_ctrl_scoreboard: + type: scoreboard +# # Default APs + analysis_exports: + - name: fuse_ctrl_rst_in_agent_ae + type: 'fuse_ctrl_rst_in_transaction' + + - name: fuse_ctrl_core_axi_write_in_agent_ae + type: 'fuse_ctrl_core_axi_write_in_transaction' + + - name: fuse_ctrl_prim_axi_write_in_agent_ae + type: 'fuse_ctrl_prim_axi_write_in_transaction' + + - name: fuse_ctrl_core_axi_read_in_agent_ae + type: 'fuse_ctrl_core_axi_read_in_transaction' + + - name: fuse_ctrl_prim_axi_read_in_agent_ae + type: 'fuse_ctrl_prim_axi_read_in_transaction' + + - name: fuse_ctrl_secreg_axi_read_in_agent_ae + type: 'fuse_ctrl_secreg_axi_read_in_transaction' + + - name: fuse_ctrl_lc_otp_in_agent_ae + type: 'fuse_ctrl_lc_otp_in_transaction' + + - name: fuse_ctrl_in_agent_ae + type: 'fuse_ctrl_in_transaction' + #qvip_analysis_exports: + #- name: expected_ahb_analysis_export + # type: 'ahb_master_burst_transfer #(ahb_lite_slave_0_params::AHB_NUM_MASTERS, + # ahb_lite_slave_0_params::AHB_NUM_MASTER_BITS, + # ahb_lite_slave_0_params::AHB_NUM_SLAVES, + # ahb_lite_slave_0_params::AHB_ADDRESS_WIDTH, + # ahb_lite_slave_0_params::AHB_WDATA_WIDTH, + # ahb_lite_slave_0_params::AHB_RDATA_WIDTH)' + # - name: expected_apb_analysis_export + # type: 'apb3_host_apb3_transaction #(apb5_master_0_params::APB3_SLAVE_COUNT, + # apb5_master_0_params::APB3_PADDR_BIT_WIDTH, + # apb5_master_0_params::APB3_PWDATA_BIT_WIDTH, + # apb5_master_0_params::APB3_PRDATA_BIT_WIDTH)' + #- name: actual_ahb_analysis_export + # # type: 'mvc_sequence_item_base' + # type: 'ahb_master_burst_transfer #(ahb_lite_slave_0_params::AHB_NUM_MASTERS, + # ahb_lite_slave_0_params::AHB_NUM_MASTER_BITS, + # ahb_lite_slave_0_params::AHB_NUM_SLAVES, + # ahb_lite_slave_0_params::AHB_ADDRESS_WIDTH, + # ahb_lite_slave_0_params::AHB_WDATA_WIDTH, + # ahb_lite_slave_0_params::AHB_RDATA_WIDTH)' + # - name: actual_apb_analysis_export + # type: 'mvc_sequence_item_base' +# type: 'apb3_host_apb3_transaction #(apb5_master_0_params::APB3_SLAVE_COUNT, +# apb5_master_0_params::APB3_PADDR_BIT_WIDTH, +# apb5_master_0_params::APB3_PWDATA_BIT_WIDTH, +# apb5_master_0_params::APB3_PRDATA_BIT_WIDTH)' diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/run_yaml_uvmf_scripts.sh b/src/fuse_ctrl/uvmf_fuse_ctrl/run_yaml_uvmf_scripts.sh new file mode 100755 index 0000000..dedf0f3 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/run_yaml_uvmf_scripts.sh @@ -0,0 +1,12 @@ +#export UVMF_HOME='/home/cad/tools/mentor/uvmf/UVMF_2022.3' +python ${UVMF_HOME}/scripts/yaml2uvmf.py --merge_source uvmf_template_output \ + --merge_skip_missing_blocks \ + fuse_ctrl_global.yaml \ + fuse_ctrl_in_interfaces.yaml \ + fuse_ctrl_out_interfaces.yaml \ + fuse_ctrl_util_comp_predictor.yaml \ + fuse_ctrl_util_comp_scoreboard.yaml \ + fuse_ctrl_environment.yaml \ + fuse_ctrl_bench.yaml \ + -d uvmf_template_output_merged + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/.project b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/.project new file mode 100644 index 0000000..1462dce --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/.project @@ -0,0 +1,37 @@ + + + fuse_ctrl + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + verification_ip + 2 + UVMF_VIP_LIBRARY_HOME + + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D/verification_ip + + + + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/.svproject b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/.svproject new file mode 100644 index 0000000..9e84acf --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/docs/interfaces.csv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/docs/interfaces.csv new file mode 100644 index 0000000..d783ccf --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/docs/interfaces.csv @@ -0,0 +1,42 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +, +Interface Description, Interface Type, Interface Transaction, Interface Name, +fuse_ctrl_rst_in_agent, fuse_ctrl_rst_in_driver_bfm fuse_ctrl_rst_in_monitor_bfm, fuse_ctrl_rst_in_transaction, fuse_ctrl_rst_in_pkg_fuse_ctrl_rst_in_agent_BFM, +fuse_ctrl_rst_out_agent, fuse_ctrl_rst_out_driver_bfm fuse_ctrl_rst_out_monitor_bfm, fuse_ctrl_rst_out_transaction, fuse_ctrl_rst_out_pkg_fuse_ctrl_rst_out_agent_BFM, +fuse_ctrl_core_axi_write_in_if_agent, fuse_ctrl_core_axi_write_in_driver_bfm fuse_ctrl_core_axi_write_in_monitor_bfm, fuse_ctrl_core_axi_write_in_transaction, fuse_ctrl_core_axi_write_in_pkg_fuse_ctrl_core_axi_write_in_if_agent_BFM, +fuse_ctrl_core_axi_write_out_if_agent, fuse_ctrl_core_axi_write_out_driver_bfm fuse_ctrl_core_axi_write_out_monitor_bfm, fuse_ctrl_core_axi_write_out_transaction, fuse_ctrl_core_axi_write_out_pkg_fuse_ctrl_core_axi_write_out_if_agent_BFM, +fuse_ctrl_prim_axi_write_in_if_agent, fuse_ctrl_prim_axi_write_in_driver_bfm fuse_ctrl_prim_axi_write_in_monitor_bfm, fuse_ctrl_prim_axi_write_in_transaction, fuse_ctrl_prim_axi_write_in_pkg_fuse_ctrl_prim_axi_write_in_if_agent_BFM, +fuse_ctrl_prim_axi_write_out_if_agent, fuse_ctrl_prim_axi_write_out_driver_bfm fuse_ctrl_prim_axi_write_out_monitor_bfm, fuse_ctrl_prim_axi_write_out_transaction, fuse_ctrl_prim_axi_write_out_pkg_fuse_ctrl_prim_axi_write_out_if_agent_BFM, +fuse_ctrl_core_axi_read_in_if_agent, fuse_ctrl_core_axi_read_in_driver_bfm fuse_ctrl_core_axi_read_in_monitor_bfm, fuse_ctrl_core_axi_read_in_transaction, fuse_ctrl_core_axi_read_in_pkg_fuse_ctrl_core_axi_read_in_if_agent_BFM, +fuse_ctrl_core_axi_read_out_if_agent, fuse_ctrl_core_axi_read_out_driver_bfm fuse_ctrl_core_axi_read_out_monitor_bfm, fuse_ctrl_core_axi_read_out_transaction, fuse_ctrl_core_axi_read_out_pkg_fuse_ctrl_core_axi_read_out_if_agent_BFM, +fuse_ctrl_prim_axi_read_in_if_agent, fuse_ctrl_prim_axi_read_in_driver_bfm fuse_ctrl_prim_axi_read_in_monitor_bfm, fuse_ctrl_prim_axi_read_in_transaction, fuse_ctrl_prim_axi_read_in_pkg_fuse_ctrl_prim_axi_read_in_if_agent_BFM, +fuse_ctrl_prim_axi_read_out_if_agent, fuse_ctrl_prim_axi_read_out_driver_bfm fuse_ctrl_prim_axi_read_out_monitor_bfm, fuse_ctrl_prim_axi_read_out_transaction, fuse_ctrl_prim_axi_read_out_pkg_fuse_ctrl_prim_axi_read_out_if_agent_BFM, +fuse_ctrl_secreg_axi_read_in_if_agent, fuse_ctrl_secreg_axi_read_in_driver_bfm fuse_ctrl_secreg_axi_read_in_monitor_bfm, fuse_ctrl_secreg_axi_read_in_transaction, fuse_ctrl_secreg_axi_read_in_pkg_fuse_ctrl_secreg_axi_read_in_if_agent_BFM, +fuse_ctrl_secreg_axi_read_out_if_agent, fuse_ctrl_secreg_axi_read_out_driver_bfm fuse_ctrl_secreg_axi_read_out_monitor_bfm, fuse_ctrl_secreg_axi_read_out_transaction, fuse_ctrl_secreg_axi_read_out_pkg_fuse_ctrl_secreg_axi_read_out_if_agent_BFM, +fuse_ctrl_lc_otp_in_if_agent, fuse_ctrl_lc_otp_in_driver_bfm fuse_ctrl_lc_otp_in_monitor_bfm, fuse_ctrl_lc_otp_in_transaction, fuse_ctrl_lc_otp_in_pkg_fuse_ctrl_lc_otp_in_if_agent_BFM, +fuse_ctrl_lc_otp_out_if_agent, fuse_ctrl_lc_otp_out_driver_bfm fuse_ctrl_lc_otp_out_monitor_bfm, fuse_ctrl_lc_otp_out_transaction, fuse_ctrl_lc_otp_out_pkg_fuse_ctrl_lc_otp_out_if_agent_BFM, +fuse_ctrl_in_if_agent, fuse_ctrl_in_driver_bfm fuse_ctrl_in_monitor_bfm, fuse_ctrl_in_transaction, fuse_ctrl_in_pkg_fuse_ctrl_in_if_agent_BFM, +fuse_ctrl_out_if_agent, fuse_ctrl_out_driver_bfm fuse_ctrl_out_monitor_bfm, fuse_ctrl_out_transaction, fuse_ctrl_out_pkg_fuse_ctrl_out_if_agent_BFM, + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/fuse_ctrl_sve.F b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/fuse_ctrl_sve.F new file mode 100644 index 0000000..37457d7 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/fuse_ctrl_sve.F @@ -0,0 +1,42 @@ + +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + +// BFM Files +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_pkg_sve.F +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_pkg_sve.F +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_pkg_sve.F +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_pkg_sve.F +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_pkg_sve.F +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_pkg_sve.F +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_pkg_sve.F +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_pkg_sve.F +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_pkg_sve.F +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_pkg_sve.F +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_pkg_sve.F +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_pkg_sve.F +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_pkg_sve.F +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_pkg_sve.F +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_pkg_sve.F +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_pkg_sve.F + +// Environment Files +-F ${UVMF_VIP_LIBRARY_HOME}/environment_packages/fuse_ctrl_env_pkg/fuse_ctrl_env_pkg_sve.F + +// Bench Files ++incdir+./tb/tests +./tb/tests/fuse_ctrl_tests_pkg.sv + ++incdir+./tb/sequences +./tb/sequences/fuse_ctrl_sequences_pkg.sv + ++incdir+./tb/parameters +./tb/parameters/fuse_ctrl_parameters_pkg.sv + +./tb/testbench/hdl_top.sv +./tb/testbench/hvl_top.sv + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/rtl/dut.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/rtl/dut.compile new file mode 100644 index 0000000..9b0008f --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/rtl/dut.compile @@ -0,0 +1,6 @@ + +# pragma uvmf custom dut_compile_info begin +src: + - ./vhdl/vhdl_dut.vhd + - ./verilog/verilog_dut.v +# pragma uvmf custom dut_compile_info end diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/rtl/verilog/verilog_dut.v b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/rtl/verilog/verilog_dut.v new file mode 100644 index 0000000..9619844 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/rtl/verilog/verilog_dut.v @@ -0,0 +1,21 @@ +module verilog_dut(clk, rst, in_signal, out_signal); + +input clk; +input rst; +input in_signal; +output out_signal; + +reg out_signal_o; + +always @(posedge clk) begin + if (rst) begin + out_signal_o <= 0; + end + else begin + out_signal_o <= ~in_signal; + end + end + +assign out_signal = out_signal_o; + +endmodule diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/rtl/verilog/verilog_dut.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/rtl/verilog/verilog_dut.vinfo new file mode 100644 index 0000000..87e95f3 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/rtl/verilog/verilog_dut.vinfo @@ -0,0 +1 @@ +verilog_dut.v diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/rtl/vhdl/vhdl_dut.vhd b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/rtl/vhdl/vhdl_dut.vhd new file mode 100644 index 0000000..904aa37 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/rtl/vhdl/vhdl_dut.vhd @@ -0,0 +1,21 @@ +library ieee; +use ieee.std_logic_1164.all ; + +entity vhdl_dut is + port ( clk : in std_logic ; + rst : in std_logic ; + in_signal : in std_logic ; + out_signal :out std_logic + ); +end vhdl_dut; + +architecture rtl of vhdl_dut is + begin + P1: process + variable out_signal_o : std_logic; + begin + wait until clk'event and clk = '1'; + out_signal_o := in_signal; + out_signal <= out_signal_o; + end process; + end rtl; diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/sim/Makefile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/sim/Makefile new file mode 100644 index 0000000..7ca2e94 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/sim/Makefile @@ -0,0 +1,213 @@ + +# +#---------------------------------------------------------------------- +# +# DESCRIPTION: This makefile includes the shared makefile and contains +# bench level make targets. +# +#---------------------------------------------------------------------- + + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +# ********************************************************************************************* +# UVMF library directory: +# This variable points to the UVMF release where uvmf_base_pkg directory resides. +# This variable points to release code that is not user modified. +# This variable allows for UVMF release directories to reside independent of project related verification IP and project bench directories. +# This code below looks "upward" for directory starting with UVMF_* and returns first match for use with the release examples. +UVMF_HOME ?= ___PLEASE_SET_AN_ENVIRONMENT_VARIABLE_NAMED_UVMF_HOME_TO_POINT_TO_THE_UVMF_INSTALLATION___ + +# pragma uvmf custom exports begin +# +# Project(s) specific verification IP library: +# Directory where reusable verification packages for interfaces, environments, utilities, etc. reside. +# This variable allows for your verification IP to reside independent of project bench and UVMF release directories. +# For examples deployed with UVMF this will be $(UVMF_HOME)//verification_ip +export UVMF_VIP_LIBRARY_HOME ?= $(PWD)/../../../verification_ip +# +# Project specific bench: +# Directory where bench specific code is located. +# This variable allows for project_benches to reside independent of verification IP and UVMF release directories. +# For examples deployed with UVMF this will be $(UVMF_HOME)//project_benches/ +export UVMF_PROJECT_DIR ?= $(PWD)/.. +# +# +# pragma uvmf custom exports end +# ********************************************************************************************* + +## Check PATH for required vinfo scripts +PVAL := $(shell command -v make_filelist.py 2> /dev/null) +ifndef PVAL + MFLIST = $(UVMF_HOME)/scripts/make_filelist.py +else + MFLIST = make_filelist.py +endif + + +# Set test case specific Variables +TEST_NAME ?= test_top + +TEST_SEED ?= random +UVM_CLI_ARGS = + +# Usage of Veloce, etc. to be input by the user (subject to defaults) +USE_VELOCE ?= 0 + +# Usage of vinfo flow for generating file list +USE_VINFO ?= 0 + +# Usage of Veloce and Questa profilers +USE_VELOCE_PROFILER ?= 0 +USE_QUESTA_PROFILER ?= 0 + + +# Set project Variables +TEST_PLAN_NAME = fuse_ctrl_TestPlan +REPORTING_DO_FILE = fuse_ctrl_reports_script + + +# Include makefile that includes targets for UVM_VIP_Library packages +include $(UVMF_HOME)/scripts/Makefile + + + + +# Include all requisite interface package targets for this bench +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_in_pkg/Makefile +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_out_pkg/Makefile +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_write_in_pkg/Makefile +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_write_out_pkg/Makefile +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/Makefile +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/Makefile +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_read_in_pkg/Makefile +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_read_out_pkg/Makefile +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/Makefile +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/Makefile +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/Makefile +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/Makefile +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_lc_otp_in_pkg/Makefile +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_lc_otp_out_pkg/Makefile +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_in_pkg/Makefile +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_out_pkg/Makefile + +# Include all requisite environment package targets for this bench +include $(UVMF_VIP_LIBRARY_HOME)/environment_packages/fuse_ctrl_env_pkg/Makefile + + + +# Add to default compile/load/run arguments +VCOM_ARGS += + +# Note: vsim-3009 error can be eliminated by adding -timescale 1ps/1ps to VLOG_ARGS + +VLOG_ARGS += $(UVM_DISABLE_FILE_LINE_CMD) + +VELANALYZE_ARGS += +VELANALYZE_HVL_ARGS += + +BATCH_VOPT_ARGS += +DEBUG_VOPT_ARGS += +EXTRA_VOPT_TOPS += +COMMON_VSIM_ARGS += +COMMON_VSIM_ARGS += + + +BATCH_VSIM_ARGS += #-uvmcontrol=none +DEBUG_VSIM_ARGS += +EXTRA_VSIM_TOPS += + +# pragma uvmf custom additional_args begin +# pragma uvmf custom additional_args end + + +# Project bench package source +fuse_ctrl_PARAMETERS_PKG ?=\ +$(UVMF_PROJECT_DIR)/tb/parameters/fuse_ctrl_parameters_pkg.sv + + +fuse_ctrl_SEQUENCES_PKG ?=\ +$(UVMF_PROJECT_DIR)/tb/sequences/fuse_ctrl_sequences_pkg.sv + + +fuse_ctrl_TEST_PKG ?=\ +$(UVMF_PROJECT_DIR)/tb/tests/fuse_ctrl_tests_pkg.sv + +# pragma uvmf custom dut_files begin +# UVMF_CHANGE_ME : Reference Verilog DUT source. +fuse_ctrl_VERILOG_DUT ?=\ +$(UVMF_PROJECT_DIR)/rtl/verilog/verilog_dut.v + +# UVMF_CHANGE_ME : Reference VHDL DUT source. +fuse_ctrl_VHDL_DUT ?=\ +$(UVMF_PROJECT_DIR)/rtl/vhdl/vhdl_dut.vhd +# pragma uvmf custom dut_files end + + +# Project bench package targets +COMP_fuse_ctrl_PARAMETERS_PKG_TGT_0 = q_comp_fuse_ctrl_parameters_pkg +COMP_fuse_ctrl_PARAMETERS_PKG_TGT_1 = v_comp_fuse_ctrl_parameters_pkg +COMP_fuse_ctrl_PARAMETERS_PKG_TGT = $(COMP_fuse_ctrl_PARAMETERS_PKG_TGT_$(USE_VELOCE)) + +comp_fuse_ctrl_parameters_pkg: $(COMP_fuse_ctrl_PARAMETERS_PKG_TGT) + +q_comp_fuse_ctrl_parameters_pkg: + $(HVL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/parameters $(fuse_ctrl_PARAMETERS_PKG) + +v_comp_fuse_ctrl_parameters_pkg: q_comp_fuse_ctrl_parameters_pkg + $(HDL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/parameters $(fuse_ctrl_PARAMETERS_PKG) + + +comp_fuse_ctrl_sequence_pkg: + $(HVL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/sequences $(fuse_ctrl_SEQUENCES_PKG) + +comp_fuse_ctrl_tests_pkg: + $(HVL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/tests $(fuse_ctrl_TEST_PKG) + +# pragma uvmf custom dut_compile_make_target begin +# UVMF_CHANGE_ME : Add make target to compile your verilog dut here +comp_fuse_ctrl_verilog_dut: + echo "Compile your verilog DUT here" + $(HDL_COMP_CMD) $(fuse_ctrl_VERILOG_DUT) + +# UVMF_CHANGE_ME : Add make target to compile your vhdl dut here +comp_fuse_ctrl_vhdl_dut: + echo "Compile your vhdl DUT here" + $(HDL_COMP_CMD_VHDL) $(fuse_ctrl_VHDL_DUT) + +# UVMF_CHANGE_ME : Add make target to compile your dut here +comp_fuse_ctrl_dut: comp_fuse_ctrl_vhdl_dut comp_fuse_ctrl_verilog_dut +# pragma uvmf custom dut_compile_make_target end + + +BUILD_TGT_0 = make_build +BUILD_TGT_1 = vinfo_build +BUILD_TGT = $(BUILD_TGT_$(USE_VINFO)) + + +comp_hvl : comp_hvl_core + + +comp_hvl_core : \ + comp_fuse_ctrl_rst_in_pkg comp_fuse_ctrl_rst_out_pkg comp_fuse_ctrl_core_axi_write_in_pkg comp_fuse_ctrl_core_axi_write_out_pkg comp_fuse_ctrl_prim_axi_write_in_pkg comp_fuse_ctrl_prim_axi_write_out_pkg comp_fuse_ctrl_core_axi_read_in_pkg comp_fuse_ctrl_core_axi_read_out_pkg comp_fuse_ctrl_prim_axi_read_in_pkg comp_fuse_ctrl_prim_axi_read_out_pkg comp_fuse_ctrl_secreg_axi_read_in_pkg comp_fuse_ctrl_secreg_axi_read_out_pkg comp_fuse_ctrl_lc_otp_in_pkg comp_fuse_ctrl_lc_otp_out_pkg comp_fuse_ctrl_in_pkg comp_fuse_ctrl_out_pkg \ + comp_fuse_ctrl_env_pkg \ + comp_fuse_ctrl_parameters_pkg comp_fuse_ctrl_sequence_pkg comp_fuse_ctrl_tests_pkg + +comp_uvmf_core : comp_uvm_pkg comp_uvmf_base_pkg + +make_build: comp_fuse_ctrl_dut comp_uvmf_core comp_hvl comp_test_bench + +hvl_build: q_comp_fuse_ctrl_rst_in_pkg q_comp_fuse_ctrl_rst_out_pkg q_comp_fuse_ctrl_core_axi_write_in_pkg q_comp_fuse_ctrl_core_axi_write_out_pkg q_comp_fuse_ctrl_prim_axi_write_in_pkg q_comp_fuse_ctrl_prim_axi_write_out_pkg q_comp_fuse_ctrl_core_axi_read_in_pkg q_comp_fuse_ctrl_core_axi_read_out_pkg q_comp_fuse_ctrl_prim_axi_read_in_pkg q_comp_fuse_ctrl_prim_axi_read_out_pkg q_comp_fuse_ctrl_secreg_axi_read_in_pkg q_comp_fuse_ctrl_secreg_axi_read_out_pkg q_comp_fuse_ctrl_lc_otp_in_pkg q_comp_fuse_ctrl_lc_otp_out_pkg q_comp_fuse_ctrl_in_pkg q_comp_fuse_ctrl_out_pkg comp_fuse_ctrl_env_pkg comp_fuse_ctrl_sequence_pkg comp_fuse_ctrl_tests_pkg hvl_comp_testbench link optimize + + +vinfo_build: comp_fuse_ctrl_vhdl_dut build_hdl_vinfo build_hvl_vinfo $(VINFO_TGT) + + $(HDL_COMP_CMD) -F hdl.vf + $(VEL_COMP) + +build: $(BUILD_TGT) + +# pragma uvmf custom additional_targets begin +# pragma uvmf custom additional_targets end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/sim/bcr_testlist b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/sim/bcr_testlist new file mode 100644 index 0000000..4df4567 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/sim/bcr_testlist @@ -0,0 +1,19 @@ + + + +# Test list for use by RMDB file +# File syntax is +# TB_INFO { } { } +# TB ## All subsequent tests will run on this bench until a different "TB" line is seen +# TEST <1st_seed> ... +# If not enough seeds are provided then random seeds are used to pad +# If no repeat count is given, default is 1 +# pragma uvmf custom tb_info begin +TB_INFO fuse_ctrl { } { } +# pragma uvmf custom tb_info end +TB fuse_ctrl +# pragma uvmf custom regression_suite begin +TEST test_top 3 +# pragma uvmf custom regression_suite end + + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/sim/bcr_testlist.yaml b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/sim/bcr_testlist.yaml new file mode 100644 index 0000000..65b6be0 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/sim/bcr_testlist.yaml @@ -0,0 +1,44 @@ + + + +# YAML test list for use by RMDB file +# File syntax is +# uvmf_testlist: +# testbenches: +# - name: +# extra_build_options: +# extra_run_options: +# - name: +# ... +# - name: +# tests: +# - name: +# uvm_testname: (defaults to test_name) +# testbench: (defaults to last tb name seen) +# repeat: (defaults to 1) +# seeds: [,,...,] (defaults to all random) +# extra_test_options: +# - name: +# ... +# - name: +# include: +# - (relative path reference is to the including YAML file) +# - +# ... +# - + +uvmf_testlist: + testbenches: +# pragma uvmf custom tb_info begin + - name: fuse_ctrl + extra_build_options: "" + extra_run_options: "" +# pragma uvmf custom tb_info end + tests: + - testbench: fuse_ctrl +# pragma uvmf custom regression_suite begin + - name: test_top + repeat: 3 +# pragma uvmf custom regression_suite end + + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/sim/compile.do b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/sim/compile.do new file mode 100644 index 0000000..c361846 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/sim/compile.do @@ -0,0 +1,85 @@ + + +################################################################## +## ENVIRONMENT VARIABLES +################################################################## +quietly set ::env(UVMF_VIP_LIBRARY_HOME) ../../../verification_ip +quietly set ::env(UVMF_PROJECT_DIR) .. + +## Using VRM means that the build is occuring several more directories deeper underneath +## the sim directory, need to prepend some more '..' +if {[info exists ::env(VRM_BUILD)]} { + quietly set ::env(UVMF_VIP_LIBRARY_HOME) "../../../../../$::env(UVMF_VIP_LIBRARY_HOME)" + quietly set ::env(UVMF_PROJECT_DIR) "../../../../../$::env(UVMF_PROJECT_DIR)" +} +quietly set ::env(UVMF_VIP_LIBRARY_HOME) [file normalize $::env(UVMF_VIP_LIBRARY_HOME)] +quietly set ::env(UVMF_PROJECT_DIR) [file normalize $::env(UVMF_PROJECT_DIR)] +quietly echo "UVMF_VIP_LIBRARY_HOME = $::env(UVMF_VIP_LIBRARY_HOME)" +quietly echo "UVMF_PROJECT_DIR = $::env(UVMF_PROJECT_DIR)" + + +################################################################### +## HOUSEKEEPING : DELETE FILES THAT WILL BE REGENERATED +################################################################### +file delete -force *~ *.ucdb vsim.dbg *.vstf *.log work *.mem *.transcript.txt certe_dump.xml *.wlf covhtmlreport VRMDATA +file delete -force design.bin qwave.db dpiheader.h visualizer*.ses +file delete -force veloce.med veloce.wave veloce.map tbxbindings.h edsenv velrunopts.ini +file delete -force sv_connect.* + +################################################################### +## COMPILE DUT SOURCE CODE +################################################################### +vlib work +# pragma uvmf custom dut_compile_dofile_target begin +# UVMF_CHANGE_ME : Add commands to compile your dut here, replacing the default examples +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 $env(UVMF_PROJECT_DIR)/rtl/verilog/verilog_dut.v +vcom $env(UVMF_PROJECT_DIR)/rtl/vhdl/vhdl_dut.vhd +# pragma uvmf custom dut_compile_dofile_target end + +################################################################### +## COMPILE UVMF BASE/COMMON SOURCE CODE +################################################################### +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_HOME)/uvmf_base_pkg -F $env(UVMF_HOME)/uvmf_base_pkg/uvmf_base_pkg_filelist_hdl.f +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_HOME)/uvmf_base_pkg -F $env(UVMF_HOME)/uvmf_base_pkg/uvmf_base_pkg_filelist_hvl.f + + +################################################################### +## UVMF INTERFACE COMPILATION +################################################################### +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_in_pkg/compile.do +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_out_pkg/compile.do +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_write_in_pkg/compile.do +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_write_out_pkg/compile.do +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/compile.do +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/compile.do +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_read_in_pkg/compile.do +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_read_out_pkg/compile.do +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/compile.do +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/compile.do +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/compile.do +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/compile.do +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_lc_otp_in_pkg/compile.do +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_lc_otp_out_pkg/compile.do +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_in_pkg/compile.do +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_out_pkg/compile.do + +################################################################### +## UVMF ENVIRONMENT COMPILATION +################################################################### +do $env(UVMF_VIP_LIBRARY_HOME)/environment_packages/fuse_ctrl_env_pkg/compile.do + +################################################################### +## UVMF BENCHES COMPILATION +################################################################### +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/parameters $env(UVMF_PROJECT_DIR)/tb/parameters/fuse_ctrl_parameters_pkg.sv +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/sequences $env(UVMF_PROJECT_DIR)/tb/sequences/fuse_ctrl_sequences_pkg.sv +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/tests $env(UVMF_PROJECT_DIR)/tb/tests/fuse_ctrl_tests_pkg.sv + +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/testbench -F $env(UVMF_PROJECT_DIR)/tb/testbench/top_filelist_hdl.f +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/testbench -F $env(UVMF_PROJECT_DIR)/tb/testbench/top_filelist_hvl.f + +################################################################### +## OPTIMIZATION +################################################################### +vopt hvl_top hdl_top -o optimized_batch_top_tb +vopt +acc hvl_top hdl_top -o optimized_debug_top_tb diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/sim/hdl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/sim/hdl.compile new file mode 100644 index 0000000..8e7bd41 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/sim/hdl.compile @@ -0,0 +1,5 @@ +needs: +# pragma uvmf custom dut_compile_info begin + - ../rtl/dut.compile +# pragma uvmf custom dut_compile_info end + - ../tb/testbench/hdl_top.compile diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/sim/hdl.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/sim/hdl.vinfo new file mode 100644 index 0000000..da27ec7 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/sim/hdl.vinfo @@ -0,0 +1 @@ +@use $UVMF_PROJECT_DIR/tb/testbench/hdl_top.vinfo diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/sim/hvl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/sim/hvl.compile new file mode 100644 index 0000000..ce95254 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/sim/hvl.compile @@ -0,0 +1,2 @@ +needs: + - ../tb/testbench/hvl_top.compile diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/sim/hvl.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/sim/hvl.vinfo new file mode 100644 index 0000000..d22eff3 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/sim/hvl.vinfo @@ -0,0 +1 @@ +@use $UVMF_PROJECT_DIR/tb/testbench/hvl_top.vinfo diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/sim/run.do b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/sim/run.do new file mode 100644 index 0000000..101ddc4 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/sim/run.do @@ -0,0 +1,21 @@ + + +quietly set svLibs "" +quietly set extra_vsim_args "" + +################################################################### +## Check for additional vsim arguments passed using env var $UVMF_EXTRA_VSIM_ARGS +################################################################### +if {[info exists ::env(UVMF_EXTRA_VSIM_ARGS)]} { + echo "Adding more args to vsim command" + quietly set extra_vsim_args $::env(UVMF_EXTRA_VSIM_ARGS) +} + +################################################################## +## Launch Questa : generate vsim command line and execute +################################################################## +# pragma uvmf custom dut_run_dofile_target begin +# UVMF_CHANGE_ME : Change the UVM_TESTNAME plusarg to run a different test +quietly set cmd [format "vsim -i -sv_seed random +UVM_TESTNAME=test_top +UVM_VERBOSITY=UVM_HIGH -permit_unmatched_virtual_intf +notimingchecks -suppress 8887 %s %s -uvmcontrol=all -msgmode both -classdebug -assertdebug +uvm_set_config_int=*,enable_transaction_viewing,1 -do { set NoQuitOnFinish 1; onbreak {resume}; run 0; do wave.do; set PrefSource(OpenOnBreak) 0; radix hex showbase; } optimized_debug_top_tb" $svLibs $extra_vsim_args] +# pragma uvmf custom dut_run_dofile_target end +eval $cmd diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/sim/tbx.config b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/sim/tbx.config new file mode 100644 index 0000000..eec5816 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/sim/tbx.config @@ -0,0 +1,10 @@ + + + + + +comp -questa +velsyn -D1S +rtlc -allow_4ST + + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/sim/testlist b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/sim/testlist new file mode 100644 index 0000000..0c62297 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/sim/testlist @@ -0,0 +1,20 @@ + + + + +# Test list for use by RMDB file +# File syntax is +# TB_INFO { } { } +# TB ## All subsequent tests will run on this bench until a different "TB" line is seen +# TEST <1st_seed> ... +# If not enough seeds are provided then random seeds are used to pad +# If no repeat count is given, default is 1 +# pragma uvmf custom tb_info begin +TB_INFO fuse_ctrl { UVMF_VIP_LIBRARY_HOME=../../../../../../../../verification_ip UVMF_PROJECT_DIR=../../../../../../../fuse_ctrl } { } +# pragma uvmf custom tb_info end +TB fuse_ctrl +# pragma uvmf custom regression_suite begin +TEST test_top 3 +# pragma uvmf custom regression_suite end + + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/sim/testlist.yaml b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/sim/testlist.yaml new file mode 100644 index 0000000..6236cc7 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/sim/testlist.yaml @@ -0,0 +1,44 @@ + + + +# YAML test list for use by RMDB file +# File syntax is +# uvmf_testlist: +# testbenches: +# - name: +# extra_build_options: +# extra_run_options: +# - name: +# ... +# - name: +# tests: +# - name: +# uvm_testname: (defaults to test_name) +# testbench: (defaults to last tb name seen) +# repeat: (defaults to 1) +# seeds: [,,...,] (defaults to all random) +# extra_test_options: +# - name: +# ... +# - name: +# include: +# - (relative path reference is to the including YAML file) +# - +# ... +# - + +uvmf_testlist: + testbenches: +# pragma uvmf custom tb_info begin + - name: fuse_ctrl + extra_build_options: "UVMF_VIP_LIBRARY_HOME=../../../../../../../../verification_ip UVMF_PROJECT_DIR=../../../../../../../fuse_ctrl" + extra_run_options: "" +# pragma uvmf custom tb_info end + tests: + - testbench: fuse_ctrl +# pragma uvmf custom regression_suite begin + - name: test_top + repeat: 3 +# pragma uvmf custom regression_suite end + + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/sim/top.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/sim/top.compile new file mode 100644 index 0000000..efd51c0 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/sim/top.compile @@ -0,0 +1,3 @@ +needs: + - hvl.compile + - hdl.compile diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/sim/veloce.config b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/sim/veloce.config new file mode 100644 index 0000000..d097515 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/sim/veloce.config @@ -0,0 +1,26 @@ + + + + + +# pragma uvmf custom additional begin +comp -num_boards 1 +comp -hvl questa +# Please choose the correct emulator type code for +# comp -platform command or else velcomp will fail +# Available types are: +# - Veloce2 Quattro: D2 +# - Veloce2 Maximus: D2M +# - Veloce Strato TiL, Ti, and Mi: Strato +# - Veloce Strato M and Strato T: StratoM +# - comp -platform +comp -platform Strato + +rtlc -enable_tbx_pragma_checks +rtlc -allow_4ST +rtlc -allow_MDR +rtlc -compile_display +rtlc -xwave_siglist xwaves.sigs +# pragma uvmf custom additional end + + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/sim/viswave.do b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/sim/viswave.do new file mode 100644 index 0000000..db43b44 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/sim/viswave.do @@ -0,0 +1,106 @@ + + +onerror resume +wave tags F0 +wave update off + +wave spacer -backgroundcolor Salmon { fuse_ctrl_rst_in_agent } +wave add uvm_test_top.environment.fuse_ctrl_rst_in_agent.fuse_ctrl_rst_in_agent_monitor.txn_stream -radix string -tag F0 +wave group fuse_ctrl_rst_in_agent_bus +wave add -group fuse_ctrl_rst_in_agent_bus hdl_top.fuse_ctrl_rst_in_agent_bus.* -radix hexadecimal -tag F0 +wave group fuse_ctrl_rst_in_agent_bus -collapse +wave insertion [expr [wave index insertpoint] +1] +wave spacer -backgroundcolor Salmon { fuse_ctrl_rst_out_agent } +wave add uvm_test_top.environment.fuse_ctrl_rst_out_agent.fuse_ctrl_rst_out_agent_monitor.txn_stream -radix string -tag F0 +wave group fuse_ctrl_rst_out_agent_bus +wave add -group fuse_ctrl_rst_out_agent_bus hdl_top.fuse_ctrl_rst_out_agent_bus.* -radix hexadecimal -tag F0 +wave group fuse_ctrl_rst_out_agent_bus -collapse +wave insertion [expr [wave index insertpoint] +1] +wave spacer -backgroundcolor Salmon { fuse_ctrl_core_axi_write_in_if_agent } +wave add uvm_test_top.environment.fuse_ctrl_core_axi_write_in_if_agent.fuse_ctrl_core_axi_write_in_if_agent_monitor.txn_stream -radix string -tag F0 +wave group fuse_ctrl_core_axi_write_in_if_agent_bus +wave add -group fuse_ctrl_core_axi_write_in_if_agent_bus hdl_top.fuse_ctrl_core_axi_write_in_if_agent_bus.* -radix hexadecimal -tag F0 +wave group fuse_ctrl_core_axi_write_in_if_agent_bus -collapse +wave insertion [expr [wave index insertpoint] +1] +wave spacer -backgroundcolor Salmon { fuse_ctrl_core_axi_write_out_if_agent } +wave add uvm_test_top.environment.fuse_ctrl_core_axi_write_out_if_agent.fuse_ctrl_core_axi_write_out_if_agent_monitor.txn_stream -radix string -tag F0 +wave group fuse_ctrl_core_axi_write_out_if_agent_bus +wave add -group fuse_ctrl_core_axi_write_out_if_agent_bus hdl_top.fuse_ctrl_core_axi_write_out_if_agent_bus.* -radix hexadecimal -tag F0 +wave group fuse_ctrl_core_axi_write_out_if_agent_bus -collapse +wave insertion [expr [wave index insertpoint] +1] +wave spacer -backgroundcolor Salmon { fuse_ctrl_prim_axi_write_in_if_agent } +wave add uvm_test_top.environment.fuse_ctrl_prim_axi_write_in_if_agent.fuse_ctrl_prim_axi_write_in_if_agent_monitor.txn_stream -radix string -tag F0 +wave group fuse_ctrl_prim_axi_write_in_if_agent_bus +wave add -group fuse_ctrl_prim_axi_write_in_if_agent_bus hdl_top.fuse_ctrl_prim_axi_write_in_if_agent_bus.* -radix hexadecimal -tag F0 +wave group fuse_ctrl_prim_axi_write_in_if_agent_bus -collapse +wave insertion [expr [wave index insertpoint] +1] +wave spacer -backgroundcolor Salmon { fuse_ctrl_prim_axi_write_out_if_agent } +wave add uvm_test_top.environment.fuse_ctrl_prim_axi_write_out_if_agent.fuse_ctrl_prim_axi_write_out_if_agent_monitor.txn_stream -radix string -tag F0 +wave group fuse_ctrl_prim_axi_write_out_if_agent_bus +wave add -group fuse_ctrl_prim_axi_write_out_if_agent_bus hdl_top.fuse_ctrl_prim_axi_write_out_if_agent_bus.* -radix hexadecimal -tag F0 +wave group fuse_ctrl_prim_axi_write_out_if_agent_bus -collapse +wave insertion [expr [wave index insertpoint] +1] +wave spacer -backgroundcolor Salmon { fuse_ctrl_core_axi_read_in_if_agent } +wave add uvm_test_top.environment.fuse_ctrl_core_axi_read_in_if_agent.fuse_ctrl_core_axi_read_in_if_agent_monitor.txn_stream -radix string -tag F0 +wave group fuse_ctrl_core_axi_read_in_if_agent_bus +wave add -group fuse_ctrl_core_axi_read_in_if_agent_bus hdl_top.fuse_ctrl_core_axi_read_in_if_agent_bus.* -radix hexadecimal -tag F0 +wave group fuse_ctrl_core_axi_read_in_if_agent_bus -collapse +wave insertion [expr [wave index insertpoint] +1] +wave spacer -backgroundcolor Salmon { fuse_ctrl_core_axi_read_out_if_agent } +wave add uvm_test_top.environment.fuse_ctrl_core_axi_read_out_if_agent.fuse_ctrl_core_axi_read_out_if_agent_monitor.txn_stream -radix string -tag F0 +wave group fuse_ctrl_core_axi_read_out_if_agent_bus +wave add -group fuse_ctrl_core_axi_read_out_if_agent_bus hdl_top.fuse_ctrl_core_axi_read_out_if_agent_bus.* -radix hexadecimal -tag F0 +wave group fuse_ctrl_core_axi_read_out_if_agent_bus -collapse +wave insertion [expr [wave index insertpoint] +1] +wave spacer -backgroundcolor Salmon { fuse_ctrl_prim_axi_read_in_if_agent } +wave add uvm_test_top.environment.fuse_ctrl_prim_axi_read_in_if_agent.fuse_ctrl_prim_axi_read_in_if_agent_monitor.txn_stream -radix string -tag F0 +wave group fuse_ctrl_prim_axi_read_in_if_agent_bus +wave add -group fuse_ctrl_prim_axi_read_in_if_agent_bus hdl_top.fuse_ctrl_prim_axi_read_in_if_agent_bus.* -radix hexadecimal -tag F0 +wave group fuse_ctrl_prim_axi_read_in_if_agent_bus -collapse +wave insertion [expr [wave index insertpoint] +1] +wave spacer -backgroundcolor Salmon { fuse_ctrl_prim_axi_read_out_if_agent } +wave add uvm_test_top.environment.fuse_ctrl_prim_axi_read_out_if_agent.fuse_ctrl_prim_axi_read_out_if_agent_monitor.txn_stream -radix string -tag F0 +wave group fuse_ctrl_prim_axi_read_out_if_agent_bus +wave add -group fuse_ctrl_prim_axi_read_out_if_agent_bus hdl_top.fuse_ctrl_prim_axi_read_out_if_agent_bus.* -radix hexadecimal -tag F0 +wave group fuse_ctrl_prim_axi_read_out_if_agent_bus -collapse +wave insertion [expr [wave index insertpoint] +1] +wave spacer -backgroundcolor Salmon { fuse_ctrl_secreg_axi_read_in_if_agent } +wave add uvm_test_top.environment.fuse_ctrl_secreg_axi_read_in_if_agent.fuse_ctrl_secreg_axi_read_in_if_agent_monitor.txn_stream -radix string -tag F0 +wave group fuse_ctrl_secreg_axi_read_in_if_agent_bus +wave add -group fuse_ctrl_secreg_axi_read_in_if_agent_bus hdl_top.fuse_ctrl_secreg_axi_read_in_if_agent_bus.* -radix hexadecimal -tag F0 +wave group fuse_ctrl_secreg_axi_read_in_if_agent_bus -collapse +wave insertion [expr [wave index insertpoint] +1] +wave spacer -backgroundcolor Salmon { fuse_ctrl_secreg_axi_read_out_if_agent } +wave add uvm_test_top.environment.fuse_ctrl_secreg_axi_read_out_if_agent.fuse_ctrl_secreg_axi_read_out_if_agent_monitor.txn_stream -radix string -tag F0 +wave group fuse_ctrl_secreg_axi_read_out_if_agent_bus +wave add -group fuse_ctrl_secreg_axi_read_out_if_agent_bus hdl_top.fuse_ctrl_secreg_axi_read_out_if_agent_bus.* -radix hexadecimal -tag F0 +wave group fuse_ctrl_secreg_axi_read_out_if_agent_bus -collapse +wave insertion [expr [wave index insertpoint] +1] +wave spacer -backgroundcolor Salmon { fuse_ctrl_lc_otp_in_if_agent } +wave add uvm_test_top.environment.fuse_ctrl_lc_otp_in_if_agent.fuse_ctrl_lc_otp_in_if_agent_monitor.txn_stream -radix string -tag F0 +wave group fuse_ctrl_lc_otp_in_if_agent_bus +wave add -group fuse_ctrl_lc_otp_in_if_agent_bus hdl_top.fuse_ctrl_lc_otp_in_if_agent_bus.* -radix hexadecimal -tag F0 +wave group fuse_ctrl_lc_otp_in_if_agent_bus -collapse +wave insertion [expr [wave index insertpoint] +1] +wave spacer -backgroundcolor Salmon { fuse_ctrl_lc_otp_out_if_agent } +wave add uvm_test_top.environment.fuse_ctrl_lc_otp_out_if_agent.fuse_ctrl_lc_otp_out_if_agent_monitor.txn_stream -radix string -tag F0 +wave group fuse_ctrl_lc_otp_out_if_agent_bus +wave add -group fuse_ctrl_lc_otp_out_if_agent_bus hdl_top.fuse_ctrl_lc_otp_out_if_agent_bus.* -radix hexadecimal -tag F0 +wave group fuse_ctrl_lc_otp_out_if_agent_bus -collapse +wave insertion [expr [wave index insertpoint] +1] +wave spacer -backgroundcolor Salmon { fuse_ctrl_in_if_agent } +wave add uvm_test_top.environment.fuse_ctrl_in_if_agent.fuse_ctrl_in_if_agent_monitor.txn_stream -radix string -tag F0 +wave group fuse_ctrl_in_if_agent_bus +wave add -group fuse_ctrl_in_if_agent_bus hdl_top.fuse_ctrl_in_if_agent_bus.* -radix hexadecimal -tag F0 +wave group fuse_ctrl_in_if_agent_bus -collapse +wave insertion [expr [wave index insertpoint] +1] +wave spacer -backgroundcolor Salmon { fuse_ctrl_out_if_agent } +wave add uvm_test_top.environment.fuse_ctrl_out_if_agent.fuse_ctrl_out_if_agent_monitor.txn_stream -radix string -tag F0 +wave group fuse_ctrl_out_if_agent_bus +wave add -group fuse_ctrl_out_if_agent_bus hdl_top.fuse_ctrl_out_if_agent_bus.* -radix hexadecimal -tag F0 +wave group fuse_ctrl_out_if_agent_bus -collapse +wave insertion [expr [wave index insertpoint] +1] + +wave update on +WaveSetStreamView + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/sim/wave.do b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/sim/wave.do new file mode 100644 index 0000000..1ec9959 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/sim/wave.do @@ -0,0 +1,72 @@ + + +onerror {resume} +quietly WaveActivateNextPane {} 0 + +add wave -noupdate -divider fuse_ctrl_rst_in_agent +add wave -noupdate /uvm_root/uvm_test_top/environment/fuse_ctrl_rst_in_agent/fuse_ctrl_rst_in_agent_monitor/txn_stream +add wave -noupdate -group fuse_ctrl_rst_in_agent_bus /hdl_top/fuse_ctrl_rst_in_agent_bus/* +add wave -noupdate -divider fuse_ctrl_rst_out_agent +add wave -noupdate /uvm_root/uvm_test_top/environment/fuse_ctrl_rst_out_agent/fuse_ctrl_rst_out_agent_monitor/txn_stream +add wave -noupdate -group fuse_ctrl_rst_out_agent_bus /hdl_top/fuse_ctrl_rst_out_agent_bus/* +add wave -noupdate -divider fuse_ctrl_core_axi_write_in_if_agent +add wave -noupdate /uvm_root/uvm_test_top/environment/fuse_ctrl_core_axi_write_in_if_agent/fuse_ctrl_core_axi_write_in_if_agent_monitor/txn_stream +add wave -noupdate -group fuse_ctrl_core_axi_write_in_if_agent_bus /hdl_top/fuse_ctrl_core_axi_write_in_if_agent_bus/* +add wave -noupdate -divider fuse_ctrl_core_axi_write_out_if_agent +add wave -noupdate /uvm_root/uvm_test_top/environment/fuse_ctrl_core_axi_write_out_if_agent/fuse_ctrl_core_axi_write_out_if_agent_monitor/txn_stream +add wave -noupdate -group fuse_ctrl_core_axi_write_out_if_agent_bus /hdl_top/fuse_ctrl_core_axi_write_out_if_agent_bus/* +add wave -noupdate -divider fuse_ctrl_prim_axi_write_in_if_agent +add wave -noupdate /uvm_root/uvm_test_top/environment/fuse_ctrl_prim_axi_write_in_if_agent/fuse_ctrl_prim_axi_write_in_if_agent_monitor/txn_stream +add wave -noupdate -group fuse_ctrl_prim_axi_write_in_if_agent_bus /hdl_top/fuse_ctrl_prim_axi_write_in_if_agent_bus/* +add wave -noupdate -divider fuse_ctrl_prim_axi_write_out_if_agent +add wave -noupdate /uvm_root/uvm_test_top/environment/fuse_ctrl_prim_axi_write_out_if_agent/fuse_ctrl_prim_axi_write_out_if_agent_monitor/txn_stream +add wave -noupdate -group fuse_ctrl_prim_axi_write_out_if_agent_bus /hdl_top/fuse_ctrl_prim_axi_write_out_if_agent_bus/* +add wave -noupdate -divider fuse_ctrl_core_axi_read_in_if_agent +add wave -noupdate /uvm_root/uvm_test_top/environment/fuse_ctrl_core_axi_read_in_if_agent/fuse_ctrl_core_axi_read_in_if_agent_monitor/txn_stream +add wave -noupdate -group fuse_ctrl_core_axi_read_in_if_agent_bus /hdl_top/fuse_ctrl_core_axi_read_in_if_agent_bus/* +add wave -noupdate -divider fuse_ctrl_core_axi_read_out_if_agent +add wave -noupdate /uvm_root/uvm_test_top/environment/fuse_ctrl_core_axi_read_out_if_agent/fuse_ctrl_core_axi_read_out_if_agent_monitor/txn_stream +add wave -noupdate -group fuse_ctrl_core_axi_read_out_if_agent_bus /hdl_top/fuse_ctrl_core_axi_read_out_if_agent_bus/* +add wave -noupdate -divider fuse_ctrl_prim_axi_read_in_if_agent +add wave -noupdate /uvm_root/uvm_test_top/environment/fuse_ctrl_prim_axi_read_in_if_agent/fuse_ctrl_prim_axi_read_in_if_agent_monitor/txn_stream +add wave -noupdate -group fuse_ctrl_prim_axi_read_in_if_agent_bus /hdl_top/fuse_ctrl_prim_axi_read_in_if_agent_bus/* +add wave -noupdate -divider fuse_ctrl_prim_axi_read_out_if_agent +add wave -noupdate /uvm_root/uvm_test_top/environment/fuse_ctrl_prim_axi_read_out_if_agent/fuse_ctrl_prim_axi_read_out_if_agent_monitor/txn_stream +add wave -noupdate -group fuse_ctrl_prim_axi_read_out_if_agent_bus /hdl_top/fuse_ctrl_prim_axi_read_out_if_agent_bus/* +add wave -noupdate -divider fuse_ctrl_secreg_axi_read_in_if_agent +add wave -noupdate /uvm_root/uvm_test_top/environment/fuse_ctrl_secreg_axi_read_in_if_agent/fuse_ctrl_secreg_axi_read_in_if_agent_monitor/txn_stream +add wave -noupdate -group fuse_ctrl_secreg_axi_read_in_if_agent_bus /hdl_top/fuse_ctrl_secreg_axi_read_in_if_agent_bus/* +add wave -noupdate -divider fuse_ctrl_secreg_axi_read_out_if_agent +add wave -noupdate /uvm_root/uvm_test_top/environment/fuse_ctrl_secreg_axi_read_out_if_agent/fuse_ctrl_secreg_axi_read_out_if_agent_monitor/txn_stream +add wave -noupdate -group fuse_ctrl_secreg_axi_read_out_if_agent_bus /hdl_top/fuse_ctrl_secreg_axi_read_out_if_agent_bus/* +add wave -noupdate -divider fuse_ctrl_lc_otp_in_if_agent +add wave -noupdate /uvm_root/uvm_test_top/environment/fuse_ctrl_lc_otp_in_if_agent/fuse_ctrl_lc_otp_in_if_agent_monitor/txn_stream +add wave -noupdate -group fuse_ctrl_lc_otp_in_if_agent_bus /hdl_top/fuse_ctrl_lc_otp_in_if_agent_bus/* +add wave -noupdate -divider fuse_ctrl_lc_otp_out_if_agent +add wave -noupdate /uvm_root/uvm_test_top/environment/fuse_ctrl_lc_otp_out_if_agent/fuse_ctrl_lc_otp_out_if_agent_monitor/txn_stream +add wave -noupdate -group fuse_ctrl_lc_otp_out_if_agent_bus /hdl_top/fuse_ctrl_lc_otp_out_if_agent_bus/* +add wave -noupdate -divider fuse_ctrl_in_if_agent +add wave -noupdate /uvm_root/uvm_test_top/environment/fuse_ctrl_in_if_agent/fuse_ctrl_in_if_agent_monitor/txn_stream +add wave -noupdate -group fuse_ctrl_in_if_agent_bus /hdl_top/fuse_ctrl_in_if_agent_bus/* +add wave -noupdate -divider fuse_ctrl_out_if_agent +add wave -noupdate /uvm_root/uvm_test_top/environment/fuse_ctrl_out_if_agent/fuse_ctrl_out_if_agent_monitor/txn_stream +add wave -noupdate -group fuse_ctrl_out_if_agent_bus /hdl_top/fuse_ctrl_out_if_agent_bus/* + +TreeUpdate [SetDefaultTree] +quietly wave cursor active 0 +configure wave -namecolwidth 472 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {27 ns} {168 ns} + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/sim/xwaves.sigs b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/sim/xwaves.sigs new file mode 100644 index 0000000..d75f0a5 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/sim/xwaves.sigs @@ -0,0 +1,17 @@ + + + + + +# pragma uvmf custom additional begin + +Group All + +#Top level signals +hdl_top.* +#Add additional levels or individual signals as needed +hdl_top.*.* + +# pragma uvmf custom additional end + + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/parameters/fuse_ctrl_parameters_pkg.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/parameters/fuse_ctrl_parameters_pkg.compile new file mode 100644 index 0000000..0c6b841 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/parameters/fuse_ctrl_parameters_pkg.compile @@ -0,0 +1,4 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +src: + - fuse_ctrl_parameters_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/parameters/fuse_ctrl_parameters_pkg.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/parameters/fuse_ctrl_parameters_pkg.sv new file mode 100644 index 0000000..df84a8b --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/parameters/fuse_ctrl_parameters_pkg.sv @@ -0,0 +1,66 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This package contains test level parameters +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + +package fuse_ctrl_parameters_pkg; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + + // These parameters are used to uniquely identify each interface. The monitor_bfm and + // driver_bfm are placed into and retrieved from the uvm_config_db using these string + // names as the field_name. The parameter is also used to enable transaction viewing + // from the command line for selected interfaces using the UVM command line processing. + parameter string fuse_ctrl_rst_in_agent_BFM = "fuse_ctrl_rst_in_agent_BFM"; /* [0] */ + parameter string fuse_ctrl_rst_out_agent_BFM = "fuse_ctrl_rst_out_agent_BFM"; /* [1] */ + parameter string fuse_ctrl_core_axi_write_in_if_agent_BFM = "fuse_ctrl_core_axi_write_in_if_agent_BFM"; /* [2] */ + parameter string fuse_ctrl_core_axi_write_out_if_agent_BFM = "fuse_ctrl_core_axi_write_out_if_agent_BFM"; /* [3] */ + parameter string fuse_ctrl_prim_axi_write_in_if_agent_BFM = "fuse_ctrl_prim_axi_write_in_if_agent_BFM"; /* [4] */ + parameter string fuse_ctrl_prim_axi_write_out_if_agent_BFM = "fuse_ctrl_prim_axi_write_out_if_agent_BFM"; /* [5] */ + parameter string fuse_ctrl_core_axi_read_in_if_agent_BFM = "fuse_ctrl_core_axi_read_in_if_agent_BFM"; /* [6] */ + parameter string fuse_ctrl_core_axi_read_out_if_agent_BFM = "fuse_ctrl_core_axi_read_out_if_agent_BFM"; /* [7] */ + parameter string fuse_ctrl_prim_axi_read_in_if_agent_BFM = "fuse_ctrl_prim_axi_read_in_if_agent_BFM"; /* [8] */ + parameter string fuse_ctrl_prim_axi_read_out_if_agent_BFM = "fuse_ctrl_prim_axi_read_out_if_agent_BFM"; /* [9] */ + parameter string fuse_ctrl_secreg_axi_read_in_if_agent_BFM = "fuse_ctrl_secreg_axi_read_in_if_agent_BFM"; /* [10] */ + parameter string fuse_ctrl_secreg_axi_read_out_if_agent_BFM = "fuse_ctrl_secreg_axi_read_out_if_agent_BFM"; /* [11] */ + parameter string fuse_ctrl_lc_otp_in_if_agent_BFM = "fuse_ctrl_lc_otp_in_if_agent_BFM"; /* [12] */ + parameter string fuse_ctrl_lc_otp_out_if_agent_BFM = "fuse_ctrl_lc_otp_out_if_agent_BFM"; /* [13] */ + parameter string fuse_ctrl_in_if_agent_BFM = "fuse_ctrl_in_if_agent_BFM"; /* [14] */ + parameter string fuse_ctrl_out_if_agent_BFM = "fuse_ctrl_out_if_agent_BFM"; /* [15] */ + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/parameters/fuse_ctrl_parameters_pkg.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/parameters/fuse_ctrl_parameters_pkg.vinfo new file mode 100644 index 0000000..3bd4d7f --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/parameters/fuse_ctrl_parameters_pkg.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +fuse_ctrl_parameters_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/sequences/fuse_ctrl_sequences_pkg.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/sequences/fuse_ctrl_sequences_pkg.compile new file mode 100644 index 0000000..85c9189 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/sequences/fuse_ctrl_sequences_pkg.compile @@ -0,0 +1,22 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out.compile + - ../../../../verification_ip/environment_packages/fuse_ctrl_env_pkg/fuse_ctrl_env_pkg.compile + - ../parameters/fuse_ctrl_parameters_pkg.compile +src: + - fuse_ctrl_sequences_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/sequences/fuse_ctrl_sequences_pkg.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/sequences/fuse_ctrl_sequences_pkg.sv new file mode 100644 index 0000000..3ebdc90 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/sequences/fuse_ctrl_sequences_pkg.sv @@ -0,0 +1,93 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This package includes all high level sequence classes used +// in the environment. These include utility sequences and top +// level sequences. +// +// CONTAINS: +// - +// - +// +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// + +package fuse_ctrl_sequences_pkg; + import uvm_pkg::*; + import uvmf_base_pkg::*; + import fuse_ctrl_rst_in_pkg::*; + import fuse_ctrl_rst_in_pkg_hdl::*; + import fuse_ctrl_rst_out_pkg::*; + import fuse_ctrl_rst_out_pkg_hdl::*; + import fuse_ctrl_core_axi_write_in_pkg::*; + import fuse_ctrl_core_axi_write_in_pkg_hdl::*; + import fuse_ctrl_core_axi_write_out_pkg::*; + import fuse_ctrl_core_axi_write_out_pkg_hdl::*; + import fuse_ctrl_prim_axi_write_in_pkg::*; + import fuse_ctrl_prim_axi_write_in_pkg_hdl::*; + import fuse_ctrl_prim_axi_write_out_pkg::*; + import fuse_ctrl_prim_axi_write_out_pkg_hdl::*; + import fuse_ctrl_core_axi_read_in_pkg::*; + import fuse_ctrl_core_axi_read_in_pkg_hdl::*; + import fuse_ctrl_core_axi_read_out_pkg::*; + import fuse_ctrl_core_axi_read_out_pkg_hdl::*; + import fuse_ctrl_prim_axi_read_in_pkg::*; + import fuse_ctrl_prim_axi_read_in_pkg_hdl::*; + import fuse_ctrl_prim_axi_read_out_pkg::*; + import fuse_ctrl_prim_axi_read_out_pkg_hdl::*; + import fuse_ctrl_secreg_axi_read_in_pkg::*; + import fuse_ctrl_secreg_axi_read_in_pkg_hdl::*; + import fuse_ctrl_secreg_axi_read_out_pkg::*; + import fuse_ctrl_secreg_axi_read_out_pkg_hdl::*; + import fuse_ctrl_lc_otp_in_pkg::*; + import fuse_ctrl_lc_otp_in_pkg_hdl::*; + import fuse_ctrl_lc_otp_out_pkg::*; + import fuse_ctrl_lc_otp_out_pkg_hdl::*; + import fuse_ctrl_in_pkg::*; + import fuse_ctrl_in_pkg_hdl::*; + import fuse_ctrl_out_pkg::*; + import fuse_ctrl_out_pkg_hdl::*; + import fuse_ctrl_parameters_pkg::*; + import fuse_ctrl_env_pkg::*; + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + `include "src/fuse_ctrl_bench_sequence_base.svh" + `include "src/register_test_sequence.svh" + `include "src/example_derived_test_sequence.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the sequence package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/sequences/fuse_ctrl_sequences_pkg.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/sequences/fuse_ctrl_sequences_pkg.vinfo new file mode 100644 index 0000000..150eb8c --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/sequences/fuse_ctrl_sequences_pkg.vinfo @@ -0,0 +1,21 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/environment_packages/fuse_ctrl_env_pkg/fuse_ctrl_env_pkg.vinfo +@use $UVMF_PROJECT_DIR/tb/parameters/fuse_ctrl_parameters_pkg.vinfo ++incdir+@vinfodir +fuse_ctrl_sequences_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/sequences/src/example_derived_test_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/sequences/src/example_derived_test_sequence.svh new file mode 100644 index 0000000..7566dc5 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/sequences/src/example_derived_test_sequence.svh @@ -0,0 +1,44 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains the top level sequence used in example_derived_test. +// It is an example of a sequence that is extended from %(benchName)_bench_sequence_base +// and can override %(benchName)_bench_sequence_base. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class example_derived_test_sequence extends fuse_ctrl_bench_sequence_base; + + `uvm_object_utils( example_derived_test_sequence ); + + function new(string name = "" ); + super.new(name); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/sequences/src/fuse_ctrl_bench_sequence_base.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/sequences/src/fuse_ctrl_bench_sequence_base.svh new file mode 100644 index 0000000..5b73892 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/sequences/src/fuse_ctrl_bench_sequence_base.svh @@ -0,0 +1,254 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// Description: This file contains the top level and utility sequences +// used by test_top. It can be extended to create derivative top +// level sequences. +// +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// + + +typedef fuse_ctrl_env_configuration fuse_ctrl_env_configuration_t; + +class fuse_ctrl_bench_sequence_base extends uvmf_sequence_base #(uvm_sequence_item); + + `uvm_object_utils( fuse_ctrl_bench_sequence_base ); + + // pragma uvmf custom sequences begin + +typedef fuse_ctrl_env_sequence_base #( + .CONFIG_T(fuse_ctrl_env_configuration_t) + ) + fuse_ctrl_env_sequence_base_t; +rand fuse_ctrl_env_sequence_base_t fuse_ctrl_env_seq; + + + + // UVMF_CHANGE_ME : Instantiate, construct, and start sequences as needed to create stimulus scenarios. + // Instantiate sequences here + typedef fuse_ctrl_rst_in_random_sequence fuse_ctrl_rst_in_agent_random_seq_t; + fuse_ctrl_rst_in_agent_random_seq_t fuse_ctrl_rst_in_agent_random_seq; + typedef fuse_ctrl_core_axi_write_in_random_sequence fuse_ctrl_core_axi_write_in_if_agent_random_seq_t; + fuse_ctrl_core_axi_write_in_if_agent_random_seq_t fuse_ctrl_core_axi_write_in_if_agent_random_seq; + typedef fuse_ctrl_prim_axi_write_in_random_sequence fuse_ctrl_prim_axi_write_in_if_agent_random_seq_t; + fuse_ctrl_prim_axi_write_in_if_agent_random_seq_t fuse_ctrl_prim_axi_write_in_if_agent_random_seq; + typedef fuse_ctrl_core_axi_read_in_random_sequence fuse_ctrl_core_axi_read_in_if_agent_random_seq_t; + fuse_ctrl_core_axi_read_in_if_agent_random_seq_t fuse_ctrl_core_axi_read_in_if_agent_random_seq; + typedef fuse_ctrl_prim_axi_read_in_random_sequence fuse_ctrl_prim_axi_read_in_if_agent_random_seq_t; + fuse_ctrl_prim_axi_read_in_if_agent_random_seq_t fuse_ctrl_prim_axi_read_in_if_agent_random_seq; + typedef fuse_ctrl_secreg_axi_read_in_random_sequence fuse_ctrl_secreg_axi_read_in_if_agent_random_seq_t; + fuse_ctrl_secreg_axi_read_in_if_agent_random_seq_t fuse_ctrl_secreg_axi_read_in_if_agent_random_seq; + typedef fuse_ctrl_lc_otp_in_random_sequence fuse_ctrl_lc_otp_in_if_agent_random_seq_t; + fuse_ctrl_lc_otp_in_if_agent_random_seq_t fuse_ctrl_lc_otp_in_if_agent_random_seq; + typedef fuse_ctrl_in_random_sequence fuse_ctrl_in_if_agent_random_seq_t; + fuse_ctrl_in_if_agent_random_seq_t fuse_ctrl_in_if_agent_random_seq; + // pragma uvmf custom sequences end + + // Sequencer handles for each active interface in the environment + typedef fuse_ctrl_rst_in_transaction fuse_ctrl_rst_in_agent_transaction_t; + uvm_sequencer #(fuse_ctrl_rst_in_agent_transaction_t) fuse_ctrl_rst_in_agent_sequencer; + typedef fuse_ctrl_core_axi_write_in_transaction fuse_ctrl_core_axi_write_in_if_agent_transaction_t; + uvm_sequencer #(fuse_ctrl_core_axi_write_in_if_agent_transaction_t) fuse_ctrl_core_axi_write_in_if_agent_sequencer; + typedef fuse_ctrl_prim_axi_write_in_transaction fuse_ctrl_prim_axi_write_in_if_agent_transaction_t; + uvm_sequencer #(fuse_ctrl_prim_axi_write_in_if_agent_transaction_t) fuse_ctrl_prim_axi_write_in_if_agent_sequencer; + typedef fuse_ctrl_core_axi_read_in_transaction fuse_ctrl_core_axi_read_in_if_agent_transaction_t; + uvm_sequencer #(fuse_ctrl_core_axi_read_in_if_agent_transaction_t) fuse_ctrl_core_axi_read_in_if_agent_sequencer; + typedef fuse_ctrl_prim_axi_read_in_transaction fuse_ctrl_prim_axi_read_in_if_agent_transaction_t; + uvm_sequencer #(fuse_ctrl_prim_axi_read_in_if_agent_transaction_t) fuse_ctrl_prim_axi_read_in_if_agent_sequencer; + typedef fuse_ctrl_secreg_axi_read_in_transaction fuse_ctrl_secreg_axi_read_in_if_agent_transaction_t; + uvm_sequencer #(fuse_ctrl_secreg_axi_read_in_if_agent_transaction_t) fuse_ctrl_secreg_axi_read_in_if_agent_sequencer; + typedef fuse_ctrl_lc_otp_in_transaction fuse_ctrl_lc_otp_in_if_agent_transaction_t; + uvm_sequencer #(fuse_ctrl_lc_otp_in_if_agent_transaction_t) fuse_ctrl_lc_otp_in_if_agent_sequencer; + typedef fuse_ctrl_in_transaction fuse_ctrl_in_if_agent_transaction_t; + uvm_sequencer #(fuse_ctrl_in_if_agent_transaction_t) fuse_ctrl_in_if_agent_sequencer; + + + // Top level environment configuration handle + fuse_ctrl_env_configuration_t top_configuration; + + // Configuration handles to access interface BFM's + fuse_ctrl_rst_in_configuration fuse_ctrl_rst_in_agent_config; + fuse_ctrl_rst_out_configuration fuse_ctrl_rst_out_agent_config; + fuse_ctrl_core_axi_write_in_configuration fuse_ctrl_core_axi_write_in_if_agent_config; + fuse_ctrl_core_axi_write_out_configuration fuse_ctrl_core_axi_write_out_if_agent_config; + fuse_ctrl_prim_axi_write_in_configuration fuse_ctrl_prim_axi_write_in_if_agent_config; + fuse_ctrl_prim_axi_write_out_configuration fuse_ctrl_prim_axi_write_out_if_agent_config; + fuse_ctrl_core_axi_read_in_configuration fuse_ctrl_core_axi_read_in_if_agent_config; + fuse_ctrl_core_axi_read_out_configuration fuse_ctrl_core_axi_read_out_if_agent_config; + fuse_ctrl_prim_axi_read_in_configuration fuse_ctrl_prim_axi_read_in_if_agent_config; + fuse_ctrl_prim_axi_read_out_configuration fuse_ctrl_prim_axi_read_out_if_agent_config; + fuse_ctrl_secreg_axi_read_in_configuration fuse_ctrl_secreg_axi_read_in_if_agent_config; + fuse_ctrl_secreg_axi_read_out_configuration fuse_ctrl_secreg_axi_read_out_if_agent_config; + fuse_ctrl_lc_otp_in_configuration fuse_ctrl_lc_otp_in_if_agent_config; + fuse_ctrl_lc_otp_out_configuration fuse_ctrl_lc_otp_out_if_agent_config; + fuse_ctrl_in_configuration fuse_ctrl_in_if_agent_config; + fuse_ctrl_out_configuration fuse_ctrl_out_if_agent_config; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + function new( string name = "" ); + super.new( name ); + // Retrieve the configuration handles from the uvm_config_db + + // Retrieve top level configuration handle + if ( !uvm_config_db#(fuse_ctrl_env_configuration_t)::get(null,UVMF_CONFIGURATIONS, "TOP_ENV_CONFIG",top_configuration) ) begin + `uvm_info("CFG", "*** FATAL *** uvm_config_db::get can not find TOP_ENV_CONFIG. Are you using an older UVMF release than what was used to generate this bench?",UVM_NONE); + `uvm_fatal("CFG", "uvm_config_db#(fuse_ctrl_env_configuration_t)::get cannot find resource TOP_ENV_CONFIG"); + end + + // Retrieve config handles for all agents + if( !uvm_config_db #( fuse_ctrl_rst_in_configuration )::get( null , UVMF_CONFIGURATIONS , fuse_ctrl_rst_in_agent_BFM , fuse_ctrl_rst_in_agent_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( fuse_ctrl_rst_in_configuration )::get cannot find resource fuse_ctrl_rst_in_agent_BFM" ) + if( !uvm_config_db #( fuse_ctrl_rst_out_configuration )::get( null , UVMF_CONFIGURATIONS , fuse_ctrl_rst_out_agent_BFM , fuse_ctrl_rst_out_agent_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( fuse_ctrl_rst_out_configuration )::get cannot find resource fuse_ctrl_rst_out_agent_BFM" ) + if( !uvm_config_db #( fuse_ctrl_core_axi_write_in_configuration )::get( null , UVMF_CONFIGURATIONS , fuse_ctrl_core_axi_write_in_if_agent_BFM , fuse_ctrl_core_axi_write_in_if_agent_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( fuse_ctrl_core_axi_write_in_configuration )::get cannot find resource fuse_ctrl_core_axi_write_in_if_agent_BFM" ) + if( !uvm_config_db #( fuse_ctrl_core_axi_write_out_configuration )::get( null , UVMF_CONFIGURATIONS , fuse_ctrl_core_axi_write_out_if_agent_BFM , fuse_ctrl_core_axi_write_out_if_agent_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( fuse_ctrl_core_axi_write_out_configuration )::get cannot find resource fuse_ctrl_core_axi_write_out_if_agent_BFM" ) + if( !uvm_config_db #( fuse_ctrl_prim_axi_write_in_configuration )::get( null , UVMF_CONFIGURATIONS , fuse_ctrl_prim_axi_write_in_if_agent_BFM , fuse_ctrl_prim_axi_write_in_if_agent_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( fuse_ctrl_prim_axi_write_in_configuration )::get cannot find resource fuse_ctrl_prim_axi_write_in_if_agent_BFM" ) + if( !uvm_config_db #( fuse_ctrl_prim_axi_write_out_configuration )::get( null , UVMF_CONFIGURATIONS , fuse_ctrl_prim_axi_write_out_if_agent_BFM , fuse_ctrl_prim_axi_write_out_if_agent_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( fuse_ctrl_prim_axi_write_out_configuration )::get cannot find resource fuse_ctrl_prim_axi_write_out_if_agent_BFM" ) + if( !uvm_config_db #( fuse_ctrl_core_axi_read_in_configuration )::get( null , UVMF_CONFIGURATIONS , fuse_ctrl_core_axi_read_in_if_agent_BFM , fuse_ctrl_core_axi_read_in_if_agent_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( fuse_ctrl_core_axi_read_in_configuration )::get cannot find resource fuse_ctrl_core_axi_read_in_if_agent_BFM" ) + if( !uvm_config_db #( fuse_ctrl_core_axi_read_out_configuration )::get( null , UVMF_CONFIGURATIONS , fuse_ctrl_core_axi_read_out_if_agent_BFM , fuse_ctrl_core_axi_read_out_if_agent_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( fuse_ctrl_core_axi_read_out_configuration )::get cannot find resource fuse_ctrl_core_axi_read_out_if_agent_BFM" ) + if( !uvm_config_db #( fuse_ctrl_prim_axi_read_in_configuration )::get( null , UVMF_CONFIGURATIONS , fuse_ctrl_prim_axi_read_in_if_agent_BFM , fuse_ctrl_prim_axi_read_in_if_agent_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( fuse_ctrl_prim_axi_read_in_configuration )::get cannot find resource fuse_ctrl_prim_axi_read_in_if_agent_BFM" ) + if( !uvm_config_db #( fuse_ctrl_prim_axi_read_out_configuration )::get( null , UVMF_CONFIGURATIONS , fuse_ctrl_prim_axi_read_out_if_agent_BFM , fuse_ctrl_prim_axi_read_out_if_agent_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( fuse_ctrl_prim_axi_read_out_configuration )::get cannot find resource fuse_ctrl_prim_axi_read_out_if_agent_BFM" ) + if( !uvm_config_db #( fuse_ctrl_secreg_axi_read_in_configuration )::get( null , UVMF_CONFIGURATIONS , fuse_ctrl_secreg_axi_read_in_if_agent_BFM , fuse_ctrl_secreg_axi_read_in_if_agent_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( fuse_ctrl_secreg_axi_read_in_configuration )::get cannot find resource fuse_ctrl_secreg_axi_read_in_if_agent_BFM" ) + if( !uvm_config_db #( fuse_ctrl_secreg_axi_read_out_configuration )::get( null , UVMF_CONFIGURATIONS , fuse_ctrl_secreg_axi_read_out_if_agent_BFM , fuse_ctrl_secreg_axi_read_out_if_agent_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( fuse_ctrl_secreg_axi_read_out_configuration )::get cannot find resource fuse_ctrl_secreg_axi_read_out_if_agent_BFM" ) + if( !uvm_config_db #( fuse_ctrl_lc_otp_in_configuration )::get( null , UVMF_CONFIGURATIONS , fuse_ctrl_lc_otp_in_if_agent_BFM , fuse_ctrl_lc_otp_in_if_agent_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( fuse_ctrl_lc_otp_in_configuration )::get cannot find resource fuse_ctrl_lc_otp_in_if_agent_BFM" ) + if( !uvm_config_db #( fuse_ctrl_lc_otp_out_configuration )::get( null , UVMF_CONFIGURATIONS , fuse_ctrl_lc_otp_out_if_agent_BFM , fuse_ctrl_lc_otp_out_if_agent_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( fuse_ctrl_lc_otp_out_configuration )::get cannot find resource fuse_ctrl_lc_otp_out_if_agent_BFM" ) + if( !uvm_config_db #( fuse_ctrl_in_configuration )::get( null , UVMF_CONFIGURATIONS , fuse_ctrl_in_if_agent_BFM , fuse_ctrl_in_if_agent_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( fuse_ctrl_in_configuration )::get cannot find resource fuse_ctrl_in_if_agent_BFM" ) + if( !uvm_config_db #( fuse_ctrl_out_configuration )::get( null , UVMF_CONFIGURATIONS , fuse_ctrl_out_if_agent_BFM , fuse_ctrl_out_if_agent_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( fuse_ctrl_out_configuration )::get cannot find resource fuse_ctrl_out_if_agent_BFM" ) + + // Assign the sequencer handles from the handles within agent configurations + fuse_ctrl_rst_in_agent_sequencer = fuse_ctrl_rst_in_agent_config.get_sequencer(); + fuse_ctrl_core_axi_write_in_if_agent_sequencer = fuse_ctrl_core_axi_write_in_if_agent_config.get_sequencer(); + fuse_ctrl_prim_axi_write_in_if_agent_sequencer = fuse_ctrl_prim_axi_write_in_if_agent_config.get_sequencer(); + fuse_ctrl_core_axi_read_in_if_agent_sequencer = fuse_ctrl_core_axi_read_in_if_agent_config.get_sequencer(); + fuse_ctrl_prim_axi_read_in_if_agent_sequencer = fuse_ctrl_prim_axi_read_in_if_agent_config.get_sequencer(); + fuse_ctrl_secreg_axi_read_in_if_agent_sequencer = fuse_ctrl_secreg_axi_read_in_if_agent_config.get_sequencer(); + fuse_ctrl_lc_otp_in_if_agent_sequencer = fuse_ctrl_lc_otp_in_if_agent_config.get_sequencer(); + fuse_ctrl_in_if_agent_sequencer = fuse_ctrl_in_if_agent_config.get_sequencer(); + + + + // pragma uvmf custom new begin + // pragma uvmf custom new end + + endfunction + + // **************************************************************************** + virtual task body(); + // pragma uvmf custom body begin + + // Construct sequences here + + fuse_ctrl_env_seq = fuse_ctrl_env_sequence_base_t::type_id::create("fuse_ctrl_env_seq"); + + fuse_ctrl_rst_in_agent_random_seq = fuse_ctrl_rst_in_agent_random_seq_t::type_id::create("fuse_ctrl_rst_in_agent_random_seq"); + fuse_ctrl_core_axi_write_in_if_agent_random_seq = fuse_ctrl_core_axi_write_in_if_agent_random_seq_t::type_id::create("fuse_ctrl_core_axi_write_in_if_agent_random_seq"); + fuse_ctrl_prim_axi_write_in_if_agent_random_seq = fuse_ctrl_prim_axi_write_in_if_agent_random_seq_t::type_id::create("fuse_ctrl_prim_axi_write_in_if_agent_random_seq"); + fuse_ctrl_core_axi_read_in_if_agent_random_seq = fuse_ctrl_core_axi_read_in_if_agent_random_seq_t::type_id::create("fuse_ctrl_core_axi_read_in_if_agent_random_seq"); + fuse_ctrl_prim_axi_read_in_if_agent_random_seq = fuse_ctrl_prim_axi_read_in_if_agent_random_seq_t::type_id::create("fuse_ctrl_prim_axi_read_in_if_agent_random_seq"); + fuse_ctrl_secreg_axi_read_in_if_agent_random_seq = fuse_ctrl_secreg_axi_read_in_if_agent_random_seq_t::type_id::create("fuse_ctrl_secreg_axi_read_in_if_agent_random_seq"); + fuse_ctrl_lc_otp_in_if_agent_random_seq = fuse_ctrl_lc_otp_in_if_agent_random_seq_t::type_id::create("fuse_ctrl_lc_otp_in_if_agent_random_seq"); + fuse_ctrl_in_if_agent_random_seq = fuse_ctrl_in_if_agent_random_seq_t::type_id::create("fuse_ctrl_in_if_agent_random_seq"); + fork + fuse_ctrl_rst_in_agent_config.wait_for_reset(); + fuse_ctrl_rst_out_agent_config.wait_for_reset(); + fuse_ctrl_core_axi_write_in_if_agent_config.wait_for_reset(); + fuse_ctrl_core_axi_write_out_if_agent_config.wait_for_reset(); + fuse_ctrl_prim_axi_write_in_if_agent_config.wait_for_reset(); + fuse_ctrl_prim_axi_write_out_if_agent_config.wait_for_reset(); + fuse_ctrl_core_axi_read_in_if_agent_config.wait_for_reset(); + fuse_ctrl_core_axi_read_out_if_agent_config.wait_for_reset(); + fuse_ctrl_prim_axi_read_in_if_agent_config.wait_for_reset(); + fuse_ctrl_prim_axi_read_out_if_agent_config.wait_for_reset(); + fuse_ctrl_secreg_axi_read_in_if_agent_config.wait_for_reset(); + fuse_ctrl_secreg_axi_read_out_if_agent_config.wait_for_reset(); + fuse_ctrl_lc_otp_in_if_agent_config.wait_for_reset(); + fuse_ctrl_lc_otp_out_if_agent_config.wait_for_reset(); + fuse_ctrl_in_if_agent_config.wait_for_reset(); + fuse_ctrl_out_if_agent_config.wait_for_reset(); + join + // Start RESPONDER sequences here + fork + join_none + // Start INITIATOR sequences here + fork + repeat (25) fuse_ctrl_rst_in_agent_random_seq.start(fuse_ctrl_rst_in_agent_sequencer); + repeat (25) fuse_ctrl_core_axi_write_in_if_agent_random_seq.start(fuse_ctrl_core_axi_write_in_if_agent_sequencer); + repeat (25) fuse_ctrl_prim_axi_write_in_if_agent_random_seq.start(fuse_ctrl_prim_axi_write_in_if_agent_sequencer); + repeat (25) fuse_ctrl_core_axi_read_in_if_agent_random_seq.start(fuse_ctrl_core_axi_read_in_if_agent_sequencer); + repeat (25) fuse_ctrl_prim_axi_read_in_if_agent_random_seq.start(fuse_ctrl_prim_axi_read_in_if_agent_sequencer); + repeat (25) fuse_ctrl_secreg_axi_read_in_if_agent_random_seq.start(fuse_ctrl_secreg_axi_read_in_if_agent_sequencer); + repeat (25) fuse_ctrl_lc_otp_in_if_agent_random_seq.start(fuse_ctrl_lc_otp_in_if_agent_sequencer); + repeat (25) fuse_ctrl_in_if_agent_random_seq.start(fuse_ctrl_in_if_agent_sequencer); + join + +fuse_ctrl_env_seq.start(top_configuration.vsqr); + + // UVMF_CHANGE_ME : Extend the simulation XXX number of clocks after + // the last sequence to allow for the last sequence item to flow + // through the design. + fork + fuse_ctrl_rst_in_agent_config.wait_for_num_clocks(400); + fuse_ctrl_rst_out_agent_config.wait_for_num_clocks(400); + fuse_ctrl_core_axi_write_in_if_agent_config.wait_for_num_clocks(400); + fuse_ctrl_core_axi_write_out_if_agent_config.wait_for_num_clocks(400); + fuse_ctrl_prim_axi_write_in_if_agent_config.wait_for_num_clocks(400); + fuse_ctrl_prim_axi_write_out_if_agent_config.wait_for_num_clocks(400); + fuse_ctrl_core_axi_read_in_if_agent_config.wait_for_num_clocks(400); + fuse_ctrl_core_axi_read_out_if_agent_config.wait_for_num_clocks(400); + fuse_ctrl_prim_axi_read_in_if_agent_config.wait_for_num_clocks(400); + fuse_ctrl_prim_axi_read_out_if_agent_config.wait_for_num_clocks(400); + fuse_ctrl_secreg_axi_read_in_if_agent_config.wait_for_num_clocks(400); + fuse_ctrl_secreg_axi_read_out_if_agent_config.wait_for_num_clocks(400); + fuse_ctrl_lc_otp_in_if_agent_config.wait_for_num_clocks(400); + fuse_ctrl_lc_otp_out_if_agent_config.wait_for_num_clocks(400); + fuse_ctrl_in_if_agent_config.wait_for_num_clocks(400); + fuse_ctrl_out_if_agent_config.wait_for_num_clocks(400); + join + + // pragma uvmf custom body end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/sequences/src/register_test_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/sequences/src/register_test_sequence.svh new file mode 100644 index 0000000..d863142 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/sequences/src/register_test_sequence.svh @@ -0,0 +1,85 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains the top level sequence used in register_test. +// It uses the UVM built in register test. Specific UVM built-in tests can be +// selected in the body task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class register_test_sequence extends fuse_ctrl_bench_sequence_base; + + `uvm_object_utils( register_test_sequence ); + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "" ); + super.new(name); + endfunction + + // **************************************************************************** + virtual task body(); + + // Reset the DUT + fork + // pragma uvmf custom register_test_reset begin + // UVMF_CHANGE_ME + // Select the desired wait_for_reset or provide custom mechanism. + // fork-join for this code block may be unnecessary based on your situation. + fuse_ctrl_rst_in_agent_config.wait_for_reset(); + fuse_ctrl_rst_out_agent_config.wait_for_reset(); + fuse_ctrl_core_axi_write_in_if_agent_config.wait_for_reset(); + fuse_ctrl_core_axi_write_out_if_agent_config.wait_for_reset(); + fuse_ctrl_prim_axi_write_in_if_agent_config.wait_for_reset(); + fuse_ctrl_prim_axi_write_out_if_agent_config.wait_for_reset(); + fuse_ctrl_core_axi_read_in_if_agent_config.wait_for_reset(); + fuse_ctrl_core_axi_read_out_if_agent_config.wait_for_reset(); + fuse_ctrl_prim_axi_read_in_if_agent_config.wait_for_reset(); + fuse_ctrl_prim_axi_read_out_if_agent_config.wait_for_reset(); + fuse_ctrl_secreg_axi_read_in_if_agent_config.wait_for_reset(); + fuse_ctrl_secreg_axi_read_out_if_agent_config.wait_for_reset(); + fuse_ctrl_lc_otp_in_if_agent_config.wait_for_reset(); + fuse_ctrl_lc_otp_out_if_agent_config.wait_for_reset(); + fuse_ctrl_in_if_agent_config.wait_for_reset(); + fuse_ctrl_out_if_agent_config.wait_for_reset(); + // pragma uvmf custom register_test_reset end + join + + // pragma uvmf custom register_test_setup begin + // UVMF_CHANGE_ME perform potentially necessary operations before running the sequence. + // pragma uvmf custom register_test_setup end + + // pragma uvmf custom register_test_operation begin + // UVMF_CHANGE_ME Perform your custom register test + // pragma uvmf custom register_test_operation end + + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/testbench/hdl_top.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/testbench/hdl_top.compile new file mode 100644 index 0000000..651edf5 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/testbench/hdl_top.compile @@ -0,0 +1,24 @@ +incdir: + - ${uvm_path}/src + - . +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ../parameters/fuse_ctrl_parameters_pkg.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_hdl.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_hdl.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_hdl.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_hdl.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_hdl.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_hdl.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_hdl.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_hdl.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_hdl.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_hdl.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_hdl.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_hdl.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_hdl.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_hdl.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_hdl.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_hdl.compile +src: + - hdl_top.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/testbench/hdl_top.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/testbench/hdl_top.sv new file mode 100644 index 0000000..134ef5d --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/testbench/hdl_top.sv @@ -0,0 +1,412 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// Description: This top level module instantiates all synthesizable +// static content. This and tb_top.sv are the two top level modules +// of the simulation. +// +// This module instantiates the following: +// DUT: The Design Under Test +// Interfaces: Signal bundles that contain signals connected to DUT +// Driver BFM's: BFM's that actively drive interface signals +// Monitor BFM's: BFM's that passively monitor interface signals +// +//---------------------------------------------------------------------- + +//---------------------------------------------------------------------- +// + +module hdl_top; + +import fuse_ctrl_parameters_pkg::*; +import uvmf_base_pkg_hdl::*; +import axi_pkg::*; + + // pragma attribute hdl_top partition_module_xrtl +// pragma uvmf custom clock_generator begin + bit clk; + // Instantiate a clk driver + // tbx clkgen + initial begin + clk = 0; + #0ns; + forever begin + clk = ~clk; + #5ns; + end + end +// pragma uvmf custom clock_generator end + +// pragma uvmf custom reset_generator begin + bit rst; + // Instantiate a rst driver + // tbx clkgen + initial begin + rst = 0; + #200ns; + rst = 1; + end +// pragma uvmf custom reset_generator end + + // pragma uvmf custom module_item_additional begin + logic edn_clk; + logic edn_rst_n; + + localparam MemInitFile = "/home/ws/caliptra/anjpar/ws1/chipsalliance/caliptra-rtl/src/fuse_ctrl/data/otp-img.2048.vmem"; + // pragma uvmf custom module_item_additional end + + // Instantiate the signal bundle, monitor bfm and driver bfm for each interface. + // The signal bundle, _if, contains signals to be connected to the DUT. + // The monitor, monitor_bfm, observes the bus, _if, and captures transactions. + // The driver, driver_bfm, drives transactions onto the bus, _if. + fuse_ctrl_rst_in_if fuse_ctrl_rst_in_agent_bus( + // pragma uvmf custom fuse_ctrl_rst_in_agent_bus_connections begin + .clk_i(clk), .rst_ni(rst) + // pragma uvmf custom fuse_ctrl_rst_in_agent_bus_connections end + ); + fuse_ctrl_rst_out_if fuse_ctrl_rst_out_agent_bus( + // pragma uvmf custom fuse_ctrl_rst_out_agent_bus_connections begin + .clk_i(clk), .rst_ni(rst) + // pragma uvmf custom fuse_ctrl_rst_out_agent_bus_connections end + ); + fuse_ctrl_core_axi_write_in_if fuse_ctrl_core_axi_write_in_if_agent_bus( + // pragma uvmf custom fuse_ctrl_core_axi_write_in_if_agent_bus_connections begin + .clk_i(clk), .rst_ni(rst) + // pragma uvmf custom fuse_ctrl_core_axi_write_in_if_agent_bus_connections end + ); + fuse_ctrl_core_axi_write_out_if fuse_ctrl_core_axi_write_out_if_agent_bus( + // pragma uvmf custom fuse_ctrl_core_axi_write_out_if_agent_bus_connections begin + .clk_i(clk), .rst_ni(rst) + // pragma uvmf custom fuse_ctrl_core_axi_write_out_if_agent_bus_connections end + ); + fuse_ctrl_prim_axi_write_in_if fuse_ctrl_prim_axi_write_in_if_agent_bus( + // pragma uvmf custom fuse_ctrl_prim_axi_write_in_if_agent_bus_connections begin + .clk_i(clk), .rst_ni(rst) + // pragma uvmf custom fuse_ctrl_prim_axi_write_in_if_agent_bus_connections end + ); + fuse_ctrl_prim_axi_write_out_if fuse_ctrl_prim_axi_write_out_if_agent_bus( + // pragma uvmf custom fuse_ctrl_prim_axi_write_out_if_agent_bus_connections begin + .clk_i(clk), .rst_ni(rst) + // pragma uvmf custom fuse_ctrl_prim_axi_write_out_if_agent_bus_connections end + ); + fuse_ctrl_core_axi_read_in_if fuse_ctrl_core_axi_read_in_if_agent_bus( + // pragma uvmf custom fuse_ctrl_core_axi_read_in_if_agent_bus_connections begin + .clk_i(clk), .rst_ni(rst) + // pragma uvmf custom fuse_ctrl_core_axi_read_in_if_agent_bus_connections end + ); + fuse_ctrl_core_axi_read_out_if fuse_ctrl_core_axi_read_out_if_agent_bus( + // pragma uvmf custom fuse_ctrl_core_axi_read_out_if_agent_bus_connections begin + .clk_i(clk), .rst_ni(rst) + // pragma uvmf custom fuse_ctrl_core_axi_read_out_if_agent_bus_connections end + ); + fuse_ctrl_prim_axi_read_in_if fuse_ctrl_prim_axi_read_in_if_agent_bus( + // pragma uvmf custom fuse_ctrl_prim_axi_read_in_if_agent_bus_connections begin + .clk_i(clk), .rst_ni(rst) + // pragma uvmf custom fuse_ctrl_prim_axi_read_in_if_agent_bus_connections end + ); + fuse_ctrl_prim_axi_read_out_if fuse_ctrl_prim_axi_read_out_if_agent_bus( + // pragma uvmf custom fuse_ctrl_prim_axi_read_out_if_agent_bus_connections begin + .clk_i(clk), .rst_ni(rst) + // pragma uvmf custom fuse_ctrl_prim_axi_read_out_if_agent_bus_connections end + ); + fuse_ctrl_secreg_axi_read_in_if fuse_ctrl_secreg_axi_read_in_if_agent_bus( + // pragma uvmf custom fuse_ctrl_secreg_axi_read_in_if_agent_bus_connections begin + .clk_i(clk), .rst_ni(rst) + // pragma uvmf custom fuse_ctrl_secreg_axi_read_in_if_agent_bus_connections end + ); + fuse_ctrl_secreg_axi_read_out_if fuse_ctrl_secreg_axi_read_out_if_agent_bus( + // pragma uvmf custom fuse_ctrl_secreg_axi_read_out_if_agent_bus_connections begin + .clk_i(clk), .rst_ni(rst) + // pragma uvmf custom fuse_ctrl_secreg_axi_read_out_if_agent_bus_connections end + ); + fuse_ctrl_lc_otp_in_if fuse_ctrl_lc_otp_in_if_agent_bus( + // pragma uvmf custom fuse_ctrl_lc_otp_in_if_agent_bus_connections begin + .clk_i(clk), .rst_ni(rst) + // pragma uvmf custom fuse_ctrl_lc_otp_in_if_agent_bus_connections end + ); + fuse_ctrl_lc_otp_out_if fuse_ctrl_lc_otp_out_if_agent_bus( + // pragma uvmf custom fuse_ctrl_lc_otp_out_if_agent_bus_connections begin + .clk_i(clk), .rst_ni(rst) + // pragma uvmf custom fuse_ctrl_lc_otp_out_if_agent_bus_connections end + ); + fuse_ctrl_in_if fuse_ctrl_in_if_agent_bus( + // pragma uvmf custom fuse_ctrl_in_if_agent_bus_connections begin + .clk_i(clk), .rst_ni(rst) + // pragma uvmf custom fuse_ctrl_in_if_agent_bus_connections end + ); + fuse_ctrl_out_if fuse_ctrl_out_if_agent_bus( + // pragma uvmf custom fuse_ctrl_out_if_agent_bus_connections begin + .clk_i(clk), .rst_ni(rst) + // pragma uvmf custom fuse_ctrl_out_if_agent_bus_connections end + ); + fuse_ctrl_rst_in_monitor_bfm fuse_ctrl_rst_in_agent_mon_bfm(fuse_ctrl_rst_in_agent_bus.monitor_port); + fuse_ctrl_rst_out_monitor_bfm fuse_ctrl_rst_out_agent_mon_bfm(fuse_ctrl_rst_out_agent_bus.monitor_port); + fuse_ctrl_core_axi_write_in_monitor_bfm fuse_ctrl_core_axi_write_in_if_agent_mon_bfm(fuse_ctrl_core_axi_write_in_if_agent_bus.monitor_port); + fuse_ctrl_core_axi_write_out_monitor_bfm fuse_ctrl_core_axi_write_out_if_agent_mon_bfm(fuse_ctrl_core_axi_write_out_if_agent_bus.monitor_port); + fuse_ctrl_prim_axi_write_in_monitor_bfm fuse_ctrl_prim_axi_write_in_if_agent_mon_bfm(fuse_ctrl_prim_axi_write_in_if_agent_bus.monitor_port); + fuse_ctrl_prim_axi_write_out_monitor_bfm fuse_ctrl_prim_axi_write_out_if_agent_mon_bfm(fuse_ctrl_prim_axi_write_out_if_agent_bus.monitor_port); + fuse_ctrl_core_axi_read_in_monitor_bfm fuse_ctrl_core_axi_read_in_if_agent_mon_bfm(fuse_ctrl_core_axi_read_in_if_agent_bus.monitor_port); + fuse_ctrl_core_axi_read_out_monitor_bfm fuse_ctrl_core_axi_read_out_if_agent_mon_bfm(fuse_ctrl_core_axi_read_out_if_agent_bus.monitor_port); + fuse_ctrl_prim_axi_read_in_monitor_bfm fuse_ctrl_prim_axi_read_in_if_agent_mon_bfm(fuse_ctrl_prim_axi_read_in_if_agent_bus.monitor_port); + fuse_ctrl_prim_axi_read_out_monitor_bfm fuse_ctrl_prim_axi_read_out_if_agent_mon_bfm(fuse_ctrl_prim_axi_read_out_if_agent_bus.monitor_port); + fuse_ctrl_secreg_axi_read_in_monitor_bfm fuse_ctrl_secreg_axi_read_in_if_agent_mon_bfm(fuse_ctrl_secreg_axi_read_in_if_agent_bus.monitor_port); + fuse_ctrl_secreg_axi_read_out_monitor_bfm fuse_ctrl_secreg_axi_read_out_if_agent_mon_bfm(fuse_ctrl_secreg_axi_read_out_if_agent_bus.monitor_port); + fuse_ctrl_lc_otp_in_monitor_bfm fuse_ctrl_lc_otp_in_if_agent_mon_bfm(fuse_ctrl_lc_otp_in_if_agent_bus.monitor_port); + fuse_ctrl_lc_otp_out_monitor_bfm fuse_ctrl_lc_otp_out_if_agent_mon_bfm(fuse_ctrl_lc_otp_out_if_agent_bus.monitor_port); + fuse_ctrl_in_monitor_bfm fuse_ctrl_in_if_agent_mon_bfm(fuse_ctrl_in_if_agent_bus.monitor_port); + fuse_ctrl_out_monitor_bfm fuse_ctrl_out_if_agent_mon_bfm(fuse_ctrl_out_if_agent_bus.monitor_port); + fuse_ctrl_rst_in_driver_bfm fuse_ctrl_rst_in_agent_drv_bfm(fuse_ctrl_rst_in_agent_bus.initiator_port); + fuse_ctrl_core_axi_write_in_driver_bfm fuse_ctrl_core_axi_write_in_if_agent_drv_bfm(fuse_ctrl_core_axi_write_in_if_agent_bus.initiator_port); + fuse_ctrl_prim_axi_write_in_driver_bfm fuse_ctrl_prim_axi_write_in_if_agent_drv_bfm(fuse_ctrl_prim_axi_write_in_if_agent_bus.initiator_port); + fuse_ctrl_core_axi_read_in_driver_bfm fuse_ctrl_core_axi_read_in_if_agent_drv_bfm(fuse_ctrl_core_axi_read_in_if_agent_bus.initiator_port); + fuse_ctrl_prim_axi_read_in_driver_bfm fuse_ctrl_prim_axi_read_in_if_agent_drv_bfm(fuse_ctrl_prim_axi_read_in_if_agent_bus.initiator_port); + fuse_ctrl_secreg_axi_read_in_driver_bfm fuse_ctrl_secreg_axi_read_in_if_agent_drv_bfm(fuse_ctrl_secreg_axi_read_in_if_agent_bus.initiator_port); + fuse_ctrl_lc_otp_in_driver_bfm fuse_ctrl_lc_otp_in_if_agent_drv_bfm(fuse_ctrl_lc_otp_in_if_agent_bus.initiator_port); + fuse_ctrl_in_driver_bfm fuse_ctrl_in_if_agent_drv_bfm(fuse_ctrl_in_if_agent_bus.initiator_port); + + // pragma uvmf custom dut_instantiation begin + // UVMF_CHANGE_ME : Add DUT and connect to signals in _bus interfaces listed above + // Instantiate your DUT here + // These DUT's instantiated to show verilog and vhdl instantiation + //verilog_dut dut_verilog( .clk(clk), .rst(rst), .in_signal(vhdl_to_verilog_signal), .out_signal(verilog_to_vhdl_signal)); + //vhdl_dut dut_vhdl ( .clk(clk), .rst(rst), .in_signal(verilog_to_vhdl_signal), .out_signal(vhdl_to_verilog_signal)); + + otp_ctrl_top #( + .MemInitFile (MemInitFile) + ) dut ( + .clk_i (fuse_ctrl_rst_in_agent_bus.clk_i ), + .rst_ni (fuse_ctrl_rst_in_agent_bus.rst_ni ), + // edn + .clk_edn_i (edn_clk ), + .rst_edn_ni (edn_rst_n ), + .edn_o (fuse_ctrl_out_if_agent_bus.edn_o), //(edn_if[0].req ), + .edn_i (fuse_ctrl_in_if_agent_bus.edn_i), //({edn_if[0].ack, edn_if[0].d_data}), + // AXI interface + .s_core_axi_r_if (axi_core_if.r_sub), + .s_core_axi_w_if (axi_core_if.w_sub), + .s_prim_axi_r_if (axi_prim_if.r_sub), + .s_prim_axi_w_if (axi_prim_if.w_sub), + .s_secreg_axi_r_if (axi_secreg_if.r_sub), + // interrupt + .intr_otp_operation_done_o (fuse_ctrl_out_if_agent_bus.intr_otp_operation_done_o), + .intr_otp_error_o (fuse_ctrl_out_if_agent_bus.intr_otp_error_o), + // alert + .alert_rx_i (fuse_ctrl_in_if_agent_bus.alert_rx_i ), //(alert_rx parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_ALERT_TEST_OFFSET = 13'h c; + .alert_tx_o (fuse_ctrl_out_if_agent_bus.alert_tx_o ), //(alert_tx ), + // ast + .obs_ctrl_i (fuse_ctrl_in_if_agent_bus.obs_ctrl_i), //(otp_ctrl_if.obs_ctrl_i), + .otp_obs_o (fuse_ctrl_out_if_agent_bus.otp_obs_o), + .otp_ast_pwr_seq_o (fuse_ctrl_out_if_agent_bus.otp_ast_pwr_seq_o), //(ast_req), + .otp_ast_pwr_seq_h_i (fuse_ctrl_in_if_agent_bus.otp_ast_pwr_seq_h_i), //(otp_ctrl_if.otp_ast_pwr_seq_h_i), + // pwrmgr + .pwr_otp_i (fuse_ctrl_rst_in_agent_bus.pwr_otp_i), //(otp_ctrl_if.pwr_otp_init_i), + .pwr_otp_o (fuse_ctrl_rst_out_agent_bus.pwr_otp_o), //({otp_ctrl_if.pwr_otp_done_o, otp_ctrl_if.pwr_otp_idle_o}), + // lc + .lc_otp_vendor_test_i (fuse_ctrl_lc_otp_in_if_agent_bus.lc_otp_vendor_test_i), //(otp_ctrl_if.otp_vendor_test_ctrl_i), + .lc_otp_vendor_test_o (fuse_ctrl_lc_otp_out_if_agent_bus.lc_otp_vendor_test_o), //(otp_ctrl_if.otp_vendor_test_status_o), + .lc_otp_program_i (fuse_ctrl_lc_otp_in_if_agent_bus.lc_otp_program_i), //({lc_prog_if.req, lc_prog_if.h_data}), + .lc_otp_program_o (fuse_ctrl_lc_otp_out_if_agent_bus.lc_otp_program_o), //({lc_prog_if.d_data, lc_prog_if.ack}), + //.lc_creator_seed_sw_rw_en_i (lc_creator_seed_sw_rw_en_i), //(otp_ctrl_if.lc_creator_seed_sw_rw_en_i), + //.lc_owner_seed_sw_rw_en_i (lc_owner_seed_sw_rw_en_i), //(otp_ctrl_if.lc_owner_seed_sw_rw_en_i), + //.lc_seed_hw_rd_en_i (lc_seed_hw_rd_en_i), //(otp_ctrl_if.lc_seed_hw_rd_en_i), + .lc_dft_en_i (fuse_ctrl_lc_otp_in_if_agent_bus.lc_dft_en_i), //(otp_ctrl_if.lc_dft_en_i), + .lc_escalate_en_i (fuse_ctrl_lc_otp_in_if_agent_bus.lc_escalate_en_i), //(otp_ctrl_if.lc_escalate_en_i), + .lc_check_byp_en_i (fuse_ctrl_lc_otp_in_if_agent_bus.lc_check_byp_en_i), //(otp_ctrl_if.lc_check_byp_en_i), + .otp_lc_data_o (fuse_ctrl_lc_otp_out_if_agent_bus.otp_lc_data_o), //(otp_ctrl_if.lc_data_o), + + + .otp_broadcast_o (fuse_ctrl_out_if_agent_bus.otp_broadcast_o), //(otp_ctrl_if.otp_broadcast_o), + .otp_ext_voltage_h_io (fuse_ctrl_rst_in_agent_bus.otp_ext_voltage_h_io), + //scan + .scan_en_i (fuse_ctrl_in_if_agent_bus.scan_en_i), //(otp_ctrl_if.scan_en_i), + .scan_rst_ni (fuse_ctrl_in_if_agent_bus.scan_rst_ni), //(otp_ctrl_if.scan_rst_ni), + .scanmode_i (fuse_ctrl_in_if_agent_bus.scanmode_i), //(otp_ctrl_if.scanmode_i), + + // Test-related GPIO output + .cio_test_o (fuse_ctrl_out_if_agent_bus.cio_test_o), //(otp_ctrl_if.cio_test_o), + .cio_test_en_o (fuse_ctrl_out_if_agent_bus.cio_test_en_o) //(otp_ctrl_if.cio_test_en_o) + ); + + // AXI Core Interface + axi_if #( + .AW (AXI_AW), + .DW (AXI_DW), + .IW (AXI_IW), + .UW (AXI_UW) + ) axi_core_if ( + .clk (fuse_ctrl_rst_in_agent_bus.clk_i ), + .rst_n (fuse_ctrl_rst_in_agent_bus.rst_ni ) + ); + + // AXI Prim Interface + axi_if #( + .AW (AXI_AW), + .DW (AXI_DW), + .IW (AXI_IW), + .UW (AXI_UW) + ) axi_prim_if ( + .clk (fuse_ctrl_rst_in_agent_bus.clk_i ), + .rst_n (fuse_ctrl_rst_in_agent_bus.rst_ni) + ); + + // AXI Secret Reg Interface + axi_if #( + .AW (AXI_AW), + .DW (AXI_DW), + .IW (AXI_IW), + .UW (AXI_UW) + ) axi_secreg_if ( + .clk (fuse_ctrl_rst_in_agent_bus.clk_i ), + .rst_n (fuse_ctrl_rst_in_agent_bus.rst_ni) + ); + + // Core AXI IF + assign fuse_ctrl_core_axi_write_in_if_agent_bus.awaddr = axi_core_if.awaddr; + assign fuse_ctrl_core_axi_write_in_if_agent_bus.awburst = axi_core_if.awburst; + assign fuse_ctrl_core_axi_write_in_if_agent_bus.awsize = axi_core_if.awsize; + assign fuse_ctrl_core_axi_write_in_if_agent_bus.awlen = axi_core_if.awlen; + assign fuse_ctrl_core_axi_write_in_if_agent_bus.awuser = axi_core_if.awuser; + assign fuse_ctrl_core_axi_write_in_if_agent_bus.awid = axi_core_if.awid; + assign fuse_ctrl_core_axi_write_in_if_agent_bus.awlock = axi_core_if.awlock; + assign fuse_ctrl_core_axi_write_in_if_agent_bus.awvalid = axi_core_if.awvalid; + assign fuse_ctrl_core_axi_write_in_if_agent_bus.wdata = axi_core_if.wdata; + assign fuse_ctrl_core_axi_write_in_if_agent_bus.wstrb = axi_core_if.wstrb; + assign fuse_ctrl_core_axi_write_in_if_agent_bus.wlast = axi_core_if.wlast; + assign fuse_ctrl_core_axi_write_in_if_agent_bus.wvalid = axi_core_if.wvalid; + assign fuse_ctrl_core_axi_write_in_if_agent_bus.bready = axi_core_if.bready; + + assign fuse_ctrl_core_axi_write_out_if_agent_bus.awready = axi_core_if.awready; + assign fuse_ctrl_core_axi_write_out_if_agent_bus.wready = axi_core_if.wready; + assign fuse_ctrl_core_axi_write_out_if_agent_bus.bresp = axi_core_if.bresp; + assign fuse_ctrl_core_axi_write_out_if_agent_bus.bvalid = axi_core_if.bvalid; + assign fuse_ctrl_core_axi_write_out_if_agent_bus.bid = axi_core_if.bid; + + assign fuse_ctrl_core_axi_read_in_if_agent_bus.araddr = axi_core_if.araddr; + assign fuse_ctrl_core_axi_read_in_if_agent_bus.arburst = axi_core_if.arburst; + assign fuse_ctrl_core_axi_read_in_if_agent_bus.arsize = axi_core_if.arsize; + assign fuse_ctrl_core_axi_read_in_if_agent_bus.arlen = axi_core_if.arlen; + assign fuse_ctrl_core_axi_read_in_if_agent_bus.aruser = axi_core_if.aruser; + assign fuse_ctrl_core_axi_read_in_if_agent_bus.arid = axi_core_if.arid; + assign fuse_ctrl_core_axi_read_in_if_agent_bus.arlock = axi_core_if.arlock; + assign fuse_ctrl_core_axi_read_in_if_agent_bus.arvalid = axi_core_if.arvalid; + assign fuse_ctrl_core_axi_read_in_if_agent_bus.rready = axi_core_if.rready; + + assign fuse_ctrl_core_axi_read_out_if_agent_bus.arready = axi_core_if.arready; + assign fuse_ctrl_core_axi_read_out_if_agent_bus.rdata = axi_core_if.rdata; + assign fuse_ctrl_core_axi_read_out_if_agent_bus.rresp = axi_core_if.rresp; + assign fuse_ctrl_core_axi_read_out_if_agent_bus.rid = axi_core_if.rid; + assign fuse_ctrl_core_axi_read_out_if_agent_bus.rvalid = axi_core_if.rvalid; + assign fuse_ctrl_core_axi_read_out_if_agent_bus.rlast = axi_core_if.rlast; + + // Prim AXI IF + assign fuse_ctrl_prim_axi_write_in_if_agent_bus.awaddr = axi_prim_if.awaddr; + assign fuse_ctrl_prim_axi_write_in_if_agent_bus.awburst = axi_prim_if.awburst; + assign fuse_ctrl_prim_axi_write_in_if_agent_bus.awsize = axi_prim_if.awsize; + assign fuse_ctrl_prim_axi_write_in_if_agent_bus.awlen = axi_prim_if.awlen; + assign fuse_ctrl_prim_axi_write_in_if_agent_bus.awuser = axi_prim_if.awuser; + assign fuse_ctrl_prim_axi_write_in_if_agent_bus.awid = axi_prim_if.awid; + assign fuse_ctrl_prim_axi_write_in_if_agent_bus.awlock = axi_prim_if.awlock; + assign fuse_ctrl_prim_axi_write_in_if_agent_bus.awvalid = axi_prim_if.awvalid; + assign fuse_ctrl_prim_axi_write_in_if_agent_bus.wdata = axi_prim_if.wdata; + assign fuse_ctrl_prim_axi_write_in_if_agent_bus.wstrb = axi_prim_if.wstrb; + assign fuse_ctrl_prim_axi_write_in_if_agent_bus.wlast = axi_prim_if.wlast; + assign fuse_ctrl_prim_axi_write_in_if_agent_bus.wvalid = axi_prim_if.wvalid; + assign fuse_ctrl_prim_axi_write_in_if_agent_bus.bready = axi_prim_if.bready; + assign fuse_ctrl_prim_axi_write_out_if_agent_bus.awready = axi_prim_if.awready; + assign fuse_ctrl_prim_axi_write_out_if_agent_bus.wready = axi_prim_if.wready; + assign fuse_ctrl_prim_axi_write_out_if_agent_bus.bresp = axi_prim_if.bresp; + assign fuse_ctrl_prim_axi_write_out_if_agent_bus.bvalid = axi_prim_if.bvalid; + assign fuse_ctrl_prim_axi_write_out_if_agent_bus.bid = axi_prim_if.bid; + + assign fuse_ctrl_prim_axi_read_in_if_agent_bus.araddr = axi_prim_if.araddr; + assign fuse_ctrl_prim_axi_read_in_if_agent_bus.arburst = axi_prim_if.arburst; + assign fuse_ctrl_prim_axi_read_in_if_agent_bus.arsize = axi_prim_if.arsize; + assign fuse_ctrl_prim_axi_read_in_if_agent_bus.arlen = axi_prim_if.arlen; + assign fuse_ctrl_prim_axi_read_in_if_agent_bus.aruser = axi_prim_if.aruser; + assign fuse_ctrl_prim_axi_read_in_if_agent_bus.arid = axi_prim_if.arid; + assign fuse_ctrl_prim_axi_read_in_if_agent_bus.arlock = axi_prim_if.arlock; + assign fuse_ctrl_prim_axi_read_in_if_agent_bus.arvalid = axi_prim_if.arvalid; + assign fuse_ctrl_prim_axi_read_in_if_agent_bus.rready = axi_prim_if.rready; + + assign fuse_ctrl_prim_axi_read_out_if_agent_bus.arready = axi_prim_if.arready; + assign fuse_ctrl_prim_axi_read_out_if_agent_bus.rdata = axi_prim_if.rdata; + assign fuse_ctrl_prim_axi_read_out_if_agent_bus.rresp = axi_prim_if.rresp; + assign fuse_ctrl_prim_axi_read_out_if_agent_bus.rid = axi_prim_if.rid; + assign fuse_ctrl_prim_axi_read_out_if_agent_bus.rvalid = axi_prim_if.rvalid; + assign fuse_ctrl_prim_axi_read_out_if_agent_bus.rlast = axi_prim_if.rlast; + + // Secreg AXI IF + assign fuse_ctrl_secreg_axi_read_in_if_agent_bus.araddr = axi_secreg_if.araddr; + assign fuse_ctrl_secreg_axi_read_in_if_agent_bus.arburst = axi_secreg_if.arburst; + assign fuse_ctrl_secreg_axi_read_in_if_agent_bus.arsize = axi_secreg_if.arsize; + assign fuse_ctrl_secreg_axi_read_in_if_agent_bus.arlen = axi_secreg_if.arlen; + assign fuse_ctrl_secreg_axi_read_in_if_agent_bus.aruser = axi_secreg_if.aruser; + assign fuse_ctrl_secreg_axi_read_in_if_agent_bus.arid = axi_secreg_if.arid; + assign fuse_ctrl_secreg_axi_read_in_if_agent_bus.arlock = axi_secreg_if.arlock; + assign fuse_ctrl_secreg_axi_read_in_if_agent_bus.arvalid = axi_secreg_if.arvalid; + assign fuse_ctrl_secreg_axi_read_in_if_agent_bus.rready = axi_secreg_if.rready; + + assign fuse_ctrl_secreg_axi_read_out_if_agent_bus.arready = axi_secreg_if.arready; + assign fuse_ctrl_secreg_axi_read_out_if_agent_bus.rdata = axi_secreg_if.rdata; + assign fuse_ctrl_secreg_axi_read_out_if_agent_bus.rresp = axi_secreg_if.rresp; + assign fuse_ctrl_secreg_axi_read_out_if_agent_bus.rid = axi_secreg_if.rid; + assign fuse_ctrl_secreg_axi_read_out_if_agent_bus.rvalid = axi_secreg_if.rvalid; + assign fuse_ctrl_secreg_axi_read_out_if_agent_bus.rlast = axi_secreg_if.rlast; + // pragma uvmf custom dut_instantiation end + + initial begin // tbx vif_binding_block + import uvm_pkg::uvm_config_db; + // The monitor_bfm and driver_bfm for each interface is placed into the uvm_config_db. + // They are placed into the uvm_config_db using the string names defined in the parameters package. + // The string names are passed to the agent configurations by test_top through the top level configuration. + // They are retrieved by the agents configuration class for use by the agent. + uvm_config_db #( virtual fuse_ctrl_rst_in_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , fuse_ctrl_rst_in_agent_BFM , fuse_ctrl_rst_in_agent_mon_bfm ); + uvm_config_db #( virtual fuse_ctrl_rst_out_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , fuse_ctrl_rst_out_agent_BFM , fuse_ctrl_rst_out_agent_mon_bfm ); + uvm_config_db #( virtual fuse_ctrl_core_axi_write_in_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , fuse_ctrl_core_axi_write_in_if_agent_BFM , fuse_ctrl_core_axi_write_in_if_agent_mon_bfm ); + uvm_config_db #( virtual fuse_ctrl_core_axi_write_out_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , fuse_ctrl_core_axi_write_out_if_agent_BFM , fuse_ctrl_core_axi_write_out_if_agent_mon_bfm ); + uvm_config_db #( virtual fuse_ctrl_prim_axi_write_in_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , fuse_ctrl_prim_axi_write_in_if_agent_BFM , fuse_ctrl_prim_axi_write_in_if_agent_mon_bfm ); + uvm_config_db #( virtual fuse_ctrl_prim_axi_write_out_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , fuse_ctrl_prim_axi_write_out_if_agent_BFM , fuse_ctrl_prim_axi_write_out_if_agent_mon_bfm ); + uvm_config_db #( virtual fuse_ctrl_core_axi_read_in_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , fuse_ctrl_core_axi_read_in_if_agent_BFM , fuse_ctrl_core_axi_read_in_if_agent_mon_bfm ); + uvm_config_db #( virtual fuse_ctrl_core_axi_read_out_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , fuse_ctrl_core_axi_read_out_if_agent_BFM , fuse_ctrl_core_axi_read_out_if_agent_mon_bfm ); + uvm_config_db #( virtual fuse_ctrl_prim_axi_read_in_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , fuse_ctrl_prim_axi_read_in_if_agent_BFM , fuse_ctrl_prim_axi_read_in_if_agent_mon_bfm ); + uvm_config_db #( virtual fuse_ctrl_prim_axi_read_out_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , fuse_ctrl_prim_axi_read_out_if_agent_BFM , fuse_ctrl_prim_axi_read_out_if_agent_mon_bfm ); + uvm_config_db #( virtual fuse_ctrl_secreg_axi_read_in_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , fuse_ctrl_secreg_axi_read_in_if_agent_BFM , fuse_ctrl_secreg_axi_read_in_if_agent_mon_bfm ); + uvm_config_db #( virtual fuse_ctrl_secreg_axi_read_out_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , fuse_ctrl_secreg_axi_read_out_if_agent_BFM , fuse_ctrl_secreg_axi_read_out_if_agent_mon_bfm ); + uvm_config_db #( virtual fuse_ctrl_lc_otp_in_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , fuse_ctrl_lc_otp_in_if_agent_BFM , fuse_ctrl_lc_otp_in_if_agent_mon_bfm ); + uvm_config_db #( virtual fuse_ctrl_lc_otp_out_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , fuse_ctrl_lc_otp_out_if_agent_BFM , fuse_ctrl_lc_otp_out_if_agent_mon_bfm ); + uvm_config_db #( virtual fuse_ctrl_in_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , fuse_ctrl_in_if_agent_BFM , fuse_ctrl_in_if_agent_mon_bfm ); + uvm_config_db #( virtual fuse_ctrl_out_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , fuse_ctrl_out_if_agent_BFM , fuse_ctrl_out_if_agent_mon_bfm ); + uvm_config_db #( virtual fuse_ctrl_rst_in_driver_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , fuse_ctrl_rst_in_agent_BFM , fuse_ctrl_rst_in_agent_drv_bfm ); + uvm_config_db #( virtual fuse_ctrl_core_axi_write_in_driver_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , fuse_ctrl_core_axi_write_in_if_agent_BFM , fuse_ctrl_core_axi_write_in_if_agent_drv_bfm ); + uvm_config_db #( virtual fuse_ctrl_prim_axi_write_in_driver_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , fuse_ctrl_prim_axi_write_in_if_agent_BFM , fuse_ctrl_prim_axi_write_in_if_agent_drv_bfm ); + uvm_config_db #( virtual fuse_ctrl_core_axi_read_in_driver_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , fuse_ctrl_core_axi_read_in_if_agent_BFM , fuse_ctrl_core_axi_read_in_if_agent_drv_bfm ); + uvm_config_db #( virtual fuse_ctrl_prim_axi_read_in_driver_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , fuse_ctrl_prim_axi_read_in_if_agent_BFM , fuse_ctrl_prim_axi_read_in_if_agent_drv_bfm ); + uvm_config_db #( virtual fuse_ctrl_secreg_axi_read_in_driver_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , fuse_ctrl_secreg_axi_read_in_if_agent_BFM , fuse_ctrl_secreg_axi_read_in_if_agent_drv_bfm ); + uvm_config_db #( virtual fuse_ctrl_lc_otp_in_driver_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , fuse_ctrl_lc_otp_in_if_agent_BFM , fuse_ctrl_lc_otp_in_if_agent_drv_bfm ); + uvm_config_db #( virtual fuse_ctrl_in_driver_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , fuse_ctrl_in_if_agent_BFM , fuse_ctrl_in_if_agent_drv_bfm ); + end + +endmodule + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/testbench/hdl_top.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/testbench/hdl_top.vinfo new file mode 100644 index 0000000..b39169a --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/testbench/hdl_top.vinfo @@ -0,0 +1,20 @@ +@use $UVMF_PROJECT_DIR/rtl/verilog/verilog_dut.vinfo +@use $UVMF_PROJECT_DIR/tb/parameters/fuse_ctrl_parameters_pkg.vinfo +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_bfm.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_bfm.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_bfm.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_bfm.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_bfm.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_bfm.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_bfm.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_bfm.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_bfm.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_bfm.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_bfm.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_bfm.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_bfm.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_bfm.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_bfm.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_bfm.vinfo +hdl_top.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/testbench/hvl_top.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/testbench/hvl_top.compile new file mode 100644 index 0000000..0404887 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/testbench/hvl_top.compile @@ -0,0 +1,7 @@ +incdir: + - ${uvm_path}/src + - . +needs: + - ../tests/fuse_ctrl_tests_pkg.compile +src: + - hvl_top.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/testbench/hvl_top.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/testbench/hvl_top.sv new file mode 100644 index 0000000..68e3fc6 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/testbench/hvl_top.sv @@ -0,0 +1,47 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// +// DESCRIPTION: This module loads the test package and starts the UVM phases. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +module hvl_top; + +import uvm_pkg::*; +import fuse_ctrl_tests_pkg::*; + + // pragma uvmf custom module_item_additional begin + // pragma uvmf custom module_item_additional end + + initial begin + $timeformat(-9,3,"ns",5); + run_test(); + end + +endmodule + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/testbench/hvl_top.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/testbench/hvl_top.vinfo new file mode 100644 index 0000000..31185e4 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/testbench/hvl_top.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_PROJECT_DIR/tb/tests/fuse_ctrl_tests_pkg.vinfo +hvl_top.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/testbench/top_filelist_hdl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/testbench/top_filelist_hdl.f new file mode 100644 index 0000000..1e9dab6 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/testbench/top_filelist_hdl.f @@ -0,0 +1,3 @@ +$UVMF_PROJECT_DIR/tb/testbench/hdl_top.sv +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/testbench/top_filelist_hvl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/testbench/top_filelist_hvl.f new file mode 100644 index 0000000..42383ab --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/testbench/top_filelist_hvl.f @@ -0,0 +1,3 @@ +$UVMF_PROJECT_DIR/tb/testbench/hvl_top.sv +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/tests/fuse_ctrl_tests_pkg.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/tests/fuse_ctrl_tests_pkg.compile new file mode 100644 index 0000000..c755851 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/tests/fuse_ctrl_tests_pkg.compile @@ -0,0 +1,23 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out.compile + - ../../../../verification_ip/environment_packages/fuse_ctrl_env_pkg/fuse_ctrl_env_pkg.compile + - ../parameters/fuse_ctrl_parameters_pkg.compile + - ../sequences/fuse_ctrl_sequences_pkg.compile +src: + - fuse_ctrl_tests_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/tests/fuse_ctrl_tests_pkg.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/tests/fuse_ctrl_tests_pkg.sv new file mode 100644 index 0000000..05f83c5 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/tests/fuse_ctrl_tests_pkg.sv @@ -0,0 +1,96 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This package contains all tests currently written for +// the simulation project. Once compiled, any test can be selected +// from the vsim command line using +UVM_TESTNAME=yourTestNameHere +// +// CONTAINS: +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +package fuse_ctrl_tests_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg::*; + import fuse_ctrl_parameters_pkg::*; + import fuse_ctrl_env_pkg::*; + import fuse_ctrl_sequences_pkg::*; + import fuse_ctrl_rst_in_pkg::*; + import fuse_ctrl_rst_in_pkg_hdl::*; + import fuse_ctrl_rst_out_pkg::*; + import fuse_ctrl_rst_out_pkg_hdl::*; + import fuse_ctrl_core_axi_write_in_pkg::*; + import fuse_ctrl_core_axi_write_in_pkg_hdl::*; + import fuse_ctrl_core_axi_write_out_pkg::*; + import fuse_ctrl_core_axi_write_out_pkg_hdl::*; + import fuse_ctrl_prim_axi_write_in_pkg::*; + import fuse_ctrl_prim_axi_write_in_pkg_hdl::*; + import fuse_ctrl_prim_axi_write_out_pkg::*; + import fuse_ctrl_prim_axi_write_out_pkg_hdl::*; + import fuse_ctrl_core_axi_read_in_pkg::*; + import fuse_ctrl_core_axi_read_in_pkg_hdl::*; + import fuse_ctrl_core_axi_read_out_pkg::*; + import fuse_ctrl_core_axi_read_out_pkg_hdl::*; + import fuse_ctrl_prim_axi_read_in_pkg::*; + import fuse_ctrl_prim_axi_read_in_pkg_hdl::*; + import fuse_ctrl_prim_axi_read_out_pkg::*; + import fuse_ctrl_prim_axi_read_out_pkg_hdl::*; + import fuse_ctrl_secreg_axi_read_in_pkg::*; + import fuse_ctrl_secreg_axi_read_in_pkg_hdl::*; + import fuse_ctrl_secreg_axi_read_out_pkg::*; + import fuse_ctrl_secreg_axi_read_out_pkg_hdl::*; + import fuse_ctrl_lc_otp_in_pkg::*; + import fuse_ctrl_lc_otp_in_pkg_hdl::*; + import fuse_ctrl_lc_otp_out_pkg::*; + import fuse_ctrl_lc_otp_out_pkg_hdl::*; + import fuse_ctrl_in_pkg::*; + import fuse_ctrl_in_pkg_hdl::*; + import fuse_ctrl_out_pkg::*; + import fuse_ctrl_out_pkg_hdl::*; + + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + `include "src/test_top.svh" + `include "src/register_test.svh" + `include "src/example_derived_test.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new tests to the src directory + // be sure to add the test file here so that it will be + // compiled as part of the test package. Be sure to place + // the new test after any base tests of the new test. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/tests/fuse_ctrl_tests_pkg.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/tests/fuse_ctrl_tests_pkg.vinfo new file mode 100644 index 0000000..651052b --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/tests/fuse_ctrl_tests_pkg.vinfo @@ -0,0 +1,22 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/environment_packages/fuse_ctrl_env_pkg/fuse_ctrl_env_pkg.vinfo +@use $UVMF_PROJECT_DIR/tb/parameters/fuse_ctrl_parameters_pkg.vinfo +@use $UVMF_PROJECT_DIR/tb/sequences/fuse_ctrl_sequences_pkg.vinfo ++incdir+@vinfodir +fuse_ctrl_tests_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/tests/src/example_derived_test.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/tests/src/example_derived_test.svh new file mode 100644 index 0000000..82d6c45 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/tests/src/example_derived_test.svh @@ -0,0 +1,57 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This test extends test_top and makes +// changes to test_top using the UVM factory type_override: +// +// Test scenario: +// This is a template test that can be used to create future tests. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class example_derived_test extends test_top; + + `uvm_component_utils( example_derived_test ); + + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + + virtual function void build_phase(uvm_phase phase); + // The factory override below is an example of how to replace the fuse_ctrl_bench_sequence_base + // sequence with the example_derived_test_sequence. + fuse_ctrl_bench_sequence_base::type_id::set_type_override(example_derived_test_sequence::get_type()); + // Execute the build_phase of test_top AFTER all factory overrides have been created. + super.build_phase(phase); + // pragma uvmf custom configuration_settings_post_randomize begin + // UVMF_CHANGE_ME Test specific configuration values can be set here. + // The configuration structure has already been randomized. + // pragma uvmf custom configuration_settings_post_randomize end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/tests/src/register_test.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/tests/src/register_test.svh new file mode 100644 index 0000000..1be7222 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/tests/src/register_test.svh @@ -0,0 +1,54 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This test extends test_top and makes +// changes to test_top using the UVM factory type_override: +// +// Test scenario: +// This is a template test that can be used to create future tests. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class register_test extends test_top; + + `uvm_component_utils( register_test ); + + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + + virtual function void build_phase(uvm_phase phase); + // The factory override below replaces the fuse_ctrl_bench_sequence_base + // sequence with the register_test_sequence. + fuse_ctrl_bench_sequence_base::type_id::set_type_override(register_test_sequence::get_type()); + // Execute the build_phase of test_top AFTER all factory overrides have been created. + super.build_phase(phase); + endfunction + + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/tests/src/test_top.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/tests/src/test_top.svh new file mode 100644 index 0000000..f5b1c3c --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/tb/tests/src/test_top.svh @@ -0,0 +1,120 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// Description: This top level UVM test is the base class for all +// future tests created for this project. +// +// This test class contains: +// Configuration: The top level configuration for the project. +// Environment: The top level environment for the project. +// Top_level_sequence: The top level sequence for the project. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +typedef fuse_ctrl_env_configuration fuse_ctrl_env_configuration_t; +typedef fuse_ctrl_environment fuse_ctrl_environment_t; + +class test_top extends uvmf_test_base #(.CONFIG_T(fuse_ctrl_env_configuration_t), + .ENV_T(fuse_ctrl_environment_t), + .TOP_LEVEL_SEQ_T(fuse_ctrl_bench_sequence_base)); + + `uvm_component_utils( test_top ); + + + + string interface_names[] = { + fuse_ctrl_rst_in_agent_BFM /* fuse_ctrl_rst_in_agent [0] */ , + fuse_ctrl_rst_out_agent_BFM /* fuse_ctrl_rst_out_agent [1] */ , + fuse_ctrl_core_axi_write_in_if_agent_BFM /* fuse_ctrl_core_axi_write_in_if_agent [2] */ , + fuse_ctrl_core_axi_write_out_if_agent_BFM /* fuse_ctrl_core_axi_write_out_if_agent [3] */ , + fuse_ctrl_prim_axi_write_in_if_agent_BFM /* fuse_ctrl_prim_axi_write_in_if_agent [4] */ , + fuse_ctrl_prim_axi_write_out_if_agent_BFM /* fuse_ctrl_prim_axi_write_out_if_agent [5] */ , + fuse_ctrl_core_axi_read_in_if_agent_BFM /* fuse_ctrl_core_axi_read_in_if_agent [6] */ , + fuse_ctrl_core_axi_read_out_if_agent_BFM /* fuse_ctrl_core_axi_read_out_if_agent [7] */ , + fuse_ctrl_prim_axi_read_in_if_agent_BFM /* fuse_ctrl_prim_axi_read_in_if_agent [8] */ , + fuse_ctrl_prim_axi_read_out_if_agent_BFM /* fuse_ctrl_prim_axi_read_out_if_agent [9] */ , + fuse_ctrl_secreg_axi_read_in_if_agent_BFM /* fuse_ctrl_secreg_axi_read_in_if_agent [10] */ , + fuse_ctrl_secreg_axi_read_out_if_agent_BFM /* fuse_ctrl_secreg_axi_read_out_if_agent [11] */ , + fuse_ctrl_lc_otp_in_if_agent_BFM /* fuse_ctrl_lc_otp_in_if_agent [12] */ , + fuse_ctrl_lc_otp_out_if_agent_BFM /* fuse_ctrl_lc_otp_out_if_agent [13] */ , + fuse_ctrl_in_if_agent_BFM /* fuse_ctrl_in_if_agent [14] */ , + fuse_ctrl_out_if_agent_BFM /* fuse_ctrl_out_if_agent [15] */ +}; + +uvmf_active_passive_t interface_activities[] = { + ACTIVE /* fuse_ctrl_rst_in_agent [0] */ , + PASSIVE /* fuse_ctrl_rst_out_agent [1] */ , + ACTIVE /* fuse_ctrl_core_axi_write_in_if_agent [2] */ , + PASSIVE /* fuse_ctrl_core_axi_write_out_if_agent [3] */ , + ACTIVE /* fuse_ctrl_prim_axi_write_in_if_agent [4] */ , + PASSIVE /* fuse_ctrl_prim_axi_write_out_if_agent [5] */ , + ACTIVE /* fuse_ctrl_core_axi_read_in_if_agent [6] */ , + PASSIVE /* fuse_ctrl_core_axi_read_out_if_agent [7] */ , + ACTIVE /* fuse_ctrl_prim_axi_read_in_if_agent [8] */ , + PASSIVE /* fuse_ctrl_prim_axi_read_out_if_agent [9] */ , + ACTIVE /* fuse_ctrl_secreg_axi_read_in_if_agent [10] */ , + PASSIVE /* fuse_ctrl_secreg_axi_read_out_if_agent [11] */ , + ACTIVE /* fuse_ctrl_lc_otp_in_if_agent [12] */ , + PASSIVE /* fuse_ctrl_lc_otp_out_if_agent [13] */ , + ACTIVE /* fuse_ctrl_in_if_agent [14] */ , + PASSIVE /* fuse_ctrl_out_if_agent [15] */ }; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // FUNCTION: new() + // This is the standard systemVerilog constructor. All components are + // constructed in the build_phase to allow factory overriding. + // + function new( string name = "", uvm_component parent = null ); + super.new( name ,parent ); + endfunction + + + + // **************************************************************************** + // FUNCTION: build_phase() + // The construction of the configuration and environment classes is done in + // the build_phase of uvmf_test_base. Once the configuraton and environment + // classes are built then the initialize call is made to perform the + // following: + // Monitor and driver BFM virtual interface handle passing into agents + // Set the active/passive state for each agent + // Once this build_phase completes, the build_phase of the environment is + // executed which builds the agents. + // + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + // pragma uvmf custom configuration_settings_post_randomize begin + // pragma uvmf custom configuration_settings_post_randomize end + configuration.initialize(NA, "uvm_test_top.environment", interface_names, null, interface_activities); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/yaml/fuse_ctrl_bench.yaml b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/yaml/fuse_ctrl_bench.yaml new file mode 100644 index 0000000..24489d9 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/project_benches/fuse_ctrl/yaml/fuse_ctrl_bench.yaml @@ -0,0 +1,45 @@ +uvmf: + benches: + fuse_ctrl: + active_passive: + - bfm_name: fuse_ctrl_rst_in_agent + value: ACTIVE + - bfm_name: fuse_ctrl_rst_out_agent + value: PASSIVE + - bfm_name: fuse_ctrl_core_axi_write_in_if_agent + value: ACTIVE + - bfm_name: fuse_ctrl_core_axi_write_out_if_agent + value: PASSIVE + - bfm_name: fuse_ctrl_prim_axi_write_in_if_agent + value: ACTIVE + - bfm_name: fuse_ctrl_prim_axi_write_out_if_agent + value: PASSIVE + - bfm_name: fuse_ctrl_core_axi_read_in_if_agent + value: ACTIVE + - bfm_name: fuse_ctrl_core_axi_read_out_if_agent + value: PASSIVE + - bfm_name: fuse_ctrl_prim_axi_read_in_if_agent + value: ACTIVE + - bfm_name: fuse_ctrl_prim_axi_read_out_if_agent + value: PASSIVE + - bfm_name: fuse_ctrl_secreg_axi_read_in_if_agent + value: ACTIVE + - bfm_name: fuse_ctrl_secreg_axi_read_out_if_agent + value: PASSIVE + - bfm_name: fuse_ctrl_lc_otp_in_if_agent + value: ACTIVE + - bfm_name: fuse_ctrl_lc_otp_out_if_agent + value: PASSIVE + - bfm_name: fuse_ctrl_in_if_agent + value: ACTIVE + - bfm_name: fuse_ctrl_out_if_agent + value: PASSIVE + active_passive_default: ACTIVE + clock_half_period: 5ns + clock_phase_offset: 0ns + existing_library_component: 'True' + interface_params: [] + reset_assertion_level: 'False' + reset_duration: 200ns + top_env: fuse_ctrl + use_dpi_link: 'False' diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/environment_packages/fuse_ctrl_env_pkg/.project b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/environment_packages/fuse_ctrl_env_pkg/.project new file mode 100644 index 0000000..ec64afa --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/environment_packages/fuse_ctrl_env_pkg/.project @@ -0,0 +1,32 @@ + + + fuse_ctrl_env_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/environment_packages/fuse_ctrl_env_pkg/.svproject b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/environment_packages/fuse_ctrl_env_pkg/.svproject new file mode 100644 index 0000000..bcfe6ac --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/environment_packages/fuse_ctrl_env_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/environment_packages/fuse_ctrl_env_pkg/Makefile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/environment_packages/fuse_ctrl_env_pkg/Makefile new file mode 100644 index 0000000..4cf61d5 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/environment_packages/fuse_ctrl_env_pkg/Makefile @@ -0,0 +1,56 @@ +# fuse_ctrl environment packages source and make target + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +# Include all requisite sub-environment package targets for this bench + +fuse_ctrl_ENV_PKG =\ + $(UVMF_VIP_LIBRARY_HOME)/environment_packages/fuse_ctrl_env_pkg/fuse_ctrl_env_pkg.sv + +COMP_fuse_ctrl_PKG_TGT_0 = q_comp_fuse_ctrl_env_pkg +COMP_fuse_ctrl_PKG_TGT_1 = v_comp_fuse_ctrl_env_pkg +COMP_fuse_ctrl_PKG_TGT = $(COMP_fuse_ctrl_PKG_TGT_$(USE_VELOCE)) + +comp_fuse_ctrl_env_pkg: $(COMP_fuse_ctrl_PKG_TGT) + +q_comp_fuse_ctrl_env_pkg: + $(HVL_COMP_CMD) +incdir+$(UVMF_VIP_LIBRARY_HOME)/environment_packages/fuse_ctrl_env_pkg $(fuse_ctrl_ENV_PKG) + +v_comp_fuse_ctrl_env_pkg: q_comp_fuse_ctrl_env_pkg + $(VELANALYZE_HVL_CMD) +incdir+$(UVMF_VIP_LIBRARY_HOME)/environment_packages/fuse_ctrl_env_pkg $(fuse_ctrl_ENV_PKG) + + + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export fuse_ctrl_ENV_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/environment_packages/fuse_ctrl_env_pkg/dpi + +C_FILE_COMPILE_LIST_fuse_ctrl_env_pkg = \ + +O_FILE_COMPILE_LIST_fuse_ctrl_env_pkg = $(notdir $(C_FILE_COMPILE_LIST_fuse_ctrl_env_pkg:.c=.o)) + +GCC_COMP_ARGS_fuse_ctrl_env_pkg += -I$(fuse_ctrl_ENV_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_fuse_ctrl_env_pkg += $(fuse_ctrl_ENV_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_fuse_ctrl_env_pkg += \ + \ + -o .so + +comp_fuse_ctrl_env_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Environment C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_fuse_ctrl_env_pkg) $(C_FILE_COMPILE_LIST_fuse_ctrl_env_pkg) + @echo "--------------------------------" + @echo "Linking Environment C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_fuse_ctrl_env_pkg) $(O_FILE_COMPILE_LIST_fuse_ctrl_env_pkg) + @echo "--------------------------------" + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/environment_packages/fuse_ctrl_env_pkg/compile.do b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/environment_packages/fuse_ctrl_env_pkg/compile.do new file mode 100644 index 0000000..05dca66 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/environment_packages/fuse_ctrl_env_pkg/compile.do @@ -0,0 +1,12 @@ +# Tcl do file for compile of fuse_ctrl interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + + +quietly set cmd [format "vlog -timescale 1ps/1ps +incdir+%s/environment_packages/fuse_ctrl_env_pkg" $env(UVMF_VIP_LIBRARY_HOME)] +quietly set cmd [format "%s %s/environment_packages/fuse_ctrl_env_pkg/fuse_ctrl_env_pkg.sv" $cmd $env(UVMF_VIP_LIBRARY_HOME)] +eval $cmd + + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/environment_packages/fuse_ctrl_env_pkg/fuse_ctrl_env_pkg.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/environment_packages/fuse_ctrl_env_pkg/fuse_ctrl_env_pkg.compile new file mode 100644 index 0000000..7bd08d6 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/environment_packages/fuse_ctrl_env_pkg/fuse_ctrl_env_pkg.compile @@ -0,0 +1,22 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ../../../verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_hvl.compile + - ../../../verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_hvl.compile + - ../../../verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_hvl.compile + - ../../../verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_hvl.compile + - ../../../verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_hvl.compile + - ../../../verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_hvl.compile + - ../../../verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_hvl.compile + - ../../../verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_hvl.compile + - ../../../verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_hvl.compile + - ../../../verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_hvl.compile + - ../../../verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_hvl.compile + - ../../../verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_hvl.compile + - ../../../verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_hvl.compile + - ../../../verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_hvl.compile + - ../../../verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_hvl.compile + - ../../../verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_hvl.compile + +src: + - fuse_ctrl_env_pkg.sv + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/environment_packages/fuse_ctrl_env_pkg/fuse_ctrl_env_pkg.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/environment_packages/fuse_ctrl_env_pkg/fuse_ctrl_env_pkg.sv new file mode 100644 index 0000000..a58a3ce --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/environment_packages/fuse_ctrl_env_pkg/fuse_ctrl_env_pkg.sv @@ -0,0 +1,106 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// environment package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_env_pkg; + + import uvm_pkg::*; + `include "uvm_macros.svh" + import uvmf_base_pkg::*; + import fuse_ctrl_rst_in_pkg::*; + import fuse_ctrl_rst_in_pkg_hdl::*; + import fuse_ctrl_rst_out_pkg::*; + import fuse_ctrl_rst_out_pkg_hdl::*; + import fuse_ctrl_core_axi_write_in_pkg::*; + import fuse_ctrl_core_axi_write_in_pkg_hdl::*; + import fuse_ctrl_core_axi_write_out_pkg::*; + import fuse_ctrl_core_axi_write_out_pkg_hdl::*; + import fuse_ctrl_prim_axi_write_in_pkg::*; + import fuse_ctrl_prim_axi_write_in_pkg_hdl::*; + import fuse_ctrl_prim_axi_write_out_pkg::*; + import fuse_ctrl_prim_axi_write_out_pkg_hdl::*; + import fuse_ctrl_core_axi_read_in_pkg::*; + import fuse_ctrl_core_axi_read_in_pkg_hdl::*; + import fuse_ctrl_core_axi_read_out_pkg::*; + import fuse_ctrl_core_axi_read_out_pkg_hdl::*; + import fuse_ctrl_prim_axi_read_in_pkg::*; + import fuse_ctrl_prim_axi_read_in_pkg_hdl::*; + import fuse_ctrl_prim_axi_read_out_pkg::*; + import fuse_ctrl_prim_axi_read_out_pkg_hdl::*; + import fuse_ctrl_secreg_axi_read_in_pkg::*; + import fuse_ctrl_secreg_axi_read_in_pkg_hdl::*; + import fuse_ctrl_secreg_axi_read_out_pkg::*; + import fuse_ctrl_secreg_axi_read_out_pkg_hdl::*; + import fuse_ctrl_lc_otp_in_pkg::*; + import fuse_ctrl_lc_otp_in_pkg_hdl::*; + import fuse_ctrl_lc_otp_out_pkg::*; + import fuse_ctrl_lc_otp_out_pkg_hdl::*; + import fuse_ctrl_in_pkg::*; + import fuse_ctrl_in_pkg_hdl::*; + import fuse_ctrl_out_pkg::*; + import fuse_ctrl_out_pkg_hdl::*; + + `uvm_analysis_imp_decl(_fuse_ctrl_lc_otp_in_agent_ae) + `uvm_analysis_imp_decl(_fuse_ctrl_rst_in_agent_ae) + `uvm_analysis_imp_decl(_fuse_ctrl_core_axi_write_in_agent_ae) + `uvm_analysis_imp_decl(_fuse_ctrl_secreg_axi_read_in_agent_ae) + `uvm_analysis_imp_decl(_fuse_ctrl_prim_axi_write_in_agent_ae) + `uvm_analysis_imp_decl(_fuse_ctrl_in_agent_ae) + `uvm_analysis_imp_decl(_fuse_ctrl_core_axi_read_in_agent_ae) + `uvm_analysis_imp_decl(_fuse_ctrl_prim_axi_read_in_agent_ae) + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HVL parameters + + `include "src/fuse_ctrl_env_typedefs.svh" + `include "src/fuse_ctrl_env_configuration.svh" + `include "src/fuse_ctrl_predictor.svh" + `include "src/fuse_ctrl_scoreboard.svh" + `include "src/fuse_ctrl_environment.svh" + `include "src/fuse_ctrl_env_sequence_base.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new environment level sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the environment package. Be sure to place + // the new sequence after any base sequence of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/environment_packages/fuse_ctrl_env_pkg/fuse_ctrl_env_pkg.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/environment_packages/fuse_ctrl_env_pkg/fuse_ctrl_env_pkg.vinfo new file mode 100644 index 0000000..f4f985f --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/environment_packages/fuse_ctrl_env_pkg/fuse_ctrl_env_pkg.vinfo @@ -0,0 +1,19 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_pkg.vinfo ++incdir+@vinfodir +fuse_ctrl_env_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/environment_packages/fuse_ctrl_env_pkg/fuse_ctrl_env_pkg_sve.F b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/environment_packages/fuse_ctrl_env_pkg/fuse_ctrl_env_pkg_sve.F new file mode 100644 index 0000000..b40213d --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/environment_packages/fuse_ctrl_env_pkg/fuse_ctrl_env_pkg_sve.F @@ -0,0 +1,12 @@ + +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + +// Sub-Environments + ++incdir+. +./fuse_ctrl_env_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/environment_packages/fuse_ctrl_env_pkg/src/fuse_ctrl_env_configuration.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/environment_packages/fuse_ctrl_env_pkg/src/fuse_ctrl_env_configuration.svh new file mode 100644 index 0000000..01b71d1 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/environment_packages/fuse_ctrl_env_pkg/src/fuse_ctrl_env_configuration.svh @@ -0,0 +1,270 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: THis is the configuration for the fuse_ctrl environment. +// it contains configuration classes for each agent. It also contains +// environment level configuration variables. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_env_configuration +extends uvmf_environment_configuration_base; + + `uvm_object_utils( fuse_ctrl_env_configuration ) + + +//Constraints for the configuration variables: + + + covergroup fuse_ctrl_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + // pragma uvmf custom covergroup end + endgroup + + + typedef fuse_ctrl_rst_in_configuration fuse_ctrl_rst_in_agent_config_t; + rand fuse_ctrl_rst_in_agent_config_t fuse_ctrl_rst_in_agent_config; + + typedef fuse_ctrl_rst_out_configuration fuse_ctrl_rst_out_agent_config_t; + rand fuse_ctrl_rst_out_agent_config_t fuse_ctrl_rst_out_agent_config; + + typedef fuse_ctrl_core_axi_write_in_configuration fuse_ctrl_core_axi_write_in_if_agent_config_t; + rand fuse_ctrl_core_axi_write_in_if_agent_config_t fuse_ctrl_core_axi_write_in_if_agent_config; + + typedef fuse_ctrl_core_axi_write_out_configuration fuse_ctrl_core_axi_write_out_if_agent_config_t; + rand fuse_ctrl_core_axi_write_out_if_agent_config_t fuse_ctrl_core_axi_write_out_if_agent_config; + + typedef fuse_ctrl_prim_axi_write_in_configuration fuse_ctrl_prim_axi_write_in_if_agent_config_t; + rand fuse_ctrl_prim_axi_write_in_if_agent_config_t fuse_ctrl_prim_axi_write_in_if_agent_config; + + typedef fuse_ctrl_prim_axi_write_out_configuration fuse_ctrl_prim_axi_write_out_if_agent_config_t; + rand fuse_ctrl_prim_axi_write_out_if_agent_config_t fuse_ctrl_prim_axi_write_out_if_agent_config; + + typedef fuse_ctrl_core_axi_read_in_configuration fuse_ctrl_core_axi_read_in_if_agent_config_t; + rand fuse_ctrl_core_axi_read_in_if_agent_config_t fuse_ctrl_core_axi_read_in_if_agent_config; + + typedef fuse_ctrl_core_axi_read_out_configuration fuse_ctrl_core_axi_read_out_if_agent_config_t; + rand fuse_ctrl_core_axi_read_out_if_agent_config_t fuse_ctrl_core_axi_read_out_if_agent_config; + + typedef fuse_ctrl_prim_axi_read_in_configuration fuse_ctrl_prim_axi_read_in_if_agent_config_t; + rand fuse_ctrl_prim_axi_read_in_if_agent_config_t fuse_ctrl_prim_axi_read_in_if_agent_config; + + typedef fuse_ctrl_prim_axi_read_out_configuration fuse_ctrl_prim_axi_read_out_if_agent_config_t; + rand fuse_ctrl_prim_axi_read_out_if_agent_config_t fuse_ctrl_prim_axi_read_out_if_agent_config; + + typedef fuse_ctrl_secreg_axi_read_in_configuration fuse_ctrl_secreg_axi_read_in_if_agent_config_t; + rand fuse_ctrl_secreg_axi_read_in_if_agent_config_t fuse_ctrl_secreg_axi_read_in_if_agent_config; + + typedef fuse_ctrl_secreg_axi_read_out_configuration fuse_ctrl_secreg_axi_read_out_if_agent_config_t; + rand fuse_ctrl_secreg_axi_read_out_if_agent_config_t fuse_ctrl_secreg_axi_read_out_if_agent_config; + + typedef fuse_ctrl_lc_otp_in_configuration fuse_ctrl_lc_otp_in_if_agent_config_t; + rand fuse_ctrl_lc_otp_in_if_agent_config_t fuse_ctrl_lc_otp_in_if_agent_config; + + typedef fuse_ctrl_lc_otp_out_configuration fuse_ctrl_lc_otp_out_if_agent_config_t; + rand fuse_ctrl_lc_otp_out_if_agent_config_t fuse_ctrl_lc_otp_out_if_agent_config; + + typedef fuse_ctrl_in_configuration fuse_ctrl_in_if_agent_config_t; + rand fuse_ctrl_in_if_agent_config_t fuse_ctrl_in_if_agent_config; + + typedef fuse_ctrl_out_configuration fuse_ctrl_out_if_agent_config_t; + rand fuse_ctrl_out_if_agent_config_t fuse_ctrl_out_if_agent_config; + + + + + typedef uvmf_virtual_sequencer_base #(.CONFIG_T(fuse_ctrl_env_configuration)) fuse_ctrl_vsqr_t; + fuse_ctrl_vsqr_t vsqr; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// This function constructs the configuration object for each agent in the environment. +// + function new( string name = "" ); + super.new( name ); + + + fuse_ctrl_rst_in_agent_config = fuse_ctrl_rst_in_agent_config_t::type_id::create("fuse_ctrl_rst_in_agent_config"); + fuse_ctrl_rst_out_agent_config = fuse_ctrl_rst_out_agent_config_t::type_id::create("fuse_ctrl_rst_out_agent_config"); + fuse_ctrl_core_axi_write_in_if_agent_config = fuse_ctrl_core_axi_write_in_if_agent_config_t::type_id::create("fuse_ctrl_core_axi_write_in_if_agent_config"); + fuse_ctrl_core_axi_write_out_if_agent_config = fuse_ctrl_core_axi_write_out_if_agent_config_t::type_id::create("fuse_ctrl_core_axi_write_out_if_agent_config"); + fuse_ctrl_prim_axi_write_in_if_agent_config = fuse_ctrl_prim_axi_write_in_if_agent_config_t::type_id::create("fuse_ctrl_prim_axi_write_in_if_agent_config"); + fuse_ctrl_prim_axi_write_out_if_agent_config = fuse_ctrl_prim_axi_write_out_if_agent_config_t::type_id::create("fuse_ctrl_prim_axi_write_out_if_agent_config"); + fuse_ctrl_core_axi_read_in_if_agent_config = fuse_ctrl_core_axi_read_in_if_agent_config_t::type_id::create("fuse_ctrl_core_axi_read_in_if_agent_config"); + fuse_ctrl_core_axi_read_out_if_agent_config = fuse_ctrl_core_axi_read_out_if_agent_config_t::type_id::create("fuse_ctrl_core_axi_read_out_if_agent_config"); + fuse_ctrl_prim_axi_read_in_if_agent_config = fuse_ctrl_prim_axi_read_in_if_agent_config_t::type_id::create("fuse_ctrl_prim_axi_read_in_if_agent_config"); + fuse_ctrl_prim_axi_read_out_if_agent_config = fuse_ctrl_prim_axi_read_out_if_agent_config_t::type_id::create("fuse_ctrl_prim_axi_read_out_if_agent_config"); + fuse_ctrl_secreg_axi_read_in_if_agent_config = fuse_ctrl_secreg_axi_read_in_if_agent_config_t::type_id::create("fuse_ctrl_secreg_axi_read_in_if_agent_config"); + fuse_ctrl_secreg_axi_read_out_if_agent_config = fuse_ctrl_secreg_axi_read_out_if_agent_config_t::type_id::create("fuse_ctrl_secreg_axi_read_out_if_agent_config"); + fuse_ctrl_lc_otp_in_if_agent_config = fuse_ctrl_lc_otp_in_if_agent_config_t::type_id::create("fuse_ctrl_lc_otp_in_if_agent_config"); + fuse_ctrl_lc_otp_out_if_agent_config = fuse_ctrl_lc_otp_out_if_agent_config_t::type_id::create("fuse_ctrl_lc_otp_out_if_agent_config"); + fuse_ctrl_in_if_agent_config = fuse_ctrl_in_if_agent_config_t::type_id::create("fuse_ctrl_in_if_agent_config"); + fuse_ctrl_out_if_agent_config = fuse_ctrl_out_if_agent_config_t::type_id::create("fuse_ctrl_out_if_agent_config"); + + + fuse_ctrl_configuration_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that configuration variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + + // pragma uvmf custom new begin + // pragma uvmf custom new end + endfunction + +// **************************************************************************** +// FUNCTION : set_vsqr() +// This function is used to assign the vsqr handle. + virtual function void set_vsqr( fuse_ctrl_vsqr_t vsqr); + this.vsqr = vsqr; + endfunction : set_vsqr + +// **************************************************************************** +// FUNCTION: post_randomize() +// This function is automatically called after the randomize() function +// is executed. +// + function void post_randomize(); + super.post_randomize(); + // pragma uvmf custom post_randomize begin + // pragma uvmf custom post_randomize end + endfunction + +// **************************************************************************** +// FUNCTION: convert2string() +// This function converts all variables in this class to a single string for +// logfile reporting. This function concatenates the convert2string result for +// each agent configuration in this configuration class. +// + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + return { + + "\n", fuse_ctrl_rst_in_agent_config.convert2string, + "\n", fuse_ctrl_rst_out_agent_config.convert2string, + "\n", fuse_ctrl_core_axi_write_in_if_agent_config.convert2string, + "\n", fuse_ctrl_core_axi_write_out_if_agent_config.convert2string, + "\n", fuse_ctrl_prim_axi_write_in_if_agent_config.convert2string, + "\n", fuse_ctrl_prim_axi_write_out_if_agent_config.convert2string, + "\n", fuse_ctrl_core_axi_read_in_if_agent_config.convert2string, + "\n", fuse_ctrl_core_axi_read_out_if_agent_config.convert2string, + "\n", fuse_ctrl_prim_axi_read_in_if_agent_config.convert2string, + "\n", fuse_ctrl_prim_axi_read_out_if_agent_config.convert2string, + "\n", fuse_ctrl_secreg_axi_read_in_if_agent_config.convert2string, + "\n", fuse_ctrl_secreg_axi_read_out_if_agent_config.convert2string, + "\n", fuse_ctrl_lc_otp_in_if_agent_config.convert2string, + "\n", fuse_ctrl_lc_otp_out_if_agent_config.convert2string, + "\n", fuse_ctrl_in_if_agent_config.convert2string, + "\n", fuse_ctrl_out_if_agent_config.convert2string + + + }; + // pragma uvmf custom convert2string end + endfunction +// **************************************************************************** +// FUNCTION: initialize(); +// This function configures each interface agents configuration class. The +// sim level determines the active/passive state of the agent. The environment_path +// identifies the hierarchy down to and including the instantiation name of the +// environment for this configuration class. Each instance of the environment +// has its own configuration class. The string interface names are used by +// the agent configurations to identify the virtual interface handle to pull from +// the uvm_config_db. +// + function void initialize(uvmf_sim_level_t sim_level, + string environment_path, + string interface_names[], + uvm_reg_block register_model = null, + uvmf_active_passive_t interface_activity[] = {} + ); + + super.initialize(sim_level, environment_path, interface_names, register_model, interface_activity); + + + + // Interface initialization for local agents + fuse_ctrl_rst_in_agent_config.initialize( interface_activity[0], {environment_path,".fuse_ctrl_rst_in_agent"}, interface_names[0]); + fuse_ctrl_rst_in_agent_config.initiator_responder = INITIATOR; + // fuse_ctrl_rst_in_agent_config.has_coverage = 1; + fuse_ctrl_rst_out_agent_config.initialize( interface_activity[1], {environment_path,".fuse_ctrl_rst_out_agent"}, interface_names[1]); + fuse_ctrl_rst_out_agent_config.initiator_responder = RESPONDER; + // fuse_ctrl_rst_out_agent_config.has_coverage = 1; + fuse_ctrl_core_axi_write_in_if_agent_config.initialize( interface_activity[2], {environment_path,".fuse_ctrl_core_axi_write_in_if_agent"}, interface_names[2]); + fuse_ctrl_core_axi_write_in_if_agent_config.initiator_responder = INITIATOR; + // fuse_ctrl_core_axi_write_in_if_agent_config.has_coverage = 1; + fuse_ctrl_core_axi_write_out_if_agent_config.initialize( interface_activity[3], {environment_path,".fuse_ctrl_core_axi_write_out_if_agent"}, interface_names[3]); + fuse_ctrl_core_axi_write_out_if_agent_config.initiator_responder = RESPONDER; + // fuse_ctrl_core_axi_write_out_if_agent_config.has_coverage = 1; + fuse_ctrl_prim_axi_write_in_if_agent_config.initialize( interface_activity[4], {environment_path,".fuse_ctrl_prim_axi_write_in_if_agent"}, interface_names[4]); + fuse_ctrl_prim_axi_write_in_if_agent_config.initiator_responder = INITIATOR; + // fuse_ctrl_prim_axi_write_in_if_agent_config.has_coverage = 1; + fuse_ctrl_prim_axi_write_out_if_agent_config.initialize( interface_activity[5], {environment_path,".fuse_ctrl_prim_axi_write_out_if_agent"}, interface_names[5]); + fuse_ctrl_prim_axi_write_out_if_agent_config.initiator_responder = RESPONDER; + // fuse_ctrl_prim_axi_write_out_if_agent_config.has_coverage = 1; + fuse_ctrl_core_axi_read_in_if_agent_config.initialize( interface_activity[6], {environment_path,".fuse_ctrl_core_axi_read_in_if_agent"}, interface_names[6]); + fuse_ctrl_core_axi_read_in_if_agent_config.initiator_responder = INITIATOR; + // fuse_ctrl_core_axi_read_in_if_agent_config.has_coverage = 1; + fuse_ctrl_core_axi_read_out_if_agent_config.initialize( interface_activity[7], {environment_path,".fuse_ctrl_core_axi_read_out_if_agent"}, interface_names[7]); + fuse_ctrl_core_axi_read_out_if_agent_config.initiator_responder = RESPONDER; + // fuse_ctrl_core_axi_read_out_if_agent_config.has_coverage = 1; + fuse_ctrl_prim_axi_read_in_if_agent_config.initialize( interface_activity[8], {environment_path,".fuse_ctrl_prim_axi_read_in_if_agent"}, interface_names[8]); + fuse_ctrl_prim_axi_read_in_if_agent_config.initiator_responder = INITIATOR; + // fuse_ctrl_prim_axi_read_in_if_agent_config.has_coverage = 1; + fuse_ctrl_prim_axi_read_out_if_agent_config.initialize( interface_activity[9], {environment_path,".fuse_ctrl_prim_axi_read_out_if_agent"}, interface_names[9]); + fuse_ctrl_prim_axi_read_out_if_agent_config.initiator_responder = RESPONDER; + // fuse_ctrl_prim_axi_read_out_if_agent_config.has_coverage = 1; + fuse_ctrl_secreg_axi_read_in_if_agent_config.initialize( interface_activity[10], {environment_path,".fuse_ctrl_secreg_axi_read_in_if_agent"}, interface_names[10]); + fuse_ctrl_secreg_axi_read_in_if_agent_config.initiator_responder = INITIATOR; + // fuse_ctrl_secreg_axi_read_in_if_agent_config.has_coverage = 1; + fuse_ctrl_secreg_axi_read_out_if_agent_config.initialize( interface_activity[11], {environment_path,".fuse_ctrl_secreg_axi_read_out_if_agent"}, interface_names[11]); + fuse_ctrl_secreg_axi_read_out_if_agent_config.initiator_responder = RESPONDER; + // fuse_ctrl_secreg_axi_read_out_if_agent_config.has_coverage = 1; + fuse_ctrl_lc_otp_in_if_agent_config.initialize( interface_activity[12], {environment_path,".fuse_ctrl_lc_otp_in_if_agent"}, interface_names[12]); + fuse_ctrl_lc_otp_in_if_agent_config.initiator_responder = INITIATOR; + // fuse_ctrl_lc_otp_in_if_agent_config.has_coverage = 1; + fuse_ctrl_lc_otp_out_if_agent_config.initialize( interface_activity[13], {environment_path,".fuse_ctrl_lc_otp_out_if_agent"}, interface_names[13]); + fuse_ctrl_lc_otp_out_if_agent_config.initiator_responder = RESPONDER; + // fuse_ctrl_lc_otp_out_if_agent_config.has_coverage = 1; + fuse_ctrl_in_if_agent_config.initialize( interface_activity[14], {environment_path,".fuse_ctrl_in_if_agent"}, interface_names[14]); + fuse_ctrl_in_if_agent_config.initiator_responder = INITIATOR; + // fuse_ctrl_in_if_agent_config.has_coverage = 1; + fuse_ctrl_out_if_agent_config.initialize( interface_activity[15], {environment_path,".fuse_ctrl_out_if_agent"}, interface_names[15]); + fuse_ctrl_out_if_agent_config.initiator_responder = RESPONDER; + // fuse_ctrl_out_if_agent_config.has_coverage = 1; + + + + + + // pragma uvmf custom initialize begin + // pragma uvmf custom initialize end + + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/environment_packages/fuse_ctrl_env_pkg/src/fuse_ctrl_env_sequence_base.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/environment_packages/fuse_ctrl_env_pkg/src/fuse_ctrl_env_sequence_base.svh new file mode 100644 index 0000000..ac7965f --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/environment_packages/fuse_ctrl_env_pkg/src/fuse_ctrl_env_sequence_base.svh @@ -0,0 +1,146 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains environment level sequences that will +// be reused from block to top level simulations. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_env_sequence_base #( + type CONFIG_T + ) extends uvmf_virtual_sequence_base #(.CONFIG_T(CONFIG_T)); + + + `uvm_object_param_utils( fuse_ctrl_env_sequence_base #( + CONFIG_T + ) ); + + +// This fuse_ctrl_env_sequence_base contains a handle to a fuse_ctrl_env_configuration object +// named configuration. This configuration variable contains a handle to each +// sequencer within each agent within this environment and any sub-environments. +// The configuration object handle is automatically assigned in the pre_body in the +// base class of this sequence. The configuration handle is retrieved from the +// virtual sequencer that this sequence is started on. +// Available sequencer handles within the environment configuration: + + // Initiator agent sequencers in fuse_ctrl_environment: + // configuration.fuse_ctrl_rst_in_agent_config.sequencer + // configuration.fuse_ctrl_core_axi_write_in_if_agent_config.sequencer + // configuration.fuse_ctrl_prim_axi_write_in_if_agent_config.sequencer + // configuration.fuse_ctrl_core_axi_read_in_if_agent_config.sequencer + // configuration.fuse_ctrl_prim_axi_read_in_if_agent_config.sequencer + // configuration.fuse_ctrl_secreg_axi_read_in_if_agent_config.sequencer + // configuration.fuse_ctrl_lc_otp_in_if_agent_config.sequencer + // configuration.fuse_ctrl_in_if_agent_config.sequencer + + // Responder agent sequencers in fuse_ctrl_environment: + // configuration.fuse_ctrl_rst_out_agent_config.sequencer + // configuration.fuse_ctrl_core_axi_write_out_if_agent_config.sequencer + // configuration.fuse_ctrl_prim_axi_write_out_if_agent_config.sequencer + // configuration.fuse_ctrl_core_axi_read_out_if_agent_config.sequencer + // configuration.fuse_ctrl_prim_axi_read_out_if_agent_config.sequencer + // configuration.fuse_ctrl_secreg_axi_read_out_if_agent_config.sequencer + // configuration.fuse_ctrl_lc_otp_out_if_agent_config.sequencer + // configuration.fuse_ctrl_out_if_agent_config.sequencer + + + typedef fuse_ctrl_rst_in_random_sequence fuse_ctrl_rst_in_agent_random_sequence_t; + fuse_ctrl_rst_in_agent_random_sequence_t fuse_ctrl_rst_in_agent_rand_seq; + + + typedef fuse_ctrl_core_axi_write_in_random_sequence fuse_ctrl_core_axi_write_in_if_agent_random_sequence_t; + fuse_ctrl_core_axi_write_in_if_agent_random_sequence_t fuse_ctrl_core_axi_write_in_if_agent_rand_seq; + + + typedef fuse_ctrl_prim_axi_write_in_random_sequence fuse_ctrl_prim_axi_write_in_if_agent_random_sequence_t; + fuse_ctrl_prim_axi_write_in_if_agent_random_sequence_t fuse_ctrl_prim_axi_write_in_if_agent_rand_seq; + + + typedef fuse_ctrl_core_axi_read_in_random_sequence fuse_ctrl_core_axi_read_in_if_agent_random_sequence_t; + fuse_ctrl_core_axi_read_in_if_agent_random_sequence_t fuse_ctrl_core_axi_read_in_if_agent_rand_seq; + + + typedef fuse_ctrl_prim_axi_read_in_random_sequence fuse_ctrl_prim_axi_read_in_if_agent_random_sequence_t; + fuse_ctrl_prim_axi_read_in_if_agent_random_sequence_t fuse_ctrl_prim_axi_read_in_if_agent_rand_seq; + + + typedef fuse_ctrl_secreg_axi_read_in_random_sequence fuse_ctrl_secreg_axi_read_in_if_agent_random_sequence_t; + fuse_ctrl_secreg_axi_read_in_if_agent_random_sequence_t fuse_ctrl_secreg_axi_read_in_if_agent_rand_seq; + + + typedef fuse_ctrl_lc_otp_in_random_sequence fuse_ctrl_lc_otp_in_if_agent_random_sequence_t; + fuse_ctrl_lc_otp_in_if_agent_random_sequence_t fuse_ctrl_lc_otp_in_if_agent_rand_seq; + + + typedef fuse_ctrl_in_random_sequence fuse_ctrl_in_if_agent_random_sequence_t; + fuse_ctrl_in_if_agent_random_sequence_t fuse_ctrl_in_if_agent_rand_seq; + + + + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "" ); + super.new(name); + fuse_ctrl_rst_in_agent_rand_seq = fuse_ctrl_rst_in_agent_random_sequence_t::type_id::create("fuse_ctrl_rst_in_agent_rand_seq"); + fuse_ctrl_core_axi_write_in_if_agent_rand_seq = fuse_ctrl_core_axi_write_in_if_agent_random_sequence_t::type_id::create("fuse_ctrl_core_axi_write_in_if_agent_rand_seq"); + fuse_ctrl_prim_axi_write_in_if_agent_rand_seq = fuse_ctrl_prim_axi_write_in_if_agent_random_sequence_t::type_id::create("fuse_ctrl_prim_axi_write_in_if_agent_rand_seq"); + fuse_ctrl_core_axi_read_in_if_agent_rand_seq = fuse_ctrl_core_axi_read_in_if_agent_random_sequence_t::type_id::create("fuse_ctrl_core_axi_read_in_if_agent_rand_seq"); + fuse_ctrl_prim_axi_read_in_if_agent_rand_seq = fuse_ctrl_prim_axi_read_in_if_agent_random_sequence_t::type_id::create("fuse_ctrl_prim_axi_read_in_if_agent_rand_seq"); + fuse_ctrl_secreg_axi_read_in_if_agent_rand_seq = fuse_ctrl_secreg_axi_read_in_if_agent_random_sequence_t::type_id::create("fuse_ctrl_secreg_axi_read_in_if_agent_rand_seq"); + fuse_ctrl_lc_otp_in_if_agent_rand_seq = fuse_ctrl_lc_otp_in_if_agent_random_sequence_t::type_id::create("fuse_ctrl_lc_otp_in_if_agent_rand_seq"); + fuse_ctrl_in_if_agent_rand_seq = fuse_ctrl_in_if_agent_random_sequence_t::type_id::create("fuse_ctrl_in_if_agent_rand_seq"); + + + endfunction + + virtual task body(); + + if ( configuration.fuse_ctrl_rst_in_agent_config.sequencer != null ) + repeat (25) fuse_ctrl_rst_in_agent_rand_seq.start(configuration.fuse_ctrl_rst_in_agent_config.sequencer); + if ( configuration.fuse_ctrl_core_axi_write_in_if_agent_config.sequencer != null ) + repeat (25) fuse_ctrl_core_axi_write_in_if_agent_rand_seq.start(configuration.fuse_ctrl_core_axi_write_in_if_agent_config.sequencer); + if ( configuration.fuse_ctrl_prim_axi_write_in_if_agent_config.sequencer != null ) + repeat (25) fuse_ctrl_prim_axi_write_in_if_agent_rand_seq.start(configuration.fuse_ctrl_prim_axi_write_in_if_agent_config.sequencer); + if ( configuration.fuse_ctrl_core_axi_read_in_if_agent_config.sequencer != null ) + repeat (25) fuse_ctrl_core_axi_read_in_if_agent_rand_seq.start(configuration.fuse_ctrl_core_axi_read_in_if_agent_config.sequencer); + if ( configuration.fuse_ctrl_prim_axi_read_in_if_agent_config.sequencer != null ) + repeat (25) fuse_ctrl_prim_axi_read_in_if_agent_rand_seq.start(configuration.fuse_ctrl_prim_axi_read_in_if_agent_config.sequencer); + if ( configuration.fuse_ctrl_secreg_axi_read_in_if_agent_config.sequencer != null ) + repeat (25) fuse_ctrl_secreg_axi_read_in_if_agent_rand_seq.start(configuration.fuse_ctrl_secreg_axi_read_in_if_agent_config.sequencer); + if ( configuration.fuse_ctrl_lc_otp_in_if_agent_config.sequencer != null ) + repeat (25) fuse_ctrl_lc_otp_in_if_agent_rand_seq.start(configuration.fuse_ctrl_lc_otp_in_if_agent_config.sequencer); + if ( configuration.fuse_ctrl_in_if_agent_config.sequencer != null ) + repeat (25) fuse_ctrl_in_if_agent_rand_seq.start(configuration.fuse_ctrl_in_if_agent_config.sequencer); + + + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/environment_packages/fuse_ctrl_env_pkg/src/fuse_ctrl_env_typedefs.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/environment_packages/fuse_ctrl_env_pkg/src/fuse_ctrl_env_typedefs.svh new file mode 100644 index 0000000..79d1b10 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/environment_packages/fuse_ctrl_env_pkg/src/fuse_ctrl_env_typedefs.svh @@ -0,0 +1,34 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the environment package. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + + // pragma uvmf custom additional begin + // pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/environment_packages/fuse_ctrl_env_pkg/src/fuse_ctrl_environment.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/environment_packages/fuse_ctrl_env_pkg/src/fuse_ctrl_environment.svh new file mode 100644 index 0000000..660ac5d --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/environment_packages/fuse_ctrl_env_pkg/src/fuse_ctrl_environment.svh @@ -0,0 +1,217 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This environment contains all agents, predictors and +// scoreboards required for the block level design. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class fuse_ctrl_environment extends uvmf_environment_base #( + .CONFIG_T( fuse_ctrl_env_configuration + )); + `uvm_component_utils( fuse_ctrl_environment ) + + + + + + typedef fuse_ctrl_rst_in_agent fuse_ctrl_rst_in_agent_t; + fuse_ctrl_rst_in_agent_t fuse_ctrl_rst_in_agent; + + typedef fuse_ctrl_rst_out_agent fuse_ctrl_rst_out_agent_t; + fuse_ctrl_rst_out_agent_t fuse_ctrl_rst_out_agent; + + typedef fuse_ctrl_core_axi_write_in_agent fuse_ctrl_core_axi_write_in_if_agent_t; + fuse_ctrl_core_axi_write_in_if_agent_t fuse_ctrl_core_axi_write_in_if_agent; + + typedef fuse_ctrl_core_axi_write_out_agent fuse_ctrl_core_axi_write_out_if_agent_t; + fuse_ctrl_core_axi_write_out_if_agent_t fuse_ctrl_core_axi_write_out_if_agent; + + typedef fuse_ctrl_prim_axi_write_in_agent fuse_ctrl_prim_axi_write_in_if_agent_t; + fuse_ctrl_prim_axi_write_in_if_agent_t fuse_ctrl_prim_axi_write_in_if_agent; + + typedef fuse_ctrl_prim_axi_write_out_agent fuse_ctrl_prim_axi_write_out_if_agent_t; + fuse_ctrl_prim_axi_write_out_if_agent_t fuse_ctrl_prim_axi_write_out_if_agent; + + typedef fuse_ctrl_core_axi_read_in_agent fuse_ctrl_core_axi_read_in_if_agent_t; + fuse_ctrl_core_axi_read_in_if_agent_t fuse_ctrl_core_axi_read_in_if_agent; + + typedef fuse_ctrl_core_axi_read_out_agent fuse_ctrl_core_axi_read_out_if_agent_t; + fuse_ctrl_core_axi_read_out_if_agent_t fuse_ctrl_core_axi_read_out_if_agent; + + typedef fuse_ctrl_prim_axi_read_in_agent fuse_ctrl_prim_axi_read_in_if_agent_t; + fuse_ctrl_prim_axi_read_in_if_agent_t fuse_ctrl_prim_axi_read_in_if_agent; + + typedef fuse_ctrl_prim_axi_read_out_agent fuse_ctrl_prim_axi_read_out_if_agent_t; + fuse_ctrl_prim_axi_read_out_if_agent_t fuse_ctrl_prim_axi_read_out_if_agent; + + typedef fuse_ctrl_secreg_axi_read_in_agent fuse_ctrl_secreg_axi_read_in_if_agent_t; + fuse_ctrl_secreg_axi_read_in_if_agent_t fuse_ctrl_secreg_axi_read_in_if_agent; + + typedef fuse_ctrl_secreg_axi_read_out_agent fuse_ctrl_secreg_axi_read_out_if_agent_t; + fuse_ctrl_secreg_axi_read_out_if_agent_t fuse_ctrl_secreg_axi_read_out_if_agent; + + typedef fuse_ctrl_lc_otp_in_agent fuse_ctrl_lc_otp_in_if_agent_t; + fuse_ctrl_lc_otp_in_if_agent_t fuse_ctrl_lc_otp_in_if_agent; + + typedef fuse_ctrl_lc_otp_out_agent fuse_ctrl_lc_otp_out_if_agent_t; + fuse_ctrl_lc_otp_out_if_agent_t fuse_ctrl_lc_otp_out_if_agent; + + typedef fuse_ctrl_in_agent fuse_ctrl_in_if_agent_t; + fuse_ctrl_in_if_agent_t fuse_ctrl_in_if_agent; + + typedef fuse_ctrl_out_agent fuse_ctrl_out_if_agent_t; + fuse_ctrl_out_if_agent_t fuse_ctrl_out_if_agent; + + + + + typedef fuse_ctrl_predictor #( + .CONFIG_T(CONFIG_T) + ) fuse_ctrl_pred_t; + fuse_ctrl_pred_t fuse_ctrl_pred; + typedef fuse_ctrl_scoreboard #( + .CONFIG_T(CONFIG_T) + ) fuse_ctrl_sb_t; + fuse_ctrl_sb_t fuse_ctrl_sb; + + + + + typedef uvmf_virtual_sequencer_base #(.CONFIG_T(fuse_ctrl_env_configuration)) fuse_ctrl_vsqr_t; + fuse_ctrl_vsqr_t vsqr; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// FUNCTION: build_phase() +// This function builds all components within this environment. +// + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + fuse_ctrl_rst_in_agent = fuse_ctrl_rst_in_agent_t::type_id::create("fuse_ctrl_rst_in_agent",this); + fuse_ctrl_rst_in_agent.set_config(configuration.fuse_ctrl_rst_in_agent_config); + fuse_ctrl_rst_out_agent = fuse_ctrl_rst_out_agent_t::type_id::create("fuse_ctrl_rst_out_agent",this); + fuse_ctrl_rst_out_agent.set_config(configuration.fuse_ctrl_rst_out_agent_config); + fuse_ctrl_core_axi_write_in_if_agent = fuse_ctrl_core_axi_write_in_if_agent_t::type_id::create("fuse_ctrl_core_axi_write_in_if_agent",this); + fuse_ctrl_core_axi_write_in_if_agent.set_config(configuration.fuse_ctrl_core_axi_write_in_if_agent_config); + fuse_ctrl_core_axi_write_out_if_agent = fuse_ctrl_core_axi_write_out_if_agent_t::type_id::create("fuse_ctrl_core_axi_write_out_if_agent",this); + fuse_ctrl_core_axi_write_out_if_agent.set_config(configuration.fuse_ctrl_core_axi_write_out_if_agent_config); + fuse_ctrl_prim_axi_write_in_if_agent = fuse_ctrl_prim_axi_write_in_if_agent_t::type_id::create("fuse_ctrl_prim_axi_write_in_if_agent",this); + fuse_ctrl_prim_axi_write_in_if_agent.set_config(configuration.fuse_ctrl_prim_axi_write_in_if_agent_config); + fuse_ctrl_prim_axi_write_out_if_agent = fuse_ctrl_prim_axi_write_out_if_agent_t::type_id::create("fuse_ctrl_prim_axi_write_out_if_agent",this); + fuse_ctrl_prim_axi_write_out_if_agent.set_config(configuration.fuse_ctrl_prim_axi_write_out_if_agent_config); + fuse_ctrl_core_axi_read_in_if_agent = fuse_ctrl_core_axi_read_in_if_agent_t::type_id::create("fuse_ctrl_core_axi_read_in_if_agent",this); + fuse_ctrl_core_axi_read_in_if_agent.set_config(configuration.fuse_ctrl_core_axi_read_in_if_agent_config); + fuse_ctrl_core_axi_read_out_if_agent = fuse_ctrl_core_axi_read_out_if_agent_t::type_id::create("fuse_ctrl_core_axi_read_out_if_agent",this); + fuse_ctrl_core_axi_read_out_if_agent.set_config(configuration.fuse_ctrl_core_axi_read_out_if_agent_config); + fuse_ctrl_prim_axi_read_in_if_agent = fuse_ctrl_prim_axi_read_in_if_agent_t::type_id::create("fuse_ctrl_prim_axi_read_in_if_agent",this); + fuse_ctrl_prim_axi_read_in_if_agent.set_config(configuration.fuse_ctrl_prim_axi_read_in_if_agent_config); + fuse_ctrl_prim_axi_read_out_if_agent = fuse_ctrl_prim_axi_read_out_if_agent_t::type_id::create("fuse_ctrl_prim_axi_read_out_if_agent",this); + fuse_ctrl_prim_axi_read_out_if_agent.set_config(configuration.fuse_ctrl_prim_axi_read_out_if_agent_config); + fuse_ctrl_secreg_axi_read_in_if_agent = fuse_ctrl_secreg_axi_read_in_if_agent_t::type_id::create("fuse_ctrl_secreg_axi_read_in_if_agent",this); + fuse_ctrl_secreg_axi_read_in_if_agent.set_config(configuration.fuse_ctrl_secreg_axi_read_in_if_agent_config); + fuse_ctrl_secreg_axi_read_out_if_agent = fuse_ctrl_secreg_axi_read_out_if_agent_t::type_id::create("fuse_ctrl_secreg_axi_read_out_if_agent",this); + fuse_ctrl_secreg_axi_read_out_if_agent.set_config(configuration.fuse_ctrl_secreg_axi_read_out_if_agent_config); + fuse_ctrl_lc_otp_in_if_agent = fuse_ctrl_lc_otp_in_if_agent_t::type_id::create("fuse_ctrl_lc_otp_in_if_agent",this); + fuse_ctrl_lc_otp_in_if_agent.set_config(configuration.fuse_ctrl_lc_otp_in_if_agent_config); + fuse_ctrl_lc_otp_out_if_agent = fuse_ctrl_lc_otp_out_if_agent_t::type_id::create("fuse_ctrl_lc_otp_out_if_agent",this); + fuse_ctrl_lc_otp_out_if_agent.set_config(configuration.fuse_ctrl_lc_otp_out_if_agent_config); + fuse_ctrl_in_if_agent = fuse_ctrl_in_if_agent_t::type_id::create("fuse_ctrl_in_if_agent",this); + fuse_ctrl_in_if_agent.set_config(configuration.fuse_ctrl_in_if_agent_config); + fuse_ctrl_out_if_agent = fuse_ctrl_out_if_agent_t::type_id::create("fuse_ctrl_out_if_agent",this); + fuse_ctrl_out_if_agent.set_config(configuration.fuse_ctrl_out_if_agent_config); + fuse_ctrl_pred = fuse_ctrl_pred_t::type_id::create("fuse_ctrl_pred",this); + fuse_ctrl_pred.configuration = configuration; + fuse_ctrl_sb = fuse_ctrl_sb_t::type_id::create("fuse_ctrl_sb",this); + fuse_ctrl_sb.configuration = configuration; + + vsqr = fuse_ctrl_vsqr_t::type_id::create("vsqr", this); + vsqr.set_config(configuration); + configuration.set_vsqr(vsqr); + + // pragma uvmf custom build_phase begin + // pragma uvmf custom build_phase end + endfunction + +// **************************************************************************** +// FUNCTION: connect_phase() +// This function makes all connections within this environment. Connections +// typically inclue agent to predictor, predictor to scoreboard and scoreboard +// to agent. +// + virtual function void connect_phase(uvm_phase phase); +// pragma uvmf custom connect_phase_pre_super begin +// pragma uvmf custom connect_phase_pre_super end + super.connect_phase(phase); + fuse_ctrl_rst_in_agent.monitored_ap.connect(fuse_ctrl_pred.fuse_ctrl_rst_in_agent_ae); + fuse_ctrl_core_axi_write_in_if_agent.monitored_ap.connect(fuse_ctrl_pred.fuse_ctrl_core_axi_write_in_agent_ae); + fuse_ctrl_core_axi_write_out_if_agent.monitored_ap.connect(fuse_ctrl_sb.fuse_ctrl_core_axi_write_in_agent_ae); + fuse_ctrl_core_axi_read_in_if_agent.monitored_ap.connect(fuse_ctrl_pred.fuse_ctrl_core_axi_read_in_agent_ae); + fuse_ctrl_core_axi_read_out_if_agent.monitored_ap.connect(fuse_ctrl_sb.fuse_ctrl_core_axi_read_in_agent_ae); + fuse_ctrl_prim_axi_write_in_if_agent.monitored_ap.connect(fuse_ctrl_pred.fuse_ctrl_prim_axi_write_in_agent_ae); + fuse_ctrl_prim_axi_write_out_if_agent.monitored_ap.connect(fuse_ctrl_sb.fuse_ctrl_prim_axi_write_in_agent_ae); + fuse_ctrl_prim_axi_read_in_if_agent.monitored_ap.connect(fuse_ctrl_pred.fuse_ctrl_prim_axi_read_in_agent_ae); + fuse_ctrl_prim_axi_read_out_if_agent.monitored_ap.connect(fuse_ctrl_sb.fuse_ctrl_prim_axi_read_in_agent_ae); + fuse_ctrl_secreg_axi_read_in_if_agent.monitored_ap.connect(fuse_ctrl_pred.fuse_ctrl_secreg_axi_read_in_agent_ae); + fuse_ctrl_secreg_axi_read_out_if_agent.monitored_ap.connect(fuse_ctrl_sb.fuse_ctrl_secreg_axi_read_in_agent_ae); + fuse_ctrl_lc_otp_in_if_agent.monitored_ap.connect(fuse_ctrl_pred.fuse_ctrl_lc_otp_in_agent_ae); + fuse_ctrl_lc_otp_out_if_agent.monitored_ap.connect(fuse_ctrl_sb.fuse_ctrl_lc_otp_in_agent_ae); + fuse_ctrl_in_if_agent.monitored_ap.connect(fuse_ctrl_pred.fuse_ctrl_in_agent_ae); + fuse_ctrl_out_if_agent.monitored_ap.connect(fuse_ctrl_sb.fuse_ctrl_in_agent_ae); + // pragma uvmf custom reg_model_connect_phase begin + // pragma uvmf custom reg_model_connect_phase end + endfunction + +// **************************************************************************** +// FUNCTION: end_of_simulation_phase() +// This function is executed just prior to executing run_phase. This function +// was added to the environment to sample environment configuration settings +// just before the simulation exits time 0. The configuration structure is +// randomized in the build phase before the environment structure is constructed. +// Configuration variables can be customized after randomization in the build_phase +// of the extended test. +// If a sequence modifies values in the configuration structure then the sequence is +// responsible for sampling the covergroup in the configuration if required. +// + virtual function void start_of_simulation_phase(uvm_phase phase); + configuration.fuse_ctrl_configuration_cg.sample(); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/environment_packages/fuse_ctrl_env_pkg/src/fuse_ctrl_predictor.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/environment_packages/fuse_ctrl_env_pkg/src/fuse_ctrl_predictor.svh new file mode 100644 index 0000000..220286a --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/environment_packages/fuse_ctrl_env_pkg/src/fuse_ctrl_predictor.svh @@ -0,0 +1,807 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// +// DESCRIPTION: This analysis component contains analysis_exports for receiving +// data and analysis_ports for sending data. +// +// This analysis component has the following analysis_exports that receive the +// listed transaction type. +// +// fuse_ctrl_lc_otp_in_agent_ae receives transactions of type fuse_ctrl_lc_otp_in_transaction +// fuse_ctrl_rst_in_agent_ae receives transactions of type fuse_ctrl_rst_in_transaction +// fuse_ctrl_core_axi_write_in_agent_ae receives transactions of type fuse_ctrl_core_axi_write_in_transaction +// fuse_ctrl_secreg_axi_read_in_agent_ae receives transactions of type fuse_ctrl_secreg_axi_read_in_transaction +// fuse_ctrl_prim_axi_write_in_agent_ae receives transactions of type fuse_ctrl_prim_axi_write_in_transaction +// fuse_ctrl_in_agent_ae receives transactions of type fuse_ctrl_in_transaction +// fuse_ctrl_core_axi_read_in_agent_ae receives transactions of type fuse_ctrl_core_axi_read_in_transaction +// fuse_ctrl_prim_axi_read_in_agent_ae receives transactions of type fuse_ctrl_prim_axi_read_in_transaction +// +// This analysis component has the following analysis_ports that can broadcast +// the listed transaction type. +// +// fuse_ctrl_prim_axi_write_in_agent_ap broadcasts transactions of type fuse_ctrl_prim_axi_write_in_transaction +// fuse_ctrl_core_axi_read_in_agent_ap broadcasts transactions of type fuse_ctrl_core_axi_read_in_transaction +// fuse_ctrl_prim_axi_read_in_agent_ap broadcasts transactions of type fuse_ctrl_prim_axi_read_in_transaction +// fuse_ctrl_in_agent_ap broadcasts transactions of type fuse_ctrl_in_transaction +// fuse_ctrl_rst_in_agent_ap broadcasts transactions of type fuse_ctrl_rst_in_transaction +// fuse_ctrl_secreg_axi_read_in_agent_ap broadcasts transactions of type fuse_ctrl_secreg_axi_read_in_transaction +// fuse_ctrl_core_axi_write_in_agent_ap broadcasts transactions of type fuse_ctrl_core_axi_write_in_transaction +// fuse_ctrl_lc_otp_in_agent_ap broadcasts transactions of type fuse_ctrl_lc_otp_in_transaction +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class fuse_ctrl_predictor #( + type CONFIG_T, + type BASE_T = uvm_component + ) extends BASE_T; + + // Factory registration of this class + `uvm_component_param_utils( fuse_ctrl_predictor #( + CONFIG_T, + BASE_T + )) + + + // Instantiate a handle to the configuration of the environment in which this component resides + CONFIG_T configuration; + + + // Instantiate the analysis exports + uvm_analysis_imp_fuse_ctrl_lc_otp_in_agent_ae #(fuse_ctrl_lc_otp_in_transaction, fuse_ctrl_predictor #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + )) fuse_ctrl_lc_otp_in_agent_ae; + uvm_analysis_imp_fuse_ctrl_rst_in_agent_ae #(fuse_ctrl_rst_in_transaction, fuse_ctrl_predictor #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + )) fuse_ctrl_rst_in_agent_ae; + uvm_analysis_imp_fuse_ctrl_core_axi_write_in_agent_ae #(fuse_ctrl_core_axi_write_in_transaction, fuse_ctrl_predictor #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + )) fuse_ctrl_core_axi_write_in_agent_ae; + uvm_analysis_imp_fuse_ctrl_secreg_axi_read_in_agent_ae #(fuse_ctrl_secreg_axi_read_in_transaction, fuse_ctrl_predictor #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + )) fuse_ctrl_secreg_axi_read_in_agent_ae; + uvm_analysis_imp_fuse_ctrl_prim_axi_write_in_agent_ae #(fuse_ctrl_prim_axi_write_in_transaction, fuse_ctrl_predictor #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + )) fuse_ctrl_prim_axi_write_in_agent_ae; + uvm_analysis_imp_fuse_ctrl_in_agent_ae #(fuse_ctrl_in_transaction, fuse_ctrl_predictor #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + )) fuse_ctrl_in_agent_ae; + uvm_analysis_imp_fuse_ctrl_core_axi_read_in_agent_ae #(fuse_ctrl_core_axi_read_in_transaction, fuse_ctrl_predictor #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + )) fuse_ctrl_core_axi_read_in_agent_ae; + uvm_analysis_imp_fuse_ctrl_prim_axi_read_in_agent_ae #(fuse_ctrl_prim_axi_read_in_transaction, fuse_ctrl_predictor #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + )) fuse_ctrl_prim_axi_read_in_agent_ae; + + + // Instantiate the analysis ports + uvm_analysis_port #(fuse_ctrl_prim_axi_write_in_transaction) fuse_ctrl_prim_axi_write_in_agent_ap; + uvm_analysis_port #(fuse_ctrl_core_axi_read_in_transaction) fuse_ctrl_core_axi_read_in_agent_ap; + uvm_analysis_port #(fuse_ctrl_prim_axi_read_in_transaction) fuse_ctrl_prim_axi_read_in_agent_ap; + uvm_analysis_port #(fuse_ctrl_in_transaction) fuse_ctrl_in_agent_ap; + uvm_analysis_port #(fuse_ctrl_rst_in_transaction) fuse_ctrl_rst_in_agent_ap; + uvm_analysis_port #(fuse_ctrl_secreg_axi_read_in_transaction) fuse_ctrl_secreg_axi_read_in_agent_ap; + uvm_analysis_port #(fuse_ctrl_core_axi_write_in_transaction) fuse_ctrl_core_axi_write_in_agent_ap; + uvm_analysis_port #(fuse_ctrl_lc_otp_in_transaction) fuse_ctrl_lc_otp_in_agent_ap; + + + // Transaction variable for predicted values to be sent out fuse_ctrl_prim_axi_write_in_agent_ap + // Once a transaction is sent through an analysis_port, another transaction should + // be constructed for the next predicted transaction. + typedef fuse_ctrl_prim_axi_write_in_transaction fuse_ctrl_prim_axi_write_in_agent_ap_output_transaction_t; + fuse_ctrl_prim_axi_write_in_agent_ap_output_transaction_t fuse_ctrl_prim_axi_write_in_agent_ap_output_transaction; + // Code for sending output transaction out through fuse_ctrl_prim_axi_write_in_agent_ap + // fuse_ctrl_prim_axi_write_in_agent_ap.write(fuse_ctrl_prim_axi_write_in_agent_ap_output_transaction); + // Transaction variable for predicted values to be sent out fuse_ctrl_core_axi_read_in_agent_ap + // Once a transaction is sent through an analysis_port, another transaction should + // be constructed for the next predicted transaction. + typedef fuse_ctrl_core_axi_read_in_transaction fuse_ctrl_core_axi_read_in_agent_ap_output_transaction_t; + fuse_ctrl_core_axi_read_in_agent_ap_output_transaction_t fuse_ctrl_core_axi_read_in_agent_ap_output_transaction; + // Code for sending output transaction out through fuse_ctrl_core_axi_read_in_agent_ap + // fuse_ctrl_core_axi_read_in_agent_ap.write(fuse_ctrl_core_axi_read_in_agent_ap_output_transaction); + // Transaction variable for predicted values to be sent out fuse_ctrl_prim_axi_read_in_agent_ap + // Once a transaction is sent through an analysis_port, another transaction should + // be constructed for the next predicted transaction. + typedef fuse_ctrl_prim_axi_read_in_transaction fuse_ctrl_prim_axi_read_in_agent_ap_output_transaction_t; + fuse_ctrl_prim_axi_read_in_agent_ap_output_transaction_t fuse_ctrl_prim_axi_read_in_agent_ap_output_transaction; + // Code for sending output transaction out through fuse_ctrl_prim_axi_read_in_agent_ap + // fuse_ctrl_prim_axi_read_in_agent_ap.write(fuse_ctrl_prim_axi_read_in_agent_ap_output_transaction); + // Transaction variable for predicted values to be sent out fuse_ctrl_in_agent_ap + // Once a transaction is sent through an analysis_port, another transaction should + // be constructed for the next predicted transaction. + typedef fuse_ctrl_in_transaction fuse_ctrl_in_agent_ap_output_transaction_t; + fuse_ctrl_in_agent_ap_output_transaction_t fuse_ctrl_in_agent_ap_output_transaction; + // Code for sending output transaction out through fuse_ctrl_in_agent_ap + // fuse_ctrl_in_agent_ap.write(fuse_ctrl_in_agent_ap_output_transaction); + // Transaction variable for predicted values to be sent out fuse_ctrl_rst_in_agent_ap + // Once a transaction is sent through an analysis_port, another transaction should + // be constructed for the next predicted transaction. + typedef fuse_ctrl_rst_in_transaction fuse_ctrl_rst_in_agent_ap_output_transaction_t; + fuse_ctrl_rst_in_agent_ap_output_transaction_t fuse_ctrl_rst_in_agent_ap_output_transaction; + // Code for sending output transaction out through fuse_ctrl_rst_in_agent_ap + // fuse_ctrl_rst_in_agent_ap.write(fuse_ctrl_rst_in_agent_ap_output_transaction); + // Transaction variable for predicted values to be sent out fuse_ctrl_secreg_axi_read_in_agent_ap + // Once a transaction is sent through an analysis_port, another transaction should + // be constructed for the next predicted transaction. + typedef fuse_ctrl_secreg_axi_read_in_transaction fuse_ctrl_secreg_axi_read_in_agent_ap_output_transaction_t; + fuse_ctrl_secreg_axi_read_in_agent_ap_output_transaction_t fuse_ctrl_secreg_axi_read_in_agent_ap_output_transaction; + // Code for sending output transaction out through fuse_ctrl_secreg_axi_read_in_agent_ap + // fuse_ctrl_secreg_axi_read_in_agent_ap.write(fuse_ctrl_secreg_axi_read_in_agent_ap_output_transaction); + // Transaction variable for predicted values to be sent out fuse_ctrl_core_axi_write_in_agent_ap + // Once a transaction is sent through an analysis_port, another transaction should + // be constructed for the next predicted transaction. + typedef fuse_ctrl_core_axi_write_in_transaction fuse_ctrl_core_axi_write_in_agent_ap_output_transaction_t; + fuse_ctrl_core_axi_write_in_agent_ap_output_transaction_t fuse_ctrl_core_axi_write_in_agent_ap_output_transaction; + // Code for sending output transaction out through fuse_ctrl_core_axi_write_in_agent_ap + // fuse_ctrl_core_axi_write_in_agent_ap.write(fuse_ctrl_core_axi_write_in_agent_ap_output_transaction); + // Transaction variable for predicted values to be sent out fuse_ctrl_lc_otp_in_agent_ap + // Once a transaction is sent through an analysis_port, another transaction should + // be constructed for the next predicted transaction. + typedef fuse_ctrl_lc_otp_in_transaction fuse_ctrl_lc_otp_in_agent_ap_output_transaction_t; + fuse_ctrl_lc_otp_in_agent_ap_output_transaction_t fuse_ctrl_lc_otp_in_agent_ap_output_transaction; + // Code for sending output transaction out through fuse_ctrl_lc_otp_in_agent_ap + // fuse_ctrl_lc_otp_in_agent_ap.write(fuse_ctrl_lc_otp_in_agent_ap_output_transaction); + + // Define transaction handles for debug visibility + fuse_ctrl_lc_otp_in_transaction fuse_ctrl_lc_otp_in_agent_ae_debug; + fuse_ctrl_rst_in_transaction fuse_ctrl_rst_in_agent_ae_debug; + fuse_ctrl_core_axi_write_in_transaction fuse_ctrl_core_axi_write_in_agent_ae_debug; + fuse_ctrl_secreg_axi_read_in_transaction fuse_ctrl_secreg_axi_read_in_agent_ae_debug; + fuse_ctrl_prim_axi_write_in_transaction fuse_ctrl_prim_axi_write_in_agent_ae_debug; + fuse_ctrl_in_transaction fuse_ctrl_in_agent_ae_debug; + fuse_ctrl_core_axi_read_in_transaction fuse_ctrl_core_axi_read_in_agent_ae_debug; + fuse_ctrl_prim_axi_read_in_transaction fuse_ctrl_prim_axi_read_in_agent_ae_debug; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // FUNCTION: new + function new(string name, uvm_component parent); + super.new(name,parent); + `uvm_warning("PREDICTOR_REVIEW", "This predictor has been created either through generation or re-generation with merging. Remove this warning after the predictor has been reviewed.") + // pragma uvmf custom new begin + // pragma uvmf custom new end + endfunction + + // FUNCTION: build_phase + virtual function void build_phase (uvm_phase phase); + + fuse_ctrl_lc_otp_in_agent_ae = new("fuse_ctrl_lc_otp_in_agent_ae", this); + fuse_ctrl_rst_in_agent_ae = new("fuse_ctrl_rst_in_agent_ae", this); + fuse_ctrl_core_axi_write_in_agent_ae = new("fuse_ctrl_core_axi_write_in_agent_ae", this); + fuse_ctrl_secreg_axi_read_in_agent_ae = new("fuse_ctrl_secreg_axi_read_in_agent_ae", this); + fuse_ctrl_prim_axi_write_in_agent_ae = new("fuse_ctrl_prim_axi_write_in_agent_ae", this); + fuse_ctrl_in_agent_ae = new("fuse_ctrl_in_agent_ae", this); + fuse_ctrl_core_axi_read_in_agent_ae = new("fuse_ctrl_core_axi_read_in_agent_ae", this); + fuse_ctrl_prim_axi_read_in_agent_ae = new("fuse_ctrl_prim_axi_read_in_agent_ae", this); + fuse_ctrl_prim_axi_write_in_agent_ap =new("fuse_ctrl_prim_axi_write_in_agent_ap", this ); + fuse_ctrl_core_axi_read_in_agent_ap =new("fuse_ctrl_core_axi_read_in_agent_ap", this ); + fuse_ctrl_prim_axi_read_in_agent_ap =new("fuse_ctrl_prim_axi_read_in_agent_ap", this ); + fuse_ctrl_in_agent_ap =new("fuse_ctrl_in_agent_ap", this ); + fuse_ctrl_rst_in_agent_ap =new("fuse_ctrl_rst_in_agent_ap", this ); + fuse_ctrl_secreg_axi_read_in_agent_ap =new("fuse_ctrl_secreg_axi_read_in_agent_ap", this ); + fuse_ctrl_core_axi_write_in_agent_ap =new("fuse_ctrl_core_axi_write_in_agent_ap", this ); + fuse_ctrl_lc_otp_in_agent_ap =new("fuse_ctrl_lc_otp_in_agent_ap", this ); + // pragma uvmf custom build_phase begin + // pragma uvmf custom build_phase end + endfunction + + // FUNCTION: write_fuse_ctrl_lc_otp_in_agent_ae + // Transactions received through fuse_ctrl_lc_otp_in_agent_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_fuse_ctrl_lc_otp_in_agent_ae(fuse_ctrl_lc_otp_in_transaction t); + // pragma uvmf custom fuse_ctrl_lc_otp_in_agent_ae_predictor begin + fuse_ctrl_lc_otp_in_agent_ae_debug = t; + `uvm_info("PRED", "Transaction Received through fuse_ctrl_lc_otp_in_agent_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // Construct one of each output transaction type. + fuse_ctrl_prim_axi_write_in_agent_ap_output_transaction = fuse_ctrl_prim_axi_write_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_prim_axi_write_in_agent_ap_output_transaction"); + fuse_ctrl_core_axi_read_in_agent_ap_output_transaction = fuse_ctrl_core_axi_read_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_core_axi_read_in_agent_ap_output_transaction"); + fuse_ctrl_prim_axi_read_in_agent_ap_output_transaction = fuse_ctrl_prim_axi_read_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_prim_axi_read_in_agent_ap_output_transaction"); + fuse_ctrl_in_agent_ap_output_transaction = fuse_ctrl_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_in_agent_ap_output_transaction"); + fuse_ctrl_rst_in_agent_ap_output_transaction = fuse_ctrl_rst_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_rst_in_agent_ap_output_transaction"); + fuse_ctrl_secreg_axi_read_in_agent_ap_output_transaction = fuse_ctrl_secreg_axi_read_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_secreg_axi_read_in_agent_ap_output_transaction"); + fuse_ctrl_core_axi_write_in_agent_ap_output_transaction = fuse_ctrl_core_axi_write_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_core_axi_write_in_agent_ap_output_transaction"); + fuse_ctrl_lc_otp_in_agent_ap_output_transaction = fuse_ctrl_lc_otp_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_lc_otp_in_agent_ap_output_transaction"); + // UVMF_CHANGE_ME: Implement predictor model here. + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "UVMF_CHANGE_ME: The fuse_ctrl_predictor::write_fuse_ctrl_lc_otp_in_agent_ae function needs to be completed with DUT prediction model",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + + // Code for sending output transaction out through fuse_ctrl_prim_axi_write_in_agent_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_prim_axi_write_in_agent_ap.write(fuse_ctrl_prim_axi_write_in_agent_ap_output_transaction); + // Code for sending output transaction out through fuse_ctrl_core_axi_read_in_agent_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_core_axi_read_in_agent_ap.write(fuse_ctrl_core_axi_read_in_agent_ap_output_transaction); + // Code for sending output transaction out through fuse_ctrl_prim_axi_read_in_agent_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_prim_axi_read_in_agent_ap.write(fuse_ctrl_prim_axi_read_in_agent_ap_output_transaction); + // Code for sending output transaction out through fuse_ctrl_in_agent_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_in_agent_ap.write(fuse_ctrl_in_agent_ap_output_transaction); + // Code for sending output transaction out through fuse_ctrl_rst_in_agent_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_rst_in_agent_ap.write(fuse_ctrl_rst_in_agent_ap_output_transaction); + // Code for sending output transaction out through fuse_ctrl_secreg_axi_read_in_agent_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_secreg_axi_read_in_agent_ap.write(fuse_ctrl_secreg_axi_read_in_agent_ap_output_transaction); + // Code for sending output transaction out through fuse_ctrl_core_axi_write_in_agent_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_core_axi_write_in_agent_ap.write(fuse_ctrl_core_axi_write_in_agent_ap_output_transaction); + // Code for sending output transaction out through fuse_ctrl_lc_otp_in_agent_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_lc_otp_in_agent_ap.write(fuse_ctrl_lc_otp_in_agent_ap_output_transaction); + // pragma uvmf custom fuse_ctrl_lc_otp_in_agent_ae_predictor end + endfunction + + // FUNCTION: write_fuse_ctrl_rst_in_agent_ae + // Transactions received through fuse_ctrl_rst_in_agent_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_fuse_ctrl_rst_in_agent_ae(fuse_ctrl_rst_in_transaction t); + // pragma uvmf custom fuse_ctrl_rst_in_agent_ae_predictor begin + fuse_ctrl_rst_in_agent_ae_debug = t; + `uvm_info("PRED", "Transaction Received through fuse_ctrl_rst_in_agent_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // Construct one of each output transaction type. + fuse_ctrl_prim_axi_write_in_agent_ap_output_transaction = fuse_ctrl_prim_axi_write_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_prim_axi_write_in_agent_ap_output_transaction"); + fuse_ctrl_core_axi_read_in_agent_ap_output_transaction = fuse_ctrl_core_axi_read_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_core_axi_read_in_agent_ap_output_transaction"); + fuse_ctrl_prim_axi_read_in_agent_ap_output_transaction = fuse_ctrl_prim_axi_read_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_prim_axi_read_in_agent_ap_output_transaction"); + fuse_ctrl_in_agent_ap_output_transaction = fuse_ctrl_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_in_agent_ap_output_transaction"); + fuse_ctrl_rst_in_agent_ap_output_transaction = fuse_ctrl_rst_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_rst_in_agent_ap_output_transaction"); + fuse_ctrl_secreg_axi_read_in_agent_ap_output_transaction = fuse_ctrl_secreg_axi_read_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_secreg_axi_read_in_agent_ap_output_transaction"); + fuse_ctrl_core_axi_write_in_agent_ap_output_transaction = fuse_ctrl_core_axi_write_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_core_axi_write_in_agent_ap_output_transaction"); + fuse_ctrl_lc_otp_in_agent_ap_output_transaction = fuse_ctrl_lc_otp_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_lc_otp_in_agent_ap_output_transaction"); + // UVMF_CHANGE_ME: Implement predictor model here. + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "UVMF_CHANGE_ME: The fuse_ctrl_predictor::write_fuse_ctrl_rst_in_agent_ae function needs to be completed with DUT prediction model",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + + // Code for sending output transaction out through fuse_ctrl_prim_axi_write_in_agent_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_prim_axi_write_in_agent_ap.write(fuse_ctrl_prim_axi_write_in_agent_ap_output_transaction); + // Code for sending output transaction out through fuse_ctrl_core_axi_read_in_agent_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_core_axi_read_in_agent_ap.write(fuse_ctrl_core_axi_read_in_agent_ap_output_transaction); + // Code for sending output transaction out through fuse_ctrl_prim_axi_read_in_agent_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_prim_axi_read_in_agent_ap.write(fuse_ctrl_prim_axi_read_in_agent_ap_output_transaction); + // Code for sending output transaction out through fuse_ctrl_in_agent_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_in_agent_ap.write(fuse_ctrl_in_agent_ap_output_transaction); + // Code for sending output transaction out through fuse_ctrl_rst_in_agent_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_rst_in_agent_ap.write(fuse_ctrl_rst_in_agent_ap_output_transaction); + // Code for sending output transaction out through fuse_ctrl_secreg_axi_read_in_agent_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_secreg_axi_read_in_agent_ap.write(fuse_ctrl_secreg_axi_read_in_agent_ap_output_transaction); + // Code for sending output transaction out through fuse_ctrl_core_axi_write_in_agent_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_core_axi_write_in_agent_ap.write(fuse_ctrl_core_axi_write_in_agent_ap_output_transaction); + // Code for sending output transaction out through fuse_ctrl_lc_otp_in_agent_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_lc_otp_in_agent_ap.write(fuse_ctrl_lc_otp_in_agent_ap_output_transaction); + // pragma uvmf custom fuse_ctrl_rst_in_agent_ae_predictor end + endfunction + + // FUNCTION: write_fuse_ctrl_core_axi_write_in_agent_ae + // Transactions received through fuse_ctrl_core_axi_write_in_agent_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_fuse_ctrl_core_axi_write_in_agent_ae(fuse_ctrl_core_axi_write_in_transaction t); + // pragma uvmf custom fuse_ctrl_core_axi_write_in_agent_ae_predictor begin + fuse_ctrl_core_axi_write_in_agent_ae_debug = t; + `uvm_info("PRED", "Transaction Received through fuse_ctrl_core_axi_write_in_agent_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // Construct one of each output transaction type. + fuse_ctrl_prim_axi_write_in_agent_ap_output_transaction = fuse_ctrl_prim_axi_write_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_prim_axi_write_in_agent_ap_output_transaction"); + fuse_ctrl_core_axi_read_in_agent_ap_output_transaction = fuse_ctrl_core_axi_read_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_core_axi_read_in_agent_ap_output_transaction"); + fuse_ctrl_prim_axi_read_in_agent_ap_output_transaction = fuse_ctrl_prim_axi_read_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_prim_axi_read_in_agent_ap_output_transaction"); + fuse_ctrl_in_agent_ap_output_transaction = fuse_ctrl_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_in_agent_ap_output_transaction"); + fuse_ctrl_rst_in_agent_ap_output_transaction = fuse_ctrl_rst_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_rst_in_agent_ap_output_transaction"); + fuse_ctrl_secreg_axi_read_in_agent_ap_output_transaction = fuse_ctrl_secreg_axi_read_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_secreg_axi_read_in_agent_ap_output_transaction"); + fuse_ctrl_core_axi_write_in_agent_ap_output_transaction = fuse_ctrl_core_axi_write_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_core_axi_write_in_agent_ap_output_transaction"); + fuse_ctrl_lc_otp_in_agent_ap_output_transaction = fuse_ctrl_lc_otp_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_lc_otp_in_agent_ap_output_transaction"); + // UVMF_CHANGE_ME: Implement predictor model here. + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "UVMF_CHANGE_ME: The fuse_ctrl_predictor::write_fuse_ctrl_core_axi_write_in_agent_ae function needs to be completed with DUT prediction model",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + + // Code for sending output transaction out through fuse_ctrl_prim_axi_write_in_agent_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_prim_axi_write_in_agent_ap.write(fuse_ctrl_prim_axi_write_in_agent_ap_output_transaction); + // Code for sending output transaction out through fuse_ctrl_core_axi_read_in_agent_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_core_axi_read_in_agent_ap.write(fuse_ctrl_core_axi_read_in_agent_ap_output_transaction); + // Code for sending output transaction out through fuse_ctrl_prim_axi_read_in_agent_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_prim_axi_read_in_agent_ap.write(fuse_ctrl_prim_axi_read_in_agent_ap_output_transaction); + // Code for sending output transaction out through fuse_ctrl_in_agent_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_in_agent_ap.write(fuse_ctrl_in_agent_ap_output_transaction); + // Code for sending output transaction out through fuse_ctrl_rst_in_agent_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_rst_in_agent_ap.write(fuse_ctrl_rst_in_agent_ap_output_transaction); + // Code for sending output transaction out through fuse_ctrl_secreg_axi_read_in_agent_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_secreg_axi_read_in_agent_ap.write(fuse_ctrl_secreg_axi_read_in_agent_ap_output_transaction); + // Code for sending output transaction out through fuse_ctrl_core_axi_write_in_agent_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_core_axi_write_in_agent_ap.write(fuse_ctrl_core_axi_write_in_agent_ap_output_transaction); + // Code for sending output transaction out through fuse_ctrl_lc_otp_in_agent_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_lc_otp_in_agent_ap.write(fuse_ctrl_lc_otp_in_agent_ap_output_transaction); + // pragma uvmf custom fuse_ctrl_core_axi_write_in_agent_ae_predictor end + endfunction + + // FUNCTION: write_fuse_ctrl_secreg_axi_read_in_agent_ae + // Transactions received through fuse_ctrl_secreg_axi_read_in_agent_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_fuse_ctrl_secreg_axi_read_in_agent_ae(fuse_ctrl_secreg_axi_read_in_transaction t); + // pragma uvmf custom fuse_ctrl_secreg_axi_read_in_agent_ae_predictor begin + fuse_ctrl_secreg_axi_read_in_agent_ae_debug = t; + `uvm_info("PRED", "Transaction Received through fuse_ctrl_secreg_axi_read_in_agent_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // Construct one of each output transaction type. + fuse_ctrl_prim_axi_write_in_agent_ap_output_transaction = fuse_ctrl_prim_axi_write_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_prim_axi_write_in_agent_ap_output_transaction"); + fuse_ctrl_core_axi_read_in_agent_ap_output_transaction = fuse_ctrl_core_axi_read_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_core_axi_read_in_agent_ap_output_transaction"); + fuse_ctrl_prim_axi_read_in_agent_ap_output_transaction = fuse_ctrl_prim_axi_read_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_prim_axi_read_in_agent_ap_output_transaction"); + fuse_ctrl_in_agent_ap_output_transaction = fuse_ctrl_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_in_agent_ap_output_transaction"); + fuse_ctrl_rst_in_agent_ap_output_transaction = fuse_ctrl_rst_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_rst_in_agent_ap_output_transaction"); + fuse_ctrl_secreg_axi_read_in_agent_ap_output_transaction = fuse_ctrl_secreg_axi_read_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_secreg_axi_read_in_agent_ap_output_transaction"); + fuse_ctrl_core_axi_write_in_agent_ap_output_transaction = fuse_ctrl_core_axi_write_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_core_axi_write_in_agent_ap_output_transaction"); + fuse_ctrl_lc_otp_in_agent_ap_output_transaction = fuse_ctrl_lc_otp_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_lc_otp_in_agent_ap_output_transaction"); + // UVMF_CHANGE_ME: Implement predictor model here. + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "UVMF_CHANGE_ME: The fuse_ctrl_predictor::write_fuse_ctrl_secreg_axi_read_in_agent_ae function needs to be completed with DUT prediction model",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + + // Code for sending output transaction out through fuse_ctrl_prim_axi_write_in_agent_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_prim_axi_write_in_agent_ap.write(fuse_ctrl_prim_axi_write_in_agent_ap_output_transaction); + // Code for sending output transaction out through fuse_ctrl_core_axi_read_in_agent_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_core_axi_read_in_agent_ap.write(fuse_ctrl_core_axi_read_in_agent_ap_output_transaction); + // Code for sending output transaction out through fuse_ctrl_prim_axi_read_in_agent_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_prim_axi_read_in_agent_ap.write(fuse_ctrl_prim_axi_read_in_agent_ap_output_transaction); + // Code for sending output transaction out through fuse_ctrl_in_agent_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_in_agent_ap.write(fuse_ctrl_in_agent_ap_output_transaction); + // Code for sending output transaction out through fuse_ctrl_rst_in_agent_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_rst_in_agent_ap.write(fuse_ctrl_rst_in_agent_ap_output_transaction); + // Code for sending output transaction out through fuse_ctrl_secreg_axi_read_in_agent_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_secreg_axi_read_in_agent_ap.write(fuse_ctrl_secreg_axi_read_in_agent_ap_output_transaction); + // Code for sending output transaction out through fuse_ctrl_core_axi_write_in_agent_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_core_axi_write_in_agent_ap.write(fuse_ctrl_core_axi_write_in_agent_ap_output_transaction); + // Code for sending output transaction out through fuse_ctrl_lc_otp_in_agent_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_lc_otp_in_agent_ap.write(fuse_ctrl_lc_otp_in_agent_ap_output_transaction); + // pragma uvmf custom fuse_ctrl_secreg_axi_read_in_agent_ae_predictor end + endfunction + + // FUNCTION: write_fuse_ctrl_prim_axi_write_in_agent_ae + // Transactions received through fuse_ctrl_prim_axi_write_in_agent_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_fuse_ctrl_prim_axi_write_in_agent_ae(fuse_ctrl_prim_axi_write_in_transaction t); + // pragma uvmf custom fuse_ctrl_prim_axi_write_in_agent_ae_predictor begin + fuse_ctrl_prim_axi_write_in_agent_ae_debug = t; + `uvm_info("PRED", "Transaction Received through fuse_ctrl_prim_axi_write_in_agent_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // Construct one of each output transaction type. + fuse_ctrl_prim_axi_write_in_agent_ap_output_transaction = fuse_ctrl_prim_axi_write_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_prim_axi_write_in_agent_ap_output_transaction"); + fuse_ctrl_core_axi_read_in_agent_ap_output_transaction = fuse_ctrl_core_axi_read_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_core_axi_read_in_agent_ap_output_transaction"); + fuse_ctrl_prim_axi_read_in_agent_ap_output_transaction = fuse_ctrl_prim_axi_read_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_prim_axi_read_in_agent_ap_output_transaction"); + fuse_ctrl_in_agent_ap_output_transaction = fuse_ctrl_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_in_agent_ap_output_transaction"); + fuse_ctrl_rst_in_agent_ap_output_transaction = fuse_ctrl_rst_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_rst_in_agent_ap_output_transaction"); + fuse_ctrl_secreg_axi_read_in_agent_ap_output_transaction = fuse_ctrl_secreg_axi_read_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_secreg_axi_read_in_agent_ap_output_transaction"); + fuse_ctrl_core_axi_write_in_agent_ap_output_transaction = fuse_ctrl_core_axi_write_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_core_axi_write_in_agent_ap_output_transaction"); + fuse_ctrl_lc_otp_in_agent_ap_output_transaction = fuse_ctrl_lc_otp_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_lc_otp_in_agent_ap_output_transaction"); + // UVMF_CHANGE_ME: Implement predictor model here. + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "UVMF_CHANGE_ME: The fuse_ctrl_predictor::write_fuse_ctrl_prim_axi_write_in_agent_ae function needs to be completed with DUT prediction model",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + + // Code for sending output transaction out through fuse_ctrl_prim_axi_write_in_agent_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_prim_axi_write_in_agent_ap.write(fuse_ctrl_prim_axi_write_in_agent_ap_output_transaction); + // Code for sending output transaction out through fuse_ctrl_core_axi_read_in_agent_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_core_axi_read_in_agent_ap.write(fuse_ctrl_core_axi_read_in_agent_ap_output_transaction); + // Code for sending output transaction out through fuse_ctrl_prim_axi_read_in_agent_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_prim_axi_read_in_agent_ap.write(fuse_ctrl_prim_axi_read_in_agent_ap_output_transaction); + // Code for sending output transaction out through fuse_ctrl_in_agent_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_in_agent_ap.write(fuse_ctrl_in_agent_ap_output_transaction); + // Code for sending output transaction out through fuse_ctrl_rst_in_agent_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_rst_in_agent_ap.write(fuse_ctrl_rst_in_agent_ap_output_transaction); + // Code for sending output transaction out through fuse_ctrl_secreg_axi_read_in_agent_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_secreg_axi_read_in_agent_ap.write(fuse_ctrl_secreg_axi_read_in_agent_ap_output_transaction); + // Code for sending output transaction out through fuse_ctrl_core_axi_write_in_agent_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_core_axi_write_in_agent_ap.write(fuse_ctrl_core_axi_write_in_agent_ap_output_transaction); + // Code for sending output transaction out through fuse_ctrl_lc_otp_in_agent_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_lc_otp_in_agent_ap.write(fuse_ctrl_lc_otp_in_agent_ap_output_transaction); + // pragma uvmf custom fuse_ctrl_prim_axi_write_in_agent_ae_predictor end + endfunction + + // FUNCTION: write_fuse_ctrl_in_agent_ae + // Transactions received through fuse_ctrl_in_agent_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_fuse_ctrl_in_agent_ae(fuse_ctrl_in_transaction t); + // pragma uvmf custom fuse_ctrl_in_agent_ae_predictor begin + fuse_ctrl_in_agent_ae_debug = t; + `uvm_info("PRED", "Transaction Received through fuse_ctrl_in_agent_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // Construct one of each output transaction type. + fuse_ctrl_prim_axi_write_in_agent_ap_output_transaction = fuse_ctrl_prim_axi_write_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_prim_axi_write_in_agent_ap_output_transaction"); + fuse_ctrl_core_axi_read_in_agent_ap_output_transaction = fuse_ctrl_core_axi_read_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_core_axi_read_in_agent_ap_output_transaction"); + fuse_ctrl_prim_axi_read_in_agent_ap_output_transaction = fuse_ctrl_prim_axi_read_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_prim_axi_read_in_agent_ap_output_transaction"); + fuse_ctrl_in_agent_ap_output_transaction = fuse_ctrl_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_in_agent_ap_output_transaction"); + fuse_ctrl_rst_in_agent_ap_output_transaction = fuse_ctrl_rst_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_rst_in_agent_ap_output_transaction"); + fuse_ctrl_secreg_axi_read_in_agent_ap_output_transaction = fuse_ctrl_secreg_axi_read_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_secreg_axi_read_in_agent_ap_output_transaction"); + fuse_ctrl_core_axi_write_in_agent_ap_output_transaction = fuse_ctrl_core_axi_write_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_core_axi_write_in_agent_ap_output_transaction"); + fuse_ctrl_lc_otp_in_agent_ap_output_transaction = fuse_ctrl_lc_otp_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_lc_otp_in_agent_ap_output_transaction"); + // UVMF_CHANGE_ME: Implement predictor model here. + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "UVMF_CHANGE_ME: The fuse_ctrl_predictor::write_fuse_ctrl_in_agent_ae function needs to be completed with DUT prediction model",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + + // Code for sending output transaction out through fuse_ctrl_prim_axi_write_in_agent_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_prim_axi_write_in_agent_ap.write(fuse_ctrl_prim_axi_write_in_agent_ap_output_transaction); + // Code for sending output transaction out through fuse_ctrl_core_axi_read_in_agent_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_core_axi_read_in_agent_ap.write(fuse_ctrl_core_axi_read_in_agent_ap_output_transaction); + // Code for sending output transaction out through fuse_ctrl_prim_axi_read_in_agent_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_prim_axi_read_in_agent_ap.write(fuse_ctrl_prim_axi_read_in_agent_ap_output_transaction); + // Code for sending output transaction out through fuse_ctrl_in_agent_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_in_agent_ap.write(fuse_ctrl_in_agent_ap_output_transaction); + // Code for sending output transaction out through fuse_ctrl_rst_in_agent_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_rst_in_agent_ap.write(fuse_ctrl_rst_in_agent_ap_output_transaction); + // Code for sending output transaction out through fuse_ctrl_secreg_axi_read_in_agent_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_secreg_axi_read_in_agent_ap.write(fuse_ctrl_secreg_axi_read_in_agent_ap_output_transaction); + // Code for sending output transaction out through fuse_ctrl_core_axi_write_in_agent_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_core_axi_write_in_agent_ap.write(fuse_ctrl_core_axi_write_in_agent_ap_output_transaction); + // Code for sending output transaction out through fuse_ctrl_lc_otp_in_agent_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_lc_otp_in_agent_ap.write(fuse_ctrl_lc_otp_in_agent_ap_output_transaction); + // pragma uvmf custom fuse_ctrl_in_agent_ae_predictor end + endfunction + + // FUNCTION: write_fuse_ctrl_core_axi_read_in_agent_ae + // Transactions received through fuse_ctrl_core_axi_read_in_agent_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_fuse_ctrl_core_axi_read_in_agent_ae(fuse_ctrl_core_axi_read_in_transaction t); + // pragma uvmf custom fuse_ctrl_core_axi_read_in_agent_ae_predictor begin + fuse_ctrl_core_axi_read_in_agent_ae_debug = t; + `uvm_info("PRED", "Transaction Received through fuse_ctrl_core_axi_read_in_agent_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // Construct one of each output transaction type. + fuse_ctrl_prim_axi_write_in_agent_ap_output_transaction = fuse_ctrl_prim_axi_write_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_prim_axi_write_in_agent_ap_output_transaction"); + fuse_ctrl_core_axi_read_in_agent_ap_output_transaction = fuse_ctrl_core_axi_read_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_core_axi_read_in_agent_ap_output_transaction"); + fuse_ctrl_prim_axi_read_in_agent_ap_output_transaction = fuse_ctrl_prim_axi_read_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_prim_axi_read_in_agent_ap_output_transaction"); + fuse_ctrl_in_agent_ap_output_transaction = fuse_ctrl_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_in_agent_ap_output_transaction"); + fuse_ctrl_rst_in_agent_ap_output_transaction = fuse_ctrl_rst_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_rst_in_agent_ap_output_transaction"); + fuse_ctrl_secreg_axi_read_in_agent_ap_output_transaction = fuse_ctrl_secreg_axi_read_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_secreg_axi_read_in_agent_ap_output_transaction"); + fuse_ctrl_core_axi_write_in_agent_ap_output_transaction = fuse_ctrl_core_axi_write_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_core_axi_write_in_agent_ap_output_transaction"); + fuse_ctrl_lc_otp_in_agent_ap_output_transaction = fuse_ctrl_lc_otp_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_lc_otp_in_agent_ap_output_transaction"); + // UVMF_CHANGE_ME: Implement predictor model here. + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "UVMF_CHANGE_ME: The fuse_ctrl_predictor::write_fuse_ctrl_core_axi_read_in_agent_ae function needs to be completed with DUT prediction model",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + + // Code for sending output transaction out through fuse_ctrl_prim_axi_write_in_agent_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_prim_axi_write_in_agent_ap.write(fuse_ctrl_prim_axi_write_in_agent_ap_output_transaction); + // Code for sending output transaction out through fuse_ctrl_core_axi_read_in_agent_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_core_axi_read_in_agent_ap.write(fuse_ctrl_core_axi_read_in_agent_ap_output_transaction); + // Code for sending output transaction out through fuse_ctrl_prim_axi_read_in_agent_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_prim_axi_read_in_agent_ap.write(fuse_ctrl_prim_axi_read_in_agent_ap_output_transaction); + // Code for sending output transaction out through fuse_ctrl_in_agent_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_in_agent_ap.write(fuse_ctrl_in_agent_ap_output_transaction); + // Code for sending output transaction out through fuse_ctrl_rst_in_agent_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_rst_in_agent_ap.write(fuse_ctrl_rst_in_agent_ap_output_transaction); + // Code for sending output transaction out through fuse_ctrl_secreg_axi_read_in_agent_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_secreg_axi_read_in_agent_ap.write(fuse_ctrl_secreg_axi_read_in_agent_ap_output_transaction); + // Code for sending output transaction out through fuse_ctrl_core_axi_write_in_agent_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_core_axi_write_in_agent_ap.write(fuse_ctrl_core_axi_write_in_agent_ap_output_transaction); + // Code for sending output transaction out through fuse_ctrl_lc_otp_in_agent_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_lc_otp_in_agent_ap.write(fuse_ctrl_lc_otp_in_agent_ap_output_transaction); + // pragma uvmf custom fuse_ctrl_core_axi_read_in_agent_ae_predictor end + endfunction + + // FUNCTION: write_fuse_ctrl_prim_axi_read_in_agent_ae + // Transactions received through fuse_ctrl_prim_axi_read_in_agent_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_fuse_ctrl_prim_axi_read_in_agent_ae(fuse_ctrl_prim_axi_read_in_transaction t); + // pragma uvmf custom fuse_ctrl_prim_axi_read_in_agent_ae_predictor begin + fuse_ctrl_prim_axi_read_in_agent_ae_debug = t; + `uvm_info("PRED", "Transaction Received through fuse_ctrl_prim_axi_read_in_agent_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // Construct one of each output transaction type. + fuse_ctrl_prim_axi_write_in_agent_ap_output_transaction = fuse_ctrl_prim_axi_write_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_prim_axi_write_in_agent_ap_output_transaction"); + fuse_ctrl_core_axi_read_in_agent_ap_output_transaction = fuse_ctrl_core_axi_read_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_core_axi_read_in_agent_ap_output_transaction"); + fuse_ctrl_prim_axi_read_in_agent_ap_output_transaction = fuse_ctrl_prim_axi_read_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_prim_axi_read_in_agent_ap_output_transaction"); + fuse_ctrl_in_agent_ap_output_transaction = fuse_ctrl_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_in_agent_ap_output_transaction"); + fuse_ctrl_rst_in_agent_ap_output_transaction = fuse_ctrl_rst_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_rst_in_agent_ap_output_transaction"); + fuse_ctrl_secreg_axi_read_in_agent_ap_output_transaction = fuse_ctrl_secreg_axi_read_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_secreg_axi_read_in_agent_ap_output_transaction"); + fuse_ctrl_core_axi_write_in_agent_ap_output_transaction = fuse_ctrl_core_axi_write_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_core_axi_write_in_agent_ap_output_transaction"); + fuse_ctrl_lc_otp_in_agent_ap_output_transaction = fuse_ctrl_lc_otp_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_lc_otp_in_agent_ap_output_transaction"); + // UVMF_CHANGE_ME: Implement predictor model here. + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "UVMF_CHANGE_ME: The fuse_ctrl_predictor::write_fuse_ctrl_prim_axi_read_in_agent_ae function needs to be completed with DUT prediction model",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + + // Code for sending output transaction out through fuse_ctrl_prim_axi_write_in_agent_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_prim_axi_write_in_agent_ap.write(fuse_ctrl_prim_axi_write_in_agent_ap_output_transaction); + // Code for sending output transaction out through fuse_ctrl_core_axi_read_in_agent_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_core_axi_read_in_agent_ap.write(fuse_ctrl_core_axi_read_in_agent_ap_output_transaction); + // Code for sending output transaction out through fuse_ctrl_prim_axi_read_in_agent_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_prim_axi_read_in_agent_ap.write(fuse_ctrl_prim_axi_read_in_agent_ap_output_transaction); + // Code for sending output transaction out through fuse_ctrl_in_agent_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_in_agent_ap.write(fuse_ctrl_in_agent_ap_output_transaction); + // Code for sending output transaction out through fuse_ctrl_rst_in_agent_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_rst_in_agent_ap.write(fuse_ctrl_rst_in_agent_ap_output_transaction); + // Code for sending output transaction out through fuse_ctrl_secreg_axi_read_in_agent_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_secreg_axi_read_in_agent_ap.write(fuse_ctrl_secreg_axi_read_in_agent_ap_output_transaction); + // Code for sending output transaction out through fuse_ctrl_core_axi_write_in_agent_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_core_axi_write_in_agent_ap.write(fuse_ctrl_core_axi_write_in_agent_ap_output_transaction); + // Code for sending output transaction out through fuse_ctrl_lc_otp_in_agent_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_lc_otp_in_agent_ap.write(fuse_ctrl_lc_otp_in_agent_ap_output_transaction); + // pragma uvmf custom fuse_ctrl_prim_axi_read_in_agent_ae_predictor end + endfunction + + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/environment_packages/fuse_ctrl_env_pkg/src/fuse_ctrl_scoreboard.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/environment_packages/fuse_ctrl_env_pkg/src/fuse_ctrl_scoreboard.svh new file mode 100644 index 0000000..626fdd0 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/environment_packages/fuse_ctrl_env_pkg/src/fuse_ctrl_scoreboard.svh @@ -0,0 +1,271 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This analysis component contains analysis_exports for receiving +// data and analysis_ports for sending data. +// +// This analysis component has the following analysis_exports that receive the +// listed transaction type. +// +// fuse_ctrl_lc_otp_in_agent_ae receives transactions of type fuse_ctrl_lc_otp_in_transaction +// fuse_ctrl_rst_in_agent_ae receives transactions of type fuse_ctrl_rst_in_transaction +// fuse_ctrl_core_axi_write_in_agent_ae receives transactions of type fuse_ctrl_core_axi_write_in_transaction +// fuse_ctrl_secreg_axi_read_in_agent_ae receives transactions of type fuse_ctrl_secreg_axi_read_in_transaction +// fuse_ctrl_prim_axi_write_in_agent_ae receives transactions of type fuse_ctrl_prim_axi_write_in_transaction +// fuse_ctrl_in_agent_ae receives transactions of type fuse_ctrl_in_transaction +// fuse_ctrl_core_axi_read_in_agent_ae receives transactions of type fuse_ctrl_core_axi_read_in_transaction +// fuse_ctrl_prim_axi_read_in_agent_ae receives transactions of type fuse_ctrl_prim_axi_read_in_transaction +// +// This analysis component has the following analysis_ports that can broadcast +// the listed transaction type. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + +class fuse_ctrl_scoreboard #( + type CONFIG_T, + type BASE_T = uvm_component + ) extends BASE_T; + + // Factory registration of this class + `uvm_component_param_utils( fuse_ctrl_scoreboard #( + CONFIG_T, + BASE_T + )) + + + // Instantiate a handle to the configuration of the environment in which this component resides + CONFIG_T configuration; + + + // Instantiate the analysis exports + uvm_analysis_imp_fuse_ctrl_lc_otp_in_agent_ae #(fuse_ctrl_lc_otp_in_transaction, fuse_ctrl_scoreboard #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + )) fuse_ctrl_lc_otp_in_agent_ae; + uvm_analysis_imp_fuse_ctrl_rst_in_agent_ae #(fuse_ctrl_rst_in_transaction, fuse_ctrl_scoreboard #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + )) fuse_ctrl_rst_in_agent_ae; + uvm_analysis_imp_fuse_ctrl_core_axi_write_in_agent_ae #(fuse_ctrl_core_axi_write_in_transaction, fuse_ctrl_scoreboard #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + )) fuse_ctrl_core_axi_write_in_agent_ae; + uvm_analysis_imp_fuse_ctrl_secreg_axi_read_in_agent_ae #(fuse_ctrl_secreg_axi_read_in_transaction, fuse_ctrl_scoreboard #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + )) fuse_ctrl_secreg_axi_read_in_agent_ae; + uvm_analysis_imp_fuse_ctrl_prim_axi_write_in_agent_ae #(fuse_ctrl_prim_axi_write_in_transaction, fuse_ctrl_scoreboard #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + )) fuse_ctrl_prim_axi_write_in_agent_ae; + uvm_analysis_imp_fuse_ctrl_in_agent_ae #(fuse_ctrl_in_transaction, fuse_ctrl_scoreboard #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + )) fuse_ctrl_in_agent_ae; + uvm_analysis_imp_fuse_ctrl_core_axi_read_in_agent_ae #(fuse_ctrl_core_axi_read_in_transaction, fuse_ctrl_scoreboard #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + )) fuse_ctrl_core_axi_read_in_agent_ae; + uvm_analysis_imp_fuse_ctrl_prim_axi_read_in_agent_ae #(fuse_ctrl_prim_axi_read_in_transaction, fuse_ctrl_scoreboard #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + )) fuse_ctrl_prim_axi_read_in_agent_ae; + + + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // FUNCTION: new + function new(string name, uvm_component parent); + super.new(name,parent); + // pragma uvmf custom new begin + // pragma uvmf custom new end + endfunction + + // FUNCTION: build_phase + virtual function void build_phase (uvm_phase phase); + + fuse_ctrl_lc_otp_in_agent_ae = new("fuse_ctrl_lc_otp_in_agent_ae", this); + fuse_ctrl_rst_in_agent_ae = new("fuse_ctrl_rst_in_agent_ae", this); + fuse_ctrl_core_axi_write_in_agent_ae = new("fuse_ctrl_core_axi_write_in_agent_ae", this); + fuse_ctrl_secreg_axi_read_in_agent_ae = new("fuse_ctrl_secreg_axi_read_in_agent_ae", this); + fuse_ctrl_prim_axi_write_in_agent_ae = new("fuse_ctrl_prim_axi_write_in_agent_ae", this); + fuse_ctrl_in_agent_ae = new("fuse_ctrl_in_agent_ae", this); + fuse_ctrl_core_axi_read_in_agent_ae = new("fuse_ctrl_core_axi_read_in_agent_ae", this); + fuse_ctrl_prim_axi_read_in_agent_ae = new("fuse_ctrl_prim_axi_read_in_agent_ae", this); + // pragma uvmf custom build_phase begin + // pragma uvmf custom build_phase end + endfunction + + // FUNCTION: write_fuse_ctrl_lc_otp_in_agent_ae + // Transactions received through fuse_ctrl_lc_otp_in_agent_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_fuse_ctrl_lc_otp_in_agent_ae(fuse_ctrl_lc_otp_in_transaction t); + // pragma uvmf custom fuse_ctrl_lc_otp_in_agent_ae_scoreboard begin + `uvm_info("PRED", "Transaction Received through fuse_ctrl_lc_otp_in_agent_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // UVMF_CHANGE_ME: Implement custom scoreboard here. + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "UVMF_CHANGE_ME: The fuse_ctrl_scoreboard::write_fuse_ctrl_lc_otp_in_agent_ae function needs to be completed with custom scoreboard functionality",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + + // pragma uvmf custom fuse_ctrl_lc_otp_in_agent_ae_scoreboard end + endfunction + + // FUNCTION: write_fuse_ctrl_rst_in_agent_ae + // Transactions received through fuse_ctrl_rst_in_agent_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_fuse_ctrl_rst_in_agent_ae(fuse_ctrl_rst_in_transaction t); + // pragma uvmf custom fuse_ctrl_rst_in_agent_ae_scoreboard begin + `uvm_info("PRED", "Transaction Received through fuse_ctrl_rst_in_agent_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // UVMF_CHANGE_ME: Implement custom scoreboard here. + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "UVMF_CHANGE_ME: The fuse_ctrl_scoreboard::write_fuse_ctrl_rst_in_agent_ae function needs to be completed with custom scoreboard functionality",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + + // pragma uvmf custom fuse_ctrl_rst_in_agent_ae_scoreboard end + endfunction + + // FUNCTION: write_fuse_ctrl_core_axi_write_in_agent_ae + // Transactions received through fuse_ctrl_core_axi_write_in_agent_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_fuse_ctrl_core_axi_write_in_agent_ae(fuse_ctrl_core_axi_write_in_transaction t); + // pragma uvmf custom fuse_ctrl_core_axi_write_in_agent_ae_scoreboard begin + `uvm_info("PRED", "Transaction Received through fuse_ctrl_core_axi_write_in_agent_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // UVMF_CHANGE_ME: Implement custom scoreboard here. + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "UVMF_CHANGE_ME: The fuse_ctrl_scoreboard::write_fuse_ctrl_core_axi_write_in_agent_ae function needs to be completed with custom scoreboard functionality",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + + // pragma uvmf custom fuse_ctrl_core_axi_write_in_agent_ae_scoreboard end + endfunction + + // FUNCTION: write_fuse_ctrl_secreg_axi_read_in_agent_ae + // Transactions received through fuse_ctrl_secreg_axi_read_in_agent_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_fuse_ctrl_secreg_axi_read_in_agent_ae(fuse_ctrl_secreg_axi_read_in_transaction t); + // pragma uvmf custom fuse_ctrl_secreg_axi_read_in_agent_ae_scoreboard begin + `uvm_info("PRED", "Transaction Received through fuse_ctrl_secreg_axi_read_in_agent_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // UVMF_CHANGE_ME: Implement custom scoreboard here. + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "UVMF_CHANGE_ME: The fuse_ctrl_scoreboard::write_fuse_ctrl_secreg_axi_read_in_agent_ae function needs to be completed with custom scoreboard functionality",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + + // pragma uvmf custom fuse_ctrl_secreg_axi_read_in_agent_ae_scoreboard end + endfunction + + // FUNCTION: write_fuse_ctrl_prim_axi_write_in_agent_ae + // Transactions received through fuse_ctrl_prim_axi_write_in_agent_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_fuse_ctrl_prim_axi_write_in_agent_ae(fuse_ctrl_prim_axi_write_in_transaction t); + // pragma uvmf custom fuse_ctrl_prim_axi_write_in_agent_ae_scoreboard begin + `uvm_info("PRED", "Transaction Received through fuse_ctrl_prim_axi_write_in_agent_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // UVMF_CHANGE_ME: Implement custom scoreboard here. + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "UVMF_CHANGE_ME: The fuse_ctrl_scoreboard::write_fuse_ctrl_prim_axi_write_in_agent_ae function needs to be completed with custom scoreboard functionality",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + + // pragma uvmf custom fuse_ctrl_prim_axi_write_in_agent_ae_scoreboard end + endfunction + + // FUNCTION: write_fuse_ctrl_in_agent_ae + // Transactions received through fuse_ctrl_in_agent_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_fuse_ctrl_in_agent_ae(fuse_ctrl_in_transaction t); + // pragma uvmf custom fuse_ctrl_in_agent_ae_scoreboard begin + `uvm_info("PRED", "Transaction Received through fuse_ctrl_in_agent_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // UVMF_CHANGE_ME: Implement custom scoreboard here. + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "UVMF_CHANGE_ME: The fuse_ctrl_scoreboard::write_fuse_ctrl_in_agent_ae function needs to be completed with custom scoreboard functionality",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + + // pragma uvmf custom fuse_ctrl_in_agent_ae_scoreboard end + endfunction + + // FUNCTION: write_fuse_ctrl_core_axi_read_in_agent_ae + // Transactions received through fuse_ctrl_core_axi_read_in_agent_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_fuse_ctrl_core_axi_read_in_agent_ae(fuse_ctrl_core_axi_read_in_transaction t); + // pragma uvmf custom fuse_ctrl_core_axi_read_in_agent_ae_scoreboard begin + `uvm_info("PRED", "Transaction Received through fuse_ctrl_core_axi_read_in_agent_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // UVMF_CHANGE_ME: Implement custom scoreboard here. + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "UVMF_CHANGE_ME: The fuse_ctrl_scoreboard::write_fuse_ctrl_core_axi_read_in_agent_ae function needs to be completed with custom scoreboard functionality",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + + // pragma uvmf custom fuse_ctrl_core_axi_read_in_agent_ae_scoreboard end + endfunction + + // FUNCTION: write_fuse_ctrl_prim_axi_read_in_agent_ae + // Transactions received through fuse_ctrl_prim_axi_read_in_agent_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_fuse_ctrl_prim_axi_read_in_agent_ae(fuse_ctrl_prim_axi_read_in_transaction t); + // pragma uvmf custom fuse_ctrl_prim_axi_read_in_agent_ae_scoreboard begin + `uvm_info("PRED", "Transaction Received through fuse_ctrl_prim_axi_read_in_agent_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // UVMF_CHANGE_ME: Implement custom scoreboard here. + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "UVMF_CHANGE_ME: The fuse_ctrl_scoreboard::write_fuse_ctrl_prim_axi_read_in_agent_ae function needs to be completed with custom scoreboard functionality",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + + // pragma uvmf custom fuse_ctrl_prim_axi_read_in_agent_ae_scoreboard end + endfunction + + + + // FUNCTION: extract_phase + virtual function void extract_phase(uvm_phase phase); +// pragma uvmf custom extract_phase begin + super.extract_phase(phase); +// pragma uvmf custom extract_phase end + endfunction + + // FUNCTION: check_phase + virtual function void check_phase(uvm_phase phase); +// pragma uvmf custom check_phase begin + super.check_phase(phase); +// pragma uvmf custom check_phase end + endfunction + + // FUNCTION: report_phase + virtual function void report_phase(uvm_phase phase); +// pragma uvmf custom report_phase begin + super.report_phase(phase); +// pragma uvmf custom report_phase end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/environment_packages/fuse_ctrl_env_pkg/yaml/fuse_ctrl_environment.yaml b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/environment_packages/fuse_ctrl_env_pkg/yaml/fuse_ctrl_environment.yaml new file mode 100644 index 0000000..84226cb --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/environment_packages/fuse_ctrl_env_pkg/yaml/fuse_ctrl_environment.yaml @@ -0,0 +1,116 @@ +uvmf: + environments: + fuse_ctrl: + agents: + - initiator_responder: INITIATOR + name: fuse_ctrl_rst_in_agent + type: fuse_ctrl_rst_in + - initiator_responder: RESPONDER + name: fuse_ctrl_rst_out_agent + type: fuse_ctrl_rst_out + - initiator_responder: INITIATOR + name: fuse_ctrl_core_axi_write_in_if_agent + type: fuse_ctrl_core_axi_write_in + - initiator_responder: RESPONDER + name: fuse_ctrl_core_axi_write_out_if_agent + type: fuse_ctrl_core_axi_write_out + - initiator_responder: INITIATOR + name: fuse_ctrl_prim_axi_write_in_if_agent + type: fuse_ctrl_prim_axi_write_in + - initiator_responder: RESPONDER + name: fuse_ctrl_prim_axi_write_out_if_agent + type: fuse_ctrl_prim_axi_write_out + - initiator_responder: INITIATOR + name: fuse_ctrl_core_axi_read_in_if_agent + type: fuse_ctrl_core_axi_read_in + - initiator_responder: RESPONDER + name: fuse_ctrl_core_axi_read_out_if_agent + type: fuse_ctrl_core_axi_read_out + - initiator_responder: INITIATOR + name: fuse_ctrl_prim_axi_read_in_if_agent + type: fuse_ctrl_prim_axi_read_in + - initiator_responder: RESPONDER + name: fuse_ctrl_prim_axi_read_out_if_agent + type: fuse_ctrl_prim_axi_read_out + - initiator_responder: INITIATOR + name: fuse_ctrl_secreg_axi_read_in_if_agent + type: fuse_ctrl_secreg_axi_read_in + - initiator_responder: RESPONDER + name: fuse_ctrl_secreg_axi_read_out_if_agent + type: fuse_ctrl_secreg_axi_read_out + - initiator_responder: INITIATOR + name: fuse_ctrl_lc_otp_in_if_agent + type: fuse_ctrl_lc_otp_in + - initiator_responder: RESPONDER + name: fuse_ctrl_lc_otp_out_if_agent + type: fuse_ctrl_lc_otp_out + - initiator_responder: INITIATOR + name: fuse_ctrl_in_if_agent + type: fuse_ctrl_in + - initiator_responder: RESPONDER + name: fuse_ctrl_out_if_agent + type: fuse_ctrl_out + analysis_components: + - name: fuse_ctrl_pred + parameters: [] + type: fuse_ctrl_predictor + - name: fuse_ctrl_sb + parameters: [] + type: fuse_ctrl_scoreboard + analysis_exports: [] + analysis_ports: [] + config_constraints: [] + config_vars: [] + existing_library_component: 'True' + hvl_pkg_parameters: [] + non_uvmf_components: [] + parameters: [] + qvip_memory_agents: [] + scoreboards: [] + subenvs: [] + tlm_connections: + - driver: fuse_ctrl_rst_in_agent.monitored_ap + receiver: fuse_ctrl_pred.fuse_ctrl_rst_in_agent_ae + validate: 'True' + - driver: fuse_ctrl_core_axi_write_in_if_agent.monitored_ap + receiver: fuse_ctrl_pred.fuse_ctrl_core_axi_write_in_agent_ae + validate: 'True' + - driver: fuse_ctrl_core_axi_write_out_if_agent.monitored_ap + receiver: fuse_ctrl_sb.fuse_ctrl_core_axi_write_in_agent_ae + validate: 'True' + - driver: fuse_ctrl_core_axi_read_in_if_agent.monitored_ap + receiver: fuse_ctrl_pred.fuse_ctrl_core_axi_read_in_agent_ae + validate: 'True' + - driver: fuse_ctrl_core_axi_read_out_if_agent.monitored_ap + receiver: fuse_ctrl_sb.fuse_ctrl_core_axi_read_in_agent_ae + validate: 'True' + - driver: fuse_ctrl_prim_axi_write_in_if_agent.monitored_ap + receiver: fuse_ctrl_pred.fuse_ctrl_prim_axi_write_in_agent_ae + validate: 'True' + - driver: fuse_ctrl_prim_axi_write_out_if_agent.monitored_ap + receiver: fuse_ctrl_sb.fuse_ctrl_prim_axi_write_in_agent_ae + validate: 'True' + - driver: fuse_ctrl_prim_axi_read_in_if_agent.monitored_ap + receiver: fuse_ctrl_pred.fuse_ctrl_prim_axi_read_in_agent_ae + validate: 'True' + - driver: fuse_ctrl_prim_axi_read_out_if_agent.monitored_ap + receiver: fuse_ctrl_sb.fuse_ctrl_prim_axi_read_in_agent_ae + validate: 'True' + - driver: fuse_ctrl_secreg_axi_read_in_if_agent.monitored_ap + receiver: fuse_ctrl_pred.fuse_ctrl_secreg_axi_read_in_agent_ae + validate: 'True' + - driver: fuse_ctrl_secreg_axi_read_out_if_agent.monitored_ap + receiver: fuse_ctrl_sb.fuse_ctrl_secreg_axi_read_in_agent_ae + validate: 'True' + - driver: fuse_ctrl_lc_otp_in_if_agent.monitored_ap + receiver: fuse_ctrl_pred.fuse_ctrl_lc_otp_in_agent_ae + validate: 'True' + - driver: fuse_ctrl_lc_otp_out_if_agent.monitored_ap + receiver: fuse_ctrl_sb.fuse_ctrl_lc_otp_in_agent_ae + validate: 'True' + - driver: fuse_ctrl_in_if_agent.monitored_ap + receiver: fuse_ctrl_pred.fuse_ctrl_in_agent_ae + validate: 'True' + - driver: fuse_ctrl_out_if_agent.monitored_ap + receiver: fuse_ctrl_sb.fuse_ctrl_in_agent_ae + validate: 'True' diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/environment_packages/fuse_ctrl_env_pkg/yaml/fuse_ctrl_util_comp_fuse_ctrl_predictor.yaml b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/environment_packages/fuse_ctrl_env_pkg/yaml/fuse_ctrl_util_comp_fuse_ctrl_predictor.yaml new file mode 100644 index 0000000..6fc20b8 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/environment_packages/fuse_ctrl_env_pkg/yaml/fuse_ctrl_util_comp_fuse_ctrl_predictor.yaml @@ -0,0 +1,39 @@ +uvmf: + util_components: + fuse_ctrl_predictor: + analysis_exports: + - name: fuse_ctrl_lc_otp_in_agent_ae + type: fuse_ctrl_lc_otp_in_transaction + - name: fuse_ctrl_rst_in_agent_ae + type: fuse_ctrl_rst_in_transaction + - name: fuse_ctrl_core_axi_write_in_agent_ae + type: fuse_ctrl_core_axi_write_in_transaction + - name: fuse_ctrl_secreg_axi_read_in_agent_ae + type: fuse_ctrl_secreg_axi_read_in_transaction + - name: fuse_ctrl_prim_axi_write_in_agent_ae + type: fuse_ctrl_prim_axi_write_in_transaction + - name: fuse_ctrl_in_agent_ae + type: fuse_ctrl_in_transaction + - name: fuse_ctrl_core_axi_read_in_agent_ae + type: fuse_ctrl_core_axi_read_in_transaction + - name: fuse_ctrl_prim_axi_read_in_agent_ae + type: fuse_ctrl_prim_axi_read_in_transaction + analysis_ports: + - name: fuse_ctrl_prim_axi_write_in_agent_ap + type: fuse_ctrl_prim_axi_write_in_transaction + - name: fuse_ctrl_core_axi_read_in_agent_ap + type: fuse_ctrl_core_axi_read_in_transaction + - name: fuse_ctrl_prim_axi_read_in_agent_ap + type: fuse_ctrl_prim_axi_read_in_transaction + - name: fuse_ctrl_in_agent_ap + type: fuse_ctrl_in_transaction + - name: fuse_ctrl_rst_in_agent_ap + type: fuse_ctrl_rst_in_transaction + - name: fuse_ctrl_secreg_axi_read_in_agent_ap + type: fuse_ctrl_secreg_axi_read_in_transaction + - name: fuse_ctrl_core_axi_write_in_agent_ap + type: fuse_ctrl_core_axi_write_in_transaction + - name: fuse_ctrl_lc_otp_in_agent_ap + type: fuse_ctrl_lc_otp_in_transaction + existing_library_component: 'True' + type: predictor diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/environment_packages/fuse_ctrl_env_pkg/yaml/fuse_ctrl_util_comp_fuse_ctrl_scoreboard.yaml b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/environment_packages/fuse_ctrl_env_pkg/yaml/fuse_ctrl_util_comp_fuse_ctrl_scoreboard.yaml new file mode 100644 index 0000000..e645b91 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/environment_packages/fuse_ctrl_env_pkg/yaml/fuse_ctrl_util_comp_fuse_ctrl_scoreboard.yaml @@ -0,0 +1,22 @@ +uvmf: + util_components: + fuse_ctrl_scoreboard: + analysis_exports: + - name: fuse_ctrl_lc_otp_in_agent_ae + type: fuse_ctrl_lc_otp_in_transaction + - name: fuse_ctrl_rst_in_agent_ae + type: fuse_ctrl_rst_in_transaction + - name: fuse_ctrl_core_axi_write_in_agent_ae + type: fuse_ctrl_core_axi_write_in_transaction + - name: fuse_ctrl_secreg_axi_read_in_agent_ae + type: fuse_ctrl_secreg_axi_read_in_transaction + - name: fuse_ctrl_prim_axi_write_in_agent_ae + type: fuse_ctrl_prim_axi_write_in_transaction + - name: fuse_ctrl_in_agent_ae + type: fuse_ctrl_in_transaction + - name: fuse_ctrl_core_axi_read_in_agent_ae + type: fuse_ctrl_core_axi_read_in_transaction + - name: fuse_ctrl_prim_axi_read_in_agent_ae + type: fuse_ctrl_prim_axi_read_in_transaction + existing_library_component: 'True' + type: scoreboard diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/.project b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/.project new file mode 100644 index 0000000..e463bf0 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/.project @@ -0,0 +1,30 @@ + + + fuse_ctrl_core_axi_read_in_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/.svproject b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/.svproject new file mode 100644 index 0000000..4a40ac8 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/Makefile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/Makefile new file mode 100644 index 0000000..0ccd2f8 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/Makefile @@ -0,0 +1,66 @@ +# fuse_ctrl_core_axi_read_in interface packages source +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +fuse_ctrl_core_axi_read_in_PKG = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_read_in_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_filelist_hvl.f + +fuse_ctrl_core_axi_read_in_PKG_HDL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_read_in_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_filelist_hdl.f + +fuse_ctrl_core_axi_read_in_PKG_XRTL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_read_in_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_filelist_xrtl.f + +COMP_fuse_ctrl_core_axi_read_in_PKG_TGT_0 = q_comp_fuse_ctrl_core_axi_read_in_pkg +COMP_fuse_ctrl_core_axi_read_in_PKG_TGT_1 = v_comp_fuse_ctrl_core_axi_read_in_pkg +COMP_fuse_ctrl_core_axi_read_in_PKG_TGT = $(COMP_fuse_ctrl_core_axi_read_in_PKG_TGT_$(USE_VELOCE)) + +comp_fuse_ctrl_core_axi_read_in_pkg: $(COMP_fuse_ctrl_core_axi_read_in_PKG_TGT) + +q_comp_fuse_ctrl_core_axi_read_in_pkg: + $(HDL_COMP_CMD) $(fuse_ctrl_core_axi_read_in_PKG_HDL) + $(HVL_COMP_CMD) $(fuse_ctrl_core_axi_read_in_PKG) + $(HDL_COMP_CMD) $(fuse_ctrl_core_axi_read_in_PKG_XRTL) + +v_comp_fuse_ctrl_core_axi_read_in_pkg: + $(HVL_COMP_CMD) $(fuse_ctrl_core_axi_read_in_PKG_HDL) + $(HVL_COMP_CMD) $(fuse_ctrl_core_axi_read_in_PKG) + $(VELANALYZE_CMD) $(fuse_ctrl_core_axi_read_in_PKG_HDL) + $(VELANALYZE_HVL_CMD) $(fuse_ctrl_core_axi_read_in_PKG) + $(HDL_COMP_CMD) $(fuse_ctrl_core_axi_read_in_PKG_XRTL) + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export fuse_ctrl_core_axi_read_in_IF_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_read_in_pkg/dpi + +C_FILE_COMPILE_LIST_fuse_ctrl_core_axi_read_in_pkg = \ + +O_FILE_COMPILE_LIST_fuse_ctrl_core_axi_read_in_pkg = $(notdir $(C_FILE_COMPILE_LIST_fuse_ctrl_core_axi_read_in_pkg:.c=.o)) + +GCC_COMP_ARGS_fuse_ctrl_core_axi_read_in_pkg += -I$(fuse_ctrl_core_axi_read_in_IF_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_fuse_ctrl_core_axi_read_in_pkg += $(fuse_ctrl_core_axi_read_in_IF_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_fuse_ctrl_core_axi_read_in_pkg += \ + \ + -o .so + +comp_fuse_ctrl_core_axi_read_in_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Interface C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_fuse_ctrl_core_axi_read_in_pkg) $(C_FILE_COMPILE_LIST_fuse_ctrl_core_axi_read_in_pkg) + @echo "--------------------------------" + @echo "Linking Interface C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_fuse_ctrl_core_axi_read_in_pkg) $(O_FILE_COMPILE_LIST_fuse_ctrl_core_axi_read_in_pkg) + @echo "--------------------------------" + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/compile.do b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/compile.do new file mode 100644 index 0000000..badb448 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/compile.do @@ -0,0 +1,14 @@ +# Tcl do file for compile of fuse_ctrl_core_axi_read_in interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_read_in_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_filelist_hdl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_read_in_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_filelist_hvl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_read_in_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_filelist_xrtl.f \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in.compile new file mode 100644 index 0000000..87b941a --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in.compile @@ -0,0 +1,3 @@ +needs: + - fuse_ctrl_core_axi_read_in_hvl.compile + - fuse_ctrl_core_axi_read_in_hdl.compile diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_bfm.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_bfm.vinfo new file mode 100644 index 0000000..5b88121 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_bfm.vinfo @@ -0,0 +1,6 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use fuse_ctrl_core_axi_read_in_pkg_hdl.vinfo ++incdir+@vinfodir +src/fuse_ctrl_core_axi_read_in_if.sv +src/fuse_ctrl_core_axi_read_in_driver_bfm.sv +src/fuse_ctrl_core_axi_read_in_monitor_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_common.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_common.compile new file mode 100644 index 0000000..c150c93 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_common.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +incdir: + - . + - ${uvm_path}/src +src: + - fuse_ctrl_core_axi_read_in_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_filelist_hdl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_filelist_hdl.f new file mode 100644 index 0000000..b5ab5ea --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_filelist_hdl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_filelist_hvl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_filelist_hvl.f new file mode 100644 index 0000000..ea2d101 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_filelist_hvl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_pkg.sv \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_filelist_xrtl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_filelist_xrtl.f new file mode 100644 index 0000000..16c4792 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_filelist_xrtl.f @@ -0,0 +1,3 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_if.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_monitor_bfm.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_driver_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_hdl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_hdl.compile new file mode 100644 index 0000000..96c4c97 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_hdl.compile @@ -0,0 +1,9 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ./fuse_ctrl_core_axi_read_in_common.compile +incdir: + - . +src: + - src/fuse_ctrl_core_axi_read_in_if.sv + - src/fuse_ctrl_core_axi_read_in_monitor_bfm.sv + - src/fuse_ctrl_core_axi_read_in_driver_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_hvl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_hvl.compile new file mode 100644 index 0000000..287ac6a --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_hvl.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ./fuse_ctrl_core_axi_read_in_common.compile +incdir: + - . +src: + - fuse_ctrl_core_axi_read_in_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_pkg.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_pkg.sv new file mode 100644 index 0000000..69c23d8 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_pkg.sv @@ -0,0 +1,91 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - + +// - +// - +// - + +// - +// - +// - + +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_core_axi_read_in_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg_hdl::*; + import uvmf_base_pkg::*; + import fuse_ctrl_core_axi_read_in_pkg_hdl::*; + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + `include "src/fuse_ctrl_core_axi_read_in_macros.svh" + + export fuse_ctrl_core_axi_read_in_pkg_hdl::*; + + + + // Parameters defined as HVL parameters + + `include "src/fuse_ctrl_core_axi_read_in_typedefs.svh" + `include "src/fuse_ctrl_core_axi_read_in_transaction.svh" + + `include "src/fuse_ctrl_core_axi_read_in_configuration.svh" + `include "src/fuse_ctrl_core_axi_read_in_driver.svh" + `include "src/fuse_ctrl_core_axi_read_in_monitor.svh" + + `include "src/fuse_ctrl_core_axi_read_in_transaction_coverage.svh" + `include "src/fuse_ctrl_core_axi_read_in_sequence_base.svh" + `include "src/fuse_ctrl_core_axi_read_in_random_sequence.svh" + + `include "src/fuse_ctrl_core_axi_read_in_responder_sequence.svh" + `include "src/fuse_ctrl_core_axi_read_in2reg_adapter.svh" + + `include "src/fuse_ctrl_core_axi_read_in_agent.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new interface sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the interface package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_pkg.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_pkg.vinfo new file mode 100644 index 0000000..0c3c242 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_pkg.vinfo @@ -0,0 +1,4 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use fuse_ctrl_core_axi_read_in_pkg_hdl.vinfo ++incdir+@vinfodir +fuse_ctrl_core_axi_read_in_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_pkg_hdl.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_pkg_hdl.sv new file mode 100644 index 0000000..2377e24 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_pkg_hdl.sv @@ -0,0 +1,52 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that needs to be compiled and synthesized +// for running on Veloce. +// +// CONTAINS: +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_core_axi_read_in_pkg_hdl; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HDL parameters + + `include "src/fuse_ctrl_core_axi_read_in_typedefs_hdl.svh" + `include "src/fuse_ctrl_core_axi_read_in_macros.svh" + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_pkg_hdl.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_pkg_hdl.vinfo new file mode 100644 index 0000000..ff9df31 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_pkg_hdl.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +fuse_ctrl_core_axi_read_in_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_pkg_sve.F b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_pkg_sve.F new file mode 100644 index 0000000..2a3defa --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_pkg_sve.F @@ -0,0 +1,10 @@ +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + ++incdir+. +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_filelist_hdl.f +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_filelist_hvl.f diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in2reg_adapter.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in2reg_adapter.svh new file mode 100644 index 0000000..378fe6a --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in2reg_adapter.svh @@ -0,0 +1,137 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the UVM register adapter for the fuse_ctrl_core_axi_read_in interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_read_in2reg_adapter #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvm_reg_adapter; + + `uvm_object_param_utils( fuse_ctrl_core_axi_read_in2reg_adapter #( + AW, + DW, + IW, + UW + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //-------------------------------------------------------------------- + // new + //-------------------------------------------------------------------- + function new (string name = "fuse_ctrl_core_axi_read_in2reg_adapter" ); + super.new(name); + // pragma uvmf custom new begin + // UVMF_CHANGE_ME : Configure the adapter regarding byte enables and provides response. + + // Does the protocol the Agent is modeling support byte enables? + // 0 = NO + // 1 = YES + supports_byte_enable = 0; + + // Does the Agent's Driver provide separate response sequence items? + // i.e. Does the driver call seq_item_port.put() + // and do the sequences call get_response()? + // 0 = NO + // 1 = YES + provides_responses = 0; + // pragma uvmf custom new end + + endfunction: new + + //-------------------------------------------------------------------- + // reg2bus + //-------------------------------------------------------------------- + virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw); + + fuse_ctrl_core_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) trans_h = fuse_ctrl_core_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )::type_id::create("trans_h"); + + // pragma uvmf custom reg2bus begin + // UVMF_CHANGE_ME : Fill in the reg2bus adapter mapping registe fields to protocol fields. + + //Adapt the following for your sequence item type + // trans_h.op = (rw.kind == UVM_READ) ? WB_READ : WB_WRITE; + //Copy over address + // trans_h.addr = rw.addr; + //Copy over write data + // trans_h.data = rw.data; + + // pragma uvmf custom reg2bus end + + // Return the adapted transaction + return trans_h; + + endfunction: reg2bus + + //-------------------------------------------------------------------- + // bus2reg + //-------------------------------------------------------------------- + virtual function void bus2reg(uvm_sequence_item bus_item, + ref uvm_reg_bus_op rw); + fuse_ctrl_core_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) trans_h; + if (!$cast(trans_h, bus_item)) begin + `uvm_fatal("ADAPT","Provided bus_item is not of the correct type") + return; + end + // pragma uvmf custom bus2reg begin + // UVMF_CHANGE_ME : Fill in the bus2reg adapter mapping protocol fields to register fields. + //Adapt the following for your sequence item type + //Copy over instruction type + // rw.kind = (trans_h.op == WB_WRITE) ? UVM_WRITE : UVM_READ; + //Copy over address + // rw.addr = trans_h.addr; + //Copy over read data + // rw.data = trans_h.data; + //Check for errors on the bus and return UVM_NOT_OK if there is an error + // rw.status = UVM_IS_OK; + // pragma uvmf custom bus2reg end + + endfunction: bus2reg + +endclass : fuse_ctrl_core_axi_read_in2reg_adapter + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_agent.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_agent.svh new file mode 100644 index 0000000..1ed60ea --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_agent.svh @@ -0,0 +1,102 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: Protocol specific agent class definition +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_read_in_agent #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvmf_parameterized_agent #( + .CONFIG_T(fuse_ctrl_core_axi_read_in_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .DRIVER_T(fuse_ctrl_core_axi_read_in_driver #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .MONITOR_T(fuse_ctrl_core_axi_read_in_monitor #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .COVERAGE_T(fuse_ctrl_core_axi_read_in_transaction_coverage #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .TRANS_T(fuse_ctrl_core_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )) + ); + + `uvm_component_param_utils( fuse_ctrl_core_axi_read_in_agent #( + AW, + DW, + IW, + UW + )) + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** + // FUNCTION: build_phase + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + if (configuration.active_passive == ACTIVE) begin + // Place sequencer handle into configuration object + // so that it may be retrieved from configuration + // rather than using uvm_config_db + configuration.sequencer = this.sequencer; + end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_configuration.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_configuration.svh new file mode 100644 index 0000000..395c11b --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_configuration.svh @@ -0,0 +1,233 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class contains all variables and functions used +// to configure the fuse_ctrl_core_axi_read_in agent and its bfm's. It gets the +// bfm's from the uvm_config_db for use by the agent. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_read_in_configuration #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvmf_parameterized_agent_configuration_base #( + .DRIVER_BFM_BIND_T(virtual fuse_ctrl_core_axi_read_in_driver_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .MONITOR_BFM_BIND_T( virtual fuse_ctrl_core_axi_read_in_monitor_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ))); + + `uvm_object_param_utils( fuse_ctrl_core_axi_read_in_configuration #( + AW, + DW, + IW, + UW + )) + + + // Sequencer handle populated by agent + uvm_sequencer #(fuse_ctrl_core_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) ) sequencer; + + //Constraints for the configuration variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + covergroup fuse_ctrl_core_axi_read_in_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + // pragma uvmf custom covergroup end + endgroup + + //******************************************************************* + //******************************************************************* + // Structure used to pass configuration variables to monitor and driver BFM's. + // Use to_struct function to pack variables into structure. + // Use from_struct function to unpack variables from structure. + // This structure is defined in fuse_ctrl_core_axi_read_in_macros.svh + `fuse_ctrl_core_axi_read_in_CONFIGURATION_STRUCT + fuse_ctrl_core_axi_read_in_configuration_s fuse_ctrl_core_axi_read_in_configuration_struct; + //******************************************************************* + // FUNCTION: to_struct() + // This function packs variables into a fuse_ctrl_core_axi_read_in_configuration_s + // structure. The function returns the handle to the fuse_ctrl_core_axi_read_in_configuration_struct. + // This function is defined in fuse_ctrl_core_axi_read_in_macros.svh + `fuse_ctrl_core_axi_read_in_CONFIGURATION_TO_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_struct() + // This function unpacks the struct provided as an argument into + // variables of this class. + // This function is defined in fuse_ctrl_core_axi_read_in_macros.svh + `fuse_ctrl_core_axi_read_in_CONFIGURATION_FROM_STRUCT_FUNCTION + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + // Construct the covergroup for this configuration class + fuse_ctrl_core_axi_read_in_configuration_cg = new; + endfunction + + // **************************************************************************** + // FUNCTION: post_randomize() + // This function is automatically called after the randomize() function + // is executed. + // + function void post_randomize(); + super.post_randomize(); + fuse_ctrl_core_axi_read_in_configuration_cg.sample(); + endfunction + + // **************************************************************************** + // FUNCTION: initialize + // This function causes the configuration to retrieve + // its virtual interface handle from the uvm_config_db. + // This function also makes itself available to its + // agent through the uvm_config_db. + // + // ARGUMENTS: + // uvmf_active_passive_t activity: + // This argument identifies the simulation level + // as either BLOCK, CHIP, SIMULATION, etc. + // + // AGENT_PATH: + // This argument identifies the path to this + // configurations agent. This configuration + // makes itself available to the agent specified + // by agent_path by placing itself into the + // uvm_config_db. + // + // INTERFACE_NAME: + // This argument identifies the string name of + // this configurations BFM's. This string + // name is used to retrieve the driver and + // monitor BFM from the uvm_config_db. + // + virtual function void initialize(uvmf_active_passive_t activity, + string agent_path, + string interface_name); + + super.initialize( activity, agent_path, interface_name); + // The covergroup is given the same name as the interface + fuse_ctrl_core_axi_read_in_configuration_cg.set_inst_name(interface_name); + + // This configuration places itself into the uvm_config_db for the agent, identified by the agent_path variable, to retrieve. + uvm_config_db #( fuse_ctrl_core_axi_read_in_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + )::set( null ,agent_path,UVMF_AGENT_CONFIG, this ); + + // This configuration also places itself in the config db using the same identifier used by the interface. This allows users to access + // configuration variables and the interface through the bfm api class rather than directly accessing the BFM. This is useful for + // accessingthe BFM when using Veloce + uvm_config_db #( fuse_ctrl_core_axi_read_in_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + )::set( null ,UVMF_CONFIGURATIONS, interface_name, this ); + + fuse_ctrl_core_axi_read_in_configuration_cg.set_inst_name($sformatf("fuse_ctrl_core_axi_read_in_configuration_cg_%s",get_full_name())); + +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. + `uvm_info("CFG", + $psprintf("The agent at '%s' is using interface named %s has the following parameters: AW=%x DW=%x IW=%x UW=%x ", agent_path, interface_name, AW ,DW ,IW ,UW ), + UVM_DEBUG) + + // pragma uvmf custom initialize begin + // This controls whether or not the agent returns a transaction handle in the driver when calling + // item_done() back into the sequencer or not. If set to 1, a transaction is sent back which means + // the sequence on the other end must use the get_response() part of the driver/sequence API. If + // this doesn't occur, there will eventually be response_queue overflow errors during the test. + return_transaction_response = 1'b0; + + // pragma uvmf custom initialize end + + endfunction + + // **************************************************************************** + // TASK: wait_for_reset + // *[Required]* Blocks until reset is released. The wait_for_reset operation is performed + // by a task in the monitor bfm. + virtual task wait_for_reset(); + monitor_bfm.wait_for_reset(); + endtask + + // **************************************************************************** + // TASK: wait_for_num_clocks + // *[Required]* Blocks until specified number of clocks have elapsed. The wait_for_num_clocks + // operation is performed by a task in the monitor bfm. + virtual task wait_for_num_clocks(int clocks); + monitor_bfm.wait_for_num_clocks(clocks); + endtask + + // **************************************************************************** + // FUNCTION : convert2string() + // This function is used to convert variables in this class into a string for log messaging. + // + virtual function string convert2string (); + // pragma uvmf custom convert2string begin + return $sformatf(""); + // pragma uvmf custom convert2string end + endfunction + + // **************************************************************************** + // FUNCTION: get_sequencer + function uvm_sequencer #(fuse_ctrl_core_axi_read_in_transaction#( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )) get_sequencer(); + return sequencer; + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_driver.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_driver.svh new file mode 100644 index 0000000..8aa1c0c --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_driver.svh @@ -0,0 +1,135 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class passes transactions between the sequencer +// and the BFM driver interface. It accesses the driver BFM +// through the bfm handle. This driver +// passes transactions to the driver BFM through the access +// task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_read_in_driver #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvmf_driver_base #( + .CONFIG_T(fuse_ctrl_core_axi_read_in_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) ), + .BFM_BIND_T(virtual fuse_ctrl_core_axi_read_in_driver_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) ), + .REQ(fuse_ctrl_core_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) ), + .RSP(fuse_ctrl_core_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) )); + + `uvm_component_param_utils( fuse_ctrl_core_axi_read_in_driver #( + AW, + DW, + IW, + UW + )) +//******************************************************************* +// Macros that define structs located in fuse_ctrl_core_axi_read_in_macros.svh +//******************************************************************* +// Initiator macro used by fuse_ctrl_core_axi_read_in_driver and fuse_ctrl_core_axi_read_in_driver_bfm +// to communicate initiator driven data to fuse_ctrl_core_axi_read_in_driver_bfm. +`fuse_ctrl_core_axi_read_in_INITIATOR_STRUCT + fuse_ctrl_core_axi_read_in_initiator_s fuse_ctrl_core_axi_read_in_initiator_struct; +//******************************************************************* +// Responder macro used by fuse_ctrl_core_axi_read_in_driver and fuse_ctrl_core_axi_read_in_driver_bfm +// to communicate Responder driven data to fuse_ctrl_core_axi_read_in_driver_bfm. +`fuse_ctrl_core_axi_read_in_RESPONDER_STRUCT + fuse_ctrl_core_axi_read_in_responder_s fuse_ctrl_core_axi_read_in_responder_struct; + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent=null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the driver BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// driver BFM. This allows the driver BFM to call tasks and function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// **************************************************************************** +// This task is called by the run_phase in uvmf_driver_base. + virtual task access( inout REQ txn ); +// pragma uvmf custom access begin + if (configuration.initiator_responder==RESPONDER) begin + // Complete current transfer and wait for next transfer + bfm.respond_and_wait_for_next_transfer( + fuse_ctrl_core_axi_read_in_initiator_struct, + txn.to_responder_struct() + ); + // Unpack information about initiated transfer received by this responder + txn.from_initiator_struct(fuse_ctrl_core_axi_read_in_initiator_struct); + end else begin + // Initiate a transfer and get response + bfm.initiate_and_get_response( + txn.to_initiator_struct(), + fuse_ctrl_core_axi_read_in_responder_struct + ); + // Unpack transfer response information received by this initiator + txn.from_responder_struct(fuse_ctrl_core_axi_read_in_responder_struct); + end +// pragma uvmf custom access end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_driver_bfm.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_driver_bfm.sv new file mode 100644 index 0000000..548dff9 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_driver_bfm.sv @@ -0,0 +1,383 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This interface performs the fuse_ctrl_core_axi_read_in signal driving. It is +// accessed by the uvm fuse_ctrl_core_axi_read_in driver through a virtual interface +// handle in the fuse_ctrl_core_axi_read_in configuration. It drives the singals passed +// in through the port connection named bus of type fuse_ctrl_core_axi_read_in_if. +// +// Input signals from the fuse_ctrl_core_axi_read_in_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// This bfm drives signals with a _o suffix. These signals +// are driven onto signals within fuse_ctrl_core_axi_read_in_if based on INITIATOR/RESPONDER and/or +// ARBITRATION/GRANT status. +// +// The output signal connections are as follows: +// signal_o -> bus.signal +// +// +// Interface functions and tasks used by UVM components: +// +// configure: +// This function gets configuration attributes from the +// UVM driver to set any required BFM configuration +// variables such as 'initiator_responder'. +// +// initiate_and_get_response: +// This task is used to perform signaling activity for initiating +// a protocol transfer. The task initiates the transfer, using +// input data from the initiator struct. Then the task captures +// response data, placing the data into the response struct. +// The response struct is returned to the driver class. +// +// respond_and_wait_for_next_transfer: +// This task is used to complete a current transfer as a responder +// and then wait for the initiator to start the next transfer. +// The task uses data in the responder struct to drive protocol +// signals to complete the transfer. The task then waits for +// the next transfer. Once the next transfer begins, data from +// the initiator is placed into the initiator struct and sent +// to the responder sequence for processing to determine +// what data to respond with. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_core_axi_read_in_pkg_hdl::*; +`include "src/fuse_ctrl_core_axi_read_in_macros.svh" + +interface fuse_ctrl_core_axi_read_in_driver_bfm #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + (fuse_ctrl_core_axi_read_in_if bus); + // The following pragma and additional ones in-lined further below are for running this BFM on Veloce + // pragma attribute fuse_ctrl_core_axi_read_in_driver_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: AW=%x DW=%x IW=%x UW=%x ", AW,DW,IW,UW), + UVM_DEBUG) +end +`endif + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + tri clk_i_i; + tri rst_ni_i; + + // Signal list (all signals are capable of being inputs and outputs for the sake + // of supporting both INITIATOR and RESPONDER mode operation. Expectation is that + // directionality in the config file was from the point-of-view of the INITIATOR + + // INITIATOR mode input signals + + // INITIATOR mode output signals + tri [AW-1:0] araddr_i; + reg [AW-1:0] araddr_o = 'bz; + tri [$bits(axi_pkg::axi_burst_e)-1:0] arburst_i; + reg [$bits(axi_pkg::axi_burst_e)-1:0] arburst_o = 'bz; + tri [2:0] arsize_i; + reg [2:0] arsize_o = 'bz; + tri [7:0] arlen_i; + reg [7:0] arlen_o = 'bz; + tri [UW-1:0] aruser_i; + reg [UW-1:0] aruser_o = 'bz; + tri [IW-1:0] arid_i; + reg [IW-1:0] arid_o = 'bz; + tri arlock_i; + reg arlock_o = 'bz; + tri arvalid_i; + reg arvalid_o = 'bz; + tri rready_i; + reg rready_o = 'bz; + + // Bi-directional signals + + + assign clk_i_i = bus.clk_i; + assign rst_ni_i = bus.rst_ni; + + // These are signals marked as 'input' by the config file, but the signals will be + // driven by this BFM if put into RESPONDER mode (flipping all signal directions around) + + + // These are signals marked as 'output' by the config file, but the outputs will + // not be driven by this BFM unless placed in INITIATOR mode. + assign bus.araddr = (initiator_responder == INITIATOR) ? araddr_o : 'bz; + assign araddr_i = bus.araddr; + assign bus.arburst = (initiator_responder == INITIATOR) ? arburst_o : 'bz; + assign arburst_i = bus.arburst; + assign bus.arsize = (initiator_responder == INITIATOR) ? arsize_o : 'bz; + assign arsize_i = bus.arsize; + assign bus.arlen = (initiator_responder == INITIATOR) ? arlen_o : 'bz; + assign arlen_i = bus.arlen; + assign bus.aruser = (initiator_responder == INITIATOR) ? aruser_o : 'bz; + assign aruser_i = bus.aruser; + assign bus.arid = (initiator_responder == INITIATOR) ? arid_o : 'bz; + assign arid_i = bus.arid; + assign bus.arlock = (initiator_responder == INITIATOR) ? arlock_o : 'bz; + assign arlock_i = bus.arlock; + assign bus.arvalid = (initiator_responder == INITIATOR) ? arvalid_o : 'bz; + assign arvalid_i = bus.arvalid; + assign bus.rready = (initiator_responder == INITIATOR) ? rready_o : 'bz; + assign rready_i = bus.rready; + + // Proxy handle to UVM driver + fuse_ctrl_core_axi_read_in_pkg::fuse_ctrl_core_axi_read_in_driver #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) proxy; + // pragma tbx oneway proxy.my_function_name_in_uvm_driver + + // **************************************************************************** + // **************************************************************************** + // Macros that define structs located in fuse_ctrl_core_axi_read_in_macros.svh + // **************************************************************************** + // Struct for passing configuration data from fuse_ctrl_core_axi_read_in_driver to this BFM + // **************************************************************************** + `fuse_ctrl_core_axi_read_in_CONFIGURATION_STRUCT + // **************************************************************************** + // Structs for INITIATOR and RESPONDER data flow + //******************************************************************* + // Initiator macro used by fuse_ctrl_core_axi_read_in_driver and fuse_ctrl_core_axi_read_in_driver_bfm + // to communicate initiator driven data to fuse_ctrl_core_axi_read_in_driver_bfm. + `fuse_ctrl_core_axi_read_in_INITIATOR_STRUCT + fuse_ctrl_core_axi_read_in_initiator_s initiator_struct; + // Responder macro used by fuse_ctrl_core_axi_read_in_driver and fuse_ctrl_core_axi_read_in_driver_bfm + // to communicate Responder driven data to fuse_ctrl_core_axi_read_in_driver_bfm. + `fuse_ctrl_core_axi_read_in_RESPONDER_STRUCT + fuse_ctrl_core_axi_read_in_responder_s responder_struct; + + // **************************************************************************** +// pragma uvmf custom reset_condition_and_response begin + // Always block used to return signals to reset value upon assertion of reset + always @( negedge rst_ni_i ) + begin + // RESPONDER mode output signals + // INITIATOR mode output signals + araddr_o <= 'bz; + arburst_o <= 'bz; + arsize_o <= 'bz; + arlen_o <= 'bz; + aruser_o <= 'bz; + arid_o <= 'bz; + arlock_o <= 'bz; + arvalid_o <= 'bz; + rready_o <= 'bz; + // Bi-directional signals + + end +// pragma uvmf custom reset_condition_and_response end + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the driver BFM. It is called by the driver within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the driver BFM needs to be aware of the new configuration + // variables. + // + + function void configure(fuse_ctrl_core_axi_read_in_configuration_s fuse_ctrl_core_axi_read_in_configuration_arg); // pragma tbx xtf + initiator_responder = fuse_ctrl_core_axi_read_in_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + +// pragma uvmf custom initiate_and_get_response begin +// **************************************************************************** +// UVMF_CHANGE_ME +// This task is used by an initator. The task first initiates a transfer then +// waits for the responder to complete the transfer. + task initiate_and_get_response( + // This argument passes transaction variables used by an initiator + // to perform the initial part of a protocol transfer. The values + // come from a sequence item created in a sequence. + input fuse_ctrl_core_axi_read_in_initiator_s fuse_ctrl_core_axi_read_in_initiator_struct, + // This argument is used to send data received from the responder + // back to the sequence item. The sequence item is returned to the sequence. + output fuse_ctrl_core_axi_read_in_responder_s fuse_ctrl_core_axi_read_in_responder_struct + );// pragma tbx xtf + // + // Members within the fuse_ctrl_core_axi_read_in_initiator_struct: + // logic [AW-1:0] core_araddr ; + // logic core_arvalid ; + // logic [$bits(axi_pkg::axi_burst_e)] core_arburst ; + // logic [2:0] core_arsize ; + // logic [7:0] core_arlen ; + // logic [UW-1:0] core_aruser ; + // logic [IW-1:0] core_arid ; + // logic core_arlock ; + // logic core_rready ; + // Members within the fuse_ctrl_core_axi_read_in_responder_struct: + // logic [AW-1:0] core_araddr ; + // logic core_arvalid ; + // logic [$bits(axi_pkg::axi_burst_e)] core_arburst ; + // logic [2:0] core_arsize ; + // logic [7:0] core_arlen ; + // logic [UW-1:0] core_aruser ; + // logic [IW-1:0] core_arid ; + // logic core_arlock ; + // logic core_rready ; + initiator_struct = fuse_ctrl_core_axi_read_in_initiator_struct; + // + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clk_i_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available initiator input and inout signals listed. + // Initiator input signals + // Initiator inout signals + // How to assign a signal from an initiator struct member named xyz. + // All available initiator output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Initiator output signals + // araddr_o <= fuse_ctrl_core_axi_read_in_initiator_struct.xyz; // [AW-1:0] + // arburst_o <= fuse_ctrl_core_axi_read_in_initiator_struct.xyz; // [$bits(axi_pkg::axi_burst_e)-1:0] + // arsize_o <= fuse_ctrl_core_axi_read_in_initiator_struct.xyz; // [2:0] + // arlen_o <= fuse_ctrl_core_axi_read_in_initiator_struct.xyz; // [7:0] + // aruser_o <= fuse_ctrl_core_axi_read_in_initiator_struct.xyz; // [UW-1:0] + // arid_o <= fuse_ctrl_core_axi_read_in_initiator_struct.xyz; // [IW-1:0] + // arlock_o <= fuse_ctrl_core_axi_read_in_initiator_struct.xyz; // + // arvalid_o <= fuse_ctrl_core_axi_read_in_initiator_struct.xyz; // + // rready_o <= fuse_ctrl_core_axi_read_in_initiator_struct.xyz; // + // Initiator inout signals + // Initiate a transfer using the data received. + @(posedge clk_i_i); + @(posedge clk_i_i); + // Wait for the responder to complete the transfer then place the responder data into + // fuse_ctrl_core_axi_read_in_responder_struct. + @(posedge clk_i_i); + @(posedge clk_i_i); + responder_struct = fuse_ctrl_core_axi_read_in_responder_struct; + endtask +// pragma uvmf custom initiate_and_get_response end + +// pragma uvmf custom respond_and_wait_for_next_transfer begin +// **************************************************************************** +// The first_transfer variable is used to prevent completing a transfer in the +// first call to this task. For the first call to this task, there is not +// current transfer to complete. +bit first_transfer=1; + +// UVMF_CHANGE_ME +// This task is used by a responder. The task first completes the current +// transfer in progress then waits for the initiator to start the next transfer. + task respond_and_wait_for_next_transfer( + // This argument is used to send data received from the initiator + // back to the sequence item. The sequence determines how to respond. + output fuse_ctrl_core_axi_read_in_initiator_s fuse_ctrl_core_axi_read_in_initiator_struct, + // This argument passes transaction variables used by a responder + // to complete a protocol transfer. The values come from a sequence item. + input fuse_ctrl_core_axi_read_in_responder_s fuse_ctrl_core_axi_read_in_responder_struct + );// pragma tbx xtf + // Variables within the fuse_ctrl_core_axi_read_in_initiator_struct: + // logic [AW-1:0] core_araddr ; + // logic core_arvalid ; + // logic [$bits(axi_pkg::axi_burst_e)] core_arburst ; + // logic [2:0] core_arsize ; + // logic [7:0] core_arlen ; + // logic [UW-1:0] core_aruser ; + // logic [IW-1:0] core_arid ; + // logic core_arlock ; + // logic core_rready ; + // Variables within the fuse_ctrl_core_axi_read_in_responder_struct: + // logic [AW-1:0] core_araddr ; + // logic core_arvalid ; + // logic [$bits(axi_pkg::axi_burst_e)] core_arburst ; + // logic [2:0] core_arsize ; + // logic [7:0] core_arlen ; + // logic [UW-1:0] core_aruser ; + // logic [IW-1:0] core_arid ; + // logic core_arlock ; + // logic core_rready ; + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clk_i_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available responder input and inout signals listed. + // Responder input signals + // fuse_ctrl_core_axi_read_in_responder_struct.xyz = araddr_i; // [AW-1:0] + // fuse_ctrl_core_axi_read_in_responder_struct.xyz = arburst_i; // [$bits(axi_pkg::axi_burst_e)-1:0] + // fuse_ctrl_core_axi_read_in_responder_struct.xyz = arsize_i; // [2:0] + // fuse_ctrl_core_axi_read_in_responder_struct.xyz = arlen_i; // [7:0] + // fuse_ctrl_core_axi_read_in_responder_struct.xyz = aruser_i; // [UW-1:0] + // fuse_ctrl_core_axi_read_in_responder_struct.xyz = arid_i; // [IW-1:0] + // fuse_ctrl_core_axi_read_in_responder_struct.xyz = arlock_i; // + // fuse_ctrl_core_axi_read_in_responder_struct.xyz = arvalid_i; // + // fuse_ctrl_core_axi_read_in_responder_struct.xyz = rready_i; // + // Responder inout signals + // How to assign a signal, named xyz, from an initiator struct member. + // All available responder output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Responder output signals + // Responder inout signals + + @(posedge clk_i_i); + if (!first_transfer) begin + // Perform transfer response here. + // Reply using data recieved in the fuse_ctrl_core_axi_read_in_responder_struct. + @(posedge clk_i_i); + // Reply using data recieved in the transaction handle. + @(posedge clk_i_i); + end + // Wait for next transfer then gather info from intiator about the transfer. + // Place the data into the fuse_ctrl_core_axi_read_in_initiator_struct. + @(posedge clk_i_i); + @(posedge clk_i_i); + first_transfer = 0; + endtask +// pragma uvmf custom respond_and_wait_for_next_transfer end + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_if.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_if.sv new file mode 100644 index 0000000..c14953d --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_if.sv @@ -0,0 +1,123 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface contains the fuse_ctrl_core_axi_read_in interface signals. +// It is instantiated once per fuse_ctrl_core_axi_read_in bus. Bus Functional Models, +// BFM's named fuse_ctrl_core_axi_read_in_driver_bfm, are used to drive signals on the bus. +// BFM's named fuse_ctrl_core_axi_read_in_monitor_bfm are used to monitor signals on the +// bus. This interface signal bundle is passed in the port list of +// the BFM in order to give the BFM access to the signals in this +// interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// This template can be used to connect a DUT to these signals +// +// .dut_signal_port(fuse_ctrl_core_axi_read_in_bus.araddr), // Agent output +// .dut_signal_port(fuse_ctrl_core_axi_read_in_bus.arburst), // Agent output +// .dut_signal_port(fuse_ctrl_core_axi_read_in_bus.arsize), // Agent output +// .dut_signal_port(fuse_ctrl_core_axi_read_in_bus.arlen), // Agent output +// .dut_signal_port(fuse_ctrl_core_axi_read_in_bus.aruser), // Agent output +// .dut_signal_port(fuse_ctrl_core_axi_read_in_bus.arid), // Agent output +// .dut_signal_port(fuse_ctrl_core_axi_read_in_bus.arlock), // Agent output +// .dut_signal_port(fuse_ctrl_core_axi_read_in_bus.arvalid), // Agent output +// .dut_signal_port(fuse_ctrl_core_axi_read_in_bus.rready), // Agent output + +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_core_axi_read_in_pkg_hdl::*; + +interface fuse_ctrl_core_axi_read_in_if #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + + ( + input tri clk_i, + input tri rst_ni, + inout tri [AW-1:0] araddr, + inout tri [$bits(axi_pkg::axi_burst_e)-1:0] arburst, + inout tri [2:0] arsize, + inout tri [7:0] arlen, + inout tri [UW-1:0] aruser, + inout tri [IW-1:0] arid, + inout tri arlock, + inout tri arvalid, + inout tri rready + ); + +modport monitor_port + ( + input clk_i, + input rst_ni, + input araddr, + input arburst, + input arsize, + input arlen, + input aruser, + input arid, + input arlock, + input arvalid, + input rready + ); + +modport initiator_port + ( + input clk_i, + input rst_ni, + output araddr, + output arburst, + output arsize, + output arlen, + output aruser, + output arid, + output arlock, + output arvalid, + output rready + ); + +modport responder_port + ( + input clk_i, + input rst_ni, + input araddr, + input arburst, + input arsize, + input arlen, + input aruser, + input arid, + input arlock, + input arvalid, + input rready + ); + + +// pragma uvmf custom interface_item_additional begin +// pragma uvmf custom interface_item_additional end + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_infact_coverage_strategy.csv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_infact_coverage_strategy.csv new file mode 100644 index 0000000..1c218e1 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_infact_coverage_strategy.csv @@ -0,0 +1,6 @@ +Global +auto_bin_max, 64 + +Name,Type,Include +rand_fields,coverpoint,=rand *.** + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_macros.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_macros.svh new file mode 100644 index 0000000..4ada88f --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_macros.svh @@ -0,0 +1,207 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains macros used with the fuse_ctrl_core_axi_read_in package. +// These macros include packed struct definitions. These structs are +// used to pass data between classes, hvl, and BFM's, hdl. Use of +// structs are more efficient and simpler to modify. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_struct +// and from_struct methods defined in the macros below that are used in +// the fuse_ctrl_core_axi_read_in_configuration class. +// + `define fuse_ctrl_core_axi_read_in_CONFIGURATION_STRUCT \ +typedef struct packed { \ + uvmf_active_passive_t active_passive; \ + uvmf_initiator_responder_t initiator_responder; \ + } fuse_ctrl_core_axi_read_in_configuration_s; + + `define fuse_ctrl_core_axi_read_in_CONFIGURATION_TO_STRUCT_FUNCTION \ + virtual function fuse_ctrl_core_axi_read_in_configuration_s to_struct();\ + fuse_ctrl_core_axi_read_in_configuration_struct = \ + {\ + this.active_passive,\ + this.initiator_responder\ + };\ + return ( fuse_ctrl_core_axi_read_in_configuration_struct );\ + endfunction + + `define fuse_ctrl_core_axi_read_in_CONFIGURATION_FROM_STRUCT_FUNCTION \ + virtual function void from_struct(fuse_ctrl_core_axi_read_in_configuration_s fuse_ctrl_core_axi_read_in_configuration_struct);\ + {\ + this.active_passive,\ + this.initiator_responder \ + } = fuse_ctrl_core_axi_read_in_configuration_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_monitor_struct +// and from_monitor_struct methods of the fuse_ctrl_core_axi_read_in_transaction class. +// + `define fuse_ctrl_core_axi_read_in_MONITOR_STRUCT typedef struct packed { \ + logic [AW-1:0] core_araddr ; \ + logic core_arvalid ; \ + logic [$bits(axi_pkg::axi_burst_e)] core_arburst ; \ + logic [2:0] core_arsize ; \ + logic [7:0] core_arlen ; \ + logic [UW-1:0] core_aruser ; \ + logic [IW-1:0] core_arid ; \ + logic core_arlock ; \ + logic core_rready ; \ + } fuse_ctrl_core_axi_read_in_monitor_s; + + `define fuse_ctrl_core_axi_read_in_TO_MONITOR_STRUCT_FUNCTION \ + virtual function fuse_ctrl_core_axi_read_in_monitor_s to_monitor_struct();\ + fuse_ctrl_core_axi_read_in_monitor_struct = \ + { \ + this.core_araddr , \ + this.core_arvalid , \ + this.core_arburst , \ + this.core_arsize , \ + this.core_arlen , \ + this.core_aruser , \ + this.core_arid , \ + this.core_arlock , \ + this.core_rready \ + };\ + return ( fuse_ctrl_core_axi_read_in_monitor_struct);\ + endfunction\ + + `define fuse_ctrl_core_axi_read_in_FROM_MONITOR_STRUCT_FUNCTION \ + virtual function void from_monitor_struct(fuse_ctrl_core_axi_read_in_monitor_s fuse_ctrl_core_axi_read_in_monitor_struct);\ + {\ + this.core_araddr , \ + this.core_arvalid , \ + this.core_arburst , \ + this.core_arsize , \ + this.core_arlen , \ + this.core_aruser , \ + this.core_arid , \ + this.core_arlock , \ + this.core_rready \ + } = fuse_ctrl_core_axi_read_in_monitor_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_initiator_struct +// and from_initiator_struct methods of the fuse_ctrl_core_axi_read_in_transaction class. +// Also update the comments in the driver BFM. +// + `define fuse_ctrl_core_axi_read_in_INITIATOR_STRUCT typedef struct packed { \ + logic [AW-1:0] core_araddr ; \ + logic core_arvalid ; \ + logic [$bits(axi_pkg::axi_burst_e)] core_arburst ; \ + logic [2:0] core_arsize ; \ + logic [7:0] core_arlen ; \ + logic [UW-1:0] core_aruser ; \ + logic [IW-1:0] core_arid ; \ + logic core_arlock ; \ + logic core_rready ; \ + } fuse_ctrl_core_axi_read_in_initiator_s; + + `define fuse_ctrl_core_axi_read_in_TO_INITIATOR_STRUCT_FUNCTION \ + virtual function fuse_ctrl_core_axi_read_in_initiator_s to_initiator_struct();\ + fuse_ctrl_core_axi_read_in_initiator_struct = \ + {\ + this.core_araddr , \ + this.core_arvalid , \ + this.core_arburst , \ + this.core_arsize , \ + this.core_arlen , \ + this.core_aruser , \ + this.core_arid , \ + this.core_arlock , \ + this.core_rready \ + };\ + return ( fuse_ctrl_core_axi_read_in_initiator_struct);\ + endfunction + + `define fuse_ctrl_core_axi_read_in_FROM_INITIATOR_STRUCT_FUNCTION \ + virtual function void from_initiator_struct(fuse_ctrl_core_axi_read_in_initiator_s fuse_ctrl_core_axi_read_in_initiator_struct);\ + {\ + this.core_araddr , \ + this.core_arvalid , \ + this.core_arburst , \ + this.core_arsize , \ + this.core_arlen , \ + this.core_aruser , \ + this.core_arid , \ + this.core_arlock , \ + this.core_rready \ + } = fuse_ctrl_core_axi_read_in_initiator_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_responder_struct +// and from_responder_struct methods of the fuse_ctrl_core_axi_read_in_transaction class. +// Also update the comments in the driver BFM. +// + `define fuse_ctrl_core_axi_read_in_RESPONDER_STRUCT typedef struct packed { \ + logic [AW-1:0] core_araddr ; \ + logic core_arvalid ; \ + logic [$bits(axi_pkg::axi_burst_e)] core_arburst ; \ + logic [2:0] core_arsize ; \ + logic [7:0] core_arlen ; \ + logic [UW-1:0] core_aruser ; \ + logic [IW-1:0] core_arid ; \ + logic core_arlock ; \ + logic core_rready ; \ + } fuse_ctrl_core_axi_read_in_responder_s; + + `define fuse_ctrl_core_axi_read_in_TO_RESPONDER_STRUCT_FUNCTION \ + virtual function fuse_ctrl_core_axi_read_in_responder_s to_responder_struct();\ + fuse_ctrl_core_axi_read_in_responder_struct = \ + {\ + this.core_araddr , \ + this.core_arvalid , \ + this.core_arburst , \ + this.core_arsize , \ + this.core_arlen , \ + this.core_aruser , \ + this.core_arid , \ + this.core_arlock , \ + this.core_rready \ + };\ + return ( fuse_ctrl_core_axi_read_in_responder_struct);\ + endfunction + + `define fuse_ctrl_core_axi_read_in_FROM_RESPONDER_STRUCT_FUNCTION \ + virtual function void from_responder_struct(fuse_ctrl_core_axi_read_in_responder_s fuse_ctrl_core_axi_read_in_responder_struct);\ + {\ + this.core_araddr , \ + this.core_arvalid , \ + this.core_arburst , \ + this.core_arsize , \ + this.core_arlen , \ + this.core_aruser , \ + this.core_arid , \ + this.core_arlock , \ + this.core_rready \ + } = fuse_ctrl_core_axi_read_in_responder_struct;\ + endfunction +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_monitor.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_monitor.svh new file mode 100644 index 0000000..eab0f2f --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_monitor.svh @@ -0,0 +1,126 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class receives fuse_ctrl_core_axi_read_in transactions observed by the +// fuse_ctrl_core_axi_read_in monitor BFM and broadcasts them through the analysis port +// on the agent. It accesses the monitor BFM through the monitor +// task. This UVM component captures transactions +// for viewing in the waveform viewer if the +// enable_transaction_viewing flag is set in the configuration. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_read_in_monitor #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvmf_monitor_base #( + .CONFIG_T(fuse_ctrl_core_axi_read_in_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .BFM_BIND_T(virtual fuse_ctrl_core_axi_read_in_monitor_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .TRANS_T(fuse_ctrl_core_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ))); + + `uvm_component_param_utils( fuse_ctrl_core_axi_read_in_monitor #( + AW, + DW, + IW, + UW + )) + +// Structure used to pass data from monitor BFM to monitor class in agent. +// Use to_monitor_struct function to pack transaction variables into structure. +// Use from_monitor_struct function to unpack transaction variables from structure. +`fuse_ctrl_core_axi_read_in_MONITOR_STRUCT + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the monitor BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// monitor BFM. This allows the monitor BFM to call the notify_transaction +// function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// *************************************************************************** + virtual task run_phase(uvm_phase phase); + // Start monitor BFM thread and don't call super.run() in order to + // override the default monitor proxy 'pull' behavior with the more + // emulation-friendly BFM 'push' approach using the notify_transaction + // function below + bfm.start_monitoring(); + endtask + +// ************************************************************************** + +// This function is called by the monitor BFM. It receives data observed by the +// monitor BFM. Data is passed using the fuse_ctrl_core_axi_read_in_monitor_struct. + virtual function void notify_transaction(input fuse_ctrl_core_axi_read_in_monitor_s fuse_ctrl_core_axi_read_in_monitor_struct); + + + trans = new("trans"); + trans.from_monitor_struct(fuse_ctrl_core_axi_read_in_monitor_struct); + trans.start_time = time_stamp; + trans.end_time = $time; + time_stamp = trans.end_time; + + analyze(trans); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_monitor_bfm.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_monitor_bfm.sv new file mode 100644 index 0000000..9819fd5 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_monitor_bfm.sv @@ -0,0 +1,230 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface performs the fuse_ctrl_core_axi_read_in signal monitoring. +// It is accessed by the uvm fuse_ctrl_core_axi_read_in monitor through a virtual +// interface handle in the fuse_ctrl_core_axi_read_in configuration. It monitors the +// signals passed in through the port connection named bus of +// type fuse_ctrl_core_axi_read_in_if. +// +// Input signals from the fuse_ctrl_core_axi_read_in_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// Interface functions and tasks used by UVM components: +// monitor(inout TRANS_T txn); +// This task receives the transaction, txn, from the +// UVM monitor and then populates variables in txn +// from values observed on bus activity. This task +// blocks until an operation on the fuse_ctrl_core_axi_read_in bus is complete. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_core_axi_read_in_pkg_hdl::*; +`include "src/fuse_ctrl_core_axi_read_in_macros.svh" + + +interface fuse_ctrl_core_axi_read_in_monitor_bfm #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + ( fuse_ctrl_core_axi_read_in_if bus ); + // The pragma below and additional ones in-lined further down are for running this BFM on Veloce + // pragma attribute fuse_ctrl_core_axi_read_in_monitor_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: AW=%x DW=%x IW=%x UW=%x ", AW,DW,IW,UW), + UVM_DEBUG) +end +`endif + + + // Structure used to pass transaction data from monitor BFM to monitor class in agent. +`fuse_ctrl_core_axi_read_in_MONITOR_STRUCT + fuse_ctrl_core_axi_read_in_monitor_s fuse_ctrl_core_axi_read_in_monitor_struct; + + // Structure used to pass configuration data from monitor class to monitor BFM. + `fuse_ctrl_core_axi_read_in_CONFIGURATION_STRUCT + + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + tri clk_i_i; + tri rst_ni_i; + tri [AW-1:0] araddr_i; + tri [$bits(axi_pkg::axi_burst_e)-1:0] arburst_i; + tri [2:0] arsize_i; + tri [7:0] arlen_i; + tri [UW-1:0] aruser_i; + tri [IW-1:0] arid_i; + tri arlock_i; + tri arvalid_i; + tri rready_i; + assign clk_i_i = bus.clk_i; + assign rst_ni_i = bus.rst_ni; + assign araddr_i = bus.araddr; + assign arburst_i = bus.arburst; + assign arsize_i = bus.arsize; + assign arlen_i = bus.arlen; + assign aruser_i = bus.aruser; + assign arid_i = bus.arid; + assign arlock_i = bus.arlock; + assign arvalid_i = bus.arvalid; + assign rready_i = bus.rready; + + // Proxy handle to UVM monitor + fuse_ctrl_core_axi_read_in_pkg::fuse_ctrl_core_axi_read_in_monitor #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) proxy; + // pragma tbx oneway proxy.notify_transaction + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + task wait_for_reset();// pragma tbx xtf + @(posedge clk_i_i) ; + do_wait_for_reset(); + endtask + + // **************************************************************************** + task do_wait_for_reset(); + // pragma uvmf custom reset_condition begin + wait ( rst_ni_i === 1 ) ; + @(posedge clk_i_i) ; + // pragma uvmf custom reset_condition end + endtask + + //****************************************************************** + + task wait_for_num_clocks(input int unsigned count); // pragma tbx xtf + @(posedge clk_i_i); + + repeat (count-1) @(posedge clk_i_i); + endtask + + //****************************************************************** + event go; + function void start_monitoring();// pragma tbx xtf + -> go; + endfunction + + // **************************************************************************** + initial begin + @go; + forever begin + @(posedge clk_i_i); + do_monitor( fuse_ctrl_core_axi_read_in_monitor_struct ); + + + proxy.notify_transaction( fuse_ctrl_core_axi_read_in_monitor_struct ); + + end + end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the monitor BFM. It is called by the monitor within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the monitor BFM needs to be aware of the new configuration + // variables. + // + function void configure(fuse_ctrl_core_axi_read_in_configuration_s fuse_ctrl_core_axi_read_in_configuration_arg); // pragma tbx xtf + initiator_responder = fuse_ctrl_core_axi_read_in_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + + + // **************************************************************************** + + task do_monitor(output fuse_ctrl_core_axi_read_in_monitor_s fuse_ctrl_core_axi_read_in_monitor_struct); + // + // Available struct members: + // // fuse_ctrl_core_axi_read_in_monitor_struct.core_araddr + // // fuse_ctrl_core_axi_read_in_monitor_struct.core_arvalid + // // fuse_ctrl_core_axi_read_in_monitor_struct.core_arburst + // // fuse_ctrl_core_axi_read_in_monitor_struct.core_arsize + // // fuse_ctrl_core_axi_read_in_monitor_struct.core_arlen + // // fuse_ctrl_core_axi_read_in_monitor_struct.core_aruser + // // fuse_ctrl_core_axi_read_in_monitor_struct.core_arid + // // fuse_ctrl_core_axi_read_in_monitor_struct.core_arlock + // // fuse_ctrl_core_axi_read_in_monitor_struct.core_rready + // // + // Reference code; + // How to wait for signal value + // while (control_signal === 1'b1) @(posedge clk_i_i); + // + // How to assign a struct member, named xyz, from a signal. + // All available input signals listed. + // fuse_ctrl_core_axi_read_in_monitor_struct.xyz = araddr_i; // [AW-1:0] + // fuse_ctrl_core_axi_read_in_monitor_struct.xyz = arburst_i; // [$bits(axi_pkg::axi_burst_e)-1:0] + // fuse_ctrl_core_axi_read_in_monitor_struct.xyz = arsize_i; // [2:0] + // fuse_ctrl_core_axi_read_in_monitor_struct.xyz = arlen_i; // [7:0] + // fuse_ctrl_core_axi_read_in_monitor_struct.xyz = aruser_i; // [UW-1:0] + // fuse_ctrl_core_axi_read_in_monitor_struct.xyz = arid_i; // [IW-1:0] + // fuse_ctrl_core_axi_read_in_monitor_struct.xyz = arlock_i; // + // fuse_ctrl_core_axi_read_in_monitor_struct.xyz = arvalid_i; // + // fuse_ctrl_core_axi_read_in_monitor_struct.xyz = rready_i; // + // pragma uvmf custom do_monitor begin + // UVMF_CHANGE_ME : Implement protocol monitoring. The commented reference code + // below are examples of how to capture signal values and assign them to + // structure members. All available input signals are listed. The 'while' + // code example shows how to wait for a synchronous flow control signal. This + // task should return when a complete transfer has been observed. Once this task is + // exited with captured values, it is then called again to wait for and observe + // the next transfer. One clock cycle is consumed between calls to do_monitor. + @(posedge clk_i_i); + @(posedge clk_i_i); + @(posedge clk_i_i); + @(posedge clk_i_i); + // pragma uvmf custom do_monitor end + endtask + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_random_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_random_sequence.svh new file mode 100644 index 0000000..790d7a8 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_random_sequence.svh @@ -0,0 +1,87 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This sequences randomizes the fuse_ctrl_core_axi_read_in transaction and sends it +// to the UVM driver. +// +// This sequence constructs and randomizes a fuse_ctrl_core_axi_read_in_transaction. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_read_in_random_sequence #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends fuse_ctrl_core_axi_read_in_sequence_base #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ); + + `uvm_object_param_utils( fuse_ctrl_core_axi_read_in_random_sequence #( + AW, + DW, + IW, + UW + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //***************************************************************** + function new(string name = ""); + super.new(name); + endfunction: new + + // **************************************************************************** + // TASK : body() + // This task is automatically executed when this sequence is started using the + // start(sequencerHandle) task. + // + task body(); + + // Construct the transaction + req=fuse_ctrl_core_axi_read_in_transaction#( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )::type_id::create("req"); + start_item(req); + // Randomize the transaction + if(!req.randomize()) `uvm_fatal("SEQ", "fuse_ctrl_core_axi_read_in_random_sequence::body()-fuse_ctrl_core_axi_read_in_transaction randomization failed") + // Send the transaction to the fuse_ctrl_core_axi_read_in_driver_bfm via the sequencer and fuse_ctrl_core_axi_read_in_driver. + finish_item(req); + `uvm_info("SEQ", {"Response:",req.convert2string()},UVM_MEDIUM) + + endtask + +endclass: fuse_ctrl_core_axi_read_in_random_sequence + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_responder_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_responder_sequence.svh new file mode 100644 index 0000000..9e72dab --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_responder_sequence.svh @@ -0,0 +1,83 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class can be used to provide stimulus when an interface +// has been configured to run in a responder mode. It +// will never finish by default, always going back to the driver +// and driver BFM for the next transaction with which to respond. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_read_in_responder_sequence #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends fuse_ctrl_core_axi_read_in_sequence_base #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ); + + `uvm_object_param_utils( fuse_ctrl_core_axi_read_in_responder_sequence #( + AW, + DW, + IW, + UW + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "fuse_ctrl_core_axi_read_in_responder_sequence"); + super.new(name); + endfunction + + task body(); + req=fuse_ctrl_core_axi_read_in_transaction#( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )::type_id::create("req"); + forever begin + start_item(req); + finish_item(req); + // pragma uvmf custom body begin + // UVMF_CHANGE_ME : Do something here with the resulting req item. The + // finish_item() call above will block until the req transaction is ready + // to be handled by the responder sequence. + // If this was an item that required a response, the expectation is + // that the response should be populated within this transaction now. + `uvm_info("SEQ",$sformatf("Processed txn: %s",req.convert2string()),UVM_HIGH) + // pragma uvmf custom body end + end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_sequence_base.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_sequence_base.svh new file mode 100644 index 0000000..efaac03 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_sequence_base.svh @@ -0,0 +1,140 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the class used as the base class for all sequences +// for this interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_read_in_sequence_base #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvmf_sequence_base #( + .REQ(fuse_ctrl_core_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .RSP(fuse_ctrl_core_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ))); + + `uvm_object_param_utils( fuse_ctrl_core_axi_read_in_sequence_base #( + AW, + DW, + IW, + UW + )) + + // variables + typedef fuse_ctrl_core_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) fuse_ctrl_core_axi_read_in_transaction_req_t; + fuse_ctrl_core_axi_read_in_transaction_req_t req; + typedef fuse_ctrl_core_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) fuse_ctrl_core_axi_read_in_transaction_rsp_t; + fuse_ctrl_core_axi_read_in_transaction_rsp_t rsp; + + // Event for identifying when a response was received from the sequencer + event new_rsp; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // TASK : get_responses() + // This task recursively gets sequence item responses from the sequencer. + // + virtual task get_responses(); + fork + begin + // Block until new rsp available + get_response(rsp); + // New rsp received. Indicate to sequence using event. + ->new_rsp; + // Display the received response transaction + `uvm_info("SEQ", {"New response transaction:",rsp.convert2string()}, UVM_MEDIUM) + end + join_none + endtask + + // **************************************************************************** + // TASK : pre_body() + // This task is called automatically when start is called with call_pre_post set to 1 (default). + // By calling get_responses() within pre_body() any derived sequences are automatically + // processing response transactions. Only un-comment this call to get_responses() if you + // have configured the interface driver to utilize the response transaction path by setting + // the configuration variable "return_transaction_response" to 1. Otherwise it is possible + // to impact runtime performance and memory utilization. + // + virtual task pre_body(); + // pragma uvmf custom pre_body begin +// get_responses(); + // pragma uvmf custom pre_body end + endtask + + // **************************************************************************** + // TASK : body() + // This task is called automatically when start is called. This sequence sends + // a req sequence item to the sequencer identified as an argument in the call + // to start. + // + virtual task body(); + // pragma uvmf custom body begin + start_item(req); + finish_item(req); + // pragma uvmf custom body end + endtask + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name =""); + super.new( name ); + // pragma uvmf custom new begin + req = fuse_ctrl_core_axi_read_in_transaction_req_t::type_id::create("req"); + rsp = fuse_ctrl_core_axi_read_in_transaction_rsp_t::type_id::create("rsp"); + // pragma uvmf custom new end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_transaction.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_transaction.svh new file mode 100644 index 0000000..440d724 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_transaction.svh @@ -0,0 +1,239 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class defines the variables required for an fuse_ctrl_core_axi_read_in +// transaction. Class variables to be displayed in waveform transaction +// viewing are added to the transaction viewing stream in the add_to_wave +// function. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_read_in_transaction #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvmf_transaction_base; + + `uvm_object_param_utils( fuse_ctrl_core_axi_read_in_transaction #( + AW, + DW, + IW, + UW + )) + + rand logic [AW-1:0] core_araddr ; + logic core_arvalid ; + logic [$bits(axi_pkg::axi_burst_e)] core_arburst ; + logic [2:0] core_arsize ; + logic [7:0] core_arlen ; + logic [UW-1:0] core_aruser ; + logic [IW-1:0] core_arid ; + logic core_arlock ; + logic core_rready ; + + //Constraints for the transaction variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //******************************************************************* + //******************************************************************* + // Macros that define structs and associated functions are + // located in fuse_ctrl_core_axi_read_in_macros.svh + + //******************************************************************* + // Monitor macro used by fuse_ctrl_core_axi_read_in_monitor and fuse_ctrl_core_axi_read_in_monitor_bfm + // This struct is defined in fuse_ctrl_core_axi_read_in_macros.svh + `fuse_ctrl_core_axi_read_in_MONITOR_STRUCT + fuse_ctrl_core_axi_read_in_monitor_s fuse_ctrl_core_axi_read_in_monitor_struct; + //******************************************************************* + // FUNCTION: to_monitor_struct() + // This function packs transaction variables into a fuse_ctrl_core_axi_read_in_monitor_s + // structure. The function returns the handle to the fuse_ctrl_core_axi_read_in_monitor_struct. + // This function is defined in fuse_ctrl_core_axi_read_in_macros.svh + `fuse_ctrl_core_axi_read_in_TO_MONITOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_monitor_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_core_axi_read_in_macros.svh + `fuse_ctrl_core_axi_read_in_FROM_MONITOR_STRUCT_FUNCTION + + //******************************************************************* + // Initiator macro used by fuse_ctrl_core_axi_read_in_driver and fuse_ctrl_core_axi_read_in_driver_bfm + // to communicate initiator driven data to fuse_ctrl_core_axi_read_in_driver_bfm. + // This struct is defined in fuse_ctrl_core_axi_read_in_macros.svh + `fuse_ctrl_core_axi_read_in_INITIATOR_STRUCT + fuse_ctrl_core_axi_read_in_initiator_s fuse_ctrl_core_axi_read_in_initiator_struct; + //******************************************************************* + // FUNCTION: to_initiator_struct() + // This function packs transaction variables into a fuse_ctrl_core_axi_read_in_initiator_s + // structure. The function returns the handle to the fuse_ctrl_core_axi_read_in_initiator_struct. + // This function is defined in fuse_ctrl_core_axi_read_in_macros.svh + `fuse_ctrl_core_axi_read_in_TO_INITIATOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_initiator_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_core_axi_read_in_macros.svh + `fuse_ctrl_core_axi_read_in_FROM_INITIATOR_STRUCT_FUNCTION + + //******************************************************************* + // Responder macro used by fuse_ctrl_core_axi_read_in_driver and fuse_ctrl_core_axi_read_in_driver_bfm + // to communicate Responder driven data to fuse_ctrl_core_axi_read_in_driver_bfm. + // This struct is defined in fuse_ctrl_core_axi_read_in_macros.svh + `fuse_ctrl_core_axi_read_in_RESPONDER_STRUCT + fuse_ctrl_core_axi_read_in_responder_s fuse_ctrl_core_axi_read_in_responder_struct; + //******************************************************************* + // FUNCTION: to_responder_struct() + // This function packs transaction variables into a fuse_ctrl_core_axi_read_in_responder_s + // structure. The function returns the handle to the fuse_ctrl_core_axi_read_in_responder_struct. + // This function is defined in fuse_ctrl_core_axi_read_in_macros.svh + `fuse_ctrl_core_axi_read_in_TO_RESPONDER_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_responder_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_core_axi_read_in_macros.svh + `fuse_ctrl_core_axi_read_in_FROM_RESPONDER_STRUCT_FUNCTION + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + endfunction + + // **************************************************************************** + // FUNCTION: convert2string() + // This function converts all variables in this class to a single string for + // logfile reporting. + // + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + // UVMF_CHANGE_ME : Customize format if desired. + return $sformatf("core_araddr:0x%x core_arvalid:0x%x core_arburst:0x%x core_arsize:0x%x core_arlen:0x%x core_aruser:0x%x core_arid:0x%x core_arlock:0x%x core_rready:0x%x ",core_araddr,core_arvalid,core_arburst,core_arsize,core_arlen,core_aruser,core_arid,core_arlock,core_rready); + // pragma uvmf custom convert2string end + endfunction + + //******************************************************************* + // FUNCTION: do_print() + // This function is automatically called when the .print() function + // is called on this class. + // + virtual function void do_print(uvm_printer printer); + // pragma uvmf custom do_print begin + // UVMF_CHANGE_ME : Current contents of do_print allows for the use of UVM 1.1d, 1.2 or P1800.2. + // Update based on your own printing preference according to your preferred UVM version + $display(convert2string()); + // pragma uvmf custom do_print end + endfunction + + //******************************************************************* + // FUNCTION: do_compare() + // This function is automatically called when the .compare() function + // is called on this class. + // + virtual function bit do_compare (uvm_object rhs, uvm_comparer comparer); + fuse_ctrl_core_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) RHS; + if (!$cast(RHS,rhs)) return 0; + // pragma uvmf custom do_compare begin + // UVMF_CHANGE_ME : Eliminate comparison of variables not to be used for compare + return (super.do_compare(rhs,comparer) + ); + // pragma uvmf custom do_compare end + endfunction + + //******************************************************************* + // FUNCTION: do_copy() + // This function is automatically called when the .copy() function + // is called on this class. + // + virtual function void do_copy (uvm_object rhs); + fuse_ctrl_core_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) RHS; + assert($cast(RHS,rhs)); + // pragma uvmf custom do_copy begin + super.do_copy(rhs); + this.core_araddr = RHS.core_araddr; + this.core_arvalid = RHS.core_arvalid; + this.core_arburst = RHS.core_arburst; + this.core_arsize = RHS.core_arsize; + this.core_arlen = RHS.core_arlen; + this.core_aruser = RHS.core_aruser; + this.core_arid = RHS.core_arid; + this.core_arlock = RHS.core_arlock; + this.core_rready = RHS.core_rready; + // pragma uvmf custom do_copy end + endfunction + + // **************************************************************************** + // FUNCTION: add_to_wave() + // This function is used to display variables in this class in the waveform + // viewer. The start_time and end_time variables must be set before this + // function is called. If the start_time and end_time variables are not set + // the transaction will be hidden at 0ns on the waveform display. + // + virtual function void add_to_wave(int transaction_viewing_stream_h); + `ifdef QUESTA + if (transaction_view_h == 0) begin + transaction_view_h = $begin_transaction(transaction_viewing_stream_h,"fuse_ctrl_core_axi_read_in_transaction",start_time); + end + super.add_to_wave(transaction_view_h); + // pragma uvmf custom add_to_wave begin + // UVMF_CHANGE_ME : Color can be applied to transaction entries based on content, example below + // case() + // 1 : $add_color(transaction_view_h,"red"); + // default : $add_color(transaction_view_h,"grey"); + // endcase + // UVMF_CHANGE_ME : Eliminate transaction variables not wanted in transaction viewing in the waveform viewer + $add_attribute(transaction_view_h,core_araddr,"core_araddr"); + $add_attribute(transaction_view_h,core_arvalid,"core_arvalid"); + $add_attribute(transaction_view_h,core_arburst,"core_arburst"); + $add_attribute(transaction_view_h,core_arsize,"core_arsize"); + $add_attribute(transaction_view_h,core_arlen,"core_arlen"); + $add_attribute(transaction_view_h,core_aruser,"core_aruser"); + $add_attribute(transaction_view_h,core_arid,"core_arid"); + $add_attribute(transaction_view_h,core_arlock,"core_arlock"); + $add_attribute(transaction_view_h,core_rready,"core_rready"); + // pragma uvmf custom add_to_wave end + $end_transaction(transaction_view_h,end_time); + $free_transaction(transaction_view_h); + `endif // QUESTA + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_transaction_coverage.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_transaction_coverage.svh new file mode 100644 index 0000000..2a3ba75 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_transaction_coverage.svh @@ -0,0 +1,107 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class records fuse_ctrl_core_axi_read_in transaction information using +// a covergroup named fuse_ctrl_core_axi_read_in_transaction_cg. An instance of this +// coverage component is instantiated in the uvmf_parameterized_agent +// if the has_coverage flag is set. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_read_in_transaction_coverage #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvm_subscriber #(.T(fuse_ctrl_core_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ))); + + `uvm_component_param_utils( fuse_ctrl_core_axi_read_in_transaction_coverage #( + AW, + DW, + IW, + UW + )) + + T coverage_trans; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + covergroup fuse_ctrl_core_axi_read_in_transaction_cg; + // pragma uvmf custom covergroup begin + // UVMF_CHANGE_ME : Add coverage bins, crosses, exclusions, etc. according to coverage needs. + option.auto_bin_max=1024; + option.per_instance=1; + core_araddr: coverpoint coverage_trans.core_araddr; + core_arvalid: coverpoint coverage_trans.core_arvalid; + core_arburst: coverpoint coverage_trans.core_arburst; + core_arsize: coverpoint coverage_trans.core_arsize; + core_arlen: coverpoint coverage_trans.core_arlen; + core_aruser: coverpoint coverage_trans.core_aruser; + core_arid: coverpoint coverage_trans.core_arid; + core_arlock: coverpoint coverage_trans.core_arlock; + core_rready: coverpoint coverage_trans.core_rready; + // pragma uvmf custom covergroup end + endgroup + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new(string name="", uvm_component parent=null); + super.new(name,parent); + fuse_ctrl_core_axi_read_in_transaction_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that transaction variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + endfunction + + // **************************************************************************** + // FUNCTION : build_phase() + // This function is the standard UVM build_phase. + // + function void build_phase(uvm_phase phase); + fuse_ctrl_core_axi_read_in_transaction_cg.set_inst_name($sformatf("fuse_ctrl_core_axi_read_in_transaction_cg_%s",get_full_name())); + endfunction + + // **************************************************************************** + // FUNCTION: write (T t) + // This function is automatically executed when a transaction arrives on the + // analysis_export. It copies values from the variables in the transaction + // to local variables used to collect functional coverage. + // + virtual function void write (T t); + `uvm_info("COV","Received transaction",UVM_HIGH); + coverage_trans = t; + fuse_ctrl_core_axi_read_in_transaction_cg.sample(); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_typedefs.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_typedefs.svh new file mode 100644 index 0000000..f2a7bdb --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_typedefs.svh @@ -0,0 +1,34 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the host server when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_typedefs_hdl.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_typedefs_hdl.svh new file mode 100644 index 0000000..0d58518 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_typedefs_hdl.svh @@ -0,0 +1,35 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the emulator when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/yaml/fuse_ctrl_core_axi_read_in_interface.yaml b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/yaml/fuse_ctrl_core_axi_read_in_interface.yaml new file mode 100644 index 0000000..85b8443 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/yaml/fuse_ctrl_core_axi_read_in_interface.yaml @@ -0,0 +1,121 @@ +uvmf: + interfaces: + fuse_ctrl_core_axi_read_in: + clock: clk_i + config_constraints: [] + config_vars: [] + existing_library_component: 'True' + gen_inbound_streaming_driver: 'False' + hdl_pkg_parameters: [] + hdl_typedefs: [] + hvl_pkg_parameters: [] + hvl_typedefs: [] + parameters: + - name: AW + type: int + value: '32' + - name: DW + type: int + value: '32' + - name: IW + type: int + value: '3' + - name: UW + type: int + value: '32' + ports: + - dir: output + name: araddr + reset_value: '''bz' + width: '[''AW'']' + - dir: output + name: arburst + reset_value: '''bz' + width: '[''$bits(axi_pkg::axi_burst_e)'']' + - dir: output + name: arsize + reset_value: '''bz' + width: '3' + - dir: output + name: arlen + reset_value: '''bz' + width: '8' + - dir: output + name: aruser + reset_value: '''bz' + width: '[''UW'']' + - dir: output + name: arid + reset_value: '''bz' + width: '[''IW'']' + - dir: output + name: arlock + reset_value: '''bz' + width: '1' + - dir: output + name: arvalid + reset_value: '''bz' + width: '1' + - dir: output + name: rready + reset_value: '''bz' + width: '1' + reset: rst_ni + reset_assertion_level: 'False' + transaction_constraints: [] + transaction_vars: + - comment: '' + iscompare: 'False' + isrand: 'True' + name: core_araddr + type: logic [AW-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: core_arvalid + type: logic + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: core_arburst + type: logic [$bits(axi_pkg::axi_burst_e)] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: core_arsize + type: logic [2:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: core_arlen + type: logic [7:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: core_aruser + type: logic [UW-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: core_arid + type: logic [IW-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: core_arlock + type: logic + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: core_rready + type: logic + unpacked_dimension: '' + use_dpi_link: 'False' diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/.project b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/.project new file mode 100644 index 0000000..23723dd --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/.project @@ -0,0 +1,30 @@ + + + fuse_ctrl_core_axi_read_out_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/.svproject b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/.svproject new file mode 100644 index 0000000..b74d826 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/Makefile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/Makefile new file mode 100644 index 0000000..673e00d --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/Makefile @@ -0,0 +1,66 @@ +# fuse_ctrl_core_axi_read_out interface packages source +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +fuse_ctrl_core_axi_read_out_PKG = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_read_out_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_filelist_hvl.f + +fuse_ctrl_core_axi_read_out_PKG_HDL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_read_out_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_filelist_hdl.f + +fuse_ctrl_core_axi_read_out_PKG_XRTL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_read_out_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_filelist_xrtl.f + +COMP_fuse_ctrl_core_axi_read_out_PKG_TGT_0 = q_comp_fuse_ctrl_core_axi_read_out_pkg +COMP_fuse_ctrl_core_axi_read_out_PKG_TGT_1 = v_comp_fuse_ctrl_core_axi_read_out_pkg +COMP_fuse_ctrl_core_axi_read_out_PKG_TGT = $(COMP_fuse_ctrl_core_axi_read_out_PKG_TGT_$(USE_VELOCE)) + +comp_fuse_ctrl_core_axi_read_out_pkg: $(COMP_fuse_ctrl_core_axi_read_out_PKG_TGT) + +q_comp_fuse_ctrl_core_axi_read_out_pkg: + $(HDL_COMP_CMD) $(fuse_ctrl_core_axi_read_out_PKG_HDL) + $(HVL_COMP_CMD) $(fuse_ctrl_core_axi_read_out_PKG) + $(HDL_COMP_CMD) $(fuse_ctrl_core_axi_read_out_PKG_XRTL) + +v_comp_fuse_ctrl_core_axi_read_out_pkg: + $(HVL_COMP_CMD) $(fuse_ctrl_core_axi_read_out_PKG_HDL) + $(HVL_COMP_CMD) $(fuse_ctrl_core_axi_read_out_PKG) + $(VELANALYZE_CMD) $(fuse_ctrl_core_axi_read_out_PKG_HDL) + $(VELANALYZE_HVL_CMD) $(fuse_ctrl_core_axi_read_out_PKG) + $(HDL_COMP_CMD) $(fuse_ctrl_core_axi_read_out_PKG_XRTL) + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export fuse_ctrl_core_axi_read_out_IF_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_read_out_pkg/dpi + +C_FILE_COMPILE_LIST_fuse_ctrl_core_axi_read_out_pkg = \ + +O_FILE_COMPILE_LIST_fuse_ctrl_core_axi_read_out_pkg = $(notdir $(C_FILE_COMPILE_LIST_fuse_ctrl_core_axi_read_out_pkg:.c=.o)) + +GCC_COMP_ARGS_fuse_ctrl_core_axi_read_out_pkg += -I$(fuse_ctrl_core_axi_read_out_IF_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_fuse_ctrl_core_axi_read_out_pkg += $(fuse_ctrl_core_axi_read_out_IF_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_fuse_ctrl_core_axi_read_out_pkg += \ + \ + -o .so + +comp_fuse_ctrl_core_axi_read_out_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Interface C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_fuse_ctrl_core_axi_read_out_pkg) $(C_FILE_COMPILE_LIST_fuse_ctrl_core_axi_read_out_pkg) + @echo "--------------------------------" + @echo "Linking Interface C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_fuse_ctrl_core_axi_read_out_pkg) $(O_FILE_COMPILE_LIST_fuse_ctrl_core_axi_read_out_pkg) + @echo "--------------------------------" + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/compile.do b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/compile.do new file mode 100644 index 0000000..5e6a9fd --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/compile.do @@ -0,0 +1,14 @@ +# Tcl do file for compile of fuse_ctrl_core_axi_read_out interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_read_out_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_filelist_hdl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_read_out_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_filelist_hvl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_read_out_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_filelist_xrtl.f \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out.compile new file mode 100644 index 0000000..ad96a80 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out.compile @@ -0,0 +1,3 @@ +needs: + - fuse_ctrl_core_axi_read_out_hvl.compile + - fuse_ctrl_core_axi_read_out_hdl.compile diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_bfm.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_bfm.vinfo new file mode 100644 index 0000000..03fc49a --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_bfm.vinfo @@ -0,0 +1,6 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use fuse_ctrl_core_axi_read_out_pkg_hdl.vinfo ++incdir+@vinfodir +src/fuse_ctrl_core_axi_read_out_if.sv +src/fuse_ctrl_core_axi_read_out_driver_bfm.sv +src/fuse_ctrl_core_axi_read_out_monitor_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_common.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_common.compile new file mode 100644 index 0000000..84d4f2e --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_common.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +incdir: + - . + - ${uvm_path}/src +src: + - fuse_ctrl_core_axi_read_out_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_filelist_hdl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_filelist_hdl.f new file mode 100644 index 0000000..2debd1c --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_filelist_hdl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_filelist_hvl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_filelist_hvl.f new file mode 100644 index 0000000..8e9b75a --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_filelist_hvl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_pkg.sv \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_filelist_xrtl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_filelist_xrtl.f new file mode 100644 index 0000000..4b0eaa2 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_filelist_xrtl.f @@ -0,0 +1,3 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_if.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_monitor_bfm.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_driver_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_hdl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_hdl.compile new file mode 100644 index 0000000..5b16e75 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_hdl.compile @@ -0,0 +1,9 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ./fuse_ctrl_core_axi_read_out_common.compile +incdir: + - . +src: + - src/fuse_ctrl_core_axi_read_out_if.sv + - src/fuse_ctrl_core_axi_read_out_monitor_bfm.sv + - src/fuse_ctrl_core_axi_read_out_driver_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_hvl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_hvl.compile new file mode 100644 index 0000000..a240210 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_hvl.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ./fuse_ctrl_core_axi_read_out_common.compile +incdir: + - . +src: + - fuse_ctrl_core_axi_read_out_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_pkg.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_pkg.sv new file mode 100644 index 0000000..d297db4 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_pkg.sv @@ -0,0 +1,91 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - + +// - +// - +// - + +// - +// - +// - + +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_core_axi_read_out_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg_hdl::*; + import uvmf_base_pkg::*; + import fuse_ctrl_core_axi_read_out_pkg_hdl::*; + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + `include "src/fuse_ctrl_core_axi_read_out_macros.svh" + + export fuse_ctrl_core_axi_read_out_pkg_hdl::*; + + + + // Parameters defined as HVL parameters + + `include "src/fuse_ctrl_core_axi_read_out_typedefs.svh" + `include "src/fuse_ctrl_core_axi_read_out_transaction.svh" + + `include "src/fuse_ctrl_core_axi_read_out_configuration.svh" + `include "src/fuse_ctrl_core_axi_read_out_driver.svh" + `include "src/fuse_ctrl_core_axi_read_out_monitor.svh" + + `include "src/fuse_ctrl_core_axi_read_out_transaction_coverage.svh" + `include "src/fuse_ctrl_core_axi_read_out_sequence_base.svh" + `include "src/fuse_ctrl_core_axi_read_out_random_sequence.svh" + + `include "src/fuse_ctrl_core_axi_read_out_responder_sequence.svh" + `include "src/fuse_ctrl_core_axi_read_out2reg_adapter.svh" + + `include "src/fuse_ctrl_core_axi_read_out_agent.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new interface sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the interface package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_pkg.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_pkg.vinfo new file mode 100644 index 0000000..50e86c0 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_pkg.vinfo @@ -0,0 +1,4 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use fuse_ctrl_core_axi_read_out_pkg_hdl.vinfo ++incdir+@vinfodir +fuse_ctrl_core_axi_read_out_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_pkg_hdl.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_pkg_hdl.sv new file mode 100644 index 0000000..0e4cd58 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_pkg_hdl.sv @@ -0,0 +1,52 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that needs to be compiled and synthesized +// for running on Veloce. +// +// CONTAINS: +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_core_axi_read_out_pkg_hdl; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HDL parameters + + `include "src/fuse_ctrl_core_axi_read_out_typedefs_hdl.svh" + `include "src/fuse_ctrl_core_axi_read_out_macros.svh" + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_pkg_hdl.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_pkg_hdl.vinfo new file mode 100644 index 0000000..b7569b9 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_pkg_hdl.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +fuse_ctrl_core_axi_read_out_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_pkg_sve.F b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_pkg_sve.F new file mode 100644 index 0000000..531457d --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_pkg_sve.F @@ -0,0 +1,10 @@ +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + ++incdir+. +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_filelist_hdl.f +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_filelist_hvl.f diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out2reg_adapter.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out2reg_adapter.svh new file mode 100644 index 0000000..125c5be --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out2reg_adapter.svh @@ -0,0 +1,137 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the UVM register adapter for the fuse_ctrl_core_axi_read_out interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_read_out2reg_adapter #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvm_reg_adapter; + + `uvm_object_param_utils( fuse_ctrl_core_axi_read_out2reg_adapter #( + AW, + DW, + IW, + UW + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //-------------------------------------------------------------------- + // new + //-------------------------------------------------------------------- + function new (string name = "fuse_ctrl_core_axi_read_out2reg_adapter" ); + super.new(name); + // pragma uvmf custom new begin + // UVMF_CHANGE_ME : Configure the adapter regarding byte enables and provides response. + + // Does the protocol the Agent is modeling support byte enables? + // 0 = NO + // 1 = YES + supports_byte_enable = 0; + + // Does the Agent's Driver provide separate response sequence items? + // i.e. Does the driver call seq_item_port.put() + // and do the sequences call get_response()? + // 0 = NO + // 1 = YES + provides_responses = 0; + // pragma uvmf custom new end + + endfunction: new + + //-------------------------------------------------------------------- + // reg2bus + //-------------------------------------------------------------------- + virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw); + + fuse_ctrl_core_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) trans_h = fuse_ctrl_core_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )::type_id::create("trans_h"); + + // pragma uvmf custom reg2bus begin + // UVMF_CHANGE_ME : Fill in the reg2bus adapter mapping registe fields to protocol fields. + + //Adapt the following for your sequence item type + // trans_h.op = (rw.kind == UVM_READ) ? WB_READ : WB_WRITE; + //Copy over address + // trans_h.addr = rw.addr; + //Copy over write data + // trans_h.data = rw.data; + + // pragma uvmf custom reg2bus end + + // Return the adapted transaction + return trans_h; + + endfunction: reg2bus + + //-------------------------------------------------------------------- + // bus2reg + //-------------------------------------------------------------------- + virtual function void bus2reg(uvm_sequence_item bus_item, + ref uvm_reg_bus_op rw); + fuse_ctrl_core_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) trans_h; + if (!$cast(trans_h, bus_item)) begin + `uvm_fatal("ADAPT","Provided bus_item is not of the correct type") + return; + end + // pragma uvmf custom bus2reg begin + // UVMF_CHANGE_ME : Fill in the bus2reg adapter mapping protocol fields to register fields. + //Adapt the following for your sequence item type + //Copy over instruction type + // rw.kind = (trans_h.op == WB_WRITE) ? UVM_WRITE : UVM_READ; + //Copy over address + // rw.addr = trans_h.addr; + //Copy over read data + // rw.data = trans_h.data; + //Check for errors on the bus and return UVM_NOT_OK if there is an error + // rw.status = UVM_IS_OK; + // pragma uvmf custom bus2reg end + + endfunction: bus2reg + +endclass : fuse_ctrl_core_axi_read_out2reg_adapter + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_agent.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_agent.svh new file mode 100644 index 0000000..bada90f --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_agent.svh @@ -0,0 +1,102 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: Protocol specific agent class definition +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_read_out_agent #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvmf_parameterized_agent #( + .CONFIG_T(fuse_ctrl_core_axi_read_out_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .DRIVER_T(fuse_ctrl_core_axi_read_out_driver #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .MONITOR_T(fuse_ctrl_core_axi_read_out_monitor #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .COVERAGE_T(fuse_ctrl_core_axi_read_out_transaction_coverage #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .TRANS_T(fuse_ctrl_core_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )) + ); + + `uvm_component_param_utils( fuse_ctrl_core_axi_read_out_agent #( + AW, + DW, + IW, + UW + )) + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** + // FUNCTION: build_phase + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + if (configuration.active_passive == ACTIVE) begin + // Place sequencer handle into configuration object + // so that it may be retrieved from configuration + // rather than using uvm_config_db + configuration.sequencer = this.sequencer; + end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_configuration.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_configuration.svh new file mode 100644 index 0000000..6f61e3b --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_configuration.svh @@ -0,0 +1,233 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class contains all variables and functions used +// to configure the fuse_ctrl_core_axi_read_out agent and its bfm's. It gets the +// bfm's from the uvm_config_db for use by the agent. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_read_out_configuration #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvmf_parameterized_agent_configuration_base #( + .DRIVER_BFM_BIND_T(virtual fuse_ctrl_core_axi_read_out_driver_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .MONITOR_BFM_BIND_T( virtual fuse_ctrl_core_axi_read_out_monitor_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ))); + + `uvm_object_param_utils( fuse_ctrl_core_axi_read_out_configuration #( + AW, + DW, + IW, + UW + )) + + + // Sequencer handle populated by agent + uvm_sequencer #(fuse_ctrl_core_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) ) sequencer; + + //Constraints for the configuration variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + covergroup fuse_ctrl_core_axi_read_out_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + // pragma uvmf custom covergroup end + endgroup + + //******************************************************************* + //******************************************************************* + // Structure used to pass configuration variables to monitor and driver BFM's. + // Use to_struct function to pack variables into structure. + // Use from_struct function to unpack variables from structure. + // This structure is defined in fuse_ctrl_core_axi_read_out_macros.svh + `fuse_ctrl_core_axi_read_out_CONFIGURATION_STRUCT + fuse_ctrl_core_axi_read_out_configuration_s fuse_ctrl_core_axi_read_out_configuration_struct; + //******************************************************************* + // FUNCTION: to_struct() + // This function packs variables into a fuse_ctrl_core_axi_read_out_configuration_s + // structure. The function returns the handle to the fuse_ctrl_core_axi_read_out_configuration_struct. + // This function is defined in fuse_ctrl_core_axi_read_out_macros.svh + `fuse_ctrl_core_axi_read_out_CONFIGURATION_TO_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_struct() + // This function unpacks the struct provided as an argument into + // variables of this class. + // This function is defined in fuse_ctrl_core_axi_read_out_macros.svh + `fuse_ctrl_core_axi_read_out_CONFIGURATION_FROM_STRUCT_FUNCTION + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + // Construct the covergroup for this configuration class + fuse_ctrl_core_axi_read_out_configuration_cg = new; + endfunction + + // **************************************************************************** + // FUNCTION: post_randomize() + // This function is automatically called after the randomize() function + // is executed. + // + function void post_randomize(); + super.post_randomize(); + fuse_ctrl_core_axi_read_out_configuration_cg.sample(); + endfunction + + // **************************************************************************** + // FUNCTION: initialize + // This function causes the configuration to retrieve + // its virtual interface handle from the uvm_config_db. + // This function also makes itself available to its + // agent through the uvm_config_db. + // + // ARGUMENTS: + // uvmf_active_passive_t activity: + // This argument identifies the simulation level + // as either BLOCK, CHIP, SIMULATION, etc. + // + // AGENT_PATH: + // This argument identifies the path to this + // configurations agent. This configuration + // makes itself available to the agent specified + // by agent_path by placing itself into the + // uvm_config_db. + // + // INTERFACE_NAME: + // This argument identifies the string name of + // this configurations BFM's. This string + // name is used to retrieve the driver and + // monitor BFM from the uvm_config_db. + // + virtual function void initialize(uvmf_active_passive_t activity, + string agent_path, + string interface_name); + + super.initialize( activity, agent_path, interface_name); + // The covergroup is given the same name as the interface + fuse_ctrl_core_axi_read_out_configuration_cg.set_inst_name(interface_name); + + // This configuration places itself into the uvm_config_db for the agent, identified by the agent_path variable, to retrieve. + uvm_config_db #( fuse_ctrl_core_axi_read_out_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + )::set( null ,agent_path,UVMF_AGENT_CONFIG, this ); + + // This configuration also places itself in the config db using the same identifier used by the interface. This allows users to access + // configuration variables and the interface through the bfm api class rather than directly accessing the BFM. This is useful for + // accessingthe BFM when using Veloce + uvm_config_db #( fuse_ctrl_core_axi_read_out_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + )::set( null ,UVMF_CONFIGURATIONS, interface_name, this ); + + fuse_ctrl_core_axi_read_out_configuration_cg.set_inst_name($sformatf("fuse_ctrl_core_axi_read_out_configuration_cg_%s",get_full_name())); + +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. + `uvm_info("CFG", + $psprintf("The agent at '%s' is using interface named %s has the following parameters: AW=%x DW=%x IW=%x UW=%x ", agent_path, interface_name, AW ,DW ,IW ,UW ), + UVM_DEBUG) + + // pragma uvmf custom initialize begin + // This controls whether or not the agent returns a transaction handle in the driver when calling + // item_done() back into the sequencer or not. If set to 1, a transaction is sent back which means + // the sequence on the other end must use the get_response() part of the driver/sequence API. If + // this doesn't occur, there will eventually be response_queue overflow errors during the test. + return_transaction_response = 1'b0; + + // pragma uvmf custom initialize end + + endfunction + + // **************************************************************************** + // TASK: wait_for_reset + // *[Required]* Blocks until reset is released. The wait_for_reset operation is performed + // by a task in the monitor bfm. + virtual task wait_for_reset(); + monitor_bfm.wait_for_reset(); + endtask + + // **************************************************************************** + // TASK: wait_for_num_clocks + // *[Required]* Blocks until specified number of clocks have elapsed. The wait_for_num_clocks + // operation is performed by a task in the monitor bfm. + virtual task wait_for_num_clocks(int clocks); + monitor_bfm.wait_for_num_clocks(clocks); + endtask + + // **************************************************************************** + // FUNCTION : convert2string() + // This function is used to convert variables in this class into a string for log messaging. + // + virtual function string convert2string (); + // pragma uvmf custom convert2string begin + return $sformatf(""); + // pragma uvmf custom convert2string end + endfunction + + // **************************************************************************** + // FUNCTION: get_sequencer + function uvm_sequencer #(fuse_ctrl_core_axi_read_out_transaction#( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )) get_sequencer(); + return sequencer; + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_driver.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_driver.svh new file mode 100644 index 0000000..e99d125 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_driver.svh @@ -0,0 +1,135 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class passes transactions between the sequencer +// and the BFM driver interface. It accesses the driver BFM +// through the bfm handle. This driver +// passes transactions to the driver BFM through the access +// task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_read_out_driver #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvmf_driver_base #( + .CONFIG_T(fuse_ctrl_core_axi_read_out_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) ), + .BFM_BIND_T(virtual fuse_ctrl_core_axi_read_out_driver_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) ), + .REQ(fuse_ctrl_core_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) ), + .RSP(fuse_ctrl_core_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) )); + + `uvm_component_param_utils( fuse_ctrl_core_axi_read_out_driver #( + AW, + DW, + IW, + UW + )) +//******************************************************************* +// Macros that define structs located in fuse_ctrl_core_axi_read_out_macros.svh +//******************************************************************* +// Initiator macro used by fuse_ctrl_core_axi_read_out_driver and fuse_ctrl_core_axi_read_out_driver_bfm +// to communicate initiator driven data to fuse_ctrl_core_axi_read_out_driver_bfm. +`fuse_ctrl_core_axi_read_out_INITIATOR_STRUCT + fuse_ctrl_core_axi_read_out_initiator_s fuse_ctrl_core_axi_read_out_initiator_struct; +//******************************************************************* +// Responder macro used by fuse_ctrl_core_axi_read_out_driver and fuse_ctrl_core_axi_read_out_driver_bfm +// to communicate Responder driven data to fuse_ctrl_core_axi_read_out_driver_bfm. +`fuse_ctrl_core_axi_read_out_RESPONDER_STRUCT + fuse_ctrl_core_axi_read_out_responder_s fuse_ctrl_core_axi_read_out_responder_struct; + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent=null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the driver BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// driver BFM. This allows the driver BFM to call tasks and function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// **************************************************************************** +// This task is called by the run_phase in uvmf_driver_base. + virtual task access( inout REQ txn ); +// pragma uvmf custom access begin + if (configuration.initiator_responder==RESPONDER) begin + // Complete current transfer and wait for next transfer + bfm.respond_and_wait_for_next_transfer( + fuse_ctrl_core_axi_read_out_initiator_struct, + txn.to_responder_struct() + ); + // Unpack information about initiated transfer received by this responder + txn.from_initiator_struct(fuse_ctrl_core_axi_read_out_initiator_struct); + end else begin + // Initiate a transfer and get response + bfm.initiate_and_get_response( + txn.to_initiator_struct(), + fuse_ctrl_core_axi_read_out_responder_struct + ); + // Unpack transfer response information received by this initiator + txn.from_responder_struct(fuse_ctrl_core_axi_read_out_responder_struct); + end +// pragma uvmf custom access end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_driver_bfm.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_driver_bfm.sv new file mode 100644 index 0000000..1f8fb45 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_driver_bfm.sv @@ -0,0 +1,350 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This interface performs the fuse_ctrl_core_axi_read_out signal driving. It is +// accessed by the uvm fuse_ctrl_core_axi_read_out driver through a virtual interface +// handle in the fuse_ctrl_core_axi_read_out configuration. It drives the singals passed +// in through the port connection named bus of type fuse_ctrl_core_axi_read_out_if. +// +// Input signals from the fuse_ctrl_core_axi_read_out_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// This bfm drives signals with a _o suffix. These signals +// are driven onto signals within fuse_ctrl_core_axi_read_out_if based on INITIATOR/RESPONDER and/or +// ARBITRATION/GRANT status. +// +// The output signal connections are as follows: +// signal_o -> bus.signal +// +// +// Interface functions and tasks used by UVM components: +// +// configure: +// This function gets configuration attributes from the +// UVM driver to set any required BFM configuration +// variables such as 'initiator_responder'. +// +// initiate_and_get_response: +// This task is used to perform signaling activity for initiating +// a protocol transfer. The task initiates the transfer, using +// input data from the initiator struct. Then the task captures +// response data, placing the data into the response struct. +// The response struct is returned to the driver class. +// +// respond_and_wait_for_next_transfer: +// This task is used to complete a current transfer as a responder +// and then wait for the initiator to start the next transfer. +// The task uses data in the responder struct to drive protocol +// signals to complete the transfer. The task then waits for +// the next transfer. Once the next transfer begins, data from +// the initiator is placed into the initiator struct and sent +// to the responder sequence for processing to determine +// what data to respond with. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_core_axi_read_out_pkg_hdl::*; +`include "src/fuse_ctrl_core_axi_read_out_macros.svh" + +interface fuse_ctrl_core_axi_read_out_driver_bfm #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + (fuse_ctrl_core_axi_read_out_if bus); + // The following pragma and additional ones in-lined further below are for running this BFM on Veloce + // pragma attribute fuse_ctrl_core_axi_read_out_driver_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: AW=%x DW=%x IW=%x UW=%x ", AW,DW,IW,UW), + UVM_DEBUG) +end +`endif + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + tri clk_i_i; + tri rst_ni_i; + + // Signal list (all signals are capable of being inputs and outputs for the sake + // of supporting both INITIATOR and RESPONDER mode operation. Expectation is that + // directionality in the config file was from the point-of-view of the INITIATOR + + // INITIATOR mode input signals + tri arready_i; + reg arready_o = 'bz; + tri [DW-1:0] rdata_i; + reg [DW-1:0] rdata_o = 'bz; + tri rresp_i; + reg rresp_o = 'bz; + tri rid_i; + reg rid_o = 'bz; + tri rlast_i; + reg rlast_o = 'bz; + tri rvalid_i; + reg rvalid_o = 'bz; + + // INITIATOR mode output signals + + // Bi-directional signals + + + assign clk_i_i = bus.clk_i; + assign rst_ni_i = bus.rst_ni; + + // These are signals marked as 'input' by the config file, but the signals will be + // driven by this BFM if put into RESPONDER mode (flipping all signal directions around) + assign arready_i = bus.arready; + assign bus.arready = (initiator_responder == RESPONDER) ? arready_o : 'bz; + assign rdata_i = bus.rdata; + assign bus.rdata = (initiator_responder == RESPONDER) ? rdata_o : 'bz; + assign rresp_i = bus.rresp; + assign bus.rresp = (initiator_responder == RESPONDER) ? rresp_o : 'bz; + assign rid_i = bus.rid; + assign bus.rid = (initiator_responder == RESPONDER) ? rid_o : 'bz; + assign rlast_i = bus.rlast; + assign bus.rlast = (initiator_responder == RESPONDER) ? rlast_o : 'bz; + assign rvalid_i = bus.rvalid; + assign bus.rvalid = (initiator_responder == RESPONDER) ? rvalid_o : 'bz; + + + // These are signals marked as 'output' by the config file, but the outputs will + // not be driven by this BFM unless placed in INITIATOR mode. + + // Proxy handle to UVM driver + fuse_ctrl_core_axi_read_out_pkg::fuse_ctrl_core_axi_read_out_driver #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) proxy; + // pragma tbx oneway proxy.my_function_name_in_uvm_driver + + // **************************************************************************** + // **************************************************************************** + // Macros that define structs located in fuse_ctrl_core_axi_read_out_macros.svh + // **************************************************************************** + // Struct for passing configuration data from fuse_ctrl_core_axi_read_out_driver to this BFM + // **************************************************************************** + `fuse_ctrl_core_axi_read_out_CONFIGURATION_STRUCT + // **************************************************************************** + // Structs for INITIATOR and RESPONDER data flow + //******************************************************************* + // Initiator macro used by fuse_ctrl_core_axi_read_out_driver and fuse_ctrl_core_axi_read_out_driver_bfm + // to communicate initiator driven data to fuse_ctrl_core_axi_read_out_driver_bfm. + `fuse_ctrl_core_axi_read_out_INITIATOR_STRUCT + fuse_ctrl_core_axi_read_out_initiator_s initiator_struct; + // Responder macro used by fuse_ctrl_core_axi_read_out_driver and fuse_ctrl_core_axi_read_out_driver_bfm + // to communicate Responder driven data to fuse_ctrl_core_axi_read_out_driver_bfm. + `fuse_ctrl_core_axi_read_out_RESPONDER_STRUCT + fuse_ctrl_core_axi_read_out_responder_s responder_struct; + + // **************************************************************************** +// pragma uvmf custom reset_condition_and_response begin + // Always block used to return signals to reset value upon assertion of reset + always @( negedge rst_ni_i ) + begin + // RESPONDER mode output signals + arready_o <= 'bz; + rdata_o <= 'bz; + rresp_o <= 'bz; + rid_o <= 'bz; + rlast_o <= 'bz; + rvalid_o <= 'bz; + // INITIATOR mode output signals + // Bi-directional signals + + end +// pragma uvmf custom reset_condition_and_response end + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the driver BFM. It is called by the driver within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the driver BFM needs to be aware of the new configuration + // variables. + // + + function void configure(fuse_ctrl_core_axi_read_out_configuration_s fuse_ctrl_core_axi_read_out_configuration_arg); // pragma tbx xtf + initiator_responder = fuse_ctrl_core_axi_read_out_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + +// pragma uvmf custom initiate_and_get_response begin +// **************************************************************************** +// UVMF_CHANGE_ME +// This task is used by an initator. The task first initiates a transfer then +// waits for the responder to complete the transfer. + task initiate_and_get_response( + // This argument passes transaction variables used by an initiator + // to perform the initial part of a protocol transfer. The values + // come from a sequence item created in a sequence. + input fuse_ctrl_core_axi_read_out_initiator_s fuse_ctrl_core_axi_read_out_initiator_struct, + // This argument is used to send data received from the responder + // back to the sequence item. The sequence item is returned to the sequence. + output fuse_ctrl_core_axi_read_out_responder_s fuse_ctrl_core_axi_read_out_responder_struct + );// pragma tbx xtf + // + // Members within the fuse_ctrl_core_axi_read_out_initiator_struct: + // logic core_arready ; + // logic [DW-1:0] core_rdata ; + // axi_pkg::axi_burst_e core_rresp ; + // logic [IW-1:0] core_rid ; + // logic core_rlast ; + // logic core_rvalid ; + // Members within the fuse_ctrl_core_axi_read_out_responder_struct: + // logic core_arready ; + // logic [DW-1:0] core_rdata ; + // axi_pkg::axi_burst_e core_rresp ; + // logic [IW-1:0] core_rid ; + // logic core_rlast ; + // logic core_rvalid ; + initiator_struct = fuse_ctrl_core_axi_read_out_initiator_struct; + // + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clk_i_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available initiator input and inout signals listed. + // Initiator input signals + // fuse_ctrl_core_axi_read_out_responder_struct.xyz = arready_i; // + // fuse_ctrl_core_axi_read_out_responder_struct.xyz = rdata_i; // [DW-1:0] + // fuse_ctrl_core_axi_read_out_responder_struct.xyz = rresp_i; // + // fuse_ctrl_core_axi_read_out_responder_struct.xyz = rid_i; // + // fuse_ctrl_core_axi_read_out_responder_struct.xyz = rlast_i; // + // fuse_ctrl_core_axi_read_out_responder_struct.xyz = rvalid_i; // + // Initiator inout signals + // How to assign a signal from an initiator struct member named xyz. + // All available initiator output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Initiator output signals + // Initiator inout signals + // Initiate a transfer using the data received. + @(posedge clk_i_i); + @(posedge clk_i_i); + // Wait for the responder to complete the transfer then place the responder data into + // fuse_ctrl_core_axi_read_out_responder_struct. + @(posedge clk_i_i); + @(posedge clk_i_i); + responder_struct = fuse_ctrl_core_axi_read_out_responder_struct; + endtask +// pragma uvmf custom initiate_and_get_response end + +// pragma uvmf custom respond_and_wait_for_next_transfer begin +// **************************************************************************** +// The first_transfer variable is used to prevent completing a transfer in the +// first call to this task. For the first call to this task, there is not +// current transfer to complete. +bit first_transfer=1; + +// UVMF_CHANGE_ME +// This task is used by a responder. The task first completes the current +// transfer in progress then waits for the initiator to start the next transfer. + task respond_and_wait_for_next_transfer( + // This argument is used to send data received from the initiator + // back to the sequence item. The sequence determines how to respond. + output fuse_ctrl_core_axi_read_out_initiator_s fuse_ctrl_core_axi_read_out_initiator_struct, + // This argument passes transaction variables used by a responder + // to complete a protocol transfer. The values come from a sequence item. + input fuse_ctrl_core_axi_read_out_responder_s fuse_ctrl_core_axi_read_out_responder_struct + );// pragma tbx xtf + // Variables within the fuse_ctrl_core_axi_read_out_initiator_struct: + // logic core_arready ; + // logic [DW-1:0] core_rdata ; + // axi_pkg::axi_burst_e core_rresp ; + // logic [IW-1:0] core_rid ; + // logic core_rlast ; + // logic core_rvalid ; + // Variables within the fuse_ctrl_core_axi_read_out_responder_struct: + // logic core_arready ; + // logic [DW-1:0] core_rdata ; + // axi_pkg::axi_burst_e core_rresp ; + // logic [IW-1:0] core_rid ; + // logic core_rlast ; + // logic core_rvalid ; + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clk_i_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available responder input and inout signals listed. + // Responder input signals + // Responder inout signals + // How to assign a signal, named xyz, from an initiator struct member. + // All available responder output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Responder output signals + // arready_o <= fuse_ctrl_core_axi_read_out_initiator_struct.xyz; // + // rdata_o <= fuse_ctrl_core_axi_read_out_initiator_struct.xyz; // [DW-1:0] + // rresp_o <= fuse_ctrl_core_axi_read_out_initiator_struct.xyz; // + // rid_o <= fuse_ctrl_core_axi_read_out_initiator_struct.xyz; // + // rlast_o <= fuse_ctrl_core_axi_read_out_initiator_struct.xyz; // + // rvalid_o <= fuse_ctrl_core_axi_read_out_initiator_struct.xyz; // + // Responder inout signals + + @(posedge clk_i_i); + if (!first_transfer) begin + // Perform transfer response here. + // Reply using data recieved in the fuse_ctrl_core_axi_read_out_responder_struct. + @(posedge clk_i_i); + // Reply using data recieved in the transaction handle. + @(posedge clk_i_i); + end + // Wait for next transfer then gather info from intiator about the transfer. + // Place the data into the fuse_ctrl_core_axi_read_out_initiator_struct. + @(posedge clk_i_i); + @(posedge clk_i_i); + first_transfer = 0; + endtask +// pragma uvmf custom respond_and_wait_for_next_transfer end + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_if.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_if.sv new file mode 100644 index 0000000..7cc1b50 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_if.sv @@ -0,0 +1,108 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface contains the fuse_ctrl_core_axi_read_out interface signals. +// It is instantiated once per fuse_ctrl_core_axi_read_out bus. Bus Functional Models, +// BFM's named fuse_ctrl_core_axi_read_out_driver_bfm, are used to drive signals on the bus. +// BFM's named fuse_ctrl_core_axi_read_out_monitor_bfm are used to monitor signals on the +// bus. This interface signal bundle is passed in the port list of +// the BFM in order to give the BFM access to the signals in this +// interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// This template can be used to connect a DUT to these signals +// +// .dut_signal_port(fuse_ctrl_core_axi_read_out_bus.arready), // Agent input +// .dut_signal_port(fuse_ctrl_core_axi_read_out_bus.rdata), // Agent input +// .dut_signal_port(fuse_ctrl_core_axi_read_out_bus.rresp), // Agent input +// .dut_signal_port(fuse_ctrl_core_axi_read_out_bus.rid), // Agent input +// .dut_signal_port(fuse_ctrl_core_axi_read_out_bus.rlast), // Agent input +// .dut_signal_port(fuse_ctrl_core_axi_read_out_bus.rvalid), // Agent input + +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_core_axi_read_out_pkg_hdl::*; + +interface fuse_ctrl_core_axi_read_out_if #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + + ( + input tri clk_i, + input tri rst_ni, + inout tri arready, + inout tri [DW-1:0] rdata, + inout tri rresp, + inout tri rid, + inout tri rlast, + inout tri rvalid + ); + +modport monitor_port + ( + input clk_i, + input rst_ni, + input arready, + input rdata, + input rresp, + input rid, + input rlast, + input rvalid + ); + +modport initiator_port + ( + input clk_i, + input rst_ni, + input arready, + input rdata, + input rresp, + input rid, + input rlast, + input rvalid + ); + +modport responder_port + ( + input clk_i, + input rst_ni, + output arready, + output rdata, + output rresp, + output rid, + output rlast, + output rvalid + ); + + +// pragma uvmf custom interface_item_additional begin +// pragma uvmf custom interface_item_additional end + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_infact_coverage_strategy.csv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_infact_coverage_strategy.csv new file mode 100644 index 0000000..1c218e1 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_infact_coverage_strategy.csv @@ -0,0 +1,6 @@ +Global +auto_bin_max, 64 + +Name,Type,Include +rand_fields,coverpoint,=rand *.** + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_macros.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_macros.svh new file mode 100644 index 0000000..2742dc0 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_macros.svh @@ -0,0 +1,180 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains macros used with the fuse_ctrl_core_axi_read_out package. +// These macros include packed struct definitions. These structs are +// used to pass data between classes, hvl, and BFM's, hdl. Use of +// structs are more efficient and simpler to modify. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_struct +// and from_struct methods defined in the macros below that are used in +// the fuse_ctrl_core_axi_read_out_configuration class. +// + `define fuse_ctrl_core_axi_read_out_CONFIGURATION_STRUCT \ +typedef struct packed { \ + uvmf_active_passive_t active_passive; \ + uvmf_initiator_responder_t initiator_responder; \ + } fuse_ctrl_core_axi_read_out_configuration_s; + + `define fuse_ctrl_core_axi_read_out_CONFIGURATION_TO_STRUCT_FUNCTION \ + virtual function fuse_ctrl_core_axi_read_out_configuration_s to_struct();\ + fuse_ctrl_core_axi_read_out_configuration_struct = \ + {\ + this.active_passive,\ + this.initiator_responder\ + };\ + return ( fuse_ctrl_core_axi_read_out_configuration_struct );\ + endfunction + + `define fuse_ctrl_core_axi_read_out_CONFIGURATION_FROM_STRUCT_FUNCTION \ + virtual function void from_struct(fuse_ctrl_core_axi_read_out_configuration_s fuse_ctrl_core_axi_read_out_configuration_struct);\ + {\ + this.active_passive,\ + this.initiator_responder \ + } = fuse_ctrl_core_axi_read_out_configuration_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_monitor_struct +// and from_monitor_struct methods of the fuse_ctrl_core_axi_read_out_transaction class. +// + `define fuse_ctrl_core_axi_read_out_MONITOR_STRUCT typedef struct packed { \ + logic core_arready ; \ + logic [DW-1:0] core_rdata ; \ + axi_pkg::axi_burst_e core_rresp ; \ + logic [IW-1:0] core_rid ; \ + logic core_rlast ; \ + logic core_rvalid ; \ + } fuse_ctrl_core_axi_read_out_monitor_s; + + `define fuse_ctrl_core_axi_read_out_TO_MONITOR_STRUCT_FUNCTION \ + virtual function fuse_ctrl_core_axi_read_out_monitor_s to_monitor_struct();\ + fuse_ctrl_core_axi_read_out_monitor_struct = \ + { \ + this.core_arready , \ + this.core_rdata , \ + this.core_rresp , \ + this.core_rid , \ + this.core_rlast , \ + this.core_rvalid \ + };\ + return ( fuse_ctrl_core_axi_read_out_monitor_struct);\ + endfunction\ + + `define fuse_ctrl_core_axi_read_out_FROM_MONITOR_STRUCT_FUNCTION \ + virtual function void from_monitor_struct(fuse_ctrl_core_axi_read_out_monitor_s fuse_ctrl_core_axi_read_out_monitor_struct);\ + {\ + this.core_arready , \ + this.core_rdata , \ + this.core_rresp , \ + this.core_rid , \ + this.core_rlast , \ + this.core_rvalid \ + } = fuse_ctrl_core_axi_read_out_monitor_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_initiator_struct +// and from_initiator_struct methods of the fuse_ctrl_core_axi_read_out_transaction class. +// Also update the comments in the driver BFM. +// + `define fuse_ctrl_core_axi_read_out_INITIATOR_STRUCT typedef struct packed { \ + logic core_arready ; \ + logic [DW-1:0] core_rdata ; \ + axi_pkg::axi_burst_e core_rresp ; \ + logic [IW-1:0] core_rid ; \ + logic core_rlast ; \ + logic core_rvalid ; \ + } fuse_ctrl_core_axi_read_out_initiator_s; + + `define fuse_ctrl_core_axi_read_out_TO_INITIATOR_STRUCT_FUNCTION \ + virtual function fuse_ctrl_core_axi_read_out_initiator_s to_initiator_struct();\ + fuse_ctrl_core_axi_read_out_initiator_struct = \ + {\ + this.core_arready , \ + this.core_rdata , \ + this.core_rresp , \ + this.core_rid , \ + this.core_rlast , \ + this.core_rvalid \ + };\ + return ( fuse_ctrl_core_axi_read_out_initiator_struct);\ + endfunction + + `define fuse_ctrl_core_axi_read_out_FROM_INITIATOR_STRUCT_FUNCTION \ + virtual function void from_initiator_struct(fuse_ctrl_core_axi_read_out_initiator_s fuse_ctrl_core_axi_read_out_initiator_struct);\ + {\ + this.core_arready , \ + this.core_rdata , \ + this.core_rresp , \ + this.core_rid , \ + this.core_rlast , \ + this.core_rvalid \ + } = fuse_ctrl_core_axi_read_out_initiator_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_responder_struct +// and from_responder_struct methods of the fuse_ctrl_core_axi_read_out_transaction class. +// Also update the comments in the driver BFM. +// + `define fuse_ctrl_core_axi_read_out_RESPONDER_STRUCT typedef struct packed { \ + logic core_arready ; \ + logic [DW-1:0] core_rdata ; \ + axi_pkg::axi_burst_e core_rresp ; \ + logic [IW-1:0] core_rid ; \ + logic core_rlast ; \ + logic core_rvalid ; \ + } fuse_ctrl_core_axi_read_out_responder_s; + + `define fuse_ctrl_core_axi_read_out_TO_RESPONDER_STRUCT_FUNCTION \ + virtual function fuse_ctrl_core_axi_read_out_responder_s to_responder_struct();\ + fuse_ctrl_core_axi_read_out_responder_struct = \ + {\ + this.core_arready , \ + this.core_rdata , \ + this.core_rresp , \ + this.core_rid , \ + this.core_rlast , \ + this.core_rvalid \ + };\ + return ( fuse_ctrl_core_axi_read_out_responder_struct);\ + endfunction + + `define fuse_ctrl_core_axi_read_out_FROM_RESPONDER_STRUCT_FUNCTION \ + virtual function void from_responder_struct(fuse_ctrl_core_axi_read_out_responder_s fuse_ctrl_core_axi_read_out_responder_struct);\ + {\ + this.core_arready , \ + this.core_rdata , \ + this.core_rresp , \ + this.core_rid , \ + this.core_rlast , \ + this.core_rvalid \ + } = fuse_ctrl_core_axi_read_out_responder_struct;\ + endfunction +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_monitor.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_monitor.svh new file mode 100644 index 0000000..7320d3d --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_monitor.svh @@ -0,0 +1,126 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class receives fuse_ctrl_core_axi_read_out transactions observed by the +// fuse_ctrl_core_axi_read_out monitor BFM and broadcasts them through the analysis port +// on the agent. It accesses the monitor BFM through the monitor +// task. This UVM component captures transactions +// for viewing in the waveform viewer if the +// enable_transaction_viewing flag is set in the configuration. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_read_out_monitor #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvmf_monitor_base #( + .CONFIG_T(fuse_ctrl_core_axi_read_out_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .BFM_BIND_T(virtual fuse_ctrl_core_axi_read_out_monitor_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .TRANS_T(fuse_ctrl_core_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ))); + + `uvm_component_param_utils( fuse_ctrl_core_axi_read_out_monitor #( + AW, + DW, + IW, + UW + )) + +// Structure used to pass data from monitor BFM to monitor class in agent. +// Use to_monitor_struct function to pack transaction variables into structure. +// Use from_monitor_struct function to unpack transaction variables from structure. +`fuse_ctrl_core_axi_read_out_MONITOR_STRUCT + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the monitor BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// monitor BFM. This allows the monitor BFM to call the notify_transaction +// function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// *************************************************************************** + virtual task run_phase(uvm_phase phase); + // Start monitor BFM thread and don't call super.run() in order to + // override the default monitor proxy 'pull' behavior with the more + // emulation-friendly BFM 'push' approach using the notify_transaction + // function below + bfm.start_monitoring(); + endtask + +// ************************************************************************** + +// This function is called by the monitor BFM. It receives data observed by the +// monitor BFM. Data is passed using the fuse_ctrl_core_axi_read_out_monitor_struct. + virtual function void notify_transaction(input fuse_ctrl_core_axi_read_out_monitor_s fuse_ctrl_core_axi_read_out_monitor_struct); + + + trans = new("trans"); + trans.from_monitor_struct(fuse_ctrl_core_axi_read_out_monitor_struct); + trans.start_time = time_stamp; + trans.end_time = $time; + time_stamp = trans.end_time; + + analyze(trans); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_monitor_bfm.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_monitor_bfm.sv new file mode 100644 index 0000000..f2b126d --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_monitor_bfm.sv @@ -0,0 +1,218 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface performs the fuse_ctrl_core_axi_read_out signal monitoring. +// It is accessed by the uvm fuse_ctrl_core_axi_read_out monitor through a virtual +// interface handle in the fuse_ctrl_core_axi_read_out configuration. It monitors the +// signals passed in through the port connection named bus of +// type fuse_ctrl_core_axi_read_out_if. +// +// Input signals from the fuse_ctrl_core_axi_read_out_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// Interface functions and tasks used by UVM components: +// monitor(inout TRANS_T txn); +// This task receives the transaction, txn, from the +// UVM monitor and then populates variables in txn +// from values observed on bus activity. This task +// blocks until an operation on the fuse_ctrl_core_axi_read_out bus is complete. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_core_axi_read_out_pkg_hdl::*; +`include "src/fuse_ctrl_core_axi_read_out_macros.svh" + + +interface fuse_ctrl_core_axi_read_out_monitor_bfm #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + ( fuse_ctrl_core_axi_read_out_if bus ); + // The pragma below and additional ones in-lined further down are for running this BFM on Veloce + // pragma attribute fuse_ctrl_core_axi_read_out_monitor_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: AW=%x DW=%x IW=%x UW=%x ", AW,DW,IW,UW), + UVM_DEBUG) +end +`endif + + + // Structure used to pass transaction data from monitor BFM to monitor class in agent. +`fuse_ctrl_core_axi_read_out_MONITOR_STRUCT + fuse_ctrl_core_axi_read_out_monitor_s fuse_ctrl_core_axi_read_out_monitor_struct; + + // Structure used to pass configuration data from monitor class to monitor BFM. + `fuse_ctrl_core_axi_read_out_CONFIGURATION_STRUCT + + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + tri clk_i_i; + tri rst_ni_i; + tri arready_i; + tri [DW-1:0] rdata_i; + tri rresp_i; + tri rid_i; + tri rlast_i; + tri rvalid_i; + assign clk_i_i = bus.clk_i; + assign rst_ni_i = bus.rst_ni; + assign arready_i = bus.arready; + assign rdata_i = bus.rdata; + assign rresp_i = bus.rresp; + assign rid_i = bus.rid; + assign rlast_i = bus.rlast; + assign rvalid_i = bus.rvalid; + + // Proxy handle to UVM monitor + fuse_ctrl_core_axi_read_out_pkg::fuse_ctrl_core_axi_read_out_monitor #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) proxy; + // pragma tbx oneway proxy.notify_transaction + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + task wait_for_reset();// pragma tbx xtf + @(posedge clk_i_i) ; + do_wait_for_reset(); + endtask + + // **************************************************************************** + task do_wait_for_reset(); + // pragma uvmf custom reset_condition begin + wait ( rst_ni_i === 1 ) ; + @(posedge clk_i_i) ; + // pragma uvmf custom reset_condition end + endtask + + //****************************************************************** + + task wait_for_num_clocks(input int unsigned count); // pragma tbx xtf + @(posedge clk_i_i); + + repeat (count-1) @(posedge clk_i_i); + endtask + + //****************************************************************** + event go; + function void start_monitoring();// pragma tbx xtf + -> go; + endfunction + + // **************************************************************************** + initial begin + @go; + forever begin + @(posedge clk_i_i); + do_monitor( fuse_ctrl_core_axi_read_out_monitor_struct ); + + + proxy.notify_transaction( fuse_ctrl_core_axi_read_out_monitor_struct ); + + end + end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the monitor BFM. It is called by the monitor within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the monitor BFM needs to be aware of the new configuration + // variables. + // + function void configure(fuse_ctrl_core_axi_read_out_configuration_s fuse_ctrl_core_axi_read_out_configuration_arg); // pragma tbx xtf + initiator_responder = fuse_ctrl_core_axi_read_out_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + + + // **************************************************************************** + + task do_monitor(output fuse_ctrl_core_axi_read_out_monitor_s fuse_ctrl_core_axi_read_out_monitor_struct); + // + // Available struct members: + // // fuse_ctrl_core_axi_read_out_monitor_struct.core_arready + // // fuse_ctrl_core_axi_read_out_monitor_struct.core_rdata + // // fuse_ctrl_core_axi_read_out_monitor_struct.core_rresp + // // fuse_ctrl_core_axi_read_out_monitor_struct.core_rid + // // fuse_ctrl_core_axi_read_out_monitor_struct.core_rlast + // // fuse_ctrl_core_axi_read_out_monitor_struct.core_rvalid + // // + // Reference code; + // How to wait for signal value + // while (control_signal === 1'b1) @(posedge clk_i_i); + // + // How to assign a struct member, named xyz, from a signal. + // All available input signals listed. + // fuse_ctrl_core_axi_read_out_monitor_struct.xyz = arready_i; // + // fuse_ctrl_core_axi_read_out_monitor_struct.xyz = rdata_i; // [DW-1:0] + // fuse_ctrl_core_axi_read_out_monitor_struct.xyz = rresp_i; // + // fuse_ctrl_core_axi_read_out_monitor_struct.xyz = rid_i; // + // fuse_ctrl_core_axi_read_out_monitor_struct.xyz = rlast_i; // + // fuse_ctrl_core_axi_read_out_monitor_struct.xyz = rvalid_i; // + // pragma uvmf custom do_monitor begin + // UVMF_CHANGE_ME : Implement protocol monitoring. The commented reference code + // below are examples of how to capture signal values and assign them to + // structure members. All available input signals are listed. The 'while' + // code example shows how to wait for a synchronous flow control signal. This + // task should return when a complete transfer has been observed. Once this task is + // exited with captured values, it is then called again to wait for and observe + // the next transfer. One clock cycle is consumed between calls to do_monitor. + @(posedge clk_i_i); + @(posedge clk_i_i); + @(posedge clk_i_i); + @(posedge clk_i_i); + // pragma uvmf custom do_monitor end + endtask + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_random_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_random_sequence.svh new file mode 100644 index 0000000..cb48c28 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_random_sequence.svh @@ -0,0 +1,87 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This sequences randomizes the fuse_ctrl_core_axi_read_out transaction and sends it +// to the UVM driver. +// +// This sequence constructs and randomizes a fuse_ctrl_core_axi_read_out_transaction. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_read_out_random_sequence #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends fuse_ctrl_core_axi_read_out_sequence_base #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ); + + `uvm_object_param_utils( fuse_ctrl_core_axi_read_out_random_sequence #( + AW, + DW, + IW, + UW + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //***************************************************************** + function new(string name = ""); + super.new(name); + endfunction: new + + // **************************************************************************** + // TASK : body() + // This task is automatically executed when this sequence is started using the + // start(sequencerHandle) task. + // + task body(); + + // Construct the transaction + req=fuse_ctrl_core_axi_read_out_transaction#( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )::type_id::create("req"); + start_item(req); + // Randomize the transaction + if(!req.randomize()) `uvm_fatal("SEQ", "fuse_ctrl_core_axi_read_out_random_sequence::body()-fuse_ctrl_core_axi_read_out_transaction randomization failed") + // Send the transaction to the fuse_ctrl_core_axi_read_out_driver_bfm via the sequencer and fuse_ctrl_core_axi_read_out_driver. + finish_item(req); + `uvm_info("SEQ", {"Response:",req.convert2string()},UVM_MEDIUM) + + endtask + +endclass: fuse_ctrl_core_axi_read_out_random_sequence + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_responder_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_responder_sequence.svh new file mode 100644 index 0000000..ffe88ce --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_responder_sequence.svh @@ -0,0 +1,83 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class can be used to provide stimulus when an interface +// has been configured to run in a responder mode. It +// will never finish by default, always going back to the driver +// and driver BFM for the next transaction with which to respond. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_read_out_responder_sequence #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends fuse_ctrl_core_axi_read_out_sequence_base #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ); + + `uvm_object_param_utils( fuse_ctrl_core_axi_read_out_responder_sequence #( + AW, + DW, + IW, + UW + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "fuse_ctrl_core_axi_read_out_responder_sequence"); + super.new(name); + endfunction + + task body(); + req=fuse_ctrl_core_axi_read_out_transaction#( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )::type_id::create("req"); + forever begin + start_item(req); + finish_item(req); + // pragma uvmf custom body begin + // UVMF_CHANGE_ME : Do something here with the resulting req item. The + // finish_item() call above will block until the req transaction is ready + // to be handled by the responder sequence. + // If this was an item that required a response, the expectation is + // that the response should be populated within this transaction now. + `uvm_info("SEQ",$sformatf("Processed txn: %s",req.convert2string()),UVM_HIGH) + // pragma uvmf custom body end + end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_sequence_base.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_sequence_base.svh new file mode 100644 index 0000000..be33441 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_sequence_base.svh @@ -0,0 +1,140 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the class used as the base class for all sequences +// for this interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_read_out_sequence_base #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvmf_sequence_base #( + .REQ(fuse_ctrl_core_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .RSP(fuse_ctrl_core_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ))); + + `uvm_object_param_utils( fuse_ctrl_core_axi_read_out_sequence_base #( + AW, + DW, + IW, + UW + )) + + // variables + typedef fuse_ctrl_core_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) fuse_ctrl_core_axi_read_out_transaction_req_t; + fuse_ctrl_core_axi_read_out_transaction_req_t req; + typedef fuse_ctrl_core_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) fuse_ctrl_core_axi_read_out_transaction_rsp_t; + fuse_ctrl_core_axi_read_out_transaction_rsp_t rsp; + + // Event for identifying when a response was received from the sequencer + event new_rsp; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // TASK : get_responses() + // This task recursively gets sequence item responses from the sequencer. + // + virtual task get_responses(); + fork + begin + // Block until new rsp available + get_response(rsp); + // New rsp received. Indicate to sequence using event. + ->new_rsp; + // Display the received response transaction + `uvm_info("SEQ", {"New response transaction:",rsp.convert2string()}, UVM_MEDIUM) + end + join_none + endtask + + // **************************************************************************** + // TASK : pre_body() + // This task is called automatically when start is called with call_pre_post set to 1 (default). + // By calling get_responses() within pre_body() any derived sequences are automatically + // processing response transactions. Only un-comment this call to get_responses() if you + // have configured the interface driver to utilize the response transaction path by setting + // the configuration variable "return_transaction_response" to 1. Otherwise it is possible + // to impact runtime performance and memory utilization. + // + virtual task pre_body(); + // pragma uvmf custom pre_body begin +// get_responses(); + // pragma uvmf custom pre_body end + endtask + + // **************************************************************************** + // TASK : body() + // This task is called automatically when start is called. This sequence sends + // a req sequence item to the sequencer identified as an argument in the call + // to start. + // + virtual task body(); + // pragma uvmf custom body begin + start_item(req); + finish_item(req); + // pragma uvmf custom body end + endtask + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name =""); + super.new( name ); + // pragma uvmf custom new begin + req = fuse_ctrl_core_axi_read_out_transaction_req_t::type_id::create("req"); + rsp = fuse_ctrl_core_axi_read_out_transaction_rsp_t::type_id::create("rsp"); + // pragma uvmf custom new end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_transaction.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_transaction.svh new file mode 100644 index 0000000..d19ec49 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_transaction.svh @@ -0,0 +1,236 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class defines the variables required for an fuse_ctrl_core_axi_read_out +// transaction. Class variables to be displayed in waveform transaction +// viewing are added to the transaction viewing stream in the add_to_wave +// function. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_read_out_transaction #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvmf_transaction_base; + + `uvm_object_param_utils( fuse_ctrl_core_axi_read_out_transaction #( + AW, + DW, + IW, + UW + )) + + logic core_arready ; + logic [DW-1:0] core_rdata ; + axi_pkg::axi_burst_e core_rresp ; + logic [IW-1:0] core_rid ; + logic core_rlast ; + logic core_rvalid ; + + //Constraints for the transaction variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //******************************************************************* + //******************************************************************* + // Macros that define structs and associated functions are + // located in fuse_ctrl_core_axi_read_out_macros.svh + + //******************************************************************* + // Monitor macro used by fuse_ctrl_core_axi_read_out_monitor and fuse_ctrl_core_axi_read_out_monitor_bfm + // This struct is defined in fuse_ctrl_core_axi_read_out_macros.svh + `fuse_ctrl_core_axi_read_out_MONITOR_STRUCT + fuse_ctrl_core_axi_read_out_monitor_s fuse_ctrl_core_axi_read_out_monitor_struct; + //******************************************************************* + // FUNCTION: to_monitor_struct() + // This function packs transaction variables into a fuse_ctrl_core_axi_read_out_monitor_s + // structure. The function returns the handle to the fuse_ctrl_core_axi_read_out_monitor_struct. + // This function is defined in fuse_ctrl_core_axi_read_out_macros.svh + `fuse_ctrl_core_axi_read_out_TO_MONITOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_monitor_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_core_axi_read_out_macros.svh + `fuse_ctrl_core_axi_read_out_FROM_MONITOR_STRUCT_FUNCTION + + //******************************************************************* + // Initiator macro used by fuse_ctrl_core_axi_read_out_driver and fuse_ctrl_core_axi_read_out_driver_bfm + // to communicate initiator driven data to fuse_ctrl_core_axi_read_out_driver_bfm. + // This struct is defined in fuse_ctrl_core_axi_read_out_macros.svh + `fuse_ctrl_core_axi_read_out_INITIATOR_STRUCT + fuse_ctrl_core_axi_read_out_initiator_s fuse_ctrl_core_axi_read_out_initiator_struct; + //******************************************************************* + // FUNCTION: to_initiator_struct() + // This function packs transaction variables into a fuse_ctrl_core_axi_read_out_initiator_s + // structure. The function returns the handle to the fuse_ctrl_core_axi_read_out_initiator_struct. + // This function is defined in fuse_ctrl_core_axi_read_out_macros.svh + `fuse_ctrl_core_axi_read_out_TO_INITIATOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_initiator_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_core_axi_read_out_macros.svh + `fuse_ctrl_core_axi_read_out_FROM_INITIATOR_STRUCT_FUNCTION + + //******************************************************************* + // Responder macro used by fuse_ctrl_core_axi_read_out_driver and fuse_ctrl_core_axi_read_out_driver_bfm + // to communicate Responder driven data to fuse_ctrl_core_axi_read_out_driver_bfm. + // This struct is defined in fuse_ctrl_core_axi_read_out_macros.svh + `fuse_ctrl_core_axi_read_out_RESPONDER_STRUCT + fuse_ctrl_core_axi_read_out_responder_s fuse_ctrl_core_axi_read_out_responder_struct; + //******************************************************************* + // FUNCTION: to_responder_struct() + // This function packs transaction variables into a fuse_ctrl_core_axi_read_out_responder_s + // structure. The function returns the handle to the fuse_ctrl_core_axi_read_out_responder_struct. + // This function is defined in fuse_ctrl_core_axi_read_out_macros.svh + `fuse_ctrl_core_axi_read_out_TO_RESPONDER_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_responder_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_core_axi_read_out_macros.svh + `fuse_ctrl_core_axi_read_out_FROM_RESPONDER_STRUCT_FUNCTION + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + endfunction + + // **************************************************************************** + // FUNCTION: convert2string() + // This function converts all variables in this class to a single string for + // logfile reporting. + // + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + // UVMF_CHANGE_ME : Customize format if desired. + return $sformatf("core_arready:0x%x core_rdata:0x%x core_rresp:0x%x core_rid:0x%x core_rlast:0x%x core_rvalid:0x%x ",core_arready,core_rdata,core_rresp,core_rid,core_rlast,core_rvalid); + // pragma uvmf custom convert2string end + endfunction + + //******************************************************************* + // FUNCTION: do_print() + // This function is automatically called when the .print() function + // is called on this class. + // + virtual function void do_print(uvm_printer printer); + // pragma uvmf custom do_print begin + // UVMF_CHANGE_ME : Current contents of do_print allows for the use of UVM 1.1d, 1.2 or P1800.2. + // Update based on your own printing preference according to your preferred UVM version + $display(convert2string()); + // pragma uvmf custom do_print end + endfunction + + //******************************************************************* + // FUNCTION: do_compare() + // This function is automatically called when the .compare() function + // is called on this class. + // + virtual function bit do_compare (uvm_object rhs, uvm_comparer comparer); + fuse_ctrl_core_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) RHS; + if (!$cast(RHS,rhs)) return 0; + // pragma uvmf custom do_compare begin + // UVMF_CHANGE_ME : Eliminate comparison of variables not to be used for compare + return (super.do_compare(rhs,comparer) + &&(this.core_arready == RHS.core_arready) + &&(this.core_rdata == RHS.core_rdata) + &&(this.core_rresp == RHS.core_rresp) + &&(this.core_rid == RHS.core_rid) + &&(this.core_rlast == RHS.core_rlast) + &&(this.core_rvalid == RHS.core_rvalid) + ); + // pragma uvmf custom do_compare end + endfunction + + //******************************************************************* + // FUNCTION: do_copy() + // This function is automatically called when the .copy() function + // is called on this class. + // + virtual function void do_copy (uvm_object rhs); + fuse_ctrl_core_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) RHS; + assert($cast(RHS,rhs)); + // pragma uvmf custom do_copy begin + super.do_copy(rhs); + this.core_arready = RHS.core_arready; + this.core_rdata = RHS.core_rdata; + this.core_rresp = RHS.core_rresp; + this.core_rid = RHS.core_rid; + this.core_rlast = RHS.core_rlast; + this.core_rvalid = RHS.core_rvalid; + // pragma uvmf custom do_copy end + endfunction + + // **************************************************************************** + // FUNCTION: add_to_wave() + // This function is used to display variables in this class in the waveform + // viewer. The start_time and end_time variables must be set before this + // function is called. If the start_time and end_time variables are not set + // the transaction will be hidden at 0ns on the waveform display. + // + virtual function void add_to_wave(int transaction_viewing_stream_h); + `ifdef QUESTA + if (transaction_view_h == 0) begin + transaction_view_h = $begin_transaction(transaction_viewing_stream_h,"fuse_ctrl_core_axi_read_out_transaction",start_time); + end + super.add_to_wave(transaction_view_h); + // pragma uvmf custom add_to_wave begin + // UVMF_CHANGE_ME : Color can be applied to transaction entries based on content, example below + // case() + // 1 : $add_color(transaction_view_h,"red"); + // default : $add_color(transaction_view_h,"grey"); + // endcase + // UVMF_CHANGE_ME : Eliminate transaction variables not wanted in transaction viewing in the waveform viewer + $add_attribute(transaction_view_h,core_arready,"core_arready"); + $add_attribute(transaction_view_h,core_rdata,"core_rdata"); + $add_attribute(transaction_view_h,core_rresp,"core_rresp"); + $add_attribute(transaction_view_h,core_rid,"core_rid"); + $add_attribute(transaction_view_h,core_rlast,"core_rlast"); + $add_attribute(transaction_view_h,core_rvalid,"core_rvalid"); + // pragma uvmf custom add_to_wave end + $end_transaction(transaction_view_h,end_time); + $free_transaction(transaction_view_h); + `endif // QUESTA + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_transaction_coverage.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_transaction_coverage.svh new file mode 100644 index 0000000..602b9df --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_transaction_coverage.svh @@ -0,0 +1,104 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class records fuse_ctrl_core_axi_read_out transaction information using +// a covergroup named fuse_ctrl_core_axi_read_out_transaction_cg. An instance of this +// coverage component is instantiated in the uvmf_parameterized_agent +// if the has_coverage flag is set. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_read_out_transaction_coverage #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvm_subscriber #(.T(fuse_ctrl_core_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ))); + + `uvm_component_param_utils( fuse_ctrl_core_axi_read_out_transaction_coverage #( + AW, + DW, + IW, + UW + )) + + T coverage_trans; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + covergroup fuse_ctrl_core_axi_read_out_transaction_cg; + // pragma uvmf custom covergroup begin + // UVMF_CHANGE_ME : Add coverage bins, crosses, exclusions, etc. according to coverage needs. + option.auto_bin_max=1024; + option.per_instance=1; + core_arready: coverpoint coverage_trans.core_arready; + core_rdata: coverpoint coverage_trans.core_rdata; + core_rresp: coverpoint coverage_trans.core_rresp; + core_rid: coverpoint coverage_trans.core_rid; + core_rlast: coverpoint coverage_trans.core_rlast; + core_rvalid: coverpoint coverage_trans.core_rvalid; + // pragma uvmf custom covergroup end + endgroup + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new(string name="", uvm_component parent=null); + super.new(name,parent); + fuse_ctrl_core_axi_read_out_transaction_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that transaction variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + endfunction + + // **************************************************************************** + // FUNCTION : build_phase() + // This function is the standard UVM build_phase. + // + function void build_phase(uvm_phase phase); + fuse_ctrl_core_axi_read_out_transaction_cg.set_inst_name($sformatf("fuse_ctrl_core_axi_read_out_transaction_cg_%s",get_full_name())); + endfunction + + // **************************************************************************** + // FUNCTION: write (T t) + // This function is automatically executed when a transaction arrives on the + // analysis_export. It copies values from the variables in the transaction + // to local variables used to collect functional coverage. + // + virtual function void write (T t); + `uvm_info("COV","Received transaction",UVM_HIGH); + coverage_trans = t; + fuse_ctrl_core_axi_read_out_transaction_cg.sample(); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_typedefs.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_typedefs.svh new file mode 100644 index 0000000..f2a7bdb --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_typedefs.svh @@ -0,0 +1,34 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the host server when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_typedefs_hdl.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_typedefs_hdl.svh new file mode 100644 index 0000000..0d58518 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_typedefs_hdl.svh @@ -0,0 +1,35 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the emulator when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/yaml/fuse_ctrl_core_axi_read_out_interface.yaml b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/yaml/fuse_ctrl_core_axi_read_out_interface.yaml new file mode 100644 index 0000000..9e2244b --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/yaml/fuse_ctrl_core_axi_read_out_interface.yaml @@ -0,0 +1,91 @@ +uvmf: + interfaces: + fuse_ctrl_core_axi_read_out: + clock: clk_i + config_constraints: [] + config_vars: [] + existing_library_component: 'True' + gen_inbound_streaming_driver: 'False' + hdl_pkg_parameters: [] + hdl_typedefs: [] + hvl_pkg_parameters: [] + hvl_typedefs: [] + parameters: + - name: AW + type: int + value: '32' + - name: DW + type: int + value: '32' + - name: IW + type: int + value: '3' + - name: UW + type: int + value: '32' + ports: + - dir: input + name: arready + reset_value: '''bz' + width: '1' + - dir: input + name: rdata + reset_value: '''bz' + width: DW + - dir: input + name: rresp + reset_value: '''bz' + width: '1' + - dir: input + name: rid + reset_value: '''bz' + width: '1' + - dir: input + name: rlast + reset_value: '''bz' + width: '1' + - dir: input + name: rvalid + reset_value: '''bz' + width: '1' + reset: rst_ni + reset_assertion_level: 'False' + transaction_constraints: [] + transaction_vars: + - comment: '' + iscompare: 'True' + isrand: 'False' + name: core_arready + type: logic + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'False' + name: core_rdata + type: logic [DW-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'False' + name: core_rresp + type: axi_pkg::axi_burst_e + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'False' + name: core_rid + type: logic [IW-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'False' + name: core_rlast + type: logic + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'False' + name: core_rvalid + type: logic + unpacked_dimension: '' + use_dpi_link: 'False' diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/.project b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/.project new file mode 100644 index 0000000..b26e81c --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/.project @@ -0,0 +1,30 @@ + + + fuse_ctrl_core_axi_write_in_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/.svproject b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/.svproject new file mode 100644 index 0000000..be11cb6 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/Makefile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/Makefile new file mode 100644 index 0000000..b9ea6af --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/Makefile @@ -0,0 +1,66 @@ +# fuse_ctrl_core_axi_write_in interface packages source +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +fuse_ctrl_core_axi_write_in_PKG = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_write_in_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_filelist_hvl.f + +fuse_ctrl_core_axi_write_in_PKG_HDL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_write_in_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_filelist_hdl.f + +fuse_ctrl_core_axi_write_in_PKG_XRTL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_write_in_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_filelist_xrtl.f + +COMP_fuse_ctrl_core_axi_write_in_PKG_TGT_0 = q_comp_fuse_ctrl_core_axi_write_in_pkg +COMP_fuse_ctrl_core_axi_write_in_PKG_TGT_1 = v_comp_fuse_ctrl_core_axi_write_in_pkg +COMP_fuse_ctrl_core_axi_write_in_PKG_TGT = $(COMP_fuse_ctrl_core_axi_write_in_PKG_TGT_$(USE_VELOCE)) + +comp_fuse_ctrl_core_axi_write_in_pkg: $(COMP_fuse_ctrl_core_axi_write_in_PKG_TGT) + +q_comp_fuse_ctrl_core_axi_write_in_pkg: + $(HDL_COMP_CMD) $(fuse_ctrl_core_axi_write_in_PKG_HDL) + $(HVL_COMP_CMD) $(fuse_ctrl_core_axi_write_in_PKG) + $(HDL_COMP_CMD) $(fuse_ctrl_core_axi_write_in_PKG_XRTL) + +v_comp_fuse_ctrl_core_axi_write_in_pkg: + $(HVL_COMP_CMD) $(fuse_ctrl_core_axi_write_in_PKG_HDL) + $(HVL_COMP_CMD) $(fuse_ctrl_core_axi_write_in_PKG) + $(VELANALYZE_CMD) $(fuse_ctrl_core_axi_write_in_PKG_HDL) + $(VELANALYZE_HVL_CMD) $(fuse_ctrl_core_axi_write_in_PKG) + $(HDL_COMP_CMD) $(fuse_ctrl_core_axi_write_in_PKG_XRTL) + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export fuse_ctrl_core_axi_write_in_IF_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_write_in_pkg/dpi + +C_FILE_COMPILE_LIST_fuse_ctrl_core_axi_write_in_pkg = \ + +O_FILE_COMPILE_LIST_fuse_ctrl_core_axi_write_in_pkg = $(notdir $(C_FILE_COMPILE_LIST_fuse_ctrl_core_axi_write_in_pkg:.c=.o)) + +GCC_COMP_ARGS_fuse_ctrl_core_axi_write_in_pkg += -I$(fuse_ctrl_core_axi_write_in_IF_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_fuse_ctrl_core_axi_write_in_pkg += $(fuse_ctrl_core_axi_write_in_IF_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_fuse_ctrl_core_axi_write_in_pkg += \ + \ + -o .so + +comp_fuse_ctrl_core_axi_write_in_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Interface C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_fuse_ctrl_core_axi_write_in_pkg) $(C_FILE_COMPILE_LIST_fuse_ctrl_core_axi_write_in_pkg) + @echo "--------------------------------" + @echo "Linking Interface C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_fuse_ctrl_core_axi_write_in_pkg) $(O_FILE_COMPILE_LIST_fuse_ctrl_core_axi_write_in_pkg) + @echo "--------------------------------" + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/compile.do b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/compile.do new file mode 100644 index 0000000..a2f727a --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/compile.do @@ -0,0 +1,14 @@ +# Tcl do file for compile of fuse_ctrl_core_axi_write_in interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_write_in_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_filelist_hdl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_write_in_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_filelist_hvl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_write_in_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_filelist_xrtl.f \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in.compile new file mode 100644 index 0000000..328de17 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in.compile @@ -0,0 +1,3 @@ +needs: + - fuse_ctrl_core_axi_write_in_hvl.compile + - fuse_ctrl_core_axi_write_in_hdl.compile diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_bfm.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_bfm.vinfo new file mode 100644 index 0000000..8580294 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_bfm.vinfo @@ -0,0 +1,6 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use fuse_ctrl_core_axi_write_in_pkg_hdl.vinfo ++incdir+@vinfodir +src/fuse_ctrl_core_axi_write_in_if.sv +src/fuse_ctrl_core_axi_write_in_driver_bfm.sv +src/fuse_ctrl_core_axi_write_in_monitor_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_common.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_common.compile new file mode 100644 index 0000000..ebcb42c --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_common.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +incdir: + - . + - ${uvm_path}/src +src: + - fuse_ctrl_core_axi_write_in_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_filelist_hdl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_filelist_hdl.f new file mode 100644 index 0000000..dcea9f3 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_filelist_hdl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_filelist_hvl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_filelist_hvl.f new file mode 100644 index 0000000..0aa6cf4 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_filelist_hvl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_pkg.sv \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_filelist_xrtl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_filelist_xrtl.f new file mode 100644 index 0000000..9729a9f --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_filelist_xrtl.f @@ -0,0 +1,3 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_if.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_monitor_bfm.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_driver_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_hdl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_hdl.compile new file mode 100644 index 0000000..b28a2bd --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_hdl.compile @@ -0,0 +1,9 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ./fuse_ctrl_core_axi_write_in_common.compile +incdir: + - . +src: + - src/fuse_ctrl_core_axi_write_in_if.sv + - src/fuse_ctrl_core_axi_write_in_monitor_bfm.sv + - src/fuse_ctrl_core_axi_write_in_driver_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_hvl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_hvl.compile new file mode 100644 index 0000000..7801ce4 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_hvl.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ./fuse_ctrl_core_axi_write_in_common.compile +incdir: + - . +src: + - fuse_ctrl_core_axi_write_in_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_pkg.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_pkg.sv new file mode 100644 index 0000000..af90383 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_pkg.sv @@ -0,0 +1,91 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - + +// - +// - +// - + +// - +// - +// - + +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_core_axi_write_in_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg_hdl::*; + import uvmf_base_pkg::*; + import fuse_ctrl_core_axi_write_in_pkg_hdl::*; + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + `include "src/fuse_ctrl_core_axi_write_in_macros.svh" + + export fuse_ctrl_core_axi_write_in_pkg_hdl::*; + + + + // Parameters defined as HVL parameters + + `include "src/fuse_ctrl_core_axi_write_in_typedefs.svh" + `include "src/fuse_ctrl_core_axi_write_in_transaction.svh" + + `include "src/fuse_ctrl_core_axi_write_in_configuration.svh" + `include "src/fuse_ctrl_core_axi_write_in_driver.svh" + `include "src/fuse_ctrl_core_axi_write_in_monitor.svh" + + `include "src/fuse_ctrl_core_axi_write_in_transaction_coverage.svh" + `include "src/fuse_ctrl_core_axi_write_in_sequence_base.svh" + `include "src/fuse_ctrl_core_axi_write_in_random_sequence.svh" + + `include "src/fuse_ctrl_core_axi_write_in_responder_sequence.svh" + `include "src/fuse_ctrl_core_axi_write_in2reg_adapter.svh" + + `include "src/fuse_ctrl_core_axi_write_in_agent.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new interface sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the interface package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_pkg.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_pkg.vinfo new file mode 100644 index 0000000..07d2c9a --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_pkg.vinfo @@ -0,0 +1,4 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use fuse_ctrl_core_axi_write_in_pkg_hdl.vinfo ++incdir+@vinfodir +fuse_ctrl_core_axi_write_in_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_pkg_hdl.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_pkg_hdl.sv new file mode 100644 index 0000000..48ee663 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_pkg_hdl.sv @@ -0,0 +1,52 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that needs to be compiled and synthesized +// for running on Veloce. +// +// CONTAINS: +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_core_axi_write_in_pkg_hdl; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HDL parameters + + `include "src/fuse_ctrl_core_axi_write_in_typedefs_hdl.svh" + `include "src/fuse_ctrl_core_axi_write_in_macros.svh" + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_pkg_hdl.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_pkg_hdl.vinfo new file mode 100644 index 0000000..5c56ef5 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_pkg_hdl.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +fuse_ctrl_core_axi_write_in_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_pkg_sve.F b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_pkg_sve.F new file mode 100644 index 0000000..24bdc9f --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_pkg_sve.F @@ -0,0 +1,10 @@ +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + ++incdir+. +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_filelist_hdl.f +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_filelist_hvl.f diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in2reg_adapter.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in2reg_adapter.svh new file mode 100644 index 0000000..c7125cc --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in2reg_adapter.svh @@ -0,0 +1,137 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the UVM register adapter for the fuse_ctrl_core_axi_write_in interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_write_in2reg_adapter #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvm_reg_adapter; + + `uvm_object_param_utils( fuse_ctrl_core_axi_write_in2reg_adapter #( + AW, + DW, + IW, + UW + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //-------------------------------------------------------------------- + // new + //-------------------------------------------------------------------- + function new (string name = "fuse_ctrl_core_axi_write_in2reg_adapter" ); + super.new(name); + // pragma uvmf custom new begin + // UVMF_CHANGE_ME : Configure the adapter regarding byte enables and provides response. + + // Does the protocol the Agent is modeling support byte enables? + // 0 = NO + // 1 = YES + supports_byte_enable = 0; + + // Does the Agent's Driver provide separate response sequence items? + // i.e. Does the driver call seq_item_port.put() + // and do the sequences call get_response()? + // 0 = NO + // 1 = YES + provides_responses = 0; + // pragma uvmf custom new end + + endfunction: new + + //-------------------------------------------------------------------- + // reg2bus + //-------------------------------------------------------------------- + virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw); + + fuse_ctrl_core_axi_write_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) trans_h = fuse_ctrl_core_axi_write_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )::type_id::create("trans_h"); + + // pragma uvmf custom reg2bus begin + // UVMF_CHANGE_ME : Fill in the reg2bus adapter mapping registe fields to protocol fields. + + //Adapt the following for your sequence item type + // trans_h.op = (rw.kind == UVM_READ) ? WB_READ : WB_WRITE; + //Copy over address + // trans_h.addr = rw.addr; + //Copy over write data + // trans_h.data = rw.data; + + // pragma uvmf custom reg2bus end + + // Return the adapted transaction + return trans_h; + + endfunction: reg2bus + + //-------------------------------------------------------------------- + // bus2reg + //-------------------------------------------------------------------- + virtual function void bus2reg(uvm_sequence_item bus_item, + ref uvm_reg_bus_op rw); + fuse_ctrl_core_axi_write_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) trans_h; + if (!$cast(trans_h, bus_item)) begin + `uvm_fatal("ADAPT","Provided bus_item is not of the correct type") + return; + end + // pragma uvmf custom bus2reg begin + // UVMF_CHANGE_ME : Fill in the bus2reg adapter mapping protocol fields to register fields. + //Adapt the following for your sequence item type + //Copy over instruction type + // rw.kind = (trans_h.op == WB_WRITE) ? UVM_WRITE : UVM_READ; + //Copy over address + // rw.addr = trans_h.addr; + //Copy over read data + // rw.data = trans_h.data; + //Check for errors on the bus and return UVM_NOT_OK if there is an error + // rw.status = UVM_IS_OK; + // pragma uvmf custom bus2reg end + + endfunction: bus2reg + +endclass : fuse_ctrl_core_axi_write_in2reg_adapter + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_agent.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_agent.svh new file mode 100644 index 0000000..70333af --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_agent.svh @@ -0,0 +1,102 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: Protocol specific agent class definition +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_write_in_agent #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvmf_parameterized_agent #( + .CONFIG_T(fuse_ctrl_core_axi_write_in_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .DRIVER_T(fuse_ctrl_core_axi_write_in_driver #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .MONITOR_T(fuse_ctrl_core_axi_write_in_monitor #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .COVERAGE_T(fuse_ctrl_core_axi_write_in_transaction_coverage #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .TRANS_T(fuse_ctrl_core_axi_write_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )) + ); + + `uvm_component_param_utils( fuse_ctrl_core_axi_write_in_agent #( + AW, + DW, + IW, + UW + )) + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** + // FUNCTION: build_phase + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + if (configuration.active_passive == ACTIVE) begin + // Place sequencer handle into configuration object + // so that it may be retrieved from configuration + // rather than using uvm_config_db + configuration.sequencer = this.sequencer; + end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_configuration.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_configuration.svh new file mode 100644 index 0000000..a8673e0 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_configuration.svh @@ -0,0 +1,233 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class contains all variables and functions used +// to configure the fuse_ctrl_core_axi_write_in agent and its bfm's. It gets the +// bfm's from the uvm_config_db for use by the agent. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_write_in_configuration #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvmf_parameterized_agent_configuration_base #( + .DRIVER_BFM_BIND_T(virtual fuse_ctrl_core_axi_write_in_driver_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .MONITOR_BFM_BIND_T( virtual fuse_ctrl_core_axi_write_in_monitor_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ))); + + `uvm_object_param_utils( fuse_ctrl_core_axi_write_in_configuration #( + AW, + DW, + IW, + UW + )) + + + // Sequencer handle populated by agent + uvm_sequencer #(fuse_ctrl_core_axi_write_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) ) sequencer; + + //Constraints for the configuration variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + covergroup fuse_ctrl_core_axi_write_in_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + // pragma uvmf custom covergroup end + endgroup + + //******************************************************************* + //******************************************************************* + // Structure used to pass configuration variables to monitor and driver BFM's. + // Use to_struct function to pack variables into structure. + // Use from_struct function to unpack variables from structure. + // This structure is defined in fuse_ctrl_core_axi_write_in_macros.svh + `fuse_ctrl_core_axi_write_in_CONFIGURATION_STRUCT + fuse_ctrl_core_axi_write_in_configuration_s fuse_ctrl_core_axi_write_in_configuration_struct; + //******************************************************************* + // FUNCTION: to_struct() + // This function packs variables into a fuse_ctrl_core_axi_write_in_configuration_s + // structure. The function returns the handle to the fuse_ctrl_core_axi_write_in_configuration_struct. + // This function is defined in fuse_ctrl_core_axi_write_in_macros.svh + `fuse_ctrl_core_axi_write_in_CONFIGURATION_TO_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_struct() + // This function unpacks the struct provided as an argument into + // variables of this class. + // This function is defined in fuse_ctrl_core_axi_write_in_macros.svh + `fuse_ctrl_core_axi_write_in_CONFIGURATION_FROM_STRUCT_FUNCTION + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + // Construct the covergroup for this configuration class + fuse_ctrl_core_axi_write_in_configuration_cg = new; + endfunction + + // **************************************************************************** + // FUNCTION: post_randomize() + // This function is automatically called after the randomize() function + // is executed. + // + function void post_randomize(); + super.post_randomize(); + fuse_ctrl_core_axi_write_in_configuration_cg.sample(); + endfunction + + // **************************************************************************** + // FUNCTION: initialize + // This function causes the configuration to retrieve + // its virtual interface handle from the uvm_config_db. + // This function also makes itself available to its + // agent through the uvm_config_db. + // + // ARGUMENTS: + // uvmf_active_passive_t activity: + // This argument identifies the simulation level + // as either BLOCK, CHIP, SIMULATION, etc. + // + // AGENT_PATH: + // This argument identifies the path to this + // configurations agent. This configuration + // makes itself available to the agent specified + // by agent_path by placing itself into the + // uvm_config_db. + // + // INTERFACE_NAME: + // This argument identifies the string name of + // this configurations BFM's. This string + // name is used to retrieve the driver and + // monitor BFM from the uvm_config_db. + // + virtual function void initialize(uvmf_active_passive_t activity, + string agent_path, + string interface_name); + + super.initialize( activity, agent_path, interface_name); + // The covergroup is given the same name as the interface + fuse_ctrl_core_axi_write_in_configuration_cg.set_inst_name(interface_name); + + // This configuration places itself into the uvm_config_db for the agent, identified by the agent_path variable, to retrieve. + uvm_config_db #( fuse_ctrl_core_axi_write_in_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + )::set( null ,agent_path,UVMF_AGENT_CONFIG, this ); + + // This configuration also places itself in the config db using the same identifier used by the interface. This allows users to access + // configuration variables and the interface through the bfm api class rather than directly accessing the BFM. This is useful for + // accessingthe BFM when using Veloce + uvm_config_db #( fuse_ctrl_core_axi_write_in_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + )::set( null ,UVMF_CONFIGURATIONS, interface_name, this ); + + fuse_ctrl_core_axi_write_in_configuration_cg.set_inst_name($sformatf("fuse_ctrl_core_axi_write_in_configuration_cg_%s",get_full_name())); + +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. + `uvm_info("CFG", + $psprintf("The agent at '%s' is using interface named %s has the following parameters: AW=%x DW=%x IW=%x UW=%x ", agent_path, interface_name, AW ,DW ,IW ,UW ), + UVM_DEBUG) + + // pragma uvmf custom initialize begin + // This controls whether or not the agent returns a transaction handle in the driver when calling + // item_done() back into the sequencer or not. If set to 1, a transaction is sent back which means + // the sequence on the other end must use the get_response() part of the driver/sequence API. If + // this doesn't occur, there will eventually be response_queue overflow errors during the test. + return_transaction_response = 1'b0; + + // pragma uvmf custom initialize end + + endfunction + + // **************************************************************************** + // TASK: wait_for_reset + // *[Required]* Blocks until reset is released. The wait_for_reset operation is performed + // by a task in the monitor bfm. + virtual task wait_for_reset(); + monitor_bfm.wait_for_reset(); + endtask + + // **************************************************************************** + // TASK: wait_for_num_clocks + // *[Required]* Blocks until specified number of clocks have elapsed. The wait_for_num_clocks + // operation is performed by a task in the monitor bfm. + virtual task wait_for_num_clocks(int clocks); + monitor_bfm.wait_for_num_clocks(clocks); + endtask + + // **************************************************************************** + // FUNCTION : convert2string() + // This function is used to convert variables in this class into a string for log messaging. + // + virtual function string convert2string (); + // pragma uvmf custom convert2string begin + return $sformatf(""); + // pragma uvmf custom convert2string end + endfunction + + // **************************************************************************** + // FUNCTION: get_sequencer + function uvm_sequencer #(fuse_ctrl_core_axi_write_in_transaction#( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )) get_sequencer(); + return sequencer; + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_driver.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_driver.svh new file mode 100644 index 0000000..f5c3517 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_driver.svh @@ -0,0 +1,135 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class passes transactions between the sequencer +// and the BFM driver interface. It accesses the driver BFM +// through the bfm handle. This driver +// passes transactions to the driver BFM through the access +// task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_write_in_driver #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvmf_driver_base #( + .CONFIG_T(fuse_ctrl_core_axi_write_in_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) ), + .BFM_BIND_T(virtual fuse_ctrl_core_axi_write_in_driver_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) ), + .REQ(fuse_ctrl_core_axi_write_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) ), + .RSP(fuse_ctrl_core_axi_write_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) )); + + `uvm_component_param_utils( fuse_ctrl_core_axi_write_in_driver #( + AW, + DW, + IW, + UW + )) +//******************************************************************* +// Macros that define structs located in fuse_ctrl_core_axi_write_in_macros.svh +//******************************************************************* +// Initiator macro used by fuse_ctrl_core_axi_write_in_driver and fuse_ctrl_core_axi_write_in_driver_bfm +// to communicate initiator driven data to fuse_ctrl_core_axi_write_in_driver_bfm. +`fuse_ctrl_core_axi_write_in_INITIATOR_STRUCT + fuse_ctrl_core_axi_write_in_initiator_s fuse_ctrl_core_axi_write_in_initiator_struct; +//******************************************************************* +// Responder macro used by fuse_ctrl_core_axi_write_in_driver and fuse_ctrl_core_axi_write_in_driver_bfm +// to communicate Responder driven data to fuse_ctrl_core_axi_write_in_driver_bfm. +`fuse_ctrl_core_axi_write_in_RESPONDER_STRUCT + fuse_ctrl_core_axi_write_in_responder_s fuse_ctrl_core_axi_write_in_responder_struct; + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent=null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the driver BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// driver BFM. This allows the driver BFM to call tasks and function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// **************************************************************************** +// This task is called by the run_phase in uvmf_driver_base. + virtual task access( inout REQ txn ); +// pragma uvmf custom access begin + if (configuration.initiator_responder==RESPONDER) begin + // Complete current transfer and wait for next transfer + bfm.respond_and_wait_for_next_transfer( + fuse_ctrl_core_axi_write_in_initiator_struct, + txn.to_responder_struct() + ); + // Unpack information about initiated transfer received by this responder + txn.from_initiator_struct(fuse_ctrl_core_axi_write_in_initiator_struct); + end else begin + // Initiate a transfer and get response + bfm.initiate_and_get_response( + txn.to_initiator_struct(), + fuse_ctrl_core_axi_write_in_responder_struct + ); + // Unpack transfer response information received by this initiator + txn.from_responder_struct(fuse_ctrl_core_axi_write_in_responder_struct); + end +// pragma uvmf custom access end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_driver_bfm.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_driver_bfm.sv new file mode 100644 index 0000000..44ae1bb --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_driver_bfm.sv @@ -0,0 +1,427 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This interface performs the fuse_ctrl_core_axi_write_in signal driving. It is +// accessed by the uvm fuse_ctrl_core_axi_write_in driver through a virtual interface +// handle in the fuse_ctrl_core_axi_write_in configuration. It drives the singals passed +// in through the port connection named bus of type fuse_ctrl_core_axi_write_in_if. +// +// Input signals from the fuse_ctrl_core_axi_write_in_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// This bfm drives signals with a _o suffix. These signals +// are driven onto signals within fuse_ctrl_core_axi_write_in_if based on INITIATOR/RESPONDER and/or +// ARBITRATION/GRANT status. +// +// The output signal connections are as follows: +// signal_o -> bus.signal +// +// +// Interface functions and tasks used by UVM components: +// +// configure: +// This function gets configuration attributes from the +// UVM driver to set any required BFM configuration +// variables such as 'initiator_responder'. +// +// initiate_and_get_response: +// This task is used to perform signaling activity for initiating +// a protocol transfer. The task initiates the transfer, using +// input data from the initiator struct. Then the task captures +// response data, placing the data into the response struct. +// The response struct is returned to the driver class. +// +// respond_and_wait_for_next_transfer: +// This task is used to complete a current transfer as a responder +// and then wait for the initiator to start the next transfer. +// The task uses data in the responder struct to drive protocol +// signals to complete the transfer. The task then waits for +// the next transfer. Once the next transfer begins, data from +// the initiator is placed into the initiator struct and sent +// to the responder sequence for processing to determine +// what data to respond with. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_core_axi_write_in_pkg_hdl::*; +`include "src/fuse_ctrl_core_axi_write_in_macros.svh" + +interface fuse_ctrl_core_axi_write_in_driver_bfm #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + (fuse_ctrl_core_axi_write_in_if bus); + // The following pragma and additional ones in-lined further below are for running this BFM on Veloce + // pragma attribute fuse_ctrl_core_axi_write_in_driver_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: AW=%x DW=%x IW=%x UW=%x ", AW,DW,IW,UW), + UVM_DEBUG) +end +`endif + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + tri clk_i_i; + tri rst_ni_i; + + // Signal list (all signals are capable of being inputs and outputs for the sake + // of supporting both INITIATOR and RESPONDER mode operation. Expectation is that + // directionality in the config file was from the point-of-view of the INITIATOR + + // INITIATOR mode input signals + + // INITIATOR mode output signals + tri [AW-1:0] awaddr_i; + reg [AW-1:0] awaddr_o = 'bz; + tri [$bits(axi_pkg::axi_burst_e)-1:0] awburst_i; + reg [$bits(axi_pkg::axi_burst_e)-1:0] awburst_o = 'bz; + tri [2:0] awsize_i; + reg [2:0] awsize_o = 'bz; + tri [7:0] awlen_i; + reg [7:0] awlen_o = 'bz; + tri [UW-1:0] awuser_i; + reg [UW-1:0] awuser_o = 'bz; + tri [UW-1:0] awid_i; + reg [UW-1:0] awid_o = 'bz; + tri awlock_i; + reg awlock_o = 'bz; + tri awvalid_i; + reg awvalid_o = 'bz; + tri [DW-1:0] wdata_i; + reg [DW-1:0] wdata_o = 'bz; + tri [DW/8-1:0] wstrb_i; + reg [DW/8-1:0] wstrb_o = 'bz; + tri wvalid_i; + reg wvalid_o = 'bz; + tri wlast_i; + reg wlast_o = 'bz; + tri bready_i; + reg bready_o = 'bz; + + // Bi-directional signals + + + assign clk_i_i = bus.clk_i; + assign rst_ni_i = bus.rst_ni; + + // These are signals marked as 'input' by the config file, but the signals will be + // driven by this BFM if put into RESPONDER mode (flipping all signal directions around) + + + // These are signals marked as 'output' by the config file, but the outputs will + // not be driven by this BFM unless placed in INITIATOR mode. + assign bus.awaddr = (initiator_responder == INITIATOR) ? awaddr_o : 'bz; + assign awaddr_i = bus.awaddr; + assign bus.awburst = (initiator_responder == INITIATOR) ? awburst_o : 'bz; + assign awburst_i = bus.awburst; + assign bus.awsize = (initiator_responder == INITIATOR) ? awsize_o : 'bz; + assign awsize_i = bus.awsize; + assign bus.awlen = (initiator_responder == INITIATOR) ? awlen_o : 'bz; + assign awlen_i = bus.awlen; + assign bus.awuser = (initiator_responder == INITIATOR) ? awuser_o : 'bz; + assign awuser_i = bus.awuser; + assign bus.awid = (initiator_responder == INITIATOR) ? awid_o : 'bz; + assign awid_i = bus.awid; + assign bus.awlock = (initiator_responder == INITIATOR) ? awlock_o : 'bz; + assign awlock_i = bus.awlock; + assign bus.awvalid = (initiator_responder == INITIATOR) ? awvalid_o : 'bz; + assign awvalid_i = bus.awvalid; + assign bus.wdata = (initiator_responder == INITIATOR) ? wdata_o : 'bz; + assign wdata_i = bus.wdata; + assign bus.wstrb = (initiator_responder == INITIATOR) ? wstrb_o : 'bz; + assign wstrb_i = bus.wstrb; + assign bus.wvalid = (initiator_responder == INITIATOR) ? wvalid_o : 'bz; + assign wvalid_i = bus.wvalid; + assign bus.wlast = (initiator_responder == INITIATOR) ? wlast_o : 'bz; + assign wlast_i = bus.wlast; + assign bus.bready = (initiator_responder == INITIATOR) ? bready_o : 'bz; + assign bready_i = bus.bready; + + // Proxy handle to UVM driver + fuse_ctrl_core_axi_write_in_pkg::fuse_ctrl_core_axi_write_in_driver #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) proxy; + // pragma tbx oneway proxy.my_function_name_in_uvm_driver + + // **************************************************************************** + // **************************************************************************** + // Macros that define structs located in fuse_ctrl_core_axi_write_in_macros.svh + // **************************************************************************** + // Struct for passing configuration data from fuse_ctrl_core_axi_write_in_driver to this BFM + // **************************************************************************** + `fuse_ctrl_core_axi_write_in_CONFIGURATION_STRUCT + // **************************************************************************** + // Structs for INITIATOR and RESPONDER data flow + //******************************************************************* + // Initiator macro used by fuse_ctrl_core_axi_write_in_driver and fuse_ctrl_core_axi_write_in_driver_bfm + // to communicate initiator driven data to fuse_ctrl_core_axi_write_in_driver_bfm. + `fuse_ctrl_core_axi_write_in_INITIATOR_STRUCT + fuse_ctrl_core_axi_write_in_initiator_s initiator_struct; + // Responder macro used by fuse_ctrl_core_axi_write_in_driver and fuse_ctrl_core_axi_write_in_driver_bfm + // to communicate Responder driven data to fuse_ctrl_core_axi_write_in_driver_bfm. + `fuse_ctrl_core_axi_write_in_RESPONDER_STRUCT + fuse_ctrl_core_axi_write_in_responder_s responder_struct; + + // **************************************************************************** +// pragma uvmf custom reset_condition_and_response begin + // Always block used to return signals to reset value upon assertion of reset + always @( negedge rst_ni_i ) + begin + // RESPONDER mode output signals + // INITIATOR mode output signals + awaddr_o <= 'bz; + awburst_o <= 'bz; + awsize_o <= 'bz; + awlen_o <= 'bz; + awuser_o <= 'bz; + awid_o <= 'bz; + awlock_o <= 'bz; + awvalid_o <= 'bz; + wdata_o <= 'bz; + wstrb_o <= 'bz; + wvalid_o <= 'bz; + wlast_o <= 'bz; + bready_o <= 'bz; + // Bi-directional signals + + end +// pragma uvmf custom reset_condition_and_response end + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the driver BFM. It is called by the driver within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the driver BFM needs to be aware of the new configuration + // variables. + // + + function void configure(fuse_ctrl_core_axi_write_in_configuration_s fuse_ctrl_core_axi_write_in_configuration_arg); // pragma tbx xtf + initiator_responder = fuse_ctrl_core_axi_write_in_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + +// pragma uvmf custom initiate_and_get_response begin +// **************************************************************************** +// UVMF_CHANGE_ME +// This task is used by an initator. The task first initiates a transfer then +// waits for the responder to complete the transfer. + task initiate_and_get_response( + // This argument passes transaction variables used by an initiator + // to perform the initial part of a protocol transfer. The values + // come from a sequence item created in a sequence. + input fuse_ctrl_core_axi_write_in_initiator_s fuse_ctrl_core_axi_write_in_initiator_struct, + // This argument is used to send data received from the responder + // back to the sequence item. The sequence item is returned to the sequence. + output fuse_ctrl_core_axi_write_in_responder_s fuse_ctrl_core_axi_write_in_responder_struct + );// pragma tbx xtf + // + // Members within the fuse_ctrl_core_axi_write_in_initiator_struct: + // logic [AW-1:0] core_awaddr ; + // logic core_awvalid ; + // logic [$bits(axi_pkg::axi_burst_e)] core_awburst ; + // logic [2:0] core_awsize ; + // logic [7:0] core_awlen ; + // logic [UW-1:0] core_awuser ; + // logic [IW-1:0] core_awid ; + // logic core_awlock ; + // logic [DW-1:0] core_wdata ; + // logic [DW/8 - 1:0] core_wstrb ; + // logic core_wvalid ; + // logic core_wlast ; + // logic core_bready ; + // Members within the fuse_ctrl_core_axi_write_in_responder_struct: + // logic [AW-1:0] core_awaddr ; + // logic core_awvalid ; + // logic [$bits(axi_pkg::axi_burst_e)] core_awburst ; + // logic [2:0] core_awsize ; + // logic [7:0] core_awlen ; + // logic [UW-1:0] core_awuser ; + // logic [IW-1:0] core_awid ; + // logic core_awlock ; + // logic [DW-1:0] core_wdata ; + // logic [DW/8 - 1:0] core_wstrb ; + // logic core_wvalid ; + // logic core_wlast ; + // logic core_bready ; + initiator_struct = fuse_ctrl_core_axi_write_in_initiator_struct; + // + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clk_i_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available initiator input and inout signals listed. + // Initiator input signals + // Initiator inout signals + // How to assign a signal from an initiator struct member named xyz. + // All available initiator output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Initiator output signals + // awaddr_o <= fuse_ctrl_core_axi_write_in_initiator_struct.xyz; // [AW-1:0] + // awburst_o <= fuse_ctrl_core_axi_write_in_initiator_struct.xyz; // [$bits(axi_pkg::axi_burst_e)-1:0] + // awsize_o <= fuse_ctrl_core_axi_write_in_initiator_struct.xyz; // [2:0] + // awlen_o <= fuse_ctrl_core_axi_write_in_initiator_struct.xyz; // [7:0] + // awuser_o <= fuse_ctrl_core_axi_write_in_initiator_struct.xyz; // [UW-1:0] + // awid_o <= fuse_ctrl_core_axi_write_in_initiator_struct.xyz; // [UW-1:0] + // awlock_o <= fuse_ctrl_core_axi_write_in_initiator_struct.xyz; // + // awvalid_o <= fuse_ctrl_core_axi_write_in_initiator_struct.xyz; // + // wdata_o <= fuse_ctrl_core_axi_write_in_initiator_struct.xyz; // [DW-1:0] + // wstrb_o <= fuse_ctrl_core_axi_write_in_initiator_struct.xyz; // [DW/8-1:0] + // wvalid_o <= fuse_ctrl_core_axi_write_in_initiator_struct.xyz; // + // wlast_o <= fuse_ctrl_core_axi_write_in_initiator_struct.xyz; // + // bready_o <= fuse_ctrl_core_axi_write_in_initiator_struct.xyz; // + // Initiator inout signals + // Initiate a transfer using the data received. + @(posedge clk_i_i); + @(posedge clk_i_i); + // Wait for the responder to complete the transfer then place the responder data into + // fuse_ctrl_core_axi_write_in_responder_struct. + @(posedge clk_i_i); + @(posedge clk_i_i); + responder_struct = fuse_ctrl_core_axi_write_in_responder_struct; + endtask +// pragma uvmf custom initiate_and_get_response end + +// pragma uvmf custom respond_and_wait_for_next_transfer begin +// **************************************************************************** +// The first_transfer variable is used to prevent completing a transfer in the +// first call to this task. For the first call to this task, there is not +// current transfer to complete. +bit first_transfer=1; + +// UVMF_CHANGE_ME +// This task is used by a responder. The task first completes the current +// transfer in progress then waits for the initiator to start the next transfer. + task respond_and_wait_for_next_transfer( + // This argument is used to send data received from the initiator + // back to the sequence item. The sequence determines how to respond. + output fuse_ctrl_core_axi_write_in_initiator_s fuse_ctrl_core_axi_write_in_initiator_struct, + // This argument passes transaction variables used by a responder + // to complete a protocol transfer. The values come from a sequence item. + input fuse_ctrl_core_axi_write_in_responder_s fuse_ctrl_core_axi_write_in_responder_struct + );// pragma tbx xtf + // Variables within the fuse_ctrl_core_axi_write_in_initiator_struct: + // logic [AW-1:0] core_awaddr ; + // logic core_awvalid ; + // logic [$bits(axi_pkg::axi_burst_e)] core_awburst ; + // logic [2:0] core_awsize ; + // logic [7:0] core_awlen ; + // logic [UW-1:0] core_awuser ; + // logic [IW-1:0] core_awid ; + // logic core_awlock ; + // logic [DW-1:0] core_wdata ; + // logic [DW/8 - 1:0] core_wstrb ; + // logic core_wvalid ; + // logic core_wlast ; + // logic core_bready ; + // Variables within the fuse_ctrl_core_axi_write_in_responder_struct: + // logic [AW-1:0] core_awaddr ; + // logic core_awvalid ; + // logic [$bits(axi_pkg::axi_burst_e)] core_awburst ; + // logic [2:0] core_awsize ; + // logic [7:0] core_awlen ; + // logic [UW-1:0] core_awuser ; + // logic [IW-1:0] core_awid ; + // logic core_awlock ; + // logic [DW-1:0] core_wdata ; + // logic [DW/8 - 1:0] core_wstrb ; + // logic core_wvalid ; + // logic core_wlast ; + // logic core_bready ; + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clk_i_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available responder input and inout signals listed. + // Responder input signals + // fuse_ctrl_core_axi_write_in_responder_struct.xyz = awaddr_i; // [AW-1:0] + // fuse_ctrl_core_axi_write_in_responder_struct.xyz = awburst_i; // [$bits(axi_pkg::axi_burst_e)-1:0] + // fuse_ctrl_core_axi_write_in_responder_struct.xyz = awsize_i; // [2:0] + // fuse_ctrl_core_axi_write_in_responder_struct.xyz = awlen_i; // [7:0] + // fuse_ctrl_core_axi_write_in_responder_struct.xyz = awuser_i; // [UW-1:0] + // fuse_ctrl_core_axi_write_in_responder_struct.xyz = awid_i; // [UW-1:0] + // fuse_ctrl_core_axi_write_in_responder_struct.xyz = awlock_i; // + // fuse_ctrl_core_axi_write_in_responder_struct.xyz = awvalid_i; // + // fuse_ctrl_core_axi_write_in_responder_struct.xyz = wdata_i; // [DW-1:0] + // fuse_ctrl_core_axi_write_in_responder_struct.xyz = wstrb_i; // [DW/8-1:0] + // fuse_ctrl_core_axi_write_in_responder_struct.xyz = wvalid_i; // + // fuse_ctrl_core_axi_write_in_responder_struct.xyz = wlast_i; // + // fuse_ctrl_core_axi_write_in_responder_struct.xyz = bready_i; // + // Responder inout signals + // How to assign a signal, named xyz, from an initiator struct member. + // All available responder output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Responder output signals + // Responder inout signals + + @(posedge clk_i_i); + if (!first_transfer) begin + // Perform transfer response here. + // Reply using data recieved in the fuse_ctrl_core_axi_write_in_responder_struct. + @(posedge clk_i_i); + // Reply using data recieved in the transaction handle. + @(posedge clk_i_i); + end + // Wait for next transfer then gather info from intiator about the transfer. + // Place the data into the fuse_ctrl_core_axi_write_in_initiator_struct. + @(posedge clk_i_i); + @(posedge clk_i_i); + first_transfer = 0; + endtask +// pragma uvmf custom respond_and_wait_for_next_transfer end + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_if.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_if.sv new file mode 100644 index 0000000..b7e16e6 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_if.sv @@ -0,0 +1,143 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface contains the fuse_ctrl_core_axi_write_in interface signals. +// It is instantiated once per fuse_ctrl_core_axi_write_in bus. Bus Functional Models, +// BFM's named fuse_ctrl_core_axi_write_in_driver_bfm, are used to drive signals on the bus. +// BFM's named fuse_ctrl_core_axi_write_in_monitor_bfm are used to monitor signals on the +// bus. This interface signal bundle is passed in the port list of +// the BFM in order to give the BFM access to the signals in this +// interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// This template can be used to connect a DUT to these signals +// +// .dut_signal_port(fuse_ctrl_core_axi_write_in_bus.awaddr), // Agent output +// .dut_signal_port(fuse_ctrl_core_axi_write_in_bus.awburst), // Agent output +// .dut_signal_port(fuse_ctrl_core_axi_write_in_bus.awsize), // Agent output +// .dut_signal_port(fuse_ctrl_core_axi_write_in_bus.awlen), // Agent output +// .dut_signal_port(fuse_ctrl_core_axi_write_in_bus.awuser), // Agent output +// .dut_signal_port(fuse_ctrl_core_axi_write_in_bus.awid), // Agent output +// .dut_signal_port(fuse_ctrl_core_axi_write_in_bus.awlock), // Agent output +// .dut_signal_port(fuse_ctrl_core_axi_write_in_bus.awvalid), // Agent output +// .dut_signal_port(fuse_ctrl_core_axi_write_in_bus.wdata), // Agent output +// .dut_signal_port(fuse_ctrl_core_axi_write_in_bus.wstrb), // Agent output +// .dut_signal_port(fuse_ctrl_core_axi_write_in_bus.wvalid), // Agent output +// .dut_signal_port(fuse_ctrl_core_axi_write_in_bus.wlast), // Agent output +// .dut_signal_port(fuse_ctrl_core_axi_write_in_bus.bready), // Agent output + +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_core_axi_write_in_pkg_hdl::*; + +interface fuse_ctrl_core_axi_write_in_if #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + + ( + input tri clk_i, + input tri rst_ni, + inout tri [AW-1:0] awaddr, + inout tri [$bits(axi_pkg::axi_burst_e)-1:0] awburst, + inout tri [2:0] awsize, + inout tri [7:0] awlen, + inout tri [UW-1:0] awuser, + inout tri [UW-1:0] awid, + inout tri awlock, + inout tri awvalid, + inout tri [DW-1:0] wdata, + inout tri [DW/8-1:0] wstrb, + inout tri wvalid, + inout tri wlast, + inout tri bready + ); + +modport monitor_port + ( + input clk_i, + input rst_ni, + input awaddr, + input awburst, + input awsize, + input awlen, + input awuser, + input awid, + input awlock, + input awvalid, + input wdata, + input wstrb, + input wvalid, + input wlast, + input bready + ); + +modport initiator_port + ( + input clk_i, + input rst_ni, + output awaddr, + output awburst, + output awsize, + output awlen, + output awuser, + output awid, + output awlock, + output awvalid, + output wdata, + output wstrb, + output wvalid, + output wlast, + output bready + ); + +modport responder_port + ( + input clk_i, + input rst_ni, + input awaddr, + input awburst, + input awsize, + input awlen, + input awuser, + input awid, + input awlock, + input awvalid, + input wdata, + input wstrb, + input wvalid, + input wlast, + input bready + ); + + +// pragma uvmf custom interface_item_additional begin +// pragma uvmf custom interface_item_additional end + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_infact_coverage_strategy.csv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_infact_coverage_strategy.csv new file mode 100644 index 0000000..1c218e1 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_infact_coverage_strategy.csv @@ -0,0 +1,6 @@ +Global +auto_bin_max, 64 + +Name,Type,Include +rand_fields,coverpoint,=rand *.** + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_macros.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_macros.svh new file mode 100644 index 0000000..c925c15 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_macros.svh @@ -0,0 +1,243 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains macros used with the fuse_ctrl_core_axi_write_in package. +// These macros include packed struct definitions. These structs are +// used to pass data between classes, hvl, and BFM's, hdl. Use of +// structs are more efficient and simpler to modify. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_struct +// and from_struct methods defined in the macros below that are used in +// the fuse_ctrl_core_axi_write_in_configuration class. +// + `define fuse_ctrl_core_axi_write_in_CONFIGURATION_STRUCT \ +typedef struct packed { \ + uvmf_active_passive_t active_passive; \ + uvmf_initiator_responder_t initiator_responder; \ + } fuse_ctrl_core_axi_write_in_configuration_s; + + `define fuse_ctrl_core_axi_write_in_CONFIGURATION_TO_STRUCT_FUNCTION \ + virtual function fuse_ctrl_core_axi_write_in_configuration_s to_struct();\ + fuse_ctrl_core_axi_write_in_configuration_struct = \ + {\ + this.active_passive,\ + this.initiator_responder\ + };\ + return ( fuse_ctrl_core_axi_write_in_configuration_struct );\ + endfunction + + `define fuse_ctrl_core_axi_write_in_CONFIGURATION_FROM_STRUCT_FUNCTION \ + virtual function void from_struct(fuse_ctrl_core_axi_write_in_configuration_s fuse_ctrl_core_axi_write_in_configuration_struct);\ + {\ + this.active_passive,\ + this.initiator_responder \ + } = fuse_ctrl_core_axi_write_in_configuration_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_monitor_struct +// and from_monitor_struct methods of the fuse_ctrl_core_axi_write_in_transaction class. +// + `define fuse_ctrl_core_axi_write_in_MONITOR_STRUCT typedef struct packed { \ + logic [AW-1:0] core_awaddr ; \ + logic core_awvalid ; \ + logic [$bits(axi_pkg::axi_burst_e)] core_awburst ; \ + logic [2:0] core_awsize ; \ + logic [7:0] core_awlen ; \ + logic [UW-1:0] core_awuser ; \ + logic [IW-1:0] core_awid ; \ + logic core_awlock ; \ + logic [DW-1:0] core_wdata ; \ + logic [DW/8 - 1:0] core_wstrb ; \ + logic core_wvalid ; \ + logic core_wlast ; \ + logic core_bready ; \ + } fuse_ctrl_core_axi_write_in_monitor_s; + + `define fuse_ctrl_core_axi_write_in_TO_MONITOR_STRUCT_FUNCTION \ + virtual function fuse_ctrl_core_axi_write_in_monitor_s to_monitor_struct();\ + fuse_ctrl_core_axi_write_in_monitor_struct = \ + { \ + this.core_awaddr , \ + this.core_awvalid , \ + this.core_awburst , \ + this.core_awsize , \ + this.core_awlen , \ + this.core_awuser , \ + this.core_awid , \ + this.core_awlock , \ + this.core_wdata , \ + this.core_wstrb , \ + this.core_wvalid , \ + this.core_wlast , \ + this.core_bready \ + };\ + return ( fuse_ctrl_core_axi_write_in_monitor_struct);\ + endfunction\ + + `define fuse_ctrl_core_axi_write_in_FROM_MONITOR_STRUCT_FUNCTION \ + virtual function void from_monitor_struct(fuse_ctrl_core_axi_write_in_monitor_s fuse_ctrl_core_axi_write_in_monitor_struct);\ + {\ + this.core_awaddr , \ + this.core_awvalid , \ + this.core_awburst , \ + this.core_awsize , \ + this.core_awlen , \ + this.core_awuser , \ + this.core_awid , \ + this.core_awlock , \ + this.core_wdata , \ + this.core_wstrb , \ + this.core_wvalid , \ + this.core_wlast , \ + this.core_bready \ + } = fuse_ctrl_core_axi_write_in_monitor_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_initiator_struct +// and from_initiator_struct methods of the fuse_ctrl_core_axi_write_in_transaction class. +// Also update the comments in the driver BFM. +// + `define fuse_ctrl_core_axi_write_in_INITIATOR_STRUCT typedef struct packed { \ + logic [AW-1:0] core_awaddr ; \ + logic core_awvalid ; \ + logic [$bits(axi_pkg::axi_burst_e)] core_awburst ; \ + logic [2:0] core_awsize ; \ + logic [7:0] core_awlen ; \ + logic [UW-1:0] core_awuser ; \ + logic [IW-1:0] core_awid ; \ + logic core_awlock ; \ + logic [DW-1:0] core_wdata ; \ + logic [DW/8 - 1:0] core_wstrb ; \ + logic core_wvalid ; \ + logic core_wlast ; \ + logic core_bready ; \ + } fuse_ctrl_core_axi_write_in_initiator_s; + + `define fuse_ctrl_core_axi_write_in_TO_INITIATOR_STRUCT_FUNCTION \ + virtual function fuse_ctrl_core_axi_write_in_initiator_s to_initiator_struct();\ + fuse_ctrl_core_axi_write_in_initiator_struct = \ + {\ + this.core_awaddr , \ + this.core_awvalid , \ + this.core_awburst , \ + this.core_awsize , \ + this.core_awlen , \ + this.core_awuser , \ + this.core_awid , \ + this.core_awlock , \ + this.core_wdata , \ + this.core_wstrb , \ + this.core_wvalid , \ + this.core_wlast , \ + this.core_bready \ + };\ + return ( fuse_ctrl_core_axi_write_in_initiator_struct);\ + endfunction + + `define fuse_ctrl_core_axi_write_in_FROM_INITIATOR_STRUCT_FUNCTION \ + virtual function void from_initiator_struct(fuse_ctrl_core_axi_write_in_initiator_s fuse_ctrl_core_axi_write_in_initiator_struct);\ + {\ + this.core_awaddr , \ + this.core_awvalid , \ + this.core_awburst , \ + this.core_awsize , \ + this.core_awlen , \ + this.core_awuser , \ + this.core_awid , \ + this.core_awlock , \ + this.core_wdata , \ + this.core_wstrb , \ + this.core_wvalid , \ + this.core_wlast , \ + this.core_bready \ + } = fuse_ctrl_core_axi_write_in_initiator_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_responder_struct +// and from_responder_struct methods of the fuse_ctrl_core_axi_write_in_transaction class. +// Also update the comments in the driver BFM. +// + `define fuse_ctrl_core_axi_write_in_RESPONDER_STRUCT typedef struct packed { \ + logic [AW-1:0] core_awaddr ; \ + logic core_awvalid ; \ + logic [$bits(axi_pkg::axi_burst_e)] core_awburst ; \ + logic [2:0] core_awsize ; \ + logic [7:0] core_awlen ; \ + logic [UW-1:0] core_awuser ; \ + logic [IW-1:0] core_awid ; \ + logic core_awlock ; \ + logic [DW-1:0] core_wdata ; \ + logic [DW/8 - 1:0] core_wstrb ; \ + logic core_wvalid ; \ + logic core_wlast ; \ + logic core_bready ; \ + } fuse_ctrl_core_axi_write_in_responder_s; + + `define fuse_ctrl_core_axi_write_in_TO_RESPONDER_STRUCT_FUNCTION \ + virtual function fuse_ctrl_core_axi_write_in_responder_s to_responder_struct();\ + fuse_ctrl_core_axi_write_in_responder_struct = \ + {\ + this.core_awaddr , \ + this.core_awvalid , \ + this.core_awburst , \ + this.core_awsize , \ + this.core_awlen , \ + this.core_awuser , \ + this.core_awid , \ + this.core_awlock , \ + this.core_wdata , \ + this.core_wstrb , \ + this.core_wvalid , \ + this.core_wlast , \ + this.core_bready \ + };\ + return ( fuse_ctrl_core_axi_write_in_responder_struct);\ + endfunction + + `define fuse_ctrl_core_axi_write_in_FROM_RESPONDER_STRUCT_FUNCTION \ + virtual function void from_responder_struct(fuse_ctrl_core_axi_write_in_responder_s fuse_ctrl_core_axi_write_in_responder_struct);\ + {\ + this.core_awaddr , \ + this.core_awvalid , \ + this.core_awburst , \ + this.core_awsize , \ + this.core_awlen , \ + this.core_awuser , \ + this.core_awid , \ + this.core_awlock , \ + this.core_wdata , \ + this.core_wstrb , \ + this.core_wvalid , \ + this.core_wlast , \ + this.core_bready \ + } = fuse_ctrl_core_axi_write_in_responder_struct;\ + endfunction +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_monitor.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_monitor.svh new file mode 100644 index 0000000..f9196a4 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_monitor.svh @@ -0,0 +1,126 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class receives fuse_ctrl_core_axi_write_in transactions observed by the +// fuse_ctrl_core_axi_write_in monitor BFM and broadcasts them through the analysis port +// on the agent. It accesses the monitor BFM through the monitor +// task. This UVM component captures transactions +// for viewing in the waveform viewer if the +// enable_transaction_viewing flag is set in the configuration. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_write_in_monitor #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvmf_monitor_base #( + .CONFIG_T(fuse_ctrl_core_axi_write_in_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .BFM_BIND_T(virtual fuse_ctrl_core_axi_write_in_monitor_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .TRANS_T(fuse_ctrl_core_axi_write_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ))); + + `uvm_component_param_utils( fuse_ctrl_core_axi_write_in_monitor #( + AW, + DW, + IW, + UW + )) + +// Structure used to pass data from monitor BFM to monitor class in agent. +// Use to_monitor_struct function to pack transaction variables into structure. +// Use from_monitor_struct function to unpack transaction variables from structure. +`fuse_ctrl_core_axi_write_in_MONITOR_STRUCT + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the monitor BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// monitor BFM. This allows the monitor BFM to call the notify_transaction +// function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// *************************************************************************** + virtual task run_phase(uvm_phase phase); + // Start monitor BFM thread and don't call super.run() in order to + // override the default monitor proxy 'pull' behavior with the more + // emulation-friendly BFM 'push' approach using the notify_transaction + // function below + bfm.start_monitoring(); + endtask + +// ************************************************************************** + +// This function is called by the monitor BFM. It receives data observed by the +// monitor BFM. Data is passed using the fuse_ctrl_core_axi_write_in_monitor_struct. + virtual function void notify_transaction(input fuse_ctrl_core_axi_write_in_monitor_s fuse_ctrl_core_axi_write_in_monitor_struct); + + + trans = new("trans"); + trans.from_monitor_struct(fuse_ctrl_core_axi_write_in_monitor_struct); + trans.start_time = time_stamp; + trans.end_time = $time; + time_stamp = trans.end_time; + + analyze(trans); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_monitor_bfm.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_monitor_bfm.sv new file mode 100644 index 0000000..b7d40a4 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_monitor_bfm.sv @@ -0,0 +1,246 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface performs the fuse_ctrl_core_axi_write_in signal monitoring. +// It is accessed by the uvm fuse_ctrl_core_axi_write_in monitor through a virtual +// interface handle in the fuse_ctrl_core_axi_write_in configuration. It monitors the +// signals passed in through the port connection named bus of +// type fuse_ctrl_core_axi_write_in_if. +// +// Input signals from the fuse_ctrl_core_axi_write_in_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// Interface functions and tasks used by UVM components: +// monitor(inout TRANS_T txn); +// This task receives the transaction, txn, from the +// UVM monitor and then populates variables in txn +// from values observed on bus activity. This task +// blocks until an operation on the fuse_ctrl_core_axi_write_in bus is complete. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_core_axi_write_in_pkg_hdl::*; +`include "src/fuse_ctrl_core_axi_write_in_macros.svh" + + +interface fuse_ctrl_core_axi_write_in_monitor_bfm #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + ( fuse_ctrl_core_axi_write_in_if bus ); + // The pragma below and additional ones in-lined further down are for running this BFM on Veloce + // pragma attribute fuse_ctrl_core_axi_write_in_monitor_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: AW=%x DW=%x IW=%x UW=%x ", AW,DW,IW,UW), + UVM_DEBUG) +end +`endif + + + // Structure used to pass transaction data from monitor BFM to monitor class in agent. +`fuse_ctrl_core_axi_write_in_MONITOR_STRUCT + fuse_ctrl_core_axi_write_in_monitor_s fuse_ctrl_core_axi_write_in_monitor_struct; + + // Structure used to pass configuration data from monitor class to monitor BFM. + `fuse_ctrl_core_axi_write_in_CONFIGURATION_STRUCT + + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + tri clk_i_i; + tri rst_ni_i; + tri [AW-1:0] awaddr_i; + tri [$bits(axi_pkg::axi_burst_e)-1:0] awburst_i; + tri [2:0] awsize_i; + tri [7:0] awlen_i; + tri [UW-1:0] awuser_i; + tri [UW-1:0] awid_i; + tri awlock_i; + tri awvalid_i; + tri [DW-1:0] wdata_i; + tri [DW/8-1:0] wstrb_i; + tri wvalid_i; + tri wlast_i; + tri bready_i; + assign clk_i_i = bus.clk_i; + assign rst_ni_i = bus.rst_ni; + assign awaddr_i = bus.awaddr; + assign awburst_i = bus.awburst; + assign awsize_i = bus.awsize; + assign awlen_i = bus.awlen; + assign awuser_i = bus.awuser; + assign awid_i = bus.awid; + assign awlock_i = bus.awlock; + assign awvalid_i = bus.awvalid; + assign wdata_i = bus.wdata; + assign wstrb_i = bus.wstrb; + assign wvalid_i = bus.wvalid; + assign wlast_i = bus.wlast; + assign bready_i = bus.bready; + + // Proxy handle to UVM monitor + fuse_ctrl_core_axi_write_in_pkg::fuse_ctrl_core_axi_write_in_monitor #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) proxy; + // pragma tbx oneway proxy.notify_transaction + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + task wait_for_reset();// pragma tbx xtf + @(posedge clk_i_i) ; + do_wait_for_reset(); + endtask + + // **************************************************************************** + task do_wait_for_reset(); + // pragma uvmf custom reset_condition begin + wait ( rst_ni_i === 1 ) ; + @(posedge clk_i_i) ; + // pragma uvmf custom reset_condition end + endtask + + //****************************************************************** + + task wait_for_num_clocks(input int unsigned count); // pragma tbx xtf + @(posedge clk_i_i); + + repeat (count-1) @(posedge clk_i_i); + endtask + + //****************************************************************** + event go; + function void start_monitoring();// pragma tbx xtf + -> go; + endfunction + + // **************************************************************************** + initial begin + @go; + forever begin + @(posedge clk_i_i); + do_monitor( fuse_ctrl_core_axi_write_in_monitor_struct ); + + + proxy.notify_transaction( fuse_ctrl_core_axi_write_in_monitor_struct ); + + end + end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the monitor BFM. It is called by the monitor within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the monitor BFM needs to be aware of the new configuration + // variables. + // + function void configure(fuse_ctrl_core_axi_write_in_configuration_s fuse_ctrl_core_axi_write_in_configuration_arg); // pragma tbx xtf + initiator_responder = fuse_ctrl_core_axi_write_in_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + + + // **************************************************************************** + + task do_monitor(output fuse_ctrl_core_axi_write_in_monitor_s fuse_ctrl_core_axi_write_in_monitor_struct); + // + // Available struct members: + // // fuse_ctrl_core_axi_write_in_monitor_struct.core_awaddr + // // fuse_ctrl_core_axi_write_in_monitor_struct.core_awvalid + // // fuse_ctrl_core_axi_write_in_monitor_struct.core_awburst + // // fuse_ctrl_core_axi_write_in_monitor_struct.core_awsize + // // fuse_ctrl_core_axi_write_in_monitor_struct.core_awlen + // // fuse_ctrl_core_axi_write_in_monitor_struct.core_awuser + // // fuse_ctrl_core_axi_write_in_monitor_struct.core_awid + // // fuse_ctrl_core_axi_write_in_monitor_struct.core_awlock + // // fuse_ctrl_core_axi_write_in_monitor_struct.core_wdata + // // fuse_ctrl_core_axi_write_in_monitor_struct.core_wstrb + // // fuse_ctrl_core_axi_write_in_monitor_struct.core_wvalid + // // fuse_ctrl_core_axi_write_in_monitor_struct.core_wlast + // // fuse_ctrl_core_axi_write_in_monitor_struct.core_bready + // // + // Reference code; + // How to wait for signal value + // while (control_signal === 1'b1) @(posedge clk_i_i); + // + // How to assign a struct member, named xyz, from a signal. + // All available input signals listed. + // fuse_ctrl_core_axi_write_in_monitor_struct.xyz = awaddr_i; // [AW-1:0] + // fuse_ctrl_core_axi_write_in_monitor_struct.xyz = awburst_i; // [$bits(axi_pkg::axi_burst_e)-1:0] + // fuse_ctrl_core_axi_write_in_monitor_struct.xyz = awsize_i; // [2:0] + // fuse_ctrl_core_axi_write_in_monitor_struct.xyz = awlen_i; // [7:0] + // fuse_ctrl_core_axi_write_in_monitor_struct.xyz = awuser_i; // [UW-1:0] + // fuse_ctrl_core_axi_write_in_monitor_struct.xyz = awid_i; // [UW-1:0] + // fuse_ctrl_core_axi_write_in_monitor_struct.xyz = awlock_i; // + // fuse_ctrl_core_axi_write_in_monitor_struct.xyz = awvalid_i; // + // fuse_ctrl_core_axi_write_in_monitor_struct.xyz = wdata_i; // [DW-1:0] + // fuse_ctrl_core_axi_write_in_monitor_struct.xyz = wstrb_i; // [DW/8-1:0] + // fuse_ctrl_core_axi_write_in_monitor_struct.xyz = wvalid_i; // + // fuse_ctrl_core_axi_write_in_monitor_struct.xyz = wlast_i; // + // fuse_ctrl_core_axi_write_in_monitor_struct.xyz = bready_i; // + // pragma uvmf custom do_monitor begin + // UVMF_CHANGE_ME : Implement protocol monitoring. The commented reference code + // below are examples of how to capture signal values and assign them to + // structure members. All available input signals are listed. The 'while' + // code example shows how to wait for a synchronous flow control signal. This + // task should return when a complete transfer has been observed. Once this task is + // exited with captured values, it is then called again to wait for and observe + // the next transfer. One clock cycle is consumed between calls to do_monitor. + @(posedge clk_i_i); + @(posedge clk_i_i); + @(posedge clk_i_i); + @(posedge clk_i_i); + // pragma uvmf custom do_monitor end + endtask + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_random_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_random_sequence.svh new file mode 100644 index 0000000..641ace5 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_random_sequence.svh @@ -0,0 +1,87 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This sequences randomizes the fuse_ctrl_core_axi_write_in transaction and sends it +// to the UVM driver. +// +// This sequence constructs and randomizes a fuse_ctrl_core_axi_write_in_transaction. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_write_in_random_sequence #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends fuse_ctrl_core_axi_write_in_sequence_base #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ); + + `uvm_object_param_utils( fuse_ctrl_core_axi_write_in_random_sequence #( + AW, + DW, + IW, + UW + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //***************************************************************** + function new(string name = ""); + super.new(name); + endfunction: new + + // **************************************************************************** + // TASK : body() + // This task is automatically executed when this sequence is started using the + // start(sequencerHandle) task. + // + task body(); + + // Construct the transaction + req=fuse_ctrl_core_axi_write_in_transaction#( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )::type_id::create("req"); + start_item(req); + // Randomize the transaction + if(!req.randomize()) `uvm_fatal("SEQ", "fuse_ctrl_core_axi_write_in_random_sequence::body()-fuse_ctrl_core_axi_write_in_transaction randomization failed") + // Send the transaction to the fuse_ctrl_core_axi_write_in_driver_bfm via the sequencer and fuse_ctrl_core_axi_write_in_driver. + finish_item(req); + `uvm_info("SEQ", {"Response:",req.convert2string()},UVM_MEDIUM) + + endtask + +endclass: fuse_ctrl_core_axi_write_in_random_sequence + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_responder_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_responder_sequence.svh new file mode 100644 index 0000000..0b07917 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_responder_sequence.svh @@ -0,0 +1,83 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class can be used to provide stimulus when an interface +// has been configured to run in a responder mode. It +// will never finish by default, always going back to the driver +// and driver BFM for the next transaction with which to respond. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_write_in_responder_sequence #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends fuse_ctrl_core_axi_write_in_sequence_base #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ); + + `uvm_object_param_utils( fuse_ctrl_core_axi_write_in_responder_sequence #( + AW, + DW, + IW, + UW + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "fuse_ctrl_core_axi_write_in_responder_sequence"); + super.new(name); + endfunction + + task body(); + req=fuse_ctrl_core_axi_write_in_transaction#( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )::type_id::create("req"); + forever begin + start_item(req); + finish_item(req); + // pragma uvmf custom body begin + // UVMF_CHANGE_ME : Do something here with the resulting req item. The + // finish_item() call above will block until the req transaction is ready + // to be handled by the responder sequence. + // If this was an item that required a response, the expectation is + // that the response should be populated within this transaction now. + `uvm_info("SEQ",$sformatf("Processed txn: %s",req.convert2string()),UVM_HIGH) + // pragma uvmf custom body end + end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_sequence_base.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_sequence_base.svh new file mode 100644 index 0000000..461b94a --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_sequence_base.svh @@ -0,0 +1,140 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the class used as the base class for all sequences +// for this interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_write_in_sequence_base #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvmf_sequence_base #( + .REQ(fuse_ctrl_core_axi_write_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .RSP(fuse_ctrl_core_axi_write_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ))); + + `uvm_object_param_utils( fuse_ctrl_core_axi_write_in_sequence_base #( + AW, + DW, + IW, + UW + )) + + // variables + typedef fuse_ctrl_core_axi_write_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) fuse_ctrl_core_axi_write_in_transaction_req_t; + fuse_ctrl_core_axi_write_in_transaction_req_t req; + typedef fuse_ctrl_core_axi_write_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) fuse_ctrl_core_axi_write_in_transaction_rsp_t; + fuse_ctrl_core_axi_write_in_transaction_rsp_t rsp; + + // Event for identifying when a response was received from the sequencer + event new_rsp; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // TASK : get_responses() + // This task recursively gets sequence item responses from the sequencer. + // + virtual task get_responses(); + fork + begin + // Block until new rsp available + get_response(rsp); + // New rsp received. Indicate to sequence using event. + ->new_rsp; + // Display the received response transaction + `uvm_info("SEQ", {"New response transaction:",rsp.convert2string()}, UVM_MEDIUM) + end + join_none + endtask + + // **************************************************************************** + // TASK : pre_body() + // This task is called automatically when start is called with call_pre_post set to 1 (default). + // By calling get_responses() within pre_body() any derived sequences are automatically + // processing response transactions. Only un-comment this call to get_responses() if you + // have configured the interface driver to utilize the response transaction path by setting + // the configuration variable "return_transaction_response" to 1. Otherwise it is possible + // to impact runtime performance and memory utilization. + // + virtual task pre_body(); + // pragma uvmf custom pre_body begin +// get_responses(); + // pragma uvmf custom pre_body end + endtask + + // **************************************************************************** + // TASK : body() + // This task is called automatically when start is called. This sequence sends + // a req sequence item to the sequencer identified as an argument in the call + // to start. + // + virtual task body(); + // pragma uvmf custom body begin + start_item(req); + finish_item(req); + // pragma uvmf custom body end + endtask + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name =""); + super.new( name ); + // pragma uvmf custom new begin + req = fuse_ctrl_core_axi_write_in_transaction_req_t::type_id::create("req"); + rsp = fuse_ctrl_core_axi_write_in_transaction_rsp_t::type_id::create("rsp"); + // pragma uvmf custom new end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_transaction.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_transaction.svh new file mode 100644 index 0000000..f279322 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_transaction.svh @@ -0,0 +1,252 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class defines the variables required for an fuse_ctrl_core_axi_write_in +// transaction. Class variables to be displayed in waveform transaction +// viewing are added to the transaction viewing stream in the add_to_wave +// function. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_write_in_transaction #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvmf_transaction_base; + + `uvm_object_param_utils( fuse_ctrl_core_axi_write_in_transaction #( + AW, + DW, + IW, + UW + )) + + rand logic [AW-1:0] core_awaddr ; + logic core_awvalid ; + logic [$bits(axi_pkg::axi_burst_e)] core_awburst ; + logic [2:0] core_awsize ; + logic [7:0] core_awlen ; + logic [UW-1:0] core_awuser ; + logic [IW-1:0] core_awid ; + logic core_awlock ; + logic [DW-1:0] core_wdata ; + logic [DW/8 - 1:0] core_wstrb ; + logic core_wvalid ; + logic core_wlast ; + logic core_bready ; + + //Constraints for the transaction variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //******************************************************************* + //******************************************************************* + // Macros that define structs and associated functions are + // located in fuse_ctrl_core_axi_write_in_macros.svh + + //******************************************************************* + // Monitor macro used by fuse_ctrl_core_axi_write_in_monitor and fuse_ctrl_core_axi_write_in_monitor_bfm + // This struct is defined in fuse_ctrl_core_axi_write_in_macros.svh + `fuse_ctrl_core_axi_write_in_MONITOR_STRUCT + fuse_ctrl_core_axi_write_in_monitor_s fuse_ctrl_core_axi_write_in_monitor_struct; + //******************************************************************* + // FUNCTION: to_monitor_struct() + // This function packs transaction variables into a fuse_ctrl_core_axi_write_in_monitor_s + // structure. The function returns the handle to the fuse_ctrl_core_axi_write_in_monitor_struct. + // This function is defined in fuse_ctrl_core_axi_write_in_macros.svh + `fuse_ctrl_core_axi_write_in_TO_MONITOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_monitor_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_core_axi_write_in_macros.svh + `fuse_ctrl_core_axi_write_in_FROM_MONITOR_STRUCT_FUNCTION + + //******************************************************************* + // Initiator macro used by fuse_ctrl_core_axi_write_in_driver and fuse_ctrl_core_axi_write_in_driver_bfm + // to communicate initiator driven data to fuse_ctrl_core_axi_write_in_driver_bfm. + // This struct is defined in fuse_ctrl_core_axi_write_in_macros.svh + `fuse_ctrl_core_axi_write_in_INITIATOR_STRUCT + fuse_ctrl_core_axi_write_in_initiator_s fuse_ctrl_core_axi_write_in_initiator_struct; + //******************************************************************* + // FUNCTION: to_initiator_struct() + // This function packs transaction variables into a fuse_ctrl_core_axi_write_in_initiator_s + // structure. The function returns the handle to the fuse_ctrl_core_axi_write_in_initiator_struct. + // This function is defined in fuse_ctrl_core_axi_write_in_macros.svh + `fuse_ctrl_core_axi_write_in_TO_INITIATOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_initiator_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_core_axi_write_in_macros.svh + `fuse_ctrl_core_axi_write_in_FROM_INITIATOR_STRUCT_FUNCTION + + //******************************************************************* + // Responder macro used by fuse_ctrl_core_axi_write_in_driver and fuse_ctrl_core_axi_write_in_driver_bfm + // to communicate Responder driven data to fuse_ctrl_core_axi_write_in_driver_bfm. + // This struct is defined in fuse_ctrl_core_axi_write_in_macros.svh + `fuse_ctrl_core_axi_write_in_RESPONDER_STRUCT + fuse_ctrl_core_axi_write_in_responder_s fuse_ctrl_core_axi_write_in_responder_struct; + //******************************************************************* + // FUNCTION: to_responder_struct() + // This function packs transaction variables into a fuse_ctrl_core_axi_write_in_responder_s + // structure. The function returns the handle to the fuse_ctrl_core_axi_write_in_responder_struct. + // This function is defined in fuse_ctrl_core_axi_write_in_macros.svh + `fuse_ctrl_core_axi_write_in_TO_RESPONDER_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_responder_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_core_axi_write_in_macros.svh + `fuse_ctrl_core_axi_write_in_FROM_RESPONDER_STRUCT_FUNCTION + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + endfunction + + // **************************************************************************** + // FUNCTION: convert2string() + // This function converts all variables in this class to a single string for + // logfile reporting. + // + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + // UVMF_CHANGE_ME : Customize format if desired. + return $sformatf("core_awaddr:0x%x core_awvalid:0x%x core_awburst:0x%x core_awsize:0x%x core_awlen:0x%x core_awuser:0x%x core_awid:0x%x core_awlock:0x%x core_wdata:0x%x core_wstrb:0x%x core_wvalid:0x%x core_wlast:0x%x core_bready:0x%x ",core_awaddr,core_awvalid,core_awburst,core_awsize,core_awlen,core_awuser,core_awid,core_awlock,core_wdata,core_wstrb,core_wvalid,core_wlast,core_bready); + // pragma uvmf custom convert2string end + endfunction + + //******************************************************************* + // FUNCTION: do_print() + // This function is automatically called when the .print() function + // is called on this class. + // + virtual function void do_print(uvm_printer printer); + // pragma uvmf custom do_print begin + // UVMF_CHANGE_ME : Current contents of do_print allows for the use of UVM 1.1d, 1.2 or P1800.2. + // Update based on your own printing preference according to your preferred UVM version + $display(convert2string()); + // pragma uvmf custom do_print end + endfunction + + //******************************************************************* + // FUNCTION: do_compare() + // This function is automatically called when the .compare() function + // is called on this class. + // + virtual function bit do_compare (uvm_object rhs, uvm_comparer comparer); + fuse_ctrl_core_axi_write_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) RHS; + if (!$cast(RHS,rhs)) return 0; + // pragma uvmf custom do_compare begin + // UVMF_CHANGE_ME : Eliminate comparison of variables not to be used for compare + return (super.do_compare(rhs,comparer) + &&(this.core_wdata == RHS.core_wdata) + ); + // pragma uvmf custom do_compare end + endfunction + + //******************************************************************* + // FUNCTION: do_copy() + // This function is automatically called when the .copy() function + // is called on this class. + // + virtual function void do_copy (uvm_object rhs); + fuse_ctrl_core_axi_write_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) RHS; + assert($cast(RHS,rhs)); + // pragma uvmf custom do_copy begin + super.do_copy(rhs); + this.core_awaddr = RHS.core_awaddr; + this.core_awvalid = RHS.core_awvalid; + this.core_awburst = RHS.core_awburst; + this.core_awsize = RHS.core_awsize; + this.core_awlen = RHS.core_awlen; + this.core_awuser = RHS.core_awuser; + this.core_awid = RHS.core_awid; + this.core_awlock = RHS.core_awlock; + this.core_wdata = RHS.core_wdata; + this.core_wstrb = RHS.core_wstrb; + this.core_wvalid = RHS.core_wvalid; + this.core_wlast = RHS.core_wlast; + this.core_bready = RHS.core_bready; + // pragma uvmf custom do_copy end + endfunction + + // **************************************************************************** + // FUNCTION: add_to_wave() + // This function is used to display variables in this class in the waveform + // viewer. The start_time and end_time variables must be set before this + // function is called. If the start_time and end_time variables are not set + // the transaction will be hidden at 0ns on the waveform display. + // + virtual function void add_to_wave(int transaction_viewing_stream_h); + `ifdef QUESTA + if (transaction_view_h == 0) begin + transaction_view_h = $begin_transaction(transaction_viewing_stream_h,"fuse_ctrl_core_axi_write_in_transaction",start_time); + end + super.add_to_wave(transaction_view_h); + // pragma uvmf custom add_to_wave begin + // UVMF_CHANGE_ME : Color can be applied to transaction entries based on content, example below + // case() + // 1 : $add_color(transaction_view_h,"red"); + // default : $add_color(transaction_view_h,"grey"); + // endcase + // UVMF_CHANGE_ME : Eliminate transaction variables not wanted in transaction viewing in the waveform viewer + $add_attribute(transaction_view_h,core_awaddr,"core_awaddr"); + $add_attribute(transaction_view_h,core_awvalid,"core_awvalid"); + $add_attribute(transaction_view_h,core_awburst,"core_awburst"); + $add_attribute(transaction_view_h,core_awsize,"core_awsize"); + $add_attribute(transaction_view_h,core_awlen,"core_awlen"); + $add_attribute(transaction_view_h,core_awuser,"core_awuser"); + $add_attribute(transaction_view_h,core_awid,"core_awid"); + $add_attribute(transaction_view_h,core_awlock,"core_awlock"); + $add_attribute(transaction_view_h,core_wdata,"core_wdata"); + $add_attribute(transaction_view_h,core_wstrb,"core_wstrb"); + $add_attribute(transaction_view_h,core_wvalid,"core_wvalid"); + $add_attribute(transaction_view_h,core_wlast,"core_wlast"); + $add_attribute(transaction_view_h,core_bready,"core_bready"); + // pragma uvmf custom add_to_wave end + $end_transaction(transaction_view_h,end_time); + $free_transaction(transaction_view_h); + `endif // QUESTA + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_transaction_coverage.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_transaction_coverage.svh new file mode 100644 index 0000000..d000917 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_transaction_coverage.svh @@ -0,0 +1,111 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class records fuse_ctrl_core_axi_write_in transaction information using +// a covergroup named fuse_ctrl_core_axi_write_in_transaction_cg. An instance of this +// coverage component is instantiated in the uvmf_parameterized_agent +// if the has_coverage flag is set. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_write_in_transaction_coverage #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvm_subscriber #(.T(fuse_ctrl_core_axi_write_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ))); + + `uvm_component_param_utils( fuse_ctrl_core_axi_write_in_transaction_coverage #( + AW, + DW, + IW, + UW + )) + + T coverage_trans; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + covergroup fuse_ctrl_core_axi_write_in_transaction_cg; + // pragma uvmf custom covergroup begin + // UVMF_CHANGE_ME : Add coverage bins, crosses, exclusions, etc. according to coverage needs. + option.auto_bin_max=1024; + option.per_instance=1; + core_awaddr: coverpoint coverage_trans.core_awaddr; + core_awvalid: coverpoint coverage_trans.core_awvalid; + core_awburst: coverpoint coverage_trans.core_awburst; + core_awsize: coverpoint coverage_trans.core_awsize; + core_awlen: coverpoint coverage_trans.core_awlen; + core_awuser: coverpoint coverage_trans.core_awuser; + core_awid: coverpoint coverage_trans.core_awid; + core_awlock: coverpoint coverage_trans.core_awlock; + core_wdata: coverpoint coverage_trans.core_wdata; + core_wstrb: coverpoint coverage_trans.core_wstrb; + core_wvalid: coverpoint coverage_trans.core_wvalid; + core_wlast: coverpoint coverage_trans.core_wlast; + core_bready: coverpoint coverage_trans.core_bready; + // pragma uvmf custom covergroup end + endgroup + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new(string name="", uvm_component parent=null); + super.new(name,parent); + fuse_ctrl_core_axi_write_in_transaction_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that transaction variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + endfunction + + // **************************************************************************** + // FUNCTION : build_phase() + // This function is the standard UVM build_phase. + // + function void build_phase(uvm_phase phase); + fuse_ctrl_core_axi_write_in_transaction_cg.set_inst_name($sformatf("fuse_ctrl_core_axi_write_in_transaction_cg_%s",get_full_name())); + endfunction + + // **************************************************************************** + // FUNCTION: write (T t) + // This function is automatically executed when a transaction arrives on the + // analysis_export. It copies values from the variables in the transaction + // to local variables used to collect functional coverage. + // + virtual function void write (T t); + `uvm_info("COV","Received transaction",UVM_HIGH); + coverage_trans = t; + fuse_ctrl_core_axi_write_in_transaction_cg.sample(); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_typedefs.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_typedefs.svh new file mode 100644 index 0000000..f2a7bdb --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_typedefs.svh @@ -0,0 +1,34 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the host server when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_typedefs_hdl.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_typedefs_hdl.svh new file mode 100644 index 0000000..0d58518 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_typedefs_hdl.svh @@ -0,0 +1,35 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the emulator when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/yaml/fuse_ctrl_core_axi_write_in_interface.yaml b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/yaml/fuse_ctrl_core_axi_write_in_interface.yaml new file mode 100644 index 0000000..9882e7c --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/yaml/fuse_ctrl_core_axi_write_in_interface.yaml @@ -0,0 +1,161 @@ +uvmf: + interfaces: + fuse_ctrl_core_axi_write_in: + clock: clk_i + config_constraints: [] + config_vars: [] + existing_library_component: 'True' + gen_inbound_streaming_driver: 'False' + hdl_pkg_parameters: [] + hdl_typedefs: [] + hvl_pkg_parameters: [] + hvl_typedefs: [] + parameters: + - name: AW + type: int + value: '32' + - name: DW + type: int + value: '32' + - name: IW + type: int + value: '3' + - name: UW + type: int + value: '32' + ports: + - dir: output + name: awaddr + reset_value: '''bz' + width: '[''AW'']' + - dir: output + name: awburst + reset_value: '''bz' + width: '[''$bits(axi_pkg::axi_burst_e)'']' + - dir: output + name: awsize + reset_value: '''bz' + width: '3' + - dir: output + name: awlen + reset_value: '''bz' + width: '8' + - dir: output + name: awuser + reset_value: '''bz' + width: '[''UW'']' + - dir: output + name: awid + reset_value: '''bz' + width: '[''UW'']' + - dir: output + name: awlock + reset_value: '''bz' + width: '1' + - dir: output + name: awvalid + reset_value: '''bz' + width: '1' + - dir: output + name: wdata + reset_value: '''bz' + width: '[''DW'']' + - dir: output + name: wstrb + reset_value: '''bz' + width: '[''DW/8'']' + - dir: output + name: wvalid + reset_value: '''bz' + width: '1' + - dir: output + name: wlast + reset_value: '''bz' + width: '1' + - dir: output + name: bready + reset_value: '''bz' + width: '1' + reset: rst_ni + reset_assertion_level: 'False' + transaction_constraints: [] + transaction_vars: + - comment: '' + iscompare: 'False' + isrand: 'True' + name: core_awaddr + type: logic [AW-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: core_awvalid + type: logic + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: core_awburst + type: logic [$bits(axi_pkg::axi_burst_e)] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: core_awsize + type: logic [2:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: core_awlen + type: logic [7:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: core_awuser + type: logic [UW-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: core_awid + type: logic [IW-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: core_awlock + type: logic + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'False' + name: core_wdata + type: logic [DW-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: core_wstrb + type: logic [DW/8 - 1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: core_wvalid + type: logic + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: core_wlast + type: logic + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: core_bready + type: logic + unpacked_dimension: '' + use_dpi_link: 'False' diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/.project b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/.project new file mode 100644 index 0000000..673a410 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/.project @@ -0,0 +1,30 @@ + + + fuse_ctrl_core_axi_write_out_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/.svproject b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/.svproject new file mode 100644 index 0000000..e0ccd60 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/Makefile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/Makefile new file mode 100644 index 0000000..b885f66 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/Makefile @@ -0,0 +1,66 @@ +# fuse_ctrl_core_axi_write_out interface packages source +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +fuse_ctrl_core_axi_write_out_PKG = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_write_out_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_filelist_hvl.f + +fuse_ctrl_core_axi_write_out_PKG_HDL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_write_out_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_filelist_hdl.f + +fuse_ctrl_core_axi_write_out_PKG_XRTL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_write_out_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_filelist_xrtl.f + +COMP_fuse_ctrl_core_axi_write_out_PKG_TGT_0 = q_comp_fuse_ctrl_core_axi_write_out_pkg +COMP_fuse_ctrl_core_axi_write_out_PKG_TGT_1 = v_comp_fuse_ctrl_core_axi_write_out_pkg +COMP_fuse_ctrl_core_axi_write_out_PKG_TGT = $(COMP_fuse_ctrl_core_axi_write_out_PKG_TGT_$(USE_VELOCE)) + +comp_fuse_ctrl_core_axi_write_out_pkg: $(COMP_fuse_ctrl_core_axi_write_out_PKG_TGT) + +q_comp_fuse_ctrl_core_axi_write_out_pkg: + $(HDL_COMP_CMD) $(fuse_ctrl_core_axi_write_out_PKG_HDL) + $(HVL_COMP_CMD) $(fuse_ctrl_core_axi_write_out_PKG) + $(HDL_COMP_CMD) $(fuse_ctrl_core_axi_write_out_PKG_XRTL) + +v_comp_fuse_ctrl_core_axi_write_out_pkg: + $(HVL_COMP_CMD) $(fuse_ctrl_core_axi_write_out_PKG_HDL) + $(HVL_COMP_CMD) $(fuse_ctrl_core_axi_write_out_PKG) + $(VELANALYZE_CMD) $(fuse_ctrl_core_axi_write_out_PKG_HDL) + $(VELANALYZE_HVL_CMD) $(fuse_ctrl_core_axi_write_out_PKG) + $(HDL_COMP_CMD) $(fuse_ctrl_core_axi_write_out_PKG_XRTL) + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export fuse_ctrl_core_axi_write_out_IF_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_write_out_pkg/dpi + +C_FILE_COMPILE_LIST_fuse_ctrl_core_axi_write_out_pkg = \ + +O_FILE_COMPILE_LIST_fuse_ctrl_core_axi_write_out_pkg = $(notdir $(C_FILE_COMPILE_LIST_fuse_ctrl_core_axi_write_out_pkg:.c=.o)) + +GCC_COMP_ARGS_fuse_ctrl_core_axi_write_out_pkg += -I$(fuse_ctrl_core_axi_write_out_IF_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_fuse_ctrl_core_axi_write_out_pkg += $(fuse_ctrl_core_axi_write_out_IF_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_fuse_ctrl_core_axi_write_out_pkg += \ + \ + -o .so + +comp_fuse_ctrl_core_axi_write_out_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Interface C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_fuse_ctrl_core_axi_write_out_pkg) $(C_FILE_COMPILE_LIST_fuse_ctrl_core_axi_write_out_pkg) + @echo "--------------------------------" + @echo "Linking Interface C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_fuse_ctrl_core_axi_write_out_pkg) $(O_FILE_COMPILE_LIST_fuse_ctrl_core_axi_write_out_pkg) + @echo "--------------------------------" + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/compile.do b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/compile.do new file mode 100644 index 0000000..dd7c8df --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/compile.do @@ -0,0 +1,14 @@ +# Tcl do file for compile of fuse_ctrl_core_axi_write_out interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_write_out_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_filelist_hdl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_write_out_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_filelist_hvl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_write_out_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_filelist_xrtl.f \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out.compile new file mode 100644 index 0000000..fc356ad --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out.compile @@ -0,0 +1,3 @@ +needs: + - fuse_ctrl_core_axi_write_out_hvl.compile + - fuse_ctrl_core_axi_write_out_hdl.compile diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_bfm.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_bfm.vinfo new file mode 100644 index 0000000..4acbc3d --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_bfm.vinfo @@ -0,0 +1,6 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use fuse_ctrl_core_axi_write_out_pkg_hdl.vinfo ++incdir+@vinfodir +src/fuse_ctrl_core_axi_write_out_if.sv +src/fuse_ctrl_core_axi_write_out_driver_bfm.sv +src/fuse_ctrl_core_axi_write_out_monitor_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_common.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_common.compile new file mode 100644 index 0000000..ab99fa6 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_common.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +incdir: + - . + - ${uvm_path}/src +src: + - fuse_ctrl_core_axi_write_out_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_filelist_hdl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_filelist_hdl.f new file mode 100644 index 0000000..354fe24 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_filelist_hdl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_filelist_hvl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_filelist_hvl.f new file mode 100644 index 0000000..d14e3d6 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_filelist_hvl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_pkg.sv \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_filelist_xrtl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_filelist_xrtl.f new file mode 100644 index 0000000..9aecc88 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_filelist_xrtl.f @@ -0,0 +1,3 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_if.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_monitor_bfm.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_driver_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_hdl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_hdl.compile new file mode 100644 index 0000000..d220bb8 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_hdl.compile @@ -0,0 +1,9 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ./fuse_ctrl_core_axi_write_out_common.compile +incdir: + - . +src: + - src/fuse_ctrl_core_axi_write_out_if.sv + - src/fuse_ctrl_core_axi_write_out_monitor_bfm.sv + - src/fuse_ctrl_core_axi_write_out_driver_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_hvl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_hvl.compile new file mode 100644 index 0000000..2d0aa98 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_hvl.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ./fuse_ctrl_core_axi_write_out_common.compile +incdir: + - . +src: + - fuse_ctrl_core_axi_write_out_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_pkg.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_pkg.sv new file mode 100644 index 0000000..4e525f1 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_pkg.sv @@ -0,0 +1,91 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - + +// - +// - +// - + +// - +// - +// - + +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_core_axi_write_out_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg_hdl::*; + import uvmf_base_pkg::*; + import fuse_ctrl_core_axi_write_out_pkg_hdl::*; + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + `include "src/fuse_ctrl_core_axi_write_out_macros.svh" + + export fuse_ctrl_core_axi_write_out_pkg_hdl::*; + + + + // Parameters defined as HVL parameters + + `include "src/fuse_ctrl_core_axi_write_out_typedefs.svh" + `include "src/fuse_ctrl_core_axi_write_out_transaction.svh" + + `include "src/fuse_ctrl_core_axi_write_out_configuration.svh" + `include "src/fuse_ctrl_core_axi_write_out_driver.svh" + `include "src/fuse_ctrl_core_axi_write_out_monitor.svh" + + `include "src/fuse_ctrl_core_axi_write_out_transaction_coverage.svh" + `include "src/fuse_ctrl_core_axi_write_out_sequence_base.svh" + `include "src/fuse_ctrl_core_axi_write_out_random_sequence.svh" + + `include "src/fuse_ctrl_core_axi_write_out_responder_sequence.svh" + `include "src/fuse_ctrl_core_axi_write_out2reg_adapter.svh" + + `include "src/fuse_ctrl_core_axi_write_out_agent.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new interface sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the interface package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_pkg.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_pkg.vinfo new file mode 100644 index 0000000..6c1d385 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_pkg.vinfo @@ -0,0 +1,4 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use fuse_ctrl_core_axi_write_out_pkg_hdl.vinfo ++incdir+@vinfodir +fuse_ctrl_core_axi_write_out_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_pkg_hdl.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_pkg_hdl.sv new file mode 100644 index 0000000..9bdd4e6 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_pkg_hdl.sv @@ -0,0 +1,52 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that needs to be compiled and synthesized +// for running on Veloce. +// +// CONTAINS: +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_core_axi_write_out_pkg_hdl; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HDL parameters + + `include "src/fuse_ctrl_core_axi_write_out_typedefs_hdl.svh" + `include "src/fuse_ctrl_core_axi_write_out_macros.svh" + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_pkg_hdl.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_pkg_hdl.vinfo new file mode 100644 index 0000000..68e75c6 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_pkg_hdl.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +fuse_ctrl_core_axi_write_out_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_pkg_sve.F b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_pkg_sve.F new file mode 100644 index 0000000..dd141cc --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_pkg_sve.F @@ -0,0 +1,10 @@ +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + ++incdir+. +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_filelist_hdl.f +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_filelist_hvl.f diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out2reg_adapter.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out2reg_adapter.svh new file mode 100644 index 0000000..257cf76 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out2reg_adapter.svh @@ -0,0 +1,137 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the UVM register adapter for the fuse_ctrl_core_axi_write_out interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_write_out2reg_adapter #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvm_reg_adapter; + + `uvm_object_param_utils( fuse_ctrl_core_axi_write_out2reg_adapter #( + AW, + DW, + IW, + UW + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //-------------------------------------------------------------------- + // new + //-------------------------------------------------------------------- + function new (string name = "fuse_ctrl_core_axi_write_out2reg_adapter" ); + super.new(name); + // pragma uvmf custom new begin + // UVMF_CHANGE_ME : Configure the adapter regarding byte enables and provides response. + + // Does the protocol the Agent is modeling support byte enables? + // 0 = NO + // 1 = YES + supports_byte_enable = 0; + + // Does the Agent's Driver provide separate response sequence items? + // i.e. Does the driver call seq_item_port.put() + // and do the sequences call get_response()? + // 0 = NO + // 1 = YES + provides_responses = 0; + // pragma uvmf custom new end + + endfunction: new + + //-------------------------------------------------------------------- + // reg2bus + //-------------------------------------------------------------------- + virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw); + + fuse_ctrl_core_axi_write_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) trans_h = fuse_ctrl_core_axi_write_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )::type_id::create("trans_h"); + + // pragma uvmf custom reg2bus begin + // UVMF_CHANGE_ME : Fill in the reg2bus adapter mapping registe fields to protocol fields. + + //Adapt the following for your sequence item type + // trans_h.op = (rw.kind == UVM_READ) ? WB_READ : WB_WRITE; + //Copy over address + // trans_h.addr = rw.addr; + //Copy over write data + // trans_h.data = rw.data; + + // pragma uvmf custom reg2bus end + + // Return the adapted transaction + return trans_h; + + endfunction: reg2bus + + //-------------------------------------------------------------------- + // bus2reg + //-------------------------------------------------------------------- + virtual function void bus2reg(uvm_sequence_item bus_item, + ref uvm_reg_bus_op rw); + fuse_ctrl_core_axi_write_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) trans_h; + if (!$cast(trans_h, bus_item)) begin + `uvm_fatal("ADAPT","Provided bus_item is not of the correct type") + return; + end + // pragma uvmf custom bus2reg begin + // UVMF_CHANGE_ME : Fill in the bus2reg adapter mapping protocol fields to register fields. + //Adapt the following for your sequence item type + //Copy over instruction type + // rw.kind = (trans_h.op == WB_WRITE) ? UVM_WRITE : UVM_READ; + //Copy over address + // rw.addr = trans_h.addr; + //Copy over read data + // rw.data = trans_h.data; + //Check for errors on the bus and return UVM_NOT_OK if there is an error + // rw.status = UVM_IS_OK; + // pragma uvmf custom bus2reg end + + endfunction: bus2reg + +endclass : fuse_ctrl_core_axi_write_out2reg_adapter + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_agent.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_agent.svh new file mode 100644 index 0000000..a1e9bf3 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_agent.svh @@ -0,0 +1,102 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: Protocol specific agent class definition +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_write_out_agent #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvmf_parameterized_agent #( + .CONFIG_T(fuse_ctrl_core_axi_write_out_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .DRIVER_T(fuse_ctrl_core_axi_write_out_driver #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .MONITOR_T(fuse_ctrl_core_axi_write_out_monitor #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .COVERAGE_T(fuse_ctrl_core_axi_write_out_transaction_coverage #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .TRANS_T(fuse_ctrl_core_axi_write_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )) + ); + + `uvm_component_param_utils( fuse_ctrl_core_axi_write_out_agent #( + AW, + DW, + IW, + UW + )) + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** + // FUNCTION: build_phase + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + if (configuration.active_passive == ACTIVE) begin + // Place sequencer handle into configuration object + // so that it may be retrieved from configuration + // rather than using uvm_config_db + configuration.sequencer = this.sequencer; + end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_configuration.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_configuration.svh new file mode 100644 index 0000000..cd9e187 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_configuration.svh @@ -0,0 +1,233 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class contains all variables and functions used +// to configure the fuse_ctrl_core_axi_write_out agent and its bfm's. It gets the +// bfm's from the uvm_config_db for use by the agent. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_write_out_configuration #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvmf_parameterized_agent_configuration_base #( + .DRIVER_BFM_BIND_T(virtual fuse_ctrl_core_axi_write_out_driver_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .MONITOR_BFM_BIND_T( virtual fuse_ctrl_core_axi_write_out_monitor_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ))); + + `uvm_object_param_utils( fuse_ctrl_core_axi_write_out_configuration #( + AW, + DW, + IW, + UW + )) + + + // Sequencer handle populated by agent + uvm_sequencer #(fuse_ctrl_core_axi_write_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) ) sequencer; + + //Constraints for the configuration variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + covergroup fuse_ctrl_core_axi_write_out_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + // pragma uvmf custom covergroup end + endgroup + + //******************************************************************* + //******************************************************************* + // Structure used to pass configuration variables to monitor and driver BFM's. + // Use to_struct function to pack variables into structure. + // Use from_struct function to unpack variables from structure. + // This structure is defined in fuse_ctrl_core_axi_write_out_macros.svh + `fuse_ctrl_core_axi_write_out_CONFIGURATION_STRUCT + fuse_ctrl_core_axi_write_out_configuration_s fuse_ctrl_core_axi_write_out_configuration_struct; + //******************************************************************* + // FUNCTION: to_struct() + // This function packs variables into a fuse_ctrl_core_axi_write_out_configuration_s + // structure. The function returns the handle to the fuse_ctrl_core_axi_write_out_configuration_struct. + // This function is defined in fuse_ctrl_core_axi_write_out_macros.svh + `fuse_ctrl_core_axi_write_out_CONFIGURATION_TO_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_struct() + // This function unpacks the struct provided as an argument into + // variables of this class. + // This function is defined in fuse_ctrl_core_axi_write_out_macros.svh + `fuse_ctrl_core_axi_write_out_CONFIGURATION_FROM_STRUCT_FUNCTION + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + // Construct the covergroup for this configuration class + fuse_ctrl_core_axi_write_out_configuration_cg = new; + endfunction + + // **************************************************************************** + // FUNCTION: post_randomize() + // This function is automatically called after the randomize() function + // is executed. + // + function void post_randomize(); + super.post_randomize(); + fuse_ctrl_core_axi_write_out_configuration_cg.sample(); + endfunction + + // **************************************************************************** + // FUNCTION: initialize + // This function causes the configuration to retrieve + // its virtual interface handle from the uvm_config_db. + // This function also makes itself available to its + // agent through the uvm_config_db. + // + // ARGUMENTS: + // uvmf_active_passive_t activity: + // This argument identifies the simulation level + // as either BLOCK, CHIP, SIMULATION, etc. + // + // AGENT_PATH: + // This argument identifies the path to this + // configurations agent. This configuration + // makes itself available to the agent specified + // by agent_path by placing itself into the + // uvm_config_db. + // + // INTERFACE_NAME: + // This argument identifies the string name of + // this configurations BFM's. This string + // name is used to retrieve the driver and + // monitor BFM from the uvm_config_db. + // + virtual function void initialize(uvmf_active_passive_t activity, + string agent_path, + string interface_name); + + super.initialize( activity, agent_path, interface_name); + // The covergroup is given the same name as the interface + fuse_ctrl_core_axi_write_out_configuration_cg.set_inst_name(interface_name); + + // This configuration places itself into the uvm_config_db for the agent, identified by the agent_path variable, to retrieve. + uvm_config_db #( fuse_ctrl_core_axi_write_out_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + )::set( null ,agent_path,UVMF_AGENT_CONFIG, this ); + + // This configuration also places itself in the config db using the same identifier used by the interface. This allows users to access + // configuration variables and the interface through the bfm api class rather than directly accessing the BFM. This is useful for + // accessingthe BFM when using Veloce + uvm_config_db #( fuse_ctrl_core_axi_write_out_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + )::set( null ,UVMF_CONFIGURATIONS, interface_name, this ); + + fuse_ctrl_core_axi_write_out_configuration_cg.set_inst_name($sformatf("fuse_ctrl_core_axi_write_out_configuration_cg_%s",get_full_name())); + +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. + `uvm_info("CFG", + $psprintf("The agent at '%s' is using interface named %s has the following parameters: AW=%x DW=%x IW=%x UW=%x ", agent_path, interface_name, AW ,DW ,IW ,UW ), + UVM_DEBUG) + + // pragma uvmf custom initialize begin + // This controls whether or not the agent returns a transaction handle in the driver when calling + // item_done() back into the sequencer or not. If set to 1, a transaction is sent back which means + // the sequence on the other end must use the get_response() part of the driver/sequence API. If + // this doesn't occur, there will eventually be response_queue overflow errors during the test. + return_transaction_response = 1'b0; + + // pragma uvmf custom initialize end + + endfunction + + // **************************************************************************** + // TASK: wait_for_reset + // *[Required]* Blocks until reset is released. The wait_for_reset operation is performed + // by a task in the monitor bfm. + virtual task wait_for_reset(); + monitor_bfm.wait_for_reset(); + endtask + + // **************************************************************************** + // TASK: wait_for_num_clocks + // *[Required]* Blocks until specified number of clocks have elapsed. The wait_for_num_clocks + // operation is performed by a task in the monitor bfm. + virtual task wait_for_num_clocks(int clocks); + monitor_bfm.wait_for_num_clocks(clocks); + endtask + + // **************************************************************************** + // FUNCTION : convert2string() + // This function is used to convert variables in this class into a string for log messaging. + // + virtual function string convert2string (); + // pragma uvmf custom convert2string begin + return $sformatf(""); + // pragma uvmf custom convert2string end + endfunction + + // **************************************************************************** + // FUNCTION: get_sequencer + function uvm_sequencer #(fuse_ctrl_core_axi_write_out_transaction#( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )) get_sequencer(); + return sequencer; + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_driver.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_driver.svh new file mode 100644 index 0000000..e5c47f6 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_driver.svh @@ -0,0 +1,135 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class passes transactions between the sequencer +// and the BFM driver interface. It accesses the driver BFM +// through the bfm handle. This driver +// passes transactions to the driver BFM through the access +// task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_write_out_driver #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvmf_driver_base #( + .CONFIG_T(fuse_ctrl_core_axi_write_out_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) ), + .BFM_BIND_T(virtual fuse_ctrl_core_axi_write_out_driver_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) ), + .REQ(fuse_ctrl_core_axi_write_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) ), + .RSP(fuse_ctrl_core_axi_write_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) )); + + `uvm_component_param_utils( fuse_ctrl_core_axi_write_out_driver #( + AW, + DW, + IW, + UW + )) +//******************************************************************* +// Macros that define structs located in fuse_ctrl_core_axi_write_out_macros.svh +//******************************************************************* +// Initiator macro used by fuse_ctrl_core_axi_write_out_driver and fuse_ctrl_core_axi_write_out_driver_bfm +// to communicate initiator driven data to fuse_ctrl_core_axi_write_out_driver_bfm. +`fuse_ctrl_core_axi_write_out_INITIATOR_STRUCT + fuse_ctrl_core_axi_write_out_initiator_s fuse_ctrl_core_axi_write_out_initiator_struct; +//******************************************************************* +// Responder macro used by fuse_ctrl_core_axi_write_out_driver and fuse_ctrl_core_axi_write_out_driver_bfm +// to communicate Responder driven data to fuse_ctrl_core_axi_write_out_driver_bfm. +`fuse_ctrl_core_axi_write_out_RESPONDER_STRUCT + fuse_ctrl_core_axi_write_out_responder_s fuse_ctrl_core_axi_write_out_responder_struct; + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent=null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the driver BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// driver BFM. This allows the driver BFM to call tasks and function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// **************************************************************************** +// This task is called by the run_phase in uvmf_driver_base. + virtual task access( inout REQ txn ); +// pragma uvmf custom access begin + if (configuration.initiator_responder==RESPONDER) begin + // Complete current transfer and wait for next transfer + bfm.respond_and_wait_for_next_transfer( + fuse_ctrl_core_axi_write_out_initiator_struct, + txn.to_responder_struct() + ); + // Unpack information about initiated transfer received by this responder + txn.from_initiator_struct(fuse_ctrl_core_axi_write_out_initiator_struct); + end else begin + // Initiate a transfer and get response + bfm.initiate_and_get_response( + txn.to_initiator_struct(), + fuse_ctrl_core_axi_write_out_responder_struct + ); + // Unpack transfer response information received by this initiator + txn.from_responder_struct(fuse_ctrl_core_axi_write_out_responder_struct); + end +// pragma uvmf custom access end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_driver_bfm.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_driver_bfm.sv new file mode 100644 index 0000000..c6335cf --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_driver_bfm.sv @@ -0,0 +1,339 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This interface performs the fuse_ctrl_core_axi_write_out signal driving. It is +// accessed by the uvm fuse_ctrl_core_axi_write_out driver through a virtual interface +// handle in the fuse_ctrl_core_axi_write_out configuration. It drives the singals passed +// in through the port connection named bus of type fuse_ctrl_core_axi_write_out_if. +// +// Input signals from the fuse_ctrl_core_axi_write_out_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// This bfm drives signals with a _o suffix. These signals +// are driven onto signals within fuse_ctrl_core_axi_write_out_if based on INITIATOR/RESPONDER and/or +// ARBITRATION/GRANT status. +// +// The output signal connections are as follows: +// signal_o -> bus.signal +// +// +// Interface functions and tasks used by UVM components: +// +// configure: +// This function gets configuration attributes from the +// UVM driver to set any required BFM configuration +// variables such as 'initiator_responder'. +// +// initiate_and_get_response: +// This task is used to perform signaling activity for initiating +// a protocol transfer. The task initiates the transfer, using +// input data from the initiator struct. Then the task captures +// response data, placing the data into the response struct. +// The response struct is returned to the driver class. +// +// respond_and_wait_for_next_transfer: +// This task is used to complete a current transfer as a responder +// and then wait for the initiator to start the next transfer. +// The task uses data in the responder struct to drive protocol +// signals to complete the transfer. The task then waits for +// the next transfer. Once the next transfer begins, data from +// the initiator is placed into the initiator struct and sent +// to the responder sequence for processing to determine +// what data to respond with. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_core_axi_write_out_pkg_hdl::*; +`include "src/fuse_ctrl_core_axi_write_out_macros.svh" + +interface fuse_ctrl_core_axi_write_out_driver_bfm #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + (fuse_ctrl_core_axi_write_out_if bus); + // The following pragma and additional ones in-lined further below are for running this BFM on Veloce + // pragma attribute fuse_ctrl_core_axi_write_out_driver_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: AW=%x DW=%x IW=%x UW=%x ", AW,DW,IW,UW), + UVM_DEBUG) +end +`endif + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + tri clk_i_i; + tri rst_ni_i; + + // Signal list (all signals are capable of being inputs and outputs for the sake + // of supporting both INITIATOR and RESPONDER mode operation. Expectation is that + // directionality in the config file was from the point-of-view of the INITIATOR + + // INITIATOR mode input signals + tri awready_i; + reg awready_o = 'bz; + tri wready_i; + reg wready_o = 'bz; + tri [$bits(axi_pkg::axi_burst_e)-1:0] bresp_i; + reg [$bits(axi_pkg::axi_burst_e)-1:0] bresp_o = 'bz; + tri bid_i; + reg bid_o = 'bz; + tri bvalid_i; + reg bvalid_o = 'bz; + + // INITIATOR mode output signals + + // Bi-directional signals + + + assign clk_i_i = bus.clk_i; + assign rst_ni_i = bus.rst_ni; + + // These are signals marked as 'input' by the config file, but the signals will be + // driven by this BFM if put into RESPONDER mode (flipping all signal directions around) + assign awready_i = bus.awready; + assign bus.awready = (initiator_responder == RESPONDER) ? awready_o : 'bz; + assign wready_i = bus.wready; + assign bus.wready = (initiator_responder == RESPONDER) ? wready_o : 'bz; + assign bresp_i = bus.bresp; + assign bus.bresp = (initiator_responder == RESPONDER) ? bresp_o : 'bz; + assign bid_i = bus.bid; + assign bus.bid = (initiator_responder == RESPONDER) ? bid_o : 'bz; + assign bvalid_i = bus.bvalid; + assign bus.bvalid = (initiator_responder == RESPONDER) ? bvalid_o : 'bz; + + + // These are signals marked as 'output' by the config file, but the outputs will + // not be driven by this BFM unless placed in INITIATOR mode. + + // Proxy handle to UVM driver + fuse_ctrl_core_axi_write_out_pkg::fuse_ctrl_core_axi_write_out_driver #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) proxy; + // pragma tbx oneway proxy.my_function_name_in_uvm_driver + + // **************************************************************************** + // **************************************************************************** + // Macros that define structs located in fuse_ctrl_core_axi_write_out_macros.svh + // **************************************************************************** + // Struct for passing configuration data from fuse_ctrl_core_axi_write_out_driver to this BFM + // **************************************************************************** + `fuse_ctrl_core_axi_write_out_CONFIGURATION_STRUCT + // **************************************************************************** + // Structs for INITIATOR and RESPONDER data flow + //******************************************************************* + // Initiator macro used by fuse_ctrl_core_axi_write_out_driver and fuse_ctrl_core_axi_write_out_driver_bfm + // to communicate initiator driven data to fuse_ctrl_core_axi_write_out_driver_bfm. + `fuse_ctrl_core_axi_write_out_INITIATOR_STRUCT + fuse_ctrl_core_axi_write_out_initiator_s initiator_struct; + // Responder macro used by fuse_ctrl_core_axi_write_out_driver and fuse_ctrl_core_axi_write_out_driver_bfm + // to communicate Responder driven data to fuse_ctrl_core_axi_write_out_driver_bfm. + `fuse_ctrl_core_axi_write_out_RESPONDER_STRUCT + fuse_ctrl_core_axi_write_out_responder_s responder_struct; + + // **************************************************************************** +// pragma uvmf custom reset_condition_and_response begin + // Always block used to return signals to reset value upon assertion of reset + always @( negedge rst_ni_i ) + begin + // RESPONDER mode output signals + awready_o <= 'bz; + wready_o <= 'bz; + bresp_o <= 'bz; + bid_o <= 'bz; + bvalid_o <= 'bz; + // INITIATOR mode output signals + // Bi-directional signals + + end +// pragma uvmf custom reset_condition_and_response end + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the driver BFM. It is called by the driver within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the driver BFM needs to be aware of the new configuration + // variables. + // + + function void configure(fuse_ctrl_core_axi_write_out_configuration_s fuse_ctrl_core_axi_write_out_configuration_arg); // pragma tbx xtf + initiator_responder = fuse_ctrl_core_axi_write_out_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + +// pragma uvmf custom initiate_and_get_response begin +// **************************************************************************** +// UVMF_CHANGE_ME +// This task is used by an initator. The task first initiates a transfer then +// waits for the responder to complete the transfer. + task initiate_and_get_response( + // This argument passes transaction variables used by an initiator + // to perform the initial part of a protocol transfer. The values + // come from a sequence item created in a sequence. + input fuse_ctrl_core_axi_write_out_initiator_s fuse_ctrl_core_axi_write_out_initiator_struct, + // This argument is used to send data received from the responder + // back to the sequence item. The sequence item is returned to the sequence. + output fuse_ctrl_core_axi_write_out_responder_s fuse_ctrl_core_axi_write_out_responder_struct + );// pragma tbx xtf + // + // Members within the fuse_ctrl_core_axi_write_out_initiator_struct: + // logic core_awready ; + // logic core_wready ; + // axi_pkg::axi_burst_e core_bresp ; + // logic core_bid ; + // logic core_bvalid ; + // Members within the fuse_ctrl_core_axi_write_out_responder_struct: + // logic core_awready ; + // logic core_wready ; + // axi_pkg::axi_burst_e core_bresp ; + // logic core_bid ; + // logic core_bvalid ; + initiator_struct = fuse_ctrl_core_axi_write_out_initiator_struct; + // + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clk_i_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available initiator input and inout signals listed. + // Initiator input signals + // fuse_ctrl_core_axi_write_out_responder_struct.xyz = awready_i; // + // fuse_ctrl_core_axi_write_out_responder_struct.xyz = wready_i; // + // fuse_ctrl_core_axi_write_out_responder_struct.xyz = bresp_i; // [$bits(axi_pkg::axi_burst_e)-1:0] + // fuse_ctrl_core_axi_write_out_responder_struct.xyz = bid_i; // + // fuse_ctrl_core_axi_write_out_responder_struct.xyz = bvalid_i; // + // Initiator inout signals + // How to assign a signal from an initiator struct member named xyz. + // All available initiator output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Initiator output signals + // Initiator inout signals + // Initiate a transfer using the data received. + @(posedge clk_i_i); + @(posedge clk_i_i); + // Wait for the responder to complete the transfer then place the responder data into + // fuse_ctrl_core_axi_write_out_responder_struct. + @(posedge clk_i_i); + @(posedge clk_i_i); + responder_struct = fuse_ctrl_core_axi_write_out_responder_struct; + endtask +// pragma uvmf custom initiate_and_get_response end + +// pragma uvmf custom respond_and_wait_for_next_transfer begin +// **************************************************************************** +// The first_transfer variable is used to prevent completing a transfer in the +// first call to this task. For the first call to this task, there is not +// current transfer to complete. +bit first_transfer=1; + +// UVMF_CHANGE_ME +// This task is used by a responder. The task first completes the current +// transfer in progress then waits for the initiator to start the next transfer. + task respond_and_wait_for_next_transfer( + // This argument is used to send data received from the initiator + // back to the sequence item. The sequence determines how to respond. + output fuse_ctrl_core_axi_write_out_initiator_s fuse_ctrl_core_axi_write_out_initiator_struct, + // This argument passes transaction variables used by a responder + // to complete a protocol transfer. The values come from a sequence item. + input fuse_ctrl_core_axi_write_out_responder_s fuse_ctrl_core_axi_write_out_responder_struct + );// pragma tbx xtf + // Variables within the fuse_ctrl_core_axi_write_out_initiator_struct: + // logic core_awready ; + // logic core_wready ; + // axi_pkg::axi_burst_e core_bresp ; + // logic core_bid ; + // logic core_bvalid ; + // Variables within the fuse_ctrl_core_axi_write_out_responder_struct: + // logic core_awready ; + // logic core_wready ; + // axi_pkg::axi_burst_e core_bresp ; + // logic core_bid ; + // logic core_bvalid ; + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clk_i_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available responder input and inout signals listed. + // Responder input signals + // Responder inout signals + // How to assign a signal, named xyz, from an initiator struct member. + // All available responder output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Responder output signals + // awready_o <= fuse_ctrl_core_axi_write_out_initiator_struct.xyz; // + // wready_o <= fuse_ctrl_core_axi_write_out_initiator_struct.xyz; // + // bresp_o <= fuse_ctrl_core_axi_write_out_initiator_struct.xyz; // [$bits(axi_pkg::axi_burst_e)-1:0] + // bid_o <= fuse_ctrl_core_axi_write_out_initiator_struct.xyz; // + // bvalid_o <= fuse_ctrl_core_axi_write_out_initiator_struct.xyz; // + // Responder inout signals + + @(posedge clk_i_i); + if (!first_transfer) begin + // Perform transfer response here. + // Reply using data recieved in the fuse_ctrl_core_axi_write_out_responder_struct. + @(posedge clk_i_i); + // Reply using data recieved in the transaction handle. + @(posedge clk_i_i); + end + // Wait for next transfer then gather info from intiator about the transfer. + // Place the data into the fuse_ctrl_core_axi_write_out_initiator_struct. + @(posedge clk_i_i); + @(posedge clk_i_i); + first_transfer = 0; + endtask +// pragma uvmf custom respond_and_wait_for_next_transfer end + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_if.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_if.sv new file mode 100644 index 0000000..a08368a --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_if.sv @@ -0,0 +1,103 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface contains the fuse_ctrl_core_axi_write_out interface signals. +// It is instantiated once per fuse_ctrl_core_axi_write_out bus. Bus Functional Models, +// BFM's named fuse_ctrl_core_axi_write_out_driver_bfm, are used to drive signals on the bus. +// BFM's named fuse_ctrl_core_axi_write_out_monitor_bfm are used to monitor signals on the +// bus. This interface signal bundle is passed in the port list of +// the BFM in order to give the BFM access to the signals in this +// interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// This template can be used to connect a DUT to these signals +// +// .dut_signal_port(fuse_ctrl_core_axi_write_out_bus.awready), // Agent input +// .dut_signal_port(fuse_ctrl_core_axi_write_out_bus.wready), // Agent input +// .dut_signal_port(fuse_ctrl_core_axi_write_out_bus.bresp), // Agent input +// .dut_signal_port(fuse_ctrl_core_axi_write_out_bus.bid), // Agent input +// .dut_signal_port(fuse_ctrl_core_axi_write_out_bus.bvalid), // Agent input + +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_core_axi_write_out_pkg_hdl::*; + +interface fuse_ctrl_core_axi_write_out_if #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + + ( + input tri clk_i, + input tri rst_ni, + inout tri awready, + inout tri wready, + inout tri [$bits(axi_pkg::axi_burst_e)-1:0] bresp, + inout tri bid, + inout tri bvalid + ); + +modport monitor_port + ( + input clk_i, + input rst_ni, + input awready, + input wready, + input bresp, + input bid, + input bvalid + ); + +modport initiator_port + ( + input clk_i, + input rst_ni, + input awready, + input wready, + input bresp, + input bid, + input bvalid + ); + +modport responder_port + ( + input clk_i, + input rst_ni, + output awready, + output wready, + output bresp, + output bid, + output bvalid + ); + + +// pragma uvmf custom interface_item_additional begin +// pragma uvmf custom interface_item_additional end + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_infact_coverage_strategy.csv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_infact_coverage_strategy.csv new file mode 100644 index 0000000..1c218e1 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_infact_coverage_strategy.csv @@ -0,0 +1,6 @@ +Global +auto_bin_max, 64 + +Name,Type,Include +rand_fields,coverpoint,=rand *.** + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_macros.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_macros.svh new file mode 100644 index 0000000..5f57ee1 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_macros.svh @@ -0,0 +1,171 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains macros used with the fuse_ctrl_core_axi_write_out package. +// These macros include packed struct definitions. These structs are +// used to pass data between classes, hvl, and BFM's, hdl. Use of +// structs are more efficient and simpler to modify. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_struct +// and from_struct methods defined in the macros below that are used in +// the fuse_ctrl_core_axi_write_out_configuration class. +// + `define fuse_ctrl_core_axi_write_out_CONFIGURATION_STRUCT \ +typedef struct packed { \ + uvmf_active_passive_t active_passive; \ + uvmf_initiator_responder_t initiator_responder; \ + } fuse_ctrl_core_axi_write_out_configuration_s; + + `define fuse_ctrl_core_axi_write_out_CONFIGURATION_TO_STRUCT_FUNCTION \ + virtual function fuse_ctrl_core_axi_write_out_configuration_s to_struct();\ + fuse_ctrl_core_axi_write_out_configuration_struct = \ + {\ + this.active_passive,\ + this.initiator_responder\ + };\ + return ( fuse_ctrl_core_axi_write_out_configuration_struct );\ + endfunction + + `define fuse_ctrl_core_axi_write_out_CONFIGURATION_FROM_STRUCT_FUNCTION \ + virtual function void from_struct(fuse_ctrl_core_axi_write_out_configuration_s fuse_ctrl_core_axi_write_out_configuration_struct);\ + {\ + this.active_passive,\ + this.initiator_responder \ + } = fuse_ctrl_core_axi_write_out_configuration_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_monitor_struct +// and from_monitor_struct methods of the fuse_ctrl_core_axi_write_out_transaction class. +// + `define fuse_ctrl_core_axi_write_out_MONITOR_STRUCT typedef struct packed { \ + logic core_awready ; \ + logic core_wready ; \ + axi_pkg::axi_burst_e core_bresp ; \ + logic core_bid ; \ + logic core_bvalid ; \ + } fuse_ctrl_core_axi_write_out_monitor_s; + + `define fuse_ctrl_core_axi_write_out_TO_MONITOR_STRUCT_FUNCTION \ + virtual function fuse_ctrl_core_axi_write_out_monitor_s to_monitor_struct();\ + fuse_ctrl_core_axi_write_out_monitor_struct = \ + { \ + this.core_awready , \ + this.core_wready , \ + this.core_bresp , \ + this.core_bid , \ + this.core_bvalid \ + };\ + return ( fuse_ctrl_core_axi_write_out_monitor_struct);\ + endfunction\ + + `define fuse_ctrl_core_axi_write_out_FROM_MONITOR_STRUCT_FUNCTION \ + virtual function void from_monitor_struct(fuse_ctrl_core_axi_write_out_monitor_s fuse_ctrl_core_axi_write_out_monitor_struct);\ + {\ + this.core_awready , \ + this.core_wready , \ + this.core_bresp , \ + this.core_bid , \ + this.core_bvalid \ + } = fuse_ctrl_core_axi_write_out_monitor_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_initiator_struct +// and from_initiator_struct methods of the fuse_ctrl_core_axi_write_out_transaction class. +// Also update the comments in the driver BFM. +// + `define fuse_ctrl_core_axi_write_out_INITIATOR_STRUCT typedef struct packed { \ + logic core_awready ; \ + logic core_wready ; \ + axi_pkg::axi_burst_e core_bresp ; \ + logic core_bid ; \ + logic core_bvalid ; \ + } fuse_ctrl_core_axi_write_out_initiator_s; + + `define fuse_ctrl_core_axi_write_out_TO_INITIATOR_STRUCT_FUNCTION \ + virtual function fuse_ctrl_core_axi_write_out_initiator_s to_initiator_struct();\ + fuse_ctrl_core_axi_write_out_initiator_struct = \ + {\ + this.core_awready , \ + this.core_wready , \ + this.core_bresp , \ + this.core_bid , \ + this.core_bvalid \ + };\ + return ( fuse_ctrl_core_axi_write_out_initiator_struct);\ + endfunction + + `define fuse_ctrl_core_axi_write_out_FROM_INITIATOR_STRUCT_FUNCTION \ + virtual function void from_initiator_struct(fuse_ctrl_core_axi_write_out_initiator_s fuse_ctrl_core_axi_write_out_initiator_struct);\ + {\ + this.core_awready , \ + this.core_wready , \ + this.core_bresp , \ + this.core_bid , \ + this.core_bvalid \ + } = fuse_ctrl_core_axi_write_out_initiator_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_responder_struct +// and from_responder_struct methods of the fuse_ctrl_core_axi_write_out_transaction class. +// Also update the comments in the driver BFM. +// + `define fuse_ctrl_core_axi_write_out_RESPONDER_STRUCT typedef struct packed { \ + logic core_awready ; \ + logic core_wready ; \ + axi_pkg::axi_burst_e core_bresp ; \ + logic core_bid ; \ + logic core_bvalid ; \ + } fuse_ctrl_core_axi_write_out_responder_s; + + `define fuse_ctrl_core_axi_write_out_TO_RESPONDER_STRUCT_FUNCTION \ + virtual function fuse_ctrl_core_axi_write_out_responder_s to_responder_struct();\ + fuse_ctrl_core_axi_write_out_responder_struct = \ + {\ + this.core_awready , \ + this.core_wready , \ + this.core_bresp , \ + this.core_bid , \ + this.core_bvalid \ + };\ + return ( fuse_ctrl_core_axi_write_out_responder_struct);\ + endfunction + + `define fuse_ctrl_core_axi_write_out_FROM_RESPONDER_STRUCT_FUNCTION \ + virtual function void from_responder_struct(fuse_ctrl_core_axi_write_out_responder_s fuse_ctrl_core_axi_write_out_responder_struct);\ + {\ + this.core_awready , \ + this.core_wready , \ + this.core_bresp , \ + this.core_bid , \ + this.core_bvalid \ + } = fuse_ctrl_core_axi_write_out_responder_struct;\ + endfunction +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_monitor.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_monitor.svh new file mode 100644 index 0000000..638ba10 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_monitor.svh @@ -0,0 +1,126 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class receives fuse_ctrl_core_axi_write_out transactions observed by the +// fuse_ctrl_core_axi_write_out monitor BFM and broadcasts them through the analysis port +// on the agent. It accesses the monitor BFM through the monitor +// task. This UVM component captures transactions +// for viewing in the waveform viewer if the +// enable_transaction_viewing flag is set in the configuration. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_write_out_monitor #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvmf_monitor_base #( + .CONFIG_T(fuse_ctrl_core_axi_write_out_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .BFM_BIND_T(virtual fuse_ctrl_core_axi_write_out_monitor_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .TRANS_T(fuse_ctrl_core_axi_write_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ))); + + `uvm_component_param_utils( fuse_ctrl_core_axi_write_out_monitor #( + AW, + DW, + IW, + UW + )) + +// Structure used to pass data from monitor BFM to monitor class in agent. +// Use to_monitor_struct function to pack transaction variables into structure. +// Use from_monitor_struct function to unpack transaction variables from structure. +`fuse_ctrl_core_axi_write_out_MONITOR_STRUCT + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the monitor BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// monitor BFM. This allows the monitor BFM to call the notify_transaction +// function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// *************************************************************************** + virtual task run_phase(uvm_phase phase); + // Start monitor BFM thread and don't call super.run() in order to + // override the default monitor proxy 'pull' behavior with the more + // emulation-friendly BFM 'push' approach using the notify_transaction + // function below + bfm.start_monitoring(); + endtask + +// ************************************************************************** + +// This function is called by the monitor BFM. It receives data observed by the +// monitor BFM. Data is passed using the fuse_ctrl_core_axi_write_out_monitor_struct. + virtual function void notify_transaction(input fuse_ctrl_core_axi_write_out_monitor_s fuse_ctrl_core_axi_write_out_monitor_struct); + + + trans = new("trans"); + trans.from_monitor_struct(fuse_ctrl_core_axi_write_out_monitor_struct); + trans.start_time = time_stamp; + trans.end_time = $time; + time_stamp = trans.end_time; + + analyze(trans); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_monitor_bfm.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_monitor_bfm.sv new file mode 100644 index 0000000..8575acd --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_monitor_bfm.sv @@ -0,0 +1,214 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface performs the fuse_ctrl_core_axi_write_out signal monitoring. +// It is accessed by the uvm fuse_ctrl_core_axi_write_out monitor through a virtual +// interface handle in the fuse_ctrl_core_axi_write_out configuration. It monitors the +// signals passed in through the port connection named bus of +// type fuse_ctrl_core_axi_write_out_if. +// +// Input signals from the fuse_ctrl_core_axi_write_out_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// Interface functions and tasks used by UVM components: +// monitor(inout TRANS_T txn); +// This task receives the transaction, txn, from the +// UVM monitor and then populates variables in txn +// from values observed on bus activity. This task +// blocks until an operation on the fuse_ctrl_core_axi_write_out bus is complete. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_core_axi_write_out_pkg_hdl::*; +`include "src/fuse_ctrl_core_axi_write_out_macros.svh" + + +interface fuse_ctrl_core_axi_write_out_monitor_bfm #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + ( fuse_ctrl_core_axi_write_out_if bus ); + // The pragma below and additional ones in-lined further down are for running this BFM on Veloce + // pragma attribute fuse_ctrl_core_axi_write_out_monitor_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: AW=%x DW=%x IW=%x UW=%x ", AW,DW,IW,UW), + UVM_DEBUG) +end +`endif + + + // Structure used to pass transaction data from monitor BFM to monitor class in agent. +`fuse_ctrl_core_axi_write_out_MONITOR_STRUCT + fuse_ctrl_core_axi_write_out_monitor_s fuse_ctrl_core_axi_write_out_monitor_struct; + + // Structure used to pass configuration data from monitor class to monitor BFM. + `fuse_ctrl_core_axi_write_out_CONFIGURATION_STRUCT + + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + tri clk_i_i; + tri rst_ni_i; + tri awready_i; + tri wready_i; + tri [$bits(axi_pkg::axi_burst_e)-1:0] bresp_i; + tri bid_i; + tri bvalid_i; + assign clk_i_i = bus.clk_i; + assign rst_ni_i = bus.rst_ni; + assign awready_i = bus.awready; + assign wready_i = bus.wready; + assign bresp_i = bus.bresp; + assign bid_i = bus.bid; + assign bvalid_i = bus.bvalid; + + // Proxy handle to UVM monitor + fuse_ctrl_core_axi_write_out_pkg::fuse_ctrl_core_axi_write_out_monitor #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) proxy; + // pragma tbx oneway proxy.notify_transaction + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + task wait_for_reset();// pragma tbx xtf + @(posedge clk_i_i) ; + do_wait_for_reset(); + endtask + + // **************************************************************************** + task do_wait_for_reset(); + // pragma uvmf custom reset_condition begin + wait ( rst_ni_i === 1 ) ; + @(posedge clk_i_i) ; + // pragma uvmf custom reset_condition end + endtask + + //****************************************************************** + + task wait_for_num_clocks(input int unsigned count); // pragma tbx xtf + @(posedge clk_i_i); + + repeat (count-1) @(posedge clk_i_i); + endtask + + //****************************************************************** + event go; + function void start_monitoring();// pragma tbx xtf + -> go; + endfunction + + // **************************************************************************** + initial begin + @go; + forever begin + @(posedge clk_i_i); + do_monitor( fuse_ctrl_core_axi_write_out_monitor_struct ); + + + proxy.notify_transaction( fuse_ctrl_core_axi_write_out_monitor_struct ); + + end + end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the monitor BFM. It is called by the monitor within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the monitor BFM needs to be aware of the new configuration + // variables. + // + function void configure(fuse_ctrl_core_axi_write_out_configuration_s fuse_ctrl_core_axi_write_out_configuration_arg); // pragma tbx xtf + initiator_responder = fuse_ctrl_core_axi_write_out_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + + + // **************************************************************************** + + task do_monitor(output fuse_ctrl_core_axi_write_out_monitor_s fuse_ctrl_core_axi_write_out_monitor_struct); + // + // Available struct members: + // // fuse_ctrl_core_axi_write_out_monitor_struct.core_awready + // // fuse_ctrl_core_axi_write_out_monitor_struct.core_wready + // // fuse_ctrl_core_axi_write_out_monitor_struct.core_bresp + // // fuse_ctrl_core_axi_write_out_monitor_struct.core_bid + // // fuse_ctrl_core_axi_write_out_monitor_struct.core_bvalid + // // + // Reference code; + // How to wait for signal value + // while (control_signal === 1'b1) @(posedge clk_i_i); + // + // How to assign a struct member, named xyz, from a signal. + // All available input signals listed. + // fuse_ctrl_core_axi_write_out_monitor_struct.xyz = awready_i; // + // fuse_ctrl_core_axi_write_out_monitor_struct.xyz = wready_i; // + // fuse_ctrl_core_axi_write_out_monitor_struct.xyz = bresp_i; // [$bits(axi_pkg::axi_burst_e)-1:0] + // fuse_ctrl_core_axi_write_out_monitor_struct.xyz = bid_i; // + // fuse_ctrl_core_axi_write_out_monitor_struct.xyz = bvalid_i; // + // pragma uvmf custom do_monitor begin + // UVMF_CHANGE_ME : Implement protocol monitoring. The commented reference code + // below are examples of how to capture signal values and assign them to + // structure members. All available input signals are listed. The 'while' + // code example shows how to wait for a synchronous flow control signal. This + // task should return when a complete transfer has been observed. Once this task is + // exited with captured values, it is then called again to wait for and observe + // the next transfer. One clock cycle is consumed between calls to do_monitor. + @(posedge clk_i_i); + @(posedge clk_i_i); + @(posedge clk_i_i); + @(posedge clk_i_i); + // pragma uvmf custom do_monitor end + endtask + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_random_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_random_sequence.svh new file mode 100644 index 0000000..beb75c5 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_random_sequence.svh @@ -0,0 +1,87 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This sequences randomizes the fuse_ctrl_core_axi_write_out transaction and sends it +// to the UVM driver. +// +// This sequence constructs and randomizes a fuse_ctrl_core_axi_write_out_transaction. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_write_out_random_sequence #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends fuse_ctrl_core_axi_write_out_sequence_base #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ); + + `uvm_object_param_utils( fuse_ctrl_core_axi_write_out_random_sequence #( + AW, + DW, + IW, + UW + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //***************************************************************** + function new(string name = ""); + super.new(name); + endfunction: new + + // **************************************************************************** + // TASK : body() + // This task is automatically executed when this sequence is started using the + // start(sequencerHandle) task. + // + task body(); + + // Construct the transaction + req=fuse_ctrl_core_axi_write_out_transaction#( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )::type_id::create("req"); + start_item(req); + // Randomize the transaction + if(!req.randomize()) `uvm_fatal("SEQ", "fuse_ctrl_core_axi_write_out_random_sequence::body()-fuse_ctrl_core_axi_write_out_transaction randomization failed") + // Send the transaction to the fuse_ctrl_core_axi_write_out_driver_bfm via the sequencer and fuse_ctrl_core_axi_write_out_driver. + finish_item(req); + `uvm_info("SEQ", {"Response:",req.convert2string()},UVM_MEDIUM) + + endtask + +endclass: fuse_ctrl_core_axi_write_out_random_sequence + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_responder_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_responder_sequence.svh new file mode 100644 index 0000000..cae8be2 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_responder_sequence.svh @@ -0,0 +1,83 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class can be used to provide stimulus when an interface +// has been configured to run in a responder mode. It +// will never finish by default, always going back to the driver +// and driver BFM for the next transaction with which to respond. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_write_out_responder_sequence #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends fuse_ctrl_core_axi_write_out_sequence_base #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ); + + `uvm_object_param_utils( fuse_ctrl_core_axi_write_out_responder_sequence #( + AW, + DW, + IW, + UW + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "fuse_ctrl_core_axi_write_out_responder_sequence"); + super.new(name); + endfunction + + task body(); + req=fuse_ctrl_core_axi_write_out_transaction#( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )::type_id::create("req"); + forever begin + start_item(req); + finish_item(req); + // pragma uvmf custom body begin + // UVMF_CHANGE_ME : Do something here with the resulting req item. The + // finish_item() call above will block until the req transaction is ready + // to be handled by the responder sequence. + // If this was an item that required a response, the expectation is + // that the response should be populated within this transaction now. + `uvm_info("SEQ",$sformatf("Processed txn: %s",req.convert2string()),UVM_HIGH) + // pragma uvmf custom body end + end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_sequence_base.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_sequence_base.svh new file mode 100644 index 0000000..870d9f7 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_sequence_base.svh @@ -0,0 +1,140 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the class used as the base class for all sequences +// for this interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_write_out_sequence_base #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvmf_sequence_base #( + .REQ(fuse_ctrl_core_axi_write_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .RSP(fuse_ctrl_core_axi_write_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ))); + + `uvm_object_param_utils( fuse_ctrl_core_axi_write_out_sequence_base #( + AW, + DW, + IW, + UW + )) + + // variables + typedef fuse_ctrl_core_axi_write_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) fuse_ctrl_core_axi_write_out_transaction_req_t; + fuse_ctrl_core_axi_write_out_transaction_req_t req; + typedef fuse_ctrl_core_axi_write_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) fuse_ctrl_core_axi_write_out_transaction_rsp_t; + fuse_ctrl_core_axi_write_out_transaction_rsp_t rsp; + + // Event for identifying when a response was received from the sequencer + event new_rsp; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // TASK : get_responses() + // This task recursively gets sequence item responses from the sequencer. + // + virtual task get_responses(); + fork + begin + // Block until new rsp available + get_response(rsp); + // New rsp received. Indicate to sequence using event. + ->new_rsp; + // Display the received response transaction + `uvm_info("SEQ", {"New response transaction:",rsp.convert2string()}, UVM_MEDIUM) + end + join_none + endtask + + // **************************************************************************** + // TASK : pre_body() + // This task is called automatically when start is called with call_pre_post set to 1 (default). + // By calling get_responses() within pre_body() any derived sequences are automatically + // processing response transactions. Only un-comment this call to get_responses() if you + // have configured the interface driver to utilize the response transaction path by setting + // the configuration variable "return_transaction_response" to 1. Otherwise it is possible + // to impact runtime performance and memory utilization. + // + virtual task pre_body(); + // pragma uvmf custom pre_body begin +// get_responses(); + // pragma uvmf custom pre_body end + endtask + + // **************************************************************************** + // TASK : body() + // This task is called automatically when start is called. This sequence sends + // a req sequence item to the sequencer identified as an argument in the call + // to start. + // + virtual task body(); + // pragma uvmf custom body begin + start_item(req); + finish_item(req); + // pragma uvmf custom body end + endtask + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name =""); + super.new( name ); + // pragma uvmf custom new begin + req = fuse_ctrl_core_axi_write_out_transaction_req_t::type_id::create("req"); + rsp = fuse_ctrl_core_axi_write_out_transaction_rsp_t::type_id::create("rsp"); + // pragma uvmf custom new end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_transaction.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_transaction.svh new file mode 100644 index 0000000..42eb5e7 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_transaction.svh @@ -0,0 +1,232 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class defines the variables required for an fuse_ctrl_core_axi_write_out +// transaction. Class variables to be displayed in waveform transaction +// viewing are added to the transaction viewing stream in the add_to_wave +// function. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_write_out_transaction #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvmf_transaction_base; + + `uvm_object_param_utils( fuse_ctrl_core_axi_write_out_transaction #( + AW, + DW, + IW, + UW + )) + + logic core_awready ; + logic core_wready ; + axi_pkg::axi_burst_e core_bresp ; + logic core_bid ; + logic core_bvalid ; + + //Constraints for the transaction variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //******************************************************************* + //******************************************************************* + // Macros that define structs and associated functions are + // located in fuse_ctrl_core_axi_write_out_macros.svh + + //******************************************************************* + // Monitor macro used by fuse_ctrl_core_axi_write_out_monitor and fuse_ctrl_core_axi_write_out_monitor_bfm + // This struct is defined in fuse_ctrl_core_axi_write_out_macros.svh + `fuse_ctrl_core_axi_write_out_MONITOR_STRUCT + fuse_ctrl_core_axi_write_out_monitor_s fuse_ctrl_core_axi_write_out_monitor_struct; + //******************************************************************* + // FUNCTION: to_monitor_struct() + // This function packs transaction variables into a fuse_ctrl_core_axi_write_out_monitor_s + // structure. The function returns the handle to the fuse_ctrl_core_axi_write_out_monitor_struct. + // This function is defined in fuse_ctrl_core_axi_write_out_macros.svh + `fuse_ctrl_core_axi_write_out_TO_MONITOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_monitor_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_core_axi_write_out_macros.svh + `fuse_ctrl_core_axi_write_out_FROM_MONITOR_STRUCT_FUNCTION + + //******************************************************************* + // Initiator macro used by fuse_ctrl_core_axi_write_out_driver and fuse_ctrl_core_axi_write_out_driver_bfm + // to communicate initiator driven data to fuse_ctrl_core_axi_write_out_driver_bfm. + // This struct is defined in fuse_ctrl_core_axi_write_out_macros.svh + `fuse_ctrl_core_axi_write_out_INITIATOR_STRUCT + fuse_ctrl_core_axi_write_out_initiator_s fuse_ctrl_core_axi_write_out_initiator_struct; + //******************************************************************* + // FUNCTION: to_initiator_struct() + // This function packs transaction variables into a fuse_ctrl_core_axi_write_out_initiator_s + // structure. The function returns the handle to the fuse_ctrl_core_axi_write_out_initiator_struct. + // This function is defined in fuse_ctrl_core_axi_write_out_macros.svh + `fuse_ctrl_core_axi_write_out_TO_INITIATOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_initiator_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_core_axi_write_out_macros.svh + `fuse_ctrl_core_axi_write_out_FROM_INITIATOR_STRUCT_FUNCTION + + //******************************************************************* + // Responder macro used by fuse_ctrl_core_axi_write_out_driver and fuse_ctrl_core_axi_write_out_driver_bfm + // to communicate Responder driven data to fuse_ctrl_core_axi_write_out_driver_bfm. + // This struct is defined in fuse_ctrl_core_axi_write_out_macros.svh + `fuse_ctrl_core_axi_write_out_RESPONDER_STRUCT + fuse_ctrl_core_axi_write_out_responder_s fuse_ctrl_core_axi_write_out_responder_struct; + //******************************************************************* + // FUNCTION: to_responder_struct() + // This function packs transaction variables into a fuse_ctrl_core_axi_write_out_responder_s + // structure. The function returns the handle to the fuse_ctrl_core_axi_write_out_responder_struct. + // This function is defined in fuse_ctrl_core_axi_write_out_macros.svh + `fuse_ctrl_core_axi_write_out_TO_RESPONDER_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_responder_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_core_axi_write_out_macros.svh + `fuse_ctrl_core_axi_write_out_FROM_RESPONDER_STRUCT_FUNCTION + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + endfunction + + // **************************************************************************** + // FUNCTION: convert2string() + // This function converts all variables in this class to a single string for + // logfile reporting. + // + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + // UVMF_CHANGE_ME : Customize format if desired. + return $sformatf("core_awready:0x%x core_wready:0x%x core_bresp:0x%x core_bid:0x%x core_bvalid:0x%x ",core_awready,core_wready,core_bresp,core_bid,core_bvalid); + // pragma uvmf custom convert2string end + endfunction + + //******************************************************************* + // FUNCTION: do_print() + // This function is automatically called when the .print() function + // is called on this class. + // + virtual function void do_print(uvm_printer printer); + // pragma uvmf custom do_print begin + // UVMF_CHANGE_ME : Current contents of do_print allows for the use of UVM 1.1d, 1.2 or P1800.2. + // Update based on your own printing preference according to your preferred UVM version + $display(convert2string()); + // pragma uvmf custom do_print end + endfunction + + //******************************************************************* + // FUNCTION: do_compare() + // This function is automatically called when the .compare() function + // is called on this class. + // + virtual function bit do_compare (uvm_object rhs, uvm_comparer comparer); + fuse_ctrl_core_axi_write_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) RHS; + if (!$cast(RHS,rhs)) return 0; + // pragma uvmf custom do_compare begin + // UVMF_CHANGE_ME : Eliminate comparison of variables not to be used for compare + return (super.do_compare(rhs,comparer) + &&(this.core_awready == RHS.core_awready) + &&(this.core_wready == RHS.core_wready) + &&(this.core_bresp == RHS.core_bresp) + &&(this.core_bid == RHS.core_bid) + &&(this.core_bvalid == RHS.core_bvalid) + ); + // pragma uvmf custom do_compare end + endfunction + + //******************************************************************* + // FUNCTION: do_copy() + // This function is automatically called when the .copy() function + // is called on this class. + // + virtual function void do_copy (uvm_object rhs); + fuse_ctrl_core_axi_write_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) RHS; + assert($cast(RHS,rhs)); + // pragma uvmf custom do_copy begin + super.do_copy(rhs); + this.core_awready = RHS.core_awready; + this.core_wready = RHS.core_wready; + this.core_bresp = RHS.core_bresp; + this.core_bid = RHS.core_bid; + this.core_bvalid = RHS.core_bvalid; + // pragma uvmf custom do_copy end + endfunction + + // **************************************************************************** + // FUNCTION: add_to_wave() + // This function is used to display variables in this class in the waveform + // viewer. The start_time and end_time variables must be set before this + // function is called. If the start_time and end_time variables are not set + // the transaction will be hidden at 0ns on the waveform display. + // + virtual function void add_to_wave(int transaction_viewing_stream_h); + `ifdef QUESTA + if (transaction_view_h == 0) begin + transaction_view_h = $begin_transaction(transaction_viewing_stream_h,"fuse_ctrl_core_axi_write_out_transaction",start_time); + end + super.add_to_wave(transaction_view_h); + // pragma uvmf custom add_to_wave begin + // UVMF_CHANGE_ME : Color can be applied to transaction entries based on content, example below + // case() + // 1 : $add_color(transaction_view_h,"red"); + // default : $add_color(transaction_view_h,"grey"); + // endcase + // UVMF_CHANGE_ME : Eliminate transaction variables not wanted in transaction viewing in the waveform viewer + $add_attribute(transaction_view_h,core_awready,"core_awready"); + $add_attribute(transaction_view_h,core_wready,"core_wready"); + $add_attribute(transaction_view_h,core_bresp,"core_bresp"); + $add_attribute(transaction_view_h,core_bid,"core_bid"); + $add_attribute(transaction_view_h,core_bvalid,"core_bvalid"); + // pragma uvmf custom add_to_wave end + $end_transaction(transaction_view_h,end_time); + $free_transaction(transaction_view_h); + `endif // QUESTA + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_transaction_coverage.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_transaction_coverage.svh new file mode 100644 index 0000000..38c1b44 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_transaction_coverage.svh @@ -0,0 +1,103 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class records fuse_ctrl_core_axi_write_out transaction information using +// a covergroup named fuse_ctrl_core_axi_write_out_transaction_cg. An instance of this +// coverage component is instantiated in the uvmf_parameterized_agent +// if the has_coverage flag is set. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_write_out_transaction_coverage #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvm_subscriber #(.T(fuse_ctrl_core_axi_write_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ))); + + `uvm_component_param_utils( fuse_ctrl_core_axi_write_out_transaction_coverage #( + AW, + DW, + IW, + UW + )) + + T coverage_trans; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + covergroup fuse_ctrl_core_axi_write_out_transaction_cg; + // pragma uvmf custom covergroup begin + // UVMF_CHANGE_ME : Add coverage bins, crosses, exclusions, etc. according to coverage needs. + option.auto_bin_max=1024; + option.per_instance=1; + core_awready: coverpoint coverage_trans.core_awready; + core_wready: coverpoint coverage_trans.core_wready; + core_bresp: coverpoint coverage_trans.core_bresp; + core_bid: coverpoint coverage_trans.core_bid; + core_bvalid: coverpoint coverage_trans.core_bvalid; + // pragma uvmf custom covergroup end + endgroup + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new(string name="", uvm_component parent=null); + super.new(name,parent); + fuse_ctrl_core_axi_write_out_transaction_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that transaction variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + endfunction + + // **************************************************************************** + // FUNCTION : build_phase() + // This function is the standard UVM build_phase. + // + function void build_phase(uvm_phase phase); + fuse_ctrl_core_axi_write_out_transaction_cg.set_inst_name($sformatf("fuse_ctrl_core_axi_write_out_transaction_cg_%s",get_full_name())); + endfunction + + // **************************************************************************** + // FUNCTION: write (T t) + // This function is automatically executed when a transaction arrives on the + // analysis_export. It copies values from the variables in the transaction + // to local variables used to collect functional coverage. + // + virtual function void write (T t); + `uvm_info("COV","Received transaction",UVM_HIGH); + coverage_trans = t; + fuse_ctrl_core_axi_write_out_transaction_cg.sample(); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_typedefs.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_typedefs.svh new file mode 100644 index 0000000..f2a7bdb --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_typedefs.svh @@ -0,0 +1,34 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the host server when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_typedefs_hdl.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_typedefs_hdl.svh new file mode 100644 index 0000000..0d58518 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_typedefs_hdl.svh @@ -0,0 +1,35 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the emulator when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/yaml/fuse_ctrl_core_axi_write_out_interface.yaml b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/yaml/fuse_ctrl_core_axi_write_out_interface.yaml new file mode 100644 index 0000000..7f30cb1 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/yaml/fuse_ctrl_core_axi_write_out_interface.yaml @@ -0,0 +1,81 @@ +uvmf: + interfaces: + fuse_ctrl_core_axi_write_out: + clock: clk_i + config_constraints: [] + config_vars: [] + existing_library_component: 'True' + gen_inbound_streaming_driver: 'False' + hdl_pkg_parameters: [] + hdl_typedefs: [] + hvl_pkg_parameters: [] + hvl_typedefs: [] + parameters: + - name: AW + type: int + value: '32' + - name: DW + type: int + value: '32' + - name: IW + type: int + value: '3' + - name: UW + type: int + value: '32' + ports: + - dir: input + name: awready + reset_value: '''bz' + width: '1' + - dir: input + name: wready + reset_value: '''bz' + width: '1' + - dir: input + name: bresp + reset_value: '''bz' + width: '[''$bits(axi_pkg::axi_burst_e)'']' + - dir: input + name: bid + reset_value: '''bz' + width: '1' + - dir: input + name: bvalid + reset_value: '''bz' + width: '1' + reset: rst_ni + reset_assertion_level: 'False' + transaction_constraints: [] + transaction_vars: + - comment: '' + iscompare: 'True' + isrand: 'False' + name: core_awready + type: logic + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'False' + name: core_wready + type: logic + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'False' + name: core_bresp + type: axi_pkg::axi_burst_e + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'False' + name: core_bid + type: logic + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'False' + name: core_bvalid + type: logic + unpacked_dimension: '' + use_dpi_link: 'False' diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/.project b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/.project new file mode 100644 index 0000000..3038bf5 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/.project @@ -0,0 +1,30 @@ + + + fuse_ctrl_in_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/.svproject b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/.svproject new file mode 100644 index 0000000..40fcc43 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/Makefile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/Makefile new file mode 100644 index 0000000..9fd3230 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/Makefile @@ -0,0 +1,66 @@ +# fuse_ctrl_in interface packages source +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +fuse_ctrl_in_PKG = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_in_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_filelist_hvl.f + +fuse_ctrl_in_PKG_HDL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_in_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_filelist_hdl.f + +fuse_ctrl_in_PKG_XRTL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_in_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_filelist_xrtl.f + +COMP_fuse_ctrl_in_PKG_TGT_0 = q_comp_fuse_ctrl_in_pkg +COMP_fuse_ctrl_in_PKG_TGT_1 = v_comp_fuse_ctrl_in_pkg +COMP_fuse_ctrl_in_PKG_TGT = $(COMP_fuse_ctrl_in_PKG_TGT_$(USE_VELOCE)) + +comp_fuse_ctrl_in_pkg: $(COMP_fuse_ctrl_in_PKG_TGT) + +q_comp_fuse_ctrl_in_pkg: + $(HDL_COMP_CMD) $(fuse_ctrl_in_PKG_HDL) + $(HVL_COMP_CMD) $(fuse_ctrl_in_PKG) + $(HDL_COMP_CMD) $(fuse_ctrl_in_PKG_XRTL) + +v_comp_fuse_ctrl_in_pkg: + $(HVL_COMP_CMD) $(fuse_ctrl_in_PKG_HDL) + $(HVL_COMP_CMD) $(fuse_ctrl_in_PKG) + $(VELANALYZE_CMD) $(fuse_ctrl_in_PKG_HDL) + $(VELANALYZE_HVL_CMD) $(fuse_ctrl_in_PKG) + $(HDL_COMP_CMD) $(fuse_ctrl_in_PKG_XRTL) + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export fuse_ctrl_in_IF_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_in_pkg/dpi + +C_FILE_COMPILE_LIST_fuse_ctrl_in_pkg = \ + +O_FILE_COMPILE_LIST_fuse_ctrl_in_pkg = $(notdir $(C_FILE_COMPILE_LIST_fuse_ctrl_in_pkg:.c=.o)) + +GCC_COMP_ARGS_fuse_ctrl_in_pkg += -I$(fuse_ctrl_in_IF_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_fuse_ctrl_in_pkg += $(fuse_ctrl_in_IF_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_fuse_ctrl_in_pkg += \ + \ + -o .so + +comp_fuse_ctrl_in_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Interface C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_fuse_ctrl_in_pkg) $(C_FILE_COMPILE_LIST_fuse_ctrl_in_pkg) + @echo "--------------------------------" + @echo "Linking Interface C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_fuse_ctrl_in_pkg) $(O_FILE_COMPILE_LIST_fuse_ctrl_in_pkg) + @echo "--------------------------------" + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/compile.do b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/compile.do new file mode 100644 index 0000000..2645839 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/compile.do @@ -0,0 +1,14 @@ +# Tcl do file for compile of fuse_ctrl_in interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_in_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_filelist_hdl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_in_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_filelist_hvl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_in_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_filelist_xrtl.f \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in.compile new file mode 100644 index 0000000..ae6ef9d --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in.compile @@ -0,0 +1,3 @@ +needs: + - fuse_ctrl_in_hvl.compile + - fuse_ctrl_in_hdl.compile diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_bfm.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_bfm.vinfo new file mode 100644 index 0000000..cf88b70 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_bfm.vinfo @@ -0,0 +1,6 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use fuse_ctrl_in_pkg_hdl.vinfo ++incdir+@vinfodir +src/fuse_ctrl_in_if.sv +src/fuse_ctrl_in_driver_bfm.sv +src/fuse_ctrl_in_monitor_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_common.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_common.compile new file mode 100644 index 0000000..82360a8 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_common.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +incdir: + - . + - ${uvm_path}/src +src: + - fuse_ctrl_in_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_filelist_hdl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_filelist_hdl.f new file mode 100644 index 0000000..959aa9e --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_filelist_hdl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_filelist_hvl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_filelist_hvl.f new file mode 100644 index 0000000..e57e74b --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_filelist_hvl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_pkg.sv \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_filelist_xrtl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_filelist_xrtl.f new file mode 100644 index 0000000..1e9819e --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_filelist_xrtl.f @@ -0,0 +1,3 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_if.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_monitor_bfm.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_driver_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_hdl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_hdl.compile new file mode 100644 index 0000000..da38bec --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_hdl.compile @@ -0,0 +1,9 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ./fuse_ctrl_in_common.compile +incdir: + - . +src: + - src/fuse_ctrl_in_if.sv + - src/fuse_ctrl_in_monitor_bfm.sv + - src/fuse_ctrl_in_driver_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_hvl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_hvl.compile new file mode 100644 index 0000000..210102c --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_hvl.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ./fuse_ctrl_in_common.compile +incdir: + - . +src: + - fuse_ctrl_in_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_pkg.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_pkg.sv new file mode 100644 index 0000000..58df769 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_pkg.sv @@ -0,0 +1,91 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - + +// - +// - +// - + +// - +// - +// - + +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_in_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg_hdl::*; + import uvmf_base_pkg::*; + import fuse_ctrl_in_pkg_hdl::*; + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + `include "src/fuse_ctrl_in_macros.svh" + + export fuse_ctrl_in_pkg_hdl::*; + + + + // Parameters defined as HVL parameters + + `include "src/fuse_ctrl_in_typedefs.svh" + `include "src/fuse_ctrl_in_transaction.svh" + + `include "src/fuse_ctrl_in_configuration.svh" + `include "src/fuse_ctrl_in_driver.svh" + `include "src/fuse_ctrl_in_monitor.svh" + + `include "src/fuse_ctrl_in_transaction_coverage.svh" + `include "src/fuse_ctrl_in_sequence_base.svh" + `include "src/fuse_ctrl_in_random_sequence.svh" + + `include "src/fuse_ctrl_in_responder_sequence.svh" + `include "src/fuse_ctrl_in2reg_adapter.svh" + + `include "src/fuse_ctrl_in_agent.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new interface sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the interface package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_pkg.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_pkg.vinfo new file mode 100644 index 0000000..164f125 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_pkg.vinfo @@ -0,0 +1,4 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use fuse_ctrl_in_pkg_hdl.vinfo ++incdir+@vinfodir +fuse_ctrl_in_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_pkg_hdl.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_pkg_hdl.sv new file mode 100644 index 0000000..b13dcf7 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_pkg_hdl.sv @@ -0,0 +1,52 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that needs to be compiled and synthesized +// for running on Veloce. +// +// CONTAINS: +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_in_pkg_hdl; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HDL parameters + + `include "src/fuse_ctrl_in_typedefs_hdl.svh" + `include "src/fuse_ctrl_in_macros.svh" + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_pkg_hdl.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_pkg_hdl.vinfo new file mode 100644 index 0000000..79de2ad --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_pkg_hdl.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +fuse_ctrl_in_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_pkg_sve.F b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_pkg_sve.F new file mode 100644 index 0000000..345b7e8 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_pkg_sve.F @@ -0,0 +1,10 @@ +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + ++incdir+. +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_filelist_hdl.f +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_filelist_hvl.f diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in2reg_adapter.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in2reg_adapter.svh new file mode 100644 index 0000000..1a7408a --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in2reg_adapter.svh @@ -0,0 +1,137 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the UVM register adapter for the fuse_ctrl_in interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_in2reg_adapter #( + int AlertSyncOn = 3, + caliptra_otp_ctrl_pkg::lfsr_seed_t RndConstLfrSeed = caliptra_otp_ctrl_pkg::RndCnstLfsrSeedDefault, + caliptra_otp_ctrl_pkg::lfsr_perm_t RndCnstLfsrPerm = caliptra_otp_ctrl_pkg::RndCnstLfsrPermDefault, + string MemInitFile = "" + ) extends uvm_reg_adapter; + + `uvm_object_param_utils( fuse_ctrl_in2reg_adapter #( + AlertSyncOn, + RndConstLfrSeed, + RndCnstLfsrPerm, + MemInitFile + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //-------------------------------------------------------------------- + // new + //-------------------------------------------------------------------- + function new (string name = "fuse_ctrl_in2reg_adapter" ); + super.new(name); + // pragma uvmf custom new begin + // UVMF_CHANGE_ME : Configure the adapter regarding byte enables and provides response. + + // Does the protocol the Agent is modeling support byte enables? + // 0 = NO + // 1 = YES + supports_byte_enable = 0; + + // Does the Agent's Driver provide separate response sequence items? + // i.e. Does the driver call seq_item_port.put() + // and do the sequences call get_response()? + // 0 = NO + // 1 = YES + provides_responses = 0; + // pragma uvmf custom new end + + endfunction: new + + //-------------------------------------------------------------------- + // reg2bus + //-------------------------------------------------------------------- + virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw); + + fuse_ctrl_in_transaction #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) trans_h = fuse_ctrl_in_transaction #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + )::type_id::create("trans_h"); + + // pragma uvmf custom reg2bus begin + // UVMF_CHANGE_ME : Fill in the reg2bus adapter mapping registe fields to protocol fields. + + //Adapt the following for your sequence item type + // trans_h.op = (rw.kind == UVM_READ) ? WB_READ : WB_WRITE; + //Copy over address + // trans_h.addr = rw.addr; + //Copy over write data + // trans_h.data = rw.data; + + // pragma uvmf custom reg2bus end + + // Return the adapted transaction + return trans_h; + + endfunction: reg2bus + + //-------------------------------------------------------------------- + // bus2reg + //-------------------------------------------------------------------- + virtual function void bus2reg(uvm_sequence_item bus_item, + ref uvm_reg_bus_op rw); + fuse_ctrl_in_transaction #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) trans_h; + if (!$cast(trans_h, bus_item)) begin + `uvm_fatal("ADAPT","Provided bus_item is not of the correct type") + return; + end + // pragma uvmf custom bus2reg begin + // UVMF_CHANGE_ME : Fill in the bus2reg adapter mapping protocol fields to register fields. + //Adapt the following for your sequence item type + //Copy over instruction type + // rw.kind = (trans_h.op == WB_WRITE) ? UVM_WRITE : UVM_READ; + //Copy over address + // rw.addr = trans_h.addr; + //Copy over read data + // rw.data = trans_h.data; + //Check for errors on the bus and return UVM_NOT_OK if there is an error + // rw.status = UVM_IS_OK; + // pragma uvmf custom bus2reg end + + endfunction: bus2reg + +endclass : fuse_ctrl_in2reg_adapter + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_agent.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_agent.svh new file mode 100644 index 0000000..8448ed4 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_agent.svh @@ -0,0 +1,102 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: Protocol specific agent class definition +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_in_agent #( + int AlertSyncOn = 3, + caliptra_otp_ctrl_pkg::lfsr_seed_t RndConstLfrSeed = caliptra_otp_ctrl_pkg::RndCnstLfsrSeedDefault, + caliptra_otp_ctrl_pkg::lfsr_perm_t RndCnstLfsrPerm = caliptra_otp_ctrl_pkg::RndCnstLfsrPermDefault, + string MemInitFile = "" + ) extends uvmf_parameterized_agent #( + .CONFIG_T(fuse_ctrl_in_configuration #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + )), + .DRIVER_T(fuse_ctrl_in_driver #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + )), + .MONITOR_T(fuse_ctrl_in_monitor #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + )), + .COVERAGE_T(fuse_ctrl_in_transaction_coverage #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + )), + .TRANS_T(fuse_ctrl_in_transaction #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + )) + ); + + `uvm_component_param_utils( fuse_ctrl_in_agent #( + AlertSyncOn, + RndConstLfrSeed, + RndCnstLfsrPerm, + MemInitFile + )) + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** + // FUNCTION: build_phase + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + if (configuration.active_passive == ACTIVE) begin + // Place sequencer handle into configuration object + // so that it may be retrieved from configuration + // rather than using uvm_config_db + configuration.sequencer = this.sequencer; + end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_configuration.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_configuration.svh new file mode 100644 index 0000000..decc63a --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_configuration.svh @@ -0,0 +1,233 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class contains all variables and functions used +// to configure the fuse_ctrl_in agent and its bfm's. It gets the +// bfm's from the uvm_config_db for use by the agent. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_in_configuration #( + int AlertSyncOn = 3, + caliptra_otp_ctrl_pkg::lfsr_seed_t RndConstLfrSeed = caliptra_otp_ctrl_pkg::RndCnstLfsrSeedDefault, + caliptra_otp_ctrl_pkg::lfsr_perm_t RndCnstLfsrPerm = caliptra_otp_ctrl_pkg::RndCnstLfsrPermDefault, + string MemInitFile = "" + ) extends uvmf_parameterized_agent_configuration_base #( + .DRIVER_BFM_BIND_T(virtual fuse_ctrl_in_driver_bfm #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + )), + .MONITOR_BFM_BIND_T( virtual fuse_ctrl_in_monitor_bfm #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ))); + + `uvm_object_param_utils( fuse_ctrl_in_configuration #( + AlertSyncOn, + RndConstLfrSeed, + RndCnstLfsrPerm, + MemInitFile + )) + + + // Sequencer handle populated by agent + uvm_sequencer #(fuse_ctrl_in_transaction #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) ) sequencer; + + //Constraints for the configuration variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + covergroup fuse_ctrl_in_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + // pragma uvmf custom covergroup end + endgroup + + //******************************************************************* + //******************************************************************* + // Structure used to pass configuration variables to monitor and driver BFM's. + // Use to_struct function to pack variables into structure. + // Use from_struct function to unpack variables from structure. + // This structure is defined in fuse_ctrl_in_macros.svh + `fuse_ctrl_in_CONFIGURATION_STRUCT + fuse_ctrl_in_configuration_s fuse_ctrl_in_configuration_struct; + //******************************************************************* + // FUNCTION: to_struct() + // This function packs variables into a fuse_ctrl_in_configuration_s + // structure. The function returns the handle to the fuse_ctrl_in_configuration_struct. + // This function is defined in fuse_ctrl_in_macros.svh + `fuse_ctrl_in_CONFIGURATION_TO_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_struct() + // This function unpacks the struct provided as an argument into + // variables of this class. + // This function is defined in fuse_ctrl_in_macros.svh + `fuse_ctrl_in_CONFIGURATION_FROM_STRUCT_FUNCTION + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + // Construct the covergroup for this configuration class + fuse_ctrl_in_configuration_cg = new; + endfunction + + // **************************************************************************** + // FUNCTION: post_randomize() + // This function is automatically called after the randomize() function + // is executed. + // + function void post_randomize(); + super.post_randomize(); + fuse_ctrl_in_configuration_cg.sample(); + endfunction + + // **************************************************************************** + // FUNCTION: initialize + // This function causes the configuration to retrieve + // its virtual interface handle from the uvm_config_db. + // This function also makes itself available to its + // agent through the uvm_config_db. + // + // ARGUMENTS: + // uvmf_active_passive_t activity: + // This argument identifies the simulation level + // as either BLOCK, CHIP, SIMULATION, etc. + // + // AGENT_PATH: + // This argument identifies the path to this + // configurations agent. This configuration + // makes itself available to the agent specified + // by agent_path by placing itself into the + // uvm_config_db. + // + // INTERFACE_NAME: + // This argument identifies the string name of + // this configurations BFM's. This string + // name is used to retrieve the driver and + // monitor BFM from the uvm_config_db. + // + virtual function void initialize(uvmf_active_passive_t activity, + string agent_path, + string interface_name); + + super.initialize( activity, agent_path, interface_name); + // The covergroup is given the same name as the interface + fuse_ctrl_in_configuration_cg.set_inst_name(interface_name); + + // This configuration places itself into the uvm_config_db for the agent, identified by the agent_path variable, to retrieve. + uvm_config_db #( fuse_ctrl_in_configuration #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) + )::set( null ,agent_path,UVMF_AGENT_CONFIG, this ); + + // This configuration also places itself in the config db using the same identifier used by the interface. This allows users to access + // configuration variables and the interface through the bfm api class rather than directly accessing the BFM. This is useful for + // accessingthe BFM when using Veloce + uvm_config_db #( fuse_ctrl_in_configuration #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) + )::set( null ,UVMF_CONFIGURATIONS, interface_name, this ); + + fuse_ctrl_in_configuration_cg.set_inst_name($sformatf("fuse_ctrl_in_configuration_cg_%s",get_full_name())); + +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. + `uvm_info("CFG", + $psprintf("The agent at '%s' is using interface named %s has the following parameters: AlertSyncOn=%x RndConstLfrSeed=%x RndCnstLfsrPerm=%x MemInitFile=%x ", agent_path, interface_name, AlertSyncOn ,RndConstLfrSeed ,RndCnstLfsrPerm ,MemInitFile ), + UVM_DEBUG) + + // pragma uvmf custom initialize begin + // This controls whether or not the agent returns a transaction handle in the driver when calling + // item_done() back into the sequencer or not. If set to 1, a transaction is sent back which means + // the sequence on the other end must use the get_response() part of the driver/sequence API. If + // this doesn't occur, there will eventually be response_queue overflow errors during the test. + return_transaction_response = 1'b0; + + // pragma uvmf custom initialize end + + endfunction + + // **************************************************************************** + // TASK: wait_for_reset + // *[Required]* Blocks until reset is released. The wait_for_reset operation is performed + // by a task in the monitor bfm. + virtual task wait_for_reset(); + monitor_bfm.wait_for_reset(); + endtask + + // **************************************************************************** + // TASK: wait_for_num_clocks + // *[Required]* Blocks until specified number of clocks have elapsed. The wait_for_num_clocks + // operation is performed by a task in the monitor bfm. + virtual task wait_for_num_clocks(int clocks); + monitor_bfm.wait_for_num_clocks(clocks); + endtask + + // **************************************************************************** + // FUNCTION : convert2string() + // This function is used to convert variables in this class into a string for log messaging. + // + virtual function string convert2string (); + // pragma uvmf custom convert2string begin + return $sformatf(""); + // pragma uvmf custom convert2string end + endfunction + + // **************************************************************************** + // FUNCTION: get_sequencer + function uvm_sequencer #(fuse_ctrl_in_transaction#( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + )) get_sequencer(); + return sequencer; + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_driver.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_driver.svh new file mode 100644 index 0000000..3ffc4b6 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_driver.svh @@ -0,0 +1,135 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class passes transactions between the sequencer +// and the BFM driver interface. It accesses the driver BFM +// through the bfm handle. This driver +// passes transactions to the driver BFM through the access +// task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_in_driver #( + int AlertSyncOn = 3, + caliptra_otp_ctrl_pkg::lfsr_seed_t RndConstLfrSeed = caliptra_otp_ctrl_pkg::RndCnstLfsrSeedDefault, + caliptra_otp_ctrl_pkg::lfsr_perm_t RndCnstLfsrPerm = caliptra_otp_ctrl_pkg::RndCnstLfsrPermDefault, + string MemInitFile = "" + ) extends uvmf_driver_base #( + .CONFIG_T(fuse_ctrl_in_configuration #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) ), + .BFM_BIND_T(virtual fuse_ctrl_in_driver_bfm #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) ), + .REQ(fuse_ctrl_in_transaction #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) ), + .RSP(fuse_ctrl_in_transaction #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) )); + + `uvm_component_param_utils( fuse_ctrl_in_driver #( + AlertSyncOn, + RndConstLfrSeed, + RndCnstLfsrPerm, + MemInitFile + )) +//******************************************************************* +// Macros that define structs located in fuse_ctrl_in_macros.svh +//******************************************************************* +// Initiator macro used by fuse_ctrl_in_driver and fuse_ctrl_in_driver_bfm +// to communicate initiator driven data to fuse_ctrl_in_driver_bfm. +`fuse_ctrl_in_INITIATOR_STRUCT + fuse_ctrl_in_initiator_s fuse_ctrl_in_initiator_struct; +//******************************************************************* +// Responder macro used by fuse_ctrl_in_driver and fuse_ctrl_in_driver_bfm +// to communicate Responder driven data to fuse_ctrl_in_driver_bfm. +`fuse_ctrl_in_RESPONDER_STRUCT + fuse_ctrl_in_responder_s fuse_ctrl_in_responder_struct; + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent=null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the driver BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// driver BFM. This allows the driver BFM to call tasks and function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// **************************************************************************** +// This task is called by the run_phase in uvmf_driver_base. + virtual task access( inout REQ txn ); +// pragma uvmf custom access begin + if (configuration.initiator_responder==RESPONDER) begin + // Complete current transfer and wait for next transfer + bfm.respond_and_wait_for_next_transfer( + fuse_ctrl_in_initiator_struct, + txn.to_responder_struct() + ); + // Unpack information about initiated transfer received by this responder + txn.from_initiator_struct(fuse_ctrl_in_initiator_struct); + end else begin + // Initiate a transfer and get response + bfm.initiate_and_get_response( + txn.to_initiator_struct(), + fuse_ctrl_in_responder_struct + ); + // Unpack transfer response information received by this initiator + txn.from_responder_struct(fuse_ctrl_in_responder_struct); + end +// pragma uvmf custom access end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_driver_bfm.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_driver_bfm.sv new file mode 100644 index 0000000..fb3abaf --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_driver_bfm.sv @@ -0,0 +1,337 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This interface performs the fuse_ctrl_in signal driving. It is +// accessed by the uvm fuse_ctrl_in driver through a virtual interface +// handle in the fuse_ctrl_in configuration. It drives the singals passed +// in through the port connection named bus of type fuse_ctrl_in_if. +// +// Input signals from the fuse_ctrl_in_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// This bfm drives signals with a _o suffix. These signals +// are driven onto signals within fuse_ctrl_in_if based on INITIATOR/RESPONDER and/or +// ARBITRATION/GRANT status. +// +// The output signal connections are as follows: +// signal_o -> bus.signal +// +// +// Interface functions and tasks used by UVM components: +// +// configure: +// This function gets configuration attributes from the +// UVM driver to set any required BFM configuration +// variables such as 'initiator_responder'. +// +// initiate_and_get_response: +// This task is used to perform signaling activity for initiating +// a protocol transfer. The task initiates the transfer, using +// input data from the initiator struct. Then the task captures +// response data, placing the data into the response struct. +// The response struct is returned to the driver class. +// +// respond_and_wait_for_next_transfer: +// This task is used to complete a current transfer as a responder +// and then wait for the initiator to start the next transfer. +// The task uses data in the responder struct to drive protocol +// signals to complete the transfer. The task then waits for +// the next transfer. Once the next transfer begins, data from +// the initiator is placed into the initiator struct and sent +// to the responder sequence for processing to determine +// what data to respond with. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_in_pkg_hdl::*; +`include "src/fuse_ctrl_in_macros.svh" + +interface fuse_ctrl_in_driver_bfm #( + int AlertSyncOn = 3, + caliptra_otp_ctrl_pkg::lfsr_seed_t RndConstLfrSeed = caliptra_otp_ctrl_pkg::RndCnstLfsrSeedDefault, + caliptra_otp_ctrl_pkg::lfsr_perm_t RndCnstLfsrPerm = caliptra_otp_ctrl_pkg::RndCnstLfsrPermDefault, + string MemInitFile = "" + ) + (fuse_ctrl_in_if bus); + // The following pragma and additional ones in-lined further below are for running this BFM on Veloce + // pragma attribute fuse_ctrl_in_driver_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: AlertSyncOn=%x RndConstLfrSeed=%x RndCnstLfsrPerm=%x MemInitFile=%x ", AlertSyncOn,RndConstLfrSeed,RndCnstLfsrPerm,MemInitFile), + UVM_DEBUG) +end +`endif + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + tri clk_i_i; + tri rst_ni_i; + + // Signal list (all signals are capable of being inputs and outputs for the sake + // of supporting both INITIATOR and RESPONDER mode operation. Expectation is that + // directionality in the config file was from the point-of-view of the INITIATOR + + // INITIATOR mode input signals + + // INITIATOR mode output signals + tri [$bits(edn_pkg::edn_req_t)-1:0] edn_i_i; + reg [$bits(edn_pkg::edn_req_t)-1:0] edn_i_o = 'bz; + tri [ast_pkg::NumAlerts * $bits(caliptra_prim_alert_pkg::alert_rx_t)-1:0] alert_rx_i_i; + reg [ast_pkg::NumAlerts * $bits(caliptra_prim_alert_pkg::alert_rx_t)-1:0] alert_rx_i_o = 'bz; + tri [$bits(ast_pkg::ast_obs_ctrl_t)-1:0] obs_ctrl_i_i; + reg [$bits(ast_pkg::ast_obs_ctrl_t)-1:0] obs_ctrl_i_o = 'bz; + tri [$bits(caliptra_otp_ctrl_pkg::otp_ast_req_t)-1:0] otp_ast_pwr_seq_h_i_i; + reg [$bits(caliptra_otp_ctrl_pkg::otp_ast_req_t)-1:0] otp_ast_pwr_seq_h_i_o = 'bz; + tri scan_en_i_i; + reg scan_en_i_o = 'bz; + tri scan_rst_ni_i; + reg scan_rst_ni_o = 'bz; + tri scanmode_i_i; + reg scanmode_i_o = 'bz; + + // Bi-directional signals + + + assign clk_i_i = bus.clk_i; + assign rst_ni_i = bus.rst_ni; + + // These are signals marked as 'input' by the config file, but the signals will be + // driven by this BFM if put into RESPONDER mode (flipping all signal directions around) + + + // These are signals marked as 'output' by the config file, but the outputs will + // not be driven by this BFM unless placed in INITIATOR mode. + assign bus.edn_i = (initiator_responder == INITIATOR) ? edn_i_o : 'bz; + assign edn_i_i = bus.edn_i; + assign bus.alert_rx_i = (initiator_responder == INITIATOR) ? alert_rx_i_o : 'bz; + assign alert_rx_i_i = bus.alert_rx_i; + assign bus.obs_ctrl_i = (initiator_responder == INITIATOR) ? obs_ctrl_i_o : 'bz; + assign obs_ctrl_i_i = bus.obs_ctrl_i; + assign bus.otp_ast_pwr_seq_h_i = (initiator_responder == INITIATOR) ? otp_ast_pwr_seq_h_i_o : 'bz; + assign otp_ast_pwr_seq_h_i_i = bus.otp_ast_pwr_seq_h_i; + assign bus.scan_en_i = (initiator_responder == INITIATOR) ? scan_en_i_o : 'bz; + assign scan_en_i_i = bus.scan_en_i; + assign bus.scan_rst_ni = (initiator_responder == INITIATOR) ? scan_rst_ni_o : 'bz; + assign scan_rst_ni_i = bus.scan_rst_ni; + assign bus.scanmode_i = (initiator_responder == INITIATOR) ? scanmode_i_o : 'bz; + assign scanmode_i_i = bus.scanmode_i; + + // Proxy handle to UVM driver + fuse_ctrl_in_pkg::fuse_ctrl_in_driver #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) proxy; + // pragma tbx oneway proxy.my_function_name_in_uvm_driver + + // **************************************************************************** + // **************************************************************************** + // Macros that define structs located in fuse_ctrl_in_macros.svh + // **************************************************************************** + // Struct for passing configuration data from fuse_ctrl_in_driver to this BFM + // **************************************************************************** + `fuse_ctrl_in_CONFIGURATION_STRUCT + // **************************************************************************** + // Structs for INITIATOR and RESPONDER data flow + //******************************************************************* + // Initiator macro used by fuse_ctrl_in_driver and fuse_ctrl_in_driver_bfm + // to communicate initiator driven data to fuse_ctrl_in_driver_bfm. + `fuse_ctrl_in_INITIATOR_STRUCT + fuse_ctrl_in_initiator_s initiator_struct; + // Responder macro used by fuse_ctrl_in_driver and fuse_ctrl_in_driver_bfm + // to communicate Responder driven data to fuse_ctrl_in_driver_bfm. + `fuse_ctrl_in_RESPONDER_STRUCT + fuse_ctrl_in_responder_s responder_struct; + + // **************************************************************************** +// pragma uvmf custom reset_condition_and_response begin + // Always block used to return signals to reset value upon assertion of reset + always @( negedge rst_ni_i ) + begin + // RESPONDER mode output signals + // INITIATOR mode output signals + edn_i_o <= 'bz; + alert_rx_i_o <= 'bz; + obs_ctrl_i_o <= 'bz; + otp_ast_pwr_seq_h_i_o <= 'bz; + scan_en_i_o <= 'bz; + scan_rst_ni_o <= 'bz; + scanmode_i_o <= 'bz; + // Bi-directional signals + + end +// pragma uvmf custom reset_condition_and_response end + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the driver BFM. It is called by the driver within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the driver BFM needs to be aware of the new configuration + // variables. + // + + function void configure(fuse_ctrl_in_configuration_s fuse_ctrl_in_configuration_arg); // pragma tbx xtf + initiator_responder = fuse_ctrl_in_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + +// pragma uvmf custom initiate_and_get_response begin +// **************************************************************************** +// UVMF_CHANGE_ME +// This task is used by an initator. The task first initiates a transfer then +// waits for the responder to complete the transfer. + task initiate_and_get_response( + // This argument passes transaction variables used by an initiator + // to perform the initial part of a protocol transfer. The values + // come from a sequence item created in a sequence. + input fuse_ctrl_in_initiator_s fuse_ctrl_in_initiator_struct, + // This argument is used to send data received from the responder + // back to the sequence item. The sequence item is returned to the sequence. + output fuse_ctrl_in_responder_s fuse_ctrl_in_responder_struct + );// pragma tbx xtf + // + // Members within the fuse_ctrl_in_initiator_struct: + // caliptra_prim_alert_pkg::alert_rx_t set_alert_rx_i ; + // Members within the fuse_ctrl_in_responder_struct: + // caliptra_prim_alert_pkg::alert_rx_t set_alert_rx_i ; + initiator_struct = fuse_ctrl_in_initiator_struct; + // + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clk_i_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available initiator input and inout signals listed. + // Initiator input signals + // Initiator inout signals + // How to assign a signal from an initiator struct member named xyz. + // All available initiator output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Initiator output signals + // edn_i_o <= fuse_ctrl_in_initiator_struct.xyz; // [$bits(edn_pkg::edn_req_t)-1:0] + // alert_rx_i_o <= fuse_ctrl_in_initiator_struct.xyz; // [ast_pkg::NumAlerts * $bits(caliptra_prim_alert_pkg::alert_rx_t)-1:0] + // obs_ctrl_i_o <= fuse_ctrl_in_initiator_struct.xyz; // [$bits(ast_pkg::ast_obs_ctrl_t)-1:0] + // otp_ast_pwr_seq_h_i_o <= fuse_ctrl_in_initiator_struct.xyz; // [$bits(caliptra_otp_ctrl_pkg::otp_ast_req_t)-1:0] + // scan_en_i_o <= fuse_ctrl_in_initiator_struct.xyz; // + // scan_rst_ni_o <= fuse_ctrl_in_initiator_struct.xyz; // + // scanmode_i_o <= fuse_ctrl_in_initiator_struct.xyz; // + // Initiator inout signals + // Initiate a transfer using the data received. + @(posedge clk_i_i); + @(posedge clk_i_i); + // Wait for the responder to complete the transfer then place the responder data into + // fuse_ctrl_in_responder_struct. + @(posedge clk_i_i); + @(posedge clk_i_i); + responder_struct = fuse_ctrl_in_responder_struct; + endtask +// pragma uvmf custom initiate_and_get_response end + +// pragma uvmf custom respond_and_wait_for_next_transfer begin +// **************************************************************************** +// The first_transfer variable is used to prevent completing a transfer in the +// first call to this task. For the first call to this task, there is not +// current transfer to complete. +bit first_transfer=1; + +// UVMF_CHANGE_ME +// This task is used by a responder. The task first completes the current +// transfer in progress then waits for the initiator to start the next transfer. + task respond_and_wait_for_next_transfer( + // This argument is used to send data received from the initiator + // back to the sequence item. The sequence determines how to respond. + output fuse_ctrl_in_initiator_s fuse_ctrl_in_initiator_struct, + // This argument passes transaction variables used by a responder + // to complete a protocol transfer. The values come from a sequence item. + input fuse_ctrl_in_responder_s fuse_ctrl_in_responder_struct + );// pragma tbx xtf + // Variables within the fuse_ctrl_in_initiator_struct: + // caliptra_prim_alert_pkg::alert_rx_t set_alert_rx_i ; + // Variables within the fuse_ctrl_in_responder_struct: + // caliptra_prim_alert_pkg::alert_rx_t set_alert_rx_i ; + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clk_i_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available responder input and inout signals listed. + // Responder input signals + // fuse_ctrl_in_responder_struct.xyz = edn_i_i; // [$bits(edn_pkg::edn_req_t)-1:0] + // fuse_ctrl_in_responder_struct.xyz = alert_rx_i_i; // [ast_pkg::NumAlerts * $bits(caliptra_prim_alert_pkg::alert_rx_t)-1:0] + // fuse_ctrl_in_responder_struct.xyz = obs_ctrl_i_i; // [$bits(ast_pkg::ast_obs_ctrl_t)-1:0] + // fuse_ctrl_in_responder_struct.xyz = otp_ast_pwr_seq_h_i_i; // [$bits(caliptra_otp_ctrl_pkg::otp_ast_req_t)-1:0] + // fuse_ctrl_in_responder_struct.xyz = scan_en_i_i; // + // fuse_ctrl_in_responder_struct.xyz = scan_rst_ni_i; // + // fuse_ctrl_in_responder_struct.xyz = scanmode_i_i; // + // Responder inout signals + // How to assign a signal, named xyz, from an initiator struct member. + // All available responder output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Responder output signals + // Responder inout signals + + @(posedge clk_i_i); + if (!first_transfer) begin + // Perform transfer response here. + // Reply using data recieved in the fuse_ctrl_in_responder_struct. + @(posedge clk_i_i); + // Reply using data recieved in the transaction handle. + @(posedge clk_i_i); + end + // Wait for next transfer then gather info from intiator about the transfer. + // Place the data into the fuse_ctrl_in_initiator_struct. + @(posedge clk_i_i); + @(posedge clk_i_i); + first_transfer = 0; + endtask +// pragma uvmf custom respond_and_wait_for_next_transfer end + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_if.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_if.sv new file mode 100644 index 0000000..3b48315 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_if.sv @@ -0,0 +1,113 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface contains the fuse_ctrl_in interface signals. +// It is instantiated once per fuse_ctrl_in bus. Bus Functional Models, +// BFM's named fuse_ctrl_in_driver_bfm, are used to drive signals on the bus. +// BFM's named fuse_ctrl_in_monitor_bfm are used to monitor signals on the +// bus. This interface signal bundle is passed in the port list of +// the BFM in order to give the BFM access to the signals in this +// interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// This template can be used to connect a DUT to these signals +// +// .dut_signal_port(fuse_ctrl_in_bus.edn_i), // Agent output +// .dut_signal_port(fuse_ctrl_in_bus.alert_rx_i), // Agent output +// .dut_signal_port(fuse_ctrl_in_bus.obs_ctrl_i), // Agent output +// .dut_signal_port(fuse_ctrl_in_bus.otp_ast_pwr_seq_h_i), // Agent output +// .dut_signal_port(fuse_ctrl_in_bus.scan_en_i), // Agent output +// .dut_signal_port(fuse_ctrl_in_bus.scan_rst_ni), // Agent output +// .dut_signal_port(fuse_ctrl_in_bus.scanmode_i), // Agent output + +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_in_pkg_hdl::*; + +interface fuse_ctrl_in_if #( + int AlertSyncOn = 3, + caliptra_otp_ctrl_pkg::lfsr_seed_t RndConstLfrSeed = caliptra_otp_ctrl_pkg::RndCnstLfsrSeedDefault, + caliptra_otp_ctrl_pkg::lfsr_perm_t RndCnstLfsrPerm = caliptra_otp_ctrl_pkg::RndCnstLfsrPermDefault, + string MemInitFile = "" + ) + + ( + input tri clk_i, + input tri rst_ni, + inout tri [$bits(edn_pkg::edn_req_t)-1:0] edn_i, + inout tri [ast_pkg::NumAlerts * $bits(caliptra_prim_alert_pkg::alert_rx_t)-1:0] alert_rx_i, + inout tri [$bits(ast_pkg::ast_obs_ctrl_t)-1:0] obs_ctrl_i, + inout tri [$bits(caliptra_otp_ctrl_pkg::otp_ast_req_t)-1:0] otp_ast_pwr_seq_h_i, + inout tri scan_en_i, + inout tri scan_rst_ni, + inout tri scanmode_i + ); + +modport monitor_port + ( + input clk_i, + input rst_ni, + input edn_i, + input alert_rx_i, + input obs_ctrl_i, + input otp_ast_pwr_seq_h_i, + input scan_en_i, + input scan_rst_ni, + input scanmode_i + ); + +modport initiator_port + ( + input clk_i, + input rst_ni, + output edn_i, + output alert_rx_i, + output obs_ctrl_i, + output otp_ast_pwr_seq_h_i, + output scan_en_i, + output scan_rst_ni, + output scanmode_i + ); + +modport responder_port + ( + input clk_i, + input rst_ni, + input edn_i, + input alert_rx_i, + input obs_ctrl_i, + input otp_ast_pwr_seq_h_i, + input scan_en_i, + input scan_rst_ni, + input scanmode_i + ); + + +// pragma uvmf custom interface_item_additional begin +// pragma uvmf custom interface_item_additional end + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_infact_coverage_strategy.csv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_infact_coverage_strategy.csv new file mode 100644 index 0000000..1c218e1 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_infact_coverage_strategy.csv @@ -0,0 +1,6 @@ +Global +auto_bin_max, 64 + +Name,Type,Include +rand_fields,coverpoint,=rand *.** + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_macros.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_macros.svh new file mode 100644 index 0000000..cf85634 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_macros.svh @@ -0,0 +1,135 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains macros used with the fuse_ctrl_in package. +// These macros include packed struct definitions. These structs are +// used to pass data between classes, hvl, and BFM's, hdl. Use of +// structs are more efficient and simpler to modify. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_struct +// and from_struct methods defined in the macros below that are used in +// the fuse_ctrl_in_configuration class. +// + `define fuse_ctrl_in_CONFIGURATION_STRUCT \ +typedef struct packed { \ + uvmf_active_passive_t active_passive; \ + uvmf_initiator_responder_t initiator_responder; \ + } fuse_ctrl_in_configuration_s; + + `define fuse_ctrl_in_CONFIGURATION_TO_STRUCT_FUNCTION \ + virtual function fuse_ctrl_in_configuration_s to_struct();\ + fuse_ctrl_in_configuration_struct = \ + {\ + this.active_passive,\ + this.initiator_responder\ + };\ + return ( fuse_ctrl_in_configuration_struct );\ + endfunction + + `define fuse_ctrl_in_CONFIGURATION_FROM_STRUCT_FUNCTION \ + virtual function void from_struct(fuse_ctrl_in_configuration_s fuse_ctrl_in_configuration_struct);\ + {\ + this.active_passive,\ + this.initiator_responder \ + } = fuse_ctrl_in_configuration_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_monitor_struct +// and from_monitor_struct methods of the fuse_ctrl_in_transaction class. +// + `define fuse_ctrl_in_MONITOR_STRUCT typedef struct packed { \ + caliptra_prim_alert_pkg::alert_rx_t set_alert_rx_i ; \ + } fuse_ctrl_in_monitor_s; + + `define fuse_ctrl_in_TO_MONITOR_STRUCT_FUNCTION \ + virtual function fuse_ctrl_in_monitor_s to_monitor_struct();\ + fuse_ctrl_in_monitor_struct = \ + { \ + this.set_alert_rx_i \ + };\ + return ( fuse_ctrl_in_monitor_struct);\ + endfunction\ + + `define fuse_ctrl_in_FROM_MONITOR_STRUCT_FUNCTION \ + virtual function void from_monitor_struct(fuse_ctrl_in_monitor_s fuse_ctrl_in_monitor_struct);\ + {\ + this.set_alert_rx_i \ + } = fuse_ctrl_in_monitor_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_initiator_struct +// and from_initiator_struct methods of the fuse_ctrl_in_transaction class. +// Also update the comments in the driver BFM. +// + `define fuse_ctrl_in_INITIATOR_STRUCT typedef struct packed { \ + caliptra_prim_alert_pkg::alert_rx_t set_alert_rx_i ; \ + } fuse_ctrl_in_initiator_s; + + `define fuse_ctrl_in_TO_INITIATOR_STRUCT_FUNCTION \ + virtual function fuse_ctrl_in_initiator_s to_initiator_struct();\ + fuse_ctrl_in_initiator_struct = \ + {\ + this.set_alert_rx_i \ + };\ + return ( fuse_ctrl_in_initiator_struct);\ + endfunction + + `define fuse_ctrl_in_FROM_INITIATOR_STRUCT_FUNCTION \ + virtual function void from_initiator_struct(fuse_ctrl_in_initiator_s fuse_ctrl_in_initiator_struct);\ + {\ + this.set_alert_rx_i \ + } = fuse_ctrl_in_initiator_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_responder_struct +// and from_responder_struct methods of the fuse_ctrl_in_transaction class. +// Also update the comments in the driver BFM. +// + `define fuse_ctrl_in_RESPONDER_STRUCT typedef struct packed { \ + caliptra_prim_alert_pkg::alert_rx_t set_alert_rx_i ; \ + } fuse_ctrl_in_responder_s; + + `define fuse_ctrl_in_TO_RESPONDER_STRUCT_FUNCTION \ + virtual function fuse_ctrl_in_responder_s to_responder_struct();\ + fuse_ctrl_in_responder_struct = \ + {\ + this.set_alert_rx_i \ + };\ + return ( fuse_ctrl_in_responder_struct);\ + endfunction + + `define fuse_ctrl_in_FROM_RESPONDER_STRUCT_FUNCTION \ + virtual function void from_responder_struct(fuse_ctrl_in_responder_s fuse_ctrl_in_responder_struct);\ + {\ + this.set_alert_rx_i \ + } = fuse_ctrl_in_responder_struct;\ + endfunction +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_monitor.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_monitor.svh new file mode 100644 index 0000000..6eebd7b --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_monitor.svh @@ -0,0 +1,126 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class receives fuse_ctrl_in transactions observed by the +// fuse_ctrl_in monitor BFM and broadcasts them through the analysis port +// on the agent. It accesses the monitor BFM through the monitor +// task. This UVM component captures transactions +// for viewing in the waveform viewer if the +// enable_transaction_viewing flag is set in the configuration. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_in_monitor #( + int AlertSyncOn = 3, + caliptra_otp_ctrl_pkg::lfsr_seed_t RndConstLfrSeed = caliptra_otp_ctrl_pkg::RndCnstLfsrSeedDefault, + caliptra_otp_ctrl_pkg::lfsr_perm_t RndCnstLfsrPerm = caliptra_otp_ctrl_pkg::RndCnstLfsrPermDefault, + string MemInitFile = "" + ) extends uvmf_monitor_base #( + .CONFIG_T(fuse_ctrl_in_configuration #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + )), + .BFM_BIND_T(virtual fuse_ctrl_in_monitor_bfm #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + )), + .TRANS_T(fuse_ctrl_in_transaction #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ))); + + `uvm_component_param_utils( fuse_ctrl_in_monitor #( + AlertSyncOn, + RndConstLfrSeed, + RndCnstLfsrPerm, + MemInitFile + )) + +// Structure used to pass data from monitor BFM to monitor class in agent. +// Use to_monitor_struct function to pack transaction variables into structure. +// Use from_monitor_struct function to unpack transaction variables from structure. +`fuse_ctrl_in_MONITOR_STRUCT + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the monitor BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// monitor BFM. This allows the monitor BFM to call the notify_transaction +// function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// *************************************************************************** + virtual task run_phase(uvm_phase phase); + // Start monitor BFM thread and don't call super.run() in order to + // override the default monitor proxy 'pull' behavior with the more + // emulation-friendly BFM 'push' approach using the notify_transaction + // function below + bfm.start_monitoring(); + endtask + +// ************************************************************************** + +// This function is called by the monitor BFM. It receives data observed by the +// monitor BFM. Data is passed using the fuse_ctrl_in_monitor_struct. + virtual function void notify_transaction(input fuse_ctrl_in_monitor_s fuse_ctrl_in_monitor_struct); + + + trans = new("trans"); + trans.from_monitor_struct(fuse_ctrl_in_monitor_struct); + trans.start_time = time_stamp; + trans.end_time = $time; + time_stamp = trans.end_time; + + analyze(trans); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_monitor_bfm.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_monitor_bfm.sv new file mode 100644 index 0000000..b068660 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_monitor_bfm.sv @@ -0,0 +1,216 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface performs the fuse_ctrl_in signal monitoring. +// It is accessed by the uvm fuse_ctrl_in monitor through a virtual +// interface handle in the fuse_ctrl_in configuration. It monitors the +// signals passed in through the port connection named bus of +// type fuse_ctrl_in_if. +// +// Input signals from the fuse_ctrl_in_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// Interface functions and tasks used by UVM components: +// monitor(inout TRANS_T txn); +// This task receives the transaction, txn, from the +// UVM monitor and then populates variables in txn +// from values observed on bus activity. This task +// blocks until an operation on the fuse_ctrl_in bus is complete. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_in_pkg_hdl::*; +`include "src/fuse_ctrl_in_macros.svh" + + +interface fuse_ctrl_in_monitor_bfm #( + int AlertSyncOn = 3, + caliptra_otp_ctrl_pkg::lfsr_seed_t RndConstLfrSeed = caliptra_otp_ctrl_pkg::RndCnstLfsrSeedDefault, + caliptra_otp_ctrl_pkg::lfsr_perm_t RndCnstLfsrPerm = caliptra_otp_ctrl_pkg::RndCnstLfsrPermDefault, + string MemInitFile = "" + ) + ( fuse_ctrl_in_if bus ); + // The pragma below and additional ones in-lined further down are for running this BFM on Veloce + // pragma attribute fuse_ctrl_in_monitor_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: AlertSyncOn=%x RndConstLfrSeed=%x RndCnstLfsrPerm=%x MemInitFile=%x ", AlertSyncOn,RndConstLfrSeed,RndCnstLfsrPerm,MemInitFile), + UVM_DEBUG) +end +`endif + + + // Structure used to pass transaction data from monitor BFM to monitor class in agent. +`fuse_ctrl_in_MONITOR_STRUCT + fuse_ctrl_in_monitor_s fuse_ctrl_in_monitor_struct; + + // Structure used to pass configuration data from monitor class to monitor BFM. + `fuse_ctrl_in_CONFIGURATION_STRUCT + + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + tri clk_i_i; + tri rst_ni_i; + tri [$bits(edn_pkg::edn_req_t)-1:0] edn_i_i; + tri [ast_pkg::NumAlerts * $bits(caliptra_prim_alert_pkg::alert_rx_t)-1:0] alert_rx_i_i; + tri [$bits(ast_pkg::ast_obs_ctrl_t)-1:0] obs_ctrl_i_i; + tri [$bits(caliptra_otp_ctrl_pkg::otp_ast_req_t)-1:0] otp_ast_pwr_seq_h_i_i; + tri scan_en_i_i; + tri scan_rst_ni_i; + tri scanmode_i_i; + assign clk_i_i = bus.clk_i; + assign rst_ni_i = bus.rst_ni; + assign edn_i_i = bus.edn_i; + assign alert_rx_i_i = bus.alert_rx_i; + assign obs_ctrl_i_i = bus.obs_ctrl_i; + assign otp_ast_pwr_seq_h_i_i = bus.otp_ast_pwr_seq_h_i; + assign scan_en_i_i = bus.scan_en_i; + assign scan_rst_ni_i = bus.scan_rst_ni; + assign scanmode_i_i = bus.scanmode_i; + + // Proxy handle to UVM monitor + fuse_ctrl_in_pkg::fuse_ctrl_in_monitor #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) proxy; + // pragma tbx oneway proxy.notify_transaction + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + task wait_for_reset();// pragma tbx xtf + @(posedge clk_i_i) ; + do_wait_for_reset(); + endtask + + // **************************************************************************** + task do_wait_for_reset(); + // pragma uvmf custom reset_condition begin + wait ( rst_ni_i === 1 ) ; + @(posedge clk_i_i) ; + // pragma uvmf custom reset_condition end + endtask + + //****************************************************************** + + task wait_for_num_clocks(input int unsigned count); // pragma tbx xtf + @(posedge clk_i_i); + + repeat (count-1) @(posedge clk_i_i); + endtask + + //****************************************************************** + event go; + function void start_monitoring();// pragma tbx xtf + -> go; + endfunction + + // **************************************************************************** + initial begin + @go; + forever begin + @(posedge clk_i_i); + do_monitor( fuse_ctrl_in_monitor_struct ); + + + proxy.notify_transaction( fuse_ctrl_in_monitor_struct ); + + end + end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the monitor BFM. It is called by the monitor within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the monitor BFM needs to be aware of the new configuration + // variables. + // + function void configure(fuse_ctrl_in_configuration_s fuse_ctrl_in_configuration_arg); // pragma tbx xtf + initiator_responder = fuse_ctrl_in_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + + + // **************************************************************************** + + task do_monitor(output fuse_ctrl_in_monitor_s fuse_ctrl_in_monitor_struct); + // + // Available struct members: + // // fuse_ctrl_in_monitor_struct.set_alert_rx_i + // // + // Reference code; + // How to wait for signal value + // while (control_signal === 1'b1) @(posedge clk_i_i); + // + // How to assign a struct member, named xyz, from a signal. + // All available input signals listed. + // fuse_ctrl_in_monitor_struct.xyz = edn_i_i; // [$bits(edn_pkg::edn_req_t)-1:0] + // fuse_ctrl_in_monitor_struct.xyz = alert_rx_i_i; // [ast_pkg::NumAlerts * $bits(caliptra_prim_alert_pkg::alert_rx_t)-1:0] + // fuse_ctrl_in_monitor_struct.xyz = obs_ctrl_i_i; // [$bits(ast_pkg::ast_obs_ctrl_t)-1:0] + // fuse_ctrl_in_monitor_struct.xyz = otp_ast_pwr_seq_h_i_i; // [$bits(caliptra_otp_ctrl_pkg::otp_ast_req_t)-1:0] + // fuse_ctrl_in_monitor_struct.xyz = scan_en_i_i; // + // fuse_ctrl_in_monitor_struct.xyz = scan_rst_ni_i; // + // fuse_ctrl_in_monitor_struct.xyz = scanmode_i_i; // + // pragma uvmf custom do_monitor begin + // UVMF_CHANGE_ME : Implement protocol monitoring. The commented reference code + // below are examples of how to capture signal values and assign them to + // structure members. All available input signals are listed. The 'while' + // code example shows how to wait for a synchronous flow control signal. This + // task should return when a complete transfer has been observed. Once this task is + // exited with captured values, it is then called again to wait for and observe + // the next transfer. One clock cycle is consumed between calls to do_monitor. + @(posedge clk_i_i); + @(posedge clk_i_i); + @(posedge clk_i_i); + @(posedge clk_i_i); + // pragma uvmf custom do_monitor end + endtask + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_random_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_random_sequence.svh new file mode 100644 index 0000000..42aacc2 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_random_sequence.svh @@ -0,0 +1,87 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This sequences randomizes the fuse_ctrl_in transaction and sends it +// to the UVM driver. +// +// This sequence constructs and randomizes a fuse_ctrl_in_transaction. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_in_random_sequence #( + int AlertSyncOn = 3, + caliptra_otp_ctrl_pkg::lfsr_seed_t RndConstLfrSeed = caliptra_otp_ctrl_pkg::RndCnstLfsrSeedDefault, + caliptra_otp_ctrl_pkg::lfsr_perm_t RndCnstLfsrPerm = caliptra_otp_ctrl_pkg::RndCnstLfsrPermDefault, + string MemInitFile = "" + ) + extends fuse_ctrl_in_sequence_base #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ); + + `uvm_object_param_utils( fuse_ctrl_in_random_sequence #( + AlertSyncOn, + RndConstLfrSeed, + RndCnstLfsrPerm, + MemInitFile + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //***************************************************************** + function new(string name = ""); + super.new(name); + endfunction: new + + // **************************************************************************** + // TASK : body() + // This task is automatically executed when this sequence is started using the + // start(sequencerHandle) task. + // + task body(); + + // Construct the transaction + req=fuse_ctrl_in_transaction#( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + )::type_id::create("req"); + start_item(req); + // Randomize the transaction + if(!req.randomize()) `uvm_fatal("SEQ", "fuse_ctrl_in_random_sequence::body()-fuse_ctrl_in_transaction randomization failed") + // Send the transaction to the fuse_ctrl_in_driver_bfm via the sequencer and fuse_ctrl_in_driver. + finish_item(req); + `uvm_info("SEQ", {"Response:",req.convert2string()},UVM_MEDIUM) + + endtask + +endclass: fuse_ctrl_in_random_sequence + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_responder_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_responder_sequence.svh new file mode 100644 index 0000000..239bc5a --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_responder_sequence.svh @@ -0,0 +1,83 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class can be used to provide stimulus when an interface +// has been configured to run in a responder mode. It +// will never finish by default, always going back to the driver +// and driver BFM for the next transaction with which to respond. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_in_responder_sequence #( + int AlertSyncOn = 3, + caliptra_otp_ctrl_pkg::lfsr_seed_t RndConstLfrSeed = caliptra_otp_ctrl_pkg::RndCnstLfsrSeedDefault, + caliptra_otp_ctrl_pkg::lfsr_perm_t RndCnstLfsrPerm = caliptra_otp_ctrl_pkg::RndCnstLfsrPermDefault, + string MemInitFile = "" + ) + extends fuse_ctrl_in_sequence_base #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ); + + `uvm_object_param_utils( fuse_ctrl_in_responder_sequence #( + AlertSyncOn, + RndConstLfrSeed, + RndCnstLfsrPerm, + MemInitFile + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "fuse_ctrl_in_responder_sequence"); + super.new(name); + endfunction + + task body(); + req=fuse_ctrl_in_transaction#( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + )::type_id::create("req"); + forever begin + start_item(req); + finish_item(req); + // pragma uvmf custom body begin + // UVMF_CHANGE_ME : Do something here with the resulting req item. The + // finish_item() call above will block until the req transaction is ready + // to be handled by the responder sequence. + // If this was an item that required a response, the expectation is + // that the response should be populated within this transaction now. + `uvm_info("SEQ",$sformatf("Processed txn: %s",req.convert2string()),UVM_HIGH) + // pragma uvmf custom body end + end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_sequence_base.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_sequence_base.svh new file mode 100644 index 0000000..0a998f1 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_sequence_base.svh @@ -0,0 +1,140 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the class used as the base class for all sequences +// for this interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_in_sequence_base #( + int AlertSyncOn = 3, + caliptra_otp_ctrl_pkg::lfsr_seed_t RndConstLfrSeed = caliptra_otp_ctrl_pkg::RndCnstLfsrSeedDefault, + caliptra_otp_ctrl_pkg::lfsr_perm_t RndCnstLfsrPerm = caliptra_otp_ctrl_pkg::RndCnstLfsrPermDefault, + string MemInitFile = "" + ) extends uvmf_sequence_base #( + .REQ(fuse_ctrl_in_transaction #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + )), + .RSP(fuse_ctrl_in_transaction #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ))); + + `uvm_object_param_utils( fuse_ctrl_in_sequence_base #( + AlertSyncOn, + RndConstLfrSeed, + RndCnstLfsrPerm, + MemInitFile + )) + + // variables + typedef fuse_ctrl_in_transaction #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) fuse_ctrl_in_transaction_req_t; + fuse_ctrl_in_transaction_req_t req; + typedef fuse_ctrl_in_transaction #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) fuse_ctrl_in_transaction_rsp_t; + fuse_ctrl_in_transaction_rsp_t rsp; + + // Event for identifying when a response was received from the sequencer + event new_rsp; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // TASK : get_responses() + // This task recursively gets sequence item responses from the sequencer. + // + virtual task get_responses(); + fork + begin + // Block until new rsp available + get_response(rsp); + // New rsp received. Indicate to sequence using event. + ->new_rsp; + // Display the received response transaction + `uvm_info("SEQ", {"New response transaction:",rsp.convert2string()}, UVM_MEDIUM) + end + join_none + endtask + + // **************************************************************************** + // TASK : pre_body() + // This task is called automatically when start is called with call_pre_post set to 1 (default). + // By calling get_responses() within pre_body() any derived sequences are automatically + // processing response transactions. Only un-comment this call to get_responses() if you + // have configured the interface driver to utilize the response transaction path by setting + // the configuration variable "return_transaction_response" to 1. Otherwise it is possible + // to impact runtime performance and memory utilization. + // + virtual task pre_body(); + // pragma uvmf custom pre_body begin +// get_responses(); + // pragma uvmf custom pre_body end + endtask + + // **************************************************************************** + // TASK : body() + // This task is called automatically when start is called. This sequence sends + // a req sequence item to the sequencer identified as an argument in the call + // to start. + // + virtual task body(); + // pragma uvmf custom body begin + start_item(req); + finish_item(req); + // pragma uvmf custom body end + endtask + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name =""); + super.new( name ); + // pragma uvmf custom new begin + req = fuse_ctrl_in_transaction_req_t::type_id::create("req"); + rsp = fuse_ctrl_in_transaction_rsp_t::type_id::create("rsp"); + // pragma uvmf custom new end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_transaction.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_transaction.svh new file mode 100644 index 0000000..d8559f2 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_transaction.svh @@ -0,0 +1,215 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class defines the variables required for an fuse_ctrl_in +// transaction. Class variables to be displayed in waveform transaction +// viewing are added to the transaction viewing stream in the add_to_wave +// function. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_in_transaction #( + int AlertSyncOn = 3, + caliptra_otp_ctrl_pkg::lfsr_seed_t RndConstLfrSeed = caliptra_otp_ctrl_pkg::RndCnstLfsrSeedDefault, + caliptra_otp_ctrl_pkg::lfsr_perm_t RndCnstLfsrPerm = caliptra_otp_ctrl_pkg::RndCnstLfsrPermDefault, + string MemInitFile = "" + ) extends uvmf_transaction_base; + + `uvm_object_param_utils( fuse_ctrl_in_transaction #( + AlertSyncOn, + RndConstLfrSeed, + RndCnstLfsrPerm, + MemInitFile + )) + + caliptra_prim_alert_pkg::alert_rx_t set_alert_rx_i ; + + //Constraints for the transaction variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //******************************************************************* + //******************************************************************* + // Macros that define structs and associated functions are + // located in fuse_ctrl_in_macros.svh + + //******************************************************************* + // Monitor macro used by fuse_ctrl_in_monitor and fuse_ctrl_in_monitor_bfm + // This struct is defined in fuse_ctrl_in_macros.svh + `fuse_ctrl_in_MONITOR_STRUCT + fuse_ctrl_in_monitor_s fuse_ctrl_in_monitor_struct; + //******************************************************************* + // FUNCTION: to_monitor_struct() + // This function packs transaction variables into a fuse_ctrl_in_monitor_s + // structure. The function returns the handle to the fuse_ctrl_in_monitor_struct. + // This function is defined in fuse_ctrl_in_macros.svh + `fuse_ctrl_in_TO_MONITOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_monitor_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_in_macros.svh + `fuse_ctrl_in_FROM_MONITOR_STRUCT_FUNCTION + + //******************************************************************* + // Initiator macro used by fuse_ctrl_in_driver and fuse_ctrl_in_driver_bfm + // to communicate initiator driven data to fuse_ctrl_in_driver_bfm. + // This struct is defined in fuse_ctrl_in_macros.svh + `fuse_ctrl_in_INITIATOR_STRUCT + fuse_ctrl_in_initiator_s fuse_ctrl_in_initiator_struct; + //******************************************************************* + // FUNCTION: to_initiator_struct() + // This function packs transaction variables into a fuse_ctrl_in_initiator_s + // structure. The function returns the handle to the fuse_ctrl_in_initiator_struct. + // This function is defined in fuse_ctrl_in_macros.svh + `fuse_ctrl_in_TO_INITIATOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_initiator_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_in_macros.svh + `fuse_ctrl_in_FROM_INITIATOR_STRUCT_FUNCTION + + //******************************************************************* + // Responder macro used by fuse_ctrl_in_driver and fuse_ctrl_in_driver_bfm + // to communicate Responder driven data to fuse_ctrl_in_driver_bfm. + // This struct is defined in fuse_ctrl_in_macros.svh + `fuse_ctrl_in_RESPONDER_STRUCT + fuse_ctrl_in_responder_s fuse_ctrl_in_responder_struct; + //******************************************************************* + // FUNCTION: to_responder_struct() + // This function packs transaction variables into a fuse_ctrl_in_responder_s + // structure. The function returns the handle to the fuse_ctrl_in_responder_struct. + // This function is defined in fuse_ctrl_in_macros.svh + `fuse_ctrl_in_TO_RESPONDER_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_responder_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_in_macros.svh + `fuse_ctrl_in_FROM_RESPONDER_STRUCT_FUNCTION + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + endfunction + + // **************************************************************************** + // FUNCTION: convert2string() + // This function converts all variables in this class to a single string for + // logfile reporting. + // + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + // UVMF_CHANGE_ME : Customize format if desired. + return $sformatf("set_alert_rx_i:0x%x ",set_alert_rx_i); + // pragma uvmf custom convert2string end + endfunction + + //******************************************************************* + // FUNCTION: do_print() + // This function is automatically called when the .print() function + // is called on this class. + // + virtual function void do_print(uvm_printer printer); + // pragma uvmf custom do_print begin + // UVMF_CHANGE_ME : Current contents of do_print allows for the use of UVM 1.1d, 1.2 or P1800.2. + // Update based on your own printing preference according to your preferred UVM version + $display(convert2string()); + // pragma uvmf custom do_print end + endfunction + + //******************************************************************* + // FUNCTION: do_compare() + // This function is automatically called when the .compare() function + // is called on this class. + // + virtual function bit do_compare (uvm_object rhs, uvm_comparer comparer); + fuse_ctrl_in_transaction #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) RHS; + if (!$cast(RHS,rhs)) return 0; + // pragma uvmf custom do_compare begin + // UVMF_CHANGE_ME : Eliminate comparison of variables not to be used for compare + return (super.do_compare(rhs,comparer) + ); + // pragma uvmf custom do_compare end + endfunction + + //******************************************************************* + // FUNCTION: do_copy() + // This function is automatically called when the .copy() function + // is called on this class. + // + virtual function void do_copy (uvm_object rhs); + fuse_ctrl_in_transaction #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) RHS; + assert($cast(RHS,rhs)); + // pragma uvmf custom do_copy begin + super.do_copy(rhs); + this.set_alert_rx_i = RHS.set_alert_rx_i; + // pragma uvmf custom do_copy end + endfunction + + // **************************************************************************** + // FUNCTION: add_to_wave() + // This function is used to display variables in this class in the waveform + // viewer. The start_time and end_time variables must be set before this + // function is called. If the start_time and end_time variables are not set + // the transaction will be hidden at 0ns on the waveform display. + // + virtual function void add_to_wave(int transaction_viewing_stream_h); + `ifdef QUESTA + if (transaction_view_h == 0) begin + transaction_view_h = $begin_transaction(transaction_viewing_stream_h,"fuse_ctrl_in_transaction",start_time); + end + super.add_to_wave(transaction_view_h); + // pragma uvmf custom add_to_wave begin + // UVMF_CHANGE_ME : Color can be applied to transaction entries based on content, example below + // case() + // 1 : $add_color(transaction_view_h,"red"); + // default : $add_color(transaction_view_h,"grey"); + // endcase + // UVMF_CHANGE_ME : Eliminate transaction variables not wanted in transaction viewing in the waveform viewer + $add_attribute(transaction_view_h,set_alert_rx_i,"set_alert_rx_i"); + // pragma uvmf custom add_to_wave end + $end_transaction(transaction_view_h,end_time); + $free_transaction(transaction_view_h); + `endif // QUESTA + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_transaction_coverage.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_transaction_coverage.svh new file mode 100644 index 0000000..ab8eedd --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_transaction_coverage.svh @@ -0,0 +1,99 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class records fuse_ctrl_in transaction information using +// a covergroup named fuse_ctrl_in_transaction_cg. An instance of this +// coverage component is instantiated in the uvmf_parameterized_agent +// if the has_coverage flag is set. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_in_transaction_coverage #( + int AlertSyncOn = 3, + caliptra_otp_ctrl_pkg::lfsr_seed_t RndConstLfrSeed = caliptra_otp_ctrl_pkg::RndCnstLfsrSeedDefault, + caliptra_otp_ctrl_pkg::lfsr_perm_t RndCnstLfsrPerm = caliptra_otp_ctrl_pkg::RndCnstLfsrPermDefault, + string MemInitFile = "" + ) extends uvm_subscriber #(.T(fuse_ctrl_in_transaction #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ))); + + `uvm_component_param_utils( fuse_ctrl_in_transaction_coverage #( + AlertSyncOn, + RndConstLfrSeed, + RndCnstLfsrPerm, + MemInitFile + )) + + T coverage_trans; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + covergroup fuse_ctrl_in_transaction_cg; + // pragma uvmf custom covergroup begin + // UVMF_CHANGE_ME : Add coverage bins, crosses, exclusions, etc. according to coverage needs. + option.auto_bin_max=1024; + option.per_instance=1; + set_alert_rx_i: coverpoint coverage_trans.set_alert_rx_i; + // pragma uvmf custom covergroup end + endgroup + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new(string name="", uvm_component parent=null); + super.new(name,parent); + fuse_ctrl_in_transaction_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that transaction variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + endfunction + + // **************************************************************************** + // FUNCTION : build_phase() + // This function is the standard UVM build_phase. + // + function void build_phase(uvm_phase phase); + fuse_ctrl_in_transaction_cg.set_inst_name($sformatf("fuse_ctrl_in_transaction_cg_%s",get_full_name())); + endfunction + + // **************************************************************************** + // FUNCTION: write (T t) + // This function is automatically executed when a transaction arrives on the + // analysis_export. It copies values from the variables in the transaction + // to local variables used to collect functional coverage. + // + virtual function void write (T t); + `uvm_info("COV","Received transaction",UVM_HIGH); + coverage_trans = t; + fuse_ctrl_in_transaction_cg.sample(); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_typedefs.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_typedefs.svh new file mode 100644 index 0000000..f2a7bdb --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_typedefs.svh @@ -0,0 +1,34 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the host server when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_typedefs_hdl.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_typedefs_hdl.svh new file mode 100644 index 0000000..0d58518 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_typedefs_hdl.svh @@ -0,0 +1,35 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the emulator when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/yaml/fuse_ctrl_in_interface.yaml b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/yaml/fuse_ctrl_in_interface.yaml new file mode 100644 index 0000000..691d296 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_in_pkg/yaml/fuse_ctrl_in_interface.yaml @@ -0,0 +1,65 @@ +uvmf: + interfaces: + fuse_ctrl_in: + clock: clk_i + config_constraints: [] + config_vars: [] + existing_library_component: 'True' + gen_inbound_streaming_driver: 'False' + hdl_pkg_parameters: [] + hdl_typedefs: [] + hvl_pkg_parameters: [] + hvl_typedefs: [] + parameters: + - name: AlertSyncOn + type: int + value: '3' + - name: RndConstLfrSeed + type: caliptra_otp_ctrl_pkg::lfsr_seed_t + value: caliptra_otp_ctrl_pkg::RndCnstLfsrSeedDefault + - name: RndCnstLfsrPerm + type: caliptra_otp_ctrl_pkg::lfsr_perm_t + value: caliptra_otp_ctrl_pkg::RndCnstLfsrPermDefault + - name: MemInitFile + type: string + value: '""' + ports: + - dir: output + name: edn_i + reset_value: '''bz' + width: '[''$bits(edn_pkg::edn_req_t)'']' + - dir: output + name: alert_rx_i + reset_value: '''bz' + width: '[''ast_pkg::NumAlerts * $bits(caliptra_prim_alert_pkg::alert_rx_t)'']' + - dir: output + name: obs_ctrl_i + reset_value: '''bz' + width: '[''$bits(ast_pkg::ast_obs_ctrl_t)'']' + - dir: output + name: otp_ast_pwr_seq_h_i + reset_value: '''bz' + width: '[''$bits(caliptra_otp_ctrl_pkg::otp_ast_req_t)'']' + - dir: output + name: scan_en_i + reset_value: '''bz' + width: '1' + - dir: output + name: scan_rst_ni + reset_value: '''bz' + width: '1' + - dir: output + name: scanmode_i + reset_value: '''bz' + width: '1' + reset: rst_ni + reset_assertion_level: 'False' + transaction_constraints: [] + transaction_vars: + - comment: '' + iscompare: 'False' + isrand: 'False' + name: set_alert_rx_i + type: caliptra_prim_alert_pkg::alert_rx_t + unpacked_dimension: '' + use_dpi_link: 'False' diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/.project b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/.project new file mode 100644 index 0000000..bc9bb7a --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/.project @@ -0,0 +1,30 @@ + + + fuse_ctrl_lc_otp_in_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/.svproject b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/.svproject new file mode 100644 index 0000000..e267e6c --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/Makefile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/Makefile new file mode 100644 index 0000000..48df82f --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/Makefile @@ -0,0 +1,66 @@ +# fuse_ctrl_lc_otp_in interface packages source +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +fuse_ctrl_lc_otp_in_PKG = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_lc_otp_in_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_filelist_hvl.f + +fuse_ctrl_lc_otp_in_PKG_HDL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_lc_otp_in_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_filelist_hdl.f + +fuse_ctrl_lc_otp_in_PKG_XRTL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_lc_otp_in_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_filelist_xrtl.f + +COMP_fuse_ctrl_lc_otp_in_PKG_TGT_0 = q_comp_fuse_ctrl_lc_otp_in_pkg +COMP_fuse_ctrl_lc_otp_in_PKG_TGT_1 = v_comp_fuse_ctrl_lc_otp_in_pkg +COMP_fuse_ctrl_lc_otp_in_PKG_TGT = $(COMP_fuse_ctrl_lc_otp_in_PKG_TGT_$(USE_VELOCE)) + +comp_fuse_ctrl_lc_otp_in_pkg: $(COMP_fuse_ctrl_lc_otp_in_PKG_TGT) + +q_comp_fuse_ctrl_lc_otp_in_pkg: + $(HDL_COMP_CMD) $(fuse_ctrl_lc_otp_in_PKG_HDL) + $(HVL_COMP_CMD) $(fuse_ctrl_lc_otp_in_PKG) + $(HDL_COMP_CMD) $(fuse_ctrl_lc_otp_in_PKG_XRTL) + +v_comp_fuse_ctrl_lc_otp_in_pkg: + $(HVL_COMP_CMD) $(fuse_ctrl_lc_otp_in_PKG_HDL) + $(HVL_COMP_CMD) $(fuse_ctrl_lc_otp_in_PKG) + $(VELANALYZE_CMD) $(fuse_ctrl_lc_otp_in_PKG_HDL) + $(VELANALYZE_HVL_CMD) $(fuse_ctrl_lc_otp_in_PKG) + $(HDL_COMP_CMD) $(fuse_ctrl_lc_otp_in_PKG_XRTL) + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export fuse_ctrl_lc_otp_in_IF_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_lc_otp_in_pkg/dpi + +C_FILE_COMPILE_LIST_fuse_ctrl_lc_otp_in_pkg = \ + +O_FILE_COMPILE_LIST_fuse_ctrl_lc_otp_in_pkg = $(notdir $(C_FILE_COMPILE_LIST_fuse_ctrl_lc_otp_in_pkg:.c=.o)) + +GCC_COMP_ARGS_fuse_ctrl_lc_otp_in_pkg += -I$(fuse_ctrl_lc_otp_in_IF_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_fuse_ctrl_lc_otp_in_pkg += $(fuse_ctrl_lc_otp_in_IF_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_fuse_ctrl_lc_otp_in_pkg += \ + \ + -o .so + +comp_fuse_ctrl_lc_otp_in_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Interface C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_fuse_ctrl_lc_otp_in_pkg) $(C_FILE_COMPILE_LIST_fuse_ctrl_lc_otp_in_pkg) + @echo "--------------------------------" + @echo "Linking Interface C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_fuse_ctrl_lc_otp_in_pkg) $(O_FILE_COMPILE_LIST_fuse_ctrl_lc_otp_in_pkg) + @echo "--------------------------------" + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/compile.do b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/compile.do new file mode 100644 index 0000000..2334cca --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/compile.do @@ -0,0 +1,14 @@ +# Tcl do file for compile of fuse_ctrl_lc_otp_in interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_lc_otp_in_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_filelist_hdl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_lc_otp_in_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_filelist_hvl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_lc_otp_in_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_filelist_xrtl.f \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in.compile new file mode 100644 index 0000000..934282f --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in.compile @@ -0,0 +1,3 @@ +needs: + - fuse_ctrl_lc_otp_in_hvl.compile + - fuse_ctrl_lc_otp_in_hdl.compile diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_bfm.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_bfm.vinfo new file mode 100644 index 0000000..35c34c5 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_bfm.vinfo @@ -0,0 +1,6 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use fuse_ctrl_lc_otp_in_pkg_hdl.vinfo ++incdir+@vinfodir +src/fuse_ctrl_lc_otp_in_if.sv +src/fuse_ctrl_lc_otp_in_driver_bfm.sv +src/fuse_ctrl_lc_otp_in_monitor_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_common.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_common.compile new file mode 100644 index 0000000..5683974 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_common.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +incdir: + - . + - ${uvm_path}/src +src: + - fuse_ctrl_lc_otp_in_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_filelist_hdl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_filelist_hdl.f new file mode 100644 index 0000000..fd87f10 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_filelist_hdl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_filelist_hvl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_filelist_hvl.f new file mode 100644 index 0000000..ea2637f --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_filelist_hvl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_pkg.sv \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_filelist_xrtl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_filelist_xrtl.f new file mode 100644 index 0000000..736ca19 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_filelist_xrtl.f @@ -0,0 +1,3 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_if.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_monitor_bfm.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_driver_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_hdl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_hdl.compile new file mode 100644 index 0000000..9def84f --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_hdl.compile @@ -0,0 +1,9 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ./fuse_ctrl_lc_otp_in_common.compile +incdir: + - . +src: + - src/fuse_ctrl_lc_otp_in_if.sv + - src/fuse_ctrl_lc_otp_in_monitor_bfm.sv + - src/fuse_ctrl_lc_otp_in_driver_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_hvl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_hvl.compile new file mode 100644 index 0000000..0374205 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_hvl.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ./fuse_ctrl_lc_otp_in_common.compile +incdir: + - . +src: + - fuse_ctrl_lc_otp_in_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_pkg.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_pkg.sv new file mode 100644 index 0000000..7077717 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_pkg.sv @@ -0,0 +1,91 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - + +// - +// - +// - + +// - +// - +// - + +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_lc_otp_in_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg_hdl::*; + import uvmf_base_pkg::*; + import fuse_ctrl_lc_otp_in_pkg_hdl::*; + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + `include "src/fuse_ctrl_lc_otp_in_macros.svh" + + export fuse_ctrl_lc_otp_in_pkg_hdl::*; + + + + // Parameters defined as HVL parameters + + `include "src/fuse_ctrl_lc_otp_in_typedefs.svh" + `include "src/fuse_ctrl_lc_otp_in_transaction.svh" + + `include "src/fuse_ctrl_lc_otp_in_configuration.svh" + `include "src/fuse_ctrl_lc_otp_in_driver.svh" + `include "src/fuse_ctrl_lc_otp_in_monitor.svh" + + `include "src/fuse_ctrl_lc_otp_in_transaction_coverage.svh" + `include "src/fuse_ctrl_lc_otp_in_sequence_base.svh" + `include "src/fuse_ctrl_lc_otp_in_random_sequence.svh" + + `include "src/fuse_ctrl_lc_otp_in_responder_sequence.svh" + `include "src/fuse_ctrl_lc_otp_in2reg_adapter.svh" + + `include "src/fuse_ctrl_lc_otp_in_agent.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new interface sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the interface package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_pkg.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_pkg.vinfo new file mode 100644 index 0000000..a51e3e0 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_pkg.vinfo @@ -0,0 +1,4 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use fuse_ctrl_lc_otp_in_pkg_hdl.vinfo ++incdir+@vinfodir +fuse_ctrl_lc_otp_in_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_pkg_hdl.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_pkg_hdl.sv new file mode 100644 index 0000000..e1761c3 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_pkg_hdl.sv @@ -0,0 +1,52 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that needs to be compiled and synthesized +// for running on Veloce. +// +// CONTAINS: +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_lc_otp_in_pkg_hdl; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HDL parameters + + `include "src/fuse_ctrl_lc_otp_in_typedefs_hdl.svh" + `include "src/fuse_ctrl_lc_otp_in_macros.svh" + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_pkg_hdl.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_pkg_hdl.vinfo new file mode 100644 index 0000000..536dd9e --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_pkg_hdl.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +fuse_ctrl_lc_otp_in_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_pkg_sve.F b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_pkg_sve.F new file mode 100644 index 0000000..1f476e9 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_pkg_sve.F @@ -0,0 +1,10 @@ +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + ++incdir+. +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_filelist_hdl.f +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_filelist_hvl.f diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in2reg_adapter.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in2reg_adapter.svh new file mode 100644 index 0000000..b1d2bb5 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in2reg_adapter.svh @@ -0,0 +1,112 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the UVM register adapter for the fuse_ctrl_lc_otp_in interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_lc_otp_in2reg_adapter extends uvm_reg_adapter; + + `uvm_object_utils( fuse_ctrl_lc_otp_in2reg_adapter ) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //-------------------------------------------------------------------- + // new + //-------------------------------------------------------------------- + function new (string name = "fuse_ctrl_lc_otp_in2reg_adapter" ); + super.new(name); + // pragma uvmf custom new begin + // UVMF_CHANGE_ME : Configure the adapter regarding byte enables and provides response. + + // Does the protocol the Agent is modeling support byte enables? + // 0 = NO + // 1 = YES + supports_byte_enable = 0; + + // Does the Agent's Driver provide separate response sequence items? + // i.e. Does the driver call seq_item_port.put() + // and do the sequences call get_response()? + // 0 = NO + // 1 = YES + provides_responses = 0; + // pragma uvmf custom new end + + endfunction: new + + //-------------------------------------------------------------------- + // reg2bus + //-------------------------------------------------------------------- + virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw); + + fuse_ctrl_lc_otp_in_transaction trans_h = fuse_ctrl_lc_otp_in_transaction ::type_id::create("trans_h"); + + // pragma uvmf custom reg2bus begin + // UVMF_CHANGE_ME : Fill in the reg2bus adapter mapping registe fields to protocol fields. + + //Adapt the following for your sequence item type + // trans_h.op = (rw.kind == UVM_READ) ? WB_READ : WB_WRITE; + //Copy over address + // trans_h.addr = rw.addr; + //Copy over write data + // trans_h.data = rw.data; + + // pragma uvmf custom reg2bus end + + // Return the adapted transaction + return trans_h; + + endfunction: reg2bus + + //-------------------------------------------------------------------- + // bus2reg + //-------------------------------------------------------------------- + virtual function void bus2reg(uvm_sequence_item bus_item, + ref uvm_reg_bus_op rw); + fuse_ctrl_lc_otp_in_transaction trans_h; + if (!$cast(trans_h, bus_item)) begin + `uvm_fatal("ADAPT","Provided bus_item is not of the correct type") + return; + end + // pragma uvmf custom bus2reg begin + // UVMF_CHANGE_ME : Fill in the bus2reg adapter mapping protocol fields to register fields. + //Adapt the following for your sequence item type + //Copy over instruction type + // rw.kind = (trans_h.op == WB_WRITE) ? UVM_WRITE : UVM_READ; + //Copy over address + // rw.addr = trans_h.addr; + //Copy over read data + // rw.data = trans_h.data; + //Check for errors on the bus and return UVM_NOT_OK if there is an error + // rw.status = UVM_IS_OK; + // pragma uvmf custom bus2reg end + + endfunction: bus2reg + +endclass : fuse_ctrl_lc_otp_in2reg_adapter + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_agent.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_agent.svh new file mode 100644 index 0000000..1bcc445 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_agent.svh @@ -0,0 +1,67 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: Protocol specific agent class definition +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_lc_otp_in_agent extends uvmf_parameterized_agent #( + .CONFIG_T(fuse_ctrl_lc_otp_in_configuration ), + .DRIVER_T(fuse_ctrl_lc_otp_in_driver ), + .MONITOR_T(fuse_ctrl_lc_otp_in_monitor ), + .COVERAGE_T(fuse_ctrl_lc_otp_in_transaction_coverage ), + .TRANS_T(fuse_ctrl_lc_otp_in_transaction ) + ); + + `uvm_component_utils( fuse_ctrl_lc_otp_in_agent ) + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** + // FUNCTION: build_phase + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + if (configuration.active_passive == ACTIVE) begin + // Place sequencer handle into configuration object + // so that it may be retrieved from configuration + // rather than using uvm_config_db + configuration.sequencer = this.sequencer; + end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_configuration.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_configuration.svh new file mode 100644 index 0000000..3d01dbb --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_configuration.svh @@ -0,0 +1,193 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class contains all variables and functions used +// to configure the fuse_ctrl_lc_otp_in agent and its bfm's. It gets the +// bfm's from the uvm_config_db for use by the agent. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_lc_otp_in_configuration extends uvmf_parameterized_agent_configuration_base #( + .DRIVER_BFM_BIND_T(virtual fuse_ctrl_lc_otp_in_driver_bfm ), + .MONITOR_BFM_BIND_T( virtual fuse_ctrl_lc_otp_in_monitor_bfm )); + + `uvm_object_utils( fuse_ctrl_lc_otp_in_configuration ) + + + // Sequencer handle populated by agent + uvm_sequencer #(fuse_ctrl_lc_otp_in_transaction ) sequencer; + + //Constraints for the configuration variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + covergroup fuse_ctrl_lc_otp_in_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + // pragma uvmf custom covergroup end + endgroup + + //******************************************************************* + //******************************************************************* + // Structure used to pass configuration variables to monitor and driver BFM's. + // Use to_struct function to pack variables into structure. + // Use from_struct function to unpack variables from structure. + // This structure is defined in fuse_ctrl_lc_otp_in_macros.svh + `fuse_ctrl_lc_otp_in_CONFIGURATION_STRUCT + fuse_ctrl_lc_otp_in_configuration_s fuse_ctrl_lc_otp_in_configuration_struct; + //******************************************************************* + // FUNCTION: to_struct() + // This function packs variables into a fuse_ctrl_lc_otp_in_configuration_s + // structure. The function returns the handle to the fuse_ctrl_lc_otp_in_configuration_struct. + // This function is defined in fuse_ctrl_lc_otp_in_macros.svh + `fuse_ctrl_lc_otp_in_CONFIGURATION_TO_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_struct() + // This function unpacks the struct provided as an argument into + // variables of this class. + // This function is defined in fuse_ctrl_lc_otp_in_macros.svh + `fuse_ctrl_lc_otp_in_CONFIGURATION_FROM_STRUCT_FUNCTION + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + // Construct the covergroup for this configuration class + fuse_ctrl_lc_otp_in_configuration_cg = new; + endfunction + + // **************************************************************************** + // FUNCTION: post_randomize() + // This function is automatically called after the randomize() function + // is executed. + // + function void post_randomize(); + super.post_randomize(); + fuse_ctrl_lc_otp_in_configuration_cg.sample(); + endfunction + + // **************************************************************************** + // FUNCTION: initialize + // This function causes the configuration to retrieve + // its virtual interface handle from the uvm_config_db. + // This function also makes itself available to its + // agent through the uvm_config_db. + // + // ARGUMENTS: + // uvmf_active_passive_t activity: + // This argument identifies the simulation level + // as either BLOCK, CHIP, SIMULATION, etc. + // + // AGENT_PATH: + // This argument identifies the path to this + // configurations agent. This configuration + // makes itself available to the agent specified + // by agent_path by placing itself into the + // uvm_config_db. + // + // INTERFACE_NAME: + // This argument identifies the string name of + // this configurations BFM's. This string + // name is used to retrieve the driver and + // monitor BFM from the uvm_config_db. + // + virtual function void initialize(uvmf_active_passive_t activity, + string agent_path, + string interface_name); + + super.initialize( activity, agent_path, interface_name); + // The covergroup is given the same name as the interface + fuse_ctrl_lc_otp_in_configuration_cg.set_inst_name(interface_name); + + // This configuration places itself into the uvm_config_db for the agent, identified by the agent_path variable, to retrieve. + uvm_config_db #( fuse_ctrl_lc_otp_in_configuration + )::set( null ,agent_path,UVMF_AGENT_CONFIG, this ); + + // This configuration also places itself in the config db using the same identifier used by the interface. This allows users to access + // configuration variables and the interface through the bfm api class rather than directly accessing the BFM. This is useful for + // accessingthe BFM when using Veloce + uvm_config_db #( fuse_ctrl_lc_otp_in_configuration + )::set( null ,UVMF_CONFIGURATIONS, interface_name, this ); + + fuse_ctrl_lc_otp_in_configuration_cg.set_inst_name($sformatf("fuse_ctrl_lc_otp_in_configuration_cg_%s",get_full_name())); + +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. + `uvm_info("CFG", + $psprintf("The agent at '%s' is using interface named %s has the following parameters: ", agent_path, interface_name, ), + UVM_DEBUG) + + // pragma uvmf custom initialize begin + // This controls whether or not the agent returns a transaction handle in the driver when calling + // item_done() back into the sequencer or not. If set to 1, a transaction is sent back which means + // the sequence on the other end must use the get_response() part of the driver/sequence API. If + // this doesn't occur, there will eventually be response_queue overflow errors during the test. + return_transaction_response = 1'b0; + + // pragma uvmf custom initialize end + + endfunction + + // **************************************************************************** + // TASK: wait_for_reset + // *[Required]* Blocks until reset is released. The wait_for_reset operation is performed + // by a task in the monitor bfm. + virtual task wait_for_reset(); + monitor_bfm.wait_for_reset(); + endtask + + // **************************************************************************** + // TASK: wait_for_num_clocks + // *[Required]* Blocks until specified number of clocks have elapsed. The wait_for_num_clocks + // operation is performed by a task in the monitor bfm. + virtual task wait_for_num_clocks(int clocks); + monitor_bfm.wait_for_num_clocks(clocks); + endtask + + // **************************************************************************** + // FUNCTION : convert2string() + // This function is used to convert variables in this class into a string for log messaging. + // + virtual function string convert2string (); + // pragma uvmf custom convert2string begin + return $sformatf(""); + // pragma uvmf custom convert2string end + endfunction + + // **************************************************************************** + // FUNCTION: get_sequencer + function uvm_sequencer #(fuse_ctrl_lc_otp_in_transaction) get_sequencer(); + return sequencer; + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_driver.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_driver.svh new file mode 100644 index 0000000..fc0a219 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_driver.svh @@ -0,0 +1,105 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class passes transactions between the sequencer +// and the BFM driver interface. It accesses the driver BFM +// through the bfm handle. This driver +// passes transactions to the driver BFM through the access +// task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_lc_otp_in_driver extends uvmf_driver_base #( + .CONFIG_T(fuse_ctrl_lc_otp_in_configuration ), + .BFM_BIND_T(virtual fuse_ctrl_lc_otp_in_driver_bfm ), + .REQ(fuse_ctrl_lc_otp_in_transaction ), + .RSP(fuse_ctrl_lc_otp_in_transaction )); + + `uvm_component_utils( fuse_ctrl_lc_otp_in_driver ) +//******************************************************************* +// Macros that define structs located in fuse_ctrl_lc_otp_in_macros.svh +//******************************************************************* +// Initiator macro used by fuse_ctrl_lc_otp_in_driver and fuse_ctrl_lc_otp_in_driver_bfm +// to communicate initiator driven data to fuse_ctrl_lc_otp_in_driver_bfm. +`fuse_ctrl_lc_otp_in_INITIATOR_STRUCT + fuse_ctrl_lc_otp_in_initiator_s fuse_ctrl_lc_otp_in_initiator_struct; +//******************************************************************* +// Responder macro used by fuse_ctrl_lc_otp_in_driver and fuse_ctrl_lc_otp_in_driver_bfm +// to communicate Responder driven data to fuse_ctrl_lc_otp_in_driver_bfm. +`fuse_ctrl_lc_otp_in_RESPONDER_STRUCT + fuse_ctrl_lc_otp_in_responder_s fuse_ctrl_lc_otp_in_responder_struct; + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent=null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the driver BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// driver BFM. This allows the driver BFM to call tasks and function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// **************************************************************************** +// This task is called by the run_phase in uvmf_driver_base. + virtual task access( inout REQ txn ); +// pragma uvmf custom access begin + if (configuration.initiator_responder==RESPONDER) begin + // Complete current transfer and wait for next transfer + bfm.respond_and_wait_for_next_transfer( + fuse_ctrl_lc_otp_in_initiator_struct, + txn.to_responder_struct() + ); + // Unpack information about initiated transfer received by this responder + txn.from_initiator_struct(fuse_ctrl_lc_otp_in_initiator_struct); + end else begin + // Initiate a transfer and get response + bfm.initiate_and_get_response( + txn.to_initiator_struct(), + fuse_ctrl_lc_otp_in_responder_struct + ); + // Unpack transfer response information received by this initiator + txn.from_responder_struct(fuse_ctrl_lc_otp_in_responder_struct); + end +// pragma uvmf custom access end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_driver_bfm.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_driver_bfm.sv new file mode 100644 index 0000000..30b642a --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_driver_bfm.sv @@ -0,0 +1,321 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This interface performs the fuse_ctrl_lc_otp_in signal driving. It is +// accessed by the uvm fuse_ctrl_lc_otp_in driver through a virtual interface +// handle in the fuse_ctrl_lc_otp_in configuration. It drives the singals passed +// in through the port connection named bus of type fuse_ctrl_lc_otp_in_if. +// +// Input signals from the fuse_ctrl_lc_otp_in_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// This bfm drives signals with a _o suffix. These signals +// are driven onto signals within fuse_ctrl_lc_otp_in_if based on INITIATOR/RESPONDER and/or +// ARBITRATION/GRANT status. +// +// The output signal connections are as follows: +// signal_o -> bus.signal +// +// +// Interface functions and tasks used by UVM components: +// +// configure: +// This function gets configuration attributes from the +// UVM driver to set any required BFM configuration +// variables such as 'initiator_responder'. +// +// initiate_and_get_response: +// This task is used to perform signaling activity for initiating +// a protocol transfer. The task initiates the transfer, using +// input data from the initiator struct. Then the task captures +// response data, placing the data into the response struct. +// The response struct is returned to the driver class. +// +// respond_and_wait_for_next_transfer: +// This task is used to complete a current transfer as a responder +// and then wait for the initiator to start the next transfer. +// The task uses data in the responder struct to drive protocol +// signals to complete the transfer. The task then waits for +// the next transfer. Once the next transfer begins, data from +// the initiator is placed into the initiator struct and sent +// to the responder sequence for processing to determine +// what data to respond with. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_lc_otp_in_pkg_hdl::*; +`include "src/fuse_ctrl_lc_otp_in_macros.svh" + +interface fuse_ctrl_lc_otp_in_driver_bfm + (fuse_ctrl_lc_otp_in_if bus); + // The following pragma and additional ones in-lined further below are for running this BFM on Veloce + // pragma attribute fuse_ctrl_lc_otp_in_driver_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: ", ), + UVM_DEBUG) +end +`endif + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + tri clk_i_i; + tri rst_ni_i; + + // Signal list (all signals are capable of being inputs and outputs for the sake + // of supporting both INITIATOR and RESPONDER mode operation. Expectation is that + // directionality in the config file was from the point-of-view of the INITIATOR + + // INITIATOR mode input signals + + // INITIATOR mode output signals + tri [$bits(caliptra_otp_ctrl_pkg::lc_otp_vendor_test_req_t)-1:0] lc_otp_vendor_test_i_i; + reg [$bits(caliptra_otp_ctrl_pkg::lc_otp_vendor_test_req_t)-1:0] lc_otp_vendor_test_i_o = 'bz; + tri [$bits(caliptra_otp_ctrl_pkg::lc_otp_program_req_t)-1:0] lc_otp_program_i_i; + reg [$bits(caliptra_otp_ctrl_pkg::lc_otp_program_req_t)-1:0] lc_otp_program_i_o = 'bz; + tri [$bits(lc_ctrl_pkg::lc_tx_t)-1:0] lc_dft_en_i_i; + reg [$bits(lc_ctrl_pkg::lc_tx_t)-1:0] lc_dft_en_i_o = 'bz; + tri [$bits(lc_ctrl_pkg::lc_tx_t)-1:0] lc_escalate_en_i_i; + reg [$bits(lc_ctrl_pkg::lc_tx_t)-1:0] lc_escalate_en_i_o = 'bz; + tri [$bits(lc_ctrl_pkg::lc_tx_t)-1:0] lc_check_byp_en_i_i; + reg [$bits(lc_ctrl_pkg::lc_tx_t)-1:0] lc_check_byp_en_i_o = 'bz; + + // Bi-directional signals + + + assign clk_i_i = bus.clk_i; + assign rst_ni_i = bus.rst_ni; + + // These are signals marked as 'input' by the config file, but the signals will be + // driven by this BFM if put into RESPONDER mode (flipping all signal directions around) + + + // These are signals marked as 'output' by the config file, but the outputs will + // not be driven by this BFM unless placed in INITIATOR mode. + assign bus.lc_otp_vendor_test_i = (initiator_responder == INITIATOR) ? lc_otp_vendor_test_i_o : 'bz; + assign lc_otp_vendor_test_i_i = bus.lc_otp_vendor_test_i; + assign bus.lc_otp_program_i = (initiator_responder == INITIATOR) ? lc_otp_program_i_o : 'bz; + assign lc_otp_program_i_i = bus.lc_otp_program_i; + assign bus.lc_dft_en_i = (initiator_responder == INITIATOR) ? lc_dft_en_i_o : 'bz; + assign lc_dft_en_i_i = bus.lc_dft_en_i; + assign bus.lc_escalate_en_i = (initiator_responder == INITIATOR) ? lc_escalate_en_i_o : 'bz; + assign lc_escalate_en_i_i = bus.lc_escalate_en_i; + assign bus.lc_check_byp_en_i = (initiator_responder == INITIATOR) ? lc_check_byp_en_i_o : 'bz; + assign lc_check_byp_en_i_i = bus.lc_check_byp_en_i; + + // Proxy handle to UVM driver + fuse_ctrl_lc_otp_in_pkg::fuse_ctrl_lc_otp_in_driver proxy; + // pragma tbx oneway proxy.my_function_name_in_uvm_driver + + // **************************************************************************** + // **************************************************************************** + // Macros that define structs located in fuse_ctrl_lc_otp_in_macros.svh + // **************************************************************************** + // Struct for passing configuration data from fuse_ctrl_lc_otp_in_driver to this BFM + // **************************************************************************** + `fuse_ctrl_lc_otp_in_CONFIGURATION_STRUCT + // **************************************************************************** + // Structs for INITIATOR and RESPONDER data flow + //******************************************************************* + // Initiator macro used by fuse_ctrl_lc_otp_in_driver and fuse_ctrl_lc_otp_in_driver_bfm + // to communicate initiator driven data to fuse_ctrl_lc_otp_in_driver_bfm. + `fuse_ctrl_lc_otp_in_INITIATOR_STRUCT + fuse_ctrl_lc_otp_in_initiator_s initiator_struct; + // Responder macro used by fuse_ctrl_lc_otp_in_driver and fuse_ctrl_lc_otp_in_driver_bfm + // to communicate Responder driven data to fuse_ctrl_lc_otp_in_driver_bfm. + `fuse_ctrl_lc_otp_in_RESPONDER_STRUCT + fuse_ctrl_lc_otp_in_responder_s responder_struct; + + // **************************************************************************** +// pragma uvmf custom reset_condition_and_response begin + // Always block used to return signals to reset value upon assertion of reset + always @( negedge rst_ni_i ) + begin + // RESPONDER mode output signals + // INITIATOR mode output signals + lc_otp_vendor_test_i_o <= 'bz; + lc_otp_program_i_o <= 'bz; + lc_dft_en_i_o <= 'bz; + lc_escalate_en_i_o <= 'bz; + lc_check_byp_en_i_o <= 'bz; + // Bi-directional signals + + end +// pragma uvmf custom reset_condition_and_response end + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the driver BFM. It is called by the driver within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the driver BFM needs to be aware of the new configuration + // variables. + // + + function void configure(fuse_ctrl_lc_otp_in_configuration_s fuse_ctrl_lc_otp_in_configuration_arg); // pragma tbx xtf + initiator_responder = fuse_ctrl_lc_otp_in_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + +// pragma uvmf custom initiate_and_get_response begin +// **************************************************************************** +// UVMF_CHANGE_ME +// This task is used by an initator. The task first initiates a transfer then +// waits for the responder to complete the transfer. + task initiate_and_get_response( + // This argument passes transaction variables used by an initiator + // to perform the initial part of a protocol transfer. The values + // come from a sequence item created in a sequence. + input fuse_ctrl_lc_otp_in_initiator_s fuse_ctrl_lc_otp_in_initiator_struct, + // This argument is used to send data received from the responder + // back to the sequence item. The sequence item is returned to the sequence. + output fuse_ctrl_lc_otp_in_responder_s fuse_ctrl_lc_otp_in_responder_struct + );// pragma tbx xtf + // + // Members within the fuse_ctrl_lc_otp_in_initiator_struct: + // lc_ctrl_pkg::lc_tx_t lc_dft_en_i ; + // lc_ctrl_pkg::lc_tx_t lc_escalate_en_i ; + // lc_ctrl_pkg::lc_tx_t lc_check_byp_en_i ; + // Members within the fuse_ctrl_lc_otp_in_responder_struct: + // lc_ctrl_pkg::lc_tx_t lc_dft_en_i ; + // lc_ctrl_pkg::lc_tx_t lc_escalate_en_i ; + // lc_ctrl_pkg::lc_tx_t lc_check_byp_en_i ; + initiator_struct = fuse_ctrl_lc_otp_in_initiator_struct; + // + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clk_i_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available initiator input and inout signals listed. + // Initiator input signals + // Initiator inout signals + // How to assign a signal from an initiator struct member named xyz. + // All available initiator output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Initiator output signals + // lc_otp_vendor_test_i_o <= fuse_ctrl_lc_otp_in_initiator_struct.xyz; // [$bits(caliptra_otp_ctrl_pkg::lc_otp_vendor_test_req_t)-1:0] + // lc_otp_program_i_o <= fuse_ctrl_lc_otp_in_initiator_struct.xyz; // [$bits(caliptra_otp_ctrl_pkg::lc_otp_program_req_t)-1:0] + // lc_dft_en_i_o <= fuse_ctrl_lc_otp_in_initiator_struct.xyz; // [$bits(lc_ctrl_pkg::lc_tx_t)-1:0] + // lc_escalate_en_i_o <= fuse_ctrl_lc_otp_in_initiator_struct.xyz; // [$bits(lc_ctrl_pkg::lc_tx_t)-1:0] + // lc_check_byp_en_i_o <= fuse_ctrl_lc_otp_in_initiator_struct.xyz; // [$bits(lc_ctrl_pkg::lc_tx_t)-1:0] + // Initiator inout signals + // Initiate a transfer using the data received. + @(posedge clk_i_i); + @(posedge clk_i_i); + // Wait for the responder to complete the transfer then place the responder data into + // fuse_ctrl_lc_otp_in_responder_struct. + @(posedge clk_i_i); + @(posedge clk_i_i); + responder_struct = fuse_ctrl_lc_otp_in_responder_struct; + endtask +// pragma uvmf custom initiate_and_get_response end + +// pragma uvmf custom respond_and_wait_for_next_transfer begin +// **************************************************************************** +// The first_transfer variable is used to prevent completing a transfer in the +// first call to this task. For the first call to this task, there is not +// current transfer to complete. +bit first_transfer=1; + +// UVMF_CHANGE_ME +// This task is used by a responder. The task first completes the current +// transfer in progress then waits for the initiator to start the next transfer. + task respond_and_wait_for_next_transfer( + // This argument is used to send data received from the initiator + // back to the sequence item. The sequence determines how to respond. + output fuse_ctrl_lc_otp_in_initiator_s fuse_ctrl_lc_otp_in_initiator_struct, + // This argument passes transaction variables used by a responder + // to complete a protocol transfer. The values come from a sequence item. + input fuse_ctrl_lc_otp_in_responder_s fuse_ctrl_lc_otp_in_responder_struct + );// pragma tbx xtf + // Variables within the fuse_ctrl_lc_otp_in_initiator_struct: + // lc_ctrl_pkg::lc_tx_t lc_dft_en_i ; + // lc_ctrl_pkg::lc_tx_t lc_escalate_en_i ; + // lc_ctrl_pkg::lc_tx_t lc_check_byp_en_i ; + // Variables within the fuse_ctrl_lc_otp_in_responder_struct: + // lc_ctrl_pkg::lc_tx_t lc_dft_en_i ; + // lc_ctrl_pkg::lc_tx_t lc_escalate_en_i ; + // lc_ctrl_pkg::lc_tx_t lc_check_byp_en_i ; + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clk_i_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available responder input and inout signals listed. + // Responder input signals + // fuse_ctrl_lc_otp_in_responder_struct.xyz = lc_otp_vendor_test_i_i; // [$bits(caliptra_otp_ctrl_pkg::lc_otp_vendor_test_req_t)-1:0] + // fuse_ctrl_lc_otp_in_responder_struct.xyz = lc_otp_program_i_i; // [$bits(caliptra_otp_ctrl_pkg::lc_otp_program_req_t)-1:0] + // fuse_ctrl_lc_otp_in_responder_struct.xyz = lc_dft_en_i_i; // [$bits(lc_ctrl_pkg::lc_tx_t)-1:0] + // fuse_ctrl_lc_otp_in_responder_struct.xyz = lc_escalate_en_i_i; // [$bits(lc_ctrl_pkg::lc_tx_t)-1:0] + // fuse_ctrl_lc_otp_in_responder_struct.xyz = lc_check_byp_en_i_i; // [$bits(lc_ctrl_pkg::lc_tx_t)-1:0] + // Responder inout signals + // How to assign a signal, named xyz, from an initiator struct member. + // All available responder output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Responder output signals + // Responder inout signals + + @(posedge clk_i_i); + if (!first_transfer) begin + // Perform transfer response here. + // Reply using data recieved in the fuse_ctrl_lc_otp_in_responder_struct. + @(posedge clk_i_i); + // Reply using data recieved in the transaction handle. + @(posedge clk_i_i); + end + // Wait for next transfer then gather info from intiator about the transfer. + // Place the data into the fuse_ctrl_lc_otp_in_initiator_struct. + @(posedge clk_i_i); + @(posedge clk_i_i); + first_transfer = 0; + endtask +// pragma uvmf custom respond_and_wait_for_next_transfer end + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_if.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_if.sv new file mode 100644 index 0000000..7da88a3 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_if.sv @@ -0,0 +1,98 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface contains the fuse_ctrl_lc_otp_in interface signals. +// It is instantiated once per fuse_ctrl_lc_otp_in bus. Bus Functional Models, +// BFM's named fuse_ctrl_lc_otp_in_driver_bfm, are used to drive signals on the bus. +// BFM's named fuse_ctrl_lc_otp_in_monitor_bfm are used to monitor signals on the +// bus. This interface signal bundle is passed in the port list of +// the BFM in order to give the BFM access to the signals in this +// interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// This template can be used to connect a DUT to these signals +// +// .dut_signal_port(fuse_ctrl_lc_otp_in_bus.lc_otp_vendor_test_i), // Agent output +// .dut_signal_port(fuse_ctrl_lc_otp_in_bus.lc_otp_program_i), // Agent output +// .dut_signal_port(fuse_ctrl_lc_otp_in_bus.lc_dft_en_i), // Agent output +// .dut_signal_port(fuse_ctrl_lc_otp_in_bus.lc_escalate_en_i), // Agent output +// .dut_signal_port(fuse_ctrl_lc_otp_in_bus.lc_check_byp_en_i), // Agent output + +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_lc_otp_in_pkg_hdl::*; + +interface fuse_ctrl_lc_otp_in_if + + ( + input tri clk_i, + input tri rst_ni, + inout tri [$bits(caliptra_otp_ctrl_pkg::lc_otp_vendor_test_req_t)-1:0] lc_otp_vendor_test_i, + inout tri [$bits(caliptra_otp_ctrl_pkg::lc_otp_program_req_t)-1:0] lc_otp_program_i, + inout tri [$bits(lc_ctrl_pkg::lc_tx_t)-1:0] lc_dft_en_i, + inout tri [$bits(lc_ctrl_pkg::lc_tx_t)-1:0] lc_escalate_en_i, + inout tri [$bits(lc_ctrl_pkg::lc_tx_t)-1:0] lc_check_byp_en_i + ); + +modport monitor_port + ( + input clk_i, + input rst_ni, + input lc_otp_vendor_test_i, + input lc_otp_program_i, + input lc_dft_en_i, + input lc_escalate_en_i, + input lc_check_byp_en_i + ); + +modport initiator_port + ( + input clk_i, + input rst_ni, + output lc_otp_vendor_test_i, + output lc_otp_program_i, + output lc_dft_en_i, + output lc_escalate_en_i, + output lc_check_byp_en_i + ); + +modport responder_port + ( + input clk_i, + input rst_ni, + input lc_otp_vendor_test_i, + input lc_otp_program_i, + input lc_dft_en_i, + input lc_escalate_en_i, + input lc_check_byp_en_i + ); + + +// pragma uvmf custom interface_item_additional begin +// pragma uvmf custom interface_item_additional end + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_infact_coverage_strategy.csv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_infact_coverage_strategy.csv new file mode 100644 index 0000000..1c218e1 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_infact_coverage_strategy.csv @@ -0,0 +1,6 @@ +Global +auto_bin_max, 64 + +Name,Type,Include +rand_fields,coverpoint,=rand *.** + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_macros.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_macros.svh new file mode 100644 index 0000000..9ad130b --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_macros.svh @@ -0,0 +1,153 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains macros used with the fuse_ctrl_lc_otp_in package. +// These macros include packed struct definitions. These structs are +// used to pass data between classes, hvl, and BFM's, hdl. Use of +// structs are more efficient and simpler to modify. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_struct +// and from_struct methods defined in the macros below that are used in +// the fuse_ctrl_lc_otp_in_configuration class. +// + `define fuse_ctrl_lc_otp_in_CONFIGURATION_STRUCT \ +typedef struct packed { \ + uvmf_active_passive_t active_passive; \ + uvmf_initiator_responder_t initiator_responder; \ + } fuse_ctrl_lc_otp_in_configuration_s; + + `define fuse_ctrl_lc_otp_in_CONFIGURATION_TO_STRUCT_FUNCTION \ + virtual function fuse_ctrl_lc_otp_in_configuration_s to_struct();\ + fuse_ctrl_lc_otp_in_configuration_struct = \ + {\ + this.active_passive,\ + this.initiator_responder\ + };\ + return ( fuse_ctrl_lc_otp_in_configuration_struct );\ + endfunction + + `define fuse_ctrl_lc_otp_in_CONFIGURATION_FROM_STRUCT_FUNCTION \ + virtual function void from_struct(fuse_ctrl_lc_otp_in_configuration_s fuse_ctrl_lc_otp_in_configuration_struct);\ + {\ + this.active_passive,\ + this.initiator_responder \ + } = fuse_ctrl_lc_otp_in_configuration_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_monitor_struct +// and from_monitor_struct methods of the fuse_ctrl_lc_otp_in_transaction class. +// + `define fuse_ctrl_lc_otp_in_MONITOR_STRUCT typedef struct packed { \ + lc_ctrl_pkg::lc_tx_t lc_dft_en_i ; \ + lc_ctrl_pkg::lc_tx_t lc_escalate_en_i ; \ + lc_ctrl_pkg::lc_tx_t lc_check_byp_en_i ; \ + } fuse_ctrl_lc_otp_in_monitor_s; + + `define fuse_ctrl_lc_otp_in_TO_MONITOR_STRUCT_FUNCTION \ + virtual function fuse_ctrl_lc_otp_in_monitor_s to_monitor_struct();\ + fuse_ctrl_lc_otp_in_monitor_struct = \ + { \ + this.lc_dft_en_i , \ + this.lc_escalate_en_i , \ + this.lc_check_byp_en_i \ + };\ + return ( fuse_ctrl_lc_otp_in_monitor_struct);\ + endfunction\ + + `define fuse_ctrl_lc_otp_in_FROM_MONITOR_STRUCT_FUNCTION \ + virtual function void from_monitor_struct(fuse_ctrl_lc_otp_in_monitor_s fuse_ctrl_lc_otp_in_monitor_struct);\ + {\ + this.lc_dft_en_i , \ + this.lc_escalate_en_i , \ + this.lc_check_byp_en_i \ + } = fuse_ctrl_lc_otp_in_monitor_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_initiator_struct +// and from_initiator_struct methods of the fuse_ctrl_lc_otp_in_transaction class. +// Also update the comments in the driver BFM. +// + `define fuse_ctrl_lc_otp_in_INITIATOR_STRUCT typedef struct packed { \ + lc_ctrl_pkg::lc_tx_t lc_dft_en_i ; \ + lc_ctrl_pkg::lc_tx_t lc_escalate_en_i ; \ + lc_ctrl_pkg::lc_tx_t lc_check_byp_en_i ; \ + } fuse_ctrl_lc_otp_in_initiator_s; + + `define fuse_ctrl_lc_otp_in_TO_INITIATOR_STRUCT_FUNCTION \ + virtual function fuse_ctrl_lc_otp_in_initiator_s to_initiator_struct();\ + fuse_ctrl_lc_otp_in_initiator_struct = \ + {\ + this.lc_dft_en_i , \ + this.lc_escalate_en_i , \ + this.lc_check_byp_en_i \ + };\ + return ( fuse_ctrl_lc_otp_in_initiator_struct);\ + endfunction + + `define fuse_ctrl_lc_otp_in_FROM_INITIATOR_STRUCT_FUNCTION \ + virtual function void from_initiator_struct(fuse_ctrl_lc_otp_in_initiator_s fuse_ctrl_lc_otp_in_initiator_struct);\ + {\ + this.lc_dft_en_i , \ + this.lc_escalate_en_i , \ + this.lc_check_byp_en_i \ + } = fuse_ctrl_lc_otp_in_initiator_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_responder_struct +// and from_responder_struct methods of the fuse_ctrl_lc_otp_in_transaction class. +// Also update the comments in the driver BFM. +// + `define fuse_ctrl_lc_otp_in_RESPONDER_STRUCT typedef struct packed { \ + lc_ctrl_pkg::lc_tx_t lc_dft_en_i ; \ + lc_ctrl_pkg::lc_tx_t lc_escalate_en_i ; \ + lc_ctrl_pkg::lc_tx_t lc_check_byp_en_i ; \ + } fuse_ctrl_lc_otp_in_responder_s; + + `define fuse_ctrl_lc_otp_in_TO_RESPONDER_STRUCT_FUNCTION \ + virtual function fuse_ctrl_lc_otp_in_responder_s to_responder_struct();\ + fuse_ctrl_lc_otp_in_responder_struct = \ + {\ + this.lc_dft_en_i , \ + this.lc_escalate_en_i , \ + this.lc_check_byp_en_i \ + };\ + return ( fuse_ctrl_lc_otp_in_responder_struct);\ + endfunction + + `define fuse_ctrl_lc_otp_in_FROM_RESPONDER_STRUCT_FUNCTION \ + virtual function void from_responder_struct(fuse_ctrl_lc_otp_in_responder_s fuse_ctrl_lc_otp_in_responder_struct);\ + {\ + this.lc_dft_en_i , \ + this.lc_escalate_en_i , \ + this.lc_check_byp_en_i \ + } = fuse_ctrl_lc_otp_in_responder_struct;\ + endfunction +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_monitor.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_monitor.svh new file mode 100644 index 0000000..f046d7e --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_monitor.svh @@ -0,0 +1,101 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class receives fuse_ctrl_lc_otp_in transactions observed by the +// fuse_ctrl_lc_otp_in monitor BFM and broadcasts them through the analysis port +// on the agent. It accesses the monitor BFM through the monitor +// task. This UVM component captures transactions +// for viewing in the waveform viewer if the +// enable_transaction_viewing flag is set in the configuration. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_lc_otp_in_monitor extends uvmf_monitor_base #( + .CONFIG_T(fuse_ctrl_lc_otp_in_configuration ), + .BFM_BIND_T(virtual fuse_ctrl_lc_otp_in_monitor_bfm ), + .TRANS_T(fuse_ctrl_lc_otp_in_transaction )); + + `uvm_component_utils( fuse_ctrl_lc_otp_in_monitor ) + +// Structure used to pass data from monitor BFM to monitor class in agent. +// Use to_monitor_struct function to pack transaction variables into structure. +// Use from_monitor_struct function to unpack transaction variables from structure. +`fuse_ctrl_lc_otp_in_MONITOR_STRUCT + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the monitor BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// monitor BFM. This allows the monitor BFM to call the notify_transaction +// function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// *************************************************************************** + virtual task run_phase(uvm_phase phase); + // Start monitor BFM thread and don't call super.run() in order to + // override the default monitor proxy 'pull' behavior with the more + // emulation-friendly BFM 'push' approach using the notify_transaction + // function below + bfm.start_monitoring(); + endtask + +// ************************************************************************** + +// This function is called by the monitor BFM. It receives data observed by the +// monitor BFM. Data is passed using the fuse_ctrl_lc_otp_in_monitor_struct. + virtual function void notify_transaction(input fuse_ctrl_lc_otp_in_monitor_s fuse_ctrl_lc_otp_in_monitor_struct); + + + trans = new("trans"); + trans.from_monitor_struct(fuse_ctrl_lc_otp_in_monitor_struct); + trans.start_time = time_stamp; + trans.end_time = $time; + time_stamp = trans.end_time; + + analyze(trans); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_monitor_bfm.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_monitor_bfm.sv new file mode 100644 index 0000000..68a74b8 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_monitor_bfm.sv @@ -0,0 +1,202 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface performs the fuse_ctrl_lc_otp_in signal monitoring. +// It is accessed by the uvm fuse_ctrl_lc_otp_in monitor through a virtual +// interface handle in the fuse_ctrl_lc_otp_in configuration. It monitors the +// signals passed in through the port connection named bus of +// type fuse_ctrl_lc_otp_in_if. +// +// Input signals from the fuse_ctrl_lc_otp_in_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// Interface functions and tasks used by UVM components: +// monitor(inout TRANS_T txn); +// This task receives the transaction, txn, from the +// UVM monitor and then populates variables in txn +// from values observed on bus activity. This task +// blocks until an operation on the fuse_ctrl_lc_otp_in bus is complete. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_lc_otp_in_pkg_hdl::*; +`include "src/fuse_ctrl_lc_otp_in_macros.svh" + + +interface fuse_ctrl_lc_otp_in_monitor_bfm + ( fuse_ctrl_lc_otp_in_if bus ); + // The pragma below and additional ones in-lined further down are for running this BFM on Veloce + // pragma attribute fuse_ctrl_lc_otp_in_monitor_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: ", ), + UVM_DEBUG) +end +`endif + + + // Structure used to pass transaction data from monitor BFM to monitor class in agent. +`fuse_ctrl_lc_otp_in_MONITOR_STRUCT + fuse_ctrl_lc_otp_in_monitor_s fuse_ctrl_lc_otp_in_monitor_struct; + + // Structure used to pass configuration data from monitor class to monitor BFM. + `fuse_ctrl_lc_otp_in_CONFIGURATION_STRUCT + + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + tri clk_i_i; + tri rst_ni_i; + tri [$bits(caliptra_otp_ctrl_pkg::lc_otp_vendor_test_req_t)-1:0] lc_otp_vendor_test_i_i; + tri [$bits(caliptra_otp_ctrl_pkg::lc_otp_program_req_t)-1:0] lc_otp_program_i_i; + tri [$bits(lc_ctrl_pkg::lc_tx_t)-1:0] lc_dft_en_i_i; + tri [$bits(lc_ctrl_pkg::lc_tx_t)-1:0] lc_escalate_en_i_i; + tri [$bits(lc_ctrl_pkg::lc_tx_t)-1:0] lc_check_byp_en_i_i; + assign clk_i_i = bus.clk_i; + assign rst_ni_i = bus.rst_ni; + assign lc_otp_vendor_test_i_i = bus.lc_otp_vendor_test_i; + assign lc_otp_program_i_i = bus.lc_otp_program_i; + assign lc_dft_en_i_i = bus.lc_dft_en_i; + assign lc_escalate_en_i_i = bus.lc_escalate_en_i; + assign lc_check_byp_en_i_i = bus.lc_check_byp_en_i; + + // Proxy handle to UVM monitor + fuse_ctrl_lc_otp_in_pkg::fuse_ctrl_lc_otp_in_monitor proxy; + // pragma tbx oneway proxy.notify_transaction + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + task wait_for_reset();// pragma tbx xtf + @(posedge clk_i_i) ; + do_wait_for_reset(); + endtask + + // **************************************************************************** + task do_wait_for_reset(); + // pragma uvmf custom reset_condition begin + wait ( rst_ni_i === 1 ) ; + @(posedge clk_i_i) ; + // pragma uvmf custom reset_condition end + endtask + + //****************************************************************** + + task wait_for_num_clocks(input int unsigned count); // pragma tbx xtf + @(posedge clk_i_i); + + repeat (count-1) @(posedge clk_i_i); + endtask + + //****************************************************************** + event go; + function void start_monitoring();// pragma tbx xtf + -> go; + endfunction + + // **************************************************************************** + initial begin + @go; + forever begin + @(posedge clk_i_i); + do_monitor( fuse_ctrl_lc_otp_in_monitor_struct ); + + + proxy.notify_transaction( fuse_ctrl_lc_otp_in_monitor_struct ); + + end + end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the monitor BFM. It is called by the monitor within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the monitor BFM needs to be aware of the new configuration + // variables. + // + function void configure(fuse_ctrl_lc_otp_in_configuration_s fuse_ctrl_lc_otp_in_configuration_arg); // pragma tbx xtf + initiator_responder = fuse_ctrl_lc_otp_in_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + + + // **************************************************************************** + + task do_monitor(output fuse_ctrl_lc_otp_in_monitor_s fuse_ctrl_lc_otp_in_monitor_struct); + // + // Available struct members: + // // fuse_ctrl_lc_otp_in_monitor_struct.lc_dft_en_i + // // fuse_ctrl_lc_otp_in_monitor_struct.lc_escalate_en_i + // // fuse_ctrl_lc_otp_in_monitor_struct.lc_check_byp_en_i + // // + // Reference code; + // How to wait for signal value + // while (control_signal === 1'b1) @(posedge clk_i_i); + // + // How to assign a struct member, named xyz, from a signal. + // All available input signals listed. + // fuse_ctrl_lc_otp_in_monitor_struct.xyz = lc_otp_vendor_test_i_i; // [$bits(caliptra_otp_ctrl_pkg::lc_otp_vendor_test_req_t)-1:0] + // fuse_ctrl_lc_otp_in_monitor_struct.xyz = lc_otp_program_i_i; // [$bits(caliptra_otp_ctrl_pkg::lc_otp_program_req_t)-1:0] + // fuse_ctrl_lc_otp_in_monitor_struct.xyz = lc_dft_en_i_i; // [$bits(lc_ctrl_pkg::lc_tx_t)-1:0] + // fuse_ctrl_lc_otp_in_monitor_struct.xyz = lc_escalate_en_i_i; // [$bits(lc_ctrl_pkg::lc_tx_t)-1:0] + // fuse_ctrl_lc_otp_in_monitor_struct.xyz = lc_check_byp_en_i_i; // [$bits(lc_ctrl_pkg::lc_tx_t)-1:0] + // pragma uvmf custom do_monitor begin + // UVMF_CHANGE_ME : Implement protocol monitoring. The commented reference code + // below are examples of how to capture signal values and assign them to + // structure members. All available input signals are listed. The 'while' + // code example shows how to wait for a synchronous flow control signal. This + // task should return when a complete transfer has been observed. Once this task is + // exited with captured values, it is then called again to wait for and observe + // the next transfer. One clock cycle is consumed between calls to do_monitor. + @(posedge clk_i_i); + @(posedge clk_i_i); + @(posedge clk_i_i); + @(posedge clk_i_i); + // pragma uvmf custom do_monitor end + endtask + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_random_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_random_sequence.svh new file mode 100644 index 0000000..477393c --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_random_sequence.svh @@ -0,0 +1,67 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This sequences randomizes the fuse_ctrl_lc_otp_in transaction and sends it +// to the UVM driver. +// +// This sequence constructs and randomizes a fuse_ctrl_lc_otp_in_transaction. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_lc_otp_in_random_sequence + extends fuse_ctrl_lc_otp_in_sequence_base ; + + `uvm_object_utils( fuse_ctrl_lc_otp_in_random_sequence ) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //***************************************************************** + function new(string name = ""); + super.new(name); + endfunction: new + + // **************************************************************************** + // TASK : body() + // This task is automatically executed when this sequence is started using the + // start(sequencerHandle) task. + // + task body(); + + // Construct the transaction + req=fuse_ctrl_lc_otp_in_transaction::type_id::create("req"); + start_item(req); + // Randomize the transaction + if(!req.randomize()) `uvm_fatal("SEQ", "fuse_ctrl_lc_otp_in_random_sequence::body()-fuse_ctrl_lc_otp_in_transaction randomization failed") + // Send the transaction to the fuse_ctrl_lc_otp_in_driver_bfm via the sequencer and fuse_ctrl_lc_otp_in_driver. + finish_item(req); + `uvm_info("SEQ", {"Response:",req.convert2string()},UVM_MEDIUM) + + endtask + +endclass: fuse_ctrl_lc_otp_in_random_sequence + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_responder_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_responder_sequence.svh new file mode 100644 index 0000000..e414968 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_responder_sequence.svh @@ -0,0 +1,63 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class can be used to provide stimulus when an interface +// has been configured to run in a responder mode. It +// will never finish by default, always going back to the driver +// and driver BFM for the next transaction with which to respond. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_lc_otp_in_responder_sequence + extends fuse_ctrl_lc_otp_in_sequence_base ; + + `uvm_object_utils( fuse_ctrl_lc_otp_in_responder_sequence ) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "fuse_ctrl_lc_otp_in_responder_sequence"); + super.new(name); + endfunction + + task body(); + req=fuse_ctrl_lc_otp_in_transaction::type_id::create("req"); + forever begin + start_item(req); + finish_item(req); + // pragma uvmf custom body begin + // UVMF_CHANGE_ME : Do something here with the resulting req item. The + // finish_item() call above will block until the req transaction is ready + // to be handled by the responder sequence. + // If this was an item that required a response, the expectation is + // that the response should be populated within this transaction now. + `uvm_info("SEQ",$sformatf("Processed txn: %s",req.convert2string()),UVM_HIGH) + // pragma uvmf custom body end + end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_sequence_base.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_sequence_base.svh new file mode 100644 index 0000000..83a122c --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_sequence_base.svh @@ -0,0 +1,110 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the class used as the base class for all sequences +// for this interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_lc_otp_in_sequence_base extends uvmf_sequence_base #( + .REQ(fuse_ctrl_lc_otp_in_transaction ), + .RSP(fuse_ctrl_lc_otp_in_transaction )); + + `uvm_object_utils( fuse_ctrl_lc_otp_in_sequence_base ) + + // variables + typedef fuse_ctrl_lc_otp_in_transaction fuse_ctrl_lc_otp_in_transaction_req_t; + fuse_ctrl_lc_otp_in_transaction_req_t req; + typedef fuse_ctrl_lc_otp_in_transaction fuse_ctrl_lc_otp_in_transaction_rsp_t; + fuse_ctrl_lc_otp_in_transaction_rsp_t rsp; + + // Event for identifying when a response was received from the sequencer + event new_rsp; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // TASK : get_responses() + // This task recursively gets sequence item responses from the sequencer. + // + virtual task get_responses(); + fork + begin + // Block until new rsp available + get_response(rsp); + // New rsp received. Indicate to sequence using event. + ->new_rsp; + // Display the received response transaction + `uvm_info("SEQ", {"New response transaction:",rsp.convert2string()}, UVM_MEDIUM) + end + join_none + endtask + + // **************************************************************************** + // TASK : pre_body() + // This task is called automatically when start is called with call_pre_post set to 1 (default). + // By calling get_responses() within pre_body() any derived sequences are automatically + // processing response transactions. Only un-comment this call to get_responses() if you + // have configured the interface driver to utilize the response transaction path by setting + // the configuration variable "return_transaction_response" to 1. Otherwise it is possible + // to impact runtime performance and memory utilization. + // + virtual task pre_body(); + // pragma uvmf custom pre_body begin +// get_responses(); + // pragma uvmf custom pre_body end + endtask + + // **************************************************************************** + // TASK : body() + // This task is called automatically when start is called. This sequence sends + // a req sequence item to the sequencer identified as an argument in the call + // to start. + // + virtual task body(); + // pragma uvmf custom body begin + start_item(req); + finish_item(req); + // pragma uvmf custom body end + endtask + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name =""); + super.new( name ); + // pragma uvmf custom new begin + req = fuse_ctrl_lc_otp_in_transaction_req_t::type_id::create("req"); + rsp = fuse_ctrl_lc_otp_in_transaction_rsp_t::type_id::create("rsp"); + // pragma uvmf custom new end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_transaction.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_transaction.svh new file mode 100644 index 0000000..187b648 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_transaction.svh @@ -0,0 +1,201 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class defines the variables required for an fuse_ctrl_lc_otp_in +// transaction. Class variables to be displayed in waveform transaction +// viewing are added to the transaction viewing stream in the add_to_wave +// function. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_lc_otp_in_transaction extends uvmf_transaction_base; + + `uvm_object_utils( fuse_ctrl_lc_otp_in_transaction ) + + lc_ctrl_pkg::lc_tx_t lc_dft_en_i ; + lc_ctrl_pkg::lc_tx_t lc_escalate_en_i ; + lc_ctrl_pkg::lc_tx_t lc_check_byp_en_i ; + + //Constraints for the transaction variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //******************************************************************* + //******************************************************************* + // Macros that define structs and associated functions are + // located in fuse_ctrl_lc_otp_in_macros.svh + + //******************************************************************* + // Monitor macro used by fuse_ctrl_lc_otp_in_monitor and fuse_ctrl_lc_otp_in_monitor_bfm + // This struct is defined in fuse_ctrl_lc_otp_in_macros.svh + `fuse_ctrl_lc_otp_in_MONITOR_STRUCT + fuse_ctrl_lc_otp_in_monitor_s fuse_ctrl_lc_otp_in_monitor_struct; + //******************************************************************* + // FUNCTION: to_monitor_struct() + // This function packs transaction variables into a fuse_ctrl_lc_otp_in_monitor_s + // structure. The function returns the handle to the fuse_ctrl_lc_otp_in_monitor_struct. + // This function is defined in fuse_ctrl_lc_otp_in_macros.svh + `fuse_ctrl_lc_otp_in_TO_MONITOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_monitor_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_lc_otp_in_macros.svh + `fuse_ctrl_lc_otp_in_FROM_MONITOR_STRUCT_FUNCTION + + //******************************************************************* + // Initiator macro used by fuse_ctrl_lc_otp_in_driver and fuse_ctrl_lc_otp_in_driver_bfm + // to communicate initiator driven data to fuse_ctrl_lc_otp_in_driver_bfm. + // This struct is defined in fuse_ctrl_lc_otp_in_macros.svh + `fuse_ctrl_lc_otp_in_INITIATOR_STRUCT + fuse_ctrl_lc_otp_in_initiator_s fuse_ctrl_lc_otp_in_initiator_struct; + //******************************************************************* + // FUNCTION: to_initiator_struct() + // This function packs transaction variables into a fuse_ctrl_lc_otp_in_initiator_s + // structure. The function returns the handle to the fuse_ctrl_lc_otp_in_initiator_struct. + // This function is defined in fuse_ctrl_lc_otp_in_macros.svh + `fuse_ctrl_lc_otp_in_TO_INITIATOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_initiator_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_lc_otp_in_macros.svh + `fuse_ctrl_lc_otp_in_FROM_INITIATOR_STRUCT_FUNCTION + + //******************************************************************* + // Responder macro used by fuse_ctrl_lc_otp_in_driver and fuse_ctrl_lc_otp_in_driver_bfm + // to communicate Responder driven data to fuse_ctrl_lc_otp_in_driver_bfm. + // This struct is defined in fuse_ctrl_lc_otp_in_macros.svh + `fuse_ctrl_lc_otp_in_RESPONDER_STRUCT + fuse_ctrl_lc_otp_in_responder_s fuse_ctrl_lc_otp_in_responder_struct; + //******************************************************************* + // FUNCTION: to_responder_struct() + // This function packs transaction variables into a fuse_ctrl_lc_otp_in_responder_s + // structure. The function returns the handle to the fuse_ctrl_lc_otp_in_responder_struct. + // This function is defined in fuse_ctrl_lc_otp_in_macros.svh + `fuse_ctrl_lc_otp_in_TO_RESPONDER_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_responder_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_lc_otp_in_macros.svh + `fuse_ctrl_lc_otp_in_FROM_RESPONDER_STRUCT_FUNCTION + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + endfunction + + // **************************************************************************** + // FUNCTION: convert2string() + // This function converts all variables in this class to a single string for + // logfile reporting. + // + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + // UVMF_CHANGE_ME : Customize format if desired. + return $sformatf("lc_dft_en_i:0x%x lc_escalate_en_i:0x%x lc_check_byp_en_i:0x%x ",lc_dft_en_i,lc_escalate_en_i,lc_check_byp_en_i); + // pragma uvmf custom convert2string end + endfunction + + //******************************************************************* + // FUNCTION: do_print() + // This function is automatically called when the .print() function + // is called on this class. + // + virtual function void do_print(uvm_printer printer); + // pragma uvmf custom do_print begin + // UVMF_CHANGE_ME : Current contents of do_print allows for the use of UVM 1.1d, 1.2 or P1800.2. + // Update based on your own printing preference according to your preferred UVM version + $display(convert2string()); + // pragma uvmf custom do_print end + endfunction + + //******************************************************************* + // FUNCTION: do_compare() + // This function is automatically called when the .compare() function + // is called on this class. + // + virtual function bit do_compare (uvm_object rhs, uvm_comparer comparer); + fuse_ctrl_lc_otp_in_transaction RHS; + if (!$cast(RHS,rhs)) return 0; + // pragma uvmf custom do_compare begin + // UVMF_CHANGE_ME : Eliminate comparison of variables not to be used for compare + return (super.do_compare(rhs,comparer) + ); + // pragma uvmf custom do_compare end + endfunction + + //******************************************************************* + // FUNCTION: do_copy() + // This function is automatically called when the .copy() function + // is called on this class. + // + virtual function void do_copy (uvm_object rhs); + fuse_ctrl_lc_otp_in_transaction RHS; + assert($cast(RHS,rhs)); + // pragma uvmf custom do_copy begin + super.do_copy(rhs); + this.lc_dft_en_i = RHS.lc_dft_en_i; + this.lc_escalate_en_i = RHS.lc_escalate_en_i; + this.lc_check_byp_en_i = RHS.lc_check_byp_en_i; + // pragma uvmf custom do_copy end + endfunction + + // **************************************************************************** + // FUNCTION: add_to_wave() + // This function is used to display variables in this class in the waveform + // viewer. The start_time and end_time variables must be set before this + // function is called. If the start_time and end_time variables are not set + // the transaction will be hidden at 0ns on the waveform display. + // + virtual function void add_to_wave(int transaction_viewing_stream_h); + `ifdef QUESTA + if (transaction_view_h == 0) begin + transaction_view_h = $begin_transaction(transaction_viewing_stream_h,"fuse_ctrl_lc_otp_in_transaction",start_time); + end + super.add_to_wave(transaction_view_h); + // pragma uvmf custom add_to_wave begin + // UVMF_CHANGE_ME : Color can be applied to transaction entries based on content, example below + // case() + // 1 : $add_color(transaction_view_h,"red"); + // default : $add_color(transaction_view_h,"grey"); + // endcase + // UVMF_CHANGE_ME : Eliminate transaction variables not wanted in transaction viewing in the waveform viewer + $add_attribute(transaction_view_h,lc_dft_en_i,"lc_dft_en_i"); + $add_attribute(transaction_view_h,lc_escalate_en_i,"lc_escalate_en_i"); + $add_attribute(transaction_view_h,lc_check_byp_en_i,"lc_check_byp_en_i"); + // pragma uvmf custom add_to_wave end + $end_transaction(transaction_view_h,end_time); + $free_transaction(transaction_view_h); + `endif // QUESTA + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_transaction_coverage.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_transaction_coverage.svh new file mode 100644 index 0000000..e5fa783 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_transaction_coverage.svh @@ -0,0 +1,86 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class records fuse_ctrl_lc_otp_in transaction information using +// a covergroup named fuse_ctrl_lc_otp_in_transaction_cg. An instance of this +// coverage component is instantiated in the uvmf_parameterized_agent +// if the has_coverage flag is set. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_lc_otp_in_transaction_coverage extends uvm_subscriber #(.T(fuse_ctrl_lc_otp_in_transaction )); + + `uvm_component_utils( fuse_ctrl_lc_otp_in_transaction_coverage ) + + T coverage_trans; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + covergroup fuse_ctrl_lc_otp_in_transaction_cg; + // pragma uvmf custom covergroup begin + // UVMF_CHANGE_ME : Add coverage bins, crosses, exclusions, etc. according to coverage needs. + option.auto_bin_max=1024; + option.per_instance=1; + lc_dft_en_i: coverpoint coverage_trans.lc_dft_en_i; + lc_escalate_en_i: coverpoint coverage_trans.lc_escalate_en_i; + lc_check_byp_en_i: coverpoint coverage_trans.lc_check_byp_en_i; + // pragma uvmf custom covergroup end + endgroup + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new(string name="", uvm_component parent=null); + super.new(name,parent); + fuse_ctrl_lc_otp_in_transaction_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that transaction variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + endfunction + + // **************************************************************************** + // FUNCTION : build_phase() + // This function is the standard UVM build_phase. + // + function void build_phase(uvm_phase phase); + fuse_ctrl_lc_otp_in_transaction_cg.set_inst_name($sformatf("fuse_ctrl_lc_otp_in_transaction_cg_%s",get_full_name())); + endfunction + + // **************************************************************************** + // FUNCTION: write (T t) + // This function is automatically executed when a transaction arrives on the + // analysis_export. It copies values from the variables in the transaction + // to local variables used to collect functional coverage. + // + virtual function void write (T t); + `uvm_info("COV","Received transaction",UVM_HIGH); + coverage_trans = t; + fuse_ctrl_lc_otp_in_transaction_cg.sample(); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_typedefs.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_typedefs.svh new file mode 100644 index 0000000..f2a7bdb --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_typedefs.svh @@ -0,0 +1,34 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the host server when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_typedefs_hdl.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_typedefs_hdl.svh new file mode 100644 index 0000000..0d58518 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_typedefs_hdl.svh @@ -0,0 +1,35 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the emulator when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/yaml/fuse_ctrl_lc_otp_in_interface.yaml b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/yaml/fuse_ctrl_lc_otp_in_interface.yaml new file mode 100644 index 0000000..a380327 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/yaml/fuse_ctrl_lc_otp_in_interface.yaml @@ -0,0 +1,57 @@ +uvmf: + interfaces: + fuse_ctrl_lc_otp_in: + clock: clk_i + config_constraints: [] + config_vars: [] + existing_library_component: 'True' + gen_inbound_streaming_driver: 'False' + hdl_pkg_parameters: [] + hdl_typedefs: [] + hvl_pkg_parameters: [] + hvl_typedefs: [] + parameters: [] + ports: + - dir: output + name: lc_otp_vendor_test_i + reset_value: '''bz' + width: '[''$bits(caliptra_otp_ctrl_pkg::lc_otp_vendor_test_req_t)'']' + - dir: output + name: lc_otp_program_i + reset_value: '''bz' + width: '[''$bits(caliptra_otp_ctrl_pkg::lc_otp_program_req_t)'']' + - dir: output + name: lc_dft_en_i + reset_value: '''bz' + width: '[''$bits(lc_ctrl_pkg::lc_tx_t)'']' + - dir: output + name: lc_escalate_en_i + reset_value: '''bz' + width: '[''$bits(lc_ctrl_pkg::lc_tx_t)'']' + - dir: output + name: lc_check_byp_en_i + reset_value: '''bz' + width: '[''$bits(lc_ctrl_pkg::lc_tx_t)'']' + reset: rst_ni + reset_assertion_level: 'False' + transaction_constraints: [] + transaction_vars: + - comment: '' + iscompare: 'False' + isrand: 'False' + name: lc_dft_en_i + type: lc_ctrl_pkg::lc_tx_t + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: lc_escalate_en_i + type: lc_ctrl_pkg::lc_tx_t + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: lc_check_byp_en_i + type: lc_ctrl_pkg::lc_tx_t + unpacked_dimension: '' + use_dpi_link: 'False' diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/.project b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/.project new file mode 100644 index 0000000..42717ee --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/.project @@ -0,0 +1,30 @@ + + + fuse_ctrl_lc_otp_out_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/.svproject b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/.svproject new file mode 100644 index 0000000..fe0ca64 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/Makefile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/Makefile new file mode 100644 index 0000000..f975b19 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/Makefile @@ -0,0 +1,66 @@ +# fuse_ctrl_lc_otp_out interface packages source +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +fuse_ctrl_lc_otp_out_PKG = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_lc_otp_out_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_filelist_hvl.f + +fuse_ctrl_lc_otp_out_PKG_HDL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_lc_otp_out_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_filelist_hdl.f + +fuse_ctrl_lc_otp_out_PKG_XRTL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_lc_otp_out_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_filelist_xrtl.f + +COMP_fuse_ctrl_lc_otp_out_PKG_TGT_0 = q_comp_fuse_ctrl_lc_otp_out_pkg +COMP_fuse_ctrl_lc_otp_out_PKG_TGT_1 = v_comp_fuse_ctrl_lc_otp_out_pkg +COMP_fuse_ctrl_lc_otp_out_PKG_TGT = $(COMP_fuse_ctrl_lc_otp_out_PKG_TGT_$(USE_VELOCE)) + +comp_fuse_ctrl_lc_otp_out_pkg: $(COMP_fuse_ctrl_lc_otp_out_PKG_TGT) + +q_comp_fuse_ctrl_lc_otp_out_pkg: + $(HDL_COMP_CMD) $(fuse_ctrl_lc_otp_out_PKG_HDL) + $(HVL_COMP_CMD) $(fuse_ctrl_lc_otp_out_PKG) + $(HDL_COMP_CMD) $(fuse_ctrl_lc_otp_out_PKG_XRTL) + +v_comp_fuse_ctrl_lc_otp_out_pkg: + $(HVL_COMP_CMD) $(fuse_ctrl_lc_otp_out_PKG_HDL) + $(HVL_COMP_CMD) $(fuse_ctrl_lc_otp_out_PKG) + $(VELANALYZE_CMD) $(fuse_ctrl_lc_otp_out_PKG_HDL) + $(VELANALYZE_HVL_CMD) $(fuse_ctrl_lc_otp_out_PKG) + $(HDL_COMP_CMD) $(fuse_ctrl_lc_otp_out_PKG_XRTL) + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export fuse_ctrl_lc_otp_out_IF_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_lc_otp_out_pkg/dpi + +C_FILE_COMPILE_LIST_fuse_ctrl_lc_otp_out_pkg = \ + +O_FILE_COMPILE_LIST_fuse_ctrl_lc_otp_out_pkg = $(notdir $(C_FILE_COMPILE_LIST_fuse_ctrl_lc_otp_out_pkg:.c=.o)) + +GCC_COMP_ARGS_fuse_ctrl_lc_otp_out_pkg += -I$(fuse_ctrl_lc_otp_out_IF_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_fuse_ctrl_lc_otp_out_pkg += $(fuse_ctrl_lc_otp_out_IF_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_fuse_ctrl_lc_otp_out_pkg += \ + \ + -o .so + +comp_fuse_ctrl_lc_otp_out_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Interface C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_fuse_ctrl_lc_otp_out_pkg) $(C_FILE_COMPILE_LIST_fuse_ctrl_lc_otp_out_pkg) + @echo "--------------------------------" + @echo "Linking Interface C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_fuse_ctrl_lc_otp_out_pkg) $(O_FILE_COMPILE_LIST_fuse_ctrl_lc_otp_out_pkg) + @echo "--------------------------------" + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/compile.do b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/compile.do new file mode 100644 index 0000000..8073231 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/compile.do @@ -0,0 +1,14 @@ +# Tcl do file for compile of fuse_ctrl_lc_otp_out interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_lc_otp_out_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_filelist_hdl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_lc_otp_out_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_filelist_hvl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_lc_otp_out_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_filelist_xrtl.f \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out.compile new file mode 100644 index 0000000..f8a8ac4 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out.compile @@ -0,0 +1,3 @@ +needs: + - fuse_ctrl_lc_otp_out_hvl.compile + - fuse_ctrl_lc_otp_out_hdl.compile diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_bfm.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_bfm.vinfo new file mode 100644 index 0000000..0c1d35f --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_bfm.vinfo @@ -0,0 +1,6 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use fuse_ctrl_lc_otp_out_pkg_hdl.vinfo ++incdir+@vinfodir +src/fuse_ctrl_lc_otp_out_if.sv +src/fuse_ctrl_lc_otp_out_driver_bfm.sv +src/fuse_ctrl_lc_otp_out_monitor_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_common.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_common.compile new file mode 100644 index 0000000..42616d5 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_common.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +incdir: + - . + - ${uvm_path}/src +src: + - fuse_ctrl_lc_otp_out_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_filelist_hdl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_filelist_hdl.f new file mode 100644 index 0000000..dd3eb8a --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_filelist_hdl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_filelist_hvl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_filelist_hvl.f new file mode 100644 index 0000000..b0a13c6 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_filelist_hvl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_pkg.sv \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_filelist_xrtl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_filelist_xrtl.f new file mode 100644 index 0000000..48f620e --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_filelist_xrtl.f @@ -0,0 +1,3 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_if.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_monitor_bfm.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_driver_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_hdl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_hdl.compile new file mode 100644 index 0000000..2ce74cc --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_hdl.compile @@ -0,0 +1,9 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ./fuse_ctrl_lc_otp_out_common.compile +incdir: + - . +src: + - src/fuse_ctrl_lc_otp_out_if.sv + - src/fuse_ctrl_lc_otp_out_monitor_bfm.sv + - src/fuse_ctrl_lc_otp_out_driver_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_hvl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_hvl.compile new file mode 100644 index 0000000..d6a5b88 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_hvl.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ./fuse_ctrl_lc_otp_out_common.compile +incdir: + - . +src: + - fuse_ctrl_lc_otp_out_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_pkg.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_pkg.sv new file mode 100644 index 0000000..c18cea8 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_pkg.sv @@ -0,0 +1,91 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - + +// - +// - +// - + +// - +// - +// - + +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_lc_otp_out_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg_hdl::*; + import uvmf_base_pkg::*; + import fuse_ctrl_lc_otp_out_pkg_hdl::*; + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + `include "src/fuse_ctrl_lc_otp_out_macros.svh" + + export fuse_ctrl_lc_otp_out_pkg_hdl::*; + + + + // Parameters defined as HVL parameters + + `include "src/fuse_ctrl_lc_otp_out_typedefs.svh" + `include "src/fuse_ctrl_lc_otp_out_transaction.svh" + + `include "src/fuse_ctrl_lc_otp_out_configuration.svh" + `include "src/fuse_ctrl_lc_otp_out_driver.svh" + `include "src/fuse_ctrl_lc_otp_out_monitor.svh" + + `include "src/fuse_ctrl_lc_otp_out_transaction_coverage.svh" + `include "src/fuse_ctrl_lc_otp_out_sequence_base.svh" + `include "src/fuse_ctrl_lc_otp_out_random_sequence.svh" + + `include "src/fuse_ctrl_lc_otp_out_responder_sequence.svh" + `include "src/fuse_ctrl_lc_otp_out2reg_adapter.svh" + + `include "src/fuse_ctrl_lc_otp_out_agent.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new interface sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the interface package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_pkg.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_pkg.vinfo new file mode 100644 index 0000000..7a4f8b1 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_pkg.vinfo @@ -0,0 +1,4 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use fuse_ctrl_lc_otp_out_pkg_hdl.vinfo ++incdir+@vinfodir +fuse_ctrl_lc_otp_out_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_pkg_hdl.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_pkg_hdl.sv new file mode 100644 index 0000000..8987535 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_pkg_hdl.sv @@ -0,0 +1,52 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that needs to be compiled and synthesized +// for running on Veloce. +// +// CONTAINS: +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_lc_otp_out_pkg_hdl; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HDL parameters + + `include "src/fuse_ctrl_lc_otp_out_typedefs_hdl.svh" + `include "src/fuse_ctrl_lc_otp_out_macros.svh" + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_pkg_hdl.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_pkg_hdl.vinfo new file mode 100644 index 0000000..f662f8c --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_pkg_hdl.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +fuse_ctrl_lc_otp_out_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_pkg_sve.F b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_pkg_sve.F new file mode 100644 index 0000000..0483ef5 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_pkg_sve.F @@ -0,0 +1,10 @@ +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + ++incdir+. +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_filelist_hdl.f +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_filelist_hvl.f diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out2reg_adapter.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out2reg_adapter.svh new file mode 100644 index 0000000..bd1fa55 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out2reg_adapter.svh @@ -0,0 +1,112 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the UVM register adapter for the fuse_ctrl_lc_otp_out interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_lc_otp_out2reg_adapter extends uvm_reg_adapter; + + `uvm_object_utils( fuse_ctrl_lc_otp_out2reg_adapter ) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //-------------------------------------------------------------------- + // new + //-------------------------------------------------------------------- + function new (string name = "fuse_ctrl_lc_otp_out2reg_adapter" ); + super.new(name); + // pragma uvmf custom new begin + // UVMF_CHANGE_ME : Configure the adapter regarding byte enables and provides response. + + // Does the protocol the Agent is modeling support byte enables? + // 0 = NO + // 1 = YES + supports_byte_enable = 0; + + // Does the Agent's Driver provide separate response sequence items? + // i.e. Does the driver call seq_item_port.put() + // and do the sequences call get_response()? + // 0 = NO + // 1 = YES + provides_responses = 0; + // pragma uvmf custom new end + + endfunction: new + + //-------------------------------------------------------------------- + // reg2bus + //-------------------------------------------------------------------- + virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw); + + fuse_ctrl_lc_otp_out_transaction trans_h = fuse_ctrl_lc_otp_out_transaction ::type_id::create("trans_h"); + + // pragma uvmf custom reg2bus begin + // UVMF_CHANGE_ME : Fill in the reg2bus adapter mapping registe fields to protocol fields. + + //Adapt the following for your sequence item type + // trans_h.op = (rw.kind == UVM_READ) ? WB_READ : WB_WRITE; + //Copy over address + // trans_h.addr = rw.addr; + //Copy over write data + // trans_h.data = rw.data; + + // pragma uvmf custom reg2bus end + + // Return the adapted transaction + return trans_h; + + endfunction: reg2bus + + //-------------------------------------------------------------------- + // bus2reg + //-------------------------------------------------------------------- + virtual function void bus2reg(uvm_sequence_item bus_item, + ref uvm_reg_bus_op rw); + fuse_ctrl_lc_otp_out_transaction trans_h; + if (!$cast(trans_h, bus_item)) begin + `uvm_fatal("ADAPT","Provided bus_item is not of the correct type") + return; + end + // pragma uvmf custom bus2reg begin + // UVMF_CHANGE_ME : Fill in the bus2reg adapter mapping protocol fields to register fields. + //Adapt the following for your sequence item type + //Copy over instruction type + // rw.kind = (trans_h.op == WB_WRITE) ? UVM_WRITE : UVM_READ; + //Copy over address + // rw.addr = trans_h.addr; + //Copy over read data + // rw.data = trans_h.data; + //Check for errors on the bus and return UVM_NOT_OK if there is an error + // rw.status = UVM_IS_OK; + // pragma uvmf custom bus2reg end + + endfunction: bus2reg + +endclass : fuse_ctrl_lc_otp_out2reg_adapter + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_agent.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_agent.svh new file mode 100644 index 0000000..2b6207d --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_agent.svh @@ -0,0 +1,67 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: Protocol specific agent class definition +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_lc_otp_out_agent extends uvmf_parameterized_agent #( + .CONFIG_T(fuse_ctrl_lc_otp_out_configuration ), + .DRIVER_T(fuse_ctrl_lc_otp_out_driver ), + .MONITOR_T(fuse_ctrl_lc_otp_out_monitor ), + .COVERAGE_T(fuse_ctrl_lc_otp_out_transaction_coverage ), + .TRANS_T(fuse_ctrl_lc_otp_out_transaction ) + ); + + `uvm_component_utils( fuse_ctrl_lc_otp_out_agent ) + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** + // FUNCTION: build_phase + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + if (configuration.active_passive == ACTIVE) begin + // Place sequencer handle into configuration object + // so that it may be retrieved from configuration + // rather than using uvm_config_db + configuration.sequencer = this.sequencer; + end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_configuration.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_configuration.svh new file mode 100644 index 0000000..b7ccdac --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_configuration.svh @@ -0,0 +1,193 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class contains all variables and functions used +// to configure the fuse_ctrl_lc_otp_out agent and its bfm's. It gets the +// bfm's from the uvm_config_db for use by the agent. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_lc_otp_out_configuration extends uvmf_parameterized_agent_configuration_base #( + .DRIVER_BFM_BIND_T(virtual fuse_ctrl_lc_otp_out_driver_bfm ), + .MONITOR_BFM_BIND_T( virtual fuse_ctrl_lc_otp_out_monitor_bfm )); + + `uvm_object_utils( fuse_ctrl_lc_otp_out_configuration ) + + + // Sequencer handle populated by agent + uvm_sequencer #(fuse_ctrl_lc_otp_out_transaction ) sequencer; + + //Constraints for the configuration variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + covergroup fuse_ctrl_lc_otp_out_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + // pragma uvmf custom covergroup end + endgroup + + //******************************************************************* + //******************************************************************* + // Structure used to pass configuration variables to monitor and driver BFM's. + // Use to_struct function to pack variables into structure. + // Use from_struct function to unpack variables from structure. + // This structure is defined in fuse_ctrl_lc_otp_out_macros.svh + `fuse_ctrl_lc_otp_out_CONFIGURATION_STRUCT + fuse_ctrl_lc_otp_out_configuration_s fuse_ctrl_lc_otp_out_configuration_struct; + //******************************************************************* + // FUNCTION: to_struct() + // This function packs variables into a fuse_ctrl_lc_otp_out_configuration_s + // structure. The function returns the handle to the fuse_ctrl_lc_otp_out_configuration_struct. + // This function is defined in fuse_ctrl_lc_otp_out_macros.svh + `fuse_ctrl_lc_otp_out_CONFIGURATION_TO_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_struct() + // This function unpacks the struct provided as an argument into + // variables of this class. + // This function is defined in fuse_ctrl_lc_otp_out_macros.svh + `fuse_ctrl_lc_otp_out_CONFIGURATION_FROM_STRUCT_FUNCTION + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + // Construct the covergroup for this configuration class + fuse_ctrl_lc_otp_out_configuration_cg = new; + endfunction + + // **************************************************************************** + // FUNCTION: post_randomize() + // This function is automatically called after the randomize() function + // is executed. + // + function void post_randomize(); + super.post_randomize(); + fuse_ctrl_lc_otp_out_configuration_cg.sample(); + endfunction + + // **************************************************************************** + // FUNCTION: initialize + // This function causes the configuration to retrieve + // its virtual interface handle from the uvm_config_db. + // This function also makes itself available to its + // agent through the uvm_config_db. + // + // ARGUMENTS: + // uvmf_active_passive_t activity: + // This argument identifies the simulation level + // as either BLOCK, CHIP, SIMULATION, etc. + // + // AGENT_PATH: + // This argument identifies the path to this + // configurations agent. This configuration + // makes itself available to the agent specified + // by agent_path by placing itself into the + // uvm_config_db. + // + // INTERFACE_NAME: + // This argument identifies the string name of + // this configurations BFM's. This string + // name is used to retrieve the driver and + // monitor BFM from the uvm_config_db. + // + virtual function void initialize(uvmf_active_passive_t activity, + string agent_path, + string interface_name); + + super.initialize( activity, agent_path, interface_name); + // The covergroup is given the same name as the interface + fuse_ctrl_lc_otp_out_configuration_cg.set_inst_name(interface_name); + + // This configuration places itself into the uvm_config_db for the agent, identified by the agent_path variable, to retrieve. + uvm_config_db #( fuse_ctrl_lc_otp_out_configuration + )::set( null ,agent_path,UVMF_AGENT_CONFIG, this ); + + // This configuration also places itself in the config db using the same identifier used by the interface. This allows users to access + // configuration variables and the interface through the bfm api class rather than directly accessing the BFM. This is useful for + // accessingthe BFM when using Veloce + uvm_config_db #( fuse_ctrl_lc_otp_out_configuration + )::set( null ,UVMF_CONFIGURATIONS, interface_name, this ); + + fuse_ctrl_lc_otp_out_configuration_cg.set_inst_name($sformatf("fuse_ctrl_lc_otp_out_configuration_cg_%s",get_full_name())); + +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. + `uvm_info("CFG", + $psprintf("The agent at '%s' is using interface named %s has the following parameters: ", agent_path, interface_name, ), + UVM_DEBUG) + + // pragma uvmf custom initialize begin + // This controls whether or not the agent returns a transaction handle in the driver when calling + // item_done() back into the sequencer or not. If set to 1, a transaction is sent back which means + // the sequence on the other end must use the get_response() part of the driver/sequence API. If + // this doesn't occur, there will eventually be response_queue overflow errors during the test. + return_transaction_response = 1'b0; + + // pragma uvmf custom initialize end + + endfunction + + // **************************************************************************** + // TASK: wait_for_reset + // *[Required]* Blocks until reset is released. The wait_for_reset operation is performed + // by a task in the monitor bfm. + virtual task wait_for_reset(); + monitor_bfm.wait_for_reset(); + endtask + + // **************************************************************************** + // TASK: wait_for_num_clocks + // *[Required]* Blocks until specified number of clocks have elapsed. The wait_for_num_clocks + // operation is performed by a task in the monitor bfm. + virtual task wait_for_num_clocks(int clocks); + monitor_bfm.wait_for_num_clocks(clocks); + endtask + + // **************************************************************************** + // FUNCTION : convert2string() + // This function is used to convert variables in this class into a string for log messaging. + // + virtual function string convert2string (); + // pragma uvmf custom convert2string begin + return $sformatf(""); + // pragma uvmf custom convert2string end + endfunction + + // **************************************************************************** + // FUNCTION: get_sequencer + function uvm_sequencer #(fuse_ctrl_lc_otp_out_transaction) get_sequencer(); + return sequencer; + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_driver.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_driver.svh new file mode 100644 index 0000000..d25471c --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_driver.svh @@ -0,0 +1,105 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class passes transactions between the sequencer +// and the BFM driver interface. It accesses the driver BFM +// through the bfm handle. This driver +// passes transactions to the driver BFM through the access +// task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_lc_otp_out_driver extends uvmf_driver_base #( + .CONFIG_T(fuse_ctrl_lc_otp_out_configuration ), + .BFM_BIND_T(virtual fuse_ctrl_lc_otp_out_driver_bfm ), + .REQ(fuse_ctrl_lc_otp_out_transaction ), + .RSP(fuse_ctrl_lc_otp_out_transaction )); + + `uvm_component_utils( fuse_ctrl_lc_otp_out_driver ) +//******************************************************************* +// Macros that define structs located in fuse_ctrl_lc_otp_out_macros.svh +//******************************************************************* +// Initiator macro used by fuse_ctrl_lc_otp_out_driver and fuse_ctrl_lc_otp_out_driver_bfm +// to communicate initiator driven data to fuse_ctrl_lc_otp_out_driver_bfm. +`fuse_ctrl_lc_otp_out_INITIATOR_STRUCT + fuse_ctrl_lc_otp_out_initiator_s fuse_ctrl_lc_otp_out_initiator_struct; +//******************************************************************* +// Responder macro used by fuse_ctrl_lc_otp_out_driver and fuse_ctrl_lc_otp_out_driver_bfm +// to communicate Responder driven data to fuse_ctrl_lc_otp_out_driver_bfm. +`fuse_ctrl_lc_otp_out_RESPONDER_STRUCT + fuse_ctrl_lc_otp_out_responder_s fuse_ctrl_lc_otp_out_responder_struct; + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent=null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the driver BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// driver BFM. This allows the driver BFM to call tasks and function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// **************************************************************************** +// This task is called by the run_phase in uvmf_driver_base. + virtual task access( inout REQ txn ); +// pragma uvmf custom access begin + if (configuration.initiator_responder==RESPONDER) begin + // Complete current transfer and wait for next transfer + bfm.respond_and_wait_for_next_transfer( + fuse_ctrl_lc_otp_out_initiator_struct, + txn.to_responder_struct() + ); + // Unpack information about initiated transfer received by this responder + txn.from_initiator_struct(fuse_ctrl_lc_otp_out_initiator_struct); + end else begin + // Initiate a transfer and get response + bfm.initiate_and_get_response( + txn.to_initiator_struct(), + fuse_ctrl_lc_otp_out_responder_struct + ); + // Unpack transfer response information received by this initiator + txn.from_responder_struct(fuse_ctrl_lc_otp_out_responder_struct); + end +// pragma uvmf custom access end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_driver_bfm.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_driver_bfm.sv new file mode 100644 index 0000000..bc51e85 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_driver_bfm.sv @@ -0,0 +1,299 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This interface performs the fuse_ctrl_lc_otp_out signal driving. It is +// accessed by the uvm fuse_ctrl_lc_otp_out driver through a virtual interface +// handle in the fuse_ctrl_lc_otp_out configuration. It drives the singals passed +// in through the port connection named bus of type fuse_ctrl_lc_otp_out_if. +// +// Input signals from the fuse_ctrl_lc_otp_out_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// This bfm drives signals with a _o suffix. These signals +// are driven onto signals within fuse_ctrl_lc_otp_out_if based on INITIATOR/RESPONDER and/or +// ARBITRATION/GRANT status. +// +// The output signal connections are as follows: +// signal_o -> bus.signal +// +// +// Interface functions and tasks used by UVM components: +// +// configure: +// This function gets configuration attributes from the +// UVM driver to set any required BFM configuration +// variables such as 'initiator_responder'. +// +// initiate_and_get_response: +// This task is used to perform signaling activity for initiating +// a protocol transfer. The task initiates the transfer, using +// input data from the initiator struct. Then the task captures +// response data, placing the data into the response struct. +// The response struct is returned to the driver class. +// +// respond_and_wait_for_next_transfer: +// This task is used to complete a current transfer as a responder +// and then wait for the initiator to start the next transfer. +// The task uses data in the responder struct to drive protocol +// signals to complete the transfer. The task then waits for +// the next transfer. Once the next transfer begins, data from +// the initiator is placed into the initiator struct and sent +// to the responder sequence for processing to determine +// what data to respond with. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_lc_otp_out_pkg_hdl::*; +`include "src/fuse_ctrl_lc_otp_out_macros.svh" + +interface fuse_ctrl_lc_otp_out_driver_bfm + (fuse_ctrl_lc_otp_out_if bus); + // The following pragma and additional ones in-lined further below are for running this BFM on Veloce + // pragma attribute fuse_ctrl_lc_otp_out_driver_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: ", ), + UVM_DEBUG) +end +`endif + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + tri clk_i_i; + tri rst_ni_i; + + // Signal list (all signals are capable of being inputs and outputs for the sake + // of supporting both INITIATOR and RESPONDER mode operation. Expectation is that + // directionality in the config file was from the point-of-view of the INITIATOR + + // INITIATOR mode input signals + tri [$bits(caliptra_otp_ctrl_pkg::lc_otp_vendor_test_rsp_t)-1:0] lc_otp_vendor_test_o_i; + reg [$bits(caliptra_otp_ctrl_pkg::lc_otp_vendor_test_rsp_t)-1:0] lc_otp_vendor_test_o_o = 'bz; + tri [$bits(caliptra_otp_ctrl_pkg::lc_otp_program_rsp_t)-1:0] lc_otp_program_o_i; + reg [$bits(caliptra_otp_ctrl_pkg::lc_otp_program_rsp_t)-1:0] lc_otp_program_o_o = 'bz; + tri [$bits(caliptra_otp_ctrl_pkg::otp_lc_data_t)-1:0] otp_lc_data_o_i; + reg [$bits(caliptra_otp_ctrl_pkg::otp_lc_data_t)-1:0] otp_lc_data_o_o = 'bz; + + // INITIATOR mode output signals + + // Bi-directional signals + + + assign clk_i_i = bus.clk_i; + assign rst_ni_i = bus.rst_ni; + + // These are signals marked as 'input' by the config file, but the signals will be + // driven by this BFM if put into RESPONDER mode (flipping all signal directions around) + assign lc_otp_vendor_test_o_i = bus.lc_otp_vendor_test_o; + assign bus.lc_otp_vendor_test_o = (initiator_responder == RESPONDER) ? lc_otp_vendor_test_o_o : 'bz; + assign lc_otp_program_o_i = bus.lc_otp_program_o; + assign bus.lc_otp_program_o = (initiator_responder == RESPONDER) ? lc_otp_program_o_o : 'bz; + assign otp_lc_data_o_i = bus.otp_lc_data_o; + assign bus.otp_lc_data_o = (initiator_responder == RESPONDER) ? otp_lc_data_o_o : 'bz; + + + // These are signals marked as 'output' by the config file, but the outputs will + // not be driven by this BFM unless placed in INITIATOR mode. + + // Proxy handle to UVM driver + fuse_ctrl_lc_otp_out_pkg::fuse_ctrl_lc_otp_out_driver proxy; + // pragma tbx oneway proxy.my_function_name_in_uvm_driver + + // **************************************************************************** + // **************************************************************************** + // Macros that define structs located in fuse_ctrl_lc_otp_out_macros.svh + // **************************************************************************** + // Struct for passing configuration data from fuse_ctrl_lc_otp_out_driver to this BFM + // **************************************************************************** + `fuse_ctrl_lc_otp_out_CONFIGURATION_STRUCT + // **************************************************************************** + // Structs for INITIATOR and RESPONDER data flow + //******************************************************************* + // Initiator macro used by fuse_ctrl_lc_otp_out_driver and fuse_ctrl_lc_otp_out_driver_bfm + // to communicate initiator driven data to fuse_ctrl_lc_otp_out_driver_bfm. + `fuse_ctrl_lc_otp_out_INITIATOR_STRUCT + fuse_ctrl_lc_otp_out_initiator_s initiator_struct; + // Responder macro used by fuse_ctrl_lc_otp_out_driver and fuse_ctrl_lc_otp_out_driver_bfm + // to communicate Responder driven data to fuse_ctrl_lc_otp_out_driver_bfm. + `fuse_ctrl_lc_otp_out_RESPONDER_STRUCT + fuse_ctrl_lc_otp_out_responder_s responder_struct; + + // **************************************************************************** +// pragma uvmf custom reset_condition_and_response begin + // Always block used to return signals to reset value upon assertion of reset + always @( negedge rst_ni_i ) + begin + // RESPONDER mode output signals + lc_otp_vendor_test_o_o <= 'bz; + lc_otp_program_o_o <= 'bz; + otp_lc_data_o_o <= 'bz; + // INITIATOR mode output signals + // Bi-directional signals + + end +// pragma uvmf custom reset_condition_and_response end + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the driver BFM. It is called by the driver within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the driver BFM needs to be aware of the new configuration + // variables. + // + + function void configure(fuse_ctrl_lc_otp_out_configuration_s fuse_ctrl_lc_otp_out_configuration_arg); // pragma tbx xtf + initiator_responder = fuse_ctrl_lc_otp_out_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + +// pragma uvmf custom initiate_and_get_response begin +// **************************************************************************** +// UVMF_CHANGE_ME +// This task is used by an initator. The task first initiates a transfer then +// waits for the responder to complete the transfer. + task initiate_and_get_response( + // This argument passes transaction variables used by an initiator + // to perform the initial part of a protocol transfer. The values + // come from a sequence item created in a sequence. + input fuse_ctrl_lc_otp_out_initiator_s fuse_ctrl_lc_otp_out_initiator_struct, + // This argument is used to send data received from the responder + // back to the sequence item. The sequence item is returned to the sequence. + output fuse_ctrl_lc_otp_out_responder_s fuse_ctrl_lc_otp_out_responder_struct + );// pragma tbx xtf + // + // Members within the fuse_ctrl_lc_otp_out_initiator_struct: + // caliptra_otp_ctrl_pkg::otp_lc_data_t otp_lc_data_o ; + // Members within the fuse_ctrl_lc_otp_out_responder_struct: + // caliptra_otp_ctrl_pkg::otp_lc_data_t otp_lc_data_o ; + initiator_struct = fuse_ctrl_lc_otp_out_initiator_struct; + // + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clk_i_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available initiator input and inout signals listed. + // Initiator input signals + // fuse_ctrl_lc_otp_out_responder_struct.xyz = lc_otp_vendor_test_o_i; // [$bits(caliptra_otp_ctrl_pkg::lc_otp_vendor_test_rsp_t)-1:0] + // fuse_ctrl_lc_otp_out_responder_struct.xyz = lc_otp_program_o_i; // [$bits(caliptra_otp_ctrl_pkg::lc_otp_program_rsp_t)-1:0] + // fuse_ctrl_lc_otp_out_responder_struct.xyz = otp_lc_data_o_i; // [$bits(caliptra_otp_ctrl_pkg::otp_lc_data_t)-1:0] + // Initiator inout signals + // How to assign a signal from an initiator struct member named xyz. + // All available initiator output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Initiator output signals + // Initiator inout signals + // Initiate a transfer using the data received. + @(posedge clk_i_i); + @(posedge clk_i_i); + // Wait for the responder to complete the transfer then place the responder data into + // fuse_ctrl_lc_otp_out_responder_struct. + @(posedge clk_i_i); + @(posedge clk_i_i); + responder_struct = fuse_ctrl_lc_otp_out_responder_struct; + endtask +// pragma uvmf custom initiate_and_get_response end + +// pragma uvmf custom respond_and_wait_for_next_transfer begin +// **************************************************************************** +// The first_transfer variable is used to prevent completing a transfer in the +// first call to this task. For the first call to this task, there is not +// current transfer to complete. +bit first_transfer=1; + +// UVMF_CHANGE_ME +// This task is used by a responder. The task first completes the current +// transfer in progress then waits for the initiator to start the next transfer. + task respond_and_wait_for_next_transfer( + // This argument is used to send data received from the initiator + // back to the sequence item. The sequence determines how to respond. + output fuse_ctrl_lc_otp_out_initiator_s fuse_ctrl_lc_otp_out_initiator_struct, + // This argument passes transaction variables used by a responder + // to complete a protocol transfer. The values come from a sequence item. + input fuse_ctrl_lc_otp_out_responder_s fuse_ctrl_lc_otp_out_responder_struct + );// pragma tbx xtf + // Variables within the fuse_ctrl_lc_otp_out_initiator_struct: + // caliptra_otp_ctrl_pkg::otp_lc_data_t otp_lc_data_o ; + // Variables within the fuse_ctrl_lc_otp_out_responder_struct: + // caliptra_otp_ctrl_pkg::otp_lc_data_t otp_lc_data_o ; + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clk_i_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available responder input and inout signals listed. + // Responder input signals + // Responder inout signals + // How to assign a signal, named xyz, from an initiator struct member. + // All available responder output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Responder output signals + // lc_otp_vendor_test_o_o <= fuse_ctrl_lc_otp_out_initiator_struct.xyz; // [$bits(caliptra_otp_ctrl_pkg::lc_otp_vendor_test_rsp_t)-1:0] + // lc_otp_program_o_o <= fuse_ctrl_lc_otp_out_initiator_struct.xyz; // [$bits(caliptra_otp_ctrl_pkg::lc_otp_program_rsp_t)-1:0] + // otp_lc_data_o_o <= fuse_ctrl_lc_otp_out_initiator_struct.xyz; // [$bits(caliptra_otp_ctrl_pkg::otp_lc_data_t)-1:0] + // Responder inout signals + + @(posedge clk_i_i); + if (!first_transfer) begin + // Perform transfer response here. + // Reply using data recieved in the fuse_ctrl_lc_otp_out_responder_struct. + @(posedge clk_i_i); + // Reply using data recieved in the transaction handle. + @(posedge clk_i_i); + end + // Wait for next transfer then gather info from intiator about the transfer. + // Place the data into the fuse_ctrl_lc_otp_out_initiator_struct. + @(posedge clk_i_i); + @(posedge clk_i_i); + first_transfer = 0; + endtask +// pragma uvmf custom respond_and_wait_for_next_transfer end + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_if.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_if.sv new file mode 100644 index 0000000..f4fcd32 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_if.sv @@ -0,0 +1,88 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface contains the fuse_ctrl_lc_otp_out interface signals. +// It is instantiated once per fuse_ctrl_lc_otp_out bus. Bus Functional Models, +// BFM's named fuse_ctrl_lc_otp_out_driver_bfm, are used to drive signals on the bus. +// BFM's named fuse_ctrl_lc_otp_out_monitor_bfm are used to monitor signals on the +// bus. This interface signal bundle is passed in the port list of +// the BFM in order to give the BFM access to the signals in this +// interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// This template can be used to connect a DUT to these signals +// +// .dut_signal_port(fuse_ctrl_lc_otp_out_bus.lc_otp_vendor_test_o), // Agent input +// .dut_signal_port(fuse_ctrl_lc_otp_out_bus.lc_otp_program_o), // Agent input +// .dut_signal_port(fuse_ctrl_lc_otp_out_bus.otp_lc_data_o), // Agent input + +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_lc_otp_out_pkg_hdl::*; + +interface fuse_ctrl_lc_otp_out_if + + ( + input tri clk_i, + input tri rst_ni, + inout tri [$bits(caliptra_otp_ctrl_pkg::lc_otp_vendor_test_rsp_t)-1:0] lc_otp_vendor_test_o, + inout tri [$bits(caliptra_otp_ctrl_pkg::lc_otp_program_rsp_t)-1:0] lc_otp_program_o, + inout tri [$bits(caliptra_otp_ctrl_pkg::otp_lc_data_t)-1:0] otp_lc_data_o + ); + +modport monitor_port + ( + input clk_i, + input rst_ni, + input lc_otp_vendor_test_o, + input lc_otp_program_o, + input otp_lc_data_o + ); + +modport initiator_port + ( + input clk_i, + input rst_ni, + input lc_otp_vendor_test_o, + input lc_otp_program_o, + input otp_lc_data_o + ); + +modport responder_port + ( + input clk_i, + input rst_ni, + output lc_otp_vendor_test_o, + output lc_otp_program_o, + output otp_lc_data_o + ); + + +// pragma uvmf custom interface_item_additional begin +// pragma uvmf custom interface_item_additional end + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_infact_coverage_strategy.csv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_infact_coverage_strategy.csv new file mode 100644 index 0000000..1c218e1 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_infact_coverage_strategy.csv @@ -0,0 +1,6 @@ +Global +auto_bin_max, 64 + +Name,Type,Include +rand_fields,coverpoint,=rand *.** + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_macros.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_macros.svh new file mode 100644 index 0000000..f9c1d7b --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_macros.svh @@ -0,0 +1,135 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains macros used with the fuse_ctrl_lc_otp_out package. +// These macros include packed struct definitions. These structs are +// used to pass data between classes, hvl, and BFM's, hdl. Use of +// structs are more efficient and simpler to modify. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_struct +// and from_struct methods defined in the macros below that are used in +// the fuse_ctrl_lc_otp_out_configuration class. +// + `define fuse_ctrl_lc_otp_out_CONFIGURATION_STRUCT \ +typedef struct packed { \ + uvmf_active_passive_t active_passive; \ + uvmf_initiator_responder_t initiator_responder; \ + } fuse_ctrl_lc_otp_out_configuration_s; + + `define fuse_ctrl_lc_otp_out_CONFIGURATION_TO_STRUCT_FUNCTION \ + virtual function fuse_ctrl_lc_otp_out_configuration_s to_struct();\ + fuse_ctrl_lc_otp_out_configuration_struct = \ + {\ + this.active_passive,\ + this.initiator_responder\ + };\ + return ( fuse_ctrl_lc_otp_out_configuration_struct );\ + endfunction + + `define fuse_ctrl_lc_otp_out_CONFIGURATION_FROM_STRUCT_FUNCTION \ + virtual function void from_struct(fuse_ctrl_lc_otp_out_configuration_s fuse_ctrl_lc_otp_out_configuration_struct);\ + {\ + this.active_passive,\ + this.initiator_responder \ + } = fuse_ctrl_lc_otp_out_configuration_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_monitor_struct +// and from_monitor_struct methods of the fuse_ctrl_lc_otp_out_transaction class. +// + `define fuse_ctrl_lc_otp_out_MONITOR_STRUCT typedef struct packed { \ + caliptra_otp_ctrl_pkg::otp_lc_data_t otp_lc_data_o ; \ + } fuse_ctrl_lc_otp_out_monitor_s; + + `define fuse_ctrl_lc_otp_out_TO_MONITOR_STRUCT_FUNCTION \ + virtual function fuse_ctrl_lc_otp_out_monitor_s to_monitor_struct();\ + fuse_ctrl_lc_otp_out_monitor_struct = \ + { \ + this.otp_lc_data_o \ + };\ + return ( fuse_ctrl_lc_otp_out_monitor_struct);\ + endfunction\ + + `define fuse_ctrl_lc_otp_out_FROM_MONITOR_STRUCT_FUNCTION \ + virtual function void from_monitor_struct(fuse_ctrl_lc_otp_out_monitor_s fuse_ctrl_lc_otp_out_monitor_struct);\ + {\ + this.otp_lc_data_o \ + } = fuse_ctrl_lc_otp_out_monitor_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_initiator_struct +// and from_initiator_struct methods of the fuse_ctrl_lc_otp_out_transaction class. +// Also update the comments in the driver BFM. +// + `define fuse_ctrl_lc_otp_out_INITIATOR_STRUCT typedef struct packed { \ + caliptra_otp_ctrl_pkg::otp_lc_data_t otp_lc_data_o ; \ + } fuse_ctrl_lc_otp_out_initiator_s; + + `define fuse_ctrl_lc_otp_out_TO_INITIATOR_STRUCT_FUNCTION \ + virtual function fuse_ctrl_lc_otp_out_initiator_s to_initiator_struct();\ + fuse_ctrl_lc_otp_out_initiator_struct = \ + {\ + this.otp_lc_data_o \ + };\ + return ( fuse_ctrl_lc_otp_out_initiator_struct);\ + endfunction + + `define fuse_ctrl_lc_otp_out_FROM_INITIATOR_STRUCT_FUNCTION \ + virtual function void from_initiator_struct(fuse_ctrl_lc_otp_out_initiator_s fuse_ctrl_lc_otp_out_initiator_struct);\ + {\ + this.otp_lc_data_o \ + } = fuse_ctrl_lc_otp_out_initiator_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_responder_struct +// and from_responder_struct methods of the fuse_ctrl_lc_otp_out_transaction class. +// Also update the comments in the driver BFM. +// + `define fuse_ctrl_lc_otp_out_RESPONDER_STRUCT typedef struct packed { \ + caliptra_otp_ctrl_pkg::otp_lc_data_t otp_lc_data_o ; \ + } fuse_ctrl_lc_otp_out_responder_s; + + `define fuse_ctrl_lc_otp_out_TO_RESPONDER_STRUCT_FUNCTION \ + virtual function fuse_ctrl_lc_otp_out_responder_s to_responder_struct();\ + fuse_ctrl_lc_otp_out_responder_struct = \ + {\ + this.otp_lc_data_o \ + };\ + return ( fuse_ctrl_lc_otp_out_responder_struct);\ + endfunction + + `define fuse_ctrl_lc_otp_out_FROM_RESPONDER_STRUCT_FUNCTION \ + virtual function void from_responder_struct(fuse_ctrl_lc_otp_out_responder_s fuse_ctrl_lc_otp_out_responder_struct);\ + {\ + this.otp_lc_data_o \ + } = fuse_ctrl_lc_otp_out_responder_struct;\ + endfunction +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_monitor.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_monitor.svh new file mode 100644 index 0000000..0c9f446 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_monitor.svh @@ -0,0 +1,101 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class receives fuse_ctrl_lc_otp_out transactions observed by the +// fuse_ctrl_lc_otp_out monitor BFM and broadcasts them through the analysis port +// on the agent. It accesses the monitor BFM through the monitor +// task. This UVM component captures transactions +// for viewing in the waveform viewer if the +// enable_transaction_viewing flag is set in the configuration. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_lc_otp_out_monitor extends uvmf_monitor_base #( + .CONFIG_T(fuse_ctrl_lc_otp_out_configuration ), + .BFM_BIND_T(virtual fuse_ctrl_lc_otp_out_monitor_bfm ), + .TRANS_T(fuse_ctrl_lc_otp_out_transaction )); + + `uvm_component_utils( fuse_ctrl_lc_otp_out_monitor ) + +// Structure used to pass data from monitor BFM to monitor class in agent. +// Use to_monitor_struct function to pack transaction variables into structure. +// Use from_monitor_struct function to unpack transaction variables from structure. +`fuse_ctrl_lc_otp_out_MONITOR_STRUCT + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the monitor BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// monitor BFM. This allows the monitor BFM to call the notify_transaction +// function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// *************************************************************************** + virtual task run_phase(uvm_phase phase); + // Start monitor BFM thread and don't call super.run() in order to + // override the default monitor proxy 'pull' behavior with the more + // emulation-friendly BFM 'push' approach using the notify_transaction + // function below + bfm.start_monitoring(); + endtask + +// ************************************************************************** + +// This function is called by the monitor BFM. It receives data observed by the +// monitor BFM. Data is passed using the fuse_ctrl_lc_otp_out_monitor_struct. + virtual function void notify_transaction(input fuse_ctrl_lc_otp_out_monitor_s fuse_ctrl_lc_otp_out_monitor_struct); + + + trans = new("trans"); + trans.from_monitor_struct(fuse_ctrl_lc_otp_out_monitor_struct); + trans.start_time = time_stamp; + trans.end_time = $time; + time_stamp = trans.end_time; + + analyze(trans); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_monitor_bfm.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_monitor_bfm.sv new file mode 100644 index 0000000..ca97fe2 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_monitor_bfm.sv @@ -0,0 +1,194 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface performs the fuse_ctrl_lc_otp_out signal monitoring. +// It is accessed by the uvm fuse_ctrl_lc_otp_out monitor through a virtual +// interface handle in the fuse_ctrl_lc_otp_out configuration. It monitors the +// signals passed in through the port connection named bus of +// type fuse_ctrl_lc_otp_out_if. +// +// Input signals from the fuse_ctrl_lc_otp_out_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// Interface functions and tasks used by UVM components: +// monitor(inout TRANS_T txn); +// This task receives the transaction, txn, from the +// UVM monitor and then populates variables in txn +// from values observed on bus activity. This task +// blocks until an operation on the fuse_ctrl_lc_otp_out bus is complete. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_lc_otp_out_pkg_hdl::*; +`include "src/fuse_ctrl_lc_otp_out_macros.svh" + + +interface fuse_ctrl_lc_otp_out_monitor_bfm + ( fuse_ctrl_lc_otp_out_if bus ); + // The pragma below and additional ones in-lined further down are for running this BFM on Veloce + // pragma attribute fuse_ctrl_lc_otp_out_monitor_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: ", ), + UVM_DEBUG) +end +`endif + + + // Structure used to pass transaction data from monitor BFM to monitor class in agent. +`fuse_ctrl_lc_otp_out_MONITOR_STRUCT + fuse_ctrl_lc_otp_out_monitor_s fuse_ctrl_lc_otp_out_monitor_struct; + + // Structure used to pass configuration data from monitor class to monitor BFM. + `fuse_ctrl_lc_otp_out_CONFIGURATION_STRUCT + + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + tri clk_i_i; + tri rst_ni_i; + tri [$bits(caliptra_otp_ctrl_pkg::lc_otp_vendor_test_rsp_t)-1:0] lc_otp_vendor_test_o_i; + tri [$bits(caliptra_otp_ctrl_pkg::lc_otp_program_rsp_t)-1:0] lc_otp_program_o_i; + tri [$bits(caliptra_otp_ctrl_pkg::otp_lc_data_t)-1:0] otp_lc_data_o_i; + assign clk_i_i = bus.clk_i; + assign rst_ni_i = bus.rst_ni; + assign lc_otp_vendor_test_o_i = bus.lc_otp_vendor_test_o; + assign lc_otp_program_o_i = bus.lc_otp_program_o; + assign otp_lc_data_o_i = bus.otp_lc_data_o; + + // Proxy handle to UVM monitor + fuse_ctrl_lc_otp_out_pkg::fuse_ctrl_lc_otp_out_monitor proxy; + // pragma tbx oneway proxy.notify_transaction + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + task wait_for_reset();// pragma tbx xtf + @(posedge clk_i_i) ; + do_wait_for_reset(); + endtask + + // **************************************************************************** + task do_wait_for_reset(); + // pragma uvmf custom reset_condition begin + wait ( rst_ni_i === 1 ) ; + @(posedge clk_i_i) ; + // pragma uvmf custom reset_condition end + endtask + + //****************************************************************** + + task wait_for_num_clocks(input int unsigned count); // pragma tbx xtf + @(posedge clk_i_i); + + repeat (count-1) @(posedge clk_i_i); + endtask + + //****************************************************************** + event go; + function void start_monitoring();// pragma tbx xtf + -> go; + endfunction + + // **************************************************************************** + initial begin + @go; + forever begin + @(posedge clk_i_i); + do_monitor( fuse_ctrl_lc_otp_out_monitor_struct ); + + + proxy.notify_transaction( fuse_ctrl_lc_otp_out_monitor_struct ); + + end + end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the monitor BFM. It is called by the monitor within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the monitor BFM needs to be aware of the new configuration + // variables. + // + function void configure(fuse_ctrl_lc_otp_out_configuration_s fuse_ctrl_lc_otp_out_configuration_arg); // pragma tbx xtf + initiator_responder = fuse_ctrl_lc_otp_out_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + + + // **************************************************************************** + + task do_monitor(output fuse_ctrl_lc_otp_out_monitor_s fuse_ctrl_lc_otp_out_monitor_struct); + // + // Available struct members: + // // fuse_ctrl_lc_otp_out_monitor_struct.otp_lc_data_o + // // + // Reference code; + // How to wait for signal value + // while (control_signal === 1'b1) @(posedge clk_i_i); + // + // How to assign a struct member, named xyz, from a signal. + // All available input signals listed. + // fuse_ctrl_lc_otp_out_monitor_struct.xyz = lc_otp_vendor_test_o_i; // [$bits(caliptra_otp_ctrl_pkg::lc_otp_vendor_test_rsp_t)-1:0] + // fuse_ctrl_lc_otp_out_monitor_struct.xyz = lc_otp_program_o_i; // [$bits(caliptra_otp_ctrl_pkg::lc_otp_program_rsp_t)-1:0] + // fuse_ctrl_lc_otp_out_monitor_struct.xyz = otp_lc_data_o_i; // [$bits(caliptra_otp_ctrl_pkg::otp_lc_data_t)-1:0] + // pragma uvmf custom do_monitor begin + // UVMF_CHANGE_ME : Implement protocol monitoring. The commented reference code + // below are examples of how to capture signal values and assign them to + // structure members. All available input signals are listed. The 'while' + // code example shows how to wait for a synchronous flow control signal. This + // task should return when a complete transfer has been observed. Once this task is + // exited with captured values, it is then called again to wait for and observe + // the next transfer. One clock cycle is consumed between calls to do_monitor. + @(posedge clk_i_i); + @(posedge clk_i_i); + @(posedge clk_i_i); + @(posedge clk_i_i); + // pragma uvmf custom do_monitor end + endtask + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_random_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_random_sequence.svh new file mode 100644 index 0000000..a680653 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_random_sequence.svh @@ -0,0 +1,67 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This sequences randomizes the fuse_ctrl_lc_otp_out transaction and sends it +// to the UVM driver. +// +// This sequence constructs and randomizes a fuse_ctrl_lc_otp_out_transaction. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_lc_otp_out_random_sequence + extends fuse_ctrl_lc_otp_out_sequence_base ; + + `uvm_object_utils( fuse_ctrl_lc_otp_out_random_sequence ) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //***************************************************************** + function new(string name = ""); + super.new(name); + endfunction: new + + // **************************************************************************** + // TASK : body() + // This task is automatically executed when this sequence is started using the + // start(sequencerHandle) task. + // + task body(); + + // Construct the transaction + req=fuse_ctrl_lc_otp_out_transaction::type_id::create("req"); + start_item(req); + // Randomize the transaction + if(!req.randomize()) `uvm_fatal("SEQ", "fuse_ctrl_lc_otp_out_random_sequence::body()-fuse_ctrl_lc_otp_out_transaction randomization failed") + // Send the transaction to the fuse_ctrl_lc_otp_out_driver_bfm via the sequencer and fuse_ctrl_lc_otp_out_driver. + finish_item(req); + `uvm_info("SEQ", {"Response:",req.convert2string()},UVM_MEDIUM) + + endtask + +endclass: fuse_ctrl_lc_otp_out_random_sequence + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_responder_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_responder_sequence.svh new file mode 100644 index 0000000..0e7cf5c --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_responder_sequence.svh @@ -0,0 +1,63 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class can be used to provide stimulus when an interface +// has been configured to run in a responder mode. It +// will never finish by default, always going back to the driver +// and driver BFM for the next transaction with which to respond. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_lc_otp_out_responder_sequence + extends fuse_ctrl_lc_otp_out_sequence_base ; + + `uvm_object_utils( fuse_ctrl_lc_otp_out_responder_sequence ) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "fuse_ctrl_lc_otp_out_responder_sequence"); + super.new(name); + endfunction + + task body(); + req=fuse_ctrl_lc_otp_out_transaction::type_id::create("req"); + forever begin + start_item(req); + finish_item(req); + // pragma uvmf custom body begin + // UVMF_CHANGE_ME : Do something here with the resulting req item. The + // finish_item() call above will block until the req transaction is ready + // to be handled by the responder sequence. + // If this was an item that required a response, the expectation is + // that the response should be populated within this transaction now. + `uvm_info("SEQ",$sformatf("Processed txn: %s",req.convert2string()),UVM_HIGH) + // pragma uvmf custom body end + end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_sequence_base.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_sequence_base.svh new file mode 100644 index 0000000..d084a6b --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_sequence_base.svh @@ -0,0 +1,110 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the class used as the base class for all sequences +// for this interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_lc_otp_out_sequence_base extends uvmf_sequence_base #( + .REQ(fuse_ctrl_lc_otp_out_transaction ), + .RSP(fuse_ctrl_lc_otp_out_transaction )); + + `uvm_object_utils( fuse_ctrl_lc_otp_out_sequence_base ) + + // variables + typedef fuse_ctrl_lc_otp_out_transaction fuse_ctrl_lc_otp_out_transaction_req_t; + fuse_ctrl_lc_otp_out_transaction_req_t req; + typedef fuse_ctrl_lc_otp_out_transaction fuse_ctrl_lc_otp_out_transaction_rsp_t; + fuse_ctrl_lc_otp_out_transaction_rsp_t rsp; + + // Event for identifying when a response was received from the sequencer + event new_rsp; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // TASK : get_responses() + // This task recursively gets sequence item responses from the sequencer. + // + virtual task get_responses(); + fork + begin + // Block until new rsp available + get_response(rsp); + // New rsp received. Indicate to sequence using event. + ->new_rsp; + // Display the received response transaction + `uvm_info("SEQ", {"New response transaction:",rsp.convert2string()}, UVM_MEDIUM) + end + join_none + endtask + + // **************************************************************************** + // TASK : pre_body() + // This task is called automatically when start is called with call_pre_post set to 1 (default). + // By calling get_responses() within pre_body() any derived sequences are automatically + // processing response transactions. Only un-comment this call to get_responses() if you + // have configured the interface driver to utilize the response transaction path by setting + // the configuration variable "return_transaction_response" to 1. Otherwise it is possible + // to impact runtime performance and memory utilization. + // + virtual task pre_body(); + // pragma uvmf custom pre_body begin +// get_responses(); + // pragma uvmf custom pre_body end + endtask + + // **************************************************************************** + // TASK : body() + // This task is called automatically when start is called. This sequence sends + // a req sequence item to the sequencer identified as an argument in the call + // to start. + // + virtual task body(); + // pragma uvmf custom body begin + start_item(req); + finish_item(req); + // pragma uvmf custom body end + endtask + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name =""); + super.new( name ); + // pragma uvmf custom new begin + req = fuse_ctrl_lc_otp_out_transaction_req_t::type_id::create("req"); + rsp = fuse_ctrl_lc_otp_out_transaction_rsp_t::type_id::create("rsp"); + // pragma uvmf custom new end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_transaction.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_transaction.svh new file mode 100644 index 0000000..f62fa69 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_transaction.svh @@ -0,0 +1,196 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class defines the variables required for an fuse_ctrl_lc_otp_out +// transaction. Class variables to be displayed in waveform transaction +// viewing are added to the transaction viewing stream in the add_to_wave +// function. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_lc_otp_out_transaction extends uvmf_transaction_base; + + `uvm_object_utils( fuse_ctrl_lc_otp_out_transaction ) + + caliptra_otp_ctrl_pkg::otp_lc_data_t otp_lc_data_o ; + + //Constraints for the transaction variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //******************************************************************* + //******************************************************************* + // Macros that define structs and associated functions are + // located in fuse_ctrl_lc_otp_out_macros.svh + + //******************************************************************* + // Monitor macro used by fuse_ctrl_lc_otp_out_monitor and fuse_ctrl_lc_otp_out_monitor_bfm + // This struct is defined in fuse_ctrl_lc_otp_out_macros.svh + `fuse_ctrl_lc_otp_out_MONITOR_STRUCT + fuse_ctrl_lc_otp_out_monitor_s fuse_ctrl_lc_otp_out_monitor_struct; + //******************************************************************* + // FUNCTION: to_monitor_struct() + // This function packs transaction variables into a fuse_ctrl_lc_otp_out_monitor_s + // structure. The function returns the handle to the fuse_ctrl_lc_otp_out_monitor_struct. + // This function is defined in fuse_ctrl_lc_otp_out_macros.svh + `fuse_ctrl_lc_otp_out_TO_MONITOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_monitor_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_lc_otp_out_macros.svh + `fuse_ctrl_lc_otp_out_FROM_MONITOR_STRUCT_FUNCTION + + //******************************************************************* + // Initiator macro used by fuse_ctrl_lc_otp_out_driver and fuse_ctrl_lc_otp_out_driver_bfm + // to communicate initiator driven data to fuse_ctrl_lc_otp_out_driver_bfm. + // This struct is defined in fuse_ctrl_lc_otp_out_macros.svh + `fuse_ctrl_lc_otp_out_INITIATOR_STRUCT + fuse_ctrl_lc_otp_out_initiator_s fuse_ctrl_lc_otp_out_initiator_struct; + //******************************************************************* + // FUNCTION: to_initiator_struct() + // This function packs transaction variables into a fuse_ctrl_lc_otp_out_initiator_s + // structure. The function returns the handle to the fuse_ctrl_lc_otp_out_initiator_struct. + // This function is defined in fuse_ctrl_lc_otp_out_macros.svh + `fuse_ctrl_lc_otp_out_TO_INITIATOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_initiator_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_lc_otp_out_macros.svh + `fuse_ctrl_lc_otp_out_FROM_INITIATOR_STRUCT_FUNCTION + + //******************************************************************* + // Responder macro used by fuse_ctrl_lc_otp_out_driver and fuse_ctrl_lc_otp_out_driver_bfm + // to communicate Responder driven data to fuse_ctrl_lc_otp_out_driver_bfm. + // This struct is defined in fuse_ctrl_lc_otp_out_macros.svh + `fuse_ctrl_lc_otp_out_RESPONDER_STRUCT + fuse_ctrl_lc_otp_out_responder_s fuse_ctrl_lc_otp_out_responder_struct; + //******************************************************************* + // FUNCTION: to_responder_struct() + // This function packs transaction variables into a fuse_ctrl_lc_otp_out_responder_s + // structure. The function returns the handle to the fuse_ctrl_lc_otp_out_responder_struct. + // This function is defined in fuse_ctrl_lc_otp_out_macros.svh + `fuse_ctrl_lc_otp_out_TO_RESPONDER_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_responder_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_lc_otp_out_macros.svh + `fuse_ctrl_lc_otp_out_FROM_RESPONDER_STRUCT_FUNCTION + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + endfunction + + // **************************************************************************** + // FUNCTION: convert2string() + // This function converts all variables in this class to a single string for + // logfile reporting. + // + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + // UVMF_CHANGE_ME : Customize format if desired. + return $sformatf("otp_lc_data_o:0x%x ",otp_lc_data_o); + // pragma uvmf custom convert2string end + endfunction + + //******************************************************************* + // FUNCTION: do_print() + // This function is automatically called when the .print() function + // is called on this class. + // + virtual function void do_print(uvm_printer printer); + // pragma uvmf custom do_print begin + // UVMF_CHANGE_ME : Current contents of do_print allows for the use of UVM 1.1d, 1.2 or P1800.2. + // Update based on your own printing preference according to your preferred UVM version + $display(convert2string()); + // pragma uvmf custom do_print end + endfunction + + //******************************************************************* + // FUNCTION: do_compare() + // This function is automatically called when the .compare() function + // is called on this class. + // + virtual function bit do_compare (uvm_object rhs, uvm_comparer comparer); + fuse_ctrl_lc_otp_out_transaction RHS; + if (!$cast(RHS,rhs)) return 0; + // pragma uvmf custom do_compare begin + // UVMF_CHANGE_ME : Eliminate comparison of variables not to be used for compare + return (super.do_compare(rhs,comparer) + &&(this.otp_lc_data_o == RHS.otp_lc_data_o) + ); + // pragma uvmf custom do_compare end + endfunction + + //******************************************************************* + // FUNCTION: do_copy() + // This function is automatically called when the .copy() function + // is called on this class. + // + virtual function void do_copy (uvm_object rhs); + fuse_ctrl_lc_otp_out_transaction RHS; + assert($cast(RHS,rhs)); + // pragma uvmf custom do_copy begin + super.do_copy(rhs); + this.otp_lc_data_o = RHS.otp_lc_data_o; + // pragma uvmf custom do_copy end + endfunction + + // **************************************************************************** + // FUNCTION: add_to_wave() + // This function is used to display variables in this class in the waveform + // viewer. The start_time and end_time variables must be set before this + // function is called. If the start_time and end_time variables are not set + // the transaction will be hidden at 0ns on the waveform display. + // + virtual function void add_to_wave(int transaction_viewing_stream_h); + `ifdef QUESTA + if (transaction_view_h == 0) begin + transaction_view_h = $begin_transaction(transaction_viewing_stream_h,"fuse_ctrl_lc_otp_out_transaction",start_time); + end + super.add_to_wave(transaction_view_h); + // pragma uvmf custom add_to_wave begin + // UVMF_CHANGE_ME : Color can be applied to transaction entries based on content, example below + // case() + // 1 : $add_color(transaction_view_h,"red"); + // default : $add_color(transaction_view_h,"grey"); + // endcase + // UVMF_CHANGE_ME : Eliminate transaction variables not wanted in transaction viewing in the waveform viewer + $add_attribute(transaction_view_h,otp_lc_data_o,"otp_lc_data_o"); + // pragma uvmf custom add_to_wave end + $end_transaction(transaction_view_h,end_time); + $free_transaction(transaction_view_h); + `endif // QUESTA + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_transaction_coverage.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_transaction_coverage.svh new file mode 100644 index 0000000..25eeac7 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_transaction_coverage.svh @@ -0,0 +1,84 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class records fuse_ctrl_lc_otp_out transaction information using +// a covergroup named fuse_ctrl_lc_otp_out_transaction_cg. An instance of this +// coverage component is instantiated in the uvmf_parameterized_agent +// if the has_coverage flag is set. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_lc_otp_out_transaction_coverage extends uvm_subscriber #(.T(fuse_ctrl_lc_otp_out_transaction )); + + `uvm_component_utils( fuse_ctrl_lc_otp_out_transaction_coverage ) + + T coverage_trans; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + covergroup fuse_ctrl_lc_otp_out_transaction_cg; + // pragma uvmf custom covergroup begin + // UVMF_CHANGE_ME : Add coverage bins, crosses, exclusions, etc. according to coverage needs. + option.auto_bin_max=1024; + option.per_instance=1; + otp_lc_data_o: coverpoint coverage_trans.otp_lc_data_o; + // pragma uvmf custom covergroup end + endgroup + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new(string name="", uvm_component parent=null); + super.new(name,parent); + fuse_ctrl_lc_otp_out_transaction_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that transaction variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + endfunction + + // **************************************************************************** + // FUNCTION : build_phase() + // This function is the standard UVM build_phase. + // + function void build_phase(uvm_phase phase); + fuse_ctrl_lc_otp_out_transaction_cg.set_inst_name($sformatf("fuse_ctrl_lc_otp_out_transaction_cg_%s",get_full_name())); + endfunction + + // **************************************************************************** + // FUNCTION: write (T t) + // This function is automatically executed when a transaction arrives on the + // analysis_export. It copies values from the variables in the transaction + // to local variables used to collect functional coverage. + // + virtual function void write (T t); + `uvm_info("COV","Received transaction",UVM_HIGH); + coverage_trans = t; + fuse_ctrl_lc_otp_out_transaction_cg.sample(); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_typedefs.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_typedefs.svh new file mode 100644 index 0000000..f2a7bdb --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_typedefs.svh @@ -0,0 +1,34 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the host server when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_typedefs_hdl.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_typedefs_hdl.svh new file mode 100644 index 0000000..0d58518 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_typedefs_hdl.svh @@ -0,0 +1,35 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the emulator when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/yaml/fuse_ctrl_lc_otp_out_interface.yaml b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/yaml/fuse_ctrl_lc_otp_out_interface.yaml new file mode 100644 index 0000000..5b9107e --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/yaml/fuse_ctrl_lc_otp_out_interface.yaml @@ -0,0 +1,37 @@ +uvmf: + interfaces: + fuse_ctrl_lc_otp_out: + clock: clk_i + config_constraints: [] + config_vars: [] + existing_library_component: 'True' + gen_inbound_streaming_driver: 'False' + hdl_pkg_parameters: [] + hdl_typedefs: [] + hvl_pkg_parameters: [] + hvl_typedefs: [] + parameters: [] + ports: + - dir: input + name: lc_otp_vendor_test_o + reset_value: '''bz' + width: '[''$bits(caliptra_otp_ctrl_pkg::lc_otp_vendor_test_rsp_t)'']' + - dir: input + name: lc_otp_program_o + reset_value: '''bz' + width: '[''$bits(caliptra_otp_ctrl_pkg::lc_otp_program_rsp_t)'']' + - dir: input + name: otp_lc_data_o + reset_value: '''bz' + width: '[''$bits(caliptra_otp_ctrl_pkg::otp_lc_data_t)'']' + reset: rst_ni + reset_assertion_level: 'False' + transaction_constraints: [] + transaction_vars: + - comment: '' + iscompare: 'True' + isrand: 'False' + name: otp_lc_data_o + type: caliptra_otp_ctrl_pkg::otp_lc_data_t + unpacked_dimension: '' + use_dpi_link: 'False' diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/.project b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/.project new file mode 100644 index 0000000..c96dcb4 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/.project @@ -0,0 +1,30 @@ + + + fuse_ctrl_out_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/.svproject b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/.svproject new file mode 100644 index 0000000..64d224a --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/Makefile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/Makefile new file mode 100644 index 0000000..b5ee9df --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/Makefile @@ -0,0 +1,66 @@ +# fuse_ctrl_out interface packages source +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +fuse_ctrl_out_PKG = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_out_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_filelist_hvl.f + +fuse_ctrl_out_PKG_HDL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_out_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_filelist_hdl.f + +fuse_ctrl_out_PKG_XRTL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_out_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_filelist_xrtl.f + +COMP_fuse_ctrl_out_PKG_TGT_0 = q_comp_fuse_ctrl_out_pkg +COMP_fuse_ctrl_out_PKG_TGT_1 = v_comp_fuse_ctrl_out_pkg +COMP_fuse_ctrl_out_PKG_TGT = $(COMP_fuse_ctrl_out_PKG_TGT_$(USE_VELOCE)) + +comp_fuse_ctrl_out_pkg: $(COMP_fuse_ctrl_out_PKG_TGT) + +q_comp_fuse_ctrl_out_pkg: + $(HDL_COMP_CMD) $(fuse_ctrl_out_PKG_HDL) + $(HVL_COMP_CMD) $(fuse_ctrl_out_PKG) + $(HDL_COMP_CMD) $(fuse_ctrl_out_PKG_XRTL) + +v_comp_fuse_ctrl_out_pkg: + $(HVL_COMP_CMD) $(fuse_ctrl_out_PKG_HDL) + $(HVL_COMP_CMD) $(fuse_ctrl_out_PKG) + $(VELANALYZE_CMD) $(fuse_ctrl_out_PKG_HDL) + $(VELANALYZE_HVL_CMD) $(fuse_ctrl_out_PKG) + $(HDL_COMP_CMD) $(fuse_ctrl_out_PKG_XRTL) + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export fuse_ctrl_out_IF_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_out_pkg/dpi + +C_FILE_COMPILE_LIST_fuse_ctrl_out_pkg = \ + +O_FILE_COMPILE_LIST_fuse_ctrl_out_pkg = $(notdir $(C_FILE_COMPILE_LIST_fuse_ctrl_out_pkg:.c=.o)) + +GCC_COMP_ARGS_fuse_ctrl_out_pkg += -I$(fuse_ctrl_out_IF_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_fuse_ctrl_out_pkg += $(fuse_ctrl_out_IF_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_fuse_ctrl_out_pkg += \ + \ + -o .so + +comp_fuse_ctrl_out_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Interface C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_fuse_ctrl_out_pkg) $(C_FILE_COMPILE_LIST_fuse_ctrl_out_pkg) + @echo "--------------------------------" + @echo "Linking Interface C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_fuse_ctrl_out_pkg) $(O_FILE_COMPILE_LIST_fuse_ctrl_out_pkg) + @echo "--------------------------------" + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/compile.do b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/compile.do new file mode 100644 index 0000000..5fdaafc --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/compile.do @@ -0,0 +1,14 @@ +# Tcl do file for compile of fuse_ctrl_out interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_out_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_filelist_hdl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_out_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_filelist_hvl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_out_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_filelist_xrtl.f \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out.compile new file mode 100644 index 0000000..3ac4b24 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out.compile @@ -0,0 +1,3 @@ +needs: + - fuse_ctrl_out_hvl.compile + - fuse_ctrl_out_hdl.compile diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_bfm.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_bfm.vinfo new file mode 100644 index 0000000..b4ea598 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_bfm.vinfo @@ -0,0 +1,6 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use fuse_ctrl_out_pkg_hdl.vinfo ++incdir+@vinfodir +src/fuse_ctrl_out_if.sv +src/fuse_ctrl_out_driver_bfm.sv +src/fuse_ctrl_out_monitor_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_common.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_common.compile new file mode 100644 index 0000000..1193b25 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_common.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +incdir: + - . + - ${uvm_path}/src +src: + - fuse_ctrl_out_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_filelist_hdl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_filelist_hdl.f new file mode 100644 index 0000000..5be2773 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_filelist_hdl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_filelist_hvl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_filelist_hvl.f new file mode 100644 index 0000000..fc769ad --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_filelist_hvl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_pkg.sv \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_filelist_xrtl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_filelist_xrtl.f new file mode 100644 index 0000000..4a7b8cc --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_filelist_xrtl.f @@ -0,0 +1,3 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_if.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_monitor_bfm.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_driver_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_hdl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_hdl.compile new file mode 100644 index 0000000..2745ad2 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_hdl.compile @@ -0,0 +1,9 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ./fuse_ctrl_out_common.compile +incdir: + - . +src: + - src/fuse_ctrl_out_if.sv + - src/fuse_ctrl_out_monitor_bfm.sv + - src/fuse_ctrl_out_driver_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_hvl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_hvl.compile new file mode 100644 index 0000000..5562a20 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_hvl.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ./fuse_ctrl_out_common.compile +incdir: + - . +src: + - fuse_ctrl_out_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_pkg.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_pkg.sv new file mode 100644 index 0000000..afb8df9 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_pkg.sv @@ -0,0 +1,91 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - + +// - +// - +// - + +// - +// - +// - + +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_out_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg_hdl::*; + import uvmf_base_pkg::*; + import fuse_ctrl_out_pkg_hdl::*; + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + `include "src/fuse_ctrl_out_macros.svh" + + export fuse_ctrl_out_pkg_hdl::*; + + + + // Parameters defined as HVL parameters + + `include "src/fuse_ctrl_out_typedefs.svh" + `include "src/fuse_ctrl_out_transaction.svh" + + `include "src/fuse_ctrl_out_configuration.svh" + `include "src/fuse_ctrl_out_driver.svh" + `include "src/fuse_ctrl_out_monitor.svh" + + `include "src/fuse_ctrl_out_transaction_coverage.svh" + `include "src/fuse_ctrl_out_sequence_base.svh" + `include "src/fuse_ctrl_out_random_sequence.svh" + + `include "src/fuse_ctrl_out_responder_sequence.svh" + `include "src/fuse_ctrl_out2reg_adapter.svh" + + `include "src/fuse_ctrl_out_agent.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new interface sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the interface package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_pkg.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_pkg.vinfo new file mode 100644 index 0000000..4f08c9e --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_pkg.vinfo @@ -0,0 +1,4 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use fuse_ctrl_out_pkg_hdl.vinfo ++incdir+@vinfodir +fuse_ctrl_out_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_pkg_hdl.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_pkg_hdl.sv new file mode 100644 index 0000000..f90777a --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_pkg_hdl.sv @@ -0,0 +1,52 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that needs to be compiled and synthesized +// for running on Veloce. +// +// CONTAINS: +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_out_pkg_hdl; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HDL parameters + + `include "src/fuse_ctrl_out_typedefs_hdl.svh" + `include "src/fuse_ctrl_out_macros.svh" + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_pkg_hdl.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_pkg_hdl.vinfo new file mode 100644 index 0000000..c55df62 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_pkg_hdl.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +fuse_ctrl_out_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_pkg_sve.F b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_pkg_sve.F new file mode 100644 index 0000000..94ccd9b --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_pkg_sve.F @@ -0,0 +1,10 @@ +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + ++incdir+. +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_filelist_hdl.f +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_filelist_hvl.f diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out2reg_adapter.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out2reg_adapter.svh new file mode 100644 index 0000000..3d1523d --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out2reg_adapter.svh @@ -0,0 +1,137 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the UVM register adapter for the fuse_ctrl_out interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_out2reg_adapter #( + int AlertSyncOn = 3, + caliptra_otp_ctrl_pkg::lfsr_seed_t RndConstLfrSeed = caliptra_otp_ctrl_pkg::RndCnstLfsrSeedDefault, + caliptra_otp_ctrl_pkg::lfsr_perm_t RndCnstLfsrPerm = caliptra_otp_ctrl_pkg::RndCnstLfsrPermDefault, + string MemInitFile = "" + ) extends uvm_reg_adapter; + + `uvm_object_param_utils( fuse_ctrl_out2reg_adapter #( + AlertSyncOn, + RndConstLfrSeed, + RndCnstLfsrPerm, + MemInitFile + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //-------------------------------------------------------------------- + // new + //-------------------------------------------------------------------- + function new (string name = "fuse_ctrl_out2reg_adapter" ); + super.new(name); + // pragma uvmf custom new begin + // UVMF_CHANGE_ME : Configure the adapter regarding byte enables and provides response. + + // Does the protocol the Agent is modeling support byte enables? + // 0 = NO + // 1 = YES + supports_byte_enable = 0; + + // Does the Agent's Driver provide separate response sequence items? + // i.e. Does the driver call seq_item_port.put() + // and do the sequences call get_response()? + // 0 = NO + // 1 = YES + provides_responses = 0; + // pragma uvmf custom new end + + endfunction: new + + //-------------------------------------------------------------------- + // reg2bus + //-------------------------------------------------------------------- + virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw); + + fuse_ctrl_out_transaction #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) trans_h = fuse_ctrl_out_transaction #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + )::type_id::create("trans_h"); + + // pragma uvmf custom reg2bus begin + // UVMF_CHANGE_ME : Fill in the reg2bus adapter mapping registe fields to protocol fields. + + //Adapt the following for your sequence item type + // trans_h.op = (rw.kind == UVM_READ) ? WB_READ : WB_WRITE; + //Copy over address + // trans_h.addr = rw.addr; + //Copy over write data + // trans_h.data = rw.data; + + // pragma uvmf custom reg2bus end + + // Return the adapted transaction + return trans_h; + + endfunction: reg2bus + + //-------------------------------------------------------------------- + // bus2reg + //-------------------------------------------------------------------- + virtual function void bus2reg(uvm_sequence_item bus_item, + ref uvm_reg_bus_op rw); + fuse_ctrl_out_transaction #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) trans_h; + if (!$cast(trans_h, bus_item)) begin + `uvm_fatal("ADAPT","Provided bus_item is not of the correct type") + return; + end + // pragma uvmf custom bus2reg begin + // UVMF_CHANGE_ME : Fill in the bus2reg adapter mapping protocol fields to register fields. + //Adapt the following for your sequence item type + //Copy over instruction type + // rw.kind = (trans_h.op == WB_WRITE) ? UVM_WRITE : UVM_READ; + //Copy over address + // rw.addr = trans_h.addr; + //Copy over read data + // rw.data = trans_h.data; + //Check for errors on the bus and return UVM_NOT_OK if there is an error + // rw.status = UVM_IS_OK; + // pragma uvmf custom bus2reg end + + endfunction: bus2reg + +endclass : fuse_ctrl_out2reg_adapter + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_agent.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_agent.svh new file mode 100644 index 0000000..52705d1 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_agent.svh @@ -0,0 +1,102 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: Protocol specific agent class definition +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_out_agent #( + int AlertSyncOn = 3, + caliptra_otp_ctrl_pkg::lfsr_seed_t RndConstLfrSeed = caliptra_otp_ctrl_pkg::RndCnstLfsrSeedDefault, + caliptra_otp_ctrl_pkg::lfsr_perm_t RndCnstLfsrPerm = caliptra_otp_ctrl_pkg::RndCnstLfsrPermDefault, + string MemInitFile = "" + ) extends uvmf_parameterized_agent #( + .CONFIG_T(fuse_ctrl_out_configuration #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + )), + .DRIVER_T(fuse_ctrl_out_driver #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + )), + .MONITOR_T(fuse_ctrl_out_monitor #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + )), + .COVERAGE_T(fuse_ctrl_out_transaction_coverage #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + )), + .TRANS_T(fuse_ctrl_out_transaction #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + )) + ); + + `uvm_component_param_utils( fuse_ctrl_out_agent #( + AlertSyncOn, + RndConstLfrSeed, + RndCnstLfsrPerm, + MemInitFile + )) + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** + // FUNCTION: build_phase + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + if (configuration.active_passive == ACTIVE) begin + // Place sequencer handle into configuration object + // so that it may be retrieved from configuration + // rather than using uvm_config_db + configuration.sequencer = this.sequencer; + end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_configuration.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_configuration.svh new file mode 100644 index 0000000..4fdfc70 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_configuration.svh @@ -0,0 +1,233 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class contains all variables and functions used +// to configure the fuse_ctrl_out agent and its bfm's. It gets the +// bfm's from the uvm_config_db for use by the agent. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_out_configuration #( + int AlertSyncOn = 3, + caliptra_otp_ctrl_pkg::lfsr_seed_t RndConstLfrSeed = caliptra_otp_ctrl_pkg::RndCnstLfsrSeedDefault, + caliptra_otp_ctrl_pkg::lfsr_perm_t RndCnstLfsrPerm = caliptra_otp_ctrl_pkg::RndCnstLfsrPermDefault, + string MemInitFile = "" + ) extends uvmf_parameterized_agent_configuration_base #( + .DRIVER_BFM_BIND_T(virtual fuse_ctrl_out_driver_bfm #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + )), + .MONITOR_BFM_BIND_T( virtual fuse_ctrl_out_monitor_bfm #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ))); + + `uvm_object_param_utils( fuse_ctrl_out_configuration #( + AlertSyncOn, + RndConstLfrSeed, + RndCnstLfsrPerm, + MemInitFile + )) + + + // Sequencer handle populated by agent + uvm_sequencer #(fuse_ctrl_out_transaction #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) ) sequencer; + + //Constraints for the configuration variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + covergroup fuse_ctrl_out_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + // pragma uvmf custom covergroup end + endgroup + + //******************************************************************* + //******************************************************************* + // Structure used to pass configuration variables to monitor and driver BFM's. + // Use to_struct function to pack variables into structure. + // Use from_struct function to unpack variables from structure. + // This structure is defined in fuse_ctrl_out_macros.svh + `fuse_ctrl_out_CONFIGURATION_STRUCT + fuse_ctrl_out_configuration_s fuse_ctrl_out_configuration_struct; + //******************************************************************* + // FUNCTION: to_struct() + // This function packs variables into a fuse_ctrl_out_configuration_s + // structure. The function returns the handle to the fuse_ctrl_out_configuration_struct. + // This function is defined in fuse_ctrl_out_macros.svh + `fuse_ctrl_out_CONFIGURATION_TO_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_struct() + // This function unpacks the struct provided as an argument into + // variables of this class. + // This function is defined in fuse_ctrl_out_macros.svh + `fuse_ctrl_out_CONFIGURATION_FROM_STRUCT_FUNCTION + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + // Construct the covergroup for this configuration class + fuse_ctrl_out_configuration_cg = new; + endfunction + + // **************************************************************************** + // FUNCTION: post_randomize() + // This function is automatically called after the randomize() function + // is executed. + // + function void post_randomize(); + super.post_randomize(); + fuse_ctrl_out_configuration_cg.sample(); + endfunction + + // **************************************************************************** + // FUNCTION: initialize + // This function causes the configuration to retrieve + // its virtual interface handle from the uvm_config_db. + // This function also makes itself available to its + // agent through the uvm_config_db. + // + // ARGUMENTS: + // uvmf_active_passive_t activity: + // This argument identifies the simulation level + // as either BLOCK, CHIP, SIMULATION, etc. + // + // AGENT_PATH: + // This argument identifies the path to this + // configurations agent. This configuration + // makes itself available to the agent specified + // by agent_path by placing itself into the + // uvm_config_db. + // + // INTERFACE_NAME: + // This argument identifies the string name of + // this configurations BFM's. This string + // name is used to retrieve the driver and + // monitor BFM from the uvm_config_db. + // + virtual function void initialize(uvmf_active_passive_t activity, + string agent_path, + string interface_name); + + super.initialize( activity, agent_path, interface_name); + // The covergroup is given the same name as the interface + fuse_ctrl_out_configuration_cg.set_inst_name(interface_name); + + // This configuration places itself into the uvm_config_db for the agent, identified by the agent_path variable, to retrieve. + uvm_config_db #( fuse_ctrl_out_configuration #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) + )::set( null ,agent_path,UVMF_AGENT_CONFIG, this ); + + // This configuration also places itself in the config db using the same identifier used by the interface. This allows users to access + // configuration variables and the interface through the bfm api class rather than directly accessing the BFM. This is useful for + // accessingthe BFM when using Veloce + uvm_config_db #( fuse_ctrl_out_configuration #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) + )::set( null ,UVMF_CONFIGURATIONS, interface_name, this ); + + fuse_ctrl_out_configuration_cg.set_inst_name($sformatf("fuse_ctrl_out_configuration_cg_%s",get_full_name())); + +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. + `uvm_info("CFG", + $psprintf("The agent at '%s' is using interface named %s has the following parameters: AlertSyncOn=%x RndConstLfrSeed=%x RndCnstLfsrPerm=%x MemInitFile=%x ", agent_path, interface_name, AlertSyncOn ,RndConstLfrSeed ,RndCnstLfsrPerm ,MemInitFile ), + UVM_DEBUG) + + // pragma uvmf custom initialize begin + // This controls whether or not the agent returns a transaction handle in the driver when calling + // item_done() back into the sequencer or not. If set to 1, a transaction is sent back which means + // the sequence on the other end must use the get_response() part of the driver/sequence API. If + // this doesn't occur, there will eventually be response_queue overflow errors during the test. + return_transaction_response = 1'b0; + + // pragma uvmf custom initialize end + + endfunction + + // **************************************************************************** + // TASK: wait_for_reset + // *[Required]* Blocks until reset is released. The wait_for_reset operation is performed + // by a task in the monitor bfm. + virtual task wait_for_reset(); + monitor_bfm.wait_for_reset(); + endtask + + // **************************************************************************** + // TASK: wait_for_num_clocks + // *[Required]* Blocks until specified number of clocks have elapsed. The wait_for_num_clocks + // operation is performed by a task in the monitor bfm. + virtual task wait_for_num_clocks(int clocks); + monitor_bfm.wait_for_num_clocks(clocks); + endtask + + // **************************************************************************** + // FUNCTION : convert2string() + // This function is used to convert variables in this class into a string for log messaging. + // + virtual function string convert2string (); + // pragma uvmf custom convert2string begin + return $sformatf(""); + // pragma uvmf custom convert2string end + endfunction + + // **************************************************************************** + // FUNCTION: get_sequencer + function uvm_sequencer #(fuse_ctrl_out_transaction#( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + )) get_sequencer(); + return sequencer; + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_driver.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_driver.svh new file mode 100644 index 0000000..fcb748e --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_driver.svh @@ -0,0 +1,135 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class passes transactions between the sequencer +// and the BFM driver interface. It accesses the driver BFM +// through the bfm handle. This driver +// passes transactions to the driver BFM through the access +// task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_out_driver #( + int AlertSyncOn = 3, + caliptra_otp_ctrl_pkg::lfsr_seed_t RndConstLfrSeed = caliptra_otp_ctrl_pkg::RndCnstLfsrSeedDefault, + caliptra_otp_ctrl_pkg::lfsr_perm_t RndCnstLfsrPerm = caliptra_otp_ctrl_pkg::RndCnstLfsrPermDefault, + string MemInitFile = "" + ) extends uvmf_driver_base #( + .CONFIG_T(fuse_ctrl_out_configuration #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) ), + .BFM_BIND_T(virtual fuse_ctrl_out_driver_bfm #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) ), + .REQ(fuse_ctrl_out_transaction #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) ), + .RSP(fuse_ctrl_out_transaction #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) )); + + `uvm_component_param_utils( fuse_ctrl_out_driver #( + AlertSyncOn, + RndConstLfrSeed, + RndCnstLfsrPerm, + MemInitFile + )) +//******************************************************************* +// Macros that define structs located in fuse_ctrl_out_macros.svh +//******************************************************************* +// Initiator macro used by fuse_ctrl_out_driver and fuse_ctrl_out_driver_bfm +// to communicate initiator driven data to fuse_ctrl_out_driver_bfm. +`fuse_ctrl_out_INITIATOR_STRUCT + fuse_ctrl_out_initiator_s fuse_ctrl_out_initiator_struct; +//******************************************************************* +// Responder macro used by fuse_ctrl_out_driver and fuse_ctrl_out_driver_bfm +// to communicate Responder driven data to fuse_ctrl_out_driver_bfm. +`fuse_ctrl_out_RESPONDER_STRUCT + fuse_ctrl_out_responder_s fuse_ctrl_out_responder_struct; + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent=null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the driver BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// driver BFM. This allows the driver BFM to call tasks and function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// **************************************************************************** +// This task is called by the run_phase in uvmf_driver_base. + virtual task access( inout REQ txn ); +// pragma uvmf custom access begin + if (configuration.initiator_responder==RESPONDER) begin + // Complete current transfer and wait for next transfer + bfm.respond_and_wait_for_next_transfer( + fuse_ctrl_out_initiator_struct, + txn.to_responder_struct() + ); + // Unpack information about initiated transfer received by this responder + txn.from_initiator_struct(fuse_ctrl_out_initiator_struct); + end else begin + // Initiate a transfer and get response + bfm.initiate_and_get_response( + txn.to_initiator_struct(), + fuse_ctrl_out_responder_struct + ); + // Unpack transfer response information received by this initiator + txn.from_responder_struct(fuse_ctrl_out_responder_struct); + end +// pragma uvmf custom access end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_driver_bfm.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_driver_bfm.sv new file mode 100644 index 0000000..9e53a99 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_driver_bfm.sv @@ -0,0 +1,351 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This interface performs the fuse_ctrl_out signal driving. It is +// accessed by the uvm fuse_ctrl_out driver through a virtual interface +// handle in the fuse_ctrl_out configuration. It drives the singals passed +// in through the port connection named bus of type fuse_ctrl_out_if. +// +// Input signals from the fuse_ctrl_out_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// This bfm drives signals with a _o suffix. These signals +// are driven onto signals within fuse_ctrl_out_if based on INITIATOR/RESPONDER and/or +// ARBITRATION/GRANT status. +// +// The output signal connections are as follows: +// signal_o -> bus.signal +// +// +// Interface functions and tasks used by UVM components: +// +// configure: +// This function gets configuration attributes from the +// UVM driver to set any required BFM configuration +// variables such as 'initiator_responder'. +// +// initiate_and_get_response: +// This task is used to perform signaling activity for initiating +// a protocol transfer. The task initiates the transfer, using +// input data from the initiator struct. Then the task captures +// response data, placing the data into the response struct. +// The response struct is returned to the driver class. +// +// respond_and_wait_for_next_transfer: +// This task is used to complete a current transfer as a responder +// and then wait for the initiator to start the next transfer. +// The task uses data in the responder struct to drive protocol +// signals to complete the transfer. The task then waits for +// the next transfer. Once the next transfer begins, data from +// the initiator is placed into the initiator struct and sent +// to the responder sequence for processing to determine +// what data to respond with. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_out_pkg_hdl::*; +`include "src/fuse_ctrl_out_macros.svh" + +interface fuse_ctrl_out_driver_bfm #( + int AlertSyncOn = 3, + caliptra_otp_ctrl_pkg::lfsr_seed_t RndConstLfrSeed = caliptra_otp_ctrl_pkg::RndCnstLfsrSeedDefault, + caliptra_otp_ctrl_pkg::lfsr_perm_t RndCnstLfsrPerm = caliptra_otp_ctrl_pkg::RndCnstLfsrPermDefault, + string MemInitFile = "" + ) + (fuse_ctrl_out_if bus); + // The following pragma and additional ones in-lined further below are for running this BFM on Veloce + // pragma attribute fuse_ctrl_out_driver_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: AlertSyncOn=%x RndConstLfrSeed=%x RndCnstLfsrPerm=%x MemInitFile=%x ", AlertSyncOn,RndConstLfrSeed,RndCnstLfsrPerm,MemInitFile), + UVM_DEBUG) +end +`endif + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + tri clk_i_i; + tri rst_ni_i; + + // Signal list (all signals are capable of being inputs and outputs for the sake + // of supporting both INITIATOR and RESPONDER mode operation. Expectation is that + // directionality in the config file was from the point-of-view of the INITIATOR + + // INITIATOR mode input signals + tri [$bits(edn_pkg::edn_req_t)-1:0] edn_o_i; + reg [$bits(edn_pkg::edn_req_t)-1:0] edn_o_o = 'bz; + tri intr_otp_operation_done_o_i; + reg intr_otp_operation_done_o_o = 'bz; + tri intr_otp_error_o_i; + reg intr_otp_error_o_o = 'bz; + tri [ast_pkg::NumAlerts * $bits(caliptra_prim_alert_pkg::alert_tx_t)-1:0] alert_tx_o_i; + reg [ast_pkg::NumAlerts * $bits(caliptra_prim_alert_pkg::alert_tx_t)-1:0] alert_tx_o_o = 'bz; + tri [7:0] otp_obs_o_i; + reg [7:0] otp_obs_o_o = 'bz; + tri [$bits(caliptra_otp_ctrl_pkg::otp_ast_req_t)-1:0] otp_ast_pwr_seq_o_i; + reg [$bits(caliptra_otp_ctrl_pkg::otp_ast_req_t)-1:0] otp_ast_pwr_seq_o_o = 'bz; + tri [$bits(caliptra_otp_ctrl_part_pkg::otp_broadcast_t)-1:0] otp_broadcast_o_i; + reg [$bits(caliptra_otp_ctrl_part_pkg::otp_broadcast_t)-1:0] otp_broadcast_o_o = 'bz; + tri [caliptra_otp_ctrl_pkg::OtpTestVectWidth-1:0] cio_test_o_i; + reg [caliptra_otp_ctrl_pkg::OtpTestVectWidth-1:0] cio_test_o_o = 'bz; + tri [caliptra_otp_ctrl_pkg::OtpTestVectWidth-1:0] cio_test_en_o_i; + reg [caliptra_otp_ctrl_pkg::OtpTestVectWidth-1:0] cio_test_en_o_o = 'bz; + + // INITIATOR mode output signals + + // Bi-directional signals + + + assign clk_i_i = bus.clk_i; + assign rst_ni_i = bus.rst_ni; + + // These are signals marked as 'input' by the config file, but the signals will be + // driven by this BFM if put into RESPONDER mode (flipping all signal directions around) + assign edn_o_i = bus.edn_o; + assign bus.edn_o = (initiator_responder == RESPONDER) ? edn_o_o : 'bz; + assign intr_otp_operation_done_o_i = bus.intr_otp_operation_done_o; + assign bus.intr_otp_operation_done_o = (initiator_responder == RESPONDER) ? intr_otp_operation_done_o_o : 'bz; + assign intr_otp_error_o_i = bus.intr_otp_error_o; + assign bus.intr_otp_error_o = (initiator_responder == RESPONDER) ? intr_otp_error_o_o : 'bz; + assign alert_tx_o_i = bus.alert_tx_o; + assign bus.alert_tx_o = (initiator_responder == RESPONDER) ? alert_tx_o_o : 'bz; + assign otp_obs_o_i = bus.otp_obs_o; + assign bus.otp_obs_o = (initiator_responder == RESPONDER) ? otp_obs_o_o : 'bz; + assign otp_ast_pwr_seq_o_i = bus.otp_ast_pwr_seq_o; + assign bus.otp_ast_pwr_seq_o = (initiator_responder == RESPONDER) ? otp_ast_pwr_seq_o_o : 'bz; + assign otp_broadcast_o_i = bus.otp_broadcast_o; + assign bus.otp_broadcast_o = (initiator_responder == RESPONDER) ? otp_broadcast_o_o : 'bz; + assign cio_test_o_i = bus.cio_test_o; + assign bus.cio_test_o = (initiator_responder == RESPONDER) ? cio_test_o_o : 'bz; + assign cio_test_en_o_i = bus.cio_test_en_o; + assign bus.cio_test_en_o = (initiator_responder == RESPONDER) ? cio_test_en_o_o : 'bz; + + + // These are signals marked as 'output' by the config file, but the outputs will + // not be driven by this BFM unless placed in INITIATOR mode. + + // Proxy handle to UVM driver + fuse_ctrl_out_pkg::fuse_ctrl_out_driver #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) proxy; + // pragma tbx oneway proxy.my_function_name_in_uvm_driver + + // **************************************************************************** + // **************************************************************************** + // Macros that define structs located in fuse_ctrl_out_macros.svh + // **************************************************************************** + // Struct for passing configuration data from fuse_ctrl_out_driver to this BFM + // **************************************************************************** + `fuse_ctrl_out_CONFIGURATION_STRUCT + // **************************************************************************** + // Structs for INITIATOR and RESPONDER data flow + //******************************************************************* + // Initiator macro used by fuse_ctrl_out_driver and fuse_ctrl_out_driver_bfm + // to communicate initiator driven data to fuse_ctrl_out_driver_bfm. + `fuse_ctrl_out_INITIATOR_STRUCT + fuse_ctrl_out_initiator_s initiator_struct; + // Responder macro used by fuse_ctrl_out_driver and fuse_ctrl_out_driver_bfm + // to communicate Responder driven data to fuse_ctrl_out_driver_bfm. + `fuse_ctrl_out_RESPONDER_STRUCT + fuse_ctrl_out_responder_s responder_struct; + + // **************************************************************************** +// pragma uvmf custom reset_condition_and_response begin + // Always block used to return signals to reset value upon assertion of reset + always @( negedge rst_ni_i ) + begin + // RESPONDER mode output signals + edn_o_o <= 'bz; + intr_otp_operation_done_o_o <= 'bz; + intr_otp_error_o_o <= 'bz; + alert_tx_o_o <= 'bz; + otp_obs_o_o <= 'bz; + otp_ast_pwr_seq_o_o <= 'bz; + otp_broadcast_o_o <= 'bz; + cio_test_o_o <= 'bz; + cio_test_en_o_o <= 'bz; + // INITIATOR mode output signals + // Bi-directional signals + + end +// pragma uvmf custom reset_condition_and_response end + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the driver BFM. It is called by the driver within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the driver BFM needs to be aware of the new configuration + // variables. + // + + function void configure(fuse_ctrl_out_configuration_s fuse_ctrl_out_configuration_arg); // pragma tbx xtf + initiator_responder = fuse_ctrl_out_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + +// pragma uvmf custom initiate_and_get_response begin +// **************************************************************************** +// UVMF_CHANGE_ME +// This task is used by an initator. The task first initiates a transfer then +// waits for the responder to complete the transfer. + task initiate_and_get_response( + // This argument passes transaction variables used by an initiator + // to perform the initial part of a protocol transfer. The values + // come from a sequence item created in a sequence. + input fuse_ctrl_out_initiator_s fuse_ctrl_out_initiator_struct, + // This argument is used to send data received from the responder + // back to the sequence item. The sequence item is returned to the sequence. + output fuse_ctrl_out_responder_s fuse_ctrl_out_responder_struct + );// pragma tbx xtf + // + // Members within the fuse_ctrl_out_initiator_struct: + // pwrmgr_pkg::pwr_otp_rsp_t pwr_otp_o ; + // Members within the fuse_ctrl_out_responder_struct: + // pwrmgr_pkg::pwr_otp_rsp_t pwr_otp_o ; + initiator_struct = fuse_ctrl_out_initiator_struct; + // + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clk_i_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available initiator input and inout signals listed. + // Initiator input signals + // fuse_ctrl_out_responder_struct.xyz = edn_o_i; // [$bits(edn_pkg::edn_req_t)-1:0] + // fuse_ctrl_out_responder_struct.xyz = intr_otp_operation_done_o_i; // + // fuse_ctrl_out_responder_struct.xyz = intr_otp_error_o_i; // + // fuse_ctrl_out_responder_struct.xyz = alert_tx_o_i; // [ast_pkg::NumAlerts * $bits(caliptra_prim_alert_pkg::alert_tx_t)-1:0] + // fuse_ctrl_out_responder_struct.xyz = otp_obs_o_i; // [7:0] + // fuse_ctrl_out_responder_struct.xyz = otp_ast_pwr_seq_o_i; // [$bits(caliptra_otp_ctrl_pkg::otp_ast_req_t)-1:0] + // fuse_ctrl_out_responder_struct.xyz = otp_broadcast_o_i; // [$bits(caliptra_otp_ctrl_part_pkg::otp_broadcast_t)-1:0] + // fuse_ctrl_out_responder_struct.xyz = cio_test_o_i; // [caliptra_otp_ctrl_pkg::OtpTestVectWidth-1:0] + // fuse_ctrl_out_responder_struct.xyz = cio_test_en_o_i; // [caliptra_otp_ctrl_pkg::OtpTestVectWidth-1:0] + // Initiator inout signals + // How to assign a signal from an initiator struct member named xyz. + // All available initiator output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Initiator output signals + // Initiator inout signals + // Initiate a transfer using the data received. + @(posedge clk_i_i); + @(posedge clk_i_i); + // Wait for the responder to complete the transfer then place the responder data into + // fuse_ctrl_out_responder_struct. + @(posedge clk_i_i); + @(posedge clk_i_i); + responder_struct = fuse_ctrl_out_responder_struct; + endtask +// pragma uvmf custom initiate_and_get_response end + +// pragma uvmf custom respond_and_wait_for_next_transfer begin +// **************************************************************************** +// The first_transfer variable is used to prevent completing a transfer in the +// first call to this task. For the first call to this task, there is not +// current transfer to complete. +bit first_transfer=1; + +// UVMF_CHANGE_ME +// This task is used by a responder. The task first completes the current +// transfer in progress then waits for the initiator to start the next transfer. + task respond_and_wait_for_next_transfer( + // This argument is used to send data received from the initiator + // back to the sequence item. The sequence determines how to respond. + output fuse_ctrl_out_initiator_s fuse_ctrl_out_initiator_struct, + // This argument passes transaction variables used by a responder + // to complete a protocol transfer. The values come from a sequence item. + input fuse_ctrl_out_responder_s fuse_ctrl_out_responder_struct + );// pragma tbx xtf + // Variables within the fuse_ctrl_out_initiator_struct: + // pwrmgr_pkg::pwr_otp_rsp_t pwr_otp_o ; + // Variables within the fuse_ctrl_out_responder_struct: + // pwrmgr_pkg::pwr_otp_rsp_t pwr_otp_o ; + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clk_i_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available responder input and inout signals listed. + // Responder input signals + // Responder inout signals + // How to assign a signal, named xyz, from an initiator struct member. + // All available responder output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Responder output signals + // edn_o_o <= fuse_ctrl_out_initiator_struct.xyz; // [$bits(edn_pkg::edn_req_t)-1:0] + // intr_otp_operation_done_o_o <= fuse_ctrl_out_initiator_struct.xyz; // + // intr_otp_error_o_o <= fuse_ctrl_out_initiator_struct.xyz; // + // alert_tx_o_o <= fuse_ctrl_out_initiator_struct.xyz; // [ast_pkg::NumAlerts * $bits(caliptra_prim_alert_pkg::alert_tx_t)-1:0] + // otp_obs_o_o <= fuse_ctrl_out_initiator_struct.xyz; // [7:0] + // otp_ast_pwr_seq_o_o <= fuse_ctrl_out_initiator_struct.xyz; // [$bits(caliptra_otp_ctrl_pkg::otp_ast_req_t)-1:0] + // otp_broadcast_o_o <= fuse_ctrl_out_initiator_struct.xyz; // [$bits(caliptra_otp_ctrl_part_pkg::otp_broadcast_t)-1:0] + // cio_test_o_o <= fuse_ctrl_out_initiator_struct.xyz; // [caliptra_otp_ctrl_pkg::OtpTestVectWidth-1:0] + // cio_test_en_o_o <= fuse_ctrl_out_initiator_struct.xyz; // [caliptra_otp_ctrl_pkg::OtpTestVectWidth-1:0] + // Responder inout signals + + @(posedge clk_i_i); + if (!first_transfer) begin + // Perform transfer response here. + // Reply using data recieved in the fuse_ctrl_out_responder_struct. + @(posedge clk_i_i); + // Reply using data recieved in the transaction handle. + @(posedge clk_i_i); + end + // Wait for next transfer then gather info from intiator about the transfer. + // Place the data into the fuse_ctrl_out_initiator_struct. + @(posedge clk_i_i); + @(posedge clk_i_i); + first_transfer = 0; + endtask +// pragma uvmf custom respond_and_wait_for_next_transfer end + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_if.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_if.sv new file mode 100644 index 0000000..aeb916c --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_if.sv @@ -0,0 +1,123 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface contains the fuse_ctrl_out interface signals. +// It is instantiated once per fuse_ctrl_out bus. Bus Functional Models, +// BFM's named fuse_ctrl_out_driver_bfm, are used to drive signals on the bus. +// BFM's named fuse_ctrl_out_monitor_bfm are used to monitor signals on the +// bus. This interface signal bundle is passed in the port list of +// the BFM in order to give the BFM access to the signals in this +// interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// This template can be used to connect a DUT to these signals +// +// .dut_signal_port(fuse_ctrl_out_bus.edn_o), // Agent input +// .dut_signal_port(fuse_ctrl_out_bus.intr_otp_operation_done_o), // Agent input +// .dut_signal_port(fuse_ctrl_out_bus.intr_otp_error_o), // Agent input +// .dut_signal_port(fuse_ctrl_out_bus.alert_tx_o), // Agent input +// .dut_signal_port(fuse_ctrl_out_bus.otp_obs_o), // Agent input +// .dut_signal_port(fuse_ctrl_out_bus.otp_ast_pwr_seq_o), // Agent input +// .dut_signal_port(fuse_ctrl_out_bus.otp_broadcast_o), // Agent input +// .dut_signal_port(fuse_ctrl_out_bus.cio_test_o), // Agent input +// .dut_signal_port(fuse_ctrl_out_bus.cio_test_en_o), // Agent input + +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_out_pkg_hdl::*; + +interface fuse_ctrl_out_if #( + int AlertSyncOn = 3, + caliptra_otp_ctrl_pkg::lfsr_seed_t RndConstLfrSeed = caliptra_otp_ctrl_pkg::RndCnstLfsrSeedDefault, + caliptra_otp_ctrl_pkg::lfsr_perm_t RndCnstLfsrPerm = caliptra_otp_ctrl_pkg::RndCnstLfsrPermDefault, + string MemInitFile = "" + ) + + ( + input tri clk_i, + input tri rst_ni, + inout tri [$bits(edn_pkg::edn_req_t)-1:0] edn_o, + inout tri intr_otp_operation_done_o, + inout tri intr_otp_error_o, + inout tri [ast_pkg::NumAlerts * $bits(caliptra_prim_alert_pkg::alert_tx_t)-1:0] alert_tx_o, + inout tri [7:0] otp_obs_o, + inout tri [$bits(caliptra_otp_ctrl_pkg::otp_ast_req_t)-1:0] otp_ast_pwr_seq_o, + inout tri [$bits(caliptra_otp_ctrl_part_pkg::otp_broadcast_t)-1:0] otp_broadcast_o, + inout tri [caliptra_otp_ctrl_pkg::OtpTestVectWidth-1:0] cio_test_o, + inout tri [caliptra_otp_ctrl_pkg::OtpTestVectWidth-1:0] cio_test_en_o + ); + +modport monitor_port + ( + input clk_i, + input rst_ni, + input edn_o, + input intr_otp_operation_done_o, + input intr_otp_error_o, + input alert_tx_o, + input otp_obs_o, + input otp_ast_pwr_seq_o, + input otp_broadcast_o, + input cio_test_o, + input cio_test_en_o + ); + +modport initiator_port + ( + input clk_i, + input rst_ni, + input edn_o, + input intr_otp_operation_done_o, + input intr_otp_error_o, + input alert_tx_o, + input otp_obs_o, + input otp_ast_pwr_seq_o, + input otp_broadcast_o, + input cio_test_o, + input cio_test_en_o + ); + +modport responder_port + ( + input clk_i, + input rst_ni, + output edn_o, + output intr_otp_operation_done_o, + output intr_otp_error_o, + output alert_tx_o, + output otp_obs_o, + output otp_ast_pwr_seq_o, + output otp_broadcast_o, + output cio_test_o, + output cio_test_en_o + ); + + +// pragma uvmf custom interface_item_additional begin +// pragma uvmf custom interface_item_additional end + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_infact_coverage_strategy.csv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_infact_coverage_strategy.csv new file mode 100644 index 0000000..1c218e1 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_infact_coverage_strategy.csv @@ -0,0 +1,6 @@ +Global +auto_bin_max, 64 + +Name,Type,Include +rand_fields,coverpoint,=rand *.** + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_macros.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_macros.svh new file mode 100644 index 0000000..3002819 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_macros.svh @@ -0,0 +1,135 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains macros used with the fuse_ctrl_out package. +// These macros include packed struct definitions. These structs are +// used to pass data between classes, hvl, and BFM's, hdl. Use of +// structs are more efficient and simpler to modify. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_struct +// and from_struct methods defined in the macros below that are used in +// the fuse_ctrl_out_configuration class. +// + `define fuse_ctrl_out_CONFIGURATION_STRUCT \ +typedef struct packed { \ + uvmf_active_passive_t active_passive; \ + uvmf_initiator_responder_t initiator_responder; \ + } fuse_ctrl_out_configuration_s; + + `define fuse_ctrl_out_CONFIGURATION_TO_STRUCT_FUNCTION \ + virtual function fuse_ctrl_out_configuration_s to_struct();\ + fuse_ctrl_out_configuration_struct = \ + {\ + this.active_passive,\ + this.initiator_responder\ + };\ + return ( fuse_ctrl_out_configuration_struct );\ + endfunction + + `define fuse_ctrl_out_CONFIGURATION_FROM_STRUCT_FUNCTION \ + virtual function void from_struct(fuse_ctrl_out_configuration_s fuse_ctrl_out_configuration_struct);\ + {\ + this.active_passive,\ + this.initiator_responder \ + } = fuse_ctrl_out_configuration_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_monitor_struct +// and from_monitor_struct methods of the fuse_ctrl_out_transaction class. +// + `define fuse_ctrl_out_MONITOR_STRUCT typedef struct packed { \ + pwrmgr_pkg::pwr_otp_rsp_t pwr_otp_o ; \ + } fuse_ctrl_out_monitor_s; + + `define fuse_ctrl_out_TO_MONITOR_STRUCT_FUNCTION \ + virtual function fuse_ctrl_out_monitor_s to_monitor_struct();\ + fuse_ctrl_out_monitor_struct = \ + { \ + this.pwr_otp_o \ + };\ + return ( fuse_ctrl_out_monitor_struct);\ + endfunction\ + + `define fuse_ctrl_out_FROM_MONITOR_STRUCT_FUNCTION \ + virtual function void from_monitor_struct(fuse_ctrl_out_monitor_s fuse_ctrl_out_monitor_struct);\ + {\ + this.pwr_otp_o \ + } = fuse_ctrl_out_monitor_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_initiator_struct +// and from_initiator_struct methods of the fuse_ctrl_out_transaction class. +// Also update the comments in the driver BFM. +// + `define fuse_ctrl_out_INITIATOR_STRUCT typedef struct packed { \ + pwrmgr_pkg::pwr_otp_rsp_t pwr_otp_o ; \ + } fuse_ctrl_out_initiator_s; + + `define fuse_ctrl_out_TO_INITIATOR_STRUCT_FUNCTION \ + virtual function fuse_ctrl_out_initiator_s to_initiator_struct();\ + fuse_ctrl_out_initiator_struct = \ + {\ + this.pwr_otp_o \ + };\ + return ( fuse_ctrl_out_initiator_struct);\ + endfunction + + `define fuse_ctrl_out_FROM_INITIATOR_STRUCT_FUNCTION \ + virtual function void from_initiator_struct(fuse_ctrl_out_initiator_s fuse_ctrl_out_initiator_struct);\ + {\ + this.pwr_otp_o \ + } = fuse_ctrl_out_initiator_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_responder_struct +// and from_responder_struct methods of the fuse_ctrl_out_transaction class. +// Also update the comments in the driver BFM. +// + `define fuse_ctrl_out_RESPONDER_STRUCT typedef struct packed { \ + pwrmgr_pkg::pwr_otp_rsp_t pwr_otp_o ; \ + } fuse_ctrl_out_responder_s; + + `define fuse_ctrl_out_TO_RESPONDER_STRUCT_FUNCTION \ + virtual function fuse_ctrl_out_responder_s to_responder_struct();\ + fuse_ctrl_out_responder_struct = \ + {\ + this.pwr_otp_o \ + };\ + return ( fuse_ctrl_out_responder_struct);\ + endfunction + + `define fuse_ctrl_out_FROM_RESPONDER_STRUCT_FUNCTION \ + virtual function void from_responder_struct(fuse_ctrl_out_responder_s fuse_ctrl_out_responder_struct);\ + {\ + this.pwr_otp_o \ + } = fuse_ctrl_out_responder_struct;\ + endfunction +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_monitor.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_monitor.svh new file mode 100644 index 0000000..8cf053b --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_monitor.svh @@ -0,0 +1,126 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class receives fuse_ctrl_out transactions observed by the +// fuse_ctrl_out monitor BFM and broadcasts them through the analysis port +// on the agent. It accesses the monitor BFM through the monitor +// task. This UVM component captures transactions +// for viewing in the waveform viewer if the +// enable_transaction_viewing flag is set in the configuration. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_out_monitor #( + int AlertSyncOn = 3, + caliptra_otp_ctrl_pkg::lfsr_seed_t RndConstLfrSeed = caliptra_otp_ctrl_pkg::RndCnstLfsrSeedDefault, + caliptra_otp_ctrl_pkg::lfsr_perm_t RndCnstLfsrPerm = caliptra_otp_ctrl_pkg::RndCnstLfsrPermDefault, + string MemInitFile = "" + ) extends uvmf_monitor_base #( + .CONFIG_T(fuse_ctrl_out_configuration #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + )), + .BFM_BIND_T(virtual fuse_ctrl_out_monitor_bfm #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + )), + .TRANS_T(fuse_ctrl_out_transaction #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ))); + + `uvm_component_param_utils( fuse_ctrl_out_monitor #( + AlertSyncOn, + RndConstLfrSeed, + RndCnstLfsrPerm, + MemInitFile + )) + +// Structure used to pass data from monitor BFM to monitor class in agent. +// Use to_monitor_struct function to pack transaction variables into structure. +// Use from_monitor_struct function to unpack transaction variables from structure. +`fuse_ctrl_out_MONITOR_STRUCT + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the monitor BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// monitor BFM. This allows the monitor BFM to call the notify_transaction +// function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// *************************************************************************** + virtual task run_phase(uvm_phase phase); + // Start monitor BFM thread and don't call super.run() in order to + // override the default monitor proxy 'pull' behavior with the more + // emulation-friendly BFM 'push' approach using the notify_transaction + // function below + bfm.start_monitoring(); + endtask + +// ************************************************************************** + +// This function is called by the monitor BFM. It receives data observed by the +// monitor BFM. Data is passed using the fuse_ctrl_out_monitor_struct. + virtual function void notify_transaction(input fuse_ctrl_out_monitor_s fuse_ctrl_out_monitor_struct); + + + trans = new("trans"); + trans.from_monitor_struct(fuse_ctrl_out_monitor_struct); + trans.start_time = time_stamp; + trans.end_time = $time; + time_stamp = trans.end_time; + + analyze(trans); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_monitor_bfm.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_monitor_bfm.sv new file mode 100644 index 0000000..216a43e --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_monitor_bfm.sv @@ -0,0 +1,222 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface performs the fuse_ctrl_out signal monitoring. +// It is accessed by the uvm fuse_ctrl_out monitor through a virtual +// interface handle in the fuse_ctrl_out configuration. It monitors the +// signals passed in through the port connection named bus of +// type fuse_ctrl_out_if. +// +// Input signals from the fuse_ctrl_out_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// Interface functions and tasks used by UVM components: +// monitor(inout TRANS_T txn); +// This task receives the transaction, txn, from the +// UVM monitor and then populates variables in txn +// from values observed on bus activity. This task +// blocks until an operation on the fuse_ctrl_out bus is complete. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_out_pkg_hdl::*; +`include "src/fuse_ctrl_out_macros.svh" + + +interface fuse_ctrl_out_monitor_bfm #( + int AlertSyncOn = 3, + caliptra_otp_ctrl_pkg::lfsr_seed_t RndConstLfrSeed = caliptra_otp_ctrl_pkg::RndCnstLfsrSeedDefault, + caliptra_otp_ctrl_pkg::lfsr_perm_t RndCnstLfsrPerm = caliptra_otp_ctrl_pkg::RndCnstLfsrPermDefault, + string MemInitFile = "" + ) + ( fuse_ctrl_out_if bus ); + // The pragma below and additional ones in-lined further down are for running this BFM on Veloce + // pragma attribute fuse_ctrl_out_monitor_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: AlertSyncOn=%x RndConstLfrSeed=%x RndCnstLfsrPerm=%x MemInitFile=%x ", AlertSyncOn,RndConstLfrSeed,RndCnstLfsrPerm,MemInitFile), + UVM_DEBUG) +end +`endif + + + // Structure used to pass transaction data from monitor BFM to monitor class in agent. +`fuse_ctrl_out_MONITOR_STRUCT + fuse_ctrl_out_monitor_s fuse_ctrl_out_monitor_struct; + + // Structure used to pass configuration data from monitor class to monitor BFM. + `fuse_ctrl_out_CONFIGURATION_STRUCT + + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + tri clk_i_i; + tri rst_ni_i; + tri [$bits(edn_pkg::edn_req_t)-1:0] edn_o_i; + tri intr_otp_operation_done_o_i; + tri intr_otp_error_o_i; + tri [ast_pkg::NumAlerts * $bits(caliptra_prim_alert_pkg::alert_tx_t)-1:0] alert_tx_o_i; + tri [7:0] otp_obs_o_i; + tri [$bits(caliptra_otp_ctrl_pkg::otp_ast_req_t)-1:0] otp_ast_pwr_seq_o_i; + tri [$bits(caliptra_otp_ctrl_part_pkg::otp_broadcast_t)-1:0] otp_broadcast_o_i; + tri [caliptra_otp_ctrl_pkg::OtpTestVectWidth-1:0] cio_test_o_i; + tri [caliptra_otp_ctrl_pkg::OtpTestVectWidth-1:0] cio_test_en_o_i; + assign clk_i_i = bus.clk_i; + assign rst_ni_i = bus.rst_ni; + assign edn_o_i = bus.edn_o; + assign intr_otp_operation_done_o_i = bus.intr_otp_operation_done_o; + assign intr_otp_error_o_i = bus.intr_otp_error_o; + assign alert_tx_o_i = bus.alert_tx_o; + assign otp_obs_o_i = bus.otp_obs_o; + assign otp_ast_pwr_seq_o_i = bus.otp_ast_pwr_seq_o; + assign otp_broadcast_o_i = bus.otp_broadcast_o; + assign cio_test_o_i = bus.cio_test_o; + assign cio_test_en_o_i = bus.cio_test_en_o; + + // Proxy handle to UVM monitor + fuse_ctrl_out_pkg::fuse_ctrl_out_monitor #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) proxy; + // pragma tbx oneway proxy.notify_transaction + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + task wait_for_reset();// pragma tbx xtf + @(posedge clk_i_i) ; + do_wait_for_reset(); + endtask + + // **************************************************************************** + task do_wait_for_reset(); + // pragma uvmf custom reset_condition begin + wait ( rst_ni_i === 1 ) ; + @(posedge clk_i_i) ; + // pragma uvmf custom reset_condition end + endtask + + //****************************************************************** + + task wait_for_num_clocks(input int unsigned count); // pragma tbx xtf + @(posedge clk_i_i); + + repeat (count-1) @(posedge clk_i_i); + endtask + + //****************************************************************** + event go; + function void start_monitoring();// pragma tbx xtf + -> go; + endfunction + + // **************************************************************************** + initial begin + @go; + forever begin + @(posedge clk_i_i); + do_monitor( fuse_ctrl_out_monitor_struct ); + + + proxy.notify_transaction( fuse_ctrl_out_monitor_struct ); + + end + end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the monitor BFM. It is called by the monitor within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the monitor BFM needs to be aware of the new configuration + // variables. + // + function void configure(fuse_ctrl_out_configuration_s fuse_ctrl_out_configuration_arg); // pragma tbx xtf + initiator_responder = fuse_ctrl_out_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + + + // **************************************************************************** + + task do_monitor(output fuse_ctrl_out_monitor_s fuse_ctrl_out_monitor_struct); + // + // Available struct members: + // // fuse_ctrl_out_monitor_struct.pwr_otp_o + // // + // Reference code; + // How to wait for signal value + // while (control_signal === 1'b1) @(posedge clk_i_i); + // + // How to assign a struct member, named xyz, from a signal. + // All available input signals listed. + // fuse_ctrl_out_monitor_struct.xyz = edn_o_i; // [$bits(edn_pkg::edn_req_t)-1:0] + // fuse_ctrl_out_monitor_struct.xyz = intr_otp_operation_done_o_i; // + // fuse_ctrl_out_monitor_struct.xyz = intr_otp_error_o_i; // + // fuse_ctrl_out_monitor_struct.xyz = alert_tx_o_i; // [ast_pkg::NumAlerts * $bits(caliptra_prim_alert_pkg::alert_tx_t)-1:0] + // fuse_ctrl_out_monitor_struct.xyz = otp_obs_o_i; // [7:0] + // fuse_ctrl_out_monitor_struct.xyz = otp_ast_pwr_seq_o_i; // [$bits(caliptra_otp_ctrl_pkg::otp_ast_req_t)-1:0] + // fuse_ctrl_out_monitor_struct.xyz = otp_broadcast_o_i; // [$bits(caliptra_otp_ctrl_part_pkg::otp_broadcast_t)-1:0] + // fuse_ctrl_out_monitor_struct.xyz = cio_test_o_i; // [caliptra_otp_ctrl_pkg::OtpTestVectWidth-1:0] + // fuse_ctrl_out_monitor_struct.xyz = cio_test_en_o_i; // [caliptra_otp_ctrl_pkg::OtpTestVectWidth-1:0] + // pragma uvmf custom do_monitor begin + // UVMF_CHANGE_ME : Implement protocol monitoring. The commented reference code + // below are examples of how to capture signal values and assign them to + // structure members. All available input signals are listed. The 'while' + // code example shows how to wait for a synchronous flow control signal. This + // task should return when a complete transfer has been observed. Once this task is + // exited with captured values, it is then called again to wait for and observe + // the next transfer. One clock cycle is consumed between calls to do_monitor. + @(posedge clk_i_i); + @(posedge clk_i_i); + @(posedge clk_i_i); + @(posedge clk_i_i); + // pragma uvmf custom do_monitor end + endtask + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_random_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_random_sequence.svh new file mode 100644 index 0000000..7e0e226 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_random_sequence.svh @@ -0,0 +1,87 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This sequences randomizes the fuse_ctrl_out transaction and sends it +// to the UVM driver. +// +// This sequence constructs and randomizes a fuse_ctrl_out_transaction. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_out_random_sequence #( + int AlertSyncOn = 3, + caliptra_otp_ctrl_pkg::lfsr_seed_t RndConstLfrSeed = caliptra_otp_ctrl_pkg::RndCnstLfsrSeedDefault, + caliptra_otp_ctrl_pkg::lfsr_perm_t RndCnstLfsrPerm = caliptra_otp_ctrl_pkg::RndCnstLfsrPermDefault, + string MemInitFile = "" + ) + extends fuse_ctrl_out_sequence_base #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ); + + `uvm_object_param_utils( fuse_ctrl_out_random_sequence #( + AlertSyncOn, + RndConstLfrSeed, + RndCnstLfsrPerm, + MemInitFile + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //***************************************************************** + function new(string name = ""); + super.new(name); + endfunction: new + + // **************************************************************************** + // TASK : body() + // This task is automatically executed when this sequence is started using the + // start(sequencerHandle) task. + // + task body(); + + // Construct the transaction + req=fuse_ctrl_out_transaction#( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + )::type_id::create("req"); + start_item(req); + // Randomize the transaction + if(!req.randomize()) `uvm_fatal("SEQ", "fuse_ctrl_out_random_sequence::body()-fuse_ctrl_out_transaction randomization failed") + // Send the transaction to the fuse_ctrl_out_driver_bfm via the sequencer and fuse_ctrl_out_driver. + finish_item(req); + `uvm_info("SEQ", {"Response:",req.convert2string()},UVM_MEDIUM) + + endtask + +endclass: fuse_ctrl_out_random_sequence + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_responder_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_responder_sequence.svh new file mode 100644 index 0000000..5204741 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_responder_sequence.svh @@ -0,0 +1,83 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class can be used to provide stimulus when an interface +// has been configured to run in a responder mode. It +// will never finish by default, always going back to the driver +// and driver BFM for the next transaction with which to respond. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_out_responder_sequence #( + int AlertSyncOn = 3, + caliptra_otp_ctrl_pkg::lfsr_seed_t RndConstLfrSeed = caliptra_otp_ctrl_pkg::RndCnstLfsrSeedDefault, + caliptra_otp_ctrl_pkg::lfsr_perm_t RndCnstLfsrPerm = caliptra_otp_ctrl_pkg::RndCnstLfsrPermDefault, + string MemInitFile = "" + ) + extends fuse_ctrl_out_sequence_base #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ); + + `uvm_object_param_utils( fuse_ctrl_out_responder_sequence #( + AlertSyncOn, + RndConstLfrSeed, + RndCnstLfsrPerm, + MemInitFile + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "fuse_ctrl_out_responder_sequence"); + super.new(name); + endfunction + + task body(); + req=fuse_ctrl_out_transaction#( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + )::type_id::create("req"); + forever begin + start_item(req); + finish_item(req); + // pragma uvmf custom body begin + // UVMF_CHANGE_ME : Do something here with the resulting req item. The + // finish_item() call above will block until the req transaction is ready + // to be handled by the responder sequence. + // If this was an item that required a response, the expectation is + // that the response should be populated within this transaction now. + `uvm_info("SEQ",$sformatf("Processed txn: %s",req.convert2string()),UVM_HIGH) + // pragma uvmf custom body end + end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_sequence_base.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_sequence_base.svh new file mode 100644 index 0000000..03504c9 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_sequence_base.svh @@ -0,0 +1,140 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the class used as the base class for all sequences +// for this interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_out_sequence_base #( + int AlertSyncOn = 3, + caliptra_otp_ctrl_pkg::lfsr_seed_t RndConstLfrSeed = caliptra_otp_ctrl_pkg::RndCnstLfsrSeedDefault, + caliptra_otp_ctrl_pkg::lfsr_perm_t RndCnstLfsrPerm = caliptra_otp_ctrl_pkg::RndCnstLfsrPermDefault, + string MemInitFile = "" + ) extends uvmf_sequence_base #( + .REQ(fuse_ctrl_out_transaction #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + )), + .RSP(fuse_ctrl_out_transaction #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ))); + + `uvm_object_param_utils( fuse_ctrl_out_sequence_base #( + AlertSyncOn, + RndConstLfrSeed, + RndCnstLfsrPerm, + MemInitFile + )) + + // variables + typedef fuse_ctrl_out_transaction #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) fuse_ctrl_out_transaction_req_t; + fuse_ctrl_out_transaction_req_t req; + typedef fuse_ctrl_out_transaction #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) fuse_ctrl_out_transaction_rsp_t; + fuse_ctrl_out_transaction_rsp_t rsp; + + // Event for identifying when a response was received from the sequencer + event new_rsp; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // TASK : get_responses() + // This task recursively gets sequence item responses from the sequencer. + // + virtual task get_responses(); + fork + begin + // Block until new rsp available + get_response(rsp); + // New rsp received. Indicate to sequence using event. + ->new_rsp; + // Display the received response transaction + `uvm_info("SEQ", {"New response transaction:",rsp.convert2string()}, UVM_MEDIUM) + end + join_none + endtask + + // **************************************************************************** + // TASK : pre_body() + // This task is called automatically when start is called with call_pre_post set to 1 (default). + // By calling get_responses() within pre_body() any derived sequences are automatically + // processing response transactions. Only un-comment this call to get_responses() if you + // have configured the interface driver to utilize the response transaction path by setting + // the configuration variable "return_transaction_response" to 1. Otherwise it is possible + // to impact runtime performance and memory utilization. + // + virtual task pre_body(); + // pragma uvmf custom pre_body begin +// get_responses(); + // pragma uvmf custom pre_body end + endtask + + // **************************************************************************** + // TASK : body() + // This task is called automatically when start is called. This sequence sends + // a req sequence item to the sequencer identified as an argument in the call + // to start. + // + virtual task body(); + // pragma uvmf custom body begin + start_item(req); + finish_item(req); + // pragma uvmf custom body end + endtask + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name =""); + super.new( name ); + // pragma uvmf custom new begin + req = fuse_ctrl_out_transaction_req_t::type_id::create("req"); + rsp = fuse_ctrl_out_transaction_rsp_t::type_id::create("rsp"); + // pragma uvmf custom new end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_transaction.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_transaction.svh new file mode 100644 index 0000000..42d9dea --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_transaction.svh @@ -0,0 +1,216 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class defines the variables required for an fuse_ctrl_out +// transaction. Class variables to be displayed in waveform transaction +// viewing are added to the transaction viewing stream in the add_to_wave +// function. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_out_transaction #( + int AlertSyncOn = 3, + caliptra_otp_ctrl_pkg::lfsr_seed_t RndConstLfrSeed = caliptra_otp_ctrl_pkg::RndCnstLfsrSeedDefault, + caliptra_otp_ctrl_pkg::lfsr_perm_t RndCnstLfsrPerm = caliptra_otp_ctrl_pkg::RndCnstLfsrPermDefault, + string MemInitFile = "" + ) extends uvmf_transaction_base; + + `uvm_object_param_utils( fuse_ctrl_out_transaction #( + AlertSyncOn, + RndConstLfrSeed, + RndCnstLfsrPerm, + MemInitFile + )) + + pwrmgr_pkg::pwr_otp_rsp_t pwr_otp_o ; + + //Constraints for the transaction variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //******************************************************************* + //******************************************************************* + // Macros that define structs and associated functions are + // located in fuse_ctrl_out_macros.svh + + //******************************************************************* + // Monitor macro used by fuse_ctrl_out_monitor and fuse_ctrl_out_monitor_bfm + // This struct is defined in fuse_ctrl_out_macros.svh + `fuse_ctrl_out_MONITOR_STRUCT + fuse_ctrl_out_monitor_s fuse_ctrl_out_monitor_struct; + //******************************************************************* + // FUNCTION: to_monitor_struct() + // This function packs transaction variables into a fuse_ctrl_out_monitor_s + // structure. The function returns the handle to the fuse_ctrl_out_monitor_struct. + // This function is defined in fuse_ctrl_out_macros.svh + `fuse_ctrl_out_TO_MONITOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_monitor_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_out_macros.svh + `fuse_ctrl_out_FROM_MONITOR_STRUCT_FUNCTION + + //******************************************************************* + // Initiator macro used by fuse_ctrl_out_driver and fuse_ctrl_out_driver_bfm + // to communicate initiator driven data to fuse_ctrl_out_driver_bfm. + // This struct is defined in fuse_ctrl_out_macros.svh + `fuse_ctrl_out_INITIATOR_STRUCT + fuse_ctrl_out_initiator_s fuse_ctrl_out_initiator_struct; + //******************************************************************* + // FUNCTION: to_initiator_struct() + // This function packs transaction variables into a fuse_ctrl_out_initiator_s + // structure. The function returns the handle to the fuse_ctrl_out_initiator_struct. + // This function is defined in fuse_ctrl_out_macros.svh + `fuse_ctrl_out_TO_INITIATOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_initiator_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_out_macros.svh + `fuse_ctrl_out_FROM_INITIATOR_STRUCT_FUNCTION + + //******************************************************************* + // Responder macro used by fuse_ctrl_out_driver and fuse_ctrl_out_driver_bfm + // to communicate Responder driven data to fuse_ctrl_out_driver_bfm. + // This struct is defined in fuse_ctrl_out_macros.svh + `fuse_ctrl_out_RESPONDER_STRUCT + fuse_ctrl_out_responder_s fuse_ctrl_out_responder_struct; + //******************************************************************* + // FUNCTION: to_responder_struct() + // This function packs transaction variables into a fuse_ctrl_out_responder_s + // structure. The function returns the handle to the fuse_ctrl_out_responder_struct. + // This function is defined in fuse_ctrl_out_macros.svh + `fuse_ctrl_out_TO_RESPONDER_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_responder_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_out_macros.svh + `fuse_ctrl_out_FROM_RESPONDER_STRUCT_FUNCTION + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + endfunction + + // **************************************************************************** + // FUNCTION: convert2string() + // This function converts all variables in this class to a single string for + // logfile reporting. + // + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + // UVMF_CHANGE_ME : Customize format if desired. + return $sformatf("pwr_otp_o:0x%x ",pwr_otp_o); + // pragma uvmf custom convert2string end + endfunction + + //******************************************************************* + // FUNCTION: do_print() + // This function is automatically called when the .print() function + // is called on this class. + // + virtual function void do_print(uvm_printer printer); + // pragma uvmf custom do_print begin + // UVMF_CHANGE_ME : Current contents of do_print allows for the use of UVM 1.1d, 1.2 or P1800.2. + // Update based on your own printing preference according to your preferred UVM version + $display(convert2string()); + // pragma uvmf custom do_print end + endfunction + + //******************************************************************* + // FUNCTION: do_compare() + // This function is automatically called when the .compare() function + // is called on this class. + // + virtual function bit do_compare (uvm_object rhs, uvm_comparer comparer); + fuse_ctrl_out_transaction #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) RHS; + if (!$cast(RHS,rhs)) return 0; + // pragma uvmf custom do_compare begin + // UVMF_CHANGE_ME : Eliminate comparison of variables not to be used for compare + return (super.do_compare(rhs,comparer) + &&(this.pwr_otp_o == RHS.pwr_otp_o) + ); + // pragma uvmf custom do_compare end + endfunction + + //******************************************************************* + // FUNCTION: do_copy() + // This function is automatically called when the .copy() function + // is called on this class. + // + virtual function void do_copy (uvm_object rhs); + fuse_ctrl_out_transaction #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) RHS; + assert($cast(RHS,rhs)); + // pragma uvmf custom do_copy begin + super.do_copy(rhs); + this.pwr_otp_o = RHS.pwr_otp_o; + // pragma uvmf custom do_copy end + endfunction + + // **************************************************************************** + // FUNCTION: add_to_wave() + // This function is used to display variables in this class in the waveform + // viewer. The start_time and end_time variables must be set before this + // function is called. If the start_time and end_time variables are not set + // the transaction will be hidden at 0ns on the waveform display. + // + virtual function void add_to_wave(int transaction_viewing_stream_h); + `ifdef QUESTA + if (transaction_view_h == 0) begin + transaction_view_h = $begin_transaction(transaction_viewing_stream_h,"fuse_ctrl_out_transaction",start_time); + end + super.add_to_wave(transaction_view_h); + // pragma uvmf custom add_to_wave begin + // UVMF_CHANGE_ME : Color can be applied to transaction entries based on content, example below + // case() + // 1 : $add_color(transaction_view_h,"red"); + // default : $add_color(transaction_view_h,"grey"); + // endcase + // UVMF_CHANGE_ME : Eliminate transaction variables not wanted in transaction viewing in the waveform viewer + $add_attribute(transaction_view_h,pwr_otp_o,"pwr_otp_o"); + // pragma uvmf custom add_to_wave end + $end_transaction(transaction_view_h,end_time); + $free_transaction(transaction_view_h); + `endif // QUESTA + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_transaction_coverage.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_transaction_coverage.svh new file mode 100644 index 0000000..f418978 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_transaction_coverage.svh @@ -0,0 +1,99 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class records fuse_ctrl_out transaction information using +// a covergroup named fuse_ctrl_out_transaction_cg. An instance of this +// coverage component is instantiated in the uvmf_parameterized_agent +// if the has_coverage flag is set. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_out_transaction_coverage #( + int AlertSyncOn = 3, + caliptra_otp_ctrl_pkg::lfsr_seed_t RndConstLfrSeed = caliptra_otp_ctrl_pkg::RndCnstLfsrSeedDefault, + caliptra_otp_ctrl_pkg::lfsr_perm_t RndCnstLfsrPerm = caliptra_otp_ctrl_pkg::RndCnstLfsrPermDefault, + string MemInitFile = "" + ) extends uvm_subscriber #(.T(fuse_ctrl_out_transaction #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ))); + + `uvm_component_param_utils( fuse_ctrl_out_transaction_coverage #( + AlertSyncOn, + RndConstLfrSeed, + RndCnstLfsrPerm, + MemInitFile + )) + + T coverage_trans; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + covergroup fuse_ctrl_out_transaction_cg; + // pragma uvmf custom covergroup begin + // UVMF_CHANGE_ME : Add coverage bins, crosses, exclusions, etc. according to coverage needs. + option.auto_bin_max=1024; + option.per_instance=1; + pwr_otp_o: coverpoint coverage_trans.pwr_otp_o; + // pragma uvmf custom covergroup end + endgroup + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new(string name="", uvm_component parent=null); + super.new(name,parent); + fuse_ctrl_out_transaction_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that transaction variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + endfunction + + // **************************************************************************** + // FUNCTION : build_phase() + // This function is the standard UVM build_phase. + // + function void build_phase(uvm_phase phase); + fuse_ctrl_out_transaction_cg.set_inst_name($sformatf("fuse_ctrl_out_transaction_cg_%s",get_full_name())); + endfunction + + // **************************************************************************** + // FUNCTION: write (T t) + // This function is automatically executed when a transaction arrives on the + // analysis_export. It copies values from the variables in the transaction + // to local variables used to collect functional coverage. + // + virtual function void write (T t); + `uvm_info("COV","Received transaction",UVM_HIGH); + coverage_trans = t; + fuse_ctrl_out_transaction_cg.sample(); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_typedefs.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_typedefs.svh new file mode 100644 index 0000000..f2a7bdb --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_typedefs.svh @@ -0,0 +1,34 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the host server when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_typedefs_hdl.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_typedefs_hdl.svh new file mode 100644 index 0000000..0d58518 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_typedefs_hdl.svh @@ -0,0 +1,35 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the emulator when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/yaml/fuse_ctrl_out_interface.yaml b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/yaml/fuse_ctrl_out_interface.yaml new file mode 100644 index 0000000..0067495 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_out_pkg/yaml/fuse_ctrl_out_interface.yaml @@ -0,0 +1,73 @@ +uvmf: + interfaces: + fuse_ctrl_out: + clock: clk_i + config_constraints: [] + config_vars: [] + existing_library_component: 'True' + gen_inbound_streaming_driver: 'False' + hdl_pkg_parameters: [] + hdl_typedefs: [] + hvl_pkg_parameters: [] + hvl_typedefs: [] + parameters: + - name: AlertSyncOn + type: int + value: '3' + - name: RndConstLfrSeed + type: caliptra_otp_ctrl_pkg::lfsr_seed_t + value: caliptra_otp_ctrl_pkg::RndCnstLfsrSeedDefault + - name: RndCnstLfsrPerm + type: caliptra_otp_ctrl_pkg::lfsr_perm_t + value: caliptra_otp_ctrl_pkg::RndCnstLfsrPermDefault + - name: MemInitFile + type: string + value: '""' + ports: + - dir: input + name: edn_o + reset_value: '''bz' + width: '[''$bits(edn_pkg::edn_req_t)'']' + - dir: input + name: intr_otp_operation_done_o + reset_value: '''bz' + width: '1' + - dir: input + name: intr_otp_error_o + reset_value: '''bz' + width: '1' + - dir: input + name: alert_tx_o + reset_value: '''bz' + width: '[''ast_pkg::NumAlerts * $bits(caliptra_prim_alert_pkg::alert_tx_t)'']' + - dir: input + name: otp_obs_o + reset_value: '''bz' + width: '8' + - dir: input + name: otp_ast_pwr_seq_o + reset_value: '''bz' + width: '[''$bits(caliptra_otp_ctrl_pkg::otp_ast_req_t)'']' + - dir: input + name: otp_broadcast_o + reset_value: '''bz' + width: '[''$bits(caliptra_otp_ctrl_part_pkg::otp_broadcast_t)'']' + - dir: input + name: cio_test_o + reset_value: '''bz' + width: '[''caliptra_otp_ctrl_pkg::OtpTestVectWidth'']' + - dir: input + name: cio_test_en_o + reset_value: '''bz' + width: '[''caliptra_otp_ctrl_pkg::OtpTestVectWidth'']' + reset: rst_ni + reset_assertion_level: 'False' + transaction_constraints: [] + transaction_vars: + - comment: '' + iscompare: 'True' + isrand: 'False' + name: pwr_otp_o + type: pwrmgr_pkg::pwr_otp_rsp_t + unpacked_dimension: '' + use_dpi_link: 'False' diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/.project b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/.project new file mode 100644 index 0000000..d0dba88 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/.project @@ -0,0 +1,30 @@ + + + fuse_ctrl_prim_axi_read_in_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/.svproject b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/.svproject new file mode 100644 index 0000000..7f5e878 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/Makefile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/Makefile new file mode 100644 index 0000000..ff74765 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/Makefile @@ -0,0 +1,66 @@ +# fuse_ctrl_prim_axi_read_in interface packages source +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +fuse_ctrl_prim_axi_read_in_PKG = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_read_in_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_filelist_hvl.f + +fuse_ctrl_prim_axi_read_in_PKG_HDL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_read_in_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_filelist_hdl.f + +fuse_ctrl_prim_axi_read_in_PKG_XRTL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_read_in_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_filelist_xrtl.f + +COMP_fuse_ctrl_prim_axi_read_in_PKG_TGT_0 = q_comp_fuse_ctrl_prim_axi_read_in_pkg +COMP_fuse_ctrl_prim_axi_read_in_PKG_TGT_1 = v_comp_fuse_ctrl_prim_axi_read_in_pkg +COMP_fuse_ctrl_prim_axi_read_in_PKG_TGT = $(COMP_fuse_ctrl_prim_axi_read_in_PKG_TGT_$(USE_VELOCE)) + +comp_fuse_ctrl_prim_axi_read_in_pkg: $(COMP_fuse_ctrl_prim_axi_read_in_PKG_TGT) + +q_comp_fuse_ctrl_prim_axi_read_in_pkg: + $(HDL_COMP_CMD) $(fuse_ctrl_prim_axi_read_in_PKG_HDL) + $(HVL_COMP_CMD) $(fuse_ctrl_prim_axi_read_in_PKG) + $(HDL_COMP_CMD) $(fuse_ctrl_prim_axi_read_in_PKG_XRTL) + +v_comp_fuse_ctrl_prim_axi_read_in_pkg: + $(HVL_COMP_CMD) $(fuse_ctrl_prim_axi_read_in_PKG_HDL) + $(HVL_COMP_CMD) $(fuse_ctrl_prim_axi_read_in_PKG) + $(VELANALYZE_CMD) $(fuse_ctrl_prim_axi_read_in_PKG_HDL) + $(VELANALYZE_HVL_CMD) $(fuse_ctrl_prim_axi_read_in_PKG) + $(HDL_COMP_CMD) $(fuse_ctrl_prim_axi_read_in_PKG_XRTL) + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export fuse_ctrl_prim_axi_read_in_IF_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/dpi + +C_FILE_COMPILE_LIST_fuse_ctrl_prim_axi_read_in_pkg = \ + +O_FILE_COMPILE_LIST_fuse_ctrl_prim_axi_read_in_pkg = $(notdir $(C_FILE_COMPILE_LIST_fuse_ctrl_prim_axi_read_in_pkg:.c=.o)) + +GCC_COMP_ARGS_fuse_ctrl_prim_axi_read_in_pkg += -I$(fuse_ctrl_prim_axi_read_in_IF_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_fuse_ctrl_prim_axi_read_in_pkg += $(fuse_ctrl_prim_axi_read_in_IF_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_fuse_ctrl_prim_axi_read_in_pkg += \ + \ + -o .so + +comp_fuse_ctrl_prim_axi_read_in_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Interface C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_fuse_ctrl_prim_axi_read_in_pkg) $(C_FILE_COMPILE_LIST_fuse_ctrl_prim_axi_read_in_pkg) + @echo "--------------------------------" + @echo "Linking Interface C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_fuse_ctrl_prim_axi_read_in_pkg) $(O_FILE_COMPILE_LIST_fuse_ctrl_prim_axi_read_in_pkg) + @echo "--------------------------------" + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/compile.do b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/compile.do new file mode 100644 index 0000000..d5afe8a --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/compile.do @@ -0,0 +1,14 @@ +# Tcl do file for compile of fuse_ctrl_prim_axi_read_in interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_read_in_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_filelist_hdl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_read_in_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_filelist_hvl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_read_in_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_filelist_xrtl.f \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in.compile new file mode 100644 index 0000000..73650e4 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in.compile @@ -0,0 +1,3 @@ +needs: + - fuse_ctrl_prim_axi_read_in_hvl.compile + - fuse_ctrl_prim_axi_read_in_hdl.compile diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_bfm.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_bfm.vinfo new file mode 100644 index 0000000..8ed6f0d --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_bfm.vinfo @@ -0,0 +1,6 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use fuse_ctrl_prim_axi_read_in_pkg_hdl.vinfo ++incdir+@vinfodir +src/fuse_ctrl_prim_axi_read_in_if.sv +src/fuse_ctrl_prim_axi_read_in_driver_bfm.sv +src/fuse_ctrl_prim_axi_read_in_monitor_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_common.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_common.compile new file mode 100644 index 0000000..ca43b4d --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_common.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +incdir: + - . + - ${uvm_path}/src +src: + - fuse_ctrl_prim_axi_read_in_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_filelist_hdl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_filelist_hdl.f new file mode 100644 index 0000000..f0b99a3 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_filelist_hdl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_filelist_hvl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_filelist_hvl.f new file mode 100644 index 0000000..8dcf197 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_filelist_hvl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_pkg.sv \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_filelist_xrtl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_filelist_xrtl.f new file mode 100644 index 0000000..46c2aab --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_filelist_xrtl.f @@ -0,0 +1,3 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_if.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_monitor_bfm.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_driver_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_hdl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_hdl.compile new file mode 100644 index 0000000..31d8fb1 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_hdl.compile @@ -0,0 +1,9 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ./fuse_ctrl_prim_axi_read_in_common.compile +incdir: + - . +src: + - src/fuse_ctrl_prim_axi_read_in_if.sv + - src/fuse_ctrl_prim_axi_read_in_monitor_bfm.sv + - src/fuse_ctrl_prim_axi_read_in_driver_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_hvl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_hvl.compile new file mode 100644 index 0000000..7c7cc34 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_hvl.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ./fuse_ctrl_prim_axi_read_in_common.compile +incdir: + - . +src: + - fuse_ctrl_prim_axi_read_in_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_pkg.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_pkg.sv new file mode 100644 index 0000000..2e29485 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_pkg.sv @@ -0,0 +1,91 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - + +// - +// - +// - + +// - +// - +// - + +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_prim_axi_read_in_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg_hdl::*; + import uvmf_base_pkg::*; + import fuse_ctrl_prim_axi_read_in_pkg_hdl::*; + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + `include "src/fuse_ctrl_prim_axi_read_in_macros.svh" + + export fuse_ctrl_prim_axi_read_in_pkg_hdl::*; + + + + // Parameters defined as HVL parameters + + `include "src/fuse_ctrl_prim_axi_read_in_typedefs.svh" + `include "src/fuse_ctrl_prim_axi_read_in_transaction.svh" + + `include "src/fuse_ctrl_prim_axi_read_in_configuration.svh" + `include "src/fuse_ctrl_prim_axi_read_in_driver.svh" + `include "src/fuse_ctrl_prim_axi_read_in_monitor.svh" + + `include "src/fuse_ctrl_prim_axi_read_in_transaction_coverage.svh" + `include "src/fuse_ctrl_prim_axi_read_in_sequence_base.svh" + `include "src/fuse_ctrl_prim_axi_read_in_random_sequence.svh" + + `include "src/fuse_ctrl_prim_axi_read_in_responder_sequence.svh" + `include "src/fuse_ctrl_prim_axi_read_in2reg_adapter.svh" + + `include "src/fuse_ctrl_prim_axi_read_in_agent.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new interface sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the interface package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_pkg.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_pkg.vinfo new file mode 100644 index 0000000..7f62c30 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_pkg.vinfo @@ -0,0 +1,4 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use fuse_ctrl_prim_axi_read_in_pkg_hdl.vinfo ++incdir+@vinfodir +fuse_ctrl_prim_axi_read_in_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_pkg_hdl.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_pkg_hdl.sv new file mode 100644 index 0000000..f771faa --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_pkg_hdl.sv @@ -0,0 +1,52 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that needs to be compiled and synthesized +// for running on Veloce. +// +// CONTAINS: +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_prim_axi_read_in_pkg_hdl; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HDL parameters + + `include "src/fuse_ctrl_prim_axi_read_in_typedefs_hdl.svh" + `include "src/fuse_ctrl_prim_axi_read_in_macros.svh" + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_pkg_hdl.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_pkg_hdl.vinfo new file mode 100644 index 0000000..eb67953 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_pkg_hdl.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +fuse_ctrl_prim_axi_read_in_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_pkg_sve.F b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_pkg_sve.F new file mode 100644 index 0000000..ce8af16 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_pkg_sve.F @@ -0,0 +1,10 @@ +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + ++incdir+. +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_filelist_hdl.f +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_filelist_hvl.f diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in2reg_adapter.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in2reg_adapter.svh new file mode 100644 index 0000000..da4790c --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in2reg_adapter.svh @@ -0,0 +1,137 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the UVM register adapter for the fuse_ctrl_prim_axi_read_in interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_read_in2reg_adapter #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvm_reg_adapter; + + `uvm_object_param_utils( fuse_ctrl_prim_axi_read_in2reg_adapter #( + AW, + DW, + IW, + UW + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //-------------------------------------------------------------------- + // new + //-------------------------------------------------------------------- + function new (string name = "fuse_ctrl_prim_axi_read_in2reg_adapter" ); + super.new(name); + // pragma uvmf custom new begin + // UVMF_CHANGE_ME : Configure the adapter regarding byte enables and provides response. + + // Does the protocol the Agent is modeling support byte enables? + // 0 = NO + // 1 = YES + supports_byte_enable = 0; + + // Does the Agent's Driver provide separate response sequence items? + // i.e. Does the driver call seq_item_port.put() + // and do the sequences call get_response()? + // 0 = NO + // 1 = YES + provides_responses = 0; + // pragma uvmf custom new end + + endfunction: new + + //-------------------------------------------------------------------- + // reg2bus + //-------------------------------------------------------------------- + virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw); + + fuse_ctrl_prim_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) trans_h = fuse_ctrl_prim_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )::type_id::create("trans_h"); + + // pragma uvmf custom reg2bus begin + // UVMF_CHANGE_ME : Fill in the reg2bus adapter mapping registe fields to protocol fields. + + //Adapt the following for your sequence item type + // trans_h.op = (rw.kind == UVM_READ) ? WB_READ : WB_WRITE; + //Copy over address + // trans_h.addr = rw.addr; + //Copy over write data + // trans_h.data = rw.data; + + // pragma uvmf custom reg2bus end + + // Return the adapted transaction + return trans_h; + + endfunction: reg2bus + + //-------------------------------------------------------------------- + // bus2reg + //-------------------------------------------------------------------- + virtual function void bus2reg(uvm_sequence_item bus_item, + ref uvm_reg_bus_op rw); + fuse_ctrl_prim_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) trans_h; + if (!$cast(trans_h, bus_item)) begin + `uvm_fatal("ADAPT","Provided bus_item is not of the correct type") + return; + end + // pragma uvmf custom bus2reg begin + // UVMF_CHANGE_ME : Fill in the bus2reg adapter mapping protocol fields to register fields. + //Adapt the following for your sequence item type + //Copy over instruction type + // rw.kind = (trans_h.op == WB_WRITE) ? UVM_WRITE : UVM_READ; + //Copy over address + // rw.addr = trans_h.addr; + //Copy over read data + // rw.data = trans_h.data; + //Check for errors on the bus and return UVM_NOT_OK if there is an error + // rw.status = UVM_IS_OK; + // pragma uvmf custom bus2reg end + + endfunction: bus2reg + +endclass : fuse_ctrl_prim_axi_read_in2reg_adapter + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_agent.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_agent.svh new file mode 100644 index 0000000..86f6725 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_agent.svh @@ -0,0 +1,102 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: Protocol specific agent class definition +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_read_in_agent #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvmf_parameterized_agent #( + .CONFIG_T(fuse_ctrl_prim_axi_read_in_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .DRIVER_T(fuse_ctrl_prim_axi_read_in_driver #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .MONITOR_T(fuse_ctrl_prim_axi_read_in_monitor #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .COVERAGE_T(fuse_ctrl_prim_axi_read_in_transaction_coverage #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .TRANS_T(fuse_ctrl_prim_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )) + ); + + `uvm_component_param_utils( fuse_ctrl_prim_axi_read_in_agent #( + AW, + DW, + IW, + UW + )) + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** + // FUNCTION: build_phase + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + if (configuration.active_passive == ACTIVE) begin + // Place sequencer handle into configuration object + // so that it may be retrieved from configuration + // rather than using uvm_config_db + configuration.sequencer = this.sequencer; + end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_configuration.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_configuration.svh new file mode 100644 index 0000000..ec9a380 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_configuration.svh @@ -0,0 +1,233 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class contains all variables and functions used +// to configure the fuse_ctrl_prim_axi_read_in agent and its bfm's. It gets the +// bfm's from the uvm_config_db for use by the agent. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_read_in_configuration #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvmf_parameterized_agent_configuration_base #( + .DRIVER_BFM_BIND_T(virtual fuse_ctrl_prim_axi_read_in_driver_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .MONITOR_BFM_BIND_T( virtual fuse_ctrl_prim_axi_read_in_monitor_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ))); + + `uvm_object_param_utils( fuse_ctrl_prim_axi_read_in_configuration #( + AW, + DW, + IW, + UW + )) + + + // Sequencer handle populated by agent + uvm_sequencer #(fuse_ctrl_prim_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) ) sequencer; + + //Constraints for the configuration variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + covergroup fuse_ctrl_prim_axi_read_in_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + // pragma uvmf custom covergroup end + endgroup + + //******************************************************************* + //******************************************************************* + // Structure used to pass configuration variables to monitor and driver BFM's. + // Use to_struct function to pack variables into structure. + // Use from_struct function to unpack variables from structure. + // This structure is defined in fuse_ctrl_prim_axi_read_in_macros.svh + `fuse_ctrl_prim_axi_read_in_CONFIGURATION_STRUCT + fuse_ctrl_prim_axi_read_in_configuration_s fuse_ctrl_prim_axi_read_in_configuration_struct; + //******************************************************************* + // FUNCTION: to_struct() + // This function packs variables into a fuse_ctrl_prim_axi_read_in_configuration_s + // structure. The function returns the handle to the fuse_ctrl_prim_axi_read_in_configuration_struct. + // This function is defined in fuse_ctrl_prim_axi_read_in_macros.svh + `fuse_ctrl_prim_axi_read_in_CONFIGURATION_TO_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_struct() + // This function unpacks the struct provided as an argument into + // variables of this class. + // This function is defined in fuse_ctrl_prim_axi_read_in_macros.svh + `fuse_ctrl_prim_axi_read_in_CONFIGURATION_FROM_STRUCT_FUNCTION + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + // Construct the covergroup for this configuration class + fuse_ctrl_prim_axi_read_in_configuration_cg = new; + endfunction + + // **************************************************************************** + // FUNCTION: post_randomize() + // This function is automatically called after the randomize() function + // is executed. + // + function void post_randomize(); + super.post_randomize(); + fuse_ctrl_prim_axi_read_in_configuration_cg.sample(); + endfunction + + // **************************************************************************** + // FUNCTION: initialize + // This function causes the configuration to retrieve + // its virtual interface handle from the uvm_config_db. + // This function also makes itself available to its + // agent through the uvm_config_db. + // + // ARGUMENTS: + // uvmf_active_passive_t activity: + // This argument identifies the simulation level + // as either BLOCK, CHIP, SIMULATION, etc. + // + // AGENT_PATH: + // This argument identifies the path to this + // configurations agent. This configuration + // makes itself available to the agent specified + // by agent_path by placing itself into the + // uvm_config_db. + // + // INTERFACE_NAME: + // This argument identifies the string name of + // this configurations BFM's. This string + // name is used to retrieve the driver and + // monitor BFM from the uvm_config_db. + // + virtual function void initialize(uvmf_active_passive_t activity, + string agent_path, + string interface_name); + + super.initialize( activity, agent_path, interface_name); + // The covergroup is given the same name as the interface + fuse_ctrl_prim_axi_read_in_configuration_cg.set_inst_name(interface_name); + + // This configuration places itself into the uvm_config_db for the agent, identified by the agent_path variable, to retrieve. + uvm_config_db #( fuse_ctrl_prim_axi_read_in_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + )::set( null ,agent_path,UVMF_AGENT_CONFIG, this ); + + // This configuration also places itself in the config db using the same identifier used by the interface. This allows users to access + // configuration variables and the interface through the bfm api class rather than directly accessing the BFM. This is useful for + // accessingthe BFM when using Veloce + uvm_config_db #( fuse_ctrl_prim_axi_read_in_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + )::set( null ,UVMF_CONFIGURATIONS, interface_name, this ); + + fuse_ctrl_prim_axi_read_in_configuration_cg.set_inst_name($sformatf("fuse_ctrl_prim_axi_read_in_configuration_cg_%s",get_full_name())); + +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. + `uvm_info("CFG", + $psprintf("The agent at '%s' is using interface named %s has the following parameters: AW=%x DW=%x IW=%x UW=%x ", agent_path, interface_name, AW ,DW ,IW ,UW ), + UVM_DEBUG) + + // pragma uvmf custom initialize begin + // This controls whether or not the agent returns a transaction handle in the driver when calling + // item_done() back into the sequencer or not. If set to 1, a transaction is sent back which means + // the sequence on the other end must use the get_response() part of the driver/sequence API. If + // this doesn't occur, there will eventually be response_queue overflow errors during the test. + return_transaction_response = 1'b0; + + // pragma uvmf custom initialize end + + endfunction + + // **************************************************************************** + // TASK: wait_for_reset + // *[Required]* Blocks until reset is released. The wait_for_reset operation is performed + // by a task in the monitor bfm. + virtual task wait_for_reset(); + monitor_bfm.wait_for_reset(); + endtask + + // **************************************************************************** + // TASK: wait_for_num_clocks + // *[Required]* Blocks until specified number of clocks have elapsed. The wait_for_num_clocks + // operation is performed by a task in the monitor bfm. + virtual task wait_for_num_clocks(int clocks); + monitor_bfm.wait_for_num_clocks(clocks); + endtask + + // **************************************************************************** + // FUNCTION : convert2string() + // This function is used to convert variables in this class into a string for log messaging. + // + virtual function string convert2string (); + // pragma uvmf custom convert2string begin + return $sformatf(""); + // pragma uvmf custom convert2string end + endfunction + + // **************************************************************************** + // FUNCTION: get_sequencer + function uvm_sequencer #(fuse_ctrl_prim_axi_read_in_transaction#( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )) get_sequencer(); + return sequencer; + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_driver.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_driver.svh new file mode 100644 index 0000000..da5cb2e --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_driver.svh @@ -0,0 +1,135 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class passes transactions between the sequencer +// and the BFM driver interface. It accesses the driver BFM +// through the bfm handle. This driver +// passes transactions to the driver BFM through the access +// task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_read_in_driver #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvmf_driver_base #( + .CONFIG_T(fuse_ctrl_prim_axi_read_in_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) ), + .BFM_BIND_T(virtual fuse_ctrl_prim_axi_read_in_driver_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) ), + .REQ(fuse_ctrl_prim_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) ), + .RSP(fuse_ctrl_prim_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) )); + + `uvm_component_param_utils( fuse_ctrl_prim_axi_read_in_driver #( + AW, + DW, + IW, + UW + )) +//******************************************************************* +// Macros that define structs located in fuse_ctrl_prim_axi_read_in_macros.svh +//******************************************************************* +// Initiator macro used by fuse_ctrl_prim_axi_read_in_driver and fuse_ctrl_prim_axi_read_in_driver_bfm +// to communicate initiator driven data to fuse_ctrl_prim_axi_read_in_driver_bfm. +`fuse_ctrl_prim_axi_read_in_INITIATOR_STRUCT + fuse_ctrl_prim_axi_read_in_initiator_s fuse_ctrl_prim_axi_read_in_initiator_struct; +//******************************************************************* +// Responder macro used by fuse_ctrl_prim_axi_read_in_driver and fuse_ctrl_prim_axi_read_in_driver_bfm +// to communicate Responder driven data to fuse_ctrl_prim_axi_read_in_driver_bfm. +`fuse_ctrl_prim_axi_read_in_RESPONDER_STRUCT + fuse_ctrl_prim_axi_read_in_responder_s fuse_ctrl_prim_axi_read_in_responder_struct; + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent=null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the driver BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// driver BFM. This allows the driver BFM to call tasks and function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// **************************************************************************** +// This task is called by the run_phase in uvmf_driver_base. + virtual task access( inout REQ txn ); +// pragma uvmf custom access begin + if (configuration.initiator_responder==RESPONDER) begin + // Complete current transfer and wait for next transfer + bfm.respond_and_wait_for_next_transfer( + fuse_ctrl_prim_axi_read_in_initiator_struct, + txn.to_responder_struct() + ); + // Unpack information about initiated transfer received by this responder + txn.from_initiator_struct(fuse_ctrl_prim_axi_read_in_initiator_struct); + end else begin + // Initiate a transfer and get response + bfm.initiate_and_get_response( + txn.to_initiator_struct(), + fuse_ctrl_prim_axi_read_in_responder_struct + ); + // Unpack transfer response information received by this initiator + txn.from_responder_struct(fuse_ctrl_prim_axi_read_in_responder_struct); + end +// pragma uvmf custom access end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_driver_bfm.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_driver_bfm.sv new file mode 100644 index 0000000..225df6f --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_driver_bfm.sv @@ -0,0 +1,383 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This interface performs the fuse_ctrl_prim_axi_read_in signal driving. It is +// accessed by the uvm fuse_ctrl_prim_axi_read_in driver through a virtual interface +// handle in the fuse_ctrl_prim_axi_read_in configuration. It drives the singals passed +// in through the port connection named bus of type fuse_ctrl_prim_axi_read_in_if. +// +// Input signals from the fuse_ctrl_prim_axi_read_in_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// This bfm drives signals with a _o suffix. These signals +// are driven onto signals within fuse_ctrl_prim_axi_read_in_if based on INITIATOR/RESPONDER and/or +// ARBITRATION/GRANT status. +// +// The output signal connections are as follows: +// signal_o -> bus.signal +// +// +// Interface functions and tasks used by UVM components: +// +// configure: +// This function gets configuration attributes from the +// UVM driver to set any required BFM configuration +// variables such as 'initiator_responder'. +// +// initiate_and_get_response: +// This task is used to perform signaling activity for initiating +// a protocol transfer. The task initiates the transfer, using +// input data from the initiator struct. Then the task captures +// response data, placing the data into the response struct. +// The response struct is returned to the driver class. +// +// respond_and_wait_for_next_transfer: +// This task is used to complete a current transfer as a responder +// and then wait for the initiator to start the next transfer. +// The task uses data in the responder struct to drive protocol +// signals to complete the transfer. The task then waits for +// the next transfer. Once the next transfer begins, data from +// the initiator is placed into the initiator struct and sent +// to the responder sequence for processing to determine +// what data to respond with. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_prim_axi_read_in_pkg_hdl::*; +`include "src/fuse_ctrl_prim_axi_read_in_macros.svh" + +interface fuse_ctrl_prim_axi_read_in_driver_bfm #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + (fuse_ctrl_prim_axi_read_in_if bus); + // The following pragma and additional ones in-lined further below are for running this BFM on Veloce + // pragma attribute fuse_ctrl_prim_axi_read_in_driver_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: AW=%x DW=%x IW=%x UW=%x ", AW,DW,IW,UW), + UVM_DEBUG) +end +`endif + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + tri clk_i_i; + tri rst_ni_i; + + // Signal list (all signals are capable of being inputs and outputs for the sake + // of supporting both INITIATOR and RESPONDER mode operation. Expectation is that + // directionality in the config file was from the point-of-view of the INITIATOR + + // INITIATOR mode input signals + + // INITIATOR mode output signals + tri [AW-1:0] araddr_i; + reg [AW-1:0] araddr_o = 'bz; + tri [$bits(axi_pkg::axi_burst_e)-1:0] arburst_i; + reg [$bits(axi_pkg::axi_burst_e)-1:0] arburst_o = 'bz; + tri [2:0] arsize_i; + reg [2:0] arsize_o = 'bz; + tri [7:0] arlen_i; + reg [7:0] arlen_o = 'bz; + tri [UW-1:0] aruser_i; + reg [UW-1:0] aruser_o = 'bz; + tri [IW-1:0] arid_i; + reg [IW-1:0] arid_o = 'bz; + tri arlock_i; + reg arlock_o = 'bz; + tri arvalid_i; + reg arvalid_o = 'bz; + tri rready_i; + reg rready_o = 'bz; + + // Bi-directional signals + + + assign clk_i_i = bus.clk_i; + assign rst_ni_i = bus.rst_ni; + + // These are signals marked as 'input' by the config file, but the signals will be + // driven by this BFM if put into RESPONDER mode (flipping all signal directions around) + + + // These are signals marked as 'output' by the config file, but the outputs will + // not be driven by this BFM unless placed in INITIATOR mode. + assign bus.araddr = (initiator_responder == INITIATOR) ? araddr_o : 'bz; + assign araddr_i = bus.araddr; + assign bus.arburst = (initiator_responder == INITIATOR) ? arburst_o : 'bz; + assign arburst_i = bus.arburst; + assign bus.arsize = (initiator_responder == INITIATOR) ? arsize_o : 'bz; + assign arsize_i = bus.arsize; + assign bus.arlen = (initiator_responder == INITIATOR) ? arlen_o : 'bz; + assign arlen_i = bus.arlen; + assign bus.aruser = (initiator_responder == INITIATOR) ? aruser_o : 'bz; + assign aruser_i = bus.aruser; + assign bus.arid = (initiator_responder == INITIATOR) ? arid_o : 'bz; + assign arid_i = bus.arid; + assign bus.arlock = (initiator_responder == INITIATOR) ? arlock_o : 'bz; + assign arlock_i = bus.arlock; + assign bus.arvalid = (initiator_responder == INITIATOR) ? arvalid_o : 'bz; + assign arvalid_i = bus.arvalid; + assign bus.rready = (initiator_responder == INITIATOR) ? rready_o : 'bz; + assign rready_i = bus.rready; + + // Proxy handle to UVM driver + fuse_ctrl_prim_axi_read_in_pkg::fuse_ctrl_prim_axi_read_in_driver #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) proxy; + // pragma tbx oneway proxy.my_function_name_in_uvm_driver + + // **************************************************************************** + // **************************************************************************** + // Macros that define structs located in fuse_ctrl_prim_axi_read_in_macros.svh + // **************************************************************************** + // Struct for passing configuration data from fuse_ctrl_prim_axi_read_in_driver to this BFM + // **************************************************************************** + `fuse_ctrl_prim_axi_read_in_CONFIGURATION_STRUCT + // **************************************************************************** + // Structs for INITIATOR and RESPONDER data flow + //******************************************************************* + // Initiator macro used by fuse_ctrl_prim_axi_read_in_driver and fuse_ctrl_prim_axi_read_in_driver_bfm + // to communicate initiator driven data to fuse_ctrl_prim_axi_read_in_driver_bfm. + `fuse_ctrl_prim_axi_read_in_INITIATOR_STRUCT + fuse_ctrl_prim_axi_read_in_initiator_s initiator_struct; + // Responder macro used by fuse_ctrl_prim_axi_read_in_driver and fuse_ctrl_prim_axi_read_in_driver_bfm + // to communicate Responder driven data to fuse_ctrl_prim_axi_read_in_driver_bfm. + `fuse_ctrl_prim_axi_read_in_RESPONDER_STRUCT + fuse_ctrl_prim_axi_read_in_responder_s responder_struct; + + // **************************************************************************** +// pragma uvmf custom reset_condition_and_response begin + // Always block used to return signals to reset value upon assertion of reset + always @( negedge rst_ni_i ) + begin + // RESPONDER mode output signals + // INITIATOR mode output signals + araddr_o <= 'bz; + arburst_o <= 'bz; + arsize_o <= 'bz; + arlen_o <= 'bz; + aruser_o <= 'bz; + arid_o <= 'bz; + arlock_o <= 'bz; + arvalid_o <= 'bz; + rready_o <= 'bz; + // Bi-directional signals + + end +// pragma uvmf custom reset_condition_and_response end + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the driver BFM. It is called by the driver within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the driver BFM needs to be aware of the new configuration + // variables. + // + + function void configure(fuse_ctrl_prim_axi_read_in_configuration_s fuse_ctrl_prim_axi_read_in_configuration_arg); // pragma tbx xtf + initiator_responder = fuse_ctrl_prim_axi_read_in_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + +// pragma uvmf custom initiate_and_get_response begin +// **************************************************************************** +// UVMF_CHANGE_ME +// This task is used by an initator. The task first initiates a transfer then +// waits for the responder to complete the transfer. + task initiate_and_get_response( + // This argument passes transaction variables used by an initiator + // to perform the initial part of a protocol transfer. The values + // come from a sequence item created in a sequence. + input fuse_ctrl_prim_axi_read_in_initiator_s fuse_ctrl_prim_axi_read_in_initiator_struct, + // This argument is used to send data received from the responder + // back to the sequence item. The sequence item is returned to the sequence. + output fuse_ctrl_prim_axi_read_in_responder_s fuse_ctrl_prim_axi_read_in_responder_struct + );// pragma tbx xtf + // + // Members within the fuse_ctrl_prim_axi_read_in_initiator_struct: + // logic [AW-1:0] prim_araddr ; + // logic prim_arvalid ; + // logic [$bits(axi_pkg::axi_burst_e)] prim_arburst ; + // logic [2:0] prim_arsize ; + // logic [7:0] prim_arlen ; + // logic [UW-1:0] prim_aruser ; + // logic [IW-1:0] prim_arid ; + // logic prim_arlock ; + // logic prim_rready ; + // Members within the fuse_ctrl_prim_axi_read_in_responder_struct: + // logic [AW-1:0] prim_araddr ; + // logic prim_arvalid ; + // logic [$bits(axi_pkg::axi_burst_e)] prim_arburst ; + // logic [2:0] prim_arsize ; + // logic [7:0] prim_arlen ; + // logic [UW-1:0] prim_aruser ; + // logic [IW-1:0] prim_arid ; + // logic prim_arlock ; + // logic prim_rready ; + initiator_struct = fuse_ctrl_prim_axi_read_in_initiator_struct; + // + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clk_i_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available initiator input and inout signals listed. + // Initiator input signals + // Initiator inout signals + // How to assign a signal from an initiator struct member named xyz. + // All available initiator output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Initiator output signals + // araddr_o <= fuse_ctrl_prim_axi_read_in_initiator_struct.xyz; // [AW-1:0] + // arburst_o <= fuse_ctrl_prim_axi_read_in_initiator_struct.xyz; // [$bits(axi_pkg::axi_burst_e)-1:0] + // arsize_o <= fuse_ctrl_prim_axi_read_in_initiator_struct.xyz; // [2:0] + // arlen_o <= fuse_ctrl_prim_axi_read_in_initiator_struct.xyz; // [7:0] + // aruser_o <= fuse_ctrl_prim_axi_read_in_initiator_struct.xyz; // [UW-1:0] + // arid_o <= fuse_ctrl_prim_axi_read_in_initiator_struct.xyz; // [IW-1:0] + // arlock_o <= fuse_ctrl_prim_axi_read_in_initiator_struct.xyz; // + // arvalid_o <= fuse_ctrl_prim_axi_read_in_initiator_struct.xyz; // + // rready_o <= fuse_ctrl_prim_axi_read_in_initiator_struct.xyz; // + // Initiator inout signals + // Initiate a transfer using the data received. + @(posedge clk_i_i); + @(posedge clk_i_i); + // Wait for the responder to complete the transfer then place the responder data into + // fuse_ctrl_prim_axi_read_in_responder_struct. + @(posedge clk_i_i); + @(posedge clk_i_i); + responder_struct = fuse_ctrl_prim_axi_read_in_responder_struct; + endtask +// pragma uvmf custom initiate_and_get_response end + +// pragma uvmf custom respond_and_wait_for_next_transfer begin +// **************************************************************************** +// The first_transfer variable is used to prevent completing a transfer in the +// first call to this task. For the first call to this task, there is not +// current transfer to complete. +bit first_transfer=1; + +// UVMF_CHANGE_ME +// This task is used by a responder. The task first completes the current +// transfer in progress then waits for the initiator to start the next transfer. + task respond_and_wait_for_next_transfer( + // This argument is used to send data received from the initiator + // back to the sequence item. The sequence determines how to respond. + output fuse_ctrl_prim_axi_read_in_initiator_s fuse_ctrl_prim_axi_read_in_initiator_struct, + // This argument passes transaction variables used by a responder + // to complete a protocol transfer. The values come from a sequence item. + input fuse_ctrl_prim_axi_read_in_responder_s fuse_ctrl_prim_axi_read_in_responder_struct + );// pragma tbx xtf + // Variables within the fuse_ctrl_prim_axi_read_in_initiator_struct: + // logic [AW-1:0] prim_araddr ; + // logic prim_arvalid ; + // logic [$bits(axi_pkg::axi_burst_e)] prim_arburst ; + // logic [2:0] prim_arsize ; + // logic [7:0] prim_arlen ; + // logic [UW-1:0] prim_aruser ; + // logic [IW-1:0] prim_arid ; + // logic prim_arlock ; + // logic prim_rready ; + // Variables within the fuse_ctrl_prim_axi_read_in_responder_struct: + // logic [AW-1:0] prim_araddr ; + // logic prim_arvalid ; + // logic [$bits(axi_pkg::axi_burst_e)] prim_arburst ; + // logic [2:0] prim_arsize ; + // logic [7:0] prim_arlen ; + // logic [UW-1:0] prim_aruser ; + // logic [IW-1:0] prim_arid ; + // logic prim_arlock ; + // logic prim_rready ; + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clk_i_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available responder input and inout signals listed. + // Responder input signals + // fuse_ctrl_prim_axi_read_in_responder_struct.xyz = araddr_i; // [AW-1:0] + // fuse_ctrl_prim_axi_read_in_responder_struct.xyz = arburst_i; // [$bits(axi_pkg::axi_burst_e)-1:0] + // fuse_ctrl_prim_axi_read_in_responder_struct.xyz = arsize_i; // [2:0] + // fuse_ctrl_prim_axi_read_in_responder_struct.xyz = arlen_i; // [7:0] + // fuse_ctrl_prim_axi_read_in_responder_struct.xyz = aruser_i; // [UW-1:0] + // fuse_ctrl_prim_axi_read_in_responder_struct.xyz = arid_i; // [IW-1:0] + // fuse_ctrl_prim_axi_read_in_responder_struct.xyz = arlock_i; // + // fuse_ctrl_prim_axi_read_in_responder_struct.xyz = arvalid_i; // + // fuse_ctrl_prim_axi_read_in_responder_struct.xyz = rready_i; // + // Responder inout signals + // How to assign a signal, named xyz, from an initiator struct member. + // All available responder output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Responder output signals + // Responder inout signals + + @(posedge clk_i_i); + if (!first_transfer) begin + // Perform transfer response here. + // Reply using data recieved in the fuse_ctrl_prim_axi_read_in_responder_struct. + @(posedge clk_i_i); + // Reply using data recieved in the transaction handle. + @(posedge clk_i_i); + end + // Wait for next transfer then gather info from intiator about the transfer. + // Place the data into the fuse_ctrl_prim_axi_read_in_initiator_struct. + @(posedge clk_i_i); + @(posedge clk_i_i); + first_transfer = 0; + endtask +// pragma uvmf custom respond_and_wait_for_next_transfer end + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_if.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_if.sv new file mode 100644 index 0000000..76b8af3 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_if.sv @@ -0,0 +1,123 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface contains the fuse_ctrl_prim_axi_read_in interface signals. +// It is instantiated once per fuse_ctrl_prim_axi_read_in bus. Bus Functional Models, +// BFM's named fuse_ctrl_prim_axi_read_in_driver_bfm, are used to drive signals on the bus. +// BFM's named fuse_ctrl_prim_axi_read_in_monitor_bfm are used to monitor signals on the +// bus. This interface signal bundle is passed in the port list of +// the BFM in order to give the BFM access to the signals in this +// interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// This template can be used to connect a DUT to these signals +// +// .dut_signal_port(fuse_ctrl_prim_axi_read_in_bus.araddr), // Agent output +// .dut_signal_port(fuse_ctrl_prim_axi_read_in_bus.arburst), // Agent output +// .dut_signal_port(fuse_ctrl_prim_axi_read_in_bus.arsize), // Agent output +// .dut_signal_port(fuse_ctrl_prim_axi_read_in_bus.arlen), // Agent output +// .dut_signal_port(fuse_ctrl_prim_axi_read_in_bus.aruser), // Agent output +// .dut_signal_port(fuse_ctrl_prim_axi_read_in_bus.arid), // Agent output +// .dut_signal_port(fuse_ctrl_prim_axi_read_in_bus.arlock), // Agent output +// .dut_signal_port(fuse_ctrl_prim_axi_read_in_bus.arvalid), // Agent output +// .dut_signal_port(fuse_ctrl_prim_axi_read_in_bus.rready), // Agent output + +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_prim_axi_read_in_pkg_hdl::*; + +interface fuse_ctrl_prim_axi_read_in_if #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + + ( + input tri clk_i, + input tri rst_ni, + inout tri [AW-1:0] araddr, + inout tri [$bits(axi_pkg::axi_burst_e)-1:0] arburst, + inout tri [2:0] arsize, + inout tri [7:0] arlen, + inout tri [UW-1:0] aruser, + inout tri [IW-1:0] arid, + inout tri arlock, + inout tri arvalid, + inout tri rready + ); + +modport monitor_port + ( + input clk_i, + input rst_ni, + input araddr, + input arburst, + input arsize, + input arlen, + input aruser, + input arid, + input arlock, + input arvalid, + input rready + ); + +modport initiator_port + ( + input clk_i, + input rst_ni, + output araddr, + output arburst, + output arsize, + output arlen, + output aruser, + output arid, + output arlock, + output arvalid, + output rready + ); + +modport responder_port + ( + input clk_i, + input rst_ni, + input araddr, + input arburst, + input arsize, + input arlen, + input aruser, + input arid, + input arlock, + input arvalid, + input rready + ); + + +// pragma uvmf custom interface_item_additional begin +// pragma uvmf custom interface_item_additional end + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_infact_coverage_strategy.csv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_infact_coverage_strategy.csv new file mode 100644 index 0000000..1c218e1 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_infact_coverage_strategy.csv @@ -0,0 +1,6 @@ +Global +auto_bin_max, 64 + +Name,Type,Include +rand_fields,coverpoint,=rand *.** + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_macros.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_macros.svh new file mode 100644 index 0000000..ba93fd2 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_macros.svh @@ -0,0 +1,207 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains macros used with the fuse_ctrl_prim_axi_read_in package. +// These macros include packed struct definitions. These structs are +// used to pass data between classes, hvl, and BFM's, hdl. Use of +// structs are more efficient and simpler to modify. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_struct +// and from_struct methods defined in the macros below that are used in +// the fuse_ctrl_prim_axi_read_in_configuration class. +// + `define fuse_ctrl_prim_axi_read_in_CONFIGURATION_STRUCT \ +typedef struct packed { \ + uvmf_active_passive_t active_passive; \ + uvmf_initiator_responder_t initiator_responder; \ + } fuse_ctrl_prim_axi_read_in_configuration_s; + + `define fuse_ctrl_prim_axi_read_in_CONFIGURATION_TO_STRUCT_FUNCTION \ + virtual function fuse_ctrl_prim_axi_read_in_configuration_s to_struct();\ + fuse_ctrl_prim_axi_read_in_configuration_struct = \ + {\ + this.active_passive,\ + this.initiator_responder\ + };\ + return ( fuse_ctrl_prim_axi_read_in_configuration_struct );\ + endfunction + + `define fuse_ctrl_prim_axi_read_in_CONFIGURATION_FROM_STRUCT_FUNCTION \ + virtual function void from_struct(fuse_ctrl_prim_axi_read_in_configuration_s fuse_ctrl_prim_axi_read_in_configuration_struct);\ + {\ + this.active_passive,\ + this.initiator_responder \ + } = fuse_ctrl_prim_axi_read_in_configuration_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_monitor_struct +// and from_monitor_struct methods of the fuse_ctrl_prim_axi_read_in_transaction class. +// + `define fuse_ctrl_prim_axi_read_in_MONITOR_STRUCT typedef struct packed { \ + logic [AW-1:0] prim_araddr ; \ + logic prim_arvalid ; \ + logic [$bits(axi_pkg::axi_burst_e)] prim_arburst ; \ + logic [2:0] prim_arsize ; \ + logic [7:0] prim_arlen ; \ + logic [UW-1:0] prim_aruser ; \ + logic [IW-1:0] prim_arid ; \ + logic prim_arlock ; \ + logic prim_rready ; \ + } fuse_ctrl_prim_axi_read_in_monitor_s; + + `define fuse_ctrl_prim_axi_read_in_TO_MONITOR_STRUCT_FUNCTION \ + virtual function fuse_ctrl_prim_axi_read_in_monitor_s to_monitor_struct();\ + fuse_ctrl_prim_axi_read_in_monitor_struct = \ + { \ + this.prim_araddr , \ + this.prim_arvalid , \ + this.prim_arburst , \ + this.prim_arsize , \ + this.prim_arlen , \ + this.prim_aruser , \ + this.prim_arid , \ + this.prim_arlock , \ + this.prim_rready \ + };\ + return ( fuse_ctrl_prim_axi_read_in_monitor_struct);\ + endfunction\ + + `define fuse_ctrl_prim_axi_read_in_FROM_MONITOR_STRUCT_FUNCTION \ + virtual function void from_monitor_struct(fuse_ctrl_prim_axi_read_in_monitor_s fuse_ctrl_prim_axi_read_in_monitor_struct);\ + {\ + this.prim_araddr , \ + this.prim_arvalid , \ + this.prim_arburst , \ + this.prim_arsize , \ + this.prim_arlen , \ + this.prim_aruser , \ + this.prim_arid , \ + this.prim_arlock , \ + this.prim_rready \ + } = fuse_ctrl_prim_axi_read_in_monitor_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_initiator_struct +// and from_initiator_struct methods of the fuse_ctrl_prim_axi_read_in_transaction class. +// Also update the comments in the driver BFM. +// + `define fuse_ctrl_prim_axi_read_in_INITIATOR_STRUCT typedef struct packed { \ + logic [AW-1:0] prim_araddr ; \ + logic prim_arvalid ; \ + logic [$bits(axi_pkg::axi_burst_e)] prim_arburst ; \ + logic [2:0] prim_arsize ; \ + logic [7:0] prim_arlen ; \ + logic [UW-1:0] prim_aruser ; \ + logic [IW-1:0] prim_arid ; \ + logic prim_arlock ; \ + logic prim_rready ; \ + } fuse_ctrl_prim_axi_read_in_initiator_s; + + `define fuse_ctrl_prim_axi_read_in_TO_INITIATOR_STRUCT_FUNCTION \ + virtual function fuse_ctrl_prim_axi_read_in_initiator_s to_initiator_struct();\ + fuse_ctrl_prim_axi_read_in_initiator_struct = \ + {\ + this.prim_araddr , \ + this.prim_arvalid , \ + this.prim_arburst , \ + this.prim_arsize , \ + this.prim_arlen , \ + this.prim_aruser , \ + this.prim_arid , \ + this.prim_arlock , \ + this.prim_rready \ + };\ + return ( fuse_ctrl_prim_axi_read_in_initiator_struct);\ + endfunction + + `define fuse_ctrl_prim_axi_read_in_FROM_INITIATOR_STRUCT_FUNCTION \ + virtual function void from_initiator_struct(fuse_ctrl_prim_axi_read_in_initiator_s fuse_ctrl_prim_axi_read_in_initiator_struct);\ + {\ + this.prim_araddr , \ + this.prim_arvalid , \ + this.prim_arburst , \ + this.prim_arsize , \ + this.prim_arlen , \ + this.prim_aruser , \ + this.prim_arid , \ + this.prim_arlock , \ + this.prim_rready \ + } = fuse_ctrl_prim_axi_read_in_initiator_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_responder_struct +// and from_responder_struct methods of the fuse_ctrl_prim_axi_read_in_transaction class. +// Also update the comments in the driver BFM. +// + `define fuse_ctrl_prim_axi_read_in_RESPONDER_STRUCT typedef struct packed { \ + logic [AW-1:0] prim_araddr ; \ + logic prim_arvalid ; \ + logic [$bits(axi_pkg::axi_burst_e)] prim_arburst ; \ + logic [2:0] prim_arsize ; \ + logic [7:0] prim_arlen ; \ + logic [UW-1:0] prim_aruser ; \ + logic [IW-1:0] prim_arid ; \ + logic prim_arlock ; \ + logic prim_rready ; \ + } fuse_ctrl_prim_axi_read_in_responder_s; + + `define fuse_ctrl_prim_axi_read_in_TO_RESPONDER_STRUCT_FUNCTION \ + virtual function fuse_ctrl_prim_axi_read_in_responder_s to_responder_struct();\ + fuse_ctrl_prim_axi_read_in_responder_struct = \ + {\ + this.prim_araddr , \ + this.prim_arvalid , \ + this.prim_arburst , \ + this.prim_arsize , \ + this.prim_arlen , \ + this.prim_aruser , \ + this.prim_arid , \ + this.prim_arlock , \ + this.prim_rready \ + };\ + return ( fuse_ctrl_prim_axi_read_in_responder_struct);\ + endfunction + + `define fuse_ctrl_prim_axi_read_in_FROM_RESPONDER_STRUCT_FUNCTION \ + virtual function void from_responder_struct(fuse_ctrl_prim_axi_read_in_responder_s fuse_ctrl_prim_axi_read_in_responder_struct);\ + {\ + this.prim_araddr , \ + this.prim_arvalid , \ + this.prim_arburst , \ + this.prim_arsize , \ + this.prim_arlen , \ + this.prim_aruser , \ + this.prim_arid , \ + this.prim_arlock , \ + this.prim_rready \ + } = fuse_ctrl_prim_axi_read_in_responder_struct;\ + endfunction +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_monitor.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_monitor.svh new file mode 100644 index 0000000..db6abfc --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_monitor.svh @@ -0,0 +1,126 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class receives fuse_ctrl_prim_axi_read_in transactions observed by the +// fuse_ctrl_prim_axi_read_in monitor BFM and broadcasts them through the analysis port +// on the agent. It accesses the monitor BFM through the monitor +// task. This UVM component captures transactions +// for viewing in the waveform viewer if the +// enable_transaction_viewing flag is set in the configuration. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_read_in_monitor #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvmf_monitor_base #( + .CONFIG_T(fuse_ctrl_prim_axi_read_in_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .BFM_BIND_T(virtual fuse_ctrl_prim_axi_read_in_monitor_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .TRANS_T(fuse_ctrl_prim_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ))); + + `uvm_component_param_utils( fuse_ctrl_prim_axi_read_in_monitor #( + AW, + DW, + IW, + UW + )) + +// Structure used to pass data from monitor BFM to monitor class in agent. +// Use to_monitor_struct function to pack transaction variables into structure. +// Use from_monitor_struct function to unpack transaction variables from structure. +`fuse_ctrl_prim_axi_read_in_MONITOR_STRUCT + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the monitor BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// monitor BFM. This allows the monitor BFM to call the notify_transaction +// function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// *************************************************************************** + virtual task run_phase(uvm_phase phase); + // Start monitor BFM thread and don't call super.run() in order to + // override the default monitor proxy 'pull' behavior with the more + // emulation-friendly BFM 'push' approach using the notify_transaction + // function below + bfm.start_monitoring(); + endtask + +// ************************************************************************** + +// This function is called by the monitor BFM. It receives data observed by the +// monitor BFM. Data is passed using the fuse_ctrl_prim_axi_read_in_monitor_struct. + virtual function void notify_transaction(input fuse_ctrl_prim_axi_read_in_monitor_s fuse_ctrl_prim_axi_read_in_monitor_struct); + + + trans = new("trans"); + trans.from_monitor_struct(fuse_ctrl_prim_axi_read_in_monitor_struct); + trans.start_time = time_stamp; + trans.end_time = $time; + time_stamp = trans.end_time; + + analyze(trans); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_monitor_bfm.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_monitor_bfm.sv new file mode 100644 index 0000000..c2f64b9 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_monitor_bfm.sv @@ -0,0 +1,230 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface performs the fuse_ctrl_prim_axi_read_in signal monitoring. +// It is accessed by the uvm fuse_ctrl_prim_axi_read_in monitor through a virtual +// interface handle in the fuse_ctrl_prim_axi_read_in configuration. It monitors the +// signals passed in through the port connection named bus of +// type fuse_ctrl_prim_axi_read_in_if. +// +// Input signals from the fuse_ctrl_prim_axi_read_in_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// Interface functions and tasks used by UVM components: +// monitor(inout TRANS_T txn); +// This task receives the transaction, txn, from the +// UVM monitor and then populates variables in txn +// from values observed on bus activity. This task +// blocks until an operation on the fuse_ctrl_prim_axi_read_in bus is complete. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_prim_axi_read_in_pkg_hdl::*; +`include "src/fuse_ctrl_prim_axi_read_in_macros.svh" + + +interface fuse_ctrl_prim_axi_read_in_monitor_bfm #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + ( fuse_ctrl_prim_axi_read_in_if bus ); + // The pragma below and additional ones in-lined further down are for running this BFM on Veloce + // pragma attribute fuse_ctrl_prim_axi_read_in_monitor_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: AW=%x DW=%x IW=%x UW=%x ", AW,DW,IW,UW), + UVM_DEBUG) +end +`endif + + + // Structure used to pass transaction data from monitor BFM to monitor class in agent. +`fuse_ctrl_prim_axi_read_in_MONITOR_STRUCT + fuse_ctrl_prim_axi_read_in_monitor_s fuse_ctrl_prim_axi_read_in_monitor_struct; + + // Structure used to pass configuration data from monitor class to monitor BFM. + `fuse_ctrl_prim_axi_read_in_CONFIGURATION_STRUCT + + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + tri clk_i_i; + tri rst_ni_i; + tri [AW-1:0] araddr_i; + tri [$bits(axi_pkg::axi_burst_e)-1:0] arburst_i; + tri [2:0] arsize_i; + tri [7:0] arlen_i; + tri [UW-1:0] aruser_i; + tri [IW-1:0] arid_i; + tri arlock_i; + tri arvalid_i; + tri rready_i; + assign clk_i_i = bus.clk_i; + assign rst_ni_i = bus.rst_ni; + assign araddr_i = bus.araddr; + assign arburst_i = bus.arburst; + assign arsize_i = bus.arsize; + assign arlen_i = bus.arlen; + assign aruser_i = bus.aruser; + assign arid_i = bus.arid; + assign arlock_i = bus.arlock; + assign arvalid_i = bus.arvalid; + assign rready_i = bus.rready; + + // Proxy handle to UVM monitor + fuse_ctrl_prim_axi_read_in_pkg::fuse_ctrl_prim_axi_read_in_monitor #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) proxy; + // pragma tbx oneway proxy.notify_transaction + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + task wait_for_reset();// pragma tbx xtf + @(posedge clk_i_i) ; + do_wait_for_reset(); + endtask + + // **************************************************************************** + task do_wait_for_reset(); + // pragma uvmf custom reset_condition begin + wait ( rst_ni_i === 1 ) ; + @(posedge clk_i_i) ; + // pragma uvmf custom reset_condition end + endtask + + //****************************************************************** + + task wait_for_num_clocks(input int unsigned count); // pragma tbx xtf + @(posedge clk_i_i); + + repeat (count-1) @(posedge clk_i_i); + endtask + + //****************************************************************** + event go; + function void start_monitoring();// pragma tbx xtf + -> go; + endfunction + + // **************************************************************************** + initial begin + @go; + forever begin + @(posedge clk_i_i); + do_monitor( fuse_ctrl_prim_axi_read_in_monitor_struct ); + + + proxy.notify_transaction( fuse_ctrl_prim_axi_read_in_monitor_struct ); + + end + end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the monitor BFM. It is called by the monitor within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the monitor BFM needs to be aware of the new configuration + // variables. + // + function void configure(fuse_ctrl_prim_axi_read_in_configuration_s fuse_ctrl_prim_axi_read_in_configuration_arg); // pragma tbx xtf + initiator_responder = fuse_ctrl_prim_axi_read_in_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + + + // **************************************************************************** + + task do_monitor(output fuse_ctrl_prim_axi_read_in_monitor_s fuse_ctrl_prim_axi_read_in_monitor_struct); + // + // Available struct members: + // // fuse_ctrl_prim_axi_read_in_monitor_struct.prim_araddr + // // fuse_ctrl_prim_axi_read_in_monitor_struct.prim_arvalid + // // fuse_ctrl_prim_axi_read_in_monitor_struct.prim_arburst + // // fuse_ctrl_prim_axi_read_in_monitor_struct.prim_arsize + // // fuse_ctrl_prim_axi_read_in_monitor_struct.prim_arlen + // // fuse_ctrl_prim_axi_read_in_monitor_struct.prim_aruser + // // fuse_ctrl_prim_axi_read_in_monitor_struct.prim_arid + // // fuse_ctrl_prim_axi_read_in_monitor_struct.prim_arlock + // // fuse_ctrl_prim_axi_read_in_monitor_struct.prim_rready + // // + // Reference code; + // How to wait for signal value + // while (control_signal === 1'b1) @(posedge clk_i_i); + // + // How to assign a struct member, named xyz, from a signal. + // All available input signals listed. + // fuse_ctrl_prim_axi_read_in_monitor_struct.xyz = araddr_i; // [AW-1:0] + // fuse_ctrl_prim_axi_read_in_monitor_struct.xyz = arburst_i; // [$bits(axi_pkg::axi_burst_e)-1:0] + // fuse_ctrl_prim_axi_read_in_monitor_struct.xyz = arsize_i; // [2:0] + // fuse_ctrl_prim_axi_read_in_monitor_struct.xyz = arlen_i; // [7:0] + // fuse_ctrl_prim_axi_read_in_monitor_struct.xyz = aruser_i; // [UW-1:0] + // fuse_ctrl_prim_axi_read_in_monitor_struct.xyz = arid_i; // [IW-1:0] + // fuse_ctrl_prim_axi_read_in_monitor_struct.xyz = arlock_i; // + // fuse_ctrl_prim_axi_read_in_monitor_struct.xyz = arvalid_i; // + // fuse_ctrl_prim_axi_read_in_monitor_struct.xyz = rready_i; // + // pragma uvmf custom do_monitor begin + // UVMF_CHANGE_ME : Implement protocol monitoring. The commented reference code + // below are examples of how to capture signal values and assign them to + // structure members. All available input signals are listed. The 'while' + // code example shows how to wait for a synchronous flow control signal. This + // task should return when a complete transfer has been observed. Once this task is + // exited with captured values, it is then called again to wait for and observe + // the next transfer. One clock cycle is consumed between calls to do_monitor. + @(posedge clk_i_i); + @(posedge clk_i_i); + @(posedge clk_i_i); + @(posedge clk_i_i); + // pragma uvmf custom do_monitor end + endtask + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_random_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_random_sequence.svh new file mode 100644 index 0000000..559d975 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_random_sequence.svh @@ -0,0 +1,87 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This sequences randomizes the fuse_ctrl_prim_axi_read_in transaction and sends it +// to the UVM driver. +// +// This sequence constructs and randomizes a fuse_ctrl_prim_axi_read_in_transaction. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_read_in_random_sequence #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends fuse_ctrl_prim_axi_read_in_sequence_base #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ); + + `uvm_object_param_utils( fuse_ctrl_prim_axi_read_in_random_sequence #( + AW, + DW, + IW, + UW + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //***************************************************************** + function new(string name = ""); + super.new(name); + endfunction: new + + // **************************************************************************** + // TASK : body() + // This task is automatically executed when this sequence is started using the + // start(sequencerHandle) task. + // + task body(); + + // Construct the transaction + req=fuse_ctrl_prim_axi_read_in_transaction#( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )::type_id::create("req"); + start_item(req); + // Randomize the transaction + if(!req.randomize()) `uvm_fatal("SEQ", "fuse_ctrl_prim_axi_read_in_random_sequence::body()-fuse_ctrl_prim_axi_read_in_transaction randomization failed") + // Send the transaction to the fuse_ctrl_prim_axi_read_in_driver_bfm via the sequencer and fuse_ctrl_prim_axi_read_in_driver. + finish_item(req); + `uvm_info("SEQ", {"Response:",req.convert2string()},UVM_MEDIUM) + + endtask + +endclass: fuse_ctrl_prim_axi_read_in_random_sequence + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_responder_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_responder_sequence.svh new file mode 100644 index 0000000..2a1a833 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_responder_sequence.svh @@ -0,0 +1,83 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class can be used to provide stimulus when an interface +// has been configured to run in a responder mode. It +// will never finish by default, always going back to the driver +// and driver BFM for the next transaction with which to respond. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_read_in_responder_sequence #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends fuse_ctrl_prim_axi_read_in_sequence_base #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ); + + `uvm_object_param_utils( fuse_ctrl_prim_axi_read_in_responder_sequence #( + AW, + DW, + IW, + UW + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "fuse_ctrl_prim_axi_read_in_responder_sequence"); + super.new(name); + endfunction + + task body(); + req=fuse_ctrl_prim_axi_read_in_transaction#( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )::type_id::create("req"); + forever begin + start_item(req); + finish_item(req); + // pragma uvmf custom body begin + // UVMF_CHANGE_ME : Do something here with the resulting req item. The + // finish_item() call above will block until the req transaction is ready + // to be handled by the responder sequence. + // If this was an item that required a response, the expectation is + // that the response should be populated within this transaction now. + `uvm_info("SEQ",$sformatf("Processed txn: %s",req.convert2string()),UVM_HIGH) + // pragma uvmf custom body end + end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_sequence_base.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_sequence_base.svh new file mode 100644 index 0000000..a8775f4 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_sequence_base.svh @@ -0,0 +1,140 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the class used as the base class for all sequences +// for this interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_read_in_sequence_base #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvmf_sequence_base #( + .REQ(fuse_ctrl_prim_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .RSP(fuse_ctrl_prim_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ))); + + `uvm_object_param_utils( fuse_ctrl_prim_axi_read_in_sequence_base #( + AW, + DW, + IW, + UW + )) + + // variables + typedef fuse_ctrl_prim_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) fuse_ctrl_prim_axi_read_in_transaction_req_t; + fuse_ctrl_prim_axi_read_in_transaction_req_t req; + typedef fuse_ctrl_prim_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) fuse_ctrl_prim_axi_read_in_transaction_rsp_t; + fuse_ctrl_prim_axi_read_in_transaction_rsp_t rsp; + + // Event for identifying when a response was received from the sequencer + event new_rsp; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // TASK : get_responses() + // This task recursively gets sequence item responses from the sequencer. + // + virtual task get_responses(); + fork + begin + // Block until new rsp available + get_response(rsp); + // New rsp received. Indicate to sequence using event. + ->new_rsp; + // Display the received response transaction + `uvm_info("SEQ", {"New response transaction:",rsp.convert2string()}, UVM_MEDIUM) + end + join_none + endtask + + // **************************************************************************** + // TASK : pre_body() + // This task is called automatically when start is called with call_pre_post set to 1 (default). + // By calling get_responses() within pre_body() any derived sequences are automatically + // processing response transactions. Only un-comment this call to get_responses() if you + // have configured the interface driver to utilize the response transaction path by setting + // the configuration variable "return_transaction_response" to 1. Otherwise it is possible + // to impact runtime performance and memory utilization. + // + virtual task pre_body(); + // pragma uvmf custom pre_body begin +// get_responses(); + // pragma uvmf custom pre_body end + endtask + + // **************************************************************************** + // TASK : body() + // This task is called automatically when start is called. This sequence sends + // a req sequence item to the sequencer identified as an argument in the call + // to start. + // + virtual task body(); + // pragma uvmf custom body begin + start_item(req); + finish_item(req); + // pragma uvmf custom body end + endtask + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name =""); + super.new( name ); + // pragma uvmf custom new begin + req = fuse_ctrl_prim_axi_read_in_transaction_req_t::type_id::create("req"); + rsp = fuse_ctrl_prim_axi_read_in_transaction_rsp_t::type_id::create("rsp"); + // pragma uvmf custom new end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_transaction.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_transaction.svh new file mode 100644 index 0000000..4c11b1b --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_transaction.svh @@ -0,0 +1,239 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class defines the variables required for an fuse_ctrl_prim_axi_read_in +// transaction. Class variables to be displayed in waveform transaction +// viewing are added to the transaction viewing stream in the add_to_wave +// function. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_read_in_transaction #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvmf_transaction_base; + + `uvm_object_param_utils( fuse_ctrl_prim_axi_read_in_transaction #( + AW, + DW, + IW, + UW + )) + + rand logic [AW-1:0] prim_araddr ; + logic prim_arvalid ; + logic [$bits(axi_pkg::axi_burst_e)] prim_arburst ; + logic [2:0] prim_arsize ; + logic [7:0] prim_arlen ; + logic [UW-1:0] prim_aruser ; + logic [IW-1:0] prim_arid ; + logic prim_arlock ; + logic prim_rready ; + + //Constraints for the transaction variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //******************************************************************* + //******************************************************************* + // Macros that define structs and associated functions are + // located in fuse_ctrl_prim_axi_read_in_macros.svh + + //******************************************************************* + // Monitor macro used by fuse_ctrl_prim_axi_read_in_monitor and fuse_ctrl_prim_axi_read_in_monitor_bfm + // This struct is defined in fuse_ctrl_prim_axi_read_in_macros.svh + `fuse_ctrl_prim_axi_read_in_MONITOR_STRUCT + fuse_ctrl_prim_axi_read_in_monitor_s fuse_ctrl_prim_axi_read_in_monitor_struct; + //******************************************************************* + // FUNCTION: to_monitor_struct() + // This function packs transaction variables into a fuse_ctrl_prim_axi_read_in_monitor_s + // structure. The function returns the handle to the fuse_ctrl_prim_axi_read_in_monitor_struct. + // This function is defined in fuse_ctrl_prim_axi_read_in_macros.svh + `fuse_ctrl_prim_axi_read_in_TO_MONITOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_monitor_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_prim_axi_read_in_macros.svh + `fuse_ctrl_prim_axi_read_in_FROM_MONITOR_STRUCT_FUNCTION + + //******************************************************************* + // Initiator macro used by fuse_ctrl_prim_axi_read_in_driver and fuse_ctrl_prim_axi_read_in_driver_bfm + // to communicate initiator driven data to fuse_ctrl_prim_axi_read_in_driver_bfm. + // This struct is defined in fuse_ctrl_prim_axi_read_in_macros.svh + `fuse_ctrl_prim_axi_read_in_INITIATOR_STRUCT + fuse_ctrl_prim_axi_read_in_initiator_s fuse_ctrl_prim_axi_read_in_initiator_struct; + //******************************************************************* + // FUNCTION: to_initiator_struct() + // This function packs transaction variables into a fuse_ctrl_prim_axi_read_in_initiator_s + // structure. The function returns the handle to the fuse_ctrl_prim_axi_read_in_initiator_struct. + // This function is defined in fuse_ctrl_prim_axi_read_in_macros.svh + `fuse_ctrl_prim_axi_read_in_TO_INITIATOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_initiator_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_prim_axi_read_in_macros.svh + `fuse_ctrl_prim_axi_read_in_FROM_INITIATOR_STRUCT_FUNCTION + + //******************************************************************* + // Responder macro used by fuse_ctrl_prim_axi_read_in_driver and fuse_ctrl_prim_axi_read_in_driver_bfm + // to communicate Responder driven data to fuse_ctrl_prim_axi_read_in_driver_bfm. + // This struct is defined in fuse_ctrl_prim_axi_read_in_macros.svh + `fuse_ctrl_prim_axi_read_in_RESPONDER_STRUCT + fuse_ctrl_prim_axi_read_in_responder_s fuse_ctrl_prim_axi_read_in_responder_struct; + //******************************************************************* + // FUNCTION: to_responder_struct() + // This function packs transaction variables into a fuse_ctrl_prim_axi_read_in_responder_s + // structure. The function returns the handle to the fuse_ctrl_prim_axi_read_in_responder_struct. + // This function is defined in fuse_ctrl_prim_axi_read_in_macros.svh + `fuse_ctrl_prim_axi_read_in_TO_RESPONDER_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_responder_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_prim_axi_read_in_macros.svh + `fuse_ctrl_prim_axi_read_in_FROM_RESPONDER_STRUCT_FUNCTION + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + endfunction + + // **************************************************************************** + // FUNCTION: convert2string() + // This function converts all variables in this class to a single string for + // logfile reporting. + // + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + // UVMF_CHANGE_ME : Customize format if desired. + return $sformatf("prim_araddr:0x%x prim_arvalid:0x%x prim_arburst:0x%x prim_arsize:0x%x prim_arlen:0x%x prim_aruser:0x%x prim_arid:0x%x prim_arlock:0x%x prim_rready:0x%x ",prim_araddr,prim_arvalid,prim_arburst,prim_arsize,prim_arlen,prim_aruser,prim_arid,prim_arlock,prim_rready); + // pragma uvmf custom convert2string end + endfunction + + //******************************************************************* + // FUNCTION: do_print() + // This function is automatically called when the .print() function + // is called on this class. + // + virtual function void do_print(uvm_printer printer); + // pragma uvmf custom do_print begin + // UVMF_CHANGE_ME : Current contents of do_print allows for the use of UVM 1.1d, 1.2 or P1800.2. + // Update based on your own printing preference according to your preferred UVM version + $display(convert2string()); + // pragma uvmf custom do_print end + endfunction + + //******************************************************************* + // FUNCTION: do_compare() + // This function is automatically called when the .compare() function + // is called on this class. + // + virtual function bit do_compare (uvm_object rhs, uvm_comparer comparer); + fuse_ctrl_prim_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) RHS; + if (!$cast(RHS,rhs)) return 0; + // pragma uvmf custom do_compare begin + // UVMF_CHANGE_ME : Eliminate comparison of variables not to be used for compare + return (super.do_compare(rhs,comparer) + ); + // pragma uvmf custom do_compare end + endfunction + + //******************************************************************* + // FUNCTION: do_copy() + // This function is automatically called when the .copy() function + // is called on this class. + // + virtual function void do_copy (uvm_object rhs); + fuse_ctrl_prim_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) RHS; + assert($cast(RHS,rhs)); + // pragma uvmf custom do_copy begin + super.do_copy(rhs); + this.prim_araddr = RHS.prim_araddr; + this.prim_arvalid = RHS.prim_arvalid; + this.prim_arburst = RHS.prim_arburst; + this.prim_arsize = RHS.prim_arsize; + this.prim_arlen = RHS.prim_arlen; + this.prim_aruser = RHS.prim_aruser; + this.prim_arid = RHS.prim_arid; + this.prim_arlock = RHS.prim_arlock; + this.prim_rready = RHS.prim_rready; + // pragma uvmf custom do_copy end + endfunction + + // **************************************************************************** + // FUNCTION: add_to_wave() + // This function is used to display variables in this class in the waveform + // viewer. The start_time and end_time variables must be set before this + // function is called. If the start_time and end_time variables are not set + // the transaction will be hidden at 0ns on the waveform display. + // + virtual function void add_to_wave(int transaction_viewing_stream_h); + `ifdef QUESTA + if (transaction_view_h == 0) begin + transaction_view_h = $begin_transaction(transaction_viewing_stream_h,"fuse_ctrl_prim_axi_read_in_transaction",start_time); + end + super.add_to_wave(transaction_view_h); + // pragma uvmf custom add_to_wave begin + // UVMF_CHANGE_ME : Color can be applied to transaction entries based on content, example below + // case() + // 1 : $add_color(transaction_view_h,"red"); + // default : $add_color(transaction_view_h,"grey"); + // endcase + // UVMF_CHANGE_ME : Eliminate transaction variables not wanted in transaction viewing in the waveform viewer + $add_attribute(transaction_view_h,prim_araddr,"prim_araddr"); + $add_attribute(transaction_view_h,prim_arvalid,"prim_arvalid"); + $add_attribute(transaction_view_h,prim_arburst,"prim_arburst"); + $add_attribute(transaction_view_h,prim_arsize,"prim_arsize"); + $add_attribute(transaction_view_h,prim_arlen,"prim_arlen"); + $add_attribute(transaction_view_h,prim_aruser,"prim_aruser"); + $add_attribute(transaction_view_h,prim_arid,"prim_arid"); + $add_attribute(transaction_view_h,prim_arlock,"prim_arlock"); + $add_attribute(transaction_view_h,prim_rready,"prim_rready"); + // pragma uvmf custom add_to_wave end + $end_transaction(transaction_view_h,end_time); + $free_transaction(transaction_view_h); + `endif // QUESTA + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_transaction_coverage.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_transaction_coverage.svh new file mode 100644 index 0000000..23fe17e --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_transaction_coverage.svh @@ -0,0 +1,107 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class records fuse_ctrl_prim_axi_read_in transaction information using +// a covergroup named fuse_ctrl_prim_axi_read_in_transaction_cg. An instance of this +// coverage component is instantiated in the uvmf_parameterized_agent +// if the has_coverage flag is set. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_read_in_transaction_coverage #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvm_subscriber #(.T(fuse_ctrl_prim_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ))); + + `uvm_component_param_utils( fuse_ctrl_prim_axi_read_in_transaction_coverage #( + AW, + DW, + IW, + UW + )) + + T coverage_trans; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + covergroup fuse_ctrl_prim_axi_read_in_transaction_cg; + // pragma uvmf custom covergroup begin + // UVMF_CHANGE_ME : Add coverage bins, crosses, exclusions, etc. according to coverage needs. + option.auto_bin_max=1024; + option.per_instance=1; + prim_araddr: coverpoint coverage_trans.prim_araddr; + prim_arvalid: coverpoint coverage_trans.prim_arvalid; + prim_arburst: coverpoint coverage_trans.prim_arburst; + prim_arsize: coverpoint coverage_trans.prim_arsize; + prim_arlen: coverpoint coverage_trans.prim_arlen; + prim_aruser: coverpoint coverage_trans.prim_aruser; + prim_arid: coverpoint coverage_trans.prim_arid; + prim_arlock: coverpoint coverage_trans.prim_arlock; + prim_rready: coverpoint coverage_trans.prim_rready; + // pragma uvmf custom covergroup end + endgroup + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new(string name="", uvm_component parent=null); + super.new(name,parent); + fuse_ctrl_prim_axi_read_in_transaction_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that transaction variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + endfunction + + // **************************************************************************** + // FUNCTION : build_phase() + // This function is the standard UVM build_phase. + // + function void build_phase(uvm_phase phase); + fuse_ctrl_prim_axi_read_in_transaction_cg.set_inst_name($sformatf("fuse_ctrl_prim_axi_read_in_transaction_cg_%s",get_full_name())); + endfunction + + // **************************************************************************** + // FUNCTION: write (T t) + // This function is automatically executed when a transaction arrives on the + // analysis_export. It copies values from the variables in the transaction + // to local variables used to collect functional coverage. + // + virtual function void write (T t); + `uvm_info("COV","Received transaction",UVM_HIGH); + coverage_trans = t; + fuse_ctrl_prim_axi_read_in_transaction_cg.sample(); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_typedefs.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_typedefs.svh new file mode 100644 index 0000000..f2a7bdb --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_typedefs.svh @@ -0,0 +1,34 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the host server when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_typedefs_hdl.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_typedefs_hdl.svh new file mode 100644 index 0000000..0d58518 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_typedefs_hdl.svh @@ -0,0 +1,35 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the emulator when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/yaml/fuse_ctrl_prim_axi_read_in_interface.yaml b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/yaml/fuse_ctrl_prim_axi_read_in_interface.yaml new file mode 100644 index 0000000..722b476 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/yaml/fuse_ctrl_prim_axi_read_in_interface.yaml @@ -0,0 +1,121 @@ +uvmf: + interfaces: + fuse_ctrl_prim_axi_read_in: + clock: clk_i + config_constraints: [] + config_vars: [] + existing_library_component: 'True' + gen_inbound_streaming_driver: 'False' + hdl_pkg_parameters: [] + hdl_typedefs: [] + hvl_pkg_parameters: [] + hvl_typedefs: [] + parameters: + - name: AW + type: int + value: '32' + - name: DW + type: int + value: '32' + - name: IW + type: int + value: '3' + - name: UW + type: int + value: '32' + ports: + - dir: output + name: araddr + reset_value: '''bz' + width: '[''AW'']' + - dir: output + name: arburst + reset_value: '''bz' + width: '[''$bits(axi_pkg::axi_burst_e)'']' + - dir: output + name: arsize + reset_value: '''bz' + width: '3' + - dir: output + name: arlen + reset_value: '''bz' + width: '8' + - dir: output + name: aruser + reset_value: '''bz' + width: '[''UW'']' + - dir: output + name: arid + reset_value: '''bz' + width: '[''IW'']' + - dir: output + name: arlock + reset_value: '''bz' + width: '1' + - dir: output + name: arvalid + reset_value: '''bz' + width: '1' + - dir: output + name: rready + reset_value: '''bz' + width: '1' + reset: rst_ni + reset_assertion_level: 'False' + transaction_constraints: [] + transaction_vars: + - comment: '' + iscompare: 'False' + isrand: 'True' + name: prim_araddr + type: logic [AW-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: prim_arvalid + type: logic + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: prim_arburst + type: logic [$bits(axi_pkg::axi_burst_e)] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: prim_arsize + type: logic [2:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: prim_arlen + type: logic [7:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: prim_aruser + type: logic [UW-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: prim_arid + type: logic [IW-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: prim_arlock + type: logic + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: prim_rready + type: logic + unpacked_dimension: '' + use_dpi_link: 'False' diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/.project b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/.project new file mode 100644 index 0000000..a150c26 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/.project @@ -0,0 +1,30 @@ + + + fuse_ctrl_prim_axi_read_out_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/.svproject b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/.svproject new file mode 100644 index 0000000..07283b0 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/Makefile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/Makefile new file mode 100644 index 0000000..c82fb10 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/Makefile @@ -0,0 +1,66 @@ +# fuse_ctrl_prim_axi_read_out interface packages source +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +fuse_ctrl_prim_axi_read_out_PKG = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_read_out_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_filelist_hvl.f + +fuse_ctrl_prim_axi_read_out_PKG_HDL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_read_out_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_filelist_hdl.f + +fuse_ctrl_prim_axi_read_out_PKG_XRTL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_read_out_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_filelist_xrtl.f + +COMP_fuse_ctrl_prim_axi_read_out_PKG_TGT_0 = q_comp_fuse_ctrl_prim_axi_read_out_pkg +COMP_fuse_ctrl_prim_axi_read_out_PKG_TGT_1 = v_comp_fuse_ctrl_prim_axi_read_out_pkg +COMP_fuse_ctrl_prim_axi_read_out_PKG_TGT = $(COMP_fuse_ctrl_prim_axi_read_out_PKG_TGT_$(USE_VELOCE)) + +comp_fuse_ctrl_prim_axi_read_out_pkg: $(COMP_fuse_ctrl_prim_axi_read_out_PKG_TGT) + +q_comp_fuse_ctrl_prim_axi_read_out_pkg: + $(HDL_COMP_CMD) $(fuse_ctrl_prim_axi_read_out_PKG_HDL) + $(HVL_COMP_CMD) $(fuse_ctrl_prim_axi_read_out_PKG) + $(HDL_COMP_CMD) $(fuse_ctrl_prim_axi_read_out_PKG_XRTL) + +v_comp_fuse_ctrl_prim_axi_read_out_pkg: + $(HVL_COMP_CMD) $(fuse_ctrl_prim_axi_read_out_PKG_HDL) + $(HVL_COMP_CMD) $(fuse_ctrl_prim_axi_read_out_PKG) + $(VELANALYZE_CMD) $(fuse_ctrl_prim_axi_read_out_PKG_HDL) + $(VELANALYZE_HVL_CMD) $(fuse_ctrl_prim_axi_read_out_PKG) + $(HDL_COMP_CMD) $(fuse_ctrl_prim_axi_read_out_PKG_XRTL) + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export fuse_ctrl_prim_axi_read_out_IF_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/dpi + +C_FILE_COMPILE_LIST_fuse_ctrl_prim_axi_read_out_pkg = \ + +O_FILE_COMPILE_LIST_fuse_ctrl_prim_axi_read_out_pkg = $(notdir $(C_FILE_COMPILE_LIST_fuse_ctrl_prim_axi_read_out_pkg:.c=.o)) + +GCC_COMP_ARGS_fuse_ctrl_prim_axi_read_out_pkg += -I$(fuse_ctrl_prim_axi_read_out_IF_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_fuse_ctrl_prim_axi_read_out_pkg += $(fuse_ctrl_prim_axi_read_out_IF_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_fuse_ctrl_prim_axi_read_out_pkg += \ + \ + -o .so + +comp_fuse_ctrl_prim_axi_read_out_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Interface C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_fuse_ctrl_prim_axi_read_out_pkg) $(C_FILE_COMPILE_LIST_fuse_ctrl_prim_axi_read_out_pkg) + @echo "--------------------------------" + @echo "Linking Interface C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_fuse_ctrl_prim_axi_read_out_pkg) $(O_FILE_COMPILE_LIST_fuse_ctrl_prim_axi_read_out_pkg) + @echo "--------------------------------" + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/compile.do b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/compile.do new file mode 100644 index 0000000..1f3f425 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/compile.do @@ -0,0 +1,14 @@ +# Tcl do file for compile of fuse_ctrl_prim_axi_read_out interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_read_out_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_filelist_hdl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_read_out_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_filelist_hvl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_read_out_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_filelist_xrtl.f \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out.compile new file mode 100644 index 0000000..3ae619a --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out.compile @@ -0,0 +1,3 @@ +needs: + - fuse_ctrl_prim_axi_read_out_hvl.compile + - fuse_ctrl_prim_axi_read_out_hdl.compile diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_bfm.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_bfm.vinfo new file mode 100644 index 0000000..804bede --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_bfm.vinfo @@ -0,0 +1,6 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use fuse_ctrl_prim_axi_read_out_pkg_hdl.vinfo ++incdir+@vinfodir +src/fuse_ctrl_prim_axi_read_out_if.sv +src/fuse_ctrl_prim_axi_read_out_driver_bfm.sv +src/fuse_ctrl_prim_axi_read_out_monitor_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_common.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_common.compile new file mode 100644 index 0000000..473bd10 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_common.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +incdir: + - . + - ${uvm_path}/src +src: + - fuse_ctrl_prim_axi_read_out_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_filelist_hdl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_filelist_hdl.f new file mode 100644 index 0000000..9915fab --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_filelist_hdl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_filelist_hvl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_filelist_hvl.f new file mode 100644 index 0000000..c105f6a --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_filelist_hvl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_pkg.sv \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_filelist_xrtl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_filelist_xrtl.f new file mode 100644 index 0000000..efd90f5 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_filelist_xrtl.f @@ -0,0 +1,3 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_if.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_monitor_bfm.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_driver_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_hdl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_hdl.compile new file mode 100644 index 0000000..3110b63 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_hdl.compile @@ -0,0 +1,9 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ./fuse_ctrl_prim_axi_read_out_common.compile +incdir: + - . +src: + - src/fuse_ctrl_prim_axi_read_out_if.sv + - src/fuse_ctrl_prim_axi_read_out_monitor_bfm.sv + - src/fuse_ctrl_prim_axi_read_out_driver_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_hvl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_hvl.compile new file mode 100644 index 0000000..5f022ac --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_hvl.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ./fuse_ctrl_prim_axi_read_out_common.compile +incdir: + - . +src: + - fuse_ctrl_prim_axi_read_out_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_pkg.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_pkg.sv new file mode 100644 index 0000000..d12ebea --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_pkg.sv @@ -0,0 +1,91 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - + +// - +// - +// - + +// - +// - +// - + +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_prim_axi_read_out_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg_hdl::*; + import uvmf_base_pkg::*; + import fuse_ctrl_prim_axi_read_out_pkg_hdl::*; + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + `include "src/fuse_ctrl_prim_axi_read_out_macros.svh" + + export fuse_ctrl_prim_axi_read_out_pkg_hdl::*; + + + + // Parameters defined as HVL parameters + + `include "src/fuse_ctrl_prim_axi_read_out_typedefs.svh" + `include "src/fuse_ctrl_prim_axi_read_out_transaction.svh" + + `include "src/fuse_ctrl_prim_axi_read_out_configuration.svh" + `include "src/fuse_ctrl_prim_axi_read_out_driver.svh" + `include "src/fuse_ctrl_prim_axi_read_out_monitor.svh" + + `include "src/fuse_ctrl_prim_axi_read_out_transaction_coverage.svh" + `include "src/fuse_ctrl_prim_axi_read_out_sequence_base.svh" + `include "src/fuse_ctrl_prim_axi_read_out_random_sequence.svh" + + `include "src/fuse_ctrl_prim_axi_read_out_responder_sequence.svh" + `include "src/fuse_ctrl_prim_axi_read_out2reg_adapter.svh" + + `include "src/fuse_ctrl_prim_axi_read_out_agent.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new interface sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the interface package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_pkg.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_pkg.vinfo new file mode 100644 index 0000000..ce44bd3 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_pkg.vinfo @@ -0,0 +1,4 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use fuse_ctrl_prim_axi_read_out_pkg_hdl.vinfo ++incdir+@vinfodir +fuse_ctrl_prim_axi_read_out_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_pkg_hdl.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_pkg_hdl.sv new file mode 100644 index 0000000..3a6641b --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_pkg_hdl.sv @@ -0,0 +1,52 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that needs to be compiled and synthesized +// for running on Veloce. +// +// CONTAINS: +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_prim_axi_read_out_pkg_hdl; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HDL parameters + + `include "src/fuse_ctrl_prim_axi_read_out_typedefs_hdl.svh" + `include "src/fuse_ctrl_prim_axi_read_out_macros.svh" + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_pkg_hdl.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_pkg_hdl.vinfo new file mode 100644 index 0000000..d2706f6 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_pkg_hdl.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +fuse_ctrl_prim_axi_read_out_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_pkg_sve.F b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_pkg_sve.F new file mode 100644 index 0000000..e27a449 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_pkg_sve.F @@ -0,0 +1,10 @@ +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + ++incdir+. +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_filelist_hdl.f +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_filelist_hvl.f diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out2reg_adapter.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out2reg_adapter.svh new file mode 100644 index 0000000..b8395bb --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out2reg_adapter.svh @@ -0,0 +1,137 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the UVM register adapter for the fuse_ctrl_prim_axi_read_out interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_read_out2reg_adapter #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvm_reg_adapter; + + `uvm_object_param_utils( fuse_ctrl_prim_axi_read_out2reg_adapter #( + AW, + DW, + IW, + UW + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //-------------------------------------------------------------------- + // new + //-------------------------------------------------------------------- + function new (string name = "fuse_ctrl_prim_axi_read_out2reg_adapter" ); + super.new(name); + // pragma uvmf custom new begin + // UVMF_CHANGE_ME : Configure the adapter regarding byte enables and provides response. + + // Does the protocol the Agent is modeling support byte enables? + // 0 = NO + // 1 = YES + supports_byte_enable = 0; + + // Does the Agent's Driver provide separate response sequence items? + // i.e. Does the driver call seq_item_port.put() + // and do the sequences call get_response()? + // 0 = NO + // 1 = YES + provides_responses = 0; + // pragma uvmf custom new end + + endfunction: new + + //-------------------------------------------------------------------- + // reg2bus + //-------------------------------------------------------------------- + virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw); + + fuse_ctrl_prim_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) trans_h = fuse_ctrl_prim_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )::type_id::create("trans_h"); + + // pragma uvmf custom reg2bus begin + // UVMF_CHANGE_ME : Fill in the reg2bus adapter mapping registe fields to protocol fields. + + //Adapt the following for your sequence item type + // trans_h.op = (rw.kind == UVM_READ) ? WB_READ : WB_WRITE; + //Copy over address + // trans_h.addr = rw.addr; + //Copy over write data + // trans_h.data = rw.data; + + // pragma uvmf custom reg2bus end + + // Return the adapted transaction + return trans_h; + + endfunction: reg2bus + + //-------------------------------------------------------------------- + // bus2reg + //-------------------------------------------------------------------- + virtual function void bus2reg(uvm_sequence_item bus_item, + ref uvm_reg_bus_op rw); + fuse_ctrl_prim_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) trans_h; + if (!$cast(trans_h, bus_item)) begin + `uvm_fatal("ADAPT","Provided bus_item is not of the correct type") + return; + end + // pragma uvmf custom bus2reg begin + // UVMF_CHANGE_ME : Fill in the bus2reg adapter mapping protocol fields to register fields. + //Adapt the following for your sequence item type + //Copy over instruction type + // rw.kind = (trans_h.op == WB_WRITE) ? UVM_WRITE : UVM_READ; + //Copy over address + // rw.addr = trans_h.addr; + //Copy over read data + // rw.data = trans_h.data; + //Check for errors on the bus and return UVM_NOT_OK if there is an error + // rw.status = UVM_IS_OK; + // pragma uvmf custom bus2reg end + + endfunction: bus2reg + +endclass : fuse_ctrl_prim_axi_read_out2reg_adapter + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_agent.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_agent.svh new file mode 100644 index 0000000..48eac05 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_agent.svh @@ -0,0 +1,102 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: Protocol specific agent class definition +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_read_out_agent #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvmf_parameterized_agent #( + .CONFIG_T(fuse_ctrl_prim_axi_read_out_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .DRIVER_T(fuse_ctrl_prim_axi_read_out_driver #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .MONITOR_T(fuse_ctrl_prim_axi_read_out_monitor #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .COVERAGE_T(fuse_ctrl_prim_axi_read_out_transaction_coverage #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .TRANS_T(fuse_ctrl_prim_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )) + ); + + `uvm_component_param_utils( fuse_ctrl_prim_axi_read_out_agent #( + AW, + DW, + IW, + UW + )) + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** + // FUNCTION: build_phase + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + if (configuration.active_passive == ACTIVE) begin + // Place sequencer handle into configuration object + // so that it may be retrieved from configuration + // rather than using uvm_config_db + configuration.sequencer = this.sequencer; + end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_configuration.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_configuration.svh new file mode 100644 index 0000000..ed0b5b2 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_configuration.svh @@ -0,0 +1,233 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class contains all variables and functions used +// to configure the fuse_ctrl_prim_axi_read_out agent and its bfm's. It gets the +// bfm's from the uvm_config_db for use by the agent. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_read_out_configuration #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvmf_parameterized_agent_configuration_base #( + .DRIVER_BFM_BIND_T(virtual fuse_ctrl_prim_axi_read_out_driver_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .MONITOR_BFM_BIND_T( virtual fuse_ctrl_prim_axi_read_out_monitor_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ))); + + `uvm_object_param_utils( fuse_ctrl_prim_axi_read_out_configuration #( + AW, + DW, + IW, + UW + )) + + + // Sequencer handle populated by agent + uvm_sequencer #(fuse_ctrl_prim_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) ) sequencer; + + //Constraints for the configuration variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + covergroup fuse_ctrl_prim_axi_read_out_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + // pragma uvmf custom covergroup end + endgroup + + //******************************************************************* + //******************************************************************* + // Structure used to pass configuration variables to monitor and driver BFM's. + // Use to_struct function to pack variables into structure. + // Use from_struct function to unpack variables from structure. + // This structure is defined in fuse_ctrl_prim_axi_read_out_macros.svh + `fuse_ctrl_prim_axi_read_out_CONFIGURATION_STRUCT + fuse_ctrl_prim_axi_read_out_configuration_s fuse_ctrl_prim_axi_read_out_configuration_struct; + //******************************************************************* + // FUNCTION: to_struct() + // This function packs variables into a fuse_ctrl_prim_axi_read_out_configuration_s + // structure. The function returns the handle to the fuse_ctrl_prim_axi_read_out_configuration_struct. + // This function is defined in fuse_ctrl_prim_axi_read_out_macros.svh + `fuse_ctrl_prim_axi_read_out_CONFIGURATION_TO_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_struct() + // This function unpacks the struct provided as an argument into + // variables of this class. + // This function is defined in fuse_ctrl_prim_axi_read_out_macros.svh + `fuse_ctrl_prim_axi_read_out_CONFIGURATION_FROM_STRUCT_FUNCTION + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + // Construct the covergroup for this configuration class + fuse_ctrl_prim_axi_read_out_configuration_cg = new; + endfunction + + // **************************************************************************** + // FUNCTION: post_randomize() + // This function is automatically called after the randomize() function + // is executed. + // + function void post_randomize(); + super.post_randomize(); + fuse_ctrl_prim_axi_read_out_configuration_cg.sample(); + endfunction + + // **************************************************************************** + // FUNCTION: initialize + // This function causes the configuration to retrieve + // its virtual interface handle from the uvm_config_db. + // This function also makes itself available to its + // agent through the uvm_config_db. + // + // ARGUMENTS: + // uvmf_active_passive_t activity: + // This argument identifies the simulation level + // as either BLOCK, CHIP, SIMULATION, etc. + // + // AGENT_PATH: + // This argument identifies the path to this + // configurations agent. This configuration + // makes itself available to the agent specified + // by agent_path by placing itself into the + // uvm_config_db. + // + // INTERFACE_NAME: + // This argument identifies the string name of + // this configurations BFM's. This string + // name is used to retrieve the driver and + // monitor BFM from the uvm_config_db. + // + virtual function void initialize(uvmf_active_passive_t activity, + string agent_path, + string interface_name); + + super.initialize( activity, agent_path, interface_name); + // The covergroup is given the same name as the interface + fuse_ctrl_prim_axi_read_out_configuration_cg.set_inst_name(interface_name); + + // This configuration places itself into the uvm_config_db for the agent, identified by the agent_path variable, to retrieve. + uvm_config_db #( fuse_ctrl_prim_axi_read_out_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + )::set( null ,agent_path,UVMF_AGENT_CONFIG, this ); + + // This configuration also places itself in the config db using the same identifier used by the interface. This allows users to access + // configuration variables and the interface through the bfm api class rather than directly accessing the BFM. This is useful for + // accessingthe BFM when using Veloce + uvm_config_db #( fuse_ctrl_prim_axi_read_out_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + )::set( null ,UVMF_CONFIGURATIONS, interface_name, this ); + + fuse_ctrl_prim_axi_read_out_configuration_cg.set_inst_name($sformatf("fuse_ctrl_prim_axi_read_out_configuration_cg_%s",get_full_name())); + +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. + `uvm_info("CFG", + $psprintf("The agent at '%s' is using interface named %s has the following parameters: AW=%x DW=%x IW=%x UW=%x ", agent_path, interface_name, AW ,DW ,IW ,UW ), + UVM_DEBUG) + + // pragma uvmf custom initialize begin + // This controls whether or not the agent returns a transaction handle in the driver when calling + // item_done() back into the sequencer or not. If set to 1, a transaction is sent back which means + // the sequence on the other end must use the get_response() part of the driver/sequence API. If + // this doesn't occur, there will eventually be response_queue overflow errors during the test. + return_transaction_response = 1'b0; + + // pragma uvmf custom initialize end + + endfunction + + // **************************************************************************** + // TASK: wait_for_reset + // *[Required]* Blocks until reset is released. The wait_for_reset operation is performed + // by a task in the monitor bfm. + virtual task wait_for_reset(); + monitor_bfm.wait_for_reset(); + endtask + + // **************************************************************************** + // TASK: wait_for_num_clocks + // *[Required]* Blocks until specified number of clocks have elapsed. The wait_for_num_clocks + // operation is performed by a task in the monitor bfm. + virtual task wait_for_num_clocks(int clocks); + monitor_bfm.wait_for_num_clocks(clocks); + endtask + + // **************************************************************************** + // FUNCTION : convert2string() + // This function is used to convert variables in this class into a string for log messaging. + // + virtual function string convert2string (); + // pragma uvmf custom convert2string begin + return $sformatf(""); + // pragma uvmf custom convert2string end + endfunction + + // **************************************************************************** + // FUNCTION: get_sequencer + function uvm_sequencer #(fuse_ctrl_prim_axi_read_out_transaction#( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )) get_sequencer(); + return sequencer; + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_driver.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_driver.svh new file mode 100644 index 0000000..4b50877 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_driver.svh @@ -0,0 +1,135 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class passes transactions between the sequencer +// and the BFM driver interface. It accesses the driver BFM +// through the bfm handle. This driver +// passes transactions to the driver BFM through the access +// task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_read_out_driver #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvmf_driver_base #( + .CONFIG_T(fuse_ctrl_prim_axi_read_out_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) ), + .BFM_BIND_T(virtual fuse_ctrl_prim_axi_read_out_driver_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) ), + .REQ(fuse_ctrl_prim_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) ), + .RSP(fuse_ctrl_prim_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) )); + + `uvm_component_param_utils( fuse_ctrl_prim_axi_read_out_driver #( + AW, + DW, + IW, + UW + )) +//******************************************************************* +// Macros that define structs located in fuse_ctrl_prim_axi_read_out_macros.svh +//******************************************************************* +// Initiator macro used by fuse_ctrl_prim_axi_read_out_driver and fuse_ctrl_prim_axi_read_out_driver_bfm +// to communicate initiator driven data to fuse_ctrl_prim_axi_read_out_driver_bfm. +`fuse_ctrl_prim_axi_read_out_INITIATOR_STRUCT + fuse_ctrl_prim_axi_read_out_initiator_s fuse_ctrl_prim_axi_read_out_initiator_struct; +//******************************************************************* +// Responder macro used by fuse_ctrl_prim_axi_read_out_driver and fuse_ctrl_prim_axi_read_out_driver_bfm +// to communicate Responder driven data to fuse_ctrl_prim_axi_read_out_driver_bfm. +`fuse_ctrl_prim_axi_read_out_RESPONDER_STRUCT + fuse_ctrl_prim_axi_read_out_responder_s fuse_ctrl_prim_axi_read_out_responder_struct; + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent=null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the driver BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// driver BFM. This allows the driver BFM to call tasks and function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// **************************************************************************** +// This task is called by the run_phase in uvmf_driver_base. + virtual task access( inout REQ txn ); +// pragma uvmf custom access begin + if (configuration.initiator_responder==RESPONDER) begin + // Complete current transfer and wait for next transfer + bfm.respond_and_wait_for_next_transfer( + fuse_ctrl_prim_axi_read_out_initiator_struct, + txn.to_responder_struct() + ); + // Unpack information about initiated transfer received by this responder + txn.from_initiator_struct(fuse_ctrl_prim_axi_read_out_initiator_struct); + end else begin + // Initiate a transfer and get response + bfm.initiate_and_get_response( + txn.to_initiator_struct(), + fuse_ctrl_prim_axi_read_out_responder_struct + ); + // Unpack transfer response information received by this initiator + txn.from_responder_struct(fuse_ctrl_prim_axi_read_out_responder_struct); + end +// pragma uvmf custom access end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_driver_bfm.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_driver_bfm.sv new file mode 100644 index 0000000..6e215d6 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_driver_bfm.sv @@ -0,0 +1,350 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This interface performs the fuse_ctrl_prim_axi_read_out signal driving. It is +// accessed by the uvm fuse_ctrl_prim_axi_read_out driver through a virtual interface +// handle in the fuse_ctrl_prim_axi_read_out configuration. It drives the singals passed +// in through the port connection named bus of type fuse_ctrl_prim_axi_read_out_if. +// +// Input signals from the fuse_ctrl_prim_axi_read_out_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// This bfm drives signals with a _o suffix. These signals +// are driven onto signals within fuse_ctrl_prim_axi_read_out_if based on INITIATOR/RESPONDER and/or +// ARBITRATION/GRANT status. +// +// The output signal connections are as follows: +// signal_o -> bus.signal +// +// +// Interface functions and tasks used by UVM components: +// +// configure: +// This function gets configuration attributes from the +// UVM driver to set any required BFM configuration +// variables such as 'initiator_responder'. +// +// initiate_and_get_response: +// This task is used to perform signaling activity for initiating +// a protocol transfer. The task initiates the transfer, using +// input data from the initiator struct. Then the task captures +// response data, placing the data into the response struct. +// The response struct is returned to the driver class. +// +// respond_and_wait_for_next_transfer: +// This task is used to complete a current transfer as a responder +// and then wait for the initiator to start the next transfer. +// The task uses data in the responder struct to drive protocol +// signals to complete the transfer. The task then waits for +// the next transfer. Once the next transfer begins, data from +// the initiator is placed into the initiator struct and sent +// to the responder sequence for processing to determine +// what data to respond with. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_prim_axi_read_out_pkg_hdl::*; +`include "src/fuse_ctrl_prim_axi_read_out_macros.svh" + +interface fuse_ctrl_prim_axi_read_out_driver_bfm #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + (fuse_ctrl_prim_axi_read_out_if bus); + // The following pragma and additional ones in-lined further below are for running this BFM on Veloce + // pragma attribute fuse_ctrl_prim_axi_read_out_driver_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: AW=%x DW=%x IW=%x UW=%x ", AW,DW,IW,UW), + UVM_DEBUG) +end +`endif + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + tri clk_i_i; + tri rst_ni_i; + + // Signal list (all signals are capable of being inputs and outputs for the sake + // of supporting both INITIATOR and RESPONDER mode operation. Expectation is that + // directionality in the config file was from the point-of-view of the INITIATOR + + // INITIATOR mode input signals + tri arready_i; + reg arready_o = 'bz; + tri [DW-1:0] rdata_i; + reg [DW-1:0] rdata_o = 'bz; + tri rresp_i; + reg rresp_o = 'bz; + tri rid_i; + reg rid_o = 'bz; + tri rlast_i; + reg rlast_o = 'bz; + tri rvalid_i; + reg rvalid_o = 'bz; + + // INITIATOR mode output signals + + // Bi-directional signals + + + assign clk_i_i = bus.clk_i; + assign rst_ni_i = bus.rst_ni; + + // These are signals marked as 'input' by the config file, but the signals will be + // driven by this BFM if put into RESPONDER mode (flipping all signal directions around) + assign arready_i = bus.arready; + assign bus.arready = (initiator_responder == RESPONDER) ? arready_o : 'bz; + assign rdata_i = bus.rdata; + assign bus.rdata = (initiator_responder == RESPONDER) ? rdata_o : 'bz; + assign rresp_i = bus.rresp; + assign bus.rresp = (initiator_responder == RESPONDER) ? rresp_o : 'bz; + assign rid_i = bus.rid; + assign bus.rid = (initiator_responder == RESPONDER) ? rid_o : 'bz; + assign rlast_i = bus.rlast; + assign bus.rlast = (initiator_responder == RESPONDER) ? rlast_o : 'bz; + assign rvalid_i = bus.rvalid; + assign bus.rvalid = (initiator_responder == RESPONDER) ? rvalid_o : 'bz; + + + // These are signals marked as 'output' by the config file, but the outputs will + // not be driven by this BFM unless placed in INITIATOR mode. + + // Proxy handle to UVM driver + fuse_ctrl_prim_axi_read_out_pkg::fuse_ctrl_prim_axi_read_out_driver #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) proxy; + // pragma tbx oneway proxy.my_function_name_in_uvm_driver + + // **************************************************************************** + // **************************************************************************** + // Macros that define structs located in fuse_ctrl_prim_axi_read_out_macros.svh + // **************************************************************************** + // Struct for passing configuration data from fuse_ctrl_prim_axi_read_out_driver to this BFM + // **************************************************************************** + `fuse_ctrl_prim_axi_read_out_CONFIGURATION_STRUCT + // **************************************************************************** + // Structs for INITIATOR and RESPONDER data flow + //******************************************************************* + // Initiator macro used by fuse_ctrl_prim_axi_read_out_driver and fuse_ctrl_prim_axi_read_out_driver_bfm + // to communicate initiator driven data to fuse_ctrl_prim_axi_read_out_driver_bfm. + `fuse_ctrl_prim_axi_read_out_INITIATOR_STRUCT + fuse_ctrl_prim_axi_read_out_initiator_s initiator_struct; + // Responder macro used by fuse_ctrl_prim_axi_read_out_driver and fuse_ctrl_prim_axi_read_out_driver_bfm + // to communicate Responder driven data to fuse_ctrl_prim_axi_read_out_driver_bfm. + `fuse_ctrl_prim_axi_read_out_RESPONDER_STRUCT + fuse_ctrl_prim_axi_read_out_responder_s responder_struct; + + // **************************************************************************** +// pragma uvmf custom reset_condition_and_response begin + // Always block used to return signals to reset value upon assertion of reset + always @( negedge rst_ni_i ) + begin + // RESPONDER mode output signals + arready_o <= 'bz; + rdata_o <= 'bz; + rresp_o <= 'bz; + rid_o <= 'bz; + rlast_o <= 'bz; + rvalid_o <= 'bz; + // INITIATOR mode output signals + // Bi-directional signals + + end +// pragma uvmf custom reset_condition_and_response end + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the driver BFM. It is called by the driver within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the driver BFM needs to be aware of the new configuration + // variables. + // + + function void configure(fuse_ctrl_prim_axi_read_out_configuration_s fuse_ctrl_prim_axi_read_out_configuration_arg); // pragma tbx xtf + initiator_responder = fuse_ctrl_prim_axi_read_out_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + +// pragma uvmf custom initiate_and_get_response begin +// **************************************************************************** +// UVMF_CHANGE_ME +// This task is used by an initator. The task first initiates a transfer then +// waits for the responder to complete the transfer. + task initiate_and_get_response( + // This argument passes transaction variables used by an initiator + // to perform the initial part of a protocol transfer. The values + // come from a sequence item created in a sequence. + input fuse_ctrl_prim_axi_read_out_initiator_s fuse_ctrl_prim_axi_read_out_initiator_struct, + // This argument is used to send data received from the responder + // back to the sequence item. The sequence item is returned to the sequence. + output fuse_ctrl_prim_axi_read_out_responder_s fuse_ctrl_prim_axi_read_out_responder_struct + );// pragma tbx xtf + // + // Members within the fuse_ctrl_prim_axi_read_out_initiator_struct: + // logic prim_arready ; + // logic [DW-1:0] prim_rdata ; + // axi_pkg::axi_burst_e prim_rresp ; + // logic [IW-1:0] prim_rid ; + // logic prim_rlast ; + // logic prim_rvalid ; + // Members within the fuse_ctrl_prim_axi_read_out_responder_struct: + // logic prim_arready ; + // logic [DW-1:0] prim_rdata ; + // axi_pkg::axi_burst_e prim_rresp ; + // logic [IW-1:0] prim_rid ; + // logic prim_rlast ; + // logic prim_rvalid ; + initiator_struct = fuse_ctrl_prim_axi_read_out_initiator_struct; + // + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clk_i_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available initiator input and inout signals listed. + // Initiator input signals + // fuse_ctrl_prim_axi_read_out_responder_struct.xyz = arready_i; // + // fuse_ctrl_prim_axi_read_out_responder_struct.xyz = rdata_i; // [DW-1:0] + // fuse_ctrl_prim_axi_read_out_responder_struct.xyz = rresp_i; // + // fuse_ctrl_prim_axi_read_out_responder_struct.xyz = rid_i; // + // fuse_ctrl_prim_axi_read_out_responder_struct.xyz = rlast_i; // + // fuse_ctrl_prim_axi_read_out_responder_struct.xyz = rvalid_i; // + // Initiator inout signals + // How to assign a signal from an initiator struct member named xyz. + // All available initiator output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Initiator output signals + // Initiator inout signals + // Initiate a transfer using the data received. + @(posedge clk_i_i); + @(posedge clk_i_i); + // Wait for the responder to complete the transfer then place the responder data into + // fuse_ctrl_prim_axi_read_out_responder_struct. + @(posedge clk_i_i); + @(posedge clk_i_i); + responder_struct = fuse_ctrl_prim_axi_read_out_responder_struct; + endtask +// pragma uvmf custom initiate_and_get_response end + +// pragma uvmf custom respond_and_wait_for_next_transfer begin +// **************************************************************************** +// The first_transfer variable is used to prevent completing a transfer in the +// first call to this task. For the first call to this task, there is not +// current transfer to complete. +bit first_transfer=1; + +// UVMF_CHANGE_ME +// This task is used by a responder. The task first completes the current +// transfer in progress then waits for the initiator to start the next transfer. + task respond_and_wait_for_next_transfer( + // This argument is used to send data received from the initiator + // back to the sequence item. The sequence determines how to respond. + output fuse_ctrl_prim_axi_read_out_initiator_s fuse_ctrl_prim_axi_read_out_initiator_struct, + // This argument passes transaction variables used by a responder + // to complete a protocol transfer. The values come from a sequence item. + input fuse_ctrl_prim_axi_read_out_responder_s fuse_ctrl_prim_axi_read_out_responder_struct + );// pragma tbx xtf + // Variables within the fuse_ctrl_prim_axi_read_out_initiator_struct: + // logic prim_arready ; + // logic [DW-1:0] prim_rdata ; + // axi_pkg::axi_burst_e prim_rresp ; + // logic [IW-1:0] prim_rid ; + // logic prim_rlast ; + // logic prim_rvalid ; + // Variables within the fuse_ctrl_prim_axi_read_out_responder_struct: + // logic prim_arready ; + // logic [DW-1:0] prim_rdata ; + // axi_pkg::axi_burst_e prim_rresp ; + // logic [IW-1:0] prim_rid ; + // logic prim_rlast ; + // logic prim_rvalid ; + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clk_i_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available responder input and inout signals listed. + // Responder input signals + // Responder inout signals + // How to assign a signal, named xyz, from an initiator struct member. + // All available responder output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Responder output signals + // arready_o <= fuse_ctrl_prim_axi_read_out_initiator_struct.xyz; // + // rdata_o <= fuse_ctrl_prim_axi_read_out_initiator_struct.xyz; // [DW-1:0] + // rresp_o <= fuse_ctrl_prim_axi_read_out_initiator_struct.xyz; // + // rid_o <= fuse_ctrl_prim_axi_read_out_initiator_struct.xyz; // + // rlast_o <= fuse_ctrl_prim_axi_read_out_initiator_struct.xyz; // + // rvalid_o <= fuse_ctrl_prim_axi_read_out_initiator_struct.xyz; // + // Responder inout signals + + @(posedge clk_i_i); + if (!first_transfer) begin + // Perform transfer response here. + // Reply using data recieved in the fuse_ctrl_prim_axi_read_out_responder_struct. + @(posedge clk_i_i); + // Reply using data recieved in the transaction handle. + @(posedge clk_i_i); + end + // Wait for next transfer then gather info from intiator about the transfer. + // Place the data into the fuse_ctrl_prim_axi_read_out_initiator_struct. + @(posedge clk_i_i); + @(posedge clk_i_i); + first_transfer = 0; + endtask +// pragma uvmf custom respond_and_wait_for_next_transfer end + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_if.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_if.sv new file mode 100644 index 0000000..f08a9f5 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_if.sv @@ -0,0 +1,108 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface contains the fuse_ctrl_prim_axi_read_out interface signals. +// It is instantiated once per fuse_ctrl_prim_axi_read_out bus. Bus Functional Models, +// BFM's named fuse_ctrl_prim_axi_read_out_driver_bfm, are used to drive signals on the bus. +// BFM's named fuse_ctrl_prim_axi_read_out_monitor_bfm are used to monitor signals on the +// bus. This interface signal bundle is passed in the port list of +// the BFM in order to give the BFM access to the signals in this +// interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// This template can be used to connect a DUT to these signals +// +// .dut_signal_port(fuse_ctrl_prim_axi_read_out_bus.arready), // Agent input +// .dut_signal_port(fuse_ctrl_prim_axi_read_out_bus.rdata), // Agent input +// .dut_signal_port(fuse_ctrl_prim_axi_read_out_bus.rresp), // Agent input +// .dut_signal_port(fuse_ctrl_prim_axi_read_out_bus.rid), // Agent input +// .dut_signal_port(fuse_ctrl_prim_axi_read_out_bus.rlast), // Agent input +// .dut_signal_port(fuse_ctrl_prim_axi_read_out_bus.rvalid), // Agent input + +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_prim_axi_read_out_pkg_hdl::*; + +interface fuse_ctrl_prim_axi_read_out_if #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + + ( + input tri clk_i, + input tri rst_ni, + inout tri arready, + inout tri [DW-1:0] rdata, + inout tri rresp, + inout tri rid, + inout tri rlast, + inout tri rvalid + ); + +modport monitor_port + ( + input clk_i, + input rst_ni, + input arready, + input rdata, + input rresp, + input rid, + input rlast, + input rvalid + ); + +modport initiator_port + ( + input clk_i, + input rst_ni, + input arready, + input rdata, + input rresp, + input rid, + input rlast, + input rvalid + ); + +modport responder_port + ( + input clk_i, + input rst_ni, + output arready, + output rdata, + output rresp, + output rid, + output rlast, + output rvalid + ); + + +// pragma uvmf custom interface_item_additional begin +// pragma uvmf custom interface_item_additional end + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_infact_coverage_strategy.csv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_infact_coverage_strategy.csv new file mode 100644 index 0000000..1c218e1 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_infact_coverage_strategy.csv @@ -0,0 +1,6 @@ +Global +auto_bin_max, 64 + +Name,Type,Include +rand_fields,coverpoint,=rand *.** + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_macros.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_macros.svh new file mode 100644 index 0000000..a5d9e29 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_macros.svh @@ -0,0 +1,180 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains macros used with the fuse_ctrl_prim_axi_read_out package. +// These macros include packed struct definitions. These structs are +// used to pass data between classes, hvl, and BFM's, hdl. Use of +// structs are more efficient and simpler to modify. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_struct +// and from_struct methods defined in the macros below that are used in +// the fuse_ctrl_prim_axi_read_out_configuration class. +// + `define fuse_ctrl_prim_axi_read_out_CONFIGURATION_STRUCT \ +typedef struct packed { \ + uvmf_active_passive_t active_passive; \ + uvmf_initiator_responder_t initiator_responder; \ + } fuse_ctrl_prim_axi_read_out_configuration_s; + + `define fuse_ctrl_prim_axi_read_out_CONFIGURATION_TO_STRUCT_FUNCTION \ + virtual function fuse_ctrl_prim_axi_read_out_configuration_s to_struct();\ + fuse_ctrl_prim_axi_read_out_configuration_struct = \ + {\ + this.active_passive,\ + this.initiator_responder\ + };\ + return ( fuse_ctrl_prim_axi_read_out_configuration_struct );\ + endfunction + + `define fuse_ctrl_prim_axi_read_out_CONFIGURATION_FROM_STRUCT_FUNCTION \ + virtual function void from_struct(fuse_ctrl_prim_axi_read_out_configuration_s fuse_ctrl_prim_axi_read_out_configuration_struct);\ + {\ + this.active_passive,\ + this.initiator_responder \ + } = fuse_ctrl_prim_axi_read_out_configuration_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_monitor_struct +// and from_monitor_struct methods of the fuse_ctrl_prim_axi_read_out_transaction class. +// + `define fuse_ctrl_prim_axi_read_out_MONITOR_STRUCT typedef struct packed { \ + logic prim_arready ; \ + logic [DW-1:0] prim_rdata ; \ + axi_pkg::axi_burst_e prim_rresp ; \ + logic [IW-1:0] prim_rid ; \ + logic prim_rlast ; \ + logic prim_rvalid ; \ + } fuse_ctrl_prim_axi_read_out_monitor_s; + + `define fuse_ctrl_prim_axi_read_out_TO_MONITOR_STRUCT_FUNCTION \ + virtual function fuse_ctrl_prim_axi_read_out_monitor_s to_monitor_struct();\ + fuse_ctrl_prim_axi_read_out_monitor_struct = \ + { \ + this.prim_arready , \ + this.prim_rdata , \ + this.prim_rresp , \ + this.prim_rid , \ + this.prim_rlast , \ + this.prim_rvalid \ + };\ + return ( fuse_ctrl_prim_axi_read_out_monitor_struct);\ + endfunction\ + + `define fuse_ctrl_prim_axi_read_out_FROM_MONITOR_STRUCT_FUNCTION \ + virtual function void from_monitor_struct(fuse_ctrl_prim_axi_read_out_monitor_s fuse_ctrl_prim_axi_read_out_monitor_struct);\ + {\ + this.prim_arready , \ + this.prim_rdata , \ + this.prim_rresp , \ + this.prim_rid , \ + this.prim_rlast , \ + this.prim_rvalid \ + } = fuse_ctrl_prim_axi_read_out_monitor_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_initiator_struct +// and from_initiator_struct methods of the fuse_ctrl_prim_axi_read_out_transaction class. +// Also update the comments in the driver BFM. +// + `define fuse_ctrl_prim_axi_read_out_INITIATOR_STRUCT typedef struct packed { \ + logic prim_arready ; \ + logic [DW-1:0] prim_rdata ; \ + axi_pkg::axi_burst_e prim_rresp ; \ + logic [IW-1:0] prim_rid ; \ + logic prim_rlast ; \ + logic prim_rvalid ; \ + } fuse_ctrl_prim_axi_read_out_initiator_s; + + `define fuse_ctrl_prim_axi_read_out_TO_INITIATOR_STRUCT_FUNCTION \ + virtual function fuse_ctrl_prim_axi_read_out_initiator_s to_initiator_struct();\ + fuse_ctrl_prim_axi_read_out_initiator_struct = \ + {\ + this.prim_arready , \ + this.prim_rdata , \ + this.prim_rresp , \ + this.prim_rid , \ + this.prim_rlast , \ + this.prim_rvalid \ + };\ + return ( fuse_ctrl_prim_axi_read_out_initiator_struct);\ + endfunction + + `define fuse_ctrl_prim_axi_read_out_FROM_INITIATOR_STRUCT_FUNCTION \ + virtual function void from_initiator_struct(fuse_ctrl_prim_axi_read_out_initiator_s fuse_ctrl_prim_axi_read_out_initiator_struct);\ + {\ + this.prim_arready , \ + this.prim_rdata , \ + this.prim_rresp , \ + this.prim_rid , \ + this.prim_rlast , \ + this.prim_rvalid \ + } = fuse_ctrl_prim_axi_read_out_initiator_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_responder_struct +// and from_responder_struct methods of the fuse_ctrl_prim_axi_read_out_transaction class. +// Also update the comments in the driver BFM. +// + `define fuse_ctrl_prim_axi_read_out_RESPONDER_STRUCT typedef struct packed { \ + logic prim_arready ; \ + logic [DW-1:0] prim_rdata ; \ + axi_pkg::axi_burst_e prim_rresp ; \ + logic [IW-1:0] prim_rid ; \ + logic prim_rlast ; \ + logic prim_rvalid ; \ + } fuse_ctrl_prim_axi_read_out_responder_s; + + `define fuse_ctrl_prim_axi_read_out_TO_RESPONDER_STRUCT_FUNCTION \ + virtual function fuse_ctrl_prim_axi_read_out_responder_s to_responder_struct();\ + fuse_ctrl_prim_axi_read_out_responder_struct = \ + {\ + this.prim_arready , \ + this.prim_rdata , \ + this.prim_rresp , \ + this.prim_rid , \ + this.prim_rlast , \ + this.prim_rvalid \ + };\ + return ( fuse_ctrl_prim_axi_read_out_responder_struct);\ + endfunction + + `define fuse_ctrl_prim_axi_read_out_FROM_RESPONDER_STRUCT_FUNCTION \ + virtual function void from_responder_struct(fuse_ctrl_prim_axi_read_out_responder_s fuse_ctrl_prim_axi_read_out_responder_struct);\ + {\ + this.prim_arready , \ + this.prim_rdata , \ + this.prim_rresp , \ + this.prim_rid , \ + this.prim_rlast , \ + this.prim_rvalid \ + } = fuse_ctrl_prim_axi_read_out_responder_struct;\ + endfunction +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_monitor.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_monitor.svh new file mode 100644 index 0000000..97b1df2 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_monitor.svh @@ -0,0 +1,126 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class receives fuse_ctrl_prim_axi_read_out transactions observed by the +// fuse_ctrl_prim_axi_read_out monitor BFM and broadcasts them through the analysis port +// on the agent. It accesses the monitor BFM through the monitor +// task. This UVM component captures transactions +// for viewing in the waveform viewer if the +// enable_transaction_viewing flag is set in the configuration. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_read_out_monitor #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvmf_monitor_base #( + .CONFIG_T(fuse_ctrl_prim_axi_read_out_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .BFM_BIND_T(virtual fuse_ctrl_prim_axi_read_out_monitor_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .TRANS_T(fuse_ctrl_prim_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ))); + + `uvm_component_param_utils( fuse_ctrl_prim_axi_read_out_monitor #( + AW, + DW, + IW, + UW + )) + +// Structure used to pass data from monitor BFM to monitor class in agent. +// Use to_monitor_struct function to pack transaction variables into structure. +// Use from_monitor_struct function to unpack transaction variables from structure. +`fuse_ctrl_prim_axi_read_out_MONITOR_STRUCT + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the monitor BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// monitor BFM. This allows the monitor BFM to call the notify_transaction +// function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// *************************************************************************** + virtual task run_phase(uvm_phase phase); + // Start monitor BFM thread and don't call super.run() in order to + // override the default monitor proxy 'pull' behavior with the more + // emulation-friendly BFM 'push' approach using the notify_transaction + // function below + bfm.start_monitoring(); + endtask + +// ************************************************************************** + +// This function is called by the monitor BFM. It receives data observed by the +// monitor BFM. Data is passed using the fuse_ctrl_prim_axi_read_out_monitor_struct. + virtual function void notify_transaction(input fuse_ctrl_prim_axi_read_out_monitor_s fuse_ctrl_prim_axi_read_out_monitor_struct); + + + trans = new("trans"); + trans.from_monitor_struct(fuse_ctrl_prim_axi_read_out_monitor_struct); + trans.start_time = time_stamp; + trans.end_time = $time; + time_stamp = trans.end_time; + + analyze(trans); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_monitor_bfm.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_monitor_bfm.sv new file mode 100644 index 0000000..69f8258 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_monitor_bfm.sv @@ -0,0 +1,218 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface performs the fuse_ctrl_prim_axi_read_out signal monitoring. +// It is accessed by the uvm fuse_ctrl_prim_axi_read_out monitor through a virtual +// interface handle in the fuse_ctrl_prim_axi_read_out configuration. It monitors the +// signals passed in through the port connection named bus of +// type fuse_ctrl_prim_axi_read_out_if. +// +// Input signals from the fuse_ctrl_prim_axi_read_out_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// Interface functions and tasks used by UVM components: +// monitor(inout TRANS_T txn); +// This task receives the transaction, txn, from the +// UVM monitor and then populates variables in txn +// from values observed on bus activity. This task +// blocks until an operation on the fuse_ctrl_prim_axi_read_out bus is complete. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_prim_axi_read_out_pkg_hdl::*; +`include "src/fuse_ctrl_prim_axi_read_out_macros.svh" + + +interface fuse_ctrl_prim_axi_read_out_monitor_bfm #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + ( fuse_ctrl_prim_axi_read_out_if bus ); + // The pragma below and additional ones in-lined further down are for running this BFM on Veloce + // pragma attribute fuse_ctrl_prim_axi_read_out_monitor_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: AW=%x DW=%x IW=%x UW=%x ", AW,DW,IW,UW), + UVM_DEBUG) +end +`endif + + + // Structure used to pass transaction data from monitor BFM to monitor class in agent. +`fuse_ctrl_prim_axi_read_out_MONITOR_STRUCT + fuse_ctrl_prim_axi_read_out_monitor_s fuse_ctrl_prim_axi_read_out_monitor_struct; + + // Structure used to pass configuration data from monitor class to monitor BFM. + `fuse_ctrl_prim_axi_read_out_CONFIGURATION_STRUCT + + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + tri clk_i_i; + tri rst_ni_i; + tri arready_i; + tri [DW-1:0] rdata_i; + tri rresp_i; + tri rid_i; + tri rlast_i; + tri rvalid_i; + assign clk_i_i = bus.clk_i; + assign rst_ni_i = bus.rst_ni; + assign arready_i = bus.arready; + assign rdata_i = bus.rdata; + assign rresp_i = bus.rresp; + assign rid_i = bus.rid; + assign rlast_i = bus.rlast; + assign rvalid_i = bus.rvalid; + + // Proxy handle to UVM monitor + fuse_ctrl_prim_axi_read_out_pkg::fuse_ctrl_prim_axi_read_out_monitor #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) proxy; + // pragma tbx oneway proxy.notify_transaction + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + task wait_for_reset();// pragma tbx xtf + @(posedge clk_i_i) ; + do_wait_for_reset(); + endtask + + // **************************************************************************** + task do_wait_for_reset(); + // pragma uvmf custom reset_condition begin + wait ( rst_ni_i === 1 ) ; + @(posedge clk_i_i) ; + // pragma uvmf custom reset_condition end + endtask + + //****************************************************************** + + task wait_for_num_clocks(input int unsigned count); // pragma tbx xtf + @(posedge clk_i_i); + + repeat (count-1) @(posedge clk_i_i); + endtask + + //****************************************************************** + event go; + function void start_monitoring();// pragma tbx xtf + -> go; + endfunction + + // **************************************************************************** + initial begin + @go; + forever begin + @(posedge clk_i_i); + do_monitor( fuse_ctrl_prim_axi_read_out_monitor_struct ); + + + proxy.notify_transaction( fuse_ctrl_prim_axi_read_out_monitor_struct ); + + end + end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the monitor BFM. It is called by the monitor within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the monitor BFM needs to be aware of the new configuration + // variables. + // + function void configure(fuse_ctrl_prim_axi_read_out_configuration_s fuse_ctrl_prim_axi_read_out_configuration_arg); // pragma tbx xtf + initiator_responder = fuse_ctrl_prim_axi_read_out_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + + + // **************************************************************************** + + task do_monitor(output fuse_ctrl_prim_axi_read_out_monitor_s fuse_ctrl_prim_axi_read_out_monitor_struct); + // + // Available struct members: + // // fuse_ctrl_prim_axi_read_out_monitor_struct.prim_arready + // // fuse_ctrl_prim_axi_read_out_monitor_struct.prim_rdata + // // fuse_ctrl_prim_axi_read_out_monitor_struct.prim_rresp + // // fuse_ctrl_prim_axi_read_out_monitor_struct.prim_rid + // // fuse_ctrl_prim_axi_read_out_monitor_struct.prim_rlast + // // fuse_ctrl_prim_axi_read_out_monitor_struct.prim_rvalid + // // + // Reference code; + // How to wait for signal value + // while (control_signal === 1'b1) @(posedge clk_i_i); + // + // How to assign a struct member, named xyz, from a signal. + // All available input signals listed. + // fuse_ctrl_prim_axi_read_out_monitor_struct.xyz = arready_i; // + // fuse_ctrl_prim_axi_read_out_monitor_struct.xyz = rdata_i; // [DW-1:0] + // fuse_ctrl_prim_axi_read_out_monitor_struct.xyz = rresp_i; // + // fuse_ctrl_prim_axi_read_out_monitor_struct.xyz = rid_i; // + // fuse_ctrl_prim_axi_read_out_monitor_struct.xyz = rlast_i; // + // fuse_ctrl_prim_axi_read_out_monitor_struct.xyz = rvalid_i; // + // pragma uvmf custom do_monitor begin + // UVMF_CHANGE_ME : Implement protocol monitoring. The commented reference code + // below are examples of how to capture signal values and assign them to + // structure members. All available input signals are listed. The 'while' + // code example shows how to wait for a synchronous flow control signal. This + // task should return when a complete transfer has been observed. Once this task is + // exited with captured values, it is then called again to wait for and observe + // the next transfer. One clock cycle is consumed between calls to do_monitor. + @(posedge clk_i_i); + @(posedge clk_i_i); + @(posedge clk_i_i); + @(posedge clk_i_i); + // pragma uvmf custom do_monitor end + endtask + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_random_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_random_sequence.svh new file mode 100644 index 0000000..1aeac4b --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_random_sequence.svh @@ -0,0 +1,87 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This sequences randomizes the fuse_ctrl_prim_axi_read_out transaction and sends it +// to the UVM driver. +// +// This sequence constructs and randomizes a fuse_ctrl_prim_axi_read_out_transaction. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_read_out_random_sequence #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends fuse_ctrl_prim_axi_read_out_sequence_base #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ); + + `uvm_object_param_utils( fuse_ctrl_prim_axi_read_out_random_sequence #( + AW, + DW, + IW, + UW + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //***************************************************************** + function new(string name = ""); + super.new(name); + endfunction: new + + // **************************************************************************** + // TASK : body() + // This task is automatically executed when this sequence is started using the + // start(sequencerHandle) task. + // + task body(); + + // Construct the transaction + req=fuse_ctrl_prim_axi_read_out_transaction#( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )::type_id::create("req"); + start_item(req); + // Randomize the transaction + if(!req.randomize()) `uvm_fatal("SEQ", "fuse_ctrl_prim_axi_read_out_random_sequence::body()-fuse_ctrl_prim_axi_read_out_transaction randomization failed") + // Send the transaction to the fuse_ctrl_prim_axi_read_out_driver_bfm via the sequencer and fuse_ctrl_prim_axi_read_out_driver. + finish_item(req); + `uvm_info("SEQ", {"Response:",req.convert2string()},UVM_MEDIUM) + + endtask + +endclass: fuse_ctrl_prim_axi_read_out_random_sequence + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_responder_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_responder_sequence.svh new file mode 100644 index 0000000..4a4d700 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_responder_sequence.svh @@ -0,0 +1,83 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class can be used to provide stimulus when an interface +// has been configured to run in a responder mode. It +// will never finish by default, always going back to the driver +// and driver BFM for the next transaction with which to respond. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_read_out_responder_sequence #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends fuse_ctrl_prim_axi_read_out_sequence_base #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ); + + `uvm_object_param_utils( fuse_ctrl_prim_axi_read_out_responder_sequence #( + AW, + DW, + IW, + UW + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "fuse_ctrl_prim_axi_read_out_responder_sequence"); + super.new(name); + endfunction + + task body(); + req=fuse_ctrl_prim_axi_read_out_transaction#( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )::type_id::create("req"); + forever begin + start_item(req); + finish_item(req); + // pragma uvmf custom body begin + // UVMF_CHANGE_ME : Do something here with the resulting req item. The + // finish_item() call above will block until the req transaction is ready + // to be handled by the responder sequence. + // If this was an item that required a response, the expectation is + // that the response should be populated within this transaction now. + `uvm_info("SEQ",$sformatf("Processed txn: %s",req.convert2string()),UVM_HIGH) + // pragma uvmf custom body end + end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_sequence_base.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_sequence_base.svh new file mode 100644 index 0000000..9733761 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_sequence_base.svh @@ -0,0 +1,140 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the class used as the base class for all sequences +// for this interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_read_out_sequence_base #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvmf_sequence_base #( + .REQ(fuse_ctrl_prim_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .RSP(fuse_ctrl_prim_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ))); + + `uvm_object_param_utils( fuse_ctrl_prim_axi_read_out_sequence_base #( + AW, + DW, + IW, + UW + )) + + // variables + typedef fuse_ctrl_prim_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) fuse_ctrl_prim_axi_read_out_transaction_req_t; + fuse_ctrl_prim_axi_read_out_transaction_req_t req; + typedef fuse_ctrl_prim_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) fuse_ctrl_prim_axi_read_out_transaction_rsp_t; + fuse_ctrl_prim_axi_read_out_transaction_rsp_t rsp; + + // Event for identifying when a response was received from the sequencer + event new_rsp; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // TASK : get_responses() + // This task recursively gets sequence item responses from the sequencer. + // + virtual task get_responses(); + fork + begin + // Block until new rsp available + get_response(rsp); + // New rsp received. Indicate to sequence using event. + ->new_rsp; + // Display the received response transaction + `uvm_info("SEQ", {"New response transaction:",rsp.convert2string()}, UVM_MEDIUM) + end + join_none + endtask + + // **************************************************************************** + // TASK : pre_body() + // This task is called automatically when start is called with call_pre_post set to 1 (default). + // By calling get_responses() within pre_body() any derived sequences are automatically + // processing response transactions. Only un-comment this call to get_responses() if you + // have configured the interface driver to utilize the response transaction path by setting + // the configuration variable "return_transaction_response" to 1. Otherwise it is possible + // to impact runtime performance and memory utilization. + // + virtual task pre_body(); + // pragma uvmf custom pre_body begin +// get_responses(); + // pragma uvmf custom pre_body end + endtask + + // **************************************************************************** + // TASK : body() + // This task is called automatically when start is called. This sequence sends + // a req sequence item to the sequencer identified as an argument in the call + // to start. + // + virtual task body(); + // pragma uvmf custom body begin + start_item(req); + finish_item(req); + // pragma uvmf custom body end + endtask + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name =""); + super.new( name ); + // pragma uvmf custom new begin + req = fuse_ctrl_prim_axi_read_out_transaction_req_t::type_id::create("req"); + rsp = fuse_ctrl_prim_axi_read_out_transaction_rsp_t::type_id::create("rsp"); + // pragma uvmf custom new end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_transaction.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_transaction.svh new file mode 100644 index 0000000..183b66c --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_transaction.svh @@ -0,0 +1,236 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class defines the variables required for an fuse_ctrl_prim_axi_read_out +// transaction. Class variables to be displayed in waveform transaction +// viewing are added to the transaction viewing stream in the add_to_wave +// function. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_read_out_transaction #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvmf_transaction_base; + + `uvm_object_param_utils( fuse_ctrl_prim_axi_read_out_transaction #( + AW, + DW, + IW, + UW + )) + + logic prim_arready ; + logic [DW-1:0] prim_rdata ; + axi_pkg::axi_burst_e prim_rresp ; + logic [IW-1:0] prim_rid ; + logic prim_rlast ; + logic prim_rvalid ; + + //Constraints for the transaction variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //******************************************************************* + //******************************************************************* + // Macros that define structs and associated functions are + // located in fuse_ctrl_prim_axi_read_out_macros.svh + + //******************************************************************* + // Monitor macro used by fuse_ctrl_prim_axi_read_out_monitor and fuse_ctrl_prim_axi_read_out_monitor_bfm + // This struct is defined in fuse_ctrl_prim_axi_read_out_macros.svh + `fuse_ctrl_prim_axi_read_out_MONITOR_STRUCT + fuse_ctrl_prim_axi_read_out_monitor_s fuse_ctrl_prim_axi_read_out_monitor_struct; + //******************************************************************* + // FUNCTION: to_monitor_struct() + // This function packs transaction variables into a fuse_ctrl_prim_axi_read_out_monitor_s + // structure. The function returns the handle to the fuse_ctrl_prim_axi_read_out_monitor_struct. + // This function is defined in fuse_ctrl_prim_axi_read_out_macros.svh + `fuse_ctrl_prim_axi_read_out_TO_MONITOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_monitor_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_prim_axi_read_out_macros.svh + `fuse_ctrl_prim_axi_read_out_FROM_MONITOR_STRUCT_FUNCTION + + //******************************************************************* + // Initiator macro used by fuse_ctrl_prim_axi_read_out_driver and fuse_ctrl_prim_axi_read_out_driver_bfm + // to communicate initiator driven data to fuse_ctrl_prim_axi_read_out_driver_bfm. + // This struct is defined in fuse_ctrl_prim_axi_read_out_macros.svh + `fuse_ctrl_prim_axi_read_out_INITIATOR_STRUCT + fuse_ctrl_prim_axi_read_out_initiator_s fuse_ctrl_prim_axi_read_out_initiator_struct; + //******************************************************************* + // FUNCTION: to_initiator_struct() + // This function packs transaction variables into a fuse_ctrl_prim_axi_read_out_initiator_s + // structure. The function returns the handle to the fuse_ctrl_prim_axi_read_out_initiator_struct. + // This function is defined in fuse_ctrl_prim_axi_read_out_macros.svh + `fuse_ctrl_prim_axi_read_out_TO_INITIATOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_initiator_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_prim_axi_read_out_macros.svh + `fuse_ctrl_prim_axi_read_out_FROM_INITIATOR_STRUCT_FUNCTION + + //******************************************************************* + // Responder macro used by fuse_ctrl_prim_axi_read_out_driver and fuse_ctrl_prim_axi_read_out_driver_bfm + // to communicate Responder driven data to fuse_ctrl_prim_axi_read_out_driver_bfm. + // This struct is defined in fuse_ctrl_prim_axi_read_out_macros.svh + `fuse_ctrl_prim_axi_read_out_RESPONDER_STRUCT + fuse_ctrl_prim_axi_read_out_responder_s fuse_ctrl_prim_axi_read_out_responder_struct; + //******************************************************************* + // FUNCTION: to_responder_struct() + // This function packs transaction variables into a fuse_ctrl_prim_axi_read_out_responder_s + // structure. The function returns the handle to the fuse_ctrl_prim_axi_read_out_responder_struct. + // This function is defined in fuse_ctrl_prim_axi_read_out_macros.svh + `fuse_ctrl_prim_axi_read_out_TO_RESPONDER_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_responder_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_prim_axi_read_out_macros.svh + `fuse_ctrl_prim_axi_read_out_FROM_RESPONDER_STRUCT_FUNCTION + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + endfunction + + // **************************************************************************** + // FUNCTION: convert2string() + // This function converts all variables in this class to a single string for + // logfile reporting. + // + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + // UVMF_CHANGE_ME : Customize format if desired. + return $sformatf("prim_arready:0x%x prim_rdata:0x%x prim_rresp:0x%x prim_rid:0x%x prim_rlast:0x%x prim_rvalid:0x%x ",prim_arready,prim_rdata,prim_rresp,prim_rid,prim_rlast,prim_rvalid); + // pragma uvmf custom convert2string end + endfunction + + //******************************************************************* + // FUNCTION: do_print() + // This function is automatically called when the .print() function + // is called on this class. + // + virtual function void do_print(uvm_printer printer); + // pragma uvmf custom do_print begin + // UVMF_CHANGE_ME : Current contents of do_print allows for the use of UVM 1.1d, 1.2 or P1800.2. + // Update based on your own printing preference according to your preferred UVM version + $display(convert2string()); + // pragma uvmf custom do_print end + endfunction + + //******************************************************************* + // FUNCTION: do_compare() + // This function is automatically called when the .compare() function + // is called on this class. + // + virtual function bit do_compare (uvm_object rhs, uvm_comparer comparer); + fuse_ctrl_prim_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) RHS; + if (!$cast(RHS,rhs)) return 0; + // pragma uvmf custom do_compare begin + // UVMF_CHANGE_ME : Eliminate comparison of variables not to be used for compare + return (super.do_compare(rhs,comparer) + &&(this.prim_arready == RHS.prim_arready) + &&(this.prim_rdata == RHS.prim_rdata) + &&(this.prim_rresp == RHS.prim_rresp) + &&(this.prim_rid == RHS.prim_rid) + &&(this.prim_rlast == RHS.prim_rlast) + &&(this.prim_rvalid == RHS.prim_rvalid) + ); + // pragma uvmf custom do_compare end + endfunction + + //******************************************************************* + // FUNCTION: do_copy() + // This function is automatically called when the .copy() function + // is called on this class. + // + virtual function void do_copy (uvm_object rhs); + fuse_ctrl_prim_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) RHS; + assert($cast(RHS,rhs)); + // pragma uvmf custom do_copy begin + super.do_copy(rhs); + this.prim_arready = RHS.prim_arready; + this.prim_rdata = RHS.prim_rdata; + this.prim_rresp = RHS.prim_rresp; + this.prim_rid = RHS.prim_rid; + this.prim_rlast = RHS.prim_rlast; + this.prim_rvalid = RHS.prim_rvalid; + // pragma uvmf custom do_copy end + endfunction + + // **************************************************************************** + // FUNCTION: add_to_wave() + // This function is used to display variables in this class in the waveform + // viewer. The start_time and end_time variables must be set before this + // function is called. If the start_time and end_time variables are not set + // the transaction will be hidden at 0ns on the waveform display. + // + virtual function void add_to_wave(int transaction_viewing_stream_h); + `ifdef QUESTA + if (transaction_view_h == 0) begin + transaction_view_h = $begin_transaction(transaction_viewing_stream_h,"fuse_ctrl_prim_axi_read_out_transaction",start_time); + end + super.add_to_wave(transaction_view_h); + // pragma uvmf custom add_to_wave begin + // UVMF_CHANGE_ME : Color can be applied to transaction entries based on content, example below + // case() + // 1 : $add_color(transaction_view_h,"red"); + // default : $add_color(transaction_view_h,"grey"); + // endcase + // UVMF_CHANGE_ME : Eliminate transaction variables not wanted in transaction viewing in the waveform viewer + $add_attribute(transaction_view_h,prim_arready,"prim_arready"); + $add_attribute(transaction_view_h,prim_rdata,"prim_rdata"); + $add_attribute(transaction_view_h,prim_rresp,"prim_rresp"); + $add_attribute(transaction_view_h,prim_rid,"prim_rid"); + $add_attribute(transaction_view_h,prim_rlast,"prim_rlast"); + $add_attribute(transaction_view_h,prim_rvalid,"prim_rvalid"); + // pragma uvmf custom add_to_wave end + $end_transaction(transaction_view_h,end_time); + $free_transaction(transaction_view_h); + `endif // QUESTA + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_transaction_coverage.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_transaction_coverage.svh new file mode 100644 index 0000000..199ee53 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_transaction_coverage.svh @@ -0,0 +1,104 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class records fuse_ctrl_prim_axi_read_out transaction information using +// a covergroup named fuse_ctrl_prim_axi_read_out_transaction_cg. An instance of this +// coverage component is instantiated in the uvmf_parameterized_agent +// if the has_coverage flag is set. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_read_out_transaction_coverage #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvm_subscriber #(.T(fuse_ctrl_prim_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ))); + + `uvm_component_param_utils( fuse_ctrl_prim_axi_read_out_transaction_coverage #( + AW, + DW, + IW, + UW + )) + + T coverage_trans; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + covergroup fuse_ctrl_prim_axi_read_out_transaction_cg; + // pragma uvmf custom covergroup begin + // UVMF_CHANGE_ME : Add coverage bins, crosses, exclusions, etc. according to coverage needs. + option.auto_bin_max=1024; + option.per_instance=1; + prim_arready: coverpoint coverage_trans.prim_arready; + prim_rdata: coverpoint coverage_trans.prim_rdata; + prim_rresp: coverpoint coverage_trans.prim_rresp; + prim_rid: coverpoint coverage_trans.prim_rid; + prim_rlast: coverpoint coverage_trans.prim_rlast; + prim_rvalid: coverpoint coverage_trans.prim_rvalid; + // pragma uvmf custom covergroup end + endgroup + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new(string name="", uvm_component parent=null); + super.new(name,parent); + fuse_ctrl_prim_axi_read_out_transaction_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that transaction variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + endfunction + + // **************************************************************************** + // FUNCTION : build_phase() + // This function is the standard UVM build_phase. + // + function void build_phase(uvm_phase phase); + fuse_ctrl_prim_axi_read_out_transaction_cg.set_inst_name($sformatf("fuse_ctrl_prim_axi_read_out_transaction_cg_%s",get_full_name())); + endfunction + + // **************************************************************************** + // FUNCTION: write (T t) + // This function is automatically executed when a transaction arrives on the + // analysis_export. It copies values from the variables in the transaction + // to local variables used to collect functional coverage. + // + virtual function void write (T t); + `uvm_info("COV","Received transaction",UVM_HIGH); + coverage_trans = t; + fuse_ctrl_prim_axi_read_out_transaction_cg.sample(); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_typedefs.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_typedefs.svh new file mode 100644 index 0000000..f2a7bdb --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_typedefs.svh @@ -0,0 +1,34 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the host server when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_typedefs_hdl.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_typedefs_hdl.svh new file mode 100644 index 0000000..0d58518 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_typedefs_hdl.svh @@ -0,0 +1,35 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the emulator when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/yaml/fuse_ctrl_prim_axi_read_out_interface.yaml b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/yaml/fuse_ctrl_prim_axi_read_out_interface.yaml new file mode 100644 index 0000000..518e6a1 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/yaml/fuse_ctrl_prim_axi_read_out_interface.yaml @@ -0,0 +1,91 @@ +uvmf: + interfaces: + fuse_ctrl_prim_axi_read_out: + clock: clk_i + config_constraints: [] + config_vars: [] + existing_library_component: 'True' + gen_inbound_streaming_driver: 'False' + hdl_pkg_parameters: [] + hdl_typedefs: [] + hvl_pkg_parameters: [] + hvl_typedefs: [] + parameters: + - name: AW + type: int + value: '32' + - name: DW + type: int + value: '32' + - name: IW + type: int + value: '3' + - name: UW + type: int + value: '32' + ports: + - dir: input + name: arready + reset_value: '''bz' + width: '1' + - dir: input + name: rdata + reset_value: '''bz' + width: DW + - dir: input + name: rresp + reset_value: '''bz' + width: '1' + - dir: input + name: rid + reset_value: '''bz' + width: '1' + - dir: input + name: rlast + reset_value: '''bz' + width: '1' + - dir: input + name: rvalid + reset_value: '''bz' + width: '1' + reset: rst_ni + reset_assertion_level: 'False' + transaction_constraints: [] + transaction_vars: + - comment: '' + iscompare: 'True' + isrand: 'False' + name: prim_arready + type: logic + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'False' + name: prim_rdata + type: logic [DW-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'False' + name: prim_rresp + type: axi_pkg::axi_burst_e + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'False' + name: prim_rid + type: logic [IW-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'False' + name: prim_rlast + type: logic + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'False' + name: prim_rvalid + type: logic + unpacked_dimension: '' + use_dpi_link: 'False' diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/.project b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/.project new file mode 100644 index 0000000..8c615b5 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/.project @@ -0,0 +1,30 @@ + + + fuse_ctrl_prim_axi_write_in_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/.svproject b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/.svproject new file mode 100644 index 0000000..14eb90e --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/Makefile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/Makefile new file mode 100644 index 0000000..58b6255 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/Makefile @@ -0,0 +1,66 @@ +# fuse_ctrl_prim_axi_write_in interface packages source +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +fuse_ctrl_prim_axi_write_in_PKG = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_write_in_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_filelist_hvl.f + +fuse_ctrl_prim_axi_write_in_PKG_HDL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_write_in_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_filelist_hdl.f + +fuse_ctrl_prim_axi_write_in_PKG_XRTL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_write_in_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_filelist_xrtl.f + +COMP_fuse_ctrl_prim_axi_write_in_PKG_TGT_0 = q_comp_fuse_ctrl_prim_axi_write_in_pkg +COMP_fuse_ctrl_prim_axi_write_in_PKG_TGT_1 = v_comp_fuse_ctrl_prim_axi_write_in_pkg +COMP_fuse_ctrl_prim_axi_write_in_PKG_TGT = $(COMP_fuse_ctrl_prim_axi_write_in_PKG_TGT_$(USE_VELOCE)) + +comp_fuse_ctrl_prim_axi_write_in_pkg: $(COMP_fuse_ctrl_prim_axi_write_in_PKG_TGT) + +q_comp_fuse_ctrl_prim_axi_write_in_pkg: + $(HDL_COMP_CMD) $(fuse_ctrl_prim_axi_write_in_PKG_HDL) + $(HVL_COMP_CMD) $(fuse_ctrl_prim_axi_write_in_PKG) + $(HDL_COMP_CMD) $(fuse_ctrl_prim_axi_write_in_PKG_XRTL) + +v_comp_fuse_ctrl_prim_axi_write_in_pkg: + $(HVL_COMP_CMD) $(fuse_ctrl_prim_axi_write_in_PKG_HDL) + $(HVL_COMP_CMD) $(fuse_ctrl_prim_axi_write_in_PKG) + $(VELANALYZE_CMD) $(fuse_ctrl_prim_axi_write_in_PKG_HDL) + $(VELANALYZE_HVL_CMD) $(fuse_ctrl_prim_axi_write_in_PKG) + $(HDL_COMP_CMD) $(fuse_ctrl_prim_axi_write_in_PKG_XRTL) + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export fuse_ctrl_prim_axi_write_in_IF_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/dpi + +C_FILE_COMPILE_LIST_fuse_ctrl_prim_axi_write_in_pkg = \ + +O_FILE_COMPILE_LIST_fuse_ctrl_prim_axi_write_in_pkg = $(notdir $(C_FILE_COMPILE_LIST_fuse_ctrl_prim_axi_write_in_pkg:.c=.o)) + +GCC_COMP_ARGS_fuse_ctrl_prim_axi_write_in_pkg += -I$(fuse_ctrl_prim_axi_write_in_IF_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_fuse_ctrl_prim_axi_write_in_pkg += $(fuse_ctrl_prim_axi_write_in_IF_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_fuse_ctrl_prim_axi_write_in_pkg += \ + \ + -o .so + +comp_fuse_ctrl_prim_axi_write_in_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Interface C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_fuse_ctrl_prim_axi_write_in_pkg) $(C_FILE_COMPILE_LIST_fuse_ctrl_prim_axi_write_in_pkg) + @echo "--------------------------------" + @echo "Linking Interface C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_fuse_ctrl_prim_axi_write_in_pkg) $(O_FILE_COMPILE_LIST_fuse_ctrl_prim_axi_write_in_pkg) + @echo "--------------------------------" + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/compile.do b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/compile.do new file mode 100644 index 0000000..0b7eaf6 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/compile.do @@ -0,0 +1,14 @@ +# Tcl do file for compile of fuse_ctrl_prim_axi_write_in interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_write_in_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_filelist_hdl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_write_in_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_filelist_hvl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_write_in_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_filelist_xrtl.f \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in.compile new file mode 100644 index 0000000..cc55184 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in.compile @@ -0,0 +1,3 @@ +needs: + - fuse_ctrl_prim_axi_write_in_hvl.compile + - fuse_ctrl_prim_axi_write_in_hdl.compile diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_bfm.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_bfm.vinfo new file mode 100644 index 0000000..f0da591 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_bfm.vinfo @@ -0,0 +1,6 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use fuse_ctrl_prim_axi_write_in_pkg_hdl.vinfo ++incdir+@vinfodir +src/fuse_ctrl_prim_axi_write_in_if.sv +src/fuse_ctrl_prim_axi_write_in_driver_bfm.sv +src/fuse_ctrl_prim_axi_write_in_monitor_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_common.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_common.compile new file mode 100644 index 0000000..9fd1f6c --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_common.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +incdir: + - . + - ${uvm_path}/src +src: + - fuse_ctrl_prim_axi_write_in_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_filelist_hdl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_filelist_hdl.f new file mode 100644 index 0000000..05ff744 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_filelist_hdl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_filelist_hvl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_filelist_hvl.f new file mode 100644 index 0000000..9e594a7 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_filelist_hvl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_pkg.sv \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_filelist_xrtl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_filelist_xrtl.f new file mode 100644 index 0000000..aeb9836 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_filelist_xrtl.f @@ -0,0 +1,3 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_if.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_monitor_bfm.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_driver_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_hdl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_hdl.compile new file mode 100644 index 0000000..954117b --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_hdl.compile @@ -0,0 +1,9 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ./fuse_ctrl_prim_axi_write_in_common.compile +incdir: + - . +src: + - src/fuse_ctrl_prim_axi_write_in_if.sv + - src/fuse_ctrl_prim_axi_write_in_monitor_bfm.sv + - src/fuse_ctrl_prim_axi_write_in_driver_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_hvl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_hvl.compile new file mode 100644 index 0000000..7be9859 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_hvl.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ./fuse_ctrl_prim_axi_write_in_common.compile +incdir: + - . +src: + - fuse_ctrl_prim_axi_write_in_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_pkg.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_pkg.sv new file mode 100644 index 0000000..bebb7a3 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_pkg.sv @@ -0,0 +1,91 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - + +// - +// - +// - + +// - +// - +// - + +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_prim_axi_write_in_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg_hdl::*; + import uvmf_base_pkg::*; + import fuse_ctrl_prim_axi_write_in_pkg_hdl::*; + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + `include "src/fuse_ctrl_prim_axi_write_in_macros.svh" + + export fuse_ctrl_prim_axi_write_in_pkg_hdl::*; + + + + // Parameters defined as HVL parameters + + `include "src/fuse_ctrl_prim_axi_write_in_typedefs.svh" + `include "src/fuse_ctrl_prim_axi_write_in_transaction.svh" + + `include "src/fuse_ctrl_prim_axi_write_in_configuration.svh" + `include "src/fuse_ctrl_prim_axi_write_in_driver.svh" + `include "src/fuse_ctrl_prim_axi_write_in_monitor.svh" + + `include "src/fuse_ctrl_prim_axi_write_in_transaction_coverage.svh" + `include "src/fuse_ctrl_prim_axi_write_in_sequence_base.svh" + `include "src/fuse_ctrl_prim_axi_write_in_random_sequence.svh" + + `include "src/fuse_ctrl_prim_axi_write_in_responder_sequence.svh" + `include "src/fuse_ctrl_prim_axi_write_in2reg_adapter.svh" + + `include "src/fuse_ctrl_prim_axi_write_in_agent.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new interface sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the interface package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_pkg.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_pkg.vinfo new file mode 100644 index 0000000..a03a77b --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_pkg.vinfo @@ -0,0 +1,4 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use fuse_ctrl_prim_axi_write_in_pkg_hdl.vinfo ++incdir+@vinfodir +fuse_ctrl_prim_axi_write_in_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_pkg_hdl.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_pkg_hdl.sv new file mode 100644 index 0000000..b974d8d --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_pkg_hdl.sv @@ -0,0 +1,52 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that needs to be compiled and synthesized +// for running on Veloce. +// +// CONTAINS: +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_prim_axi_write_in_pkg_hdl; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HDL parameters + + `include "src/fuse_ctrl_prim_axi_write_in_typedefs_hdl.svh" + `include "src/fuse_ctrl_prim_axi_write_in_macros.svh" + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_pkg_hdl.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_pkg_hdl.vinfo new file mode 100644 index 0000000..6813b25 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_pkg_hdl.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +fuse_ctrl_prim_axi_write_in_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_pkg_sve.F b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_pkg_sve.F new file mode 100644 index 0000000..2762780 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_pkg_sve.F @@ -0,0 +1,10 @@ +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + ++incdir+. +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_filelist_hdl.f +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_filelist_hvl.f diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in2reg_adapter.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in2reg_adapter.svh new file mode 100644 index 0000000..5affa0a --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in2reg_adapter.svh @@ -0,0 +1,137 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the UVM register adapter for the fuse_ctrl_prim_axi_write_in interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_write_in2reg_adapter #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvm_reg_adapter; + + `uvm_object_param_utils( fuse_ctrl_prim_axi_write_in2reg_adapter #( + AW, + DW, + IW, + UW + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //-------------------------------------------------------------------- + // new + //-------------------------------------------------------------------- + function new (string name = "fuse_ctrl_prim_axi_write_in2reg_adapter" ); + super.new(name); + // pragma uvmf custom new begin + // UVMF_CHANGE_ME : Configure the adapter regarding byte enables and provides response. + + // Does the protocol the Agent is modeling support byte enables? + // 0 = NO + // 1 = YES + supports_byte_enable = 0; + + // Does the Agent's Driver provide separate response sequence items? + // i.e. Does the driver call seq_item_port.put() + // and do the sequences call get_response()? + // 0 = NO + // 1 = YES + provides_responses = 0; + // pragma uvmf custom new end + + endfunction: new + + //-------------------------------------------------------------------- + // reg2bus + //-------------------------------------------------------------------- + virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw); + + fuse_ctrl_prim_axi_write_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) trans_h = fuse_ctrl_prim_axi_write_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )::type_id::create("trans_h"); + + // pragma uvmf custom reg2bus begin + // UVMF_CHANGE_ME : Fill in the reg2bus adapter mapping registe fields to protocol fields. + + //Adapt the following for your sequence item type + // trans_h.op = (rw.kind == UVM_READ) ? WB_READ : WB_WRITE; + //Copy over address + // trans_h.addr = rw.addr; + //Copy over write data + // trans_h.data = rw.data; + + // pragma uvmf custom reg2bus end + + // Return the adapted transaction + return trans_h; + + endfunction: reg2bus + + //-------------------------------------------------------------------- + // bus2reg + //-------------------------------------------------------------------- + virtual function void bus2reg(uvm_sequence_item bus_item, + ref uvm_reg_bus_op rw); + fuse_ctrl_prim_axi_write_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) trans_h; + if (!$cast(trans_h, bus_item)) begin + `uvm_fatal("ADAPT","Provided bus_item is not of the correct type") + return; + end + // pragma uvmf custom bus2reg begin + // UVMF_CHANGE_ME : Fill in the bus2reg adapter mapping protocol fields to register fields. + //Adapt the following for your sequence item type + //Copy over instruction type + // rw.kind = (trans_h.op == WB_WRITE) ? UVM_WRITE : UVM_READ; + //Copy over address + // rw.addr = trans_h.addr; + //Copy over read data + // rw.data = trans_h.data; + //Check for errors on the bus and return UVM_NOT_OK if there is an error + // rw.status = UVM_IS_OK; + // pragma uvmf custom bus2reg end + + endfunction: bus2reg + +endclass : fuse_ctrl_prim_axi_write_in2reg_adapter + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_agent.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_agent.svh new file mode 100644 index 0000000..6e27bc5 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_agent.svh @@ -0,0 +1,102 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: Protocol specific agent class definition +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_write_in_agent #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvmf_parameterized_agent #( + .CONFIG_T(fuse_ctrl_prim_axi_write_in_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .DRIVER_T(fuse_ctrl_prim_axi_write_in_driver #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .MONITOR_T(fuse_ctrl_prim_axi_write_in_monitor #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .COVERAGE_T(fuse_ctrl_prim_axi_write_in_transaction_coverage #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .TRANS_T(fuse_ctrl_prim_axi_write_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )) + ); + + `uvm_component_param_utils( fuse_ctrl_prim_axi_write_in_agent #( + AW, + DW, + IW, + UW + )) + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** + // FUNCTION: build_phase + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + if (configuration.active_passive == ACTIVE) begin + // Place sequencer handle into configuration object + // so that it may be retrieved from configuration + // rather than using uvm_config_db + configuration.sequencer = this.sequencer; + end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_configuration.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_configuration.svh new file mode 100644 index 0000000..98f1bbd --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_configuration.svh @@ -0,0 +1,233 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class contains all variables and functions used +// to configure the fuse_ctrl_prim_axi_write_in agent and its bfm's. It gets the +// bfm's from the uvm_config_db for use by the agent. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_write_in_configuration #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvmf_parameterized_agent_configuration_base #( + .DRIVER_BFM_BIND_T(virtual fuse_ctrl_prim_axi_write_in_driver_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .MONITOR_BFM_BIND_T( virtual fuse_ctrl_prim_axi_write_in_monitor_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ))); + + `uvm_object_param_utils( fuse_ctrl_prim_axi_write_in_configuration #( + AW, + DW, + IW, + UW + )) + + + // Sequencer handle populated by agent + uvm_sequencer #(fuse_ctrl_prim_axi_write_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) ) sequencer; + + //Constraints for the configuration variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + covergroup fuse_ctrl_prim_axi_write_in_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + // pragma uvmf custom covergroup end + endgroup + + //******************************************************************* + //******************************************************************* + // Structure used to pass configuration variables to monitor and driver BFM's. + // Use to_struct function to pack variables into structure. + // Use from_struct function to unpack variables from structure. + // This structure is defined in fuse_ctrl_prim_axi_write_in_macros.svh + `fuse_ctrl_prim_axi_write_in_CONFIGURATION_STRUCT + fuse_ctrl_prim_axi_write_in_configuration_s fuse_ctrl_prim_axi_write_in_configuration_struct; + //******************************************************************* + // FUNCTION: to_struct() + // This function packs variables into a fuse_ctrl_prim_axi_write_in_configuration_s + // structure. The function returns the handle to the fuse_ctrl_prim_axi_write_in_configuration_struct. + // This function is defined in fuse_ctrl_prim_axi_write_in_macros.svh + `fuse_ctrl_prim_axi_write_in_CONFIGURATION_TO_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_struct() + // This function unpacks the struct provided as an argument into + // variables of this class. + // This function is defined in fuse_ctrl_prim_axi_write_in_macros.svh + `fuse_ctrl_prim_axi_write_in_CONFIGURATION_FROM_STRUCT_FUNCTION + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + // Construct the covergroup for this configuration class + fuse_ctrl_prim_axi_write_in_configuration_cg = new; + endfunction + + // **************************************************************************** + // FUNCTION: post_randomize() + // This function is automatically called after the randomize() function + // is executed. + // + function void post_randomize(); + super.post_randomize(); + fuse_ctrl_prim_axi_write_in_configuration_cg.sample(); + endfunction + + // **************************************************************************** + // FUNCTION: initialize + // This function causes the configuration to retrieve + // its virtual interface handle from the uvm_config_db. + // This function also makes itself available to its + // agent through the uvm_config_db. + // + // ARGUMENTS: + // uvmf_active_passive_t activity: + // This argument identifies the simulation level + // as either BLOCK, CHIP, SIMULATION, etc. + // + // AGENT_PATH: + // This argument identifies the path to this + // configurations agent. This configuration + // makes itself available to the agent specified + // by agent_path by placing itself into the + // uvm_config_db. + // + // INTERFACE_NAME: + // This argument identifies the string name of + // this configurations BFM's. This string + // name is used to retrieve the driver and + // monitor BFM from the uvm_config_db. + // + virtual function void initialize(uvmf_active_passive_t activity, + string agent_path, + string interface_name); + + super.initialize( activity, agent_path, interface_name); + // The covergroup is given the same name as the interface + fuse_ctrl_prim_axi_write_in_configuration_cg.set_inst_name(interface_name); + + // This configuration places itself into the uvm_config_db for the agent, identified by the agent_path variable, to retrieve. + uvm_config_db #( fuse_ctrl_prim_axi_write_in_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + )::set( null ,agent_path,UVMF_AGENT_CONFIG, this ); + + // This configuration also places itself in the config db using the same identifier used by the interface. This allows users to access + // configuration variables and the interface through the bfm api class rather than directly accessing the BFM. This is useful for + // accessingthe BFM when using Veloce + uvm_config_db #( fuse_ctrl_prim_axi_write_in_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + )::set( null ,UVMF_CONFIGURATIONS, interface_name, this ); + + fuse_ctrl_prim_axi_write_in_configuration_cg.set_inst_name($sformatf("fuse_ctrl_prim_axi_write_in_configuration_cg_%s",get_full_name())); + +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. + `uvm_info("CFG", + $psprintf("The agent at '%s' is using interface named %s has the following parameters: AW=%x DW=%x IW=%x UW=%x ", agent_path, interface_name, AW ,DW ,IW ,UW ), + UVM_DEBUG) + + // pragma uvmf custom initialize begin + // This controls whether or not the agent returns a transaction handle in the driver when calling + // item_done() back into the sequencer or not. If set to 1, a transaction is sent back which means + // the sequence on the other end must use the get_response() part of the driver/sequence API. If + // this doesn't occur, there will eventually be response_queue overflow errors during the test. + return_transaction_response = 1'b0; + + // pragma uvmf custom initialize end + + endfunction + + // **************************************************************************** + // TASK: wait_for_reset + // *[Required]* Blocks until reset is released. The wait_for_reset operation is performed + // by a task in the monitor bfm. + virtual task wait_for_reset(); + monitor_bfm.wait_for_reset(); + endtask + + // **************************************************************************** + // TASK: wait_for_num_clocks + // *[Required]* Blocks until specified number of clocks have elapsed. The wait_for_num_clocks + // operation is performed by a task in the monitor bfm. + virtual task wait_for_num_clocks(int clocks); + monitor_bfm.wait_for_num_clocks(clocks); + endtask + + // **************************************************************************** + // FUNCTION : convert2string() + // This function is used to convert variables in this class into a string for log messaging. + // + virtual function string convert2string (); + // pragma uvmf custom convert2string begin + return $sformatf(""); + // pragma uvmf custom convert2string end + endfunction + + // **************************************************************************** + // FUNCTION: get_sequencer + function uvm_sequencer #(fuse_ctrl_prim_axi_write_in_transaction#( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )) get_sequencer(); + return sequencer; + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_driver.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_driver.svh new file mode 100644 index 0000000..6294cf5 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_driver.svh @@ -0,0 +1,135 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class passes transactions between the sequencer +// and the BFM driver interface. It accesses the driver BFM +// through the bfm handle. This driver +// passes transactions to the driver BFM through the access +// task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_write_in_driver #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvmf_driver_base #( + .CONFIG_T(fuse_ctrl_prim_axi_write_in_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) ), + .BFM_BIND_T(virtual fuse_ctrl_prim_axi_write_in_driver_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) ), + .REQ(fuse_ctrl_prim_axi_write_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) ), + .RSP(fuse_ctrl_prim_axi_write_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) )); + + `uvm_component_param_utils( fuse_ctrl_prim_axi_write_in_driver #( + AW, + DW, + IW, + UW + )) +//******************************************************************* +// Macros that define structs located in fuse_ctrl_prim_axi_write_in_macros.svh +//******************************************************************* +// Initiator macro used by fuse_ctrl_prim_axi_write_in_driver and fuse_ctrl_prim_axi_write_in_driver_bfm +// to communicate initiator driven data to fuse_ctrl_prim_axi_write_in_driver_bfm. +`fuse_ctrl_prim_axi_write_in_INITIATOR_STRUCT + fuse_ctrl_prim_axi_write_in_initiator_s fuse_ctrl_prim_axi_write_in_initiator_struct; +//******************************************************************* +// Responder macro used by fuse_ctrl_prim_axi_write_in_driver and fuse_ctrl_prim_axi_write_in_driver_bfm +// to communicate Responder driven data to fuse_ctrl_prim_axi_write_in_driver_bfm. +`fuse_ctrl_prim_axi_write_in_RESPONDER_STRUCT + fuse_ctrl_prim_axi_write_in_responder_s fuse_ctrl_prim_axi_write_in_responder_struct; + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent=null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the driver BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// driver BFM. This allows the driver BFM to call tasks and function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// **************************************************************************** +// This task is called by the run_phase in uvmf_driver_base. + virtual task access( inout REQ txn ); +// pragma uvmf custom access begin + if (configuration.initiator_responder==RESPONDER) begin + // Complete current transfer and wait for next transfer + bfm.respond_and_wait_for_next_transfer( + fuse_ctrl_prim_axi_write_in_initiator_struct, + txn.to_responder_struct() + ); + // Unpack information about initiated transfer received by this responder + txn.from_initiator_struct(fuse_ctrl_prim_axi_write_in_initiator_struct); + end else begin + // Initiate a transfer and get response + bfm.initiate_and_get_response( + txn.to_initiator_struct(), + fuse_ctrl_prim_axi_write_in_responder_struct + ); + // Unpack transfer response information received by this initiator + txn.from_responder_struct(fuse_ctrl_prim_axi_write_in_responder_struct); + end +// pragma uvmf custom access end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_driver_bfm.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_driver_bfm.sv new file mode 100644 index 0000000..1f54377 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_driver_bfm.sv @@ -0,0 +1,427 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This interface performs the fuse_ctrl_prim_axi_write_in signal driving. It is +// accessed by the uvm fuse_ctrl_prim_axi_write_in driver through a virtual interface +// handle in the fuse_ctrl_prim_axi_write_in configuration. It drives the singals passed +// in through the port connection named bus of type fuse_ctrl_prim_axi_write_in_if. +// +// Input signals from the fuse_ctrl_prim_axi_write_in_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// This bfm drives signals with a _o suffix. These signals +// are driven onto signals within fuse_ctrl_prim_axi_write_in_if based on INITIATOR/RESPONDER and/or +// ARBITRATION/GRANT status. +// +// The output signal connections are as follows: +// signal_o -> bus.signal +// +// +// Interface functions and tasks used by UVM components: +// +// configure: +// This function gets configuration attributes from the +// UVM driver to set any required BFM configuration +// variables such as 'initiator_responder'. +// +// initiate_and_get_response: +// This task is used to perform signaling activity for initiating +// a protocol transfer. The task initiates the transfer, using +// input data from the initiator struct. Then the task captures +// response data, placing the data into the response struct. +// The response struct is returned to the driver class. +// +// respond_and_wait_for_next_transfer: +// This task is used to complete a current transfer as a responder +// and then wait for the initiator to start the next transfer. +// The task uses data in the responder struct to drive protocol +// signals to complete the transfer. The task then waits for +// the next transfer. Once the next transfer begins, data from +// the initiator is placed into the initiator struct and sent +// to the responder sequence for processing to determine +// what data to respond with. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_prim_axi_write_in_pkg_hdl::*; +`include "src/fuse_ctrl_prim_axi_write_in_macros.svh" + +interface fuse_ctrl_prim_axi_write_in_driver_bfm #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + (fuse_ctrl_prim_axi_write_in_if bus); + // The following pragma and additional ones in-lined further below are for running this BFM on Veloce + // pragma attribute fuse_ctrl_prim_axi_write_in_driver_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: AW=%x DW=%x IW=%x UW=%x ", AW,DW,IW,UW), + UVM_DEBUG) +end +`endif + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + tri clk_i_i; + tri rst_ni_i; + + // Signal list (all signals are capable of being inputs and outputs for the sake + // of supporting both INITIATOR and RESPONDER mode operation. Expectation is that + // directionality in the config file was from the point-of-view of the INITIATOR + + // INITIATOR mode input signals + + // INITIATOR mode output signals + tri [AW-1:0] awaddr_i; + reg [AW-1:0] awaddr_o = 'bz; + tri [$bits(axi_pkg::axi_burst_e)-1:0] awburst_i; + reg [$bits(axi_pkg::axi_burst_e)-1:0] awburst_o = 'bz; + tri [2:0] awsize_i; + reg [2:0] awsize_o = 'bz; + tri [7:0] awlen_i; + reg [7:0] awlen_o = 'bz; + tri [UW-1:0] awuser_i; + reg [UW-1:0] awuser_o = 'bz; + tri [UW-1:0] awid_i; + reg [UW-1:0] awid_o = 'bz; + tri awlock_i; + reg awlock_o = 'bz; + tri awvalid_i; + reg awvalid_o = 'bz; + tri [DW-1:0] wdata_i; + reg [DW-1:0] wdata_o = 'bz; + tri [DW/8-1:0] wstrb_i; + reg [DW/8-1:0] wstrb_o = 'bz; + tri wvalid_i; + reg wvalid_o = 'bz; + tri wlast_i; + reg wlast_o = 'bz; + tri bready_i; + reg bready_o = 'bz; + + // Bi-directional signals + + + assign clk_i_i = bus.clk_i; + assign rst_ni_i = bus.rst_ni; + + // These are signals marked as 'input' by the config file, but the signals will be + // driven by this BFM if put into RESPONDER mode (flipping all signal directions around) + + + // These are signals marked as 'output' by the config file, but the outputs will + // not be driven by this BFM unless placed in INITIATOR mode. + assign bus.awaddr = (initiator_responder == INITIATOR) ? awaddr_o : 'bz; + assign awaddr_i = bus.awaddr; + assign bus.awburst = (initiator_responder == INITIATOR) ? awburst_o : 'bz; + assign awburst_i = bus.awburst; + assign bus.awsize = (initiator_responder == INITIATOR) ? awsize_o : 'bz; + assign awsize_i = bus.awsize; + assign bus.awlen = (initiator_responder == INITIATOR) ? awlen_o : 'bz; + assign awlen_i = bus.awlen; + assign bus.awuser = (initiator_responder == INITIATOR) ? awuser_o : 'bz; + assign awuser_i = bus.awuser; + assign bus.awid = (initiator_responder == INITIATOR) ? awid_o : 'bz; + assign awid_i = bus.awid; + assign bus.awlock = (initiator_responder == INITIATOR) ? awlock_o : 'bz; + assign awlock_i = bus.awlock; + assign bus.awvalid = (initiator_responder == INITIATOR) ? awvalid_o : 'bz; + assign awvalid_i = bus.awvalid; + assign bus.wdata = (initiator_responder == INITIATOR) ? wdata_o : 'bz; + assign wdata_i = bus.wdata; + assign bus.wstrb = (initiator_responder == INITIATOR) ? wstrb_o : 'bz; + assign wstrb_i = bus.wstrb; + assign bus.wvalid = (initiator_responder == INITIATOR) ? wvalid_o : 'bz; + assign wvalid_i = bus.wvalid; + assign bus.wlast = (initiator_responder == INITIATOR) ? wlast_o : 'bz; + assign wlast_i = bus.wlast; + assign bus.bready = (initiator_responder == INITIATOR) ? bready_o : 'bz; + assign bready_i = bus.bready; + + // Proxy handle to UVM driver + fuse_ctrl_prim_axi_write_in_pkg::fuse_ctrl_prim_axi_write_in_driver #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) proxy; + // pragma tbx oneway proxy.my_function_name_in_uvm_driver + + // **************************************************************************** + // **************************************************************************** + // Macros that define structs located in fuse_ctrl_prim_axi_write_in_macros.svh + // **************************************************************************** + // Struct for passing configuration data from fuse_ctrl_prim_axi_write_in_driver to this BFM + // **************************************************************************** + `fuse_ctrl_prim_axi_write_in_CONFIGURATION_STRUCT + // **************************************************************************** + // Structs for INITIATOR and RESPONDER data flow + //******************************************************************* + // Initiator macro used by fuse_ctrl_prim_axi_write_in_driver and fuse_ctrl_prim_axi_write_in_driver_bfm + // to communicate initiator driven data to fuse_ctrl_prim_axi_write_in_driver_bfm. + `fuse_ctrl_prim_axi_write_in_INITIATOR_STRUCT + fuse_ctrl_prim_axi_write_in_initiator_s initiator_struct; + // Responder macro used by fuse_ctrl_prim_axi_write_in_driver and fuse_ctrl_prim_axi_write_in_driver_bfm + // to communicate Responder driven data to fuse_ctrl_prim_axi_write_in_driver_bfm. + `fuse_ctrl_prim_axi_write_in_RESPONDER_STRUCT + fuse_ctrl_prim_axi_write_in_responder_s responder_struct; + + // **************************************************************************** +// pragma uvmf custom reset_condition_and_response begin + // Always block used to return signals to reset value upon assertion of reset + always @( negedge rst_ni_i ) + begin + // RESPONDER mode output signals + // INITIATOR mode output signals + awaddr_o <= 'bz; + awburst_o <= 'bz; + awsize_o <= 'bz; + awlen_o <= 'bz; + awuser_o <= 'bz; + awid_o <= 'bz; + awlock_o <= 'bz; + awvalid_o <= 'bz; + wdata_o <= 'bz; + wstrb_o <= 'bz; + wvalid_o <= 'bz; + wlast_o <= 'bz; + bready_o <= 'bz; + // Bi-directional signals + + end +// pragma uvmf custom reset_condition_and_response end + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the driver BFM. It is called by the driver within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the driver BFM needs to be aware of the new configuration + // variables. + // + + function void configure(fuse_ctrl_prim_axi_write_in_configuration_s fuse_ctrl_prim_axi_write_in_configuration_arg); // pragma tbx xtf + initiator_responder = fuse_ctrl_prim_axi_write_in_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + +// pragma uvmf custom initiate_and_get_response begin +// **************************************************************************** +// UVMF_CHANGE_ME +// This task is used by an initator. The task first initiates a transfer then +// waits for the responder to complete the transfer. + task initiate_and_get_response( + // This argument passes transaction variables used by an initiator + // to perform the initial part of a protocol transfer. The values + // come from a sequence item created in a sequence. + input fuse_ctrl_prim_axi_write_in_initiator_s fuse_ctrl_prim_axi_write_in_initiator_struct, + // This argument is used to send data received from the responder + // back to the sequence item. The sequence item is returned to the sequence. + output fuse_ctrl_prim_axi_write_in_responder_s fuse_ctrl_prim_axi_write_in_responder_struct + );// pragma tbx xtf + // + // Members within the fuse_ctrl_prim_axi_write_in_initiator_struct: + // logic [AW-1:0] prim_awaddr ; + // logic prim_awvalid ; + // logic [$bits(axi_pkg::axi_burst_e)] prim_awburst ; + // logic [2:0] prim_awsize ; + // logic [7:0] prim_awlen ; + // logic [UW-1:0] prim_awuser ; + // logic [IW-1:0] prim_awid ; + // logic prim_awlock ; + // logic [DW-1:0] prim_wdata ; + // logic [DW/8 - 1:0] prim_wstrb ; + // logic prim_wvalid ; + // logic prim_wlast ; + // logic prim_bready ; + // Members within the fuse_ctrl_prim_axi_write_in_responder_struct: + // logic [AW-1:0] prim_awaddr ; + // logic prim_awvalid ; + // logic [$bits(axi_pkg::axi_burst_e)] prim_awburst ; + // logic [2:0] prim_awsize ; + // logic [7:0] prim_awlen ; + // logic [UW-1:0] prim_awuser ; + // logic [IW-1:0] prim_awid ; + // logic prim_awlock ; + // logic [DW-1:0] prim_wdata ; + // logic [DW/8 - 1:0] prim_wstrb ; + // logic prim_wvalid ; + // logic prim_wlast ; + // logic prim_bready ; + initiator_struct = fuse_ctrl_prim_axi_write_in_initiator_struct; + // + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clk_i_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available initiator input and inout signals listed. + // Initiator input signals + // Initiator inout signals + // How to assign a signal from an initiator struct member named xyz. + // All available initiator output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Initiator output signals + // awaddr_o <= fuse_ctrl_prim_axi_write_in_initiator_struct.xyz; // [AW-1:0] + // awburst_o <= fuse_ctrl_prim_axi_write_in_initiator_struct.xyz; // [$bits(axi_pkg::axi_burst_e)-1:0] + // awsize_o <= fuse_ctrl_prim_axi_write_in_initiator_struct.xyz; // [2:0] + // awlen_o <= fuse_ctrl_prim_axi_write_in_initiator_struct.xyz; // [7:0] + // awuser_o <= fuse_ctrl_prim_axi_write_in_initiator_struct.xyz; // [UW-1:0] + // awid_o <= fuse_ctrl_prim_axi_write_in_initiator_struct.xyz; // [UW-1:0] + // awlock_o <= fuse_ctrl_prim_axi_write_in_initiator_struct.xyz; // + // awvalid_o <= fuse_ctrl_prim_axi_write_in_initiator_struct.xyz; // + // wdata_o <= fuse_ctrl_prim_axi_write_in_initiator_struct.xyz; // [DW-1:0] + // wstrb_o <= fuse_ctrl_prim_axi_write_in_initiator_struct.xyz; // [DW/8-1:0] + // wvalid_o <= fuse_ctrl_prim_axi_write_in_initiator_struct.xyz; // + // wlast_o <= fuse_ctrl_prim_axi_write_in_initiator_struct.xyz; // + // bready_o <= fuse_ctrl_prim_axi_write_in_initiator_struct.xyz; // + // Initiator inout signals + // Initiate a transfer using the data received. + @(posedge clk_i_i); + @(posedge clk_i_i); + // Wait for the responder to complete the transfer then place the responder data into + // fuse_ctrl_prim_axi_write_in_responder_struct. + @(posedge clk_i_i); + @(posedge clk_i_i); + responder_struct = fuse_ctrl_prim_axi_write_in_responder_struct; + endtask +// pragma uvmf custom initiate_and_get_response end + +// pragma uvmf custom respond_and_wait_for_next_transfer begin +// **************************************************************************** +// The first_transfer variable is used to prevent completing a transfer in the +// first call to this task. For the first call to this task, there is not +// current transfer to complete. +bit first_transfer=1; + +// UVMF_CHANGE_ME +// This task is used by a responder. The task first completes the current +// transfer in progress then waits for the initiator to start the next transfer. + task respond_and_wait_for_next_transfer( + // This argument is used to send data received from the initiator + // back to the sequence item. The sequence determines how to respond. + output fuse_ctrl_prim_axi_write_in_initiator_s fuse_ctrl_prim_axi_write_in_initiator_struct, + // This argument passes transaction variables used by a responder + // to complete a protocol transfer. The values come from a sequence item. + input fuse_ctrl_prim_axi_write_in_responder_s fuse_ctrl_prim_axi_write_in_responder_struct + );// pragma tbx xtf + // Variables within the fuse_ctrl_prim_axi_write_in_initiator_struct: + // logic [AW-1:0] prim_awaddr ; + // logic prim_awvalid ; + // logic [$bits(axi_pkg::axi_burst_e)] prim_awburst ; + // logic [2:0] prim_awsize ; + // logic [7:0] prim_awlen ; + // logic [UW-1:0] prim_awuser ; + // logic [IW-1:0] prim_awid ; + // logic prim_awlock ; + // logic [DW-1:0] prim_wdata ; + // logic [DW/8 - 1:0] prim_wstrb ; + // logic prim_wvalid ; + // logic prim_wlast ; + // logic prim_bready ; + // Variables within the fuse_ctrl_prim_axi_write_in_responder_struct: + // logic [AW-1:0] prim_awaddr ; + // logic prim_awvalid ; + // logic [$bits(axi_pkg::axi_burst_e)] prim_awburst ; + // logic [2:0] prim_awsize ; + // logic [7:0] prim_awlen ; + // logic [UW-1:0] prim_awuser ; + // logic [IW-1:0] prim_awid ; + // logic prim_awlock ; + // logic [DW-1:0] prim_wdata ; + // logic [DW/8 - 1:0] prim_wstrb ; + // logic prim_wvalid ; + // logic prim_wlast ; + // logic prim_bready ; + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clk_i_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available responder input and inout signals listed. + // Responder input signals + // fuse_ctrl_prim_axi_write_in_responder_struct.xyz = awaddr_i; // [AW-1:0] + // fuse_ctrl_prim_axi_write_in_responder_struct.xyz = awburst_i; // [$bits(axi_pkg::axi_burst_e)-1:0] + // fuse_ctrl_prim_axi_write_in_responder_struct.xyz = awsize_i; // [2:0] + // fuse_ctrl_prim_axi_write_in_responder_struct.xyz = awlen_i; // [7:0] + // fuse_ctrl_prim_axi_write_in_responder_struct.xyz = awuser_i; // [UW-1:0] + // fuse_ctrl_prim_axi_write_in_responder_struct.xyz = awid_i; // [UW-1:0] + // fuse_ctrl_prim_axi_write_in_responder_struct.xyz = awlock_i; // + // fuse_ctrl_prim_axi_write_in_responder_struct.xyz = awvalid_i; // + // fuse_ctrl_prim_axi_write_in_responder_struct.xyz = wdata_i; // [DW-1:0] + // fuse_ctrl_prim_axi_write_in_responder_struct.xyz = wstrb_i; // [DW/8-1:0] + // fuse_ctrl_prim_axi_write_in_responder_struct.xyz = wvalid_i; // + // fuse_ctrl_prim_axi_write_in_responder_struct.xyz = wlast_i; // + // fuse_ctrl_prim_axi_write_in_responder_struct.xyz = bready_i; // + // Responder inout signals + // How to assign a signal, named xyz, from an initiator struct member. + // All available responder output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Responder output signals + // Responder inout signals + + @(posedge clk_i_i); + if (!first_transfer) begin + // Perform transfer response here. + // Reply using data recieved in the fuse_ctrl_prim_axi_write_in_responder_struct. + @(posedge clk_i_i); + // Reply using data recieved in the transaction handle. + @(posedge clk_i_i); + end + // Wait for next transfer then gather info from intiator about the transfer. + // Place the data into the fuse_ctrl_prim_axi_write_in_initiator_struct. + @(posedge clk_i_i); + @(posedge clk_i_i); + first_transfer = 0; + endtask +// pragma uvmf custom respond_and_wait_for_next_transfer end + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_if.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_if.sv new file mode 100644 index 0000000..9375d70 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_if.sv @@ -0,0 +1,143 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface contains the fuse_ctrl_prim_axi_write_in interface signals. +// It is instantiated once per fuse_ctrl_prim_axi_write_in bus. Bus Functional Models, +// BFM's named fuse_ctrl_prim_axi_write_in_driver_bfm, are used to drive signals on the bus. +// BFM's named fuse_ctrl_prim_axi_write_in_monitor_bfm are used to monitor signals on the +// bus. This interface signal bundle is passed in the port list of +// the BFM in order to give the BFM access to the signals in this +// interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// This template can be used to connect a DUT to these signals +// +// .dut_signal_port(fuse_ctrl_prim_axi_write_in_bus.awaddr), // Agent output +// .dut_signal_port(fuse_ctrl_prim_axi_write_in_bus.awburst), // Agent output +// .dut_signal_port(fuse_ctrl_prim_axi_write_in_bus.awsize), // Agent output +// .dut_signal_port(fuse_ctrl_prim_axi_write_in_bus.awlen), // Agent output +// .dut_signal_port(fuse_ctrl_prim_axi_write_in_bus.awuser), // Agent output +// .dut_signal_port(fuse_ctrl_prim_axi_write_in_bus.awid), // Agent output +// .dut_signal_port(fuse_ctrl_prim_axi_write_in_bus.awlock), // Agent output +// .dut_signal_port(fuse_ctrl_prim_axi_write_in_bus.awvalid), // Agent output +// .dut_signal_port(fuse_ctrl_prim_axi_write_in_bus.wdata), // Agent output +// .dut_signal_port(fuse_ctrl_prim_axi_write_in_bus.wstrb), // Agent output +// .dut_signal_port(fuse_ctrl_prim_axi_write_in_bus.wvalid), // Agent output +// .dut_signal_port(fuse_ctrl_prim_axi_write_in_bus.wlast), // Agent output +// .dut_signal_port(fuse_ctrl_prim_axi_write_in_bus.bready), // Agent output + +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_prim_axi_write_in_pkg_hdl::*; + +interface fuse_ctrl_prim_axi_write_in_if #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + + ( + input tri clk_i, + input tri rst_ni, + inout tri [AW-1:0] awaddr, + inout tri [$bits(axi_pkg::axi_burst_e)-1:0] awburst, + inout tri [2:0] awsize, + inout tri [7:0] awlen, + inout tri [UW-1:0] awuser, + inout tri [UW-1:0] awid, + inout tri awlock, + inout tri awvalid, + inout tri [DW-1:0] wdata, + inout tri [DW/8-1:0] wstrb, + inout tri wvalid, + inout tri wlast, + inout tri bready + ); + +modport monitor_port + ( + input clk_i, + input rst_ni, + input awaddr, + input awburst, + input awsize, + input awlen, + input awuser, + input awid, + input awlock, + input awvalid, + input wdata, + input wstrb, + input wvalid, + input wlast, + input bready + ); + +modport initiator_port + ( + input clk_i, + input rst_ni, + output awaddr, + output awburst, + output awsize, + output awlen, + output awuser, + output awid, + output awlock, + output awvalid, + output wdata, + output wstrb, + output wvalid, + output wlast, + output bready + ); + +modport responder_port + ( + input clk_i, + input rst_ni, + input awaddr, + input awburst, + input awsize, + input awlen, + input awuser, + input awid, + input awlock, + input awvalid, + input wdata, + input wstrb, + input wvalid, + input wlast, + input bready + ); + + +// pragma uvmf custom interface_item_additional begin +// pragma uvmf custom interface_item_additional end + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_infact_coverage_strategy.csv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_infact_coverage_strategy.csv new file mode 100644 index 0000000..1c218e1 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_infact_coverage_strategy.csv @@ -0,0 +1,6 @@ +Global +auto_bin_max, 64 + +Name,Type,Include +rand_fields,coverpoint,=rand *.** + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_macros.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_macros.svh new file mode 100644 index 0000000..5d21a90 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_macros.svh @@ -0,0 +1,243 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains macros used with the fuse_ctrl_prim_axi_write_in package. +// These macros include packed struct definitions. These structs are +// used to pass data between classes, hvl, and BFM's, hdl. Use of +// structs are more efficient and simpler to modify. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_struct +// and from_struct methods defined in the macros below that are used in +// the fuse_ctrl_prim_axi_write_in_configuration class. +// + `define fuse_ctrl_prim_axi_write_in_CONFIGURATION_STRUCT \ +typedef struct packed { \ + uvmf_active_passive_t active_passive; \ + uvmf_initiator_responder_t initiator_responder; \ + } fuse_ctrl_prim_axi_write_in_configuration_s; + + `define fuse_ctrl_prim_axi_write_in_CONFIGURATION_TO_STRUCT_FUNCTION \ + virtual function fuse_ctrl_prim_axi_write_in_configuration_s to_struct();\ + fuse_ctrl_prim_axi_write_in_configuration_struct = \ + {\ + this.active_passive,\ + this.initiator_responder\ + };\ + return ( fuse_ctrl_prim_axi_write_in_configuration_struct );\ + endfunction + + `define fuse_ctrl_prim_axi_write_in_CONFIGURATION_FROM_STRUCT_FUNCTION \ + virtual function void from_struct(fuse_ctrl_prim_axi_write_in_configuration_s fuse_ctrl_prim_axi_write_in_configuration_struct);\ + {\ + this.active_passive,\ + this.initiator_responder \ + } = fuse_ctrl_prim_axi_write_in_configuration_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_monitor_struct +// and from_monitor_struct methods of the fuse_ctrl_prim_axi_write_in_transaction class. +// + `define fuse_ctrl_prim_axi_write_in_MONITOR_STRUCT typedef struct packed { \ + logic [AW-1:0] prim_awaddr ; \ + logic prim_awvalid ; \ + logic [$bits(axi_pkg::axi_burst_e)] prim_awburst ; \ + logic [2:0] prim_awsize ; \ + logic [7:0] prim_awlen ; \ + logic [UW-1:0] prim_awuser ; \ + logic [IW-1:0] prim_awid ; \ + logic prim_awlock ; \ + logic [DW-1:0] prim_wdata ; \ + logic [DW/8 - 1:0] prim_wstrb ; \ + logic prim_wvalid ; \ + logic prim_wlast ; \ + logic prim_bready ; \ + } fuse_ctrl_prim_axi_write_in_monitor_s; + + `define fuse_ctrl_prim_axi_write_in_TO_MONITOR_STRUCT_FUNCTION \ + virtual function fuse_ctrl_prim_axi_write_in_monitor_s to_monitor_struct();\ + fuse_ctrl_prim_axi_write_in_monitor_struct = \ + { \ + this.prim_awaddr , \ + this.prim_awvalid , \ + this.prim_awburst , \ + this.prim_awsize , \ + this.prim_awlen , \ + this.prim_awuser , \ + this.prim_awid , \ + this.prim_awlock , \ + this.prim_wdata , \ + this.prim_wstrb , \ + this.prim_wvalid , \ + this.prim_wlast , \ + this.prim_bready \ + };\ + return ( fuse_ctrl_prim_axi_write_in_monitor_struct);\ + endfunction\ + + `define fuse_ctrl_prim_axi_write_in_FROM_MONITOR_STRUCT_FUNCTION \ + virtual function void from_monitor_struct(fuse_ctrl_prim_axi_write_in_monitor_s fuse_ctrl_prim_axi_write_in_monitor_struct);\ + {\ + this.prim_awaddr , \ + this.prim_awvalid , \ + this.prim_awburst , \ + this.prim_awsize , \ + this.prim_awlen , \ + this.prim_awuser , \ + this.prim_awid , \ + this.prim_awlock , \ + this.prim_wdata , \ + this.prim_wstrb , \ + this.prim_wvalid , \ + this.prim_wlast , \ + this.prim_bready \ + } = fuse_ctrl_prim_axi_write_in_monitor_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_initiator_struct +// and from_initiator_struct methods of the fuse_ctrl_prim_axi_write_in_transaction class. +// Also update the comments in the driver BFM. +// + `define fuse_ctrl_prim_axi_write_in_INITIATOR_STRUCT typedef struct packed { \ + logic [AW-1:0] prim_awaddr ; \ + logic prim_awvalid ; \ + logic [$bits(axi_pkg::axi_burst_e)] prim_awburst ; \ + logic [2:0] prim_awsize ; \ + logic [7:0] prim_awlen ; \ + logic [UW-1:0] prim_awuser ; \ + logic [IW-1:0] prim_awid ; \ + logic prim_awlock ; \ + logic [DW-1:0] prim_wdata ; \ + logic [DW/8 - 1:0] prim_wstrb ; \ + logic prim_wvalid ; \ + logic prim_wlast ; \ + logic prim_bready ; \ + } fuse_ctrl_prim_axi_write_in_initiator_s; + + `define fuse_ctrl_prim_axi_write_in_TO_INITIATOR_STRUCT_FUNCTION \ + virtual function fuse_ctrl_prim_axi_write_in_initiator_s to_initiator_struct();\ + fuse_ctrl_prim_axi_write_in_initiator_struct = \ + {\ + this.prim_awaddr , \ + this.prim_awvalid , \ + this.prim_awburst , \ + this.prim_awsize , \ + this.prim_awlen , \ + this.prim_awuser , \ + this.prim_awid , \ + this.prim_awlock , \ + this.prim_wdata , \ + this.prim_wstrb , \ + this.prim_wvalid , \ + this.prim_wlast , \ + this.prim_bready \ + };\ + return ( fuse_ctrl_prim_axi_write_in_initiator_struct);\ + endfunction + + `define fuse_ctrl_prim_axi_write_in_FROM_INITIATOR_STRUCT_FUNCTION \ + virtual function void from_initiator_struct(fuse_ctrl_prim_axi_write_in_initiator_s fuse_ctrl_prim_axi_write_in_initiator_struct);\ + {\ + this.prim_awaddr , \ + this.prim_awvalid , \ + this.prim_awburst , \ + this.prim_awsize , \ + this.prim_awlen , \ + this.prim_awuser , \ + this.prim_awid , \ + this.prim_awlock , \ + this.prim_wdata , \ + this.prim_wstrb , \ + this.prim_wvalid , \ + this.prim_wlast , \ + this.prim_bready \ + } = fuse_ctrl_prim_axi_write_in_initiator_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_responder_struct +// and from_responder_struct methods of the fuse_ctrl_prim_axi_write_in_transaction class. +// Also update the comments in the driver BFM. +// + `define fuse_ctrl_prim_axi_write_in_RESPONDER_STRUCT typedef struct packed { \ + logic [AW-1:0] prim_awaddr ; \ + logic prim_awvalid ; \ + logic [$bits(axi_pkg::axi_burst_e)] prim_awburst ; \ + logic [2:0] prim_awsize ; \ + logic [7:0] prim_awlen ; \ + logic [UW-1:0] prim_awuser ; \ + logic [IW-1:0] prim_awid ; \ + logic prim_awlock ; \ + logic [DW-1:0] prim_wdata ; \ + logic [DW/8 - 1:0] prim_wstrb ; \ + logic prim_wvalid ; \ + logic prim_wlast ; \ + logic prim_bready ; \ + } fuse_ctrl_prim_axi_write_in_responder_s; + + `define fuse_ctrl_prim_axi_write_in_TO_RESPONDER_STRUCT_FUNCTION \ + virtual function fuse_ctrl_prim_axi_write_in_responder_s to_responder_struct();\ + fuse_ctrl_prim_axi_write_in_responder_struct = \ + {\ + this.prim_awaddr , \ + this.prim_awvalid , \ + this.prim_awburst , \ + this.prim_awsize , \ + this.prim_awlen , \ + this.prim_awuser , \ + this.prim_awid , \ + this.prim_awlock , \ + this.prim_wdata , \ + this.prim_wstrb , \ + this.prim_wvalid , \ + this.prim_wlast , \ + this.prim_bready \ + };\ + return ( fuse_ctrl_prim_axi_write_in_responder_struct);\ + endfunction + + `define fuse_ctrl_prim_axi_write_in_FROM_RESPONDER_STRUCT_FUNCTION \ + virtual function void from_responder_struct(fuse_ctrl_prim_axi_write_in_responder_s fuse_ctrl_prim_axi_write_in_responder_struct);\ + {\ + this.prim_awaddr , \ + this.prim_awvalid , \ + this.prim_awburst , \ + this.prim_awsize , \ + this.prim_awlen , \ + this.prim_awuser , \ + this.prim_awid , \ + this.prim_awlock , \ + this.prim_wdata , \ + this.prim_wstrb , \ + this.prim_wvalid , \ + this.prim_wlast , \ + this.prim_bready \ + } = fuse_ctrl_prim_axi_write_in_responder_struct;\ + endfunction +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_monitor.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_monitor.svh new file mode 100644 index 0000000..ac0a5c9 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_monitor.svh @@ -0,0 +1,126 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class receives fuse_ctrl_prim_axi_write_in transactions observed by the +// fuse_ctrl_prim_axi_write_in monitor BFM and broadcasts them through the analysis port +// on the agent. It accesses the monitor BFM through the monitor +// task. This UVM component captures transactions +// for viewing in the waveform viewer if the +// enable_transaction_viewing flag is set in the configuration. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_write_in_monitor #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvmf_monitor_base #( + .CONFIG_T(fuse_ctrl_prim_axi_write_in_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .BFM_BIND_T(virtual fuse_ctrl_prim_axi_write_in_monitor_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .TRANS_T(fuse_ctrl_prim_axi_write_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ))); + + `uvm_component_param_utils( fuse_ctrl_prim_axi_write_in_monitor #( + AW, + DW, + IW, + UW + )) + +// Structure used to pass data from monitor BFM to monitor class in agent. +// Use to_monitor_struct function to pack transaction variables into structure. +// Use from_monitor_struct function to unpack transaction variables from structure. +`fuse_ctrl_prim_axi_write_in_MONITOR_STRUCT + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the monitor BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// monitor BFM. This allows the monitor BFM to call the notify_transaction +// function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// *************************************************************************** + virtual task run_phase(uvm_phase phase); + // Start monitor BFM thread and don't call super.run() in order to + // override the default monitor proxy 'pull' behavior with the more + // emulation-friendly BFM 'push' approach using the notify_transaction + // function below + bfm.start_monitoring(); + endtask + +// ************************************************************************** + +// This function is called by the monitor BFM. It receives data observed by the +// monitor BFM. Data is passed using the fuse_ctrl_prim_axi_write_in_monitor_struct. + virtual function void notify_transaction(input fuse_ctrl_prim_axi_write_in_monitor_s fuse_ctrl_prim_axi_write_in_monitor_struct); + + + trans = new("trans"); + trans.from_monitor_struct(fuse_ctrl_prim_axi_write_in_monitor_struct); + trans.start_time = time_stamp; + trans.end_time = $time; + time_stamp = trans.end_time; + + analyze(trans); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_monitor_bfm.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_monitor_bfm.sv new file mode 100644 index 0000000..801736a --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_monitor_bfm.sv @@ -0,0 +1,246 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface performs the fuse_ctrl_prim_axi_write_in signal monitoring. +// It is accessed by the uvm fuse_ctrl_prim_axi_write_in monitor through a virtual +// interface handle in the fuse_ctrl_prim_axi_write_in configuration. It monitors the +// signals passed in through the port connection named bus of +// type fuse_ctrl_prim_axi_write_in_if. +// +// Input signals from the fuse_ctrl_prim_axi_write_in_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// Interface functions and tasks used by UVM components: +// monitor(inout TRANS_T txn); +// This task receives the transaction, txn, from the +// UVM monitor and then populates variables in txn +// from values observed on bus activity. This task +// blocks until an operation on the fuse_ctrl_prim_axi_write_in bus is complete. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_prim_axi_write_in_pkg_hdl::*; +`include "src/fuse_ctrl_prim_axi_write_in_macros.svh" + + +interface fuse_ctrl_prim_axi_write_in_monitor_bfm #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + ( fuse_ctrl_prim_axi_write_in_if bus ); + // The pragma below and additional ones in-lined further down are for running this BFM on Veloce + // pragma attribute fuse_ctrl_prim_axi_write_in_monitor_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: AW=%x DW=%x IW=%x UW=%x ", AW,DW,IW,UW), + UVM_DEBUG) +end +`endif + + + // Structure used to pass transaction data from monitor BFM to monitor class in agent. +`fuse_ctrl_prim_axi_write_in_MONITOR_STRUCT + fuse_ctrl_prim_axi_write_in_monitor_s fuse_ctrl_prim_axi_write_in_monitor_struct; + + // Structure used to pass configuration data from monitor class to monitor BFM. + `fuse_ctrl_prim_axi_write_in_CONFIGURATION_STRUCT + + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + tri clk_i_i; + tri rst_ni_i; + tri [AW-1:0] awaddr_i; + tri [$bits(axi_pkg::axi_burst_e)-1:0] awburst_i; + tri [2:0] awsize_i; + tri [7:0] awlen_i; + tri [UW-1:0] awuser_i; + tri [UW-1:0] awid_i; + tri awlock_i; + tri awvalid_i; + tri [DW-1:0] wdata_i; + tri [DW/8-1:0] wstrb_i; + tri wvalid_i; + tri wlast_i; + tri bready_i; + assign clk_i_i = bus.clk_i; + assign rst_ni_i = bus.rst_ni; + assign awaddr_i = bus.awaddr; + assign awburst_i = bus.awburst; + assign awsize_i = bus.awsize; + assign awlen_i = bus.awlen; + assign awuser_i = bus.awuser; + assign awid_i = bus.awid; + assign awlock_i = bus.awlock; + assign awvalid_i = bus.awvalid; + assign wdata_i = bus.wdata; + assign wstrb_i = bus.wstrb; + assign wvalid_i = bus.wvalid; + assign wlast_i = bus.wlast; + assign bready_i = bus.bready; + + // Proxy handle to UVM monitor + fuse_ctrl_prim_axi_write_in_pkg::fuse_ctrl_prim_axi_write_in_monitor #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) proxy; + // pragma tbx oneway proxy.notify_transaction + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + task wait_for_reset();// pragma tbx xtf + @(posedge clk_i_i) ; + do_wait_for_reset(); + endtask + + // **************************************************************************** + task do_wait_for_reset(); + // pragma uvmf custom reset_condition begin + wait ( rst_ni_i === 1 ) ; + @(posedge clk_i_i) ; + // pragma uvmf custom reset_condition end + endtask + + //****************************************************************** + + task wait_for_num_clocks(input int unsigned count); // pragma tbx xtf + @(posedge clk_i_i); + + repeat (count-1) @(posedge clk_i_i); + endtask + + //****************************************************************** + event go; + function void start_monitoring();// pragma tbx xtf + -> go; + endfunction + + // **************************************************************************** + initial begin + @go; + forever begin + @(posedge clk_i_i); + do_monitor( fuse_ctrl_prim_axi_write_in_monitor_struct ); + + + proxy.notify_transaction( fuse_ctrl_prim_axi_write_in_monitor_struct ); + + end + end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the monitor BFM. It is called by the monitor within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the monitor BFM needs to be aware of the new configuration + // variables. + // + function void configure(fuse_ctrl_prim_axi_write_in_configuration_s fuse_ctrl_prim_axi_write_in_configuration_arg); // pragma tbx xtf + initiator_responder = fuse_ctrl_prim_axi_write_in_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + + + // **************************************************************************** + + task do_monitor(output fuse_ctrl_prim_axi_write_in_monitor_s fuse_ctrl_prim_axi_write_in_monitor_struct); + // + // Available struct members: + // // fuse_ctrl_prim_axi_write_in_monitor_struct.prim_awaddr + // // fuse_ctrl_prim_axi_write_in_monitor_struct.prim_awvalid + // // fuse_ctrl_prim_axi_write_in_monitor_struct.prim_awburst + // // fuse_ctrl_prim_axi_write_in_monitor_struct.prim_awsize + // // fuse_ctrl_prim_axi_write_in_monitor_struct.prim_awlen + // // fuse_ctrl_prim_axi_write_in_monitor_struct.prim_awuser + // // fuse_ctrl_prim_axi_write_in_monitor_struct.prim_awid + // // fuse_ctrl_prim_axi_write_in_monitor_struct.prim_awlock + // // fuse_ctrl_prim_axi_write_in_monitor_struct.prim_wdata + // // fuse_ctrl_prim_axi_write_in_monitor_struct.prim_wstrb + // // fuse_ctrl_prim_axi_write_in_monitor_struct.prim_wvalid + // // fuse_ctrl_prim_axi_write_in_monitor_struct.prim_wlast + // // fuse_ctrl_prim_axi_write_in_monitor_struct.prim_bready + // // + // Reference code; + // How to wait for signal value + // while (control_signal === 1'b1) @(posedge clk_i_i); + // + // How to assign a struct member, named xyz, from a signal. + // All available input signals listed. + // fuse_ctrl_prim_axi_write_in_monitor_struct.xyz = awaddr_i; // [AW-1:0] + // fuse_ctrl_prim_axi_write_in_monitor_struct.xyz = awburst_i; // [$bits(axi_pkg::axi_burst_e)-1:0] + // fuse_ctrl_prim_axi_write_in_monitor_struct.xyz = awsize_i; // [2:0] + // fuse_ctrl_prim_axi_write_in_monitor_struct.xyz = awlen_i; // [7:0] + // fuse_ctrl_prim_axi_write_in_monitor_struct.xyz = awuser_i; // [UW-1:0] + // fuse_ctrl_prim_axi_write_in_monitor_struct.xyz = awid_i; // [UW-1:0] + // fuse_ctrl_prim_axi_write_in_monitor_struct.xyz = awlock_i; // + // fuse_ctrl_prim_axi_write_in_monitor_struct.xyz = awvalid_i; // + // fuse_ctrl_prim_axi_write_in_monitor_struct.xyz = wdata_i; // [DW-1:0] + // fuse_ctrl_prim_axi_write_in_monitor_struct.xyz = wstrb_i; // [DW/8-1:0] + // fuse_ctrl_prim_axi_write_in_monitor_struct.xyz = wvalid_i; // + // fuse_ctrl_prim_axi_write_in_monitor_struct.xyz = wlast_i; // + // fuse_ctrl_prim_axi_write_in_monitor_struct.xyz = bready_i; // + // pragma uvmf custom do_monitor begin + // UVMF_CHANGE_ME : Implement protocol monitoring. The commented reference code + // below are examples of how to capture signal values and assign them to + // structure members. All available input signals are listed. The 'while' + // code example shows how to wait for a synchronous flow control signal. This + // task should return when a complete transfer has been observed. Once this task is + // exited with captured values, it is then called again to wait for and observe + // the next transfer. One clock cycle is consumed between calls to do_monitor. + @(posedge clk_i_i); + @(posedge clk_i_i); + @(posedge clk_i_i); + @(posedge clk_i_i); + // pragma uvmf custom do_monitor end + endtask + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_random_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_random_sequence.svh new file mode 100644 index 0000000..b45c725 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_random_sequence.svh @@ -0,0 +1,87 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This sequences randomizes the fuse_ctrl_prim_axi_write_in transaction and sends it +// to the UVM driver. +// +// This sequence constructs and randomizes a fuse_ctrl_prim_axi_write_in_transaction. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_write_in_random_sequence #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends fuse_ctrl_prim_axi_write_in_sequence_base #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ); + + `uvm_object_param_utils( fuse_ctrl_prim_axi_write_in_random_sequence #( + AW, + DW, + IW, + UW + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //***************************************************************** + function new(string name = ""); + super.new(name); + endfunction: new + + // **************************************************************************** + // TASK : body() + // This task is automatically executed when this sequence is started using the + // start(sequencerHandle) task. + // + task body(); + + // Construct the transaction + req=fuse_ctrl_prim_axi_write_in_transaction#( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )::type_id::create("req"); + start_item(req); + // Randomize the transaction + if(!req.randomize()) `uvm_fatal("SEQ", "fuse_ctrl_prim_axi_write_in_random_sequence::body()-fuse_ctrl_prim_axi_write_in_transaction randomization failed") + // Send the transaction to the fuse_ctrl_prim_axi_write_in_driver_bfm via the sequencer and fuse_ctrl_prim_axi_write_in_driver. + finish_item(req); + `uvm_info("SEQ", {"Response:",req.convert2string()},UVM_MEDIUM) + + endtask + +endclass: fuse_ctrl_prim_axi_write_in_random_sequence + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_responder_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_responder_sequence.svh new file mode 100644 index 0000000..8f4a7f5 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_responder_sequence.svh @@ -0,0 +1,83 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class can be used to provide stimulus when an interface +// has been configured to run in a responder mode. It +// will never finish by default, always going back to the driver +// and driver BFM for the next transaction with which to respond. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_write_in_responder_sequence #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends fuse_ctrl_prim_axi_write_in_sequence_base #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ); + + `uvm_object_param_utils( fuse_ctrl_prim_axi_write_in_responder_sequence #( + AW, + DW, + IW, + UW + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "fuse_ctrl_prim_axi_write_in_responder_sequence"); + super.new(name); + endfunction + + task body(); + req=fuse_ctrl_prim_axi_write_in_transaction#( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )::type_id::create("req"); + forever begin + start_item(req); + finish_item(req); + // pragma uvmf custom body begin + // UVMF_CHANGE_ME : Do something here with the resulting req item. The + // finish_item() call above will block until the req transaction is ready + // to be handled by the responder sequence. + // If this was an item that required a response, the expectation is + // that the response should be populated within this transaction now. + `uvm_info("SEQ",$sformatf("Processed txn: %s",req.convert2string()),UVM_HIGH) + // pragma uvmf custom body end + end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_sequence_base.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_sequence_base.svh new file mode 100644 index 0000000..2392875 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_sequence_base.svh @@ -0,0 +1,140 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the class used as the base class for all sequences +// for this interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_write_in_sequence_base #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvmf_sequence_base #( + .REQ(fuse_ctrl_prim_axi_write_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .RSP(fuse_ctrl_prim_axi_write_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ))); + + `uvm_object_param_utils( fuse_ctrl_prim_axi_write_in_sequence_base #( + AW, + DW, + IW, + UW + )) + + // variables + typedef fuse_ctrl_prim_axi_write_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) fuse_ctrl_prim_axi_write_in_transaction_req_t; + fuse_ctrl_prim_axi_write_in_transaction_req_t req; + typedef fuse_ctrl_prim_axi_write_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) fuse_ctrl_prim_axi_write_in_transaction_rsp_t; + fuse_ctrl_prim_axi_write_in_transaction_rsp_t rsp; + + // Event for identifying when a response was received from the sequencer + event new_rsp; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // TASK : get_responses() + // This task recursively gets sequence item responses from the sequencer. + // + virtual task get_responses(); + fork + begin + // Block until new rsp available + get_response(rsp); + // New rsp received. Indicate to sequence using event. + ->new_rsp; + // Display the received response transaction + `uvm_info("SEQ", {"New response transaction:",rsp.convert2string()}, UVM_MEDIUM) + end + join_none + endtask + + // **************************************************************************** + // TASK : pre_body() + // This task is called automatically when start is called with call_pre_post set to 1 (default). + // By calling get_responses() within pre_body() any derived sequences are automatically + // processing response transactions. Only un-comment this call to get_responses() if you + // have configured the interface driver to utilize the response transaction path by setting + // the configuration variable "return_transaction_response" to 1. Otherwise it is possible + // to impact runtime performance and memory utilization. + // + virtual task pre_body(); + // pragma uvmf custom pre_body begin +// get_responses(); + // pragma uvmf custom pre_body end + endtask + + // **************************************************************************** + // TASK : body() + // This task is called automatically when start is called. This sequence sends + // a req sequence item to the sequencer identified as an argument in the call + // to start. + // + virtual task body(); + // pragma uvmf custom body begin + start_item(req); + finish_item(req); + // pragma uvmf custom body end + endtask + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name =""); + super.new( name ); + // pragma uvmf custom new begin + req = fuse_ctrl_prim_axi_write_in_transaction_req_t::type_id::create("req"); + rsp = fuse_ctrl_prim_axi_write_in_transaction_rsp_t::type_id::create("rsp"); + // pragma uvmf custom new end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_transaction.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_transaction.svh new file mode 100644 index 0000000..9cc7421 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_transaction.svh @@ -0,0 +1,252 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class defines the variables required for an fuse_ctrl_prim_axi_write_in +// transaction. Class variables to be displayed in waveform transaction +// viewing are added to the transaction viewing stream in the add_to_wave +// function. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_write_in_transaction #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvmf_transaction_base; + + `uvm_object_param_utils( fuse_ctrl_prim_axi_write_in_transaction #( + AW, + DW, + IW, + UW + )) + + rand logic [AW-1:0] prim_awaddr ; + logic prim_awvalid ; + logic [$bits(axi_pkg::axi_burst_e)] prim_awburst ; + logic [2:0] prim_awsize ; + logic [7:0] prim_awlen ; + logic [UW-1:0] prim_awuser ; + logic [IW-1:0] prim_awid ; + logic prim_awlock ; + logic [DW-1:0] prim_wdata ; + logic [DW/8 - 1:0] prim_wstrb ; + logic prim_wvalid ; + logic prim_wlast ; + logic prim_bready ; + + //Constraints for the transaction variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //******************************************************************* + //******************************************************************* + // Macros that define structs and associated functions are + // located in fuse_ctrl_prim_axi_write_in_macros.svh + + //******************************************************************* + // Monitor macro used by fuse_ctrl_prim_axi_write_in_monitor and fuse_ctrl_prim_axi_write_in_monitor_bfm + // This struct is defined in fuse_ctrl_prim_axi_write_in_macros.svh + `fuse_ctrl_prim_axi_write_in_MONITOR_STRUCT + fuse_ctrl_prim_axi_write_in_monitor_s fuse_ctrl_prim_axi_write_in_monitor_struct; + //******************************************************************* + // FUNCTION: to_monitor_struct() + // This function packs transaction variables into a fuse_ctrl_prim_axi_write_in_monitor_s + // structure. The function returns the handle to the fuse_ctrl_prim_axi_write_in_monitor_struct. + // This function is defined in fuse_ctrl_prim_axi_write_in_macros.svh + `fuse_ctrl_prim_axi_write_in_TO_MONITOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_monitor_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_prim_axi_write_in_macros.svh + `fuse_ctrl_prim_axi_write_in_FROM_MONITOR_STRUCT_FUNCTION + + //******************************************************************* + // Initiator macro used by fuse_ctrl_prim_axi_write_in_driver and fuse_ctrl_prim_axi_write_in_driver_bfm + // to communicate initiator driven data to fuse_ctrl_prim_axi_write_in_driver_bfm. + // This struct is defined in fuse_ctrl_prim_axi_write_in_macros.svh + `fuse_ctrl_prim_axi_write_in_INITIATOR_STRUCT + fuse_ctrl_prim_axi_write_in_initiator_s fuse_ctrl_prim_axi_write_in_initiator_struct; + //******************************************************************* + // FUNCTION: to_initiator_struct() + // This function packs transaction variables into a fuse_ctrl_prim_axi_write_in_initiator_s + // structure. The function returns the handle to the fuse_ctrl_prim_axi_write_in_initiator_struct. + // This function is defined in fuse_ctrl_prim_axi_write_in_macros.svh + `fuse_ctrl_prim_axi_write_in_TO_INITIATOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_initiator_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_prim_axi_write_in_macros.svh + `fuse_ctrl_prim_axi_write_in_FROM_INITIATOR_STRUCT_FUNCTION + + //******************************************************************* + // Responder macro used by fuse_ctrl_prim_axi_write_in_driver and fuse_ctrl_prim_axi_write_in_driver_bfm + // to communicate Responder driven data to fuse_ctrl_prim_axi_write_in_driver_bfm. + // This struct is defined in fuse_ctrl_prim_axi_write_in_macros.svh + `fuse_ctrl_prim_axi_write_in_RESPONDER_STRUCT + fuse_ctrl_prim_axi_write_in_responder_s fuse_ctrl_prim_axi_write_in_responder_struct; + //******************************************************************* + // FUNCTION: to_responder_struct() + // This function packs transaction variables into a fuse_ctrl_prim_axi_write_in_responder_s + // structure. The function returns the handle to the fuse_ctrl_prim_axi_write_in_responder_struct. + // This function is defined in fuse_ctrl_prim_axi_write_in_macros.svh + `fuse_ctrl_prim_axi_write_in_TO_RESPONDER_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_responder_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_prim_axi_write_in_macros.svh + `fuse_ctrl_prim_axi_write_in_FROM_RESPONDER_STRUCT_FUNCTION + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + endfunction + + // **************************************************************************** + // FUNCTION: convert2string() + // This function converts all variables in this class to a single string for + // logfile reporting. + // + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + // UVMF_CHANGE_ME : Customize format if desired. + return $sformatf("prim_awaddr:0x%x prim_awvalid:0x%x prim_awburst:0x%x prim_awsize:0x%x prim_awlen:0x%x prim_awuser:0x%x prim_awid:0x%x prim_awlock:0x%x prim_wdata:0x%x prim_wstrb:0x%x prim_wvalid:0x%x prim_wlast:0x%x prim_bready:0x%x ",prim_awaddr,prim_awvalid,prim_awburst,prim_awsize,prim_awlen,prim_awuser,prim_awid,prim_awlock,prim_wdata,prim_wstrb,prim_wvalid,prim_wlast,prim_bready); + // pragma uvmf custom convert2string end + endfunction + + //******************************************************************* + // FUNCTION: do_print() + // This function is automatically called when the .print() function + // is called on this class. + // + virtual function void do_print(uvm_printer printer); + // pragma uvmf custom do_print begin + // UVMF_CHANGE_ME : Current contents of do_print allows for the use of UVM 1.1d, 1.2 or P1800.2. + // Update based on your own printing preference according to your preferred UVM version + $display(convert2string()); + // pragma uvmf custom do_print end + endfunction + + //******************************************************************* + // FUNCTION: do_compare() + // This function is automatically called when the .compare() function + // is called on this class. + // + virtual function bit do_compare (uvm_object rhs, uvm_comparer comparer); + fuse_ctrl_prim_axi_write_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) RHS; + if (!$cast(RHS,rhs)) return 0; + // pragma uvmf custom do_compare begin + // UVMF_CHANGE_ME : Eliminate comparison of variables not to be used for compare + return (super.do_compare(rhs,comparer) + &&(this.prim_wdata == RHS.prim_wdata) + ); + // pragma uvmf custom do_compare end + endfunction + + //******************************************************************* + // FUNCTION: do_copy() + // This function is automatically called when the .copy() function + // is called on this class. + // + virtual function void do_copy (uvm_object rhs); + fuse_ctrl_prim_axi_write_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) RHS; + assert($cast(RHS,rhs)); + // pragma uvmf custom do_copy begin + super.do_copy(rhs); + this.prim_awaddr = RHS.prim_awaddr; + this.prim_awvalid = RHS.prim_awvalid; + this.prim_awburst = RHS.prim_awburst; + this.prim_awsize = RHS.prim_awsize; + this.prim_awlen = RHS.prim_awlen; + this.prim_awuser = RHS.prim_awuser; + this.prim_awid = RHS.prim_awid; + this.prim_awlock = RHS.prim_awlock; + this.prim_wdata = RHS.prim_wdata; + this.prim_wstrb = RHS.prim_wstrb; + this.prim_wvalid = RHS.prim_wvalid; + this.prim_wlast = RHS.prim_wlast; + this.prim_bready = RHS.prim_bready; + // pragma uvmf custom do_copy end + endfunction + + // **************************************************************************** + // FUNCTION: add_to_wave() + // This function is used to display variables in this class in the waveform + // viewer. The start_time and end_time variables must be set before this + // function is called. If the start_time and end_time variables are not set + // the transaction will be hidden at 0ns on the waveform display. + // + virtual function void add_to_wave(int transaction_viewing_stream_h); + `ifdef QUESTA + if (transaction_view_h == 0) begin + transaction_view_h = $begin_transaction(transaction_viewing_stream_h,"fuse_ctrl_prim_axi_write_in_transaction",start_time); + end + super.add_to_wave(transaction_view_h); + // pragma uvmf custom add_to_wave begin + // UVMF_CHANGE_ME : Color can be applied to transaction entries based on content, example below + // case() + // 1 : $add_color(transaction_view_h,"red"); + // default : $add_color(transaction_view_h,"grey"); + // endcase + // UVMF_CHANGE_ME : Eliminate transaction variables not wanted in transaction viewing in the waveform viewer + $add_attribute(transaction_view_h,prim_awaddr,"prim_awaddr"); + $add_attribute(transaction_view_h,prim_awvalid,"prim_awvalid"); + $add_attribute(transaction_view_h,prim_awburst,"prim_awburst"); + $add_attribute(transaction_view_h,prim_awsize,"prim_awsize"); + $add_attribute(transaction_view_h,prim_awlen,"prim_awlen"); + $add_attribute(transaction_view_h,prim_awuser,"prim_awuser"); + $add_attribute(transaction_view_h,prim_awid,"prim_awid"); + $add_attribute(transaction_view_h,prim_awlock,"prim_awlock"); + $add_attribute(transaction_view_h,prim_wdata,"prim_wdata"); + $add_attribute(transaction_view_h,prim_wstrb,"prim_wstrb"); + $add_attribute(transaction_view_h,prim_wvalid,"prim_wvalid"); + $add_attribute(transaction_view_h,prim_wlast,"prim_wlast"); + $add_attribute(transaction_view_h,prim_bready,"prim_bready"); + // pragma uvmf custom add_to_wave end + $end_transaction(transaction_view_h,end_time); + $free_transaction(transaction_view_h); + `endif // QUESTA + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_transaction_coverage.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_transaction_coverage.svh new file mode 100644 index 0000000..582d238 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_transaction_coverage.svh @@ -0,0 +1,111 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class records fuse_ctrl_prim_axi_write_in transaction information using +// a covergroup named fuse_ctrl_prim_axi_write_in_transaction_cg. An instance of this +// coverage component is instantiated in the uvmf_parameterized_agent +// if the has_coverage flag is set. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_write_in_transaction_coverage #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvm_subscriber #(.T(fuse_ctrl_prim_axi_write_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ))); + + `uvm_component_param_utils( fuse_ctrl_prim_axi_write_in_transaction_coverage #( + AW, + DW, + IW, + UW + )) + + T coverage_trans; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + covergroup fuse_ctrl_prim_axi_write_in_transaction_cg; + // pragma uvmf custom covergroup begin + // UVMF_CHANGE_ME : Add coverage bins, crosses, exclusions, etc. according to coverage needs. + option.auto_bin_max=1024; + option.per_instance=1; + prim_awaddr: coverpoint coverage_trans.prim_awaddr; + prim_awvalid: coverpoint coverage_trans.prim_awvalid; + prim_awburst: coverpoint coverage_trans.prim_awburst; + prim_awsize: coverpoint coverage_trans.prim_awsize; + prim_awlen: coverpoint coverage_trans.prim_awlen; + prim_awuser: coverpoint coverage_trans.prim_awuser; + prim_awid: coverpoint coverage_trans.prim_awid; + prim_awlock: coverpoint coverage_trans.prim_awlock; + prim_wdata: coverpoint coverage_trans.prim_wdata; + prim_wstrb: coverpoint coverage_trans.prim_wstrb; + prim_wvalid: coverpoint coverage_trans.prim_wvalid; + prim_wlast: coverpoint coverage_trans.prim_wlast; + prim_bready: coverpoint coverage_trans.prim_bready; + // pragma uvmf custom covergroup end + endgroup + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new(string name="", uvm_component parent=null); + super.new(name,parent); + fuse_ctrl_prim_axi_write_in_transaction_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that transaction variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + endfunction + + // **************************************************************************** + // FUNCTION : build_phase() + // This function is the standard UVM build_phase. + // + function void build_phase(uvm_phase phase); + fuse_ctrl_prim_axi_write_in_transaction_cg.set_inst_name($sformatf("fuse_ctrl_prim_axi_write_in_transaction_cg_%s",get_full_name())); + endfunction + + // **************************************************************************** + // FUNCTION: write (T t) + // This function is automatically executed when a transaction arrives on the + // analysis_export. It copies values from the variables in the transaction + // to local variables used to collect functional coverage. + // + virtual function void write (T t); + `uvm_info("COV","Received transaction",UVM_HIGH); + coverage_trans = t; + fuse_ctrl_prim_axi_write_in_transaction_cg.sample(); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_typedefs.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_typedefs.svh new file mode 100644 index 0000000..f2a7bdb --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_typedefs.svh @@ -0,0 +1,34 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the host server when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_typedefs_hdl.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_typedefs_hdl.svh new file mode 100644 index 0000000..0d58518 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_typedefs_hdl.svh @@ -0,0 +1,35 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the emulator when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/yaml/fuse_ctrl_prim_axi_write_in_interface.yaml b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/yaml/fuse_ctrl_prim_axi_write_in_interface.yaml new file mode 100644 index 0000000..ec7591e --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/yaml/fuse_ctrl_prim_axi_write_in_interface.yaml @@ -0,0 +1,161 @@ +uvmf: + interfaces: + fuse_ctrl_prim_axi_write_in: + clock: clk_i + config_constraints: [] + config_vars: [] + existing_library_component: 'True' + gen_inbound_streaming_driver: 'False' + hdl_pkg_parameters: [] + hdl_typedefs: [] + hvl_pkg_parameters: [] + hvl_typedefs: [] + parameters: + - name: AW + type: int + value: '32' + - name: DW + type: int + value: '32' + - name: IW + type: int + value: '3' + - name: UW + type: int + value: '32' + ports: + - dir: output + name: awaddr + reset_value: '''bz' + width: '[''AW'']' + - dir: output + name: awburst + reset_value: '''bz' + width: '[''$bits(axi_pkg::axi_burst_e)'']' + - dir: output + name: awsize + reset_value: '''bz' + width: '3' + - dir: output + name: awlen + reset_value: '''bz' + width: '8' + - dir: output + name: awuser + reset_value: '''bz' + width: '[''UW'']' + - dir: output + name: awid + reset_value: '''bz' + width: '[''UW'']' + - dir: output + name: awlock + reset_value: '''bz' + width: '1' + - dir: output + name: awvalid + reset_value: '''bz' + width: '1' + - dir: output + name: wdata + reset_value: '''bz' + width: '[''DW'']' + - dir: output + name: wstrb + reset_value: '''bz' + width: '[''DW/8'']' + - dir: output + name: wvalid + reset_value: '''bz' + width: '1' + - dir: output + name: wlast + reset_value: '''bz' + width: '1' + - dir: output + name: bready + reset_value: '''bz' + width: '1' + reset: rst_ni + reset_assertion_level: 'False' + transaction_constraints: [] + transaction_vars: + - comment: '' + iscompare: 'False' + isrand: 'True' + name: prim_awaddr + type: logic [AW-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: prim_awvalid + type: logic + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: prim_awburst + type: logic [$bits(axi_pkg::axi_burst_e)] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: prim_awsize + type: logic [2:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: prim_awlen + type: logic [7:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: prim_awuser + type: logic [UW-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: prim_awid + type: logic [IW-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: prim_awlock + type: logic + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'False' + name: prim_wdata + type: logic [DW-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: prim_wstrb + type: logic [DW/8 - 1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: prim_wvalid + type: logic + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: prim_wlast + type: logic + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: prim_bready + type: logic + unpacked_dimension: '' + use_dpi_link: 'False' diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/.project b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/.project new file mode 100644 index 0000000..3e0bf6c --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/.project @@ -0,0 +1,30 @@ + + + fuse_ctrl_prim_axi_write_out_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/.svproject b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/.svproject new file mode 100644 index 0000000..376273a --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/Makefile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/Makefile new file mode 100644 index 0000000..7bd75ac --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/Makefile @@ -0,0 +1,66 @@ +# fuse_ctrl_prim_axi_write_out interface packages source +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +fuse_ctrl_prim_axi_write_out_PKG = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_write_out_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_filelist_hvl.f + +fuse_ctrl_prim_axi_write_out_PKG_HDL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_write_out_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_filelist_hdl.f + +fuse_ctrl_prim_axi_write_out_PKG_XRTL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_write_out_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_filelist_xrtl.f + +COMP_fuse_ctrl_prim_axi_write_out_PKG_TGT_0 = q_comp_fuse_ctrl_prim_axi_write_out_pkg +COMP_fuse_ctrl_prim_axi_write_out_PKG_TGT_1 = v_comp_fuse_ctrl_prim_axi_write_out_pkg +COMP_fuse_ctrl_prim_axi_write_out_PKG_TGT = $(COMP_fuse_ctrl_prim_axi_write_out_PKG_TGT_$(USE_VELOCE)) + +comp_fuse_ctrl_prim_axi_write_out_pkg: $(COMP_fuse_ctrl_prim_axi_write_out_PKG_TGT) + +q_comp_fuse_ctrl_prim_axi_write_out_pkg: + $(HDL_COMP_CMD) $(fuse_ctrl_prim_axi_write_out_PKG_HDL) + $(HVL_COMP_CMD) $(fuse_ctrl_prim_axi_write_out_PKG) + $(HDL_COMP_CMD) $(fuse_ctrl_prim_axi_write_out_PKG_XRTL) + +v_comp_fuse_ctrl_prim_axi_write_out_pkg: + $(HVL_COMP_CMD) $(fuse_ctrl_prim_axi_write_out_PKG_HDL) + $(HVL_COMP_CMD) $(fuse_ctrl_prim_axi_write_out_PKG) + $(VELANALYZE_CMD) $(fuse_ctrl_prim_axi_write_out_PKG_HDL) + $(VELANALYZE_HVL_CMD) $(fuse_ctrl_prim_axi_write_out_PKG) + $(HDL_COMP_CMD) $(fuse_ctrl_prim_axi_write_out_PKG_XRTL) + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export fuse_ctrl_prim_axi_write_out_IF_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/dpi + +C_FILE_COMPILE_LIST_fuse_ctrl_prim_axi_write_out_pkg = \ + +O_FILE_COMPILE_LIST_fuse_ctrl_prim_axi_write_out_pkg = $(notdir $(C_FILE_COMPILE_LIST_fuse_ctrl_prim_axi_write_out_pkg:.c=.o)) + +GCC_COMP_ARGS_fuse_ctrl_prim_axi_write_out_pkg += -I$(fuse_ctrl_prim_axi_write_out_IF_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_fuse_ctrl_prim_axi_write_out_pkg += $(fuse_ctrl_prim_axi_write_out_IF_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_fuse_ctrl_prim_axi_write_out_pkg += \ + \ + -o .so + +comp_fuse_ctrl_prim_axi_write_out_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Interface C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_fuse_ctrl_prim_axi_write_out_pkg) $(C_FILE_COMPILE_LIST_fuse_ctrl_prim_axi_write_out_pkg) + @echo "--------------------------------" + @echo "Linking Interface C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_fuse_ctrl_prim_axi_write_out_pkg) $(O_FILE_COMPILE_LIST_fuse_ctrl_prim_axi_write_out_pkg) + @echo "--------------------------------" + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/compile.do b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/compile.do new file mode 100644 index 0000000..2728571 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/compile.do @@ -0,0 +1,14 @@ +# Tcl do file for compile of fuse_ctrl_prim_axi_write_out interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_write_out_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_filelist_hdl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_write_out_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_filelist_hvl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_write_out_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_filelist_xrtl.f \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out.compile new file mode 100644 index 0000000..fa21f0f --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out.compile @@ -0,0 +1,3 @@ +needs: + - fuse_ctrl_prim_axi_write_out_hvl.compile + - fuse_ctrl_prim_axi_write_out_hdl.compile diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_bfm.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_bfm.vinfo new file mode 100644 index 0000000..708c584 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_bfm.vinfo @@ -0,0 +1,6 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use fuse_ctrl_prim_axi_write_out_pkg_hdl.vinfo ++incdir+@vinfodir +src/fuse_ctrl_prim_axi_write_out_if.sv +src/fuse_ctrl_prim_axi_write_out_driver_bfm.sv +src/fuse_ctrl_prim_axi_write_out_monitor_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_common.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_common.compile new file mode 100644 index 0000000..ba5ad35 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_common.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +incdir: + - . + - ${uvm_path}/src +src: + - fuse_ctrl_prim_axi_write_out_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_filelist_hdl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_filelist_hdl.f new file mode 100644 index 0000000..6b9dd5f --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_filelist_hdl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_filelist_hvl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_filelist_hvl.f new file mode 100644 index 0000000..6aea297 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_filelist_hvl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_pkg.sv \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_filelist_xrtl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_filelist_xrtl.f new file mode 100644 index 0000000..3c62931 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_filelist_xrtl.f @@ -0,0 +1,3 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_if.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_monitor_bfm.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_driver_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_hdl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_hdl.compile new file mode 100644 index 0000000..1a738c1 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_hdl.compile @@ -0,0 +1,9 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ./fuse_ctrl_prim_axi_write_out_common.compile +incdir: + - . +src: + - src/fuse_ctrl_prim_axi_write_out_if.sv + - src/fuse_ctrl_prim_axi_write_out_monitor_bfm.sv + - src/fuse_ctrl_prim_axi_write_out_driver_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_hvl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_hvl.compile new file mode 100644 index 0000000..894eaaf --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_hvl.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ./fuse_ctrl_prim_axi_write_out_common.compile +incdir: + - . +src: + - fuse_ctrl_prim_axi_write_out_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_pkg.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_pkg.sv new file mode 100644 index 0000000..50f57ff --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_pkg.sv @@ -0,0 +1,91 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - + +// - +// - +// - + +// - +// - +// - + +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_prim_axi_write_out_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg_hdl::*; + import uvmf_base_pkg::*; + import fuse_ctrl_prim_axi_write_out_pkg_hdl::*; + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + `include "src/fuse_ctrl_prim_axi_write_out_macros.svh" + + export fuse_ctrl_prim_axi_write_out_pkg_hdl::*; + + + + // Parameters defined as HVL parameters + + `include "src/fuse_ctrl_prim_axi_write_out_typedefs.svh" + `include "src/fuse_ctrl_prim_axi_write_out_transaction.svh" + + `include "src/fuse_ctrl_prim_axi_write_out_configuration.svh" + `include "src/fuse_ctrl_prim_axi_write_out_driver.svh" + `include "src/fuse_ctrl_prim_axi_write_out_monitor.svh" + + `include "src/fuse_ctrl_prim_axi_write_out_transaction_coverage.svh" + `include "src/fuse_ctrl_prim_axi_write_out_sequence_base.svh" + `include "src/fuse_ctrl_prim_axi_write_out_random_sequence.svh" + + `include "src/fuse_ctrl_prim_axi_write_out_responder_sequence.svh" + `include "src/fuse_ctrl_prim_axi_write_out2reg_adapter.svh" + + `include "src/fuse_ctrl_prim_axi_write_out_agent.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new interface sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the interface package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_pkg.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_pkg.vinfo new file mode 100644 index 0000000..790347e --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_pkg.vinfo @@ -0,0 +1,4 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use fuse_ctrl_prim_axi_write_out_pkg_hdl.vinfo ++incdir+@vinfodir +fuse_ctrl_prim_axi_write_out_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_pkg_hdl.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_pkg_hdl.sv new file mode 100644 index 0000000..bd64b4e --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_pkg_hdl.sv @@ -0,0 +1,52 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that needs to be compiled and synthesized +// for running on Veloce. +// +// CONTAINS: +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_prim_axi_write_out_pkg_hdl; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HDL parameters + + `include "src/fuse_ctrl_prim_axi_write_out_typedefs_hdl.svh" + `include "src/fuse_ctrl_prim_axi_write_out_macros.svh" + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_pkg_hdl.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_pkg_hdl.vinfo new file mode 100644 index 0000000..dfc2d8e --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_pkg_hdl.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +fuse_ctrl_prim_axi_write_out_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_pkg_sve.F b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_pkg_sve.F new file mode 100644 index 0000000..9a71aaf --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_pkg_sve.F @@ -0,0 +1,10 @@ +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + ++incdir+. +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_filelist_hdl.f +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_filelist_hvl.f diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out2reg_adapter.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out2reg_adapter.svh new file mode 100644 index 0000000..398f7c7 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out2reg_adapter.svh @@ -0,0 +1,137 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the UVM register adapter for the fuse_ctrl_prim_axi_write_out interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_write_out2reg_adapter #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvm_reg_adapter; + + `uvm_object_param_utils( fuse_ctrl_prim_axi_write_out2reg_adapter #( + AW, + DW, + IW, + UW + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //-------------------------------------------------------------------- + // new + //-------------------------------------------------------------------- + function new (string name = "fuse_ctrl_prim_axi_write_out2reg_adapter" ); + super.new(name); + // pragma uvmf custom new begin + // UVMF_CHANGE_ME : Configure the adapter regarding byte enables and provides response. + + // Does the protocol the Agent is modeling support byte enables? + // 0 = NO + // 1 = YES + supports_byte_enable = 0; + + // Does the Agent's Driver provide separate response sequence items? + // i.e. Does the driver call seq_item_port.put() + // and do the sequences call get_response()? + // 0 = NO + // 1 = YES + provides_responses = 0; + // pragma uvmf custom new end + + endfunction: new + + //-------------------------------------------------------------------- + // reg2bus + //-------------------------------------------------------------------- + virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw); + + fuse_ctrl_prim_axi_write_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) trans_h = fuse_ctrl_prim_axi_write_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )::type_id::create("trans_h"); + + // pragma uvmf custom reg2bus begin + // UVMF_CHANGE_ME : Fill in the reg2bus adapter mapping registe fields to protocol fields. + + //Adapt the following for your sequence item type + // trans_h.op = (rw.kind == UVM_READ) ? WB_READ : WB_WRITE; + //Copy over address + // trans_h.addr = rw.addr; + //Copy over write data + // trans_h.data = rw.data; + + // pragma uvmf custom reg2bus end + + // Return the adapted transaction + return trans_h; + + endfunction: reg2bus + + //-------------------------------------------------------------------- + // bus2reg + //-------------------------------------------------------------------- + virtual function void bus2reg(uvm_sequence_item bus_item, + ref uvm_reg_bus_op rw); + fuse_ctrl_prim_axi_write_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) trans_h; + if (!$cast(trans_h, bus_item)) begin + `uvm_fatal("ADAPT","Provided bus_item is not of the correct type") + return; + end + // pragma uvmf custom bus2reg begin + // UVMF_CHANGE_ME : Fill in the bus2reg adapter mapping protocol fields to register fields. + //Adapt the following for your sequence item type + //Copy over instruction type + // rw.kind = (trans_h.op == WB_WRITE) ? UVM_WRITE : UVM_READ; + //Copy over address + // rw.addr = trans_h.addr; + //Copy over read data + // rw.data = trans_h.data; + //Check for errors on the bus and return UVM_NOT_OK if there is an error + // rw.status = UVM_IS_OK; + // pragma uvmf custom bus2reg end + + endfunction: bus2reg + +endclass : fuse_ctrl_prim_axi_write_out2reg_adapter + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_agent.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_agent.svh new file mode 100644 index 0000000..9f22c5c --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_agent.svh @@ -0,0 +1,102 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: Protocol specific agent class definition +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_write_out_agent #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvmf_parameterized_agent #( + .CONFIG_T(fuse_ctrl_prim_axi_write_out_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .DRIVER_T(fuse_ctrl_prim_axi_write_out_driver #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .MONITOR_T(fuse_ctrl_prim_axi_write_out_monitor #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .COVERAGE_T(fuse_ctrl_prim_axi_write_out_transaction_coverage #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .TRANS_T(fuse_ctrl_prim_axi_write_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )) + ); + + `uvm_component_param_utils( fuse_ctrl_prim_axi_write_out_agent #( + AW, + DW, + IW, + UW + )) + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** + // FUNCTION: build_phase + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + if (configuration.active_passive == ACTIVE) begin + // Place sequencer handle into configuration object + // so that it may be retrieved from configuration + // rather than using uvm_config_db + configuration.sequencer = this.sequencer; + end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_configuration.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_configuration.svh new file mode 100644 index 0000000..ada4304 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_configuration.svh @@ -0,0 +1,233 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class contains all variables and functions used +// to configure the fuse_ctrl_prim_axi_write_out agent and its bfm's. It gets the +// bfm's from the uvm_config_db for use by the agent. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_write_out_configuration #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvmf_parameterized_agent_configuration_base #( + .DRIVER_BFM_BIND_T(virtual fuse_ctrl_prim_axi_write_out_driver_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .MONITOR_BFM_BIND_T( virtual fuse_ctrl_prim_axi_write_out_monitor_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ))); + + `uvm_object_param_utils( fuse_ctrl_prim_axi_write_out_configuration #( + AW, + DW, + IW, + UW + )) + + + // Sequencer handle populated by agent + uvm_sequencer #(fuse_ctrl_prim_axi_write_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) ) sequencer; + + //Constraints for the configuration variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + covergroup fuse_ctrl_prim_axi_write_out_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + // pragma uvmf custom covergroup end + endgroup + + //******************************************************************* + //******************************************************************* + // Structure used to pass configuration variables to monitor and driver BFM's. + // Use to_struct function to pack variables into structure. + // Use from_struct function to unpack variables from structure. + // This structure is defined in fuse_ctrl_prim_axi_write_out_macros.svh + `fuse_ctrl_prim_axi_write_out_CONFIGURATION_STRUCT + fuse_ctrl_prim_axi_write_out_configuration_s fuse_ctrl_prim_axi_write_out_configuration_struct; + //******************************************************************* + // FUNCTION: to_struct() + // This function packs variables into a fuse_ctrl_prim_axi_write_out_configuration_s + // structure. The function returns the handle to the fuse_ctrl_prim_axi_write_out_configuration_struct. + // This function is defined in fuse_ctrl_prim_axi_write_out_macros.svh + `fuse_ctrl_prim_axi_write_out_CONFIGURATION_TO_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_struct() + // This function unpacks the struct provided as an argument into + // variables of this class. + // This function is defined in fuse_ctrl_prim_axi_write_out_macros.svh + `fuse_ctrl_prim_axi_write_out_CONFIGURATION_FROM_STRUCT_FUNCTION + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + // Construct the covergroup for this configuration class + fuse_ctrl_prim_axi_write_out_configuration_cg = new; + endfunction + + // **************************************************************************** + // FUNCTION: post_randomize() + // This function is automatically called after the randomize() function + // is executed. + // + function void post_randomize(); + super.post_randomize(); + fuse_ctrl_prim_axi_write_out_configuration_cg.sample(); + endfunction + + // **************************************************************************** + // FUNCTION: initialize + // This function causes the configuration to retrieve + // its virtual interface handle from the uvm_config_db. + // This function also makes itself available to its + // agent through the uvm_config_db. + // + // ARGUMENTS: + // uvmf_active_passive_t activity: + // This argument identifies the simulation level + // as either BLOCK, CHIP, SIMULATION, etc. + // + // AGENT_PATH: + // This argument identifies the path to this + // configurations agent. This configuration + // makes itself available to the agent specified + // by agent_path by placing itself into the + // uvm_config_db. + // + // INTERFACE_NAME: + // This argument identifies the string name of + // this configurations BFM's. This string + // name is used to retrieve the driver and + // monitor BFM from the uvm_config_db. + // + virtual function void initialize(uvmf_active_passive_t activity, + string agent_path, + string interface_name); + + super.initialize( activity, agent_path, interface_name); + // The covergroup is given the same name as the interface + fuse_ctrl_prim_axi_write_out_configuration_cg.set_inst_name(interface_name); + + // This configuration places itself into the uvm_config_db for the agent, identified by the agent_path variable, to retrieve. + uvm_config_db #( fuse_ctrl_prim_axi_write_out_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + )::set( null ,agent_path,UVMF_AGENT_CONFIG, this ); + + // This configuration also places itself in the config db using the same identifier used by the interface. This allows users to access + // configuration variables and the interface through the bfm api class rather than directly accessing the BFM. This is useful for + // accessingthe BFM when using Veloce + uvm_config_db #( fuse_ctrl_prim_axi_write_out_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + )::set( null ,UVMF_CONFIGURATIONS, interface_name, this ); + + fuse_ctrl_prim_axi_write_out_configuration_cg.set_inst_name($sformatf("fuse_ctrl_prim_axi_write_out_configuration_cg_%s",get_full_name())); + +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. + `uvm_info("CFG", + $psprintf("The agent at '%s' is using interface named %s has the following parameters: AW=%x DW=%x IW=%x UW=%x ", agent_path, interface_name, AW ,DW ,IW ,UW ), + UVM_DEBUG) + + // pragma uvmf custom initialize begin + // This controls whether or not the agent returns a transaction handle in the driver when calling + // item_done() back into the sequencer or not. If set to 1, a transaction is sent back which means + // the sequence on the other end must use the get_response() part of the driver/sequence API. If + // this doesn't occur, there will eventually be response_queue overflow errors during the test. + return_transaction_response = 1'b0; + + // pragma uvmf custom initialize end + + endfunction + + // **************************************************************************** + // TASK: wait_for_reset + // *[Required]* Blocks until reset is released. The wait_for_reset operation is performed + // by a task in the monitor bfm. + virtual task wait_for_reset(); + monitor_bfm.wait_for_reset(); + endtask + + // **************************************************************************** + // TASK: wait_for_num_clocks + // *[Required]* Blocks until specified number of clocks have elapsed. The wait_for_num_clocks + // operation is performed by a task in the monitor bfm. + virtual task wait_for_num_clocks(int clocks); + monitor_bfm.wait_for_num_clocks(clocks); + endtask + + // **************************************************************************** + // FUNCTION : convert2string() + // This function is used to convert variables in this class into a string for log messaging. + // + virtual function string convert2string (); + // pragma uvmf custom convert2string begin + return $sformatf(""); + // pragma uvmf custom convert2string end + endfunction + + // **************************************************************************** + // FUNCTION: get_sequencer + function uvm_sequencer #(fuse_ctrl_prim_axi_write_out_transaction#( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )) get_sequencer(); + return sequencer; + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_driver.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_driver.svh new file mode 100644 index 0000000..92352d6 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_driver.svh @@ -0,0 +1,135 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class passes transactions between the sequencer +// and the BFM driver interface. It accesses the driver BFM +// through the bfm handle. This driver +// passes transactions to the driver BFM through the access +// task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_write_out_driver #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvmf_driver_base #( + .CONFIG_T(fuse_ctrl_prim_axi_write_out_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) ), + .BFM_BIND_T(virtual fuse_ctrl_prim_axi_write_out_driver_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) ), + .REQ(fuse_ctrl_prim_axi_write_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) ), + .RSP(fuse_ctrl_prim_axi_write_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) )); + + `uvm_component_param_utils( fuse_ctrl_prim_axi_write_out_driver #( + AW, + DW, + IW, + UW + )) +//******************************************************************* +// Macros that define structs located in fuse_ctrl_prim_axi_write_out_macros.svh +//******************************************************************* +// Initiator macro used by fuse_ctrl_prim_axi_write_out_driver and fuse_ctrl_prim_axi_write_out_driver_bfm +// to communicate initiator driven data to fuse_ctrl_prim_axi_write_out_driver_bfm. +`fuse_ctrl_prim_axi_write_out_INITIATOR_STRUCT + fuse_ctrl_prim_axi_write_out_initiator_s fuse_ctrl_prim_axi_write_out_initiator_struct; +//******************************************************************* +// Responder macro used by fuse_ctrl_prim_axi_write_out_driver and fuse_ctrl_prim_axi_write_out_driver_bfm +// to communicate Responder driven data to fuse_ctrl_prim_axi_write_out_driver_bfm. +`fuse_ctrl_prim_axi_write_out_RESPONDER_STRUCT + fuse_ctrl_prim_axi_write_out_responder_s fuse_ctrl_prim_axi_write_out_responder_struct; + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent=null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the driver BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// driver BFM. This allows the driver BFM to call tasks and function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// **************************************************************************** +// This task is called by the run_phase in uvmf_driver_base. + virtual task access( inout REQ txn ); +// pragma uvmf custom access begin + if (configuration.initiator_responder==RESPONDER) begin + // Complete current transfer and wait for next transfer + bfm.respond_and_wait_for_next_transfer( + fuse_ctrl_prim_axi_write_out_initiator_struct, + txn.to_responder_struct() + ); + // Unpack information about initiated transfer received by this responder + txn.from_initiator_struct(fuse_ctrl_prim_axi_write_out_initiator_struct); + end else begin + // Initiate a transfer and get response + bfm.initiate_and_get_response( + txn.to_initiator_struct(), + fuse_ctrl_prim_axi_write_out_responder_struct + ); + // Unpack transfer response information received by this initiator + txn.from_responder_struct(fuse_ctrl_prim_axi_write_out_responder_struct); + end +// pragma uvmf custom access end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_driver_bfm.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_driver_bfm.sv new file mode 100644 index 0000000..1855a5b --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_driver_bfm.sv @@ -0,0 +1,339 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This interface performs the fuse_ctrl_prim_axi_write_out signal driving. It is +// accessed by the uvm fuse_ctrl_prim_axi_write_out driver through a virtual interface +// handle in the fuse_ctrl_prim_axi_write_out configuration. It drives the singals passed +// in through the port connection named bus of type fuse_ctrl_prim_axi_write_out_if. +// +// Input signals from the fuse_ctrl_prim_axi_write_out_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// This bfm drives signals with a _o suffix. These signals +// are driven onto signals within fuse_ctrl_prim_axi_write_out_if based on INITIATOR/RESPONDER and/or +// ARBITRATION/GRANT status. +// +// The output signal connections are as follows: +// signal_o -> bus.signal +// +// +// Interface functions and tasks used by UVM components: +// +// configure: +// This function gets configuration attributes from the +// UVM driver to set any required BFM configuration +// variables such as 'initiator_responder'. +// +// initiate_and_get_response: +// This task is used to perform signaling activity for initiating +// a protocol transfer. The task initiates the transfer, using +// input data from the initiator struct. Then the task captures +// response data, placing the data into the response struct. +// The response struct is returned to the driver class. +// +// respond_and_wait_for_next_transfer: +// This task is used to complete a current transfer as a responder +// and then wait for the initiator to start the next transfer. +// The task uses data in the responder struct to drive protocol +// signals to complete the transfer. The task then waits for +// the next transfer. Once the next transfer begins, data from +// the initiator is placed into the initiator struct and sent +// to the responder sequence for processing to determine +// what data to respond with. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_prim_axi_write_out_pkg_hdl::*; +`include "src/fuse_ctrl_prim_axi_write_out_macros.svh" + +interface fuse_ctrl_prim_axi_write_out_driver_bfm #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + (fuse_ctrl_prim_axi_write_out_if bus); + // The following pragma and additional ones in-lined further below are for running this BFM on Veloce + // pragma attribute fuse_ctrl_prim_axi_write_out_driver_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: AW=%x DW=%x IW=%x UW=%x ", AW,DW,IW,UW), + UVM_DEBUG) +end +`endif + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + tri clk_i_i; + tri rst_ni_i; + + // Signal list (all signals are capable of being inputs and outputs for the sake + // of supporting both INITIATOR and RESPONDER mode operation. Expectation is that + // directionality in the config file was from the point-of-view of the INITIATOR + + // INITIATOR mode input signals + tri awready_i; + reg awready_o = 'bz; + tri wready_i; + reg wready_o = 'bz; + tri [$bits(axi_pkg::axi_burst_e)-1:0] bresp_i; + reg [$bits(axi_pkg::axi_burst_e)-1:0] bresp_o = 'bz; + tri bid_i; + reg bid_o = 'bz; + tri bvalid_i; + reg bvalid_o = 'bz; + + // INITIATOR mode output signals + + // Bi-directional signals + + + assign clk_i_i = bus.clk_i; + assign rst_ni_i = bus.rst_ni; + + // These are signals marked as 'input' by the config file, but the signals will be + // driven by this BFM if put into RESPONDER mode (flipping all signal directions around) + assign awready_i = bus.awready; + assign bus.awready = (initiator_responder == RESPONDER) ? awready_o : 'bz; + assign wready_i = bus.wready; + assign bus.wready = (initiator_responder == RESPONDER) ? wready_o : 'bz; + assign bresp_i = bus.bresp; + assign bus.bresp = (initiator_responder == RESPONDER) ? bresp_o : 'bz; + assign bid_i = bus.bid; + assign bus.bid = (initiator_responder == RESPONDER) ? bid_o : 'bz; + assign bvalid_i = bus.bvalid; + assign bus.bvalid = (initiator_responder == RESPONDER) ? bvalid_o : 'bz; + + + // These are signals marked as 'output' by the config file, but the outputs will + // not be driven by this BFM unless placed in INITIATOR mode. + + // Proxy handle to UVM driver + fuse_ctrl_prim_axi_write_out_pkg::fuse_ctrl_prim_axi_write_out_driver #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) proxy; + // pragma tbx oneway proxy.my_function_name_in_uvm_driver + + // **************************************************************************** + // **************************************************************************** + // Macros that define structs located in fuse_ctrl_prim_axi_write_out_macros.svh + // **************************************************************************** + // Struct for passing configuration data from fuse_ctrl_prim_axi_write_out_driver to this BFM + // **************************************************************************** + `fuse_ctrl_prim_axi_write_out_CONFIGURATION_STRUCT + // **************************************************************************** + // Structs for INITIATOR and RESPONDER data flow + //******************************************************************* + // Initiator macro used by fuse_ctrl_prim_axi_write_out_driver and fuse_ctrl_prim_axi_write_out_driver_bfm + // to communicate initiator driven data to fuse_ctrl_prim_axi_write_out_driver_bfm. + `fuse_ctrl_prim_axi_write_out_INITIATOR_STRUCT + fuse_ctrl_prim_axi_write_out_initiator_s initiator_struct; + // Responder macro used by fuse_ctrl_prim_axi_write_out_driver and fuse_ctrl_prim_axi_write_out_driver_bfm + // to communicate Responder driven data to fuse_ctrl_prim_axi_write_out_driver_bfm. + `fuse_ctrl_prim_axi_write_out_RESPONDER_STRUCT + fuse_ctrl_prim_axi_write_out_responder_s responder_struct; + + // **************************************************************************** +// pragma uvmf custom reset_condition_and_response begin + // Always block used to return signals to reset value upon assertion of reset + always @( negedge rst_ni_i ) + begin + // RESPONDER mode output signals + awready_o <= 'bz; + wready_o <= 'bz; + bresp_o <= 'bz; + bid_o <= 'bz; + bvalid_o <= 'bz; + // INITIATOR mode output signals + // Bi-directional signals + + end +// pragma uvmf custom reset_condition_and_response end + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the driver BFM. It is called by the driver within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the driver BFM needs to be aware of the new configuration + // variables. + // + + function void configure(fuse_ctrl_prim_axi_write_out_configuration_s fuse_ctrl_prim_axi_write_out_configuration_arg); // pragma tbx xtf + initiator_responder = fuse_ctrl_prim_axi_write_out_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + +// pragma uvmf custom initiate_and_get_response begin +// **************************************************************************** +// UVMF_CHANGE_ME +// This task is used by an initator. The task first initiates a transfer then +// waits for the responder to complete the transfer. + task initiate_and_get_response( + // This argument passes transaction variables used by an initiator + // to perform the initial part of a protocol transfer. The values + // come from a sequence item created in a sequence. + input fuse_ctrl_prim_axi_write_out_initiator_s fuse_ctrl_prim_axi_write_out_initiator_struct, + // This argument is used to send data received from the responder + // back to the sequence item. The sequence item is returned to the sequence. + output fuse_ctrl_prim_axi_write_out_responder_s fuse_ctrl_prim_axi_write_out_responder_struct + );// pragma tbx xtf + // + // Members within the fuse_ctrl_prim_axi_write_out_initiator_struct: + // logic prim_awready ; + // logic prim_wready ; + // axi_pkg::axi_burst_e prim_bresp ; + // logic prim_bid ; + // logic prim_bvalid ; + // Members within the fuse_ctrl_prim_axi_write_out_responder_struct: + // logic prim_awready ; + // logic prim_wready ; + // axi_pkg::axi_burst_e prim_bresp ; + // logic prim_bid ; + // logic prim_bvalid ; + initiator_struct = fuse_ctrl_prim_axi_write_out_initiator_struct; + // + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clk_i_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available initiator input and inout signals listed. + // Initiator input signals + // fuse_ctrl_prim_axi_write_out_responder_struct.xyz = awready_i; // + // fuse_ctrl_prim_axi_write_out_responder_struct.xyz = wready_i; // + // fuse_ctrl_prim_axi_write_out_responder_struct.xyz = bresp_i; // [$bits(axi_pkg::axi_burst_e)-1:0] + // fuse_ctrl_prim_axi_write_out_responder_struct.xyz = bid_i; // + // fuse_ctrl_prim_axi_write_out_responder_struct.xyz = bvalid_i; // + // Initiator inout signals + // How to assign a signal from an initiator struct member named xyz. + // All available initiator output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Initiator output signals + // Initiator inout signals + // Initiate a transfer using the data received. + @(posedge clk_i_i); + @(posedge clk_i_i); + // Wait for the responder to complete the transfer then place the responder data into + // fuse_ctrl_prim_axi_write_out_responder_struct. + @(posedge clk_i_i); + @(posedge clk_i_i); + responder_struct = fuse_ctrl_prim_axi_write_out_responder_struct; + endtask +// pragma uvmf custom initiate_and_get_response end + +// pragma uvmf custom respond_and_wait_for_next_transfer begin +// **************************************************************************** +// The first_transfer variable is used to prevent completing a transfer in the +// first call to this task. For the first call to this task, there is not +// current transfer to complete. +bit first_transfer=1; + +// UVMF_CHANGE_ME +// This task is used by a responder. The task first completes the current +// transfer in progress then waits for the initiator to start the next transfer. + task respond_and_wait_for_next_transfer( + // This argument is used to send data received from the initiator + // back to the sequence item. The sequence determines how to respond. + output fuse_ctrl_prim_axi_write_out_initiator_s fuse_ctrl_prim_axi_write_out_initiator_struct, + // This argument passes transaction variables used by a responder + // to complete a protocol transfer. The values come from a sequence item. + input fuse_ctrl_prim_axi_write_out_responder_s fuse_ctrl_prim_axi_write_out_responder_struct + );// pragma tbx xtf + // Variables within the fuse_ctrl_prim_axi_write_out_initiator_struct: + // logic prim_awready ; + // logic prim_wready ; + // axi_pkg::axi_burst_e prim_bresp ; + // logic prim_bid ; + // logic prim_bvalid ; + // Variables within the fuse_ctrl_prim_axi_write_out_responder_struct: + // logic prim_awready ; + // logic prim_wready ; + // axi_pkg::axi_burst_e prim_bresp ; + // logic prim_bid ; + // logic prim_bvalid ; + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clk_i_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available responder input and inout signals listed. + // Responder input signals + // Responder inout signals + // How to assign a signal, named xyz, from an initiator struct member. + // All available responder output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Responder output signals + // awready_o <= fuse_ctrl_prim_axi_write_out_initiator_struct.xyz; // + // wready_o <= fuse_ctrl_prim_axi_write_out_initiator_struct.xyz; // + // bresp_o <= fuse_ctrl_prim_axi_write_out_initiator_struct.xyz; // [$bits(axi_pkg::axi_burst_e)-1:0] + // bid_o <= fuse_ctrl_prim_axi_write_out_initiator_struct.xyz; // + // bvalid_o <= fuse_ctrl_prim_axi_write_out_initiator_struct.xyz; // + // Responder inout signals + + @(posedge clk_i_i); + if (!first_transfer) begin + // Perform transfer response here. + // Reply using data recieved in the fuse_ctrl_prim_axi_write_out_responder_struct. + @(posedge clk_i_i); + // Reply using data recieved in the transaction handle. + @(posedge clk_i_i); + end + // Wait for next transfer then gather info from intiator about the transfer. + // Place the data into the fuse_ctrl_prim_axi_write_out_initiator_struct. + @(posedge clk_i_i); + @(posedge clk_i_i); + first_transfer = 0; + endtask +// pragma uvmf custom respond_and_wait_for_next_transfer end + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_if.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_if.sv new file mode 100644 index 0000000..096078a --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_if.sv @@ -0,0 +1,103 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface contains the fuse_ctrl_prim_axi_write_out interface signals. +// It is instantiated once per fuse_ctrl_prim_axi_write_out bus. Bus Functional Models, +// BFM's named fuse_ctrl_prim_axi_write_out_driver_bfm, are used to drive signals on the bus. +// BFM's named fuse_ctrl_prim_axi_write_out_monitor_bfm are used to monitor signals on the +// bus. This interface signal bundle is passed in the port list of +// the BFM in order to give the BFM access to the signals in this +// interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// This template can be used to connect a DUT to these signals +// +// .dut_signal_port(fuse_ctrl_prim_axi_write_out_bus.awready), // Agent input +// .dut_signal_port(fuse_ctrl_prim_axi_write_out_bus.wready), // Agent input +// .dut_signal_port(fuse_ctrl_prim_axi_write_out_bus.bresp), // Agent input +// .dut_signal_port(fuse_ctrl_prim_axi_write_out_bus.bid), // Agent input +// .dut_signal_port(fuse_ctrl_prim_axi_write_out_bus.bvalid), // Agent input + +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_prim_axi_write_out_pkg_hdl::*; + +interface fuse_ctrl_prim_axi_write_out_if #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + + ( + input tri clk_i, + input tri rst_ni, + inout tri awready, + inout tri wready, + inout tri [$bits(axi_pkg::axi_burst_e)-1:0] bresp, + inout tri bid, + inout tri bvalid + ); + +modport monitor_port + ( + input clk_i, + input rst_ni, + input awready, + input wready, + input bresp, + input bid, + input bvalid + ); + +modport initiator_port + ( + input clk_i, + input rst_ni, + input awready, + input wready, + input bresp, + input bid, + input bvalid + ); + +modport responder_port + ( + input clk_i, + input rst_ni, + output awready, + output wready, + output bresp, + output bid, + output bvalid + ); + + +// pragma uvmf custom interface_item_additional begin +// pragma uvmf custom interface_item_additional end + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_infact_coverage_strategy.csv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_infact_coverage_strategy.csv new file mode 100644 index 0000000..1c218e1 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_infact_coverage_strategy.csv @@ -0,0 +1,6 @@ +Global +auto_bin_max, 64 + +Name,Type,Include +rand_fields,coverpoint,=rand *.** + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_macros.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_macros.svh new file mode 100644 index 0000000..28bfd68 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_macros.svh @@ -0,0 +1,171 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains macros used with the fuse_ctrl_prim_axi_write_out package. +// These macros include packed struct definitions. These structs are +// used to pass data between classes, hvl, and BFM's, hdl. Use of +// structs are more efficient and simpler to modify. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_struct +// and from_struct methods defined in the macros below that are used in +// the fuse_ctrl_prim_axi_write_out_configuration class. +// + `define fuse_ctrl_prim_axi_write_out_CONFIGURATION_STRUCT \ +typedef struct packed { \ + uvmf_active_passive_t active_passive; \ + uvmf_initiator_responder_t initiator_responder; \ + } fuse_ctrl_prim_axi_write_out_configuration_s; + + `define fuse_ctrl_prim_axi_write_out_CONFIGURATION_TO_STRUCT_FUNCTION \ + virtual function fuse_ctrl_prim_axi_write_out_configuration_s to_struct();\ + fuse_ctrl_prim_axi_write_out_configuration_struct = \ + {\ + this.active_passive,\ + this.initiator_responder\ + };\ + return ( fuse_ctrl_prim_axi_write_out_configuration_struct );\ + endfunction + + `define fuse_ctrl_prim_axi_write_out_CONFIGURATION_FROM_STRUCT_FUNCTION \ + virtual function void from_struct(fuse_ctrl_prim_axi_write_out_configuration_s fuse_ctrl_prim_axi_write_out_configuration_struct);\ + {\ + this.active_passive,\ + this.initiator_responder \ + } = fuse_ctrl_prim_axi_write_out_configuration_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_monitor_struct +// and from_monitor_struct methods of the fuse_ctrl_prim_axi_write_out_transaction class. +// + `define fuse_ctrl_prim_axi_write_out_MONITOR_STRUCT typedef struct packed { \ + logic prim_awready ; \ + logic prim_wready ; \ + axi_pkg::axi_burst_e prim_bresp ; \ + logic prim_bid ; \ + logic prim_bvalid ; \ + } fuse_ctrl_prim_axi_write_out_monitor_s; + + `define fuse_ctrl_prim_axi_write_out_TO_MONITOR_STRUCT_FUNCTION \ + virtual function fuse_ctrl_prim_axi_write_out_monitor_s to_monitor_struct();\ + fuse_ctrl_prim_axi_write_out_monitor_struct = \ + { \ + this.prim_awready , \ + this.prim_wready , \ + this.prim_bresp , \ + this.prim_bid , \ + this.prim_bvalid \ + };\ + return ( fuse_ctrl_prim_axi_write_out_monitor_struct);\ + endfunction\ + + `define fuse_ctrl_prim_axi_write_out_FROM_MONITOR_STRUCT_FUNCTION \ + virtual function void from_monitor_struct(fuse_ctrl_prim_axi_write_out_monitor_s fuse_ctrl_prim_axi_write_out_monitor_struct);\ + {\ + this.prim_awready , \ + this.prim_wready , \ + this.prim_bresp , \ + this.prim_bid , \ + this.prim_bvalid \ + } = fuse_ctrl_prim_axi_write_out_monitor_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_initiator_struct +// and from_initiator_struct methods of the fuse_ctrl_prim_axi_write_out_transaction class. +// Also update the comments in the driver BFM. +// + `define fuse_ctrl_prim_axi_write_out_INITIATOR_STRUCT typedef struct packed { \ + logic prim_awready ; \ + logic prim_wready ; \ + axi_pkg::axi_burst_e prim_bresp ; \ + logic prim_bid ; \ + logic prim_bvalid ; \ + } fuse_ctrl_prim_axi_write_out_initiator_s; + + `define fuse_ctrl_prim_axi_write_out_TO_INITIATOR_STRUCT_FUNCTION \ + virtual function fuse_ctrl_prim_axi_write_out_initiator_s to_initiator_struct();\ + fuse_ctrl_prim_axi_write_out_initiator_struct = \ + {\ + this.prim_awready , \ + this.prim_wready , \ + this.prim_bresp , \ + this.prim_bid , \ + this.prim_bvalid \ + };\ + return ( fuse_ctrl_prim_axi_write_out_initiator_struct);\ + endfunction + + `define fuse_ctrl_prim_axi_write_out_FROM_INITIATOR_STRUCT_FUNCTION \ + virtual function void from_initiator_struct(fuse_ctrl_prim_axi_write_out_initiator_s fuse_ctrl_prim_axi_write_out_initiator_struct);\ + {\ + this.prim_awready , \ + this.prim_wready , \ + this.prim_bresp , \ + this.prim_bid , \ + this.prim_bvalid \ + } = fuse_ctrl_prim_axi_write_out_initiator_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_responder_struct +// and from_responder_struct methods of the fuse_ctrl_prim_axi_write_out_transaction class. +// Also update the comments in the driver BFM. +// + `define fuse_ctrl_prim_axi_write_out_RESPONDER_STRUCT typedef struct packed { \ + logic prim_awready ; \ + logic prim_wready ; \ + axi_pkg::axi_burst_e prim_bresp ; \ + logic prim_bid ; \ + logic prim_bvalid ; \ + } fuse_ctrl_prim_axi_write_out_responder_s; + + `define fuse_ctrl_prim_axi_write_out_TO_RESPONDER_STRUCT_FUNCTION \ + virtual function fuse_ctrl_prim_axi_write_out_responder_s to_responder_struct();\ + fuse_ctrl_prim_axi_write_out_responder_struct = \ + {\ + this.prim_awready , \ + this.prim_wready , \ + this.prim_bresp , \ + this.prim_bid , \ + this.prim_bvalid \ + };\ + return ( fuse_ctrl_prim_axi_write_out_responder_struct);\ + endfunction + + `define fuse_ctrl_prim_axi_write_out_FROM_RESPONDER_STRUCT_FUNCTION \ + virtual function void from_responder_struct(fuse_ctrl_prim_axi_write_out_responder_s fuse_ctrl_prim_axi_write_out_responder_struct);\ + {\ + this.prim_awready , \ + this.prim_wready , \ + this.prim_bresp , \ + this.prim_bid , \ + this.prim_bvalid \ + } = fuse_ctrl_prim_axi_write_out_responder_struct;\ + endfunction +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_monitor.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_monitor.svh new file mode 100644 index 0000000..0f355e2 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_monitor.svh @@ -0,0 +1,126 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class receives fuse_ctrl_prim_axi_write_out transactions observed by the +// fuse_ctrl_prim_axi_write_out monitor BFM and broadcasts them through the analysis port +// on the agent. It accesses the monitor BFM through the monitor +// task. This UVM component captures transactions +// for viewing in the waveform viewer if the +// enable_transaction_viewing flag is set in the configuration. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_write_out_monitor #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvmf_monitor_base #( + .CONFIG_T(fuse_ctrl_prim_axi_write_out_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .BFM_BIND_T(virtual fuse_ctrl_prim_axi_write_out_monitor_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .TRANS_T(fuse_ctrl_prim_axi_write_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ))); + + `uvm_component_param_utils( fuse_ctrl_prim_axi_write_out_monitor #( + AW, + DW, + IW, + UW + )) + +// Structure used to pass data from monitor BFM to monitor class in agent. +// Use to_monitor_struct function to pack transaction variables into structure. +// Use from_monitor_struct function to unpack transaction variables from structure. +`fuse_ctrl_prim_axi_write_out_MONITOR_STRUCT + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the monitor BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// monitor BFM. This allows the monitor BFM to call the notify_transaction +// function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// *************************************************************************** + virtual task run_phase(uvm_phase phase); + // Start monitor BFM thread and don't call super.run() in order to + // override the default monitor proxy 'pull' behavior with the more + // emulation-friendly BFM 'push' approach using the notify_transaction + // function below + bfm.start_monitoring(); + endtask + +// ************************************************************************** + +// This function is called by the monitor BFM. It receives data observed by the +// monitor BFM. Data is passed using the fuse_ctrl_prim_axi_write_out_monitor_struct. + virtual function void notify_transaction(input fuse_ctrl_prim_axi_write_out_monitor_s fuse_ctrl_prim_axi_write_out_monitor_struct); + + + trans = new("trans"); + trans.from_monitor_struct(fuse_ctrl_prim_axi_write_out_monitor_struct); + trans.start_time = time_stamp; + trans.end_time = $time; + time_stamp = trans.end_time; + + analyze(trans); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_monitor_bfm.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_monitor_bfm.sv new file mode 100644 index 0000000..8241af8 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_monitor_bfm.sv @@ -0,0 +1,214 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface performs the fuse_ctrl_prim_axi_write_out signal monitoring. +// It is accessed by the uvm fuse_ctrl_prim_axi_write_out monitor through a virtual +// interface handle in the fuse_ctrl_prim_axi_write_out configuration. It monitors the +// signals passed in through the port connection named bus of +// type fuse_ctrl_prim_axi_write_out_if. +// +// Input signals from the fuse_ctrl_prim_axi_write_out_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// Interface functions and tasks used by UVM components: +// monitor(inout TRANS_T txn); +// This task receives the transaction, txn, from the +// UVM monitor and then populates variables in txn +// from values observed on bus activity. This task +// blocks until an operation on the fuse_ctrl_prim_axi_write_out bus is complete. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_prim_axi_write_out_pkg_hdl::*; +`include "src/fuse_ctrl_prim_axi_write_out_macros.svh" + + +interface fuse_ctrl_prim_axi_write_out_monitor_bfm #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + ( fuse_ctrl_prim_axi_write_out_if bus ); + // The pragma below and additional ones in-lined further down are for running this BFM on Veloce + // pragma attribute fuse_ctrl_prim_axi_write_out_monitor_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: AW=%x DW=%x IW=%x UW=%x ", AW,DW,IW,UW), + UVM_DEBUG) +end +`endif + + + // Structure used to pass transaction data from monitor BFM to monitor class in agent. +`fuse_ctrl_prim_axi_write_out_MONITOR_STRUCT + fuse_ctrl_prim_axi_write_out_monitor_s fuse_ctrl_prim_axi_write_out_monitor_struct; + + // Structure used to pass configuration data from monitor class to monitor BFM. + `fuse_ctrl_prim_axi_write_out_CONFIGURATION_STRUCT + + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + tri clk_i_i; + tri rst_ni_i; + tri awready_i; + tri wready_i; + tri [$bits(axi_pkg::axi_burst_e)-1:0] bresp_i; + tri bid_i; + tri bvalid_i; + assign clk_i_i = bus.clk_i; + assign rst_ni_i = bus.rst_ni; + assign awready_i = bus.awready; + assign wready_i = bus.wready; + assign bresp_i = bus.bresp; + assign bid_i = bus.bid; + assign bvalid_i = bus.bvalid; + + // Proxy handle to UVM monitor + fuse_ctrl_prim_axi_write_out_pkg::fuse_ctrl_prim_axi_write_out_monitor #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) proxy; + // pragma tbx oneway proxy.notify_transaction + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + task wait_for_reset();// pragma tbx xtf + @(posedge clk_i_i) ; + do_wait_for_reset(); + endtask + + // **************************************************************************** + task do_wait_for_reset(); + // pragma uvmf custom reset_condition begin + wait ( rst_ni_i === 1 ) ; + @(posedge clk_i_i) ; + // pragma uvmf custom reset_condition end + endtask + + //****************************************************************** + + task wait_for_num_clocks(input int unsigned count); // pragma tbx xtf + @(posedge clk_i_i); + + repeat (count-1) @(posedge clk_i_i); + endtask + + //****************************************************************** + event go; + function void start_monitoring();// pragma tbx xtf + -> go; + endfunction + + // **************************************************************************** + initial begin + @go; + forever begin + @(posedge clk_i_i); + do_monitor( fuse_ctrl_prim_axi_write_out_monitor_struct ); + + + proxy.notify_transaction( fuse_ctrl_prim_axi_write_out_monitor_struct ); + + end + end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the monitor BFM. It is called by the monitor within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the monitor BFM needs to be aware of the new configuration + // variables. + // + function void configure(fuse_ctrl_prim_axi_write_out_configuration_s fuse_ctrl_prim_axi_write_out_configuration_arg); // pragma tbx xtf + initiator_responder = fuse_ctrl_prim_axi_write_out_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + + + // **************************************************************************** + + task do_monitor(output fuse_ctrl_prim_axi_write_out_monitor_s fuse_ctrl_prim_axi_write_out_monitor_struct); + // + // Available struct members: + // // fuse_ctrl_prim_axi_write_out_monitor_struct.prim_awready + // // fuse_ctrl_prim_axi_write_out_monitor_struct.prim_wready + // // fuse_ctrl_prim_axi_write_out_monitor_struct.prim_bresp + // // fuse_ctrl_prim_axi_write_out_monitor_struct.prim_bid + // // fuse_ctrl_prim_axi_write_out_monitor_struct.prim_bvalid + // // + // Reference code; + // How to wait for signal value + // while (control_signal === 1'b1) @(posedge clk_i_i); + // + // How to assign a struct member, named xyz, from a signal. + // All available input signals listed. + // fuse_ctrl_prim_axi_write_out_monitor_struct.xyz = awready_i; // + // fuse_ctrl_prim_axi_write_out_monitor_struct.xyz = wready_i; // + // fuse_ctrl_prim_axi_write_out_monitor_struct.xyz = bresp_i; // [$bits(axi_pkg::axi_burst_e)-1:0] + // fuse_ctrl_prim_axi_write_out_monitor_struct.xyz = bid_i; // + // fuse_ctrl_prim_axi_write_out_monitor_struct.xyz = bvalid_i; // + // pragma uvmf custom do_monitor begin + // UVMF_CHANGE_ME : Implement protocol monitoring. The commented reference code + // below are examples of how to capture signal values and assign them to + // structure members. All available input signals are listed. The 'while' + // code example shows how to wait for a synchronous flow control signal. This + // task should return when a complete transfer has been observed. Once this task is + // exited with captured values, it is then called again to wait for and observe + // the next transfer. One clock cycle is consumed between calls to do_monitor. + @(posedge clk_i_i); + @(posedge clk_i_i); + @(posedge clk_i_i); + @(posedge clk_i_i); + // pragma uvmf custom do_monitor end + endtask + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_random_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_random_sequence.svh new file mode 100644 index 0000000..cfaf058 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_random_sequence.svh @@ -0,0 +1,87 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This sequences randomizes the fuse_ctrl_prim_axi_write_out transaction and sends it +// to the UVM driver. +// +// This sequence constructs and randomizes a fuse_ctrl_prim_axi_write_out_transaction. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_write_out_random_sequence #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends fuse_ctrl_prim_axi_write_out_sequence_base #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ); + + `uvm_object_param_utils( fuse_ctrl_prim_axi_write_out_random_sequence #( + AW, + DW, + IW, + UW + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //***************************************************************** + function new(string name = ""); + super.new(name); + endfunction: new + + // **************************************************************************** + // TASK : body() + // This task is automatically executed when this sequence is started using the + // start(sequencerHandle) task. + // + task body(); + + // Construct the transaction + req=fuse_ctrl_prim_axi_write_out_transaction#( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )::type_id::create("req"); + start_item(req); + // Randomize the transaction + if(!req.randomize()) `uvm_fatal("SEQ", "fuse_ctrl_prim_axi_write_out_random_sequence::body()-fuse_ctrl_prim_axi_write_out_transaction randomization failed") + // Send the transaction to the fuse_ctrl_prim_axi_write_out_driver_bfm via the sequencer and fuse_ctrl_prim_axi_write_out_driver. + finish_item(req); + `uvm_info("SEQ", {"Response:",req.convert2string()},UVM_MEDIUM) + + endtask + +endclass: fuse_ctrl_prim_axi_write_out_random_sequence + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_responder_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_responder_sequence.svh new file mode 100644 index 0000000..ac54773 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_responder_sequence.svh @@ -0,0 +1,83 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class can be used to provide stimulus when an interface +// has been configured to run in a responder mode. It +// will never finish by default, always going back to the driver +// and driver BFM for the next transaction with which to respond. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_write_out_responder_sequence #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends fuse_ctrl_prim_axi_write_out_sequence_base #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ); + + `uvm_object_param_utils( fuse_ctrl_prim_axi_write_out_responder_sequence #( + AW, + DW, + IW, + UW + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "fuse_ctrl_prim_axi_write_out_responder_sequence"); + super.new(name); + endfunction + + task body(); + req=fuse_ctrl_prim_axi_write_out_transaction#( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )::type_id::create("req"); + forever begin + start_item(req); + finish_item(req); + // pragma uvmf custom body begin + // UVMF_CHANGE_ME : Do something here with the resulting req item. The + // finish_item() call above will block until the req transaction is ready + // to be handled by the responder sequence. + // If this was an item that required a response, the expectation is + // that the response should be populated within this transaction now. + `uvm_info("SEQ",$sformatf("Processed txn: %s",req.convert2string()),UVM_HIGH) + // pragma uvmf custom body end + end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_sequence_base.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_sequence_base.svh new file mode 100644 index 0000000..2941e54 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_sequence_base.svh @@ -0,0 +1,140 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the class used as the base class for all sequences +// for this interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_write_out_sequence_base #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvmf_sequence_base #( + .REQ(fuse_ctrl_prim_axi_write_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .RSP(fuse_ctrl_prim_axi_write_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ))); + + `uvm_object_param_utils( fuse_ctrl_prim_axi_write_out_sequence_base #( + AW, + DW, + IW, + UW + )) + + // variables + typedef fuse_ctrl_prim_axi_write_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) fuse_ctrl_prim_axi_write_out_transaction_req_t; + fuse_ctrl_prim_axi_write_out_transaction_req_t req; + typedef fuse_ctrl_prim_axi_write_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) fuse_ctrl_prim_axi_write_out_transaction_rsp_t; + fuse_ctrl_prim_axi_write_out_transaction_rsp_t rsp; + + // Event for identifying when a response was received from the sequencer + event new_rsp; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // TASK : get_responses() + // This task recursively gets sequence item responses from the sequencer. + // + virtual task get_responses(); + fork + begin + // Block until new rsp available + get_response(rsp); + // New rsp received. Indicate to sequence using event. + ->new_rsp; + // Display the received response transaction + `uvm_info("SEQ", {"New response transaction:",rsp.convert2string()}, UVM_MEDIUM) + end + join_none + endtask + + // **************************************************************************** + // TASK : pre_body() + // This task is called automatically when start is called with call_pre_post set to 1 (default). + // By calling get_responses() within pre_body() any derived sequences are automatically + // processing response transactions. Only un-comment this call to get_responses() if you + // have configured the interface driver to utilize the response transaction path by setting + // the configuration variable "return_transaction_response" to 1. Otherwise it is possible + // to impact runtime performance and memory utilization. + // + virtual task pre_body(); + // pragma uvmf custom pre_body begin +// get_responses(); + // pragma uvmf custom pre_body end + endtask + + // **************************************************************************** + // TASK : body() + // This task is called automatically when start is called. This sequence sends + // a req sequence item to the sequencer identified as an argument in the call + // to start. + // + virtual task body(); + // pragma uvmf custom body begin + start_item(req); + finish_item(req); + // pragma uvmf custom body end + endtask + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name =""); + super.new( name ); + // pragma uvmf custom new begin + req = fuse_ctrl_prim_axi_write_out_transaction_req_t::type_id::create("req"); + rsp = fuse_ctrl_prim_axi_write_out_transaction_rsp_t::type_id::create("rsp"); + // pragma uvmf custom new end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_transaction.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_transaction.svh new file mode 100644 index 0000000..f3606b9 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_transaction.svh @@ -0,0 +1,232 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class defines the variables required for an fuse_ctrl_prim_axi_write_out +// transaction. Class variables to be displayed in waveform transaction +// viewing are added to the transaction viewing stream in the add_to_wave +// function. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_write_out_transaction #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvmf_transaction_base; + + `uvm_object_param_utils( fuse_ctrl_prim_axi_write_out_transaction #( + AW, + DW, + IW, + UW + )) + + logic prim_awready ; + logic prim_wready ; + axi_pkg::axi_burst_e prim_bresp ; + logic prim_bid ; + logic prim_bvalid ; + + //Constraints for the transaction variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //******************************************************************* + //******************************************************************* + // Macros that define structs and associated functions are + // located in fuse_ctrl_prim_axi_write_out_macros.svh + + //******************************************************************* + // Monitor macro used by fuse_ctrl_prim_axi_write_out_monitor and fuse_ctrl_prim_axi_write_out_monitor_bfm + // This struct is defined in fuse_ctrl_prim_axi_write_out_macros.svh + `fuse_ctrl_prim_axi_write_out_MONITOR_STRUCT + fuse_ctrl_prim_axi_write_out_monitor_s fuse_ctrl_prim_axi_write_out_monitor_struct; + //******************************************************************* + // FUNCTION: to_monitor_struct() + // This function packs transaction variables into a fuse_ctrl_prim_axi_write_out_monitor_s + // structure. The function returns the handle to the fuse_ctrl_prim_axi_write_out_monitor_struct. + // This function is defined in fuse_ctrl_prim_axi_write_out_macros.svh + `fuse_ctrl_prim_axi_write_out_TO_MONITOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_monitor_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_prim_axi_write_out_macros.svh + `fuse_ctrl_prim_axi_write_out_FROM_MONITOR_STRUCT_FUNCTION + + //******************************************************************* + // Initiator macro used by fuse_ctrl_prim_axi_write_out_driver and fuse_ctrl_prim_axi_write_out_driver_bfm + // to communicate initiator driven data to fuse_ctrl_prim_axi_write_out_driver_bfm. + // This struct is defined in fuse_ctrl_prim_axi_write_out_macros.svh + `fuse_ctrl_prim_axi_write_out_INITIATOR_STRUCT + fuse_ctrl_prim_axi_write_out_initiator_s fuse_ctrl_prim_axi_write_out_initiator_struct; + //******************************************************************* + // FUNCTION: to_initiator_struct() + // This function packs transaction variables into a fuse_ctrl_prim_axi_write_out_initiator_s + // structure. The function returns the handle to the fuse_ctrl_prim_axi_write_out_initiator_struct. + // This function is defined in fuse_ctrl_prim_axi_write_out_macros.svh + `fuse_ctrl_prim_axi_write_out_TO_INITIATOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_initiator_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_prim_axi_write_out_macros.svh + `fuse_ctrl_prim_axi_write_out_FROM_INITIATOR_STRUCT_FUNCTION + + //******************************************************************* + // Responder macro used by fuse_ctrl_prim_axi_write_out_driver and fuse_ctrl_prim_axi_write_out_driver_bfm + // to communicate Responder driven data to fuse_ctrl_prim_axi_write_out_driver_bfm. + // This struct is defined in fuse_ctrl_prim_axi_write_out_macros.svh + `fuse_ctrl_prim_axi_write_out_RESPONDER_STRUCT + fuse_ctrl_prim_axi_write_out_responder_s fuse_ctrl_prim_axi_write_out_responder_struct; + //******************************************************************* + // FUNCTION: to_responder_struct() + // This function packs transaction variables into a fuse_ctrl_prim_axi_write_out_responder_s + // structure. The function returns the handle to the fuse_ctrl_prim_axi_write_out_responder_struct. + // This function is defined in fuse_ctrl_prim_axi_write_out_macros.svh + `fuse_ctrl_prim_axi_write_out_TO_RESPONDER_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_responder_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_prim_axi_write_out_macros.svh + `fuse_ctrl_prim_axi_write_out_FROM_RESPONDER_STRUCT_FUNCTION + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + endfunction + + // **************************************************************************** + // FUNCTION: convert2string() + // This function converts all variables in this class to a single string for + // logfile reporting. + // + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + // UVMF_CHANGE_ME : Customize format if desired. + return $sformatf("prim_awready:0x%x prim_wready:0x%x prim_bresp:0x%x prim_bid:0x%x prim_bvalid:0x%x ",prim_awready,prim_wready,prim_bresp,prim_bid,prim_bvalid); + // pragma uvmf custom convert2string end + endfunction + + //******************************************************************* + // FUNCTION: do_print() + // This function is automatically called when the .print() function + // is called on this class. + // + virtual function void do_print(uvm_printer printer); + // pragma uvmf custom do_print begin + // UVMF_CHANGE_ME : Current contents of do_print allows for the use of UVM 1.1d, 1.2 or P1800.2. + // Update based on your own printing preference according to your preferred UVM version + $display(convert2string()); + // pragma uvmf custom do_print end + endfunction + + //******************************************************************* + // FUNCTION: do_compare() + // This function is automatically called when the .compare() function + // is called on this class. + // + virtual function bit do_compare (uvm_object rhs, uvm_comparer comparer); + fuse_ctrl_prim_axi_write_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) RHS; + if (!$cast(RHS,rhs)) return 0; + // pragma uvmf custom do_compare begin + // UVMF_CHANGE_ME : Eliminate comparison of variables not to be used for compare + return (super.do_compare(rhs,comparer) + &&(this.prim_awready == RHS.prim_awready) + &&(this.prim_wready == RHS.prim_wready) + &&(this.prim_bresp == RHS.prim_bresp) + &&(this.prim_bid == RHS.prim_bid) + &&(this.prim_bvalid == RHS.prim_bvalid) + ); + // pragma uvmf custom do_compare end + endfunction + + //******************************************************************* + // FUNCTION: do_copy() + // This function is automatically called when the .copy() function + // is called on this class. + // + virtual function void do_copy (uvm_object rhs); + fuse_ctrl_prim_axi_write_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) RHS; + assert($cast(RHS,rhs)); + // pragma uvmf custom do_copy begin + super.do_copy(rhs); + this.prim_awready = RHS.prim_awready; + this.prim_wready = RHS.prim_wready; + this.prim_bresp = RHS.prim_bresp; + this.prim_bid = RHS.prim_bid; + this.prim_bvalid = RHS.prim_bvalid; + // pragma uvmf custom do_copy end + endfunction + + // **************************************************************************** + // FUNCTION: add_to_wave() + // This function is used to display variables in this class in the waveform + // viewer. The start_time and end_time variables must be set before this + // function is called. If the start_time and end_time variables are not set + // the transaction will be hidden at 0ns on the waveform display. + // + virtual function void add_to_wave(int transaction_viewing_stream_h); + `ifdef QUESTA + if (transaction_view_h == 0) begin + transaction_view_h = $begin_transaction(transaction_viewing_stream_h,"fuse_ctrl_prim_axi_write_out_transaction",start_time); + end + super.add_to_wave(transaction_view_h); + // pragma uvmf custom add_to_wave begin + // UVMF_CHANGE_ME : Color can be applied to transaction entries based on content, example below + // case() + // 1 : $add_color(transaction_view_h,"red"); + // default : $add_color(transaction_view_h,"grey"); + // endcase + // UVMF_CHANGE_ME : Eliminate transaction variables not wanted in transaction viewing in the waveform viewer + $add_attribute(transaction_view_h,prim_awready,"prim_awready"); + $add_attribute(transaction_view_h,prim_wready,"prim_wready"); + $add_attribute(transaction_view_h,prim_bresp,"prim_bresp"); + $add_attribute(transaction_view_h,prim_bid,"prim_bid"); + $add_attribute(transaction_view_h,prim_bvalid,"prim_bvalid"); + // pragma uvmf custom add_to_wave end + $end_transaction(transaction_view_h,end_time); + $free_transaction(transaction_view_h); + `endif // QUESTA + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_transaction_coverage.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_transaction_coverage.svh new file mode 100644 index 0000000..437d3bc --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_transaction_coverage.svh @@ -0,0 +1,103 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class records fuse_ctrl_prim_axi_write_out transaction information using +// a covergroup named fuse_ctrl_prim_axi_write_out_transaction_cg. An instance of this +// coverage component is instantiated in the uvmf_parameterized_agent +// if the has_coverage flag is set. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_write_out_transaction_coverage #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvm_subscriber #(.T(fuse_ctrl_prim_axi_write_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ))); + + `uvm_component_param_utils( fuse_ctrl_prim_axi_write_out_transaction_coverage #( + AW, + DW, + IW, + UW + )) + + T coverage_trans; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + covergroup fuse_ctrl_prim_axi_write_out_transaction_cg; + // pragma uvmf custom covergroup begin + // UVMF_CHANGE_ME : Add coverage bins, crosses, exclusions, etc. according to coverage needs. + option.auto_bin_max=1024; + option.per_instance=1; + prim_awready: coverpoint coverage_trans.prim_awready; + prim_wready: coverpoint coverage_trans.prim_wready; + prim_bresp: coverpoint coverage_trans.prim_bresp; + prim_bid: coverpoint coverage_trans.prim_bid; + prim_bvalid: coverpoint coverage_trans.prim_bvalid; + // pragma uvmf custom covergroup end + endgroup + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new(string name="", uvm_component parent=null); + super.new(name,parent); + fuse_ctrl_prim_axi_write_out_transaction_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that transaction variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + endfunction + + // **************************************************************************** + // FUNCTION : build_phase() + // This function is the standard UVM build_phase. + // + function void build_phase(uvm_phase phase); + fuse_ctrl_prim_axi_write_out_transaction_cg.set_inst_name($sformatf("fuse_ctrl_prim_axi_write_out_transaction_cg_%s",get_full_name())); + endfunction + + // **************************************************************************** + // FUNCTION: write (T t) + // This function is automatically executed when a transaction arrives on the + // analysis_export. It copies values from the variables in the transaction + // to local variables used to collect functional coverage. + // + virtual function void write (T t); + `uvm_info("COV","Received transaction",UVM_HIGH); + coverage_trans = t; + fuse_ctrl_prim_axi_write_out_transaction_cg.sample(); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_typedefs.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_typedefs.svh new file mode 100644 index 0000000..f2a7bdb --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_typedefs.svh @@ -0,0 +1,34 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the host server when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_typedefs_hdl.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_typedefs_hdl.svh new file mode 100644 index 0000000..0d58518 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_typedefs_hdl.svh @@ -0,0 +1,35 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the emulator when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/yaml/fuse_ctrl_prim_axi_write_out_interface.yaml b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/yaml/fuse_ctrl_prim_axi_write_out_interface.yaml new file mode 100644 index 0000000..d0566d0 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/yaml/fuse_ctrl_prim_axi_write_out_interface.yaml @@ -0,0 +1,81 @@ +uvmf: + interfaces: + fuse_ctrl_prim_axi_write_out: + clock: clk_i + config_constraints: [] + config_vars: [] + existing_library_component: 'True' + gen_inbound_streaming_driver: 'False' + hdl_pkg_parameters: [] + hdl_typedefs: [] + hvl_pkg_parameters: [] + hvl_typedefs: [] + parameters: + - name: AW + type: int + value: '32' + - name: DW + type: int + value: '32' + - name: IW + type: int + value: '3' + - name: UW + type: int + value: '32' + ports: + - dir: input + name: awready + reset_value: '''bz' + width: '1' + - dir: input + name: wready + reset_value: '''bz' + width: '1' + - dir: input + name: bresp + reset_value: '''bz' + width: '[''$bits(axi_pkg::axi_burst_e)'']' + - dir: input + name: bid + reset_value: '''bz' + width: '1' + - dir: input + name: bvalid + reset_value: '''bz' + width: '1' + reset: rst_ni + reset_assertion_level: 'False' + transaction_constraints: [] + transaction_vars: + - comment: '' + iscompare: 'True' + isrand: 'False' + name: prim_awready + type: logic + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'False' + name: prim_wready + type: logic + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'False' + name: prim_bresp + type: axi_pkg::axi_burst_e + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'False' + name: prim_bid + type: logic + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'False' + name: prim_bvalid + type: logic + unpacked_dimension: '' + use_dpi_link: 'False' diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/.project b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/.project new file mode 100644 index 0000000..942f586 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/.project @@ -0,0 +1,30 @@ + + + fuse_ctrl_rst_in_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/.svproject b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/.svproject new file mode 100644 index 0000000..8ad7633 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/Makefile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/Makefile new file mode 100644 index 0000000..7a8fb49 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/Makefile @@ -0,0 +1,66 @@ +# fuse_ctrl_rst_in interface packages source +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +fuse_ctrl_rst_in_PKG = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_in_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_filelist_hvl.f + +fuse_ctrl_rst_in_PKG_HDL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_in_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_filelist_hdl.f + +fuse_ctrl_rst_in_PKG_XRTL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_in_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_filelist_xrtl.f + +COMP_fuse_ctrl_rst_in_PKG_TGT_0 = q_comp_fuse_ctrl_rst_in_pkg +COMP_fuse_ctrl_rst_in_PKG_TGT_1 = v_comp_fuse_ctrl_rst_in_pkg +COMP_fuse_ctrl_rst_in_PKG_TGT = $(COMP_fuse_ctrl_rst_in_PKG_TGT_$(USE_VELOCE)) + +comp_fuse_ctrl_rst_in_pkg: $(COMP_fuse_ctrl_rst_in_PKG_TGT) + +q_comp_fuse_ctrl_rst_in_pkg: + $(HDL_COMP_CMD) $(fuse_ctrl_rst_in_PKG_HDL) + $(HVL_COMP_CMD) $(fuse_ctrl_rst_in_PKG) + $(HDL_COMP_CMD) $(fuse_ctrl_rst_in_PKG_XRTL) + +v_comp_fuse_ctrl_rst_in_pkg: + $(HVL_COMP_CMD) $(fuse_ctrl_rst_in_PKG_HDL) + $(HVL_COMP_CMD) $(fuse_ctrl_rst_in_PKG) + $(VELANALYZE_CMD) $(fuse_ctrl_rst_in_PKG_HDL) + $(VELANALYZE_HVL_CMD) $(fuse_ctrl_rst_in_PKG) + $(HDL_COMP_CMD) $(fuse_ctrl_rst_in_PKG_XRTL) + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export fuse_ctrl_rst_in_IF_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_in_pkg/dpi + +C_FILE_COMPILE_LIST_fuse_ctrl_rst_in_pkg = \ + +O_FILE_COMPILE_LIST_fuse_ctrl_rst_in_pkg = $(notdir $(C_FILE_COMPILE_LIST_fuse_ctrl_rst_in_pkg:.c=.o)) + +GCC_COMP_ARGS_fuse_ctrl_rst_in_pkg += -I$(fuse_ctrl_rst_in_IF_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_fuse_ctrl_rst_in_pkg += $(fuse_ctrl_rst_in_IF_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_fuse_ctrl_rst_in_pkg += \ + \ + -o .so + +comp_fuse_ctrl_rst_in_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Interface C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_fuse_ctrl_rst_in_pkg) $(C_FILE_COMPILE_LIST_fuse_ctrl_rst_in_pkg) + @echo "--------------------------------" + @echo "Linking Interface C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_fuse_ctrl_rst_in_pkg) $(O_FILE_COMPILE_LIST_fuse_ctrl_rst_in_pkg) + @echo "--------------------------------" + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/compile.do b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/compile.do new file mode 100644 index 0000000..8fe1b23 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/compile.do @@ -0,0 +1,14 @@ +# Tcl do file for compile of fuse_ctrl_rst_in interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_in_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_filelist_hdl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_in_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_filelist_hvl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_in_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_filelist_xrtl.f \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in.compile new file mode 100644 index 0000000..fdf807f --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in.compile @@ -0,0 +1,3 @@ +needs: + - fuse_ctrl_rst_in_hvl.compile + - fuse_ctrl_rst_in_hdl.compile diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_bfm.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_bfm.vinfo new file mode 100644 index 0000000..acb7e42 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_bfm.vinfo @@ -0,0 +1,6 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use fuse_ctrl_rst_in_pkg_hdl.vinfo ++incdir+@vinfodir +src/fuse_ctrl_rst_in_if.sv +src/fuse_ctrl_rst_in_driver_bfm.sv +src/fuse_ctrl_rst_in_monitor_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_common.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_common.compile new file mode 100644 index 0000000..66aaa58 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_common.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +incdir: + - . + - ${uvm_path}/src +src: + - fuse_ctrl_rst_in_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_filelist_hdl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_filelist_hdl.f new file mode 100644 index 0000000..19c4368 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_filelist_hdl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_filelist_hvl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_filelist_hvl.f new file mode 100644 index 0000000..1a44578 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_filelist_hvl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_pkg.sv \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_filelist_xrtl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_filelist_xrtl.f new file mode 100644 index 0000000..2a4fd65 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_filelist_xrtl.f @@ -0,0 +1,3 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_if.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_monitor_bfm.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_driver_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_hdl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_hdl.compile new file mode 100644 index 0000000..a3d5a61 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_hdl.compile @@ -0,0 +1,9 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ./fuse_ctrl_rst_in_common.compile +incdir: + - . +src: + - src/fuse_ctrl_rst_in_if.sv + - src/fuse_ctrl_rst_in_monitor_bfm.sv + - src/fuse_ctrl_rst_in_driver_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_hvl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_hvl.compile new file mode 100644 index 0000000..26e18a7 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_hvl.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ./fuse_ctrl_rst_in_common.compile +incdir: + - . +src: + - fuse_ctrl_rst_in_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_pkg.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_pkg.sv new file mode 100644 index 0000000..05dd6ee --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_pkg.sv @@ -0,0 +1,91 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - + +// - +// - +// - + +// - +// - +// - + +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_rst_in_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg_hdl::*; + import uvmf_base_pkg::*; + import fuse_ctrl_rst_in_pkg_hdl::*; + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + `include "src/fuse_ctrl_rst_in_macros.svh" + + export fuse_ctrl_rst_in_pkg_hdl::*; + + + + // Parameters defined as HVL parameters + + `include "src/fuse_ctrl_rst_in_typedefs.svh" + `include "src/fuse_ctrl_rst_in_transaction.svh" + + `include "src/fuse_ctrl_rst_in_configuration.svh" + `include "src/fuse_ctrl_rst_in_driver.svh" + `include "src/fuse_ctrl_rst_in_monitor.svh" + + `include "src/fuse_ctrl_rst_in_transaction_coverage.svh" + `include "src/fuse_ctrl_rst_in_sequence_base.svh" + `include "src/fuse_ctrl_rst_in_random_sequence.svh" + + `include "src/fuse_ctrl_rst_in_responder_sequence.svh" + `include "src/fuse_ctrl_rst_in2reg_adapter.svh" + + `include "src/fuse_ctrl_rst_in_agent.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new interface sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the interface package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_pkg.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_pkg.vinfo new file mode 100644 index 0000000..37f5660 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_pkg.vinfo @@ -0,0 +1,4 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use fuse_ctrl_rst_in_pkg_hdl.vinfo ++incdir+@vinfodir +fuse_ctrl_rst_in_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_pkg_hdl.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_pkg_hdl.sv new file mode 100644 index 0000000..5723531 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_pkg_hdl.sv @@ -0,0 +1,52 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that needs to be compiled and synthesized +// for running on Veloce. +// +// CONTAINS: +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_rst_in_pkg_hdl; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HDL parameters + + `include "src/fuse_ctrl_rst_in_typedefs_hdl.svh" + `include "src/fuse_ctrl_rst_in_macros.svh" + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_pkg_hdl.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_pkg_hdl.vinfo new file mode 100644 index 0000000..313c0e8 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_pkg_hdl.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +fuse_ctrl_rst_in_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_pkg_sve.F b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_pkg_sve.F new file mode 100644 index 0000000..d9e5416 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_pkg_sve.F @@ -0,0 +1,10 @@ +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + ++incdir+. +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_filelist_hdl.f +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_filelist_hvl.f diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in2reg_adapter.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in2reg_adapter.svh new file mode 100644 index 0000000..00428f2 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in2reg_adapter.svh @@ -0,0 +1,112 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the UVM register adapter for the fuse_ctrl_rst_in interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_rst_in2reg_adapter extends uvm_reg_adapter; + + `uvm_object_utils( fuse_ctrl_rst_in2reg_adapter ) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //-------------------------------------------------------------------- + // new + //-------------------------------------------------------------------- + function new (string name = "fuse_ctrl_rst_in2reg_adapter" ); + super.new(name); + // pragma uvmf custom new begin + // UVMF_CHANGE_ME : Configure the adapter regarding byte enables and provides response. + + // Does the protocol the Agent is modeling support byte enables? + // 0 = NO + // 1 = YES + supports_byte_enable = 0; + + // Does the Agent's Driver provide separate response sequence items? + // i.e. Does the driver call seq_item_port.put() + // and do the sequences call get_response()? + // 0 = NO + // 1 = YES + provides_responses = 0; + // pragma uvmf custom new end + + endfunction: new + + //-------------------------------------------------------------------- + // reg2bus + //-------------------------------------------------------------------- + virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw); + + fuse_ctrl_rst_in_transaction trans_h = fuse_ctrl_rst_in_transaction ::type_id::create("trans_h"); + + // pragma uvmf custom reg2bus begin + // UVMF_CHANGE_ME : Fill in the reg2bus adapter mapping registe fields to protocol fields. + + //Adapt the following for your sequence item type + // trans_h.op = (rw.kind == UVM_READ) ? WB_READ : WB_WRITE; + //Copy over address + // trans_h.addr = rw.addr; + //Copy over write data + // trans_h.data = rw.data; + + // pragma uvmf custom reg2bus end + + // Return the adapted transaction + return trans_h; + + endfunction: reg2bus + + //-------------------------------------------------------------------- + // bus2reg + //-------------------------------------------------------------------- + virtual function void bus2reg(uvm_sequence_item bus_item, + ref uvm_reg_bus_op rw); + fuse_ctrl_rst_in_transaction trans_h; + if (!$cast(trans_h, bus_item)) begin + `uvm_fatal("ADAPT","Provided bus_item is not of the correct type") + return; + end + // pragma uvmf custom bus2reg begin + // UVMF_CHANGE_ME : Fill in the bus2reg adapter mapping protocol fields to register fields. + //Adapt the following for your sequence item type + //Copy over instruction type + // rw.kind = (trans_h.op == WB_WRITE) ? UVM_WRITE : UVM_READ; + //Copy over address + // rw.addr = trans_h.addr; + //Copy over read data + // rw.data = trans_h.data; + //Check for errors on the bus and return UVM_NOT_OK if there is an error + // rw.status = UVM_IS_OK; + // pragma uvmf custom bus2reg end + + endfunction: bus2reg + +endclass : fuse_ctrl_rst_in2reg_adapter + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_agent.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_agent.svh new file mode 100644 index 0000000..2de920a --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_agent.svh @@ -0,0 +1,67 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: Protocol specific agent class definition +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_rst_in_agent extends uvmf_parameterized_agent #( + .CONFIG_T(fuse_ctrl_rst_in_configuration ), + .DRIVER_T(fuse_ctrl_rst_in_driver ), + .MONITOR_T(fuse_ctrl_rst_in_monitor ), + .COVERAGE_T(fuse_ctrl_rst_in_transaction_coverage ), + .TRANS_T(fuse_ctrl_rst_in_transaction ) + ); + + `uvm_component_utils( fuse_ctrl_rst_in_agent ) + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** + // FUNCTION: build_phase + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + if (configuration.active_passive == ACTIVE) begin + // Place sequencer handle into configuration object + // so that it may be retrieved from configuration + // rather than using uvm_config_db + configuration.sequencer = this.sequencer; + end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_configuration.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_configuration.svh new file mode 100644 index 0000000..3010ecf --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_configuration.svh @@ -0,0 +1,193 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class contains all variables and functions used +// to configure the fuse_ctrl_rst_in agent and its bfm's. It gets the +// bfm's from the uvm_config_db for use by the agent. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_rst_in_configuration extends uvmf_parameterized_agent_configuration_base #( + .DRIVER_BFM_BIND_T(virtual fuse_ctrl_rst_in_driver_bfm ), + .MONITOR_BFM_BIND_T( virtual fuse_ctrl_rst_in_monitor_bfm )); + + `uvm_object_utils( fuse_ctrl_rst_in_configuration ) + + + // Sequencer handle populated by agent + uvm_sequencer #(fuse_ctrl_rst_in_transaction ) sequencer; + + //Constraints for the configuration variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + covergroup fuse_ctrl_rst_in_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + // pragma uvmf custom covergroup end + endgroup + + //******************************************************************* + //******************************************************************* + // Structure used to pass configuration variables to monitor and driver BFM's. + // Use to_struct function to pack variables into structure. + // Use from_struct function to unpack variables from structure. + // This structure is defined in fuse_ctrl_rst_in_macros.svh + `fuse_ctrl_rst_in_CONFIGURATION_STRUCT + fuse_ctrl_rst_in_configuration_s fuse_ctrl_rst_in_configuration_struct; + //******************************************************************* + // FUNCTION: to_struct() + // This function packs variables into a fuse_ctrl_rst_in_configuration_s + // structure. The function returns the handle to the fuse_ctrl_rst_in_configuration_struct. + // This function is defined in fuse_ctrl_rst_in_macros.svh + `fuse_ctrl_rst_in_CONFIGURATION_TO_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_struct() + // This function unpacks the struct provided as an argument into + // variables of this class. + // This function is defined in fuse_ctrl_rst_in_macros.svh + `fuse_ctrl_rst_in_CONFIGURATION_FROM_STRUCT_FUNCTION + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + // Construct the covergroup for this configuration class + fuse_ctrl_rst_in_configuration_cg = new; + endfunction + + // **************************************************************************** + // FUNCTION: post_randomize() + // This function is automatically called after the randomize() function + // is executed. + // + function void post_randomize(); + super.post_randomize(); + fuse_ctrl_rst_in_configuration_cg.sample(); + endfunction + + // **************************************************************************** + // FUNCTION: initialize + // This function causes the configuration to retrieve + // its virtual interface handle from the uvm_config_db. + // This function also makes itself available to its + // agent through the uvm_config_db. + // + // ARGUMENTS: + // uvmf_active_passive_t activity: + // This argument identifies the simulation level + // as either BLOCK, CHIP, SIMULATION, etc. + // + // AGENT_PATH: + // This argument identifies the path to this + // configurations agent. This configuration + // makes itself available to the agent specified + // by agent_path by placing itself into the + // uvm_config_db. + // + // INTERFACE_NAME: + // This argument identifies the string name of + // this configurations BFM's. This string + // name is used to retrieve the driver and + // monitor BFM from the uvm_config_db. + // + virtual function void initialize(uvmf_active_passive_t activity, + string agent_path, + string interface_name); + + super.initialize( activity, agent_path, interface_name); + // The covergroup is given the same name as the interface + fuse_ctrl_rst_in_configuration_cg.set_inst_name(interface_name); + + // This configuration places itself into the uvm_config_db for the agent, identified by the agent_path variable, to retrieve. + uvm_config_db #( fuse_ctrl_rst_in_configuration + )::set( null ,agent_path,UVMF_AGENT_CONFIG, this ); + + // This configuration also places itself in the config db using the same identifier used by the interface. This allows users to access + // configuration variables and the interface through the bfm api class rather than directly accessing the BFM. This is useful for + // accessingthe BFM when using Veloce + uvm_config_db #( fuse_ctrl_rst_in_configuration + )::set( null ,UVMF_CONFIGURATIONS, interface_name, this ); + + fuse_ctrl_rst_in_configuration_cg.set_inst_name($sformatf("fuse_ctrl_rst_in_configuration_cg_%s",get_full_name())); + +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. + `uvm_info("CFG", + $psprintf("The agent at '%s' is using interface named %s has the following parameters: ", agent_path, interface_name, ), + UVM_DEBUG) + + // pragma uvmf custom initialize begin + // This controls whether or not the agent returns a transaction handle in the driver when calling + // item_done() back into the sequencer or not. If set to 1, a transaction is sent back which means + // the sequence on the other end must use the get_response() part of the driver/sequence API. If + // this doesn't occur, there will eventually be response_queue overflow errors during the test. + return_transaction_response = 1'b0; + + // pragma uvmf custom initialize end + + endfunction + + // **************************************************************************** + // TASK: wait_for_reset + // *[Required]* Blocks until reset is released. The wait_for_reset operation is performed + // by a task in the monitor bfm. + virtual task wait_for_reset(); + monitor_bfm.wait_for_reset(); + endtask + + // **************************************************************************** + // TASK: wait_for_num_clocks + // *[Required]* Blocks until specified number of clocks have elapsed. The wait_for_num_clocks + // operation is performed by a task in the monitor bfm. + virtual task wait_for_num_clocks(int clocks); + monitor_bfm.wait_for_num_clocks(clocks); + endtask + + // **************************************************************************** + // FUNCTION : convert2string() + // This function is used to convert variables in this class into a string for log messaging. + // + virtual function string convert2string (); + // pragma uvmf custom convert2string begin + return $sformatf(""); + // pragma uvmf custom convert2string end + endfunction + + // **************************************************************************** + // FUNCTION: get_sequencer + function uvm_sequencer #(fuse_ctrl_rst_in_transaction) get_sequencer(); + return sequencer; + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_driver.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_driver.svh new file mode 100644 index 0000000..e691b01 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_driver.svh @@ -0,0 +1,105 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class passes transactions between the sequencer +// and the BFM driver interface. It accesses the driver BFM +// through the bfm handle. This driver +// passes transactions to the driver BFM through the access +// task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_rst_in_driver extends uvmf_driver_base #( + .CONFIG_T(fuse_ctrl_rst_in_configuration ), + .BFM_BIND_T(virtual fuse_ctrl_rst_in_driver_bfm ), + .REQ(fuse_ctrl_rst_in_transaction ), + .RSP(fuse_ctrl_rst_in_transaction )); + + `uvm_component_utils( fuse_ctrl_rst_in_driver ) +//******************************************************************* +// Macros that define structs located in fuse_ctrl_rst_in_macros.svh +//******************************************************************* +// Initiator macro used by fuse_ctrl_rst_in_driver and fuse_ctrl_rst_in_driver_bfm +// to communicate initiator driven data to fuse_ctrl_rst_in_driver_bfm. +`fuse_ctrl_rst_in_INITIATOR_STRUCT + fuse_ctrl_rst_in_initiator_s fuse_ctrl_rst_in_initiator_struct; +//******************************************************************* +// Responder macro used by fuse_ctrl_rst_in_driver and fuse_ctrl_rst_in_driver_bfm +// to communicate Responder driven data to fuse_ctrl_rst_in_driver_bfm. +`fuse_ctrl_rst_in_RESPONDER_STRUCT + fuse_ctrl_rst_in_responder_s fuse_ctrl_rst_in_responder_struct; + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent=null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the driver BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// driver BFM. This allows the driver BFM to call tasks and function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// **************************************************************************** +// This task is called by the run_phase in uvmf_driver_base. + virtual task access( inout REQ txn ); +// pragma uvmf custom access begin + if (configuration.initiator_responder==RESPONDER) begin + // Complete current transfer and wait for next transfer + bfm.respond_and_wait_for_next_transfer( + fuse_ctrl_rst_in_initiator_struct, + txn.to_responder_struct() + ); + // Unpack information about initiated transfer received by this responder + txn.from_initiator_struct(fuse_ctrl_rst_in_initiator_struct); + end else begin + // Initiate a transfer and get response + bfm.initiate_and_get_response( + txn.to_initiator_struct(), + fuse_ctrl_rst_in_responder_struct + ); + // Unpack transfer response information received by this initiator + txn.from_responder_struct(fuse_ctrl_rst_in_responder_struct); + end +// pragma uvmf custom access end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_driver_bfm.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_driver_bfm.sv new file mode 100644 index 0000000..b992b39 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_driver_bfm.sv @@ -0,0 +1,298 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This interface performs the fuse_ctrl_rst_in signal driving. It is +// accessed by the uvm fuse_ctrl_rst_in driver through a virtual interface +// handle in the fuse_ctrl_rst_in configuration. It drives the singals passed +// in through the port connection named bus of type fuse_ctrl_rst_in_if. +// +// Input signals from the fuse_ctrl_rst_in_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// This bfm drives signals with a _o suffix. These signals +// are driven onto signals within fuse_ctrl_rst_in_if based on INITIATOR/RESPONDER and/or +// ARBITRATION/GRANT status. +// +// The output signal connections are as follows: +// signal_o -> bus.signal +// +// +// Interface functions and tasks used by UVM components: +// +// configure: +// This function gets configuration attributes from the +// UVM driver to set any required BFM configuration +// variables such as 'initiator_responder'. +// +// initiate_and_get_response: +// This task is used to perform signaling activity for initiating +// a protocol transfer. The task initiates the transfer, using +// input data from the initiator struct. Then the task captures +// response data, placing the data into the response struct. +// The response struct is returned to the driver class. +// +// respond_and_wait_for_next_transfer: +// This task is used to complete a current transfer as a responder +// and then wait for the initiator to start the next transfer. +// The task uses data in the responder struct to drive protocol +// signals to complete the transfer. The task then waits for +// the next transfer. Once the next transfer begins, data from +// the initiator is placed into the initiator struct and sent +// to the responder sequence for processing to determine +// what data to respond with. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_rst_in_pkg_hdl::*; +`include "src/fuse_ctrl_rst_in_macros.svh" + +interface fuse_ctrl_rst_in_driver_bfm + (fuse_ctrl_rst_in_if bus); + // The following pragma and additional ones in-lined further below are for running this BFM on Veloce + // pragma attribute fuse_ctrl_rst_in_driver_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: ", ), + UVM_DEBUG) +end +`endif + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + tri clk_i_i; + tri rst_ni_i; + + // Signal list (all signals are capable of being inputs and outputs for the sake + // of supporting both INITIATOR and RESPONDER mode operation. Expectation is that + // directionality in the config file was from the point-of-view of the INITIATOR + + // INITIATOR mode input signals + + // INITIATOR mode output signals + tri [$bits(pwrmgr_pkg::pwr_otp_req_t)-1:0] pwr_otp_i_i; + reg [$bits(pwrmgr_pkg::pwr_otp_req_t)-1:0] pwr_otp_i_o = 'bz; + + // Bi-directional signals + tri otp_ext_voltage_h_io_i; + reg otp_ext_voltage_h_io_o = 'bz; + + + assign clk_i_i = bus.clk_i; + assign rst_ni_i = bus.rst_ni; + + // These are signals marked as 'input' by the config file, but the signals will be + // driven by this BFM if put into RESPONDER mode (flipping all signal directions around) + + assign otp_ext_voltage_h_io_i = bus.otp_ext_voltage_h_io; + + // These are signals marked as 'output' by the config file, but the outputs will + // not be driven by this BFM unless placed in INITIATOR mode. + assign bus.pwr_otp_i = (initiator_responder == INITIATOR) ? pwr_otp_i_o : 'bz; + assign pwr_otp_i_i = bus.pwr_otp_i; + assign bus.otp_ext_voltage_h_io = otp_ext_voltage_h_io_o; + + // Proxy handle to UVM driver + fuse_ctrl_rst_in_pkg::fuse_ctrl_rst_in_driver proxy; + // pragma tbx oneway proxy.my_function_name_in_uvm_driver + + // **************************************************************************** + // **************************************************************************** + // Macros that define structs located in fuse_ctrl_rst_in_macros.svh + // **************************************************************************** + // Struct for passing configuration data from fuse_ctrl_rst_in_driver to this BFM + // **************************************************************************** + `fuse_ctrl_rst_in_CONFIGURATION_STRUCT + // **************************************************************************** + // Structs for INITIATOR and RESPONDER data flow + //******************************************************************* + // Initiator macro used by fuse_ctrl_rst_in_driver and fuse_ctrl_rst_in_driver_bfm + // to communicate initiator driven data to fuse_ctrl_rst_in_driver_bfm. + `fuse_ctrl_rst_in_INITIATOR_STRUCT + fuse_ctrl_rst_in_initiator_s initiator_struct; + // Responder macro used by fuse_ctrl_rst_in_driver and fuse_ctrl_rst_in_driver_bfm + // to communicate Responder driven data to fuse_ctrl_rst_in_driver_bfm. + `fuse_ctrl_rst_in_RESPONDER_STRUCT + fuse_ctrl_rst_in_responder_s responder_struct; + + // **************************************************************************** +// pragma uvmf custom reset_condition_and_response begin + // Always block used to return signals to reset value upon assertion of reset + always @( negedge rst_ni_i ) + begin + // RESPONDER mode output signals + // INITIATOR mode output signals + pwr_otp_i_o <= 'bz; + // Bi-directional signals + otp_ext_voltage_h_io_o <= 'bz; + + end +// pragma uvmf custom reset_condition_and_response end + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the driver BFM. It is called by the driver within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the driver BFM needs to be aware of the new configuration + // variables. + // + + function void configure(fuse_ctrl_rst_in_configuration_s fuse_ctrl_rst_in_configuration_arg); // pragma tbx xtf + initiator_responder = fuse_ctrl_rst_in_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + +// pragma uvmf custom initiate_and_get_response begin +// **************************************************************************** +// UVMF_CHANGE_ME +// This task is used by an initator. The task first initiates a transfer then +// waits for the responder to complete the transfer. + task initiate_and_get_response( + // This argument passes transaction variables used by an initiator + // to perform the initial part of a protocol transfer. The values + // come from a sequence item created in a sequence. + input fuse_ctrl_rst_in_initiator_s fuse_ctrl_rst_in_initiator_struct, + // This argument is used to send data received from the responder + // back to the sequence item. The sequence item is returned to the sequence. + output fuse_ctrl_rst_in_responder_s fuse_ctrl_rst_in_responder_struct + );// pragma tbx xtf + // + // Members within the fuse_ctrl_rst_in_initiator_struct: + // bit assert_rst ; + // bit assert_otp_pwr_init ; + // Members within the fuse_ctrl_rst_in_responder_struct: + // bit assert_rst ; + // bit assert_otp_pwr_init ; + initiator_struct = fuse_ctrl_rst_in_initiator_struct; + // + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clk_i_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available initiator input and inout signals listed. + // Initiator input signals + // Initiator inout signals + // fuse_ctrl_rst_in_responder_struct.xyz = otp_ext_voltage_h_io_i; // + // How to assign a signal from an initiator struct member named xyz. + // All available initiator output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Initiator output signals + // pwr_otp_i_o <= fuse_ctrl_rst_in_initiator_struct.xyz; // [$bits(pwrmgr_pkg::pwr_otp_req_t)-1:0] + // Initiator inout signals + // otp_ext_voltage_h_io_o <= fuse_ctrl_rst_in_initiator_struct.xyz; // + // Initiate a transfer using the data received. + @(posedge clk_i_i); + @(posedge clk_i_i); + // Wait for the responder to complete the transfer then place the responder data into + // fuse_ctrl_rst_in_responder_struct. + @(posedge clk_i_i); + @(posedge clk_i_i); + responder_struct = fuse_ctrl_rst_in_responder_struct; + endtask +// pragma uvmf custom initiate_and_get_response end + +// pragma uvmf custom respond_and_wait_for_next_transfer begin +// **************************************************************************** +// The first_transfer variable is used to prevent completing a transfer in the +// first call to this task. For the first call to this task, there is not +// current transfer to complete. +bit first_transfer=1; + +// UVMF_CHANGE_ME +// This task is used by a responder. The task first completes the current +// transfer in progress then waits for the initiator to start the next transfer. + task respond_and_wait_for_next_transfer( + // This argument is used to send data received from the initiator + // back to the sequence item. The sequence determines how to respond. + output fuse_ctrl_rst_in_initiator_s fuse_ctrl_rst_in_initiator_struct, + // This argument passes transaction variables used by a responder + // to complete a protocol transfer. The values come from a sequence item. + input fuse_ctrl_rst_in_responder_s fuse_ctrl_rst_in_responder_struct + );// pragma tbx xtf + // Variables within the fuse_ctrl_rst_in_initiator_struct: + // bit assert_rst ; + // bit assert_otp_pwr_init ; + // Variables within the fuse_ctrl_rst_in_responder_struct: + // bit assert_rst ; + // bit assert_otp_pwr_init ; + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clk_i_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available responder input and inout signals listed. + // Responder input signals + // fuse_ctrl_rst_in_responder_struct.xyz = pwr_otp_i_i; // [$bits(pwrmgr_pkg::pwr_otp_req_t)-1:0] + // Responder inout signals + // fuse_ctrl_rst_in_responder_struct.xyz = otp_ext_voltage_h_io_i; // + // How to assign a signal, named xyz, from an initiator struct member. + // All available responder output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Responder output signals + // Responder inout signals + // otp_ext_voltage_h_io_o <= fuse_ctrl_rst_in_initiator_struct.xyz; // + + @(posedge clk_i_i); + if (!first_transfer) begin + // Perform transfer response here. + // Reply using data recieved in the fuse_ctrl_rst_in_responder_struct. + @(posedge clk_i_i); + // Reply using data recieved in the transaction handle. + @(posedge clk_i_i); + end + // Wait for next transfer then gather info from intiator about the transfer. + // Place the data into the fuse_ctrl_rst_in_initiator_struct. + @(posedge clk_i_i); + @(posedge clk_i_i); + first_transfer = 0; + endtask +// pragma uvmf custom respond_and_wait_for_next_transfer end + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_if.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_if.sv new file mode 100644 index 0000000..de04ea9 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_if.sv @@ -0,0 +1,83 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface contains the fuse_ctrl_rst_in interface signals. +// It is instantiated once per fuse_ctrl_rst_in bus. Bus Functional Models, +// BFM's named fuse_ctrl_rst_in_driver_bfm, are used to drive signals on the bus. +// BFM's named fuse_ctrl_rst_in_monitor_bfm are used to monitor signals on the +// bus. This interface signal bundle is passed in the port list of +// the BFM in order to give the BFM access to the signals in this +// interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// This template can be used to connect a DUT to these signals +// +// .dut_signal_port(fuse_ctrl_rst_in_bus.pwr_otp_i), // Agent output +// .dut_signal_port(fuse_ctrl_rst_in_bus.otp_ext_voltage_h_io), // Agent inout + +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_rst_in_pkg_hdl::*; + +interface fuse_ctrl_rst_in_if + + ( + input tri clk_i, + input tri rst_ni, + inout tri [$bits(pwrmgr_pkg::pwr_otp_req_t)-1:0] pwr_otp_i, + inout tri otp_ext_voltage_h_io + ); + +modport monitor_port + ( + input clk_i, + input rst_ni, + input pwr_otp_i, + input otp_ext_voltage_h_io + ); + +modport initiator_port + ( + input clk_i, + input rst_ni, + output pwr_otp_i, + inout otp_ext_voltage_h_io + ); + +modport responder_port + ( + input clk_i, + input rst_ni, + input pwr_otp_i, + inout otp_ext_voltage_h_io + ); + + +// pragma uvmf custom interface_item_additional begin +// pragma uvmf custom interface_item_additional end + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_infact_coverage_strategy.csv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_infact_coverage_strategy.csv new file mode 100644 index 0000000..1c218e1 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_infact_coverage_strategy.csv @@ -0,0 +1,6 @@ +Global +auto_bin_max, 64 + +Name,Type,Include +rand_fields,coverpoint,=rand *.** + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_macros.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_macros.svh new file mode 100644 index 0000000..a7124a6 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_macros.svh @@ -0,0 +1,144 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains macros used with the fuse_ctrl_rst_in package. +// These macros include packed struct definitions. These structs are +// used to pass data between classes, hvl, and BFM's, hdl. Use of +// structs are more efficient and simpler to modify. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_struct +// and from_struct methods defined in the macros below that are used in +// the fuse_ctrl_rst_in_configuration class. +// + `define fuse_ctrl_rst_in_CONFIGURATION_STRUCT \ +typedef struct packed { \ + uvmf_active_passive_t active_passive; \ + uvmf_initiator_responder_t initiator_responder; \ + } fuse_ctrl_rst_in_configuration_s; + + `define fuse_ctrl_rst_in_CONFIGURATION_TO_STRUCT_FUNCTION \ + virtual function fuse_ctrl_rst_in_configuration_s to_struct();\ + fuse_ctrl_rst_in_configuration_struct = \ + {\ + this.active_passive,\ + this.initiator_responder\ + };\ + return ( fuse_ctrl_rst_in_configuration_struct );\ + endfunction + + `define fuse_ctrl_rst_in_CONFIGURATION_FROM_STRUCT_FUNCTION \ + virtual function void from_struct(fuse_ctrl_rst_in_configuration_s fuse_ctrl_rst_in_configuration_struct);\ + {\ + this.active_passive,\ + this.initiator_responder \ + } = fuse_ctrl_rst_in_configuration_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_monitor_struct +// and from_monitor_struct methods of the fuse_ctrl_rst_in_transaction class. +// + `define fuse_ctrl_rst_in_MONITOR_STRUCT typedef struct packed { \ + bit assert_rst ; \ + bit assert_otp_pwr_init ; \ + } fuse_ctrl_rst_in_monitor_s; + + `define fuse_ctrl_rst_in_TO_MONITOR_STRUCT_FUNCTION \ + virtual function fuse_ctrl_rst_in_monitor_s to_monitor_struct();\ + fuse_ctrl_rst_in_monitor_struct = \ + { \ + this.assert_rst , \ + this.assert_otp_pwr_init \ + };\ + return ( fuse_ctrl_rst_in_monitor_struct);\ + endfunction\ + + `define fuse_ctrl_rst_in_FROM_MONITOR_STRUCT_FUNCTION \ + virtual function void from_monitor_struct(fuse_ctrl_rst_in_monitor_s fuse_ctrl_rst_in_monitor_struct);\ + {\ + this.assert_rst , \ + this.assert_otp_pwr_init \ + } = fuse_ctrl_rst_in_monitor_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_initiator_struct +// and from_initiator_struct methods of the fuse_ctrl_rst_in_transaction class. +// Also update the comments in the driver BFM. +// + `define fuse_ctrl_rst_in_INITIATOR_STRUCT typedef struct packed { \ + bit assert_rst ; \ + bit assert_otp_pwr_init ; \ + } fuse_ctrl_rst_in_initiator_s; + + `define fuse_ctrl_rst_in_TO_INITIATOR_STRUCT_FUNCTION \ + virtual function fuse_ctrl_rst_in_initiator_s to_initiator_struct();\ + fuse_ctrl_rst_in_initiator_struct = \ + {\ + this.assert_rst , \ + this.assert_otp_pwr_init \ + };\ + return ( fuse_ctrl_rst_in_initiator_struct);\ + endfunction + + `define fuse_ctrl_rst_in_FROM_INITIATOR_STRUCT_FUNCTION \ + virtual function void from_initiator_struct(fuse_ctrl_rst_in_initiator_s fuse_ctrl_rst_in_initiator_struct);\ + {\ + this.assert_rst , \ + this.assert_otp_pwr_init \ + } = fuse_ctrl_rst_in_initiator_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_responder_struct +// and from_responder_struct methods of the fuse_ctrl_rst_in_transaction class. +// Also update the comments in the driver BFM. +// + `define fuse_ctrl_rst_in_RESPONDER_STRUCT typedef struct packed { \ + bit assert_rst ; \ + bit assert_otp_pwr_init ; \ + } fuse_ctrl_rst_in_responder_s; + + `define fuse_ctrl_rst_in_TO_RESPONDER_STRUCT_FUNCTION \ + virtual function fuse_ctrl_rst_in_responder_s to_responder_struct();\ + fuse_ctrl_rst_in_responder_struct = \ + {\ + this.assert_rst , \ + this.assert_otp_pwr_init \ + };\ + return ( fuse_ctrl_rst_in_responder_struct);\ + endfunction + + `define fuse_ctrl_rst_in_FROM_RESPONDER_STRUCT_FUNCTION \ + virtual function void from_responder_struct(fuse_ctrl_rst_in_responder_s fuse_ctrl_rst_in_responder_struct);\ + {\ + this.assert_rst , \ + this.assert_otp_pwr_init \ + } = fuse_ctrl_rst_in_responder_struct;\ + endfunction +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_monitor.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_monitor.svh new file mode 100644 index 0000000..f160bbc --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_monitor.svh @@ -0,0 +1,101 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class receives fuse_ctrl_rst_in transactions observed by the +// fuse_ctrl_rst_in monitor BFM and broadcasts them through the analysis port +// on the agent. It accesses the monitor BFM through the monitor +// task. This UVM component captures transactions +// for viewing in the waveform viewer if the +// enable_transaction_viewing flag is set in the configuration. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_rst_in_monitor extends uvmf_monitor_base #( + .CONFIG_T(fuse_ctrl_rst_in_configuration ), + .BFM_BIND_T(virtual fuse_ctrl_rst_in_monitor_bfm ), + .TRANS_T(fuse_ctrl_rst_in_transaction )); + + `uvm_component_utils( fuse_ctrl_rst_in_monitor ) + +// Structure used to pass data from monitor BFM to monitor class in agent. +// Use to_monitor_struct function to pack transaction variables into structure. +// Use from_monitor_struct function to unpack transaction variables from structure. +`fuse_ctrl_rst_in_MONITOR_STRUCT + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the monitor BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// monitor BFM. This allows the monitor BFM to call the notify_transaction +// function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// *************************************************************************** + virtual task run_phase(uvm_phase phase); + // Start monitor BFM thread and don't call super.run() in order to + // override the default monitor proxy 'pull' behavior with the more + // emulation-friendly BFM 'push' approach using the notify_transaction + // function below + bfm.start_monitoring(); + endtask + +// ************************************************************************** + +// This function is called by the monitor BFM. It receives data observed by the +// monitor BFM. Data is passed using the fuse_ctrl_rst_in_monitor_struct. + virtual function void notify_transaction(input fuse_ctrl_rst_in_monitor_s fuse_ctrl_rst_in_monitor_struct); + + + trans = new("trans"); + trans.from_monitor_struct(fuse_ctrl_rst_in_monitor_struct); + trans.start_time = time_stamp; + trans.end_time = $time; + time_stamp = trans.end_time; + + analyze(trans); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_monitor_bfm.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_monitor_bfm.sv new file mode 100644 index 0000000..0e43766 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_monitor_bfm.sv @@ -0,0 +1,192 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface performs the fuse_ctrl_rst_in signal monitoring. +// It is accessed by the uvm fuse_ctrl_rst_in monitor through a virtual +// interface handle in the fuse_ctrl_rst_in configuration. It monitors the +// signals passed in through the port connection named bus of +// type fuse_ctrl_rst_in_if. +// +// Input signals from the fuse_ctrl_rst_in_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// Interface functions and tasks used by UVM components: +// monitor(inout TRANS_T txn); +// This task receives the transaction, txn, from the +// UVM monitor and then populates variables in txn +// from values observed on bus activity. This task +// blocks until an operation on the fuse_ctrl_rst_in bus is complete. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_rst_in_pkg_hdl::*; +`include "src/fuse_ctrl_rst_in_macros.svh" + + +interface fuse_ctrl_rst_in_monitor_bfm + ( fuse_ctrl_rst_in_if bus ); + // The pragma below and additional ones in-lined further down are for running this BFM on Veloce + // pragma attribute fuse_ctrl_rst_in_monitor_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: ", ), + UVM_DEBUG) +end +`endif + + + // Structure used to pass transaction data from monitor BFM to monitor class in agent. +`fuse_ctrl_rst_in_MONITOR_STRUCT + fuse_ctrl_rst_in_monitor_s fuse_ctrl_rst_in_monitor_struct; + + // Structure used to pass configuration data from monitor class to monitor BFM. + `fuse_ctrl_rst_in_CONFIGURATION_STRUCT + + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + tri clk_i_i; + tri rst_ni_i; + tri [$bits(pwrmgr_pkg::pwr_otp_req_t)-1:0] pwr_otp_i_i; + tri otp_ext_voltage_h_io_i; + assign clk_i_i = bus.clk_i; + assign rst_ni_i = bus.rst_ni; + assign pwr_otp_i_i = bus.pwr_otp_i; + assign otp_ext_voltage_h_io_i = bus.otp_ext_voltage_h_io; + + // Proxy handle to UVM monitor + fuse_ctrl_rst_in_pkg::fuse_ctrl_rst_in_monitor proxy; + // pragma tbx oneway proxy.notify_transaction + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + task wait_for_reset();// pragma tbx xtf + @(posedge clk_i_i) ; + do_wait_for_reset(); + endtask + + // **************************************************************************** + task do_wait_for_reset(); + // pragma uvmf custom reset_condition begin + wait ( rst_ni_i === 1 ) ; + @(posedge clk_i_i) ; + // pragma uvmf custom reset_condition end + endtask + + //****************************************************************** + + task wait_for_num_clocks(input int unsigned count); // pragma tbx xtf + @(posedge clk_i_i); + + repeat (count-1) @(posedge clk_i_i); + endtask + + //****************************************************************** + event go; + function void start_monitoring();// pragma tbx xtf + -> go; + endfunction + + // **************************************************************************** + initial begin + @go; + forever begin + @(posedge clk_i_i); + do_monitor( fuse_ctrl_rst_in_monitor_struct ); + + + proxy.notify_transaction( fuse_ctrl_rst_in_monitor_struct ); + + end + end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the monitor BFM. It is called by the monitor within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the monitor BFM needs to be aware of the new configuration + // variables. + // + function void configure(fuse_ctrl_rst_in_configuration_s fuse_ctrl_rst_in_configuration_arg); // pragma tbx xtf + initiator_responder = fuse_ctrl_rst_in_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + + + // **************************************************************************** + + task do_monitor(output fuse_ctrl_rst_in_monitor_s fuse_ctrl_rst_in_monitor_struct); + // + // Available struct members: + // // fuse_ctrl_rst_in_monitor_struct.assert_rst + // // fuse_ctrl_rst_in_monitor_struct.assert_otp_pwr_init + // // + // Reference code; + // How to wait for signal value + // while (control_signal === 1'b1) @(posedge clk_i_i); + // + // How to assign a struct member, named xyz, from a signal. + // All available input signals listed. + // fuse_ctrl_rst_in_monitor_struct.xyz = pwr_otp_i_i; // [$bits(pwrmgr_pkg::pwr_otp_req_t)-1:0] + // fuse_ctrl_rst_in_monitor_struct.xyz = otp_ext_voltage_h_io_i; // + // pragma uvmf custom do_monitor begin + // UVMF_CHANGE_ME : Implement protocol monitoring. The commented reference code + // below are examples of how to capture signal values and assign them to + // structure members. All available input signals are listed. The 'while' + // code example shows how to wait for a synchronous flow control signal. This + // task should return when a complete transfer has been observed. Once this task is + // exited with captured values, it is then called again to wait for and observe + // the next transfer. One clock cycle is consumed between calls to do_monitor. + @(posedge clk_i_i); + @(posedge clk_i_i); + @(posedge clk_i_i); + @(posedge clk_i_i); + // pragma uvmf custom do_monitor end + endtask + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_random_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_random_sequence.svh new file mode 100644 index 0000000..99ba931 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_random_sequence.svh @@ -0,0 +1,67 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This sequences randomizes the fuse_ctrl_rst_in transaction and sends it +// to the UVM driver. +// +// This sequence constructs and randomizes a fuse_ctrl_rst_in_transaction. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_rst_in_random_sequence + extends fuse_ctrl_rst_in_sequence_base ; + + `uvm_object_utils( fuse_ctrl_rst_in_random_sequence ) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //***************************************************************** + function new(string name = ""); + super.new(name); + endfunction: new + + // **************************************************************************** + // TASK : body() + // This task is automatically executed when this sequence is started using the + // start(sequencerHandle) task. + // + task body(); + + // Construct the transaction + req=fuse_ctrl_rst_in_transaction::type_id::create("req"); + start_item(req); + // Randomize the transaction + if(!req.randomize()) `uvm_fatal("SEQ", "fuse_ctrl_rst_in_random_sequence::body()-fuse_ctrl_rst_in_transaction randomization failed") + // Send the transaction to the fuse_ctrl_rst_in_driver_bfm via the sequencer and fuse_ctrl_rst_in_driver. + finish_item(req); + `uvm_info("SEQ", {"Response:",req.convert2string()},UVM_MEDIUM) + + endtask + +endclass: fuse_ctrl_rst_in_random_sequence + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_responder_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_responder_sequence.svh new file mode 100644 index 0000000..96f0fa3 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_responder_sequence.svh @@ -0,0 +1,63 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class can be used to provide stimulus when an interface +// has been configured to run in a responder mode. It +// will never finish by default, always going back to the driver +// and driver BFM for the next transaction with which to respond. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_rst_in_responder_sequence + extends fuse_ctrl_rst_in_sequence_base ; + + `uvm_object_utils( fuse_ctrl_rst_in_responder_sequence ) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "fuse_ctrl_rst_in_responder_sequence"); + super.new(name); + endfunction + + task body(); + req=fuse_ctrl_rst_in_transaction::type_id::create("req"); + forever begin + start_item(req); + finish_item(req); + // pragma uvmf custom body begin + // UVMF_CHANGE_ME : Do something here with the resulting req item. The + // finish_item() call above will block until the req transaction is ready + // to be handled by the responder sequence. + // If this was an item that required a response, the expectation is + // that the response should be populated within this transaction now. + `uvm_info("SEQ",$sformatf("Processed txn: %s",req.convert2string()),UVM_HIGH) + // pragma uvmf custom body end + end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_sequence_base.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_sequence_base.svh new file mode 100644 index 0000000..47c3b89 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_sequence_base.svh @@ -0,0 +1,110 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the class used as the base class for all sequences +// for this interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_rst_in_sequence_base extends uvmf_sequence_base #( + .REQ(fuse_ctrl_rst_in_transaction ), + .RSP(fuse_ctrl_rst_in_transaction )); + + `uvm_object_utils( fuse_ctrl_rst_in_sequence_base ) + + // variables + typedef fuse_ctrl_rst_in_transaction fuse_ctrl_rst_in_transaction_req_t; + fuse_ctrl_rst_in_transaction_req_t req; + typedef fuse_ctrl_rst_in_transaction fuse_ctrl_rst_in_transaction_rsp_t; + fuse_ctrl_rst_in_transaction_rsp_t rsp; + + // Event for identifying when a response was received from the sequencer + event new_rsp; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // TASK : get_responses() + // This task recursively gets sequence item responses from the sequencer. + // + virtual task get_responses(); + fork + begin + // Block until new rsp available + get_response(rsp); + // New rsp received. Indicate to sequence using event. + ->new_rsp; + // Display the received response transaction + `uvm_info("SEQ", {"New response transaction:",rsp.convert2string()}, UVM_MEDIUM) + end + join_none + endtask + + // **************************************************************************** + // TASK : pre_body() + // This task is called automatically when start is called with call_pre_post set to 1 (default). + // By calling get_responses() within pre_body() any derived sequences are automatically + // processing response transactions. Only un-comment this call to get_responses() if you + // have configured the interface driver to utilize the response transaction path by setting + // the configuration variable "return_transaction_response" to 1. Otherwise it is possible + // to impact runtime performance and memory utilization. + // + virtual task pre_body(); + // pragma uvmf custom pre_body begin +// get_responses(); + // pragma uvmf custom pre_body end + endtask + + // **************************************************************************** + // TASK : body() + // This task is called automatically when start is called. This sequence sends + // a req sequence item to the sequencer identified as an argument in the call + // to start. + // + virtual task body(); + // pragma uvmf custom body begin + start_item(req); + finish_item(req); + // pragma uvmf custom body end + endtask + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name =""); + super.new( name ); + // pragma uvmf custom new begin + req = fuse_ctrl_rst_in_transaction_req_t::type_id::create("req"); + rsp = fuse_ctrl_rst_in_transaction_rsp_t::type_id::create("rsp"); + // pragma uvmf custom new end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_transaction.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_transaction.svh new file mode 100644 index 0000000..83d7dbc --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_transaction.svh @@ -0,0 +1,198 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class defines the variables required for an fuse_ctrl_rst_in +// transaction. Class variables to be displayed in waveform transaction +// viewing are added to the transaction viewing stream in the add_to_wave +// function. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_rst_in_transaction extends uvmf_transaction_base; + + `uvm_object_utils( fuse_ctrl_rst_in_transaction ) + + bit assert_rst ; + bit assert_otp_pwr_init ; + + //Constraints for the transaction variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //******************************************************************* + //******************************************************************* + // Macros that define structs and associated functions are + // located in fuse_ctrl_rst_in_macros.svh + + //******************************************************************* + // Monitor macro used by fuse_ctrl_rst_in_monitor and fuse_ctrl_rst_in_monitor_bfm + // This struct is defined in fuse_ctrl_rst_in_macros.svh + `fuse_ctrl_rst_in_MONITOR_STRUCT + fuse_ctrl_rst_in_monitor_s fuse_ctrl_rst_in_monitor_struct; + //******************************************************************* + // FUNCTION: to_monitor_struct() + // This function packs transaction variables into a fuse_ctrl_rst_in_monitor_s + // structure. The function returns the handle to the fuse_ctrl_rst_in_monitor_struct. + // This function is defined in fuse_ctrl_rst_in_macros.svh + `fuse_ctrl_rst_in_TO_MONITOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_monitor_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_rst_in_macros.svh + `fuse_ctrl_rst_in_FROM_MONITOR_STRUCT_FUNCTION + + //******************************************************************* + // Initiator macro used by fuse_ctrl_rst_in_driver and fuse_ctrl_rst_in_driver_bfm + // to communicate initiator driven data to fuse_ctrl_rst_in_driver_bfm. + // This struct is defined in fuse_ctrl_rst_in_macros.svh + `fuse_ctrl_rst_in_INITIATOR_STRUCT + fuse_ctrl_rst_in_initiator_s fuse_ctrl_rst_in_initiator_struct; + //******************************************************************* + // FUNCTION: to_initiator_struct() + // This function packs transaction variables into a fuse_ctrl_rst_in_initiator_s + // structure. The function returns the handle to the fuse_ctrl_rst_in_initiator_struct. + // This function is defined in fuse_ctrl_rst_in_macros.svh + `fuse_ctrl_rst_in_TO_INITIATOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_initiator_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_rst_in_macros.svh + `fuse_ctrl_rst_in_FROM_INITIATOR_STRUCT_FUNCTION + + //******************************************************************* + // Responder macro used by fuse_ctrl_rst_in_driver and fuse_ctrl_rst_in_driver_bfm + // to communicate Responder driven data to fuse_ctrl_rst_in_driver_bfm. + // This struct is defined in fuse_ctrl_rst_in_macros.svh + `fuse_ctrl_rst_in_RESPONDER_STRUCT + fuse_ctrl_rst_in_responder_s fuse_ctrl_rst_in_responder_struct; + //******************************************************************* + // FUNCTION: to_responder_struct() + // This function packs transaction variables into a fuse_ctrl_rst_in_responder_s + // structure. The function returns the handle to the fuse_ctrl_rst_in_responder_struct. + // This function is defined in fuse_ctrl_rst_in_macros.svh + `fuse_ctrl_rst_in_TO_RESPONDER_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_responder_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_rst_in_macros.svh + `fuse_ctrl_rst_in_FROM_RESPONDER_STRUCT_FUNCTION + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + endfunction + + // **************************************************************************** + // FUNCTION: convert2string() + // This function converts all variables in this class to a single string for + // logfile reporting. + // + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + // UVMF_CHANGE_ME : Customize format if desired. + return $sformatf("assert_rst:0x%x assert_otp_pwr_init:0x%x ",assert_rst,assert_otp_pwr_init); + // pragma uvmf custom convert2string end + endfunction + + //******************************************************************* + // FUNCTION: do_print() + // This function is automatically called when the .print() function + // is called on this class. + // + virtual function void do_print(uvm_printer printer); + // pragma uvmf custom do_print begin + // UVMF_CHANGE_ME : Current contents of do_print allows for the use of UVM 1.1d, 1.2 or P1800.2. + // Update based on your own printing preference according to your preferred UVM version + $display(convert2string()); + // pragma uvmf custom do_print end + endfunction + + //******************************************************************* + // FUNCTION: do_compare() + // This function is automatically called when the .compare() function + // is called on this class. + // + virtual function bit do_compare (uvm_object rhs, uvm_comparer comparer); + fuse_ctrl_rst_in_transaction RHS; + if (!$cast(RHS,rhs)) return 0; + // pragma uvmf custom do_compare begin + // UVMF_CHANGE_ME : Eliminate comparison of variables not to be used for compare + return (super.do_compare(rhs,comparer) + ); + // pragma uvmf custom do_compare end + endfunction + + //******************************************************************* + // FUNCTION: do_copy() + // This function is automatically called when the .copy() function + // is called on this class. + // + virtual function void do_copy (uvm_object rhs); + fuse_ctrl_rst_in_transaction RHS; + assert($cast(RHS,rhs)); + // pragma uvmf custom do_copy begin + super.do_copy(rhs); + this.assert_rst = RHS.assert_rst; + this.assert_otp_pwr_init = RHS.assert_otp_pwr_init; + // pragma uvmf custom do_copy end + endfunction + + // **************************************************************************** + // FUNCTION: add_to_wave() + // This function is used to display variables in this class in the waveform + // viewer. The start_time and end_time variables must be set before this + // function is called. If the start_time and end_time variables are not set + // the transaction will be hidden at 0ns on the waveform display. + // + virtual function void add_to_wave(int transaction_viewing_stream_h); + `ifdef QUESTA + if (transaction_view_h == 0) begin + transaction_view_h = $begin_transaction(transaction_viewing_stream_h,"fuse_ctrl_rst_in_transaction",start_time); + end + super.add_to_wave(transaction_view_h); + // pragma uvmf custom add_to_wave begin + // UVMF_CHANGE_ME : Color can be applied to transaction entries based on content, example below + // case() + // 1 : $add_color(transaction_view_h,"red"); + // default : $add_color(transaction_view_h,"grey"); + // endcase + // UVMF_CHANGE_ME : Eliminate transaction variables not wanted in transaction viewing in the waveform viewer + $add_attribute(transaction_view_h,assert_rst,"assert_rst"); + $add_attribute(transaction_view_h,assert_otp_pwr_init,"assert_otp_pwr_init"); + // pragma uvmf custom add_to_wave end + $end_transaction(transaction_view_h,end_time); + $free_transaction(transaction_view_h); + `endif // QUESTA + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_transaction_coverage.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_transaction_coverage.svh new file mode 100644 index 0000000..32b88a0 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_transaction_coverage.svh @@ -0,0 +1,85 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class records fuse_ctrl_rst_in transaction information using +// a covergroup named fuse_ctrl_rst_in_transaction_cg. An instance of this +// coverage component is instantiated in the uvmf_parameterized_agent +// if the has_coverage flag is set. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_rst_in_transaction_coverage extends uvm_subscriber #(.T(fuse_ctrl_rst_in_transaction )); + + `uvm_component_utils( fuse_ctrl_rst_in_transaction_coverage ) + + T coverage_trans; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + covergroup fuse_ctrl_rst_in_transaction_cg; + // pragma uvmf custom covergroup begin + // UVMF_CHANGE_ME : Add coverage bins, crosses, exclusions, etc. according to coverage needs. + option.auto_bin_max=1024; + option.per_instance=1; + assert_rst: coverpoint coverage_trans.assert_rst; + assert_otp_pwr_init: coverpoint coverage_trans.assert_otp_pwr_init; + // pragma uvmf custom covergroup end + endgroup + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new(string name="", uvm_component parent=null); + super.new(name,parent); + fuse_ctrl_rst_in_transaction_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that transaction variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + endfunction + + // **************************************************************************** + // FUNCTION : build_phase() + // This function is the standard UVM build_phase. + // + function void build_phase(uvm_phase phase); + fuse_ctrl_rst_in_transaction_cg.set_inst_name($sformatf("fuse_ctrl_rst_in_transaction_cg_%s",get_full_name())); + endfunction + + // **************************************************************************** + // FUNCTION: write (T t) + // This function is automatically executed when a transaction arrives on the + // analysis_export. It copies values from the variables in the transaction + // to local variables used to collect functional coverage. + // + virtual function void write (T t); + `uvm_info("COV","Received transaction",UVM_HIGH); + coverage_trans = t; + fuse_ctrl_rst_in_transaction_cg.sample(); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_typedefs.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_typedefs.svh new file mode 100644 index 0000000..f2a7bdb --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_typedefs.svh @@ -0,0 +1,34 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the host server when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_typedefs_hdl.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_typedefs_hdl.svh new file mode 100644 index 0000000..0d58518 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_typedefs_hdl.svh @@ -0,0 +1,35 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the emulator when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/yaml/fuse_ctrl_rst_in_interface.yaml b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/yaml/fuse_ctrl_rst_in_interface.yaml new file mode 100644 index 0000000..6da6d45 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/yaml/fuse_ctrl_rst_in_interface.yaml @@ -0,0 +1,39 @@ +uvmf: + interfaces: + fuse_ctrl_rst_in: + clock: clk_i + config_constraints: [] + config_vars: [] + existing_library_component: 'True' + gen_inbound_streaming_driver: 'False' + hdl_pkg_parameters: [] + hdl_typedefs: [] + hvl_pkg_parameters: [] + hvl_typedefs: [] + parameters: [] + ports: + - dir: output + name: pwr_otp_i + reset_value: '''bz' + width: '[''$bits(pwrmgr_pkg::pwr_otp_req_t)'']' + - dir: inout + name: otp_ext_voltage_h_io + reset_value: '''bz' + width: '1' + reset: rst_ni + reset_assertion_level: 'False' + transaction_constraints: [] + transaction_vars: + - comment: '' + iscompare: 'False' + isrand: 'False' + name: assert_rst + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: assert_otp_pwr_init + type: bit + unpacked_dimension: '' + use_dpi_link: 'False' diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/.project b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/.project new file mode 100644 index 0000000..dfcfc9a --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/.project @@ -0,0 +1,30 @@ + + + fuse_ctrl_rst_out_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/.svproject b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/.svproject new file mode 100644 index 0000000..e389a42 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/Makefile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/Makefile new file mode 100644 index 0000000..cec1c89 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/Makefile @@ -0,0 +1,66 @@ +# fuse_ctrl_rst_out interface packages source +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +fuse_ctrl_rst_out_PKG = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_out_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_filelist_hvl.f + +fuse_ctrl_rst_out_PKG_HDL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_out_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_filelist_hdl.f + +fuse_ctrl_rst_out_PKG_XRTL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_out_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_filelist_xrtl.f + +COMP_fuse_ctrl_rst_out_PKG_TGT_0 = q_comp_fuse_ctrl_rst_out_pkg +COMP_fuse_ctrl_rst_out_PKG_TGT_1 = v_comp_fuse_ctrl_rst_out_pkg +COMP_fuse_ctrl_rst_out_PKG_TGT = $(COMP_fuse_ctrl_rst_out_PKG_TGT_$(USE_VELOCE)) + +comp_fuse_ctrl_rst_out_pkg: $(COMP_fuse_ctrl_rst_out_PKG_TGT) + +q_comp_fuse_ctrl_rst_out_pkg: + $(HDL_COMP_CMD) $(fuse_ctrl_rst_out_PKG_HDL) + $(HVL_COMP_CMD) $(fuse_ctrl_rst_out_PKG) + $(HDL_COMP_CMD) $(fuse_ctrl_rst_out_PKG_XRTL) + +v_comp_fuse_ctrl_rst_out_pkg: + $(HVL_COMP_CMD) $(fuse_ctrl_rst_out_PKG_HDL) + $(HVL_COMP_CMD) $(fuse_ctrl_rst_out_PKG) + $(VELANALYZE_CMD) $(fuse_ctrl_rst_out_PKG_HDL) + $(VELANALYZE_HVL_CMD) $(fuse_ctrl_rst_out_PKG) + $(HDL_COMP_CMD) $(fuse_ctrl_rst_out_PKG_XRTL) + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export fuse_ctrl_rst_out_IF_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_out_pkg/dpi + +C_FILE_COMPILE_LIST_fuse_ctrl_rst_out_pkg = \ + +O_FILE_COMPILE_LIST_fuse_ctrl_rst_out_pkg = $(notdir $(C_FILE_COMPILE_LIST_fuse_ctrl_rst_out_pkg:.c=.o)) + +GCC_COMP_ARGS_fuse_ctrl_rst_out_pkg += -I$(fuse_ctrl_rst_out_IF_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_fuse_ctrl_rst_out_pkg += $(fuse_ctrl_rst_out_IF_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_fuse_ctrl_rst_out_pkg += \ + \ + -o .so + +comp_fuse_ctrl_rst_out_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Interface C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_fuse_ctrl_rst_out_pkg) $(C_FILE_COMPILE_LIST_fuse_ctrl_rst_out_pkg) + @echo "--------------------------------" + @echo "Linking Interface C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_fuse_ctrl_rst_out_pkg) $(O_FILE_COMPILE_LIST_fuse_ctrl_rst_out_pkg) + @echo "--------------------------------" + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/compile.do b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/compile.do new file mode 100644 index 0000000..d9a26ba --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/compile.do @@ -0,0 +1,14 @@ +# Tcl do file for compile of fuse_ctrl_rst_out interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_out_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_filelist_hdl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_out_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_filelist_hvl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_out_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_filelist_xrtl.f \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out.compile new file mode 100644 index 0000000..d3c0b46 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out.compile @@ -0,0 +1,3 @@ +needs: + - fuse_ctrl_rst_out_hvl.compile + - fuse_ctrl_rst_out_hdl.compile diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_bfm.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_bfm.vinfo new file mode 100644 index 0000000..6c2d817 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_bfm.vinfo @@ -0,0 +1,6 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use fuse_ctrl_rst_out_pkg_hdl.vinfo ++incdir+@vinfodir +src/fuse_ctrl_rst_out_if.sv +src/fuse_ctrl_rst_out_driver_bfm.sv +src/fuse_ctrl_rst_out_monitor_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_common.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_common.compile new file mode 100644 index 0000000..f6f7480 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_common.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +incdir: + - . + - ${uvm_path}/src +src: + - fuse_ctrl_rst_out_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_filelist_hdl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_filelist_hdl.f new file mode 100644 index 0000000..a63bb95 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_filelist_hdl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_filelist_hvl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_filelist_hvl.f new file mode 100644 index 0000000..411a2c8 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_filelist_hvl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_pkg.sv \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_filelist_xrtl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_filelist_xrtl.f new file mode 100644 index 0000000..7fb91c0 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_filelist_xrtl.f @@ -0,0 +1,3 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_if.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_monitor_bfm.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_driver_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_hdl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_hdl.compile new file mode 100644 index 0000000..e4bbfcc --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_hdl.compile @@ -0,0 +1,9 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ./fuse_ctrl_rst_out_common.compile +incdir: + - . +src: + - src/fuse_ctrl_rst_out_if.sv + - src/fuse_ctrl_rst_out_monitor_bfm.sv + - src/fuse_ctrl_rst_out_driver_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_hvl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_hvl.compile new file mode 100644 index 0000000..71b0f73 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_hvl.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ./fuse_ctrl_rst_out_common.compile +incdir: + - . +src: + - fuse_ctrl_rst_out_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_pkg.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_pkg.sv new file mode 100644 index 0000000..114980c --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_pkg.sv @@ -0,0 +1,91 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - + +// - +// - +// - + +// - +// - +// - + +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_rst_out_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg_hdl::*; + import uvmf_base_pkg::*; + import fuse_ctrl_rst_out_pkg_hdl::*; + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + `include "src/fuse_ctrl_rst_out_macros.svh" + + export fuse_ctrl_rst_out_pkg_hdl::*; + + + + // Parameters defined as HVL parameters + + `include "src/fuse_ctrl_rst_out_typedefs.svh" + `include "src/fuse_ctrl_rst_out_transaction.svh" + + `include "src/fuse_ctrl_rst_out_configuration.svh" + `include "src/fuse_ctrl_rst_out_driver.svh" + `include "src/fuse_ctrl_rst_out_monitor.svh" + + `include "src/fuse_ctrl_rst_out_transaction_coverage.svh" + `include "src/fuse_ctrl_rst_out_sequence_base.svh" + `include "src/fuse_ctrl_rst_out_random_sequence.svh" + + `include "src/fuse_ctrl_rst_out_responder_sequence.svh" + `include "src/fuse_ctrl_rst_out2reg_adapter.svh" + + `include "src/fuse_ctrl_rst_out_agent.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new interface sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the interface package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_pkg.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_pkg.vinfo new file mode 100644 index 0000000..e117063 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_pkg.vinfo @@ -0,0 +1,4 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use fuse_ctrl_rst_out_pkg_hdl.vinfo ++incdir+@vinfodir +fuse_ctrl_rst_out_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_pkg_hdl.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_pkg_hdl.sv new file mode 100644 index 0000000..0dca9e6 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_pkg_hdl.sv @@ -0,0 +1,52 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that needs to be compiled and synthesized +// for running on Veloce. +// +// CONTAINS: +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_rst_out_pkg_hdl; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HDL parameters + + `include "src/fuse_ctrl_rst_out_typedefs_hdl.svh" + `include "src/fuse_ctrl_rst_out_macros.svh" + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_pkg_hdl.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_pkg_hdl.vinfo new file mode 100644 index 0000000..3d6a42b --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_pkg_hdl.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +fuse_ctrl_rst_out_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_pkg_sve.F b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_pkg_sve.F new file mode 100644 index 0000000..a4e1931 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_pkg_sve.F @@ -0,0 +1,10 @@ +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + ++incdir+. +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_filelist_hdl.f +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_filelist_hvl.f diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out2reg_adapter.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out2reg_adapter.svh new file mode 100644 index 0000000..ebcb194 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out2reg_adapter.svh @@ -0,0 +1,112 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the UVM register adapter for the fuse_ctrl_rst_out interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_rst_out2reg_adapter extends uvm_reg_adapter; + + `uvm_object_utils( fuse_ctrl_rst_out2reg_adapter ) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //-------------------------------------------------------------------- + // new + //-------------------------------------------------------------------- + function new (string name = "fuse_ctrl_rst_out2reg_adapter" ); + super.new(name); + // pragma uvmf custom new begin + // UVMF_CHANGE_ME : Configure the adapter regarding byte enables and provides response. + + // Does the protocol the Agent is modeling support byte enables? + // 0 = NO + // 1 = YES + supports_byte_enable = 0; + + // Does the Agent's Driver provide separate response sequence items? + // i.e. Does the driver call seq_item_port.put() + // and do the sequences call get_response()? + // 0 = NO + // 1 = YES + provides_responses = 0; + // pragma uvmf custom new end + + endfunction: new + + //-------------------------------------------------------------------- + // reg2bus + //-------------------------------------------------------------------- + virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw); + + fuse_ctrl_rst_out_transaction trans_h = fuse_ctrl_rst_out_transaction ::type_id::create("trans_h"); + + // pragma uvmf custom reg2bus begin + // UVMF_CHANGE_ME : Fill in the reg2bus adapter mapping registe fields to protocol fields. + + //Adapt the following for your sequence item type + // trans_h.op = (rw.kind == UVM_READ) ? WB_READ : WB_WRITE; + //Copy over address + // trans_h.addr = rw.addr; + //Copy over write data + // trans_h.data = rw.data; + + // pragma uvmf custom reg2bus end + + // Return the adapted transaction + return trans_h; + + endfunction: reg2bus + + //-------------------------------------------------------------------- + // bus2reg + //-------------------------------------------------------------------- + virtual function void bus2reg(uvm_sequence_item bus_item, + ref uvm_reg_bus_op rw); + fuse_ctrl_rst_out_transaction trans_h; + if (!$cast(trans_h, bus_item)) begin + `uvm_fatal("ADAPT","Provided bus_item is not of the correct type") + return; + end + // pragma uvmf custom bus2reg begin + // UVMF_CHANGE_ME : Fill in the bus2reg adapter mapping protocol fields to register fields. + //Adapt the following for your sequence item type + //Copy over instruction type + // rw.kind = (trans_h.op == WB_WRITE) ? UVM_WRITE : UVM_READ; + //Copy over address + // rw.addr = trans_h.addr; + //Copy over read data + // rw.data = trans_h.data; + //Check for errors on the bus and return UVM_NOT_OK if there is an error + // rw.status = UVM_IS_OK; + // pragma uvmf custom bus2reg end + + endfunction: bus2reg + +endclass : fuse_ctrl_rst_out2reg_adapter + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_agent.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_agent.svh new file mode 100644 index 0000000..72f514f --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_agent.svh @@ -0,0 +1,67 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: Protocol specific agent class definition +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_rst_out_agent extends uvmf_parameterized_agent #( + .CONFIG_T(fuse_ctrl_rst_out_configuration ), + .DRIVER_T(fuse_ctrl_rst_out_driver ), + .MONITOR_T(fuse_ctrl_rst_out_monitor ), + .COVERAGE_T(fuse_ctrl_rst_out_transaction_coverage ), + .TRANS_T(fuse_ctrl_rst_out_transaction ) + ); + + `uvm_component_utils( fuse_ctrl_rst_out_agent ) + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** + // FUNCTION: build_phase + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + if (configuration.active_passive == ACTIVE) begin + // Place sequencer handle into configuration object + // so that it may be retrieved from configuration + // rather than using uvm_config_db + configuration.sequencer = this.sequencer; + end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_configuration.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_configuration.svh new file mode 100644 index 0000000..cc1788a --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_configuration.svh @@ -0,0 +1,193 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class contains all variables and functions used +// to configure the fuse_ctrl_rst_out agent and its bfm's. It gets the +// bfm's from the uvm_config_db for use by the agent. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_rst_out_configuration extends uvmf_parameterized_agent_configuration_base #( + .DRIVER_BFM_BIND_T(virtual fuse_ctrl_rst_out_driver_bfm ), + .MONITOR_BFM_BIND_T( virtual fuse_ctrl_rst_out_monitor_bfm )); + + `uvm_object_utils( fuse_ctrl_rst_out_configuration ) + + + // Sequencer handle populated by agent + uvm_sequencer #(fuse_ctrl_rst_out_transaction ) sequencer; + + //Constraints for the configuration variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + covergroup fuse_ctrl_rst_out_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + // pragma uvmf custom covergroup end + endgroup + + //******************************************************************* + //******************************************************************* + // Structure used to pass configuration variables to monitor and driver BFM's. + // Use to_struct function to pack variables into structure. + // Use from_struct function to unpack variables from structure. + // This structure is defined in fuse_ctrl_rst_out_macros.svh + `fuse_ctrl_rst_out_CONFIGURATION_STRUCT + fuse_ctrl_rst_out_configuration_s fuse_ctrl_rst_out_configuration_struct; + //******************************************************************* + // FUNCTION: to_struct() + // This function packs variables into a fuse_ctrl_rst_out_configuration_s + // structure. The function returns the handle to the fuse_ctrl_rst_out_configuration_struct. + // This function is defined in fuse_ctrl_rst_out_macros.svh + `fuse_ctrl_rst_out_CONFIGURATION_TO_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_struct() + // This function unpacks the struct provided as an argument into + // variables of this class. + // This function is defined in fuse_ctrl_rst_out_macros.svh + `fuse_ctrl_rst_out_CONFIGURATION_FROM_STRUCT_FUNCTION + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + // Construct the covergroup for this configuration class + fuse_ctrl_rst_out_configuration_cg = new; + endfunction + + // **************************************************************************** + // FUNCTION: post_randomize() + // This function is automatically called after the randomize() function + // is executed. + // + function void post_randomize(); + super.post_randomize(); + fuse_ctrl_rst_out_configuration_cg.sample(); + endfunction + + // **************************************************************************** + // FUNCTION: initialize + // This function causes the configuration to retrieve + // its virtual interface handle from the uvm_config_db. + // This function also makes itself available to its + // agent through the uvm_config_db. + // + // ARGUMENTS: + // uvmf_active_passive_t activity: + // This argument identifies the simulation level + // as either BLOCK, CHIP, SIMULATION, etc. + // + // AGENT_PATH: + // This argument identifies the path to this + // configurations agent. This configuration + // makes itself available to the agent specified + // by agent_path by placing itself into the + // uvm_config_db. + // + // INTERFACE_NAME: + // This argument identifies the string name of + // this configurations BFM's. This string + // name is used to retrieve the driver and + // monitor BFM from the uvm_config_db. + // + virtual function void initialize(uvmf_active_passive_t activity, + string agent_path, + string interface_name); + + super.initialize( activity, agent_path, interface_name); + // The covergroup is given the same name as the interface + fuse_ctrl_rst_out_configuration_cg.set_inst_name(interface_name); + + // This configuration places itself into the uvm_config_db for the agent, identified by the agent_path variable, to retrieve. + uvm_config_db #( fuse_ctrl_rst_out_configuration + )::set( null ,agent_path,UVMF_AGENT_CONFIG, this ); + + // This configuration also places itself in the config db using the same identifier used by the interface. This allows users to access + // configuration variables and the interface through the bfm api class rather than directly accessing the BFM. This is useful for + // accessingthe BFM when using Veloce + uvm_config_db #( fuse_ctrl_rst_out_configuration + )::set( null ,UVMF_CONFIGURATIONS, interface_name, this ); + + fuse_ctrl_rst_out_configuration_cg.set_inst_name($sformatf("fuse_ctrl_rst_out_configuration_cg_%s",get_full_name())); + +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. + `uvm_info("CFG", + $psprintf("The agent at '%s' is using interface named %s has the following parameters: ", agent_path, interface_name, ), + UVM_DEBUG) + + // pragma uvmf custom initialize begin + // This controls whether or not the agent returns a transaction handle in the driver when calling + // item_done() back into the sequencer or not. If set to 1, a transaction is sent back which means + // the sequence on the other end must use the get_response() part of the driver/sequence API. If + // this doesn't occur, there will eventually be response_queue overflow errors during the test. + return_transaction_response = 1'b0; + + // pragma uvmf custom initialize end + + endfunction + + // **************************************************************************** + // TASK: wait_for_reset + // *[Required]* Blocks until reset is released. The wait_for_reset operation is performed + // by a task in the monitor bfm. + virtual task wait_for_reset(); + monitor_bfm.wait_for_reset(); + endtask + + // **************************************************************************** + // TASK: wait_for_num_clocks + // *[Required]* Blocks until specified number of clocks have elapsed. The wait_for_num_clocks + // operation is performed by a task in the monitor bfm. + virtual task wait_for_num_clocks(int clocks); + monitor_bfm.wait_for_num_clocks(clocks); + endtask + + // **************************************************************************** + // FUNCTION : convert2string() + // This function is used to convert variables in this class into a string for log messaging. + // + virtual function string convert2string (); + // pragma uvmf custom convert2string begin + return $sformatf(""); + // pragma uvmf custom convert2string end + endfunction + + // **************************************************************************** + // FUNCTION: get_sequencer + function uvm_sequencer #(fuse_ctrl_rst_out_transaction) get_sequencer(); + return sequencer; + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_driver.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_driver.svh new file mode 100644 index 0000000..6b15dc2 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_driver.svh @@ -0,0 +1,105 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class passes transactions between the sequencer +// and the BFM driver interface. It accesses the driver BFM +// through the bfm handle. This driver +// passes transactions to the driver BFM through the access +// task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_rst_out_driver extends uvmf_driver_base #( + .CONFIG_T(fuse_ctrl_rst_out_configuration ), + .BFM_BIND_T(virtual fuse_ctrl_rst_out_driver_bfm ), + .REQ(fuse_ctrl_rst_out_transaction ), + .RSP(fuse_ctrl_rst_out_transaction )); + + `uvm_component_utils( fuse_ctrl_rst_out_driver ) +//******************************************************************* +// Macros that define structs located in fuse_ctrl_rst_out_macros.svh +//******************************************************************* +// Initiator macro used by fuse_ctrl_rst_out_driver and fuse_ctrl_rst_out_driver_bfm +// to communicate initiator driven data to fuse_ctrl_rst_out_driver_bfm. +`fuse_ctrl_rst_out_INITIATOR_STRUCT + fuse_ctrl_rst_out_initiator_s fuse_ctrl_rst_out_initiator_struct; +//******************************************************************* +// Responder macro used by fuse_ctrl_rst_out_driver and fuse_ctrl_rst_out_driver_bfm +// to communicate Responder driven data to fuse_ctrl_rst_out_driver_bfm. +`fuse_ctrl_rst_out_RESPONDER_STRUCT + fuse_ctrl_rst_out_responder_s fuse_ctrl_rst_out_responder_struct; + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent=null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the driver BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// driver BFM. This allows the driver BFM to call tasks and function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// **************************************************************************** +// This task is called by the run_phase in uvmf_driver_base. + virtual task access( inout REQ txn ); +// pragma uvmf custom access begin + if (configuration.initiator_responder==RESPONDER) begin + // Complete current transfer and wait for next transfer + bfm.respond_and_wait_for_next_transfer( + fuse_ctrl_rst_out_initiator_struct, + txn.to_responder_struct() + ); + // Unpack information about initiated transfer received by this responder + txn.from_initiator_struct(fuse_ctrl_rst_out_initiator_struct); + end else begin + // Initiate a transfer and get response + bfm.initiate_and_get_response( + txn.to_initiator_struct(), + fuse_ctrl_rst_out_responder_struct + ); + // Unpack transfer response information received by this initiator + txn.from_responder_struct(fuse_ctrl_rst_out_responder_struct); + end +// pragma uvmf custom access end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_driver_bfm.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_driver_bfm.sv new file mode 100644 index 0000000..b66cf3d --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_driver_bfm.sv @@ -0,0 +1,294 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This interface performs the fuse_ctrl_rst_out signal driving. It is +// accessed by the uvm fuse_ctrl_rst_out driver through a virtual interface +// handle in the fuse_ctrl_rst_out configuration. It drives the singals passed +// in through the port connection named bus of type fuse_ctrl_rst_out_if. +// +// Input signals from the fuse_ctrl_rst_out_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// This bfm drives signals with a _o suffix. These signals +// are driven onto signals within fuse_ctrl_rst_out_if based on INITIATOR/RESPONDER and/or +// ARBITRATION/GRANT status. +// +// The output signal connections are as follows: +// signal_o -> bus.signal +// +// +// Interface functions and tasks used by UVM components: +// +// configure: +// This function gets configuration attributes from the +// UVM driver to set any required BFM configuration +// variables such as 'initiator_responder'. +// +// initiate_and_get_response: +// This task is used to perform signaling activity for initiating +// a protocol transfer. The task initiates the transfer, using +// input data from the initiator struct. Then the task captures +// response data, placing the data into the response struct. +// The response struct is returned to the driver class. +// +// respond_and_wait_for_next_transfer: +// This task is used to complete a current transfer as a responder +// and then wait for the initiator to start the next transfer. +// The task uses data in the responder struct to drive protocol +// signals to complete the transfer. The task then waits for +// the next transfer. Once the next transfer begins, data from +// the initiator is placed into the initiator struct and sent +// to the responder sequence for processing to determine +// what data to respond with. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_rst_out_pkg_hdl::*; +`include "src/fuse_ctrl_rst_out_macros.svh" + +interface fuse_ctrl_rst_out_driver_bfm + (fuse_ctrl_rst_out_if bus); + // The following pragma and additional ones in-lined further below are for running this BFM on Veloce + // pragma attribute fuse_ctrl_rst_out_driver_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: ", ), + UVM_DEBUG) +end +`endif + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + tri clk_i_i; + tri rst_ni_i; + + // Signal list (all signals are capable of being inputs and outputs for the sake + // of supporting both INITIATOR and RESPONDER mode operation. Expectation is that + // directionality in the config file was from the point-of-view of the INITIATOR + + // INITIATOR mode input signals + tri [$bits(pwrmgr_pkg::pwr_otp_rsp_t)-1:0] pwr_otp_o_i; + reg [$bits(pwrmgr_pkg::pwr_otp_rsp_t)-1:0] pwr_otp_o_o = 'bz; + + // INITIATOR mode output signals + + // Bi-directional signals + tri otp_ext_voltage_h_io_i; + reg otp_ext_voltage_h_io_o = 'bz; + + + assign clk_i_i = bus.clk_i; + assign rst_ni_i = bus.rst_ni; + + // These are signals marked as 'input' by the config file, but the signals will be + // driven by this BFM if put into RESPONDER mode (flipping all signal directions around) + assign pwr_otp_o_i = bus.pwr_otp_o; + assign bus.pwr_otp_o = (initiator_responder == RESPONDER) ? pwr_otp_o_o : 'bz; + + assign otp_ext_voltage_h_io_i = bus.otp_ext_voltage_h_io; + + // These are signals marked as 'output' by the config file, but the outputs will + // not be driven by this BFM unless placed in INITIATOR mode. + assign bus.otp_ext_voltage_h_io = otp_ext_voltage_h_io_o; + + // Proxy handle to UVM driver + fuse_ctrl_rst_out_pkg::fuse_ctrl_rst_out_driver proxy; + // pragma tbx oneway proxy.my_function_name_in_uvm_driver + + // **************************************************************************** + // **************************************************************************** + // Macros that define structs located in fuse_ctrl_rst_out_macros.svh + // **************************************************************************** + // Struct for passing configuration data from fuse_ctrl_rst_out_driver to this BFM + // **************************************************************************** + `fuse_ctrl_rst_out_CONFIGURATION_STRUCT + // **************************************************************************** + // Structs for INITIATOR and RESPONDER data flow + //******************************************************************* + // Initiator macro used by fuse_ctrl_rst_out_driver and fuse_ctrl_rst_out_driver_bfm + // to communicate initiator driven data to fuse_ctrl_rst_out_driver_bfm. + `fuse_ctrl_rst_out_INITIATOR_STRUCT + fuse_ctrl_rst_out_initiator_s initiator_struct; + // Responder macro used by fuse_ctrl_rst_out_driver and fuse_ctrl_rst_out_driver_bfm + // to communicate Responder driven data to fuse_ctrl_rst_out_driver_bfm. + `fuse_ctrl_rst_out_RESPONDER_STRUCT + fuse_ctrl_rst_out_responder_s responder_struct; + + // **************************************************************************** +// pragma uvmf custom reset_condition_and_response begin + // Always block used to return signals to reset value upon assertion of reset + always @( negedge rst_ni_i ) + begin + // RESPONDER mode output signals + pwr_otp_o_o <= 'bz; + // INITIATOR mode output signals + // Bi-directional signals + otp_ext_voltage_h_io_o <= 'bz; + + end +// pragma uvmf custom reset_condition_and_response end + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the driver BFM. It is called by the driver within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the driver BFM needs to be aware of the new configuration + // variables. + // + + function void configure(fuse_ctrl_rst_out_configuration_s fuse_ctrl_rst_out_configuration_arg); // pragma tbx xtf + initiator_responder = fuse_ctrl_rst_out_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + +// pragma uvmf custom initiate_and_get_response begin +// **************************************************************************** +// UVMF_CHANGE_ME +// This task is used by an initator. The task first initiates a transfer then +// waits for the responder to complete the transfer. + task initiate_and_get_response( + // This argument passes transaction variables used by an initiator + // to perform the initial part of a protocol transfer. The values + // come from a sequence item created in a sequence. + input fuse_ctrl_rst_out_initiator_s fuse_ctrl_rst_out_initiator_struct, + // This argument is used to send data received from the responder + // back to the sequence item. The sequence item is returned to the sequence. + output fuse_ctrl_rst_out_responder_s fuse_ctrl_rst_out_responder_struct + );// pragma tbx xtf + // + // Members within the fuse_ctrl_rst_out_initiator_struct: + // pwrmgr_pkg::pwr_otp_rsp_t pwr_otp_o ; + // Members within the fuse_ctrl_rst_out_responder_struct: + // pwrmgr_pkg::pwr_otp_rsp_t pwr_otp_o ; + initiator_struct = fuse_ctrl_rst_out_initiator_struct; + // + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clk_i_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available initiator input and inout signals listed. + // Initiator input signals + // fuse_ctrl_rst_out_responder_struct.xyz = pwr_otp_o_i; // [$bits(pwrmgr_pkg::pwr_otp_rsp_t)-1:0] + // Initiator inout signals + // fuse_ctrl_rst_out_responder_struct.xyz = otp_ext_voltage_h_io_i; // + // How to assign a signal from an initiator struct member named xyz. + // All available initiator output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Initiator output signals + // Initiator inout signals + // otp_ext_voltage_h_io_o <= fuse_ctrl_rst_out_initiator_struct.xyz; // + // Initiate a transfer using the data received. + @(posedge clk_i_i); + @(posedge clk_i_i); + // Wait for the responder to complete the transfer then place the responder data into + // fuse_ctrl_rst_out_responder_struct. + @(posedge clk_i_i); + @(posedge clk_i_i); + responder_struct = fuse_ctrl_rst_out_responder_struct; + endtask +// pragma uvmf custom initiate_and_get_response end + +// pragma uvmf custom respond_and_wait_for_next_transfer begin +// **************************************************************************** +// The first_transfer variable is used to prevent completing a transfer in the +// first call to this task. For the first call to this task, there is not +// current transfer to complete. +bit first_transfer=1; + +// UVMF_CHANGE_ME +// This task is used by a responder. The task first completes the current +// transfer in progress then waits for the initiator to start the next transfer. + task respond_and_wait_for_next_transfer( + // This argument is used to send data received from the initiator + // back to the sequence item. The sequence determines how to respond. + output fuse_ctrl_rst_out_initiator_s fuse_ctrl_rst_out_initiator_struct, + // This argument passes transaction variables used by a responder + // to complete a protocol transfer. The values come from a sequence item. + input fuse_ctrl_rst_out_responder_s fuse_ctrl_rst_out_responder_struct + );// pragma tbx xtf + // Variables within the fuse_ctrl_rst_out_initiator_struct: + // pwrmgr_pkg::pwr_otp_rsp_t pwr_otp_o ; + // Variables within the fuse_ctrl_rst_out_responder_struct: + // pwrmgr_pkg::pwr_otp_rsp_t pwr_otp_o ; + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clk_i_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available responder input and inout signals listed. + // Responder input signals + // Responder inout signals + // fuse_ctrl_rst_out_responder_struct.xyz = otp_ext_voltage_h_io_i; // + // How to assign a signal, named xyz, from an initiator struct member. + // All available responder output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Responder output signals + // pwr_otp_o_o <= fuse_ctrl_rst_out_initiator_struct.xyz; // [$bits(pwrmgr_pkg::pwr_otp_rsp_t)-1:0] + // Responder inout signals + // otp_ext_voltage_h_io_o <= fuse_ctrl_rst_out_initiator_struct.xyz; // + + @(posedge clk_i_i); + if (!first_transfer) begin + // Perform transfer response here. + // Reply using data recieved in the fuse_ctrl_rst_out_responder_struct. + @(posedge clk_i_i); + // Reply using data recieved in the transaction handle. + @(posedge clk_i_i); + end + // Wait for next transfer then gather info from intiator about the transfer. + // Place the data into the fuse_ctrl_rst_out_initiator_struct. + @(posedge clk_i_i); + @(posedge clk_i_i); + first_transfer = 0; + endtask +// pragma uvmf custom respond_and_wait_for_next_transfer end + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_if.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_if.sv new file mode 100644 index 0000000..d510f9f --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_if.sv @@ -0,0 +1,83 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface contains the fuse_ctrl_rst_out interface signals. +// It is instantiated once per fuse_ctrl_rst_out bus. Bus Functional Models, +// BFM's named fuse_ctrl_rst_out_driver_bfm, are used to drive signals on the bus. +// BFM's named fuse_ctrl_rst_out_monitor_bfm are used to monitor signals on the +// bus. This interface signal bundle is passed in the port list of +// the BFM in order to give the BFM access to the signals in this +// interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// This template can be used to connect a DUT to these signals +// +// .dut_signal_port(fuse_ctrl_rst_out_bus.pwr_otp_o), // Agent input +// .dut_signal_port(fuse_ctrl_rst_out_bus.otp_ext_voltage_h_io), // Agent inout + +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_rst_out_pkg_hdl::*; + +interface fuse_ctrl_rst_out_if + + ( + input tri clk_i, + input tri rst_ni, + inout tri [$bits(pwrmgr_pkg::pwr_otp_rsp_t)-1:0] pwr_otp_o, + inout tri otp_ext_voltage_h_io + ); + +modport monitor_port + ( + input clk_i, + input rst_ni, + input pwr_otp_o, + input otp_ext_voltage_h_io + ); + +modport initiator_port + ( + input clk_i, + input rst_ni, + input pwr_otp_o, + inout otp_ext_voltage_h_io + ); + +modport responder_port + ( + input clk_i, + input rst_ni, + output pwr_otp_o, + inout otp_ext_voltage_h_io + ); + + +// pragma uvmf custom interface_item_additional begin +// pragma uvmf custom interface_item_additional end + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_infact_coverage_strategy.csv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_infact_coverage_strategy.csv new file mode 100644 index 0000000..1c218e1 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_infact_coverage_strategy.csv @@ -0,0 +1,6 @@ +Global +auto_bin_max, 64 + +Name,Type,Include +rand_fields,coverpoint,=rand *.** + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_macros.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_macros.svh new file mode 100644 index 0000000..244a2c7 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_macros.svh @@ -0,0 +1,135 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains macros used with the fuse_ctrl_rst_out package. +// These macros include packed struct definitions. These structs are +// used to pass data between classes, hvl, and BFM's, hdl. Use of +// structs are more efficient and simpler to modify. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_struct +// and from_struct methods defined in the macros below that are used in +// the fuse_ctrl_rst_out_configuration class. +// + `define fuse_ctrl_rst_out_CONFIGURATION_STRUCT \ +typedef struct packed { \ + uvmf_active_passive_t active_passive; \ + uvmf_initiator_responder_t initiator_responder; \ + } fuse_ctrl_rst_out_configuration_s; + + `define fuse_ctrl_rst_out_CONFIGURATION_TO_STRUCT_FUNCTION \ + virtual function fuse_ctrl_rst_out_configuration_s to_struct();\ + fuse_ctrl_rst_out_configuration_struct = \ + {\ + this.active_passive,\ + this.initiator_responder\ + };\ + return ( fuse_ctrl_rst_out_configuration_struct );\ + endfunction + + `define fuse_ctrl_rst_out_CONFIGURATION_FROM_STRUCT_FUNCTION \ + virtual function void from_struct(fuse_ctrl_rst_out_configuration_s fuse_ctrl_rst_out_configuration_struct);\ + {\ + this.active_passive,\ + this.initiator_responder \ + } = fuse_ctrl_rst_out_configuration_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_monitor_struct +// and from_monitor_struct methods of the fuse_ctrl_rst_out_transaction class. +// + `define fuse_ctrl_rst_out_MONITOR_STRUCT typedef struct packed { \ + pwrmgr_pkg::pwr_otp_rsp_t pwr_otp_o ; \ + } fuse_ctrl_rst_out_monitor_s; + + `define fuse_ctrl_rst_out_TO_MONITOR_STRUCT_FUNCTION \ + virtual function fuse_ctrl_rst_out_monitor_s to_monitor_struct();\ + fuse_ctrl_rst_out_monitor_struct = \ + { \ + this.pwr_otp_o \ + };\ + return ( fuse_ctrl_rst_out_monitor_struct);\ + endfunction\ + + `define fuse_ctrl_rst_out_FROM_MONITOR_STRUCT_FUNCTION \ + virtual function void from_monitor_struct(fuse_ctrl_rst_out_monitor_s fuse_ctrl_rst_out_monitor_struct);\ + {\ + this.pwr_otp_o \ + } = fuse_ctrl_rst_out_monitor_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_initiator_struct +// and from_initiator_struct methods of the fuse_ctrl_rst_out_transaction class. +// Also update the comments in the driver BFM. +// + `define fuse_ctrl_rst_out_INITIATOR_STRUCT typedef struct packed { \ + pwrmgr_pkg::pwr_otp_rsp_t pwr_otp_o ; \ + } fuse_ctrl_rst_out_initiator_s; + + `define fuse_ctrl_rst_out_TO_INITIATOR_STRUCT_FUNCTION \ + virtual function fuse_ctrl_rst_out_initiator_s to_initiator_struct();\ + fuse_ctrl_rst_out_initiator_struct = \ + {\ + this.pwr_otp_o \ + };\ + return ( fuse_ctrl_rst_out_initiator_struct);\ + endfunction + + `define fuse_ctrl_rst_out_FROM_INITIATOR_STRUCT_FUNCTION \ + virtual function void from_initiator_struct(fuse_ctrl_rst_out_initiator_s fuse_ctrl_rst_out_initiator_struct);\ + {\ + this.pwr_otp_o \ + } = fuse_ctrl_rst_out_initiator_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_responder_struct +// and from_responder_struct methods of the fuse_ctrl_rst_out_transaction class. +// Also update the comments in the driver BFM. +// + `define fuse_ctrl_rst_out_RESPONDER_STRUCT typedef struct packed { \ + pwrmgr_pkg::pwr_otp_rsp_t pwr_otp_o ; \ + } fuse_ctrl_rst_out_responder_s; + + `define fuse_ctrl_rst_out_TO_RESPONDER_STRUCT_FUNCTION \ + virtual function fuse_ctrl_rst_out_responder_s to_responder_struct();\ + fuse_ctrl_rst_out_responder_struct = \ + {\ + this.pwr_otp_o \ + };\ + return ( fuse_ctrl_rst_out_responder_struct);\ + endfunction + + `define fuse_ctrl_rst_out_FROM_RESPONDER_STRUCT_FUNCTION \ + virtual function void from_responder_struct(fuse_ctrl_rst_out_responder_s fuse_ctrl_rst_out_responder_struct);\ + {\ + this.pwr_otp_o \ + } = fuse_ctrl_rst_out_responder_struct;\ + endfunction +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_monitor.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_monitor.svh new file mode 100644 index 0000000..22093ba --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_monitor.svh @@ -0,0 +1,101 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class receives fuse_ctrl_rst_out transactions observed by the +// fuse_ctrl_rst_out monitor BFM and broadcasts them through the analysis port +// on the agent. It accesses the monitor BFM through the monitor +// task. This UVM component captures transactions +// for viewing in the waveform viewer if the +// enable_transaction_viewing flag is set in the configuration. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_rst_out_monitor extends uvmf_monitor_base #( + .CONFIG_T(fuse_ctrl_rst_out_configuration ), + .BFM_BIND_T(virtual fuse_ctrl_rst_out_monitor_bfm ), + .TRANS_T(fuse_ctrl_rst_out_transaction )); + + `uvm_component_utils( fuse_ctrl_rst_out_monitor ) + +// Structure used to pass data from monitor BFM to monitor class in agent. +// Use to_monitor_struct function to pack transaction variables into structure. +// Use from_monitor_struct function to unpack transaction variables from structure. +`fuse_ctrl_rst_out_MONITOR_STRUCT + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the monitor BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// monitor BFM. This allows the monitor BFM to call the notify_transaction +// function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// *************************************************************************** + virtual task run_phase(uvm_phase phase); + // Start monitor BFM thread and don't call super.run() in order to + // override the default monitor proxy 'pull' behavior with the more + // emulation-friendly BFM 'push' approach using the notify_transaction + // function below + bfm.start_monitoring(); + endtask + +// ************************************************************************** + +// This function is called by the monitor BFM. It receives data observed by the +// monitor BFM. Data is passed using the fuse_ctrl_rst_out_monitor_struct. + virtual function void notify_transaction(input fuse_ctrl_rst_out_monitor_s fuse_ctrl_rst_out_monitor_struct); + + + trans = new("trans"); + trans.from_monitor_struct(fuse_ctrl_rst_out_monitor_struct); + trans.start_time = time_stamp; + trans.end_time = $time; + time_stamp = trans.end_time; + + analyze(trans); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_monitor_bfm.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_monitor_bfm.sv new file mode 100644 index 0000000..596760d --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_monitor_bfm.sv @@ -0,0 +1,191 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface performs the fuse_ctrl_rst_out signal monitoring. +// It is accessed by the uvm fuse_ctrl_rst_out monitor through a virtual +// interface handle in the fuse_ctrl_rst_out configuration. It monitors the +// signals passed in through the port connection named bus of +// type fuse_ctrl_rst_out_if. +// +// Input signals from the fuse_ctrl_rst_out_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// Interface functions and tasks used by UVM components: +// monitor(inout TRANS_T txn); +// This task receives the transaction, txn, from the +// UVM monitor and then populates variables in txn +// from values observed on bus activity. This task +// blocks until an operation on the fuse_ctrl_rst_out bus is complete. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_rst_out_pkg_hdl::*; +`include "src/fuse_ctrl_rst_out_macros.svh" + + +interface fuse_ctrl_rst_out_monitor_bfm + ( fuse_ctrl_rst_out_if bus ); + // The pragma below and additional ones in-lined further down are for running this BFM on Veloce + // pragma attribute fuse_ctrl_rst_out_monitor_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: ", ), + UVM_DEBUG) +end +`endif + + + // Structure used to pass transaction data from monitor BFM to monitor class in agent. +`fuse_ctrl_rst_out_MONITOR_STRUCT + fuse_ctrl_rst_out_monitor_s fuse_ctrl_rst_out_monitor_struct; + + // Structure used to pass configuration data from monitor class to monitor BFM. + `fuse_ctrl_rst_out_CONFIGURATION_STRUCT + + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + tri clk_i_i; + tri rst_ni_i; + tri [$bits(pwrmgr_pkg::pwr_otp_rsp_t)-1:0] pwr_otp_o_i; + tri otp_ext_voltage_h_io_i; + assign clk_i_i = bus.clk_i; + assign rst_ni_i = bus.rst_ni; + assign pwr_otp_o_i = bus.pwr_otp_o; + assign otp_ext_voltage_h_io_i = bus.otp_ext_voltage_h_io; + + // Proxy handle to UVM monitor + fuse_ctrl_rst_out_pkg::fuse_ctrl_rst_out_monitor proxy; + // pragma tbx oneway proxy.notify_transaction + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + task wait_for_reset();// pragma tbx xtf + @(posedge clk_i_i) ; + do_wait_for_reset(); + endtask + + // **************************************************************************** + task do_wait_for_reset(); + // pragma uvmf custom reset_condition begin + wait ( rst_ni_i === 1 ) ; + @(posedge clk_i_i) ; + // pragma uvmf custom reset_condition end + endtask + + //****************************************************************** + + task wait_for_num_clocks(input int unsigned count); // pragma tbx xtf + @(posedge clk_i_i); + + repeat (count-1) @(posedge clk_i_i); + endtask + + //****************************************************************** + event go; + function void start_monitoring();// pragma tbx xtf + -> go; + endfunction + + // **************************************************************************** + initial begin + @go; + forever begin + @(posedge clk_i_i); + do_monitor( fuse_ctrl_rst_out_monitor_struct ); + + + proxy.notify_transaction( fuse_ctrl_rst_out_monitor_struct ); + + end + end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the monitor BFM. It is called by the monitor within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the monitor BFM needs to be aware of the new configuration + // variables. + // + function void configure(fuse_ctrl_rst_out_configuration_s fuse_ctrl_rst_out_configuration_arg); // pragma tbx xtf + initiator_responder = fuse_ctrl_rst_out_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + + + // **************************************************************************** + + task do_monitor(output fuse_ctrl_rst_out_monitor_s fuse_ctrl_rst_out_monitor_struct); + // + // Available struct members: + // // fuse_ctrl_rst_out_monitor_struct.pwr_otp_o + // // + // Reference code; + // How to wait for signal value + // while (control_signal === 1'b1) @(posedge clk_i_i); + // + // How to assign a struct member, named xyz, from a signal. + // All available input signals listed. + // fuse_ctrl_rst_out_monitor_struct.xyz = pwr_otp_o_i; // [$bits(pwrmgr_pkg::pwr_otp_rsp_t)-1:0] + // fuse_ctrl_rst_out_monitor_struct.xyz = otp_ext_voltage_h_io_i; // + // pragma uvmf custom do_monitor begin + // UVMF_CHANGE_ME : Implement protocol monitoring. The commented reference code + // below are examples of how to capture signal values and assign them to + // structure members. All available input signals are listed. The 'while' + // code example shows how to wait for a synchronous flow control signal. This + // task should return when a complete transfer has been observed. Once this task is + // exited with captured values, it is then called again to wait for and observe + // the next transfer. One clock cycle is consumed between calls to do_monitor. + @(posedge clk_i_i); + @(posedge clk_i_i); + @(posedge clk_i_i); + @(posedge clk_i_i); + // pragma uvmf custom do_monitor end + endtask + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_random_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_random_sequence.svh new file mode 100644 index 0000000..448cc51 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_random_sequence.svh @@ -0,0 +1,67 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This sequences randomizes the fuse_ctrl_rst_out transaction and sends it +// to the UVM driver. +// +// This sequence constructs and randomizes a fuse_ctrl_rst_out_transaction. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_rst_out_random_sequence + extends fuse_ctrl_rst_out_sequence_base ; + + `uvm_object_utils( fuse_ctrl_rst_out_random_sequence ) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //***************************************************************** + function new(string name = ""); + super.new(name); + endfunction: new + + // **************************************************************************** + // TASK : body() + // This task is automatically executed when this sequence is started using the + // start(sequencerHandle) task. + // + task body(); + + // Construct the transaction + req=fuse_ctrl_rst_out_transaction::type_id::create("req"); + start_item(req); + // Randomize the transaction + if(!req.randomize()) `uvm_fatal("SEQ", "fuse_ctrl_rst_out_random_sequence::body()-fuse_ctrl_rst_out_transaction randomization failed") + // Send the transaction to the fuse_ctrl_rst_out_driver_bfm via the sequencer and fuse_ctrl_rst_out_driver. + finish_item(req); + `uvm_info("SEQ", {"Response:",req.convert2string()},UVM_MEDIUM) + + endtask + +endclass: fuse_ctrl_rst_out_random_sequence + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_responder_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_responder_sequence.svh new file mode 100644 index 0000000..0a1e3cb --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_responder_sequence.svh @@ -0,0 +1,63 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class can be used to provide stimulus when an interface +// has been configured to run in a responder mode. It +// will never finish by default, always going back to the driver +// and driver BFM for the next transaction with which to respond. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_rst_out_responder_sequence + extends fuse_ctrl_rst_out_sequence_base ; + + `uvm_object_utils( fuse_ctrl_rst_out_responder_sequence ) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "fuse_ctrl_rst_out_responder_sequence"); + super.new(name); + endfunction + + task body(); + req=fuse_ctrl_rst_out_transaction::type_id::create("req"); + forever begin + start_item(req); + finish_item(req); + // pragma uvmf custom body begin + // UVMF_CHANGE_ME : Do something here with the resulting req item. The + // finish_item() call above will block until the req transaction is ready + // to be handled by the responder sequence. + // If this was an item that required a response, the expectation is + // that the response should be populated within this transaction now. + `uvm_info("SEQ",$sformatf("Processed txn: %s",req.convert2string()),UVM_HIGH) + // pragma uvmf custom body end + end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_sequence_base.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_sequence_base.svh new file mode 100644 index 0000000..e4c8255 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_sequence_base.svh @@ -0,0 +1,110 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the class used as the base class for all sequences +// for this interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_rst_out_sequence_base extends uvmf_sequence_base #( + .REQ(fuse_ctrl_rst_out_transaction ), + .RSP(fuse_ctrl_rst_out_transaction )); + + `uvm_object_utils( fuse_ctrl_rst_out_sequence_base ) + + // variables + typedef fuse_ctrl_rst_out_transaction fuse_ctrl_rst_out_transaction_req_t; + fuse_ctrl_rst_out_transaction_req_t req; + typedef fuse_ctrl_rst_out_transaction fuse_ctrl_rst_out_transaction_rsp_t; + fuse_ctrl_rst_out_transaction_rsp_t rsp; + + // Event for identifying when a response was received from the sequencer + event new_rsp; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // TASK : get_responses() + // This task recursively gets sequence item responses from the sequencer. + // + virtual task get_responses(); + fork + begin + // Block until new rsp available + get_response(rsp); + // New rsp received. Indicate to sequence using event. + ->new_rsp; + // Display the received response transaction + `uvm_info("SEQ", {"New response transaction:",rsp.convert2string()}, UVM_MEDIUM) + end + join_none + endtask + + // **************************************************************************** + // TASK : pre_body() + // This task is called automatically when start is called with call_pre_post set to 1 (default). + // By calling get_responses() within pre_body() any derived sequences are automatically + // processing response transactions. Only un-comment this call to get_responses() if you + // have configured the interface driver to utilize the response transaction path by setting + // the configuration variable "return_transaction_response" to 1. Otherwise it is possible + // to impact runtime performance and memory utilization. + // + virtual task pre_body(); + // pragma uvmf custom pre_body begin +// get_responses(); + // pragma uvmf custom pre_body end + endtask + + // **************************************************************************** + // TASK : body() + // This task is called automatically when start is called. This sequence sends + // a req sequence item to the sequencer identified as an argument in the call + // to start. + // + virtual task body(); + // pragma uvmf custom body begin + start_item(req); + finish_item(req); + // pragma uvmf custom body end + endtask + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name =""); + super.new( name ); + // pragma uvmf custom new begin + req = fuse_ctrl_rst_out_transaction_req_t::type_id::create("req"); + rsp = fuse_ctrl_rst_out_transaction_rsp_t::type_id::create("rsp"); + // pragma uvmf custom new end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_transaction.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_transaction.svh new file mode 100644 index 0000000..5573643 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_transaction.svh @@ -0,0 +1,196 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class defines the variables required for an fuse_ctrl_rst_out +// transaction. Class variables to be displayed in waveform transaction +// viewing are added to the transaction viewing stream in the add_to_wave +// function. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_rst_out_transaction extends uvmf_transaction_base; + + `uvm_object_utils( fuse_ctrl_rst_out_transaction ) + + pwrmgr_pkg::pwr_otp_rsp_t pwr_otp_o ; + + //Constraints for the transaction variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //******************************************************************* + //******************************************************************* + // Macros that define structs and associated functions are + // located in fuse_ctrl_rst_out_macros.svh + + //******************************************************************* + // Monitor macro used by fuse_ctrl_rst_out_monitor and fuse_ctrl_rst_out_monitor_bfm + // This struct is defined in fuse_ctrl_rst_out_macros.svh + `fuse_ctrl_rst_out_MONITOR_STRUCT + fuse_ctrl_rst_out_monitor_s fuse_ctrl_rst_out_monitor_struct; + //******************************************************************* + // FUNCTION: to_monitor_struct() + // This function packs transaction variables into a fuse_ctrl_rst_out_monitor_s + // structure. The function returns the handle to the fuse_ctrl_rst_out_monitor_struct. + // This function is defined in fuse_ctrl_rst_out_macros.svh + `fuse_ctrl_rst_out_TO_MONITOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_monitor_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_rst_out_macros.svh + `fuse_ctrl_rst_out_FROM_MONITOR_STRUCT_FUNCTION + + //******************************************************************* + // Initiator macro used by fuse_ctrl_rst_out_driver and fuse_ctrl_rst_out_driver_bfm + // to communicate initiator driven data to fuse_ctrl_rst_out_driver_bfm. + // This struct is defined in fuse_ctrl_rst_out_macros.svh + `fuse_ctrl_rst_out_INITIATOR_STRUCT + fuse_ctrl_rst_out_initiator_s fuse_ctrl_rst_out_initiator_struct; + //******************************************************************* + // FUNCTION: to_initiator_struct() + // This function packs transaction variables into a fuse_ctrl_rst_out_initiator_s + // structure. The function returns the handle to the fuse_ctrl_rst_out_initiator_struct. + // This function is defined in fuse_ctrl_rst_out_macros.svh + `fuse_ctrl_rst_out_TO_INITIATOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_initiator_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_rst_out_macros.svh + `fuse_ctrl_rst_out_FROM_INITIATOR_STRUCT_FUNCTION + + //******************************************************************* + // Responder macro used by fuse_ctrl_rst_out_driver and fuse_ctrl_rst_out_driver_bfm + // to communicate Responder driven data to fuse_ctrl_rst_out_driver_bfm. + // This struct is defined in fuse_ctrl_rst_out_macros.svh + `fuse_ctrl_rst_out_RESPONDER_STRUCT + fuse_ctrl_rst_out_responder_s fuse_ctrl_rst_out_responder_struct; + //******************************************************************* + // FUNCTION: to_responder_struct() + // This function packs transaction variables into a fuse_ctrl_rst_out_responder_s + // structure. The function returns the handle to the fuse_ctrl_rst_out_responder_struct. + // This function is defined in fuse_ctrl_rst_out_macros.svh + `fuse_ctrl_rst_out_TO_RESPONDER_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_responder_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_rst_out_macros.svh + `fuse_ctrl_rst_out_FROM_RESPONDER_STRUCT_FUNCTION + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + endfunction + + // **************************************************************************** + // FUNCTION: convert2string() + // This function converts all variables in this class to a single string for + // logfile reporting. + // + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + // UVMF_CHANGE_ME : Customize format if desired. + return $sformatf("pwr_otp_o:0x%x ",pwr_otp_o); + // pragma uvmf custom convert2string end + endfunction + + //******************************************************************* + // FUNCTION: do_print() + // This function is automatically called when the .print() function + // is called on this class. + // + virtual function void do_print(uvm_printer printer); + // pragma uvmf custom do_print begin + // UVMF_CHANGE_ME : Current contents of do_print allows for the use of UVM 1.1d, 1.2 or P1800.2. + // Update based on your own printing preference according to your preferred UVM version + $display(convert2string()); + // pragma uvmf custom do_print end + endfunction + + //******************************************************************* + // FUNCTION: do_compare() + // This function is automatically called when the .compare() function + // is called on this class. + // + virtual function bit do_compare (uvm_object rhs, uvm_comparer comparer); + fuse_ctrl_rst_out_transaction RHS; + if (!$cast(RHS,rhs)) return 0; + // pragma uvmf custom do_compare begin + // UVMF_CHANGE_ME : Eliminate comparison of variables not to be used for compare + return (super.do_compare(rhs,comparer) + &&(this.pwr_otp_o == RHS.pwr_otp_o) + ); + // pragma uvmf custom do_compare end + endfunction + + //******************************************************************* + // FUNCTION: do_copy() + // This function is automatically called when the .copy() function + // is called on this class. + // + virtual function void do_copy (uvm_object rhs); + fuse_ctrl_rst_out_transaction RHS; + assert($cast(RHS,rhs)); + // pragma uvmf custom do_copy begin + super.do_copy(rhs); + this.pwr_otp_o = RHS.pwr_otp_o; + // pragma uvmf custom do_copy end + endfunction + + // **************************************************************************** + // FUNCTION: add_to_wave() + // This function is used to display variables in this class in the waveform + // viewer. The start_time and end_time variables must be set before this + // function is called. If the start_time and end_time variables are not set + // the transaction will be hidden at 0ns on the waveform display. + // + virtual function void add_to_wave(int transaction_viewing_stream_h); + `ifdef QUESTA + if (transaction_view_h == 0) begin + transaction_view_h = $begin_transaction(transaction_viewing_stream_h,"fuse_ctrl_rst_out_transaction",start_time); + end + super.add_to_wave(transaction_view_h); + // pragma uvmf custom add_to_wave begin + // UVMF_CHANGE_ME : Color can be applied to transaction entries based on content, example below + // case() + // 1 : $add_color(transaction_view_h,"red"); + // default : $add_color(transaction_view_h,"grey"); + // endcase + // UVMF_CHANGE_ME : Eliminate transaction variables not wanted in transaction viewing in the waveform viewer + $add_attribute(transaction_view_h,pwr_otp_o,"pwr_otp_o"); + // pragma uvmf custom add_to_wave end + $end_transaction(transaction_view_h,end_time); + $free_transaction(transaction_view_h); + `endif // QUESTA + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_transaction_coverage.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_transaction_coverage.svh new file mode 100644 index 0000000..ef38834 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_transaction_coverage.svh @@ -0,0 +1,84 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class records fuse_ctrl_rst_out transaction information using +// a covergroup named fuse_ctrl_rst_out_transaction_cg. An instance of this +// coverage component is instantiated in the uvmf_parameterized_agent +// if the has_coverage flag is set. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_rst_out_transaction_coverage extends uvm_subscriber #(.T(fuse_ctrl_rst_out_transaction )); + + `uvm_component_utils( fuse_ctrl_rst_out_transaction_coverage ) + + T coverage_trans; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + covergroup fuse_ctrl_rst_out_transaction_cg; + // pragma uvmf custom covergroup begin + // UVMF_CHANGE_ME : Add coverage bins, crosses, exclusions, etc. according to coverage needs. + option.auto_bin_max=1024; + option.per_instance=1; + pwr_otp_o: coverpoint coverage_trans.pwr_otp_o; + // pragma uvmf custom covergroup end + endgroup + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new(string name="", uvm_component parent=null); + super.new(name,parent); + fuse_ctrl_rst_out_transaction_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that transaction variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + endfunction + + // **************************************************************************** + // FUNCTION : build_phase() + // This function is the standard UVM build_phase. + // + function void build_phase(uvm_phase phase); + fuse_ctrl_rst_out_transaction_cg.set_inst_name($sformatf("fuse_ctrl_rst_out_transaction_cg_%s",get_full_name())); + endfunction + + // **************************************************************************** + // FUNCTION: write (T t) + // This function is automatically executed when a transaction arrives on the + // analysis_export. It copies values from the variables in the transaction + // to local variables used to collect functional coverage. + // + virtual function void write (T t); + `uvm_info("COV","Received transaction",UVM_HIGH); + coverage_trans = t; + fuse_ctrl_rst_out_transaction_cg.sample(); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_typedefs.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_typedefs.svh new file mode 100644 index 0000000..f2a7bdb --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_typedefs.svh @@ -0,0 +1,34 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the host server when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_typedefs_hdl.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_typedefs_hdl.svh new file mode 100644 index 0000000..0d58518 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_typedefs_hdl.svh @@ -0,0 +1,35 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the emulator when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/yaml/fuse_ctrl_rst_out_interface.yaml b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/yaml/fuse_ctrl_rst_out_interface.yaml new file mode 100644 index 0000000..ca4764b --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/yaml/fuse_ctrl_rst_out_interface.yaml @@ -0,0 +1,33 @@ +uvmf: + interfaces: + fuse_ctrl_rst_out: + clock: clk_i + config_constraints: [] + config_vars: [] + existing_library_component: 'True' + gen_inbound_streaming_driver: 'False' + hdl_pkg_parameters: [] + hdl_typedefs: [] + hvl_pkg_parameters: [] + hvl_typedefs: [] + parameters: [] + ports: + - dir: input + name: pwr_otp_o + reset_value: '''bz' + width: '[''$bits(pwrmgr_pkg::pwr_otp_rsp_t)'']' + - dir: inout + name: otp_ext_voltage_h_io + reset_value: '''bz' + width: '1' + reset: rst_ni + reset_assertion_level: 'False' + transaction_constraints: [] + transaction_vars: + - comment: '' + iscompare: 'True' + isrand: 'False' + name: pwr_otp_o + type: pwrmgr_pkg::pwr_otp_rsp_t + unpacked_dimension: '' + use_dpi_link: 'False' diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/.project b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/.project new file mode 100644 index 0000000..a4da8e3 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/.project @@ -0,0 +1,30 @@ + + + fuse_ctrl_secreg_axi_read_in_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/.svproject b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/.svproject new file mode 100644 index 0000000..52a9f8c --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/Makefile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/Makefile new file mode 100644 index 0000000..0c9fcbd --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/Makefile @@ -0,0 +1,66 @@ +# fuse_ctrl_secreg_axi_read_in interface packages source +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +fuse_ctrl_secreg_axi_read_in_PKG = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_filelist_hvl.f + +fuse_ctrl_secreg_axi_read_in_PKG_HDL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_filelist_hdl.f + +fuse_ctrl_secreg_axi_read_in_PKG_XRTL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_filelist_xrtl.f + +COMP_fuse_ctrl_secreg_axi_read_in_PKG_TGT_0 = q_comp_fuse_ctrl_secreg_axi_read_in_pkg +COMP_fuse_ctrl_secreg_axi_read_in_PKG_TGT_1 = v_comp_fuse_ctrl_secreg_axi_read_in_pkg +COMP_fuse_ctrl_secreg_axi_read_in_PKG_TGT = $(COMP_fuse_ctrl_secreg_axi_read_in_PKG_TGT_$(USE_VELOCE)) + +comp_fuse_ctrl_secreg_axi_read_in_pkg: $(COMP_fuse_ctrl_secreg_axi_read_in_PKG_TGT) + +q_comp_fuse_ctrl_secreg_axi_read_in_pkg: + $(HDL_COMP_CMD) $(fuse_ctrl_secreg_axi_read_in_PKG_HDL) + $(HVL_COMP_CMD) $(fuse_ctrl_secreg_axi_read_in_PKG) + $(HDL_COMP_CMD) $(fuse_ctrl_secreg_axi_read_in_PKG_XRTL) + +v_comp_fuse_ctrl_secreg_axi_read_in_pkg: + $(HVL_COMP_CMD) $(fuse_ctrl_secreg_axi_read_in_PKG_HDL) + $(HVL_COMP_CMD) $(fuse_ctrl_secreg_axi_read_in_PKG) + $(VELANALYZE_CMD) $(fuse_ctrl_secreg_axi_read_in_PKG_HDL) + $(VELANALYZE_HVL_CMD) $(fuse_ctrl_secreg_axi_read_in_PKG) + $(HDL_COMP_CMD) $(fuse_ctrl_secreg_axi_read_in_PKG_XRTL) + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export fuse_ctrl_secreg_axi_read_in_IF_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/dpi + +C_FILE_COMPILE_LIST_fuse_ctrl_secreg_axi_read_in_pkg = \ + +O_FILE_COMPILE_LIST_fuse_ctrl_secreg_axi_read_in_pkg = $(notdir $(C_FILE_COMPILE_LIST_fuse_ctrl_secreg_axi_read_in_pkg:.c=.o)) + +GCC_COMP_ARGS_fuse_ctrl_secreg_axi_read_in_pkg += -I$(fuse_ctrl_secreg_axi_read_in_IF_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_fuse_ctrl_secreg_axi_read_in_pkg += $(fuse_ctrl_secreg_axi_read_in_IF_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_fuse_ctrl_secreg_axi_read_in_pkg += \ + \ + -o .so + +comp_fuse_ctrl_secreg_axi_read_in_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Interface C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_fuse_ctrl_secreg_axi_read_in_pkg) $(C_FILE_COMPILE_LIST_fuse_ctrl_secreg_axi_read_in_pkg) + @echo "--------------------------------" + @echo "Linking Interface C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_fuse_ctrl_secreg_axi_read_in_pkg) $(O_FILE_COMPILE_LIST_fuse_ctrl_secreg_axi_read_in_pkg) + @echo "--------------------------------" + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/compile.do b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/compile.do new file mode 100644 index 0000000..88878d4 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/compile.do @@ -0,0 +1,14 @@ +# Tcl do file for compile of fuse_ctrl_secreg_axi_read_in interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_filelist_hdl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_filelist_hvl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_filelist_xrtl.f \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in.compile new file mode 100644 index 0000000..30a6c81 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in.compile @@ -0,0 +1,3 @@ +needs: + - fuse_ctrl_secreg_axi_read_in_hvl.compile + - fuse_ctrl_secreg_axi_read_in_hdl.compile diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_bfm.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_bfm.vinfo new file mode 100644 index 0000000..7a7c867 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_bfm.vinfo @@ -0,0 +1,6 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use fuse_ctrl_secreg_axi_read_in_pkg_hdl.vinfo ++incdir+@vinfodir +src/fuse_ctrl_secreg_axi_read_in_if.sv +src/fuse_ctrl_secreg_axi_read_in_driver_bfm.sv +src/fuse_ctrl_secreg_axi_read_in_monitor_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_common.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_common.compile new file mode 100644 index 0000000..34e8920 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_common.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +incdir: + - . + - ${uvm_path}/src +src: + - fuse_ctrl_secreg_axi_read_in_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_filelist_hdl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_filelist_hdl.f new file mode 100644 index 0000000..5f203b9 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_filelist_hdl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_filelist_hvl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_filelist_hvl.f new file mode 100644 index 0000000..6917a8f --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_filelist_hvl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_pkg.sv \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_filelist_xrtl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_filelist_xrtl.f new file mode 100644 index 0000000..4801037 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_filelist_xrtl.f @@ -0,0 +1,3 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_if.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_monitor_bfm.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_driver_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_hdl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_hdl.compile new file mode 100644 index 0000000..822c6da --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_hdl.compile @@ -0,0 +1,9 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ./fuse_ctrl_secreg_axi_read_in_common.compile +incdir: + - . +src: + - src/fuse_ctrl_secreg_axi_read_in_if.sv + - src/fuse_ctrl_secreg_axi_read_in_monitor_bfm.sv + - src/fuse_ctrl_secreg_axi_read_in_driver_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_hvl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_hvl.compile new file mode 100644 index 0000000..baf1ae9 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_hvl.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ./fuse_ctrl_secreg_axi_read_in_common.compile +incdir: + - . +src: + - fuse_ctrl_secreg_axi_read_in_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_pkg.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_pkg.sv new file mode 100644 index 0000000..411b495 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_pkg.sv @@ -0,0 +1,91 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - + +// - +// - +// - + +// - +// - +// - + +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_secreg_axi_read_in_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg_hdl::*; + import uvmf_base_pkg::*; + import fuse_ctrl_secreg_axi_read_in_pkg_hdl::*; + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + `include "src/fuse_ctrl_secreg_axi_read_in_macros.svh" + + export fuse_ctrl_secreg_axi_read_in_pkg_hdl::*; + + + + // Parameters defined as HVL parameters + + `include "src/fuse_ctrl_secreg_axi_read_in_typedefs.svh" + `include "src/fuse_ctrl_secreg_axi_read_in_transaction.svh" + + `include "src/fuse_ctrl_secreg_axi_read_in_configuration.svh" + `include "src/fuse_ctrl_secreg_axi_read_in_driver.svh" + `include "src/fuse_ctrl_secreg_axi_read_in_monitor.svh" + + `include "src/fuse_ctrl_secreg_axi_read_in_transaction_coverage.svh" + `include "src/fuse_ctrl_secreg_axi_read_in_sequence_base.svh" + `include "src/fuse_ctrl_secreg_axi_read_in_random_sequence.svh" + + `include "src/fuse_ctrl_secreg_axi_read_in_responder_sequence.svh" + `include "src/fuse_ctrl_secreg_axi_read_in2reg_adapter.svh" + + `include "src/fuse_ctrl_secreg_axi_read_in_agent.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new interface sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the interface package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_pkg.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_pkg.vinfo new file mode 100644 index 0000000..a76e858 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_pkg.vinfo @@ -0,0 +1,4 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use fuse_ctrl_secreg_axi_read_in_pkg_hdl.vinfo ++incdir+@vinfodir +fuse_ctrl_secreg_axi_read_in_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_pkg_hdl.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_pkg_hdl.sv new file mode 100644 index 0000000..1b90f02 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_pkg_hdl.sv @@ -0,0 +1,52 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that needs to be compiled and synthesized +// for running on Veloce. +// +// CONTAINS: +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_secreg_axi_read_in_pkg_hdl; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HDL parameters + + `include "src/fuse_ctrl_secreg_axi_read_in_typedefs_hdl.svh" + `include "src/fuse_ctrl_secreg_axi_read_in_macros.svh" + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_pkg_hdl.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_pkg_hdl.vinfo new file mode 100644 index 0000000..269b5c0 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_pkg_hdl.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +fuse_ctrl_secreg_axi_read_in_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_pkg_sve.F b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_pkg_sve.F new file mode 100644 index 0000000..8fec4a9 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_pkg_sve.F @@ -0,0 +1,10 @@ +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + ++incdir+. +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_filelist_hdl.f +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_filelist_hvl.f diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in2reg_adapter.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in2reg_adapter.svh new file mode 100644 index 0000000..eb4b887 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in2reg_adapter.svh @@ -0,0 +1,137 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the UVM register adapter for the fuse_ctrl_secreg_axi_read_in interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_secreg_axi_read_in2reg_adapter #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvm_reg_adapter; + + `uvm_object_param_utils( fuse_ctrl_secreg_axi_read_in2reg_adapter #( + AW, + DW, + IW, + UW + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //-------------------------------------------------------------------- + // new + //-------------------------------------------------------------------- + function new (string name = "fuse_ctrl_secreg_axi_read_in2reg_adapter" ); + super.new(name); + // pragma uvmf custom new begin + // UVMF_CHANGE_ME : Configure the adapter regarding byte enables and provides response. + + // Does the protocol the Agent is modeling support byte enables? + // 0 = NO + // 1 = YES + supports_byte_enable = 0; + + // Does the Agent's Driver provide separate response sequence items? + // i.e. Does the driver call seq_item_port.put() + // and do the sequences call get_response()? + // 0 = NO + // 1 = YES + provides_responses = 0; + // pragma uvmf custom new end + + endfunction: new + + //-------------------------------------------------------------------- + // reg2bus + //-------------------------------------------------------------------- + virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw); + + fuse_ctrl_secreg_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) trans_h = fuse_ctrl_secreg_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )::type_id::create("trans_h"); + + // pragma uvmf custom reg2bus begin + // UVMF_CHANGE_ME : Fill in the reg2bus adapter mapping registe fields to protocol fields. + + //Adapt the following for your sequence item type + // trans_h.op = (rw.kind == UVM_READ) ? WB_READ : WB_WRITE; + //Copy over address + // trans_h.addr = rw.addr; + //Copy over write data + // trans_h.data = rw.data; + + // pragma uvmf custom reg2bus end + + // Return the adapted transaction + return trans_h; + + endfunction: reg2bus + + //-------------------------------------------------------------------- + // bus2reg + //-------------------------------------------------------------------- + virtual function void bus2reg(uvm_sequence_item bus_item, + ref uvm_reg_bus_op rw); + fuse_ctrl_secreg_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) trans_h; + if (!$cast(trans_h, bus_item)) begin + `uvm_fatal("ADAPT","Provided bus_item is not of the correct type") + return; + end + // pragma uvmf custom bus2reg begin + // UVMF_CHANGE_ME : Fill in the bus2reg adapter mapping protocol fields to register fields. + //Adapt the following for your sequence item type + //Copy over instruction type + // rw.kind = (trans_h.op == WB_WRITE) ? UVM_WRITE : UVM_READ; + //Copy over address + // rw.addr = trans_h.addr; + //Copy over read data + // rw.data = trans_h.data; + //Check for errors on the bus and return UVM_NOT_OK if there is an error + // rw.status = UVM_IS_OK; + // pragma uvmf custom bus2reg end + + endfunction: bus2reg + +endclass : fuse_ctrl_secreg_axi_read_in2reg_adapter + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_agent.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_agent.svh new file mode 100644 index 0000000..93bc093 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_agent.svh @@ -0,0 +1,102 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: Protocol specific agent class definition +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_secreg_axi_read_in_agent #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvmf_parameterized_agent #( + .CONFIG_T(fuse_ctrl_secreg_axi_read_in_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .DRIVER_T(fuse_ctrl_secreg_axi_read_in_driver #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .MONITOR_T(fuse_ctrl_secreg_axi_read_in_monitor #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .COVERAGE_T(fuse_ctrl_secreg_axi_read_in_transaction_coverage #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .TRANS_T(fuse_ctrl_secreg_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )) + ); + + `uvm_component_param_utils( fuse_ctrl_secreg_axi_read_in_agent #( + AW, + DW, + IW, + UW + )) + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** + // FUNCTION: build_phase + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + if (configuration.active_passive == ACTIVE) begin + // Place sequencer handle into configuration object + // so that it may be retrieved from configuration + // rather than using uvm_config_db + configuration.sequencer = this.sequencer; + end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_configuration.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_configuration.svh new file mode 100644 index 0000000..696cdb0 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_configuration.svh @@ -0,0 +1,233 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class contains all variables and functions used +// to configure the fuse_ctrl_secreg_axi_read_in agent and its bfm's. It gets the +// bfm's from the uvm_config_db for use by the agent. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_secreg_axi_read_in_configuration #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvmf_parameterized_agent_configuration_base #( + .DRIVER_BFM_BIND_T(virtual fuse_ctrl_secreg_axi_read_in_driver_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .MONITOR_BFM_BIND_T( virtual fuse_ctrl_secreg_axi_read_in_monitor_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ))); + + `uvm_object_param_utils( fuse_ctrl_secreg_axi_read_in_configuration #( + AW, + DW, + IW, + UW + )) + + + // Sequencer handle populated by agent + uvm_sequencer #(fuse_ctrl_secreg_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) ) sequencer; + + //Constraints for the configuration variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + covergroup fuse_ctrl_secreg_axi_read_in_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + // pragma uvmf custom covergroup end + endgroup + + //******************************************************************* + //******************************************************************* + // Structure used to pass configuration variables to monitor and driver BFM's. + // Use to_struct function to pack variables into structure. + // Use from_struct function to unpack variables from structure. + // This structure is defined in fuse_ctrl_secreg_axi_read_in_macros.svh + `fuse_ctrl_secreg_axi_read_in_CONFIGURATION_STRUCT + fuse_ctrl_secreg_axi_read_in_configuration_s fuse_ctrl_secreg_axi_read_in_configuration_struct; + //******************************************************************* + // FUNCTION: to_struct() + // This function packs variables into a fuse_ctrl_secreg_axi_read_in_configuration_s + // structure. The function returns the handle to the fuse_ctrl_secreg_axi_read_in_configuration_struct. + // This function is defined in fuse_ctrl_secreg_axi_read_in_macros.svh + `fuse_ctrl_secreg_axi_read_in_CONFIGURATION_TO_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_struct() + // This function unpacks the struct provided as an argument into + // variables of this class. + // This function is defined in fuse_ctrl_secreg_axi_read_in_macros.svh + `fuse_ctrl_secreg_axi_read_in_CONFIGURATION_FROM_STRUCT_FUNCTION + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + // Construct the covergroup for this configuration class + fuse_ctrl_secreg_axi_read_in_configuration_cg = new; + endfunction + + // **************************************************************************** + // FUNCTION: post_randomize() + // This function is automatically called after the randomize() function + // is executed. + // + function void post_randomize(); + super.post_randomize(); + fuse_ctrl_secreg_axi_read_in_configuration_cg.sample(); + endfunction + + // **************************************************************************** + // FUNCTION: initialize + // This function causes the configuration to retrieve + // its virtual interface handle from the uvm_config_db. + // This function also makes itself available to its + // agent through the uvm_config_db. + // + // ARGUMENTS: + // uvmf_active_passive_t activity: + // This argument identifies the simulation level + // as either BLOCK, CHIP, SIMULATION, etc. + // + // AGENT_PATH: + // This argument identifies the path to this + // configurations agent. This configuration + // makes itself available to the agent specified + // by agent_path by placing itself into the + // uvm_config_db. + // + // INTERFACE_NAME: + // This argument identifies the string name of + // this configurations BFM's. This string + // name is used to retrieve the driver and + // monitor BFM from the uvm_config_db. + // + virtual function void initialize(uvmf_active_passive_t activity, + string agent_path, + string interface_name); + + super.initialize( activity, agent_path, interface_name); + // The covergroup is given the same name as the interface + fuse_ctrl_secreg_axi_read_in_configuration_cg.set_inst_name(interface_name); + + // This configuration places itself into the uvm_config_db for the agent, identified by the agent_path variable, to retrieve. + uvm_config_db #( fuse_ctrl_secreg_axi_read_in_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + )::set( null ,agent_path,UVMF_AGENT_CONFIG, this ); + + // This configuration also places itself in the config db using the same identifier used by the interface. This allows users to access + // configuration variables and the interface through the bfm api class rather than directly accessing the BFM. This is useful for + // accessingthe BFM when using Veloce + uvm_config_db #( fuse_ctrl_secreg_axi_read_in_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + )::set( null ,UVMF_CONFIGURATIONS, interface_name, this ); + + fuse_ctrl_secreg_axi_read_in_configuration_cg.set_inst_name($sformatf("fuse_ctrl_secreg_axi_read_in_configuration_cg_%s",get_full_name())); + +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. + `uvm_info("CFG", + $psprintf("The agent at '%s' is using interface named %s has the following parameters: AW=%x DW=%x IW=%x UW=%x ", agent_path, interface_name, AW ,DW ,IW ,UW ), + UVM_DEBUG) + + // pragma uvmf custom initialize begin + // This controls whether or not the agent returns a transaction handle in the driver when calling + // item_done() back into the sequencer or not. If set to 1, a transaction is sent back which means + // the sequence on the other end must use the get_response() part of the driver/sequence API. If + // this doesn't occur, there will eventually be response_queue overflow errors during the test. + return_transaction_response = 1'b0; + + // pragma uvmf custom initialize end + + endfunction + + // **************************************************************************** + // TASK: wait_for_reset + // *[Required]* Blocks until reset is released. The wait_for_reset operation is performed + // by a task in the monitor bfm. + virtual task wait_for_reset(); + monitor_bfm.wait_for_reset(); + endtask + + // **************************************************************************** + // TASK: wait_for_num_clocks + // *[Required]* Blocks until specified number of clocks have elapsed. The wait_for_num_clocks + // operation is performed by a task in the monitor bfm. + virtual task wait_for_num_clocks(int clocks); + monitor_bfm.wait_for_num_clocks(clocks); + endtask + + // **************************************************************************** + // FUNCTION : convert2string() + // This function is used to convert variables in this class into a string for log messaging. + // + virtual function string convert2string (); + // pragma uvmf custom convert2string begin + return $sformatf(""); + // pragma uvmf custom convert2string end + endfunction + + // **************************************************************************** + // FUNCTION: get_sequencer + function uvm_sequencer #(fuse_ctrl_secreg_axi_read_in_transaction#( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )) get_sequencer(); + return sequencer; + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_driver.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_driver.svh new file mode 100644 index 0000000..2a03dee --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_driver.svh @@ -0,0 +1,135 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class passes transactions between the sequencer +// and the BFM driver interface. It accesses the driver BFM +// through the bfm handle. This driver +// passes transactions to the driver BFM through the access +// task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_secreg_axi_read_in_driver #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvmf_driver_base #( + .CONFIG_T(fuse_ctrl_secreg_axi_read_in_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) ), + .BFM_BIND_T(virtual fuse_ctrl_secreg_axi_read_in_driver_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) ), + .REQ(fuse_ctrl_secreg_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) ), + .RSP(fuse_ctrl_secreg_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) )); + + `uvm_component_param_utils( fuse_ctrl_secreg_axi_read_in_driver #( + AW, + DW, + IW, + UW + )) +//******************************************************************* +// Macros that define structs located in fuse_ctrl_secreg_axi_read_in_macros.svh +//******************************************************************* +// Initiator macro used by fuse_ctrl_secreg_axi_read_in_driver and fuse_ctrl_secreg_axi_read_in_driver_bfm +// to communicate initiator driven data to fuse_ctrl_secreg_axi_read_in_driver_bfm. +`fuse_ctrl_secreg_axi_read_in_INITIATOR_STRUCT + fuse_ctrl_secreg_axi_read_in_initiator_s fuse_ctrl_secreg_axi_read_in_initiator_struct; +//******************************************************************* +// Responder macro used by fuse_ctrl_secreg_axi_read_in_driver and fuse_ctrl_secreg_axi_read_in_driver_bfm +// to communicate Responder driven data to fuse_ctrl_secreg_axi_read_in_driver_bfm. +`fuse_ctrl_secreg_axi_read_in_RESPONDER_STRUCT + fuse_ctrl_secreg_axi_read_in_responder_s fuse_ctrl_secreg_axi_read_in_responder_struct; + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent=null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the driver BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// driver BFM. This allows the driver BFM to call tasks and function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// **************************************************************************** +// This task is called by the run_phase in uvmf_driver_base. + virtual task access( inout REQ txn ); +// pragma uvmf custom access begin + if (configuration.initiator_responder==RESPONDER) begin + // Complete current transfer and wait for next transfer + bfm.respond_and_wait_for_next_transfer( + fuse_ctrl_secreg_axi_read_in_initiator_struct, + txn.to_responder_struct() + ); + // Unpack information about initiated transfer received by this responder + txn.from_initiator_struct(fuse_ctrl_secreg_axi_read_in_initiator_struct); + end else begin + // Initiate a transfer and get response + bfm.initiate_and_get_response( + txn.to_initiator_struct(), + fuse_ctrl_secreg_axi_read_in_responder_struct + ); + // Unpack transfer response information received by this initiator + txn.from_responder_struct(fuse_ctrl_secreg_axi_read_in_responder_struct); + end +// pragma uvmf custom access end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_driver_bfm.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_driver_bfm.sv new file mode 100644 index 0000000..509fca7 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_driver_bfm.sv @@ -0,0 +1,383 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This interface performs the fuse_ctrl_secreg_axi_read_in signal driving. It is +// accessed by the uvm fuse_ctrl_secreg_axi_read_in driver through a virtual interface +// handle in the fuse_ctrl_secreg_axi_read_in configuration. It drives the singals passed +// in through the port connection named bus of type fuse_ctrl_secreg_axi_read_in_if. +// +// Input signals from the fuse_ctrl_secreg_axi_read_in_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// This bfm drives signals with a _o suffix. These signals +// are driven onto signals within fuse_ctrl_secreg_axi_read_in_if based on INITIATOR/RESPONDER and/or +// ARBITRATION/GRANT status. +// +// The output signal connections are as follows: +// signal_o -> bus.signal +// +// +// Interface functions and tasks used by UVM components: +// +// configure: +// This function gets configuration attributes from the +// UVM driver to set any required BFM configuration +// variables such as 'initiator_responder'. +// +// initiate_and_get_response: +// This task is used to perform signaling activity for initiating +// a protocol transfer. The task initiates the transfer, using +// input data from the initiator struct. Then the task captures +// response data, placing the data into the response struct. +// The response struct is returned to the driver class. +// +// respond_and_wait_for_next_transfer: +// This task is used to complete a current transfer as a responder +// and then wait for the initiator to start the next transfer. +// The task uses data in the responder struct to drive protocol +// signals to complete the transfer. The task then waits for +// the next transfer. Once the next transfer begins, data from +// the initiator is placed into the initiator struct and sent +// to the responder sequence for processing to determine +// what data to respond with. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_secreg_axi_read_in_pkg_hdl::*; +`include "src/fuse_ctrl_secreg_axi_read_in_macros.svh" + +interface fuse_ctrl_secreg_axi_read_in_driver_bfm #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + (fuse_ctrl_secreg_axi_read_in_if bus); + // The following pragma and additional ones in-lined further below are for running this BFM on Veloce + // pragma attribute fuse_ctrl_secreg_axi_read_in_driver_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: AW=%x DW=%x IW=%x UW=%x ", AW,DW,IW,UW), + UVM_DEBUG) +end +`endif + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + tri clk_i_i; + tri rst_ni_i; + + // Signal list (all signals are capable of being inputs and outputs for the sake + // of supporting both INITIATOR and RESPONDER mode operation. Expectation is that + // directionality in the config file was from the point-of-view of the INITIATOR + + // INITIATOR mode input signals + + // INITIATOR mode output signals + tri [AW-1:0] araddr_i; + reg [AW-1:0] araddr_o = 'bz; + tri [$bits(axi_pkg::axi_burst_e)-1:0] arburst_i; + reg [$bits(axi_pkg::axi_burst_e)-1:0] arburst_o = 'bz; + tri [2:0] arsize_i; + reg [2:0] arsize_o = 'bz; + tri [7:0] arlen_i; + reg [7:0] arlen_o = 'bz; + tri [UW-1:0] aruser_i; + reg [UW-1:0] aruser_o = 'bz; + tri [IW-1:0] arid_i; + reg [IW-1:0] arid_o = 'bz; + tri arlock_i; + reg arlock_o = 'bz; + tri arvalid_i; + reg arvalid_o = 'bz; + tri rready_i; + reg rready_o = 'bz; + + // Bi-directional signals + + + assign clk_i_i = bus.clk_i; + assign rst_ni_i = bus.rst_ni; + + // These are signals marked as 'input' by the config file, but the signals will be + // driven by this BFM if put into RESPONDER mode (flipping all signal directions around) + + + // These are signals marked as 'output' by the config file, but the outputs will + // not be driven by this BFM unless placed in INITIATOR mode. + assign bus.araddr = (initiator_responder == INITIATOR) ? araddr_o : 'bz; + assign araddr_i = bus.araddr; + assign bus.arburst = (initiator_responder == INITIATOR) ? arburst_o : 'bz; + assign arburst_i = bus.arburst; + assign bus.arsize = (initiator_responder == INITIATOR) ? arsize_o : 'bz; + assign arsize_i = bus.arsize; + assign bus.arlen = (initiator_responder == INITIATOR) ? arlen_o : 'bz; + assign arlen_i = bus.arlen; + assign bus.aruser = (initiator_responder == INITIATOR) ? aruser_o : 'bz; + assign aruser_i = bus.aruser; + assign bus.arid = (initiator_responder == INITIATOR) ? arid_o : 'bz; + assign arid_i = bus.arid; + assign bus.arlock = (initiator_responder == INITIATOR) ? arlock_o : 'bz; + assign arlock_i = bus.arlock; + assign bus.arvalid = (initiator_responder == INITIATOR) ? arvalid_o : 'bz; + assign arvalid_i = bus.arvalid; + assign bus.rready = (initiator_responder == INITIATOR) ? rready_o : 'bz; + assign rready_i = bus.rready; + + // Proxy handle to UVM driver + fuse_ctrl_secreg_axi_read_in_pkg::fuse_ctrl_secreg_axi_read_in_driver #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) proxy; + // pragma tbx oneway proxy.my_function_name_in_uvm_driver + + // **************************************************************************** + // **************************************************************************** + // Macros that define structs located in fuse_ctrl_secreg_axi_read_in_macros.svh + // **************************************************************************** + // Struct for passing configuration data from fuse_ctrl_secreg_axi_read_in_driver to this BFM + // **************************************************************************** + `fuse_ctrl_secreg_axi_read_in_CONFIGURATION_STRUCT + // **************************************************************************** + // Structs for INITIATOR and RESPONDER data flow + //******************************************************************* + // Initiator macro used by fuse_ctrl_secreg_axi_read_in_driver and fuse_ctrl_secreg_axi_read_in_driver_bfm + // to communicate initiator driven data to fuse_ctrl_secreg_axi_read_in_driver_bfm. + `fuse_ctrl_secreg_axi_read_in_INITIATOR_STRUCT + fuse_ctrl_secreg_axi_read_in_initiator_s initiator_struct; + // Responder macro used by fuse_ctrl_secreg_axi_read_in_driver and fuse_ctrl_secreg_axi_read_in_driver_bfm + // to communicate Responder driven data to fuse_ctrl_secreg_axi_read_in_driver_bfm. + `fuse_ctrl_secreg_axi_read_in_RESPONDER_STRUCT + fuse_ctrl_secreg_axi_read_in_responder_s responder_struct; + + // **************************************************************************** +// pragma uvmf custom reset_condition_and_response begin + // Always block used to return signals to reset value upon assertion of reset + always @( negedge rst_ni_i ) + begin + // RESPONDER mode output signals + // INITIATOR mode output signals + araddr_o <= 'bz; + arburst_o <= 'bz; + arsize_o <= 'bz; + arlen_o <= 'bz; + aruser_o <= 'bz; + arid_o <= 'bz; + arlock_o <= 'bz; + arvalid_o <= 'bz; + rready_o <= 'bz; + // Bi-directional signals + + end +// pragma uvmf custom reset_condition_and_response end + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the driver BFM. It is called by the driver within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the driver BFM needs to be aware of the new configuration + // variables. + // + + function void configure(fuse_ctrl_secreg_axi_read_in_configuration_s fuse_ctrl_secreg_axi_read_in_configuration_arg); // pragma tbx xtf + initiator_responder = fuse_ctrl_secreg_axi_read_in_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + +// pragma uvmf custom initiate_and_get_response begin +// **************************************************************************** +// UVMF_CHANGE_ME +// This task is used by an initator. The task first initiates a transfer then +// waits for the responder to complete the transfer. + task initiate_and_get_response( + // This argument passes transaction variables used by an initiator + // to perform the initial part of a protocol transfer. The values + // come from a sequence item created in a sequence. + input fuse_ctrl_secreg_axi_read_in_initiator_s fuse_ctrl_secreg_axi_read_in_initiator_struct, + // This argument is used to send data received from the responder + // back to the sequence item. The sequence item is returned to the sequence. + output fuse_ctrl_secreg_axi_read_in_responder_s fuse_ctrl_secreg_axi_read_in_responder_struct + );// pragma tbx xtf + // + // Members within the fuse_ctrl_secreg_axi_read_in_initiator_struct: + // logic [AW-1:0] secreg_araddr ; + // logic secreg_arvalid ; + // logic [$bits(axi_pkg::axi_burst_e)] secreg_arburst ; + // logic [2:0] secreg_arsize ; + // logic [7:0] secreg_arlen ; + // logic [UW-1:0] secreg_aruser ; + // logic [IW-1:0] secreg_arid ; + // logic secreg_arlock ; + // logic secreg_rready ; + // Members within the fuse_ctrl_secreg_axi_read_in_responder_struct: + // logic [AW-1:0] secreg_araddr ; + // logic secreg_arvalid ; + // logic [$bits(axi_pkg::axi_burst_e)] secreg_arburst ; + // logic [2:0] secreg_arsize ; + // logic [7:0] secreg_arlen ; + // logic [UW-1:0] secreg_aruser ; + // logic [IW-1:0] secreg_arid ; + // logic secreg_arlock ; + // logic secreg_rready ; + initiator_struct = fuse_ctrl_secreg_axi_read_in_initiator_struct; + // + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clk_i_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available initiator input and inout signals listed. + // Initiator input signals + // Initiator inout signals + // How to assign a signal from an initiator struct member named xyz. + // All available initiator output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Initiator output signals + // araddr_o <= fuse_ctrl_secreg_axi_read_in_initiator_struct.xyz; // [AW-1:0] + // arburst_o <= fuse_ctrl_secreg_axi_read_in_initiator_struct.xyz; // [$bits(axi_pkg::axi_burst_e)-1:0] + // arsize_o <= fuse_ctrl_secreg_axi_read_in_initiator_struct.xyz; // [2:0] + // arlen_o <= fuse_ctrl_secreg_axi_read_in_initiator_struct.xyz; // [7:0] + // aruser_o <= fuse_ctrl_secreg_axi_read_in_initiator_struct.xyz; // [UW-1:0] + // arid_o <= fuse_ctrl_secreg_axi_read_in_initiator_struct.xyz; // [IW-1:0] + // arlock_o <= fuse_ctrl_secreg_axi_read_in_initiator_struct.xyz; // + // arvalid_o <= fuse_ctrl_secreg_axi_read_in_initiator_struct.xyz; // + // rready_o <= fuse_ctrl_secreg_axi_read_in_initiator_struct.xyz; // + // Initiator inout signals + // Initiate a transfer using the data received. + @(posedge clk_i_i); + @(posedge clk_i_i); + // Wait for the responder to complete the transfer then place the responder data into + // fuse_ctrl_secreg_axi_read_in_responder_struct. + @(posedge clk_i_i); + @(posedge clk_i_i); + responder_struct = fuse_ctrl_secreg_axi_read_in_responder_struct; + endtask +// pragma uvmf custom initiate_and_get_response end + +// pragma uvmf custom respond_and_wait_for_next_transfer begin +// **************************************************************************** +// The first_transfer variable is used to prevent completing a transfer in the +// first call to this task. For the first call to this task, there is not +// current transfer to complete. +bit first_transfer=1; + +// UVMF_CHANGE_ME +// This task is used by a responder. The task first completes the current +// transfer in progress then waits for the initiator to start the next transfer. + task respond_and_wait_for_next_transfer( + // This argument is used to send data received from the initiator + // back to the sequence item. The sequence determines how to respond. + output fuse_ctrl_secreg_axi_read_in_initiator_s fuse_ctrl_secreg_axi_read_in_initiator_struct, + // This argument passes transaction variables used by a responder + // to complete a protocol transfer. The values come from a sequence item. + input fuse_ctrl_secreg_axi_read_in_responder_s fuse_ctrl_secreg_axi_read_in_responder_struct + );// pragma tbx xtf + // Variables within the fuse_ctrl_secreg_axi_read_in_initiator_struct: + // logic [AW-1:0] secreg_araddr ; + // logic secreg_arvalid ; + // logic [$bits(axi_pkg::axi_burst_e)] secreg_arburst ; + // logic [2:0] secreg_arsize ; + // logic [7:0] secreg_arlen ; + // logic [UW-1:0] secreg_aruser ; + // logic [IW-1:0] secreg_arid ; + // logic secreg_arlock ; + // logic secreg_rready ; + // Variables within the fuse_ctrl_secreg_axi_read_in_responder_struct: + // logic [AW-1:0] secreg_araddr ; + // logic secreg_arvalid ; + // logic [$bits(axi_pkg::axi_burst_e)] secreg_arburst ; + // logic [2:0] secreg_arsize ; + // logic [7:0] secreg_arlen ; + // logic [UW-1:0] secreg_aruser ; + // logic [IW-1:0] secreg_arid ; + // logic secreg_arlock ; + // logic secreg_rready ; + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clk_i_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available responder input and inout signals listed. + // Responder input signals + // fuse_ctrl_secreg_axi_read_in_responder_struct.xyz = araddr_i; // [AW-1:0] + // fuse_ctrl_secreg_axi_read_in_responder_struct.xyz = arburst_i; // [$bits(axi_pkg::axi_burst_e)-1:0] + // fuse_ctrl_secreg_axi_read_in_responder_struct.xyz = arsize_i; // [2:0] + // fuse_ctrl_secreg_axi_read_in_responder_struct.xyz = arlen_i; // [7:0] + // fuse_ctrl_secreg_axi_read_in_responder_struct.xyz = aruser_i; // [UW-1:0] + // fuse_ctrl_secreg_axi_read_in_responder_struct.xyz = arid_i; // [IW-1:0] + // fuse_ctrl_secreg_axi_read_in_responder_struct.xyz = arlock_i; // + // fuse_ctrl_secreg_axi_read_in_responder_struct.xyz = arvalid_i; // + // fuse_ctrl_secreg_axi_read_in_responder_struct.xyz = rready_i; // + // Responder inout signals + // How to assign a signal, named xyz, from an initiator struct member. + // All available responder output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Responder output signals + // Responder inout signals + + @(posedge clk_i_i); + if (!first_transfer) begin + // Perform transfer response here. + // Reply using data recieved in the fuse_ctrl_secreg_axi_read_in_responder_struct. + @(posedge clk_i_i); + // Reply using data recieved in the transaction handle. + @(posedge clk_i_i); + end + // Wait for next transfer then gather info from intiator about the transfer. + // Place the data into the fuse_ctrl_secreg_axi_read_in_initiator_struct. + @(posedge clk_i_i); + @(posedge clk_i_i); + first_transfer = 0; + endtask +// pragma uvmf custom respond_and_wait_for_next_transfer end + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_if.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_if.sv new file mode 100644 index 0000000..9d81ead --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_if.sv @@ -0,0 +1,123 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface contains the fuse_ctrl_secreg_axi_read_in interface signals. +// It is instantiated once per fuse_ctrl_secreg_axi_read_in bus. Bus Functional Models, +// BFM's named fuse_ctrl_secreg_axi_read_in_driver_bfm, are used to drive signals on the bus. +// BFM's named fuse_ctrl_secreg_axi_read_in_monitor_bfm are used to monitor signals on the +// bus. This interface signal bundle is passed in the port list of +// the BFM in order to give the BFM access to the signals in this +// interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// This template can be used to connect a DUT to these signals +// +// .dut_signal_port(fuse_ctrl_secreg_axi_read_in_bus.araddr), // Agent output +// .dut_signal_port(fuse_ctrl_secreg_axi_read_in_bus.arburst), // Agent output +// .dut_signal_port(fuse_ctrl_secreg_axi_read_in_bus.arsize), // Agent output +// .dut_signal_port(fuse_ctrl_secreg_axi_read_in_bus.arlen), // Agent output +// .dut_signal_port(fuse_ctrl_secreg_axi_read_in_bus.aruser), // Agent output +// .dut_signal_port(fuse_ctrl_secreg_axi_read_in_bus.arid), // Agent output +// .dut_signal_port(fuse_ctrl_secreg_axi_read_in_bus.arlock), // Agent output +// .dut_signal_port(fuse_ctrl_secreg_axi_read_in_bus.arvalid), // Agent output +// .dut_signal_port(fuse_ctrl_secreg_axi_read_in_bus.rready), // Agent output + +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_secreg_axi_read_in_pkg_hdl::*; + +interface fuse_ctrl_secreg_axi_read_in_if #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + + ( + input tri clk_i, + input tri rst_ni, + inout tri [AW-1:0] araddr, + inout tri [$bits(axi_pkg::axi_burst_e)-1:0] arburst, + inout tri [2:0] arsize, + inout tri [7:0] arlen, + inout tri [UW-1:0] aruser, + inout tri [IW-1:0] arid, + inout tri arlock, + inout tri arvalid, + inout tri rready + ); + +modport monitor_port + ( + input clk_i, + input rst_ni, + input araddr, + input arburst, + input arsize, + input arlen, + input aruser, + input arid, + input arlock, + input arvalid, + input rready + ); + +modport initiator_port + ( + input clk_i, + input rst_ni, + output araddr, + output arburst, + output arsize, + output arlen, + output aruser, + output arid, + output arlock, + output arvalid, + output rready + ); + +modport responder_port + ( + input clk_i, + input rst_ni, + input araddr, + input arburst, + input arsize, + input arlen, + input aruser, + input arid, + input arlock, + input arvalid, + input rready + ); + + +// pragma uvmf custom interface_item_additional begin +// pragma uvmf custom interface_item_additional end + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_infact_coverage_strategy.csv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_infact_coverage_strategy.csv new file mode 100644 index 0000000..1c218e1 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_infact_coverage_strategy.csv @@ -0,0 +1,6 @@ +Global +auto_bin_max, 64 + +Name,Type,Include +rand_fields,coverpoint,=rand *.** + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_macros.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_macros.svh new file mode 100644 index 0000000..fd62fe9 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_macros.svh @@ -0,0 +1,207 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains macros used with the fuse_ctrl_secreg_axi_read_in package. +// These macros include packed struct definitions. These structs are +// used to pass data between classes, hvl, and BFM's, hdl. Use of +// structs are more efficient and simpler to modify. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_struct +// and from_struct methods defined in the macros below that are used in +// the fuse_ctrl_secreg_axi_read_in_configuration class. +// + `define fuse_ctrl_secreg_axi_read_in_CONFIGURATION_STRUCT \ +typedef struct packed { \ + uvmf_active_passive_t active_passive; \ + uvmf_initiator_responder_t initiator_responder; \ + } fuse_ctrl_secreg_axi_read_in_configuration_s; + + `define fuse_ctrl_secreg_axi_read_in_CONFIGURATION_TO_STRUCT_FUNCTION \ + virtual function fuse_ctrl_secreg_axi_read_in_configuration_s to_struct();\ + fuse_ctrl_secreg_axi_read_in_configuration_struct = \ + {\ + this.active_passive,\ + this.initiator_responder\ + };\ + return ( fuse_ctrl_secreg_axi_read_in_configuration_struct );\ + endfunction + + `define fuse_ctrl_secreg_axi_read_in_CONFIGURATION_FROM_STRUCT_FUNCTION \ + virtual function void from_struct(fuse_ctrl_secreg_axi_read_in_configuration_s fuse_ctrl_secreg_axi_read_in_configuration_struct);\ + {\ + this.active_passive,\ + this.initiator_responder \ + } = fuse_ctrl_secreg_axi_read_in_configuration_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_monitor_struct +// and from_monitor_struct methods of the fuse_ctrl_secreg_axi_read_in_transaction class. +// + `define fuse_ctrl_secreg_axi_read_in_MONITOR_STRUCT typedef struct packed { \ + logic [AW-1:0] secreg_araddr ; \ + logic secreg_arvalid ; \ + logic [$bits(axi_pkg::axi_burst_e)] secreg_arburst ; \ + logic [2:0] secreg_arsize ; \ + logic [7:0] secreg_arlen ; \ + logic [UW-1:0] secreg_aruser ; \ + logic [IW-1:0] secreg_arid ; \ + logic secreg_arlock ; \ + logic secreg_rready ; \ + } fuse_ctrl_secreg_axi_read_in_monitor_s; + + `define fuse_ctrl_secreg_axi_read_in_TO_MONITOR_STRUCT_FUNCTION \ + virtual function fuse_ctrl_secreg_axi_read_in_monitor_s to_monitor_struct();\ + fuse_ctrl_secreg_axi_read_in_monitor_struct = \ + { \ + this.secreg_araddr , \ + this.secreg_arvalid , \ + this.secreg_arburst , \ + this.secreg_arsize , \ + this.secreg_arlen , \ + this.secreg_aruser , \ + this.secreg_arid , \ + this.secreg_arlock , \ + this.secreg_rready \ + };\ + return ( fuse_ctrl_secreg_axi_read_in_monitor_struct);\ + endfunction\ + + `define fuse_ctrl_secreg_axi_read_in_FROM_MONITOR_STRUCT_FUNCTION \ + virtual function void from_monitor_struct(fuse_ctrl_secreg_axi_read_in_monitor_s fuse_ctrl_secreg_axi_read_in_monitor_struct);\ + {\ + this.secreg_araddr , \ + this.secreg_arvalid , \ + this.secreg_arburst , \ + this.secreg_arsize , \ + this.secreg_arlen , \ + this.secreg_aruser , \ + this.secreg_arid , \ + this.secreg_arlock , \ + this.secreg_rready \ + } = fuse_ctrl_secreg_axi_read_in_monitor_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_initiator_struct +// and from_initiator_struct methods of the fuse_ctrl_secreg_axi_read_in_transaction class. +// Also update the comments in the driver BFM. +// + `define fuse_ctrl_secreg_axi_read_in_INITIATOR_STRUCT typedef struct packed { \ + logic [AW-1:0] secreg_araddr ; \ + logic secreg_arvalid ; \ + logic [$bits(axi_pkg::axi_burst_e)] secreg_arburst ; \ + logic [2:0] secreg_arsize ; \ + logic [7:0] secreg_arlen ; \ + logic [UW-1:0] secreg_aruser ; \ + logic [IW-1:0] secreg_arid ; \ + logic secreg_arlock ; \ + logic secreg_rready ; \ + } fuse_ctrl_secreg_axi_read_in_initiator_s; + + `define fuse_ctrl_secreg_axi_read_in_TO_INITIATOR_STRUCT_FUNCTION \ + virtual function fuse_ctrl_secreg_axi_read_in_initiator_s to_initiator_struct();\ + fuse_ctrl_secreg_axi_read_in_initiator_struct = \ + {\ + this.secreg_araddr , \ + this.secreg_arvalid , \ + this.secreg_arburst , \ + this.secreg_arsize , \ + this.secreg_arlen , \ + this.secreg_aruser , \ + this.secreg_arid , \ + this.secreg_arlock , \ + this.secreg_rready \ + };\ + return ( fuse_ctrl_secreg_axi_read_in_initiator_struct);\ + endfunction + + `define fuse_ctrl_secreg_axi_read_in_FROM_INITIATOR_STRUCT_FUNCTION \ + virtual function void from_initiator_struct(fuse_ctrl_secreg_axi_read_in_initiator_s fuse_ctrl_secreg_axi_read_in_initiator_struct);\ + {\ + this.secreg_araddr , \ + this.secreg_arvalid , \ + this.secreg_arburst , \ + this.secreg_arsize , \ + this.secreg_arlen , \ + this.secreg_aruser , \ + this.secreg_arid , \ + this.secreg_arlock , \ + this.secreg_rready \ + } = fuse_ctrl_secreg_axi_read_in_initiator_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_responder_struct +// and from_responder_struct methods of the fuse_ctrl_secreg_axi_read_in_transaction class. +// Also update the comments in the driver BFM. +// + `define fuse_ctrl_secreg_axi_read_in_RESPONDER_STRUCT typedef struct packed { \ + logic [AW-1:0] secreg_araddr ; \ + logic secreg_arvalid ; \ + logic [$bits(axi_pkg::axi_burst_e)] secreg_arburst ; \ + logic [2:0] secreg_arsize ; \ + logic [7:0] secreg_arlen ; \ + logic [UW-1:0] secreg_aruser ; \ + logic [IW-1:0] secreg_arid ; \ + logic secreg_arlock ; \ + logic secreg_rready ; \ + } fuse_ctrl_secreg_axi_read_in_responder_s; + + `define fuse_ctrl_secreg_axi_read_in_TO_RESPONDER_STRUCT_FUNCTION \ + virtual function fuse_ctrl_secreg_axi_read_in_responder_s to_responder_struct();\ + fuse_ctrl_secreg_axi_read_in_responder_struct = \ + {\ + this.secreg_araddr , \ + this.secreg_arvalid , \ + this.secreg_arburst , \ + this.secreg_arsize , \ + this.secreg_arlen , \ + this.secreg_aruser , \ + this.secreg_arid , \ + this.secreg_arlock , \ + this.secreg_rready \ + };\ + return ( fuse_ctrl_secreg_axi_read_in_responder_struct);\ + endfunction + + `define fuse_ctrl_secreg_axi_read_in_FROM_RESPONDER_STRUCT_FUNCTION \ + virtual function void from_responder_struct(fuse_ctrl_secreg_axi_read_in_responder_s fuse_ctrl_secreg_axi_read_in_responder_struct);\ + {\ + this.secreg_araddr , \ + this.secreg_arvalid , \ + this.secreg_arburst , \ + this.secreg_arsize , \ + this.secreg_arlen , \ + this.secreg_aruser , \ + this.secreg_arid , \ + this.secreg_arlock , \ + this.secreg_rready \ + } = fuse_ctrl_secreg_axi_read_in_responder_struct;\ + endfunction +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_monitor.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_monitor.svh new file mode 100644 index 0000000..b137238 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_monitor.svh @@ -0,0 +1,126 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class receives fuse_ctrl_secreg_axi_read_in transactions observed by the +// fuse_ctrl_secreg_axi_read_in monitor BFM and broadcasts them through the analysis port +// on the agent. It accesses the monitor BFM through the monitor +// task. This UVM component captures transactions +// for viewing in the waveform viewer if the +// enable_transaction_viewing flag is set in the configuration. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_secreg_axi_read_in_monitor #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvmf_monitor_base #( + .CONFIG_T(fuse_ctrl_secreg_axi_read_in_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .BFM_BIND_T(virtual fuse_ctrl_secreg_axi_read_in_monitor_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .TRANS_T(fuse_ctrl_secreg_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ))); + + `uvm_component_param_utils( fuse_ctrl_secreg_axi_read_in_monitor #( + AW, + DW, + IW, + UW + )) + +// Structure used to pass data from monitor BFM to monitor class in agent. +// Use to_monitor_struct function to pack transaction variables into structure. +// Use from_monitor_struct function to unpack transaction variables from structure. +`fuse_ctrl_secreg_axi_read_in_MONITOR_STRUCT + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the monitor BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// monitor BFM. This allows the monitor BFM to call the notify_transaction +// function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// *************************************************************************** + virtual task run_phase(uvm_phase phase); + // Start monitor BFM thread and don't call super.run() in order to + // override the default monitor proxy 'pull' behavior with the more + // emulation-friendly BFM 'push' approach using the notify_transaction + // function below + bfm.start_monitoring(); + endtask + +// ************************************************************************** + +// This function is called by the monitor BFM. It receives data observed by the +// monitor BFM. Data is passed using the fuse_ctrl_secreg_axi_read_in_monitor_struct. + virtual function void notify_transaction(input fuse_ctrl_secreg_axi_read_in_monitor_s fuse_ctrl_secreg_axi_read_in_monitor_struct); + + + trans = new("trans"); + trans.from_monitor_struct(fuse_ctrl_secreg_axi_read_in_monitor_struct); + trans.start_time = time_stamp; + trans.end_time = $time; + time_stamp = trans.end_time; + + analyze(trans); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_monitor_bfm.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_monitor_bfm.sv new file mode 100644 index 0000000..11f9b2c --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_monitor_bfm.sv @@ -0,0 +1,230 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface performs the fuse_ctrl_secreg_axi_read_in signal monitoring. +// It is accessed by the uvm fuse_ctrl_secreg_axi_read_in monitor through a virtual +// interface handle in the fuse_ctrl_secreg_axi_read_in configuration. It monitors the +// signals passed in through the port connection named bus of +// type fuse_ctrl_secreg_axi_read_in_if. +// +// Input signals from the fuse_ctrl_secreg_axi_read_in_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// Interface functions and tasks used by UVM components: +// monitor(inout TRANS_T txn); +// This task receives the transaction, txn, from the +// UVM monitor and then populates variables in txn +// from values observed on bus activity. This task +// blocks until an operation on the fuse_ctrl_secreg_axi_read_in bus is complete. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_secreg_axi_read_in_pkg_hdl::*; +`include "src/fuse_ctrl_secreg_axi_read_in_macros.svh" + + +interface fuse_ctrl_secreg_axi_read_in_monitor_bfm #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + ( fuse_ctrl_secreg_axi_read_in_if bus ); + // The pragma below and additional ones in-lined further down are for running this BFM on Veloce + // pragma attribute fuse_ctrl_secreg_axi_read_in_monitor_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: AW=%x DW=%x IW=%x UW=%x ", AW,DW,IW,UW), + UVM_DEBUG) +end +`endif + + + // Structure used to pass transaction data from monitor BFM to monitor class in agent. +`fuse_ctrl_secreg_axi_read_in_MONITOR_STRUCT + fuse_ctrl_secreg_axi_read_in_monitor_s fuse_ctrl_secreg_axi_read_in_monitor_struct; + + // Structure used to pass configuration data from monitor class to monitor BFM. + `fuse_ctrl_secreg_axi_read_in_CONFIGURATION_STRUCT + + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + tri clk_i_i; + tri rst_ni_i; + tri [AW-1:0] araddr_i; + tri [$bits(axi_pkg::axi_burst_e)-1:0] arburst_i; + tri [2:0] arsize_i; + tri [7:0] arlen_i; + tri [UW-1:0] aruser_i; + tri [IW-1:0] arid_i; + tri arlock_i; + tri arvalid_i; + tri rready_i; + assign clk_i_i = bus.clk_i; + assign rst_ni_i = bus.rst_ni; + assign araddr_i = bus.araddr; + assign arburst_i = bus.arburst; + assign arsize_i = bus.arsize; + assign arlen_i = bus.arlen; + assign aruser_i = bus.aruser; + assign arid_i = bus.arid; + assign arlock_i = bus.arlock; + assign arvalid_i = bus.arvalid; + assign rready_i = bus.rready; + + // Proxy handle to UVM monitor + fuse_ctrl_secreg_axi_read_in_pkg::fuse_ctrl_secreg_axi_read_in_monitor #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) proxy; + // pragma tbx oneway proxy.notify_transaction + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + task wait_for_reset();// pragma tbx xtf + @(posedge clk_i_i) ; + do_wait_for_reset(); + endtask + + // **************************************************************************** + task do_wait_for_reset(); + // pragma uvmf custom reset_condition begin + wait ( rst_ni_i === 1 ) ; + @(posedge clk_i_i) ; + // pragma uvmf custom reset_condition end + endtask + + //****************************************************************** + + task wait_for_num_clocks(input int unsigned count); // pragma tbx xtf + @(posedge clk_i_i); + + repeat (count-1) @(posedge clk_i_i); + endtask + + //****************************************************************** + event go; + function void start_monitoring();// pragma tbx xtf + -> go; + endfunction + + // **************************************************************************** + initial begin + @go; + forever begin + @(posedge clk_i_i); + do_monitor( fuse_ctrl_secreg_axi_read_in_monitor_struct ); + + + proxy.notify_transaction( fuse_ctrl_secreg_axi_read_in_monitor_struct ); + + end + end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the monitor BFM. It is called by the monitor within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the monitor BFM needs to be aware of the new configuration + // variables. + // + function void configure(fuse_ctrl_secreg_axi_read_in_configuration_s fuse_ctrl_secreg_axi_read_in_configuration_arg); // pragma tbx xtf + initiator_responder = fuse_ctrl_secreg_axi_read_in_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + + + // **************************************************************************** + + task do_monitor(output fuse_ctrl_secreg_axi_read_in_monitor_s fuse_ctrl_secreg_axi_read_in_monitor_struct); + // + // Available struct members: + // // fuse_ctrl_secreg_axi_read_in_monitor_struct.secreg_araddr + // // fuse_ctrl_secreg_axi_read_in_monitor_struct.secreg_arvalid + // // fuse_ctrl_secreg_axi_read_in_monitor_struct.secreg_arburst + // // fuse_ctrl_secreg_axi_read_in_monitor_struct.secreg_arsize + // // fuse_ctrl_secreg_axi_read_in_monitor_struct.secreg_arlen + // // fuse_ctrl_secreg_axi_read_in_monitor_struct.secreg_aruser + // // fuse_ctrl_secreg_axi_read_in_monitor_struct.secreg_arid + // // fuse_ctrl_secreg_axi_read_in_monitor_struct.secreg_arlock + // // fuse_ctrl_secreg_axi_read_in_monitor_struct.secreg_rready + // // + // Reference code; + // How to wait for signal value + // while (control_signal === 1'b1) @(posedge clk_i_i); + // + // How to assign a struct member, named xyz, from a signal. + // All available input signals listed. + // fuse_ctrl_secreg_axi_read_in_monitor_struct.xyz = araddr_i; // [AW-1:0] + // fuse_ctrl_secreg_axi_read_in_monitor_struct.xyz = arburst_i; // [$bits(axi_pkg::axi_burst_e)-1:0] + // fuse_ctrl_secreg_axi_read_in_monitor_struct.xyz = arsize_i; // [2:0] + // fuse_ctrl_secreg_axi_read_in_monitor_struct.xyz = arlen_i; // [7:0] + // fuse_ctrl_secreg_axi_read_in_monitor_struct.xyz = aruser_i; // [UW-1:0] + // fuse_ctrl_secreg_axi_read_in_monitor_struct.xyz = arid_i; // [IW-1:0] + // fuse_ctrl_secreg_axi_read_in_monitor_struct.xyz = arlock_i; // + // fuse_ctrl_secreg_axi_read_in_monitor_struct.xyz = arvalid_i; // + // fuse_ctrl_secreg_axi_read_in_monitor_struct.xyz = rready_i; // + // pragma uvmf custom do_monitor begin + // UVMF_CHANGE_ME : Implement protocol monitoring. The commented reference code + // below are examples of how to capture signal values and assign them to + // structure members. All available input signals are listed. The 'while' + // code example shows how to wait for a synchronous flow control signal. This + // task should return when a complete transfer has been observed. Once this task is + // exited with captured values, it is then called again to wait for and observe + // the next transfer. One clock cycle is consumed between calls to do_monitor. + @(posedge clk_i_i); + @(posedge clk_i_i); + @(posedge clk_i_i); + @(posedge clk_i_i); + // pragma uvmf custom do_monitor end + endtask + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_random_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_random_sequence.svh new file mode 100644 index 0000000..1d7b7b6 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_random_sequence.svh @@ -0,0 +1,87 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This sequences randomizes the fuse_ctrl_secreg_axi_read_in transaction and sends it +// to the UVM driver. +// +// This sequence constructs and randomizes a fuse_ctrl_secreg_axi_read_in_transaction. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_secreg_axi_read_in_random_sequence #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends fuse_ctrl_secreg_axi_read_in_sequence_base #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ); + + `uvm_object_param_utils( fuse_ctrl_secreg_axi_read_in_random_sequence #( + AW, + DW, + IW, + UW + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //***************************************************************** + function new(string name = ""); + super.new(name); + endfunction: new + + // **************************************************************************** + // TASK : body() + // This task is automatically executed when this sequence is started using the + // start(sequencerHandle) task. + // + task body(); + + // Construct the transaction + req=fuse_ctrl_secreg_axi_read_in_transaction#( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )::type_id::create("req"); + start_item(req); + // Randomize the transaction + if(!req.randomize()) `uvm_fatal("SEQ", "fuse_ctrl_secreg_axi_read_in_random_sequence::body()-fuse_ctrl_secreg_axi_read_in_transaction randomization failed") + // Send the transaction to the fuse_ctrl_secreg_axi_read_in_driver_bfm via the sequencer and fuse_ctrl_secreg_axi_read_in_driver. + finish_item(req); + `uvm_info("SEQ", {"Response:",req.convert2string()},UVM_MEDIUM) + + endtask + +endclass: fuse_ctrl_secreg_axi_read_in_random_sequence + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_responder_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_responder_sequence.svh new file mode 100644 index 0000000..875ef73 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_responder_sequence.svh @@ -0,0 +1,83 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class can be used to provide stimulus when an interface +// has been configured to run in a responder mode. It +// will never finish by default, always going back to the driver +// and driver BFM for the next transaction with which to respond. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_secreg_axi_read_in_responder_sequence #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends fuse_ctrl_secreg_axi_read_in_sequence_base #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ); + + `uvm_object_param_utils( fuse_ctrl_secreg_axi_read_in_responder_sequence #( + AW, + DW, + IW, + UW + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "fuse_ctrl_secreg_axi_read_in_responder_sequence"); + super.new(name); + endfunction + + task body(); + req=fuse_ctrl_secreg_axi_read_in_transaction#( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )::type_id::create("req"); + forever begin + start_item(req); + finish_item(req); + // pragma uvmf custom body begin + // UVMF_CHANGE_ME : Do something here with the resulting req item. The + // finish_item() call above will block until the req transaction is ready + // to be handled by the responder sequence. + // If this was an item that required a response, the expectation is + // that the response should be populated within this transaction now. + `uvm_info("SEQ",$sformatf("Processed txn: %s",req.convert2string()),UVM_HIGH) + // pragma uvmf custom body end + end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_sequence_base.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_sequence_base.svh new file mode 100644 index 0000000..8454209 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_sequence_base.svh @@ -0,0 +1,140 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the class used as the base class for all sequences +// for this interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_secreg_axi_read_in_sequence_base #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvmf_sequence_base #( + .REQ(fuse_ctrl_secreg_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .RSP(fuse_ctrl_secreg_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ))); + + `uvm_object_param_utils( fuse_ctrl_secreg_axi_read_in_sequence_base #( + AW, + DW, + IW, + UW + )) + + // variables + typedef fuse_ctrl_secreg_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) fuse_ctrl_secreg_axi_read_in_transaction_req_t; + fuse_ctrl_secreg_axi_read_in_transaction_req_t req; + typedef fuse_ctrl_secreg_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) fuse_ctrl_secreg_axi_read_in_transaction_rsp_t; + fuse_ctrl_secreg_axi_read_in_transaction_rsp_t rsp; + + // Event for identifying when a response was received from the sequencer + event new_rsp; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // TASK : get_responses() + // This task recursively gets sequence item responses from the sequencer. + // + virtual task get_responses(); + fork + begin + // Block until new rsp available + get_response(rsp); + // New rsp received. Indicate to sequence using event. + ->new_rsp; + // Display the received response transaction + `uvm_info("SEQ", {"New response transaction:",rsp.convert2string()}, UVM_MEDIUM) + end + join_none + endtask + + // **************************************************************************** + // TASK : pre_body() + // This task is called automatically when start is called with call_pre_post set to 1 (default). + // By calling get_responses() within pre_body() any derived sequences are automatically + // processing response transactions. Only un-comment this call to get_responses() if you + // have configured the interface driver to utilize the response transaction path by setting + // the configuration variable "return_transaction_response" to 1. Otherwise it is possible + // to impact runtime performance and memory utilization. + // + virtual task pre_body(); + // pragma uvmf custom pre_body begin +// get_responses(); + // pragma uvmf custom pre_body end + endtask + + // **************************************************************************** + // TASK : body() + // This task is called automatically when start is called. This sequence sends + // a req sequence item to the sequencer identified as an argument in the call + // to start. + // + virtual task body(); + // pragma uvmf custom body begin + start_item(req); + finish_item(req); + // pragma uvmf custom body end + endtask + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name =""); + super.new( name ); + // pragma uvmf custom new begin + req = fuse_ctrl_secreg_axi_read_in_transaction_req_t::type_id::create("req"); + rsp = fuse_ctrl_secreg_axi_read_in_transaction_rsp_t::type_id::create("rsp"); + // pragma uvmf custom new end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_transaction.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_transaction.svh new file mode 100644 index 0000000..35ecfae --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_transaction.svh @@ -0,0 +1,239 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class defines the variables required for an fuse_ctrl_secreg_axi_read_in +// transaction. Class variables to be displayed in waveform transaction +// viewing are added to the transaction viewing stream in the add_to_wave +// function. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_secreg_axi_read_in_transaction #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvmf_transaction_base; + + `uvm_object_param_utils( fuse_ctrl_secreg_axi_read_in_transaction #( + AW, + DW, + IW, + UW + )) + + rand logic [AW-1:0] secreg_araddr ; + logic secreg_arvalid ; + logic [$bits(axi_pkg::axi_burst_e)] secreg_arburst ; + logic [2:0] secreg_arsize ; + logic [7:0] secreg_arlen ; + logic [UW-1:0] secreg_aruser ; + logic [IW-1:0] secreg_arid ; + logic secreg_arlock ; + logic secreg_rready ; + + //Constraints for the transaction variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //******************************************************************* + //******************************************************************* + // Macros that define structs and associated functions are + // located in fuse_ctrl_secreg_axi_read_in_macros.svh + + //******************************************************************* + // Monitor macro used by fuse_ctrl_secreg_axi_read_in_monitor and fuse_ctrl_secreg_axi_read_in_monitor_bfm + // This struct is defined in fuse_ctrl_secreg_axi_read_in_macros.svh + `fuse_ctrl_secreg_axi_read_in_MONITOR_STRUCT + fuse_ctrl_secreg_axi_read_in_monitor_s fuse_ctrl_secreg_axi_read_in_monitor_struct; + //******************************************************************* + // FUNCTION: to_monitor_struct() + // This function packs transaction variables into a fuse_ctrl_secreg_axi_read_in_monitor_s + // structure. The function returns the handle to the fuse_ctrl_secreg_axi_read_in_monitor_struct. + // This function is defined in fuse_ctrl_secreg_axi_read_in_macros.svh + `fuse_ctrl_secreg_axi_read_in_TO_MONITOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_monitor_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_secreg_axi_read_in_macros.svh + `fuse_ctrl_secreg_axi_read_in_FROM_MONITOR_STRUCT_FUNCTION + + //******************************************************************* + // Initiator macro used by fuse_ctrl_secreg_axi_read_in_driver and fuse_ctrl_secreg_axi_read_in_driver_bfm + // to communicate initiator driven data to fuse_ctrl_secreg_axi_read_in_driver_bfm. + // This struct is defined in fuse_ctrl_secreg_axi_read_in_macros.svh + `fuse_ctrl_secreg_axi_read_in_INITIATOR_STRUCT + fuse_ctrl_secreg_axi_read_in_initiator_s fuse_ctrl_secreg_axi_read_in_initiator_struct; + //******************************************************************* + // FUNCTION: to_initiator_struct() + // This function packs transaction variables into a fuse_ctrl_secreg_axi_read_in_initiator_s + // structure. The function returns the handle to the fuse_ctrl_secreg_axi_read_in_initiator_struct. + // This function is defined in fuse_ctrl_secreg_axi_read_in_macros.svh + `fuse_ctrl_secreg_axi_read_in_TO_INITIATOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_initiator_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_secreg_axi_read_in_macros.svh + `fuse_ctrl_secreg_axi_read_in_FROM_INITIATOR_STRUCT_FUNCTION + + //******************************************************************* + // Responder macro used by fuse_ctrl_secreg_axi_read_in_driver and fuse_ctrl_secreg_axi_read_in_driver_bfm + // to communicate Responder driven data to fuse_ctrl_secreg_axi_read_in_driver_bfm. + // This struct is defined in fuse_ctrl_secreg_axi_read_in_macros.svh + `fuse_ctrl_secreg_axi_read_in_RESPONDER_STRUCT + fuse_ctrl_secreg_axi_read_in_responder_s fuse_ctrl_secreg_axi_read_in_responder_struct; + //******************************************************************* + // FUNCTION: to_responder_struct() + // This function packs transaction variables into a fuse_ctrl_secreg_axi_read_in_responder_s + // structure. The function returns the handle to the fuse_ctrl_secreg_axi_read_in_responder_struct. + // This function is defined in fuse_ctrl_secreg_axi_read_in_macros.svh + `fuse_ctrl_secreg_axi_read_in_TO_RESPONDER_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_responder_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_secreg_axi_read_in_macros.svh + `fuse_ctrl_secreg_axi_read_in_FROM_RESPONDER_STRUCT_FUNCTION + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + endfunction + + // **************************************************************************** + // FUNCTION: convert2string() + // This function converts all variables in this class to a single string for + // logfile reporting. + // + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + // UVMF_CHANGE_ME : Customize format if desired. + return $sformatf("secreg_araddr:0x%x secreg_arvalid:0x%x secreg_arburst:0x%x secreg_arsize:0x%x secreg_arlen:0x%x secreg_aruser:0x%x secreg_arid:0x%x secreg_arlock:0x%x secreg_rready:0x%x ",secreg_araddr,secreg_arvalid,secreg_arburst,secreg_arsize,secreg_arlen,secreg_aruser,secreg_arid,secreg_arlock,secreg_rready); + // pragma uvmf custom convert2string end + endfunction + + //******************************************************************* + // FUNCTION: do_print() + // This function is automatically called when the .print() function + // is called on this class. + // + virtual function void do_print(uvm_printer printer); + // pragma uvmf custom do_print begin + // UVMF_CHANGE_ME : Current contents of do_print allows for the use of UVM 1.1d, 1.2 or P1800.2. + // Update based on your own printing preference according to your preferred UVM version + $display(convert2string()); + // pragma uvmf custom do_print end + endfunction + + //******************************************************************* + // FUNCTION: do_compare() + // This function is automatically called when the .compare() function + // is called on this class. + // + virtual function bit do_compare (uvm_object rhs, uvm_comparer comparer); + fuse_ctrl_secreg_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) RHS; + if (!$cast(RHS,rhs)) return 0; + // pragma uvmf custom do_compare begin + // UVMF_CHANGE_ME : Eliminate comparison of variables not to be used for compare + return (super.do_compare(rhs,comparer) + ); + // pragma uvmf custom do_compare end + endfunction + + //******************************************************************* + // FUNCTION: do_copy() + // This function is automatically called when the .copy() function + // is called on this class. + // + virtual function void do_copy (uvm_object rhs); + fuse_ctrl_secreg_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) RHS; + assert($cast(RHS,rhs)); + // pragma uvmf custom do_copy begin + super.do_copy(rhs); + this.secreg_araddr = RHS.secreg_araddr; + this.secreg_arvalid = RHS.secreg_arvalid; + this.secreg_arburst = RHS.secreg_arburst; + this.secreg_arsize = RHS.secreg_arsize; + this.secreg_arlen = RHS.secreg_arlen; + this.secreg_aruser = RHS.secreg_aruser; + this.secreg_arid = RHS.secreg_arid; + this.secreg_arlock = RHS.secreg_arlock; + this.secreg_rready = RHS.secreg_rready; + // pragma uvmf custom do_copy end + endfunction + + // **************************************************************************** + // FUNCTION: add_to_wave() + // This function is used to display variables in this class in the waveform + // viewer. The start_time and end_time variables must be set before this + // function is called. If the start_time and end_time variables are not set + // the transaction will be hidden at 0ns on the waveform display. + // + virtual function void add_to_wave(int transaction_viewing_stream_h); + `ifdef QUESTA + if (transaction_view_h == 0) begin + transaction_view_h = $begin_transaction(transaction_viewing_stream_h,"fuse_ctrl_secreg_axi_read_in_transaction",start_time); + end + super.add_to_wave(transaction_view_h); + // pragma uvmf custom add_to_wave begin + // UVMF_CHANGE_ME : Color can be applied to transaction entries based on content, example below + // case() + // 1 : $add_color(transaction_view_h,"red"); + // default : $add_color(transaction_view_h,"grey"); + // endcase + // UVMF_CHANGE_ME : Eliminate transaction variables not wanted in transaction viewing in the waveform viewer + $add_attribute(transaction_view_h,secreg_araddr,"secreg_araddr"); + $add_attribute(transaction_view_h,secreg_arvalid,"secreg_arvalid"); + $add_attribute(transaction_view_h,secreg_arburst,"secreg_arburst"); + $add_attribute(transaction_view_h,secreg_arsize,"secreg_arsize"); + $add_attribute(transaction_view_h,secreg_arlen,"secreg_arlen"); + $add_attribute(transaction_view_h,secreg_aruser,"secreg_aruser"); + $add_attribute(transaction_view_h,secreg_arid,"secreg_arid"); + $add_attribute(transaction_view_h,secreg_arlock,"secreg_arlock"); + $add_attribute(transaction_view_h,secreg_rready,"secreg_rready"); + // pragma uvmf custom add_to_wave end + $end_transaction(transaction_view_h,end_time); + $free_transaction(transaction_view_h); + `endif // QUESTA + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_transaction_coverage.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_transaction_coverage.svh new file mode 100644 index 0000000..e46fe52 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_transaction_coverage.svh @@ -0,0 +1,107 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class records fuse_ctrl_secreg_axi_read_in transaction information using +// a covergroup named fuse_ctrl_secreg_axi_read_in_transaction_cg. An instance of this +// coverage component is instantiated in the uvmf_parameterized_agent +// if the has_coverage flag is set. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_secreg_axi_read_in_transaction_coverage #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvm_subscriber #(.T(fuse_ctrl_secreg_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ))); + + `uvm_component_param_utils( fuse_ctrl_secreg_axi_read_in_transaction_coverage #( + AW, + DW, + IW, + UW + )) + + T coverage_trans; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + covergroup fuse_ctrl_secreg_axi_read_in_transaction_cg; + // pragma uvmf custom covergroup begin + // UVMF_CHANGE_ME : Add coverage bins, crosses, exclusions, etc. according to coverage needs. + option.auto_bin_max=1024; + option.per_instance=1; + secreg_araddr: coverpoint coverage_trans.secreg_araddr; + secreg_arvalid: coverpoint coverage_trans.secreg_arvalid; + secreg_arburst: coverpoint coverage_trans.secreg_arburst; + secreg_arsize: coverpoint coverage_trans.secreg_arsize; + secreg_arlen: coverpoint coverage_trans.secreg_arlen; + secreg_aruser: coverpoint coverage_trans.secreg_aruser; + secreg_arid: coverpoint coverage_trans.secreg_arid; + secreg_arlock: coverpoint coverage_trans.secreg_arlock; + secreg_rready: coverpoint coverage_trans.secreg_rready; + // pragma uvmf custom covergroup end + endgroup + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new(string name="", uvm_component parent=null); + super.new(name,parent); + fuse_ctrl_secreg_axi_read_in_transaction_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that transaction variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + endfunction + + // **************************************************************************** + // FUNCTION : build_phase() + // This function is the standard UVM build_phase. + // + function void build_phase(uvm_phase phase); + fuse_ctrl_secreg_axi_read_in_transaction_cg.set_inst_name($sformatf("fuse_ctrl_secreg_axi_read_in_transaction_cg_%s",get_full_name())); + endfunction + + // **************************************************************************** + // FUNCTION: write (T t) + // This function is automatically executed when a transaction arrives on the + // analysis_export. It copies values from the variables in the transaction + // to local variables used to collect functional coverage. + // + virtual function void write (T t); + `uvm_info("COV","Received transaction",UVM_HIGH); + coverage_trans = t; + fuse_ctrl_secreg_axi_read_in_transaction_cg.sample(); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_typedefs.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_typedefs.svh new file mode 100644 index 0000000..f2a7bdb --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_typedefs.svh @@ -0,0 +1,34 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the host server when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_typedefs_hdl.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_typedefs_hdl.svh new file mode 100644 index 0000000..0d58518 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_typedefs_hdl.svh @@ -0,0 +1,35 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the emulator when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/yaml/fuse_ctrl_secreg_axi_read_in_interface.yaml b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/yaml/fuse_ctrl_secreg_axi_read_in_interface.yaml new file mode 100644 index 0000000..a5ff8dd --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/yaml/fuse_ctrl_secreg_axi_read_in_interface.yaml @@ -0,0 +1,121 @@ +uvmf: + interfaces: + fuse_ctrl_secreg_axi_read_in: + clock: clk_i + config_constraints: [] + config_vars: [] + existing_library_component: 'True' + gen_inbound_streaming_driver: 'False' + hdl_pkg_parameters: [] + hdl_typedefs: [] + hvl_pkg_parameters: [] + hvl_typedefs: [] + parameters: + - name: AW + type: int + value: '32' + - name: DW + type: int + value: '32' + - name: IW + type: int + value: '3' + - name: UW + type: int + value: '32' + ports: + - dir: output + name: araddr + reset_value: '''bz' + width: '[''AW'']' + - dir: output + name: arburst + reset_value: '''bz' + width: '[''$bits(axi_pkg::axi_burst_e)'']' + - dir: output + name: arsize + reset_value: '''bz' + width: '3' + - dir: output + name: arlen + reset_value: '''bz' + width: '8' + - dir: output + name: aruser + reset_value: '''bz' + width: '[''UW'']' + - dir: output + name: arid + reset_value: '''bz' + width: '[''IW'']' + - dir: output + name: arlock + reset_value: '''bz' + width: '1' + - dir: output + name: arvalid + reset_value: '''bz' + width: '1' + - dir: output + name: rready + reset_value: '''bz' + width: '1' + reset: rst_ni + reset_assertion_level: 'False' + transaction_constraints: [] + transaction_vars: + - comment: '' + iscompare: 'False' + isrand: 'True' + name: secreg_araddr + type: logic [AW-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: secreg_arvalid + type: logic + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: secreg_arburst + type: logic [$bits(axi_pkg::axi_burst_e)] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: secreg_arsize + type: logic [2:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: secreg_arlen + type: logic [7:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: secreg_aruser + type: logic [UW-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: secreg_arid + type: logic [IW-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: secreg_arlock + type: logic + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: secreg_rready + type: logic + unpacked_dimension: '' + use_dpi_link: 'False' diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/.project b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/.project new file mode 100644 index 0000000..615ab14 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/.project @@ -0,0 +1,30 @@ + + + fuse_ctrl_secreg_axi_read_out_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/.svproject b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/.svproject new file mode 100644 index 0000000..9d45666 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/Makefile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/Makefile new file mode 100644 index 0000000..2b62709 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/Makefile @@ -0,0 +1,66 @@ +# fuse_ctrl_secreg_axi_read_out interface packages source +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +fuse_ctrl_secreg_axi_read_out_PKG = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_filelist_hvl.f + +fuse_ctrl_secreg_axi_read_out_PKG_HDL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_filelist_hdl.f + +fuse_ctrl_secreg_axi_read_out_PKG_XRTL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_filelist_xrtl.f + +COMP_fuse_ctrl_secreg_axi_read_out_PKG_TGT_0 = q_comp_fuse_ctrl_secreg_axi_read_out_pkg +COMP_fuse_ctrl_secreg_axi_read_out_PKG_TGT_1 = v_comp_fuse_ctrl_secreg_axi_read_out_pkg +COMP_fuse_ctrl_secreg_axi_read_out_PKG_TGT = $(COMP_fuse_ctrl_secreg_axi_read_out_PKG_TGT_$(USE_VELOCE)) + +comp_fuse_ctrl_secreg_axi_read_out_pkg: $(COMP_fuse_ctrl_secreg_axi_read_out_PKG_TGT) + +q_comp_fuse_ctrl_secreg_axi_read_out_pkg: + $(HDL_COMP_CMD) $(fuse_ctrl_secreg_axi_read_out_PKG_HDL) + $(HVL_COMP_CMD) $(fuse_ctrl_secreg_axi_read_out_PKG) + $(HDL_COMP_CMD) $(fuse_ctrl_secreg_axi_read_out_PKG_XRTL) + +v_comp_fuse_ctrl_secreg_axi_read_out_pkg: + $(HVL_COMP_CMD) $(fuse_ctrl_secreg_axi_read_out_PKG_HDL) + $(HVL_COMP_CMD) $(fuse_ctrl_secreg_axi_read_out_PKG) + $(VELANALYZE_CMD) $(fuse_ctrl_secreg_axi_read_out_PKG_HDL) + $(VELANALYZE_HVL_CMD) $(fuse_ctrl_secreg_axi_read_out_PKG) + $(HDL_COMP_CMD) $(fuse_ctrl_secreg_axi_read_out_PKG_XRTL) + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export fuse_ctrl_secreg_axi_read_out_IF_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/dpi + +C_FILE_COMPILE_LIST_fuse_ctrl_secreg_axi_read_out_pkg = \ + +O_FILE_COMPILE_LIST_fuse_ctrl_secreg_axi_read_out_pkg = $(notdir $(C_FILE_COMPILE_LIST_fuse_ctrl_secreg_axi_read_out_pkg:.c=.o)) + +GCC_COMP_ARGS_fuse_ctrl_secreg_axi_read_out_pkg += -I$(fuse_ctrl_secreg_axi_read_out_IF_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_fuse_ctrl_secreg_axi_read_out_pkg += $(fuse_ctrl_secreg_axi_read_out_IF_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_fuse_ctrl_secreg_axi_read_out_pkg += \ + \ + -o .so + +comp_fuse_ctrl_secreg_axi_read_out_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Interface C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_fuse_ctrl_secreg_axi_read_out_pkg) $(C_FILE_COMPILE_LIST_fuse_ctrl_secreg_axi_read_out_pkg) + @echo "--------------------------------" + @echo "Linking Interface C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_fuse_ctrl_secreg_axi_read_out_pkg) $(O_FILE_COMPILE_LIST_fuse_ctrl_secreg_axi_read_out_pkg) + @echo "--------------------------------" + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/compile.do b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/compile.do new file mode 100644 index 0000000..76aa3ca --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/compile.do @@ -0,0 +1,14 @@ +# Tcl do file for compile of fuse_ctrl_secreg_axi_read_out interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_filelist_hdl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_filelist_hvl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_filelist_xrtl.f \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out.compile new file mode 100644 index 0000000..630dad5 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out.compile @@ -0,0 +1,3 @@ +needs: + - fuse_ctrl_secreg_axi_read_out_hvl.compile + - fuse_ctrl_secreg_axi_read_out_hdl.compile diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_bfm.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_bfm.vinfo new file mode 100644 index 0000000..ecf711b --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_bfm.vinfo @@ -0,0 +1,6 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use fuse_ctrl_secreg_axi_read_out_pkg_hdl.vinfo ++incdir+@vinfodir +src/fuse_ctrl_secreg_axi_read_out_if.sv +src/fuse_ctrl_secreg_axi_read_out_driver_bfm.sv +src/fuse_ctrl_secreg_axi_read_out_monitor_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_common.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_common.compile new file mode 100644 index 0000000..ab88d14 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_common.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +incdir: + - . + - ${uvm_path}/src +src: + - fuse_ctrl_secreg_axi_read_out_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_filelist_hdl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_filelist_hdl.f new file mode 100644 index 0000000..5665d94 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_filelist_hdl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_filelist_hvl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_filelist_hvl.f new file mode 100644 index 0000000..dd6d2e7 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_filelist_hvl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_pkg.sv \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_filelist_xrtl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_filelist_xrtl.f new file mode 100644 index 0000000..39d2672 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_filelist_xrtl.f @@ -0,0 +1,3 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_if.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_monitor_bfm.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_driver_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_hdl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_hdl.compile new file mode 100644 index 0000000..7def000 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_hdl.compile @@ -0,0 +1,9 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ./fuse_ctrl_secreg_axi_read_out_common.compile +incdir: + - . +src: + - src/fuse_ctrl_secreg_axi_read_out_if.sv + - src/fuse_ctrl_secreg_axi_read_out_monitor_bfm.sv + - src/fuse_ctrl_secreg_axi_read_out_driver_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_hvl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_hvl.compile new file mode 100644 index 0000000..b4a074d --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_hvl.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ./fuse_ctrl_secreg_axi_read_out_common.compile +incdir: + - . +src: + - fuse_ctrl_secreg_axi_read_out_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_pkg.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_pkg.sv new file mode 100644 index 0000000..e5e0fb1 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_pkg.sv @@ -0,0 +1,91 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - + +// - +// - +// - + +// - +// - +// - + +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_secreg_axi_read_out_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg_hdl::*; + import uvmf_base_pkg::*; + import fuse_ctrl_secreg_axi_read_out_pkg_hdl::*; + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + `include "src/fuse_ctrl_secreg_axi_read_out_macros.svh" + + export fuse_ctrl_secreg_axi_read_out_pkg_hdl::*; + + + + // Parameters defined as HVL parameters + + `include "src/fuse_ctrl_secreg_axi_read_out_typedefs.svh" + `include "src/fuse_ctrl_secreg_axi_read_out_transaction.svh" + + `include "src/fuse_ctrl_secreg_axi_read_out_configuration.svh" + `include "src/fuse_ctrl_secreg_axi_read_out_driver.svh" + `include "src/fuse_ctrl_secreg_axi_read_out_monitor.svh" + + `include "src/fuse_ctrl_secreg_axi_read_out_transaction_coverage.svh" + `include "src/fuse_ctrl_secreg_axi_read_out_sequence_base.svh" + `include "src/fuse_ctrl_secreg_axi_read_out_random_sequence.svh" + + `include "src/fuse_ctrl_secreg_axi_read_out_responder_sequence.svh" + `include "src/fuse_ctrl_secreg_axi_read_out2reg_adapter.svh" + + `include "src/fuse_ctrl_secreg_axi_read_out_agent.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new interface sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the interface package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_pkg.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_pkg.vinfo new file mode 100644 index 0000000..fcfbb84 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_pkg.vinfo @@ -0,0 +1,4 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use fuse_ctrl_secreg_axi_read_out_pkg_hdl.vinfo ++incdir+@vinfodir +fuse_ctrl_secreg_axi_read_out_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_pkg_hdl.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_pkg_hdl.sv new file mode 100644 index 0000000..86bf6a5 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_pkg_hdl.sv @@ -0,0 +1,52 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that needs to be compiled and synthesized +// for running on Veloce. +// +// CONTAINS: +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_secreg_axi_read_out_pkg_hdl; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HDL parameters + + `include "src/fuse_ctrl_secreg_axi_read_out_typedefs_hdl.svh" + `include "src/fuse_ctrl_secreg_axi_read_out_macros.svh" + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_pkg_hdl.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_pkg_hdl.vinfo new file mode 100644 index 0000000..217e9f2 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_pkg_hdl.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +fuse_ctrl_secreg_axi_read_out_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_pkg_sve.F b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_pkg_sve.F new file mode 100644 index 0000000..7feb9ad --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_pkg_sve.F @@ -0,0 +1,10 @@ +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + ++incdir+. +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_filelist_hdl.f +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_filelist_hvl.f diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out2reg_adapter.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out2reg_adapter.svh new file mode 100644 index 0000000..f00f29b --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out2reg_adapter.svh @@ -0,0 +1,137 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the UVM register adapter for the fuse_ctrl_secreg_axi_read_out interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_secreg_axi_read_out2reg_adapter #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvm_reg_adapter; + + `uvm_object_param_utils( fuse_ctrl_secreg_axi_read_out2reg_adapter #( + AW, + DW, + IW, + UW + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //-------------------------------------------------------------------- + // new + //-------------------------------------------------------------------- + function new (string name = "fuse_ctrl_secreg_axi_read_out2reg_adapter" ); + super.new(name); + // pragma uvmf custom new begin + // UVMF_CHANGE_ME : Configure the adapter regarding byte enables and provides response. + + // Does the protocol the Agent is modeling support byte enables? + // 0 = NO + // 1 = YES + supports_byte_enable = 0; + + // Does the Agent's Driver provide separate response sequence items? + // i.e. Does the driver call seq_item_port.put() + // and do the sequences call get_response()? + // 0 = NO + // 1 = YES + provides_responses = 0; + // pragma uvmf custom new end + + endfunction: new + + //-------------------------------------------------------------------- + // reg2bus + //-------------------------------------------------------------------- + virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw); + + fuse_ctrl_secreg_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) trans_h = fuse_ctrl_secreg_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )::type_id::create("trans_h"); + + // pragma uvmf custom reg2bus begin + // UVMF_CHANGE_ME : Fill in the reg2bus adapter mapping registe fields to protocol fields. + + //Adapt the following for your sequence item type + // trans_h.op = (rw.kind == UVM_READ) ? WB_READ : WB_WRITE; + //Copy over address + // trans_h.addr = rw.addr; + //Copy over write data + // trans_h.data = rw.data; + + // pragma uvmf custom reg2bus end + + // Return the adapted transaction + return trans_h; + + endfunction: reg2bus + + //-------------------------------------------------------------------- + // bus2reg + //-------------------------------------------------------------------- + virtual function void bus2reg(uvm_sequence_item bus_item, + ref uvm_reg_bus_op rw); + fuse_ctrl_secreg_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) trans_h; + if (!$cast(trans_h, bus_item)) begin + `uvm_fatal("ADAPT","Provided bus_item is not of the correct type") + return; + end + // pragma uvmf custom bus2reg begin + // UVMF_CHANGE_ME : Fill in the bus2reg adapter mapping protocol fields to register fields. + //Adapt the following for your sequence item type + //Copy over instruction type + // rw.kind = (trans_h.op == WB_WRITE) ? UVM_WRITE : UVM_READ; + //Copy over address + // rw.addr = trans_h.addr; + //Copy over read data + // rw.data = trans_h.data; + //Check for errors on the bus and return UVM_NOT_OK if there is an error + // rw.status = UVM_IS_OK; + // pragma uvmf custom bus2reg end + + endfunction: bus2reg + +endclass : fuse_ctrl_secreg_axi_read_out2reg_adapter + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_agent.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_agent.svh new file mode 100644 index 0000000..893db4b --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_agent.svh @@ -0,0 +1,102 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: Protocol specific agent class definition +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_secreg_axi_read_out_agent #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvmf_parameterized_agent #( + .CONFIG_T(fuse_ctrl_secreg_axi_read_out_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .DRIVER_T(fuse_ctrl_secreg_axi_read_out_driver #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .MONITOR_T(fuse_ctrl_secreg_axi_read_out_monitor #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .COVERAGE_T(fuse_ctrl_secreg_axi_read_out_transaction_coverage #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .TRANS_T(fuse_ctrl_secreg_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )) + ); + + `uvm_component_param_utils( fuse_ctrl_secreg_axi_read_out_agent #( + AW, + DW, + IW, + UW + )) + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** + // FUNCTION: build_phase + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + if (configuration.active_passive == ACTIVE) begin + // Place sequencer handle into configuration object + // so that it may be retrieved from configuration + // rather than using uvm_config_db + configuration.sequencer = this.sequencer; + end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_configuration.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_configuration.svh new file mode 100644 index 0000000..5b7faa2 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_configuration.svh @@ -0,0 +1,233 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class contains all variables and functions used +// to configure the fuse_ctrl_secreg_axi_read_out agent and its bfm's. It gets the +// bfm's from the uvm_config_db for use by the agent. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_secreg_axi_read_out_configuration #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvmf_parameterized_agent_configuration_base #( + .DRIVER_BFM_BIND_T(virtual fuse_ctrl_secreg_axi_read_out_driver_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .MONITOR_BFM_BIND_T( virtual fuse_ctrl_secreg_axi_read_out_monitor_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ))); + + `uvm_object_param_utils( fuse_ctrl_secreg_axi_read_out_configuration #( + AW, + DW, + IW, + UW + )) + + + // Sequencer handle populated by agent + uvm_sequencer #(fuse_ctrl_secreg_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) ) sequencer; + + //Constraints for the configuration variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + covergroup fuse_ctrl_secreg_axi_read_out_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + // pragma uvmf custom covergroup end + endgroup + + //******************************************************************* + //******************************************************************* + // Structure used to pass configuration variables to monitor and driver BFM's. + // Use to_struct function to pack variables into structure. + // Use from_struct function to unpack variables from structure. + // This structure is defined in fuse_ctrl_secreg_axi_read_out_macros.svh + `fuse_ctrl_secreg_axi_read_out_CONFIGURATION_STRUCT + fuse_ctrl_secreg_axi_read_out_configuration_s fuse_ctrl_secreg_axi_read_out_configuration_struct; + //******************************************************************* + // FUNCTION: to_struct() + // This function packs variables into a fuse_ctrl_secreg_axi_read_out_configuration_s + // structure. The function returns the handle to the fuse_ctrl_secreg_axi_read_out_configuration_struct. + // This function is defined in fuse_ctrl_secreg_axi_read_out_macros.svh + `fuse_ctrl_secreg_axi_read_out_CONFIGURATION_TO_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_struct() + // This function unpacks the struct provided as an argument into + // variables of this class. + // This function is defined in fuse_ctrl_secreg_axi_read_out_macros.svh + `fuse_ctrl_secreg_axi_read_out_CONFIGURATION_FROM_STRUCT_FUNCTION + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + // Construct the covergroup for this configuration class + fuse_ctrl_secreg_axi_read_out_configuration_cg = new; + endfunction + + // **************************************************************************** + // FUNCTION: post_randomize() + // This function is automatically called after the randomize() function + // is executed. + // + function void post_randomize(); + super.post_randomize(); + fuse_ctrl_secreg_axi_read_out_configuration_cg.sample(); + endfunction + + // **************************************************************************** + // FUNCTION: initialize + // This function causes the configuration to retrieve + // its virtual interface handle from the uvm_config_db. + // This function also makes itself available to its + // agent through the uvm_config_db. + // + // ARGUMENTS: + // uvmf_active_passive_t activity: + // This argument identifies the simulation level + // as either BLOCK, CHIP, SIMULATION, etc. + // + // AGENT_PATH: + // This argument identifies the path to this + // configurations agent. This configuration + // makes itself available to the agent specified + // by agent_path by placing itself into the + // uvm_config_db. + // + // INTERFACE_NAME: + // This argument identifies the string name of + // this configurations BFM's. This string + // name is used to retrieve the driver and + // monitor BFM from the uvm_config_db. + // + virtual function void initialize(uvmf_active_passive_t activity, + string agent_path, + string interface_name); + + super.initialize( activity, agent_path, interface_name); + // The covergroup is given the same name as the interface + fuse_ctrl_secreg_axi_read_out_configuration_cg.set_inst_name(interface_name); + + // This configuration places itself into the uvm_config_db for the agent, identified by the agent_path variable, to retrieve. + uvm_config_db #( fuse_ctrl_secreg_axi_read_out_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + )::set( null ,agent_path,UVMF_AGENT_CONFIG, this ); + + // This configuration also places itself in the config db using the same identifier used by the interface. This allows users to access + // configuration variables and the interface through the bfm api class rather than directly accessing the BFM. This is useful for + // accessingthe BFM when using Veloce + uvm_config_db #( fuse_ctrl_secreg_axi_read_out_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + )::set( null ,UVMF_CONFIGURATIONS, interface_name, this ); + + fuse_ctrl_secreg_axi_read_out_configuration_cg.set_inst_name($sformatf("fuse_ctrl_secreg_axi_read_out_configuration_cg_%s",get_full_name())); + +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. + `uvm_info("CFG", + $psprintf("The agent at '%s' is using interface named %s has the following parameters: AW=%x DW=%x IW=%x UW=%x ", agent_path, interface_name, AW ,DW ,IW ,UW ), + UVM_DEBUG) + + // pragma uvmf custom initialize begin + // This controls whether or not the agent returns a transaction handle in the driver when calling + // item_done() back into the sequencer or not. If set to 1, a transaction is sent back which means + // the sequence on the other end must use the get_response() part of the driver/sequence API. If + // this doesn't occur, there will eventually be response_queue overflow errors during the test. + return_transaction_response = 1'b0; + + // pragma uvmf custom initialize end + + endfunction + + // **************************************************************************** + // TASK: wait_for_reset + // *[Required]* Blocks until reset is released. The wait_for_reset operation is performed + // by a task in the monitor bfm. + virtual task wait_for_reset(); + monitor_bfm.wait_for_reset(); + endtask + + // **************************************************************************** + // TASK: wait_for_num_clocks + // *[Required]* Blocks until specified number of clocks have elapsed. The wait_for_num_clocks + // operation is performed by a task in the monitor bfm. + virtual task wait_for_num_clocks(int clocks); + monitor_bfm.wait_for_num_clocks(clocks); + endtask + + // **************************************************************************** + // FUNCTION : convert2string() + // This function is used to convert variables in this class into a string for log messaging. + // + virtual function string convert2string (); + // pragma uvmf custom convert2string begin + return $sformatf(""); + // pragma uvmf custom convert2string end + endfunction + + // **************************************************************************** + // FUNCTION: get_sequencer + function uvm_sequencer #(fuse_ctrl_secreg_axi_read_out_transaction#( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )) get_sequencer(); + return sequencer; + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_driver.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_driver.svh new file mode 100644 index 0000000..1bed248 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_driver.svh @@ -0,0 +1,135 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class passes transactions between the sequencer +// and the BFM driver interface. It accesses the driver BFM +// through the bfm handle. This driver +// passes transactions to the driver BFM through the access +// task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_secreg_axi_read_out_driver #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvmf_driver_base #( + .CONFIG_T(fuse_ctrl_secreg_axi_read_out_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) ), + .BFM_BIND_T(virtual fuse_ctrl_secreg_axi_read_out_driver_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) ), + .REQ(fuse_ctrl_secreg_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) ), + .RSP(fuse_ctrl_secreg_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) )); + + `uvm_component_param_utils( fuse_ctrl_secreg_axi_read_out_driver #( + AW, + DW, + IW, + UW + )) +//******************************************************************* +// Macros that define structs located in fuse_ctrl_secreg_axi_read_out_macros.svh +//******************************************************************* +// Initiator macro used by fuse_ctrl_secreg_axi_read_out_driver and fuse_ctrl_secreg_axi_read_out_driver_bfm +// to communicate initiator driven data to fuse_ctrl_secreg_axi_read_out_driver_bfm. +`fuse_ctrl_secreg_axi_read_out_INITIATOR_STRUCT + fuse_ctrl_secreg_axi_read_out_initiator_s fuse_ctrl_secreg_axi_read_out_initiator_struct; +//******************************************************************* +// Responder macro used by fuse_ctrl_secreg_axi_read_out_driver and fuse_ctrl_secreg_axi_read_out_driver_bfm +// to communicate Responder driven data to fuse_ctrl_secreg_axi_read_out_driver_bfm. +`fuse_ctrl_secreg_axi_read_out_RESPONDER_STRUCT + fuse_ctrl_secreg_axi_read_out_responder_s fuse_ctrl_secreg_axi_read_out_responder_struct; + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent=null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the driver BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// driver BFM. This allows the driver BFM to call tasks and function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// **************************************************************************** +// This task is called by the run_phase in uvmf_driver_base. + virtual task access( inout REQ txn ); +// pragma uvmf custom access begin + if (configuration.initiator_responder==RESPONDER) begin + // Complete current transfer and wait for next transfer + bfm.respond_and_wait_for_next_transfer( + fuse_ctrl_secreg_axi_read_out_initiator_struct, + txn.to_responder_struct() + ); + // Unpack information about initiated transfer received by this responder + txn.from_initiator_struct(fuse_ctrl_secreg_axi_read_out_initiator_struct); + end else begin + // Initiate a transfer and get response + bfm.initiate_and_get_response( + txn.to_initiator_struct(), + fuse_ctrl_secreg_axi_read_out_responder_struct + ); + // Unpack transfer response information received by this initiator + txn.from_responder_struct(fuse_ctrl_secreg_axi_read_out_responder_struct); + end +// pragma uvmf custom access end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_driver_bfm.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_driver_bfm.sv new file mode 100644 index 0000000..c2c4732 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_driver_bfm.sv @@ -0,0 +1,350 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This interface performs the fuse_ctrl_secreg_axi_read_out signal driving. It is +// accessed by the uvm fuse_ctrl_secreg_axi_read_out driver through a virtual interface +// handle in the fuse_ctrl_secreg_axi_read_out configuration. It drives the singals passed +// in through the port connection named bus of type fuse_ctrl_secreg_axi_read_out_if. +// +// Input signals from the fuse_ctrl_secreg_axi_read_out_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// This bfm drives signals with a _o suffix. These signals +// are driven onto signals within fuse_ctrl_secreg_axi_read_out_if based on INITIATOR/RESPONDER and/or +// ARBITRATION/GRANT status. +// +// The output signal connections are as follows: +// signal_o -> bus.signal +// +// +// Interface functions and tasks used by UVM components: +// +// configure: +// This function gets configuration attributes from the +// UVM driver to set any required BFM configuration +// variables such as 'initiator_responder'. +// +// initiate_and_get_response: +// This task is used to perform signaling activity for initiating +// a protocol transfer. The task initiates the transfer, using +// input data from the initiator struct. Then the task captures +// response data, placing the data into the response struct. +// The response struct is returned to the driver class. +// +// respond_and_wait_for_next_transfer: +// This task is used to complete a current transfer as a responder +// and then wait for the initiator to start the next transfer. +// The task uses data in the responder struct to drive protocol +// signals to complete the transfer. The task then waits for +// the next transfer. Once the next transfer begins, data from +// the initiator is placed into the initiator struct and sent +// to the responder sequence for processing to determine +// what data to respond with. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_secreg_axi_read_out_pkg_hdl::*; +`include "src/fuse_ctrl_secreg_axi_read_out_macros.svh" + +interface fuse_ctrl_secreg_axi_read_out_driver_bfm #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + (fuse_ctrl_secreg_axi_read_out_if bus); + // The following pragma and additional ones in-lined further below are for running this BFM on Veloce + // pragma attribute fuse_ctrl_secreg_axi_read_out_driver_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: AW=%x DW=%x IW=%x UW=%x ", AW,DW,IW,UW), + UVM_DEBUG) +end +`endif + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + tri clk_i_i; + tri rst_ni_i; + + // Signal list (all signals are capable of being inputs and outputs for the sake + // of supporting both INITIATOR and RESPONDER mode operation. Expectation is that + // directionality in the config file was from the point-of-view of the INITIATOR + + // INITIATOR mode input signals + tri arready_i; + reg arready_o = 'bz; + tri [DW-1:0] rdata_i; + reg [DW-1:0] rdata_o = 'bz; + tri rresp_i; + reg rresp_o = 'bz; + tri rid_i; + reg rid_o = 'bz; + tri rlast_i; + reg rlast_o = 'bz; + tri rvalid_i; + reg rvalid_o = 'bz; + + // INITIATOR mode output signals + + // Bi-directional signals + + + assign clk_i_i = bus.clk_i; + assign rst_ni_i = bus.rst_ni; + + // These are signals marked as 'input' by the config file, but the signals will be + // driven by this BFM if put into RESPONDER mode (flipping all signal directions around) + assign arready_i = bus.arready; + assign bus.arready = (initiator_responder == RESPONDER) ? arready_o : 'bz; + assign rdata_i = bus.rdata; + assign bus.rdata = (initiator_responder == RESPONDER) ? rdata_o : 'bz; + assign rresp_i = bus.rresp; + assign bus.rresp = (initiator_responder == RESPONDER) ? rresp_o : 'bz; + assign rid_i = bus.rid; + assign bus.rid = (initiator_responder == RESPONDER) ? rid_o : 'bz; + assign rlast_i = bus.rlast; + assign bus.rlast = (initiator_responder == RESPONDER) ? rlast_o : 'bz; + assign rvalid_i = bus.rvalid; + assign bus.rvalid = (initiator_responder == RESPONDER) ? rvalid_o : 'bz; + + + // These are signals marked as 'output' by the config file, but the outputs will + // not be driven by this BFM unless placed in INITIATOR mode. + + // Proxy handle to UVM driver + fuse_ctrl_secreg_axi_read_out_pkg::fuse_ctrl_secreg_axi_read_out_driver #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) proxy; + // pragma tbx oneway proxy.my_function_name_in_uvm_driver + + // **************************************************************************** + // **************************************************************************** + // Macros that define structs located in fuse_ctrl_secreg_axi_read_out_macros.svh + // **************************************************************************** + // Struct for passing configuration data from fuse_ctrl_secreg_axi_read_out_driver to this BFM + // **************************************************************************** + `fuse_ctrl_secreg_axi_read_out_CONFIGURATION_STRUCT + // **************************************************************************** + // Structs for INITIATOR and RESPONDER data flow + //******************************************************************* + // Initiator macro used by fuse_ctrl_secreg_axi_read_out_driver and fuse_ctrl_secreg_axi_read_out_driver_bfm + // to communicate initiator driven data to fuse_ctrl_secreg_axi_read_out_driver_bfm. + `fuse_ctrl_secreg_axi_read_out_INITIATOR_STRUCT + fuse_ctrl_secreg_axi_read_out_initiator_s initiator_struct; + // Responder macro used by fuse_ctrl_secreg_axi_read_out_driver and fuse_ctrl_secreg_axi_read_out_driver_bfm + // to communicate Responder driven data to fuse_ctrl_secreg_axi_read_out_driver_bfm. + `fuse_ctrl_secreg_axi_read_out_RESPONDER_STRUCT + fuse_ctrl_secreg_axi_read_out_responder_s responder_struct; + + // **************************************************************************** +// pragma uvmf custom reset_condition_and_response begin + // Always block used to return signals to reset value upon assertion of reset + always @( negedge rst_ni_i ) + begin + // RESPONDER mode output signals + arready_o <= 'bz; + rdata_o <= 'bz; + rresp_o <= 'bz; + rid_o <= 'bz; + rlast_o <= 'bz; + rvalid_o <= 'bz; + // INITIATOR mode output signals + // Bi-directional signals + + end +// pragma uvmf custom reset_condition_and_response end + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the driver BFM. It is called by the driver within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the driver BFM needs to be aware of the new configuration + // variables. + // + + function void configure(fuse_ctrl_secreg_axi_read_out_configuration_s fuse_ctrl_secreg_axi_read_out_configuration_arg); // pragma tbx xtf + initiator_responder = fuse_ctrl_secreg_axi_read_out_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + +// pragma uvmf custom initiate_and_get_response begin +// **************************************************************************** +// UVMF_CHANGE_ME +// This task is used by an initator. The task first initiates a transfer then +// waits for the responder to complete the transfer. + task initiate_and_get_response( + // This argument passes transaction variables used by an initiator + // to perform the initial part of a protocol transfer. The values + // come from a sequence item created in a sequence. + input fuse_ctrl_secreg_axi_read_out_initiator_s fuse_ctrl_secreg_axi_read_out_initiator_struct, + // This argument is used to send data received from the responder + // back to the sequence item. The sequence item is returned to the sequence. + output fuse_ctrl_secreg_axi_read_out_responder_s fuse_ctrl_secreg_axi_read_out_responder_struct + );// pragma tbx xtf + // + // Members within the fuse_ctrl_secreg_axi_read_out_initiator_struct: + // logic secreg_arready ; + // logic [DW-1:0] secreg_rdata ; + // axi_pkg::axi_burst_e secreg_rresp ; + // logic [IW-1:0] secreg_rid ; + // logic secreg_rlast ; + // logic secreg_rvalid ; + // Members within the fuse_ctrl_secreg_axi_read_out_responder_struct: + // logic secreg_arready ; + // logic [DW-1:0] secreg_rdata ; + // axi_pkg::axi_burst_e secreg_rresp ; + // logic [IW-1:0] secreg_rid ; + // logic secreg_rlast ; + // logic secreg_rvalid ; + initiator_struct = fuse_ctrl_secreg_axi_read_out_initiator_struct; + // + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clk_i_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available initiator input and inout signals listed. + // Initiator input signals + // fuse_ctrl_secreg_axi_read_out_responder_struct.xyz = arready_i; // + // fuse_ctrl_secreg_axi_read_out_responder_struct.xyz = rdata_i; // [DW-1:0] + // fuse_ctrl_secreg_axi_read_out_responder_struct.xyz = rresp_i; // + // fuse_ctrl_secreg_axi_read_out_responder_struct.xyz = rid_i; // + // fuse_ctrl_secreg_axi_read_out_responder_struct.xyz = rlast_i; // + // fuse_ctrl_secreg_axi_read_out_responder_struct.xyz = rvalid_i; // + // Initiator inout signals + // How to assign a signal from an initiator struct member named xyz. + // All available initiator output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Initiator output signals + // Initiator inout signals + // Initiate a transfer using the data received. + @(posedge clk_i_i); + @(posedge clk_i_i); + // Wait for the responder to complete the transfer then place the responder data into + // fuse_ctrl_secreg_axi_read_out_responder_struct. + @(posedge clk_i_i); + @(posedge clk_i_i); + responder_struct = fuse_ctrl_secreg_axi_read_out_responder_struct; + endtask +// pragma uvmf custom initiate_and_get_response end + +// pragma uvmf custom respond_and_wait_for_next_transfer begin +// **************************************************************************** +// The first_transfer variable is used to prevent completing a transfer in the +// first call to this task. For the first call to this task, there is not +// current transfer to complete. +bit first_transfer=1; + +// UVMF_CHANGE_ME +// This task is used by a responder. The task first completes the current +// transfer in progress then waits for the initiator to start the next transfer. + task respond_and_wait_for_next_transfer( + // This argument is used to send data received from the initiator + // back to the sequence item. The sequence determines how to respond. + output fuse_ctrl_secreg_axi_read_out_initiator_s fuse_ctrl_secreg_axi_read_out_initiator_struct, + // This argument passes transaction variables used by a responder + // to complete a protocol transfer. The values come from a sequence item. + input fuse_ctrl_secreg_axi_read_out_responder_s fuse_ctrl_secreg_axi_read_out_responder_struct + );// pragma tbx xtf + // Variables within the fuse_ctrl_secreg_axi_read_out_initiator_struct: + // logic secreg_arready ; + // logic [DW-1:0] secreg_rdata ; + // axi_pkg::axi_burst_e secreg_rresp ; + // logic [IW-1:0] secreg_rid ; + // logic secreg_rlast ; + // logic secreg_rvalid ; + // Variables within the fuse_ctrl_secreg_axi_read_out_responder_struct: + // logic secreg_arready ; + // logic [DW-1:0] secreg_rdata ; + // axi_pkg::axi_burst_e secreg_rresp ; + // logic [IW-1:0] secreg_rid ; + // logic secreg_rlast ; + // logic secreg_rvalid ; + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clk_i_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available responder input and inout signals listed. + // Responder input signals + // Responder inout signals + // How to assign a signal, named xyz, from an initiator struct member. + // All available responder output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Responder output signals + // arready_o <= fuse_ctrl_secreg_axi_read_out_initiator_struct.xyz; // + // rdata_o <= fuse_ctrl_secreg_axi_read_out_initiator_struct.xyz; // [DW-1:0] + // rresp_o <= fuse_ctrl_secreg_axi_read_out_initiator_struct.xyz; // + // rid_o <= fuse_ctrl_secreg_axi_read_out_initiator_struct.xyz; // + // rlast_o <= fuse_ctrl_secreg_axi_read_out_initiator_struct.xyz; // + // rvalid_o <= fuse_ctrl_secreg_axi_read_out_initiator_struct.xyz; // + // Responder inout signals + + @(posedge clk_i_i); + if (!first_transfer) begin + // Perform transfer response here. + // Reply using data recieved in the fuse_ctrl_secreg_axi_read_out_responder_struct. + @(posedge clk_i_i); + // Reply using data recieved in the transaction handle. + @(posedge clk_i_i); + end + // Wait for next transfer then gather info from intiator about the transfer. + // Place the data into the fuse_ctrl_secreg_axi_read_out_initiator_struct. + @(posedge clk_i_i); + @(posedge clk_i_i); + first_transfer = 0; + endtask +// pragma uvmf custom respond_and_wait_for_next_transfer end + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_if.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_if.sv new file mode 100644 index 0000000..b181c55 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_if.sv @@ -0,0 +1,108 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface contains the fuse_ctrl_secreg_axi_read_out interface signals. +// It is instantiated once per fuse_ctrl_secreg_axi_read_out bus. Bus Functional Models, +// BFM's named fuse_ctrl_secreg_axi_read_out_driver_bfm, are used to drive signals on the bus. +// BFM's named fuse_ctrl_secreg_axi_read_out_monitor_bfm are used to monitor signals on the +// bus. This interface signal bundle is passed in the port list of +// the BFM in order to give the BFM access to the signals in this +// interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// This template can be used to connect a DUT to these signals +// +// .dut_signal_port(fuse_ctrl_secreg_axi_read_out_bus.arready), // Agent input +// .dut_signal_port(fuse_ctrl_secreg_axi_read_out_bus.rdata), // Agent input +// .dut_signal_port(fuse_ctrl_secreg_axi_read_out_bus.rresp), // Agent input +// .dut_signal_port(fuse_ctrl_secreg_axi_read_out_bus.rid), // Agent input +// .dut_signal_port(fuse_ctrl_secreg_axi_read_out_bus.rlast), // Agent input +// .dut_signal_port(fuse_ctrl_secreg_axi_read_out_bus.rvalid), // Agent input + +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_secreg_axi_read_out_pkg_hdl::*; + +interface fuse_ctrl_secreg_axi_read_out_if #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + + ( + input tri clk_i, + input tri rst_ni, + inout tri arready, + inout tri [DW-1:0] rdata, + inout tri rresp, + inout tri rid, + inout tri rlast, + inout tri rvalid + ); + +modport monitor_port + ( + input clk_i, + input rst_ni, + input arready, + input rdata, + input rresp, + input rid, + input rlast, + input rvalid + ); + +modport initiator_port + ( + input clk_i, + input rst_ni, + input arready, + input rdata, + input rresp, + input rid, + input rlast, + input rvalid + ); + +modport responder_port + ( + input clk_i, + input rst_ni, + output arready, + output rdata, + output rresp, + output rid, + output rlast, + output rvalid + ); + + +// pragma uvmf custom interface_item_additional begin +// pragma uvmf custom interface_item_additional end + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_infact_coverage_strategy.csv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_infact_coverage_strategy.csv new file mode 100644 index 0000000..1c218e1 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_infact_coverage_strategy.csv @@ -0,0 +1,6 @@ +Global +auto_bin_max, 64 + +Name,Type,Include +rand_fields,coverpoint,=rand *.** + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_macros.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_macros.svh new file mode 100644 index 0000000..882e661 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_macros.svh @@ -0,0 +1,180 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains macros used with the fuse_ctrl_secreg_axi_read_out package. +// These macros include packed struct definitions. These structs are +// used to pass data between classes, hvl, and BFM's, hdl. Use of +// structs are more efficient and simpler to modify. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_struct +// and from_struct methods defined in the macros below that are used in +// the fuse_ctrl_secreg_axi_read_out_configuration class. +// + `define fuse_ctrl_secreg_axi_read_out_CONFIGURATION_STRUCT \ +typedef struct packed { \ + uvmf_active_passive_t active_passive; \ + uvmf_initiator_responder_t initiator_responder; \ + } fuse_ctrl_secreg_axi_read_out_configuration_s; + + `define fuse_ctrl_secreg_axi_read_out_CONFIGURATION_TO_STRUCT_FUNCTION \ + virtual function fuse_ctrl_secreg_axi_read_out_configuration_s to_struct();\ + fuse_ctrl_secreg_axi_read_out_configuration_struct = \ + {\ + this.active_passive,\ + this.initiator_responder\ + };\ + return ( fuse_ctrl_secreg_axi_read_out_configuration_struct );\ + endfunction + + `define fuse_ctrl_secreg_axi_read_out_CONFIGURATION_FROM_STRUCT_FUNCTION \ + virtual function void from_struct(fuse_ctrl_secreg_axi_read_out_configuration_s fuse_ctrl_secreg_axi_read_out_configuration_struct);\ + {\ + this.active_passive,\ + this.initiator_responder \ + } = fuse_ctrl_secreg_axi_read_out_configuration_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_monitor_struct +// and from_monitor_struct methods of the fuse_ctrl_secreg_axi_read_out_transaction class. +// + `define fuse_ctrl_secreg_axi_read_out_MONITOR_STRUCT typedef struct packed { \ + logic secreg_arready ; \ + logic [DW-1:0] secreg_rdata ; \ + axi_pkg::axi_burst_e secreg_rresp ; \ + logic [IW-1:0] secreg_rid ; \ + logic secreg_rlast ; \ + logic secreg_rvalid ; \ + } fuse_ctrl_secreg_axi_read_out_monitor_s; + + `define fuse_ctrl_secreg_axi_read_out_TO_MONITOR_STRUCT_FUNCTION \ + virtual function fuse_ctrl_secreg_axi_read_out_monitor_s to_monitor_struct();\ + fuse_ctrl_secreg_axi_read_out_monitor_struct = \ + { \ + this.secreg_arready , \ + this.secreg_rdata , \ + this.secreg_rresp , \ + this.secreg_rid , \ + this.secreg_rlast , \ + this.secreg_rvalid \ + };\ + return ( fuse_ctrl_secreg_axi_read_out_monitor_struct);\ + endfunction\ + + `define fuse_ctrl_secreg_axi_read_out_FROM_MONITOR_STRUCT_FUNCTION \ + virtual function void from_monitor_struct(fuse_ctrl_secreg_axi_read_out_monitor_s fuse_ctrl_secreg_axi_read_out_monitor_struct);\ + {\ + this.secreg_arready , \ + this.secreg_rdata , \ + this.secreg_rresp , \ + this.secreg_rid , \ + this.secreg_rlast , \ + this.secreg_rvalid \ + } = fuse_ctrl_secreg_axi_read_out_monitor_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_initiator_struct +// and from_initiator_struct methods of the fuse_ctrl_secreg_axi_read_out_transaction class. +// Also update the comments in the driver BFM. +// + `define fuse_ctrl_secreg_axi_read_out_INITIATOR_STRUCT typedef struct packed { \ + logic secreg_arready ; \ + logic [DW-1:0] secreg_rdata ; \ + axi_pkg::axi_burst_e secreg_rresp ; \ + logic [IW-1:0] secreg_rid ; \ + logic secreg_rlast ; \ + logic secreg_rvalid ; \ + } fuse_ctrl_secreg_axi_read_out_initiator_s; + + `define fuse_ctrl_secreg_axi_read_out_TO_INITIATOR_STRUCT_FUNCTION \ + virtual function fuse_ctrl_secreg_axi_read_out_initiator_s to_initiator_struct();\ + fuse_ctrl_secreg_axi_read_out_initiator_struct = \ + {\ + this.secreg_arready , \ + this.secreg_rdata , \ + this.secreg_rresp , \ + this.secreg_rid , \ + this.secreg_rlast , \ + this.secreg_rvalid \ + };\ + return ( fuse_ctrl_secreg_axi_read_out_initiator_struct);\ + endfunction + + `define fuse_ctrl_secreg_axi_read_out_FROM_INITIATOR_STRUCT_FUNCTION \ + virtual function void from_initiator_struct(fuse_ctrl_secreg_axi_read_out_initiator_s fuse_ctrl_secreg_axi_read_out_initiator_struct);\ + {\ + this.secreg_arready , \ + this.secreg_rdata , \ + this.secreg_rresp , \ + this.secreg_rid , \ + this.secreg_rlast , \ + this.secreg_rvalid \ + } = fuse_ctrl_secreg_axi_read_out_initiator_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_responder_struct +// and from_responder_struct methods of the fuse_ctrl_secreg_axi_read_out_transaction class. +// Also update the comments in the driver BFM. +// + `define fuse_ctrl_secreg_axi_read_out_RESPONDER_STRUCT typedef struct packed { \ + logic secreg_arready ; \ + logic [DW-1:0] secreg_rdata ; \ + axi_pkg::axi_burst_e secreg_rresp ; \ + logic [IW-1:0] secreg_rid ; \ + logic secreg_rlast ; \ + logic secreg_rvalid ; \ + } fuse_ctrl_secreg_axi_read_out_responder_s; + + `define fuse_ctrl_secreg_axi_read_out_TO_RESPONDER_STRUCT_FUNCTION \ + virtual function fuse_ctrl_secreg_axi_read_out_responder_s to_responder_struct();\ + fuse_ctrl_secreg_axi_read_out_responder_struct = \ + {\ + this.secreg_arready , \ + this.secreg_rdata , \ + this.secreg_rresp , \ + this.secreg_rid , \ + this.secreg_rlast , \ + this.secreg_rvalid \ + };\ + return ( fuse_ctrl_secreg_axi_read_out_responder_struct);\ + endfunction + + `define fuse_ctrl_secreg_axi_read_out_FROM_RESPONDER_STRUCT_FUNCTION \ + virtual function void from_responder_struct(fuse_ctrl_secreg_axi_read_out_responder_s fuse_ctrl_secreg_axi_read_out_responder_struct);\ + {\ + this.secreg_arready , \ + this.secreg_rdata , \ + this.secreg_rresp , \ + this.secreg_rid , \ + this.secreg_rlast , \ + this.secreg_rvalid \ + } = fuse_ctrl_secreg_axi_read_out_responder_struct;\ + endfunction +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_monitor.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_monitor.svh new file mode 100644 index 0000000..e743dab --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_monitor.svh @@ -0,0 +1,126 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class receives fuse_ctrl_secreg_axi_read_out transactions observed by the +// fuse_ctrl_secreg_axi_read_out monitor BFM and broadcasts them through the analysis port +// on the agent. It accesses the monitor BFM through the monitor +// task. This UVM component captures transactions +// for viewing in the waveform viewer if the +// enable_transaction_viewing flag is set in the configuration. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_secreg_axi_read_out_monitor #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvmf_monitor_base #( + .CONFIG_T(fuse_ctrl_secreg_axi_read_out_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .BFM_BIND_T(virtual fuse_ctrl_secreg_axi_read_out_monitor_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .TRANS_T(fuse_ctrl_secreg_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ))); + + `uvm_component_param_utils( fuse_ctrl_secreg_axi_read_out_monitor #( + AW, + DW, + IW, + UW + )) + +// Structure used to pass data from monitor BFM to monitor class in agent. +// Use to_monitor_struct function to pack transaction variables into structure. +// Use from_monitor_struct function to unpack transaction variables from structure. +`fuse_ctrl_secreg_axi_read_out_MONITOR_STRUCT + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the monitor BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// monitor BFM. This allows the monitor BFM to call the notify_transaction +// function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// *************************************************************************** + virtual task run_phase(uvm_phase phase); + // Start monitor BFM thread and don't call super.run() in order to + // override the default monitor proxy 'pull' behavior with the more + // emulation-friendly BFM 'push' approach using the notify_transaction + // function below + bfm.start_monitoring(); + endtask + +// ************************************************************************** + +// This function is called by the monitor BFM. It receives data observed by the +// monitor BFM. Data is passed using the fuse_ctrl_secreg_axi_read_out_monitor_struct. + virtual function void notify_transaction(input fuse_ctrl_secreg_axi_read_out_monitor_s fuse_ctrl_secreg_axi_read_out_monitor_struct); + + + trans = new("trans"); + trans.from_monitor_struct(fuse_ctrl_secreg_axi_read_out_monitor_struct); + trans.start_time = time_stamp; + trans.end_time = $time; + time_stamp = trans.end_time; + + analyze(trans); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_monitor_bfm.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_monitor_bfm.sv new file mode 100644 index 0000000..b09537e --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_monitor_bfm.sv @@ -0,0 +1,218 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface performs the fuse_ctrl_secreg_axi_read_out signal monitoring. +// It is accessed by the uvm fuse_ctrl_secreg_axi_read_out monitor through a virtual +// interface handle in the fuse_ctrl_secreg_axi_read_out configuration. It monitors the +// signals passed in through the port connection named bus of +// type fuse_ctrl_secreg_axi_read_out_if. +// +// Input signals from the fuse_ctrl_secreg_axi_read_out_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// Interface functions and tasks used by UVM components: +// monitor(inout TRANS_T txn); +// This task receives the transaction, txn, from the +// UVM monitor and then populates variables in txn +// from values observed on bus activity. This task +// blocks until an operation on the fuse_ctrl_secreg_axi_read_out bus is complete. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_secreg_axi_read_out_pkg_hdl::*; +`include "src/fuse_ctrl_secreg_axi_read_out_macros.svh" + + +interface fuse_ctrl_secreg_axi_read_out_monitor_bfm #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + ( fuse_ctrl_secreg_axi_read_out_if bus ); + // The pragma below and additional ones in-lined further down are for running this BFM on Veloce + // pragma attribute fuse_ctrl_secreg_axi_read_out_monitor_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: AW=%x DW=%x IW=%x UW=%x ", AW,DW,IW,UW), + UVM_DEBUG) +end +`endif + + + // Structure used to pass transaction data from monitor BFM to monitor class in agent. +`fuse_ctrl_secreg_axi_read_out_MONITOR_STRUCT + fuse_ctrl_secreg_axi_read_out_monitor_s fuse_ctrl_secreg_axi_read_out_monitor_struct; + + // Structure used to pass configuration data from monitor class to monitor BFM. + `fuse_ctrl_secreg_axi_read_out_CONFIGURATION_STRUCT + + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + tri clk_i_i; + tri rst_ni_i; + tri arready_i; + tri [DW-1:0] rdata_i; + tri rresp_i; + tri rid_i; + tri rlast_i; + tri rvalid_i; + assign clk_i_i = bus.clk_i; + assign rst_ni_i = bus.rst_ni; + assign arready_i = bus.arready; + assign rdata_i = bus.rdata; + assign rresp_i = bus.rresp; + assign rid_i = bus.rid; + assign rlast_i = bus.rlast; + assign rvalid_i = bus.rvalid; + + // Proxy handle to UVM monitor + fuse_ctrl_secreg_axi_read_out_pkg::fuse_ctrl_secreg_axi_read_out_monitor #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) proxy; + // pragma tbx oneway proxy.notify_transaction + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + task wait_for_reset();// pragma tbx xtf + @(posedge clk_i_i) ; + do_wait_for_reset(); + endtask + + // **************************************************************************** + task do_wait_for_reset(); + // pragma uvmf custom reset_condition begin + wait ( rst_ni_i === 1 ) ; + @(posedge clk_i_i) ; + // pragma uvmf custom reset_condition end + endtask + + //****************************************************************** + + task wait_for_num_clocks(input int unsigned count); // pragma tbx xtf + @(posedge clk_i_i); + + repeat (count-1) @(posedge clk_i_i); + endtask + + //****************************************************************** + event go; + function void start_monitoring();// pragma tbx xtf + -> go; + endfunction + + // **************************************************************************** + initial begin + @go; + forever begin + @(posedge clk_i_i); + do_monitor( fuse_ctrl_secreg_axi_read_out_monitor_struct ); + + + proxy.notify_transaction( fuse_ctrl_secreg_axi_read_out_monitor_struct ); + + end + end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the monitor BFM. It is called by the monitor within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the monitor BFM needs to be aware of the new configuration + // variables. + // + function void configure(fuse_ctrl_secreg_axi_read_out_configuration_s fuse_ctrl_secreg_axi_read_out_configuration_arg); // pragma tbx xtf + initiator_responder = fuse_ctrl_secreg_axi_read_out_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + + + // **************************************************************************** + + task do_monitor(output fuse_ctrl_secreg_axi_read_out_monitor_s fuse_ctrl_secreg_axi_read_out_monitor_struct); + // + // Available struct members: + // // fuse_ctrl_secreg_axi_read_out_monitor_struct.secreg_arready + // // fuse_ctrl_secreg_axi_read_out_monitor_struct.secreg_rdata + // // fuse_ctrl_secreg_axi_read_out_monitor_struct.secreg_rresp + // // fuse_ctrl_secreg_axi_read_out_monitor_struct.secreg_rid + // // fuse_ctrl_secreg_axi_read_out_monitor_struct.secreg_rlast + // // fuse_ctrl_secreg_axi_read_out_monitor_struct.secreg_rvalid + // // + // Reference code; + // How to wait for signal value + // while (control_signal === 1'b1) @(posedge clk_i_i); + // + // How to assign a struct member, named xyz, from a signal. + // All available input signals listed. + // fuse_ctrl_secreg_axi_read_out_monitor_struct.xyz = arready_i; // + // fuse_ctrl_secreg_axi_read_out_monitor_struct.xyz = rdata_i; // [DW-1:0] + // fuse_ctrl_secreg_axi_read_out_monitor_struct.xyz = rresp_i; // + // fuse_ctrl_secreg_axi_read_out_monitor_struct.xyz = rid_i; // + // fuse_ctrl_secreg_axi_read_out_monitor_struct.xyz = rlast_i; // + // fuse_ctrl_secreg_axi_read_out_monitor_struct.xyz = rvalid_i; // + // pragma uvmf custom do_monitor begin + // UVMF_CHANGE_ME : Implement protocol monitoring. The commented reference code + // below are examples of how to capture signal values and assign them to + // structure members. All available input signals are listed. The 'while' + // code example shows how to wait for a synchronous flow control signal. This + // task should return when a complete transfer has been observed. Once this task is + // exited with captured values, it is then called again to wait for and observe + // the next transfer. One clock cycle is consumed between calls to do_monitor. + @(posedge clk_i_i); + @(posedge clk_i_i); + @(posedge clk_i_i); + @(posedge clk_i_i); + // pragma uvmf custom do_monitor end + endtask + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_random_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_random_sequence.svh new file mode 100644 index 0000000..6f16e84 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_random_sequence.svh @@ -0,0 +1,87 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This sequences randomizes the fuse_ctrl_secreg_axi_read_out transaction and sends it +// to the UVM driver. +// +// This sequence constructs and randomizes a fuse_ctrl_secreg_axi_read_out_transaction. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_secreg_axi_read_out_random_sequence #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends fuse_ctrl_secreg_axi_read_out_sequence_base #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ); + + `uvm_object_param_utils( fuse_ctrl_secreg_axi_read_out_random_sequence #( + AW, + DW, + IW, + UW + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //***************************************************************** + function new(string name = ""); + super.new(name); + endfunction: new + + // **************************************************************************** + // TASK : body() + // This task is automatically executed when this sequence is started using the + // start(sequencerHandle) task. + // + task body(); + + // Construct the transaction + req=fuse_ctrl_secreg_axi_read_out_transaction#( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )::type_id::create("req"); + start_item(req); + // Randomize the transaction + if(!req.randomize()) `uvm_fatal("SEQ", "fuse_ctrl_secreg_axi_read_out_random_sequence::body()-fuse_ctrl_secreg_axi_read_out_transaction randomization failed") + // Send the transaction to the fuse_ctrl_secreg_axi_read_out_driver_bfm via the sequencer and fuse_ctrl_secreg_axi_read_out_driver. + finish_item(req); + `uvm_info("SEQ", {"Response:",req.convert2string()},UVM_MEDIUM) + + endtask + +endclass: fuse_ctrl_secreg_axi_read_out_random_sequence + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_responder_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_responder_sequence.svh new file mode 100644 index 0000000..6f646a9 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_responder_sequence.svh @@ -0,0 +1,83 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class can be used to provide stimulus when an interface +// has been configured to run in a responder mode. It +// will never finish by default, always going back to the driver +// and driver BFM for the next transaction with which to respond. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_secreg_axi_read_out_responder_sequence #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends fuse_ctrl_secreg_axi_read_out_sequence_base #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ); + + `uvm_object_param_utils( fuse_ctrl_secreg_axi_read_out_responder_sequence #( + AW, + DW, + IW, + UW + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "fuse_ctrl_secreg_axi_read_out_responder_sequence"); + super.new(name); + endfunction + + task body(); + req=fuse_ctrl_secreg_axi_read_out_transaction#( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )::type_id::create("req"); + forever begin + start_item(req); + finish_item(req); + // pragma uvmf custom body begin + // UVMF_CHANGE_ME : Do something here with the resulting req item. The + // finish_item() call above will block until the req transaction is ready + // to be handled by the responder sequence. + // If this was an item that required a response, the expectation is + // that the response should be populated within this transaction now. + `uvm_info("SEQ",$sformatf("Processed txn: %s",req.convert2string()),UVM_HIGH) + // pragma uvmf custom body end + end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_sequence_base.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_sequence_base.svh new file mode 100644 index 0000000..516bebd --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_sequence_base.svh @@ -0,0 +1,140 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the class used as the base class for all sequences +// for this interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_secreg_axi_read_out_sequence_base #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvmf_sequence_base #( + .REQ(fuse_ctrl_secreg_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + )), + .RSP(fuse_ctrl_secreg_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ))); + + `uvm_object_param_utils( fuse_ctrl_secreg_axi_read_out_sequence_base #( + AW, + DW, + IW, + UW + )) + + // variables + typedef fuse_ctrl_secreg_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) fuse_ctrl_secreg_axi_read_out_transaction_req_t; + fuse_ctrl_secreg_axi_read_out_transaction_req_t req; + typedef fuse_ctrl_secreg_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) fuse_ctrl_secreg_axi_read_out_transaction_rsp_t; + fuse_ctrl_secreg_axi_read_out_transaction_rsp_t rsp; + + // Event for identifying when a response was received from the sequencer + event new_rsp; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // TASK : get_responses() + // This task recursively gets sequence item responses from the sequencer. + // + virtual task get_responses(); + fork + begin + // Block until new rsp available + get_response(rsp); + // New rsp received. Indicate to sequence using event. + ->new_rsp; + // Display the received response transaction + `uvm_info("SEQ", {"New response transaction:",rsp.convert2string()}, UVM_MEDIUM) + end + join_none + endtask + + // **************************************************************************** + // TASK : pre_body() + // This task is called automatically when start is called with call_pre_post set to 1 (default). + // By calling get_responses() within pre_body() any derived sequences are automatically + // processing response transactions. Only un-comment this call to get_responses() if you + // have configured the interface driver to utilize the response transaction path by setting + // the configuration variable "return_transaction_response" to 1. Otherwise it is possible + // to impact runtime performance and memory utilization. + // + virtual task pre_body(); + // pragma uvmf custom pre_body begin +// get_responses(); + // pragma uvmf custom pre_body end + endtask + + // **************************************************************************** + // TASK : body() + // This task is called automatically when start is called. This sequence sends + // a req sequence item to the sequencer identified as an argument in the call + // to start. + // + virtual task body(); + // pragma uvmf custom body begin + start_item(req); + finish_item(req); + // pragma uvmf custom body end + endtask + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name =""); + super.new( name ); + // pragma uvmf custom new begin + req = fuse_ctrl_secreg_axi_read_out_transaction_req_t::type_id::create("req"); + rsp = fuse_ctrl_secreg_axi_read_out_transaction_rsp_t::type_id::create("rsp"); + // pragma uvmf custom new end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_transaction.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_transaction.svh new file mode 100644 index 0000000..9c49e7b --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_transaction.svh @@ -0,0 +1,236 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class defines the variables required for an fuse_ctrl_secreg_axi_read_out +// transaction. Class variables to be displayed in waveform transaction +// viewing are added to the transaction viewing stream in the add_to_wave +// function. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_secreg_axi_read_out_transaction #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvmf_transaction_base; + + `uvm_object_param_utils( fuse_ctrl_secreg_axi_read_out_transaction #( + AW, + DW, + IW, + UW + )) + + logic secreg_arready ; + logic [DW-1:0] secreg_rdata ; + axi_pkg::axi_burst_e secreg_rresp ; + logic [IW-1:0] secreg_rid ; + logic secreg_rlast ; + logic secreg_rvalid ; + + //Constraints for the transaction variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //******************************************************************* + //******************************************************************* + // Macros that define structs and associated functions are + // located in fuse_ctrl_secreg_axi_read_out_macros.svh + + //******************************************************************* + // Monitor macro used by fuse_ctrl_secreg_axi_read_out_monitor and fuse_ctrl_secreg_axi_read_out_monitor_bfm + // This struct is defined in fuse_ctrl_secreg_axi_read_out_macros.svh + `fuse_ctrl_secreg_axi_read_out_MONITOR_STRUCT + fuse_ctrl_secreg_axi_read_out_monitor_s fuse_ctrl_secreg_axi_read_out_monitor_struct; + //******************************************************************* + // FUNCTION: to_monitor_struct() + // This function packs transaction variables into a fuse_ctrl_secreg_axi_read_out_monitor_s + // structure. The function returns the handle to the fuse_ctrl_secreg_axi_read_out_monitor_struct. + // This function is defined in fuse_ctrl_secreg_axi_read_out_macros.svh + `fuse_ctrl_secreg_axi_read_out_TO_MONITOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_monitor_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_secreg_axi_read_out_macros.svh + `fuse_ctrl_secreg_axi_read_out_FROM_MONITOR_STRUCT_FUNCTION + + //******************************************************************* + // Initiator macro used by fuse_ctrl_secreg_axi_read_out_driver and fuse_ctrl_secreg_axi_read_out_driver_bfm + // to communicate initiator driven data to fuse_ctrl_secreg_axi_read_out_driver_bfm. + // This struct is defined in fuse_ctrl_secreg_axi_read_out_macros.svh + `fuse_ctrl_secreg_axi_read_out_INITIATOR_STRUCT + fuse_ctrl_secreg_axi_read_out_initiator_s fuse_ctrl_secreg_axi_read_out_initiator_struct; + //******************************************************************* + // FUNCTION: to_initiator_struct() + // This function packs transaction variables into a fuse_ctrl_secreg_axi_read_out_initiator_s + // structure. The function returns the handle to the fuse_ctrl_secreg_axi_read_out_initiator_struct. + // This function is defined in fuse_ctrl_secreg_axi_read_out_macros.svh + `fuse_ctrl_secreg_axi_read_out_TO_INITIATOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_initiator_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_secreg_axi_read_out_macros.svh + `fuse_ctrl_secreg_axi_read_out_FROM_INITIATOR_STRUCT_FUNCTION + + //******************************************************************* + // Responder macro used by fuse_ctrl_secreg_axi_read_out_driver and fuse_ctrl_secreg_axi_read_out_driver_bfm + // to communicate Responder driven data to fuse_ctrl_secreg_axi_read_out_driver_bfm. + // This struct is defined in fuse_ctrl_secreg_axi_read_out_macros.svh + `fuse_ctrl_secreg_axi_read_out_RESPONDER_STRUCT + fuse_ctrl_secreg_axi_read_out_responder_s fuse_ctrl_secreg_axi_read_out_responder_struct; + //******************************************************************* + // FUNCTION: to_responder_struct() + // This function packs transaction variables into a fuse_ctrl_secreg_axi_read_out_responder_s + // structure. The function returns the handle to the fuse_ctrl_secreg_axi_read_out_responder_struct. + // This function is defined in fuse_ctrl_secreg_axi_read_out_macros.svh + `fuse_ctrl_secreg_axi_read_out_TO_RESPONDER_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_responder_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_secreg_axi_read_out_macros.svh + `fuse_ctrl_secreg_axi_read_out_FROM_RESPONDER_STRUCT_FUNCTION + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + endfunction + + // **************************************************************************** + // FUNCTION: convert2string() + // This function converts all variables in this class to a single string for + // logfile reporting. + // + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + // UVMF_CHANGE_ME : Customize format if desired. + return $sformatf("secreg_arready:0x%x secreg_rdata:0x%x secreg_rresp:0x%x secreg_rid:0x%x secreg_rlast:0x%x secreg_rvalid:0x%x ",secreg_arready,secreg_rdata,secreg_rresp,secreg_rid,secreg_rlast,secreg_rvalid); + // pragma uvmf custom convert2string end + endfunction + + //******************************************************************* + // FUNCTION: do_print() + // This function is automatically called when the .print() function + // is called on this class. + // + virtual function void do_print(uvm_printer printer); + // pragma uvmf custom do_print begin + // UVMF_CHANGE_ME : Current contents of do_print allows for the use of UVM 1.1d, 1.2 or P1800.2. + // Update based on your own printing preference according to your preferred UVM version + $display(convert2string()); + // pragma uvmf custom do_print end + endfunction + + //******************************************************************* + // FUNCTION: do_compare() + // This function is automatically called when the .compare() function + // is called on this class. + // + virtual function bit do_compare (uvm_object rhs, uvm_comparer comparer); + fuse_ctrl_secreg_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) RHS; + if (!$cast(RHS,rhs)) return 0; + // pragma uvmf custom do_compare begin + // UVMF_CHANGE_ME : Eliminate comparison of variables not to be used for compare + return (super.do_compare(rhs,comparer) + &&(this.secreg_arready == RHS.secreg_arready) + &&(this.secreg_rdata == RHS.secreg_rdata) + &&(this.secreg_rresp == RHS.secreg_rresp) + &&(this.secreg_rid == RHS.secreg_rid) + &&(this.secreg_rlast == RHS.secreg_rlast) + &&(this.secreg_rvalid == RHS.secreg_rvalid) + ); + // pragma uvmf custom do_compare end + endfunction + + //******************************************************************* + // FUNCTION: do_copy() + // This function is automatically called when the .copy() function + // is called on this class. + // + virtual function void do_copy (uvm_object rhs); + fuse_ctrl_secreg_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) RHS; + assert($cast(RHS,rhs)); + // pragma uvmf custom do_copy begin + super.do_copy(rhs); + this.secreg_arready = RHS.secreg_arready; + this.secreg_rdata = RHS.secreg_rdata; + this.secreg_rresp = RHS.secreg_rresp; + this.secreg_rid = RHS.secreg_rid; + this.secreg_rlast = RHS.secreg_rlast; + this.secreg_rvalid = RHS.secreg_rvalid; + // pragma uvmf custom do_copy end + endfunction + + // **************************************************************************** + // FUNCTION: add_to_wave() + // This function is used to display variables in this class in the waveform + // viewer. The start_time and end_time variables must be set before this + // function is called. If the start_time and end_time variables are not set + // the transaction will be hidden at 0ns on the waveform display. + // + virtual function void add_to_wave(int transaction_viewing_stream_h); + `ifdef QUESTA + if (transaction_view_h == 0) begin + transaction_view_h = $begin_transaction(transaction_viewing_stream_h,"fuse_ctrl_secreg_axi_read_out_transaction",start_time); + end + super.add_to_wave(transaction_view_h); + // pragma uvmf custom add_to_wave begin + // UVMF_CHANGE_ME : Color can be applied to transaction entries based on content, example below + // case() + // 1 : $add_color(transaction_view_h,"red"); + // default : $add_color(transaction_view_h,"grey"); + // endcase + // UVMF_CHANGE_ME : Eliminate transaction variables not wanted in transaction viewing in the waveform viewer + $add_attribute(transaction_view_h,secreg_arready,"secreg_arready"); + $add_attribute(transaction_view_h,secreg_rdata,"secreg_rdata"); + $add_attribute(transaction_view_h,secreg_rresp,"secreg_rresp"); + $add_attribute(transaction_view_h,secreg_rid,"secreg_rid"); + $add_attribute(transaction_view_h,secreg_rlast,"secreg_rlast"); + $add_attribute(transaction_view_h,secreg_rvalid,"secreg_rvalid"); + // pragma uvmf custom add_to_wave end + $end_transaction(transaction_view_h,end_time); + $free_transaction(transaction_view_h); + `endif // QUESTA + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_transaction_coverage.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_transaction_coverage.svh new file mode 100644 index 0000000..d7a0270 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_transaction_coverage.svh @@ -0,0 +1,104 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class records fuse_ctrl_secreg_axi_read_out transaction information using +// a covergroup named fuse_ctrl_secreg_axi_read_out_transaction_cg. An instance of this +// coverage component is instantiated in the uvmf_parameterized_agent +// if the has_coverage flag is set. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_secreg_axi_read_out_transaction_coverage #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) extends uvm_subscriber #(.T(fuse_ctrl_secreg_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ))); + + `uvm_component_param_utils( fuse_ctrl_secreg_axi_read_out_transaction_coverage #( + AW, + DW, + IW, + UW + )) + + T coverage_trans; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + covergroup fuse_ctrl_secreg_axi_read_out_transaction_cg; + // pragma uvmf custom covergroup begin + // UVMF_CHANGE_ME : Add coverage bins, crosses, exclusions, etc. according to coverage needs. + option.auto_bin_max=1024; + option.per_instance=1; + secreg_arready: coverpoint coverage_trans.secreg_arready; + secreg_rdata: coverpoint coverage_trans.secreg_rdata; + secreg_rresp: coverpoint coverage_trans.secreg_rresp; + secreg_rid: coverpoint coverage_trans.secreg_rid; + secreg_rlast: coverpoint coverage_trans.secreg_rlast; + secreg_rvalid: coverpoint coverage_trans.secreg_rvalid; + // pragma uvmf custom covergroup end + endgroup + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new(string name="", uvm_component parent=null); + super.new(name,parent); + fuse_ctrl_secreg_axi_read_out_transaction_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that transaction variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + endfunction + + // **************************************************************************** + // FUNCTION : build_phase() + // This function is the standard UVM build_phase. + // + function void build_phase(uvm_phase phase); + fuse_ctrl_secreg_axi_read_out_transaction_cg.set_inst_name($sformatf("fuse_ctrl_secreg_axi_read_out_transaction_cg_%s",get_full_name())); + endfunction + + // **************************************************************************** + // FUNCTION: write (T t) + // This function is automatically executed when a transaction arrives on the + // analysis_export. It copies values from the variables in the transaction + // to local variables used to collect functional coverage. + // + virtual function void write (T t); + `uvm_info("COV","Received transaction",UVM_HIGH); + coverage_trans = t; + fuse_ctrl_secreg_axi_read_out_transaction_cg.sample(); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_typedefs.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_typedefs.svh new file mode 100644 index 0000000..f2a7bdb --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_typedefs.svh @@ -0,0 +1,34 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the host server when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_typedefs_hdl.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_typedefs_hdl.svh new file mode 100644 index 0000000..0d58518 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_typedefs_hdl.svh @@ -0,0 +1,35 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the emulator when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/yaml/fuse_ctrl_secreg_axi_read_out_interface.yaml b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/yaml/fuse_ctrl_secreg_axi_read_out_interface.yaml new file mode 100644 index 0000000..a0081ff --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/yaml/fuse_ctrl_secreg_axi_read_out_interface.yaml @@ -0,0 +1,91 @@ +uvmf: + interfaces: + fuse_ctrl_secreg_axi_read_out: + clock: clk_i + config_constraints: [] + config_vars: [] + existing_library_component: 'True' + gen_inbound_streaming_driver: 'False' + hdl_pkg_parameters: [] + hdl_typedefs: [] + hvl_pkg_parameters: [] + hvl_typedefs: [] + parameters: + - name: AW + type: int + value: '32' + - name: DW + type: int + value: '32' + - name: IW + type: int + value: '3' + - name: UW + type: int + value: '32' + ports: + - dir: input + name: arready + reset_value: '''bz' + width: '1' + - dir: input + name: rdata + reset_value: '''bz' + width: DW + - dir: input + name: rresp + reset_value: '''bz' + width: '1' + - dir: input + name: rid + reset_value: '''bz' + width: '1' + - dir: input + name: rlast + reset_value: '''bz' + width: '1' + - dir: input + name: rvalid + reset_value: '''bz' + width: '1' + reset: rst_ni + reset_assertion_level: 'False' + transaction_constraints: [] + transaction_vars: + - comment: '' + iscompare: 'True' + isrand: 'False' + name: secreg_arready + type: logic + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'False' + name: secreg_rdata + type: logic [DW-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'False' + name: secreg_rresp + type: axi_pkg::axi_burst_e + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'False' + name: secreg_rid + type: logic [IW-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'False' + name: secreg_rlast + type: logic + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'False' + name: secreg_rvalid + type: logic + unpacked_dimension: '' + use_dpi_link: 'False' diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/.project b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/.project new file mode 100644 index 0000000..1462dce --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/.project @@ -0,0 +1,37 @@ + + + fuse_ctrl + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + verification_ip + 2 + UVMF_VIP_LIBRARY_HOME + + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D/verification_ip + + + + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/.svproject b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/.svproject new file mode 100644 index 0000000..9e84acf --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/docs/interfaces.csv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/docs/interfaces.csv new file mode 100644 index 0000000..d783ccf --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/docs/interfaces.csv @@ -0,0 +1,42 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +, +Interface Description, Interface Type, Interface Transaction, Interface Name, +fuse_ctrl_rst_in_agent, fuse_ctrl_rst_in_driver_bfm fuse_ctrl_rst_in_monitor_bfm, fuse_ctrl_rst_in_transaction, fuse_ctrl_rst_in_pkg_fuse_ctrl_rst_in_agent_BFM, +fuse_ctrl_rst_out_agent, fuse_ctrl_rst_out_driver_bfm fuse_ctrl_rst_out_monitor_bfm, fuse_ctrl_rst_out_transaction, fuse_ctrl_rst_out_pkg_fuse_ctrl_rst_out_agent_BFM, +fuse_ctrl_core_axi_write_in_if_agent, fuse_ctrl_core_axi_write_in_driver_bfm fuse_ctrl_core_axi_write_in_monitor_bfm, fuse_ctrl_core_axi_write_in_transaction, fuse_ctrl_core_axi_write_in_pkg_fuse_ctrl_core_axi_write_in_if_agent_BFM, +fuse_ctrl_core_axi_write_out_if_agent, fuse_ctrl_core_axi_write_out_driver_bfm fuse_ctrl_core_axi_write_out_monitor_bfm, fuse_ctrl_core_axi_write_out_transaction, fuse_ctrl_core_axi_write_out_pkg_fuse_ctrl_core_axi_write_out_if_agent_BFM, +fuse_ctrl_prim_axi_write_in_if_agent, fuse_ctrl_prim_axi_write_in_driver_bfm fuse_ctrl_prim_axi_write_in_monitor_bfm, fuse_ctrl_prim_axi_write_in_transaction, fuse_ctrl_prim_axi_write_in_pkg_fuse_ctrl_prim_axi_write_in_if_agent_BFM, +fuse_ctrl_prim_axi_write_out_if_agent, fuse_ctrl_prim_axi_write_out_driver_bfm fuse_ctrl_prim_axi_write_out_monitor_bfm, fuse_ctrl_prim_axi_write_out_transaction, fuse_ctrl_prim_axi_write_out_pkg_fuse_ctrl_prim_axi_write_out_if_agent_BFM, +fuse_ctrl_core_axi_read_in_if_agent, fuse_ctrl_core_axi_read_in_driver_bfm fuse_ctrl_core_axi_read_in_monitor_bfm, fuse_ctrl_core_axi_read_in_transaction, fuse_ctrl_core_axi_read_in_pkg_fuse_ctrl_core_axi_read_in_if_agent_BFM, +fuse_ctrl_core_axi_read_out_if_agent, fuse_ctrl_core_axi_read_out_driver_bfm fuse_ctrl_core_axi_read_out_monitor_bfm, fuse_ctrl_core_axi_read_out_transaction, fuse_ctrl_core_axi_read_out_pkg_fuse_ctrl_core_axi_read_out_if_agent_BFM, +fuse_ctrl_prim_axi_read_in_if_agent, fuse_ctrl_prim_axi_read_in_driver_bfm fuse_ctrl_prim_axi_read_in_monitor_bfm, fuse_ctrl_prim_axi_read_in_transaction, fuse_ctrl_prim_axi_read_in_pkg_fuse_ctrl_prim_axi_read_in_if_agent_BFM, +fuse_ctrl_prim_axi_read_out_if_agent, fuse_ctrl_prim_axi_read_out_driver_bfm fuse_ctrl_prim_axi_read_out_monitor_bfm, fuse_ctrl_prim_axi_read_out_transaction, fuse_ctrl_prim_axi_read_out_pkg_fuse_ctrl_prim_axi_read_out_if_agent_BFM, +fuse_ctrl_secreg_axi_read_in_if_agent, fuse_ctrl_secreg_axi_read_in_driver_bfm fuse_ctrl_secreg_axi_read_in_monitor_bfm, fuse_ctrl_secreg_axi_read_in_transaction, fuse_ctrl_secreg_axi_read_in_pkg_fuse_ctrl_secreg_axi_read_in_if_agent_BFM, +fuse_ctrl_secreg_axi_read_out_if_agent, fuse_ctrl_secreg_axi_read_out_driver_bfm fuse_ctrl_secreg_axi_read_out_monitor_bfm, fuse_ctrl_secreg_axi_read_out_transaction, fuse_ctrl_secreg_axi_read_out_pkg_fuse_ctrl_secreg_axi_read_out_if_agent_BFM, +fuse_ctrl_lc_otp_in_if_agent, fuse_ctrl_lc_otp_in_driver_bfm fuse_ctrl_lc_otp_in_monitor_bfm, fuse_ctrl_lc_otp_in_transaction, fuse_ctrl_lc_otp_in_pkg_fuse_ctrl_lc_otp_in_if_agent_BFM, +fuse_ctrl_lc_otp_out_if_agent, fuse_ctrl_lc_otp_out_driver_bfm fuse_ctrl_lc_otp_out_monitor_bfm, fuse_ctrl_lc_otp_out_transaction, fuse_ctrl_lc_otp_out_pkg_fuse_ctrl_lc_otp_out_if_agent_BFM, +fuse_ctrl_in_if_agent, fuse_ctrl_in_driver_bfm fuse_ctrl_in_monitor_bfm, fuse_ctrl_in_transaction, fuse_ctrl_in_pkg_fuse_ctrl_in_if_agent_BFM, +fuse_ctrl_out_if_agent, fuse_ctrl_out_driver_bfm fuse_ctrl_out_monitor_bfm, fuse_ctrl_out_transaction, fuse_ctrl_out_pkg_fuse_ctrl_out_if_agent_BFM, + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/fuse_ctrl_sve.F b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/fuse_ctrl_sve.F new file mode 100644 index 0000000..37457d7 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/fuse_ctrl_sve.F @@ -0,0 +1,42 @@ + +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + +// BFM Files +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_pkg_sve.F +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_pkg_sve.F +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_pkg_sve.F +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_pkg_sve.F +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_pkg_sve.F +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_pkg_sve.F +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_pkg_sve.F +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_pkg_sve.F +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_pkg_sve.F +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_pkg_sve.F +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_pkg_sve.F +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_pkg_sve.F +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_pkg_sve.F +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_pkg_sve.F +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_pkg_sve.F +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_pkg_sve.F + +// Environment Files +-F ${UVMF_VIP_LIBRARY_HOME}/environment_packages/fuse_ctrl_env_pkg/fuse_ctrl_env_pkg_sve.F + +// Bench Files ++incdir+./tb/tests +./tb/tests/fuse_ctrl_tests_pkg.sv + ++incdir+./tb/sequences +./tb/sequences/fuse_ctrl_sequences_pkg.sv + ++incdir+./tb/parameters +./tb/parameters/fuse_ctrl_parameters_pkg.sv + +./tb/testbench/hdl_top.sv +./tb/testbench/hvl_top.sv + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/rtl/dut.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/rtl/dut.compile new file mode 100644 index 0000000..9b0008f --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/rtl/dut.compile @@ -0,0 +1,6 @@ + +# pragma uvmf custom dut_compile_info begin +src: + - ./vhdl/vhdl_dut.vhd + - ./verilog/verilog_dut.v +# pragma uvmf custom dut_compile_info end diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/rtl/verilog/verilog_dut.v b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/rtl/verilog/verilog_dut.v new file mode 100644 index 0000000..9619844 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/rtl/verilog/verilog_dut.v @@ -0,0 +1,21 @@ +module verilog_dut(clk, rst, in_signal, out_signal); + +input clk; +input rst; +input in_signal; +output out_signal; + +reg out_signal_o; + +always @(posedge clk) begin + if (rst) begin + out_signal_o <= 0; + end + else begin + out_signal_o <= ~in_signal; + end + end + +assign out_signal = out_signal_o; + +endmodule diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/rtl/verilog/verilog_dut.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/rtl/verilog/verilog_dut.vinfo new file mode 100644 index 0000000..87e95f3 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/rtl/verilog/verilog_dut.vinfo @@ -0,0 +1 @@ +verilog_dut.v diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/rtl/vhdl/vhdl_dut.vhd b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/rtl/vhdl/vhdl_dut.vhd new file mode 100644 index 0000000..904aa37 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/rtl/vhdl/vhdl_dut.vhd @@ -0,0 +1,21 @@ +library ieee; +use ieee.std_logic_1164.all ; + +entity vhdl_dut is + port ( clk : in std_logic ; + rst : in std_logic ; + in_signal : in std_logic ; + out_signal :out std_logic + ); +end vhdl_dut; + +architecture rtl of vhdl_dut is + begin + P1: process + variable out_signal_o : std_logic; + begin + wait until clk'event and clk = '1'; + out_signal_o := in_signal; + out_signal <= out_signal_o; + end process; + end rtl; diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/sim/Makefile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/sim/Makefile new file mode 100644 index 0000000..2a9a2e5 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/sim/Makefile @@ -0,0 +1,377 @@ + +# +#---------------------------------------------------------------------- +# +# DESCRIPTION: This makefile includes the shared makefile and contains +# bench level make targets. +# +#---------------------------------------------------------------------- + + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +# ********************************************************************************************* +# UVMF library directory: +# This variable points to the UVMF release where uvmf_base_pkg directory resides. +# This variable points to release code that is not user modified. +# This variable allows for UVMF release directories to reside independent of project related verification IP and project bench directories. +# This code below looks "upward" for directory starting with UVMF_* and returns first match for use with the release examples. +UVMF_HOME ?= ___PLEASE_SET_AN_ENVIRONMENT_VARIABLE_NAMED_UVMF_HOME_TO_POINT_TO_THE_UVMF_INSTALLATION___ + +# pragma uvmf custom exports begin +# +# Project(s) specific verification IP library: +# Directory where reusable verification packages for interfaces, environments, utilities, etc. reside. +# This variable allows for your verification IP to reside independent of project bench and UVMF release directories. +# For examples deployed with UVMF this will be $(UVMF_HOME)//verification_ip +export UVMF_VIP_LIBRARY_HOME ?= $(PWD)/../../../verification_ip +# +# Project specific bench: +# Directory where bench specific code is located. +# This variable allows for project_benches to reside independent of verification IP and UVMF release directories. +# For examples deployed with UVMF this will be $(UVMF_HOME)//project_benches/ +export UVMF_PROJECT_DIR ?= $(PWD)/.. +# +# +# pragma uvmf custom exports end +# ********************************************************************************************* + +## Check PATH for required vinfo scripts +PVAL := $(shell command -v make_filelist.py 2> /dev/null) +ifndef PVAL + MFLIST = $(UVMF_HOME)/scripts/make_filelist.py +else + MFLIST = make_filelist.py +endif + + +# Set test case specific Variables +TEST_NAME ?= test_top + +TEST_SEED ?= random +UVM_CLI_ARGS = + +# Usage of Veloce, etc. to be input by the user (subject to defaults) +USE_VELOCE ?= 0 + +# Usage of vinfo flow for generating file list +USE_VINFO ?= 0 + +# Usage of Veloce and Questa profilers +USE_VELOCE_PROFILER ?= 0 +USE_QUESTA_PROFILER ?= 0 + + +# Set project Variables +TEST_PLAN_NAME = fuse_ctrl_TestPlan +REPORTING_DO_FILE = fuse_ctrl_reports_script + + +# Include makefile that includes targets for UVM_VIP_Library packages +include $(UVMF_HOME)/scripts/Makefile + + + + +# Include all requisite interface package targets for this bench +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_in_pkg/Makefile +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_out_pkg/Makefile +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_write_in_pkg/Makefile +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_write_out_pkg/Makefile +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/Makefile +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/Makefile +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_read_in_pkg/Makefile +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_read_out_pkg/Makefile +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/Makefile +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/Makefile +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/Makefile +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/Makefile +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_lc_otp_in_pkg/Makefile +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_lc_otp_out_pkg/Makefile +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_in_pkg/Makefile +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_out_pkg/Makefile + +# Include all requisite environment package targets for this bench +include $(UVMF_VIP_LIBRARY_HOME)/environment_packages/fuse_ctrl_env_pkg/Makefile + + + +# Add to default compile/load/run arguments +VCOM_ARGS += + +# Note: vsim-3009 error can be eliminated by adding -timescale 1ps/1ps to VLOG_ARGS + +VLOG_ARGS += $(UVM_DISABLE_FILE_LINE_CMD) + +VELANALYZE_ARGS += +VELANALYZE_HVL_ARGS += + +BATCH_VOPT_ARGS += +DEBUG_VOPT_ARGS += +EXTRA_VOPT_TOPS += +COMMON_VSIM_ARGS += +COMMON_VSIM_ARGS += + + +BATCH_VSIM_ARGS += #-uvmcontrol=none +DEBUG_VSIM_ARGS += +EXTRA_VSIM_TOPS += + +# pragma uvmf custom additional_args begin +# pragma uvmf custom additional_args end + + +# Project bench package source +fuse_ctrl_PARAMETERS_PKG ?=\ +$(UVMF_PROJECT_DIR)/tb/parameters/fuse_ctrl_parameters_pkg.sv + + +fuse_ctrl_SEQUENCES_PKG ?=\ +$(UVMF_PROJECT_DIR)/tb/sequences/fuse_ctrl_sequences_pkg.sv + + +fuse_ctrl_TEST_PKG ?=\ +$(UVMF_PROJECT_DIR)/tb/tests/fuse_ctrl_tests_pkg.sv + +# pragma uvmf custom dut_files begin +# UVMF_CHANGE_ME : Reference Verilog DUT source. +fuse_ctrl_VERILOG_DUT ?=\ +$(UVMF_PROJECT_DIR)/../../../../../integration/rtl/config_defines.svh \ +$(UVMF_PROJECT_DIR)/../../../../../integration/rtl/caliptra_reg_defines.svh \ +$(UVMF_PROJECT_DIR)/../../../../../libs/rtl/caliptra_sva.svh \ +$(UVMF_PROJECT_DIR)/../../../../../libs/rtl/caliptra_macros.svh \ +$(UVMF_PROJECT_DIR)/../../../../../libs/rtl/caliptra_sram.sv \ +$(UVMF_PROJECT_DIR)/../../../../../libs/rtl/ahb_defines_pkg.sv \ +$(UVMF_PROJECT_DIR)/../../../../../libs/rtl/caliptra_ahb_srom.sv \ +$(UVMF_PROJECT_DIR)/../../../../../libs/rtl/apb_slv_sif.sv \ +$(UVMF_PROJECT_DIR)/../../../../../libs/rtl/ahb_slv_sif.sv \ +$(UVMF_PROJECT_DIR)/../../../../../libs/rtl/caliptra_icg.sv \ +$(UVMF_PROJECT_DIR)/../../../../../libs/rtl/clk_gate.sv \ +$(UVMF_PROJECT_DIR)/../../../../../libs/rtl/caliptra_2ff_sync.sv \ +$(UVMF_PROJECT_DIR)/../../../../../libs/rtl/ahb_to_reg_adapter.sv \ +$(UVMF_PROJECT_DIR)/../../../../../libs/rtl/skidbuffer.v \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_util_pkg.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_alert_pkg.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_subreg_pkg.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_mubi_pkg.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_cipher_pkg.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_pkg.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_sparse_fsm_pkg.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_secded_pkg.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_otp_pkg.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_ram_1p_pkg.sv \ +$(UVMF_PROJECT_DIR)/../../../../../lc_ctrl/rtl/lc_ctrl_reg_pkg.sv \ +$(UVMF_PROJECT_DIR)/../../../../../lc_ctrl/rtl/lc_ctrl_state_pkg.sv \ +$(UVMF_PROJECT_DIR)/../../../../../lc_ctrl/rtl/lc_ctrl_pkg.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim_generic/rtl/caliptra_prim_generic_flop_en.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim_generic/rtl/caliptra_prim_generic_flop.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim_generic/rtl/caliptra_prim_generic_buf.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim_generic/rtl/caliptra_prim_generic_otp.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim_generic/rtl/caliptra_prim_generic_ram_1p.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim_generic/rtl/caliptra_prim_generic_and2.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_flop_en.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_cdc_rand_delay.sv@(posedge clk_i_i); \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_flop_2sync.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_lfsr.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_double_lfsr.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_arbiter_fixed.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_arbiter_tree.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_edn_req.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_present.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_lc_sender.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_sync_reqack.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_sync_reqack_data.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_mubi4_sync.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_diff_decode.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_sec_anchor_buf.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_slicer.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_count.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_sparse_fsm_flop.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_dom_and_2share.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_sec_anchor_flop.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_reg_we_check.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_packer_fifo.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_max_tree.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_subreg_arb.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_subreg.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_intr_hw.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_onehot_check.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_mubi8_sync.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_mubi8_sender.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_fifo_sync_cnt.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_buf.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_lc_sync.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_alert_receiver.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_flop.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_alert_sender.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_fifo_sync.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_arbiter_ppc.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_sum_tree.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_subreg_ext.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_edge_detector.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_blanker.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_ram_1p_adv.sv \ +$(UVMF_PROJECT_DIR)/../../../../../tlul/rtl/tlul_pkg.sv \ +$(UVMF_PROJECT_DIR)/../../../../../tlul/rtl/tlul_assert_multiple.sv \ +$(UVMF_PROJECT_DIR)/../../../../../tlul/rtl/tlul_assert.sv \ +$(UVMF_PROJECT_DIR)/../../../../../tlul/rtl/sram2tlul.sv \ +$(UVMF_PROJECT_DIR)/../../../../../tlul/rtl/tlul_adapter_host.sv \ +$(UVMF_PROJECT_DIR)/../../../../../tlul/rtl/tlul_adapter_reg.sv \ +$(UVMF_PROJECT_DIR)/../../../../../tlul/rtl/tlul_adapter_sram.sv \ +$(UVMF_PROJECT_DIR)/../../../../../tlul/rtl/tlul_cmd_intg_chk.sv \ +$(UVMF_PROJECT_DIR)/../../../../../tlul/rtl/tlul_cmd_intg_gen.sv \ +$(UVMF_PROJECT_DIR)/../../../../../tlul/rtl/tlul_data_integ_dec.sv \ +$(UVMF_PROJECT_DIR)/../../../../../tlul/rtl/tlul_data_integ_enc.sv \ +$(UVMF_PROJECT_DIR)/../../../../../tlul/rtl/tlul_err_resp.sv \ +$(UVMF_PROJECT_DIR)/../../../../../tlul/rtl/tlul_err.sv \ +$(UVMF_PROJECT_DIR)/../../../../../tlul/rtl/tlul_fifo_async.sv \ +$(UVMF_PROJECT_DIR)/../../../../../tlul/rtl/tlul_fifo_sync.sv \ +$(UVMF_PROJECT_DIR)/../../../../../tlul/rtl/tlul_lc_gate.sv \ +$(UVMF_PROJECT_DIR)/../../../../../tlul/rtl/tlul_rsp_intg_chk.sv \ +$(UVMF_PROJECT_DIR)/../../../../../tlul/rtl/tlul_rsp_intg_gen.sv \ +$(UVMF_PROJECT_DIR)/../../../../../tlul/rtl/tlul_socket_1n.sv \ +$(UVMF_PROJECT_DIR)/../../../../../tlul/rtl/tlul_socket_m1.sv \ +$(UVMF_PROJECT_DIR)/../../../../../tlul/rtl/tlul_sram_byte.sv \ +$(UVMF_PROJECT_DIR)/../../../../../axi/rtl/axi_pkg.sv \ +$(UVMF_PROJECT_DIR)/../../../../../axi/rtl/axi_if.sv \ +$(UVMF_PROJECT_DIR)/../../../../../axi/rtl/axi_addr.v \ +$(UVMF_PROJECT_DIR)/../../../../../axi/rtl/axi_sub_rd.sv \ +$(UVMF_PROJECT_DIR)/../../../../../axi/rtl/axi_sub_wr.sv \ +$(UVMF_PROJECT_DIR)/../../../../../axi/rtl/axi_sub_arb.sv \ +$(UVMF_PROJECT_DIR)/../../../../../axi/rtl/axi_sub.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_secded_22_16_dec.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_secded_22_16_enc.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_secded_28_22_dec.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_secded_28_22_enc.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_secded_39_32_dec.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_secded_39_32_enc.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_secded_64_57_dec.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_secded_64_57_enc.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_secded_72_64_dec.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_secded_72_64_enc.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_secded_hamming_22_16_dec.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_secded_hamming_22_16_enc.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_secded_hamming_39_32_dec.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_secded_hamming_39_32_enc.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_secded_hamming_72_64_dec.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_secded_hamming_72_64_enc.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_secded_hamming_76_68_dec.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_secded_hamming_76_68_enc.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_secded_inv_22_16_dec.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_secded_inv_22_16_enc.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_secded_inv_28_22_dec.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_secded_inv_28_22_enc.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_secded_inv_39_32_dec.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_secded_inv_39_32_enc.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_secded_inv_64_57_dec.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_secded_inv_64_57_enc.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_secded_inv_72_64_dec.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_secded_inv_72_64_enc.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_secded_inv_hamming_22_16_dec.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_secded_inv_hamming_22_16_enc.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_secded_inv_hamming_39_32_dec.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_secded_inv_hamming_39_32_enc.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_secded_inv_hamming_72_64_dec.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_secded_inv_hamming_72_64_enc.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_secded_inv_hamming_76_68_dec.sv \ +$(UVMF_PROJECT_DIR)/../../../../../caliptra_prim/rtl/caliptra_prim_secded_inv_hamming_76_68_enc.sv \ +$(UVMF_PROJECT_DIR)/../../../../../axi2tlul/rtl/axi2tlul_cmd_intg_gen.sv \ +$(UVMF_PROJECT_DIR)/../../../../../axi2tlul/rtl/sub2tlul.sv \ +$(UVMF_PROJECT_DIR)/../../../../../axi2tlul/rtl/axi2tlul.sv \ +$(UVMF_PROJECT_DIR)/../../../../../entropy_src/rtl/entropy_src_main_sm_pkg.sv \ +$(UVMF_PROJECT_DIR)/../../../../../entropy_src/rtl/entropy_src_ack_sm_pkg.sv \ +$(UVMF_PROJECT_DIR)/../../../../../entropy_src/rtl/entropy_src_reg_pkg.sv \ +$(UVMF_PROJECT_DIR)/../../../../../entropy_src/rtl/entropy_src_pkg.sv \ +$(UVMF_PROJECT_DIR)/../../../../../edn/rtl/edn_pkg.sv \ +$(UVMF_PROJECT_DIR)/../../../../../ast/rtl/ast_pkg.sv \ +$(UVMF_PROJECT_DIR)/../../../../../pwrmgr/rtl/pwrmgr_reg_pkg.sv \ +$(UVMF_PROJECT_DIR)/../../../../../pwrmgr/rtl/pwrmgr_pkg.sv \ +$(UVMF_PROJECT_DIR)/../../../../rtl/caliptra_otp_ctrl_reg_pkg.sv \ +$(UVMF_PROJECT_DIR)/../../../../rtl/caliptra_otp_ctrl_pkg.sv \ +$(UVMF_PROJECT_DIR)/../../../../rtl/caliptra_otp_ctrl_part_pkg.sv \ +$(UVMF_PROJECT_DIR)/../../../../rtl/caliptra_otp_ctrl_core_reg_top.sv \ +$(UVMF_PROJECT_DIR)/../../../../rtl/caliptra_otp_ctrl_prim_reg_top.sv \ +$(UVMF_PROJECT_DIR)/../../../../rtl/otp_ctrl_dai.sv \ +$(UVMF_PROJECT_DIR)/../../../../rtl/otp_ctrl_ecc_reg.sv \ +$(UVMF_PROJECT_DIR)/../../../../rtl/otp_ctrl_lci.sv \ +$(UVMF_PROJECT_DIR)/../../../../rtl/otp_ctrl_lfsr_timer.sv \ +$(UVMF_PROJECT_DIR)/../../../../rtl/otp_ctrl_part_buf.sv \ +$(UVMF_PROJECT_DIR)/../../../../rtl/otp_ctrl_part_unbuf.sv \ +$(UVMF_PROJECT_DIR)/../../../../rtl/otp_ctrl_scrmbl.sv \ +$(UVMF_PROJECT_DIR)/../../../../rtl/otp_ctrl.sv \ +$(UVMF_PROJECT_DIR)/../../../../rtl/otp_ctrl_top.sv + + +# UVMF_CHANGE_ME : Reference VHDL DUT source. +fuse_ctrl_VHDL_DUT ?=\ +$(UVMF_PROJECT_DIR)/rtl/vhdl/vhdl_dut.vhd +# pragma uvmf custom dut_files end + + +# Project bench package targets +COMP_fuse_ctrl_PARAMETERS_PKG_TGT_0 = q_comp_fuse_ctrl_parameters_pkg +COMP_fuse_ctrl_PARAMETERS_PKG_TGT_1 = v_comp_fuse_ctrl_parameters_pkg +COMP_fuse_ctrl_PARAMETERS_PKG_TGT = $(COMP_fuse_ctrl_PARAMETERS_PKG_TGT_$(USE_VELOCE)) + +comp_fuse_ctrl_parameters_pkg: $(COMP_fuse_ctrl_PARAMETERS_PKG_TGT) + +q_comp_fuse_ctrl_parameters_pkg: + $(HVL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/parameters $(fuse_ctrl_PARAMETERS_PKG) + +v_comp_fuse_ctrl_parameters_pkg: q_comp_fuse_ctrl_parameters_pkg + $(HDL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/parameters $(fuse_ctrl_PARAMETERS_PKG) + + +comp_fuse_ctrl_sequence_pkg: + $(HVL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/sequences $(fuse_ctrl_SEQUENCES_PKG) + +comp_fuse_ctrl_tests_pkg: + $(HVL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/tests $(fuse_ctrl_TEST_PKG) + +# pragma uvmf custom dut_compile_make_target begin +# UVMF_CHANGE_ME : Add make target to compile your verilog dut here +comp_fuse_ctrl_verilog_dut: + echo "Compile your verilog DUT here" + $(HDL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/../../../../../libs/rtl $(fuse_ctrl_VERILOG_DUT) + +# UVMF_CHANGE_ME : Add make target to compile your vhdl dut here +comp_fuse_ctrl_vhdl_dut: + echo "Compile your vhdl DUT here" + $(HDL_COMP_CMD_VHDL) $(fuse_ctrl_VHDL_DUT) + +# UVMF_CHANGE_ME : Add make target to compile your dut here +comp_fuse_ctrl_dut: comp_fuse_ctrl_vhdl_dut comp_fuse_ctrl_verilog_dut +# pragma uvmf custom dut_compile_make_target end + + +BUILD_TGT_0 = make_build +BUILD_TGT_1 = vinfo_build +BUILD_TGT = $(BUILD_TGT_$(USE_VINFO)) + + +comp_hvl : comp_hvl_core + + +comp_hvl_core : \ + comp_fuse_ctrl_rst_in_pkg comp_fuse_ctrl_rst_out_pkg comp_fuse_ctrl_core_axi_write_in_pkg comp_fuse_ctrl_core_axi_write_out_pkg comp_fuse_ctrl_prim_axi_write_in_pkg comp_fuse_ctrl_prim_axi_write_out_pkg comp_fuse_ctrl_core_axi_read_in_pkg comp_fuse_ctrl_core_axi_read_out_pkg comp_fuse_ctrl_prim_axi_read_in_pkg comp_fuse_ctrl_prim_axi_read_out_pkg comp_fuse_ctrl_secreg_axi_read_in_pkg comp_fuse_ctrl_secreg_axi_read_out_pkg comp_fuse_ctrl_lc_otp_in_pkg comp_fuse_ctrl_lc_otp_out_pkg comp_fuse_ctrl_in_pkg comp_fuse_ctrl_out_pkg \ + comp_fuse_ctrl_env_pkg \ + comp_fuse_ctrl_parameters_pkg comp_fuse_ctrl_sequence_pkg comp_fuse_ctrl_tests_pkg + +comp_uvmf_core : comp_uvm_pkg comp_uvmf_base_pkg + +make_build: comp_fuse_ctrl_dut comp_uvmf_core comp_hvl comp_test_bench + +hvl_build: q_comp_fuse_ctrl_rst_in_pkg q_comp_fuse_ctrl_rst_out_pkg q_comp_fuse_ctrl_core_axi_write_in_pkg q_comp_fuse_ctrl_core_axi_write_out_pkg q_comp_fuse_ctrl_prim_axi_write_in_pkg q_comp_fuse_ctrl_prim_axi_write_out_pkg q_comp_fuse_ctrl_core_axi_read_in_pkg q_comp_fuse_ctrl_core_axi_read_out_pkg q_comp_fuse_ctrl_prim_axi_read_in_pkg q_comp_fuse_ctrl_prim_axi_read_out_pkg q_comp_fuse_ctrl_secreg_axi_read_in_pkg q_comp_fuse_ctrl_secreg_axi_read_out_pkg q_comp_fuse_ctrl_lc_otp_in_pkg q_comp_fuse_ctrl_lc_otp_out_pkg q_comp_fuse_ctrl_in_pkg q_comp_fuse_ctrl_out_pkg comp_fuse_ctrl_env_pkg comp_fuse_ctrl_sequence_pkg comp_fuse_ctrl_tests_pkg hvl_comp_testbench link optimize + + +vinfo_build: comp_fuse_ctrl_vhdl_dut build_hdl_vinfo build_hvl_vinfo $(VINFO_TGT) + + $(HDL_COMP_CMD) -F hdl.vf + $(VEL_COMP) + +build: $(BUILD_TGT) + +# pragma uvmf custom additional_targets begin +# pragma uvmf custom additional_targets end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/sim/bcr_testlist b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/sim/bcr_testlist new file mode 100644 index 0000000..4df4567 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/sim/bcr_testlist @@ -0,0 +1,19 @@ + + + +# Test list for use by RMDB file +# File syntax is +# TB_INFO { } { } +# TB ## All subsequent tests will run on this bench until a different "TB" line is seen +# TEST <1st_seed> ... +# If not enough seeds are provided then random seeds are used to pad +# If no repeat count is given, default is 1 +# pragma uvmf custom tb_info begin +TB_INFO fuse_ctrl { } { } +# pragma uvmf custom tb_info end +TB fuse_ctrl +# pragma uvmf custom regression_suite begin +TEST test_top 3 +# pragma uvmf custom regression_suite end + + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/sim/bcr_testlist.yaml b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/sim/bcr_testlist.yaml new file mode 100644 index 0000000..65b6be0 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/sim/bcr_testlist.yaml @@ -0,0 +1,44 @@ + + + +# YAML test list for use by RMDB file +# File syntax is +# uvmf_testlist: +# testbenches: +# - name: +# extra_build_options: +# extra_run_options: +# - name: +# ... +# - name: +# tests: +# - name: +# uvm_testname: (defaults to test_name) +# testbench: (defaults to last tb name seen) +# repeat: (defaults to 1) +# seeds: [,,...,] (defaults to all random) +# extra_test_options: +# - name: +# ... +# - name: +# include: +# - (relative path reference is to the including YAML file) +# - +# ... +# - + +uvmf_testlist: + testbenches: +# pragma uvmf custom tb_info begin + - name: fuse_ctrl + extra_build_options: "" + extra_run_options: "" +# pragma uvmf custom tb_info end + tests: + - testbench: fuse_ctrl +# pragma uvmf custom regression_suite begin + - name: test_top + repeat: 3 +# pragma uvmf custom regression_suite end + + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/sim/compile.do b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/sim/compile.do new file mode 100644 index 0000000..be95260 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/sim/compile.do @@ -0,0 +1,85 @@ + + +################################################################## +## ENVIRONMENT VARIABLES +################################################################## +quietly set ::env(UVMF_VIP_LIBRARY_HOME) ../../../verification_ip +quietly set ::env(UVMF_PROJECT_DIR) .. + +## Using VRM means that the build is occuring several more directories deeper underneath +## the sim directory, need to prepend some more '..' +if {[info exists ::env(VRM_BUILD)]} { + quietly set ::env(UVMF_VIP_LIBRARY_HOME) "../../../../../$::env(UVMF_VIP_LIBRARY_HOME)" + quietly set ::env(UVMF_PROJECT_DIR) "../../../../../$::env(UVMF_PROJECT_DIR)" +} +quietly set ::env(UVMF_VIP_LIBRARY_HOME) [file normalize $::env(UVMF_VIP_LIBRARY_HOME)] +quietly set ::env(UVMF_PROJECT_DIR) [file normalize $::env(UVMF_PROJECT_DIR)] +quietly echo "UVMF_VIP_LIBRARY_HOME = $::env(UVMF_VIP_LIBRARY_HOME)" +quietly echo "UVMF_PROJECT_DIR = $::env(UVMF_PROJECT_DIR)" + + +################################################################### +## HOUSEKEEPING : DELETE FILES THAT WILL BE REGENERATED +################################################################### +file delete -force *~ *.ucdb vsim.dbg *.vstf *.log work *.mem *.transcript.txt certe_dump.xml *.wlf covhtmlreport VRMDATA +file delete -force design.bin qwave.db dpiheader.h visualizer*.ses +file delete -force veloce.med veloce.wave veloce.map tbxbindings.h edsenv velrunopts.ini +file delete -force sv_connect.* + +################################################################### +## COMPILE DUT SOURCE CODE +################################################################### +vlib work +# pragma uvmf custom dut_compile_dofile_target begin +# UVMF_CHANGE_ME : Add commands to compile your dut here, replacing the default examples +#vlog -sv -timescale 1ps/1ps -suppress 2223,2286 $env(UVMF_PROJECT_DIR)/rtl/verilog/verilog_dut.v +#vcom $env(UVMF_PROJECT_DIR)/rtl/vhdl/vhdl_dut.vhd +# pragma uvmf custom dut_compile_dofile_target end + +################################################################### +## COMPILE UVMF BASE/COMMON SOURCE CODE +################################################################### +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_HOME)/uvmf_base_pkg -F $env(UVMF_HOME)/uvmf_base_pkg/uvmf_base_pkg_filelist_hdl.f +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_HOME)/uvmf_base_pkg -F $env(UVMF_HOME)/uvmf_base_pkg/uvmf_base_pkg_filelist_hvl.f + + +################################################################### +## UVMF INTERFACE COMPILATION +################################################################### +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_in_pkg/compile.do +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_out_pkg/compile.do +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_write_in_pkg/compile.do +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_write_out_pkg/compile.do +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/compile.do +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/compile.do +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_read_in_pkg/compile.do +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_read_out_pkg/compile.do +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/compile.do +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/compile.do +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/compile.do +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/compile.do +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_lc_otp_in_pkg/compile.do +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_lc_otp_out_pkg/compile.do +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_in_pkg/compile.do +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_out_pkg/compile.do + +################################################################### +## UVMF ENVIRONMENT COMPILATION +################################################################### +do $env(UVMF_VIP_LIBRARY_HOME)/environment_packages/fuse_ctrl_env_pkg/compile.do + +################################################################### +## UVMF BENCHES COMPILATION +################################################################### +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/parameters $env(UVMF_PROJECT_DIR)/tb/parameters/fuse_ctrl_parameters_pkg.sv +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/sequences $env(UVMF_PROJECT_DIR)/tb/sequences/fuse_ctrl_sequences_pkg.sv +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/tests $env(UVMF_PROJECT_DIR)/tb/tests/fuse_ctrl_tests_pkg.sv + +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/testbench -F $env(UVMF_PROJECT_DIR)/tb/testbench/top_filelist_hdl.f +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/testbench -F $env(UVMF_PROJECT_DIR)/tb/testbench/top_filelist_hvl.f + +################################################################### +## OPTIMIZATION +################################################################### +vopt hvl_top hdl_top -o optimized_batch_top_tb +vopt +acc hvl_top hdl_top -o optimized_debug_top_tb diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/sim/docs/interfaces.csv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/sim/docs/interfaces.csv new file mode 100644 index 0000000..d783ccf --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/sim/docs/interfaces.csv @@ -0,0 +1,42 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +, +Interface Description, Interface Type, Interface Transaction, Interface Name, +fuse_ctrl_rst_in_agent, fuse_ctrl_rst_in_driver_bfm fuse_ctrl_rst_in_monitor_bfm, fuse_ctrl_rst_in_transaction, fuse_ctrl_rst_in_pkg_fuse_ctrl_rst_in_agent_BFM, +fuse_ctrl_rst_out_agent, fuse_ctrl_rst_out_driver_bfm fuse_ctrl_rst_out_monitor_bfm, fuse_ctrl_rst_out_transaction, fuse_ctrl_rst_out_pkg_fuse_ctrl_rst_out_agent_BFM, +fuse_ctrl_core_axi_write_in_if_agent, fuse_ctrl_core_axi_write_in_driver_bfm fuse_ctrl_core_axi_write_in_monitor_bfm, fuse_ctrl_core_axi_write_in_transaction, fuse_ctrl_core_axi_write_in_pkg_fuse_ctrl_core_axi_write_in_if_agent_BFM, +fuse_ctrl_core_axi_write_out_if_agent, fuse_ctrl_core_axi_write_out_driver_bfm fuse_ctrl_core_axi_write_out_monitor_bfm, fuse_ctrl_core_axi_write_out_transaction, fuse_ctrl_core_axi_write_out_pkg_fuse_ctrl_core_axi_write_out_if_agent_BFM, +fuse_ctrl_prim_axi_write_in_if_agent, fuse_ctrl_prim_axi_write_in_driver_bfm fuse_ctrl_prim_axi_write_in_monitor_bfm, fuse_ctrl_prim_axi_write_in_transaction, fuse_ctrl_prim_axi_write_in_pkg_fuse_ctrl_prim_axi_write_in_if_agent_BFM, +fuse_ctrl_prim_axi_write_out_if_agent, fuse_ctrl_prim_axi_write_out_driver_bfm fuse_ctrl_prim_axi_write_out_monitor_bfm, fuse_ctrl_prim_axi_write_out_transaction, fuse_ctrl_prim_axi_write_out_pkg_fuse_ctrl_prim_axi_write_out_if_agent_BFM, +fuse_ctrl_core_axi_read_in_if_agent, fuse_ctrl_core_axi_read_in_driver_bfm fuse_ctrl_core_axi_read_in_monitor_bfm, fuse_ctrl_core_axi_read_in_transaction, fuse_ctrl_core_axi_read_in_pkg_fuse_ctrl_core_axi_read_in_if_agent_BFM, +fuse_ctrl_core_axi_read_out_if_agent, fuse_ctrl_core_axi_read_out_driver_bfm fuse_ctrl_core_axi_read_out_monitor_bfm, fuse_ctrl_core_axi_read_out_transaction, fuse_ctrl_core_axi_read_out_pkg_fuse_ctrl_core_axi_read_out_if_agent_BFM, +fuse_ctrl_prim_axi_read_in_if_agent, fuse_ctrl_prim_axi_read_in_driver_bfm fuse_ctrl_prim_axi_read_in_monitor_bfm, fuse_ctrl_prim_axi_read_in_transaction, fuse_ctrl_prim_axi_read_in_pkg_fuse_ctrl_prim_axi_read_in_if_agent_BFM, +fuse_ctrl_prim_axi_read_out_if_agent, fuse_ctrl_prim_axi_read_out_driver_bfm fuse_ctrl_prim_axi_read_out_monitor_bfm, fuse_ctrl_prim_axi_read_out_transaction, fuse_ctrl_prim_axi_read_out_pkg_fuse_ctrl_prim_axi_read_out_if_agent_BFM, +fuse_ctrl_secreg_axi_read_in_if_agent, fuse_ctrl_secreg_axi_read_in_driver_bfm fuse_ctrl_secreg_axi_read_in_monitor_bfm, fuse_ctrl_secreg_axi_read_in_transaction, fuse_ctrl_secreg_axi_read_in_pkg_fuse_ctrl_secreg_axi_read_in_if_agent_BFM, +fuse_ctrl_secreg_axi_read_out_if_agent, fuse_ctrl_secreg_axi_read_out_driver_bfm fuse_ctrl_secreg_axi_read_out_monitor_bfm, fuse_ctrl_secreg_axi_read_out_transaction, fuse_ctrl_secreg_axi_read_out_pkg_fuse_ctrl_secreg_axi_read_out_if_agent_BFM, +fuse_ctrl_lc_otp_in_if_agent, fuse_ctrl_lc_otp_in_driver_bfm fuse_ctrl_lc_otp_in_monitor_bfm, fuse_ctrl_lc_otp_in_transaction, fuse_ctrl_lc_otp_in_pkg_fuse_ctrl_lc_otp_in_if_agent_BFM, +fuse_ctrl_lc_otp_out_if_agent, fuse_ctrl_lc_otp_out_driver_bfm fuse_ctrl_lc_otp_out_monitor_bfm, fuse_ctrl_lc_otp_out_transaction, fuse_ctrl_lc_otp_out_pkg_fuse_ctrl_lc_otp_out_if_agent_BFM, +fuse_ctrl_in_if_agent, fuse_ctrl_in_driver_bfm fuse_ctrl_in_monitor_bfm, fuse_ctrl_in_transaction, fuse_ctrl_in_pkg_fuse_ctrl_in_if_agent_BFM, +fuse_ctrl_out_if_agent, fuse_ctrl_out_driver_bfm fuse_ctrl_out_monitor_bfm, fuse_ctrl_out_transaction, fuse_ctrl_out_pkg_fuse_ctrl_out_if_agent_BFM, + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/sim/hdl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/sim/hdl.compile new file mode 100644 index 0000000..8e7bd41 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/sim/hdl.compile @@ -0,0 +1,5 @@ +needs: +# pragma uvmf custom dut_compile_info begin + - ../rtl/dut.compile +# pragma uvmf custom dut_compile_info end + - ../tb/testbench/hdl_top.compile diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/sim/hdl.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/sim/hdl.vinfo new file mode 100644 index 0000000..da27ec7 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/sim/hdl.vinfo @@ -0,0 +1 @@ +@use $UVMF_PROJECT_DIR/tb/testbench/hdl_top.vinfo diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/sim/hvl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/sim/hvl.compile new file mode 100644 index 0000000..ce95254 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/sim/hvl.compile @@ -0,0 +1,2 @@ +needs: + - ../tb/testbench/hvl_top.compile diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/sim/hvl.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/sim/hvl.vinfo new file mode 100644 index 0000000..d22eff3 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/sim/hvl.vinfo @@ -0,0 +1 @@ +@use $UVMF_PROJECT_DIR/tb/testbench/hvl_top.vinfo diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/sim/run.do b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/sim/run.do new file mode 100644 index 0000000..101ddc4 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/sim/run.do @@ -0,0 +1,21 @@ + + +quietly set svLibs "" +quietly set extra_vsim_args "" + +################################################################### +## Check for additional vsim arguments passed using env var $UVMF_EXTRA_VSIM_ARGS +################################################################### +if {[info exists ::env(UVMF_EXTRA_VSIM_ARGS)]} { + echo "Adding more args to vsim command" + quietly set extra_vsim_args $::env(UVMF_EXTRA_VSIM_ARGS) +} + +################################################################## +## Launch Questa : generate vsim command line and execute +################################################################## +# pragma uvmf custom dut_run_dofile_target begin +# UVMF_CHANGE_ME : Change the UVM_TESTNAME plusarg to run a different test +quietly set cmd [format "vsim -i -sv_seed random +UVM_TESTNAME=test_top +UVM_VERBOSITY=UVM_HIGH -permit_unmatched_virtual_intf +notimingchecks -suppress 8887 %s %s -uvmcontrol=all -msgmode both -classdebug -assertdebug +uvm_set_config_int=*,enable_transaction_viewing,1 -do { set NoQuitOnFinish 1; onbreak {resume}; run 0; do wave.do; set PrefSource(OpenOnBreak) 0; radix hex showbase; } optimized_debug_top_tb" $svLibs $extra_vsim_args] +# pragma uvmf custom dut_run_dofile_target end +eval $cmd diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/sim/tbx.config b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/sim/tbx.config new file mode 100644 index 0000000..eec5816 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/sim/tbx.config @@ -0,0 +1,10 @@ + + + + + +comp -questa +velsyn -D1S +rtlc -allow_4ST + + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/sim/testlist b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/sim/testlist new file mode 100644 index 0000000..0c62297 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/sim/testlist @@ -0,0 +1,20 @@ + + + + +# Test list for use by RMDB file +# File syntax is +# TB_INFO { } { } +# TB ## All subsequent tests will run on this bench until a different "TB" line is seen +# TEST <1st_seed> ... +# If not enough seeds are provided then random seeds are used to pad +# If no repeat count is given, default is 1 +# pragma uvmf custom tb_info begin +TB_INFO fuse_ctrl { UVMF_VIP_LIBRARY_HOME=../../../../../../../../verification_ip UVMF_PROJECT_DIR=../../../../../../../fuse_ctrl } { } +# pragma uvmf custom tb_info end +TB fuse_ctrl +# pragma uvmf custom regression_suite begin +TEST test_top 3 +# pragma uvmf custom regression_suite end + + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/sim/testlist.yaml b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/sim/testlist.yaml new file mode 100644 index 0000000..6236cc7 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/sim/testlist.yaml @@ -0,0 +1,44 @@ + + + +# YAML test list for use by RMDB file +# File syntax is +# uvmf_testlist: +# testbenches: +# - name: +# extra_build_options: +# extra_run_options: +# - name: +# ... +# - name: +# tests: +# - name: +# uvm_testname: (defaults to test_name) +# testbench: (defaults to last tb name seen) +# repeat: (defaults to 1) +# seeds: [,,...,] (defaults to all random) +# extra_test_options: +# - name: +# ... +# - name: +# include: +# - (relative path reference is to the including YAML file) +# - +# ... +# - + +uvmf_testlist: + testbenches: +# pragma uvmf custom tb_info begin + - name: fuse_ctrl + extra_build_options: "UVMF_VIP_LIBRARY_HOME=../../../../../../../../verification_ip UVMF_PROJECT_DIR=../../../../../../../fuse_ctrl" + extra_run_options: "" +# pragma uvmf custom tb_info end + tests: + - testbench: fuse_ctrl +# pragma uvmf custom regression_suite begin + - name: test_top + repeat: 3 +# pragma uvmf custom regression_suite end + + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/sim/top.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/sim/top.compile new file mode 100644 index 0000000..efd51c0 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/sim/top.compile @@ -0,0 +1,3 @@ +needs: + - hvl.compile + - hdl.compile diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/sim/veloce.config b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/sim/veloce.config new file mode 100644 index 0000000..d097515 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/sim/veloce.config @@ -0,0 +1,26 @@ + + + + + +# pragma uvmf custom additional begin +comp -num_boards 1 +comp -hvl questa +# Please choose the correct emulator type code for +# comp -platform command or else velcomp will fail +# Available types are: +# - Veloce2 Quattro: D2 +# - Veloce2 Maximus: D2M +# - Veloce Strato TiL, Ti, and Mi: Strato +# - Veloce Strato M and Strato T: StratoM +# - comp -platform +comp -platform Strato + +rtlc -enable_tbx_pragma_checks +rtlc -allow_4ST +rtlc -allow_MDR +rtlc -compile_display +rtlc -xwave_siglist xwaves.sigs +# pragma uvmf custom additional end + + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/sim/viswave.do b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/sim/viswave.do new file mode 100644 index 0000000..db43b44 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/sim/viswave.do @@ -0,0 +1,106 @@ + + +onerror resume +wave tags F0 +wave update off + +wave spacer -backgroundcolor Salmon { fuse_ctrl_rst_in_agent } +wave add uvm_test_top.environment.fuse_ctrl_rst_in_agent.fuse_ctrl_rst_in_agent_monitor.txn_stream -radix string -tag F0 +wave group fuse_ctrl_rst_in_agent_bus +wave add -group fuse_ctrl_rst_in_agent_bus hdl_top.fuse_ctrl_rst_in_agent_bus.* -radix hexadecimal -tag F0 +wave group fuse_ctrl_rst_in_agent_bus -collapse +wave insertion [expr [wave index insertpoint] +1] +wave spacer -backgroundcolor Salmon { fuse_ctrl_rst_out_agent } +wave add uvm_test_top.environment.fuse_ctrl_rst_out_agent.fuse_ctrl_rst_out_agent_monitor.txn_stream -radix string -tag F0 +wave group fuse_ctrl_rst_out_agent_bus +wave add -group fuse_ctrl_rst_out_agent_bus hdl_top.fuse_ctrl_rst_out_agent_bus.* -radix hexadecimal -tag F0 +wave group fuse_ctrl_rst_out_agent_bus -collapse +wave insertion [expr [wave index insertpoint] +1] +wave spacer -backgroundcolor Salmon { fuse_ctrl_core_axi_write_in_if_agent } +wave add uvm_test_top.environment.fuse_ctrl_core_axi_write_in_if_agent.fuse_ctrl_core_axi_write_in_if_agent_monitor.txn_stream -radix string -tag F0 +wave group fuse_ctrl_core_axi_write_in_if_agent_bus +wave add -group fuse_ctrl_core_axi_write_in_if_agent_bus hdl_top.fuse_ctrl_core_axi_write_in_if_agent_bus.* -radix hexadecimal -tag F0 +wave group fuse_ctrl_core_axi_write_in_if_agent_bus -collapse +wave insertion [expr [wave index insertpoint] +1] +wave spacer -backgroundcolor Salmon { fuse_ctrl_core_axi_write_out_if_agent } +wave add uvm_test_top.environment.fuse_ctrl_core_axi_write_out_if_agent.fuse_ctrl_core_axi_write_out_if_agent_monitor.txn_stream -radix string -tag F0 +wave group fuse_ctrl_core_axi_write_out_if_agent_bus +wave add -group fuse_ctrl_core_axi_write_out_if_agent_bus hdl_top.fuse_ctrl_core_axi_write_out_if_agent_bus.* -radix hexadecimal -tag F0 +wave group fuse_ctrl_core_axi_write_out_if_agent_bus -collapse +wave insertion [expr [wave index insertpoint] +1] +wave spacer -backgroundcolor Salmon { fuse_ctrl_prim_axi_write_in_if_agent } +wave add uvm_test_top.environment.fuse_ctrl_prim_axi_write_in_if_agent.fuse_ctrl_prim_axi_write_in_if_agent_monitor.txn_stream -radix string -tag F0 +wave group fuse_ctrl_prim_axi_write_in_if_agent_bus +wave add -group fuse_ctrl_prim_axi_write_in_if_agent_bus hdl_top.fuse_ctrl_prim_axi_write_in_if_agent_bus.* -radix hexadecimal -tag F0 +wave group fuse_ctrl_prim_axi_write_in_if_agent_bus -collapse +wave insertion [expr [wave index insertpoint] +1] +wave spacer -backgroundcolor Salmon { fuse_ctrl_prim_axi_write_out_if_agent } +wave add uvm_test_top.environment.fuse_ctrl_prim_axi_write_out_if_agent.fuse_ctrl_prim_axi_write_out_if_agent_monitor.txn_stream -radix string -tag F0 +wave group fuse_ctrl_prim_axi_write_out_if_agent_bus +wave add -group fuse_ctrl_prim_axi_write_out_if_agent_bus hdl_top.fuse_ctrl_prim_axi_write_out_if_agent_bus.* -radix hexadecimal -tag F0 +wave group fuse_ctrl_prim_axi_write_out_if_agent_bus -collapse +wave insertion [expr [wave index insertpoint] +1] +wave spacer -backgroundcolor Salmon { fuse_ctrl_core_axi_read_in_if_agent } +wave add uvm_test_top.environment.fuse_ctrl_core_axi_read_in_if_agent.fuse_ctrl_core_axi_read_in_if_agent_monitor.txn_stream -radix string -tag F0 +wave group fuse_ctrl_core_axi_read_in_if_agent_bus +wave add -group fuse_ctrl_core_axi_read_in_if_agent_bus hdl_top.fuse_ctrl_core_axi_read_in_if_agent_bus.* -radix hexadecimal -tag F0 +wave group fuse_ctrl_core_axi_read_in_if_agent_bus -collapse +wave insertion [expr [wave index insertpoint] +1] +wave spacer -backgroundcolor Salmon { fuse_ctrl_core_axi_read_out_if_agent } +wave add uvm_test_top.environment.fuse_ctrl_core_axi_read_out_if_agent.fuse_ctrl_core_axi_read_out_if_agent_monitor.txn_stream -radix string -tag F0 +wave group fuse_ctrl_core_axi_read_out_if_agent_bus +wave add -group fuse_ctrl_core_axi_read_out_if_agent_bus hdl_top.fuse_ctrl_core_axi_read_out_if_agent_bus.* -radix hexadecimal -tag F0 +wave group fuse_ctrl_core_axi_read_out_if_agent_bus -collapse +wave insertion [expr [wave index insertpoint] +1] +wave spacer -backgroundcolor Salmon { fuse_ctrl_prim_axi_read_in_if_agent } +wave add uvm_test_top.environment.fuse_ctrl_prim_axi_read_in_if_agent.fuse_ctrl_prim_axi_read_in_if_agent_monitor.txn_stream -radix string -tag F0 +wave group fuse_ctrl_prim_axi_read_in_if_agent_bus +wave add -group fuse_ctrl_prim_axi_read_in_if_agent_bus hdl_top.fuse_ctrl_prim_axi_read_in_if_agent_bus.* -radix hexadecimal -tag F0 +wave group fuse_ctrl_prim_axi_read_in_if_agent_bus -collapse +wave insertion [expr [wave index insertpoint] +1] +wave spacer -backgroundcolor Salmon { fuse_ctrl_prim_axi_read_out_if_agent } +wave add uvm_test_top.environment.fuse_ctrl_prim_axi_read_out_if_agent.fuse_ctrl_prim_axi_read_out_if_agent_monitor.txn_stream -radix string -tag F0 +wave group fuse_ctrl_prim_axi_read_out_if_agent_bus +wave add -group fuse_ctrl_prim_axi_read_out_if_agent_bus hdl_top.fuse_ctrl_prim_axi_read_out_if_agent_bus.* -radix hexadecimal -tag F0 +wave group fuse_ctrl_prim_axi_read_out_if_agent_bus -collapse +wave insertion [expr [wave index insertpoint] +1] +wave spacer -backgroundcolor Salmon { fuse_ctrl_secreg_axi_read_in_if_agent } +wave add uvm_test_top.environment.fuse_ctrl_secreg_axi_read_in_if_agent.fuse_ctrl_secreg_axi_read_in_if_agent_monitor.txn_stream -radix string -tag F0 +wave group fuse_ctrl_secreg_axi_read_in_if_agent_bus +wave add -group fuse_ctrl_secreg_axi_read_in_if_agent_bus hdl_top.fuse_ctrl_secreg_axi_read_in_if_agent_bus.* -radix hexadecimal -tag F0 +wave group fuse_ctrl_secreg_axi_read_in_if_agent_bus -collapse +wave insertion [expr [wave index insertpoint] +1] +wave spacer -backgroundcolor Salmon { fuse_ctrl_secreg_axi_read_out_if_agent } +wave add uvm_test_top.environment.fuse_ctrl_secreg_axi_read_out_if_agent.fuse_ctrl_secreg_axi_read_out_if_agent_monitor.txn_stream -radix string -tag F0 +wave group fuse_ctrl_secreg_axi_read_out_if_agent_bus +wave add -group fuse_ctrl_secreg_axi_read_out_if_agent_bus hdl_top.fuse_ctrl_secreg_axi_read_out_if_agent_bus.* -radix hexadecimal -tag F0 +wave group fuse_ctrl_secreg_axi_read_out_if_agent_bus -collapse +wave insertion [expr [wave index insertpoint] +1] +wave spacer -backgroundcolor Salmon { fuse_ctrl_lc_otp_in_if_agent } +wave add uvm_test_top.environment.fuse_ctrl_lc_otp_in_if_agent.fuse_ctrl_lc_otp_in_if_agent_monitor.txn_stream -radix string -tag F0 +wave group fuse_ctrl_lc_otp_in_if_agent_bus +wave add -group fuse_ctrl_lc_otp_in_if_agent_bus hdl_top.fuse_ctrl_lc_otp_in_if_agent_bus.* -radix hexadecimal -tag F0 +wave group fuse_ctrl_lc_otp_in_if_agent_bus -collapse +wave insertion [expr [wave index insertpoint] +1] +wave spacer -backgroundcolor Salmon { fuse_ctrl_lc_otp_out_if_agent } +wave add uvm_test_top.environment.fuse_ctrl_lc_otp_out_if_agent.fuse_ctrl_lc_otp_out_if_agent_monitor.txn_stream -radix string -tag F0 +wave group fuse_ctrl_lc_otp_out_if_agent_bus +wave add -group fuse_ctrl_lc_otp_out_if_agent_bus hdl_top.fuse_ctrl_lc_otp_out_if_agent_bus.* -radix hexadecimal -tag F0 +wave group fuse_ctrl_lc_otp_out_if_agent_bus -collapse +wave insertion [expr [wave index insertpoint] +1] +wave spacer -backgroundcolor Salmon { fuse_ctrl_in_if_agent } +wave add uvm_test_top.environment.fuse_ctrl_in_if_agent.fuse_ctrl_in_if_agent_monitor.txn_stream -radix string -tag F0 +wave group fuse_ctrl_in_if_agent_bus +wave add -group fuse_ctrl_in_if_agent_bus hdl_top.fuse_ctrl_in_if_agent_bus.* -radix hexadecimal -tag F0 +wave group fuse_ctrl_in_if_agent_bus -collapse +wave insertion [expr [wave index insertpoint] +1] +wave spacer -backgroundcolor Salmon { fuse_ctrl_out_if_agent } +wave add uvm_test_top.environment.fuse_ctrl_out_if_agent.fuse_ctrl_out_if_agent_monitor.txn_stream -radix string -tag F0 +wave group fuse_ctrl_out_if_agent_bus +wave add -group fuse_ctrl_out_if_agent_bus hdl_top.fuse_ctrl_out_if_agent_bus.* -radix hexadecimal -tag F0 +wave group fuse_ctrl_out_if_agent_bus -collapse +wave insertion [expr [wave index insertpoint] +1] + +wave update on +WaveSetStreamView + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/sim/wave.do b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/sim/wave.do new file mode 100644 index 0000000..1ec9959 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/sim/wave.do @@ -0,0 +1,72 @@ + + +onerror {resume} +quietly WaveActivateNextPane {} 0 + +add wave -noupdate -divider fuse_ctrl_rst_in_agent +add wave -noupdate /uvm_root/uvm_test_top/environment/fuse_ctrl_rst_in_agent/fuse_ctrl_rst_in_agent_monitor/txn_stream +add wave -noupdate -group fuse_ctrl_rst_in_agent_bus /hdl_top/fuse_ctrl_rst_in_agent_bus/* +add wave -noupdate -divider fuse_ctrl_rst_out_agent +add wave -noupdate /uvm_root/uvm_test_top/environment/fuse_ctrl_rst_out_agent/fuse_ctrl_rst_out_agent_monitor/txn_stream +add wave -noupdate -group fuse_ctrl_rst_out_agent_bus /hdl_top/fuse_ctrl_rst_out_agent_bus/* +add wave -noupdate -divider fuse_ctrl_core_axi_write_in_if_agent +add wave -noupdate /uvm_root/uvm_test_top/environment/fuse_ctrl_core_axi_write_in_if_agent/fuse_ctrl_core_axi_write_in_if_agent_monitor/txn_stream +add wave -noupdate -group fuse_ctrl_core_axi_write_in_if_agent_bus /hdl_top/fuse_ctrl_core_axi_write_in_if_agent_bus/* +add wave -noupdate -divider fuse_ctrl_core_axi_write_out_if_agent +add wave -noupdate /uvm_root/uvm_test_top/environment/fuse_ctrl_core_axi_write_out_if_agent/fuse_ctrl_core_axi_write_out_if_agent_monitor/txn_stream +add wave -noupdate -group fuse_ctrl_core_axi_write_out_if_agent_bus /hdl_top/fuse_ctrl_core_axi_write_out_if_agent_bus/* +add wave -noupdate -divider fuse_ctrl_prim_axi_write_in_if_agent +add wave -noupdate /uvm_root/uvm_test_top/environment/fuse_ctrl_prim_axi_write_in_if_agent/fuse_ctrl_prim_axi_write_in_if_agent_monitor/txn_stream +add wave -noupdate -group fuse_ctrl_prim_axi_write_in_if_agent_bus /hdl_top/fuse_ctrl_prim_axi_write_in_if_agent_bus/* +add wave -noupdate -divider fuse_ctrl_prim_axi_write_out_if_agent +add wave -noupdate /uvm_root/uvm_test_top/environment/fuse_ctrl_prim_axi_write_out_if_agent/fuse_ctrl_prim_axi_write_out_if_agent_monitor/txn_stream +add wave -noupdate -group fuse_ctrl_prim_axi_write_out_if_agent_bus /hdl_top/fuse_ctrl_prim_axi_write_out_if_agent_bus/* +add wave -noupdate -divider fuse_ctrl_core_axi_read_in_if_agent +add wave -noupdate /uvm_root/uvm_test_top/environment/fuse_ctrl_core_axi_read_in_if_agent/fuse_ctrl_core_axi_read_in_if_agent_monitor/txn_stream +add wave -noupdate -group fuse_ctrl_core_axi_read_in_if_agent_bus /hdl_top/fuse_ctrl_core_axi_read_in_if_agent_bus/* +add wave -noupdate -divider fuse_ctrl_core_axi_read_out_if_agent +add wave -noupdate /uvm_root/uvm_test_top/environment/fuse_ctrl_core_axi_read_out_if_agent/fuse_ctrl_core_axi_read_out_if_agent_monitor/txn_stream +add wave -noupdate -group fuse_ctrl_core_axi_read_out_if_agent_bus /hdl_top/fuse_ctrl_core_axi_read_out_if_agent_bus/* +add wave -noupdate -divider fuse_ctrl_prim_axi_read_in_if_agent +add wave -noupdate /uvm_root/uvm_test_top/environment/fuse_ctrl_prim_axi_read_in_if_agent/fuse_ctrl_prim_axi_read_in_if_agent_monitor/txn_stream +add wave -noupdate -group fuse_ctrl_prim_axi_read_in_if_agent_bus /hdl_top/fuse_ctrl_prim_axi_read_in_if_agent_bus/* +add wave -noupdate -divider fuse_ctrl_prim_axi_read_out_if_agent +add wave -noupdate /uvm_root/uvm_test_top/environment/fuse_ctrl_prim_axi_read_out_if_agent/fuse_ctrl_prim_axi_read_out_if_agent_monitor/txn_stream +add wave -noupdate -group fuse_ctrl_prim_axi_read_out_if_agent_bus /hdl_top/fuse_ctrl_prim_axi_read_out_if_agent_bus/* +add wave -noupdate -divider fuse_ctrl_secreg_axi_read_in_if_agent +add wave -noupdate /uvm_root/uvm_test_top/environment/fuse_ctrl_secreg_axi_read_in_if_agent/fuse_ctrl_secreg_axi_read_in_if_agent_monitor/txn_stream +add wave -noupdate -group fuse_ctrl_secreg_axi_read_in_if_agent_bus /hdl_top/fuse_ctrl_secreg_axi_read_in_if_agent_bus/* +add wave -noupdate -divider fuse_ctrl_secreg_axi_read_out_if_agent +add wave -noupdate /uvm_root/uvm_test_top/environment/fuse_ctrl_secreg_axi_read_out_if_agent/fuse_ctrl_secreg_axi_read_out_if_agent_monitor/txn_stream +add wave -noupdate -group fuse_ctrl_secreg_axi_read_out_if_agent_bus /hdl_top/fuse_ctrl_secreg_axi_read_out_if_agent_bus/* +add wave -noupdate -divider fuse_ctrl_lc_otp_in_if_agent +add wave -noupdate /uvm_root/uvm_test_top/environment/fuse_ctrl_lc_otp_in_if_agent/fuse_ctrl_lc_otp_in_if_agent_monitor/txn_stream +add wave -noupdate -group fuse_ctrl_lc_otp_in_if_agent_bus /hdl_top/fuse_ctrl_lc_otp_in_if_agent_bus/* +add wave -noupdate -divider fuse_ctrl_lc_otp_out_if_agent +add wave -noupdate /uvm_root/uvm_test_top/environment/fuse_ctrl_lc_otp_out_if_agent/fuse_ctrl_lc_otp_out_if_agent_monitor/txn_stream +add wave -noupdate -group fuse_ctrl_lc_otp_out_if_agent_bus /hdl_top/fuse_ctrl_lc_otp_out_if_agent_bus/* +add wave -noupdate -divider fuse_ctrl_in_if_agent +add wave -noupdate /uvm_root/uvm_test_top/environment/fuse_ctrl_in_if_agent/fuse_ctrl_in_if_agent_monitor/txn_stream +add wave -noupdate -group fuse_ctrl_in_if_agent_bus /hdl_top/fuse_ctrl_in_if_agent_bus/* +add wave -noupdate -divider fuse_ctrl_out_if_agent +add wave -noupdate /uvm_root/uvm_test_top/environment/fuse_ctrl_out_if_agent/fuse_ctrl_out_if_agent_monitor/txn_stream +add wave -noupdate -group fuse_ctrl_out_if_agent_bus /hdl_top/fuse_ctrl_out_if_agent_bus/* + +TreeUpdate [SetDefaultTree] +quietly wave cursor active 0 +configure wave -namecolwidth 472 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {27 ns} {168 ns} + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/sim/xwaves.sigs b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/sim/xwaves.sigs new file mode 100644 index 0000000..d75f0a5 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/sim/xwaves.sigs @@ -0,0 +1,17 @@ + + + + + +# pragma uvmf custom additional begin + +Group All + +#Top level signals +hdl_top.* +#Add additional levels or individual signals as needed +hdl_top.*.* + +# pragma uvmf custom additional end + + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/parameters/fuse_ctrl_parameters_pkg.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/parameters/fuse_ctrl_parameters_pkg.compile new file mode 100644 index 0000000..0c6b841 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/parameters/fuse_ctrl_parameters_pkg.compile @@ -0,0 +1,4 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +src: + - fuse_ctrl_parameters_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/parameters/fuse_ctrl_parameters_pkg.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/parameters/fuse_ctrl_parameters_pkg.sv new file mode 100644 index 0000000..df84a8b --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/parameters/fuse_ctrl_parameters_pkg.sv @@ -0,0 +1,66 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This package contains test level parameters +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + +package fuse_ctrl_parameters_pkg; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + + // These parameters are used to uniquely identify each interface. The monitor_bfm and + // driver_bfm are placed into and retrieved from the uvm_config_db using these string + // names as the field_name. The parameter is also used to enable transaction viewing + // from the command line for selected interfaces using the UVM command line processing. + parameter string fuse_ctrl_rst_in_agent_BFM = "fuse_ctrl_rst_in_agent_BFM"; /* [0] */ + parameter string fuse_ctrl_rst_out_agent_BFM = "fuse_ctrl_rst_out_agent_BFM"; /* [1] */ + parameter string fuse_ctrl_core_axi_write_in_if_agent_BFM = "fuse_ctrl_core_axi_write_in_if_agent_BFM"; /* [2] */ + parameter string fuse_ctrl_core_axi_write_out_if_agent_BFM = "fuse_ctrl_core_axi_write_out_if_agent_BFM"; /* [3] */ + parameter string fuse_ctrl_prim_axi_write_in_if_agent_BFM = "fuse_ctrl_prim_axi_write_in_if_agent_BFM"; /* [4] */ + parameter string fuse_ctrl_prim_axi_write_out_if_agent_BFM = "fuse_ctrl_prim_axi_write_out_if_agent_BFM"; /* [5] */ + parameter string fuse_ctrl_core_axi_read_in_if_agent_BFM = "fuse_ctrl_core_axi_read_in_if_agent_BFM"; /* [6] */ + parameter string fuse_ctrl_core_axi_read_out_if_agent_BFM = "fuse_ctrl_core_axi_read_out_if_agent_BFM"; /* [7] */ + parameter string fuse_ctrl_prim_axi_read_in_if_agent_BFM = "fuse_ctrl_prim_axi_read_in_if_agent_BFM"; /* [8] */ + parameter string fuse_ctrl_prim_axi_read_out_if_agent_BFM = "fuse_ctrl_prim_axi_read_out_if_agent_BFM"; /* [9] */ + parameter string fuse_ctrl_secreg_axi_read_in_if_agent_BFM = "fuse_ctrl_secreg_axi_read_in_if_agent_BFM"; /* [10] */ + parameter string fuse_ctrl_secreg_axi_read_out_if_agent_BFM = "fuse_ctrl_secreg_axi_read_out_if_agent_BFM"; /* [11] */ + parameter string fuse_ctrl_lc_otp_in_if_agent_BFM = "fuse_ctrl_lc_otp_in_if_agent_BFM"; /* [12] */ + parameter string fuse_ctrl_lc_otp_out_if_agent_BFM = "fuse_ctrl_lc_otp_out_if_agent_BFM"; /* [13] */ + parameter string fuse_ctrl_in_if_agent_BFM = "fuse_ctrl_in_if_agent_BFM"; /* [14] */ + parameter string fuse_ctrl_out_if_agent_BFM = "fuse_ctrl_out_if_agent_BFM"; /* [15] */ + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/parameters/fuse_ctrl_parameters_pkg.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/parameters/fuse_ctrl_parameters_pkg.vinfo new file mode 100644 index 0000000..3bd4d7f --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/parameters/fuse_ctrl_parameters_pkg.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +fuse_ctrl_parameters_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/sequences/fuse_ctrl_sequences_pkg.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/sequences/fuse_ctrl_sequences_pkg.compile new file mode 100644 index 0000000..85c9189 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/sequences/fuse_ctrl_sequences_pkg.compile @@ -0,0 +1,22 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out.compile + - ../../../../verification_ip/environment_packages/fuse_ctrl_env_pkg/fuse_ctrl_env_pkg.compile + - ../parameters/fuse_ctrl_parameters_pkg.compile +src: + - fuse_ctrl_sequences_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/sequences/fuse_ctrl_sequences_pkg.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/sequences/fuse_ctrl_sequences_pkg.sv new file mode 100644 index 0000000..3ebdc90 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/sequences/fuse_ctrl_sequences_pkg.sv @@ -0,0 +1,93 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This package includes all high level sequence classes used +// in the environment. These include utility sequences and top +// level sequences. +// +// CONTAINS: +// - +// - +// +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// + +package fuse_ctrl_sequences_pkg; + import uvm_pkg::*; + import uvmf_base_pkg::*; + import fuse_ctrl_rst_in_pkg::*; + import fuse_ctrl_rst_in_pkg_hdl::*; + import fuse_ctrl_rst_out_pkg::*; + import fuse_ctrl_rst_out_pkg_hdl::*; + import fuse_ctrl_core_axi_write_in_pkg::*; + import fuse_ctrl_core_axi_write_in_pkg_hdl::*; + import fuse_ctrl_core_axi_write_out_pkg::*; + import fuse_ctrl_core_axi_write_out_pkg_hdl::*; + import fuse_ctrl_prim_axi_write_in_pkg::*; + import fuse_ctrl_prim_axi_write_in_pkg_hdl::*; + import fuse_ctrl_prim_axi_write_out_pkg::*; + import fuse_ctrl_prim_axi_write_out_pkg_hdl::*; + import fuse_ctrl_core_axi_read_in_pkg::*; + import fuse_ctrl_core_axi_read_in_pkg_hdl::*; + import fuse_ctrl_core_axi_read_out_pkg::*; + import fuse_ctrl_core_axi_read_out_pkg_hdl::*; + import fuse_ctrl_prim_axi_read_in_pkg::*; + import fuse_ctrl_prim_axi_read_in_pkg_hdl::*; + import fuse_ctrl_prim_axi_read_out_pkg::*; + import fuse_ctrl_prim_axi_read_out_pkg_hdl::*; + import fuse_ctrl_secreg_axi_read_in_pkg::*; + import fuse_ctrl_secreg_axi_read_in_pkg_hdl::*; + import fuse_ctrl_secreg_axi_read_out_pkg::*; + import fuse_ctrl_secreg_axi_read_out_pkg_hdl::*; + import fuse_ctrl_lc_otp_in_pkg::*; + import fuse_ctrl_lc_otp_in_pkg_hdl::*; + import fuse_ctrl_lc_otp_out_pkg::*; + import fuse_ctrl_lc_otp_out_pkg_hdl::*; + import fuse_ctrl_in_pkg::*; + import fuse_ctrl_in_pkg_hdl::*; + import fuse_ctrl_out_pkg::*; + import fuse_ctrl_out_pkg_hdl::*; + import fuse_ctrl_parameters_pkg::*; + import fuse_ctrl_env_pkg::*; + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + `include "src/fuse_ctrl_bench_sequence_base.svh" + `include "src/register_test_sequence.svh" + `include "src/example_derived_test_sequence.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the sequence package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/sequences/fuse_ctrl_sequences_pkg.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/sequences/fuse_ctrl_sequences_pkg.vinfo new file mode 100644 index 0000000..150eb8c --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/sequences/fuse_ctrl_sequences_pkg.vinfo @@ -0,0 +1,21 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/environment_packages/fuse_ctrl_env_pkg/fuse_ctrl_env_pkg.vinfo +@use $UVMF_PROJECT_DIR/tb/parameters/fuse_ctrl_parameters_pkg.vinfo ++incdir+@vinfodir +fuse_ctrl_sequences_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/sequences/src/example_derived_test_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/sequences/src/example_derived_test_sequence.svh new file mode 100644 index 0000000..7566dc5 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/sequences/src/example_derived_test_sequence.svh @@ -0,0 +1,44 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains the top level sequence used in example_derived_test. +// It is an example of a sequence that is extended from %(benchName)_bench_sequence_base +// and can override %(benchName)_bench_sequence_base. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class example_derived_test_sequence extends fuse_ctrl_bench_sequence_base; + + `uvm_object_utils( example_derived_test_sequence ); + + function new(string name = "" ); + super.new(name); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/sequences/src/fuse_ctrl_bench_sequence_base.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/sequences/src/fuse_ctrl_bench_sequence_base.svh new file mode 100644 index 0000000..a12b377 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/sequences/src/fuse_ctrl_bench_sequence_base.svh @@ -0,0 +1,232 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// Description: This file contains the top level and utility sequences +// used by test_top. It can be extended to create derivative top +// level sequences. +// +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// + + +typedef fuse_ctrl_env_configuration fuse_ctrl_env_configuration_t; + +class fuse_ctrl_bench_sequence_base extends uvmf_sequence_base #(uvm_sequence_item); + + `uvm_object_utils( fuse_ctrl_bench_sequence_base ); + + // pragma uvmf custom sequences begin + +typedef fuse_ctrl_env_sequence_base #( + .CONFIG_T(fuse_ctrl_env_configuration_t) + ) + fuse_ctrl_env_sequence_base_t; +rand fuse_ctrl_env_sequence_base_t fuse_ctrl_env_seq; + + + + // UVMF_CHANGE_ME : Instantiate, construct, and start sequences as needed to create stimulus scenarios. + // Instantiate sequences here + typedef fuse_ctrl_rst_in_random_sequence fuse_ctrl_rst_in_agent_random_seq_t; + fuse_ctrl_rst_in_agent_random_seq_t fuse_ctrl_rst_in_agent_random_seq; + typedef fuse_ctrl_core_axi_write_in_random_sequence fuse_ctrl_core_axi_write_in_agent_random_seq_t; + fuse_ctrl_core_axi_write_in_agent_random_seq_t fuse_ctrl_core_axi_write_in_agent_random_seq; + typedef fuse_ctrl_prim_axi_write_in_random_sequence fuse_ctrl_prim_axi_write_in_agent_random_seq_t; + fuse_ctrl_prim_axi_write_in_agent_random_seq_t fuse_ctrl_prim_axi_write_in_agent_random_seq; + typedef fuse_ctrl_core_axi_read_in_random_sequence fuse_ctrl_core_axi_read_in_agent_random_seq_t; + fuse_ctrl_core_axi_read_in_agent_random_seq_t fuse_ctrl_core_axi_read_in_agent_random_seq; + typedef fuse_ctrl_prim_axi_read_in_random_sequence fuse_ctrl_prim_axi_read_in_agent_random_seq_t; + fuse_ctrl_prim_axi_read_in_agent_random_seq_t fuse_ctrl_prim_axi_read_in_agent_random_seq; + typedef fuse_ctrl_secreg_axi_read_in_random_sequence fuse_ctrl_secreg_axi_read_in_agent_random_seq_t; + fuse_ctrl_secreg_axi_read_in_agent_random_seq_t fuse_ctrl_secreg_axi_read_in_agent_random_seq; + typedef fuse_ctrl_lc_otp_in_random_sequence fuse_ctrl_lc_otp_in_agent_random_seq_t; + fuse_ctrl_lc_otp_in_agent_random_seq_t fuse_ctrl_lc_otp_in_agent_random_seq; + // pragma uvmf custom sequences end + + // Sequencer handles for each active interface in the environment + typedef fuse_ctrl_rst_in_transaction fuse_ctrl_rst_in_agent_transaction_t; + uvm_sequencer #(fuse_ctrl_rst_in_agent_transaction_t) fuse_ctrl_rst_in_agent_sequencer; + typedef fuse_ctrl_core_axi_write_in_transaction fuse_ctrl_core_axi_write_in_if_agent_transaction_t; + uvm_sequencer #(fuse_ctrl_core_axi_write_in_if_agent_transaction_t) fuse_ctrl_core_axi_write_in_if_agent_sequencer; + typedef fuse_ctrl_prim_axi_write_in_transaction fuse_ctrl_prim_axi_write_in_if_agent_transaction_t; + uvm_sequencer #(fuse_ctrl_prim_axi_write_in_if_agent_transaction_t) fuse_ctrl_prim_axi_write_in_if_agent_sequencer; + typedef fuse_ctrl_core_axi_read_in_transaction fuse_ctrl_core_axi_read_in_if_agent_transaction_t; + uvm_sequencer #(fuse_ctrl_core_axi_read_in_if_agent_transaction_t) fuse_ctrl_core_axi_read_in_if_agent_sequencer; + typedef fuse_ctrl_prim_axi_read_in_transaction fuse_ctrl_prim_axi_read_in_if_agent_transaction_t; + uvm_sequencer #(fuse_ctrl_prim_axi_read_in_if_agent_transaction_t) fuse_ctrl_prim_axi_read_in_if_agent_sequencer; + typedef fuse_ctrl_secreg_axi_read_in_transaction fuse_ctrl_secreg_axi_read_in_if_agent_transaction_t; + uvm_sequencer #(fuse_ctrl_secreg_axi_read_in_if_agent_transaction_t) fuse_ctrl_secreg_axi_read_in_if_agent_sequencer; + typedef fuse_ctrl_lc_otp_in_transaction fuse_ctrl_lc_otp_in_if_agent_transaction_t; + uvm_sequencer #(fuse_ctrl_lc_otp_in_if_agent_transaction_t) fuse_ctrl_lc_otp_in_if_agent_sequencer; + typedef fuse_ctrl_in_transaction fuse_ctrl_in_if_agent_transaction_t; + uvm_sequencer #(fuse_ctrl_in_if_agent_transaction_t) fuse_ctrl_in_if_agent_sequencer; + + + // Top level environment configuration handle + fuse_ctrl_env_configuration_t top_configuration; + + // Configuration handles to access interface BFM's + fuse_ctrl_rst_in_configuration fuse_ctrl_rst_in_agent_config; + fuse_ctrl_rst_out_configuration fuse_ctrl_rst_out_agent_config; + fuse_ctrl_core_axi_write_in_configuration fuse_ctrl_core_axi_write_in_if_agent_config; + fuse_ctrl_core_axi_write_out_configuration fuse_ctrl_core_axi_write_out_if_agent_config; + fuse_ctrl_prim_axi_write_in_configuration fuse_ctrl_prim_axi_write_in_if_agent_config; + fuse_ctrl_prim_axi_write_out_configuration fuse_ctrl_prim_axi_write_out_if_agent_config; + fuse_ctrl_core_axi_read_in_configuration fuse_ctrl_core_axi_read_in_if_agent_config; + fuse_ctrl_core_axi_read_out_configuration fuse_ctrl_core_axi_read_out_if_agent_config; + fuse_ctrl_prim_axi_read_in_configuration fuse_ctrl_prim_axi_read_in_if_agent_config; + fuse_ctrl_prim_axi_read_out_configuration fuse_ctrl_prim_axi_read_out_if_agent_config; + fuse_ctrl_secreg_axi_read_in_configuration fuse_ctrl_secreg_axi_read_in_if_agent_config; + fuse_ctrl_secreg_axi_read_out_configuration fuse_ctrl_secreg_axi_read_out_if_agent_config; + fuse_ctrl_lc_otp_in_configuration fuse_ctrl_lc_otp_in_if_agent_config; + fuse_ctrl_lc_otp_out_configuration fuse_ctrl_lc_otp_out_if_agent_config; + fuse_ctrl_in_configuration fuse_ctrl_in_if_agent_config; + fuse_ctrl_out_configuration fuse_ctrl_out_if_agent_config; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + function new( string name = "" ); + super.new( name ); + // Retrieve the configuration handles from the uvm_config_db + + // Retrieve top level configuration handle + if ( !uvm_config_db#(fuse_ctrl_env_configuration_t)::get(null,UVMF_CONFIGURATIONS, "TOP_ENV_CONFIG",top_configuration) ) begin + `uvm_info("CFG", "*** FATAL *** uvm_config_db::get can not find TOP_ENV_CONFIG. Are you using an older UVMF release than what was used to generate this bench?",UVM_NONE); + `uvm_fatal("CFG", "uvm_config_db#(fuse_ctrl_env_configuration_t)::get cannot find resource TOP_ENV_CONFIG"); + end + + // Retrieve config handles for all agents + if( !uvm_config_db #( fuse_ctrl_rst_in_configuration )::get( null , UVMF_CONFIGURATIONS , fuse_ctrl_rst_in_agent_BFM , fuse_ctrl_rst_in_agent_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( fuse_ctrl_rst_in_configuration )::get cannot find resource fuse_ctrl_rst_in_agent_BFM" ) + if( !uvm_config_db #( fuse_ctrl_rst_out_configuration )::get( null , UVMF_CONFIGURATIONS , fuse_ctrl_rst_out_agent_BFM , fuse_ctrl_rst_out_agent_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( fuse_ctrl_rst_out_configuration )::get cannot find resource fuse_ctrl_rst_out_agent_BFM" ) + if( !uvm_config_db #( fuse_ctrl_core_axi_write_in_configuration )::get( null , UVMF_CONFIGURATIONS , fuse_ctrl_core_axi_write_in_if_agent_BFM , fuse_ctrl_core_axi_write_in_if_agent_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( fuse_ctrl_core_axi_write_in_configuration )::get cannot find resource fuse_ctrl_core_axi_write_in_if_agent_BFM" ) + if( !uvm_config_db #( fuse_ctrl_core_axi_write_out_configuration )::get( null , UVMF_CONFIGURATIONS , fuse_ctrl_core_axi_write_out_if_agent_BFM , fuse_ctrl_core_axi_write_out_if_agent_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( fuse_ctrl_core_axi_write_out_configuration )::get cannot find resource fuse_ctrl_core_axi_write_out_if_agent_BFM" ) + if( !uvm_config_db #( fuse_ctrl_prim_axi_write_in_configuration )::get( null , UVMF_CONFIGURATIONS , fuse_ctrl_prim_axi_write_in_if_agent_BFM , fuse_ctrl_prim_axi_write_in_if_agent_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( fuse_ctrl_prim_axi_write_in_configuration )::get cannot find resource fuse_ctrl_prim_axi_write_in_if_agent_BFM" ) + if( !uvm_config_db #( fuse_ctrl_prim_axi_write_out_configuration )::get( null , UVMF_CONFIGURATIONS , fuse_ctrl_prim_axi_write_out_if_agent_BFM , fuse_ctrl_prim_axi_write_out_if_agent_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( fuse_ctrl_prim_axi_write_out_configuration )::get cannot find resource fuse_ctrl_prim_axi_write_out_if_agent_BFM" ) + if( !uvm_config_db #( fuse_ctrl_core_axi_read_in_configuration )::get( null , UVMF_CONFIGURATIONS , fuse_ctrl_core_axi_read_in_if_agent_BFM , fuse_ctrl_core_axi_read_in_if_agent_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( fuse_ctrl_core_axi_read_in_configuration )::get cannot find resource fuse_ctrl_core_axi_read_in_if_agent_BFM" ) + if( !uvm_config_db #( fuse_ctrl_core_axi_read_out_configuration )::get( null , UVMF_CONFIGURATIONS , fuse_ctrl_core_axi_read_out_if_agent_BFM , fuse_ctrl_core_axi_read_out_if_agent_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( fuse_ctrl_core_axi_read_out_configuration )::get cannot find resource fuse_ctrl_core_axi_read_out_if_agent_BFM" ) + if( !uvm_config_db #( fuse_ctrl_prim_axi_read_in_configuration )::get( null , UVMF_CONFIGURATIONS , fuse_ctrl_prim_axi_read_in_if_agent_BFM , fuse_ctrl_prim_axi_read_in_if_agent_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( fuse_ctrl_prim_axi_read_in_configuration )::get cannot find resource fuse_ctrl_prim_axi_read_in_if_agent_BFM" ) + if( !uvm_config_db #( fuse_ctrl_prim_axi_read_out_configuration )::get( null , UVMF_CONFIGURATIONS , fuse_ctrl_prim_axi_read_out_if_agent_BFM , fuse_ctrl_prim_axi_read_out_if_agent_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( fuse_ctrl_prim_axi_read_out_configuration )::get cannot find resource fuse_ctrl_prim_axi_read_out_if_agent_BFM" ) + if( !uvm_config_db #( fuse_ctrl_secreg_axi_read_in_configuration )::get( null , UVMF_CONFIGURATIONS , fuse_ctrl_secreg_axi_read_in_if_agent_BFM , fuse_ctrl_secreg_axi_read_in_if_agent_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( fuse_ctrl_secreg_axi_read_in_configuration )::get cannot find resource fuse_ctrl_secreg_axi_read_in_if_agent_BFM" ) + if( !uvm_config_db #( fuse_ctrl_secreg_axi_read_out_configuration )::get( null , UVMF_CONFIGURATIONS , fuse_ctrl_secreg_axi_read_out_if_agent_BFM , fuse_ctrl_secreg_axi_read_out_if_agent_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( fuse_ctrl_secreg_axi_read_out_configuration )::get cannot find resource fuse_ctrl_secreg_axi_read_out_if_agent_BFM" ) + if( !uvm_config_db #( fuse_ctrl_lc_otp_in_configuration )::get( null , UVMF_CONFIGURATIONS , fuse_ctrl_lc_otp_in_if_agent_BFM , fuse_ctrl_lc_otp_in_if_agent_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( fuse_ctrl_lc_otp_in_configuration )::get cannot find resource fuse_ctrl_lc_otp_in_if_agent_BFM" ) + if( !uvm_config_db #( fuse_ctrl_lc_otp_out_configuration )::get( null , UVMF_CONFIGURATIONS , fuse_ctrl_lc_otp_out_if_agent_BFM , fuse_ctrl_lc_otp_out_if_agent_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( fuse_ctrl_lc_otp_out_configuration )::get cannot find resource fuse_ctrl_lc_otp_out_if_agent_BFM" ) + if( !uvm_config_db #( fuse_ctrl_in_configuration )::get( null , UVMF_CONFIGURATIONS , fuse_ctrl_in_if_agent_BFM , fuse_ctrl_in_if_agent_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( fuse_ctrl_in_configuration )::get cannot find resource fuse_ctrl_in_if_agent_BFM" ) + if( !uvm_config_db #( fuse_ctrl_out_configuration )::get( null , UVMF_CONFIGURATIONS , fuse_ctrl_out_if_agent_BFM , fuse_ctrl_out_if_agent_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( fuse_ctrl_out_configuration )::get cannot find resource fuse_ctrl_out_if_agent_BFM" ) + + // Assign the sequencer handles from the handles within agent configurations + fuse_ctrl_rst_in_agent_sequencer = fuse_ctrl_rst_in_agent_config.get_sequencer(); + fuse_ctrl_core_axi_write_in_if_agent_sequencer = fuse_ctrl_core_axi_write_in_if_agent_config.get_sequencer(); + fuse_ctrl_prim_axi_write_in_if_agent_sequencer = fuse_ctrl_prim_axi_write_in_if_agent_config.get_sequencer(); + fuse_ctrl_core_axi_read_in_if_agent_sequencer = fuse_ctrl_core_axi_read_in_if_agent_config.get_sequencer(); + fuse_ctrl_prim_axi_read_in_if_agent_sequencer = fuse_ctrl_prim_axi_read_in_if_agent_config.get_sequencer(); + fuse_ctrl_secreg_axi_read_in_if_agent_sequencer = fuse_ctrl_secreg_axi_read_in_if_agent_config.get_sequencer(); + fuse_ctrl_lc_otp_in_if_agent_sequencer = fuse_ctrl_lc_otp_in_if_agent_config.get_sequencer(); + fuse_ctrl_in_if_agent_sequencer = fuse_ctrl_in_if_agent_config.get_sequencer(); + + + + // pragma uvmf custom new begin + // pragma uvmf custom new end + + endfunction + + // **************************************************************************** + virtual task body(); + // pragma uvmf custom body begin + + // Construct sequences here + + fuse_ctrl_env_seq = fuse_ctrl_env_sequence_base_t::type_id::create("fuse_ctrl_env_seq"); + + fuse_ctrl_rst_in_agent_random_seq = fuse_ctrl_rst_in_agent_random_seq_t::type_id::create("fuse_ctrl_rst_in_agent_random_seq"); + fuse_ctrl_core_axi_write_in_agent_random_seq = fuse_ctrl_core_axi_write_in_agent_random_seq_t::type_id::create("fuse_ctrl_core_axi_write_in_agent_random_seq"); + fuse_ctrl_prim_axi_write_in_agent_random_seq = fuse_ctrl_prim_axi_write_in_agent_random_seq_t::type_id::create("fuse_ctrl_prim_axi_write_in_agent_random_seq"); + fuse_ctrl_core_axi_read_in_agent_random_seq = fuse_ctrl_core_axi_read_in_agent_random_seq_t::type_id::create("fuse_ctrl_core_axi_read_in_agent_random_seq"); + fuse_ctrl_prim_axi_read_in_agent_random_seq = fuse_ctrl_prim_axi_read_in_agent_random_seq_t::type_id::create("fuse_ctrl_prim_axi_read_in_agent_random_seq"); + fuse_ctrl_secreg_axi_read_in_agent_random_seq = fuse_ctrl_secreg_axi_read_in_agent_random_seq_t::type_id::create("fuse_ctrl_secreg_axi_read_in_agent_random_seq"); + fuse_ctrl_lc_otp_in_agent_random_seq = fuse_ctrl_lc_otp_in_agent_random_seq_t::type_id::create("fuse_ctrl_lc_otp_in_agent_random_seq"); + fork + fuse_ctrl_rst_in_agent_config.wait_for_reset(); + fuse_ctrl_core_axi_write_in_agent_config.wait_for_reset(); + fuse_ctrl_prim_axi_write_in_agent_config.wait_for_reset(); + fuse_ctrl_core_axi_read_in_agent_config.wait_for_reset(); + fuse_ctrl_prim_axi_read_in_agent_config.wait_for_reset(); + fuse_ctrl_secreg_axi_read_in_agent_config.wait_for_reset(); + fuse_ctrl_lc_otp_in_agent_config.wait_for_reset(); + join + // Start RESPONDER sequences here + fork + join_none + // Start INITIATOR sequences here + fork + repeat (25) fuse_ctrl_rst_in_agent_random_seq.start(fuse_ctrl_rst_in_agent_sequencer); + repeat (25) fuse_ctrl_core_axi_write_in_agent_random_seq.start(fuse_ctrl_core_axi_write_in_agent_sequencer); + repeat (25) fuse_ctrl_prim_axi_write_in_agent_random_seq.start(fuse_ctrl_prim_axi_write_in_agent_sequencer); + repeat (25) fuse_ctrl_core_axi_read_in_agent_random_seq.start(fuse_ctrl_core_axi_read_in_agent_sequencer); + repeat (25) fuse_ctrl_prim_axi_read_in_agent_random_seq.start(fuse_ctrl_prim_axi_read_in_agent_sequencer); + repeat (25) fuse_ctrl_secreg_axi_read_in_agent_random_seq.start(fuse_ctrl_secreg_axi_read_in_agent_sequencer); + repeat (25) fuse_ctrl_lc_otp_in_agent_random_seq.start(fuse_ctrl_lc_otp_in_agent_sequencer); + join + +fuse_ctrl_env_seq.start(top_configuration.vsqr); + + // UVMF_CHANGE_ME : Extend the simulation XXX number of clocks after + // the last sequence to allow for the last sequence item to flow + // through the design. + fork + fuse_ctrl_rst_in_agent_config.wait_for_num_clocks(400); + fuse_ctrl_core_axi_write_in_agent_config.wait_for_num_clocks(400); + fuse_ctrl_prim_axi_write_in_agent_config.wait_for_num_clocks(400); + fuse_ctrl_core_axi_read_in_agent_config.wait_for_num_clocks(400); + fuse_ctrl_prim_axi_read_in_agent_config.wait_for_num_clocks(400); + fuse_ctrl_secreg_axi_read_in_agent_config.wait_for_num_clocks(400); + fuse_ctrl_lc_otp_in_agent_config.wait_for_num_clocks(400); + join + + // pragma uvmf custom body end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/sequences/src/register_test_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/sequences/src/register_test_sequence.svh new file mode 100644 index 0000000..0db60c3 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/sequences/src/register_test_sequence.svh @@ -0,0 +1,76 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains the top level sequence used in register_test. +// It uses the UVM built in register test. Specific UVM built-in tests can be +// selected in the body task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class register_test_sequence extends fuse_ctrl_bench_sequence_base; + + `uvm_object_utils( register_test_sequence ); + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "" ); + super.new(name); + endfunction + + // **************************************************************************** + virtual task body(); + + // Reset the DUT + fork + // pragma uvmf custom register_test_reset begin + // UVMF_CHANGE_ME + // Select the desired wait_for_reset or provide custom mechanism. + // fork-join for this code block may be unnecessary based on your situation. + fuse_ctrl_rst_agent_config.wait_for_reset(); + fuse_ctrl_core_axi_write_agent_config.wait_for_reset(); + fuse_ctrl_prim_axi_write_agent_config.wait_for_reset(); + fuse_ctrl_core_axi_read_agent_config.wait_for_reset(); + fuse_ctrl_prim_axi_read_agent_config.wait_for_reset(); + fuse_ctrl_secreg_axi_read_agent_config.wait_for_reset(); + fuse_ctrl_lc_otp_if_agent_config.wait_for_reset(); + // pragma uvmf custom register_test_reset end + join + + // pragma uvmf custom register_test_setup begin + // UVMF_CHANGE_ME perform potentially necessary operations before running the sequence. + // pragma uvmf custom register_test_setup end + + // pragma uvmf custom register_test_operation begin + // UVMF_CHANGE_ME Perform your custom register test + // pragma uvmf custom register_test_operation end + + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/testbench/hdl_top.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/testbench/hdl_top.compile new file mode 100644 index 0000000..651edf5 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/testbench/hdl_top.compile @@ -0,0 +1,24 @@ +incdir: + - ${uvm_path}/src + - . +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ../parameters/fuse_ctrl_parameters_pkg.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_hdl.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_hdl.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_hdl.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_hdl.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_hdl.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_hdl.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_hdl.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_hdl.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_hdl.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_hdl.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_hdl.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_hdl.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_hdl.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_hdl.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_hdl.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_hdl.compile +src: + - hdl_top.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/testbench/hdl_top.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/testbench/hdl_top.sv new file mode 100644 index 0000000..1be4308 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/testbench/hdl_top.sv @@ -0,0 +1,415 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// Description: This top level module instantiates all synthesizable +// static content. This and tb_top.sv are the two top level modules +// of the simulation. +// +// This module instantiates the following: +// DUT: The Design Under Test +// Interfaces: Signal bundles that contain signals connected to DUT +// Driver BFM's: BFM's that actively drive interface signals +// Monitor BFM's: BFM's that passively monitor interface signals +// +//---------------------------------------------------------------------- + +//---------------------------------------------------------------------- +// + +module hdl_top; + +import fuse_ctrl_parameters_pkg::*; +import uvmf_base_pkg_hdl::*; +import axi_pkg::*; + + // pragma attribute hdl_top partition_module_xrtl +// pragma uvmf custom clock_generator begin + bit clk; + // Instantiate a clk driver + // tbx clkgen + initial begin + clk = 0; + #0ns; + forever begin + clk = ~clk; + #5ns; + end + end +// pragma uvmf custom clock_generator end + +// pragma uvmf custom reset_generator begin + bit rst; + // Instantiate a rst driver + // tbx clkgen + initial begin + rst = 0; + #200ns; + rst = 1; + end +// pragma uvmf custom reset_generator end + + // pragma uvmf custom module_item_additional begin + logic edn_clk; + logic edn_rst_n; + + localparam MemInitFile = "/home/ws/caliptra/anjpar/ws1/chipsalliance/caliptra-rtl/src/fuse_ctrl/data/otp-img.2048.vmem"; + // pragma uvmf custom module_item_additional end + + // Instantiate the signal bundle, monitor bfm and driver bfm for each interface. + // The signal bundle, _if, contains signals to be connected to the DUT. + // The monitor, monitor_bfm, observes the bus, _if, and captures transactions. + // The driver, driver_bfm, drives transactions onto the bus, _if. + fuse_ctrl_rst_in_if fuse_ctrl_rst_in_agent_bus( + // pragma uvmf custom fuse_ctrl_rst_in_agent_bus_connections begin + .clk_i(clk), .rst_ni(rst) + // pragma uvmf custom fuse_ctrl_rst_in_agent_bus_connections end + ); + fuse_ctrl_rst_out_if fuse_ctrl_rst_out_agent_bus( + // pragma uvmf custom fuse_ctrl_rst_out_agent_bus_connections begin + .clk_i(clk), .rst_ni(rst) + // pragma uvmf custom fuse_ctrl_rst_out_agent_bus_connections end + ); + fuse_ctrl_core_axi_write_in_if fuse_ctrl_core_axi_write_in_if_agent_bus( + // pragma uvmf custom fuse_ctrl_core_axi_write_in_if_agent_bus_connections begin + .clk_i(clk), .rst_ni(rst) + // pragma uvmf custom fuse_ctrl_core_axi_write_in_if_agent_bus_connections end + ); + fuse_ctrl_core_axi_write_out_if fuse_ctrl_core_axi_write_out_if_agent_bus( + // pragma uvmf custom fuse_ctrl_core_axi_write_out_if_agent_bus_connections begin + .clk_i(clk), .rst_ni(rst) + // pragma uvmf custom fuse_ctrl_core_axi_write_out_if_agent_bus_connections end + ); + fuse_ctrl_prim_axi_write_in_if fuse_ctrl_prim_axi_write_in_if_agent_bus( + // pragma uvmf custom fuse_ctrl_prim_axi_write_in_if_agent_bus_connections begin + .clk_i(clk), .rst_ni(rst) + // pragma uvmf custom fuse_ctrl_prim_axi_write_in_if_agent_bus_connections end + ); + fuse_ctrl_prim_axi_write_out_if fuse_ctrl_prim_axi_write_out_if_agent_bus( + // pragma uvmf custom fuse_ctrl_prim_axi_write_out_if_agent_bus_connections begin + .clk_i(clk), .rst_ni(rst) + // pragma uvmf custom fuse_ctrl_prim_axi_write_out_if_agent_bus_connections end + ); + fuse_ctrl_core_axi_read_in_if fuse_ctrl_core_axi_read_in_if_agent_bus( + // pragma uvmf custom fuse_ctrl_core_axi_read_in_if_agent_bus_connections begin + .clk_i(clk), .rst_ni(rst) + // pragma uvmf custom fuse_ctrl_core_axi_read_in_if_agent_bus_connections end + ); + fuse_ctrl_core_axi_read_out_if fuse_ctrl_core_axi_read_out_if_agent_bus( + // pragma uvmf custom fuse_ctrl_core_axi_read_out_if_agent_bus_connections begin + .clk_i(clk), .rst_ni(rst) + // pragma uvmf custom fuse_ctrl_core_axi_read_out_if_agent_bus_connections end + ); + fuse_ctrl_prim_axi_read_in_if fuse_ctrl_prim_axi_read_in_if_agent_bus( + // pragma uvmf custom fuse_ctrl_prim_axi_read_in_if_agent_bus_connections begin + .clk_i(clk), .rst_ni(rst) + // pragma uvmf custom fuse_ctrl_prim_axi_read_in_if_agent_bus_connections end + ); + fuse_ctrl_prim_axi_read_out_if fuse_ctrl_prim_axi_read_out_if_agent_bus( + // pragma uvmf custom fuse_ctrl_prim_axi_read_out_if_agent_bus_connections begin + .clk_i(clk), .rst_ni(rst) + // pragma uvmf custom fuse_ctrl_prim_axi_read_out_if_agent_bus_connections end + ); + fuse_ctrl_secreg_axi_read_in_if fuse_ctrl_secreg_axi_read_in_if_agent_bus( + // pragma uvmf custom fuse_ctrl_secreg_axi_read_in_if_agent_bus_connections begin + .clk_i(clk), .rst_ni(rst) + // pragma uvmf custom fuse_ctrl_secreg_axi_read_in_if_agent_bus_connections end + ); + fuse_ctrl_secreg_axi_read_out_if fuse_ctrl_secreg_axi_read_out_if_agent_bus( + // pragma uvmf custom fuse_ctrl_secreg_axi_read_out_if_agent_bus_connections begin + .clk_i(clk), .rst_ni(rst) + // pragma uvmf custom fuse_ctrl_secreg_axi_read_out_if_agent_bus_connections end + ); + fuse_ctrl_lc_otp_in_if fuse_ctrl_lc_otp_in_if_agent_bus( + // pragma uvmf custom fuse_ctrl_lc_otp_in_if_agent_bus_connections begin + .clk_i(clk), .rst_ni(rst) + // pragma uvmf custom fuse_ctrl_lc_otp_in_if_agent_bus_connections end + ); + fuse_ctrl_lc_otp_out_if fuse_ctrl_lc_otp_out_if_agent_bus( + // pragma uvmf custom fuse_ctrl_lc_otp_out_if_agent_bus_connections begin + .clk_i(clk), .rst_ni(rst) + // pragma uvmf custom fuse_ctrl_lc_otp_out_if_agent_bus_connections end + ); + fuse_ctrl_in_if fuse_ctrl_in_if_agent_bus( + // pragma uvmf custom fuse_ctrl_in_if_agent_bus_connections begin + .clk_i(clk), .rst_ni(rst) + // pragma uvmf custom fuse_ctrl_in_if_agent_bus_connections end + ); + fuse_ctrl_out_if fuse_ctrl_out_if_agent_bus( + // pragma uvmf custom fuse_ctrl_out_if_agent_bus_connections begin + .clk_i(clk), .rst_ni(rst) + // pragma uvmf custom fuse_ctrl_out_if_agent_bus_connections end + ); + fuse_ctrl_rst_in_monitor_bfm fuse_ctrl_rst_in_agent_mon_bfm(fuse_ctrl_rst_in_agent_bus.monitor_port); + fuse_ctrl_rst_out_monitor_bfm fuse_ctrl_rst_out_agent_mon_bfm(fuse_ctrl_rst_out_agent_bus.monitor_port); + fuse_ctrl_core_axi_write_in_monitor_bfm fuse_ctrl_core_axi_write_in_if_agent_mon_bfm(fuse_ctrl_core_axi_write_in_if_agent_bus.monitor_port); + fuse_ctrl_core_axi_write_out_monitor_bfm fuse_ctrl_core_axi_write_out_if_agent_mon_bfm(fuse_ctrl_core_axi_write_out_if_agent_bus.monitor_port); + fuse_ctrl_prim_axi_write_in_monitor_bfm fuse_ctrl_prim_axi_write_in_if_agent_mon_bfm(fuse_ctrl_prim_axi_write_in_if_agent_bus.monitor_port); + fuse_ctrl_prim_axi_write_out_monitor_bfm fuse_ctrl_prim_axi_write_out_if_agent_mon_bfm(fuse_ctrl_prim_axi_write_out_if_agent_bus.monitor_port); + fuse_ctrl_core_axi_read_in_monitor_bfm fuse_ctrl_core_axi_read_in_if_agent_mon_bfm(fuse_ctrl_core_axi_read_in_if_agent_bus.monitor_port); + fuse_ctrl_core_axi_read_out_monitor_bfm fuse_ctrl_core_axi_read_out_if_agent_mon_bfm(fuse_ctrl_core_axi_read_out_if_agent_bus.monitor_port); + fuse_ctrl_prim_axi_read_in_monitor_bfm fuse_ctrl_prim_axi_read_in_if_agent_mon_bfm(fuse_ctrl_prim_axi_read_in_if_agent_bus.monitor_port); + fuse_ctrl_prim_axi_read_out_monitor_bfm fuse_ctrl_prim_axi_read_out_if_agent_mon_bfm(fuse_ctrl_prim_axi_read_out_if_agent_bus.monitor_port); + fuse_ctrl_secreg_axi_read_in_monitor_bfm fuse_ctrl_secreg_axi_read_in_if_agent_mon_bfm(fuse_ctrl_secreg_axi_read_in_if_agent_bus.monitor_port); + fuse_ctrl_secreg_axi_read_out_monitor_bfm fuse_ctrl_secreg_axi_read_out_if_agent_mon_bfm(fuse_ctrl_secreg_axi_read_out_if_agent_bus.monitor_port); + fuse_ctrl_lc_otp_in_monitor_bfm fuse_ctrl_lc_otp_in_if_agent_mon_bfm(fuse_ctrl_lc_otp_in_if_agent_bus.monitor_port); + fuse_ctrl_lc_otp_out_monitor_bfm fuse_ctrl_lc_otp_out_if_agent_mon_bfm(fuse_ctrl_lc_otp_out_if_agent_bus.monitor_port); + fuse_ctrl_in_monitor_bfm fuse_ctrl_in_if_agent_mon_bfm(fuse_ctrl_in_if_agent_bus.monitor_port); + fuse_ctrl_out_monitor_bfm fuse_ctrl_out_if_agent_mon_bfm(fuse_ctrl_out_if_agent_bus.monitor_port); + fuse_ctrl_rst_in_driver_bfm fuse_ctrl_rst_in_agent_drv_bfm(fuse_ctrl_rst_in_agent_bus.initiator_port); + fuse_ctrl_core_axi_write_in_driver_bfm fuse_ctrl_core_axi_write_in_if_agent_drv_bfm(fuse_ctrl_core_axi_write_in_if_agent_bus.initiator_port); + fuse_ctrl_prim_axi_write_in_driver_bfm fuse_ctrl_prim_axi_write_in_if_agent_drv_bfm(fuse_ctrl_prim_axi_write_in_if_agent_bus.initiator_port); + fuse_ctrl_core_axi_read_in_driver_bfm fuse_ctrl_core_axi_read_in_if_agent_drv_bfm(fuse_ctrl_core_axi_read_in_if_agent_bus.initiator_port); + fuse_ctrl_prim_axi_read_in_driver_bfm fuse_ctrl_prim_axi_read_in_if_agent_drv_bfm(fuse_ctrl_prim_axi_read_in_if_agent_bus.initiator_port); + fuse_ctrl_secreg_axi_read_in_driver_bfm fuse_ctrl_secreg_axi_read_in_if_agent_drv_bfm(fuse_ctrl_secreg_axi_read_in_if_agent_bus.initiator_port); + fuse_ctrl_lc_otp_in_driver_bfm fuse_ctrl_lc_otp_in_if_agent_drv_bfm(fuse_ctrl_lc_otp_in_if_agent_bus.initiator_port); + fuse_ctrl_in_driver_bfm fuse_ctrl_in_if_agent_drv_bfm(fuse_ctrl_in_if_agent_bus.initiator_port); + + // pragma uvmf custom dut_instantiation begin + // UVMF_CHANGE_ME : Add DUT and connect to signals in _bus interfaces listed above + // Instantiate your DUT here + // These DUT's instantiated to show verilog and vhdl instantiation + //verilog_dut dut_verilog( .clk(clk), .rst(rst), .in_signal(vhdl_to_verilog_signal), .out_signal(verilog_to_vhdl_signal)); + //vhdl_dut dut_vhdl ( .clk(clk), .rst(rst), .in_signal(verilog_to_vhdl_signal), .out_signal(vhdl_to_verilog_signal)); + + otp_ctrl_top #( + .MemInitFile (MemInitFile) + ) dut ( + .clk_i (fuse_ctrl_rst_in_agent_bus.clk_i ), + .rst_ni (fuse_ctrl_rst_in_agent_bus.rst_ni ), + // edn + .clk_edn_i (edn_clk ), + .rst_edn_ni (edn_rst_n ), + .edn_o (fuse_ctrl_out_if_agent_bus.edn_o), //(edn_if[0].req ), + .edn_i (fuse_ctrl_in_if_agent_bus.edn_i), //({edn_if[0].ack, edn_if[0].d_data}), + // AXI interface + .s_core_axi_r_if (axi_core_if.r_sub), + .s_core_axi_w_if (axi_core_if.w_sub), + .s_prim_axi_r_if (axi_prim_if.r_sub), + .s_prim_axi_w_if (axi_prim_if.w_sub), + .s_secreg_axi_r_if (axi_secreg_if.r_sub), + // interrupt + .intr_otp_operation_done_o (fuse_ctrl_out_if_agent_bus.intr_otp_operation_done_o), + .intr_otp_error_o (fuse_ctrl_out_if_agent_bus.intr_otp_error_o), + // alert + .alert_rx_i (fuse_ctrl_in_if_agent_bus.alert_rx_i ), //(alert_rx parameter logic [CoreAw-1:0] CALIPTRA_OTP_CTRL_ALERT_TEST_OFFSET = 13'h c; + .alert_tx_o (fuse_ctrl_out_if_agent_bus.alert_tx_o ), //(alert_tx ), + // ast + .obs_ctrl_i (fuse_ctrl_in_if_agent_bus.obs_ctrl_i), //(otp_ctrl_if.obs_ctrl_i), + .otp_obs_o (fuse_ctrl_out_if_agent_bus.otp_obs_o), + .otp_ast_pwr_seq_o (fuse_ctrl_out_if_agent_bus.otp_ast_pwr_seq_o), //(ast_req), + .otp_ast_pwr_seq_h_i (fuse_ctrl_in_if_agent_bus.otp_ast_pwr_seq_h_i), //(otp_ctrl_if.otp_ast_pwr_seq_h_i), + // pwrmgr + .pwr_otp_i (fuse_ctrl_rst_in_agent_bus.pwr_otp_i), //(otp_ctrl_if.pwr_otp_init_i), + .pwr_otp_o (fuse_ctrl_rst_out_agent_bus.pwr_otp_o), //({otp_ctrl_if.pwr_otp_done_o, otp_ctrl_if.pwr_otp_idle_o}), + // lc + .lc_otp_vendor_test_i (fuse_ctrl_lc_otp_in_if_agent_bus.lc_otp_vendor_test_i), //(otp_ctrl_if.otp_vendor_test_ctrl_i), + .lc_otp_vendor_test_o (fuse_ctrl_lc_otp_out_if_agent_bus.lc_otp_vendor_test_o), //(otp_ctrl_if.otp_vendor_test_status_o), + .lc_otp_program_i (fuse_ctrl_lc_otp_in_if_agent_bus.lc_otp_program_i), //({lc_prog_if.req, lc_prog_if.h_data}), + .lc_otp_program_o (fuse_ctrl_lc_otp_out_if_agent_bus.lc_otp_program_o), //({lc_prog_if.d_data, lc_prog_if.ack}), + //.lc_creator_seed_sw_rw_en_i (lc_creator_seed_sw_rw_en_i), //(otp_ctrl_if.lc_creator_seed_sw_rw_en_i), + //.lc_owner_seed_sw_rw_en_i (lc_owner_seed_sw_rw_en_i), //(otp_ctrl_if.lc_owner_seed_sw_rw_en_i), + //.lc_seed_hw_rd_en_i (lc_seed_hw_rd_en_i), //(otp_ctrl_if.lc_seed_hw_rd_en_i), + .lc_dft_en_i (fuse_ctrl_lc_otp_in_if_agent_bus.lc_dft_en_i), //(otp_ctrl_if.lc_dft_en_i), + .lc_escalate_en_i (fuse_ctrl_lc_otp_in_if_agent_bus.lc_escalate_en_i), //(otp_ctrl_if.lc_escalate_en_i), + .lc_check_byp_en_i (fuse_ctrl_lc_otp_in_if_agent_bus.lc_check_byp_en_i), //(otp_ctrl_if.lc_check_byp_en_i), + .otp_lc_data_o (fuse_ctrl_lc_otp_out_if_agent_bus.otp_lc_data_o), //(otp_ctrl_if.lc_data_o), + + + .otp_broadcast_o (fuse_ctrl_out_if_agent_bus.otp_broadcast_o), //(otp_ctrl_if.otp_broadcast_o), + .otp_ext_voltage_h_io (fuse_ctrl_rst_in_agent_bus.otp_ext_voltage_h_io), + //scan + .scan_en_i (fuse_ctrl_in_if_agent_bus.scan_en_i), //(otp_ctrl_if.scan_en_i), + .scan_rst_ni (fuse_ctrl_in_if_agent_bus.scan_rst_ni), //(otp_ctrl_if.scan_rst_ni), + .scanmode_i (fuse_ctrl_in_if_agent_bus.scanmode_i), //(otp_ctrl_if.scanmode_i), + + // Test-related GPIO output + .cio_test_o (fuse_ctrl_out_if_agent_bus.cio_test_o), //(otp_ctrl_if.cio_test_o), + .cio_test_en_o (fuse_ctrl_out_if_agent_bus.cio_test_en_o) //(otp_ctrl_if.cio_test_en_o) + ); + + // AXI Core Interface + axi_if #( + .AW (AXI_AW), + .DW (AXI_DW), + .IW (AXI_IW), + .UW (AXI_UW) + ) axi_core_if ( + .clk (fuse_ctrl_rst_in_agent_bus.clk_i ), + .rst_n (fuse_ctrl_rst_in_agent_bus.rst_ni ) + ); + + // AXI Prim Interface + axi_if #( + .AW (AXI_AW), + .DW (AXI_DW), + .IW (AXI_IW), + .UW (AXI_UW) + ) axi_prim_if ( + .clk (fuse_ctrl_rst_in_agent_bus.clk_i ), + .rst_n (fuse_ctrl_rst_in_agent_bus.rst_ni) + ); + + // AXI Secret Reg Interface + axi_if #( + .AW (AXI_AW), + .DW (AXI_DW), + .IW (AXI_IW), + .UW (AXI_UW) + ) axi_secreg_if ( + .clk (fuse_ctrl_rst_in_agent_bus.clk_i ), + .rst_n (fuse_ctrl_rst_in_agent_bus.rst_ni) + ); + + /* + // Core AXI IF + assign fuse_ctrl_core_axi_write_in_if_agent_bus.awaddr = axi_core_if.w_sub.awaddr; + assign fuse_ctrl_core_axi_write_in_if_agent_bus.awburst = axi_core_if.w_sub.awburst; + assign fuse_ctrl_core_axi_write_in_if_agent_bus.awsize = axi_core_if.w_sub.awsize; + assign fuse_ctrl_core_axi_write_in_if_agent_bus.awlen = axi_core_if.w_sub.awlen; + assign fuse_ctrl_core_axi_write_in_if_agent_bus.awuser = axi_core_if.w_sub.awuser; + assign fuse_ctrl_core_axi_write_in_if_agent_bus.awid = axi_core_if.w_sub.awid; + assign fuse_ctrl_core_axi_write_in_if_agent_bus.awlock = axi_core_if.w_sub.awlock; + assign fuse_ctrl_core_axi_write_in_if_agent_bus.awvalid = axi_core_if.w_sub.awvalid; + assign fuse_ctrl_core_axi_write_in_if_agent_bus.wdata = axi_core_if.w_sub.wdata; + assign fuse_ctrl_core_axi_write_in_if_agent_bus.wstrb = axi_core_if.w_sub.wstrb; + assign fuse_ctrl_core_axi_write_in_if_agent_bus.wlast = axi_core_if.w_sub.wlast; + assign fuse_ctrl_core_axi_write_in_if_agent_bus.wvalid = axi_core_if.w_sub.wvalid; + assign fuse_ctrl_core_axi_write_in_if_agent_bus.bready = axi_core_if.w_sub.bready; + + assign fuse_ctrl_core_axi_write_out_if_agent_bus.awready = axi_core_if.w_sub.awready; + assign fuse_ctrl_core_axi_write_out_if_agent_bus.wready = axi_core_if.w_sub.wready; + assign fuse_ctrl_core_axi_write_out_if_agent_bus.bresp = axi_core_if.w_sub.bresp; + assign fuse_ctrl_core_axi_write_out_if_agent_bus.bvalid = axi_core_if.w_sub.bvalid; + assign fuse_ctrl_core_axi_write_out_if_agent_bus.bid = axi_core_if.w_sub.bid; + + assign fuse_ctrl_core_axi_read_in_if_agent_bus.araddr = axi_core_if.r_sub.araddr; + assign fuse_ctrl_core_axi_read_in_if_agent_bus.arburst = axi_core_if.r_sub.arburst; + assign fuse_ctrl_core_axi_read_in_if_agent_bus.arsize = axi_core_if.r_sub.arsize; + assign fuse_ctrl_core_axi_read_in_if_agent_bus.arlen = axi_core_if.r_sub.arlen; + assign fuse_ctrl_core_axi_read_in_if_agent_bus.aruser = axi_core_if.r_sub.aruser; + assign fuse_ctrl_core_axi_read_in_if_agent_bus.arid = axi_core_if.r_sub.arid; + assign fuse_ctrl_core_axi_read_in_if_agent_bus.arlock = axi_core_if.r_sub.arlock; + assign fuse_ctrl_core_axi_read_in_if_agent_bus.arvalid = axi_core_if.r_sub.arvalid; + assign fuse_ctrl_core_axi_read_in_if_agent_bus.rready = axi_core_if.r_sub.rready; + + assign fuse_ctrl_core_axi_read_out_if_agent_bus.arready = axi_core_if.r_sub.arready; + assign fuse_ctrl_core_axi_read_out_if_agent_bus.rdata = axi_core_if.r_sub.rdata; + assign fuse_ctrl_core_axi_read_out_if_agent_bus.rresp = axi_core_if.r_sub.rresp; + assign fuse_ctrl_core_axi_read_out_if_agent_bus.rid = axi_core_if.r_sub.rid; + assign fuse_ctrl_core_axi_read_out_if_agent_bus.rvalid = axi_core_if.r_sub.rvalid; + assign fuse_ctrl_core_axi_read_out_if_agent_bus.rlast = axi_core_if.r_sub.rlast; + + // Prim AXI IF + assign fuse_ctrl_prim_axi_write_in_if_agent_bus.awaddr = axi_prim_if.w_sub.awaddr; + assign fuse_ctrl_prim_axi_write_in_if_agent_bus.awburst = axi_prim_if.w_sub.awburst; + assign fuse_ctrl_prim_axi_write_in_if_agent_bus.awsize = axi_prim_if.w_sub.awsize; + assign fuse_ctrl_prim_axi_write_in_if_agent_bus.awlen = axi_prim_if.w_sub.awlen; + assign fuse_ctrl_prim_axi_write_in_if_agent_bus.awuser = axi_prim_if.w_sub.awuser; + assign fuse_ctrl_prim_axi_write_in_if_agent_bus.awid = axi_prim_if.w_sub.awid; + assign fuse_ctrl_prim_axi_write_in_if_agent_bus.awlock = axi_prim_if.w_sub.awlock; + assign fuse_ctrl_prim_axi_write_in_if_agent_bus.awvalid = axi_prim_if.w_sub.awvalid; + assign fuse_ctrl_prim_axi_write_in_if_agent_bus.wdata = axi_prim_if.w_sub.wdata; + assign fuse_ctrl_prim_axi_write_in_if_agent_bus.wstrb = axi_prim_if.w_sub.wstrb; + assign fuse_ctrl_prim_axi_write_in_if_agent_bus.wlast = axi_prim_if.w_sub.wlast; + assign fuse_ctrl_prim_axi_write_in_if_agent_bus.wvalid = axi_prim_if.w_sub.wvalid; + assign fuse_ctrl_prim_axi_write_in_if_agent_bus.bready = axi_prim_if.w_sub.bready; + + assign fuse_ctrl_prim_axi_write_out_if_agent_bus.awready = axi_prim_if.w_sub.awready; + assign fuse_ctrl_prim_axi_write_out_if_agent_bus.wready = axi_prim_if.w_sub.wready; + assign fuse_ctrl_prim_axi_write_out_if_agent_bus.bresp = axi_prim_if.w_sub.bresp; + assign fuse_ctrl_prim_axi_write_out_if_agent_bus.bvalid = axi_prim_if.w_sub.bvalid; + assign fuse_ctrl_prim_axi_write_out_if_agent_bus.bid = axi_prim_if.w_sub.bid; + + assign fuse_ctrl_prim_axi_read_in_if_agent_bus.araddr = axi_prim_if.r_sub.araddr; + assign fuse_ctrl_prim_axi_read_in_if_agent_bus.arburst = axi_prim_if.r_sub.arburst; + assign fuse_ctrl_prim_axi_read_in_if_agent_bus.arsize = axi_prim_if.r_sub.arsize; + assign fuse_ctrl_prim_axi_read_in_if_agent_bus.arlen = axi_prim_if.r_sub.arlen; + assign fuse_ctrl_prim_axi_read_in_if_agent_bus.aruser = axi_prim_if.r_sub.aruser; + assign fuse_ctrl_prim_axi_read_in_if_agent_bus.arid = axi_prim_if.r_sub.arid; + assign fuse_ctrl_prim_axi_read_in_if_agent_bus.arlock = axi_prim_if.r_sub.arlock; + assign fuse_ctrl_prim_axi_read_in_if_agent_bus.arvalid = axi_prim_if.r_sub.arvalid; + assign fuse_ctrl_prim_axi_read_in_if_agent_bus.rready = axi_prim_if.r_sub.rready; + + assign fuse_ctrl_prim_axi_read_out_if_agent_bus.arready = axi_prim_if.r_sub.arready; + assign fuse_ctrl_prim_axi_read_out_if_agent_bus.rdata = axi_prim_if.r_sub.rdata; + assign fuse_ctrl_prim_axi_read_out_if_agent_bus.rresp = axi_prim_if.r_sub.rresp; + assign fuse_ctrl_prim_axi_read_out_if_agent_bus.rid = axi_prim_if.r_sub.rid; + assign fuse_ctrl_prim_axi_read_out_if_agent_bus.rvalid = axi_prim_if.r_sub.rvalid; + assign fuse_ctrl_prim_axi_read_out_if_agent_bus.rlast = axi_prim_if.r_sub.rlast; + + // Secreg AXI IF + assign fuse_ctrl_secreg_axi_read_in_if_agent_bus.araddr = axi_secreg_if.r_sub.araddr; + assign fuse_ctrl_secreg_axi_read_in_if_agent_bus.arburst = axi_secreg_if.r_sub.arburst; + assign fuse_ctrl_secreg_axi_read_in_if_agent_bus.arsize = axi_secreg_if.r_sub.arsize; + assign fuse_ctrl_secreg_axi_read_in_if_agent_bus.arlen = axi_secreg_if.r_sub.arlen; + assign fuse_ctrl_secreg_axi_read_in_if_agent_bus.aruser = axi_secreg_if.r_sub.aruser; + assign fuse_ctrl_secreg_axi_read_in_if_agent_bus.arid = axi_secreg_if.r_sub.arid; + assign fuse_ctrl_secreg_axi_read_in_if_agent_bus.arlock = axi_secreg_if.r_sub.arlock; + assign fuse_ctrl_secreg_axi_read_in_if_agent_bus.arvalid = axi_secreg_if.r_sub.arvalid; + assign fuse_ctrl_secreg_axi_read_in_if_agent_bus.rready = axi_secreg_if.r_sub.rready; + + assign fuse_ctrl_secreg_axi_read_out_if_agent_bus.arready = axi_secreg_if.r_sub.arready; + assign fuse_ctrl_secreg_axi_read_out_if_agent_bus.rdata = axi_secreg_if.r_sub.rdata; + assign fuse_ctrl_secreg_axi_read_out_if_agent_bus.rresp = axi_secreg_if.r_sub.rresp; + assign fuse_ctrl_secreg_axi_read_out_if_agent_bus.rid = axi_secreg_if.r_sub.rid; + assign fuse_ctrl_secreg_axi_read_out_if_agent_bus.rvalid = axi_secreg_if.r_sub.rvalid; + assign fuse_ctrl_secreg_axi_read_out_if_agent_bus.rlast = axi_secreg_if.r_sub.rlast; + */ + // pragma uvmf custom dut_instantiation end + + initial begin // tbx vif_binding_block + import uvm_pkg::uvm_config_db; + // The monitor_bfm and driver_bfm for each interface is placed into the uvm_config_db. + // They are placed into the uvm_config_db using the string names defined in the parameters package. + // The string names are passed to the agent configurations by test_top through the top level configuration. + // They are retrieved by the agents configuration class for use by the agent. + uvm_config_db #( virtual fuse_ctrl_rst_in_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , fuse_ctrl_rst_in_agent_BFM , fuse_ctrl_rst_in_agent_mon_bfm ); + uvm_config_db #( virtual fuse_ctrl_rst_out_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , fuse_ctrl_rst_out_agent_BFM , fuse_ctrl_rst_out_agent_mon_bfm ); + uvm_config_db #( virtual fuse_ctrl_core_axi_write_in_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , fuse_ctrl_core_axi_write_in_if_agent_BFM , fuse_ctrl_core_axi_write_in_if_agent_mon_bfm ); + uvm_config_db #( virtual fuse_ctrl_core_axi_write_out_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , fuse_ctrl_core_axi_write_out_if_agent_BFM , fuse_ctrl_core_axi_write_out_if_agent_mon_bfm ); + uvm_config_db #( virtual fuse_ctrl_prim_axi_write_in_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , fuse_ctrl_prim_axi_write_in_if_agent_BFM , fuse_ctrl_prim_axi_write_in_if_agent_mon_bfm ); + uvm_config_db #( virtual fuse_ctrl_prim_axi_write_out_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , fuse_ctrl_prim_axi_write_out_if_agent_BFM , fuse_ctrl_prim_axi_write_out_if_agent_mon_bfm ); + uvm_config_db #( virtual fuse_ctrl_core_axi_read_in_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , fuse_ctrl_core_axi_read_in_if_agent_BFM , fuse_ctrl_core_axi_read_in_if_agent_mon_bfm ); + uvm_config_db #( virtual fuse_ctrl_core_axi_read_out_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , fuse_ctrl_core_axi_read_out_if_agent_BFM , fuse_ctrl_core_axi_read_out_if_agent_mon_bfm ); + uvm_config_db #( virtual fuse_ctrl_prim_axi_read_in_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , fuse_ctrl_prim_axi_read_in_if_agent_BFM , fuse_ctrl_prim_axi_read_in_if_agent_mon_bfm ); + uvm_config_db #( virtual fuse_ctrl_prim_axi_read_out_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , fuse_ctrl_prim_axi_read_out_if_agent_BFM , fuse_ctrl_prim_axi_read_out_if_agent_mon_bfm ); + uvm_config_db #( virtual fuse_ctrl_secreg_axi_read_in_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , fuse_ctrl_secreg_axi_read_in_if_agent_BFM , fuse_ctrl_secreg_axi_read_in_if_agent_mon_bfm ); + uvm_config_db #( virtual fuse_ctrl_secreg_axi_read_out_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , fuse_ctrl_secreg_axi_read_out_if_agent_BFM , fuse_ctrl_secreg_axi_read_out_if_agent_mon_bfm ); + uvm_config_db #( virtual fuse_ctrl_lc_otp_in_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , fuse_ctrl_lc_otp_in_if_agent_BFM , fuse_ctrl_lc_otp_in_if_agent_mon_bfm ); + uvm_config_db #( virtual fuse_ctrl_lc_otp_out_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , fuse_ctrl_lc_otp_out_if_agent_BFM , fuse_ctrl_lc_otp_out_if_agent_mon_bfm ); + uvm_config_db #( virtual fuse_ctrl_in_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , fuse_ctrl_in_if_agent_BFM , fuse_ctrl_in_if_agent_mon_bfm ); + uvm_config_db #( virtual fuse_ctrl_out_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , fuse_ctrl_out_if_agent_BFM , fuse_ctrl_out_if_agent_mon_bfm ); + uvm_config_db #( virtual fuse_ctrl_rst_in_driver_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , fuse_ctrl_rst_in_agent_BFM , fuse_ctrl_rst_in_agent_drv_bfm ); + uvm_config_db #( virtual fuse_ctrl_core_axi_write_in_driver_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , fuse_ctrl_core_axi_write_in_if_agent_BFM , fuse_ctrl_core_axi_write_in_if_agent_drv_bfm ); + uvm_config_db #( virtual fuse_ctrl_prim_axi_write_in_driver_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , fuse_ctrl_prim_axi_write_in_if_agent_BFM , fuse_ctrl_prim_axi_write_in_if_agent_drv_bfm ); + uvm_config_db #( virtual fuse_ctrl_core_axi_read_in_driver_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , fuse_ctrl_core_axi_read_in_if_agent_BFM , fuse_ctrl_core_axi_read_in_if_agent_drv_bfm ); + uvm_config_db #( virtual fuse_ctrl_prim_axi_read_in_driver_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , fuse_ctrl_prim_axi_read_in_if_agent_BFM , fuse_ctrl_prim_axi_read_in_if_agent_drv_bfm ); + uvm_config_db #( virtual fuse_ctrl_secreg_axi_read_in_driver_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , fuse_ctrl_secreg_axi_read_in_if_agent_BFM , fuse_ctrl_secreg_axi_read_in_if_agent_drv_bfm ); + uvm_config_db #( virtual fuse_ctrl_lc_otp_in_driver_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , fuse_ctrl_lc_otp_in_if_agent_BFM , fuse_ctrl_lc_otp_in_if_agent_drv_bfm ); + uvm_config_db #( virtual fuse_ctrl_in_driver_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , fuse_ctrl_in_if_agent_BFM , fuse_ctrl_in_if_agent_drv_bfm ); + end + +endmodule + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/testbench/hdl_top.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/testbench/hdl_top.vinfo new file mode 100644 index 0000000..b39169a --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/testbench/hdl_top.vinfo @@ -0,0 +1,20 @@ +@use $UVMF_PROJECT_DIR/rtl/verilog/verilog_dut.vinfo +@use $UVMF_PROJECT_DIR/tb/parameters/fuse_ctrl_parameters_pkg.vinfo +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_bfm.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_bfm.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_bfm.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_bfm.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_bfm.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_bfm.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_bfm.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_bfm.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_bfm.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_bfm.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_bfm.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_bfm.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_bfm.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_bfm.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_bfm.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_bfm.vinfo +hdl_top.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/testbench/hvl_top.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/testbench/hvl_top.compile new file mode 100644 index 0000000..0404887 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/testbench/hvl_top.compile @@ -0,0 +1,7 @@ +incdir: + - ${uvm_path}/src + - . +needs: + - ../tests/fuse_ctrl_tests_pkg.compile +src: + - hvl_top.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/testbench/hvl_top.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/testbench/hvl_top.sv new file mode 100644 index 0000000..68e3fc6 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/testbench/hvl_top.sv @@ -0,0 +1,47 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// +// DESCRIPTION: This module loads the test package and starts the UVM phases. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +module hvl_top; + +import uvm_pkg::*; +import fuse_ctrl_tests_pkg::*; + + // pragma uvmf custom module_item_additional begin + // pragma uvmf custom module_item_additional end + + initial begin + $timeformat(-9,3,"ns",5); + run_test(); + end + +endmodule + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/testbench/hvl_top.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/testbench/hvl_top.vinfo new file mode 100644 index 0000000..31185e4 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/testbench/hvl_top.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_PROJECT_DIR/tb/tests/fuse_ctrl_tests_pkg.vinfo +hvl_top.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/testbench/top_filelist_hdl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/testbench/top_filelist_hdl.f new file mode 100644 index 0000000..1e9dab6 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/testbench/top_filelist_hdl.f @@ -0,0 +1,3 @@ +$UVMF_PROJECT_DIR/tb/testbench/hdl_top.sv +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/testbench/top_filelist_hvl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/testbench/top_filelist_hvl.f new file mode 100644 index 0000000..42383ab --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/testbench/top_filelist_hvl.f @@ -0,0 +1,3 @@ +$UVMF_PROJECT_DIR/tb/testbench/hvl_top.sv +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/tests/fuse_ctrl_tests_pkg.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/tests/fuse_ctrl_tests_pkg.compile new file mode 100644 index 0000000..c755851 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/tests/fuse_ctrl_tests_pkg.compile @@ -0,0 +1,23 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in.compile + - ../../../../verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out.compile + - ../../../../verification_ip/environment_packages/fuse_ctrl_env_pkg/fuse_ctrl_env_pkg.compile + - ../parameters/fuse_ctrl_parameters_pkg.compile + - ../sequences/fuse_ctrl_sequences_pkg.compile +src: + - fuse_ctrl_tests_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/tests/fuse_ctrl_tests_pkg.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/tests/fuse_ctrl_tests_pkg.sv new file mode 100644 index 0000000..05f83c5 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/tests/fuse_ctrl_tests_pkg.sv @@ -0,0 +1,96 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This package contains all tests currently written for +// the simulation project. Once compiled, any test can be selected +// from the vsim command line using +UVM_TESTNAME=yourTestNameHere +// +// CONTAINS: +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +package fuse_ctrl_tests_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg::*; + import fuse_ctrl_parameters_pkg::*; + import fuse_ctrl_env_pkg::*; + import fuse_ctrl_sequences_pkg::*; + import fuse_ctrl_rst_in_pkg::*; + import fuse_ctrl_rst_in_pkg_hdl::*; + import fuse_ctrl_rst_out_pkg::*; + import fuse_ctrl_rst_out_pkg_hdl::*; + import fuse_ctrl_core_axi_write_in_pkg::*; + import fuse_ctrl_core_axi_write_in_pkg_hdl::*; + import fuse_ctrl_core_axi_write_out_pkg::*; + import fuse_ctrl_core_axi_write_out_pkg_hdl::*; + import fuse_ctrl_prim_axi_write_in_pkg::*; + import fuse_ctrl_prim_axi_write_in_pkg_hdl::*; + import fuse_ctrl_prim_axi_write_out_pkg::*; + import fuse_ctrl_prim_axi_write_out_pkg_hdl::*; + import fuse_ctrl_core_axi_read_in_pkg::*; + import fuse_ctrl_core_axi_read_in_pkg_hdl::*; + import fuse_ctrl_core_axi_read_out_pkg::*; + import fuse_ctrl_core_axi_read_out_pkg_hdl::*; + import fuse_ctrl_prim_axi_read_in_pkg::*; + import fuse_ctrl_prim_axi_read_in_pkg_hdl::*; + import fuse_ctrl_prim_axi_read_out_pkg::*; + import fuse_ctrl_prim_axi_read_out_pkg_hdl::*; + import fuse_ctrl_secreg_axi_read_in_pkg::*; + import fuse_ctrl_secreg_axi_read_in_pkg_hdl::*; + import fuse_ctrl_secreg_axi_read_out_pkg::*; + import fuse_ctrl_secreg_axi_read_out_pkg_hdl::*; + import fuse_ctrl_lc_otp_in_pkg::*; + import fuse_ctrl_lc_otp_in_pkg_hdl::*; + import fuse_ctrl_lc_otp_out_pkg::*; + import fuse_ctrl_lc_otp_out_pkg_hdl::*; + import fuse_ctrl_in_pkg::*; + import fuse_ctrl_in_pkg_hdl::*; + import fuse_ctrl_out_pkg::*; + import fuse_ctrl_out_pkg_hdl::*; + + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + `include "src/test_top.svh" + `include "src/register_test.svh" + `include "src/example_derived_test.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new tests to the src directory + // be sure to add the test file here so that it will be + // compiled as part of the test package. Be sure to place + // the new test after any base tests of the new test. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/tests/fuse_ctrl_tests_pkg.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/tests/fuse_ctrl_tests_pkg.vinfo new file mode 100644 index 0000000..651052b --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/tests/fuse_ctrl_tests_pkg.vinfo @@ -0,0 +1,22 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/environment_packages/fuse_ctrl_env_pkg/fuse_ctrl_env_pkg.vinfo +@use $UVMF_PROJECT_DIR/tb/parameters/fuse_ctrl_parameters_pkg.vinfo +@use $UVMF_PROJECT_DIR/tb/sequences/fuse_ctrl_sequences_pkg.vinfo ++incdir+@vinfodir +fuse_ctrl_tests_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/tests/src/example_derived_test.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/tests/src/example_derived_test.svh new file mode 100644 index 0000000..82d6c45 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/tests/src/example_derived_test.svh @@ -0,0 +1,57 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This test extends test_top and makes +// changes to test_top using the UVM factory type_override: +// +// Test scenario: +// This is a template test that can be used to create future tests. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class example_derived_test extends test_top; + + `uvm_component_utils( example_derived_test ); + + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + + virtual function void build_phase(uvm_phase phase); + // The factory override below is an example of how to replace the fuse_ctrl_bench_sequence_base + // sequence with the example_derived_test_sequence. + fuse_ctrl_bench_sequence_base::type_id::set_type_override(example_derived_test_sequence::get_type()); + // Execute the build_phase of test_top AFTER all factory overrides have been created. + super.build_phase(phase); + // pragma uvmf custom configuration_settings_post_randomize begin + // UVMF_CHANGE_ME Test specific configuration values can be set here. + // The configuration structure has already been randomized. + // pragma uvmf custom configuration_settings_post_randomize end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/tests/src/register_test.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/tests/src/register_test.svh new file mode 100644 index 0000000..1be7222 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/tests/src/register_test.svh @@ -0,0 +1,54 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This test extends test_top and makes +// changes to test_top using the UVM factory type_override: +// +// Test scenario: +// This is a template test that can be used to create future tests. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class register_test extends test_top; + + `uvm_component_utils( register_test ); + + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + + virtual function void build_phase(uvm_phase phase); + // The factory override below replaces the fuse_ctrl_bench_sequence_base + // sequence with the register_test_sequence. + fuse_ctrl_bench_sequence_base::type_id::set_type_override(register_test_sequence::get_type()); + // Execute the build_phase of test_top AFTER all factory overrides have been created. + super.build_phase(phase); + endfunction + + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/tests/src/test_top.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/tests/src/test_top.svh new file mode 100644 index 0000000..f5b1c3c --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/tb/tests/src/test_top.svh @@ -0,0 +1,120 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// Description: This top level UVM test is the base class for all +// future tests created for this project. +// +// This test class contains: +// Configuration: The top level configuration for the project. +// Environment: The top level environment for the project. +// Top_level_sequence: The top level sequence for the project. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +typedef fuse_ctrl_env_configuration fuse_ctrl_env_configuration_t; +typedef fuse_ctrl_environment fuse_ctrl_environment_t; + +class test_top extends uvmf_test_base #(.CONFIG_T(fuse_ctrl_env_configuration_t), + .ENV_T(fuse_ctrl_environment_t), + .TOP_LEVEL_SEQ_T(fuse_ctrl_bench_sequence_base)); + + `uvm_component_utils( test_top ); + + + + string interface_names[] = { + fuse_ctrl_rst_in_agent_BFM /* fuse_ctrl_rst_in_agent [0] */ , + fuse_ctrl_rst_out_agent_BFM /* fuse_ctrl_rst_out_agent [1] */ , + fuse_ctrl_core_axi_write_in_if_agent_BFM /* fuse_ctrl_core_axi_write_in_if_agent [2] */ , + fuse_ctrl_core_axi_write_out_if_agent_BFM /* fuse_ctrl_core_axi_write_out_if_agent [3] */ , + fuse_ctrl_prim_axi_write_in_if_agent_BFM /* fuse_ctrl_prim_axi_write_in_if_agent [4] */ , + fuse_ctrl_prim_axi_write_out_if_agent_BFM /* fuse_ctrl_prim_axi_write_out_if_agent [5] */ , + fuse_ctrl_core_axi_read_in_if_agent_BFM /* fuse_ctrl_core_axi_read_in_if_agent [6] */ , + fuse_ctrl_core_axi_read_out_if_agent_BFM /* fuse_ctrl_core_axi_read_out_if_agent [7] */ , + fuse_ctrl_prim_axi_read_in_if_agent_BFM /* fuse_ctrl_prim_axi_read_in_if_agent [8] */ , + fuse_ctrl_prim_axi_read_out_if_agent_BFM /* fuse_ctrl_prim_axi_read_out_if_agent [9] */ , + fuse_ctrl_secreg_axi_read_in_if_agent_BFM /* fuse_ctrl_secreg_axi_read_in_if_agent [10] */ , + fuse_ctrl_secreg_axi_read_out_if_agent_BFM /* fuse_ctrl_secreg_axi_read_out_if_agent [11] */ , + fuse_ctrl_lc_otp_in_if_agent_BFM /* fuse_ctrl_lc_otp_in_if_agent [12] */ , + fuse_ctrl_lc_otp_out_if_agent_BFM /* fuse_ctrl_lc_otp_out_if_agent [13] */ , + fuse_ctrl_in_if_agent_BFM /* fuse_ctrl_in_if_agent [14] */ , + fuse_ctrl_out_if_agent_BFM /* fuse_ctrl_out_if_agent [15] */ +}; + +uvmf_active_passive_t interface_activities[] = { + ACTIVE /* fuse_ctrl_rst_in_agent [0] */ , + PASSIVE /* fuse_ctrl_rst_out_agent [1] */ , + ACTIVE /* fuse_ctrl_core_axi_write_in_if_agent [2] */ , + PASSIVE /* fuse_ctrl_core_axi_write_out_if_agent [3] */ , + ACTIVE /* fuse_ctrl_prim_axi_write_in_if_agent [4] */ , + PASSIVE /* fuse_ctrl_prim_axi_write_out_if_agent [5] */ , + ACTIVE /* fuse_ctrl_core_axi_read_in_if_agent [6] */ , + PASSIVE /* fuse_ctrl_core_axi_read_out_if_agent [7] */ , + ACTIVE /* fuse_ctrl_prim_axi_read_in_if_agent [8] */ , + PASSIVE /* fuse_ctrl_prim_axi_read_out_if_agent [9] */ , + ACTIVE /* fuse_ctrl_secreg_axi_read_in_if_agent [10] */ , + PASSIVE /* fuse_ctrl_secreg_axi_read_out_if_agent [11] */ , + ACTIVE /* fuse_ctrl_lc_otp_in_if_agent [12] */ , + PASSIVE /* fuse_ctrl_lc_otp_out_if_agent [13] */ , + ACTIVE /* fuse_ctrl_in_if_agent [14] */ , + PASSIVE /* fuse_ctrl_out_if_agent [15] */ }; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // FUNCTION: new() + // This is the standard systemVerilog constructor. All components are + // constructed in the build_phase to allow factory overriding. + // + function new( string name = "", uvm_component parent = null ); + super.new( name ,parent ); + endfunction + + + + // **************************************************************************** + // FUNCTION: build_phase() + // The construction of the configuration and environment classes is done in + // the build_phase of uvmf_test_base. Once the configuraton and environment + // classes are built then the initialize call is made to perform the + // following: + // Monitor and driver BFM virtual interface handle passing into agents + // Set the active/passive state for each agent + // Once this build_phase completes, the build_phase of the environment is + // executed which builds the agents. + // + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + // pragma uvmf custom configuration_settings_post_randomize begin + // pragma uvmf custom configuration_settings_post_randomize end + configuration.initialize(NA, "uvm_test_top.environment", interface_names, null, interface_activities); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/yaml/fuse_ctrl_bench.yaml b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/yaml/fuse_ctrl_bench.yaml new file mode 100644 index 0000000..24489d9 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/project_benches/fuse_ctrl/yaml/fuse_ctrl_bench.yaml @@ -0,0 +1,45 @@ +uvmf: + benches: + fuse_ctrl: + active_passive: + - bfm_name: fuse_ctrl_rst_in_agent + value: ACTIVE + - bfm_name: fuse_ctrl_rst_out_agent + value: PASSIVE + - bfm_name: fuse_ctrl_core_axi_write_in_if_agent + value: ACTIVE + - bfm_name: fuse_ctrl_core_axi_write_out_if_agent + value: PASSIVE + - bfm_name: fuse_ctrl_prim_axi_write_in_if_agent + value: ACTIVE + - bfm_name: fuse_ctrl_prim_axi_write_out_if_agent + value: PASSIVE + - bfm_name: fuse_ctrl_core_axi_read_in_if_agent + value: ACTIVE + - bfm_name: fuse_ctrl_core_axi_read_out_if_agent + value: PASSIVE + - bfm_name: fuse_ctrl_prim_axi_read_in_if_agent + value: ACTIVE + - bfm_name: fuse_ctrl_prim_axi_read_out_if_agent + value: PASSIVE + - bfm_name: fuse_ctrl_secreg_axi_read_in_if_agent + value: ACTIVE + - bfm_name: fuse_ctrl_secreg_axi_read_out_if_agent + value: PASSIVE + - bfm_name: fuse_ctrl_lc_otp_in_if_agent + value: ACTIVE + - bfm_name: fuse_ctrl_lc_otp_out_if_agent + value: PASSIVE + - bfm_name: fuse_ctrl_in_if_agent + value: ACTIVE + - bfm_name: fuse_ctrl_out_if_agent + value: PASSIVE + active_passive_default: ACTIVE + clock_half_period: 5ns + clock_phase_offset: 0ns + existing_library_component: 'True' + interface_params: [] + reset_assertion_level: 'False' + reset_duration: 200ns + top_env: fuse_ctrl + use_dpi_link: 'False' diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/environment_packages/fuse_ctrl_env_pkg/.project b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/environment_packages/fuse_ctrl_env_pkg/.project new file mode 100644 index 0000000..ec64afa --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/environment_packages/fuse_ctrl_env_pkg/.project @@ -0,0 +1,32 @@ + + + fuse_ctrl_env_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/environment_packages/fuse_ctrl_env_pkg/.svproject b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/environment_packages/fuse_ctrl_env_pkg/.svproject new file mode 100644 index 0000000..bcfe6ac --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/environment_packages/fuse_ctrl_env_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/environment_packages/fuse_ctrl_env_pkg/Makefile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/environment_packages/fuse_ctrl_env_pkg/Makefile new file mode 100644 index 0000000..4cf61d5 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/environment_packages/fuse_ctrl_env_pkg/Makefile @@ -0,0 +1,56 @@ +# fuse_ctrl environment packages source and make target + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +# Include all requisite sub-environment package targets for this bench + +fuse_ctrl_ENV_PKG =\ + $(UVMF_VIP_LIBRARY_HOME)/environment_packages/fuse_ctrl_env_pkg/fuse_ctrl_env_pkg.sv + +COMP_fuse_ctrl_PKG_TGT_0 = q_comp_fuse_ctrl_env_pkg +COMP_fuse_ctrl_PKG_TGT_1 = v_comp_fuse_ctrl_env_pkg +COMP_fuse_ctrl_PKG_TGT = $(COMP_fuse_ctrl_PKG_TGT_$(USE_VELOCE)) + +comp_fuse_ctrl_env_pkg: $(COMP_fuse_ctrl_PKG_TGT) + +q_comp_fuse_ctrl_env_pkg: + $(HVL_COMP_CMD) +incdir+$(UVMF_VIP_LIBRARY_HOME)/environment_packages/fuse_ctrl_env_pkg $(fuse_ctrl_ENV_PKG) + +v_comp_fuse_ctrl_env_pkg: q_comp_fuse_ctrl_env_pkg + $(VELANALYZE_HVL_CMD) +incdir+$(UVMF_VIP_LIBRARY_HOME)/environment_packages/fuse_ctrl_env_pkg $(fuse_ctrl_ENV_PKG) + + + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export fuse_ctrl_ENV_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/environment_packages/fuse_ctrl_env_pkg/dpi + +C_FILE_COMPILE_LIST_fuse_ctrl_env_pkg = \ + +O_FILE_COMPILE_LIST_fuse_ctrl_env_pkg = $(notdir $(C_FILE_COMPILE_LIST_fuse_ctrl_env_pkg:.c=.o)) + +GCC_COMP_ARGS_fuse_ctrl_env_pkg += -I$(fuse_ctrl_ENV_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_fuse_ctrl_env_pkg += $(fuse_ctrl_ENV_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_fuse_ctrl_env_pkg += \ + \ + -o .so + +comp_fuse_ctrl_env_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Environment C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_fuse_ctrl_env_pkg) $(C_FILE_COMPILE_LIST_fuse_ctrl_env_pkg) + @echo "--------------------------------" + @echo "Linking Environment C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_fuse_ctrl_env_pkg) $(O_FILE_COMPILE_LIST_fuse_ctrl_env_pkg) + @echo "--------------------------------" + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/environment_packages/fuse_ctrl_env_pkg/compile.do b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/environment_packages/fuse_ctrl_env_pkg/compile.do new file mode 100644 index 0000000..05dca66 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/environment_packages/fuse_ctrl_env_pkg/compile.do @@ -0,0 +1,12 @@ +# Tcl do file for compile of fuse_ctrl interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + + +quietly set cmd [format "vlog -timescale 1ps/1ps +incdir+%s/environment_packages/fuse_ctrl_env_pkg" $env(UVMF_VIP_LIBRARY_HOME)] +quietly set cmd [format "%s %s/environment_packages/fuse_ctrl_env_pkg/fuse_ctrl_env_pkg.sv" $cmd $env(UVMF_VIP_LIBRARY_HOME)] +eval $cmd + + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/environment_packages/fuse_ctrl_env_pkg/fuse_ctrl_env_pkg.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/environment_packages/fuse_ctrl_env_pkg/fuse_ctrl_env_pkg.compile new file mode 100644 index 0000000..7bd08d6 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/environment_packages/fuse_ctrl_env_pkg/fuse_ctrl_env_pkg.compile @@ -0,0 +1,22 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ../../../verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_hvl.compile + - ../../../verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_hvl.compile + - ../../../verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_hvl.compile + - ../../../verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_hvl.compile + - ../../../verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_hvl.compile + - ../../../verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_hvl.compile + - ../../../verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_hvl.compile + - ../../../verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_hvl.compile + - ../../../verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_hvl.compile + - ../../../verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_hvl.compile + - ../../../verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_hvl.compile + - ../../../verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_hvl.compile + - ../../../verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_hvl.compile + - ../../../verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_hvl.compile + - ../../../verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_hvl.compile + - ../../../verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_hvl.compile + +src: + - fuse_ctrl_env_pkg.sv + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/environment_packages/fuse_ctrl_env_pkg/fuse_ctrl_env_pkg.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/environment_packages/fuse_ctrl_env_pkg/fuse_ctrl_env_pkg.sv new file mode 100644 index 0000000..7a5859b --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/environment_packages/fuse_ctrl_env_pkg/fuse_ctrl_env_pkg.sv @@ -0,0 +1,106 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// environment package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_env_pkg; + + import uvm_pkg::*; + `include "uvm_macros.svh" + import uvmf_base_pkg::*; + import fuse_ctrl_rst_in_pkg::*; + import fuse_ctrl_rst_in_pkg_hdl::*; + import fuse_ctrl_rst_out_pkg::*; + import fuse_ctrl_rst_out_pkg_hdl::*; + import fuse_ctrl_core_axi_write_in_pkg::*; + import fuse_ctrl_core_axi_write_in_pkg_hdl::*; + import fuse_ctrl_core_axi_write_out_pkg::*; + import fuse_ctrl_core_axi_write_out_pkg_hdl::*; + import fuse_ctrl_prim_axi_write_in_pkg::*; + import fuse_ctrl_prim_axi_write_in_pkg_hdl::*; + import fuse_ctrl_prim_axi_write_out_pkg::*; + import fuse_ctrl_prim_axi_write_out_pkg_hdl::*; + import fuse_ctrl_core_axi_read_in_pkg::*; + import fuse_ctrl_core_axi_read_in_pkg_hdl::*; + import fuse_ctrl_core_axi_read_out_pkg::*; + import fuse_ctrl_core_axi_read_out_pkg_hdl::*; + import fuse_ctrl_prim_axi_read_in_pkg::*; + import fuse_ctrl_prim_axi_read_in_pkg_hdl::*; + import fuse_ctrl_prim_axi_read_out_pkg::*; + import fuse_ctrl_prim_axi_read_out_pkg_hdl::*; + import fuse_ctrl_secreg_axi_read_in_pkg::*; + import fuse_ctrl_secreg_axi_read_in_pkg_hdl::*; + import fuse_ctrl_secreg_axi_read_out_pkg::*; + import fuse_ctrl_secreg_axi_read_out_pkg_hdl::*; + import fuse_ctrl_lc_otp_in_pkg::*; + import fuse_ctrl_lc_otp_in_pkg_hdl::*; + import fuse_ctrl_lc_otp_out_pkg::*; + import fuse_ctrl_lc_otp_out_pkg_hdl::*; + import fuse_ctrl_in_pkg::*; + import fuse_ctrl_in_pkg_hdl::*; + import fuse_ctrl_out_pkg::*; + import fuse_ctrl_out_pkg_hdl::*; + + `uvm_analysis_imp_decl(_fuse_ctrl_rst_in_agent_ae) + `uvm_analysis_imp_decl(_fuse_ctrl_core_axi_write_in_agent_ae) + `uvm_analysis_imp_decl(_fuse_ctrl_prim_axi_write_in_agent_ae) + `uvm_analysis_imp_decl(_fuse_ctrl_core_axi_read_in_agent_ae) + `uvm_analysis_imp_decl(_fuse_ctrl_prim_axi_read_in_agent_ae) + `uvm_analysis_imp_decl(_fuse_ctrl_secreg_axi_read_in_agent_ae) + `uvm_analysis_imp_decl(_fuse_ctrl_lc_otp_in_agent_ae) + `uvm_analysis_imp_decl(_fuse_ctrl_in_agent_ae) + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HVL parameters + + `include "src/fuse_ctrl_env_typedefs.svh" + `include "src/fuse_ctrl_env_configuration.svh" + `include "src/fuse_ctrl_predictor.svh" + `include "src/fuse_ctrl_scoreboard.svh" + `include "src/fuse_ctrl_environment.svh" + `include "src/fuse_ctrl_env_sequence_base.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new environment level sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the environment package. Be sure to place + // the new sequence after any base sequence of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/environment_packages/fuse_ctrl_env_pkg/fuse_ctrl_env_pkg.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/environment_packages/fuse_ctrl_env_pkg/fuse_ctrl_env_pkg.vinfo new file mode 100644 index 0000000..f4f985f --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/environment_packages/fuse_ctrl_env_pkg/fuse_ctrl_env_pkg.vinfo @@ -0,0 +1,19 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_pkg.vinfo ++incdir+@vinfodir +fuse_ctrl_env_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/environment_packages/fuse_ctrl_env_pkg/fuse_ctrl_env_pkg_sve.F b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/environment_packages/fuse_ctrl_env_pkg/fuse_ctrl_env_pkg_sve.F new file mode 100644 index 0000000..b40213d --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/environment_packages/fuse_ctrl_env_pkg/fuse_ctrl_env_pkg_sve.F @@ -0,0 +1,12 @@ + +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + +// Sub-Environments + ++incdir+. +./fuse_ctrl_env_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/environment_packages/fuse_ctrl_env_pkg/src/fuse_ctrl_env_configuration.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/environment_packages/fuse_ctrl_env_pkg/src/fuse_ctrl_env_configuration.svh new file mode 100644 index 0000000..1f5b77d --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/environment_packages/fuse_ctrl_env_pkg/src/fuse_ctrl_env_configuration.svh @@ -0,0 +1,261 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: THis is the configuration for the fuse_ctrl environment. +// it contains configuration classes for each agent. It also contains +// environment level configuration variables. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_env_configuration +extends uvmf_environment_configuration_base; + + `uvm_object_utils( fuse_ctrl_env_configuration ) + + +//Constraints for the configuration variables: + + + covergroup fuse_ctrl_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + // pragma uvmf custom covergroup end + endgroup + + + typedef fuse_ctrl_rst_in_configuration fuse_ctrl_rst_in_agent_config_t; + rand fuse_ctrl_rst_in_agent_config_t fuse_ctrl_rst_in_agent_config; + + typedef fuse_ctrl_rst_out_configuration fuse_ctrl_rst_out_agent_config_t; + rand fuse_ctrl_rst_out_agent_config_t fuse_ctrl_rst_out_agent_config; + + typedef fuse_ctrl_core_axi_write_in_configuration fuse_ctrl_core_axi_write_in_if_agent_config_t; + rand fuse_ctrl_core_axi_write_in_if_agent_config_t fuse_ctrl_core_axi_write_in_if_agent_config; + + typedef fuse_ctrl_core_axi_write_out_configuration fuse_ctrl_core_axi_write_out_if_agent_config_t; + rand fuse_ctrl_core_axi_write_out_if_agent_config_t fuse_ctrl_core_axi_write_out_if_agent_config; + + typedef fuse_ctrl_prim_axi_write_in_configuration fuse_ctrl_prim_axi_write_in_if_agent_config_t; + rand fuse_ctrl_prim_axi_write_in_if_agent_config_t fuse_ctrl_prim_axi_write_in_if_agent_config; + + typedef fuse_ctrl_prim_axi_write_out_configuration fuse_ctrl_prim_axi_write_out_if_agent_config_t; + rand fuse_ctrl_prim_axi_write_out_if_agent_config_t fuse_ctrl_prim_axi_write_out_if_agent_config; + + typedef fuse_ctrl_core_axi_read_in_configuration fuse_ctrl_core_axi_read_in_if_agent_config_t; + rand fuse_ctrl_core_axi_read_in_if_agent_config_t fuse_ctrl_core_axi_read_in_if_agent_config; + + typedef fuse_ctrl_core_axi_read_out_configuration fuse_ctrl_core_axi_read_out_if_agent_config_t; + rand fuse_ctrl_core_axi_read_out_if_agent_config_t fuse_ctrl_core_axi_read_out_if_agent_config; + + typedef fuse_ctrl_prim_axi_read_in_configuration fuse_ctrl_prim_axi_read_in_if_agent_config_t; + rand fuse_ctrl_prim_axi_read_in_if_agent_config_t fuse_ctrl_prim_axi_read_in_if_agent_config; + + typedef fuse_ctrl_prim_axi_read_out_configuration fuse_ctrl_prim_axi_read_out_if_agent_config_t; + rand fuse_ctrl_prim_axi_read_out_if_agent_config_t fuse_ctrl_prim_axi_read_out_if_agent_config; + + typedef fuse_ctrl_secreg_axi_read_in_configuration fuse_ctrl_secreg_axi_read_in_if_agent_config_t; + rand fuse_ctrl_secreg_axi_read_in_if_agent_config_t fuse_ctrl_secreg_axi_read_in_if_agent_config; + + typedef fuse_ctrl_secreg_axi_read_out_configuration fuse_ctrl_secreg_axi_read_out_if_agent_config_t; + rand fuse_ctrl_secreg_axi_read_out_if_agent_config_t fuse_ctrl_secreg_axi_read_out_if_agent_config; + + typedef fuse_ctrl_lc_otp_in_configuration fuse_ctrl_lc_otp_in_if_agent_config_t; + rand fuse_ctrl_lc_otp_in_if_agent_config_t fuse_ctrl_lc_otp_in_if_agent_config; + + typedef fuse_ctrl_lc_otp_out_configuration fuse_ctrl_lc_otp_out_if_agent_config_t; + rand fuse_ctrl_lc_otp_out_if_agent_config_t fuse_ctrl_lc_otp_out_if_agent_config; + + typedef fuse_ctrl_in_configuration fuse_ctrl_in_if_agent_config_t; + rand fuse_ctrl_in_if_agent_config_t fuse_ctrl_in_if_agent_config; + + typedef fuse_ctrl_out_configuration fuse_ctrl_out_if_agent_config_t; + rand fuse_ctrl_out_if_agent_config_t fuse_ctrl_out_if_agent_config; + + + + + typedef uvmf_virtual_sequencer_base #(.CONFIG_T(fuse_ctrl_env_configuration)) fuse_ctrl_vsqr_t; + fuse_ctrl_vsqr_t vsqr; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// This function constructs the configuration object for each agent in the environment. +// + function new( string name = "" ); + super.new( name ); + + + fuse_ctrl_rst_in_agent_config = fuse_ctrl_rst_in_agent_config_t::type_id::create("fuse_ctrl_rst_in_agent_config"); + fuse_ctrl_rst_out_agent_config = fuse_ctrl_rst_out_agent_config_t::type_id::create("fuse_ctrl_rst_out_agent_config"); + fuse_ctrl_core_axi_write_in_if_agent_config = fuse_ctrl_core_axi_write_in_if_agent_config_t::type_id::create("fuse_ctrl_core_axi_write_in_if_agent_config"); + fuse_ctrl_core_axi_write_out_if_agent_config = fuse_ctrl_core_axi_write_out_if_agent_config_t::type_id::create("fuse_ctrl_core_axi_write_out_if_agent_config"); + fuse_ctrl_prim_axi_write_in_if_agent_config = fuse_ctrl_prim_axi_write_in_if_agent_config_t::type_id::create("fuse_ctrl_prim_axi_write_in_if_agent_config"); + fuse_ctrl_prim_axi_write_out_if_agent_config = fuse_ctrl_prim_axi_write_out_if_agent_config_t::type_id::create("fuse_ctrl_prim_axi_write_out_if_agent_config"); + fuse_ctrl_core_axi_read_in_if_agent_config = fuse_ctrl_core_axi_read_in_if_agent_config_t::type_id::create("fuse_ctrl_core_axi_read_in_if_agent_config"); + fuse_ctrl_core_axi_read_out_if_agent_config = fuse_ctrl_core_axi_read_out_if_agent_config_t::type_id::create("fuse_ctrl_core_axi_read_out_if_agent_config"); + fuse_ctrl_prim_axi_read_in_if_agent_config = fuse_ctrl_prim_axi_read_in_if_agent_config_t::type_id::create("fuse_ctrl_prim_axi_read_in_if_agent_config"); + fuse_ctrl_prim_axi_read_out_if_agent_config = fuse_ctrl_prim_axi_read_out_if_agent_config_t::type_id::create("fuse_ctrl_prim_axi_read_out_if_agent_config"); + fuse_ctrl_secreg_axi_read_in_if_agent_config = fuse_ctrl_secreg_axi_read_in_if_agent_config_t::type_id::create("fuse_ctrl_secreg_axi_read_in_if_agent_config"); + fuse_ctrl_secreg_axi_read_out_if_agent_config = fuse_ctrl_secreg_axi_read_out_if_agent_config_t::type_id::create("fuse_ctrl_secreg_axi_read_out_if_agent_config"); + fuse_ctrl_lc_otp_in_if_agent_config = fuse_ctrl_lc_otp_in_if_agent_config_t::type_id::create("fuse_ctrl_lc_otp_in_if_agent_config"); + fuse_ctrl_lc_otp_out_if_agent_config = fuse_ctrl_lc_otp_out_if_agent_config_t::type_id::create("fuse_ctrl_lc_otp_out_if_agent_config"); + fuse_ctrl_in_if_agent_config = fuse_ctrl_in_if_agent_config_t::type_id::create("fuse_ctrl_in_if_agent_config"); + fuse_ctrl_out_if_agent_config = fuse_ctrl_out_if_agent_config_t::type_id::create("fuse_ctrl_out_if_agent_config"); + + + fuse_ctrl_configuration_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that configuration variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + + // pragma uvmf custom new begin + // pragma uvmf custom new end + endfunction + +// **************************************************************************** +// FUNCTION : set_vsqr() +// This function is used to assign the vsqr handle. + virtual function void set_vsqr( fuse_ctrl_vsqr_t vsqr); + this.vsqr = vsqr; + endfunction : set_vsqr + +// **************************************************************************** +// FUNCTION: post_randomize() +// This function is automatically called after the randomize() function +// is executed. +// + function void post_randomize(); + super.post_randomize(); + // pragma uvmf custom post_randomize begin + // pragma uvmf custom post_randomize end + endfunction + +// **************************************************************************** +// FUNCTION: convert2string() +// This function converts all variables in this class to a single string for +// logfile reporting. This function concatenates the convert2string result for +// each agent configuration in this configuration class. +// + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + return { + + "\n", fuse_ctrl_rst_agent_config.convert2string, + "\n", fuse_ctrl_core_axi_write_agent_config.convert2string, + "\n", fuse_ctrl_prim_axi_write_agent_config.convert2string, + "\n", fuse_ctrl_core_axi_read_agent_config.convert2string, + "\n", fuse_ctrl_prim_axi_read_agent_config.convert2string, + "\n", fuse_ctrl_secreg_axi_read_agent_config.convert2string, + "\n", fuse_ctrl_lc_otp_if_agent_config.convert2string + + + }; + // pragma uvmf custom convert2string end + endfunction +// **************************************************************************** +// FUNCTION: initialize(); +// This function configures each interface agents configuration class. The +// sim level determines the active/passive state of the agent. The environment_path +// identifies the hierarchy down to and including the instantiation name of the +// environment for this configuration class. Each instance of the environment +// has its own configuration class. The string interface names are used by +// the agent configurations to identify the virtual interface handle to pull from +// the uvm_config_db. +// + function void initialize(uvmf_sim_level_t sim_level, + string environment_path, + string interface_names[], + uvm_reg_block register_model = null, + uvmf_active_passive_t interface_activity[] = {} + ); + + super.initialize(sim_level, environment_path, interface_names, register_model, interface_activity); + + + + // Interface initialization for local agents + fuse_ctrl_rst_in_agent_config.initialize( interface_activity[0], {environment_path,".fuse_ctrl_rst_in_agent"}, interface_names[0]); + fuse_ctrl_rst_in_agent_config.initiator_responder = INITIATOR; + // fuse_ctrl_rst_in_agent_config.has_coverage = 1; + fuse_ctrl_rst_out_agent_config.initialize( interface_activity[1], {environment_path,".fuse_ctrl_rst_out_agent"}, interface_names[1]); + fuse_ctrl_rst_out_agent_config.initiator_responder = RESPONDER; + // fuse_ctrl_rst_out_agent_config.has_coverage = 1; + fuse_ctrl_core_axi_write_in_if_agent_config.initialize( interface_activity[2], {environment_path,".fuse_ctrl_core_axi_write_in_if_agent"}, interface_names[2]); + fuse_ctrl_core_axi_write_in_if_agent_config.initiator_responder = INITIATOR; + // fuse_ctrl_core_axi_write_in_if_agent_config.has_coverage = 1; + fuse_ctrl_core_axi_write_out_if_agent_config.initialize( interface_activity[3], {environment_path,".fuse_ctrl_core_axi_write_out_if_agent"}, interface_names[3]); + fuse_ctrl_core_axi_write_out_if_agent_config.initiator_responder = RESPONDER; + // fuse_ctrl_core_axi_write_out_if_agent_config.has_coverage = 1; + fuse_ctrl_prim_axi_write_in_if_agent_config.initialize( interface_activity[4], {environment_path,".fuse_ctrl_prim_axi_write_in_if_agent"}, interface_names[4]); + fuse_ctrl_prim_axi_write_in_if_agent_config.initiator_responder = INITIATOR; + // fuse_ctrl_prim_axi_write_in_if_agent_config.has_coverage = 1; + fuse_ctrl_prim_axi_write_out_if_agent_config.initialize( interface_activity[5], {environment_path,".fuse_ctrl_prim_axi_write_out_if_agent"}, interface_names[5]); + fuse_ctrl_prim_axi_write_out_if_agent_config.initiator_responder = RESPONDER; + // fuse_ctrl_prim_axi_write_out_if_agent_config.has_coverage = 1; + fuse_ctrl_core_axi_read_in_if_agent_config.initialize( interface_activity[6], {environment_path,".fuse_ctrl_core_axi_read_in_if_agent"}, interface_names[6]); + fuse_ctrl_core_axi_read_in_if_agent_config.initiator_responder = INITIATOR; + // fuse_ctrl_core_axi_read_in_if_agent_config.has_coverage = 1; + fuse_ctrl_core_axi_read_out_if_agent_config.initialize( interface_activity[7], {environment_path,".fuse_ctrl_core_axi_read_out_if_agent"}, interface_names[7]); + fuse_ctrl_core_axi_read_out_if_agent_config.initiator_responder = RESPONDER; + // fuse_ctrl_core_axi_read_out_if_agent_config.has_coverage = 1; + fuse_ctrl_prim_axi_read_in_if_agent_config.initialize( interface_activity[8], {environment_path,".fuse_ctrl_prim_axi_read_in_if_agent"}, interface_names[8]); + fuse_ctrl_prim_axi_read_in_if_agent_config.initiator_responder = INITIATOR; + // fuse_ctrl_prim_axi_read_in_if_agent_config.has_coverage = 1; + fuse_ctrl_prim_axi_read_out_if_agent_config.initialize( interface_activity[9], {environment_path,".fuse_ctrl_prim_axi_read_out_if_agent"}, interface_names[9]); + fuse_ctrl_prim_axi_read_out_if_agent_config.initiator_responder = RESPONDER; + // fuse_ctrl_prim_axi_read_out_if_agent_config.has_coverage = 1; + fuse_ctrl_secreg_axi_read_in_if_agent_config.initialize( interface_activity[10], {environment_path,".fuse_ctrl_secreg_axi_read_in_if_agent"}, interface_names[10]); + fuse_ctrl_secreg_axi_read_in_if_agent_config.initiator_responder = INITIATOR; + // fuse_ctrl_secreg_axi_read_in_if_agent_config.has_coverage = 1; + fuse_ctrl_secreg_axi_read_out_if_agent_config.initialize( interface_activity[11], {environment_path,".fuse_ctrl_secreg_axi_read_out_if_agent"}, interface_names[11]); + fuse_ctrl_secreg_axi_read_out_if_agent_config.initiator_responder = RESPONDER; + // fuse_ctrl_secreg_axi_read_out_if_agent_config.has_coverage = 1; + fuse_ctrl_lc_otp_in_if_agent_config.initialize( interface_activity[12], {environment_path,".fuse_ctrl_lc_otp_in_if_agent"}, interface_names[12]); + fuse_ctrl_lc_otp_in_if_agent_config.initiator_responder = INITIATOR; + // fuse_ctrl_lc_otp_in_if_agent_config.has_coverage = 1; + fuse_ctrl_lc_otp_out_if_agent_config.initialize( interface_activity[13], {environment_path,".fuse_ctrl_lc_otp_out_if_agent"}, interface_names[13]); + fuse_ctrl_lc_otp_out_if_agent_config.initiator_responder = RESPONDER; + // fuse_ctrl_lc_otp_out_if_agent_config.has_coverage = 1; + fuse_ctrl_in_if_agent_config.initialize( interface_activity[14], {environment_path,".fuse_ctrl_in_if_agent"}, interface_names[14]); + fuse_ctrl_in_if_agent_config.initiator_responder = INITIATOR; + // fuse_ctrl_in_if_agent_config.has_coverage = 1; + fuse_ctrl_out_if_agent_config.initialize( interface_activity[15], {environment_path,".fuse_ctrl_out_if_agent"}, interface_names[15]); + fuse_ctrl_out_if_agent_config.initiator_responder = RESPONDER; + // fuse_ctrl_out_if_agent_config.has_coverage = 1; + + + + + + // pragma uvmf custom initialize begin + // pragma uvmf custom initialize end + + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/environment_packages/fuse_ctrl_env_pkg/src/fuse_ctrl_env_sequence_base.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/environment_packages/fuse_ctrl_env_pkg/src/fuse_ctrl_env_sequence_base.svh new file mode 100644 index 0000000..ac7965f --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/environment_packages/fuse_ctrl_env_pkg/src/fuse_ctrl_env_sequence_base.svh @@ -0,0 +1,146 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains environment level sequences that will +// be reused from block to top level simulations. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_env_sequence_base #( + type CONFIG_T + ) extends uvmf_virtual_sequence_base #(.CONFIG_T(CONFIG_T)); + + + `uvm_object_param_utils( fuse_ctrl_env_sequence_base #( + CONFIG_T + ) ); + + +// This fuse_ctrl_env_sequence_base contains a handle to a fuse_ctrl_env_configuration object +// named configuration. This configuration variable contains a handle to each +// sequencer within each agent within this environment and any sub-environments. +// The configuration object handle is automatically assigned in the pre_body in the +// base class of this sequence. The configuration handle is retrieved from the +// virtual sequencer that this sequence is started on. +// Available sequencer handles within the environment configuration: + + // Initiator agent sequencers in fuse_ctrl_environment: + // configuration.fuse_ctrl_rst_in_agent_config.sequencer + // configuration.fuse_ctrl_core_axi_write_in_if_agent_config.sequencer + // configuration.fuse_ctrl_prim_axi_write_in_if_agent_config.sequencer + // configuration.fuse_ctrl_core_axi_read_in_if_agent_config.sequencer + // configuration.fuse_ctrl_prim_axi_read_in_if_agent_config.sequencer + // configuration.fuse_ctrl_secreg_axi_read_in_if_agent_config.sequencer + // configuration.fuse_ctrl_lc_otp_in_if_agent_config.sequencer + // configuration.fuse_ctrl_in_if_agent_config.sequencer + + // Responder agent sequencers in fuse_ctrl_environment: + // configuration.fuse_ctrl_rst_out_agent_config.sequencer + // configuration.fuse_ctrl_core_axi_write_out_if_agent_config.sequencer + // configuration.fuse_ctrl_prim_axi_write_out_if_agent_config.sequencer + // configuration.fuse_ctrl_core_axi_read_out_if_agent_config.sequencer + // configuration.fuse_ctrl_prim_axi_read_out_if_agent_config.sequencer + // configuration.fuse_ctrl_secreg_axi_read_out_if_agent_config.sequencer + // configuration.fuse_ctrl_lc_otp_out_if_agent_config.sequencer + // configuration.fuse_ctrl_out_if_agent_config.sequencer + + + typedef fuse_ctrl_rst_in_random_sequence fuse_ctrl_rst_in_agent_random_sequence_t; + fuse_ctrl_rst_in_agent_random_sequence_t fuse_ctrl_rst_in_agent_rand_seq; + + + typedef fuse_ctrl_core_axi_write_in_random_sequence fuse_ctrl_core_axi_write_in_if_agent_random_sequence_t; + fuse_ctrl_core_axi_write_in_if_agent_random_sequence_t fuse_ctrl_core_axi_write_in_if_agent_rand_seq; + + + typedef fuse_ctrl_prim_axi_write_in_random_sequence fuse_ctrl_prim_axi_write_in_if_agent_random_sequence_t; + fuse_ctrl_prim_axi_write_in_if_agent_random_sequence_t fuse_ctrl_prim_axi_write_in_if_agent_rand_seq; + + + typedef fuse_ctrl_core_axi_read_in_random_sequence fuse_ctrl_core_axi_read_in_if_agent_random_sequence_t; + fuse_ctrl_core_axi_read_in_if_agent_random_sequence_t fuse_ctrl_core_axi_read_in_if_agent_rand_seq; + + + typedef fuse_ctrl_prim_axi_read_in_random_sequence fuse_ctrl_prim_axi_read_in_if_agent_random_sequence_t; + fuse_ctrl_prim_axi_read_in_if_agent_random_sequence_t fuse_ctrl_prim_axi_read_in_if_agent_rand_seq; + + + typedef fuse_ctrl_secreg_axi_read_in_random_sequence fuse_ctrl_secreg_axi_read_in_if_agent_random_sequence_t; + fuse_ctrl_secreg_axi_read_in_if_agent_random_sequence_t fuse_ctrl_secreg_axi_read_in_if_agent_rand_seq; + + + typedef fuse_ctrl_lc_otp_in_random_sequence fuse_ctrl_lc_otp_in_if_agent_random_sequence_t; + fuse_ctrl_lc_otp_in_if_agent_random_sequence_t fuse_ctrl_lc_otp_in_if_agent_rand_seq; + + + typedef fuse_ctrl_in_random_sequence fuse_ctrl_in_if_agent_random_sequence_t; + fuse_ctrl_in_if_agent_random_sequence_t fuse_ctrl_in_if_agent_rand_seq; + + + + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "" ); + super.new(name); + fuse_ctrl_rst_in_agent_rand_seq = fuse_ctrl_rst_in_agent_random_sequence_t::type_id::create("fuse_ctrl_rst_in_agent_rand_seq"); + fuse_ctrl_core_axi_write_in_if_agent_rand_seq = fuse_ctrl_core_axi_write_in_if_agent_random_sequence_t::type_id::create("fuse_ctrl_core_axi_write_in_if_agent_rand_seq"); + fuse_ctrl_prim_axi_write_in_if_agent_rand_seq = fuse_ctrl_prim_axi_write_in_if_agent_random_sequence_t::type_id::create("fuse_ctrl_prim_axi_write_in_if_agent_rand_seq"); + fuse_ctrl_core_axi_read_in_if_agent_rand_seq = fuse_ctrl_core_axi_read_in_if_agent_random_sequence_t::type_id::create("fuse_ctrl_core_axi_read_in_if_agent_rand_seq"); + fuse_ctrl_prim_axi_read_in_if_agent_rand_seq = fuse_ctrl_prim_axi_read_in_if_agent_random_sequence_t::type_id::create("fuse_ctrl_prim_axi_read_in_if_agent_rand_seq"); + fuse_ctrl_secreg_axi_read_in_if_agent_rand_seq = fuse_ctrl_secreg_axi_read_in_if_agent_random_sequence_t::type_id::create("fuse_ctrl_secreg_axi_read_in_if_agent_rand_seq"); + fuse_ctrl_lc_otp_in_if_agent_rand_seq = fuse_ctrl_lc_otp_in_if_agent_random_sequence_t::type_id::create("fuse_ctrl_lc_otp_in_if_agent_rand_seq"); + fuse_ctrl_in_if_agent_rand_seq = fuse_ctrl_in_if_agent_random_sequence_t::type_id::create("fuse_ctrl_in_if_agent_rand_seq"); + + + endfunction + + virtual task body(); + + if ( configuration.fuse_ctrl_rst_in_agent_config.sequencer != null ) + repeat (25) fuse_ctrl_rst_in_agent_rand_seq.start(configuration.fuse_ctrl_rst_in_agent_config.sequencer); + if ( configuration.fuse_ctrl_core_axi_write_in_if_agent_config.sequencer != null ) + repeat (25) fuse_ctrl_core_axi_write_in_if_agent_rand_seq.start(configuration.fuse_ctrl_core_axi_write_in_if_agent_config.sequencer); + if ( configuration.fuse_ctrl_prim_axi_write_in_if_agent_config.sequencer != null ) + repeat (25) fuse_ctrl_prim_axi_write_in_if_agent_rand_seq.start(configuration.fuse_ctrl_prim_axi_write_in_if_agent_config.sequencer); + if ( configuration.fuse_ctrl_core_axi_read_in_if_agent_config.sequencer != null ) + repeat (25) fuse_ctrl_core_axi_read_in_if_agent_rand_seq.start(configuration.fuse_ctrl_core_axi_read_in_if_agent_config.sequencer); + if ( configuration.fuse_ctrl_prim_axi_read_in_if_agent_config.sequencer != null ) + repeat (25) fuse_ctrl_prim_axi_read_in_if_agent_rand_seq.start(configuration.fuse_ctrl_prim_axi_read_in_if_agent_config.sequencer); + if ( configuration.fuse_ctrl_secreg_axi_read_in_if_agent_config.sequencer != null ) + repeat (25) fuse_ctrl_secreg_axi_read_in_if_agent_rand_seq.start(configuration.fuse_ctrl_secreg_axi_read_in_if_agent_config.sequencer); + if ( configuration.fuse_ctrl_lc_otp_in_if_agent_config.sequencer != null ) + repeat (25) fuse_ctrl_lc_otp_in_if_agent_rand_seq.start(configuration.fuse_ctrl_lc_otp_in_if_agent_config.sequencer); + if ( configuration.fuse_ctrl_in_if_agent_config.sequencer != null ) + repeat (25) fuse_ctrl_in_if_agent_rand_seq.start(configuration.fuse_ctrl_in_if_agent_config.sequencer); + + + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/environment_packages/fuse_ctrl_env_pkg/src/fuse_ctrl_env_typedefs.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/environment_packages/fuse_ctrl_env_pkg/src/fuse_ctrl_env_typedefs.svh new file mode 100644 index 0000000..79d1b10 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/environment_packages/fuse_ctrl_env_pkg/src/fuse_ctrl_env_typedefs.svh @@ -0,0 +1,34 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the environment package. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + + // pragma uvmf custom additional begin + // pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/environment_packages/fuse_ctrl_env_pkg/src/fuse_ctrl_environment.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/environment_packages/fuse_ctrl_env_pkg/src/fuse_ctrl_environment.svh new file mode 100644 index 0000000..9221c4f --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/environment_packages/fuse_ctrl_env_pkg/src/fuse_ctrl_environment.svh @@ -0,0 +1,219 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This environment contains all agents, predictors and +// scoreboards required for the block level design. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class fuse_ctrl_environment extends uvmf_environment_base #( + .CONFIG_T( fuse_ctrl_env_configuration + )); + `uvm_component_utils( fuse_ctrl_environment ) + + + + + + typedef fuse_ctrl_rst_in_agent fuse_ctrl_rst_in_agent_t; + fuse_ctrl_rst_in_agent_t fuse_ctrl_rst_in_agent; + + typedef fuse_ctrl_rst_out_agent fuse_ctrl_rst_out_agent_t; + fuse_ctrl_rst_out_agent_t fuse_ctrl_rst_out_agent; + + typedef fuse_ctrl_core_axi_write_in_agent fuse_ctrl_core_axi_write_in_if_agent_t; + fuse_ctrl_core_axi_write_in_if_agent_t fuse_ctrl_core_axi_write_in_if_agent; + + typedef fuse_ctrl_core_axi_write_out_agent fuse_ctrl_core_axi_write_out_if_agent_t; + fuse_ctrl_core_axi_write_out_if_agent_t fuse_ctrl_core_axi_write_out_if_agent; + + typedef fuse_ctrl_prim_axi_write_in_agent fuse_ctrl_prim_axi_write_in_if_agent_t; + fuse_ctrl_prim_axi_write_in_if_agent_t fuse_ctrl_prim_axi_write_in_if_agent; + + typedef fuse_ctrl_prim_axi_write_out_agent fuse_ctrl_prim_axi_write_out_if_agent_t; + fuse_ctrl_prim_axi_write_out_if_agent_t fuse_ctrl_prim_axi_write_out_if_agent; + + typedef fuse_ctrl_core_axi_read_in_agent fuse_ctrl_core_axi_read_in_if_agent_t; + fuse_ctrl_core_axi_read_in_if_agent_t fuse_ctrl_core_axi_read_in_if_agent; + + typedef fuse_ctrl_core_axi_read_out_agent fuse_ctrl_core_axi_read_out_if_agent_t; + fuse_ctrl_core_axi_read_out_if_agent_t fuse_ctrl_core_axi_read_out_if_agent; + + typedef fuse_ctrl_prim_axi_read_in_agent fuse_ctrl_prim_axi_read_in_if_agent_t; + fuse_ctrl_prim_axi_read_in_if_agent_t fuse_ctrl_prim_axi_read_in_if_agent; + + typedef fuse_ctrl_prim_axi_read_out_agent fuse_ctrl_prim_axi_read_out_if_agent_t; + fuse_ctrl_prim_axi_read_out_if_agent_t fuse_ctrl_prim_axi_read_out_if_agent; + + typedef fuse_ctrl_secreg_axi_read_in_agent fuse_ctrl_secreg_axi_read_in_if_agent_t; + fuse_ctrl_secreg_axi_read_in_if_agent_t fuse_ctrl_secreg_axi_read_in_if_agent; + + typedef fuse_ctrl_secreg_axi_read_out_agent fuse_ctrl_secreg_axi_read_out_if_agent_t; + fuse_ctrl_secreg_axi_read_out_if_agent_t fuse_ctrl_secreg_axi_read_out_if_agent; + + typedef fuse_ctrl_lc_otp_in_agent fuse_ctrl_lc_otp_in_if_agent_t; + fuse_ctrl_lc_otp_in_if_agent_t fuse_ctrl_lc_otp_in_if_agent; + + typedef fuse_ctrl_lc_otp_out_agent fuse_ctrl_lc_otp_out_if_agent_t; + fuse_ctrl_lc_otp_out_if_agent_t fuse_ctrl_lc_otp_out_if_agent; + + typedef fuse_ctrl_in_agent fuse_ctrl_in_if_agent_t; + fuse_ctrl_in_if_agent_t fuse_ctrl_in_if_agent; + + typedef fuse_ctrl_out_agent fuse_ctrl_out_if_agent_t; + fuse_ctrl_out_if_agent_t fuse_ctrl_out_if_agent; + + + + + typedef fuse_ctrl_predictor #( + .CONFIG_T(CONFIG_T) + ) + fuse_ctrl_pred_t; + fuse_ctrl_pred_t fuse_ctrl_pred; + typedef fuse_ctrl_scoreboard #( + .CONFIG_T(CONFIG_T) + ) + fuse_ctrl_sb_t; + fuse_ctrl_sb_t fuse_ctrl_sb; + + + + + typedef uvmf_virtual_sequencer_base #(.CONFIG_T(fuse_ctrl_env_configuration)) fuse_ctrl_vsqr_t; + fuse_ctrl_vsqr_t vsqr; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// FUNCTION: build_phase() +// This function builds all components within this environment. +// + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + fuse_ctrl_rst_in_agent = fuse_ctrl_rst_in_agent_t::type_id::create("fuse_ctrl_rst_in_agent",this); + fuse_ctrl_rst_in_agent.set_config(configuration.fuse_ctrl_rst_in_agent_config); + fuse_ctrl_rst_out_agent = fuse_ctrl_rst_out_agent_t::type_id::create("fuse_ctrl_rst_out_agent",this); + fuse_ctrl_rst_out_agent.set_config(configuration.fuse_ctrl_rst_out_agent_config); + fuse_ctrl_core_axi_write_in_if_agent = fuse_ctrl_core_axi_write_in_if_agent_t::type_id::create("fuse_ctrl_core_axi_write_in_if_agent",this); + fuse_ctrl_core_axi_write_in_if_agent.set_config(configuration.fuse_ctrl_core_axi_write_in_if_agent_config); + fuse_ctrl_core_axi_write_out_if_agent = fuse_ctrl_core_axi_write_out_if_agent_t::type_id::create("fuse_ctrl_core_axi_write_out_if_agent",this); + fuse_ctrl_core_axi_write_out_if_agent.set_config(configuration.fuse_ctrl_core_axi_write_out_if_agent_config); + fuse_ctrl_prim_axi_write_in_if_agent = fuse_ctrl_prim_axi_write_in_if_agent_t::type_id::create("fuse_ctrl_prim_axi_write_in_if_agent",this); + fuse_ctrl_prim_axi_write_in_if_agent.set_config(configuration.fuse_ctrl_prim_axi_write_in_if_agent_config); + fuse_ctrl_prim_axi_write_out_if_agent = fuse_ctrl_prim_axi_write_out_if_agent_t::type_id::create("fuse_ctrl_prim_axi_write_out_if_agent",this); + fuse_ctrl_prim_axi_write_out_if_agent.set_config(configuration.fuse_ctrl_prim_axi_write_out_if_agent_config); + fuse_ctrl_core_axi_read_in_if_agent = fuse_ctrl_core_axi_read_in_if_agent_t::type_id::create("fuse_ctrl_core_axi_read_in_if_agent",this); + fuse_ctrl_core_axi_read_in_if_agent.set_config(configuration.fuse_ctrl_core_axi_read_in_if_agent_config); + fuse_ctrl_core_axi_read_out_if_agent = fuse_ctrl_core_axi_read_out_if_agent_t::type_id::create("fuse_ctrl_core_axi_read_out_if_agent",this); + fuse_ctrl_core_axi_read_out_if_agent.set_config(configuration.fuse_ctrl_core_axi_read_out_if_agent_config); + fuse_ctrl_prim_axi_read_in_if_agent = fuse_ctrl_prim_axi_read_in_if_agent_t::type_id::create("fuse_ctrl_prim_axi_read_in_if_agent",this); + fuse_ctrl_prim_axi_read_in_if_agent.set_config(configuration.fuse_ctrl_prim_axi_read_in_if_agent_config); + fuse_ctrl_prim_axi_read_out_if_agent = fuse_ctrl_prim_axi_read_out_if_agent_t::type_id::create("fuse_ctrl_prim_axi_read_out_if_agent",this); + fuse_ctrl_prim_axi_read_out_if_agent.set_config(configuration.fuse_ctrl_prim_axi_read_out_if_agent_config); + fuse_ctrl_secreg_axi_read_in_if_agent = fuse_ctrl_secreg_axi_read_in_if_agent_t::type_id::create("fuse_ctrl_secreg_axi_read_in_if_agent",this); + fuse_ctrl_secreg_axi_read_in_if_agent.set_config(configuration.fuse_ctrl_secreg_axi_read_in_if_agent_config); + fuse_ctrl_secreg_axi_read_out_if_agent = fuse_ctrl_secreg_axi_read_out_if_agent_t::type_id::create("fuse_ctrl_secreg_axi_read_out_if_agent",this); + fuse_ctrl_secreg_axi_read_out_if_agent.set_config(configuration.fuse_ctrl_secreg_axi_read_out_if_agent_config); + fuse_ctrl_lc_otp_in_if_agent = fuse_ctrl_lc_otp_in_if_agent_t::type_id::create("fuse_ctrl_lc_otp_in_if_agent",this); + fuse_ctrl_lc_otp_in_if_agent.set_config(configuration.fuse_ctrl_lc_otp_in_if_agent_config); + fuse_ctrl_lc_otp_out_if_agent = fuse_ctrl_lc_otp_out_if_agent_t::type_id::create("fuse_ctrl_lc_otp_out_if_agent",this); + fuse_ctrl_lc_otp_out_if_agent.set_config(configuration.fuse_ctrl_lc_otp_out_if_agent_config); + fuse_ctrl_in_if_agent = fuse_ctrl_in_if_agent_t::type_id::create("fuse_ctrl_in_if_agent",this); + fuse_ctrl_in_if_agent.set_config(configuration.fuse_ctrl_in_if_agent_config); + fuse_ctrl_out_if_agent = fuse_ctrl_out_if_agent_t::type_id::create("fuse_ctrl_out_if_agent",this); + fuse_ctrl_out_if_agent.set_config(configuration.fuse_ctrl_out_if_agent_config); + fuse_ctrl_pred = fuse_ctrl_pred_t::type_id::create("fuse_ctrl_pred",this); + fuse_ctrl_pred.configuration = configuration; + fuse_ctrl_sb = fuse_ctrl_sb_t::type_id::create("fuse_ctrl_sb",this); + fuse_ctrl_sb.configuration = configuration; + + vsqr = fuse_ctrl_vsqr_t::type_id::create("vsqr", this); + vsqr.set_config(configuration); + configuration.set_vsqr(vsqr); + + // pragma uvmf custom build_phase begin + // pragma uvmf custom build_phase end + endfunction + +// **************************************************************************** +// FUNCTION: connect_phase() +// This function makes all connections within this environment. Connections +// typically inclue agent to predictor, predictor to scoreboard and scoreboard +// to agent. +// + virtual function void connect_phase(uvm_phase phase); +// pragma uvmf custom connect_phase_pre_super begin +// pragma uvmf custom connect_phase_pre_super end + super.connect_phase(phase); + fuse_ctrl_rst_in_agent.monitored_ap.connect(fuse_ctrl_pred.fuse_ctrl_rst_in_agent_ae); + fuse_ctrl_core_axi_write_in_if_agent.monitored_ap.connect(fuse_ctrl_pred.fuse_ctrl_core_axi_write_in_agent_ae); + fuse_ctrl_core_axi_write_out_if_agent.monitored_ap.connect(fuse_ctrl_sb.fuse_ctrl_core_axi_write_in_agent_ae); + fuse_ctrl_core_axi_read_in_if_agent.monitored_ap.connect(fuse_ctrl_pred.fuse_ctrl_core_axi_read_in_agent_ae); + fuse_ctrl_core_axi_read_out_if_agent.monitored_ap.connect(fuse_ctrl_sb.fuse_ctrl_core_axi_read_in_agent_ae); + fuse_ctrl_prim_axi_write_in_if_agent.monitored_ap.connect(fuse_ctrl_pred.fuse_ctrl_prim_axi_write_in_agent_ae); + fuse_ctrl_prim_axi_write_out_if_agent.monitored_ap.connect(fuse_ctrl_sb.fuse_ctrl_prim_axi_write_in_agent_ae); + fuse_ctrl_prim_axi_read_in_if_agent.monitored_ap.connect(fuse_ctrl_pred.fuse_ctrl_prim_axi_read_in_agent_ae); + fuse_ctrl_prim_axi_read_out_if_agent.monitored_ap.connect(fuse_ctrl_sb.fuse_ctrl_prim_axi_read_in_agent_ae); + fuse_ctrl_secreg_axi_read_in_if_agent.monitored_ap.connect(fuse_ctrl_pred.fuse_ctrl_secreg_axi_read_in_agent_ae); + fuse_ctrl_secreg_axi_read_out_if_agent.monitored_ap.connect(fuse_ctrl_sb.fuse_ctrl_secreg_axi_read_in_agent_ae); + fuse_ctrl_lc_otp_in_if_agent.monitored_ap.connect(fuse_ctrl_pred.fuse_ctrl_lc_otp_in_agent_ae); + fuse_ctrl_lc_otp_out_if_agent.monitored_ap.connect(fuse_ctrl_sb.fuse_ctrl_lc_otp_in_agent_ae); + fuse_ctrl_in_if_agent.monitored_ap.connect(fuse_ctrl_pred.fuse_ctrl_in_agent_ae); + fuse_ctrl_out_if_agent.monitored_ap.connect(fuse_ctrl_sb.fuse_ctrl_in_agent_ae); + // pragma uvmf custom reg_model_connect_phase begin + // pragma uvmf custom reg_model_connect_phase end + endfunction + +// **************************************************************************** +// FUNCTION: end_of_simulation_phase() +// This function is executed just prior to executing run_phase. This function +// was added to the environment to sample environment configuration settings +// just before the simulation exits time 0. The configuration structure is +// randomized in the build phase before the environment structure is constructed. +// Configuration variables can be customized after randomization in the build_phase +// of the extended test. +// If a sequence modifies values in the configuration structure then the sequence is +// responsible for sampling the covergroup in the configuration if required. +// + virtual function void start_of_simulation_phase(uvm_phase phase); + configuration.fuse_ctrl_configuration_cg.sample(); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/environment_packages/fuse_ctrl_env_pkg/src/fuse_ctrl_predictor.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/environment_packages/fuse_ctrl_env_pkg/src/fuse_ctrl_predictor.svh new file mode 100644 index 0000000..c5bfc1c --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/environment_packages/fuse_ctrl_env_pkg/src/fuse_ctrl_predictor.svh @@ -0,0 +1,425 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// +// DESCRIPTION: This analysis component contains analysis_exports for receiving +// data and analysis_ports for sending data. +// +// This analysis component has the following analysis_exports that receive the +// listed transaction type. +// +// fuse_ctrl_rst_in_agent_ae receives transactions of type fuse_ctrl_rst_in_transaction +// fuse_ctrl_core_axi_write_in_agent_ae receives transactions of type fuse_ctrl_core_axi_write_in_transaction +// fuse_ctrl_prim_axi_write_in_agent_ae receives transactions of type fuse_ctrl_prim_axi_write_in_transaction +// fuse_ctrl_core_axi_read_in_agent_ae receives transactions of type fuse_ctrl_core_axi_read_in_transaction +// fuse_ctrl_prim_axi_read_in_agent_ae receives transactions of type fuse_ctrl_prim_axi_read_in_transaction +// fuse_ctrl_secreg_axi_read_in_agent_ae receives transactions of type fuse_ctrl_secreg_axi_read_in_transaction +// fuse_ctrl_lc_otp_in_agent_ae receives transactions of type fuse_ctrl_lc_otp_in_transaction +// fuse_ctrl_in_agent_ae receives transactions of type fuse_ctrl_in_transaction +// +// This analysis component has the following analysis_ports that can broadcast +// the listed transaction type. +// +// fuse_ctrl_rst_in_agent_ap broadcasts transactions of type fuse_ctrl_rst_in_transaction +// fuse_ctrl_core_axi_write_in_agent_ap broadcasts transactions of type fuse_ctrl_core_axi_write_in_transaction +// fuse_ctrl_prim_axi_write_in_agent_ap broadcasts transactions of type fuse_ctrl_prim_axi_write_in_transaction +// fuse_ctrl_core_axi_read_in_agent_ap broadcasts transactions of type fuse_ctrl_core_axi_read_in_transaction +// fuse_ctrl_prim_axi_read_in_agent_ap broadcasts transactions of type fuse_ctrl_prim_axi_read_in_transaction +// fuse_ctrl_secreg_axi_read_in_agent_ap broadcasts transactions of type fuse_ctrl_secreg_axi_read_in_transaction +// fuse_ctrl_lc_otp_in_agent_ap broadcasts transactions of type fuse_ctrl_lc_otp_in_transaction +// fuse_ctrl_in_agent_ap broadcasts transactions of type fuse_ctrl_in_transaction +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class fuse_ctrl_predictor #( + type CONFIG_T, + type BASE_T = uvm_component + ) + extends BASE_T; + + // Factory registration of this class + `uvm_component_param_utils( fuse_ctrl_predictor #( + CONFIG_T, + BASE_T + ) +) + + + // Instantiate a handle to the configuration of the environment in which this component resides + CONFIG_T configuration; + + + // Instantiate the analysis exports + uvm_analysis_imp_fuse_ctrl_rst_in_agent_ae #(fuse_ctrl_rst_in_transaction, fuse_ctrl_predictor #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + ) +) fuse_ctrl_rst_in_agent_ae; + uvm_analysis_imp_fuse_ctrl_core_axi_write_in_agent_ae #(fuse_ctrl_core_axi_write_in_transaction, fuse_ctrl_predictor #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + ) +) fuse_ctrl_core_axi_write_in_agent_ae; + uvm_analysis_imp_fuse_ctrl_prim_axi_write_in_agent_ae #(fuse_ctrl_prim_axi_write_in_transaction, fuse_ctrl_predictor #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + ) +) fuse_ctrl_prim_axi_write_in_agent_ae; + uvm_analysis_imp_fuse_ctrl_core_axi_read_in_agent_ae #(fuse_ctrl_core_axi_read_in_transaction, fuse_ctrl_predictor #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + ) +) fuse_ctrl_core_axi_read_in_agent_ae; + uvm_analysis_imp_fuse_ctrl_prim_axi_read_in_agent_ae #(fuse_ctrl_prim_axi_read_in_transaction, fuse_ctrl_predictor #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + ) +) fuse_ctrl_prim_axi_read_in_agent_ae; + uvm_analysis_imp_fuse_ctrl_secreg_axi_read_in_agent_ae #(fuse_ctrl_secreg_axi_read_in_transaction, fuse_ctrl_predictor #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + ) +) fuse_ctrl_secreg_axi_read_in_agent_ae; + uvm_analysis_imp_fuse_ctrl_lc_otp_in_agent_ae #(fuse_ctrl_lc_otp_in_transaction, fuse_ctrl_predictor #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + ) +) fuse_ctrl_lc_otp_in_agent_ae; + uvm_analysis_imp_fuse_ctrl_in_agent_ae #(fuse_ctrl_in_transaction, fuse_ctrl_predictor #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + ) +) fuse_ctrl_in_agent_ae; + + + // Instantiate the analysis ports + uvm_analysis_port #(fuse_ctrl_rst_in_transaction) fuse_ctrl_rst_in_agent_ap; + uvm_analysis_port #(fuse_ctrl_core_axi_write_in_transaction) fuse_ctrl_core_axi_write_in_agent_ap; + uvm_analysis_port #(fuse_ctrl_prim_axi_write_in_transaction) fuse_ctrl_prim_axi_write_in_agent_ap; + uvm_analysis_port #(fuse_ctrl_core_axi_read_in_transaction) fuse_ctrl_core_axi_read_in_agent_ap; + uvm_analysis_port #(fuse_ctrl_prim_axi_read_in_transaction) fuse_ctrl_prim_axi_read_in_agent_ap; + uvm_analysis_port #(fuse_ctrl_secreg_axi_read_in_transaction) fuse_ctrl_secreg_axi_read_in_agent_ap; + uvm_analysis_port #(fuse_ctrl_lc_otp_in_transaction) fuse_ctrl_lc_otp_in_agent_ap; + uvm_analysis_port #(fuse_ctrl_in_transaction) fuse_ctrl_in_agent_ap; + + + // Transaction variable for predicted values to be sent out fuse_ctrl_rst_in_agent_ap + // Once a transaction is sent through an analysis_port, another transaction should + // be constructed for the next predicted transaction. + typedef fuse_ctrl_rst_in_transaction fuse_ctrl_rst_in_agent_ap_output_transaction_t; + fuse_ctrl_rst_in_agent_ap_output_transaction_t fuse_ctrl_rst_in_agent_ap_output_transaction; + // Code for sending output transaction out through fuse_ctrl_rst_in_agent_ap + // fuse_ctrl_rst_in_agent_ap.write(fuse_ctrl_rst_in_agent_ap_output_transaction); + // Transaction variable for predicted values to be sent out fuse_ctrl_core_axi_write_in_agent_ap + // Once a transaction is sent through an analysis_port, another transaction should + // be constructed for the next predicted transaction. + typedef fuse_ctrl_core_axi_write_in_transaction fuse_ctrl_core_axi_write_in_agent_ap_output_transaction_t; + fuse_ctrl_core_axi_write_in_agent_ap_output_transaction_t fuse_ctrl_core_axi_write_in_agent_ap_output_transaction; + // Code for sending output transaction out through fuse_ctrl_core_axi_write_in_agent_ap + // fuse_ctrl_core_axi_write_in_agent_ap.write(fuse_ctrl_core_axi_write_in_agent_ap_output_transaction); + // Transaction variable for predicted values to be sent out fuse_ctrl_prim_axi_write_in_agent_ap + // Once a transaction is sent through an analysis_port, another transaction should + // be constructed for the next predicted transaction. + typedef fuse_ctrl_prim_axi_write_in_transaction fuse_ctrl_prim_axi_write_in_agent_ap_output_transaction_t; + fuse_ctrl_prim_axi_write_in_agent_ap_output_transaction_t fuse_ctrl_prim_axi_write_in_agent_ap_output_transaction; + // Code for sending output transaction out through fuse_ctrl_prim_axi_write_in_agent_ap + // fuse_ctrl_prim_axi_write_in_agent_ap.write(fuse_ctrl_prim_axi_write_in_agent_ap_output_transaction); + // Transaction variable for predicted values to be sent out fuse_ctrl_core_axi_read_in_agent_ap + // Once a transaction is sent through an analysis_port, another transaction should + // be constructed for the next predicted transaction. + typedef fuse_ctrl_core_axi_read_in_transaction fuse_ctrl_core_axi_read_in_agent_ap_output_transaction_t; + fuse_ctrl_core_axi_read_in_agent_ap_output_transaction_t fuse_ctrl_core_axi_read_in_agent_ap_output_transaction; + // Code for sending output transaction out through fuse_ctrl_core_axi_read_in_agent_ap + // fuse_ctrl_core_axi_read_in_agent_ap.write(fuse_ctrl_core_axi_read_in_agent_ap_output_transaction); + // Transaction variable for predicted values to be sent out fuse_ctrl_prim_axi_read_in_agent_ap + // Once a transaction is sent through an analysis_port, another transaction should + // be constructed for the next predicted transaction. + typedef fuse_ctrl_prim_axi_read_in_transaction fuse_ctrl_prim_axi_read_in_agent_ap_output_transaction_t; + fuse_ctrl_prim_axi_read_in_agent_ap_output_transaction_t fuse_ctrl_prim_axi_read_in_agent_ap_output_transaction; + // Code for sending output transaction out through fuse_ctrl_prim_axi_read_in_agent_ap + // fuse_ctrl_prim_axi_read_in_agent_ap.write(fuse_ctrl_prim_axi_read_in_agent_ap_output_transaction); + // Transaction variable for predicted values to be sent out fuse_ctrl_secreg_axi_read_in_agent_ap + // Once a transaction is sent through an analysis_port, another transaction should + // be constructed for the next predicted transaction. + typedef fuse_ctrl_secreg_axi_read_in_transaction fuse_ctrl_secreg_axi_read_in_agent_ap_output_transaction_t; + fuse_ctrl_secreg_axi_read_in_agent_ap_output_transaction_t fuse_ctrl_secreg_axi_read_in_agent_ap_output_transaction; + // Code for sending output transaction out through fuse_ctrl_secreg_axi_read_in_agent_ap + // fuse_ctrl_secreg_axi_read_in_agent_ap.write(fuse_ctrl_secreg_axi_read_in_agent_ap_output_transaction); + // Transaction variable for predicted values to be sent out fuse_ctrl_lc_otp_in_agent_ap + // Once a transaction is sent through an analysis_port, another transaction should + // be constructed for the next predicted transaction. + typedef fuse_ctrl_lc_otp_in_transaction fuse_ctrl_lc_otp_in_agent_ap_output_transaction_t; + fuse_ctrl_lc_otp_in_agent_ap_output_transaction_t fuse_ctrl_lc_otp_in_agent_ap_output_transaction; + // Code for sending output transaction out through fuse_ctrl_lc_otp_in_agent_ap + // fuse_ctrl_lc_otp_in_agent_ap.write(fuse_ctrl_lc_otp_in_agent_ap_output_transaction); + // Transaction variable for predicted values to be sent out fuse_ctrl_in_agent_ap + // Once a transaction is sent through an analysis_port, another transaction should + // be constructed for the next predicted transaction. + typedef fuse_ctrl_in_transaction fuse_ctrl_in_agent_ap_output_transaction_t; + fuse_ctrl_in_agent_ap_output_transaction_t fuse_ctrl_in_agent_ap_output_transaction; + // Code for sending output transaction out through fuse_ctrl_in_agent_ap + // fuse_ctrl_in_agent_ap.write(fuse_ctrl_in_agent_ap_output_transaction); + + // Define transaction handles for debug visibility + fuse_ctrl_rst_in_transaction fuse_ctrl_rst_in_agent_ae_debug; + fuse_ctrl_core_axi_write_in_transaction fuse_ctrl_core_axi_write_in_agent_ae_debug; + fuse_ctrl_prim_axi_write_in_transaction fuse_ctrl_prim_axi_write_in_agent_ae_debug; + fuse_ctrl_core_axi_read_in_transaction fuse_ctrl_core_axi_read_in_agent_ae_debug; + fuse_ctrl_prim_axi_read_in_transaction fuse_ctrl_prim_axi_read_in_agent_ae_debug; + fuse_ctrl_secreg_axi_read_in_transaction fuse_ctrl_secreg_axi_read_in_agent_ae_debug; + fuse_ctrl_lc_otp_in_transaction fuse_ctrl_lc_otp_in_agent_ae_debug; + fuse_ctrl_in_transaction fuse_ctrl_in_agent_ae_debug; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // FUNCTION: new + function new(string name, uvm_component parent); + super.new(name,parent); + `uvm_warning("PREDICTOR_REVIEW", "This predictor has been created either through generation or re-generation with merging. Remove this warning after the predictor has been reviewed.") + // pragma uvmf custom new begin + // pragma uvmf custom new end + endfunction + + // FUNCTION: build_phase + virtual function void build_phase (uvm_phase phase); + + fuse_ctrl_rst_in_agent_ae = new("fuse_ctrl_rst_in_agent_ae", this); + fuse_ctrl_core_axi_write_in_agent_ae = new("fuse_ctrl_core_axi_write_in_agent_ae", this); + fuse_ctrl_prim_axi_write_in_agent_ae = new("fuse_ctrl_prim_axi_write_in_agent_ae", this); + fuse_ctrl_core_axi_read_in_agent_ae = new("fuse_ctrl_core_axi_read_in_agent_ae", this); + fuse_ctrl_prim_axi_read_in_agent_ae = new("fuse_ctrl_prim_axi_read_in_agent_ae", this); + fuse_ctrl_secreg_axi_read_in_agent_ae = new("fuse_ctrl_secreg_axi_read_in_agent_ae", this); + fuse_ctrl_lc_otp_in_agent_ae = new("fuse_ctrl_lc_otp_in_agent_ae", this); + fuse_ctrl_in_agent_ae = new("fuse_ctrl_in_agent_ae", this); + fuse_ctrl_rst_in_agent_ap =new("fuse_ctrl_rst_in_agent_ap", this ); + fuse_ctrl_core_axi_write_in_agent_ap =new("fuse_ctrl_core_axi_write_in_agent_ap", this ); + fuse_ctrl_prim_axi_write_in_agent_ap =new("fuse_ctrl_prim_axi_write_in_agent_ap", this ); + fuse_ctrl_core_axi_read_in_agent_ap =new("fuse_ctrl_core_axi_read_in_agent_ap", this ); + fuse_ctrl_prim_axi_read_in_agent_ap =new("fuse_ctrl_prim_axi_read_in_agent_ap", this ); + fuse_ctrl_secreg_axi_read_in_agent_ap =new("fuse_ctrl_secreg_axi_read_in_agent_ap", this ); + fuse_ctrl_lc_otp_in_agent_ap =new("fuse_ctrl_lc_otp_in_agent_ap", this ); + fuse_ctrl_in_agent_ap =new("fuse_ctrl_in_agent_ap", this ); + // pragma uvmf custom build_phase begin + // pragma uvmf custom build_phase end + endfunction + + // FUNCTION: write_fuse_ctrl_rst_in_agent_ae + // Transactions received through fuse_ctrl_rst_in_agent_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_fuse_ctrl_rst_in_agent_ae(fuse_ctrl_rst_in_transaction t); + // pragma uvmf custom fuse_ctrl_rst_in_agent_ae_predictor begin + fuse_ctrl_rst_in_agent_ae_debug = t; + `uvm_info("PRED", "Transaction Received through fuse_ctrl_rst_in_agent_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // Construct one of each output transaction type. + fuse_ctrl_rst_in_agent_ap_output_transaction = fuse_ctrl_rst_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_rst_in_agent_ap_output_transaction"); + // UVMF_CHANGE_ME: Implement predictor model here. + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "UVMF_CHANGE_ME: The fuse_ctrl_predictor::write_fuse_ctrl_rst_in_agent_ae function needs to be completed with DUT prediction model",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + + // Code for sending output transaction out through fuse_ctrl_sb_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_rst_in_agent_ap.write(fuse_ctrl_rst_in_agent_ap_output_transaction); + // pragma uvmf custom fuse_ctrl_rst_in_agent_ae_predictor end + endfunction + + // FUNCTION: write_fuse_ctrl_core_axi_write_in_agent_ae + // Transactions received through fuse_ctrl_core_axi_write_in_agent_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_fuse_ctrl_core_axi_write_in_agent_ae(fuse_ctrl_core_axi_write_in_transaction t); + // pragma uvmf custom fuse_ctrl_core_axi_write_in_agent_ae_predictor begin + fuse_ctrl_core_axi_write_in_agent_ae_debug = t; + `uvm_info("PRED", "Transaction Received through fuse_ctrl_core_axi_write_in_agent_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // Construct one of each output transaction type. + fuse_ctrl_core_axi_write_in_agent_ap_output_transaction = fuse_ctrl_core_axi_write_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_core_axi_write_in_agent_ap_output_transaction"); + // UVMF_CHANGE_ME: Implement predictor model here. + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "UVMF_CHANGE_ME: The fuse_ctrl_predictor::write_fuse_ctrl_core_axi_write_in_agent_ae function needs to be completed with DUT prediction model",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + + // Code for sending output transaction out through fuse_ctrl_sb_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_core_axi_write_in_agent_ap.write(fuse_ctrl_core_axi_write_in_agent_ap_output_transaction); + // pragma uvmf custom fuse_ctrl_core_axi_write_in_agent_ae_predictor end + endfunction + + // FUNCTION: write_fuse_ctrl_prim_axi_write_in_agent_ae + // Transactions received through fuse_ctrl_prim_axi_write_in_agent_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_fuse_ctrl_prim_axi_write_in_agent_ae(fuse_ctrl_prim_axi_write_in_transaction t); + // pragma uvmf custom fuse_ctrl_prim_axi_write_in_agent_ae_predictor begin + fuse_ctrl_prim_axi_write_in_agent_ae_debug = t; + `uvm_info("PRED", "Transaction Received through fuse_ctrl_prim_axi_write_in_agent_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // Construct one of each output transaction type. + fuse_ctrl_prim_axi_write_in_agent_ap_output_transaction = fuse_ctrl_prim_axi_write_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_prim_axi_write_in_agent_ap_output_transaction"); + // UVMF_CHANGE_ME: Implement predictor model here. + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "UVMF_CHANGE_ME: The fuse_ctrl_predictor::write_fuse_ctrl_prim_axi_write_in_agent_ae function needs to be completed with DUT prediction model",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + + // Code for sending output transaction out through fuse_ctrl_sb_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_prim_xi_write_in_agent_ap.write(fuse_ctrl_prim_axi_write_in_agent_ap_output_transaction); + // pragma uvmf custom fuse_ctrl_prim_axi_write_in_agent_ae_predictor end + endfunction + + // FUNCTION: write_fuse_ctrl_core_axi_read_in_agent_ae + // Transactions received through fuse_ctrl_core_axi_read_in_agent_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_fuse_ctrl_core_axi_read_in_agent_ae(fuse_ctrl_core_axi_read_in_transaction t); + // pragma uvmf custom fuse_ctrl_core_axi_read_in_agent_ae_predictor begin + fuse_ctrl_core_axi_read_in_agent_ae_debug = t; + `uvm_info("PRED", "Transaction Received through fuse_ctrl_core_axi_read_in_agent_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // Construct one of each output transaction type. + fuse_ctrl_core_axi_read_in_agent_ap_output_transaction = fuse_ctrl_core_axi_read_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_core_axi_read_in_agent_ap_output_transaction"); + // UVMF_CHANGE_ME: Implement predictor model here. + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "UVMF_CHANGE_ME: The fuse_ctrl_predictor::write_fuse_ctrl_core_axi_read_in_agent_ae function needs to be completed with DUT prediction model",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + + // Code for sending output transaction out through fuse_ctrl_sb_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_core_axi_read_in_agent_ap.write(fuse_ctrl_core_axi_read_in_agent_ap_output_transaction); + // pragma uvmf custom fuse_ctrl_core_axi_read_in_agent_ae_predictor end + endfunction + + // FUNCTION: write_fuse_ctrl_prim_axi_read_in_agent_ae + // Transactions received through fuse_ctrl_prim_axi_read_in_agent_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_fuse_ctrl_prim_axi_read_in_agent_ae(fuse_ctrl_prim_axi_read_in_transaction t); + // pragma uvmf custom fuse_ctrl_prim_axi_read_in_agent_ae_predictor begin + fuse_ctrl_prim_axi_read_in_agent_ae_debug = t; + `uvm_info("PRED", "Transaction Received through fuse_ctrl_prim_axi_read_in_agent_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // Construct one of each output transaction type. + fuse_ctrl_prim_axi_read_in_agent_ap_output_transaction = fuse_ctrl_prim_axi_read_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_prim_axi_read_in_agent_ap_output_transaction"); + // UVMF_CHANGE_ME: Implement predictor model here. + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "UVMF_CHANGE_ME: The fuse_ctrl_predictor::write_fuse_ctrl_prim_axi_read_in_agent_ae function needs to be completed with DUT prediction model",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + + // Code for sending output transaction out through fuse_ctrl_sb_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_prim_axi_read_in_agent_ap.write(fuse_ctrl_prim_axi_read_in_agent_ap_output_transaction); + // pragma uvmf custom fuse_ctrl_prim_axi_read_in_agent_ae_predictor end + endfunction + + // FUNCTION: write_fuse_ctrl_secreg_axi_read_in_agent_ae + // Transactions received through fuse_ctrl_secreg_axi_read_in_agent_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_fuse_ctrl_secreg_axi_read_in_agent_ae(fuse_ctrl_secreg_axi_read_in_transaction t); + // pragma uvmf custom fuse_ctrl_secreg_axi_read_in_agent_ae_predictor begin + fuse_ctrl_secreg_axi_read_in_agent_ae_debug = t; + `uvm_info("PRED", "Transaction Received through fuse_ctrl_secreg_axi_read_in_agent_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // Construct one of each output transaction type. + fuse_ctrl_secreg_axi_read_in_agent_ap_output_transaction = fuse_ctrl_secreg_axi_read_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_secreg_axi_read_in_agent_ap_output_transaction"); + // UVMF_CHANGE_ME: Implement predictor model here. + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "UVMF_CHANGE_ME: The fuse_ctrl_predictor::write_fuse_ctrl_secreg_axi_read_in_agent_ae function needs to be completed with DUT prediction model",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + + // Code for sending output transaction out through fuse_ctrl_sb_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_secreg_axi_read_in_agent_ap.write(fuse_ctrl_secreg_axi_read_in_agent_ap_output_transaction); + // pragma uvmf custom fuse_ctrl_secreg_axi_read_in_agent_ae_predictor end + endfunction + + // FUNCTION: write_fuse_ctrl_lc_otp_in_agent_ae + // Transactions received through fuse_ctrl_lc_otp_in_agent_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_fuse_ctrl_lc_otp_in_agent_ae(fuse_ctrl_lc_otp_in_transaction t); + // pragma uvmf custom fuse_ctrl_lc_otp_in_agent_ae_predictor begin + fuse_ctrl_lc_otp_in_agent_ae_debug = t; + `uvm_info("PRED", "Transaction Received through fuse_ctrl_lc_otp_in_agent_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // Construct one of each output transaction type. + fuse_ctrl_lc_otp_in_agent_ap_output_transaction = fuse_ctrl_lc_otp_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_lc_otp_in_agent_ap_output_transaction"); + // UVMF_CHANGE_ME: Implement predictor model here. + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "UVMF_CHANGE_ME: The fuse_ctrl_predictor::write_fuse_ctrl_lc_otp_in_agent_ae function needs to be completed with DUT prediction model",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + + // Code for sending output transaction out through fuse_ctrl_sb_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_lc_otp_in_agent_ap.write(fuse_ctrl_lc_otp_in_agent_ap_output_transaction); + // pragma uvmf custom fuse_ctrl_lc_otp_in_agent_ae_predictor end + endfunction + + // FUNCTION: write_fuse_ctrl_in_agent_ae + // Transactions received through fuse_ctrl_in_agent_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_fuse_ctrl_in_agent_ae(fuse_ctrl_in_transaction t); + // pragma uvmf custom fuse_ctrl_in_agent_ae_predictor begin + fuse_ctrl_in_agent_ae_debug = t; + `uvm_info("PRED", "Transaction Received through fuse_ctrl_in_agent_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // Construct one of each output transaction type. + fuse_ctrl_in_agent_ap_output_transaction = fuse_ctrl_in_agent_ap_output_transaction_t::type_id::create("fuse_ctrl_in_agent_ap_output_transaction"); + // UVMF_CHANGE_ME: Implement predictor model here. + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "UVMF_CHANGE_ME: The fuse_ctrl_predictor::write_fuse_ctrl_in_agent_ae function needs to be completed with DUT prediction model",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + + // Code for sending output transaction out through fuse_ctrl_sb_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + fuse_ctrl_in_agent_ap.write(fuse_ctrl_in_agent_ap_output_transaction); + // pragma uvmf custom fuse_ctrl_in_agent_ae_predictor end + endfunction + + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/environment_packages/fuse_ctrl_env_pkg/src/fuse_ctrl_scoreboard.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/environment_packages/fuse_ctrl_env_pkg/src/fuse_ctrl_scoreboard.svh new file mode 100644 index 0000000..c72a452 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/environment_packages/fuse_ctrl_env_pkg/src/fuse_ctrl_scoreboard.svh @@ -0,0 +1,281 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This analysis component contains analysis_exports for receiving +// data and analysis_ports for sending data. +// +// This analysis component has the following analysis_exports that receive the +// listed transaction type. +// +// fuse_ctrl_rst_in_agent_ae receives transactions of type fuse_ctrl_rst_in_transaction +// fuse_ctrl_core_axi_write_in_agent_ae receives transactions of type fuse_ctrl_core_axi_write_in_transaction +// fuse_ctrl_prim_axi_write_in_agent_ae receives transactions of type fuse_ctrl_prim_axi_write_in_transaction +// fuse_ctrl_core_axi_read_in_agent_ae receives transactions of type fuse_ctrl_core_axi_read_in_transaction +// fuse_ctrl_prim_axi_read_in_agent_ae receives transactions of type fuse_ctrl_prim_axi_read_in_transaction +// fuse_ctrl_secreg_axi_read_in_agent_ae receives transactions of type fuse_ctrl_secreg_axi_read_in_transaction +// fuse_ctrl_lc_otp_in_agent_ae receives transactions of type fuse_ctrl_lc_otp_in_transaction +// fuse_ctrl_in_agent_ae receives transactions of type fuse_ctrl_in_transaction +// +// This analysis component has the following analysis_ports that can broadcast +// the listed transaction type. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + +class fuse_ctrl_scoreboard #( + type CONFIG_T, + type BASE_T = uvm_component + ) + extends BASE_T; + + // Factory registration of this class + `uvm_component_param_utils( fuse_ctrl_scoreboard #( + CONFIG_T, + BASE_T + ) +) + + + // Instantiate a handle to the configuration of the environment in which this component resides + CONFIG_T configuration; + + + // Instantiate the analysis exports + uvm_analysis_imp_fuse_ctrl_rst_in_agent_ae #(fuse_ctrl_rst_in_transaction, fuse_ctrl_scoreboard #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + ) +) fuse_ctrl_rst_in_agent_ae; + uvm_analysis_imp_fuse_ctrl_core_axi_write_in_agent_ae #(fuse_ctrl_core_axi_write_in_transaction, fuse_ctrl_scoreboard #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + ) +) fuse_ctrl_core_axi_write_in_agent_ae; + uvm_analysis_imp_fuse_ctrl_prim_axi_write_in_agent_ae #(fuse_ctrl_prim_axi_write_in_transaction, fuse_ctrl_scoreboard #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + ) +) fuse_ctrl_prim_axi_write_in_agent_ae; + uvm_analysis_imp_fuse_ctrl_core_axi_read_in_agent_ae #(fuse_ctrl_core_axi_read_in_transaction, fuse_ctrl_scoreboard #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + ) +) fuse_ctrl_core_axi_read_in_agent_ae; + uvm_analysis_imp_fuse_ctrl_prim_axi_read_in_agent_ae #(fuse_ctrl_prim_axi_read_in_transaction, fuse_ctrl_scoreboard #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + ) +) fuse_ctrl_prim_axi_read_in_agent_ae; + uvm_analysis_imp_fuse_ctrl_secreg_axi_read_in_agent_ae #(fuse_ctrl_secreg_axi_read_in_transaction, fuse_ctrl_scoreboard #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + ) +) fuse_ctrl_secreg_axi_read_in_agent_ae; + uvm_analysis_imp_fuse_ctrl_lc_otp_in_agent_ae #(fuse_ctrl_lc_otp_in_transaction, fuse_ctrl_scoreboard #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + ) +) fuse_ctrl_lc_otp_in_agent_ae; + uvm_analysis_imp_fuse_ctrl_in_agent_ae #(fuse_ctrl_in_transaction, fuse_ctrl_scoreboard #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + ) +) fuse_ctrl_in_agent_ae; + + + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // FUNCTION: new + function new(string name, uvm_component parent); + super.new(name,parent); + // pragma uvmf custom new begin + // pragma uvmf custom new end + endfunction + + // FUNCTION: build_phase + virtual function void build_phase (uvm_phase phase); + + fuse_ctrl_rst_in_agent_ae = new("fuse_ctrl_rst_in_agent_ae", this); + fuse_ctrl_core_axi_write_in_agent_ae = new("fuse_ctrl_core_axi_write_in_agent_ae", this); + fuse_ctrl_prim_axi_write_in_agent_ae = new("fuse_ctrl_prim_axi_write_in_agent_ae", this); + fuse_ctrl_core_axi_read_in_agent_ae = new("fuse_ctrl_core_axi_read_in_agent_ae", this); + fuse_ctrl_prim_axi_read_in_agent_ae = new("fuse_ctrl_prim_axi_read_in_agent_ae", this); + fuse_ctrl_secreg_axi_read_in_agent_ae = new("fuse_ctrl_secreg_axi_read_in_agent_ae", this); + fuse_ctrl_lc_otp_in_agent_ae = new("fuse_ctrl_lc_otp_in_agent_ae", this); + fuse_ctrl_in_agent_ae = new("fuse_ctrl_in_agent_ae", this); + // pragma uvmf custom build_phase begin + // pragma uvmf custom build_phase end + endfunction + + // FUNCTION: write_fuse_ctrl_rst_in_agent_ae + // Transactions received through fuse_ctrl_rst_in_agent_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_fuse_ctrl_rst_in_agent_ae(fuse_ctrl_rst_in_transaction t); + // pragma uvmf custom fuse_ctrl_rst_in_agent_ae_scoreboard begin + `uvm_info("PRED", "Transaction Received through fuse_ctrl_rst_in_agent_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // UVMF_CHANGE_ME: Implement custom scoreboard here. + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "UVMF_CHANGE_ME: The fuse_ctrl_scoreboard::write_fuse_ctrl_rst_in_agent_ae function needs to be completed with custom scoreboard functionality",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + + // pragma uvmf custom fuse_ctrl_rst_in_agent_ae_scoreboard end + endfunction + + // FUNCTION: write_fuse_ctrl_core_axi_write_in_agent_ae + // Transactions received through fuse_ctrl_core_axi_write_in_agent_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_fuse_ctrl_core_axi_write_in_agent_ae(fuse_ctrl_core_axi_write_in_transaction t); + // pragma uvmf custom fuse_ctrl_core_axi_write_in_agent_ae_scoreboard begin + `uvm_info("PRED", "Transaction Received through fuse_ctrl_core_axi_write_in_agent_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // UVMF_CHANGE_ME: Implement custom scoreboard here. + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "UVMF_CHANGE_ME: The fuse_ctrl_scoreboard::write_fuse_ctrl_core_axi_write_in_agent_ae function needs to be completed with custom scoreboard functionality",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + + // pragma uvmf custom fuse_ctrl_core_axi_write_in_agent_ae_scoreboard end + endfunction + + // FUNCTION: write_fuse_ctrl_prim_axi_write_in_agent_ae + // Transactions received through fuse_ctrl_prim_axi_write_in_agent_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_fuse_ctrl_prim_axi_write_in_agent_ae(fuse_ctrl_prim_axi_write_in_transaction t); + // pragma uvmf custom fuse_ctrl_prim_axi_write_in_agent_ae_scoreboard begin + `uvm_info("PRED", "Transaction Received through fuse_ctrl_prim_axi_write_in_agent_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // UVMF_CHANGE_ME: Implement custom scoreboard here. + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "UVMF_CHANGE_ME: The fuse_ctrl_scoreboard::write_fuse_ctrl_prim_axi_write_in_agent_ae function needs to be completed with custom scoreboard functionality",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + + // pragma uvmf custom fuse_ctrl_prim_axi_write_in_agent_ae_scoreboard end + endfunction + + // FUNCTION: write_fuse_ctrl_core_axi_read_in_agent_ae + // Transactions received through fuse_ctrl_core_axi_read_in_agent_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_fuse_ctrl_core_axi_read_in_agent_ae(fuse_ctrl_core_axi_read_in_transaction t); + // pragma uvmf custom fuse_ctrl_core_axi_read_in_agent_ae_scoreboard begin + `uvm_info("PRED", "Transaction Received through fuse_ctrl_core_axi_read_in_agent_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // UVMF_CHANGE_ME: Implement custom scoreboard here. + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "UVMF_CHANGE_ME: The fuse_ctrl_scoreboard::write_fuse_ctrl_core_axi_read_in_agent_ae function needs to be completed with custom scoreboard functionality",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + + // pragma uvmf custom fuse_ctrl_core_axi_read_in_agent_ae_scoreboard end + endfunction + + // FUNCTION: write_fuse_ctrl_prim_axi_read_in_agent_ae + // Transactions received through fuse_ctrl_prim_axi_read_in_agent_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_fuse_ctrl_prim_axi_read_in_agent_ae(fuse_ctrl_prim_axi_read_in_transaction t); + // pragma uvmf custom fuse_ctrl_prim_axi_read_in_agent_ae_scoreboard begin + `uvm_info("PRED", "Transaction Received through fuse_ctrl_prim_axi_read_in_agent_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // UVMF_CHANGE_ME: Implement custom scoreboard here. + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "UVMF_CHANGE_ME: The fuse_ctrl_scoreboard::write_fuse_ctrl_prim_axi_read_in_agent_ae function needs to be completed with custom scoreboard functionality",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + + // pragma uvmf custom fuse_ctrl_prim_axi_read_in_agent_ae_scoreboard end + endfunction + + // FUNCTION: write_fuse_ctrl_secreg_axi_read_in_agent_ae + // Transactions received through fuse_ctrl_secreg_axi_read_in_agent_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_fuse_ctrl_secreg_axi_read_in_agent_ae(fuse_ctrl_secreg_axi_read_in_transaction t); + // pragma uvmf custom fuse_ctrl_secreg_axi_read_in_agent_ae_scoreboard begin + `uvm_info("PRED", "Transaction Received through fuse_ctrl_secreg_axi_read_in_agent_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // UVMF_CHANGE_ME: Implement custom scoreboard here. + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "UVMF_CHANGE_ME: The fuse_ctrl_scoreboard::write_fuse_ctrl_secreg_axi_read_in_agent_ae function needs to be completed with custom scoreboard functionality",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + + // pragma uvmf custom fuse_ctrl_secreg_axi_read_in_agent_ae_scoreboard end + endfunction + + // FUNCTION: write_fuse_ctrl_lc_otp_in_agent_ae + // Transactions received through fuse_ctrl_lc_otp_in_agent_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_fuse_ctrl_lc_otp_in_agent_ae(fuse_ctrl_lc_otp_in_transaction t); + // pragma uvmf custom fuse_ctrl_lc_otp_in_agent_ae_scoreboard begin + `uvm_info("PRED", "Transaction Received through fuse_ctrl_lc_otp_in_agent_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // UVMF_CHANGE_ME: Implement custom scoreboard here. + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "UVMF_CHANGE_ME: The fuse_ctrl_scoreboard::write_fuse_ctrl_lc_otp_in_agent_ae function needs to be completed with custom scoreboard functionality",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + + // pragma uvmf custom fuse_ctrl_lc_otp_in_agent_ae_scoreboard end + endfunction + + // FUNCTION: write_fuse_ctrl_in_agent_ae + // Transactions received through fuse_ctrl_in_agent_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_fuse_ctrl_in_agent_ae(fuse_ctrl_in_transaction t); + // pragma uvmf custom fuse_ctrl_in_agent_ae_scoreboard begin + `uvm_info("PRED", "Transaction Received through fuse_ctrl_in_agent_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // UVMF_CHANGE_ME: Implement custom scoreboard here. + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "UVMF_CHANGE_ME: The fuse_ctrl_scoreboard::write_fuse_ctrl_in_agent_ae function needs to be completed with custom scoreboard functionality",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + + // pragma uvmf custom fuse_ctrl_in_agent_ae_scoreboard end + endfunction + + + + // FUNCTION: extract_phase + virtual function void extract_phase(uvm_phase phase); +// pragma uvmf custom extract_phase begin + super.extract_phase(phase); +// pragma uvmf custom extract_phase end + endfunction + + // FUNCTION: check_phase + virtual function void check_phase(uvm_phase phase); +// pragma uvmf custom check_phase begin + super.check_phase(phase); +// pragma uvmf custom check_phase end + endfunction + + // FUNCTION: report_phase + virtual function void report_phase(uvm_phase phase); +// pragma uvmf custom report_phase begin + super.report_phase(phase); +// pragma uvmf custom report_phase end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/environment_packages/fuse_ctrl_env_pkg/yaml/fuse_ctrl_environment.yaml b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/environment_packages/fuse_ctrl_env_pkg/yaml/fuse_ctrl_environment.yaml new file mode 100644 index 0000000..84226cb --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/environment_packages/fuse_ctrl_env_pkg/yaml/fuse_ctrl_environment.yaml @@ -0,0 +1,116 @@ +uvmf: + environments: + fuse_ctrl: + agents: + - initiator_responder: INITIATOR + name: fuse_ctrl_rst_in_agent + type: fuse_ctrl_rst_in + - initiator_responder: RESPONDER + name: fuse_ctrl_rst_out_agent + type: fuse_ctrl_rst_out + - initiator_responder: INITIATOR + name: fuse_ctrl_core_axi_write_in_if_agent + type: fuse_ctrl_core_axi_write_in + - initiator_responder: RESPONDER + name: fuse_ctrl_core_axi_write_out_if_agent + type: fuse_ctrl_core_axi_write_out + - initiator_responder: INITIATOR + name: fuse_ctrl_prim_axi_write_in_if_agent + type: fuse_ctrl_prim_axi_write_in + - initiator_responder: RESPONDER + name: fuse_ctrl_prim_axi_write_out_if_agent + type: fuse_ctrl_prim_axi_write_out + - initiator_responder: INITIATOR + name: fuse_ctrl_core_axi_read_in_if_agent + type: fuse_ctrl_core_axi_read_in + - initiator_responder: RESPONDER + name: fuse_ctrl_core_axi_read_out_if_agent + type: fuse_ctrl_core_axi_read_out + - initiator_responder: INITIATOR + name: fuse_ctrl_prim_axi_read_in_if_agent + type: fuse_ctrl_prim_axi_read_in + - initiator_responder: RESPONDER + name: fuse_ctrl_prim_axi_read_out_if_agent + type: fuse_ctrl_prim_axi_read_out + - initiator_responder: INITIATOR + name: fuse_ctrl_secreg_axi_read_in_if_agent + type: fuse_ctrl_secreg_axi_read_in + - initiator_responder: RESPONDER + name: fuse_ctrl_secreg_axi_read_out_if_agent + type: fuse_ctrl_secreg_axi_read_out + - initiator_responder: INITIATOR + name: fuse_ctrl_lc_otp_in_if_agent + type: fuse_ctrl_lc_otp_in + - initiator_responder: RESPONDER + name: fuse_ctrl_lc_otp_out_if_agent + type: fuse_ctrl_lc_otp_out + - initiator_responder: INITIATOR + name: fuse_ctrl_in_if_agent + type: fuse_ctrl_in + - initiator_responder: RESPONDER + name: fuse_ctrl_out_if_agent + type: fuse_ctrl_out + analysis_components: + - name: fuse_ctrl_pred + parameters: [] + type: fuse_ctrl_predictor + - name: fuse_ctrl_sb + parameters: [] + type: fuse_ctrl_scoreboard + analysis_exports: [] + analysis_ports: [] + config_constraints: [] + config_vars: [] + existing_library_component: 'True' + hvl_pkg_parameters: [] + non_uvmf_components: [] + parameters: [] + qvip_memory_agents: [] + scoreboards: [] + subenvs: [] + tlm_connections: + - driver: fuse_ctrl_rst_in_agent.monitored_ap + receiver: fuse_ctrl_pred.fuse_ctrl_rst_in_agent_ae + validate: 'True' + - driver: fuse_ctrl_core_axi_write_in_if_agent.monitored_ap + receiver: fuse_ctrl_pred.fuse_ctrl_core_axi_write_in_agent_ae + validate: 'True' + - driver: fuse_ctrl_core_axi_write_out_if_agent.monitored_ap + receiver: fuse_ctrl_sb.fuse_ctrl_core_axi_write_in_agent_ae + validate: 'True' + - driver: fuse_ctrl_core_axi_read_in_if_agent.monitored_ap + receiver: fuse_ctrl_pred.fuse_ctrl_core_axi_read_in_agent_ae + validate: 'True' + - driver: fuse_ctrl_core_axi_read_out_if_agent.monitored_ap + receiver: fuse_ctrl_sb.fuse_ctrl_core_axi_read_in_agent_ae + validate: 'True' + - driver: fuse_ctrl_prim_axi_write_in_if_agent.monitored_ap + receiver: fuse_ctrl_pred.fuse_ctrl_prim_axi_write_in_agent_ae + validate: 'True' + - driver: fuse_ctrl_prim_axi_write_out_if_agent.monitored_ap + receiver: fuse_ctrl_sb.fuse_ctrl_prim_axi_write_in_agent_ae + validate: 'True' + - driver: fuse_ctrl_prim_axi_read_in_if_agent.monitored_ap + receiver: fuse_ctrl_pred.fuse_ctrl_prim_axi_read_in_agent_ae + validate: 'True' + - driver: fuse_ctrl_prim_axi_read_out_if_agent.monitored_ap + receiver: fuse_ctrl_sb.fuse_ctrl_prim_axi_read_in_agent_ae + validate: 'True' + - driver: fuse_ctrl_secreg_axi_read_in_if_agent.monitored_ap + receiver: fuse_ctrl_pred.fuse_ctrl_secreg_axi_read_in_agent_ae + validate: 'True' + - driver: fuse_ctrl_secreg_axi_read_out_if_agent.monitored_ap + receiver: fuse_ctrl_sb.fuse_ctrl_secreg_axi_read_in_agent_ae + validate: 'True' + - driver: fuse_ctrl_lc_otp_in_if_agent.monitored_ap + receiver: fuse_ctrl_pred.fuse_ctrl_lc_otp_in_agent_ae + validate: 'True' + - driver: fuse_ctrl_lc_otp_out_if_agent.monitored_ap + receiver: fuse_ctrl_sb.fuse_ctrl_lc_otp_in_agent_ae + validate: 'True' + - driver: fuse_ctrl_in_if_agent.monitored_ap + receiver: fuse_ctrl_pred.fuse_ctrl_in_agent_ae + validate: 'True' + - driver: fuse_ctrl_out_if_agent.monitored_ap + receiver: fuse_ctrl_sb.fuse_ctrl_in_agent_ae + validate: 'True' diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/environment_packages/fuse_ctrl_env_pkg/yaml/fuse_ctrl_util_comp_fuse_ctrl_predictor.yaml b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/environment_packages/fuse_ctrl_env_pkg/yaml/fuse_ctrl_util_comp_fuse_ctrl_predictor.yaml new file mode 100644 index 0000000..65e9ddc --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/environment_packages/fuse_ctrl_env_pkg/yaml/fuse_ctrl_util_comp_fuse_ctrl_predictor.yaml @@ -0,0 +1,39 @@ +uvmf: + util_components: + fuse_ctrl_predictor: + analysis_exports: + - name: fuse_ctrl_rst_in_agent_ae + type: fuse_ctrl_rst_in_transaction + - name: fuse_ctrl_core_axi_write_in_agent_ae + type: fuse_ctrl_core_axi_write_in_transaction + - name: fuse_ctrl_prim_axi_write_in_agent_ae + type: fuse_ctrl_prim_axi_write_in_transaction + - name: fuse_ctrl_core_axi_read_in_agent_ae + type: fuse_ctrl_core_axi_read_in_transaction + - name: fuse_ctrl_prim_axi_read_in_agent_ae + type: fuse_ctrl_prim_axi_read_in_transaction + - name: fuse_ctrl_secreg_axi_read_in_agent_ae + type: fuse_ctrl_secreg_axi_read_in_transaction + - name: fuse_ctrl_lc_otp_in_agent_ae + type: fuse_ctrl_lc_otp_in_transaction + - name: fuse_ctrl_in_agent_ae + type: fuse_ctrl_in_transaction + analysis_ports: + - name: fuse_ctrl_rst_in_agent_ap + type: fuse_ctrl_rst_in_transaction + - name: fuse_ctrl_core_axi_write_in_agent_ap + type: fuse_ctrl_core_axi_write_in_transaction + - name: fuse_ctrl_prim_axi_write_in_agent_ap + type: fuse_ctrl_prim_axi_write_in_transaction + - name: fuse_ctrl_core_axi_read_in_agent_ap + type: fuse_ctrl_core_axi_read_in_transaction + - name: fuse_ctrl_prim_axi_read_in_agent_ap + type: fuse_ctrl_prim_axi_read_in_transaction + - name: fuse_ctrl_secreg_axi_read_in_agent_ap + type: fuse_ctrl_secreg_axi_read_in_transaction + - name: fuse_ctrl_lc_otp_in_agent_ap + type: fuse_ctrl_lc_otp_in_transaction + - name: fuse_ctrl_in_agent_ap + type: fuse_ctrl_in_transaction + existing_library_component: 'True' + type: predictor diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/environment_packages/fuse_ctrl_env_pkg/yaml/fuse_ctrl_util_comp_fuse_ctrl_scoreboard.yaml b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/environment_packages/fuse_ctrl_env_pkg/yaml/fuse_ctrl_util_comp_fuse_ctrl_scoreboard.yaml new file mode 100644 index 0000000..4d9bd6f --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/environment_packages/fuse_ctrl_env_pkg/yaml/fuse_ctrl_util_comp_fuse_ctrl_scoreboard.yaml @@ -0,0 +1,22 @@ +uvmf: + util_components: + fuse_ctrl_scoreboard: + analysis_exports: + - name: fuse_ctrl_rst_in_agent_ae + type: fuse_ctrl_rst_in_transaction + - name: fuse_ctrl_core_axi_write_in_agent_ae + type: fuse_ctrl_core_axi_write_in_transaction + - name: fuse_ctrl_prim_axi_write_in_agent_ae + type: fuse_ctrl_prim_axi_write_in_transaction + - name: fuse_ctrl_core_axi_read_in_agent_ae + type: fuse_ctrl_core_axi_read_in_transaction + - name: fuse_ctrl_prim_axi_read_in_agent_ae + type: fuse_ctrl_prim_axi_read_in_transaction + - name: fuse_ctrl_secreg_axi_read_in_agent_ae + type: fuse_ctrl_secreg_axi_read_in_transaction + - name: fuse_ctrl_lc_otp_in_agent_ae + type: fuse_ctrl_lc_otp_in_transaction + - name: fuse_ctrl_in_agent_ae + type: fuse_ctrl_in_transaction + existing_library_component: 'True' + type: scoreboard diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/.project b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/.project new file mode 100644 index 0000000..e463bf0 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/.project @@ -0,0 +1,30 @@ + + + fuse_ctrl_core_axi_read_in_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/.svproject b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/.svproject new file mode 100644 index 0000000..4a40ac8 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/Makefile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/Makefile new file mode 100644 index 0000000..0ccd2f8 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/Makefile @@ -0,0 +1,66 @@ +# fuse_ctrl_core_axi_read_in interface packages source +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +fuse_ctrl_core_axi_read_in_PKG = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_read_in_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_filelist_hvl.f + +fuse_ctrl_core_axi_read_in_PKG_HDL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_read_in_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_filelist_hdl.f + +fuse_ctrl_core_axi_read_in_PKG_XRTL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_read_in_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_filelist_xrtl.f + +COMP_fuse_ctrl_core_axi_read_in_PKG_TGT_0 = q_comp_fuse_ctrl_core_axi_read_in_pkg +COMP_fuse_ctrl_core_axi_read_in_PKG_TGT_1 = v_comp_fuse_ctrl_core_axi_read_in_pkg +COMP_fuse_ctrl_core_axi_read_in_PKG_TGT = $(COMP_fuse_ctrl_core_axi_read_in_PKG_TGT_$(USE_VELOCE)) + +comp_fuse_ctrl_core_axi_read_in_pkg: $(COMP_fuse_ctrl_core_axi_read_in_PKG_TGT) + +q_comp_fuse_ctrl_core_axi_read_in_pkg: + $(HDL_COMP_CMD) $(fuse_ctrl_core_axi_read_in_PKG_HDL) + $(HVL_COMP_CMD) $(fuse_ctrl_core_axi_read_in_PKG) + $(HDL_COMP_CMD) $(fuse_ctrl_core_axi_read_in_PKG_XRTL) + +v_comp_fuse_ctrl_core_axi_read_in_pkg: + $(HVL_COMP_CMD) $(fuse_ctrl_core_axi_read_in_PKG_HDL) + $(HVL_COMP_CMD) $(fuse_ctrl_core_axi_read_in_PKG) + $(VELANALYZE_CMD) $(fuse_ctrl_core_axi_read_in_PKG_HDL) + $(VELANALYZE_HVL_CMD) $(fuse_ctrl_core_axi_read_in_PKG) + $(HDL_COMP_CMD) $(fuse_ctrl_core_axi_read_in_PKG_XRTL) + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export fuse_ctrl_core_axi_read_in_IF_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_read_in_pkg/dpi + +C_FILE_COMPILE_LIST_fuse_ctrl_core_axi_read_in_pkg = \ + +O_FILE_COMPILE_LIST_fuse_ctrl_core_axi_read_in_pkg = $(notdir $(C_FILE_COMPILE_LIST_fuse_ctrl_core_axi_read_in_pkg:.c=.o)) + +GCC_COMP_ARGS_fuse_ctrl_core_axi_read_in_pkg += -I$(fuse_ctrl_core_axi_read_in_IF_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_fuse_ctrl_core_axi_read_in_pkg += $(fuse_ctrl_core_axi_read_in_IF_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_fuse_ctrl_core_axi_read_in_pkg += \ + \ + -o .so + +comp_fuse_ctrl_core_axi_read_in_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Interface C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_fuse_ctrl_core_axi_read_in_pkg) $(C_FILE_COMPILE_LIST_fuse_ctrl_core_axi_read_in_pkg) + @echo "--------------------------------" + @echo "Linking Interface C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_fuse_ctrl_core_axi_read_in_pkg) $(O_FILE_COMPILE_LIST_fuse_ctrl_core_axi_read_in_pkg) + @echo "--------------------------------" + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/compile.do b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/compile.do new file mode 100644 index 0000000..badb448 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/compile.do @@ -0,0 +1,14 @@ +# Tcl do file for compile of fuse_ctrl_core_axi_read_in interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_read_in_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_filelist_hdl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_read_in_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_filelist_hvl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_read_in_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_filelist_xrtl.f \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in.compile new file mode 100644 index 0000000..87b941a --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in.compile @@ -0,0 +1,3 @@ +needs: + - fuse_ctrl_core_axi_read_in_hvl.compile + - fuse_ctrl_core_axi_read_in_hdl.compile diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_bfm.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_bfm.vinfo new file mode 100644 index 0000000..5b88121 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_bfm.vinfo @@ -0,0 +1,6 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use fuse_ctrl_core_axi_read_in_pkg_hdl.vinfo ++incdir+@vinfodir +src/fuse_ctrl_core_axi_read_in_if.sv +src/fuse_ctrl_core_axi_read_in_driver_bfm.sv +src/fuse_ctrl_core_axi_read_in_monitor_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_common.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_common.compile new file mode 100644 index 0000000..c150c93 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_common.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +incdir: + - . + - ${uvm_path}/src +src: + - fuse_ctrl_core_axi_read_in_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_filelist_hdl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_filelist_hdl.f new file mode 100644 index 0000000..b5ab5ea --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_filelist_hdl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_filelist_hvl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_filelist_hvl.f new file mode 100644 index 0000000..ea2d101 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_filelist_hvl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_pkg.sv \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_filelist_xrtl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_filelist_xrtl.f new file mode 100644 index 0000000..16c4792 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_filelist_xrtl.f @@ -0,0 +1,3 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_if.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_monitor_bfm.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_driver_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_hdl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_hdl.compile new file mode 100644 index 0000000..96c4c97 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_hdl.compile @@ -0,0 +1,9 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ./fuse_ctrl_core_axi_read_in_common.compile +incdir: + - . +src: + - src/fuse_ctrl_core_axi_read_in_if.sv + - src/fuse_ctrl_core_axi_read_in_monitor_bfm.sv + - src/fuse_ctrl_core_axi_read_in_driver_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_hvl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_hvl.compile new file mode 100644 index 0000000..287ac6a --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_hvl.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ./fuse_ctrl_core_axi_read_in_common.compile +incdir: + - . +src: + - fuse_ctrl_core_axi_read_in_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_pkg.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_pkg.sv new file mode 100644 index 0000000..69c23d8 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_pkg.sv @@ -0,0 +1,91 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - + +// - +// - +// - + +// - +// - +// - + +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_core_axi_read_in_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg_hdl::*; + import uvmf_base_pkg::*; + import fuse_ctrl_core_axi_read_in_pkg_hdl::*; + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + `include "src/fuse_ctrl_core_axi_read_in_macros.svh" + + export fuse_ctrl_core_axi_read_in_pkg_hdl::*; + + + + // Parameters defined as HVL parameters + + `include "src/fuse_ctrl_core_axi_read_in_typedefs.svh" + `include "src/fuse_ctrl_core_axi_read_in_transaction.svh" + + `include "src/fuse_ctrl_core_axi_read_in_configuration.svh" + `include "src/fuse_ctrl_core_axi_read_in_driver.svh" + `include "src/fuse_ctrl_core_axi_read_in_monitor.svh" + + `include "src/fuse_ctrl_core_axi_read_in_transaction_coverage.svh" + `include "src/fuse_ctrl_core_axi_read_in_sequence_base.svh" + `include "src/fuse_ctrl_core_axi_read_in_random_sequence.svh" + + `include "src/fuse_ctrl_core_axi_read_in_responder_sequence.svh" + `include "src/fuse_ctrl_core_axi_read_in2reg_adapter.svh" + + `include "src/fuse_ctrl_core_axi_read_in_agent.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new interface sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the interface package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_pkg.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_pkg.vinfo new file mode 100644 index 0000000..0c3c242 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_pkg.vinfo @@ -0,0 +1,4 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use fuse_ctrl_core_axi_read_in_pkg_hdl.vinfo ++incdir+@vinfodir +fuse_ctrl_core_axi_read_in_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_pkg_hdl.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_pkg_hdl.sv new file mode 100644 index 0000000..2377e24 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_pkg_hdl.sv @@ -0,0 +1,52 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that needs to be compiled and synthesized +// for running on Veloce. +// +// CONTAINS: +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_core_axi_read_in_pkg_hdl; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HDL parameters + + `include "src/fuse_ctrl_core_axi_read_in_typedefs_hdl.svh" + `include "src/fuse_ctrl_core_axi_read_in_macros.svh" + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_pkg_hdl.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_pkg_hdl.vinfo new file mode 100644 index 0000000..ff9df31 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_pkg_hdl.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +fuse_ctrl_core_axi_read_in_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_pkg_sve.F b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_pkg_sve.F new file mode 100644 index 0000000..2a3defa --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_pkg_sve.F @@ -0,0 +1,10 @@ +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + ++incdir+. +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_filelist_hdl.f +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_core_axi_read_in_pkg/fuse_ctrl_core_axi_read_in_filelist_hvl.f diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in2reg_adapter.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in2reg_adapter.svh new file mode 100644 index 0000000..cb98163 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in2reg_adapter.svh @@ -0,0 +1,142 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the UVM register adapter for the fuse_ctrl_core_axi_read_in interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_read_in2reg_adapter #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvm_reg_adapter; + + `uvm_object_param_utils( fuse_ctrl_core_axi_read_in2reg_adapter #( + AW, + DW, + IW, + UW + ) +) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //-------------------------------------------------------------------- + // new + //-------------------------------------------------------------------- + function new (string name = "fuse_ctrl_core_axi_read_in2reg_adapter" ); + super.new(name); + // pragma uvmf custom new begin + // UVMF_CHANGE_ME : Configure the adapter regarding byte enables and provides response. + + // Does the protocol the Agent is modeling support byte enables? + // 0 = NO + // 1 = YES + supports_byte_enable = 0; + + // Does the Agent's Driver provide separate response sequence items? + // i.e. Does the driver call seq_item_port.put() + // and do the sequences call get_response()? + // 0 = NO + // 1 = YES + provides_responses = 0; + // pragma uvmf custom new end + + endfunction: new + + //-------------------------------------------------------------------- + // reg2bus + //-------------------------------------------------------------------- + virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw); + + fuse_ctrl_core_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + trans_h = fuse_ctrl_core_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +::type_id::create("trans_h"); + + // pragma uvmf custom reg2bus begin + // UVMF_CHANGE_ME : Fill in the reg2bus adapter mapping registe fields to protocol fields. + + //Adapt the following for your sequence item type + // trans_h.op = (rw.kind == UVM_READ) ? WB_READ : WB_WRITE; + //Copy over address + // trans_h.addr = rw.addr; + //Copy over write data + // trans_h.data = rw.data; + + // pragma uvmf custom reg2bus end + + // Return the adapted transaction + return trans_h; + + endfunction: reg2bus + + //-------------------------------------------------------------------- + // bus2reg + //-------------------------------------------------------------------- + virtual function void bus2reg(uvm_sequence_item bus_item, + ref uvm_reg_bus_op rw); + fuse_ctrl_core_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + trans_h; + if (!$cast(trans_h, bus_item)) begin + `uvm_fatal("ADAPT","Provided bus_item is not of the correct type") + return; + end + // pragma uvmf custom bus2reg begin + // UVMF_CHANGE_ME : Fill in the bus2reg adapter mapping protocol fields to register fields. + //Adapt the following for your sequence item type + //Copy over instruction type + // rw.kind = (trans_h.op == WB_WRITE) ? UVM_WRITE : UVM_READ; + //Copy over address + // rw.addr = trans_h.addr; + //Copy over read data + // rw.data = trans_h.data; + //Check for errors on the bus and return UVM_NOT_OK if there is an error + // rw.status = UVM_IS_OK; + // pragma uvmf custom bus2reg end + + endfunction: bus2reg + +endclass : fuse_ctrl_core_axi_read_in2reg_adapter + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_agent.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_agent.svh new file mode 100644 index 0000000..40c3aad --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_agent.svh @@ -0,0 +1,109 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: Protocol specific agent class definition +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_read_in_agent #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvmf_parameterized_agent #( + .CONFIG_T(fuse_ctrl_core_axi_read_in_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .DRIVER_T(fuse_ctrl_core_axi_read_in_driver #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .MONITOR_T(fuse_ctrl_core_axi_read_in_monitor #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .COVERAGE_T(fuse_ctrl_core_axi_read_in_transaction_coverage #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .TRANS_T(fuse_ctrl_core_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +) + ); + + `uvm_component_param_utils( fuse_ctrl_core_axi_read_in_agent #( + AW, + DW, + IW, + UW + ) +) + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** + // FUNCTION: build_phase + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + if (configuration.active_passive == ACTIVE) begin + // Place sequencer handle into configuration object + // so that it may be retrieved from configuration + // rather than using uvm_config_db + configuration.sequencer = this.sequencer; + end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_configuration.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_configuration.svh new file mode 100644 index 0000000..55a8cfe --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_configuration.svh @@ -0,0 +1,241 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class contains all variables and functions used +// to configure the fuse_ctrl_core_axi_read_in agent and its bfm's. It gets the +// bfm's from the uvm_config_db for use by the agent. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_read_in_configuration #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvmf_parameterized_agent_configuration_base #( + .DRIVER_BFM_BIND_T(virtual fuse_ctrl_core_axi_read_in_driver_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .MONITOR_BFM_BIND_T( virtual fuse_ctrl_core_axi_read_in_monitor_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +)); + + `uvm_object_param_utils( fuse_ctrl_core_axi_read_in_configuration #( + AW, + DW, + IW, + UW + ) +) + + + // Sequencer handle populated by agent + uvm_sequencer #(fuse_ctrl_core_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + ) sequencer; + + //Constraints for the configuration variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + covergroup fuse_ctrl_core_axi_read_in_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + // pragma uvmf custom covergroup end + endgroup + + //******************************************************************* + //******************************************************************* + // Structure used to pass configuration variables to monitor and driver BFM's. + // Use to_struct function to pack variables into structure. + // Use from_struct function to unpack variables from structure. + // This structure is defined in fuse_ctrl_core_axi_read_in_macros.svh + `fuse_ctrl_core_axi_read_in_CONFIGURATION_STRUCT + fuse_ctrl_core_axi_read_in_configuration_s fuse_ctrl_core_axi_read_in_configuration_struct; + //******************************************************************* + // FUNCTION: to_struct() + // This function packs variables into a fuse_ctrl_core_axi_read_in_configuration_s + // structure. The function returns the handle to the fuse_ctrl_core_axi_read_in_configuration_struct. + // This function is defined in fuse_ctrl_core_axi_read_in_macros.svh + `fuse_ctrl_core_axi_read_in_CONFIGURATION_TO_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_struct() + // This function unpacks the struct provided as an argument into + // variables of this class. + // This function is defined in fuse_ctrl_core_axi_read_in_macros.svh + `fuse_ctrl_core_axi_read_in_CONFIGURATION_FROM_STRUCT_FUNCTION + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + // Construct the covergroup for this configuration class + fuse_ctrl_core_axi_read_in_configuration_cg = new; + endfunction + + // **************************************************************************** + // FUNCTION: post_randomize() + // This function is automatically called after the randomize() function + // is executed. + // + function void post_randomize(); + super.post_randomize(); + fuse_ctrl_core_axi_read_in_configuration_cg.sample(); + endfunction + + // **************************************************************************** + // FUNCTION: initialize + // This function causes the configuration to retrieve + // its virtual interface handle from the uvm_config_db. + // This function also makes itself available to its + // agent through the uvm_config_db. + // + // ARGUMENTS: + // uvmf_active_passive_t activity: + // This argument identifies the simulation level + // as either BLOCK, CHIP, SIMULATION, etc. + // + // AGENT_PATH: + // This argument identifies the path to this + // configurations agent. This configuration + // makes itself available to the agent specified + // by agent_path by placing itself into the + // uvm_config_db. + // + // INTERFACE_NAME: + // This argument identifies the string name of + // this configurations BFM's. This string + // name is used to retrieve the driver and + // monitor BFM from the uvm_config_db. + // + virtual function void initialize(uvmf_active_passive_t activity, + string agent_path, + string interface_name); + + super.initialize( activity, agent_path, interface_name); + // The covergroup is given the same name as the interface + fuse_ctrl_core_axi_read_in_configuration_cg.set_inst_name(interface_name); + + // This configuration places itself into the uvm_config_db for the agent, identified by the agent_path variable, to retrieve. + uvm_config_db #( fuse_ctrl_core_axi_read_in_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + + )::set( null ,agent_path,UVMF_AGENT_CONFIG, this ); + + // This configuration also places itself in the config db using the same identifier used by the interface. This allows users to access + // configuration variables and the interface through the bfm api class rather than directly accessing the BFM. This is useful for + // accessingthe BFM when using Veloce + uvm_config_db #( fuse_ctrl_core_axi_read_in_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + + )::set( null ,UVMF_CONFIGURATIONS, interface_name, this ); + + fuse_ctrl_core_axi_read_in_configuration_cg.set_inst_name($sformatf("fuse_ctrl_core_axi_read_in_configuration_cg_%s",get_full_name())); + +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. + `uvm_info("CFG", + $psprintf("The agent at '%s' is using interface named %s has the following parameters: AW=%x DW=%x IW=%x UW=%x ", agent_path, interface_name, AW ,DW ,IW ,UW ), + UVM_DEBUG) + + // pragma uvmf custom initialize begin + // This controls whether or not the agent returns a transaction handle in the driver when calling + // item_done() back into the sequencer or not. If set to 1, a transaction is sent back which means + // the sequence on the other end must use the get_response() part of the driver/sequence API. If + // this doesn't occur, there will eventually be response_queue overflow errors during the test. + return_transaction_response = 1'b0; + + // pragma uvmf custom initialize end + + endfunction + + // **************************************************************************** + // TASK: wait_for_reset + // *[Required]* Blocks until reset is released. The wait_for_reset operation is performed + // by a task in the monitor bfm. + virtual task wait_for_reset(); + monitor_bfm.wait_for_reset(); + endtask + + // **************************************************************************** + // TASK: wait_for_num_clocks + // *[Required]* Blocks until specified number of clocks have elapsed. The wait_for_num_clocks + // operation is performed by a task in the monitor bfm. + virtual task wait_for_num_clocks(int clocks); + monitor_bfm.wait_for_num_clocks(clocks); + endtask + + // **************************************************************************** + // FUNCTION : convert2string() + // This function is used to convert variables in this class into a string for log messaging. + // + virtual function string convert2string (); + // pragma uvmf custom convert2string begin + return $sformatf(""); + // pragma uvmf custom convert2string end + endfunction + + // **************************************************************************** + // FUNCTION: get_sequencer + function uvm_sequencer #(fuse_ctrl_core_axi_read_in_transaction#( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +) get_sequencer(); + return sequencer; + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_driver.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_driver.svh new file mode 100644 index 0000000..a0a7a6d --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_driver.svh @@ -0,0 +1,141 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class passes transactions between the sequencer +// and the BFM driver interface. It accesses the driver BFM +// through the bfm handle. This driver +// passes transactions to the driver BFM through the access +// task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_read_in_driver #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvmf_driver_base #( + .CONFIG_T(fuse_ctrl_core_axi_read_in_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + ), + .BFM_BIND_T(virtual fuse_ctrl_core_axi_read_in_driver_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + ), + .REQ(fuse_ctrl_core_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + ), + .RSP(fuse_ctrl_core_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + )); + + `uvm_component_param_utils( fuse_ctrl_core_axi_read_in_driver #( + AW, + DW, + IW, + UW + ) +) +//******************************************************************* +// Macros that define structs located in fuse_ctrl_core_axi_read_in_macros.svh +//******************************************************************* +// Initiator macro used by fuse_ctrl_core_axi_read_in_driver and fuse_ctrl_core_axi_read_in_driver_bfm +// to communicate initiator driven data to fuse_ctrl_core_axi_read_in_driver_bfm. +`fuse_ctrl_core_axi_read_in_INITIATOR_STRUCT + fuse_ctrl_core_axi_read_in_initiator_s fuse_ctrl_core_axi_read_in_initiator_struct; +//******************************************************************* +// Responder macro used by fuse_ctrl_core_axi_read_in_driver and fuse_ctrl_core_axi_read_in_driver_bfm +// to communicate Responder driven data to fuse_ctrl_core_axi_read_in_driver_bfm. +`fuse_ctrl_core_axi_read_in_RESPONDER_STRUCT + fuse_ctrl_core_axi_read_in_responder_s fuse_ctrl_core_axi_read_in_responder_struct; + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent=null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the driver BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// driver BFM. This allows the driver BFM to call tasks and function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// **************************************************************************** +// This task is called by the run_phase in uvmf_driver_base. + virtual task access( inout REQ txn ); +// pragma uvmf custom access begin + if (configuration.initiator_responder==RESPONDER) begin + // Complete current transfer and wait for next transfer + bfm.respond_and_wait_for_next_transfer( + fuse_ctrl_core_axi_read_in_initiator_struct, + txn.to_responder_struct() + ); + // Unpack information about initiated transfer received by this responder + txn.from_initiator_struct(fuse_ctrl_core_axi_read_in_initiator_struct); + end else begin + // Initiate a transfer and get response + bfm.initiate_and_get_response( + txn.to_initiator_struct(), + fuse_ctrl_core_axi_read_in_responder_struct + ); + // Unpack transfer response information received by this initiator + txn.from_responder_struct(fuse_ctrl_core_axi_read_in_responder_struct); + end +// pragma uvmf custom access end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_driver_bfm.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_driver_bfm.sv new file mode 100644 index 0000000..ae6de99 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_driver_bfm.sv @@ -0,0 +1,385 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This interface performs the fuse_ctrl_core_axi_read_in signal driving. It is +// accessed by the uvm fuse_ctrl_core_axi_read_in driver through a virtual interface +// handle in the fuse_ctrl_core_axi_read_in configuration. It drives the singals passed +// in through the port connection named bus of type fuse_ctrl_core_axi_read_in_if. +// +// Input signals from the fuse_ctrl_core_axi_read_in_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// This bfm drives signals with a _o suffix. These signals +// are driven onto signals within fuse_ctrl_core_axi_read_in_if based on INITIATOR/RESPONDER and/or +// ARBITRATION/GRANT status. +// +// The output signal connections are as follows: +// signal_o -> bus.signal +// +// +// Interface functions and tasks used by UVM components: +// +// configure: +// This function gets configuration attributes from the +// UVM driver to set any required BFM configuration +// variables such as 'initiator_responder'. +// +// initiate_and_get_response: +// This task is used to perform signaling activity for initiating +// a protocol transfer. The task initiates the transfer, using +// input data from the initiator struct. Then the task captures +// response data, placing the data into the response struct. +// The response struct is returned to the driver class. +// +// respond_and_wait_for_next_transfer: +// This task is used to complete a current transfer as a responder +// and then wait for the initiator to start the next transfer. +// The task uses data in the responder struct to drive protocol +// signals to complete the transfer. The task then waits for +// the next transfer. Once the next transfer begins, data from +// the initiator is placed into the initiator struct and sent +// to the responder sequence for processing to determine +// what data to respond with. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_core_axi_read_in_pkg_hdl::*; +`include "src/fuse_ctrl_core_axi_read_in_macros.svh" + +interface fuse_ctrl_core_axi_read_in_driver_bfm #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + + (fuse_ctrl_core_axi_read_in_if bus); + // The following pragma and additional ones in-lined further below are for running this BFM on Veloce + // pragma attribute fuse_ctrl_core_axi_read_in_driver_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: AW=%x DW=%x IW=%x UW=%x ", AW,DW,IW,UW), + UVM_DEBUG) +end +`endif + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + tri clk_i_i; + tri rst_ni_i; + + // Signal list (all signals are capable of being inputs and outputs for the sake + // of supporting both INITIATOR and RESPONDER mode operation. Expectation is that + // directionality in the config file was from the point-of-view of the INITIATOR + + // INITIATOR mode input signals + + // INITIATOR mode output signals + tri [AW-1:0] araddr_i; + reg [AW-1:0] araddr_o = 'bz; + tri [$bits(axi_pkg::axi_burst_e)-1:0] arburst_i; + reg [$bits(axi_pkg::axi_burst_e)-1:0] arburst_o = 'bz; + tri [2:0] arsize_i; + reg [2:0] arsize_o = 'bz; + tri [7:0] arlen_i; + reg [7:0] arlen_o = 'bz; + tri [UW-1:0] aruser_i; + reg [UW-1:0] aruser_o = 'bz; + tri [IW-1:0] arid_i; + reg [IW-1:0] arid_o = 'bz; + tri arlock_i; + reg arlock_o = 'bz; + tri arvalid_i; + reg arvalid_o = 'bz; + tri rready_i; + reg rready_o = 'bz; + + // Bi-directional signals + + + assign clk_i_i = bus.clk_i; + assign rst_ni_i = bus.rst_ni; + + // These are signals marked as 'input' by the config file, but the signals will be + // driven by this BFM if put into RESPONDER mode (flipping all signal directions around) + + + // These are signals marked as 'output' by the config file, but the outputs will + // not be driven by this BFM unless placed in INITIATOR mode. + assign bus.araddr = (initiator_responder == INITIATOR) ? araddr_o : 'bz; + assign araddr_i = bus.araddr; + assign bus.arburst = (initiator_responder == INITIATOR) ? arburst_o : 'bz; + assign arburst_i = bus.arburst; + assign bus.arsize = (initiator_responder == INITIATOR) ? arsize_o : 'bz; + assign arsize_i = bus.arsize; + assign bus.arlen = (initiator_responder == INITIATOR) ? arlen_o : 'bz; + assign arlen_i = bus.arlen; + assign bus.aruser = (initiator_responder == INITIATOR) ? aruser_o : 'bz; + assign aruser_i = bus.aruser; + assign bus.arid = (initiator_responder == INITIATOR) ? arid_o : 'bz; + assign arid_i = bus.arid; + assign bus.arlock = (initiator_responder == INITIATOR) ? arlock_o : 'bz; + assign arlock_i = bus.arlock; + assign bus.arvalid = (initiator_responder == INITIATOR) ? arvalid_o : 'bz; + assign arvalid_i = bus.arvalid; + assign bus.rready = (initiator_responder == INITIATOR) ? rready_o : 'bz; + assign rready_i = bus.rready; + + // Proxy handle to UVM driver + fuse_ctrl_core_axi_read_in_pkg::fuse_ctrl_core_axi_read_in_driver #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + proxy; + // pragma tbx oneway proxy.my_function_name_in_uvm_driver + + // **************************************************************************** + // **************************************************************************** + // Macros that define structs located in fuse_ctrl_core_axi_read_in_macros.svh + // **************************************************************************** + // Struct for passing configuration data from fuse_ctrl_core_axi_read_in_driver to this BFM + // **************************************************************************** + `fuse_ctrl_core_axi_read_in_CONFIGURATION_STRUCT + // **************************************************************************** + // Structs for INITIATOR and RESPONDER data flow + //******************************************************************* + // Initiator macro used by fuse_ctrl_core_axi_read_in_driver and fuse_ctrl_core_axi_read_in_driver_bfm + // to communicate initiator driven data to fuse_ctrl_core_axi_read_in_driver_bfm. + `fuse_ctrl_core_axi_read_in_INITIATOR_STRUCT + fuse_ctrl_core_axi_read_in_initiator_s initiator_struct; + // Responder macro used by fuse_ctrl_core_axi_read_in_driver and fuse_ctrl_core_axi_read_in_driver_bfm + // to communicate Responder driven data to fuse_ctrl_core_axi_read_in_driver_bfm. + `fuse_ctrl_core_axi_read_in_RESPONDER_STRUCT + fuse_ctrl_core_axi_read_in_responder_s responder_struct; + + // **************************************************************************** +// pragma uvmf custom reset_condition_and_response begin + // Always block used to return signals to reset value upon assertion of reset + always @( negedge rst_ni_i ) + begin + // RESPONDER mode output signals + // INITIATOR mode output signals + araddr_o <= 'bz; + arburst_o <= 'bz; + arsize_o <= 'bz; + arlen_o <= 'bz; + aruser_o <= 'bz; + arid_o <= 'bz; + arlock_o <= 'bz; + arvalid_o <= 'bz; + rready_o <= 'bz; + // Bi-directional signals + + end +// pragma uvmf custom reset_condition_and_response end + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the driver BFM. It is called by the driver within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the driver BFM needs to be aware of the new configuration + // variables. + // + + function void configure(fuse_ctrl_core_axi_read_in_configuration_s fuse_ctrl_core_axi_read_in_configuration_arg); // pragma tbx xtf + initiator_responder = fuse_ctrl_core_axi_read_in_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + +// pragma uvmf custom initiate_and_get_response begin +// **************************************************************************** +// UVMF_CHANGE_ME +// This task is used by an initator. The task first initiates a transfer then +// waits for the responder to complete the transfer. + task initiate_and_get_response( + // This argument passes transaction variables used by an initiator + // to perform the initial part of a protocol transfer. The values + // come from a sequence item created in a sequence. + input fuse_ctrl_core_axi_read_in_initiator_s fuse_ctrl_core_axi_read_in_initiator_struct, + // This argument is used to send data received from the responder + // back to the sequence item. The sequence item is returned to the sequence. + output fuse_ctrl_core_axi_read_in_responder_s fuse_ctrl_core_axi_read_in_responder_struct + );// pragma tbx xtf + // + // Members within the fuse_ctrl_core_axi_read_in_initiator_struct: + // logic [AW-1:0] core_araddr ; + // logic core_arvalid ; + // logic [$bits(axi_pkg::axi_burst_e)] core_arburst ; + // logic [2:0] core_arsize ; + // logic [7:0] core_arlen ; + // logic [UW-1:0] core_aruser ; + // logic [IW-1:0] core_arid ; + // logic core_arlock ; + // logic core_rready ; + // Members within the fuse_ctrl_core_axi_read_in_responder_struct: + // logic [AW-1:0] core_araddr ; + // logic core_arvalid ; + // logic [$bits(axi_pkg::axi_burst_e)] core_arburst ; + // logic [2:0] core_arsize ; + // logic [7:0] core_arlen ; + // logic [UW-1:0] core_aruser ; + // logic [IW-1:0] core_arid ; + // logic core_arlock ; + // logic core_rready ; + initiator_struct = fuse_ctrl_core_axi_read_in_initiator_struct; + // + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clk_i_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available initiator input and inout signals listed. + // Initiator input signals + // Initiator inout signals + // How to assign a signal from an initiator struct member named xyz. + // All available initiator output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Initiator output signals + // araddr_o <= fuse_ctrl_core_axi_read_in_initiator_struct.xyz; // [AW-1:0] + // arburst_o <= fuse_ctrl_core_axi_read_in_initiator_struct.xyz; // [$bits(axi_pkg::axi_burst_e)-1:0] + // arsize_o <= fuse_ctrl_core_axi_read_in_initiator_struct.xyz; // [2:0] + // arlen_o <= fuse_ctrl_core_axi_read_in_initiator_struct.xyz; // [7:0] + // aruser_o <= fuse_ctrl_core_axi_read_in_initiator_struct.xyz; // [UW-1:0] + // arid_o <= fuse_ctrl_core_axi_read_in_initiator_struct.xyz; // [IW-1:0] + // arlock_o <= fuse_ctrl_core_axi_read_in_initiator_struct.xyz; // + // arvalid_o <= fuse_ctrl_core_axi_read_in_initiator_struct.xyz; // + // rready_o <= fuse_ctrl_core_axi_read_in_initiator_struct.xyz; // + // Initiator inout signals + // Initiate a transfer using the data received. + @(posedge clk_i_i); + @(posedge clk_i_i); + // Wait for the responder to complete the transfer then place the responder data into + // fuse_ctrl_core_axi_read_in_responder_struct. + @(posedge clk_i_i); + @(posedge clk_i_i); + responder_struct = fuse_ctrl_core_axi_read_in_responder_struct; + endtask +// pragma uvmf custom initiate_and_get_response end + +// pragma uvmf custom respond_and_wait_for_next_transfer begin +// **************************************************************************** +// The first_transfer variable is used to prevent completing a transfer in the +// first call to this task. For the first call to this task, there is not +// current transfer to complete. +bit first_transfer=1; + +// UVMF_CHANGE_ME +// This task is used by a responder. The task first completes the current +// transfer in progress then waits for the initiator to start the next transfer. + task respond_and_wait_for_next_transfer( + // This argument is used to send data received from the initiator + // back to the sequence item. The sequence determines how to respond. + output fuse_ctrl_core_axi_read_in_initiator_s fuse_ctrl_core_axi_read_in_initiator_struct, + // This argument passes transaction variables used by a responder + // to complete a protocol transfer. The values come from a sequence item. + input fuse_ctrl_core_axi_read_in_responder_s fuse_ctrl_core_axi_read_in_responder_struct + );// pragma tbx xtf + // Variables within the fuse_ctrl_core_axi_read_in_initiator_struct: + // logic [AW-1:0] core_araddr ; + // logic core_arvalid ; + // logic [$bits(axi_pkg::axi_burst_e)] core_arburst ; + // logic [2:0] core_arsize ; + // logic [7:0] core_arlen ; + // logic [UW-1:0] core_aruser ; + // logic [IW-1:0] core_arid ; + // logic core_arlock ; + // logic core_rready ; + // Variables within the fuse_ctrl_core_axi_read_in_responder_struct: + // logic [AW-1:0] core_araddr ; + // logic core_arvalid ; + // logic [$bits(axi_pkg::axi_burst_e)] core_arburst ; + // logic [2:0] core_arsize ; + // logic [7:0] core_arlen ; + // logic [UW-1:0] core_aruser ; + // logic [IW-1:0] core_arid ; + // logic core_arlock ; + // logic core_rready ; + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clk_i_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available responder input and inout signals listed. + // Responder input signals + // fuse_ctrl_core_axi_read_in_responder_struct.xyz = araddr_i; // [AW-1:0] + // fuse_ctrl_core_axi_read_in_responder_struct.xyz = arburst_i; // [$bits(axi_pkg::axi_burst_e)-1:0] + // fuse_ctrl_core_axi_read_in_responder_struct.xyz = arsize_i; // [2:0] + // fuse_ctrl_core_axi_read_in_responder_struct.xyz = arlen_i; // [7:0] + // fuse_ctrl_core_axi_read_in_responder_struct.xyz = aruser_i; // [UW-1:0] + // fuse_ctrl_core_axi_read_in_responder_struct.xyz = arid_i; // [IW-1:0] + // fuse_ctrl_core_axi_read_in_responder_struct.xyz = arlock_i; // + // fuse_ctrl_core_axi_read_in_responder_struct.xyz = arvalid_i; // + // fuse_ctrl_core_axi_read_in_responder_struct.xyz = rready_i; // + // Responder inout signals + // How to assign a signal, named xyz, from an initiator struct member. + // All available responder output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Responder output signals + // Responder inout signals + + @(posedge clk_i_i); + if (!first_transfer) begin + // Perform transfer response here. + // Reply using data recieved in the fuse_ctrl_core_axi_read_in_responder_struct. + @(posedge clk_i_i); + // Reply using data recieved in the transaction handle. + @(posedge clk_i_i); + end + // Wait for next transfer then gather info from intiator about the transfer. + // Place the data into the fuse_ctrl_core_axi_read_in_initiator_struct. + @(posedge clk_i_i); + @(posedge clk_i_i); + first_transfer = 0; + endtask +// pragma uvmf custom respond_and_wait_for_next_transfer end + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_if.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_if.sv new file mode 100644 index 0000000..b778c92 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_if.sv @@ -0,0 +1,124 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface contains the fuse_ctrl_core_axi_read_in interface signals. +// It is instantiated once per fuse_ctrl_core_axi_read_in bus. Bus Functional Models, +// BFM's named fuse_ctrl_core_axi_read_in_driver_bfm, are used to drive signals on the bus. +// BFM's named fuse_ctrl_core_axi_read_in_monitor_bfm are used to monitor signals on the +// bus. This interface signal bundle is passed in the port list of +// the BFM in order to give the BFM access to the signals in this +// interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// This template can be used to connect a DUT to these signals +// +// .dut_signal_port(fuse_ctrl_core_axi_read_in_bus.araddr), // Agent output +// .dut_signal_port(fuse_ctrl_core_axi_read_in_bus.arburst), // Agent output +// .dut_signal_port(fuse_ctrl_core_axi_read_in_bus.arsize), // Agent output +// .dut_signal_port(fuse_ctrl_core_axi_read_in_bus.arlen), // Agent output +// .dut_signal_port(fuse_ctrl_core_axi_read_in_bus.aruser), // Agent output +// .dut_signal_port(fuse_ctrl_core_axi_read_in_bus.arid), // Agent output +// .dut_signal_port(fuse_ctrl_core_axi_read_in_bus.arlock), // Agent output +// .dut_signal_port(fuse_ctrl_core_axi_read_in_bus.arvalid), // Agent output +// .dut_signal_port(fuse_ctrl_core_axi_read_in_bus.rready), // Agent output + +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_core_axi_read_in_pkg_hdl::*; + +interface fuse_ctrl_core_axi_read_in_if #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + + + ( + input tri clk_i, + input tri rst_ni, + inout tri [AW-1:0] araddr, + inout tri [$bits(axi_pkg::axi_burst_e)-1:0] arburst, + inout tri [2:0] arsize, + inout tri [7:0] arlen, + inout tri [UW-1:0] aruser, + inout tri [IW-1:0] arid, + inout tri arlock, + inout tri arvalid, + inout tri rready + ); + +modport monitor_port + ( + input clk_i, + input rst_ni, + input araddr, + input arburst, + input arsize, + input arlen, + input aruser, + input arid, + input arlock, + input arvalid, + input rready + ); + +modport initiator_port + ( + input clk_i, + input rst_ni, + output araddr, + output arburst, + output arsize, + output arlen, + output aruser, + output arid, + output arlock, + output arvalid, + output rready + ); + +modport responder_port + ( + input clk_i, + input rst_ni, + input araddr, + input arburst, + input arsize, + input arlen, + input aruser, + input arid, + input arlock, + input arvalid, + input rready + ); + + +// pragma uvmf custom interface_item_additional begin +// pragma uvmf custom interface_item_additional end + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_infact_coverage_strategy.csv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_infact_coverage_strategy.csv new file mode 100644 index 0000000..1c218e1 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_infact_coverage_strategy.csv @@ -0,0 +1,6 @@ +Global +auto_bin_max, 64 + +Name,Type,Include +rand_fields,coverpoint,=rand *.** + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_macros.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_macros.svh new file mode 100644 index 0000000..4ada88f --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_macros.svh @@ -0,0 +1,207 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains macros used with the fuse_ctrl_core_axi_read_in package. +// These macros include packed struct definitions. These structs are +// used to pass data between classes, hvl, and BFM's, hdl. Use of +// structs are more efficient and simpler to modify. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_struct +// and from_struct methods defined in the macros below that are used in +// the fuse_ctrl_core_axi_read_in_configuration class. +// + `define fuse_ctrl_core_axi_read_in_CONFIGURATION_STRUCT \ +typedef struct packed { \ + uvmf_active_passive_t active_passive; \ + uvmf_initiator_responder_t initiator_responder; \ + } fuse_ctrl_core_axi_read_in_configuration_s; + + `define fuse_ctrl_core_axi_read_in_CONFIGURATION_TO_STRUCT_FUNCTION \ + virtual function fuse_ctrl_core_axi_read_in_configuration_s to_struct();\ + fuse_ctrl_core_axi_read_in_configuration_struct = \ + {\ + this.active_passive,\ + this.initiator_responder\ + };\ + return ( fuse_ctrl_core_axi_read_in_configuration_struct );\ + endfunction + + `define fuse_ctrl_core_axi_read_in_CONFIGURATION_FROM_STRUCT_FUNCTION \ + virtual function void from_struct(fuse_ctrl_core_axi_read_in_configuration_s fuse_ctrl_core_axi_read_in_configuration_struct);\ + {\ + this.active_passive,\ + this.initiator_responder \ + } = fuse_ctrl_core_axi_read_in_configuration_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_monitor_struct +// and from_monitor_struct methods of the fuse_ctrl_core_axi_read_in_transaction class. +// + `define fuse_ctrl_core_axi_read_in_MONITOR_STRUCT typedef struct packed { \ + logic [AW-1:0] core_araddr ; \ + logic core_arvalid ; \ + logic [$bits(axi_pkg::axi_burst_e)] core_arburst ; \ + logic [2:0] core_arsize ; \ + logic [7:0] core_arlen ; \ + logic [UW-1:0] core_aruser ; \ + logic [IW-1:0] core_arid ; \ + logic core_arlock ; \ + logic core_rready ; \ + } fuse_ctrl_core_axi_read_in_monitor_s; + + `define fuse_ctrl_core_axi_read_in_TO_MONITOR_STRUCT_FUNCTION \ + virtual function fuse_ctrl_core_axi_read_in_monitor_s to_monitor_struct();\ + fuse_ctrl_core_axi_read_in_monitor_struct = \ + { \ + this.core_araddr , \ + this.core_arvalid , \ + this.core_arburst , \ + this.core_arsize , \ + this.core_arlen , \ + this.core_aruser , \ + this.core_arid , \ + this.core_arlock , \ + this.core_rready \ + };\ + return ( fuse_ctrl_core_axi_read_in_monitor_struct);\ + endfunction\ + + `define fuse_ctrl_core_axi_read_in_FROM_MONITOR_STRUCT_FUNCTION \ + virtual function void from_monitor_struct(fuse_ctrl_core_axi_read_in_monitor_s fuse_ctrl_core_axi_read_in_monitor_struct);\ + {\ + this.core_araddr , \ + this.core_arvalid , \ + this.core_arburst , \ + this.core_arsize , \ + this.core_arlen , \ + this.core_aruser , \ + this.core_arid , \ + this.core_arlock , \ + this.core_rready \ + } = fuse_ctrl_core_axi_read_in_monitor_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_initiator_struct +// and from_initiator_struct methods of the fuse_ctrl_core_axi_read_in_transaction class. +// Also update the comments in the driver BFM. +// + `define fuse_ctrl_core_axi_read_in_INITIATOR_STRUCT typedef struct packed { \ + logic [AW-1:0] core_araddr ; \ + logic core_arvalid ; \ + logic [$bits(axi_pkg::axi_burst_e)] core_arburst ; \ + logic [2:0] core_arsize ; \ + logic [7:0] core_arlen ; \ + logic [UW-1:0] core_aruser ; \ + logic [IW-1:0] core_arid ; \ + logic core_arlock ; \ + logic core_rready ; \ + } fuse_ctrl_core_axi_read_in_initiator_s; + + `define fuse_ctrl_core_axi_read_in_TO_INITIATOR_STRUCT_FUNCTION \ + virtual function fuse_ctrl_core_axi_read_in_initiator_s to_initiator_struct();\ + fuse_ctrl_core_axi_read_in_initiator_struct = \ + {\ + this.core_araddr , \ + this.core_arvalid , \ + this.core_arburst , \ + this.core_arsize , \ + this.core_arlen , \ + this.core_aruser , \ + this.core_arid , \ + this.core_arlock , \ + this.core_rready \ + };\ + return ( fuse_ctrl_core_axi_read_in_initiator_struct);\ + endfunction + + `define fuse_ctrl_core_axi_read_in_FROM_INITIATOR_STRUCT_FUNCTION \ + virtual function void from_initiator_struct(fuse_ctrl_core_axi_read_in_initiator_s fuse_ctrl_core_axi_read_in_initiator_struct);\ + {\ + this.core_araddr , \ + this.core_arvalid , \ + this.core_arburst , \ + this.core_arsize , \ + this.core_arlen , \ + this.core_aruser , \ + this.core_arid , \ + this.core_arlock , \ + this.core_rready \ + } = fuse_ctrl_core_axi_read_in_initiator_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_responder_struct +// and from_responder_struct methods of the fuse_ctrl_core_axi_read_in_transaction class. +// Also update the comments in the driver BFM. +// + `define fuse_ctrl_core_axi_read_in_RESPONDER_STRUCT typedef struct packed { \ + logic [AW-1:0] core_araddr ; \ + logic core_arvalid ; \ + logic [$bits(axi_pkg::axi_burst_e)] core_arburst ; \ + logic [2:0] core_arsize ; \ + logic [7:0] core_arlen ; \ + logic [UW-1:0] core_aruser ; \ + logic [IW-1:0] core_arid ; \ + logic core_arlock ; \ + logic core_rready ; \ + } fuse_ctrl_core_axi_read_in_responder_s; + + `define fuse_ctrl_core_axi_read_in_TO_RESPONDER_STRUCT_FUNCTION \ + virtual function fuse_ctrl_core_axi_read_in_responder_s to_responder_struct();\ + fuse_ctrl_core_axi_read_in_responder_struct = \ + {\ + this.core_araddr , \ + this.core_arvalid , \ + this.core_arburst , \ + this.core_arsize , \ + this.core_arlen , \ + this.core_aruser , \ + this.core_arid , \ + this.core_arlock , \ + this.core_rready \ + };\ + return ( fuse_ctrl_core_axi_read_in_responder_struct);\ + endfunction + + `define fuse_ctrl_core_axi_read_in_FROM_RESPONDER_STRUCT_FUNCTION \ + virtual function void from_responder_struct(fuse_ctrl_core_axi_read_in_responder_s fuse_ctrl_core_axi_read_in_responder_struct);\ + {\ + this.core_araddr , \ + this.core_arvalid , \ + this.core_arburst , \ + this.core_arsize , \ + this.core_arlen , \ + this.core_aruser , \ + this.core_arid , \ + this.core_arlock , \ + this.core_rready \ + } = fuse_ctrl_core_axi_read_in_responder_struct;\ + endfunction +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_monitor.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_monitor.svh new file mode 100644 index 0000000..62b74b3 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_monitor.svh @@ -0,0 +1,131 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class receives fuse_ctrl_core_axi_read_in transactions observed by the +// fuse_ctrl_core_axi_read_in monitor BFM and broadcasts them through the analysis port +// on the agent. It accesses the monitor BFM through the monitor +// task. This UVM component captures transactions +// for viewing in the waveform viewer if the +// enable_transaction_viewing flag is set in the configuration. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_read_in_monitor #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvmf_monitor_base #( + .CONFIG_T(fuse_ctrl_core_axi_read_in_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .BFM_BIND_T(virtual fuse_ctrl_core_axi_read_in_monitor_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .TRANS_T(fuse_ctrl_core_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +)); + + `uvm_component_param_utils( fuse_ctrl_core_axi_read_in_monitor #( + AW, + DW, + IW, + UW + ) +) + +// Structure used to pass data from monitor BFM to monitor class in agent. +// Use to_monitor_struct function to pack transaction variables into structure. +// Use from_monitor_struct function to unpack transaction variables from structure. +`fuse_ctrl_core_axi_read_in_MONITOR_STRUCT + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the monitor BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// monitor BFM. This allows the monitor BFM to call the notify_transaction +// function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// *************************************************************************** + virtual task run_phase(uvm_phase phase); + // Start monitor BFM thread and don't call super.run() in order to + // override the default monitor proxy 'pull' behavior with the more + // emulation-friendly BFM 'push' approach using the notify_transaction + // function below + bfm.start_monitoring(); + endtask + +// ************************************************************************** + +// This function is called by the monitor BFM. It receives data observed by the +// monitor BFM. Data is passed using the fuse_ctrl_core_axi_read_in_monitor_struct. + virtual function void notify_transaction(input fuse_ctrl_core_axi_read_in_monitor_s fuse_ctrl_core_axi_read_in_monitor_struct); + + + trans = new("trans"); + trans.from_monitor_struct(fuse_ctrl_core_axi_read_in_monitor_struct); + trans.start_time = time_stamp; + trans.end_time = $time; + time_stamp = trans.end_time; + + analyze(trans); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_monitor_bfm.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_monitor_bfm.sv new file mode 100644 index 0000000..13ea7d2 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_monitor_bfm.sv @@ -0,0 +1,232 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface performs the fuse_ctrl_core_axi_read_in signal monitoring. +// It is accessed by the uvm fuse_ctrl_core_axi_read_in monitor through a virtual +// interface handle in the fuse_ctrl_core_axi_read_in configuration. It monitors the +// signals passed in through the port connection named bus of +// type fuse_ctrl_core_axi_read_in_if. +// +// Input signals from the fuse_ctrl_core_axi_read_in_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// Interface functions and tasks used by UVM components: +// monitor(inout TRANS_T txn); +// This task receives the transaction, txn, from the +// UVM monitor and then populates variables in txn +// from values observed on bus activity. This task +// blocks until an operation on the fuse_ctrl_core_axi_read_in bus is complete. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_core_axi_read_in_pkg_hdl::*; +`include "src/fuse_ctrl_core_axi_read_in_macros.svh" + + +interface fuse_ctrl_core_axi_read_in_monitor_bfm #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + + ( fuse_ctrl_core_axi_read_in_if bus ); + // The pragma below and additional ones in-lined further down are for running this BFM on Veloce + // pragma attribute fuse_ctrl_core_axi_read_in_monitor_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: AW=%x DW=%x IW=%x UW=%x ", AW,DW,IW,UW), + UVM_DEBUG) +end +`endif + + + // Structure used to pass transaction data from monitor BFM to monitor class in agent. +`fuse_ctrl_core_axi_read_in_MONITOR_STRUCT + fuse_ctrl_core_axi_read_in_monitor_s fuse_ctrl_core_axi_read_in_monitor_struct; + + // Structure used to pass configuration data from monitor class to monitor BFM. + `fuse_ctrl_core_axi_read_in_CONFIGURATION_STRUCT + + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + tri clk_i_i; + tri rst_ni_i; + tri [AW-1:0] araddr_i; + tri [$bits(axi_pkg::axi_burst_e)-1:0] arburst_i; + tri [2:0] arsize_i; + tri [7:0] arlen_i; + tri [UW-1:0] aruser_i; + tri [IW-1:0] arid_i; + tri arlock_i; + tri arvalid_i; + tri rready_i; + assign clk_i_i = bus.clk_i; + assign rst_ni_i = bus.rst_ni; + assign araddr_i = bus.araddr; + assign arburst_i = bus.arburst; + assign arsize_i = bus.arsize; + assign arlen_i = bus.arlen; + assign aruser_i = bus.aruser; + assign arid_i = bus.arid; + assign arlock_i = bus.arlock; + assign arvalid_i = bus.arvalid; + assign rready_i = bus.rready; + + // Proxy handle to UVM monitor + fuse_ctrl_core_axi_read_in_pkg::fuse_ctrl_core_axi_read_in_monitor #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + proxy; + // pragma tbx oneway proxy.notify_transaction + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + task wait_for_reset();// pragma tbx xtf + @(posedge clk_i_i) ; + do_wait_for_reset(); + endtask + + // **************************************************************************** + task do_wait_for_reset(); + // pragma uvmf custom reset_condition begin + wait ( rst_ni_i === 1 ) ; + @(posedge clk_i_i) ; + // pragma uvmf custom reset_condition end + endtask + + //****************************************************************** + + task wait_for_num_clocks(input int unsigned count); // pragma tbx xtf + @(posedge clk_i_i); + + repeat (count-1) @(posedge clk_i_i); + endtask + + //****************************************************************** + event go; + function void start_monitoring();// pragma tbx xtf + -> go; + endfunction + + // **************************************************************************** + initial begin + @go; + forever begin + @(posedge clk_i_i); + do_monitor( fuse_ctrl_core_axi_read_in_monitor_struct ); + + + proxy.notify_transaction( fuse_ctrl_core_axi_read_in_monitor_struct ); + + end + end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the monitor BFM. It is called by the monitor within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the monitor BFM needs to be aware of the new configuration + // variables. + // + function void configure(fuse_ctrl_core_axi_read_in_configuration_s fuse_ctrl_core_axi_read_in_configuration_arg); // pragma tbx xtf + initiator_responder = fuse_ctrl_core_axi_read_in_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + + + // **************************************************************************** + + task do_monitor(output fuse_ctrl_core_axi_read_in_monitor_s fuse_ctrl_core_axi_read_in_monitor_struct); + // + // Available struct members: + // // fuse_ctrl_core_axi_read_in_monitor_struct.core_araddr + // // fuse_ctrl_core_axi_read_in_monitor_struct.core_arvalid + // // fuse_ctrl_core_axi_read_in_monitor_struct.core_arburst + // // fuse_ctrl_core_axi_read_in_monitor_struct.core_arsize + // // fuse_ctrl_core_axi_read_in_monitor_struct.core_arlen + // // fuse_ctrl_core_axi_read_in_monitor_struct.core_aruser + // // fuse_ctrl_core_axi_read_in_monitor_struct.core_arid + // // fuse_ctrl_core_axi_read_in_monitor_struct.core_arlock + // // fuse_ctrl_core_axi_read_in_monitor_struct.core_rready + // // + // Reference code; + // How to wait for signal value + // while (control_signal === 1'b1) @(posedge clk_i_i); + // + // How to assign a struct member, named xyz, from a signal. + // All available input signals listed. + // fuse_ctrl_core_axi_read_in_monitor_struct.xyz = araddr_i; // [AW-1:0] + // fuse_ctrl_core_axi_read_in_monitor_struct.xyz = arburst_i; // [$bits(axi_pkg::axi_burst_e)-1:0] + // fuse_ctrl_core_axi_read_in_monitor_struct.xyz = arsize_i; // [2:0] + // fuse_ctrl_core_axi_read_in_monitor_struct.xyz = arlen_i; // [7:0] + // fuse_ctrl_core_axi_read_in_monitor_struct.xyz = aruser_i; // [UW-1:0] + // fuse_ctrl_core_axi_read_in_monitor_struct.xyz = arid_i; // [IW-1:0] + // fuse_ctrl_core_axi_read_in_monitor_struct.xyz = arlock_i; // + // fuse_ctrl_core_axi_read_in_monitor_struct.xyz = arvalid_i; // + // fuse_ctrl_core_axi_read_in_monitor_struct.xyz = rready_i; // + // pragma uvmf custom do_monitor begin + // UVMF_CHANGE_ME : Implement protocol monitoring. The commented reference code + // below are examples of how to capture signal values and assign them to + // structure members. All available input signals are listed. The 'while' + // code example shows how to wait for a synchronous flow control signal. This + // task should return when a complete transfer has been observed. Once this task is + // exited with captured values, it is then called again to wait for and observe + // the next transfer. One clock cycle is consumed between calls to do_monitor. + @(posedge clk_i_i); + @(posedge clk_i_i); + @(posedge clk_i_i); + @(posedge clk_i_i); + // pragma uvmf custom do_monitor end + endtask + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_random_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_random_sequence.svh new file mode 100644 index 0000000..ce6f4ef --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_random_sequence.svh @@ -0,0 +1,91 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This sequences randomizes the fuse_ctrl_core_axi_read_in transaction and sends it +// to the UVM driver. +// +// This sequence constructs and randomizes a fuse_ctrl_core_axi_read_in_transaction. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_read_in_random_sequence #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + + extends fuse_ctrl_core_axi_read_in_sequence_base #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +; + + `uvm_object_param_utils( fuse_ctrl_core_axi_read_in_random_sequence #( + AW, + DW, + IW, + UW + ) +) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //***************************************************************** + function new(string name = ""); + super.new(name); + endfunction: new + + // **************************************************************************** + // TASK : body() + // This task is automatically executed when this sequence is started using the + // start(sequencerHandle) task. + // + task body(); + + // Construct the transaction + req=fuse_ctrl_core_axi_read_in_transaction#( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +::type_id::create("req"); + start_item(req); + // Randomize the transaction + if(!req.randomize()) `uvm_fatal("SEQ", "fuse_ctrl_core_axi_read_in_random_sequence::body()-fuse_ctrl_core_axi_read_in_transaction randomization failed") + // Send the transaction to the fuse_ctrl_core_axi_read_in_driver_bfm via the sequencer and fuse_ctrl_core_axi_read_in_driver. + finish_item(req); + `uvm_info("SEQ", {"Response:",req.convert2string()},UVM_MEDIUM) + + endtask + +endclass: fuse_ctrl_core_axi_read_in_random_sequence + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_responder_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_responder_sequence.svh new file mode 100644 index 0000000..44a3b25 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_responder_sequence.svh @@ -0,0 +1,87 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class can be used to provide stimulus when an interface +// has been configured to run in a responder mode. It +// will never finish by default, always going back to the driver +// and driver BFM for the next transaction with which to respond. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_read_in_responder_sequence #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + + extends fuse_ctrl_core_axi_read_in_sequence_base #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +; + + `uvm_object_param_utils( fuse_ctrl_core_axi_read_in_responder_sequence #( + AW, + DW, + IW, + UW + ) +) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "fuse_ctrl_core_axi_read_in_responder_sequence"); + super.new(name); + endfunction + + task body(); + req=fuse_ctrl_core_axi_read_in_transaction#( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +::type_id::create("req"); + forever begin + start_item(req); + finish_item(req); + // pragma uvmf custom body begin + // UVMF_CHANGE_ME : Do something here with the resulting req item. The + // finish_item() call above will block until the req transaction is ready + // to be handled by the responder sequence. + // If this was an item that required a response, the expectation is + // that the response should be populated within this transaction now. + `uvm_info("SEQ",$sformatf("Processed txn: %s",req.convert2string()),UVM_HIGH) + // pragma uvmf custom body end + end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_sequence_base.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_sequence_base.svh new file mode 100644 index 0000000..bb92d24 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_sequence_base.svh @@ -0,0 +1,146 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the class used as the base class for all sequences +// for this interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_read_in_sequence_base #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvmf_sequence_base #( + .REQ(fuse_ctrl_core_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .RSP(fuse_ctrl_core_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +)); + + `uvm_object_param_utils( fuse_ctrl_core_axi_read_in_sequence_base #( + AW, + DW, + IW, + UW + ) +) + + // variables + typedef fuse_ctrl_core_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + fuse_ctrl_core_axi_read_in_transaction_req_t; + fuse_ctrl_core_axi_read_in_transaction_req_t req; + typedef fuse_ctrl_core_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + fuse_ctrl_core_axi_read_in_transaction_rsp_t; + fuse_ctrl_core_axi_read_in_transaction_rsp_t rsp; + + // Event for identifying when a response was received from the sequencer + event new_rsp; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // TASK : get_responses() + // This task recursively gets sequence item responses from the sequencer. + // + virtual task get_responses(); + fork + begin + // Block until new rsp available + get_response(rsp); + // New rsp received. Indicate to sequence using event. + ->new_rsp; + // Display the received response transaction + `uvm_info("SEQ", {"New response transaction:",rsp.convert2string()}, UVM_MEDIUM) + end + join_none + endtask + + // **************************************************************************** + // TASK : pre_body() + // This task is called automatically when start is called with call_pre_post set to 1 (default). + // By calling get_responses() within pre_body() any derived sequences are automatically + // processing response transactions. Only un-comment this call to get_responses() if you + // have configured the interface driver to utilize the response transaction path by setting + // the configuration variable "return_transaction_response" to 1. Otherwise it is possible + // to impact runtime performance and memory utilization. + // + virtual task pre_body(); + // pragma uvmf custom pre_body begin +// get_responses(); + // pragma uvmf custom pre_body end + endtask + + // **************************************************************************** + // TASK : body() + // This task is called automatically when start is called. This sequence sends + // a req sequence item to the sequencer identified as an argument in the call + // to start. + // + virtual task body(); + // pragma uvmf custom body begin + start_item(req); + finish_item(req); + // pragma uvmf custom body end + endtask + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name =""); + super.new( name ); + // pragma uvmf custom new begin + req = fuse_ctrl_core_axi_read_in_transaction_req_t::type_id::create("req"); + rsp = fuse_ctrl_core_axi_read_in_transaction_rsp_t::type_id::create("rsp"); + // pragma uvmf custom new end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_transaction.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_transaction.svh new file mode 100644 index 0000000..39e8f97 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_transaction.svh @@ -0,0 +1,243 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class defines the variables required for an fuse_ctrl_core_axi_read_in +// transaction. Class variables to be displayed in waveform transaction +// viewing are added to the transaction viewing stream in the add_to_wave +// function. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_read_in_transaction #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvmf_transaction_base; + + `uvm_object_param_utils( fuse_ctrl_core_axi_read_in_transaction #( + AW, + DW, + IW, + UW + ) +) + + rand logic [AW-1:0] core_araddr ; + logic core_arvalid ; + logic [$bits(axi_pkg::axi_burst_e)] core_arburst ; + logic [2:0] core_arsize ; + logic [7:0] core_arlen ; + logic [UW-1:0] core_aruser ; + logic [IW-1:0] core_arid ; + logic core_arlock ; + logic core_rready ; + + //Constraints for the transaction variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //******************************************************************* + //******************************************************************* + // Macros that define structs and associated functions are + // located in fuse_ctrl_core_axi_read_in_macros.svh + + //******************************************************************* + // Monitor macro used by fuse_ctrl_core_axi_read_in_monitor and fuse_ctrl_core_axi_read_in_monitor_bfm + // This struct is defined in fuse_ctrl_core_axi_read_in_macros.svh + `fuse_ctrl_core_axi_read_in_MONITOR_STRUCT + fuse_ctrl_core_axi_read_in_monitor_s fuse_ctrl_core_axi_read_in_monitor_struct; + //******************************************************************* + // FUNCTION: to_monitor_struct() + // This function packs transaction variables into a fuse_ctrl_core_axi_read_in_monitor_s + // structure. The function returns the handle to the fuse_ctrl_core_axi_read_in_monitor_struct. + // This function is defined in fuse_ctrl_core_axi_read_in_macros.svh + `fuse_ctrl_core_axi_read_in_TO_MONITOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_monitor_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_core_axi_read_in_macros.svh + `fuse_ctrl_core_axi_read_in_FROM_MONITOR_STRUCT_FUNCTION + + //******************************************************************* + // Initiator macro used by fuse_ctrl_core_axi_read_in_driver and fuse_ctrl_core_axi_read_in_driver_bfm + // to communicate initiator driven data to fuse_ctrl_core_axi_read_in_driver_bfm. + // This struct is defined in fuse_ctrl_core_axi_read_in_macros.svh + `fuse_ctrl_core_axi_read_in_INITIATOR_STRUCT + fuse_ctrl_core_axi_read_in_initiator_s fuse_ctrl_core_axi_read_in_initiator_struct; + //******************************************************************* + // FUNCTION: to_initiator_struct() + // This function packs transaction variables into a fuse_ctrl_core_axi_read_in_initiator_s + // structure. The function returns the handle to the fuse_ctrl_core_axi_read_in_initiator_struct. + // This function is defined in fuse_ctrl_core_axi_read_in_macros.svh + `fuse_ctrl_core_axi_read_in_TO_INITIATOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_initiator_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_core_axi_read_in_macros.svh + `fuse_ctrl_core_axi_read_in_FROM_INITIATOR_STRUCT_FUNCTION + + //******************************************************************* + // Responder macro used by fuse_ctrl_core_axi_read_in_driver and fuse_ctrl_core_axi_read_in_driver_bfm + // to communicate Responder driven data to fuse_ctrl_core_axi_read_in_driver_bfm. + // This struct is defined in fuse_ctrl_core_axi_read_in_macros.svh + `fuse_ctrl_core_axi_read_in_RESPONDER_STRUCT + fuse_ctrl_core_axi_read_in_responder_s fuse_ctrl_core_axi_read_in_responder_struct; + //******************************************************************* + // FUNCTION: to_responder_struct() + // This function packs transaction variables into a fuse_ctrl_core_axi_read_in_responder_s + // structure. The function returns the handle to the fuse_ctrl_core_axi_read_in_responder_struct. + // This function is defined in fuse_ctrl_core_axi_read_in_macros.svh + `fuse_ctrl_core_axi_read_in_TO_RESPONDER_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_responder_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_core_axi_read_in_macros.svh + `fuse_ctrl_core_axi_read_in_FROM_RESPONDER_STRUCT_FUNCTION + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + endfunction + + // **************************************************************************** + // FUNCTION: convert2string() + // This function converts all variables in this class to a single string for + // logfile reporting. + // + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + // UVMF_CHANGE_ME : Customize format if desired. + return $sformatf("core_araddr:0x%x core_arvalid:0x%x core_arburst:0x%x core_arsize:0x%x core_arlen:0x%x core_aruser:0x%x core_arid:0x%x core_arlock:0x%x core_rready:0x%x ",core_araddr,core_arvalid,core_arburst,core_arsize,core_arlen,core_aruser,core_arid,core_arlock,core_rready); + // pragma uvmf custom convert2string end + endfunction + + //******************************************************************* + // FUNCTION: do_print() + // This function is automatically called when the .print() function + // is called on this class. + // + virtual function void do_print(uvm_printer printer); + // pragma uvmf custom do_print begin + // UVMF_CHANGE_ME : Current contents of do_print allows for the use of UVM 1.1d, 1.2 or P1800.2. + // Update based on your own printing preference according to your preferred UVM version + $display(convert2string()); + // pragma uvmf custom do_print end + endfunction + + //******************************************************************* + // FUNCTION: do_compare() + // This function is automatically called when the .compare() function + // is called on this class. + // + virtual function bit do_compare (uvm_object rhs, uvm_comparer comparer); + fuse_ctrl_core_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + RHS; + if (!$cast(RHS,rhs)) return 0; + // pragma uvmf custom do_compare begin + // UVMF_CHANGE_ME : Eliminate comparison of variables not to be used for compare + return (super.do_compare(rhs,comparer) + ); + // pragma uvmf custom do_compare end + endfunction + + //******************************************************************* + // FUNCTION: do_copy() + // This function is automatically called when the .copy() function + // is called on this class. + // + virtual function void do_copy (uvm_object rhs); + fuse_ctrl_core_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + RHS; + assert($cast(RHS,rhs)); + // pragma uvmf custom do_copy begin + super.do_copy(rhs); + this.core_araddr = RHS.core_araddr; + this.core_arvalid = RHS.core_arvalid; + this.core_arburst = RHS.core_arburst; + this.core_arsize = RHS.core_arsize; + this.core_arlen = RHS.core_arlen; + this.core_aruser = RHS.core_aruser; + this.core_arid = RHS.core_arid; + this.core_arlock = RHS.core_arlock; + this.core_rready = RHS.core_rready; + // pragma uvmf custom do_copy end + endfunction + + // **************************************************************************** + // FUNCTION: add_to_wave() + // This function is used to display variables in this class in the waveform + // viewer. The start_time and end_time variables must be set before this + // function is called. If the start_time and end_time variables are not set + // the transaction will be hidden at 0ns on the waveform display. + // + virtual function void add_to_wave(int transaction_viewing_stream_h); + `ifdef QUESTA + if (transaction_view_h == 0) begin + transaction_view_h = $begin_transaction(transaction_viewing_stream_h,"fuse_ctrl_core_axi_read_in_transaction",start_time); + end + super.add_to_wave(transaction_view_h); + // pragma uvmf custom add_to_wave begin + // UVMF_CHANGE_ME : Color can be applied to transaction entries based on content, example below + // case() + // 1 : $add_color(transaction_view_h,"red"); + // default : $add_color(transaction_view_h,"grey"); + // endcase + // UVMF_CHANGE_ME : Eliminate transaction variables not wanted in transaction viewing in the waveform viewer + $add_attribute(transaction_view_h,core_araddr,"core_araddr"); + $add_attribute(transaction_view_h,core_arvalid,"core_arvalid"); + $add_attribute(transaction_view_h,core_arburst,"core_arburst"); + $add_attribute(transaction_view_h,core_arsize,"core_arsize"); + $add_attribute(transaction_view_h,core_arlen,"core_arlen"); + $add_attribute(transaction_view_h,core_aruser,"core_aruser"); + $add_attribute(transaction_view_h,core_arid,"core_arid"); + $add_attribute(transaction_view_h,core_arlock,"core_arlock"); + $add_attribute(transaction_view_h,core_rready,"core_rready"); + // pragma uvmf custom add_to_wave end + $end_transaction(transaction_view_h,end_time); + $free_transaction(transaction_view_h); + `endif // QUESTA + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_transaction_coverage.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_transaction_coverage.svh new file mode 100644 index 0000000..b172524 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_transaction_coverage.svh @@ -0,0 +1,110 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class records fuse_ctrl_core_axi_read_in transaction information using +// a covergroup named fuse_ctrl_core_axi_read_in_transaction_cg. An instance of this +// coverage component is instantiated in the uvmf_parameterized_agent +// if the has_coverage flag is set. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_read_in_transaction_coverage #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvm_subscriber #(.T(fuse_ctrl_core_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +)); + + `uvm_component_param_utils( fuse_ctrl_core_axi_read_in_transaction_coverage #( + AW, + DW, + IW, + UW + ) +) + + T coverage_trans; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + covergroup fuse_ctrl_core_axi_read_in_transaction_cg; + // pragma uvmf custom covergroup begin + // UVMF_CHANGE_ME : Add coverage bins, crosses, exclusions, etc. according to coverage needs. + option.auto_bin_max=1024; + option.per_instance=1; + core_araddr: coverpoint coverage_trans.core_araddr; + core_arvalid: coverpoint coverage_trans.core_arvalid; + core_arburst: coverpoint coverage_trans.core_arburst; + core_arsize: coverpoint coverage_trans.core_arsize; + core_arlen: coverpoint coverage_trans.core_arlen; + core_aruser: coverpoint coverage_trans.core_aruser; + core_arid: coverpoint coverage_trans.core_arid; + core_arlock: coverpoint coverage_trans.core_arlock; + core_rready: coverpoint coverage_trans.core_rready; + // pragma uvmf custom covergroup end + endgroup + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new(string name="", uvm_component parent=null); + super.new(name,parent); + fuse_ctrl_core_axi_read_in_transaction_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that transaction variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + endfunction + + // **************************************************************************** + // FUNCTION : build_phase() + // This function is the standard UVM build_phase. + // + function void build_phase(uvm_phase phase); + fuse_ctrl_core_axi_read_in_transaction_cg.set_inst_name($sformatf("fuse_ctrl_core_axi_read_in_transaction_cg_%s",get_full_name())); + endfunction + + // **************************************************************************** + // FUNCTION: write (T t) + // This function is automatically executed when a transaction arrives on the + // analysis_export. It copies values from the variables in the transaction + // to local variables used to collect functional coverage. + // + virtual function void write (T t); + `uvm_info("COV","Received transaction",UVM_HIGH); + coverage_trans = t; + fuse_ctrl_core_axi_read_in_transaction_cg.sample(); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_typedefs.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_typedefs.svh new file mode 100644 index 0000000..f2a7bdb --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_typedefs.svh @@ -0,0 +1,34 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the host server when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_typedefs_hdl.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_typedefs_hdl.svh new file mode 100644 index 0000000..0d58518 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/src/fuse_ctrl_core_axi_read_in_typedefs_hdl.svh @@ -0,0 +1,35 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the emulator when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/yaml/fuse_ctrl_core_axi_read_in_interface.yaml b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/yaml/fuse_ctrl_core_axi_read_in_interface.yaml new file mode 100644 index 0000000..85b8443 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_in_pkg/yaml/fuse_ctrl_core_axi_read_in_interface.yaml @@ -0,0 +1,121 @@ +uvmf: + interfaces: + fuse_ctrl_core_axi_read_in: + clock: clk_i + config_constraints: [] + config_vars: [] + existing_library_component: 'True' + gen_inbound_streaming_driver: 'False' + hdl_pkg_parameters: [] + hdl_typedefs: [] + hvl_pkg_parameters: [] + hvl_typedefs: [] + parameters: + - name: AW + type: int + value: '32' + - name: DW + type: int + value: '32' + - name: IW + type: int + value: '3' + - name: UW + type: int + value: '32' + ports: + - dir: output + name: araddr + reset_value: '''bz' + width: '[''AW'']' + - dir: output + name: arburst + reset_value: '''bz' + width: '[''$bits(axi_pkg::axi_burst_e)'']' + - dir: output + name: arsize + reset_value: '''bz' + width: '3' + - dir: output + name: arlen + reset_value: '''bz' + width: '8' + - dir: output + name: aruser + reset_value: '''bz' + width: '[''UW'']' + - dir: output + name: arid + reset_value: '''bz' + width: '[''IW'']' + - dir: output + name: arlock + reset_value: '''bz' + width: '1' + - dir: output + name: arvalid + reset_value: '''bz' + width: '1' + - dir: output + name: rready + reset_value: '''bz' + width: '1' + reset: rst_ni + reset_assertion_level: 'False' + transaction_constraints: [] + transaction_vars: + - comment: '' + iscompare: 'False' + isrand: 'True' + name: core_araddr + type: logic [AW-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: core_arvalid + type: logic + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: core_arburst + type: logic [$bits(axi_pkg::axi_burst_e)] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: core_arsize + type: logic [2:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: core_arlen + type: logic [7:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: core_aruser + type: logic [UW-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: core_arid + type: logic [IW-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: core_arlock + type: logic + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: core_rready + type: logic + unpacked_dimension: '' + use_dpi_link: 'False' diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/.project b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/.project new file mode 100644 index 0000000..23723dd --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/.project @@ -0,0 +1,30 @@ + + + fuse_ctrl_core_axi_read_out_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/.svproject b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/.svproject new file mode 100644 index 0000000..b74d826 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/Makefile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/Makefile new file mode 100644 index 0000000..673e00d --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/Makefile @@ -0,0 +1,66 @@ +# fuse_ctrl_core_axi_read_out interface packages source +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +fuse_ctrl_core_axi_read_out_PKG = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_read_out_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_filelist_hvl.f + +fuse_ctrl_core_axi_read_out_PKG_HDL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_read_out_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_filelist_hdl.f + +fuse_ctrl_core_axi_read_out_PKG_XRTL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_read_out_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_filelist_xrtl.f + +COMP_fuse_ctrl_core_axi_read_out_PKG_TGT_0 = q_comp_fuse_ctrl_core_axi_read_out_pkg +COMP_fuse_ctrl_core_axi_read_out_PKG_TGT_1 = v_comp_fuse_ctrl_core_axi_read_out_pkg +COMP_fuse_ctrl_core_axi_read_out_PKG_TGT = $(COMP_fuse_ctrl_core_axi_read_out_PKG_TGT_$(USE_VELOCE)) + +comp_fuse_ctrl_core_axi_read_out_pkg: $(COMP_fuse_ctrl_core_axi_read_out_PKG_TGT) + +q_comp_fuse_ctrl_core_axi_read_out_pkg: + $(HDL_COMP_CMD) $(fuse_ctrl_core_axi_read_out_PKG_HDL) + $(HVL_COMP_CMD) $(fuse_ctrl_core_axi_read_out_PKG) + $(HDL_COMP_CMD) $(fuse_ctrl_core_axi_read_out_PKG_XRTL) + +v_comp_fuse_ctrl_core_axi_read_out_pkg: + $(HVL_COMP_CMD) $(fuse_ctrl_core_axi_read_out_PKG_HDL) + $(HVL_COMP_CMD) $(fuse_ctrl_core_axi_read_out_PKG) + $(VELANALYZE_CMD) $(fuse_ctrl_core_axi_read_out_PKG_HDL) + $(VELANALYZE_HVL_CMD) $(fuse_ctrl_core_axi_read_out_PKG) + $(HDL_COMP_CMD) $(fuse_ctrl_core_axi_read_out_PKG_XRTL) + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export fuse_ctrl_core_axi_read_out_IF_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_read_out_pkg/dpi + +C_FILE_COMPILE_LIST_fuse_ctrl_core_axi_read_out_pkg = \ + +O_FILE_COMPILE_LIST_fuse_ctrl_core_axi_read_out_pkg = $(notdir $(C_FILE_COMPILE_LIST_fuse_ctrl_core_axi_read_out_pkg:.c=.o)) + +GCC_COMP_ARGS_fuse_ctrl_core_axi_read_out_pkg += -I$(fuse_ctrl_core_axi_read_out_IF_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_fuse_ctrl_core_axi_read_out_pkg += $(fuse_ctrl_core_axi_read_out_IF_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_fuse_ctrl_core_axi_read_out_pkg += \ + \ + -o .so + +comp_fuse_ctrl_core_axi_read_out_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Interface C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_fuse_ctrl_core_axi_read_out_pkg) $(C_FILE_COMPILE_LIST_fuse_ctrl_core_axi_read_out_pkg) + @echo "--------------------------------" + @echo "Linking Interface C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_fuse_ctrl_core_axi_read_out_pkg) $(O_FILE_COMPILE_LIST_fuse_ctrl_core_axi_read_out_pkg) + @echo "--------------------------------" + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/compile.do b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/compile.do new file mode 100644 index 0000000..5e6a9fd --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/compile.do @@ -0,0 +1,14 @@ +# Tcl do file for compile of fuse_ctrl_core_axi_read_out interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_read_out_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_filelist_hdl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_read_out_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_filelist_hvl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_read_out_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_filelist_xrtl.f \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out.compile new file mode 100644 index 0000000..ad96a80 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out.compile @@ -0,0 +1,3 @@ +needs: + - fuse_ctrl_core_axi_read_out_hvl.compile + - fuse_ctrl_core_axi_read_out_hdl.compile diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_bfm.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_bfm.vinfo new file mode 100644 index 0000000..03fc49a --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_bfm.vinfo @@ -0,0 +1,6 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use fuse_ctrl_core_axi_read_out_pkg_hdl.vinfo ++incdir+@vinfodir +src/fuse_ctrl_core_axi_read_out_if.sv +src/fuse_ctrl_core_axi_read_out_driver_bfm.sv +src/fuse_ctrl_core_axi_read_out_monitor_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_common.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_common.compile new file mode 100644 index 0000000..84d4f2e --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_common.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +incdir: + - . + - ${uvm_path}/src +src: + - fuse_ctrl_core_axi_read_out_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_filelist_hdl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_filelist_hdl.f new file mode 100644 index 0000000..2debd1c --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_filelist_hdl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_filelist_hvl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_filelist_hvl.f new file mode 100644 index 0000000..8e9b75a --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_filelist_hvl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_pkg.sv \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_filelist_xrtl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_filelist_xrtl.f new file mode 100644 index 0000000..4b0eaa2 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_filelist_xrtl.f @@ -0,0 +1,3 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_if.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_monitor_bfm.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_driver_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_hdl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_hdl.compile new file mode 100644 index 0000000..5b16e75 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_hdl.compile @@ -0,0 +1,9 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ./fuse_ctrl_core_axi_read_out_common.compile +incdir: + - . +src: + - src/fuse_ctrl_core_axi_read_out_if.sv + - src/fuse_ctrl_core_axi_read_out_monitor_bfm.sv + - src/fuse_ctrl_core_axi_read_out_driver_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_hvl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_hvl.compile new file mode 100644 index 0000000..a240210 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_hvl.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ./fuse_ctrl_core_axi_read_out_common.compile +incdir: + - . +src: + - fuse_ctrl_core_axi_read_out_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_pkg.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_pkg.sv new file mode 100644 index 0000000..d297db4 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_pkg.sv @@ -0,0 +1,91 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - + +// - +// - +// - + +// - +// - +// - + +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_core_axi_read_out_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg_hdl::*; + import uvmf_base_pkg::*; + import fuse_ctrl_core_axi_read_out_pkg_hdl::*; + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + `include "src/fuse_ctrl_core_axi_read_out_macros.svh" + + export fuse_ctrl_core_axi_read_out_pkg_hdl::*; + + + + // Parameters defined as HVL parameters + + `include "src/fuse_ctrl_core_axi_read_out_typedefs.svh" + `include "src/fuse_ctrl_core_axi_read_out_transaction.svh" + + `include "src/fuse_ctrl_core_axi_read_out_configuration.svh" + `include "src/fuse_ctrl_core_axi_read_out_driver.svh" + `include "src/fuse_ctrl_core_axi_read_out_monitor.svh" + + `include "src/fuse_ctrl_core_axi_read_out_transaction_coverage.svh" + `include "src/fuse_ctrl_core_axi_read_out_sequence_base.svh" + `include "src/fuse_ctrl_core_axi_read_out_random_sequence.svh" + + `include "src/fuse_ctrl_core_axi_read_out_responder_sequence.svh" + `include "src/fuse_ctrl_core_axi_read_out2reg_adapter.svh" + + `include "src/fuse_ctrl_core_axi_read_out_agent.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new interface sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the interface package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_pkg.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_pkg.vinfo new file mode 100644 index 0000000..50e86c0 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_pkg.vinfo @@ -0,0 +1,4 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use fuse_ctrl_core_axi_read_out_pkg_hdl.vinfo ++incdir+@vinfodir +fuse_ctrl_core_axi_read_out_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_pkg_hdl.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_pkg_hdl.sv new file mode 100644 index 0000000..0e4cd58 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_pkg_hdl.sv @@ -0,0 +1,52 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that needs to be compiled and synthesized +// for running on Veloce. +// +// CONTAINS: +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_core_axi_read_out_pkg_hdl; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HDL parameters + + `include "src/fuse_ctrl_core_axi_read_out_typedefs_hdl.svh" + `include "src/fuse_ctrl_core_axi_read_out_macros.svh" + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_pkg_hdl.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_pkg_hdl.vinfo new file mode 100644 index 0000000..b7569b9 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_pkg_hdl.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +fuse_ctrl_core_axi_read_out_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_pkg_sve.F b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_pkg_sve.F new file mode 100644 index 0000000..531457d --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_pkg_sve.F @@ -0,0 +1,10 @@ +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + ++incdir+. +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_filelist_hdl.f +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_core_axi_read_out_pkg/fuse_ctrl_core_axi_read_out_filelist_hvl.f diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out2reg_adapter.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out2reg_adapter.svh new file mode 100644 index 0000000..44bdb87 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out2reg_adapter.svh @@ -0,0 +1,142 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the UVM register adapter for the fuse_ctrl_core_axi_read_out interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_read_out2reg_adapter #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvm_reg_adapter; + + `uvm_object_param_utils( fuse_ctrl_core_axi_read_out2reg_adapter #( + AW, + DW, + IW, + UW + ) +) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //-------------------------------------------------------------------- + // new + //-------------------------------------------------------------------- + function new (string name = "fuse_ctrl_core_axi_read_out2reg_adapter" ); + super.new(name); + // pragma uvmf custom new begin + // UVMF_CHANGE_ME : Configure the adapter regarding byte enables and provides response. + + // Does the protocol the Agent is modeling support byte enables? + // 0 = NO + // 1 = YES + supports_byte_enable = 0; + + // Does the Agent's Driver provide separate response sequence items? + // i.e. Does the driver call seq_item_port.put() + // and do the sequences call get_response()? + // 0 = NO + // 1 = YES + provides_responses = 0; + // pragma uvmf custom new end + + endfunction: new + + //-------------------------------------------------------------------- + // reg2bus + //-------------------------------------------------------------------- + virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw); + + fuse_ctrl_core_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + trans_h = fuse_ctrl_core_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +::type_id::create("trans_h"); + + // pragma uvmf custom reg2bus begin + // UVMF_CHANGE_ME : Fill in the reg2bus adapter mapping registe fields to protocol fields. + + //Adapt the following for your sequence item type + // trans_h.op = (rw.kind == UVM_READ) ? WB_READ : WB_WRITE; + //Copy over address + // trans_h.addr = rw.addr; + //Copy over write data + // trans_h.data = rw.data; + + // pragma uvmf custom reg2bus end + + // Return the adapted transaction + return trans_h; + + endfunction: reg2bus + + //-------------------------------------------------------------------- + // bus2reg + //-------------------------------------------------------------------- + virtual function void bus2reg(uvm_sequence_item bus_item, + ref uvm_reg_bus_op rw); + fuse_ctrl_core_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + trans_h; + if (!$cast(trans_h, bus_item)) begin + `uvm_fatal("ADAPT","Provided bus_item is not of the correct type") + return; + end + // pragma uvmf custom bus2reg begin + // UVMF_CHANGE_ME : Fill in the bus2reg adapter mapping protocol fields to register fields. + //Adapt the following for your sequence item type + //Copy over instruction type + // rw.kind = (trans_h.op == WB_WRITE) ? UVM_WRITE : UVM_READ; + //Copy over address + // rw.addr = trans_h.addr; + //Copy over read data + // rw.data = trans_h.data; + //Check for errors on the bus and return UVM_NOT_OK if there is an error + // rw.status = UVM_IS_OK; + // pragma uvmf custom bus2reg end + + endfunction: bus2reg + +endclass : fuse_ctrl_core_axi_read_out2reg_adapter + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_agent.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_agent.svh new file mode 100644 index 0000000..4c2bae4 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_agent.svh @@ -0,0 +1,109 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: Protocol specific agent class definition +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_read_out_agent #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvmf_parameterized_agent #( + .CONFIG_T(fuse_ctrl_core_axi_read_out_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .DRIVER_T(fuse_ctrl_core_axi_read_out_driver #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .MONITOR_T(fuse_ctrl_core_axi_read_out_monitor #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .COVERAGE_T(fuse_ctrl_core_axi_read_out_transaction_coverage #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .TRANS_T(fuse_ctrl_core_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +) + ); + + `uvm_component_param_utils( fuse_ctrl_core_axi_read_out_agent #( + AW, + DW, + IW, + UW + ) +) + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** + // FUNCTION: build_phase + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + if (configuration.active_passive == ACTIVE) begin + // Place sequencer handle into configuration object + // so that it may be retrieved from configuration + // rather than using uvm_config_db + configuration.sequencer = this.sequencer; + end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_configuration.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_configuration.svh new file mode 100644 index 0000000..cadcf88 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_configuration.svh @@ -0,0 +1,241 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class contains all variables and functions used +// to configure the fuse_ctrl_core_axi_read_out agent and its bfm's. It gets the +// bfm's from the uvm_config_db for use by the agent. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_read_out_configuration #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvmf_parameterized_agent_configuration_base #( + .DRIVER_BFM_BIND_T(virtual fuse_ctrl_core_axi_read_out_driver_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .MONITOR_BFM_BIND_T( virtual fuse_ctrl_core_axi_read_out_monitor_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +)); + + `uvm_object_param_utils( fuse_ctrl_core_axi_read_out_configuration #( + AW, + DW, + IW, + UW + ) +) + + + // Sequencer handle populated by agent + uvm_sequencer #(fuse_ctrl_core_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + ) sequencer; + + //Constraints for the configuration variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + covergroup fuse_ctrl_core_axi_read_out_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + // pragma uvmf custom covergroup end + endgroup + + //******************************************************************* + //******************************************************************* + // Structure used to pass configuration variables to monitor and driver BFM's. + // Use to_struct function to pack variables into structure. + // Use from_struct function to unpack variables from structure. + // This structure is defined in fuse_ctrl_core_axi_read_out_macros.svh + `fuse_ctrl_core_axi_read_out_CONFIGURATION_STRUCT + fuse_ctrl_core_axi_read_out_configuration_s fuse_ctrl_core_axi_read_out_configuration_struct; + //******************************************************************* + // FUNCTION: to_struct() + // This function packs variables into a fuse_ctrl_core_axi_read_out_configuration_s + // structure. The function returns the handle to the fuse_ctrl_core_axi_read_out_configuration_struct. + // This function is defined in fuse_ctrl_core_axi_read_out_macros.svh + `fuse_ctrl_core_axi_read_out_CONFIGURATION_TO_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_struct() + // This function unpacks the struct provided as an argument into + // variables of this class. + // This function is defined in fuse_ctrl_core_axi_read_out_macros.svh + `fuse_ctrl_core_axi_read_out_CONFIGURATION_FROM_STRUCT_FUNCTION + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + // Construct the covergroup for this configuration class + fuse_ctrl_core_axi_read_out_configuration_cg = new; + endfunction + + // **************************************************************************** + // FUNCTION: post_randomize() + // This function is automatically called after the randomize() function + // is executed. + // + function void post_randomize(); + super.post_randomize(); + fuse_ctrl_core_axi_read_out_configuration_cg.sample(); + endfunction + + // **************************************************************************** + // FUNCTION: initialize + // This function causes the configuration to retrieve + // its virtual interface handle from the uvm_config_db. + // This function also makes itself available to its + // agent through the uvm_config_db. + // + // ARGUMENTS: + // uvmf_active_passive_t activity: + // This argument identifies the simulation level + // as either BLOCK, CHIP, SIMULATION, etc. + // + // AGENT_PATH: + // This argument identifies the path to this + // configurations agent. This configuration + // makes itself available to the agent specified + // by agent_path by placing itself into the + // uvm_config_db. + // + // INTERFACE_NAME: + // This argument identifies the string name of + // this configurations BFM's. This string + // name is used to retrieve the driver and + // monitor BFM from the uvm_config_db. + // + virtual function void initialize(uvmf_active_passive_t activity, + string agent_path, + string interface_name); + + super.initialize( activity, agent_path, interface_name); + // The covergroup is given the same name as the interface + fuse_ctrl_core_axi_read_out_configuration_cg.set_inst_name(interface_name); + + // This configuration places itself into the uvm_config_db for the agent, identified by the agent_path variable, to retrieve. + uvm_config_db #( fuse_ctrl_core_axi_read_out_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + + )::set( null ,agent_path,UVMF_AGENT_CONFIG, this ); + + // This configuration also places itself in the config db using the same identifier used by the interface. This allows users to access + // configuration variables and the interface through the bfm api class rather than directly accessing the BFM. This is useful for + // accessingthe BFM when using Veloce + uvm_config_db #( fuse_ctrl_core_axi_read_out_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + + )::set( null ,UVMF_CONFIGURATIONS, interface_name, this ); + + fuse_ctrl_core_axi_read_out_configuration_cg.set_inst_name($sformatf("fuse_ctrl_core_axi_read_out_configuration_cg_%s",get_full_name())); + +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. + `uvm_info("CFG", + $psprintf("The agent at '%s' is using interface named %s has the following parameters: AW=%x DW=%x IW=%x UW=%x ", agent_path, interface_name, AW ,DW ,IW ,UW ), + UVM_DEBUG) + + // pragma uvmf custom initialize begin + // This controls whether or not the agent returns a transaction handle in the driver when calling + // item_done() back into the sequencer or not. If set to 1, a transaction is sent back which means + // the sequence on the other end must use the get_response() part of the driver/sequence API. If + // this doesn't occur, there will eventually be response_queue overflow errors during the test. + return_transaction_response = 1'b0; + + // pragma uvmf custom initialize end + + endfunction + + // **************************************************************************** + // TASK: wait_for_reset + // *[Required]* Blocks until reset is released. The wait_for_reset operation is performed + // by a task in the monitor bfm. + virtual task wait_for_reset(); + monitor_bfm.wait_for_reset(); + endtask + + // **************************************************************************** + // TASK: wait_for_num_clocks + // *[Required]* Blocks until specified number of clocks have elapsed. The wait_for_num_clocks + // operation is performed by a task in the monitor bfm. + virtual task wait_for_num_clocks(int clocks); + monitor_bfm.wait_for_num_clocks(clocks); + endtask + + // **************************************************************************** + // FUNCTION : convert2string() + // This function is used to convert variables in this class into a string for log messaging. + // + virtual function string convert2string (); + // pragma uvmf custom convert2string begin + return $sformatf(""); + // pragma uvmf custom convert2string end + endfunction + + // **************************************************************************** + // FUNCTION: get_sequencer + function uvm_sequencer #(fuse_ctrl_core_axi_read_out_transaction#( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +) get_sequencer(); + return sequencer; + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_driver.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_driver.svh new file mode 100644 index 0000000..0471800 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_driver.svh @@ -0,0 +1,141 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class passes transactions between the sequencer +// and the BFM driver interface. It accesses the driver BFM +// through the bfm handle. This driver +// passes transactions to the driver BFM through the access +// task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_read_out_driver #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvmf_driver_base #( + .CONFIG_T(fuse_ctrl_core_axi_read_out_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + ), + .BFM_BIND_T(virtual fuse_ctrl_core_axi_read_out_driver_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + ), + .REQ(fuse_ctrl_core_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + ), + .RSP(fuse_ctrl_core_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + )); + + `uvm_component_param_utils( fuse_ctrl_core_axi_read_out_driver #( + AW, + DW, + IW, + UW + ) +) +//******************************************************************* +// Macros that define structs located in fuse_ctrl_core_axi_read_out_macros.svh +//******************************************************************* +// Initiator macro used by fuse_ctrl_core_axi_read_out_driver and fuse_ctrl_core_axi_read_out_driver_bfm +// to communicate initiator driven data to fuse_ctrl_core_axi_read_out_driver_bfm. +`fuse_ctrl_core_axi_read_out_INITIATOR_STRUCT + fuse_ctrl_core_axi_read_out_initiator_s fuse_ctrl_core_axi_read_out_initiator_struct; +//******************************************************************* +// Responder macro used by fuse_ctrl_core_axi_read_out_driver and fuse_ctrl_core_axi_read_out_driver_bfm +// to communicate Responder driven data to fuse_ctrl_core_axi_read_out_driver_bfm. +`fuse_ctrl_core_axi_read_out_RESPONDER_STRUCT + fuse_ctrl_core_axi_read_out_responder_s fuse_ctrl_core_axi_read_out_responder_struct; + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent=null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the driver BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// driver BFM. This allows the driver BFM to call tasks and function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// **************************************************************************** +// This task is called by the run_phase in uvmf_driver_base. + virtual task access( inout REQ txn ); +// pragma uvmf custom access begin + if (configuration.initiator_responder==RESPONDER) begin + // Complete current transfer and wait for next transfer + bfm.respond_and_wait_for_next_transfer( + fuse_ctrl_core_axi_read_out_initiator_struct, + txn.to_responder_struct() + ); + // Unpack information about initiated transfer received by this responder + txn.from_initiator_struct(fuse_ctrl_core_axi_read_out_initiator_struct); + end else begin + // Initiate a transfer and get response + bfm.initiate_and_get_response( + txn.to_initiator_struct(), + fuse_ctrl_core_axi_read_out_responder_struct + ); + // Unpack transfer response information received by this initiator + txn.from_responder_struct(fuse_ctrl_core_axi_read_out_responder_struct); + end +// pragma uvmf custom access end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_driver_bfm.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_driver_bfm.sv new file mode 100644 index 0000000..e7cfcff --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_driver_bfm.sv @@ -0,0 +1,352 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This interface performs the fuse_ctrl_core_axi_read_out signal driving. It is +// accessed by the uvm fuse_ctrl_core_axi_read_out driver through a virtual interface +// handle in the fuse_ctrl_core_axi_read_out configuration. It drives the singals passed +// in through the port connection named bus of type fuse_ctrl_core_axi_read_out_if. +// +// Input signals from the fuse_ctrl_core_axi_read_out_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// This bfm drives signals with a _o suffix. These signals +// are driven onto signals within fuse_ctrl_core_axi_read_out_if based on INITIATOR/RESPONDER and/or +// ARBITRATION/GRANT status. +// +// The output signal connections are as follows: +// signal_o -> bus.signal +// +// +// Interface functions and tasks used by UVM components: +// +// configure: +// This function gets configuration attributes from the +// UVM driver to set any required BFM configuration +// variables such as 'initiator_responder'. +// +// initiate_and_get_response: +// This task is used to perform signaling activity for initiating +// a protocol transfer. The task initiates the transfer, using +// input data from the initiator struct. Then the task captures +// response data, placing the data into the response struct. +// The response struct is returned to the driver class. +// +// respond_and_wait_for_next_transfer: +// This task is used to complete a current transfer as a responder +// and then wait for the initiator to start the next transfer. +// The task uses data in the responder struct to drive protocol +// signals to complete the transfer. The task then waits for +// the next transfer. Once the next transfer begins, data from +// the initiator is placed into the initiator struct and sent +// to the responder sequence for processing to determine +// what data to respond with. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_core_axi_read_out_pkg_hdl::*; +`include "src/fuse_ctrl_core_axi_read_out_macros.svh" + +interface fuse_ctrl_core_axi_read_out_driver_bfm #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + + (fuse_ctrl_core_axi_read_out_if bus); + // The following pragma and additional ones in-lined further below are for running this BFM on Veloce + // pragma attribute fuse_ctrl_core_axi_read_out_driver_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: AW=%x DW=%x IW=%x UW=%x ", AW,DW,IW,UW), + UVM_DEBUG) +end +`endif + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + tri clk_i_i; + tri rst_ni_i; + + // Signal list (all signals are capable of being inputs and outputs for the sake + // of supporting both INITIATOR and RESPONDER mode operation. Expectation is that + // directionality in the config file was from the point-of-view of the INITIATOR + + // INITIATOR mode input signals + tri arready_i; + reg arready_o = 'bz; + tri [DW-1:0] rdata_i; + reg [DW-1:0] rdata_o = 'bz; + tri rresp_i; + reg rresp_o = 'bz; + tri rid_i; + reg rid_o = 'bz; + tri rlast_i; + reg rlast_o = 'bz; + tri rvalid_i; + reg rvalid_o = 'bz; + + // INITIATOR mode output signals + + // Bi-directional signals + + + assign clk_i_i = bus.clk_i; + assign rst_ni_i = bus.rst_ni; + + // These are signals marked as 'input' by the config file, but the signals will be + // driven by this BFM if put into RESPONDER mode (flipping all signal directions around) + assign arready_i = bus.arready; + assign bus.arready = (initiator_responder == RESPONDER) ? arready_o : 'bz; + assign rdata_i = bus.rdata; + assign bus.rdata = (initiator_responder == RESPONDER) ? rdata_o : 'bz; + assign rresp_i = bus.rresp; + assign bus.rresp = (initiator_responder == RESPONDER) ? rresp_o : 'bz; + assign rid_i = bus.rid; + assign bus.rid = (initiator_responder == RESPONDER) ? rid_o : 'bz; + assign rlast_i = bus.rlast; + assign bus.rlast = (initiator_responder == RESPONDER) ? rlast_o : 'bz; + assign rvalid_i = bus.rvalid; + assign bus.rvalid = (initiator_responder == RESPONDER) ? rvalid_o : 'bz; + + + // These are signals marked as 'output' by the config file, but the outputs will + // not be driven by this BFM unless placed in INITIATOR mode. + + // Proxy handle to UVM driver + fuse_ctrl_core_axi_read_out_pkg::fuse_ctrl_core_axi_read_out_driver #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + proxy; + // pragma tbx oneway proxy.my_function_name_in_uvm_driver + + // **************************************************************************** + // **************************************************************************** + // Macros that define structs located in fuse_ctrl_core_axi_read_out_macros.svh + // **************************************************************************** + // Struct for passing configuration data from fuse_ctrl_core_axi_read_out_driver to this BFM + // **************************************************************************** + `fuse_ctrl_core_axi_read_out_CONFIGURATION_STRUCT + // **************************************************************************** + // Structs for INITIATOR and RESPONDER data flow + //******************************************************************* + // Initiator macro used by fuse_ctrl_core_axi_read_out_driver and fuse_ctrl_core_axi_read_out_driver_bfm + // to communicate initiator driven data to fuse_ctrl_core_axi_read_out_driver_bfm. + `fuse_ctrl_core_axi_read_out_INITIATOR_STRUCT + fuse_ctrl_core_axi_read_out_initiator_s initiator_struct; + // Responder macro used by fuse_ctrl_core_axi_read_out_driver and fuse_ctrl_core_axi_read_out_driver_bfm + // to communicate Responder driven data to fuse_ctrl_core_axi_read_out_driver_bfm. + `fuse_ctrl_core_axi_read_out_RESPONDER_STRUCT + fuse_ctrl_core_axi_read_out_responder_s responder_struct; + + // **************************************************************************** +// pragma uvmf custom reset_condition_and_response begin + // Always block used to return signals to reset value upon assertion of reset + always @( negedge rst_ni_i ) + begin + // RESPONDER mode output signals + arready_o <= 'bz; + rdata_o <= 'bz; + rresp_o <= 'bz; + rid_o <= 'bz; + rlast_o <= 'bz; + rvalid_o <= 'bz; + // INITIATOR mode output signals + // Bi-directional signals + + end +// pragma uvmf custom reset_condition_and_response end + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the driver BFM. It is called by the driver within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the driver BFM needs to be aware of the new configuration + // variables. + // + + function void configure(fuse_ctrl_core_axi_read_out_configuration_s fuse_ctrl_core_axi_read_out_configuration_arg); // pragma tbx xtf + initiator_responder = fuse_ctrl_core_axi_read_out_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + +// pragma uvmf custom initiate_and_get_response begin +// **************************************************************************** +// UVMF_CHANGE_ME +// This task is used by an initator. The task first initiates a transfer then +// waits for the responder to complete the transfer. + task initiate_and_get_response( + // This argument passes transaction variables used by an initiator + // to perform the initial part of a protocol transfer. The values + // come from a sequence item created in a sequence. + input fuse_ctrl_core_axi_read_out_initiator_s fuse_ctrl_core_axi_read_out_initiator_struct, + // This argument is used to send data received from the responder + // back to the sequence item. The sequence item is returned to the sequence. + output fuse_ctrl_core_axi_read_out_responder_s fuse_ctrl_core_axi_read_out_responder_struct + );// pragma tbx xtf + // + // Members within the fuse_ctrl_core_axi_read_out_initiator_struct: + // logic core_arready ; + // logic [DW-1:0] core_rdata ; + // axi_pkg::axi_burst_e core_rresp ; + // logic [IW-1:0] core_rid ; + // logic core_rlast ; + // logic core_rvalid ; + // Members within the fuse_ctrl_core_axi_read_out_responder_struct: + // logic core_arready ; + // logic [DW-1:0] core_rdata ; + // axi_pkg::axi_burst_e core_rresp ; + // logic [IW-1:0] core_rid ; + // logic core_rlast ; + // logic core_rvalid ; + initiator_struct = fuse_ctrl_core_axi_read_out_initiator_struct; + // + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clk_i_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available initiator input and inout signals listed. + // Initiator input signals + // fuse_ctrl_core_axi_read_out_responder_struct.xyz = arready_i; // + // fuse_ctrl_core_axi_read_out_responder_struct.xyz = rdata_i; // [DW-1:0] + // fuse_ctrl_core_axi_read_out_responder_struct.xyz = rresp_i; // + // fuse_ctrl_core_axi_read_out_responder_struct.xyz = rid_i; // + // fuse_ctrl_core_axi_read_out_responder_struct.xyz = rlast_i; // + // fuse_ctrl_core_axi_read_out_responder_struct.xyz = rvalid_i; // + // Initiator inout signals + // How to assign a signal from an initiator struct member named xyz. + // All available initiator output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Initiator output signals + // Initiator inout signals + // Initiate a transfer using the data received. + @(posedge clk_i_i); + @(posedge clk_i_i); + // Wait for the responder to complete the transfer then place the responder data into + // fuse_ctrl_core_axi_read_out_responder_struct. + @(posedge clk_i_i); + @(posedge clk_i_i); + responder_struct = fuse_ctrl_core_axi_read_out_responder_struct; + endtask +// pragma uvmf custom initiate_and_get_response end + +// pragma uvmf custom respond_and_wait_for_next_transfer begin +// **************************************************************************** +// The first_transfer variable is used to prevent completing a transfer in the +// first call to this task. For the first call to this task, there is not +// current transfer to complete. +bit first_transfer=1; + +// UVMF_CHANGE_ME +// This task is used by a responder. The task first completes the current +// transfer in progress then waits for the initiator to start the next transfer. + task respond_and_wait_for_next_transfer( + // This argument is used to send data received from the initiator + // back to the sequence item. The sequence determines how to respond. + output fuse_ctrl_core_axi_read_out_initiator_s fuse_ctrl_core_axi_read_out_initiator_struct, + // This argument passes transaction variables used by a responder + // to complete a protocol transfer. The values come from a sequence item. + input fuse_ctrl_core_axi_read_out_responder_s fuse_ctrl_core_axi_read_out_responder_struct + );// pragma tbx xtf + // Variables within the fuse_ctrl_core_axi_read_out_initiator_struct: + // logic core_arready ; + // logic [DW-1:0] core_rdata ; + // axi_pkg::axi_burst_e core_rresp ; + // logic [IW-1:0] core_rid ; + // logic core_rlast ; + // logic core_rvalid ; + // Variables within the fuse_ctrl_core_axi_read_out_responder_struct: + // logic core_arready ; + // logic [DW-1:0] core_rdata ; + // axi_pkg::axi_burst_e core_rresp ; + // logic [IW-1:0] core_rid ; + // logic core_rlast ; + // logic core_rvalid ; + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clk_i_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available responder input and inout signals listed. + // Responder input signals + // Responder inout signals + // How to assign a signal, named xyz, from an initiator struct member. + // All available responder output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Responder output signals + // arready_o <= fuse_ctrl_core_axi_read_out_initiator_struct.xyz; // + // rdata_o <= fuse_ctrl_core_axi_read_out_initiator_struct.xyz; // [DW-1:0] + // rresp_o <= fuse_ctrl_core_axi_read_out_initiator_struct.xyz; // + // rid_o <= fuse_ctrl_core_axi_read_out_initiator_struct.xyz; // + // rlast_o <= fuse_ctrl_core_axi_read_out_initiator_struct.xyz; // + // rvalid_o <= fuse_ctrl_core_axi_read_out_initiator_struct.xyz; // + // Responder inout signals + + @(posedge clk_i_i); + if (!first_transfer) begin + // Perform transfer response here. + // Reply using data recieved in the fuse_ctrl_core_axi_read_out_responder_struct. + @(posedge clk_i_i); + // Reply using data recieved in the transaction handle. + @(posedge clk_i_i); + end + // Wait for next transfer then gather info from intiator about the transfer. + // Place the data into the fuse_ctrl_core_axi_read_out_initiator_struct. + @(posedge clk_i_i); + @(posedge clk_i_i); + first_transfer = 0; + endtask +// pragma uvmf custom respond_and_wait_for_next_transfer end + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_if.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_if.sv new file mode 100644 index 0000000..f32c01a --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_if.sv @@ -0,0 +1,109 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface contains the fuse_ctrl_core_axi_read_out interface signals. +// It is instantiated once per fuse_ctrl_core_axi_read_out bus. Bus Functional Models, +// BFM's named fuse_ctrl_core_axi_read_out_driver_bfm, are used to drive signals on the bus. +// BFM's named fuse_ctrl_core_axi_read_out_monitor_bfm are used to monitor signals on the +// bus. This interface signal bundle is passed in the port list of +// the BFM in order to give the BFM access to the signals in this +// interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// This template can be used to connect a DUT to these signals +// +// .dut_signal_port(fuse_ctrl_core_axi_read_out_bus.arready), // Agent input +// .dut_signal_port(fuse_ctrl_core_axi_read_out_bus.rdata), // Agent input +// .dut_signal_port(fuse_ctrl_core_axi_read_out_bus.rresp), // Agent input +// .dut_signal_port(fuse_ctrl_core_axi_read_out_bus.rid), // Agent input +// .dut_signal_port(fuse_ctrl_core_axi_read_out_bus.rlast), // Agent input +// .dut_signal_port(fuse_ctrl_core_axi_read_out_bus.rvalid), // Agent input + +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_core_axi_read_out_pkg_hdl::*; + +interface fuse_ctrl_core_axi_read_out_if #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + + + ( + input tri clk_i, + input tri rst_ni, + inout tri arready, + inout tri [DW-1:0] rdata, + inout tri rresp, + inout tri rid, + inout tri rlast, + inout tri rvalid + ); + +modport monitor_port + ( + input clk_i, + input rst_ni, + input arready, + input rdata, + input rresp, + input rid, + input rlast, + input rvalid + ); + +modport initiator_port + ( + input clk_i, + input rst_ni, + input arready, + input rdata, + input rresp, + input rid, + input rlast, + input rvalid + ); + +modport responder_port + ( + input clk_i, + input rst_ni, + output arready, + output rdata, + output rresp, + output rid, + output rlast, + output rvalid + ); + + +// pragma uvmf custom interface_item_additional begin +// pragma uvmf custom interface_item_additional end + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_infact_coverage_strategy.csv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_infact_coverage_strategy.csv new file mode 100644 index 0000000..1c218e1 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_infact_coverage_strategy.csv @@ -0,0 +1,6 @@ +Global +auto_bin_max, 64 + +Name,Type,Include +rand_fields,coverpoint,=rand *.** + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_macros.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_macros.svh new file mode 100644 index 0000000..2742dc0 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_macros.svh @@ -0,0 +1,180 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains macros used with the fuse_ctrl_core_axi_read_out package. +// These macros include packed struct definitions. These structs are +// used to pass data between classes, hvl, and BFM's, hdl. Use of +// structs are more efficient and simpler to modify. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_struct +// and from_struct methods defined in the macros below that are used in +// the fuse_ctrl_core_axi_read_out_configuration class. +// + `define fuse_ctrl_core_axi_read_out_CONFIGURATION_STRUCT \ +typedef struct packed { \ + uvmf_active_passive_t active_passive; \ + uvmf_initiator_responder_t initiator_responder; \ + } fuse_ctrl_core_axi_read_out_configuration_s; + + `define fuse_ctrl_core_axi_read_out_CONFIGURATION_TO_STRUCT_FUNCTION \ + virtual function fuse_ctrl_core_axi_read_out_configuration_s to_struct();\ + fuse_ctrl_core_axi_read_out_configuration_struct = \ + {\ + this.active_passive,\ + this.initiator_responder\ + };\ + return ( fuse_ctrl_core_axi_read_out_configuration_struct );\ + endfunction + + `define fuse_ctrl_core_axi_read_out_CONFIGURATION_FROM_STRUCT_FUNCTION \ + virtual function void from_struct(fuse_ctrl_core_axi_read_out_configuration_s fuse_ctrl_core_axi_read_out_configuration_struct);\ + {\ + this.active_passive,\ + this.initiator_responder \ + } = fuse_ctrl_core_axi_read_out_configuration_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_monitor_struct +// and from_monitor_struct methods of the fuse_ctrl_core_axi_read_out_transaction class. +// + `define fuse_ctrl_core_axi_read_out_MONITOR_STRUCT typedef struct packed { \ + logic core_arready ; \ + logic [DW-1:0] core_rdata ; \ + axi_pkg::axi_burst_e core_rresp ; \ + logic [IW-1:0] core_rid ; \ + logic core_rlast ; \ + logic core_rvalid ; \ + } fuse_ctrl_core_axi_read_out_monitor_s; + + `define fuse_ctrl_core_axi_read_out_TO_MONITOR_STRUCT_FUNCTION \ + virtual function fuse_ctrl_core_axi_read_out_monitor_s to_monitor_struct();\ + fuse_ctrl_core_axi_read_out_monitor_struct = \ + { \ + this.core_arready , \ + this.core_rdata , \ + this.core_rresp , \ + this.core_rid , \ + this.core_rlast , \ + this.core_rvalid \ + };\ + return ( fuse_ctrl_core_axi_read_out_monitor_struct);\ + endfunction\ + + `define fuse_ctrl_core_axi_read_out_FROM_MONITOR_STRUCT_FUNCTION \ + virtual function void from_monitor_struct(fuse_ctrl_core_axi_read_out_monitor_s fuse_ctrl_core_axi_read_out_monitor_struct);\ + {\ + this.core_arready , \ + this.core_rdata , \ + this.core_rresp , \ + this.core_rid , \ + this.core_rlast , \ + this.core_rvalid \ + } = fuse_ctrl_core_axi_read_out_monitor_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_initiator_struct +// and from_initiator_struct methods of the fuse_ctrl_core_axi_read_out_transaction class. +// Also update the comments in the driver BFM. +// + `define fuse_ctrl_core_axi_read_out_INITIATOR_STRUCT typedef struct packed { \ + logic core_arready ; \ + logic [DW-1:0] core_rdata ; \ + axi_pkg::axi_burst_e core_rresp ; \ + logic [IW-1:0] core_rid ; \ + logic core_rlast ; \ + logic core_rvalid ; \ + } fuse_ctrl_core_axi_read_out_initiator_s; + + `define fuse_ctrl_core_axi_read_out_TO_INITIATOR_STRUCT_FUNCTION \ + virtual function fuse_ctrl_core_axi_read_out_initiator_s to_initiator_struct();\ + fuse_ctrl_core_axi_read_out_initiator_struct = \ + {\ + this.core_arready , \ + this.core_rdata , \ + this.core_rresp , \ + this.core_rid , \ + this.core_rlast , \ + this.core_rvalid \ + };\ + return ( fuse_ctrl_core_axi_read_out_initiator_struct);\ + endfunction + + `define fuse_ctrl_core_axi_read_out_FROM_INITIATOR_STRUCT_FUNCTION \ + virtual function void from_initiator_struct(fuse_ctrl_core_axi_read_out_initiator_s fuse_ctrl_core_axi_read_out_initiator_struct);\ + {\ + this.core_arready , \ + this.core_rdata , \ + this.core_rresp , \ + this.core_rid , \ + this.core_rlast , \ + this.core_rvalid \ + } = fuse_ctrl_core_axi_read_out_initiator_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_responder_struct +// and from_responder_struct methods of the fuse_ctrl_core_axi_read_out_transaction class. +// Also update the comments in the driver BFM. +// + `define fuse_ctrl_core_axi_read_out_RESPONDER_STRUCT typedef struct packed { \ + logic core_arready ; \ + logic [DW-1:0] core_rdata ; \ + axi_pkg::axi_burst_e core_rresp ; \ + logic [IW-1:0] core_rid ; \ + logic core_rlast ; \ + logic core_rvalid ; \ + } fuse_ctrl_core_axi_read_out_responder_s; + + `define fuse_ctrl_core_axi_read_out_TO_RESPONDER_STRUCT_FUNCTION \ + virtual function fuse_ctrl_core_axi_read_out_responder_s to_responder_struct();\ + fuse_ctrl_core_axi_read_out_responder_struct = \ + {\ + this.core_arready , \ + this.core_rdata , \ + this.core_rresp , \ + this.core_rid , \ + this.core_rlast , \ + this.core_rvalid \ + };\ + return ( fuse_ctrl_core_axi_read_out_responder_struct);\ + endfunction + + `define fuse_ctrl_core_axi_read_out_FROM_RESPONDER_STRUCT_FUNCTION \ + virtual function void from_responder_struct(fuse_ctrl_core_axi_read_out_responder_s fuse_ctrl_core_axi_read_out_responder_struct);\ + {\ + this.core_arready , \ + this.core_rdata , \ + this.core_rresp , \ + this.core_rid , \ + this.core_rlast , \ + this.core_rvalid \ + } = fuse_ctrl_core_axi_read_out_responder_struct;\ + endfunction +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_monitor.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_monitor.svh new file mode 100644 index 0000000..192a182 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_monitor.svh @@ -0,0 +1,131 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class receives fuse_ctrl_core_axi_read_out transactions observed by the +// fuse_ctrl_core_axi_read_out monitor BFM and broadcasts them through the analysis port +// on the agent. It accesses the monitor BFM through the monitor +// task. This UVM component captures transactions +// for viewing in the waveform viewer if the +// enable_transaction_viewing flag is set in the configuration. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_read_out_monitor #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvmf_monitor_base #( + .CONFIG_T(fuse_ctrl_core_axi_read_out_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .BFM_BIND_T(virtual fuse_ctrl_core_axi_read_out_monitor_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .TRANS_T(fuse_ctrl_core_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +)); + + `uvm_component_param_utils( fuse_ctrl_core_axi_read_out_monitor #( + AW, + DW, + IW, + UW + ) +) + +// Structure used to pass data from monitor BFM to monitor class in agent. +// Use to_monitor_struct function to pack transaction variables into structure. +// Use from_monitor_struct function to unpack transaction variables from structure. +`fuse_ctrl_core_axi_read_out_MONITOR_STRUCT + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the monitor BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// monitor BFM. This allows the monitor BFM to call the notify_transaction +// function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// *************************************************************************** + virtual task run_phase(uvm_phase phase); + // Start monitor BFM thread and don't call super.run() in order to + // override the default monitor proxy 'pull' behavior with the more + // emulation-friendly BFM 'push' approach using the notify_transaction + // function below + bfm.start_monitoring(); + endtask + +// ************************************************************************** + +// This function is called by the monitor BFM. It receives data observed by the +// monitor BFM. Data is passed using the fuse_ctrl_core_axi_read_out_monitor_struct. + virtual function void notify_transaction(input fuse_ctrl_core_axi_read_out_monitor_s fuse_ctrl_core_axi_read_out_monitor_struct); + + + trans = new("trans"); + trans.from_monitor_struct(fuse_ctrl_core_axi_read_out_monitor_struct); + trans.start_time = time_stamp; + trans.end_time = $time; + time_stamp = trans.end_time; + + analyze(trans); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_monitor_bfm.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_monitor_bfm.sv new file mode 100644 index 0000000..05a619e --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_monitor_bfm.sv @@ -0,0 +1,220 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface performs the fuse_ctrl_core_axi_read_out signal monitoring. +// It is accessed by the uvm fuse_ctrl_core_axi_read_out monitor through a virtual +// interface handle in the fuse_ctrl_core_axi_read_out configuration. It monitors the +// signals passed in through the port connection named bus of +// type fuse_ctrl_core_axi_read_out_if. +// +// Input signals from the fuse_ctrl_core_axi_read_out_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// Interface functions and tasks used by UVM components: +// monitor(inout TRANS_T txn); +// This task receives the transaction, txn, from the +// UVM monitor and then populates variables in txn +// from values observed on bus activity. This task +// blocks until an operation on the fuse_ctrl_core_axi_read_out bus is complete. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_core_axi_read_out_pkg_hdl::*; +`include "src/fuse_ctrl_core_axi_read_out_macros.svh" + + +interface fuse_ctrl_core_axi_read_out_monitor_bfm #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + + ( fuse_ctrl_core_axi_read_out_if bus ); + // The pragma below and additional ones in-lined further down are for running this BFM on Veloce + // pragma attribute fuse_ctrl_core_axi_read_out_monitor_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: AW=%x DW=%x IW=%x UW=%x ", AW,DW,IW,UW), + UVM_DEBUG) +end +`endif + + + // Structure used to pass transaction data from monitor BFM to monitor class in agent. +`fuse_ctrl_core_axi_read_out_MONITOR_STRUCT + fuse_ctrl_core_axi_read_out_monitor_s fuse_ctrl_core_axi_read_out_monitor_struct; + + // Structure used to pass configuration data from monitor class to monitor BFM. + `fuse_ctrl_core_axi_read_out_CONFIGURATION_STRUCT + + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + tri clk_i_i; + tri rst_ni_i; + tri arready_i; + tri [DW-1:0] rdata_i; + tri rresp_i; + tri rid_i; + tri rlast_i; + tri rvalid_i; + assign clk_i_i = bus.clk_i; + assign rst_ni_i = bus.rst_ni; + assign arready_i = bus.arready; + assign rdata_i = bus.rdata; + assign rresp_i = bus.rresp; + assign rid_i = bus.rid; + assign rlast_i = bus.rlast; + assign rvalid_i = bus.rvalid; + + // Proxy handle to UVM monitor + fuse_ctrl_core_axi_read_out_pkg::fuse_ctrl_core_axi_read_out_monitor #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + proxy; + // pragma tbx oneway proxy.notify_transaction + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + task wait_for_reset();// pragma tbx xtf + @(posedge clk_i_i) ; + do_wait_for_reset(); + endtask + + // **************************************************************************** + task do_wait_for_reset(); + // pragma uvmf custom reset_condition begin + wait ( rst_ni_i === 1 ) ; + @(posedge clk_i_i) ; + // pragma uvmf custom reset_condition end + endtask + + //****************************************************************** + + task wait_for_num_clocks(input int unsigned count); // pragma tbx xtf + @(posedge clk_i_i); + + repeat (count-1) @(posedge clk_i_i); + endtask + + //****************************************************************** + event go; + function void start_monitoring();// pragma tbx xtf + -> go; + endfunction + + // **************************************************************************** + initial begin + @go; + forever begin + @(posedge clk_i_i); + do_monitor( fuse_ctrl_core_axi_read_out_monitor_struct ); + + + proxy.notify_transaction( fuse_ctrl_core_axi_read_out_monitor_struct ); + + end + end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the monitor BFM. It is called by the monitor within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the monitor BFM needs to be aware of the new configuration + // variables. + // + function void configure(fuse_ctrl_core_axi_read_out_configuration_s fuse_ctrl_core_axi_read_out_configuration_arg); // pragma tbx xtf + initiator_responder = fuse_ctrl_core_axi_read_out_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + + + // **************************************************************************** + + task do_monitor(output fuse_ctrl_core_axi_read_out_monitor_s fuse_ctrl_core_axi_read_out_monitor_struct); + // + // Available struct members: + // // fuse_ctrl_core_axi_read_out_monitor_struct.core_arready + // // fuse_ctrl_core_axi_read_out_monitor_struct.core_rdata + // // fuse_ctrl_core_axi_read_out_monitor_struct.core_rresp + // // fuse_ctrl_core_axi_read_out_monitor_struct.core_rid + // // fuse_ctrl_core_axi_read_out_monitor_struct.core_rlast + // // fuse_ctrl_core_axi_read_out_monitor_struct.core_rvalid + // // + // Reference code; + // How to wait for signal value + // while (control_signal === 1'b1) @(posedge clk_i_i); + // + // How to assign a struct member, named xyz, from a signal. + // All available input signals listed. + // fuse_ctrl_core_axi_read_out_monitor_struct.xyz = arready_i; // + // fuse_ctrl_core_axi_read_out_monitor_struct.xyz = rdata_i; // [DW-1:0] + // fuse_ctrl_core_axi_read_out_monitor_struct.xyz = rresp_i; // + // fuse_ctrl_core_axi_read_out_monitor_struct.xyz = rid_i; // + // fuse_ctrl_core_axi_read_out_monitor_struct.xyz = rlast_i; // + // fuse_ctrl_core_axi_read_out_monitor_struct.xyz = rvalid_i; // + // pragma uvmf custom do_monitor begin + // UVMF_CHANGE_ME : Implement protocol monitoring. The commented reference code + // below are examples of how to capture signal values and assign them to + // structure members. All available input signals are listed. The 'while' + // code example shows how to wait for a synchronous flow control signal. This + // task should return when a complete transfer has been observed. Once this task is + // exited with captured values, it is then called again to wait for and observe + // the next transfer. One clock cycle is consumed between calls to do_monitor. + @(posedge clk_i_i); + @(posedge clk_i_i); + @(posedge clk_i_i); + @(posedge clk_i_i); + // pragma uvmf custom do_monitor end + endtask + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_random_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_random_sequence.svh new file mode 100644 index 0000000..7564421 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_random_sequence.svh @@ -0,0 +1,91 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This sequences randomizes the fuse_ctrl_core_axi_read_out transaction and sends it +// to the UVM driver. +// +// This sequence constructs and randomizes a fuse_ctrl_core_axi_read_out_transaction. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_read_out_random_sequence #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + + extends fuse_ctrl_core_axi_read_out_sequence_base #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +; + + `uvm_object_param_utils( fuse_ctrl_core_axi_read_out_random_sequence #( + AW, + DW, + IW, + UW + ) +) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //***************************************************************** + function new(string name = ""); + super.new(name); + endfunction: new + + // **************************************************************************** + // TASK : body() + // This task is automatically executed when this sequence is started using the + // start(sequencerHandle) task. + // + task body(); + + // Construct the transaction + req=fuse_ctrl_core_axi_read_out_transaction#( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +::type_id::create("req"); + start_item(req); + // Randomize the transaction + if(!req.randomize()) `uvm_fatal("SEQ", "fuse_ctrl_core_axi_read_out_random_sequence::body()-fuse_ctrl_core_axi_read_out_transaction randomization failed") + // Send the transaction to the fuse_ctrl_core_axi_read_out_driver_bfm via the sequencer and fuse_ctrl_core_axi_read_out_driver. + finish_item(req); + `uvm_info("SEQ", {"Response:",req.convert2string()},UVM_MEDIUM) + + endtask + +endclass: fuse_ctrl_core_axi_read_out_random_sequence + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_responder_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_responder_sequence.svh new file mode 100644 index 0000000..7201178 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_responder_sequence.svh @@ -0,0 +1,87 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class can be used to provide stimulus when an interface +// has been configured to run in a responder mode. It +// will never finish by default, always going back to the driver +// and driver BFM for the next transaction with which to respond. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_read_out_responder_sequence #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + + extends fuse_ctrl_core_axi_read_out_sequence_base #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +; + + `uvm_object_param_utils( fuse_ctrl_core_axi_read_out_responder_sequence #( + AW, + DW, + IW, + UW + ) +) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "fuse_ctrl_core_axi_read_out_responder_sequence"); + super.new(name); + endfunction + + task body(); + req=fuse_ctrl_core_axi_read_out_transaction#( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +::type_id::create("req"); + forever begin + start_item(req); + finish_item(req); + // pragma uvmf custom body begin + // UVMF_CHANGE_ME : Do something here with the resulting req item. The + // finish_item() call above will block until the req transaction is ready + // to be handled by the responder sequence. + // If this was an item that required a response, the expectation is + // that the response should be populated within this transaction now. + `uvm_info("SEQ",$sformatf("Processed txn: %s",req.convert2string()),UVM_HIGH) + // pragma uvmf custom body end + end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_sequence_base.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_sequence_base.svh new file mode 100644 index 0000000..552bdba --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_sequence_base.svh @@ -0,0 +1,146 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the class used as the base class for all sequences +// for this interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_read_out_sequence_base #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvmf_sequence_base #( + .REQ(fuse_ctrl_core_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .RSP(fuse_ctrl_core_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +)); + + `uvm_object_param_utils( fuse_ctrl_core_axi_read_out_sequence_base #( + AW, + DW, + IW, + UW + ) +) + + // variables + typedef fuse_ctrl_core_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + fuse_ctrl_core_axi_read_out_transaction_req_t; + fuse_ctrl_core_axi_read_out_transaction_req_t req; + typedef fuse_ctrl_core_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + fuse_ctrl_core_axi_read_out_transaction_rsp_t; + fuse_ctrl_core_axi_read_out_transaction_rsp_t rsp; + + // Event for identifying when a response was received from the sequencer + event new_rsp; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // TASK : get_responses() + // This task recursively gets sequence item responses from the sequencer. + // + virtual task get_responses(); + fork + begin + // Block until new rsp available + get_response(rsp); + // New rsp received. Indicate to sequence using event. + ->new_rsp; + // Display the received response transaction + `uvm_info("SEQ", {"New response transaction:",rsp.convert2string()}, UVM_MEDIUM) + end + join_none + endtask + + // **************************************************************************** + // TASK : pre_body() + // This task is called automatically when start is called with call_pre_post set to 1 (default). + // By calling get_responses() within pre_body() any derived sequences are automatically + // processing response transactions. Only un-comment this call to get_responses() if you + // have configured the interface driver to utilize the response transaction path by setting + // the configuration variable "return_transaction_response" to 1. Otherwise it is possible + // to impact runtime performance and memory utilization. + // + virtual task pre_body(); + // pragma uvmf custom pre_body begin +// get_responses(); + // pragma uvmf custom pre_body end + endtask + + // **************************************************************************** + // TASK : body() + // This task is called automatically when start is called. This sequence sends + // a req sequence item to the sequencer identified as an argument in the call + // to start. + // + virtual task body(); + // pragma uvmf custom body begin + start_item(req); + finish_item(req); + // pragma uvmf custom body end + endtask + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name =""); + super.new( name ); + // pragma uvmf custom new begin + req = fuse_ctrl_core_axi_read_out_transaction_req_t::type_id::create("req"); + rsp = fuse_ctrl_core_axi_read_out_transaction_rsp_t::type_id::create("rsp"); + // pragma uvmf custom new end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_transaction.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_transaction.svh new file mode 100644 index 0000000..4654272 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_transaction.svh @@ -0,0 +1,240 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class defines the variables required for an fuse_ctrl_core_axi_read_out +// transaction. Class variables to be displayed in waveform transaction +// viewing are added to the transaction viewing stream in the add_to_wave +// function. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_read_out_transaction #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvmf_transaction_base; + + `uvm_object_param_utils( fuse_ctrl_core_axi_read_out_transaction #( + AW, + DW, + IW, + UW + ) +) + + logic core_arready ; + logic [DW-1:0] core_rdata ; + axi_pkg::axi_burst_e core_rresp ; + logic [IW-1:0] core_rid ; + logic core_rlast ; + logic core_rvalid ; + + //Constraints for the transaction variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //******************************************************************* + //******************************************************************* + // Macros that define structs and associated functions are + // located in fuse_ctrl_core_axi_read_out_macros.svh + + //******************************************************************* + // Monitor macro used by fuse_ctrl_core_axi_read_out_monitor and fuse_ctrl_core_axi_read_out_monitor_bfm + // This struct is defined in fuse_ctrl_core_axi_read_out_macros.svh + `fuse_ctrl_core_axi_read_out_MONITOR_STRUCT + fuse_ctrl_core_axi_read_out_monitor_s fuse_ctrl_core_axi_read_out_monitor_struct; + //******************************************************************* + // FUNCTION: to_monitor_struct() + // This function packs transaction variables into a fuse_ctrl_core_axi_read_out_monitor_s + // structure. The function returns the handle to the fuse_ctrl_core_axi_read_out_monitor_struct. + // This function is defined in fuse_ctrl_core_axi_read_out_macros.svh + `fuse_ctrl_core_axi_read_out_TO_MONITOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_monitor_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_core_axi_read_out_macros.svh + `fuse_ctrl_core_axi_read_out_FROM_MONITOR_STRUCT_FUNCTION + + //******************************************************************* + // Initiator macro used by fuse_ctrl_core_axi_read_out_driver and fuse_ctrl_core_axi_read_out_driver_bfm + // to communicate initiator driven data to fuse_ctrl_core_axi_read_out_driver_bfm. + // This struct is defined in fuse_ctrl_core_axi_read_out_macros.svh + `fuse_ctrl_core_axi_read_out_INITIATOR_STRUCT + fuse_ctrl_core_axi_read_out_initiator_s fuse_ctrl_core_axi_read_out_initiator_struct; + //******************************************************************* + // FUNCTION: to_initiator_struct() + // This function packs transaction variables into a fuse_ctrl_core_axi_read_out_initiator_s + // structure. The function returns the handle to the fuse_ctrl_core_axi_read_out_initiator_struct. + // This function is defined in fuse_ctrl_core_axi_read_out_macros.svh + `fuse_ctrl_core_axi_read_out_TO_INITIATOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_initiator_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_core_axi_read_out_macros.svh + `fuse_ctrl_core_axi_read_out_FROM_INITIATOR_STRUCT_FUNCTION + + //******************************************************************* + // Responder macro used by fuse_ctrl_core_axi_read_out_driver and fuse_ctrl_core_axi_read_out_driver_bfm + // to communicate Responder driven data to fuse_ctrl_core_axi_read_out_driver_bfm. + // This struct is defined in fuse_ctrl_core_axi_read_out_macros.svh + `fuse_ctrl_core_axi_read_out_RESPONDER_STRUCT + fuse_ctrl_core_axi_read_out_responder_s fuse_ctrl_core_axi_read_out_responder_struct; + //******************************************************************* + // FUNCTION: to_responder_struct() + // This function packs transaction variables into a fuse_ctrl_core_axi_read_out_responder_s + // structure. The function returns the handle to the fuse_ctrl_core_axi_read_out_responder_struct. + // This function is defined in fuse_ctrl_core_axi_read_out_macros.svh + `fuse_ctrl_core_axi_read_out_TO_RESPONDER_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_responder_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_core_axi_read_out_macros.svh + `fuse_ctrl_core_axi_read_out_FROM_RESPONDER_STRUCT_FUNCTION + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + endfunction + + // **************************************************************************** + // FUNCTION: convert2string() + // This function converts all variables in this class to a single string for + // logfile reporting. + // + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + // UVMF_CHANGE_ME : Customize format if desired. + return $sformatf("core_arready:0x%x core_rdata:0x%x core_rresp:0x%x core_rid:0x%x core_rlast:0x%x core_rvalid:0x%x ",core_arready,core_rdata,core_rresp,core_rid,core_rlast,core_rvalid); + // pragma uvmf custom convert2string end + endfunction + + //******************************************************************* + // FUNCTION: do_print() + // This function is automatically called when the .print() function + // is called on this class. + // + virtual function void do_print(uvm_printer printer); + // pragma uvmf custom do_print begin + // UVMF_CHANGE_ME : Current contents of do_print allows for the use of UVM 1.1d, 1.2 or P1800.2. + // Update based on your own printing preference according to your preferred UVM version + $display(convert2string()); + // pragma uvmf custom do_print end + endfunction + + //******************************************************************* + // FUNCTION: do_compare() + // This function is automatically called when the .compare() function + // is called on this class. + // + virtual function bit do_compare (uvm_object rhs, uvm_comparer comparer); + fuse_ctrl_core_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + RHS; + if (!$cast(RHS,rhs)) return 0; + // pragma uvmf custom do_compare begin + // UVMF_CHANGE_ME : Eliminate comparison of variables not to be used for compare + return (super.do_compare(rhs,comparer) + &&(this.core_arready == RHS.core_arready) + &&(this.core_rdata == RHS.core_rdata) + &&(this.core_rresp == RHS.core_rresp) + &&(this.core_rid == RHS.core_rid) + &&(this.core_rlast == RHS.core_rlast) + &&(this.core_rvalid == RHS.core_rvalid) + ); + // pragma uvmf custom do_compare end + endfunction + + //******************************************************************* + // FUNCTION: do_copy() + // This function is automatically called when the .copy() function + // is called on this class. + // + virtual function void do_copy (uvm_object rhs); + fuse_ctrl_core_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + RHS; + assert($cast(RHS,rhs)); + // pragma uvmf custom do_copy begin + super.do_copy(rhs); + this.core_arready = RHS.core_arready; + this.core_rdata = RHS.core_rdata; + this.core_rresp = RHS.core_rresp; + this.core_rid = RHS.core_rid; + this.core_rlast = RHS.core_rlast; + this.core_rvalid = RHS.core_rvalid; + // pragma uvmf custom do_copy end + endfunction + + // **************************************************************************** + // FUNCTION: add_to_wave() + // This function is used to display variables in this class in the waveform + // viewer. The start_time and end_time variables must be set before this + // function is called. If the start_time and end_time variables are not set + // the transaction will be hidden at 0ns on the waveform display. + // + virtual function void add_to_wave(int transaction_viewing_stream_h); + `ifdef QUESTA + if (transaction_view_h == 0) begin + transaction_view_h = $begin_transaction(transaction_viewing_stream_h,"fuse_ctrl_core_axi_read_out_transaction",start_time); + end + super.add_to_wave(transaction_view_h); + // pragma uvmf custom add_to_wave begin + // UVMF_CHANGE_ME : Color can be applied to transaction entries based on content, example below + // case() + // 1 : $add_color(transaction_view_h,"red"); + // default : $add_color(transaction_view_h,"grey"); + // endcase + // UVMF_CHANGE_ME : Eliminate transaction variables not wanted in transaction viewing in the waveform viewer + $add_attribute(transaction_view_h,core_arready,"core_arready"); + $add_attribute(transaction_view_h,core_rdata,"core_rdata"); + $add_attribute(transaction_view_h,core_rresp,"core_rresp"); + $add_attribute(transaction_view_h,core_rid,"core_rid"); + $add_attribute(transaction_view_h,core_rlast,"core_rlast"); + $add_attribute(transaction_view_h,core_rvalid,"core_rvalid"); + // pragma uvmf custom add_to_wave end + $end_transaction(transaction_view_h,end_time); + $free_transaction(transaction_view_h); + `endif // QUESTA + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_transaction_coverage.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_transaction_coverage.svh new file mode 100644 index 0000000..ad53e49 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_transaction_coverage.svh @@ -0,0 +1,107 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class records fuse_ctrl_core_axi_read_out transaction information using +// a covergroup named fuse_ctrl_core_axi_read_out_transaction_cg. An instance of this +// coverage component is instantiated in the uvmf_parameterized_agent +// if the has_coverage flag is set. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_read_out_transaction_coverage #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvm_subscriber #(.T(fuse_ctrl_core_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +)); + + `uvm_component_param_utils( fuse_ctrl_core_axi_read_out_transaction_coverage #( + AW, + DW, + IW, + UW + ) +) + + T coverage_trans; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + covergroup fuse_ctrl_core_axi_read_out_transaction_cg; + // pragma uvmf custom covergroup begin + // UVMF_CHANGE_ME : Add coverage bins, crosses, exclusions, etc. according to coverage needs. + option.auto_bin_max=1024; + option.per_instance=1; + core_arready: coverpoint coverage_trans.core_arready; + core_rdata: coverpoint coverage_trans.core_rdata; + core_rresp: coverpoint coverage_trans.core_rresp; + core_rid: coverpoint coverage_trans.core_rid; + core_rlast: coverpoint coverage_trans.core_rlast; + core_rvalid: coverpoint coverage_trans.core_rvalid; + // pragma uvmf custom covergroup end + endgroup + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new(string name="", uvm_component parent=null); + super.new(name,parent); + fuse_ctrl_core_axi_read_out_transaction_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that transaction variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + endfunction + + // **************************************************************************** + // FUNCTION : build_phase() + // This function is the standard UVM build_phase. + // + function void build_phase(uvm_phase phase); + fuse_ctrl_core_axi_read_out_transaction_cg.set_inst_name($sformatf("fuse_ctrl_core_axi_read_out_transaction_cg_%s",get_full_name())); + endfunction + + // **************************************************************************** + // FUNCTION: write (T t) + // This function is automatically executed when a transaction arrives on the + // analysis_export. It copies values from the variables in the transaction + // to local variables used to collect functional coverage. + // + virtual function void write (T t); + `uvm_info("COV","Received transaction",UVM_HIGH); + coverage_trans = t; + fuse_ctrl_core_axi_read_out_transaction_cg.sample(); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_typedefs.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_typedefs.svh new file mode 100644 index 0000000..f2a7bdb --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_typedefs.svh @@ -0,0 +1,34 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the host server when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_typedefs_hdl.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_typedefs_hdl.svh new file mode 100644 index 0000000..0d58518 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/src/fuse_ctrl_core_axi_read_out_typedefs_hdl.svh @@ -0,0 +1,35 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the emulator when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/yaml/fuse_ctrl_core_axi_read_out_interface.yaml b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/yaml/fuse_ctrl_core_axi_read_out_interface.yaml new file mode 100644 index 0000000..9e2244b --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_read_out_pkg/yaml/fuse_ctrl_core_axi_read_out_interface.yaml @@ -0,0 +1,91 @@ +uvmf: + interfaces: + fuse_ctrl_core_axi_read_out: + clock: clk_i + config_constraints: [] + config_vars: [] + existing_library_component: 'True' + gen_inbound_streaming_driver: 'False' + hdl_pkg_parameters: [] + hdl_typedefs: [] + hvl_pkg_parameters: [] + hvl_typedefs: [] + parameters: + - name: AW + type: int + value: '32' + - name: DW + type: int + value: '32' + - name: IW + type: int + value: '3' + - name: UW + type: int + value: '32' + ports: + - dir: input + name: arready + reset_value: '''bz' + width: '1' + - dir: input + name: rdata + reset_value: '''bz' + width: DW + - dir: input + name: rresp + reset_value: '''bz' + width: '1' + - dir: input + name: rid + reset_value: '''bz' + width: '1' + - dir: input + name: rlast + reset_value: '''bz' + width: '1' + - dir: input + name: rvalid + reset_value: '''bz' + width: '1' + reset: rst_ni + reset_assertion_level: 'False' + transaction_constraints: [] + transaction_vars: + - comment: '' + iscompare: 'True' + isrand: 'False' + name: core_arready + type: logic + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'False' + name: core_rdata + type: logic [DW-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'False' + name: core_rresp + type: axi_pkg::axi_burst_e + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'False' + name: core_rid + type: logic [IW-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'False' + name: core_rlast + type: logic + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'False' + name: core_rvalid + type: logic + unpacked_dimension: '' + use_dpi_link: 'False' diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/.project b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/.project new file mode 100644 index 0000000..b26e81c --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/.project @@ -0,0 +1,30 @@ + + + fuse_ctrl_core_axi_write_in_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/.svproject b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/.svproject new file mode 100644 index 0000000..be11cb6 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/Makefile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/Makefile new file mode 100644 index 0000000..b9ea6af --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/Makefile @@ -0,0 +1,66 @@ +# fuse_ctrl_core_axi_write_in interface packages source +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +fuse_ctrl_core_axi_write_in_PKG = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_write_in_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_filelist_hvl.f + +fuse_ctrl_core_axi_write_in_PKG_HDL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_write_in_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_filelist_hdl.f + +fuse_ctrl_core_axi_write_in_PKG_XRTL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_write_in_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_filelist_xrtl.f + +COMP_fuse_ctrl_core_axi_write_in_PKG_TGT_0 = q_comp_fuse_ctrl_core_axi_write_in_pkg +COMP_fuse_ctrl_core_axi_write_in_PKG_TGT_1 = v_comp_fuse_ctrl_core_axi_write_in_pkg +COMP_fuse_ctrl_core_axi_write_in_PKG_TGT = $(COMP_fuse_ctrl_core_axi_write_in_PKG_TGT_$(USE_VELOCE)) + +comp_fuse_ctrl_core_axi_write_in_pkg: $(COMP_fuse_ctrl_core_axi_write_in_PKG_TGT) + +q_comp_fuse_ctrl_core_axi_write_in_pkg: + $(HDL_COMP_CMD) $(fuse_ctrl_core_axi_write_in_PKG_HDL) + $(HVL_COMP_CMD) $(fuse_ctrl_core_axi_write_in_PKG) + $(HDL_COMP_CMD) $(fuse_ctrl_core_axi_write_in_PKG_XRTL) + +v_comp_fuse_ctrl_core_axi_write_in_pkg: + $(HVL_COMP_CMD) $(fuse_ctrl_core_axi_write_in_PKG_HDL) + $(HVL_COMP_CMD) $(fuse_ctrl_core_axi_write_in_PKG) + $(VELANALYZE_CMD) $(fuse_ctrl_core_axi_write_in_PKG_HDL) + $(VELANALYZE_HVL_CMD) $(fuse_ctrl_core_axi_write_in_PKG) + $(HDL_COMP_CMD) $(fuse_ctrl_core_axi_write_in_PKG_XRTL) + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export fuse_ctrl_core_axi_write_in_IF_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_write_in_pkg/dpi + +C_FILE_COMPILE_LIST_fuse_ctrl_core_axi_write_in_pkg = \ + +O_FILE_COMPILE_LIST_fuse_ctrl_core_axi_write_in_pkg = $(notdir $(C_FILE_COMPILE_LIST_fuse_ctrl_core_axi_write_in_pkg:.c=.o)) + +GCC_COMP_ARGS_fuse_ctrl_core_axi_write_in_pkg += -I$(fuse_ctrl_core_axi_write_in_IF_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_fuse_ctrl_core_axi_write_in_pkg += $(fuse_ctrl_core_axi_write_in_IF_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_fuse_ctrl_core_axi_write_in_pkg += \ + \ + -o .so + +comp_fuse_ctrl_core_axi_write_in_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Interface C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_fuse_ctrl_core_axi_write_in_pkg) $(C_FILE_COMPILE_LIST_fuse_ctrl_core_axi_write_in_pkg) + @echo "--------------------------------" + @echo "Linking Interface C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_fuse_ctrl_core_axi_write_in_pkg) $(O_FILE_COMPILE_LIST_fuse_ctrl_core_axi_write_in_pkg) + @echo "--------------------------------" + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/compile.do b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/compile.do new file mode 100644 index 0000000..a2f727a --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/compile.do @@ -0,0 +1,14 @@ +# Tcl do file for compile of fuse_ctrl_core_axi_write_in interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_write_in_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_filelist_hdl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_write_in_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_filelist_hvl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_write_in_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_filelist_xrtl.f \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in.compile new file mode 100644 index 0000000..328de17 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in.compile @@ -0,0 +1,3 @@ +needs: + - fuse_ctrl_core_axi_write_in_hvl.compile + - fuse_ctrl_core_axi_write_in_hdl.compile diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_bfm.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_bfm.vinfo new file mode 100644 index 0000000..8580294 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_bfm.vinfo @@ -0,0 +1,6 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use fuse_ctrl_core_axi_write_in_pkg_hdl.vinfo ++incdir+@vinfodir +src/fuse_ctrl_core_axi_write_in_if.sv +src/fuse_ctrl_core_axi_write_in_driver_bfm.sv +src/fuse_ctrl_core_axi_write_in_monitor_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_common.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_common.compile new file mode 100644 index 0000000..ebcb42c --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_common.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +incdir: + - . + - ${uvm_path}/src +src: + - fuse_ctrl_core_axi_write_in_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_filelist_hdl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_filelist_hdl.f new file mode 100644 index 0000000..dcea9f3 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_filelist_hdl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_filelist_hvl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_filelist_hvl.f new file mode 100644 index 0000000..0aa6cf4 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_filelist_hvl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_pkg.sv \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_filelist_xrtl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_filelist_xrtl.f new file mode 100644 index 0000000..9729a9f --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_filelist_xrtl.f @@ -0,0 +1,3 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_if.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_monitor_bfm.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_driver_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_hdl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_hdl.compile new file mode 100644 index 0000000..b28a2bd --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_hdl.compile @@ -0,0 +1,9 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ./fuse_ctrl_core_axi_write_in_common.compile +incdir: + - . +src: + - src/fuse_ctrl_core_axi_write_in_if.sv + - src/fuse_ctrl_core_axi_write_in_monitor_bfm.sv + - src/fuse_ctrl_core_axi_write_in_driver_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_hvl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_hvl.compile new file mode 100644 index 0000000..7801ce4 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_hvl.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ./fuse_ctrl_core_axi_write_in_common.compile +incdir: + - . +src: + - fuse_ctrl_core_axi_write_in_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_pkg.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_pkg.sv new file mode 100644 index 0000000..af90383 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_pkg.sv @@ -0,0 +1,91 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - + +// - +// - +// - + +// - +// - +// - + +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_core_axi_write_in_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg_hdl::*; + import uvmf_base_pkg::*; + import fuse_ctrl_core_axi_write_in_pkg_hdl::*; + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + `include "src/fuse_ctrl_core_axi_write_in_macros.svh" + + export fuse_ctrl_core_axi_write_in_pkg_hdl::*; + + + + // Parameters defined as HVL parameters + + `include "src/fuse_ctrl_core_axi_write_in_typedefs.svh" + `include "src/fuse_ctrl_core_axi_write_in_transaction.svh" + + `include "src/fuse_ctrl_core_axi_write_in_configuration.svh" + `include "src/fuse_ctrl_core_axi_write_in_driver.svh" + `include "src/fuse_ctrl_core_axi_write_in_monitor.svh" + + `include "src/fuse_ctrl_core_axi_write_in_transaction_coverage.svh" + `include "src/fuse_ctrl_core_axi_write_in_sequence_base.svh" + `include "src/fuse_ctrl_core_axi_write_in_random_sequence.svh" + + `include "src/fuse_ctrl_core_axi_write_in_responder_sequence.svh" + `include "src/fuse_ctrl_core_axi_write_in2reg_adapter.svh" + + `include "src/fuse_ctrl_core_axi_write_in_agent.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new interface sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the interface package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_pkg.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_pkg.vinfo new file mode 100644 index 0000000..07d2c9a --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_pkg.vinfo @@ -0,0 +1,4 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use fuse_ctrl_core_axi_write_in_pkg_hdl.vinfo ++incdir+@vinfodir +fuse_ctrl_core_axi_write_in_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_pkg_hdl.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_pkg_hdl.sv new file mode 100644 index 0000000..48ee663 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_pkg_hdl.sv @@ -0,0 +1,52 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that needs to be compiled and synthesized +// for running on Veloce. +// +// CONTAINS: +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_core_axi_write_in_pkg_hdl; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HDL parameters + + `include "src/fuse_ctrl_core_axi_write_in_typedefs_hdl.svh" + `include "src/fuse_ctrl_core_axi_write_in_macros.svh" + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_pkg_hdl.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_pkg_hdl.vinfo new file mode 100644 index 0000000..5c56ef5 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_pkg_hdl.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +fuse_ctrl_core_axi_write_in_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_pkg_sve.F b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_pkg_sve.F new file mode 100644 index 0000000..24bdc9f --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_pkg_sve.F @@ -0,0 +1,10 @@ +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + ++incdir+. +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_filelist_hdl.f +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_core_axi_write_in_pkg/fuse_ctrl_core_axi_write_in_filelist_hvl.f diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in2reg_adapter.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in2reg_adapter.svh new file mode 100644 index 0000000..0265f70 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in2reg_adapter.svh @@ -0,0 +1,142 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the UVM register adapter for the fuse_ctrl_core_axi_write_in interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_write_in2reg_adapter #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvm_reg_adapter; + + `uvm_object_param_utils( fuse_ctrl_core_axi_write_in2reg_adapter #( + AW, + DW, + IW, + UW + ) +) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //-------------------------------------------------------------------- + // new + //-------------------------------------------------------------------- + function new (string name = "fuse_ctrl_core_axi_write_in2reg_adapter" ); + super.new(name); + // pragma uvmf custom new begin + // UVMF_CHANGE_ME : Configure the adapter regarding byte enables and provides response. + + // Does the protocol the Agent is modeling support byte enables? + // 0 = NO + // 1 = YES + supports_byte_enable = 0; + + // Does the Agent's Driver provide separate response sequence items? + // i.e. Does the driver call seq_item_port.put() + // and do the sequences call get_response()? + // 0 = NO + // 1 = YES + provides_responses = 0; + // pragma uvmf custom new end + + endfunction: new + + //-------------------------------------------------------------------- + // reg2bus + //-------------------------------------------------------------------- + virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw); + + fuse_ctrl_core_axi_write_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + trans_h = fuse_ctrl_core_axi_write_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +::type_id::create("trans_h"); + + // pragma uvmf custom reg2bus begin + // UVMF_CHANGE_ME : Fill in the reg2bus adapter mapping registe fields to protocol fields. + + //Adapt the following for your sequence item type + // trans_h.op = (rw.kind == UVM_READ) ? WB_READ : WB_WRITE; + //Copy over address + // trans_h.addr = rw.addr; + //Copy over write data + // trans_h.data = rw.data; + + // pragma uvmf custom reg2bus end + + // Return the adapted transaction + return trans_h; + + endfunction: reg2bus + + //-------------------------------------------------------------------- + // bus2reg + //-------------------------------------------------------------------- + virtual function void bus2reg(uvm_sequence_item bus_item, + ref uvm_reg_bus_op rw); + fuse_ctrl_core_axi_write_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + trans_h; + if (!$cast(trans_h, bus_item)) begin + `uvm_fatal("ADAPT","Provided bus_item is not of the correct type") + return; + end + // pragma uvmf custom bus2reg begin + // UVMF_CHANGE_ME : Fill in the bus2reg adapter mapping protocol fields to register fields. + //Adapt the following for your sequence item type + //Copy over instruction type + // rw.kind = (trans_h.op == WB_WRITE) ? UVM_WRITE : UVM_READ; + //Copy over address + // rw.addr = trans_h.addr; + //Copy over read data + // rw.data = trans_h.data; + //Check for errors on the bus and return UVM_NOT_OK if there is an error + // rw.status = UVM_IS_OK; + // pragma uvmf custom bus2reg end + + endfunction: bus2reg + +endclass : fuse_ctrl_core_axi_write_in2reg_adapter + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_agent.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_agent.svh new file mode 100644 index 0000000..2bd552a --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_agent.svh @@ -0,0 +1,109 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: Protocol specific agent class definition +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_write_in_agent #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvmf_parameterized_agent #( + .CONFIG_T(fuse_ctrl_core_axi_write_in_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .DRIVER_T(fuse_ctrl_core_axi_write_in_driver #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .MONITOR_T(fuse_ctrl_core_axi_write_in_monitor #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .COVERAGE_T(fuse_ctrl_core_axi_write_in_transaction_coverage #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .TRANS_T(fuse_ctrl_core_axi_write_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +) + ); + + `uvm_component_param_utils( fuse_ctrl_core_axi_write_in_agent #( + AW, + DW, + IW, + UW + ) +) + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** + // FUNCTION: build_phase + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + if (configuration.active_passive == ACTIVE) begin + // Place sequencer handle into configuration object + // so that it may be retrieved from configuration + // rather than using uvm_config_db + configuration.sequencer = this.sequencer; + end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_configuration.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_configuration.svh new file mode 100644 index 0000000..374ebfb --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_configuration.svh @@ -0,0 +1,241 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class contains all variables and functions used +// to configure the fuse_ctrl_core_axi_write_in agent and its bfm's. It gets the +// bfm's from the uvm_config_db for use by the agent. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_write_in_configuration #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvmf_parameterized_agent_configuration_base #( + .DRIVER_BFM_BIND_T(virtual fuse_ctrl_core_axi_write_in_driver_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .MONITOR_BFM_BIND_T( virtual fuse_ctrl_core_axi_write_in_monitor_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +)); + + `uvm_object_param_utils( fuse_ctrl_core_axi_write_in_configuration #( + AW, + DW, + IW, + UW + ) +) + + + // Sequencer handle populated by agent + uvm_sequencer #(fuse_ctrl_core_axi_write_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + ) sequencer; + + //Constraints for the configuration variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + covergroup fuse_ctrl_core_axi_write_in_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + // pragma uvmf custom covergroup end + endgroup + + //******************************************************************* + //******************************************************************* + // Structure used to pass configuration variables to monitor and driver BFM's. + // Use to_struct function to pack variables into structure. + // Use from_struct function to unpack variables from structure. + // This structure is defined in fuse_ctrl_core_axi_write_in_macros.svh + `fuse_ctrl_core_axi_write_in_CONFIGURATION_STRUCT + fuse_ctrl_core_axi_write_in_configuration_s fuse_ctrl_core_axi_write_in_configuration_struct; + //******************************************************************* + // FUNCTION: to_struct() + // This function packs variables into a fuse_ctrl_core_axi_write_in_configuration_s + // structure. The function returns the handle to the fuse_ctrl_core_axi_write_in_configuration_struct. + // This function is defined in fuse_ctrl_core_axi_write_in_macros.svh + `fuse_ctrl_core_axi_write_in_CONFIGURATION_TO_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_struct() + // This function unpacks the struct provided as an argument into + // variables of this class. + // This function is defined in fuse_ctrl_core_axi_write_in_macros.svh + `fuse_ctrl_core_axi_write_in_CONFIGURATION_FROM_STRUCT_FUNCTION + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + // Construct the covergroup for this configuration class + fuse_ctrl_core_axi_write_in_configuration_cg = new; + endfunction + + // **************************************************************************** + // FUNCTION: post_randomize() + // This function is automatically called after the randomize() function + // is executed. + // + function void post_randomize(); + super.post_randomize(); + fuse_ctrl_core_axi_write_in_configuration_cg.sample(); + endfunction + + // **************************************************************************** + // FUNCTION: initialize + // This function causes the configuration to retrieve + // its virtual interface handle from the uvm_config_db. + // This function also makes itself available to its + // agent through the uvm_config_db. + // + // ARGUMENTS: + // uvmf_active_passive_t activity: + // This argument identifies the simulation level + // as either BLOCK, CHIP, SIMULATION, etc. + // + // AGENT_PATH: + // This argument identifies the path to this + // configurations agent. This configuration + // makes itself available to the agent specified + // by agent_path by placing itself into the + // uvm_config_db. + // + // INTERFACE_NAME: + // This argument identifies the string name of + // this configurations BFM's. This string + // name is used to retrieve the driver and + // monitor BFM from the uvm_config_db. + // + virtual function void initialize(uvmf_active_passive_t activity, + string agent_path, + string interface_name); + + super.initialize( activity, agent_path, interface_name); + // The covergroup is given the same name as the interface + fuse_ctrl_core_axi_write_in_configuration_cg.set_inst_name(interface_name); + + // This configuration places itself into the uvm_config_db for the agent, identified by the agent_path variable, to retrieve. + uvm_config_db #( fuse_ctrl_core_axi_write_in_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + + )::set( null ,agent_path,UVMF_AGENT_CONFIG, this ); + + // This configuration also places itself in the config db using the same identifier used by the interface. This allows users to access + // configuration variables and the interface through the bfm api class rather than directly accessing the BFM. This is useful for + // accessingthe BFM when using Veloce + uvm_config_db #( fuse_ctrl_core_axi_write_in_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + + )::set( null ,UVMF_CONFIGURATIONS, interface_name, this ); + + fuse_ctrl_core_axi_write_in_configuration_cg.set_inst_name($sformatf("fuse_ctrl_core_axi_write_in_configuration_cg_%s",get_full_name())); + +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. + `uvm_info("CFG", + $psprintf("The agent at '%s' is using interface named %s has the following parameters: AW=%x DW=%x IW=%x UW=%x ", agent_path, interface_name, AW ,DW ,IW ,UW ), + UVM_DEBUG) + + // pragma uvmf custom initialize begin + // This controls whether or not the agent returns a transaction handle in the driver when calling + // item_done() back into the sequencer or not. If set to 1, a transaction is sent back which means + // the sequence on the other end must use the get_response() part of the driver/sequence API. If + // this doesn't occur, there will eventually be response_queue overflow errors during the test. + return_transaction_response = 1'b0; + + // pragma uvmf custom initialize end + + endfunction + + // **************************************************************************** + // TASK: wait_for_reset + // *[Required]* Blocks until reset is released. The wait_for_reset operation is performed + // by a task in the monitor bfm. + virtual task wait_for_reset(); + monitor_bfm.wait_for_reset(); + endtask + + // **************************************************************************** + // TASK: wait_for_num_clocks + // *[Required]* Blocks until specified number of clocks have elapsed. The wait_for_num_clocks + // operation is performed by a task in the monitor bfm. + virtual task wait_for_num_clocks(int clocks); + monitor_bfm.wait_for_num_clocks(clocks); + endtask + + // **************************************************************************** + // FUNCTION : convert2string() + // This function is used to convert variables in this class into a string for log messaging. + // + virtual function string convert2string (); + // pragma uvmf custom convert2string begin + return $sformatf(""); + // pragma uvmf custom convert2string end + endfunction + + // **************************************************************************** + // FUNCTION: get_sequencer + function uvm_sequencer #(fuse_ctrl_core_axi_write_in_transaction#( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +) get_sequencer(); + return sequencer; + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_driver.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_driver.svh new file mode 100644 index 0000000..2454403 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_driver.svh @@ -0,0 +1,141 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class passes transactions between the sequencer +// and the BFM driver interface. It accesses the driver BFM +// through the bfm handle. This driver +// passes transactions to the driver BFM through the access +// task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_write_in_driver #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvmf_driver_base #( + .CONFIG_T(fuse_ctrl_core_axi_write_in_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + ), + .BFM_BIND_T(virtual fuse_ctrl_core_axi_write_in_driver_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + ), + .REQ(fuse_ctrl_core_axi_write_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + ), + .RSP(fuse_ctrl_core_axi_write_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + )); + + `uvm_component_param_utils( fuse_ctrl_core_axi_write_in_driver #( + AW, + DW, + IW, + UW + ) +) +//******************************************************************* +// Macros that define structs located in fuse_ctrl_core_axi_write_in_macros.svh +//******************************************************************* +// Initiator macro used by fuse_ctrl_core_axi_write_in_driver and fuse_ctrl_core_axi_write_in_driver_bfm +// to communicate initiator driven data to fuse_ctrl_core_axi_write_in_driver_bfm. +`fuse_ctrl_core_axi_write_in_INITIATOR_STRUCT + fuse_ctrl_core_axi_write_in_initiator_s fuse_ctrl_core_axi_write_in_initiator_struct; +//******************************************************************* +// Responder macro used by fuse_ctrl_core_axi_write_in_driver and fuse_ctrl_core_axi_write_in_driver_bfm +// to communicate Responder driven data to fuse_ctrl_core_axi_write_in_driver_bfm. +`fuse_ctrl_core_axi_write_in_RESPONDER_STRUCT + fuse_ctrl_core_axi_write_in_responder_s fuse_ctrl_core_axi_write_in_responder_struct; + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent=null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the driver BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// driver BFM. This allows the driver BFM to call tasks and function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// **************************************************************************** +// This task is called by the run_phase in uvmf_driver_base. + virtual task access( inout REQ txn ); +// pragma uvmf custom access begin + if (configuration.initiator_responder==RESPONDER) begin + // Complete current transfer and wait for next transfer + bfm.respond_and_wait_for_next_transfer( + fuse_ctrl_core_axi_write_in_initiator_struct, + txn.to_responder_struct() + ); + // Unpack information about initiated transfer received by this responder + txn.from_initiator_struct(fuse_ctrl_core_axi_write_in_initiator_struct); + end else begin + // Initiate a transfer and get response + bfm.initiate_and_get_response( + txn.to_initiator_struct(), + fuse_ctrl_core_axi_write_in_responder_struct + ); + // Unpack transfer response information received by this initiator + txn.from_responder_struct(fuse_ctrl_core_axi_write_in_responder_struct); + end +// pragma uvmf custom access end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_driver_bfm.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_driver_bfm.sv new file mode 100644 index 0000000..934c0f8 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_driver_bfm.sv @@ -0,0 +1,429 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This interface performs the fuse_ctrl_core_axi_write_in signal driving. It is +// accessed by the uvm fuse_ctrl_core_axi_write_in driver through a virtual interface +// handle in the fuse_ctrl_core_axi_write_in configuration. It drives the singals passed +// in through the port connection named bus of type fuse_ctrl_core_axi_write_in_if. +// +// Input signals from the fuse_ctrl_core_axi_write_in_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// This bfm drives signals with a _o suffix. These signals +// are driven onto signals within fuse_ctrl_core_axi_write_in_if based on INITIATOR/RESPONDER and/or +// ARBITRATION/GRANT status. +// +// The output signal connections are as follows: +// signal_o -> bus.signal +// +// +// Interface functions and tasks used by UVM components: +// +// configure: +// This function gets configuration attributes from the +// UVM driver to set any required BFM configuration +// variables such as 'initiator_responder'. +// +// initiate_and_get_response: +// This task is used to perform signaling activity for initiating +// a protocol transfer. The task initiates the transfer, using +// input data from the initiator struct. Then the task captures +// response data, placing the data into the response struct. +// The response struct is returned to the driver class. +// +// respond_and_wait_for_next_transfer: +// This task is used to complete a current transfer as a responder +// and then wait for the initiator to start the next transfer. +// The task uses data in the responder struct to drive protocol +// signals to complete the transfer. The task then waits for +// the next transfer. Once the next transfer begins, data from +// the initiator is placed into the initiator struct and sent +// to the responder sequence for processing to determine +// what data to respond with. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_core_axi_write_in_pkg_hdl::*; +`include "src/fuse_ctrl_core_axi_write_in_macros.svh" + +interface fuse_ctrl_core_axi_write_in_driver_bfm #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + + (fuse_ctrl_core_axi_write_in_if bus); + // The following pragma and additional ones in-lined further below are for running this BFM on Veloce + // pragma attribute fuse_ctrl_core_axi_write_in_driver_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: AW=%x DW=%x IW=%x UW=%x ", AW,DW,IW,UW), + UVM_DEBUG) +end +`endif + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + tri clk_i_i; + tri rst_ni_i; + + // Signal list (all signals are capable of being inputs and outputs for the sake + // of supporting both INITIATOR and RESPONDER mode operation. Expectation is that + // directionality in the config file was from the point-of-view of the INITIATOR + + // INITIATOR mode input signals + + // INITIATOR mode output signals + tri [AW-1:0] awaddr_i; + reg [AW-1:0] awaddr_o = 'bz; + tri [$bits(axi_pkg::axi_burst_e)-1:0] awburst_i; + reg [$bits(axi_pkg::axi_burst_e)-1:0] awburst_o = 'bz; + tri [2:0] awsize_i; + reg [2:0] awsize_o = 'bz; + tri [7:0] awlen_i; + reg [7:0] awlen_o = 'bz; + tri [UW-1:0] awuser_i; + reg [UW-1:0] awuser_o = 'bz; + tri [UW-1:0] awid_i; + reg [UW-1:0] awid_o = 'bz; + tri awlock_i; + reg awlock_o = 'bz; + tri awvalid_i; + reg awvalid_o = 'bz; + tri [DW-1:0] wdata_i; + reg [DW-1:0] wdata_o = 'bz; + tri [DW/8-1:0] wstrb_i; + reg [DW/8-1:0] wstrb_o = 'bz; + tri wvalid_i; + reg wvalid_o = 'bz; + tri wlast_i; + reg wlast_o = 'bz; + tri bready_i; + reg bready_o = 'bz; + + // Bi-directional signals + + + assign clk_i_i = bus.clk_i; + assign rst_ni_i = bus.rst_ni; + + // These are signals marked as 'input' by the config file, but the signals will be + // driven by this BFM if put into RESPONDER mode (flipping all signal directions around) + + + // These are signals marked as 'output' by the config file, but the outputs will + // not be driven by this BFM unless placed in INITIATOR mode. + assign bus.awaddr = (initiator_responder == INITIATOR) ? awaddr_o : 'bz; + assign awaddr_i = bus.awaddr; + assign bus.awburst = (initiator_responder == INITIATOR) ? awburst_o : 'bz; + assign awburst_i = bus.awburst; + assign bus.awsize = (initiator_responder == INITIATOR) ? awsize_o : 'bz; + assign awsize_i = bus.awsize; + assign bus.awlen = (initiator_responder == INITIATOR) ? awlen_o : 'bz; + assign awlen_i = bus.awlen; + assign bus.awuser = (initiator_responder == INITIATOR) ? awuser_o : 'bz; + assign awuser_i = bus.awuser; + assign bus.awid = (initiator_responder == INITIATOR) ? awid_o : 'bz; + assign awid_i = bus.awid; + assign bus.awlock = (initiator_responder == INITIATOR) ? awlock_o : 'bz; + assign awlock_i = bus.awlock; + assign bus.awvalid = (initiator_responder == INITIATOR) ? awvalid_o : 'bz; + assign awvalid_i = bus.awvalid; + assign bus.wdata = (initiator_responder == INITIATOR) ? wdata_o : 'bz; + assign wdata_i = bus.wdata; + assign bus.wstrb = (initiator_responder == INITIATOR) ? wstrb_o : 'bz; + assign wstrb_i = bus.wstrb; + assign bus.wvalid = (initiator_responder == INITIATOR) ? wvalid_o : 'bz; + assign wvalid_i = bus.wvalid; + assign bus.wlast = (initiator_responder == INITIATOR) ? wlast_o : 'bz; + assign wlast_i = bus.wlast; + assign bus.bready = (initiator_responder == INITIATOR) ? bready_o : 'bz; + assign bready_i = bus.bready; + + // Proxy handle to UVM driver + fuse_ctrl_core_axi_write_in_pkg::fuse_ctrl_core_axi_write_in_driver #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + proxy; + // pragma tbx oneway proxy.my_function_name_in_uvm_driver + + // **************************************************************************** + // **************************************************************************** + // Macros that define structs located in fuse_ctrl_core_axi_write_in_macros.svh + // **************************************************************************** + // Struct for passing configuration data from fuse_ctrl_core_axi_write_in_driver to this BFM + // **************************************************************************** + `fuse_ctrl_core_axi_write_in_CONFIGURATION_STRUCT + // **************************************************************************** + // Structs for INITIATOR and RESPONDER data flow + //******************************************************************* + // Initiator macro used by fuse_ctrl_core_axi_write_in_driver and fuse_ctrl_core_axi_write_in_driver_bfm + // to communicate initiator driven data to fuse_ctrl_core_axi_write_in_driver_bfm. + `fuse_ctrl_core_axi_write_in_INITIATOR_STRUCT + fuse_ctrl_core_axi_write_in_initiator_s initiator_struct; + // Responder macro used by fuse_ctrl_core_axi_write_in_driver and fuse_ctrl_core_axi_write_in_driver_bfm + // to communicate Responder driven data to fuse_ctrl_core_axi_write_in_driver_bfm. + `fuse_ctrl_core_axi_write_in_RESPONDER_STRUCT + fuse_ctrl_core_axi_write_in_responder_s responder_struct; + + // **************************************************************************** +// pragma uvmf custom reset_condition_and_response begin + // Always block used to return signals to reset value upon assertion of reset + always @( negedge rst_ni_i ) + begin + // RESPONDER mode output signals + // INITIATOR mode output signals + awaddr_o <= 'bz; + awburst_o <= 'bz; + awsize_o <= 'bz; + awlen_o <= 'bz; + awuser_o <= 'bz; + awid_o <= 'bz; + awlock_o <= 'bz; + awvalid_o <= 'bz; + wdata_o <= 'bz; + wstrb_o <= 'bz; + wvalid_o <= 'bz; + wlast_o <= 'bz; + bready_o <= 'bz; + // Bi-directional signals + + end +// pragma uvmf custom reset_condition_and_response end + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the driver BFM. It is called by the driver within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the driver BFM needs to be aware of the new configuration + // variables. + // + + function void configure(fuse_ctrl_core_axi_write_in_configuration_s fuse_ctrl_core_axi_write_in_configuration_arg); // pragma tbx xtf + initiator_responder = fuse_ctrl_core_axi_write_in_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + +// pragma uvmf custom initiate_and_get_response begin +// **************************************************************************** +// UVMF_CHANGE_ME +// This task is used by an initator. The task first initiates a transfer then +// waits for the responder to complete the transfer. + task initiate_and_get_response( + // This argument passes transaction variables used by an initiator + // to perform the initial part of a protocol transfer. The values + // come from a sequence item created in a sequence. + input fuse_ctrl_core_axi_write_in_initiator_s fuse_ctrl_core_axi_write_in_initiator_struct, + // This argument is used to send data received from the responder + // back to the sequence item. The sequence item is returned to the sequence. + output fuse_ctrl_core_axi_write_in_responder_s fuse_ctrl_core_axi_write_in_responder_struct + );// pragma tbx xtf + // + // Members within the fuse_ctrl_core_axi_write_in_initiator_struct: + // logic [AW-1:0] core_awaddr ; + // logic core_awvalid ; + // logic [$bits(axi_pkg::axi_burst_e)] core_awburst ; + // logic [2:0] core_awsize ; + // logic [7:0] core_awlen ; + // logic [UW-1:0] core_awuser ; + // logic [IW-1:0] core_awid ; + // logic core_awlock ; + // logic [DW-1:0] core_wdata ; + // logic [DW/8 - 1:0] core_wstrb ; + // logic core_wvalid ; + // logic core_wlast ; + // logic core_bready ; + // Members within the fuse_ctrl_core_axi_write_in_responder_struct: + // logic [AW-1:0] core_awaddr ; + // logic core_awvalid ; + // logic [$bits(axi_pkg::axi_burst_e)] core_awburst ; + // logic [2:0] core_awsize ; + // logic [7:0] core_awlen ; + // logic [UW-1:0] core_awuser ; + // logic [IW-1:0] core_awid ; + // logic core_awlock ; + // logic [DW-1:0] core_wdata ; + // logic [DW/8 - 1:0] core_wstrb ; + // logic core_wvalid ; + // logic core_wlast ; + // logic core_bready ; + initiator_struct = fuse_ctrl_core_axi_write_in_initiator_struct; + // + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clk_i_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available initiator input and inout signals listed. + // Initiator input signals + // Initiator inout signals + // How to assign a signal from an initiator struct member named xyz. + // All available initiator output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Initiator output signals + // awaddr_o <= fuse_ctrl_core_axi_write_in_initiator_struct.xyz; // [AW-1:0] + // awburst_o <= fuse_ctrl_core_axi_write_in_initiator_struct.xyz; // [$bits(axi_pkg::axi_burst_e)-1:0] + // awsize_o <= fuse_ctrl_core_axi_write_in_initiator_struct.xyz; // [2:0] + // awlen_o <= fuse_ctrl_core_axi_write_in_initiator_struct.xyz; // [7:0] + // awuser_o <= fuse_ctrl_core_axi_write_in_initiator_struct.xyz; // [UW-1:0] + // awid_o <= fuse_ctrl_core_axi_write_in_initiator_struct.xyz; // [UW-1:0] + // awlock_o <= fuse_ctrl_core_axi_write_in_initiator_struct.xyz; // + // awvalid_o <= fuse_ctrl_core_axi_write_in_initiator_struct.xyz; // + // wdata_o <= fuse_ctrl_core_axi_write_in_initiator_struct.xyz; // [DW-1:0] + // wstrb_o <= fuse_ctrl_core_axi_write_in_initiator_struct.xyz; // [DW/8-1:0] + // wvalid_o <= fuse_ctrl_core_axi_write_in_initiator_struct.xyz; // + // wlast_o <= fuse_ctrl_core_axi_write_in_initiator_struct.xyz; // + // bready_o <= fuse_ctrl_core_axi_write_in_initiator_struct.xyz; // + // Initiator inout signals + // Initiate a transfer using the data received. + @(posedge clk_i_i); + @(posedge clk_i_i); + // Wait for the responder to complete the transfer then place the responder data into + // fuse_ctrl_core_axi_write_in_responder_struct. + @(posedge clk_i_i); + @(posedge clk_i_i); + responder_struct = fuse_ctrl_core_axi_write_in_responder_struct; + endtask +// pragma uvmf custom initiate_and_get_response end + +// pragma uvmf custom respond_and_wait_for_next_transfer begin +// **************************************************************************** +// The first_transfer variable is used to prevent completing a transfer in the +// first call to this task. For the first call to this task, there is not +// current transfer to complete. +bit first_transfer=1; + +// UVMF_CHANGE_ME +// This task is used by a responder. The task first completes the current +// transfer in progress then waits for the initiator to start the next transfer. + task respond_and_wait_for_next_transfer( + // This argument is used to send data received from the initiator + // back to the sequence item. The sequence determines how to respond. + output fuse_ctrl_core_axi_write_in_initiator_s fuse_ctrl_core_axi_write_in_initiator_struct, + // This argument passes transaction variables used by a responder + // to complete a protocol transfer. The values come from a sequence item. + input fuse_ctrl_core_axi_write_in_responder_s fuse_ctrl_core_axi_write_in_responder_struct + );// pragma tbx xtf + // Variables within the fuse_ctrl_core_axi_write_in_initiator_struct: + // logic [AW-1:0] core_awaddr ; + // logic core_awvalid ; + // logic [$bits(axi_pkg::axi_burst_e)] core_awburst ; + // logic [2:0] core_awsize ; + // logic [7:0] core_awlen ; + // logic [UW-1:0] core_awuser ; + // logic [IW-1:0] core_awid ; + // logic core_awlock ; + // logic [DW-1:0] core_wdata ; + // logic [DW/8 - 1:0] core_wstrb ; + // logic core_wvalid ; + // logic core_wlast ; + // logic core_bready ; + // Variables within the fuse_ctrl_core_axi_write_in_responder_struct: + // logic [AW-1:0] core_awaddr ; + // logic core_awvalid ; + // logic [$bits(axi_pkg::axi_burst_e)] core_awburst ; + // logic [2:0] core_awsize ; + // logic [7:0] core_awlen ; + // logic [UW-1:0] core_awuser ; + // logic [IW-1:0] core_awid ; + // logic core_awlock ; + // logic [DW-1:0] core_wdata ; + // logic [DW/8 - 1:0] core_wstrb ; + // logic core_wvalid ; + // logic core_wlast ; + // logic core_bready ; + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clk_i_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available responder input and inout signals listed. + // Responder input signals + // fuse_ctrl_core_axi_write_in_responder_struct.xyz = awaddr_i; // [AW-1:0] + // fuse_ctrl_core_axi_write_in_responder_struct.xyz = awburst_i; // [$bits(axi_pkg::axi_burst_e)-1:0] + // fuse_ctrl_core_axi_write_in_responder_struct.xyz = awsize_i; // [2:0] + // fuse_ctrl_core_axi_write_in_responder_struct.xyz = awlen_i; // [7:0] + // fuse_ctrl_core_axi_write_in_responder_struct.xyz = awuser_i; // [UW-1:0] + // fuse_ctrl_core_axi_write_in_responder_struct.xyz = awid_i; // [UW-1:0] + // fuse_ctrl_core_axi_write_in_responder_struct.xyz = awlock_i; // + // fuse_ctrl_core_axi_write_in_responder_struct.xyz = awvalid_i; // + // fuse_ctrl_core_axi_write_in_responder_struct.xyz = wdata_i; // [DW-1:0] + // fuse_ctrl_core_axi_write_in_responder_struct.xyz = wstrb_i; // [DW/8-1:0] + // fuse_ctrl_core_axi_write_in_responder_struct.xyz = wvalid_i; // + // fuse_ctrl_core_axi_write_in_responder_struct.xyz = wlast_i; // + // fuse_ctrl_core_axi_write_in_responder_struct.xyz = bready_i; // + // Responder inout signals + // How to assign a signal, named xyz, from an initiator struct member. + // All available responder output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Responder output signals + // Responder inout signals + + @(posedge clk_i_i); + if (!first_transfer) begin + // Perform transfer response here. + // Reply using data recieved in the fuse_ctrl_core_axi_write_in_responder_struct. + @(posedge clk_i_i); + // Reply using data recieved in the transaction handle. + @(posedge clk_i_i); + end + // Wait for next transfer then gather info from intiator about the transfer. + // Place the data into the fuse_ctrl_core_axi_write_in_initiator_struct. + @(posedge clk_i_i); + @(posedge clk_i_i); + first_transfer = 0; + endtask +// pragma uvmf custom respond_and_wait_for_next_transfer end + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_if.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_if.sv new file mode 100644 index 0000000..5208bdd --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_if.sv @@ -0,0 +1,144 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface contains the fuse_ctrl_core_axi_write_in interface signals. +// It is instantiated once per fuse_ctrl_core_axi_write_in bus. Bus Functional Models, +// BFM's named fuse_ctrl_core_axi_write_in_driver_bfm, are used to drive signals on the bus. +// BFM's named fuse_ctrl_core_axi_write_in_monitor_bfm are used to monitor signals on the +// bus. This interface signal bundle is passed in the port list of +// the BFM in order to give the BFM access to the signals in this +// interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// This template can be used to connect a DUT to these signals +// +// .dut_signal_port(fuse_ctrl_core_axi_write_in_bus.awaddr), // Agent output +// .dut_signal_port(fuse_ctrl_core_axi_write_in_bus.awburst), // Agent output +// .dut_signal_port(fuse_ctrl_core_axi_write_in_bus.awsize), // Agent output +// .dut_signal_port(fuse_ctrl_core_axi_write_in_bus.awlen), // Agent output +// .dut_signal_port(fuse_ctrl_core_axi_write_in_bus.awuser), // Agent output +// .dut_signal_port(fuse_ctrl_core_axi_write_in_bus.awid), // Agent output +// .dut_signal_port(fuse_ctrl_core_axi_write_in_bus.awlock), // Agent output +// .dut_signal_port(fuse_ctrl_core_axi_write_in_bus.awvalid), // Agent output +// .dut_signal_port(fuse_ctrl_core_axi_write_in_bus.wdata), // Agent output +// .dut_signal_port(fuse_ctrl_core_axi_write_in_bus.wstrb), // Agent output +// .dut_signal_port(fuse_ctrl_core_axi_write_in_bus.wvalid), // Agent output +// .dut_signal_port(fuse_ctrl_core_axi_write_in_bus.wlast), // Agent output +// .dut_signal_port(fuse_ctrl_core_axi_write_in_bus.bready), // Agent output + +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_core_axi_write_in_pkg_hdl::*; + +interface fuse_ctrl_core_axi_write_in_if #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + + + ( + input tri clk_i, + input tri rst_ni, + inout tri [AW-1:0] awaddr, + inout tri [$bits(axi_pkg::axi_burst_e)-1:0] awburst, + inout tri [2:0] awsize, + inout tri [7:0] awlen, + inout tri [UW-1:0] awuser, + inout tri [UW-1:0] awid, + inout tri awlock, + inout tri awvalid, + inout tri [DW-1:0] wdata, + inout tri [DW/8-1:0] wstrb, + inout tri wvalid, + inout tri wlast, + inout tri bready + ); + +modport monitor_port + ( + input clk_i, + input rst_ni, + input awaddr, + input awburst, + input awsize, + input awlen, + input awuser, + input awid, + input awlock, + input awvalid, + input wdata, + input wstrb, + input wvalid, + input wlast, + input bready + ); + +modport initiator_port + ( + input clk_i, + input rst_ni, + output awaddr, + output awburst, + output awsize, + output awlen, + output awuser, + output awid, + output awlock, + output awvalid, + output wdata, + output wstrb, + output wvalid, + output wlast, + output bready + ); + +modport responder_port + ( + input clk_i, + input rst_ni, + input awaddr, + input awburst, + input awsize, + input awlen, + input awuser, + input awid, + input awlock, + input awvalid, + input wdata, + input wstrb, + input wvalid, + input wlast, + input bready + ); + + +// pragma uvmf custom interface_item_additional begin +// pragma uvmf custom interface_item_additional end + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_infact_coverage_strategy.csv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_infact_coverage_strategy.csv new file mode 100644 index 0000000..1c218e1 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_infact_coverage_strategy.csv @@ -0,0 +1,6 @@ +Global +auto_bin_max, 64 + +Name,Type,Include +rand_fields,coverpoint,=rand *.** + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_macros.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_macros.svh new file mode 100644 index 0000000..c925c15 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_macros.svh @@ -0,0 +1,243 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains macros used with the fuse_ctrl_core_axi_write_in package. +// These macros include packed struct definitions. These structs are +// used to pass data between classes, hvl, and BFM's, hdl. Use of +// structs are more efficient and simpler to modify. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_struct +// and from_struct methods defined in the macros below that are used in +// the fuse_ctrl_core_axi_write_in_configuration class. +// + `define fuse_ctrl_core_axi_write_in_CONFIGURATION_STRUCT \ +typedef struct packed { \ + uvmf_active_passive_t active_passive; \ + uvmf_initiator_responder_t initiator_responder; \ + } fuse_ctrl_core_axi_write_in_configuration_s; + + `define fuse_ctrl_core_axi_write_in_CONFIGURATION_TO_STRUCT_FUNCTION \ + virtual function fuse_ctrl_core_axi_write_in_configuration_s to_struct();\ + fuse_ctrl_core_axi_write_in_configuration_struct = \ + {\ + this.active_passive,\ + this.initiator_responder\ + };\ + return ( fuse_ctrl_core_axi_write_in_configuration_struct );\ + endfunction + + `define fuse_ctrl_core_axi_write_in_CONFIGURATION_FROM_STRUCT_FUNCTION \ + virtual function void from_struct(fuse_ctrl_core_axi_write_in_configuration_s fuse_ctrl_core_axi_write_in_configuration_struct);\ + {\ + this.active_passive,\ + this.initiator_responder \ + } = fuse_ctrl_core_axi_write_in_configuration_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_monitor_struct +// and from_monitor_struct methods of the fuse_ctrl_core_axi_write_in_transaction class. +// + `define fuse_ctrl_core_axi_write_in_MONITOR_STRUCT typedef struct packed { \ + logic [AW-1:0] core_awaddr ; \ + logic core_awvalid ; \ + logic [$bits(axi_pkg::axi_burst_e)] core_awburst ; \ + logic [2:0] core_awsize ; \ + logic [7:0] core_awlen ; \ + logic [UW-1:0] core_awuser ; \ + logic [IW-1:0] core_awid ; \ + logic core_awlock ; \ + logic [DW-1:0] core_wdata ; \ + logic [DW/8 - 1:0] core_wstrb ; \ + logic core_wvalid ; \ + logic core_wlast ; \ + logic core_bready ; \ + } fuse_ctrl_core_axi_write_in_monitor_s; + + `define fuse_ctrl_core_axi_write_in_TO_MONITOR_STRUCT_FUNCTION \ + virtual function fuse_ctrl_core_axi_write_in_monitor_s to_monitor_struct();\ + fuse_ctrl_core_axi_write_in_monitor_struct = \ + { \ + this.core_awaddr , \ + this.core_awvalid , \ + this.core_awburst , \ + this.core_awsize , \ + this.core_awlen , \ + this.core_awuser , \ + this.core_awid , \ + this.core_awlock , \ + this.core_wdata , \ + this.core_wstrb , \ + this.core_wvalid , \ + this.core_wlast , \ + this.core_bready \ + };\ + return ( fuse_ctrl_core_axi_write_in_monitor_struct);\ + endfunction\ + + `define fuse_ctrl_core_axi_write_in_FROM_MONITOR_STRUCT_FUNCTION \ + virtual function void from_monitor_struct(fuse_ctrl_core_axi_write_in_monitor_s fuse_ctrl_core_axi_write_in_monitor_struct);\ + {\ + this.core_awaddr , \ + this.core_awvalid , \ + this.core_awburst , \ + this.core_awsize , \ + this.core_awlen , \ + this.core_awuser , \ + this.core_awid , \ + this.core_awlock , \ + this.core_wdata , \ + this.core_wstrb , \ + this.core_wvalid , \ + this.core_wlast , \ + this.core_bready \ + } = fuse_ctrl_core_axi_write_in_monitor_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_initiator_struct +// and from_initiator_struct methods of the fuse_ctrl_core_axi_write_in_transaction class. +// Also update the comments in the driver BFM. +// + `define fuse_ctrl_core_axi_write_in_INITIATOR_STRUCT typedef struct packed { \ + logic [AW-1:0] core_awaddr ; \ + logic core_awvalid ; \ + logic [$bits(axi_pkg::axi_burst_e)] core_awburst ; \ + logic [2:0] core_awsize ; \ + logic [7:0] core_awlen ; \ + logic [UW-1:0] core_awuser ; \ + logic [IW-1:0] core_awid ; \ + logic core_awlock ; \ + logic [DW-1:0] core_wdata ; \ + logic [DW/8 - 1:0] core_wstrb ; \ + logic core_wvalid ; \ + logic core_wlast ; \ + logic core_bready ; \ + } fuse_ctrl_core_axi_write_in_initiator_s; + + `define fuse_ctrl_core_axi_write_in_TO_INITIATOR_STRUCT_FUNCTION \ + virtual function fuse_ctrl_core_axi_write_in_initiator_s to_initiator_struct();\ + fuse_ctrl_core_axi_write_in_initiator_struct = \ + {\ + this.core_awaddr , \ + this.core_awvalid , \ + this.core_awburst , \ + this.core_awsize , \ + this.core_awlen , \ + this.core_awuser , \ + this.core_awid , \ + this.core_awlock , \ + this.core_wdata , \ + this.core_wstrb , \ + this.core_wvalid , \ + this.core_wlast , \ + this.core_bready \ + };\ + return ( fuse_ctrl_core_axi_write_in_initiator_struct);\ + endfunction + + `define fuse_ctrl_core_axi_write_in_FROM_INITIATOR_STRUCT_FUNCTION \ + virtual function void from_initiator_struct(fuse_ctrl_core_axi_write_in_initiator_s fuse_ctrl_core_axi_write_in_initiator_struct);\ + {\ + this.core_awaddr , \ + this.core_awvalid , \ + this.core_awburst , \ + this.core_awsize , \ + this.core_awlen , \ + this.core_awuser , \ + this.core_awid , \ + this.core_awlock , \ + this.core_wdata , \ + this.core_wstrb , \ + this.core_wvalid , \ + this.core_wlast , \ + this.core_bready \ + } = fuse_ctrl_core_axi_write_in_initiator_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_responder_struct +// and from_responder_struct methods of the fuse_ctrl_core_axi_write_in_transaction class. +// Also update the comments in the driver BFM. +// + `define fuse_ctrl_core_axi_write_in_RESPONDER_STRUCT typedef struct packed { \ + logic [AW-1:0] core_awaddr ; \ + logic core_awvalid ; \ + logic [$bits(axi_pkg::axi_burst_e)] core_awburst ; \ + logic [2:0] core_awsize ; \ + logic [7:0] core_awlen ; \ + logic [UW-1:0] core_awuser ; \ + logic [IW-1:0] core_awid ; \ + logic core_awlock ; \ + logic [DW-1:0] core_wdata ; \ + logic [DW/8 - 1:0] core_wstrb ; \ + logic core_wvalid ; \ + logic core_wlast ; \ + logic core_bready ; \ + } fuse_ctrl_core_axi_write_in_responder_s; + + `define fuse_ctrl_core_axi_write_in_TO_RESPONDER_STRUCT_FUNCTION \ + virtual function fuse_ctrl_core_axi_write_in_responder_s to_responder_struct();\ + fuse_ctrl_core_axi_write_in_responder_struct = \ + {\ + this.core_awaddr , \ + this.core_awvalid , \ + this.core_awburst , \ + this.core_awsize , \ + this.core_awlen , \ + this.core_awuser , \ + this.core_awid , \ + this.core_awlock , \ + this.core_wdata , \ + this.core_wstrb , \ + this.core_wvalid , \ + this.core_wlast , \ + this.core_bready \ + };\ + return ( fuse_ctrl_core_axi_write_in_responder_struct);\ + endfunction + + `define fuse_ctrl_core_axi_write_in_FROM_RESPONDER_STRUCT_FUNCTION \ + virtual function void from_responder_struct(fuse_ctrl_core_axi_write_in_responder_s fuse_ctrl_core_axi_write_in_responder_struct);\ + {\ + this.core_awaddr , \ + this.core_awvalid , \ + this.core_awburst , \ + this.core_awsize , \ + this.core_awlen , \ + this.core_awuser , \ + this.core_awid , \ + this.core_awlock , \ + this.core_wdata , \ + this.core_wstrb , \ + this.core_wvalid , \ + this.core_wlast , \ + this.core_bready \ + } = fuse_ctrl_core_axi_write_in_responder_struct;\ + endfunction +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_monitor.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_monitor.svh new file mode 100644 index 0000000..b175878 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_monitor.svh @@ -0,0 +1,131 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class receives fuse_ctrl_core_axi_write_in transactions observed by the +// fuse_ctrl_core_axi_write_in monitor BFM and broadcasts them through the analysis port +// on the agent. It accesses the monitor BFM through the monitor +// task. This UVM component captures transactions +// for viewing in the waveform viewer if the +// enable_transaction_viewing flag is set in the configuration. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_write_in_monitor #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvmf_monitor_base #( + .CONFIG_T(fuse_ctrl_core_axi_write_in_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .BFM_BIND_T(virtual fuse_ctrl_core_axi_write_in_monitor_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .TRANS_T(fuse_ctrl_core_axi_write_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +)); + + `uvm_component_param_utils( fuse_ctrl_core_axi_write_in_monitor #( + AW, + DW, + IW, + UW + ) +) + +// Structure used to pass data from monitor BFM to monitor class in agent. +// Use to_monitor_struct function to pack transaction variables into structure. +// Use from_monitor_struct function to unpack transaction variables from structure. +`fuse_ctrl_core_axi_write_in_MONITOR_STRUCT + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the monitor BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// monitor BFM. This allows the monitor BFM to call the notify_transaction +// function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// *************************************************************************** + virtual task run_phase(uvm_phase phase); + // Start monitor BFM thread and don't call super.run() in order to + // override the default monitor proxy 'pull' behavior with the more + // emulation-friendly BFM 'push' approach using the notify_transaction + // function below + bfm.start_monitoring(); + endtask + +// ************************************************************************** + +// This function is called by the monitor BFM. It receives data observed by the +// monitor BFM. Data is passed using the fuse_ctrl_core_axi_write_in_monitor_struct. + virtual function void notify_transaction(input fuse_ctrl_core_axi_write_in_monitor_s fuse_ctrl_core_axi_write_in_monitor_struct); + + + trans = new("trans"); + trans.from_monitor_struct(fuse_ctrl_core_axi_write_in_monitor_struct); + trans.start_time = time_stamp; + trans.end_time = $time; + time_stamp = trans.end_time; + + analyze(trans); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_monitor_bfm.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_monitor_bfm.sv new file mode 100644 index 0000000..f251321 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_monitor_bfm.sv @@ -0,0 +1,248 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface performs the fuse_ctrl_core_axi_write_in signal monitoring. +// It is accessed by the uvm fuse_ctrl_core_axi_write_in monitor through a virtual +// interface handle in the fuse_ctrl_core_axi_write_in configuration. It monitors the +// signals passed in through the port connection named bus of +// type fuse_ctrl_core_axi_write_in_if. +// +// Input signals from the fuse_ctrl_core_axi_write_in_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// Interface functions and tasks used by UVM components: +// monitor(inout TRANS_T txn); +// This task receives the transaction, txn, from the +// UVM monitor and then populates variables in txn +// from values observed on bus activity. This task +// blocks until an operation on the fuse_ctrl_core_axi_write_in bus is complete. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_core_axi_write_in_pkg_hdl::*; +`include "src/fuse_ctrl_core_axi_write_in_macros.svh" + + +interface fuse_ctrl_core_axi_write_in_monitor_bfm #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + + ( fuse_ctrl_core_axi_write_in_if bus ); + // The pragma below and additional ones in-lined further down are for running this BFM on Veloce + // pragma attribute fuse_ctrl_core_axi_write_in_monitor_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: AW=%x DW=%x IW=%x UW=%x ", AW,DW,IW,UW), + UVM_DEBUG) +end +`endif + + + // Structure used to pass transaction data from monitor BFM to monitor class in agent. +`fuse_ctrl_core_axi_write_in_MONITOR_STRUCT + fuse_ctrl_core_axi_write_in_monitor_s fuse_ctrl_core_axi_write_in_monitor_struct; + + // Structure used to pass configuration data from monitor class to monitor BFM. + `fuse_ctrl_core_axi_write_in_CONFIGURATION_STRUCT + + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + tri clk_i_i; + tri rst_ni_i; + tri [AW-1:0] awaddr_i; + tri [$bits(axi_pkg::axi_burst_e)-1:0] awburst_i; + tri [2:0] awsize_i; + tri [7:0] awlen_i; + tri [UW-1:0] awuser_i; + tri [UW-1:0] awid_i; + tri awlock_i; + tri awvalid_i; + tri [DW-1:0] wdata_i; + tri [DW/8-1:0] wstrb_i; + tri wvalid_i; + tri wlast_i; + tri bready_i; + assign clk_i_i = bus.clk_i; + assign rst_ni_i = bus.rst_ni; + assign awaddr_i = bus.awaddr; + assign awburst_i = bus.awburst; + assign awsize_i = bus.awsize; + assign awlen_i = bus.awlen; + assign awuser_i = bus.awuser; + assign awid_i = bus.awid; + assign awlock_i = bus.awlock; + assign awvalid_i = bus.awvalid; + assign wdata_i = bus.wdata; + assign wstrb_i = bus.wstrb; + assign wvalid_i = bus.wvalid; + assign wlast_i = bus.wlast; + assign bready_i = bus.bready; + + // Proxy handle to UVM monitor + fuse_ctrl_core_axi_write_in_pkg::fuse_ctrl_core_axi_write_in_monitor #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + proxy; + // pragma tbx oneway proxy.notify_transaction + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + task wait_for_reset();// pragma tbx xtf + @(posedge clk_i_i) ; + do_wait_for_reset(); + endtask + + // **************************************************************************** + task do_wait_for_reset(); + // pragma uvmf custom reset_condition begin + wait ( rst_ni_i === 1 ) ; + @(posedge clk_i_i) ; + // pragma uvmf custom reset_condition end + endtask + + //****************************************************************** + + task wait_for_num_clocks(input int unsigned count); // pragma tbx xtf + @(posedge clk_i_i); + + repeat (count-1) @(posedge clk_i_i); + endtask + + //****************************************************************** + event go; + function void start_monitoring();// pragma tbx xtf + -> go; + endfunction + + // **************************************************************************** + initial begin + @go; + forever begin + @(posedge clk_i_i); + do_monitor( fuse_ctrl_core_axi_write_in_monitor_struct ); + + + proxy.notify_transaction( fuse_ctrl_core_axi_write_in_monitor_struct ); + + end + end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the monitor BFM. It is called by the monitor within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the monitor BFM needs to be aware of the new configuration + // variables. + // + function void configure(fuse_ctrl_core_axi_write_in_configuration_s fuse_ctrl_core_axi_write_in_configuration_arg); // pragma tbx xtf + initiator_responder = fuse_ctrl_core_axi_write_in_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + + + // **************************************************************************** + + task do_monitor(output fuse_ctrl_core_axi_write_in_monitor_s fuse_ctrl_core_axi_write_in_monitor_struct); + // + // Available struct members: + // // fuse_ctrl_core_axi_write_in_monitor_struct.core_awaddr + // // fuse_ctrl_core_axi_write_in_monitor_struct.core_awvalid + // // fuse_ctrl_core_axi_write_in_monitor_struct.core_awburst + // // fuse_ctrl_core_axi_write_in_monitor_struct.core_awsize + // // fuse_ctrl_core_axi_write_in_monitor_struct.core_awlen + // // fuse_ctrl_core_axi_write_in_monitor_struct.core_awuser + // // fuse_ctrl_core_axi_write_in_monitor_struct.core_awid + // // fuse_ctrl_core_axi_write_in_monitor_struct.core_awlock + // // fuse_ctrl_core_axi_write_in_monitor_struct.core_wdata + // // fuse_ctrl_core_axi_write_in_monitor_struct.core_wstrb + // // fuse_ctrl_core_axi_write_in_monitor_struct.core_wvalid + // // fuse_ctrl_core_axi_write_in_monitor_struct.core_wlast + // // fuse_ctrl_core_axi_write_in_monitor_struct.core_bready + // // + // Reference code; + // How to wait for signal value + // while (control_signal === 1'b1) @(posedge clk_i_i); + // + // How to assign a struct member, named xyz, from a signal. + // All available input signals listed. + // fuse_ctrl_core_axi_write_in_monitor_struct.xyz = awaddr_i; // [AW-1:0] + // fuse_ctrl_core_axi_write_in_monitor_struct.xyz = awburst_i; // [$bits(axi_pkg::axi_burst_e)-1:0] + // fuse_ctrl_core_axi_write_in_monitor_struct.xyz = awsize_i; // [2:0] + // fuse_ctrl_core_axi_write_in_monitor_struct.xyz = awlen_i; // [7:0] + // fuse_ctrl_core_axi_write_in_monitor_struct.xyz = awuser_i; // [UW-1:0] + // fuse_ctrl_core_axi_write_in_monitor_struct.xyz = awid_i; // [UW-1:0] + // fuse_ctrl_core_axi_write_in_monitor_struct.xyz = awlock_i; // + // fuse_ctrl_core_axi_write_in_monitor_struct.xyz = awvalid_i; // + // fuse_ctrl_core_axi_write_in_monitor_struct.xyz = wdata_i; // [DW-1:0] + // fuse_ctrl_core_axi_write_in_monitor_struct.xyz = wstrb_i; // [DW/8-1:0] + // fuse_ctrl_core_axi_write_in_monitor_struct.xyz = wvalid_i; // + // fuse_ctrl_core_axi_write_in_monitor_struct.xyz = wlast_i; // + // fuse_ctrl_core_axi_write_in_monitor_struct.xyz = bready_i; // + // pragma uvmf custom do_monitor begin + // UVMF_CHANGE_ME : Implement protocol monitoring. The commented reference code + // below are examples of how to capture signal values and assign them to + // structure members. All available input signals are listed. The 'while' + // code example shows how to wait for a synchronous flow control signal. This + // task should return when a complete transfer has been observed. Once this task is + // exited with captured values, it is then called again to wait for and observe + // the next transfer. One clock cycle is consumed between calls to do_monitor. + @(posedge clk_i_i); + @(posedge clk_i_i); + @(posedge clk_i_i); + @(posedge clk_i_i); + // pragma uvmf custom do_monitor end + endtask + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_random_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_random_sequence.svh new file mode 100644 index 0000000..fd2c3c9 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_random_sequence.svh @@ -0,0 +1,91 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This sequences randomizes the fuse_ctrl_core_axi_write_in transaction and sends it +// to the UVM driver. +// +// This sequence constructs and randomizes a fuse_ctrl_core_axi_write_in_transaction. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_write_in_random_sequence #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + + extends fuse_ctrl_core_axi_write_in_sequence_base #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +; + + `uvm_object_param_utils( fuse_ctrl_core_axi_write_in_random_sequence #( + AW, + DW, + IW, + UW + ) +) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //***************************************************************** + function new(string name = ""); + super.new(name); + endfunction: new + + // **************************************************************************** + // TASK : body() + // This task is automatically executed when this sequence is started using the + // start(sequencerHandle) task. + // + task body(); + + // Construct the transaction + req=fuse_ctrl_core_axi_write_in_transaction#( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +::type_id::create("req"); + start_item(req); + // Randomize the transaction + if(!req.randomize()) `uvm_fatal("SEQ", "fuse_ctrl_core_axi_write_in_random_sequence::body()-fuse_ctrl_core_axi_write_in_transaction randomization failed") + // Send the transaction to the fuse_ctrl_core_axi_write_in_driver_bfm via the sequencer and fuse_ctrl_core_axi_write_in_driver. + finish_item(req); + `uvm_info("SEQ", {"Response:",req.convert2string()},UVM_MEDIUM) + + endtask + +endclass: fuse_ctrl_core_axi_write_in_random_sequence + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_responder_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_responder_sequence.svh new file mode 100644 index 0000000..6305f4d --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_responder_sequence.svh @@ -0,0 +1,87 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class can be used to provide stimulus when an interface +// has been configured to run in a responder mode. It +// will never finish by default, always going back to the driver +// and driver BFM for the next transaction with which to respond. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_write_in_responder_sequence #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + + extends fuse_ctrl_core_axi_write_in_sequence_base #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +; + + `uvm_object_param_utils( fuse_ctrl_core_axi_write_in_responder_sequence #( + AW, + DW, + IW, + UW + ) +) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "fuse_ctrl_core_axi_write_in_responder_sequence"); + super.new(name); + endfunction + + task body(); + req=fuse_ctrl_core_axi_write_in_transaction#( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +::type_id::create("req"); + forever begin + start_item(req); + finish_item(req); + // pragma uvmf custom body begin + // UVMF_CHANGE_ME : Do something here with the resulting req item. The + // finish_item() call above will block until the req transaction is ready + // to be handled by the responder sequence. + // If this was an item that required a response, the expectation is + // that the response should be populated within this transaction now. + `uvm_info("SEQ",$sformatf("Processed txn: %s",req.convert2string()),UVM_HIGH) + // pragma uvmf custom body end + end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_sequence_base.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_sequence_base.svh new file mode 100644 index 0000000..69be976 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_sequence_base.svh @@ -0,0 +1,146 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the class used as the base class for all sequences +// for this interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_write_in_sequence_base #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvmf_sequence_base #( + .REQ(fuse_ctrl_core_axi_write_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .RSP(fuse_ctrl_core_axi_write_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +)); + + `uvm_object_param_utils( fuse_ctrl_core_axi_write_in_sequence_base #( + AW, + DW, + IW, + UW + ) +) + + // variables + typedef fuse_ctrl_core_axi_write_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + fuse_ctrl_core_axi_write_in_transaction_req_t; + fuse_ctrl_core_axi_write_in_transaction_req_t req; + typedef fuse_ctrl_core_axi_write_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + fuse_ctrl_core_axi_write_in_transaction_rsp_t; + fuse_ctrl_core_axi_write_in_transaction_rsp_t rsp; + + // Event for identifying when a response was received from the sequencer + event new_rsp; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // TASK : get_responses() + // This task recursively gets sequence item responses from the sequencer. + // + virtual task get_responses(); + fork + begin + // Block until new rsp available + get_response(rsp); + // New rsp received. Indicate to sequence using event. + ->new_rsp; + // Display the received response transaction + `uvm_info("SEQ", {"New response transaction:",rsp.convert2string()}, UVM_MEDIUM) + end + join_none + endtask + + // **************************************************************************** + // TASK : pre_body() + // This task is called automatically when start is called with call_pre_post set to 1 (default). + // By calling get_responses() within pre_body() any derived sequences are automatically + // processing response transactions. Only un-comment this call to get_responses() if you + // have configured the interface driver to utilize the response transaction path by setting + // the configuration variable "return_transaction_response" to 1. Otherwise it is possible + // to impact runtime performance and memory utilization. + // + virtual task pre_body(); + // pragma uvmf custom pre_body begin +// get_responses(); + // pragma uvmf custom pre_body end + endtask + + // **************************************************************************** + // TASK : body() + // This task is called automatically when start is called. This sequence sends + // a req sequence item to the sequencer identified as an argument in the call + // to start. + // + virtual task body(); + // pragma uvmf custom body begin + start_item(req); + finish_item(req); + // pragma uvmf custom body end + endtask + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name =""); + super.new( name ); + // pragma uvmf custom new begin + req = fuse_ctrl_core_axi_write_in_transaction_req_t::type_id::create("req"); + rsp = fuse_ctrl_core_axi_write_in_transaction_rsp_t::type_id::create("rsp"); + // pragma uvmf custom new end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_transaction.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_transaction.svh new file mode 100644 index 0000000..08595f6 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_transaction.svh @@ -0,0 +1,256 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class defines the variables required for an fuse_ctrl_core_axi_write_in +// transaction. Class variables to be displayed in waveform transaction +// viewing are added to the transaction viewing stream in the add_to_wave +// function. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_write_in_transaction #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvmf_transaction_base; + + `uvm_object_param_utils( fuse_ctrl_core_axi_write_in_transaction #( + AW, + DW, + IW, + UW + ) +) + + rand logic [AW-1:0] core_awaddr ; + logic core_awvalid ; + logic [$bits(axi_pkg::axi_burst_e)] core_awburst ; + logic [2:0] core_awsize ; + logic [7:0] core_awlen ; + logic [UW-1:0] core_awuser ; + logic [IW-1:0] core_awid ; + logic core_awlock ; + logic [DW-1:0] core_wdata ; + logic [DW/8 - 1:0] core_wstrb ; + logic core_wvalid ; + logic core_wlast ; + logic core_bready ; + + //Constraints for the transaction variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //******************************************************************* + //******************************************************************* + // Macros that define structs and associated functions are + // located in fuse_ctrl_core_axi_write_in_macros.svh + + //******************************************************************* + // Monitor macro used by fuse_ctrl_core_axi_write_in_monitor and fuse_ctrl_core_axi_write_in_monitor_bfm + // This struct is defined in fuse_ctrl_core_axi_write_in_macros.svh + `fuse_ctrl_core_axi_write_in_MONITOR_STRUCT + fuse_ctrl_core_axi_write_in_monitor_s fuse_ctrl_core_axi_write_in_monitor_struct; + //******************************************************************* + // FUNCTION: to_monitor_struct() + // This function packs transaction variables into a fuse_ctrl_core_axi_write_in_monitor_s + // structure. The function returns the handle to the fuse_ctrl_core_axi_write_in_monitor_struct. + // This function is defined in fuse_ctrl_core_axi_write_in_macros.svh + `fuse_ctrl_core_axi_write_in_TO_MONITOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_monitor_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_core_axi_write_in_macros.svh + `fuse_ctrl_core_axi_write_in_FROM_MONITOR_STRUCT_FUNCTION + + //******************************************************************* + // Initiator macro used by fuse_ctrl_core_axi_write_in_driver and fuse_ctrl_core_axi_write_in_driver_bfm + // to communicate initiator driven data to fuse_ctrl_core_axi_write_in_driver_bfm. + // This struct is defined in fuse_ctrl_core_axi_write_in_macros.svh + `fuse_ctrl_core_axi_write_in_INITIATOR_STRUCT + fuse_ctrl_core_axi_write_in_initiator_s fuse_ctrl_core_axi_write_in_initiator_struct; + //******************************************************************* + // FUNCTION: to_initiator_struct() + // This function packs transaction variables into a fuse_ctrl_core_axi_write_in_initiator_s + // structure. The function returns the handle to the fuse_ctrl_core_axi_write_in_initiator_struct. + // This function is defined in fuse_ctrl_core_axi_write_in_macros.svh + `fuse_ctrl_core_axi_write_in_TO_INITIATOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_initiator_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_core_axi_write_in_macros.svh + `fuse_ctrl_core_axi_write_in_FROM_INITIATOR_STRUCT_FUNCTION + + //******************************************************************* + // Responder macro used by fuse_ctrl_core_axi_write_in_driver and fuse_ctrl_core_axi_write_in_driver_bfm + // to communicate Responder driven data to fuse_ctrl_core_axi_write_in_driver_bfm. + // This struct is defined in fuse_ctrl_core_axi_write_in_macros.svh + `fuse_ctrl_core_axi_write_in_RESPONDER_STRUCT + fuse_ctrl_core_axi_write_in_responder_s fuse_ctrl_core_axi_write_in_responder_struct; + //******************************************************************* + // FUNCTION: to_responder_struct() + // This function packs transaction variables into a fuse_ctrl_core_axi_write_in_responder_s + // structure. The function returns the handle to the fuse_ctrl_core_axi_write_in_responder_struct. + // This function is defined in fuse_ctrl_core_axi_write_in_macros.svh + `fuse_ctrl_core_axi_write_in_TO_RESPONDER_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_responder_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_core_axi_write_in_macros.svh + `fuse_ctrl_core_axi_write_in_FROM_RESPONDER_STRUCT_FUNCTION + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + endfunction + + // **************************************************************************** + // FUNCTION: convert2string() + // This function converts all variables in this class to a single string for + // logfile reporting. + // + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + // UVMF_CHANGE_ME : Customize format if desired. + return $sformatf("core_awaddr:0x%x core_awvalid:0x%x core_awburst:0x%x core_awsize:0x%x core_awlen:0x%x core_awuser:0x%x core_awid:0x%x core_awlock:0x%x core_wdata:0x%x core_wstrb:0x%x core_wvalid:0x%x core_wlast:0x%x core_bready:0x%x ",core_awaddr,core_awvalid,core_awburst,core_awsize,core_awlen,core_awuser,core_awid,core_awlock,core_wdata,core_wstrb,core_wvalid,core_wlast,core_bready); + // pragma uvmf custom convert2string end + endfunction + + //******************************************************************* + // FUNCTION: do_print() + // This function is automatically called when the .print() function + // is called on this class. + // + virtual function void do_print(uvm_printer printer); + // pragma uvmf custom do_print begin + // UVMF_CHANGE_ME : Current contents of do_print allows for the use of UVM 1.1d, 1.2 or P1800.2. + // Update based on your own printing preference according to your preferred UVM version + $display(convert2string()); + // pragma uvmf custom do_print end + endfunction + + //******************************************************************* + // FUNCTION: do_compare() + // This function is automatically called when the .compare() function + // is called on this class. + // + virtual function bit do_compare (uvm_object rhs, uvm_comparer comparer); + fuse_ctrl_core_axi_write_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + RHS; + if (!$cast(RHS,rhs)) return 0; + // pragma uvmf custom do_compare begin + // UVMF_CHANGE_ME : Eliminate comparison of variables not to be used for compare + return (super.do_compare(rhs,comparer) + &&(this.core_wdata == RHS.core_wdata) + ); + // pragma uvmf custom do_compare end + endfunction + + //******************************************************************* + // FUNCTION: do_copy() + // This function is automatically called when the .copy() function + // is called on this class. + // + virtual function void do_copy (uvm_object rhs); + fuse_ctrl_core_axi_write_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + RHS; + assert($cast(RHS,rhs)); + // pragma uvmf custom do_copy begin + super.do_copy(rhs); + this.core_awaddr = RHS.core_awaddr; + this.core_awvalid = RHS.core_awvalid; + this.core_awburst = RHS.core_awburst; + this.core_awsize = RHS.core_awsize; + this.core_awlen = RHS.core_awlen; + this.core_awuser = RHS.core_awuser; + this.core_awid = RHS.core_awid; + this.core_awlock = RHS.core_awlock; + this.core_wdata = RHS.core_wdata; + this.core_wstrb = RHS.core_wstrb; + this.core_wvalid = RHS.core_wvalid; + this.core_wlast = RHS.core_wlast; + this.core_bready = RHS.core_bready; + // pragma uvmf custom do_copy end + endfunction + + // **************************************************************************** + // FUNCTION: add_to_wave() + // This function is used to display variables in this class in the waveform + // viewer. The start_time and end_time variables must be set before this + // function is called. If the start_time and end_time variables are not set + // the transaction will be hidden at 0ns on the waveform display. + // + virtual function void add_to_wave(int transaction_viewing_stream_h); + `ifdef QUESTA + if (transaction_view_h == 0) begin + transaction_view_h = $begin_transaction(transaction_viewing_stream_h,"fuse_ctrl_core_axi_write_in_transaction",start_time); + end + super.add_to_wave(transaction_view_h); + // pragma uvmf custom add_to_wave begin + // UVMF_CHANGE_ME : Color can be applied to transaction entries based on content, example below + // case() + // 1 : $add_color(transaction_view_h,"red"); + // default : $add_color(transaction_view_h,"grey"); + // endcase + // UVMF_CHANGE_ME : Eliminate transaction variables not wanted in transaction viewing in the waveform viewer + $add_attribute(transaction_view_h,core_awaddr,"core_awaddr"); + $add_attribute(transaction_view_h,core_awvalid,"core_awvalid"); + $add_attribute(transaction_view_h,core_awburst,"core_awburst"); + $add_attribute(transaction_view_h,core_awsize,"core_awsize"); + $add_attribute(transaction_view_h,core_awlen,"core_awlen"); + $add_attribute(transaction_view_h,core_awuser,"core_awuser"); + $add_attribute(transaction_view_h,core_awid,"core_awid"); + $add_attribute(transaction_view_h,core_awlock,"core_awlock"); + $add_attribute(transaction_view_h,core_wdata,"core_wdata"); + $add_attribute(transaction_view_h,core_wstrb,"core_wstrb"); + $add_attribute(transaction_view_h,core_wvalid,"core_wvalid"); + $add_attribute(transaction_view_h,core_wlast,"core_wlast"); + $add_attribute(transaction_view_h,core_bready,"core_bready"); + // pragma uvmf custom add_to_wave end + $end_transaction(transaction_view_h,end_time); + $free_transaction(transaction_view_h); + `endif // QUESTA + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_transaction_coverage.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_transaction_coverage.svh new file mode 100644 index 0000000..8fd4174 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_transaction_coverage.svh @@ -0,0 +1,114 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class records fuse_ctrl_core_axi_write_in transaction information using +// a covergroup named fuse_ctrl_core_axi_write_in_transaction_cg. An instance of this +// coverage component is instantiated in the uvmf_parameterized_agent +// if the has_coverage flag is set. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_write_in_transaction_coverage #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvm_subscriber #(.T(fuse_ctrl_core_axi_write_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +)); + + `uvm_component_param_utils( fuse_ctrl_core_axi_write_in_transaction_coverage #( + AW, + DW, + IW, + UW + ) +) + + T coverage_trans; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + covergroup fuse_ctrl_core_axi_write_in_transaction_cg; + // pragma uvmf custom covergroup begin + // UVMF_CHANGE_ME : Add coverage bins, crosses, exclusions, etc. according to coverage needs. + option.auto_bin_max=1024; + option.per_instance=1; + core_awaddr: coverpoint coverage_trans.core_awaddr; + core_awvalid: coverpoint coverage_trans.core_awvalid; + core_awburst: coverpoint coverage_trans.core_awburst; + core_awsize: coverpoint coverage_trans.core_awsize; + core_awlen: coverpoint coverage_trans.core_awlen; + core_awuser: coverpoint coverage_trans.core_awuser; + core_awid: coverpoint coverage_trans.core_awid; + core_awlock: coverpoint coverage_trans.core_awlock; + core_wdata: coverpoint coverage_trans.core_wdata; + core_wstrb: coverpoint coverage_trans.core_wstrb; + core_wvalid: coverpoint coverage_trans.core_wvalid; + core_wlast: coverpoint coverage_trans.core_wlast; + core_bready: coverpoint coverage_trans.core_bready; + // pragma uvmf custom covergroup end + endgroup + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new(string name="", uvm_component parent=null); + super.new(name,parent); + fuse_ctrl_core_axi_write_in_transaction_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that transaction variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + endfunction + + // **************************************************************************** + // FUNCTION : build_phase() + // This function is the standard UVM build_phase. + // + function void build_phase(uvm_phase phase); + fuse_ctrl_core_axi_write_in_transaction_cg.set_inst_name($sformatf("fuse_ctrl_core_axi_write_in_transaction_cg_%s",get_full_name())); + endfunction + + // **************************************************************************** + // FUNCTION: write (T t) + // This function is automatically executed when a transaction arrives on the + // analysis_export. It copies values from the variables in the transaction + // to local variables used to collect functional coverage. + // + virtual function void write (T t); + `uvm_info("COV","Received transaction",UVM_HIGH); + coverage_trans = t; + fuse_ctrl_core_axi_write_in_transaction_cg.sample(); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_typedefs.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_typedefs.svh new file mode 100644 index 0000000..f2a7bdb --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_typedefs.svh @@ -0,0 +1,34 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the host server when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_typedefs_hdl.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_typedefs_hdl.svh new file mode 100644 index 0000000..0d58518 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/src/fuse_ctrl_core_axi_write_in_typedefs_hdl.svh @@ -0,0 +1,35 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the emulator when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/yaml/fuse_ctrl_core_axi_write_in_interface.yaml b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/yaml/fuse_ctrl_core_axi_write_in_interface.yaml new file mode 100644 index 0000000..9882e7c --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_in_pkg/yaml/fuse_ctrl_core_axi_write_in_interface.yaml @@ -0,0 +1,161 @@ +uvmf: + interfaces: + fuse_ctrl_core_axi_write_in: + clock: clk_i + config_constraints: [] + config_vars: [] + existing_library_component: 'True' + gen_inbound_streaming_driver: 'False' + hdl_pkg_parameters: [] + hdl_typedefs: [] + hvl_pkg_parameters: [] + hvl_typedefs: [] + parameters: + - name: AW + type: int + value: '32' + - name: DW + type: int + value: '32' + - name: IW + type: int + value: '3' + - name: UW + type: int + value: '32' + ports: + - dir: output + name: awaddr + reset_value: '''bz' + width: '[''AW'']' + - dir: output + name: awburst + reset_value: '''bz' + width: '[''$bits(axi_pkg::axi_burst_e)'']' + - dir: output + name: awsize + reset_value: '''bz' + width: '3' + - dir: output + name: awlen + reset_value: '''bz' + width: '8' + - dir: output + name: awuser + reset_value: '''bz' + width: '[''UW'']' + - dir: output + name: awid + reset_value: '''bz' + width: '[''UW'']' + - dir: output + name: awlock + reset_value: '''bz' + width: '1' + - dir: output + name: awvalid + reset_value: '''bz' + width: '1' + - dir: output + name: wdata + reset_value: '''bz' + width: '[''DW'']' + - dir: output + name: wstrb + reset_value: '''bz' + width: '[''DW/8'']' + - dir: output + name: wvalid + reset_value: '''bz' + width: '1' + - dir: output + name: wlast + reset_value: '''bz' + width: '1' + - dir: output + name: bready + reset_value: '''bz' + width: '1' + reset: rst_ni + reset_assertion_level: 'False' + transaction_constraints: [] + transaction_vars: + - comment: '' + iscompare: 'False' + isrand: 'True' + name: core_awaddr + type: logic [AW-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: core_awvalid + type: logic + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: core_awburst + type: logic [$bits(axi_pkg::axi_burst_e)] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: core_awsize + type: logic [2:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: core_awlen + type: logic [7:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: core_awuser + type: logic [UW-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: core_awid + type: logic [IW-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: core_awlock + type: logic + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'False' + name: core_wdata + type: logic [DW-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: core_wstrb + type: logic [DW/8 - 1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: core_wvalid + type: logic + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: core_wlast + type: logic + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: core_bready + type: logic + unpacked_dimension: '' + use_dpi_link: 'False' diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/.project b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/.project new file mode 100644 index 0000000..673a410 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/.project @@ -0,0 +1,30 @@ + + + fuse_ctrl_core_axi_write_out_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/.svproject b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/.svproject new file mode 100644 index 0000000..e0ccd60 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/Makefile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/Makefile new file mode 100644 index 0000000..b885f66 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/Makefile @@ -0,0 +1,66 @@ +# fuse_ctrl_core_axi_write_out interface packages source +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +fuse_ctrl_core_axi_write_out_PKG = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_write_out_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_filelist_hvl.f + +fuse_ctrl_core_axi_write_out_PKG_HDL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_write_out_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_filelist_hdl.f + +fuse_ctrl_core_axi_write_out_PKG_XRTL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_write_out_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_filelist_xrtl.f + +COMP_fuse_ctrl_core_axi_write_out_PKG_TGT_0 = q_comp_fuse_ctrl_core_axi_write_out_pkg +COMP_fuse_ctrl_core_axi_write_out_PKG_TGT_1 = v_comp_fuse_ctrl_core_axi_write_out_pkg +COMP_fuse_ctrl_core_axi_write_out_PKG_TGT = $(COMP_fuse_ctrl_core_axi_write_out_PKG_TGT_$(USE_VELOCE)) + +comp_fuse_ctrl_core_axi_write_out_pkg: $(COMP_fuse_ctrl_core_axi_write_out_PKG_TGT) + +q_comp_fuse_ctrl_core_axi_write_out_pkg: + $(HDL_COMP_CMD) $(fuse_ctrl_core_axi_write_out_PKG_HDL) + $(HVL_COMP_CMD) $(fuse_ctrl_core_axi_write_out_PKG) + $(HDL_COMP_CMD) $(fuse_ctrl_core_axi_write_out_PKG_XRTL) + +v_comp_fuse_ctrl_core_axi_write_out_pkg: + $(HVL_COMP_CMD) $(fuse_ctrl_core_axi_write_out_PKG_HDL) + $(HVL_COMP_CMD) $(fuse_ctrl_core_axi_write_out_PKG) + $(VELANALYZE_CMD) $(fuse_ctrl_core_axi_write_out_PKG_HDL) + $(VELANALYZE_HVL_CMD) $(fuse_ctrl_core_axi_write_out_PKG) + $(HDL_COMP_CMD) $(fuse_ctrl_core_axi_write_out_PKG_XRTL) + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export fuse_ctrl_core_axi_write_out_IF_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_write_out_pkg/dpi + +C_FILE_COMPILE_LIST_fuse_ctrl_core_axi_write_out_pkg = \ + +O_FILE_COMPILE_LIST_fuse_ctrl_core_axi_write_out_pkg = $(notdir $(C_FILE_COMPILE_LIST_fuse_ctrl_core_axi_write_out_pkg:.c=.o)) + +GCC_COMP_ARGS_fuse_ctrl_core_axi_write_out_pkg += -I$(fuse_ctrl_core_axi_write_out_IF_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_fuse_ctrl_core_axi_write_out_pkg += $(fuse_ctrl_core_axi_write_out_IF_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_fuse_ctrl_core_axi_write_out_pkg += \ + \ + -o .so + +comp_fuse_ctrl_core_axi_write_out_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Interface C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_fuse_ctrl_core_axi_write_out_pkg) $(C_FILE_COMPILE_LIST_fuse_ctrl_core_axi_write_out_pkg) + @echo "--------------------------------" + @echo "Linking Interface C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_fuse_ctrl_core_axi_write_out_pkg) $(O_FILE_COMPILE_LIST_fuse_ctrl_core_axi_write_out_pkg) + @echo "--------------------------------" + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/compile.do b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/compile.do new file mode 100644 index 0000000..dd7c8df --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/compile.do @@ -0,0 +1,14 @@ +# Tcl do file for compile of fuse_ctrl_core_axi_write_out interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_write_out_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_filelist_hdl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_write_out_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_filelist_hvl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_write_out_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_filelist_xrtl.f \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out.compile new file mode 100644 index 0000000..fc356ad --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out.compile @@ -0,0 +1,3 @@ +needs: + - fuse_ctrl_core_axi_write_out_hvl.compile + - fuse_ctrl_core_axi_write_out_hdl.compile diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_bfm.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_bfm.vinfo new file mode 100644 index 0000000..4acbc3d --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_bfm.vinfo @@ -0,0 +1,6 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use fuse_ctrl_core_axi_write_out_pkg_hdl.vinfo ++incdir+@vinfodir +src/fuse_ctrl_core_axi_write_out_if.sv +src/fuse_ctrl_core_axi_write_out_driver_bfm.sv +src/fuse_ctrl_core_axi_write_out_monitor_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_common.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_common.compile new file mode 100644 index 0000000..ab99fa6 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_common.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +incdir: + - . + - ${uvm_path}/src +src: + - fuse_ctrl_core_axi_write_out_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_filelist_hdl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_filelist_hdl.f new file mode 100644 index 0000000..354fe24 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_filelist_hdl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_filelist_hvl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_filelist_hvl.f new file mode 100644 index 0000000..d14e3d6 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_filelist_hvl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_pkg.sv \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_filelist_xrtl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_filelist_xrtl.f new file mode 100644 index 0000000..9aecc88 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_filelist_xrtl.f @@ -0,0 +1,3 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_if.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_monitor_bfm.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_driver_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_hdl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_hdl.compile new file mode 100644 index 0000000..d220bb8 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_hdl.compile @@ -0,0 +1,9 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ./fuse_ctrl_core_axi_write_out_common.compile +incdir: + - . +src: + - src/fuse_ctrl_core_axi_write_out_if.sv + - src/fuse_ctrl_core_axi_write_out_monitor_bfm.sv + - src/fuse_ctrl_core_axi_write_out_driver_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_hvl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_hvl.compile new file mode 100644 index 0000000..2d0aa98 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_hvl.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ./fuse_ctrl_core_axi_write_out_common.compile +incdir: + - . +src: + - fuse_ctrl_core_axi_write_out_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_pkg.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_pkg.sv new file mode 100644 index 0000000..4e525f1 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_pkg.sv @@ -0,0 +1,91 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - + +// - +// - +// - + +// - +// - +// - + +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_core_axi_write_out_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg_hdl::*; + import uvmf_base_pkg::*; + import fuse_ctrl_core_axi_write_out_pkg_hdl::*; + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + `include "src/fuse_ctrl_core_axi_write_out_macros.svh" + + export fuse_ctrl_core_axi_write_out_pkg_hdl::*; + + + + // Parameters defined as HVL parameters + + `include "src/fuse_ctrl_core_axi_write_out_typedefs.svh" + `include "src/fuse_ctrl_core_axi_write_out_transaction.svh" + + `include "src/fuse_ctrl_core_axi_write_out_configuration.svh" + `include "src/fuse_ctrl_core_axi_write_out_driver.svh" + `include "src/fuse_ctrl_core_axi_write_out_monitor.svh" + + `include "src/fuse_ctrl_core_axi_write_out_transaction_coverage.svh" + `include "src/fuse_ctrl_core_axi_write_out_sequence_base.svh" + `include "src/fuse_ctrl_core_axi_write_out_random_sequence.svh" + + `include "src/fuse_ctrl_core_axi_write_out_responder_sequence.svh" + `include "src/fuse_ctrl_core_axi_write_out2reg_adapter.svh" + + `include "src/fuse_ctrl_core_axi_write_out_agent.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new interface sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the interface package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_pkg.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_pkg.vinfo new file mode 100644 index 0000000..6c1d385 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_pkg.vinfo @@ -0,0 +1,4 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use fuse_ctrl_core_axi_write_out_pkg_hdl.vinfo ++incdir+@vinfodir +fuse_ctrl_core_axi_write_out_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_pkg_hdl.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_pkg_hdl.sv new file mode 100644 index 0000000..9bdd4e6 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_pkg_hdl.sv @@ -0,0 +1,52 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that needs to be compiled and synthesized +// for running on Veloce. +// +// CONTAINS: +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_core_axi_write_out_pkg_hdl; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HDL parameters + + `include "src/fuse_ctrl_core_axi_write_out_typedefs_hdl.svh" + `include "src/fuse_ctrl_core_axi_write_out_macros.svh" + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_pkg_hdl.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_pkg_hdl.vinfo new file mode 100644 index 0000000..68e75c6 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_pkg_hdl.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +fuse_ctrl_core_axi_write_out_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_pkg_sve.F b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_pkg_sve.F new file mode 100644 index 0000000..dd141cc --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_pkg_sve.F @@ -0,0 +1,10 @@ +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + ++incdir+. +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_filelist_hdl.f +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_core_axi_write_out_pkg/fuse_ctrl_core_axi_write_out_filelist_hvl.f diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out2reg_adapter.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out2reg_adapter.svh new file mode 100644 index 0000000..7f7d115 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out2reg_adapter.svh @@ -0,0 +1,142 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the UVM register adapter for the fuse_ctrl_core_axi_write_out interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_write_out2reg_adapter #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvm_reg_adapter; + + `uvm_object_param_utils( fuse_ctrl_core_axi_write_out2reg_adapter #( + AW, + DW, + IW, + UW + ) +) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //-------------------------------------------------------------------- + // new + //-------------------------------------------------------------------- + function new (string name = "fuse_ctrl_core_axi_write_out2reg_adapter" ); + super.new(name); + // pragma uvmf custom new begin + // UVMF_CHANGE_ME : Configure the adapter regarding byte enables and provides response. + + // Does the protocol the Agent is modeling support byte enables? + // 0 = NO + // 1 = YES + supports_byte_enable = 0; + + // Does the Agent's Driver provide separate response sequence items? + // i.e. Does the driver call seq_item_port.put() + // and do the sequences call get_response()? + // 0 = NO + // 1 = YES + provides_responses = 0; + // pragma uvmf custom new end + + endfunction: new + + //-------------------------------------------------------------------- + // reg2bus + //-------------------------------------------------------------------- + virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw); + + fuse_ctrl_core_axi_write_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + trans_h = fuse_ctrl_core_axi_write_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +::type_id::create("trans_h"); + + // pragma uvmf custom reg2bus begin + // UVMF_CHANGE_ME : Fill in the reg2bus adapter mapping registe fields to protocol fields. + + //Adapt the following for your sequence item type + // trans_h.op = (rw.kind == UVM_READ) ? WB_READ : WB_WRITE; + //Copy over address + // trans_h.addr = rw.addr; + //Copy over write data + // trans_h.data = rw.data; + + // pragma uvmf custom reg2bus end + + // Return the adapted transaction + return trans_h; + + endfunction: reg2bus + + //-------------------------------------------------------------------- + // bus2reg + //-------------------------------------------------------------------- + virtual function void bus2reg(uvm_sequence_item bus_item, + ref uvm_reg_bus_op rw); + fuse_ctrl_core_axi_write_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + trans_h; + if (!$cast(trans_h, bus_item)) begin + `uvm_fatal("ADAPT","Provided bus_item is not of the correct type") + return; + end + // pragma uvmf custom bus2reg begin + // UVMF_CHANGE_ME : Fill in the bus2reg adapter mapping protocol fields to register fields. + //Adapt the following for your sequence item type + //Copy over instruction type + // rw.kind = (trans_h.op == WB_WRITE) ? UVM_WRITE : UVM_READ; + //Copy over address + // rw.addr = trans_h.addr; + //Copy over read data + // rw.data = trans_h.data; + //Check for errors on the bus and return UVM_NOT_OK if there is an error + // rw.status = UVM_IS_OK; + // pragma uvmf custom bus2reg end + + endfunction: bus2reg + +endclass : fuse_ctrl_core_axi_write_out2reg_adapter + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_agent.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_agent.svh new file mode 100644 index 0000000..f35b0c2 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_agent.svh @@ -0,0 +1,109 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: Protocol specific agent class definition +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_write_out_agent #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvmf_parameterized_agent #( + .CONFIG_T(fuse_ctrl_core_axi_write_out_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .DRIVER_T(fuse_ctrl_core_axi_write_out_driver #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .MONITOR_T(fuse_ctrl_core_axi_write_out_monitor #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .COVERAGE_T(fuse_ctrl_core_axi_write_out_transaction_coverage #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .TRANS_T(fuse_ctrl_core_axi_write_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +) + ); + + `uvm_component_param_utils( fuse_ctrl_core_axi_write_out_agent #( + AW, + DW, + IW, + UW + ) +) + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** + // FUNCTION: build_phase + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + if (configuration.active_passive == ACTIVE) begin + // Place sequencer handle into configuration object + // so that it may be retrieved from configuration + // rather than using uvm_config_db + configuration.sequencer = this.sequencer; + end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_configuration.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_configuration.svh new file mode 100644 index 0000000..e6dac33 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_configuration.svh @@ -0,0 +1,241 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class contains all variables and functions used +// to configure the fuse_ctrl_core_axi_write_out agent and its bfm's. It gets the +// bfm's from the uvm_config_db for use by the agent. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_write_out_configuration #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvmf_parameterized_agent_configuration_base #( + .DRIVER_BFM_BIND_T(virtual fuse_ctrl_core_axi_write_out_driver_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .MONITOR_BFM_BIND_T( virtual fuse_ctrl_core_axi_write_out_monitor_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +)); + + `uvm_object_param_utils( fuse_ctrl_core_axi_write_out_configuration #( + AW, + DW, + IW, + UW + ) +) + + + // Sequencer handle populated by agent + uvm_sequencer #(fuse_ctrl_core_axi_write_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + ) sequencer; + + //Constraints for the configuration variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + covergroup fuse_ctrl_core_axi_write_out_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + // pragma uvmf custom covergroup end + endgroup + + //******************************************************************* + //******************************************************************* + // Structure used to pass configuration variables to monitor and driver BFM's. + // Use to_struct function to pack variables into structure. + // Use from_struct function to unpack variables from structure. + // This structure is defined in fuse_ctrl_core_axi_write_out_macros.svh + `fuse_ctrl_core_axi_write_out_CONFIGURATION_STRUCT + fuse_ctrl_core_axi_write_out_configuration_s fuse_ctrl_core_axi_write_out_configuration_struct; + //******************************************************************* + // FUNCTION: to_struct() + // This function packs variables into a fuse_ctrl_core_axi_write_out_configuration_s + // structure. The function returns the handle to the fuse_ctrl_core_axi_write_out_configuration_struct. + // This function is defined in fuse_ctrl_core_axi_write_out_macros.svh + `fuse_ctrl_core_axi_write_out_CONFIGURATION_TO_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_struct() + // This function unpacks the struct provided as an argument into + // variables of this class. + // This function is defined in fuse_ctrl_core_axi_write_out_macros.svh + `fuse_ctrl_core_axi_write_out_CONFIGURATION_FROM_STRUCT_FUNCTION + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + // Construct the covergroup for this configuration class + fuse_ctrl_core_axi_write_out_configuration_cg = new; + endfunction + + // **************************************************************************** + // FUNCTION: post_randomize() + // This function is automatically called after the randomize() function + // is executed. + // + function void post_randomize(); + super.post_randomize(); + fuse_ctrl_core_axi_write_out_configuration_cg.sample(); + endfunction + + // **************************************************************************** + // FUNCTION: initialize + // This function causes the configuration to retrieve + // its virtual interface handle from the uvm_config_db. + // This function also makes itself available to its + // agent through the uvm_config_db. + // + // ARGUMENTS: + // uvmf_active_passive_t activity: + // This argument identifies the simulation level + // as either BLOCK, CHIP, SIMULATION, etc. + // + // AGENT_PATH: + // This argument identifies the path to this + // configurations agent. This configuration + // makes itself available to the agent specified + // by agent_path by placing itself into the + // uvm_config_db. + // + // INTERFACE_NAME: + // This argument identifies the string name of + // this configurations BFM's. This string + // name is used to retrieve the driver and + // monitor BFM from the uvm_config_db. + // + virtual function void initialize(uvmf_active_passive_t activity, + string agent_path, + string interface_name); + + super.initialize( activity, agent_path, interface_name); + // The covergroup is given the same name as the interface + fuse_ctrl_core_axi_write_out_configuration_cg.set_inst_name(interface_name); + + // This configuration places itself into the uvm_config_db for the agent, identified by the agent_path variable, to retrieve. + uvm_config_db #( fuse_ctrl_core_axi_write_out_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + + )::set( null ,agent_path,UVMF_AGENT_CONFIG, this ); + + // This configuration also places itself in the config db using the same identifier used by the interface. This allows users to access + // configuration variables and the interface through the bfm api class rather than directly accessing the BFM. This is useful for + // accessingthe BFM when using Veloce + uvm_config_db #( fuse_ctrl_core_axi_write_out_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + + )::set( null ,UVMF_CONFIGURATIONS, interface_name, this ); + + fuse_ctrl_core_axi_write_out_configuration_cg.set_inst_name($sformatf("fuse_ctrl_core_axi_write_out_configuration_cg_%s",get_full_name())); + +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. + `uvm_info("CFG", + $psprintf("The agent at '%s' is using interface named %s has the following parameters: AW=%x DW=%x IW=%x UW=%x ", agent_path, interface_name, AW ,DW ,IW ,UW ), + UVM_DEBUG) + + // pragma uvmf custom initialize begin + // This controls whether or not the agent returns a transaction handle in the driver when calling + // item_done() back into the sequencer or not. If set to 1, a transaction is sent back which means + // the sequence on the other end must use the get_response() part of the driver/sequence API. If + // this doesn't occur, there will eventually be response_queue overflow errors during the test. + return_transaction_response = 1'b0; + + // pragma uvmf custom initialize end + + endfunction + + // **************************************************************************** + // TASK: wait_for_reset + // *[Required]* Blocks until reset is released. The wait_for_reset operation is performed + // by a task in the monitor bfm. + virtual task wait_for_reset(); + monitor_bfm.wait_for_reset(); + endtask + + // **************************************************************************** + // TASK: wait_for_num_clocks + // *[Required]* Blocks until specified number of clocks have elapsed. The wait_for_num_clocks + // operation is performed by a task in the monitor bfm. + virtual task wait_for_num_clocks(int clocks); + monitor_bfm.wait_for_num_clocks(clocks); + endtask + + // **************************************************************************** + // FUNCTION : convert2string() + // This function is used to convert variables in this class into a string for log messaging. + // + virtual function string convert2string (); + // pragma uvmf custom convert2string begin + return $sformatf(""); + // pragma uvmf custom convert2string end + endfunction + + // **************************************************************************** + // FUNCTION: get_sequencer + function uvm_sequencer #(fuse_ctrl_core_axi_write_out_transaction#( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +) get_sequencer(); + return sequencer; + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_driver.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_driver.svh new file mode 100644 index 0000000..18a3dac --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_driver.svh @@ -0,0 +1,141 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class passes transactions between the sequencer +// and the BFM driver interface. It accesses the driver BFM +// through the bfm handle. This driver +// passes transactions to the driver BFM through the access +// task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_write_out_driver #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvmf_driver_base #( + .CONFIG_T(fuse_ctrl_core_axi_write_out_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + ), + .BFM_BIND_T(virtual fuse_ctrl_core_axi_write_out_driver_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + ), + .REQ(fuse_ctrl_core_axi_write_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + ), + .RSP(fuse_ctrl_core_axi_write_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + )); + + `uvm_component_param_utils( fuse_ctrl_core_axi_write_out_driver #( + AW, + DW, + IW, + UW + ) +) +//******************************************************************* +// Macros that define structs located in fuse_ctrl_core_axi_write_out_macros.svh +//******************************************************************* +// Initiator macro used by fuse_ctrl_core_axi_write_out_driver and fuse_ctrl_core_axi_write_out_driver_bfm +// to communicate initiator driven data to fuse_ctrl_core_axi_write_out_driver_bfm. +`fuse_ctrl_core_axi_write_out_INITIATOR_STRUCT + fuse_ctrl_core_axi_write_out_initiator_s fuse_ctrl_core_axi_write_out_initiator_struct; +//******************************************************************* +// Responder macro used by fuse_ctrl_core_axi_write_out_driver and fuse_ctrl_core_axi_write_out_driver_bfm +// to communicate Responder driven data to fuse_ctrl_core_axi_write_out_driver_bfm. +`fuse_ctrl_core_axi_write_out_RESPONDER_STRUCT + fuse_ctrl_core_axi_write_out_responder_s fuse_ctrl_core_axi_write_out_responder_struct; + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent=null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the driver BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// driver BFM. This allows the driver BFM to call tasks and function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// **************************************************************************** +// This task is called by the run_phase in uvmf_driver_base. + virtual task access( inout REQ txn ); +// pragma uvmf custom access begin + if (configuration.initiator_responder==RESPONDER) begin + // Complete current transfer and wait for next transfer + bfm.respond_and_wait_for_next_transfer( + fuse_ctrl_core_axi_write_out_initiator_struct, + txn.to_responder_struct() + ); + // Unpack information about initiated transfer received by this responder + txn.from_initiator_struct(fuse_ctrl_core_axi_write_out_initiator_struct); + end else begin + // Initiate a transfer and get response + bfm.initiate_and_get_response( + txn.to_initiator_struct(), + fuse_ctrl_core_axi_write_out_responder_struct + ); + // Unpack transfer response information received by this initiator + txn.from_responder_struct(fuse_ctrl_core_axi_write_out_responder_struct); + end +// pragma uvmf custom access end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_driver_bfm.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_driver_bfm.sv new file mode 100644 index 0000000..ee3c4fb --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_driver_bfm.sv @@ -0,0 +1,341 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This interface performs the fuse_ctrl_core_axi_write_out signal driving. It is +// accessed by the uvm fuse_ctrl_core_axi_write_out driver through a virtual interface +// handle in the fuse_ctrl_core_axi_write_out configuration. It drives the singals passed +// in through the port connection named bus of type fuse_ctrl_core_axi_write_out_if. +// +// Input signals from the fuse_ctrl_core_axi_write_out_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// This bfm drives signals with a _o suffix. These signals +// are driven onto signals within fuse_ctrl_core_axi_write_out_if based on INITIATOR/RESPONDER and/or +// ARBITRATION/GRANT status. +// +// The output signal connections are as follows: +// signal_o -> bus.signal +// +// +// Interface functions and tasks used by UVM components: +// +// configure: +// This function gets configuration attributes from the +// UVM driver to set any required BFM configuration +// variables such as 'initiator_responder'. +// +// initiate_and_get_response: +// This task is used to perform signaling activity for initiating +// a protocol transfer. The task initiates the transfer, using +// input data from the initiator struct. Then the task captures +// response data, placing the data into the response struct. +// The response struct is returned to the driver class. +// +// respond_and_wait_for_next_transfer: +// This task is used to complete a current transfer as a responder +// and then wait for the initiator to start the next transfer. +// The task uses data in the responder struct to drive protocol +// signals to complete the transfer. The task then waits for +// the next transfer. Once the next transfer begins, data from +// the initiator is placed into the initiator struct and sent +// to the responder sequence for processing to determine +// what data to respond with. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_core_axi_write_out_pkg_hdl::*; +`include "src/fuse_ctrl_core_axi_write_out_macros.svh" + +interface fuse_ctrl_core_axi_write_out_driver_bfm #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + + (fuse_ctrl_core_axi_write_out_if bus); + // The following pragma and additional ones in-lined further below are for running this BFM on Veloce + // pragma attribute fuse_ctrl_core_axi_write_out_driver_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: AW=%x DW=%x IW=%x UW=%x ", AW,DW,IW,UW), + UVM_DEBUG) +end +`endif + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + tri clk_i_i; + tri rst_ni_i; + + // Signal list (all signals are capable of being inputs and outputs for the sake + // of supporting both INITIATOR and RESPONDER mode operation. Expectation is that + // directionality in the config file was from the point-of-view of the INITIATOR + + // INITIATOR mode input signals + tri awready_i; + reg awready_o = 'bz; + tri wready_i; + reg wready_o = 'bz; + tri [$bits(axi_pkg::axi_burst_e)-1:0] bresp_i; + reg [$bits(axi_pkg::axi_burst_e)-1:0] bresp_o = 'bz; + tri bid_i; + reg bid_o = 'bz; + tri bvalid_i; + reg bvalid_o = 'bz; + + // INITIATOR mode output signals + + // Bi-directional signals + + + assign clk_i_i = bus.clk_i; + assign rst_ni_i = bus.rst_ni; + + // These are signals marked as 'input' by the config file, but the signals will be + // driven by this BFM if put into RESPONDER mode (flipping all signal directions around) + assign awready_i = bus.awready; + assign bus.awready = (initiator_responder == RESPONDER) ? awready_o : 'bz; + assign wready_i = bus.wready; + assign bus.wready = (initiator_responder == RESPONDER) ? wready_o : 'bz; + assign bresp_i = bus.bresp; + assign bus.bresp = (initiator_responder == RESPONDER) ? bresp_o : 'bz; + assign bid_i = bus.bid; + assign bus.bid = (initiator_responder == RESPONDER) ? bid_o : 'bz; + assign bvalid_i = bus.bvalid; + assign bus.bvalid = (initiator_responder == RESPONDER) ? bvalid_o : 'bz; + + + // These are signals marked as 'output' by the config file, but the outputs will + // not be driven by this BFM unless placed in INITIATOR mode. + + // Proxy handle to UVM driver + fuse_ctrl_core_axi_write_out_pkg::fuse_ctrl_core_axi_write_out_driver #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + proxy; + // pragma tbx oneway proxy.my_function_name_in_uvm_driver + + // **************************************************************************** + // **************************************************************************** + // Macros that define structs located in fuse_ctrl_core_axi_write_out_macros.svh + // **************************************************************************** + // Struct for passing configuration data from fuse_ctrl_core_axi_write_out_driver to this BFM + // **************************************************************************** + `fuse_ctrl_core_axi_write_out_CONFIGURATION_STRUCT + // **************************************************************************** + // Structs for INITIATOR and RESPONDER data flow + //******************************************************************* + // Initiator macro used by fuse_ctrl_core_axi_write_out_driver and fuse_ctrl_core_axi_write_out_driver_bfm + // to communicate initiator driven data to fuse_ctrl_core_axi_write_out_driver_bfm. + `fuse_ctrl_core_axi_write_out_INITIATOR_STRUCT + fuse_ctrl_core_axi_write_out_initiator_s initiator_struct; + // Responder macro used by fuse_ctrl_core_axi_write_out_driver and fuse_ctrl_core_axi_write_out_driver_bfm + // to communicate Responder driven data to fuse_ctrl_core_axi_write_out_driver_bfm. + `fuse_ctrl_core_axi_write_out_RESPONDER_STRUCT + fuse_ctrl_core_axi_write_out_responder_s responder_struct; + + // **************************************************************************** +// pragma uvmf custom reset_condition_and_response begin + // Always block used to return signals to reset value upon assertion of reset + always @( negedge rst_ni_i ) + begin + // RESPONDER mode output signals + awready_o <= 'bz; + wready_o <= 'bz; + bresp_o <= 'bz; + bid_o <= 'bz; + bvalid_o <= 'bz; + // INITIATOR mode output signals + // Bi-directional signals + + end +// pragma uvmf custom reset_condition_and_response end + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the driver BFM. It is called by the driver within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the driver BFM needs to be aware of the new configuration + // variables. + // + + function void configure(fuse_ctrl_core_axi_write_out_configuration_s fuse_ctrl_core_axi_write_out_configuration_arg); // pragma tbx xtf + initiator_responder = fuse_ctrl_core_axi_write_out_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + +// pragma uvmf custom initiate_and_get_response begin +// **************************************************************************** +// UVMF_CHANGE_ME +// This task is used by an initator. The task first initiates a transfer then +// waits for the responder to complete the transfer. + task initiate_and_get_response( + // This argument passes transaction variables used by an initiator + // to perform the initial part of a protocol transfer. The values + // come from a sequence item created in a sequence. + input fuse_ctrl_core_axi_write_out_initiator_s fuse_ctrl_core_axi_write_out_initiator_struct, + // This argument is used to send data received from the responder + // back to the sequence item. The sequence item is returned to the sequence. + output fuse_ctrl_core_axi_write_out_responder_s fuse_ctrl_core_axi_write_out_responder_struct + );// pragma tbx xtf + // + // Members within the fuse_ctrl_core_axi_write_out_initiator_struct: + // logic core_awready ; + // logic core_wready ; + // axi_pkg::axi_burst_e core_bresp ; + // logic core_bid ; + // logic core_bvalid ; + // Members within the fuse_ctrl_core_axi_write_out_responder_struct: + // logic core_awready ; + // logic core_wready ; + // axi_pkg::axi_burst_e core_bresp ; + // logic core_bid ; + // logic core_bvalid ; + initiator_struct = fuse_ctrl_core_axi_write_out_initiator_struct; + // + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clk_i_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available initiator input and inout signals listed. + // Initiator input signals + // fuse_ctrl_core_axi_write_out_responder_struct.xyz = awready_i; // + // fuse_ctrl_core_axi_write_out_responder_struct.xyz = wready_i; // + // fuse_ctrl_core_axi_write_out_responder_struct.xyz = bresp_i; // [$bits(axi_pkg::axi_burst_e)-1:0] + // fuse_ctrl_core_axi_write_out_responder_struct.xyz = bid_i; // + // fuse_ctrl_core_axi_write_out_responder_struct.xyz = bvalid_i; // + // Initiator inout signals + // How to assign a signal from an initiator struct member named xyz. + // All available initiator output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Initiator output signals + // Initiator inout signals + // Initiate a transfer using the data received. + @(posedge clk_i_i); + @(posedge clk_i_i); + // Wait for the responder to complete the transfer then place the responder data into + // fuse_ctrl_core_axi_write_out_responder_struct. + @(posedge clk_i_i); + @(posedge clk_i_i); + responder_struct = fuse_ctrl_core_axi_write_out_responder_struct; + endtask +// pragma uvmf custom initiate_and_get_response end + +// pragma uvmf custom respond_and_wait_for_next_transfer begin +// **************************************************************************** +// The first_transfer variable is used to prevent completing a transfer in the +// first call to this task. For the first call to this task, there is not +// current transfer to complete. +bit first_transfer=1; + +// UVMF_CHANGE_ME +// This task is used by a responder. The task first completes the current +// transfer in progress then waits for the initiator to start the next transfer. + task respond_and_wait_for_next_transfer( + // This argument is used to send data received from the initiator + // back to the sequence item. The sequence determines how to respond. + output fuse_ctrl_core_axi_write_out_initiator_s fuse_ctrl_core_axi_write_out_initiator_struct, + // This argument passes transaction variables used by a responder + // to complete a protocol transfer. The values come from a sequence item. + input fuse_ctrl_core_axi_write_out_responder_s fuse_ctrl_core_axi_write_out_responder_struct + );// pragma tbx xtf + // Variables within the fuse_ctrl_core_axi_write_out_initiator_struct: + // logic core_awready ; + // logic core_wready ; + // axi_pkg::axi_burst_e core_bresp ; + // logic core_bid ; + // logic core_bvalid ; + // Variables within the fuse_ctrl_core_axi_write_out_responder_struct: + // logic core_awready ; + // logic core_wready ; + // axi_pkg::axi_burst_e core_bresp ; + // logic core_bid ; + // logic core_bvalid ; + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clk_i_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available responder input and inout signals listed. + // Responder input signals + // Responder inout signals + // How to assign a signal, named xyz, from an initiator struct member. + // All available responder output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Responder output signals + // awready_o <= fuse_ctrl_core_axi_write_out_initiator_struct.xyz; // + // wready_o <= fuse_ctrl_core_axi_write_out_initiator_struct.xyz; // + // bresp_o <= fuse_ctrl_core_axi_write_out_initiator_struct.xyz; // [$bits(axi_pkg::axi_burst_e)-1:0] + // bid_o <= fuse_ctrl_core_axi_write_out_initiator_struct.xyz; // + // bvalid_o <= fuse_ctrl_core_axi_write_out_initiator_struct.xyz; // + // Responder inout signals + + @(posedge clk_i_i); + if (!first_transfer) begin + // Perform transfer response here. + // Reply using data recieved in the fuse_ctrl_core_axi_write_out_responder_struct. + @(posedge clk_i_i); + // Reply using data recieved in the transaction handle. + @(posedge clk_i_i); + end + // Wait for next transfer then gather info from intiator about the transfer. + // Place the data into the fuse_ctrl_core_axi_write_out_initiator_struct. + @(posedge clk_i_i); + @(posedge clk_i_i); + first_transfer = 0; + endtask +// pragma uvmf custom respond_and_wait_for_next_transfer end + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_if.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_if.sv new file mode 100644 index 0000000..a5e2f1c --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_if.sv @@ -0,0 +1,104 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface contains the fuse_ctrl_core_axi_write_out interface signals. +// It is instantiated once per fuse_ctrl_core_axi_write_out bus. Bus Functional Models, +// BFM's named fuse_ctrl_core_axi_write_out_driver_bfm, are used to drive signals on the bus. +// BFM's named fuse_ctrl_core_axi_write_out_monitor_bfm are used to monitor signals on the +// bus. This interface signal bundle is passed in the port list of +// the BFM in order to give the BFM access to the signals in this +// interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// This template can be used to connect a DUT to these signals +// +// .dut_signal_port(fuse_ctrl_core_axi_write_out_bus.awready), // Agent input +// .dut_signal_port(fuse_ctrl_core_axi_write_out_bus.wready), // Agent input +// .dut_signal_port(fuse_ctrl_core_axi_write_out_bus.bresp), // Agent input +// .dut_signal_port(fuse_ctrl_core_axi_write_out_bus.bid), // Agent input +// .dut_signal_port(fuse_ctrl_core_axi_write_out_bus.bvalid), // Agent input + +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_core_axi_write_out_pkg_hdl::*; + +interface fuse_ctrl_core_axi_write_out_if #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + + + ( + input tri clk_i, + input tri rst_ni, + inout tri awready, + inout tri wready, + inout tri [$bits(axi_pkg::axi_burst_e)-1:0] bresp, + inout tri bid, + inout tri bvalid + ); + +modport monitor_port + ( + input clk_i, + input rst_ni, + input awready, + input wready, + input bresp, + input bid, + input bvalid + ); + +modport initiator_port + ( + input clk_i, + input rst_ni, + input awready, + input wready, + input bresp, + input bid, + input bvalid + ); + +modport responder_port + ( + input clk_i, + input rst_ni, + output awready, + output wready, + output bresp, + output bid, + output bvalid + ); + + +// pragma uvmf custom interface_item_additional begin +// pragma uvmf custom interface_item_additional end + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_infact_coverage_strategy.csv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_infact_coverage_strategy.csv new file mode 100644 index 0000000..1c218e1 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_infact_coverage_strategy.csv @@ -0,0 +1,6 @@ +Global +auto_bin_max, 64 + +Name,Type,Include +rand_fields,coverpoint,=rand *.** + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_macros.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_macros.svh new file mode 100644 index 0000000..5f57ee1 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_macros.svh @@ -0,0 +1,171 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains macros used with the fuse_ctrl_core_axi_write_out package. +// These macros include packed struct definitions. These structs are +// used to pass data between classes, hvl, and BFM's, hdl. Use of +// structs are more efficient and simpler to modify. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_struct +// and from_struct methods defined in the macros below that are used in +// the fuse_ctrl_core_axi_write_out_configuration class. +// + `define fuse_ctrl_core_axi_write_out_CONFIGURATION_STRUCT \ +typedef struct packed { \ + uvmf_active_passive_t active_passive; \ + uvmf_initiator_responder_t initiator_responder; \ + } fuse_ctrl_core_axi_write_out_configuration_s; + + `define fuse_ctrl_core_axi_write_out_CONFIGURATION_TO_STRUCT_FUNCTION \ + virtual function fuse_ctrl_core_axi_write_out_configuration_s to_struct();\ + fuse_ctrl_core_axi_write_out_configuration_struct = \ + {\ + this.active_passive,\ + this.initiator_responder\ + };\ + return ( fuse_ctrl_core_axi_write_out_configuration_struct );\ + endfunction + + `define fuse_ctrl_core_axi_write_out_CONFIGURATION_FROM_STRUCT_FUNCTION \ + virtual function void from_struct(fuse_ctrl_core_axi_write_out_configuration_s fuse_ctrl_core_axi_write_out_configuration_struct);\ + {\ + this.active_passive,\ + this.initiator_responder \ + } = fuse_ctrl_core_axi_write_out_configuration_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_monitor_struct +// and from_monitor_struct methods of the fuse_ctrl_core_axi_write_out_transaction class. +// + `define fuse_ctrl_core_axi_write_out_MONITOR_STRUCT typedef struct packed { \ + logic core_awready ; \ + logic core_wready ; \ + axi_pkg::axi_burst_e core_bresp ; \ + logic core_bid ; \ + logic core_bvalid ; \ + } fuse_ctrl_core_axi_write_out_monitor_s; + + `define fuse_ctrl_core_axi_write_out_TO_MONITOR_STRUCT_FUNCTION \ + virtual function fuse_ctrl_core_axi_write_out_monitor_s to_monitor_struct();\ + fuse_ctrl_core_axi_write_out_monitor_struct = \ + { \ + this.core_awready , \ + this.core_wready , \ + this.core_bresp , \ + this.core_bid , \ + this.core_bvalid \ + };\ + return ( fuse_ctrl_core_axi_write_out_monitor_struct);\ + endfunction\ + + `define fuse_ctrl_core_axi_write_out_FROM_MONITOR_STRUCT_FUNCTION \ + virtual function void from_monitor_struct(fuse_ctrl_core_axi_write_out_monitor_s fuse_ctrl_core_axi_write_out_monitor_struct);\ + {\ + this.core_awready , \ + this.core_wready , \ + this.core_bresp , \ + this.core_bid , \ + this.core_bvalid \ + } = fuse_ctrl_core_axi_write_out_monitor_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_initiator_struct +// and from_initiator_struct methods of the fuse_ctrl_core_axi_write_out_transaction class. +// Also update the comments in the driver BFM. +// + `define fuse_ctrl_core_axi_write_out_INITIATOR_STRUCT typedef struct packed { \ + logic core_awready ; \ + logic core_wready ; \ + axi_pkg::axi_burst_e core_bresp ; \ + logic core_bid ; \ + logic core_bvalid ; \ + } fuse_ctrl_core_axi_write_out_initiator_s; + + `define fuse_ctrl_core_axi_write_out_TO_INITIATOR_STRUCT_FUNCTION \ + virtual function fuse_ctrl_core_axi_write_out_initiator_s to_initiator_struct();\ + fuse_ctrl_core_axi_write_out_initiator_struct = \ + {\ + this.core_awready , \ + this.core_wready , \ + this.core_bresp , \ + this.core_bid , \ + this.core_bvalid \ + };\ + return ( fuse_ctrl_core_axi_write_out_initiator_struct);\ + endfunction + + `define fuse_ctrl_core_axi_write_out_FROM_INITIATOR_STRUCT_FUNCTION \ + virtual function void from_initiator_struct(fuse_ctrl_core_axi_write_out_initiator_s fuse_ctrl_core_axi_write_out_initiator_struct);\ + {\ + this.core_awready , \ + this.core_wready , \ + this.core_bresp , \ + this.core_bid , \ + this.core_bvalid \ + } = fuse_ctrl_core_axi_write_out_initiator_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_responder_struct +// and from_responder_struct methods of the fuse_ctrl_core_axi_write_out_transaction class. +// Also update the comments in the driver BFM. +// + `define fuse_ctrl_core_axi_write_out_RESPONDER_STRUCT typedef struct packed { \ + logic core_awready ; \ + logic core_wready ; \ + axi_pkg::axi_burst_e core_bresp ; \ + logic core_bid ; \ + logic core_bvalid ; \ + } fuse_ctrl_core_axi_write_out_responder_s; + + `define fuse_ctrl_core_axi_write_out_TO_RESPONDER_STRUCT_FUNCTION \ + virtual function fuse_ctrl_core_axi_write_out_responder_s to_responder_struct();\ + fuse_ctrl_core_axi_write_out_responder_struct = \ + {\ + this.core_awready , \ + this.core_wready , \ + this.core_bresp , \ + this.core_bid , \ + this.core_bvalid \ + };\ + return ( fuse_ctrl_core_axi_write_out_responder_struct);\ + endfunction + + `define fuse_ctrl_core_axi_write_out_FROM_RESPONDER_STRUCT_FUNCTION \ + virtual function void from_responder_struct(fuse_ctrl_core_axi_write_out_responder_s fuse_ctrl_core_axi_write_out_responder_struct);\ + {\ + this.core_awready , \ + this.core_wready , \ + this.core_bresp , \ + this.core_bid , \ + this.core_bvalid \ + } = fuse_ctrl_core_axi_write_out_responder_struct;\ + endfunction +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_monitor.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_monitor.svh new file mode 100644 index 0000000..d540c2d --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_monitor.svh @@ -0,0 +1,131 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class receives fuse_ctrl_core_axi_write_out transactions observed by the +// fuse_ctrl_core_axi_write_out monitor BFM and broadcasts them through the analysis port +// on the agent. It accesses the monitor BFM through the monitor +// task. This UVM component captures transactions +// for viewing in the waveform viewer if the +// enable_transaction_viewing flag is set in the configuration. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_write_out_monitor #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvmf_monitor_base #( + .CONFIG_T(fuse_ctrl_core_axi_write_out_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .BFM_BIND_T(virtual fuse_ctrl_core_axi_write_out_monitor_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .TRANS_T(fuse_ctrl_core_axi_write_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +)); + + `uvm_component_param_utils( fuse_ctrl_core_axi_write_out_monitor #( + AW, + DW, + IW, + UW + ) +) + +// Structure used to pass data from monitor BFM to monitor class in agent. +// Use to_monitor_struct function to pack transaction variables into structure. +// Use from_monitor_struct function to unpack transaction variables from structure. +`fuse_ctrl_core_axi_write_out_MONITOR_STRUCT + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the monitor BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// monitor BFM. This allows the monitor BFM to call the notify_transaction +// function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// *************************************************************************** + virtual task run_phase(uvm_phase phase); + // Start monitor BFM thread and don't call super.run() in order to + // override the default monitor proxy 'pull' behavior with the more + // emulation-friendly BFM 'push' approach using the notify_transaction + // function below + bfm.start_monitoring(); + endtask + +// ************************************************************************** + +// This function is called by the monitor BFM. It receives data observed by the +// monitor BFM. Data is passed using the fuse_ctrl_core_axi_write_out_monitor_struct. + virtual function void notify_transaction(input fuse_ctrl_core_axi_write_out_monitor_s fuse_ctrl_core_axi_write_out_monitor_struct); + + + trans = new("trans"); + trans.from_monitor_struct(fuse_ctrl_core_axi_write_out_monitor_struct); + trans.start_time = time_stamp; + trans.end_time = $time; + time_stamp = trans.end_time; + + analyze(trans); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_monitor_bfm.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_monitor_bfm.sv new file mode 100644 index 0000000..d39a378 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_monitor_bfm.sv @@ -0,0 +1,216 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface performs the fuse_ctrl_core_axi_write_out signal monitoring. +// It is accessed by the uvm fuse_ctrl_core_axi_write_out monitor through a virtual +// interface handle in the fuse_ctrl_core_axi_write_out configuration. It monitors the +// signals passed in through the port connection named bus of +// type fuse_ctrl_core_axi_write_out_if. +// +// Input signals from the fuse_ctrl_core_axi_write_out_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// Interface functions and tasks used by UVM components: +// monitor(inout TRANS_T txn); +// This task receives the transaction, txn, from the +// UVM monitor and then populates variables in txn +// from values observed on bus activity. This task +// blocks until an operation on the fuse_ctrl_core_axi_write_out bus is complete. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_core_axi_write_out_pkg_hdl::*; +`include "src/fuse_ctrl_core_axi_write_out_macros.svh" + + +interface fuse_ctrl_core_axi_write_out_monitor_bfm #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + + ( fuse_ctrl_core_axi_write_out_if bus ); + // The pragma below and additional ones in-lined further down are for running this BFM on Veloce + // pragma attribute fuse_ctrl_core_axi_write_out_monitor_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: AW=%x DW=%x IW=%x UW=%x ", AW,DW,IW,UW), + UVM_DEBUG) +end +`endif + + + // Structure used to pass transaction data from monitor BFM to monitor class in agent. +`fuse_ctrl_core_axi_write_out_MONITOR_STRUCT + fuse_ctrl_core_axi_write_out_monitor_s fuse_ctrl_core_axi_write_out_monitor_struct; + + // Structure used to pass configuration data from monitor class to monitor BFM. + `fuse_ctrl_core_axi_write_out_CONFIGURATION_STRUCT + + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + tri clk_i_i; + tri rst_ni_i; + tri awready_i; + tri wready_i; + tri [$bits(axi_pkg::axi_burst_e)-1:0] bresp_i; + tri bid_i; + tri bvalid_i; + assign clk_i_i = bus.clk_i; + assign rst_ni_i = bus.rst_ni; + assign awready_i = bus.awready; + assign wready_i = bus.wready; + assign bresp_i = bus.bresp; + assign bid_i = bus.bid; + assign bvalid_i = bus.bvalid; + + // Proxy handle to UVM monitor + fuse_ctrl_core_axi_write_out_pkg::fuse_ctrl_core_axi_write_out_monitor #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + proxy; + // pragma tbx oneway proxy.notify_transaction + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + task wait_for_reset();// pragma tbx xtf + @(posedge clk_i_i) ; + do_wait_for_reset(); + endtask + + // **************************************************************************** + task do_wait_for_reset(); + // pragma uvmf custom reset_condition begin + wait ( rst_ni_i === 1 ) ; + @(posedge clk_i_i) ; + // pragma uvmf custom reset_condition end + endtask + + //****************************************************************** + + task wait_for_num_clocks(input int unsigned count); // pragma tbx xtf + @(posedge clk_i_i); + + repeat (count-1) @(posedge clk_i_i); + endtask + + //****************************************************************** + event go; + function void start_monitoring();// pragma tbx xtf + -> go; + endfunction + + // **************************************************************************** + initial begin + @go; + forever begin + @(posedge clk_i_i); + do_monitor( fuse_ctrl_core_axi_write_out_monitor_struct ); + + + proxy.notify_transaction( fuse_ctrl_core_axi_write_out_monitor_struct ); + + end + end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the monitor BFM. It is called by the monitor within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the monitor BFM needs to be aware of the new configuration + // variables. + // + function void configure(fuse_ctrl_core_axi_write_out_configuration_s fuse_ctrl_core_axi_write_out_configuration_arg); // pragma tbx xtf + initiator_responder = fuse_ctrl_core_axi_write_out_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + + + // **************************************************************************** + + task do_monitor(output fuse_ctrl_core_axi_write_out_monitor_s fuse_ctrl_core_axi_write_out_monitor_struct); + // + // Available struct members: + // // fuse_ctrl_core_axi_write_out_monitor_struct.core_awready + // // fuse_ctrl_core_axi_write_out_monitor_struct.core_wready + // // fuse_ctrl_core_axi_write_out_monitor_struct.core_bresp + // // fuse_ctrl_core_axi_write_out_monitor_struct.core_bid + // // fuse_ctrl_core_axi_write_out_monitor_struct.core_bvalid + // // + // Reference code; + // How to wait for signal value + // while (control_signal === 1'b1) @(posedge clk_i_i); + // + // How to assign a struct member, named xyz, from a signal. + // All available input signals listed. + // fuse_ctrl_core_axi_write_out_monitor_struct.xyz = awready_i; // + // fuse_ctrl_core_axi_write_out_monitor_struct.xyz = wready_i; // + // fuse_ctrl_core_axi_write_out_monitor_struct.xyz = bresp_i; // [$bits(axi_pkg::axi_burst_e)-1:0] + // fuse_ctrl_core_axi_write_out_monitor_struct.xyz = bid_i; // + // fuse_ctrl_core_axi_write_out_monitor_struct.xyz = bvalid_i; // + // pragma uvmf custom do_monitor begin + // UVMF_CHANGE_ME : Implement protocol monitoring. The commented reference code + // below are examples of how to capture signal values and assign them to + // structure members. All available input signals are listed. The 'while' + // code example shows how to wait for a synchronous flow control signal. This + // task should return when a complete transfer has been observed. Once this task is + // exited with captured values, it is then called again to wait for and observe + // the next transfer. One clock cycle is consumed between calls to do_monitor. + @(posedge clk_i_i); + @(posedge clk_i_i); + @(posedge clk_i_i); + @(posedge clk_i_i); + // pragma uvmf custom do_monitor end + endtask + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_random_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_random_sequence.svh new file mode 100644 index 0000000..490a94f --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_random_sequence.svh @@ -0,0 +1,91 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This sequences randomizes the fuse_ctrl_core_axi_write_out transaction and sends it +// to the UVM driver. +// +// This sequence constructs and randomizes a fuse_ctrl_core_axi_write_out_transaction. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_write_out_random_sequence #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + + extends fuse_ctrl_core_axi_write_out_sequence_base #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +; + + `uvm_object_param_utils( fuse_ctrl_core_axi_write_out_random_sequence #( + AW, + DW, + IW, + UW + ) +) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //***************************************************************** + function new(string name = ""); + super.new(name); + endfunction: new + + // **************************************************************************** + // TASK : body() + // This task is automatically executed when this sequence is started using the + // start(sequencerHandle) task. + // + task body(); + + // Construct the transaction + req=fuse_ctrl_core_axi_write_out_transaction#( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +::type_id::create("req"); + start_item(req); + // Randomize the transaction + if(!req.randomize()) `uvm_fatal("SEQ", "fuse_ctrl_core_axi_write_out_random_sequence::body()-fuse_ctrl_core_axi_write_out_transaction randomization failed") + // Send the transaction to the fuse_ctrl_core_axi_write_out_driver_bfm via the sequencer and fuse_ctrl_core_axi_write_out_driver. + finish_item(req); + `uvm_info("SEQ", {"Response:",req.convert2string()},UVM_MEDIUM) + + endtask + +endclass: fuse_ctrl_core_axi_write_out_random_sequence + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_responder_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_responder_sequence.svh new file mode 100644 index 0000000..9aaa395 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_responder_sequence.svh @@ -0,0 +1,87 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class can be used to provide stimulus when an interface +// has been configured to run in a responder mode. It +// will never finish by default, always going back to the driver +// and driver BFM for the next transaction with which to respond. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_write_out_responder_sequence #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + + extends fuse_ctrl_core_axi_write_out_sequence_base #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +; + + `uvm_object_param_utils( fuse_ctrl_core_axi_write_out_responder_sequence #( + AW, + DW, + IW, + UW + ) +) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "fuse_ctrl_core_axi_write_out_responder_sequence"); + super.new(name); + endfunction + + task body(); + req=fuse_ctrl_core_axi_write_out_transaction#( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +::type_id::create("req"); + forever begin + start_item(req); + finish_item(req); + // pragma uvmf custom body begin + // UVMF_CHANGE_ME : Do something here with the resulting req item. The + // finish_item() call above will block until the req transaction is ready + // to be handled by the responder sequence. + // If this was an item that required a response, the expectation is + // that the response should be populated within this transaction now. + `uvm_info("SEQ",$sformatf("Processed txn: %s",req.convert2string()),UVM_HIGH) + // pragma uvmf custom body end + end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_sequence_base.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_sequence_base.svh new file mode 100644 index 0000000..d4ae2f4 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_sequence_base.svh @@ -0,0 +1,146 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the class used as the base class for all sequences +// for this interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_write_out_sequence_base #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvmf_sequence_base #( + .REQ(fuse_ctrl_core_axi_write_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .RSP(fuse_ctrl_core_axi_write_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +)); + + `uvm_object_param_utils( fuse_ctrl_core_axi_write_out_sequence_base #( + AW, + DW, + IW, + UW + ) +) + + // variables + typedef fuse_ctrl_core_axi_write_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + fuse_ctrl_core_axi_write_out_transaction_req_t; + fuse_ctrl_core_axi_write_out_transaction_req_t req; + typedef fuse_ctrl_core_axi_write_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + fuse_ctrl_core_axi_write_out_transaction_rsp_t; + fuse_ctrl_core_axi_write_out_transaction_rsp_t rsp; + + // Event for identifying when a response was received from the sequencer + event new_rsp; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // TASK : get_responses() + // This task recursively gets sequence item responses from the sequencer. + // + virtual task get_responses(); + fork + begin + // Block until new rsp available + get_response(rsp); + // New rsp received. Indicate to sequence using event. + ->new_rsp; + // Display the received response transaction + `uvm_info("SEQ", {"New response transaction:",rsp.convert2string()}, UVM_MEDIUM) + end + join_none + endtask + + // **************************************************************************** + // TASK : pre_body() + // This task is called automatically when start is called with call_pre_post set to 1 (default). + // By calling get_responses() within pre_body() any derived sequences are automatically + // processing response transactions. Only un-comment this call to get_responses() if you + // have configured the interface driver to utilize the response transaction path by setting + // the configuration variable "return_transaction_response" to 1. Otherwise it is possible + // to impact runtime performance and memory utilization. + // + virtual task pre_body(); + // pragma uvmf custom pre_body begin +// get_responses(); + // pragma uvmf custom pre_body end + endtask + + // **************************************************************************** + // TASK : body() + // This task is called automatically when start is called. This sequence sends + // a req sequence item to the sequencer identified as an argument in the call + // to start. + // + virtual task body(); + // pragma uvmf custom body begin + start_item(req); + finish_item(req); + // pragma uvmf custom body end + endtask + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name =""); + super.new( name ); + // pragma uvmf custom new begin + req = fuse_ctrl_core_axi_write_out_transaction_req_t::type_id::create("req"); + rsp = fuse_ctrl_core_axi_write_out_transaction_rsp_t::type_id::create("rsp"); + // pragma uvmf custom new end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_transaction.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_transaction.svh new file mode 100644 index 0000000..fc836d8 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_transaction.svh @@ -0,0 +1,236 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class defines the variables required for an fuse_ctrl_core_axi_write_out +// transaction. Class variables to be displayed in waveform transaction +// viewing are added to the transaction viewing stream in the add_to_wave +// function. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_write_out_transaction #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvmf_transaction_base; + + `uvm_object_param_utils( fuse_ctrl_core_axi_write_out_transaction #( + AW, + DW, + IW, + UW + ) +) + + logic core_awready ; + logic core_wready ; + axi_pkg::axi_burst_e core_bresp ; + logic core_bid ; + logic core_bvalid ; + + //Constraints for the transaction variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //******************************************************************* + //******************************************************************* + // Macros that define structs and associated functions are + // located in fuse_ctrl_core_axi_write_out_macros.svh + + //******************************************************************* + // Monitor macro used by fuse_ctrl_core_axi_write_out_monitor and fuse_ctrl_core_axi_write_out_monitor_bfm + // This struct is defined in fuse_ctrl_core_axi_write_out_macros.svh + `fuse_ctrl_core_axi_write_out_MONITOR_STRUCT + fuse_ctrl_core_axi_write_out_monitor_s fuse_ctrl_core_axi_write_out_monitor_struct; + //******************************************************************* + // FUNCTION: to_monitor_struct() + // This function packs transaction variables into a fuse_ctrl_core_axi_write_out_monitor_s + // structure. The function returns the handle to the fuse_ctrl_core_axi_write_out_monitor_struct. + // This function is defined in fuse_ctrl_core_axi_write_out_macros.svh + `fuse_ctrl_core_axi_write_out_TO_MONITOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_monitor_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_core_axi_write_out_macros.svh + `fuse_ctrl_core_axi_write_out_FROM_MONITOR_STRUCT_FUNCTION + + //******************************************************************* + // Initiator macro used by fuse_ctrl_core_axi_write_out_driver and fuse_ctrl_core_axi_write_out_driver_bfm + // to communicate initiator driven data to fuse_ctrl_core_axi_write_out_driver_bfm. + // This struct is defined in fuse_ctrl_core_axi_write_out_macros.svh + `fuse_ctrl_core_axi_write_out_INITIATOR_STRUCT + fuse_ctrl_core_axi_write_out_initiator_s fuse_ctrl_core_axi_write_out_initiator_struct; + //******************************************************************* + // FUNCTION: to_initiator_struct() + // This function packs transaction variables into a fuse_ctrl_core_axi_write_out_initiator_s + // structure. The function returns the handle to the fuse_ctrl_core_axi_write_out_initiator_struct. + // This function is defined in fuse_ctrl_core_axi_write_out_macros.svh + `fuse_ctrl_core_axi_write_out_TO_INITIATOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_initiator_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_core_axi_write_out_macros.svh + `fuse_ctrl_core_axi_write_out_FROM_INITIATOR_STRUCT_FUNCTION + + //******************************************************************* + // Responder macro used by fuse_ctrl_core_axi_write_out_driver and fuse_ctrl_core_axi_write_out_driver_bfm + // to communicate Responder driven data to fuse_ctrl_core_axi_write_out_driver_bfm. + // This struct is defined in fuse_ctrl_core_axi_write_out_macros.svh + `fuse_ctrl_core_axi_write_out_RESPONDER_STRUCT + fuse_ctrl_core_axi_write_out_responder_s fuse_ctrl_core_axi_write_out_responder_struct; + //******************************************************************* + // FUNCTION: to_responder_struct() + // This function packs transaction variables into a fuse_ctrl_core_axi_write_out_responder_s + // structure. The function returns the handle to the fuse_ctrl_core_axi_write_out_responder_struct. + // This function is defined in fuse_ctrl_core_axi_write_out_macros.svh + `fuse_ctrl_core_axi_write_out_TO_RESPONDER_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_responder_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_core_axi_write_out_macros.svh + `fuse_ctrl_core_axi_write_out_FROM_RESPONDER_STRUCT_FUNCTION + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + endfunction + + // **************************************************************************** + // FUNCTION: convert2string() + // This function converts all variables in this class to a single string for + // logfile reporting. + // + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + // UVMF_CHANGE_ME : Customize format if desired. + return $sformatf("core_awready:0x%x core_wready:0x%x core_bresp:0x%x core_bid:0x%x core_bvalid:0x%x ",core_awready,core_wready,core_bresp,core_bid,core_bvalid); + // pragma uvmf custom convert2string end + endfunction + + //******************************************************************* + // FUNCTION: do_print() + // This function is automatically called when the .print() function + // is called on this class. + // + virtual function void do_print(uvm_printer printer); + // pragma uvmf custom do_print begin + // UVMF_CHANGE_ME : Current contents of do_print allows for the use of UVM 1.1d, 1.2 or P1800.2. + // Update based on your own printing preference according to your preferred UVM version + $display(convert2string()); + // pragma uvmf custom do_print end + endfunction + + //******************************************************************* + // FUNCTION: do_compare() + // This function is automatically called when the .compare() function + // is called on this class. + // + virtual function bit do_compare (uvm_object rhs, uvm_comparer comparer); + fuse_ctrl_core_axi_write_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + RHS; + if (!$cast(RHS,rhs)) return 0; + // pragma uvmf custom do_compare begin + // UVMF_CHANGE_ME : Eliminate comparison of variables not to be used for compare + return (super.do_compare(rhs,comparer) + &&(this.core_awready == RHS.core_awready) + &&(this.core_wready == RHS.core_wready) + &&(this.core_bresp == RHS.core_bresp) + &&(this.core_bid == RHS.core_bid) + &&(this.core_bvalid == RHS.core_bvalid) + ); + // pragma uvmf custom do_compare end + endfunction + + //******************************************************************* + // FUNCTION: do_copy() + // This function is automatically called when the .copy() function + // is called on this class. + // + virtual function void do_copy (uvm_object rhs); + fuse_ctrl_core_axi_write_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + RHS; + assert($cast(RHS,rhs)); + // pragma uvmf custom do_copy begin + super.do_copy(rhs); + this.core_awready = RHS.core_awready; + this.core_wready = RHS.core_wready; + this.core_bresp = RHS.core_bresp; + this.core_bid = RHS.core_bid; + this.core_bvalid = RHS.core_bvalid; + // pragma uvmf custom do_copy end + endfunction + + // **************************************************************************** + // FUNCTION: add_to_wave() + // This function is used to display variables in this class in the waveform + // viewer. The start_time and end_time variables must be set before this + // function is called. If the start_time and end_time variables are not set + // the transaction will be hidden at 0ns on the waveform display. + // + virtual function void add_to_wave(int transaction_viewing_stream_h); + `ifdef QUESTA + if (transaction_view_h == 0) begin + transaction_view_h = $begin_transaction(transaction_viewing_stream_h,"fuse_ctrl_core_axi_write_out_transaction",start_time); + end + super.add_to_wave(transaction_view_h); + // pragma uvmf custom add_to_wave begin + // UVMF_CHANGE_ME : Color can be applied to transaction entries based on content, example below + // case() + // 1 : $add_color(transaction_view_h,"red"); + // default : $add_color(transaction_view_h,"grey"); + // endcase + // UVMF_CHANGE_ME : Eliminate transaction variables not wanted in transaction viewing in the waveform viewer + $add_attribute(transaction_view_h,core_awready,"core_awready"); + $add_attribute(transaction_view_h,core_wready,"core_wready"); + $add_attribute(transaction_view_h,core_bresp,"core_bresp"); + $add_attribute(transaction_view_h,core_bid,"core_bid"); + $add_attribute(transaction_view_h,core_bvalid,"core_bvalid"); + // pragma uvmf custom add_to_wave end + $end_transaction(transaction_view_h,end_time); + $free_transaction(transaction_view_h); + `endif // QUESTA + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_transaction_coverage.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_transaction_coverage.svh new file mode 100644 index 0000000..f6e0831 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_transaction_coverage.svh @@ -0,0 +1,106 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class records fuse_ctrl_core_axi_write_out transaction information using +// a covergroup named fuse_ctrl_core_axi_write_out_transaction_cg. An instance of this +// coverage component is instantiated in the uvmf_parameterized_agent +// if the has_coverage flag is set. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_core_axi_write_out_transaction_coverage #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvm_subscriber #(.T(fuse_ctrl_core_axi_write_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +)); + + `uvm_component_param_utils( fuse_ctrl_core_axi_write_out_transaction_coverage #( + AW, + DW, + IW, + UW + ) +) + + T coverage_trans; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + covergroup fuse_ctrl_core_axi_write_out_transaction_cg; + // pragma uvmf custom covergroup begin + // UVMF_CHANGE_ME : Add coverage bins, crosses, exclusions, etc. according to coverage needs. + option.auto_bin_max=1024; + option.per_instance=1; + core_awready: coverpoint coverage_trans.core_awready; + core_wready: coverpoint coverage_trans.core_wready; + core_bresp: coverpoint coverage_trans.core_bresp; + core_bid: coverpoint coverage_trans.core_bid; + core_bvalid: coverpoint coverage_trans.core_bvalid; + // pragma uvmf custom covergroup end + endgroup + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new(string name="", uvm_component parent=null); + super.new(name,parent); + fuse_ctrl_core_axi_write_out_transaction_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that transaction variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + endfunction + + // **************************************************************************** + // FUNCTION : build_phase() + // This function is the standard UVM build_phase. + // + function void build_phase(uvm_phase phase); + fuse_ctrl_core_axi_write_out_transaction_cg.set_inst_name($sformatf("fuse_ctrl_core_axi_write_out_transaction_cg_%s",get_full_name())); + endfunction + + // **************************************************************************** + // FUNCTION: write (T t) + // This function is automatically executed when a transaction arrives on the + // analysis_export. It copies values from the variables in the transaction + // to local variables used to collect functional coverage. + // + virtual function void write (T t); + `uvm_info("COV","Received transaction",UVM_HIGH); + coverage_trans = t; + fuse_ctrl_core_axi_write_out_transaction_cg.sample(); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_typedefs.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_typedefs.svh new file mode 100644 index 0000000..f2a7bdb --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_typedefs.svh @@ -0,0 +1,34 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the host server when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_typedefs_hdl.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_typedefs_hdl.svh new file mode 100644 index 0000000..0d58518 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/src/fuse_ctrl_core_axi_write_out_typedefs_hdl.svh @@ -0,0 +1,35 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the emulator when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/yaml/fuse_ctrl_core_axi_write_out_interface.yaml b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/yaml/fuse_ctrl_core_axi_write_out_interface.yaml new file mode 100644 index 0000000..7f30cb1 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_core_axi_write_out_pkg/yaml/fuse_ctrl_core_axi_write_out_interface.yaml @@ -0,0 +1,81 @@ +uvmf: + interfaces: + fuse_ctrl_core_axi_write_out: + clock: clk_i + config_constraints: [] + config_vars: [] + existing_library_component: 'True' + gen_inbound_streaming_driver: 'False' + hdl_pkg_parameters: [] + hdl_typedefs: [] + hvl_pkg_parameters: [] + hvl_typedefs: [] + parameters: + - name: AW + type: int + value: '32' + - name: DW + type: int + value: '32' + - name: IW + type: int + value: '3' + - name: UW + type: int + value: '32' + ports: + - dir: input + name: awready + reset_value: '''bz' + width: '1' + - dir: input + name: wready + reset_value: '''bz' + width: '1' + - dir: input + name: bresp + reset_value: '''bz' + width: '[''$bits(axi_pkg::axi_burst_e)'']' + - dir: input + name: bid + reset_value: '''bz' + width: '1' + - dir: input + name: bvalid + reset_value: '''bz' + width: '1' + reset: rst_ni + reset_assertion_level: 'False' + transaction_constraints: [] + transaction_vars: + - comment: '' + iscompare: 'True' + isrand: 'False' + name: core_awready + type: logic + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'False' + name: core_wready + type: logic + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'False' + name: core_bresp + type: axi_pkg::axi_burst_e + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'False' + name: core_bid + type: logic + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'False' + name: core_bvalid + type: logic + unpacked_dimension: '' + use_dpi_link: 'False' diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/.project b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/.project new file mode 100644 index 0000000..3038bf5 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/.project @@ -0,0 +1,30 @@ + + + fuse_ctrl_in_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/.svproject b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/.svproject new file mode 100644 index 0000000..40fcc43 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/Makefile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/Makefile new file mode 100644 index 0000000..9fd3230 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/Makefile @@ -0,0 +1,66 @@ +# fuse_ctrl_in interface packages source +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +fuse_ctrl_in_PKG = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_in_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_filelist_hvl.f + +fuse_ctrl_in_PKG_HDL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_in_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_filelist_hdl.f + +fuse_ctrl_in_PKG_XRTL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_in_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_filelist_xrtl.f + +COMP_fuse_ctrl_in_PKG_TGT_0 = q_comp_fuse_ctrl_in_pkg +COMP_fuse_ctrl_in_PKG_TGT_1 = v_comp_fuse_ctrl_in_pkg +COMP_fuse_ctrl_in_PKG_TGT = $(COMP_fuse_ctrl_in_PKG_TGT_$(USE_VELOCE)) + +comp_fuse_ctrl_in_pkg: $(COMP_fuse_ctrl_in_PKG_TGT) + +q_comp_fuse_ctrl_in_pkg: + $(HDL_COMP_CMD) $(fuse_ctrl_in_PKG_HDL) + $(HVL_COMP_CMD) $(fuse_ctrl_in_PKG) + $(HDL_COMP_CMD) $(fuse_ctrl_in_PKG_XRTL) + +v_comp_fuse_ctrl_in_pkg: + $(HVL_COMP_CMD) $(fuse_ctrl_in_PKG_HDL) + $(HVL_COMP_CMD) $(fuse_ctrl_in_PKG) + $(VELANALYZE_CMD) $(fuse_ctrl_in_PKG_HDL) + $(VELANALYZE_HVL_CMD) $(fuse_ctrl_in_PKG) + $(HDL_COMP_CMD) $(fuse_ctrl_in_PKG_XRTL) + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export fuse_ctrl_in_IF_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_in_pkg/dpi + +C_FILE_COMPILE_LIST_fuse_ctrl_in_pkg = \ + +O_FILE_COMPILE_LIST_fuse_ctrl_in_pkg = $(notdir $(C_FILE_COMPILE_LIST_fuse_ctrl_in_pkg:.c=.o)) + +GCC_COMP_ARGS_fuse_ctrl_in_pkg += -I$(fuse_ctrl_in_IF_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_fuse_ctrl_in_pkg += $(fuse_ctrl_in_IF_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_fuse_ctrl_in_pkg += \ + \ + -o .so + +comp_fuse_ctrl_in_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Interface C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_fuse_ctrl_in_pkg) $(C_FILE_COMPILE_LIST_fuse_ctrl_in_pkg) + @echo "--------------------------------" + @echo "Linking Interface C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_fuse_ctrl_in_pkg) $(O_FILE_COMPILE_LIST_fuse_ctrl_in_pkg) + @echo "--------------------------------" + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/compile.do b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/compile.do new file mode 100644 index 0000000..2645839 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/compile.do @@ -0,0 +1,14 @@ +# Tcl do file for compile of fuse_ctrl_in interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_in_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_filelist_hdl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_in_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_filelist_hvl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_in_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_filelist_xrtl.f \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in.compile new file mode 100644 index 0000000..ae6ef9d --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in.compile @@ -0,0 +1,3 @@ +needs: + - fuse_ctrl_in_hvl.compile + - fuse_ctrl_in_hdl.compile diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_bfm.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_bfm.vinfo new file mode 100644 index 0000000..cf88b70 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_bfm.vinfo @@ -0,0 +1,6 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use fuse_ctrl_in_pkg_hdl.vinfo ++incdir+@vinfodir +src/fuse_ctrl_in_if.sv +src/fuse_ctrl_in_driver_bfm.sv +src/fuse_ctrl_in_monitor_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_common.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_common.compile new file mode 100644 index 0000000..82360a8 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_common.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +incdir: + - . + - ${uvm_path}/src +src: + - fuse_ctrl_in_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_filelist_hdl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_filelist_hdl.f new file mode 100644 index 0000000..959aa9e --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_filelist_hdl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_filelist_hvl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_filelist_hvl.f new file mode 100644 index 0000000..e57e74b --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_filelist_hvl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_pkg.sv \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_filelist_xrtl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_filelist_xrtl.f new file mode 100644 index 0000000..1e9819e --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_filelist_xrtl.f @@ -0,0 +1,3 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_if.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_monitor_bfm.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_driver_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_hdl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_hdl.compile new file mode 100644 index 0000000..da38bec --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_hdl.compile @@ -0,0 +1,9 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ./fuse_ctrl_in_common.compile +incdir: + - . +src: + - src/fuse_ctrl_in_if.sv + - src/fuse_ctrl_in_monitor_bfm.sv + - src/fuse_ctrl_in_driver_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_hvl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_hvl.compile new file mode 100644 index 0000000..210102c --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_hvl.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ./fuse_ctrl_in_common.compile +incdir: + - . +src: + - fuse_ctrl_in_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_pkg.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_pkg.sv new file mode 100644 index 0000000..58df769 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_pkg.sv @@ -0,0 +1,91 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - + +// - +// - +// - + +// - +// - +// - + +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_in_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg_hdl::*; + import uvmf_base_pkg::*; + import fuse_ctrl_in_pkg_hdl::*; + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + `include "src/fuse_ctrl_in_macros.svh" + + export fuse_ctrl_in_pkg_hdl::*; + + + + // Parameters defined as HVL parameters + + `include "src/fuse_ctrl_in_typedefs.svh" + `include "src/fuse_ctrl_in_transaction.svh" + + `include "src/fuse_ctrl_in_configuration.svh" + `include "src/fuse_ctrl_in_driver.svh" + `include "src/fuse_ctrl_in_monitor.svh" + + `include "src/fuse_ctrl_in_transaction_coverage.svh" + `include "src/fuse_ctrl_in_sequence_base.svh" + `include "src/fuse_ctrl_in_random_sequence.svh" + + `include "src/fuse_ctrl_in_responder_sequence.svh" + `include "src/fuse_ctrl_in2reg_adapter.svh" + + `include "src/fuse_ctrl_in_agent.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new interface sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the interface package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_pkg.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_pkg.vinfo new file mode 100644 index 0000000..164f125 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_pkg.vinfo @@ -0,0 +1,4 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use fuse_ctrl_in_pkg_hdl.vinfo ++incdir+@vinfodir +fuse_ctrl_in_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_pkg_hdl.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_pkg_hdl.sv new file mode 100644 index 0000000..b13dcf7 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_pkg_hdl.sv @@ -0,0 +1,52 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that needs to be compiled and synthesized +// for running on Veloce. +// +// CONTAINS: +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_in_pkg_hdl; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HDL parameters + + `include "src/fuse_ctrl_in_typedefs_hdl.svh" + `include "src/fuse_ctrl_in_macros.svh" + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_pkg_hdl.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_pkg_hdl.vinfo new file mode 100644 index 0000000..79de2ad --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_pkg_hdl.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +fuse_ctrl_in_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_pkg_sve.F b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_pkg_sve.F new file mode 100644 index 0000000..345b7e8 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_pkg_sve.F @@ -0,0 +1,10 @@ +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + ++incdir+. +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_filelist_hdl.f +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_in_pkg/fuse_ctrl_in_filelist_hvl.f diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in2reg_adapter.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in2reg_adapter.svh new file mode 100644 index 0000000..1f5c433 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in2reg_adapter.svh @@ -0,0 +1,142 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the UVM register adapter for the fuse_ctrl_in interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_in2reg_adapter #( + int AlertSyncOn = 3, + caliptra_otp_ctrl_pkg::lfsr_seed_t RndConstLfrSeed = caliptra_otp_ctrl_pkg::RndCnstLfsrSeedDefault, + caliptra_otp_ctrl_pkg::lfsr_perm_t RndCnstLfsrPerm = caliptra_otp_ctrl_pkg::RndCnstLfsrPermDefault, + string MemInitFile = "/home/ws/caliptra/anjpar/ws1/chipsalliance/caliptra-rtl/src/fuse_ctrl/data/otp-img.2048.vmem" + ) + extends uvm_reg_adapter; + + `uvm_object_param_utils( fuse_ctrl_in2reg_adapter #( + AlertSyncOn, + RndConstLfrSeed, + RndCnstLfsrPerm, + MemInitFile + ) +) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //-------------------------------------------------------------------- + // new + //-------------------------------------------------------------------- + function new (string name = "fuse_ctrl_in2reg_adapter" ); + super.new(name); + // pragma uvmf custom new begin + // UVMF_CHANGE_ME : Configure the adapter regarding byte enables and provides response. + + // Does the protocol the Agent is modeling support byte enables? + // 0 = NO + // 1 = YES + supports_byte_enable = 0; + + // Does the Agent's Driver provide separate response sequence items? + // i.e. Does the driver call seq_item_port.put() + // and do the sequences call get_response()? + // 0 = NO + // 1 = YES + provides_responses = 0; + // pragma uvmf custom new end + + endfunction: new + + //-------------------------------------------------------------------- + // reg2bus + //-------------------------------------------------------------------- + virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw); + + fuse_ctrl_in_transaction #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) + trans_h = fuse_ctrl_in_transaction #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) +::type_id::create("trans_h"); + + // pragma uvmf custom reg2bus begin + // UVMF_CHANGE_ME : Fill in the reg2bus adapter mapping registe fields to protocol fields. + + //Adapt the following for your sequence item type + // trans_h.op = (rw.kind == UVM_READ) ? WB_READ : WB_WRITE; + //Copy over address + // trans_h.addr = rw.addr; + //Copy over write data + // trans_h.data = rw.data; + + // pragma uvmf custom reg2bus end + + // Return the adapted transaction + return trans_h; + + endfunction: reg2bus + + //-------------------------------------------------------------------- + // bus2reg + //-------------------------------------------------------------------- + virtual function void bus2reg(uvm_sequence_item bus_item, + ref uvm_reg_bus_op rw); + fuse_ctrl_in_transaction #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) + trans_h; + if (!$cast(trans_h, bus_item)) begin + `uvm_fatal("ADAPT","Provided bus_item is not of the correct type") + return; + end + // pragma uvmf custom bus2reg begin + // UVMF_CHANGE_ME : Fill in the bus2reg adapter mapping protocol fields to register fields. + //Adapt the following for your sequence item type + //Copy over instruction type + // rw.kind = (trans_h.op == WB_WRITE) ? UVM_WRITE : UVM_READ; + //Copy over address + // rw.addr = trans_h.addr; + //Copy over read data + // rw.data = trans_h.data; + //Check for errors on the bus and return UVM_NOT_OK if there is an error + // rw.status = UVM_IS_OK; + // pragma uvmf custom bus2reg end + + endfunction: bus2reg + +endclass : fuse_ctrl_in2reg_adapter + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_agent.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_agent.svh new file mode 100644 index 0000000..c03c6fb --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_agent.svh @@ -0,0 +1,109 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: Protocol specific agent class definition +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_in_agent #( + int AlertSyncOn = 3, + caliptra_otp_ctrl_pkg::lfsr_seed_t RndConstLfrSeed = caliptra_otp_ctrl_pkg::RndCnstLfsrSeedDefault, + caliptra_otp_ctrl_pkg::lfsr_perm_t RndCnstLfsrPerm = caliptra_otp_ctrl_pkg::RndCnstLfsrPermDefault, + string MemInitFile = "/home/ws/caliptra/anjpar/ws1/chipsalliance/caliptra-rtl/src/fuse_ctrl/data/otp-img.2048.vmem" + ) + extends uvmf_parameterized_agent #( + .CONFIG_T(fuse_ctrl_in_configuration #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) +), + .DRIVER_T(fuse_ctrl_in_driver #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) +), + .MONITOR_T(fuse_ctrl_in_monitor #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) +), + .COVERAGE_T(fuse_ctrl_in_transaction_coverage #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) +), + .TRANS_T(fuse_ctrl_in_transaction #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) +) + ); + + `uvm_component_param_utils( fuse_ctrl_in_agent #( + AlertSyncOn, + RndConstLfrSeed, + RndCnstLfsrPerm, + MemInitFile + ) +) + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** + // FUNCTION: build_phase + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + if (configuration.active_passive == ACTIVE) begin + // Place sequencer handle into configuration object + // so that it may be retrieved from configuration + // rather than using uvm_config_db + configuration.sequencer = this.sequencer; + end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_configuration.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_configuration.svh new file mode 100644 index 0000000..31aac40 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_configuration.svh @@ -0,0 +1,241 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class contains all variables and functions used +// to configure the fuse_ctrl_in agent and its bfm's. It gets the +// bfm's from the uvm_config_db for use by the agent. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_in_configuration #( + int AlertSyncOn = 3, + caliptra_otp_ctrl_pkg::lfsr_seed_t RndConstLfrSeed = caliptra_otp_ctrl_pkg::RndCnstLfsrSeedDefault, + caliptra_otp_ctrl_pkg::lfsr_perm_t RndCnstLfsrPerm = caliptra_otp_ctrl_pkg::RndCnstLfsrPermDefault, + string MemInitFile = "/home/ws/caliptra/anjpar/ws1/chipsalliance/caliptra-rtl/src/fuse_ctrl/data/otp-img.2048.vmem" + ) + extends uvmf_parameterized_agent_configuration_base #( + .DRIVER_BFM_BIND_T(virtual fuse_ctrl_in_driver_bfm #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) +), + .MONITOR_BFM_BIND_T( virtual fuse_ctrl_in_monitor_bfm #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) +)); + + `uvm_object_param_utils( fuse_ctrl_in_configuration #( + AlertSyncOn, + RndConstLfrSeed, + RndCnstLfsrPerm, + MemInitFile + ) +) + + + // Sequencer handle populated by agent + uvm_sequencer #(fuse_ctrl_in_transaction #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) + ) sequencer; + + //Constraints for the configuration variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + covergroup fuse_ctrl_in_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + // pragma uvmf custom covergroup end + endgroup + + //******************************************************************* + //******************************************************************* + // Structure used to pass configuration variables to monitor and driver BFM's. + // Use to_struct function to pack variables into structure. + // Use from_struct function to unpack variables from structure. + // This structure is defined in fuse_ctrl_in_macros.svh + `fuse_ctrl_in_CONFIGURATION_STRUCT + fuse_ctrl_in_configuration_s fuse_ctrl_in_configuration_struct; + //******************************************************************* + // FUNCTION: to_struct() + // This function packs variables into a fuse_ctrl_in_configuration_s + // structure. The function returns the handle to the fuse_ctrl_in_configuration_struct. + // This function is defined in fuse_ctrl_in_macros.svh + `fuse_ctrl_in_CONFIGURATION_TO_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_struct() + // This function unpacks the struct provided as an argument into + // variables of this class. + // This function is defined in fuse_ctrl_in_macros.svh + `fuse_ctrl_in_CONFIGURATION_FROM_STRUCT_FUNCTION + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + // Construct the covergroup for this configuration class + fuse_ctrl_in_configuration_cg = new; + endfunction + + // **************************************************************************** + // FUNCTION: post_randomize() + // This function is automatically called after the randomize() function + // is executed. + // + function void post_randomize(); + super.post_randomize(); + fuse_ctrl_in_configuration_cg.sample(); + endfunction + + // **************************************************************************** + // FUNCTION: initialize + // This function causes the configuration to retrieve + // its virtual interface handle from the uvm_config_db. + // This function also makes itself available to its + // agent through the uvm_config_db. + // + // ARGUMENTS: + // uvmf_active_passive_t activity: + // This argument identifies the simulation level + // as either BLOCK, CHIP, SIMULATION, etc. + // + // AGENT_PATH: + // This argument identifies the path to this + // configurations agent. This configuration + // makes itself available to the agent specified + // by agent_path by placing itself into the + // uvm_config_db. + // + // INTERFACE_NAME: + // This argument identifies the string name of + // this configurations BFM's. This string + // name is used to retrieve the driver and + // monitor BFM from the uvm_config_db. + // + virtual function void initialize(uvmf_active_passive_t activity, + string agent_path, + string interface_name); + + super.initialize( activity, agent_path, interface_name); + // The covergroup is given the same name as the interface + fuse_ctrl_in_configuration_cg.set_inst_name(interface_name); + + // This configuration places itself into the uvm_config_db for the agent, identified by the agent_path variable, to retrieve. + uvm_config_db #( fuse_ctrl_in_configuration #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) + + )::set( null ,agent_path,UVMF_AGENT_CONFIG, this ); + + // This configuration also places itself in the config db using the same identifier used by the interface. This allows users to access + // configuration variables and the interface through the bfm api class rather than directly accessing the BFM. This is useful for + // accessingthe BFM when using Veloce + uvm_config_db #( fuse_ctrl_in_configuration #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) + + )::set( null ,UVMF_CONFIGURATIONS, interface_name, this ); + + fuse_ctrl_in_configuration_cg.set_inst_name($sformatf("fuse_ctrl_in_configuration_cg_%s",get_full_name())); + +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. + `uvm_info("CFG", + $psprintf("The agent at '%s' is using interface named %s has the following parameters: AlertSyncOn=%x RndConstLfrSeed=%x RndCnstLfsrPerm=%x MemInitFile=%x ", agent_path, interface_name, AlertSyncOn ,RndConstLfrSeed ,RndCnstLfsrPerm ,MemInitFile ), + UVM_DEBUG) + + // pragma uvmf custom initialize begin + // This controls whether or not the agent returns a transaction handle in the driver when calling + // item_done() back into the sequencer or not. If set to 1, a transaction is sent back which means + // the sequence on the other end must use the get_response() part of the driver/sequence API. If + // this doesn't occur, there will eventually be response_queue overflow errors during the test. + return_transaction_response = 1'b0; + + // pragma uvmf custom initialize end + + endfunction + + // **************************************************************************** + // TASK: wait_for_reset + // *[Required]* Blocks until reset is released. The wait_for_reset operation is performed + // by a task in the monitor bfm. + virtual task wait_for_reset(); + monitor_bfm.wait_for_reset(); + endtask + + // **************************************************************************** + // TASK: wait_for_num_clocks + // *[Required]* Blocks until specified number of clocks have elapsed. The wait_for_num_clocks + // operation is performed by a task in the monitor bfm. + virtual task wait_for_num_clocks(int clocks); + monitor_bfm.wait_for_num_clocks(clocks); + endtask + + // **************************************************************************** + // FUNCTION : convert2string() + // This function is used to convert variables in this class into a string for log messaging. + // + virtual function string convert2string (); + // pragma uvmf custom convert2string begin + return $sformatf(""); + // pragma uvmf custom convert2string end + endfunction + + // **************************************************************************** + // FUNCTION: get_sequencer + function uvm_sequencer #(fuse_ctrl_in_transaction#( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) +) get_sequencer(); + return sequencer; + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_driver.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_driver.svh new file mode 100644 index 0000000..4a96de8 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_driver.svh @@ -0,0 +1,141 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class passes transactions between the sequencer +// and the BFM driver interface. It accesses the driver BFM +// through the bfm handle. This driver +// passes transactions to the driver BFM through the access +// task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_in_driver #( + int AlertSyncOn = 3, + caliptra_otp_ctrl_pkg::lfsr_seed_t RndConstLfrSeed = caliptra_otp_ctrl_pkg::RndCnstLfsrSeedDefault, + caliptra_otp_ctrl_pkg::lfsr_perm_t RndCnstLfsrPerm = caliptra_otp_ctrl_pkg::RndCnstLfsrPermDefault, + string MemInitFile = "/home/ws/caliptra/anjpar/ws1/chipsalliance/caliptra-rtl/src/fuse_ctrl/data/otp-img.2048.vmem" + ) + extends uvmf_driver_base #( + .CONFIG_T(fuse_ctrl_in_configuration #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) + ), + .BFM_BIND_T(virtual fuse_ctrl_in_driver_bfm #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) + ), + .REQ(fuse_ctrl_in_transaction #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) + ), + .RSP(fuse_ctrl_in_transaction #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) + )); + + `uvm_component_param_utils( fuse_ctrl_in_driver #( + AlertSyncOn, + RndConstLfrSeed, + RndCnstLfsrPerm, + MemInitFile + ) +) +//******************************************************************* +// Macros that define structs located in fuse_ctrl_in_macros.svh +//******************************************************************* +// Initiator macro used by fuse_ctrl_in_driver and fuse_ctrl_in_driver_bfm +// to communicate initiator driven data to fuse_ctrl_in_driver_bfm. +`fuse_ctrl_in_INITIATOR_STRUCT + fuse_ctrl_in_initiator_s fuse_ctrl_in_initiator_struct; +//******************************************************************* +// Responder macro used by fuse_ctrl_in_driver and fuse_ctrl_in_driver_bfm +// to communicate Responder driven data to fuse_ctrl_in_driver_bfm. +`fuse_ctrl_in_RESPONDER_STRUCT + fuse_ctrl_in_responder_s fuse_ctrl_in_responder_struct; + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent=null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the driver BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// driver BFM. This allows the driver BFM to call tasks and function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// **************************************************************************** +// This task is called by the run_phase in uvmf_driver_base. + virtual task access( inout REQ txn ); +// pragma uvmf custom access begin + if (configuration.initiator_responder==RESPONDER) begin + // Complete current transfer and wait for next transfer + bfm.respond_and_wait_for_next_transfer( + fuse_ctrl_in_initiator_struct, + txn.to_responder_struct() + ); + // Unpack information about initiated transfer received by this responder + txn.from_initiator_struct(fuse_ctrl_in_initiator_struct); + end else begin + // Initiate a transfer and get response + bfm.initiate_and_get_response( + txn.to_initiator_struct(), + fuse_ctrl_in_responder_struct + ); + // Unpack transfer response information received by this initiator + txn.from_responder_struct(fuse_ctrl_in_responder_struct); + end +// pragma uvmf custom access end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_driver_bfm.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_driver_bfm.sv new file mode 100644 index 0000000..e82cd60 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_driver_bfm.sv @@ -0,0 +1,342 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This interface performs the fuse_ctrl_in signal driving. It is +// accessed by the uvm fuse_ctrl_in driver through a virtual interface +// handle in the fuse_ctrl_in configuration. It drives the singals passed +// in through the port connection named bus of type fuse_ctrl_in_if. +// +// Input signals from the fuse_ctrl_in_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// This bfm drives signals with a _o suffix. These signals +// are driven onto signals within fuse_ctrl_in_if based on INITIATOR/RESPONDER and/or +// ARBITRATION/GRANT status. +// +// The output signal connections are as follows: +// signal_o -> bus.signal +// +// +// Interface functions and tasks used by UVM components: +// +// configure: +// This function gets configuration attributes from the +// UVM driver to set any required BFM configuration +// variables such as 'initiator_responder'. +// +// initiate_and_get_response: +// This task is used to perform signaling activity for initiating +// a protocol transfer. The task initiates the transfer, using +// input data from the initiator struct. Then the task captures +// response data, placing the data into the response struct. +// The response struct is returned to the driver class. +// +// respond_and_wait_for_next_transfer: +// This task is used to complete a current transfer as a responder +// and then wait for the initiator to start the next transfer. +// The task uses data in the responder struct to drive protocol +// signals to complete the transfer. The task then waits for +// the next transfer. Once the next transfer begins, data from +// the initiator is placed into the initiator struct and sent +// to the responder sequence for processing to determine +// what data to respond with. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_in_pkg_hdl::*; +`include "src/fuse_ctrl_in_macros.svh" + +interface fuse_ctrl_in_driver_bfm #( + int AlertSyncOn = 3, + caliptra_otp_ctrl_pkg::lfsr_seed_t RndConstLfrSeed = caliptra_otp_ctrl_pkg::RndCnstLfsrSeedDefault, + caliptra_otp_ctrl_pkg::lfsr_perm_t RndCnstLfsrPerm = caliptra_otp_ctrl_pkg::RndCnstLfsrPermDefault, + string MemInitFile = "/home/ws/caliptra/anjpar/ws1/chipsalliance/caliptra-rtl/src/fuse_ctrl/data/otp-img.2048.vmem" + ) + + (fuse_ctrl_in_if bus); + // The following pragma and additional ones in-lined further below are for running this BFM on Veloce + // pragma attribute fuse_ctrl_in_driver_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: AlertSyncOn=%x RndConstLfrSeed=%x RndCnstLfsrPerm=%x MemInitFile=%x ", AlertSyncOn,RndConstLfrSeed,RndCnstLfsrPerm,MemInitFile), + UVM_DEBUG) +end +`endif + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + tri clk_i_i; + tri rst_ni_i; + + // Signal list (all signals are capable of being inputs and outputs for the sake + // of supporting both INITIATOR and RESPONDER mode operation. Expectation is that + // directionality in the config file was from the point-of-view of the INITIATOR + + // INITIATOR mode input signals + + // INITIATOR mode output signals + tri [$bits(edn_pkg::edn_req_t)-1:0] edn_i_i; + reg [$bits(edn_pkg::edn_req_t)-1:0] edn_i_o = 'bz; + tri [ast_pkg::NumAlerts * $bits(caliptra_prim_alert_pkg::alert_rx_t)-1:0] alert_rx_i_i; + reg [ast_pkg::NumAlerts * $bits(caliptra_prim_alert_pkg::alert_rx_t)-1:0] alert_rx_i_o = 'bz; + tri [$bits(ast_pkg::ast_obs_ctrl_t)-1:0] obs_ctrl_i_i; + reg [$bits(ast_pkg::ast_obs_ctrl_t)-1:0] obs_ctrl_i_o = 'bz; + tri [$bits(caliptra_otp_ctrl_pkg::otp_ast_req_t)-1:0] otp_ast_pwr_seq_h_i_i; + reg [$bits(caliptra_otp_ctrl_pkg::otp_ast_req_t)-1:0] otp_ast_pwr_seq_h_i_o = 'bz; + tri scan_en_i_i; + reg scan_en_i_o = 'bz; + tri scan_rst_ni_i; + reg scan_rst_ni_o = 'bz; + tri scanmode_i_i; + reg scanmode_i_o = 'bz; + + // Bi-directional signals + + + assign clk_i_i = bus.clk_i; + assign rst_ni_i = bus.rst_ni; + + // These are signals marked as 'input' by the config file, but the signals will be + // driven by this BFM if put into RESPONDER mode (flipping all signal directions around) + + + // These are signals marked as 'output' by the config file, but the outputs will + // not be driven by this BFM unless placed in INITIATOR mode. + assign bus.edn_i = (initiator_responder == INITIATOR) ? edn_i_o : 'bz; + assign edn_i_i = bus.edn_i; + assign bus.alert_rx_i = (initiator_responder == INITIATOR) ? alert_rx_i_o : 'bz; + assign alert_rx_i_i = bus.alert_rx_i; + assign bus.obs_ctrl_i = (initiator_responder == INITIATOR) ? obs_ctrl_i_o : 'bz; + assign obs_ctrl_i_i = bus.obs_ctrl_i; + assign bus.otp_ast_pwr_seq_h_i = (initiator_responder == INITIATOR) ? otp_ast_pwr_seq_h_i_o : 'bz; + assign otp_ast_pwr_seq_h_i_i = bus.otp_ast_pwr_seq_h_i; + assign bus.scan_en_i = (initiator_responder == INITIATOR) ? scan_en_i_o : 'bz; + assign scan_en_i_i = bus.scan_en_i; + assign bus.scan_rst_ni = (initiator_responder == INITIATOR) ? scan_rst_ni_o : 'bz; + assign scan_rst_ni_i = bus.scan_rst_ni; + assign bus.scanmode_i = (initiator_responder == INITIATOR) ? scanmode_i_o : 'bz; + assign scanmode_i_i = bus.scanmode_i; + + // Proxy handle to UVM driver + fuse_ctrl_in_pkg::fuse_ctrl_in_driver #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) + proxy; + // pragma tbx oneway proxy.my_function_name_in_uvm_driver + + // **************************************************************************** + // **************************************************************************** + // Macros that define structs located in fuse_ctrl_in_macros.svh + // **************************************************************************** + // Struct for passing configuration data from fuse_ctrl_in_driver to this BFM + // **************************************************************************** + `fuse_ctrl_in_CONFIGURATION_STRUCT + // **************************************************************************** + // Structs for INITIATOR and RESPONDER data flow + //******************************************************************* + // Initiator macro used by fuse_ctrl_in_driver and fuse_ctrl_in_driver_bfm + // to communicate initiator driven data to fuse_ctrl_in_driver_bfm. + `fuse_ctrl_in_INITIATOR_STRUCT + fuse_ctrl_in_initiator_s initiator_struct; + // Responder macro used by fuse_ctrl_in_driver and fuse_ctrl_in_driver_bfm + // to communicate Responder driven data to fuse_ctrl_in_driver_bfm. + `fuse_ctrl_in_RESPONDER_STRUCT + fuse_ctrl_in_responder_s responder_struct; + + // **************************************************************************** +// pragma uvmf custom reset_condition_and_response begin + // Always block used to return signals to reset value upon assertion of reset + always @( negedge rst_ni_i ) + begin + // RESPONDER mode output signals + // INITIATOR mode output signals + edn_i_o <= 'bz; + alert_rx_i_o <= 'bz; + obs_ctrl_i_o <= 'bz; + otp_ast_pwr_seq_h_i_o <= 'bz; + //otp_ext_voltage_h_io_o <= 'bz; + scan_en_i_o <= 'bz; + scan_rst_ni_o <= 'bz; + scanmode_i_o <= 'bz; + // Bi-directional signals + + end +// pragma uvmf custom reset_condition_and_response end + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the driver BFM. It is called by the driver within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the driver BFM needs to be aware of the new configuration + // variables. + // + + function void configure(fuse_ctrl_in_configuration_s fuse_ctrl_in_configuration_arg); // pragma tbx xtf + initiator_responder = fuse_ctrl_in_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + +// pragma uvmf custom initiate_and_get_response begin +// **************************************************************************** +// UVMF_CHANGE_ME +// This task is used by an initator. The task first initiates a transfer then +// waits for the responder to complete the transfer. + task initiate_and_get_response( + // This argument passes transaction variables used by an initiator + // to perform the initial part of a protocol transfer. The values + // come from a sequence item created in a sequence. + input fuse_ctrl_in_initiator_s fuse_ctrl_in_initiator_struct, + // This argument is used to send data received from the responder + // back to the sequence item. The sequence item is returned to the sequence. + output fuse_ctrl_in_responder_s fuse_ctrl_in_responder_struct + );// pragma tbx xtf + // + // Members within the fuse_ctrl_in_initiator_struct: + // caliptra_prim_alert_pkg::alert_rx_t set_alert_rx_i ; + // Members within the fuse_ctrl_in_responder_struct: + // caliptra_prim_alert_pkg::alert_rx_t set_alert_rx_i ; + initiator_struct = fuse_ctrl_in_initiator_struct; + // + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clk_i_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available initiator input and inout signals listed. + // Initiator input signals + // Initiator inout signals + // How to assign a signal from an initiator struct member named xyz. + // All available initiator output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Initiator output signals + // edn_i_o <= fuse_ctrl_in_initiator_struct.xyz; // [$bits(edn_pkg::edn_req_t)-1:0] + // alert_rx_i_o <= fuse_ctrl_in_initiator_struct.xyz; // [NumAlerts * $bits(caliptra_prim_alert_pkg::alert_rx_t)-1:0] + // obs_ctrl_i_o <= fuse_ctrl_in_initiator_struct.xyz; // [$bits(ast_pkg::ast_obs_ctrl_t)-1:0] + // otp_ast_pwr_seq_h_i_o <= fuse_ctrl_in_initiator_struct.xyz; // [$bits(otp_ast_req_t)-1:0] + // otp_ext_voltage_h_io_o <= fuse_ctrl_in_initiator_struct.xyz; // + // scan_en_i_o <= fuse_ctrl_in_initiator_struct.xyz; // + // scan_rst_ni_o <= fuse_ctrl_in_initiator_struct.xyz; // + // scanmode_i_o <= fuse_ctrl_in_initiator_struct.xyz; // + // Initiator inout signals + // Initiate a transfer using the data received. + @(posedge clk_i_i); + @(posedge clk_i_i); + // Wait for the responder to complete the transfer then place the responder data into + // fuse_ctrl_in_responder_struct. + @(posedge clk_i_i); + @(posedge clk_i_i); + responder_struct = fuse_ctrl_in_responder_struct; + endtask +// pragma uvmf custom initiate_and_get_response end + +// pragma uvmf custom respond_and_wait_for_next_transfer begin +// **************************************************************************** +// The first_transfer variable is used to prevent completing a transfer in the +// first call to this task. For the first call to this task, there is not +// current transfer to complete. +bit first_transfer=1; + +// UVMF_CHANGE_ME +// This task is used by a responder. The task first completes the current +// transfer in progress then waits for the initiator to start the next transfer. + task respond_and_wait_for_next_transfer( + // This argument is used to send data received from the initiator + // back to the sequence item. The sequence determines how to respond. + output fuse_ctrl_in_initiator_s fuse_ctrl_in_initiator_struct, + // This argument passes transaction variables used by a responder + // to complete a protocol transfer. The values come from a sequence item. + input fuse_ctrl_in_responder_s fuse_ctrl_in_responder_struct + );// pragma tbx xtf + // Variables within the fuse_ctrl_in_initiator_struct: + // caliptra_prim_alert_pkg::alert_rx_t set_alert_rx_i ; + // Variables within the fuse_ctrl_in_responder_struct: + // caliptra_prim_alert_pkg::alert_rx_t set_alert_rx_i ; + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clk_i_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available responder input and inout signals listed. + // Responder input signals + // fuse_ctrl_in_responder_struct.xyz = edn_i_i; // [$bits(edn_pkg::edn_req_t)-1:0] + // fuse_ctrl_in_responder_struct.xyz = alert_rx_i_i; // [NumAlerts * $bits(caliptra_prim_alert_pkg::alert_rx_t)-1:0] + // fuse_ctrl_in_responder_struct.xyz = obs_ctrl_i_i; // [$bits(ast_pkg::ast_obs_ctrl_t)-1:0] + // fuse_ctrl_in_responder_struct.xyz = otp_ast_pwr_seq_h_i_i; // [$bits(otp_ast_req_t)-1:0] + // fuse_ctrl_in_responder_struct.xyz = otp_ext_voltage_h_io_i; // + // fuse_ctrl_in_responder_struct.xyz = scan_en_i_i; // + // fuse_ctrl_in_responder_struct.xyz = scan_rst_ni_i; // + // fuse_ctrl_in_responder_struct.xyz = scanmode_i_i; // + // Responder inout signals + // How to assign a signal, named xyz, from an initiator struct member. + // All available responder output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Responder output signals + // Responder inout signals + + @(posedge clk_i_i); + if (!first_transfer) begin + // Perform transfer response here. + // Reply using data recieved in the fuse_ctrl_in_responder_struct. + @(posedge clk_i_i); + // Reply using data recieved in the transaction handle. + @(posedge clk_i_i); + end + // Wait for next transfer then gather info from intiator about the transfer. + // Place the data into the fuse_ctrl_in_initiator_struct. + @(posedge clk_i_i); + @(posedge clk_i_i); + first_transfer = 0; + endtask +// pragma uvmf custom respond_and_wait_for_next_transfer end + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_if.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_if.sv new file mode 100644 index 0000000..3a674ce --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_if.sv @@ -0,0 +1,114 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface contains the fuse_ctrl_in interface signals. +// It is instantiated once per fuse_ctrl_in bus. Bus Functional Models, +// BFM's named fuse_ctrl_in_driver_bfm, are used to drive signals on the bus. +// BFM's named fuse_ctrl_in_monitor_bfm are used to monitor signals on the +// bus. This interface signal bundle is passed in the port list of +// the BFM in order to give the BFM access to the signals in this +// interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// This template can be used to connect a DUT to these signals +// +// .dut_signal_port(fuse_ctrl_in_bus.edn_i), // Agent output +// .dut_signal_port(fuse_ctrl_in_bus.alert_rx_i), // Agent output +// .dut_signal_port(fuse_ctrl_in_bus.obs_ctrl_i), // Agent output +// .dut_signal_port(fuse_ctrl_in_bus.otp_ast_pwr_seq_h_i), // Agent output +// .dut_signal_port(fuse_ctrl_in_bus.scan_en_i), // Agent output +// .dut_signal_port(fuse_ctrl_in_bus.scan_rst_ni), // Agent output +// .dut_signal_port(fuse_ctrl_in_bus.scanmode_i), // Agent output + +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_in_pkg_hdl::*; + +interface fuse_ctrl_in_if #( + int AlertSyncOn = 3, + caliptra_otp_ctrl_pkg::lfsr_seed_t RndConstLfrSeed = caliptra_otp_ctrl_pkg::RndCnstLfsrSeedDefault, + caliptra_otp_ctrl_pkg::lfsr_perm_t RndCnstLfsrPerm = caliptra_otp_ctrl_pkg::RndCnstLfsrPermDefault, + string MemInitFile = "/home/ws/caliptra/anjpar/ws1/chipsalliance/caliptra-rtl/src/fuse_ctrl/data/otp-img.2048.vmem" + ) + + + ( + input tri clk_i, + input tri rst_ni, + inout tri [$bits(edn_pkg::edn_req_t)-1:0] edn_i, + inout tri [ast_pkg::NumAlerts * $bits(caliptra_prim_alert_pkg::alert_rx_t)-1:0] alert_rx_i, + inout tri [$bits(ast_pkg::ast_obs_ctrl_t)-1:0] obs_ctrl_i, + inout tri [$bits(caliptra_otp_ctrl_pkg::otp_ast_req_t)-1:0] otp_ast_pwr_seq_h_i, + inout tri scan_en_i, + inout tri scan_rst_ni, + inout tri scanmode_i + ); + +modport monitor_port + ( + input clk_i, + input rst_ni, + input edn_i, + input alert_rx_i, + input obs_ctrl_i, + input otp_ast_pwr_seq_h_i, + input scan_en_i, + input scan_rst_ni, + input scanmode_i + ); + +modport initiator_port + ( + input clk_i, + input rst_ni, + output edn_i, + output alert_rx_i, + output obs_ctrl_i, + output otp_ast_pwr_seq_h_i, + output scan_en_i, + output scan_rst_ni, + output scanmode_i + ); + +modport responder_port + ( + input clk_i, + input rst_ni, + input edn_i, + input alert_rx_i, + input obs_ctrl_i, + input otp_ast_pwr_seq_h_i, + input scan_en_i, + input scan_rst_ni, + input scanmode_i + ); + + +// pragma uvmf custom interface_item_additional begin +// pragma uvmf custom interface_item_additional end + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_infact_coverage_strategy.csv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_infact_coverage_strategy.csv new file mode 100644 index 0000000..1c218e1 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_infact_coverage_strategy.csv @@ -0,0 +1,6 @@ +Global +auto_bin_max, 64 + +Name,Type,Include +rand_fields,coverpoint,=rand *.** + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_macros.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_macros.svh new file mode 100644 index 0000000..cf85634 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_macros.svh @@ -0,0 +1,135 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains macros used with the fuse_ctrl_in package. +// These macros include packed struct definitions. These structs are +// used to pass data between classes, hvl, and BFM's, hdl. Use of +// structs are more efficient and simpler to modify. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_struct +// and from_struct methods defined in the macros below that are used in +// the fuse_ctrl_in_configuration class. +// + `define fuse_ctrl_in_CONFIGURATION_STRUCT \ +typedef struct packed { \ + uvmf_active_passive_t active_passive; \ + uvmf_initiator_responder_t initiator_responder; \ + } fuse_ctrl_in_configuration_s; + + `define fuse_ctrl_in_CONFIGURATION_TO_STRUCT_FUNCTION \ + virtual function fuse_ctrl_in_configuration_s to_struct();\ + fuse_ctrl_in_configuration_struct = \ + {\ + this.active_passive,\ + this.initiator_responder\ + };\ + return ( fuse_ctrl_in_configuration_struct );\ + endfunction + + `define fuse_ctrl_in_CONFIGURATION_FROM_STRUCT_FUNCTION \ + virtual function void from_struct(fuse_ctrl_in_configuration_s fuse_ctrl_in_configuration_struct);\ + {\ + this.active_passive,\ + this.initiator_responder \ + } = fuse_ctrl_in_configuration_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_monitor_struct +// and from_monitor_struct methods of the fuse_ctrl_in_transaction class. +// + `define fuse_ctrl_in_MONITOR_STRUCT typedef struct packed { \ + caliptra_prim_alert_pkg::alert_rx_t set_alert_rx_i ; \ + } fuse_ctrl_in_monitor_s; + + `define fuse_ctrl_in_TO_MONITOR_STRUCT_FUNCTION \ + virtual function fuse_ctrl_in_monitor_s to_monitor_struct();\ + fuse_ctrl_in_monitor_struct = \ + { \ + this.set_alert_rx_i \ + };\ + return ( fuse_ctrl_in_monitor_struct);\ + endfunction\ + + `define fuse_ctrl_in_FROM_MONITOR_STRUCT_FUNCTION \ + virtual function void from_monitor_struct(fuse_ctrl_in_monitor_s fuse_ctrl_in_monitor_struct);\ + {\ + this.set_alert_rx_i \ + } = fuse_ctrl_in_monitor_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_initiator_struct +// and from_initiator_struct methods of the fuse_ctrl_in_transaction class. +// Also update the comments in the driver BFM. +// + `define fuse_ctrl_in_INITIATOR_STRUCT typedef struct packed { \ + caliptra_prim_alert_pkg::alert_rx_t set_alert_rx_i ; \ + } fuse_ctrl_in_initiator_s; + + `define fuse_ctrl_in_TO_INITIATOR_STRUCT_FUNCTION \ + virtual function fuse_ctrl_in_initiator_s to_initiator_struct();\ + fuse_ctrl_in_initiator_struct = \ + {\ + this.set_alert_rx_i \ + };\ + return ( fuse_ctrl_in_initiator_struct);\ + endfunction + + `define fuse_ctrl_in_FROM_INITIATOR_STRUCT_FUNCTION \ + virtual function void from_initiator_struct(fuse_ctrl_in_initiator_s fuse_ctrl_in_initiator_struct);\ + {\ + this.set_alert_rx_i \ + } = fuse_ctrl_in_initiator_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_responder_struct +// and from_responder_struct methods of the fuse_ctrl_in_transaction class. +// Also update the comments in the driver BFM. +// + `define fuse_ctrl_in_RESPONDER_STRUCT typedef struct packed { \ + caliptra_prim_alert_pkg::alert_rx_t set_alert_rx_i ; \ + } fuse_ctrl_in_responder_s; + + `define fuse_ctrl_in_TO_RESPONDER_STRUCT_FUNCTION \ + virtual function fuse_ctrl_in_responder_s to_responder_struct();\ + fuse_ctrl_in_responder_struct = \ + {\ + this.set_alert_rx_i \ + };\ + return ( fuse_ctrl_in_responder_struct);\ + endfunction + + `define fuse_ctrl_in_FROM_RESPONDER_STRUCT_FUNCTION \ + virtual function void from_responder_struct(fuse_ctrl_in_responder_s fuse_ctrl_in_responder_struct);\ + {\ + this.set_alert_rx_i \ + } = fuse_ctrl_in_responder_struct;\ + endfunction +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_monitor.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_monitor.svh new file mode 100644 index 0000000..fca344d --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_monitor.svh @@ -0,0 +1,131 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class receives fuse_ctrl_in transactions observed by the +// fuse_ctrl_in monitor BFM and broadcasts them through the analysis port +// on the agent. It accesses the monitor BFM through the monitor +// task. This UVM component captures transactions +// for viewing in the waveform viewer if the +// enable_transaction_viewing flag is set in the configuration. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_in_monitor #( + int AlertSyncOn = 3, + caliptra_otp_ctrl_pkg::lfsr_seed_t RndConstLfrSeed = caliptra_otp_ctrl_pkg::RndCnstLfsrSeedDefault, + caliptra_otp_ctrl_pkg::lfsr_perm_t RndCnstLfsrPerm = caliptra_otp_ctrl_pkg::RndCnstLfsrPermDefault, + string MemInitFile = "/home/ws/caliptra/anjpar/ws1/chipsalliance/caliptra-rtl/src/fuse_ctrl/data/otp-img.2048.vmem" + ) + extends uvmf_monitor_base #( + .CONFIG_T(fuse_ctrl_in_configuration #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) +), + .BFM_BIND_T(virtual fuse_ctrl_in_monitor_bfm #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) +), + .TRANS_T(fuse_ctrl_in_transaction #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) +)); + + `uvm_component_param_utils( fuse_ctrl_in_monitor #( + AlertSyncOn, + RndConstLfrSeed, + RndCnstLfsrPerm, + MemInitFile + ) +) + +// Structure used to pass data from monitor BFM to monitor class in agent. +// Use to_monitor_struct function to pack transaction variables into structure. +// Use from_monitor_struct function to unpack transaction variables from structure. +`fuse_ctrl_in_MONITOR_STRUCT + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the monitor BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// monitor BFM. This allows the monitor BFM to call the notify_transaction +// function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// *************************************************************************** + virtual task run_phase(uvm_phase phase); + // Start monitor BFM thread and don't call super.run() in order to + // override the default monitor proxy 'pull' behavior with the more + // emulation-friendly BFM 'push' approach using the notify_transaction + // function below + bfm.start_monitoring(); + endtask + +// ************************************************************************** + +// This function is called by the monitor BFM. It receives data observed by the +// monitor BFM. Data is passed using the fuse_ctrl_in_monitor_struct. + virtual function void notify_transaction(input fuse_ctrl_in_monitor_s fuse_ctrl_in_monitor_struct); + + + trans = new("trans"); + trans.from_monitor_struct(fuse_ctrl_in_monitor_struct); + trans.start_time = time_stamp; + trans.end_time = $time; + time_stamp = trans.end_time; + + analyze(trans); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_monitor_bfm.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_monitor_bfm.sv new file mode 100644 index 0000000..7ab1a87 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_monitor_bfm.sv @@ -0,0 +1,218 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface performs the fuse_ctrl_in signal monitoring. +// It is accessed by the uvm fuse_ctrl_in monitor through a virtual +// interface handle in the fuse_ctrl_in configuration. It monitors the +// signals passed in through the port connection named bus of +// type fuse_ctrl_in_if. +// +// Input signals from the fuse_ctrl_in_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// Interface functions and tasks used by UVM components: +// monitor(inout TRANS_T txn); +// This task receives the transaction, txn, from the +// UVM monitor and then populates variables in txn +// from values observed on bus activity. This task +// blocks until an operation on the fuse_ctrl_in bus is complete. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_in_pkg_hdl::*; +`include "src/fuse_ctrl_in_macros.svh" + + +interface fuse_ctrl_in_monitor_bfm #( + int AlertSyncOn = 3, + caliptra_otp_ctrl_pkg::lfsr_seed_t RndConstLfrSeed = caliptra_otp_ctrl_pkg::RndCnstLfsrSeedDefault, + caliptra_otp_ctrl_pkg::lfsr_perm_t RndCnstLfsrPerm = caliptra_otp_ctrl_pkg::RndCnstLfsrPermDefault, + string MemInitFile = "/home/ws/caliptra/anjpar/ws1/chipsalliance/caliptra-rtl/src/fuse_ctrl/data/otp-img.2048.vmem" + ) + + ( fuse_ctrl_in_if bus ); + // The pragma below and additional ones in-lined further down are for running this BFM on Veloce + // pragma attribute fuse_ctrl_in_monitor_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: AlertSyncOn=%x RndConstLfrSeed=%x RndCnstLfsrPerm=%x MemInitFile=%x ", AlertSyncOn,RndConstLfrSeed,RndCnstLfsrPerm,MemInitFile), + UVM_DEBUG) +end +`endif + + + // Structure used to pass transaction data from monitor BFM to monitor class in agent. +`fuse_ctrl_in_MONITOR_STRUCT + fuse_ctrl_in_monitor_s fuse_ctrl_in_monitor_struct; + + // Structure used to pass configuration data from monitor class to monitor BFM. + `fuse_ctrl_in_CONFIGURATION_STRUCT + + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + tri clk_i_i; + tri rst_ni_i; + tri [$bits(edn_pkg::edn_req_t)-1:0] edn_i_i; + tri [ast_pkg::NumAlerts * $bits(caliptra_prim_alert_pkg::alert_rx_t)-1:0] alert_rx_i_i; + tri [$bits(ast_pkg::ast_obs_ctrl_t)-1:0] obs_ctrl_i_i; + tri [$bits(caliptra_otp_ctrl_pkg::otp_ast_req_t)-1:0] otp_ast_pwr_seq_h_i_i; + tri scan_en_i_i; + tri scan_rst_ni_i; + tri scanmode_i_i; + assign clk_i_i = bus.clk_i; + assign rst_ni_i = bus.rst_ni; + assign edn_i_i = bus.edn_i; + assign alert_rx_i_i = bus.alert_rx_i; + assign obs_ctrl_i_i = bus.obs_ctrl_i; + assign otp_ast_pwr_seq_h_i_i = bus.otp_ast_pwr_seq_h_i; + assign scan_en_i_i = bus.scan_en_i; + assign scan_rst_ni_i = bus.scan_rst_ni; + assign scanmode_i_i = bus.scanmode_i; + + // Proxy handle to UVM monitor + fuse_ctrl_in_pkg::fuse_ctrl_in_monitor #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) + proxy; + // pragma tbx oneway proxy.notify_transaction + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + task wait_for_reset();// pragma tbx xtf + @(posedge clk_i_i) ; + do_wait_for_reset(); + endtask + + // **************************************************************************** + task do_wait_for_reset(); + // pragma uvmf custom reset_condition begin + wait ( rst_ni_i === 1 ) ; + @(posedge clk_i_i) ; + // pragma uvmf custom reset_condition end + endtask + + //****************************************************************** + + task wait_for_num_clocks(input int unsigned count); // pragma tbx xtf + @(posedge clk_i_i); + + repeat (count-1) @(posedge clk_i_i); + endtask + + //****************************************************************** + event go; + function void start_monitoring();// pragma tbx xtf + -> go; + endfunction + + // **************************************************************************** + initial begin + @go; + forever begin + @(posedge clk_i_i); + do_monitor( fuse_ctrl_in_monitor_struct ); + + + proxy.notify_transaction( fuse_ctrl_in_monitor_struct ); + + end + end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the monitor BFM. It is called by the monitor within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the monitor BFM needs to be aware of the new configuration + // variables. + // + function void configure(fuse_ctrl_in_configuration_s fuse_ctrl_in_configuration_arg); // pragma tbx xtf + initiator_responder = fuse_ctrl_in_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + + + // **************************************************************************** + + task do_monitor(output fuse_ctrl_in_monitor_s fuse_ctrl_in_monitor_struct); + // + // Available struct members: + // // fuse_ctrl_in_monitor_struct.set_alert_rx_i + // // + // Reference code; + // How to wait for signal value + // while (control_signal === 1'b1) @(posedge clk_i_i); + // + // How to assign a struct member, named xyz, from a signal. + // All available input signals listed. + // fuse_ctrl_in_monitor_struct.xyz = edn_i_i; // [$bits(edn_pkg::edn_req_t)-1:0] + // fuse_ctrl_in_monitor_struct.xyz = alert_rx_i_i; // [ast_pkg::NumAlerts * $bits(caliptra_prim_alert_pkg::alert_rx_t)-1:0] + // fuse_ctrl_in_monitor_struct.xyz = obs_ctrl_i_i; // [$bits(ast_pkg::ast_obs_ctrl_t)-1:0] + // fuse_ctrl_in_monitor_struct.xyz = otp_ast_pwr_seq_h_i_i; // [$bits(caliptra_otp_ctrl_pkg::otp_ast_req_t)-1:0] + // fuse_ctrl_in_monitor_struct.xyz = scan_en_i_i; // + // fuse_ctrl_in_monitor_struct.xyz = scan_rst_ni_i; // + // fuse_ctrl_in_monitor_struct.xyz = scanmode_i_i; // + // pragma uvmf custom do_monitor begin + // UVMF_CHANGE_ME : Implement protocol monitoring. The commented reference code + // below are examples of how to capture signal values and assign them to + // structure members. All available input signals are listed. The 'while' + // code example shows how to wait for a synchronous flow control signal. This + // task should return when a complete transfer has been observed. Once this task is + // exited with captured values, it is then called again to wait for and observe + // the next transfer. One clock cycle is consumed between calls to do_monitor. + @(posedge clk_i_i); + @(posedge clk_i_i); + @(posedge clk_i_i); + @(posedge clk_i_i); + // pragma uvmf custom do_monitor end + endtask + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_random_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_random_sequence.svh new file mode 100644 index 0000000..bc71689 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_random_sequence.svh @@ -0,0 +1,91 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This sequences randomizes the fuse_ctrl_in transaction and sends it +// to the UVM driver. +// +// This sequence constructs and randomizes a fuse_ctrl_in_transaction. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_in_random_sequence #( + int AlertSyncOn = 3, + caliptra_otp_ctrl_pkg::lfsr_seed_t RndConstLfrSeed = caliptra_otp_ctrl_pkg::RndCnstLfsrSeedDefault, + caliptra_otp_ctrl_pkg::lfsr_perm_t RndCnstLfsrPerm = caliptra_otp_ctrl_pkg::RndCnstLfsrPermDefault, + string MemInitFile = "/home/ws/caliptra/anjpar/ws1/chipsalliance/caliptra-rtl/src/fuse_ctrl/data/otp-img.2048.vmem" + ) + + extends fuse_ctrl_in_sequence_base #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) +; + + `uvm_object_param_utils( fuse_ctrl_in_random_sequence #( + AlertSyncOn, + RndConstLfrSeed, + RndCnstLfsrPerm, + MemInitFile + ) +) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //***************************************************************** + function new(string name = ""); + super.new(name); + endfunction: new + + // **************************************************************************** + // TASK : body() + // This task is automatically executed when this sequence is started using the + // start(sequencerHandle) task. + // + task body(); + + // Construct the transaction + req=fuse_ctrl_in_transaction#( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) +::type_id::create("req"); + start_item(req); + // Randomize the transaction + if(!req.randomize()) `uvm_fatal("SEQ", "fuse_ctrl_in_random_sequence::body()-fuse_ctrl_in_transaction randomization failed") + // Send the transaction to the fuse_ctrl_in_driver_bfm via the sequencer and fuse_ctrl_in_driver. + finish_item(req); + `uvm_info("SEQ", {"Response:",req.convert2string()},UVM_MEDIUM) + + endtask + +endclass: fuse_ctrl_in_random_sequence + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_responder_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_responder_sequence.svh new file mode 100644 index 0000000..cb9a26f --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_responder_sequence.svh @@ -0,0 +1,87 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class can be used to provide stimulus when an interface +// has been configured to run in a responder mode. It +// will never finish by default, always going back to the driver +// and driver BFM for the next transaction with which to respond. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_in_responder_sequence #( + int AlertSyncOn = 3, + caliptra_otp_ctrl_pkg::lfsr_seed_t RndConstLfrSeed = caliptra_otp_ctrl_pkg::RndCnstLfsrSeedDefault, + caliptra_otp_ctrl_pkg::lfsr_perm_t RndCnstLfsrPerm = caliptra_otp_ctrl_pkg::RndCnstLfsrPermDefault, + string MemInitFile = "/home/ws/caliptra/anjpar/ws1/chipsalliance/caliptra-rtl/src/fuse_ctrl/data/otp-img.2048.vmem" + ) + + extends fuse_ctrl_in_sequence_base #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) +; + + `uvm_object_param_utils( fuse_ctrl_in_responder_sequence #( + AlertSyncOn, + RndConstLfrSeed, + RndCnstLfsrPerm, + MemInitFile + ) +) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "fuse_ctrl_in_responder_sequence"); + super.new(name); + endfunction + + task body(); + req=fuse_ctrl_in_transaction#( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) +::type_id::create("req"); + forever begin + start_item(req); + finish_item(req); + // pragma uvmf custom body begin + // UVMF_CHANGE_ME : Do something here with the resulting req item. The + // finish_item() call above will block until the req transaction is ready + // to be handled by the responder sequence. + // If this was an item that required a response, the expectation is + // that the response should be populated within this transaction now. + `uvm_info("SEQ",$sformatf("Processed txn: %s",req.convert2string()),UVM_HIGH) + // pragma uvmf custom body end + end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_sequence_base.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_sequence_base.svh new file mode 100644 index 0000000..c4f0be3 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_sequence_base.svh @@ -0,0 +1,146 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the class used as the base class for all sequences +// for this interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_in_sequence_base #( + int AlertSyncOn = 3, + caliptra_otp_ctrl_pkg::lfsr_seed_t RndConstLfrSeed = caliptra_otp_ctrl_pkg::RndCnstLfsrSeedDefault, + caliptra_otp_ctrl_pkg::lfsr_perm_t RndCnstLfsrPerm = caliptra_otp_ctrl_pkg::RndCnstLfsrPermDefault, + string MemInitFile = "/home/ws/caliptra/anjpar/ws1/chipsalliance/caliptra-rtl/src/fuse_ctrl/data/otp-img.2048.vmem" + ) + extends uvmf_sequence_base #( + .REQ(fuse_ctrl_in_transaction #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) +), + .RSP(fuse_ctrl_in_transaction #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) +)); + + `uvm_object_param_utils( fuse_ctrl_in_sequence_base #( + AlertSyncOn, + RndConstLfrSeed, + RndCnstLfsrPerm, + MemInitFile + ) +) + + // variables + typedef fuse_ctrl_in_transaction #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) + fuse_ctrl_in_transaction_req_t; + fuse_ctrl_in_transaction_req_t req; + typedef fuse_ctrl_in_transaction #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) + fuse_ctrl_in_transaction_rsp_t; + fuse_ctrl_in_transaction_rsp_t rsp; + + // Event for identifying when a response was received from the sequencer + event new_rsp; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // TASK : get_responses() + // This task recursively gets sequence item responses from the sequencer. + // + virtual task get_responses(); + fork + begin + // Block until new rsp available + get_response(rsp); + // New rsp received. Indicate to sequence using event. + ->new_rsp; + // Display the received response transaction + `uvm_info("SEQ", {"New response transaction:",rsp.convert2string()}, UVM_MEDIUM) + end + join_none + endtask + + // **************************************************************************** + // TASK : pre_body() + // This task is called automatically when start is called with call_pre_post set to 1 (default). + // By calling get_responses() within pre_body() any derived sequences are automatically + // processing response transactions. Only un-comment this call to get_responses() if you + // have configured the interface driver to utilize the response transaction path by setting + // the configuration variable "return_transaction_response" to 1. Otherwise it is possible + // to impact runtime performance and memory utilization. + // + virtual task pre_body(); + // pragma uvmf custom pre_body begin +// get_responses(); + // pragma uvmf custom pre_body end + endtask + + // **************************************************************************** + // TASK : body() + // This task is called automatically when start is called. This sequence sends + // a req sequence item to the sequencer identified as an argument in the call + // to start. + // + virtual task body(); + // pragma uvmf custom body begin + start_item(req); + finish_item(req); + // pragma uvmf custom body end + endtask + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name =""); + super.new( name ); + // pragma uvmf custom new begin + req = fuse_ctrl_in_transaction_req_t::type_id::create("req"); + rsp = fuse_ctrl_in_transaction_rsp_t::type_id::create("rsp"); + // pragma uvmf custom new end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_transaction.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_transaction.svh new file mode 100644 index 0000000..853ddc2 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_transaction.svh @@ -0,0 +1,219 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class defines the variables required for an fuse_ctrl_in +// transaction. Class variables to be displayed in waveform transaction +// viewing are added to the transaction viewing stream in the add_to_wave +// function. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_in_transaction #( + int AlertSyncOn = 3, + caliptra_otp_ctrl_pkg::lfsr_seed_t RndConstLfrSeed = caliptra_otp_ctrl_pkg::RndCnstLfsrSeedDefault, + caliptra_otp_ctrl_pkg::lfsr_perm_t RndCnstLfsrPerm = caliptra_otp_ctrl_pkg::RndCnstLfsrPermDefault, + string MemInitFile = "/home/ws/caliptra/anjpar/ws1/chipsalliance/caliptra-rtl/src/fuse_ctrl/data/otp-img.2048.vmem" + ) + extends uvmf_transaction_base; + + `uvm_object_param_utils( fuse_ctrl_in_transaction #( + AlertSyncOn, + RndConstLfrSeed, + RndCnstLfsrPerm, + MemInitFile + ) +) + + caliptra_prim_alert_pkg::alert_rx_t set_alert_rx_i ; + + //Constraints for the transaction variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //******************************************************************* + //******************************************************************* + // Macros that define structs and associated functions are + // located in fuse_ctrl_in_macros.svh + + //******************************************************************* + // Monitor macro used by fuse_ctrl_in_monitor and fuse_ctrl_in_monitor_bfm + // This struct is defined in fuse_ctrl_in_macros.svh + `fuse_ctrl_in_MONITOR_STRUCT + fuse_ctrl_in_monitor_s fuse_ctrl_in_monitor_struct; + //******************************************************************* + // FUNCTION: to_monitor_struct() + // This function packs transaction variables into a fuse_ctrl_in_monitor_s + // structure. The function returns the handle to the fuse_ctrl_in_monitor_struct. + // This function is defined in fuse_ctrl_in_macros.svh + `fuse_ctrl_in_TO_MONITOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_monitor_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_in_macros.svh + `fuse_ctrl_in_FROM_MONITOR_STRUCT_FUNCTION + + //******************************************************************* + // Initiator macro used by fuse_ctrl_in_driver and fuse_ctrl_in_driver_bfm + // to communicate initiator driven data to fuse_ctrl_in_driver_bfm. + // This struct is defined in fuse_ctrl_in_macros.svh + `fuse_ctrl_in_INITIATOR_STRUCT + fuse_ctrl_in_initiator_s fuse_ctrl_in_initiator_struct; + //******************************************************************* + // FUNCTION: to_initiator_struct() + // This function packs transaction variables into a fuse_ctrl_in_initiator_s + // structure. The function returns the handle to the fuse_ctrl_in_initiator_struct. + // This function is defined in fuse_ctrl_in_macros.svh + `fuse_ctrl_in_TO_INITIATOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_initiator_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_in_macros.svh + `fuse_ctrl_in_FROM_INITIATOR_STRUCT_FUNCTION + + //******************************************************************* + // Responder macro used by fuse_ctrl_in_driver and fuse_ctrl_in_driver_bfm + // to communicate Responder driven data to fuse_ctrl_in_driver_bfm. + // This struct is defined in fuse_ctrl_in_macros.svh + `fuse_ctrl_in_RESPONDER_STRUCT + fuse_ctrl_in_responder_s fuse_ctrl_in_responder_struct; + //******************************************************************* + // FUNCTION: to_responder_struct() + // This function packs transaction variables into a fuse_ctrl_in_responder_s + // structure. The function returns the handle to the fuse_ctrl_in_responder_struct. + // This function is defined in fuse_ctrl_in_macros.svh + `fuse_ctrl_in_TO_RESPONDER_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_responder_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_in_macros.svh + `fuse_ctrl_in_FROM_RESPONDER_STRUCT_FUNCTION + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + endfunction + + // **************************************************************************** + // FUNCTION: convert2string() + // This function converts all variables in this class to a single string for + // logfile reporting. + // + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + // UVMF_CHANGE_ME : Customize format if desired. + return $sformatf("set_alert_rx_i:0x%x ",set_alert_rx_i); + // pragma uvmf custom convert2string end + endfunction + + //******************************************************************* + // FUNCTION: do_print() + // This function is automatically called when the .print() function + // is called on this class. + // + virtual function void do_print(uvm_printer printer); + // pragma uvmf custom do_print begin + // UVMF_CHANGE_ME : Current contents of do_print allows for the use of UVM 1.1d, 1.2 or P1800.2. + // Update based on your own printing preference according to your preferred UVM version + $display(convert2string()); + // pragma uvmf custom do_print end + endfunction + + //******************************************************************* + // FUNCTION: do_compare() + // This function is automatically called when the .compare() function + // is called on this class. + // + virtual function bit do_compare (uvm_object rhs, uvm_comparer comparer); + fuse_ctrl_in_transaction #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) + RHS; + if (!$cast(RHS,rhs)) return 0; + // pragma uvmf custom do_compare begin + // UVMF_CHANGE_ME : Eliminate comparison of variables not to be used for compare + return (super.do_compare(rhs,comparer) + ); + // pragma uvmf custom do_compare end + endfunction + + //******************************************************************* + // FUNCTION: do_copy() + // This function is automatically called when the .copy() function + // is called on this class. + // + virtual function void do_copy (uvm_object rhs); + fuse_ctrl_in_transaction #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) + RHS; + assert($cast(RHS,rhs)); + // pragma uvmf custom do_copy begin + super.do_copy(rhs); + this.set_alert_rx_i = RHS.set_alert_rx_i; + // pragma uvmf custom do_copy end + endfunction + + // **************************************************************************** + // FUNCTION: add_to_wave() + // This function is used to display variables in this class in the waveform + // viewer. The start_time and end_time variables must be set before this + // function is called. If the start_time and end_time variables are not set + // the transaction will be hidden at 0ns on the waveform display. + // + virtual function void add_to_wave(int transaction_viewing_stream_h); + `ifdef QUESTA + if (transaction_view_h == 0) begin + transaction_view_h = $begin_transaction(transaction_viewing_stream_h,"fuse_ctrl_in_transaction",start_time); + end + super.add_to_wave(transaction_view_h); + // pragma uvmf custom add_to_wave begin + // UVMF_CHANGE_ME : Color can be applied to transaction entries based on content, example below + // case() + // 1 : $add_color(transaction_view_h,"red"); + // default : $add_color(transaction_view_h,"grey"); + // endcase + // UVMF_CHANGE_ME : Eliminate transaction variables not wanted in transaction viewing in the waveform viewer + $add_attribute(transaction_view_h,set_alert_rx_i,"set_alert_rx_i"); + // pragma uvmf custom add_to_wave end + $end_transaction(transaction_view_h,end_time); + $free_transaction(transaction_view_h); + `endif // QUESTA + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_transaction_coverage.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_transaction_coverage.svh new file mode 100644 index 0000000..d6bdbd6 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_transaction_coverage.svh @@ -0,0 +1,102 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class records fuse_ctrl_in transaction information using +// a covergroup named fuse_ctrl_in_transaction_cg. An instance of this +// coverage component is instantiated in the uvmf_parameterized_agent +// if the has_coverage flag is set. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_in_transaction_coverage #( + int AlertSyncOn = 3, + caliptra_otp_ctrl_pkg::lfsr_seed_t RndConstLfrSeed = caliptra_otp_ctrl_pkg::RndCnstLfsrSeedDefault, + caliptra_otp_ctrl_pkg::lfsr_perm_t RndCnstLfsrPerm = caliptra_otp_ctrl_pkg::RndCnstLfsrPermDefault, + string MemInitFile = "/home/ws/caliptra/anjpar/ws1/chipsalliance/caliptra-rtl/src/fuse_ctrl/data/otp-img.2048.vmem" + ) + extends uvm_subscriber #(.T(fuse_ctrl_in_transaction #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) +)); + + `uvm_component_param_utils( fuse_ctrl_in_transaction_coverage #( + AlertSyncOn, + RndConstLfrSeed, + RndCnstLfsrPerm, + MemInitFile + ) +) + + T coverage_trans; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + covergroup fuse_ctrl_in_transaction_cg; + // pragma uvmf custom covergroup begin + // UVMF_CHANGE_ME : Add coverage bins, crosses, exclusions, etc. according to coverage needs. + option.auto_bin_max=1024; + option.per_instance=1; + set_alert_rx_i: coverpoint coverage_trans.set_alert_rx_i; + // pragma uvmf custom covergroup end + endgroup + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new(string name="", uvm_component parent=null); + super.new(name,parent); + fuse_ctrl_in_transaction_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that transaction variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + endfunction + + // **************************************************************************** + // FUNCTION : build_phase() + // This function is the standard UVM build_phase. + // + function void build_phase(uvm_phase phase); + fuse_ctrl_in_transaction_cg.set_inst_name($sformatf("fuse_ctrl_in_transaction_cg_%s",get_full_name())); + endfunction + + // **************************************************************************** + // FUNCTION: write (T t) + // This function is automatically executed when a transaction arrives on the + // analysis_export. It copies values from the variables in the transaction + // to local variables used to collect functional coverage. + // + virtual function void write (T t); + `uvm_info("COV","Received transaction",UVM_HIGH); + coverage_trans = t; + fuse_ctrl_in_transaction_cg.sample(); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_typedefs.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_typedefs.svh new file mode 100644 index 0000000..f2a7bdb --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_typedefs.svh @@ -0,0 +1,34 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the host server when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_typedefs_hdl.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_typedefs_hdl.svh new file mode 100644 index 0000000..0d58518 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/src/fuse_ctrl_in_typedefs_hdl.svh @@ -0,0 +1,35 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the emulator when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/yaml/fuse_ctrl_in_interface.yaml b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/yaml/fuse_ctrl_in_interface.yaml new file mode 100644 index 0000000..e1024d7 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_in_pkg/yaml/fuse_ctrl_in_interface.yaml @@ -0,0 +1,65 @@ +uvmf: + interfaces: + fuse_ctrl_in: + clock: clk_i + config_constraints: [] + config_vars: [] + existing_library_component: 'True' + gen_inbound_streaming_driver: 'False' + hdl_pkg_parameters: [] + hdl_typedefs: [] + hvl_pkg_parameters: [] + hvl_typedefs: [] + parameters: + - name: AlertSyncOn + type: int + value: '3' + - name: RndConstLfrSeed + type: caliptra_otp_ctrl_pkg::lfsr_seed_t + value: caliptra_otp_ctrl_pkg::RndCnstLfsrSeedDefault + - name: RndCnstLfsrPerm + type: caliptra_otp_ctrl_pkg::lfsr_perm_t + value: caliptra_otp_ctrl_pkg::RndCnstLfsrPermDefault + - name: MemInitFile + type: string + value: /home/ws/caliptra/anjpar/ws1/chipsalliance/caliptra-rtl/src/fuse_ctrl/data/otp-img.2048.vmem + ports: + - dir: output + name: edn_i + reset_value: '''bz' + width: '[''$bits(edn_pkg::edn_req_t)'']' + - dir: output + name: alert_rx_i + reset_value: '''bz' + width: '[''ast_pkg::NumAlerts * $bits(caliptra_prim_alert_pkg::alert_rx_t)'']' + - dir: output + name: obs_ctrl_i + reset_value: '''bz' + width: '[''$bits(ast_pkg::ast_obs_ctrl_t)'']' + - dir: output + name: otp_ast_pwr_seq_h_i + reset_value: '''bz' + width: '[''$bits(caliptra_otp_ctrl_pkg::otp_ast_req_t)'']' + - dir: output + name: scan_en_i + reset_value: '''bz' + width: '1' + - dir: output + name: scan_rst_ni + reset_value: '''bz' + width: '1' + - dir: output + name: scanmode_i + reset_value: '''bz' + width: '1' + reset: rst_ni + reset_assertion_level: 'False' + transaction_constraints: [] + transaction_vars: + - comment: '' + iscompare: 'False' + isrand: 'False' + name: set_alert_rx_i + type: caliptra_prim_alert_pkg::alert_rx_t + unpacked_dimension: '' + use_dpi_link: 'False' diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/.project b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/.project new file mode 100644 index 0000000..bc9bb7a --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/.project @@ -0,0 +1,30 @@ + + + fuse_ctrl_lc_otp_in_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/.svproject b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/.svproject new file mode 100644 index 0000000..e267e6c --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/Makefile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/Makefile new file mode 100644 index 0000000..48df82f --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/Makefile @@ -0,0 +1,66 @@ +# fuse_ctrl_lc_otp_in interface packages source +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +fuse_ctrl_lc_otp_in_PKG = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_lc_otp_in_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_filelist_hvl.f + +fuse_ctrl_lc_otp_in_PKG_HDL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_lc_otp_in_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_filelist_hdl.f + +fuse_ctrl_lc_otp_in_PKG_XRTL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_lc_otp_in_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_filelist_xrtl.f + +COMP_fuse_ctrl_lc_otp_in_PKG_TGT_0 = q_comp_fuse_ctrl_lc_otp_in_pkg +COMP_fuse_ctrl_lc_otp_in_PKG_TGT_1 = v_comp_fuse_ctrl_lc_otp_in_pkg +COMP_fuse_ctrl_lc_otp_in_PKG_TGT = $(COMP_fuse_ctrl_lc_otp_in_PKG_TGT_$(USE_VELOCE)) + +comp_fuse_ctrl_lc_otp_in_pkg: $(COMP_fuse_ctrl_lc_otp_in_PKG_TGT) + +q_comp_fuse_ctrl_lc_otp_in_pkg: + $(HDL_COMP_CMD) $(fuse_ctrl_lc_otp_in_PKG_HDL) + $(HVL_COMP_CMD) $(fuse_ctrl_lc_otp_in_PKG) + $(HDL_COMP_CMD) $(fuse_ctrl_lc_otp_in_PKG_XRTL) + +v_comp_fuse_ctrl_lc_otp_in_pkg: + $(HVL_COMP_CMD) $(fuse_ctrl_lc_otp_in_PKG_HDL) + $(HVL_COMP_CMD) $(fuse_ctrl_lc_otp_in_PKG) + $(VELANALYZE_CMD) $(fuse_ctrl_lc_otp_in_PKG_HDL) + $(VELANALYZE_HVL_CMD) $(fuse_ctrl_lc_otp_in_PKG) + $(HDL_COMP_CMD) $(fuse_ctrl_lc_otp_in_PKG_XRTL) + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export fuse_ctrl_lc_otp_in_IF_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_lc_otp_in_pkg/dpi + +C_FILE_COMPILE_LIST_fuse_ctrl_lc_otp_in_pkg = \ + +O_FILE_COMPILE_LIST_fuse_ctrl_lc_otp_in_pkg = $(notdir $(C_FILE_COMPILE_LIST_fuse_ctrl_lc_otp_in_pkg:.c=.o)) + +GCC_COMP_ARGS_fuse_ctrl_lc_otp_in_pkg += -I$(fuse_ctrl_lc_otp_in_IF_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_fuse_ctrl_lc_otp_in_pkg += $(fuse_ctrl_lc_otp_in_IF_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_fuse_ctrl_lc_otp_in_pkg += \ + \ + -o .so + +comp_fuse_ctrl_lc_otp_in_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Interface C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_fuse_ctrl_lc_otp_in_pkg) $(C_FILE_COMPILE_LIST_fuse_ctrl_lc_otp_in_pkg) + @echo "--------------------------------" + @echo "Linking Interface C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_fuse_ctrl_lc_otp_in_pkg) $(O_FILE_COMPILE_LIST_fuse_ctrl_lc_otp_in_pkg) + @echo "--------------------------------" + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/compile.do b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/compile.do new file mode 100644 index 0000000..2334cca --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/compile.do @@ -0,0 +1,14 @@ +# Tcl do file for compile of fuse_ctrl_lc_otp_in interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_lc_otp_in_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_filelist_hdl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_lc_otp_in_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_filelist_hvl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_lc_otp_in_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_filelist_xrtl.f \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in.compile new file mode 100644 index 0000000..934282f --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in.compile @@ -0,0 +1,3 @@ +needs: + - fuse_ctrl_lc_otp_in_hvl.compile + - fuse_ctrl_lc_otp_in_hdl.compile diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_bfm.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_bfm.vinfo new file mode 100644 index 0000000..35c34c5 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_bfm.vinfo @@ -0,0 +1,6 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use fuse_ctrl_lc_otp_in_pkg_hdl.vinfo ++incdir+@vinfodir +src/fuse_ctrl_lc_otp_in_if.sv +src/fuse_ctrl_lc_otp_in_driver_bfm.sv +src/fuse_ctrl_lc_otp_in_monitor_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_common.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_common.compile new file mode 100644 index 0000000..5683974 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_common.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +incdir: + - . + - ${uvm_path}/src +src: + - fuse_ctrl_lc_otp_in_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_filelist_hdl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_filelist_hdl.f new file mode 100644 index 0000000..fd87f10 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_filelist_hdl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_filelist_hvl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_filelist_hvl.f new file mode 100644 index 0000000..ea2637f --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_filelist_hvl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_pkg.sv \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_filelist_xrtl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_filelist_xrtl.f new file mode 100644 index 0000000..736ca19 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_filelist_xrtl.f @@ -0,0 +1,3 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_if.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_monitor_bfm.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_driver_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_hdl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_hdl.compile new file mode 100644 index 0000000..9def84f --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_hdl.compile @@ -0,0 +1,9 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ./fuse_ctrl_lc_otp_in_common.compile +incdir: + - . +src: + - src/fuse_ctrl_lc_otp_in_if.sv + - src/fuse_ctrl_lc_otp_in_monitor_bfm.sv + - src/fuse_ctrl_lc_otp_in_driver_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_hvl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_hvl.compile new file mode 100644 index 0000000..0374205 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_hvl.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ./fuse_ctrl_lc_otp_in_common.compile +incdir: + - . +src: + - fuse_ctrl_lc_otp_in_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_pkg.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_pkg.sv new file mode 100644 index 0000000..7077717 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_pkg.sv @@ -0,0 +1,91 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - + +// - +// - +// - + +// - +// - +// - + +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_lc_otp_in_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg_hdl::*; + import uvmf_base_pkg::*; + import fuse_ctrl_lc_otp_in_pkg_hdl::*; + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + `include "src/fuse_ctrl_lc_otp_in_macros.svh" + + export fuse_ctrl_lc_otp_in_pkg_hdl::*; + + + + // Parameters defined as HVL parameters + + `include "src/fuse_ctrl_lc_otp_in_typedefs.svh" + `include "src/fuse_ctrl_lc_otp_in_transaction.svh" + + `include "src/fuse_ctrl_lc_otp_in_configuration.svh" + `include "src/fuse_ctrl_lc_otp_in_driver.svh" + `include "src/fuse_ctrl_lc_otp_in_monitor.svh" + + `include "src/fuse_ctrl_lc_otp_in_transaction_coverage.svh" + `include "src/fuse_ctrl_lc_otp_in_sequence_base.svh" + `include "src/fuse_ctrl_lc_otp_in_random_sequence.svh" + + `include "src/fuse_ctrl_lc_otp_in_responder_sequence.svh" + `include "src/fuse_ctrl_lc_otp_in2reg_adapter.svh" + + `include "src/fuse_ctrl_lc_otp_in_agent.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new interface sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the interface package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_pkg.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_pkg.vinfo new file mode 100644 index 0000000..a51e3e0 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_pkg.vinfo @@ -0,0 +1,4 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use fuse_ctrl_lc_otp_in_pkg_hdl.vinfo ++incdir+@vinfodir +fuse_ctrl_lc_otp_in_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_pkg_hdl.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_pkg_hdl.sv new file mode 100644 index 0000000..e1761c3 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_pkg_hdl.sv @@ -0,0 +1,52 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that needs to be compiled and synthesized +// for running on Veloce. +// +// CONTAINS: +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_lc_otp_in_pkg_hdl; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HDL parameters + + `include "src/fuse_ctrl_lc_otp_in_typedefs_hdl.svh" + `include "src/fuse_ctrl_lc_otp_in_macros.svh" + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_pkg_hdl.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_pkg_hdl.vinfo new file mode 100644 index 0000000..536dd9e --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_pkg_hdl.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +fuse_ctrl_lc_otp_in_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_pkg_sve.F b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_pkg_sve.F new file mode 100644 index 0000000..1f476e9 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_pkg_sve.F @@ -0,0 +1,10 @@ +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + ++incdir+. +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_filelist_hdl.f +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_lc_otp_in_pkg/fuse_ctrl_lc_otp_in_filelist_hvl.f diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in2reg_adapter.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in2reg_adapter.svh new file mode 100644 index 0000000..b1d2bb5 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in2reg_adapter.svh @@ -0,0 +1,112 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the UVM register adapter for the fuse_ctrl_lc_otp_in interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_lc_otp_in2reg_adapter extends uvm_reg_adapter; + + `uvm_object_utils( fuse_ctrl_lc_otp_in2reg_adapter ) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //-------------------------------------------------------------------- + // new + //-------------------------------------------------------------------- + function new (string name = "fuse_ctrl_lc_otp_in2reg_adapter" ); + super.new(name); + // pragma uvmf custom new begin + // UVMF_CHANGE_ME : Configure the adapter regarding byte enables and provides response. + + // Does the protocol the Agent is modeling support byte enables? + // 0 = NO + // 1 = YES + supports_byte_enable = 0; + + // Does the Agent's Driver provide separate response sequence items? + // i.e. Does the driver call seq_item_port.put() + // and do the sequences call get_response()? + // 0 = NO + // 1 = YES + provides_responses = 0; + // pragma uvmf custom new end + + endfunction: new + + //-------------------------------------------------------------------- + // reg2bus + //-------------------------------------------------------------------- + virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw); + + fuse_ctrl_lc_otp_in_transaction trans_h = fuse_ctrl_lc_otp_in_transaction ::type_id::create("trans_h"); + + // pragma uvmf custom reg2bus begin + // UVMF_CHANGE_ME : Fill in the reg2bus adapter mapping registe fields to protocol fields. + + //Adapt the following for your sequence item type + // trans_h.op = (rw.kind == UVM_READ) ? WB_READ : WB_WRITE; + //Copy over address + // trans_h.addr = rw.addr; + //Copy over write data + // trans_h.data = rw.data; + + // pragma uvmf custom reg2bus end + + // Return the adapted transaction + return trans_h; + + endfunction: reg2bus + + //-------------------------------------------------------------------- + // bus2reg + //-------------------------------------------------------------------- + virtual function void bus2reg(uvm_sequence_item bus_item, + ref uvm_reg_bus_op rw); + fuse_ctrl_lc_otp_in_transaction trans_h; + if (!$cast(trans_h, bus_item)) begin + `uvm_fatal("ADAPT","Provided bus_item is not of the correct type") + return; + end + // pragma uvmf custom bus2reg begin + // UVMF_CHANGE_ME : Fill in the bus2reg adapter mapping protocol fields to register fields. + //Adapt the following for your sequence item type + //Copy over instruction type + // rw.kind = (trans_h.op == WB_WRITE) ? UVM_WRITE : UVM_READ; + //Copy over address + // rw.addr = trans_h.addr; + //Copy over read data + // rw.data = trans_h.data; + //Check for errors on the bus and return UVM_NOT_OK if there is an error + // rw.status = UVM_IS_OK; + // pragma uvmf custom bus2reg end + + endfunction: bus2reg + +endclass : fuse_ctrl_lc_otp_in2reg_adapter + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_agent.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_agent.svh new file mode 100644 index 0000000..1bcc445 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_agent.svh @@ -0,0 +1,67 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: Protocol specific agent class definition +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_lc_otp_in_agent extends uvmf_parameterized_agent #( + .CONFIG_T(fuse_ctrl_lc_otp_in_configuration ), + .DRIVER_T(fuse_ctrl_lc_otp_in_driver ), + .MONITOR_T(fuse_ctrl_lc_otp_in_monitor ), + .COVERAGE_T(fuse_ctrl_lc_otp_in_transaction_coverage ), + .TRANS_T(fuse_ctrl_lc_otp_in_transaction ) + ); + + `uvm_component_utils( fuse_ctrl_lc_otp_in_agent ) + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** + // FUNCTION: build_phase + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + if (configuration.active_passive == ACTIVE) begin + // Place sequencer handle into configuration object + // so that it may be retrieved from configuration + // rather than using uvm_config_db + configuration.sequencer = this.sequencer; + end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_configuration.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_configuration.svh new file mode 100644 index 0000000..3d01dbb --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_configuration.svh @@ -0,0 +1,193 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class contains all variables and functions used +// to configure the fuse_ctrl_lc_otp_in agent and its bfm's. It gets the +// bfm's from the uvm_config_db for use by the agent. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_lc_otp_in_configuration extends uvmf_parameterized_agent_configuration_base #( + .DRIVER_BFM_BIND_T(virtual fuse_ctrl_lc_otp_in_driver_bfm ), + .MONITOR_BFM_BIND_T( virtual fuse_ctrl_lc_otp_in_monitor_bfm )); + + `uvm_object_utils( fuse_ctrl_lc_otp_in_configuration ) + + + // Sequencer handle populated by agent + uvm_sequencer #(fuse_ctrl_lc_otp_in_transaction ) sequencer; + + //Constraints for the configuration variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + covergroup fuse_ctrl_lc_otp_in_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + // pragma uvmf custom covergroup end + endgroup + + //******************************************************************* + //******************************************************************* + // Structure used to pass configuration variables to monitor and driver BFM's. + // Use to_struct function to pack variables into structure. + // Use from_struct function to unpack variables from structure. + // This structure is defined in fuse_ctrl_lc_otp_in_macros.svh + `fuse_ctrl_lc_otp_in_CONFIGURATION_STRUCT + fuse_ctrl_lc_otp_in_configuration_s fuse_ctrl_lc_otp_in_configuration_struct; + //******************************************************************* + // FUNCTION: to_struct() + // This function packs variables into a fuse_ctrl_lc_otp_in_configuration_s + // structure. The function returns the handle to the fuse_ctrl_lc_otp_in_configuration_struct. + // This function is defined in fuse_ctrl_lc_otp_in_macros.svh + `fuse_ctrl_lc_otp_in_CONFIGURATION_TO_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_struct() + // This function unpacks the struct provided as an argument into + // variables of this class. + // This function is defined in fuse_ctrl_lc_otp_in_macros.svh + `fuse_ctrl_lc_otp_in_CONFIGURATION_FROM_STRUCT_FUNCTION + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + // Construct the covergroup for this configuration class + fuse_ctrl_lc_otp_in_configuration_cg = new; + endfunction + + // **************************************************************************** + // FUNCTION: post_randomize() + // This function is automatically called after the randomize() function + // is executed. + // + function void post_randomize(); + super.post_randomize(); + fuse_ctrl_lc_otp_in_configuration_cg.sample(); + endfunction + + // **************************************************************************** + // FUNCTION: initialize + // This function causes the configuration to retrieve + // its virtual interface handle from the uvm_config_db. + // This function also makes itself available to its + // agent through the uvm_config_db. + // + // ARGUMENTS: + // uvmf_active_passive_t activity: + // This argument identifies the simulation level + // as either BLOCK, CHIP, SIMULATION, etc. + // + // AGENT_PATH: + // This argument identifies the path to this + // configurations agent. This configuration + // makes itself available to the agent specified + // by agent_path by placing itself into the + // uvm_config_db. + // + // INTERFACE_NAME: + // This argument identifies the string name of + // this configurations BFM's. This string + // name is used to retrieve the driver and + // monitor BFM from the uvm_config_db. + // + virtual function void initialize(uvmf_active_passive_t activity, + string agent_path, + string interface_name); + + super.initialize( activity, agent_path, interface_name); + // The covergroup is given the same name as the interface + fuse_ctrl_lc_otp_in_configuration_cg.set_inst_name(interface_name); + + // This configuration places itself into the uvm_config_db for the agent, identified by the agent_path variable, to retrieve. + uvm_config_db #( fuse_ctrl_lc_otp_in_configuration + )::set( null ,agent_path,UVMF_AGENT_CONFIG, this ); + + // This configuration also places itself in the config db using the same identifier used by the interface. This allows users to access + // configuration variables and the interface through the bfm api class rather than directly accessing the BFM. This is useful for + // accessingthe BFM when using Veloce + uvm_config_db #( fuse_ctrl_lc_otp_in_configuration + )::set( null ,UVMF_CONFIGURATIONS, interface_name, this ); + + fuse_ctrl_lc_otp_in_configuration_cg.set_inst_name($sformatf("fuse_ctrl_lc_otp_in_configuration_cg_%s",get_full_name())); + +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. + `uvm_info("CFG", + $psprintf("The agent at '%s' is using interface named %s has the following parameters: ", agent_path, interface_name, ), + UVM_DEBUG) + + // pragma uvmf custom initialize begin + // This controls whether or not the agent returns a transaction handle in the driver when calling + // item_done() back into the sequencer or not. If set to 1, a transaction is sent back which means + // the sequence on the other end must use the get_response() part of the driver/sequence API. If + // this doesn't occur, there will eventually be response_queue overflow errors during the test. + return_transaction_response = 1'b0; + + // pragma uvmf custom initialize end + + endfunction + + // **************************************************************************** + // TASK: wait_for_reset + // *[Required]* Blocks until reset is released. The wait_for_reset operation is performed + // by a task in the monitor bfm. + virtual task wait_for_reset(); + monitor_bfm.wait_for_reset(); + endtask + + // **************************************************************************** + // TASK: wait_for_num_clocks + // *[Required]* Blocks until specified number of clocks have elapsed. The wait_for_num_clocks + // operation is performed by a task in the monitor bfm. + virtual task wait_for_num_clocks(int clocks); + monitor_bfm.wait_for_num_clocks(clocks); + endtask + + // **************************************************************************** + // FUNCTION : convert2string() + // This function is used to convert variables in this class into a string for log messaging. + // + virtual function string convert2string (); + // pragma uvmf custom convert2string begin + return $sformatf(""); + // pragma uvmf custom convert2string end + endfunction + + // **************************************************************************** + // FUNCTION: get_sequencer + function uvm_sequencer #(fuse_ctrl_lc_otp_in_transaction) get_sequencer(); + return sequencer; + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_driver.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_driver.svh new file mode 100644 index 0000000..fc0a219 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_driver.svh @@ -0,0 +1,105 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class passes transactions between the sequencer +// and the BFM driver interface. It accesses the driver BFM +// through the bfm handle. This driver +// passes transactions to the driver BFM through the access +// task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_lc_otp_in_driver extends uvmf_driver_base #( + .CONFIG_T(fuse_ctrl_lc_otp_in_configuration ), + .BFM_BIND_T(virtual fuse_ctrl_lc_otp_in_driver_bfm ), + .REQ(fuse_ctrl_lc_otp_in_transaction ), + .RSP(fuse_ctrl_lc_otp_in_transaction )); + + `uvm_component_utils( fuse_ctrl_lc_otp_in_driver ) +//******************************************************************* +// Macros that define structs located in fuse_ctrl_lc_otp_in_macros.svh +//******************************************************************* +// Initiator macro used by fuse_ctrl_lc_otp_in_driver and fuse_ctrl_lc_otp_in_driver_bfm +// to communicate initiator driven data to fuse_ctrl_lc_otp_in_driver_bfm. +`fuse_ctrl_lc_otp_in_INITIATOR_STRUCT + fuse_ctrl_lc_otp_in_initiator_s fuse_ctrl_lc_otp_in_initiator_struct; +//******************************************************************* +// Responder macro used by fuse_ctrl_lc_otp_in_driver and fuse_ctrl_lc_otp_in_driver_bfm +// to communicate Responder driven data to fuse_ctrl_lc_otp_in_driver_bfm. +`fuse_ctrl_lc_otp_in_RESPONDER_STRUCT + fuse_ctrl_lc_otp_in_responder_s fuse_ctrl_lc_otp_in_responder_struct; + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent=null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the driver BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// driver BFM. This allows the driver BFM to call tasks and function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// **************************************************************************** +// This task is called by the run_phase in uvmf_driver_base. + virtual task access( inout REQ txn ); +// pragma uvmf custom access begin + if (configuration.initiator_responder==RESPONDER) begin + // Complete current transfer and wait for next transfer + bfm.respond_and_wait_for_next_transfer( + fuse_ctrl_lc_otp_in_initiator_struct, + txn.to_responder_struct() + ); + // Unpack information about initiated transfer received by this responder + txn.from_initiator_struct(fuse_ctrl_lc_otp_in_initiator_struct); + end else begin + // Initiate a transfer and get response + bfm.initiate_and_get_response( + txn.to_initiator_struct(), + fuse_ctrl_lc_otp_in_responder_struct + ); + // Unpack transfer response information received by this initiator + txn.from_responder_struct(fuse_ctrl_lc_otp_in_responder_struct); + end +// pragma uvmf custom access end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_driver_bfm.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_driver_bfm.sv new file mode 100644 index 0000000..b38ec1e --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_driver_bfm.sv @@ -0,0 +1,321 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This interface performs the fuse_ctrl_lc_otp_in signal driving. It is +// accessed by the uvm fuse_ctrl_lc_otp_in driver through a virtual interface +// handle in the fuse_ctrl_lc_otp_in configuration. It drives the singals passed +// in through the port connection named bus of type fuse_ctrl_lc_otp_in_if. +// +// Input signals from the fuse_ctrl_lc_otp_in_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// This bfm drives signals with a _o suffix. These signals +// are driven onto signals within fuse_ctrl_lc_otp_in_if based on INITIATOR/RESPONDER and/or +// ARBITRATION/GRANT status. +// +// The output signal connections are as follows: +// signal_o -> bus.signal +// +// +// Interface functions and tasks used by UVM components: +// +// configure: +// This function gets configuration attributes from the +// UVM driver to set any required BFM configuration +// variables such as 'initiator_responder'. +// +// initiate_and_get_response: +// This task is used to perform signaling activity for initiating +// a protocol transfer. The task initiates the transfer, using +// input data from the initiator struct. Then the task captures +// response data, placing the data into the response struct. +// The response struct is returned to the driver class. +// +// respond_and_wait_for_next_transfer: +// This task is used to complete a current transfer as a responder +// and then wait for the initiator to start the next transfer. +// The task uses data in the responder struct to drive protocol +// signals to complete the transfer. The task then waits for +// the next transfer. Once the next transfer begins, data from +// the initiator is placed into the initiator struct and sent +// to the responder sequence for processing to determine +// what data to respond with. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_lc_otp_in_pkg_hdl::*; +`include "src/fuse_ctrl_lc_otp_in_macros.svh" + +interface fuse_ctrl_lc_otp_in_driver_bfm + (fuse_ctrl_lc_otp_in_if bus); + // The following pragma and additional ones in-lined further below are for running this BFM on Veloce + // pragma attribute fuse_ctrl_lc_otp_in_driver_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: ", ), + UVM_DEBUG) +end +`endif + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + tri clk_i_i; + tri rst_ni_i; + + // Signal list (all signals are capable of being inputs and outputs for the sake + // of supporting both INITIATOR and RESPONDER mode operation. Expectation is that + // directionality in the config file was from the point-of-view of the INITIATOR + + // INITIATOR mode input signals + + // INITIATOR mode output signals + tri [$bits(caliptra_otp_ctrl_pkg::lc_otp_vendor_test_req_t)-1:0] lc_otp_vendor_test_i_i; + reg [$bits(caliptra_otp_ctrl_pkg::lc_otp_vendor_test_req_t)-1:0] lc_otp_vendor_test_i_o = 'bz; + tri [$bits(caliptra_otp_ctrl_pkg::lc_otp_program_req_t)-1:0] lc_otp_program_i_i; + reg [$bits(caliptra_otp_ctrl_pkg::lc_otp_program_req_t)-1:0] lc_otp_program_i_o = 'bz; + tri [$bits(lc_ctrl_pkg::lc_tx_t)-1:0] lc_dft_en_i_i; + reg [$bits(lc_ctrl_pkg::lc_tx_t)-1:0] lc_dft_en_i_o = 'bz; + tri [$bits(lc_ctrl_pkg::lc_tx_t)-1:0] lc_escalate_en_i_i; + reg [$bits(lc_ctrl_pkg::lc_tx_t)-1:0] lc_escalate_en_i_o = 'bz; + tri [$bits(lc_ctrl_pkg::lc_tx_t)-1:0] lc_check_byp_en_i_i; + reg [$bits(lc_ctrl_pkg::lc_tx_t)-1:0] lc_check_byp_en_i_o = 'bz; + + // Bi-directional signals + + + assign clk_i_i = bus.clk_i; + assign rst_ni_i = bus.rst_ni; + + // These are signals marked as 'input' by the config file, but the signals will be + // driven by this BFM if put into RESPONDER mode (flipping all signal directions around) + + + // These are signals marked as 'output' by the config file, but the outputs will + // not be driven by this BFM unless placed in INITIATOR mode. + assign bus.lc_otp_vendor_test_i = (initiator_responder == INITIATOR) ? lc_otp_vendor_test_i_o : 'bz; + assign lc_otp_vendor_test_i_i = bus.lc_otp_vendor_test_i; + assign bus.lc_otp_program_i = (initiator_responder == INITIATOR) ? lc_otp_program_i_o : 'bz; + assign lc_otp_program_i_i = bus.lc_otp_program_i; + assign bus.lc_dft_en_i = (initiator_responder == INITIATOR) ? lc_dft_en_i_o : 'bz; + assign lc_dft_en_i_i = bus.lc_dft_en_i; + assign bus.lc_escalate_en_i = (initiator_responder == INITIATOR) ? lc_escalate_en_i_o : 'bz; + assign lc_escalate_en_i_i = bus.lc_escalate_en_i; + assign bus.lc_check_byp_en_i = (initiator_responder == INITIATOR) ? lc_check_byp_en_i_o : 'bz; + assign lc_check_byp_en_i_i = bus.lc_check_byp_en_i; + + // Proxy handle to UVM driver + fuse_ctrl_lc_otp_in_pkg::fuse_ctrl_lc_otp_in_driver proxy; + // pragma tbx oneway proxy.my_function_name_in_uvm_driver + + // **************************************************************************** + // **************************************************************************** + // Macros that define structs located in fuse_ctrl_lc_otp_in_macros.svh + // **************************************************************************** + // Struct for passing configuration data from fuse_ctrl_lc_otp_in_driver to this BFM + // **************************************************************************** + `fuse_ctrl_lc_otp_in_CONFIGURATION_STRUCT + // **************************************************************************** + // Structs for INITIATOR and RESPONDER data flow + //******************************************************************* + // Initiator macro used by fuse_ctrl_lc_otp_in_driver and fuse_ctrl_lc_otp_in_driver_bfm + // to communicate initiator driven data to fuse_ctrl_lc_otp_in_driver_bfm. + `fuse_ctrl_lc_otp_in_INITIATOR_STRUCT + fuse_ctrl_lc_otp_in_initiator_s initiator_struct; + // Responder macro used by fuse_ctrl_lc_otp_in_driver and fuse_ctrl_lc_otp_in_driver_bfm + // to communicate Responder driven data to fuse_ctrl_lc_otp_in_driver_bfm. + `fuse_ctrl_lc_otp_in_RESPONDER_STRUCT + fuse_ctrl_lc_otp_in_responder_s responder_struct; + + // **************************************************************************** +// pragma uvmf custom reset_condition_and_response begin + // Always block used to return signals to reset value upon assertion of reset + always @( negedge rst_ni_i ) + begin + // RESPONDER mode output signals + // INITIATOR mode output signals + lc_otp_vendor_test_i_o <= 'bz; + lc_otp_program_i_o <= 'bz; + lc_dft_en_i_o <= 'bz; + lc_escalate_en_i_o <= 'bz; + lc_check_byp_en_i_o <= 'bz; + // Bi-directional signals + + end +// pragma uvmf custom reset_condition_and_response end + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the driver BFM. It is called by the driver within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the driver BFM needs to be aware of the new configuration + // variables. + // + + function void configure(fuse_ctrl_lc_otp_in_configuration_s fuse_ctrl_lc_otp_in_configuration_arg); // pragma tbx xtf + initiator_responder = fuse_ctrl_lc_otp_in_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + +// pragma uvmf custom initiate_and_get_response begin +// **************************************************************************** +// UVMF_CHANGE_ME +// This task is used by an initator. The task first initiates a transfer then +// waits for the responder to complete the transfer. + task initiate_and_get_response( + // This argument passes transaction variables used by an initiator + // to perform the initial part of a protocol transfer. The values + // come from a sequence item created in a sequence. + input fuse_ctrl_lc_otp_in_initiator_s fuse_ctrl_lc_otp_in_initiator_struct, + // This argument is used to send data received from the responder + // back to the sequence item. The sequence item is returned to the sequence. + output fuse_ctrl_lc_otp_in_responder_s fuse_ctrl_lc_otp_in_responder_struct + );// pragma tbx xtf + // + // Members within the fuse_ctrl_lc_otp_in_initiator_struct: + // lc_ctrl_pkg::lc_tx_t lc_dft_en_i ; + // lc_ctrl_pkg::lc_tx_t lc_escalate_en_i ; + // lc_ctrl_pkg::lc_tx_t lc_check_byp_en_i ; + // Members within the fuse_ctrl_lc_otp_in_responder_struct: + // lc_ctrl_pkg::lc_tx_t lc_dft_en_i ; + // lc_ctrl_pkg::lc_tx_t lc_escalate_en_i ; + // lc_ctrl_pkg::lc_tx_t lc_check_byp_en_i ; + initiator_struct = fuse_ctrl_lc_otp_in_initiator_struct; + // + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clk_i_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available initiator input and inout signals listed. + // Initiator input signals + // Initiator inout signals + // How to assign a signal from an initiator struct member named xyz. + // All available initiator output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Initiator output signals + // lc_otp_vendor_test_i_o <= fuse_ctrl_lc_otp_in_initiator_struct.xyz; // [$bits(lc_otp_vendor_test_req_t)-1:0] + // lc_otp_program_i_o <= fuse_ctrl_lc_otp_in_initiator_struct.xyz; // [$bits(lc_otp_program_req_t)-1:0] + // lc_dft_en_i_o <= fuse_ctrl_lc_otp_in_initiator_struct.xyz; // [$bits(lc_ctrl_pkg::lc_tx_t)-1:0] + // lc_escalate_en_i_o <= fuse_ctrl_lc_otp_in_initiator_struct.xyz; // [$bits(lc_ctrl_pkg::lc_tx_t)-1:0] + // lc_check_byp_en_i_o <= fuse_ctrl_lc_otp_in_initiator_struct.xyz; // [$bits(lc_ctrl_pkg::lc_tx_t)-1:0] + // Initiator inout signals + // Initiate a transfer using the data received. + @(posedge clk_i_i); + @(posedge clk_i_i); + // Wait for the responder to complete the transfer then place the responder data into + // fuse_ctrl_lc_otp_in_responder_struct. + @(posedge clk_i_i); + @(posedge clk_i_i); + responder_struct = fuse_ctrl_lc_otp_in_responder_struct; + endtask +// pragma uvmf custom initiate_and_get_response end + +// pragma uvmf custom respond_and_wait_for_next_transfer begin +// **************************************************************************** +// The first_transfer variable is used to prevent completing a transfer in the +// first call to this task. For the first call to this task, there is not +// current transfer to complete. +bit first_transfer=1; + +// UVMF_CHANGE_ME +// This task is used by a responder. The task first completes the current +// transfer in progress then waits for the initiator to start the next transfer. + task respond_and_wait_for_next_transfer( + // This argument is used to send data received from the initiator + // back to the sequence item. The sequence determines how to respond. + output fuse_ctrl_lc_otp_in_initiator_s fuse_ctrl_lc_otp_in_initiator_struct, + // This argument passes transaction variables used by a responder + // to complete a protocol transfer. The values come from a sequence item. + input fuse_ctrl_lc_otp_in_responder_s fuse_ctrl_lc_otp_in_responder_struct + );// pragma tbx xtf + // Variables within the fuse_ctrl_lc_otp_in_initiator_struct: + // lc_ctrl_pkg::lc_tx_t lc_dft_en_i ; + // lc_ctrl_pkg::lc_tx_t lc_escalate_en_i ; + // lc_ctrl_pkg::lc_tx_t lc_check_byp_en_i ; + // Variables within the fuse_ctrl_lc_otp_in_responder_struct: + // lc_ctrl_pkg::lc_tx_t lc_dft_en_i ; + // lc_ctrl_pkg::lc_tx_t lc_escalate_en_i ; + // lc_ctrl_pkg::lc_tx_t lc_check_byp_en_i ; + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clk_i_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available responder input and inout signals listed. + // Responder input signals + // fuse_ctrl_lc_otp_in_responder_struct.xyz = lc_otp_vendor_test_i_i; // [$bits(lc_otp_vendor_test_req_t)-1:0] + // fuse_ctrl_lc_otp_in_responder_struct.xyz = lc_otp_program_i_i; // [$bits(lc_otp_program_req_t)-1:0] + // fuse_ctrl_lc_otp_in_responder_struct.xyz = lc_dft_en_i_i; // [$bits(lc_ctrl_pkg::lc_tx_t)-1:0] + // fuse_ctrl_lc_otp_in_responder_struct.xyz = lc_escalate_en_i_i; // [$bits(lc_ctrl_pkg::lc_tx_t)-1:0] + // fuse_ctrl_lc_otp_in_responder_struct.xyz = lc_check_byp_en_i_i; // [$bits(lc_ctrl_pkg::lc_tx_t)-1:0] + // Responder inout signals + // How to assign a signal, named xyz, from an initiator struct member. + // All available responder output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Responder output signals + // Responder inout signals + + @(posedge clk_i_i); + if (!first_transfer) begin + // Perform transfer response here. + // Reply using data recieved in the fuse_ctrl_lc_otp_in_responder_struct. + @(posedge clk_i_i); + // Reply using data recieved in the transaction handle. + @(posedge clk_i_i); + end + // Wait for next transfer then gather info from intiator about the transfer. + // Place the data into the fuse_ctrl_lc_otp_in_initiator_struct. + @(posedge clk_i_i); + @(posedge clk_i_i); + first_transfer = 0; + endtask +// pragma uvmf custom respond_and_wait_for_next_transfer end + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_if.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_if.sv new file mode 100644 index 0000000..7da88a3 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_if.sv @@ -0,0 +1,98 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface contains the fuse_ctrl_lc_otp_in interface signals. +// It is instantiated once per fuse_ctrl_lc_otp_in bus. Bus Functional Models, +// BFM's named fuse_ctrl_lc_otp_in_driver_bfm, are used to drive signals on the bus. +// BFM's named fuse_ctrl_lc_otp_in_monitor_bfm are used to monitor signals on the +// bus. This interface signal bundle is passed in the port list of +// the BFM in order to give the BFM access to the signals in this +// interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// This template can be used to connect a DUT to these signals +// +// .dut_signal_port(fuse_ctrl_lc_otp_in_bus.lc_otp_vendor_test_i), // Agent output +// .dut_signal_port(fuse_ctrl_lc_otp_in_bus.lc_otp_program_i), // Agent output +// .dut_signal_port(fuse_ctrl_lc_otp_in_bus.lc_dft_en_i), // Agent output +// .dut_signal_port(fuse_ctrl_lc_otp_in_bus.lc_escalate_en_i), // Agent output +// .dut_signal_port(fuse_ctrl_lc_otp_in_bus.lc_check_byp_en_i), // Agent output + +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_lc_otp_in_pkg_hdl::*; + +interface fuse_ctrl_lc_otp_in_if + + ( + input tri clk_i, + input tri rst_ni, + inout tri [$bits(caliptra_otp_ctrl_pkg::lc_otp_vendor_test_req_t)-1:0] lc_otp_vendor_test_i, + inout tri [$bits(caliptra_otp_ctrl_pkg::lc_otp_program_req_t)-1:0] lc_otp_program_i, + inout tri [$bits(lc_ctrl_pkg::lc_tx_t)-1:0] lc_dft_en_i, + inout tri [$bits(lc_ctrl_pkg::lc_tx_t)-1:0] lc_escalate_en_i, + inout tri [$bits(lc_ctrl_pkg::lc_tx_t)-1:0] lc_check_byp_en_i + ); + +modport monitor_port + ( + input clk_i, + input rst_ni, + input lc_otp_vendor_test_i, + input lc_otp_program_i, + input lc_dft_en_i, + input lc_escalate_en_i, + input lc_check_byp_en_i + ); + +modport initiator_port + ( + input clk_i, + input rst_ni, + output lc_otp_vendor_test_i, + output lc_otp_program_i, + output lc_dft_en_i, + output lc_escalate_en_i, + output lc_check_byp_en_i + ); + +modport responder_port + ( + input clk_i, + input rst_ni, + input lc_otp_vendor_test_i, + input lc_otp_program_i, + input lc_dft_en_i, + input lc_escalate_en_i, + input lc_check_byp_en_i + ); + + +// pragma uvmf custom interface_item_additional begin +// pragma uvmf custom interface_item_additional end + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_infact_coverage_strategy.csv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_infact_coverage_strategy.csv new file mode 100644 index 0000000..1c218e1 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_infact_coverage_strategy.csv @@ -0,0 +1,6 @@ +Global +auto_bin_max, 64 + +Name,Type,Include +rand_fields,coverpoint,=rand *.** + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_macros.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_macros.svh new file mode 100644 index 0000000..9ad130b --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_macros.svh @@ -0,0 +1,153 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains macros used with the fuse_ctrl_lc_otp_in package. +// These macros include packed struct definitions. These structs are +// used to pass data between classes, hvl, and BFM's, hdl. Use of +// structs are more efficient and simpler to modify. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_struct +// and from_struct methods defined in the macros below that are used in +// the fuse_ctrl_lc_otp_in_configuration class. +// + `define fuse_ctrl_lc_otp_in_CONFIGURATION_STRUCT \ +typedef struct packed { \ + uvmf_active_passive_t active_passive; \ + uvmf_initiator_responder_t initiator_responder; \ + } fuse_ctrl_lc_otp_in_configuration_s; + + `define fuse_ctrl_lc_otp_in_CONFIGURATION_TO_STRUCT_FUNCTION \ + virtual function fuse_ctrl_lc_otp_in_configuration_s to_struct();\ + fuse_ctrl_lc_otp_in_configuration_struct = \ + {\ + this.active_passive,\ + this.initiator_responder\ + };\ + return ( fuse_ctrl_lc_otp_in_configuration_struct );\ + endfunction + + `define fuse_ctrl_lc_otp_in_CONFIGURATION_FROM_STRUCT_FUNCTION \ + virtual function void from_struct(fuse_ctrl_lc_otp_in_configuration_s fuse_ctrl_lc_otp_in_configuration_struct);\ + {\ + this.active_passive,\ + this.initiator_responder \ + } = fuse_ctrl_lc_otp_in_configuration_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_monitor_struct +// and from_monitor_struct methods of the fuse_ctrl_lc_otp_in_transaction class. +// + `define fuse_ctrl_lc_otp_in_MONITOR_STRUCT typedef struct packed { \ + lc_ctrl_pkg::lc_tx_t lc_dft_en_i ; \ + lc_ctrl_pkg::lc_tx_t lc_escalate_en_i ; \ + lc_ctrl_pkg::lc_tx_t lc_check_byp_en_i ; \ + } fuse_ctrl_lc_otp_in_monitor_s; + + `define fuse_ctrl_lc_otp_in_TO_MONITOR_STRUCT_FUNCTION \ + virtual function fuse_ctrl_lc_otp_in_monitor_s to_monitor_struct();\ + fuse_ctrl_lc_otp_in_monitor_struct = \ + { \ + this.lc_dft_en_i , \ + this.lc_escalate_en_i , \ + this.lc_check_byp_en_i \ + };\ + return ( fuse_ctrl_lc_otp_in_monitor_struct);\ + endfunction\ + + `define fuse_ctrl_lc_otp_in_FROM_MONITOR_STRUCT_FUNCTION \ + virtual function void from_monitor_struct(fuse_ctrl_lc_otp_in_monitor_s fuse_ctrl_lc_otp_in_monitor_struct);\ + {\ + this.lc_dft_en_i , \ + this.lc_escalate_en_i , \ + this.lc_check_byp_en_i \ + } = fuse_ctrl_lc_otp_in_monitor_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_initiator_struct +// and from_initiator_struct methods of the fuse_ctrl_lc_otp_in_transaction class. +// Also update the comments in the driver BFM. +// + `define fuse_ctrl_lc_otp_in_INITIATOR_STRUCT typedef struct packed { \ + lc_ctrl_pkg::lc_tx_t lc_dft_en_i ; \ + lc_ctrl_pkg::lc_tx_t lc_escalate_en_i ; \ + lc_ctrl_pkg::lc_tx_t lc_check_byp_en_i ; \ + } fuse_ctrl_lc_otp_in_initiator_s; + + `define fuse_ctrl_lc_otp_in_TO_INITIATOR_STRUCT_FUNCTION \ + virtual function fuse_ctrl_lc_otp_in_initiator_s to_initiator_struct();\ + fuse_ctrl_lc_otp_in_initiator_struct = \ + {\ + this.lc_dft_en_i , \ + this.lc_escalate_en_i , \ + this.lc_check_byp_en_i \ + };\ + return ( fuse_ctrl_lc_otp_in_initiator_struct);\ + endfunction + + `define fuse_ctrl_lc_otp_in_FROM_INITIATOR_STRUCT_FUNCTION \ + virtual function void from_initiator_struct(fuse_ctrl_lc_otp_in_initiator_s fuse_ctrl_lc_otp_in_initiator_struct);\ + {\ + this.lc_dft_en_i , \ + this.lc_escalate_en_i , \ + this.lc_check_byp_en_i \ + } = fuse_ctrl_lc_otp_in_initiator_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_responder_struct +// and from_responder_struct methods of the fuse_ctrl_lc_otp_in_transaction class. +// Also update the comments in the driver BFM. +// + `define fuse_ctrl_lc_otp_in_RESPONDER_STRUCT typedef struct packed { \ + lc_ctrl_pkg::lc_tx_t lc_dft_en_i ; \ + lc_ctrl_pkg::lc_tx_t lc_escalate_en_i ; \ + lc_ctrl_pkg::lc_tx_t lc_check_byp_en_i ; \ + } fuse_ctrl_lc_otp_in_responder_s; + + `define fuse_ctrl_lc_otp_in_TO_RESPONDER_STRUCT_FUNCTION \ + virtual function fuse_ctrl_lc_otp_in_responder_s to_responder_struct();\ + fuse_ctrl_lc_otp_in_responder_struct = \ + {\ + this.lc_dft_en_i , \ + this.lc_escalate_en_i , \ + this.lc_check_byp_en_i \ + };\ + return ( fuse_ctrl_lc_otp_in_responder_struct);\ + endfunction + + `define fuse_ctrl_lc_otp_in_FROM_RESPONDER_STRUCT_FUNCTION \ + virtual function void from_responder_struct(fuse_ctrl_lc_otp_in_responder_s fuse_ctrl_lc_otp_in_responder_struct);\ + {\ + this.lc_dft_en_i , \ + this.lc_escalate_en_i , \ + this.lc_check_byp_en_i \ + } = fuse_ctrl_lc_otp_in_responder_struct;\ + endfunction +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_monitor.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_monitor.svh new file mode 100644 index 0000000..f046d7e --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_monitor.svh @@ -0,0 +1,101 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class receives fuse_ctrl_lc_otp_in transactions observed by the +// fuse_ctrl_lc_otp_in monitor BFM and broadcasts them through the analysis port +// on the agent. It accesses the monitor BFM through the monitor +// task. This UVM component captures transactions +// for viewing in the waveform viewer if the +// enable_transaction_viewing flag is set in the configuration. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_lc_otp_in_monitor extends uvmf_monitor_base #( + .CONFIG_T(fuse_ctrl_lc_otp_in_configuration ), + .BFM_BIND_T(virtual fuse_ctrl_lc_otp_in_monitor_bfm ), + .TRANS_T(fuse_ctrl_lc_otp_in_transaction )); + + `uvm_component_utils( fuse_ctrl_lc_otp_in_monitor ) + +// Structure used to pass data from monitor BFM to monitor class in agent. +// Use to_monitor_struct function to pack transaction variables into structure. +// Use from_monitor_struct function to unpack transaction variables from structure. +`fuse_ctrl_lc_otp_in_MONITOR_STRUCT + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the monitor BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// monitor BFM. This allows the monitor BFM to call the notify_transaction +// function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// *************************************************************************** + virtual task run_phase(uvm_phase phase); + // Start monitor BFM thread and don't call super.run() in order to + // override the default monitor proxy 'pull' behavior with the more + // emulation-friendly BFM 'push' approach using the notify_transaction + // function below + bfm.start_monitoring(); + endtask + +// ************************************************************************** + +// This function is called by the monitor BFM. It receives data observed by the +// monitor BFM. Data is passed using the fuse_ctrl_lc_otp_in_monitor_struct. + virtual function void notify_transaction(input fuse_ctrl_lc_otp_in_monitor_s fuse_ctrl_lc_otp_in_monitor_struct); + + + trans = new("trans"); + trans.from_monitor_struct(fuse_ctrl_lc_otp_in_monitor_struct); + trans.start_time = time_stamp; + trans.end_time = $time; + time_stamp = trans.end_time; + + analyze(trans); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_monitor_bfm.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_monitor_bfm.sv new file mode 100644 index 0000000..68a74b8 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_monitor_bfm.sv @@ -0,0 +1,202 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface performs the fuse_ctrl_lc_otp_in signal monitoring. +// It is accessed by the uvm fuse_ctrl_lc_otp_in monitor through a virtual +// interface handle in the fuse_ctrl_lc_otp_in configuration. It monitors the +// signals passed in through the port connection named bus of +// type fuse_ctrl_lc_otp_in_if. +// +// Input signals from the fuse_ctrl_lc_otp_in_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// Interface functions and tasks used by UVM components: +// monitor(inout TRANS_T txn); +// This task receives the transaction, txn, from the +// UVM monitor and then populates variables in txn +// from values observed on bus activity. This task +// blocks until an operation on the fuse_ctrl_lc_otp_in bus is complete. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_lc_otp_in_pkg_hdl::*; +`include "src/fuse_ctrl_lc_otp_in_macros.svh" + + +interface fuse_ctrl_lc_otp_in_monitor_bfm + ( fuse_ctrl_lc_otp_in_if bus ); + // The pragma below and additional ones in-lined further down are for running this BFM on Veloce + // pragma attribute fuse_ctrl_lc_otp_in_monitor_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: ", ), + UVM_DEBUG) +end +`endif + + + // Structure used to pass transaction data from monitor BFM to monitor class in agent. +`fuse_ctrl_lc_otp_in_MONITOR_STRUCT + fuse_ctrl_lc_otp_in_monitor_s fuse_ctrl_lc_otp_in_monitor_struct; + + // Structure used to pass configuration data from monitor class to monitor BFM. + `fuse_ctrl_lc_otp_in_CONFIGURATION_STRUCT + + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + tri clk_i_i; + tri rst_ni_i; + tri [$bits(caliptra_otp_ctrl_pkg::lc_otp_vendor_test_req_t)-1:0] lc_otp_vendor_test_i_i; + tri [$bits(caliptra_otp_ctrl_pkg::lc_otp_program_req_t)-1:0] lc_otp_program_i_i; + tri [$bits(lc_ctrl_pkg::lc_tx_t)-1:0] lc_dft_en_i_i; + tri [$bits(lc_ctrl_pkg::lc_tx_t)-1:0] lc_escalate_en_i_i; + tri [$bits(lc_ctrl_pkg::lc_tx_t)-1:0] lc_check_byp_en_i_i; + assign clk_i_i = bus.clk_i; + assign rst_ni_i = bus.rst_ni; + assign lc_otp_vendor_test_i_i = bus.lc_otp_vendor_test_i; + assign lc_otp_program_i_i = bus.lc_otp_program_i; + assign lc_dft_en_i_i = bus.lc_dft_en_i; + assign lc_escalate_en_i_i = bus.lc_escalate_en_i; + assign lc_check_byp_en_i_i = bus.lc_check_byp_en_i; + + // Proxy handle to UVM monitor + fuse_ctrl_lc_otp_in_pkg::fuse_ctrl_lc_otp_in_monitor proxy; + // pragma tbx oneway proxy.notify_transaction + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + task wait_for_reset();// pragma tbx xtf + @(posedge clk_i_i) ; + do_wait_for_reset(); + endtask + + // **************************************************************************** + task do_wait_for_reset(); + // pragma uvmf custom reset_condition begin + wait ( rst_ni_i === 1 ) ; + @(posedge clk_i_i) ; + // pragma uvmf custom reset_condition end + endtask + + //****************************************************************** + + task wait_for_num_clocks(input int unsigned count); // pragma tbx xtf + @(posedge clk_i_i); + + repeat (count-1) @(posedge clk_i_i); + endtask + + //****************************************************************** + event go; + function void start_monitoring();// pragma tbx xtf + -> go; + endfunction + + // **************************************************************************** + initial begin + @go; + forever begin + @(posedge clk_i_i); + do_monitor( fuse_ctrl_lc_otp_in_monitor_struct ); + + + proxy.notify_transaction( fuse_ctrl_lc_otp_in_monitor_struct ); + + end + end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the monitor BFM. It is called by the monitor within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the monitor BFM needs to be aware of the new configuration + // variables. + // + function void configure(fuse_ctrl_lc_otp_in_configuration_s fuse_ctrl_lc_otp_in_configuration_arg); // pragma tbx xtf + initiator_responder = fuse_ctrl_lc_otp_in_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + + + // **************************************************************************** + + task do_monitor(output fuse_ctrl_lc_otp_in_monitor_s fuse_ctrl_lc_otp_in_monitor_struct); + // + // Available struct members: + // // fuse_ctrl_lc_otp_in_monitor_struct.lc_dft_en_i + // // fuse_ctrl_lc_otp_in_monitor_struct.lc_escalate_en_i + // // fuse_ctrl_lc_otp_in_monitor_struct.lc_check_byp_en_i + // // + // Reference code; + // How to wait for signal value + // while (control_signal === 1'b1) @(posedge clk_i_i); + // + // How to assign a struct member, named xyz, from a signal. + // All available input signals listed. + // fuse_ctrl_lc_otp_in_monitor_struct.xyz = lc_otp_vendor_test_i_i; // [$bits(caliptra_otp_ctrl_pkg::lc_otp_vendor_test_req_t)-1:0] + // fuse_ctrl_lc_otp_in_monitor_struct.xyz = lc_otp_program_i_i; // [$bits(caliptra_otp_ctrl_pkg::lc_otp_program_req_t)-1:0] + // fuse_ctrl_lc_otp_in_monitor_struct.xyz = lc_dft_en_i_i; // [$bits(lc_ctrl_pkg::lc_tx_t)-1:0] + // fuse_ctrl_lc_otp_in_monitor_struct.xyz = lc_escalate_en_i_i; // [$bits(lc_ctrl_pkg::lc_tx_t)-1:0] + // fuse_ctrl_lc_otp_in_monitor_struct.xyz = lc_check_byp_en_i_i; // [$bits(lc_ctrl_pkg::lc_tx_t)-1:0] + // pragma uvmf custom do_monitor begin + // UVMF_CHANGE_ME : Implement protocol monitoring. The commented reference code + // below are examples of how to capture signal values and assign them to + // structure members. All available input signals are listed. The 'while' + // code example shows how to wait for a synchronous flow control signal. This + // task should return when a complete transfer has been observed. Once this task is + // exited with captured values, it is then called again to wait for and observe + // the next transfer. One clock cycle is consumed between calls to do_monitor. + @(posedge clk_i_i); + @(posedge clk_i_i); + @(posedge clk_i_i); + @(posedge clk_i_i); + // pragma uvmf custom do_monitor end + endtask + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_random_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_random_sequence.svh new file mode 100644 index 0000000..477393c --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_random_sequence.svh @@ -0,0 +1,67 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This sequences randomizes the fuse_ctrl_lc_otp_in transaction and sends it +// to the UVM driver. +// +// This sequence constructs and randomizes a fuse_ctrl_lc_otp_in_transaction. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_lc_otp_in_random_sequence + extends fuse_ctrl_lc_otp_in_sequence_base ; + + `uvm_object_utils( fuse_ctrl_lc_otp_in_random_sequence ) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //***************************************************************** + function new(string name = ""); + super.new(name); + endfunction: new + + // **************************************************************************** + // TASK : body() + // This task is automatically executed when this sequence is started using the + // start(sequencerHandle) task. + // + task body(); + + // Construct the transaction + req=fuse_ctrl_lc_otp_in_transaction::type_id::create("req"); + start_item(req); + // Randomize the transaction + if(!req.randomize()) `uvm_fatal("SEQ", "fuse_ctrl_lc_otp_in_random_sequence::body()-fuse_ctrl_lc_otp_in_transaction randomization failed") + // Send the transaction to the fuse_ctrl_lc_otp_in_driver_bfm via the sequencer and fuse_ctrl_lc_otp_in_driver. + finish_item(req); + `uvm_info("SEQ", {"Response:",req.convert2string()},UVM_MEDIUM) + + endtask + +endclass: fuse_ctrl_lc_otp_in_random_sequence + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_responder_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_responder_sequence.svh new file mode 100644 index 0000000..e414968 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_responder_sequence.svh @@ -0,0 +1,63 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class can be used to provide stimulus when an interface +// has been configured to run in a responder mode. It +// will never finish by default, always going back to the driver +// and driver BFM for the next transaction with which to respond. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_lc_otp_in_responder_sequence + extends fuse_ctrl_lc_otp_in_sequence_base ; + + `uvm_object_utils( fuse_ctrl_lc_otp_in_responder_sequence ) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "fuse_ctrl_lc_otp_in_responder_sequence"); + super.new(name); + endfunction + + task body(); + req=fuse_ctrl_lc_otp_in_transaction::type_id::create("req"); + forever begin + start_item(req); + finish_item(req); + // pragma uvmf custom body begin + // UVMF_CHANGE_ME : Do something here with the resulting req item. The + // finish_item() call above will block until the req transaction is ready + // to be handled by the responder sequence. + // If this was an item that required a response, the expectation is + // that the response should be populated within this transaction now. + `uvm_info("SEQ",$sformatf("Processed txn: %s",req.convert2string()),UVM_HIGH) + // pragma uvmf custom body end + end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_sequence_base.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_sequence_base.svh new file mode 100644 index 0000000..83a122c --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_sequence_base.svh @@ -0,0 +1,110 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the class used as the base class for all sequences +// for this interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_lc_otp_in_sequence_base extends uvmf_sequence_base #( + .REQ(fuse_ctrl_lc_otp_in_transaction ), + .RSP(fuse_ctrl_lc_otp_in_transaction )); + + `uvm_object_utils( fuse_ctrl_lc_otp_in_sequence_base ) + + // variables + typedef fuse_ctrl_lc_otp_in_transaction fuse_ctrl_lc_otp_in_transaction_req_t; + fuse_ctrl_lc_otp_in_transaction_req_t req; + typedef fuse_ctrl_lc_otp_in_transaction fuse_ctrl_lc_otp_in_transaction_rsp_t; + fuse_ctrl_lc_otp_in_transaction_rsp_t rsp; + + // Event for identifying when a response was received from the sequencer + event new_rsp; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // TASK : get_responses() + // This task recursively gets sequence item responses from the sequencer. + // + virtual task get_responses(); + fork + begin + // Block until new rsp available + get_response(rsp); + // New rsp received. Indicate to sequence using event. + ->new_rsp; + // Display the received response transaction + `uvm_info("SEQ", {"New response transaction:",rsp.convert2string()}, UVM_MEDIUM) + end + join_none + endtask + + // **************************************************************************** + // TASK : pre_body() + // This task is called automatically when start is called with call_pre_post set to 1 (default). + // By calling get_responses() within pre_body() any derived sequences are automatically + // processing response transactions. Only un-comment this call to get_responses() if you + // have configured the interface driver to utilize the response transaction path by setting + // the configuration variable "return_transaction_response" to 1. Otherwise it is possible + // to impact runtime performance and memory utilization. + // + virtual task pre_body(); + // pragma uvmf custom pre_body begin +// get_responses(); + // pragma uvmf custom pre_body end + endtask + + // **************************************************************************** + // TASK : body() + // This task is called automatically when start is called. This sequence sends + // a req sequence item to the sequencer identified as an argument in the call + // to start. + // + virtual task body(); + // pragma uvmf custom body begin + start_item(req); + finish_item(req); + // pragma uvmf custom body end + endtask + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name =""); + super.new( name ); + // pragma uvmf custom new begin + req = fuse_ctrl_lc_otp_in_transaction_req_t::type_id::create("req"); + rsp = fuse_ctrl_lc_otp_in_transaction_rsp_t::type_id::create("rsp"); + // pragma uvmf custom new end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_transaction.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_transaction.svh new file mode 100644 index 0000000..187b648 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_transaction.svh @@ -0,0 +1,201 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class defines the variables required for an fuse_ctrl_lc_otp_in +// transaction. Class variables to be displayed in waveform transaction +// viewing are added to the transaction viewing stream in the add_to_wave +// function. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_lc_otp_in_transaction extends uvmf_transaction_base; + + `uvm_object_utils( fuse_ctrl_lc_otp_in_transaction ) + + lc_ctrl_pkg::lc_tx_t lc_dft_en_i ; + lc_ctrl_pkg::lc_tx_t lc_escalate_en_i ; + lc_ctrl_pkg::lc_tx_t lc_check_byp_en_i ; + + //Constraints for the transaction variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //******************************************************************* + //******************************************************************* + // Macros that define structs and associated functions are + // located in fuse_ctrl_lc_otp_in_macros.svh + + //******************************************************************* + // Monitor macro used by fuse_ctrl_lc_otp_in_monitor and fuse_ctrl_lc_otp_in_monitor_bfm + // This struct is defined in fuse_ctrl_lc_otp_in_macros.svh + `fuse_ctrl_lc_otp_in_MONITOR_STRUCT + fuse_ctrl_lc_otp_in_monitor_s fuse_ctrl_lc_otp_in_monitor_struct; + //******************************************************************* + // FUNCTION: to_monitor_struct() + // This function packs transaction variables into a fuse_ctrl_lc_otp_in_monitor_s + // structure. The function returns the handle to the fuse_ctrl_lc_otp_in_monitor_struct. + // This function is defined in fuse_ctrl_lc_otp_in_macros.svh + `fuse_ctrl_lc_otp_in_TO_MONITOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_monitor_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_lc_otp_in_macros.svh + `fuse_ctrl_lc_otp_in_FROM_MONITOR_STRUCT_FUNCTION + + //******************************************************************* + // Initiator macro used by fuse_ctrl_lc_otp_in_driver and fuse_ctrl_lc_otp_in_driver_bfm + // to communicate initiator driven data to fuse_ctrl_lc_otp_in_driver_bfm. + // This struct is defined in fuse_ctrl_lc_otp_in_macros.svh + `fuse_ctrl_lc_otp_in_INITIATOR_STRUCT + fuse_ctrl_lc_otp_in_initiator_s fuse_ctrl_lc_otp_in_initiator_struct; + //******************************************************************* + // FUNCTION: to_initiator_struct() + // This function packs transaction variables into a fuse_ctrl_lc_otp_in_initiator_s + // structure. The function returns the handle to the fuse_ctrl_lc_otp_in_initiator_struct. + // This function is defined in fuse_ctrl_lc_otp_in_macros.svh + `fuse_ctrl_lc_otp_in_TO_INITIATOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_initiator_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_lc_otp_in_macros.svh + `fuse_ctrl_lc_otp_in_FROM_INITIATOR_STRUCT_FUNCTION + + //******************************************************************* + // Responder macro used by fuse_ctrl_lc_otp_in_driver and fuse_ctrl_lc_otp_in_driver_bfm + // to communicate Responder driven data to fuse_ctrl_lc_otp_in_driver_bfm. + // This struct is defined in fuse_ctrl_lc_otp_in_macros.svh + `fuse_ctrl_lc_otp_in_RESPONDER_STRUCT + fuse_ctrl_lc_otp_in_responder_s fuse_ctrl_lc_otp_in_responder_struct; + //******************************************************************* + // FUNCTION: to_responder_struct() + // This function packs transaction variables into a fuse_ctrl_lc_otp_in_responder_s + // structure. The function returns the handle to the fuse_ctrl_lc_otp_in_responder_struct. + // This function is defined in fuse_ctrl_lc_otp_in_macros.svh + `fuse_ctrl_lc_otp_in_TO_RESPONDER_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_responder_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_lc_otp_in_macros.svh + `fuse_ctrl_lc_otp_in_FROM_RESPONDER_STRUCT_FUNCTION + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + endfunction + + // **************************************************************************** + // FUNCTION: convert2string() + // This function converts all variables in this class to a single string for + // logfile reporting. + // + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + // UVMF_CHANGE_ME : Customize format if desired. + return $sformatf("lc_dft_en_i:0x%x lc_escalate_en_i:0x%x lc_check_byp_en_i:0x%x ",lc_dft_en_i,lc_escalate_en_i,lc_check_byp_en_i); + // pragma uvmf custom convert2string end + endfunction + + //******************************************************************* + // FUNCTION: do_print() + // This function is automatically called when the .print() function + // is called on this class. + // + virtual function void do_print(uvm_printer printer); + // pragma uvmf custom do_print begin + // UVMF_CHANGE_ME : Current contents of do_print allows for the use of UVM 1.1d, 1.2 or P1800.2. + // Update based on your own printing preference according to your preferred UVM version + $display(convert2string()); + // pragma uvmf custom do_print end + endfunction + + //******************************************************************* + // FUNCTION: do_compare() + // This function is automatically called when the .compare() function + // is called on this class. + // + virtual function bit do_compare (uvm_object rhs, uvm_comparer comparer); + fuse_ctrl_lc_otp_in_transaction RHS; + if (!$cast(RHS,rhs)) return 0; + // pragma uvmf custom do_compare begin + // UVMF_CHANGE_ME : Eliminate comparison of variables not to be used for compare + return (super.do_compare(rhs,comparer) + ); + // pragma uvmf custom do_compare end + endfunction + + //******************************************************************* + // FUNCTION: do_copy() + // This function is automatically called when the .copy() function + // is called on this class. + // + virtual function void do_copy (uvm_object rhs); + fuse_ctrl_lc_otp_in_transaction RHS; + assert($cast(RHS,rhs)); + // pragma uvmf custom do_copy begin + super.do_copy(rhs); + this.lc_dft_en_i = RHS.lc_dft_en_i; + this.lc_escalate_en_i = RHS.lc_escalate_en_i; + this.lc_check_byp_en_i = RHS.lc_check_byp_en_i; + // pragma uvmf custom do_copy end + endfunction + + // **************************************************************************** + // FUNCTION: add_to_wave() + // This function is used to display variables in this class in the waveform + // viewer. The start_time and end_time variables must be set before this + // function is called. If the start_time and end_time variables are not set + // the transaction will be hidden at 0ns on the waveform display. + // + virtual function void add_to_wave(int transaction_viewing_stream_h); + `ifdef QUESTA + if (transaction_view_h == 0) begin + transaction_view_h = $begin_transaction(transaction_viewing_stream_h,"fuse_ctrl_lc_otp_in_transaction",start_time); + end + super.add_to_wave(transaction_view_h); + // pragma uvmf custom add_to_wave begin + // UVMF_CHANGE_ME : Color can be applied to transaction entries based on content, example below + // case() + // 1 : $add_color(transaction_view_h,"red"); + // default : $add_color(transaction_view_h,"grey"); + // endcase + // UVMF_CHANGE_ME : Eliminate transaction variables not wanted in transaction viewing in the waveform viewer + $add_attribute(transaction_view_h,lc_dft_en_i,"lc_dft_en_i"); + $add_attribute(transaction_view_h,lc_escalate_en_i,"lc_escalate_en_i"); + $add_attribute(transaction_view_h,lc_check_byp_en_i,"lc_check_byp_en_i"); + // pragma uvmf custom add_to_wave end + $end_transaction(transaction_view_h,end_time); + $free_transaction(transaction_view_h); + `endif // QUESTA + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_transaction_coverage.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_transaction_coverage.svh new file mode 100644 index 0000000..e5fa783 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_transaction_coverage.svh @@ -0,0 +1,86 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class records fuse_ctrl_lc_otp_in transaction information using +// a covergroup named fuse_ctrl_lc_otp_in_transaction_cg. An instance of this +// coverage component is instantiated in the uvmf_parameterized_agent +// if the has_coverage flag is set. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_lc_otp_in_transaction_coverage extends uvm_subscriber #(.T(fuse_ctrl_lc_otp_in_transaction )); + + `uvm_component_utils( fuse_ctrl_lc_otp_in_transaction_coverage ) + + T coverage_trans; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + covergroup fuse_ctrl_lc_otp_in_transaction_cg; + // pragma uvmf custom covergroup begin + // UVMF_CHANGE_ME : Add coverage bins, crosses, exclusions, etc. according to coverage needs. + option.auto_bin_max=1024; + option.per_instance=1; + lc_dft_en_i: coverpoint coverage_trans.lc_dft_en_i; + lc_escalate_en_i: coverpoint coverage_trans.lc_escalate_en_i; + lc_check_byp_en_i: coverpoint coverage_trans.lc_check_byp_en_i; + // pragma uvmf custom covergroup end + endgroup + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new(string name="", uvm_component parent=null); + super.new(name,parent); + fuse_ctrl_lc_otp_in_transaction_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that transaction variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + endfunction + + // **************************************************************************** + // FUNCTION : build_phase() + // This function is the standard UVM build_phase. + // + function void build_phase(uvm_phase phase); + fuse_ctrl_lc_otp_in_transaction_cg.set_inst_name($sformatf("fuse_ctrl_lc_otp_in_transaction_cg_%s",get_full_name())); + endfunction + + // **************************************************************************** + // FUNCTION: write (T t) + // This function is automatically executed when a transaction arrives on the + // analysis_export. It copies values from the variables in the transaction + // to local variables used to collect functional coverage. + // + virtual function void write (T t); + `uvm_info("COV","Received transaction",UVM_HIGH); + coverage_trans = t; + fuse_ctrl_lc_otp_in_transaction_cg.sample(); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_typedefs.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_typedefs.svh new file mode 100644 index 0000000..f2a7bdb --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_typedefs.svh @@ -0,0 +1,34 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the host server when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_typedefs_hdl.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_typedefs_hdl.svh new file mode 100644 index 0000000..0d58518 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/src/fuse_ctrl_lc_otp_in_typedefs_hdl.svh @@ -0,0 +1,35 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the emulator when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/yaml/fuse_ctrl_lc_otp_in_interface.yaml b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/yaml/fuse_ctrl_lc_otp_in_interface.yaml new file mode 100644 index 0000000..a380327 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_in_pkg/yaml/fuse_ctrl_lc_otp_in_interface.yaml @@ -0,0 +1,57 @@ +uvmf: + interfaces: + fuse_ctrl_lc_otp_in: + clock: clk_i + config_constraints: [] + config_vars: [] + existing_library_component: 'True' + gen_inbound_streaming_driver: 'False' + hdl_pkg_parameters: [] + hdl_typedefs: [] + hvl_pkg_parameters: [] + hvl_typedefs: [] + parameters: [] + ports: + - dir: output + name: lc_otp_vendor_test_i + reset_value: '''bz' + width: '[''$bits(caliptra_otp_ctrl_pkg::lc_otp_vendor_test_req_t)'']' + - dir: output + name: lc_otp_program_i + reset_value: '''bz' + width: '[''$bits(caliptra_otp_ctrl_pkg::lc_otp_program_req_t)'']' + - dir: output + name: lc_dft_en_i + reset_value: '''bz' + width: '[''$bits(lc_ctrl_pkg::lc_tx_t)'']' + - dir: output + name: lc_escalate_en_i + reset_value: '''bz' + width: '[''$bits(lc_ctrl_pkg::lc_tx_t)'']' + - dir: output + name: lc_check_byp_en_i + reset_value: '''bz' + width: '[''$bits(lc_ctrl_pkg::lc_tx_t)'']' + reset: rst_ni + reset_assertion_level: 'False' + transaction_constraints: [] + transaction_vars: + - comment: '' + iscompare: 'False' + isrand: 'False' + name: lc_dft_en_i + type: lc_ctrl_pkg::lc_tx_t + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: lc_escalate_en_i + type: lc_ctrl_pkg::lc_tx_t + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: lc_check_byp_en_i + type: lc_ctrl_pkg::lc_tx_t + unpacked_dimension: '' + use_dpi_link: 'False' diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/.project b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/.project new file mode 100644 index 0000000..42717ee --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/.project @@ -0,0 +1,30 @@ + + + fuse_ctrl_lc_otp_out_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/.svproject b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/.svproject new file mode 100644 index 0000000..fe0ca64 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/Makefile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/Makefile new file mode 100644 index 0000000..f975b19 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/Makefile @@ -0,0 +1,66 @@ +# fuse_ctrl_lc_otp_out interface packages source +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +fuse_ctrl_lc_otp_out_PKG = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_lc_otp_out_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_filelist_hvl.f + +fuse_ctrl_lc_otp_out_PKG_HDL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_lc_otp_out_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_filelist_hdl.f + +fuse_ctrl_lc_otp_out_PKG_XRTL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_lc_otp_out_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_filelist_xrtl.f + +COMP_fuse_ctrl_lc_otp_out_PKG_TGT_0 = q_comp_fuse_ctrl_lc_otp_out_pkg +COMP_fuse_ctrl_lc_otp_out_PKG_TGT_1 = v_comp_fuse_ctrl_lc_otp_out_pkg +COMP_fuse_ctrl_lc_otp_out_PKG_TGT = $(COMP_fuse_ctrl_lc_otp_out_PKG_TGT_$(USE_VELOCE)) + +comp_fuse_ctrl_lc_otp_out_pkg: $(COMP_fuse_ctrl_lc_otp_out_PKG_TGT) + +q_comp_fuse_ctrl_lc_otp_out_pkg: + $(HDL_COMP_CMD) $(fuse_ctrl_lc_otp_out_PKG_HDL) + $(HVL_COMP_CMD) $(fuse_ctrl_lc_otp_out_PKG) + $(HDL_COMP_CMD) $(fuse_ctrl_lc_otp_out_PKG_XRTL) + +v_comp_fuse_ctrl_lc_otp_out_pkg: + $(HVL_COMP_CMD) $(fuse_ctrl_lc_otp_out_PKG_HDL) + $(HVL_COMP_CMD) $(fuse_ctrl_lc_otp_out_PKG) + $(VELANALYZE_CMD) $(fuse_ctrl_lc_otp_out_PKG_HDL) + $(VELANALYZE_HVL_CMD) $(fuse_ctrl_lc_otp_out_PKG) + $(HDL_COMP_CMD) $(fuse_ctrl_lc_otp_out_PKG_XRTL) + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export fuse_ctrl_lc_otp_out_IF_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_lc_otp_out_pkg/dpi + +C_FILE_COMPILE_LIST_fuse_ctrl_lc_otp_out_pkg = \ + +O_FILE_COMPILE_LIST_fuse_ctrl_lc_otp_out_pkg = $(notdir $(C_FILE_COMPILE_LIST_fuse_ctrl_lc_otp_out_pkg:.c=.o)) + +GCC_COMP_ARGS_fuse_ctrl_lc_otp_out_pkg += -I$(fuse_ctrl_lc_otp_out_IF_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_fuse_ctrl_lc_otp_out_pkg += $(fuse_ctrl_lc_otp_out_IF_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_fuse_ctrl_lc_otp_out_pkg += \ + \ + -o .so + +comp_fuse_ctrl_lc_otp_out_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Interface C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_fuse_ctrl_lc_otp_out_pkg) $(C_FILE_COMPILE_LIST_fuse_ctrl_lc_otp_out_pkg) + @echo "--------------------------------" + @echo "Linking Interface C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_fuse_ctrl_lc_otp_out_pkg) $(O_FILE_COMPILE_LIST_fuse_ctrl_lc_otp_out_pkg) + @echo "--------------------------------" + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/compile.do b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/compile.do new file mode 100644 index 0000000..8073231 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/compile.do @@ -0,0 +1,14 @@ +# Tcl do file for compile of fuse_ctrl_lc_otp_out interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_lc_otp_out_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_filelist_hdl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_lc_otp_out_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_filelist_hvl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_lc_otp_out_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_filelist_xrtl.f \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out.compile new file mode 100644 index 0000000..f8a8ac4 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out.compile @@ -0,0 +1,3 @@ +needs: + - fuse_ctrl_lc_otp_out_hvl.compile + - fuse_ctrl_lc_otp_out_hdl.compile diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_bfm.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_bfm.vinfo new file mode 100644 index 0000000..0c1d35f --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_bfm.vinfo @@ -0,0 +1,6 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use fuse_ctrl_lc_otp_out_pkg_hdl.vinfo ++incdir+@vinfodir +src/fuse_ctrl_lc_otp_out_if.sv +src/fuse_ctrl_lc_otp_out_driver_bfm.sv +src/fuse_ctrl_lc_otp_out_monitor_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_common.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_common.compile new file mode 100644 index 0000000..42616d5 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_common.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +incdir: + - . + - ${uvm_path}/src +src: + - fuse_ctrl_lc_otp_out_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_filelist_hdl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_filelist_hdl.f new file mode 100644 index 0000000..dd3eb8a --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_filelist_hdl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_filelist_hvl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_filelist_hvl.f new file mode 100644 index 0000000..b0a13c6 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_filelist_hvl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_pkg.sv \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_filelist_xrtl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_filelist_xrtl.f new file mode 100644 index 0000000..48f620e --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_filelist_xrtl.f @@ -0,0 +1,3 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_if.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_monitor_bfm.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_driver_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_hdl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_hdl.compile new file mode 100644 index 0000000..2ce74cc --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_hdl.compile @@ -0,0 +1,9 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ./fuse_ctrl_lc_otp_out_common.compile +incdir: + - . +src: + - src/fuse_ctrl_lc_otp_out_if.sv + - src/fuse_ctrl_lc_otp_out_monitor_bfm.sv + - src/fuse_ctrl_lc_otp_out_driver_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_hvl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_hvl.compile new file mode 100644 index 0000000..d6a5b88 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_hvl.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ./fuse_ctrl_lc_otp_out_common.compile +incdir: + - . +src: + - fuse_ctrl_lc_otp_out_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_pkg.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_pkg.sv new file mode 100644 index 0000000..c18cea8 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_pkg.sv @@ -0,0 +1,91 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - + +// - +// - +// - + +// - +// - +// - + +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_lc_otp_out_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg_hdl::*; + import uvmf_base_pkg::*; + import fuse_ctrl_lc_otp_out_pkg_hdl::*; + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + `include "src/fuse_ctrl_lc_otp_out_macros.svh" + + export fuse_ctrl_lc_otp_out_pkg_hdl::*; + + + + // Parameters defined as HVL parameters + + `include "src/fuse_ctrl_lc_otp_out_typedefs.svh" + `include "src/fuse_ctrl_lc_otp_out_transaction.svh" + + `include "src/fuse_ctrl_lc_otp_out_configuration.svh" + `include "src/fuse_ctrl_lc_otp_out_driver.svh" + `include "src/fuse_ctrl_lc_otp_out_monitor.svh" + + `include "src/fuse_ctrl_lc_otp_out_transaction_coverage.svh" + `include "src/fuse_ctrl_lc_otp_out_sequence_base.svh" + `include "src/fuse_ctrl_lc_otp_out_random_sequence.svh" + + `include "src/fuse_ctrl_lc_otp_out_responder_sequence.svh" + `include "src/fuse_ctrl_lc_otp_out2reg_adapter.svh" + + `include "src/fuse_ctrl_lc_otp_out_agent.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new interface sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the interface package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_pkg.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_pkg.vinfo new file mode 100644 index 0000000..7a4f8b1 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_pkg.vinfo @@ -0,0 +1,4 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use fuse_ctrl_lc_otp_out_pkg_hdl.vinfo ++incdir+@vinfodir +fuse_ctrl_lc_otp_out_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_pkg_hdl.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_pkg_hdl.sv new file mode 100644 index 0000000..8987535 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_pkg_hdl.sv @@ -0,0 +1,52 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that needs to be compiled and synthesized +// for running on Veloce. +// +// CONTAINS: +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_lc_otp_out_pkg_hdl; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HDL parameters + + `include "src/fuse_ctrl_lc_otp_out_typedefs_hdl.svh" + `include "src/fuse_ctrl_lc_otp_out_macros.svh" + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_pkg_hdl.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_pkg_hdl.vinfo new file mode 100644 index 0000000..f662f8c --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_pkg_hdl.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +fuse_ctrl_lc_otp_out_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_pkg_sve.F b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_pkg_sve.F new file mode 100644 index 0000000..0483ef5 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_pkg_sve.F @@ -0,0 +1,10 @@ +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + ++incdir+. +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_filelist_hdl.f +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_lc_otp_out_pkg/fuse_ctrl_lc_otp_out_filelist_hvl.f diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out2reg_adapter.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out2reg_adapter.svh new file mode 100644 index 0000000..bd1fa55 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out2reg_adapter.svh @@ -0,0 +1,112 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the UVM register adapter for the fuse_ctrl_lc_otp_out interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_lc_otp_out2reg_adapter extends uvm_reg_adapter; + + `uvm_object_utils( fuse_ctrl_lc_otp_out2reg_adapter ) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //-------------------------------------------------------------------- + // new + //-------------------------------------------------------------------- + function new (string name = "fuse_ctrl_lc_otp_out2reg_adapter" ); + super.new(name); + // pragma uvmf custom new begin + // UVMF_CHANGE_ME : Configure the adapter regarding byte enables and provides response. + + // Does the protocol the Agent is modeling support byte enables? + // 0 = NO + // 1 = YES + supports_byte_enable = 0; + + // Does the Agent's Driver provide separate response sequence items? + // i.e. Does the driver call seq_item_port.put() + // and do the sequences call get_response()? + // 0 = NO + // 1 = YES + provides_responses = 0; + // pragma uvmf custom new end + + endfunction: new + + //-------------------------------------------------------------------- + // reg2bus + //-------------------------------------------------------------------- + virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw); + + fuse_ctrl_lc_otp_out_transaction trans_h = fuse_ctrl_lc_otp_out_transaction ::type_id::create("trans_h"); + + // pragma uvmf custom reg2bus begin + // UVMF_CHANGE_ME : Fill in the reg2bus adapter mapping registe fields to protocol fields. + + //Adapt the following for your sequence item type + // trans_h.op = (rw.kind == UVM_READ) ? WB_READ : WB_WRITE; + //Copy over address + // trans_h.addr = rw.addr; + //Copy over write data + // trans_h.data = rw.data; + + // pragma uvmf custom reg2bus end + + // Return the adapted transaction + return trans_h; + + endfunction: reg2bus + + //-------------------------------------------------------------------- + // bus2reg + //-------------------------------------------------------------------- + virtual function void bus2reg(uvm_sequence_item bus_item, + ref uvm_reg_bus_op rw); + fuse_ctrl_lc_otp_out_transaction trans_h; + if (!$cast(trans_h, bus_item)) begin + `uvm_fatal("ADAPT","Provided bus_item is not of the correct type") + return; + end + // pragma uvmf custom bus2reg begin + // UVMF_CHANGE_ME : Fill in the bus2reg adapter mapping protocol fields to register fields. + //Adapt the following for your sequence item type + //Copy over instruction type + // rw.kind = (trans_h.op == WB_WRITE) ? UVM_WRITE : UVM_READ; + //Copy over address + // rw.addr = trans_h.addr; + //Copy over read data + // rw.data = trans_h.data; + //Check for errors on the bus and return UVM_NOT_OK if there is an error + // rw.status = UVM_IS_OK; + // pragma uvmf custom bus2reg end + + endfunction: bus2reg + +endclass : fuse_ctrl_lc_otp_out2reg_adapter + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_agent.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_agent.svh new file mode 100644 index 0000000..2b6207d --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_agent.svh @@ -0,0 +1,67 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: Protocol specific agent class definition +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_lc_otp_out_agent extends uvmf_parameterized_agent #( + .CONFIG_T(fuse_ctrl_lc_otp_out_configuration ), + .DRIVER_T(fuse_ctrl_lc_otp_out_driver ), + .MONITOR_T(fuse_ctrl_lc_otp_out_monitor ), + .COVERAGE_T(fuse_ctrl_lc_otp_out_transaction_coverage ), + .TRANS_T(fuse_ctrl_lc_otp_out_transaction ) + ); + + `uvm_component_utils( fuse_ctrl_lc_otp_out_agent ) + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** + // FUNCTION: build_phase + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + if (configuration.active_passive == ACTIVE) begin + // Place sequencer handle into configuration object + // so that it may be retrieved from configuration + // rather than using uvm_config_db + configuration.sequencer = this.sequencer; + end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_configuration.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_configuration.svh new file mode 100644 index 0000000..b7ccdac --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_configuration.svh @@ -0,0 +1,193 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class contains all variables and functions used +// to configure the fuse_ctrl_lc_otp_out agent and its bfm's. It gets the +// bfm's from the uvm_config_db for use by the agent. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_lc_otp_out_configuration extends uvmf_parameterized_agent_configuration_base #( + .DRIVER_BFM_BIND_T(virtual fuse_ctrl_lc_otp_out_driver_bfm ), + .MONITOR_BFM_BIND_T( virtual fuse_ctrl_lc_otp_out_monitor_bfm )); + + `uvm_object_utils( fuse_ctrl_lc_otp_out_configuration ) + + + // Sequencer handle populated by agent + uvm_sequencer #(fuse_ctrl_lc_otp_out_transaction ) sequencer; + + //Constraints for the configuration variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + covergroup fuse_ctrl_lc_otp_out_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + // pragma uvmf custom covergroup end + endgroup + + //******************************************************************* + //******************************************************************* + // Structure used to pass configuration variables to monitor and driver BFM's. + // Use to_struct function to pack variables into structure. + // Use from_struct function to unpack variables from structure. + // This structure is defined in fuse_ctrl_lc_otp_out_macros.svh + `fuse_ctrl_lc_otp_out_CONFIGURATION_STRUCT + fuse_ctrl_lc_otp_out_configuration_s fuse_ctrl_lc_otp_out_configuration_struct; + //******************************************************************* + // FUNCTION: to_struct() + // This function packs variables into a fuse_ctrl_lc_otp_out_configuration_s + // structure. The function returns the handle to the fuse_ctrl_lc_otp_out_configuration_struct. + // This function is defined in fuse_ctrl_lc_otp_out_macros.svh + `fuse_ctrl_lc_otp_out_CONFIGURATION_TO_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_struct() + // This function unpacks the struct provided as an argument into + // variables of this class. + // This function is defined in fuse_ctrl_lc_otp_out_macros.svh + `fuse_ctrl_lc_otp_out_CONFIGURATION_FROM_STRUCT_FUNCTION + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + // Construct the covergroup for this configuration class + fuse_ctrl_lc_otp_out_configuration_cg = new; + endfunction + + // **************************************************************************** + // FUNCTION: post_randomize() + // This function is automatically called after the randomize() function + // is executed. + // + function void post_randomize(); + super.post_randomize(); + fuse_ctrl_lc_otp_out_configuration_cg.sample(); + endfunction + + // **************************************************************************** + // FUNCTION: initialize + // This function causes the configuration to retrieve + // its virtual interface handle from the uvm_config_db. + // This function also makes itself available to its + // agent through the uvm_config_db. + // + // ARGUMENTS: + // uvmf_active_passive_t activity: + // This argument identifies the simulation level + // as either BLOCK, CHIP, SIMULATION, etc. + // + // AGENT_PATH: + // This argument identifies the path to this + // configurations agent. This configuration + // makes itself available to the agent specified + // by agent_path by placing itself into the + // uvm_config_db. + // + // INTERFACE_NAME: + // This argument identifies the string name of + // this configurations BFM's. This string + // name is used to retrieve the driver and + // monitor BFM from the uvm_config_db. + // + virtual function void initialize(uvmf_active_passive_t activity, + string agent_path, + string interface_name); + + super.initialize( activity, agent_path, interface_name); + // The covergroup is given the same name as the interface + fuse_ctrl_lc_otp_out_configuration_cg.set_inst_name(interface_name); + + // This configuration places itself into the uvm_config_db for the agent, identified by the agent_path variable, to retrieve. + uvm_config_db #( fuse_ctrl_lc_otp_out_configuration + )::set( null ,agent_path,UVMF_AGENT_CONFIG, this ); + + // This configuration also places itself in the config db using the same identifier used by the interface. This allows users to access + // configuration variables and the interface through the bfm api class rather than directly accessing the BFM. This is useful for + // accessingthe BFM when using Veloce + uvm_config_db #( fuse_ctrl_lc_otp_out_configuration + )::set( null ,UVMF_CONFIGURATIONS, interface_name, this ); + + fuse_ctrl_lc_otp_out_configuration_cg.set_inst_name($sformatf("fuse_ctrl_lc_otp_out_configuration_cg_%s",get_full_name())); + +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. + `uvm_info("CFG", + $psprintf("The agent at '%s' is using interface named %s has the following parameters: ", agent_path, interface_name, ), + UVM_DEBUG) + + // pragma uvmf custom initialize begin + // This controls whether or not the agent returns a transaction handle in the driver when calling + // item_done() back into the sequencer or not. If set to 1, a transaction is sent back which means + // the sequence on the other end must use the get_response() part of the driver/sequence API. If + // this doesn't occur, there will eventually be response_queue overflow errors during the test. + return_transaction_response = 1'b0; + + // pragma uvmf custom initialize end + + endfunction + + // **************************************************************************** + // TASK: wait_for_reset + // *[Required]* Blocks until reset is released. The wait_for_reset operation is performed + // by a task in the monitor bfm. + virtual task wait_for_reset(); + monitor_bfm.wait_for_reset(); + endtask + + // **************************************************************************** + // TASK: wait_for_num_clocks + // *[Required]* Blocks until specified number of clocks have elapsed. The wait_for_num_clocks + // operation is performed by a task in the monitor bfm. + virtual task wait_for_num_clocks(int clocks); + monitor_bfm.wait_for_num_clocks(clocks); + endtask + + // **************************************************************************** + // FUNCTION : convert2string() + // This function is used to convert variables in this class into a string for log messaging. + // + virtual function string convert2string (); + // pragma uvmf custom convert2string begin + return $sformatf(""); + // pragma uvmf custom convert2string end + endfunction + + // **************************************************************************** + // FUNCTION: get_sequencer + function uvm_sequencer #(fuse_ctrl_lc_otp_out_transaction) get_sequencer(); + return sequencer; + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_driver.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_driver.svh new file mode 100644 index 0000000..d25471c --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_driver.svh @@ -0,0 +1,105 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class passes transactions between the sequencer +// and the BFM driver interface. It accesses the driver BFM +// through the bfm handle. This driver +// passes transactions to the driver BFM through the access +// task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_lc_otp_out_driver extends uvmf_driver_base #( + .CONFIG_T(fuse_ctrl_lc_otp_out_configuration ), + .BFM_BIND_T(virtual fuse_ctrl_lc_otp_out_driver_bfm ), + .REQ(fuse_ctrl_lc_otp_out_transaction ), + .RSP(fuse_ctrl_lc_otp_out_transaction )); + + `uvm_component_utils( fuse_ctrl_lc_otp_out_driver ) +//******************************************************************* +// Macros that define structs located in fuse_ctrl_lc_otp_out_macros.svh +//******************************************************************* +// Initiator macro used by fuse_ctrl_lc_otp_out_driver and fuse_ctrl_lc_otp_out_driver_bfm +// to communicate initiator driven data to fuse_ctrl_lc_otp_out_driver_bfm. +`fuse_ctrl_lc_otp_out_INITIATOR_STRUCT + fuse_ctrl_lc_otp_out_initiator_s fuse_ctrl_lc_otp_out_initiator_struct; +//******************************************************************* +// Responder macro used by fuse_ctrl_lc_otp_out_driver and fuse_ctrl_lc_otp_out_driver_bfm +// to communicate Responder driven data to fuse_ctrl_lc_otp_out_driver_bfm. +`fuse_ctrl_lc_otp_out_RESPONDER_STRUCT + fuse_ctrl_lc_otp_out_responder_s fuse_ctrl_lc_otp_out_responder_struct; + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent=null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the driver BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// driver BFM. This allows the driver BFM to call tasks and function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// **************************************************************************** +// This task is called by the run_phase in uvmf_driver_base. + virtual task access( inout REQ txn ); +// pragma uvmf custom access begin + if (configuration.initiator_responder==RESPONDER) begin + // Complete current transfer and wait for next transfer + bfm.respond_and_wait_for_next_transfer( + fuse_ctrl_lc_otp_out_initiator_struct, + txn.to_responder_struct() + ); + // Unpack information about initiated transfer received by this responder + txn.from_initiator_struct(fuse_ctrl_lc_otp_out_initiator_struct); + end else begin + // Initiate a transfer and get response + bfm.initiate_and_get_response( + txn.to_initiator_struct(), + fuse_ctrl_lc_otp_out_responder_struct + ); + // Unpack transfer response information received by this initiator + txn.from_responder_struct(fuse_ctrl_lc_otp_out_responder_struct); + end +// pragma uvmf custom access end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_driver_bfm.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_driver_bfm.sv new file mode 100644 index 0000000..956aa61 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_driver_bfm.sv @@ -0,0 +1,299 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This interface performs the fuse_ctrl_lc_otp_out signal driving. It is +// accessed by the uvm fuse_ctrl_lc_otp_out driver through a virtual interface +// handle in the fuse_ctrl_lc_otp_out configuration. It drives the singals passed +// in through the port connection named bus of type fuse_ctrl_lc_otp_out_if. +// +// Input signals from the fuse_ctrl_lc_otp_out_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// This bfm drives signals with a _o suffix. These signals +// are driven onto signals within fuse_ctrl_lc_otp_out_if based on INITIATOR/RESPONDER and/or +// ARBITRATION/GRANT status. +// +// The output signal connections are as follows: +// signal_o -> bus.signal +// +// +// Interface functions and tasks used by UVM components: +// +// configure: +// This function gets configuration attributes from the +// UVM driver to set any required BFM configuration +// variables such as 'initiator_responder'. +// +// initiate_and_get_response: +// This task is used to perform signaling activity for initiating +// a protocol transfer. The task initiates the transfer, using +// input data from the initiator struct. Then the task captures +// response data, placing the data into the response struct. +// The response struct is returned to the driver class. +// +// respond_and_wait_for_next_transfer: +// This task is used to complete a current transfer as a responder +// and then wait for the initiator to start the next transfer. +// The task uses data in the responder struct to drive protocol +// signals to complete the transfer. The task then waits for +// the next transfer. Once the next transfer begins, data from +// the initiator is placed into the initiator struct and sent +// to the responder sequence for processing to determine +// what data to respond with. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_lc_otp_out_pkg_hdl::*; +`include "src/fuse_ctrl_lc_otp_out_macros.svh" + +interface fuse_ctrl_lc_otp_out_driver_bfm + (fuse_ctrl_lc_otp_out_if bus); + // The following pragma and additional ones in-lined further below are for running this BFM on Veloce + // pragma attribute fuse_ctrl_lc_otp_out_driver_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: ", ), + UVM_DEBUG) +end +`endif + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + tri clk_i_i; + tri rst_ni_i; + + // Signal list (all signals are capable of being inputs and outputs for the sake + // of supporting both INITIATOR and RESPONDER mode operation. Expectation is that + // directionality in the config file was from the point-of-view of the INITIATOR + + // INITIATOR mode input signals + tri [$bits(caliptra_otp_ctrl_pkg::lc_otp_vendor_test_rsp_t)-1:0] lc_otp_vendor_test_o_i; + reg [$bits(caliptra_otp_ctrl_pkg::lc_otp_vendor_test_rsp_t)-1:0] lc_otp_vendor_test_o_o = 'bz; + tri [$bits(caliptra_otp_ctrl_pkg::lc_otp_program_rsp_t)-1:0] lc_otp_program_o_i; + reg [$bits(caliptra_otp_ctrl_pkg::lc_otp_program_rsp_t)-1:0] lc_otp_program_o_o = 'bz; + tri [$bits(caliptra_otp_ctrl_pkg::otp_lc_data_t)-1:0] otp_lc_data_o_i; + reg [$bits(caliptra_otp_ctrl_pkg::otp_lc_data_t)-1:0] otp_lc_data_o_o = 'bz; + + // INITIATOR mode output signals + + // Bi-directional signals + + + assign clk_i_i = bus.clk_i; + assign rst_ni_i = bus.rst_ni; + + // These are signals marked as 'input' by the config file, but the signals will be + // driven by this BFM if put into RESPONDER mode (flipping all signal directions around) + assign lc_otp_vendor_test_o_i = bus.lc_otp_vendor_test_o; + assign bus.lc_otp_vendor_test_o = (initiator_responder == RESPONDER) ? lc_otp_vendor_test_o_o : 'bz; + assign lc_otp_program_o_i = bus.lc_otp_program_o; + assign bus.lc_otp_program_o = (initiator_responder == RESPONDER) ? lc_otp_program_o_o : 'bz; + assign otp_lc_data_o_i = bus.otp_lc_data_o; + assign bus.otp_lc_data_o = (initiator_responder == RESPONDER) ? otp_lc_data_o_o : 'bz; + + + // These are signals marked as 'output' by the config file, but the outputs will + // not be driven by this BFM unless placed in INITIATOR mode. + + // Proxy handle to UVM driver + fuse_ctrl_lc_otp_out_pkg::fuse_ctrl_lc_otp_out_driver proxy; + // pragma tbx oneway proxy.my_function_name_in_uvm_driver + + // **************************************************************************** + // **************************************************************************** + // Macros that define structs located in fuse_ctrl_lc_otp_out_macros.svh + // **************************************************************************** + // Struct for passing configuration data from fuse_ctrl_lc_otp_out_driver to this BFM + // **************************************************************************** + `fuse_ctrl_lc_otp_out_CONFIGURATION_STRUCT + // **************************************************************************** + // Structs for INITIATOR and RESPONDER data flow + //******************************************************************* + // Initiator macro used by fuse_ctrl_lc_otp_out_driver and fuse_ctrl_lc_otp_out_driver_bfm + // to communicate initiator driven data to fuse_ctrl_lc_otp_out_driver_bfm. + `fuse_ctrl_lc_otp_out_INITIATOR_STRUCT + fuse_ctrl_lc_otp_out_initiator_s initiator_struct; + // Responder macro used by fuse_ctrl_lc_otp_out_driver and fuse_ctrl_lc_otp_out_driver_bfm + // to communicate Responder driven data to fuse_ctrl_lc_otp_out_driver_bfm. + `fuse_ctrl_lc_otp_out_RESPONDER_STRUCT + fuse_ctrl_lc_otp_out_responder_s responder_struct; + + // **************************************************************************** +// pragma uvmf custom reset_condition_and_response begin + // Always block used to return signals to reset value upon assertion of reset + always @( negedge rst_ni_i ) + begin + // RESPONDER mode output signals + lc_otp_vendor_test_o_o <= 'bz; + lc_otp_program_o_o <= 'bz; + otp_lc_data_o_o <= 'bz; + // INITIATOR mode output signals + // Bi-directional signals + + end +// pragma uvmf custom reset_condition_and_response end + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the driver BFM. It is called by the driver within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the driver BFM needs to be aware of the new configuration + // variables. + // + + function void configure(fuse_ctrl_lc_otp_out_configuration_s fuse_ctrl_lc_otp_out_configuration_arg); // pragma tbx xtf + initiator_responder = fuse_ctrl_lc_otp_out_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + +// pragma uvmf custom initiate_and_get_response begin +// **************************************************************************** +// UVMF_CHANGE_ME +// This task is used by an initator. The task first initiates a transfer then +// waits for the responder to complete the transfer. + task initiate_and_get_response( + // This argument passes transaction variables used by an initiator + // to perform the initial part of a protocol transfer. The values + // come from a sequence item created in a sequence. + input fuse_ctrl_lc_otp_out_initiator_s fuse_ctrl_lc_otp_out_initiator_struct, + // This argument is used to send data received from the responder + // back to the sequence item. The sequence item is returned to the sequence. + output fuse_ctrl_lc_otp_out_responder_s fuse_ctrl_lc_otp_out_responder_struct + );// pragma tbx xtf + // + // Members within the fuse_ctrl_lc_otp_out_initiator_struct: + // otp_lc_data_t otp_lc_data_o ; + // Members within the fuse_ctrl_lc_otp_out_responder_struct: + // otp_lc_data_t otp_lc_data_o ; + initiator_struct = fuse_ctrl_lc_otp_out_initiator_struct; + // + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clk_i_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available initiator input and inout signals listed. + // Initiator input signals + // fuse_ctrl_lc_otp_out_responder_struct.xyz = lc_otp_vendor_test_o_i; // [$bits(lc_otp_vendor_test_rsp_t)-1:0] + // fuse_ctrl_lc_otp_out_responder_struct.xyz = lc_otp_program_o_i; // [$bits(lc_otp_program_rsp_t)-1:0] + // fuse_ctrl_lc_otp_out_responder_struct.xyz = otp_lc_data_o_i; // [$bits(otp_lc_data_t)-1:0] + // Initiator inout signals + // How to assign a signal from an initiator struct member named xyz. + // All available initiator output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Initiator output signals + // Initiator inout signals + // Initiate a transfer using the data received. + @(posedge clk_i_i); + @(posedge clk_i_i); + // Wait for the responder to complete the transfer then place the responder data into + // fuse_ctrl_lc_otp_out_responder_struct. + @(posedge clk_i_i); + @(posedge clk_i_i); + responder_struct = fuse_ctrl_lc_otp_out_responder_struct; + endtask +// pragma uvmf custom initiate_and_get_response end + +// pragma uvmf custom respond_and_wait_for_next_transfer begin +// **************************************************************************** +// The first_transfer variable is used to prevent completing a transfer in the +// first call to this task. For the first call to this task, there is not +// current transfer to complete. +bit first_transfer=1; + +// UVMF_CHANGE_ME +// This task is used by a responder. The task first completes the current +// transfer in progress then waits for the initiator to start the next transfer. + task respond_and_wait_for_next_transfer( + // This argument is used to send data received from the initiator + // back to the sequence item. The sequence determines how to respond. + output fuse_ctrl_lc_otp_out_initiator_s fuse_ctrl_lc_otp_out_initiator_struct, + // This argument passes transaction variables used by a responder + // to complete a protocol transfer. The values come from a sequence item. + input fuse_ctrl_lc_otp_out_responder_s fuse_ctrl_lc_otp_out_responder_struct + );// pragma tbx xtf + // Variables within the fuse_ctrl_lc_otp_out_initiator_struct: + // otp_lc_data_t otp_lc_data_o ; + // Variables within the fuse_ctrl_lc_otp_out_responder_struct: + // otp_lc_data_t otp_lc_data_o ; + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clk_i_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available responder input and inout signals listed. + // Responder input signals + // Responder inout signals + // How to assign a signal, named xyz, from an initiator struct member. + // All available responder output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Responder output signals + // lc_otp_vendor_test_o_o <= fuse_ctrl_lc_otp_out_initiator_struct.xyz; // [$bits(lc_otp_vendor_test_rsp_t)-1:0] + // lc_otp_program_o_o <= fuse_ctrl_lc_otp_out_initiator_struct.xyz; // [$bits(lc_otp_program_rsp_t)-1:0] + // otp_lc_data_o_o <= fuse_ctrl_lc_otp_out_initiator_struct.xyz; // [$bits(otp_lc_data_t)-1:0] + // Responder inout signals + + @(posedge clk_i_i); + if (!first_transfer) begin + // Perform transfer response here. + // Reply using data recieved in the fuse_ctrl_lc_otp_out_responder_struct. + @(posedge clk_i_i); + // Reply using data recieved in the transaction handle. + @(posedge clk_i_i); + end + // Wait for next transfer then gather info from intiator about the transfer. + // Place the data into the fuse_ctrl_lc_otp_out_initiator_struct. + @(posedge clk_i_i); + @(posedge clk_i_i); + first_transfer = 0; + endtask +// pragma uvmf custom respond_and_wait_for_next_transfer end + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_if.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_if.sv new file mode 100644 index 0000000..f4fcd32 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_if.sv @@ -0,0 +1,88 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface contains the fuse_ctrl_lc_otp_out interface signals. +// It is instantiated once per fuse_ctrl_lc_otp_out bus. Bus Functional Models, +// BFM's named fuse_ctrl_lc_otp_out_driver_bfm, are used to drive signals on the bus. +// BFM's named fuse_ctrl_lc_otp_out_monitor_bfm are used to monitor signals on the +// bus. This interface signal bundle is passed in the port list of +// the BFM in order to give the BFM access to the signals in this +// interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// This template can be used to connect a DUT to these signals +// +// .dut_signal_port(fuse_ctrl_lc_otp_out_bus.lc_otp_vendor_test_o), // Agent input +// .dut_signal_port(fuse_ctrl_lc_otp_out_bus.lc_otp_program_o), // Agent input +// .dut_signal_port(fuse_ctrl_lc_otp_out_bus.otp_lc_data_o), // Agent input + +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_lc_otp_out_pkg_hdl::*; + +interface fuse_ctrl_lc_otp_out_if + + ( + input tri clk_i, + input tri rst_ni, + inout tri [$bits(caliptra_otp_ctrl_pkg::lc_otp_vendor_test_rsp_t)-1:0] lc_otp_vendor_test_o, + inout tri [$bits(caliptra_otp_ctrl_pkg::lc_otp_program_rsp_t)-1:0] lc_otp_program_o, + inout tri [$bits(caliptra_otp_ctrl_pkg::otp_lc_data_t)-1:0] otp_lc_data_o + ); + +modport monitor_port + ( + input clk_i, + input rst_ni, + input lc_otp_vendor_test_o, + input lc_otp_program_o, + input otp_lc_data_o + ); + +modport initiator_port + ( + input clk_i, + input rst_ni, + input lc_otp_vendor_test_o, + input lc_otp_program_o, + input otp_lc_data_o + ); + +modport responder_port + ( + input clk_i, + input rst_ni, + output lc_otp_vendor_test_o, + output lc_otp_program_o, + output otp_lc_data_o + ); + + +// pragma uvmf custom interface_item_additional begin +// pragma uvmf custom interface_item_additional end + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_infact_coverage_strategy.csv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_infact_coverage_strategy.csv new file mode 100644 index 0000000..1c218e1 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_infact_coverage_strategy.csv @@ -0,0 +1,6 @@ +Global +auto_bin_max, 64 + +Name,Type,Include +rand_fields,coverpoint,=rand *.** + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_macros.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_macros.svh new file mode 100644 index 0000000..f9c1d7b --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_macros.svh @@ -0,0 +1,135 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains macros used with the fuse_ctrl_lc_otp_out package. +// These macros include packed struct definitions. These structs are +// used to pass data between classes, hvl, and BFM's, hdl. Use of +// structs are more efficient and simpler to modify. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_struct +// and from_struct methods defined in the macros below that are used in +// the fuse_ctrl_lc_otp_out_configuration class. +// + `define fuse_ctrl_lc_otp_out_CONFIGURATION_STRUCT \ +typedef struct packed { \ + uvmf_active_passive_t active_passive; \ + uvmf_initiator_responder_t initiator_responder; \ + } fuse_ctrl_lc_otp_out_configuration_s; + + `define fuse_ctrl_lc_otp_out_CONFIGURATION_TO_STRUCT_FUNCTION \ + virtual function fuse_ctrl_lc_otp_out_configuration_s to_struct();\ + fuse_ctrl_lc_otp_out_configuration_struct = \ + {\ + this.active_passive,\ + this.initiator_responder\ + };\ + return ( fuse_ctrl_lc_otp_out_configuration_struct );\ + endfunction + + `define fuse_ctrl_lc_otp_out_CONFIGURATION_FROM_STRUCT_FUNCTION \ + virtual function void from_struct(fuse_ctrl_lc_otp_out_configuration_s fuse_ctrl_lc_otp_out_configuration_struct);\ + {\ + this.active_passive,\ + this.initiator_responder \ + } = fuse_ctrl_lc_otp_out_configuration_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_monitor_struct +// and from_monitor_struct methods of the fuse_ctrl_lc_otp_out_transaction class. +// + `define fuse_ctrl_lc_otp_out_MONITOR_STRUCT typedef struct packed { \ + caliptra_otp_ctrl_pkg::otp_lc_data_t otp_lc_data_o ; \ + } fuse_ctrl_lc_otp_out_monitor_s; + + `define fuse_ctrl_lc_otp_out_TO_MONITOR_STRUCT_FUNCTION \ + virtual function fuse_ctrl_lc_otp_out_monitor_s to_monitor_struct();\ + fuse_ctrl_lc_otp_out_monitor_struct = \ + { \ + this.otp_lc_data_o \ + };\ + return ( fuse_ctrl_lc_otp_out_monitor_struct);\ + endfunction\ + + `define fuse_ctrl_lc_otp_out_FROM_MONITOR_STRUCT_FUNCTION \ + virtual function void from_monitor_struct(fuse_ctrl_lc_otp_out_monitor_s fuse_ctrl_lc_otp_out_monitor_struct);\ + {\ + this.otp_lc_data_o \ + } = fuse_ctrl_lc_otp_out_monitor_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_initiator_struct +// and from_initiator_struct methods of the fuse_ctrl_lc_otp_out_transaction class. +// Also update the comments in the driver BFM. +// + `define fuse_ctrl_lc_otp_out_INITIATOR_STRUCT typedef struct packed { \ + caliptra_otp_ctrl_pkg::otp_lc_data_t otp_lc_data_o ; \ + } fuse_ctrl_lc_otp_out_initiator_s; + + `define fuse_ctrl_lc_otp_out_TO_INITIATOR_STRUCT_FUNCTION \ + virtual function fuse_ctrl_lc_otp_out_initiator_s to_initiator_struct();\ + fuse_ctrl_lc_otp_out_initiator_struct = \ + {\ + this.otp_lc_data_o \ + };\ + return ( fuse_ctrl_lc_otp_out_initiator_struct);\ + endfunction + + `define fuse_ctrl_lc_otp_out_FROM_INITIATOR_STRUCT_FUNCTION \ + virtual function void from_initiator_struct(fuse_ctrl_lc_otp_out_initiator_s fuse_ctrl_lc_otp_out_initiator_struct);\ + {\ + this.otp_lc_data_o \ + } = fuse_ctrl_lc_otp_out_initiator_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_responder_struct +// and from_responder_struct methods of the fuse_ctrl_lc_otp_out_transaction class. +// Also update the comments in the driver BFM. +// + `define fuse_ctrl_lc_otp_out_RESPONDER_STRUCT typedef struct packed { \ + caliptra_otp_ctrl_pkg::otp_lc_data_t otp_lc_data_o ; \ + } fuse_ctrl_lc_otp_out_responder_s; + + `define fuse_ctrl_lc_otp_out_TO_RESPONDER_STRUCT_FUNCTION \ + virtual function fuse_ctrl_lc_otp_out_responder_s to_responder_struct();\ + fuse_ctrl_lc_otp_out_responder_struct = \ + {\ + this.otp_lc_data_o \ + };\ + return ( fuse_ctrl_lc_otp_out_responder_struct);\ + endfunction + + `define fuse_ctrl_lc_otp_out_FROM_RESPONDER_STRUCT_FUNCTION \ + virtual function void from_responder_struct(fuse_ctrl_lc_otp_out_responder_s fuse_ctrl_lc_otp_out_responder_struct);\ + {\ + this.otp_lc_data_o \ + } = fuse_ctrl_lc_otp_out_responder_struct;\ + endfunction +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_monitor.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_monitor.svh new file mode 100644 index 0000000..0c9f446 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_monitor.svh @@ -0,0 +1,101 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class receives fuse_ctrl_lc_otp_out transactions observed by the +// fuse_ctrl_lc_otp_out monitor BFM and broadcasts them through the analysis port +// on the agent. It accesses the monitor BFM through the monitor +// task. This UVM component captures transactions +// for viewing in the waveform viewer if the +// enable_transaction_viewing flag is set in the configuration. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_lc_otp_out_monitor extends uvmf_monitor_base #( + .CONFIG_T(fuse_ctrl_lc_otp_out_configuration ), + .BFM_BIND_T(virtual fuse_ctrl_lc_otp_out_monitor_bfm ), + .TRANS_T(fuse_ctrl_lc_otp_out_transaction )); + + `uvm_component_utils( fuse_ctrl_lc_otp_out_monitor ) + +// Structure used to pass data from monitor BFM to monitor class in agent. +// Use to_monitor_struct function to pack transaction variables into structure. +// Use from_monitor_struct function to unpack transaction variables from structure. +`fuse_ctrl_lc_otp_out_MONITOR_STRUCT + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the monitor BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// monitor BFM. This allows the monitor BFM to call the notify_transaction +// function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// *************************************************************************** + virtual task run_phase(uvm_phase phase); + // Start monitor BFM thread and don't call super.run() in order to + // override the default monitor proxy 'pull' behavior with the more + // emulation-friendly BFM 'push' approach using the notify_transaction + // function below + bfm.start_monitoring(); + endtask + +// ************************************************************************** + +// This function is called by the monitor BFM. It receives data observed by the +// monitor BFM. Data is passed using the fuse_ctrl_lc_otp_out_monitor_struct. + virtual function void notify_transaction(input fuse_ctrl_lc_otp_out_monitor_s fuse_ctrl_lc_otp_out_monitor_struct); + + + trans = new("trans"); + trans.from_monitor_struct(fuse_ctrl_lc_otp_out_monitor_struct); + trans.start_time = time_stamp; + trans.end_time = $time; + time_stamp = trans.end_time; + + analyze(trans); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_monitor_bfm.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_monitor_bfm.sv new file mode 100644 index 0000000..ca97fe2 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_monitor_bfm.sv @@ -0,0 +1,194 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface performs the fuse_ctrl_lc_otp_out signal monitoring. +// It is accessed by the uvm fuse_ctrl_lc_otp_out monitor through a virtual +// interface handle in the fuse_ctrl_lc_otp_out configuration. It monitors the +// signals passed in through the port connection named bus of +// type fuse_ctrl_lc_otp_out_if. +// +// Input signals from the fuse_ctrl_lc_otp_out_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// Interface functions and tasks used by UVM components: +// monitor(inout TRANS_T txn); +// This task receives the transaction, txn, from the +// UVM monitor and then populates variables in txn +// from values observed on bus activity. This task +// blocks until an operation on the fuse_ctrl_lc_otp_out bus is complete. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_lc_otp_out_pkg_hdl::*; +`include "src/fuse_ctrl_lc_otp_out_macros.svh" + + +interface fuse_ctrl_lc_otp_out_monitor_bfm + ( fuse_ctrl_lc_otp_out_if bus ); + // The pragma below and additional ones in-lined further down are for running this BFM on Veloce + // pragma attribute fuse_ctrl_lc_otp_out_monitor_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: ", ), + UVM_DEBUG) +end +`endif + + + // Structure used to pass transaction data from monitor BFM to monitor class in agent. +`fuse_ctrl_lc_otp_out_MONITOR_STRUCT + fuse_ctrl_lc_otp_out_monitor_s fuse_ctrl_lc_otp_out_monitor_struct; + + // Structure used to pass configuration data from monitor class to monitor BFM. + `fuse_ctrl_lc_otp_out_CONFIGURATION_STRUCT + + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + tri clk_i_i; + tri rst_ni_i; + tri [$bits(caliptra_otp_ctrl_pkg::lc_otp_vendor_test_rsp_t)-1:0] lc_otp_vendor_test_o_i; + tri [$bits(caliptra_otp_ctrl_pkg::lc_otp_program_rsp_t)-1:0] lc_otp_program_o_i; + tri [$bits(caliptra_otp_ctrl_pkg::otp_lc_data_t)-1:0] otp_lc_data_o_i; + assign clk_i_i = bus.clk_i; + assign rst_ni_i = bus.rst_ni; + assign lc_otp_vendor_test_o_i = bus.lc_otp_vendor_test_o; + assign lc_otp_program_o_i = bus.lc_otp_program_o; + assign otp_lc_data_o_i = bus.otp_lc_data_o; + + // Proxy handle to UVM monitor + fuse_ctrl_lc_otp_out_pkg::fuse_ctrl_lc_otp_out_monitor proxy; + // pragma tbx oneway proxy.notify_transaction + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + task wait_for_reset();// pragma tbx xtf + @(posedge clk_i_i) ; + do_wait_for_reset(); + endtask + + // **************************************************************************** + task do_wait_for_reset(); + // pragma uvmf custom reset_condition begin + wait ( rst_ni_i === 1 ) ; + @(posedge clk_i_i) ; + // pragma uvmf custom reset_condition end + endtask + + //****************************************************************** + + task wait_for_num_clocks(input int unsigned count); // pragma tbx xtf + @(posedge clk_i_i); + + repeat (count-1) @(posedge clk_i_i); + endtask + + //****************************************************************** + event go; + function void start_monitoring();// pragma tbx xtf + -> go; + endfunction + + // **************************************************************************** + initial begin + @go; + forever begin + @(posedge clk_i_i); + do_monitor( fuse_ctrl_lc_otp_out_monitor_struct ); + + + proxy.notify_transaction( fuse_ctrl_lc_otp_out_monitor_struct ); + + end + end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the monitor BFM. It is called by the monitor within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the monitor BFM needs to be aware of the new configuration + // variables. + // + function void configure(fuse_ctrl_lc_otp_out_configuration_s fuse_ctrl_lc_otp_out_configuration_arg); // pragma tbx xtf + initiator_responder = fuse_ctrl_lc_otp_out_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + + + // **************************************************************************** + + task do_monitor(output fuse_ctrl_lc_otp_out_monitor_s fuse_ctrl_lc_otp_out_monitor_struct); + // + // Available struct members: + // // fuse_ctrl_lc_otp_out_monitor_struct.otp_lc_data_o + // // + // Reference code; + // How to wait for signal value + // while (control_signal === 1'b1) @(posedge clk_i_i); + // + // How to assign a struct member, named xyz, from a signal. + // All available input signals listed. + // fuse_ctrl_lc_otp_out_monitor_struct.xyz = lc_otp_vendor_test_o_i; // [$bits(caliptra_otp_ctrl_pkg::lc_otp_vendor_test_rsp_t)-1:0] + // fuse_ctrl_lc_otp_out_monitor_struct.xyz = lc_otp_program_o_i; // [$bits(caliptra_otp_ctrl_pkg::lc_otp_program_rsp_t)-1:0] + // fuse_ctrl_lc_otp_out_monitor_struct.xyz = otp_lc_data_o_i; // [$bits(caliptra_otp_ctrl_pkg::otp_lc_data_t)-1:0] + // pragma uvmf custom do_monitor begin + // UVMF_CHANGE_ME : Implement protocol monitoring. The commented reference code + // below are examples of how to capture signal values and assign them to + // structure members. All available input signals are listed. The 'while' + // code example shows how to wait for a synchronous flow control signal. This + // task should return when a complete transfer has been observed. Once this task is + // exited with captured values, it is then called again to wait for and observe + // the next transfer. One clock cycle is consumed between calls to do_monitor. + @(posedge clk_i_i); + @(posedge clk_i_i); + @(posedge clk_i_i); + @(posedge clk_i_i); + // pragma uvmf custom do_monitor end + endtask + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_random_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_random_sequence.svh new file mode 100644 index 0000000..a680653 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_random_sequence.svh @@ -0,0 +1,67 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This sequences randomizes the fuse_ctrl_lc_otp_out transaction and sends it +// to the UVM driver. +// +// This sequence constructs and randomizes a fuse_ctrl_lc_otp_out_transaction. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_lc_otp_out_random_sequence + extends fuse_ctrl_lc_otp_out_sequence_base ; + + `uvm_object_utils( fuse_ctrl_lc_otp_out_random_sequence ) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //***************************************************************** + function new(string name = ""); + super.new(name); + endfunction: new + + // **************************************************************************** + // TASK : body() + // This task is automatically executed when this sequence is started using the + // start(sequencerHandle) task. + // + task body(); + + // Construct the transaction + req=fuse_ctrl_lc_otp_out_transaction::type_id::create("req"); + start_item(req); + // Randomize the transaction + if(!req.randomize()) `uvm_fatal("SEQ", "fuse_ctrl_lc_otp_out_random_sequence::body()-fuse_ctrl_lc_otp_out_transaction randomization failed") + // Send the transaction to the fuse_ctrl_lc_otp_out_driver_bfm via the sequencer and fuse_ctrl_lc_otp_out_driver. + finish_item(req); + `uvm_info("SEQ", {"Response:",req.convert2string()},UVM_MEDIUM) + + endtask + +endclass: fuse_ctrl_lc_otp_out_random_sequence + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_responder_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_responder_sequence.svh new file mode 100644 index 0000000..0e7cf5c --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_responder_sequence.svh @@ -0,0 +1,63 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class can be used to provide stimulus when an interface +// has been configured to run in a responder mode. It +// will never finish by default, always going back to the driver +// and driver BFM for the next transaction with which to respond. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_lc_otp_out_responder_sequence + extends fuse_ctrl_lc_otp_out_sequence_base ; + + `uvm_object_utils( fuse_ctrl_lc_otp_out_responder_sequence ) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "fuse_ctrl_lc_otp_out_responder_sequence"); + super.new(name); + endfunction + + task body(); + req=fuse_ctrl_lc_otp_out_transaction::type_id::create("req"); + forever begin + start_item(req); + finish_item(req); + // pragma uvmf custom body begin + // UVMF_CHANGE_ME : Do something here with the resulting req item. The + // finish_item() call above will block until the req transaction is ready + // to be handled by the responder sequence. + // If this was an item that required a response, the expectation is + // that the response should be populated within this transaction now. + `uvm_info("SEQ",$sformatf("Processed txn: %s",req.convert2string()),UVM_HIGH) + // pragma uvmf custom body end + end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_sequence_base.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_sequence_base.svh new file mode 100644 index 0000000..d084a6b --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_sequence_base.svh @@ -0,0 +1,110 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the class used as the base class for all sequences +// for this interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_lc_otp_out_sequence_base extends uvmf_sequence_base #( + .REQ(fuse_ctrl_lc_otp_out_transaction ), + .RSP(fuse_ctrl_lc_otp_out_transaction )); + + `uvm_object_utils( fuse_ctrl_lc_otp_out_sequence_base ) + + // variables + typedef fuse_ctrl_lc_otp_out_transaction fuse_ctrl_lc_otp_out_transaction_req_t; + fuse_ctrl_lc_otp_out_transaction_req_t req; + typedef fuse_ctrl_lc_otp_out_transaction fuse_ctrl_lc_otp_out_transaction_rsp_t; + fuse_ctrl_lc_otp_out_transaction_rsp_t rsp; + + // Event for identifying when a response was received from the sequencer + event new_rsp; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // TASK : get_responses() + // This task recursively gets sequence item responses from the sequencer. + // + virtual task get_responses(); + fork + begin + // Block until new rsp available + get_response(rsp); + // New rsp received. Indicate to sequence using event. + ->new_rsp; + // Display the received response transaction + `uvm_info("SEQ", {"New response transaction:",rsp.convert2string()}, UVM_MEDIUM) + end + join_none + endtask + + // **************************************************************************** + // TASK : pre_body() + // This task is called automatically when start is called with call_pre_post set to 1 (default). + // By calling get_responses() within pre_body() any derived sequences are automatically + // processing response transactions. Only un-comment this call to get_responses() if you + // have configured the interface driver to utilize the response transaction path by setting + // the configuration variable "return_transaction_response" to 1. Otherwise it is possible + // to impact runtime performance and memory utilization. + // + virtual task pre_body(); + // pragma uvmf custom pre_body begin +// get_responses(); + // pragma uvmf custom pre_body end + endtask + + // **************************************************************************** + // TASK : body() + // This task is called automatically when start is called. This sequence sends + // a req sequence item to the sequencer identified as an argument in the call + // to start. + // + virtual task body(); + // pragma uvmf custom body begin + start_item(req); + finish_item(req); + // pragma uvmf custom body end + endtask + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name =""); + super.new( name ); + // pragma uvmf custom new begin + req = fuse_ctrl_lc_otp_out_transaction_req_t::type_id::create("req"); + rsp = fuse_ctrl_lc_otp_out_transaction_rsp_t::type_id::create("rsp"); + // pragma uvmf custom new end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_transaction.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_transaction.svh new file mode 100644 index 0000000..f62fa69 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_transaction.svh @@ -0,0 +1,196 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class defines the variables required for an fuse_ctrl_lc_otp_out +// transaction. Class variables to be displayed in waveform transaction +// viewing are added to the transaction viewing stream in the add_to_wave +// function. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_lc_otp_out_transaction extends uvmf_transaction_base; + + `uvm_object_utils( fuse_ctrl_lc_otp_out_transaction ) + + caliptra_otp_ctrl_pkg::otp_lc_data_t otp_lc_data_o ; + + //Constraints for the transaction variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //******************************************************************* + //******************************************************************* + // Macros that define structs and associated functions are + // located in fuse_ctrl_lc_otp_out_macros.svh + + //******************************************************************* + // Monitor macro used by fuse_ctrl_lc_otp_out_monitor and fuse_ctrl_lc_otp_out_monitor_bfm + // This struct is defined in fuse_ctrl_lc_otp_out_macros.svh + `fuse_ctrl_lc_otp_out_MONITOR_STRUCT + fuse_ctrl_lc_otp_out_monitor_s fuse_ctrl_lc_otp_out_monitor_struct; + //******************************************************************* + // FUNCTION: to_monitor_struct() + // This function packs transaction variables into a fuse_ctrl_lc_otp_out_monitor_s + // structure. The function returns the handle to the fuse_ctrl_lc_otp_out_monitor_struct. + // This function is defined in fuse_ctrl_lc_otp_out_macros.svh + `fuse_ctrl_lc_otp_out_TO_MONITOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_monitor_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_lc_otp_out_macros.svh + `fuse_ctrl_lc_otp_out_FROM_MONITOR_STRUCT_FUNCTION + + //******************************************************************* + // Initiator macro used by fuse_ctrl_lc_otp_out_driver and fuse_ctrl_lc_otp_out_driver_bfm + // to communicate initiator driven data to fuse_ctrl_lc_otp_out_driver_bfm. + // This struct is defined in fuse_ctrl_lc_otp_out_macros.svh + `fuse_ctrl_lc_otp_out_INITIATOR_STRUCT + fuse_ctrl_lc_otp_out_initiator_s fuse_ctrl_lc_otp_out_initiator_struct; + //******************************************************************* + // FUNCTION: to_initiator_struct() + // This function packs transaction variables into a fuse_ctrl_lc_otp_out_initiator_s + // structure. The function returns the handle to the fuse_ctrl_lc_otp_out_initiator_struct. + // This function is defined in fuse_ctrl_lc_otp_out_macros.svh + `fuse_ctrl_lc_otp_out_TO_INITIATOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_initiator_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_lc_otp_out_macros.svh + `fuse_ctrl_lc_otp_out_FROM_INITIATOR_STRUCT_FUNCTION + + //******************************************************************* + // Responder macro used by fuse_ctrl_lc_otp_out_driver and fuse_ctrl_lc_otp_out_driver_bfm + // to communicate Responder driven data to fuse_ctrl_lc_otp_out_driver_bfm. + // This struct is defined in fuse_ctrl_lc_otp_out_macros.svh + `fuse_ctrl_lc_otp_out_RESPONDER_STRUCT + fuse_ctrl_lc_otp_out_responder_s fuse_ctrl_lc_otp_out_responder_struct; + //******************************************************************* + // FUNCTION: to_responder_struct() + // This function packs transaction variables into a fuse_ctrl_lc_otp_out_responder_s + // structure. The function returns the handle to the fuse_ctrl_lc_otp_out_responder_struct. + // This function is defined in fuse_ctrl_lc_otp_out_macros.svh + `fuse_ctrl_lc_otp_out_TO_RESPONDER_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_responder_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_lc_otp_out_macros.svh + `fuse_ctrl_lc_otp_out_FROM_RESPONDER_STRUCT_FUNCTION + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + endfunction + + // **************************************************************************** + // FUNCTION: convert2string() + // This function converts all variables in this class to a single string for + // logfile reporting. + // + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + // UVMF_CHANGE_ME : Customize format if desired. + return $sformatf("otp_lc_data_o:0x%x ",otp_lc_data_o); + // pragma uvmf custom convert2string end + endfunction + + //******************************************************************* + // FUNCTION: do_print() + // This function is automatically called when the .print() function + // is called on this class. + // + virtual function void do_print(uvm_printer printer); + // pragma uvmf custom do_print begin + // UVMF_CHANGE_ME : Current contents of do_print allows for the use of UVM 1.1d, 1.2 or P1800.2. + // Update based on your own printing preference according to your preferred UVM version + $display(convert2string()); + // pragma uvmf custom do_print end + endfunction + + //******************************************************************* + // FUNCTION: do_compare() + // This function is automatically called when the .compare() function + // is called on this class. + // + virtual function bit do_compare (uvm_object rhs, uvm_comparer comparer); + fuse_ctrl_lc_otp_out_transaction RHS; + if (!$cast(RHS,rhs)) return 0; + // pragma uvmf custom do_compare begin + // UVMF_CHANGE_ME : Eliminate comparison of variables not to be used for compare + return (super.do_compare(rhs,comparer) + &&(this.otp_lc_data_o == RHS.otp_lc_data_o) + ); + // pragma uvmf custom do_compare end + endfunction + + //******************************************************************* + // FUNCTION: do_copy() + // This function is automatically called when the .copy() function + // is called on this class. + // + virtual function void do_copy (uvm_object rhs); + fuse_ctrl_lc_otp_out_transaction RHS; + assert($cast(RHS,rhs)); + // pragma uvmf custom do_copy begin + super.do_copy(rhs); + this.otp_lc_data_o = RHS.otp_lc_data_o; + // pragma uvmf custom do_copy end + endfunction + + // **************************************************************************** + // FUNCTION: add_to_wave() + // This function is used to display variables in this class in the waveform + // viewer. The start_time and end_time variables must be set before this + // function is called. If the start_time and end_time variables are not set + // the transaction will be hidden at 0ns on the waveform display. + // + virtual function void add_to_wave(int transaction_viewing_stream_h); + `ifdef QUESTA + if (transaction_view_h == 0) begin + transaction_view_h = $begin_transaction(transaction_viewing_stream_h,"fuse_ctrl_lc_otp_out_transaction",start_time); + end + super.add_to_wave(transaction_view_h); + // pragma uvmf custom add_to_wave begin + // UVMF_CHANGE_ME : Color can be applied to transaction entries based on content, example below + // case() + // 1 : $add_color(transaction_view_h,"red"); + // default : $add_color(transaction_view_h,"grey"); + // endcase + // UVMF_CHANGE_ME : Eliminate transaction variables not wanted in transaction viewing in the waveform viewer + $add_attribute(transaction_view_h,otp_lc_data_o,"otp_lc_data_o"); + // pragma uvmf custom add_to_wave end + $end_transaction(transaction_view_h,end_time); + $free_transaction(transaction_view_h); + `endif // QUESTA + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_transaction_coverage.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_transaction_coverage.svh new file mode 100644 index 0000000..25eeac7 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_transaction_coverage.svh @@ -0,0 +1,84 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class records fuse_ctrl_lc_otp_out transaction information using +// a covergroup named fuse_ctrl_lc_otp_out_transaction_cg. An instance of this +// coverage component is instantiated in the uvmf_parameterized_agent +// if the has_coverage flag is set. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_lc_otp_out_transaction_coverage extends uvm_subscriber #(.T(fuse_ctrl_lc_otp_out_transaction )); + + `uvm_component_utils( fuse_ctrl_lc_otp_out_transaction_coverage ) + + T coverage_trans; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + covergroup fuse_ctrl_lc_otp_out_transaction_cg; + // pragma uvmf custom covergroup begin + // UVMF_CHANGE_ME : Add coverage bins, crosses, exclusions, etc. according to coverage needs. + option.auto_bin_max=1024; + option.per_instance=1; + otp_lc_data_o: coverpoint coverage_trans.otp_lc_data_o; + // pragma uvmf custom covergroup end + endgroup + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new(string name="", uvm_component parent=null); + super.new(name,parent); + fuse_ctrl_lc_otp_out_transaction_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that transaction variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + endfunction + + // **************************************************************************** + // FUNCTION : build_phase() + // This function is the standard UVM build_phase. + // + function void build_phase(uvm_phase phase); + fuse_ctrl_lc_otp_out_transaction_cg.set_inst_name($sformatf("fuse_ctrl_lc_otp_out_transaction_cg_%s",get_full_name())); + endfunction + + // **************************************************************************** + // FUNCTION: write (T t) + // This function is automatically executed when a transaction arrives on the + // analysis_export. It copies values from the variables in the transaction + // to local variables used to collect functional coverage. + // + virtual function void write (T t); + `uvm_info("COV","Received transaction",UVM_HIGH); + coverage_trans = t; + fuse_ctrl_lc_otp_out_transaction_cg.sample(); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_typedefs.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_typedefs.svh new file mode 100644 index 0000000..f2a7bdb --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_typedefs.svh @@ -0,0 +1,34 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the host server when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_typedefs_hdl.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_typedefs_hdl.svh new file mode 100644 index 0000000..0d58518 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/src/fuse_ctrl_lc_otp_out_typedefs_hdl.svh @@ -0,0 +1,35 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the emulator when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/yaml/fuse_ctrl_lc_otp_out_interface.yaml b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/yaml/fuse_ctrl_lc_otp_out_interface.yaml new file mode 100644 index 0000000..5b9107e --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_lc_otp_out_pkg/yaml/fuse_ctrl_lc_otp_out_interface.yaml @@ -0,0 +1,37 @@ +uvmf: + interfaces: + fuse_ctrl_lc_otp_out: + clock: clk_i + config_constraints: [] + config_vars: [] + existing_library_component: 'True' + gen_inbound_streaming_driver: 'False' + hdl_pkg_parameters: [] + hdl_typedefs: [] + hvl_pkg_parameters: [] + hvl_typedefs: [] + parameters: [] + ports: + - dir: input + name: lc_otp_vendor_test_o + reset_value: '''bz' + width: '[''$bits(caliptra_otp_ctrl_pkg::lc_otp_vendor_test_rsp_t)'']' + - dir: input + name: lc_otp_program_o + reset_value: '''bz' + width: '[''$bits(caliptra_otp_ctrl_pkg::lc_otp_program_rsp_t)'']' + - dir: input + name: otp_lc_data_o + reset_value: '''bz' + width: '[''$bits(caliptra_otp_ctrl_pkg::otp_lc_data_t)'']' + reset: rst_ni + reset_assertion_level: 'False' + transaction_constraints: [] + transaction_vars: + - comment: '' + iscompare: 'True' + isrand: 'False' + name: otp_lc_data_o + type: caliptra_otp_ctrl_pkg::otp_lc_data_t + unpacked_dimension: '' + use_dpi_link: 'False' diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/.project b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/.project new file mode 100644 index 0000000..c96dcb4 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/.project @@ -0,0 +1,30 @@ + + + fuse_ctrl_out_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/.svproject b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/.svproject new file mode 100644 index 0000000..64d224a --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/Makefile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/Makefile new file mode 100644 index 0000000..b5ee9df --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/Makefile @@ -0,0 +1,66 @@ +# fuse_ctrl_out interface packages source +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +fuse_ctrl_out_PKG = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_out_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_filelist_hvl.f + +fuse_ctrl_out_PKG_HDL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_out_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_filelist_hdl.f + +fuse_ctrl_out_PKG_XRTL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_out_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_filelist_xrtl.f + +COMP_fuse_ctrl_out_PKG_TGT_0 = q_comp_fuse_ctrl_out_pkg +COMP_fuse_ctrl_out_PKG_TGT_1 = v_comp_fuse_ctrl_out_pkg +COMP_fuse_ctrl_out_PKG_TGT = $(COMP_fuse_ctrl_out_PKG_TGT_$(USE_VELOCE)) + +comp_fuse_ctrl_out_pkg: $(COMP_fuse_ctrl_out_PKG_TGT) + +q_comp_fuse_ctrl_out_pkg: + $(HDL_COMP_CMD) $(fuse_ctrl_out_PKG_HDL) + $(HVL_COMP_CMD) $(fuse_ctrl_out_PKG) + $(HDL_COMP_CMD) $(fuse_ctrl_out_PKG_XRTL) + +v_comp_fuse_ctrl_out_pkg: + $(HVL_COMP_CMD) $(fuse_ctrl_out_PKG_HDL) + $(HVL_COMP_CMD) $(fuse_ctrl_out_PKG) + $(VELANALYZE_CMD) $(fuse_ctrl_out_PKG_HDL) + $(VELANALYZE_HVL_CMD) $(fuse_ctrl_out_PKG) + $(HDL_COMP_CMD) $(fuse_ctrl_out_PKG_XRTL) + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export fuse_ctrl_out_IF_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_out_pkg/dpi + +C_FILE_COMPILE_LIST_fuse_ctrl_out_pkg = \ + +O_FILE_COMPILE_LIST_fuse_ctrl_out_pkg = $(notdir $(C_FILE_COMPILE_LIST_fuse_ctrl_out_pkg:.c=.o)) + +GCC_COMP_ARGS_fuse_ctrl_out_pkg += -I$(fuse_ctrl_out_IF_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_fuse_ctrl_out_pkg += $(fuse_ctrl_out_IF_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_fuse_ctrl_out_pkg += \ + \ + -o .so + +comp_fuse_ctrl_out_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Interface C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_fuse_ctrl_out_pkg) $(C_FILE_COMPILE_LIST_fuse_ctrl_out_pkg) + @echo "--------------------------------" + @echo "Linking Interface C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_fuse_ctrl_out_pkg) $(O_FILE_COMPILE_LIST_fuse_ctrl_out_pkg) + @echo "--------------------------------" + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/compile.do b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/compile.do new file mode 100644 index 0000000..5fdaafc --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/compile.do @@ -0,0 +1,14 @@ +# Tcl do file for compile of fuse_ctrl_out interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_out_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_filelist_hdl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_out_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_filelist_hvl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_out_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_filelist_xrtl.f \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out.compile new file mode 100644 index 0000000..3ac4b24 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out.compile @@ -0,0 +1,3 @@ +needs: + - fuse_ctrl_out_hvl.compile + - fuse_ctrl_out_hdl.compile diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_bfm.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_bfm.vinfo new file mode 100644 index 0000000..b4ea598 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_bfm.vinfo @@ -0,0 +1,6 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use fuse_ctrl_out_pkg_hdl.vinfo ++incdir+@vinfodir +src/fuse_ctrl_out_if.sv +src/fuse_ctrl_out_driver_bfm.sv +src/fuse_ctrl_out_monitor_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_common.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_common.compile new file mode 100644 index 0000000..1193b25 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_common.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +incdir: + - . + - ${uvm_path}/src +src: + - fuse_ctrl_out_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_filelist_hdl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_filelist_hdl.f new file mode 100644 index 0000000..5be2773 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_filelist_hdl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_filelist_hvl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_filelist_hvl.f new file mode 100644 index 0000000..fc769ad --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_filelist_hvl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_pkg.sv \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_filelist_xrtl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_filelist_xrtl.f new file mode 100644 index 0000000..4a7b8cc --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_filelist_xrtl.f @@ -0,0 +1,3 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_if.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_monitor_bfm.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_driver_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_hdl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_hdl.compile new file mode 100644 index 0000000..2745ad2 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_hdl.compile @@ -0,0 +1,9 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ./fuse_ctrl_out_common.compile +incdir: + - . +src: + - src/fuse_ctrl_out_if.sv + - src/fuse_ctrl_out_monitor_bfm.sv + - src/fuse_ctrl_out_driver_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_hvl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_hvl.compile new file mode 100644 index 0000000..5562a20 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_hvl.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ./fuse_ctrl_out_common.compile +incdir: + - . +src: + - fuse_ctrl_out_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_pkg.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_pkg.sv new file mode 100644 index 0000000..afb8df9 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_pkg.sv @@ -0,0 +1,91 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - + +// - +// - +// - + +// - +// - +// - + +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_out_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg_hdl::*; + import uvmf_base_pkg::*; + import fuse_ctrl_out_pkg_hdl::*; + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + `include "src/fuse_ctrl_out_macros.svh" + + export fuse_ctrl_out_pkg_hdl::*; + + + + // Parameters defined as HVL parameters + + `include "src/fuse_ctrl_out_typedefs.svh" + `include "src/fuse_ctrl_out_transaction.svh" + + `include "src/fuse_ctrl_out_configuration.svh" + `include "src/fuse_ctrl_out_driver.svh" + `include "src/fuse_ctrl_out_monitor.svh" + + `include "src/fuse_ctrl_out_transaction_coverage.svh" + `include "src/fuse_ctrl_out_sequence_base.svh" + `include "src/fuse_ctrl_out_random_sequence.svh" + + `include "src/fuse_ctrl_out_responder_sequence.svh" + `include "src/fuse_ctrl_out2reg_adapter.svh" + + `include "src/fuse_ctrl_out_agent.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new interface sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the interface package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_pkg.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_pkg.vinfo new file mode 100644 index 0000000..4f08c9e --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_pkg.vinfo @@ -0,0 +1,4 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use fuse_ctrl_out_pkg_hdl.vinfo ++incdir+@vinfodir +fuse_ctrl_out_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_pkg_hdl.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_pkg_hdl.sv new file mode 100644 index 0000000..f90777a --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_pkg_hdl.sv @@ -0,0 +1,52 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that needs to be compiled and synthesized +// for running on Veloce. +// +// CONTAINS: +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_out_pkg_hdl; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HDL parameters + + `include "src/fuse_ctrl_out_typedefs_hdl.svh" + `include "src/fuse_ctrl_out_macros.svh" + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_pkg_hdl.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_pkg_hdl.vinfo new file mode 100644 index 0000000..c55df62 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_pkg_hdl.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +fuse_ctrl_out_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_pkg_sve.F b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_pkg_sve.F new file mode 100644 index 0000000..94ccd9b --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_pkg_sve.F @@ -0,0 +1,10 @@ +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + ++incdir+. +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_filelist_hdl.f +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_out_pkg/fuse_ctrl_out_filelist_hvl.f diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out2reg_adapter.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out2reg_adapter.svh new file mode 100644 index 0000000..2b7cf97 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out2reg_adapter.svh @@ -0,0 +1,142 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the UVM register adapter for the fuse_ctrl_out interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_out2reg_adapter #( + int AlertSyncOn = 3, + caliptra_otp_ctrl_pkg::lfsr_seed_t RndConstLfrSeed = caliptra_otp_ctrl_pkg::RndCnstLfsrSeedDefault, + caliptra_otp_ctrl_pkg::lfsr_perm_t RndCnstLfsrPerm = caliptra_otp_ctrl_pkg::RndCnstLfsrPermDefault, + string MemInitFile = "/home/ws/caliptra/anjpar/ws1/chipsalliance/caliptra-rtl/src/fuse_ctrl/data/otp-img.2048.vmem" + ) + extends uvm_reg_adapter; + + `uvm_object_param_utils( fuse_ctrl_out2reg_adapter #( + AlertSyncOn, + RndConstLfrSeed, + RndCnstLfsrPerm, + MemInitFile + ) +) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //-------------------------------------------------------------------- + // new + //-------------------------------------------------------------------- + function new (string name = "fuse_ctrl_out2reg_adapter" ); + super.new(name); + // pragma uvmf custom new begin + // UVMF_CHANGE_ME : Configure the adapter regarding byte enables and provides response. + + // Does the protocol the Agent is modeling support byte enables? + // 0 = NO + // 1 = YES + supports_byte_enable = 0; + + // Does the Agent's Driver provide separate response sequence items? + // i.e. Does the driver call seq_item_port.put() + // and do the sequences call get_response()? + // 0 = NO + // 1 = YES + provides_responses = 0; + // pragma uvmf custom new end + + endfunction: new + + //-------------------------------------------------------------------- + // reg2bus + //-------------------------------------------------------------------- + virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw); + + fuse_ctrl_out_transaction #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) + trans_h = fuse_ctrl_out_transaction #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) +::type_id::create("trans_h"); + + // pragma uvmf custom reg2bus begin + // UVMF_CHANGE_ME : Fill in the reg2bus adapter mapping registe fields to protocol fields. + + //Adapt the following for your sequence item type + // trans_h.op = (rw.kind == UVM_READ) ? WB_READ : WB_WRITE; + //Copy over address + // trans_h.addr = rw.addr; + //Copy over write data + // trans_h.data = rw.data; + + // pragma uvmf custom reg2bus end + + // Return the adapted transaction + return trans_h; + + endfunction: reg2bus + + //-------------------------------------------------------------------- + // bus2reg + //-------------------------------------------------------------------- + virtual function void bus2reg(uvm_sequence_item bus_item, + ref uvm_reg_bus_op rw); + fuse_ctrl_out_transaction #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) + trans_h; + if (!$cast(trans_h, bus_item)) begin + `uvm_fatal("ADAPT","Provided bus_item is not of the correct type") + return; + end + // pragma uvmf custom bus2reg begin + // UVMF_CHANGE_ME : Fill in the bus2reg adapter mapping protocol fields to register fields. + //Adapt the following for your sequence item type + //Copy over instruction type + // rw.kind = (trans_h.op == WB_WRITE) ? UVM_WRITE : UVM_READ; + //Copy over address + // rw.addr = trans_h.addr; + //Copy over read data + // rw.data = trans_h.data; + //Check for errors on the bus and return UVM_NOT_OK if there is an error + // rw.status = UVM_IS_OK; + // pragma uvmf custom bus2reg end + + endfunction: bus2reg + +endclass : fuse_ctrl_out2reg_adapter + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_agent.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_agent.svh new file mode 100644 index 0000000..515daaf --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_agent.svh @@ -0,0 +1,109 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: Protocol specific agent class definition +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_out_agent #( + int AlertSyncOn = 3, + caliptra_otp_ctrl_pkg::lfsr_seed_t RndConstLfrSeed = caliptra_otp_ctrl_pkg::RndCnstLfsrSeedDefault, + caliptra_otp_ctrl_pkg::lfsr_perm_t RndCnstLfsrPerm = caliptra_otp_ctrl_pkg::RndCnstLfsrPermDefault, + string MemInitFile = "/home/ws/caliptra/anjpar/ws1/chipsalliance/caliptra-rtl/src/fuse_ctrl/data/otp-img.2048.vmem" + ) + extends uvmf_parameterized_agent #( + .CONFIG_T(fuse_ctrl_out_configuration #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) +), + .DRIVER_T(fuse_ctrl_out_driver #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) +), + .MONITOR_T(fuse_ctrl_out_monitor #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) +), + .COVERAGE_T(fuse_ctrl_out_transaction_coverage #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) +), + .TRANS_T(fuse_ctrl_out_transaction #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) +) + ); + + `uvm_component_param_utils( fuse_ctrl_out_agent #( + AlertSyncOn, + RndConstLfrSeed, + RndCnstLfsrPerm, + MemInitFile + ) +) + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** + // FUNCTION: build_phase + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + if (configuration.active_passive == ACTIVE) begin + // Place sequencer handle into configuration object + // so that it may be retrieved from configuration + // rather than using uvm_config_db + configuration.sequencer = this.sequencer; + end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_configuration.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_configuration.svh new file mode 100644 index 0000000..3ca84ba --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_configuration.svh @@ -0,0 +1,241 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class contains all variables and functions used +// to configure the fuse_ctrl_out agent and its bfm's. It gets the +// bfm's from the uvm_config_db for use by the agent. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_out_configuration #( + int AlertSyncOn = 3, + caliptra_otp_ctrl_pkg::lfsr_seed_t RndConstLfrSeed = caliptra_otp_ctrl_pkg::RndCnstLfsrSeedDefault, + caliptra_otp_ctrl_pkg::lfsr_perm_t RndCnstLfsrPerm = caliptra_otp_ctrl_pkg::RndCnstLfsrPermDefault, + string MemInitFile = "/home/ws/caliptra/anjpar/ws1/chipsalliance/caliptra-rtl/src/fuse_ctrl/data/otp-img.2048.vmem" + ) + extends uvmf_parameterized_agent_configuration_base #( + .DRIVER_BFM_BIND_T(virtual fuse_ctrl_out_driver_bfm #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) +), + .MONITOR_BFM_BIND_T( virtual fuse_ctrl_out_monitor_bfm #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) +)); + + `uvm_object_param_utils( fuse_ctrl_out_configuration #( + AlertSyncOn, + RndConstLfrSeed, + RndCnstLfsrPerm, + MemInitFile + ) +) + + + // Sequencer handle populated by agent + uvm_sequencer #(fuse_ctrl_out_transaction #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) + ) sequencer; + + //Constraints for the configuration variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + covergroup fuse_ctrl_out_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + // pragma uvmf custom covergroup end + endgroup + + //******************************************************************* + //******************************************************************* + // Structure used to pass configuration variables to monitor and driver BFM's. + // Use to_struct function to pack variables into structure. + // Use from_struct function to unpack variables from structure. + // This structure is defined in fuse_ctrl_out_macros.svh + `fuse_ctrl_out_CONFIGURATION_STRUCT + fuse_ctrl_out_configuration_s fuse_ctrl_out_configuration_struct; + //******************************************************************* + // FUNCTION: to_struct() + // This function packs variables into a fuse_ctrl_out_configuration_s + // structure. The function returns the handle to the fuse_ctrl_out_configuration_struct. + // This function is defined in fuse_ctrl_out_macros.svh + `fuse_ctrl_out_CONFIGURATION_TO_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_struct() + // This function unpacks the struct provided as an argument into + // variables of this class. + // This function is defined in fuse_ctrl_out_macros.svh + `fuse_ctrl_out_CONFIGURATION_FROM_STRUCT_FUNCTION + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + // Construct the covergroup for this configuration class + fuse_ctrl_out_configuration_cg = new; + endfunction + + // **************************************************************************** + // FUNCTION: post_randomize() + // This function is automatically called after the randomize() function + // is executed. + // + function void post_randomize(); + super.post_randomize(); + fuse_ctrl_out_configuration_cg.sample(); + endfunction + + // **************************************************************************** + // FUNCTION: initialize + // This function causes the configuration to retrieve + // its virtual interface handle from the uvm_config_db. + // This function also makes itself available to its + // agent through the uvm_config_db. + // + // ARGUMENTS: + // uvmf_active_passive_t activity: + // This argument identifies the simulation level + // as either BLOCK, CHIP, SIMULATION, etc. + // + // AGENT_PATH: + // This argument identifies the path to this + // configurations agent. This configuration + // makes itself available to the agent specified + // by agent_path by placing itself into the + // uvm_config_db. + // + // INTERFACE_NAME: + // This argument identifies the string name of + // this configurations BFM's. This string + // name is used to retrieve the driver and + // monitor BFM from the uvm_config_db. + // + virtual function void initialize(uvmf_active_passive_t activity, + string agent_path, + string interface_name); + + super.initialize( activity, agent_path, interface_name); + // The covergroup is given the same name as the interface + fuse_ctrl_out_configuration_cg.set_inst_name(interface_name); + + // This configuration places itself into the uvm_config_db for the agent, identified by the agent_path variable, to retrieve. + uvm_config_db #( fuse_ctrl_out_configuration #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) + + )::set( null ,agent_path,UVMF_AGENT_CONFIG, this ); + + // This configuration also places itself in the config db using the same identifier used by the interface. This allows users to access + // configuration variables and the interface through the bfm api class rather than directly accessing the BFM. This is useful for + // accessingthe BFM when using Veloce + uvm_config_db #( fuse_ctrl_out_configuration #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) + + )::set( null ,UVMF_CONFIGURATIONS, interface_name, this ); + + fuse_ctrl_out_configuration_cg.set_inst_name($sformatf("fuse_ctrl_out_configuration_cg_%s",get_full_name())); + +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. + `uvm_info("CFG", + $psprintf("The agent at '%s' is using interface named %s has the following parameters: AlertSyncOn=%x RndConstLfrSeed=%x RndCnstLfsrPerm=%x MemInitFile=%x ", agent_path, interface_name, AlertSyncOn ,RndConstLfrSeed ,RndCnstLfsrPerm ,MemInitFile ), + UVM_DEBUG) + + // pragma uvmf custom initialize begin + // This controls whether or not the agent returns a transaction handle in the driver when calling + // item_done() back into the sequencer or not. If set to 1, a transaction is sent back which means + // the sequence on the other end must use the get_response() part of the driver/sequence API. If + // this doesn't occur, there will eventually be response_queue overflow errors during the test. + return_transaction_response = 1'b0; + + // pragma uvmf custom initialize end + + endfunction + + // **************************************************************************** + // TASK: wait_for_reset + // *[Required]* Blocks until reset is released. The wait_for_reset operation is performed + // by a task in the monitor bfm. + virtual task wait_for_reset(); + monitor_bfm.wait_for_reset(); + endtask + + // **************************************************************************** + // TASK: wait_for_num_clocks + // *[Required]* Blocks until specified number of clocks have elapsed. The wait_for_num_clocks + // operation is performed by a task in the monitor bfm. + virtual task wait_for_num_clocks(int clocks); + monitor_bfm.wait_for_num_clocks(clocks); + endtask + + // **************************************************************************** + // FUNCTION : convert2string() + // This function is used to convert variables in this class into a string for log messaging. + // + virtual function string convert2string (); + // pragma uvmf custom convert2string begin + return $sformatf(""); + // pragma uvmf custom convert2string end + endfunction + + // **************************************************************************** + // FUNCTION: get_sequencer + function uvm_sequencer #(fuse_ctrl_out_transaction#( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) +) get_sequencer(); + return sequencer; + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_driver.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_driver.svh new file mode 100644 index 0000000..b894382 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_driver.svh @@ -0,0 +1,141 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class passes transactions between the sequencer +// and the BFM driver interface. It accesses the driver BFM +// through the bfm handle. This driver +// passes transactions to the driver BFM through the access +// task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_out_driver #( + int AlertSyncOn = 3, + caliptra_otp_ctrl_pkg::lfsr_seed_t RndConstLfrSeed = caliptra_otp_ctrl_pkg::RndCnstLfsrSeedDefault, + caliptra_otp_ctrl_pkg::lfsr_perm_t RndCnstLfsrPerm = caliptra_otp_ctrl_pkg::RndCnstLfsrPermDefault, + string MemInitFile = "/home/ws/caliptra/anjpar/ws1/chipsalliance/caliptra-rtl/src/fuse_ctrl/data/otp-img.2048.vmem" + ) + extends uvmf_driver_base #( + .CONFIG_T(fuse_ctrl_out_configuration #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) + ), + .BFM_BIND_T(virtual fuse_ctrl_out_driver_bfm #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) + ), + .REQ(fuse_ctrl_out_transaction #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) + ), + .RSP(fuse_ctrl_out_transaction #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) + )); + + `uvm_component_param_utils( fuse_ctrl_out_driver #( + AlertSyncOn, + RndConstLfrSeed, + RndCnstLfsrPerm, + MemInitFile + ) +) +//******************************************************************* +// Macros that define structs located in fuse_ctrl_out_macros.svh +//******************************************************************* +// Initiator macro used by fuse_ctrl_out_driver and fuse_ctrl_out_driver_bfm +// to communicate initiator driven data to fuse_ctrl_out_driver_bfm. +`fuse_ctrl_out_INITIATOR_STRUCT + fuse_ctrl_out_initiator_s fuse_ctrl_out_initiator_struct; +//******************************************************************* +// Responder macro used by fuse_ctrl_out_driver and fuse_ctrl_out_driver_bfm +// to communicate Responder driven data to fuse_ctrl_out_driver_bfm. +`fuse_ctrl_out_RESPONDER_STRUCT + fuse_ctrl_out_responder_s fuse_ctrl_out_responder_struct; + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent=null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the driver BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// driver BFM. This allows the driver BFM to call tasks and function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// **************************************************************************** +// This task is called by the run_phase in uvmf_driver_base. + virtual task access( inout REQ txn ); +// pragma uvmf custom access begin + if (configuration.initiator_responder==RESPONDER) begin + // Complete current transfer and wait for next transfer + bfm.respond_and_wait_for_next_transfer( + fuse_ctrl_out_initiator_struct, + txn.to_responder_struct() + ); + // Unpack information about initiated transfer received by this responder + txn.from_initiator_struct(fuse_ctrl_out_initiator_struct); + end else begin + // Initiate a transfer and get response + bfm.initiate_and_get_response( + txn.to_initiator_struct(), + fuse_ctrl_out_responder_struct + ); + // Unpack transfer response information received by this initiator + txn.from_responder_struct(fuse_ctrl_out_responder_struct); + end +// pragma uvmf custom access end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_driver_bfm.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_driver_bfm.sv new file mode 100644 index 0000000..a58bda2 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_driver_bfm.sv @@ -0,0 +1,368 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This interface performs the fuse_ctrl_out signal driving. It is +// accessed by the uvm fuse_ctrl_out driver through a virtual interface +// handle in the fuse_ctrl_out configuration. It drives the singals passed +// in through the port connection named bus of type fuse_ctrl_out_if. +// +// Input signals from the fuse_ctrl_out_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// This bfm drives signals with a _o suffix. These signals +// are driven onto signals within fuse_ctrl_out_if based on INITIATOR/RESPONDER and/or +// ARBITRATION/GRANT status. +// +// The output signal connections are as follows: +// signal_o -> bus.signal +// +// +// Interface functions and tasks used by UVM components: +// +// configure: +// This function gets configuration attributes from the +// UVM driver to set any required BFM configuration +// variables such as 'initiator_responder'. +// +// initiate_and_get_response: +// This task is used to perform signaling activity for initiating +// a protocol transfer. The task initiates the transfer, using +// input data from the initiator struct. Then the task captures +// response data, placing the data into the response struct. +// The response struct is returned to the driver class. +// +// respond_and_wait_for_next_transfer: +// This task is used to complete a current transfer as a responder +// and then wait for the initiator to start the next transfer. +// The task uses data in the responder struct to drive protocol +// signals to complete the transfer. The task then waits for +// the next transfer. Once the next transfer begins, data from +// the initiator is placed into the initiator struct and sent +// to the responder sequence for processing to determine +// what data to respond with. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_out_pkg_hdl::*; +`include "src/fuse_ctrl_out_macros.svh" + +interface fuse_ctrl_out_driver_bfm #( + int AlertSyncOn = 3, + caliptra_otp_ctrl_pkg::lfsr_seed_t RndConstLfrSeed = caliptra_otp_ctrl_pkg::RndCnstLfsrSeedDefault, + caliptra_otp_ctrl_pkg::lfsr_perm_t RndCnstLfsrPerm = caliptra_otp_ctrl_pkg::RndCnstLfsrPermDefault, + string MemInitFile = "/home/ws/caliptra/anjpar/ws1/chipsalliance/caliptra-rtl/src/fuse_ctrl/data/otp-img.2048.vmem" + ) + + (fuse_ctrl_out_if bus); + // The following pragma and additional ones in-lined further below are for running this BFM on Veloce + // pragma attribute fuse_ctrl_out_driver_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: AlertSyncOn=%x RndConstLfrSeed=%x RndCnstLfsrPerm=%x MemInitFile=%x ", AlertSyncOn,RndConstLfrSeed,RndCnstLfsrPerm,MemInitFile), + UVM_DEBUG) +end +`endif + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + tri clk_i_i; + tri rst_ni_i; + + // Signal list (all signals are capable of being inputs and outputs for the sake + // of supporting both INITIATOR and RESPONDER mode operation. Expectation is that + // directionality in the config file was from the point-of-view of the INITIATOR + + // INITIATOR mode input signals + tri [$bits(edn_pkg::edn_req_t)-1:0] edn_o_i; + reg [$bits(edn_pkg::edn_req_t)-1:0] edn_o_o = 'bz; + tri intr_otp_operation_done_o_i; + reg intr_otp_operation_done_o_o = 'bz; + tri intr_otp_error_o_i; + reg intr_otp_error_o_o = 'bz; + tri [ast_pkg::NumAlerts * $bits(caliptra_prim_alert_pkg::alert_tx_t)-1:0] alert_tx_o_i; + reg [ast_pkg::NumAlerts * $bits(caliptra_prim_alert_pkg::alert_tx_t)-1:0] alert_tx_o_o = 'bz; + tri [7:0] otp_obs_o_i; + reg [7:0] otp_obs_o_o = 'bz; + tri [$bits(caliptra_otp_ctrl_pkg::otp_ast_req_t)-1:0] otp_ast_pwr_seq_o_i; + reg [$bits(caliptra_otp_ctrl_pkg::otp_ast_req_t)-1:0] otp_ast_pwr_seq_o_o = 'bz; + tri [$bits(caliptra_otp_ctrl_part_pkg::otp_broadcast_t)-1:0] otp_broadcast_o_i; + reg [$bits(caliptra_otp_ctrl_part_pkg::otp_broadcast_t)-1:0] otp_broadcast_o_o = 'bz; + tri [caliptra_otp_ctrl_pkg::OtpTestVectWidth-1:0] cio_test_o_i; + reg [caliptra_otp_ctrl_pkg::OtpTestVectWidth-1:0] cio_test_o_o = 'bz; + tri [caliptra_otp_ctrl_pkg::OtpTestVectWidth-1:0] cio_test_en_o_i; + reg [caliptra_otp_ctrl_pkg::OtpTestVectWidth-1:0] cio_test_en_o_o = 'bz; + + // INITIATOR mode output signals + + // Bi-directional signals + + + assign clk_i_i = bus.clk_i; + assign rst_ni_i = bus.rst_ni; + + // These are signals marked as 'input' by the config file, but the signals will be + // driven by this BFM if put into RESPONDER mode (flipping all signal directions around) + assign edn_o_i = bus.edn_o; + assign bus.edn_o = (initiator_responder == RESPONDER) ? edn_o_o : 'bz; + assign intr_otp_operation_done_o_i = bus.intr_otp_operation_done_o; + assign bus.intr_otp_operation_done_o = (initiator_responder == RESPONDER) ? intr_otp_operation_done_o_o : 'bz; + assign intr_otp_error_o_i = bus.intr_otp_error_o; + assign bus.intr_otp_error_o = (initiator_responder == RESPONDER) ? intr_otp_error_o_o : 'bz; + assign alert_tx_o_i = bus.alert_tx_o; + assign bus.alert_tx_o = (initiator_responder == RESPONDER) ? alert_tx_o_o : 'bz; + assign otp_obs_o_i = bus.otp_obs_o; + assign bus.otp_obs_o = (initiator_responder == RESPONDER) ? otp_obs_o_o : 'bz; + assign otp_ast_pwr_seq_o_i = bus.otp_ast_pwr_seq_o; + assign bus.otp_ast_pwr_seq_o = (initiator_responder == RESPONDER) ? otp_ast_pwr_seq_o_o : 'bz; + assign otp_broadcast_o_i = bus.otp_broadcast_o; + assign bus.otp_broadcast_o = (initiator_responder == RESPONDER) ? otp_broadcast_o_o : 'bz; + assign cio_test_o_i = bus.cio_test_o; + assign bus.cio_test_o = (initiator_responder == RESPONDER) ? cio_test_o_o : 'bz; + assign cio_test_en_o_i = bus.cio_test_en_o; + assign bus.cio_test_en_o = (initiator_responder == RESPONDER) ? cio_test_en_o_o : 'bz; + + + // These are signals marked as 'output' by the config file, but the outputs will + // not be driven by this BFM unless placed in INITIATOR mode. + + // Proxy handle to UVM driver + fuse_ctrl_out_pkg::fuse_ctrl_out_driver #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) + proxy; + // pragma tbx oneway proxy.my_function_name_in_uvm_driver + + // **************************************************************************** + // **************************************************************************** + // Macros that define structs located in fuse_ctrl_out_macros.svh + // **************************************************************************** + // Struct for passing configuration data from fuse_ctrl_out_driver to this BFM + // **************************************************************************** + `fuse_ctrl_out_CONFIGURATION_STRUCT + // **************************************************************************** + // Structs for INITIATOR and RESPONDER data flow + //******************************************************************* + // Initiator macro used by fuse_ctrl_out_driver and fuse_ctrl_out_driver_bfm + // to communicate initiator driven data to fuse_ctrl_out_driver_bfm. + `fuse_ctrl_out_INITIATOR_STRUCT + fuse_ctrl_out_initiator_s initiator_struct; + // Responder macro used by fuse_ctrl_out_driver and fuse_ctrl_out_driver_bfm + // to communicate Responder driven data to fuse_ctrl_out_driver_bfm. + `fuse_ctrl_out_RESPONDER_STRUCT + fuse_ctrl_out_responder_s responder_struct; + + // **************************************************************************** +// pragma uvmf custom reset_condition_and_response begin + // Always block used to return signals to reset value upon assertion of reset + always @( negedge rst_ni_i ) + begin + // RESPONDER mode output signals + edn_o_o <= 'bz; + intr_otp_operation_done_o_o <= 'bz; + intr_otp_error_o_o <= 'bz; + alert_tx_o_o <= 'bz; + otp_obs_o_o <= 'bz; + otp_ast_pwr_seq_o_o <= 'bz; + otp_broadcast_o_o <= 'bz; + cio_test_o_o <= 'bz; + cio_test_en_o_o <= 'bz; + // INITIATOR mode output signals + // Bi-directional signals + end +// pragma uvmf custom reset_condition_and_response end + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the driver BFM. It is called by the driver within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the driver BFM needs to be aware of the new configuration + // variables. + // + + function void configure(fuse_ctrl_out_configuration_s fuse_ctrl_out_configuration_arg); // pragma tbx xtf + initiator_responder = fuse_ctrl_out_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + +// pragma uvmf custom initiate_and_get_response begin +// **************************************************************************** +// UVMF_CHANGE_ME +// This task is used by an initator. The task first initiates a transfer then +// waits for the responder to complete the transfer. + task initiate_and_get_response( + // This argument passes transaction variables used by an initiator + // to perform the initial part of a protocol transfer. The values + // come from a sequence item created in a sequence. + input fuse_ctrl_out_initiator_s fuse_ctrl_out_initiator_struct, + // This argument is used to send data received from the responder + // back to the sequence item. The sequence item is returned to the sequence. + output fuse_ctrl_out_responder_s fuse_ctrl_out_responder_struct + );// pragma tbx xtf + // + // Members within the fuse_ctrl_out_initiator_struct: + // otp_lc_data_t otp_lc_data_o ; + // pwrmgr_pkg::pwr_otp_rsp_t pwr_otp_o ; + // Members within the fuse_ctrl_out_responder_struct: + // otp_lc_data_t otp_lc_data_o ; + // pwrmgr_pkg::pwr_otp_rsp_t pwr_otp_o ; + initiator_struct = fuse_ctrl_out_initiator_struct; + // + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clk_i_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available initiator input and inout signals listed. + // Initiator input signals + // fuse_ctrl_out_responder_struct.xyz = edn_o_i; // [$bits(edn_pkg::edn_req_t)-1:0] + // fuse_ctrl_out_responder_struct.xyz = intr_otp_operation_done_o_i; // + // fuse_ctrl_out_responder_struct.xyz = intr_otp_error_o_i; // + // fuse_ctrl_out_responder_struct.xyz = alert_tx_o_i; // [NumAlerts * $bits(caliptra_prim_alert_pkg::alert_tx_t)-1:0] + // fuse_ctrl_out_responder_struct.xyz = otp_obs_o_i; // [7:0] + // fuse_ctrl_out_responder_struct.xyz = otp_ast_pwr_seq_o_i; // [$bits(caliptra_otp_ctrl_pkg::otp_ast_req_t)-1:0] + // fuse_ctrl_out_responder_struct.xyz = pwr_otp_o_i; // [$bits(pwrmgr_pkg::pwr_otp_rsp_t)-1:0] + // fuse_ctrl_out_responder_struct.xyz = lc_otp_vendor_test_o_i; // [$bits(lc_otp_vendor_test_rsp_t)-1:0] + // fuse_ctrl_out_responder_struct.xyz = lc_otp_program_o_i; // [$bits(lc_otp_program_rsp_t)-1:0] + // fuse_ctrl_out_responder_struct.xyz = otp_lc_data_o_i; // [$bits(otp_lc_data_t)-1:0] + // fuse_ctrl_out_responder_struct.xyz = otp_broadcast_o_i; // [$bits(otp_broadcast_t)-1:0] + // fuse_ctrl_out_responder_struct.xyz = cio_test_o_i; // [OtpTestVectWidth-1:0] + // fuse_ctrl_out_responder_struct.xyz = cio_test_en_o_i; // [OtpTestVectWidth-1:0] + // Initiator inout signals + // fuse_ctrl_out_responder_struct.xyz = otp_ext_voltage_h_io_i; // + // How to assign a signal from an initiator struct member named xyz. + // All available initiator output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Initiator output signals + // Initiator inout signals + // otp_ext_voltage_h_io_o <= fuse_ctrl_out_initiator_struct.xyz; // + // Initiate a transfer using the data received. + @(posedge clk_i_i); + @(posedge clk_i_i); + // Wait for the responder to complete the transfer then place the responder data into + // fuse_ctrl_out_responder_struct. + @(posedge clk_i_i); + @(posedge clk_i_i); + responder_struct = fuse_ctrl_out_responder_struct; + endtask +// pragma uvmf custom initiate_and_get_response end + +// pragma uvmf custom respond_and_wait_for_next_transfer begin +// **************************************************************************** +// The first_transfer variable is used to prevent completing a transfer in the +// first call to this task. For the first call to this task, there is not +// current transfer to complete. +bit first_transfer=1; + +// UVMF_CHANGE_ME +// This task is used by a responder. The task first completes the current +// transfer in progress then waits for the initiator to start the next transfer. + task respond_and_wait_for_next_transfer( + // This argument is used to send data received from the initiator + // back to the sequence item. The sequence determines how to respond. + output fuse_ctrl_out_initiator_s fuse_ctrl_out_initiator_struct, + // This argument passes transaction variables used by a responder + // to complete a protocol transfer. The values come from a sequence item. + input fuse_ctrl_out_responder_s fuse_ctrl_out_responder_struct + );// pragma tbx xtf + // Variables within the fuse_ctrl_out_initiator_struct: + // otp_lc_data_t otp_lc_data_o ; + // pwrmgr_pkg::pwr_otp_rsp_t pwr_otp_o ; + // Variables within the fuse_ctrl_out_responder_struct: + // otp_lc_data_t otp_lc_data_o ; + // pwrmgr_pkg::pwr_otp_rsp_t pwr_otp_o ; + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clk_i_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available responder input and inout signals listed. + // Responder input signals + // Responder inout signals + // fuse_ctrl_out_responder_struct.xyz = otp_ext_voltage_h_io_i; // + // How to assign a signal, named xyz, from an initiator struct member. + // All available responder output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Responder output signals + // edn_o_o <= fuse_ctrl_out_initiator_struct.xyz; // [$bits(edn_pkg::edn_req_t)-1:0] + // intr_otp_operation_done_o_o <= fuse_ctrl_out_initiator_struct.xyz; // + // intr_otp_error_o_o <= fuse_ctrl_out_initiator_struct.xyz; // + // alert_tx_o_o <= fuse_ctrl_out_initiator_struct.xyz; // [NumAlerts * $bits(caliptra_prim_alert_pkg::alert_tx_t)-1:0] + // otp_obs_o_o <= fuse_ctrl_out_initiator_struct.xyz; // [7:0] + // otp_ast_pwr_seq_o_o <= fuse_ctrl_out_initiator_struct.xyz; // [$bits(caliptra_otp_ctrl_pkg::otp_ast_req_t)-1:0] + // pwr_otp_o_o <= fuse_ctrl_out_initiator_struct.xyz; // [$bits(pwrmgr_pkg::pwr_otp_rsp_t)-1:0] + // lc_otp_vendor_test_o_o <= fuse_ctrl_out_initiator_struct.xyz; // [$bits(lc_otp_vendor_test_rsp_t)-1:0] + // lc_otp_program_o_o <= fuse_ctrl_out_initiator_struct.xyz; // [$bits(lc_otp_program_rsp_t)-1:0] + // otp_lc_data_o_o <= fuse_ctrl_out_initiator_struct.xyz; // [$bits(otp_lc_data_t)-1:0] + // otp_broadcast_o_o <= fuse_ctrl_out_initiator_struct.xyz; // [$bits(otp_broadcast_t)-1:0] + // cio_test_o_o <= fuse_ctrl_out_initiator_struct.xyz; // [OtpTestVectWidth-1:0] + // cio_test_en_o_o <= fuse_ctrl_out_initiator_struct.xyz; // [OtpTestVectWidth-1:0] + // Responder inout signals + // otp_ext_voltage_h_io_o <= fuse_ctrl_out_initiator_struct.xyz; // + + @(posedge clk_i_i); + if (!first_transfer) begin + // Perform transfer response here. + // Reply using data recieved in the fuse_ctrl_out_responder_struct. + @(posedge clk_i_i); + // Reply using data recieved in the transaction handle. + @(posedge clk_i_i); + end + // Wait for next transfer then gather info from intiator about the transfer. + // Place the data into the fuse_ctrl_out_initiator_struct. + @(posedge clk_i_i); + @(posedge clk_i_i); + first_transfer = 0; + endtask +// pragma uvmf custom respond_and_wait_for_next_transfer end + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_if.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_if.sv new file mode 100644 index 0000000..6647c95 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_if.sv @@ -0,0 +1,124 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface contains the fuse_ctrl_out interface signals. +// It is instantiated once per fuse_ctrl_out bus. Bus Functional Models, +// BFM's named fuse_ctrl_out_driver_bfm, are used to drive signals on the bus. +// BFM's named fuse_ctrl_out_monitor_bfm are used to monitor signals on the +// bus. This interface signal bundle is passed in the port list of +// the BFM in order to give the BFM access to the signals in this +// interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// This template can be used to connect a DUT to these signals +// +// .dut_signal_port(fuse_ctrl_out_bus.edn_o), // Agent input +// .dut_signal_port(fuse_ctrl_out_bus.intr_otp_operation_done_o), // Agent input +// .dut_signal_port(fuse_ctrl_out_bus.intr_otp_error_o), // Agent input +// .dut_signal_port(fuse_ctrl_out_bus.alert_tx_o), // Agent input +// .dut_signal_port(fuse_ctrl_out_bus.otp_obs_o), // Agent input +// .dut_signal_port(fuse_ctrl_out_bus.otp_ast_pwr_seq_o), // Agent input +// .dut_signal_port(fuse_ctrl_out_bus.otp_broadcast_o), // Agent input +// .dut_signal_port(fuse_ctrl_out_bus.cio_test_o), // Agent input +// .dut_signal_port(fuse_ctrl_out_bus.cio_test_en_o), // Agent input + +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_out_pkg_hdl::*; + +interface fuse_ctrl_out_if #( + int AlertSyncOn = 3, + caliptra_otp_ctrl_pkg::lfsr_seed_t RndConstLfrSeed = caliptra_otp_ctrl_pkg::RndCnstLfsrSeedDefault, + caliptra_otp_ctrl_pkg::lfsr_perm_t RndCnstLfsrPerm = caliptra_otp_ctrl_pkg::RndCnstLfsrPermDefault, + string MemInitFile = "/home/ws/caliptra/anjpar/ws1/chipsalliance/caliptra-rtl/src/fuse_ctrl/data/otp-img.2048.vmem" + ) + + + ( + input tri clk_i, + input tri rst_ni, + inout tri [$bits(edn_pkg::edn_req_t)-1:0] edn_o, + inout tri intr_otp_operation_done_o, + inout tri intr_otp_error_o, + inout tri [ast_pkg::NumAlerts * $bits(caliptra_prim_alert_pkg::alert_tx_t)-1:0] alert_tx_o, + inout tri [7:0] otp_obs_o, + inout tri [$bits(caliptra_otp_ctrl_pkg::otp_ast_req_t)-1:0] otp_ast_pwr_seq_o, + inout tri [$bits(caliptra_otp_ctrl_part_pkg::otp_broadcast_t)-1:0] otp_broadcast_o, + inout tri [caliptra_otp_ctrl_pkg::OtpTestVectWidth-1:0] cio_test_o, + inout tri [caliptra_otp_ctrl_pkg::OtpTestVectWidth-1:0] cio_test_en_o + ); + +modport monitor_port + ( + input clk_i, + input rst_ni, + input edn_o, + input intr_otp_operation_done_o, + input intr_otp_error_o, + input alert_tx_o, + input otp_obs_o, + input otp_ast_pwr_seq_o, + input otp_broadcast_o, + input cio_test_o, + input cio_test_en_o + ); + +modport initiator_port + ( + input clk_i, + input rst_ni, + input edn_o, + input intr_otp_operation_done_o, + input intr_otp_error_o, + input alert_tx_o, + input otp_obs_o, + input otp_ast_pwr_seq_o, + input otp_broadcast_o, + input cio_test_o, + input cio_test_en_o + ); + +modport responder_port + ( + input clk_i, + input rst_ni, + output edn_o, + output intr_otp_operation_done_o, + output intr_otp_error_o, + output alert_tx_o, + output otp_obs_o, + output otp_ast_pwr_seq_o, + output otp_broadcast_o, + output cio_test_o, + output cio_test_en_o + ); + + +// pragma uvmf custom interface_item_additional begin +// pragma uvmf custom interface_item_additional end + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_infact_coverage_strategy.csv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_infact_coverage_strategy.csv new file mode 100644 index 0000000..1c218e1 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_infact_coverage_strategy.csv @@ -0,0 +1,6 @@ +Global +auto_bin_max, 64 + +Name,Type,Include +rand_fields,coverpoint,=rand *.** + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_macros.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_macros.svh new file mode 100644 index 0000000..3002819 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_macros.svh @@ -0,0 +1,135 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains macros used with the fuse_ctrl_out package. +// These macros include packed struct definitions. These structs are +// used to pass data between classes, hvl, and BFM's, hdl. Use of +// structs are more efficient and simpler to modify. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_struct +// and from_struct methods defined in the macros below that are used in +// the fuse_ctrl_out_configuration class. +// + `define fuse_ctrl_out_CONFIGURATION_STRUCT \ +typedef struct packed { \ + uvmf_active_passive_t active_passive; \ + uvmf_initiator_responder_t initiator_responder; \ + } fuse_ctrl_out_configuration_s; + + `define fuse_ctrl_out_CONFIGURATION_TO_STRUCT_FUNCTION \ + virtual function fuse_ctrl_out_configuration_s to_struct();\ + fuse_ctrl_out_configuration_struct = \ + {\ + this.active_passive,\ + this.initiator_responder\ + };\ + return ( fuse_ctrl_out_configuration_struct );\ + endfunction + + `define fuse_ctrl_out_CONFIGURATION_FROM_STRUCT_FUNCTION \ + virtual function void from_struct(fuse_ctrl_out_configuration_s fuse_ctrl_out_configuration_struct);\ + {\ + this.active_passive,\ + this.initiator_responder \ + } = fuse_ctrl_out_configuration_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_monitor_struct +// and from_monitor_struct methods of the fuse_ctrl_out_transaction class. +// + `define fuse_ctrl_out_MONITOR_STRUCT typedef struct packed { \ + pwrmgr_pkg::pwr_otp_rsp_t pwr_otp_o ; \ + } fuse_ctrl_out_monitor_s; + + `define fuse_ctrl_out_TO_MONITOR_STRUCT_FUNCTION \ + virtual function fuse_ctrl_out_monitor_s to_monitor_struct();\ + fuse_ctrl_out_monitor_struct = \ + { \ + this.pwr_otp_o \ + };\ + return ( fuse_ctrl_out_monitor_struct);\ + endfunction\ + + `define fuse_ctrl_out_FROM_MONITOR_STRUCT_FUNCTION \ + virtual function void from_monitor_struct(fuse_ctrl_out_monitor_s fuse_ctrl_out_monitor_struct);\ + {\ + this.pwr_otp_o \ + } = fuse_ctrl_out_monitor_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_initiator_struct +// and from_initiator_struct methods of the fuse_ctrl_out_transaction class. +// Also update the comments in the driver BFM. +// + `define fuse_ctrl_out_INITIATOR_STRUCT typedef struct packed { \ + pwrmgr_pkg::pwr_otp_rsp_t pwr_otp_o ; \ + } fuse_ctrl_out_initiator_s; + + `define fuse_ctrl_out_TO_INITIATOR_STRUCT_FUNCTION \ + virtual function fuse_ctrl_out_initiator_s to_initiator_struct();\ + fuse_ctrl_out_initiator_struct = \ + {\ + this.pwr_otp_o \ + };\ + return ( fuse_ctrl_out_initiator_struct);\ + endfunction + + `define fuse_ctrl_out_FROM_INITIATOR_STRUCT_FUNCTION \ + virtual function void from_initiator_struct(fuse_ctrl_out_initiator_s fuse_ctrl_out_initiator_struct);\ + {\ + this.pwr_otp_o \ + } = fuse_ctrl_out_initiator_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_responder_struct +// and from_responder_struct methods of the fuse_ctrl_out_transaction class. +// Also update the comments in the driver BFM. +// + `define fuse_ctrl_out_RESPONDER_STRUCT typedef struct packed { \ + pwrmgr_pkg::pwr_otp_rsp_t pwr_otp_o ; \ + } fuse_ctrl_out_responder_s; + + `define fuse_ctrl_out_TO_RESPONDER_STRUCT_FUNCTION \ + virtual function fuse_ctrl_out_responder_s to_responder_struct();\ + fuse_ctrl_out_responder_struct = \ + {\ + this.pwr_otp_o \ + };\ + return ( fuse_ctrl_out_responder_struct);\ + endfunction + + `define fuse_ctrl_out_FROM_RESPONDER_STRUCT_FUNCTION \ + virtual function void from_responder_struct(fuse_ctrl_out_responder_s fuse_ctrl_out_responder_struct);\ + {\ + this.pwr_otp_o \ + } = fuse_ctrl_out_responder_struct;\ + endfunction +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_monitor.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_monitor.svh new file mode 100644 index 0000000..4cfb4d6 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_monitor.svh @@ -0,0 +1,131 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class receives fuse_ctrl_out transactions observed by the +// fuse_ctrl_out monitor BFM and broadcasts them through the analysis port +// on the agent. It accesses the monitor BFM through the monitor +// task. This UVM component captures transactions +// for viewing in the waveform viewer if the +// enable_transaction_viewing flag is set in the configuration. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_out_monitor #( + int AlertSyncOn = 3, + caliptra_otp_ctrl_pkg::lfsr_seed_t RndConstLfrSeed = caliptra_otp_ctrl_pkg::RndCnstLfsrSeedDefault, + caliptra_otp_ctrl_pkg::lfsr_perm_t RndCnstLfsrPerm = caliptra_otp_ctrl_pkg::RndCnstLfsrPermDefault, + string MemInitFile = "/home/ws/caliptra/anjpar/ws1/chipsalliance/caliptra-rtl/src/fuse_ctrl/data/otp-img.2048.vmem" + ) + extends uvmf_monitor_base #( + .CONFIG_T(fuse_ctrl_out_configuration #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) +), + .BFM_BIND_T(virtual fuse_ctrl_out_monitor_bfm #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) +), + .TRANS_T(fuse_ctrl_out_transaction #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) +)); + + `uvm_component_param_utils( fuse_ctrl_out_monitor #( + AlertSyncOn, + RndConstLfrSeed, + RndCnstLfsrPerm, + MemInitFile + ) +) + +// Structure used to pass data from monitor BFM to monitor class in agent. +// Use to_monitor_struct function to pack transaction variables into structure. +// Use from_monitor_struct function to unpack transaction variables from structure. +`fuse_ctrl_out_MONITOR_STRUCT + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the monitor BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// monitor BFM. This allows the monitor BFM to call the notify_transaction +// function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// *************************************************************************** + virtual task run_phase(uvm_phase phase); + // Start monitor BFM thread and don't call super.run() in order to + // override the default monitor proxy 'pull' behavior with the more + // emulation-friendly BFM 'push' approach using the notify_transaction + // function below + bfm.start_monitoring(); + endtask + +// ************************************************************************** + +// This function is called by the monitor BFM. It receives data observed by the +// monitor BFM. Data is passed using the fuse_ctrl_out_monitor_struct. + virtual function void notify_transaction(input fuse_ctrl_out_monitor_s fuse_ctrl_out_monitor_struct); + + + trans = new("trans"); + trans.from_monitor_struct(fuse_ctrl_out_monitor_struct); + trans.start_time = time_stamp; + trans.end_time = $time; + time_stamp = trans.end_time; + + analyze(trans); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_monitor_bfm.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_monitor_bfm.sv new file mode 100644 index 0000000..fc5a9dd --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_monitor_bfm.sv @@ -0,0 +1,224 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface performs the fuse_ctrl_out signal monitoring. +// It is accessed by the uvm fuse_ctrl_out monitor through a virtual +// interface handle in the fuse_ctrl_out configuration. It monitors the +// signals passed in through the port connection named bus of +// type fuse_ctrl_out_if. +// +// Input signals from the fuse_ctrl_out_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// Interface functions and tasks used by UVM components: +// monitor(inout TRANS_T txn); +// This task receives the transaction, txn, from the +// UVM monitor and then populates variables in txn +// from values observed on bus activity. This task +// blocks until an operation on the fuse_ctrl_out bus is complete. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_out_pkg_hdl::*; +`include "src/fuse_ctrl_out_macros.svh" + + +interface fuse_ctrl_out_monitor_bfm #( + int AlertSyncOn = 3, + caliptra_otp_ctrl_pkg::lfsr_seed_t RndConstLfrSeed = caliptra_otp_ctrl_pkg::RndCnstLfsrSeedDefault, + caliptra_otp_ctrl_pkg::lfsr_perm_t RndCnstLfsrPerm = caliptra_otp_ctrl_pkg::RndCnstLfsrPermDefault, + string MemInitFile = "/home/ws/caliptra/anjpar/ws1/chipsalliance/caliptra-rtl/src/fuse_ctrl/data/otp-img.2048.vmem" + ) + + ( fuse_ctrl_out_if bus ); + // The pragma below and additional ones in-lined further down are for running this BFM on Veloce + // pragma attribute fuse_ctrl_out_monitor_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: AlertSyncOn=%x RndConstLfrSeed=%x RndCnstLfsrPerm=%x MemInitFile=%x ", AlertSyncOn,RndConstLfrSeed,RndCnstLfsrPerm,MemInitFile), + UVM_DEBUG) +end +`endif + + + // Structure used to pass transaction data from monitor BFM to monitor class in agent. +`fuse_ctrl_out_MONITOR_STRUCT + fuse_ctrl_out_monitor_s fuse_ctrl_out_monitor_struct; + + // Structure used to pass configuration data from monitor class to monitor BFM. + `fuse_ctrl_out_CONFIGURATION_STRUCT + + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + tri clk_i_i; + tri rst_ni_i; + tri [$bits(edn_pkg::edn_req_t)-1:0] edn_o_i; + tri intr_otp_operation_done_o_i; + tri intr_otp_error_o_i; + tri [ast_pkg::NumAlerts * $bits(caliptra_prim_alert_pkg::alert_tx_t)-1:0] alert_tx_o_i; + tri [7:0] otp_obs_o_i; + tri [$bits(caliptra_otp_ctrl_pkg::otp_ast_req_t)-1:0] otp_ast_pwr_seq_o_i; + tri [$bits(caliptra_otp_ctrl_part_pkg::otp_broadcast_t)-1:0] otp_broadcast_o_i; + tri [caliptra_otp_ctrl_pkg::OtpTestVectWidth-1:0] cio_test_o_i; + tri [caliptra_otp_ctrl_pkg::OtpTestVectWidth-1:0] cio_test_en_o_i; + assign clk_i_i = bus.clk_i; + assign rst_ni_i = bus.rst_ni; + assign edn_o_i = bus.edn_o; + assign intr_otp_operation_done_o_i = bus.intr_otp_operation_done_o; + assign intr_otp_error_o_i = bus.intr_otp_error_o; + assign alert_tx_o_i = bus.alert_tx_o; + assign otp_obs_o_i = bus.otp_obs_o; + assign otp_ast_pwr_seq_o_i = bus.otp_ast_pwr_seq_o; + assign otp_broadcast_o_i = bus.otp_broadcast_o; + assign cio_test_o_i = bus.cio_test_o; + assign cio_test_en_o_i = bus.cio_test_en_o; + + // Proxy handle to UVM monitor + fuse_ctrl_out_pkg::fuse_ctrl_out_monitor #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) + proxy; + // pragma tbx oneway proxy.notify_transaction + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + task wait_for_reset();// pragma tbx xtf + @(posedge clk_i_i) ; + do_wait_for_reset(); + endtask + + // **************************************************************************** + task do_wait_for_reset(); + // pragma uvmf custom reset_condition begin + wait ( rst_ni_i === 1 ) ; + @(posedge clk_i_i) ; + // pragma uvmf custom reset_condition end + endtask + + //****************************************************************** + + task wait_for_num_clocks(input int unsigned count); // pragma tbx xtf + @(posedge clk_i_i); + + repeat (count-1) @(posedge clk_i_i); + endtask + + //****************************************************************** + event go; + function void start_monitoring();// pragma tbx xtf + -> go; + endfunction + + // **************************************************************************** + initial begin + @go; + forever begin + @(posedge clk_i_i); + do_monitor( fuse_ctrl_out_monitor_struct ); + + + proxy.notify_transaction( fuse_ctrl_out_monitor_struct ); + + end + end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the monitor BFM. It is called by the monitor within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the monitor BFM needs to be aware of the new configuration + // variables. + // + function void configure(fuse_ctrl_out_configuration_s fuse_ctrl_out_configuration_arg); // pragma tbx xtf + initiator_responder = fuse_ctrl_out_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + + + // **************************************************************************** + + task do_monitor(output fuse_ctrl_out_monitor_s fuse_ctrl_out_monitor_struct); + // + // Available struct members: + // // fuse_ctrl_out_monitor_struct.pwr_otp_o + // // + // Reference code; + // How to wait for signal value + // while (control_signal === 1'b1) @(posedge clk_i_i); + // + // How to assign a struct member, named xyz, from a signal. + // All available input signals listed. + // fuse_ctrl_out_monitor_struct.xyz = edn_o_i; // [$bits(edn_pkg::edn_req_t)-1:0] + // fuse_ctrl_out_monitor_struct.xyz = intr_otp_operation_done_o_i; // + // fuse_ctrl_out_monitor_struct.xyz = intr_otp_error_o_i; // + // fuse_ctrl_out_monitor_struct.xyz = alert_tx_o_i; // [ast_pkg::NumAlerts * $bits(caliptra_prim_alert_pkg::alert_tx_t)-1:0] + // fuse_ctrl_out_monitor_struct.xyz = otp_obs_o_i; // [7:0] + // fuse_ctrl_out_monitor_struct.xyz = otp_ast_pwr_seq_o_i; // [$bits(caliptra_otp_ctrl_pkg::otp_ast_req_t)-1:0] + // fuse_ctrl_out_monitor_struct.xyz = otp_broadcast_o_i; // [$bits(caliptra_otp_ctrl_part_pkg::otp_broadcast_t)-1:0] + // fuse_ctrl_out_monitor_struct.xyz = cio_test_o_i; // [caliptra_otp_ctrl_pkg::OtpTestVectWidth-1:0] + // fuse_ctrl_out_monitor_struct.xyz = cio_test_en_o_i; // [caliptra_otp_ctrl_pkg::OtpTestVectWidth-1:0] + // pragma uvmf custom do_monitor begin + // UVMF_CHANGE_ME : Implement protocol monitoring. The commented reference code + // below are examples of how to capture signal values and assign them to + // structure members. All available input signals are listed. The 'while' + // code example shows how to wait for a synchronous flow control signal. This + // task should return when a complete transfer has been observed. Once this task is + // exited with captured values, it is then called again to wait for and observe + // the next transfer. One clock cycle is consumed between calls to do_monitor. + @(posedge clk_i_i); + @(posedge clk_i_i); + @(posedge clk_i_i); + @(posedge clk_i_i); + // pragma uvmf custom do_monitor end + endtask + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_random_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_random_sequence.svh new file mode 100644 index 0000000..0e16eef --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_random_sequence.svh @@ -0,0 +1,91 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This sequences randomizes the fuse_ctrl_out transaction and sends it +// to the UVM driver. +// +// This sequence constructs and randomizes a fuse_ctrl_out_transaction. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_out_random_sequence #( + int AlertSyncOn = 3, + caliptra_otp_ctrl_pkg::lfsr_seed_t RndConstLfrSeed = caliptra_otp_ctrl_pkg::RndCnstLfsrSeedDefault, + caliptra_otp_ctrl_pkg::lfsr_perm_t RndCnstLfsrPerm = caliptra_otp_ctrl_pkg::RndCnstLfsrPermDefault, + string MemInitFile = "/home/ws/caliptra/anjpar/ws1/chipsalliance/caliptra-rtl/src/fuse_ctrl/data/otp-img.2048.vmem" + ) + + extends fuse_ctrl_out_sequence_base #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) +; + + `uvm_object_param_utils( fuse_ctrl_out_random_sequence #( + AlertSyncOn, + RndConstLfrSeed, + RndCnstLfsrPerm, + MemInitFile + ) +) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //***************************************************************** + function new(string name = ""); + super.new(name); + endfunction: new + + // **************************************************************************** + // TASK : body() + // This task is automatically executed when this sequence is started using the + // start(sequencerHandle) task. + // + task body(); + + // Construct the transaction + req=fuse_ctrl_out_transaction#( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) +::type_id::create("req"); + start_item(req); + // Randomize the transaction + if(!req.randomize()) `uvm_fatal("SEQ", "fuse_ctrl_out_random_sequence::body()-fuse_ctrl_out_transaction randomization failed") + // Send the transaction to the fuse_ctrl_out_driver_bfm via the sequencer and fuse_ctrl_out_driver. + finish_item(req); + `uvm_info("SEQ", {"Response:",req.convert2string()},UVM_MEDIUM) + + endtask + +endclass: fuse_ctrl_out_random_sequence + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_responder_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_responder_sequence.svh new file mode 100644 index 0000000..919d45d --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_responder_sequence.svh @@ -0,0 +1,87 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class can be used to provide stimulus when an interface +// has been configured to run in a responder mode. It +// will never finish by default, always going back to the driver +// and driver BFM for the next transaction with which to respond. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_out_responder_sequence #( + int AlertSyncOn = 3, + caliptra_otp_ctrl_pkg::lfsr_seed_t RndConstLfrSeed = caliptra_otp_ctrl_pkg::RndCnstLfsrSeedDefault, + caliptra_otp_ctrl_pkg::lfsr_perm_t RndCnstLfsrPerm = caliptra_otp_ctrl_pkg::RndCnstLfsrPermDefault, + string MemInitFile = "/home/ws/caliptra/anjpar/ws1/chipsalliance/caliptra-rtl/src/fuse_ctrl/data/otp-img.2048.vmem" + ) + + extends fuse_ctrl_out_sequence_base #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) +; + + `uvm_object_param_utils( fuse_ctrl_out_responder_sequence #( + AlertSyncOn, + RndConstLfrSeed, + RndCnstLfsrPerm, + MemInitFile + ) +) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "fuse_ctrl_out_responder_sequence"); + super.new(name); + endfunction + + task body(); + req=fuse_ctrl_out_transaction#( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) +::type_id::create("req"); + forever begin + start_item(req); + finish_item(req); + // pragma uvmf custom body begin + // UVMF_CHANGE_ME : Do something here with the resulting req item. The + // finish_item() call above will block until the req transaction is ready + // to be handled by the responder sequence. + // If this was an item that required a response, the expectation is + // that the response should be populated within this transaction now. + `uvm_info("SEQ",$sformatf("Processed txn: %s",req.convert2string()),UVM_HIGH) + // pragma uvmf custom body end + end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_sequence_base.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_sequence_base.svh new file mode 100644 index 0000000..f7c5c09 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_sequence_base.svh @@ -0,0 +1,146 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the class used as the base class for all sequences +// for this interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_out_sequence_base #( + int AlertSyncOn = 3, + caliptra_otp_ctrl_pkg::lfsr_seed_t RndConstLfrSeed = caliptra_otp_ctrl_pkg::RndCnstLfsrSeedDefault, + caliptra_otp_ctrl_pkg::lfsr_perm_t RndCnstLfsrPerm = caliptra_otp_ctrl_pkg::RndCnstLfsrPermDefault, + string MemInitFile = "/home/ws/caliptra/anjpar/ws1/chipsalliance/caliptra-rtl/src/fuse_ctrl/data/otp-img.2048.vmem" + ) + extends uvmf_sequence_base #( + .REQ(fuse_ctrl_out_transaction #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) +), + .RSP(fuse_ctrl_out_transaction #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) +)); + + `uvm_object_param_utils( fuse_ctrl_out_sequence_base #( + AlertSyncOn, + RndConstLfrSeed, + RndCnstLfsrPerm, + MemInitFile + ) +) + + // variables + typedef fuse_ctrl_out_transaction #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) + fuse_ctrl_out_transaction_req_t; + fuse_ctrl_out_transaction_req_t req; + typedef fuse_ctrl_out_transaction #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) + fuse_ctrl_out_transaction_rsp_t; + fuse_ctrl_out_transaction_rsp_t rsp; + + // Event for identifying when a response was received from the sequencer + event new_rsp; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // TASK : get_responses() + // This task recursively gets sequence item responses from the sequencer. + // + virtual task get_responses(); + fork + begin + // Block until new rsp available + get_response(rsp); + // New rsp received. Indicate to sequence using event. + ->new_rsp; + // Display the received response transaction + `uvm_info("SEQ", {"New response transaction:",rsp.convert2string()}, UVM_MEDIUM) + end + join_none + endtask + + // **************************************************************************** + // TASK : pre_body() + // This task is called automatically when start is called with call_pre_post set to 1 (default). + // By calling get_responses() within pre_body() any derived sequences are automatically + // processing response transactions. Only un-comment this call to get_responses() if you + // have configured the interface driver to utilize the response transaction path by setting + // the configuration variable "return_transaction_response" to 1. Otherwise it is possible + // to impact runtime performance and memory utilization. + // + virtual task pre_body(); + // pragma uvmf custom pre_body begin +// get_responses(); + // pragma uvmf custom pre_body end + endtask + + // **************************************************************************** + // TASK : body() + // This task is called automatically when start is called. This sequence sends + // a req sequence item to the sequencer identified as an argument in the call + // to start. + // + virtual task body(); + // pragma uvmf custom body begin + start_item(req); + finish_item(req); + // pragma uvmf custom body end + endtask + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name =""); + super.new( name ); + // pragma uvmf custom new begin + req = fuse_ctrl_out_transaction_req_t::type_id::create("req"); + rsp = fuse_ctrl_out_transaction_rsp_t::type_id::create("rsp"); + // pragma uvmf custom new end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_transaction.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_transaction.svh new file mode 100644 index 0000000..2c5fdf7 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_transaction.svh @@ -0,0 +1,223 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class defines the variables required for an fuse_ctrl_out +// transaction. Class variables to be displayed in waveform transaction +// viewing are added to the transaction viewing stream in the add_to_wave +// function. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_out_transaction #( + int AlertSyncOn = 3, + caliptra_otp_ctrl_pkg::lfsr_seed_t RndConstLfrSeed = caliptra_otp_ctrl_pkg::RndCnstLfsrSeedDefault, + caliptra_otp_ctrl_pkg::lfsr_perm_t RndCnstLfsrPerm = caliptra_otp_ctrl_pkg::RndCnstLfsrPermDefault, + string MemInitFile = "/home/ws/caliptra/anjpar/ws1/chipsalliance/caliptra-rtl/src/fuse_ctrl/data/otp-img.2048.vmem" + ) + extends uvmf_transaction_base; + + `uvm_object_param_utils( fuse_ctrl_out_transaction #( + AlertSyncOn, + RndConstLfrSeed, + RndCnstLfsrPerm, + MemInitFile + ) +) + + pwrmgr_pkg::pwr_otp_rsp_t pwr_otp_o ; + + //Constraints for the transaction variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //******************************************************************* + //******************************************************************* + // Macros that define structs and associated functions are + // located in fuse_ctrl_out_macros.svh + + //******************************************************************* + // Monitor macro used by fuse_ctrl_out_monitor and fuse_ctrl_out_monitor_bfm + // This struct is defined in fuse_ctrl_out_macros.svh + `fuse_ctrl_out_MONITOR_STRUCT + fuse_ctrl_out_monitor_s fuse_ctrl_out_monitor_struct; + //******************************************************************* + // FUNCTION: to_monitor_struct() + // This function packs transaction variables into a fuse_ctrl_out_monitor_s + // structure. The function returns the handle to the fuse_ctrl_out_monitor_struct. + // This function is defined in fuse_ctrl_out_macros.svh + `fuse_ctrl_out_TO_MONITOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_monitor_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_out_macros.svh + `fuse_ctrl_out_FROM_MONITOR_STRUCT_FUNCTION + + //******************************************************************* + // Initiator macro used by fuse_ctrl_out_driver and fuse_ctrl_out_driver_bfm + // to communicate initiator driven data to fuse_ctrl_out_driver_bfm. + // This struct is defined in fuse_ctrl_out_macros.svh + `fuse_ctrl_out_INITIATOR_STRUCT + fuse_ctrl_out_initiator_s fuse_ctrl_out_initiator_struct; + //******************************************************************* + // FUNCTION: to_initiator_struct() + // This function packs transaction variables into a fuse_ctrl_out_initiator_s + // structure. The function returns the handle to the fuse_ctrl_out_initiator_struct. + // This function is defined in fuse_ctrl_out_macros.svh + `fuse_ctrl_out_TO_INITIATOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_initiator_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_out_macros.svh + `fuse_ctrl_out_FROM_INITIATOR_STRUCT_FUNCTION + + //******************************************************************* + // Responder macro used by fuse_ctrl_out_driver and fuse_ctrl_out_driver_bfm + // to communicate Responder driven data to fuse_ctrl_out_driver_bfm. + // This struct is defined in fuse_ctrl_out_macros.svh + `fuse_ctrl_out_RESPONDER_STRUCT + fuse_ctrl_out_responder_s fuse_ctrl_out_responder_struct; + //******************************************************************* + // FUNCTION: to_responder_struct() + // This function packs transaction variables into a fuse_ctrl_out_responder_s + // structure. The function returns the handle to the fuse_ctrl_out_responder_struct. + // This function is defined in fuse_ctrl_out_macros.svh + `fuse_ctrl_out_TO_RESPONDER_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_responder_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_out_macros.svh + `fuse_ctrl_out_FROM_RESPONDER_STRUCT_FUNCTION + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + endfunction + + // **************************************************************************** + // FUNCTION: convert2string() + // This function converts all variables in this class to a single string for + // logfile reporting. + // + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + // UVMF_CHANGE_ME : Customize format if desired. + return $sformatf("otp_lc_data_o:0x%x pwr_otp_o:0x%x ",otp_lc_data_o,pwr_otp_o); + // pragma uvmf custom convert2string end + endfunction + + //******************************************************************* + // FUNCTION: do_print() + // This function is automatically called when the .print() function + // is called on this class. + // + virtual function void do_print(uvm_printer printer); + // pragma uvmf custom do_print begin + // UVMF_CHANGE_ME : Current contents of do_print allows for the use of UVM 1.1d, 1.2 or P1800.2. + // Update based on your own printing preference according to your preferred UVM version + $display(convert2string()); + // pragma uvmf custom do_print end + endfunction + + //******************************************************************* + // FUNCTION: do_compare() + // This function is automatically called when the .compare() function + // is called on this class. + // + virtual function bit do_compare (uvm_object rhs, uvm_comparer comparer); + fuse_ctrl_out_transaction #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) + RHS; + if (!$cast(RHS,rhs)) return 0; + // pragma uvmf custom do_compare begin + // UVMF_CHANGE_ME : Eliminate comparison of variables not to be used for compare + return (super.do_compare(rhs,comparer) + &&(this.otp_lc_data_o == RHS.otp_lc_data_o) + &&(this.pwr_otp_o == RHS.pwr_otp_o) + ); + // pragma uvmf custom do_compare end + endfunction + + //******************************************************************* + // FUNCTION: do_copy() + // This function is automatically called when the .copy() function + // is called on this class. + // + virtual function void do_copy (uvm_object rhs); + fuse_ctrl_out_transaction #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) + RHS; + assert($cast(RHS,rhs)); + // pragma uvmf custom do_copy begin + super.do_copy(rhs); + this.otp_lc_data_o = RHS.otp_lc_data_o; + this.pwr_otp_o = RHS.pwr_otp_o; + // pragma uvmf custom do_copy end + endfunction + + // **************************************************************************** + // FUNCTION: add_to_wave() + // This function is used to display variables in this class in the waveform + // viewer. The start_time and end_time variables must be set before this + // function is called. If the start_time and end_time variables are not set + // the transaction will be hidden at 0ns on the waveform display. + // + virtual function void add_to_wave(int transaction_viewing_stream_h); + `ifdef QUESTA + if (transaction_view_h == 0) begin + transaction_view_h = $begin_transaction(transaction_viewing_stream_h,"fuse_ctrl_out_transaction",start_time); + end + super.add_to_wave(transaction_view_h); + // pragma uvmf custom add_to_wave begin + // UVMF_CHANGE_ME : Color can be applied to transaction entries based on content, example below + // case() + // 1 : $add_color(transaction_view_h,"red"); + // default : $add_color(transaction_view_h,"grey"); + // endcase + // UVMF_CHANGE_ME : Eliminate transaction variables not wanted in transaction viewing in the waveform viewer + $add_attribute(transaction_view_h,otp_lc_data_o,"otp_lc_data_o"); + $add_attribute(transaction_view_h,pwr_otp_o,"pwr_otp_o"); + // pragma uvmf custom add_to_wave end + $end_transaction(transaction_view_h,end_time); + $free_transaction(transaction_view_h); + `endif // QUESTA + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_transaction_coverage.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_transaction_coverage.svh new file mode 100644 index 0000000..9450c04 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_transaction_coverage.svh @@ -0,0 +1,103 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class records fuse_ctrl_out transaction information using +// a covergroup named fuse_ctrl_out_transaction_cg. An instance of this +// coverage component is instantiated in the uvmf_parameterized_agent +// if the has_coverage flag is set. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_out_transaction_coverage #( + int AlertSyncOn = 3, + caliptra_otp_ctrl_pkg::lfsr_seed_t RndConstLfrSeed = caliptra_otp_ctrl_pkg::RndCnstLfsrSeedDefault, + caliptra_otp_ctrl_pkg::lfsr_perm_t RndCnstLfsrPerm = caliptra_otp_ctrl_pkg::RndCnstLfsrPermDefault, + string MemInitFile = "/home/ws/caliptra/anjpar/ws1/chipsalliance/caliptra-rtl/src/fuse_ctrl/data/otp-img.2048.vmem" + ) + extends uvm_subscriber #(.T(fuse_ctrl_out_transaction #( + .AlertSyncOn(AlertSyncOn), + .RndConstLfrSeed(RndConstLfrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm), + .MemInitFile(MemInitFile) + ) +)); + + `uvm_component_param_utils( fuse_ctrl_out_transaction_coverage #( + AlertSyncOn, + RndConstLfrSeed, + RndCnstLfsrPerm, + MemInitFile + ) +) + + T coverage_trans; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + covergroup fuse_ctrl_out_transaction_cg; + // pragma uvmf custom covergroup begin + // UVMF_CHANGE_ME : Add coverage bins, crosses, exclusions, etc. according to coverage needs. + option.auto_bin_max=1024; + option.per_instance=1; + otp_lc_data_o: coverpoint coverage_trans.otp_lc_data_o; + pwr_otp_o: coverpoint coverage_trans.pwr_otp_o; + // pragma uvmf custom covergroup end + endgroup + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new(string name="", uvm_component parent=null); + super.new(name,parent); + fuse_ctrl_out_transaction_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that transaction variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + endfunction + + // **************************************************************************** + // FUNCTION : build_phase() + // This function is the standard UVM build_phase. + // + function void build_phase(uvm_phase phase); + fuse_ctrl_out_transaction_cg.set_inst_name($sformatf("fuse_ctrl_out_transaction_cg_%s",get_full_name())); + endfunction + + // **************************************************************************** + // FUNCTION: write (T t) + // This function is automatically executed when a transaction arrives on the + // analysis_export. It copies values from the variables in the transaction + // to local variables used to collect functional coverage. + // + virtual function void write (T t); + `uvm_info("COV","Received transaction",UVM_HIGH); + coverage_trans = t; + fuse_ctrl_out_transaction_cg.sample(); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_typedefs.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_typedefs.svh new file mode 100644 index 0000000..f2a7bdb --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_typedefs.svh @@ -0,0 +1,34 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the host server when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_typedefs_hdl.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_typedefs_hdl.svh new file mode 100644 index 0000000..0d58518 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/src/fuse_ctrl_out_typedefs_hdl.svh @@ -0,0 +1,35 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the emulator when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/yaml/fuse_ctrl_out_interface.yaml b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/yaml/fuse_ctrl_out_interface.yaml new file mode 100644 index 0000000..692854f --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_out_pkg/yaml/fuse_ctrl_out_interface.yaml @@ -0,0 +1,72 @@ +uvmf: + interfaces: + fuse_ctrl_out: + clock: clk_i + config_constraints: [] + config_vars: [] + existing_library_component: 'True' + gen_inbound_streaming_driver: 'False' + hdl_pkg_parameters: [] + hdl_typedefs: [] + hvl_pkg_parameters: [] + hvl_typedefs: [] + parameters: + - name: AlertSyncOn + type: int + value: '3' + - name: RndConstLfrSeed + type: caliptra_otp_ctrl_pkg::lfsr_seed_t + value: caliptra_otp_ctrl_pkg::RndCnstLfsrSeedDefault + - name: RndCnstLfsrPerm + type: caliptra_otp_ctrl_pkg::lfsr_perm_t + value: caliptra_otp_ctrl_pkg::RndCnstLfsrPermDefault + - name: MemInitFile + type: string + ports: + - dir: input + name: edn_o + reset_value: '''bz' + width: '[''$bits(edn_pkg::edn_req_t)'']' + - dir: input + name: intr_otp_operation_done_o + reset_value: '''bz' + width: '1' + - dir: input + name: intr_otp_error_o + reset_value: '''bz' + width: '1' + - dir: input + name: alert_tx_o + reset_value: '''bz' + width: '[''ast_pkg::NumAlerts * $bits(caliptra_prim_alert_pkg::alert_tx_t)'']' + - dir: input + name: otp_obs_o + reset_value: '''bz' + width: '8' + - dir: input + name: otp_ast_pwr_seq_o + reset_value: '''bz' + width: '[''$bits(caliptra_otp_ctrl_pkg::otp_ast_req_t)'']' + - dir: input + name: otp_broadcast_o + reset_value: '''bz' + width: '[''$bits(caliptra_otp_ctrl_part_pkg::otp_broadcast_t)'']' + - dir: input + name: cio_test_o + reset_value: '''bz' + width: '[''caliptra_otp_ctrl_pkg::OtpTestVectWidth'']' + - dir: input + name: cio_test_en_o + reset_value: '''bz' + width: '[''caliptra_otp_ctrl_pkg::OtpTestVectWidth'']' + reset: rst_ni + reset_assertion_level: 'False' + transaction_constraints: [] + transaction_vars: + - comment: '' + iscompare: 'True' + isrand: 'False' + name: pwr_otp_o + type: pwrmgr_pkg::pwr_otp_rsp_t + unpacked_dimension: '' + use_dpi_link: 'False' diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/.project b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/.project new file mode 100644 index 0000000..d0dba88 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/.project @@ -0,0 +1,30 @@ + + + fuse_ctrl_prim_axi_read_in_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/.svproject b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/.svproject new file mode 100644 index 0000000..7f5e878 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/Makefile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/Makefile new file mode 100644 index 0000000..ff74765 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/Makefile @@ -0,0 +1,66 @@ +# fuse_ctrl_prim_axi_read_in interface packages source +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +fuse_ctrl_prim_axi_read_in_PKG = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_read_in_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_filelist_hvl.f + +fuse_ctrl_prim_axi_read_in_PKG_HDL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_read_in_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_filelist_hdl.f + +fuse_ctrl_prim_axi_read_in_PKG_XRTL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_read_in_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_filelist_xrtl.f + +COMP_fuse_ctrl_prim_axi_read_in_PKG_TGT_0 = q_comp_fuse_ctrl_prim_axi_read_in_pkg +COMP_fuse_ctrl_prim_axi_read_in_PKG_TGT_1 = v_comp_fuse_ctrl_prim_axi_read_in_pkg +COMP_fuse_ctrl_prim_axi_read_in_PKG_TGT = $(COMP_fuse_ctrl_prim_axi_read_in_PKG_TGT_$(USE_VELOCE)) + +comp_fuse_ctrl_prim_axi_read_in_pkg: $(COMP_fuse_ctrl_prim_axi_read_in_PKG_TGT) + +q_comp_fuse_ctrl_prim_axi_read_in_pkg: + $(HDL_COMP_CMD) $(fuse_ctrl_prim_axi_read_in_PKG_HDL) + $(HVL_COMP_CMD) $(fuse_ctrl_prim_axi_read_in_PKG) + $(HDL_COMP_CMD) $(fuse_ctrl_prim_axi_read_in_PKG_XRTL) + +v_comp_fuse_ctrl_prim_axi_read_in_pkg: + $(HVL_COMP_CMD) $(fuse_ctrl_prim_axi_read_in_PKG_HDL) + $(HVL_COMP_CMD) $(fuse_ctrl_prim_axi_read_in_PKG) + $(VELANALYZE_CMD) $(fuse_ctrl_prim_axi_read_in_PKG_HDL) + $(VELANALYZE_HVL_CMD) $(fuse_ctrl_prim_axi_read_in_PKG) + $(HDL_COMP_CMD) $(fuse_ctrl_prim_axi_read_in_PKG_XRTL) + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export fuse_ctrl_prim_axi_read_in_IF_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/dpi + +C_FILE_COMPILE_LIST_fuse_ctrl_prim_axi_read_in_pkg = \ + +O_FILE_COMPILE_LIST_fuse_ctrl_prim_axi_read_in_pkg = $(notdir $(C_FILE_COMPILE_LIST_fuse_ctrl_prim_axi_read_in_pkg:.c=.o)) + +GCC_COMP_ARGS_fuse_ctrl_prim_axi_read_in_pkg += -I$(fuse_ctrl_prim_axi_read_in_IF_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_fuse_ctrl_prim_axi_read_in_pkg += $(fuse_ctrl_prim_axi_read_in_IF_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_fuse_ctrl_prim_axi_read_in_pkg += \ + \ + -o .so + +comp_fuse_ctrl_prim_axi_read_in_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Interface C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_fuse_ctrl_prim_axi_read_in_pkg) $(C_FILE_COMPILE_LIST_fuse_ctrl_prim_axi_read_in_pkg) + @echo "--------------------------------" + @echo "Linking Interface C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_fuse_ctrl_prim_axi_read_in_pkg) $(O_FILE_COMPILE_LIST_fuse_ctrl_prim_axi_read_in_pkg) + @echo "--------------------------------" + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/compile.do b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/compile.do new file mode 100644 index 0000000..d5afe8a --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/compile.do @@ -0,0 +1,14 @@ +# Tcl do file for compile of fuse_ctrl_prim_axi_read_in interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_read_in_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_filelist_hdl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_read_in_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_filelist_hvl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_read_in_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_filelist_xrtl.f \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in.compile new file mode 100644 index 0000000..73650e4 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in.compile @@ -0,0 +1,3 @@ +needs: + - fuse_ctrl_prim_axi_read_in_hvl.compile + - fuse_ctrl_prim_axi_read_in_hdl.compile diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_bfm.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_bfm.vinfo new file mode 100644 index 0000000..8ed6f0d --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_bfm.vinfo @@ -0,0 +1,6 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use fuse_ctrl_prim_axi_read_in_pkg_hdl.vinfo ++incdir+@vinfodir +src/fuse_ctrl_prim_axi_read_in_if.sv +src/fuse_ctrl_prim_axi_read_in_driver_bfm.sv +src/fuse_ctrl_prim_axi_read_in_monitor_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_common.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_common.compile new file mode 100644 index 0000000..ca43b4d --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_common.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +incdir: + - . + - ${uvm_path}/src +src: + - fuse_ctrl_prim_axi_read_in_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_filelist_hdl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_filelist_hdl.f new file mode 100644 index 0000000..f0b99a3 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_filelist_hdl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_filelist_hvl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_filelist_hvl.f new file mode 100644 index 0000000..8dcf197 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_filelist_hvl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_pkg.sv \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_filelist_xrtl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_filelist_xrtl.f new file mode 100644 index 0000000..46c2aab --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_filelist_xrtl.f @@ -0,0 +1,3 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_if.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_monitor_bfm.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_driver_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_hdl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_hdl.compile new file mode 100644 index 0000000..31d8fb1 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_hdl.compile @@ -0,0 +1,9 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ./fuse_ctrl_prim_axi_read_in_common.compile +incdir: + - . +src: + - src/fuse_ctrl_prim_axi_read_in_if.sv + - src/fuse_ctrl_prim_axi_read_in_monitor_bfm.sv + - src/fuse_ctrl_prim_axi_read_in_driver_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_hvl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_hvl.compile new file mode 100644 index 0000000..7c7cc34 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_hvl.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ./fuse_ctrl_prim_axi_read_in_common.compile +incdir: + - . +src: + - fuse_ctrl_prim_axi_read_in_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_pkg.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_pkg.sv new file mode 100644 index 0000000..2e29485 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_pkg.sv @@ -0,0 +1,91 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - + +// - +// - +// - + +// - +// - +// - + +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_prim_axi_read_in_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg_hdl::*; + import uvmf_base_pkg::*; + import fuse_ctrl_prim_axi_read_in_pkg_hdl::*; + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + `include "src/fuse_ctrl_prim_axi_read_in_macros.svh" + + export fuse_ctrl_prim_axi_read_in_pkg_hdl::*; + + + + // Parameters defined as HVL parameters + + `include "src/fuse_ctrl_prim_axi_read_in_typedefs.svh" + `include "src/fuse_ctrl_prim_axi_read_in_transaction.svh" + + `include "src/fuse_ctrl_prim_axi_read_in_configuration.svh" + `include "src/fuse_ctrl_prim_axi_read_in_driver.svh" + `include "src/fuse_ctrl_prim_axi_read_in_monitor.svh" + + `include "src/fuse_ctrl_prim_axi_read_in_transaction_coverage.svh" + `include "src/fuse_ctrl_prim_axi_read_in_sequence_base.svh" + `include "src/fuse_ctrl_prim_axi_read_in_random_sequence.svh" + + `include "src/fuse_ctrl_prim_axi_read_in_responder_sequence.svh" + `include "src/fuse_ctrl_prim_axi_read_in2reg_adapter.svh" + + `include "src/fuse_ctrl_prim_axi_read_in_agent.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new interface sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the interface package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_pkg.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_pkg.vinfo new file mode 100644 index 0000000..7f62c30 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_pkg.vinfo @@ -0,0 +1,4 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use fuse_ctrl_prim_axi_read_in_pkg_hdl.vinfo ++incdir+@vinfodir +fuse_ctrl_prim_axi_read_in_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_pkg_hdl.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_pkg_hdl.sv new file mode 100644 index 0000000..f771faa --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_pkg_hdl.sv @@ -0,0 +1,52 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that needs to be compiled and synthesized +// for running on Veloce. +// +// CONTAINS: +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_prim_axi_read_in_pkg_hdl; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HDL parameters + + `include "src/fuse_ctrl_prim_axi_read_in_typedefs_hdl.svh" + `include "src/fuse_ctrl_prim_axi_read_in_macros.svh" + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_pkg_hdl.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_pkg_hdl.vinfo new file mode 100644 index 0000000..eb67953 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_pkg_hdl.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +fuse_ctrl_prim_axi_read_in_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_pkg_sve.F b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_pkg_sve.F new file mode 100644 index 0000000..ce8af16 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_pkg_sve.F @@ -0,0 +1,10 @@ +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + ++incdir+. +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_filelist_hdl.f +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/fuse_ctrl_prim_axi_read_in_filelist_hvl.f diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in2reg_adapter.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in2reg_adapter.svh new file mode 100644 index 0000000..2c9b99e --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in2reg_adapter.svh @@ -0,0 +1,142 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the UVM register adapter for the fuse_ctrl_prim_axi_read_in interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_read_in2reg_adapter #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvm_reg_adapter; + + `uvm_object_param_utils( fuse_ctrl_prim_axi_read_in2reg_adapter #( + AW, + DW, + IW, + UW + ) +) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //-------------------------------------------------------------------- + // new + //-------------------------------------------------------------------- + function new (string name = "fuse_ctrl_prim_axi_read_in2reg_adapter" ); + super.new(name); + // pragma uvmf custom new begin + // UVMF_CHANGE_ME : Configure the adapter regarding byte enables and provides response. + + // Does the protocol the Agent is modeling support byte enables? + // 0 = NO + // 1 = YES + supports_byte_enable = 0; + + // Does the Agent's Driver provide separate response sequence items? + // i.e. Does the driver call seq_item_port.put() + // and do the sequences call get_response()? + // 0 = NO + // 1 = YES + provides_responses = 0; + // pragma uvmf custom new end + + endfunction: new + + //-------------------------------------------------------------------- + // reg2bus + //-------------------------------------------------------------------- + virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw); + + fuse_ctrl_prim_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + trans_h = fuse_ctrl_prim_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +::type_id::create("trans_h"); + + // pragma uvmf custom reg2bus begin + // UVMF_CHANGE_ME : Fill in the reg2bus adapter mapping registe fields to protocol fields. + + //Adapt the following for your sequence item type + // trans_h.op = (rw.kind == UVM_READ) ? WB_READ : WB_WRITE; + //Copy over address + // trans_h.addr = rw.addr; + //Copy over write data + // trans_h.data = rw.data; + + // pragma uvmf custom reg2bus end + + // Return the adapted transaction + return trans_h; + + endfunction: reg2bus + + //-------------------------------------------------------------------- + // bus2reg + //-------------------------------------------------------------------- + virtual function void bus2reg(uvm_sequence_item bus_item, + ref uvm_reg_bus_op rw); + fuse_ctrl_prim_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + trans_h; + if (!$cast(trans_h, bus_item)) begin + `uvm_fatal("ADAPT","Provided bus_item is not of the correct type") + return; + end + // pragma uvmf custom bus2reg begin + // UVMF_CHANGE_ME : Fill in the bus2reg adapter mapping protocol fields to register fields. + //Adapt the following for your sequence item type + //Copy over instruction type + // rw.kind = (trans_h.op == WB_WRITE) ? UVM_WRITE : UVM_READ; + //Copy over address + // rw.addr = trans_h.addr; + //Copy over read data + // rw.data = trans_h.data; + //Check for errors on the bus and return UVM_NOT_OK if there is an error + // rw.status = UVM_IS_OK; + // pragma uvmf custom bus2reg end + + endfunction: bus2reg + +endclass : fuse_ctrl_prim_axi_read_in2reg_adapter + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_agent.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_agent.svh new file mode 100644 index 0000000..b2ff8a6 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_agent.svh @@ -0,0 +1,109 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: Protocol specific agent class definition +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_read_in_agent #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvmf_parameterized_agent #( + .CONFIG_T(fuse_ctrl_prim_axi_read_in_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .DRIVER_T(fuse_ctrl_prim_axi_read_in_driver #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .MONITOR_T(fuse_ctrl_prim_axi_read_in_monitor #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .COVERAGE_T(fuse_ctrl_prim_axi_read_in_transaction_coverage #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .TRANS_T(fuse_ctrl_prim_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +) + ); + + `uvm_component_param_utils( fuse_ctrl_prim_axi_read_in_agent #( + AW, + DW, + IW, + UW + ) +) + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** + // FUNCTION: build_phase + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + if (configuration.active_passive == ACTIVE) begin + // Place sequencer handle into configuration object + // so that it may be retrieved from configuration + // rather than using uvm_config_db + configuration.sequencer = this.sequencer; + end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_configuration.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_configuration.svh new file mode 100644 index 0000000..7692603 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_configuration.svh @@ -0,0 +1,241 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class contains all variables and functions used +// to configure the fuse_ctrl_prim_axi_read_in agent and its bfm's. It gets the +// bfm's from the uvm_config_db for use by the agent. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_read_in_configuration #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvmf_parameterized_agent_configuration_base #( + .DRIVER_BFM_BIND_T(virtual fuse_ctrl_prim_axi_read_in_driver_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .MONITOR_BFM_BIND_T( virtual fuse_ctrl_prim_axi_read_in_monitor_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +)); + + `uvm_object_param_utils( fuse_ctrl_prim_axi_read_in_configuration #( + AW, + DW, + IW, + UW + ) +) + + + // Sequencer handle populated by agent + uvm_sequencer #(fuse_ctrl_prim_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + ) sequencer; + + //Constraints for the configuration variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + covergroup fuse_ctrl_prim_axi_read_in_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + // pragma uvmf custom covergroup end + endgroup + + //******************************************************************* + //******************************************************************* + // Structure used to pass configuration variables to monitor and driver BFM's. + // Use to_struct function to pack variables into structure. + // Use from_struct function to unpack variables from structure. + // This structure is defined in fuse_ctrl_prim_axi_read_in_macros.svh + `fuse_ctrl_prim_axi_read_in_CONFIGURATION_STRUCT + fuse_ctrl_prim_axi_read_in_configuration_s fuse_ctrl_prim_axi_read_in_configuration_struct; + //******************************************************************* + // FUNCTION: to_struct() + // This function packs variables into a fuse_ctrl_prim_axi_read_in_configuration_s + // structure. The function returns the handle to the fuse_ctrl_prim_axi_read_in_configuration_struct. + // This function is defined in fuse_ctrl_prim_axi_read_in_macros.svh + `fuse_ctrl_prim_axi_read_in_CONFIGURATION_TO_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_struct() + // This function unpacks the struct provided as an argument into + // variables of this class. + // This function is defined in fuse_ctrl_prim_axi_read_in_macros.svh + `fuse_ctrl_prim_axi_read_in_CONFIGURATION_FROM_STRUCT_FUNCTION + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + // Construct the covergroup for this configuration class + fuse_ctrl_prim_axi_read_in_configuration_cg = new; + endfunction + + // **************************************************************************** + // FUNCTION: post_randomize() + // This function is automatically called after the randomize() function + // is executed. + // + function void post_randomize(); + super.post_randomize(); + fuse_ctrl_prim_axi_read_in_configuration_cg.sample(); + endfunction + + // **************************************************************************** + // FUNCTION: initialize + // This function causes the configuration to retrieve + // its virtual interface handle from the uvm_config_db. + // This function also makes itself available to its + // agent through the uvm_config_db. + // + // ARGUMENTS: + // uvmf_active_passive_t activity: + // This argument identifies the simulation level + // as either BLOCK, CHIP, SIMULATION, etc. + // + // AGENT_PATH: + // This argument identifies the path to this + // configurations agent. This configuration + // makes itself available to the agent specified + // by agent_path by placing itself into the + // uvm_config_db. + // + // INTERFACE_NAME: + // This argument identifies the string name of + // this configurations BFM's. This string + // name is used to retrieve the driver and + // monitor BFM from the uvm_config_db. + // + virtual function void initialize(uvmf_active_passive_t activity, + string agent_path, + string interface_name); + + super.initialize( activity, agent_path, interface_name); + // The covergroup is given the same name as the interface + fuse_ctrl_prim_axi_read_in_configuration_cg.set_inst_name(interface_name); + + // This configuration places itself into the uvm_config_db for the agent, identified by the agent_path variable, to retrieve. + uvm_config_db #( fuse_ctrl_prim_axi_read_in_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + + )::set( null ,agent_path,UVMF_AGENT_CONFIG, this ); + + // This configuration also places itself in the config db using the same identifier used by the interface. This allows users to access + // configuration variables and the interface through the bfm api class rather than directly accessing the BFM. This is useful for + // accessingthe BFM when using Veloce + uvm_config_db #( fuse_ctrl_prim_axi_read_in_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + + )::set( null ,UVMF_CONFIGURATIONS, interface_name, this ); + + fuse_ctrl_prim_axi_read_in_configuration_cg.set_inst_name($sformatf("fuse_ctrl_prim_axi_read_in_configuration_cg_%s",get_full_name())); + +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. + `uvm_info("CFG", + $psprintf("The agent at '%s' is using interface named %s has the following parameters: AW=%x DW=%x IW=%x UW=%x ", agent_path, interface_name, AW ,DW ,IW ,UW ), + UVM_DEBUG) + + // pragma uvmf custom initialize begin + // This controls whether or not the agent returns a transaction handle in the driver when calling + // item_done() back into the sequencer or not. If set to 1, a transaction is sent back which means + // the sequence on the other end must use the get_response() part of the driver/sequence API. If + // this doesn't occur, there will eventually be response_queue overflow errors during the test. + return_transaction_response = 1'b0; + + // pragma uvmf custom initialize end + + endfunction + + // **************************************************************************** + // TASK: wait_for_reset + // *[Required]* Blocks until reset is released. The wait_for_reset operation is performed + // by a task in the monitor bfm. + virtual task wait_for_reset(); + monitor_bfm.wait_for_reset(); + endtask + + // **************************************************************************** + // TASK: wait_for_num_clocks + // *[Required]* Blocks until specified number of clocks have elapsed. The wait_for_num_clocks + // operation is performed by a task in the monitor bfm. + virtual task wait_for_num_clocks(int clocks); + monitor_bfm.wait_for_num_clocks(clocks); + endtask + + // **************************************************************************** + // FUNCTION : convert2string() + // This function is used to convert variables in this class into a string for log messaging. + // + virtual function string convert2string (); + // pragma uvmf custom convert2string begin + return $sformatf(""); + // pragma uvmf custom convert2string end + endfunction + + // **************************************************************************** + // FUNCTION: get_sequencer + function uvm_sequencer #(fuse_ctrl_prim_axi_read_in_transaction#( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +) get_sequencer(); + return sequencer; + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_driver.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_driver.svh new file mode 100644 index 0000000..47ced3b --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_driver.svh @@ -0,0 +1,141 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class passes transactions between the sequencer +// and the BFM driver interface. It accesses the driver BFM +// through the bfm handle. This driver +// passes transactions to the driver BFM through the access +// task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_read_in_driver #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvmf_driver_base #( + .CONFIG_T(fuse_ctrl_prim_axi_read_in_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + ), + .BFM_BIND_T(virtual fuse_ctrl_prim_axi_read_in_driver_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + ), + .REQ(fuse_ctrl_prim_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + ), + .RSP(fuse_ctrl_prim_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + )); + + `uvm_component_param_utils( fuse_ctrl_prim_axi_read_in_driver #( + AW, + DW, + IW, + UW + ) +) +//******************************************************************* +// Macros that define structs located in fuse_ctrl_prim_axi_read_in_macros.svh +//******************************************************************* +// Initiator macro used by fuse_ctrl_prim_axi_read_in_driver and fuse_ctrl_prim_axi_read_in_driver_bfm +// to communicate initiator driven data to fuse_ctrl_prim_axi_read_in_driver_bfm. +`fuse_ctrl_prim_axi_read_in_INITIATOR_STRUCT + fuse_ctrl_prim_axi_read_in_initiator_s fuse_ctrl_prim_axi_read_in_initiator_struct; +//******************************************************************* +// Responder macro used by fuse_ctrl_prim_axi_read_in_driver and fuse_ctrl_prim_axi_read_in_driver_bfm +// to communicate Responder driven data to fuse_ctrl_prim_axi_read_in_driver_bfm. +`fuse_ctrl_prim_axi_read_in_RESPONDER_STRUCT + fuse_ctrl_prim_axi_read_in_responder_s fuse_ctrl_prim_axi_read_in_responder_struct; + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent=null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the driver BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// driver BFM. This allows the driver BFM to call tasks and function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// **************************************************************************** +// This task is called by the run_phase in uvmf_driver_base. + virtual task access( inout REQ txn ); +// pragma uvmf custom access begin + if (configuration.initiator_responder==RESPONDER) begin + // Complete current transfer and wait for next transfer + bfm.respond_and_wait_for_next_transfer( + fuse_ctrl_prim_axi_read_in_initiator_struct, + txn.to_responder_struct() + ); + // Unpack information about initiated transfer received by this responder + txn.from_initiator_struct(fuse_ctrl_prim_axi_read_in_initiator_struct); + end else begin + // Initiate a transfer and get response + bfm.initiate_and_get_response( + txn.to_initiator_struct(), + fuse_ctrl_prim_axi_read_in_responder_struct + ); + // Unpack transfer response information received by this initiator + txn.from_responder_struct(fuse_ctrl_prim_axi_read_in_responder_struct); + end +// pragma uvmf custom access end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_driver_bfm.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_driver_bfm.sv new file mode 100644 index 0000000..a3f220a --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_driver_bfm.sv @@ -0,0 +1,385 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This interface performs the fuse_ctrl_prim_axi_read_in signal driving. It is +// accessed by the uvm fuse_ctrl_prim_axi_read_in driver through a virtual interface +// handle in the fuse_ctrl_prim_axi_read_in configuration. It drives the singals passed +// in through the port connection named bus of type fuse_ctrl_prim_axi_read_in_if. +// +// Input signals from the fuse_ctrl_prim_axi_read_in_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// This bfm drives signals with a _o suffix. These signals +// are driven onto signals within fuse_ctrl_prim_axi_read_in_if based on INITIATOR/RESPONDER and/or +// ARBITRATION/GRANT status. +// +// The output signal connections are as follows: +// signal_o -> bus.signal +// +// +// Interface functions and tasks used by UVM components: +// +// configure: +// This function gets configuration attributes from the +// UVM driver to set any required BFM configuration +// variables such as 'initiator_responder'. +// +// initiate_and_get_response: +// This task is used to perform signaling activity for initiating +// a protocol transfer. The task initiates the transfer, using +// input data from the initiator struct. Then the task captures +// response data, placing the data into the response struct. +// The response struct is returned to the driver class. +// +// respond_and_wait_for_next_transfer: +// This task is used to complete a current transfer as a responder +// and then wait for the initiator to start the next transfer. +// The task uses data in the responder struct to drive protocol +// signals to complete the transfer. The task then waits for +// the next transfer. Once the next transfer begins, data from +// the initiator is placed into the initiator struct and sent +// to the responder sequence for processing to determine +// what data to respond with. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_prim_axi_read_in_pkg_hdl::*; +`include "src/fuse_ctrl_prim_axi_read_in_macros.svh" + +interface fuse_ctrl_prim_axi_read_in_driver_bfm #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + + (fuse_ctrl_prim_axi_read_in_if bus); + // The following pragma and additional ones in-lined further below are for running this BFM on Veloce + // pragma attribute fuse_ctrl_prim_axi_read_in_driver_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: AW=%x DW=%x IW=%x UW=%x ", AW,DW,IW,UW), + UVM_DEBUG) +end +`endif + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + tri clk_i_i; + tri rst_ni_i; + + // Signal list (all signals are capable of being inputs and outputs for the sake + // of supporting both INITIATOR and RESPONDER mode operation. Expectation is that + // directionality in the config file was from the point-of-view of the INITIATOR + + // INITIATOR mode input signals + + // INITIATOR mode output signals + tri [AW-1:0] araddr_i; + reg [AW-1:0] araddr_o = 'bz; + tri [$bits(axi_pkg::axi_burst_e)-1:0] arburst_i; + reg [$bits(axi_pkg::axi_burst_e)-1:0] arburst_o = 'bz; + tri [2:0] arsize_i; + reg [2:0] arsize_o = 'bz; + tri [7:0] arlen_i; + reg [7:0] arlen_o = 'bz; + tri [UW-1:0] aruser_i; + reg [UW-1:0] aruser_o = 'bz; + tri [IW-1:0] arid_i; + reg [IW-1:0] arid_o = 'bz; + tri arlock_i; + reg arlock_o = 'bz; + tri arvalid_i; + reg arvalid_o = 'bz; + tri rready_i; + reg rready_o = 'bz; + + // Bi-directional signals + + + assign clk_i_i = bus.clk_i; + assign rst_ni_i = bus.rst_ni; + + // These are signals marked as 'input' by the config file, but the signals will be + // driven by this BFM if put into RESPONDER mode (flipping all signal directions around) + + + // These are signals marked as 'output' by the config file, but the outputs will + // not be driven by this BFM unless placed in INITIATOR mode. + assign bus.araddr = (initiator_responder == INITIATOR) ? araddr_o : 'bz; + assign araddr_i = bus.araddr; + assign bus.arburst = (initiator_responder == INITIATOR) ? arburst_o : 'bz; + assign arburst_i = bus.arburst; + assign bus.arsize = (initiator_responder == INITIATOR) ? arsize_o : 'bz; + assign arsize_i = bus.arsize; + assign bus.arlen = (initiator_responder == INITIATOR) ? arlen_o : 'bz; + assign arlen_i = bus.arlen; + assign bus.aruser = (initiator_responder == INITIATOR) ? aruser_o : 'bz; + assign aruser_i = bus.aruser; + assign bus.arid = (initiator_responder == INITIATOR) ? arid_o : 'bz; + assign arid_i = bus.arid; + assign bus.arlock = (initiator_responder == INITIATOR) ? arlock_o : 'bz; + assign arlock_i = bus.arlock; + assign bus.arvalid = (initiator_responder == INITIATOR) ? arvalid_o : 'bz; + assign arvalid_i = bus.arvalid; + assign bus.rready = (initiator_responder == INITIATOR) ? rready_o : 'bz; + assign rready_i = bus.rready; + + // Proxy handle to UVM driver + fuse_ctrl_prim_axi_read_in_pkg::fuse_ctrl_prim_axi_read_in_driver #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + proxy; + // pragma tbx oneway proxy.my_function_name_in_uvm_driver + + // **************************************************************************** + // **************************************************************************** + // Macros that define structs located in fuse_ctrl_prim_axi_read_in_macros.svh + // **************************************************************************** + // Struct for passing configuration data from fuse_ctrl_prim_axi_read_in_driver to this BFM + // **************************************************************************** + `fuse_ctrl_prim_axi_read_in_CONFIGURATION_STRUCT + // **************************************************************************** + // Structs for INITIATOR and RESPONDER data flow + //******************************************************************* + // Initiator macro used by fuse_ctrl_prim_axi_read_in_driver and fuse_ctrl_prim_axi_read_in_driver_bfm + // to communicate initiator driven data to fuse_ctrl_prim_axi_read_in_driver_bfm. + `fuse_ctrl_prim_axi_read_in_INITIATOR_STRUCT + fuse_ctrl_prim_axi_read_in_initiator_s initiator_struct; + // Responder macro used by fuse_ctrl_prim_axi_read_in_driver and fuse_ctrl_prim_axi_read_in_driver_bfm + // to communicate Responder driven data to fuse_ctrl_prim_axi_read_in_driver_bfm. + `fuse_ctrl_prim_axi_read_in_RESPONDER_STRUCT + fuse_ctrl_prim_axi_read_in_responder_s responder_struct; + + // **************************************************************************** +// pragma uvmf custom reset_condition_and_response begin + // Always block used to return signals to reset value upon assertion of reset + always @( negedge rst_ni_i ) + begin + // RESPONDER mode output signals + // INITIATOR mode output signals + araddr_o <= 'bz; + arburst_o <= 'bz; + arsize_o <= 'bz; + arlen_o <= 'bz; + aruser_o <= 'bz; + arid_o <= 'bz; + arlock_o <= 'bz; + arvalid_o <= 'bz; + rready_o <= 'bz; + // Bi-directional signals + + end +// pragma uvmf custom reset_condition_and_response end + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the driver BFM. It is called by the driver within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the driver BFM needs to be aware of the new configuration + // variables. + // + + function void configure(fuse_ctrl_prim_axi_read_in_configuration_s fuse_ctrl_prim_axi_read_in_configuration_arg); // pragma tbx xtf + initiator_responder = fuse_ctrl_prim_axi_read_in_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + +// pragma uvmf custom initiate_and_get_response begin +// **************************************************************************** +// UVMF_CHANGE_ME +// This task is used by an initator. The task first initiates a transfer then +// waits for the responder to complete the transfer. + task initiate_and_get_response( + // This argument passes transaction variables used by an initiator + // to perform the initial part of a protocol transfer. The values + // come from a sequence item created in a sequence. + input fuse_ctrl_prim_axi_read_in_initiator_s fuse_ctrl_prim_axi_read_in_initiator_struct, + // This argument is used to send data received from the responder + // back to the sequence item. The sequence item is returned to the sequence. + output fuse_ctrl_prim_axi_read_in_responder_s fuse_ctrl_prim_axi_read_in_responder_struct + );// pragma tbx xtf + // + // Members within the fuse_ctrl_prim_axi_read_in_initiator_struct: + // logic [AW-1:0] prim_araddr ; + // logic prim_arvalid ; + // logic [$bits(axi_pkg::axi_burst_e)] prim_arburst ; + // logic [2:0] prim_arsize ; + // logic [7:0] prim_arlen ; + // logic [UW-1:0] prim_aruser ; + // logic [IW-1:0] prim_arid ; + // logic prim_arlock ; + // logic prim_rready ; + // Members within the fuse_ctrl_prim_axi_read_in_responder_struct: + // logic [AW-1:0] prim_araddr ; + // logic prim_arvalid ; + // logic [$bits(axi_pkg::axi_burst_e)] prim_arburst ; + // logic [2:0] prim_arsize ; + // logic [7:0] prim_arlen ; + // logic [UW-1:0] prim_aruser ; + // logic [IW-1:0] prim_arid ; + // logic prim_arlock ; + // logic prim_rready ; + initiator_struct = fuse_ctrl_prim_axi_read_in_initiator_struct; + // + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clk_i_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available initiator input and inout signals listed. + // Initiator input signals + // Initiator inout signals + // How to assign a signal from an initiator struct member named xyz. + // All available initiator output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Initiator output signals + // araddr_o <= fuse_ctrl_prim_axi_read_in_initiator_struct.xyz; // [AW-1:0] + // arburst_o <= fuse_ctrl_prim_axi_read_in_initiator_struct.xyz; // [$bits(axi_pkg::axi_burst_e)-1:0] + // arsize_o <= fuse_ctrl_prim_axi_read_in_initiator_struct.xyz; // [2:0] + // arlen_o <= fuse_ctrl_prim_axi_read_in_initiator_struct.xyz; // [7:0] + // aruser_o <= fuse_ctrl_prim_axi_read_in_initiator_struct.xyz; // [UW-1:0] + // arid_o <= fuse_ctrl_prim_axi_read_in_initiator_struct.xyz; // [IW-1:0] + // arlock_o <= fuse_ctrl_prim_axi_read_in_initiator_struct.xyz; // + // arvalid_o <= fuse_ctrl_prim_axi_read_in_initiator_struct.xyz; // + // rready_o <= fuse_ctrl_prim_axi_read_in_initiator_struct.xyz; // + // Initiator inout signals + // Initiate a transfer using the data received. + @(posedge clk_i_i); + @(posedge clk_i_i); + // Wait for the responder to complete the transfer then place the responder data into + // fuse_ctrl_prim_axi_read_in_responder_struct. + @(posedge clk_i_i); + @(posedge clk_i_i); + responder_struct = fuse_ctrl_prim_axi_read_in_responder_struct; + endtask +// pragma uvmf custom initiate_and_get_response end + +// pragma uvmf custom respond_and_wait_for_next_transfer begin +// **************************************************************************** +// The first_transfer variable is used to prevent completing a transfer in the +// first call to this task. For the first call to this task, there is not +// current transfer to complete. +bit first_transfer=1; + +// UVMF_CHANGE_ME +// This task is used by a responder. The task first completes the current +// transfer in progress then waits for the initiator to start the next transfer. + task respond_and_wait_for_next_transfer( + // This argument is used to send data received from the initiator + // back to the sequence item. The sequence determines how to respond. + output fuse_ctrl_prim_axi_read_in_initiator_s fuse_ctrl_prim_axi_read_in_initiator_struct, + // This argument passes transaction variables used by a responder + // to complete a protocol transfer. The values come from a sequence item. + input fuse_ctrl_prim_axi_read_in_responder_s fuse_ctrl_prim_axi_read_in_responder_struct + );// pragma tbx xtf + // Variables within the fuse_ctrl_prim_axi_read_in_initiator_struct: + // logic [AW-1:0] prim_araddr ; + // logic prim_arvalid ; + // logic [$bits(axi_pkg::axi_burst_e)] prim_arburst ; + // logic [2:0] prim_arsize ; + // logic [7:0] prim_arlen ; + // logic [UW-1:0] prim_aruser ; + // logic [IW-1:0] prim_arid ; + // logic prim_arlock ; + // logic prim_rready ; + // Variables within the fuse_ctrl_prim_axi_read_in_responder_struct: + // logic [AW-1:0] prim_araddr ; + // logic prim_arvalid ; + // logic [$bits(axi_pkg::axi_burst_e)] prim_arburst ; + // logic [2:0] prim_arsize ; + // logic [7:0] prim_arlen ; + // logic [UW-1:0] prim_aruser ; + // logic [IW-1:0] prim_arid ; + // logic prim_arlock ; + // logic prim_rready ; + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clk_i_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available responder input and inout signals listed. + // Responder input signals + // fuse_ctrl_prim_axi_read_in_responder_struct.xyz = araddr_i; // [AW-1:0] + // fuse_ctrl_prim_axi_read_in_responder_struct.xyz = arburst_i; // [$bits(axi_pkg::axi_burst_e)-1:0] + // fuse_ctrl_prim_axi_read_in_responder_struct.xyz = arsize_i; // [2:0] + // fuse_ctrl_prim_axi_read_in_responder_struct.xyz = arlen_i; // [7:0] + // fuse_ctrl_prim_axi_read_in_responder_struct.xyz = aruser_i; // [UW-1:0] + // fuse_ctrl_prim_axi_read_in_responder_struct.xyz = arid_i; // [IW-1:0] + // fuse_ctrl_prim_axi_read_in_responder_struct.xyz = arlock_i; // + // fuse_ctrl_prim_axi_read_in_responder_struct.xyz = arvalid_i; // + // fuse_ctrl_prim_axi_read_in_responder_struct.xyz = rready_i; // + // Responder inout signals + // How to assign a signal, named xyz, from an initiator struct member. + // All available responder output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Responder output signals + // Responder inout signals + + @(posedge clk_i_i); + if (!first_transfer) begin + // Perform transfer response here. + // Reply using data recieved in the fuse_ctrl_prim_axi_read_in_responder_struct. + @(posedge clk_i_i); + // Reply using data recieved in the transaction handle. + @(posedge clk_i_i); + end + // Wait for next transfer then gather info from intiator about the transfer. + // Place the data into the fuse_ctrl_prim_axi_read_in_initiator_struct. + @(posedge clk_i_i); + @(posedge clk_i_i); + first_transfer = 0; + endtask +// pragma uvmf custom respond_and_wait_for_next_transfer end + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_if.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_if.sv new file mode 100644 index 0000000..f7a4f7b --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_if.sv @@ -0,0 +1,124 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface contains the fuse_ctrl_prim_axi_read_in interface signals. +// It is instantiated once per fuse_ctrl_prim_axi_read_in bus. Bus Functional Models, +// BFM's named fuse_ctrl_prim_axi_read_in_driver_bfm, are used to drive signals on the bus. +// BFM's named fuse_ctrl_prim_axi_read_in_monitor_bfm are used to monitor signals on the +// bus. This interface signal bundle is passed in the port list of +// the BFM in order to give the BFM access to the signals in this +// interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// This template can be used to connect a DUT to these signals +// +// .dut_signal_port(fuse_ctrl_prim_axi_read_in_bus.araddr), // Agent output +// .dut_signal_port(fuse_ctrl_prim_axi_read_in_bus.arburst), // Agent output +// .dut_signal_port(fuse_ctrl_prim_axi_read_in_bus.arsize), // Agent output +// .dut_signal_port(fuse_ctrl_prim_axi_read_in_bus.arlen), // Agent output +// .dut_signal_port(fuse_ctrl_prim_axi_read_in_bus.aruser), // Agent output +// .dut_signal_port(fuse_ctrl_prim_axi_read_in_bus.arid), // Agent output +// .dut_signal_port(fuse_ctrl_prim_axi_read_in_bus.arlock), // Agent output +// .dut_signal_port(fuse_ctrl_prim_axi_read_in_bus.arvalid), // Agent output +// .dut_signal_port(fuse_ctrl_prim_axi_read_in_bus.rready), // Agent output + +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_prim_axi_read_in_pkg_hdl::*; + +interface fuse_ctrl_prim_axi_read_in_if #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + + + ( + input tri clk_i, + input tri rst_ni, + inout tri [AW-1:0] araddr, + inout tri [$bits(axi_pkg::axi_burst_e)-1:0] arburst, + inout tri [2:0] arsize, + inout tri [7:0] arlen, + inout tri [UW-1:0] aruser, + inout tri [IW-1:0] arid, + inout tri arlock, + inout tri arvalid, + inout tri rready + ); + +modport monitor_port + ( + input clk_i, + input rst_ni, + input araddr, + input arburst, + input arsize, + input arlen, + input aruser, + input arid, + input arlock, + input arvalid, + input rready + ); + +modport initiator_port + ( + input clk_i, + input rst_ni, + output araddr, + output arburst, + output arsize, + output arlen, + output aruser, + output arid, + output arlock, + output arvalid, + output rready + ); + +modport responder_port + ( + input clk_i, + input rst_ni, + input araddr, + input arburst, + input arsize, + input arlen, + input aruser, + input arid, + input arlock, + input arvalid, + input rready + ); + + +// pragma uvmf custom interface_item_additional begin +// pragma uvmf custom interface_item_additional end + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_infact_coverage_strategy.csv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_infact_coverage_strategy.csv new file mode 100644 index 0000000..1c218e1 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_infact_coverage_strategy.csv @@ -0,0 +1,6 @@ +Global +auto_bin_max, 64 + +Name,Type,Include +rand_fields,coverpoint,=rand *.** + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_macros.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_macros.svh new file mode 100644 index 0000000..ba93fd2 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_macros.svh @@ -0,0 +1,207 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains macros used with the fuse_ctrl_prim_axi_read_in package. +// These macros include packed struct definitions. These structs are +// used to pass data between classes, hvl, and BFM's, hdl. Use of +// structs are more efficient and simpler to modify. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_struct +// and from_struct methods defined in the macros below that are used in +// the fuse_ctrl_prim_axi_read_in_configuration class. +// + `define fuse_ctrl_prim_axi_read_in_CONFIGURATION_STRUCT \ +typedef struct packed { \ + uvmf_active_passive_t active_passive; \ + uvmf_initiator_responder_t initiator_responder; \ + } fuse_ctrl_prim_axi_read_in_configuration_s; + + `define fuse_ctrl_prim_axi_read_in_CONFIGURATION_TO_STRUCT_FUNCTION \ + virtual function fuse_ctrl_prim_axi_read_in_configuration_s to_struct();\ + fuse_ctrl_prim_axi_read_in_configuration_struct = \ + {\ + this.active_passive,\ + this.initiator_responder\ + };\ + return ( fuse_ctrl_prim_axi_read_in_configuration_struct );\ + endfunction + + `define fuse_ctrl_prim_axi_read_in_CONFIGURATION_FROM_STRUCT_FUNCTION \ + virtual function void from_struct(fuse_ctrl_prim_axi_read_in_configuration_s fuse_ctrl_prim_axi_read_in_configuration_struct);\ + {\ + this.active_passive,\ + this.initiator_responder \ + } = fuse_ctrl_prim_axi_read_in_configuration_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_monitor_struct +// and from_monitor_struct methods of the fuse_ctrl_prim_axi_read_in_transaction class. +// + `define fuse_ctrl_prim_axi_read_in_MONITOR_STRUCT typedef struct packed { \ + logic [AW-1:0] prim_araddr ; \ + logic prim_arvalid ; \ + logic [$bits(axi_pkg::axi_burst_e)] prim_arburst ; \ + logic [2:0] prim_arsize ; \ + logic [7:0] prim_arlen ; \ + logic [UW-1:0] prim_aruser ; \ + logic [IW-1:0] prim_arid ; \ + logic prim_arlock ; \ + logic prim_rready ; \ + } fuse_ctrl_prim_axi_read_in_monitor_s; + + `define fuse_ctrl_prim_axi_read_in_TO_MONITOR_STRUCT_FUNCTION \ + virtual function fuse_ctrl_prim_axi_read_in_monitor_s to_monitor_struct();\ + fuse_ctrl_prim_axi_read_in_monitor_struct = \ + { \ + this.prim_araddr , \ + this.prim_arvalid , \ + this.prim_arburst , \ + this.prim_arsize , \ + this.prim_arlen , \ + this.prim_aruser , \ + this.prim_arid , \ + this.prim_arlock , \ + this.prim_rready \ + };\ + return ( fuse_ctrl_prim_axi_read_in_monitor_struct);\ + endfunction\ + + `define fuse_ctrl_prim_axi_read_in_FROM_MONITOR_STRUCT_FUNCTION \ + virtual function void from_monitor_struct(fuse_ctrl_prim_axi_read_in_monitor_s fuse_ctrl_prim_axi_read_in_monitor_struct);\ + {\ + this.prim_araddr , \ + this.prim_arvalid , \ + this.prim_arburst , \ + this.prim_arsize , \ + this.prim_arlen , \ + this.prim_aruser , \ + this.prim_arid , \ + this.prim_arlock , \ + this.prim_rready \ + } = fuse_ctrl_prim_axi_read_in_monitor_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_initiator_struct +// and from_initiator_struct methods of the fuse_ctrl_prim_axi_read_in_transaction class. +// Also update the comments in the driver BFM. +// + `define fuse_ctrl_prim_axi_read_in_INITIATOR_STRUCT typedef struct packed { \ + logic [AW-1:0] prim_araddr ; \ + logic prim_arvalid ; \ + logic [$bits(axi_pkg::axi_burst_e)] prim_arburst ; \ + logic [2:0] prim_arsize ; \ + logic [7:0] prim_arlen ; \ + logic [UW-1:0] prim_aruser ; \ + logic [IW-1:0] prim_arid ; \ + logic prim_arlock ; \ + logic prim_rready ; \ + } fuse_ctrl_prim_axi_read_in_initiator_s; + + `define fuse_ctrl_prim_axi_read_in_TO_INITIATOR_STRUCT_FUNCTION \ + virtual function fuse_ctrl_prim_axi_read_in_initiator_s to_initiator_struct();\ + fuse_ctrl_prim_axi_read_in_initiator_struct = \ + {\ + this.prim_araddr , \ + this.prim_arvalid , \ + this.prim_arburst , \ + this.prim_arsize , \ + this.prim_arlen , \ + this.prim_aruser , \ + this.prim_arid , \ + this.prim_arlock , \ + this.prim_rready \ + };\ + return ( fuse_ctrl_prim_axi_read_in_initiator_struct);\ + endfunction + + `define fuse_ctrl_prim_axi_read_in_FROM_INITIATOR_STRUCT_FUNCTION \ + virtual function void from_initiator_struct(fuse_ctrl_prim_axi_read_in_initiator_s fuse_ctrl_prim_axi_read_in_initiator_struct);\ + {\ + this.prim_araddr , \ + this.prim_arvalid , \ + this.prim_arburst , \ + this.prim_arsize , \ + this.prim_arlen , \ + this.prim_aruser , \ + this.prim_arid , \ + this.prim_arlock , \ + this.prim_rready \ + } = fuse_ctrl_prim_axi_read_in_initiator_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_responder_struct +// and from_responder_struct methods of the fuse_ctrl_prim_axi_read_in_transaction class. +// Also update the comments in the driver BFM. +// + `define fuse_ctrl_prim_axi_read_in_RESPONDER_STRUCT typedef struct packed { \ + logic [AW-1:0] prim_araddr ; \ + logic prim_arvalid ; \ + logic [$bits(axi_pkg::axi_burst_e)] prim_arburst ; \ + logic [2:0] prim_arsize ; \ + logic [7:0] prim_arlen ; \ + logic [UW-1:0] prim_aruser ; \ + logic [IW-1:0] prim_arid ; \ + logic prim_arlock ; \ + logic prim_rready ; \ + } fuse_ctrl_prim_axi_read_in_responder_s; + + `define fuse_ctrl_prim_axi_read_in_TO_RESPONDER_STRUCT_FUNCTION \ + virtual function fuse_ctrl_prim_axi_read_in_responder_s to_responder_struct();\ + fuse_ctrl_prim_axi_read_in_responder_struct = \ + {\ + this.prim_araddr , \ + this.prim_arvalid , \ + this.prim_arburst , \ + this.prim_arsize , \ + this.prim_arlen , \ + this.prim_aruser , \ + this.prim_arid , \ + this.prim_arlock , \ + this.prim_rready \ + };\ + return ( fuse_ctrl_prim_axi_read_in_responder_struct);\ + endfunction + + `define fuse_ctrl_prim_axi_read_in_FROM_RESPONDER_STRUCT_FUNCTION \ + virtual function void from_responder_struct(fuse_ctrl_prim_axi_read_in_responder_s fuse_ctrl_prim_axi_read_in_responder_struct);\ + {\ + this.prim_araddr , \ + this.prim_arvalid , \ + this.prim_arburst , \ + this.prim_arsize , \ + this.prim_arlen , \ + this.prim_aruser , \ + this.prim_arid , \ + this.prim_arlock , \ + this.prim_rready \ + } = fuse_ctrl_prim_axi_read_in_responder_struct;\ + endfunction +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_monitor.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_monitor.svh new file mode 100644 index 0000000..1c39493 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_monitor.svh @@ -0,0 +1,131 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class receives fuse_ctrl_prim_axi_read_in transactions observed by the +// fuse_ctrl_prim_axi_read_in monitor BFM and broadcasts them through the analysis port +// on the agent. It accesses the monitor BFM through the monitor +// task. This UVM component captures transactions +// for viewing in the waveform viewer if the +// enable_transaction_viewing flag is set in the configuration. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_read_in_monitor #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvmf_monitor_base #( + .CONFIG_T(fuse_ctrl_prim_axi_read_in_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .BFM_BIND_T(virtual fuse_ctrl_prim_axi_read_in_monitor_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .TRANS_T(fuse_ctrl_prim_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +)); + + `uvm_component_param_utils( fuse_ctrl_prim_axi_read_in_monitor #( + AW, + DW, + IW, + UW + ) +) + +// Structure used to pass data from monitor BFM to monitor class in agent. +// Use to_monitor_struct function to pack transaction variables into structure. +// Use from_monitor_struct function to unpack transaction variables from structure. +`fuse_ctrl_prim_axi_read_in_MONITOR_STRUCT + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the monitor BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// monitor BFM. This allows the monitor BFM to call the notify_transaction +// function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// *************************************************************************** + virtual task run_phase(uvm_phase phase); + // Start monitor BFM thread and don't call super.run() in order to + // override the default monitor proxy 'pull' behavior with the more + // emulation-friendly BFM 'push' approach using the notify_transaction + // function below + bfm.start_monitoring(); + endtask + +// ************************************************************************** + +// This function is called by the monitor BFM. It receives data observed by the +// monitor BFM. Data is passed using the fuse_ctrl_prim_axi_read_in_monitor_struct. + virtual function void notify_transaction(input fuse_ctrl_prim_axi_read_in_monitor_s fuse_ctrl_prim_axi_read_in_monitor_struct); + + + trans = new("trans"); + trans.from_monitor_struct(fuse_ctrl_prim_axi_read_in_monitor_struct); + trans.start_time = time_stamp; + trans.end_time = $time; + time_stamp = trans.end_time; + + analyze(trans); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_monitor_bfm.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_monitor_bfm.sv new file mode 100644 index 0000000..efa2c9f --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_monitor_bfm.sv @@ -0,0 +1,232 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface performs the fuse_ctrl_prim_axi_read_in signal monitoring. +// It is accessed by the uvm fuse_ctrl_prim_axi_read_in monitor through a virtual +// interface handle in the fuse_ctrl_prim_axi_read_in configuration. It monitors the +// signals passed in through the port connection named bus of +// type fuse_ctrl_prim_axi_read_in_if. +// +// Input signals from the fuse_ctrl_prim_axi_read_in_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// Interface functions and tasks used by UVM components: +// monitor(inout TRANS_T txn); +// This task receives the transaction, txn, from the +// UVM monitor and then populates variables in txn +// from values observed on bus activity. This task +// blocks until an operation on the fuse_ctrl_prim_axi_read_in bus is complete. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_prim_axi_read_in_pkg_hdl::*; +`include "src/fuse_ctrl_prim_axi_read_in_macros.svh" + + +interface fuse_ctrl_prim_axi_read_in_monitor_bfm #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + + ( fuse_ctrl_prim_axi_read_in_if bus ); + // The pragma below and additional ones in-lined further down are for running this BFM on Veloce + // pragma attribute fuse_ctrl_prim_axi_read_in_monitor_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: AW=%x DW=%x IW=%x UW=%x ", AW,DW,IW,UW), + UVM_DEBUG) +end +`endif + + + // Structure used to pass transaction data from monitor BFM to monitor class in agent. +`fuse_ctrl_prim_axi_read_in_MONITOR_STRUCT + fuse_ctrl_prim_axi_read_in_monitor_s fuse_ctrl_prim_axi_read_in_monitor_struct; + + // Structure used to pass configuration data from monitor class to monitor BFM. + `fuse_ctrl_prim_axi_read_in_CONFIGURATION_STRUCT + + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + tri clk_i_i; + tri rst_ni_i; + tri [AW-1:0] araddr_i; + tri [$bits(axi_pkg::axi_burst_e)-1:0] arburst_i; + tri [2:0] arsize_i; + tri [7:0] arlen_i; + tri [UW-1:0] aruser_i; + tri [IW-1:0] arid_i; + tri arlock_i; + tri arvalid_i; + tri rready_i; + assign clk_i_i = bus.clk_i; + assign rst_ni_i = bus.rst_ni; + assign araddr_i = bus.araddr; + assign arburst_i = bus.arburst; + assign arsize_i = bus.arsize; + assign arlen_i = bus.arlen; + assign aruser_i = bus.aruser; + assign arid_i = bus.arid; + assign arlock_i = bus.arlock; + assign arvalid_i = bus.arvalid; + assign rready_i = bus.rready; + + // Proxy handle to UVM monitor + fuse_ctrl_prim_axi_read_in_pkg::fuse_ctrl_prim_axi_read_in_monitor #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + proxy; + // pragma tbx oneway proxy.notify_transaction + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + task wait_for_reset();// pragma tbx xtf + @(posedge clk_i_i) ; + do_wait_for_reset(); + endtask + + // **************************************************************************** + task do_wait_for_reset(); + // pragma uvmf custom reset_condition begin + wait ( rst_ni_i === 1 ) ; + @(posedge clk_i_i) ; + // pragma uvmf custom reset_condition end + endtask + + //****************************************************************** + + task wait_for_num_clocks(input int unsigned count); // pragma tbx xtf + @(posedge clk_i_i); + + repeat (count-1) @(posedge clk_i_i); + endtask + + //****************************************************************** + event go; + function void start_monitoring();// pragma tbx xtf + -> go; + endfunction + + // **************************************************************************** + initial begin + @go; + forever begin + @(posedge clk_i_i); + do_monitor( fuse_ctrl_prim_axi_read_in_monitor_struct ); + + + proxy.notify_transaction( fuse_ctrl_prim_axi_read_in_monitor_struct ); + + end + end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the monitor BFM. It is called by the monitor within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the monitor BFM needs to be aware of the new configuration + // variables. + // + function void configure(fuse_ctrl_prim_axi_read_in_configuration_s fuse_ctrl_prim_axi_read_in_configuration_arg); // pragma tbx xtf + initiator_responder = fuse_ctrl_prim_axi_read_in_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + + + // **************************************************************************** + + task do_monitor(output fuse_ctrl_prim_axi_read_in_monitor_s fuse_ctrl_prim_axi_read_in_monitor_struct); + // + // Available struct members: + // // fuse_ctrl_prim_axi_read_in_monitor_struct.prim_araddr + // // fuse_ctrl_prim_axi_read_in_monitor_struct.prim_arvalid + // // fuse_ctrl_prim_axi_read_in_monitor_struct.prim_arburst + // // fuse_ctrl_prim_axi_read_in_monitor_struct.prim_arsize + // // fuse_ctrl_prim_axi_read_in_monitor_struct.prim_arlen + // // fuse_ctrl_prim_axi_read_in_monitor_struct.prim_aruser + // // fuse_ctrl_prim_axi_read_in_monitor_struct.prim_arid + // // fuse_ctrl_prim_axi_read_in_monitor_struct.prim_arlock + // // fuse_ctrl_prim_axi_read_in_monitor_struct.prim_rready + // // + // Reference code; + // How to wait for signal value + // while (control_signal === 1'b1) @(posedge clk_i_i); + // + // How to assign a struct member, named xyz, from a signal. + // All available input signals listed. + // fuse_ctrl_prim_axi_read_in_monitor_struct.xyz = araddr_i; // [AW-1:0] + // fuse_ctrl_prim_axi_read_in_monitor_struct.xyz = arburst_i; // [$bits(axi_pkg::axi_burst_e)-1:0] + // fuse_ctrl_prim_axi_read_in_monitor_struct.xyz = arsize_i; // [2:0] + // fuse_ctrl_prim_axi_read_in_monitor_struct.xyz = arlen_i; // [7:0] + // fuse_ctrl_prim_axi_read_in_monitor_struct.xyz = aruser_i; // [UW-1:0] + // fuse_ctrl_prim_axi_read_in_monitor_struct.xyz = arid_i; // [IW-1:0] + // fuse_ctrl_prim_axi_read_in_monitor_struct.xyz = arlock_i; // + // fuse_ctrl_prim_axi_read_in_monitor_struct.xyz = arvalid_i; // + // fuse_ctrl_prim_axi_read_in_monitor_struct.xyz = rready_i; // + // pragma uvmf custom do_monitor begin + // UVMF_CHANGE_ME : Implement protocol monitoring. The commented reference code + // below are examples of how to capture signal values and assign them to + // structure members. All available input signals are listed. The 'while' + // code example shows how to wait for a synchronous flow control signal. This + // task should return when a complete transfer has been observed. Once this task is + // exited with captured values, it is then called again to wait for and observe + // the next transfer. One clock cycle is consumed between calls to do_monitor. + @(posedge clk_i_i); + @(posedge clk_i_i); + @(posedge clk_i_i); + @(posedge clk_i_i); + // pragma uvmf custom do_monitor end + endtask + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_random_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_random_sequence.svh new file mode 100644 index 0000000..1cb563f --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_random_sequence.svh @@ -0,0 +1,91 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This sequences randomizes the fuse_ctrl_prim_axi_read_in transaction and sends it +// to the UVM driver. +// +// This sequence constructs and randomizes a fuse_ctrl_prim_axi_read_in_transaction. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_read_in_random_sequence #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + + extends fuse_ctrl_prim_axi_read_in_sequence_base #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +; + + `uvm_object_param_utils( fuse_ctrl_prim_axi_read_in_random_sequence #( + AW, + DW, + IW, + UW + ) +) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //***************************************************************** + function new(string name = ""); + super.new(name); + endfunction: new + + // **************************************************************************** + // TASK : body() + // This task is automatically executed when this sequence is started using the + // start(sequencerHandle) task. + // + task body(); + + // Construct the transaction + req=fuse_ctrl_prim_axi_read_in_transaction#( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +::type_id::create("req"); + start_item(req); + // Randomize the transaction + if(!req.randomize()) `uvm_fatal("SEQ", "fuse_ctrl_prim_axi_read_in_random_sequence::body()-fuse_ctrl_prim_axi_read_in_transaction randomization failed") + // Send the transaction to the fuse_ctrl_prim_axi_read_in_driver_bfm via the sequencer and fuse_ctrl_prim_axi_read_in_driver. + finish_item(req); + `uvm_info("SEQ", {"Response:",req.convert2string()},UVM_MEDIUM) + + endtask + +endclass: fuse_ctrl_prim_axi_read_in_random_sequence + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_responder_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_responder_sequence.svh new file mode 100644 index 0000000..3a60a5c --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_responder_sequence.svh @@ -0,0 +1,87 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class can be used to provide stimulus when an interface +// has been configured to run in a responder mode. It +// will never finish by default, always going back to the driver +// and driver BFM for the next transaction with which to respond. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_read_in_responder_sequence #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + + extends fuse_ctrl_prim_axi_read_in_sequence_base #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +; + + `uvm_object_param_utils( fuse_ctrl_prim_axi_read_in_responder_sequence #( + AW, + DW, + IW, + UW + ) +) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "fuse_ctrl_prim_axi_read_in_responder_sequence"); + super.new(name); + endfunction + + task body(); + req=fuse_ctrl_prim_axi_read_in_transaction#( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +::type_id::create("req"); + forever begin + start_item(req); + finish_item(req); + // pragma uvmf custom body begin + // UVMF_CHANGE_ME : Do something here with the resulting req item. The + // finish_item() call above will block until the req transaction is ready + // to be handled by the responder sequence. + // If this was an item that required a response, the expectation is + // that the response should be populated within this transaction now. + `uvm_info("SEQ",$sformatf("Processed txn: %s",req.convert2string()),UVM_HIGH) + // pragma uvmf custom body end + end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_sequence_base.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_sequence_base.svh new file mode 100644 index 0000000..7c8932c --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_sequence_base.svh @@ -0,0 +1,146 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the class used as the base class for all sequences +// for this interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_read_in_sequence_base #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvmf_sequence_base #( + .REQ(fuse_ctrl_prim_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .RSP(fuse_ctrl_prim_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +)); + + `uvm_object_param_utils( fuse_ctrl_prim_axi_read_in_sequence_base #( + AW, + DW, + IW, + UW + ) +) + + // variables + typedef fuse_ctrl_prim_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + fuse_ctrl_prim_axi_read_in_transaction_req_t; + fuse_ctrl_prim_axi_read_in_transaction_req_t req; + typedef fuse_ctrl_prim_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + fuse_ctrl_prim_axi_read_in_transaction_rsp_t; + fuse_ctrl_prim_axi_read_in_transaction_rsp_t rsp; + + // Event for identifying when a response was received from the sequencer + event new_rsp; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // TASK : get_responses() + // This task recursively gets sequence item responses from the sequencer. + // + virtual task get_responses(); + fork + begin + // Block until new rsp available + get_response(rsp); + // New rsp received. Indicate to sequence using event. + ->new_rsp; + // Display the received response transaction + `uvm_info("SEQ", {"New response transaction:",rsp.convert2string()}, UVM_MEDIUM) + end + join_none + endtask + + // **************************************************************************** + // TASK : pre_body() + // This task is called automatically when start is called with call_pre_post set to 1 (default). + // By calling get_responses() within pre_body() any derived sequences are automatically + // processing response transactions. Only un-comment this call to get_responses() if you + // have configured the interface driver to utilize the response transaction path by setting + // the configuration variable "return_transaction_response" to 1. Otherwise it is possible + // to impact runtime performance and memory utilization. + // + virtual task pre_body(); + // pragma uvmf custom pre_body begin +// get_responses(); + // pragma uvmf custom pre_body end + endtask + + // **************************************************************************** + // TASK : body() + // This task is called automatically when start is called. This sequence sends + // a req sequence item to the sequencer identified as an argument in the call + // to start. + // + virtual task body(); + // pragma uvmf custom body begin + start_item(req); + finish_item(req); + // pragma uvmf custom body end + endtask + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name =""); + super.new( name ); + // pragma uvmf custom new begin + req = fuse_ctrl_prim_axi_read_in_transaction_req_t::type_id::create("req"); + rsp = fuse_ctrl_prim_axi_read_in_transaction_rsp_t::type_id::create("rsp"); + // pragma uvmf custom new end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_transaction.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_transaction.svh new file mode 100644 index 0000000..601cca3 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_transaction.svh @@ -0,0 +1,243 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class defines the variables required for an fuse_ctrl_prim_axi_read_in +// transaction. Class variables to be displayed in waveform transaction +// viewing are added to the transaction viewing stream in the add_to_wave +// function. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_read_in_transaction #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvmf_transaction_base; + + `uvm_object_param_utils( fuse_ctrl_prim_axi_read_in_transaction #( + AW, + DW, + IW, + UW + ) +) + + rand logic [AW-1:0] prim_araddr ; + logic prim_arvalid ; + logic [$bits(axi_pkg::axi_burst_e)] prim_arburst ; + logic [2:0] prim_arsize ; + logic [7:0] prim_arlen ; + logic [UW-1:0] prim_aruser ; + logic [IW-1:0] prim_arid ; + logic prim_arlock ; + logic prim_rready ; + + //Constraints for the transaction variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //******************************************************************* + //******************************************************************* + // Macros that define structs and associated functions are + // located in fuse_ctrl_prim_axi_read_in_macros.svh + + //******************************************************************* + // Monitor macro used by fuse_ctrl_prim_axi_read_in_monitor and fuse_ctrl_prim_axi_read_in_monitor_bfm + // This struct is defined in fuse_ctrl_prim_axi_read_in_macros.svh + `fuse_ctrl_prim_axi_read_in_MONITOR_STRUCT + fuse_ctrl_prim_axi_read_in_monitor_s fuse_ctrl_prim_axi_read_in_monitor_struct; + //******************************************************************* + // FUNCTION: to_monitor_struct() + // This function packs transaction variables into a fuse_ctrl_prim_axi_read_in_monitor_s + // structure. The function returns the handle to the fuse_ctrl_prim_axi_read_in_monitor_struct. + // This function is defined in fuse_ctrl_prim_axi_read_in_macros.svh + `fuse_ctrl_prim_axi_read_in_TO_MONITOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_monitor_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_prim_axi_read_in_macros.svh + `fuse_ctrl_prim_axi_read_in_FROM_MONITOR_STRUCT_FUNCTION + + //******************************************************************* + // Initiator macro used by fuse_ctrl_prim_axi_read_in_driver and fuse_ctrl_prim_axi_read_in_driver_bfm + // to communicate initiator driven data to fuse_ctrl_prim_axi_read_in_driver_bfm. + // This struct is defined in fuse_ctrl_prim_axi_read_in_macros.svh + `fuse_ctrl_prim_axi_read_in_INITIATOR_STRUCT + fuse_ctrl_prim_axi_read_in_initiator_s fuse_ctrl_prim_axi_read_in_initiator_struct; + //******************************************************************* + // FUNCTION: to_initiator_struct() + // This function packs transaction variables into a fuse_ctrl_prim_axi_read_in_initiator_s + // structure. The function returns the handle to the fuse_ctrl_prim_axi_read_in_initiator_struct. + // This function is defined in fuse_ctrl_prim_axi_read_in_macros.svh + `fuse_ctrl_prim_axi_read_in_TO_INITIATOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_initiator_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_prim_axi_read_in_macros.svh + `fuse_ctrl_prim_axi_read_in_FROM_INITIATOR_STRUCT_FUNCTION + + //******************************************************************* + // Responder macro used by fuse_ctrl_prim_axi_read_in_driver and fuse_ctrl_prim_axi_read_in_driver_bfm + // to communicate Responder driven data to fuse_ctrl_prim_axi_read_in_driver_bfm. + // This struct is defined in fuse_ctrl_prim_axi_read_in_macros.svh + `fuse_ctrl_prim_axi_read_in_RESPONDER_STRUCT + fuse_ctrl_prim_axi_read_in_responder_s fuse_ctrl_prim_axi_read_in_responder_struct; + //******************************************************************* + // FUNCTION: to_responder_struct() + // This function packs transaction variables into a fuse_ctrl_prim_axi_read_in_responder_s + // structure. The function returns the handle to the fuse_ctrl_prim_axi_read_in_responder_struct. + // This function is defined in fuse_ctrl_prim_axi_read_in_macros.svh + `fuse_ctrl_prim_axi_read_in_TO_RESPONDER_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_responder_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_prim_axi_read_in_macros.svh + `fuse_ctrl_prim_axi_read_in_FROM_RESPONDER_STRUCT_FUNCTION + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + endfunction + + // **************************************************************************** + // FUNCTION: convert2string() + // This function converts all variables in this class to a single string for + // logfile reporting. + // + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + // UVMF_CHANGE_ME : Customize format if desired. + return $sformatf("prim_araddr:0x%x prim_arvalid:0x%x prim_arburst:0x%x prim_arsize:0x%x prim_arlen:0x%x prim_aruser:0x%x prim_arid:0x%x prim_arlock:0x%x prim_rready:0x%x ",prim_araddr,prim_arvalid,prim_arburst,prim_arsize,prim_arlen,prim_aruser,prim_arid,prim_arlock,prim_rready); + // pragma uvmf custom convert2string end + endfunction + + //******************************************************************* + // FUNCTION: do_print() + // This function is automatically called when the .print() function + // is called on this class. + // + virtual function void do_print(uvm_printer printer); + // pragma uvmf custom do_print begin + // UVMF_CHANGE_ME : Current contents of do_print allows for the use of UVM 1.1d, 1.2 or P1800.2. + // Update based on your own printing preference according to your preferred UVM version + $display(convert2string()); + // pragma uvmf custom do_print end + endfunction + + //******************************************************************* + // FUNCTION: do_compare() + // This function is automatically called when the .compare() function + // is called on this class. + // + virtual function bit do_compare (uvm_object rhs, uvm_comparer comparer); + fuse_ctrl_prim_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + RHS; + if (!$cast(RHS,rhs)) return 0; + // pragma uvmf custom do_compare begin + // UVMF_CHANGE_ME : Eliminate comparison of variables not to be used for compare + return (super.do_compare(rhs,comparer) + ); + // pragma uvmf custom do_compare end + endfunction + + //******************************************************************* + // FUNCTION: do_copy() + // This function is automatically called when the .copy() function + // is called on this class. + // + virtual function void do_copy (uvm_object rhs); + fuse_ctrl_prim_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + RHS; + assert($cast(RHS,rhs)); + // pragma uvmf custom do_copy begin + super.do_copy(rhs); + this.prim_araddr = RHS.prim_araddr; + this.prim_arvalid = RHS.prim_arvalid; + this.prim_arburst = RHS.prim_arburst; + this.prim_arsize = RHS.prim_arsize; + this.prim_arlen = RHS.prim_arlen; + this.prim_aruser = RHS.prim_aruser; + this.prim_arid = RHS.prim_arid; + this.prim_arlock = RHS.prim_arlock; + this.prim_rready = RHS.prim_rready; + // pragma uvmf custom do_copy end + endfunction + + // **************************************************************************** + // FUNCTION: add_to_wave() + // This function is used to display variables in this class in the waveform + // viewer. The start_time and end_time variables must be set before this + // function is called. If the start_time and end_time variables are not set + // the transaction will be hidden at 0ns on the waveform display. + // + virtual function void add_to_wave(int transaction_viewing_stream_h); + `ifdef QUESTA + if (transaction_view_h == 0) begin + transaction_view_h = $begin_transaction(transaction_viewing_stream_h,"fuse_ctrl_prim_axi_read_in_transaction",start_time); + end + super.add_to_wave(transaction_view_h); + // pragma uvmf custom add_to_wave begin + // UVMF_CHANGE_ME : Color can be applied to transaction entries based on content, example below + // case() + // 1 : $add_color(transaction_view_h,"red"); + // default : $add_color(transaction_view_h,"grey"); + // endcase + // UVMF_CHANGE_ME : Eliminate transaction variables not wanted in transaction viewing in the waveform viewer + $add_attribute(transaction_view_h,prim_araddr,"prim_araddr"); + $add_attribute(transaction_view_h,prim_arvalid,"prim_arvalid"); + $add_attribute(transaction_view_h,prim_arburst,"prim_arburst"); + $add_attribute(transaction_view_h,prim_arsize,"prim_arsize"); + $add_attribute(transaction_view_h,prim_arlen,"prim_arlen"); + $add_attribute(transaction_view_h,prim_aruser,"prim_aruser"); + $add_attribute(transaction_view_h,prim_arid,"prim_arid"); + $add_attribute(transaction_view_h,prim_arlock,"prim_arlock"); + $add_attribute(transaction_view_h,prim_rready,"prim_rready"); + // pragma uvmf custom add_to_wave end + $end_transaction(transaction_view_h,end_time); + $free_transaction(transaction_view_h); + `endif // QUESTA + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_transaction_coverage.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_transaction_coverage.svh new file mode 100644 index 0000000..9315e32 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_transaction_coverage.svh @@ -0,0 +1,110 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class records fuse_ctrl_prim_axi_read_in transaction information using +// a covergroup named fuse_ctrl_prim_axi_read_in_transaction_cg. An instance of this +// coverage component is instantiated in the uvmf_parameterized_agent +// if the has_coverage flag is set. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_read_in_transaction_coverage #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvm_subscriber #(.T(fuse_ctrl_prim_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +)); + + `uvm_component_param_utils( fuse_ctrl_prim_axi_read_in_transaction_coverage #( + AW, + DW, + IW, + UW + ) +) + + T coverage_trans; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + covergroup fuse_ctrl_prim_axi_read_in_transaction_cg; + // pragma uvmf custom covergroup begin + // UVMF_CHANGE_ME : Add coverage bins, crosses, exclusions, etc. according to coverage needs. + option.auto_bin_max=1024; + option.per_instance=1; + prim_araddr: coverpoint coverage_trans.prim_araddr; + prim_arvalid: coverpoint coverage_trans.prim_arvalid; + prim_arburst: coverpoint coverage_trans.prim_arburst; + prim_arsize: coverpoint coverage_trans.prim_arsize; + prim_arlen: coverpoint coverage_trans.prim_arlen; + prim_aruser: coverpoint coverage_trans.prim_aruser; + prim_arid: coverpoint coverage_trans.prim_arid; + prim_arlock: coverpoint coverage_trans.prim_arlock; + prim_rready: coverpoint coverage_trans.prim_rready; + // pragma uvmf custom covergroup end + endgroup + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new(string name="", uvm_component parent=null); + super.new(name,parent); + fuse_ctrl_prim_axi_read_in_transaction_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that transaction variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + endfunction + + // **************************************************************************** + // FUNCTION : build_phase() + // This function is the standard UVM build_phase. + // + function void build_phase(uvm_phase phase); + fuse_ctrl_prim_axi_read_in_transaction_cg.set_inst_name($sformatf("fuse_ctrl_prim_axi_read_in_transaction_cg_%s",get_full_name())); + endfunction + + // **************************************************************************** + // FUNCTION: write (T t) + // This function is automatically executed when a transaction arrives on the + // analysis_export. It copies values from the variables in the transaction + // to local variables used to collect functional coverage. + // + virtual function void write (T t); + `uvm_info("COV","Received transaction",UVM_HIGH); + coverage_trans = t; + fuse_ctrl_prim_axi_read_in_transaction_cg.sample(); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_typedefs.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_typedefs.svh new file mode 100644 index 0000000..f2a7bdb --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_typedefs.svh @@ -0,0 +1,34 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the host server when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_typedefs_hdl.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_typedefs_hdl.svh new file mode 100644 index 0000000..0d58518 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/src/fuse_ctrl_prim_axi_read_in_typedefs_hdl.svh @@ -0,0 +1,35 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the emulator when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/yaml/fuse_ctrl_prim_axi_read_in_interface.yaml b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/yaml/fuse_ctrl_prim_axi_read_in_interface.yaml new file mode 100644 index 0000000..722b476 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_in_pkg/yaml/fuse_ctrl_prim_axi_read_in_interface.yaml @@ -0,0 +1,121 @@ +uvmf: + interfaces: + fuse_ctrl_prim_axi_read_in: + clock: clk_i + config_constraints: [] + config_vars: [] + existing_library_component: 'True' + gen_inbound_streaming_driver: 'False' + hdl_pkg_parameters: [] + hdl_typedefs: [] + hvl_pkg_parameters: [] + hvl_typedefs: [] + parameters: + - name: AW + type: int + value: '32' + - name: DW + type: int + value: '32' + - name: IW + type: int + value: '3' + - name: UW + type: int + value: '32' + ports: + - dir: output + name: araddr + reset_value: '''bz' + width: '[''AW'']' + - dir: output + name: arburst + reset_value: '''bz' + width: '[''$bits(axi_pkg::axi_burst_e)'']' + - dir: output + name: arsize + reset_value: '''bz' + width: '3' + - dir: output + name: arlen + reset_value: '''bz' + width: '8' + - dir: output + name: aruser + reset_value: '''bz' + width: '[''UW'']' + - dir: output + name: arid + reset_value: '''bz' + width: '[''IW'']' + - dir: output + name: arlock + reset_value: '''bz' + width: '1' + - dir: output + name: arvalid + reset_value: '''bz' + width: '1' + - dir: output + name: rready + reset_value: '''bz' + width: '1' + reset: rst_ni + reset_assertion_level: 'False' + transaction_constraints: [] + transaction_vars: + - comment: '' + iscompare: 'False' + isrand: 'True' + name: prim_araddr + type: logic [AW-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: prim_arvalid + type: logic + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: prim_arburst + type: logic [$bits(axi_pkg::axi_burst_e)] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: prim_arsize + type: logic [2:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: prim_arlen + type: logic [7:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: prim_aruser + type: logic [UW-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: prim_arid + type: logic [IW-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: prim_arlock + type: logic + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: prim_rready + type: logic + unpacked_dimension: '' + use_dpi_link: 'False' diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/.project b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/.project new file mode 100644 index 0000000..a150c26 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/.project @@ -0,0 +1,30 @@ + + + fuse_ctrl_prim_axi_read_out_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/.svproject b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/.svproject new file mode 100644 index 0000000..07283b0 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/Makefile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/Makefile new file mode 100644 index 0000000..c82fb10 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/Makefile @@ -0,0 +1,66 @@ +# fuse_ctrl_prim_axi_read_out interface packages source +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +fuse_ctrl_prim_axi_read_out_PKG = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_read_out_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_filelist_hvl.f + +fuse_ctrl_prim_axi_read_out_PKG_HDL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_read_out_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_filelist_hdl.f + +fuse_ctrl_prim_axi_read_out_PKG_XRTL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_read_out_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_filelist_xrtl.f + +COMP_fuse_ctrl_prim_axi_read_out_PKG_TGT_0 = q_comp_fuse_ctrl_prim_axi_read_out_pkg +COMP_fuse_ctrl_prim_axi_read_out_PKG_TGT_1 = v_comp_fuse_ctrl_prim_axi_read_out_pkg +COMP_fuse_ctrl_prim_axi_read_out_PKG_TGT = $(COMP_fuse_ctrl_prim_axi_read_out_PKG_TGT_$(USE_VELOCE)) + +comp_fuse_ctrl_prim_axi_read_out_pkg: $(COMP_fuse_ctrl_prim_axi_read_out_PKG_TGT) + +q_comp_fuse_ctrl_prim_axi_read_out_pkg: + $(HDL_COMP_CMD) $(fuse_ctrl_prim_axi_read_out_PKG_HDL) + $(HVL_COMP_CMD) $(fuse_ctrl_prim_axi_read_out_PKG) + $(HDL_COMP_CMD) $(fuse_ctrl_prim_axi_read_out_PKG_XRTL) + +v_comp_fuse_ctrl_prim_axi_read_out_pkg: + $(HVL_COMP_CMD) $(fuse_ctrl_prim_axi_read_out_PKG_HDL) + $(HVL_COMP_CMD) $(fuse_ctrl_prim_axi_read_out_PKG) + $(VELANALYZE_CMD) $(fuse_ctrl_prim_axi_read_out_PKG_HDL) + $(VELANALYZE_HVL_CMD) $(fuse_ctrl_prim_axi_read_out_PKG) + $(HDL_COMP_CMD) $(fuse_ctrl_prim_axi_read_out_PKG_XRTL) + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export fuse_ctrl_prim_axi_read_out_IF_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/dpi + +C_FILE_COMPILE_LIST_fuse_ctrl_prim_axi_read_out_pkg = \ + +O_FILE_COMPILE_LIST_fuse_ctrl_prim_axi_read_out_pkg = $(notdir $(C_FILE_COMPILE_LIST_fuse_ctrl_prim_axi_read_out_pkg:.c=.o)) + +GCC_COMP_ARGS_fuse_ctrl_prim_axi_read_out_pkg += -I$(fuse_ctrl_prim_axi_read_out_IF_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_fuse_ctrl_prim_axi_read_out_pkg += $(fuse_ctrl_prim_axi_read_out_IF_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_fuse_ctrl_prim_axi_read_out_pkg += \ + \ + -o .so + +comp_fuse_ctrl_prim_axi_read_out_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Interface C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_fuse_ctrl_prim_axi_read_out_pkg) $(C_FILE_COMPILE_LIST_fuse_ctrl_prim_axi_read_out_pkg) + @echo "--------------------------------" + @echo "Linking Interface C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_fuse_ctrl_prim_axi_read_out_pkg) $(O_FILE_COMPILE_LIST_fuse_ctrl_prim_axi_read_out_pkg) + @echo "--------------------------------" + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/compile.do b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/compile.do new file mode 100644 index 0000000..1f3f425 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/compile.do @@ -0,0 +1,14 @@ +# Tcl do file for compile of fuse_ctrl_prim_axi_read_out interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_read_out_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_filelist_hdl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_read_out_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_filelist_hvl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_read_out_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_filelist_xrtl.f \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out.compile new file mode 100644 index 0000000..3ae619a --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out.compile @@ -0,0 +1,3 @@ +needs: + - fuse_ctrl_prim_axi_read_out_hvl.compile + - fuse_ctrl_prim_axi_read_out_hdl.compile diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_bfm.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_bfm.vinfo new file mode 100644 index 0000000..804bede --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_bfm.vinfo @@ -0,0 +1,6 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use fuse_ctrl_prim_axi_read_out_pkg_hdl.vinfo ++incdir+@vinfodir +src/fuse_ctrl_prim_axi_read_out_if.sv +src/fuse_ctrl_prim_axi_read_out_driver_bfm.sv +src/fuse_ctrl_prim_axi_read_out_monitor_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_common.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_common.compile new file mode 100644 index 0000000..473bd10 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_common.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +incdir: + - . + - ${uvm_path}/src +src: + - fuse_ctrl_prim_axi_read_out_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_filelist_hdl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_filelist_hdl.f new file mode 100644 index 0000000..9915fab --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_filelist_hdl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_filelist_hvl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_filelist_hvl.f new file mode 100644 index 0000000..c105f6a --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_filelist_hvl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_pkg.sv \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_filelist_xrtl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_filelist_xrtl.f new file mode 100644 index 0000000..efd90f5 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_filelist_xrtl.f @@ -0,0 +1,3 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_if.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_monitor_bfm.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_driver_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_hdl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_hdl.compile new file mode 100644 index 0000000..3110b63 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_hdl.compile @@ -0,0 +1,9 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ./fuse_ctrl_prim_axi_read_out_common.compile +incdir: + - . +src: + - src/fuse_ctrl_prim_axi_read_out_if.sv + - src/fuse_ctrl_prim_axi_read_out_monitor_bfm.sv + - src/fuse_ctrl_prim_axi_read_out_driver_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_hvl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_hvl.compile new file mode 100644 index 0000000..5f022ac --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_hvl.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ./fuse_ctrl_prim_axi_read_out_common.compile +incdir: + - . +src: + - fuse_ctrl_prim_axi_read_out_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_pkg.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_pkg.sv new file mode 100644 index 0000000..d12ebea --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_pkg.sv @@ -0,0 +1,91 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - + +// - +// - +// - + +// - +// - +// - + +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_prim_axi_read_out_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg_hdl::*; + import uvmf_base_pkg::*; + import fuse_ctrl_prim_axi_read_out_pkg_hdl::*; + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + `include "src/fuse_ctrl_prim_axi_read_out_macros.svh" + + export fuse_ctrl_prim_axi_read_out_pkg_hdl::*; + + + + // Parameters defined as HVL parameters + + `include "src/fuse_ctrl_prim_axi_read_out_typedefs.svh" + `include "src/fuse_ctrl_prim_axi_read_out_transaction.svh" + + `include "src/fuse_ctrl_prim_axi_read_out_configuration.svh" + `include "src/fuse_ctrl_prim_axi_read_out_driver.svh" + `include "src/fuse_ctrl_prim_axi_read_out_monitor.svh" + + `include "src/fuse_ctrl_prim_axi_read_out_transaction_coverage.svh" + `include "src/fuse_ctrl_prim_axi_read_out_sequence_base.svh" + `include "src/fuse_ctrl_prim_axi_read_out_random_sequence.svh" + + `include "src/fuse_ctrl_prim_axi_read_out_responder_sequence.svh" + `include "src/fuse_ctrl_prim_axi_read_out2reg_adapter.svh" + + `include "src/fuse_ctrl_prim_axi_read_out_agent.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new interface sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the interface package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_pkg.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_pkg.vinfo new file mode 100644 index 0000000..ce44bd3 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_pkg.vinfo @@ -0,0 +1,4 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use fuse_ctrl_prim_axi_read_out_pkg_hdl.vinfo ++incdir+@vinfodir +fuse_ctrl_prim_axi_read_out_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_pkg_hdl.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_pkg_hdl.sv new file mode 100644 index 0000000..3a6641b --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_pkg_hdl.sv @@ -0,0 +1,52 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that needs to be compiled and synthesized +// for running on Veloce. +// +// CONTAINS: +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_prim_axi_read_out_pkg_hdl; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HDL parameters + + `include "src/fuse_ctrl_prim_axi_read_out_typedefs_hdl.svh" + `include "src/fuse_ctrl_prim_axi_read_out_macros.svh" + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_pkg_hdl.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_pkg_hdl.vinfo new file mode 100644 index 0000000..d2706f6 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_pkg_hdl.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +fuse_ctrl_prim_axi_read_out_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_pkg_sve.F b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_pkg_sve.F new file mode 100644 index 0000000..e27a449 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_pkg_sve.F @@ -0,0 +1,10 @@ +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + ++incdir+. +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_filelist_hdl.f +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/fuse_ctrl_prim_axi_read_out_filelist_hvl.f diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out2reg_adapter.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out2reg_adapter.svh new file mode 100644 index 0000000..6d0791b --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out2reg_adapter.svh @@ -0,0 +1,142 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the UVM register adapter for the fuse_ctrl_prim_axi_read_out interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_read_out2reg_adapter #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvm_reg_adapter; + + `uvm_object_param_utils( fuse_ctrl_prim_axi_read_out2reg_adapter #( + AW, + DW, + IW, + UW + ) +) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //-------------------------------------------------------------------- + // new + //-------------------------------------------------------------------- + function new (string name = "fuse_ctrl_prim_axi_read_out2reg_adapter" ); + super.new(name); + // pragma uvmf custom new begin + // UVMF_CHANGE_ME : Configure the adapter regarding byte enables and provides response. + + // Does the protocol the Agent is modeling support byte enables? + // 0 = NO + // 1 = YES + supports_byte_enable = 0; + + // Does the Agent's Driver provide separate response sequence items? + // i.e. Does the driver call seq_item_port.put() + // and do the sequences call get_response()? + // 0 = NO + // 1 = YES + provides_responses = 0; + // pragma uvmf custom new end + + endfunction: new + + //-------------------------------------------------------------------- + // reg2bus + //-------------------------------------------------------------------- + virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw); + + fuse_ctrl_prim_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + trans_h = fuse_ctrl_prim_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +::type_id::create("trans_h"); + + // pragma uvmf custom reg2bus begin + // UVMF_CHANGE_ME : Fill in the reg2bus adapter mapping registe fields to protocol fields. + + //Adapt the following for your sequence item type + // trans_h.op = (rw.kind == UVM_READ) ? WB_READ : WB_WRITE; + //Copy over address + // trans_h.addr = rw.addr; + //Copy over write data + // trans_h.data = rw.data; + + // pragma uvmf custom reg2bus end + + // Return the adapted transaction + return trans_h; + + endfunction: reg2bus + + //-------------------------------------------------------------------- + // bus2reg + //-------------------------------------------------------------------- + virtual function void bus2reg(uvm_sequence_item bus_item, + ref uvm_reg_bus_op rw); + fuse_ctrl_prim_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + trans_h; + if (!$cast(trans_h, bus_item)) begin + `uvm_fatal("ADAPT","Provided bus_item is not of the correct type") + return; + end + // pragma uvmf custom bus2reg begin + // UVMF_CHANGE_ME : Fill in the bus2reg adapter mapping protocol fields to register fields. + //Adapt the following for your sequence item type + //Copy over instruction type + // rw.kind = (trans_h.op == WB_WRITE) ? UVM_WRITE : UVM_READ; + //Copy over address + // rw.addr = trans_h.addr; + //Copy over read data + // rw.data = trans_h.data; + //Check for errors on the bus and return UVM_NOT_OK if there is an error + // rw.status = UVM_IS_OK; + // pragma uvmf custom bus2reg end + + endfunction: bus2reg + +endclass : fuse_ctrl_prim_axi_read_out2reg_adapter + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_agent.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_agent.svh new file mode 100644 index 0000000..4ecac4a --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_agent.svh @@ -0,0 +1,109 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: Protocol specific agent class definition +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_read_out_agent #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvmf_parameterized_agent #( + .CONFIG_T(fuse_ctrl_prim_axi_read_out_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .DRIVER_T(fuse_ctrl_prim_axi_read_out_driver #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .MONITOR_T(fuse_ctrl_prim_axi_read_out_monitor #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .COVERAGE_T(fuse_ctrl_prim_axi_read_out_transaction_coverage #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .TRANS_T(fuse_ctrl_prim_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +) + ); + + `uvm_component_param_utils( fuse_ctrl_prim_axi_read_out_agent #( + AW, + DW, + IW, + UW + ) +) + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** + // FUNCTION: build_phase + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + if (configuration.active_passive == ACTIVE) begin + // Place sequencer handle into configuration object + // so that it may be retrieved from configuration + // rather than using uvm_config_db + configuration.sequencer = this.sequencer; + end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_configuration.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_configuration.svh new file mode 100644 index 0000000..04a822d --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_configuration.svh @@ -0,0 +1,241 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class contains all variables and functions used +// to configure the fuse_ctrl_prim_axi_read_out agent and its bfm's. It gets the +// bfm's from the uvm_config_db for use by the agent. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_read_out_configuration #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvmf_parameterized_agent_configuration_base #( + .DRIVER_BFM_BIND_T(virtual fuse_ctrl_prim_axi_read_out_driver_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .MONITOR_BFM_BIND_T( virtual fuse_ctrl_prim_axi_read_out_monitor_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +)); + + `uvm_object_param_utils( fuse_ctrl_prim_axi_read_out_configuration #( + AW, + DW, + IW, + UW + ) +) + + + // Sequencer handle populated by agent + uvm_sequencer #(fuse_ctrl_prim_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + ) sequencer; + + //Constraints for the configuration variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + covergroup fuse_ctrl_prim_axi_read_out_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + // pragma uvmf custom covergroup end + endgroup + + //******************************************************************* + //******************************************************************* + // Structure used to pass configuration variables to monitor and driver BFM's. + // Use to_struct function to pack variables into structure. + // Use from_struct function to unpack variables from structure. + // This structure is defined in fuse_ctrl_prim_axi_read_out_macros.svh + `fuse_ctrl_prim_axi_read_out_CONFIGURATION_STRUCT + fuse_ctrl_prim_axi_read_out_configuration_s fuse_ctrl_prim_axi_read_out_configuration_struct; + //******************************************************************* + // FUNCTION: to_struct() + // This function packs variables into a fuse_ctrl_prim_axi_read_out_configuration_s + // structure. The function returns the handle to the fuse_ctrl_prim_axi_read_out_configuration_struct. + // This function is defined in fuse_ctrl_prim_axi_read_out_macros.svh + `fuse_ctrl_prim_axi_read_out_CONFIGURATION_TO_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_struct() + // This function unpacks the struct provided as an argument into + // variables of this class. + // This function is defined in fuse_ctrl_prim_axi_read_out_macros.svh + `fuse_ctrl_prim_axi_read_out_CONFIGURATION_FROM_STRUCT_FUNCTION + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + // Construct the covergroup for this configuration class + fuse_ctrl_prim_axi_read_out_configuration_cg = new; + endfunction + + // **************************************************************************** + // FUNCTION: post_randomize() + // This function is automatically called after the randomize() function + // is executed. + // + function void post_randomize(); + super.post_randomize(); + fuse_ctrl_prim_axi_read_out_configuration_cg.sample(); + endfunction + + // **************************************************************************** + // FUNCTION: initialize + // This function causes the configuration to retrieve + // its virtual interface handle from the uvm_config_db. + // This function also makes itself available to its + // agent through the uvm_config_db. + // + // ARGUMENTS: + // uvmf_active_passive_t activity: + // This argument identifies the simulation level + // as either BLOCK, CHIP, SIMULATION, etc. + // + // AGENT_PATH: + // This argument identifies the path to this + // configurations agent. This configuration + // makes itself available to the agent specified + // by agent_path by placing itself into the + // uvm_config_db. + // + // INTERFACE_NAME: + // This argument identifies the string name of + // this configurations BFM's. This string + // name is used to retrieve the driver and + // monitor BFM from the uvm_config_db. + // + virtual function void initialize(uvmf_active_passive_t activity, + string agent_path, + string interface_name); + + super.initialize( activity, agent_path, interface_name); + // The covergroup is given the same name as the interface + fuse_ctrl_prim_axi_read_out_configuration_cg.set_inst_name(interface_name); + + // This configuration places itself into the uvm_config_db for the agent, identified by the agent_path variable, to retrieve. + uvm_config_db #( fuse_ctrl_prim_axi_read_out_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + + )::set( null ,agent_path,UVMF_AGENT_CONFIG, this ); + + // This configuration also places itself in the config db using the same identifier used by the interface. This allows users to access + // configuration variables and the interface through the bfm api class rather than directly accessing the BFM. This is useful for + // accessingthe BFM when using Veloce + uvm_config_db #( fuse_ctrl_prim_axi_read_out_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + + )::set( null ,UVMF_CONFIGURATIONS, interface_name, this ); + + fuse_ctrl_prim_axi_read_out_configuration_cg.set_inst_name($sformatf("fuse_ctrl_prim_axi_read_out_configuration_cg_%s",get_full_name())); + +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. + `uvm_info("CFG", + $psprintf("The agent at '%s' is using interface named %s has the following parameters: AW=%x DW=%x IW=%x UW=%x ", agent_path, interface_name, AW ,DW ,IW ,UW ), + UVM_DEBUG) + + // pragma uvmf custom initialize begin + // This controls whether or not the agent returns a transaction handle in the driver when calling + // item_done() back into the sequencer or not. If set to 1, a transaction is sent back which means + // the sequence on the other end must use the get_response() part of the driver/sequence API. If + // this doesn't occur, there will eventually be response_queue overflow errors during the test. + return_transaction_response = 1'b0; + + // pragma uvmf custom initialize end + + endfunction + + // **************************************************************************** + // TASK: wait_for_reset + // *[Required]* Blocks until reset is released. The wait_for_reset operation is performed + // by a task in the monitor bfm. + virtual task wait_for_reset(); + monitor_bfm.wait_for_reset(); + endtask + + // **************************************************************************** + // TASK: wait_for_num_clocks + // *[Required]* Blocks until specified number of clocks have elapsed. The wait_for_num_clocks + // operation is performed by a task in the monitor bfm. + virtual task wait_for_num_clocks(int clocks); + monitor_bfm.wait_for_num_clocks(clocks); + endtask + + // **************************************************************************** + // FUNCTION : convert2string() + // This function is used to convert variables in this class into a string for log messaging. + // + virtual function string convert2string (); + // pragma uvmf custom convert2string begin + return $sformatf(""); + // pragma uvmf custom convert2string end + endfunction + + // **************************************************************************** + // FUNCTION: get_sequencer + function uvm_sequencer #(fuse_ctrl_prim_axi_read_out_transaction#( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +) get_sequencer(); + return sequencer; + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_driver.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_driver.svh new file mode 100644 index 0000000..706e007 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_driver.svh @@ -0,0 +1,141 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class passes transactions between the sequencer +// and the BFM driver interface. It accesses the driver BFM +// through the bfm handle. This driver +// passes transactions to the driver BFM through the access +// task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_read_out_driver #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvmf_driver_base #( + .CONFIG_T(fuse_ctrl_prim_axi_read_out_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + ), + .BFM_BIND_T(virtual fuse_ctrl_prim_axi_read_out_driver_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + ), + .REQ(fuse_ctrl_prim_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + ), + .RSP(fuse_ctrl_prim_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + )); + + `uvm_component_param_utils( fuse_ctrl_prim_axi_read_out_driver #( + AW, + DW, + IW, + UW + ) +) +//******************************************************************* +// Macros that define structs located in fuse_ctrl_prim_axi_read_out_macros.svh +//******************************************************************* +// Initiator macro used by fuse_ctrl_prim_axi_read_out_driver and fuse_ctrl_prim_axi_read_out_driver_bfm +// to communicate initiator driven data to fuse_ctrl_prim_axi_read_out_driver_bfm. +`fuse_ctrl_prim_axi_read_out_INITIATOR_STRUCT + fuse_ctrl_prim_axi_read_out_initiator_s fuse_ctrl_prim_axi_read_out_initiator_struct; +//******************************************************************* +// Responder macro used by fuse_ctrl_prim_axi_read_out_driver and fuse_ctrl_prim_axi_read_out_driver_bfm +// to communicate Responder driven data to fuse_ctrl_prim_axi_read_out_driver_bfm. +`fuse_ctrl_prim_axi_read_out_RESPONDER_STRUCT + fuse_ctrl_prim_axi_read_out_responder_s fuse_ctrl_prim_axi_read_out_responder_struct; + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent=null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the driver BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// driver BFM. This allows the driver BFM to call tasks and function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// **************************************************************************** +// This task is called by the run_phase in uvmf_driver_base. + virtual task access( inout REQ txn ); +// pragma uvmf custom access begin + if (configuration.initiator_responder==RESPONDER) begin + // Complete current transfer and wait for next transfer + bfm.respond_and_wait_for_next_transfer( + fuse_ctrl_prim_axi_read_out_initiator_struct, + txn.to_responder_struct() + ); + // Unpack information about initiated transfer received by this responder + txn.from_initiator_struct(fuse_ctrl_prim_axi_read_out_initiator_struct); + end else begin + // Initiate a transfer and get response + bfm.initiate_and_get_response( + txn.to_initiator_struct(), + fuse_ctrl_prim_axi_read_out_responder_struct + ); + // Unpack transfer response information received by this initiator + txn.from_responder_struct(fuse_ctrl_prim_axi_read_out_responder_struct); + end +// pragma uvmf custom access end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_driver_bfm.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_driver_bfm.sv new file mode 100644 index 0000000..f23f7c6 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_driver_bfm.sv @@ -0,0 +1,352 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This interface performs the fuse_ctrl_prim_axi_read_out signal driving. It is +// accessed by the uvm fuse_ctrl_prim_axi_read_out driver through a virtual interface +// handle in the fuse_ctrl_prim_axi_read_out configuration. It drives the singals passed +// in through the port connection named bus of type fuse_ctrl_prim_axi_read_out_if. +// +// Input signals from the fuse_ctrl_prim_axi_read_out_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// This bfm drives signals with a _o suffix. These signals +// are driven onto signals within fuse_ctrl_prim_axi_read_out_if based on INITIATOR/RESPONDER and/or +// ARBITRATION/GRANT status. +// +// The output signal connections are as follows: +// signal_o -> bus.signal +// +// +// Interface functions and tasks used by UVM components: +// +// configure: +// This function gets configuration attributes from the +// UVM driver to set any required BFM configuration +// variables such as 'initiator_responder'. +// +// initiate_and_get_response: +// This task is used to perform signaling activity for initiating +// a protocol transfer. The task initiates the transfer, using +// input data from the initiator struct. Then the task captures +// response data, placing the data into the response struct. +// The response struct is returned to the driver class. +// +// respond_and_wait_for_next_transfer: +// This task is used to complete a current transfer as a responder +// and then wait for the initiator to start the next transfer. +// The task uses data in the responder struct to drive protocol +// signals to complete the transfer. The task then waits for +// the next transfer. Once the next transfer begins, data from +// the initiator is placed into the initiator struct and sent +// to the responder sequence for processing to determine +// what data to respond with. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_prim_axi_read_out_pkg_hdl::*; +`include "src/fuse_ctrl_prim_axi_read_out_macros.svh" + +interface fuse_ctrl_prim_axi_read_out_driver_bfm #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + + (fuse_ctrl_prim_axi_read_out_if bus); + // The following pragma and additional ones in-lined further below are for running this BFM on Veloce + // pragma attribute fuse_ctrl_prim_axi_read_out_driver_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: AW=%x DW=%x IW=%x UW=%x ", AW,DW,IW,UW), + UVM_DEBUG) +end +`endif + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + tri clk_i_i; + tri rst_ni_i; + + // Signal list (all signals are capable of being inputs and outputs for the sake + // of supporting both INITIATOR and RESPONDER mode operation. Expectation is that + // directionality in the config file was from the point-of-view of the INITIATOR + + // INITIATOR mode input signals + tri arready_i; + reg arready_o = 'bz; + tri [DW-1:0] rdata_i; + reg [DW-1:0] rdata_o = 'bz; + tri rresp_i; + reg rresp_o = 'bz; + tri rid_i; + reg rid_o = 'bz; + tri rlast_i; + reg rlast_o = 'bz; + tri rvalid_i; + reg rvalid_o = 'bz; + + // INITIATOR mode output signals + + // Bi-directional signals + + + assign clk_i_i = bus.clk_i; + assign rst_ni_i = bus.rst_ni; + + // These are signals marked as 'input' by the config file, but the signals will be + // driven by this BFM if put into RESPONDER mode (flipping all signal directions around) + assign arready_i = bus.arready; + assign bus.arready = (initiator_responder == RESPONDER) ? arready_o : 'bz; + assign rdata_i = bus.rdata; + assign bus.rdata = (initiator_responder == RESPONDER) ? rdata_o : 'bz; + assign rresp_i = bus.rresp; + assign bus.rresp = (initiator_responder == RESPONDER) ? rresp_o : 'bz; + assign rid_i = bus.rid; + assign bus.rid = (initiator_responder == RESPONDER) ? rid_o : 'bz; + assign rlast_i = bus.rlast; + assign bus.rlast = (initiator_responder == RESPONDER) ? rlast_o : 'bz; + assign rvalid_i = bus.rvalid; + assign bus.rvalid = (initiator_responder == RESPONDER) ? rvalid_o : 'bz; + + + // These are signals marked as 'output' by the config file, but the outputs will + // not be driven by this BFM unless placed in INITIATOR mode. + + // Proxy handle to UVM driver + fuse_ctrl_prim_axi_read_out_pkg::fuse_ctrl_prim_axi_read_out_driver #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + proxy; + // pragma tbx oneway proxy.my_function_name_in_uvm_driver + + // **************************************************************************** + // **************************************************************************** + // Macros that define structs located in fuse_ctrl_prim_axi_read_out_macros.svh + // **************************************************************************** + // Struct for passing configuration data from fuse_ctrl_prim_axi_read_out_driver to this BFM + // **************************************************************************** + `fuse_ctrl_prim_axi_read_out_CONFIGURATION_STRUCT + // **************************************************************************** + // Structs for INITIATOR and RESPONDER data flow + //******************************************************************* + // Initiator macro used by fuse_ctrl_prim_axi_read_out_driver and fuse_ctrl_prim_axi_read_out_driver_bfm + // to communicate initiator driven data to fuse_ctrl_prim_axi_read_out_driver_bfm. + `fuse_ctrl_prim_axi_read_out_INITIATOR_STRUCT + fuse_ctrl_prim_axi_read_out_initiator_s initiator_struct; + // Responder macro used by fuse_ctrl_prim_axi_read_out_driver and fuse_ctrl_prim_axi_read_out_driver_bfm + // to communicate Responder driven data to fuse_ctrl_prim_axi_read_out_driver_bfm. + `fuse_ctrl_prim_axi_read_out_RESPONDER_STRUCT + fuse_ctrl_prim_axi_read_out_responder_s responder_struct; + + // **************************************************************************** +// pragma uvmf custom reset_condition_and_response begin + // Always block used to return signals to reset value upon assertion of reset + always @( negedge rst_ni_i ) + begin + // RESPONDER mode output signals + arready_o <= 'bz; + rdata_o <= 'bz; + rresp_o <= 'bz; + rid_o <= 'bz; + rlast_o <= 'bz; + rvalid_o <= 'bz; + // INITIATOR mode output signals + // Bi-directional signals + + end +// pragma uvmf custom reset_condition_and_response end + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the driver BFM. It is called by the driver within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the driver BFM needs to be aware of the new configuration + // variables. + // + + function void configure(fuse_ctrl_prim_axi_read_out_configuration_s fuse_ctrl_prim_axi_read_out_configuration_arg); // pragma tbx xtf + initiator_responder = fuse_ctrl_prim_axi_read_out_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + +// pragma uvmf custom initiate_and_get_response begin +// **************************************************************************** +// UVMF_CHANGE_ME +// This task is used by an initator. The task first initiates a transfer then +// waits for the responder to complete the transfer. + task initiate_and_get_response( + // This argument passes transaction variables used by an initiator + // to perform the initial part of a protocol transfer. The values + // come from a sequence item created in a sequence. + input fuse_ctrl_prim_axi_read_out_initiator_s fuse_ctrl_prim_axi_read_out_initiator_struct, + // This argument is used to send data received from the responder + // back to the sequence item. The sequence item is returned to the sequence. + output fuse_ctrl_prim_axi_read_out_responder_s fuse_ctrl_prim_axi_read_out_responder_struct + );// pragma tbx xtf + // + // Members within the fuse_ctrl_prim_axi_read_out_initiator_struct: + // logic prim_arready ; + // logic [DW-1:0] prim_rdata ; + // axi_pkg::axi_burst_e prim_rresp ; + // logic [IW-1:0] prim_rid ; + // logic prim_rlast ; + // logic prim_rvalid ; + // Members within the fuse_ctrl_prim_axi_read_out_responder_struct: + // logic prim_arready ; + // logic [DW-1:0] prim_rdata ; + // axi_pkg::axi_burst_e prim_rresp ; + // logic [IW-1:0] prim_rid ; + // logic prim_rlast ; + // logic prim_rvalid ; + initiator_struct = fuse_ctrl_prim_axi_read_out_initiator_struct; + // + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clk_i_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available initiator input and inout signals listed. + // Initiator input signals + // fuse_ctrl_prim_axi_read_out_responder_struct.xyz = arready_i; // + // fuse_ctrl_prim_axi_read_out_responder_struct.xyz = rdata_i; // [DW-1:0] + // fuse_ctrl_prim_axi_read_out_responder_struct.xyz = rresp_i; // + // fuse_ctrl_prim_axi_read_out_responder_struct.xyz = rid_i; // + // fuse_ctrl_prim_axi_read_out_responder_struct.xyz = rlast_i; // + // fuse_ctrl_prim_axi_read_out_responder_struct.xyz = rvalid_i; // + // Initiator inout signals + // How to assign a signal from an initiator struct member named xyz. + // All available initiator output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Initiator output signals + // Initiator inout signals + // Initiate a transfer using the data received. + @(posedge clk_i_i); + @(posedge clk_i_i); + // Wait for the responder to complete the transfer then place the responder data into + // fuse_ctrl_prim_axi_read_out_responder_struct. + @(posedge clk_i_i); + @(posedge clk_i_i); + responder_struct = fuse_ctrl_prim_axi_read_out_responder_struct; + endtask +// pragma uvmf custom initiate_and_get_response end + +// pragma uvmf custom respond_and_wait_for_next_transfer begin +// **************************************************************************** +// The first_transfer variable is used to prevent completing a transfer in the +// first call to this task. For the first call to this task, there is not +// current transfer to complete. +bit first_transfer=1; + +// UVMF_CHANGE_ME +// This task is used by a responder. The task first completes the current +// transfer in progress then waits for the initiator to start the next transfer. + task respond_and_wait_for_next_transfer( + // This argument is used to send data received from the initiator + // back to the sequence item. The sequence determines how to respond. + output fuse_ctrl_prim_axi_read_out_initiator_s fuse_ctrl_prim_axi_read_out_initiator_struct, + // This argument passes transaction variables used by a responder + // to complete a protocol transfer. The values come from a sequence item. + input fuse_ctrl_prim_axi_read_out_responder_s fuse_ctrl_prim_axi_read_out_responder_struct + );// pragma tbx xtf + // Variables within the fuse_ctrl_prim_axi_read_out_initiator_struct: + // logic prim_arready ; + // logic [DW-1:0] prim_rdata ; + // axi_pkg::axi_burst_e prim_rresp ; + // logic [IW-1:0] prim_rid ; + // logic prim_rlast ; + // logic prim_rvalid ; + // Variables within the fuse_ctrl_prim_axi_read_out_responder_struct: + // logic prim_arready ; + // logic [DW-1:0] prim_rdata ; + // axi_pkg::axi_burst_e prim_rresp ; + // logic [IW-1:0] prim_rid ; + // logic prim_rlast ; + // logic prim_rvalid ; + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clk_i_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available responder input and inout signals listed. + // Responder input signals + // Responder inout signals + // How to assign a signal, named xyz, from an initiator struct member. + // All available responder output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Responder output signals + // arready_o <= fuse_ctrl_prim_axi_read_out_initiator_struct.xyz; // + // rdata_o <= fuse_ctrl_prim_axi_read_out_initiator_struct.xyz; // [DW-1:0] + // rresp_o <= fuse_ctrl_prim_axi_read_out_initiator_struct.xyz; // + // rid_o <= fuse_ctrl_prim_axi_read_out_initiator_struct.xyz; // + // rlast_o <= fuse_ctrl_prim_axi_read_out_initiator_struct.xyz; // + // rvalid_o <= fuse_ctrl_prim_axi_read_out_initiator_struct.xyz; // + // Responder inout signals + + @(posedge clk_i_i); + if (!first_transfer) begin + // Perform transfer response here. + // Reply using data recieved in the fuse_ctrl_prim_axi_read_out_responder_struct. + @(posedge clk_i_i); + // Reply using data recieved in the transaction handle. + @(posedge clk_i_i); + end + // Wait for next transfer then gather info from intiator about the transfer. + // Place the data into the fuse_ctrl_prim_axi_read_out_initiator_struct. + @(posedge clk_i_i); + @(posedge clk_i_i); + first_transfer = 0; + endtask +// pragma uvmf custom respond_and_wait_for_next_transfer end + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_if.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_if.sv new file mode 100644 index 0000000..1f59430 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_if.sv @@ -0,0 +1,109 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface contains the fuse_ctrl_prim_axi_read_out interface signals. +// It is instantiated once per fuse_ctrl_prim_axi_read_out bus. Bus Functional Models, +// BFM's named fuse_ctrl_prim_axi_read_out_driver_bfm, are used to drive signals on the bus. +// BFM's named fuse_ctrl_prim_axi_read_out_monitor_bfm are used to monitor signals on the +// bus. This interface signal bundle is passed in the port list of +// the BFM in order to give the BFM access to the signals in this +// interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// This template can be used to connect a DUT to these signals +// +// .dut_signal_port(fuse_ctrl_prim_axi_read_out_bus.arready), // Agent input +// .dut_signal_port(fuse_ctrl_prim_axi_read_out_bus.rdata), // Agent input +// .dut_signal_port(fuse_ctrl_prim_axi_read_out_bus.rresp), // Agent input +// .dut_signal_port(fuse_ctrl_prim_axi_read_out_bus.rid), // Agent input +// .dut_signal_port(fuse_ctrl_prim_axi_read_out_bus.rlast), // Agent input +// .dut_signal_port(fuse_ctrl_prim_axi_read_out_bus.rvalid), // Agent input + +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_prim_axi_read_out_pkg_hdl::*; + +interface fuse_ctrl_prim_axi_read_out_if #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + + + ( + input tri clk_i, + input tri rst_ni, + inout tri arready, + inout tri [DW-1:0] rdata, + inout tri rresp, + inout tri rid, + inout tri rlast, + inout tri rvalid + ); + +modport monitor_port + ( + input clk_i, + input rst_ni, + input arready, + input rdata, + input rresp, + input rid, + input rlast, + input rvalid + ); + +modport initiator_port + ( + input clk_i, + input rst_ni, + input arready, + input rdata, + input rresp, + input rid, + input rlast, + input rvalid + ); + +modport responder_port + ( + input clk_i, + input rst_ni, + output arready, + output rdata, + output rresp, + output rid, + output rlast, + output rvalid + ); + + +// pragma uvmf custom interface_item_additional begin +// pragma uvmf custom interface_item_additional end + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_infact_coverage_strategy.csv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_infact_coverage_strategy.csv new file mode 100644 index 0000000..1c218e1 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_infact_coverage_strategy.csv @@ -0,0 +1,6 @@ +Global +auto_bin_max, 64 + +Name,Type,Include +rand_fields,coverpoint,=rand *.** + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_macros.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_macros.svh new file mode 100644 index 0000000..a5d9e29 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_macros.svh @@ -0,0 +1,180 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains macros used with the fuse_ctrl_prim_axi_read_out package. +// These macros include packed struct definitions. These structs are +// used to pass data between classes, hvl, and BFM's, hdl. Use of +// structs are more efficient and simpler to modify. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_struct +// and from_struct methods defined in the macros below that are used in +// the fuse_ctrl_prim_axi_read_out_configuration class. +// + `define fuse_ctrl_prim_axi_read_out_CONFIGURATION_STRUCT \ +typedef struct packed { \ + uvmf_active_passive_t active_passive; \ + uvmf_initiator_responder_t initiator_responder; \ + } fuse_ctrl_prim_axi_read_out_configuration_s; + + `define fuse_ctrl_prim_axi_read_out_CONFIGURATION_TO_STRUCT_FUNCTION \ + virtual function fuse_ctrl_prim_axi_read_out_configuration_s to_struct();\ + fuse_ctrl_prim_axi_read_out_configuration_struct = \ + {\ + this.active_passive,\ + this.initiator_responder\ + };\ + return ( fuse_ctrl_prim_axi_read_out_configuration_struct );\ + endfunction + + `define fuse_ctrl_prim_axi_read_out_CONFIGURATION_FROM_STRUCT_FUNCTION \ + virtual function void from_struct(fuse_ctrl_prim_axi_read_out_configuration_s fuse_ctrl_prim_axi_read_out_configuration_struct);\ + {\ + this.active_passive,\ + this.initiator_responder \ + } = fuse_ctrl_prim_axi_read_out_configuration_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_monitor_struct +// and from_monitor_struct methods of the fuse_ctrl_prim_axi_read_out_transaction class. +// + `define fuse_ctrl_prim_axi_read_out_MONITOR_STRUCT typedef struct packed { \ + logic prim_arready ; \ + logic [DW-1:0] prim_rdata ; \ + axi_pkg::axi_burst_e prim_rresp ; \ + logic [IW-1:0] prim_rid ; \ + logic prim_rlast ; \ + logic prim_rvalid ; \ + } fuse_ctrl_prim_axi_read_out_monitor_s; + + `define fuse_ctrl_prim_axi_read_out_TO_MONITOR_STRUCT_FUNCTION \ + virtual function fuse_ctrl_prim_axi_read_out_monitor_s to_monitor_struct();\ + fuse_ctrl_prim_axi_read_out_monitor_struct = \ + { \ + this.prim_arready , \ + this.prim_rdata , \ + this.prim_rresp , \ + this.prim_rid , \ + this.prim_rlast , \ + this.prim_rvalid \ + };\ + return ( fuse_ctrl_prim_axi_read_out_monitor_struct);\ + endfunction\ + + `define fuse_ctrl_prim_axi_read_out_FROM_MONITOR_STRUCT_FUNCTION \ + virtual function void from_monitor_struct(fuse_ctrl_prim_axi_read_out_monitor_s fuse_ctrl_prim_axi_read_out_monitor_struct);\ + {\ + this.prim_arready , \ + this.prim_rdata , \ + this.prim_rresp , \ + this.prim_rid , \ + this.prim_rlast , \ + this.prim_rvalid \ + } = fuse_ctrl_prim_axi_read_out_monitor_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_initiator_struct +// and from_initiator_struct methods of the fuse_ctrl_prim_axi_read_out_transaction class. +// Also update the comments in the driver BFM. +// + `define fuse_ctrl_prim_axi_read_out_INITIATOR_STRUCT typedef struct packed { \ + logic prim_arready ; \ + logic [DW-1:0] prim_rdata ; \ + axi_pkg::axi_burst_e prim_rresp ; \ + logic [IW-1:0] prim_rid ; \ + logic prim_rlast ; \ + logic prim_rvalid ; \ + } fuse_ctrl_prim_axi_read_out_initiator_s; + + `define fuse_ctrl_prim_axi_read_out_TO_INITIATOR_STRUCT_FUNCTION \ + virtual function fuse_ctrl_prim_axi_read_out_initiator_s to_initiator_struct();\ + fuse_ctrl_prim_axi_read_out_initiator_struct = \ + {\ + this.prim_arready , \ + this.prim_rdata , \ + this.prim_rresp , \ + this.prim_rid , \ + this.prim_rlast , \ + this.prim_rvalid \ + };\ + return ( fuse_ctrl_prim_axi_read_out_initiator_struct);\ + endfunction + + `define fuse_ctrl_prim_axi_read_out_FROM_INITIATOR_STRUCT_FUNCTION \ + virtual function void from_initiator_struct(fuse_ctrl_prim_axi_read_out_initiator_s fuse_ctrl_prim_axi_read_out_initiator_struct);\ + {\ + this.prim_arready , \ + this.prim_rdata , \ + this.prim_rresp , \ + this.prim_rid , \ + this.prim_rlast , \ + this.prim_rvalid \ + } = fuse_ctrl_prim_axi_read_out_initiator_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_responder_struct +// and from_responder_struct methods of the fuse_ctrl_prim_axi_read_out_transaction class. +// Also update the comments in the driver BFM. +// + `define fuse_ctrl_prim_axi_read_out_RESPONDER_STRUCT typedef struct packed { \ + logic prim_arready ; \ + logic [DW-1:0] prim_rdata ; \ + axi_pkg::axi_burst_e prim_rresp ; \ + logic [IW-1:0] prim_rid ; \ + logic prim_rlast ; \ + logic prim_rvalid ; \ + } fuse_ctrl_prim_axi_read_out_responder_s; + + `define fuse_ctrl_prim_axi_read_out_TO_RESPONDER_STRUCT_FUNCTION \ + virtual function fuse_ctrl_prim_axi_read_out_responder_s to_responder_struct();\ + fuse_ctrl_prim_axi_read_out_responder_struct = \ + {\ + this.prim_arready , \ + this.prim_rdata , \ + this.prim_rresp , \ + this.prim_rid , \ + this.prim_rlast , \ + this.prim_rvalid \ + };\ + return ( fuse_ctrl_prim_axi_read_out_responder_struct);\ + endfunction + + `define fuse_ctrl_prim_axi_read_out_FROM_RESPONDER_STRUCT_FUNCTION \ + virtual function void from_responder_struct(fuse_ctrl_prim_axi_read_out_responder_s fuse_ctrl_prim_axi_read_out_responder_struct);\ + {\ + this.prim_arready , \ + this.prim_rdata , \ + this.prim_rresp , \ + this.prim_rid , \ + this.prim_rlast , \ + this.prim_rvalid \ + } = fuse_ctrl_prim_axi_read_out_responder_struct;\ + endfunction +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_monitor.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_monitor.svh new file mode 100644 index 0000000..a47648e --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_monitor.svh @@ -0,0 +1,131 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class receives fuse_ctrl_prim_axi_read_out transactions observed by the +// fuse_ctrl_prim_axi_read_out monitor BFM and broadcasts them through the analysis port +// on the agent. It accesses the monitor BFM through the monitor +// task. This UVM component captures transactions +// for viewing in the waveform viewer if the +// enable_transaction_viewing flag is set in the configuration. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_read_out_monitor #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvmf_monitor_base #( + .CONFIG_T(fuse_ctrl_prim_axi_read_out_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .BFM_BIND_T(virtual fuse_ctrl_prim_axi_read_out_monitor_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .TRANS_T(fuse_ctrl_prim_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +)); + + `uvm_component_param_utils( fuse_ctrl_prim_axi_read_out_monitor #( + AW, + DW, + IW, + UW + ) +) + +// Structure used to pass data from monitor BFM to monitor class in agent. +// Use to_monitor_struct function to pack transaction variables into structure. +// Use from_monitor_struct function to unpack transaction variables from structure. +`fuse_ctrl_prim_axi_read_out_MONITOR_STRUCT + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the monitor BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// monitor BFM. This allows the monitor BFM to call the notify_transaction +// function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// *************************************************************************** + virtual task run_phase(uvm_phase phase); + // Start monitor BFM thread and don't call super.run() in order to + // override the default monitor proxy 'pull' behavior with the more + // emulation-friendly BFM 'push' approach using the notify_transaction + // function below + bfm.start_monitoring(); + endtask + +// ************************************************************************** + +// This function is called by the monitor BFM. It receives data observed by the +// monitor BFM. Data is passed using the fuse_ctrl_prim_axi_read_out_monitor_struct. + virtual function void notify_transaction(input fuse_ctrl_prim_axi_read_out_monitor_s fuse_ctrl_prim_axi_read_out_monitor_struct); + + + trans = new("trans"); + trans.from_monitor_struct(fuse_ctrl_prim_axi_read_out_monitor_struct); + trans.start_time = time_stamp; + trans.end_time = $time; + time_stamp = trans.end_time; + + analyze(trans); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_monitor_bfm.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_monitor_bfm.sv new file mode 100644 index 0000000..8aae56b --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_monitor_bfm.sv @@ -0,0 +1,220 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface performs the fuse_ctrl_prim_axi_read_out signal monitoring. +// It is accessed by the uvm fuse_ctrl_prim_axi_read_out monitor through a virtual +// interface handle in the fuse_ctrl_prim_axi_read_out configuration. It monitors the +// signals passed in through the port connection named bus of +// type fuse_ctrl_prim_axi_read_out_if. +// +// Input signals from the fuse_ctrl_prim_axi_read_out_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// Interface functions and tasks used by UVM components: +// monitor(inout TRANS_T txn); +// This task receives the transaction, txn, from the +// UVM monitor and then populates variables in txn +// from values observed on bus activity. This task +// blocks until an operation on the fuse_ctrl_prim_axi_read_out bus is complete. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_prim_axi_read_out_pkg_hdl::*; +`include "src/fuse_ctrl_prim_axi_read_out_macros.svh" + + +interface fuse_ctrl_prim_axi_read_out_monitor_bfm #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + + ( fuse_ctrl_prim_axi_read_out_if bus ); + // The pragma below and additional ones in-lined further down are for running this BFM on Veloce + // pragma attribute fuse_ctrl_prim_axi_read_out_monitor_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: AW=%x DW=%x IW=%x UW=%x ", AW,DW,IW,UW), + UVM_DEBUG) +end +`endif + + + // Structure used to pass transaction data from monitor BFM to monitor class in agent. +`fuse_ctrl_prim_axi_read_out_MONITOR_STRUCT + fuse_ctrl_prim_axi_read_out_monitor_s fuse_ctrl_prim_axi_read_out_monitor_struct; + + // Structure used to pass configuration data from monitor class to monitor BFM. + `fuse_ctrl_prim_axi_read_out_CONFIGURATION_STRUCT + + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + tri clk_i_i; + tri rst_ni_i; + tri arready_i; + tri [DW-1:0] rdata_i; + tri rresp_i; + tri rid_i; + tri rlast_i; + tri rvalid_i; + assign clk_i_i = bus.clk_i; + assign rst_ni_i = bus.rst_ni; + assign arready_i = bus.arready; + assign rdata_i = bus.rdata; + assign rresp_i = bus.rresp; + assign rid_i = bus.rid; + assign rlast_i = bus.rlast; + assign rvalid_i = bus.rvalid; + + // Proxy handle to UVM monitor + fuse_ctrl_prim_axi_read_out_pkg::fuse_ctrl_prim_axi_read_out_monitor #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + proxy; + // pragma tbx oneway proxy.notify_transaction + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + task wait_for_reset();// pragma tbx xtf + @(posedge clk_i_i) ; + do_wait_for_reset(); + endtask + + // **************************************************************************** + task do_wait_for_reset(); + // pragma uvmf custom reset_condition begin + wait ( rst_ni_i === 1 ) ; + @(posedge clk_i_i) ; + // pragma uvmf custom reset_condition end + endtask + + //****************************************************************** + + task wait_for_num_clocks(input int unsigned count); // pragma tbx xtf + @(posedge clk_i_i); + + repeat (count-1) @(posedge clk_i_i); + endtask + + //****************************************************************** + event go; + function void start_monitoring();// pragma tbx xtf + -> go; + endfunction + + // **************************************************************************** + initial begin + @go; + forever begin + @(posedge clk_i_i); + do_monitor( fuse_ctrl_prim_axi_read_out_monitor_struct ); + + + proxy.notify_transaction( fuse_ctrl_prim_axi_read_out_monitor_struct ); + + end + end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the monitor BFM. It is called by the monitor within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the monitor BFM needs to be aware of the new configuration + // variables. + // + function void configure(fuse_ctrl_prim_axi_read_out_configuration_s fuse_ctrl_prim_axi_read_out_configuration_arg); // pragma tbx xtf + initiator_responder = fuse_ctrl_prim_axi_read_out_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + + + // **************************************************************************** + + task do_monitor(output fuse_ctrl_prim_axi_read_out_monitor_s fuse_ctrl_prim_axi_read_out_monitor_struct); + // + // Available struct members: + // // fuse_ctrl_prim_axi_read_out_monitor_struct.prim_arready + // // fuse_ctrl_prim_axi_read_out_monitor_struct.prim_rdata + // // fuse_ctrl_prim_axi_read_out_monitor_struct.prim_rresp + // // fuse_ctrl_prim_axi_read_out_monitor_struct.prim_rid + // // fuse_ctrl_prim_axi_read_out_monitor_struct.prim_rlast + // // fuse_ctrl_prim_axi_read_out_monitor_struct.prim_rvalid + // // + // Reference code; + // How to wait for signal value + // while (control_signal === 1'b1) @(posedge clk_i_i); + // + // How to assign a struct member, named xyz, from a signal. + // All available input signals listed. + // fuse_ctrl_prim_axi_read_out_monitor_struct.xyz = arready_i; // + // fuse_ctrl_prim_axi_read_out_monitor_struct.xyz = rdata_i; // [DW-1:0] + // fuse_ctrl_prim_axi_read_out_monitor_struct.xyz = rresp_i; // + // fuse_ctrl_prim_axi_read_out_monitor_struct.xyz = rid_i; // + // fuse_ctrl_prim_axi_read_out_monitor_struct.xyz = rlast_i; // + // fuse_ctrl_prim_axi_read_out_monitor_struct.xyz = rvalid_i; // + // pragma uvmf custom do_monitor begin + // UVMF_CHANGE_ME : Implement protocol monitoring. The commented reference code + // below are examples of how to capture signal values and assign them to + // structure members. All available input signals are listed. The 'while' + // code example shows how to wait for a synchronous flow control signal. This + // task should return when a complete transfer has been observed. Once this task is + // exited with captured values, it is then called again to wait for and observe + // the next transfer. One clock cycle is consumed between calls to do_monitor. + @(posedge clk_i_i); + @(posedge clk_i_i); + @(posedge clk_i_i); + @(posedge clk_i_i); + // pragma uvmf custom do_monitor end + endtask + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_random_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_random_sequence.svh new file mode 100644 index 0000000..869532e --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_random_sequence.svh @@ -0,0 +1,91 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This sequences randomizes the fuse_ctrl_prim_axi_read_out transaction and sends it +// to the UVM driver. +// +// This sequence constructs and randomizes a fuse_ctrl_prim_axi_read_out_transaction. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_read_out_random_sequence #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + + extends fuse_ctrl_prim_axi_read_out_sequence_base #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +; + + `uvm_object_param_utils( fuse_ctrl_prim_axi_read_out_random_sequence #( + AW, + DW, + IW, + UW + ) +) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //***************************************************************** + function new(string name = ""); + super.new(name); + endfunction: new + + // **************************************************************************** + // TASK : body() + // This task is automatically executed when this sequence is started using the + // start(sequencerHandle) task. + // + task body(); + + // Construct the transaction + req=fuse_ctrl_prim_axi_read_out_transaction#( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +::type_id::create("req"); + start_item(req); + // Randomize the transaction + if(!req.randomize()) `uvm_fatal("SEQ", "fuse_ctrl_prim_axi_read_out_random_sequence::body()-fuse_ctrl_prim_axi_read_out_transaction randomization failed") + // Send the transaction to the fuse_ctrl_prim_axi_read_out_driver_bfm via the sequencer and fuse_ctrl_prim_axi_read_out_driver. + finish_item(req); + `uvm_info("SEQ", {"Response:",req.convert2string()},UVM_MEDIUM) + + endtask + +endclass: fuse_ctrl_prim_axi_read_out_random_sequence + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_responder_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_responder_sequence.svh new file mode 100644 index 0000000..f27579b --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_responder_sequence.svh @@ -0,0 +1,87 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class can be used to provide stimulus when an interface +// has been configured to run in a responder mode. It +// will never finish by default, always going back to the driver +// and driver BFM for the next transaction with which to respond. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_read_out_responder_sequence #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + + extends fuse_ctrl_prim_axi_read_out_sequence_base #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +; + + `uvm_object_param_utils( fuse_ctrl_prim_axi_read_out_responder_sequence #( + AW, + DW, + IW, + UW + ) +) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "fuse_ctrl_prim_axi_read_out_responder_sequence"); + super.new(name); + endfunction + + task body(); + req=fuse_ctrl_prim_axi_read_out_transaction#( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +::type_id::create("req"); + forever begin + start_item(req); + finish_item(req); + // pragma uvmf custom body begin + // UVMF_CHANGE_ME : Do something here with the resulting req item. The + // finish_item() call above will block until the req transaction is ready + // to be handled by the responder sequence. + // If this was an item that required a response, the expectation is + // that the response should be populated within this transaction now. + `uvm_info("SEQ",$sformatf("Processed txn: %s",req.convert2string()),UVM_HIGH) + // pragma uvmf custom body end + end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_sequence_base.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_sequence_base.svh new file mode 100644 index 0000000..fb92381 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_sequence_base.svh @@ -0,0 +1,146 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the class used as the base class for all sequences +// for this interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_read_out_sequence_base #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvmf_sequence_base #( + .REQ(fuse_ctrl_prim_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .RSP(fuse_ctrl_prim_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +)); + + `uvm_object_param_utils( fuse_ctrl_prim_axi_read_out_sequence_base #( + AW, + DW, + IW, + UW + ) +) + + // variables + typedef fuse_ctrl_prim_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + fuse_ctrl_prim_axi_read_out_transaction_req_t; + fuse_ctrl_prim_axi_read_out_transaction_req_t req; + typedef fuse_ctrl_prim_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + fuse_ctrl_prim_axi_read_out_transaction_rsp_t; + fuse_ctrl_prim_axi_read_out_transaction_rsp_t rsp; + + // Event for identifying when a response was received from the sequencer + event new_rsp; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // TASK : get_responses() + // This task recursively gets sequence item responses from the sequencer. + // + virtual task get_responses(); + fork + begin + // Block until new rsp available + get_response(rsp); + // New rsp received. Indicate to sequence using event. + ->new_rsp; + // Display the received response transaction + `uvm_info("SEQ", {"New response transaction:",rsp.convert2string()}, UVM_MEDIUM) + end + join_none + endtask + + // **************************************************************************** + // TASK : pre_body() + // This task is called automatically when start is called with call_pre_post set to 1 (default). + // By calling get_responses() within pre_body() any derived sequences are automatically + // processing response transactions. Only un-comment this call to get_responses() if you + // have configured the interface driver to utilize the response transaction path by setting + // the configuration variable "return_transaction_response" to 1. Otherwise it is possible + // to impact runtime performance and memory utilization. + // + virtual task pre_body(); + // pragma uvmf custom pre_body begin +// get_responses(); + // pragma uvmf custom pre_body end + endtask + + // **************************************************************************** + // TASK : body() + // This task is called automatically when start is called. This sequence sends + // a req sequence item to the sequencer identified as an argument in the call + // to start. + // + virtual task body(); + // pragma uvmf custom body begin + start_item(req); + finish_item(req); + // pragma uvmf custom body end + endtask + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name =""); + super.new( name ); + // pragma uvmf custom new begin + req = fuse_ctrl_prim_axi_read_out_transaction_req_t::type_id::create("req"); + rsp = fuse_ctrl_prim_axi_read_out_transaction_rsp_t::type_id::create("rsp"); + // pragma uvmf custom new end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_transaction.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_transaction.svh new file mode 100644 index 0000000..4eda4df --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_transaction.svh @@ -0,0 +1,240 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class defines the variables required for an fuse_ctrl_prim_axi_read_out +// transaction. Class variables to be displayed in waveform transaction +// viewing are added to the transaction viewing stream in the add_to_wave +// function. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_read_out_transaction #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvmf_transaction_base; + + `uvm_object_param_utils( fuse_ctrl_prim_axi_read_out_transaction #( + AW, + DW, + IW, + UW + ) +) + + logic prim_arready ; + logic [DW-1:0] prim_rdata ; + axi_pkg::axi_burst_e prim_rresp ; + logic [IW-1:0] prim_rid ; + logic prim_rlast ; + logic prim_rvalid ; + + //Constraints for the transaction variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //******************************************************************* + //******************************************************************* + // Macros that define structs and associated functions are + // located in fuse_ctrl_prim_axi_read_out_macros.svh + + //******************************************************************* + // Monitor macro used by fuse_ctrl_prim_axi_read_out_monitor and fuse_ctrl_prim_axi_read_out_monitor_bfm + // This struct is defined in fuse_ctrl_prim_axi_read_out_macros.svh + `fuse_ctrl_prim_axi_read_out_MONITOR_STRUCT + fuse_ctrl_prim_axi_read_out_monitor_s fuse_ctrl_prim_axi_read_out_monitor_struct; + //******************************************************************* + // FUNCTION: to_monitor_struct() + // This function packs transaction variables into a fuse_ctrl_prim_axi_read_out_monitor_s + // structure. The function returns the handle to the fuse_ctrl_prim_axi_read_out_monitor_struct. + // This function is defined in fuse_ctrl_prim_axi_read_out_macros.svh + `fuse_ctrl_prim_axi_read_out_TO_MONITOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_monitor_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_prim_axi_read_out_macros.svh + `fuse_ctrl_prim_axi_read_out_FROM_MONITOR_STRUCT_FUNCTION + + //******************************************************************* + // Initiator macro used by fuse_ctrl_prim_axi_read_out_driver and fuse_ctrl_prim_axi_read_out_driver_bfm + // to communicate initiator driven data to fuse_ctrl_prim_axi_read_out_driver_bfm. + // This struct is defined in fuse_ctrl_prim_axi_read_out_macros.svh + `fuse_ctrl_prim_axi_read_out_INITIATOR_STRUCT + fuse_ctrl_prim_axi_read_out_initiator_s fuse_ctrl_prim_axi_read_out_initiator_struct; + //******************************************************************* + // FUNCTION: to_initiator_struct() + // This function packs transaction variables into a fuse_ctrl_prim_axi_read_out_initiator_s + // structure. The function returns the handle to the fuse_ctrl_prim_axi_read_out_initiator_struct. + // This function is defined in fuse_ctrl_prim_axi_read_out_macros.svh + `fuse_ctrl_prim_axi_read_out_TO_INITIATOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_initiator_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_prim_axi_read_out_macros.svh + `fuse_ctrl_prim_axi_read_out_FROM_INITIATOR_STRUCT_FUNCTION + + //******************************************************************* + // Responder macro used by fuse_ctrl_prim_axi_read_out_driver and fuse_ctrl_prim_axi_read_out_driver_bfm + // to communicate Responder driven data to fuse_ctrl_prim_axi_read_out_driver_bfm. + // This struct is defined in fuse_ctrl_prim_axi_read_out_macros.svh + `fuse_ctrl_prim_axi_read_out_RESPONDER_STRUCT + fuse_ctrl_prim_axi_read_out_responder_s fuse_ctrl_prim_axi_read_out_responder_struct; + //******************************************************************* + // FUNCTION: to_responder_struct() + // This function packs transaction variables into a fuse_ctrl_prim_axi_read_out_responder_s + // structure. The function returns the handle to the fuse_ctrl_prim_axi_read_out_responder_struct. + // This function is defined in fuse_ctrl_prim_axi_read_out_macros.svh + `fuse_ctrl_prim_axi_read_out_TO_RESPONDER_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_responder_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_prim_axi_read_out_macros.svh + `fuse_ctrl_prim_axi_read_out_FROM_RESPONDER_STRUCT_FUNCTION + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + endfunction + + // **************************************************************************** + // FUNCTION: convert2string() + // This function converts all variables in this class to a single string for + // logfile reporting. + // + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + // UVMF_CHANGE_ME : Customize format if desired. + return $sformatf("prim_arready:0x%x prim_rdata:0x%x prim_rresp:0x%x prim_rid:0x%x prim_rlast:0x%x prim_rvalid:0x%x ",prim_arready,prim_rdata,prim_rresp,prim_rid,prim_rlast,prim_rvalid); + // pragma uvmf custom convert2string end + endfunction + + //******************************************************************* + // FUNCTION: do_print() + // This function is automatically called when the .print() function + // is called on this class. + // + virtual function void do_print(uvm_printer printer); + // pragma uvmf custom do_print begin + // UVMF_CHANGE_ME : Current contents of do_print allows for the use of UVM 1.1d, 1.2 or P1800.2. + // Update based on your own printing preference according to your preferred UVM version + $display(convert2string()); + // pragma uvmf custom do_print end + endfunction + + //******************************************************************* + // FUNCTION: do_compare() + // This function is automatically called when the .compare() function + // is called on this class. + // + virtual function bit do_compare (uvm_object rhs, uvm_comparer comparer); + fuse_ctrl_prim_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + RHS; + if (!$cast(RHS,rhs)) return 0; + // pragma uvmf custom do_compare begin + // UVMF_CHANGE_ME : Eliminate comparison of variables not to be used for compare + return (super.do_compare(rhs,comparer) + &&(this.prim_arready == RHS.prim_arready) + &&(this.prim_rdata == RHS.prim_rdata) + &&(this.prim_rresp == RHS.prim_rresp) + &&(this.prim_rid == RHS.prim_rid) + &&(this.prim_rlast == RHS.prim_rlast) + &&(this.prim_rvalid == RHS.prim_rvalid) + ); + // pragma uvmf custom do_compare end + endfunction + + //******************************************************************* + // FUNCTION: do_copy() + // This function is automatically called when the .copy() function + // is called on this class. + // + virtual function void do_copy (uvm_object rhs); + fuse_ctrl_prim_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + RHS; + assert($cast(RHS,rhs)); + // pragma uvmf custom do_copy begin + super.do_copy(rhs); + this.prim_arready = RHS.prim_arready; + this.prim_rdata = RHS.prim_rdata; + this.prim_rresp = RHS.prim_rresp; + this.prim_rid = RHS.prim_rid; + this.prim_rlast = RHS.prim_rlast; + this.prim_rvalid = RHS.prim_rvalid; + // pragma uvmf custom do_copy end + endfunction + + // **************************************************************************** + // FUNCTION: add_to_wave() + // This function is used to display variables in this class in the waveform + // viewer. The start_time and end_time variables must be set before this + // function is called. If the start_time and end_time variables are not set + // the transaction will be hidden at 0ns on the waveform display. + // + virtual function void add_to_wave(int transaction_viewing_stream_h); + `ifdef QUESTA + if (transaction_view_h == 0) begin + transaction_view_h = $begin_transaction(transaction_viewing_stream_h,"fuse_ctrl_prim_axi_read_out_transaction",start_time); + end + super.add_to_wave(transaction_view_h); + // pragma uvmf custom add_to_wave begin + // UVMF_CHANGE_ME : Color can be applied to transaction entries based on content, example below + // case() + // 1 : $add_color(transaction_view_h,"red"); + // default : $add_color(transaction_view_h,"grey"); + // endcase + // UVMF_CHANGE_ME : Eliminate transaction variables not wanted in transaction viewing in the waveform viewer + $add_attribute(transaction_view_h,prim_arready,"prim_arready"); + $add_attribute(transaction_view_h,prim_rdata,"prim_rdata"); + $add_attribute(transaction_view_h,prim_rresp,"prim_rresp"); + $add_attribute(transaction_view_h,prim_rid,"prim_rid"); + $add_attribute(transaction_view_h,prim_rlast,"prim_rlast"); + $add_attribute(transaction_view_h,prim_rvalid,"prim_rvalid"); + // pragma uvmf custom add_to_wave end + $end_transaction(transaction_view_h,end_time); + $free_transaction(transaction_view_h); + `endif // QUESTA + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_transaction_coverage.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_transaction_coverage.svh new file mode 100644 index 0000000..b701f57 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_transaction_coverage.svh @@ -0,0 +1,107 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class records fuse_ctrl_prim_axi_read_out transaction information using +// a covergroup named fuse_ctrl_prim_axi_read_out_transaction_cg. An instance of this +// coverage component is instantiated in the uvmf_parameterized_agent +// if the has_coverage flag is set. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_read_out_transaction_coverage #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvm_subscriber #(.T(fuse_ctrl_prim_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +)); + + `uvm_component_param_utils( fuse_ctrl_prim_axi_read_out_transaction_coverage #( + AW, + DW, + IW, + UW + ) +) + + T coverage_trans; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + covergroup fuse_ctrl_prim_axi_read_out_transaction_cg; + // pragma uvmf custom covergroup begin + // UVMF_CHANGE_ME : Add coverage bins, crosses, exclusions, etc. according to coverage needs. + option.auto_bin_max=1024; + option.per_instance=1; + prim_arready: coverpoint coverage_trans.prim_arready; + prim_rdata: coverpoint coverage_trans.prim_rdata; + prim_rresp: coverpoint coverage_trans.prim_rresp; + prim_rid: coverpoint coverage_trans.prim_rid; + prim_rlast: coverpoint coverage_trans.prim_rlast; + prim_rvalid: coverpoint coverage_trans.prim_rvalid; + // pragma uvmf custom covergroup end + endgroup + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new(string name="", uvm_component parent=null); + super.new(name,parent); + fuse_ctrl_prim_axi_read_out_transaction_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that transaction variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + endfunction + + // **************************************************************************** + // FUNCTION : build_phase() + // This function is the standard UVM build_phase. + // + function void build_phase(uvm_phase phase); + fuse_ctrl_prim_axi_read_out_transaction_cg.set_inst_name($sformatf("fuse_ctrl_prim_axi_read_out_transaction_cg_%s",get_full_name())); + endfunction + + // **************************************************************************** + // FUNCTION: write (T t) + // This function is automatically executed when a transaction arrives on the + // analysis_export. It copies values from the variables in the transaction + // to local variables used to collect functional coverage. + // + virtual function void write (T t); + `uvm_info("COV","Received transaction",UVM_HIGH); + coverage_trans = t; + fuse_ctrl_prim_axi_read_out_transaction_cg.sample(); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_typedefs.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_typedefs.svh new file mode 100644 index 0000000..f2a7bdb --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_typedefs.svh @@ -0,0 +1,34 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the host server when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_typedefs_hdl.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_typedefs_hdl.svh new file mode 100644 index 0000000..0d58518 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/src/fuse_ctrl_prim_axi_read_out_typedefs_hdl.svh @@ -0,0 +1,35 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the emulator when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/yaml/fuse_ctrl_prim_axi_read_out_interface.yaml b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/yaml/fuse_ctrl_prim_axi_read_out_interface.yaml new file mode 100644 index 0000000..518e6a1 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_read_out_pkg/yaml/fuse_ctrl_prim_axi_read_out_interface.yaml @@ -0,0 +1,91 @@ +uvmf: + interfaces: + fuse_ctrl_prim_axi_read_out: + clock: clk_i + config_constraints: [] + config_vars: [] + existing_library_component: 'True' + gen_inbound_streaming_driver: 'False' + hdl_pkg_parameters: [] + hdl_typedefs: [] + hvl_pkg_parameters: [] + hvl_typedefs: [] + parameters: + - name: AW + type: int + value: '32' + - name: DW + type: int + value: '32' + - name: IW + type: int + value: '3' + - name: UW + type: int + value: '32' + ports: + - dir: input + name: arready + reset_value: '''bz' + width: '1' + - dir: input + name: rdata + reset_value: '''bz' + width: DW + - dir: input + name: rresp + reset_value: '''bz' + width: '1' + - dir: input + name: rid + reset_value: '''bz' + width: '1' + - dir: input + name: rlast + reset_value: '''bz' + width: '1' + - dir: input + name: rvalid + reset_value: '''bz' + width: '1' + reset: rst_ni + reset_assertion_level: 'False' + transaction_constraints: [] + transaction_vars: + - comment: '' + iscompare: 'True' + isrand: 'False' + name: prim_arready + type: logic + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'False' + name: prim_rdata + type: logic [DW-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'False' + name: prim_rresp + type: axi_pkg::axi_burst_e + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'False' + name: prim_rid + type: logic [IW-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'False' + name: prim_rlast + type: logic + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'False' + name: prim_rvalid + type: logic + unpacked_dimension: '' + use_dpi_link: 'False' diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/.project b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/.project new file mode 100644 index 0000000..8c615b5 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/.project @@ -0,0 +1,30 @@ + + + fuse_ctrl_prim_axi_write_in_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/.svproject b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/.svproject new file mode 100644 index 0000000..14eb90e --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/Makefile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/Makefile new file mode 100644 index 0000000..58b6255 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/Makefile @@ -0,0 +1,66 @@ +# fuse_ctrl_prim_axi_write_in interface packages source +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +fuse_ctrl_prim_axi_write_in_PKG = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_write_in_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_filelist_hvl.f + +fuse_ctrl_prim_axi_write_in_PKG_HDL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_write_in_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_filelist_hdl.f + +fuse_ctrl_prim_axi_write_in_PKG_XRTL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_write_in_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_filelist_xrtl.f + +COMP_fuse_ctrl_prim_axi_write_in_PKG_TGT_0 = q_comp_fuse_ctrl_prim_axi_write_in_pkg +COMP_fuse_ctrl_prim_axi_write_in_PKG_TGT_1 = v_comp_fuse_ctrl_prim_axi_write_in_pkg +COMP_fuse_ctrl_prim_axi_write_in_PKG_TGT = $(COMP_fuse_ctrl_prim_axi_write_in_PKG_TGT_$(USE_VELOCE)) + +comp_fuse_ctrl_prim_axi_write_in_pkg: $(COMP_fuse_ctrl_prim_axi_write_in_PKG_TGT) + +q_comp_fuse_ctrl_prim_axi_write_in_pkg: + $(HDL_COMP_CMD) $(fuse_ctrl_prim_axi_write_in_PKG_HDL) + $(HVL_COMP_CMD) $(fuse_ctrl_prim_axi_write_in_PKG) + $(HDL_COMP_CMD) $(fuse_ctrl_prim_axi_write_in_PKG_XRTL) + +v_comp_fuse_ctrl_prim_axi_write_in_pkg: + $(HVL_COMP_CMD) $(fuse_ctrl_prim_axi_write_in_PKG_HDL) + $(HVL_COMP_CMD) $(fuse_ctrl_prim_axi_write_in_PKG) + $(VELANALYZE_CMD) $(fuse_ctrl_prim_axi_write_in_PKG_HDL) + $(VELANALYZE_HVL_CMD) $(fuse_ctrl_prim_axi_write_in_PKG) + $(HDL_COMP_CMD) $(fuse_ctrl_prim_axi_write_in_PKG_XRTL) + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export fuse_ctrl_prim_axi_write_in_IF_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/dpi + +C_FILE_COMPILE_LIST_fuse_ctrl_prim_axi_write_in_pkg = \ + +O_FILE_COMPILE_LIST_fuse_ctrl_prim_axi_write_in_pkg = $(notdir $(C_FILE_COMPILE_LIST_fuse_ctrl_prim_axi_write_in_pkg:.c=.o)) + +GCC_COMP_ARGS_fuse_ctrl_prim_axi_write_in_pkg += -I$(fuse_ctrl_prim_axi_write_in_IF_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_fuse_ctrl_prim_axi_write_in_pkg += $(fuse_ctrl_prim_axi_write_in_IF_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_fuse_ctrl_prim_axi_write_in_pkg += \ + \ + -o .so + +comp_fuse_ctrl_prim_axi_write_in_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Interface C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_fuse_ctrl_prim_axi_write_in_pkg) $(C_FILE_COMPILE_LIST_fuse_ctrl_prim_axi_write_in_pkg) + @echo "--------------------------------" + @echo "Linking Interface C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_fuse_ctrl_prim_axi_write_in_pkg) $(O_FILE_COMPILE_LIST_fuse_ctrl_prim_axi_write_in_pkg) + @echo "--------------------------------" + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/compile.do b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/compile.do new file mode 100644 index 0000000..0b7eaf6 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/compile.do @@ -0,0 +1,14 @@ +# Tcl do file for compile of fuse_ctrl_prim_axi_write_in interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_write_in_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_filelist_hdl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_write_in_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_filelist_hvl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_write_in_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_filelist_xrtl.f \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in.compile new file mode 100644 index 0000000..cc55184 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in.compile @@ -0,0 +1,3 @@ +needs: + - fuse_ctrl_prim_axi_write_in_hvl.compile + - fuse_ctrl_prim_axi_write_in_hdl.compile diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_bfm.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_bfm.vinfo new file mode 100644 index 0000000..f0da591 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_bfm.vinfo @@ -0,0 +1,6 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use fuse_ctrl_prim_axi_write_in_pkg_hdl.vinfo ++incdir+@vinfodir +src/fuse_ctrl_prim_axi_write_in_if.sv +src/fuse_ctrl_prim_axi_write_in_driver_bfm.sv +src/fuse_ctrl_prim_axi_write_in_monitor_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_common.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_common.compile new file mode 100644 index 0000000..9fd1f6c --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_common.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +incdir: + - . + - ${uvm_path}/src +src: + - fuse_ctrl_prim_axi_write_in_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_filelist_hdl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_filelist_hdl.f new file mode 100644 index 0000000..05ff744 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_filelist_hdl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_filelist_hvl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_filelist_hvl.f new file mode 100644 index 0000000..9e594a7 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_filelist_hvl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_pkg.sv \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_filelist_xrtl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_filelist_xrtl.f new file mode 100644 index 0000000..aeb9836 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_filelist_xrtl.f @@ -0,0 +1,3 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_if.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_monitor_bfm.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_driver_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_hdl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_hdl.compile new file mode 100644 index 0000000..954117b --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_hdl.compile @@ -0,0 +1,9 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ./fuse_ctrl_prim_axi_write_in_common.compile +incdir: + - . +src: + - src/fuse_ctrl_prim_axi_write_in_if.sv + - src/fuse_ctrl_prim_axi_write_in_monitor_bfm.sv + - src/fuse_ctrl_prim_axi_write_in_driver_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_hvl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_hvl.compile new file mode 100644 index 0000000..7be9859 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_hvl.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ./fuse_ctrl_prim_axi_write_in_common.compile +incdir: + - . +src: + - fuse_ctrl_prim_axi_write_in_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_pkg.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_pkg.sv new file mode 100644 index 0000000..bebb7a3 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_pkg.sv @@ -0,0 +1,91 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - + +// - +// - +// - + +// - +// - +// - + +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_prim_axi_write_in_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg_hdl::*; + import uvmf_base_pkg::*; + import fuse_ctrl_prim_axi_write_in_pkg_hdl::*; + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + `include "src/fuse_ctrl_prim_axi_write_in_macros.svh" + + export fuse_ctrl_prim_axi_write_in_pkg_hdl::*; + + + + // Parameters defined as HVL parameters + + `include "src/fuse_ctrl_prim_axi_write_in_typedefs.svh" + `include "src/fuse_ctrl_prim_axi_write_in_transaction.svh" + + `include "src/fuse_ctrl_prim_axi_write_in_configuration.svh" + `include "src/fuse_ctrl_prim_axi_write_in_driver.svh" + `include "src/fuse_ctrl_prim_axi_write_in_monitor.svh" + + `include "src/fuse_ctrl_prim_axi_write_in_transaction_coverage.svh" + `include "src/fuse_ctrl_prim_axi_write_in_sequence_base.svh" + `include "src/fuse_ctrl_prim_axi_write_in_random_sequence.svh" + + `include "src/fuse_ctrl_prim_axi_write_in_responder_sequence.svh" + `include "src/fuse_ctrl_prim_axi_write_in2reg_adapter.svh" + + `include "src/fuse_ctrl_prim_axi_write_in_agent.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new interface sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the interface package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_pkg.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_pkg.vinfo new file mode 100644 index 0000000..a03a77b --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_pkg.vinfo @@ -0,0 +1,4 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use fuse_ctrl_prim_axi_write_in_pkg_hdl.vinfo ++incdir+@vinfodir +fuse_ctrl_prim_axi_write_in_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_pkg_hdl.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_pkg_hdl.sv new file mode 100644 index 0000000..b974d8d --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_pkg_hdl.sv @@ -0,0 +1,52 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that needs to be compiled and synthesized +// for running on Veloce. +// +// CONTAINS: +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_prim_axi_write_in_pkg_hdl; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HDL parameters + + `include "src/fuse_ctrl_prim_axi_write_in_typedefs_hdl.svh" + `include "src/fuse_ctrl_prim_axi_write_in_macros.svh" + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_pkg_hdl.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_pkg_hdl.vinfo new file mode 100644 index 0000000..6813b25 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_pkg_hdl.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +fuse_ctrl_prim_axi_write_in_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_pkg_sve.F b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_pkg_sve.F new file mode 100644 index 0000000..2762780 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_pkg_sve.F @@ -0,0 +1,10 @@ +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + ++incdir+. +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_filelist_hdl.f +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/fuse_ctrl_prim_axi_write_in_filelist_hvl.f diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in2reg_adapter.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in2reg_adapter.svh new file mode 100644 index 0000000..5711099 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in2reg_adapter.svh @@ -0,0 +1,142 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the UVM register adapter for the fuse_ctrl_prim_axi_write_in interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_write_in2reg_adapter #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvm_reg_adapter; + + `uvm_object_param_utils( fuse_ctrl_prim_axi_write_in2reg_adapter #( + AW, + DW, + IW, + UW + ) +) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //-------------------------------------------------------------------- + // new + //-------------------------------------------------------------------- + function new (string name = "fuse_ctrl_prim_axi_write_in2reg_adapter" ); + super.new(name); + // pragma uvmf custom new begin + // UVMF_CHANGE_ME : Configure the adapter regarding byte enables and provides response. + + // Does the protocol the Agent is modeling support byte enables? + // 0 = NO + // 1 = YES + supports_byte_enable = 0; + + // Does the Agent's Driver provide separate response sequence items? + // i.e. Does the driver call seq_item_port.put() + // and do the sequences call get_response()? + // 0 = NO + // 1 = YES + provides_responses = 0; + // pragma uvmf custom new end + + endfunction: new + + //-------------------------------------------------------------------- + // reg2bus + //-------------------------------------------------------------------- + virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw); + + fuse_ctrl_prim_axi_write_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + trans_h = fuse_ctrl_prim_axi_write_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +::type_id::create("trans_h"); + + // pragma uvmf custom reg2bus begin + // UVMF_CHANGE_ME : Fill in the reg2bus adapter mapping registe fields to protocol fields. + + //Adapt the following for your sequence item type + // trans_h.op = (rw.kind == UVM_READ) ? WB_READ : WB_WRITE; + //Copy over address + // trans_h.addr = rw.addr; + //Copy over write data + // trans_h.data = rw.data; + + // pragma uvmf custom reg2bus end + + // Return the adapted transaction + return trans_h; + + endfunction: reg2bus + + //-------------------------------------------------------------------- + // bus2reg + //-------------------------------------------------------------------- + virtual function void bus2reg(uvm_sequence_item bus_item, + ref uvm_reg_bus_op rw); + fuse_ctrl_prim_axi_write_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + trans_h; + if (!$cast(trans_h, bus_item)) begin + `uvm_fatal("ADAPT","Provided bus_item is not of the correct type") + return; + end + // pragma uvmf custom bus2reg begin + // UVMF_CHANGE_ME : Fill in the bus2reg adapter mapping protocol fields to register fields. + //Adapt the following for your sequence item type + //Copy over instruction type + // rw.kind = (trans_h.op == WB_WRITE) ? UVM_WRITE : UVM_READ; + //Copy over address + // rw.addr = trans_h.addr; + //Copy over read data + // rw.data = trans_h.data; + //Check for errors on the bus and return UVM_NOT_OK if there is an error + // rw.status = UVM_IS_OK; + // pragma uvmf custom bus2reg end + + endfunction: bus2reg + +endclass : fuse_ctrl_prim_axi_write_in2reg_adapter + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_agent.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_agent.svh new file mode 100644 index 0000000..552affa --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_agent.svh @@ -0,0 +1,109 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: Protocol specific agent class definition +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_write_in_agent #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvmf_parameterized_agent #( + .CONFIG_T(fuse_ctrl_prim_axi_write_in_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .DRIVER_T(fuse_ctrl_prim_axi_write_in_driver #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .MONITOR_T(fuse_ctrl_prim_axi_write_in_monitor #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .COVERAGE_T(fuse_ctrl_prim_axi_write_in_transaction_coverage #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .TRANS_T(fuse_ctrl_prim_axi_write_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +) + ); + + `uvm_component_param_utils( fuse_ctrl_prim_axi_write_in_agent #( + AW, + DW, + IW, + UW + ) +) + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** + // FUNCTION: build_phase + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + if (configuration.active_passive == ACTIVE) begin + // Place sequencer handle into configuration object + // so that it may be retrieved from configuration + // rather than using uvm_config_db + configuration.sequencer = this.sequencer; + end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_configuration.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_configuration.svh new file mode 100644 index 0000000..2a5858b --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_configuration.svh @@ -0,0 +1,241 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class contains all variables and functions used +// to configure the fuse_ctrl_prim_axi_write_in agent and its bfm's. It gets the +// bfm's from the uvm_config_db for use by the agent. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_write_in_configuration #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvmf_parameterized_agent_configuration_base #( + .DRIVER_BFM_BIND_T(virtual fuse_ctrl_prim_axi_write_in_driver_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .MONITOR_BFM_BIND_T( virtual fuse_ctrl_prim_axi_write_in_monitor_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +)); + + `uvm_object_param_utils( fuse_ctrl_prim_axi_write_in_configuration #( + AW, + DW, + IW, + UW + ) +) + + + // Sequencer handle populated by agent + uvm_sequencer #(fuse_ctrl_prim_axi_write_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + ) sequencer; + + //Constraints for the configuration variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + covergroup fuse_ctrl_prim_axi_write_in_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + // pragma uvmf custom covergroup end + endgroup + + //******************************************************************* + //******************************************************************* + // Structure used to pass configuration variables to monitor and driver BFM's. + // Use to_struct function to pack variables into structure. + // Use from_struct function to unpack variables from structure. + // This structure is defined in fuse_ctrl_prim_axi_write_in_macros.svh + `fuse_ctrl_prim_axi_write_in_CONFIGURATION_STRUCT + fuse_ctrl_prim_axi_write_in_configuration_s fuse_ctrl_prim_axi_write_in_configuration_struct; + //******************************************************************* + // FUNCTION: to_struct() + // This function packs variables into a fuse_ctrl_prim_axi_write_in_configuration_s + // structure. The function returns the handle to the fuse_ctrl_prim_axi_write_in_configuration_struct. + // This function is defined in fuse_ctrl_prim_axi_write_in_macros.svh + `fuse_ctrl_prim_axi_write_in_CONFIGURATION_TO_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_struct() + // This function unpacks the struct provided as an argument into + // variables of this class. + // This function is defined in fuse_ctrl_prim_axi_write_in_macros.svh + `fuse_ctrl_prim_axi_write_in_CONFIGURATION_FROM_STRUCT_FUNCTION + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + // Construct the covergroup for this configuration class + fuse_ctrl_prim_axi_write_in_configuration_cg = new; + endfunction + + // **************************************************************************** + // FUNCTION: post_randomize() + // This function is automatically called after the randomize() function + // is executed. + // + function void post_randomize(); + super.post_randomize(); + fuse_ctrl_prim_axi_write_in_configuration_cg.sample(); + endfunction + + // **************************************************************************** + // FUNCTION: initialize + // This function causes the configuration to retrieve + // its virtual interface handle from the uvm_config_db. + // This function also makes itself available to its + // agent through the uvm_config_db. + // + // ARGUMENTS: + // uvmf_active_passive_t activity: + // This argument identifies the simulation level + // as either BLOCK, CHIP, SIMULATION, etc. + // + // AGENT_PATH: + // This argument identifies the path to this + // configurations agent. This configuration + // makes itself available to the agent specified + // by agent_path by placing itself into the + // uvm_config_db. + // + // INTERFACE_NAME: + // This argument identifies the string name of + // this configurations BFM's. This string + // name is used to retrieve the driver and + // monitor BFM from the uvm_config_db. + // + virtual function void initialize(uvmf_active_passive_t activity, + string agent_path, + string interface_name); + + super.initialize( activity, agent_path, interface_name); + // The covergroup is given the same name as the interface + fuse_ctrl_prim_axi_write_in_configuration_cg.set_inst_name(interface_name); + + // This configuration places itself into the uvm_config_db for the agent, identified by the agent_path variable, to retrieve. + uvm_config_db #( fuse_ctrl_prim_axi_write_in_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + + )::set( null ,agent_path,UVMF_AGENT_CONFIG, this ); + + // This configuration also places itself in the config db using the same identifier used by the interface. This allows users to access + // configuration variables and the interface through the bfm api class rather than directly accessing the BFM. This is useful for + // accessingthe BFM when using Veloce + uvm_config_db #( fuse_ctrl_prim_axi_write_in_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + + )::set( null ,UVMF_CONFIGURATIONS, interface_name, this ); + + fuse_ctrl_prim_axi_write_in_configuration_cg.set_inst_name($sformatf("fuse_ctrl_prim_axi_write_in_configuration_cg_%s",get_full_name())); + +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. + `uvm_info("CFG", + $psprintf("The agent at '%s' is using interface named %s has the following parameters: AW=%x DW=%x IW=%x UW=%x ", agent_path, interface_name, AW ,DW ,IW ,UW ), + UVM_DEBUG) + + // pragma uvmf custom initialize begin + // This controls whether or not the agent returns a transaction handle in the driver when calling + // item_done() back into the sequencer or not. If set to 1, a transaction is sent back which means + // the sequence on the other end must use the get_response() part of the driver/sequence API. If + // this doesn't occur, there will eventually be response_queue overflow errors during the test. + return_transaction_response = 1'b0; + + // pragma uvmf custom initialize end + + endfunction + + // **************************************************************************** + // TASK: wait_for_reset + // *[Required]* Blocks until reset is released. The wait_for_reset operation is performed + // by a task in the monitor bfm. + virtual task wait_for_reset(); + monitor_bfm.wait_for_reset(); + endtask + + // **************************************************************************** + // TASK: wait_for_num_clocks + // *[Required]* Blocks until specified number of clocks have elapsed. The wait_for_num_clocks + // operation is performed by a task in the monitor bfm. + virtual task wait_for_num_clocks(int clocks); + monitor_bfm.wait_for_num_clocks(clocks); + endtask + + // **************************************************************************** + // FUNCTION : convert2string() + // This function is used to convert variables in this class into a string for log messaging. + // + virtual function string convert2string (); + // pragma uvmf custom convert2string begin + return $sformatf(""); + // pragma uvmf custom convert2string end + endfunction + + // **************************************************************************** + // FUNCTION: get_sequencer + function uvm_sequencer #(fuse_ctrl_prim_axi_write_in_transaction#( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +) get_sequencer(); + return sequencer; + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_driver.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_driver.svh new file mode 100644 index 0000000..ad7975f --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_driver.svh @@ -0,0 +1,141 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class passes transactions between the sequencer +// and the BFM driver interface. It accesses the driver BFM +// through the bfm handle. This driver +// passes transactions to the driver BFM through the access +// task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_write_in_driver #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvmf_driver_base #( + .CONFIG_T(fuse_ctrl_prim_axi_write_in_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + ), + .BFM_BIND_T(virtual fuse_ctrl_prim_axi_write_in_driver_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + ), + .REQ(fuse_ctrl_prim_axi_write_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + ), + .RSP(fuse_ctrl_prim_axi_write_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + )); + + `uvm_component_param_utils( fuse_ctrl_prim_axi_write_in_driver #( + AW, + DW, + IW, + UW + ) +) +//******************************************************************* +// Macros that define structs located in fuse_ctrl_prim_axi_write_in_macros.svh +//******************************************************************* +// Initiator macro used by fuse_ctrl_prim_axi_write_in_driver and fuse_ctrl_prim_axi_write_in_driver_bfm +// to communicate initiator driven data to fuse_ctrl_prim_axi_write_in_driver_bfm. +`fuse_ctrl_prim_axi_write_in_INITIATOR_STRUCT + fuse_ctrl_prim_axi_write_in_initiator_s fuse_ctrl_prim_axi_write_in_initiator_struct; +//******************************************************************* +// Responder macro used by fuse_ctrl_prim_axi_write_in_driver and fuse_ctrl_prim_axi_write_in_driver_bfm +// to communicate Responder driven data to fuse_ctrl_prim_axi_write_in_driver_bfm. +`fuse_ctrl_prim_axi_write_in_RESPONDER_STRUCT + fuse_ctrl_prim_axi_write_in_responder_s fuse_ctrl_prim_axi_write_in_responder_struct; + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent=null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the driver BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// driver BFM. This allows the driver BFM to call tasks and function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// **************************************************************************** +// This task is called by the run_phase in uvmf_driver_base. + virtual task access( inout REQ txn ); +// pragma uvmf custom access begin + if (configuration.initiator_responder==RESPONDER) begin + // Complete current transfer and wait for next transfer + bfm.respond_and_wait_for_next_transfer( + fuse_ctrl_prim_axi_write_in_initiator_struct, + txn.to_responder_struct() + ); + // Unpack information about initiated transfer received by this responder + txn.from_initiator_struct(fuse_ctrl_prim_axi_write_in_initiator_struct); + end else begin + // Initiate a transfer and get response + bfm.initiate_and_get_response( + txn.to_initiator_struct(), + fuse_ctrl_prim_axi_write_in_responder_struct + ); + // Unpack transfer response information received by this initiator + txn.from_responder_struct(fuse_ctrl_prim_axi_write_in_responder_struct); + end +// pragma uvmf custom access end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_driver_bfm.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_driver_bfm.sv new file mode 100644 index 0000000..74c7fb4 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_driver_bfm.sv @@ -0,0 +1,429 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This interface performs the fuse_ctrl_prim_axi_write_in signal driving. It is +// accessed by the uvm fuse_ctrl_prim_axi_write_in driver through a virtual interface +// handle in the fuse_ctrl_prim_axi_write_in configuration. It drives the singals passed +// in through the port connection named bus of type fuse_ctrl_prim_axi_write_in_if. +// +// Input signals from the fuse_ctrl_prim_axi_write_in_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// This bfm drives signals with a _o suffix. These signals +// are driven onto signals within fuse_ctrl_prim_axi_write_in_if based on INITIATOR/RESPONDER and/or +// ARBITRATION/GRANT status. +// +// The output signal connections are as follows: +// signal_o -> bus.signal +// +// +// Interface functions and tasks used by UVM components: +// +// configure: +// This function gets configuration attributes from the +// UVM driver to set any required BFM configuration +// variables such as 'initiator_responder'. +// +// initiate_and_get_response: +// This task is used to perform signaling activity for initiating +// a protocol transfer. The task initiates the transfer, using +// input data from the initiator struct. Then the task captures +// response data, placing the data into the response struct. +// The response struct is returned to the driver class. +// +// respond_and_wait_for_next_transfer: +// This task is used to complete a current transfer as a responder +// and then wait for the initiator to start the next transfer. +// The task uses data in the responder struct to drive protocol +// signals to complete the transfer. The task then waits for +// the next transfer. Once the next transfer begins, data from +// the initiator is placed into the initiator struct and sent +// to the responder sequence for processing to determine +// what data to respond with. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_prim_axi_write_in_pkg_hdl::*; +`include "src/fuse_ctrl_prim_axi_write_in_macros.svh" + +interface fuse_ctrl_prim_axi_write_in_driver_bfm #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + + (fuse_ctrl_prim_axi_write_in_if bus); + // The following pragma and additional ones in-lined further below are for running this BFM on Veloce + // pragma attribute fuse_ctrl_prim_axi_write_in_driver_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: AW=%x DW=%x IW=%x UW=%x ", AW,DW,IW,UW), + UVM_DEBUG) +end +`endif + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + tri clk_i_i; + tri rst_ni_i; + + // Signal list (all signals are capable of being inputs and outputs for the sake + // of supporting both INITIATOR and RESPONDER mode operation. Expectation is that + // directionality in the config file was from the point-of-view of the INITIATOR + + // INITIATOR mode input signals + + // INITIATOR mode output signals + tri [AW-1:0] awaddr_i; + reg [AW-1:0] awaddr_o = 'bz; + tri [$bits(axi_pkg::axi_burst_e)-1:0] awburst_i; + reg [$bits(axi_pkg::axi_burst_e)-1:0] awburst_o = 'bz; + tri [2:0] awsize_i; + reg [2:0] awsize_o = 'bz; + tri [7:0] awlen_i; + reg [7:0] awlen_o = 'bz; + tri [UW-1:0] awuser_i; + reg [UW-1:0] awuser_o = 'bz; + tri [UW-1:0] awid_i; + reg [UW-1:0] awid_o = 'bz; + tri awlock_i; + reg awlock_o = 'bz; + tri awvalid_i; + reg awvalid_o = 'bz; + tri [DW-1:0] wdata_i; + reg [DW-1:0] wdata_o = 'bz; + tri [DW/8-1:0] wstrb_i; + reg [DW/8-1:0] wstrb_o = 'bz; + tri wvalid_i; + reg wvalid_o = 'bz; + tri wlast_i; + reg wlast_o = 'bz; + tri bready_i; + reg bready_o = 'bz; + + // Bi-directional signals + + + assign clk_i_i = bus.clk_i; + assign rst_ni_i = bus.rst_ni; + + // These are signals marked as 'input' by the config file, but the signals will be + // driven by this BFM if put into RESPONDER mode (flipping all signal directions around) + + + // These are signals marked as 'output' by the config file, but the outputs will + // not be driven by this BFM unless placed in INITIATOR mode. + assign bus.awaddr = (initiator_responder == INITIATOR) ? awaddr_o : 'bz; + assign awaddr_i = bus.awaddr; + assign bus.awburst = (initiator_responder == INITIATOR) ? awburst_o : 'bz; + assign awburst_i = bus.awburst; + assign bus.awsize = (initiator_responder == INITIATOR) ? awsize_o : 'bz; + assign awsize_i = bus.awsize; + assign bus.awlen = (initiator_responder == INITIATOR) ? awlen_o : 'bz; + assign awlen_i = bus.awlen; + assign bus.awuser = (initiator_responder == INITIATOR) ? awuser_o : 'bz; + assign awuser_i = bus.awuser; + assign bus.awid = (initiator_responder == INITIATOR) ? awid_o : 'bz; + assign awid_i = bus.awid; + assign bus.awlock = (initiator_responder == INITIATOR) ? awlock_o : 'bz; + assign awlock_i = bus.awlock; + assign bus.awvalid = (initiator_responder == INITIATOR) ? awvalid_o : 'bz; + assign awvalid_i = bus.awvalid; + assign bus.wdata = (initiator_responder == INITIATOR) ? wdata_o : 'bz; + assign wdata_i = bus.wdata; + assign bus.wstrb = (initiator_responder == INITIATOR) ? wstrb_o : 'bz; + assign wstrb_i = bus.wstrb; + assign bus.wvalid = (initiator_responder == INITIATOR) ? wvalid_o : 'bz; + assign wvalid_i = bus.wvalid; + assign bus.wlast = (initiator_responder == INITIATOR) ? wlast_o : 'bz; + assign wlast_i = bus.wlast; + assign bus.bready = (initiator_responder == INITIATOR) ? bready_o : 'bz; + assign bready_i = bus.bready; + + // Proxy handle to UVM driver + fuse_ctrl_prim_axi_write_in_pkg::fuse_ctrl_prim_axi_write_in_driver #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + proxy; + // pragma tbx oneway proxy.my_function_name_in_uvm_driver + + // **************************************************************************** + // **************************************************************************** + // Macros that define structs located in fuse_ctrl_prim_axi_write_in_macros.svh + // **************************************************************************** + // Struct for passing configuration data from fuse_ctrl_prim_axi_write_in_driver to this BFM + // **************************************************************************** + `fuse_ctrl_prim_axi_write_in_CONFIGURATION_STRUCT + // **************************************************************************** + // Structs for INITIATOR and RESPONDER data flow + //******************************************************************* + // Initiator macro used by fuse_ctrl_prim_axi_write_in_driver and fuse_ctrl_prim_axi_write_in_driver_bfm + // to communicate initiator driven data to fuse_ctrl_prim_axi_write_in_driver_bfm. + `fuse_ctrl_prim_axi_write_in_INITIATOR_STRUCT + fuse_ctrl_prim_axi_write_in_initiator_s initiator_struct; + // Responder macro used by fuse_ctrl_prim_axi_write_in_driver and fuse_ctrl_prim_axi_write_in_driver_bfm + // to communicate Responder driven data to fuse_ctrl_prim_axi_write_in_driver_bfm. + `fuse_ctrl_prim_axi_write_in_RESPONDER_STRUCT + fuse_ctrl_prim_axi_write_in_responder_s responder_struct; + + // **************************************************************************** +// pragma uvmf custom reset_condition_and_response begin + // Always block used to return signals to reset value upon assertion of reset + always @( negedge rst_ni_i ) + begin + // RESPONDER mode output signals + // INITIATOR mode output signals + awaddr_o <= 'bz; + awburst_o <= 'bz; + awsize_o <= 'bz; + awlen_o <= 'bz; + awuser_o <= 'bz; + awid_o <= 'bz; + awlock_o <= 'bz; + awvalid_o <= 'bz; + wdata_o <= 'bz; + wstrb_o <= 'bz; + wvalid_o <= 'bz; + wlast_o <= 'bz; + bready_o <= 'bz; + // Bi-directional signals + + end +// pragma uvmf custom reset_condition_and_response end + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the driver BFM. It is called by the driver within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the driver BFM needs to be aware of the new configuration + // variables. + // + + function void configure(fuse_ctrl_prim_axi_write_in_configuration_s fuse_ctrl_prim_axi_write_in_configuration_arg); // pragma tbx xtf + initiator_responder = fuse_ctrl_prim_axi_write_in_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + +// pragma uvmf custom initiate_and_get_response begin +// **************************************************************************** +// UVMF_CHANGE_ME +// This task is used by an initator. The task first initiates a transfer then +// waits for the responder to complete the transfer. + task initiate_and_get_response( + // This argument passes transaction variables used by an initiator + // to perform the initial part of a protocol transfer. The values + // come from a sequence item created in a sequence. + input fuse_ctrl_prim_axi_write_in_initiator_s fuse_ctrl_prim_axi_write_in_initiator_struct, + // This argument is used to send data received from the responder + // back to the sequence item. The sequence item is returned to the sequence. + output fuse_ctrl_prim_axi_write_in_responder_s fuse_ctrl_prim_axi_write_in_responder_struct + );// pragma tbx xtf + // + // Members within the fuse_ctrl_prim_axi_write_in_initiator_struct: + // logic [AW-1:0] prim_awaddr ; + // logic prim_awvalid ; + // logic [$bits(axi_pkg::axi_burst_e)] prim_awburst ; + // logic [2:0] prim_awsize ; + // logic [7:0] prim_awlen ; + // logic [UW-1:0] prim_awuser ; + // logic [IW-1:0] prim_awid ; + // logic prim_awlock ; + // logic [DW-1:0] prim_wdata ; + // logic [DW/8 - 1:0] prim_wstrb ; + // logic prim_wvalid ; + // logic prim_wlast ; + // logic prim_bready ; + // Members within the fuse_ctrl_prim_axi_write_in_responder_struct: + // logic [AW-1:0] prim_awaddr ; + // logic prim_awvalid ; + // logic [$bits(axi_pkg::axi_burst_e)] prim_awburst ; + // logic [2:0] prim_awsize ; + // logic [7:0] prim_awlen ; + // logic [UW-1:0] prim_awuser ; + // logic [IW-1:0] prim_awid ; + // logic prim_awlock ; + // logic [DW-1:0] prim_wdata ; + // logic [DW/8 - 1:0] prim_wstrb ; + // logic prim_wvalid ; + // logic prim_wlast ; + // logic prim_bready ; + initiator_struct = fuse_ctrl_prim_axi_write_in_initiator_struct; + // + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clk_i_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available initiator input and inout signals listed. + // Initiator input signals + // Initiator inout signals + // How to assign a signal from an initiator struct member named xyz. + // All available initiator output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Initiator output signals + // awaddr_o <= fuse_ctrl_prim_axi_write_in_initiator_struct.xyz; // [AW-1:0] + // awburst_o <= fuse_ctrl_prim_axi_write_in_initiator_struct.xyz; // [$bits(axi_pkg::axi_burst_e)-1:0] + // awsize_o <= fuse_ctrl_prim_axi_write_in_initiator_struct.xyz; // [2:0] + // awlen_o <= fuse_ctrl_prim_axi_write_in_initiator_struct.xyz; // [7:0] + // awuser_o <= fuse_ctrl_prim_axi_write_in_initiator_struct.xyz; // [UW-1:0] + // awid_o <= fuse_ctrl_prim_axi_write_in_initiator_struct.xyz; // [UW-1:0] + // awlock_o <= fuse_ctrl_prim_axi_write_in_initiator_struct.xyz; // + // awvalid_o <= fuse_ctrl_prim_axi_write_in_initiator_struct.xyz; // + // wdata_o <= fuse_ctrl_prim_axi_write_in_initiator_struct.xyz; // [DW-1:0] + // wstrb_o <= fuse_ctrl_prim_axi_write_in_initiator_struct.xyz; // [DW/8-1:0] + // wvalid_o <= fuse_ctrl_prim_axi_write_in_initiator_struct.xyz; // + // wlast_o <= fuse_ctrl_prim_axi_write_in_initiator_struct.xyz; // + // bready_o <= fuse_ctrl_prim_axi_write_in_initiator_struct.xyz; // + // Initiator inout signals + // Initiate a transfer using the data received. + @(posedge clk_i_i); + @(posedge clk_i_i); + // Wait for the responder to complete the transfer then place the responder data into + // fuse_ctrl_prim_axi_write_in_responder_struct. + @(posedge clk_i_i); + @(posedge clk_i_i); + responder_struct = fuse_ctrl_prim_axi_write_in_responder_struct; + endtask +// pragma uvmf custom initiate_and_get_response end + +// pragma uvmf custom respond_and_wait_for_next_transfer begin +// **************************************************************************** +// The first_transfer variable is used to prevent completing a transfer in the +// first call to this task. For the first call to this task, there is not +// current transfer to complete. +bit first_transfer=1; + +// UVMF_CHANGE_ME +// This task is used by a responder. The task first completes the current +// transfer in progress then waits for the initiator to start the next transfer. + task respond_and_wait_for_next_transfer( + // This argument is used to send data received from the initiator + // back to the sequence item. The sequence determines how to respond. + output fuse_ctrl_prim_axi_write_in_initiator_s fuse_ctrl_prim_axi_write_in_initiator_struct, + // This argument passes transaction variables used by a responder + // to complete a protocol transfer. The values come from a sequence item. + input fuse_ctrl_prim_axi_write_in_responder_s fuse_ctrl_prim_axi_write_in_responder_struct + );// pragma tbx xtf + // Variables within the fuse_ctrl_prim_axi_write_in_initiator_struct: + // logic [AW-1:0] prim_awaddr ; + // logic prim_awvalid ; + // logic [$bits(axi_pkg::axi_burst_e)] prim_awburst ; + // logic [2:0] prim_awsize ; + // logic [7:0] prim_awlen ; + // logic [UW-1:0] prim_awuser ; + // logic [IW-1:0] prim_awid ; + // logic prim_awlock ; + // logic [DW-1:0] prim_wdata ; + // logic [DW/8 - 1:0] prim_wstrb ; + // logic prim_wvalid ; + // logic prim_wlast ; + // logic prim_bready ; + // Variables within the fuse_ctrl_prim_axi_write_in_responder_struct: + // logic [AW-1:0] prim_awaddr ; + // logic prim_awvalid ; + // logic [$bits(axi_pkg::axi_burst_e)] prim_awburst ; + // logic [2:0] prim_awsize ; + // logic [7:0] prim_awlen ; + // logic [UW-1:0] prim_awuser ; + // logic [IW-1:0] prim_awid ; + // logic prim_awlock ; + // logic [DW-1:0] prim_wdata ; + // logic [DW/8 - 1:0] prim_wstrb ; + // logic prim_wvalid ; + // logic prim_wlast ; + // logic prim_bready ; + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clk_i_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available responder input and inout signals listed. + // Responder input signals + // fuse_ctrl_prim_axi_write_in_responder_struct.xyz = awaddr_i; // [AW-1:0] + // fuse_ctrl_prim_axi_write_in_responder_struct.xyz = awburst_i; // [$bits(axi_pkg::axi_burst_e)-1:0] + // fuse_ctrl_prim_axi_write_in_responder_struct.xyz = awsize_i; // [2:0] + // fuse_ctrl_prim_axi_write_in_responder_struct.xyz = awlen_i; // [7:0] + // fuse_ctrl_prim_axi_write_in_responder_struct.xyz = awuser_i; // [UW-1:0] + // fuse_ctrl_prim_axi_write_in_responder_struct.xyz = awid_i; // [UW-1:0] + // fuse_ctrl_prim_axi_write_in_responder_struct.xyz = awlock_i; // + // fuse_ctrl_prim_axi_write_in_responder_struct.xyz = awvalid_i; // + // fuse_ctrl_prim_axi_write_in_responder_struct.xyz = wdata_i; // [DW-1:0] + // fuse_ctrl_prim_axi_write_in_responder_struct.xyz = wstrb_i; // [DW/8-1:0] + // fuse_ctrl_prim_axi_write_in_responder_struct.xyz = wvalid_i; // + // fuse_ctrl_prim_axi_write_in_responder_struct.xyz = wlast_i; // + // fuse_ctrl_prim_axi_write_in_responder_struct.xyz = bready_i; // + // Responder inout signals + // How to assign a signal, named xyz, from an initiator struct member. + // All available responder output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Responder output signals + // Responder inout signals + + @(posedge clk_i_i); + if (!first_transfer) begin + // Perform transfer response here. + // Reply using data recieved in the fuse_ctrl_prim_axi_write_in_responder_struct. + @(posedge clk_i_i); + // Reply using data recieved in the transaction handle. + @(posedge clk_i_i); + end + // Wait for next transfer then gather info from intiator about the transfer. + // Place the data into the fuse_ctrl_prim_axi_write_in_initiator_struct. + @(posedge clk_i_i); + @(posedge clk_i_i); + first_transfer = 0; + endtask +// pragma uvmf custom respond_and_wait_for_next_transfer end + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_if.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_if.sv new file mode 100644 index 0000000..ba77427 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_if.sv @@ -0,0 +1,144 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface contains the fuse_ctrl_prim_axi_write_in interface signals. +// It is instantiated once per fuse_ctrl_prim_axi_write_in bus. Bus Functional Models, +// BFM's named fuse_ctrl_prim_axi_write_in_driver_bfm, are used to drive signals on the bus. +// BFM's named fuse_ctrl_prim_axi_write_in_monitor_bfm are used to monitor signals on the +// bus. This interface signal bundle is passed in the port list of +// the BFM in order to give the BFM access to the signals in this +// interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// This template can be used to connect a DUT to these signals +// +// .dut_signal_port(fuse_ctrl_prim_axi_write_in_bus.awaddr), // Agent output +// .dut_signal_port(fuse_ctrl_prim_axi_write_in_bus.awburst), // Agent output +// .dut_signal_port(fuse_ctrl_prim_axi_write_in_bus.awsize), // Agent output +// .dut_signal_port(fuse_ctrl_prim_axi_write_in_bus.awlen), // Agent output +// .dut_signal_port(fuse_ctrl_prim_axi_write_in_bus.awuser), // Agent output +// .dut_signal_port(fuse_ctrl_prim_axi_write_in_bus.awid), // Agent output +// .dut_signal_port(fuse_ctrl_prim_axi_write_in_bus.awlock), // Agent output +// .dut_signal_port(fuse_ctrl_prim_axi_write_in_bus.awvalid), // Agent output +// .dut_signal_port(fuse_ctrl_prim_axi_write_in_bus.wdata), // Agent output +// .dut_signal_port(fuse_ctrl_prim_axi_write_in_bus.wstrb), // Agent output +// .dut_signal_port(fuse_ctrl_prim_axi_write_in_bus.wvalid), // Agent output +// .dut_signal_port(fuse_ctrl_prim_axi_write_in_bus.wlast), // Agent output +// .dut_signal_port(fuse_ctrl_prim_axi_write_in_bus.bready), // Agent output + +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_prim_axi_write_in_pkg_hdl::*; + +interface fuse_ctrl_prim_axi_write_in_if #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + + + ( + input tri clk_i, + input tri rst_ni, + inout tri [AW-1:0] awaddr, + inout tri [$bits(axi_pkg::axi_burst_e)-1:0] awburst, + inout tri [2:0] awsize, + inout tri [7:0] awlen, + inout tri [UW-1:0] awuser, + inout tri [UW-1:0] awid, + inout tri awlock, + inout tri awvalid, + inout tri [DW-1:0] wdata, + inout tri [DW/8-1:0] wstrb, + inout tri wvalid, + inout tri wlast, + inout tri bready + ); + +modport monitor_port + ( + input clk_i, + input rst_ni, + input awaddr, + input awburst, + input awsize, + input awlen, + input awuser, + input awid, + input awlock, + input awvalid, + input wdata, + input wstrb, + input wvalid, + input wlast, + input bready + ); + +modport initiator_port + ( + input clk_i, + input rst_ni, + output awaddr, + output awburst, + output awsize, + output awlen, + output awuser, + output awid, + output awlock, + output awvalid, + output wdata, + output wstrb, + output wvalid, + output wlast, + output bready + ); + +modport responder_port + ( + input clk_i, + input rst_ni, + input awaddr, + input awburst, + input awsize, + input awlen, + input awuser, + input awid, + input awlock, + input awvalid, + input wdata, + input wstrb, + input wvalid, + input wlast, + input bready + ); + + +// pragma uvmf custom interface_item_additional begin +// pragma uvmf custom interface_item_additional end + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_infact_coverage_strategy.csv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_infact_coverage_strategy.csv new file mode 100644 index 0000000..1c218e1 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_infact_coverage_strategy.csv @@ -0,0 +1,6 @@ +Global +auto_bin_max, 64 + +Name,Type,Include +rand_fields,coverpoint,=rand *.** + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_macros.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_macros.svh new file mode 100644 index 0000000..5d21a90 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_macros.svh @@ -0,0 +1,243 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains macros used with the fuse_ctrl_prim_axi_write_in package. +// These macros include packed struct definitions. These structs are +// used to pass data between classes, hvl, and BFM's, hdl. Use of +// structs are more efficient and simpler to modify. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_struct +// and from_struct methods defined in the macros below that are used in +// the fuse_ctrl_prim_axi_write_in_configuration class. +// + `define fuse_ctrl_prim_axi_write_in_CONFIGURATION_STRUCT \ +typedef struct packed { \ + uvmf_active_passive_t active_passive; \ + uvmf_initiator_responder_t initiator_responder; \ + } fuse_ctrl_prim_axi_write_in_configuration_s; + + `define fuse_ctrl_prim_axi_write_in_CONFIGURATION_TO_STRUCT_FUNCTION \ + virtual function fuse_ctrl_prim_axi_write_in_configuration_s to_struct();\ + fuse_ctrl_prim_axi_write_in_configuration_struct = \ + {\ + this.active_passive,\ + this.initiator_responder\ + };\ + return ( fuse_ctrl_prim_axi_write_in_configuration_struct );\ + endfunction + + `define fuse_ctrl_prim_axi_write_in_CONFIGURATION_FROM_STRUCT_FUNCTION \ + virtual function void from_struct(fuse_ctrl_prim_axi_write_in_configuration_s fuse_ctrl_prim_axi_write_in_configuration_struct);\ + {\ + this.active_passive,\ + this.initiator_responder \ + } = fuse_ctrl_prim_axi_write_in_configuration_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_monitor_struct +// and from_monitor_struct methods of the fuse_ctrl_prim_axi_write_in_transaction class. +// + `define fuse_ctrl_prim_axi_write_in_MONITOR_STRUCT typedef struct packed { \ + logic [AW-1:0] prim_awaddr ; \ + logic prim_awvalid ; \ + logic [$bits(axi_pkg::axi_burst_e)] prim_awburst ; \ + logic [2:0] prim_awsize ; \ + logic [7:0] prim_awlen ; \ + logic [UW-1:0] prim_awuser ; \ + logic [IW-1:0] prim_awid ; \ + logic prim_awlock ; \ + logic [DW-1:0] prim_wdata ; \ + logic [DW/8 - 1:0] prim_wstrb ; \ + logic prim_wvalid ; \ + logic prim_wlast ; \ + logic prim_bready ; \ + } fuse_ctrl_prim_axi_write_in_monitor_s; + + `define fuse_ctrl_prim_axi_write_in_TO_MONITOR_STRUCT_FUNCTION \ + virtual function fuse_ctrl_prim_axi_write_in_monitor_s to_monitor_struct();\ + fuse_ctrl_prim_axi_write_in_monitor_struct = \ + { \ + this.prim_awaddr , \ + this.prim_awvalid , \ + this.prim_awburst , \ + this.prim_awsize , \ + this.prim_awlen , \ + this.prim_awuser , \ + this.prim_awid , \ + this.prim_awlock , \ + this.prim_wdata , \ + this.prim_wstrb , \ + this.prim_wvalid , \ + this.prim_wlast , \ + this.prim_bready \ + };\ + return ( fuse_ctrl_prim_axi_write_in_monitor_struct);\ + endfunction\ + + `define fuse_ctrl_prim_axi_write_in_FROM_MONITOR_STRUCT_FUNCTION \ + virtual function void from_monitor_struct(fuse_ctrl_prim_axi_write_in_monitor_s fuse_ctrl_prim_axi_write_in_monitor_struct);\ + {\ + this.prim_awaddr , \ + this.prim_awvalid , \ + this.prim_awburst , \ + this.prim_awsize , \ + this.prim_awlen , \ + this.prim_awuser , \ + this.prim_awid , \ + this.prim_awlock , \ + this.prim_wdata , \ + this.prim_wstrb , \ + this.prim_wvalid , \ + this.prim_wlast , \ + this.prim_bready \ + } = fuse_ctrl_prim_axi_write_in_monitor_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_initiator_struct +// and from_initiator_struct methods of the fuse_ctrl_prim_axi_write_in_transaction class. +// Also update the comments in the driver BFM. +// + `define fuse_ctrl_prim_axi_write_in_INITIATOR_STRUCT typedef struct packed { \ + logic [AW-1:0] prim_awaddr ; \ + logic prim_awvalid ; \ + logic [$bits(axi_pkg::axi_burst_e)] prim_awburst ; \ + logic [2:0] prim_awsize ; \ + logic [7:0] prim_awlen ; \ + logic [UW-1:0] prim_awuser ; \ + logic [IW-1:0] prim_awid ; \ + logic prim_awlock ; \ + logic [DW-1:0] prim_wdata ; \ + logic [DW/8 - 1:0] prim_wstrb ; \ + logic prim_wvalid ; \ + logic prim_wlast ; \ + logic prim_bready ; \ + } fuse_ctrl_prim_axi_write_in_initiator_s; + + `define fuse_ctrl_prim_axi_write_in_TO_INITIATOR_STRUCT_FUNCTION \ + virtual function fuse_ctrl_prim_axi_write_in_initiator_s to_initiator_struct();\ + fuse_ctrl_prim_axi_write_in_initiator_struct = \ + {\ + this.prim_awaddr , \ + this.prim_awvalid , \ + this.prim_awburst , \ + this.prim_awsize , \ + this.prim_awlen , \ + this.prim_awuser , \ + this.prim_awid , \ + this.prim_awlock , \ + this.prim_wdata , \ + this.prim_wstrb , \ + this.prim_wvalid , \ + this.prim_wlast , \ + this.prim_bready \ + };\ + return ( fuse_ctrl_prim_axi_write_in_initiator_struct);\ + endfunction + + `define fuse_ctrl_prim_axi_write_in_FROM_INITIATOR_STRUCT_FUNCTION \ + virtual function void from_initiator_struct(fuse_ctrl_prim_axi_write_in_initiator_s fuse_ctrl_prim_axi_write_in_initiator_struct);\ + {\ + this.prim_awaddr , \ + this.prim_awvalid , \ + this.prim_awburst , \ + this.prim_awsize , \ + this.prim_awlen , \ + this.prim_awuser , \ + this.prim_awid , \ + this.prim_awlock , \ + this.prim_wdata , \ + this.prim_wstrb , \ + this.prim_wvalid , \ + this.prim_wlast , \ + this.prim_bready \ + } = fuse_ctrl_prim_axi_write_in_initiator_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_responder_struct +// and from_responder_struct methods of the fuse_ctrl_prim_axi_write_in_transaction class. +// Also update the comments in the driver BFM. +// + `define fuse_ctrl_prim_axi_write_in_RESPONDER_STRUCT typedef struct packed { \ + logic [AW-1:0] prim_awaddr ; \ + logic prim_awvalid ; \ + logic [$bits(axi_pkg::axi_burst_e)] prim_awburst ; \ + logic [2:0] prim_awsize ; \ + logic [7:0] prim_awlen ; \ + logic [UW-1:0] prim_awuser ; \ + logic [IW-1:0] prim_awid ; \ + logic prim_awlock ; \ + logic [DW-1:0] prim_wdata ; \ + logic [DW/8 - 1:0] prim_wstrb ; \ + logic prim_wvalid ; \ + logic prim_wlast ; \ + logic prim_bready ; \ + } fuse_ctrl_prim_axi_write_in_responder_s; + + `define fuse_ctrl_prim_axi_write_in_TO_RESPONDER_STRUCT_FUNCTION \ + virtual function fuse_ctrl_prim_axi_write_in_responder_s to_responder_struct();\ + fuse_ctrl_prim_axi_write_in_responder_struct = \ + {\ + this.prim_awaddr , \ + this.prim_awvalid , \ + this.prim_awburst , \ + this.prim_awsize , \ + this.prim_awlen , \ + this.prim_awuser , \ + this.prim_awid , \ + this.prim_awlock , \ + this.prim_wdata , \ + this.prim_wstrb , \ + this.prim_wvalid , \ + this.prim_wlast , \ + this.prim_bready \ + };\ + return ( fuse_ctrl_prim_axi_write_in_responder_struct);\ + endfunction + + `define fuse_ctrl_prim_axi_write_in_FROM_RESPONDER_STRUCT_FUNCTION \ + virtual function void from_responder_struct(fuse_ctrl_prim_axi_write_in_responder_s fuse_ctrl_prim_axi_write_in_responder_struct);\ + {\ + this.prim_awaddr , \ + this.prim_awvalid , \ + this.prim_awburst , \ + this.prim_awsize , \ + this.prim_awlen , \ + this.prim_awuser , \ + this.prim_awid , \ + this.prim_awlock , \ + this.prim_wdata , \ + this.prim_wstrb , \ + this.prim_wvalid , \ + this.prim_wlast , \ + this.prim_bready \ + } = fuse_ctrl_prim_axi_write_in_responder_struct;\ + endfunction +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_monitor.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_monitor.svh new file mode 100644 index 0000000..4deee8c --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_monitor.svh @@ -0,0 +1,131 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class receives fuse_ctrl_prim_axi_write_in transactions observed by the +// fuse_ctrl_prim_axi_write_in monitor BFM and broadcasts them through the analysis port +// on the agent. It accesses the monitor BFM through the monitor +// task. This UVM component captures transactions +// for viewing in the waveform viewer if the +// enable_transaction_viewing flag is set in the configuration. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_write_in_monitor #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvmf_monitor_base #( + .CONFIG_T(fuse_ctrl_prim_axi_write_in_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .BFM_BIND_T(virtual fuse_ctrl_prim_axi_write_in_monitor_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .TRANS_T(fuse_ctrl_prim_axi_write_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +)); + + `uvm_component_param_utils( fuse_ctrl_prim_axi_write_in_monitor #( + AW, + DW, + IW, + UW + ) +) + +// Structure used to pass data from monitor BFM to monitor class in agent. +// Use to_monitor_struct function to pack transaction variables into structure. +// Use from_monitor_struct function to unpack transaction variables from structure. +`fuse_ctrl_prim_axi_write_in_MONITOR_STRUCT + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the monitor BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// monitor BFM. This allows the monitor BFM to call the notify_transaction +// function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// *************************************************************************** + virtual task run_phase(uvm_phase phase); + // Start monitor BFM thread and don't call super.run() in order to + // override the default monitor proxy 'pull' behavior with the more + // emulation-friendly BFM 'push' approach using the notify_transaction + // function below + bfm.start_monitoring(); + endtask + +// ************************************************************************** + +// This function is called by the monitor BFM. It receives data observed by the +// monitor BFM. Data is passed using the fuse_ctrl_prim_axi_write_in_monitor_struct. + virtual function void notify_transaction(input fuse_ctrl_prim_axi_write_in_monitor_s fuse_ctrl_prim_axi_write_in_monitor_struct); + + + trans = new("trans"); + trans.from_monitor_struct(fuse_ctrl_prim_axi_write_in_monitor_struct); + trans.start_time = time_stamp; + trans.end_time = $time; + time_stamp = trans.end_time; + + analyze(trans); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_monitor_bfm.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_monitor_bfm.sv new file mode 100644 index 0000000..80b4df5 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_monitor_bfm.sv @@ -0,0 +1,248 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface performs the fuse_ctrl_prim_axi_write_in signal monitoring. +// It is accessed by the uvm fuse_ctrl_prim_axi_write_in monitor through a virtual +// interface handle in the fuse_ctrl_prim_axi_write_in configuration. It monitors the +// signals passed in through the port connection named bus of +// type fuse_ctrl_prim_axi_write_in_if. +// +// Input signals from the fuse_ctrl_prim_axi_write_in_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// Interface functions and tasks used by UVM components: +// monitor(inout TRANS_T txn); +// This task receives the transaction, txn, from the +// UVM monitor and then populates variables in txn +// from values observed on bus activity. This task +// blocks until an operation on the fuse_ctrl_prim_axi_write_in bus is complete. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_prim_axi_write_in_pkg_hdl::*; +`include "src/fuse_ctrl_prim_axi_write_in_macros.svh" + + +interface fuse_ctrl_prim_axi_write_in_monitor_bfm #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + + ( fuse_ctrl_prim_axi_write_in_if bus ); + // The pragma below and additional ones in-lined further down are for running this BFM on Veloce + // pragma attribute fuse_ctrl_prim_axi_write_in_monitor_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: AW=%x DW=%x IW=%x UW=%x ", AW,DW,IW,UW), + UVM_DEBUG) +end +`endif + + + // Structure used to pass transaction data from monitor BFM to monitor class in agent. +`fuse_ctrl_prim_axi_write_in_MONITOR_STRUCT + fuse_ctrl_prim_axi_write_in_monitor_s fuse_ctrl_prim_axi_write_in_monitor_struct; + + // Structure used to pass configuration data from monitor class to monitor BFM. + `fuse_ctrl_prim_axi_write_in_CONFIGURATION_STRUCT + + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + tri clk_i_i; + tri rst_ni_i; + tri [AW-1:0] awaddr_i; + tri [$bits(axi_pkg::axi_burst_e)-1:0] awburst_i; + tri [2:0] awsize_i; + tri [7:0] awlen_i; + tri [UW-1:0] awuser_i; + tri [UW-1:0] awid_i; + tri awlock_i; + tri awvalid_i; + tri [DW-1:0] wdata_i; + tri [DW/8-1:0] wstrb_i; + tri wvalid_i; + tri wlast_i; + tri bready_i; + assign clk_i_i = bus.clk_i; + assign rst_ni_i = bus.rst_ni; + assign awaddr_i = bus.awaddr; + assign awburst_i = bus.awburst; + assign awsize_i = bus.awsize; + assign awlen_i = bus.awlen; + assign awuser_i = bus.awuser; + assign awid_i = bus.awid; + assign awlock_i = bus.awlock; + assign awvalid_i = bus.awvalid; + assign wdata_i = bus.wdata; + assign wstrb_i = bus.wstrb; + assign wvalid_i = bus.wvalid; + assign wlast_i = bus.wlast; + assign bready_i = bus.bready; + + // Proxy handle to UVM monitor + fuse_ctrl_prim_axi_write_in_pkg::fuse_ctrl_prim_axi_write_in_monitor #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + proxy; + // pragma tbx oneway proxy.notify_transaction + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + task wait_for_reset();// pragma tbx xtf + @(posedge clk_i_i) ; + do_wait_for_reset(); + endtask + + // **************************************************************************** + task do_wait_for_reset(); + // pragma uvmf custom reset_condition begin + wait ( rst_ni_i === 1 ) ; + @(posedge clk_i_i) ; + // pragma uvmf custom reset_condition end + endtask + + //****************************************************************** + + task wait_for_num_clocks(input int unsigned count); // pragma tbx xtf + @(posedge clk_i_i); + + repeat (count-1) @(posedge clk_i_i); + endtask + + //****************************************************************** + event go; + function void start_monitoring();// pragma tbx xtf + -> go; + endfunction + + // **************************************************************************** + initial begin + @go; + forever begin + @(posedge clk_i_i); + do_monitor( fuse_ctrl_prim_axi_write_in_monitor_struct ); + + + proxy.notify_transaction( fuse_ctrl_prim_axi_write_in_monitor_struct ); + + end + end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the monitor BFM. It is called by the monitor within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the monitor BFM needs to be aware of the new configuration + // variables. + // + function void configure(fuse_ctrl_prim_axi_write_in_configuration_s fuse_ctrl_prim_axi_write_in_configuration_arg); // pragma tbx xtf + initiator_responder = fuse_ctrl_prim_axi_write_in_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + + + // **************************************************************************** + + task do_monitor(output fuse_ctrl_prim_axi_write_in_monitor_s fuse_ctrl_prim_axi_write_in_monitor_struct); + // + // Available struct members: + // // fuse_ctrl_prim_axi_write_in_monitor_struct.prim_awaddr + // // fuse_ctrl_prim_axi_write_in_monitor_struct.prim_awvalid + // // fuse_ctrl_prim_axi_write_in_monitor_struct.prim_awburst + // // fuse_ctrl_prim_axi_write_in_monitor_struct.prim_awsize + // // fuse_ctrl_prim_axi_write_in_monitor_struct.prim_awlen + // // fuse_ctrl_prim_axi_write_in_monitor_struct.prim_awuser + // // fuse_ctrl_prim_axi_write_in_monitor_struct.prim_awid + // // fuse_ctrl_prim_axi_write_in_monitor_struct.prim_awlock + // // fuse_ctrl_prim_axi_write_in_monitor_struct.prim_wdata + // // fuse_ctrl_prim_axi_write_in_monitor_struct.prim_wstrb + // // fuse_ctrl_prim_axi_write_in_monitor_struct.prim_wvalid + // // fuse_ctrl_prim_axi_write_in_monitor_struct.prim_wlast + // // fuse_ctrl_prim_axi_write_in_monitor_struct.prim_bready + // // + // Reference code; + // How to wait for signal value + // while (control_signal === 1'b1) @(posedge clk_i_i); + // + // How to assign a struct member, named xyz, from a signal. + // All available input signals listed. + // fuse_ctrl_prim_axi_write_in_monitor_struct.xyz = awaddr_i; // [AW-1:0] + // fuse_ctrl_prim_axi_write_in_monitor_struct.xyz = awburst_i; // [$bits(axi_pkg::axi_burst_e)-1:0] + // fuse_ctrl_prim_axi_write_in_monitor_struct.xyz = awsize_i; // [2:0] + // fuse_ctrl_prim_axi_write_in_monitor_struct.xyz = awlen_i; // [7:0] + // fuse_ctrl_prim_axi_write_in_monitor_struct.xyz = awuser_i; // [UW-1:0] + // fuse_ctrl_prim_axi_write_in_monitor_struct.xyz = awid_i; // [UW-1:0] + // fuse_ctrl_prim_axi_write_in_monitor_struct.xyz = awlock_i; // + // fuse_ctrl_prim_axi_write_in_monitor_struct.xyz = awvalid_i; // + // fuse_ctrl_prim_axi_write_in_monitor_struct.xyz = wdata_i; // [DW-1:0] + // fuse_ctrl_prim_axi_write_in_monitor_struct.xyz = wstrb_i; // [DW/8-1:0] + // fuse_ctrl_prim_axi_write_in_monitor_struct.xyz = wvalid_i; // + // fuse_ctrl_prim_axi_write_in_monitor_struct.xyz = wlast_i; // + // fuse_ctrl_prim_axi_write_in_monitor_struct.xyz = bready_i; // + // pragma uvmf custom do_monitor begin + // UVMF_CHANGE_ME : Implement protocol monitoring. The commented reference code + // below are examples of how to capture signal values and assign them to + // structure members. All available input signals are listed. The 'while' + // code example shows how to wait for a synchronous flow control signal. This + // task should return when a complete transfer has been observed. Once this task is + // exited with captured values, it is then called again to wait for and observe + // the next transfer. One clock cycle is consumed between calls to do_monitor. + @(posedge clk_i_i); + @(posedge clk_i_i); + @(posedge clk_i_i); + @(posedge clk_i_i); + // pragma uvmf custom do_monitor end + endtask + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_random_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_random_sequence.svh new file mode 100644 index 0000000..5b9a8e5 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_random_sequence.svh @@ -0,0 +1,91 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This sequences randomizes the fuse_ctrl_prim_axi_write_in transaction and sends it +// to the UVM driver. +// +// This sequence constructs and randomizes a fuse_ctrl_prim_axi_write_in_transaction. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_write_in_random_sequence #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + + extends fuse_ctrl_prim_axi_write_in_sequence_base #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +; + + `uvm_object_param_utils( fuse_ctrl_prim_axi_write_in_random_sequence #( + AW, + DW, + IW, + UW + ) +) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //***************************************************************** + function new(string name = ""); + super.new(name); + endfunction: new + + // **************************************************************************** + // TASK : body() + // This task is automatically executed when this sequence is started using the + // start(sequencerHandle) task. + // + task body(); + + // Construct the transaction + req=fuse_ctrl_prim_axi_write_in_transaction#( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +::type_id::create("req"); + start_item(req); + // Randomize the transaction + if(!req.randomize()) `uvm_fatal("SEQ", "fuse_ctrl_prim_axi_write_in_random_sequence::body()-fuse_ctrl_prim_axi_write_in_transaction randomization failed") + // Send the transaction to the fuse_ctrl_prim_axi_write_in_driver_bfm via the sequencer and fuse_ctrl_prim_axi_write_in_driver. + finish_item(req); + `uvm_info("SEQ", {"Response:",req.convert2string()},UVM_MEDIUM) + + endtask + +endclass: fuse_ctrl_prim_axi_write_in_random_sequence + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_responder_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_responder_sequence.svh new file mode 100644 index 0000000..e8be306 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_responder_sequence.svh @@ -0,0 +1,87 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class can be used to provide stimulus when an interface +// has been configured to run in a responder mode. It +// will never finish by default, always going back to the driver +// and driver BFM for the next transaction with which to respond. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_write_in_responder_sequence #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + + extends fuse_ctrl_prim_axi_write_in_sequence_base #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +; + + `uvm_object_param_utils( fuse_ctrl_prim_axi_write_in_responder_sequence #( + AW, + DW, + IW, + UW + ) +) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "fuse_ctrl_prim_axi_write_in_responder_sequence"); + super.new(name); + endfunction + + task body(); + req=fuse_ctrl_prim_axi_write_in_transaction#( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +::type_id::create("req"); + forever begin + start_item(req); + finish_item(req); + // pragma uvmf custom body begin + // UVMF_CHANGE_ME : Do something here with the resulting req item. The + // finish_item() call above will block until the req transaction is ready + // to be handled by the responder sequence. + // If this was an item that required a response, the expectation is + // that the response should be populated within this transaction now. + `uvm_info("SEQ",$sformatf("Processed txn: %s",req.convert2string()),UVM_HIGH) + // pragma uvmf custom body end + end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_sequence_base.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_sequence_base.svh new file mode 100644 index 0000000..2d40c99 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_sequence_base.svh @@ -0,0 +1,146 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the class used as the base class for all sequences +// for this interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_write_in_sequence_base #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvmf_sequence_base #( + .REQ(fuse_ctrl_prim_axi_write_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .RSP(fuse_ctrl_prim_axi_write_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +)); + + `uvm_object_param_utils( fuse_ctrl_prim_axi_write_in_sequence_base #( + AW, + DW, + IW, + UW + ) +) + + // variables + typedef fuse_ctrl_prim_axi_write_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + fuse_ctrl_prim_axi_write_in_transaction_req_t; + fuse_ctrl_prim_axi_write_in_transaction_req_t req; + typedef fuse_ctrl_prim_axi_write_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + fuse_ctrl_prim_axi_write_in_transaction_rsp_t; + fuse_ctrl_prim_axi_write_in_transaction_rsp_t rsp; + + // Event for identifying when a response was received from the sequencer + event new_rsp; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // TASK : get_responses() + // This task recursively gets sequence item responses from the sequencer. + // + virtual task get_responses(); + fork + begin + // Block until new rsp available + get_response(rsp); + // New rsp received. Indicate to sequence using event. + ->new_rsp; + // Display the received response transaction + `uvm_info("SEQ", {"New response transaction:",rsp.convert2string()}, UVM_MEDIUM) + end + join_none + endtask + + // **************************************************************************** + // TASK : pre_body() + // This task is called automatically when start is called with call_pre_post set to 1 (default). + // By calling get_responses() within pre_body() any derived sequences are automatically + // processing response transactions. Only un-comment this call to get_responses() if you + // have configured the interface driver to utilize the response transaction path by setting + // the configuration variable "return_transaction_response" to 1. Otherwise it is possible + // to impact runtime performance and memory utilization. + // + virtual task pre_body(); + // pragma uvmf custom pre_body begin +// get_responses(); + // pragma uvmf custom pre_body end + endtask + + // **************************************************************************** + // TASK : body() + // This task is called automatically when start is called. This sequence sends + // a req sequence item to the sequencer identified as an argument in the call + // to start. + // + virtual task body(); + // pragma uvmf custom body begin + start_item(req); + finish_item(req); + // pragma uvmf custom body end + endtask + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name =""); + super.new( name ); + // pragma uvmf custom new begin + req = fuse_ctrl_prim_axi_write_in_transaction_req_t::type_id::create("req"); + rsp = fuse_ctrl_prim_axi_write_in_transaction_rsp_t::type_id::create("rsp"); + // pragma uvmf custom new end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_transaction.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_transaction.svh new file mode 100644 index 0000000..e58f4ec --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_transaction.svh @@ -0,0 +1,256 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class defines the variables required for an fuse_ctrl_prim_axi_write_in +// transaction. Class variables to be displayed in waveform transaction +// viewing are added to the transaction viewing stream in the add_to_wave +// function. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_write_in_transaction #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvmf_transaction_base; + + `uvm_object_param_utils( fuse_ctrl_prim_axi_write_in_transaction #( + AW, + DW, + IW, + UW + ) +) + + rand logic [AW-1:0] prim_awaddr ; + logic prim_awvalid ; + logic [$bits(axi_pkg::axi_burst_e)] prim_awburst ; + logic [2:0] prim_awsize ; + logic [7:0] prim_awlen ; + logic [UW-1:0] prim_awuser ; + logic [IW-1:0] prim_awid ; + logic prim_awlock ; + logic [DW-1:0] prim_wdata ; + logic [DW/8 - 1:0] prim_wstrb ; + logic prim_wvalid ; + logic prim_wlast ; + logic prim_bready ; + + //Constraints for the transaction variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //******************************************************************* + //******************************************************************* + // Macros that define structs and associated functions are + // located in fuse_ctrl_prim_axi_write_in_macros.svh + + //******************************************************************* + // Monitor macro used by fuse_ctrl_prim_axi_write_in_monitor and fuse_ctrl_prim_axi_write_in_monitor_bfm + // This struct is defined in fuse_ctrl_prim_axi_write_in_macros.svh + `fuse_ctrl_prim_axi_write_in_MONITOR_STRUCT + fuse_ctrl_prim_axi_write_in_monitor_s fuse_ctrl_prim_axi_write_in_monitor_struct; + //******************************************************************* + // FUNCTION: to_monitor_struct() + // This function packs transaction variables into a fuse_ctrl_prim_axi_write_in_monitor_s + // structure. The function returns the handle to the fuse_ctrl_prim_axi_write_in_monitor_struct. + // This function is defined in fuse_ctrl_prim_axi_write_in_macros.svh + `fuse_ctrl_prim_axi_write_in_TO_MONITOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_monitor_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_prim_axi_write_in_macros.svh + `fuse_ctrl_prim_axi_write_in_FROM_MONITOR_STRUCT_FUNCTION + + //******************************************************************* + // Initiator macro used by fuse_ctrl_prim_axi_write_in_driver and fuse_ctrl_prim_axi_write_in_driver_bfm + // to communicate initiator driven data to fuse_ctrl_prim_axi_write_in_driver_bfm. + // This struct is defined in fuse_ctrl_prim_axi_write_in_macros.svh + `fuse_ctrl_prim_axi_write_in_INITIATOR_STRUCT + fuse_ctrl_prim_axi_write_in_initiator_s fuse_ctrl_prim_axi_write_in_initiator_struct; + //******************************************************************* + // FUNCTION: to_initiator_struct() + // This function packs transaction variables into a fuse_ctrl_prim_axi_write_in_initiator_s + // structure. The function returns the handle to the fuse_ctrl_prim_axi_write_in_initiator_struct. + // This function is defined in fuse_ctrl_prim_axi_write_in_macros.svh + `fuse_ctrl_prim_axi_write_in_TO_INITIATOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_initiator_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_prim_axi_write_in_macros.svh + `fuse_ctrl_prim_axi_write_in_FROM_INITIATOR_STRUCT_FUNCTION + + //******************************************************************* + // Responder macro used by fuse_ctrl_prim_axi_write_in_driver and fuse_ctrl_prim_axi_write_in_driver_bfm + // to communicate Responder driven data to fuse_ctrl_prim_axi_write_in_driver_bfm. + // This struct is defined in fuse_ctrl_prim_axi_write_in_macros.svh + `fuse_ctrl_prim_axi_write_in_RESPONDER_STRUCT + fuse_ctrl_prim_axi_write_in_responder_s fuse_ctrl_prim_axi_write_in_responder_struct; + //******************************************************************* + // FUNCTION: to_responder_struct() + // This function packs transaction variables into a fuse_ctrl_prim_axi_write_in_responder_s + // structure. The function returns the handle to the fuse_ctrl_prim_axi_write_in_responder_struct. + // This function is defined in fuse_ctrl_prim_axi_write_in_macros.svh + `fuse_ctrl_prim_axi_write_in_TO_RESPONDER_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_responder_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_prim_axi_write_in_macros.svh + `fuse_ctrl_prim_axi_write_in_FROM_RESPONDER_STRUCT_FUNCTION + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + endfunction + + // **************************************************************************** + // FUNCTION: convert2string() + // This function converts all variables in this class to a single string for + // logfile reporting. + // + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + // UVMF_CHANGE_ME : Customize format if desired. + return $sformatf("prim_awaddr:0x%x prim_awvalid:0x%x prim_awburst:0x%x prim_awsize:0x%x prim_awlen:0x%x prim_awuser:0x%x prim_awid:0x%x prim_awlock:0x%x prim_wdata:0x%x prim_wstrb:0x%x prim_wvalid:0x%x prim_wlast:0x%x prim_bready:0x%x ",prim_awaddr,prim_awvalid,prim_awburst,prim_awsize,prim_awlen,prim_awuser,prim_awid,prim_awlock,prim_wdata,prim_wstrb,prim_wvalid,prim_wlast,prim_bready); + // pragma uvmf custom convert2string end + endfunction + + //******************************************************************* + // FUNCTION: do_print() + // This function is automatically called when the .print() function + // is called on this class. + // + virtual function void do_print(uvm_printer printer); + // pragma uvmf custom do_print begin + // UVMF_CHANGE_ME : Current contents of do_print allows for the use of UVM 1.1d, 1.2 or P1800.2. + // Update based on your own printing preference according to your preferred UVM version + $display(convert2string()); + // pragma uvmf custom do_print end + endfunction + + //******************************************************************* + // FUNCTION: do_compare() + // This function is automatically called when the .compare() function + // is called on this class. + // + virtual function bit do_compare (uvm_object rhs, uvm_comparer comparer); + fuse_ctrl_prim_axi_write_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + RHS; + if (!$cast(RHS,rhs)) return 0; + // pragma uvmf custom do_compare begin + // UVMF_CHANGE_ME : Eliminate comparison of variables not to be used for compare + return (super.do_compare(rhs,comparer) + &&(this.prim_wdata == RHS.prim_wdata) + ); + // pragma uvmf custom do_compare end + endfunction + + //******************************************************************* + // FUNCTION: do_copy() + // This function is automatically called when the .copy() function + // is called on this class. + // + virtual function void do_copy (uvm_object rhs); + fuse_ctrl_prim_axi_write_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + RHS; + assert($cast(RHS,rhs)); + // pragma uvmf custom do_copy begin + super.do_copy(rhs); + this.prim_awaddr = RHS.prim_awaddr; + this.prim_awvalid = RHS.prim_awvalid; + this.prim_awburst = RHS.prim_awburst; + this.prim_awsize = RHS.prim_awsize; + this.prim_awlen = RHS.prim_awlen; + this.prim_awuser = RHS.prim_awuser; + this.prim_awid = RHS.prim_awid; + this.prim_awlock = RHS.prim_awlock; + this.prim_wdata = RHS.prim_wdata; + this.prim_wstrb = RHS.prim_wstrb; + this.prim_wvalid = RHS.prim_wvalid; + this.prim_wlast = RHS.prim_wlast; + this.prim_bready = RHS.prim_bready; + // pragma uvmf custom do_copy end + endfunction + + // **************************************************************************** + // FUNCTION: add_to_wave() + // This function is used to display variables in this class in the waveform + // viewer. The start_time and end_time variables must be set before this + // function is called. If the start_time and end_time variables are not set + // the transaction will be hidden at 0ns on the waveform display. + // + virtual function void add_to_wave(int transaction_viewing_stream_h); + `ifdef QUESTA + if (transaction_view_h == 0) begin + transaction_view_h = $begin_transaction(transaction_viewing_stream_h,"fuse_ctrl_prim_axi_write_in_transaction",start_time); + end + super.add_to_wave(transaction_view_h); + // pragma uvmf custom add_to_wave begin + // UVMF_CHANGE_ME : Color can be applied to transaction entries based on content, example below + // case() + // 1 : $add_color(transaction_view_h,"red"); + // default : $add_color(transaction_view_h,"grey"); + // endcase + // UVMF_CHANGE_ME : Eliminate transaction variables not wanted in transaction viewing in the waveform viewer + $add_attribute(transaction_view_h,prim_awaddr,"prim_awaddr"); + $add_attribute(transaction_view_h,prim_awvalid,"prim_awvalid"); + $add_attribute(transaction_view_h,prim_awburst,"prim_awburst"); + $add_attribute(transaction_view_h,prim_awsize,"prim_awsize"); + $add_attribute(transaction_view_h,prim_awlen,"prim_awlen"); + $add_attribute(transaction_view_h,prim_awuser,"prim_awuser"); + $add_attribute(transaction_view_h,prim_awid,"prim_awid"); + $add_attribute(transaction_view_h,prim_awlock,"prim_awlock"); + $add_attribute(transaction_view_h,prim_wdata,"prim_wdata"); + $add_attribute(transaction_view_h,prim_wstrb,"prim_wstrb"); + $add_attribute(transaction_view_h,prim_wvalid,"prim_wvalid"); + $add_attribute(transaction_view_h,prim_wlast,"prim_wlast"); + $add_attribute(transaction_view_h,prim_bready,"prim_bready"); + // pragma uvmf custom add_to_wave end + $end_transaction(transaction_view_h,end_time); + $free_transaction(transaction_view_h); + `endif // QUESTA + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_transaction_coverage.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_transaction_coverage.svh new file mode 100644 index 0000000..30d005a --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_transaction_coverage.svh @@ -0,0 +1,114 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class records fuse_ctrl_prim_axi_write_in transaction information using +// a covergroup named fuse_ctrl_prim_axi_write_in_transaction_cg. An instance of this +// coverage component is instantiated in the uvmf_parameterized_agent +// if the has_coverage flag is set. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_write_in_transaction_coverage #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvm_subscriber #(.T(fuse_ctrl_prim_axi_write_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +)); + + `uvm_component_param_utils( fuse_ctrl_prim_axi_write_in_transaction_coverage #( + AW, + DW, + IW, + UW + ) +) + + T coverage_trans; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + covergroup fuse_ctrl_prim_axi_write_in_transaction_cg; + // pragma uvmf custom covergroup begin + // UVMF_CHANGE_ME : Add coverage bins, crosses, exclusions, etc. according to coverage needs. + option.auto_bin_max=1024; + option.per_instance=1; + prim_awaddr: coverpoint coverage_trans.prim_awaddr; + prim_awvalid: coverpoint coverage_trans.prim_awvalid; + prim_awburst: coverpoint coverage_trans.prim_awburst; + prim_awsize: coverpoint coverage_trans.prim_awsize; + prim_awlen: coverpoint coverage_trans.prim_awlen; + prim_awuser: coverpoint coverage_trans.prim_awuser; + prim_awid: coverpoint coverage_trans.prim_awid; + prim_awlock: coverpoint coverage_trans.prim_awlock; + prim_wdata: coverpoint coverage_trans.prim_wdata; + prim_wstrb: coverpoint coverage_trans.prim_wstrb; + prim_wvalid: coverpoint coverage_trans.prim_wvalid; + prim_wlast: coverpoint coverage_trans.prim_wlast; + prim_bready: coverpoint coverage_trans.prim_bready; + // pragma uvmf custom covergroup end + endgroup + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new(string name="", uvm_component parent=null); + super.new(name,parent); + fuse_ctrl_prim_axi_write_in_transaction_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that transaction variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + endfunction + + // **************************************************************************** + // FUNCTION : build_phase() + // This function is the standard UVM build_phase. + // + function void build_phase(uvm_phase phase); + fuse_ctrl_prim_axi_write_in_transaction_cg.set_inst_name($sformatf("fuse_ctrl_prim_axi_write_in_transaction_cg_%s",get_full_name())); + endfunction + + // **************************************************************************** + // FUNCTION: write (T t) + // This function is automatically executed when a transaction arrives on the + // analysis_export. It copies values from the variables in the transaction + // to local variables used to collect functional coverage. + // + virtual function void write (T t); + `uvm_info("COV","Received transaction",UVM_HIGH); + coverage_trans = t; + fuse_ctrl_prim_axi_write_in_transaction_cg.sample(); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_typedefs.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_typedefs.svh new file mode 100644 index 0000000..f2a7bdb --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_typedefs.svh @@ -0,0 +1,34 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the host server when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_typedefs_hdl.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_typedefs_hdl.svh new file mode 100644 index 0000000..0d58518 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/src/fuse_ctrl_prim_axi_write_in_typedefs_hdl.svh @@ -0,0 +1,35 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the emulator when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/yaml/fuse_ctrl_prim_axi_write_in_interface.yaml b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/yaml/fuse_ctrl_prim_axi_write_in_interface.yaml new file mode 100644 index 0000000..ec7591e --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_in_pkg/yaml/fuse_ctrl_prim_axi_write_in_interface.yaml @@ -0,0 +1,161 @@ +uvmf: + interfaces: + fuse_ctrl_prim_axi_write_in: + clock: clk_i + config_constraints: [] + config_vars: [] + existing_library_component: 'True' + gen_inbound_streaming_driver: 'False' + hdl_pkg_parameters: [] + hdl_typedefs: [] + hvl_pkg_parameters: [] + hvl_typedefs: [] + parameters: + - name: AW + type: int + value: '32' + - name: DW + type: int + value: '32' + - name: IW + type: int + value: '3' + - name: UW + type: int + value: '32' + ports: + - dir: output + name: awaddr + reset_value: '''bz' + width: '[''AW'']' + - dir: output + name: awburst + reset_value: '''bz' + width: '[''$bits(axi_pkg::axi_burst_e)'']' + - dir: output + name: awsize + reset_value: '''bz' + width: '3' + - dir: output + name: awlen + reset_value: '''bz' + width: '8' + - dir: output + name: awuser + reset_value: '''bz' + width: '[''UW'']' + - dir: output + name: awid + reset_value: '''bz' + width: '[''UW'']' + - dir: output + name: awlock + reset_value: '''bz' + width: '1' + - dir: output + name: awvalid + reset_value: '''bz' + width: '1' + - dir: output + name: wdata + reset_value: '''bz' + width: '[''DW'']' + - dir: output + name: wstrb + reset_value: '''bz' + width: '[''DW/8'']' + - dir: output + name: wvalid + reset_value: '''bz' + width: '1' + - dir: output + name: wlast + reset_value: '''bz' + width: '1' + - dir: output + name: bready + reset_value: '''bz' + width: '1' + reset: rst_ni + reset_assertion_level: 'False' + transaction_constraints: [] + transaction_vars: + - comment: '' + iscompare: 'False' + isrand: 'True' + name: prim_awaddr + type: logic [AW-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: prim_awvalid + type: logic + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: prim_awburst + type: logic [$bits(axi_pkg::axi_burst_e)] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: prim_awsize + type: logic [2:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: prim_awlen + type: logic [7:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: prim_awuser + type: logic [UW-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: prim_awid + type: logic [IW-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: prim_awlock + type: logic + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'False' + name: prim_wdata + type: logic [DW-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: prim_wstrb + type: logic [DW/8 - 1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: prim_wvalid + type: logic + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: prim_wlast + type: logic + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: prim_bready + type: logic + unpacked_dimension: '' + use_dpi_link: 'False' diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/.project b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/.project new file mode 100644 index 0000000..3e0bf6c --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/.project @@ -0,0 +1,30 @@ + + + fuse_ctrl_prim_axi_write_out_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/.svproject b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/.svproject new file mode 100644 index 0000000..376273a --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/Makefile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/Makefile new file mode 100644 index 0000000..7bd75ac --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/Makefile @@ -0,0 +1,66 @@ +# fuse_ctrl_prim_axi_write_out interface packages source +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +fuse_ctrl_prim_axi_write_out_PKG = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_write_out_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_filelist_hvl.f + +fuse_ctrl_prim_axi_write_out_PKG_HDL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_write_out_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_filelist_hdl.f + +fuse_ctrl_prim_axi_write_out_PKG_XRTL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_write_out_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_filelist_xrtl.f + +COMP_fuse_ctrl_prim_axi_write_out_PKG_TGT_0 = q_comp_fuse_ctrl_prim_axi_write_out_pkg +COMP_fuse_ctrl_prim_axi_write_out_PKG_TGT_1 = v_comp_fuse_ctrl_prim_axi_write_out_pkg +COMP_fuse_ctrl_prim_axi_write_out_PKG_TGT = $(COMP_fuse_ctrl_prim_axi_write_out_PKG_TGT_$(USE_VELOCE)) + +comp_fuse_ctrl_prim_axi_write_out_pkg: $(COMP_fuse_ctrl_prim_axi_write_out_PKG_TGT) + +q_comp_fuse_ctrl_prim_axi_write_out_pkg: + $(HDL_COMP_CMD) $(fuse_ctrl_prim_axi_write_out_PKG_HDL) + $(HVL_COMP_CMD) $(fuse_ctrl_prim_axi_write_out_PKG) + $(HDL_COMP_CMD) $(fuse_ctrl_prim_axi_write_out_PKG_XRTL) + +v_comp_fuse_ctrl_prim_axi_write_out_pkg: + $(HVL_COMP_CMD) $(fuse_ctrl_prim_axi_write_out_PKG_HDL) + $(HVL_COMP_CMD) $(fuse_ctrl_prim_axi_write_out_PKG) + $(VELANALYZE_CMD) $(fuse_ctrl_prim_axi_write_out_PKG_HDL) + $(VELANALYZE_HVL_CMD) $(fuse_ctrl_prim_axi_write_out_PKG) + $(HDL_COMP_CMD) $(fuse_ctrl_prim_axi_write_out_PKG_XRTL) + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export fuse_ctrl_prim_axi_write_out_IF_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/dpi + +C_FILE_COMPILE_LIST_fuse_ctrl_prim_axi_write_out_pkg = \ + +O_FILE_COMPILE_LIST_fuse_ctrl_prim_axi_write_out_pkg = $(notdir $(C_FILE_COMPILE_LIST_fuse_ctrl_prim_axi_write_out_pkg:.c=.o)) + +GCC_COMP_ARGS_fuse_ctrl_prim_axi_write_out_pkg += -I$(fuse_ctrl_prim_axi_write_out_IF_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_fuse_ctrl_prim_axi_write_out_pkg += $(fuse_ctrl_prim_axi_write_out_IF_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_fuse_ctrl_prim_axi_write_out_pkg += \ + \ + -o .so + +comp_fuse_ctrl_prim_axi_write_out_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Interface C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_fuse_ctrl_prim_axi_write_out_pkg) $(C_FILE_COMPILE_LIST_fuse_ctrl_prim_axi_write_out_pkg) + @echo "--------------------------------" + @echo "Linking Interface C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_fuse_ctrl_prim_axi_write_out_pkg) $(O_FILE_COMPILE_LIST_fuse_ctrl_prim_axi_write_out_pkg) + @echo "--------------------------------" + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/compile.do b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/compile.do new file mode 100644 index 0000000..2728571 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/compile.do @@ -0,0 +1,14 @@ +# Tcl do file for compile of fuse_ctrl_prim_axi_write_out interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_write_out_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_filelist_hdl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_write_out_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_filelist_hvl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_write_out_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_filelist_xrtl.f \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out.compile new file mode 100644 index 0000000..fa21f0f --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out.compile @@ -0,0 +1,3 @@ +needs: + - fuse_ctrl_prim_axi_write_out_hvl.compile + - fuse_ctrl_prim_axi_write_out_hdl.compile diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_bfm.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_bfm.vinfo new file mode 100644 index 0000000..708c584 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_bfm.vinfo @@ -0,0 +1,6 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use fuse_ctrl_prim_axi_write_out_pkg_hdl.vinfo ++incdir+@vinfodir +src/fuse_ctrl_prim_axi_write_out_if.sv +src/fuse_ctrl_prim_axi_write_out_driver_bfm.sv +src/fuse_ctrl_prim_axi_write_out_monitor_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_common.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_common.compile new file mode 100644 index 0000000..ba5ad35 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_common.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +incdir: + - . + - ${uvm_path}/src +src: + - fuse_ctrl_prim_axi_write_out_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_filelist_hdl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_filelist_hdl.f new file mode 100644 index 0000000..6b9dd5f --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_filelist_hdl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_filelist_hvl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_filelist_hvl.f new file mode 100644 index 0000000..6aea297 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_filelist_hvl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_pkg.sv \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_filelist_xrtl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_filelist_xrtl.f new file mode 100644 index 0000000..3c62931 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_filelist_xrtl.f @@ -0,0 +1,3 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_if.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_monitor_bfm.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_driver_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_hdl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_hdl.compile new file mode 100644 index 0000000..1a738c1 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_hdl.compile @@ -0,0 +1,9 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ./fuse_ctrl_prim_axi_write_out_common.compile +incdir: + - . +src: + - src/fuse_ctrl_prim_axi_write_out_if.sv + - src/fuse_ctrl_prim_axi_write_out_monitor_bfm.sv + - src/fuse_ctrl_prim_axi_write_out_driver_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_hvl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_hvl.compile new file mode 100644 index 0000000..894eaaf --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_hvl.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ./fuse_ctrl_prim_axi_write_out_common.compile +incdir: + - . +src: + - fuse_ctrl_prim_axi_write_out_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_pkg.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_pkg.sv new file mode 100644 index 0000000..50f57ff --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_pkg.sv @@ -0,0 +1,91 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - + +// - +// - +// - + +// - +// - +// - + +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_prim_axi_write_out_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg_hdl::*; + import uvmf_base_pkg::*; + import fuse_ctrl_prim_axi_write_out_pkg_hdl::*; + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + `include "src/fuse_ctrl_prim_axi_write_out_macros.svh" + + export fuse_ctrl_prim_axi_write_out_pkg_hdl::*; + + + + // Parameters defined as HVL parameters + + `include "src/fuse_ctrl_prim_axi_write_out_typedefs.svh" + `include "src/fuse_ctrl_prim_axi_write_out_transaction.svh" + + `include "src/fuse_ctrl_prim_axi_write_out_configuration.svh" + `include "src/fuse_ctrl_prim_axi_write_out_driver.svh" + `include "src/fuse_ctrl_prim_axi_write_out_monitor.svh" + + `include "src/fuse_ctrl_prim_axi_write_out_transaction_coverage.svh" + `include "src/fuse_ctrl_prim_axi_write_out_sequence_base.svh" + `include "src/fuse_ctrl_prim_axi_write_out_random_sequence.svh" + + `include "src/fuse_ctrl_prim_axi_write_out_responder_sequence.svh" + `include "src/fuse_ctrl_prim_axi_write_out2reg_adapter.svh" + + `include "src/fuse_ctrl_prim_axi_write_out_agent.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new interface sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the interface package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_pkg.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_pkg.vinfo new file mode 100644 index 0000000..790347e --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_pkg.vinfo @@ -0,0 +1,4 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use fuse_ctrl_prim_axi_write_out_pkg_hdl.vinfo ++incdir+@vinfodir +fuse_ctrl_prim_axi_write_out_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_pkg_hdl.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_pkg_hdl.sv new file mode 100644 index 0000000..bd64b4e --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_pkg_hdl.sv @@ -0,0 +1,52 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that needs to be compiled and synthesized +// for running on Veloce. +// +// CONTAINS: +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_prim_axi_write_out_pkg_hdl; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HDL parameters + + `include "src/fuse_ctrl_prim_axi_write_out_typedefs_hdl.svh" + `include "src/fuse_ctrl_prim_axi_write_out_macros.svh" + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_pkg_hdl.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_pkg_hdl.vinfo new file mode 100644 index 0000000..dfc2d8e --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_pkg_hdl.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +fuse_ctrl_prim_axi_write_out_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_pkg_sve.F b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_pkg_sve.F new file mode 100644 index 0000000..9a71aaf --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_pkg_sve.F @@ -0,0 +1,10 @@ +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + ++incdir+. +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_filelist_hdl.f +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/fuse_ctrl_prim_axi_write_out_filelist_hvl.f diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out2reg_adapter.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out2reg_adapter.svh new file mode 100644 index 0000000..34b91af --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out2reg_adapter.svh @@ -0,0 +1,142 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the UVM register adapter for the fuse_ctrl_prim_axi_write_out interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_write_out2reg_adapter #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvm_reg_adapter; + + `uvm_object_param_utils( fuse_ctrl_prim_axi_write_out2reg_adapter #( + AW, + DW, + IW, + UW + ) +) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //-------------------------------------------------------------------- + // new + //-------------------------------------------------------------------- + function new (string name = "fuse_ctrl_prim_axi_write_out2reg_adapter" ); + super.new(name); + // pragma uvmf custom new begin + // UVMF_CHANGE_ME : Configure the adapter regarding byte enables and provides response. + + // Does the protocol the Agent is modeling support byte enables? + // 0 = NO + // 1 = YES + supports_byte_enable = 0; + + // Does the Agent's Driver provide separate response sequence items? + // i.e. Does the driver call seq_item_port.put() + // and do the sequences call get_response()? + // 0 = NO + // 1 = YES + provides_responses = 0; + // pragma uvmf custom new end + + endfunction: new + + //-------------------------------------------------------------------- + // reg2bus + //-------------------------------------------------------------------- + virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw); + + fuse_ctrl_prim_axi_write_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + trans_h = fuse_ctrl_prim_axi_write_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +::type_id::create("trans_h"); + + // pragma uvmf custom reg2bus begin + // UVMF_CHANGE_ME : Fill in the reg2bus adapter mapping registe fields to protocol fields. + + //Adapt the following for your sequence item type + // trans_h.op = (rw.kind == UVM_READ) ? WB_READ : WB_WRITE; + //Copy over address + // trans_h.addr = rw.addr; + //Copy over write data + // trans_h.data = rw.data; + + // pragma uvmf custom reg2bus end + + // Return the adapted transaction + return trans_h; + + endfunction: reg2bus + + //-------------------------------------------------------------------- + // bus2reg + //-------------------------------------------------------------------- + virtual function void bus2reg(uvm_sequence_item bus_item, + ref uvm_reg_bus_op rw); + fuse_ctrl_prim_axi_write_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + trans_h; + if (!$cast(trans_h, bus_item)) begin + `uvm_fatal("ADAPT","Provided bus_item is not of the correct type") + return; + end + // pragma uvmf custom bus2reg begin + // UVMF_CHANGE_ME : Fill in the bus2reg adapter mapping protocol fields to register fields. + //Adapt the following for your sequence item type + //Copy over instruction type + // rw.kind = (trans_h.op == WB_WRITE) ? UVM_WRITE : UVM_READ; + //Copy over address + // rw.addr = trans_h.addr; + //Copy over read data + // rw.data = trans_h.data; + //Check for errors on the bus and return UVM_NOT_OK if there is an error + // rw.status = UVM_IS_OK; + // pragma uvmf custom bus2reg end + + endfunction: bus2reg + +endclass : fuse_ctrl_prim_axi_write_out2reg_adapter + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_agent.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_agent.svh new file mode 100644 index 0000000..0622fae --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_agent.svh @@ -0,0 +1,109 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: Protocol specific agent class definition +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_write_out_agent #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvmf_parameterized_agent #( + .CONFIG_T(fuse_ctrl_prim_axi_write_out_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .DRIVER_T(fuse_ctrl_prim_axi_write_out_driver #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .MONITOR_T(fuse_ctrl_prim_axi_write_out_monitor #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .COVERAGE_T(fuse_ctrl_prim_axi_write_out_transaction_coverage #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .TRANS_T(fuse_ctrl_prim_axi_write_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +) + ); + + `uvm_component_param_utils( fuse_ctrl_prim_axi_write_out_agent #( + AW, + DW, + IW, + UW + ) +) + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** + // FUNCTION: build_phase + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + if (configuration.active_passive == ACTIVE) begin + // Place sequencer handle into configuration object + // so that it may be retrieved from configuration + // rather than using uvm_config_db + configuration.sequencer = this.sequencer; + end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_configuration.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_configuration.svh new file mode 100644 index 0000000..2440f40 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_configuration.svh @@ -0,0 +1,241 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class contains all variables and functions used +// to configure the fuse_ctrl_prim_axi_write_out agent and its bfm's. It gets the +// bfm's from the uvm_config_db for use by the agent. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_write_out_configuration #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvmf_parameterized_agent_configuration_base #( + .DRIVER_BFM_BIND_T(virtual fuse_ctrl_prim_axi_write_out_driver_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .MONITOR_BFM_BIND_T( virtual fuse_ctrl_prim_axi_write_out_monitor_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +)); + + `uvm_object_param_utils( fuse_ctrl_prim_axi_write_out_configuration #( + AW, + DW, + IW, + UW + ) +) + + + // Sequencer handle populated by agent + uvm_sequencer #(fuse_ctrl_prim_axi_write_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + ) sequencer; + + //Constraints for the configuration variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + covergroup fuse_ctrl_prim_axi_write_out_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + // pragma uvmf custom covergroup end + endgroup + + //******************************************************************* + //******************************************************************* + // Structure used to pass configuration variables to monitor and driver BFM's. + // Use to_struct function to pack variables into structure. + // Use from_struct function to unpack variables from structure. + // This structure is defined in fuse_ctrl_prim_axi_write_out_macros.svh + `fuse_ctrl_prim_axi_write_out_CONFIGURATION_STRUCT + fuse_ctrl_prim_axi_write_out_configuration_s fuse_ctrl_prim_axi_write_out_configuration_struct; + //******************************************************************* + // FUNCTION: to_struct() + // This function packs variables into a fuse_ctrl_prim_axi_write_out_configuration_s + // structure. The function returns the handle to the fuse_ctrl_prim_axi_write_out_configuration_struct. + // This function is defined in fuse_ctrl_prim_axi_write_out_macros.svh + `fuse_ctrl_prim_axi_write_out_CONFIGURATION_TO_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_struct() + // This function unpacks the struct provided as an argument into + // variables of this class. + // This function is defined in fuse_ctrl_prim_axi_write_out_macros.svh + `fuse_ctrl_prim_axi_write_out_CONFIGURATION_FROM_STRUCT_FUNCTION + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + // Construct the covergroup for this configuration class + fuse_ctrl_prim_axi_write_out_configuration_cg = new; + endfunction + + // **************************************************************************** + // FUNCTION: post_randomize() + // This function is automatically called after the randomize() function + // is executed. + // + function void post_randomize(); + super.post_randomize(); + fuse_ctrl_prim_axi_write_out_configuration_cg.sample(); + endfunction + + // **************************************************************************** + // FUNCTION: initialize + // This function causes the configuration to retrieve + // its virtual interface handle from the uvm_config_db. + // This function also makes itself available to its + // agent through the uvm_config_db. + // + // ARGUMENTS: + // uvmf_active_passive_t activity: + // This argument identifies the simulation level + // as either BLOCK, CHIP, SIMULATION, etc. + // + // AGENT_PATH: + // This argument identifies the path to this + // configurations agent. This configuration + // makes itself available to the agent specified + // by agent_path by placing itself into the + // uvm_config_db. + // + // INTERFACE_NAME: + // This argument identifies the string name of + // this configurations BFM's. This string + // name is used to retrieve the driver and + // monitor BFM from the uvm_config_db. + // + virtual function void initialize(uvmf_active_passive_t activity, + string agent_path, + string interface_name); + + super.initialize( activity, agent_path, interface_name); + // The covergroup is given the same name as the interface + fuse_ctrl_prim_axi_write_out_configuration_cg.set_inst_name(interface_name); + + // This configuration places itself into the uvm_config_db for the agent, identified by the agent_path variable, to retrieve. + uvm_config_db #( fuse_ctrl_prim_axi_write_out_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + + )::set( null ,agent_path,UVMF_AGENT_CONFIG, this ); + + // This configuration also places itself in the config db using the same identifier used by the interface. This allows users to access + // configuration variables and the interface through the bfm api class rather than directly accessing the BFM. This is useful for + // accessingthe BFM when using Veloce + uvm_config_db #( fuse_ctrl_prim_axi_write_out_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + + )::set( null ,UVMF_CONFIGURATIONS, interface_name, this ); + + fuse_ctrl_prim_axi_write_out_configuration_cg.set_inst_name($sformatf("fuse_ctrl_prim_axi_write_out_configuration_cg_%s",get_full_name())); + +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. + `uvm_info("CFG", + $psprintf("The agent at '%s' is using interface named %s has the following parameters: AW=%x DW=%x IW=%x UW=%x ", agent_path, interface_name, AW ,DW ,IW ,UW ), + UVM_DEBUG) + + // pragma uvmf custom initialize begin + // This controls whether or not the agent returns a transaction handle in the driver when calling + // item_done() back into the sequencer or not. If set to 1, a transaction is sent back which means + // the sequence on the other end must use the get_response() part of the driver/sequence API. If + // this doesn't occur, there will eventually be response_queue overflow errors during the test. + return_transaction_response = 1'b0; + + // pragma uvmf custom initialize end + + endfunction + + // **************************************************************************** + // TASK: wait_for_reset + // *[Required]* Blocks until reset is released. The wait_for_reset operation is performed + // by a task in the monitor bfm. + virtual task wait_for_reset(); + monitor_bfm.wait_for_reset(); + endtask + + // **************************************************************************** + // TASK: wait_for_num_clocks + // *[Required]* Blocks until specified number of clocks have elapsed. The wait_for_num_clocks + // operation is performed by a task in the monitor bfm. + virtual task wait_for_num_clocks(int clocks); + monitor_bfm.wait_for_num_clocks(clocks); + endtask + + // **************************************************************************** + // FUNCTION : convert2string() + // This function is used to convert variables in this class into a string for log messaging. + // + virtual function string convert2string (); + // pragma uvmf custom convert2string begin + return $sformatf(""); + // pragma uvmf custom convert2string end + endfunction + + // **************************************************************************** + // FUNCTION: get_sequencer + function uvm_sequencer #(fuse_ctrl_prim_axi_write_out_transaction#( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +) get_sequencer(); + return sequencer; + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_driver.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_driver.svh new file mode 100644 index 0000000..97995a3 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_driver.svh @@ -0,0 +1,141 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class passes transactions between the sequencer +// and the BFM driver interface. It accesses the driver BFM +// through the bfm handle. This driver +// passes transactions to the driver BFM through the access +// task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_write_out_driver #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvmf_driver_base #( + .CONFIG_T(fuse_ctrl_prim_axi_write_out_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + ), + .BFM_BIND_T(virtual fuse_ctrl_prim_axi_write_out_driver_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + ), + .REQ(fuse_ctrl_prim_axi_write_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + ), + .RSP(fuse_ctrl_prim_axi_write_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + )); + + `uvm_component_param_utils( fuse_ctrl_prim_axi_write_out_driver #( + AW, + DW, + IW, + UW + ) +) +//******************************************************************* +// Macros that define structs located in fuse_ctrl_prim_axi_write_out_macros.svh +//******************************************************************* +// Initiator macro used by fuse_ctrl_prim_axi_write_out_driver and fuse_ctrl_prim_axi_write_out_driver_bfm +// to communicate initiator driven data to fuse_ctrl_prim_axi_write_out_driver_bfm. +`fuse_ctrl_prim_axi_write_out_INITIATOR_STRUCT + fuse_ctrl_prim_axi_write_out_initiator_s fuse_ctrl_prim_axi_write_out_initiator_struct; +//******************************************************************* +// Responder macro used by fuse_ctrl_prim_axi_write_out_driver and fuse_ctrl_prim_axi_write_out_driver_bfm +// to communicate Responder driven data to fuse_ctrl_prim_axi_write_out_driver_bfm. +`fuse_ctrl_prim_axi_write_out_RESPONDER_STRUCT + fuse_ctrl_prim_axi_write_out_responder_s fuse_ctrl_prim_axi_write_out_responder_struct; + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent=null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the driver BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// driver BFM. This allows the driver BFM to call tasks and function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// **************************************************************************** +// This task is called by the run_phase in uvmf_driver_base. + virtual task access( inout REQ txn ); +// pragma uvmf custom access begin + if (configuration.initiator_responder==RESPONDER) begin + // Complete current transfer and wait for next transfer + bfm.respond_and_wait_for_next_transfer( + fuse_ctrl_prim_axi_write_out_initiator_struct, + txn.to_responder_struct() + ); + // Unpack information about initiated transfer received by this responder + txn.from_initiator_struct(fuse_ctrl_prim_axi_write_out_initiator_struct); + end else begin + // Initiate a transfer and get response + bfm.initiate_and_get_response( + txn.to_initiator_struct(), + fuse_ctrl_prim_axi_write_out_responder_struct + ); + // Unpack transfer response information received by this initiator + txn.from_responder_struct(fuse_ctrl_prim_axi_write_out_responder_struct); + end +// pragma uvmf custom access end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_driver_bfm.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_driver_bfm.sv new file mode 100644 index 0000000..7e5c72d --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_driver_bfm.sv @@ -0,0 +1,341 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This interface performs the fuse_ctrl_prim_axi_write_out signal driving. It is +// accessed by the uvm fuse_ctrl_prim_axi_write_out driver through a virtual interface +// handle in the fuse_ctrl_prim_axi_write_out configuration. It drives the singals passed +// in through the port connection named bus of type fuse_ctrl_prim_axi_write_out_if. +// +// Input signals from the fuse_ctrl_prim_axi_write_out_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// This bfm drives signals with a _o suffix. These signals +// are driven onto signals within fuse_ctrl_prim_axi_write_out_if based on INITIATOR/RESPONDER and/or +// ARBITRATION/GRANT status. +// +// The output signal connections are as follows: +// signal_o -> bus.signal +// +// +// Interface functions and tasks used by UVM components: +// +// configure: +// This function gets configuration attributes from the +// UVM driver to set any required BFM configuration +// variables such as 'initiator_responder'. +// +// initiate_and_get_response: +// This task is used to perform signaling activity for initiating +// a protocol transfer. The task initiates the transfer, using +// input data from the initiator struct. Then the task captures +// response data, placing the data into the response struct. +// The response struct is returned to the driver class. +// +// respond_and_wait_for_next_transfer: +// This task is used to complete a current transfer as a responder +// and then wait for the initiator to start the next transfer. +// The task uses data in the responder struct to drive protocol +// signals to complete the transfer. The task then waits for +// the next transfer. Once the next transfer begins, data from +// the initiator is placed into the initiator struct and sent +// to the responder sequence for processing to determine +// what data to respond with. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_prim_axi_write_out_pkg_hdl::*; +`include "src/fuse_ctrl_prim_axi_write_out_macros.svh" + +interface fuse_ctrl_prim_axi_write_out_driver_bfm #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + + (fuse_ctrl_prim_axi_write_out_if bus); + // The following pragma and additional ones in-lined further below are for running this BFM on Veloce + // pragma attribute fuse_ctrl_prim_axi_write_out_driver_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: AW=%x DW=%x IW=%x UW=%x ", AW,DW,IW,UW), + UVM_DEBUG) +end +`endif + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + tri clk_i_i; + tri rst_ni_i; + + // Signal list (all signals are capable of being inputs and outputs for the sake + // of supporting both INITIATOR and RESPONDER mode operation. Expectation is that + // directionality in the config file was from the point-of-view of the INITIATOR + + // INITIATOR mode input signals + tri awready_i; + reg awready_o = 'bz; + tri wready_i; + reg wready_o = 'bz; + tri [$bits(axi_pkg::axi_burst_e)-1:0] bresp_i; + reg [$bits(axi_pkg::axi_burst_e)-1:0] bresp_o = 'bz; + tri bid_i; + reg bid_o = 'bz; + tri bvalid_i; + reg bvalid_o = 'bz; + + // INITIATOR mode output signals + + // Bi-directional signals + + + assign clk_i_i = bus.clk_i; + assign rst_ni_i = bus.rst_ni; + + // These are signals marked as 'input' by the config file, but the signals will be + // driven by this BFM if put into RESPONDER mode (flipping all signal directions around) + assign awready_i = bus.awready; + assign bus.awready = (initiator_responder == RESPONDER) ? awready_o : 'bz; + assign wready_i = bus.wready; + assign bus.wready = (initiator_responder == RESPONDER) ? wready_o : 'bz; + assign bresp_i = bus.bresp; + assign bus.bresp = (initiator_responder == RESPONDER) ? bresp_o : 'bz; + assign bid_i = bus.bid; + assign bus.bid = (initiator_responder == RESPONDER) ? bid_o : 'bz; + assign bvalid_i = bus.bvalid; + assign bus.bvalid = (initiator_responder == RESPONDER) ? bvalid_o : 'bz; + + + // These are signals marked as 'output' by the config file, but the outputs will + // not be driven by this BFM unless placed in INITIATOR mode. + + // Proxy handle to UVM driver + fuse_ctrl_prim_axi_write_out_pkg::fuse_ctrl_prim_axi_write_out_driver #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + proxy; + // pragma tbx oneway proxy.my_function_name_in_uvm_driver + + // **************************************************************************** + // **************************************************************************** + // Macros that define structs located in fuse_ctrl_prim_axi_write_out_macros.svh + // **************************************************************************** + // Struct for passing configuration data from fuse_ctrl_prim_axi_write_out_driver to this BFM + // **************************************************************************** + `fuse_ctrl_prim_axi_write_out_CONFIGURATION_STRUCT + // **************************************************************************** + // Structs for INITIATOR and RESPONDER data flow + //******************************************************************* + // Initiator macro used by fuse_ctrl_prim_axi_write_out_driver and fuse_ctrl_prim_axi_write_out_driver_bfm + // to communicate initiator driven data to fuse_ctrl_prim_axi_write_out_driver_bfm. + `fuse_ctrl_prim_axi_write_out_INITIATOR_STRUCT + fuse_ctrl_prim_axi_write_out_initiator_s initiator_struct; + // Responder macro used by fuse_ctrl_prim_axi_write_out_driver and fuse_ctrl_prim_axi_write_out_driver_bfm + // to communicate Responder driven data to fuse_ctrl_prim_axi_write_out_driver_bfm. + `fuse_ctrl_prim_axi_write_out_RESPONDER_STRUCT + fuse_ctrl_prim_axi_write_out_responder_s responder_struct; + + // **************************************************************************** +// pragma uvmf custom reset_condition_and_response begin + // Always block used to return signals to reset value upon assertion of reset + always @( negedge rst_ni_i ) + begin + // RESPONDER mode output signals + awready_o <= 'bz; + wready_o <= 'bz; + bresp_o <= 'bz; + bid_o <= 'bz; + bvalid_o <= 'bz; + // INITIATOR mode output signals + // Bi-directional signals + + end +// pragma uvmf custom reset_condition_and_response end + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the driver BFM. It is called by the driver within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the driver BFM needs to be aware of the new configuration + // variables. + // + + function void configure(fuse_ctrl_prim_axi_write_out_configuration_s fuse_ctrl_prim_axi_write_out_configuration_arg); // pragma tbx xtf + initiator_responder = fuse_ctrl_prim_axi_write_out_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + +// pragma uvmf custom initiate_and_get_response begin +// **************************************************************************** +// UVMF_CHANGE_ME +// This task is used by an initator. The task first initiates a transfer then +// waits for the responder to complete the transfer. + task initiate_and_get_response( + // This argument passes transaction variables used by an initiator + // to perform the initial part of a protocol transfer. The values + // come from a sequence item created in a sequence. + input fuse_ctrl_prim_axi_write_out_initiator_s fuse_ctrl_prim_axi_write_out_initiator_struct, + // This argument is used to send data received from the responder + // back to the sequence item. The sequence item is returned to the sequence. + output fuse_ctrl_prim_axi_write_out_responder_s fuse_ctrl_prim_axi_write_out_responder_struct + );// pragma tbx xtf + // + // Members within the fuse_ctrl_prim_axi_write_out_initiator_struct: + // logic prim_awready ; + // logic prim_wready ; + // axi_pkg::axi_burst_e prim_bresp ; + // logic prim_bid ; + // logic prim_bvalid ; + // Members within the fuse_ctrl_prim_axi_write_out_responder_struct: + // logic prim_awready ; + // logic prim_wready ; + // axi_pkg::axi_burst_e prim_bresp ; + // logic prim_bid ; + // logic prim_bvalid ; + initiator_struct = fuse_ctrl_prim_axi_write_out_initiator_struct; + // + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clk_i_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available initiator input and inout signals listed. + // Initiator input signals + // fuse_ctrl_prim_axi_write_out_responder_struct.xyz = awready_i; // + // fuse_ctrl_prim_axi_write_out_responder_struct.xyz = wready_i; // + // fuse_ctrl_prim_axi_write_out_responder_struct.xyz = bresp_i; // [$bits(axi_pkg::axi_burst_e)-1:0] + // fuse_ctrl_prim_axi_write_out_responder_struct.xyz = bid_i; // + // fuse_ctrl_prim_axi_write_out_responder_struct.xyz = bvalid_i; // + // Initiator inout signals + // How to assign a signal from an initiator struct member named xyz. + // All available initiator output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Initiator output signals + // Initiator inout signals + // Initiate a transfer using the data received. + @(posedge clk_i_i); + @(posedge clk_i_i); + // Wait for the responder to complete the transfer then place the responder data into + // fuse_ctrl_prim_axi_write_out_responder_struct. + @(posedge clk_i_i); + @(posedge clk_i_i); + responder_struct = fuse_ctrl_prim_axi_write_out_responder_struct; + endtask +// pragma uvmf custom initiate_and_get_response end + +// pragma uvmf custom respond_and_wait_for_next_transfer begin +// **************************************************************************** +// The first_transfer variable is used to prevent completing a transfer in the +// first call to this task. For the first call to this task, there is not +// current transfer to complete. +bit first_transfer=1; + +// UVMF_CHANGE_ME +// This task is used by a responder. The task first completes the current +// transfer in progress then waits for the initiator to start the next transfer. + task respond_and_wait_for_next_transfer( + // This argument is used to send data received from the initiator + // back to the sequence item. The sequence determines how to respond. + output fuse_ctrl_prim_axi_write_out_initiator_s fuse_ctrl_prim_axi_write_out_initiator_struct, + // This argument passes transaction variables used by a responder + // to complete a protocol transfer. The values come from a sequence item. + input fuse_ctrl_prim_axi_write_out_responder_s fuse_ctrl_prim_axi_write_out_responder_struct + );// pragma tbx xtf + // Variables within the fuse_ctrl_prim_axi_write_out_initiator_struct: + // logic prim_awready ; + // logic prim_wready ; + // axi_pkg::axi_burst_e prim_bresp ; + // logic prim_bid ; + // logic prim_bvalid ; + // Variables within the fuse_ctrl_prim_axi_write_out_responder_struct: + // logic prim_awready ; + // logic prim_wready ; + // axi_pkg::axi_burst_e prim_bresp ; + // logic prim_bid ; + // logic prim_bvalid ; + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clk_i_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available responder input and inout signals listed. + // Responder input signals + // Responder inout signals + // How to assign a signal, named xyz, from an initiator struct member. + // All available responder output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Responder output signals + // awready_o <= fuse_ctrl_prim_axi_write_out_initiator_struct.xyz; // + // wready_o <= fuse_ctrl_prim_axi_write_out_initiator_struct.xyz; // + // bresp_o <= fuse_ctrl_prim_axi_write_out_initiator_struct.xyz; // [$bits(axi_pkg::axi_burst_e)-1:0] + // bid_o <= fuse_ctrl_prim_axi_write_out_initiator_struct.xyz; // + // bvalid_o <= fuse_ctrl_prim_axi_write_out_initiator_struct.xyz; // + // Responder inout signals + + @(posedge clk_i_i); + if (!first_transfer) begin + // Perform transfer response here. + // Reply using data recieved in the fuse_ctrl_prim_axi_write_out_responder_struct. + @(posedge clk_i_i); + // Reply using data recieved in the transaction handle. + @(posedge clk_i_i); + end + // Wait for next transfer then gather info from intiator about the transfer. + // Place the data into the fuse_ctrl_prim_axi_write_out_initiator_struct. + @(posedge clk_i_i); + @(posedge clk_i_i); + first_transfer = 0; + endtask +// pragma uvmf custom respond_and_wait_for_next_transfer end + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_if.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_if.sv new file mode 100644 index 0000000..66c2c91 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_if.sv @@ -0,0 +1,104 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface contains the fuse_ctrl_prim_axi_write_out interface signals. +// It is instantiated once per fuse_ctrl_prim_axi_write_out bus. Bus Functional Models, +// BFM's named fuse_ctrl_prim_axi_write_out_driver_bfm, are used to drive signals on the bus. +// BFM's named fuse_ctrl_prim_axi_write_out_monitor_bfm are used to monitor signals on the +// bus. This interface signal bundle is passed in the port list of +// the BFM in order to give the BFM access to the signals in this +// interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// This template can be used to connect a DUT to these signals +// +// .dut_signal_port(fuse_ctrl_prim_axi_write_out_bus.awready), // Agent input +// .dut_signal_port(fuse_ctrl_prim_axi_write_out_bus.wready), // Agent input +// .dut_signal_port(fuse_ctrl_prim_axi_write_out_bus.bresp), // Agent input +// .dut_signal_port(fuse_ctrl_prim_axi_write_out_bus.bid), // Agent input +// .dut_signal_port(fuse_ctrl_prim_axi_write_out_bus.bvalid), // Agent input + +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_prim_axi_write_out_pkg_hdl::*; + +interface fuse_ctrl_prim_axi_write_out_if #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + + + ( + input tri clk_i, + input tri rst_ni, + inout tri awready, + inout tri wready, + inout tri [$bits(axi_pkg::axi_burst_e)-1:0] bresp, + inout tri bid, + inout tri bvalid + ); + +modport monitor_port + ( + input clk_i, + input rst_ni, + input awready, + input wready, + input bresp, + input bid, + input bvalid + ); + +modport initiator_port + ( + input clk_i, + input rst_ni, + input awready, + input wready, + input bresp, + input bid, + input bvalid + ); + +modport responder_port + ( + input clk_i, + input rst_ni, + output awready, + output wready, + output bresp, + output bid, + output bvalid + ); + + +// pragma uvmf custom interface_item_additional begin +// pragma uvmf custom interface_item_additional end + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_infact_coverage_strategy.csv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_infact_coverage_strategy.csv new file mode 100644 index 0000000..1c218e1 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_infact_coverage_strategy.csv @@ -0,0 +1,6 @@ +Global +auto_bin_max, 64 + +Name,Type,Include +rand_fields,coverpoint,=rand *.** + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_macros.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_macros.svh new file mode 100644 index 0000000..28bfd68 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_macros.svh @@ -0,0 +1,171 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains macros used with the fuse_ctrl_prim_axi_write_out package. +// These macros include packed struct definitions. These structs are +// used to pass data between classes, hvl, and BFM's, hdl. Use of +// structs are more efficient and simpler to modify. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_struct +// and from_struct methods defined in the macros below that are used in +// the fuse_ctrl_prim_axi_write_out_configuration class. +// + `define fuse_ctrl_prim_axi_write_out_CONFIGURATION_STRUCT \ +typedef struct packed { \ + uvmf_active_passive_t active_passive; \ + uvmf_initiator_responder_t initiator_responder; \ + } fuse_ctrl_prim_axi_write_out_configuration_s; + + `define fuse_ctrl_prim_axi_write_out_CONFIGURATION_TO_STRUCT_FUNCTION \ + virtual function fuse_ctrl_prim_axi_write_out_configuration_s to_struct();\ + fuse_ctrl_prim_axi_write_out_configuration_struct = \ + {\ + this.active_passive,\ + this.initiator_responder\ + };\ + return ( fuse_ctrl_prim_axi_write_out_configuration_struct );\ + endfunction + + `define fuse_ctrl_prim_axi_write_out_CONFIGURATION_FROM_STRUCT_FUNCTION \ + virtual function void from_struct(fuse_ctrl_prim_axi_write_out_configuration_s fuse_ctrl_prim_axi_write_out_configuration_struct);\ + {\ + this.active_passive,\ + this.initiator_responder \ + } = fuse_ctrl_prim_axi_write_out_configuration_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_monitor_struct +// and from_monitor_struct methods of the fuse_ctrl_prim_axi_write_out_transaction class. +// + `define fuse_ctrl_prim_axi_write_out_MONITOR_STRUCT typedef struct packed { \ + logic prim_awready ; \ + logic prim_wready ; \ + axi_pkg::axi_burst_e prim_bresp ; \ + logic prim_bid ; \ + logic prim_bvalid ; \ + } fuse_ctrl_prim_axi_write_out_monitor_s; + + `define fuse_ctrl_prim_axi_write_out_TO_MONITOR_STRUCT_FUNCTION \ + virtual function fuse_ctrl_prim_axi_write_out_monitor_s to_monitor_struct();\ + fuse_ctrl_prim_axi_write_out_monitor_struct = \ + { \ + this.prim_awready , \ + this.prim_wready , \ + this.prim_bresp , \ + this.prim_bid , \ + this.prim_bvalid \ + };\ + return ( fuse_ctrl_prim_axi_write_out_monitor_struct);\ + endfunction\ + + `define fuse_ctrl_prim_axi_write_out_FROM_MONITOR_STRUCT_FUNCTION \ + virtual function void from_monitor_struct(fuse_ctrl_prim_axi_write_out_monitor_s fuse_ctrl_prim_axi_write_out_monitor_struct);\ + {\ + this.prim_awready , \ + this.prim_wready , \ + this.prim_bresp , \ + this.prim_bid , \ + this.prim_bvalid \ + } = fuse_ctrl_prim_axi_write_out_monitor_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_initiator_struct +// and from_initiator_struct methods of the fuse_ctrl_prim_axi_write_out_transaction class. +// Also update the comments in the driver BFM. +// + `define fuse_ctrl_prim_axi_write_out_INITIATOR_STRUCT typedef struct packed { \ + logic prim_awready ; \ + logic prim_wready ; \ + axi_pkg::axi_burst_e prim_bresp ; \ + logic prim_bid ; \ + logic prim_bvalid ; \ + } fuse_ctrl_prim_axi_write_out_initiator_s; + + `define fuse_ctrl_prim_axi_write_out_TO_INITIATOR_STRUCT_FUNCTION \ + virtual function fuse_ctrl_prim_axi_write_out_initiator_s to_initiator_struct();\ + fuse_ctrl_prim_axi_write_out_initiator_struct = \ + {\ + this.prim_awready , \ + this.prim_wready , \ + this.prim_bresp , \ + this.prim_bid , \ + this.prim_bvalid \ + };\ + return ( fuse_ctrl_prim_axi_write_out_initiator_struct);\ + endfunction + + `define fuse_ctrl_prim_axi_write_out_FROM_INITIATOR_STRUCT_FUNCTION \ + virtual function void from_initiator_struct(fuse_ctrl_prim_axi_write_out_initiator_s fuse_ctrl_prim_axi_write_out_initiator_struct);\ + {\ + this.prim_awready , \ + this.prim_wready , \ + this.prim_bresp , \ + this.prim_bid , \ + this.prim_bvalid \ + } = fuse_ctrl_prim_axi_write_out_initiator_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_responder_struct +// and from_responder_struct methods of the fuse_ctrl_prim_axi_write_out_transaction class. +// Also update the comments in the driver BFM. +// + `define fuse_ctrl_prim_axi_write_out_RESPONDER_STRUCT typedef struct packed { \ + logic prim_awready ; \ + logic prim_wready ; \ + axi_pkg::axi_burst_e prim_bresp ; \ + logic prim_bid ; \ + logic prim_bvalid ; \ + } fuse_ctrl_prim_axi_write_out_responder_s; + + `define fuse_ctrl_prim_axi_write_out_TO_RESPONDER_STRUCT_FUNCTION \ + virtual function fuse_ctrl_prim_axi_write_out_responder_s to_responder_struct();\ + fuse_ctrl_prim_axi_write_out_responder_struct = \ + {\ + this.prim_awready , \ + this.prim_wready , \ + this.prim_bresp , \ + this.prim_bid , \ + this.prim_bvalid \ + };\ + return ( fuse_ctrl_prim_axi_write_out_responder_struct);\ + endfunction + + `define fuse_ctrl_prim_axi_write_out_FROM_RESPONDER_STRUCT_FUNCTION \ + virtual function void from_responder_struct(fuse_ctrl_prim_axi_write_out_responder_s fuse_ctrl_prim_axi_write_out_responder_struct);\ + {\ + this.prim_awready , \ + this.prim_wready , \ + this.prim_bresp , \ + this.prim_bid , \ + this.prim_bvalid \ + } = fuse_ctrl_prim_axi_write_out_responder_struct;\ + endfunction +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_monitor.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_monitor.svh new file mode 100644 index 0000000..db0d6bb --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_monitor.svh @@ -0,0 +1,131 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class receives fuse_ctrl_prim_axi_write_out transactions observed by the +// fuse_ctrl_prim_axi_write_out monitor BFM and broadcasts them through the analysis port +// on the agent. It accesses the monitor BFM through the monitor +// task. This UVM component captures transactions +// for viewing in the waveform viewer if the +// enable_transaction_viewing flag is set in the configuration. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_write_out_monitor #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvmf_monitor_base #( + .CONFIG_T(fuse_ctrl_prim_axi_write_out_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .BFM_BIND_T(virtual fuse_ctrl_prim_axi_write_out_monitor_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .TRANS_T(fuse_ctrl_prim_axi_write_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +)); + + `uvm_component_param_utils( fuse_ctrl_prim_axi_write_out_monitor #( + AW, + DW, + IW, + UW + ) +) + +// Structure used to pass data from monitor BFM to monitor class in agent. +// Use to_monitor_struct function to pack transaction variables into structure. +// Use from_monitor_struct function to unpack transaction variables from structure. +`fuse_ctrl_prim_axi_write_out_MONITOR_STRUCT + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the monitor BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// monitor BFM. This allows the monitor BFM to call the notify_transaction +// function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// *************************************************************************** + virtual task run_phase(uvm_phase phase); + // Start monitor BFM thread and don't call super.run() in order to + // override the default monitor proxy 'pull' behavior with the more + // emulation-friendly BFM 'push' approach using the notify_transaction + // function below + bfm.start_monitoring(); + endtask + +// ************************************************************************** + +// This function is called by the monitor BFM. It receives data observed by the +// monitor BFM. Data is passed using the fuse_ctrl_prim_axi_write_out_monitor_struct. + virtual function void notify_transaction(input fuse_ctrl_prim_axi_write_out_monitor_s fuse_ctrl_prim_axi_write_out_monitor_struct); + + + trans = new("trans"); + trans.from_monitor_struct(fuse_ctrl_prim_axi_write_out_monitor_struct); + trans.start_time = time_stamp; + trans.end_time = $time; + time_stamp = trans.end_time; + + analyze(trans); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_monitor_bfm.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_monitor_bfm.sv new file mode 100644 index 0000000..d8a5580 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_monitor_bfm.sv @@ -0,0 +1,216 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface performs the fuse_ctrl_prim_axi_write_out signal monitoring. +// It is accessed by the uvm fuse_ctrl_prim_axi_write_out monitor through a virtual +// interface handle in the fuse_ctrl_prim_axi_write_out configuration. It monitors the +// signals passed in through the port connection named bus of +// type fuse_ctrl_prim_axi_write_out_if. +// +// Input signals from the fuse_ctrl_prim_axi_write_out_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// Interface functions and tasks used by UVM components: +// monitor(inout TRANS_T txn); +// This task receives the transaction, txn, from the +// UVM monitor and then populates variables in txn +// from values observed on bus activity. This task +// blocks until an operation on the fuse_ctrl_prim_axi_write_out bus is complete. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_prim_axi_write_out_pkg_hdl::*; +`include "src/fuse_ctrl_prim_axi_write_out_macros.svh" + + +interface fuse_ctrl_prim_axi_write_out_monitor_bfm #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + + ( fuse_ctrl_prim_axi_write_out_if bus ); + // The pragma below and additional ones in-lined further down are for running this BFM on Veloce + // pragma attribute fuse_ctrl_prim_axi_write_out_monitor_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: AW=%x DW=%x IW=%x UW=%x ", AW,DW,IW,UW), + UVM_DEBUG) +end +`endif + + + // Structure used to pass transaction data from monitor BFM to monitor class in agent. +`fuse_ctrl_prim_axi_write_out_MONITOR_STRUCT + fuse_ctrl_prim_axi_write_out_monitor_s fuse_ctrl_prim_axi_write_out_monitor_struct; + + // Structure used to pass configuration data from monitor class to monitor BFM. + `fuse_ctrl_prim_axi_write_out_CONFIGURATION_STRUCT + + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + tri clk_i_i; + tri rst_ni_i; + tri awready_i; + tri wready_i; + tri [$bits(axi_pkg::axi_burst_e)-1:0] bresp_i; + tri bid_i; + tri bvalid_i; + assign clk_i_i = bus.clk_i; + assign rst_ni_i = bus.rst_ni; + assign awready_i = bus.awready; + assign wready_i = bus.wready; + assign bresp_i = bus.bresp; + assign bid_i = bus.bid; + assign bvalid_i = bus.bvalid; + + // Proxy handle to UVM monitor + fuse_ctrl_prim_axi_write_out_pkg::fuse_ctrl_prim_axi_write_out_monitor #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + proxy; + // pragma tbx oneway proxy.notify_transaction + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + task wait_for_reset();// pragma tbx xtf + @(posedge clk_i_i) ; + do_wait_for_reset(); + endtask + + // **************************************************************************** + task do_wait_for_reset(); + // pragma uvmf custom reset_condition begin + wait ( rst_ni_i === 1 ) ; + @(posedge clk_i_i) ; + // pragma uvmf custom reset_condition end + endtask + + //****************************************************************** + + task wait_for_num_clocks(input int unsigned count); // pragma tbx xtf + @(posedge clk_i_i); + + repeat (count-1) @(posedge clk_i_i); + endtask + + //****************************************************************** + event go; + function void start_monitoring();// pragma tbx xtf + -> go; + endfunction + + // **************************************************************************** + initial begin + @go; + forever begin + @(posedge clk_i_i); + do_monitor( fuse_ctrl_prim_axi_write_out_monitor_struct ); + + + proxy.notify_transaction( fuse_ctrl_prim_axi_write_out_monitor_struct ); + + end + end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the monitor BFM. It is called by the monitor within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the monitor BFM needs to be aware of the new configuration + // variables. + // + function void configure(fuse_ctrl_prim_axi_write_out_configuration_s fuse_ctrl_prim_axi_write_out_configuration_arg); // pragma tbx xtf + initiator_responder = fuse_ctrl_prim_axi_write_out_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + + + // **************************************************************************** + + task do_monitor(output fuse_ctrl_prim_axi_write_out_monitor_s fuse_ctrl_prim_axi_write_out_monitor_struct); + // + // Available struct members: + // // fuse_ctrl_prim_axi_write_out_monitor_struct.prim_awready + // // fuse_ctrl_prim_axi_write_out_monitor_struct.prim_wready + // // fuse_ctrl_prim_axi_write_out_monitor_struct.prim_bresp + // // fuse_ctrl_prim_axi_write_out_monitor_struct.prim_bid + // // fuse_ctrl_prim_axi_write_out_monitor_struct.prim_bvalid + // // + // Reference code; + // How to wait for signal value + // while (control_signal === 1'b1) @(posedge clk_i_i); + // + // How to assign a struct member, named xyz, from a signal. + // All available input signals listed. + // fuse_ctrl_prim_axi_write_out_monitor_struct.xyz = awready_i; // + // fuse_ctrl_prim_axi_write_out_monitor_struct.xyz = wready_i; // + // fuse_ctrl_prim_axi_write_out_monitor_struct.xyz = bresp_i; // [$bits(axi_pkg::axi_burst_e)-1:0] + // fuse_ctrl_prim_axi_write_out_monitor_struct.xyz = bid_i; // + // fuse_ctrl_prim_axi_write_out_monitor_struct.xyz = bvalid_i; // + // pragma uvmf custom do_monitor begin + // UVMF_CHANGE_ME : Implement protocol monitoring. The commented reference code + // below are examples of how to capture signal values and assign them to + // structure members. All available input signals are listed. The 'while' + // code example shows how to wait for a synchronous flow control signal. This + // task should return when a complete transfer has been observed. Once this task is + // exited with captured values, it is then called again to wait for and observe + // the next transfer. One clock cycle is consumed between calls to do_monitor. + @(posedge clk_i_i); + @(posedge clk_i_i); + @(posedge clk_i_i); + @(posedge clk_i_i); + // pragma uvmf custom do_monitor end + endtask + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_random_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_random_sequence.svh new file mode 100644 index 0000000..c5c4919 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_random_sequence.svh @@ -0,0 +1,91 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This sequences randomizes the fuse_ctrl_prim_axi_write_out transaction and sends it +// to the UVM driver. +// +// This sequence constructs and randomizes a fuse_ctrl_prim_axi_write_out_transaction. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_write_out_random_sequence #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + + extends fuse_ctrl_prim_axi_write_out_sequence_base #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +; + + `uvm_object_param_utils( fuse_ctrl_prim_axi_write_out_random_sequence #( + AW, + DW, + IW, + UW + ) +) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //***************************************************************** + function new(string name = ""); + super.new(name); + endfunction: new + + // **************************************************************************** + // TASK : body() + // This task is automatically executed when this sequence is started using the + // start(sequencerHandle) task. + // + task body(); + + // Construct the transaction + req=fuse_ctrl_prim_axi_write_out_transaction#( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +::type_id::create("req"); + start_item(req); + // Randomize the transaction + if(!req.randomize()) `uvm_fatal("SEQ", "fuse_ctrl_prim_axi_write_out_random_sequence::body()-fuse_ctrl_prim_axi_write_out_transaction randomization failed") + // Send the transaction to the fuse_ctrl_prim_axi_write_out_driver_bfm via the sequencer and fuse_ctrl_prim_axi_write_out_driver. + finish_item(req); + `uvm_info("SEQ", {"Response:",req.convert2string()},UVM_MEDIUM) + + endtask + +endclass: fuse_ctrl_prim_axi_write_out_random_sequence + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_responder_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_responder_sequence.svh new file mode 100644 index 0000000..f129205 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_responder_sequence.svh @@ -0,0 +1,87 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class can be used to provide stimulus when an interface +// has been configured to run in a responder mode. It +// will never finish by default, always going back to the driver +// and driver BFM for the next transaction with which to respond. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_write_out_responder_sequence #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + + extends fuse_ctrl_prim_axi_write_out_sequence_base #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +; + + `uvm_object_param_utils( fuse_ctrl_prim_axi_write_out_responder_sequence #( + AW, + DW, + IW, + UW + ) +) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "fuse_ctrl_prim_axi_write_out_responder_sequence"); + super.new(name); + endfunction + + task body(); + req=fuse_ctrl_prim_axi_write_out_transaction#( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +::type_id::create("req"); + forever begin + start_item(req); + finish_item(req); + // pragma uvmf custom body begin + // UVMF_CHANGE_ME : Do something here with the resulting req item. The + // finish_item() call above will block until the req transaction is ready + // to be handled by the responder sequence. + // If this was an item that required a response, the expectation is + // that the response should be populated within this transaction now. + `uvm_info("SEQ",$sformatf("Processed txn: %s",req.convert2string()),UVM_HIGH) + // pragma uvmf custom body end + end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_sequence_base.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_sequence_base.svh new file mode 100644 index 0000000..28cfc04 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_sequence_base.svh @@ -0,0 +1,146 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the class used as the base class for all sequences +// for this interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_write_out_sequence_base #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvmf_sequence_base #( + .REQ(fuse_ctrl_prim_axi_write_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .RSP(fuse_ctrl_prim_axi_write_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +)); + + `uvm_object_param_utils( fuse_ctrl_prim_axi_write_out_sequence_base #( + AW, + DW, + IW, + UW + ) +) + + // variables + typedef fuse_ctrl_prim_axi_write_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + fuse_ctrl_prim_axi_write_out_transaction_req_t; + fuse_ctrl_prim_axi_write_out_transaction_req_t req; + typedef fuse_ctrl_prim_axi_write_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + fuse_ctrl_prim_axi_write_out_transaction_rsp_t; + fuse_ctrl_prim_axi_write_out_transaction_rsp_t rsp; + + // Event for identifying when a response was received from the sequencer + event new_rsp; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // TASK : get_responses() + // This task recursively gets sequence item responses from the sequencer. + // + virtual task get_responses(); + fork + begin + // Block until new rsp available + get_response(rsp); + // New rsp received. Indicate to sequence using event. + ->new_rsp; + // Display the received response transaction + `uvm_info("SEQ", {"New response transaction:",rsp.convert2string()}, UVM_MEDIUM) + end + join_none + endtask + + // **************************************************************************** + // TASK : pre_body() + // This task is called automatically when start is called with call_pre_post set to 1 (default). + // By calling get_responses() within pre_body() any derived sequences are automatically + // processing response transactions. Only un-comment this call to get_responses() if you + // have configured the interface driver to utilize the response transaction path by setting + // the configuration variable "return_transaction_response" to 1. Otherwise it is possible + // to impact runtime performance and memory utilization. + // + virtual task pre_body(); + // pragma uvmf custom pre_body begin +// get_responses(); + // pragma uvmf custom pre_body end + endtask + + // **************************************************************************** + // TASK : body() + // This task is called automatically when start is called. This sequence sends + // a req sequence item to the sequencer identified as an argument in the call + // to start. + // + virtual task body(); + // pragma uvmf custom body begin + start_item(req); + finish_item(req); + // pragma uvmf custom body end + endtask + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name =""); + super.new( name ); + // pragma uvmf custom new begin + req = fuse_ctrl_prim_axi_write_out_transaction_req_t::type_id::create("req"); + rsp = fuse_ctrl_prim_axi_write_out_transaction_rsp_t::type_id::create("rsp"); + // pragma uvmf custom new end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_transaction.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_transaction.svh new file mode 100644 index 0000000..fd93a89 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_transaction.svh @@ -0,0 +1,236 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class defines the variables required for an fuse_ctrl_prim_axi_write_out +// transaction. Class variables to be displayed in waveform transaction +// viewing are added to the transaction viewing stream in the add_to_wave +// function. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_write_out_transaction #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvmf_transaction_base; + + `uvm_object_param_utils( fuse_ctrl_prim_axi_write_out_transaction #( + AW, + DW, + IW, + UW + ) +) + + logic prim_awready ; + logic prim_wready ; + axi_pkg::axi_burst_e prim_bresp ; + logic prim_bid ; + logic prim_bvalid ; + + //Constraints for the transaction variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //******************************************************************* + //******************************************************************* + // Macros that define structs and associated functions are + // located in fuse_ctrl_prim_axi_write_out_macros.svh + + //******************************************************************* + // Monitor macro used by fuse_ctrl_prim_axi_write_out_monitor and fuse_ctrl_prim_axi_write_out_monitor_bfm + // This struct is defined in fuse_ctrl_prim_axi_write_out_macros.svh + `fuse_ctrl_prim_axi_write_out_MONITOR_STRUCT + fuse_ctrl_prim_axi_write_out_monitor_s fuse_ctrl_prim_axi_write_out_monitor_struct; + //******************************************************************* + // FUNCTION: to_monitor_struct() + // This function packs transaction variables into a fuse_ctrl_prim_axi_write_out_monitor_s + // structure. The function returns the handle to the fuse_ctrl_prim_axi_write_out_monitor_struct. + // This function is defined in fuse_ctrl_prim_axi_write_out_macros.svh + `fuse_ctrl_prim_axi_write_out_TO_MONITOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_monitor_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_prim_axi_write_out_macros.svh + `fuse_ctrl_prim_axi_write_out_FROM_MONITOR_STRUCT_FUNCTION + + //******************************************************************* + // Initiator macro used by fuse_ctrl_prim_axi_write_out_driver and fuse_ctrl_prim_axi_write_out_driver_bfm + // to communicate initiator driven data to fuse_ctrl_prim_axi_write_out_driver_bfm. + // This struct is defined in fuse_ctrl_prim_axi_write_out_macros.svh + `fuse_ctrl_prim_axi_write_out_INITIATOR_STRUCT + fuse_ctrl_prim_axi_write_out_initiator_s fuse_ctrl_prim_axi_write_out_initiator_struct; + //******************************************************************* + // FUNCTION: to_initiator_struct() + // This function packs transaction variables into a fuse_ctrl_prim_axi_write_out_initiator_s + // structure. The function returns the handle to the fuse_ctrl_prim_axi_write_out_initiator_struct. + // This function is defined in fuse_ctrl_prim_axi_write_out_macros.svh + `fuse_ctrl_prim_axi_write_out_TO_INITIATOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_initiator_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_prim_axi_write_out_macros.svh + `fuse_ctrl_prim_axi_write_out_FROM_INITIATOR_STRUCT_FUNCTION + + //******************************************************************* + // Responder macro used by fuse_ctrl_prim_axi_write_out_driver and fuse_ctrl_prim_axi_write_out_driver_bfm + // to communicate Responder driven data to fuse_ctrl_prim_axi_write_out_driver_bfm. + // This struct is defined in fuse_ctrl_prim_axi_write_out_macros.svh + `fuse_ctrl_prim_axi_write_out_RESPONDER_STRUCT + fuse_ctrl_prim_axi_write_out_responder_s fuse_ctrl_prim_axi_write_out_responder_struct; + //******************************************************************* + // FUNCTION: to_responder_struct() + // This function packs transaction variables into a fuse_ctrl_prim_axi_write_out_responder_s + // structure. The function returns the handle to the fuse_ctrl_prim_axi_write_out_responder_struct. + // This function is defined in fuse_ctrl_prim_axi_write_out_macros.svh + `fuse_ctrl_prim_axi_write_out_TO_RESPONDER_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_responder_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_prim_axi_write_out_macros.svh + `fuse_ctrl_prim_axi_write_out_FROM_RESPONDER_STRUCT_FUNCTION + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + endfunction + + // **************************************************************************** + // FUNCTION: convert2string() + // This function converts all variables in this class to a single string for + // logfile reporting. + // + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + // UVMF_CHANGE_ME : Customize format if desired. + return $sformatf("prim_awready:0x%x prim_wready:0x%x prim_bresp:0x%x prim_bid:0x%x prim_bvalid:0x%x ",prim_awready,prim_wready,prim_bresp,prim_bid,prim_bvalid); + // pragma uvmf custom convert2string end + endfunction + + //******************************************************************* + // FUNCTION: do_print() + // This function is automatically called when the .print() function + // is called on this class. + // + virtual function void do_print(uvm_printer printer); + // pragma uvmf custom do_print begin + // UVMF_CHANGE_ME : Current contents of do_print allows for the use of UVM 1.1d, 1.2 or P1800.2. + // Update based on your own printing preference according to your preferred UVM version + $display(convert2string()); + // pragma uvmf custom do_print end + endfunction + + //******************************************************************* + // FUNCTION: do_compare() + // This function is automatically called when the .compare() function + // is called on this class. + // + virtual function bit do_compare (uvm_object rhs, uvm_comparer comparer); + fuse_ctrl_prim_axi_write_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + RHS; + if (!$cast(RHS,rhs)) return 0; + // pragma uvmf custom do_compare begin + // UVMF_CHANGE_ME : Eliminate comparison of variables not to be used for compare + return (super.do_compare(rhs,comparer) + &&(this.prim_awready == RHS.prim_awready) + &&(this.prim_wready == RHS.prim_wready) + &&(this.prim_bresp == RHS.prim_bresp) + &&(this.prim_bid == RHS.prim_bid) + &&(this.prim_bvalid == RHS.prim_bvalid) + ); + // pragma uvmf custom do_compare end + endfunction + + //******************************************************************* + // FUNCTION: do_copy() + // This function is automatically called when the .copy() function + // is called on this class. + // + virtual function void do_copy (uvm_object rhs); + fuse_ctrl_prim_axi_write_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + RHS; + assert($cast(RHS,rhs)); + // pragma uvmf custom do_copy begin + super.do_copy(rhs); + this.prim_awready = RHS.prim_awready; + this.prim_wready = RHS.prim_wready; + this.prim_bresp = RHS.prim_bresp; + this.prim_bid = RHS.prim_bid; + this.prim_bvalid = RHS.prim_bvalid; + // pragma uvmf custom do_copy end + endfunction + + // **************************************************************************** + // FUNCTION: add_to_wave() + // This function is used to display variables in this class in the waveform + // viewer. The start_time and end_time variables must be set before this + // function is called. If the start_time and end_time variables are not set + // the transaction will be hidden at 0ns on the waveform display. + // + virtual function void add_to_wave(int transaction_viewing_stream_h); + `ifdef QUESTA + if (transaction_view_h == 0) begin + transaction_view_h = $begin_transaction(transaction_viewing_stream_h,"fuse_ctrl_prim_axi_write_out_transaction",start_time); + end + super.add_to_wave(transaction_view_h); + // pragma uvmf custom add_to_wave begin + // UVMF_CHANGE_ME : Color can be applied to transaction entries based on content, example below + // case() + // 1 : $add_color(transaction_view_h,"red"); + // default : $add_color(transaction_view_h,"grey"); + // endcase + // UVMF_CHANGE_ME : Eliminate transaction variables not wanted in transaction viewing in the waveform viewer + $add_attribute(transaction_view_h,prim_awready,"prim_awready"); + $add_attribute(transaction_view_h,prim_wready,"prim_wready"); + $add_attribute(transaction_view_h,prim_bresp,"prim_bresp"); + $add_attribute(transaction_view_h,prim_bid,"prim_bid"); + $add_attribute(transaction_view_h,prim_bvalid,"prim_bvalid"); + // pragma uvmf custom add_to_wave end + $end_transaction(transaction_view_h,end_time); + $free_transaction(transaction_view_h); + `endif // QUESTA + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_transaction_coverage.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_transaction_coverage.svh new file mode 100644 index 0000000..8a37ca5 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_transaction_coverage.svh @@ -0,0 +1,106 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class records fuse_ctrl_prim_axi_write_out transaction information using +// a covergroup named fuse_ctrl_prim_axi_write_out_transaction_cg. An instance of this +// coverage component is instantiated in the uvmf_parameterized_agent +// if the has_coverage flag is set. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_prim_axi_write_out_transaction_coverage #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvm_subscriber #(.T(fuse_ctrl_prim_axi_write_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +)); + + `uvm_component_param_utils( fuse_ctrl_prim_axi_write_out_transaction_coverage #( + AW, + DW, + IW, + UW + ) +) + + T coverage_trans; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + covergroup fuse_ctrl_prim_axi_write_out_transaction_cg; + // pragma uvmf custom covergroup begin + // UVMF_CHANGE_ME : Add coverage bins, crosses, exclusions, etc. according to coverage needs. + option.auto_bin_max=1024; + option.per_instance=1; + prim_awready: coverpoint coverage_trans.prim_awready; + prim_wready: coverpoint coverage_trans.prim_wready; + prim_bresp: coverpoint coverage_trans.prim_bresp; + prim_bid: coverpoint coverage_trans.prim_bid; + prim_bvalid: coverpoint coverage_trans.prim_bvalid; + // pragma uvmf custom covergroup end + endgroup + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new(string name="", uvm_component parent=null); + super.new(name,parent); + fuse_ctrl_prim_axi_write_out_transaction_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that transaction variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + endfunction + + // **************************************************************************** + // FUNCTION : build_phase() + // This function is the standard UVM build_phase. + // + function void build_phase(uvm_phase phase); + fuse_ctrl_prim_axi_write_out_transaction_cg.set_inst_name($sformatf("fuse_ctrl_prim_axi_write_out_transaction_cg_%s",get_full_name())); + endfunction + + // **************************************************************************** + // FUNCTION: write (T t) + // This function is automatically executed when a transaction arrives on the + // analysis_export. It copies values from the variables in the transaction + // to local variables used to collect functional coverage. + // + virtual function void write (T t); + `uvm_info("COV","Received transaction",UVM_HIGH); + coverage_trans = t; + fuse_ctrl_prim_axi_write_out_transaction_cg.sample(); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_typedefs.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_typedefs.svh new file mode 100644 index 0000000..f2a7bdb --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_typedefs.svh @@ -0,0 +1,34 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the host server when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_typedefs_hdl.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_typedefs_hdl.svh new file mode 100644 index 0000000..0d58518 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/src/fuse_ctrl_prim_axi_write_out_typedefs_hdl.svh @@ -0,0 +1,35 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the emulator when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/yaml/fuse_ctrl_prim_axi_write_out_interface.yaml b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/yaml/fuse_ctrl_prim_axi_write_out_interface.yaml new file mode 100644 index 0000000..d0566d0 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_prim_axi_write_out_pkg/yaml/fuse_ctrl_prim_axi_write_out_interface.yaml @@ -0,0 +1,81 @@ +uvmf: + interfaces: + fuse_ctrl_prim_axi_write_out: + clock: clk_i + config_constraints: [] + config_vars: [] + existing_library_component: 'True' + gen_inbound_streaming_driver: 'False' + hdl_pkg_parameters: [] + hdl_typedefs: [] + hvl_pkg_parameters: [] + hvl_typedefs: [] + parameters: + - name: AW + type: int + value: '32' + - name: DW + type: int + value: '32' + - name: IW + type: int + value: '3' + - name: UW + type: int + value: '32' + ports: + - dir: input + name: awready + reset_value: '''bz' + width: '1' + - dir: input + name: wready + reset_value: '''bz' + width: '1' + - dir: input + name: bresp + reset_value: '''bz' + width: '[''$bits(axi_pkg::axi_burst_e)'']' + - dir: input + name: bid + reset_value: '''bz' + width: '1' + - dir: input + name: bvalid + reset_value: '''bz' + width: '1' + reset: rst_ni + reset_assertion_level: 'False' + transaction_constraints: [] + transaction_vars: + - comment: '' + iscompare: 'True' + isrand: 'False' + name: prim_awready + type: logic + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'False' + name: prim_wready + type: logic + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'False' + name: prim_bresp + type: axi_pkg::axi_burst_e + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'False' + name: prim_bid + type: logic + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'False' + name: prim_bvalid + type: logic + unpacked_dimension: '' + use_dpi_link: 'False' diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/.project b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/.project new file mode 100644 index 0000000..942f586 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/.project @@ -0,0 +1,30 @@ + + + fuse_ctrl_rst_in_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/.svproject b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/.svproject new file mode 100644 index 0000000..8ad7633 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/Makefile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/Makefile new file mode 100644 index 0000000..7a8fb49 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/Makefile @@ -0,0 +1,66 @@ +# fuse_ctrl_rst_in interface packages source +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +fuse_ctrl_rst_in_PKG = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_in_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_filelist_hvl.f + +fuse_ctrl_rst_in_PKG_HDL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_in_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_filelist_hdl.f + +fuse_ctrl_rst_in_PKG_XRTL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_in_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_filelist_xrtl.f + +COMP_fuse_ctrl_rst_in_PKG_TGT_0 = q_comp_fuse_ctrl_rst_in_pkg +COMP_fuse_ctrl_rst_in_PKG_TGT_1 = v_comp_fuse_ctrl_rst_in_pkg +COMP_fuse_ctrl_rst_in_PKG_TGT = $(COMP_fuse_ctrl_rst_in_PKG_TGT_$(USE_VELOCE)) + +comp_fuse_ctrl_rst_in_pkg: $(COMP_fuse_ctrl_rst_in_PKG_TGT) + +q_comp_fuse_ctrl_rst_in_pkg: + $(HDL_COMP_CMD) $(fuse_ctrl_rst_in_PKG_HDL) + $(HVL_COMP_CMD) $(fuse_ctrl_rst_in_PKG) + $(HDL_COMP_CMD) $(fuse_ctrl_rst_in_PKG_XRTL) + +v_comp_fuse_ctrl_rst_in_pkg: + $(HVL_COMP_CMD) $(fuse_ctrl_rst_in_PKG_HDL) + $(HVL_COMP_CMD) $(fuse_ctrl_rst_in_PKG) + $(VELANALYZE_CMD) $(fuse_ctrl_rst_in_PKG_HDL) + $(VELANALYZE_HVL_CMD) $(fuse_ctrl_rst_in_PKG) + $(HDL_COMP_CMD) $(fuse_ctrl_rst_in_PKG_XRTL) + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export fuse_ctrl_rst_in_IF_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_in_pkg/dpi + +C_FILE_COMPILE_LIST_fuse_ctrl_rst_in_pkg = \ + +O_FILE_COMPILE_LIST_fuse_ctrl_rst_in_pkg = $(notdir $(C_FILE_COMPILE_LIST_fuse_ctrl_rst_in_pkg:.c=.o)) + +GCC_COMP_ARGS_fuse_ctrl_rst_in_pkg += -I$(fuse_ctrl_rst_in_IF_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_fuse_ctrl_rst_in_pkg += $(fuse_ctrl_rst_in_IF_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_fuse_ctrl_rst_in_pkg += \ + \ + -o .so + +comp_fuse_ctrl_rst_in_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Interface C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_fuse_ctrl_rst_in_pkg) $(C_FILE_COMPILE_LIST_fuse_ctrl_rst_in_pkg) + @echo "--------------------------------" + @echo "Linking Interface C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_fuse_ctrl_rst_in_pkg) $(O_FILE_COMPILE_LIST_fuse_ctrl_rst_in_pkg) + @echo "--------------------------------" + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/compile.do b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/compile.do new file mode 100644 index 0000000..8fe1b23 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/compile.do @@ -0,0 +1,14 @@ +# Tcl do file for compile of fuse_ctrl_rst_in interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_in_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_filelist_hdl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_in_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_filelist_hvl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_in_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_filelist_xrtl.f \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in.compile new file mode 100644 index 0000000..fdf807f --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in.compile @@ -0,0 +1,3 @@ +needs: + - fuse_ctrl_rst_in_hvl.compile + - fuse_ctrl_rst_in_hdl.compile diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_bfm.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_bfm.vinfo new file mode 100644 index 0000000..acb7e42 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_bfm.vinfo @@ -0,0 +1,6 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use fuse_ctrl_rst_in_pkg_hdl.vinfo ++incdir+@vinfodir +src/fuse_ctrl_rst_in_if.sv +src/fuse_ctrl_rst_in_driver_bfm.sv +src/fuse_ctrl_rst_in_monitor_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_common.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_common.compile new file mode 100644 index 0000000..66aaa58 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_common.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +incdir: + - . + - ${uvm_path}/src +src: + - fuse_ctrl_rst_in_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_filelist_hdl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_filelist_hdl.f new file mode 100644 index 0000000..19c4368 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_filelist_hdl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_filelist_hvl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_filelist_hvl.f new file mode 100644 index 0000000..1a44578 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_filelist_hvl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_pkg.sv \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_filelist_xrtl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_filelist_xrtl.f new file mode 100644 index 0000000..2a4fd65 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_filelist_xrtl.f @@ -0,0 +1,3 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_if.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_monitor_bfm.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_driver_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_hdl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_hdl.compile new file mode 100644 index 0000000..a3d5a61 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_hdl.compile @@ -0,0 +1,9 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ./fuse_ctrl_rst_in_common.compile +incdir: + - . +src: + - src/fuse_ctrl_rst_in_if.sv + - src/fuse_ctrl_rst_in_monitor_bfm.sv + - src/fuse_ctrl_rst_in_driver_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_hvl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_hvl.compile new file mode 100644 index 0000000..26e18a7 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_hvl.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ./fuse_ctrl_rst_in_common.compile +incdir: + - . +src: + - fuse_ctrl_rst_in_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_pkg.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_pkg.sv new file mode 100644 index 0000000..05dd6ee --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_pkg.sv @@ -0,0 +1,91 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - + +// - +// - +// - + +// - +// - +// - + +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_rst_in_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg_hdl::*; + import uvmf_base_pkg::*; + import fuse_ctrl_rst_in_pkg_hdl::*; + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + `include "src/fuse_ctrl_rst_in_macros.svh" + + export fuse_ctrl_rst_in_pkg_hdl::*; + + + + // Parameters defined as HVL parameters + + `include "src/fuse_ctrl_rst_in_typedefs.svh" + `include "src/fuse_ctrl_rst_in_transaction.svh" + + `include "src/fuse_ctrl_rst_in_configuration.svh" + `include "src/fuse_ctrl_rst_in_driver.svh" + `include "src/fuse_ctrl_rst_in_monitor.svh" + + `include "src/fuse_ctrl_rst_in_transaction_coverage.svh" + `include "src/fuse_ctrl_rst_in_sequence_base.svh" + `include "src/fuse_ctrl_rst_in_random_sequence.svh" + + `include "src/fuse_ctrl_rst_in_responder_sequence.svh" + `include "src/fuse_ctrl_rst_in2reg_adapter.svh" + + `include "src/fuse_ctrl_rst_in_agent.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new interface sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the interface package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_pkg.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_pkg.vinfo new file mode 100644 index 0000000..37f5660 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_pkg.vinfo @@ -0,0 +1,4 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use fuse_ctrl_rst_in_pkg_hdl.vinfo ++incdir+@vinfodir +fuse_ctrl_rst_in_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_pkg_hdl.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_pkg_hdl.sv new file mode 100644 index 0000000..5723531 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_pkg_hdl.sv @@ -0,0 +1,52 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that needs to be compiled and synthesized +// for running on Veloce. +// +// CONTAINS: +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_rst_in_pkg_hdl; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HDL parameters + + `include "src/fuse_ctrl_rst_in_typedefs_hdl.svh" + `include "src/fuse_ctrl_rst_in_macros.svh" + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_pkg_hdl.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_pkg_hdl.vinfo new file mode 100644 index 0000000..313c0e8 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_pkg_hdl.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +fuse_ctrl_rst_in_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_pkg_sve.F b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_pkg_sve.F new file mode 100644 index 0000000..d9e5416 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_pkg_sve.F @@ -0,0 +1,10 @@ +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + ++incdir+. +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_filelist_hdl.f +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_rst_in_pkg/fuse_ctrl_rst_in_filelist_hvl.f diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in2reg_adapter.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in2reg_adapter.svh new file mode 100644 index 0000000..00428f2 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in2reg_adapter.svh @@ -0,0 +1,112 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the UVM register adapter for the fuse_ctrl_rst_in interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_rst_in2reg_adapter extends uvm_reg_adapter; + + `uvm_object_utils( fuse_ctrl_rst_in2reg_adapter ) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //-------------------------------------------------------------------- + // new + //-------------------------------------------------------------------- + function new (string name = "fuse_ctrl_rst_in2reg_adapter" ); + super.new(name); + // pragma uvmf custom new begin + // UVMF_CHANGE_ME : Configure the adapter regarding byte enables and provides response. + + // Does the protocol the Agent is modeling support byte enables? + // 0 = NO + // 1 = YES + supports_byte_enable = 0; + + // Does the Agent's Driver provide separate response sequence items? + // i.e. Does the driver call seq_item_port.put() + // and do the sequences call get_response()? + // 0 = NO + // 1 = YES + provides_responses = 0; + // pragma uvmf custom new end + + endfunction: new + + //-------------------------------------------------------------------- + // reg2bus + //-------------------------------------------------------------------- + virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw); + + fuse_ctrl_rst_in_transaction trans_h = fuse_ctrl_rst_in_transaction ::type_id::create("trans_h"); + + // pragma uvmf custom reg2bus begin + // UVMF_CHANGE_ME : Fill in the reg2bus adapter mapping registe fields to protocol fields. + + //Adapt the following for your sequence item type + // trans_h.op = (rw.kind == UVM_READ) ? WB_READ : WB_WRITE; + //Copy over address + // trans_h.addr = rw.addr; + //Copy over write data + // trans_h.data = rw.data; + + // pragma uvmf custom reg2bus end + + // Return the adapted transaction + return trans_h; + + endfunction: reg2bus + + //-------------------------------------------------------------------- + // bus2reg + //-------------------------------------------------------------------- + virtual function void bus2reg(uvm_sequence_item bus_item, + ref uvm_reg_bus_op rw); + fuse_ctrl_rst_in_transaction trans_h; + if (!$cast(trans_h, bus_item)) begin + `uvm_fatal("ADAPT","Provided bus_item is not of the correct type") + return; + end + // pragma uvmf custom bus2reg begin + // UVMF_CHANGE_ME : Fill in the bus2reg adapter mapping protocol fields to register fields. + //Adapt the following for your sequence item type + //Copy over instruction type + // rw.kind = (trans_h.op == WB_WRITE) ? UVM_WRITE : UVM_READ; + //Copy over address + // rw.addr = trans_h.addr; + //Copy over read data + // rw.data = trans_h.data; + //Check for errors on the bus and return UVM_NOT_OK if there is an error + // rw.status = UVM_IS_OK; + // pragma uvmf custom bus2reg end + + endfunction: bus2reg + +endclass : fuse_ctrl_rst_in2reg_adapter + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_agent.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_agent.svh new file mode 100644 index 0000000..2de920a --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_agent.svh @@ -0,0 +1,67 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: Protocol specific agent class definition +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_rst_in_agent extends uvmf_parameterized_agent #( + .CONFIG_T(fuse_ctrl_rst_in_configuration ), + .DRIVER_T(fuse_ctrl_rst_in_driver ), + .MONITOR_T(fuse_ctrl_rst_in_monitor ), + .COVERAGE_T(fuse_ctrl_rst_in_transaction_coverage ), + .TRANS_T(fuse_ctrl_rst_in_transaction ) + ); + + `uvm_component_utils( fuse_ctrl_rst_in_agent ) + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** + // FUNCTION: build_phase + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + if (configuration.active_passive == ACTIVE) begin + // Place sequencer handle into configuration object + // so that it may be retrieved from configuration + // rather than using uvm_config_db + configuration.sequencer = this.sequencer; + end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_configuration.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_configuration.svh new file mode 100644 index 0000000..3010ecf --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_configuration.svh @@ -0,0 +1,193 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class contains all variables and functions used +// to configure the fuse_ctrl_rst_in agent and its bfm's. It gets the +// bfm's from the uvm_config_db for use by the agent. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_rst_in_configuration extends uvmf_parameterized_agent_configuration_base #( + .DRIVER_BFM_BIND_T(virtual fuse_ctrl_rst_in_driver_bfm ), + .MONITOR_BFM_BIND_T( virtual fuse_ctrl_rst_in_monitor_bfm )); + + `uvm_object_utils( fuse_ctrl_rst_in_configuration ) + + + // Sequencer handle populated by agent + uvm_sequencer #(fuse_ctrl_rst_in_transaction ) sequencer; + + //Constraints for the configuration variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + covergroup fuse_ctrl_rst_in_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + // pragma uvmf custom covergroup end + endgroup + + //******************************************************************* + //******************************************************************* + // Structure used to pass configuration variables to monitor and driver BFM's. + // Use to_struct function to pack variables into structure. + // Use from_struct function to unpack variables from structure. + // This structure is defined in fuse_ctrl_rst_in_macros.svh + `fuse_ctrl_rst_in_CONFIGURATION_STRUCT + fuse_ctrl_rst_in_configuration_s fuse_ctrl_rst_in_configuration_struct; + //******************************************************************* + // FUNCTION: to_struct() + // This function packs variables into a fuse_ctrl_rst_in_configuration_s + // structure. The function returns the handle to the fuse_ctrl_rst_in_configuration_struct. + // This function is defined in fuse_ctrl_rst_in_macros.svh + `fuse_ctrl_rst_in_CONFIGURATION_TO_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_struct() + // This function unpacks the struct provided as an argument into + // variables of this class. + // This function is defined in fuse_ctrl_rst_in_macros.svh + `fuse_ctrl_rst_in_CONFIGURATION_FROM_STRUCT_FUNCTION + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + // Construct the covergroup for this configuration class + fuse_ctrl_rst_in_configuration_cg = new; + endfunction + + // **************************************************************************** + // FUNCTION: post_randomize() + // This function is automatically called after the randomize() function + // is executed. + // + function void post_randomize(); + super.post_randomize(); + fuse_ctrl_rst_in_configuration_cg.sample(); + endfunction + + // **************************************************************************** + // FUNCTION: initialize + // This function causes the configuration to retrieve + // its virtual interface handle from the uvm_config_db. + // This function also makes itself available to its + // agent through the uvm_config_db. + // + // ARGUMENTS: + // uvmf_active_passive_t activity: + // This argument identifies the simulation level + // as either BLOCK, CHIP, SIMULATION, etc. + // + // AGENT_PATH: + // This argument identifies the path to this + // configurations agent. This configuration + // makes itself available to the agent specified + // by agent_path by placing itself into the + // uvm_config_db. + // + // INTERFACE_NAME: + // This argument identifies the string name of + // this configurations BFM's. This string + // name is used to retrieve the driver and + // monitor BFM from the uvm_config_db. + // + virtual function void initialize(uvmf_active_passive_t activity, + string agent_path, + string interface_name); + + super.initialize( activity, agent_path, interface_name); + // The covergroup is given the same name as the interface + fuse_ctrl_rst_in_configuration_cg.set_inst_name(interface_name); + + // This configuration places itself into the uvm_config_db for the agent, identified by the agent_path variable, to retrieve. + uvm_config_db #( fuse_ctrl_rst_in_configuration + )::set( null ,agent_path,UVMF_AGENT_CONFIG, this ); + + // This configuration also places itself in the config db using the same identifier used by the interface. This allows users to access + // configuration variables and the interface through the bfm api class rather than directly accessing the BFM. This is useful for + // accessingthe BFM when using Veloce + uvm_config_db #( fuse_ctrl_rst_in_configuration + )::set( null ,UVMF_CONFIGURATIONS, interface_name, this ); + + fuse_ctrl_rst_in_configuration_cg.set_inst_name($sformatf("fuse_ctrl_rst_in_configuration_cg_%s",get_full_name())); + +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. + `uvm_info("CFG", + $psprintf("The agent at '%s' is using interface named %s has the following parameters: ", agent_path, interface_name, ), + UVM_DEBUG) + + // pragma uvmf custom initialize begin + // This controls whether or not the agent returns a transaction handle in the driver when calling + // item_done() back into the sequencer or not. If set to 1, a transaction is sent back which means + // the sequence on the other end must use the get_response() part of the driver/sequence API. If + // this doesn't occur, there will eventually be response_queue overflow errors during the test. + return_transaction_response = 1'b0; + + // pragma uvmf custom initialize end + + endfunction + + // **************************************************************************** + // TASK: wait_for_reset + // *[Required]* Blocks until reset is released. The wait_for_reset operation is performed + // by a task in the monitor bfm. + virtual task wait_for_reset(); + monitor_bfm.wait_for_reset(); + endtask + + // **************************************************************************** + // TASK: wait_for_num_clocks + // *[Required]* Blocks until specified number of clocks have elapsed. The wait_for_num_clocks + // operation is performed by a task in the monitor bfm. + virtual task wait_for_num_clocks(int clocks); + monitor_bfm.wait_for_num_clocks(clocks); + endtask + + // **************************************************************************** + // FUNCTION : convert2string() + // This function is used to convert variables in this class into a string for log messaging. + // + virtual function string convert2string (); + // pragma uvmf custom convert2string begin + return $sformatf(""); + // pragma uvmf custom convert2string end + endfunction + + // **************************************************************************** + // FUNCTION: get_sequencer + function uvm_sequencer #(fuse_ctrl_rst_in_transaction) get_sequencer(); + return sequencer; + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_driver.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_driver.svh new file mode 100644 index 0000000..e691b01 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_driver.svh @@ -0,0 +1,105 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class passes transactions between the sequencer +// and the BFM driver interface. It accesses the driver BFM +// through the bfm handle. This driver +// passes transactions to the driver BFM through the access +// task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_rst_in_driver extends uvmf_driver_base #( + .CONFIG_T(fuse_ctrl_rst_in_configuration ), + .BFM_BIND_T(virtual fuse_ctrl_rst_in_driver_bfm ), + .REQ(fuse_ctrl_rst_in_transaction ), + .RSP(fuse_ctrl_rst_in_transaction )); + + `uvm_component_utils( fuse_ctrl_rst_in_driver ) +//******************************************************************* +// Macros that define structs located in fuse_ctrl_rst_in_macros.svh +//******************************************************************* +// Initiator macro used by fuse_ctrl_rst_in_driver and fuse_ctrl_rst_in_driver_bfm +// to communicate initiator driven data to fuse_ctrl_rst_in_driver_bfm. +`fuse_ctrl_rst_in_INITIATOR_STRUCT + fuse_ctrl_rst_in_initiator_s fuse_ctrl_rst_in_initiator_struct; +//******************************************************************* +// Responder macro used by fuse_ctrl_rst_in_driver and fuse_ctrl_rst_in_driver_bfm +// to communicate Responder driven data to fuse_ctrl_rst_in_driver_bfm. +`fuse_ctrl_rst_in_RESPONDER_STRUCT + fuse_ctrl_rst_in_responder_s fuse_ctrl_rst_in_responder_struct; + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent=null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the driver BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// driver BFM. This allows the driver BFM to call tasks and function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// **************************************************************************** +// This task is called by the run_phase in uvmf_driver_base. + virtual task access( inout REQ txn ); +// pragma uvmf custom access begin + if (configuration.initiator_responder==RESPONDER) begin + // Complete current transfer and wait for next transfer + bfm.respond_and_wait_for_next_transfer( + fuse_ctrl_rst_in_initiator_struct, + txn.to_responder_struct() + ); + // Unpack information about initiated transfer received by this responder + txn.from_initiator_struct(fuse_ctrl_rst_in_initiator_struct); + end else begin + // Initiate a transfer and get response + bfm.initiate_and_get_response( + txn.to_initiator_struct(), + fuse_ctrl_rst_in_responder_struct + ); + // Unpack transfer response information received by this initiator + txn.from_responder_struct(fuse_ctrl_rst_in_responder_struct); + end +// pragma uvmf custom access end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_driver_bfm.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_driver_bfm.sv new file mode 100644 index 0000000..3f063e1 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_driver_bfm.sv @@ -0,0 +1,311 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This interface performs the fuse_ctrl_rst_in signal driving. It is +// accessed by the uvm fuse_ctrl_rst_in driver through a virtual interface +// handle in the fuse_ctrl_rst_in configuration. It drives the singals passed +// in through the port connection named bus of type fuse_ctrl_rst_in_if. +// +// Input signals from the fuse_ctrl_rst_in_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// This bfm drives signals with a _o suffix. These signals +// are driven onto signals within fuse_ctrl_rst_in_if based on INITIATOR/RESPONDER and/or +// ARBITRATION/GRANT status. +// +// The output signal connections are as follows: +// signal_o -> bus.signal +// +// +// Interface functions and tasks used by UVM components: +// +// configure: +// This function gets configuration attributes from the +// UVM driver to set any required BFM configuration +// variables such as 'initiator_responder'. +// +// initiate_and_get_response: +// This task is used to perform signaling activity for initiating +// a protocol transfer. The task initiates the transfer, using +// input data from the initiator struct. Then the task captures +// response data, placing the data into the response struct. +// The response struct is returned to the driver class. +// +// respond_and_wait_for_next_transfer: +// This task is used to complete a current transfer as a responder +// and then wait for the initiator to start the next transfer. +// The task uses data in the responder struct to drive protocol +// signals to complete the transfer. The task then waits for +// the next transfer. Once the next transfer begins, data from +// the initiator is placed into the initiator struct and sent +// to the responder sequence for processing to determine +// what data to respond with. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_rst_in_pkg_hdl::*; +`include "src/fuse_ctrl_rst_in_macros.svh" + +interface fuse_ctrl_rst_in_driver_bfm + (fuse_ctrl_rst_in_if bus); + // The following pragma and additional ones in-lined further below are for running this BFM on Veloce + // pragma attribute fuse_ctrl_rst_in_driver_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: ", ), + UVM_DEBUG) +end +`endif + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + tri clk_i_i; + tri rst_ni_i; + + // Signal list (all signals are capable of being inputs and outputs for the sake + // of supporting both INITIATOR and RESPONDER mode operation. Expectation is that + // directionality in the config file was from the point-of-view of the INITIATOR + + // INITIATOR mode input signals + + // INITIATOR mode output signals + tri [$bits(pwrmgr_pkg::pwr_otp_req_t)-1:0] pwr_otp_i_i; + reg [$bits(pwrmgr_pkg::pwr_otp_req_t)-1:0] pwr_otp_i_o = 'bz; + + // Bi-directional signals + tri otp_ext_voltage_h_io_i; + reg otp_ext_voltage_h_io_o = 'bz; + reg rst_ni_o = 'bz; + + + assign clk_i_i = bus.clk_i; + assign rst_ni_i = bus.rst_ni; + + // These are signals marked as 'input' by the config file, but the signals will be + // driven by this BFM if put into RESPONDER mode (flipping all signal directions around) + + assign otp_ext_voltage_h_io_i = bus.otp_ext_voltage_h_io; + + // These are signals marked as 'output' by the config file, but the outputs will + // not be driven by this BFM unless placed in INITIATOR mode. + assign bus.pwr_otp_i = (initiator_responder == INITIATOR) ? pwr_otp_i_o : 'bz; + assign pwr_otp_i_i = bus.pwr_otp_i; + assign bus.otp_ext_voltage_h_io = otp_ext_voltage_h_io_o; + + // Proxy handle to UVM driver + fuse_ctrl_rst_in_pkg::fuse_ctrl_rst_in_driver proxy; + // pragma tbx oneway proxy.my_function_name_in_uvm_driver + + // **************************************************************************** + // **************************************************************************** + // Macros that define structs located in fuse_ctrl_rst_in_macros.svh + // **************************************************************************** + // Struct for passing configuration data from fuse_ctrl_rst_in_driver to this BFM + // **************************************************************************** + `fuse_ctrl_rst_in_CONFIGURATION_STRUCT + // **************************************************************************** + // Structs for INITIATOR and RESPONDER data flow + //******************************************************************* + // Initiator macro used by fuse_ctrl_rst_in_driver and fuse_ctrl_rst_in_driver_bfm + // to communicate initiator driven data to fuse_ctrl_rst_in_driver_bfm. + `fuse_ctrl_rst_in_INITIATOR_STRUCT + fuse_ctrl_rst_in_initiator_s initiator_struct; + // Responder macro used by fuse_ctrl_rst_in_driver and fuse_ctrl_rst_in_driver_bfm + // to communicate Responder driven data to fuse_ctrl_rst_in_driver_bfm. + `fuse_ctrl_rst_in_RESPONDER_STRUCT + fuse_ctrl_rst_in_responder_s responder_struct; + + // **************************************************************************** +// pragma uvmf custom reset_condition_and_response begin + // Always block used to return signals to reset value upon assertion of reset + always @( negedge rst_ni_i ) + begin + // RESPONDER mode output signals + // INITIATOR mode output signals + pwr_otp_i_o <= 'bz; + // Bi-directional signals + otp_ext_voltage_h_io_o <= 'bz; + + end +// pragma uvmf custom reset_condition_and_response end + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the driver BFM. It is called by the driver within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the driver BFM needs to be aware of the new configuration + // variables. + // + + function void configure(fuse_ctrl_rst_in_configuration_s fuse_ctrl_rst_in_configuration_arg); // pragma tbx xtf + initiator_responder = fuse_ctrl_rst_in_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + +// pragma uvmf custom initiate_and_get_response begin +// **************************************************************************** +// UVMF_CHANGE_ME +// This task is used by an initator. The task first initiates a transfer then +// waits for the responder to complete the transfer. + task initiate_and_get_response( + // This argument passes transaction variables used by an initiator + // to perform the initial part of a protocol transfer. The values + // come from a sequence item created in a sequence. + input fuse_ctrl_rst_in_initiator_s fuse_ctrl_rst_in_initiator_struct, + // This argument is used to send data received from the responder + // back to the sequence item. The sequence item is returned to the sequence. + output fuse_ctrl_rst_in_responder_s fuse_ctrl_rst_in_responder_struct + );// pragma tbx xtf + // + // Members within the fuse_ctrl_rst_in_initiator_struct: + // bit assert_rst ; + // bit assert_otp_pwr_init ; + // Members within the fuse_ctrl_rst_in_responder_struct: + // bit assert_rst ; + // bit assert_otp_pwr_init ; + initiator_struct = fuse_ctrl_rst_in_initiator_struct; + // + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clk_i_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available initiator input and inout signals listed. + // Initiator input signals + // Initiator inout signals + // fuse_ctrl_rst_in_responder_struct.xyz = otp_ext_voltage_h_io_i; // + // How to assign a signal from an initiator struct member named xyz. + // All available initiator output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Initiator output signals + // pwr_otp_i_o <= fuse_ctrl_rst_in_initiator_struct.xyz; // [$bits(pwrmgr_pkg::pwr_otp_req_t)-1:0] + // Initiator inout signals + // otp_ext_voltage_h_io_o <= fuse_ctrl_rst_in_initiator_struct.xyz; // + // Initiate a transfer using the data received. + @(posedge clk_i_i); + @(posedge clk_i_i); + if (initiator_struct.assert_rst) + rst_ni_o <= 1'b0; + if (initiator_struct.assert_otp_pwr_init) + pwr_otp_i_o <= 1'b1; + // Wait for the responder to complete the transfer then place the responder data into + // fuse_ctrl_rst_in_responder_struct. + @(posedge clk_i_i); + @(posedge clk_i_i); + + if (!initiator_struct.assert_rst) + rst_ni_o <= 1'b1; + if (!initiator_struct.assert_otp_pwr_init) + pwr_otp_i_o <= 1'b0; + + fuse_ctrl_rst_in_responder_struct.assert_rst = !rst_ni_i; + fuse_ctrl_rst_in_responder_struct.assert_otp_init = pwr_otp_i_i; + responder_struct = fuse_ctrl_rst_in_responder_struct; + endtask +// pragma uvmf custom initiate_and_get_response end + +// pragma uvmf custom respond_and_wait_for_next_transfer begin +// **************************************************************************** +// The first_transfer variable is used to prevent completing a transfer in the +// first call to this task. For the first call to this task, there is not +// current transfer to complete. +bit first_transfer=1; + +// UVMF_CHANGE_ME +// This task is used by a responder. The task first completes the current +// transfer in progress then waits for the initiator to start the next transfer. + task respond_and_wait_for_next_transfer( + // This argument is used to send data received from the initiator + // back to the sequence item. The sequence determines how to respond. + output fuse_ctrl_rst_in_initiator_s fuse_ctrl_rst_in_initiator_struct, + // This argument passes transaction variables used by a responder + // to complete a protocol transfer. The values come from a sequence item. + input fuse_ctrl_rst_in_responder_s fuse_ctrl_rst_in_responder_struct + );// pragma tbx xtf + // Variables within the fuse_ctrl_rst_in_initiator_struct: + // bit assert_rst ; + // bit assert_otp_pwr_init ; + // Variables within the fuse_ctrl_rst_in_responder_struct: + // bit assert_rst ; + // bit assert_otp_pwr_init ; + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clk_i_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available responder input and inout signals listed. + // Responder input signals + // fuse_ctrl_rst_in_responder_struct.xyz = pwr_otp_i_i; // [$bits(pwrmgr_pkg::pwr_otp_req_t)-1:0] + // Responder inout signals + // fuse_ctrl_rst_in_responder_struct.xyz = otp_ext_voltage_h_io_i; // + // How to assign a signal, named xyz, from an initiator struct member. + // All available responder output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Responder output signals + // Responder inout signals + // otp_ext_voltage_h_io_o <= fuse_ctrl_rst_in_initiator_struct.xyz; // + + @(posedge clk_i_i); + if (!first_transfer) begin + // Perform transfer response here. + // Reply using data recieved in the fuse_ctrl_rst_in_responder_struct. + @(posedge clk_i_i); + // Reply using data recieved in the transaction handle. + @(posedge clk_i_i); + end + // Wait for next transfer then gather info from intiator about the transfer. + // Place the data into the fuse_ctrl_rst_in_initiator_struct. + @(posedge clk_i_i); + @(posedge clk_i_i); + first_transfer = 0; + endtask +// pragma uvmf custom respond_and_wait_for_next_transfer end + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_if.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_if.sv new file mode 100644 index 0000000..de04ea9 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_if.sv @@ -0,0 +1,83 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface contains the fuse_ctrl_rst_in interface signals. +// It is instantiated once per fuse_ctrl_rst_in bus. Bus Functional Models, +// BFM's named fuse_ctrl_rst_in_driver_bfm, are used to drive signals on the bus. +// BFM's named fuse_ctrl_rst_in_monitor_bfm are used to monitor signals on the +// bus. This interface signal bundle is passed in the port list of +// the BFM in order to give the BFM access to the signals in this +// interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// This template can be used to connect a DUT to these signals +// +// .dut_signal_port(fuse_ctrl_rst_in_bus.pwr_otp_i), // Agent output +// .dut_signal_port(fuse_ctrl_rst_in_bus.otp_ext_voltage_h_io), // Agent inout + +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_rst_in_pkg_hdl::*; + +interface fuse_ctrl_rst_in_if + + ( + input tri clk_i, + input tri rst_ni, + inout tri [$bits(pwrmgr_pkg::pwr_otp_req_t)-1:0] pwr_otp_i, + inout tri otp_ext_voltage_h_io + ); + +modport monitor_port + ( + input clk_i, + input rst_ni, + input pwr_otp_i, + input otp_ext_voltage_h_io + ); + +modport initiator_port + ( + input clk_i, + input rst_ni, + output pwr_otp_i, + inout otp_ext_voltage_h_io + ); + +modport responder_port + ( + input clk_i, + input rst_ni, + input pwr_otp_i, + inout otp_ext_voltage_h_io + ); + + +// pragma uvmf custom interface_item_additional begin +// pragma uvmf custom interface_item_additional end + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_infact_coverage_strategy.csv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_infact_coverage_strategy.csv new file mode 100644 index 0000000..1c218e1 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_infact_coverage_strategy.csv @@ -0,0 +1,6 @@ +Global +auto_bin_max, 64 + +Name,Type,Include +rand_fields,coverpoint,=rand *.** + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_macros.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_macros.svh new file mode 100644 index 0000000..a7124a6 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_macros.svh @@ -0,0 +1,144 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains macros used with the fuse_ctrl_rst_in package. +// These macros include packed struct definitions. These structs are +// used to pass data between classes, hvl, and BFM's, hdl. Use of +// structs are more efficient and simpler to modify. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_struct +// and from_struct methods defined in the macros below that are used in +// the fuse_ctrl_rst_in_configuration class. +// + `define fuse_ctrl_rst_in_CONFIGURATION_STRUCT \ +typedef struct packed { \ + uvmf_active_passive_t active_passive; \ + uvmf_initiator_responder_t initiator_responder; \ + } fuse_ctrl_rst_in_configuration_s; + + `define fuse_ctrl_rst_in_CONFIGURATION_TO_STRUCT_FUNCTION \ + virtual function fuse_ctrl_rst_in_configuration_s to_struct();\ + fuse_ctrl_rst_in_configuration_struct = \ + {\ + this.active_passive,\ + this.initiator_responder\ + };\ + return ( fuse_ctrl_rst_in_configuration_struct );\ + endfunction + + `define fuse_ctrl_rst_in_CONFIGURATION_FROM_STRUCT_FUNCTION \ + virtual function void from_struct(fuse_ctrl_rst_in_configuration_s fuse_ctrl_rst_in_configuration_struct);\ + {\ + this.active_passive,\ + this.initiator_responder \ + } = fuse_ctrl_rst_in_configuration_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_monitor_struct +// and from_monitor_struct methods of the fuse_ctrl_rst_in_transaction class. +// + `define fuse_ctrl_rst_in_MONITOR_STRUCT typedef struct packed { \ + bit assert_rst ; \ + bit assert_otp_pwr_init ; \ + } fuse_ctrl_rst_in_monitor_s; + + `define fuse_ctrl_rst_in_TO_MONITOR_STRUCT_FUNCTION \ + virtual function fuse_ctrl_rst_in_monitor_s to_monitor_struct();\ + fuse_ctrl_rst_in_monitor_struct = \ + { \ + this.assert_rst , \ + this.assert_otp_pwr_init \ + };\ + return ( fuse_ctrl_rst_in_monitor_struct);\ + endfunction\ + + `define fuse_ctrl_rst_in_FROM_MONITOR_STRUCT_FUNCTION \ + virtual function void from_monitor_struct(fuse_ctrl_rst_in_monitor_s fuse_ctrl_rst_in_monitor_struct);\ + {\ + this.assert_rst , \ + this.assert_otp_pwr_init \ + } = fuse_ctrl_rst_in_monitor_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_initiator_struct +// and from_initiator_struct methods of the fuse_ctrl_rst_in_transaction class. +// Also update the comments in the driver BFM. +// + `define fuse_ctrl_rst_in_INITIATOR_STRUCT typedef struct packed { \ + bit assert_rst ; \ + bit assert_otp_pwr_init ; \ + } fuse_ctrl_rst_in_initiator_s; + + `define fuse_ctrl_rst_in_TO_INITIATOR_STRUCT_FUNCTION \ + virtual function fuse_ctrl_rst_in_initiator_s to_initiator_struct();\ + fuse_ctrl_rst_in_initiator_struct = \ + {\ + this.assert_rst , \ + this.assert_otp_pwr_init \ + };\ + return ( fuse_ctrl_rst_in_initiator_struct);\ + endfunction + + `define fuse_ctrl_rst_in_FROM_INITIATOR_STRUCT_FUNCTION \ + virtual function void from_initiator_struct(fuse_ctrl_rst_in_initiator_s fuse_ctrl_rst_in_initiator_struct);\ + {\ + this.assert_rst , \ + this.assert_otp_pwr_init \ + } = fuse_ctrl_rst_in_initiator_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_responder_struct +// and from_responder_struct methods of the fuse_ctrl_rst_in_transaction class. +// Also update the comments in the driver BFM. +// + `define fuse_ctrl_rst_in_RESPONDER_STRUCT typedef struct packed { \ + bit assert_rst ; \ + bit assert_otp_pwr_init ; \ + } fuse_ctrl_rst_in_responder_s; + + `define fuse_ctrl_rst_in_TO_RESPONDER_STRUCT_FUNCTION \ + virtual function fuse_ctrl_rst_in_responder_s to_responder_struct();\ + fuse_ctrl_rst_in_responder_struct = \ + {\ + this.assert_rst , \ + this.assert_otp_pwr_init \ + };\ + return ( fuse_ctrl_rst_in_responder_struct);\ + endfunction + + `define fuse_ctrl_rst_in_FROM_RESPONDER_STRUCT_FUNCTION \ + virtual function void from_responder_struct(fuse_ctrl_rst_in_responder_s fuse_ctrl_rst_in_responder_struct);\ + {\ + this.assert_rst , \ + this.assert_otp_pwr_init \ + } = fuse_ctrl_rst_in_responder_struct;\ + endfunction +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_monitor.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_monitor.svh new file mode 100644 index 0000000..f160bbc --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_monitor.svh @@ -0,0 +1,101 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class receives fuse_ctrl_rst_in transactions observed by the +// fuse_ctrl_rst_in monitor BFM and broadcasts them through the analysis port +// on the agent. It accesses the monitor BFM through the monitor +// task. This UVM component captures transactions +// for viewing in the waveform viewer if the +// enable_transaction_viewing flag is set in the configuration. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_rst_in_monitor extends uvmf_monitor_base #( + .CONFIG_T(fuse_ctrl_rst_in_configuration ), + .BFM_BIND_T(virtual fuse_ctrl_rst_in_monitor_bfm ), + .TRANS_T(fuse_ctrl_rst_in_transaction )); + + `uvm_component_utils( fuse_ctrl_rst_in_monitor ) + +// Structure used to pass data from monitor BFM to monitor class in agent. +// Use to_monitor_struct function to pack transaction variables into structure. +// Use from_monitor_struct function to unpack transaction variables from structure. +`fuse_ctrl_rst_in_MONITOR_STRUCT + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the monitor BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// monitor BFM. This allows the monitor BFM to call the notify_transaction +// function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// *************************************************************************** + virtual task run_phase(uvm_phase phase); + // Start monitor BFM thread and don't call super.run() in order to + // override the default monitor proxy 'pull' behavior with the more + // emulation-friendly BFM 'push' approach using the notify_transaction + // function below + bfm.start_monitoring(); + endtask + +// ************************************************************************** + +// This function is called by the monitor BFM. It receives data observed by the +// monitor BFM. Data is passed using the fuse_ctrl_rst_in_monitor_struct. + virtual function void notify_transaction(input fuse_ctrl_rst_in_monitor_s fuse_ctrl_rst_in_monitor_struct); + + + trans = new("trans"); + trans.from_monitor_struct(fuse_ctrl_rst_in_monitor_struct); + trans.start_time = time_stamp; + trans.end_time = $time; + time_stamp = trans.end_time; + + analyze(trans); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_monitor_bfm.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_monitor_bfm.sv new file mode 100644 index 0000000..0e43766 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_monitor_bfm.sv @@ -0,0 +1,192 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface performs the fuse_ctrl_rst_in signal monitoring. +// It is accessed by the uvm fuse_ctrl_rst_in monitor through a virtual +// interface handle in the fuse_ctrl_rst_in configuration. It monitors the +// signals passed in through the port connection named bus of +// type fuse_ctrl_rst_in_if. +// +// Input signals from the fuse_ctrl_rst_in_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// Interface functions and tasks used by UVM components: +// monitor(inout TRANS_T txn); +// This task receives the transaction, txn, from the +// UVM monitor and then populates variables in txn +// from values observed on bus activity. This task +// blocks until an operation on the fuse_ctrl_rst_in bus is complete. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_rst_in_pkg_hdl::*; +`include "src/fuse_ctrl_rst_in_macros.svh" + + +interface fuse_ctrl_rst_in_monitor_bfm + ( fuse_ctrl_rst_in_if bus ); + // The pragma below and additional ones in-lined further down are for running this BFM on Veloce + // pragma attribute fuse_ctrl_rst_in_monitor_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: ", ), + UVM_DEBUG) +end +`endif + + + // Structure used to pass transaction data from monitor BFM to monitor class in agent. +`fuse_ctrl_rst_in_MONITOR_STRUCT + fuse_ctrl_rst_in_monitor_s fuse_ctrl_rst_in_monitor_struct; + + // Structure used to pass configuration data from monitor class to monitor BFM. + `fuse_ctrl_rst_in_CONFIGURATION_STRUCT + + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + tri clk_i_i; + tri rst_ni_i; + tri [$bits(pwrmgr_pkg::pwr_otp_req_t)-1:0] pwr_otp_i_i; + tri otp_ext_voltage_h_io_i; + assign clk_i_i = bus.clk_i; + assign rst_ni_i = bus.rst_ni; + assign pwr_otp_i_i = bus.pwr_otp_i; + assign otp_ext_voltage_h_io_i = bus.otp_ext_voltage_h_io; + + // Proxy handle to UVM monitor + fuse_ctrl_rst_in_pkg::fuse_ctrl_rst_in_monitor proxy; + // pragma tbx oneway proxy.notify_transaction + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + task wait_for_reset();// pragma tbx xtf + @(posedge clk_i_i) ; + do_wait_for_reset(); + endtask + + // **************************************************************************** + task do_wait_for_reset(); + // pragma uvmf custom reset_condition begin + wait ( rst_ni_i === 1 ) ; + @(posedge clk_i_i) ; + // pragma uvmf custom reset_condition end + endtask + + //****************************************************************** + + task wait_for_num_clocks(input int unsigned count); // pragma tbx xtf + @(posedge clk_i_i); + + repeat (count-1) @(posedge clk_i_i); + endtask + + //****************************************************************** + event go; + function void start_monitoring();// pragma tbx xtf + -> go; + endfunction + + // **************************************************************************** + initial begin + @go; + forever begin + @(posedge clk_i_i); + do_monitor( fuse_ctrl_rst_in_monitor_struct ); + + + proxy.notify_transaction( fuse_ctrl_rst_in_monitor_struct ); + + end + end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the monitor BFM. It is called by the monitor within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the monitor BFM needs to be aware of the new configuration + // variables. + // + function void configure(fuse_ctrl_rst_in_configuration_s fuse_ctrl_rst_in_configuration_arg); // pragma tbx xtf + initiator_responder = fuse_ctrl_rst_in_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + + + // **************************************************************************** + + task do_monitor(output fuse_ctrl_rst_in_monitor_s fuse_ctrl_rst_in_monitor_struct); + // + // Available struct members: + // // fuse_ctrl_rst_in_monitor_struct.assert_rst + // // fuse_ctrl_rst_in_monitor_struct.assert_otp_pwr_init + // // + // Reference code; + // How to wait for signal value + // while (control_signal === 1'b1) @(posedge clk_i_i); + // + // How to assign a struct member, named xyz, from a signal. + // All available input signals listed. + // fuse_ctrl_rst_in_monitor_struct.xyz = pwr_otp_i_i; // [$bits(pwrmgr_pkg::pwr_otp_req_t)-1:0] + // fuse_ctrl_rst_in_monitor_struct.xyz = otp_ext_voltage_h_io_i; // + // pragma uvmf custom do_monitor begin + // UVMF_CHANGE_ME : Implement protocol monitoring. The commented reference code + // below are examples of how to capture signal values and assign them to + // structure members. All available input signals are listed. The 'while' + // code example shows how to wait for a synchronous flow control signal. This + // task should return when a complete transfer has been observed. Once this task is + // exited with captured values, it is then called again to wait for and observe + // the next transfer. One clock cycle is consumed between calls to do_monitor. + @(posedge clk_i_i); + @(posedge clk_i_i); + @(posedge clk_i_i); + @(posedge clk_i_i); + // pragma uvmf custom do_monitor end + endtask + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_poweron_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_poweron_sequence.svh new file mode 100644 index 0000000..360c2f6 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_poweron_sequence.svh @@ -0,0 +1,82 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This sequences randomizes the fuse_ctrl_rst transaction and sends it +// to the UVM driver. +// +// This sequence constructs and randomizes a fuse_ctrl_rst_transaction. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_rst_in_poweron_sequence extends fuse_ctrl_rst_in_sequence_base; + + `uvm_object_utils( fuse_ctrl_rst_in_random_sequence ) + + function new(string name = ""); + super.new(name); + endfunction: new + + // **************************************************************************** + // TASK : body() + // This task is automatically executed when this sequence is started using the + // start(sequencerHandle) task. + // + task body(); + + // Initiate first transaction with rst_ni = 0 (asserted), pwr_otp_i = 0 (deasserted) + req = fuse_ctrl_rst_in_transaction::type_id:: create("rst_req"); + start_item(req); + // Randomize the transaction + if (!req.randomize()) `uvm_fatal("FUSE_CTRL_RST_POWERON", "fuse_ctrl_rst_poweron_sequence::body()-fuse_ctrl_rst_transaction randomization failed") + `uvm_info("FUSE_CTRL_RST_POWERON", "Asserting reset", UVM_MEDIUM) + req.assert_rst = 1'b0; + req.assert_otp_init = 1'b0; + finish_item(req); + `uvm_info("FUSE_CTRL_RST_POWERON", {"Response:", req.convert2string()}, UVM_MEDIUM) + + // Deassert rst_ni, pwr_otp_i = 0 (deasserted) + req = fuse_ctrl_rst_in_transaction::type_id:: create("rst_release_req"); + start_item(req); + // Randomize the transaction + if (!req.randomize()) `uvm_fatal("FUSE_CTRL_RST_POWERON", "fuse_ctrl_rst_poweron_sequence::body()-fuse_ctrl_rst_transaction randomization failed") + `uvm_info("FUSE_CTRL_RST_POWERON", "Deasserting reset, reset phase done", UVM_MEDIUM) + req.assert_rst = 1'b1; + req.assert_otp_init = 1'b0; + finish_item(req); + `uvm_info("FUSE_CTRL_RST_POWERON", {"Response:", req.convert2string()}, UVM_MEDIUM) + + // Assert pwr_otp_i = 1 + req = fuse_ctrl_rst_in_transaction::type_id:: create("otp_init_req"); + start_item(req); + // Randomize the transaction + if (!req.randomize()) `uvm_fatal("FUSE_CTRL_RST_POWERON", "fuse_ctrl_rst_poweron_sequence::body()-fuse_ctrl_rst_transaction randomization failed") + `uvm_info("FUSE_CTRL_RST_POWERON", "Asserting init request to all partitions", UVM_MEDIUM) + req.assert_rst = 1'b1; + req.assert_otp_init = 1'b1; + finish_item(req); + `uvm_info("FUSE_CTRL_RST_POWERON", {"Response:", req.convert2string()}, UVM_MEDIUM) + + endtask + +endclass \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_random_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_random_sequence.svh new file mode 100644 index 0000000..99ba931 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_random_sequence.svh @@ -0,0 +1,67 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This sequences randomizes the fuse_ctrl_rst_in transaction and sends it +// to the UVM driver. +// +// This sequence constructs and randomizes a fuse_ctrl_rst_in_transaction. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_rst_in_random_sequence + extends fuse_ctrl_rst_in_sequence_base ; + + `uvm_object_utils( fuse_ctrl_rst_in_random_sequence ) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //***************************************************************** + function new(string name = ""); + super.new(name); + endfunction: new + + // **************************************************************************** + // TASK : body() + // This task is automatically executed when this sequence is started using the + // start(sequencerHandle) task. + // + task body(); + + // Construct the transaction + req=fuse_ctrl_rst_in_transaction::type_id::create("req"); + start_item(req); + // Randomize the transaction + if(!req.randomize()) `uvm_fatal("SEQ", "fuse_ctrl_rst_in_random_sequence::body()-fuse_ctrl_rst_in_transaction randomization failed") + // Send the transaction to the fuse_ctrl_rst_in_driver_bfm via the sequencer and fuse_ctrl_rst_in_driver. + finish_item(req); + `uvm_info("SEQ", {"Response:",req.convert2string()},UVM_MEDIUM) + + endtask + +endclass: fuse_ctrl_rst_in_random_sequence + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_responder_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_responder_sequence.svh new file mode 100644 index 0000000..96f0fa3 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_responder_sequence.svh @@ -0,0 +1,63 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class can be used to provide stimulus when an interface +// has been configured to run in a responder mode. It +// will never finish by default, always going back to the driver +// and driver BFM for the next transaction with which to respond. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_rst_in_responder_sequence + extends fuse_ctrl_rst_in_sequence_base ; + + `uvm_object_utils( fuse_ctrl_rst_in_responder_sequence ) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "fuse_ctrl_rst_in_responder_sequence"); + super.new(name); + endfunction + + task body(); + req=fuse_ctrl_rst_in_transaction::type_id::create("req"); + forever begin + start_item(req); + finish_item(req); + // pragma uvmf custom body begin + // UVMF_CHANGE_ME : Do something here with the resulting req item. The + // finish_item() call above will block until the req transaction is ready + // to be handled by the responder sequence. + // If this was an item that required a response, the expectation is + // that the response should be populated within this transaction now. + `uvm_info("SEQ",$sformatf("Processed txn: %s",req.convert2string()),UVM_HIGH) + // pragma uvmf custom body end + end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_sequence_base.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_sequence_base.svh new file mode 100644 index 0000000..47c3b89 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_sequence_base.svh @@ -0,0 +1,110 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the class used as the base class for all sequences +// for this interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_rst_in_sequence_base extends uvmf_sequence_base #( + .REQ(fuse_ctrl_rst_in_transaction ), + .RSP(fuse_ctrl_rst_in_transaction )); + + `uvm_object_utils( fuse_ctrl_rst_in_sequence_base ) + + // variables + typedef fuse_ctrl_rst_in_transaction fuse_ctrl_rst_in_transaction_req_t; + fuse_ctrl_rst_in_transaction_req_t req; + typedef fuse_ctrl_rst_in_transaction fuse_ctrl_rst_in_transaction_rsp_t; + fuse_ctrl_rst_in_transaction_rsp_t rsp; + + // Event for identifying when a response was received from the sequencer + event new_rsp; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // TASK : get_responses() + // This task recursively gets sequence item responses from the sequencer. + // + virtual task get_responses(); + fork + begin + // Block until new rsp available + get_response(rsp); + // New rsp received. Indicate to sequence using event. + ->new_rsp; + // Display the received response transaction + `uvm_info("SEQ", {"New response transaction:",rsp.convert2string()}, UVM_MEDIUM) + end + join_none + endtask + + // **************************************************************************** + // TASK : pre_body() + // This task is called automatically when start is called with call_pre_post set to 1 (default). + // By calling get_responses() within pre_body() any derived sequences are automatically + // processing response transactions. Only un-comment this call to get_responses() if you + // have configured the interface driver to utilize the response transaction path by setting + // the configuration variable "return_transaction_response" to 1. Otherwise it is possible + // to impact runtime performance and memory utilization. + // + virtual task pre_body(); + // pragma uvmf custom pre_body begin +// get_responses(); + // pragma uvmf custom pre_body end + endtask + + // **************************************************************************** + // TASK : body() + // This task is called automatically when start is called. This sequence sends + // a req sequence item to the sequencer identified as an argument in the call + // to start. + // + virtual task body(); + // pragma uvmf custom body begin + start_item(req); + finish_item(req); + // pragma uvmf custom body end + endtask + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name =""); + super.new( name ); + // pragma uvmf custom new begin + req = fuse_ctrl_rst_in_transaction_req_t::type_id::create("req"); + rsp = fuse_ctrl_rst_in_transaction_rsp_t::type_id::create("rsp"); + // pragma uvmf custom new end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_transaction.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_transaction.svh new file mode 100644 index 0000000..83d7dbc --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_transaction.svh @@ -0,0 +1,198 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class defines the variables required for an fuse_ctrl_rst_in +// transaction. Class variables to be displayed in waveform transaction +// viewing are added to the transaction viewing stream in the add_to_wave +// function. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_rst_in_transaction extends uvmf_transaction_base; + + `uvm_object_utils( fuse_ctrl_rst_in_transaction ) + + bit assert_rst ; + bit assert_otp_pwr_init ; + + //Constraints for the transaction variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //******************************************************************* + //******************************************************************* + // Macros that define structs and associated functions are + // located in fuse_ctrl_rst_in_macros.svh + + //******************************************************************* + // Monitor macro used by fuse_ctrl_rst_in_monitor and fuse_ctrl_rst_in_monitor_bfm + // This struct is defined in fuse_ctrl_rst_in_macros.svh + `fuse_ctrl_rst_in_MONITOR_STRUCT + fuse_ctrl_rst_in_monitor_s fuse_ctrl_rst_in_monitor_struct; + //******************************************************************* + // FUNCTION: to_monitor_struct() + // This function packs transaction variables into a fuse_ctrl_rst_in_monitor_s + // structure. The function returns the handle to the fuse_ctrl_rst_in_monitor_struct. + // This function is defined in fuse_ctrl_rst_in_macros.svh + `fuse_ctrl_rst_in_TO_MONITOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_monitor_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_rst_in_macros.svh + `fuse_ctrl_rst_in_FROM_MONITOR_STRUCT_FUNCTION + + //******************************************************************* + // Initiator macro used by fuse_ctrl_rst_in_driver and fuse_ctrl_rst_in_driver_bfm + // to communicate initiator driven data to fuse_ctrl_rst_in_driver_bfm. + // This struct is defined in fuse_ctrl_rst_in_macros.svh + `fuse_ctrl_rst_in_INITIATOR_STRUCT + fuse_ctrl_rst_in_initiator_s fuse_ctrl_rst_in_initiator_struct; + //******************************************************************* + // FUNCTION: to_initiator_struct() + // This function packs transaction variables into a fuse_ctrl_rst_in_initiator_s + // structure. The function returns the handle to the fuse_ctrl_rst_in_initiator_struct. + // This function is defined in fuse_ctrl_rst_in_macros.svh + `fuse_ctrl_rst_in_TO_INITIATOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_initiator_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_rst_in_macros.svh + `fuse_ctrl_rst_in_FROM_INITIATOR_STRUCT_FUNCTION + + //******************************************************************* + // Responder macro used by fuse_ctrl_rst_in_driver and fuse_ctrl_rst_in_driver_bfm + // to communicate Responder driven data to fuse_ctrl_rst_in_driver_bfm. + // This struct is defined in fuse_ctrl_rst_in_macros.svh + `fuse_ctrl_rst_in_RESPONDER_STRUCT + fuse_ctrl_rst_in_responder_s fuse_ctrl_rst_in_responder_struct; + //******************************************************************* + // FUNCTION: to_responder_struct() + // This function packs transaction variables into a fuse_ctrl_rst_in_responder_s + // structure. The function returns the handle to the fuse_ctrl_rst_in_responder_struct. + // This function is defined in fuse_ctrl_rst_in_macros.svh + `fuse_ctrl_rst_in_TO_RESPONDER_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_responder_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_rst_in_macros.svh + `fuse_ctrl_rst_in_FROM_RESPONDER_STRUCT_FUNCTION + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + endfunction + + // **************************************************************************** + // FUNCTION: convert2string() + // This function converts all variables in this class to a single string for + // logfile reporting. + // + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + // UVMF_CHANGE_ME : Customize format if desired. + return $sformatf("assert_rst:0x%x assert_otp_pwr_init:0x%x ",assert_rst,assert_otp_pwr_init); + // pragma uvmf custom convert2string end + endfunction + + //******************************************************************* + // FUNCTION: do_print() + // This function is automatically called when the .print() function + // is called on this class. + // + virtual function void do_print(uvm_printer printer); + // pragma uvmf custom do_print begin + // UVMF_CHANGE_ME : Current contents of do_print allows for the use of UVM 1.1d, 1.2 or P1800.2. + // Update based on your own printing preference according to your preferred UVM version + $display(convert2string()); + // pragma uvmf custom do_print end + endfunction + + //******************************************************************* + // FUNCTION: do_compare() + // This function is automatically called when the .compare() function + // is called on this class. + // + virtual function bit do_compare (uvm_object rhs, uvm_comparer comparer); + fuse_ctrl_rst_in_transaction RHS; + if (!$cast(RHS,rhs)) return 0; + // pragma uvmf custom do_compare begin + // UVMF_CHANGE_ME : Eliminate comparison of variables not to be used for compare + return (super.do_compare(rhs,comparer) + ); + // pragma uvmf custom do_compare end + endfunction + + //******************************************************************* + // FUNCTION: do_copy() + // This function is automatically called when the .copy() function + // is called on this class. + // + virtual function void do_copy (uvm_object rhs); + fuse_ctrl_rst_in_transaction RHS; + assert($cast(RHS,rhs)); + // pragma uvmf custom do_copy begin + super.do_copy(rhs); + this.assert_rst = RHS.assert_rst; + this.assert_otp_pwr_init = RHS.assert_otp_pwr_init; + // pragma uvmf custom do_copy end + endfunction + + // **************************************************************************** + // FUNCTION: add_to_wave() + // This function is used to display variables in this class in the waveform + // viewer. The start_time and end_time variables must be set before this + // function is called. If the start_time and end_time variables are not set + // the transaction will be hidden at 0ns on the waveform display. + // + virtual function void add_to_wave(int transaction_viewing_stream_h); + `ifdef QUESTA + if (transaction_view_h == 0) begin + transaction_view_h = $begin_transaction(transaction_viewing_stream_h,"fuse_ctrl_rst_in_transaction",start_time); + end + super.add_to_wave(transaction_view_h); + // pragma uvmf custom add_to_wave begin + // UVMF_CHANGE_ME : Color can be applied to transaction entries based on content, example below + // case() + // 1 : $add_color(transaction_view_h,"red"); + // default : $add_color(transaction_view_h,"grey"); + // endcase + // UVMF_CHANGE_ME : Eliminate transaction variables not wanted in transaction viewing in the waveform viewer + $add_attribute(transaction_view_h,assert_rst,"assert_rst"); + $add_attribute(transaction_view_h,assert_otp_pwr_init,"assert_otp_pwr_init"); + // pragma uvmf custom add_to_wave end + $end_transaction(transaction_view_h,end_time); + $free_transaction(transaction_view_h); + `endif // QUESTA + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_transaction_coverage.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_transaction_coverage.svh new file mode 100644 index 0000000..32b88a0 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_transaction_coverage.svh @@ -0,0 +1,85 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class records fuse_ctrl_rst_in transaction information using +// a covergroup named fuse_ctrl_rst_in_transaction_cg. An instance of this +// coverage component is instantiated in the uvmf_parameterized_agent +// if the has_coverage flag is set. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_rst_in_transaction_coverage extends uvm_subscriber #(.T(fuse_ctrl_rst_in_transaction )); + + `uvm_component_utils( fuse_ctrl_rst_in_transaction_coverage ) + + T coverage_trans; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + covergroup fuse_ctrl_rst_in_transaction_cg; + // pragma uvmf custom covergroup begin + // UVMF_CHANGE_ME : Add coverage bins, crosses, exclusions, etc. according to coverage needs. + option.auto_bin_max=1024; + option.per_instance=1; + assert_rst: coverpoint coverage_trans.assert_rst; + assert_otp_pwr_init: coverpoint coverage_trans.assert_otp_pwr_init; + // pragma uvmf custom covergroup end + endgroup + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new(string name="", uvm_component parent=null); + super.new(name,parent); + fuse_ctrl_rst_in_transaction_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that transaction variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + endfunction + + // **************************************************************************** + // FUNCTION : build_phase() + // This function is the standard UVM build_phase. + // + function void build_phase(uvm_phase phase); + fuse_ctrl_rst_in_transaction_cg.set_inst_name($sformatf("fuse_ctrl_rst_in_transaction_cg_%s",get_full_name())); + endfunction + + // **************************************************************************** + // FUNCTION: write (T t) + // This function is automatically executed when a transaction arrives on the + // analysis_export. It copies values from the variables in the transaction + // to local variables used to collect functional coverage. + // + virtual function void write (T t); + `uvm_info("COV","Received transaction",UVM_HIGH); + coverage_trans = t; + fuse_ctrl_rst_in_transaction_cg.sample(); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_typedefs.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_typedefs.svh new file mode 100644 index 0000000..f2a7bdb --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_typedefs.svh @@ -0,0 +1,34 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the host server when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_typedefs_hdl.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_typedefs_hdl.svh new file mode 100644 index 0000000..0d58518 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/src/fuse_ctrl_rst_in_typedefs_hdl.svh @@ -0,0 +1,35 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the emulator when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/yaml/fuse_ctrl_rst_in_interface.yaml b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/yaml/fuse_ctrl_rst_in_interface.yaml new file mode 100644 index 0000000..6da6d45 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_in_pkg/yaml/fuse_ctrl_rst_in_interface.yaml @@ -0,0 +1,39 @@ +uvmf: + interfaces: + fuse_ctrl_rst_in: + clock: clk_i + config_constraints: [] + config_vars: [] + existing_library_component: 'True' + gen_inbound_streaming_driver: 'False' + hdl_pkg_parameters: [] + hdl_typedefs: [] + hvl_pkg_parameters: [] + hvl_typedefs: [] + parameters: [] + ports: + - dir: output + name: pwr_otp_i + reset_value: '''bz' + width: '[''$bits(pwrmgr_pkg::pwr_otp_req_t)'']' + - dir: inout + name: otp_ext_voltage_h_io + reset_value: '''bz' + width: '1' + reset: rst_ni + reset_assertion_level: 'False' + transaction_constraints: [] + transaction_vars: + - comment: '' + iscompare: 'False' + isrand: 'False' + name: assert_rst + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: assert_otp_pwr_init + type: bit + unpacked_dimension: '' + use_dpi_link: 'False' diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/.project b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/.project new file mode 100644 index 0000000..dfcfc9a --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/.project @@ -0,0 +1,30 @@ + + + fuse_ctrl_rst_out_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/.svproject b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/.svproject new file mode 100644 index 0000000..e389a42 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/Makefile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/Makefile new file mode 100644 index 0000000..cec1c89 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/Makefile @@ -0,0 +1,66 @@ +# fuse_ctrl_rst_out interface packages source +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +fuse_ctrl_rst_out_PKG = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_out_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_filelist_hvl.f + +fuse_ctrl_rst_out_PKG_HDL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_out_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_filelist_hdl.f + +fuse_ctrl_rst_out_PKG_XRTL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_out_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_filelist_xrtl.f + +COMP_fuse_ctrl_rst_out_PKG_TGT_0 = q_comp_fuse_ctrl_rst_out_pkg +COMP_fuse_ctrl_rst_out_PKG_TGT_1 = v_comp_fuse_ctrl_rst_out_pkg +COMP_fuse_ctrl_rst_out_PKG_TGT = $(COMP_fuse_ctrl_rst_out_PKG_TGT_$(USE_VELOCE)) + +comp_fuse_ctrl_rst_out_pkg: $(COMP_fuse_ctrl_rst_out_PKG_TGT) + +q_comp_fuse_ctrl_rst_out_pkg: + $(HDL_COMP_CMD) $(fuse_ctrl_rst_out_PKG_HDL) + $(HVL_COMP_CMD) $(fuse_ctrl_rst_out_PKG) + $(HDL_COMP_CMD) $(fuse_ctrl_rst_out_PKG_XRTL) + +v_comp_fuse_ctrl_rst_out_pkg: + $(HVL_COMP_CMD) $(fuse_ctrl_rst_out_PKG_HDL) + $(HVL_COMP_CMD) $(fuse_ctrl_rst_out_PKG) + $(VELANALYZE_CMD) $(fuse_ctrl_rst_out_PKG_HDL) + $(VELANALYZE_HVL_CMD) $(fuse_ctrl_rst_out_PKG) + $(HDL_COMP_CMD) $(fuse_ctrl_rst_out_PKG_XRTL) + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export fuse_ctrl_rst_out_IF_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_out_pkg/dpi + +C_FILE_COMPILE_LIST_fuse_ctrl_rst_out_pkg = \ + +O_FILE_COMPILE_LIST_fuse_ctrl_rst_out_pkg = $(notdir $(C_FILE_COMPILE_LIST_fuse_ctrl_rst_out_pkg:.c=.o)) + +GCC_COMP_ARGS_fuse_ctrl_rst_out_pkg += -I$(fuse_ctrl_rst_out_IF_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_fuse_ctrl_rst_out_pkg += $(fuse_ctrl_rst_out_IF_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_fuse_ctrl_rst_out_pkg += \ + \ + -o .so + +comp_fuse_ctrl_rst_out_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Interface C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_fuse_ctrl_rst_out_pkg) $(C_FILE_COMPILE_LIST_fuse_ctrl_rst_out_pkg) + @echo "--------------------------------" + @echo "Linking Interface C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_fuse_ctrl_rst_out_pkg) $(O_FILE_COMPILE_LIST_fuse_ctrl_rst_out_pkg) + @echo "--------------------------------" + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/compile.do b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/compile.do new file mode 100644 index 0000000..d9a26ba --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/compile.do @@ -0,0 +1,14 @@ +# Tcl do file for compile of fuse_ctrl_rst_out interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_out_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_filelist_hdl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_out_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_filelist_hvl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_out_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_filelist_xrtl.f \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out.compile new file mode 100644 index 0000000..d3c0b46 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out.compile @@ -0,0 +1,3 @@ +needs: + - fuse_ctrl_rst_out_hvl.compile + - fuse_ctrl_rst_out_hdl.compile diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_bfm.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_bfm.vinfo new file mode 100644 index 0000000..6c2d817 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_bfm.vinfo @@ -0,0 +1,6 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use fuse_ctrl_rst_out_pkg_hdl.vinfo ++incdir+@vinfodir +src/fuse_ctrl_rst_out_if.sv +src/fuse_ctrl_rst_out_driver_bfm.sv +src/fuse_ctrl_rst_out_monitor_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_common.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_common.compile new file mode 100644 index 0000000..f6f7480 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_common.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +incdir: + - . + - ${uvm_path}/src +src: + - fuse_ctrl_rst_out_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_filelist_hdl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_filelist_hdl.f new file mode 100644 index 0000000..a63bb95 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_filelist_hdl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_filelist_hvl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_filelist_hvl.f new file mode 100644 index 0000000..411a2c8 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_filelist_hvl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_pkg.sv \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_filelist_xrtl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_filelist_xrtl.f new file mode 100644 index 0000000..7fb91c0 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_filelist_xrtl.f @@ -0,0 +1,3 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_if.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_monitor_bfm.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_driver_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_hdl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_hdl.compile new file mode 100644 index 0000000..e4bbfcc --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_hdl.compile @@ -0,0 +1,9 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ./fuse_ctrl_rst_out_common.compile +incdir: + - . +src: + - src/fuse_ctrl_rst_out_if.sv + - src/fuse_ctrl_rst_out_monitor_bfm.sv + - src/fuse_ctrl_rst_out_driver_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_hvl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_hvl.compile new file mode 100644 index 0000000..71b0f73 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_hvl.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ./fuse_ctrl_rst_out_common.compile +incdir: + - . +src: + - fuse_ctrl_rst_out_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_pkg.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_pkg.sv new file mode 100644 index 0000000..114980c --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_pkg.sv @@ -0,0 +1,91 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - + +// - +// - +// - + +// - +// - +// - + +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_rst_out_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg_hdl::*; + import uvmf_base_pkg::*; + import fuse_ctrl_rst_out_pkg_hdl::*; + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + `include "src/fuse_ctrl_rst_out_macros.svh" + + export fuse_ctrl_rst_out_pkg_hdl::*; + + + + // Parameters defined as HVL parameters + + `include "src/fuse_ctrl_rst_out_typedefs.svh" + `include "src/fuse_ctrl_rst_out_transaction.svh" + + `include "src/fuse_ctrl_rst_out_configuration.svh" + `include "src/fuse_ctrl_rst_out_driver.svh" + `include "src/fuse_ctrl_rst_out_monitor.svh" + + `include "src/fuse_ctrl_rst_out_transaction_coverage.svh" + `include "src/fuse_ctrl_rst_out_sequence_base.svh" + `include "src/fuse_ctrl_rst_out_random_sequence.svh" + + `include "src/fuse_ctrl_rst_out_responder_sequence.svh" + `include "src/fuse_ctrl_rst_out2reg_adapter.svh" + + `include "src/fuse_ctrl_rst_out_agent.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new interface sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the interface package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_pkg.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_pkg.vinfo new file mode 100644 index 0000000..e117063 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_pkg.vinfo @@ -0,0 +1,4 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use fuse_ctrl_rst_out_pkg_hdl.vinfo ++incdir+@vinfodir +fuse_ctrl_rst_out_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_pkg_hdl.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_pkg_hdl.sv new file mode 100644 index 0000000..0dca9e6 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_pkg_hdl.sv @@ -0,0 +1,52 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that needs to be compiled and synthesized +// for running on Veloce. +// +// CONTAINS: +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_rst_out_pkg_hdl; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HDL parameters + + `include "src/fuse_ctrl_rst_out_typedefs_hdl.svh" + `include "src/fuse_ctrl_rst_out_macros.svh" + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_pkg_hdl.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_pkg_hdl.vinfo new file mode 100644 index 0000000..3d6a42b --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_pkg_hdl.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +fuse_ctrl_rst_out_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_pkg_sve.F b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_pkg_sve.F new file mode 100644 index 0000000..a4e1931 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_pkg_sve.F @@ -0,0 +1,10 @@ +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + ++incdir+. +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_filelist_hdl.f +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_rst_out_pkg/fuse_ctrl_rst_out_filelist_hvl.f diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out2reg_adapter.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out2reg_adapter.svh new file mode 100644 index 0000000..ebcb194 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out2reg_adapter.svh @@ -0,0 +1,112 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the UVM register adapter for the fuse_ctrl_rst_out interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_rst_out2reg_adapter extends uvm_reg_adapter; + + `uvm_object_utils( fuse_ctrl_rst_out2reg_adapter ) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //-------------------------------------------------------------------- + // new + //-------------------------------------------------------------------- + function new (string name = "fuse_ctrl_rst_out2reg_adapter" ); + super.new(name); + // pragma uvmf custom new begin + // UVMF_CHANGE_ME : Configure the adapter regarding byte enables and provides response. + + // Does the protocol the Agent is modeling support byte enables? + // 0 = NO + // 1 = YES + supports_byte_enable = 0; + + // Does the Agent's Driver provide separate response sequence items? + // i.e. Does the driver call seq_item_port.put() + // and do the sequences call get_response()? + // 0 = NO + // 1 = YES + provides_responses = 0; + // pragma uvmf custom new end + + endfunction: new + + //-------------------------------------------------------------------- + // reg2bus + //-------------------------------------------------------------------- + virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw); + + fuse_ctrl_rst_out_transaction trans_h = fuse_ctrl_rst_out_transaction ::type_id::create("trans_h"); + + // pragma uvmf custom reg2bus begin + // UVMF_CHANGE_ME : Fill in the reg2bus adapter mapping registe fields to protocol fields. + + //Adapt the following for your sequence item type + // trans_h.op = (rw.kind == UVM_READ) ? WB_READ : WB_WRITE; + //Copy over address + // trans_h.addr = rw.addr; + //Copy over write data + // trans_h.data = rw.data; + + // pragma uvmf custom reg2bus end + + // Return the adapted transaction + return trans_h; + + endfunction: reg2bus + + //-------------------------------------------------------------------- + // bus2reg + //-------------------------------------------------------------------- + virtual function void bus2reg(uvm_sequence_item bus_item, + ref uvm_reg_bus_op rw); + fuse_ctrl_rst_out_transaction trans_h; + if (!$cast(trans_h, bus_item)) begin + `uvm_fatal("ADAPT","Provided bus_item is not of the correct type") + return; + end + // pragma uvmf custom bus2reg begin + // UVMF_CHANGE_ME : Fill in the bus2reg adapter mapping protocol fields to register fields. + //Adapt the following for your sequence item type + //Copy over instruction type + // rw.kind = (trans_h.op == WB_WRITE) ? UVM_WRITE : UVM_READ; + //Copy over address + // rw.addr = trans_h.addr; + //Copy over read data + // rw.data = trans_h.data; + //Check for errors on the bus and return UVM_NOT_OK if there is an error + // rw.status = UVM_IS_OK; + // pragma uvmf custom bus2reg end + + endfunction: bus2reg + +endclass : fuse_ctrl_rst_out2reg_adapter + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_agent.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_agent.svh new file mode 100644 index 0000000..72f514f --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_agent.svh @@ -0,0 +1,67 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: Protocol specific agent class definition +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_rst_out_agent extends uvmf_parameterized_agent #( + .CONFIG_T(fuse_ctrl_rst_out_configuration ), + .DRIVER_T(fuse_ctrl_rst_out_driver ), + .MONITOR_T(fuse_ctrl_rst_out_monitor ), + .COVERAGE_T(fuse_ctrl_rst_out_transaction_coverage ), + .TRANS_T(fuse_ctrl_rst_out_transaction ) + ); + + `uvm_component_utils( fuse_ctrl_rst_out_agent ) + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** + // FUNCTION: build_phase + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + if (configuration.active_passive == ACTIVE) begin + // Place sequencer handle into configuration object + // so that it may be retrieved from configuration + // rather than using uvm_config_db + configuration.sequencer = this.sequencer; + end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_configuration.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_configuration.svh new file mode 100644 index 0000000..cc1788a --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_configuration.svh @@ -0,0 +1,193 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class contains all variables and functions used +// to configure the fuse_ctrl_rst_out agent and its bfm's. It gets the +// bfm's from the uvm_config_db for use by the agent. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_rst_out_configuration extends uvmf_parameterized_agent_configuration_base #( + .DRIVER_BFM_BIND_T(virtual fuse_ctrl_rst_out_driver_bfm ), + .MONITOR_BFM_BIND_T( virtual fuse_ctrl_rst_out_monitor_bfm )); + + `uvm_object_utils( fuse_ctrl_rst_out_configuration ) + + + // Sequencer handle populated by agent + uvm_sequencer #(fuse_ctrl_rst_out_transaction ) sequencer; + + //Constraints for the configuration variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + covergroup fuse_ctrl_rst_out_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + // pragma uvmf custom covergroup end + endgroup + + //******************************************************************* + //******************************************************************* + // Structure used to pass configuration variables to monitor and driver BFM's. + // Use to_struct function to pack variables into structure. + // Use from_struct function to unpack variables from structure. + // This structure is defined in fuse_ctrl_rst_out_macros.svh + `fuse_ctrl_rst_out_CONFIGURATION_STRUCT + fuse_ctrl_rst_out_configuration_s fuse_ctrl_rst_out_configuration_struct; + //******************************************************************* + // FUNCTION: to_struct() + // This function packs variables into a fuse_ctrl_rst_out_configuration_s + // structure. The function returns the handle to the fuse_ctrl_rst_out_configuration_struct. + // This function is defined in fuse_ctrl_rst_out_macros.svh + `fuse_ctrl_rst_out_CONFIGURATION_TO_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_struct() + // This function unpacks the struct provided as an argument into + // variables of this class. + // This function is defined in fuse_ctrl_rst_out_macros.svh + `fuse_ctrl_rst_out_CONFIGURATION_FROM_STRUCT_FUNCTION + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + // Construct the covergroup for this configuration class + fuse_ctrl_rst_out_configuration_cg = new; + endfunction + + // **************************************************************************** + // FUNCTION: post_randomize() + // This function is automatically called after the randomize() function + // is executed. + // + function void post_randomize(); + super.post_randomize(); + fuse_ctrl_rst_out_configuration_cg.sample(); + endfunction + + // **************************************************************************** + // FUNCTION: initialize + // This function causes the configuration to retrieve + // its virtual interface handle from the uvm_config_db. + // This function also makes itself available to its + // agent through the uvm_config_db. + // + // ARGUMENTS: + // uvmf_active_passive_t activity: + // This argument identifies the simulation level + // as either BLOCK, CHIP, SIMULATION, etc. + // + // AGENT_PATH: + // This argument identifies the path to this + // configurations agent. This configuration + // makes itself available to the agent specified + // by agent_path by placing itself into the + // uvm_config_db. + // + // INTERFACE_NAME: + // This argument identifies the string name of + // this configurations BFM's. This string + // name is used to retrieve the driver and + // monitor BFM from the uvm_config_db. + // + virtual function void initialize(uvmf_active_passive_t activity, + string agent_path, + string interface_name); + + super.initialize( activity, agent_path, interface_name); + // The covergroup is given the same name as the interface + fuse_ctrl_rst_out_configuration_cg.set_inst_name(interface_name); + + // This configuration places itself into the uvm_config_db for the agent, identified by the agent_path variable, to retrieve. + uvm_config_db #( fuse_ctrl_rst_out_configuration + )::set( null ,agent_path,UVMF_AGENT_CONFIG, this ); + + // This configuration also places itself in the config db using the same identifier used by the interface. This allows users to access + // configuration variables and the interface through the bfm api class rather than directly accessing the BFM. This is useful for + // accessingthe BFM when using Veloce + uvm_config_db #( fuse_ctrl_rst_out_configuration + )::set( null ,UVMF_CONFIGURATIONS, interface_name, this ); + + fuse_ctrl_rst_out_configuration_cg.set_inst_name($sformatf("fuse_ctrl_rst_out_configuration_cg_%s",get_full_name())); + +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. + `uvm_info("CFG", + $psprintf("The agent at '%s' is using interface named %s has the following parameters: ", agent_path, interface_name, ), + UVM_DEBUG) + + // pragma uvmf custom initialize begin + // This controls whether or not the agent returns a transaction handle in the driver when calling + // item_done() back into the sequencer or not. If set to 1, a transaction is sent back which means + // the sequence on the other end must use the get_response() part of the driver/sequence API. If + // this doesn't occur, there will eventually be response_queue overflow errors during the test. + return_transaction_response = 1'b0; + + // pragma uvmf custom initialize end + + endfunction + + // **************************************************************************** + // TASK: wait_for_reset + // *[Required]* Blocks until reset is released. The wait_for_reset operation is performed + // by a task in the monitor bfm. + virtual task wait_for_reset(); + monitor_bfm.wait_for_reset(); + endtask + + // **************************************************************************** + // TASK: wait_for_num_clocks + // *[Required]* Blocks until specified number of clocks have elapsed. The wait_for_num_clocks + // operation is performed by a task in the monitor bfm. + virtual task wait_for_num_clocks(int clocks); + monitor_bfm.wait_for_num_clocks(clocks); + endtask + + // **************************************************************************** + // FUNCTION : convert2string() + // This function is used to convert variables in this class into a string for log messaging. + // + virtual function string convert2string (); + // pragma uvmf custom convert2string begin + return $sformatf(""); + // pragma uvmf custom convert2string end + endfunction + + // **************************************************************************** + // FUNCTION: get_sequencer + function uvm_sequencer #(fuse_ctrl_rst_out_transaction) get_sequencer(); + return sequencer; + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_driver.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_driver.svh new file mode 100644 index 0000000..6b15dc2 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_driver.svh @@ -0,0 +1,105 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class passes transactions between the sequencer +// and the BFM driver interface. It accesses the driver BFM +// through the bfm handle. This driver +// passes transactions to the driver BFM through the access +// task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_rst_out_driver extends uvmf_driver_base #( + .CONFIG_T(fuse_ctrl_rst_out_configuration ), + .BFM_BIND_T(virtual fuse_ctrl_rst_out_driver_bfm ), + .REQ(fuse_ctrl_rst_out_transaction ), + .RSP(fuse_ctrl_rst_out_transaction )); + + `uvm_component_utils( fuse_ctrl_rst_out_driver ) +//******************************************************************* +// Macros that define structs located in fuse_ctrl_rst_out_macros.svh +//******************************************************************* +// Initiator macro used by fuse_ctrl_rst_out_driver and fuse_ctrl_rst_out_driver_bfm +// to communicate initiator driven data to fuse_ctrl_rst_out_driver_bfm. +`fuse_ctrl_rst_out_INITIATOR_STRUCT + fuse_ctrl_rst_out_initiator_s fuse_ctrl_rst_out_initiator_struct; +//******************************************************************* +// Responder macro used by fuse_ctrl_rst_out_driver and fuse_ctrl_rst_out_driver_bfm +// to communicate Responder driven data to fuse_ctrl_rst_out_driver_bfm. +`fuse_ctrl_rst_out_RESPONDER_STRUCT + fuse_ctrl_rst_out_responder_s fuse_ctrl_rst_out_responder_struct; + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent=null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the driver BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// driver BFM. This allows the driver BFM to call tasks and function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// **************************************************************************** +// This task is called by the run_phase in uvmf_driver_base. + virtual task access( inout REQ txn ); +// pragma uvmf custom access begin + if (configuration.initiator_responder==RESPONDER) begin + // Complete current transfer and wait for next transfer + bfm.respond_and_wait_for_next_transfer( + fuse_ctrl_rst_out_initiator_struct, + txn.to_responder_struct() + ); + // Unpack information about initiated transfer received by this responder + txn.from_initiator_struct(fuse_ctrl_rst_out_initiator_struct); + end else begin + // Initiate a transfer and get response + bfm.initiate_and_get_response( + txn.to_initiator_struct(), + fuse_ctrl_rst_out_responder_struct + ); + // Unpack transfer response information received by this initiator + txn.from_responder_struct(fuse_ctrl_rst_out_responder_struct); + end +// pragma uvmf custom access end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_driver_bfm.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_driver_bfm.sv new file mode 100644 index 0000000..b66cf3d --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_driver_bfm.sv @@ -0,0 +1,294 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This interface performs the fuse_ctrl_rst_out signal driving. It is +// accessed by the uvm fuse_ctrl_rst_out driver through a virtual interface +// handle in the fuse_ctrl_rst_out configuration. It drives the singals passed +// in through the port connection named bus of type fuse_ctrl_rst_out_if. +// +// Input signals from the fuse_ctrl_rst_out_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// This bfm drives signals with a _o suffix. These signals +// are driven onto signals within fuse_ctrl_rst_out_if based on INITIATOR/RESPONDER and/or +// ARBITRATION/GRANT status. +// +// The output signal connections are as follows: +// signal_o -> bus.signal +// +// +// Interface functions and tasks used by UVM components: +// +// configure: +// This function gets configuration attributes from the +// UVM driver to set any required BFM configuration +// variables such as 'initiator_responder'. +// +// initiate_and_get_response: +// This task is used to perform signaling activity for initiating +// a protocol transfer. The task initiates the transfer, using +// input data from the initiator struct. Then the task captures +// response data, placing the data into the response struct. +// The response struct is returned to the driver class. +// +// respond_and_wait_for_next_transfer: +// This task is used to complete a current transfer as a responder +// and then wait for the initiator to start the next transfer. +// The task uses data in the responder struct to drive protocol +// signals to complete the transfer. The task then waits for +// the next transfer. Once the next transfer begins, data from +// the initiator is placed into the initiator struct and sent +// to the responder sequence for processing to determine +// what data to respond with. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_rst_out_pkg_hdl::*; +`include "src/fuse_ctrl_rst_out_macros.svh" + +interface fuse_ctrl_rst_out_driver_bfm + (fuse_ctrl_rst_out_if bus); + // The following pragma and additional ones in-lined further below are for running this BFM on Veloce + // pragma attribute fuse_ctrl_rst_out_driver_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: ", ), + UVM_DEBUG) +end +`endif + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + tri clk_i_i; + tri rst_ni_i; + + // Signal list (all signals are capable of being inputs and outputs for the sake + // of supporting both INITIATOR and RESPONDER mode operation. Expectation is that + // directionality in the config file was from the point-of-view of the INITIATOR + + // INITIATOR mode input signals + tri [$bits(pwrmgr_pkg::pwr_otp_rsp_t)-1:0] pwr_otp_o_i; + reg [$bits(pwrmgr_pkg::pwr_otp_rsp_t)-1:0] pwr_otp_o_o = 'bz; + + // INITIATOR mode output signals + + // Bi-directional signals + tri otp_ext_voltage_h_io_i; + reg otp_ext_voltage_h_io_o = 'bz; + + + assign clk_i_i = bus.clk_i; + assign rst_ni_i = bus.rst_ni; + + // These are signals marked as 'input' by the config file, but the signals will be + // driven by this BFM if put into RESPONDER mode (flipping all signal directions around) + assign pwr_otp_o_i = bus.pwr_otp_o; + assign bus.pwr_otp_o = (initiator_responder == RESPONDER) ? pwr_otp_o_o : 'bz; + + assign otp_ext_voltage_h_io_i = bus.otp_ext_voltage_h_io; + + // These are signals marked as 'output' by the config file, but the outputs will + // not be driven by this BFM unless placed in INITIATOR mode. + assign bus.otp_ext_voltage_h_io = otp_ext_voltage_h_io_o; + + // Proxy handle to UVM driver + fuse_ctrl_rst_out_pkg::fuse_ctrl_rst_out_driver proxy; + // pragma tbx oneway proxy.my_function_name_in_uvm_driver + + // **************************************************************************** + // **************************************************************************** + // Macros that define structs located in fuse_ctrl_rst_out_macros.svh + // **************************************************************************** + // Struct for passing configuration data from fuse_ctrl_rst_out_driver to this BFM + // **************************************************************************** + `fuse_ctrl_rst_out_CONFIGURATION_STRUCT + // **************************************************************************** + // Structs for INITIATOR and RESPONDER data flow + //******************************************************************* + // Initiator macro used by fuse_ctrl_rst_out_driver and fuse_ctrl_rst_out_driver_bfm + // to communicate initiator driven data to fuse_ctrl_rst_out_driver_bfm. + `fuse_ctrl_rst_out_INITIATOR_STRUCT + fuse_ctrl_rst_out_initiator_s initiator_struct; + // Responder macro used by fuse_ctrl_rst_out_driver and fuse_ctrl_rst_out_driver_bfm + // to communicate Responder driven data to fuse_ctrl_rst_out_driver_bfm. + `fuse_ctrl_rst_out_RESPONDER_STRUCT + fuse_ctrl_rst_out_responder_s responder_struct; + + // **************************************************************************** +// pragma uvmf custom reset_condition_and_response begin + // Always block used to return signals to reset value upon assertion of reset + always @( negedge rst_ni_i ) + begin + // RESPONDER mode output signals + pwr_otp_o_o <= 'bz; + // INITIATOR mode output signals + // Bi-directional signals + otp_ext_voltage_h_io_o <= 'bz; + + end +// pragma uvmf custom reset_condition_and_response end + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the driver BFM. It is called by the driver within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the driver BFM needs to be aware of the new configuration + // variables. + // + + function void configure(fuse_ctrl_rst_out_configuration_s fuse_ctrl_rst_out_configuration_arg); // pragma tbx xtf + initiator_responder = fuse_ctrl_rst_out_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + +// pragma uvmf custom initiate_and_get_response begin +// **************************************************************************** +// UVMF_CHANGE_ME +// This task is used by an initator. The task first initiates a transfer then +// waits for the responder to complete the transfer. + task initiate_and_get_response( + // This argument passes transaction variables used by an initiator + // to perform the initial part of a protocol transfer. The values + // come from a sequence item created in a sequence. + input fuse_ctrl_rst_out_initiator_s fuse_ctrl_rst_out_initiator_struct, + // This argument is used to send data received from the responder + // back to the sequence item. The sequence item is returned to the sequence. + output fuse_ctrl_rst_out_responder_s fuse_ctrl_rst_out_responder_struct + );// pragma tbx xtf + // + // Members within the fuse_ctrl_rst_out_initiator_struct: + // pwrmgr_pkg::pwr_otp_rsp_t pwr_otp_o ; + // Members within the fuse_ctrl_rst_out_responder_struct: + // pwrmgr_pkg::pwr_otp_rsp_t pwr_otp_o ; + initiator_struct = fuse_ctrl_rst_out_initiator_struct; + // + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clk_i_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available initiator input and inout signals listed. + // Initiator input signals + // fuse_ctrl_rst_out_responder_struct.xyz = pwr_otp_o_i; // [$bits(pwrmgr_pkg::pwr_otp_rsp_t)-1:0] + // Initiator inout signals + // fuse_ctrl_rst_out_responder_struct.xyz = otp_ext_voltage_h_io_i; // + // How to assign a signal from an initiator struct member named xyz. + // All available initiator output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Initiator output signals + // Initiator inout signals + // otp_ext_voltage_h_io_o <= fuse_ctrl_rst_out_initiator_struct.xyz; // + // Initiate a transfer using the data received. + @(posedge clk_i_i); + @(posedge clk_i_i); + // Wait for the responder to complete the transfer then place the responder data into + // fuse_ctrl_rst_out_responder_struct. + @(posedge clk_i_i); + @(posedge clk_i_i); + responder_struct = fuse_ctrl_rst_out_responder_struct; + endtask +// pragma uvmf custom initiate_and_get_response end + +// pragma uvmf custom respond_and_wait_for_next_transfer begin +// **************************************************************************** +// The first_transfer variable is used to prevent completing a transfer in the +// first call to this task. For the first call to this task, there is not +// current transfer to complete. +bit first_transfer=1; + +// UVMF_CHANGE_ME +// This task is used by a responder. The task first completes the current +// transfer in progress then waits for the initiator to start the next transfer. + task respond_and_wait_for_next_transfer( + // This argument is used to send data received from the initiator + // back to the sequence item. The sequence determines how to respond. + output fuse_ctrl_rst_out_initiator_s fuse_ctrl_rst_out_initiator_struct, + // This argument passes transaction variables used by a responder + // to complete a protocol transfer. The values come from a sequence item. + input fuse_ctrl_rst_out_responder_s fuse_ctrl_rst_out_responder_struct + );// pragma tbx xtf + // Variables within the fuse_ctrl_rst_out_initiator_struct: + // pwrmgr_pkg::pwr_otp_rsp_t pwr_otp_o ; + // Variables within the fuse_ctrl_rst_out_responder_struct: + // pwrmgr_pkg::pwr_otp_rsp_t pwr_otp_o ; + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clk_i_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available responder input and inout signals listed. + // Responder input signals + // Responder inout signals + // fuse_ctrl_rst_out_responder_struct.xyz = otp_ext_voltage_h_io_i; // + // How to assign a signal, named xyz, from an initiator struct member. + // All available responder output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Responder output signals + // pwr_otp_o_o <= fuse_ctrl_rst_out_initiator_struct.xyz; // [$bits(pwrmgr_pkg::pwr_otp_rsp_t)-1:0] + // Responder inout signals + // otp_ext_voltage_h_io_o <= fuse_ctrl_rst_out_initiator_struct.xyz; // + + @(posedge clk_i_i); + if (!first_transfer) begin + // Perform transfer response here. + // Reply using data recieved in the fuse_ctrl_rst_out_responder_struct. + @(posedge clk_i_i); + // Reply using data recieved in the transaction handle. + @(posedge clk_i_i); + end + // Wait for next transfer then gather info from intiator about the transfer. + // Place the data into the fuse_ctrl_rst_out_initiator_struct. + @(posedge clk_i_i); + @(posedge clk_i_i); + first_transfer = 0; + endtask +// pragma uvmf custom respond_and_wait_for_next_transfer end + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_if.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_if.sv new file mode 100644 index 0000000..d510f9f --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_if.sv @@ -0,0 +1,83 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface contains the fuse_ctrl_rst_out interface signals. +// It is instantiated once per fuse_ctrl_rst_out bus. Bus Functional Models, +// BFM's named fuse_ctrl_rst_out_driver_bfm, are used to drive signals on the bus. +// BFM's named fuse_ctrl_rst_out_monitor_bfm are used to monitor signals on the +// bus. This interface signal bundle is passed in the port list of +// the BFM in order to give the BFM access to the signals in this +// interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// This template can be used to connect a DUT to these signals +// +// .dut_signal_port(fuse_ctrl_rst_out_bus.pwr_otp_o), // Agent input +// .dut_signal_port(fuse_ctrl_rst_out_bus.otp_ext_voltage_h_io), // Agent inout + +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_rst_out_pkg_hdl::*; + +interface fuse_ctrl_rst_out_if + + ( + input tri clk_i, + input tri rst_ni, + inout tri [$bits(pwrmgr_pkg::pwr_otp_rsp_t)-1:0] pwr_otp_o, + inout tri otp_ext_voltage_h_io + ); + +modport monitor_port + ( + input clk_i, + input rst_ni, + input pwr_otp_o, + input otp_ext_voltage_h_io + ); + +modport initiator_port + ( + input clk_i, + input rst_ni, + input pwr_otp_o, + inout otp_ext_voltage_h_io + ); + +modport responder_port + ( + input clk_i, + input rst_ni, + output pwr_otp_o, + inout otp_ext_voltage_h_io + ); + + +// pragma uvmf custom interface_item_additional begin +// pragma uvmf custom interface_item_additional end + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_infact_coverage_strategy.csv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_infact_coverage_strategy.csv new file mode 100644 index 0000000..1c218e1 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_infact_coverage_strategy.csv @@ -0,0 +1,6 @@ +Global +auto_bin_max, 64 + +Name,Type,Include +rand_fields,coverpoint,=rand *.** + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_macros.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_macros.svh new file mode 100644 index 0000000..244a2c7 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_macros.svh @@ -0,0 +1,135 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains macros used with the fuse_ctrl_rst_out package. +// These macros include packed struct definitions. These structs are +// used to pass data between classes, hvl, and BFM's, hdl. Use of +// structs are more efficient and simpler to modify. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_struct +// and from_struct methods defined in the macros below that are used in +// the fuse_ctrl_rst_out_configuration class. +// + `define fuse_ctrl_rst_out_CONFIGURATION_STRUCT \ +typedef struct packed { \ + uvmf_active_passive_t active_passive; \ + uvmf_initiator_responder_t initiator_responder; \ + } fuse_ctrl_rst_out_configuration_s; + + `define fuse_ctrl_rst_out_CONFIGURATION_TO_STRUCT_FUNCTION \ + virtual function fuse_ctrl_rst_out_configuration_s to_struct();\ + fuse_ctrl_rst_out_configuration_struct = \ + {\ + this.active_passive,\ + this.initiator_responder\ + };\ + return ( fuse_ctrl_rst_out_configuration_struct );\ + endfunction + + `define fuse_ctrl_rst_out_CONFIGURATION_FROM_STRUCT_FUNCTION \ + virtual function void from_struct(fuse_ctrl_rst_out_configuration_s fuse_ctrl_rst_out_configuration_struct);\ + {\ + this.active_passive,\ + this.initiator_responder \ + } = fuse_ctrl_rst_out_configuration_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_monitor_struct +// and from_monitor_struct methods of the fuse_ctrl_rst_out_transaction class. +// + `define fuse_ctrl_rst_out_MONITOR_STRUCT typedef struct packed { \ + pwrmgr_pkg::pwr_otp_rsp_t pwr_otp_o ; \ + } fuse_ctrl_rst_out_monitor_s; + + `define fuse_ctrl_rst_out_TO_MONITOR_STRUCT_FUNCTION \ + virtual function fuse_ctrl_rst_out_monitor_s to_monitor_struct();\ + fuse_ctrl_rst_out_monitor_struct = \ + { \ + this.pwr_otp_o \ + };\ + return ( fuse_ctrl_rst_out_monitor_struct);\ + endfunction\ + + `define fuse_ctrl_rst_out_FROM_MONITOR_STRUCT_FUNCTION \ + virtual function void from_monitor_struct(fuse_ctrl_rst_out_monitor_s fuse_ctrl_rst_out_monitor_struct);\ + {\ + this.pwr_otp_o \ + } = fuse_ctrl_rst_out_monitor_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_initiator_struct +// and from_initiator_struct methods of the fuse_ctrl_rst_out_transaction class. +// Also update the comments in the driver BFM. +// + `define fuse_ctrl_rst_out_INITIATOR_STRUCT typedef struct packed { \ + pwrmgr_pkg::pwr_otp_rsp_t pwr_otp_o ; \ + } fuse_ctrl_rst_out_initiator_s; + + `define fuse_ctrl_rst_out_TO_INITIATOR_STRUCT_FUNCTION \ + virtual function fuse_ctrl_rst_out_initiator_s to_initiator_struct();\ + fuse_ctrl_rst_out_initiator_struct = \ + {\ + this.pwr_otp_o \ + };\ + return ( fuse_ctrl_rst_out_initiator_struct);\ + endfunction + + `define fuse_ctrl_rst_out_FROM_INITIATOR_STRUCT_FUNCTION \ + virtual function void from_initiator_struct(fuse_ctrl_rst_out_initiator_s fuse_ctrl_rst_out_initiator_struct);\ + {\ + this.pwr_otp_o \ + } = fuse_ctrl_rst_out_initiator_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_responder_struct +// and from_responder_struct methods of the fuse_ctrl_rst_out_transaction class. +// Also update the comments in the driver BFM. +// + `define fuse_ctrl_rst_out_RESPONDER_STRUCT typedef struct packed { \ + pwrmgr_pkg::pwr_otp_rsp_t pwr_otp_o ; \ + } fuse_ctrl_rst_out_responder_s; + + `define fuse_ctrl_rst_out_TO_RESPONDER_STRUCT_FUNCTION \ + virtual function fuse_ctrl_rst_out_responder_s to_responder_struct();\ + fuse_ctrl_rst_out_responder_struct = \ + {\ + this.pwr_otp_o \ + };\ + return ( fuse_ctrl_rst_out_responder_struct);\ + endfunction + + `define fuse_ctrl_rst_out_FROM_RESPONDER_STRUCT_FUNCTION \ + virtual function void from_responder_struct(fuse_ctrl_rst_out_responder_s fuse_ctrl_rst_out_responder_struct);\ + {\ + this.pwr_otp_o \ + } = fuse_ctrl_rst_out_responder_struct;\ + endfunction +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_monitor.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_monitor.svh new file mode 100644 index 0000000..22093ba --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_monitor.svh @@ -0,0 +1,101 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class receives fuse_ctrl_rst_out transactions observed by the +// fuse_ctrl_rst_out monitor BFM and broadcasts them through the analysis port +// on the agent. It accesses the monitor BFM through the monitor +// task. This UVM component captures transactions +// for viewing in the waveform viewer if the +// enable_transaction_viewing flag is set in the configuration. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_rst_out_monitor extends uvmf_monitor_base #( + .CONFIG_T(fuse_ctrl_rst_out_configuration ), + .BFM_BIND_T(virtual fuse_ctrl_rst_out_monitor_bfm ), + .TRANS_T(fuse_ctrl_rst_out_transaction )); + + `uvm_component_utils( fuse_ctrl_rst_out_monitor ) + +// Structure used to pass data from monitor BFM to monitor class in agent. +// Use to_monitor_struct function to pack transaction variables into structure. +// Use from_monitor_struct function to unpack transaction variables from structure. +`fuse_ctrl_rst_out_MONITOR_STRUCT + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the monitor BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// monitor BFM. This allows the monitor BFM to call the notify_transaction +// function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// *************************************************************************** + virtual task run_phase(uvm_phase phase); + // Start monitor BFM thread and don't call super.run() in order to + // override the default monitor proxy 'pull' behavior with the more + // emulation-friendly BFM 'push' approach using the notify_transaction + // function below + bfm.start_monitoring(); + endtask + +// ************************************************************************** + +// This function is called by the monitor BFM. It receives data observed by the +// monitor BFM. Data is passed using the fuse_ctrl_rst_out_monitor_struct. + virtual function void notify_transaction(input fuse_ctrl_rst_out_monitor_s fuse_ctrl_rst_out_monitor_struct); + + + trans = new("trans"); + trans.from_monitor_struct(fuse_ctrl_rst_out_monitor_struct); + trans.start_time = time_stamp; + trans.end_time = $time; + time_stamp = trans.end_time; + + analyze(trans); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_monitor_bfm.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_monitor_bfm.sv new file mode 100644 index 0000000..035c794 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_monitor_bfm.sv @@ -0,0 +1,198 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface performs the fuse_ctrl_rst_out signal monitoring. +// It is accessed by the uvm fuse_ctrl_rst_out monitor through a virtual +// interface handle in the fuse_ctrl_rst_out configuration. It monitors the +// signals passed in through the port connection named bus of +// type fuse_ctrl_rst_out_if. +// +// Input signals from the fuse_ctrl_rst_out_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// Interface functions and tasks used by UVM components: +// monitor(inout TRANS_T txn); +// This task receives the transaction, txn, from the +// UVM monitor and then populates variables in txn +// from values observed on bus activity. This task +// blocks until an operation on the fuse_ctrl_rst_out bus is complete. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_rst_out_pkg_hdl::*; +`include "src/fuse_ctrl_rst_out_macros.svh" + + +interface fuse_ctrl_rst_out_monitor_bfm + ( fuse_ctrl_rst_out_if bus ); + // The pragma below and additional ones in-lined further down are for running this BFM on Veloce + // pragma attribute fuse_ctrl_rst_out_monitor_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: ", ), + UVM_DEBUG) +end +`endif + + + // Structure used to pass transaction data from monitor BFM to monitor class in agent. +`fuse_ctrl_rst_out_MONITOR_STRUCT + fuse_ctrl_rst_out_monitor_s fuse_ctrl_rst_out_monitor_struct; + + // Structure used to pass configuration data from monitor class to monitor BFM. + `fuse_ctrl_rst_out_CONFIGURATION_STRUCT + + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + tri clk_i_i; + tri rst_ni_i; + tri [$bits(pwrmgr_pkg::pwr_otp_rsp_t)-1:0] pwr_otp_o_i; + tri otp_ext_voltage_h_io_i; + assign clk_i_i = bus.clk_i; + assign rst_ni_i = bus.rst_ni; + assign pwr_otp_o_i = bus.pwr_otp_o; + assign otp_ext_voltage_h_io_i = bus.otp_ext_voltage_h_io; + + // Proxy handle to UVM monitor + fuse_ctrl_rst_out_pkg::fuse_ctrl_rst_out_monitor proxy; + // pragma tbx oneway proxy.notify_transaction + + // pragma uvmf custom interface_item_additional begin + reg pwr_otp_o_o = 'b0; + + function bit any_signal_changed(); + return |(pwr_otp_o_i ^ pwr_otp_o_o); + endfunction + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + task wait_for_reset();// pragma tbx xtf + @(posedge clk_i_i) ; + do_wait_for_reset(); + endtask + + // **************************************************************************** + task do_wait_for_reset(); + // pragma uvmf custom reset_condition begin + wait ( rst_ni_i === 1 ) ; + @(posedge clk_i_i) ; + // pragma uvmf custom reset_condition end + endtask + + //****************************************************************** + + task wait_for_num_clocks(input int unsigned count); // pragma tbx xtf + @(posedge clk_i_i); + + repeat (count-1) @(posedge clk_i_i); + endtask + + //****************************************************************** + event go; + function void start_monitoring();// pragma tbx xtf + -> go; + endfunction + + // **************************************************************************** + initial begin + @go; + forever begin + @(posedge clk_i_i); + do_monitor( fuse_ctrl_rst_out_monitor_struct ); + + + proxy.notify_transaction( fuse_ctrl_rst_out_monitor_struct ); + + end + end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the monitor BFM. It is called by the monitor within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the monitor BFM needs to be aware of the new configuration + // variables. + // + function void configure(fuse_ctrl_rst_out_configuration_s fuse_ctrl_rst_out_configuration_arg); // pragma tbx xtf + initiator_responder = fuse_ctrl_rst_out_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + + + // **************************************************************************** + + task do_monitor(output fuse_ctrl_rst_out_monitor_s fuse_ctrl_rst_out_monitor_struct); + // + // Available struct members: + // // fuse_ctrl_rst_out_monitor_struct.pwr_otp_o + // // + // Reference code; + // How to wait for signal value + // while (control_signal === 1'b1) @(posedge clk_i_i); + // + // How to assign a struct member, named xyz, from a signal. + // All available input signals listed. + // fuse_ctrl_rst_out_monitor_struct.xyz = pwr_otp_o_i; // [$bits(pwrmgr_pkg::pwr_otp_rsp_t)-1:0] + // fuse_ctrl_rst_out_monitor_struct.xyz = otp_ext_voltage_h_io_i; // + // pragma uvmf custom do_monitor begin + // UVMF_CHANGE_ME : Implement protocol monitoring. The commented reference code + // below are examples of how to capture signal values and assign them to + // structure members. All available input signals are listed. The 'while' + // code example shows how to wait for a synchronous flow control signal. This + // task should return when a complete transfer has been observed. Once this task is + // exited with captured values, it is then called again to wait for and observe + // the next transfer. One clock cycle is consumed between calls to do_monitor. + while (!any_signal_changed()) @(posedge clk_i_i); + + pwr_otp_o_o <= pwr_otp_o_i; + + fuse_ctrl_rst_out_monitor_struct.assert_rst = !rst_ni_i; + fuse_ctrl_rst_out_monitor_struct.assert_otp_init = pwr_otp_o_o; + // pragma uvmf custom do_monitor end + endtask + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_random_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_random_sequence.svh new file mode 100644 index 0000000..448cc51 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_random_sequence.svh @@ -0,0 +1,67 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This sequences randomizes the fuse_ctrl_rst_out transaction and sends it +// to the UVM driver. +// +// This sequence constructs and randomizes a fuse_ctrl_rst_out_transaction. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_rst_out_random_sequence + extends fuse_ctrl_rst_out_sequence_base ; + + `uvm_object_utils( fuse_ctrl_rst_out_random_sequence ) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //***************************************************************** + function new(string name = ""); + super.new(name); + endfunction: new + + // **************************************************************************** + // TASK : body() + // This task is automatically executed when this sequence is started using the + // start(sequencerHandle) task. + // + task body(); + + // Construct the transaction + req=fuse_ctrl_rst_out_transaction::type_id::create("req"); + start_item(req); + // Randomize the transaction + if(!req.randomize()) `uvm_fatal("SEQ", "fuse_ctrl_rst_out_random_sequence::body()-fuse_ctrl_rst_out_transaction randomization failed") + // Send the transaction to the fuse_ctrl_rst_out_driver_bfm via the sequencer and fuse_ctrl_rst_out_driver. + finish_item(req); + `uvm_info("SEQ", {"Response:",req.convert2string()},UVM_MEDIUM) + + endtask + +endclass: fuse_ctrl_rst_out_random_sequence + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_responder_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_responder_sequence.svh new file mode 100644 index 0000000..0a1e3cb --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_responder_sequence.svh @@ -0,0 +1,63 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class can be used to provide stimulus when an interface +// has been configured to run in a responder mode. It +// will never finish by default, always going back to the driver +// and driver BFM for the next transaction with which to respond. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_rst_out_responder_sequence + extends fuse_ctrl_rst_out_sequence_base ; + + `uvm_object_utils( fuse_ctrl_rst_out_responder_sequence ) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "fuse_ctrl_rst_out_responder_sequence"); + super.new(name); + endfunction + + task body(); + req=fuse_ctrl_rst_out_transaction::type_id::create("req"); + forever begin + start_item(req); + finish_item(req); + // pragma uvmf custom body begin + // UVMF_CHANGE_ME : Do something here with the resulting req item. The + // finish_item() call above will block until the req transaction is ready + // to be handled by the responder sequence. + // If this was an item that required a response, the expectation is + // that the response should be populated within this transaction now. + `uvm_info("SEQ",$sformatf("Processed txn: %s",req.convert2string()),UVM_HIGH) + // pragma uvmf custom body end + end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_sequence_base.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_sequence_base.svh new file mode 100644 index 0000000..e4c8255 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_sequence_base.svh @@ -0,0 +1,110 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the class used as the base class for all sequences +// for this interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_rst_out_sequence_base extends uvmf_sequence_base #( + .REQ(fuse_ctrl_rst_out_transaction ), + .RSP(fuse_ctrl_rst_out_transaction )); + + `uvm_object_utils( fuse_ctrl_rst_out_sequence_base ) + + // variables + typedef fuse_ctrl_rst_out_transaction fuse_ctrl_rst_out_transaction_req_t; + fuse_ctrl_rst_out_transaction_req_t req; + typedef fuse_ctrl_rst_out_transaction fuse_ctrl_rst_out_transaction_rsp_t; + fuse_ctrl_rst_out_transaction_rsp_t rsp; + + // Event for identifying when a response was received from the sequencer + event new_rsp; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // TASK : get_responses() + // This task recursively gets sequence item responses from the sequencer. + // + virtual task get_responses(); + fork + begin + // Block until new rsp available + get_response(rsp); + // New rsp received. Indicate to sequence using event. + ->new_rsp; + // Display the received response transaction + `uvm_info("SEQ", {"New response transaction:",rsp.convert2string()}, UVM_MEDIUM) + end + join_none + endtask + + // **************************************************************************** + // TASK : pre_body() + // This task is called automatically when start is called with call_pre_post set to 1 (default). + // By calling get_responses() within pre_body() any derived sequences are automatically + // processing response transactions. Only un-comment this call to get_responses() if you + // have configured the interface driver to utilize the response transaction path by setting + // the configuration variable "return_transaction_response" to 1. Otherwise it is possible + // to impact runtime performance and memory utilization. + // + virtual task pre_body(); + // pragma uvmf custom pre_body begin +// get_responses(); + // pragma uvmf custom pre_body end + endtask + + // **************************************************************************** + // TASK : body() + // This task is called automatically when start is called. This sequence sends + // a req sequence item to the sequencer identified as an argument in the call + // to start. + // + virtual task body(); + // pragma uvmf custom body begin + start_item(req); + finish_item(req); + // pragma uvmf custom body end + endtask + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name =""); + super.new( name ); + // pragma uvmf custom new begin + req = fuse_ctrl_rst_out_transaction_req_t::type_id::create("req"); + rsp = fuse_ctrl_rst_out_transaction_rsp_t::type_id::create("rsp"); + // pragma uvmf custom new end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_transaction.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_transaction.svh new file mode 100644 index 0000000..5573643 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_transaction.svh @@ -0,0 +1,196 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class defines the variables required for an fuse_ctrl_rst_out +// transaction. Class variables to be displayed in waveform transaction +// viewing are added to the transaction viewing stream in the add_to_wave +// function. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_rst_out_transaction extends uvmf_transaction_base; + + `uvm_object_utils( fuse_ctrl_rst_out_transaction ) + + pwrmgr_pkg::pwr_otp_rsp_t pwr_otp_o ; + + //Constraints for the transaction variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //******************************************************************* + //******************************************************************* + // Macros that define structs and associated functions are + // located in fuse_ctrl_rst_out_macros.svh + + //******************************************************************* + // Monitor macro used by fuse_ctrl_rst_out_monitor and fuse_ctrl_rst_out_monitor_bfm + // This struct is defined in fuse_ctrl_rst_out_macros.svh + `fuse_ctrl_rst_out_MONITOR_STRUCT + fuse_ctrl_rst_out_monitor_s fuse_ctrl_rst_out_monitor_struct; + //******************************************************************* + // FUNCTION: to_monitor_struct() + // This function packs transaction variables into a fuse_ctrl_rst_out_monitor_s + // structure. The function returns the handle to the fuse_ctrl_rst_out_monitor_struct. + // This function is defined in fuse_ctrl_rst_out_macros.svh + `fuse_ctrl_rst_out_TO_MONITOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_monitor_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_rst_out_macros.svh + `fuse_ctrl_rst_out_FROM_MONITOR_STRUCT_FUNCTION + + //******************************************************************* + // Initiator macro used by fuse_ctrl_rst_out_driver and fuse_ctrl_rst_out_driver_bfm + // to communicate initiator driven data to fuse_ctrl_rst_out_driver_bfm. + // This struct is defined in fuse_ctrl_rst_out_macros.svh + `fuse_ctrl_rst_out_INITIATOR_STRUCT + fuse_ctrl_rst_out_initiator_s fuse_ctrl_rst_out_initiator_struct; + //******************************************************************* + // FUNCTION: to_initiator_struct() + // This function packs transaction variables into a fuse_ctrl_rst_out_initiator_s + // structure. The function returns the handle to the fuse_ctrl_rst_out_initiator_struct. + // This function is defined in fuse_ctrl_rst_out_macros.svh + `fuse_ctrl_rst_out_TO_INITIATOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_initiator_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_rst_out_macros.svh + `fuse_ctrl_rst_out_FROM_INITIATOR_STRUCT_FUNCTION + + //******************************************************************* + // Responder macro used by fuse_ctrl_rst_out_driver and fuse_ctrl_rst_out_driver_bfm + // to communicate Responder driven data to fuse_ctrl_rst_out_driver_bfm. + // This struct is defined in fuse_ctrl_rst_out_macros.svh + `fuse_ctrl_rst_out_RESPONDER_STRUCT + fuse_ctrl_rst_out_responder_s fuse_ctrl_rst_out_responder_struct; + //******************************************************************* + // FUNCTION: to_responder_struct() + // This function packs transaction variables into a fuse_ctrl_rst_out_responder_s + // structure. The function returns the handle to the fuse_ctrl_rst_out_responder_struct. + // This function is defined in fuse_ctrl_rst_out_macros.svh + `fuse_ctrl_rst_out_TO_RESPONDER_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_responder_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_rst_out_macros.svh + `fuse_ctrl_rst_out_FROM_RESPONDER_STRUCT_FUNCTION + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + endfunction + + // **************************************************************************** + // FUNCTION: convert2string() + // This function converts all variables in this class to a single string for + // logfile reporting. + // + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + // UVMF_CHANGE_ME : Customize format if desired. + return $sformatf("pwr_otp_o:0x%x ",pwr_otp_o); + // pragma uvmf custom convert2string end + endfunction + + //******************************************************************* + // FUNCTION: do_print() + // This function is automatically called when the .print() function + // is called on this class. + // + virtual function void do_print(uvm_printer printer); + // pragma uvmf custom do_print begin + // UVMF_CHANGE_ME : Current contents of do_print allows for the use of UVM 1.1d, 1.2 or P1800.2. + // Update based on your own printing preference according to your preferred UVM version + $display(convert2string()); + // pragma uvmf custom do_print end + endfunction + + //******************************************************************* + // FUNCTION: do_compare() + // This function is automatically called when the .compare() function + // is called on this class. + // + virtual function bit do_compare (uvm_object rhs, uvm_comparer comparer); + fuse_ctrl_rst_out_transaction RHS; + if (!$cast(RHS,rhs)) return 0; + // pragma uvmf custom do_compare begin + // UVMF_CHANGE_ME : Eliminate comparison of variables not to be used for compare + return (super.do_compare(rhs,comparer) + &&(this.pwr_otp_o == RHS.pwr_otp_o) + ); + // pragma uvmf custom do_compare end + endfunction + + //******************************************************************* + // FUNCTION: do_copy() + // This function is automatically called when the .copy() function + // is called on this class. + // + virtual function void do_copy (uvm_object rhs); + fuse_ctrl_rst_out_transaction RHS; + assert($cast(RHS,rhs)); + // pragma uvmf custom do_copy begin + super.do_copy(rhs); + this.pwr_otp_o = RHS.pwr_otp_o; + // pragma uvmf custom do_copy end + endfunction + + // **************************************************************************** + // FUNCTION: add_to_wave() + // This function is used to display variables in this class in the waveform + // viewer. The start_time and end_time variables must be set before this + // function is called. If the start_time and end_time variables are not set + // the transaction will be hidden at 0ns on the waveform display. + // + virtual function void add_to_wave(int transaction_viewing_stream_h); + `ifdef QUESTA + if (transaction_view_h == 0) begin + transaction_view_h = $begin_transaction(transaction_viewing_stream_h,"fuse_ctrl_rst_out_transaction",start_time); + end + super.add_to_wave(transaction_view_h); + // pragma uvmf custom add_to_wave begin + // UVMF_CHANGE_ME : Color can be applied to transaction entries based on content, example below + // case() + // 1 : $add_color(transaction_view_h,"red"); + // default : $add_color(transaction_view_h,"grey"); + // endcase + // UVMF_CHANGE_ME : Eliminate transaction variables not wanted in transaction viewing in the waveform viewer + $add_attribute(transaction_view_h,pwr_otp_o,"pwr_otp_o"); + // pragma uvmf custom add_to_wave end + $end_transaction(transaction_view_h,end_time); + $free_transaction(transaction_view_h); + `endif // QUESTA + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_transaction_coverage.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_transaction_coverage.svh new file mode 100644 index 0000000..ef38834 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_transaction_coverage.svh @@ -0,0 +1,84 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class records fuse_ctrl_rst_out transaction information using +// a covergroup named fuse_ctrl_rst_out_transaction_cg. An instance of this +// coverage component is instantiated in the uvmf_parameterized_agent +// if the has_coverage flag is set. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_rst_out_transaction_coverage extends uvm_subscriber #(.T(fuse_ctrl_rst_out_transaction )); + + `uvm_component_utils( fuse_ctrl_rst_out_transaction_coverage ) + + T coverage_trans; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + covergroup fuse_ctrl_rst_out_transaction_cg; + // pragma uvmf custom covergroup begin + // UVMF_CHANGE_ME : Add coverage bins, crosses, exclusions, etc. according to coverage needs. + option.auto_bin_max=1024; + option.per_instance=1; + pwr_otp_o: coverpoint coverage_trans.pwr_otp_o; + // pragma uvmf custom covergroup end + endgroup + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new(string name="", uvm_component parent=null); + super.new(name,parent); + fuse_ctrl_rst_out_transaction_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that transaction variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + endfunction + + // **************************************************************************** + // FUNCTION : build_phase() + // This function is the standard UVM build_phase. + // + function void build_phase(uvm_phase phase); + fuse_ctrl_rst_out_transaction_cg.set_inst_name($sformatf("fuse_ctrl_rst_out_transaction_cg_%s",get_full_name())); + endfunction + + // **************************************************************************** + // FUNCTION: write (T t) + // This function is automatically executed when a transaction arrives on the + // analysis_export. It copies values from the variables in the transaction + // to local variables used to collect functional coverage. + // + virtual function void write (T t); + `uvm_info("COV","Received transaction",UVM_HIGH); + coverage_trans = t; + fuse_ctrl_rst_out_transaction_cg.sample(); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_typedefs.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_typedefs.svh new file mode 100644 index 0000000..f2a7bdb --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_typedefs.svh @@ -0,0 +1,34 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the host server when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_typedefs_hdl.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_typedefs_hdl.svh new file mode 100644 index 0000000..0d58518 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/src/fuse_ctrl_rst_out_typedefs_hdl.svh @@ -0,0 +1,35 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the emulator when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/yaml/fuse_ctrl_rst_out_interface.yaml b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/yaml/fuse_ctrl_rst_out_interface.yaml new file mode 100644 index 0000000..ca4764b --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_out_pkg/yaml/fuse_ctrl_rst_out_interface.yaml @@ -0,0 +1,33 @@ +uvmf: + interfaces: + fuse_ctrl_rst_out: + clock: clk_i + config_constraints: [] + config_vars: [] + existing_library_component: 'True' + gen_inbound_streaming_driver: 'False' + hdl_pkg_parameters: [] + hdl_typedefs: [] + hvl_pkg_parameters: [] + hvl_typedefs: [] + parameters: [] + ports: + - dir: input + name: pwr_otp_o + reset_value: '''bz' + width: '[''$bits(pwrmgr_pkg::pwr_otp_rsp_t)'']' + - dir: inout + name: otp_ext_voltage_h_io + reset_value: '''bz' + width: '1' + reset: rst_ni + reset_assertion_level: 'False' + transaction_constraints: [] + transaction_vars: + - comment: '' + iscompare: 'True' + isrand: 'False' + name: pwr_otp_o + type: pwrmgr_pkg::pwr_otp_rsp_t + unpacked_dimension: '' + use_dpi_link: 'False' diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/.project b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/.project new file mode 100644 index 0000000..ffd5f96 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/.project @@ -0,0 +1,30 @@ + + + fuse_ctrl_rst_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/.svproject b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/.svproject new file mode 100644 index 0000000..79beebd --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/Makefile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/Makefile new file mode 100644 index 0000000..4067417 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/Makefile @@ -0,0 +1,66 @@ +# fuse_ctrl_rst interface packages source +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +fuse_ctrl_rst_PKG = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_pkg/fuse_ctrl_rst_filelist_hvl.f + +fuse_ctrl_rst_PKG_HDL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_pkg/fuse_ctrl_rst_filelist_hdl.f + +fuse_ctrl_rst_PKG_XRTL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_pkg/fuse_ctrl_rst_filelist_xrtl.f + +COMP_fuse_ctrl_rst_PKG_TGT_0 = q_comp_fuse_ctrl_rst_pkg +COMP_fuse_ctrl_rst_PKG_TGT_1 = v_comp_fuse_ctrl_rst_pkg +COMP_fuse_ctrl_rst_PKG_TGT = $(COMP_fuse_ctrl_rst_PKG_TGT_$(USE_VELOCE)) + +comp_fuse_ctrl_rst_pkg: $(COMP_fuse_ctrl_rst_PKG_TGT) + +q_comp_fuse_ctrl_rst_pkg: + $(HDL_COMP_CMD) $(fuse_ctrl_rst_PKG_HDL) + $(HVL_COMP_CMD) $(fuse_ctrl_rst_PKG) + $(HDL_COMP_CMD) $(fuse_ctrl_rst_PKG_XRTL) + +v_comp_fuse_ctrl_rst_pkg: + $(HVL_COMP_CMD) $(fuse_ctrl_rst_PKG_HDL) + $(HVL_COMP_CMD) $(fuse_ctrl_rst_PKG) + $(VELANALYZE_CMD) $(fuse_ctrl_rst_PKG_HDL) + $(VELANALYZE_HVL_CMD) $(fuse_ctrl_rst_PKG) + $(HDL_COMP_CMD) $(fuse_ctrl_rst_PKG_XRTL) + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export fuse_ctrl_rst_IF_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_pkg/dpi + +C_FILE_COMPILE_LIST_fuse_ctrl_rst_pkg = \ + +O_FILE_COMPILE_LIST_fuse_ctrl_rst_pkg = $(notdir $(C_FILE_COMPILE_LIST_fuse_ctrl_rst_pkg:.c=.o)) + +GCC_COMP_ARGS_fuse_ctrl_rst_pkg += -I$(fuse_ctrl_rst_IF_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_fuse_ctrl_rst_pkg += $(fuse_ctrl_rst_IF_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_fuse_ctrl_rst_pkg += \ + \ + -o .so + +comp_fuse_ctrl_rst_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Interface C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_fuse_ctrl_rst_pkg) $(C_FILE_COMPILE_LIST_fuse_ctrl_rst_pkg) + @echo "--------------------------------" + @echo "Linking Interface C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_fuse_ctrl_rst_pkg) $(O_FILE_COMPILE_LIST_fuse_ctrl_rst_pkg) + @echo "--------------------------------" + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/compile.do b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/compile.do new file mode 100644 index 0000000..935ebc7 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/compile.do @@ -0,0 +1,14 @@ +# Tcl do file for compile of fuse_ctrl_rst interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_pkg/fuse_ctrl_rst_filelist_hdl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_pkg/fuse_ctrl_rst_filelist_hvl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_rst_pkg/fuse_ctrl_rst_filelist_xrtl.f \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/fuse_ctrl_rst.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/fuse_ctrl_rst.compile new file mode 100644 index 0000000..98756cb --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/fuse_ctrl_rst.compile @@ -0,0 +1,3 @@ +needs: + - fuse_ctrl_rst_hvl.compile + - fuse_ctrl_rst_hdl.compile diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/fuse_ctrl_rst_bfm.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/fuse_ctrl_rst_bfm.vinfo new file mode 100644 index 0000000..c41b1f1 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/fuse_ctrl_rst_bfm.vinfo @@ -0,0 +1,6 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use fuse_ctrl_rst_pkg_hdl.vinfo ++incdir+@vinfodir +src/fuse_ctrl_rst_if.sv +src/fuse_ctrl_rst_driver_bfm.sv +src/fuse_ctrl_rst_monitor_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/fuse_ctrl_rst_common.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/fuse_ctrl_rst_common.compile new file mode 100644 index 0000000..098d340 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/fuse_ctrl_rst_common.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +incdir: + - . + - ${uvm_path}/src +src: + - fuse_ctrl_rst_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/fuse_ctrl_rst_filelist_hdl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/fuse_ctrl_rst_filelist_hdl.f new file mode 100644 index 0000000..a5e629a --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/fuse_ctrl_rst_filelist_hdl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_rst_pkg/fuse_ctrl_rst_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/fuse_ctrl_rst_filelist_hvl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/fuse_ctrl_rst_filelist_hvl.f new file mode 100644 index 0000000..9bddd1e --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/fuse_ctrl_rst_filelist_hvl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_rst_pkg/fuse_ctrl_rst_pkg.sv \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/fuse_ctrl_rst_filelist_xrtl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/fuse_ctrl_rst_filelist_xrtl.f new file mode 100644 index 0000000..a68e857 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/fuse_ctrl_rst_filelist_xrtl.f @@ -0,0 +1,3 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_rst_pkg/src/fuse_ctrl_rst_if.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_rst_pkg/src/fuse_ctrl_rst_monitor_bfm.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_rst_pkg/src/fuse_ctrl_rst_driver_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/fuse_ctrl_rst_hdl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/fuse_ctrl_rst_hdl.compile new file mode 100644 index 0000000..5e99298 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/fuse_ctrl_rst_hdl.compile @@ -0,0 +1,9 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ./fuse_ctrl_rst_common.compile +incdir: + - . +src: + - src/fuse_ctrl_rst_if.sv + - src/fuse_ctrl_rst_monitor_bfm.sv + - src/fuse_ctrl_rst_driver_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/fuse_ctrl_rst_hvl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/fuse_ctrl_rst_hvl.compile new file mode 100644 index 0000000..69ab1ac --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/fuse_ctrl_rst_hvl.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ./fuse_ctrl_rst_common.compile +incdir: + - . +src: + - fuse_ctrl_rst_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/fuse_ctrl_rst_pkg.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/fuse_ctrl_rst_pkg.sv new file mode 100644 index 0000000..99c9b2b --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/fuse_ctrl_rst_pkg.sv @@ -0,0 +1,93 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - + +// - +// - +// - + +// - +// - +// - + +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_rst_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg_hdl::*; + import uvmf_base_pkg::*; + import fuse_ctrl_rst_pkg_hdl::*; + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + `include "src/fuse_ctrl_rst_macros.svh" + + export fuse_ctrl_rst_pkg_hdl::*; + + + + // Parameters defined as HVL parameters + + `include "src/fuse_ctrl_rst_typedefs.svh" + `include "src/fuse_ctrl_rst_transaction.svh" + + `include "src/fuse_ctrl_rst_configuration.svh" + `include "src/fuse_ctrl_rst_driver.svh" + `include "src/fuse_ctrl_rst_monitor.svh" + + `include "src/fuse_ctrl_rst_transaction_coverage.svh" + `include "src/fuse_ctrl_rst_sequence_base.svh" + `include "src/fuse_ctrl_rst_random_sequence.svh" + `include "src/fuse_ctrl_rst_poweron_sequence.svh" + + `include "src/fuse_ctrl_rst_responder_sequence.svh" + `include "src/fuse_ctrl_rst2reg_adapter.svh" + + `include "src/fuse_ctrl_rst_agent.svh" + + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new interface sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the interface package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/fuse_ctrl_rst_pkg.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/fuse_ctrl_rst_pkg.vinfo new file mode 100644 index 0000000..7efd3da --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/fuse_ctrl_rst_pkg.vinfo @@ -0,0 +1,4 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use fuse_ctrl_rst_pkg_hdl.vinfo ++incdir+@vinfodir +fuse_ctrl_rst_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/fuse_ctrl_rst_pkg_hdl.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/fuse_ctrl_rst_pkg_hdl.sv new file mode 100644 index 0000000..59c4ce0 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/fuse_ctrl_rst_pkg_hdl.sv @@ -0,0 +1,52 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that needs to be compiled and synthesized +// for running on Veloce. +// +// CONTAINS: +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_rst_pkg_hdl; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HDL parameters + + `include "src/fuse_ctrl_rst_typedefs_hdl.svh" + `include "src/fuse_ctrl_rst_macros.svh" + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/fuse_ctrl_rst_pkg_hdl.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/fuse_ctrl_rst_pkg_hdl.vinfo new file mode 100644 index 0000000..105e5a2 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/fuse_ctrl_rst_pkg_hdl.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +fuse_ctrl_rst_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/fuse_ctrl_rst_pkg_sve.F b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/fuse_ctrl_rst_pkg_sve.F new file mode 100644 index 0000000..2a76484 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/fuse_ctrl_rst_pkg_sve.F @@ -0,0 +1,10 @@ +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + ++incdir+. +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_rst_pkg/fuse_ctrl_rst_filelist_hdl.f +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_rst_pkg/fuse_ctrl_rst_filelist_hvl.f diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/src/fuse_ctrl_rst2reg_adapter.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/src/fuse_ctrl_rst2reg_adapter.svh new file mode 100644 index 0000000..e74aaf5 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/src/fuse_ctrl_rst2reg_adapter.svh @@ -0,0 +1,112 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the UVM register adapter for the fuse_ctrl_rst interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_rst2reg_adapter extends uvm_reg_adapter; + + `uvm_object_utils( fuse_ctrl_rst2reg_adapter ) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //-------------------------------------------------------------------- + // new + //-------------------------------------------------------------------- + function new (string name = "fuse_ctrl_rst2reg_adapter" ); + super.new(name); + // pragma uvmf custom new begin + // UVMF_CHANGE_ME : Configure the adapter regarding byte enables and provides response. + + // Does the protocol the Agent is modeling support byte enables? + // 0 = NO + // 1 = YES + supports_byte_enable = 0; + + // Does the Agent's Driver provide separate response sequence items? + // i.e. Does the driver call seq_item_port.put() + // and do the sequences call get_response()? + // 0 = NO + // 1 = YES + provides_responses = 0; + // pragma uvmf custom new end + + endfunction: new + + //-------------------------------------------------------------------- + // reg2bus + //-------------------------------------------------------------------- + virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw); + + fuse_ctrl_rst_transaction trans_h = fuse_ctrl_rst_transaction ::type_id::create("trans_h"); + + // pragma uvmf custom reg2bus begin + // UVMF_CHANGE_ME : Fill in the reg2bus adapter mapping registe fields to protocol fields. + + //Adapt the following for your sequence item type + // trans_h.op = (rw.kind == UVM_READ) ? WB_READ : WB_WRITE; + //Copy over address + // trans_h.addr = rw.addr; + //Copy over write data + // trans_h.data = rw.data; + + // pragma uvmf custom reg2bus end + + // Return the adapted transaction + return trans_h; + + endfunction: reg2bus + + //-------------------------------------------------------------------- + // bus2reg + //-------------------------------------------------------------------- + virtual function void bus2reg(uvm_sequence_item bus_item, + ref uvm_reg_bus_op rw); + fuse_ctrl_rst_transaction trans_h; + if (!$cast(trans_h, bus_item)) begin + `uvm_fatal("ADAPT","Provided bus_item is not of the correct type") + return; + end + // pragma uvmf custom bus2reg begin + // UVMF_CHANGE_ME : Fill in the bus2reg adapter mapping protocol fields to register fields. + //Adapt the following for your sequence item type + //Copy over instruction type + // rw.kind = (trans_h.op == WB_WRITE) ? UVM_WRITE : UVM_READ; + //Copy over address + // rw.addr = trans_h.addr; + //Copy over read data + // rw.data = trans_h.data; + //Check for errors on the bus and return UVM_NOT_OK if there is an error + // rw.status = UVM_IS_OK; + // pragma uvmf custom bus2reg end + + endfunction: bus2reg + +endclass : fuse_ctrl_rst2reg_adapter + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/src/fuse_ctrl_rst_agent.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/src/fuse_ctrl_rst_agent.svh new file mode 100644 index 0000000..3129024 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/src/fuse_ctrl_rst_agent.svh @@ -0,0 +1,67 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: Protocol specific agent class definition +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_rst_agent extends uvmf_parameterized_agent #( + .CONFIG_T(fuse_ctrl_rst_configuration ), + .DRIVER_T(fuse_ctrl_rst_driver ), + .MONITOR_T(fuse_ctrl_rst_monitor ), + .COVERAGE_T(fuse_ctrl_rst_transaction_coverage ), + .TRANS_T(fuse_ctrl_rst_transaction ) + ); + + `uvm_component_utils( fuse_ctrl_rst_agent ) + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** + // FUNCTION: build_phase + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + if (configuration.active_passive == ACTIVE) begin + // Place sequencer handle into configuration object + // so that it may be retrieved from configuration + // rather than using uvm_config_db + configuration.sequencer = this.sequencer; + end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/src/fuse_ctrl_rst_configuration.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/src/fuse_ctrl_rst_configuration.svh new file mode 100644 index 0000000..2b8c3b8 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/src/fuse_ctrl_rst_configuration.svh @@ -0,0 +1,193 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class contains all variables and functions used +// to configure the fuse_ctrl_rst agent and its bfm's. It gets the +// bfm's from the uvm_config_db for use by the agent. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_rst_configuration extends uvmf_parameterized_agent_configuration_base #( + .DRIVER_BFM_BIND_T(virtual fuse_ctrl_rst_driver_bfm ), + .MONITOR_BFM_BIND_T( virtual fuse_ctrl_rst_monitor_bfm )); + + `uvm_object_utils( fuse_ctrl_rst_configuration ) + + + // Sequencer handle populated by agent + uvm_sequencer #(fuse_ctrl_rst_transaction ) sequencer; + + //Constraints for the configuration variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + covergroup fuse_ctrl_rst_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + // pragma uvmf custom covergroup end + endgroup + + //******************************************************************* + //******************************************************************* + // Structure used to pass configuration variables to monitor and driver BFM's. + // Use to_struct function to pack variables into structure. + // Use from_struct function to unpack variables from structure. + // This structure is defined in fuse_ctrl_rst_macros.svh + `fuse_ctrl_rst_CONFIGURATION_STRUCT + fuse_ctrl_rst_configuration_s fuse_ctrl_rst_configuration_struct; + //******************************************************************* + // FUNCTION: to_struct() + // This function packs variables into a fuse_ctrl_rst_configuration_s + // structure. The function returns the handle to the fuse_ctrl_rst_configuration_struct. + // This function is defined in fuse_ctrl_rst_macros.svh + `fuse_ctrl_rst_CONFIGURATION_TO_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_struct() + // This function unpacks the struct provided as an argument into + // variables of this class. + // This function is defined in fuse_ctrl_rst_macros.svh + `fuse_ctrl_rst_CONFIGURATION_FROM_STRUCT_FUNCTION + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + // Construct the covergroup for this configuration class + fuse_ctrl_rst_configuration_cg = new; + endfunction + + // **************************************************************************** + // FUNCTION: post_randomize() + // This function is automatically called after the randomize() function + // is executed. + // + function void post_randomize(); + super.post_randomize(); + fuse_ctrl_rst_configuration_cg.sample(); + endfunction + + // **************************************************************************** + // FUNCTION: initialize + // This function causes the configuration to retrieve + // its virtual interface handle from the uvm_config_db. + // This function also makes itself available to its + // agent through the uvm_config_db. + // + // ARGUMENTS: + // uvmf_active_passive_t activity: + // This argument identifies the simulation level + // as either BLOCK, CHIP, SIMULATION, etc. + // + // AGENT_PATH: + // This argument identifies the path to this + // configurations agent. This configuration + // makes itself available to the agent specified + // by agent_path by placing itself into the + // uvm_config_db. + // + // INTERFACE_NAME: + // This argument identifies the string name of + // this configurations BFM's. This string + // name is used to retrieve the driver and + // monitor BFM from the uvm_config_db. + // + virtual function void initialize(uvmf_active_passive_t activity, + string agent_path, + string interface_name); + + super.initialize( activity, agent_path, interface_name); + // The covergroup is given the same name as the interface + fuse_ctrl_rst_configuration_cg.set_inst_name(interface_name); + + // This configuration places itself into the uvm_config_db for the agent, identified by the agent_path variable, to retrieve. + uvm_config_db #( fuse_ctrl_rst_configuration + )::set( null ,agent_path,UVMF_AGENT_CONFIG, this ); + + // This configuration also places itself in the config db using the same identifier used by the interface. This allows users to access + // configuration variables and the interface through the bfm api class rather than directly accessing the BFM. This is useful for + // accessingthe BFM when using Veloce + uvm_config_db #( fuse_ctrl_rst_configuration + )::set( null ,UVMF_CONFIGURATIONS, interface_name, this ); + + fuse_ctrl_rst_configuration_cg.set_inst_name($sformatf("fuse_ctrl_rst_configuration_cg_%s",get_full_name())); + +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. + `uvm_info("CFG", + $psprintf("The agent at '%s' is using interface named %s has the following parameters: ", agent_path, interface_name, ), + UVM_DEBUG) + + // pragma uvmf custom initialize begin + // This controls whether or not the agent returns a transaction handle in the driver when calling + // item_done() back into the sequencer or not. If set to 1, a transaction is sent back which means + // the sequence on the other end must use the get_response() part of the driver/sequence API. If + // this doesn't occur, there will eventually be response_queue overflow errors during the test. + return_transaction_response = 1'b0; + + // pragma uvmf custom initialize end + + endfunction + + // **************************************************************************** + // TASK: wait_for_reset + // *[Required]* Blocks until reset is released. The wait_for_reset operation is performed + // by a task in the monitor bfm. + virtual task wait_for_reset(); + monitor_bfm.wait_for_reset(); + endtask + + // **************************************************************************** + // TASK: wait_for_num_clocks + // *[Required]* Blocks until specified number of clocks have elapsed. The wait_for_num_clocks + // operation is performed by a task in the monitor bfm. + virtual task wait_for_num_clocks(int clocks); + monitor_bfm.wait_for_num_clocks(clocks); + endtask + + // **************************************************************************** + // FUNCTION : convert2string() + // This function is used to convert variables in this class into a string for log messaging. + // + virtual function string convert2string (); + // pragma uvmf custom convert2string begin + return $sformatf(""); + // pragma uvmf custom convert2string end + endfunction + + // **************************************************************************** + // FUNCTION: get_sequencer + function uvm_sequencer #(fuse_ctrl_rst_transaction) get_sequencer(); + return sequencer; + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/src/fuse_ctrl_rst_driver.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/src/fuse_ctrl_rst_driver.svh new file mode 100644 index 0000000..c0c6921 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/src/fuse_ctrl_rst_driver.svh @@ -0,0 +1,105 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class passes transactions between the sequencer +// and the BFM driver interface. It accesses the driver BFM +// through the bfm handle. This driver +// passes transactions to the driver BFM through the access +// task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_rst_driver extends uvmf_driver_base #( + .CONFIG_T(fuse_ctrl_rst_configuration ), + .BFM_BIND_T(virtual fuse_ctrl_rst_driver_bfm ), + .REQ(fuse_ctrl_rst_transaction ), + .RSP(fuse_ctrl_rst_transaction )); + + `uvm_component_utils( fuse_ctrl_rst_driver ) +//******************************************************************* +// Macros that define structs located in fuse_ctrl_rst_macros.svh +//******************************************************************* +// Initiator macro used by fuse_ctrl_rst_driver and fuse_ctrl_rst_driver_bfm +// to communicate initiator driven data to fuse_ctrl_rst_driver_bfm. +`fuse_ctrl_rst_INITIATOR_STRUCT + fuse_ctrl_rst_initiator_s fuse_ctrl_rst_initiator_struct; +//******************************************************************* +// Responder macro used by fuse_ctrl_rst_driver and fuse_ctrl_rst_driver_bfm +// to communicate Responder driven data to fuse_ctrl_rst_driver_bfm. +`fuse_ctrl_rst_RESPONDER_STRUCT + fuse_ctrl_rst_responder_s fuse_ctrl_rst_responder_struct; + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent=null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the driver BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// driver BFM. This allows the driver BFM to call tasks and function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// **************************************************************************** +// This task is called by the run_phase in uvmf_driver_base. + virtual task access( inout REQ txn ); +// pragma uvmf custom access begin + if (configuration.initiator_responder==RESPONDER) begin + // Complete current transfer and wait for next transfer + bfm.respond_and_wait_for_next_transfer( + fuse_ctrl_rst_initiator_struct, + txn.to_responder_struct() + ); + // Unpack information about initiated transfer received by this responder + txn.from_initiator_struct(fuse_ctrl_rst_initiator_struct); + end else begin + // Initiate a transfer and get response + bfm.initiate_and_get_response( + txn.to_initiator_struct(), + fuse_ctrl_rst_responder_struct + ); + // Unpack transfer response information received by this initiator + txn.from_responder_struct(fuse_ctrl_rst_responder_struct); + end +// pragma uvmf custom access end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/src/fuse_ctrl_rst_driver_bfm.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/src/fuse_ctrl_rst_driver_bfm.sv new file mode 100644 index 0000000..d3616ee --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/src/fuse_ctrl_rst_driver_bfm.sv @@ -0,0 +1,311 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This interface performs the fuse_ctrl_rst signal driving. It is +// accessed by the uvm fuse_ctrl_rst driver through a virtual interface +// handle in the fuse_ctrl_rst configuration. It drives the singals passed +// in through the port connection named bus of type fuse_ctrl_rst_if. +// +// Input signals from the fuse_ctrl_rst_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// This bfm drives signals with a _o suffix. These signals +// are driven onto signals within fuse_ctrl_rst_if based on INITIATOR/RESPONDER and/or +// ARBITRATION/GRANT status. +// +// The output signal connections are as follows: +// signal_o -> bus.signal +// +// +// Interface functions and tasks used by UVM components: +// +// configure: +// This function gets configuration attributes from the +// UVM driver to set any required BFM configuration +// variables such as 'initiator_responder'. +// +// initiate_and_get_response: +// This task is used to perform signaling activity for initiating +// a protocol transfer. The task initiates the transfer, using +// input data from the initiator struct. Then the task captures +// response data, placing the data into the response struct. +// The response struct is returned to the driver class. +// +// respond_and_wait_for_next_transfer: +// This task is used to complete a current transfer as a responder +// and then wait for the initiator to start the next transfer. +// The task uses data in the responder struct to drive protocol +// signals to complete the transfer. The task then waits for +// the next transfer. Once the next transfer begins, data from +// the initiator is placed into the initiator struct and sent +// to the responder sequence for processing to determine +// what data to respond with. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`default_nettype none + +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_rst_pkg_hdl::*; +`include "src/fuse_ctrl_rst_macros.svh" + +interface fuse_ctrl_rst_driver_bfm + (fuse_ctrl_rst_if bus); + // The following pragma and additional ones in-lined further below are for running this BFM on Veloce + // pragma attribute fuse_ctrl_rst_driver_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: ", ), + UVM_DEBUG) +end +`endif + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + tri clk_i_i; + tri rst_ni_i; + + // Signal list (all signals are capable of being inputs and outputs for the sake + // of supporting both INITIATOR and RESPONDER mode operation. Expectation is that + // directionality in the config file was from the point-of-view of the INITIATOR + + // INITIATOR mode input signals + + // INITIATOR mode output signals + tri rst_ni_i; + reg rst_ni_o = 'bz; + tri pwr_otp_i_i; + reg pwr_otp_i_o = 'bz; + + // Bi-directional signals + + + assign clk_i_i = bus.clk_i; + assign rst_ni_i = bus.rst_ni; + + // These are signals marked as 'input' by the config file, but the signals will be + // driven by this BFM if put into RESPONDER mode (flipping all signal directions around) + + + // These are signals marked as 'output' by the config file, but the outputs will + // not be driven by this BFM unless placed in INITIATOR mode. + assign bus.rst_ni = (initiator_responder == INITIATOR) ? rst_ni_o : 'bz; + assign rst_ni_i = bus.rst_ni; + assign bus.pwr_otp_i = (initiator_responder == INITIATOR) ? pwr_otp_i_o : 'bz; + assign pwr_otp_i_i = bus.pwr_otp_i; + + // Proxy handle to UVM driver + fuse_ctrl_rst_pkg::fuse_ctrl_rst_driver proxy; + // pragma tbx oneway proxy.my_function_name_in_uvm_driver + + // **************************************************************************** + // **************************************************************************** + // Macros that define structs located in fuse_ctrl_rst_macros.svh + // **************************************************************************** + // Struct for passing configuration data from fuse_ctrl_rst_driver to this BFM + // **************************************************************************** + `fuse_ctrl_rst_CONFIGURATION_STRUCT + // **************************************************************************** + // Structs for INITIATOR and RESPONDER data flow + //******************************************************************* + // Initiator macro used by fuse_ctrl_rst_driver and fuse_ctrl_rst_driver_bfm + // to communicate initiator driven data to fuse_ctrl_rst_driver_bfm. + `fuse_ctrl_rst_INITIATOR_STRUCT + fuse_ctrl_rst_initiator_s initiator_struct; + // Responder macro used by fuse_ctrl_rst_driver and fuse_ctrl_rst_driver_bfm + // to communicate Responder driven data to fuse_ctrl_rst_driver_bfm. + `fuse_ctrl_rst_RESPONDER_STRUCT + fuse_ctrl_rst_responder_s responder_struct; + + // **************************************************************************** +// pragma uvmf custom reset_condition_and_response begin + // Always block used to return signals to reset value upon assertion of reset + always @( negedge rst_ni_i ) + begin + // RESPONDER mode output signals + // INITIATOR mode output signals + rst_ni_o <= 'bz; + pwr_otp_i_o <= 'bz; + // Bi-directional signals + + end +// pragma uvmf custom reset_condition_and_response end + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the driver BFM. It is called by the driver within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the driver BFM needs to be aware of the new configuration + // variables. + // + + function void configure(fuse_ctrl_rst_configuration_s fuse_ctrl_rst_configuration_arg); // pragma tbx xtf + initiator_responder = fuse_ctrl_rst_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + +// pragma uvmf custom initiate_and_get_response begin +// **************************************************************************** +// UVMF_CHANGE_ME +// This task is used by an initator. The task first initiates a transfer then +// waits for the responder to complete the transfer. + task initiate_and_get_response( + // This argument passes transaction variables used by an initiator + // to perform the initial part of a protocol transfer. The values + // come from a sequence item created in a sequence. + input fuse_ctrl_rst_initiator_s fuse_ctrl_rst_initiator_struct, + // This argument is used to send data received from the responder + // back to the sequence item. The sequence item is returned to the sequence. + output fuse_ctrl_rst_responder_s fuse_ctrl_rst_responder_struct + );// pragma tbx xtf + // + // Members within the fuse_ctrl_rst_initiator_struct: + // bit assert_rst ; + // bit assert_otp_init ; + // Members within the fuse_ctrl_rst_responder_struct: + // bit assert_rst ;pwr_otp_init + // bit assert_otp_init ; + initiator_struct = fuse_ctrl_rst_initiator_struct; + // + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clk_i_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available initiator input and inout signals listed. + // Initiator input signals + // Initiator inout signals + // How to assign a signal from an initiator struct member named xyz. + // All available initiator output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Initiator output signals + // rst_ni_o <= fuse_ctrl_rst_initiator_struct.xyz; // + // pwr_otp_i_o <= fuse_ctrl_rst_initiator_struct.xyz; // [$bits(pwrmgr_pkg::pwr_otp_req_t)-1:0] + // Initiator inout signals + // Initiate a transfer using the data received. + @(posedge clk_i_i); + @(posedge clk_i_i); + + if (initiator_struct.assert_rst) + rst_ni_o <= 1'b0; + if (intitiator_struct.assert_otp_init) + pwr_otp_i_o <= 1'b1; + // Wait for the responder to complete the transfer then place the responder data into + // fuse_ctrl_rst_responder_struct. + @(posedge clk_i_i); + @(posedge clk_i_i); + + if (!initiator_struct.assert_rst) + rst_ni_o <= 1'b1; + if (!inititator_struct.assert_otp_init) + pwr_otp_i_o <= 1'b0; + + fuse_ctrl_rst_responder_struct.assert_rst = !rst_ni_i; + fuse_ctrl_rst_responder_struct.assert_otp_init = pwr_otp_i_i; + responder_struct = fuse_ctrl_rst_responder_struct; + endtask +// pragma uvmf custom initiate_and_get_response end + +// pragma uvmf custom respond_and_wait_for_next_transfer begin +// **************************************************************************** +// The first_transfer variable is used to prevent completing a transfer in the +// first call to this task. For the first call to this task, there is not +// current transfer to complete. +bit first_transfer=1; + +// UVMF_CHANGE_ME +// This task is used by a responder. The task first completes the current +// transfer in progress then waits for the initiator to start the next transfer. + task respond_and_wait_for_next_transfer( + // This argument is used to send data received from the initiator + // back to the sequence item. The sequence determines how to respond. + output fuse_ctrl_rst_initiator_s fuse_ctrl_rst_initiator_struct, + // This argument passes transaction variables used by a responder + // to complete a protocol transfer. The values come from a sequence item. + input fuse_ctrl_rst_responder_s fuse_ctrl_rst_responder_struct + );// pragma tbx xtf + // Variables within the fuse_ctrl_rst_initiator_struct: + // bit assert_rst ; + // bit assert_otp_init ; + // Variables within the fuse_ctrl_rst_responder_struct: + // bit assert_rst ; + // bit assert_otp_init ; + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clk_i_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available responder input and inout signals listed. + // Responder input signals + // fuse_ctrl_rst_responder_struct.xyz = rst_ni_i; // + // fuse_ctrl_rst_responder_struct.xyz = pwr_otp_i_i; // [$bits(pwrmgr_pkg::pwr_otp_req_t)-1:0] + // Responder inout signals + // How to assign a signal, named xyz, from an initiator struct member. + // All available responder output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Responder output signals + // Responder inout signals + + @(posedge clk_i_i); + if (!first_transfer) begin + // Perform transfer response here. + // Reply using data recieved in the fuse_ctrl_rst_responder_struct. + @(posedge clk_i_i); + // Reply using data recieved in the transaction handle. + @(posedge clk_i_i); + end + // Wait for next transfer then gather info from intiator about the transfer. + // Place the data into the fuse_ctrl_rst_initiator_struct. + @(posedge clk_i_i); + @(posedge clk_i_i); + first_transfer = 0; + endtask +// pragma uvmf custom respond_and_wait_for_next_transfer end + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/src/fuse_ctrl_rst_if.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/src/fuse_ctrl_rst_if.sv new file mode 100644 index 0000000..45947f7 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/src/fuse_ctrl_rst_if.sv @@ -0,0 +1,78 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface contains the fuse_ctrl_rst interface signals. +// It is instantiated once per fuse_ctrl_rst bus. Bus Functional Models, +// BFM's named fuse_ctrl_rst_driver_bfm, are used to drive signals on the bus. +// BFM's named fuse_ctrl_rst_monitor_bfm are used to monitor signals on the +// bus. This interface signal bundle is passed in the port list of +// the BFM in order to give the BFM access to the signals in this +// interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// This template can be used to connect a DUT to these signals +// +// .dut_signal_port(fuse_ctrl_rst_bus.rst_ni), // Agent output + +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_rst_pkg_hdl::*; + +interface fuse_ctrl_rst_if + + ( + input tri clk_i, + input tri rst_ni, + inout tri rst_ni + ); + +modport monitor_port + ( + input clk_i, + input rst_ni, + input rst_ni + ); + +modport initiator_port + ( + input clk_i, + input rst_ni, + output rst_ni + ); + +modport responder_port + ( + input clk_i, + input rst_ni, + input rst_ni + ); + + +// pragma uvmf custom interface_item_additional begin +// pragma uvmf custom interface_item_additional end + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/src/fuse_ctrl_rst_infact_coverage_strategy.csv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/src/fuse_ctrl_rst_infact_coverage_strategy.csv new file mode 100644 index 0000000..1c218e1 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/src/fuse_ctrl_rst_infact_coverage_strategy.csv @@ -0,0 +1,6 @@ +Global +auto_bin_max, 64 + +Name,Type,Include +rand_fields,coverpoint,=rand *.** + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/src/fuse_ctrl_rst_macros.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/src/fuse_ctrl_rst_macros.svh new file mode 100644 index 0000000..7af5376 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/src/fuse_ctrl_rst_macros.svh @@ -0,0 +1,135 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains macros used with the fuse_ctrl_rst package. +// These macros include packed struct definitions. These structs are +// used to pass data between classes, hvl, and BFM's, hdl. Use of +// structs are more efficient and simpler to modify. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_struct +// and from_struct methods defined in the macros below that are used in +// the fuse_ctrl_rst_configuration class. +// + `define fuse_ctrl_rst_CONFIGURATION_STRUCT \ +typedef struct packed { \ + uvmf_active_passive_t active_passive; \ + uvmf_initiator_responder_t initiator_responder; \ + } fuse_ctrl_rst_configuration_s; + + `define fuse_ctrl_rst_CONFIGURATION_TO_STRUCT_FUNCTION \ + virtual function fuse_ctrl_rst_configuration_s to_struct();\ + fuse_ctrl_rst_configuration_struct = \ + {\ + this.active_passive,\ + this.initiator_responder\ + };\ + return ( fuse_ctrl_rst_configuration_struct );\ + endfunction + + `define fuse_ctrl_rst_CONFIGURATION_FROM_STRUCT_FUNCTION \ + virtual function void from_struct(fuse_ctrl_rst_configuration_s fuse_ctrl_rst_configuration_struct);\ + {\ + this.active_passive,\ + this.initiator_responder \ + } = fuse_ctrl_rst_configuration_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_monitor_struct +// and from_monitor_struct methods of the fuse_ctrl_rst_transaction class. +// + `define fuse_ctrl_rst_MONITOR_STRUCT typedef struct packed { \ + bit assert_rst ; \ + } fuse_ctrl_rst_monitor_s; + + `define fuse_ctrl_rst_TO_MONITOR_STRUCT_FUNCTION \ + virtual function fuse_ctrl_rst_monitor_s to_monitor_struct();\ + fuse_ctrl_rst_monitor_struct = \ + { \ + this.assert_rst \ + };\ + return ( fuse_ctrl_rst_monitor_struct);\ + endfunction\ + + `define fuse_ctrl_rst_FROM_MONITOR_STRUCT_FUNCTION \ + virtual function void from_monitor_struct(fuse_ctrl_rst_monitor_s fuse_ctrl_rst_monitor_struct);\ + {\ + this.assert_rst \ + } = fuse_ctrl_rst_monitor_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_initiator_struct +// and from_initiator_struct methods of the fuse_ctrl_rst_transaction class. +// Also update the comments in the driver BFM. +// + `define fuse_ctrl_rst_INITIATOR_STRUCT typedef struct packed { \ + bit assert_rst ; \ + } fuse_ctrl_rst_initiator_s; + + `define fuse_ctrl_rst_TO_INITIATOR_STRUCT_FUNCTION \ + virtual function fuse_ctrl_rst_initiator_s to_initiator_struct();\ + fuse_ctrl_rst_initiator_struct = \ + {\ + this.assert_rst \ + };\ + return ( fuse_ctrl_rst_initiator_struct);\ + endfunction + + `define fuse_ctrl_rst_FROM_INITIATOR_STRUCT_FUNCTION \ + virtual function void from_initiator_struct(fuse_ctrl_rst_initiator_s fuse_ctrl_rst_initiator_struct);\ + {\ + this.assert_rst \ + } = fuse_ctrl_rst_initiator_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_responder_struct +// and from_responder_struct methods of the fuse_ctrl_rst_transaction class. +// Also update the comments in the driver BFM. +// + `define fuse_ctrl_rst_RESPONDER_STRUCT typedef struct packed { \ + bit assert_rst ; \ + } fuse_ctrl_rst_responder_s; + + `define fuse_ctrl_rst_TO_RESPONDER_STRUCT_FUNCTION \ + virtual function fuse_ctrl_rst_responder_s to_responder_struct();\ + fuse_ctrl_rst_responder_struct = \ + {\ + this.assert_rst \ + };\ + return ( fuse_ctrl_rst_responder_struct);\ + endfunction + + `define fuse_ctrl_rst_FROM_RESPONDER_STRUCT_FUNCTION \ + virtual function void from_responder_struct(fuse_ctrl_rst_responder_s fuse_ctrl_rst_responder_struct);\ + {\ + this.assert_rst \ + } = fuse_ctrl_rst_responder_struct;\ + endfunction +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/src/fuse_ctrl_rst_monitor.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/src/fuse_ctrl_rst_monitor.svh new file mode 100644 index 0000000..6e829b3 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/src/fuse_ctrl_rst_monitor.svh @@ -0,0 +1,101 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class receives fuse_ctrl_rst transactions observed by the +// fuse_ctrl_rst monitor BFM and broadcasts them through the analysis port +// on the agent. It accesses the monitor BFM through the monitor +// task. This UVM component captures transactions +// for viewing in the waveform viewer if the +// enable_transaction_viewing flag is set in the configuration. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_rst_monitor extends uvmf_monitor_base #( + .CONFIG_T(fuse_ctrl_rst_configuration ), + .BFM_BIND_T(virtual fuse_ctrl_rst_monitor_bfm ), + .TRANS_T(fuse_ctrl_rst_transaction )); + + `uvm_component_utils( fuse_ctrl_rst_monitor ) + +// Structure used to pass data from monitor BFM to monitor class in agent. +// Use to_monitor_struct function to pack transaction variables into structure. +// Use from_monitor_struct function to unpack transaction variables from structure. +`fuse_ctrl_rst_MONITOR_STRUCT + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the monitor BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// monitor BFM. This allows the monitor BFM to call the notify_transaction +// function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// *************************************************************************** + virtual task run_phase(uvm_phase phase); + // Start monitor BFM thread and don't call super.run() in order to + // override the default monitor proxy 'pull' behavior with the more + // emulation-friendly BFM 'push' approach using the notify_transaction + // function below + bfm.start_monitoring(); + endtask + +// ************************************************************************** + +// This function is called by the monitor BFM. It receives data observed by the +// monitor BFM. Data is passed using the fuse_ctrl_rst_monitor_struct. + virtual function void notify_transaction(input fuse_ctrl_rst_monitor_s fuse_ctrl_rst_monitor_struct); + + + trans = new("trans"); + trans.from_monitor_struct(fuse_ctrl_rst_monitor_struct); + trans.start_time = time_stamp; + trans.end_time = $time; + time_stamp = trans.end_time; + + analyze(trans); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/src/fuse_ctrl_rst_monitor_bfm.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/src/fuse_ctrl_rst_monitor_bfm.sv new file mode 100644 index 0000000..43887db --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/src/fuse_ctrl_rst_monitor_bfm.sv @@ -0,0 +1,196 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface performs the fuse_ctrl_rst signal monitoring. +// It is accessed by the uvm fuse_ctrl_rst monitor through a virtual +// interface handle in the fuse_ctrl_rst configuration. It monitors the +// signals passed in through the port connection named bus of +// type fuse_ctrl_rst_if. +// +// Input signals from the fuse_ctrl_rst_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// Interface functions and tasks used by UVM components: +// monitor(inout TRANS_T txn); +// This task receives the transaction, txn, from the +// UVM monitor and then populates variables in txn +// from values observed on bus activity. This task +// blocks until an operation on the fuse_ctrl_rst bus is complete. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_rst_pkg_hdl::*; +`include "src/fuse_ctrl_rst_macros.svh" + + +interface fuse_ctrl_rst_monitor_bfm + ( fuse_ctrl_rst_if bus ); + // The pragma below and additional ones in-lined further down are for running this BFM on Veloce + // pragma attribute fuse_ctrl_rst_monitor_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: ", ), + UVM_DEBUG) +end +`endif + + + // Structure used to pass transaction data from monitor BFM to monitor class in agent. +`fuse_ctrl_rst_MONITOR_STRUCT + fuse_ctrl_rst_monitor_s fuse_ctrl_rst_monitor_struct; + + // Structure used to pass configuration data from monitor class to monitor BFM. + `fuse_ctrl_rst_CONFIGURATION_STRUCT + + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + tri clk_i_i; + tri rst_ni_i; + tri pwr_otp_i_i; + assign clk_i_i = bus.clk_i; + assign rst_ni_i = bus.rst_ni; + assign pwr_otp_i_i = bus.pwr_otp_i; + // Proxy handle to UVM monitor + fuse_ctrl_rst_pkg::fuse_ctrl_rst_monitor proxy; + // pragma tbx oneway proxy.notify_transaction + + // pragma uvmf custom interface_item_additional begin + reg pwr_otp_i_o = 'b0; + reg rst_ni_o = 'b0; + + function bit any_signal_changed(); + return |(rst_ni_i ^ rst_ni_o) || + |(pwr_otp_i_i ^ pwr_otp_i_o); + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + task wait_for_reset();// pragma tbx xtf + @(posedge clk_i_i) ; + do_wait_for_reset(); + endtask + + // **************************************************************************** + task do_wait_for_reset(); + // pragma uvmf custom reset_condition begin + wait ( rst_ni_i === 1 ) ; + @(posedge clk_i_i) ; + // pragma uvmf custom reset_condition end + endtask + + //****************************************************************** + + task wait_for_num_clocks(input int unsigned count); // pragma tbx xtf + @(posedge clk_i_i); + + repeat (count-1) @(posedge clk_i_i); + endtask + + //****************************************************************** + event go; + function void start_monitoring();// pragma tbx xtf + -> go; + endfunction + + // **************************************************************************** + initial begin + @go; + forever begin + @(posedge clk_i_i); + do_monitor( fuse_ctrl_rst_monitor_struct ); + + + proxy.notify_transaction( fuse_ctrl_rst_monitor_struct ); + + end + end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the monitor BFM. It is called by the monitor within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the monitor BFM needs to be aware of the new configuration + // variables. + // + function void configure(fuse_ctrl_rst_configuration_s fuse_ctrl_rst_configuration_arg); // pragma tbx xtf + initiator_responder = fuse_ctrl_rst_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + + + // **************************************************************************** + + task do_monitor(output fuse_ctrl_rst_monitor_s fuse_ctrl_rst_monitor_struct); + // + // Available struct members: + // // fuse_ctrl_rst_monitor_struct.assert_rst + // // + // Reference code; + // How to wait for signal value + // while (control_signal === 1'b1) @(posedge clk_i_i); + // + // How to assign a struct member, named xyz, from a signal. + // All available input signals listed. + // fuse_ctrl_rst_monitor_struct.xyz = rst_ni_i; // + // pragma uvmf custom do_monitor begin + // UVMF_CHANGE_ME : Implement protocol monitoring. The commented reference code + // below are examples of how to capture signal values and assign them to + // structure members. All available input signals are listed. The 'while' + // code example shows how to wait for a synchronous flow control signal. This + // task should return when a complete transfer has been observed. Once this task is + // exited with captured values, it is then called again to wait for and observe + // the next transfer. One clock cycle is consumed between calls to do_monitor. + while (!any_signal_changed()) @(posedge clk_i_i); + + rst_ni_o <= rst_ni_i; + pwr_otp_i_o <= pwr_otp_i_i; + + fuse_ctrl_rst_monitor_struct.assert_rst = !rst_ni_i; + fuse_ctrl_rst_monitor_struct.assert_otp_init = pwr_otp_i_o; + // pragma uvmf custom do_monitor end + endtask + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/src/fuse_ctrl_rst_poweron_sequence.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/src/fuse_ctrl_rst_poweron_sequence.sv new file mode 100644 index 0000000..923771e --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/src/fuse_ctrl_rst_poweron_sequence.sv @@ -0,0 +1,82 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This sequences randomizes the fuse_ctrl_rst transaction and sends it +// to the UVM driver. +// +// This sequence constructs and randomizes a fuse_ctrl_rst_transaction. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_rst_poweron_sequence extends duse_ctrl_rst_sequence_base; + + `uvm_object_utils( fuse_ctrl_rst_random_sequence ) + + function new(string name = ""); + super.new(name); + endfunction: new + + // **************************************************************************** + // TASK : body() + // This task is automatically executed when this sequence is started using the + // start(sequencerHandle) task. + // + task body(); + + // Initiate first transaction with rst_ni = 0 (asserted), pwr_otp_i = 0 (deasserted) + req = fuse_ctrl_rst_transaction::type_id:: create("rst_req"); + start_item(req); + // Randomize the transaction + if (!req.randomize()) `uvm_fatal("FUSE_CTRL_RST_POWERON", "fuse_ctrl_rst_poweron_sequence::body()-fuse_ctrl_rst_transaction randomization failed") + `uvm_info("FUSE_CTRL_RST_POWERON", "Asserting reset", UVM_MEDIUM) + req.assert_rst = '1b0; + req.assert_otp_init = 1'b0; + finish_item(req); + `uvm_info("FUSE_CTRL_RST_POWERON", {"Response:", req.convert2string()}, UVM_MEDIUM) + + // Deassert rst_ni, pwr_otp_i = 0 (deasserted) + req = fuse_ctrl_rst_transaction::type_id:: create("rst_release_req"); + start_item(req); + // Randomize the transaction + if (!req.randomize()) `uvm_fatal("FUSE_CTRL_RST_POWERON", "fuse_ctrl_rst_poweron_sequence::body()-fuse_ctrl_rst_transaction randomization failed") + `uvm_info("FUSE_CTRL_RST_POWERON", "Deasserting reset, reset phase done", UVM_MEDIUM) + req.assert_rst = '1b1; + req.assert_otp_init = 1'b0; + finish_item(req); + `uvm_info("FUSE_CTRL_RST_POWERON", {"Response:", req.convert2string()}, UVM_MEDIUM) + + // Assert pwr_otp_i = 1 + req = fuse_ctrl_rst_transaction::type_id:: create("otp_init_req"); + start_item(req); + // Randomize the transaction + if (!req.randomize()) `uvm_fatal("FUSE_CTRL_RST_POWERON", "fuse_ctrl_rst_poweron_sequence::body()-fuse_ctrl_rst_transaction randomization failed") + `uvm_info("FUSE_CTRL_RST_POWERON", "Asserting init request to all partitions", UVM_MEDIUM) + req.assert_rst = 1'b1; + req.assert_otp_init = 1'b1; + finish_item(req); + `uvm_info("FUSE_CTRL_RST_POWERON", {"Response:", req.convert2string()}, UVM_MEDIUM) + + endtask + +endclass \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/src/fuse_ctrl_rst_random_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/src/fuse_ctrl_rst_random_sequence.svh new file mode 100644 index 0000000..2b719a0 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/src/fuse_ctrl_rst_random_sequence.svh @@ -0,0 +1,67 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This sequences randomizes the fuse_ctrl_rst transaction and sends it +// to the UVM driver. +// +// This sequence constructs and randomizes a fuse_ctrl_rst_transaction. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_rst_random_sequence + extends fuse_ctrl_rst_sequence_base ; + + `uvm_object_utils( fuse_ctrl_rst_random_sequence ) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //***************************************************************** + function new(string name = ""); + super.new(name); + endfunction: new + + // **************************************************************************** + // TASK : body() + // This task is automatically executed when this sequence is started using the + // start(sequencerHandle) task. + // + task body(); + + // Construct the transaction + req=fuse_ctrl_rst_transaction::type_id::create("req"); + start_item(req); + // Randomize the transaction + if(!req.randomize()) `uvm_fatal("SEQ", "fuse_ctrl_rst_random_sequence::body()-fuse_ctrl_rst_transaction randomization failed") + // Send the transaction to the fuse_ctrl_rst_driver_bfm via the sequencer and fuse_ctrl_rst_driver. + finish_item(req); + `uvm_info("SEQ", {"Response:",req.convert2string()},UVM_MEDIUM) + + endtask + +endclass: fuse_ctrl_rst_random_sequence + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/src/fuse_ctrl_rst_responder_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/src/fuse_ctrl_rst_responder_sequence.svh new file mode 100644 index 0000000..85fe8a7 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/src/fuse_ctrl_rst_responder_sequence.svh @@ -0,0 +1,63 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class can be used to provide stimulus when an interface +// has been configured to run in a responder mode. It +// will never finish by default, always going back to the driver +// and driver BFM for the next transaction with which to respond. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_rst_responder_sequence + extends fuse_ctrl_rst_sequence_base ; + + `uvm_object_utils( fuse_ctrl_rst_responder_sequence ) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "fuse_ctrl_rst_responder_sequence"); + super.new(name); + endfunction + + task body(); + req=fuse_ctrl_rst_transaction::type_id::create("req"); + forever begin + start_item(req); + finish_item(req); + // pragma uvmf custom body begin + // UVMF_CHANGE_ME : Do something here with the resulting req item. The + // finish_item() call above will block until the req transaction is ready + // to be handled by the responder sequence. + // If this was an item that required a response, the expectation is + // that the response should be populated within this transaction now. + `uvm_info("SEQ",$sformatf("Processed txn: %s",req.convert2string()),UVM_HIGH) + // pragma uvmf custom body end + end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/src/fuse_ctrl_rst_sequence_base.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/src/fuse_ctrl_rst_sequence_base.svh new file mode 100644 index 0000000..d6a3049 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/src/fuse_ctrl_rst_sequence_base.svh @@ -0,0 +1,110 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the class used as the base class for all sequences +// for this interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_rst_sequence_base extends uvmf_sequence_base #( + .REQ(fuse_ctrl_rst_transaction ), + .RSP(fuse_ctrl_rst_transaction )); + + `uvm_object_utils( fuse_ctrl_rst_sequence_base ) + + // variables + typedef fuse_ctrl_rst_transaction fuse_ctrl_rst_transaction_req_t; + fuse_ctrl_rst_transaction_req_t req; + typedef fuse_ctrl_rst_transaction fuse_ctrl_rst_transaction_rsp_t; + fuse_ctrl_rst_transaction_rsp_t rsp; + + // Event for identifying when a response was received from the sequencer + event new_rsp; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // TASK : get_responses() + // This task recursively gets sequence item responses from the sequencer. + // + virtual task get_responses(); + fork + begin + // Block until new rsp available + get_response(rsp); + // New rsp received. Indicate to sequence using event. + ->new_rsp; + // Display the received response transaction + `uvm_info("SEQ", {"New response transaction:",rsp.convert2string()}, UVM_MEDIUM) + end + join_none + endtask + + // **************************************************************************** + // TASK : pre_body() + // This task is called automatically when start is called with call_pre_post set to 1 (default). + // By calling get_responses() within pre_body() any derived sequences are automatically + // processing response transactions. Only un-comment this call to get_responses() if you + // have configured the interface driver to utilize the response transaction path by setting + // the configuration variable "return_transaction_response" to 1. Otherwise it is possible + // to impact runtime performance and memory utilization. + // + virtual task pre_body(); + // pragma uvmf custom pre_body begin +// get_responses(); + // pragma uvmf custom pre_body end + endtask + + // **************************************************************************** + // TASK : body() + // This task is called automatically when start is called. This sequence sends + // a req sequence item to the sequencer identified as an argument in the call + // to start. + // + virtual task body(); + // pragma uvmf custom body begin + start_item(req); + finish_item(req); + // pragma uvmf custom body end + endtask + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name =""); + super.new( name ); + // pragma uvmf custom new begin + req = fuse_ctrl_rst_transaction_req_t::type_id::create("req"); + rsp = fuse_ctrl_rst_transaction_rsp_t::type_id::create("rsp"); + // pragma uvmf custom new end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/src/fuse_ctrl_rst_transaction.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/src/fuse_ctrl_rst_transaction.svh new file mode 100644 index 0000000..806f8a2 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/src/fuse_ctrl_rst_transaction.svh @@ -0,0 +1,197 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class defines the variables required for an fuse_ctrl_rst +// transaction. Class variables to be displayed in waveform transaction +// viewing are added to the transaction viewing stream in the add_to_wave +// function. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_rst_transaction extends uvmf_transaction_base; + + `uvm_object_utils( fuse_ctrl_rst_transaction ) + + bit assert_rst ; + + //Constraints for the transaction variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //******************************************************************* + //******************************************************************* + // Macros that define structs and associated functions are + // located in fuse_ctrl_rst_macros.svh + + //******************************************************************* + // Monitor macro used by fuse_ctrl_rst_monitor and fuse_ctrl_rst_monitor_bfm + // This struct is defined in fuse_ctrl_rst_macros.svh + `fuse_ctrl_rst_MONITOR_STRUCT + fuse_ctrl_rst_monitor_s fuse_ctrl_rst_monitor_struct; + //******************************************************************* + // FUNCTION: to_monitor_struct() + // This function packs transaction variables into a fuse_ctrl_rst_monitor_s + // structure. The function returns the handle to the fuse_ctrl_rst_monitor_struct. + // This function is defined in fuse_ctrl_rst_macros.svh + `fuse_ctrl_rst_TO_MONITOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_monitor_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_rst_macros.svh + `fuse_ctrl_rst_FROM_MONITOR_STRUCT_FUNCTION + + //******************************************************************* + // Initiator macro used by fuse_ctrl_rst_driver and fuse_ctrl_rst_driver_bfm + // to communicate initiator driven data to fuse_ctrl_rst_driver_bfm. + // This struct is defined in fuse_ctrl_rst_macros.svh + `fuse_ctrl_rst_INITIATOR_STRUCT + fuse_ctrl_rst_initiator_s fuse_ctrl_rst_initiator_struct; + //******************************************************************* + // FUNCTION: to_initiator_struct() + // This function packs transaction variables into a fuse_ctrl_rst_initiator_s + // structure. The function returns the handle to the fuse_ctrl_rst_initiator_struct. + // This function is defined in fuse_ctrl_rst_macros.svh + `fuse_ctrl_rst_TO_INITIATOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_initiator_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_rst_macros.svh + `fuse_ctrl_rst_FROM_INITIATOR_STRUCT_FUNCTION + + //******************************************************************* + // Responder macro used by fuse_ctrl_rst_driver and fuse_ctrl_rst_driver_bfm + // to communicate Responder driven data to fuse_ctrl_rst_driver_bfm. + // This struct is defined in fuse_ctrl_rst_macros.svh + `fuse_ctrl_rst_RESPONDER_STRUCT + fuse_ctrl_rst_responder_s fuse_ctrl_rst_responder_struct; + //******************************************************************* + // FUNCTION: to_responder_struct() + // This function packs transaction variables into a fuse_ctrl_rst_responder_s + // structure. The function returns the handle to the fuse_ctrl_rst_responder_struct. + // This function is defined in fuse_ctrl_rst_macros.svh + `fuse_ctrl_rst_TO_RESPONDER_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_responder_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_rst_macros.svh + `fuse_ctrl_rst_FROM_RESPONDER_STRUCT_FUNCTION + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + endfunction + + // **************************************************************************** + // FUNCTION: convert2string() + // This function converts all variables in this class to a single string for + // logfile reporting. + // + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + // UVMF_CHANGE_ME : Customize format if desired. + return $sformatf("assert_rst:0x%x assert_otp_init:0x%x ",assert_rst,assert_otp_init); + // pragma uvmf custom convert2string end + endfunction + + //******************************************************************* + // FUNCTION: do_print() + // This function is automatically called when the .print() function + // is called on this class. + // + virtual function void do_print(uvm_printer printer); + // pragma uvmf custom do_print begin + // UVMF_CHANGE_ME : Current contents of do_print allows for the use of UVM 1.1d, 1.2 or P1800.2. + // Update based on your own printing preference according to your preferred UVM version + $display(convert2string()); + // pragma uvmf custom do_print end + endfunction + + //******************************************************************* + // FUNCTION: do_compare() + // This function is automatically called when the .compare() function + // is called on this class. + // + virtual function bit do_compare (uvm_object rhs, uvm_comparer comparer); + fuse_ctrl_rst_transaction RHS; + if (!$cast(RHS,rhs)) return 0; + // pragma uvmf custom do_compare begin + // UVMF_CHANGE_ME : Eliminate comparison of variables not to be used for compare + return (super.do_compare(rhs,comparer) + ); + // pragma uvmf custom do_compare end + endfunction + + //******************************************************************* + // FUNCTION: do_copy() + // This function is automatically called when the .copy() function + // is called on this class. + // + virtual function void do_copy (uvm_object rhs); + fuse_ctrl_rst_transaction RHS; + assert($cast(RHS,rhs)); + // pragma uvmf custom do_copy begin + super.do_copy(rhs); + this.assert_rst = RHS.assert_rst; + this.assert_otp_init = RHS.assert_otp_init; + // pragma uvmf custom do_copy end + endfunction + + // **************************************************************************** + // FUNCTION: add_to_wave() + // This function is used to display variables in this class in the waveform + // viewer. The start_time and end_time variables must be set before this + // function is called. If the start_time and end_time variables are not set + // the transaction will be hidden at 0ns on the waveform display. + // + virtual function void add_to_wave(int transaction_viewing_stream_h); + `ifdef QUESTA + if (transaction_view_h == 0) begin + transaction_view_h = $begin_transaction(transaction_viewing_stream_h,"fuse_ctrl_rst_transaction",start_time); + end + super.add_to_wave(transaction_view_h); + // pragma uvmf custom add_to_wave begin + // UVMF_CHANGE_ME : Color can be applied to transaction entries based on content, example below + // case() + // 1 : $add_color(transaction_view_h,"red"); + // default : $add_color(transaction_view_h,"grey"); + // endcase + // UVMF_CHANGE_ME : Eliminate transaction variables not wanted in transaction viewing in the waveform viewer + $add_attribute(transaction_view_h,assert_rst,"assert_rst"); + $add_attribute(transaction_view_h,assert_otp_init,"assert_otp_init"); + // pragma uvmf custom add_to_wave end + $end_transaction(transaction_view_h,end_time); + $free_transaction(transaction_view_h); + `endif // QUESTA + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/src/fuse_ctrl_rst_transaction_coverage.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/src/fuse_ctrl_rst_transaction_coverage.svh new file mode 100644 index 0000000..8bfc9de --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/src/fuse_ctrl_rst_transaction_coverage.svh @@ -0,0 +1,85 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class records fuse_ctrl_rst transaction information using +// a covergroup named fuse_ctrl_rst_transaction_cg. An instance of this +// coverage component is instantiated in the uvmf_parameterized_agent +// if the has_coverage flag is set. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_rst_transaction_coverage extends uvm_subscriber #(.T(fuse_ctrl_rst_transaction )); + + `uvm_component_utils( fuse_ctrl_rst_transaction_coverage ) + + T coverage_trans; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + covergroup fuse_ctrl_rst_transaction_cg; + // pragma uvmf custom covergroup begin + // UVMF_CHANGE_ME : Add coverage bins, crosses, exclusions, etc. according to coverage needs. + option.auto_bin_max=1024; + option.per_instance=1; + assert_rst: coverpoint coverage_trans.assert_rst; + assert_otp_init: coverpoint coverage_trans.assert_otp_init; + // pragma uvmf custom covergroup end + endgroup + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new(string name="", uvm_component parent=null); + super.new(name,parent); + fuse_ctrl_rst_transaction_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that transaction variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + endfunction + + // **************************************************************************** + // FUNCTION : build_phase() + // This function is the standard UVM build_phase. + // + function void build_phase(uvm_phase phase); + fuse_ctrl_rst_transaction_cg.set_inst_name($sformatf("fuse_ctrl_rst_transaction_cg_%s",get_full_name())); + endfunction + + // **************************************************************************** + // FUNCTION: write (T t) + // This function is automatically executed when a transaction arrives on the + // analysis_export. It copies values from the variables in the transaction + // to local variables used to collect functional coverage. + // + virtual function void write (T t); + `uvm_info("COV","Received transaction",UVM_HIGH); + coverage_trans = t; + fuse_ctrl_rst_transaction_cg.sample(); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/src/fuse_ctrl_rst_typedefs.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/src/fuse_ctrl_rst_typedefs.svh new file mode 100644 index 0000000..f2a7bdb --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/src/fuse_ctrl_rst_typedefs.svh @@ -0,0 +1,34 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the host server when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/src/fuse_ctrl_rst_typedefs_hdl.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/src/fuse_ctrl_rst_typedefs_hdl.svh new file mode 100644 index 0000000..0d58518 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/src/fuse_ctrl_rst_typedefs_hdl.svh @@ -0,0 +1,35 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the emulator when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/yaml/fuse_ctrl_rst_interface.yaml b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/yaml/fuse_ctrl_rst_interface.yaml new file mode 100644 index 0000000..d439455 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_rst_pkg/yaml/fuse_ctrl_rst_interface.yaml @@ -0,0 +1,29 @@ +uvmf: + interfaces: + fuse_ctrl_rst: + clock: clk_i + config_constraints: [] + config_vars: [] + existing_library_component: 'True' + gen_inbound_streaming_driver: 'False' + hdl_pkg_parameters: [] + hdl_typedefs: [] + hvl_pkg_parameters: [] + hvl_typedefs: [] + parameters: [] + ports: + - dir: output + name: rst_ni + reset_value: '''bz' + width: '1' + reset: rst_ni + reset_assertion_level: 'False' + transaction_constraints: [] + transaction_vars: + - comment: '' + iscompare: 'False' + isrand: 'False' + name: assert_rst + type: bit + unpacked_dimension: '' + use_dpi_link: 'False' diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/.project b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/.project new file mode 100644 index 0000000..a4da8e3 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/.project @@ -0,0 +1,30 @@ + + + fuse_ctrl_secreg_axi_read_in_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/.svproject b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/.svproject new file mode 100644 index 0000000..52a9f8c --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/Makefile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/Makefile new file mode 100644 index 0000000..0c9fcbd --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/Makefile @@ -0,0 +1,66 @@ +# fuse_ctrl_secreg_axi_read_in interface packages source +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +fuse_ctrl_secreg_axi_read_in_PKG = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_filelist_hvl.f + +fuse_ctrl_secreg_axi_read_in_PKG_HDL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_filelist_hdl.f + +fuse_ctrl_secreg_axi_read_in_PKG_XRTL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_filelist_xrtl.f + +COMP_fuse_ctrl_secreg_axi_read_in_PKG_TGT_0 = q_comp_fuse_ctrl_secreg_axi_read_in_pkg +COMP_fuse_ctrl_secreg_axi_read_in_PKG_TGT_1 = v_comp_fuse_ctrl_secreg_axi_read_in_pkg +COMP_fuse_ctrl_secreg_axi_read_in_PKG_TGT = $(COMP_fuse_ctrl_secreg_axi_read_in_PKG_TGT_$(USE_VELOCE)) + +comp_fuse_ctrl_secreg_axi_read_in_pkg: $(COMP_fuse_ctrl_secreg_axi_read_in_PKG_TGT) + +q_comp_fuse_ctrl_secreg_axi_read_in_pkg: + $(HDL_COMP_CMD) $(fuse_ctrl_secreg_axi_read_in_PKG_HDL) + $(HVL_COMP_CMD) $(fuse_ctrl_secreg_axi_read_in_PKG) + $(HDL_COMP_CMD) $(fuse_ctrl_secreg_axi_read_in_PKG_XRTL) + +v_comp_fuse_ctrl_secreg_axi_read_in_pkg: + $(HVL_COMP_CMD) $(fuse_ctrl_secreg_axi_read_in_PKG_HDL) + $(HVL_COMP_CMD) $(fuse_ctrl_secreg_axi_read_in_PKG) + $(VELANALYZE_CMD) $(fuse_ctrl_secreg_axi_read_in_PKG_HDL) + $(VELANALYZE_HVL_CMD) $(fuse_ctrl_secreg_axi_read_in_PKG) + $(HDL_COMP_CMD) $(fuse_ctrl_secreg_axi_read_in_PKG_XRTL) + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export fuse_ctrl_secreg_axi_read_in_IF_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/dpi + +C_FILE_COMPILE_LIST_fuse_ctrl_secreg_axi_read_in_pkg = \ + +O_FILE_COMPILE_LIST_fuse_ctrl_secreg_axi_read_in_pkg = $(notdir $(C_FILE_COMPILE_LIST_fuse_ctrl_secreg_axi_read_in_pkg:.c=.o)) + +GCC_COMP_ARGS_fuse_ctrl_secreg_axi_read_in_pkg += -I$(fuse_ctrl_secreg_axi_read_in_IF_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_fuse_ctrl_secreg_axi_read_in_pkg += $(fuse_ctrl_secreg_axi_read_in_IF_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_fuse_ctrl_secreg_axi_read_in_pkg += \ + \ + -o .so + +comp_fuse_ctrl_secreg_axi_read_in_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Interface C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_fuse_ctrl_secreg_axi_read_in_pkg) $(C_FILE_COMPILE_LIST_fuse_ctrl_secreg_axi_read_in_pkg) + @echo "--------------------------------" + @echo "Linking Interface C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_fuse_ctrl_secreg_axi_read_in_pkg) $(O_FILE_COMPILE_LIST_fuse_ctrl_secreg_axi_read_in_pkg) + @echo "--------------------------------" + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/compile.do b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/compile.do new file mode 100644 index 0000000..88878d4 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/compile.do @@ -0,0 +1,14 @@ +# Tcl do file for compile of fuse_ctrl_secreg_axi_read_in interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_filelist_hdl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_filelist_hvl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_filelist_xrtl.f \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in.compile new file mode 100644 index 0000000..30a6c81 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in.compile @@ -0,0 +1,3 @@ +needs: + - fuse_ctrl_secreg_axi_read_in_hvl.compile + - fuse_ctrl_secreg_axi_read_in_hdl.compile diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_bfm.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_bfm.vinfo new file mode 100644 index 0000000..7a7c867 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_bfm.vinfo @@ -0,0 +1,6 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use fuse_ctrl_secreg_axi_read_in_pkg_hdl.vinfo ++incdir+@vinfodir +src/fuse_ctrl_secreg_axi_read_in_if.sv +src/fuse_ctrl_secreg_axi_read_in_driver_bfm.sv +src/fuse_ctrl_secreg_axi_read_in_monitor_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_common.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_common.compile new file mode 100644 index 0000000..34e8920 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_common.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +incdir: + - . + - ${uvm_path}/src +src: + - fuse_ctrl_secreg_axi_read_in_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_filelist_hdl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_filelist_hdl.f new file mode 100644 index 0000000..5f203b9 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_filelist_hdl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_filelist_hvl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_filelist_hvl.f new file mode 100644 index 0000000..6917a8f --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_filelist_hvl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_pkg.sv \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_filelist_xrtl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_filelist_xrtl.f new file mode 100644 index 0000000..4801037 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_filelist_xrtl.f @@ -0,0 +1,3 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_if.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_monitor_bfm.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_driver_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_hdl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_hdl.compile new file mode 100644 index 0000000..822c6da --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_hdl.compile @@ -0,0 +1,9 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ./fuse_ctrl_secreg_axi_read_in_common.compile +incdir: + - . +src: + - src/fuse_ctrl_secreg_axi_read_in_if.sv + - src/fuse_ctrl_secreg_axi_read_in_monitor_bfm.sv + - src/fuse_ctrl_secreg_axi_read_in_driver_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_hvl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_hvl.compile new file mode 100644 index 0000000..baf1ae9 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_hvl.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ./fuse_ctrl_secreg_axi_read_in_common.compile +incdir: + - . +src: + - fuse_ctrl_secreg_axi_read_in_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_pkg.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_pkg.sv new file mode 100644 index 0000000..411b495 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_pkg.sv @@ -0,0 +1,91 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - + +// - +// - +// - + +// - +// - +// - + +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_secreg_axi_read_in_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg_hdl::*; + import uvmf_base_pkg::*; + import fuse_ctrl_secreg_axi_read_in_pkg_hdl::*; + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + `include "src/fuse_ctrl_secreg_axi_read_in_macros.svh" + + export fuse_ctrl_secreg_axi_read_in_pkg_hdl::*; + + + + // Parameters defined as HVL parameters + + `include "src/fuse_ctrl_secreg_axi_read_in_typedefs.svh" + `include "src/fuse_ctrl_secreg_axi_read_in_transaction.svh" + + `include "src/fuse_ctrl_secreg_axi_read_in_configuration.svh" + `include "src/fuse_ctrl_secreg_axi_read_in_driver.svh" + `include "src/fuse_ctrl_secreg_axi_read_in_monitor.svh" + + `include "src/fuse_ctrl_secreg_axi_read_in_transaction_coverage.svh" + `include "src/fuse_ctrl_secreg_axi_read_in_sequence_base.svh" + `include "src/fuse_ctrl_secreg_axi_read_in_random_sequence.svh" + + `include "src/fuse_ctrl_secreg_axi_read_in_responder_sequence.svh" + `include "src/fuse_ctrl_secreg_axi_read_in2reg_adapter.svh" + + `include "src/fuse_ctrl_secreg_axi_read_in_agent.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new interface sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the interface package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_pkg.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_pkg.vinfo new file mode 100644 index 0000000..a76e858 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_pkg.vinfo @@ -0,0 +1,4 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use fuse_ctrl_secreg_axi_read_in_pkg_hdl.vinfo ++incdir+@vinfodir +fuse_ctrl_secreg_axi_read_in_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_pkg_hdl.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_pkg_hdl.sv new file mode 100644 index 0000000..1b90f02 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_pkg_hdl.sv @@ -0,0 +1,52 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that needs to be compiled and synthesized +// for running on Veloce. +// +// CONTAINS: +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_secreg_axi_read_in_pkg_hdl; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HDL parameters + + `include "src/fuse_ctrl_secreg_axi_read_in_typedefs_hdl.svh" + `include "src/fuse_ctrl_secreg_axi_read_in_macros.svh" + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_pkg_hdl.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_pkg_hdl.vinfo new file mode 100644 index 0000000..269b5c0 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_pkg_hdl.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +fuse_ctrl_secreg_axi_read_in_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_pkg_sve.F b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_pkg_sve.F new file mode 100644 index 0000000..8fec4a9 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_pkg_sve.F @@ -0,0 +1,10 @@ +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + ++incdir+. +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_filelist_hdl.f +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/fuse_ctrl_secreg_axi_read_in_filelist_hvl.f diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in2reg_adapter.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in2reg_adapter.svh new file mode 100644 index 0000000..c7d2b13 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in2reg_adapter.svh @@ -0,0 +1,142 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the UVM register adapter for the fuse_ctrl_secreg_axi_read_in interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_secreg_axi_read_in2reg_adapter #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvm_reg_adapter; + + `uvm_object_param_utils( fuse_ctrl_secreg_axi_read_in2reg_adapter #( + AW, + DW, + IW, + UW + ) +) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //-------------------------------------------------------------------- + // new + //-------------------------------------------------------------------- + function new (string name = "fuse_ctrl_secreg_axi_read_in2reg_adapter" ); + super.new(name); + // pragma uvmf custom new begin + // UVMF_CHANGE_ME : Configure the adapter regarding byte enables and provides response. + + // Does the protocol the Agent is modeling support byte enables? + // 0 = NO + // 1 = YES + supports_byte_enable = 0; + + // Does the Agent's Driver provide separate response sequence items? + // i.e. Does the driver call seq_item_port.put() + // and do the sequences call get_response()? + // 0 = NO + // 1 = YES + provides_responses = 0; + // pragma uvmf custom new end + + endfunction: new + + //-------------------------------------------------------------------- + // reg2bus + //-------------------------------------------------------------------- + virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw); + + fuse_ctrl_secreg_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + trans_h = fuse_ctrl_secreg_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +::type_id::create("trans_h"); + + // pragma uvmf custom reg2bus begin + // UVMF_CHANGE_ME : Fill in the reg2bus adapter mapping registe fields to protocol fields. + + //Adapt the following for your sequence item type + // trans_h.op = (rw.kind == UVM_READ) ? WB_READ : WB_WRITE; + //Copy over address + // trans_h.addr = rw.addr; + //Copy over write data + // trans_h.data = rw.data; + + // pragma uvmf custom reg2bus end + + // Return the adapted transaction + return trans_h; + + endfunction: reg2bus + + //-------------------------------------------------------------------- + // bus2reg + //-------------------------------------------------------------------- + virtual function void bus2reg(uvm_sequence_item bus_item, + ref uvm_reg_bus_op rw); + fuse_ctrl_secreg_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + trans_h; + if (!$cast(trans_h, bus_item)) begin + `uvm_fatal("ADAPT","Provided bus_item is not of the correct type") + return; + end + // pragma uvmf custom bus2reg begin + // UVMF_CHANGE_ME : Fill in the bus2reg adapter mapping protocol fields to register fields. + //Adapt the following for your sequence item type + //Copy over instruction type + // rw.kind = (trans_h.op == WB_WRITE) ? UVM_WRITE : UVM_READ; + //Copy over address + // rw.addr = trans_h.addr; + //Copy over read data + // rw.data = trans_h.data; + //Check for errors on the bus and return UVM_NOT_OK if there is an error + // rw.status = UVM_IS_OK; + // pragma uvmf custom bus2reg end + + endfunction: bus2reg + +endclass : fuse_ctrl_secreg_axi_read_in2reg_adapter + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_agent.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_agent.svh new file mode 100644 index 0000000..59c7181 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_agent.svh @@ -0,0 +1,109 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: Protocol specific agent class definition +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_secreg_axi_read_in_agent #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvmf_parameterized_agent #( + .CONFIG_T(fuse_ctrl_secreg_axi_read_in_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .DRIVER_T(fuse_ctrl_secreg_axi_read_in_driver #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .MONITOR_T(fuse_ctrl_secreg_axi_read_in_monitor #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .COVERAGE_T(fuse_ctrl_secreg_axi_read_in_transaction_coverage #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .TRANS_T(fuse_ctrl_secreg_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +) + ); + + `uvm_component_param_utils( fuse_ctrl_secreg_axi_read_in_agent #( + AW, + DW, + IW, + UW + ) +) + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** + // FUNCTION: build_phase + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + if (configuration.active_passive == ACTIVE) begin + // Place sequencer handle into configuration object + // so that it may be retrieved from configuration + // rather than using uvm_config_db + configuration.sequencer = this.sequencer; + end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_configuration.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_configuration.svh new file mode 100644 index 0000000..c412470 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_configuration.svh @@ -0,0 +1,241 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class contains all variables and functions used +// to configure the fuse_ctrl_secreg_axi_read_in agent and its bfm's. It gets the +// bfm's from the uvm_config_db for use by the agent. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_secreg_axi_read_in_configuration #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvmf_parameterized_agent_configuration_base #( + .DRIVER_BFM_BIND_T(virtual fuse_ctrl_secreg_axi_read_in_driver_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .MONITOR_BFM_BIND_T( virtual fuse_ctrl_secreg_axi_read_in_monitor_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +)); + + `uvm_object_param_utils( fuse_ctrl_secreg_axi_read_in_configuration #( + AW, + DW, + IW, + UW + ) +) + + + // Sequencer handle populated by agent + uvm_sequencer #(fuse_ctrl_secreg_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + ) sequencer; + + //Constraints for the configuration variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + covergroup fuse_ctrl_secreg_axi_read_in_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + // pragma uvmf custom covergroup end + endgroup + + //******************************************************************* + //******************************************************************* + // Structure used to pass configuration variables to monitor and driver BFM's. + // Use to_struct function to pack variables into structure. + // Use from_struct function to unpack variables from structure. + // This structure is defined in fuse_ctrl_secreg_axi_read_in_macros.svh + `fuse_ctrl_secreg_axi_read_in_CONFIGURATION_STRUCT + fuse_ctrl_secreg_axi_read_in_configuration_s fuse_ctrl_secreg_axi_read_in_configuration_struct; + //******************************************************************* + // FUNCTION: to_struct() + // This function packs variables into a fuse_ctrl_secreg_axi_read_in_configuration_s + // structure. The function returns the handle to the fuse_ctrl_secreg_axi_read_in_configuration_struct. + // This function is defined in fuse_ctrl_secreg_axi_read_in_macros.svh + `fuse_ctrl_secreg_axi_read_in_CONFIGURATION_TO_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_struct() + // This function unpacks the struct provided as an argument into + // variables of this class. + // This function is defined in fuse_ctrl_secreg_axi_read_in_macros.svh + `fuse_ctrl_secreg_axi_read_in_CONFIGURATION_FROM_STRUCT_FUNCTION + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + // Construct the covergroup for this configuration class + fuse_ctrl_secreg_axi_read_in_configuration_cg = new; + endfunction + + // **************************************************************************** + // FUNCTION: post_randomize() + // This function is automatically called after the randomize() function + // is executed. + // + function void post_randomize(); + super.post_randomize(); + fuse_ctrl_secreg_axi_read_in_configuration_cg.sample(); + endfunction + + // **************************************************************************** + // FUNCTION: initialize + // This function causes the configuration to retrieve + // its virtual interface handle from the uvm_config_db. + // This function also makes itself available to its + // agent through the uvm_config_db. + // + // ARGUMENTS: + // uvmf_active_passive_t activity: + // This argument identifies the simulation level + // as either BLOCK, CHIP, SIMULATION, etc. + // + // AGENT_PATH: + // This argument identifies the path to this + // configurations agent. This configuration + // makes itself available to the agent specified + // by agent_path by placing itself into the + // uvm_config_db. + // + // INTERFACE_NAME: + // This argument identifies the string name of + // this configurations BFM's. This string + // name is used to retrieve the driver and + // monitor BFM from the uvm_config_db. + // + virtual function void initialize(uvmf_active_passive_t activity, + string agent_path, + string interface_name); + + super.initialize( activity, agent_path, interface_name); + // The covergroup is given the same name as the interface + fuse_ctrl_secreg_axi_read_in_configuration_cg.set_inst_name(interface_name); + + // This configuration places itself into the uvm_config_db for the agent, identified by the agent_path variable, to retrieve. + uvm_config_db #( fuse_ctrl_secreg_axi_read_in_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + + )::set( null ,agent_path,UVMF_AGENT_CONFIG, this ); + + // This configuration also places itself in the config db using the same identifier used by the interface. This allows users to access + // configuration variables and the interface through the bfm api class rather than directly accessing the BFM. This is useful for + // accessingthe BFM when using Veloce + uvm_config_db #( fuse_ctrl_secreg_axi_read_in_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + + )::set( null ,UVMF_CONFIGURATIONS, interface_name, this ); + + fuse_ctrl_secreg_axi_read_in_configuration_cg.set_inst_name($sformatf("fuse_ctrl_secreg_axi_read_in_configuration_cg_%s",get_full_name())); + +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. + `uvm_info("CFG", + $psprintf("The agent at '%s' is using interface named %s has the following parameters: AW=%x DW=%x IW=%x UW=%x ", agent_path, interface_name, AW ,DW ,IW ,UW ), + UVM_DEBUG) + + // pragma uvmf custom initialize begin + // This controls whether or not the agent returns a transaction handle in the driver when calling + // item_done() back into the sequencer or not. If set to 1, a transaction is sent back which means + // the sequence on the other end must use the get_response() part of the driver/sequence API. If + // this doesn't occur, there will eventually be response_queue overflow errors during the test. + return_transaction_response = 1'b0; + + // pragma uvmf custom initialize end + + endfunction + + // **************************************************************************** + // TASK: wait_for_reset + // *[Required]* Blocks until reset is released. The wait_for_reset operation is performed + // by a task in the monitor bfm. + virtual task wait_for_reset(); + monitor_bfm.wait_for_reset(); + endtask + + // **************************************************************************** + // TASK: wait_for_num_clocks + // *[Required]* Blocks until specified number of clocks have elapsed. The wait_for_num_clocks + // operation is performed by a task in the monitor bfm. + virtual task wait_for_num_clocks(int clocks); + monitor_bfm.wait_for_num_clocks(clocks); + endtask + + // **************************************************************************** + // FUNCTION : convert2string() + // This function is used to convert variables in this class into a string for log messaging. + // + virtual function string convert2string (); + // pragma uvmf custom convert2string begin + return $sformatf(""); + // pragma uvmf custom convert2string end + endfunction + + // **************************************************************************** + // FUNCTION: get_sequencer + function uvm_sequencer #(fuse_ctrl_secreg_axi_read_in_transaction#( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +) get_sequencer(); + return sequencer; + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_driver.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_driver.svh new file mode 100644 index 0000000..dae487d --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_driver.svh @@ -0,0 +1,141 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class passes transactions between the sequencer +// and the BFM driver interface. It accesses the driver BFM +// through the bfm handle. This driver +// passes transactions to the driver BFM through the access +// task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_secreg_axi_read_in_driver #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvmf_driver_base #( + .CONFIG_T(fuse_ctrl_secreg_axi_read_in_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + ), + .BFM_BIND_T(virtual fuse_ctrl_secreg_axi_read_in_driver_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + ), + .REQ(fuse_ctrl_secreg_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + ), + .RSP(fuse_ctrl_secreg_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + )); + + `uvm_component_param_utils( fuse_ctrl_secreg_axi_read_in_driver #( + AW, + DW, + IW, + UW + ) +) +//******************************************************************* +// Macros that define structs located in fuse_ctrl_secreg_axi_read_in_macros.svh +//******************************************************************* +// Initiator macro used by fuse_ctrl_secreg_axi_read_in_driver and fuse_ctrl_secreg_axi_read_in_driver_bfm +// to communicate initiator driven data to fuse_ctrl_secreg_axi_read_in_driver_bfm. +`fuse_ctrl_secreg_axi_read_in_INITIATOR_STRUCT + fuse_ctrl_secreg_axi_read_in_initiator_s fuse_ctrl_secreg_axi_read_in_initiator_struct; +//******************************************************************* +// Responder macro used by fuse_ctrl_secreg_axi_read_in_driver and fuse_ctrl_secreg_axi_read_in_driver_bfm +// to communicate Responder driven data to fuse_ctrl_secreg_axi_read_in_driver_bfm. +`fuse_ctrl_secreg_axi_read_in_RESPONDER_STRUCT + fuse_ctrl_secreg_axi_read_in_responder_s fuse_ctrl_secreg_axi_read_in_responder_struct; + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent=null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the driver BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// driver BFM. This allows the driver BFM to call tasks and function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// **************************************************************************** +// This task is called by the run_phase in uvmf_driver_base. + virtual task access( inout REQ txn ); +// pragma uvmf custom access begin + if (configuration.initiator_responder==RESPONDER) begin + // Complete current transfer and wait for next transfer + bfm.respond_and_wait_for_next_transfer( + fuse_ctrl_secreg_axi_read_in_initiator_struct, + txn.to_responder_struct() + ); + // Unpack information about initiated transfer received by this responder + txn.from_initiator_struct(fuse_ctrl_secreg_axi_read_in_initiator_struct); + end else begin + // Initiate a transfer and get response + bfm.initiate_and_get_response( + txn.to_initiator_struct(), + fuse_ctrl_secreg_axi_read_in_responder_struct + ); + // Unpack transfer response information received by this initiator + txn.from_responder_struct(fuse_ctrl_secreg_axi_read_in_responder_struct); + end +// pragma uvmf custom access end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_driver_bfm.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_driver_bfm.sv new file mode 100644 index 0000000..4b9b815 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_driver_bfm.sv @@ -0,0 +1,385 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This interface performs the fuse_ctrl_secreg_axi_read_in signal driving. It is +// accessed by the uvm fuse_ctrl_secreg_axi_read_in driver through a virtual interface +// handle in the fuse_ctrl_secreg_axi_read_in configuration. It drives the singals passed +// in through the port connection named bus of type fuse_ctrl_secreg_axi_read_in_if. +// +// Input signals from the fuse_ctrl_secreg_axi_read_in_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// This bfm drives signals with a _o suffix. These signals +// are driven onto signals within fuse_ctrl_secreg_axi_read_in_if based on INITIATOR/RESPONDER and/or +// ARBITRATION/GRANT status. +// +// The output signal connections are as follows: +// signal_o -> bus.signal +// +// +// Interface functions and tasks used by UVM components: +// +// configure: +// This function gets configuration attributes from the +// UVM driver to set any required BFM configuration +// variables such as 'initiator_responder'. +// +// initiate_and_get_response: +// This task is used to perform signaling activity for initiating +// a protocol transfer. The task initiates the transfer, using +// input data from the initiator struct. Then the task captures +// response data, placing the data into the response struct. +// The response struct is returned to the driver class. +// +// respond_and_wait_for_next_transfer: +// This task is used to complete a current transfer as a responder +// and then wait for the initiator to start the next transfer. +// The task uses data in the responder struct to drive protocol +// signals to complete the transfer. The task then waits for +// the next transfer. Once the next transfer begins, data from +// the initiator is placed into the initiator struct and sent +// to the responder sequence for processing to determine +// what data to respond with. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_secreg_axi_read_in_pkg_hdl::*; +`include "src/fuse_ctrl_secreg_axi_read_in_macros.svh" + +interface fuse_ctrl_secreg_axi_read_in_driver_bfm #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + + (fuse_ctrl_secreg_axi_read_in_if bus); + // The following pragma and additional ones in-lined further below are for running this BFM on Veloce + // pragma attribute fuse_ctrl_secreg_axi_read_in_driver_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: AW=%x DW=%x IW=%x UW=%x ", AW,DW,IW,UW), + UVM_DEBUG) +end +`endif + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + tri clk_i_i; + tri rst_ni_i; + + // Signal list (all signals are capable of being inputs and outputs for the sake + // of supporting both INITIATOR and RESPONDER mode operation. Expectation is that + // directionality in the config file was from the point-of-view of the INITIATOR + + // INITIATOR mode input signals + + // INITIATOR mode output signals + tri [AW-1:0] araddr_i; + reg [AW-1:0] araddr_o = 'bz; + tri [$bits(axi_pkg::axi_burst_e)-1:0] arburst_i; + reg [$bits(axi_pkg::axi_burst_e)-1:0] arburst_o = 'bz; + tri [2:0] arsize_i; + reg [2:0] arsize_o = 'bz; + tri [7:0] arlen_i; + reg [7:0] arlen_o = 'bz; + tri [UW-1:0] aruser_i; + reg [UW-1:0] aruser_o = 'bz; + tri [IW-1:0] arid_i; + reg [IW-1:0] arid_o = 'bz; + tri arlock_i; + reg arlock_o = 'bz; + tri arvalid_i; + reg arvalid_o = 'bz; + tri rready_i; + reg rready_o = 'bz; + + // Bi-directional signals + + + assign clk_i_i = bus.clk_i; + assign rst_ni_i = bus.rst_ni; + + // These are signals marked as 'input' by the config file, but the signals will be + // driven by this BFM if put into RESPONDER mode (flipping all signal directions around) + + + // These are signals marked as 'output' by the config file, but the outputs will + // not be driven by this BFM unless placed in INITIATOR mode. + assign bus.araddr = (initiator_responder == INITIATOR) ? araddr_o : 'bz; + assign araddr_i = bus.araddr; + assign bus.arburst = (initiator_responder == INITIATOR) ? arburst_o : 'bz; + assign arburst_i = bus.arburst; + assign bus.arsize = (initiator_responder == INITIATOR) ? arsize_o : 'bz; + assign arsize_i = bus.arsize; + assign bus.arlen = (initiator_responder == INITIATOR) ? arlen_o : 'bz; + assign arlen_i = bus.arlen; + assign bus.aruser = (initiator_responder == INITIATOR) ? aruser_o : 'bz; + assign aruser_i = bus.aruser; + assign bus.arid = (initiator_responder == INITIATOR) ? arid_o : 'bz; + assign arid_i = bus.arid; + assign bus.arlock = (initiator_responder == INITIATOR) ? arlock_o : 'bz; + assign arlock_i = bus.arlock; + assign bus.arvalid = (initiator_responder == INITIATOR) ? arvalid_o : 'bz; + assign arvalid_i = bus.arvalid; + assign bus.rready = (initiator_responder == INITIATOR) ? rready_o : 'bz; + assign rready_i = bus.rready; + + // Proxy handle to UVM driver + fuse_ctrl_secreg_axi_read_in_pkg::fuse_ctrl_secreg_axi_read_in_driver #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + proxy; + // pragma tbx oneway proxy.my_function_name_in_uvm_driver + + // **************************************************************************** + // **************************************************************************** + // Macros that define structs located in fuse_ctrl_secreg_axi_read_in_macros.svh + // **************************************************************************** + // Struct for passing configuration data from fuse_ctrl_secreg_axi_read_in_driver to this BFM + // **************************************************************************** + `fuse_ctrl_secreg_axi_read_in_CONFIGURATION_STRUCT + // **************************************************************************** + // Structs for INITIATOR and RESPONDER data flow + //******************************************************************* + // Initiator macro used by fuse_ctrl_secreg_axi_read_in_driver and fuse_ctrl_secreg_axi_read_in_driver_bfm + // to communicate initiator driven data to fuse_ctrl_secreg_axi_read_in_driver_bfm. + `fuse_ctrl_secreg_axi_read_in_INITIATOR_STRUCT + fuse_ctrl_secreg_axi_read_in_initiator_s initiator_struct; + // Responder macro used by fuse_ctrl_secreg_axi_read_in_driver and fuse_ctrl_secreg_axi_read_in_driver_bfm + // to communicate Responder driven data to fuse_ctrl_secreg_axi_read_in_driver_bfm. + `fuse_ctrl_secreg_axi_read_in_RESPONDER_STRUCT + fuse_ctrl_secreg_axi_read_in_responder_s responder_struct; + + // **************************************************************************** +// pragma uvmf custom reset_condition_and_response begin + // Always block used to return signals to reset value upon assertion of reset + always @( negedge rst_ni_i ) + begin + // RESPONDER mode output signals + // INITIATOR mode output signals + araddr_o <= 'bz; + arburst_o <= 'bz; + arsize_o <= 'bz; + arlen_o <= 'bz; + aruser_o <= 'bz; + arid_o <= 'bz; + arlock_o <= 'bz; + arvalid_o <= 'bz; + rready_o <= 'bz; + // Bi-directional signals + + end +// pragma uvmf custom reset_condition_and_response end + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the driver BFM. It is called by the driver within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the driver BFM needs to be aware of the new configuration + // variables. + // + + function void configure(fuse_ctrl_secreg_axi_read_in_configuration_s fuse_ctrl_secreg_axi_read_in_configuration_arg); // pragma tbx xtf + initiator_responder = fuse_ctrl_secreg_axi_read_in_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + +// pragma uvmf custom initiate_and_get_response begin +// **************************************************************************** +// UVMF_CHANGE_ME +// This task is used by an initator. The task first initiates a transfer then +// waits for the responder to complete the transfer. + task initiate_and_get_response( + // This argument passes transaction variables used by an initiator + // to perform the initial part of a protocol transfer. The values + // come from a sequence item created in a sequence. + input fuse_ctrl_secreg_axi_read_in_initiator_s fuse_ctrl_secreg_axi_read_in_initiator_struct, + // This argument is used to send data received from the responder + // back to the sequence item. The sequence item is returned to the sequence. + output fuse_ctrl_secreg_axi_read_in_responder_s fuse_ctrl_secreg_axi_read_in_responder_struct + );// pragma tbx xtf + // + // Members within the fuse_ctrl_secreg_axi_read_in_initiator_struct: + // logic [AW-1:0] secreg_araddr ; + // logic secreg_arvalid ; + // logic [$bits(axi_pkg::axi_burst_e)] secreg_arburst ; + // logic [2:0] secreg_arsize ; + // logic [7:0] secreg_arlen ; + // logic [UW-1:0] secreg_aruser ; + // logic [IW-1:0] secreg_arid ; + // logic secreg_arlock ; + // logic secreg_rready ; + // Members within the fuse_ctrl_secreg_axi_read_in_responder_struct: + // logic [AW-1:0] secreg_araddr ; + // logic secreg_arvalid ; + // logic [$bits(axi_pkg::axi_burst_e)] secreg_arburst ; + // logic [2:0] secreg_arsize ; + // logic [7:0] secreg_arlen ; + // logic [UW-1:0] secreg_aruser ; + // logic [IW-1:0] secreg_arid ; + // logic secreg_arlock ; + // logic secreg_rready ; + initiator_struct = fuse_ctrl_secreg_axi_read_in_initiator_struct; + // + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clk_i_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available initiator input and inout signals listed. + // Initiator input signals + // Initiator inout signals + // How to assign a signal from an initiator struct member named xyz. + // All available initiator output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Initiator output signals + // araddr_o <= fuse_ctrl_secreg_axi_read_in_initiator_struct.xyz; // [AW-1:0] + // arburst_o <= fuse_ctrl_secreg_axi_read_in_initiator_struct.xyz; // [$bits(axi_pkg::axi_burst_e)-1:0] + // arsize_o <= fuse_ctrl_secreg_axi_read_in_initiator_struct.xyz; // [2:0] + // arlen_o <= fuse_ctrl_secreg_axi_read_in_initiator_struct.xyz; // [7:0] + // aruser_o <= fuse_ctrl_secreg_axi_read_in_initiator_struct.xyz; // [UW-1:0] + // arid_o <= fuse_ctrl_secreg_axi_read_in_initiator_struct.xyz; // [IW-1:0] + // arlock_o <= fuse_ctrl_secreg_axi_read_in_initiator_struct.xyz; // + // arvalid_o <= fuse_ctrl_secreg_axi_read_in_initiator_struct.xyz; // + // rready_o <= fuse_ctrl_secreg_axi_read_in_initiator_struct.xyz; // + // Initiator inout signals + // Initiate a transfer using the data received. + @(posedge clk_i_i); + @(posedge clk_i_i); + // Wait for the responder to complete the transfer then place the responder data into + // fuse_ctrl_secreg_axi_read_in_responder_struct. + @(posedge clk_i_i); + @(posedge clk_i_i); + responder_struct = fuse_ctrl_secreg_axi_read_in_responder_struct; + endtask +// pragma uvmf custom initiate_and_get_response end + +// pragma uvmf custom respond_and_wait_for_next_transfer begin +// **************************************************************************** +// The first_transfer variable is used to prevent completing a transfer in the +// first call to this task. For the first call to this task, there is not +// current transfer to complete. +bit first_transfer=1; + +// UVMF_CHANGE_ME +// This task is used by a responder. The task first completes the current +// transfer in progress then waits for the initiator to start the next transfer. + task respond_and_wait_for_next_transfer( + // This argument is used to send data received from the initiator + // back to the sequence item. The sequence determines how to respond. + output fuse_ctrl_secreg_axi_read_in_initiator_s fuse_ctrl_secreg_axi_read_in_initiator_struct, + // This argument passes transaction variables used by a responder + // to complete a protocol transfer. The values come from a sequence item. + input fuse_ctrl_secreg_axi_read_in_responder_s fuse_ctrl_secreg_axi_read_in_responder_struct + );// pragma tbx xtf + // Variables within the fuse_ctrl_secreg_axi_read_in_initiator_struct: + // logic [AW-1:0] secreg_araddr ; + // logic secreg_arvalid ; + // logic [$bits(axi_pkg::axi_burst_e)] secreg_arburst ; + // logic [2:0] secreg_arsize ; + // logic [7:0] secreg_arlen ; + // logic [UW-1:0] secreg_aruser ; + // logic [IW-1:0] secreg_arid ; + // logic secreg_arlock ; + // logic secreg_rready ; + // Variables within the fuse_ctrl_secreg_axi_read_in_responder_struct: + // logic [AW-1:0] secreg_araddr ; + // logic secreg_arvalid ; + // logic [$bits(axi_pkg::axi_burst_e)] secreg_arburst ; + // logic [2:0] secreg_arsize ; + // logic [7:0] secreg_arlen ; + // logic [UW-1:0] secreg_aruser ; + // logic [IW-1:0] secreg_arid ; + // logic secreg_arlock ; + // logic secreg_rready ; + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clk_i_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available responder input and inout signals listed. + // Responder input signals + // fuse_ctrl_secreg_axi_read_in_responder_struct.xyz = araddr_i; // [AW-1:0] + // fuse_ctrl_secreg_axi_read_in_responder_struct.xyz = arburst_i; // [$bits(axi_pkg::axi_burst_e)-1:0] + // fuse_ctrl_secreg_axi_read_in_responder_struct.xyz = arsize_i; // [2:0] + // fuse_ctrl_secreg_axi_read_in_responder_struct.xyz = arlen_i; // [7:0] + // fuse_ctrl_secreg_axi_read_in_responder_struct.xyz = aruser_i; // [UW-1:0] + // fuse_ctrl_secreg_axi_read_in_responder_struct.xyz = arid_i; // [IW-1:0] + // fuse_ctrl_secreg_axi_read_in_responder_struct.xyz = arlock_i; // + // fuse_ctrl_secreg_axi_read_in_responder_struct.xyz = arvalid_i; // + // fuse_ctrl_secreg_axi_read_in_responder_struct.xyz = rready_i; // + // Responder inout signals + // How to assign a signal, named xyz, from an initiator struct member. + // All available responder output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Responder output signals + // Responder inout signals + + @(posedge clk_i_i); + if (!first_transfer) begin + // Perform transfer response here. + // Reply using data recieved in the fuse_ctrl_secreg_axi_read_in_responder_struct. + @(posedge clk_i_i); + // Reply using data recieved in the transaction handle. + @(posedge clk_i_i); + end + // Wait for next transfer then gather info from intiator about the transfer. + // Place the data into the fuse_ctrl_secreg_axi_read_in_initiator_struct. + @(posedge clk_i_i); + @(posedge clk_i_i); + first_transfer = 0; + endtask +// pragma uvmf custom respond_and_wait_for_next_transfer end + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_if.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_if.sv new file mode 100644 index 0000000..74f7ba6 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_if.sv @@ -0,0 +1,124 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface contains the fuse_ctrl_secreg_axi_read_in interface signals. +// It is instantiated once per fuse_ctrl_secreg_axi_read_in bus. Bus Functional Models, +// BFM's named fuse_ctrl_secreg_axi_read_in_driver_bfm, are used to drive signals on the bus. +// BFM's named fuse_ctrl_secreg_axi_read_in_monitor_bfm are used to monitor signals on the +// bus. This interface signal bundle is passed in the port list of +// the BFM in order to give the BFM access to the signals in this +// interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// This template can be used to connect a DUT to these signals +// +// .dut_signal_port(fuse_ctrl_secreg_axi_read_in_bus.araddr), // Agent output +// .dut_signal_port(fuse_ctrl_secreg_axi_read_in_bus.arburst), // Agent output +// .dut_signal_port(fuse_ctrl_secreg_axi_read_in_bus.arsize), // Agent output +// .dut_signal_port(fuse_ctrl_secreg_axi_read_in_bus.arlen), // Agent output +// .dut_signal_port(fuse_ctrl_secreg_axi_read_in_bus.aruser), // Agent output +// .dut_signal_port(fuse_ctrl_secreg_axi_read_in_bus.arid), // Agent output +// .dut_signal_port(fuse_ctrl_secreg_axi_read_in_bus.arlock), // Agent output +// .dut_signal_port(fuse_ctrl_secreg_axi_read_in_bus.arvalid), // Agent output +// .dut_signal_port(fuse_ctrl_secreg_axi_read_in_bus.rready), // Agent output + +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_secreg_axi_read_in_pkg_hdl::*; + +interface fuse_ctrl_secreg_axi_read_in_if #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + + + ( + input tri clk_i, + input tri rst_ni, + inout tri [AW-1:0] araddr, + inout tri [$bits(axi_pkg::axi_burst_e)-1:0] arburst, + inout tri [2:0] arsize, + inout tri [7:0] arlen, + inout tri [UW-1:0] aruser, + inout tri [IW-1:0] arid, + inout tri arlock, + inout tri arvalid, + inout tri rready + ); + +modport monitor_port + ( + input clk_i, + input rst_ni, + input araddr, + input arburst, + input arsize, + input arlen, + input aruser, + input arid, + input arlock, + input arvalid, + input rready + ); + +modport initiator_port + ( + input clk_i, + input rst_ni, + output araddr, + output arburst, + output arsize, + output arlen, + output aruser, + output arid, + output arlock, + output arvalid, + output rready + ); + +modport responder_port + ( + input clk_i, + input rst_ni, + input araddr, + input arburst, + input arsize, + input arlen, + input aruser, + input arid, + input arlock, + input arvalid, + input rready + ); + + +// pragma uvmf custom interface_item_additional begin +// pragma uvmf custom interface_item_additional end + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_infact_coverage_strategy.csv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_infact_coverage_strategy.csv new file mode 100644 index 0000000..1c218e1 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_infact_coverage_strategy.csv @@ -0,0 +1,6 @@ +Global +auto_bin_max, 64 + +Name,Type,Include +rand_fields,coverpoint,=rand *.** + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_macros.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_macros.svh new file mode 100644 index 0000000..fd62fe9 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_macros.svh @@ -0,0 +1,207 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains macros used with the fuse_ctrl_secreg_axi_read_in package. +// These macros include packed struct definitions. These structs are +// used to pass data between classes, hvl, and BFM's, hdl. Use of +// structs are more efficient and simpler to modify. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_struct +// and from_struct methods defined in the macros below that are used in +// the fuse_ctrl_secreg_axi_read_in_configuration class. +// + `define fuse_ctrl_secreg_axi_read_in_CONFIGURATION_STRUCT \ +typedef struct packed { \ + uvmf_active_passive_t active_passive; \ + uvmf_initiator_responder_t initiator_responder; \ + } fuse_ctrl_secreg_axi_read_in_configuration_s; + + `define fuse_ctrl_secreg_axi_read_in_CONFIGURATION_TO_STRUCT_FUNCTION \ + virtual function fuse_ctrl_secreg_axi_read_in_configuration_s to_struct();\ + fuse_ctrl_secreg_axi_read_in_configuration_struct = \ + {\ + this.active_passive,\ + this.initiator_responder\ + };\ + return ( fuse_ctrl_secreg_axi_read_in_configuration_struct );\ + endfunction + + `define fuse_ctrl_secreg_axi_read_in_CONFIGURATION_FROM_STRUCT_FUNCTION \ + virtual function void from_struct(fuse_ctrl_secreg_axi_read_in_configuration_s fuse_ctrl_secreg_axi_read_in_configuration_struct);\ + {\ + this.active_passive,\ + this.initiator_responder \ + } = fuse_ctrl_secreg_axi_read_in_configuration_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_monitor_struct +// and from_monitor_struct methods of the fuse_ctrl_secreg_axi_read_in_transaction class. +// + `define fuse_ctrl_secreg_axi_read_in_MONITOR_STRUCT typedef struct packed { \ + logic [AW-1:0] secreg_araddr ; \ + logic secreg_arvalid ; \ + logic [$bits(axi_pkg::axi_burst_e)] secreg_arburst ; \ + logic [2:0] secreg_arsize ; \ + logic [7:0] secreg_arlen ; \ + logic [UW-1:0] secreg_aruser ; \ + logic [IW-1:0] secreg_arid ; \ + logic secreg_arlock ; \ + logic secreg_rready ; \ + } fuse_ctrl_secreg_axi_read_in_monitor_s; + + `define fuse_ctrl_secreg_axi_read_in_TO_MONITOR_STRUCT_FUNCTION \ + virtual function fuse_ctrl_secreg_axi_read_in_monitor_s to_monitor_struct();\ + fuse_ctrl_secreg_axi_read_in_monitor_struct = \ + { \ + this.secreg_araddr , \ + this.secreg_arvalid , \ + this.secreg_arburst , \ + this.secreg_arsize , \ + this.secreg_arlen , \ + this.secreg_aruser , \ + this.secreg_arid , \ + this.secreg_arlock , \ + this.secreg_rready \ + };\ + return ( fuse_ctrl_secreg_axi_read_in_monitor_struct);\ + endfunction\ + + `define fuse_ctrl_secreg_axi_read_in_FROM_MONITOR_STRUCT_FUNCTION \ + virtual function void from_monitor_struct(fuse_ctrl_secreg_axi_read_in_monitor_s fuse_ctrl_secreg_axi_read_in_monitor_struct);\ + {\ + this.secreg_araddr , \ + this.secreg_arvalid , \ + this.secreg_arburst , \ + this.secreg_arsize , \ + this.secreg_arlen , \ + this.secreg_aruser , \ + this.secreg_arid , \ + this.secreg_arlock , \ + this.secreg_rready \ + } = fuse_ctrl_secreg_axi_read_in_monitor_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_initiator_struct +// and from_initiator_struct methods of the fuse_ctrl_secreg_axi_read_in_transaction class. +// Also update the comments in the driver BFM. +// + `define fuse_ctrl_secreg_axi_read_in_INITIATOR_STRUCT typedef struct packed { \ + logic [AW-1:0] secreg_araddr ; \ + logic secreg_arvalid ; \ + logic [$bits(axi_pkg::axi_burst_e)] secreg_arburst ; \ + logic [2:0] secreg_arsize ; \ + logic [7:0] secreg_arlen ; \ + logic [UW-1:0] secreg_aruser ; \ + logic [IW-1:0] secreg_arid ; \ + logic secreg_arlock ; \ + logic secreg_rready ; \ + } fuse_ctrl_secreg_axi_read_in_initiator_s; + + `define fuse_ctrl_secreg_axi_read_in_TO_INITIATOR_STRUCT_FUNCTION \ + virtual function fuse_ctrl_secreg_axi_read_in_initiator_s to_initiator_struct();\ + fuse_ctrl_secreg_axi_read_in_initiator_struct = \ + {\ + this.secreg_araddr , \ + this.secreg_arvalid , \ + this.secreg_arburst , \ + this.secreg_arsize , \ + this.secreg_arlen , \ + this.secreg_aruser , \ + this.secreg_arid , \ + this.secreg_arlock , \ + this.secreg_rready \ + };\ + return ( fuse_ctrl_secreg_axi_read_in_initiator_struct);\ + endfunction + + `define fuse_ctrl_secreg_axi_read_in_FROM_INITIATOR_STRUCT_FUNCTION \ + virtual function void from_initiator_struct(fuse_ctrl_secreg_axi_read_in_initiator_s fuse_ctrl_secreg_axi_read_in_initiator_struct);\ + {\ + this.secreg_araddr , \ + this.secreg_arvalid , \ + this.secreg_arburst , \ + this.secreg_arsize , \ + this.secreg_arlen , \ + this.secreg_aruser , \ + this.secreg_arid , \ + this.secreg_arlock , \ + this.secreg_rready \ + } = fuse_ctrl_secreg_axi_read_in_initiator_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_responder_struct +// and from_responder_struct methods of the fuse_ctrl_secreg_axi_read_in_transaction class. +// Also update the comments in the driver BFM. +// + `define fuse_ctrl_secreg_axi_read_in_RESPONDER_STRUCT typedef struct packed { \ + logic [AW-1:0] secreg_araddr ; \ + logic secreg_arvalid ; \ + logic [$bits(axi_pkg::axi_burst_e)] secreg_arburst ; \ + logic [2:0] secreg_arsize ; \ + logic [7:0] secreg_arlen ; \ + logic [UW-1:0] secreg_aruser ; \ + logic [IW-1:0] secreg_arid ; \ + logic secreg_arlock ; \ + logic secreg_rready ; \ + } fuse_ctrl_secreg_axi_read_in_responder_s; + + `define fuse_ctrl_secreg_axi_read_in_TO_RESPONDER_STRUCT_FUNCTION \ + virtual function fuse_ctrl_secreg_axi_read_in_responder_s to_responder_struct();\ + fuse_ctrl_secreg_axi_read_in_responder_struct = \ + {\ + this.secreg_araddr , \ + this.secreg_arvalid , \ + this.secreg_arburst , \ + this.secreg_arsize , \ + this.secreg_arlen , \ + this.secreg_aruser , \ + this.secreg_arid , \ + this.secreg_arlock , \ + this.secreg_rready \ + };\ + return ( fuse_ctrl_secreg_axi_read_in_responder_struct);\ + endfunction + + `define fuse_ctrl_secreg_axi_read_in_FROM_RESPONDER_STRUCT_FUNCTION \ + virtual function void from_responder_struct(fuse_ctrl_secreg_axi_read_in_responder_s fuse_ctrl_secreg_axi_read_in_responder_struct);\ + {\ + this.secreg_araddr , \ + this.secreg_arvalid , \ + this.secreg_arburst , \ + this.secreg_arsize , \ + this.secreg_arlen , \ + this.secreg_aruser , \ + this.secreg_arid , \ + this.secreg_arlock , \ + this.secreg_rready \ + } = fuse_ctrl_secreg_axi_read_in_responder_struct;\ + endfunction +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_monitor.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_monitor.svh new file mode 100644 index 0000000..f62bb2c --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_monitor.svh @@ -0,0 +1,131 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class receives fuse_ctrl_secreg_axi_read_in transactions observed by the +// fuse_ctrl_secreg_axi_read_in monitor BFM and broadcasts them through the analysis port +// on the agent. It accesses the monitor BFM through the monitor +// task. This UVM component captures transactions +// for viewing in the waveform viewer if the +// enable_transaction_viewing flag is set in the configuration. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_secreg_axi_read_in_monitor #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvmf_monitor_base #( + .CONFIG_T(fuse_ctrl_secreg_axi_read_in_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .BFM_BIND_T(virtual fuse_ctrl_secreg_axi_read_in_monitor_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .TRANS_T(fuse_ctrl_secreg_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +)); + + `uvm_component_param_utils( fuse_ctrl_secreg_axi_read_in_monitor #( + AW, + DW, + IW, + UW + ) +) + +// Structure used to pass data from monitor BFM to monitor class in agent. +// Use to_monitor_struct function to pack transaction variables into structure. +// Use from_monitor_struct function to unpack transaction variables from structure. +`fuse_ctrl_secreg_axi_read_in_MONITOR_STRUCT + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the monitor BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// monitor BFM. This allows the monitor BFM to call the notify_transaction +// function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// *************************************************************************** + virtual task run_phase(uvm_phase phase); + // Start monitor BFM thread and don't call super.run() in order to + // override the default monitor proxy 'pull' behavior with the more + // emulation-friendly BFM 'push' approach using the notify_transaction + // function below + bfm.start_monitoring(); + endtask + +// ************************************************************************** + +// This function is called by the monitor BFM. It receives data observed by the +// monitor BFM. Data is passed using the fuse_ctrl_secreg_axi_read_in_monitor_struct. + virtual function void notify_transaction(input fuse_ctrl_secreg_axi_read_in_monitor_s fuse_ctrl_secreg_axi_read_in_monitor_struct); + + + trans = new("trans"); + trans.from_monitor_struct(fuse_ctrl_secreg_axi_read_in_monitor_struct); + trans.start_time = time_stamp; + trans.end_time = $time; + time_stamp = trans.end_time; + + analyze(trans); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_monitor_bfm.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_monitor_bfm.sv new file mode 100644 index 0000000..520864f --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_monitor_bfm.sv @@ -0,0 +1,232 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface performs the fuse_ctrl_secreg_axi_read_in signal monitoring. +// It is accessed by the uvm fuse_ctrl_secreg_axi_read_in monitor through a virtual +// interface handle in the fuse_ctrl_secreg_axi_read_in configuration. It monitors the +// signals passed in through the port connection named bus of +// type fuse_ctrl_secreg_axi_read_in_if. +// +// Input signals from the fuse_ctrl_secreg_axi_read_in_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// Interface functions and tasks used by UVM components: +// monitor(inout TRANS_T txn); +// This task receives the transaction, txn, from the +// UVM monitor and then populates variables in txn +// from values observed on bus activity. This task +// blocks until an operation on the fuse_ctrl_secreg_axi_read_in bus is complete. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_secreg_axi_read_in_pkg_hdl::*; +`include "src/fuse_ctrl_secreg_axi_read_in_macros.svh" + + +interface fuse_ctrl_secreg_axi_read_in_monitor_bfm #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + + ( fuse_ctrl_secreg_axi_read_in_if bus ); + // The pragma below and additional ones in-lined further down are for running this BFM on Veloce + // pragma attribute fuse_ctrl_secreg_axi_read_in_monitor_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: AW=%x DW=%x IW=%x UW=%x ", AW,DW,IW,UW), + UVM_DEBUG) +end +`endif + + + // Structure used to pass transaction data from monitor BFM to monitor class in agent. +`fuse_ctrl_secreg_axi_read_in_MONITOR_STRUCT + fuse_ctrl_secreg_axi_read_in_monitor_s fuse_ctrl_secreg_axi_read_in_monitor_struct; + + // Structure used to pass configuration data from monitor class to monitor BFM. + `fuse_ctrl_secreg_axi_read_in_CONFIGURATION_STRUCT + + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + tri clk_i_i; + tri rst_ni_i; + tri [AW-1:0] araddr_i; + tri [$bits(axi_pkg::axi_burst_e)-1:0] arburst_i; + tri [2:0] arsize_i; + tri [7:0] arlen_i; + tri [UW-1:0] aruser_i; + tri [IW-1:0] arid_i; + tri arlock_i; + tri arvalid_i; + tri rready_i; + assign clk_i_i = bus.clk_i; + assign rst_ni_i = bus.rst_ni; + assign araddr_i = bus.araddr; + assign arburst_i = bus.arburst; + assign arsize_i = bus.arsize; + assign arlen_i = bus.arlen; + assign aruser_i = bus.aruser; + assign arid_i = bus.arid; + assign arlock_i = bus.arlock; + assign arvalid_i = bus.arvalid; + assign rready_i = bus.rready; + + // Proxy handle to UVM monitor + fuse_ctrl_secreg_axi_read_in_pkg::fuse_ctrl_secreg_axi_read_in_monitor #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + proxy; + // pragma tbx oneway proxy.notify_transaction + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + task wait_for_reset();// pragma tbx xtf + @(posedge clk_i_i) ; + do_wait_for_reset(); + endtask + + // **************************************************************************** + task do_wait_for_reset(); + // pragma uvmf custom reset_condition begin + wait ( rst_ni_i === 1 ) ; + @(posedge clk_i_i) ; + // pragma uvmf custom reset_condition end + endtask + + //****************************************************************** + + task wait_for_num_clocks(input int unsigned count); // pragma tbx xtf + @(posedge clk_i_i); + + repeat (count-1) @(posedge clk_i_i); + endtask + + //****************************************************************** + event go; + function void start_monitoring();// pragma tbx xtf + -> go; + endfunction + + // **************************************************************************** + initial begin + @go; + forever begin + @(posedge clk_i_i); + do_monitor( fuse_ctrl_secreg_axi_read_in_monitor_struct ); + + + proxy.notify_transaction( fuse_ctrl_secreg_axi_read_in_monitor_struct ); + + end + end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the monitor BFM. It is called by the monitor within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the monitor BFM needs to be aware of the new configuration + // variables. + // + function void configure(fuse_ctrl_secreg_axi_read_in_configuration_s fuse_ctrl_secreg_axi_read_in_configuration_arg); // pragma tbx xtf + initiator_responder = fuse_ctrl_secreg_axi_read_in_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + + + // **************************************************************************** + + task do_monitor(output fuse_ctrl_secreg_axi_read_in_monitor_s fuse_ctrl_secreg_axi_read_in_monitor_struct); + // + // Available struct members: + // // fuse_ctrl_secreg_axi_read_in_monitor_struct.secreg_araddr + // // fuse_ctrl_secreg_axi_read_in_monitor_struct.secreg_arvalid + // // fuse_ctrl_secreg_axi_read_in_monitor_struct.secreg_arburst + // // fuse_ctrl_secreg_axi_read_in_monitor_struct.secreg_arsize + // // fuse_ctrl_secreg_axi_read_in_monitor_struct.secreg_arlen + // // fuse_ctrl_secreg_axi_read_in_monitor_struct.secreg_aruser + // // fuse_ctrl_secreg_axi_read_in_monitor_struct.secreg_arid + // // fuse_ctrl_secreg_axi_read_in_monitor_struct.secreg_arlock + // // fuse_ctrl_secreg_axi_read_in_monitor_struct.secreg_rready + // // + // Reference code; + // How to wait for signal value + // while (control_signal === 1'b1) @(posedge clk_i_i); + // + // How to assign a struct member, named xyz, from a signal. + // All available input signals listed. + // fuse_ctrl_secreg_axi_read_in_monitor_struct.xyz = araddr_i; // [AW-1:0] + // fuse_ctrl_secreg_axi_read_in_monitor_struct.xyz = arburst_i; // [$bits(axi_pkg::axi_burst_e)-1:0] + // fuse_ctrl_secreg_axi_read_in_monitor_struct.xyz = arsize_i; // [2:0] + // fuse_ctrl_secreg_axi_read_in_monitor_struct.xyz = arlen_i; // [7:0] + // fuse_ctrl_secreg_axi_read_in_monitor_struct.xyz = aruser_i; // [UW-1:0] + // fuse_ctrl_secreg_axi_read_in_monitor_struct.xyz = arid_i; // [IW-1:0] + // fuse_ctrl_secreg_axi_read_in_monitor_struct.xyz = arlock_i; // + // fuse_ctrl_secreg_axi_read_in_monitor_struct.xyz = arvalid_i; // + // fuse_ctrl_secreg_axi_read_in_monitor_struct.xyz = rready_i; // + // pragma uvmf custom do_monitor begin + // UVMF_CHANGE_ME : Implement protocol monitoring. The commented reference code + // below are examples of how to capture signal values and assign them to + // structure members. All available input signals are listed. The 'while' + // code example shows how to wait for a synchronous flow control signal. This + // task should return when a complete transfer has been observed. Once this task is + // exited with captured values, it is then called again to wait for and observe + // the next transfer. One clock cycle is consumed between calls to do_monitor. + @(posedge clk_i_i); + @(posedge clk_i_i); + @(posedge clk_i_i); + @(posedge clk_i_i); + // pragma uvmf custom do_monitor end + endtask + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_random_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_random_sequence.svh new file mode 100644 index 0000000..b2a6f7e --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_random_sequence.svh @@ -0,0 +1,91 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This sequences randomizes the fuse_ctrl_secreg_axi_read_in transaction and sends it +// to the UVM driver. +// +// This sequence constructs and randomizes a fuse_ctrl_secreg_axi_read_in_transaction. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_secreg_axi_read_in_random_sequence #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + + extends fuse_ctrl_secreg_axi_read_in_sequence_base #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +; + + `uvm_object_param_utils( fuse_ctrl_secreg_axi_read_in_random_sequence #( + AW, + DW, + IW, + UW + ) +) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //***************************************************************** + function new(string name = ""); + super.new(name); + endfunction: new + + // **************************************************************************** + // TASK : body() + // This task is automatically executed when this sequence is started using the + // start(sequencerHandle) task. + // + task body(); + + // Construct the transaction + req=fuse_ctrl_secreg_axi_read_in_transaction#( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +::type_id::create("req"); + start_item(req); + // Randomize the transaction + if(!req.randomize()) `uvm_fatal("SEQ", "fuse_ctrl_secreg_axi_read_in_random_sequence::body()-fuse_ctrl_secreg_axi_read_in_transaction randomization failed") + // Send the transaction to the fuse_ctrl_secreg_axi_read_in_driver_bfm via the sequencer and fuse_ctrl_secreg_axi_read_in_driver. + finish_item(req); + `uvm_info("SEQ", {"Response:",req.convert2string()},UVM_MEDIUM) + + endtask + +endclass: fuse_ctrl_secreg_axi_read_in_random_sequence + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_responder_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_responder_sequence.svh new file mode 100644 index 0000000..c2c7396 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_responder_sequence.svh @@ -0,0 +1,87 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class can be used to provide stimulus when an interface +// has been configured to run in a responder mode. It +// will never finish by default, always going back to the driver +// and driver BFM for the next transaction with which to respond. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_secreg_axi_read_in_responder_sequence #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + + extends fuse_ctrl_secreg_axi_read_in_sequence_base #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +; + + `uvm_object_param_utils( fuse_ctrl_secreg_axi_read_in_responder_sequence #( + AW, + DW, + IW, + UW + ) +) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "fuse_ctrl_secreg_axi_read_in_responder_sequence"); + super.new(name); + endfunction + + task body(); + req=fuse_ctrl_secreg_axi_read_in_transaction#( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +::type_id::create("req"); + forever begin + start_item(req); + finish_item(req); + // pragma uvmf custom body begin + // UVMF_CHANGE_ME : Do something here with the resulting req item. The + // finish_item() call above will block until the req transaction is ready + // to be handled by the responder sequence. + // If this was an item that required a response, the expectation is + // that the response should be populated within this transaction now. + `uvm_info("SEQ",$sformatf("Processed txn: %s",req.convert2string()),UVM_HIGH) + // pragma uvmf custom body end + end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_sequence_base.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_sequence_base.svh new file mode 100644 index 0000000..dff36dd --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_sequence_base.svh @@ -0,0 +1,146 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the class used as the base class for all sequences +// for this interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_secreg_axi_read_in_sequence_base #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvmf_sequence_base #( + .REQ(fuse_ctrl_secreg_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .RSP(fuse_ctrl_secreg_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +)); + + `uvm_object_param_utils( fuse_ctrl_secreg_axi_read_in_sequence_base #( + AW, + DW, + IW, + UW + ) +) + + // variables + typedef fuse_ctrl_secreg_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + fuse_ctrl_secreg_axi_read_in_transaction_req_t; + fuse_ctrl_secreg_axi_read_in_transaction_req_t req; + typedef fuse_ctrl_secreg_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + fuse_ctrl_secreg_axi_read_in_transaction_rsp_t; + fuse_ctrl_secreg_axi_read_in_transaction_rsp_t rsp; + + // Event for identifying when a response was received from the sequencer + event new_rsp; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // TASK : get_responses() + // This task recursively gets sequence item responses from the sequencer. + // + virtual task get_responses(); + fork + begin + // Block until new rsp available + get_response(rsp); + // New rsp received. Indicate to sequence using event. + ->new_rsp; + // Display the received response transaction + `uvm_info("SEQ", {"New response transaction:",rsp.convert2string()}, UVM_MEDIUM) + end + join_none + endtask + + // **************************************************************************** + // TASK : pre_body() + // This task is called automatically when start is called with call_pre_post set to 1 (default). + // By calling get_responses() within pre_body() any derived sequences are automatically + // processing response transactions. Only un-comment this call to get_responses() if you + // have configured the interface driver to utilize the response transaction path by setting + // the configuration variable "return_transaction_response" to 1. Otherwise it is possible + // to impact runtime performance and memory utilization. + // + virtual task pre_body(); + // pragma uvmf custom pre_body begin +// get_responses(); + // pragma uvmf custom pre_body end + endtask + + // **************************************************************************** + // TASK : body() + // This task is called automatically when start is called. This sequence sends + // a req sequence item to the sequencer identified as an argument in the call + // to start. + // + virtual task body(); + // pragma uvmf custom body begin + start_item(req); + finish_item(req); + // pragma uvmf custom body end + endtask + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name =""); + super.new( name ); + // pragma uvmf custom new begin + req = fuse_ctrl_secreg_axi_read_in_transaction_req_t::type_id::create("req"); + rsp = fuse_ctrl_secreg_axi_read_in_transaction_rsp_t::type_id::create("rsp"); + // pragma uvmf custom new end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_transaction.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_transaction.svh new file mode 100644 index 0000000..7a2899a --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_transaction.svh @@ -0,0 +1,243 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class defines the variables required for an fuse_ctrl_secreg_axi_read_in +// transaction. Class variables to be displayed in waveform transaction +// viewing are added to the transaction viewing stream in the add_to_wave +// function. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_secreg_axi_read_in_transaction #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvmf_transaction_base; + + `uvm_object_param_utils( fuse_ctrl_secreg_axi_read_in_transaction #( + AW, + DW, + IW, + UW + ) +) + + rand logic [AW-1:0] secreg_araddr ; + logic secreg_arvalid ; + logic [$bits(axi_pkg::axi_burst_e)] secreg_arburst ; + logic [2:0] secreg_arsize ; + logic [7:0] secreg_arlen ; + logic [UW-1:0] secreg_aruser ; + logic [IW-1:0] secreg_arid ; + logic secreg_arlock ; + logic secreg_rready ; + + //Constraints for the transaction variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //******************************************************************* + //******************************************************************* + // Macros that define structs and associated functions are + // located in fuse_ctrl_secreg_axi_read_in_macros.svh + + //******************************************************************* + // Monitor macro used by fuse_ctrl_secreg_axi_read_in_monitor and fuse_ctrl_secreg_axi_read_in_monitor_bfm + // This struct is defined in fuse_ctrl_secreg_axi_read_in_macros.svh + `fuse_ctrl_secreg_axi_read_in_MONITOR_STRUCT + fuse_ctrl_secreg_axi_read_in_monitor_s fuse_ctrl_secreg_axi_read_in_monitor_struct; + //******************************************************************* + // FUNCTION: to_monitor_struct() + // This function packs transaction variables into a fuse_ctrl_secreg_axi_read_in_monitor_s + // structure. The function returns the handle to the fuse_ctrl_secreg_axi_read_in_monitor_struct. + // This function is defined in fuse_ctrl_secreg_axi_read_in_macros.svh + `fuse_ctrl_secreg_axi_read_in_TO_MONITOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_monitor_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_secreg_axi_read_in_macros.svh + `fuse_ctrl_secreg_axi_read_in_FROM_MONITOR_STRUCT_FUNCTION + + //******************************************************************* + // Initiator macro used by fuse_ctrl_secreg_axi_read_in_driver and fuse_ctrl_secreg_axi_read_in_driver_bfm + // to communicate initiator driven data to fuse_ctrl_secreg_axi_read_in_driver_bfm. + // This struct is defined in fuse_ctrl_secreg_axi_read_in_macros.svh + `fuse_ctrl_secreg_axi_read_in_INITIATOR_STRUCT + fuse_ctrl_secreg_axi_read_in_initiator_s fuse_ctrl_secreg_axi_read_in_initiator_struct; + //******************************************************************* + // FUNCTION: to_initiator_struct() + // This function packs transaction variables into a fuse_ctrl_secreg_axi_read_in_initiator_s + // structure. The function returns the handle to the fuse_ctrl_secreg_axi_read_in_initiator_struct. + // This function is defined in fuse_ctrl_secreg_axi_read_in_macros.svh + `fuse_ctrl_secreg_axi_read_in_TO_INITIATOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_initiator_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_secreg_axi_read_in_macros.svh + `fuse_ctrl_secreg_axi_read_in_FROM_INITIATOR_STRUCT_FUNCTION + + //******************************************************************* + // Responder macro used by fuse_ctrl_secreg_axi_read_in_driver and fuse_ctrl_secreg_axi_read_in_driver_bfm + // to communicate Responder driven data to fuse_ctrl_secreg_axi_read_in_driver_bfm. + // This struct is defined in fuse_ctrl_secreg_axi_read_in_macros.svh + `fuse_ctrl_secreg_axi_read_in_RESPONDER_STRUCT + fuse_ctrl_secreg_axi_read_in_responder_s fuse_ctrl_secreg_axi_read_in_responder_struct; + //******************************************************************* + // FUNCTION: to_responder_struct() + // This function packs transaction variables into a fuse_ctrl_secreg_axi_read_in_responder_s + // structure. The function returns the handle to the fuse_ctrl_secreg_axi_read_in_responder_struct. + // This function is defined in fuse_ctrl_secreg_axi_read_in_macros.svh + `fuse_ctrl_secreg_axi_read_in_TO_RESPONDER_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_responder_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_secreg_axi_read_in_macros.svh + `fuse_ctrl_secreg_axi_read_in_FROM_RESPONDER_STRUCT_FUNCTION + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + endfunction + + // **************************************************************************** + // FUNCTION: convert2string() + // This function converts all variables in this class to a single string for + // logfile reporting. + // + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + // UVMF_CHANGE_ME : Customize format if desired. + return $sformatf("secreg_araddr:0x%x secreg_arvalid:0x%x secreg_arburst:0x%x secreg_arsize:0x%x secreg_arlen:0x%x secreg_aruser:0x%x secreg_arid:0x%x secreg_arlock:0x%x secreg_rready:0x%x ",secreg_araddr,secreg_arvalid,secreg_arburst,secreg_arsize,secreg_arlen,secreg_aruser,secreg_arid,secreg_arlock,secreg_rready); + // pragma uvmf custom convert2string end + endfunction + + //******************************************************************* + // FUNCTION: do_print() + // This function is automatically called when the .print() function + // is called on this class. + // + virtual function void do_print(uvm_printer printer); + // pragma uvmf custom do_print begin + // UVMF_CHANGE_ME : Current contents of do_print allows for the use of UVM 1.1d, 1.2 or P1800.2. + // Update based on your own printing preference according to your preferred UVM version + $display(convert2string()); + // pragma uvmf custom do_print end + endfunction + + //******************************************************************* + // FUNCTION: do_compare() + // This function is automatically called when the .compare() function + // is called on this class. + // + virtual function bit do_compare (uvm_object rhs, uvm_comparer comparer); + fuse_ctrl_secreg_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + RHS; + if (!$cast(RHS,rhs)) return 0; + // pragma uvmf custom do_compare begin + // UVMF_CHANGE_ME : Eliminate comparison of variables not to be used for compare + return (super.do_compare(rhs,comparer) + ); + // pragma uvmf custom do_compare end + endfunction + + //******************************************************************* + // FUNCTION: do_copy() + // This function is automatically called when the .copy() function + // is called on this class. + // + virtual function void do_copy (uvm_object rhs); + fuse_ctrl_secreg_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + RHS; + assert($cast(RHS,rhs)); + // pragma uvmf custom do_copy begin + super.do_copy(rhs); + this.secreg_araddr = RHS.secreg_araddr; + this.secreg_arvalid = RHS.secreg_arvalid; + this.secreg_arburst = RHS.secreg_arburst; + this.secreg_arsize = RHS.secreg_arsize; + this.secreg_arlen = RHS.secreg_arlen; + this.secreg_aruser = RHS.secreg_aruser; + this.secreg_arid = RHS.secreg_arid; + this.secreg_arlock = RHS.secreg_arlock; + this.secreg_rready = RHS.secreg_rready; + // pragma uvmf custom do_copy end + endfunction + + // **************************************************************************** + // FUNCTION: add_to_wave() + // This function is used to display variables in this class in the waveform + // viewer. The start_time and end_time variables must be set before this + // function is called. If the start_time and end_time variables are not set + // the transaction will be hidden at 0ns on the waveform display. + // + virtual function void add_to_wave(int transaction_viewing_stream_h); + `ifdef QUESTA + if (transaction_view_h == 0) begin + transaction_view_h = $begin_transaction(transaction_viewing_stream_h,"fuse_ctrl_secreg_axi_read_in_transaction",start_time); + end + super.add_to_wave(transaction_view_h); + // pragma uvmf custom add_to_wave begin + // UVMF_CHANGE_ME : Color can be applied to transaction entries based on content, example below + // case() + // 1 : $add_color(transaction_view_h,"red"); + // default : $add_color(transaction_view_h,"grey"); + // endcase + // UVMF_CHANGE_ME : Eliminate transaction variables not wanted in transaction viewing in the waveform viewer + $add_attribute(transaction_view_h,secreg_araddr,"secreg_araddr"); + $add_attribute(transaction_view_h,secreg_arvalid,"secreg_arvalid"); + $add_attribute(transaction_view_h,secreg_arburst,"secreg_arburst"); + $add_attribute(transaction_view_h,secreg_arsize,"secreg_arsize"); + $add_attribute(transaction_view_h,secreg_arlen,"secreg_arlen"); + $add_attribute(transaction_view_h,secreg_aruser,"secreg_aruser"); + $add_attribute(transaction_view_h,secreg_arid,"secreg_arid"); + $add_attribute(transaction_view_h,secreg_arlock,"secreg_arlock"); + $add_attribute(transaction_view_h,secreg_rready,"secreg_rready"); + // pragma uvmf custom add_to_wave end + $end_transaction(transaction_view_h,end_time); + $free_transaction(transaction_view_h); + `endif // QUESTA + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_transaction_coverage.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_transaction_coverage.svh new file mode 100644 index 0000000..586b677 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_transaction_coverage.svh @@ -0,0 +1,110 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class records fuse_ctrl_secreg_axi_read_in transaction information using +// a covergroup named fuse_ctrl_secreg_axi_read_in_transaction_cg. An instance of this +// coverage component is instantiated in the uvmf_parameterized_agent +// if the has_coverage flag is set. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_secreg_axi_read_in_transaction_coverage #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvm_subscriber #(.T(fuse_ctrl_secreg_axi_read_in_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +)); + + `uvm_component_param_utils( fuse_ctrl_secreg_axi_read_in_transaction_coverage #( + AW, + DW, + IW, + UW + ) +) + + T coverage_trans; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + covergroup fuse_ctrl_secreg_axi_read_in_transaction_cg; + // pragma uvmf custom covergroup begin + // UVMF_CHANGE_ME : Add coverage bins, crosses, exclusions, etc. according to coverage needs. + option.auto_bin_max=1024; + option.per_instance=1; + secreg_araddr: coverpoint coverage_trans.secreg_araddr; + secreg_arvalid: coverpoint coverage_trans.secreg_arvalid; + secreg_arburst: coverpoint coverage_trans.secreg_arburst; + secreg_arsize: coverpoint coverage_trans.secreg_arsize; + secreg_arlen: coverpoint coverage_trans.secreg_arlen; + secreg_aruser: coverpoint coverage_trans.secreg_aruser; + secreg_arid: coverpoint coverage_trans.secreg_arid; + secreg_arlock: coverpoint coverage_trans.secreg_arlock; + secreg_rready: coverpoint coverage_trans.secreg_rready; + // pragma uvmf custom covergroup end + endgroup + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new(string name="", uvm_component parent=null); + super.new(name,parent); + fuse_ctrl_secreg_axi_read_in_transaction_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that transaction variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + endfunction + + // **************************************************************************** + // FUNCTION : build_phase() + // This function is the standard UVM build_phase. + // + function void build_phase(uvm_phase phase); + fuse_ctrl_secreg_axi_read_in_transaction_cg.set_inst_name($sformatf("fuse_ctrl_secreg_axi_read_in_transaction_cg_%s",get_full_name())); + endfunction + + // **************************************************************************** + // FUNCTION: write (T t) + // This function is automatically executed when a transaction arrives on the + // analysis_export. It copies values from the variables in the transaction + // to local variables used to collect functional coverage. + // + virtual function void write (T t); + `uvm_info("COV","Received transaction",UVM_HIGH); + coverage_trans = t; + fuse_ctrl_secreg_axi_read_in_transaction_cg.sample(); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_typedefs.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_typedefs.svh new file mode 100644 index 0000000..f2a7bdb --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_typedefs.svh @@ -0,0 +1,34 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the host server when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_typedefs_hdl.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_typedefs_hdl.svh new file mode 100644 index 0000000..0d58518 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/src/fuse_ctrl_secreg_axi_read_in_typedefs_hdl.svh @@ -0,0 +1,35 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the emulator when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/yaml/fuse_ctrl_secreg_axi_read_in_interface.yaml b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/yaml/fuse_ctrl_secreg_axi_read_in_interface.yaml new file mode 100644 index 0000000..a5ff8dd --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_in_pkg/yaml/fuse_ctrl_secreg_axi_read_in_interface.yaml @@ -0,0 +1,121 @@ +uvmf: + interfaces: + fuse_ctrl_secreg_axi_read_in: + clock: clk_i + config_constraints: [] + config_vars: [] + existing_library_component: 'True' + gen_inbound_streaming_driver: 'False' + hdl_pkg_parameters: [] + hdl_typedefs: [] + hvl_pkg_parameters: [] + hvl_typedefs: [] + parameters: + - name: AW + type: int + value: '32' + - name: DW + type: int + value: '32' + - name: IW + type: int + value: '3' + - name: UW + type: int + value: '32' + ports: + - dir: output + name: araddr + reset_value: '''bz' + width: '[''AW'']' + - dir: output + name: arburst + reset_value: '''bz' + width: '[''$bits(axi_pkg::axi_burst_e)'']' + - dir: output + name: arsize + reset_value: '''bz' + width: '3' + - dir: output + name: arlen + reset_value: '''bz' + width: '8' + - dir: output + name: aruser + reset_value: '''bz' + width: '[''UW'']' + - dir: output + name: arid + reset_value: '''bz' + width: '[''IW'']' + - dir: output + name: arlock + reset_value: '''bz' + width: '1' + - dir: output + name: arvalid + reset_value: '''bz' + width: '1' + - dir: output + name: rready + reset_value: '''bz' + width: '1' + reset: rst_ni + reset_assertion_level: 'False' + transaction_constraints: [] + transaction_vars: + - comment: '' + iscompare: 'False' + isrand: 'True' + name: secreg_araddr + type: logic [AW-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: secreg_arvalid + type: logic + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: secreg_arburst + type: logic [$bits(axi_pkg::axi_burst_e)] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: secreg_arsize + type: logic [2:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: secreg_arlen + type: logic [7:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: secreg_aruser + type: logic [UW-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: secreg_arid + type: logic [IW-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: secreg_arlock + type: logic + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: secreg_rready + type: logic + unpacked_dimension: '' + use_dpi_link: 'False' diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/.project b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/.project new file mode 100644 index 0000000..615ab14 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/.project @@ -0,0 +1,30 @@ + + + fuse_ctrl_secreg_axi_read_out_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/.svproject b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/.svproject new file mode 100644 index 0000000..9d45666 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/Makefile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/Makefile new file mode 100644 index 0000000..2b62709 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/Makefile @@ -0,0 +1,66 @@ +# fuse_ctrl_secreg_axi_read_out interface packages source +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +fuse_ctrl_secreg_axi_read_out_PKG = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_filelist_hvl.f + +fuse_ctrl_secreg_axi_read_out_PKG_HDL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_filelist_hdl.f + +fuse_ctrl_secreg_axi_read_out_PKG_XRTL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_filelist_xrtl.f + +COMP_fuse_ctrl_secreg_axi_read_out_PKG_TGT_0 = q_comp_fuse_ctrl_secreg_axi_read_out_pkg +COMP_fuse_ctrl_secreg_axi_read_out_PKG_TGT_1 = v_comp_fuse_ctrl_secreg_axi_read_out_pkg +COMP_fuse_ctrl_secreg_axi_read_out_PKG_TGT = $(COMP_fuse_ctrl_secreg_axi_read_out_PKG_TGT_$(USE_VELOCE)) + +comp_fuse_ctrl_secreg_axi_read_out_pkg: $(COMP_fuse_ctrl_secreg_axi_read_out_PKG_TGT) + +q_comp_fuse_ctrl_secreg_axi_read_out_pkg: + $(HDL_COMP_CMD) $(fuse_ctrl_secreg_axi_read_out_PKG_HDL) + $(HVL_COMP_CMD) $(fuse_ctrl_secreg_axi_read_out_PKG) + $(HDL_COMP_CMD) $(fuse_ctrl_secreg_axi_read_out_PKG_XRTL) + +v_comp_fuse_ctrl_secreg_axi_read_out_pkg: + $(HVL_COMP_CMD) $(fuse_ctrl_secreg_axi_read_out_PKG_HDL) + $(HVL_COMP_CMD) $(fuse_ctrl_secreg_axi_read_out_PKG) + $(VELANALYZE_CMD) $(fuse_ctrl_secreg_axi_read_out_PKG_HDL) + $(VELANALYZE_HVL_CMD) $(fuse_ctrl_secreg_axi_read_out_PKG) + $(HDL_COMP_CMD) $(fuse_ctrl_secreg_axi_read_out_PKG_XRTL) + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export fuse_ctrl_secreg_axi_read_out_IF_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/dpi + +C_FILE_COMPILE_LIST_fuse_ctrl_secreg_axi_read_out_pkg = \ + +O_FILE_COMPILE_LIST_fuse_ctrl_secreg_axi_read_out_pkg = $(notdir $(C_FILE_COMPILE_LIST_fuse_ctrl_secreg_axi_read_out_pkg:.c=.o)) + +GCC_COMP_ARGS_fuse_ctrl_secreg_axi_read_out_pkg += -I$(fuse_ctrl_secreg_axi_read_out_IF_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_fuse_ctrl_secreg_axi_read_out_pkg += $(fuse_ctrl_secreg_axi_read_out_IF_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_fuse_ctrl_secreg_axi_read_out_pkg += \ + \ + -o .so + +comp_fuse_ctrl_secreg_axi_read_out_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Interface C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_fuse_ctrl_secreg_axi_read_out_pkg) $(C_FILE_COMPILE_LIST_fuse_ctrl_secreg_axi_read_out_pkg) + @echo "--------------------------------" + @echo "Linking Interface C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_fuse_ctrl_secreg_axi_read_out_pkg) $(O_FILE_COMPILE_LIST_fuse_ctrl_secreg_axi_read_out_pkg) + @echo "--------------------------------" + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/compile.do b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/compile.do new file mode 100644 index 0000000..76aa3ca --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/compile.do @@ -0,0 +1,14 @@ +# Tcl do file for compile of fuse_ctrl_secreg_axi_read_out interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_filelist_hdl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_filelist_hvl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_filelist_xrtl.f \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out.compile new file mode 100644 index 0000000..630dad5 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out.compile @@ -0,0 +1,3 @@ +needs: + - fuse_ctrl_secreg_axi_read_out_hvl.compile + - fuse_ctrl_secreg_axi_read_out_hdl.compile diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_bfm.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_bfm.vinfo new file mode 100644 index 0000000..ecf711b --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_bfm.vinfo @@ -0,0 +1,6 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use fuse_ctrl_secreg_axi_read_out_pkg_hdl.vinfo ++incdir+@vinfodir +src/fuse_ctrl_secreg_axi_read_out_if.sv +src/fuse_ctrl_secreg_axi_read_out_driver_bfm.sv +src/fuse_ctrl_secreg_axi_read_out_monitor_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_common.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_common.compile new file mode 100644 index 0000000..ab88d14 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_common.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +incdir: + - . + - ${uvm_path}/src +src: + - fuse_ctrl_secreg_axi_read_out_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_filelist_hdl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_filelist_hdl.f new file mode 100644 index 0000000..5665d94 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_filelist_hdl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_filelist_hvl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_filelist_hvl.f new file mode 100644 index 0000000..dd6d2e7 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_filelist_hvl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_pkg.sv \ No newline at end of file diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_filelist_xrtl.f b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_filelist_xrtl.f new file mode 100644 index 0000000..39d2672 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_filelist_xrtl.f @@ -0,0 +1,3 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_if.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_monitor_bfm.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_driver_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_hdl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_hdl.compile new file mode 100644 index 0000000..7def000 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_hdl.compile @@ -0,0 +1,9 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ./fuse_ctrl_secreg_axi_read_out_common.compile +incdir: + - . +src: + - src/fuse_ctrl_secreg_axi_read_out_if.sv + - src/fuse_ctrl_secreg_axi_read_out_monitor_bfm.sv + - src/fuse_ctrl_secreg_axi_read_out_driver_bfm.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_hvl.compile b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_hvl.compile new file mode 100644 index 0000000..b4a074d --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_hvl.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ./fuse_ctrl_secreg_axi_read_out_common.compile +incdir: + - . +src: + - fuse_ctrl_secreg_axi_read_out_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_pkg.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_pkg.sv new file mode 100644 index 0000000..e5e0fb1 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_pkg.sv @@ -0,0 +1,91 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - + +// - +// - +// - + +// - +// - +// - + +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_secreg_axi_read_out_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg_hdl::*; + import uvmf_base_pkg::*; + import fuse_ctrl_secreg_axi_read_out_pkg_hdl::*; + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + `include "src/fuse_ctrl_secreg_axi_read_out_macros.svh" + + export fuse_ctrl_secreg_axi_read_out_pkg_hdl::*; + + + + // Parameters defined as HVL parameters + + `include "src/fuse_ctrl_secreg_axi_read_out_typedefs.svh" + `include "src/fuse_ctrl_secreg_axi_read_out_transaction.svh" + + `include "src/fuse_ctrl_secreg_axi_read_out_configuration.svh" + `include "src/fuse_ctrl_secreg_axi_read_out_driver.svh" + `include "src/fuse_ctrl_secreg_axi_read_out_monitor.svh" + + `include "src/fuse_ctrl_secreg_axi_read_out_transaction_coverage.svh" + `include "src/fuse_ctrl_secreg_axi_read_out_sequence_base.svh" + `include "src/fuse_ctrl_secreg_axi_read_out_random_sequence.svh" + + `include "src/fuse_ctrl_secreg_axi_read_out_responder_sequence.svh" + `include "src/fuse_ctrl_secreg_axi_read_out2reg_adapter.svh" + + `include "src/fuse_ctrl_secreg_axi_read_out_agent.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new interface sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the interface package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_pkg.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_pkg.vinfo new file mode 100644 index 0000000..fcfbb84 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_pkg.vinfo @@ -0,0 +1,4 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use fuse_ctrl_secreg_axi_read_out_pkg_hdl.vinfo ++incdir+@vinfodir +fuse_ctrl_secreg_axi_read_out_pkg.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_pkg_hdl.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_pkg_hdl.sv new file mode 100644 index 0000000..86bf6a5 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_pkg_hdl.sv @@ -0,0 +1,52 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that needs to be compiled and synthesized +// for running on Veloce. +// +// CONTAINS: +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package fuse_ctrl_secreg_axi_read_out_pkg_hdl; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HDL parameters + + `include "src/fuse_ctrl_secreg_axi_read_out_typedefs_hdl.svh" + `include "src/fuse_ctrl_secreg_axi_read_out_macros.svh" + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_pkg_hdl.vinfo b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_pkg_hdl.vinfo new file mode 100644 index 0000000..217e9f2 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_pkg_hdl.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +fuse_ctrl_secreg_axi_read_out_pkg_hdl.sv diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_pkg_sve.F b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_pkg_sve.F new file mode 100644 index 0000000..7feb9ad --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_pkg_sve.F @@ -0,0 +1,10 @@ +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + ++incdir+. +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_filelist_hdl.f +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/fuse_ctrl_secreg_axi_read_out_filelist_hvl.f diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out2reg_adapter.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out2reg_adapter.svh new file mode 100644 index 0000000..e96620f --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out2reg_adapter.svh @@ -0,0 +1,142 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the UVM register adapter for the fuse_ctrl_secreg_axi_read_out interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_secreg_axi_read_out2reg_adapter #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvm_reg_adapter; + + `uvm_object_param_utils( fuse_ctrl_secreg_axi_read_out2reg_adapter #( + AW, + DW, + IW, + UW + ) +) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //-------------------------------------------------------------------- + // new + //-------------------------------------------------------------------- + function new (string name = "fuse_ctrl_secreg_axi_read_out2reg_adapter" ); + super.new(name); + // pragma uvmf custom new begin + // UVMF_CHANGE_ME : Configure the adapter regarding byte enables and provides response. + + // Does the protocol the Agent is modeling support byte enables? + // 0 = NO + // 1 = YES + supports_byte_enable = 0; + + // Does the Agent's Driver provide separate response sequence items? + // i.e. Does the driver call seq_item_port.put() + // and do the sequences call get_response()? + // 0 = NO + // 1 = YES + provides_responses = 0; + // pragma uvmf custom new end + + endfunction: new + + //-------------------------------------------------------------------- + // reg2bus + //-------------------------------------------------------------------- + virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw); + + fuse_ctrl_secreg_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + trans_h = fuse_ctrl_secreg_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +::type_id::create("trans_h"); + + // pragma uvmf custom reg2bus begin + // UVMF_CHANGE_ME : Fill in the reg2bus adapter mapping registe fields to protocol fields. + + //Adapt the following for your sequence item type + // trans_h.op = (rw.kind == UVM_READ) ? WB_READ : WB_WRITE; + //Copy over address + // trans_h.addr = rw.addr; + //Copy over write data + // trans_h.data = rw.data; + + // pragma uvmf custom reg2bus end + + // Return the adapted transaction + return trans_h; + + endfunction: reg2bus + + //-------------------------------------------------------------------- + // bus2reg + //-------------------------------------------------------------------- + virtual function void bus2reg(uvm_sequence_item bus_item, + ref uvm_reg_bus_op rw); + fuse_ctrl_secreg_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + trans_h; + if (!$cast(trans_h, bus_item)) begin + `uvm_fatal("ADAPT","Provided bus_item is not of the correct type") + return; + end + // pragma uvmf custom bus2reg begin + // UVMF_CHANGE_ME : Fill in the bus2reg adapter mapping protocol fields to register fields. + //Adapt the following for your sequence item type + //Copy over instruction type + // rw.kind = (trans_h.op == WB_WRITE) ? UVM_WRITE : UVM_READ; + //Copy over address + // rw.addr = trans_h.addr; + //Copy over read data + // rw.data = trans_h.data; + //Check for errors on the bus and return UVM_NOT_OK if there is an error + // rw.status = UVM_IS_OK; + // pragma uvmf custom bus2reg end + + endfunction: bus2reg + +endclass : fuse_ctrl_secreg_axi_read_out2reg_adapter + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_agent.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_agent.svh new file mode 100644 index 0000000..8c136cf --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_agent.svh @@ -0,0 +1,109 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: Protocol specific agent class definition +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_secreg_axi_read_out_agent #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvmf_parameterized_agent #( + .CONFIG_T(fuse_ctrl_secreg_axi_read_out_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .DRIVER_T(fuse_ctrl_secreg_axi_read_out_driver #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .MONITOR_T(fuse_ctrl_secreg_axi_read_out_monitor #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .COVERAGE_T(fuse_ctrl_secreg_axi_read_out_transaction_coverage #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .TRANS_T(fuse_ctrl_secreg_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +) + ); + + `uvm_component_param_utils( fuse_ctrl_secreg_axi_read_out_agent #( + AW, + DW, + IW, + UW + ) +) + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** + // FUNCTION: build_phase + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + if (configuration.active_passive == ACTIVE) begin + // Place sequencer handle into configuration object + // so that it may be retrieved from configuration + // rather than using uvm_config_db + configuration.sequencer = this.sequencer; + end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_configuration.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_configuration.svh new file mode 100644 index 0000000..5660faa --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_configuration.svh @@ -0,0 +1,241 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class contains all variables and functions used +// to configure the fuse_ctrl_secreg_axi_read_out agent and its bfm's. It gets the +// bfm's from the uvm_config_db for use by the agent. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_secreg_axi_read_out_configuration #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvmf_parameterized_agent_configuration_base #( + .DRIVER_BFM_BIND_T(virtual fuse_ctrl_secreg_axi_read_out_driver_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .MONITOR_BFM_BIND_T( virtual fuse_ctrl_secreg_axi_read_out_monitor_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +)); + + `uvm_object_param_utils( fuse_ctrl_secreg_axi_read_out_configuration #( + AW, + DW, + IW, + UW + ) +) + + + // Sequencer handle populated by agent + uvm_sequencer #(fuse_ctrl_secreg_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + ) sequencer; + + //Constraints for the configuration variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + covergroup fuse_ctrl_secreg_axi_read_out_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + // pragma uvmf custom covergroup end + endgroup + + //******************************************************************* + //******************************************************************* + // Structure used to pass configuration variables to monitor and driver BFM's. + // Use to_struct function to pack variables into structure. + // Use from_struct function to unpack variables from structure. + // This structure is defined in fuse_ctrl_secreg_axi_read_out_macros.svh + `fuse_ctrl_secreg_axi_read_out_CONFIGURATION_STRUCT + fuse_ctrl_secreg_axi_read_out_configuration_s fuse_ctrl_secreg_axi_read_out_configuration_struct; + //******************************************************************* + // FUNCTION: to_struct() + // This function packs variables into a fuse_ctrl_secreg_axi_read_out_configuration_s + // structure. The function returns the handle to the fuse_ctrl_secreg_axi_read_out_configuration_struct. + // This function is defined in fuse_ctrl_secreg_axi_read_out_macros.svh + `fuse_ctrl_secreg_axi_read_out_CONFIGURATION_TO_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_struct() + // This function unpacks the struct provided as an argument into + // variables of this class. + // This function is defined in fuse_ctrl_secreg_axi_read_out_macros.svh + `fuse_ctrl_secreg_axi_read_out_CONFIGURATION_FROM_STRUCT_FUNCTION + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + // Construct the covergroup for this configuration class + fuse_ctrl_secreg_axi_read_out_configuration_cg = new; + endfunction + + // **************************************************************************** + // FUNCTION: post_randomize() + // This function is automatically called after the randomize() function + // is executed. + // + function void post_randomize(); + super.post_randomize(); + fuse_ctrl_secreg_axi_read_out_configuration_cg.sample(); + endfunction + + // **************************************************************************** + // FUNCTION: initialize + // This function causes the configuration to retrieve + // its virtual interface handle from the uvm_config_db. + // This function also makes itself available to its + // agent through the uvm_config_db. + // + // ARGUMENTS: + // uvmf_active_passive_t activity: + // This argument identifies the simulation level + // as either BLOCK, CHIP, SIMULATION, etc. + // + // AGENT_PATH: + // This argument identifies the path to this + // configurations agent. This configuration + // makes itself available to the agent specified + // by agent_path by placing itself into the + // uvm_config_db. + // + // INTERFACE_NAME: + // This argument identifies the string name of + // this configurations BFM's. This string + // name is used to retrieve the driver and + // monitor BFM from the uvm_config_db. + // + virtual function void initialize(uvmf_active_passive_t activity, + string agent_path, + string interface_name); + + super.initialize( activity, agent_path, interface_name); + // The covergroup is given the same name as the interface + fuse_ctrl_secreg_axi_read_out_configuration_cg.set_inst_name(interface_name); + + // This configuration places itself into the uvm_config_db for the agent, identified by the agent_path variable, to retrieve. + uvm_config_db #( fuse_ctrl_secreg_axi_read_out_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + + )::set( null ,agent_path,UVMF_AGENT_CONFIG, this ); + + // This configuration also places itself in the config db using the same identifier used by the interface. This allows users to access + // configuration variables and the interface through the bfm api class rather than directly accessing the BFM. This is useful for + // accessingthe BFM when using Veloce + uvm_config_db #( fuse_ctrl_secreg_axi_read_out_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + + )::set( null ,UVMF_CONFIGURATIONS, interface_name, this ); + + fuse_ctrl_secreg_axi_read_out_configuration_cg.set_inst_name($sformatf("fuse_ctrl_secreg_axi_read_out_configuration_cg_%s",get_full_name())); + +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. + `uvm_info("CFG", + $psprintf("The agent at '%s' is using interface named %s has the following parameters: AW=%x DW=%x IW=%x UW=%x ", agent_path, interface_name, AW ,DW ,IW ,UW ), + UVM_DEBUG) + + // pragma uvmf custom initialize begin + // This controls whether or not the agent returns a transaction handle in the driver when calling + // item_done() back into the sequencer or not. If set to 1, a transaction is sent back which means + // the sequence on the other end must use the get_response() part of the driver/sequence API. If + // this doesn't occur, there will eventually be response_queue overflow errors during the test. + return_transaction_response = 1'b0; + + // pragma uvmf custom initialize end + + endfunction + + // **************************************************************************** + // TASK: wait_for_reset + // *[Required]* Blocks until reset is released. The wait_for_reset operation is performed + // by a task in the monitor bfm. + virtual task wait_for_reset(); + monitor_bfm.wait_for_reset(); + endtask + + // **************************************************************************** + // TASK: wait_for_num_clocks + // *[Required]* Blocks until specified number of clocks have elapsed. The wait_for_num_clocks + // operation is performed by a task in the monitor bfm. + virtual task wait_for_num_clocks(int clocks); + monitor_bfm.wait_for_num_clocks(clocks); + endtask + + // **************************************************************************** + // FUNCTION : convert2string() + // This function is used to convert variables in this class into a string for log messaging. + // + virtual function string convert2string (); + // pragma uvmf custom convert2string begin + return $sformatf(""); + // pragma uvmf custom convert2string end + endfunction + + // **************************************************************************** + // FUNCTION: get_sequencer + function uvm_sequencer #(fuse_ctrl_secreg_axi_read_out_transaction#( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +) get_sequencer(); + return sequencer; + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_driver.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_driver.svh new file mode 100644 index 0000000..3902fe8 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_driver.svh @@ -0,0 +1,141 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class passes transactions between the sequencer +// and the BFM driver interface. It accesses the driver BFM +// through the bfm handle. This driver +// passes transactions to the driver BFM through the access +// task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_secreg_axi_read_out_driver #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvmf_driver_base #( + .CONFIG_T(fuse_ctrl_secreg_axi_read_out_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + ), + .BFM_BIND_T(virtual fuse_ctrl_secreg_axi_read_out_driver_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + ), + .REQ(fuse_ctrl_secreg_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + ), + .RSP(fuse_ctrl_secreg_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + )); + + `uvm_component_param_utils( fuse_ctrl_secreg_axi_read_out_driver #( + AW, + DW, + IW, + UW + ) +) +//******************************************************************* +// Macros that define structs located in fuse_ctrl_secreg_axi_read_out_macros.svh +//******************************************************************* +// Initiator macro used by fuse_ctrl_secreg_axi_read_out_driver and fuse_ctrl_secreg_axi_read_out_driver_bfm +// to communicate initiator driven data to fuse_ctrl_secreg_axi_read_out_driver_bfm. +`fuse_ctrl_secreg_axi_read_out_INITIATOR_STRUCT + fuse_ctrl_secreg_axi_read_out_initiator_s fuse_ctrl_secreg_axi_read_out_initiator_struct; +//******************************************************************* +// Responder macro used by fuse_ctrl_secreg_axi_read_out_driver and fuse_ctrl_secreg_axi_read_out_driver_bfm +// to communicate Responder driven data to fuse_ctrl_secreg_axi_read_out_driver_bfm. +`fuse_ctrl_secreg_axi_read_out_RESPONDER_STRUCT + fuse_ctrl_secreg_axi_read_out_responder_s fuse_ctrl_secreg_axi_read_out_responder_struct; + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent=null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the driver BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// driver BFM. This allows the driver BFM to call tasks and function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// **************************************************************************** +// This task is called by the run_phase in uvmf_driver_base. + virtual task access( inout REQ txn ); +// pragma uvmf custom access begin + if (configuration.initiator_responder==RESPONDER) begin + // Complete current transfer and wait for next transfer + bfm.respond_and_wait_for_next_transfer( + fuse_ctrl_secreg_axi_read_out_initiator_struct, + txn.to_responder_struct() + ); + // Unpack information about initiated transfer received by this responder + txn.from_initiator_struct(fuse_ctrl_secreg_axi_read_out_initiator_struct); + end else begin + // Initiate a transfer and get response + bfm.initiate_and_get_response( + txn.to_initiator_struct(), + fuse_ctrl_secreg_axi_read_out_responder_struct + ); + // Unpack transfer response information received by this initiator + txn.from_responder_struct(fuse_ctrl_secreg_axi_read_out_responder_struct); + end +// pragma uvmf custom access end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_driver_bfm.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_driver_bfm.sv new file mode 100644 index 0000000..3b1e0d5 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_driver_bfm.sv @@ -0,0 +1,352 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This interface performs the fuse_ctrl_secreg_axi_read_out signal driving. It is +// accessed by the uvm fuse_ctrl_secreg_axi_read_out driver through a virtual interface +// handle in the fuse_ctrl_secreg_axi_read_out configuration. It drives the singals passed +// in through the port connection named bus of type fuse_ctrl_secreg_axi_read_out_if. +// +// Input signals from the fuse_ctrl_secreg_axi_read_out_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// This bfm drives signals with a _o suffix. These signals +// are driven onto signals within fuse_ctrl_secreg_axi_read_out_if based on INITIATOR/RESPONDER and/or +// ARBITRATION/GRANT status. +// +// The output signal connections are as follows: +// signal_o -> bus.signal +// +// +// Interface functions and tasks used by UVM components: +// +// configure: +// This function gets configuration attributes from the +// UVM driver to set any required BFM configuration +// variables such as 'initiator_responder'. +// +// initiate_and_get_response: +// This task is used to perform signaling activity for initiating +// a protocol transfer. The task initiates the transfer, using +// input data from the initiator struct. Then the task captures +// response data, placing the data into the response struct. +// The response struct is returned to the driver class. +// +// respond_and_wait_for_next_transfer: +// This task is used to complete a current transfer as a responder +// and then wait for the initiator to start the next transfer. +// The task uses data in the responder struct to drive protocol +// signals to complete the transfer. The task then waits for +// the next transfer. Once the next transfer begins, data from +// the initiator is placed into the initiator struct and sent +// to the responder sequence for processing to determine +// what data to respond with. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_secreg_axi_read_out_pkg_hdl::*; +`include "src/fuse_ctrl_secreg_axi_read_out_macros.svh" + +interface fuse_ctrl_secreg_axi_read_out_driver_bfm #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + + (fuse_ctrl_secreg_axi_read_out_if bus); + // The following pragma and additional ones in-lined further below are for running this BFM on Veloce + // pragma attribute fuse_ctrl_secreg_axi_read_out_driver_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: AW=%x DW=%x IW=%x UW=%x ", AW,DW,IW,UW), + UVM_DEBUG) +end +`endif + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + tri clk_i_i; + tri rst_ni_i; + + // Signal list (all signals are capable of being inputs and outputs for the sake + // of supporting both INITIATOR and RESPONDER mode operation. Expectation is that + // directionality in the config file was from the point-of-view of the INITIATOR + + // INITIATOR mode input signals + tri arready_i; + reg arready_o = 'bz; + tri [DW-1:0] rdata_i; + reg [DW-1:0] rdata_o = 'bz; + tri rresp_i; + reg rresp_o = 'bz; + tri rid_i; + reg rid_o = 'bz; + tri rlast_i; + reg rlast_o = 'bz; + tri rvalid_i; + reg rvalid_o = 'bz; + + // INITIATOR mode output signals + + // Bi-directional signals + + + assign clk_i_i = bus.clk_i; + assign rst_ni_i = bus.rst_ni; + + // These are signals marked as 'input' by the config file, but the signals will be + // driven by this BFM if put into RESPONDER mode (flipping all signal directions around) + assign arready_i = bus.arready; + assign bus.arready = (initiator_responder == RESPONDER) ? arready_o : 'bz; + assign rdata_i = bus.rdata; + assign bus.rdata = (initiator_responder == RESPONDER) ? rdata_o : 'bz; + assign rresp_i = bus.rresp; + assign bus.rresp = (initiator_responder == RESPONDER) ? rresp_o : 'bz; + assign rid_i = bus.rid; + assign bus.rid = (initiator_responder == RESPONDER) ? rid_o : 'bz; + assign rlast_i = bus.rlast; + assign bus.rlast = (initiator_responder == RESPONDER) ? rlast_o : 'bz; + assign rvalid_i = bus.rvalid; + assign bus.rvalid = (initiator_responder == RESPONDER) ? rvalid_o : 'bz; + + + // These are signals marked as 'output' by the config file, but the outputs will + // not be driven by this BFM unless placed in INITIATOR mode. + + // Proxy handle to UVM driver + fuse_ctrl_secreg_axi_read_out_pkg::fuse_ctrl_secreg_axi_read_out_driver #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + proxy; + // pragma tbx oneway proxy.my_function_name_in_uvm_driver + + // **************************************************************************** + // **************************************************************************** + // Macros that define structs located in fuse_ctrl_secreg_axi_read_out_macros.svh + // **************************************************************************** + // Struct for passing configuration data from fuse_ctrl_secreg_axi_read_out_driver to this BFM + // **************************************************************************** + `fuse_ctrl_secreg_axi_read_out_CONFIGURATION_STRUCT + // **************************************************************************** + // Structs for INITIATOR and RESPONDER data flow + //******************************************************************* + // Initiator macro used by fuse_ctrl_secreg_axi_read_out_driver and fuse_ctrl_secreg_axi_read_out_driver_bfm + // to communicate initiator driven data to fuse_ctrl_secreg_axi_read_out_driver_bfm. + `fuse_ctrl_secreg_axi_read_out_INITIATOR_STRUCT + fuse_ctrl_secreg_axi_read_out_initiator_s initiator_struct; + // Responder macro used by fuse_ctrl_secreg_axi_read_out_driver and fuse_ctrl_secreg_axi_read_out_driver_bfm + // to communicate Responder driven data to fuse_ctrl_secreg_axi_read_out_driver_bfm. + `fuse_ctrl_secreg_axi_read_out_RESPONDER_STRUCT + fuse_ctrl_secreg_axi_read_out_responder_s responder_struct; + + // **************************************************************************** +// pragma uvmf custom reset_condition_and_response begin + // Always block used to return signals to reset value upon assertion of reset + always @( negedge rst_ni_i ) + begin + // RESPONDER mode output signals + arready_o <= 'bz; + rdata_o <= 'bz; + rresp_o <= 'bz; + rid_o <= 'bz; + rlast_o <= 'bz; + rvalid_o <= 'bz; + // INITIATOR mode output signals + // Bi-directional signals + + end +// pragma uvmf custom reset_condition_and_response end + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the driver BFM. It is called by the driver within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the driver BFM needs to be aware of the new configuration + // variables. + // + + function void configure(fuse_ctrl_secreg_axi_read_out_configuration_s fuse_ctrl_secreg_axi_read_out_configuration_arg); // pragma tbx xtf + initiator_responder = fuse_ctrl_secreg_axi_read_out_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + +// pragma uvmf custom initiate_and_get_response begin +// **************************************************************************** +// UVMF_CHANGE_ME +// This task is used by an initator. The task first initiates a transfer then +// waits for the responder to complete the transfer. + task initiate_and_get_response( + // This argument passes transaction variables used by an initiator + // to perform the initial part of a protocol transfer. The values + // come from a sequence item created in a sequence. + input fuse_ctrl_secreg_axi_read_out_initiator_s fuse_ctrl_secreg_axi_read_out_initiator_struct, + // This argument is used to send data received from the responder + // back to the sequence item. The sequence item is returned to the sequence. + output fuse_ctrl_secreg_axi_read_out_responder_s fuse_ctrl_secreg_axi_read_out_responder_struct + );// pragma tbx xtf + // + // Members within the fuse_ctrl_secreg_axi_read_out_initiator_struct: + // logic secreg_arready ; + // logic [DW-1:0] secreg_rdata ; + // axi_pkg::axi_burst_e secreg_rresp ; + // logic [IW-1:0] secreg_rid ; + // logic secreg_rlast ; + // logic secreg_rvalid ; + // Members within the fuse_ctrl_secreg_axi_read_out_responder_struct: + // logic secreg_arready ; + // logic [DW-1:0] secreg_rdata ; + // axi_pkg::axi_burst_e secreg_rresp ; + // logic [IW-1:0] secreg_rid ; + // logic secreg_rlast ; + // logic secreg_rvalid ; + initiator_struct = fuse_ctrl_secreg_axi_read_out_initiator_struct; + // + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clk_i_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available initiator input and inout signals listed. + // Initiator input signals + // fuse_ctrl_secreg_axi_read_out_responder_struct.xyz = arready_i; // + // fuse_ctrl_secreg_axi_read_out_responder_struct.xyz = rdata_i; // [DW-1:0] + // fuse_ctrl_secreg_axi_read_out_responder_struct.xyz = rresp_i; // + // fuse_ctrl_secreg_axi_read_out_responder_struct.xyz = rid_i; // + // fuse_ctrl_secreg_axi_read_out_responder_struct.xyz = rlast_i; // + // fuse_ctrl_secreg_axi_read_out_responder_struct.xyz = rvalid_i; // + // Initiator inout signals + // How to assign a signal from an initiator struct member named xyz. + // All available initiator output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Initiator output signals + // Initiator inout signals + // Initiate a transfer using the data received. + @(posedge clk_i_i); + @(posedge clk_i_i); + // Wait for the responder to complete the transfer then place the responder data into + // fuse_ctrl_secreg_axi_read_out_responder_struct. + @(posedge clk_i_i); + @(posedge clk_i_i); + responder_struct = fuse_ctrl_secreg_axi_read_out_responder_struct; + endtask +// pragma uvmf custom initiate_and_get_response end + +// pragma uvmf custom respond_and_wait_for_next_transfer begin +// **************************************************************************** +// The first_transfer variable is used to prevent completing a transfer in the +// first call to this task. For the first call to this task, there is not +// current transfer to complete. +bit first_transfer=1; + +// UVMF_CHANGE_ME +// This task is used by a responder. The task first completes the current +// transfer in progress then waits for the initiator to start the next transfer. + task respond_and_wait_for_next_transfer( + // This argument is used to send data received from the initiator + // back to the sequence item. The sequence determines how to respond. + output fuse_ctrl_secreg_axi_read_out_initiator_s fuse_ctrl_secreg_axi_read_out_initiator_struct, + // This argument passes transaction variables used by a responder + // to complete a protocol transfer. The values come from a sequence item. + input fuse_ctrl_secreg_axi_read_out_responder_s fuse_ctrl_secreg_axi_read_out_responder_struct + );// pragma tbx xtf + // Variables within the fuse_ctrl_secreg_axi_read_out_initiator_struct: + // logic secreg_arready ; + // logic [DW-1:0] secreg_rdata ; + // axi_pkg::axi_burst_e secreg_rresp ; + // logic [IW-1:0] secreg_rid ; + // logic secreg_rlast ; + // logic secreg_rvalid ; + // Variables within the fuse_ctrl_secreg_axi_read_out_responder_struct: + // logic secreg_arready ; + // logic [DW-1:0] secreg_rdata ; + // axi_pkg::axi_burst_e secreg_rresp ; + // logic [IW-1:0] secreg_rid ; + // logic secreg_rlast ; + // logic secreg_rvalid ; + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clk_i_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available responder input and inout signals listed. + // Responder input signals + // Responder inout signals + // How to assign a signal, named xyz, from an initiator struct member. + // All available responder output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Responder output signals + // arready_o <= fuse_ctrl_secreg_axi_read_out_initiator_struct.xyz; // + // rdata_o <= fuse_ctrl_secreg_axi_read_out_initiator_struct.xyz; // [DW-1:0] + // rresp_o <= fuse_ctrl_secreg_axi_read_out_initiator_struct.xyz; // + // rid_o <= fuse_ctrl_secreg_axi_read_out_initiator_struct.xyz; // + // rlast_o <= fuse_ctrl_secreg_axi_read_out_initiator_struct.xyz; // + // rvalid_o <= fuse_ctrl_secreg_axi_read_out_initiator_struct.xyz; // + // Responder inout signals + + @(posedge clk_i_i); + if (!first_transfer) begin + // Perform transfer response here. + // Reply using data recieved in the fuse_ctrl_secreg_axi_read_out_responder_struct. + @(posedge clk_i_i); + // Reply using data recieved in the transaction handle. + @(posedge clk_i_i); + end + // Wait for next transfer then gather info from intiator about the transfer. + // Place the data into the fuse_ctrl_secreg_axi_read_out_initiator_struct. + @(posedge clk_i_i); + @(posedge clk_i_i); + first_transfer = 0; + endtask +// pragma uvmf custom respond_and_wait_for_next_transfer end + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_if.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_if.sv new file mode 100644 index 0000000..08ee4ed --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_if.sv @@ -0,0 +1,109 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface contains the fuse_ctrl_secreg_axi_read_out interface signals. +// It is instantiated once per fuse_ctrl_secreg_axi_read_out bus. Bus Functional Models, +// BFM's named fuse_ctrl_secreg_axi_read_out_driver_bfm, are used to drive signals on the bus. +// BFM's named fuse_ctrl_secreg_axi_read_out_monitor_bfm are used to monitor signals on the +// bus. This interface signal bundle is passed in the port list of +// the BFM in order to give the BFM access to the signals in this +// interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// This template can be used to connect a DUT to these signals +// +// .dut_signal_port(fuse_ctrl_secreg_axi_read_out_bus.arready), // Agent input +// .dut_signal_port(fuse_ctrl_secreg_axi_read_out_bus.rdata), // Agent input +// .dut_signal_port(fuse_ctrl_secreg_axi_read_out_bus.rresp), // Agent input +// .dut_signal_port(fuse_ctrl_secreg_axi_read_out_bus.rid), // Agent input +// .dut_signal_port(fuse_ctrl_secreg_axi_read_out_bus.rlast), // Agent input +// .dut_signal_port(fuse_ctrl_secreg_axi_read_out_bus.rvalid), // Agent input + +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_secreg_axi_read_out_pkg_hdl::*; + +interface fuse_ctrl_secreg_axi_read_out_if #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + + + ( + input tri clk_i, + input tri rst_ni, + inout tri arready, + inout tri [DW-1:0] rdata, + inout tri rresp, + inout tri rid, + inout tri rlast, + inout tri rvalid + ); + +modport monitor_port + ( + input clk_i, + input rst_ni, + input arready, + input rdata, + input rresp, + input rid, + input rlast, + input rvalid + ); + +modport initiator_port + ( + input clk_i, + input rst_ni, + input arready, + input rdata, + input rresp, + input rid, + input rlast, + input rvalid + ); + +modport responder_port + ( + input clk_i, + input rst_ni, + output arready, + output rdata, + output rresp, + output rid, + output rlast, + output rvalid + ); + + +// pragma uvmf custom interface_item_additional begin +// pragma uvmf custom interface_item_additional end + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_infact_coverage_strategy.csv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_infact_coverage_strategy.csv new file mode 100644 index 0000000..1c218e1 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_infact_coverage_strategy.csv @@ -0,0 +1,6 @@ +Global +auto_bin_max, 64 + +Name,Type,Include +rand_fields,coverpoint,=rand *.** + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_macros.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_macros.svh new file mode 100644 index 0000000..882e661 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_macros.svh @@ -0,0 +1,180 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains macros used with the fuse_ctrl_secreg_axi_read_out package. +// These macros include packed struct definitions. These structs are +// used to pass data between classes, hvl, and BFM's, hdl. Use of +// structs are more efficient and simpler to modify. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_struct +// and from_struct methods defined in the macros below that are used in +// the fuse_ctrl_secreg_axi_read_out_configuration class. +// + `define fuse_ctrl_secreg_axi_read_out_CONFIGURATION_STRUCT \ +typedef struct packed { \ + uvmf_active_passive_t active_passive; \ + uvmf_initiator_responder_t initiator_responder; \ + } fuse_ctrl_secreg_axi_read_out_configuration_s; + + `define fuse_ctrl_secreg_axi_read_out_CONFIGURATION_TO_STRUCT_FUNCTION \ + virtual function fuse_ctrl_secreg_axi_read_out_configuration_s to_struct();\ + fuse_ctrl_secreg_axi_read_out_configuration_struct = \ + {\ + this.active_passive,\ + this.initiator_responder\ + };\ + return ( fuse_ctrl_secreg_axi_read_out_configuration_struct );\ + endfunction + + `define fuse_ctrl_secreg_axi_read_out_CONFIGURATION_FROM_STRUCT_FUNCTION \ + virtual function void from_struct(fuse_ctrl_secreg_axi_read_out_configuration_s fuse_ctrl_secreg_axi_read_out_configuration_struct);\ + {\ + this.active_passive,\ + this.initiator_responder \ + } = fuse_ctrl_secreg_axi_read_out_configuration_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_monitor_struct +// and from_monitor_struct methods of the fuse_ctrl_secreg_axi_read_out_transaction class. +// + `define fuse_ctrl_secreg_axi_read_out_MONITOR_STRUCT typedef struct packed { \ + logic secreg_arready ; \ + logic [DW-1:0] secreg_rdata ; \ + axi_pkg::axi_burst_e secreg_rresp ; \ + logic [IW-1:0] secreg_rid ; \ + logic secreg_rlast ; \ + logic secreg_rvalid ; \ + } fuse_ctrl_secreg_axi_read_out_monitor_s; + + `define fuse_ctrl_secreg_axi_read_out_TO_MONITOR_STRUCT_FUNCTION \ + virtual function fuse_ctrl_secreg_axi_read_out_monitor_s to_monitor_struct();\ + fuse_ctrl_secreg_axi_read_out_monitor_struct = \ + { \ + this.secreg_arready , \ + this.secreg_rdata , \ + this.secreg_rresp , \ + this.secreg_rid , \ + this.secreg_rlast , \ + this.secreg_rvalid \ + };\ + return ( fuse_ctrl_secreg_axi_read_out_monitor_struct);\ + endfunction\ + + `define fuse_ctrl_secreg_axi_read_out_FROM_MONITOR_STRUCT_FUNCTION \ + virtual function void from_monitor_struct(fuse_ctrl_secreg_axi_read_out_monitor_s fuse_ctrl_secreg_axi_read_out_monitor_struct);\ + {\ + this.secreg_arready , \ + this.secreg_rdata , \ + this.secreg_rresp , \ + this.secreg_rid , \ + this.secreg_rlast , \ + this.secreg_rvalid \ + } = fuse_ctrl_secreg_axi_read_out_monitor_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_initiator_struct +// and from_initiator_struct methods of the fuse_ctrl_secreg_axi_read_out_transaction class. +// Also update the comments in the driver BFM. +// + `define fuse_ctrl_secreg_axi_read_out_INITIATOR_STRUCT typedef struct packed { \ + logic secreg_arready ; \ + logic [DW-1:0] secreg_rdata ; \ + axi_pkg::axi_burst_e secreg_rresp ; \ + logic [IW-1:0] secreg_rid ; \ + logic secreg_rlast ; \ + logic secreg_rvalid ; \ + } fuse_ctrl_secreg_axi_read_out_initiator_s; + + `define fuse_ctrl_secreg_axi_read_out_TO_INITIATOR_STRUCT_FUNCTION \ + virtual function fuse_ctrl_secreg_axi_read_out_initiator_s to_initiator_struct();\ + fuse_ctrl_secreg_axi_read_out_initiator_struct = \ + {\ + this.secreg_arready , \ + this.secreg_rdata , \ + this.secreg_rresp , \ + this.secreg_rid , \ + this.secreg_rlast , \ + this.secreg_rvalid \ + };\ + return ( fuse_ctrl_secreg_axi_read_out_initiator_struct);\ + endfunction + + `define fuse_ctrl_secreg_axi_read_out_FROM_INITIATOR_STRUCT_FUNCTION \ + virtual function void from_initiator_struct(fuse_ctrl_secreg_axi_read_out_initiator_s fuse_ctrl_secreg_axi_read_out_initiator_struct);\ + {\ + this.secreg_arready , \ + this.secreg_rdata , \ + this.secreg_rresp , \ + this.secreg_rid , \ + this.secreg_rlast , \ + this.secreg_rvalid \ + } = fuse_ctrl_secreg_axi_read_out_initiator_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_responder_struct +// and from_responder_struct methods of the fuse_ctrl_secreg_axi_read_out_transaction class. +// Also update the comments in the driver BFM. +// + `define fuse_ctrl_secreg_axi_read_out_RESPONDER_STRUCT typedef struct packed { \ + logic secreg_arready ; \ + logic [DW-1:0] secreg_rdata ; \ + axi_pkg::axi_burst_e secreg_rresp ; \ + logic [IW-1:0] secreg_rid ; \ + logic secreg_rlast ; \ + logic secreg_rvalid ; \ + } fuse_ctrl_secreg_axi_read_out_responder_s; + + `define fuse_ctrl_secreg_axi_read_out_TO_RESPONDER_STRUCT_FUNCTION \ + virtual function fuse_ctrl_secreg_axi_read_out_responder_s to_responder_struct();\ + fuse_ctrl_secreg_axi_read_out_responder_struct = \ + {\ + this.secreg_arready , \ + this.secreg_rdata , \ + this.secreg_rresp , \ + this.secreg_rid , \ + this.secreg_rlast , \ + this.secreg_rvalid \ + };\ + return ( fuse_ctrl_secreg_axi_read_out_responder_struct);\ + endfunction + + `define fuse_ctrl_secreg_axi_read_out_FROM_RESPONDER_STRUCT_FUNCTION \ + virtual function void from_responder_struct(fuse_ctrl_secreg_axi_read_out_responder_s fuse_ctrl_secreg_axi_read_out_responder_struct);\ + {\ + this.secreg_arready , \ + this.secreg_rdata , \ + this.secreg_rresp , \ + this.secreg_rid , \ + this.secreg_rlast , \ + this.secreg_rvalid \ + } = fuse_ctrl_secreg_axi_read_out_responder_struct;\ + endfunction +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_monitor.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_monitor.svh new file mode 100644 index 0000000..8e4f463 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_monitor.svh @@ -0,0 +1,131 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class receives fuse_ctrl_secreg_axi_read_out transactions observed by the +// fuse_ctrl_secreg_axi_read_out monitor BFM and broadcasts them through the analysis port +// on the agent. It accesses the monitor BFM through the monitor +// task. This UVM component captures transactions +// for viewing in the waveform viewer if the +// enable_transaction_viewing flag is set in the configuration. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_secreg_axi_read_out_monitor #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvmf_monitor_base #( + .CONFIG_T(fuse_ctrl_secreg_axi_read_out_configuration #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .BFM_BIND_T(virtual fuse_ctrl_secreg_axi_read_out_monitor_bfm #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .TRANS_T(fuse_ctrl_secreg_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +)); + + `uvm_component_param_utils( fuse_ctrl_secreg_axi_read_out_monitor #( + AW, + DW, + IW, + UW + ) +) + +// Structure used to pass data from monitor BFM to monitor class in agent. +// Use to_monitor_struct function to pack transaction variables into structure. +// Use from_monitor_struct function to unpack transaction variables from structure. +`fuse_ctrl_secreg_axi_read_out_MONITOR_STRUCT + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the monitor BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// monitor BFM. This allows the monitor BFM to call the notify_transaction +// function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// *************************************************************************** + virtual task run_phase(uvm_phase phase); + // Start monitor BFM thread and don't call super.run() in order to + // override the default monitor proxy 'pull' behavior with the more + // emulation-friendly BFM 'push' approach using the notify_transaction + // function below + bfm.start_monitoring(); + endtask + +// ************************************************************************** + +// This function is called by the monitor BFM. It receives data observed by the +// monitor BFM. Data is passed using the fuse_ctrl_secreg_axi_read_out_monitor_struct. + virtual function void notify_transaction(input fuse_ctrl_secreg_axi_read_out_monitor_s fuse_ctrl_secreg_axi_read_out_monitor_struct); + + + trans = new("trans"); + trans.from_monitor_struct(fuse_ctrl_secreg_axi_read_out_monitor_struct); + trans.start_time = time_stamp; + trans.end_time = $time; + time_stamp = trans.end_time; + + analyze(trans); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_monitor_bfm.sv b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_monitor_bfm.sv new file mode 100644 index 0000000..744b715 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_monitor_bfm.sv @@ -0,0 +1,220 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface performs the fuse_ctrl_secreg_axi_read_out signal monitoring. +// It is accessed by the uvm fuse_ctrl_secreg_axi_read_out monitor through a virtual +// interface handle in the fuse_ctrl_secreg_axi_read_out configuration. It monitors the +// signals passed in through the port connection named bus of +// type fuse_ctrl_secreg_axi_read_out_if. +// +// Input signals from the fuse_ctrl_secreg_axi_read_out_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// Interface functions and tasks used by UVM components: +// monitor(inout TRANS_T txn); +// This task receives the transaction, txn, from the +// UVM monitor and then populates variables in txn +// from values observed on bus activity. This task +// blocks until an operation on the fuse_ctrl_secreg_axi_read_out bus is complete. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import fuse_ctrl_secreg_axi_read_out_pkg_hdl::*; +`include "src/fuse_ctrl_secreg_axi_read_out_macros.svh" + + +interface fuse_ctrl_secreg_axi_read_out_monitor_bfm #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + + ( fuse_ctrl_secreg_axi_read_out_if bus ); + // The pragma below and additional ones in-lined further down are for running this BFM on Veloce + // pragma attribute fuse_ctrl_secreg_axi_read_out_monitor_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: AW=%x DW=%x IW=%x UW=%x ", AW,DW,IW,UW), + UVM_DEBUG) +end +`endif + + + // Structure used to pass transaction data from monitor BFM to monitor class in agent. +`fuse_ctrl_secreg_axi_read_out_MONITOR_STRUCT + fuse_ctrl_secreg_axi_read_out_monitor_s fuse_ctrl_secreg_axi_read_out_monitor_struct; + + // Structure used to pass configuration data from monitor class to monitor BFM. + `fuse_ctrl_secreg_axi_read_out_CONFIGURATION_STRUCT + + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + tri clk_i_i; + tri rst_ni_i; + tri arready_i; + tri [DW-1:0] rdata_i; + tri rresp_i; + tri rid_i; + tri rlast_i; + tri rvalid_i; + assign clk_i_i = bus.clk_i; + assign rst_ni_i = bus.rst_ni; + assign arready_i = bus.arready; + assign rdata_i = bus.rdata; + assign rresp_i = bus.rresp; + assign rid_i = bus.rid; + assign rlast_i = bus.rlast; + assign rvalid_i = bus.rvalid; + + // Proxy handle to UVM monitor + fuse_ctrl_secreg_axi_read_out_pkg::fuse_ctrl_secreg_axi_read_out_monitor #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + proxy; + // pragma tbx oneway proxy.notify_transaction + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + task wait_for_reset();// pragma tbx xtf + @(posedge clk_i_i) ; + do_wait_for_reset(); + endtask + + // **************************************************************************** + task do_wait_for_reset(); + // pragma uvmf custom reset_condition begin + wait ( rst_ni_i === 1 ) ; + @(posedge clk_i_i) ; + // pragma uvmf custom reset_condition end + endtask + + //****************************************************************** + + task wait_for_num_clocks(input int unsigned count); // pragma tbx xtf + @(posedge clk_i_i); + + repeat (count-1) @(posedge clk_i_i); + endtask + + //****************************************************************** + event go; + function void start_monitoring();// pragma tbx xtf + -> go; + endfunction + + // **************************************************************************** + initial begin + @go; + forever begin + @(posedge clk_i_i); + do_monitor( fuse_ctrl_secreg_axi_read_out_monitor_struct ); + + + proxy.notify_transaction( fuse_ctrl_secreg_axi_read_out_monitor_struct ); + + end + end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the monitor BFM. It is called by the monitor within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the monitor BFM needs to be aware of the new configuration + // variables. + // + function void configure(fuse_ctrl_secreg_axi_read_out_configuration_s fuse_ctrl_secreg_axi_read_out_configuration_arg); // pragma tbx xtf + initiator_responder = fuse_ctrl_secreg_axi_read_out_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + + + // **************************************************************************** + + task do_monitor(output fuse_ctrl_secreg_axi_read_out_monitor_s fuse_ctrl_secreg_axi_read_out_monitor_struct); + // + // Available struct members: + // // fuse_ctrl_secreg_axi_read_out_monitor_struct.secreg_arready + // // fuse_ctrl_secreg_axi_read_out_monitor_struct.secreg_rdata + // // fuse_ctrl_secreg_axi_read_out_monitor_struct.secreg_rresp + // // fuse_ctrl_secreg_axi_read_out_monitor_struct.secreg_rid + // // fuse_ctrl_secreg_axi_read_out_monitor_struct.secreg_rlast + // // fuse_ctrl_secreg_axi_read_out_monitor_struct.secreg_rvalid + // // + // Reference code; + // How to wait for signal value + // while (control_signal === 1'b1) @(posedge clk_i_i); + // + // How to assign a struct member, named xyz, from a signal. + // All available input signals listed. + // fuse_ctrl_secreg_axi_read_out_monitor_struct.xyz = arready_i; // + // fuse_ctrl_secreg_axi_read_out_monitor_struct.xyz = rdata_i; // [DW-1:0] + // fuse_ctrl_secreg_axi_read_out_monitor_struct.xyz = rresp_i; // + // fuse_ctrl_secreg_axi_read_out_monitor_struct.xyz = rid_i; // + // fuse_ctrl_secreg_axi_read_out_monitor_struct.xyz = rlast_i; // + // fuse_ctrl_secreg_axi_read_out_monitor_struct.xyz = rvalid_i; // + // pragma uvmf custom do_monitor begin + // UVMF_CHANGE_ME : Implement protocol monitoring. The commented reference code + // below are examples of how to capture signal values and assign them to + // structure members. All available input signals are listed. The 'while' + // code example shows how to wait for a synchronous flow control signal. This + // task should return when a complete transfer has been observed. Once this task is + // exited with captured values, it is then called again to wait for and observe + // the next transfer. One clock cycle is consumed between calls to do_monitor. + @(posedge clk_i_i); + @(posedge clk_i_i); + @(posedge clk_i_i); + @(posedge clk_i_i); + // pragma uvmf custom do_monitor end + endtask + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_random_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_random_sequence.svh new file mode 100644 index 0000000..ff6541d --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_random_sequence.svh @@ -0,0 +1,91 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This sequences randomizes the fuse_ctrl_secreg_axi_read_out transaction and sends it +// to the UVM driver. +// +// This sequence constructs and randomizes a fuse_ctrl_secreg_axi_read_out_transaction. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_secreg_axi_read_out_random_sequence #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + + extends fuse_ctrl_secreg_axi_read_out_sequence_base #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +; + + `uvm_object_param_utils( fuse_ctrl_secreg_axi_read_out_random_sequence #( + AW, + DW, + IW, + UW + ) +) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //***************************************************************** + function new(string name = ""); + super.new(name); + endfunction: new + + // **************************************************************************** + // TASK : body() + // This task is automatically executed when this sequence is started using the + // start(sequencerHandle) task. + // + task body(); + + // Construct the transaction + req=fuse_ctrl_secreg_axi_read_out_transaction#( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +::type_id::create("req"); + start_item(req); + // Randomize the transaction + if(!req.randomize()) `uvm_fatal("SEQ", "fuse_ctrl_secreg_axi_read_out_random_sequence::body()-fuse_ctrl_secreg_axi_read_out_transaction randomization failed") + // Send the transaction to the fuse_ctrl_secreg_axi_read_out_driver_bfm via the sequencer and fuse_ctrl_secreg_axi_read_out_driver. + finish_item(req); + `uvm_info("SEQ", {"Response:",req.convert2string()},UVM_MEDIUM) + + endtask + +endclass: fuse_ctrl_secreg_axi_read_out_random_sequence + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_responder_sequence.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_responder_sequence.svh new file mode 100644 index 0000000..83a9996 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_responder_sequence.svh @@ -0,0 +1,87 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class can be used to provide stimulus when an interface +// has been configured to run in a responder mode. It +// will never finish by default, always going back to the driver +// and driver BFM for the next transaction with which to respond. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_secreg_axi_read_out_responder_sequence #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + + extends fuse_ctrl_secreg_axi_read_out_sequence_base #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +; + + `uvm_object_param_utils( fuse_ctrl_secreg_axi_read_out_responder_sequence #( + AW, + DW, + IW, + UW + ) +) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "fuse_ctrl_secreg_axi_read_out_responder_sequence"); + super.new(name); + endfunction + + task body(); + req=fuse_ctrl_secreg_axi_read_out_transaction#( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +::type_id::create("req"); + forever begin + start_item(req); + finish_item(req); + // pragma uvmf custom body begin + // UVMF_CHANGE_ME : Do something here with the resulting req item. The + // finish_item() call above will block until the req transaction is ready + // to be handled by the responder sequence. + // If this was an item that required a response, the expectation is + // that the response should be populated within this transaction now. + `uvm_info("SEQ",$sformatf("Processed txn: %s",req.convert2string()),UVM_HIGH) + // pragma uvmf custom body end + end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_sequence_base.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_sequence_base.svh new file mode 100644 index 0000000..30cb793 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_sequence_base.svh @@ -0,0 +1,146 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the class used as the base class for all sequences +// for this interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_secreg_axi_read_out_sequence_base #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvmf_sequence_base #( + .REQ(fuse_ctrl_secreg_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +), + .RSP(fuse_ctrl_secreg_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +)); + + `uvm_object_param_utils( fuse_ctrl_secreg_axi_read_out_sequence_base #( + AW, + DW, + IW, + UW + ) +) + + // variables + typedef fuse_ctrl_secreg_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + fuse_ctrl_secreg_axi_read_out_transaction_req_t; + fuse_ctrl_secreg_axi_read_out_transaction_req_t req; + typedef fuse_ctrl_secreg_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + fuse_ctrl_secreg_axi_read_out_transaction_rsp_t; + fuse_ctrl_secreg_axi_read_out_transaction_rsp_t rsp; + + // Event for identifying when a response was received from the sequencer + event new_rsp; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // TASK : get_responses() + // This task recursively gets sequence item responses from the sequencer. + // + virtual task get_responses(); + fork + begin + // Block until new rsp available + get_response(rsp); + // New rsp received. Indicate to sequence using event. + ->new_rsp; + // Display the received response transaction + `uvm_info("SEQ", {"New response transaction:",rsp.convert2string()}, UVM_MEDIUM) + end + join_none + endtask + + // **************************************************************************** + // TASK : pre_body() + // This task is called automatically when start is called with call_pre_post set to 1 (default). + // By calling get_responses() within pre_body() any derived sequences are automatically + // processing response transactions. Only un-comment this call to get_responses() if you + // have configured the interface driver to utilize the response transaction path by setting + // the configuration variable "return_transaction_response" to 1. Otherwise it is possible + // to impact runtime performance and memory utilization. + // + virtual task pre_body(); + // pragma uvmf custom pre_body begin +// get_responses(); + // pragma uvmf custom pre_body end + endtask + + // **************************************************************************** + // TASK : body() + // This task is called automatically when start is called. This sequence sends + // a req sequence item to the sequencer identified as an argument in the call + // to start. + // + virtual task body(); + // pragma uvmf custom body begin + start_item(req); + finish_item(req); + // pragma uvmf custom body end + endtask + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name =""); + super.new( name ); + // pragma uvmf custom new begin + req = fuse_ctrl_secreg_axi_read_out_transaction_req_t::type_id::create("req"); + rsp = fuse_ctrl_secreg_axi_read_out_transaction_rsp_t::type_id::create("rsp"); + // pragma uvmf custom new end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_transaction.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_transaction.svh new file mode 100644 index 0000000..b36b950 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_transaction.svh @@ -0,0 +1,240 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class defines the variables required for an fuse_ctrl_secreg_axi_read_out +// transaction. Class variables to be displayed in waveform transaction +// viewing are added to the transaction viewing stream in the add_to_wave +// function. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_secreg_axi_read_out_transaction #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvmf_transaction_base; + + `uvm_object_param_utils( fuse_ctrl_secreg_axi_read_out_transaction #( + AW, + DW, + IW, + UW + ) +) + + logic secreg_arready ; + logic [DW-1:0] secreg_rdata ; + axi_pkg::axi_burst_e secreg_rresp ; + logic [IW-1:0] secreg_rid ; + logic secreg_rlast ; + logic secreg_rvalid ; + + //Constraints for the transaction variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //******************************************************************* + //******************************************************************* + // Macros that define structs and associated functions are + // located in fuse_ctrl_secreg_axi_read_out_macros.svh + + //******************************************************************* + // Monitor macro used by fuse_ctrl_secreg_axi_read_out_monitor and fuse_ctrl_secreg_axi_read_out_monitor_bfm + // This struct is defined in fuse_ctrl_secreg_axi_read_out_macros.svh + `fuse_ctrl_secreg_axi_read_out_MONITOR_STRUCT + fuse_ctrl_secreg_axi_read_out_monitor_s fuse_ctrl_secreg_axi_read_out_monitor_struct; + //******************************************************************* + // FUNCTION: to_monitor_struct() + // This function packs transaction variables into a fuse_ctrl_secreg_axi_read_out_monitor_s + // structure. The function returns the handle to the fuse_ctrl_secreg_axi_read_out_monitor_struct. + // This function is defined in fuse_ctrl_secreg_axi_read_out_macros.svh + `fuse_ctrl_secreg_axi_read_out_TO_MONITOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_monitor_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_secreg_axi_read_out_macros.svh + `fuse_ctrl_secreg_axi_read_out_FROM_MONITOR_STRUCT_FUNCTION + + //******************************************************************* + // Initiator macro used by fuse_ctrl_secreg_axi_read_out_driver and fuse_ctrl_secreg_axi_read_out_driver_bfm + // to communicate initiator driven data to fuse_ctrl_secreg_axi_read_out_driver_bfm. + // This struct is defined in fuse_ctrl_secreg_axi_read_out_macros.svh + `fuse_ctrl_secreg_axi_read_out_INITIATOR_STRUCT + fuse_ctrl_secreg_axi_read_out_initiator_s fuse_ctrl_secreg_axi_read_out_initiator_struct; + //******************************************************************* + // FUNCTION: to_initiator_struct() + // This function packs transaction variables into a fuse_ctrl_secreg_axi_read_out_initiator_s + // structure. The function returns the handle to the fuse_ctrl_secreg_axi_read_out_initiator_struct. + // This function is defined in fuse_ctrl_secreg_axi_read_out_macros.svh + `fuse_ctrl_secreg_axi_read_out_TO_INITIATOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_initiator_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_secreg_axi_read_out_macros.svh + `fuse_ctrl_secreg_axi_read_out_FROM_INITIATOR_STRUCT_FUNCTION + + //******************************************************************* + // Responder macro used by fuse_ctrl_secreg_axi_read_out_driver and fuse_ctrl_secreg_axi_read_out_driver_bfm + // to communicate Responder driven data to fuse_ctrl_secreg_axi_read_out_driver_bfm. + // This struct is defined in fuse_ctrl_secreg_axi_read_out_macros.svh + `fuse_ctrl_secreg_axi_read_out_RESPONDER_STRUCT + fuse_ctrl_secreg_axi_read_out_responder_s fuse_ctrl_secreg_axi_read_out_responder_struct; + //******************************************************************* + // FUNCTION: to_responder_struct() + // This function packs transaction variables into a fuse_ctrl_secreg_axi_read_out_responder_s + // structure. The function returns the handle to the fuse_ctrl_secreg_axi_read_out_responder_struct. + // This function is defined in fuse_ctrl_secreg_axi_read_out_macros.svh + `fuse_ctrl_secreg_axi_read_out_TO_RESPONDER_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_responder_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in fuse_ctrl_secreg_axi_read_out_macros.svh + `fuse_ctrl_secreg_axi_read_out_FROM_RESPONDER_STRUCT_FUNCTION + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + endfunction + + // **************************************************************************** + // FUNCTION: convert2string() + // This function converts all variables in this class to a single string for + // logfile reporting. + // + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + // UVMF_CHANGE_ME : Customize format if desired. + return $sformatf("secreg_arready:0x%x secreg_rdata:0x%x secreg_rresp:0x%x secreg_rid:0x%x secreg_rlast:0x%x secreg_rvalid:0x%x ",secreg_arready,secreg_rdata,secreg_rresp,secreg_rid,secreg_rlast,secreg_rvalid); + // pragma uvmf custom convert2string end + endfunction + + //******************************************************************* + // FUNCTION: do_print() + // This function is automatically called when the .print() function + // is called on this class. + // + virtual function void do_print(uvm_printer printer); + // pragma uvmf custom do_print begin + // UVMF_CHANGE_ME : Current contents of do_print allows for the use of UVM 1.1d, 1.2 or P1800.2. + // Update based on your own printing preference according to your preferred UVM version + $display(convert2string()); + // pragma uvmf custom do_print end + endfunction + + //******************************************************************* + // FUNCTION: do_compare() + // This function is automatically called when the .compare() function + // is called on this class. + // + virtual function bit do_compare (uvm_object rhs, uvm_comparer comparer); + fuse_ctrl_secreg_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + RHS; + if (!$cast(RHS,rhs)) return 0; + // pragma uvmf custom do_compare begin + // UVMF_CHANGE_ME : Eliminate comparison of variables not to be used for compare + return (super.do_compare(rhs,comparer) + &&(this.secreg_arready == RHS.secreg_arready) + &&(this.secreg_rdata == RHS.secreg_rdata) + &&(this.secreg_rresp == RHS.secreg_rresp) + &&(this.secreg_rid == RHS.secreg_rid) + &&(this.secreg_rlast == RHS.secreg_rlast) + &&(this.secreg_rvalid == RHS.secreg_rvalid) + ); + // pragma uvmf custom do_compare end + endfunction + + //******************************************************************* + // FUNCTION: do_copy() + // This function is automatically called when the .copy() function + // is called on this class. + // + virtual function void do_copy (uvm_object rhs); + fuse_ctrl_secreg_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) + RHS; + assert($cast(RHS,rhs)); + // pragma uvmf custom do_copy begin + super.do_copy(rhs); + this.secreg_arready = RHS.secreg_arready; + this.secreg_rdata = RHS.secreg_rdata; + this.secreg_rresp = RHS.secreg_rresp; + this.secreg_rid = RHS.secreg_rid; + this.secreg_rlast = RHS.secreg_rlast; + this.secreg_rvalid = RHS.secreg_rvalid; + // pragma uvmf custom do_copy end + endfunction + + // **************************************************************************** + // FUNCTION: add_to_wave() + // This function is used to display variables in this class in the waveform + // viewer. The start_time and end_time variables must be set before this + // function is called. If the start_time and end_time variables are not set + // the transaction will be hidden at 0ns on the waveform display. + // + virtual function void add_to_wave(int transaction_viewing_stream_h); + `ifdef QUESTA + if (transaction_view_h == 0) begin + transaction_view_h = $begin_transaction(transaction_viewing_stream_h,"fuse_ctrl_secreg_axi_read_out_transaction",start_time); + end + super.add_to_wave(transaction_view_h); + // pragma uvmf custom add_to_wave begin + // UVMF_CHANGE_ME : Color can be applied to transaction entries based on content, example below + // case() + // 1 : $add_color(transaction_view_h,"red"); + // default : $add_color(transaction_view_h,"grey"); + // endcase + // UVMF_CHANGE_ME : Eliminate transaction variables not wanted in transaction viewing in the waveform viewer + $add_attribute(transaction_view_h,secreg_arready,"secreg_arready"); + $add_attribute(transaction_view_h,secreg_rdata,"secreg_rdata"); + $add_attribute(transaction_view_h,secreg_rresp,"secreg_rresp"); + $add_attribute(transaction_view_h,secreg_rid,"secreg_rid"); + $add_attribute(transaction_view_h,secreg_rlast,"secreg_rlast"); + $add_attribute(transaction_view_h,secreg_rvalid,"secreg_rvalid"); + // pragma uvmf custom add_to_wave end + $end_transaction(transaction_view_h,end_time); + $free_transaction(transaction_view_h); + `endif // QUESTA + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_transaction_coverage.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_transaction_coverage.svh new file mode 100644 index 0000000..cdbf4e2 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_transaction_coverage.svh @@ -0,0 +1,107 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class records fuse_ctrl_secreg_axi_read_out transaction information using +// a covergroup named fuse_ctrl_secreg_axi_read_out_transaction_cg. An instance of this +// coverage component is instantiated in the uvmf_parameterized_agent +// if the has_coverage flag is set. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class fuse_ctrl_secreg_axi_read_out_transaction_coverage #( + int AW = 32, + int DW = 32, + int IW = 3, + int UW = 32 + ) + extends uvm_subscriber #(.T(fuse_ctrl_secreg_axi_read_out_transaction #( + .AW(AW), + .DW(DW), + .IW(IW), + .UW(UW) + ) +)); + + `uvm_component_param_utils( fuse_ctrl_secreg_axi_read_out_transaction_coverage #( + AW, + DW, + IW, + UW + ) +) + + T coverage_trans; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + covergroup fuse_ctrl_secreg_axi_read_out_transaction_cg; + // pragma uvmf custom covergroup begin + // UVMF_CHANGE_ME : Add coverage bins, crosses, exclusions, etc. according to coverage needs. + option.auto_bin_max=1024; + option.per_instance=1; + secreg_arready: coverpoint coverage_trans.secreg_arready; + secreg_rdata: coverpoint coverage_trans.secreg_rdata; + secreg_rresp: coverpoint coverage_trans.secreg_rresp; + secreg_rid: coverpoint coverage_trans.secreg_rid; + secreg_rlast: coverpoint coverage_trans.secreg_rlast; + secreg_rvalid: coverpoint coverage_trans.secreg_rvalid; + // pragma uvmf custom covergroup end + endgroup + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new(string name="", uvm_component parent=null); + super.new(name,parent); + fuse_ctrl_secreg_axi_read_out_transaction_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that transaction variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + endfunction + + // **************************************************************************** + // FUNCTION : build_phase() + // This function is the standard UVM build_phase. + // + function void build_phase(uvm_phase phase); + fuse_ctrl_secreg_axi_read_out_transaction_cg.set_inst_name($sformatf("fuse_ctrl_secreg_axi_read_out_transaction_cg_%s",get_full_name())); + endfunction + + // **************************************************************************** + // FUNCTION: write (T t) + // This function is automatically executed when a transaction arrives on the + // analysis_export. It copies values from the variables in the transaction + // to local variables used to collect functional coverage. + // + virtual function void write (T t); + `uvm_info("COV","Received transaction",UVM_HIGH); + coverage_trans = t; + fuse_ctrl_secreg_axi_read_out_transaction_cg.sample(); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_typedefs.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_typedefs.svh new file mode 100644 index 0000000..f2a7bdb --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_typedefs.svh @@ -0,0 +1,34 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the host server when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_typedefs_hdl.svh b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_typedefs_hdl.svh new file mode 100644 index 0000000..0d58518 --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/src/fuse_ctrl_secreg_axi_read_out_typedefs_hdl.svh @@ -0,0 +1,35 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the emulator when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/yaml/fuse_ctrl_secreg_axi_read_out_interface.yaml b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/yaml/fuse_ctrl_secreg_axi_read_out_interface.yaml new file mode 100644 index 0000000..a0081ff --- /dev/null +++ b/src/fuse_ctrl/uvmf_fuse_ctrl/uvmf_template_output_bak/verification_ip/interface_packages/fuse_ctrl_secreg_axi_read_out_pkg/yaml/fuse_ctrl_secreg_axi_read_out_interface.yaml @@ -0,0 +1,91 @@ +uvmf: + interfaces: + fuse_ctrl_secreg_axi_read_out: + clock: clk_i + config_constraints: [] + config_vars: [] + existing_library_component: 'True' + gen_inbound_streaming_driver: 'False' + hdl_pkg_parameters: [] + hdl_typedefs: [] + hvl_pkg_parameters: [] + hvl_typedefs: [] + parameters: + - name: AW + type: int + value: '32' + - name: DW + type: int + value: '32' + - name: IW + type: int + value: '3' + - name: UW + type: int + value: '32' + ports: + - dir: input + name: arready + reset_value: '''bz' + width: '1' + - dir: input + name: rdata + reset_value: '''bz' + width: DW + - dir: input + name: rresp + reset_value: '''bz' + width: '1' + - dir: input + name: rid + reset_value: '''bz' + width: '1' + - dir: input + name: rlast + reset_value: '''bz' + width: '1' + - dir: input + name: rvalid + reset_value: '''bz' + width: '1' + reset: rst_ni + reset_assertion_level: 'False' + transaction_constraints: [] + transaction_vars: + - comment: '' + iscompare: 'True' + isrand: 'False' + name: secreg_arready + type: logic + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'False' + name: secreg_rdata + type: logic [DW-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'False' + name: secreg_rresp + type: axi_pkg::axi_burst_e + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'False' + name: secreg_rid + type: logic [IW-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'False' + name: secreg_rlast + type: logic + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'False' + name: secreg_rvalid + type: logic + unpacked_dimension: '' + use_dpi_link: 'False' diff --git a/src/integration/config/compile.yml b/src/integration/config/compile.yml index f4d4e78..ffa6faf 100644 --- a/src/integration/config/compile.yml +++ b/src/integration/config/compile.yml @@ -1,9 +1,13 @@ provides: [caliptra_ss_top] schema_version: 2.4.0 requires: + - caliptra_ss_lc_ctrl_pkg - mcu_top - css_mcu0_veer_el2_rtl_pkg - i3c-core + - tlul_pkg + - fuse_ctrl_pkg + - fuse_ctrl - caliptra_top_tb_pkg targets: tb: @@ -13,6 +17,7 @@ targets: - $AVERY_HOME/axixactor-2.1e.230314//src.axi - $AVERY_HOME/axixactor-2.1e.230314//checker/BP063-BU-01000-r0p1-00rel0/sva - $AVERY_HOME/axixactor-2.1e.230314//testbench + - $COMPILE_ROOT/testbench files: # - $COMPILE_ROOT/../../../../chipsalliance/caliptra-rtl/src/axi/rtl/caliptra_axi_sram.sv - $AVERY_HOME/axixactor-2.1e.230314//src/avery_pkg.sv @@ -24,8 +29,10 @@ targets: - $AVERY_HOME/axixactor-2.1e.230314//src.axi/aaxi_intf.sv - $COMPILE_ROOT/testbench/tb_top_pkg.sv - $COMPILE_ROOT/testbench/axi_slv.sv - - $COMPILE_ROOT/testbench/dasm.svi + # - $COMPILE_ROOT/testbench/dasm.svi + - $COMPILE_ROOT/testbench/aaxi_pkg_caliptra_test.sv - $COMPILE_ROOT/testbench/aaxi4_interconnect.sv + - $COMPILE_ROOT/testbench/fuse_ctrl_bfm.sv - $COMPILE_ROOT/testbench/caliptra_ss_top.sv tops: [caliptra_ss_top] sim: @@ -41,6 +48,7 @@ global: default: - '-assert svaext' - '-sverilog -full64' + - '-debug_access+all' # Used in caliptra_top_sva to find signals - +define+CPTRA_TB_TOP_NAME=caliptra_ss_top - +define+CPTRA_TOP_PATH=caliptra_ss_top.caliptra_top_dut @@ -58,7 +66,7 @@ global: - +define+CALIPTRA_INTERNAL_UART - '-noinherit_timescale=1ns/1ps' - +define+AAXI_INTC_MASTER_CNT=5 - - +define+AAXI_INTC_SLAVE_CNT=5 + - +define+AAXI_INTC_SLAVE_CNT=7 - '$AVERY_PLI/lib.linux/libtb_vcs64.a' - '-P $AVERY_PLI/tb_vcs64.tab' elab: diff --git a/src/integration/rtl/fuse_ctrl_address_map.h b/src/integration/rtl/fuse_ctrl_address_map.h new file mode 100644 index 0000000..dde7d51 --- /dev/null +++ b/src/integration/rtl/fuse_ctrl_address_map.h @@ -0,0 +1,135 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +#ifndef FUSE_CTRL_ADDRMAP_HEADER +#define FUSE_CTRL_ADDRMAP_HEADER + +#define FUSE_CTRL_BASE_ADDR (0x50000000) +#define FUSE_CTRL_INTR_STATE (0x50000000) +#define FUSE_CTRL_INTR_ENABLE (0x50000004) +#define FUSE_CTRL_INTR_TEST (0x50000008) +#define FUSE_CTRL_ALERT_TEST (0x5000000C) +#define FUSE_CTRL_STATUS (0x50000010) +#define FUSE_CTRL_ERR_CODE_0 (0x50000014) +#define FUSE_CTRL_ERR_CODE_1 (0x50000018) +#define FUSE_CTRL_ERR_CODE_2 (0x5000001C) +#define FUSE_CTRL_ERR_CODE_3 (0x50000020) +#define FUSE_CTRL_ERR_CODE_4 (0x50000024) +#define FUSE_CTRL_ERR_CODE_5 (0x50000028) +#define FUSE_CTRL_ERR_CODE_6 (0x5000002C) +#define FUSE_CTRL_ERR_CODE_7 (0x50000030) +#define FUSE_CTRL_ERR_CODE_8 (0x50000034) +#define FUSE_CTRL_ERR_CODE_9 (0x50000038) +#define FUSE_CTRL_ERR_CODE_10 (0x5000003C) +#define FUSE_CTRL_ERR_CODE_11 (0x50000040) +#define FUSE_CTRL_ERR_CODE_12 (0x50000044) +#define FUSE_CTRL_DIRECT_ACCESS_REGWEN (0x50000048) +#define FUSE_CTRL_DIRECT_ACCESS_CMD (0x5000004C) +#define FUSE_CTRL_DIRECT_ACCESS_ADDRESS (0x50000050) +#define FUSE_CTRL_DIRECT_ACCESS_WDATA_0 (0x50000054) +#define FUSE_CTRL_DIRECT_ACCESS_WDATA_1 (0x50000058) +#define FUSE_CTRL_DIRECT_ACCESS_RDATA_0 (0x5000005C) +#define FUSE_CTRL_DIRECT_ACCESS_RDATA_1 (0x50000060) +#define FUSE_CTRL_CHECK_TRIGGER_REGWEN (0x50000064) +#define FUSE_CTRL_CHECK_TRIGGER (0x50000068) +#define FUSE_CTRL_CHECK_REGWEN (0x5000006C) +#define FUSE_CTRL_CHECK_TIMEOUT (0x50000070) +#define FUSE_CTRL_INTEGRITY_CHECK_PERIOD (0x50000074) +#define FUSE_CTRL_CONSISTENCY_CHECK_PERIOD (0x50000078) +#define FUSE_CTRL_VENDOR_TEST_READ_LOCK (0x5000007C) +#define FUSE_CTRL_CREATOR_SW_CFG_READ_LOCK (0x50000080) +#define FUSE_CTRL_OWNER_SW_CFG_READ_LOCK (0x50000084) +#define FUSE_CTRL_ROT_CREATOR_AUTH_CODESIGN_READ_LOCK (0x50000088) +#define FUSE_CTRL_ROT_CREATOR_AUTH_STATE_READ_LOCK (0x5000008C) +#define FUSE_CTRL_VENDOR_TEST_DIGEST_0 (0x50000090) +#define FUSE_CTRL_VENDOR_TEST_DIGEST_1 (0x50000094) +#define FUSE_CTRL_CREATOR_SW_CFG_DIGEST_0 (0x50000098) +#define FUSE_CTRL_CREATOR_SW_CFG_DIGEST_1 (0x5000009C) +#define FUSE_CTRL_OWNER_SW_CFG_DIGEST_0 (0x500000A0) +#define FUSE_CTRL_OWNER_SW_CFG_DIGEST_1 (0x500000A4) +#define FUSE_CTRL_ROT_CREATOR_AUTH_CODESIGN_DIGEST_0 (0x500000A8) +#define FUSE_CTRL_ROT_CREATOR_AUTH_CODESIGN_DIGEST_1 (0x500000AC) +#define FUSE_CTRL_ROT_CREATOR_AUTH_STATE_DIGEST_0 (0x500000B0) +#define FUSE_CTRL_ROT_CREATOR_AUTH_STATE_DIGEST_1 (0x500000B4) +#define FUSE_CTRL_HW_CFG0_DIGEST_0 (0x500000B8) +#define FUSE_CTRL_HW_CFG0_DIGEST_1 (0x500000BC) +#define FUSE_CTRL_HW_CFG1_DIGEST_0 (0x500000C0) +#define FUSE_CTRL_HW_CFG1_DIGEST_1 (0x500000C4) +#define FUSE_CTRL_SECRET0_DIGEST_0 (0x500000C8) +#define FUSE_CTRL_SECRET0_DIGEST_1 (0x500000CC) +#define FUSE_CTRL_SECRET1_DIGEST_0 (0x500000D0) +#define FUSE_CTRL_SECRET1_DIGEST_1 (0x500000D4) +#define FUSE_CTRL_SECRET2_DIGEST_0 (0x500000D8) +#define FUSE_CTRL_SECRET2_DIGEST_1 (0x500000DC) +#define FUSE_CTRL_SW_CFG_WINDOW (0x50000800) + +#define FUSE_CTRL_REGISTERS { FUSE_CTRL_BASE_ADDR, \ + FUSE_CTRL_INTR_STATE, \ + FUSE_CTRL_INTR_ENABLE, \ + FUSE_CTRL_INTR_TEST, \ + FUSE_CTRL_ALERT_TEST, \ + FUSE_CTRL_STATUS, \ + FUSE_CTRL_ERR_CODE_0, \ + FUSE_CTRL_ERR_CODE_1, \ + FUSE_CTRL_ERR_CODE_2, \ + FUSE_CTRL_ERR_CODE_3, \ + FUSE_CTRL_ERR_CODE_4, \ + FUSE_CTRL_ERR_CODE_5, \ + FUSE_CTRL_ERR_CODE_6, \ + FUSE_CTRL_ERR_CODE_7, \ + FUSE_CTRL_ERR_CODE_8, \ + FUSE_CTRL_ERR_CODE_9, \ + FUSE_CTRL_ERR_CODE_10, \ + FUSE_CTRL_ERR_CODE_11, \ + FUSE_CTRL_ERR_CODE_12, \ + FUSE_CTRL_DIRECT_ACCESS_REGWEN, \ + FUSE_CTRL_DIRECT_ACCESS_CMD, \ + FUSE_CTRL_DIRECT_ACCESS_ADDRESS, \ + FUSE_CTRL_DIRECT_ACCESS_WDATA_0, \ + FUSE_CTRL_DIRECT_ACCESS_WDATA_1, \ + FUSE_CTRL_DIRECT_ACCESS_RDATA_0, \ + FUSE_CTRL_DIRECT_ACCESS_RDATA_1, \ + FUSE_CTRL_CHECK_TRIGGER_REGWEN, \ + FUSE_CTRL_CHECK_TRIGGER, \ + FUSE_CTRL_CHECK_REGWEN, \ + FUSE_CTRL_CHECK_TIMEOUT, \ + FUSE_CTRL_INTEGRITY_CHECK_PERIOD, \ + FUSE_CTRL_CONSISTENCY_CHECK_PERIOD, \ + FUSE_CTRL_VENDOR_TEST_READ_LOCK, \ + FUSE_CTRL_CREATOR_SW_CFG_READ_LOCK, \ + FUSE_CTRL_OWNER_SW_CFG_READ_LOCK, \ + FUSE_CTRL_ROT_CREATOR_AUTH_CODESIGN_READ_LOCK, \ + FUSE_CTRL_ROT_CREATOR_AUTH_STATE_READ_LOCK, \ + FUSE_CTRL_VENDOR_TEST_DIGEST_0, \ + FUSE_CTRL_VENDOR_TEST_DIGEST_1, \ + FUSE_CTRL_CREATOR_SW_CFG_DIGEST_0, \ + FUSE_CTRL_CREATOR_SW_CFG_DIGEST_1, \ + FUSE_CTRL_OWNER_SW_CFG_DIGEST_0, \ + FUSE_CTRL_OWNER_SW_CFG_DIGEST_1, \ + FUSE_CTRL_ROT_CREATOR_AUTH_CODESIGN_DIGEST_0, \ + FUSE_CTRL_ROT_CREATOR_AUTH_CODESIGN_DIGEST_1, \ + FUSE_CTRL_ROT_CREATOR_AUTH_STATE_DIGEST_0, \ + FUSE_CTRL_ROT_CREATOR_AUTH_STATE_DIGEST_1, \ + FUSE_CTRL_HW_CFG0_DIGEST_0, \ + FUSE_CTRL_HW_CFG0_DIGEST_1, \ + FUSE_CTRL_HW_CFG1_DIGEST_0, \ + FUSE_CTRL_HW_CFG1_DIGEST_1, \ + FUSE_CTRL_SECRET0_DIGEST_0, \ + FUSE_CTRL_SECRET0_DIGEST_1, \ + FUSE_CTRL_SECRET1_DIGEST_0, \ + FUSE_CTRL_SECRET1_DIGEST_1, \ + FUSE_CTRL_SECRET2_DIGEST_0, \ + FUSE_CTRL_SECRET2_DIGEST_1, \ + FUSE_CTRL_SW_CFG_WINDOW } +#endif diff --git a/src/integration/test_suites/mcu_fuse_ctrl_bringup/mcu_fuse_ctrl_bringup.c b/src/integration/test_suites/mcu_fuse_ctrl_bringup/mcu_fuse_ctrl_bringup.c new file mode 100644 index 0000000..73e3f29 --- /dev/null +++ b/src/integration/test_suites/mcu_fuse_ctrl_bringup/mcu_fuse_ctrl_bringup.c @@ -0,0 +1,73 @@ + +#include "soc_address_map.h" +#include "printf.h" +#include "riscv_hw_if.h" +#include "soc_ifc.h" +#include "fuse_ctrl_address_map.h" +#include +#include +#include +#include + +volatile char* stdout = (char *)0xd0580000; +#ifdef CPT_VERBOSITY + enum printf_verbosity verbosity_g = CPT_VERBOSITY; +#else + enum printf_verbosity verbosity_g = LOW; +#endif + +void main (void) { + int argc=0; + char *argv[1]; + //enum boot_fsm_state_e boot_fsm_ps; + const uint32_t mbox_dlen = 64; + uint32_t mbox_data[] = { 0x00000000, + 0x11111111, + 0x22222222, + 0x33333333, + 0x44444444, + 0x55555555, + 0x66666666, + 0x77777777, + 0x88888888, + 0x99999999, + 0xaaaaaaaa, + 0xbbbbbbbb, + 0xcccccccc, + 0xdddddddd, + 0xeeeeeeee, + 0xffffffff }; + uint32_t mbox_resp_dlen; + uint32_t mbox_resp_data; + uint32_t registers[] = FUSE_CTRL_REGISTERS; + int num_registers = sizeof(registers) / sizeof(registers[0]); + uint32_t random_value; + int random_index; + uint32_t write_data = 0xc001cafe; + + int array_size = sizeof(mbox_data) / sizeof(mbox_data[0]); + + VPRINTF(LOW, "=================\nMCU Fuse Controller Bringup\n=================\n\n") + + VPRINTF(LOW, "Reading all Fuse Controller CSRs\n\n"); + for (int i = 0; i < num_registers; i++) { + uint32_t reg_value = lsu_read_32(registers[i]); + VPRINTF(LOW, "Read Register [0x%08x]: 0x%08x\n", registers[i], reg_value); + } + + VPRINTF(LOW, "Writing all Fuse Controller CSRs\n\n"); + for (int i = 0; i < num_registers; i++) { + // Write 0xc001cafe to register + lsu_write_32(registers[i], write_data); + VPRINTF(LOW, "Write Register [0x%08x]: 0x%08x\n", registers[i], write_data); + } + + VPRINTF(LOW, "Reading all Fuse Controller CSRs after write\n\n"); + for (int i = 0; i < num_registers; i++) { + uint32_t reg_value = lsu_read_32(registers[i]); + VPRINTF(LOW, "Read Register [0x%08x]: 0x%08x\n", registers[i], reg_value); + } + + SEND_STDOUT_CTRL(0xff); + +} diff --git a/src/integration/test_suites/mcu_fuse_ctrl_bringup/mcu_fuse_ctrl_bringup.yml b/src/integration/test_suites/mcu_fuse_ctrl_bringup/mcu_fuse_ctrl_bringup.yml new file mode 100644 index 0000000..f037174 --- /dev/null +++ b/src/integration/test_suites/mcu_fuse_ctrl_bringup/mcu_fuse_ctrl_bringup.yml @@ -0,0 +1,3 @@ +--- +seed: 1 +testname: mcu_fuse_ctrl_bringup diff --git a/src/integration/testbench/aaxi4_interconnect.sv b/src/integration/testbench/aaxi4_interconnect.sv index 2476e93..9565100 100644 --- a/src/integration/testbench/aaxi4_interconnect.sv +++ b/src/integration/testbench/aaxi4_interconnect.sv @@ -26,6 +26,7 @@ import aaxi_pkg::*; import aaxi_pkg_xactor::*; import aaxi_pkg_test::*; import aaxi_pll::*; +import aaxi_pkg_caliptra_test::*; // AXI Reset, Deassert=H, Assert=L // bit rst_l; @@ -236,6 +237,26 @@ initial begin slave[4].cfg_info.total_outstanding_depth = 4; slave[4].cfg_info.id_outstanding_depth = 4; + //-- Fuse Controller Core AXI + slave[5].cfg_info.passive_mode = 1; + slave[5].cfg_info.opt_awuser_enable = 1; // optional, axi4_interconn_routings.sv need it + slave[5].cfg_info.opt_aruser_enable = 1; // optional, axi4_interconn_routings.sv need it + slave[5].cfg_info.base_address[0] = 64'h5000_0000; + slave[5].cfg_info.limit_address[0] = 64'h5000_FFFF; + slave[5].cfg_info.data_bus_bytes = AAXI_DATA_WIDTH >> 3; // set DATA BUS WIDTH + slave[5].cfg_info.total_outstanding_depth = 4; + slave[5].cfg_info.id_outstanding_depth = 4; + + //-- Fuse Controller Prim AXI + slave[6].cfg_info.passive_mode = 1; + slave[6].cfg_info.opt_awuser_enable = 1; // optional, axi4_interconn_routings.sv need it + slave[6].cfg_info.opt_aruser_enable = 1; // optional, axi4_interconn_routings.sv need it + slave[6].cfg_info.base_address[0] = 64'h6000_0000; + slave[6].cfg_info.limit_address[0] = 64'h6000_FFFF; + slave[6].cfg_info.data_bus_bytes = AAXI_DATA_WIDTH >> 3; // set DATA BUS WIDTH + slave[6].cfg_info.total_outstanding_depth = 4; + slave[6].cfg_info.id_outstanding_depth = 4; + //#1; //do not sure what feature of #1 // connect devices to the Interconnect @@ -292,7 +313,8 @@ initial begin `endif end - task automatic start_test(aaxi_test_base test); + //task automatic start_test(aaxi_test_base test); + task automatic start_test(aaxi_test_caliptra_ss test); aaxi_pkg_test::aaxi_test_select(test.test_name); test.master0= master[0]; test.master1= master[1]; @@ -311,12 +333,17 @@ initial begin slave[2].set("mem_uninitialized_value", 0); slave[3].set("mem_uninitialized_value", 0); slave[4].set("mem_uninitialized_value", 0); + slave[5].set("mem_uninitialized_value", 0); + slave[6].set("mem_uninitialized_value", 0); + test.slave0= slave[0]; test.slave1= slave[1]; test.slave2= slave[2]; test.slave3= slave[3]; test.slave4= slave[4]; + test.slave5= slave[5]; + test.slave6= slave[6]; for (int i=0; i< AAXI_INTC_SLAVE_CNT; i++) test.slv_bfms.push_back(slave[i]); diff --git a/src/integration/testbench/aaxi_pkg_caliptra_test.sv b/src/integration/testbench/aaxi_pkg_caliptra_test.sv new file mode 100644 index 0000000..c1bbd98 --- /dev/null +++ b/src/integration/testbench/aaxi_pkg_caliptra_test.sv @@ -0,0 +1,13 @@ +`ifndef aaxi_pkg_caliptra_test_sv +`define aaxi_pkg_caliptra_test_sv + +package aaxi_pkg_caliptra_test; + + //`include "aaxi_pkg.sv" + //`include "aaxi_pkg_test.sv" + `include "aaxi_test_caliptra_ss.svh" + +endpackage + +`endif + diff --git a/src/integration/testbench/aaxi_test_caliptra_ss.svh b/src/integration/testbench/aaxi_test_caliptra_ss.svh new file mode 100644 index 0000000..3717d7a --- /dev/null +++ b/src/integration/testbench/aaxi_test_caliptra_ss.svh @@ -0,0 +1,40 @@ +/* Class aaxi_test_caliptra_ss + * extends aaxi_test_base. */ + +import aaxi_pkg::*; +import aaxi_pkg_test::*; +import aaxi_pkg_xactor::*; + +class aaxi_test_caliptra_ss extends aaxi_test_base; + // Additional Slave BFMs slave5, slave6 + // slave0, slave1, slave2, slave3 and slave4 are defined in aaxi_test_base + aaxi_device_class slave5, slave6; + + // Constructor to initialize the class + function new(string name); + super.new(name); // Call the parent class constructor + + // Initialize and add new slave BFMs to the array + //slave5 = new(); + //slave6 = new(); + //slv_bfms.push_back(slave5); + //slv_bfms.push_back(slave6); + endfunction + /* + // Override bfm_param_setup to include new slaves + function void bfm_param_setup(); + super.bfm_param_setup(); // Call the base class method + + // Setup parameters for additional slaves + aaxi_slave_param slv_par3; + + slv_par3 = new($psprintf("slv_param%0d", slv_bfms.size() - 2)); + slave5.cfg_info.copy_slave_param(slv_par3); + slv_param_Q.push_back(slv_par3); + + slv_par3 = new($psprintf("slv_param%0d", slv_bfms.size() - 1)); + slave6.cfg_info.copy_slave_param(slv_par3); + slv_param_Q.push_back(slv_par3); + endfunction + */ +endclass \ No newline at end of file diff --git a/src/integration/testbench/caliptra_ss_top.sv b/src/integration/testbench/caliptra_ss_top.sv index 9101edb..e9e6505 100644 --- a/src/integration/testbench/caliptra_ss_top.sv +++ b/src/integration/testbench/caliptra_ss_top.sv @@ -14,6 +14,8 @@ // //`define MCU_DRAM(bk) caliptra_ss_top.mcu_top_i.dccm_loop[bk].ram.ram_core `define MCU_RV_LSU_BUS_TAG_local 1 +`define INCLUDE_FUSE_CTRL = 1 + `default_nettype none `include "common_defines.sv" @@ -423,6 +425,8 @@ module caliptra_ss_top logic [pt.DCCM_NUM_BANKS-1:0][pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_fdata_bank; logic [pt.DCCM_NUM_BANKS-1:0][pt.DCCM_FDATA_WIDTH-1:0] dccm_bank_fdout; + logic fuse_ctrl_rdy; + tb_top_pkg::veer_sram_error_injection_mode_t error_injection_mode; `define MCU_DEC rvtop_wrapper.rvtop.veer.dec @@ -732,18 +736,24 @@ module caliptra_ss_top logic deassert_rst_flag_from_service; + + + logic cptra_soc_bfm_rst_b; + caliptra_top_tb_soc_bfm #( - .SKIP_BRINGUP(1) + .SKIP_BRINGUP(1), + .SKIP_FUSE_CTRL(0) ) soc_bfm_inst ( .core_clk (core_clk ), .cptra_pwrgood (cptra_pwrgood ), - .cptra_rst_b (cptra_rst_b ), + .cptra_rst_b (cptra_soc_bfm_rst_b ), .BootFSM_BrkPoint(BootFSM_BrkPoint), .cycleCnt (cycleCnt ), + .cptra_obf_key (cptra_obf_key ), .cptra_csr_hmac_key(cptra_csr_hmac_key), @@ -1125,6 +1135,25 @@ module caliptra_ss_top else if (m_axi_if.arvalid && m_axi_if.arready) m_axi_if_rd_is_upper_dw_latched <= m_axi_if.araddr[2] && (m_axi_if.arsize < 3); `CALIPTRA_ASSERT(CPTRA_AXI_DMA_RD_32BIT, (m_axi_if.arvalid && m_axi_if.arready) -> (m_axi_if.arsize < 3), core_clk, !rst_l) + + // AXI Interconnect connections + logic m_axi_bfm_if_rd_is_upper_dw_latched; + logic m_axi_bfm_if_wr_is_upper_dw_latched; + // FIXME this is a gross hack for data width conversion + always@(posedge core_clk or negedge rst_l) + if (!rst_l) + m_axi_bfm_if_wr_is_upper_dw_latched <= 0; + else if (m_axi_bfm_if.awvalid && m_axi_bfm_if.awready) + m_axi_bfm_if_wr_is_upper_dw_latched <= m_axi_bfm_if.awaddr[2] && (m_axi_bfm_if.awsize < 3); + `CALIPTRA_ASSERT(CPTRA_AXI_DMA_WR_32BIT, (m_axi_bfm_if.awvalid && m_axi_bfm_if.awready) -> (m_axi_bfm_if.awsize < 3), core_clk, !rst_l) + // FIXME this is a gross hack for data width conversion + always@(posedge core_clk or negedge rst_l) + if (!rst_l) + m_axi_bfm_if_rd_is_upper_dw_latched <= 0; + else if (m_axi_bfm_if.arvalid && m_axi_bfm_if.arready) + m_axi_bfm_if_rd_is_upper_dw_latched <= m_axi_bfm_if.araddr[2] && (m_axi_bfm_if.arsize < 3); + `CALIPTRA_ASSERT(CPTRA_AXI_DMA_RD_32BIT, (m_axi_bfm_if.arvalid && m_axi_bfm_if.arready) -> (m_axi_bfm_if.arsize < 3), core_clk, !rst_l) + assign axi_interconnect.mintf_arr[3].AWVALID = m_axi_if.awvalid; assign axi_interconnect.mintf_arr[3].AWADDR = m_axi_if.awaddr; assign axi_interconnect.mintf_arr[3].AWID = m_axi_if.awid; @@ -1175,8 +1204,8 @@ module caliptra_ss_top assign m_axi_bfm_if.awready = axi_interconnect.mintf_arr[4].AWREADY; assign axi_interconnect.mintf_arr[4].WVALID = m_axi_bfm_if.wvalid; - assign axi_interconnect.mintf_arr[4].WDATA = m_axi_bfm_if.wdata; - assign axi_interconnect.mintf_arr[4].WSTRB = m_axi_bfm_if.wstrb; + assign axi_interconnect.mintf_arr[4].WDATA = m_axi_bfm_if.wdata << (m_axi_bfm_if_wr_is_upper_dw_latched ? 32 : 0); + assign axi_interconnect.mintf_arr[4].WSTRB = m_axi_bfm_if.wstrb << (m_axi_bfm_if_wr_is_upper_dw_latched ? 4 : 0); assign axi_interconnect.mintf_arr[4].WLAST = m_axi_bfm_if.wlast; assign m_axi_bfm_if.wready = axi_interconnect.mintf_arr[4].WREADY; @@ -1196,7 +1225,7 @@ module caliptra_ss_top assign m_axi_bfm_if.arready = axi_interconnect.mintf_arr[4].ARREADY; assign m_axi_bfm_if.rvalid = axi_interconnect.mintf_arr[4].RVALID; - assign m_axi_bfm_if.rdata = axi_interconnect.mintf_arr[4].RDATA; + assign m_axi_bfm_if.rdata = axi_interconnect.mintf_arr[4].RDATA >> (m_axi_bfm_if_rd_is_upper_dw_latched ? 32 : 0); assign m_axi_bfm_if.rresp = axi_interconnect.mintf_arr[4].RRESP; assign m_axi_bfm_if.rid = axi_interconnect.mintf_arr[4].RID; assign m_axi_bfm_if.rlast = axi_interconnect.mintf_arr[4].RLAST; @@ -1484,20 +1513,41 @@ module caliptra_ss_top ); - assign axi_interconnect.mintf_arr[0].ARID[aaxi_pkg::AAXI_INTC_ID_WIDTH-1:pt.LSU_BUS_TAG] = '0; - assign axi_interconnect.mintf_arr[0].AWID[aaxi_pkg::AAXI_INTC_ID_WIDTH-1:pt.LSU_BUS_TAG] = '0; - assign axi_interconnect.mintf_arr[0].ARUSER[aaxi_pkg::AAXI_ARUSER_WIDTH-1:0] = '1; - assign axi_interconnect.mintf_arr[0].AWUSER[aaxi_pkg::AAXI_AWUSER_WIDTH-1:0] = '1; - assign axi_interconnect.mintf_arr[0].ARADDR[aaxi_pkg::AAXI_ADDR_WIDTH-1:32] = 32'h0; - assign axi_interconnect.mintf_arr[0].AWADDR[aaxi_pkg::AAXI_ADDR_WIDTH-1:32] = 32'h0; - assign axi_interconnect.mintf_arr[1].ARID[aaxi_pkg::AAXI_INTC_ID_WIDTH-1:pt.IFU_BUS_TAG] = '0; - assign axi_interconnect.mintf_arr[1].AWID[aaxi_pkg::AAXI_INTC_ID_WIDTH-1:pt.IFU_BUS_TAG] = '0; - assign axi_interconnect.mintf_arr[1].ARADDR[aaxi_pkg::AAXI_ADDR_WIDTH-1:32] = 32'h0; - assign axi_interconnect.mintf_arr[1].AWADDR[aaxi_pkg::AAXI_ADDR_WIDTH-1:32] = 32'h0; - assign axi_interconnect.sintf_arr[2].RID[aaxi_pkg::AAXI_INTC_ID_WIDTH-1:pt.DMA_BUS_TAG] = '0; - assign axi_interconnect.sintf_arr[2].BID[aaxi_pkg::AAXI_INTC_ID_WIDTH-1:pt.DMA_BUS_TAG] = '0; - assign axi_interconnect.sintf_arr[2].ARADDR[aaxi_pkg::AAXI_ADDR_WIDTH-1:32] = 32'h0; - assign axi_interconnect.sintf_arr[2].AWADDR[aaxi_pkg::AAXI_ADDR_WIDTH-1:32] = 32'h0; + // assign axi_interconnect.mintf_arr[0].AWUSER = 32'hFFFF_FFFF; + // assign axi_interconnect.mintf_arr[0].ARUSER = 32'hFFFF_FFFF; + // assign axi_interconnect.mintf_arr[0].ARID[aaxi_pkg::AAXI_INTC_ID_WIDTH-1:pt.LSU_BUS_TAG] = '0; + // assign axi_interconnect.mintf_arr[0].AWID[aaxi_pkg::AAXI_INTC_ID_WIDTH-1:pt.LSU_BUS_TAG] = '0; + // assign axi_interconnect.mintf_arr[0].ARUSER[aaxi_pkg::AAXI_ARUSER_WIDTH-1:0] = '1; + // assign axi_interconnect.mintf_arr[0].AWUSER[aaxi_pkg::AAXI_AWUSER_WIDTH-1:0] = '1; + // assign axi_interconnect.mintf_arr[0].ARADDR[aaxi_pkg::AAXI_ADDR_WIDTH-1:32] = 32'h0; + // assign axi_interconnect.mintf_arr[0].AWADDR[aaxi_pkg::AAXI_ADDR_WIDTH-1:32] = 32'h0; + // assign axi_interconnect.mintf_arr[1].ARID[aaxi_pkg::AAXI_INTC_ID_WIDTH-1:pt.IFU_BUS_TAG] = '0; + // assign axi_interconnect.mintf_arr[1].AWID[aaxi_pkg::AAXI_INTC_ID_WIDTH-1:pt.IFU_BUS_TAG] = '0; + // assign axi_interconnect.mintf_arr[1].ARADDR[aaxi_pkg::AAXI_ADDR_WIDTH-1:32] = 32'h0; + // assign axi_interconnect.mintf_arr[1].AWADDR[aaxi_pkg::AAXI_ADDR_WIDTH-1:32] = 32'h0; + // assign axi_interconnect.sintf_arr[2].RID[aaxi_pkg::AAXI_INTC_ID_WIDTH-1:pt.DMA_BUS_TAG] = '0; + // assign axi_interconnect.sintf_arr[2].BID[aaxi_pkg::AAXI_INTC_ID_WIDTH-1:pt.DMA_BUS_TAG] = '0; + // assign axi_interconnect.sintf_arr[2].ARADDR[aaxi_pkg::AAXI_ADDR_WIDTH-1:32] = 32'h0; + // assign axi_interconnect.sintf_arr[2].AWADDR[aaxi_pkg::AAXI_ADDR_WIDTH-1:32] = 32'h0; + always_comb begin + axi_interconnect.mintf_arr[0].AWUSER = 32'hFFFF_FFFF; + axi_interconnect.mintf_arr[0].ARUSER = 32'hFFFF_FFFF; + axi_interconnect.mintf_arr[0].ARID[aaxi_pkg::AAXI_INTC_ID_WIDTH-1:pt.LSU_BUS_TAG] = '0; + axi_interconnect.mintf_arr[0].AWID[aaxi_pkg::AAXI_INTC_ID_WIDTH-1:pt.LSU_BUS_TAG] = '0; + axi_interconnect.mintf_arr[0].ARUSER[aaxi_pkg::AAXI_ARUSER_WIDTH-1:0] = '1; + axi_interconnect.mintf_arr[0].AWUSER[aaxi_pkg::AAXI_AWUSER_WIDTH-1:0] = '1; + axi_interconnect.mintf_arr[0].ARADDR[aaxi_pkg::AAXI_ADDR_WIDTH-1:32] = 32'h0; + axi_interconnect.mintf_arr[0].AWADDR[aaxi_pkg::AAXI_ADDR_WIDTH-1:32] = 32'h0; + axi_interconnect.mintf_arr[1].ARID[aaxi_pkg::AAXI_INTC_ID_WIDTH-1:pt.IFU_BUS_TAG] = '0; + axi_interconnect.mintf_arr[1].AWID[aaxi_pkg::AAXI_INTC_ID_WIDTH-1:pt.IFU_BUS_TAG] = '0; + axi_interconnect.mintf_arr[1].ARADDR[aaxi_pkg::AAXI_ADDR_WIDTH-1:32] = 32'h0; + axi_interconnect.mintf_arr[1].AWADDR[aaxi_pkg::AAXI_ADDR_WIDTH-1:32] = 32'h0; + axi_interconnect.sintf_arr[2].RID[aaxi_pkg::AAXI_INTC_ID_WIDTH-1:pt.DMA_BUS_TAG] = '0; + axi_interconnect.sintf_arr[2].BID[aaxi_pkg::AAXI_INTC_ID_WIDTH-1:pt.DMA_BUS_TAG] = '0; + axi_interconnect.sintf_arr[2].ARADDR[aaxi_pkg::AAXI_ADDR_WIDTH-1:32] = 32'h0; + axi_interconnect.sintf_arr[2].AWADDR[aaxi_pkg::AAXI_ADDR_WIDTH-1:32] = 32'h0; + end + // FIXME This hacky FIFO is to ensure the same AXI ID is used throughout a mailbox transfer. // We need an ability to deterministically use the same AXI ID from the VeeR executable @@ -1793,6 +1843,192 @@ module caliptra_ss_top assign axi_interconnect.sintf_arr[1].ARADDR[aaxi_pkg::AAXI_ADDR_WIDTH-1:32] = 32'h0; assign axi_interconnect.sintf_arr[1].AWADDR[aaxi_pkg::AAXI_ADDR_WIDTH-1:32] = 32'h0; + //=========================================================================- + // Fuse Controller Instance : + // + //=========================================================================- + + caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_t caliptra_ss_lc_dft_en_i; + logic [$bits(caliptra_ss_lc_dft_en_i)-1:0] caliptra_ss_lc_dft_en_i_tb; + assign caliptra_ss_lc_dft_en_i = caliptra_ss_lc_dft_en_i_tb; + + caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_t caliptra_ss_lc_escalate_en_i; + logic [$bits(caliptra_ss_lc_escalate_en_i)-1:0] caliptra_ss_lc_escalate_en_i_tb; + assign caliptra_ss_lc_escalate_en_i = caliptra_ss_lc_escalate_en_i_tb; + + caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_t caliptra_ss_lc_check_byp_en_i; + logic [$bits(caliptra_ss_lc_check_byp_en_i)-1:0] caliptra_ss_lc_check_byp_en_i_tb; + assign caliptra_ss_lc_check_byp_en_i = caliptra_ss_lc_check_byp_en_i_tb; + + otp_ctrl_pkg::otp_caliptra_ss_lc_data_t otp_caliptra_ss_lc_data_o; + logic [$bits(otp_caliptra_ss_lc_data_o)-1:0] otp_caliptra_ss_lc_data_o_tb; + + // logic otp_caliptra_ss_lc_data_o_valid; + logic pwr_otp_init_i; + + axi_struct_pkg::axi_wr_req_t core_axi_wr_req; + axi_struct_pkg::axi_wr_rsp_t core_axi_wr_rsp; + axi_struct_pkg::axi_rd_req_t core_axi_rd_req; + axi_struct_pkg::axi_rd_rsp_t core_axi_rd_rsp; + + axi_struct_pkg::axi_wr_req_t prim_axi_wr_req; + axi_struct_pkg::axi_wr_rsp_t prim_axi_wr_rsp; + axi_struct_pkg::axi_rd_req_t prim_axi_rd_req; + axi_struct_pkg::axi_rd_rsp_t prim_axi_rd_rsp; + + caliptra_prim_mubi_pkg::mubi4_t scanmode_mubi; + + otp_ctrl #( + .MemInitFile ("/home/ws/caliptra/anjpar/caliptra_ws_1119/Caliptra/../chipsalliance/caliptra-ss/src/fuse_ctrl/data/otp-img.2048.vmem") + ) u_otp_ctrl ( + .clk_i (core_clk), + .rst_ni (rst_l), + .clk_edn_i (), + .rst_edn_ni (), + .edn_o (), + .edn_i (), + + .core_axi_wr_req (core_axi_wr_req), + .core_axi_wr_rsp (core_axi_wr_rsp), + .core_axi_rd_req (core_axi_rd_req), + .core_axi_rd_rsp (core_axi_rd_rsp), + + .prim_axi_wr_req (prim_axi_wr_req), + .prim_axi_wr_rsp (prim_axi_wr_rsp), + .prim_axi_rd_req (prim_axi_rd_req), + .prim_axi_rd_rsp (prim_axi_rd_rsp), + + .intr_otp_operation_done_o (), + .intr_otp_error_o (), + .alert_rx_i (), + .alert_tx_o (), + .obs_ctrl_i (), + .otp_obs_o (), + .otp_ast_pwr_seq_o (), + .otp_ast_pwr_seq_h_i (), + .pwr_otp_i (pwr_otp_init_i), + .pwr_otp_o (), + .caliptra_ss_lc_otp_vendor_test_i (), + .caliptra_ss_lc_otp_vendor_test_o (), + .caliptra_ss_lc_otp_program_i (), + .caliptra_ss_lc_otp_program_o (), + .caliptra_ss_lc_creator_seed_sw_rw_en_i (), + .caliptra_ss_lc_owner_seed_sw_rw_en_i (), + .caliptra_ss_lc_seed_hw_rd_en_i (), + .caliptra_ss_lc_dft_en_i (caliptra_ss_lc_dft_en_i_tb), + .caliptra_ss_lc_escalate_en_i (caliptra_ss_lc_escalate_en_i_tb), + .caliptra_ss_lc_check_byp_en_i (caliptra_ss_lc_check_byp_en_i_tb), + .otp_caliptra_ss_lc_data_o (otp_caliptra_ss_lc_data_o_tb), + .otp_keymgr_key_o (), + .flash_otp_key_i (), + .flash_otp_key_o (), + .sram_otp_key_i (), + .sram_otp_key_o (), + .otbn_otp_key_i (), + .otbn_otp_key_o (), + .otp_broadcast_o (), + .otp_ext_voltage_h_io (), + .scan_en_i (), + .scan_rst_ni (), + .scanmode_i (scanmode_mubi), + .cio_test_o (), + .cio_test_en_o () + ); + + + assign scanmode_mubi = scan_mode ? caliptra_prim_mubi_pkg::MuBi4True : caliptra_prim_mubi_pkg::MuBi4False; + + assign core_axi_wr_req.awaddr = axi_interconnect.sintf_arr[5].AWADDR; + assign core_axi_wr_req.awburst = axi_interconnect.sintf_arr[5].AWBURST; + assign core_axi_wr_req.awsize = axi_interconnect.sintf_arr[5].AWSIZE; + assign core_axi_wr_req.awlen = axi_interconnect.sintf_arr[5].AWLEN; + assign core_axi_wr_req.awuser = axi_interconnect.sintf_arr[5].AWUSER; + assign core_axi_wr_req.awid = axi_interconnect.sintf_arr[5].AWID; + assign core_axi_wr_req.awlock = axi_interconnect.sintf_arr[5].AWLOCK; + assign core_axi_wr_req.awvalid = axi_interconnect.sintf_arr[5].AWVALID; + assign core_axi_wr_req.wdata = axi_interconnect.sintf_arr[5].WDATA; + assign core_axi_wr_req.wstrb = axi_interconnect.sintf_arr[5].WSTRB; + assign core_axi_wr_req.wlast = axi_interconnect.sintf_arr[5].WLAST; + assign core_axi_wr_req.wvalid = axi_interconnect.sintf_arr[5].WVALID; + assign core_axi_wr_req.bready = axi_interconnect.sintf_arr[5].BREADY; + + assign axi_interconnect.sintf_arr[5].AWREADY = core_axi_wr_rsp.awready; + assign axi_interconnect.sintf_arr[5].WREADY = core_axi_wr_rsp.wready; + assign axi_interconnect.sintf_arr[5].BRESP = core_axi_wr_rsp.bresp; + assign axi_interconnect.sintf_arr[5].BID = core_axi_wr_rsp.bid; + assign axi_interconnect.sintf_arr[5].BVALID = core_axi_wr_rsp.bvalid; + + assign core_axi_rd_req.araddr = axi_interconnect.sintf_arr[5].ARADDR; + assign core_axi_rd_req.arburst = axi_interconnect.sintf_arr[5].ARBURST; + assign core_axi_rd_req.arsize = axi_interconnect.sintf_arr[5].ARSIZE; + assign core_axi_rd_req.arlen = axi_interconnect.sintf_arr[5].ARLEN; + assign core_axi_rd_req.aruser = axi_interconnect.sintf_arr[5].ARUSER; + assign core_axi_rd_req.arid = axi_interconnect.sintf_arr[5].ARID; + assign core_axi_rd_req.arlock = axi_interconnect.sintf_arr[5].ARLOCK; + assign core_axi_rd_req.arvalid = axi_interconnect.sintf_arr[5].ARVALID; + assign core_axi_rd_req.rready = axi_interconnect.sintf_arr[5].RREADY; + + assign axi_interconnect.sintf_arr[5].ARREADY = core_axi_rd_rsp.arready; + assign axi_interconnect.sintf_arr[5].RDATA = core_axi_rd_rsp.rdata; + assign axi_interconnect.sintf_arr[5].RRESP = core_axi_rd_rsp.rresp; + assign axi_interconnect.sintf_arr[5].RID = core_axi_rd_rsp.rid; + assign axi_interconnect.sintf_arr[5].RLAST = core_axi_rd_rsp.rlast; + assign axi_interconnect.sintf_arr[5].RVALID = core_axi_rd_rsp.rvalid; + + assign prim_axi_wr_req.awaddr = axi_interconnect.sintf_arr[6].AWADDR; + assign prim_axi_wr_req.awburst = axi_interconnect.sintf_arr[6].AWBURST; + assign prim_axi_wr_req.awsize = axi_interconnect.sintf_arr[6].AWSIZE; + assign prim_axi_wr_req.awlen = axi_interconnect.sintf_arr[6].AWLEN; + assign prim_axi_wr_req.awuser = axi_interconnect.sintf_arr[6].AWUSER; + assign prim_axi_wr_req.awid = axi_interconnect.sintf_arr[6].AWID; + assign prim_axi_wr_req.awlock = axi_interconnect.sintf_arr[6].AWLOCK; + assign prim_axi_wr_req.awvalid = axi_interconnect.sintf_arr[6].AWVALID; + assign prim_axi_wr_req.wdata = axi_interconnect.sintf_arr[6].WDATA; + assign prim_axi_wr_req.wstrb = axi_interconnect.sintf_arr[6].WSTRB; + assign prim_axi_wr_req.wlast = axi_interconnect.sintf_arr[6].WLAST; + assign prim_axi_wr_req.wvalid = axi_interconnect.sintf_arr[6].WVALID; + assign prim_axi_wr_req.bready = axi_interconnect.sintf_arr[6].BREADY; + + assign axi_interconnect.sintf_arr[6].AWREADY = prim_axi_wr_rsp.awready; + assign axi_interconnect.sintf_arr[6].WREADY = prim_axi_wr_rsp.wready; + assign axi_interconnect.sintf_arr[6].BRESP = prim_axi_wr_rsp.bresp; + assign axi_interconnect.sintf_arr[6].BID = prim_axi_wr_rsp.bid; + assign axi_interconnect.sintf_arr[6].BVALID = prim_axi_wr_rsp.bvalid; + + assign prim_axi_rd_req.araddr = axi_interconnect.sintf_arr[6].ARADDR; + assign prim_axi_rd_req.arburst = axi_interconnect.sintf_arr[6].ARBURST; + assign prim_axi_rd_req.arsize = axi_interconnect.sintf_arr[6].ARSIZE; + assign prim_axi_rd_req.arlen = axi_interconnect.sintf_arr[6].ARLEN; + assign prim_axi_rd_req.aruser = axi_interconnect.sintf_arr[6].ARUSER; + assign prim_axi_rd_req.arid = axi_interconnect.sintf_arr[6].ARID; + assign prim_axi_rd_req.arlock = axi_interconnect.sintf_arr[6].ARLOCK; + assign prim_axi_rd_req.arvalid = axi_interconnect.sintf_arr[6].ARVALID; + assign prim_axi_rd_req.rready = axi_interconnect.sintf_arr[6].RREADY; + + assign axi_interconnect.sintf_arr[6].ARREADY = prim_axi_rd_rsp.arready; + assign axi_interconnect.sintf_arr[6].RDATA = prim_axi_rd_rsp.rdata; + assign axi_interconnect.sintf_arr[6].RRESP = prim_axi_rd_rsp.rresp; + assign axi_interconnect.sintf_arr[6].RID = prim_axi_rd_rsp.rid; + assign axi_interconnect.sintf_arr[6].RLAST = prim_axi_rd_rsp.rlast; + assign axi_interconnect.sintf_arr[6].RVALID = prim_axi_rd_rsp.rvalid; + + fuse_ctrl_bfm u_fuse_ctrl_bfm ( + .core_clk (core_clk ), + .cptra_pwrgood (cptra_pwrgood ), + .fc_partition_init (pwr_otp_init_i ), + .caliptra_ss_lc_dft_en_i (caliptra_ss_lc_dft_en_i_tb ), + .caliptra_ss_lc_escalate_en_i (caliptra_ss_lc_escalate_en_i_tb ), + .caliptra_ss_lc_check_byp_en_i (caliptra_ss_lc_check_byp_en_i_tb ), + .otp_caliptra_ss_lc_data_o (otp_caliptra_ss_lc_data_o_tb), + .fuse_ctrl_rdy (fuse_ctrl_rdy ) + ); + + // assign otp_caliptra_ss_lc_data_o_valid = otp_caliptra_ss_lc_data_o.valid; + + // assign fuse_ctrl_rdy = 1; + // De-assert cptra_rst_b only after fuse_ctrl has initialized + assign cptra_rst_b = fuse_ctrl_rdy ? cptra_soc_bfm_rst_b : 1'b0; + task preload_iccm; bit[31:0] data; bit[31:0] addr, eaddr, saddr; diff --git a/src/integration/testbench/dasm.svi b/src/integration/testbench/dasm.svi index 3ee7572..099dead 100644 --- a/src/integration/testbench/dasm.svi +++ b/src/integration/testbench/dasm.svi @@ -20,7 +20,8 @@ `define MCU_RV_NUM_THREADS 1 `endif -string abi_reg[32]; // ABI register names +// string abi_reg[32]; // ABI register names +// This string is removed since it is also defined under caliptra_ss_top bit[31:0] [31:0] gpr[`MCU_RV_NUM_THREADS]; diff --git a/src/integration/testbench/fuse_ctrl_bfm.sv b/src/integration/testbench/fuse_ctrl_bfm.sv new file mode 100644 index 0000000..aa4406d --- /dev/null +++ b/src/integration/testbench/fuse_ctrl_bfm.sv @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// + +module fuse_ctrl_bfm + import caliptra_ss_lc_ctrl_pkg::*; + import caliptra_ss_lc_ctrl_reg_pkg::*; + import caliptra_ss_lc_ctrl_state_pkg::*; + //import caliptra_top_tb_pkg::*; + //import global_fuse_ctrl_init_done_event_pkg::*; + ( + input logic core_clk, + input logic cptra_pwrgood, + output logic fc_partition_init, + output caliptra_ss_lc_tx_t caliptra_ss_lc_dft_en_i, + output caliptra_ss_lc_tx_t caliptra_ss_lc_escalate_en_i, + output caliptra_ss_lc_tx_t caliptra_ss_lc_check_byp_en_i, + input otp_ctrl_pkg::otp_caliptra_ss_lc_data_t otp_caliptra_ss_lc_data_o, + output logic fuse_ctrl_rdy + ); + + logic otp_caliptra_ss_lc_data_o_valid; + assign otp_caliptra_ss_lc_data_o_valid = otp_caliptra_ss_lc_data_o.valid; + + initial begin + fuse_ctrl_rst(); + fuse_ctrl_rdy = 0; + wait(cptra_pwrgood == 1); + $display("Fuse Controller (fuse_ctrl_init_flow): Forcing fc_partition_init = 1."); + force fc_partition_init = 1'b1; + wait(otp_caliptra_ss_lc_data_o_valid == 1); + //->caliptra_top_tb_pkg::fuse_ctrl_init_done; //Signal that fuse controler initialization is done + fuse_ctrl_rdy = 1; + $display("Fuse Controller (fuse_ctrl_init_flow): All partitions initialized."); + $display("Fuse Controller (fuse_ctrl_init_flow): Releasing fc_partition_init = 1. "); + release fc_partition_init; + end + + task fuse_ctrl_rst(); + caliptra_ss_lc_dft_en_i = caliptra_ss_lc_ctrl_pkg::Off; + caliptra_ss_lc_escalate_en_i = caliptra_ss_lc_ctrl_pkg::Off; + caliptra_ss_lc_check_byp_en_i = lc_ctrl_pkg::Off; + fc_partition_init = 0; + endtask +endmodule + diff --git a/src/mcu/rtl/caliptra_mcu_top.sv b/src/mcu/rtl/caliptra_mcu_top.sv index 5544576..9171732 100755 --- a/src/mcu/rtl/caliptra_mcu_top.sv +++ b/src/mcu/rtl/caliptra_mcu_top.sv @@ -19,9 +19,9 @@ module caliptra_mcu_top import soc_ifc_pkg::*; - import lc_ctrl_state_pkg::*; - import lc_ctrl_reg_pkg::*; - import lc_ctrl_pkg::*; + import caliptra_ss_lc_ctrl_state_pkg::*; + import caliptra_ss_lc_ctrl_reg_pkg::*; + import caliptra_ss_lc_ctrl_pkg::*; `ifdef CALIPTRA_INTERNAL_TRNG import entropy_src_pkg::*; import csrng_pkg::*; @@ -846,7 +846,7 @@ csrng #( // OTP Interface .otp_en_csrng_sw_app_read_i(caliptra_prim_mubi_pkg::MuBi8True), // Lifecycle broadcast inputs - .lc_hw_debug_en_i (lc_ctrl_pkg::On), + .caliptra_ss_lc_hw_debug_en_i (caliptra_ss_lc_ctrl_pkg::On), // Entropy Interface .entropy_src_hw_if_o (entropy_src_hw_if_req), .entropy_src_hw_if_i (entropy_src_hw_if_rsp), diff --git a/src/pwrmgr/BUILD b/src/pwrmgr/BUILD new file mode 100644 index 0000000..129296b --- /dev/null +++ b/src/pwrmgr/BUILD @@ -0,0 +1,12 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +package(default_visibility = ["//visibility:public"]) + +filegroup( + name = "all_files", + srcs = glob(["**"]) + [ + "//hw/ip_templates/pwrmgr/data:all_files", + ], +) diff --git a/src/pwrmgr/README.md.tpl b/src/pwrmgr/README.md.tpl new file mode 100644 index 0000000..e388209 --- /dev/null +++ b/src/pwrmgr/README.md.tpl @@ -0,0 +1,36 @@ +# Power Manager HWIP Technical Specification +[`pwrmgr`](https://reports.opentitan.org/hw/top_${topname}/ip_autogen/pwrmgr/dv/latest/report.html): +![](https://dashboards.lowrisc.org/badges/dv/pwrmgr/test.svg) +![](https://dashboards.lowrisc.org/badges/dv/pwrmgr/passing.svg) +![](https://dashboards.lowrisc.org/badges/dv/pwrmgr/functional.svg) +![](https://dashboards.lowrisc.org/badges/dv/pwrmgr/code.svg) + +# Overview + +This document specifies the functionality of the OpenTitan power manager. + +${"##"} Features + +- Cold boot, low power entry / exit and reset support. +- 2 different low power modes. +- Software initiated low power entry and hardware requested low power exit. +- Peripheral reset requests +- Low power abort and low power fall-through support. +- ROM integrity check at power-up. +- Local checks for escalator and power stability. + +${"##"} Description + +The power manager sequences power, clocks, and reset resources of the design through cold boot, low power entry/exit and reset scenarios. + +Cold boot, also known as POR (power on reset) is the first reset state of the design. +The power manager sequences the design from a freshly reset state to an active state where software can be initialized. + +- Low power entry is the process in which the device enters one of two low power modes (sleep or deep sleep). +- Low power exit is the process in which the device exits low power mode and returns to active state. +- Low power entry is always initiated by software, while low power exit is always initiated by a previously setup hardware event such as pins or internal timers. +- The power manager processes the software and hardware requests to perform the appropriate actions. + +Reset scenarios refer to non-POR events that cause the device to reboot. +There are various stimuli that can cause such a reset, ranging from external user input to watchdog timeout. +The power manager processes the reset request and brings the device to an appropriate state. diff --git a/src/pwrmgr/config/compile.yml b/src/pwrmgr/config/compile.yml new file mode 100644 index 0000000..890163e --- /dev/null +++ b/src/pwrmgr/config/compile.yml @@ -0,0 +1,15 @@ +--- +provides: [pwrmgr_pkg] +schema_version: 2.4.0 +requires: +targets: + rtl: + directories: [$COMPILE_ROOT/rtl] + files: + - $COMPILE_ROOT/rtl/pwrmgr_reg_pkg.sv + - $COMPILE_ROOT/rtl/pwrmgr_pkg.sv + tb: + directories: [$COMPILE_ROOT/rtl] + files: + - $COMPILE_ROOT/rtl/pwrmgr_reg_pkg.sv + - $COMPILE_ROOT/rtl/pwrmgr_pkg.sv diff --git a/src/pwrmgr/data/BUILD b/src/pwrmgr/data/BUILD new file mode 100644 index 0000000..65cf527 --- /dev/null +++ b/src/pwrmgr/data/BUILD @@ -0,0 +1,30 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +package(default_visibility = ["//visibility:public"]) + +load( + "//rules:autogen.bzl", + "autogen_hjson_c_header", + "autogen_hjson_rust_header", +) + +autogen_hjson_c_header( + name = "pwrmgr_c_regs", + srcs = [ + "pwrmgr.hjson", + ], +) + +autogen_hjson_rust_header( + name = "pwrmgr_rust_regs", + srcs = [ + "pwrmgr.hjson", + ], +) + +filegroup( + name = "all_files", + srcs = glob(["**"]), +) diff --git a/src/pwrmgr/data/pwrmgr.hjson b/src/pwrmgr/data/pwrmgr.hjson new file mode 100644 index 0000000..977e618 --- /dev/null +++ b/src/pwrmgr/data/pwrmgr.hjson @@ -0,0 +1,577 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------// +// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + name: "pwrmgr", + human_name: "Power Manager", + one_line_desc: "Sequences on-chip power, clocks, and resets through different reset and power states", + one_paragraph_desc: ''' + Power Manager sequences on-chip power, clocks, and reset signals on power-on reset (aka cold boot), low power entry and exit, and non-power-on resets. + To this end, it can turn power domains on and off, control root resets with Reset Manager, and control root clock enables with AST and Clock Manager. + During power up, Power Manager is responsible for triggering OTP sensing, initiating Life Cycle Controller, coordinating with ROM Controller for the startup ROM check, and eventually releasing software to execute. + It features several countermeasures to deter fault injection (FI) attacks. + ''' + // Unique comportable IP identifier defined under KNOWN_CIP_IDS in the regtool. + cip_id: "20", + design_spec: "../doc", + dv_doc: "../doc/dv", + hw_checklist: "../doc/checklist", + sw_checklist: "/sw/device/lib/dif/dif_pwrmgr", + revisions: [ + { + version: "0.1.0", + life_stage: "L1", + design_stage: "D1", + verification_stage: "V0", // this module is not verified at the block level + dif_stage: "S0", + commit_id: "b2abc989498f072d9a5530f8aab9b58c1f92c9fb" + } + { + version: "1.0.0", + life_stage: "L1", + design_stage: "D2S", + verification_stage: "V2S", + dif_stage: "S2", + } + ] + clocking: [ + {clock: "clk_i", reset: "rst_ni", primary: true}, + {reset: "rst_main_ni"}, + {clock: "clk_slow_i", reset: "rst_slow_ni"}, + {clock: "clk_lc_i", reset: "rst_lc_ni"}, + {clock: "clk_esc_i", reset: "rst_esc_ni"} + ] + bus_interfaces: [ + { protocol: "tlul", direction: "device" } + ], + interrupt_list: [ + { name: "wakeup", desc: "Wake from low power state. See wake info for more details" }, + ], + + inter_signal_list: [ + { struct: "pwr_ast", + type: "req_rsp", + name: "pwr_ast", + act: "req", + package: "pwrmgr_pkg", + }, + + { struct: "pwr_rst", + type: "req_rsp", + name: "pwr_rst", + act: "req", + package: "pwrmgr_pkg", + }, + + { struct: "pwr_clk", + type: "req_rsp", + name: "pwr_clk", + act: "req", + package: "pwrmgr_pkg", + }, + + { struct: "pwr_otp", + type: "req_rsp", + name: "pwr_otp", + act: "req", + package: "pwrmgr_pkg", + }, + + { struct: "pwr_lc", + type: "req_rsp", + name: "pwr_lc", + act: "req", + package: "pwrmgr_pkg", + }, + + { struct: "pwr_flash", + type: "req_rsp", + name: "pwr_flash", + act: "req", + package: "pwrmgr_pkg", + }, + + { struct: "esc_tx", + type: "uni", + name: "esc_rst_tx", + act: "rcv", + package: "prim_esc_pkg", + }, + + { struct: "esc_rx", + type: "uni", + name: "esc_rst_rx", + act: "req", + package: "prim_esc_pkg", + }, + + { struct: "pwr_cpu", + type: "uni", + name: "pwr_cpu", + act: "rcv", + package: "pwrmgr_pkg", + }, + + { struct: "logic", + width: 1, + type: "uni", + name: "wakeups", + act: "rcv", + package: "", + }, + + { struct: "logic", + width: 1, + type: "uni", + name: "rstreqs", + act: "rcv", + package: "", + }, + + ], + + param_list: [ + { name: "NumWkups", + desc: "Number of wakeups", + type: "int", + default: "1", + local: "true" + }, + { name: "NumRstReqs", + desc: "Number of reset requets", + type: "int", + default: "1", + local: "true" + }, + ], + + countermeasures: [ + { name: "BUS.INTEGRITY", + desc: "End-to-end bus integrity scheme." + } + { name: "LC_CTRL.INTERSIG.MUBI", + desc: "life cycle control / debug signals are multibit." + } + { name: "ROM_CTRL.INTERSIG.MUBI", + desc: "rom control done/good signals are multibit." + } + { name: "RSTMGR.INTERSIG.MUBI", + desc: "reset manager software request is multibit." + } + { name: "ESC_RX.CLK.BKGN_CHK", + desc: "Escalation receiver has a background timeout check" + } + { name: "ESC_RX.CLK.LOCAL_ESC", + desc: "Escalation receiver clock timeout has a local reset escalation" + } + { name: "FSM.SPARSE", + desc: "Sparse encoding for slow and fast state machines." + } + { name: "FSM.TERMINAL", + desc: "When FSMs reach a bad state, escalate directly and force user reset." + } + { name: "CTRL_FLOW.GLOBAL_ESC", + desc: "When global escalation is received, proceed directly to reset." + } + { name: "MAIN_PD.RST.LOCAL_ESC", + desc: "When main power domain reset glitches, proceed directly to reset." + } + { name: "CTRL.CONFIG.REGWEN", + desc: "Main control protected by regwen." + } + { name: "WAKEUP.CONFIG.REGWEN", + desc: "Wakeup configuration protected by regwen." + } + { name: "RESET.CONFIG.REGWEN", + desc: "Reset configuration protected by regwen." + } + + ] + + regwidth: "32", + registers: [ + + { name: "CTRL_CFG_REGWEN", + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + desc: ''' + Controls the configurability of the !!CONTROL register. + + This register ensures the contents do not change once a low power hint and + WFI has occurred. + + It unlocks whenever a low power transition has completed (transition back to the + ACTIVE state) for any reason. + ''', + + fields: [ + { bits: "0", + name: "EN", + desc: ''' + Configuration enable. + + This bit defaults to 1 and is set to 0 by hardware when low power entry is initiated. + When the device transitions back from low power state to active state, this bit is set + back to 1 to allow software configuration of !!CONTROL + ''', + resval: "1", + }, + ] + tags: [// This regwen is completely under HW management and thus cannot be manipulated + // by software. + "excl:CsrNonInitTests:CsrExclCheck"] + }, + + + { name: "CONTROL", + desc: "Control register", + swaccess: "rw", + hwaccess: "hro", + regwen: "CTRL_CFG_REGWEN", + fields: [ + { bits: "0", + hwaccess: "hrw", + name: "LOW_POWER_HINT", + desc: ''' + The low power hint to power manager. + The hint is an indication for how the manager should treat the next WFI. + Once the power manager begins a low power transition, or if a valid reset request is registered, + this bit is automatically cleared by HW. + ''' + resval: "0" + enum: [ + { value: "0", + name: "None", + desc: ''' + No low power intent + ''' + }, + { value: "1", + name: "Low Power", + desc: ''' + Next WFI should trigger low power entry + ''' + }, + ] + tags: [// The regwen for this reg is RO. CSR seq can't support to check this reg + "excl:CsrAllTests:CsrExclAll"] + }, + + { bits: "4", + name: "CORE_CLK_EN", + desc: "core clock enable during low power state", + resval: "0" + enum: [ + { value: "0", + name: "Disabled", + desc: ''' + Core clock disabled during low power state + ''' + }, + { value: "1", + name: "Enabled", + desc: ''' + Core clock enabled during low power state + ''' + }, + ] + }, + + { bits: "5", + name: "IO_CLK_EN", + desc: "IO clock enable during low power state", + resval: "0" + enum: [ + { value: "0", + name: "Disabled", + desc: ''' + IO clock disabled during low power state + ''' + }, + { value: "1", + name: "Enabled", + desc: ''' + IO clock enabled during low power state + ''' + }, + ] + }, + + { bits: "6", + name: "USB_CLK_EN_LP", + desc: "USB clock enable during low power state", + resval: "0", + enum: [ + { value: "0", + name: "Disabled", + desc: ''' + USB clock disabled during low power state + ''' + }, + { value: "1", + name: "Enabled", + desc: ''' + USB clock enabled during low power state + ''' + }, + ] + }, + + { bits: "7", + name: "USB_CLK_EN_ACTIVE", + desc: "USB clock enable during active power state", + resval: "1" + enum: [ + { value: "0", + name: "Disabled", + desc: ''' + USB clock disabled during active power state + ''' + }, + { value: "1", + name: "Enabled", + desc: ''' + USB clock enabled during active power state + ''' + }, + ] + tags: [// Turning off USB clock in active state impacts other CSRs + // at the chip level (in other blocks, such as clkmgr). + "excl:CsrNonInitTests:CsrExclWrite"] + }, + + { bits: "8", + name: "MAIN_PD_N", + desc: "Active low, main power domain power down", + resval: "1" + enum: [ + { value: "0", + name: "Power down", + desc: ''' + Main power domain is powered down during low power state + ''' + }, + { value: "1", + name: "Power up", + desc: ''' + Main power domain is kept powered during low power state + ''' + }, + ] + }, + + + ], + }, + + { name: "CFG_CDC_SYNC", + swaccess: "rw", + hwaccess: "hrw", + hwqe: "true", + desc: ''' + The configuration registers CONTROL, WAKEUP_EN, RESET_EN are all written in the + fast clock domain but used in the slow clock domain. + + The configuration are not propogated across the clock boundary until this + register is triggered and read. See fields below for more details + ''', + + fields: [ + { bits: "0", + name: "SYNC", + desc: ''' + Configuration sync. When this bit is written to 1, a sync pulse is generated. When + the sync completes, this bit then self clears. + + Software should write this bit to 1, wait for it to clear, before assuming the slow clock + domain has assumed the programmed values. + ''', + resval: "0", + }, + ] + tags: [// This bit triggers a payload synchronization and self clears when complete. + // Do not write this bit as there will be side effects and the value will not persist + "excl:CsrNonInitTests:CsrExclCheck"] + }, + + { name: "WAKEUP_EN_REGWEN", + desc: "Configuration enable for wakeup_en register", + swaccess: "rw0c", + hwaccess: "none", + fields: [ + { bits: "0", + resval: "1" + name: "EN", + desc: ''' + When 1, WAKEUP_EN register can be configured. + When 0, WAKEUP_EN register cannot be configured. + ''', + }, + ] + }, + + { multireg: + { name: "WAKEUP_EN", + desc: "Bit mask for enabled wakeups", + swaccess: "rw", + hwaccess: "hro", + regwen: "WAKEUP_EN_REGWEN", + resval: "0" + cname: "wakeup_en", + count: "NumWkups" + fields: [ + { bits: "0", + name: "EN", + desc: ''' + Whenever a particular bit is set to 1, that wakeup is also enabled. + Whenever a particular bit is set to 0, that wakeup cannot wake the device from low power. + ''', + }, + ] + }, + }, + + { multireg: + { name: "WAKE_STATUS", + desc: "A read only register of all current wake requests post enable mask", + swaccess: "ro", + hwaccess: "hwo", + resval: "0" + cname: "wake_status", + count: "NumWkups", + tags: [// Cannot auto-predict current wake request status + "excl:CsrNonInitTests:CsrExclWriteCheck"], + fields: [ + { bits: "0", + name: "VAL", + desc: ''' + Current value of wake requests + ''', + }, + ] + }, + }, + + { name: "RESET_EN_REGWEN", + desc: "Configuration enable for reset_en register", + swaccess: "rw0c", + hwaccess: "none", + fields: [ + { bits: "0", + resval: "1" + name: "EN", + desc: ''' + When 1, RESET_EN register can be configured. + When 0, RESET_EN register cannot be configured. + ''', + }, + ] + }, + + { multireg: + { name: "RESET_EN", + desc: "Bit mask for enabled reset requests", + swaccess: "rw", + hwaccess: "hro", + regwen: "RESET_EN_REGWEN", + resval: "0" + cname: "rstreq_en", + count: "NumRstReqs" + fields: [ + { bits: "0", + name: "EN", + desc: ''' + Whenever a particular bit is set to 1, that reset request is enabled. + Whenever a particular bit is set to 0, that reset request cannot reset the device. + ''', + }, + ] + }, + }, + + { multireg: + { name: "RESET_STATUS", + desc: "A read only register of all current reset requests post enable mask", + swaccess: "ro", + hwaccess: "hwo", + resval: "0" + cname: "reset_status", + count: "NumRstReqs", + fields: [ + { bits: "0", + name: "VAL", + desc: ''' + Current value of reset request + ''', + }, + ] + }, + }, + + { name: "WAKE_INFO_CAPTURE_DIS", + desc: "Disables capture by WAKE_INFO", + swaccess: "rw", + hwaccess: "hro", + resval: "0" + fields: [ + { bits: "0", + name: "VAL", + desc: ''' + When written to 1, WAKE INFO capture is suppressed. + When written to 0, WAKE_INFO capture is controlled by HW. + ''', + }, + ] + }, + + { name: "WAKE_INFO", + desc: ''' + Indicates which functions caused the chip to wakeup. + + This register starts recording upon a valid low power entry with WAKE_INFO_CAPTURE_DIS off. + Capture continues until it is explicitly disabled by setting WAKE_INFO_CAPTURE_DIS. + This means it is possible to capture multiple wakeup reasons. + ''', + swaccess: "rw1c", + hwaccess: "hrw", + hwext: "true", + hwqe: "true", + resval: "0" + fields: [ + { bits: "0:0", + name: "REASONS", + desc: "Various peripheral wake reasons" + }, + { bits: "1", + name: "FALL_THROUGH", + desc: ''' + The fall through wakeup reason indicates that despite setting a WFI and providing a low power + hint, an interrupt arrived at just the right time to break the executing core out of WFI. + + The power manager detects this condition, halts low power entry and reports as a wakeup reason + ''', + }, + { bits: "2", + name: "ABORT", + desc: ''' + The abort wakeup reason indicates that despite setting a WFI and providing a low power + hint, an active flash / lifecycle / otp transaction was ongoing when the power controller + attempted to initiate low power entry. + + The power manager detects this condition, halts low power entry and reports as a wakeup reason + ''', + }, + ] + tags: [// This regwen is completely under HW management and thus cannot be manipulated + // by software. + "excl:CsrNonInitTests:CsrExclCheck"] + }, + ] +} diff --git a/src/pwrmgr/data/pwrmgr.hjson.tpl b/src/pwrmgr/data/pwrmgr.hjson.tpl new file mode 100644 index 0000000..1c75a72 --- /dev/null +++ b/src/pwrmgr/data/pwrmgr.hjson.tpl @@ -0,0 +1,807 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +<% + # Additional reset + int_reset_reqs = rst_reqs["int"] + debug_reset_reqs = rst_reqs["debug"] +%>\ +{ + name: "pwrmgr", + human_name: "Power Manager", + one_line_desc: "Sequences on-chip power, clocks, and resets through different reset and power states", + one_paragraph_desc: ''' + Power Manager sequences on-chip power, clocks, and reset signals on power-on reset (aka cold boot), low power entry and exit, and non-power-on resets. + To this end, it can turn power domains on and off, control root resets with Reset Manager, and control root clock enables with AST and Clock Manager. + During power up, Power Manager is responsible for triggering OTP sensing, initiating Life Cycle Controller, coordinating with ROM Controller for the startup ROM check, and eventually releasing software to execute. + It features several countermeasures to deter fault injection (FI) attacks. + ''' + // Unique comportable IP identifier defined under KNOWN_CIP_IDS in the regtool. + cip_id: "20", + design_spec: "../doc", + dv_doc: "../doc/dv", + hw_checklist: "../doc/checklist", + sw_checklist: "/sw/device/lib/dif/dif_pwrmgr", + revisions: [ + { + version: "0.1.0", + life_stage: "L1", + design_stage: "D1", + verification_stage: "V0", // this module is not verified at the block level + dif_stage: "S0", + commit_id: "b2abc989498f072d9a5530f8aab9b58c1f92c9fb" + } + { + version: "1.0.0", + life_stage: "L1", + design_stage: "D2S", + verification_stage: "V2S", + dif_stage: "S2", + } + ] + clocking: [ + {clock: "clk_i", reset: "rst_ni", primary: true}, + {reset: "rst_main_ni"}, + {clock: "clk_slow_i", reset: "rst_slow_ni"}, + {clock: "clk_lc_i", reset: "rst_lc_ni"}, + {clock: "clk_esc_i", reset: "rst_esc_ni"} + ] + bus_interfaces: [ + { protocol: "tlul", direction: "device" } + ], + interrupt_list: [ + { name: "wakeup", desc: "Wake from low power state. See wake info for more details" }, + ], + alert_list: [ + { name: "fatal_fault", + desc: ''' + This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected. + ''' + } + ], + features: [ + { name: "PWRMGR.STARTUP.LIFE_CYCLE_INITIALIZATION", + desc: "Wait completion of Life Cycle initialization." + } + { name: "PWRMGR.CLOCK_CONTROL.IO_IN_LOW_POWER", + desc: '''Controls whether the IO clock remains active in + low power mode. + ''' + } + { name: "PWRMGR.CLOCK_CONTROL.MAIN_IN_LOW_POWER", + desc: '''Controls whether the MAIN clock remains active in + low power mode. + ''' + } + { name: "PWRMGR.CLOCK_CONTROL.USB_IN_LOW_POWER", + desc: '''Controls whether the USB clock remains active in + low power mode. + ''' + } + { name: "PWRMGR.CLOCK_CONTROL.USB_WHEN_ACTIVE", + desc: "Controls whether the USB clock is enabled in active state." + } + { name: "PWRMGR.LOW_POWER.ENTRY", + desc: '''Controls of low power entry, and cases when low power is + not entered due to interrupts or specific units getting busy. + ''' + } + { name: "PWRMGR.LOW_POWER.DISABLE_POWER" + desc: '''Controls whether power is turned off for non-AON domains when + in low power. + ''' + } +% for wkup in Wkups: +<% + wakeup_name = wkup["module"].upper() + "_" + wkup["name"].upper() +%>\ + { name: "PWRMGR.LOW_POWER.${wakeup_name}_WAKEUP_ENABLE" + desc: "Enable wakeup request ${wkup["name"]} from ${wkup["module"]}." + } + { name: "PWRMGR.LOW_POWER.${wakeup_name}_WAKEUP_REQUEST" + desc: "Wakeup request ${wkup["name"]} from ${wkup["module"]}." + } +% endfor + { name: "PWRMGR.LOW_POWER.WAKE_INFO" + desc: "Record what caused the chip to wakeup from low power." + } + { name: "PWRMGR.RESET.CHECK_ROM_INTEGRITY", + desc: "Wait for successful completion of ROM integrity checks." + } +% for reset in rst_reqs["peripheral"]: +<% + description = reset["desc"] + reset_name = reset["module"].upper() + "_" + reset["name"].upper() + description = description[:1].upper() + description[1:].rstrip(".") +%>\ + { name: "PWRMGR.RESET.${reset_name}_ENABLE", + desc: "Enable reset request from ${reset["module"]}." + } + { name: "PWRMGR.RESET.${reset_name}_REQUEST", + desc: "Reset request from ${reset["module"]}." + } +% endfor + { name: "PWRMGR.RESET.ESCALATION_REQUEST", + desc: "Trigger reset in response to incoming escalation requests." + } + { name: "PWRMGR.RESET.ESCALATION_TIMEOUT", + desc: "Trigger reset in response to non-responsive escalation network." + } + { name: "PWRMGR.RESET.SW_RST_REQUEST", + desc: "Trigger reset in response to rstmgr's sw reset request." + } + { name: "PWRMGR.RESET.MAIN_POWER_GLITCH_RESET", + desc: "Trigger reset in response to glitch in main power." + } + { name: "PWRMGR.RESET.NDM_RESET_REQUEST", + desc: "Trigger reset in response to RV_DM ndm reset." + } + { name: "PWRMGR.RESET.POR_REQUEST", + desc: "Trigger reset in response to POR_N pin." + } + ] + + inter_signal_list: [ + { struct: "pwr_ast", + type: "req_rsp", + name: "pwr_ast", + act: "req", + package: "pwrmgr_pkg", + }, + + { struct: "pwr_rst", + type: "req_rsp", + name: "pwr_rst", + act: "req", + package: "pwrmgr_pkg", + }, + + { struct: "pwr_clk", + type: "req_rsp", + name: "pwr_clk", + act: "req", + package: "pwrmgr_pkg", + }, + + { struct: "pwr_otp", + type: "req_rsp", + name: "pwr_otp", + act: "req", + package: "pwrmgr_pkg", + }, + + { struct: "pwr_lc", + type: "req_rsp", + name: "pwr_lc", + act: "req", + package: "pwrmgr_pkg", + }, + + { struct: "pwr_flash", + type: "uni", + name: "pwr_flash", + act: "rcv", + package: "pwrmgr_pkg", + }, + + { struct: "esc_tx", + type: "uni", + name: "esc_rst_tx", + act: "rcv", + package: "prim_esc_pkg", + }, + + { struct: "esc_rx", + type: "uni", + name: "esc_rst_rx", + act: "req", + package: "prim_esc_pkg", + }, + + { struct: "pwr_cpu", + type: "uni", + name: "pwr_cpu", + act: "rcv", + package: "pwrmgr_pkg", + }, + + { struct: "logic", + width: ${NumWkups}, + type: "uni", + name: "wakeups", + act: "rcv", + package: "", + }, + + { struct: "logic", + width: ${NumRstReqs}, + type: "uni", + name: "rstreqs", + act: "rcv", + package: "", + }, + + { struct: "logic", + type: "uni", + name: "ndmreset_req", + act: "rcv", + }, + + { struct: "logic", + type: "uni", + name: "strap", + act: "req", + package: "", + }, + + { struct: "logic", + type: "uni", + name: "low_power", + act: "req", + package: "", + }, + + { struct: "pwrmgr_data", + type: "uni", + name: "rom_ctrl", + act: "rcv", + package: "rom_ctrl_pkg", + }, + + { struct: "lc_tx", + type: "uni", + name: "fetch_en", + act: "req", + package: "lc_ctrl_pkg", + }, + + { struct: "lc_tx", + type: "uni", + name: "lc_dft_en", + act: "rcv", + package: "lc_ctrl_pkg", + }, + + { struct: "lc_tx", + type: "uni", + name: "lc_hw_debug_en", + act: "rcv", + package: "lc_ctrl_pkg", + }, + + { struct: "mubi4", + type: "uni", + name: "sw_rst_req", + act: "rcv", + package: "prim_mubi_pkg", + }, + ], + + param_list: [ + { name: "NumWkups", + desc: "Number of wakeups", + type: "int", + default: "${NumWkups}", + local: "true" + }, + + % for wkup in Wkups: + { name: "${wkup['module'].upper()}_${wkup['name'].upper()}_IDX", + desc: "Vector index for ${wkup['module']} ${wkup['name']}, applies for WAKEUP_EN, WAKE_STATUS and WAKE_INFO", + type: "int", + default: "${loop.index}", + local: "true" + }, + + % endfor + + { name: "NumRstReqs", + desc: "Number of peripheral reset requets", + type: "int", + default: "${NumRstReqs}", + local: "true" + }, + + { name: "NumIntRstReqs", + desc: "Number of pwrmgr internal reset requets", + type: "int", + default: "${len(int_reset_reqs)}", + local: "true" + }, + + { name: "NumDebugRstReqs", + desc: "Number of debug reset requets", + type: "int", + default: "${len(debug_reset_reqs)}", + local: "true" + }, + + % for req in int_reset_reqs + debug_reset_reqs: + { name: "${f"Reset{req['name']}Idx"}", + desc: "Reset req idx for ${req['name']}", + type: "int", + default: "${loop.index + NumRstReqs}", + local: "true" + }, + % endfor + + ], + countermeasures: [ + { name: "BUS.INTEGRITY", + desc: "End-to-end bus integrity scheme." + } + { name: "LC_CTRL.INTERSIG.MUBI", + desc: "life cycle control / debug signals are multibit." + } + { name: "ROM_CTRL.INTERSIG.MUBI", + desc: "rom control done/good signals are multibit." + } + { name: "RSTMGR.INTERSIG.MUBI", + desc: "reset manager software request is multibit." + } + { name: "ESC_RX.CLK.BKGN_CHK", + desc: "Escalation receiver has a background timeout check" + } + { name: "ESC_RX.CLK.LOCAL_ESC", + desc: "Escalation receiver clock timeout has a local reset escalation" + } + { name: "FSM.SPARSE", + desc: "Sparse encoding for slow and fast state machines." + } + { name: "FSM.TERMINAL", + desc: ''' + When FSMs reach a bad state, go into a terminate state that does not + recover without user or external host intervention. + ''' + } + { name: "CTRL_FLOW.GLOBAL_ESC", + desc: "When global escalation is received, proceed directly to reset." + } + { name: "MAIN_PD.RST.LOCAL_ESC", + desc: "When main power domain reset glitches, proceed directly to reset." + } + { name: "CTRL.CONFIG.REGWEN", + desc: "Main control protected by regwen." + } + { name: "WAKEUP.CONFIG.REGWEN", + desc: "Wakeup configuration protected by regwen." + } + { name: "RESET.CONFIG.REGWEN", + desc: "Reset configuration protected by regwen." + } + + ] + + regwidth: "32", + registers: [ + + { name: "CTRL_CFG_REGWEN", + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + desc: ''' + Controls the configurability of the !!CONTROL register. + + This register ensures the contents do not change once a low power hint and + WFI has occurred. + + It unlocks whenever a low power transition has completed (transition back to the + ACTIVE state) for any reason. + ''', + + fields: [ + { bits: "0", + name: "EN", + desc: ''' + Configuration enable. + + This bit defaults to 1 and is set to 0 by hardware when low power entry is initiated. + When the device transitions back from low power state to active state, this bit is set + back to 1 to allow software configuration of !!CONTROL + ''', + resval: "1", + }, + ] + tags: [// This regwen is completely under HW management and thus cannot be manipulated + // by software. + "excl:CsrNonInitTests:CsrExclCheck"] + }, + + + { name: "CONTROL", + desc: "Control register", + swaccess: "rw", + hwaccess: "hro", + regwen: "CTRL_CFG_REGWEN", + tags: [// Turning off USB clock in active state impacts other CSRs + // at the chip level (in other blocks, such as clkmgr), + // so we exclude writing from this register. + "excl:CsrAllTests:CsrExclWrite"] + fields: [ + { bits: "0", + hwaccess: "hrw", + name: "LOW_POWER_HINT", + desc: ''' + The low power hint to power manager. + The hint is an indication for how the manager should treat the next WFI. + Once the power manager begins a low power transition, or if a valid reset request is registered, + this bit is automatically cleared by HW. + ''' + resval: "0" + enum: [ + { value: "0", + name: "None", + desc: ''' + No low power intent + ''' + }, + { value: "1", + name: "Low Power", + desc: ''' + Next WFI should trigger low power entry + ''' + }, + ] + tags: [// The regwen for this reg is RO. CSR seq can't support to check this reg + "excl:CsrAllTests:CsrExclAll"] + }, + + { bits: "4", + name: "CORE_CLK_EN", + desc: "core clock enable during low power state", + resval: "0" + enum: [ + { value: "0", + name: "Disabled", + desc: ''' + Core clock disabled during low power state + ''' + }, + { value: "1", + name: "Enabled", + desc: ''' + Core clock enabled during low power state + ''' + }, + ] + }, + + { bits: "5", + name: "IO_CLK_EN", + desc: "IO clock enable during low power state", + resval: "0" + enum: [ + { value: "0", + name: "Disabled", + desc: ''' + IO clock disabled during low power state + ''' + }, + { value: "1", + name: "Enabled", + desc: ''' + IO clock enabled during low power state + ''' + }, + ] + }, + + { bits: "6", + name: "USB_CLK_EN_LP", + desc: "USB clock enable during low power state", + resval: "0", + enum: [ + { value: "0", + name: "Disabled", + desc: ''' + USB clock disabled during low power state + ''' + }, + { value: "1", + name: "Enabled", + desc: ''' + USB clock enabled during low power state. + + However, if !!CONTROL.MAIN_PD_N is 0, USB clock is disabled + during low power state. + ''' + }, + ] + }, + + { bits: "7", + name: "USB_CLK_EN_ACTIVE", + desc: "USB clock enable during active power state", + resval: "1" + enum: [ + { value: "0", + name: "Disabled", + desc: ''' + USB clock disabled during active power state + ''' + }, + { value: "1", + name: "Enabled", + desc: ''' + USB clock enabled during active power state + ''' + }, + ] + }, + + { bits: "8", + name: "MAIN_PD_N", + desc: "Active low, main power domain power down", + resval: "1" + enum: [ + { value: "0", + name: "Power down", + desc: ''' + Main power domain is powered down during low power state. + ''' + }, + { value: "1", + name: "Power up", + desc: ''' + Main power domain is kept powered during low power state + ''' + }, + ] + }, + + + ], + }, + + { name: "CFG_CDC_SYNC", + swaccess: "rw", + hwaccess: "hrw", + hwqe: "true", + desc: ''' + The configuration registers CONTROL, WAKEUP_EN, RESET_EN are all written in the + fast clock domain but used in the slow clock domain. + + The configuration are not propagated across the clock boundary until this + register is triggered and read. See fields below for more details + ''', + + fields: [ + { bits: "0", + name: "SYNC", + desc: ''' + Configuration sync. When this bit is written to 1, a sync pulse is generated. When + the sync completes, this bit then self clears. + + Software should write this bit to 1, wait for it to clear, before assuming the slow clock + domain has accepted the programmed values. + ''', + resval: "0", + }, + ] + tags: [// This bit triggers a payload synchronization and self clears when complete. + // Do not write this bit as there will be side effects and the value will not persist + "excl:CsrNonInitTests:CsrExclWrite"] + }, + + { name: "WAKEUP_EN_REGWEN", + desc: "Configuration enable for wakeup_en register", + swaccess: "rw0c", + hwaccess: "none", + fields: [ + { bits: "0", + resval: "1" + name: "EN", + desc: ''' + When 1, WAKEUP_EN register can be configured. + When 0, WAKEUP_EN register cannot be configured. + ''', + }, + ] + }, + + { multireg: + { name: "WAKEUP_EN", + desc: "Bit mask for enabled wakeups", + swaccess: "rw", + hwaccess: "hro", + regwen: "WAKEUP_EN_REGWEN", + resval: "0" + cname: "wakeup_en", + count: "NumWkups" + fields: [ + { bits: "0", + name: "EN", + desc: ''' + Whenever a particular bit is set to 1, that wakeup is also enabled. + Whenever a particular bit is set to 0, that wakeup cannot wake the device from low power. + ''', + }, + ] + }, + }, + + { multireg: + { name: "WAKE_STATUS", + desc: "A read only register of all current wake requests post enable mask", + swaccess: "ro", + hwaccess: "hwo", + resval: "0" + cname: "wake_status", + count: "NumWkups", + tags: [// Cannot auto-predict current wake request status + "excl:CsrNonInitTests:CsrExclWriteCheck"], + fields: [ + { bits: "0", + name: "VAL", + desc: ''' + Current value of wake requests + ''', + }, + ] + }, + }, + + { name: "RESET_EN_REGWEN", + desc: "Configuration enable for reset_en register", + swaccess: "rw0c", + hwaccess: "none", + fields: [ + { bits: "0", + resval: "1" + name: "EN", + desc: ''' + When 1, RESET_EN register can be configured. + When 0, RESET_EN register cannot be configured. + ''', + }, + ] + }, + + { multireg: + { name: "RESET_EN", + desc: "Bit mask for enabled reset requests", + swaccess: "rw", + hwaccess: "hro", + regwen: "RESET_EN_REGWEN", + resval: "0" + cname: "rstreq_en", + count: "NumRstReqs" + fields: [ + { bits: "0", + name: "EN", + desc: ''' + Whenever a particular bit is set to 1, that reset request is enabled. + Whenever a particular bit is set to 0, that reset request cannot reset the device. + ''', + }, + ] + tags: [// Self resets should never be triggered by automated tests + "excl:CsrAllTests:CsrExclWrite"] + }, + }, + + { multireg: + { name: "RESET_STATUS", + desc: "A read only register of all current reset requests post enable mask", + swaccess: "ro", + hwaccess: "hwo", + resval: "0" + cname: "reset_status", + count: "NumRstReqs", + fields: [ + { bits: "0", + name: "VAL", + desc: ''' + Current value of reset request + ''', + }, + ] + }, + }, + + { name: "ESCALATE_RESET_STATUS", + desc: "A read only register of escalation reset request", + swaccess: "ro", + hwaccess: "hwo", + resval: "0" + fields: [ + { bits: "0", + name: "VAL", + desc: ''' + When 1, an escalation reset has been seen. + When 0, there is no escalation reset. + ''', + }, + ] + }, + + { name: "WAKE_INFO_CAPTURE_DIS", + desc: "Indicates which functions caused the chip to wakeup", + swaccess: "rw", + hwaccess: "hro", + resval: "0" + fields: [ + { bits: "0", + name: "VAL", + desc: ''' + When written to 1, this actively suppresses the wakeup info capture. + When written to 0, wakeup info capture timing is controlled by HW. + ''', + }, + ] + }, + + { name: "WAKE_INFO", + desc: ''' + Indicates which functions caused the chip to wakeup. + The wake info recording begins whenever the device begins a valid low power entry. + + This capture is continued until it is explicitly disabled through WAKE_INFO_CAPTURE_DIS. + This means it is possible to capture multiple wakeup reasons. + ''', + swaccess: "rw1c", + hwaccess: "hrw", + hwext: "true", + hwqe: "true", + resval: "0" + fields: [ + { bits: "${NumWkups-1}:0", + name: "REASONS", + desc: "Various peripheral wake reasons" + }, + { bits: "${NumWkups}", + name: "FALL_THROUGH", + desc: ''' + The fall through wakeup reason indicates that despite setting a WFI and providing a low power + hint, an interrupt arrived at just the right time to break the executing core out of WFI. + + The power manager detects this condition, halts low power entry and reports as a wakeup reason + ''', + }, + { bits: "${NumWkups+1}", + name: "ABORT", + desc: ''' + The abort wakeup reason indicates that despite setting a WFI and providing a low power + hint, an active flash / lifecycle / otp transaction was ongoing when the power controller + attempted to initiate low power entry. + + The power manager detects this condition, halts low power entry and reports as a wakeup reason + ''', + }, + ] + tags: [// This regwen is completely under HW management and thus cannot be manipulated + // by software. + "excl:CsrNonInitTests:CsrExclCheck"] + }, + + { name: "FAULT_STATUS", + desc: "A read only register that shows the existing faults", + swaccess: "ro", + hwaccess: "hrw", + sync: "clk_lc_i", + resval: "0" + fields: [ + { bits: "0", + name: "REG_INTG_ERR", + desc: ''' + When 1, an integrity error has occurred. + ''', + }, + + { bits: "1", + name: "ESC_TIMEOUT", + desc: ''' + When 1, an escalation clock / reset timeout has occurred. + ''', + }, + + { bits: "2", + name: "MAIN_PD_GLITCH", + desc: ''' + When 1, unexpected power glitch was observed on main PD. + ''', + }, + ] + }, + ] +} diff --git a/src/pwrmgr/data/pwrmgr.tpldesc.hjson b/src/pwrmgr/data/pwrmgr.tpldesc.hjson new file mode 100644 index 0000000..77ee441 --- /dev/null +++ b/src/pwrmgr/data/pwrmgr.tpldesc.hjson @@ -0,0 +1,56 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + template_param_list: [ + { + name: "topname" + desc: "Name of top-level design, e.g., 'darjeeling' or 'earlgrey'" + type: "string" + default: "" + } + { + name: "NumWkups" + desc: "Number of wakeup requests" + type: "int" + default: "6" + } + { + name: "Wkups" + desc: "A list of dictionaries describing each wakeup" + type: "object" + default: [ + { + name: "wkup_req" + width: "1" + module: "sysrst_ctrl_aon" + } + ] + } + { + name: "rst_reqs" + desc: '''A dictionary of reset requests indexed by type, as in 'peripheral', 'int', + 'debug'. + ''' + type: "object" + default: { + peripheral: [ + { + name: "rst_req" + width: "1" + module: "sysrst_ctrl_aon" + desc: "reset request running on AON clock" + } + ] + int: [] + debug: [] + } + } + { + name: "NumRstReqs" + desc: "The number of peripheral requests" + type: "int" + default: "2" + } + ] +} diff --git a/src/pwrmgr/data/pwrmgr_sec_cm_testplan.hjson b/src/pwrmgr/data/pwrmgr_sec_cm_testplan.hjson new file mode 100644 index 0000000..d867437 --- /dev/null +++ b/src/pwrmgr/data/pwrmgr_sec_cm_testplan.hjson @@ -0,0 +1,219 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Security countermeasures testplan extracted from the IP Hjson using reggen. +// +// This testplan is auto-generated only the first time it is created. This is +// because this testplan needs to be hand-editable. It is possible that these +// testpoints can go out of date if the spec is updated with new +// countermeasures. When `reggen` is invoked when this testplan already exists, +// It checks if the list of testpoints is up-to-date and enforces the user to +// make further manual updates. +// +// These countermeasures and their descriptions can be found here: +// .../pwrmgr/data/pwrmgr.hjson +// +// It is possible that the testing of some of these countermeasures may already +// be covered as a testpoint in a different testplan. This duplication is ok - +// the test would have likely already been developed. We simply map those tests +// to the testpoints below using the `tests` key. +// +// Please ensure that this testplan is imported in: +// .../pwrmgr/data/pwrmgr_testplan.hjson +{ + testpoints: [ + { + name: sec_cm_bus_integrity + desc: '''Verify the countermeasure(s) BUS.INTEGRITY. + This entry is covered by tl_access_test + (hw/dv/tools/dvsim/tests/tl_access_tests.hjson) + ''' + stage: V2S + tests: ["pwrmgr_tl_intg_err"] + } + { + name: sec_cm_lc_ctrl_intersig_mubi + desc: '''Verify the countermeasure(s) LC_CTRL.INTERSIG.MUBI. + + **Stimulus**: + - Use comprehensive stimulus - reset and wakeup - + as background traffic to ensure this counter measure + is valid for various states of fast and slow state. + - Drive lc_hw_debug_en_i and lc_dft_en_i with + mixed valid and invalid values. + + **Check**: + - Collect coverage by binding cip_mubi_cov_if to + tb.dut.lc_hw_debug_en_i and tb.dut.lc_dft_en_i + - Add assertion to check whether rom_intg_chk_dis + is set to '1' only when lc_dft_en_i or lc_hw_debug_en_i + is high. + ''' + stage: V2S + tests: ["pwrmgr_sec_cm_lc_ctrl_intersig_mubi"] + } + { + name: sec_cm_rom_ctrl_intersig_mubi + desc: '''Verify the countermeasure(s) ROM_CTRL.INTERSIG.MUBI. + + **Stimulus**: + - Use comprehensive stimulus - reset and wakeup - + as background traffic to ensure this counter measure + is valid for various states of fast and slow fsm. + - Drive rom_ctrl_i with mixed valid and invalid values. + + **Check**: + - Collect coverage by binding cip_mubi_cov_if to + tb.dut.rom_ctrl_i + ''' + stage: V2S + tests: ["pwrmgr_sec_cm_rom_ctrl_intersig_mubi"] + } + { + name: sec_cm_rstmgr_intersig_mubi + desc: '''Verify the countermeasure(s) RSTMGR.INTERSIG.MUBI. + + **Stimulus**: + - Drive tb.dut.sw_rst_req_i with mixed valid and invalid values + + **Check**: + - See sw rst only happens when dut gets valid value by + probing fast fsm state. The state has to move low power state. + - Collect coverage by binding cip_mubi_cov_if to + tb.dut.sw_rst_req_i + ''' + stage: V2S + tests: ["pwrmgr_sec_cm_rstmgr_intersig_mubi"] + } + { + name: sec_cm_esc_rx_clk_bkgn_chk + desc: '''Verify the countermeasure(s) ESC_RX.CLK.BKGN_CHK. + + **Stimulus**: + - At FastPwrStateActive state, create escalation clock + or reset failure by stopping clock or asserting reset. + + **Check**: + - Expecting fatal alert event and rstreqs[ResetEscIdx]. + - Add assertion to see if u_esc_timeout happens, then + rstreqs[ResetEscIdx] should be asserted. + - After the alert agent processese the alert + by asserting escalation reset, + see if dut is back to normal operation state. + ''' + stage: V2S + tests: ["pwrmgr_esc_clk_rst_malfunc"] + } + { + name: sec_cm_esc_rx_clk_local_esc + desc: '''Verify the countermeasure(s) ESC_RX.CLK.LOCAL_ESC. + + This is triggered by common cm primitives (SecCmPrimCount). + (https://github.com/lowRISC/opentitan/blob/master + /hw/dv/sv/cip_lib/doc/index.md#security-verification + -for-common-countermeasure-primitives) + + **Check**: + - Detect fast state transition to FastPwrStateResetPrep. + - Add assertion to check if u_sec_timeout happens, then + rstreqs[ResetEscIdx] should be asserted. + ''' + stage: V2S + tests: ["pwrmgr_sec_cm"] + } + { + name: sec_cm_fsm_sparse + desc: '''Verify the countermeasure(s) FSM.SPARSE. + This is triggered by common cm primitives (SecCmPrimSparseFsmFlop). + (https://github.com/lowRISC/opentitan/blob/master + /hw/dv/sv/cip_lib/doc/index.md#security-verification + -for-common-countermeasure-primitives) + ''' + stage: V2S + tests: ["pwrmgr_sec_cm"] + } + { + name: sec_cm_fsm_terminal + desc: '''Verify the countermeasure(s) FSM.TERMINAL. + + This is caused by any invalid (slow|fast) state. + + **Check**: + - If slow state is invalid, fast state becomes FastPwrStateInvalid, + pwr_ast_o.pwr_clamp =1 and pwr_ast_o.main_pd_n = 0. + - If fast state is invalid, pwr_rst_o.rst_lc_req is all one, + pwr_rst_o.rst_sys_req is all one and pwr_clk_o = 0. + Dut should be recovered by asserting rst_n = 0. + ''' + stage: V2S + tests: ["pwrmgr_sec_cm"] + } + { + name: sec_cm_ctrl_flow_global_esc + desc: '''Verify the countermeasure(s) CTRL_FLOW.GLOBAL_ESC. + + **Stimulus**: + - Send escalation request to esc_rst_tx_i + + **Check**: + - Check fast state transition to FastPwrStateResetPrep + - Add assertion to see if we get pwr_rst_o.rstreqs[ResetEscIdx] + set when dut receives esc_rst_tx_i + ''' + stage: V2S + tests: ["pwrmgr_global_esc"] + } + { + name: sec_cm_main_pd_rst_local_esc + desc: '''Verify the countermeasure(s) MAIN_PD.RST.LOCAL_ESC. + + **Stimulus**: + - Create power reset glitch by setting tb.dut.rst_main_ni + and tb.dut.pwr_ast_i.main_pok to 0 + + **Check**: + - Check fast state transition to FastPwrStateResetPrep + - Add assertion to see if we get pwr_rst_o.rstreqs[ResetMainPwrIdx] + ''' + stage: V2S + tests: ["pwrmgr_glitch"] + } + { + name: sec_cm_ctrl_config_regwen + desc: '''Verify the countermeasure(s) CTRL.CONFIG.REGWEN. + + **Stimulus**: + - Initiate low power transition by setting + PWRMGR.CONTROL.LOW_POWER_HINT to 1. Wait for a few cycle + to ensure the csr value propagates to slow clock domain. + Then issue csr write to PWRMGR.CONTROL + + **Check**: + - After the csr update under PWRMGR.CTRL_CFG_REGWEN = 0, + read back and check the value is not updated by + the csr update attempt. + ''' + stage: V2S + tests: ["pwrmgr_sec_cm_ctrl_config_regwen"] + } + { + name: sec_cm_wakeup_config_regwen + desc: '''Verify the countermeasure(s) WAKEUP.CONFIG.REGWEN. + + This is covered by auto csr test. + ''' + stage: V2S + tests: ["pwrmgr_csr_rw"] + } + { + name: sec_cm_reset_config_regwen + desc: '''Verify the countermeasure(s) RESET.CONFIG.REGWEN. + + This is covered by auto csr test. + ''' + stage: V2S + tests: ["pwrmgr_csr_rw"] + } + ] +} diff --git a/src/pwrmgr/data/pwrmgr_testplan.hjson b/src/pwrmgr/data/pwrmgr_testplan.hjson new file mode 100644 index 0000000..b545255 --- /dev/null +++ b/src/pwrmgr/data/pwrmgr_testplan.hjson @@ -0,0 +1,372 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + name: "pwrmgr" + // TODO: remove the common testplans if not applicable + import_testplans: ["hw/dv/tools/dvsim/testplans/csr_testplan.hjson", + "hw/dv/tools/dvsim/testplans/intr_test_testplan.hjson", + "hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson", + "hw/dv/tools/dvsim/testplans/stress_all_with_reset_testplan.hjson", + "hw/dv/tools/dvsim/testplans/sec_cm_count_testplan.hjson", + "hw/dv/tools/dvsim/testplans/sec_cm_fsm_testplan.hjson", + // TODO: Top-level specific Hjson imported here. This will likely be resolved + // once we move to IPgen flow. + "pwrmgr_sec_cm_testplan.hjson"] + testpoints: [ + { + name: smoke + desc: ''' + Smoke test exercising the pwrmgr state transitions. + + - Brings pwrmgr out of POR. + - Enables wakeup. + - Triggers SW initiated low power transition with reset settings + in `control` CSR. + - Triggers wakeup. + - Enables and triggers a reset. + - Waits for pwrmgr to be out of reset. + + **Stimulus**: + - CSR writes to `wakeup_en`, `reset_en`, and `low_power_hint`. + - Needs many input pins to line up correctly in order to prevent the + pwrmgr from waiting forever. Most of these are set in response + to outputs, and are checked by SVA. + + **Checks**: + - The fast fsm becomes active when `fetch_en_o` output rises. + - The wakeup and reset causes are as expected reading CSRs + `wake_status` and `reset_status`. + - The output `pwr_rst_req.reset_cause` matches a low power or + reset cause. + - The output `pwr_rst_req.rstreqs` matches the enabled resets. + ''' + stage: V1 + tests: ["pwrmgr_smoke"] + } + { + name: wakeup + desc: ''' + Test random wakeup, wakeup_en, wake_info_capture_dis, and + interrupt. + + The different wakeup inputs can be disabled via bits in the + `wakeup_en` CSR. Update of `wakeup_info` can be disabled + via the `wake_info_capture_dis` CSR. Any wakeup causes an + interrupt unless interrupts are disabled. + + **Stimulus**: + - Sets `wakeup_en` randomly but don't set it to zero, or the + test will timeout. + - Set `wake_info_capture_dis` randomly on and off. + - Bring pwrmgr to low power. + - Set `wakeups_i` inputs randomly. + - Set `intr_enable` randomly. + + **Checks**: + - The fast fsm becomes active when `fetch_en_o` output rises. + - Depending on `wakeups_i`: + - If all wakeups are disabled, wait some time checking the + state remains inactive. + - Set `wakeups_i` so at least one is enabled. + - Checks `wakeup_status` CSR during transition to active state + since the reset involved will clear the wakeups_i input. + - Checks the `wake_info` CSR. + - Checks the output `pwr_rst_req.reset_cause` is `LowPwrEntry`. + - Check that `intr_wakeup_o` is set according to `intr_enable` CSR. + - Coverage collected by `wakeup_cg` and `wakeup_intr_cg`. + ''' + stage: V2 + tests: ["pwrmgr_wakeup"] + } + { + name: control_clks + desc: ''' + Test CSR control of peripheral clocks during low power. + + The peripheral clocks can be configured to remain on or be turned + off during low power with bits in the `control` CSR register. The + usb clock can also be configured off in active mode. + + **Stimulus**: + - Sets these control bits at random. + - Cause a low power transition and wakeup. + + **Checks**: + - The clock enable outputs to the AST clocks during a low + power transition match the control bits. + - The usb clock enable is also checked during active mode against + the control register. + ''' + stage: V2 + tests: ["pwrmgr_wakeup"] + } + { + name: aborted_low_power + desc: ''' + Test aborted low power transitions. + + Low power transitions can be aborted in two cases: + - The processor gets an interrupt soon after a low power entry is + triggered. + - OTP, LC, or FLASH are not idle. + This test aborts low power transitions, and disables any wakeups, + so the test would timeout if low power was entered. + + **Stimulus**: + - Bring pwrmgr to low power. + - Either disable `pwr_cpu.core_sleeping` or keep some of `lc_idle`, + `otp_idle`, or `flash_idle` inputs off. + - Disable all wakeup enables. + - Randomly set `wakeup_info_capture_dis` CSR. + + **Checks**: + - The `ctrl_cfg_regwen` CSR reads as 1 on the first attempt. + - Checks the output `pwr_rst_req.reset_cause` doesn't change for + a bounded amount of time. + - Check that the `wakeup_info` CSR flags either `fall_through` or + `abort` events when capture is enabled. + ''' + stage: V2 + tests: ["pwrmgr_aborted_low_power", "pwrmgr_lowpower_invalid"] + } + { + name: reset + desc: ''' + Test random reset and reset_en. + + Conditional reset inputs can be disabled via bits in the `reset_en` + CSR, while escalation and main power are unconditional. Resets can + be triggered either in active or low power state. + + **Stimulus**: + - Sets `reset_en` randomly. + - Randomly choose whether to put the unit in low power mode. + - Generate resets randomly in value and time: + - Conditionals via rstreqs_i, + - Main power glitch via rst_main_ni. + - Escalation via `esc_rst_tx_i`. + - Sw reset from rstmgr via `sw_rst_req_i`. + + **Checks**: + - The fast fsm becomes active when `fetch_en_o` output rises. + - Checks the `reset_status` CSRs. + - Checks `ip_clk_en` output has a low transition. + - SVA that when `pwr_rst_req.reset_cause` is HwReq, and the output + `pwr_rst_req.rstreqs` matches the unconditional and enabled + conditional resets inputs. + ''' + stage: V2 + tests: ["pwrmgr_reset", "pwrmgr_reset_invalid"] + } + { + name: main_power_glitch_reset + desc: ''' + Test reset due to a glitch in main power. + + A power glitch causes an unconditional reset. + + **Stimulus**: + - Set the rst_main_ni input low indicating a main power glitch. + + **Checks**: + - The fast fsm becomes active when `fetch_en_o` output rises. + - Checks the `reset_status` CSRs. + - Checks `ip_clk_en` output has a low transition. + - Checks the output `pwr_rst_req.reset_cause` matches HwReq. + - Checks the output `pwr_rst_req.rstreqs` matches power glitch. + ''' + stage: V2 + tests: ["pwrmgr_reset"] + } + { + name: reset_wakeup_race + desc: ''' + Test wakeup from low power and reset request almost coinciding. + + If a wakeup from low power and a reset occur at nearly the same time + the system handles them one at a time. + + **Stimulus**: + - Trigger reset and wakeup from low power as described for other + testpoints. + - Issue reset and wakeup a random number of cycles after the slow + state machine is in LowPower state. + - This also checks them coinciding. + + **Check**: + - Similar tests as for the wakeup and reset testpoints, except + making sure they happen per the triggering order. + ''' + stage: V2 + tests: ["pwrmgr_wakeup_reset"] + } + { + name: lowpower_wakeup_race + desc: ''' + Test wakeups coming close to lowpower entry. + + If low power entry and a wakeup are closely aligned the hardware + could get confused. Notice this is very unlikely, since wakeup is + only sensed when the slow fsm is in LowPower state. + + **Stimulus**: + - Trigger low power entry as described for other testpoints. + - Have all wakeups enabled. + - Assert wakeups_i in the temporal neighborhood of low power + entry. + + **Check**: + - No timeout occurs. + - Either pwrmgr remains active or a full low power cycle occurs. + ''' + stage: V2 + tests: ["pwrmgr_lowpower_wakeup_race"] + } + { + name: disable_rom_integrity_check + desc: ''' + Test rom integrity check is disabled under life cycle test states. + + While running a series of reset event, at FastPwrStateRomCheck + state, + - Drive lc_hw_debug_en_i and lc_dft_en_i to random value + excluding {lc_ctrl_pkg::On, lc_ctrl_pkg::On} for both ports. + - Set rom_ctrl_i.good = Mubi4False. + - Wait for a while to make sure fsm state check is not FastPwrStateActive. + + Then, + - Drive lc_hw_debug_en_i and lc_dft_en_i to {lc_ctrl_pkg::On, lc_ctrl_pkg::On} + - Check test finish gracefully. + + Try these steps with different lc_ctrl inputs. + ''' + stage: V2 + tests: ["pwrmgr_disable_rom_integrity_check"] + } + { + name: escalation_timeout + desc: '''This tests the escalation timeout feature. + + If the escalation network doesn't respond to an outgoing "health" + requests within 128 cycles pwrmgr should issue an escalation reset + request. + + **Stimulus**: + - Cause the external escalation network to stop responding, either + disabling the clock or jamming the differential pairs. + + **Check**: + - After 128 cycles of inactivity an escalation reset should be + triggered. + ''' + stage: V3 + tests: ["pwrmgr_escalation_timeout"] + } + { + name: stress_all + desc: '''This runs random sequences in succession. + + Randomly chooses from the following sequences: + - pwrmgr_aborted_low_power_vseq + - pwrmgr_lowpower_wakeup_race_vseq + - pwrmgr_reset_vseq + - pwrmgr_smoke_vseq + - pwrmgr_wakeup_reset_vseq + - pwrmgr_wakeup_vseq + ''' + stage: V2 + tests: ["pwrmgr_stress_all"] + } + ] + + covergroups: [ + { + name: wakeup_ctrl_cg + desc: ''' + Collects coverage on wakeup enable and capture functionality. + + This is collected per individual wakeup bit. Covergroup contains + coverpoints for the `wakeup_en` CSR bit, `wakeup_info_capture_dis` + CSR, `wakeups_i` input bit, and `wakeup_status` CSR bit, and their + cross. + ''' + } + { + name: wakeup_intr_cg + desc: ''' + Collects coverage on interrupts for wakeup functionality. + + This is collected per individual wakeup bit. Covergroup contains + coverpoints for the `intr_en` CSR, the `wakeup_status` CSR bit, + the `intr_status` CSR, the output `intr_wakeup` port, and their + cross. + ''' + } + { + name: control_cg + desc: ''' + Collects coverage on clock and power bits from `control` CSR during + a lowpower transition and active state. + ''' + } + { + name: hw_reset_0_cg + desc: ''' + Collects coverage related to external reset `0`. + + Covergroup contains coverpoints for the `rstreqs_i[0]` external + reset input, its corresponding bit in `reset_en` CSR, and whether + this reset is asserted during low power state, and suitable crosses. + ''' + } + { + name: hw_reset_1_cg + desc: ''' + Collects coverage related to external reset `1`. + + Covergroup contains coverpoints for the `rstreqs_i[1]` external + reset input, its corresponding bit in `reset_en` CSR, and whether + this reset is asserted during low power state, and suitable crosses. + ''' + } + { + name: rstmgr_sw_reset_cg + desc: ''' + Collects coverage on the software reset from rstmgr. + + Covergroup contains a coverpoint for the input `sw_rst_req_i` from + rstmgr. + ''' + } + { + name: main_power_reset_cg + desc: ''' + Collects coverage on resets due to a main power glitch. + + Covergroup contains a coverpoint for the input `rst_main_i` that + triggers a power glitch reset, and whether this reset is asserted + during low power state. + ''' + } + { + name: esc_reset_cg + desc: ''' + Collects coverage on resets due to escalation. + + Covergroup contains a coverpoint for the input `esc_rst_tx_i` that + triggers an escalation reset, and whether this reset is asserted + during low power state. + ''' + } + { + name: reset_wakeup_distance_cg + desc: ''' + Covergroup contains a coverpoint for the difference between the + cycles when the reset and the wakeup were received in the inputs. + The difference is positive when reset happened after wakeup, and + zero when the two happened at the same clock cycle. + ''' + } + ] +} diff --git a/src/pwrmgr/doc/checklist.md b/src/pwrmgr/doc/checklist.md new file mode 100644 index 0000000..1fe8d2a --- /dev/null +++ b/src/pwrmgr/doc/checklist.md @@ -0,0 +1,266 @@ +# PWRMGR Checklist + +This checklist is for [Hardware Stage](../../../../../doc/project_governance/development_stages.md) transitions for the [PWRMGR peripheral.](../README.md) +All checklist items refer to the content in the [Checklist.](../../../../../doc/project_governance/checklist/README.md) + +## Design Checklist + +### D1 + +Type | Item | Resolution | Note/Collaterals +--------------|--------------------------------|-------------|------------------ +Documentation | [SPEC_COMPLETE][] | Done |[PWRMGR Design Spec](../README.md) +Documentation | [CSR_DEFINED][] | Done | +RTL | [CLKRST_CONNECTED][] | Done | +RTL | [IP_TOP][] | Done | +RTL | [IP_INSTANTIABLE][] | Done | +RTL | [PHYSICAL_MACROS_DEFINED_80][] | N/A | +RTL | [FUNC_IMPLEMENTED][] | Done | +RTL | [ASSERT_KNOWN_ADDED][] | Done | +Code Quality | [LINT_SETUP][] | Done | + +[SPEC_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#spec_complete +[CSR_DEFINED]: ../../../../../doc/project_governance/checklist/README.md#csr_defined +[CLKRST_CONNECTED]: ../../../../../doc/project_governance/checklist/README.md#clkrst_connected +[IP_TOP]: ../../../../../doc/project_governance/checklist/README.md#ip_top +[IP_INSTANTIABLE]: ../../../../../doc/project_governance/checklist/README.md#ip_instantiable +[PHYSICAL_MACROS_DEFINED_80]: ../../../../../doc/project_governance/checklist/README.md#physical_macros_defined_80 +[FUNC_IMPLEMENTED]: ../../../../../doc/project_governance/checklist/README.md#func_implemented +[ASSERT_KNOWN_ADDED]: ../../../../../doc/project_governance/checklist/README.md#assert_known_added +[LINT_SETUP]: ../../../../../doc/project_governance/checklist/README.md#lint_setup + +### D2 + +Type | Item | Resolution | Note/Collaterals +--------------|---------------------------|-------------|------------------ +Documentation | [NEW_FEATURES][] | Done | +Documentation | [BLOCK_DIAGRAM][] | Done | +Documentation | [DOC_INTERFACE][] | Done | +Documentation | [DOC_INTEGRATION_GUIDE][] | Waived | This checklist item has been added retrospectively. +Documentation | [MISSING_FUNC][] | Done | +Documentation | [FEATURE_FROZEN][] | Done | +RTL | [FEATURE_COMPLETE][] | Done | +RTL | [PORT_FROZEN][] | Done | +RTL | [ARCHITECTURE_FROZEN][] | Done | +RTL | [REVIEW_TODO][] | Done | +RTL | [STYLE_X][] | Done | +RTL | [CDC_SYNCMACRO][] | N/A | +Code Quality | [LINT_PASS][] | Done | +Code Quality | [CDC_SETUP][] | Waived | No block-level flow available - waived to top-level signoff. +Code Quality | [RDC_SETUP][] | Waived | No block-level flow available - waived to top-level signoff. +Code Quality | [AREA_CHECK][] | Done | +Code Quality | [TIMING_CHECK][] | Done | +Security | [SEC_CM_DOCUMENTED][] | Done | + +[NEW_FEATURES]: ../../../../../doc/project_governance/checklist/README.md#new_features +[BLOCK_DIAGRAM]: ../../../../../doc/project_governance/checklist/README.md#block_diagram +[DOC_INTERFACE]: ../../../../../doc/project_governance/checklist/README.md#doc_interface +[DOC_INTEGRATION_GUIDE]: ../../../../../doc/project_governance/checklist/README.md#doc_integration_guide +[MISSING_FUNC]: ../../../../../doc/project_governance/checklist/README.md#missing_func +[FEATURE_FROZEN]: ../../../../../doc/project_governance/checklist/README.md#feature_frozen +[FEATURE_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#feature_complete +[PORT_FROZEN]: ../../../../../doc/project_governance/checklist/README.md#port_frozen +[ARCHITECTURE_FROZEN]: ../../../../../doc/project_governance/checklist/README.md#architecture_frozen +[REVIEW_TODO]: ../../../../../doc/project_governance/checklist/README.md#review_todo +[STYLE_X]: ../../../../../doc/project_governance/checklist/README.md#style_x +[CDC_SYNCMACRO]: ../../../../../doc/project_governance/checklist/README.md#cdc_syncmacro +[LINT_PASS]: ../../../../../doc/project_governance/checklist/README.md#lint_pass +[CDC_SETUP]: ../../../../../doc/project_governance/checklist/README.md#cdc_setup +[RDC_SETUP]: ../../../../../doc/project_governance/checklist/README.md#rdc_setup +[AREA_CHECK]: ../../../../../doc/project_governance/checklist/README.md#area_check +[TIMING_CHECK]: ../../../../../doc/project_governance/checklist/README.md#timing_check +[SEC_CM_DOCUMENTED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_documented + +### D2S + + Type | Item | Resolution | Note/Collaterals +--------------|------------------------------|-------------|------------------ +Security | [SEC_CM_ASSETS_LISTED][] | Done | +Security | [SEC_CM_IMPLEMENTED][] | Done | +Security | [SEC_CM_RND_CNST][] | N/A | +Security | [SEC_CM_NON_RESET_FLOPS][] | Done | +Security | [SEC_CM_SHADOW_REGS][] | Done | +Security | [SEC_CM_RTL_REVIEWED][] | Done | +Security | [SEC_CM_COUNCIL_REVIEWED][] | Done | + +[SEC_CM_ASSETS_LISTED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_assets_listed +[SEC_CM_IMPLEMENTED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_implemented +[SEC_CM_RND_CNST]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_rnd_cnst +[SEC_CM_NON_RESET_FLOPS]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_non_reset_flops +[SEC_CM_SHADOW_REGS]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_shadow_regs +[SEC_CM_RTL_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_rtl_reviewed +[SEC_CM_COUNCIL_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_council_reviewed + +### D3 + + Type | Item | Resolution | Note/Collaterals +--------------|-------------------------|-------------|------------------ +Documentation | [NEW_FEATURES_D3][] | Not Started | +RTL | [TODO_COMPLETE][] | Not Started | +Code Quality | [LINT_COMPLETE][] | Not Started | +Code Quality | [CDC_COMPLETE][] | Not Started | +Code Quality | [RDC_COMPLETE][] | Not Started | +Review | [REVIEW_RTL][] | Not Started | +Review | [REVIEW_DELETED_FF][] | Not Started | +Review | [REVIEW_SW_CHANGE][] | Not Started | +Review | [REVIEW_SW_ERRATA][] | Not Started | +Review | Reviewer(s) | Not Started | +Review | Signoff date | Not Started | + +[NEW_FEATURES_D3]: ../../../../../doc/project_governance/checklist/README.md#new_features_d3 +[TODO_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#todo_complete +[LINT_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#lint_complete +[CDC_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#cdc_complete +[RDC_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#rdc_complete +[REVIEW_RTL]: ../../../../../doc/project_governance/checklist/README.md#review_rtl +[REVIEW_DELETED_FF]: ../../../../../doc/project_governance/checklist/README.md#review_deleted_ff +[REVIEW_SW_CHANGE]: ../../../../../doc/project_governance/checklist/README.md#review_sw_change +[REVIEW_SW_ERRATA]: ../../../../../doc/project_governance/checklist/README.md#review_sw_errata + +## Verification Checklist + +### V1 + + Type | Item | Resolution | Note/Collaterals +--------------|---------------------------------------|-------------|------------------ +Documentation | [DV_DOC_DRAFT_COMPLETED][] | Done | [PWRMGR DV document](../dv/README.md) +Documentation | [TESTPLAN_COMPLETED][] | Done | [PWRMGR testplan](../dv/README.md#testplan) +Testbench | [TB_TOP_CREATED][] | Done | +Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Done | +Testbench | [SIM_TB_ENV_CREATED][] | Done | +Testbench | [SIM_RAL_MODEL_GEN_AUTOMATED][] | Done | +Testbench | [CSR_CHECK_GEN_AUTOMATED][] | Done | +Testbench | [TB_GEN_AUTOMATED][] | Done | +Tests | [SIM_SMOKE_TEST_PASSING][] | Done | +Tests | [SIM_CSR_MEM_TEST_SUITE_PASSING][] | Done | Block has no mem +Tests | [FPV_MAIN_ASSERTIONS_PROVEN][] | N/A | +Tool Setup | [SIM_ALT_TOOL_SETUP][] | Done | Xcelium +Regression | [SIM_SMOKE_REGRESSION_SETUP][] | Done | +Regression | [SIM_NIGHTLY_REGRESSION_SETUP][] | Done | +Regression | [FPV_REGRESSION_SETUP][] | N/A | +Coverage | [SIM_COVERAGE_MODEL_ADDED][] | Done | +Code Quality | [TB_LINT_SETUP][] | Done | +Integration | [PRE_VERIFIED_SUB_MODULES_V1][] | Done | +Review | [DESIGN_SPEC_REVIEWED][] | Done | +Review | [TESTPLAN_REVIEWED][] | Done | +Review | [STD_TEST_CATEGORIES_PLANNED][] | Done | Exceptions: debug, power, performance +Review | [V2_CHECKLIST_SCOPED][] | Done | + +[DV_DOC_DRAFT_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#dv_doc_draft_completed +[TESTPLAN_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#testplan_completed +[TB_TOP_CREATED]: ../../../../../doc/project_governance/checklist/README.md#tb_top_created +[PRELIMINARY_ASSERTION_CHECKS_ADDED]: ../../../../../doc/project_governance/checklist/README.md#preliminary_assertion_checks_added +[SIM_TB_ENV_CREATED]: ../../../../../doc/project_governance/checklist/README.md#sim_tb_env_created +[SIM_RAL_MODEL_GEN_AUTOMATED]: ../../../../../doc/project_governance/checklist/README.md#sim_ral_model_gen_automated +[CSR_CHECK_GEN_AUTOMATED]: ../../../../../doc/project_governance/checklist/README.md#csr_check_gen_automated +[TB_GEN_AUTOMATED]: ../../../../../doc/project_governance/checklist/README.md#tb_gen_automated +[SIM_SMOKE_TEST_PASSING]: ../../../../../doc/project_governance/checklist/README.md#sim_smoke_test_passing +[SIM_CSR_MEM_TEST_SUITE_PASSING]: ../../../../../doc/project_governance/checklist/README.md#sim_csr_mem_test_suite_passing +[FPV_MAIN_ASSERTIONS_PROVEN]: ../../../../../doc/project_governance/checklist/README.md#fpv_main_assertions_proven +[SIM_ALT_TOOL_SETUP]: ../../../../../doc/project_governance/checklist/README.md#sim_alt_tool_setup +[SIM_SMOKE_REGRESSION_SETUP]: ../../../../../doc/project_governance/checklist/README.md#sim_smoke_regression_setup +[SIM_NIGHTLY_REGRESSION_SETUP]: ../../../../../doc/project_governance/checklist/README.md#sim_nightly_regression_setup +[FPV_REGRESSION_SETUP]: ../../../../../doc/project_governance/checklist/README.md#fpv_regression_setup +[SIM_COVERAGE_MODEL_ADDED]: ../../../../../doc/project_governance/checklist/README.md#sim_coverage_model_added +[TB_LINT_SETUP]: ../../../../../doc/project_governance/checklist/README.md#tb_lint_setup +[PRE_VERIFIED_SUB_MODULES_V1]: ../../../../../doc/project_governance/checklist/README.md#pre_verified_sub_modules_v1 +[DESIGN_SPEC_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#design_spec_reviewed +[TESTPLAN_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#testplan_reviewed +[STD_TEST_CATEGORIES_PLANNED]: ../../../../../doc/project_governance/checklist/README.md#std_test_categories_planned +[V2_CHECKLIST_SCOPED]: ../../../../../doc/project_governance/checklist/README.md#v2_checklist_scoped + +### V2 + + Type | Item | Resolution | Note/Collaterals +--------------|-----------------------------------------|-------------|------------------ +Documentation | [DESIGN_DELTAS_CAPTURED_V2][] | Done | +Documentation | [DV_DOC_COMPLETED][] | Done | +Testbench | [FUNCTIONAL_COVERAGE_IMPLEMENTED][] | Done | +Testbench | [ALL_INTERFACES_EXERCISED][] | Done | +Testbench | [ALL_ASSERTION_CHECKS_ADDED][] | Done | +Testbench | [SIM_TB_ENV_COMPLETED][] | Done | +Tests | [SIM_ALL_TESTS_PASSING][] | Done | +Tests | [FPV_ALL_ASSERTIONS_WRITTEN][] | NA | +Tests | [FPV_ALL_ASSUMPTIONS_REVIEWED][] | NA | +Tests | [SIM_FW_SIMULATED][] | Done | +Regression | [SIM_NIGHTLY_REGRESSION_V2][] | Done | +Coverage | [SIM_CODE_COVERAGE_V2][] | Done | +Coverage | [SIM_FUNCTIONAL_COVERAGE_V2][] | Done | +Coverage | [FPV_CODE_COVERAGE_V2][] | NA | +Coverage | [FPV_COI_COVERAGE_V2][] | NA | +Integration | [PRE_VERIFIED_SUB_MODULES_V2][] | Done | +Issues | [NO_HIGH_PRIORITY_ISSUES_PENDING][] | Done | +Issues | [ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED][] | Done | +Review | [DV_DOC_TESTPLAN_REVIEWED][] | Done | +Review | [V3_CHECKLIST_SCOPED][] | Done | + +[DESIGN_DELTAS_CAPTURED_V2]: ../../../../../doc/project_governance/checklist/README.md#design_deltas_captured_v2 +[DV_DOC_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#dv_doc_completed +[FUNCTIONAL_COVERAGE_IMPLEMENTED]: ../../../../../doc/project_governance/checklist/README.md#functional_coverage_implemented +[ALL_INTERFACES_EXERCISED]: ../../../../../doc/project_governance/checklist/README.md#all_interfaces_exercised +[ALL_ASSERTION_CHECKS_ADDED]: ../../../../../doc/project_governance/checklist/README.md#all_assertion_checks_added +[SIM_TB_ENV_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#sim_tb_env_completed +[SIM_ALL_TESTS_PASSING]: ../../../../../doc/project_governance/checklist/README.md#sim_all_tests_passing +[FPV_ALL_ASSERTIONS_WRITTEN]: ../../../../../doc/project_governance/checklist/README.md#fpv_all_assertions_written +[FPV_ALL_ASSUMPTIONS_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#fpv_all_assumptions_reviewed +[SIM_FW_SIMULATED]: ../../../../../doc/project_governance/checklist/README.md#sim_fw_simulated +[SIM_NIGHTLY_REGRESSION_V2]: ../../../../../doc/project_governance/checklist/README.md#sim_nightly_regression_v2 +[SIM_CODE_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#sim_code_coverage_v2 +[SIM_FUNCTIONAL_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#sim_functional_coverage_v2 +[FPV_CODE_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#fpv_code_coverage_v2 +[FPV_COI_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#fpv_coi_coverage_v2 +[PRE_VERIFIED_SUB_MODULES_V2]: ../../../../../doc/project_governance/checklist/README.md#pre_verified_sub_modules_v2 +[NO_HIGH_PRIORITY_ISSUES_PENDING]: ../../../../../doc/project_governance/checklist/README.md#no_high_priority_issues_pending +[ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED]:../../../../../doc/project_governance/checklist/README.md#all_low_priority_issues_root_caused +[DV_DOC_TESTPLAN_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#dv_doc_testplan_reviewed +[V3_CHECKLIST_SCOPED]: ../../../../../doc/project_governance/checklist/README.md#v3_checklist_scoped + +### V2S + + Type | Item | Resolution | Note/Collaterals +--------------|-----------------------------------------|-------------|------------------ +Documentation | [SEC_CM_TESTPLAN_COMPLETED][] | Done | +Tests | [FPV_SEC_CM_VERIFIED][] | Done | +Tests | [SIM_SEC_CM_VERIFIED][] | Done | +Coverage | [SIM_COVERAGE_REVIEWED][] | Done | UNR will be added after intra structure issue is resolved. +Review | [SEC_CM_DV_REVIEWED][] | Done | + +[SEC_CM_TESTPLAN_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_testplan_completed +[FPV_SEC_CM_VERIFIED]: ../../../../../doc/project_governance/checklist/README.md#fpv_sec_cm_verified +[SIM_SEC_CM_VERIFIED]: ../../../../../doc/project_governance/checklist/README.md#sim_sec_cm_verified +[SIM_COVERAGE_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sim_coverage_reviewed +[SEC_CM_DV_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_dv_reviewed + +### V3 + + Type | Item | Resolution | Note/Collaterals +--------------|-----------------------------------|-------------|------------------ +Documentation | [DESIGN_DELTAS_CAPTURED_V3][] | Not Started | +Tests | [X_PROP_ANALYSIS_COMPLETED][] | Not Started | +Tests | [FPV_ASSERTIONS_PROVEN_AT_V3][] | Not Started | +Regression | [SIM_NIGHTLY_REGRESSION_AT_V3][] | Not Started | +Coverage | [SIM_CODE_COVERAGE_AT_100][] | Not Started | +Coverage | [SIM_FUNCTIONAL_COVERAGE_AT_100][]| Not Started | +Coverage | [FPV_CODE_COVERAGE_AT_100][] | Not Started | +Coverage | [FPV_COI_COVERAGE_AT_100][] | Not Started | +Code Quality | [ALL_TODOS_RESOLVED][] | Not Started | +Code Quality | [NO_TOOL_WARNINGS_THROWN][] | Not Started | +Code Quality | [TB_LINT_COMPLETE][] | Not Started | +Integration | [PRE_VERIFIED_SUB_MODULES_V3][] | Not Started | +Issues | [NO_ISSUES_PENDING][] | Not Started | +Review | Reviewer(s) | Not Started | +Review | Signoff date | Not Started | + +[DESIGN_DELTAS_CAPTURED_V3]: ../../../../../doc/project_governance/checklist/README.md#design_deltas_captured_v3 +[X_PROP_ANALYSIS_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#x_prop_analysis_completed +[FPV_ASSERTIONS_PROVEN_AT_V3]: ../../../../../doc/project_governance/checklist/README.md#fpv_assertions_proven_at_v3 +[SIM_NIGHTLY_REGRESSION_AT_V3]: ../../../../../doc/project_governance/checklist/README.md#sim_nightly_regression_at_v3 +[SIM_CODE_COVERAGE_AT_100]: ../../../../../doc/project_governance/checklist/README.md#sim_code_coverage_at_100 +[SIM_FUNCTIONAL_COVERAGE_AT_100]:../../../../../doc/project_governance/checklist/README.md#sim_functional_coverage_at_100 +[FPV_CODE_COVERAGE_AT_100]: ../../../../../doc/project_governance/checklist/README.md#fpv_code_coverage_at_100 +[FPV_COI_COVERAGE_AT_100]: ../../../../../doc/project_governance/checklist/README.md#fpv_coi_coverage_at_100 +[ALL_TODOS_RESOLVED]: ../../../../../doc/project_governance/checklist/README.md#all_todos_resolved +[NO_TOOL_WARNINGS_THROWN]: ../../../../../doc/project_governance/checklist/README.md#no_tool_warnings_thrown +[TB_LINT_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#tb_lint_complete +[PRE_VERIFIED_SUB_MODULES_V3]: ../../../../../doc/project_governance/checklist/README.md#pre_verified_sub_modules_v3 +[NO_ISSUES_PENDING]: ../../../../../doc/project_governance/checklist/README.md#no_issues_pending diff --git a/src/pwrmgr/doc/interfaces.md.tpl b/src/pwrmgr/doc/interfaces.md.tpl new file mode 100644 index 0000000..34a228c --- /dev/null +++ b/src/pwrmgr/doc/interfaces.md.tpl @@ -0,0 +1,67 @@ +# Hardware Interfaces + + +Referring to the [Comportable guideline for peripheral device functionality](https://opentitan.org/book/doc/contributing/hw/comportability), the module **`pwrmgr`** has the following hardware interfaces defined +- Primary Clock: **`clk_i`** +- Other Clocks: **`clk_slow_i`**, **`clk_lc_i`**, **`clk_esc_i`** +- Bus Device Interfaces (TL-UL): **`tl`** +- Bus Host Interfaces (TL-UL): *none* +- Peripheral Pins for Chip IO: *none* + +${"##"} [Inter-Module Signals](https://opentitan.org/book/doc/contributing/hw/comportability/index.html#inter-signal-handling) + +| Port Name | Package::Struct | Type | Act | Width | Description | +|:---------------|:--------------------------|:--------|:------|--------:|:--------------| +| pwr_ast | pwrmgr_pkg::pwr_ast | req_rsp | req | 1 | | +| pwr_rst | pwrmgr_pkg::pwr_rst | req_rsp | req | 1 | | +| pwr_clk | pwrmgr_pkg::pwr_clk | req_rsp | req | 1 | | +| pwr_otp | pwrmgr_pkg::pwr_otp | req_rsp | req | 1 | | +| pwr_lc | pwrmgr_pkg::pwr_lc | req_rsp | req | 1 | | +| pwr_flash | pwrmgr_pkg::pwr_flash | uni | rcv | 1 | | +| esc_rst_tx | prim_esc_pkg::esc_tx | uni | rcv | 1 | | +| esc_rst_rx | prim_esc_pkg::esc_rx | uni | req | 1 | | +| pwr_cpu | pwrmgr_pkg::pwr_cpu | uni | rcv | 1 | | +| wakeups | logic | uni | rcv | 6 | | +| rstreqs | logic | uni | rcv | 2 | | +| ndmreset_req | logic | uni | rcv | 1 | | +| strap | logic | uni | req | 1 | | +| low_power | logic | uni | req | 1 | | +| rom_ctrl | rom_ctrl_pkg::pwrmgr_data | uni | rcv | 1 | | +| fetch_en | lc_ctrl_pkg::lc_tx | uni | req | 1 | | +| lc_dft_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | +| lc_hw_debug_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | +| sw_rst_req | prim_mubi_pkg::mubi4 | uni | rcv | 1 | | +| tl | tlul_pkg::tl | req_rsp | rsp | 1 | | + +${"##"} Interrupts + +| Interrupt Name | Type | Description | +|:-----------------|:-------|:----------------------------------------------------------| +| wakeup | Event | Wake from low power state. See wake info for more details | + +${"##"} Security Alerts + +| Alert Name | Description | +|:-------------|:----------------------------------------------------------------------------------| +| fatal_fault | This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected. | + +${"##"} Security Countermeasures + +| Countermeasure ID | Description | +|:------------------------------|:-------------------------------------------------------------------------------------------------------------------------| +| PWRMGR.BUS.INTEGRITY | End-to-end bus integrity scheme. | +| PWRMGR.LC_CTRL.INTERSIG.MUBI | life cycle control / debug signals are multibit. | +| PWRMGR.ROM_CTRL.INTERSIG.MUBI | rom control done/good signals are multibit. | +| PWRMGR.RSTMGR.INTERSIG.MUBI | reset manager software request is multibit. | +| PWRMGR.ESC_RX.CLK.BKGN_CHK | Escalation receiver has a background timeout check | +| PWRMGR.ESC_RX.CLK.LOCAL_ESC | Escalation receiver clock timeout has a local reset escalation | +| PWRMGR.FSM.SPARSE | Sparse encoding for slow and fast state machines. | +| PWRMGR.FSM.TERMINAL | When FSMs reach a bad state, go into a terminate state that does not recover without user or external host intervention. | +| PWRMGR.CTRL_FLOW.GLOBAL_ESC | When global escalation is received, proceed directly to reset. | +| PWRMGR.MAIN_PD.RST.LOCAL_ESC | When main power domain reset glitches, proceed directly to reset. | +| PWRMGR.CTRL.CONFIG.REGWEN | Main control protected by regwen. | +| PWRMGR.WAKEUP.CONFIG.REGWEN | Wakeup configuration protected by regwen. | +| PWRMGR.RESET.CONFIG.REGWEN | Reset configuration protected by regwen. | + + + diff --git a/src/pwrmgr/doc/programmers_guide.md b/src/pwrmgr/doc/programmers_guide.md new file mode 100644 index 0000000..45bdf1d --- /dev/null +++ b/src/pwrmgr/doc/programmers_guide.md @@ -0,0 +1,63 @@ +# Programmer's Guide + +The process in which the power manager is used is highly dependent on the system's topology. +The following proposes one method for how this can be done. + +Assume first the system has the power states described [above](theory_of_operation.md#supported-low-power-modes). + +## Programmer Sequence for Entering Low Power + +1. Disable interrupts +2. Enable desired wakeup and reset sources in [`WAKEUP_EN`](registers.md#wakeup_en) and [`RESET_EN`](registers.md#reset_en). +3. Perform any system-specific low power entry steps, e.g. + - Interrupt checks (if something became pending prior to disable) +4. Configure low power mode in [`CONTROL`](registers.md#control). +5. Set low power hint in [`LOW_POWER_HINT`](registers.md#control--low_power_hint). +6. Set and poll [`CFG_CDC_SYNC`](registers.md#cfg_cdc_sync) to ensure above settings propagate across clock domains. +7. Execute wait-for-interrupt instruction on the processing host. + +### Possible Exits + +Once low power is initiated, the system may exit due to several reasons. +1. Graceful low power exit - This exit occurs when some source in the system gracefully wakes up the power manager. +2. System reset request - This exit occurs when either software or a peripheral requests the pwrmgr to reset the system. +3. [Fall through exit](theory_of_operation.md#fall-through-handling) - This exit occurs when an interrupt manages to break the wait-for-interrupt loop. +4. [Aborted entry](theory_of_operation.md#abort-handling) - This exit occurs when low power entry is attempted with an ongoing non-volatile transaction. + +In both fall through exit and aborted entry, the power manager does not actually enter low power. +Instead the low power entry is interrupted and the system restored to active state. + +## Programmer Sequence for Exiting Low Power + +There are two separate cases for low power exit. +One is exiting from deep sleep, and the other is exiting from normal sleep. + +### Exiting from Deep Sleep + +When exiting from deep sleep, the system begins execution in ROM. + +1. Complete normal preparation steps. +2. Check reset cause in [rstmgr](../../rstmgr/README.md) +3. Re-enable modules that have powered down. +4. Disable wakeup recording through [`WAKE_INFO_CAPTURE_DIS`](registers.md#wake_info_capture_dis). +5. Check which source woke up the system through [`WAKE_INFO`](registers.md#wake_info). +6. Take appropriate steps to handle the wake and resume normal operation. +7. Once wake is handled, clear the wake indication in [`WAKE_INFO`](registers.md#wake_info). + +### Exiting from Normal Sleep + +The handling for fall-through and abort are similar to normal sleep exit. +Since in these scenarios the system was not reset, software continues executing the instruction after the wait-for-interrupt invocation. + +1. Check exit condition to determine appropriate steps. +2. Clear low power hints and configuration in [`CONTROL`](registers.md#control). +3. Set and poll [`CFG_CDC_SYNC`](registers.md#cfg_cdc_sync) to ensure setting changes have propagated across clock boundaries. +4. Disable wakeup sources and stop recording. +5. Re-enable interrupts for normal operation and wakeup handling. +6. Once wake is handled, clear the wake indication in [`WAKE_INFO`](registers.md#wake_info). + +For an in-depth discussion, please see [power management programmers model](https://docs.google.com/document/d/1w86rmvylJgZVmmQ6Q1YBcCp2VFctkQT3zJ408SJMLPE/edit?usp=sharing) for additional details. + +## Device Interface Functions (DIFs) + +- [Device Interface Functions](../../../../../sw/device/lib/dif/dif_pwrmgr.h) diff --git a/src/pwrmgr/doc/pwrmgr_connectivity.svg b/src/pwrmgr/doc/pwrmgr_connectivity.svg new file mode 100644 index 0000000..b525330 --- /dev/null +++ b/src/pwrmgr/doc/pwrmgr_connectivity.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/src/pwrmgr/doc/pwrmgr_fsms.svg b/src/pwrmgr/doc/pwrmgr_fsms.svg new file mode 100644 index 0000000..962794c --- /dev/null +++ b/src/pwrmgr/doc/pwrmgr_fsms.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/src/pwrmgr/doc/registers.md.tpl b/src/pwrmgr/doc/registers.md.tpl new file mode 100644 index 0000000..3b252c7 --- /dev/null +++ b/src/pwrmgr/doc/registers.md.tpl @@ -0,0 +1,435 @@ +# Registers + + +${"##"} Summary + +| Name | Offset | Length | Description | +|:---------------------------------------------------------|:---------|---------:|:--------------------------------------------------------------------------------| +| pwrmgr.[`INTR_STATE`](#intr_state) | 0x0 | 4 | Interrupt State Register | +| pwrmgr.[`INTR_ENABLE`](#intr_enable) | 0x4 | 4 | Interrupt Enable Register | +| pwrmgr.[`INTR_TEST`](#intr_test) | 0x8 | 4 | Interrupt Test Register | +| pwrmgr.[`ALERT_TEST`](#alert_test) | 0xc | 4 | Alert Test Register | +| pwrmgr.[`CTRL_CFG_REGWEN`](#ctrl_cfg_regwen) | 0x10 | 4 | Controls the configurability of the !!CONTROL register. | +| pwrmgr.[`CONTROL`](#control) | 0x14 | 4 | Control register | +| pwrmgr.[`CFG_CDC_SYNC`](#cfg_cdc_sync) | 0x18 | 4 | The configuration registers CONTROL, WAKEUP_EN, RESET_EN are all written in the | +| pwrmgr.[`WAKEUP_EN_REGWEN`](#wakeup_en_regwen) | 0x1c | 4 | Configuration enable for wakeup_en register | +| pwrmgr.[`WAKEUP_EN`](#WAKEUP_EN) | 0x20 | 4 | Bit mask for enabled wakeups | +| pwrmgr.[`WAKE_STATUS`](#WAKE_STATUS) | 0x24 | 4 | A read only register of all current wake requests post enable mask | +| pwrmgr.[`RESET_EN_REGWEN`](#reset_en_regwen) | 0x28 | 4 | Configuration enable for reset_en register | +| pwrmgr.[`RESET_EN`](#RESET_EN) | 0x2c | 4 | Bit mask for enabled reset requests | +| pwrmgr.[`RESET_STATUS`](#RESET_STATUS) | 0x30 | 4 | A read only register of all current reset requests post enable mask | +| pwrmgr.[`ESCALATE_RESET_STATUS`](#escalate_reset_status) | 0x34 | 4 | A read only register of escalation reset request | +| pwrmgr.[`WAKE_INFO_CAPTURE_DIS`](#wake_info_capture_dis) | 0x38 | 4 | Indicates which functions caused the chip to wakeup | +| pwrmgr.[`WAKE_INFO`](#wake_info) | 0x3c | 4 | Indicates which functions caused the chip to wakeup. | +| pwrmgr.[`FAULT_STATUS`](#fault_status) | 0x40 | 4 | A read only register that shows the existing faults | + +${"##"} INTR_STATE +Interrupt State Register +- Offset: `0x0` +- Reset default: `0x0` +- Reset mask: `0x1` + +${"###"} Fields + +```wavejson +{"reg": [{"name": "wakeup", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:----------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | rw1c | 0x0 | wakeup | Wake from low power state. See wake info for more details | + +${"##"} INTR_ENABLE +Interrupt Enable Register +- Offset: `0x4` +- Reset default: `0x0` +- Reset mask: `0x1` + +${"###"} Fields + +```wavejson +{"reg": [{"name": "wakeup", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | rw | 0x0 | wakeup | Enable interrupt when [`INTR_STATE.wakeup`](#intr_state) is set. | + +${"##"} INTR_TEST +Interrupt Test Register +- Offset: `0x8` +- Reset default: `0x0` +- Reset mask: `0x1` + +${"###"} Fields + +```wavejson +{"reg": [{"name": "wakeup", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:----------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | wo | 0x0 | wakeup | Write 1 to force [`INTR_STATE.wakeup`](#intr_state) to 1. | + +${"##"} ALERT_TEST +Alert Test Register +- Offset: `0xc` +- Reset default: `0x0` +- Reset mask: `0x1` + +${"###"} Fields + +```wavejson +{"reg": [{"name": "fatal_fault", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:------------|:-------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | wo | 0x0 | fatal_fault | Write 1 to trigger one alert event of this kind. | + +${"##"} CTRL_CFG_REGWEN +Controls the configurability of the [`CONTROL`](#control) register. + +This register ensures the contents do not change once a low power hint and +WFI has occurred. + +It unlocks whenever a low power transition has completed (transition back to the +ACTIVE state) for any reason. +- Offset: `0x10` +- Reset default: `0x1` +- Reset mask: `0x1` + +${"###"} Fields + +```wavejson +{"reg": [{"name": "EN", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | ro | 0x1 | EN | Configuration enable. This bit defaults to 1 and is set to 0 by hardware when low power entry is initiated. When the device transitions back from low power state to active state, this bit is set back to 1 to allow software configuration of [`CONTROL`](#control) | + +${"##"} CONTROL +Control register +- Offset: `0x14` +- Reset default: `0x180` +- Reset mask: `0x1f1` +- Register enable: [`CTRL_CFG_REGWEN`](#ctrl_cfg_regwen) + +${"###"} Fields + +```wavejson +{"reg": [{"name": "LOW_POWER_HINT", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 3}, {"name": "CORE_CLK_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "IO_CLK_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "USB_CLK_EN_LP", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "USB_CLK_EN_ACTIVE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "MAIN_PD_N", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 23}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}} +``` + +| Bits | Type | Reset | Name | +|:------:|:------:|:-------:|:-------------------------------------------------| +| 31:9 | | | Reserved | +| 8 | rw | 0x1 | [MAIN_PD_N](#control--main_pd_n) | +| 7 | rw | 0x1 | [USB_CLK_EN_ACTIVE](#control--usb_clk_en_active) | +| 6 | rw | 0x0 | [USB_CLK_EN_LP](#control--usb_clk_en_lp) | +| 5 | rw | 0x0 | [IO_CLK_EN](#control--io_clk_en) | +| 4 | rw | 0x0 | [CORE_CLK_EN](#control--core_clk_en) | +| 3:1 | | | Reserved | +| 0 | rw | 0x0 | [LOW_POWER_HINT](#control--low_power_hint) | + +${"###"} CONTROL . MAIN_PD_N +Active low, main power domain power down + +| Value | Name | Description | +|:--------|:-----------|:----------------------------------------------------------| +| 0x0 | Power down | Main power domain is powered down during low power state. | +| 0x1 | Power up | Main power domain is kept powered during low power state | + + +${"###"} CONTROL . USB_CLK_EN_ACTIVE +USB clock enable during active power state + +| Value | Name | Description | +|:--------|:---------|:---------------------------------------------| +| 0x0 | Disabled | USB clock disabled during active power state | +| 0x1 | Enabled | USB clock enabled during active power state | + + +${"###"} CONTROL . USB_CLK_EN_LP +USB clock enable during low power state + +| Value | Name | Description | +|:--------|:---------|:------------------------------------------------------------------------------------------------------------------------------| +| 0x0 | Disabled | USB clock disabled during low power state | +| 0x1 | Enabled | USB clock enabled during low power state. However, if !!CONTROL.MAIN_PD_N is 0, USB clock is disabled during low power state. | + + +${"###"} CONTROL . IO_CLK_EN +IO clock enable during low power state + +| Value | Name | Description | +|:--------|:---------|:-----------------------------------------| +| 0x0 | Disabled | IO clock disabled during low power state | +| 0x1 | Enabled | IO clock enabled during low power state | + + +${"###"} CONTROL . CORE_CLK_EN +core clock enable during low power state + +| Value | Name | Description | +|:--------|:---------|:-------------------------------------------| +| 0x0 | Disabled | Core clock disabled during low power state | +| 0x1 | Enabled | Core clock enabled during low power state | + + +${"###"} CONTROL . LOW_POWER_HINT +The low power hint to power manager. +The hint is an indication for how the manager should treat the next WFI. +Once the power manager begins a low power transition, or if a valid reset request is registered, +this bit is automatically cleared by HW. + +| Value | Name | Description | +|:--------|:----------|:----------------------------------------| +| 0x0 | None | No low power intent | +| 0x1 | Low Power | Next WFI should trigger low power entry | + + +${"##"} CFG_CDC_SYNC +The configuration registers CONTROL, WAKEUP_EN, RESET_EN are all written in the +fast clock domain but used in the slow clock domain. + +The configuration are not propagated across the clock boundary until this +register is triggered and read. See fields below for more details +- Offset: `0x18` +- Reset default: `0x0` +- Reset mask: `0x1` + +${"###"} Fields + +```wavejson +{"reg": [{"name": "SYNC", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | +|:------:|:------:|:-------:|:----------------------------| +| 31:1 | | | Reserved | +| 0 | rw | 0x0 | [SYNC](#cfg_cdc_sync--sync) | + +${"###"} CFG_CDC_SYNC . SYNC +Configuration sync. When this bit is written to 1, a sync pulse is generated. When +the sync completes, this bit then self clears. + +Software should write this bit to 1, wait for it to clear, before assuming the slow clock +domain has accepted the programmed values. + +${"##"} WAKEUP_EN_REGWEN +Configuration enable for wakeup_en register +- Offset: `0x1c` +- Reset default: `0x1` +- Reset mask: `0x1` + +${"###"} Fields + +```wavejson +{"reg": [{"name": "EN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | rw0c | 0x1 | EN | When 1, WAKEUP_EN register can be configured. When 0, WAKEUP_EN register cannot be configured. | + +${"##"} WAKEUP_EN +Bit mask for enabled wakeups +- Offset: `0x20` +- Reset default: `0x0` +- Reset mask: `0x3f` +- Register enable: [`WAKEUP_EN_REGWEN`](#wakeup_en_regwen) + +${"###"} Fields + +```wavejson +{"reg": [{"name": "EN_0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN_1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN_2", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN_3", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN_4", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN_5", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 26}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------------------------------------------------------------------------------------------------------| +| 31:6 | | | | Reserved | +| 5 | rw | 0x0 | EN_5 | Whenever a particular bit is set to 1, that wakeup is also enabled. Whenever a particular bit is set to 0, that wakeup cannot wake the device from low power. | +| 4 | rw | 0x0 | EN_4 | Whenever a particular bit is set to 1, that wakeup is also enabled. Whenever a particular bit is set to 0, that wakeup cannot wake the device from low power. | +| 3 | rw | 0x0 | EN_3 | Whenever a particular bit is set to 1, that wakeup is also enabled. Whenever a particular bit is set to 0, that wakeup cannot wake the device from low power. | +| 2 | rw | 0x0 | EN_2 | Whenever a particular bit is set to 1, that wakeup is also enabled. Whenever a particular bit is set to 0, that wakeup cannot wake the device from low power. | +| 1 | rw | 0x0 | EN_1 | Whenever a particular bit is set to 1, that wakeup is also enabled. Whenever a particular bit is set to 0, that wakeup cannot wake the device from low power. | +| 0 | rw | 0x0 | EN_0 | Whenever a particular bit is set to 1, that wakeup is also enabled. Whenever a particular bit is set to 0, that wakeup cannot wake the device from low power. | + +${"##"} WAKE_STATUS +A read only register of all current wake requests post enable mask +- Offset: `0x24` +- Reset default: `0x0` +- Reset mask: `0x3f` + +${"###"} Fields + +```wavejson +{"reg": [{"name": "VAL_0", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "VAL_1", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "VAL_2", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "VAL_3", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "VAL_4", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "VAL_5", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 26}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:-------------------------------| +| 31:6 | | | | Reserved | +| 5 | ro | 0x0 | VAL_5 | Current value of wake requests | +| 4 | ro | 0x0 | VAL_4 | Current value of wake requests | +| 3 | ro | 0x0 | VAL_3 | Current value of wake requests | +| 2 | ro | 0x0 | VAL_2 | Current value of wake requests | +| 1 | ro | 0x0 | VAL_1 | Current value of wake requests | +| 0 | ro | 0x0 | VAL_0 | Current value of wake requests | + +${"##"} RESET_EN_REGWEN +Configuration enable for reset_en register +- Offset: `0x28` +- Reset default: `0x1` +- Reset mask: `0x1` + +${"###"} Fields + +```wavejson +{"reg": [{"name": "EN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:---------------------------------------------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | rw0c | 0x1 | EN | When 1, RESET_EN register can be configured. When 0, RESET_EN register cannot be configured. | + +${"##"} RESET_EN +Bit mask for enabled reset requests +- Offset: `0x2c` +- Reset default: `0x0` +- Reset mask: `0x3` +- Register enable: [`RESET_EN_REGWEN`](#reset_en_regwen) + +${"###"} Fields + +```wavejson +{"reg": [{"name": "EN_0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN_1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:---------------------------------------------------------------------------------------------------------------------------------------------------------| +| 31:2 | | | | Reserved | +| 1 | rw | 0x0 | EN_1 | Whenever a particular bit is set to 1, that reset request is enabled. Whenever a particular bit is set to 0, that reset request cannot reset the device. | +| 0 | rw | 0x0 | EN_0 | Whenever a particular bit is set to 1, that reset request is enabled. Whenever a particular bit is set to 0, that reset request cannot reset the device. | + +${"##"} RESET_STATUS +A read only register of all current reset requests post enable mask +- Offset: `0x30` +- Reset default: `0x0` +- Reset mask: `0x3` + +${"###"} Fields + +```wavejson +{"reg": [{"name": "VAL_0", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "VAL_1", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:-------------------------------| +| 31:2 | | | | Reserved | +| 1 | ro | 0x0 | VAL_1 | Current value of reset request | +| 0 | ro | 0x0 | VAL_0 | Current value of reset request | + +${"##"} ESCALATE_RESET_STATUS +A read only register of escalation reset request +- Offset: `0x34` +- Reset default: `0x0` +- Reset mask: `0x1` + +${"###"} Fields + +```wavejson +{"reg": [{"name": "VAL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:---------------------------------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | ro | 0x0 | VAL | When 1, an escalation reset has been seen. When 0, there is no escalation reset. | + +${"##"} WAKE_INFO_CAPTURE_DIS +Indicates which functions caused the chip to wakeup +- Offset: `0x38` +- Reset default: `0x0` +- Reset mask: `0x1` + +${"###"} Fields + +```wavejson +{"reg": [{"name": "VAL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:----------------------------------------------------------------------------------------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | rw | 0x0 | VAL | When written to 1, this actively suppresses the wakeup info capture. When written to 0, wakeup info capture timing is controlled by HW. | + +${"##"} WAKE_INFO +Indicates which functions caused the chip to wakeup. +The wake info recording begins whenever the device begins a valid low power entry. + +This capture is continued until it is explicitly disabled through WAKE_INFO_CAPTURE_DIS. +This means it is possible to capture multiple wakeup reasons. +- Offset: `0x3c` +- Reset default: `0x0` +- Reset mask: `0xff` + +${"###"} Fields + +```wavejson +{"reg": [{"name": "REASONS", "bits": 6, "attr": ["rw1c"], "rotate": 0}, {"name": "FALL_THROUGH", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "ABORT", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 140}} +``` + +| Bits | Type | Reset | Name | +|:------:|:------:|:-------:|:-----------------------------------------| +| 31:8 | | | Reserved | +| 7 | rw1c | 0x0 | [ABORT](#wake_info--abort) | +| 6 | rw1c | 0x0 | [FALL_THROUGH](#wake_info--fall_through) | +| 5:0 | rw1c | 0x0 | [REASONS](#wake_info--reasons) | + +${"###"} WAKE_INFO . ABORT +The abort wakeup reason indicates that despite setting a WFI and providing a low power +hint, an active flash / lifecycle / otp transaction was ongoing when the power controller +attempted to initiate low power entry. + +The power manager detects this condition, halts low power entry and reports as a wakeup reason + +${"###"} WAKE_INFO . FALL_THROUGH +The fall through wakeup reason indicates that despite setting a WFI and providing a low power +hint, an interrupt arrived at just the right time to break the executing core out of WFI. + +The power manager detects this condition, halts low power entry and reports as a wakeup reason + +${"###"} WAKE_INFO . REASONS +Various peripheral wake reasons + +${"##"} FAULT_STATUS +A read only register that shows the existing faults +- Offset: `0x40` +- Reset default: `0x0` +- Reset mask: `0x7` + +${"###"} Fields + +```wavejson +{"reg": [{"name": "REG_INTG_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "ESC_TIMEOUT", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "MAIN_PD_GLITCH", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 160}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:---------------|:----------------------------------------------------------| +| 31:3 | | | | Reserved | +| 2 | ro | 0x0 | MAIN_PD_GLITCH | When 1, unexpected power glitch was observed on main PD. | +| 1 | ro | 0x0 | ESC_TIMEOUT | When 1, an escalation clock / reset timeout has occurred. | +| 0 | ro | 0x0 | REG_INTG_ERR | When 1, an integrity error has occurred. | + + + diff --git a/src/pwrmgr/doc/theory_of_operation.md b/src/pwrmgr/doc/theory_of_operation.md new file mode 100644 index 0000000..5f197a8 --- /dev/null +++ b/src/pwrmgr/doc/theory_of_operation.md @@ -0,0 +1,304 @@ +# Theory of Operation + +The power manager performs the following functions: +- Turn on/off power domain(s). +- Control root resets with the reset manager. +- Control root clock enables with AST and clock manager. +- Sequence various power up activities such as OTP sensing, life cycle initiation and releasing software to execute. + + +## Block Diagram + +See the below high level block diagram that illustrates the connections between the power manager and various system components. +Blocks outlined with a solid magenta line are always on; while blocks outlined with a dashed magenta line are a mix of components that are and those that are not. + +![Power Manager Connectivity Diagram](../doc/pwrmgr_connectivity.svg) + +## Overall Sequencing + +The power manager contains two state machines. +One operates on the always-on slow clock (this clock is always running and usually measured in KHz) and is responsible for turning faster clocks on and off and managing the power domains. +The other operates on a normal fixed clock (usually measured in MHz) and is responsible for everything else in the power sequence. + +The following diagram breaks down the general functionality of both. +The state machines are colored based on their clock domains. +The green state machine is clocked by the normal fixed domain, while the orange state machine is clocked by the slow domain. +Specific request / acknowledge signals are also highlighted in this color scheme to show where the two state machines communicate. + +![Power Manager FSMs](../doc/pwrmgr_fsms.svg) + + +Note, most of the states are transitional states, and only the following state combinations are resting states. + + +* Slow FSM `Idle` and fast FSM `Active` +* Slow FSM `Low Power` and fast FSM `Low Power` + +The slow FSM `Low Power` and fast FSM `Active` states specifically are concepts useful when examining [reset handling](#reset-request-handling). + + +## Slow Clock Domain FSM + +The slow clock domain FSM (referred to as the slow FSM from here on) resets to the Reset state. +This state is released by `por_rst_n`, which is supplied from the reset controller. +The `por_rst_n` signal is released when the reset controller detects the root power domains (`vcaon_pok` from AST) of the system are ready. +Please see the [ast](../../../ip/ast/README.md) for more details. + +The slow FSM requests the AST to power up the main domain and high speed clocks. +Once those steps are done, it requests the [fast FSM](#fast-clock-domain-fsm) to begin operation. +The slow FSM also handles power isolation controls as part of this process. + +Once the fast FSM acknowledges the power-up completion, the slow FSM transitions to `Idle` and waits for a power down request. +When a power down request is received, the slow FSM turns off AST clocks and power as directed by software configuration. +This means the clocks and power are not always turned off, but are rather controlled by software configurations in [`CONTROL`](registers.md#control) prior to low power entry . +Once these steps are complete, the slow FSM transitions to a low power state and awaits a wake request, which can come either as an actual wakeup, or a reset event (for example always on watchdog expiration). + +#### Sparse FSM + +Since the slow FSM is sparsely encoded, it is possible for the FSM to end up in an undefined state if attacked. +When this occurs, the slow FSM sends an `invalid` indication to the fast FSM and forcibly powers off and clamps everything. + +The clocks are kept on however to allow the fast FSM to operate if it is able to receive the `invalid` indication. +The slow FSM does not recover from this state until the system is reset by POR. + +Unlike [escalation resets](#escalation-reset-request), the system does not self reset. +Instead the system goes into a terminal non-responsive state where a user or host must directly intervene by toggling the power or asserting an external reset input. + +## Fast Clock Domain FSM + +The fast clock domain FSM (referred to as fast FSM from here on) resets to `Low Power` state and waits for a power-up request from the slow FSM. + +Once received, the fast FSM releases the life cycle reset stage (see [reset controller](../../rstmgr/README.md) for more details). +This allows the [OTP](../../../../ip/otp_ctrl/README.md) to begin sensing. +Once OTP sensing completes, the life cycle controller is initialized. +The initialization of the life cycle controller puts the device into its allowed operating state (see [life cycle controller](../../../../ip/lc_ctrl/README.md) for more details). + +Once life cycle initialization is done, the fast FSM enables all second level clock gating (see [clock controller](../../clkmgr/README.md) for more details) and initiates strap sampling. +For more details on what exactly the strap samples, please see [here](https://docs.google.com/spreadsheets/d/1pH8T1MhQ7TXtP_bFNT85T9jSVIHlxHAfbMnPbsMdjc0/edit?usp=sharing). + +Once strap sampling is complete, the system is ready to begin normal operations (note `flash_ctrl` initialization is explicitly not done here, please see [sections below](#flash-handling) for more details). +The fast FSM acknowledges the slow FSM (which made the original power up request) and releases the system reset stage - this enables the processor to begin operation. +Afterwards, the fast FSM transitions to `Active` state and waits for a software low power entry request. + +A low power request is initiated by software through a combination of WFI and software low power hint in [`CONTROL`](registers.md#control). +Specifically, this means if software issues only WFI, the power manager does not treat it as a power down request. +The notion of WFI is exported from the processor. +For Ibex, this is currently in the form of `core_sleeping_o`. + +In response to the low power entry request, the fast FSM disables all second level clock gating. +Before proceeding, the fast FSM explicitly separates the handling between a normal low power entry and a [reset request](#reset-request-handling). + +For low power entry, there are two cases, [fall through handling](#fall-through-handling) and [abort handling](#abort-handling). +If none of these exception cases are matched for low power entry, the fast FSM then asserts appropriate resets as necessary and requests the slow FSM to take over. + +For reset requests, fall through and aborts are not checked and the system simply resets directly. +Note in this scenario the slow FSM is not requested to take over. + +#### Sparse FSM + +Since the fast FSM is sparsely encoded, it is possible for the FSM to end up in an undefined state if attacked. +When this occurs, the fast FSM forcibly disables all clocks and holds the system in reset. + +The fast FSM does not recover from this state until the system is reset by POR. + + +### ROM Integrity Checks + +The power manager coordinates the [start up ROM check](../../../../ip/rom_ctrl/README.md#the-startup-rom-check) with `rom_ctrl`. + +After every reset, the power manager sends an indication to the `rom_ctrl` to begin performing integrity checks. +When the `rom_ctrl` checks are finished, a `done` and `good` indication are sent back to the power manager. + +If the device is in life cycle test states (`TEST_UNLOCKED` or `RMA`), the `good` signal is ignored and the ROM contents are always allowed to execute. + +If the device is not in one of the test states, the `good` signal is used to determine ROM execution. +If `good` is true, ROM execution is allowed. +If `good` is false, ROM execution is disallowed. + +### Fall Through Handling + +A low power entry fall through occurs when some condition occurs that immediately de-assert the entry conditions right after the software requests it. + +This can happen if right after software asserts WFI, an interrupt is shown to the processor, thus breaking it out of its currently stopped state. +Whether this type of fall through happens is highly dependent on how the system handles interrupts during low power entry - some systems may choose to completely silence any interrupt not related to wakeup, others may choose to leave them all enabled. +The fall through handle is specifically catered to the latter category. + +For a normal low power entry, the fast FSM first checks that the low power entry conditions are still true. +If the entry conditions are no longer true, the fast FSM "falls through" the entry handling and returns the system to active state, thus terminating the entry process. + +### Abort Handling + +If the entry conditions are still true, the fast FSM then checks there are no ongoing non-volatile activities from `otp_ctrl`, `lc_ctrl` and `flash_ctrl`. +If any module is active, the fast FSM "aborts" entry handling and returns the system to active state, thus terminating the entry process. + +## Reset Request Handling + +There are 4 reset requests in the system +- peripheral requested reset such as watchdog. +- reset manager's software requested reset, which is functionally very similar to a peripheral requested reset. +- power manager's internal reset request. +- Non-debug module reset. + +Flash brownout is handled separately and described in [flash handling section](#flash-handling) below. + +Note that the non-debug module reset is handled similarly to a peripheral requested reset, except that the non-debug module reset won't affect the debug module state and associated TAP muxing logic inside the pinmux. + +The power controller only observes reset requests in two states - the slow FSM `Low Power` state and the fast FSM `Active` state. +When a reset request is received during slow FSM `Low Power` state, the system begins its usual power up sequence even if a wakeup has not been received. + +When a reset request is received during fast FSM `Active` state, the fast FSM asserts resets and transitions back to its `Low Power` state. +The normal power-up process described [above](#fast-clock-domain-fsm) is then followed to release the resets. +Note in this case, the slow FSM is "not activated" and remains in its `Idle` state. + +### Power Manager Internal Reset Requests + +In additional to external requests, the power manager maintains 2 internal reset requests: +* Escalation reset request +* Main power domain unstable reset request + +#### Escalation Reset Request + +Alert escalation resets in general behave similarly to peripheral requested resets. +However, peripheral resets are always handled gracefully and follow the normal FSM transition. + +Alert escalations can happen at any time and do not always obey normal rules. +As a result, upon alert escalation, the power manager makes a best case effort to transition directly into reset handling. + +This may not always be possible if the escalation happens while the FSM is in an invalid state. +In this scenario, the pwrmgr keeps everything powered off and silenced and requests escalation handling if the system ever wakes up. + +#### Escalation Clock Timeout + +Under normal behavior, the power manager can receive escalation requests from the system and handle them [appropriately](#escalation-reset-request). +However, if the escalation clock or reset are non-functional for any reason, the escalation request would not be serviced. + +To mitigate this, the power manager actively checks for escalation interface clock/reset timeout. +This is done by a continuous request / acknowledge interface between the power manager's local clock/reset and the escalate network's clock/reset. + +If the request / acknowledge interface does not respond within 128 power manager clock cycles, the escalate domain is assumed to be off. +When this happens, the power manager creates a local escalation request that behaves identically to the global escalation request. + + +#### Main Power Unstable Reset Requests +If the main power ever becomes unstable (the power okay indication is low even though it is powered on), the power manager requests an internal reset. +This reset behaves similarly to the escalation reset and transitions directly into reset handling. + +Note that under normal low power conditions, the main power may be turned off. +As a result of this, the main power unstable checks are valid only during states that power should be on and stable. +This includes any state where power manager has requested the power to be turned on. + + +### Reset Requests Received During Other States + +All other states in the slow / fast FSM are considered transitional states. +Resets are not observed in other states because the system will always be transitioning towards one of the steady states (the system is in the process of powering down or powering up). +Once a steady state is reached, reset requests are then observed and processed. + +### Reset Recording + +There are two ways in which the device is reset: +- The reset requests mentioned in [reset handling](#reset-request-handling) +- Low power entry (`sleep_req` in the state diagram) + +The power manager handles only one of these at a time (see state diagrams). +This means if reset request and low power entry collide, the power manager will handle them on a first come first served basis. +When the handling of the first is completed, the power manager handles the second pending request if it is still present. + +This is done because low power resets and peripheral requested resets lead to different behaviors. +When the power manager commits to handling a specific request, it informs the reset manager why it has reset the processor. + +For example, assume a low power entry request arrives slightly ahead of reset requests. +The power manager will: +- Transition the system into low power state. +- Inform the reset manager to record "low power exit" as the reset reason. +- Once in low state, transition the system to `Active` state by using the reset request as a wakeup indicator. +- Inform the reset manager to also record the peripheral that requested reset. +- Once in `Active` state, reset the system and begin normal power-up routines again. + +If reset requests arrive slightly ahead of a low power entry request, then power manager will: +- Reset the system and begin normal power-up routines. +- Inform the reset manager to record the peripheral that requested reset. +- Once in `Active` state, if the low power entry request is still present, transition to low power state. + - Inform the reset manager to also record "low power exit" as the reset reason. +- If the low power entry request was wiped out by reset, the system then stays in `Active` state and awaits software instructions. + +Ultimately when control is returned to software, it may see two reset reasons and must handle them accordingly. + + +## Wakeup Recording + +Similar to [reset handling](#reset-request-handling), wakeup signals are only observed during slow FSM `Low Power`; however their recording is continuous until explicitly disabled by software. + +Wakeup recording begins when the fast FSM transitions out of `Active` state and continues until explicitly disabled by software. +This ensures wakeup events are not missed until software has set up the appropriate peripherals. +Recording needs clocks to be active, and during low power they are usually not. +For this reason, it is important for wakeups to be level and remain active until software clears them. + +The software is also able to enable recording during `Active` state if it chooses to do so. The recording enables are OR’d together for hardware purposes. + + +## Flash Handling +For the section below, flash macro refers to the proprietary flash storage supplied by a vendor. +`flash_ctrl`, on the other hand, refers to the open source controller that manages access to the flash macro. + +### Power-Up Handling + +The [AST](../../../ip/ast/README.md) automatically takes the flash macro out of power down state as part of the power manager's power up request. + +Once flash macro is powered up and ready, an indication is sent to the `flash_ctrl`. + +Once the boot ROM is allowed to execute, it is expected to further initialize the `flash_ctrl` and flash macro prior to using it. +This involves the following steps: + +* Poll `flash_ctrl` register to ensure flash macro has powered up and completed internal initialization. +* Initialize `flash_ctrl` seed reading and scrambling. + +### Power-Down Handling + +Before the device enters low power, the pwrmgr first checks to ensure there are no ongoing transactions to the flash macro. +When the device enters deep sleep, the flash macro is automatically put into power down mode by the AST. +The AST places the flash macro into power down through direct signaling between AST and flash macro, the pwrmgr is not directly involved. + +When the device exits low power state, it is the responsibility of the boot ROM to poll for flash macro and `flash_ctrl` power-up complete similar to the above section. + +### Flash Brownout Handling + +When the external supply of the device dips below a certain threshold during a non-volatile flash macro operation (program or erase), the flash macro requires the operation to terminate in a pre-defined manner. +This sequence will be exclusively handled by the AST. + +The power manager is unaware of the difference between POR and flash brownout. +Because of this, the software also cannot distinguish between these two reset causes. + + +## Supported Low Power Modes + +This section details the various low power modes supported by OpenTitan. + + +### Deep Sleep or Standby + +This is the lowest power mode of the device (outside of full power down or device held in reset). +During this state: + +* All clocks other than the always-on slow clock are turned off at the source. +* All non-always-on digital domains are powered off. +* I/O power domains may or may not be off. + * The state of the IO power domain has no impact on the digital core’s power budget, e.g. the IO power being off does not cause the accompanying digital logic in pads or elsewhere to leak more. + + +### Normal Sleep + +This is a fast low power mode of the device that trades-off power consumption for resume latency. +During this state: + +* All clocks other than the KHz slow clock are turned off at the source. +* All power domains are kept on for fast resume. +* Sensor countermeasures can be opportunistically on. +* I/O power domains may or may not be off. + * The state of the IO power domain has no impact on the digital core’s power budget, e.g. the IO power being off does not cause the accompanying digital logic in pads or elsewhere to leak more. + +## Debug + +When performing TAP debug, it is important for the debugging software to prevent the system from going to low power. +If the system enters low power during live debug, the debug session will be broken. +There is currently no standardized way to do this, so it is up to the debugging agent to perform the correct steps. diff --git a/src/pwrmgr/dv/README.md.tpl b/src/pwrmgr/dv/README.md.tpl new file mode 100644 index 0000000..3c5c2b6 --- /dev/null +++ b/src/pwrmgr/dv/README.md.tpl @@ -0,0 +1,255 @@ +# PWRMGR DV document +<% top_name = f"top_{topname}" %> +${"##"} Goals +* **DV** + * Verify all PWRMGR IP features by running dynamic simulations with a SV/UVM based testbench. + * Develop and run all tests based on the [testplan](#testplan) below towards closing code and functional coverage on the IP and all of its sub-modules. +* **FPV** + * Verify TileLink device protocol compliance with an SVA based testbench. + +${"##"} Current status +* [Design & verification stage](../doc/checklist.md) + * [HW development stages](../../../../../doc/project_governance/development_stages.md) +* [Simulation results](https://reports.opentitan.org/hw/${top_name}/ip_autogen/pwrmgr/dv/latest/report.html) + +${"##"} Design features +For detailed information on PWRMGR design features, please see the [PWRMGR HWIP technical specification](../README.md). + +${"##"} Testbench architecture +PWRMGR testbench has been constructed based on the [CIP testbench architecture](../../../../dv/sv/cip_lib/README.md). + +${"###"} Block diagram +![Block diagram](./doc/tb.svg) + +${"###"} Top level testbench +Top level testbench is located at [`hw/${top_name}/ip_autogen/pwrmgr/dv/tb.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/${top_name}/ip_autogen/pwrmgr/dv/tb.sv). +It instantiates the PWRMGR DUT module [`hw/${top_name}/ip_autogen/pwrmgr/rtl/pwrmgr.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/${top_name}/ip_autogen/pwrmgr/rtl/pwrmgr.sv). +In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into `uvm_config_db`: +* [Clock and reset interface](../../../../dv/sv/common_ifs/README.md) +* [TileLink host interface](../../../../dv/sv/tl_agent/README.md) +* PWRMGR interface [`hw/${top_name}/ip_autogen/pwrmgr/dv/env/pwrmgr_if.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/${top_name}/ip_autogen/pwrmgr/dv/env/pwrmgr_if.sv). +* Interrupts ([`pins_if`](../../../../dv/sv/common_ifs/README.md)) +* Alerts ([`alert_esc_if`](../../../../dv/sv/alert_esc_agent/README.md)) + +${"###"} Common DV utility components +The following utilities provide generic helper tasks and functions to perform activities that are common across the project: +* [dv_utils_pkg](../../../../dv/sv/dv_utils/README.md) +* [csr_utils_pkg](../../../../dv/sv/csr_utils/README.md) + +${"###"} Global types & methods +All common types and methods defined at the package level can be found in +[`pwrmgr_env_pkg`](https://github.com/lowRISC/opentitan/blob/master/hw/${top_name}/ip_autogen/pwrmgr/dv/env/pwrmgr_env_pkg.sv). +Some of them in use are: +```systemverilog + typedef enum int { + WakeupSysrst, + WakeupDbgCable, + WakeupPin, + WakeupUsb, + WakeupAonTimer, + WakeupSensorCtrl + } wakeup_e; + + typedef struct packed { + logic main_pd_n; + logic usb_clk_en_active; + logic usb_clk_en_lp; + logic io_clk_en; + logic core_clk_en; + } control_enables_t; + + typedef bit [pwrmgr_reg_pkg::NumWkups-1:0] wakeups_t; + typedef bit [pwrmgr_reg_pkg::NumRstReqs-1:0] resets_t; + + // This is used to send all resets to rstmgr. + typedef bit [pwrmgr_pkg::HwResetWidth-1:0] resets_out_t; +``` +${"###"} TL_agent +PWRMGR testbench instantiates (already handled in CIP base env) [tl_agent](../../../../dv/sv/tl_agent/README.md) which provides the ability to drive and independently monitor random traffic via TL host interface into PWRMGR device. + +${"###"} UVM RAL Model +The PWRMGR RAL model is created with the [`ralgen`](../../../../dv/tools/ralgen/README.md) FuseSoC generator script automatically when the simulation is at the build stage. + +It can be created manually by invoking [`regtool`](../../../../../util/reggen/doc/setup_and_use.md). + +${"###"} Stimulus strategy +The sequences are closely related to the testplan's testpoints. +Testpoints and coverage are described in more detail in the [testplan](#testplan). +All test sequences reside in [`hw/${top_name}/ip_autogen/pwrmgr/dv/env/seq_lib`](https://github.com/lowRISC/opentitan/blob/master/hw/${top_name}/ip_autogen/pwrmgr/dv/env/seq_lib), and extend `pwrmgr_base_vseq`. +The `pwrmgr_base_vseq` virtual sequence is extended from `cip_base_vseq` and serves as a starting point. +It provides commonly used handles, variables, functions and tasks used by the test sequences. +Some of the most commonly used tasks and functions are as follows: +* task `wait_for_fast_fsm`: + Waits for the fast fsm to be active or inactive, indicated by whether the `fetch_en_o` output become On or Off respectively. + We mostly call this expecting it to be active before the tests can start, since any CSR accesses require the CPU to be running. + Due to complexities in the UVM sequences this task is called in the virtual post_apply_reset task of dv_base_vseq. +* task `wait_for_csr_to_propagate_to_slow_domain`: + Waits for `cfg_cdc_sync` CSR to be clear, indicating the CDC to the slow clock has completed. +* task `wait_for_reset_cause`: + Waits for the `pwr_rst_req.reset_cause` output to match an expected cause. +* task `check_wait_info`: + Checks the wake_info CSR matches expectations. +* task `check_reset_status`: + Checks the reset_status CSR matches expectations. +* task `check_and_clear_interrupt`: + Checks the interrupt enable, status, and output pin. + +In addition, the base sequence provides two tasks that provide expected inputs based on the pwrmgr outputs. +In the absence of these inputs the pwrmgr will be stuck waiting forever. +Being based on outputs means the inputs are in accordance to the implicit protocol. +The tasks in question are: +* task `slow_responder`: + Handles required input changes from AST for the slow state machine. + For the various `_en` outputs it changes the `_val` as required, for `core`, `io`, `main`, and `usb` clocks. +* task `fast_responder`: + Handles input changes for the fast state machine. + * Completes the handshake with rstmgr for lc and sys resets: some random cycles after an output reset is requested the corresponding reset src input must go low. + * Completes the handshake with clkmgr: the various `_status` inputs need to match the corresponding `_ip_clk_en` output after some cycles, for `io`, `main`, and `usb` clocks. + * Completes the handshake with lc and otp: both *_done inputs must match the corresponding *_init outputs after some cycles. + +These tasks are started by the parent sequence's `pre_start` task, and terminated gracefully in the parent sequence's `post_start` task. +${"###"} Test sequences +The test sequences besides the base are as follows: +* `pwrmgr_smoke_vseq` tests the pwrmgr through POR, entry and exit from software initiated low power and reset. +* `pwrmgr_wakeup_vseq` checks the transitions to low power and the wakeup settings. + It randomizes wakeup inputs, wakeup enables, the wakeup info capture enable, and the interrupt enable. +* `pwrmgr_aborted_low_power_vseq` creates scenarios that lead to aborting a low power transition. + The abort can be due to the processor waking up very soon, or otp, lc, or flash being busy. +* `pwrmgr_reset_vseq` checks the pwrmgr response to conditional resets and reset enables, and unconditional escalation and main power glitch resets. +* `pwrmgr_wakeup_reset_vseq` aligns reset and wakeup from low power. +* `pwrmgr_lowpower_wakeup_race_vseq` aligns a wakeup event coming in proximity to low power entry. + Notice the wakeup is not expected to impact low power entry, since it is not sampled at this time. + +${"###"} Functional coverage +To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. +The following covergroups have been developed to prove that the test intent has been adequately met: +* `wakeup_ctrl_cg` covers wakeup and capture control. +* `wakeup_intr_cg` covers control of the interrupt due to a wakeup. +* `control_cg` covers clock controls. +* `hw_reset_0_cg` covers external reset via `rstreqs_i[0]`. +* `hw_reset_1_cg` covers external reset via `rstreqs_i[1]`. +* `rstmgr_sw_reset_cg` covers software initiated resets via rstmgr CSR. +* `main_power_reset_cg` covers resets due to a main power glitch. +* `esc_reset_cg` covers resets due to an incoming escalation. +* `reset_wakeup_distance_cg` covers the distance in clock cycles between a wakeup and a reset request. + +More details about these sequences and covergroups can be found at [testplan](#testplan). + +${"###"} Self-checking strategy +Many of the checks are performed via SVA, and are enabled for all test sequences. +Refer to the [assertions](#assertions) section below for details. + +${"####"} Scoreboard +The `pwrmgr_scoreboard` is primarily used for end to end checking. + +Many inputs must have specific transitions to prevent the pwrmgr fsms from wait forever. +When possible the transitions are triggered by pwrmgr output changes. +These are described according to the unit that originates or is the recipient of the ports. +See also the test plan for specific ways these are driven to trigger different testpoints. + +${"#####"} AST +- Output `slow_clk_en` is always on. +- Input `slow_clk_val` is unused. +- Outputs `core_clk_en`, `io_clk_en`, and `usb_clk_en` reset low, and go high prior to the slow fsm requesting the fast fsm to wakeup. + Notice the usb clock can be programmed to stay low on wakeup via the `control` CSR. + These clock enables are cleared on reset, and should match their corresponding enables in the `control` CSR on low power transitions. + These clock enables are checked via SVAs in [`hw/${top_name}/ip_autogen/pwrmgr/dv/sva/pwrmgr_clock_enables_sva_if.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/${top_name}/ip_autogen/pwrmgr/dv/sva/pwrmgr_clock_enables_sva_if.sv). + When slow fsm transitions to `SlowPwrStateReqPwrUp` the clock enables should be on (except usb should match `control.usb_clk_en_active`). + When slow fsm transitions to `SlowPwrStatePwrClampOn` the clock enables should match their bits in the `control` CSR. +- Inputs `core_clk_val`, `io_clk_val`, and `usb_clk_val` track the corresponding enables. + They are driven by `slow_responder`, which turn them off when their enables go off, and turn them back on a few random slow clock cycles after their enables go on. + Slow fsm waits for them to go high prior to requesting fast fsm wakeup. + Lack of a high transition when needed is detected via timeout. + Such timeout would be due to the corresponding enables being set incorrectly. + These inputs are checked via SVAs in [`hw/${top_name}/ip_autogen/pwrmgr/dv/sva/pwrmgr_ast_sva_if.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/${top_name}/ip_autogen/pwrmgr/dv/sva/pwrmgr_ast_sva_if.sv). +- Output `main_pd_n` should go high when slow fsm transitions to `SlowPwrStateMainPowerOn`, and should match `control.main_pd_n` CSR when slow fsm transitions to `SlowPwrStateMainPowerOff`. +- Input `main_pok` should turn on for the slow fsm to start power up sequence. + This is also driven by `slow_responder`, which turn this off in response to `main_pd_n` going low, and turn it back on after a few random slow clock cycles from `main_pd_n` going high. + Lack of a high transition causes a timeout, and would point to `main_pd_n` being set incorrectly. +- Output transitions of `pwr_clamp_env` must always precede transitions of + `pwr_clamp` output. + Output transitions of `pwr_clamp` to active must always precede transitions + of `main_pd_n` output to active. + Output transitions of `pwr_clamp` to inactive must always follow transitions + of `main_pd_n` output to inactive. + +${"#####"} RSTMGR +- Output `rst_lc_req` resets to 1, also set on reset transition, and on low power transitions that turn off main clock. + Cleared early on during the steps to fast fsm active. +- Input `rst_lc_src_n` go low in response to `rst_lc_req` high, go high when `rst_lc_req` clears (and lc is reset). + Driven by `fast_responder` in response to `rst_lc_req`, waiting a few random cycles prior to transitions. + Fast fsm waits for it to go low before deactivating, and for it to go high before activating. + Checked implicitly by lack of timeout: a timeout would be due to `rst_lc_req` being set incorrectly, and by SVA as described below. +- Output `rst_sys_req` resets to 1, also set to on reset, and on low power transitions that turn off main clock. + Cleared right before the fast fsm goes active. +- Input `rst_sys_src_n` go low in response to `rst_sys_req` high. + Transitions go high when `rst_sysd_req` clears (and lc is reset). + Fast fsm waits for it to go low before deactivating. + Also driver by `fast_responder`. + Checked implicitly by lack of timeout, and by SVA. +- Output `rstreqs` correspond to the enabled pwrmgr rstreqs inputs plus main power glitch, escalation reset, and software reset request from RSTMGR. + Checked in scoreboard and SVA. +- Output `reset_cause` indicates a reset is due to low power entry or a reset request. + Checked in scoreboard. + +${"#####"} CLKMGR +- Outputs `pwr_clk_o._ip_clk_en` reset low, are driven high by fast fsm when going active, and driven low when going inactive. + The `` correspond to `io`, `main`, and `usb`. +- Inputs `pwr_clk_i._status` are expected to track `pwr_clk_o._ip_clk_en`. + Fast fsm waits for them going high prior to going active, and going low prior to deactivating. + These are controlled by the `control` CSR. + Driven by `fast_responder`, which turns them off when `_ip_clk_en` goes low, and turns them back on a few random cycles after `_ip_clk_en` goes high. + Checked by lack of a timeout: such timeout would be due to `ip_clk_en` being set incorrectly. + Also checked by SVA. + +${"#####"} OTP +- Output `otp_init` resets low, goes high when the fast fsm is going active, and low after the `otp_done` input goes high. +- Input `otp_done` is driven by `fast_responder`. + It is initialized low, and goes high some random cycles after `otp_init` goes high. + The sequencer will timeout if `otp_init` is not driven high. +- Input `otp_idle` normally set high, but is set low by the `pwrmgr_aborted_low_power_vseq` sequence. + +${"#####"} LC +The pins connecting to LC behave pretty much the same way as those to OTP. + +${"#####"} FLASH +- Input `flash_idle` is handled much like `lc_idle` and `otp_idle`. + +${"#####"} CPU +- Input `core_sleeping` is driven by sequences. + It is driven low to enable a transition to low power. + After the transition is under way it is a don't care. + The `pwrmgr_aborted_low_power_vseq` sequence sets it carefully to abort a low power entry soon after the attempt because the processor wakes up. + +${"#####"} Wakeups and Resets +There are a number of wakeup and reset requests. +They are driven by sequences as they need to. + +${"####"} Assertions +The [`hw/${top_name}/ip_autogen/pwrmgr/dv/sva/pwrmgr_bind.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/${top_name}/ip_autogen/pwrmgr/dv/sva/pwrmgr_bind.sv) module binds a few modules containing assertions to the IP as follows: +* TLUL assertions: the `tlul_assert` [assertions](../../../../ip/tlul/doc/TlulProtocolChecker.md) ensures TileLink interface protocol compliance. +* Clock enables assertions: + The `pwrmgr_clock_enables_sva_if` module contains assertions checking that the various clk_en outputs correspond to the settings in the `control` CSR. +* CLKMGR clk_en to status handshake assertions: + The `clkmgr_pwrmgr_sva_if` contains assertions checking the various `_status` inputs track the corresponding `_ip_clk_en` outputs. +* AST input/output handshake assertions: + The `pwrmgr_ast_sva_if` module contains assertions checking that the inputs from the AST respond to the pwrmgr outputs. +* RSTMGR input/output handshake assertions: + The `pwrmgr_rstmgr_sva_if` module contains assertions checking the following: + * The `rst_lc_src_n` input from RSTMGR respond to the `rst_lc_req` pwrmgr output. + * The `rst_sys_src_n` input from RSTMGR respond to the `rst_sys_req` pwrmgr output. + * The different `pwr_rst_o.rstreqs` output bits track the corresponding reset causes. + These include hardware, power glitch, escalation, and software resets. + +In addition, the RTL has assertions to ensure all outputs are initialized to known values after coming out of reset. + +${"##"} Building and running tests +We are using our in-house developed [regression tool](../../../../../util/dvsim/README.md) for building and running our tests and regressions. +Please take a look at the link for detailed information on the usage, capabilities, features and known issues. +Here's how to run a smoke test: +```console +$ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/${top_name}/ip_autogen/pwrmgr/dv/pwrmgr_sim_cfg.hjson -i pwrmgr_smoke +``` + +${"##"} Testplan +[Testplan](../data/pwrmgr_testplan.hjson) diff --git a/src/pwrmgr/dv/cov/pwrmgr_cov_bind.sv b/src/pwrmgr/dv/cov/pwrmgr_cov_bind.sv new file mode 100644 index 0000000..d3a4d08 --- /dev/null +++ b/src/pwrmgr/dv/cov/pwrmgr_cov_bind.sv @@ -0,0 +1,33 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Description: +// Power manager coverage bindings for multi bus input +module pwrmgr_cov_bind; + + bind pwrmgr cip_lc_tx_cov_if u_lc_dft_en_mubi_cov_if ( + .rst_ni (rst_ni), + .val (lc_dft_en_i) + ); + + bind pwrmgr cip_lc_tx_cov_if u_lc_hw_debug_en_mubi_cov_if ( + .rst_ni (rst_ni), + .val (lc_hw_debug_en_i) + ); + + bind pwrmgr cip_mubi_cov_if #(.Width(prim_mubi_pkg::MuBi4Width)) u_rom_ctrl_good_mubi_cov_if ( + .rst_ni (rst_ni), + .mubi (rom_ctrl_i.done) + ); + + bind pwrmgr cip_mubi_cov_if #(.Width(prim_mubi_pkg::MuBi4Width)) u_rom_ctrl_done_mubi_cov_if ( + .rst_ni (rst_ni), + .mubi (rom_ctrl_i.good) + ); + + bind pwrmgr cip_mubi_cov_if #(.Width(prim_mubi_pkg::MuBi4Width)) u_sw_rst_req_mubi_cov_if ( + .rst_ni (rst_ni), + .mubi (sw_rst_req_i) + ); +endmodule // pwrmgr_cov_bind diff --git a/src/pwrmgr/dv/cov/pwrmgr_cov_manual_excl.el b/src/pwrmgr/dv/cov/pwrmgr_cov_manual_excl.el new file mode 100644 index 0000000..6e3e974 --- /dev/null +++ b/src/pwrmgr/dv/cov/pwrmgr_cov_manual_excl.el @@ -0,0 +1,34 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +//================================================== +// This file contains the Excluded objects +// Generated By User: jdonjdon +// Format Version: 2 +// Date: Sun Sep 25 22:09:48 2022 +// ExclMode: default +//================================================== +CHECKSUM: "2301929872 963630968" +INSTANCE: tb.dut.u_esc_rx.u_prim_count +ANNOTATION: "[UNSUPPORTED] Ports are assigned constant by RTL." +Toggle step_i "net step_i[21:0]" +Toggle set_cnt_i "net set_cnt_i[21:0]" +CHECKSUM: "3681358461" +INSTANCE: tb.dut.u_esc_timeout.u_ref_timeout +ANNOTATION: "[UNR] Input req_chk_i is tied to constant 0 and src_req_i to constant 1" +Assert SyncReqAckHoldReq "assertion" +CHECKSUM: "2699797328" +INSTANCE: tb.dut.pwrmgr_ast_sva_if +ANNOTATION: "[UNR] por_d0_ni input is tied to constant 1" +Assert CoreClkGlitchToEnOff_A "assertion" +ANNOTATION: "[UNR] por_d0_ni input is tied to constant 1" +Assert UsbClkGlitchToValOff_A "assertion" +ANNOTATION: "[UNR] por_d0_ni input is tied to constant 1" +Assert UsbClkGlitchToEnOff_A "assertion" +ANNOTATION: "[UNR] por_d0_ni input is tied to constant 1" +Assert IoClkGlitchToValOff_A "assertion" +ANNOTATION: "[UNR] por_d0_ni input is tied to constant 1" +Assert IoClkGlitchToEnOff_A "assertion" +ANNOTATION: "[UNR] por_d0_ni input is tied to constant 1" +Assert CoreClkGlitchToValOff_A "assertion" diff --git a/src/pwrmgr/dv/doc/tb.svg b/src/pwrmgr/dv/doc/tb.svg new file mode 100644 index 0000000..285ef69 --- /dev/null +++ b/src/pwrmgr/dv/doc/tb.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/src/pwrmgr/dv/env/pwrmgr_env.core b/src/pwrmgr/dv/env/pwrmgr_env.core new file mode 100644 index 0000000..731e280 --- /dev/null +++ b/src/pwrmgr/dv/env/pwrmgr_env.core @@ -0,0 +1,55 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:dv:pwrmgr_env:0.1" +description: "PWRMGR DV UVM environment" +filesets: + files_dv: + depend: + - lowrisc:dv:ralgen + - lowrisc:dv:cip_lib + - lowrisc:ip_interfaces:pwrmgr_pkg + files: + - pwrmgr_env_pkg.sv + - pwrmgr_env_cfg.sv: {is_include_file: true} + - pwrmgr_env_cov.sv: {is_include_file: true} + - pwrmgr_if.sv + - pwrmgr_virtual_sequencer.sv: {is_include_file: true} + - pwrmgr_scoreboard.sv: {is_include_file: true} + - pwrmgr_env.sv: {is_include_file: true} + - seq_lib/pwrmgr_vseq_list.sv: {is_include_file: true} + - seq_lib/pwrmgr_base_vseq.sv: {is_include_file: true} + - seq_lib/pwrmgr_aborted_low_power_vseq.sv: {is_include_file: true} + - seq_lib/pwrmgr_common_vseq.sv: {is_include_file: true} + - seq_lib/pwrmgr_lowpower_wakeup_race_vseq.sv: {is_include_file: true} + - seq_lib/pwrmgr_reset_vseq.sv: {is_include_file: true} + - seq_lib/pwrmgr_smoke_vseq.sv: {is_include_file: true} + - seq_lib/pwrmgr_stress_all_vseq.sv: {is_include_file: true} + - seq_lib/pwrmgr_wakeup_reset_vseq.sv: {is_include_file: true} + - seq_lib/pwrmgr_wakeup_vseq.sv: {is_include_file: true} + - seq_lib/pwrmgr_repeat_wakeup_reset_vseq.sv: {is_include_file: true} + - seq_lib/pwrmgr_sw_reset_vseq.sv: {is_include_file: true} + - seq_lib/pwrmgr_esc_clk_rst_malfunc_vseq.sv: {is_include_file: true} + - seq_lib/pwrmgr_sec_cm_ctrl_config_regwen_vseq.sv: {is_include_file: true} + - seq_lib/pwrmgr_global_esc_vseq.sv: {is_include_file: true} + - seq_lib/pwrmgr_escalation_timeout_vseq.sv: {is_include_file: true} + - seq_lib/pwrmgr_glitch_vseq.sv: {is_include_file: true} + - seq_lib/pwrmgr_disable_rom_integrity_check_vseq.sv: {is_include_file: true} + - seq_lib/pwrmgr_reset_invalid_vseq.sv: {is_include_file: true} + - seq_lib/pwrmgr_lowpower_invalid_vseq.sv: {is_include_file: true} + file_type: systemVerilogSource + +generate: + ral: + generator: ralgen + parameters: + name: pwrmgr + ip_hjson: ../../data/pwrmgr.hjson + +targets: + default: + filesets: + - files_dv + generate: + - ral diff --git a/src/pwrmgr/dv/env/pwrmgr_env.sv b/src/pwrmgr/dv/env/pwrmgr_env.sv new file mode 100644 index 0000000..96646b5 --- /dev/null +++ b/src/pwrmgr/dv/env/pwrmgr_env.sv @@ -0,0 +1,57 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class pwrmgr_env extends cip_base_env #( + .CFG_T (pwrmgr_env_cfg), + .COV_T (pwrmgr_env_cov), + .VIRTUAL_SEQUENCER_T(pwrmgr_virtual_sequencer), + .SCOREBOARD_T (pwrmgr_scoreboard) +); + `uvm_component_utils(pwrmgr_env) + + alert_esc_agent m_esc_agent; + `uvm_component_new + + function void build_phase(uvm_phase phase); + super.build_phase(phase); + if (!uvm_config_db#(virtual clk_rst_if)::get( + this, "", "slow_clk_rst_vif", cfg.slow_clk_rst_vif + )) begin + `uvm_fatal(`gfn, "failed to get slow_clk_rst_vif from uvm_config_db") + end + if (!uvm_config_db#(virtual clk_rst_if)::get( + this, "", "esc_clk_rst_vif", cfg.esc_clk_rst_vif + )) begin + `uvm_fatal(`gfn, "failed to get esc_clk_rst_vif from uvm_config_db") + end + if (!uvm_config_db#(virtual clk_rst_if)::get( + this, "", "lc_clk_rst_vif", cfg.lc_clk_rst_vif + )) begin + `uvm_fatal(`gfn, "failed to get lc_clk_rst_vif from uvm_config_db") + end + if (!uvm_config_db#(virtual pwrmgr_if)::get(this, "", "pwrmgr_vif", cfg.pwrmgr_vif)) begin + `uvm_fatal(`gfn, "failed to get pwrmgr_vif from uvm_config_db") + end + if (!uvm_config_db#(virtual pwrmgr_clock_enables_sva_if)::get( + this, "", "pwrmgr_clock_enables_sva_vif", cfg.pwrmgr_clock_enables_sva_vif + )) begin + `uvm_fatal(`gfn, "failed to get pwrmgr_clock_enables_sva_vif from uvm_config_db") + end + if (!uvm_config_db#(virtual pwrmgr_rstmgr_sva_if)::get( + this, "", "pwrmgr_rstmgr_sva_vif", cfg.pwrmgr_rstmgr_sva_vif + )) begin + `uvm_fatal(`gfn, "failed to get pwrmgr_rstmgr_sva_vif from uvm_config_db") + end + + m_esc_agent = alert_esc_agent::type_id::create("m_esc_agent", this); + uvm_config_db#(alert_esc_agent_cfg)::set(this, "m_esc_agent", "cfg", cfg.m_esc_agent_cfg); + cfg.m_esc_agent_cfg.en_cov = cfg.en_cov; + + endfunction + + function void connect_phase(uvm_phase phase); + super.connect_phase(phase); + endfunction + +endclass diff --git a/src/pwrmgr/dv/env/pwrmgr_env_cfg.sv b/src/pwrmgr/dv/env/pwrmgr_env_cfg.sv new file mode 100644 index 0000000..b94e743 --- /dev/null +++ b/src/pwrmgr/dv/env/pwrmgr_env_cfg.sv @@ -0,0 +1,52 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class pwrmgr_env_cfg extends cip_base_env_cfg #( + .RAL_T(pwrmgr_reg_block) +); + + // disable fault csr read check from scoreboard + bit disable_csr_rd_chk = 0; + + // Invalid state test. Used to disable interrupt check. + bit invalid_st_test = 0; + + // ext component cfgs + alert_esc_agent_cfg m_esc_agent_cfg; + + `uvm_object_utils_begin(pwrmgr_env_cfg) + `uvm_object_utils_end + + `uvm_object_new + + // ext interfaces + virtual clk_rst_if esc_clk_rst_vif; + virtual clk_rst_if lc_clk_rst_vif; + virtual clk_rst_if slow_clk_rst_vif; + virtual pwrmgr_if pwrmgr_vif; + virtual pwrmgr_clock_enables_sva_if pwrmgr_clock_enables_sva_vif; + virtual pwrmgr_rstmgr_sva_if pwrmgr_rstmgr_sva_vif; + + // The run_phase object, to deal with objections. + uvm_phase run_phase; + + virtual function void initialize(bit [31:0] csr_base_addr = '1); + list_of_alerts = pwrmgr_env_pkg::LIST_OF_ALERTS; + super.initialize(csr_base_addr); + num_interrupts = ral.intr_state.get_n_used_bits(); + `ASSERT_I(NumInstrMatch_A, num_interrupts == NUM_INTERRUPTS) + `uvm_info(`gfn, $sformatf("num_interrupts = %0d", num_interrupts), UVM_MEDIUM) + + // pwrmgr_tl_intg_err test uses default alert name "fata_fault" + // and it requires following field to be '1' + tl_intg_alert_fields[ral.fault_status.reg_intg_err] = 1; + m_tl_agent_cfg.max_outstanding_req = 1; + m_esc_agent_cfg = alert_esc_agent_cfg::type_id::create("m_esc_agent_cfg"); + `DV_CHECK_RANDOMIZE_FATAL(m_esc_agent_cfg) + m_esc_agent_cfg.is_alert = 0; + // Disable escalation ping coverage. + m_esc_agent_cfg.en_ping_cov = 0; + endfunction + +endclass diff --git a/src/pwrmgr/dv/env/pwrmgr_env_cov.sv b/src/pwrmgr/dv/env/pwrmgr_env_cov.sv new file mode 100644 index 0000000..b348b99 --- /dev/null +++ b/src/pwrmgr/dv/env/pwrmgr_env_cov.sv @@ -0,0 +1,193 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +/** + * Covergoups that are dependent on run-time parameters that may be available + * only in build_phase can be defined here. + * Covergroups may also be wrapped inside helper classes if needed. + */ + +`include "cip_macros.svh" + +// Wrapper class for wakeup control covergroup. +class pwrmgr_wakeup_ctrl_cg_wrap; + // This covers enable, capture, and status of wakeups. + covergroup wakeup_ctrl_cg(string name) with function sample (bit enable, bit capture, bit wakeup); + option.name = name; + option.per_instance = 1; + + enable_cp: coverpoint enable; + capture_cp: coverpoint capture; + wakeup_cp: coverpoint wakeup; + + wakeup_cross: cross enable_cp, capture_cp, wakeup_cp; + endgroup + + function new(string name); + wakeup_ctrl_cg = new(name); + endfunction + + function void sample (bit enable, bit capture, bit wakeup); + wakeup_ctrl_cg.sample(enable, capture, wakeup); + endfunction +endclass + +// Wrapper class for wakeup interrupt covergroup. +class pwrmgr_wakeup_intr_cg_wrap; + // This covers interrupts generated by wakeups. + covergroup wakeup_intr_cg( + string name + ) with function sample ( + bit wakeup, bit enable, bit status, bit interrupt + ); + option.name = name; + option.per_instance = 1; + + enable_cp: coverpoint enable; + status_cp: coverpoint status; + wakeup_cp: coverpoint wakeup; + interrupt_cp: coverpoint interrupt; + + interrupt_cross: cross enable_cp, status_cp, wakeup_cp, interrupt_cp{ + // An interrupt cannot happen unless wake_status is on. + ignore_bins no_wakeup = interrupt_cross with (!wakeup_cp && interrupt_cp); + // An interrupt cannot happen unless it is enabled. + ignore_bins disable_pin = interrupt_cross with (!enable_cp && interrupt_cp); + // An interrupt cannot happen if intr_status is off. + ignore_bins no_status_pin = interrupt_cross with (!status_cp && interrupt_cp); + // If all preconditions are satisfied there must be an interrupt. + ignore_bins missing_int = interrupt_cross with (enable_cp && status_cp && wakeup_cp && + !interrupt_cp); + } + endgroup + + function new(string name); + wakeup_intr_cg = new(name); + endfunction + + function void sample (bit enable, bit status, bit wakeup, bit interrupt); + wakeup_intr_cg.sample(wakeup, enable, status, interrupt); + endfunction +endclass + +class pwrmgr_env_cov extends cip_base_env_cov #( + .CFG_T(pwrmgr_env_cfg) +); + `uvm_component_utils(pwrmgr_env_cov) + + // the base class provides the following handles for use: + // pwrmgr_env_cfg: cfg + + // covergroups + pwrmgr_wakeup_ctrl_cg_wrap wakeup_ctrl_cg_wrap[pwrmgr_reg_pkg::NumWkups]; + pwrmgr_wakeup_intr_cg_wrap wakeup_intr_cg_wrap[pwrmgr_reg_pkg::NumWkups]; + + // This collects coverage on the clock and power control functionality. + covergroup control_cg with function sample (control_enables_t control_enables, bit sleep); + core_cp: coverpoint control_enables.core_clk_en; + io_cp: coverpoint control_enables.io_clk_en; + usb_lp_cp: coverpoint control_enables.usb_clk_en_lp; + usb_active_cp: coverpoint control_enables.usb_clk_en_active; + main_pd_n_cp: coverpoint control_enables.main_pd_n; + sleep_cp: coverpoint sleep; + + control_cross: cross core_cp, io_cp, usb_lp_cp, usb_active_cp, main_pd_n_cp, sleep_cp; + endgroup + + covergroup hw_reset_0_cg with function sample (logic reset, logic enable, bit sleep); + reset_cp: coverpoint reset; + enable_cp: coverpoint enable; + sleep_cp: coverpoint sleep; + reset_cross: cross reset_cp, enable_cp, sleep_cp { + // Reset and sleep are mutually exclusive. + illegal_bins illegal = reset_cross with (reset_cp && sleep_cp); + } + endgroup + + covergroup hw_reset_1_cg with function sample (logic reset, logic enable, bit sleep); + reset_cp: coverpoint reset; + enable_cp: coverpoint enable; + sleep_cp: coverpoint sleep; + reset_cross: cross reset_cp, enable_cp, sleep_cp { + // Reset and sleep are mutually exclusive. + illegal_bins illegal = reset_cross with (reset_cp && sleep_cp); + } + endgroup + + // This reset cannot be generated in low power state since it is triggered by software. + covergroup rstmgr_sw_reset_cg with function sample (logic sw_reset); + sw_reset_cp: coverpoint sw_reset; + endgroup + + covergroup main_power_reset_cg with function sample (logic main_power_reset, bit sleep); + main_power_reset_cp: coverpoint main_power_reset; + sleep_cp: coverpoint sleep; + reset_cross: cross main_power_reset_cp, sleep_cp { + // Any reset and sleep are mutually exclusive. + illegal_bins illegal = reset_cross with (main_power_reset_cp && sleep_cp); + } + endgroup + + covergroup esc_reset_cg with function sample (logic esc_reset, bit sleep); + esc_reset_cp: coverpoint esc_reset; + sleep_cp: coverpoint sleep; + reset_cross: cross esc_reset_cp, sleep_cp { + // Any reset and sleep are mutually exclusive. + illegal_bins illegal = reset_cross with (esc_reset_cp && sleep_cp); + } + endgroup + + // This measures the number of cycles between the reset and wakeup. + // It is positive when reset happened after wakeup, and zero when they coincided in time. + covergroup reset_wakeup_distance_cg with function sample (int cycles); + cycles_cp: coverpoint cycles { + bins close[] = {[-4 : 4]}; + bins far = default; + } + endgroup + + // This covers the rom inputs that should prevent entering the active state. + covergroup rom_active_blockers_cg with function sample ( + logic [3:0] done, logic [3:0] good, logic [3:0] dft, logic [3:0] debug + ); + done_cp: coverpoint done { + `DV_MUBI4_CP_BINS + } + good_cp: coverpoint good { + `DV_MUBI4_CP_BINS + } + dft_cp: coverpoint dft { + `DV_LC_TX_T_CP_BINS + } + debug_cp: coverpoint debug { + `DV_LC_TX_T_CP_BINS + } + blockers_cross: cross done_cp, good_cp, dft_cp, debug_cp; + endgroup + + function new(string name, uvm_component parent); + super.new(name, parent); + foreach (wakeup_ctrl_cg_wrap[i]) begin + pwrmgr_env_pkg::wakeup_e wakeup = pwrmgr_env_pkg::wakeup_e'(i); + wakeup_ctrl_cg_wrap[i] = new({wakeup.name, "_ctrl_cg"}); + wakeup_intr_cg_wrap[i] = new({wakeup.name, "_intr_cg"}); + end + control_cg = new(); + hw_reset_0_cg = new(); + hw_reset_1_cg = new(); + rstmgr_sw_reset_cg = new(); + main_power_reset_cg = new(); + esc_reset_cg = new(); + reset_wakeup_distance_cg = new(); + rom_active_blockers_cg = new(); + endfunction : new + + virtual function void build_phase(uvm_phase phase); + super.build_phase(phase); + // [or instantiate covergroups here] + // Please instantiate sticky_intr_cov array of objects for all interrupts that are sticky + // See cip_base_env_cov for details + endfunction + +endclass diff --git a/src/pwrmgr/dv/env/pwrmgr_env_pkg.sv b/src/pwrmgr/dv/env/pwrmgr_env_pkg.sv new file mode 100644 index 0000000..abfb1c0 --- /dev/null +++ b/src/pwrmgr/dv/env/pwrmgr_env_pkg.sv @@ -0,0 +1,89 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +package pwrmgr_env_pkg; + // dep packages + import uvm_pkg::*; + import top_pkg::*; + import dv_utils_pkg::*; + import dv_lib_pkg::*; + import tl_agent_pkg::*; + import cip_base_pkg::*; + import dv_base_reg_pkg::*; + import csr_utils_pkg::*; + import pwrmgr_ral_pkg::*; + import alert_esc_agent_pkg::*; + import pwrmgr_pkg::PowerDomains; + import prim_mubi_pkg::mubi4_t; + import prim_mubi_pkg::MuBi4False; + import prim_mubi_pkg::MuBi4True; + import prim_mubi_pkg::MuBi4Width; + import sec_cm_pkg::*; + // macro includes + `include "uvm_macros.svh" + `include "dv_macros.svh" + + // parameters + parameter int NUM_INTERRUPTS = 1; + + // clk enable disable delay + parameter uint MAIN_CLK_DELAY_MIN = 15; + parameter uint MAIN_CLK_DELAY_MAX = 258; + parameter uint ESC_CLK_DELAY_MIN = 1; + parameter uint ESC_CLK_DELAY_MAX = 10; + + // alerts + parameter uint NUM_ALERTS = 1; + parameter string LIST_OF_ALERTS[] = {"fatal_fault"}; + + // types + typedef enum int { + WakeupSysrst, + WakeupDbgCable, + WakeupPin, + WakeupUsb, + WakeupAonTimer, + WakeupSensorCtrl + } wakeup_e; + + typedef enum int { + PwrmgrMubiNone = 0, + PwrmgrMubiLcCtrl = 1, + PwrmgrMubiRomCtrl = 2 + } pwrmgr_mubi_e; + + typedef struct packed { + logic main_pd_n; + logic usb_clk_en_active; + logic usb_clk_en_lp; + logic io_clk_en; + logic core_clk_en; + } control_enables_t; + + typedef bit [pwrmgr_reg_pkg::NumWkups-1:0] wakeups_t; + typedef bit [pwrmgr_reg_pkg::NumRstReqs-1:0] resets_t; + + // This is used to send all resets to rstmgr. + typedef bit [pwrmgr_pkg::HwResetWidth-1:0] resets_out_t; + + // need a short name to avoid 100 line cut off + parameter int MUBI4W = prim_mubi_pkg::MuBi4Width; + + // functions + + // variables + bit [NUM_INTERRUPTS-1:0] exp_intr; + wakeups_t exp_wakeup_reasons; + control_enables_t control_enables; + logic low_power_hint; + + // package sources + `include "pwrmgr_env_cfg.sv" + `include "pwrmgr_env_cov.sv" + `include "pwrmgr_virtual_sequencer.sv" + `include "pwrmgr_scoreboard.sv" + `include "pwrmgr_env.sv" + `include "pwrmgr_vseq_list.sv" + +endpackage diff --git a/src/pwrmgr/dv/env/pwrmgr_if.sv b/src/pwrmgr/dv/env/pwrmgr_if.sv new file mode 100644 index 0000000..2a6e720 --- /dev/null +++ b/src/pwrmgr/dv/env/pwrmgr_if.sv @@ -0,0 +1,219 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// pwrmgr interface. +// +// Samples some internal signals to help coverage collection: +interface pwrmgr_if ( + input logic clk, + input logic rst_n, + input logic clk_slow, + input logic rst_slow_n +); + import uvm_pkg::*; + import pwrmgr_env_pkg::*; + + // Ports to the dut side. + + logic rst_main_n; + + pwrmgr_pkg::pwr_ast_req_t pwr_ast_req; + pwrmgr_pkg::pwr_ast_rsp_t pwr_ast_rsp; + + pwrmgr_pkg::pwr_rst_req_t pwr_rst_req; + pwrmgr_pkg::pwr_rst_rsp_t pwr_rst_rsp; + + pwrmgr_pkg::pwr_clk_req_t pwr_clk_req; + pwrmgr_pkg::pwr_clk_rsp_t pwr_clk_rsp; + + pwrmgr_pkg::pwr_otp_req_t pwr_otp_req; + pwrmgr_pkg::pwr_otp_rsp_t pwr_otp_rsp; + + pwrmgr_pkg::pwr_lc_req_t pwr_lc_req; + pwrmgr_pkg::pwr_lc_rsp_t pwr_lc_rsp; + + pwrmgr_pkg::pwr_flash_t pwr_flash; + + pwrmgr_pkg::pwrmgr_cpu_t cpu_i; + pwrmgr_pkg::pwr_cpu_t pwr_cpu; + + lc_ctrl_pkg::lc_tx_t fetch_en; + lc_ctrl_pkg::lc_tx_t lc_hw_debug_en; + lc_ctrl_pkg::lc_tx_t lc_dft_en; + + logic [ pwrmgr_reg_pkg::NumWkups-1:0] wakeups_i; + logic [pwrmgr_reg_pkg::NumRstReqs-1:0] rstreqs_i; + + logic strap; + logic low_power; + rom_ctrl_pkg::pwrmgr_data_t rom_ctrl; + + prim_mubi_pkg::mubi4_t sw_rst_req_i; + + logic intr_wakeup; + + // Relevant CSR values. + logic wakeup_en_regwen; + logic [ pwrmgr_reg_pkg::NumWkups-1:0] wakeup_en; + logic [ pwrmgr_reg_pkg::NumWkups-1:0] wakeup_status; + logic wakeup_capture_en; + + logic [pwrmgr_reg_pkg::NumRstReqs-1:0] reset_en; + logic [pwrmgr_reg_pkg::NumRstReqs-1:0] reset_en_q; + logic [pwrmgr_reg_pkg::NumRstReqs-1:0] reset_status; + + logic lowpwr_cfg_wen; + pwrmgr_reg_pkg::pwrmgr_hw2reg_wake_info_reg_t wake_info; + + // Internal DUT signals. +`ifndef PATH_TO_DUT + `define PATH_TO_DUT tb.dut +`endif + + // Slow fsm state. + pwrmgr_pkg::slow_pwr_state_e slow_state; + always_comb slow_state = `PATH_TO_DUT.u_slow_fsm.state_q; + + // Fast fsm state. + pwrmgr_pkg::fast_pwr_state_e fast_state; + always_comb fast_state = `PATH_TO_DUT.u_fsm.state_q; + + // cfg regwen + always_comb lowpwr_cfg_wen = `PATH_TO_DUT.lowpwr_cfg_wen; + + // reset status + always_comb reset_status = {`PATH_TO_DUT.u_reg.reset_status_val_1_qs, + `PATH_TO_DUT.u_reg.reset_status_val_0_qs}; + always_comb reset_en_q = {`PATH_TO_DUT.u_reg.reset_en_en_1_qs, + `PATH_TO_DUT.u_reg.reset_en_en_0_qs}; + always_comb + wakeup_en = { + `PATH_TO_DUT.reg2hw.wakeup_en[5].q, + `PATH_TO_DUT.reg2hw.wakeup_en[4].q, + `PATH_TO_DUT.reg2hw.wakeup_en[3].q, + `PATH_TO_DUT.reg2hw.wakeup_en[2].q, + `PATH_TO_DUT.reg2hw.wakeup_en[1].q, + `PATH_TO_DUT.reg2hw.wakeup_en[0].q + }; + + // Wakeup_status ro CSR. + always_comb + wakeup_status = { + `PATH_TO_DUT.hw2reg.wake_status[5].d, + `PATH_TO_DUT.hw2reg.wake_status[4].d, + `PATH_TO_DUT.hw2reg.wake_status[3].d, + `PATH_TO_DUT.hw2reg.wake_status[2].d, + `PATH_TO_DUT.hw2reg.wake_status[1].d, + `PATH_TO_DUT.hw2reg.wake_status[0].d + }; + + always_comb wakeup_capture_en = !`PATH_TO_DUT.u_reg.wake_info_capture_dis_qs; + always_comb wake_info = `PATH_TO_DUT.i_wake_info.info_o; + + logic intr_enable; + always_comb intr_enable = `PATH_TO_DUT.reg2hw.intr_enable.q; + + logic intr_status; + always_comb intr_status = `PATH_TO_DUT.reg2hw.intr_state.q; + + // This is only used to determine if an interrupt will be set in case of a reset while in + // low power. tryIt is very hard to perdict if the reset or a wakeup happen first, so this + // signal is used to help instead. + pwrmgr_pkg::pwrup_cause_e pwrup_cause; + always_comb pwrup_cause = `PATH_TO_DUT.slow_pwrup_cause; + + // Used to disable assertions once with the first power glitch. + bit internal_assertion_disabled; + + function automatic void update_ast_main_pok(logic value); + pwr_ast_rsp.main_pok = value; + endfunction + + function automatic void update_otp_done(logic value); + pwr_otp_rsp.otp_done = value; + endfunction + + function automatic void update_otp_idle(logic value); + pwr_otp_rsp.otp_idle = value; + endfunction + + function automatic void update_lc_done(logic value); + pwr_lc_rsp.lc_done = value; + endfunction + + function automatic void update_lc_idle(logic value); + pwr_lc_rsp.lc_idle = value; + endfunction + + function automatic void update_flash_idle(logic value); + pwr_flash.flash_idle = value; + endfunction + + function automatic void update_cpu_sleeping(logic value); + pwr_cpu.core_sleeping = value; + endfunction + + function automatic void update_wakeups(logic [pwrmgr_reg_pkg::NumWkups-1:0] wakeups); + wakeups_i = wakeups; + endfunction + + function automatic void update_resets(logic [pwrmgr_reg_pkg::NumRstReqs-1:0] resets); + rstreqs_i = resets; + endfunction + + function automatic void update_reset_en( + logic [pwrmgr_reg_pkg::NumRstReqs-1:0] reset_en_value); + reset_en = reset_en_value; + endfunction + + function automatic void update_sw_rst_req(prim_mubi_pkg::mubi4_t value); + sw_rst_req_i = value; + endfunction + + // Sends a main power glitch and disables a design assertion that trips for power glitches. + task automatic glitch_power_reset(); + rst_main_n = 1'b0; + if (!internal_assertion_disabled) begin + internal_assertion_disabled = 1'b1; + `uvm_info("pwrmgr_if", "disabling power glitch related SVA", UVM_MEDIUM) + $assertoff(1, tb.dut.u_slow_fsm.IntRstReq_A); + end + repeat (2) @(posedge clk_slow); + rst_main_n = 1'b1; + endtask + + // FIXME Move all these initializations to sequences. + initial begin + // From AST. + pwr_ast_rsp = '{default: '0}; + pwr_rst_rsp = '{default: '0}; + pwr_clk_rsp = '{default: '0}; + pwr_otp_rsp = '{default: '0}; + pwr_lc_rsp = '{default: '0}; + pwr_flash = '{default: '0}; + pwr_cpu = pwrmgr_pkg::PWR_CPU_DEFAULT; + wakeups_i = pwrmgr_pkg::WAKEUPS_DEFAULT; + rstreqs_i = pwrmgr_pkg::RSTREQS_DEFAULT; + sw_rst_req_i = prim_mubi_pkg::MuBi4False; + rom_ctrl = rom_ctrl_pkg::PWRMGR_DATA_DEFAULT; + end + + clocking slow_cb @(posedge clk_slow); + input slow_state; + input pwr_ast_req; + output pwr_ast_rsp; + endclocking + + clocking fast_cb @(posedge clk); + input fast_state; + input pwr_rst_req; + output pwr_rst_rsp; + input pwr_clk_req; + output pwr_clk_rsp; + input pwr_lc_req; + output pwr_lc_rsp; + input pwr_otp_req; + output pwr_otp_rsp; + endclocking +endinterface diff --git a/src/pwrmgr/dv/env/pwrmgr_scoreboard.sv b/src/pwrmgr/dv/env/pwrmgr_scoreboard.sv new file mode 100644 index 0000000..1379896 --- /dev/null +++ b/src/pwrmgr/dv/env/pwrmgr_scoreboard.sv @@ -0,0 +1,361 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class pwrmgr_scoreboard extends cip_base_scoreboard #( + .CFG_T(pwrmgr_env_cfg), + .RAL_T(pwrmgr_reg_block), + .COV_T(pwrmgr_env_cov) +); + `uvm_component_utils(pwrmgr_scoreboard) + + // local variables + + // TLM agent fifos + + // local queues to hold incoming packets pending comparison + + `uvm_component_new + + function void build_phase(uvm_phase phase); + string common_seq_type; + super.build_phase(phase); + + void'($value$plusargs("run_%0s", common_seq_type)); + if (common_seq_type == "stress_all_with_rand_reset") do_alert_check = 0; + endfunction + + task run_phase(uvm_phase phase); + super.run_phase(phase); + cfg.run_phase = phase; + fork + monitor_power_glitch(); + monitor_escalation_timeout(); + reset_cip_helper(); + wakeup_ctrl_coverage_collector(); + wakeup_intr_coverage_collector(); + low_power_coverage_collector(); + reset_coverage_collector(); + rom_coverage_collector(); + join_none + endtask + + task monitor_power_glitch(); + fork + forever + @cfg.pwrmgr_vif.rst_main_n begin + if (cfg.pwrmgr_vif.rst_main_n == 1'b0 && `gmv(ral.control.main_pd_n)) begin + set_exp_alert("fatal_fault", 1, 500); + end + end + join + endtask + + // An escalation timeout is triggered in test sequences by stopping clk_esc_i or by driving + // rst_esc_ni active when the dut state is not expecting it. + task monitor_escalation_timeout(); + fork + forever + @(posedge cfg.esc_clk_rst_vif.clk_gate) begin + // A timeout could be triggered after more than 121 clk_i cycles, but this number + // is somewhat unpredictable for reasons explained in the pwrmgr_escalation_timeout + // sequence, so this relies on the sequence to avoid unpredictable stoppages. + `uvm_info(`gfn, "Detected unexpected clk_esc_i stop", UVM_MEDIUM) + fork + begin : isolation_fork + // This fork is so we can wait for a number of cycles with the clock inactive, + // and stop waiting if the escalation clock gate is re-opened. + fork + begin + cfg.clk_rst_vif.wait_clks(121); + if (cfg.esc_clk_rst_vif.clk_gate && cfg.pwrmgr_vif.pwr_ast_req.io_clk_en && + cfg.pwrmgr_vif.pwr_clk_req.io_ip_clk_en) begin + `uvm_info(`gfn, "clk_esc_i has been inactive enough to trigger an alert", + UVM_MEDIUM) + `uvm_info(`gfn, "set_exp_alert from monitor_escalation_timeout clock gated", + UVM_MEDIUM) + set_exp_alert("fatal_fault", 1, 500); + end + end + // This stops the wait if the gate is re-opened. + @(negedge cfg.esc_clk_rst_vif.clk_gate); + join_any + disable fork; + end + join + end + forever + @(negedge cfg.esc_clk_rst_vif.o_rst_n) begin + if (cfg.pwrmgr_vif.fetch_en == lc_ctrl_pkg::On) begin + `uvm_info(`gfn, "Detected unexpected rst_esc_ni active", UVM_MEDIUM) + set_exp_alert("fatal_fault", 1, 500); + end + end + join + endtask + + // We need to reset the cip scoreboard, since the alert handler responds + // to lc domain0 resets, yet the pwrmgr's clk_rst_vif is aon. So when a + // reset happens the cip scoreboard needs to be informed, both when reset + // starts and when it ends. + task reset_cip_helper(); + fork + forever + @cfg.pwrmgr_vif.pwr_rst_req.rst_lc_req begin + if (|cfg.pwrmgr_vif.pwr_rst_req.rst_lc_req) begin + // Start of d0 reset request. + `uvm_info(`gfn, "pwrmgr start reset in reset_cip_helper", UVM_MEDIUM) + cfg.reset_asserted(); + end + end + forever + @cfg.pwrmgr_vif.fetch_en begin + if (cfg.pwrmgr_vif.fetch_en == lc_ctrl_pkg::On) begin + // End of d0 reset request. + `uvm_info(`gfn, "pwrmgr end reset in reset_cip_helper", UVM_MEDIUM) + reset_alert_state(); + end + end + join + endtask + + task wakeup_ctrl_coverage_collector(); + forever + @(posedge (|cfg.pwrmgr_vif.wakeups_i)) begin + if (cfg.en_cov) begin + // Allow for synchronization delay. + cfg.slow_clk_rst_vif.wait_clks(2); + foreach (cov.wakeup_ctrl_cg_wrap[i]) begin + cov.wakeup_ctrl_cg_wrap[i].sample(cfg.pwrmgr_vif.wakeup_en[i], + cfg.pwrmgr_vif.wakeup_capture_en, + cfg.pwrmgr_vif.wakeups_i[i]); + end + end + end + endtask + + task wakeup_intr_coverage_collector(); + forever + @(posedge (cfg.pwrmgr_vif.fast_state == pwrmgr_pkg::FastPwrStateRomCheckDone)) begin + if (cfg.en_cov) begin + foreach (cov.wakeup_intr_cg_wrap[i]) begin + cov.wakeup_intr_cg_wrap[i].sample( + cfg.pwrmgr_vif.wakeup_status[i], cfg.pwrmgr_vif.intr_enable, + cfg.pwrmgr_vif.intr_status, cfg.pwrmgr_vif.intr_wakeup); + end + end + end + endtask + + task low_power_coverage_collector(); + forever + @(posedge cfg.pwrmgr_vif.pwr_rst_req.reset_cause == pwrmgr_pkg::LowPwrEntry) begin + if (cfg.en_cov) begin + // At this point pwrmgr is asleep. + cov.control_cg.sample(control_enables, 1'b1); + end + end + endtask + + local task sample_reset_coverage(bit sleep); + cov.hw_reset_0_cg.sample(cfg.pwrmgr_vif.rstreqs_i[0], cfg.pwrmgr_vif.reset_en[0], sleep); + cov.hw_reset_1_cg.sample(cfg.pwrmgr_vif.rstreqs_i[1], cfg.pwrmgr_vif.reset_en[1], sleep); + cov.rstmgr_sw_reset_cg.sample(cfg.pwrmgr_vif.sw_rst_req_i == prim_mubi_pkg::MuBi4True); + cov.main_power_reset_cg.sample( + cfg.pwrmgr_vif.pwr_rst_req.rstreqs[pwrmgr_reg_pkg::ResetMainPwrIdx], sleep); + cov.esc_reset_cg.sample(cfg.pwrmgr_vif.pwr_rst_req.rstreqs[pwrmgr_reg_pkg::ResetEscIdx], sleep); + `uvm_info(`gfn, $sformatf( + { + "reset_cg sample with hw_resets=%b, hw_resets_en=%b, ", + "esc_rst=%b, main_pwr_rst=%b, sw_rst=%b, sleep=%b" + }, + cfg.pwrmgr_vif.rstreqs_i, + cfg.pwrmgr_vif.reset_en, + cfg.pwrmgr_vif.pwr_rst_req.rstreqs[pwrmgr_reg_pkg::ResetEscIdx], + cfg.pwrmgr_vif.pwr_rst_req.rstreqs[pwrmgr_reg_pkg::ResetMainPwrIdx], + cfg.pwrmgr_vif.sw_rst_req_i == prim_mubi_pkg::MuBi4True, + sleep + ), UVM_MEDIUM) + endtask + + task reset_coverage_collector(); + fork + forever + @(posedge cfg.pwrmgr_vif.pwr_rst_req.reset_cause == pwrmgr_pkg::HwReq) begin + if (cfg.en_cov) begin + sample_reset_coverage(.sleep(1'b0)); + end + end + forever + @(posedge cfg.pwrmgr_vif.slow_state == pwrmgr_pkg::SlowPwrStateLowPower) begin + if (cfg.en_cov) begin + sample_reset_coverage(.sleep(1'b1)); + end + end + join_none + endtask + + task rom_coverage_collector(); + forever + @(cfg.pwrmgr_vif.rom_ctrl or cfg.pwrmgr_vif.lc_hw_debug_en or cfg.pwrmgr_vif.lc_dft_en) begin + if (cfg.en_cov) begin + cov.rom_active_blockers_cg.sample(cfg.pwrmgr_vif.rom_ctrl.done, + cfg.pwrmgr_vif.rom_ctrl.good, cfg.pwrmgr_vif.lc_dft_en, + cfg.pwrmgr_vif.lc_hw_debug_en); + end + end + endtask + + virtual task process_tl_access(tl_seq_item item, tl_channels_e channel, string ral_name); + uvm_reg csr; + bit do_read_check = ~(cfg.disable_csr_rd_chk); + bit skip_intr_chk = cfg.invalid_st_test; + bit write = item.is_write(); + uvm_reg_addr_t csr_addr = cfg.ral_models[ral_name].get_word_aligned_addr(item.a_addr); + + bit addr_phase_read = (!write && channel == AddrChannel); + bit addr_phase_write = (write && channel == AddrChannel); + bit data_phase_read = (!write && channel == DataChannel); + bit data_phase_write = (write && channel == DataChannel); + + // if access was to a valid csr, get the csr handle + if (csr_addr inside {cfg.ral_models[ral_name].csr_addrs}) begin + csr = cfg.ral_models[ral_name].default_map.get_reg_by_offset(csr_addr); + `DV_CHECK_NE_FATAL(csr, null) + end else begin + `uvm_fatal(`gfn, $sformatf("Access unexpected addr 0x%0h", csr_addr)) + end + + // if incoming access is a write to a valid csr, then make updates right away + if (addr_phase_write) begin + `uvm_info(`gfn, $sformatf("Writing 0x%x to %s", item.a_data, csr.get_full_name()), UVM_MEDIUM) + void'(csr.predict(.value(item.a_data), .kind(UVM_PREDICT_WRITE), .be(item.a_mask))); + end + + // process the csr req + // for write, update local variable and fifo at address phase + // for read, update predication at address phase and compare at data phase + case (csr.get_name()) + // add individual case item for each csr + "intr_state": begin + if (skip_intr_chk) return; + if (data_phase_write) begin + exp_intr &= ~item.a_data; + end else if (data_phase_read) begin + bit [TL_DW-1:0] intr_en = ral.intr_enable.get_mirrored_value(); + foreach (exp_intr[i]) begin + if (cfg.en_cov) begin + cov.intr_cg.sample(i, intr_en[i], exp_intr[i]); + cov.intr_pins_cg.sample(i, cfg.intr_vif.pins[i]); + end + `DV_CHECK_EQ(item.d_data[i], exp_intr[i], $sformatf("Interrupt bit %0d", i)); + `DV_CHECK_CASE_EQ(cfg.intr_vif.pins[i], (intr_en[i] & exp_intr[i]), $sformatf( + "Interrupt_pin bit %0d", i)); + end + end + // rw1c: write 1 clears, write 0 is no-op. + do_read_check = 1'b0; + end + "intr_enable", "alert_test": begin + // Do nothing + end + "intr_test": begin + if (data_phase_write) begin + bit [TL_DW-1:0] intr_en = ral.intr_enable.get_mirrored_value(); + exp_intr |= item.a_data; + if (cfg.en_cov) begin + foreach (exp_intr[i]) begin + cov.intr_test_cg.sample(i, item.a_data[i], intr_en[i], exp_intr[i]); + end + end + end + // Write-only, so it can't be read. + do_read_check = 1'b0; + end + "ctrl_cfg_regwen": begin + // Read-only. Hardware clears this bit when going to low power mode, + // and sets it in active mode. + do_read_check = 1'b0; + end + "control": begin + // Only some bits can be checked on reads. Bit 0 is cleared by hardware + // on low power transition or when registering a valid reset. + if (data_phase_write) begin + low_power_hint = get_field_val(ral.control.low_power_hint, item.a_data); + control_enables = '{ + core_clk_en: get_field_val(ral.control.core_clk_en, item.a_data), + io_clk_en: get_field_val(ral.control.io_clk_en, item.a_data), + usb_clk_en_lp: get_field_val(ral.control.usb_clk_en_lp, item.a_data), + usb_clk_en_active: get_field_val(ral.control.usb_clk_en_active, item.a_data), + main_pd_n: get_field_val(ral.control.main_pd_n, item.a_data) + }; + `uvm_info(`gfn, $sformatf("Writing low power hint=%b", low_power_hint), UVM_MEDIUM) + `uvm_info(`gfn, $sformatf("Writing control_enables=%p", control_enables), UVM_MEDIUM) + if (cfg.en_cov) begin + // At this point the processor is not asleep. + cov.control_cg.sample(control_enables, 1'b0); + end + end + end + "cfg_cdc_sync": begin + // rw1c: When written to 1 this bit self-clears when the slow clock domain + // syncs. + do_read_check = 1'b0; + end + "wakeup_en_regwen": begin + end + "wakeup_en": begin + end + "wake_status": begin + // Read-only. + do_read_check = 1'b0; + end + "reset_en_regwen": begin + // rw0c, so writing a 1 is a no-op. + end + "reset_en": begin + if (data_phase_write) begin + cfg.pwrmgr_vif.update_reset_en(item.a_data); + end + end + "reset_status": begin + // Read-only. + do_read_check = 1'b0; + end + "escalate_reset_status": begin + // Read-only. + do_read_check = 1'b0; + end + "wake_info_capture_dis": begin + end + "wake_info": begin + // rw1c: write 1 clears, write 0 is no-op. + do_read_check = 1'b0; + end + default: begin + `uvm_fatal(`gfn, $sformatf("invalid csr: %0s", csr.get_full_name())) + end + endcase + + // On reads, if do_read_check, is set, then check mirrored_value against item.d_data + if (data_phase_read) begin + `uvm_info(`gfn, $sformatf("Reading 0x%x from %s", item.d_data, csr.get_full_name()), UVM_LOW) + if (do_read_check) begin + `DV_CHECK_EQ(csr.get_mirrored_value(), item.d_data, $sformatf( + "reg name: %0s", csr.get_full_name())) + end + void'(csr.predict(.value(item.d_data), .kind(UVM_PREDICT_READ))); + end + endtask + + virtual function void reset(string kind = "HARD"); + super.reset(kind); + // reset local fifos queues and variables + endfunction + + function void check_phase(uvm_phase phase); + super.check_phase(phase); + // post test checks - ensure that all local fifos and queues are empty + endfunction + +endclass diff --git a/src/pwrmgr/dv/env/pwrmgr_virtual_sequencer.sv b/src/pwrmgr/dv/env/pwrmgr_virtual_sequencer.sv new file mode 100644 index 0000000..ec7f602 --- /dev/null +++ b/src/pwrmgr/dv/env/pwrmgr_virtual_sequencer.sv @@ -0,0 +1,14 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class pwrmgr_virtual_sequencer extends cip_base_virtual_sequencer #( + .CFG_T(pwrmgr_env_cfg), + .COV_T(pwrmgr_env_cov) +); + `uvm_component_utils(pwrmgr_virtual_sequencer) + + + `uvm_component_new + +endclass diff --git a/src/pwrmgr/dv/env/seq_lib/pwrmgr_aborted_low_power_vseq.sv b/src/pwrmgr/dv/env/seq_lib/pwrmgr_aborted_low_power_vseq.sv new file mode 100644 index 0000000..4c8bb62 --- /dev/null +++ b/src/pwrmgr/dv/env/seq_lib/pwrmgr_aborted_low_power_vseq.sv @@ -0,0 +1,126 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// The aborted low power test causes low power transitions to abort for CPU interrupts and nvms not +// idle. It randomly enables wakeups, info capture, and interrupts, and sends wakeups at random +// times, and causes a test failure if they are not aborted. +class pwrmgr_aborted_low_power_vseq extends pwrmgr_base_vseq; + `uvm_object_utils(pwrmgr_aborted_low_power_vseq) + + `uvm_object_new + + // If set causes an abort because the CPU gets an interrupt, which shows up as + // pwr_cpu.core_sleeping being low when the fast FSM is in FastPwrStateFallThrough. + rand bit cpu_interrupt; + + constraint cpu_interrupt_c { + cpu_interrupt dist { + 1 := 2, + 0 := 6 + }; + } + + rand bit flash_idle; + rand bit lc_idle; + rand bit otp_idle; + + constraint idle_c { + solve cpu_interrupt before flash_idle, lc_idle, otp_idle; + if (!cpu_interrupt) {(flash_idle && lc_idle && otp_idle) == 1'b0;} + } + + constraint wakeups_c {wakeups != 0;} + + constraint wakeup_en_c { + solve wakeups before wakeups_en; + |(wakeups_en & wakeups) == 1'b1; + } + + // Make sure wakeup capture is enabled to check the abort happened. + constraint enable_wakeup_capture_c {disable_wakeup_capture == 1'b0;} + + task body(); + logic [TL_DW-1:0] value; + wakeups_t enabled_wakeups; + wait_for_fast_fsm(FastFsmActive); + + check_wake_status('0); + set_nvms_idle(); + for (int i = 0; i < num_trans; ++i) begin + `uvm_info(`gfn, "Starting new round", UVM_MEDIUM) + `DV_CHECK_RANDOMIZE_FATAL(this) + setup_interrupt(.enable(en_intr)); + // Enable wakeups. + enabled_wakeups = wakeups_en & wakeups; + `DV_CHECK(enabled_wakeups, $sformatf( + "Some wakeup must be enabled: wkups=%b, wkup_en=%b", wakeups, wakeups_en)) + `uvm_info(`gfn, $sformatf( + "Enabled wakeups=0x%x (wkups=%x wkup_en=%x)", enabled_wakeups, wakeups, wakeups_en + ), UVM_MEDIUM) + csr_wr(.ptr(ral.wakeup_en[0]), .value(wakeups_en)); + + `uvm_info(`gfn, $sformatf("%0sabling wakeup capture", disable_wakeup_capture ? "Dis" : "En"), + UVM_MEDIUM) + csr_wr(.ptr(ral.wake_info_capture_dis), .value(disable_wakeup_capture)); + low_power_hint = 1'b1; + + // Put CPU to sleep even before the control registers are fully written to avoid + // unexpected failures to abort due to delicate timing. + cfg.pwrmgr_vif.update_cpu_sleeping(1'b1); + + fork + begin + update_control_csr(); + `uvm_info(`gfn, $sformatf("After update_control_csr exp_intr=%b", exp_intr), UVM_MEDIUM) + end + begin + // Prepare for an abort ahead of time. + `DV_WAIT(cfg.pwrmgr_vif.fast_state != pwrmgr_pkg::FastPwrStateActive) + // Wait one more cycle for update_control_csr called above to predict the interrupt + // based on the value of cpu_sleeping right after the transition out of active state. + // There is enough time for this since it takes time to disable the clocks. + cfg.clk_rst_vif.wait_clks(1); + if (cpu_interrupt) begin + `uvm_info(`gfn, "Expecting a fall through (0x40)", UVM_MEDIUM) + cfg.pwrmgr_vif.update_cpu_sleeping(1'b0); + end else begin + `uvm_info(`gfn, $sformatf( + "Expecting an abort (0x80): fi=%b, li=%b, oi=%b", + flash_idle, + lc_idle, + otp_idle + ), UVM_MEDIUM) + set_nvms_idle(flash_idle, lc_idle, otp_idle); + end + end + join + wait_for_fast_fsm(FastFsmActive); + + `uvm_info(`gfn, "Back from sleep attempt", UVM_MEDIUM) + @cfg.clk_rst_vif.cb; + + // No wakeups, but check abort and fall_through. + fork + begin + fast_check_reset_status(0); + end + begin + fast_check_wake_info(.reasons('0), .fall_through(cpu_interrupt), .abort(~cpu_interrupt)); + end + join + + clear_wake_info(); + + // And check interrupt is set. + check_and_clear_interrupt(.expected(1'b1)); + + // Get ready for another round. + cfg.pwrmgr_vif.update_cpu_sleeping(1'b0); + set_nvms_idle(); + cfg.slow_clk_rst_vif.wait_clks(4); + end + `uvm_info(`gfn, "Test done", UVM_MEDIUM) + endtask + +endclass : pwrmgr_aborted_low_power_vseq diff --git a/src/pwrmgr/dv/env/seq_lib/pwrmgr_base_vseq.sv b/src/pwrmgr/dv/env/seq_lib/pwrmgr_base_vseq.sv new file mode 100644 index 0000000..ad99b59 --- /dev/null +++ b/src/pwrmgr/dv/env/seq_lib/pwrmgr_base_vseq.sv @@ -0,0 +1,835 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class pwrmgr_base_vseq extends cip_base_vseq #( + .RAL_T (pwrmgr_reg_block), + .CFG_T (pwrmgr_env_cfg), + .COV_T (pwrmgr_env_cov), + .VIRTUAL_SEQUENCER_T(pwrmgr_virtual_sequencer) +); + `uvm_object_utils(pwrmgr_base_vseq) + + `uvm_object_new + + localparam int ActiveTimeoutInNanoSeconds = 10_000; + localparam int PropagationToSlowTimeoutInNanoSeconds = 15_000; + localparam int FetchEnTimeoutNs = 40_000; + + localparam int MaxCyclesBeforeEnable = 12; + + typedef enum int { + FastFsmActive, + FastFsmInactive + } fast_fsm_activity_e; + + // Random wakeups and resets. + rand wakeups_t wakeups; + rand wakeups_t wakeups_en; + rand resets_t resets; + rand resets_t resets_en; + rand bit power_glitch_reset; + rand bit escalation_reset; + rand bit ndm_reset; + + rand bit en_intr; + + constraint resets_en_c { + solve resets, power_glitch_reset, escalation_reset, ndm_reset before resets_en; + |{resets_en & resets, power_glitch_reset, escalation_reset, ndm_reset} == 1'b1; + } + + rand bit disable_wakeup_capture; + + // Random control enables. + rand control_enables_t control_enables; + + // Random delays. + rand int cycles_before_clks_ok; + rand int cycles_between_clks_ok; + rand int cycles_before_io_status; + rand int cycles_before_main_status; + rand int cycles_before_usb_status; + rand int cycles_before_rst_lc_src; + rand int cycles_before_rst_sys_src; + rand int cycles_before_otp_done; + rand int cycles_before_lc_done; + rand int cycles_before_wakeup; + rand int cycles_before_reset; + + // Slow responder delays. + rand int cycles_before_core_clk_en; + rand int cycles_before_io_clk_en; + rand int cycles_before_usb_clk_en; + rand int cycles_before_main_pok; + + // This tracks the local objection count from these responders. We do not use UVM + // objections because uvm_objection::wait_for(UVM_ALL_DROPPED, this) seems to wait + // for all objections to be dropped, not just those raised by this. + local int fast_objection_count = 0; + local int slow_objection_count = 0; + + constraint cycles_before_clks_ok_c {cycles_before_clks_ok inside {[3 : 10]};} + constraint cycles_between_clks_ok_c {cycles_between_clks_ok inside {[3 : 10]};} + constraint cycles_before_io_status_c {cycles_before_io_status inside {[0 : 4]};} + constraint cycles_before_main_status_c {cycles_before_main_status inside {[0 : 4]};} + constraint cycles_before_usb_status_c {cycles_before_usb_status inside {[0 : 4]};} + constraint cycles_before_rst_lc_src_base_c {cycles_before_rst_lc_src inside {[0 : 4]};} + constraint cycles_before_rst_sys_src_base_c {cycles_before_rst_sys_src inside {[0 : 4]};} + constraint cycles_before_otp_done_base_c {cycles_before_otp_done inside {[0 : 4]};} + constraint cycles_before_lc_done_base_c {cycles_before_lc_done inside {[0 : 4]};} + constraint cycles_before_wakeup_c {cycles_before_wakeup inside {[2 : 6]};} + constraint cycles_before_reset_c {cycles_before_reset inside {[2 : 6]};} + constraint cycles_before_core_clk_en_c { + cycles_before_core_clk_en inside {[1 : MaxCyclesBeforeEnable]}; + } + constraint cycles_before_io_clk_en_c { + cycles_before_io_clk_en inside {[1 : MaxCyclesBeforeEnable - 2]}; + } + constraint cycles_before_usb_clk_en_c { + cycles_before_usb_clk_en inside {[1 : MaxCyclesBeforeEnable]}; + } + constraint cycles_before_main_pok_c {cycles_before_main_pok inside {[2 : MaxCyclesBeforeEnable]};} + + // This is used to trigger a software reset, as per rstmgr's `reset_req` CSR. + prim_mubi_pkg::mubi4_t sw_rst_from_rstmgr = prim_mubi_pkg::MuBi4False; + + bit do_pwrmgr_init = 1'b1; + // This static variable is incremented in each pre_start and decremented in each post_start. + // It is used to start and stop the responders when the parent sequence starts and ends. + local static int sequence_depth = 0; + pwrmgr_mubi_e mubi_mode; + + // This stops randomizing cycles counts that select from a pipeline, since + // changes can lead to missing or unexpected transitions. + task stop_randomizing_cycles(); + cycles_before_core_clk_en.rand_mode(0); + cycles_before_io_clk_en.rand_mode(0); + cycles_before_usb_clk_en.rand_mode(0); + cycles_before_main_pok.rand_mode(0); + endtask + + // Disable exclusions for CONTROL.USB_CLK_EN_ACTIVE and RESET_EN: they are meant for full-chip only. + function void disable_unnecessary_exclusions(); + csr_excl_item csr_excl = ral.get_excl_item(); + `uvm_info(`gfn, "Dealing with exclusions", UVM_MEDIUM) + csr_excl.enable_excl(.obj("pwrmgr_reg_block.control"), .enable(1'b0)); + csr_excl.enable_excl(.obj("pwrmgr_reg_block.reset_en"), .enable(1'b0)); + csr_excl.print_exclusions(UVM_MEDIUM); + endfunction + + virtual task pre_start(); + cfg.pwrmgr_vif.lc_hw_debug_en = lc_ctrl_pkg::Off; + cfg.pwrmgr_vif.lc_dft_en = lc_ctrl_pkg::Off; + mubi_mode = PwrmgrMubiNone; + `DV_GET_ENUM_PLUSARG(pwrmgr_mubi_e, mubi_mode, pwrmgr_mubi_mode) + `uvm_info(`gfn, $sformatf("pwrmgr mubi mode : %s", mubi_mode.name()), UVM_MEDIUM) + + if (do_pwrmgr_init) pwrmgr_init(); + disable_unnecessary_exclusions(); + cfg.slow_clk_rst_vif.wait_for_reset(.wait_negedge(0)); + stop_randomizing_cycles(); + fork + // Deactivate rst_main_n to make sure the slow fsm won't be confused into thinking + // a power glitch occurred, and wait some cycles so testing doesn't start until any + // side-effects are cleared. This confusion can arise if a sequence with random resets + // gets reset while sending a power glitch. + begin + cfg.pwrmgr_vif.rst_main_n = 1'b1; + cfg.slow_clk_rst_vif.wait_clks(7); + end + begin + if (sequence_depth == 0) begin + `uvm_info(`gfn, "Starting responders", UVM_MEDIUM) + slow_responder(); + fast_responder(); + end + ++sequence_depth; + super.pre_start(); + end + join + endtask : pre_start + + task post_apply_reset(string reset_kind = "HARD"); + super.post_apply_reset(reset_kind); + if (reset_kind == "HARD") begin + // Undo any pending resets. + cfg.pwrmgr_vif.rst_main_n = 1'b1; + cfg.pwrmgr_vif.update_resets(0); + end + + `uvm_info(`gfn, "waiting for fast active after applying reset", UVM_MEDIUM) + + // There is tb lock up case + // when reset come while rom_ctrl = {false, false}. + // So we need rom_ctrl driver runs in parallel with + // wait_for_fast_fsm(FastFsmActive) + fork + wait_for_fast_fsm(FastFsmActive); + init_rom_response(); + join + // And drive the cpu not sleeping. + cfg.pwrmgr_vif.update_cpu_sleeping(1'b0); + endtask + + task post_start(); + super.post_start(); + --sequence_depth; + if (sequence_depth == 0) begin + `uvm_info(`gfn, $sformatf( + "Waiting for all objections done with fast=%0d, slow=%0d", + fast_objection_count, + slow_objection_count + ), UVM_MEDIUM) + `DV_WAIT(fast_objection_count == 0 && slow_objection_count == 0) + `uvm_info(`gfn, "all local objections are done", UVM_LOW) + control_assertions(0); + `uvm_info(`gfn, "Stopping responders", UVM_MEDIUM) + disable slow_responder; + disable fast_responder; + end + endtask + + virtual task dut_init(string reset_kind = "HARD"); + super.dut_init(); + endtask + + virtual task dut_shutdown(); + // There are no known checks to perform here. + endtask + + virtual task apply_reset(string kind = "HARD"); + `uvm_info(`gfn, $sformatf("At apply_reset kind='%0s'", kind), UVM_MEDIUM) + fork + super.apply_reset(kind); + if (kind == "HARD") begin + // A short slow clock reset should suffice. + cfg.slow_clk_rst_vif.apply_reset(.pre_reset_dly_clks(0), .reset_width_clks(5)); + end + cfg.esc_clk_rst_vif.apply_reset(); + cfg.lc_clk_rst_vif.apply_reset(); + // Escalation resets are cleared when reset goes active. + clear_escalation_reset(); + clear_ndm_reset(); + join + // And wait until the responders settle with all okay from the AST. + `DV_WAIT( + cfg.pwrmgr_vif.pwr_ast_rsp.main_pok && + cfg.pwrmgr_vif.pwr_ast_rsp.core_clk_val && + cfg.pwrmgr_vif.pwr_ast_rsp.io_clk_val) + `uvm_info(`gfn, $sformatf("Out of apply_reset kind='%0s'", kind), UVM_MEDIUM) + endtask + + virtual task apply_resets_concurrently(int reset_duration_ps = 0); + cfg.slow_clk_rst_vif.drive_rst_pin(0); + cfg.esc_clk_rst_vif.drive_rst_pin(0); + cfg.lc_clk_rst_vif.drive_rst_pin(0); + super.apply_resets_concurrently(cfg.slow_clk_rst_vif.clk_period_ps); + cfg.esc_clk_rst_vif.drive_rst_pin(1); + cfg.lc_clk_rst_vif.drive_rst_pin(1); + cfg.slow_clk_rst_vif.drive_rst_pin(1); + endtask + + // setup basic pwrmgr features + virtual task pwrmgr_init(); + // The fast clock frequency is set by ral. + // The real slow clock rate is 200kHz, but that slows testing down. + // Increasing its frequency improves DV efficiency without compromising quality. + cfg.slow_clk_rst_vif.set_freq_mhz(7); + `uvm_info(`gfn, $sformatf( + "slow clock freq=%fMHz, period=%0dns", + cfg.slow_clk_rst_vif.clk_freq_mhz, + cfg.slow_clk_rst_vif.clk_period_ps + ), UVM_MEDIUM) + cfg.esc_clk_rst_vif.set_freq_mhz(cfg.clk_rst_vif.clk_freq_mhz); + cfg.lc_clk_rst_vif.set_freq_mhz(cfg.clk_rst_vif.clk_freq_mhz); + set_ndmreset_req('0); + control_assertions(0); + endtask + + virtual task setup_interrupt(bit enable); + csr_wr(.ptr(ral.intr_enable.wakeup), .value(enable)); + `uvm_info(`gfn, $sformatf("Wakeup interrupt is %0sabled", enable ? "en" : "dis"), UVM_MEDIUM) + endtask + + // May check intr_state.wakeup CSR against expected, and regardless, it checks that the + // interrupt output matches intr_state && intr_enable. The first check is disabled if + // check_expected is off, which is used when a reset and an interrupt come in close + // temporal proximity. + virtual task check_and_clear_interrupt(bit expected, bit check_expected = 1'b1); + bit enable; + `uvm_info(`gfn, "Checking and clearing interrupt", UVM_MEDIUM) + if (check_expected) begin + csr_rd_check(.ptr(ral.intr_state.wakeup), .compare_value(expected), + .err_msg("interrupt mismatch")); + end else begin + csr_rd(.ptr(ral.intr_state.wakeup), .value(expected)); + end + csr_rd(.ptr(ral.intr_enable.wakeup), .value(enable)); + `DV_CHECK_EQ(cfg.pwrmgr_vif.intr_wakeup, expected && enable) + csr_wr(.ptr(ral.intr_state.wakeup), .value(1'b1)); + endtask + + local function void raise_fast_objection(string label); + ++fast_objection_count; + `uvm_info(`gfn, $sformatf("Raising fast objection to %0d for %0s", fast_objection_count, label), + UVM_HIGH) + endfunction + + local function void drop_fast_objection(string label); + --fast_objection_count; + `uvm_info(`gfn, $sformatf("Dropping fast objection to %0d for %0s", fast_objection_count, label + ), UVM_HIGH) + endfunction + + local function void raise_slow_objection(string label); + ++slow_objection_count; + `uvm_info(`gfn, $sformatf("Raising slow objection to %0d for %0s", slow_objection_count, label), + UVM_MEDIUM) + endfunction + + local function void drop_slow_objection(string label); + --slow_objection_count; + `uvm_info(`gfn, $sformatf("Dropping slow objection to %0d for %0s", slow_objection_count, label + ), UVM_MEDIUM) + endfunction + + virtual function void set_ndmreset_req(logic value); + cfg.pwrmgr_vif.cpu_i.ndmreset_req = value; + endfunction + + // Generates expected responses for the slow fsm. + // - Completes the clock handshake with the ast: when a clk_en output changes, after a few + // cycles the ast is expected to set the corresponding clk_val input to the same value. + // - It is possible changes occur in fast succession, so the side-effect is pipelined. + // Uses macros because VCS flags an error for assignments to automatic variables, + // even if the variable is a ref to an interface variable. + + `define SLOW_DETECT(rsp_name_, req_) \ + forever \ + @req_ begin \ + raise_slow_objection(rsp_name_); \ + `uvm_info(`gfn, $sformatf( \ + "slow_responder: Will drive %0s to %b", rsp_name_, req_), UVM_MEDIUM) \ + end + + `define SLOW_SHIFT_SR(req_, rsp_sr_) \ + forever \ + @cfg.slow_clk_rst_vif.cb begin \ + rsp_sr_ = {rsp_sr_[MaxCyclesBeforeEnable-1:0], req_}; \ + end + + `define SLOW_ASSIGN(rsp_name_, cycles_, rsp_sr_, rsp_) \ + forever \ + @(rsp_sr_[cycles_]) begin \ + `uvm_info(`gfn, $sformatf( \ + "slow_responder: Driving %0s to %b after %0d AON cycles.", \ + rsp_name_, \ + rsp_sr_[cycles_], \ + cycles_ \ + ), UVM_MEDIUM) \ + rsp_ <= rsp_sr_[cycles_]; \ + drop_slow_objection(rsp_name_); \ + end + + task slow_responder(); + logic [MaxCyclesBeforeEnable:0] core_clk_val_sr; + logic [MaxCyclesBeforeEnable:0] io_clk_val_sr; + logic [MaxCyclesBeforeEnable:0] usb_clk_val_sr; + logic [MaxCyclesBeforeEnable:0] main_pd_val_sr; + fork + `SLOW_DETECT("core_clk_val", cfg.pwrmgr_vif.slow_cb.pwr_ast_req.core_clk_en) + `SLOW_SHIFT_SR(cfg.pwrmgr_vif.slow_cb.pwr_ast_req.core_clk_en, core_clk_val_sr) + `SLOW_ASSIGN("core_clk_val", cycles_before_core_clk_en, core_clk_val_sr, + cfg.pwrmgr_vif.slow_cb.pwr_ast_rsp.core_clk_val) + + `SLOW_DETECT("io_clk_val", cfg.pwrmgr_vif.slow_cb.pwr_ast_req.io_clk_en) + `SLOW_SHIFT_SR(cfg.pwrmgr_vif.slow_cb.pwr_ast_req.io_clk_en, io_clk_val_sr) + // Notice this splits updates due to io_clk_en in two processes: with a single process + // and a wait inside a quick sequence of changes would cause skipping some update, per + // SV scheduling semantics. + forever + @(io_clk_val_sr[cycles_before_io_clk_en]) begin + logic new_value = io_clk_val_sr[cycles_before_io_clk_en]; + `uvm_info(`gfn, $sformatf( + "slow_responder: Driving %0s to %b after %0d AON cycles.", + "io_clk_val", + new_value, + cycles_before_io_clk_en + ), UVM_MEDIUM) + if (new_value == 1) begin + cfg.clk_rst_vif.start_clk(); + cfg.lc_clk_rst_vif.start_clk(); + cfg.esc_clk_rst_vif.start_clk(); + end else begin + cfg.clk_rst_vif.stop_clk(); + cfg.lc_clk_rst_vif.stop_clk(); + cfg.esc_clk_rst_vif.stop_clk(); + end + end + forever + @(io_clk_val_sr[cycles_before_io_clk_en+2]) begin + logic new_value = io_clk_val_sr[cycles_before_io_clk_en+2]; + cfg.pwrmgr_vif.slow_cb.pwr_ast_rsp.io_clk_val <= new_value; + drop_slow_objection("io_clk_val"); + end + + `SLOW_DETECT("usb_clk_val", cfg.pwrmgr_vif.slow_cb.pwr_ast_req.usb_clk_en) + `SLOW_SHIFT_SR(cfg.pwrmgr_vif.slow_cb.pwr_ast_req.usb_clk_en, usb_clk_val_sr) + `SLOW_ASSIGN("usb_clk_val", cycles_before_usb_clk_en, usb_clk_val_sr, + cfg.pwrmgr_vif.slow_cb.pwr_ast_rsp.usb_clk_val) + + `SLOW_DETECT("main_pok", cfg.pwrmgr_vif.slow_cb.pwr_ast_req.main_pd_n) + `SLOW_SHIFT_SR(cfg.pwrmgr_vif.slow_cb.pwr_ast_req.main_pd_n, main_pd_val_sr) + `SLOW_ASSIGN("main_pok", cycles_before_main_pok, main_pd_val_sr, + cfg.pwrmgr_vif.slow_cb.pwr_ast_rsp.main_pok) + join_none + endtask : slow_responder + `undef SLOW_DETECT + `undef SLOW_SHIFT_SR + `undef SLOW_ASSIGN + + // Generates expected responses for the fast fsm. + // - Completes the reset handshake with the rstmgr for lc and sys resets: soon after a + // reset is requested the corresponding active low reset src must go low. + // - Completes the handshake with the clkmgr for io, main, and usb clocks: + // each status input needs to track the corresponding ip_clk_en output. + // - Completes handshake with lc and otp: *_done needs to track *_init. + // Macros for the same reason as the slow responder. + + `define FAST_RESPONSE_ACTION(rsp_name, rsp, req, cycles) \ + `uvm_info(`gfn, $sformatf( \ + "fast_responder %s: Will drive %0s to %b in %0d fast clock cycles", \ + rsp_name, rsp_name, req, cycles), UVM_HIGH) \ + cfg.clk_rst_vif.wait_clks(cycles); \ + rsp <= req; \ + `uvm_info(`gfn, $sformatf("fast_responder %s: Driving %0s to %b", rsp_name, rsp_name, req), UVM_HIGH) \ + + + task fast_responder(); + fork + forever + @cfg.pwrmgr_vif.fast_cb.pwr_rst_req.rst_lc_req begin + `uvm_info(`gfn, $sformatf( + "fast responder got rst_lc_req change to 0x%x", + cfg.pwrmgr_vif.fast_cb.pwr_rst_req.rst_lc_req + ), UVM_HIGH) + raise_fast_objection("rst_lc_src_n"); + `FAST_RESPONSE_ACTION("rst_lc_src_n", cfg.pwrmgr_vif.fast_cb.pwr_rst_rsp.rst_lc_src_n, + ~cfg.pwrmgr_vif.fast_cb.pwr_rst_req.rst_lc_req, + cycles_before_rst_lc_src) + if (cfg.pwrmgr_vif.fast_cb.pwr_rst_req.rst_lc_req[1] == 1'b0) begin + // Wait for the rst_lc_src_n[1] input to go inactive. + if (cfg.pwrmgr_vif.pwr_rst_rsp.rst_lc_src_n[1] != 1'b1) + @(posedge cfg.pwrmgr_vif.pwr_rst_rsp.rst_lc_src_n[1]); + cfg.esc_clk_rst_vif.drive_rst_pin(1); + cfg.lc_clk_rst_vif.drive_rst_pin(1); + end else begin + // And clear all reset requests when rst_lc_src_n[1] goes active, because when + // peripherals are reset they should drop their reset requests. + if (cfg.pwrmgr_vif.pwr_rst_rsp.rst_lc_src_n[1] != 1'b0) + @(negedge cfg.pwrmgr_vif.pwr_rst_rsp.rst_lc_src_n[1]); + cfg.esc_clk_rst_vif.drive_rst_pin(0); + cfg.lc_clk_rst_vif.drive_rst_pin(0); + clear_escalation_reset(); + clear_ndm_reset(); + cfg.pwrmgr_vif.update_resets('0); + cfg.pwrmgr_vif.update_sw_rst_req(prim_mubi_pkg::MuBi4False); + `uvm_info(`gfn, "Clearing resets", UVM_MEDIUM) + end + drop_fast_objection("rst_lc_src_n"); + `uvm_info(`gfn, "fast responder done with rst_lc_req change", UVM_HIGH) + end + forever + @cfg.pwrmgr_vif.fast_cb.pwr_rst_req.rst_sys_req begin + raise_fast_objection("rst_sys_src_n"); + `FAST_RESPONSE_ACTION("rst_sys_src_n", cfg.pwrmgr_vif.fast_cb.pwr_rst_rsp.rst_sys_src_n, + ~cfg.pwrmgr_vif.fast_cb.pwr_rst_req.rst_sys_req, + cycles_before_rst_sys_src) + drop_fast_objection("rst_sys_src_n"); + end + + forever + @cfg.pwrmgr_vif.fast_cb.pwr_clk_req.io_ip_clk_en begin + logic new_value = cfg.pwrmgr_vif.fast_cb.pwr_clk_req.io_ip_clk_en; + raise_fast_objection("io_status"); + `uvm_info(`gfn, $sformatf( + "fast_responder: Will drive %0s to %b in %0d fast clock cycles", + "io_status", + new_value, + cycles_before_io_status + ), UVM_HIGH) + cfg.clk_rst_vif.wait_clks(cycles_before_io_status); + if (new_value) cfg.esc_clk_rst_vif.start_clk(); + else cfg.esc_clk_rst_vif.stop_clk(); + cfg.clk_rst_vif.wait_clks(2); + cfg.pwrmgr_vif.fast_cb.pwr_clk_rsp.io_status <= new_value; + `uvm_info(`gfn, $sformatf( + "fast_responder: Driving %0s to %b", + "io_status", + cfg.pwrmgr_vif.fast_cb.pwr_clk_req.io_ip_clk_en + ), UVM_HIGH) + drop_fast_objection("io_status"); + end + + forever + @cfg.pwrmgr_vif.fast_cb.pwr_clk_req.main_ip_clk_en begin + raise_fast_objection("main_status"); + `FAST_RESPONSE_ACTION("main_status", cfg.pwrmgr_vif.fast_cb.pwr_clk_rsp.main_status, + cfg.pwrmgr_vif.fast_cb.pwr_clk_req.main_ip_clk_en, + cycles_before_main_status) + drop_fast_objection("main_status"); + end + forever + @cfg.pwrmgr_vif.fast_cb.pwr_clk_req.usb_ip_clk_en begin + raise_fast_objection("usb_status"); + `FAST_RESPONSE_ACTION("usb_status", cfg.pwrmgr_vif.fast_cb.pwr_clk_rsp.usb_status, + cfg.pwrmgr_vif.fast_cb.pwr_clk_req.usb_ip_clk_en, + cycles_before_usb_status) + drop_fast_objection("usb_status"); + end + forever + @cfg.pwrmgr_vif.fast_cb.pwr_lc_req.lc_init begin + raise_fast_objection("lc_done"); + `FAST_RESPONSE_ACTION("lc_done", cfg.pwrmgr_vif.fast_cb.pwr_lc_rsp.lc_done, + cfg.pwrmgr_vif.fast_cb.pwr_lc_req.lc_init, cycles_before_lc_done) + drop_fast_objection("lc_done"); + end + forever + @cfg.pwrmgr_vif.fast_cb.pwr_otp_req.otp_init begin + raise_fast_objection("otp_done"); + `FAST_RESPONSE_ACTION("otp_done", cfg.pwrmgr_vif.fast_cb.pwr_otp_rsp.otp_done, + cfg.pwrmgr_vif.fast_cb.pwr_otp_req.otp_init, cycles_before_otp_done) + drop_fast_objection("otp_done"); + end + join_none + endtask : fast_responder + `undef FAST_RESPONSE_ACTION + + function void control_assertions(bit enable); + `uvm_info(`gfn, $sformatf("%0sabling assertions", enable ? "En" : "Dis"), UVM_MEDIUM) + cfg.pwrmgr_clock_enables_sva_vif.disable_sva = !enable; + cfg.pwrmgr_rstmgr_sva_vif.disable_sva = !enable; + endfunction + + local task wait_for_fall_through(); + `DV_WAIT(!cfg.pwrmgr_vif.pwr_cpu.core_sleeping) + exp_intr = 1'b1; + `uvm_info(`gfn, "wait_for_fall_through succeeds", UVM_MEDIUM) + endtask + + local task wait_for_abort(); + `DV_WAIT( + !cfg.pwrmgr_vif.pwr_flash.flash_idle || !cfg.pwrmgr_vif.pwr_otp_rsp.otp_idle || + !cfg.pwrmgr_vif.pwr_lc_rsp.lc_idle) + exp_intr = 1'b1; + `uvm_info(`gfn, "wait_for_abort succeeds", UVM_MEDIUM) + endtask + + local task wait_for_low_power_transition(); + wait_for_reset_cause(pwrmgr_pkg::LowPwrEntry); + exp_wakeup_reasons = wakeups & wakeups_en; + exp_intr = 1'b1; + `uvm_info(`gfn, "Setting expected interrupt", UVM_MEDIUM) + endtask + + task process_low_power_hint(); + `uvm_info(`gfn, "Entering process_low_power_hint", UVM_MEDIUM) + // Timeout if the low power transition waits too long for WFI. + `DV_WAIT(cfg.pwrmgr_vif.fast_state != pwrmgr_pkg::FastPwrStateActive) + `uvm_info(`gfn, "In process_low_power_hint pre forks", UVM_MEDIUM) + // Clear expectations. + exp_wakeup_reasons = 1'b0; + fork + begin : isolation_fork + fork + wait_for_fall_through(); + wait_for_abort(); + wait_for_low_power_transition(); + join_any + disable fork; + end + join + // At this point we know the low power transition went through or was aborted. + // If it went through, determine if the transition to active state is for a reset, and + // cancel the expected interrupt. + if (exp_wakeup_reasons) begin + `DV_WAIT(cfg.pwrmgr_vif.slow_state == pwrmgr_pkg::SlowPwrStateMainPowerOn) + if (cfg.pwrmgr_vif.pwrup_cause == pwrmgr_pkg::Reset) begin + `uvm_info(`gfn, "Cancelling expected interrupt", UVM_MEDIUM) + exp_intr = 1'b0; + end + end + endtask + + // Updates control CSR. + task update_control_csr(); + fork + begin + ral.control.core_clk_en.set(control_enables.core_clk_en); + ral.control.io_clk_en.set(control_enables.io_clk_en); + ral.control.usb_clk_en_lp.set(control_enables.usb_clk_en_lp); + ral.control.usb_clk_en_active.set(control_enables.usb_clk_en_active); + ral.control.main_pd_n.set(control_enables.main_pd_n); + ral.control.low_power_hint.set(low_power_hint); + // Disable assertions when main power is down. + control_assertions(control_enables.main_pd_n); + `uvm_info(`gfn, $sformatf( + "Setting control CSR to 0x%x, enables=%p, low_power_hint=%b", + ral.control.get(), + control_enables, + low_power_hint + ), UVM_MEDIUM) + csr_update(.csr(ral.control)); + wait_for_csr_to_propagate_to_slow_domain(); + end + // Predict the effect of the potential low power transition. + if (low_power_hint) process_low_power_hint(); + join_any + endtask : update_control_csr + + // This enables the fast fsm to transition to low power when all nvms are idle after the + // transition is enabled by software and cpu WFI. When not all are idle the transition is + // aborted. + virtual task set_nvms_idle(logic flash_idle = 1'b1, logic lc_idle = 1'b1, logic otp_idle = 1'b1); + `uvm_info(`gfn, $sformatf( + "Setting nvms idle: flash=%b, lc=%b, otp=%b", flash_idle, lc_idle, otp_idle), + UVM_MEDIUM) + cfg.pwrmgr_vif.update_flash_idle(flash_idle); + cfg.pwrmgr_vif.update_lc_idle(lc_idle); + cfg.pwrmgr_vif.update_otp_idle(otp_idle); + endtask + + // Waits for the fast fsm becoming active or inactive, indicated by the + // fetch_en output going On or Off respectively. + task wait_for_fast_fsm(fast_fsm_activity_e activity = FastFsmActive); + lc_ctrl_pkg::lc_tx_t fetch_en = activity == FastFsmActive ? lc_ctrl_pkg::On : lc_ctrl_pkg::Off; + `uvm_info(`gfn, $sformatf("starting wait for pwrmgr %s", activity.name), UVM_MEDIUM) + `DV_SPINWAIT(wait (cfg.pwrmgr_vif.fetch_en == fetch_en);, + "timeout waiting for pwrmgr fast fsm target activity", FetchEnTimeoutNs) + `uvm_info(`gfn, $sformatf("pwrmgr reached %s", activity.name), UVM_MEDIUM) + endtask + + // Waits for the lc_rst output going inactive, which would complete a device reset. + // This should not be called for shallow sleep, since there is no lc_rst request. + task wait_for_lc_rst_release(); + `uvm_info(`gfn, "starting wait for release of lc_rst for non-aon domain", UVM_MEDIUM) + `DV_WAIT(cfg.pwrmgr_vif.pwr_rst_req.rst_lc_req[1] == 1'b1, + "timeout waiting for lc_rst[1] to be active", FetchEnTimeoutNs) + `DV_WAIT(cfg.pwrmgr_vif.pwr_rst_req.rst_lc_req[1] == 1'b0, + "timeout waiting for lc_rst[1] to be inactive", FetchEnTimeoutNs) + `uvm_info(`gfn, "pwrmgr fast released lc_req[1]", UVM_MEDIUM) + endtask + + task wait_for_reset_cause(pwrmgr_pkg::reset_cause_e cause); + `DV_WAIT(cfg.pwrmgr_vif.pwr_rst_req.reset_cause == cause) + `uvm_info(`gfn, $sformatf("Observed reset cause_match %s (0x%x)", cause.name, cause), + UVM_MEDIUM) + endtask + + virtual task wait_for_csr_to_propagate_to_slow_domain(); + csr_wr(.ptr(ral.cfg_cdc_sync), .value(1'b1)); + csr_spinwait(.ptr(ral.cfg_cdc_sync), .exp_data(1'b0), + .timeout_ns(PropagationToSlowTimeoutInNanoSeconds)); + `uvm_info(`gfn, "CSR updates made it to the slow domain", UVM_MEDIUM) + endtask + + // Checks the reset_status CSR matches expectations. + task check_reset_status(resets_t expected_resets); + csr_rd_check(.ptr(ral.reset_status[0]), .compare_value(expected_resets), + .err_msg("reset_status")); + endtask + + task fast_check_reset_status(resets_t expected_resets); + logic [pwrmgr_reg_pkg::NumRstReqs-1:0] init_reset_status; + `uvm_info(`gfn, "init reset status", UVM_MEDIUM); + // Wait to get out of low power state, since all reset status should have settled. + if (cfg.pwrmgr_vif.fast_state == pwrmgr_pkg::FastPwrStateLowPower) begin + `DV_SPINWAIT(wait(cfg.pwrmgr_vif.fast_state != pwrmgr_pkg::FastPwrStateLowPower);, + "fast state out of low power for reset timeout", 15_000) + end + + init_reset_status = cfg.pwrmgr_vif.reset_status; + if (expected_resets == init_reset_status) begin + // This is a success, so nothing more to do. + return; + end else begin + `DV_SPINWAIT(wait(cfg.pwrmgr_vif.reset_status != init_reset_status);, $sformatf( + "reset_status wait timeout exp:%x init:%x", expected_resets, init_reset_status), + 15_000) + // The various bits of reset_status could have different sync delays, wait some more. + cfg.clk_rst_vif.wait_clks(2); + `DV_CHECK_EQ(cfg.pwrmgr_vif.reset_status, expected_resets) + end + endtask + + // Checks the wake_status CSR matches expectations. + task check_wake_status(wakeups_t expected_wakeups); + csr_rd_check(.ptr(ral.wake_status[0]), .compare_value(expected_wakeups), + .err_msg("wake_status")); + endtask + + task fast_check_wake_status(wakeups_t expected_wakeups); + logic [pwrmgr_reg_pkg::NumWkups-1:0] init_wakeup_status; + `uvm_info(`gfn, "init wakeup", UVM_MEDIUM); + init_wakeup_status = cfg.pwrmgr_vif.wakeup_status; + + // Wait to get out of low power state, since all wake status should have settled + if (cfg.pwrmgr_vif.fast_state == pwrmgr_pkg::FastPwrStateLowPower) begin + `DV_SPINWAIT(wait(cfg.pwrmgr_vif.fast_state != pwrmgr_pkg::FastPwrStateLowPower);, + "fast state out of low power for wakeup timeout", 15_000) + end + + if (expected_wakeups == init_wakeup_status) begin + // This is a success, so nothing more to do. + return; + end else begin + `DV_SPINWAIT(wait(cfg.pwrmgr_vif.wakeup_status != init_wakeup_status);, $sformatf( + "wakeup_status wait timeout exp:%x init:%x", expected_wakeups, init_wakeup_status + ), 15_000) + // The various bits of wakeup_status could have different sync delays, so wait some more. + cfg.clk_rst_vif.wait_clks(2); + `DV_CHECK_EQ(cfg.pwrmgr_vif.wakeup_status, expected_wakeups) + end + endtask + + task fast_check_wake_info(wakeups_t reasons, wakeups_t prior_reasons = '0, bit fall_through, + bit prior_fall_through = '0, bit abort, bit prior_abort = '0); + pwrmgr_reg_pkg::pwrmgr_hw2reg_wake_info_reg_t initial_value, exp_value; + initial_value = cfg.pwrmgr_vif.wake_info; + + if (disable_wakeup_capture) begin + exp_value.reasons = prior_reasons; + exp_value.fall_through = prior_fall_through; + exp_value.abort = prior_abort; + end else begin + exp_value.reasons = (reasons | prior_reasons); + exp_value.fall_through = (fall_through | prior_fall_through); + exp_value.abort = (abort | prior_abort); + end + if (exp_value != initial_value) begin + // The various bits of wake_info could have different sync delays, so wait some more. + cfg.clk_rst_vif.wait_clks(1); + `DV_SPINWAIT(wait(cfg.pwrmgr_vif.wake_info == exp_value);, + $sformatf("wake info wait timeout exp:%p actual:%p", exp_value, + cfg.pwrmgr_vif.wake_info), + 15_000) + end + endtask : fast_check_wake_info + + // Checks the wake_info CSR matches expectations depending on capture disable. + // The per-field "prior_" arguments support cases where the wake_info register was not + // cleared and may contain residual values. + task check_wake_info(wakeups_t reasons, wakeups_t prior_reasons = '0, bit fall_through, + bit prior_fall_through = '0, bit abort, bit prior_abort = '0); + if (disable_wakeup_capture) begin + csr_rd_check(.ptr(ral.wake_info.reasons), .compare_value(prior_reasons), + .err_msg("With capture disabled")); + csr_rd_check(.ptr(ral.wake_info.fall_through), .compare_value(prior_fall_through), + .err_msg("With capture disabled")); + csr_rd_check(.ptr(ral.wake_info.abort), .compare_value(prior_abort), + .err_msg("With capture disabled")); + end else begin + csr_rd_check(.ptr(ral.wake_info.reasons), .compare_value(reasons | prior_reasons), + .err_msg("With capture enabled")); + csr_rd_check(.ptr(ral.wake_info.fall_through), + .compare_value(fall_through | prior_fall_through), + .err_msg("With capture enabled")); + csr_rd_check(.ptr(ral.wake_info.abort), .compare_value(abort | prior_abort), + .err_msg("With capture enabled")); + end + endtask : check_wake_info + + task clear_wake_info(); + // To clear wake_info, capture must be disabled. + csr_wr(.ptr(ral.wake_info_capture_dis), .value(1'b1)); + csr_wr(.ptr(ral.wake_info), .value('1)); + endtask + + function void send_escalation_reset(); + `uvm_info(`gfn, "Sending escalation reset", UVM_MEDIUM) + cfg.m_esc_agent_cfg.vif.sender_cb.esc_tx_int <= 2'b10; + endfunction + + function void clear_escalation_reset(); + `uvm_info(`gfn, "Clearing escalation reset", UVM_MEDIUM) + cfg.m_esc_agent_cfg.vif.sender_cb.esc_tx_int <= 2'b01; + endfunction + + function void send_ndm_reset(); + `uvm_info(`gfn, "Sending ndm reset", UVM_MEDIUM) + cfg.pwrmgr_vif.cpu_i.ndmreset_req = 1'b1; + endfunction + + function void clear_ndm_reset(); + `uvm_info(`gfn, "Clearing ndm reset", UVM_MEDIUM) + cfg.pwrmgr_vif.cpu_i.ndmreset_req = 1'b0; + endfunction + + task send_power_glitch(); + // Create glitch by 'glitch_power_reset'. An outgoing alert is only possible + // when main power is up. + if (control_enables.main_pd_n) expect_fatal_alerts = 1; + else expect_fatal_alerts = 0; + `uvm_info(`gfn, $sformatf( + "Sending power glitch, expecting %0s alert", expect_fatal_alerts ? "an" : "no"), + UVM_MEDIUM) + cfg.pwrmgr_vif.glitch_power_reset(); + endtask + + // bad_bits = {done, good} + task add_rom_rsp_noise(); + bit [MUBI4W*2-1:0] bad_bits; + int delay; + + repeat (10) begin + delay = $urandom_range(5, 10); + `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(bad_bits, + bad_bits[MUBI4W*2-1:MUBI4W] != prim_mubi_pkg::MuBi4True; + bad_bits[MUBI4W*2-1:MUBI4W] != prim_mubi_pkg::MuBi4False; + bad_bits[MUBI4W-1:0] != prim_mubi_pkg::MuBi4False; + bad_bits[MUBI4W-1:0] != prim_mubi_pkg::MuBi4True;) + `uvm_info(`gfn, $sformatf("add_rom_rsp_noise to 0x%x", bad_bits), UVM_HIGH) + cfg.pwrmgr_vif.rom_ctrl = bad_bits; + #(delay * 10ns); + end + endtask : add_rom_rsp_noise + + // Drive rom_ctrl at post reset stage + virtual task init_rom_response(); + if (cfg.pwrmgr_vif.rom_ctrl.done != prim_mubi_pkg::MuBi4True) begin + cfg.pwrmgr_vif.rom_ctrl.good = get_rand_mubi4_val( + .t_weight(1), .f_weight(1), .other_weight(1) + ); + cfg.pwrmgr_vif.rom_ctrl.done = get_rand_mubi4_val( + .t_weight(0), .f_weight(1), .other_weight(1) + ); + `DV_WAIT(cfg.pwrmgr_vif.fast_state == pwrmgr_pkg::FastPwrStateRomCheckDone) + cfg.pwrmgr_vif.rom_ctrl.good = get_rand_mubi4_val( + .t_weight(1), .f_weight(1), .other_weight(1) + ); + cfg.pwrmgr_vif.rom_ctrl.done = get_rand_mubi4_val( + .t_weight(0), .f_weight(1), .other_weight(1) + ); + cfg.slow_clk_rst_vif.wait_clks(10); + cfg.pwrmgr_vif.rom_ctrl.good = get_rand_mubi4_val( + .t_weight(1), .f_weight(1), .other_weight(1) + ); + cfg.pwrmgr_vif.rom_ctrl.done = get_rand_mubi4_val( + .t_weight(0), .f_weight(1), .other_weight(1) + ); + cfg.slow_clk_rst_vif.wait_clks(5); + cfg.pwrmgr_vif.rom_ctrl.good = get_rand_mubi4_val( + .t_weight(1), .f_weight(1), .other_weight(1) + ); + cfg.pwrmgr_vif.rom_ctrl.done = get_rand_mubi4_val( + .t_weight(0), .f_weight(1), .other_weight(1) + ); + cfg.slow_clk_rst_vif.wait_clks(5); + cfg.pwrmgr_vif.rom_ctrl.good = prim_mubi_pkg::MuBi4True; + cfg.pwrmgr_vif.rom_ctrl.done = prim_mubi_pkg::MuBi4True; + end + `uvm_info(`gfn, "Set rom response to MuBi4True", UVM_MEDIUM) + endtask + +endclass : pwrmgr_base_vseq diff --git a/src/pwrmgr/dv/env/seq_lib/pwrmgr_common_vseq.sv b/src/pwrmgr/dv/env/seq_lib/pwrmgr_common_vseq.sv new file mode 100644 index 0000000..e3e131e --- /dev/null +++ b/src/pwrmgr/dv/env/seq_lib/pwrmgr_common_vseq.sv @@ -0,0 +1,113 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class pwrmgr_common_vseq extends pwrmgr_base_vseq; + `uvm_object_utils(pwrmgr_common_vseq) + + constraint num_trans_c {num_trans inside {[1 : 2]};} + `uvm_object_new + + parameter int STATE_TRANSITION_NS = 50000; + + virtual task pre_start(); + csr_excl_item csr_excl = ral.get_excl_item(); + super.pre_start(); + // In pwrmgr, random reset event can be regarded as power glitch in tb. + // Since glitch is marked as fatal and creates alert after PR#12072, + // exclude pwrmgr_reg_block.fault_status from the random reset tests + // to avoid spurious test failure. + if (common_seq_type inside {"csr_mem_rw_with_rand_reset", "stress_all_with_rand_reset"}) begin + csr_excl.add_excl("pwrmgr_reg_block.fault_status", CsrExclCheck); + expect_fatal_alerts = 1; + end + endtask + + virtual task body(); + run_common_vseq_wrapper(num_trans); + `uvm_info(`gfn, "Done with body", UVM_HIGH) + endtask : body + + task rand_reset_eor_clean_up(); + // clear wakeup at the beginning + cfg.pwrmgr_vif.update_wakeups('0); + cfg.clk_rst_vif.wait_clks(2); + + // clear interrupt + csr_wr(.ptr(ral.intr_state), .value(1)); + endtask : rand_reset_eor_clean_up + + // pwrmgr has three alert events + // REG_INTG_ERR, ESC_TIMEOUT and MAIN_PD_GLITCH + // all others will trigger only reset. + // So disable wait_alert by skipping super.check_sec_cm_fi_resp() + virtual task check_sec_cm_fi_resp(sec_cm_base_if_proxy if_proxy); + string slow_st_to, fast_st_to, msg; + // to avoid 100 column cut off + slow_st_to = { + "slow state local esc chk timeout:", + "fast_state %s, pwr_ast_req.pwr_clamp %0d, pwr_ast_req.main_pd_n %0d" + }; + fast_st_to = { + "fast state local esc chk timeout:", + "pwr_rst_req.rst_lc_req %0d, pwr_rst_req.rst_sys_req %0d, pwr_clk_req %0d" + }; + + `uvm_info(`gfn, $sformatf("sec_cm_type %s", if_proxy.sec_cm_type.name), UVM_MEDIUM) + + case (if_proxy.sec_cm_type) + SecCmPrimSparseFsmFlop: begin + // if slow state is unknown, + // wait for + // fast_state == FastPwrStateInvalid + // tb.dut.pwr_ast_o.pwr_clamp == 1 + // tb.dut.pwr_ast_o.main_pd_n == 0 + // + // if fast state is unknown, + // wait for + // tb.dut.pwr_rst_o.rst_lc_req == 2'b11 + // tb.dut.pwr_rst_o.rst_sys_req == 2'b11 + // tb.dut.pwr_clk_o == 3'b0 + if (!uvm_re_match("*.u_slow_fsm.*", if_proxy.path)) begin + `uvm_info(`gfn, "detect unknown slow state", UVM_MEDIUM) + msg = $sformatf( + slow_st_to, + cfg.pwrmgr_vif.fast_state.name, + cfg.pwrmgr_vif.pwr_ast_req.pwr_clamp, + cfg.pwrmgr_vif.pwr_ast_req.main_pd_n + ); + + `DV_SPINWAIT(wait(cfg.pwrmgr_vif.fast_state == pwrmgr_pkg::FastPwrStateInvalid && + cfg.pwrmgr_vif.pwr_ast_req.pwr_clamp == 1 && + cfg.pwrmgr_vif.pwr_ast_rsp.main_pok == 0);, msg, STATE_TRANSITION_NS) + end + if (!uvm_re_match("*.u_fsm.*", if_proxy.path)) begin + `uvm_info(`gfn, "detect unknown fast state", UVM_MEDIUM) + msg = $sformatf( + fast_st_to, + cfg.pwrmgr_vif.pwr_rst_req.rst_lc_req, + cfg.pwrmgr_vif.pwr_rst_req.rst_sys_req, + cfg.pwrmgr_vif.pwr_clk_req + ); + + `DV_SPINWAIT(wait(cfg.pwrmgr_vif.pwr_rst_req.rst_lc_req == 2'b11 && + cfg.pwrmgr_vif.pwr_rst_req.rst_sys_req == 2'b11 && + cfg.pwrmgr_vif.pwr_clk_req == 3'h0);, msg, 5000) + end + end + SecCmPrimCount: begin + // wait for fast state to be FastPwrStateResetPrep + // before assert reset + `uvm_info(`gfn, "check rx_clk local esc", UVM_MEDIUM) + msg = $sformatf( + "rx clk loc esc chk timeout : fast_state %s", cfg.pwrmgr_vif.fast_state.name + ); + `DV_SPINWAIT(wait(cfg.pwrmgr_vif.fast_state == pwrmgr_pkg::FastPwrStateResetPrep);, msg, + STATE_TRANSITION_NS) + end + default: `uvm_fatal(`gfn, $sformatf("unexpected sec_cm_type %s", if_proxy.sec_cm_type.name)) + endcase // case (if_proxy.sec_cm_type) + // This makes sure errors are not injected too close together to avoid confusion. + cfg.slow_clk_rst_vif.wait_clks(10); + endtask : check_sec_cm_fi_resp +endclass diff --git a/src/pwrmgr/dv/env/seq_lib/pwrmgr_disable_rom_integrity_check_vseq.sv b/src/pwrmgr/dv/env/seq_lib/pwrmgr_disable_rom_integrity_check_vseq.sv new file mode 100644 index 0000000..0026eaf --- /dev/null +++ b/src/pwrmgr/dv/env/seq_lib/pwrmgr_disable_rom_integrity_check_vseq.sv @@ -0,0 +1,130 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Test multiple resets with setting lc_* inputs with random value. +class pwrmgr_disable_rom_integrity_check_vseq extends pwrmgr_base_vseq; + + `uvm_object_utils(pwrmgr_disable_rom_integrity_check_vseq) + `uvm_object_new + + rand bit release_by_good; + + constraint wakeups_c {wakeups == 0;} + constraint wakeups_en_c {wakeups_en == 0;} + + function void post_randomize(); + sw_rst_from_rstmgr = get_rand_mubi4_val(.t_weight(8), .f_weight(4), .other_weight(4)); + super.post_randomize(); + endfunction + + local task detect_block(output bit blocked); + blocked = 1; + repeat (20) begin + @cfg.slow_clk_rst_vif.cb; + if (cfg.pwrmgr_vif.fast_state == pwrmgr_pkg::FastPwrStateActive) begin + blocked = 0; + break; + end + end + endtask + + task body(); + resets_t enabled_resets; + wait_for_fast_fsm(FastFsmActive); + check_reset_status('0); + + for (int i = 0; i < 5; ++i) begin + `uvm_info(`gfn, $sformatf("Starting new round %0d", i), UVM_MEDIUM) + `DV_CHECK_RANDOMIZE_FATAL(this) + setup_interrupt(.enable(en_intr)); + + // set lc ctrl input to random value + cfg.pwrmgr_vif.lc_hw_debug_en = get_rand_lc_tx_val( + .t_weight(1), .f_weight(3), .other_weight(1) + ); + cfg.pwrmgr_vif.lc_dft_en = get_rand_lc_tx_val(.t_weight(1), .f_weight(3), .other_weight(1)); + cfg.pwrmgr_vif.rom_ctrl.done = get_rand_mubi4_val( + .t_weight(1), .f_weight(3), .other_weight(1)); + cfg.pwrmgr_vif.rom_ctrl.good = get_rand_mubi4_val( + .t_weight(1), .f_weight(3), .other_weight(1)); + + `uvm_info(`gfn, $sformatf( + "Set done 0x%x, good 0x%x", cfg.pwrmgr_vif.rom_ctrl.done, + cfg.pwrmgr_vif.rom_ctrl.good), UVM_MEDIUM) + + enabled_resets = resets_en & resets; + `uvm_info(`gfn, $sformatf( + "Enabled resets=0x%x, power_reset=%b, escalation=%b, sw_reset=%b, ndm_reset=%b", + enabled_resets, + power_glitch_reset, + escalation_reset, + sw_rst_from_rstmgr == prim_mubi_pkg::MuBi4True, + ndm_reset + ), UVM_MEDIUM) + + csr_wr(.ptr(ral.reset_en[0]), .value(resets_en)); + // This is necessary to propagate reset_en. + wait_for_csr_to_propagate_to_slow_domain(); + + // Trigger resets. The glitch is sent prior to the externals since if it is delayed + // it will cause a separate reset after the externals, which complicates the checks. + if (power_glitch_reset) send_power_glitch(); + cfg.clk_rst_vif.wait_clks(cycles_before_reset); + + `uvm_info(`gfn, $sformatf("Sending resets=0x%x", resets), UVM_MEDIUM) + cfg.pwrmgr_vif.update_resets(resets); + `uvm_info(`gfn, $sformatf("Sending sw reset from rstmgr=%b", sw_rst_from_rstmgr), UVM_MEDIUM) + if (escalation_reset) send_escalation_reset(); + cfg.pwrmgr_vif.update_sw_rst_req(sw_rst_from_rstmgr); + if (ndm_reset) send_ndm_reset(); + + `uvm_info(`gfn, "Wait for Fast State NE FastPwrStateActive", UVM_MEDIUM) + `DV_WAIT(cfg.pwrmgr_vif.fast_state != pwrmgr_pkg::FastPwrStateActive) + + if (cfg.pwrmgr_vif.rom_ctrl.done != prim_mubi_pkg::MuBi4True) begin + // Check fast state is not FastPwrStateActive for a while + repeat (20) begin + @cfg.slow_clk_rst_vif.cb; + `DV_CHECK_NE(cfg.pwrmgr_vif.fast_state, pwrmgr_pkg::FastPwrStateActive) + end + + // Set done to True. + `uvm_info(`gfn, "Set rom_ctrl.done input True", UVM_MEDIUM) + cfg.pwrmgr_vif.rom_ctrl.done = prim_mubi_pkg::MuBi4True; + cfg.slow_clk_rst_vif.wait_clks(2); + end + + if (cfg.pwrmgr_vif.rom_ctrl.good != prim_mubi_pkg::MuBi4True) begin + bit blocked = 0; + detect_block(blocked); + if (blocked) begin + if (release_by_good) begin + // Set to good. + cfg.pwrmgr_vif.rom_ctrl.good = prim_mubi_pkg::MuBi4True; + end else begin + // Disable rom checks. + `uvm_info(`gfn, "Set lc ctrl inputs On", UVM_MEDIUM) + cfg.pwrmgr_vif.lc_hw_debug_en = lc_ctrl_pkg::On; + cfg.pwrmgr_vif.lc_dft_en = lc_ctrl_pkg::On; + end + end // if (blocked) + cfg.slow_clk_rst_vif.wait_clks(2); + end + wait(cfg.pwrmgr_vif.pwr_clk_req.main_ip_clk_en == 1'b1); + + wait_for_fast_fsm(FastFsmActive); + `uvm_info(`gfn, "Back from reset", UVM_MEDIUM) + + check_wake_info(.reasons('0), .fall_through(1'b0), .abort(1'b0)); + + cfg.slow_clk_rst_vif.wait_clks(4); + check_reset_status('0); + + // And check interrupt is not set. + check_and_clear_interrupt(.expected(1'b0)); + end + clear_wake_info(); + endtask + +endclass : pwrmgr_disable_rom_integrity_check_vseq diff --git a/src/pwrmgr/dv/env/seq_lib/pwrmgr_esc_clk_rst_malfunc_vseq.sv b/src/pwrmgr/dv/env/seq_lib/pwrmgr_esc_clk_rst_malfunc_vseq.sv new file mode 100644 index 0000000..195adc3 --- /dev/null +++ b/src/pwrmgr/dv/env/seq_lib/pwrmgr_esc_clk_rst_malfunc_vseq.sv @@ -0,0 +1,42 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Description: +// This sequence creates escalation clock and reset malfunction at FastPwrStateActive state. +// This event will trigger timeout counter and assert timeout signal +// when timeout counter reaches EscTimeOutCnt value. +// Once the timeout occurs, it will create fatal alert and alert agent(tb) will set esc rst. +// The pass or failure status is determined in the cip scoreboard. +class pwrmgr_esc_clk_rst_malfunc_vseq extends pwrmgr_base_vseq; + `uvm_object_utils(pwrmgr_esc_clk_rst_malfunc_vseq) + + `uvm_object_new + constraint num_trans_c {num_trans inside {[1 : 3]};} + + virtual task body(); + wait_for_fast_fsm(FastFsmActive); + // Wait some time so the stimulus is sent after the fast fsm becoming active. + cfg.clk_rst_vif.wait_clks(4); + expect_fatal_alerts = 1; + trigger_escalation_timeout(); + wait_for_fast_fsm(FastFsmActive); + endtask : body + + // Trigers an escalation timeout fault, either stopping clk_esc_i or driving rst_esc_ni. + // + // Randomly set a bit to 0 or 1: if 0 stop clk_esc_i, if 1 make rst_esc_ni active. + task trigger_escalation_timeout(); + int which = $urandom_range(0, 1); + `uvm_info(`gfn, $sformatf("Triggering escalation via %0s", which ? "rst" : "clk"), UVM_MEDIUM) + if (which == 0) cfg.esc_clk_rst_vif.stop_clk(); + else cfg.esc_clk_rst_vif.drive_rst_pin(1'b0); + + // Wait for cpu fetch to be disabled, as an indication a reset is triggered. + `DV_SPINWAIT(wait (cfg.pwrmgr_vif.fetch_en != lc_ctrl_pkg::On);, + "timeout waiting for the CPU to be inactive", FetchEnTimeoutNs) + `uvm_info(`gfn, "Releasing trigger", UVM_MEDIUM) + if (which == 0) cfg.esc_clk_rst_vif.start_clk(); + else cfg.esc_clk_rst_vif.drive_rst_pin(1'b1); + endtask : trigger_escalation_timeout +endclass diff --git a/src/pwrmgr/dv/env/seq_lib/pwrmgr_escalation_timeout_vseq.sv b/src/pwrmgr/dv/env/seq_lib/pwrmgr_escalation_timeout_vseq.sv new file mode 100644 index 0000000..68aad09 --- /dev/null +++ b/src/pwrmgr/dv/env/seq_lib/pwrmgr_escalation_timeout_vseq.sv @@ -0,0 +1,68 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// Description: +// This test checks that an escalation reset is generated when the escalation clock stops for +// enough cycles. +class pwrmgr_escalation_timeout_vseq extends pwrmgr_base_vseq; + `uvm_object_utils(pwrmgr_escalation_timeout_vseq) + + `uvm_object_new + + localparam int TIMEOUT_THRESHOLD = 128; + + int trans_cnt = 0; + constraint num_trans_c {num_trans inside {[1 : 5]};} + + task check_stopped_esc_clk(int stop_cycles, bit expect_reset); + fork + begin + `uvm_info(`gfn, $sformatf("Stopping escalation clock for %0d cycles", stop_cycles), + UVM_MEDIUM) + cfg.esc_clk_rst_vif.stop_clk(); + cfg.clk_rst_vif.wait_clks(stop_cycles); + `uvm_info(`gfn, "Restarting escalation clock", UVM_MEDIUM) + cfg.esc_clk_rst_vif.start_clk(); + cfg.esc_clk_rst_vif.wait_clks(4000); + end + begin + cfg.clk_rst_vif.wait_clks(TIMEOUT_THRESHOLD); + if (expect_reset) begin + `DV_WAIT(cfg.pwrmgr_vif.fetch_en != lc_ctrl_pkg::On, + "Timeout waiting for cpu fetch disable", 4000) + `uvm_info(`gfn, "cpu fetch disabled, indicating a reset", UVM_MEDIUM) + `DV_WAIT(cfg.pwrmgr_vif.pwr_rst_req.rstreqs[pwrmgr_reg_pkg::ResetEscIdx] == 1'b1 && + cfg.pwrmgr_vif.pwr_rst_req.reset_cause == pwrmgr_pkg::HwReq, + "Timeout waiting for outgoing escalation reset", 40000) + `uvm_info(`gfn, "Outgoing escalation reset", UVM_MEDIUM) + end else begin + repeat (8000) begin + cfg.clk_rst_vif.wait_clks(1); + if (cfg.pwrmgr_vif.fetch_en != lc_ctrl_pkg::On) begin + `uvm_error(`gfn, "Unexpected cpu fetch disable, indicating a reset") + end + end + end + end + join + endtask + + virtual task body(); + wait_for_fast_fsm(FastFsmActive); + cfg.slow_clk_rst_vif.set_freq_mhz(1); + cfg.esc_clk_rst_vif.wait_clks(200); + // The timeout is not predictable for two reasons: + // - The initial count for the timeout can be from 0 to 7, which means the timeout could + // happen between 121 and 128 cycles after the clock. + // - The timeout has a req-ack synchronizer which has some randomness due to the phase. + // This adds a few more cycles of uncertainty. + // Keep the clock stopped for less than 118 cycles should be safe to avoid an alert. + check_stopped_esc_clk(118, 1'b0); + check_stopped_esc_clk(2000, 1'b1); + wait_for_fast_fsm(FastFsmActive); + // This should generate a reset but it doesn't so the test will fail. + // TODO(lowrisc/opentitan#20516): Enable this test when this is fixed. + // check_stopped_esc_clk(136, 1'b1); + endtask : body + +endclass diff --git a/src/pwrmgr/dv/env/seq_lib/pwrmgr_glitch_vseq.sv b/src/pwrmgr/dv/env/seq_lib/pwrmgr_glitch_vseq.sv new file mode 100644 index 0000000..0a27b84 --- /dev/null +++ b/src/pwrmgr/dv/env/seq_lib/pwrmgr_glitch_vseq.sv @@ -0,0 +1,42 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// Description: +// This test asserts glitch to power_reset and see +// dut can recover gracefully. +class pwrmgr_glitch_vseq extends pwrmgr_base_vseq; + `uvm_object_utils(pwrmgr_glitch_vseq) + + `uvm_object_new + + int trans_cnt = 0; + constraint num_trans_c {num_trans inside {[1 : 5]};} + + virtual task body(); + expect_fatal_alerts = 1; + for (int i = 0; i < num_trans; ++i) begin + wait_for_fast_fsm(FastFsmActive); + cfg.clk_rst_vif.wait_clks(4); + + fork + send_power_glitch(); + begin + cfg.pwrmgr_vif.update_ast_main_pok(0); + cfg.slow_clk_rst_vif.wait_clks(2); + cfg.pwrmgr_vif.update_ast_main_pok(1); + end + join + + cfg.clk_rst_vif.wait_clks(cycles_before_reset); + + `DV_SPINWAIT(wait(cfg.pwrmgr_vif.fast_state == pwrmgr_pkg::FastPwrStateResetPrep && + cfg.pwrmgr_vif.pwr_rst_req.rstreqs[2] == 1);, $sformatf( + "checker timeout : fast_state %s, pwr_rst_req 0x%x", + cfg.pwrmgr_vif.fast_state.name, + cfg.pwrmgr_vif.pwr_rst_req.rstreqs + ), 10000) + + dut_init(); + end + endtask : body +endclass diff --git a/src/pwrmgr/dv/env/seq_lib/pwrmgr_global_esc_vseq.sv b/src/pwrmgr/dv/env/seq_lib/pwrmgr_global_esc_vseq.sv new file mode 100644 index 0000000..19cfba5 --- /dev/null +++ b/src/pwrmgr/dv/env/seq_lib/pwrmgr_global_esc_vseq.sv @@ -0,0 +1,63 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// Description: +// This test asserts global escalation reset to dut +// and check glocal escalation request is handled by +// dut properly. +class pwrmgr_global_esc_vseq extends pwrmgr_base_vseq; + `uvm_object_utils(pwrmgr_global_esc_vseq) + + `uvm_object_new + + int trans_cnt = 0; + constraint num_trans_c {num_trans inside {[1 : 5]};} + + virtual task body(); + fork + send_esc(); + check_rst_req(); + join + endtask : body + + task send_esc(); + int cycle; + for (int i = 0; i < num_trans; ++i) begin + wait_for_fast_fsm(FastFsmActive); + cycle = $urandom_range(50, 300); + send_escalation_reset(); + repeat (cycle) @(cfg.clk_rst_vif.cb); + clear_escalation_reset(); + end + endtask : send_esc + + task check_rst_req(); + bit dut_init_done = -1; + + while (trans_cnt < num_trans) begin + @(cfg.clk_rst_vif.cb); + wait(cfg.pwrmgr_vif.fast_state != pwrmgr_pkg::FastPwrStateActive && + cfg.pwrmgr_vif.pwr_rst_req.rstreqs[3] == 1'b1); + trans_cnt++; + + // Make sure previous dut_init is done + if (dut_init_done > -1) begin + wait(dut_init_done == 1); + end + // Spawning dut_init thread then go to + // wait reset state + fork + begin + dut_init_done = 0; + dut_init(); + dut_init_done = 1; + end + begin + cfg.clk_rst_vif.wait_clks(10); + end + join_any + end + wait(dut_init_done == 1); + endtask : check_rst_req + +endclass diff --git a/src/pwrmgr/dv/env/seq_lib/pwrmgr_lowpower_invalid_vseq.sv b/src/pwrmgr/dv/env/seq_lib/pwrmgr_lowpower_invalid_vseq.sv new file mode 100644 index 0000000..c65bcbf --- /dev/null +++ b/src/pwrmgr/dv/env/seq_lib/pwrmgr_lowpower_invalid_vseq.sv @@ -0,0 +1,140 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// The test to create transition to invalid state from any lowpower transitions. +class pwrmgr_lowpower_invalid_vseq extends pwrmgr_base_vseq; + + `uvm_object_utils(pwrmgr_lowpower_invalid_vseq) + `uvm_object_new + + // Create enum to map rtl local sparse state + // to continuous dv state. + typedef enum bit [3:0] { + DVWaitDisClks = 0, + DVWaitFallThrough = 1, + DVWaitNvmIdleChk = 2, + DVWaitLowPowerPrep = 3, + DVWaitReqPwrDn = 4, + DVWaitLowPower = 5, + DVWaitEnableClocks = 6, + DVWaitReleaseLcRst = 7, + DVWaitOtpInit = 8, + DVWaitLcInit = 9, + DVWaitAckPwrUp = 10, + DVWaitRomCheck = 11, + DVWaitStrap = 12, + DVWaitActive = 13, + DVWaitInvalid = 14 + } reset_index_e; + + constraint wakeups_c {wakeups != 0;} + constraint wakeup_en_c { + solve wakeups before wakeups_en; + |(wakeups_en & wakeups) == 1'b1; + } + + task body(); + reset_index_e reset_index; + resets_t enabled_resets; + string path = "tb.dut.u_fsm.fsm_invalid_i"; + int num_of_target_states = 4; + + // Spurious interrupt check can be executed by + // residue of lowpower task. Since we cannot kill csr op + // by disable fork, we have to disable spurious interrup check. + cfg.invalid_st_test = 1; + + wait_for_fast_fsm(FastFsmActive); + `uvm_info(`gfn, "At body start", UVM_MEDIUM) + check_wake_status('0); + reset_index = DVWaitFallThrough; + + for (int i = 0; i < num_of_target_states; ++i) begin + `uvm_info(`gfn, $sformatf("Starting new round%0d %s", i, reset_index.name), UVM_MEDIUM) + `DV_CHECK_RANDOMIZE_FATAL(this) + setup_interrupt(.enable(en_intr)); + fork + start_lowpower_transition(); + begin + int wait_time_ns = 10000; + `DV_SPINWAIT(wait(cfg.pwrmgr_vif.fast_state == dv2rtl_st(reset_index));, $sformatf( + "Timed out waiting for state %s", reset_index.name), wait_time_ns) + + @cfg.clk_rst_vif.cbn; + `DV_CHECK(uvm_hdl_force(path, 1)) + `uvm_info(`gfn, "Injected invalid slow state", UVM_MEDIUM) + @cfg.clk_rst_vif.cb; + end + join_any + @cfg.clk_rst_vif.cb; + `DV_CHECK(uvm_hdl_release(path)) + `DV_CHECK(cfg.pwrmgr_vif.fast_state, pwrmgr_pkg::FastPwrStateInvalid) + + repeat (10) @cfg.clk_rst_vif.cb; + + apply_reset(); + reset_index=reset_index.next(); + wait_for_fast_fsm(FastFsmActive); + end // for (int i = 0; i < 4; ++i) + endtask + + task start_lowpower_transition(); + wakeups_t enabled_wakeups = wakeups_en & wakeups; + `DV_CHECK(enabled_wakeups, $sformatf( + "Some wakeup must be enabled: wkups=%b, wkup_en=%b", wakeups, wakeups_en)) + `uvm_info(`gfn, $sformatf("Enabled wakeups=0x%x", enabled_wakeups), UVM_MEDIUM) + csr_wr(.ptr(ral.wakeup_en[0]), .value(wakeups_en)); + + low_power_hint = 1; + update_control_csr(); + + `uvm_info(`gfn, $sformatf("Enabled wakeups=0x%x", enabled_wakeups), UVM_MEDIUM) + + // Initiate low power transition. + cfg.pwrmgr_vif.update_cpu_sleeping(1'b1); + set_nvms_idle(); + + `DV_WAIT(cfg.pwrmgr_vif.fast_state != pwrmgr_pkg::FastPwrStateActive) + + if (ral.control.main_pd_n.get_mirrored_value() == 1'b0) begin + wait_for_reset_cause(pwrmgr_pkg::LowPwrEntry); + end + + // Now bring it back. + cfg.slow_clk_rst_vif.wait_clks(cycles_before_wakeup); + cfg.pwrmgr_vif.update_wakeups(wakeups); + + wait(cfg.pwrmgr_vif.pwr_clk_req.main_ip_clk_en == 1'b1); + + // wakeups should be registered. + cfg.pwrmgr_vif.update_wakeups('1); + + wait_for_fast_fsm(FastFsmActive); + `uvm_info(`gfn, "Back from wakeup", UVM_MEDIUM) + endtask : start_lowpower_transition + + function pwrmgr_pkg::fast_pwr_state_e dv2rtl_st(reset_index_e idx); + case (idx) + DVWaitDisClks: return pwrmgr_pkg::FastPwrStateDisClks; + DVWaitFallThrough: return pwrmgr_pkg::FastPwrStateFallThrough; + DVWaitNvmIdleChk: return pwrmgr_pkg::FastPwrStateNvmIdleChk; + DVWaitLowPowerPrep: return pwrmgr_pkg::FastPwrStateLowPowerPrep; + DVWaitReqPwrDn: return pwrmgr_pkg::FastPwrStateReqPwrDn; + DVWaitLowPower: return pwrmgr_pkg::FastPwrStateLowPower; + DVWaitEnableClocks: return pwrmgr_pkg::FastPwrStateEnableClocks; + DVWaitReleaseLcRst: return pwrmgr_pkg::FastPwrStateReleaseLcRst; + DVWaitOtpInit: return pwrmgr_pkg::FastPwrStateOtpInit; + DVWaitLcInit: return pwrmgr_pkg::FastPwrStateLcInit; + DVWaitAckPwrUp: return pwrmgr_pkg::FastPwrStateAckPwrUp; + DVWaitRomCheck: return pwrmgr_pkg::FastPwrStateRomCheckDone; + DVWaitStrap: return pwrmgr_pkg::FastPwrStateStrap; + DVWaitActive: return pwrmgr_pkg::FastPwrStateActive; + DVWaitInvalid: return pwrmgr_pkg::FastPwrStateInvalid; + default: begin + `uvm_error("dv2rma_st", $sformatf("unknown index:%0d", idx)) + end + endcase + endfunction : dv2rtl_st + +endclass : pwrmgr_lowpower_invalid_vseq diff --git a/src/pwrmgr/dv/env/seq_lib/pwrmgr_lowpower_wakeup_race_vseq.sv b/src/pwrmgr/dv/env/seq_lib/pwrmgr_lowpower_wakeup_race_vseq.sv new file mode 100644 index 0000000..7506405 --- /dev/null +++ b/src/pwrmgr/dv/env/seq_lib/pwrmgr_lowpower_wakeup_race_vseq.sv @@ -0,0 +1,138 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// The lowpower_wakeup race test randomly enables wakeups, info capture, and interrupts, +// and sends wakeups in the temporal vecinity of low power entry. It also sends wakeups +// after wakeup processing starts. +class pwrmgr_lowpower_wakeup_race_vseq extends pwrmgr_base_vseq; + `uvm_object_utils(pwrmgr_lowpower_wakeup_race_vseq) + + `uvm_object_new + + constraint wakeups_c {wakeups != 0;} + + rand bit keep_prior_wake_info; + + constraint wakeup_en_c { + solve wakeups before wakeups_en; + |(wakeups_en & wakeups) == 1'b1; + } + + rand int cycles_before_early_wakeup; + rand int cycles_before_transition; + constraint cycles_racing_c { + cycles_before_early_wakeup inside {[2 : 8]}; + cycles_before_transition inside {[2 : 8]}; + } + + task body(); + logic [TL_DW-1:0] value; + wakeups_t prior_reasons = '0; + bit prior_fall_through = '0; + bit prior_abort = '0; + wait_for_fast_fsm(FastFsmActive); + + check_wake_status('0); + for (int i = 0; i < num_trans; ++i) begin + `uvm_info(`gfn, "Starting new round", UVM_MEDIUM) + `DV_CHECK_RANDOMIZE_FATAL(this) + setup_interrupt(.enable(en_intr)); + + csr_wr(.ptr(ral.wakeup_en[0]), .value(wakeups_en)); + `uvm_info(`gfn, $sformatf("Enabled wakeups=0x%x", wakeups_en & wakeups), UVM_MEDIUM) + + if (keep_prior_wake_info) begin + csr_rd(.ptr(ral.wake_info.reasons), .value(prior_reasons)); + csr_rd(.ptr(ral.wake_info.fall_through), .value(prior_fall_through)); + csr_rd(.ptr(ral.wake_info.abort), .value(prior_abort)); + end else begin + clear_wake_info(); + prior_reasons = '0; + prior_fall_through = '0; + prior_abort = '0; + end + `uvm_info(`gfn, $sformatf( + "Prior wake_info: reasons=0x%x, fall_through=%b, abort=%b", + prior_reasons, + prior_fall_through, + prior_abort + ), UVM_MEDIUM) + + `uvm_info(`gfn, $sformatf("%0sabling wakeup capture", disable_wakeup_capture ? "Dis" : "En"), + UVM_MEDIUM) + csr_wr(.ptr(ral.wake_info_capture_dis), .value(disable_wakeup_capture)); + + low_power_hint = 1'b1; + update_control_csr(); + + set_nvms_idle(); + + // This will send the wakeup and trigger low power entry so they almost coincide. + fork + begin + cfg.slow_clk_rst_vif.wait_clks(cycles_before_transition); + // Initiate low power transition. + cfg.pwrmgr_vif.update_cpu_sleeping(1'b1); + end + begin + cfg.slow_clk_rst_vif.wait_clks(cycles_before_early_wakeup); + // Send the wakeups. + cfg.pwrmgr_vif.update_wakeups(wakeups); + end + join + + wait_for_fast_fsm(FastFsmInactive); + + // Check wake_status prior to wakeup, or the unit requesting wakeup will have been reset. + // This read will not work in the chip, since the processor will be asleep. + // We wait until the cycle following the fast fsm lc_rst release. + if (ral.control.main_pd_n.get_mirrored_value() == 1'b0) begin + wait_for_lc_rst_release(); + check_wake_status(wakeups & wakeups_en); + `uvm_info(`gfn, $sformatf("Got wake_status=0x%x", wakeups & wakeups_en), UVM_MEDIUM) + end + wait(cfg.pwrmgr_vif.pwr_clk_req.main_ip_clk_en == 1'b1); + + // Send more wakeups to make sure they are reported in CSRs. With this all enabled + // wakeups should be registered. + cfg.pwrmgr_vif.update_wakeups('1); + + wait_for_fast_fsm(FastFsmActive); + `uvm_info(`gfn, "Back from wakeup", UVM_MEDIUM) + + // make this check parallel. + // to avoid csr rd blocking later status read request and + // miss status update window. + @cfg.clk_rst_vif.cb; + fork + begin + fast_check_reset_status(0); + end + begin + fast_check_wake_info(.reasons(wakeups_en), .prior_reasons(prior_reasons), + .fall_through(1'b0), .abort(1'b0), + .prior_fall_through(prior_fall_through), .prior_abort(prior_abort)); + end + join + // This is the expected side-effect of the low power entry reset, since the source of the + // non-aon wakeup sources will deassert it as a consequence of their reset. + // Some aon wakeups may remain active until software clears them. If they didn't, such wakeups + // will remain active, preventing the device from going to sleep. + cfg.pwrmgr_vif.update_wakeups('0); + cfg.slow_clk_rst_vif.wait_clks(10); + cfg.pwrmgr_vif.update_cpu_sleeping(1'b0); + + // wait for clock is on + cfg.clk_rst_vif.wait_clks(10); + + check_wake_status('0); + + // Wait for interrupt to be generated whether or not it is enabled. + cfg.slow_clk_rst_vif.wait_clks(10); + check_and_clear_interrupt(.expected(1'b1)); + end + clear_wake_info(); + endtask + +endclass : pwrmgr_lowpower_wakeup_race_vseq diff --git a/src/pwrmgr/dv/env/seq_lib/pwrmgr_repeat_wakeup_reset_vseq.sv b/src/pwrmgr/dv/env/seq_lib/pwrmgr_repeat_wakeup_reset_vseq.sv new file mode 100644 index 0000000..a457fc5 --- /dev/null +++ b/src/pwrmgr/dv/env/seq_lib/pwrmgr_repeat_wakeup_reset_vseq.sv @@ -0,0 +1,79 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// Description: +// The wakeup_reset test randomly enables wakeups and resets, info capture, and interrupts, +// and sends wakeups and resets in close temporal proximity at random times. +class pwrmgr_repeat_wakeup_reset_vseq extends pwrmgr_wakeup_reset_vseq; + `uvm_object_utils(pwrmgr_repeat_wakeup_reset_vseq) + + `uvm_object_new + + bit [lc_ctrl_pkg::TxWidth-1:0] bad_lc_tx; + + int cycles_from_reset; + int micros_to_release; + + bit super_sequence_done; + + // add invalid value to rom_ctrl + virtual task twirl_rom_response(); + add_rom_rsp_noise(); + cfg.pwrmgr_vif.rom_ctrl.done = prim_mubi_pkg::MuBi4False; + cfg.pwrmgr_vif.rom_ctrl.good = prim_mubi_pkg::MuBi4False; + cfg.clk_rst_vif.wait_clks(5); + add_rom_rsp_noise(); + wait(cfg.pwrmgr_vif.fast_state == pwrmgr_pkg::FastPwrStateRomCheckDone); + add_rom_rsp_noise(); + cfg.pwrmgr_vif.rom_ctrl.good = prim_mubi_pkg::MuBi4True; + cfg.clk_rst_vif.wait_clks(5); + cfg.pwrmgr_vif.rom_ctrl.done = prim_mubi_pkg::MuBi4True; + endtask + + task body(); + num_trans_c.constraint_mode(0); + num_trans = 50; + super_sequence_done = 0; + + disable_assert(); + fork + begin + super.body(); + super_sequence_done = 1; + end + drv_stim(mubi_mode); + join + endtask : body + + function void disable_assert(); + $assertoff(0, "tb.dut.u_cdc.u_sync_rom_ctrl"); + endfunction : disable_assert + + task drv_stim(pwrmgr_mubi_e mubi_mode); + if (mubi_mode == PwrmgrMubiLcCtrl) drv_lc_ctrl(); + endtask : drv_stim + + task drv_lc_ctrl(); + int delay; + + `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(cycles_from_reset, cycles_from_reset inside {[2 : 8]};) + `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(micros_to_release, micros_to_release inside {[2 : 4]};) + + repeat (50) begin + wait(cfg.esc_clk_rst_vif.rst_n); + cfg.clk_rst_vif.wait_clks(cycles_from_reset); + if (super_sequence_done) break; + `uvm_info(`gfn, "Injection to lc_hw_debug_en", UVM_MEDIUM) + cfg.pwrmgr_vif.lc_hw_debug_en = get_rand_lc_tx_val( + .t_weight(1), .f_weight(1), .other_weight(2) + ); + #(micros_to_release * 1us); + `uvm_info(`gfn, "Injection to lc_dft_en", UVM_MEDIUM) + if (super_sequence_done) break; + cfg.pwrmgr_vif.lc_dft_en = get_rand_lc_tx_val(.t_weight(1), .f_weight(1), .other_weight(2)); + #(micros_to_release * 1us); + end // repeat (50) + `uvm_info(`gfn, "ended drv_lc_ctrl", UVM_MEDIUM) + endtask : drv_lc_ctrl + +endclass : pwrmgr_repeat_wakeup_reset_vseq diff --git a/src/pwrmgr/dv/env/seq_lib/pwrmgr_reset_invalid_vseq.sv b/src/pwrmgr/dv/env/seq_lib/pwrmgr_reset_invalid_vseq.sv new file mode 100644 index 0000000..7b0f55f --- /dev/null +++ b/src/pwrmgr/dv/env/seq_lib/pwrmgr_reset_invalid_vseq.sv @@ -0,0 +1,129 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// The test to create transition to invalid state from any reset transitions. +class pwrmgr_reset_invalid_vseq extends pwrmgr_base_vseq; + + `uvm_object_utils(pwrmgr_reset_invalid_vseq) + `uvm_object_new + + // Create enum to map rtl local sparse state + // to continuous dv state. + typedef enum bit [3:0] { + DVWaitDisClks = 0, + DVWaitNvmShutDown = 1, + DVWaitResetPrep = 2, + DVWaitLowPower = 3, + DVWaitEnableClocks = 4, + DVWaitReleaseLcRst = 5, + DVWaitOtpInit = 6, + DVWaitLcInit = 7, + DVWaitAckPwrUp = 8, + DVWaitRomCheck = 9, + DVWaitStrap = 10, + DVWaitActive = 11, + DVWaitInvalid = 12 + } reset_index_e; + + constraint wakeups_c {wakeups == 0;} + constraint wakeups_en_c {wakeups_en == 0;} + + function void post_randomize(); + sw_rst_from_rstmgr = get_rand_mubi4_val(.t_weight(8), .f_weight(4), .other_weight(4)); + super.post_randomize(); + endfunction + + task body(); + reset_index_e reset_index; + resets_t enabled_resets; + string path = "tb.dut.u_fsm.fsm_invalid_i"; + int num_of_target_states = 11; + + wait_for_fast_fsm(FastFsmActive); + check_reset_status('0); + $assertoff(0, "tb.dut.u_cdc.u_clr_reqack.SyncReqAckHoldReq"); + + for (int i = 0; i < num_of_target_states; ++i) begin + `uvm_info(`gfn, $sformatf("Starting new round %0d", i), UVM_MEDIUM) + `DV_CHECK_RANDOMIZE_FATAL(this) + setup_interrupt(.enable(en_intr)); + + fork + create_any_reset_event(); + begin + int wait_time_ns = 20000; + `DV_SPINWAIT(wait(cfg.pwrmgr_vif.fast_state == dv2rtl_st(reset_index));, $sformatf( + "Timed out waiting for state %s", reset_index.name), wait_time_ns) + + @cfg.clk_rst_vif.cbn; + `uvm_info(`gfn, $sformatf("Will cause invalid state forcing %s = 1", path), UVM_MEDIUM) + `DV_CHECK(uvm_hdl_force(path, 1)) + @cfg.clk_rst_vif.cb; + end + join + @cfg.clk_rst_vif.cb; + `DV_CHECK(uvm_hdl_release(path)) + `DV_CHECK(cfg.pwrmgr_vif.fast_state, pwrmgr_pkg::FastPwrStateInvalid) + `uvm_info(`gfn, "All good, resetting for next round", UVM_MEDIUM) + repeat (10) @cfg.clk_rst_vif.cb; + apply_reset(); + reset_index=reset_index.next(); + wait_for_fast_fsm(FastFsmActive); + end + endtask + + task create_any_reset_event(); + resets_t enabled_resets = resets_t'(resets_en & resets); + `uvm_info(`gfn, $sformatf( + "Enabled resets=0x%x, power_reset=%b, escalation=%b, sw_reset=%b, ndm_reset=%b", + enabled_resets, + power_glitch_reset, + escalation_reset, + sw_rst_from_rstmgr == prim_mubi_pkg::MuBi4True, + ndm_reset + ), UVM_MEDIUM) + + `uvm_info(`gfn, "Trying to write to reset_en CSR", UVM_MEDIUM) + csr_wr(.ptr(ral.reset_en[0]), .value(resets_en)); + // This is necessary to propagate reset_en. + wait_for_csr_to_propagate_to_slow_domain(); + + // Trigger resets. The glitch is sent prior to the externals since if it is delayed + // it will cause a separate reset after the externals, which complicates the checks. + if (power_glitch_reset) send_power_glitch(); + cfg.clk_rst_vif.wait_clks(cycles_before_reset); + + if (cycles_before_reset == 0) enabled_resets = 0; + + `uvm_info(`gfn, $sformatf("Sending resets=0x%x", resets), UVM_MEDIUM) + cfg.pwrmgr_vif.update_resets(resets); + `uvm_info(`gfn, $sformatf("Sending sw reset from rstmgr=%b", sw_rst_from_rstmgr), UVM_MEDIUM) + if (escalation_reset) send_escalation_reset(); + if (ndm_reset) send_ndm_reset(); + cfg.pwrmgr_vif.update_sw_rst_req(sw_rst_from_rstmgr); + + endtask : create_any_reset_event + + function pwrmgr_pkg::fast_pwr_state_e dv2rtl_st(reset_index_e idx); + case (idx) + DVWaitDisClks: return pwrmgr_pkg::FastPwrStateDisClks; + DVWaitNvmShutDown: return pwrmgr_pkg::FastPwrStateNvmShutDown; + DVWaitResetPrep: return pwrmgr_pkg::FastPwrStateResetPrep; + DVWaitLowPower: return pwrmgr_pkg::FastPwrStateLowPower; + DVWaitEnableClocks: return pwrmgr_pkg::FastPwrStateEnableClocks; + DVWaitReleaseLcRst: return pwrmgr_pkg::FastPwrStateReleaseLcRst; + DVWaitOtpInit: return pwrmgr_pkg::FastPwrStateOtpInit; + DVWaitLcInit: return pwrmgr_pkg::FastPwrStateLcInit; + DVWaitAckPwrUp: return pwrmgr_pkg::FastPwrStateAckPwrUp; + DVWaitRomCheck: return pwrmgr_pkg::FastPwrStateRomCheckDone; + DVWaitStrap: return pwrmgr_pkg::FastPwrStateStrap; + DVWaitActive: return pwrmgr_pkg::FastPwrStateActive; + DVWaitInvalid: return pwrmgr_pkg::FastPwrStateInvalid; + default: begin + `uvm_error("dv2rma_st", $sformatf("unknown index:%0d", idx)) + end + endcase + endfunction : dv2rtl_st + +endclass : pwrmgr_reset_invalid_vseq diff --git a/src/pwrmgr/dv/env/seq_lib/pwrmgr_reset_vseq.sv b/src/pwrmgr/dv/env/seq_lib/pwrmgr_reset_vseq.sv new file mode 100644 index 0000000..0b8d9d1 --- /dev/null +++ b/src/pwrmgr/dv/env/seq_lib/pwrmgr_reset_vseq.sv @@ -0,0 +1,77 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// The reset test randomly introduces external resets, ndm resets, power glitches, and escalation +// resets. +class pwrmgr_reset_vseq extends pwrmgr_base_vseq; + + `uvm_object_utils(pwrmgr_reset_vseq) + `uvm_object_new + + constraint wakeups_c {wakeups == 0;} + constraint wakeups_en_c {wakeups_en == 0;} + + function void post_randomize(); + sw_rst_from_rstmgr = get_rand_mubi4_val(.t_weight(8), .f_weight(4), .other_weight(4)); + super.post_randomize(); + endfunction + + task body(); + logic [TL_DW-1:0] value; + resets_t enabled_resets; + wait_for_fast_fsm(FastFsmActive); + + check_reset_status('0); + for (int i = 0; i < num_trans; ++i) begin + `uvm_info(`gfn, "Starting new round", UVM_MEDIUM) + `DV_CHECK_RANDOMIZE_FATAL(this) + setup_interrupt(.enable(en_intr)); + enabled_resets = resets_en & resets; + `uvm_info(`gfn, $sformatf( + "Enabled resets=0x%x, power_reset=%b, escalation=%b, sw_reset=%b, ndm_reset=%b", + enabled_resets, + power_glitch_reset, + escalation_reset, + sw_rst_from_rstmgr == prim_mubi_pkg::MuBi4True, + ndm_reset + ), UVM_MEDIUM) + + csr_wr(.ptr(ral.reset_en[0]), .value(resets_en)); + // This is necessary to propagate reset_en. + wait_for_csr_to_propagate_to_slow_domain(); + + // Trigger resets. The glitch is sent prior to the externals since if it is delayed + // it will cause a separate reset after the externals, which complicates the checks. + if (power_glitch_reset) send_power_glitch(); + cfg.clk_rst_vif.wait_clks(cycles_before_reset); + + `uvm_info(`gfn, $sformatf("Sending resets=0x%x", resets), UVM_MEDIUM) + cfg.pwrmgr_vif.update_resets(resets); + `uvm_info(`gfn, $sformatf("Sending sw reset from rstmgr=%b", sw_rst_from_rstmgr), UVM_MEDIUM) + if (escalation_reset) begin + send_escalation_reset(); + // Wait for the alert to propagate to fault_status? + end + cfg.pwrmgr_vif.update_sw_rst_req(sw_rst_from_rstmgr); + if (ndm_reset) send_ndm_reset(); + + // Expect to start reset. + `DV_WAIT(cfg.pwrmgr_vif.fast_state != pwrmgr_pkg::FastPwrStateActive) + `uvm_info(`gfn, "Started to process reset", UVM_MEDIUM) + + wait_for_fast_fsm(FastFsmActive); + `uvm_info(`gfn, "Back from reset", UVM_MEDIUM) + + check_wake_info(.reasons('0), .fall_through(1'b0), .abort(1'b0)); + + cfg.slow_clk_rst_vif.wait_clks(4); + check_reset_status('0); + + // And check interrupt is not set. + check_and_clear_interrupt(.expected(1'b0)); + end + clear_wake_info(); + endtask + +endclass : pwrmgr_reset_vseq diff --git a/src/pwrmgr/dv/env/seq_lib/pwrmgr_sec_cm_ctrl_config_regwen_vseq.sv b/src/pwrmgr/dv/env/seq_lib/pwrmgr_sec_cm_ctrl_config_regwen_vseq.sv new file mode 100644 index 0000000..b0fa045 --- /dev/null +++ b/src/pwrmgr/dv/env/seq_lib/pwrmgr_sec_cm_ctrl_config_regwen_vseq.sv @@ -0,0 +1,38 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// Decription: +// Create low power transition and wakeup a few times. +// When PWRMGR.CONTROL.LOW_POWER_HINT is set, +// issue random write to PWRMGR.CONTROL and check +// PWRMGR.CONTROL value is not changed. +class pwrmgr_sec_cm_ctrl_config_regwen_vseq extends pwrmgr_wakeup_vseq; + `uvm_object_utils(pwrmgr_sec_cm_ctrl_config_regwen_vseq) + + `uvm_object_new + + virtual task pre_start(); + super.pre_start(); + cfg.disable_csr_rd_chk = 1; + endtask : pre_start + + task proc_illegal_ctrl_access(); + uvm_reg_data_t wdata, expdata; + cfg.clk_rst_vif.wait_clks(1); + wait(cfg.pwrmgr_vif.lowpwr_cfg_wen == 0); + + repeat ($urandom_range(1, 5)) begin + `DV_CHECK_STD_RANDOMIZE_FATAL(wdata) + expdata = ral.control.get(); + `uvm_info(`gfn, $sformatf("csr start %x", ral.control.get()), UVM_HIGH) + csr_wr(.ptr(ral.control), .value(wdata)); + csr_rd_check(.ptr(ral.control), .compare_value(expdata)); + `uvm_info(`gfn, "csr done", UVM_HIGH) + end + endtask : proc_illegal_ctrl_access + + virtual task wait_for_csr_to_propagate_to_slow_domain(); + proc_illegal_ctrl_access(); + super.wait_for_csr_to_propagate_to_slow_domain(); + endtask +endclass : pwrmgr_sec_cm_ctrl_config_regwen_vseq diff --git a/src/pwrmgr/dv/env/seq_lib/pwrmgr_smoke_vseq.sv b/src/pwrmgr/dv/env/seq_lib/pwrmgr_smoke_vseq.sv new file mode 100644 index 0000000..b54c5cc --- /dev/null +++ b/src/pwrmgr/dv/env/seq_lib/pwrmgr_smoke_vseq.sv @@ -0,0 +1,90 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// The smoke test brings the pwrmgr through a POR reset, followed by a low +// power sequence, followed by reset. + +// smoke test vseq +class pwrmgr_smoke_vseq extends pwrmgr_base_vseq; + `uvm_object_utils(pwrmgr_smoke_vseq) + + `uvm_object_new + constraint cycles_before_rst_lc_src_c {cycles_before_rst_lc_src inside {[1 : 2]};} + constraint cycles_before_otp_done_c {cycles_before_otp_done inside {[1 : 2]};} + constraint cycles_before_lc_done_c {cycles_before_lc_done inside {[1 : 2]};} + + constraint wakeups_c {wakeups != 0;} + constraint resets_c {resets != 0;} + + constraint control_enables_c { + control_enables.core_clk_en == ral.control.core_clk_en.get_reset(); + control_enables.io_clk_en == ral.control.io_clk_en.get_reset(); + control_enables.usb_clk_en_lp == ral.control.usb_clk_en_lp.get_reset(); + control_enables.usb_clk_en_active == ral.control.usb_clk_en_active.get_reset(); + control_enables.main_pd_n == ral.control.main_pd_n.get_reset(); + } + + task body(); + logic [TL_DW-1:0] value; + wakeups_t wakeup_en; + resets_t reset_en; + wait_for_fast_fsm(FastFsmActive); + set_nvms_idle(); + setup_interrupt(.enable(1'b1)); + + check_wake_status('0); + check_reset_status('0); + + // Enable all wakeups so any peripheral can cause a wakeup. + wakeup_en = '1; + csr_wr(.ptr(ral.wakeup_en[0]), .value(wakeup_en)); + + low_power_hint = 1'b1; + update_control_csr(); + + // Initiate low power transition. + cfg.pwrmgr_vif.update_cpu_sleeping(1'b1); + wait_for_reset_cause(pwrmgr_pkg::LowPwrEntry); + + // Now bring it back. + cfg.slow_clk_rst_vif.wait_clks(cycles_before_wakeup); + cfg.pwrmgr_vif.update_wakeups(wakeups); + + wait_for_fast_fsm(FastFsmActive); + `uvm_info(`gfn, "smoke back from wakeup", UVM_MEDIUM) + + check_wake_status(wakeups & wakeup_en); + check_reset_status('0); + // And make the cpu active. + cfg.pwrmgr_vif.update_cpu_sleeping(1'b0); + + cfg.pwrmgr_vif.update_wakeups('0); + check_and_clear_interrupt(.expected(1'b1)); + + // Enable resets. + reset_en = '1; + csr_wr(.ptr(ral.reset_en[0]), .value(reset_en)); + wait_for_csr_to_propagate_to_slow_domain(); + + // Trigger a reset. + cfg.pwrmgr_vif.update_resets(resets); + cfg.slow_clk_rst_vif.wait_clks(2); + wait_for_reset_cause(pwrmgr_pkg::HwReq); + + // Now bring it back: the slow fsm doesn't participate on this, so we cannot + // rely on the ctrl_cfg_regwen CSR. Wait for the reset status to clear. + wait_for_fast_fsm(FastFsmActive); + + // The reset_status CSR should be clear since the unit requesting reset + // should have been reset, so the incoming reset should have cleared. + check_reset_status('0); + check_wake_status('0); + clear_wake_info(); + + // Wait for interrupt to be generated whether or not it is enabled. + cfg.slow_clk_rst_vif.wait_clks(10); + check_and_clear_interrupt(.expected(1'b0)); + endtask + +endclass : pwrmgr_smoke_vseq diff --git a/src/pwrmgr/dv/env/seq_lib/pwrmgr_stress_all_vseq.sv b/src/pwrmgr/dv/env/seq_lib/pwrmgr_stress_all_vseq.sv new file mode 100644 index 0000000..a088b29 --- /dev/null +++ b/src/pwrmgr/dv/env/seq_lib/pwrmgr_stress_all_vseq.sv @@ -0,0 +1,42 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// combine all pwrmgr seqs (except below seqs) in one seq to run sequentially +// 1. csr seq, which requires scb to be disabled +class pwrmgr_stress_all_vseq extends pwrmgr_base_vseq; + `uvm_object_utils(pwrmgr_stress_all_vseq) + + `uvm_object_new + + task body(); + string seq_names[] = { + "pwrmgr_aborted_low_power_vseq", + "pwrmgr_lowpower_wakeup_race_vseq", + "pwrmgr_reset_vseq", + "pwrmgr_smoke_vseq", + "pwrmgr_wakeup_reset_vseq", + "pwrmgr_wakeup_vseq" + }; + + for (int i = 1; i <= num_trans; i++) begin + uvm_sequence seq; + pwrmgr_base_vseq pwrmgr_vseq; + uint seq_idx = $urandom_range(0, seq_names.size - 1); + + seq = create_seq_by_name(seq_names[seq_idx]); + `downcast(pwrmgr_vseq, seq) + + pwrmgr_vseq.do_apply_reset = 1; + pwrmgr_vseq.set_sequencer(p_sequencer); + `DV_CHECK_RANDOMIZE_FATAL(pwrmgr_vseq) + `uvm_info(`gfn, $sformatf("seq_idx = %0d, sequence is %0s", seq_idx, pwrmgr_vseq.get_name()), + UVM_MEDIUM) + + pwrmgr_vseq.start(p_sequencer); + `uvm_info(`gfn, $sformatf( + "End of sequence %0s with seq_idx = %0d", pwrmgr_vseq.get_name(), seq_idx), + UVM_MEDIUM) + end + endtask : body +endclass diff --git a/src/pwrmgr/dv/env/seq_lib/pwrmgr_sw_reset_vseq.sv b/src/pwrmgr/dv/env/seq_lib/pwrmgr_sw_reset_vseq.sv new file mode 100644 index 0000000..5fdceaf --- /dev/null +++ b/src/pwrmgr/dv/env/seq_lib/pwrmgr_sw_reset_vseq.sv @@ -0,0 +1,54 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// Description: +// The reset test randomly introduces external resets. +class pwrmgr_sw_reset_vseq extends pwrmgr_base_vseq; + + `uvm_object_utils(pwrmgr_sw_reset_vseq) + `uvm_object_new + + constraint wakeups_c {wakeups == 0;} + constraint wakeups_en_c {wakeups_en == 0;} + + task body(); + int exp_rst; + wait_for_fast_fsm(FastFsmActive); + + check_reset_status('0); + num_trans_c.constraint_mode(0); + num_trans = 30; + for (int i = 0; i < num_trans; ++i) begin + `uvm_info(`gfn, "Starting new round", UVM_MEDIUM) + `DV_CHECK_RANDOMIZE_FATAL(this) + setup_interrupt(.enable(en_intr)); + + cfg.pwrmgr_vif.sw_rst_req_i = prim_mubi_pkg::mubi4_t'($urandom_range(0, 15)); + exp_rst = (cfg.pwrmgr_vif.sw_rst_req_i == prim_mubi_pkg::MuBi4True); + cfg.slow_clk_rst_vif.wait_clks(4); + + // sw reset causes fast state machine transition to lowpower state + if (exp_rst == 1) begin + `DV_SPINWAIT(wait(cfg.pwrmgr_vif.fast_state != pwrmgr_pkg::FastPwrStateActive);, + "timeout waiting for non fast-active state", 1000) + end + + // This read is not always possible since the CPU may be off. + + wait(cfg.pwrmgr_vif.pwr_clk_req.main_ip_clk_en == 1'b1); + + wait_for_fast_fsm(FastFsmActive); + `uvm_info(`gfn, "Back from reset", UVM_MEDIUM) + + check_wake_info(.reasons('0), .fall_through(1'b0), .abort(1'b0)); + + cfg.slow_clk_rst_vif.wait_clks(4); + check_reset_status('0); + + // And check interrupt is not set. + check_and_clear_interrupt(.expected(1'b0)); + end + clear_wake_info(); + endtask + +endclass : pwrmgr_sw_reset_vseq diff --git a/src/pwrmgr/dv/env/seq_lib/pwrmgr_vseq_list.sv b/src/pwrmgr/dv/env/seq_lib/pwrmgr_vseq_list.sv new file mode 100644 index 0000000..bc09a19 --- /dev/null +++ b/src/pwrmgr/dv/env/seq_lib/pwrmgr_vseq_list.sv @@ -0,0 +1,23 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +`include "pwrmgr_base_vseq.sv" +`include "pwrmgr_aborted_low_power_vseq.sv" +`include "pwrmgr_lowpower_wakeup_race_vseq.sv" +`include "pwrmgr_reset_vseq.sv" +`include "pwrmgr_smoke_vseq.sv" +`include "pwrmgr_stress_all_vseq.sv" +`include "pwrmgr_wakeup_reset_vseq.sv" +`include "pwrmgr_wakeup_vseq.sv" +`include "pwrmgr_common_vseq.sv" +`include "pwrmgr_repeat_wakeup_reset_vseq.sv" +`include "pwrmgr_sw_reset_vseq.sv" +`include "pwrmgr_esc_clk_rst_malfunc_vseq.sv" +`include "pwrmgr_sec_cm_ctrl_config_regwen_vseq.sv" +`include "pwrmgr_global_esc_vseq.sv" +`include "pwrmgr_escalation_timeout_vseq.sv" +`include "pwrmgr_glitch_vseq.sv" +`include "pwrmgr_disable_rom_integrity_check_vseq.sv" +`include "pwrmgr_reset_invalid_vseq.sv" +`include "pwrmgr_lowpower_invalid_vseq.sv" diff --git a/src/pwrmgr/dv/env/seq_lib/pwrmgr_wakeup_reset_vseq.sv.tpl b/src/pwrmgr/dv/env/seq_lib/pwrmgr_wakeup_reset_vseq.sv.tpl new file mode 100644 index 0000000..7918cb6 --- /dev/null +++ b/src/pwrmgr/dv/env/seq_lib/pwrmgr_wakeup_reset_vseq.sv.tpl @@ -0,0 +1,169 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// The wakeup_reset test randomly enables wakeups and resets, info capture, and interrupts, +// and sends wakeups and resets in close temporal proximity at random times. +// Notice it makes no sense to send escalation reset requests while in low +// power, when the clocks are stopped, or while the system is already in reset +// since escalation should not be triggered with reset active. +class pwrmgr_wakeup_reset_vseq extends pwrmgr_base_vseq; + `uvm_object_utils(pwrmgr_wakeup_reset_vseq) + + `uvm_object_new + + constraint wakeups_c {wakeups != 0;} + + constraint wakeup_en_c { + solve wakeups before wakeups_en; + (wakeups_en & wakeups) != 0; + } + constraint disable_wakeup_capture_c {disable_wakeup_capture == 1'b0;} + + // Disabling escalation resets per comment above. + constraint escalation_reset_c {escalation_reset == 0;} + + // Cause some delays for the rom_ctrl done and good inputs. Simple, enough to hold the + // transition to active state. + // ICEBOX(lowrisc/opentitan#18236) Consider adding checks to monitor fast state transitions are + // compliant with "ROM Integrity Checks" at + // https://opentitan.org/book/hw/top_${topname}/ip_autogen/pwrmgr/doc/theory_of_operation.html#rom-integrity-checks + virtual task twirl_rom_response(); + cfg.pwrmgr_vif.rom_ctrl.done = prim_mubi_pkg::MuBi4False; + cfg.pwrmgr_vif.rom_ctrl.good = prim_mubi_pkg::MuBi4False; + @(cfg.pwrmgr_vif.fast_state == pwrmgr_pkg::FastPwrStateAckPwrUp); + cfg.pwrmgr_vif.rom_ctrl.good = prim_mubi_pkg::MuBi4True; + @(cfg.pwrmgr_vif.fast_state == pwrmgr_pkg::FastPwrStateRomCheckDone); + cfg.clk_rst_vif.wait_clks(10); + cfg.pwrmgr_vif.rom_ctrl.good = prim_mubi_pkg::MuBi4False; + cfg.clk_rst_vif.wait_clks(5); + cfg.pwrmgr_vif.rom_ctrl.good = prim_mubi_pkg::MuBi4True; + cfg.clk_rst_vif.wait_clks(5); + cfg.pwrmgr_vif.rom_ctrl.done = prim_mubi_pkg::MuBi4True; + endtask + + task body(); + logic [TL_DW-1:0] value; + resets_t enabled_resets; + wakeups_t enabled_wakeups; + + wait_for_fast_fsm(FastFsmActive); + + check_reset_status('0); + check_wake_status('0); + for (int i = 0; i < num_trans; ++i) begin + `uvm_info(`gfn, "Starting new round", UVM_MEDIUM) + `DV_CHECK_RANDOMIZE_FATAL(this) + setup_interrupt(.enable(en_intr)); + + // Enable resets. + enabled_resets = resets_en & resets; + `uvm_info(`gfn, $sformatf( + "Enabled resets=0x%x, power_reset=%b, sw_reset=%b", + enabled_resets, + power_glitch_reset, + sw_rst_from_rstmgr + ), UVM_MEDIUM) + csr_wr(.ptr(ral.reset_en[0]), .value(resets_en)); + + // Enable wakeups. + enabled_wakeups = wakeups_en & wakeups; + `DV_CHECK(enabled_wakeups, $sformatf( + "Some wakeup must be enabled: wkups=%b, wkup_en=%b", wakeups, wakeups_en)) + `uvm_info(`gfn, $sformatf("Enabled wakeups=0x%x", enabled_wakeups), UVM_MEDIUM) + csr_wr(.ptr(ral.wakeup_en[0]), .value(wakeups_en)); + + clear_wake_info(); + + `uvm_info(`gfn, $sformatf("%0sabling wakeup capture", disable_wakeup_capture ? "Dis" : "En"), + UVM_MEDIUM) + csr_wr(.ptr(ral.wake_info_capture_dis), .value(disable_wakeup_capture)); + + low_power_hint = 1'b1; + update_control_csr(); + + // Initiate low power transition. + cfg.pwrmgr_vif.update_cpu_sleeping(1'b1); + set_nvms_idle(); + // Wait for the slow state machine to be in low power. + wait(cfg.pwrmgr_vif.slow_state == pwrmgr_pkg::SlowPwrStateLowPower); + // This will send the wakeup and reset so they almost coincide. + // at low power state, do not use clk_rst_vif, cause it is off. + fork + begin + cfg.slow_clk_rst_vif.wait_clks(cycles_before_reset); + cfg.pwrmgr_vif.update_resets(resets); + + if (power_glitch_reset) begin + send_power_glitch(); + enabled_resets = 0; + end + `uvm_info(`gfn, $sformatf("Sending reset=%b, power_glitch=%b", resets, power_glitch_reset + ), UVM_MEDIUM) + end + + begin + cfg.slow_clk_rst_vif.wait_clks(cycles_before_wakeup); + cfg.pwrmgr_vif.update_wakeups(wakeups); + `uvm_info(`gfn, $sformatf("Sending wakeup=%b", wakeups), UVM_MEDIUM) + end + join + + if (cfg.en_cov) begin + cov.reset_wakeup_distance_cg.sample(cycles_before_reset - cycles_before_wakeup); + end + // twirl_rom_response has some waits, and so does the code to check wake_status, + // so we fork them to avoid conflicts. + + fork + begin + // At lowpower state, wait for clock comes back before check any csr + @cfg.clk_rst_vif.cb; + // Check wake_status prior to wakeup, or the unit requesting wakeup will have been reset. + // This read will not work in the chip, since the processor will be asleep. + // Reset status cannot be reliably checked here since it is cleared when reset goes active. + fast_check_wake_status(enabled_wakeups); + `uvm_info(`gfn, $sformatf("Got wake_status=0x%x", enabled_wakeups), UVM_MEDIUM) + end + twirl_rom_response(); + join + + wait_for_fast_fsm(FastFsmActive); + + check_reset_status('0); + + check_wake_info(.reasons(enabled_wakeups), .prior_reasons(1'b0), .fall_through(1'b0), + .prior_fall_through(1'b0), .abort(1'b0), .prior_abort(1'b0)); + + if (mubi_mode == PwrmgrMubiRomCtrl) begin + add_rom_rsp_noise(); + cfg.pwrmgr_vif.rom_ctrl.good = prim_mubi_pkg::MuBi4True; + cfg.clk_rst_vif.wait_clks(5); + cfg.pwrmgr_vif.rom_ctrl.done = prim_mubi_pkg::MuBi4True; + end + + // This is the expected side-effect of the low power entry reset, since the source of the + // non-aon wakeup sources will deassert it as a consequence of their reset. + // Some aon wakeups may remain active until software clears them. If they didn't, such wakeups + // will remain active, preventing the device from going to sleep. + cfg.pwrmgr_vif.update_wakeups('0); + cfg.slow_clk_rst_vif.wait_clks(10); + check_reset_status('0); + check_wake_status('0); + + cfg.slow_clk_rst_vif.wait_clks(10); + // An interrupt will be generated depending on the exact timing of the slow fsm getting + // the reset and wakeup. We choose not to predict it here (it is checked on other tests). + // Instead, we just check if the interrupt status is asserted and it is enabled the + // output interrupt is active. + check_and_clear_interrupt(.expected(1'b1), .check_expected('0)); + // Clear hardware resets: if they are enabled they are cleared when rst_lc_req[1] goes active, + // but this makes sure they are cleared even if none is enabled for the next round. + cfg.pwrmgr_vif.update_resets('0); + // And make the cpu active. + cfg.pwrmgr_vif.update_cpu_sleeping(1'b0); + end + clear_wake_info(); + endtask + +endclass : pwrmgr_wakeup_reset_vseq diff --git a/src/pwrmgr/dv/env/seq_lib/pwrmgr_wakeup_vseq.sv b/src/pwrmgr/dv/env/seq_lib/pwrmgr_wakeup_vseq.sv new file mode 100644 index 0000000..0f331f4 --- /dev/null +++ b/src/pwrmgr/dv/env/seq_lib/pwrmgr_wakeup_vseq.sv @@ -0,0 +1,127 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// The wakeup test randomly enables wakeups, info capture, and interrupts, +// and sends wakeups at random times. +class pwrmgr_wakeup_vseq extends pwrmgr_base_vseq; + `uvm_object_utils(pwrmgr_wakeup_vseq) + + `uvm_object_new + + constraint wakeups_c {wakeups != 0;} + + rand bit keep_prior_wake_info; + + constraint wakeup_en_c { + solve wakeups before wakeups_en; + |(wakeups_en & wakeups) == 1'b1; + } + + task body(); + logic [TL_DW-1:0] value; + wakeups_t enabled_wakeups; + wakeups_t prior_reasons = '0; + bit prior_fall_through = '0; + bit prior_abort = '0; + + wait_for_fast_fsm(FastFsmActive); + check_wake_status('0); + for (int i = 0; i < num_trans; ++i) begin + `uvm_info(`gfn, "Starting new round", UVM_MEDIUM) + `DV_CHECK_RANDOMIZE_FATAL(this) + + // Instrument interrupts. + setup_interrupt(en_intr); + + // Enable wakeups. + enabled_wakeups = wakeups_en & wakeups; + `DV_CHECK(enabled_wakeups, $sformatf( + "Some wakeup must be enabled: wkups=%b, wkup_en=%b", wakeups, wakeups_en)) + `uvm_info(`gfn, $sformatf( + "Enabled wakeups=0x%x, wakeups=0x%x, enables=0x%x", + enabled_wakeups, wakeups, wakeups_en), + UVM_MEDIUM) + csr_wr(.ptr(ral.wakeup_en[0]), .value(wakeups_en)); + + if (keep_prior_wake_info) begin + csr_rd(.ptr(ral.wake_info.reasons), .value(prior_reasons)); + csr_rd(.ptr(ral.wake_info.fall_through), .value(prior_fall_through)); + csr_rd(.ptr(ral.wake_info.abort), .value(prior_abort)); + end else begin + clear_wake_info(); + prior_reasons = '0; + prior_fall_through = '0; + prior_abort = '0; + end + `uvm_info(`gfn, $sformatf( + "Prior wake_info: reasons=0x%x, fall_through=%b, abort=%b", + prior_reasons, + prior_fall_through, + prior_abort + ), UVM_MEDIUM) + + `uvm_info(`gfn, $sformatf("%0sabling wakeup capture", disable_wakeup_capture ? "Dis" : "En"), + UVM_MEDIUM) + csr_wr(.ptr(ral.wake_info_capture_dis), .value(disable_wakeup_capture)); + + low_power_hint = 1'b1; + update_control_csr(); + + // Initiate low power transition. + cfg.pwrmgr_vif.update_cpu_sleeping(1'b1); + set_nvms_idle(); + + if (ral.control.main_pd_n.get_mirrored_value() == 1'b0) begin + wait_for_reset_cause(pwrmgr_pkg::LowPwrEntry); + end + + // Now bring it back. + cfg.slow_clk_rst_vif.wait_clks(cycles_before_wakeup); + cfg.pwrmgr_vif.update_wakeups(wakeups); + // Check wake_status prior to wakeup, or the unit requesting wakeup will have been reset. + // This read will not work in the chip, since the processor will be asleep. + cfg.slow_clk_rst_vif.wait_clks(4); + // wait for clock is on + cfg.clk_rst_vif.wait_clks(10); + + check_wake_status(enabled_wakeups); + `uvm_info(`gfn, $sformatf("Got wake_status=0x%x", enabled_wakeups), UVM_MEDIUM) + wait(cfg.pwrmgr_vif.pwr_clk_req.main_ip_clk_en == 1'b1); + + wait_for_fast_fsm(FastFsmActive); + `uvm_info(`gfn, "Back from wakeup", UVM_MEDIUM) + + @cfg.clk_rst_vif.cb; + fork + begin + fast_check_reset_status(0); + end + begin + fast_check_wake_info(.reasons(enabled_wakeups), .prior_reasons(prior_reasons), + .fall_through(1'b0), .abort(1'b0), + .prior_fall_through(prior_fall_through), .prior_abort(prior_abort)); + end + join + // This is the expected side-effect of the low power entry reset, since the source of the + // non-aon wakeup sources will deassert it as a consequence of their reset. + // Some aon wakeups may remain active until software clears them. If they didn't, such wakeups + // will remain active, preventing the device from going to sleep. + cfg.pwrmgr_vif.update_wakeups('0); + cfg.slow_clk_rst_vif.wait_clks(10); + + // if clock is off, we need to wait until it is resumed. + cfg.clk_rst_vif.wait_clks(5); + check_wake_status('0); + + // And make the cpu active. + cfg.pwrmgr_vif.update_cpu_sleeping(1'b0); + + // Wait for interrupt to be generated whether or not it is enabled. + cfg.slow_clk_rst_vif.wait_clks(10); + check_and_clear_interrupt(.expected(1'b1)); + end + clear_wake_info(); + endtask + +endclass : pwrmgr_wakeup_vseq diff --git a/src/pwrmgr/dv/pwrmgr_sim.core b/src/pwrmgr/dv/pwrmgr_sim.core new file mode 100644 index 0000000..1bd1c54 --- /dev/null +++ b/src/pwrmgr/dv/pwrmgr_sim.core @@ -0,0 +1,29 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:dv:pwrmgr_sim:0.1" +description: "PWRMGR DV sim target" +filesets: + files_rtl: + depend: + - lowrisc:ip_interfaces:pwrmgr + files_dv: + depend: + - lowrisc:dv:pwrmgr_test + - lowrisc:dv:pwrmgr_sva + files: + - tb.sv + - cov/pwrmgr_cov_bind.sv + file_type: systemVerilogSource + +targets: + sim: &sim_target + toplevel: tb + filesets: + - files_rtl + - files_dv + default_tool: vcs + + lint: + <<: *sim_target diff --git a/src/pwrmgr/dv/pwrmgr_sim_cfg.hjson b/src/pwrmgr/dv/pwrmgr_sim_cfg.hjson new file mode 100644 index 0000000..450cd0b --- /dev/null +++ b/src/pwrmgr/dv/pwrmgr_sim_cfg.hjson @@ -0,0 +1,155 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + // Name of the sim cfg - typically same as the name of the DUT. + name: pwrmgr + + // Top level dut name (sv module). + dut: pwrmgr + + // Top level testbench name (sv module). + tb: tb + + // Simulator used to sign off this block + tool: vcs + + // Fusesoc core file used for building the file list. + fusesoc_core: lowrisc:dv:pwrmgr_sim:0.1 + + // Testplan hjson file. + testplan: "{self_dir}/../data/pwrmgr_testplan.hjson" + + // Import additional common sim cfg files. + import_cfgs: [// Project wide common sim cfg file + "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson", + // Common CIP test lists + "{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/intr_test.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/stress_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/sec_cm_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson"] + + // Overrides + overrides: [ + { + name: design_level + value: "top" + } + ] + + // Exclusion files + vcs_cov_excl_files: ["{self_dir}/cov/pwrmgr_cov_manual_excl.el"] + + // Add additional tops for simulation. + sim_tops: ["pwrmgr_bind", + "pwrmgr_cov_bind", + "sec_cm_prim_count_bind", + "sec_cm_prim_sparse_fsm_flop_bind", + "sec_cm_prim_onehot_check_bind"] + + // Default iterations for all tests - each test entry can override this. + reseed: 50 + + // Default UVM test and seq class name. + uvm_test: pwrmgr_base_test + uvm_test_seq: pwrmgr_base_vseq + + // Enable cdc instrumentation. + run_opts: ["+cdc_instrumentation_enabled=1"] + + // List of test specifications. + tests: [ + { + name: pwrmgr_smoke + uvm_test_seq: pwrmgr_smoke_vseq + run_opts: ["+test_timeout_ns=1000000"] + } + { + name: pwrmgr_reset + uvm_test_seq: pwrmgr_reset_vseq + run_opts: ["+test_timeout_ns=1000000"] + } + { + name: pwrmgr_lowpower_wakeup_race + uvm_test_seq: pwrmgr_lowpower_wakeup_race_vseq + run_opts: ["+test_timeout_ns=1000000"] + } + { + name: pwrmgr_wakeup + uvm_test_seq: pwrmgr_wakeup_vseq + run_opts: ["+test_timeout_ns=1000000"] + } + { + name: pwrmgr_wakeup_reset + uvm_test_seq: pwrmgr_wakeup_reset_vseq + run_opts: ["+test_timeout_ns=1000000"] + } + { + name: pwrmgr_aborted_low_power + uvm_test_seq: pwrmgr_aborted_low_power_vseq + } + { + name: pwrmgr_sec_cm_lc_ctrl_intersig_mubi + uvm_test_seq: pwrmgr_repeat_wakeup_reset_vseq + run_opts: ["+test_timeout_ns=3000000", "+pwrmgr_mubi_mode=PwrmgrMubiLcCtrl"] + } + { + name: pwrmgr_sec_cm_rom_ctrl_intersig_mubi + uvm_test_seq: pwrmgr_repeat_wakeup_reset_vseq + run_opts: ["+test_timeout_ns=4000000", "+pwrmgr_mubi_mode=PwrmgrMubiRomCtrl"] + } + { + name: pwrmgr_sec_cm_rstmgr_intersig_mubi + uvm_test_seq: pwrmgr_sw_reset_vseq + run_opts: ["+test_timeout_ns=1000000"] + } + { + name: pwrmgr_esc_clk_rst_malfunc + uvm_test_seq: pwrmgr_esc_clk_rst_malfunc_vseq + run_opts: ["+test_timeout_ns=1000000"] + } + { + name: pwrmgr_sec_cm_ctrl_config_regwen + uvm_test_seq: pwrmgr_sec_cm_ctrl_config_regwen_vseq + run_opts: ["+test_timeout_ns=50000000"] + } + { + name: pwrmgr_global_esc + uvm_test_seq: pwrmgr_global_esc_vseq + run_opts: ["+test_timeout_ns=1000000000"] + } + { + name: pwrmgr_escalation_timeout + uvm_test_seq: pwrmgr_escalation_timeout_vseq + } + { + name: pwrmgr_glitch + uvm_test_seq: pwrmgr_glitch_vseq + run_opts: ["+test_timeout_ns=1000000"] + } + { + name: pwrmgr_disable_rom_integrity_check + uvm_test_seq: pwrmgr_disable_rom_integrity_check_vseq + run_opts: ["+test_timeout_ns=1000000"] + } + { + name: pwrmgr_reset_invalid + uvm_test_seq: pwrmgr_reset_invalid_vseq + run_opts: ["+test_timeout_ns=1000000"] + } + { + name: pwrmgr_lowpower_invalid + uvm_test_seq: pwrmgr_lowpower_invalid_vseq + run_opts: ["+test_timeout_ns=1000000"] + } + ] + + // List of regressions. + regressions: [ + { + name: smoke + tests: ["pwrmgr_smoke"] + } + ] +} diff --git a/src/pwrmgr/dv/sva/pwrmgr_ast_sva_if.sv b/src/pwrmgr/dv/sva/pwrmgr_ast_sva_if.sv new file mode 100644 index 0000000..99450f7 --- /dev/null +++ b/src/pwrmgr/dv/sva/pwrmgr_ast_sva_if.sv @@ -0,0 +1,145 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This has some assertions that check the inputs from ast react according to +// the pwrmgr outputs. The ast inputs are generated by the base sequences, but +// these assertions will also be useful at full chip level. +interface pwrmgr_ast_sva_if #( + parameter bit CheckClocks = 1'b0 +) ( + input logic clk_slow_i, + input logic rst_slow_ni, + input logic clk_main_i, + input logic clk_io_i, + input logic clk_usb_i, + input logic por_d0_ni, + // The pwrmgr outputs. + input pwrmgr_pkg::pwr_ast_req_t pwr_ast_o, + // The pwrmgr inputs. + input pwrmgr_pkg::pwr_ast_rsp_t pwr_ast_i +); + + // These numbers of cycles are meant to match both the randomization in + // pwrmgr_base_vseq, and the actual cycle counts from full chip. + // Notice the expectation for full chip is that deassertion of *clk_val + // takes 0 cycles, and assertion takes a 2 cycle synchronizer delay on + // the slow clock; deassertion of main_pok takes one cycle, and assertion + // not more than 2 cycles. + localparam int MIN_CLK_WAIT_CYCLES = 0; + localparam int MIN_PDN_WAIT_CYCLES = 0; + localparam int MAX_CLK_WAIT_CYCLES = 60; + localparam int MAX_PDN_WAIT_CYCLES = 110; + + bit disable_sva; + bit reset_or_disable; + + always_comb reset_or_disable = !rst_slow_ni || disable_sva; + + `define CLK_WAIT_BOUNDS ##[MIN_CLK_WAIT_CYCLES:MAX_CLK_WAIT_CYCLES] + `define PDN_WAIT_BOUNDS ##[MIN_PDN_WAIT_CYCLES:MAX_PDN_WAIT_CYCLES] + + // Clock enable-valid. + + // Changes triggered by por_d0_ni only affect clk_val. + `ASSERT(CoreClkGlitchToValOff_A, $fell(por_d0_ni) |-> ##[0:1] !pwr_ast_i.core_clk_val, clk_slow_i, + reset_or_disable) + `ASSERT(CoreClkGlitchToValOn_A, + $rose(por_d0_ni) && pwr_ast_o.core_clk_en |-> ##[0:2] pwr_ast_i.core_clk_val, clk_slow_i, + reset_or_disable) + `ASSERT(IoClkGlitchToValOff_A, $fell(por_d0_ni) |-> ##[0:1] !pwr_ast_i.io_clk_val, clk_slow_i, + reset_or_disable) + `ASSERT(IoClkGlitchToValOn_A, + $rose(por_d0_ni) && pwr_ast_o.io_clk_en |-> ##[0:2] pwr_ast_i.io_clk_val, clk_slow_i, + reset_or_disable) + `ASSERT(UsbClkGlitchToValOff_A, $fell(por_d0_ni) |-> ##[0:5] !pwr_ast_i.usb_clk_val, clk_slow_i, + reset_or_disable) + `ASSERT(UsbClkGlitchToValOn_A, + $rose(por_d0_ni) && pwr_ast_o.usb_clk_en |-> ##[0:5] pwr_ast_i.usb_clk_val, clk_slow_i, + reset_or_disable) + + // Changes not triggered by por_d0_ni + `ASSERT(CoreClkHandshakeOn_A, + $rose(pwr_ast_o.core_clk_en) && por_d0_ni |-> `CLK_WAIT_BOUNDS + pwr_ast_i.core_clk_val || !por_d0_ni, clk_slow_i, reset_or_disable) + `ASSERT(CoreClkHandshakeOff_A, + $fell(pwr_ast_o.core_clk_en) |-> `CLK_WAIT_BOUNDS !pwr_ast_i.core_clk_val, clk_slow_i, + reset_or_disable) + + `ASSERT(IoClkHandshakeOn_A, + $rose(pwr_ast_o.io_clk_en) && por_d0_ni |-> `CLK_WAIT_BOUNDS + pwr_ast_i.io_clk_val || !por_d0_ni, clk_slow_i, reset_or_disable) + `ASSERT(IoClkHandshakeOff_A, + $fell(pwr_ast_o.io_clk_en) |-> `CLK_WAIT_BOUNDS !pwr_ast_i.io_clk_val, clk_slow_i, + reset_or_disable) + + // Usb is a bit different: apparently usb_clk_val can stay low after a power glitch, so it may + // already be low when usb_clk_en drops. + `ASSERT(UsbClkHandshakeOn_A, + $rose(pwr_ast_o.usb_clk_en) && por_d0_ni && $past(por_d0_ni, 1) |-> `CLK_WAIT_BOUNDS + pwr_ast_i.usb_clk_val || !por_d0_ni, clk_slow_i, reset_or_disable) + `ASSERT(UsbClkHandshakeOff_A, + $fell(pwr_ast_o.usb_clk_en) |-> `CLK_WAIT_BOUNDS !pwr_ast_i.usb_clk_val, clk_slow_i, + reset_or_disable) + + if (CheckClocks) begin : gen_check_clock + int main_clk_cycles, io_clk_cycles, usb_clk_cycles; + always_ff @(posedge clk_main_i) main_clk_cycles++; + always_ff @(posedge clk_io_i) io_clk_cycles++; + always_ff @(posedge clk_usb_i) usb_clk_cycles++; + + `ASSERT(MainClkStopped_A, + $fell( + pwr_ast_i.core_clk_val + ) |=> ($stable( + main_clk_cycles + ) || pwr_ast_i.core_clk_val) [* 1 : $], + clk_slow_i, reset_or_disable) + `ASSERT(MainClkRun_A, + $rose( + pwr_ast_i.core_clk_val + ) |=> (!$stable( + main_clk_cycles + ) || !pwr_ast_i.core_clk_val) [* 1 : $], + clk_slow_i, reset_or_disable) + + `ASSERT(IOClkStopped_A, + $fell( + pwr_ast_i.io_clk_val + ) |=> ($stable( + io_clk_cycles + ) || pwr_ast_i.io_clk_val) [* 1 : $], + clk_slow_i, reset_or_disable) + `ASSERT(IOClkRun_A, + $rose( + pwr_ast_i.io_clk_val + ) |=> (!$stable( + io_clk_cycles + ) || !pwr_ast_i.io_clk_val) [* 1 : $], + clk_slow_i, reset_or_disable) + + `ASSERT(USBClkStopped_A, + $fell( + pwr_ast_i.usb_clk_val + ) |=> ($stable( + usb_clk_cycles + ) || pwr_ast_i.usb_clk_val) [* 1 : $], + clk_slow_i, reset_or_disable) + `ASSERT(USBClkRun_A, + $rose( + pwr_ast_i.usb_clk_val + ) |=> (!$stable( + usb_clk_cycles + ) || !pwr_ast_i.usb_clk_val) [* 1 : $], + clk_slow_i, reset_or_disable) + end + + // Main pd-pok + `ASSERT(MainPdHandshakeOn_A, pwr_ast_o.main_pd_n |-> `PDN_WAIT_BOUNDS pwr_ast_i.main_pok, + clk_slow_i, reset_or_disable) + `ASSERT(MainPdHandshakeOff_A, !pwr_ast_o.main_pd_n |-> `PDN_WAIT_BOUNDS !pwr_ast_i.main_pok, + clk_slow_i, reset_or_disable) + + `undef CLK_WAIT_BOUNDS + `undef PDN_WAIT_BOUNDS +endinterface diff --git a/src/pwrmgr/dv/sva/pwrmgr_bind.sv b/src/pwrmgr/dv/sva/pwrmgr_bind.sv new file mode 100644 index 0000000..dd73f78 --- /dev/null +++ b/src/pwrmgr/dv/sva/pwrmgr_bind.sv @@ -0,0 +1,87 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +module pwrmgr_bind; +`ifndef GATE_LEVEL + bind pwrmgr tlul_assert #( + .EndpointType("Device") + ) tlul_assert_device (.clk_i, .rst_ni, .h2d(tl_i), .d2h(tl_o)); + + // In top-level testbench, do not bind the csr_assert_fpv to reduce simulation time. +`ifndef TOP_LEVEL_DV + bind pwrmgr pwrmgr_csr_assert_fpv pwrmgr_csr_assert (.clk_i, .rst_ni, .h2d(tl_i), .d2h(tl_o)); +`endif + + // Clock control assertions. + bind pwrmgr pwrmgr_clock_enables_sva_if pwrmgr_clock_enables_sva_if ( + .clk_i(clk_slow_i), + .rst_ni(rst_slow_ni), + .fast_state(u_fsm.state_q), + .slow_state(u_slow_fsm.state_q), + // The synchronized control CSR bits. + .main_pd_ni(slow_main_pd_n), + .core_clk_en_i(slow_core_clk_en), + .io_clk_en_i(slow_io_clk_en), + .usb_clk_en_lp_i(slow_usb_clk_en_lp), + .usb_clk_en_active_i(slow_usb_clk_en_active), + .usb_ip_clk_status_i(usb_ip_clk_status), + // The main power control. + .main_pd_n(pwr_ast_o.main_pd_n), + // The output enables. + .core_clk_en(pwr_ast_o.core_clk_en), + .io_clk_en(pwr_ast_o.io_clk_en), + .usb_clk_en(pwr_ast_o.usb_clk_en) + ); + + bind pwrmgr pwrmgr_rstmgr_sva_if pwrmgr_rstmgr_sva_if ( + .clk_i, + .rst_ni, + .clk_slow_i, + .rst_slow_ni, + // The outputs from pwrmgr. + .rst_lc_req(pwr_rst_o.rst_lc_req), + .rst_sys_req(pwr_rst_o.rst_sys_req), + // The inputs from rstmgr. + .rst_lc_src_n(pwr_rst_i.rst_lc_src_n), + .rst_sys_src_n(pwr_rst_i.rst_sys_src_n) + ); + + bind pwrmgr clkmgr_pwrmgr_sva_if clkmgr_pwrmgr_sva_if ( + .clk_i, + .rst_ni, + .io_clk_en(pwr_clk_o.io_ip_clk_en), + .io_status(pwr_clk_i.io_status), + .main_clk_en(pwr_clk_o.main_ip_clk_en), + .main_status(pwr_clk_i.main_status), + .usb_clk_en(pwr_clk_o.usb_ip_clk_en), + .usb_status(pwr_clk_i.usb_status) + ); + + bind pwrmgr pwrmgr_sec_cm_checker_assert pwrmgr_sec_cm_checker_assert ( + .clk_i, + .rst_ni, + .clk_lc_i, + .rst_lc_ni, + .clk_esc_i, + .rst_esc_ni, + .clk_slow_i, + .rst_slow_ni, + .rst_main_ni, + .pwr_rst_o, + .slow_esc_rst_req(slow_peri_reqs.rstreqs[3]), + .slow_mp_rst_req(slow_peri_reqs.rstreqs[2]), + .slow_fsm_invalid, + .fast_fsm_invalid(u_fsm.u_state_regs.unused_err_o), + .rom_intg_chk_dis(u_fsm.rom_intg_chk_dis), + .rom_intg_chk_done(u_fsm.rom_intg_chk_done), + .rom_intg_chk_good(u_fsm.rom_intg_chk_good), + .fast_state(u_fsm.state_q), + .lc_dft_en_i(u_fsm.lc_dft_en_i), + .lc_hw_debug_en_i(u_fsm.lc_hw_debug_en_i), + .main_pd_ni(u_slow_fsm.main_pd_ni), + .rom_ctrl_done_i(u_fsm.rom_ctrl_done_i), + .rom_ctrl_good_i(u_fsm.rom_ctrl_good_i) + ); +`endif +endmodule diff --git a/src/pwrmgr/dv/sva/pwrmgr_clock_enables_sva_if.sv b/src/pwrmgr/dv/sva/pwrmgr_clock_enables_sva_if.sv new file mode 100644 index 0000000..355b52c --- /dev/null +++ b/src/pwrmgr/dv/sva/pwrmgr_clock_enables_sva_if.sv @@ -0,0 +1,59 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This has some assertions that check that the output clock enables correspond +// to the control CSR when transitioning into or out of the active state. In +// addition, the usb clock can change anytime when in the active state. +interface pwrmgr_clock_enables_sva_if ( + input logic clk_i, + input logic rst_ni, + input pwrmgr_pkg::fast_pwr_state_e fast_state, + input pwrmgr_pkg::slow_pwr_state_e slow_state, + // The synchronized control CSR bits. + input logic main_pd_ni, + input logic io_clk_en_i, + input logic core_clk_en_i, + input logic usb_clk_en_lp_i, + input logic usb_clk_en_active_i, + input logic usb_ip_clk_status_i, + // The output enables. + input logic main_pd_n, + input logic io_clk_en, + input logic core_clk_en, + input logic usb_clk_en +); + + bit disable_sva; + bit reset_or_disable; + + always_comb reset_or_disable = !rst_ni || disable_sva; + + sequence transitionUp_S; slow_state == pwrmgr_pkg::SlowPwrStateReqPwrUp; endsequence + + sequence transitionDown_S; slow_state == pwrmgr_pkg::SlowPwrStatePwrClampOn; endsequence + + bit fast_is_active; + always_comb fast_is_active = fast_state == pwrmgr_pkg::FastPwrStateActive; + + // This allows the usb enable to be slower since it also depends on usb clk_status. + sequence usbActiveTransition_S; + ##[0:7] !fast_is_active || usb_clk_en == (usb_clk_en_active_i | usb_ip_clk_status_i); + endsequence + + `ASSERT(CoreClkPwrUp_A, transitionUp_S |=> core_clk_en == 1'b1, clk_i, reset_or_disable) + `ASSERT(IoClkPwrUp_A, transitionUp_S |=> io_clk_en == 1'b1, clk_i, reset_or_disable) + `ASSERT(UsbClkPwrUp_A, transitionUp_S |=> usb_clk_en == usb_clk_en_active_i, clk_i, + reset_or_disable) + + // This deals with transitions while the fast fsm is active. + `ASSERT(UsbClkActive_A, fast_is_active && $changed(usb_clk_en_active_i) |=> usbActiveTransition_S, + clk_i, reset_or_disable) + + `ASSERT(CoreClkPwrDown_A, transitionDown_S |=> core_clk_en == (core_clk_en_i && main_pd_ni), + clk_i, reset_or_disable) + `ASSERT(IoClkPwrDown_A, transitionDown_S |=> io_clk_en == (io_clk_en_i && main_pd_ni), clk_i, + reset_or_disable) + `ASSERT(UsbClkPwrDown_A, transitionDown_S |=> usb_clk_en == (usb_clk_en_lp_i && main_pd_ni), + clk_i, reset_or_disable) +endinterface diff --git a/src/pwrmgr/dv/sva/pwrmgr_rstmgr_sva_if.core b/src/pwrmgr/dv/sva/pwrmgr_rstmgr_sva_if.core new file mode 100644 index 0000000..9083269 --- /dev/null +++ b/src/pwrmgr/dv/sva/pwrmgr_rstmgr_sva_if.core @@ -0,0 +1,19 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:dv:pwrmgr_rstmgr_sva_if:0.1" +description: "PWRMGR to RSTMGR assertion interface." +filesets: + files_dv: + depend: + - lowrisc:ip_interfaces:pwrmgr_pkg + - lowrisc:prim:assert + files: + - pwrmgr_rstmgr_sva_if.sv + file_type: systemVerilogSource + +targets: + default: + filesets: + - files_dv diff --git a/src/pwrmgr/dv/sva/pwrmgr_rstmgr_sva_if.sv b/src/pwrmgr/dv/sva/pwrmgr_rstmgr_sva_if.sv new file mode 100644 index 0000000..1249991 --- /dev/null +++ b/src/pwrmgr/dv/sva/pwrmgr_rstmgr_sva_if.sv @@ -0,0 +1,49 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This has some assertions that check the inputs from rstmgr react according to +// the pwrmgr outputs. The rstmgr inputs are generated by the base sequences, but +// these assertions will also be useful at full chip level. +interface pwrmgr_rstmgr_sva_if + import pwrmgr_pkg::*, pwrmgr_reg_pkg::*; +( + input logic clk_i, + input logic rst_ni, + input logic clk_slow_i, + input logic rst_slow_ni, + + // The inputs from pwrmgr. + input logic [PowerDomains-1:0] rst_lc_req, + input logic [PowerDomains-1:0] rst_sys_req, + + // The inputs from rstmgr. + input logic [PowerDomains-1:0] rst_lc_src_n, + input logic [PowerDomains-1:0] rst_sys_src_n +); + + // Number of cycles for the LC/SYS reset handshake. + localparam int MIN_LC_SYS_CYCLES = 0; + localparam int MAX_LC_SYS_CYCLES = 150; + `define LC_SYS_CYCLES ##[MIN_LC_SYS_CYCLES:MAX_LC_SYS_CYCLES] + + bit disable_sva; + bit reset_or_disable; + + always_comb reset_or_disable = !rst_slow_ni || disable_sva; + + // Lc and Sys handshake: pwrmgr rst_*_req causes rstmgr rst_*_src_n + for (genvar pd = 0; pd < PowerDomains; ++pd) begin : gen_assertions_per_power_domains + `ASSERT(LcHandshakeOn_A, rst_lc_req[pd] |-> `LC_SYS_CYCLES !rst_lc_req[pd] || !rst_lc_src_n[pd], + clk_i, reset_or_disable) + `ASSERT(LcHandshakeOff_A, $fell(rst_lc_req[pd]) + |-> `LC_SYS_CYCLES rst_lc_req[pd] || rst_lc_src_n[pd], clk_i, reset_or_disable) + `ASSERT(SysHandshakeOn_A, + rst_sys_req[pd] |-> `LC_SYS_CYCLES !rst_sys_req[pd] || !rst_sys_src_n[pd], clk_i, + reset_or_disable) + `ASSERT(SysHandshakeOff_A, + !rst_sys_req[pd] |-> `LC_SYS_CYCLES rst_sys_req[pd] || rst_sys_src_n[pd], clk_i, + reset_or_disable) + end : gen_assertions_per_power_domains + `undef LC_SYS_CYCLES +endinterface diff --git a/src/pwrmgr/dv/sva/pwrmgr_rstreqs_sva_if.sv b/src/pwrmgr/dv/sva/pwrmgr_rstreqs_sva_if.sv new file mode 100644 index 0000000..2da3043 --- /dev/null +++ b/src/pwrmgr/dv/sva/pwrmgr_rstreqs_sva_if.sv @@ -0,0 +1,102 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This has some assertions that check the pwrmgr rstreqs and reset_cause output is set per the +// reset requests the pwrmgr receives or generates. +interface pwrmgr_rstreqs_sva_if + import pwrmgr_pkg::*, pwrmgr_reg_pkg::*; +( + input logic clk_i, + input logic rst_ni, + input logic clk_slow_i, + input logic rst_slow_ni, + + // Input causes resets. + input logic [ NumRstReqs-1:0] rstreqs_i, + input logic [ NumRstReqs-1:0] reset_en, + input logic sw_rst_req_i, + input logic main_rst_req_i, + input logic esc_rst_req_i, + input logic ndm_rst_req_i, + // outputs + input logic main_pd_n, + input reset_cause_e reset_cause, + input logic [HwResetWidth-1:0] rstreqs +); + + // output reset cycle with a clk enable disable + localparam int MIN_MAIN_RST_CYCLES = 0; + localparam int MAX_MAIN_RST_CYCLES = 400; + `define MAIN_RST_CYCLES ##[MIN_MAIN_RST_CYCLES:MAX_MAIN_RST_CYCLES] + + // The timing of the escalation reset is determined by the slow clock, but will not propagate if + // the non-slow clock is off. We use the regular clock and multiply the clock cycles times the + // clock ratio. + localparam int FAST_TO_SLOW_FREQ_RATIO = 120; + + localparam int MIN_ESC_RST_CYCLES = 0; + localparam int MAX_ESC_RST_CYCLES = 4 * FAST_TO_SLOW_FREQ_RATIO; + `define ESC_RST_CYCLES ##[MIN_ESC_RST_CYCLES:MAX_ESC_RST_CYCLES] + + bit disable_sva; + bit reset_or_disable; + + always_comb reset_or_disable = !rst_ni || !rst_slow_ni || disable_sva; + + // Reset ins to outs. + for (genvar rst = 0; rst < NumRstReqs; ++rst) begin : gen_hw_resets + `ASSERT(HwResetOn_A, + $rose( + rstreqs_i[rst] && reset_en[rst] + ) |-> `MAIN_RST_CYCLES rstreqs[rst] && reset_cause == HwReq, clk_slow_i, + reset_or_disable) + `ASSERT(HwResetOff_A, + $fell( + rstreqs_i[rst] && reset_en[rst] + ) |-> `MAIN_RST_CYCLES !rstreqs[rst] && reset_cause != HwReq, clk_slow_i, + reset_or_disable) + end + + // This is used to ignore main_rst_req_i (wired to rst_main_n) if it happens during low power, + // since as part of deep sleep rst_main_n will trigger and not because of a power glitch. + logic rst_main_n_ignored_for_main_pwr_rst; + always_ff @(posedge clk_slow_i or negedge rst_slow_ni) begin + if (!rst_slow_ni) begin + rst_main_n_ignored_for_main_pwr_rst <= 0; + end else if (!main_pd_n && reset_cause == LowPwrEntry) begin + rst_main_n_ignored_for_main_pwr_rst <= 1; + end else if (reset_cause != LowPwrEntry) begin + rst_main_n_ignored_for_main_pwr_rst <= 0; + end + end + + `ASSERT(MainPwrRstOn_A, + $rose( + main_rst_req_i && !rst_main_n_ignored_for_main_pwr_rst + ) |-> `MAIN_RST_CYCLES rstreqs[ResetMainPwrIdx], clk_slow_i, + reset_or_disable) + `ASSERT(MainPwrRstOff_A, + $fell( + main_rst_req_i + ) |-> `MAIN_RST_CYCLES !rstreqs[ResetMainPwrIdx], clk_slow_i, + reset_or_disable) + + // Signals in EscRstOn_A and EscRstOff_A are sampled with slow and fast clock. + // Since fast clock can be gated, use fast clock to evaluate cycle delay + // to avoid spurious failure. + `ASSERT(EscRstOn_A, + $rose( + esc_rst_req_i + ) |-> `ESC_RST_CYCLES rstreqs[ResetEscIdx], clk_i, reset_or_disable) + `ASSERT(EscRstOff_A, + $fell( + esc_rst_req_i + ) |-> `ESC_RST_CYCLES !rstreqs[ResetEscIdx], clk_i, reset_or_disable) + + // Software initiated resets do not affect rstreqs since rstmgr generates them. + `ASSERT(SwResetSetCause_A, + $rose(sw_rst_req_i) |-> MAIN_RST_CYCLES (reset_cause == HwReq), clk_i, + reset_or_disable) + +endinterface diff --git a/src/pwrmgr/dv/sva/pwrmgr_sec_cm_checker_assert.sv b/src/pwrmgr/dv/sva/pwrmgr_sec_cm_checker_assert.sv new file mode 100644 index 0000000..2ecefb6 --- /dev/null +++ b/src/pwrmgr/dv/sva/pwrmgr_sec_cm_checker_assert.sv @@ -0,0 +1,132 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// add description here TBD +module pwrmgr_sec_cm_checker_assert + import pwrmgr_reg_pkg::*; +( + input clk_i, + input rst_ni, + input clk_lc_i, + input rst_lc_ni, + input clk_esc_i, + input rst_esc_ni, + input rst_main_ni, + input clk_slow_i, + input rst_slow_ni, + input pwrmgr_pkg::pwr_rst_req_t pwr_rst_o, + input slow_fsm_invalid, + input fast_fsm_invalid, + input prim_mubi_pkg::mubi4_t rom_intg_chk_dis, + input prim_mubi_pkg::mubi4_t rom_intg_chk_done, + input prim_mubi_pkg::mubi4_t rom_intg_chk_good, + input pwrmgr_pkg::fast_pwr_state_e fast_state, + input lc_ctrl_pkg::lc_tx_t lc_dft_en_i, + input lc_ctrl_pkg::lc_tx_t lc_hw_debug_en_i, + input slow_esc_rst_req, + input slow_mp_rst_req, + input main_pd_ni, + input prim_mubi_pkg::mubi4_t rom_ctrl_done_i, + input prim_mubi_pkg::mubi4_t rom_ctrl_good_i +); + + bit disable_sva; + bit reset_or_disable; + bit esc_reset_or_disable; + bit slow_reset_or_disable; + + always_comb reset_or_disable = !rst_ni || disable_sva; + always_comb esc_reset_or_disable = !rst_esc_ni || disable_sva; + always_comb slow_reset_or_disable = !rst_slow_ni || disable_sva; + + // rom_intg_chk_dis only allows two states. + // Note that lc_dft_en_i and lc_hw_debug_en_i are already synchronized to clk_i at this + // hierarchy level. + `ASSERT(RomIntgChkDisTrue_A, + rom_intg_chk_dis == prim_mubi_pkg::MuBi4True |-> + (lc_dft_en_i == lc_ctrl_pkg::On && + lc_hw_debug_en_i == lc_ctrl_pkg::On), + clk_i, + reset_or_disable) + + `ASSERT(RomIntgChkDisFalse_A, + rom_intg_chk_dis == prim_mubi_pkg::MuBi4False |-> + (lc_dft_en_i !== lc_ctrl_pkg::On || + lc_hw_debug_en_i !== lc_ctrl_pkg::On), + clk_i, + reset_or_disable) + + // For any assertions involving state transitions, also allow cases where the fsm + // transitions to an invalid state, since we inject invalid encodings at random. + + // Check that unless rom_intg_chk_done is mubi true the fast state machine will + // stay in FastPwrStateRomCheckDone. + `ASSERT(RomBlockCheckGoodState_A, + rom_intg_chk_done != prim_mubi_pkg::MuBi4True && + fast_state == pwrmgr_pkg::FastPwrStateRomCheckDone |=> + fast_state == pwrmgr_pkg::FastPwrStateRomCheckDone || + fast_state == pwrmgr_pkg::FastPwrStateInvalid, + clk_i, + reset_or_disable) + + `ASSERT(RomAllowCheckGoodState_A, + rom_intg_chk_done == prim_mubi_pkg::MuBi4True && + fast_state == pwrmgr_pkg::FastPwrStateRomCheckDone |=> + fast_state == pwrmgr_pkg::FastPwrStateRomCheckGood || + fast_state == pwrmgr_pkg::FastPwrStateInvalid, + clk_i, + reset_or_disable) + + // Check that unless rom_intg_chk_good is mubi true or rom_intg_chk_dis is mubi true + // the fast state machine will stay in FastPwrStateRomCheckGood. + `ASSERT(RomBlockActiveState_A, + rom_intg_chk_good != prim_mubi_pkg::MuBi4True && + rom_intg_chk_dis != prim_mubi_pkg::MuBi4True && + fast_state == pwrmgr_pkg::FastPwrStateRomCheckGood |=> + fast_state == pwrmgr_pkg::FastPwrStateRomCheckGood || + fast_state == pwrmgr_pkg::FastPwrStateInvalid, + clk_i, + reset_or_disable) + + `ASSERT(RomAllowActiveState_A, + (rom_intg_chk_good == prim_mubi_pkg::MuBi4True || + rom_intg_chk_dis == prim_mubi_pkg::MuBi4True) && + fast_state == pwrmgr_pkg::FastPwrStateRomCheckGood |=> + fast_state == pwrmgr_pkg::FastPwrStateActive || + fast_state == pwrmgr_pkg::FastPwrStateInvalid, + clk_i, + reset_or_disable) + + // pwr_rst_o.rstreqs checker + // sec_cm_esc_rx_clk_bkgn_chk, sec_cm_esc_rx_clk_local_esc + // if esc_timeout, rstreqs[ResetEscIdx] should be asserted + `ASSERT(RstreqChkEsctimeout_A, + $rose( + slow_esc_rst_req + ) ##1 slow_esc_rst_req |-> ##[0:10] pwr_rst_o.rstreqs[ResetEscIdx], + clk_i, reset_or_disable) + +// sec_cm_fsm_terminal +// if slow_fsm or fast_fsm is invalid, +// both pwr_rst_o.rst_lc_req and pwr_rst_o.rst_sys_req should be set + + `ASSERT(RstreqChkFsmterm_A, + $rose(slow_fsm_invalid) || $rose(fast_fsm_invalid) + |-> ##[0:10] $rose(pwr_rst_o.rst_lc_req & pwr_rst_o.rst_sys_req), + clk_i, reset_or_disable) + +// sec_cm_ctrl_flow_global_esc +// if esc_rst_req is set, pwr_rst_o.rstreqs[ResetEscIdx] should be asserted. + `ASSERT(RstreqChkGlbesc_A, + $rose(slow_esc_rst_req) ##1 slow_esc_rst_req |-> + ##[0:10] (pwr_rst_o.rstreqs[ResetEscIdx] | !rst_esc_ni), + clk_i, reset_or_disable) + +// sec_cm_main_pd_rst_local_esc +// if power is up and rst_main_ni goes low, pwr_rst_o.rstreqs[ResetMainPwrIdx] should be asserted + `ASSERT(RstreqChkMainpd_A, + slow_mp_rst_req |-> ##[0:5] pwr_rst_o.rstreqs[ResetMainPwrIdx], clk_i, + reset_or_disable) + +endmodule // pwrmgr_sec_cm_checker_assert diff --git a/src/pwrmgr/dv/sva/pwrmgr_sva.core b/src/pwrmgr/dv/sva/pwrmgr_sva.core new file mode 100644 index 0000000..b5fbadc --- /dev/null +++ b/src/pwrmgr/dv/sva/pwrmgr_sva.core @@ -0,0 +1,43 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:dv:pwrmgr_sva:0.1" +description: "PWRMGR assertion modules and bind file." +filesets: + files_dv: + depend: + - lowrisc:tlul:headers + - lowrisc:fpv:csr_assert_gen + - lowrisc:ip_interfaces:pwrmgr_pkg + - lowrisc:dv:clkmgr_pwrmgr_sva_if + - lowrisc:dv:pwrmgr_rstmgr_sva_if + files: + - pwrmgr_bind.sv + - pwrmgr_clock_enables_sva_if.sv + - pwrmgr_rstreqs_sva_if.sv + - pwrmgr_sec_cm_checker_assert.sv + file_type: systemVerilogSource + + files_formal: + depend: + - lowrisc:ip_interfaces:pwrmgr + +generate: + csr_assert_gen: + generator: csr_assert_gen + parameters: + spec: ../../data/pwrmgr.hjson + +targets: + default: &default_target + filesets: + - files_dv + generate: + - csr_assert_gen + formal: + <<: *default_target + filesets: + - files_formal + - files_dv + toplevel: pwrmgr diff --git a/src/pwrmgr/dv/tb.sv b/src/pwrmgr/dv/tb.sv new file mode 100644 index 0000000..ab83adf --- /dev/null +++ b/src/pwrmgr/dv/tb.sv @@ -0,0 +1,140 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +module tb; + // dep packages + import uvm_pkg::*; + import dv_utils_pkg::*; + import pwrmgr_env_pkg::*; + import pwrmgr_test_pkg::*; + + // macro includes + `include "uvm_macros.svh" + `include "dv_macros.svh" + + wire clk, rst_n; + wire clk_esc, rst_esc_n; + wire clk_lc, rst_lc_n; + wire clk_slow, rst_slow_n; + wire [NUM_MAX_INTERRUPTS-1:0] interrupts; + + // interfaces + clk_rst_if clk_rst_if ( + .clk (clk), + .rst_n(rst_n) + ); + clk_rst_if lc_clk_rst_if ( + .clk (clk_lc), + .rst_n(rst_lc_n) + ); + clk_rst_if esc_clk_rst_if ( + .clk (clk_esc), + .rst_n(rst_esc_n) + ); + clk_rst_if slow_clk_rst_if ( + .clk (clk_slow), + .rst_n(rst_slow_n) + ); + pins_if #(NUM_MAX_INTERRUPTS) intr_if (interrupts); + alert_esc_if esc_if ( + .clk (clk), + .rst_n(rst_n) + ); + tl_if tl_if ( + .clk (clk), + .rst_n(rst_n) + ); + + assign interrupts[0] = pwrmgr_if.intr_wakeup; + + pwrmgr_if pwrmgr_if ( + .clk, + .rst_n, + .clk_slow, + .rst_slow_n + ); + + `DV_ALERT_IF_CONNECT(clk_lc, rst_lc_n) + + // dut + pwrmgr dut ( + .clk_i (clk), + .rst_ni (rst_n), + .clk_slow_i (clk_slow), + .rst_slow_ni(rst_slow_n), + .rst_main_ni(pwrmgr_if.rst_main_n), + .clk_lc_i (clk_lc), + .rst_lc_ni (rst_lc_n), + .clk_esc_i (clk_esc), + .rst_esc_ni (rst_esc_n), + + .tl_i(tl_if.h2d), + .tl_o(tl_if.d2h), + + .alert_rx_i(alert_rx), + .alert_tx_o(alert_tx), + + .pwr_ast_i(pwrmgr_if.pwr_ast_rsp), + .pwr_ast_o(pwrmgr_if.pwr_ast_req), + + .pwr_rst_i(pwrmgr_if.pwr_rst_rsp), + .pwr_rst_o(pwrmgr_if.pwr_rst_req), + + .pwr_clk_i(pwrmgr_if.pwr_clk_rsp), + .pwr_clk_o(pwrmgr_if.pwr_clk_req), + + .pwr_otp_i(pwrmgr_if.pwr_otp_rsp), + .pwr_otp_o(pwrmgr_if.pwr_otp_req), + + .pwr_lc_i(pwrmgr_if.pwr_lc_rsp), + .pwr_lc_o(pwrmgr_if.pwr_lc_req), + + .pwr_flash_i(pwrmgr_if.pwr_flash), + .pwr_cpu_i (pwrmgr_if.pwr_cpu), + + .fetch_en_o(pwrmgr_if.fetch_en), + .wakeups_i (pwrmgr_if.wakeups_i), + .rstreqs_i (pwrmgr_if.rstreqs_i), + .ndmreset_req_i(pwrmgr_if.cpu_i.ndmreset_req), + + .lc_dft_en_i (pwrmgr_if.lc_dft_en), + .lc_hw_debug_en_i(pwrmgr_if.lc_hw_debug_en), + + .strap_o (pwrmgr_if.strap), + .low_power_o(pwrmgr_if.low_power), + + .rom_ctrl_i(pwrmgr_if.rom_ctrl), + + .sw_rst_req_i(pwrmgr_if.sw_rst_req_i), + + .esc_rst_tx_i(esc_if.esc_tx), + .esc_rst_rx_o(esc_if.esc_rx), + + .intr_wakeup_o(pwrmgr_if.intr_wakeup) + ); + + initial begin + // drive clk and rst_n from clk_if + clk_rst_if.set_active(); + esc_clk_rst_if.set_active(); + lc_clk_rst_if.set_active(); + slow_clk_rst_if.set_active(); + + uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "clk_rst_vif", clk_rst_if); + uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "esc_clk_rst_vif", esc_clk_rst_if); + uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "lc_clk_rst_vif", lc_clk_rst_if); + uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "slow_clk_rst_vif", slow_clk_rst_if); + uvm_config_db#(intr_vif)::set(null, "*.env", "intr_vif", intr_if); + uvm_config_db#(virtual alert_esc_if)::set(null, "*.env.m_esc_agent*", "vif", esc_if); + uvm_config_db#(virtual pwrmgr_if)::set(null, "*.env", "pwrmgr_vif", pwrmgr_if); + uvm_config_db#(virtual tl_if)::set(null, "*.env.m_tl_agent*", "vif", tl_if); + uvm_config_db#(virtual pwrmgr_clock_enables_sva_if)::set( + null, "*.env", "pwrmgr_clock_enables_sva_vif", dut.pwrmgr_clock_enables_sva_if); + uvm_config_db#(virtual pwrmgr_rstmgr_sva_if)::set(null, "*.env", "pwrmgr_rstmgr_sva_vif", + dut.pwrmgr_rstmgr_sva_if); + $timeformat(-12, 0, " ps", 12); + run_test(); + end // initial begin + +endmodule diff --git a/src/pwrmgr/dv/tests/pwrmgr_base_test.sv b/src/pwrmgr/dv/tests/pwrmgr_base_test.sv new file mode 100644 index 0000000..0432cfc --- /dev/null +++ b/src/pwrmgr/dv/tests/pwrmgr_base_test.sv @@ -0,0 +1,20 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class pwrmgr_base_test extends cip_base_test #( + .CFG_T(pwrmgr_env_cfg), + .ENV_T(pwrmgr_env) +); + + `uvm_component_utils(pwrmgr_base_test) + `uvm_component_new + + // the base class dv_base_test creates the following instances: + // pwrmgr_env_cfg: cfg + // pwrmgr_env: env + + // the base class also looks up UVM_TEST_SEQ plusarg to create and run that seq in + // the run_phase; as such, nothing more needs to be done + +endclass : pwrmgr_base_test diff --git a/src/pwrmgr/dv/tests/pwrmgr_test.core b/src/pwrmgr/dv/tests/pwrmgr_test.core new file mode 100644 index 0000000..bf79e44 --- /dev/null +++ b/src/pwrmgr/dv/tests/pwrmgr_test.core @@ -0,0 +1,19 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:dv:pwrmgr_test:0.1" +description: "PWRMGR DV UVM test" +filesets: + files_dv: + depend: + - lowrisc:dv:pwrmgr_env + files: + - pwrmgr_test_pkg.sv + - pwrmgr_base_test.sv: {is_include_file: true} + file_type: systemVerilogSource + +targets: + default: + filesets: + - files_dv diff --git a/src/pwrmgr/dv/tests/pwrmgr_test_pkg.sv b/src/pwrmgr/dv/tests/pwrmgr_test_pkg.sv new file mode 100644 index 0000000..afbd194 --- /dev/null +++ b/src/pwrmgr/dv/tests/pwrmgr_test_pkg.sv @@ -0,0 +1,22 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +package pwrmgr_test_pkg; + // dep packages + import uvm_pkg::*; + import cip_base_pkg::*; + import pwrmgr_env_pkg::*; + + // macro includes + `include "uvm_macros.svh" + `include "dv_macros.svh" + + // local types + + // functions + + // package sources + `include "pwrmgr_base_test.sv" + +endpackage diff --git a/src/pwrmgr/lint/pwrmgr.vlt b/src/pwrmgr/lint/pwrmgr.vlt new file mode 100644 index 0000000..a38de16 --- /dev/null +++ b/src/pwrmgr/lint/pwrmgr.vlt @@ -0,0 +1,5 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// waiver file for Power Manager diff --git a/src/pwrmgr/lint/pwrmgr.waiver b/src/pwrmgr/lint/pwrmgr.waiver new file mode 100644 index 0000000..75aee6c --- /dev/null +++ b/src/pwrmgr/lint/pwrmgr.waiver @@ -0,0 +1,5 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# waiver file for Power Manager diff --git a/src/pwrmgr/lint/pwrmgr_pkg.vlt b/src/pwrmgr/lint/pwrmgr_pkg.vlt new file mode 100644 index 0000000..a5949a2 --- /dev/null +++ b/src/pwrmgr/lint/pwrmgr_pkg.vlt @@ -0,0 +1,12 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// waiver file for the pwrmgr_pkg + +`verilator_config + +// Waive the SYMRSVDWORD warning in pwrmgr_reg_pkg: we have a field in +// the WAKE_INFO register called "abort", which means pwrmgr_reg_pkg +// defines a struct with that name, clashing with a C++ reserved word. +lint_off -rule SYMRSVDWORD -file "*/pwrmgr_reg_pkg.sv" -match "*common word: 'abort'" diff --git a/src/pwrmgr/pwrmgr.core.tpl b/src/pwrmgr/pwrmgr.core.tpl new file mode 100644 index 0000000..be5aa37 --- /dev/null +++ b/src/pwrmgr/pwrmgr.core.tpl @@ -0,0 +1,66 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: ${instance_vlnv("lowrisc:ip:pwrmgr:0.1")} +description: "Power manager RTL" +virtual: + - lowrisc:ip_interfaces:pwrmgr + +filesets: + files_rtl: + depend: + - ${instance_vlnv("lowrisc:ip:pwrmgr_pkg:0.1")} + - ${instance_vlnv("lowrisc:ip:pwrmgr_reg:0.1")} + - lowrisc:ip:pwrmgr_component + file_type: systemVerilogSource + + files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + files: + - lint/pwrmgr.vlt + file_type: vlt + + files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + files: + - lint/pwrmgr.waiver + file_type: waiver + + files_veriblelint_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + +parameters: + SYNTHESIS: + datatype: bool + paramtype: vlogdefine + + +targets: + default: &default_target + filesets: + - tool_verilator ? (files_verilator_waiver) + - tool_ascentlint ? (files_ascentlint_waiver) + - tool_veriblelint ? (files_veriblelint_waiver) + - files_rtl + toplevel: pwrmgr + + lint: + <<: *default_target + default_tool: verilator + parameters: + - SYNTHESIS=true + tools: + verilator: + mode: lint-only + verilator_options: + - "-Wall" diff --git a/src/pwrmgr/pwrmgr_components.core b/src/pwrmgr/pwrmgr_components.core new file mode 100644 index 0000000..bf144fe --- /dev/null +++ b/src/pwrmgr/pwrmgr_components.core @@ -0,0 +1,80 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:ip:pwrmgr_component:0.1" +description: "Power manager RTL" + +filesets: + files_rtl: + depend: + - lowrisc:ip:tlul + - lowrisc:prim:esc + - lowrisc:prim:lc_sync + - lowrisc:prim:lc_sender + - lowrisc:prim:all + - lowrisc:ip:rom_ctrl_pkg + - lowrisc:ip:lc_ctrl_pkg + - lowrisc:prim:sparse_fsm + - lowrisc:prim:mubi + - lowrisc:prim:clock_buf + - lowrisc:prim:measure + - lowrisc:ip_interfaces:alert_handler_reg + - lowrisc:ip_interfaces:pwrmgr_pkg + files: + - rtl/pwrmgr_cdc.sv + - rtl/pwrmgr_slow_fsm.sv + - rtl/pwrmgr_fsm.sv + - rtl/pwrmgr_wake_info.sv + - rtl/pwrmgr.sv + file_type: systemVerilogSource + + files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + files: + - lint/pwrmgr.vlt + file_type: vlt + + files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + files: + - lint/pwrmgr.waiver + file_type: waiver + + files_veriblelint_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + +parameters: + SYNTHESIS: + datatype: bool + paramtype: vlogdefine + + +targets: + default: &default_target + filesets: + - tool_verilator ? (files_verilator_waiver) + - tool_ascentlint ? (files_ascentlint_waiver) + - tool_veriblelint ? (files_veriblelint_waiver) + - files_rtl + toplevel: pwrmgr + + lint: + <<: *default_target + default_tool: verilator + parameters: + - SYNTHESIS=true + tools: + verilator: + mode: lint-only + verilator_options: + - "-Wall" diff --git a/src/pwrmgr/pwrmgr_pkg.core.tpl b/src/pwrmgr/pwrmgr_pkg.core.tpl new file mode 100644 index 0000000..42012fa --- /dev/null +++ b/src/pwrmgr/pwrmgr_pkg.core.tpl @@ -0,0 +1,31 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: ${instance_vlnv("lowrisc:ip:pwrmgr_pkg:0.1")} +description: "Power manager package" +virtual: + - lowrisc:ip_interfaces:pwrmgr_pkg + +filesets: + files_rtl: + depend: + - ${instance_vlnv("lowrisc:ip:pwrmgr_reg")} + files: + - rtl/pwrmgr_pkg.sv + file_type: systemVerilogSource + + files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + files: + - lint/pwrmgr_pkg.vlt + file_type: vlt + +targets: + default: + filesets: + - tool_verilator ? (files_verilator_waiver) + - files_rtl diff --git a/src/pwrmgr/pwrmgr_reg.core.tpl b/src/pwrmgr/pwrmgr_reg.core.tpl new file mode 100644 index 0000000..886a9c9 --- /dev/null +++ b/src/pwrmgr/pwrmgr_reg.core.tpl @@ -0,0 +1,24 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: ${instance_vlnv("lowrisc:ip:pwrmgr_reg:0.1")} +description: "Power manager registers" +virtual: + - lowrisc:ip_interfaces:pwrmgr_reg + +filesets: + files_rtl: + depend: + - lowrisc:tlul:headers + - lowrisc:ip:tlul + - lowrisc:prim:subreg + files: + - rtl/pwrmgr_reg_pkg.sv + - rtl/pwrmgr_reg_top.sv + file_type: systemVerilogSource + +targets: + default: + filesets: + - files_rtl diff --git a/src/pwrmgr/rtl/pwrmgr.sv b/src/pwrmgr/rtl/pwrmgr.sv new file mode 100644 index 0000000..302697c --- /dev/null +++ b/src/pwrmgr/rtl/pwrmgr.sv @@ -0,0 +1,737 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Power Manager +// + +`include "prim_assert.sv" + +module pwrmgr + import pwrmgr_pkg::*; + import pwrmgr_reg_pkg::*; +#( + parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}} +) ( + // Clocks and resets + input clk_slow_i, + input clk_i, + input rst_slow_ni, + input rst_ni, + input rst_main_ni, + input clk_caliptra_ss_lc_i, + input rst_caliptra_ss_lc_ni, + input clk_esc_i, + input rst_esc_ni, + + // Bus Interface + input tlul_pkg::tl_h2d_t tl_i, + output tlul_pkg::tl_d2h_t tl_o, + + // Alerts + input prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i, + output prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o, + + // AST interface + input pwr_ast_rsp_t pwr_ast_i, + output pwr_ast_req_t pwr_ast_o, + + // rstmgr interface + input pwr_rst_rsp_t pwr_rst_i, + output pwr_rst_req_t pwr_rst_o, + + // clkmgr interface + output pwr_clk_req_t pwr_clk_o, + input pwr_clk_rsp_t pwr_clk_i, + + // otp interface + input pwr_otp_rsp_t pwr_otp_i, + output pwr_otp_req_t pwr_otp_o, + + // life cycle interface + input pwr_caliptra_ss_lc_rsp_t pwr_caliptra_ss_lc_i, + output pwr_caliptra_ss_lc_req_t pwr_caliptra_ss_lc_o, + + // flash interface + input pwr_flash_t pwr_flash_i, + + // processor interface + input pwr_cpu_t pwr_cpu_i, + // SEC_CM: LC_CTRL.INTERSIG.MUBI + output caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_t fetch_en_o, + input caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_t caliptra_ss_lc_hw_debug_en_i, + input caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_t caliptra_ss_lc_dft_en_i, + + // peripherals wakeup and reset requests + input [NumWkups-1:0] wakeups_i, + input [NumRstReqs-1:0] rstreqs_i, + + // cpu related inputs + input ndmreset_req_i, + + // pinmux and other peripherals + output logic strap_o, + output logic low_power_o, + + // rom_ctrl interface + // SEC_CM: ROM_CTRL.INTERSIG.MUBI + input rom_ctrl_pkg::pwrmgr_data_t rom_ctrl_i, + + // software issued reset request + // SEC_CM: RSTMGR.INTERSIG.MUBI + input prim_mubi_pkg::mubi4_t sw_rst_req_i, + + // escalation interface + input prim_esc_pkg::esc_tx_t esc_rst_tx_i, + output prim_esc_pkg::esc_rx_t esc_rst_rx_o, + + output intr_wakeup_o + +); + //////////////////////////////////////////////////// + // Input handling // + //////////////////////////////////////////////////// + + logic ndmreset_req_q; + logic ndm_req_valid; + + prim_flop_2sync #( + .Width(1), + .ResetValue('0) + ) u_ndm_sync ( + .clk_i, + .rst_ni, + .d_i(ndmreset_req_i), + .q_o(ndmreset_req_q) + ); + + assign ndm_req_valid = ndmreset_req_q; + + //////////////////////////// + /// escalation detections + //////////////////////////// + + logic clk_lc; + logic rst_caliptra_ss_lc_n; + assign clk_lc = clk_caliptra_ss_lc_i; + assign rst_caliptra_ss_lc_n = rst_caliptra_ss_lc_ni; + + logic clk_esc; + logic rst_esc_n; + prim_clock_buf #( + .NoFpgaBuf(1'b1) + ) u_esc_clk_buf ( + .clk_i(clk_esc_i), + .clk_o(clk_esc) + ); + + prim_clock_buf #( + .NoFpgaBuf(1'b1) + ) u_esc_rst_buf ( + .clk_i(rst_esc_ni), + .clk_o(rst_esc_n) + ); + + logic esc_rst_req_d, esc_rst_req_q; + prim_esc_receiver #( + .N_ESC_SEV (alert_handler_reg_pkg::N_ESC_SEV), + .PING_CNT_DW (alert_handler_reg_pkg::PING_CNT_DW) + ) u_esc_rx ( + .clk_i(clk_esc), + .rst_ni(rst_esc_n), + .esc_req_o(esc_rst_req_d), + .esc_rx_o(esc_rst_rx_o), + .esc_tx_i(esc_rst_tx_i) + ); + + // These assertions use formal or simulation to prove that once esc_rst_req is latched, we expect + // to see the lc reset requests in pwr_rst_o. The one exception is when escalation requests are + // cancelled while the CPU fetch is disabled, meaning the fast fsm is inactive. +`ifdef SIMULATION + // In simulation mode, the prim_cdc_rand_delay module inserts a random one cycle delay to the + // two flop synchronizers. There are two CDCs in the path from escalation reset to the fast fsm + // receiving it, one to the slow clock, and one back to the fast one. And there are additional + // cycles in the fast fsm to generate outputs. However, esc_rst_req_q can be dropped due to + // rst_caliptra_ss_lc_n. + `ASSERT(PwrmgrSecCmEscToSlowResetReq_A, + esc_rst_req_q |-> ##[1:5] !esc_rst_req_q || slow_peri_reqs_masked.rstreqs[ResetEscIdx], + clk_slow_i, !rst_slow_ni) + `ASSERT(PwrmgrSecCmFsmEscToResetReq_A, + slow_peri_reqs_masked.rstreqs[ResetEscIdx] |-> ##[1:4] u_fsm.reset_reqs_i[ResetEscIdx], + clk_i, !rst_ni) +`else + `ASSERT(PwrmgrSecCmEscToSlowResetReq_A, + esc_rst_req_d |-> ##[2:3] ( + (!esc_rst_req_d && caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_test_false_loose(fetch_en_o)) || + slow_peri_reqs_masked.rstreqs[ResetEscIdx] + ), clk_slow_i, !rst_slow_ni) + `ASSERT(PwrmgrSlowResetReqToFsmResetReq_A, + slow_peri_reqs_masked.rstreqs[ResetEscIdx] |-> ##1 u_fsm.reset_reqs_i[ResetEscIdx], + clk_i, !rst_ni) +`endif + + `ASSERT(PwrmgrSecCmEscToLCReset_A, u_fsm.reset_reqs_i[ResetEscIdx] && + u_fsm.state_q == FastPwrStateActive |-> ##4 pwr_rst_o.rst_caliptra_ss_lc_req == 2'b11, + clk_i, !rst_ni) + + always_ff @(posedge clk_lc or negedge rst_caliptra_ss_lc_n) begin + if (!rst_caliptra_ss_lc_n) begin + esc_rst_req_q <= '0; + end else if (esc_rst_req_d) begin + // once latched, do not clear until reset + esc_rst_req_q <= 1'b1; + end + end + + localparam int EscTimeOutCnt = 128; + logic esc_timeout, esc_timeout_caliptra_ss_lc_d, esc_timeout_caliptra_ss_lc_q; + // SEC_CM: ESC_RX.CLK.BKGN_CHK, ESC_RX.CLK.LOCAL_ESC + prim_clock_timeout #( + .TimeOutCnt(EscTimeOutCnt) + ) u_esc_timeout ( + .clk_chk_i(clk_esc), + .rst_chk_ni(rst_esc_n), + .clk_i, + .rst_ni, + // if any ip clock enable is turned on, then the escalation + // clocks are also enabled. + .en_i(|pwr_clk_o), + .timeout_o(esc_timeout) + ); + + prim_flop_2sync #( + .Width(1), + .ResetValue('0) + ) u_esc_timeout_sync ( + .clk_i(clk_lc), + .rst_ni(rst_caliptra_ss_lc_n), + .d_i(esc_timeout), + .q_o(esc_timeout_caliptra_ss_lc_d) + ); + + always_ff @(posedge clk_lc or negedge rst_caliptra_ss_lc_n) begin + if (!rst_caliptra_ss_lc_n) begin + esc_timeout_caliptra_ss_lc_q <= '0; + end else if (esc_timeout_caliptra_ss_lc_d) begin + // once latched, do not clear until reset + esc_timeout_caliptra_ss_lc_q <= 1'b1; + end + end + + + //////////////////////////// + /// async declarations + //////////////////////////// + pwr_peri_t peri_reqs_raw; + logic slow_rst_req; + + assign peri_reqs_raw.wakeups = wakeups_i; + assign peri_reqs_raw.rstreqs[NumRstReqs-1:0] = rstreqs_i; + assign peri_reqs_raw.rstreqs[ResetMainPwrIdx] = slow_rst_req; + // SEC_CM: ESC_RX.CLK.LOCAL_ESC, CTRL_FLOW.GLOBAL_ESC + assign peri_reqs_raw.rstreqs[ResetEscIdx] = esc_rst_req_q | esc_timeout_caliptra_ss_lc_q; + assign peri_reqs_raw.rstreqs[ResetNdmIdx] = ndm_req_valid; + + //////////////////////////// + /// Software reset request + //////////////////////////// + logic sw_rst_req; + prim_buf #( + .Width(1) + ) u_sw_req_buf ( + .in_i(prim_mubi_pkg::mubi4_test_true_strict(sw_rst_req_i)), + .out_o(sw_rst_req) + ); + + assign peri_reqs_raw.rstreqs[ResetSwReqIdx] = sw_rst_req; + + //////////////////////////// + /// clk_i domain declarations + //////////////////////////// + + pwrmgr_reg2hw_t reg2hw; + pwrmgr_hw2reg_t hw2reg; + pwr_peri_t peri_reqs_masked; + + logic req_pwrup; + logic ack_pwrup; + logic req_pwrdn; + logic ack_pwrdn; + logic fsm_invalid; + logic clr_slow_req; + logic usb_ip_clk_en; + logic usb_ip_clk_status; + pwrup_cause_e pwrup_cause; + + logic low_power_fall_through; + logic low_power_abort; + + pwr_flash_t flash_rsp; + pwr_otp_rsp_t otp_rsp; + + prim_mubi_pkg::mubi4_t rom_ctrl_done; + prim_mubi_pkg::mubi4_t rom_ctrl_good; + + logic core_sleeping; + + //////////////////////////// + /// clk_slow_i domain declarations + //////////////////////////// + + // Captured signals + // These signals, though on clk_i domain, are safe for clk_slow_i to use + logic [NumWkups-1:0] slow_wakeup_en; + logic [NumRstReqs-1:0] slow_reset_en; + + pwr_ast_rsp_t slow_ast; + pwr_peri_t slow_peri_reqs, slow_peri_reqs_masked; + + pwrup_cause_e slow_pwrup_cause; + logic slow_pwrup_cause_toggle; + logic slow_req_pwrup; + logic slow_ack_pwrup; + logic slow_req_pwrdn; + logic slow_ack_pwrdn; + logic slow_fsm_invalid; + logic slow_main_pd_n; + logic slow_io_clk_en; + logic slow_core_clk_en; + logic slow_usb_clk_en_lp; + logic slow_usb_clk_en_active; + logic slow_clr_req; + logic slow_usb_ip_clk_en; + logic slow_usb_ip_clk_status; + + + + //////////////////////////// + /// Register module + //////////////////////////// + logic [NumAlerts-1:0] alert_test, alerts; + logic low_power_hint; + logic lowpwr_cfg_wen; + logic clr_hint; + logic wkup; + logic clr_cfg_lock; + logic reg_intg_err; + + // SEC_CM: BUS.INTEGRITY + // SEC_CM: CTRL.CONFIG.REGWEN, WAKEUP.CONFIG.REGWEN, RESET.CONFIG.REGWEN + pwrmgr_reg_top u_reg ( + .clk_i, + .rst_ni, + .clk_caliptra_ss_lc_i (clk_lc ), + .rst_caliptra_ss_lc_ni (rst_caliptra_ss_lc_n), + .tl_i, + .tl_o, + .reg2hw, + .hw2reg, + .intg_err_o (reg_intg_err) + ); + + // whenever low power entry begins, wipe the hint + assign hw2reg.control.low_power_hint.d = 1'b0; + assign hw2reg.control.low_power_hint.de = clr_hint; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + lowpwr_cfg_wen <= 1'b1; + end else if (!lowpwr_cfg_wen && (clr_cfg_lock || wkup)) begin + lowpwr_cfg_wen <= 1'b1; + end else if (low_power_hint) begin + lowpwr_cfg_wen <= 1'b0; + end + end + + assign hw2reg.ctrl_cfg_regwen.d = lowpwr_cfg_wen; + + assign hw2reg.fault_status.reg_intg_err.de = reg_intg_err; + assign hw2reg.fault_status.reg_intg_err.d = 1'b1; + assign hw2reg.fault_status.esc_timeout.de = esc_timeout_caliptra_ss_lc_q; + assign hw2reg.fault_status.esc_timeout.d = 1'b1; + + // The main power domain glitch automatically causes a reset, so regsitering + // an alert is functionally pointless. However, if an attacker somehow manages/ + // to silence the reset, this gives us one potential back-up path through alert_handler. + // Allow capture of main_pd fault status whenever the system is live. + assign hw2reg.fault_status.main_pd_glitch.de = pwr_clk_o.main_ip_clk_en; + assign hw2reg.fault_status.main_pd_glitch.d = peri_reqs_masked.rstreqs[ResetMainPwrIdx] | + reg2hw.fault_status.main_pd_glitch.q; + + `ASSERT(GlitchStatusPersist_A, $rose(reg2hw.fault_status.main_pd_glitch.q) |-> + reg2hw.fault_status.main_pd_glitch.q until !rst_caliptra_ss_lc_ni) + + //////////////////////////// + /// alerts + //////////////////////////// + + // the logic below assumes there is only one alert, so make an + // explicit assertion check for it. + `ASSERT_INIT(AlertNumCheck_A, NumAlerts == 1) + + assign alert_test = { + reg2hw.alert_test.q & + reg2hw.alert_test.qe + }; + + assign alerts[0] = reg2hw.fault_status.reg_intg_err.q | + reg2hw.fault_status.esc_timeout.q | + reg2hw.fault_status.main_pd_glitch.q; + + for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_tx + prim_alert_sender #( + .AsyncOn(AlertAsyncOn[i]), + .IsFatal(1'b1) + ) u_prim_alert_sender ( + .clk_i ( clk_lc ), + .rst_ni ( rst_caliptra_ss_lc_n ), + .alert_test_i ( alert_test[i] ), + .alert_req_i ( alerts[i] ), + .alert_ack_o ( ), + .alert_state_o ( ), + .alert_rx_i ( alert_rx_i[i] ), + .alert_tx_o ( alert_tx_o[i] ) + ); + end + + //////////////////////////// + /// cdc handling + //////////////////////////// + + pwrmgr_cdc u_cdc ( + .clk_i, + .rst_ni, + .clk_slow_i, + .rst_slow_ni, + + // slow domain signals + .slow_req_pwrup_i(slow_req_pwrup), + .slow_ack_pwrdn_i(slow_ack_pwrdn), + .slow_fsm_invalid_i(slow_fsm_invalid), + .slow_pwrup_cause_toggle_i(slow_pwrup_cause_toggle), + .slow_pwrup_cause_i(slow_pwrup_cause), + .slow_wakeup_en_o(slow_wakeup_en), + .slow_reset_en_o(slow_reset_en), + .slow_main_pd_no(slow_main_pd_n), + .slow_io_clk_en_o(slow_io_clk_en), + .slow_core_clk_en_o(slow_core_clk_en), + .slow_usb_clk_en_lp_o(slow_usb_clk_en_lp), + .slow_usb_clk_en_active_o(slow_usb_clk_en_active), + .slow_req_pwrdn_o(slow_req_pwrdn), + .slow_ack_pwrup_o(slow_ack_pwrup), + .slow_ast_o(slow_ast), + .slow_peri_reqs_o(slow_peri_reqs), + .slow_peri_reqs_masked_i(slow_peri_reqs_masked), + .slow_clr_req_o(slow_clr_req), + .slow_usb_ip_clk_en_i(slow_usb_ip_clk_en), + .slow_usb_ip_clk_status_o(slow_usb_ip_clk_status), + + // fast domain signals + .req_pwrdn_i(req_pwrdn), + .ack_pwrup_i(ack_pwrup), + .cfg_cdc_sync_i(reg2hw.cfg_cdc_sync.qe & reg2hw.cfg_cdc_sync.q), + .cdc_sync_done_o(hw2reg.cfg_cdc_sync.de), + .wakeup_en_i(reg2hw.wakeup_en), + .reset_en_i(reg2hw.reset_en), + .main_pd_ni(reg2hw.control.main_pd_n.q), + .io_clk_en_i(reg2hw.control.io_clk_en.q), + .core_clk_en_i(reg2hw.control.core_clk_en.q), + .usb_clk_en_lp_i(reg2hw.control.usb_clk_en_lp.q), + .usb_clk_en_active_i(reg2hw.control.usb_clk_en_active.q), + .ack_pwrdn_o(ack_pwrdn), + .fsm_invalid_o(fsm_invalid), + .req_pwrup_o(req_pwrup), + .pwrup_cause_o(pwrup_cause), + .peri_reqs_o(peri_reqs_masked), + .clr_slow_req_i(clr_slow_req), + .usb_ip_clk_en_o(usb_ip_clk_en), + .usb_ip_clk_status_i(usb_ip_clk_status), + + // AST signals + .ast_i(pwr_ast_i), + + // peripheral signals + .peri_i(peri_reqs_raw), + + // flash handshake + .flash_i(pwr_flash_i), + .flash_o(flash_rsp), + + // OTP signals + .otp_i(pwr_otp_i), + .otp_o(otp_rsp), + + // rom_ctrl signals + .rom_ctrl_done_i(rom_ctrl_i.done), + .rom_ctrl_done_o(rom_ctrl_done), + + // core sleeping + .core_sleeping_i(pwr_cpu_i.core_sleeping), + .core_sleeping_o(core_sleeping) + + ); + // rom_ctrl_i.good is not synchronized as it acts as a "payload" signal + // to "done". Good is only observed if "done" is high. + assign rom_ctrl_good = rom_ctrl_i.good; + assign hw2reg.cfg_cdc_sync.d = 1'b0; + + //////////////////////////// + /// Wakup and reset capture + //////////////////////////// + + // reset and wakeup requests are captured into the slow clock domain and then + // fanned out to other domains as necessary. This ensures there is not a huge + // time gap between when the slow clk domain sees the signal vs when the fast + // clock domains see it. This creates redundant syncing but keeps the time + // scale approximately the same across all domains. + // + // This also implies that these signals must be at least 1 clk_slow pulse long + // + // Since resets are not latched inside pwrmgr, there exists a corner case where + // non-always-on reset requests may get wiped out by a graceful low power entry + // It's not clear if this is really an issue at the moment, but something to keep + // in mind if future changes are needed. + // + // Latching the reset requests is not difficult, but the bigger question is who + // should clear it and when that should happen. If the clearing does not work + // correctly, it is possible for the device to end up in a permanent reset loop, + // and that would be very undesirable. + + assign slow_peri_reqs_masked.wakeups = slow_peri_reqs.wakeups & slow_wakeup_en; + // msb is software request + // the internal requests include escalation and internal requests + // the lsbs are the software enabled peripheral requests. + assign slow_peri_reqs_masked.rstreqs = slow_peri_reqs.rstreqs & + {{NumSwRstReq{1'b1}}, + {NumDebugRstReqs{1'b1}}, + {NumIntRstReqs{1'b1}}, + slow_reset_en}; + + for (genvar i = 0; i < NumWkups; i++) begin : gen_wakeup_status + assign hw2reg.wake_status[i].de = 1'b1; + assign hw2reg.wake_status[i].d = peri_reqs_masked.wakeups[i]; + end + + for (genvar i = 0; i < NumRstReqs; i++) begin : gen_reset_status + assign hw2reg.reset_status[i].de = 1'b1; + assign hw2reg.reset_status[i].d = peri_reqs_masked.rstreqs[i]; + end + + assign hw2reg.escalate_reset_status.de = 1'b1; + assign hw2reg.escalate_reset_status.d = peri_reqs_masked.rstreqs[NumRstReqs]; + + + //////////////////////////// + /// clk_slow FSM + //////////////////////////// + + pwrmgr_slow_fsm u_slow_fsm ( + .clk_i (clk_slow_i), + .rst_ni (rst_slow_ni), + .rst_main_ni (rst_main_ni), + .wakeup_i (|slow_peri_reqs_masked.wakeups), + .reset_req_i (|slow_peri_reqs_masked.rstreqs), + .ast_i (slow_ast), + .req_pwrup_o (slow_req_pwrup), + .pwrup_cause_o (slow_pwrup_cause), + .pwrup_cause_toggle_o (slow_pwrup_cause_toggle), + .ack_pwrup_i (slow_ack_pwrup), + .req_pwrdn_i (slow_req_pwrdn), + .ack_pwrdn_o (slow_ack_pwrdn), + .rst_req_o (slow_rst_req), + .fsm_invalid_o (slow_fsm_invalid), + .clr_req_i (slow_clr_req), + .usb_ip_clk_en_o (slow_usb_ip_clk_en), + .usb_ip_clk_status_i (slow_usb_ip_clk_status), + + .main_pd_ni (slow_main_pd_n), + .io_clk_en_i (slow_io_clk_en), + .core_clk_en_i (slow_core_clk_en), + .usb_clk_en_lp_i (slow_usb_clk_en_lp), + .usb_clk_en_active_i (slow_usb_clk_en_active), + + // outputs to AST - These are on the slow clock domain + // TBD - need to check this with partners + .ast_o (pwr_ast_o) + ); + + caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_t caliptra_ss_lc_dft_en; + prim_caliptra_ss_lc_sync u_prim_caliptra_ss_lc_sync_dft_en ( + .clk_i, + .rst_ni, + .caliptra_ss_lc_en_i(caliptra_ss_lc_dft_en_i), + .caliptra_ss_lc_en_o({caliptra_ss_lc_dft_en}) + ); + + caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_t caliptra_ss_lc_hw_debug_en; + prim_caliptra_ss_lc_sync u_prim_caliptra_ss_lc_sync_hw_debug_en ( + .clk_i, + .rst_ni, + .caliptra_ss_lc_en_i(caliptra_ss_lc_hw_debug_en_i), + .caliptra_ss_lc_en_o({caliptra_ss_lc_hw_debug_en}) + ); + + //////////////////////////// + /// clk FSM + //////////////////////////// + + assign low_power_hint = reg2hw.control.low_power_hint.q == LowPower; + + pwrmgr_fsm u_fsm ( + .clk_i, + .rst_ni, + .clk_slow_i, + .rst_slow_ni, + + // interface with slow_fsm + .req_pwrup_i (req_pwrup), + .pwrup_cause_i (pwrup_cause), // por, wake or reset request + .ack_pwrup_o (ack_pwrup), + .req_pwrdn_o (req_pwrdn), + .ack_pwrdn_i (ack_pwrdn), + .low_power_entry_i (core_sleeping & low_power_hint), + .reset_reqs_i (peri_reqs_masked.rstreqs), + .fsm_invalid_i (fsm_invalid), + .clr_slow_req_o (clr_slow_req), + .usb_ip_clk_en_i (usb_ip_clk_en), + .usb_ip_clk_status_o (usb_ip_clk_status), + + // cfg + .main_pd_ni (reg2hw.control.main_pd_n.q), + + // consumed in pwrmgr + .wkup_o (wkup), + .clr_cfg_lock_o (clr_cfg_lock), + .fall_through_o (low_power_fall_through), + .abort_o (low_power_abort), + .clr_hint_o (clr_hint), + + // rstmgr + .pwr_rst_o (pwr_rst_o), + .pwr_rst_i (pwr_rst_i), + + // clkmgr + .ips_clk_en_o (pwr_clk_o), + .clk_en_status_i (pwr_clk_i), + + // otp + .otp_init_o (pwr_otp_o.otp_init), + .otp_done_i (otp_rsp.otp_done), + .otp_idle_i (otp_rsp.otp_idle), + + // lc + .caliptra_ss_lc_init_o (pwr_caliptra_ss_lc_o.caliptra_ss_lc_init), + .caliptra_ss_lc_done_i (pwr_caliptra_ss_lc_i.caliptra_ss_lc_done), + .caliptra_ss_lc_idle_i (pwr_caliptra_ss_lc_i.caliptra_ss_lc_idle), + .caliptra_ss_lc_dft_en_i (caliptra_ss_lc_dft_en), + .caliptra_ss_lc_hw_debug_en_i (caliptra_ss_lc_hw_debug_en), + + // flash + .flash_idle_i (flash_rsp.flash_idle), + + // rom_ctrl + .rom_ctrl_done_i (rom_ctrl_done), + .rom_ctrl_good_i (rom_ctrl_good), + + // processing element + .fetch_en_o, + + // pinmux and other peripherals + .strap_o, + .low_power_o + ); + + //////////////////////////// + /// Wakeup Info Capture + //////////////////////////// + + logic wake_info_wen; + logic [TotalWakeWidth-1:0] wake_info_data; + + assign wake_info_wen = reg2hw.wake_info.abort.qe | + reg2hw.wake_info.fall_through.qe | + reg2hw.wake_info.reasons.qe; + + assign wake_info_data = {reg2hw.wake_info.abort.q, + reg2hw.wake_info.fall_through.q, + reg2hw.wake_info.reasons.q}; + + pwrmgr_wake_info i_wake_info ( + .clk_i, + .rst_ni, + .wr_i (wake_info_wen), + .data_i (wake_info_data), + .start_capture_i (low_power_o), + .record_dis_i (reg2hw.wake_info_capture_dis.q), + .wakeups_i (peri_reqs_masked.wakeups), + .fall_through_i (low_power_fall_through), + .abort_i (low_power_abort), + .info_o (hw2reg.wake_info) + ); + + //////////////////////////// + /// Interrupts + //////////////////////////// + + // This interrupt is asserted whenever the fast FSM transitions + // into active state. However, it does not assert during POR + prim_intr_hw #(.Width(1)) intr_wakeup ( + .clk_i, + .rst_ni, + .event_intr_i (wkup), + .reg2hw_intr_enable_q_i (reg2hw.intr_enable.q), + .reg2hw_intr_test_q_i (reg2hw.intr_test.q), + .reg2hw_intr_test_qe_i (reg2hw.intr_test.qe), + .reg2hw_intr_state_q_i (reg2hw.intr_state.q), + .hw2reg_intr_state_de_o (hw2reg.intr_state.de), + .hw2reg_intr_state_d_o (hw2reg.intr_state.d), + .intr_o (intr_wakeup_o) + ); + + + //////////////////////////// + /// Assertions + //////////////////////////// + + `ASSERT_KNOWN(TlDValidKnownO_A, tl_o.d_valid ) + `ASSERT_KNOWN(TlAReadyKnownO_A, tl_o.a_ready ) + `ASSERT_KNOWN(AlertsKnownO_A, alert_tx_o ) + `ASSERT_KNOWN(AstKnownO_A, pwr_ast_o ) + `ASSERT_KNOWN(RstKnownO_A, pwr_rst_o ) + `ASSERT_KNOWN(ClkKnownO_A, pwr_clk_o ) + `ASSERT_KNOWN(OtpKnownO_A, pwr_otp_o ) + `ASSERT_KNOWN(LcKnownO_A, pwr_caliptra_ss_lc_o ) + `ASSERT_KNOWN(IntrKnownO_A, intr_wakeup_o ) + + // EscTimeOutCnt also sets the required clock ratios between escalator and local clock + // Ie, clk_lc cannot be so slow that the timeout count is reached + `ifdef INC_ASSERT + //VCS coverage off + // pragma coverage off + logic effective_rst_n; + assign effective_rst_n = clk_caliptra_ss_lc_i && rst_ni; + + logic [31:0] cnt; + always_ff @(posedge clk_i or negedge effective_rst_n) begin + if (!effective_rst_n) begin + cnt <= '0; + end else begin + cnt <= cnt + 1'b1; + end + end + //VCS coverage on + // pragma coverage on + + `ASSERT(ClkRatio_A, cnt < EscTimeOutCnt) + + `endif + + `ASSERT_PRIM_FSM_ERROR_TRIGGER_ERR(FsmCheck_A, u_fsm.u_state_regs, + pwr_rst_o.rst_caliptra_ss_lc_req && pwr_rst_o.rst_sys_req) + `ASSERT_PRIM_FSM_ERROR_TRIGGER_ERR(SlowFsmCheck_A, u_slow_fsm.u_state_regs, + pwr_ast_o.pwr_clamp && !pwr_ast_o.main_pd_n, 0, 2, + clk_slow_i, !rst_slow_ni) + + // Alert assertions for reg_we onehot check + `ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ALERT(RegWeOnehotCheck_A, u_reg, alert_tx_o[0]) +endmodule // pwrmgr diff --git a/src/pwrmgr/rtl/pwrmgr_cdc.sv b/src/pwrmgr/rtl/pwrmgr_cdc.sv new file mode 100644 index 0000000..90e7b69 --- /dev/null +++ b/src/pwrmgr/rtl/pwrmgr_cdc.sv @@ -0,0 +1,333 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Power Manager CDC handling +// + +`include "prim_assert.sv" + +module pwrmgr_cdc import pwrmgr_pkg::*; import pwrmgr_reg_pkg::*; +( + // Clocks and resets + input clk_slow_i, + input clk_i, + input rst_slow_ni, + input rst_ni, + + // slow domain signals, + input slow_req_pwrup_i, + input slow_ack_pwrdn_i, + input slow_fsm_invalid_i, + input slow_pwrup_cause_toggle_i, + input pwrup_cause_e slow_pwrup_cause_i, + output logic [NumWkups-1:0] slow_wakeup_en_o, + output logic [NumRstReqs-1:0] slow_reset_en_o, + output logic slow_main_pd_no, + output logic slow_io_clk_en_o, + output logic slow_core_clk_en_o, + output logic slow_usb_clk_en_lp_o, + output logic slow_usb_clk_en_active_o, + output logic slow_req_pwrdn_o, + output logic slow_ack_pwrup_o, + output pwr_ast_rsp_t slow_ast_o, + output pwr_peri_t slow_peri_reqs_o, + input pwr_peri_t slow_peri_reqs_masked_i, + output logic slow_clr_req_o, + input slow_usb_ip_clk_en_i, + output slow_usb_ip_clk_status_o, + + // fast domain signals + input req_pwrdn_i, + input ack_pwrup_i, + input cfg_cdc_sync_i, + input [NumWkups-1:0] wakeup_en_i, + input logic [NumRstReqs-1:0] reset_en_i, + input main_pd_ni, + input io_clk_en_i, + input core_clk_en_i, + input usb_clk_en_lp_i, + input usb_clk_en_active_i, + output logic ack_pwrdn_o, + output logic fsm_invalid_o, + output logic req_pwrup_o, + output pwrup_cause_e pwrup_cause_o, + output pwr_peri_t peri_reqs_o, + output logic cdc_sync_done_o, + input clr_slow_req_i, + output logic usb_ip_clk_en_o, + input usb_ip_clk_status_i, + + // peripheral inputs, mixed domains + input pwr_peri_t peri_i, + input pwr_flash_t flash_i, + output pwr_flash_t flash_o, + + // otp interface + input pwr_otp_rsp_t otp_i, + output pwr_otp_rsp_t otp_o, + + // AST inputs, unknown domain + input pwr_ast_rsp_t ast_i, + + // rom_ctrl signals + input prim_mubi_pkg::mubi4_t rom_ctrl_done_i, + output prim_mubi_pkg::mubi4_t rom_ctrl_done_o, + + // core sleeping + input core_sleeping_i, + output logic core_sleeping_o + +); + + //////////////////////////////// + // Sync from clk_i to clk_slow_i + //////////////////////////////// + + logic slow_cdc_sync; + pwr_ast_rsp_t slow_ast_q, slow_ast_q2; + + prim_flop_2sync # ( + .Width(1) + ) u_req_pwrdn_sync ( + .clk_i(clk_slow_i), + .rst_ni(rst_slow_ni), + .d_i(req_pwrdn_i), + .q_o(slow_req_pwrdn_o) + ); + + prim_flop_2sync # ( + .Width(1) + ) u_ack_pwrup_sync ( + .clk_i(clk_slow_i), + .rst_ni(rst_slow_ni), + .d_i(ack_pwrup_i), + .q_o(slow_ack_pwrup_o) + ); + + prim_pulse_sync u_slow_cdc_sync ( + .clk_src_i(clk_i), + .rst_src_ni(rst_ni), + .src_pulse_i(cfg_cdc_sync_i), + .clk_dst_i(clk_slow_i), + .rst_dst_ni(rst_slow_ni), + .dst_pulse_o(slow_cdc_sync) + ); + + // Even though this is multi-bit, the bits are individual request lines. + // So there is no general concern about recombining as there is + // no intent to use them in a related manner. + prim_flop_2sync # ( + .Width($bits(pwr_peri_t)) + ) u_slow_ext_req_sync ( + .clk_i (clk_slow_i), + .rst_ni (rst_slow_ni), + .d_i (peri_i), + .q_o (slow_peri_reqs_o) + ); + + prim_flop_2sync # ( + .Width(1) + ) u_ip_clk_status_sync ( + .clk_i (clk_slow_i), + .rst_ni (rst_slow_ni), + .d_i (usb_ip_clk_status_i), + .q_o (slow_usb_ip_clk_status_o) + ); + + // Some of the AST signals are multi-bits themselves (such as clk_val) + // thus they need to be delayed one more stage to check for stability + prim_flop_2sync # ( + .Width($bits(pwr_ast_rsp_t)), + .ResetValue(PWR_AST_RSP_SYNC_DEFAULT) + ) u_ast_sync ( + .clk_i (clk_slow_i), + .rst_ni (rst_slow_ni), + .d_i (ast_i), + .q_o (slow_ast_q) + ); + + always_ff @(posedge clk_slow_i or negedge rst_slow_ni) begin + if (!rst_slow_ni) begin + slow_ast_q2 <= PWR_AST_RSP_SYNC_DEFAULT; + end else begin + slow_ast_q2 <= slow_ast_q; + end + end + + // if possible, we should simulate below with random delays through + // flop_2sync + always_ff @(posedge clk_slow_i or negedge rst_slow_ni) begin + if (!rst_slow_ni) begin + slow_ast_o <= PWR_AST_RSP_SYNC_DEFAULT; + end else if (slow_ast_q2 == slow_ast_q) begin + // Output only updates whenever sync and delayed outputs both agree. + // If there are delays in sync, this will result in a 1 cycle difference + // and the output will hold the previous value + slow_ast_o <= slow_ast_q2; + end + end + + // only register configurations can be sync'd using slow_cdc_sync + always_ff @(posedge clk_slow_i or negedge rst_slow_ni) begin + if (!rst_slow_ni) begin + slow_wakeup_en_o <= '0; + slow_reset_en_o <= '0; + slow_main_pd_no <= '1; + slow_io_clk_en_o <= '0; + slow_core_clk_en_o <= '0; + slow_usb_clk_en_lp_o <= '0; + slow_usb_clk_en_active_o <= 1'b1; + end else if (slow_cdc_sync) begin + slow_wakeup_en_o <= wakeup_en_i; + slow_reset_en_o <= reset_en_i; + slow_main_pd_no <= main_pd_ni; + slow_io_clk_en_o <= io_clk_en_i; + slow_core_clk_en_o <= core_clk_en_i; + slow_usb_clk_en_lp_o <= usb_clk_en_lp_i; + slow_usb_clk_en_active_o <= usb_clk_en_active_i; + end + end + + //////////////////////////////// + // Sync from clk_slow_i to clk_i + //////////////////////////////// + + logic pwrup_cause_toggle_q, pwrup_cause_toggle_q2; + logic pwrup_cause_chg; + + prim_flop_2sync # ( + .Width(1) + ) u_req_pwrup_sync ( + .clk_i, + .rst_ni, + .d_i(slow_req_pwrup_i), + .q_o(req_pwrup_o) + ); + + prim_flop_2sync # ( + .Width(1) + ) u_ack_pwrdn_sync ( + .clk_i, + .rst_ni, + .d_i(slow_ack_pwrdn_i), + .q_o(ack_pwrdn_o) + ); + + prim_flop_2sync # ( + .Width(1) + ) u_int_fsm_invalid_sync ( + .clk_i, + .rst_ni, + .d_i(slow_fsm_invalid_i), + .q_o(fsm_invalid_o) + ); + + prim_flop_2sync # ( + .Width(1) + ) u_pwrup_chg_sync ( + .clk_i, + .rst_ni, + .d_i(slow_pwrup_cause_toggle_i), + .q_o(pwrup_cause_toggle_q) + ); + + prim_flop_2sync # ( + .Width(1) + ) u_ip_clk_en_sync ( + .clk_i, + .rst_ni, + .d_i(slow_usb_ip_clk_en_i), + .q_o(usb_ip_clk_en_o) + ); + + prim_flop_2sync # ( + .Width(1) + ) u_sleeping_sync ( + .clk_i, + .rst_ni, + .d_i(core_sleeping_i), + .q_o(core_sleeping_o) + ); + + prim_pulse_sync u_scdc_sync ( + .clk_src_i(clk_slow_i), + .rst_src_ni(rst_slow_ni), + .src_pulse_i(slow_cdc_sync), + .clk_dst_i(clk_i), + .rst_dst_ni(rst_ni), + .dst_pulse_o(cdc_sync_done_o) + ); + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + pwrup_cause_toggle_q2 <= 1'b0; + end else begin + pwrup_cause_toggle_q2 <= pwrup_cause_toggle_q; + end + end + + assign pwrup_cause_chg = pwrup_cause_toggle_q2 ^ pwrup_cause_toggle_q; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + pwrup_cause_o <= Por; + end else if (pwrup_cause_chg) begin + pwrup_cause_o <= slow_pwrup_cause_i; + end + end + + prim_flop_2sync #( + .Width($bits(pwr_peri_t)) + ) u_ext_req_sync ( + .clk_i, + .rst_ni, + .d_i(slow_peri_reqs_masked_i), + .q_o(peri_reqs_o) + ); + + prim_flop_2sync #( + .Width(1), + .ResetValue(1'b1) + ) u_sync_flash_idle ( + .clk_i, + .rst_ni, + .d_i(flash_i.flash_idle), + .q_o(flash_o.flash_idle) + ); + + prim_flop_2sync #( + .Width($bits(pwr_otp_rsp_t)), + .ResetValue('0) + ) u_sync_otp ( + .clk_i, + .rst_ni, + .d_i(otp_i), + .q_o(otp_o) + ); + + prim_mubi4_sync #( + .NumCopies(1), + .AsyncOn(1), + .StabilityCheck(1) + ) u_sync_rom_ctrl ( + .clk_i, + .rst_ni, + .mubi_i(rom_ctrl_done_i), + .mubi_o({rom_ctrl_done_o}) + ); + + //////////////////////////////// + // Handshake + //////////////////////////////// + prim_flop_2sync #( + .Width(1), + .ResetValue('0) + ) u_clr_req_sync ( + .clk_i(clk_slow_i), + .rst_ni(rst_slow_ni), + .d_i(clr_slow_req_i), + .q_o(slow_clr_req_o) + ); + +endmodule diff --git a/src/pwrmgr/rtl/pwrmgr_cdc_pulse.sv b/src/pwrmgr/rtl/pwrmgr_cdc_pulse.sv new file mode 100644 index 0000000..ad7c501 --- /dev/null +++ b/src/pwrmgr/rtl/pwrmgr_cdc_pulse.sv @@ -0,0 +1,91 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Power Manager module to find slow clock edges +// The clock is not used directly to avoid STA issues, instead a toggle +// pulse is used. + +`include "prim_assert.sv" + +module pwrmgr_cdc_pulse ( + input clk_slow_i, + input clk_i, + input rst_ni, + input rst_slow_ni, + input start_i, + input stop_i, + output logic pulse_o +); + + logic slow_toggle_pq, slow_toggle_nq; + logic clk_slow_pq, clk_slow_nq; + logic clk_slow_pq2, clk_slow_nq2; + logic toggle; + logic valid; + + // toggle pulse generated on positive edge + always_ff @(posedge clk_slow_i or negedge rst_slow_ni) begin + if (!rst_slow_ni) begin + slow_toggle_pq <= 1'b0; + end else begin + slow_toggle_pq <= ~slow_toggle_pq; + end + end + + // toggle pulse generated on negative edge + always_ff @(negedge clk_slow_i or negedge rst_slow_ni) begin + if (!rst_slow_ni) begin + slow_toggle_nq <= 1'b0; + end else begin + slow_toggle_nq <= ~slow_toggle_nq; + end + end + + + prim_flop_2sync # ( + .Width(1) + ) i_pos_sync ( + .clk_i, + .rst_ni, + .d_i(slow_toggle_pq), + .q_o(clk_slow_pq) + ); + + prim_flop_2sync # ( + .Width(1) + ) i_neg_sync ( + .clk_i, + .rst_ni, + .d_i(slow_toggle_nq), + .q_o(clk_slow_nq) + ); + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + clk_slow_pq2 <= 1'b0; + clk_slow_nq2 <= 1'b0; + end else begin + clk_slow_pq2 <= clk_slow_pq; + clk_slow_nq2 <= clk_slow_nq; + end + end + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + valid <= 1'b0; + end else if (valid && stop_i) begin + valid <= 1'b0; + end else if (!valid && toggle && start_i) begin + valid <= 1'b1; + end + end + + // toggle is found on either positive and negative edges of clk_slow_i + assign toggle = clk_slow_pq2 ^ clk_slow_pq | clk_slow_nq2 ^ clk_slow_nq; + assign pulse_o = valid & toggle; + + + + +endmodule // pwrmgr diff --git a/src/pwrmgr/rtl/pwrmgr_fsm.sv b/src/pwrmgr/rtl/pwrmgr_fsm.sv new file mode 100644 index 0000000..bfb015f --- /dev/null +++ b/src/pwrmgr/rtl/pwrmgr_fsm.sv @@ -0,0 +1,542 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Power Manager Fast FSM +// + +`include "prim_assert.sv" + +module pwrmgr_fsm import pwrmgr_pkg::*; import pwrmgr_reg_pkg::*;( + input clk_i, + input rst_ni, + input clk_slow_i, + input rst_slow_ni, + + // interface with slow_fsm + input req_pwrup_i, + input pwrup_cause_e pwrup_cause_i, + output logic ack_pwrup_o, + output logic req_pwrdn_o, + input ack_pwrdn_i, + input low_power_entry_i, + input main_pd_ni, + input [TotalResetWidth-1:0] reset_reqs_i, + input fsm_invalid_i, + output logic clr_slow_req_o, + input usb_ip_clk_en_i, + output logic usb_ip_clk_status_o, + + // consumed in pwrmgr + output logic wkup_o, // generate wake interrupt + output logic fall_through_o, + output logic abort_o, + output logic clr_hint_o, + output logic clr_cfg_lock_o, + + // rstmgr + output pwr_rst_req_t pwr_rst_o, + input pwr_rst_rsp_t pwr_rst_i, + + // clkmgr + output pwr_clk_req_t ips_clk_en_o, + input pwr_clk_rsp_t clk_en_status_i, + + // otp + output logic otp_init_o, + input otp_done_i, + input otp_idle_i, + + // lc + output logic caliptra_ss_lc_init_o, + input caliptra_ss_lc_done_i, + input caliptra_ss_lc_idle_i, + input caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_t caliptra_ss_lc_dft_en_i, + input caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_t caliptra_ss_lc_hw_debug_en_i, + + // flash + input flash_idle_i, + + // rom_ctrl + input prim_mubi_pkg::mubi4_t rom_ctrl_done_i, + input prim_mubi_pkg::mubi4_t rom_ctrl_good_i, + + // pinmux + output logic strap_o, + output logic low_power_o, + + // processing elements + output caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_t fetch_en_o +); + + import prim_mubi_pkg::mubi4_t; + import prim_mubi_pkg::mubi4_test_true_strict; + import prim_mubi_pkg::mubi4_or_hi; + import prim_mubi_pkg::mubi4_and_hi; + import caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_and_hi; + import caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_test_true_strict; + + // The code below always assumes the always on domain is index 0 + `ASSERT_INIT(AlwaysOnIndex_A, ALWAYS_ON_DOMAIN == 0) + + // when there are multiple on domains, the latter 1 should become another parameter + localparam int OffDomainSelStart = ALWAYS_ON_DOMAIN + 1; + + // all powered down domains have resets asserted + logic pd_n_rsts_asserted; + + // all domains have resets asserted + logic all_rsts_asserted; + + // resets are valid + logic reset_valid; + + // reset hint to rstmgr + reset_cause_e reset_cause_q, reset_cause_d; + + // reset request + logic reset_req; + logic direct_rst_req; + logic ndmreset_req; + logic hw_rst_req; + logic sw_rst_req; + + // strap sample should only happen on cold boot or when the + // the system goes through a reset cycle + logic strap_sampled; + + // disable processing element fetching + caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_t fetch_en_q, fetch_en_d; + + fast_pwr_state_e state_d, state_q; + logic reset_ongoing_q, reset_ongoing_d; + logic req_pwrdn_q, req_pwrdn_d; + logic ack_pwrup_q, ack_pwrup_d; + logic ip_clk_en_q, ip_clk_en_d; + logic [PowerDomains-1:0] rst_caliptra_ss_lc_req_q, rst_sys_req_q; + logic [PowerDomains-1:0] rst_caliptra_ss_lc_req_d, rst_sys_req_d; + logic otp_init; + logic caliptra_ss_lc_init; + logic low_power_q, low_power_d; + + assign pd_n_rsts_asserted = pwr_rst_i.rst_caliptra_ss_lc_src_n[PowerDomains-1:OffDomainSelStart] == '0 & + pwr_rst_i.rst_sys_src_n[PowerDomains-1:OffDomainSelStart] == '0; + + logic caliptra_ss_lc_rsts_valid; + assign caliptra_ss_lc_rsts_valid = ((rst_caliptra_ss_lc_req_q & ~pwr_rst_i.rst_caliptra_ss_lc_src_n) | + (~rst_caliptra_ss_lc_req_q & pwr_rst_i.rst_caliptra_ss_lc_src_n)) == {PowerDomains{1'b1}}; + logic sys_rsts_valid; + assign sys_rsts_valid = ((rst_sys_req_q & ~pwr_rst_i.rst_sys_src_n) | + (~rst_sys_req_q & pwr_rst_i.rst_sys_src_n)) == {PowerDomains{1'b1}}; + + assign all_rsts_asserted = caliptra_ss_lc_rsts_valid & sys_rsts_valid; + + // Any reset request was asserted. + assign reset_req = |reset_reqs_i; + + // Any peripheral triggererd hardware reset request. + assign hw_rst_req = |reset_reqs_i[NumRstReqs-1:0]; + + // Direct reset request that bypass checks. + assign direct_rst_req = reset_reqs_i[ResetEscIdx] | + reset_reqs_i[ResetMainPwrIdx]; + + // Ndm reset request. + assign ndmreset_req = reset_reqs_i[ResetNdmIdx]; + + // Software triggered reset request. + assign sw_rst_req = reset_reqs_i[ResetSwReqIdx]; + + // when in low power path, resets are controlled by domain power down + // when in reset path, all resets must be asserted + // when the reset cause is something else, it is invalid + assign reset_valid = reset_cause_q == LowPwrEntry ? main_pd_ni | pd_n_rsts_asserted : + reset_cause_q == HwReq ? all_rsts_asserted : 1'b0; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + ack_pwrup_q <= 1'b0; + req_pwrdn_q <= 1'b0; + reset_ongoing_q <= 1'b0; + ip_clk_en_q <= 1'b0; + rst_caliptra_ss_lc_req_q <= {PowerDomains{1'b1}}; + rst_sys_req_q <= {PowerDomains{1'b1}}; + reset_cause_q <= ResetUndefined; + low_power_q <= 1'b1; + end else begin + ack_pwrup_q <= ack_pwrup_d; + req_pwrdn_q <= req_pwrdn_d; + reset_ongoing_q <= reset_ongoing_d; + ip_clk_en_q <= ip_clk_en_d; + rst_caliptra_ss_lc_req_q <= rst_caliptra_ss_lc_req_d; + rst_sys_req_q <= rst_sys_req_d; + reset_cause_q <= reset_cause_d; + low_power_q <= low_power_d; + end + end + + // SEC_CM: FSM.SPARSE + `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, fast_pwr_state_e, FastPwrStateLowPower) + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + strap_sampled <= 1'b0; + end else if (&rst_sys_req_q) begin + strap_sampled <= 1'b0; + end else if (strap_o) begin + strap_sampled <= 1'b1; + end + end + + prim_caliptra_ss_lc_sender u_fetch_en ( + .clk_i, + .rst_ni, + .caliptra_ss_lc_en_i(fetch_en_d), + .caliptra_ss_lc_en_o(fetch_en_q) + ); + assign fetch_en_o = fetch_en_q; + + // Life cycle broadcast may take time to propagate through the system. + // The sync below simulates that behavior using the slowest clock in the + // system. + logic slow_caliptra_ss_lc_done; + logic caliptra_ss_lc_done; + + prim_flop_2sync #( + .Width(1) + ) u_slow_sync_caliptra_ss_lc_done ( + .clk_i(clk_slow_i), + .rst_ni(rst_slow_ni), + .d_i(caliptra_ss_lc_done_i), + .q_o(slow_caliptra_ss_lc_done) + ); + + prim_flop_2sync #( + .Width(1) + ) u_sync_caliptra_ss_lc_done ( + .clk_i, + .rst_ni, + .d_i(slow_caliptra_ss_lc_done), + .q_o(caliptra_ss_lc_done) + ); + + + logic clks_enabled; + logic clks_disabled; + + // clocks all enabled computed as follows: + // if enable is high, meaning clock is requested to turn on, the status must + // also be 1. + // if enable is low, meaning clock is not requested to turn on, the status is + // don't care. + // the bit-wise OR of both conditions must be all true. + assign clks_enabled = ip_clk_en_q && + &((ips_clk_en_o & clk_en_status_i) | ~ips_clk_en_o); + + // clocks all disabled is the opposite: + // if enable is low the status must also be low. + // if enable is high, the status is don't care. + // the bit-wise OR of both conditions must be all true. + assign clks_disabled = ~ip_clk_en_q && + &((~ips_clk_en_o & ~clk_en_status_i) | ips_clk_en_o); + + + // rom integrity checks are disabled during TEST / RMA states + // During TEST / RMA states, both dft_en and hw_debug_en are On. + // During DEV / PROD states, either both signals are Off, or only + // hw_debug_en is On + + mubi4_t rom_intg_chk_dis; + assign rom_intg_chk_dis = caliptra_ss_lc_tx_test_true_strict(caliptra_ss_lc_tx_and_hi(caliptra_ss_lc_dft_en_i, caliptra_ss_lc_hw_debug_en_i)) ? + prim_mubi_pkg::MuBi4True : + prim_mubi_pkg::MuBi4False; + + mubi4_t rom_intg_chk_done; + mubi4_t rom_intg_chk_good; + assign rom_intg_chk_done = mubi4_or_hi(mubi4_and_hi(rom_intg_chk_dis, rom_ctrl_done_i), + rom_ctrl_done_i); + assign rom_intg_chk_good = mubi4_or_hi(rom_intg_chk_dis, rom_ctrl_good_i); + + always_comb begin + otp_init = 1'b0; + caliptra_ss_lc_init = 1'b0; + wkup_o = 1'b0; + fall_through_o = 1'b0; + abort_o = 1'b0; + clr_hint_o = 1'b0; + clr_cfg_lock_o = 1'b0; + strap_o = 1'b0; + clr_slow_req_o = 1'b0; + + state_d = state_q; + ack_pwrup_d = ack_pwrup_q; + req_pwrdn_d = req_pwrdn_q; + reset_ongoing_d = reset_ongoing_q; + ip_clk_en_d = ip_clk_en_q; + rst_caliptra_ss_lc_req_d = rst_caliptra_ss_lc_req_q; + rst_sys_req_d = rst_sys_req_q; + reset_cause_d = reset_cause_q; + low_power_d = low_power_q; + fetch_en_d = fetch_en_q; + + unique case(state_q) + + FastPwrStateLowPower: begin + if (req_pwrup_i || reset_ongoing_q) begin + state_d = FastPwrStateEnableClocks; + end + end + + FastPwrStateEnableClocks: begin + ip_clk_en_d = 1'b1; + if (clks_enabled) begin + state_d = FastPwrStateReleaseLcRst; + end + end + + FastPwrStateReleaseLcRst: begin + rst_caliptra_ss_lc_req_d = '0; // release rst_caliptra_ss_lc_n for all power domains + rst_sys_req_d = '0; // release rst_sys_n for all power domains + // once all resets are released continue to otp initialization + if (&pwr_rst_i.rst_caliptra_ss_lc_src_n) begin + state_d = FastPwrStateOtpInit; + end + end + + FastPwrStateOtpInit: begin + otp_init = 1'b1; + + if (otp_done_i) begin + state_d = FastPwrStateLcInit; + end + end + + FastPwrStateLcInit: begin + caliptra_ss_lc_init = 1'b1; + + if (caliptra_ss_lc_done) begin + state_d = FastPwrStateAckPwrUp; + + end + end + + FastPwrStateAckPwrUp: begin + // only ack the slow_fsm if we actually transitioned through it + ack_pwrup_d = !reset_ongoing_q; + + // wait for request power up to drop relative to ack + if (!req_pwrup_i || reset_ongoing_q) begin + ack_pwrup_d = 1'b0; + clr_cfg_lock_o = 1'b1; + // generate a wakeup interrupt if we intended to go to low power + // and we were woken from low power with a wakeup and not reset + wkup_o = (pwrup_cause_i == Wake) & (reset_cause_q == LowPwrEntry); + // This constitutes the end of a reset cycle + reset_ongoing_d = 1'b0; + state_d = FastPwrStateStrap; + end + end + + FastPwrStateStrap: begin + strap_o = ~strap_sampled; + state_d = FastPwrStateRomCheckDone; + end + + FastPwrStateRomCheckDone: begin + // zero outgoing low power indication + low_power_d = '0; + reset_cause_d = ResetNone; + + // When done is observed, advance to good check + if (mubi4_test_true_strict(rom_intg_chk_done)) begin + state_d = FastPwrStateRomCheckGood; + end + end + + FastPwrStateRomCheckGood: begin + if (mubi4_test_true_strict(rom_intg_chk_good)) begin + state_d = FastPwrStateActive; + end + end + + FastPwrStateActive: begin + // only in active state, allow processor to execute + fetch_en_d = caliptra_ss_lc_ctrl_pkg::On; + + // when handling reset request or low power entry of any + // kind, stop processor from fetching + if (reset_req || low_power_entry_i) begin + fetch_en_d = caliptra_ss_lc_ctrl_pkg::Off; + reset_cause_d = ResetUndefined; + state_d = FastPwrStateDisClks; + end + end + + FastPwrStateDisClks: begin + ip_clk_en_d = 1'b0; + + if (clks_disabled) begin + state_d = reset_req ? FastPwrStateNvmShutDown : FastPwrStateFallThrough; + low_power_d = ~reset_req; + end else begin + // escalation was received, skip all handshaking and directly reset + state_d = direct_rst_req ? FastPwrStateNvmShutDown : state_q; + low_power_d = ~reset_req; + end + end + + // Low Power Path + FastPwrStateFallThrough: begin + clr_hint_o = 1'b1; + + // The processor was interrupted after it asserted WFI and is executing again + if (!low_power_entry_i) begin + ip_clk_en_d = 1'b1; + wkup_o = 1'b1; + fall_through_o = 1'b1; + state_d = FastPwrStateRomCheckDone; + end else begin + state_d = FastPwrStateNvmIdleChk; + end + end + + FastPwrStateNvmIdleChk: begin + + if (otp_idle_i && caliptra_ss_lc_idle_i && flash_idle_i) begin + state_d = FastPwrStateLowPowerPrep; + end else begin + ip_clk_en_d = 1'b1; + wkup_o = 1'b1; + abort_o = 1'b1; + state_d = FastPwrStateRomCheckDone; + end + end + + FastPwrStateLowPowerPrep: begin + // reset cause is set only if main power domain will be turned off + reset_cause_d = LowPwrEntry; + + // reset non-always-on domains if requested + // this includes the clock manager, which implies pwr/rst managers must + // be fed directly from the source + for (int i = OffDomainSelStart; i < PowerDomains; i++) begin + rst_caliptra_ss_lc_req_d[i] = ~main_pd_ni; + rst_sys_req_d[i] = ~main_pd_ni; + end + + if (reset_valid) begin + state_d = FastPwrStateReqPwrDn; + end + end + + FastPwrStateReqPwrDn: begin + req_pwrdn_d = 1'b1; + + if (ack_pwrdn_i) begin + req_pwrdn_d = 1'b0; + state_d = FastPwrStateLowPower; + end + end + + // Reset Path + FastPwrStateNvmShutDown: begin + clr_hint_o = 1'b1; + reset_ongoing_d = 1'b1; + state_d = FastPwrStateResetPrep; + end + + FastPwrStateResetPrep: begin + reset_cause_d = HwReq; + rst_caliptra_ss_lc_req_d = {PowerDomains{1'b1}}; + rst_sys_req_d = {PowerDomains{(hw_rst_req | + direct_rst_req | + sw_rst_req) | + (ndmreset_req & + caliptra_ss_lc_ctrl_pkg::caliptra_ss_lc_tx_test_false_loose(caliptra_ss_lc_hw_debug_en_i))}}; + + + state_d = FastPwrStateResetWait; + end + + FastPwrStateResetWait: begin + rst_caliptra_ss_lc_req_d = {PowerDomains{1'b1}}; + clr_slow_req_o = reset_reqs_i[ResetMainPwrIdx]; + // The main power reset request is checked here specifically because it is + // the only reset request in the system that operates on the POR domain. + // This has to be the case since it would otherwise not be able to monitor + // the non-always-on domains. + // + // As a result of this, the normal reset process does not automatically + // wipe out the reset request, so we specifically clear it and wait for it to be + // cleared before proceeding. This also implies if the system is under a persistent + // glitch, or if someone just turned off the power before pwrmgr turns it off itself, + // we will stay stuck here and perpetually hold the system in reset. + if (reset_valid && !reset_reqs_i[ResetMainPwrIdx]) begin + state_d = FastPwrStateLowPower; + end + end + + + // Terminal state, kill everything + // SEC_CM: FSM.TERMINAL + default: begin + rst_caliptra_ss_lc_req_d = {PowerDomains{1'b1}}; + rst_sys_req_d = {PowerDomains{1'b1}}; + ip_clk_en_d = 1'b0; + end + endcase // unique case (state_q) + + if (fsm_invalid_i) begin + // the slow fsm is completely out of sync, transition to terminal state + state_d = FastPwrStateInvalid; + end + + + end // always_comb + + assign ack_pwrup_o = ack_pwrup_q; + assign req_pwrdn_o = req_pwrdn_q; + assign low_power_o = low_power_q; + + assign pwr_rst_o.rst_caliptra_ss_lc_req = rst_caliptra_ss_lc_req_q; + assign pwr_rst_o.rst_sys_req = rst_sys_req_q; + assign pwr_rst_o.reset_cause = reset_cause_q; + assign pwr_rst_o.rstreqs = reset_reqs_i[HwResetWidth-1:0]; + + // main and io clocks are only turned on/off as part of normal + // power sequence + assign ips_clk_en_o.main_ip_clk_en = ip_clk_en_q; + assign ips_clk_en_o.io_ip_clk_en = ip_clk_en_q; + prim_flop #( + .Width(1), + .ResetValue(1'b0) + ) u_usb_ip_clk_en ( + .clk_i, + .rst_ni, + .d_i(ip_clk_en_d & usb_ip_clk_en_i), + .q_o(ips_clk_en_o.usb_ip_clk_en) + ); + assign usb_ip_clk_status_o = clk_en_status_i.usb_status; + + prim_flop #( + .Width(1), + .ResetValue(1'b0) + ) u_reg_otp_init ( + .clk_i, + .rst_ni, + .d_i(otp_init), + .q_o(otp_init_o) + ); + + prim_flop #( + .Width(1), + .ResetValue(1'b0) + ) u_reg_caliptra_ss_lc_init ( + .clk_i, + .rst_ni, + .d_i(caliptra_ss_lc_init), + .q_o(caliptra_ss_lc_init_o) + ); + + +endmodule diff --git a/src/pwrmgr/rtl/pwrmgr_pkg.sv b/src/pwrmgr/rtl/pwrmgr_pkg.sv new file mode 100644 index 0000000..bb69410 --- /dev/null +++ b/src/pwrmgr/rtl/pwrmgr_pkg.sv @@ -0,0 +1,282 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Power Manager Package +// + +package pwrmgr_pkg; + + // global constant + parameter int ALWAYS_ON_DOMAIN = 0; + + // variables referenced by other modules / packages + parameter int PowerDomains = 2; // this needs to be a topgen populated number, or from topcfg? + + // variables referenced only by pwrmgr + localparam int TotalWakeWidth = pwrmgr_reg_pkg::NumWkups + 2; // Abort and fall through are added + + parameter int NumSwRstReq = 1; + + // position of escalation request + parameter int HwResetWidth = pwrmgr_reg_pkg::NumRstReqs + + pwrmgr_reg_pkg::NumIntRstReqs + + pwrmgr_reg_pkg::NumDebugRstReqs; + parameter int TotalResetWidth = HwResetWidth + NumSwRstReq; + parameter int ResetSwReqIdx = TotalResetWidth - 1; + + // pwrmgr to ast + typedef struct packed { + logic main_pd_n; + logic pwr_clamp_env; + logic pwr_clamp; + logic slow_clk_en; + logic core_clk_en; + logic io_clk_en; + logic usb_clk_en; + } pwr_ast_req_t; + + typedef struct packed { + logic slow_clk_val; + logic core_clk_val; + logic io_clk_val; + logic usb_clk_val; + logic main_pok; + } pwr_ast_rsp_t; + + // default value of pwr_ast_rsp (for dangling ports) + parameter pwr_ast_rsp_t PWR_AST_RSP_DEFAULT = '{ + slow_clk_val: 1'b1, + core_clk_val: 1'b1, + io_clk_val: 1'b1, + usb_clk_val: 1'b1, + main_pok: 1'b1 + }; + + parameter pwr_ast_rsp_t PWR_AST_RSP_SYNC_DEFAULT = '{ + slow_clk_val: 1'b0, + core_clk_val: 1'b0, + io_clk_val: 1'b0, + usb_clk_val: 1'b0, + main_pok: 1'b0 + }; + + // reasons for pwrmgr reset + typedef enum logic [1:0] { + ResetNone = 0, // there is no reset + LowPwrEntry = 1, // reset is caused by low power entry + HwReq = 2, // reset is caused by peripheral reset requests + ResetUndefined = 3 // this should never happen outside of POR + } reset_cause_e; + + // pwrmgr to rstmgr + typedef struct packed { + logic [PowerDomains-1:0] rst_caliptra_ss_lc_req; + logic [PowerDomains-1:0] rst_sys_req; + logic [HwResetWidth-1:0] rstreqs; + reset_cause_e reset_cause; + } pwr_rst_req_t; + + // rstmgr to pwrmgr + typedef struct packed { + logic [PowerDomains-1:0] rst_caliptra_ss_lc_src_n; + logic [PowerDomains-1:0] rst_sys_src_n; + } pwr_rst_rsp_t; + + // default value (for dangling ports) + parameter pwr_rst_rsp_t PWR_RST_RSP_DEFAULT = '{ + rst_caliptra_ss_lc_src_n: {PowerDomains{1'b1}}, + rst_sys_src_n: {PowerDomains{1'b1}} + }; + + // pwrmgr to clkmgr + typedef struct packed { + logic main_ip_clk_en; + logic io_ip_clk_en; + logic usb_ip_clk_en; + } pwr_clk_req_t; + + // clkmgr to pwrmgr + typedef struct packed { + logic main_status; + logic io_status; + logic usb_status; + } pwr_clk_rsp_t; + + // pwrmgr to otp + typedef struct packed { + logic otp_init; + } pwr_otp_req_t; + + // otp to pwrmgr + typedef struct packed { + logic otp_done; + logic otp_idle; + } pwr_otp_rsp_t; + + // default value (for dangling ports) + parameter pwr_otp_rsp_t PWR_OTP_RSP_DEFAULT = '{ + otp_done: 1'b1, + otp_idle: 1'b1 + }; + + // pwrmgr to lifecycle + typedef struct packed { + logic caliptra_ss_lc_init; + } pwr_caliptra_ss_lc_req_t; + + // lifecycle to pwrmgr + typedef struct packed { + logic caliptra_ss_lc_done; + logic caliptra_ss_lc_idle; + } pwr_caliptra_ss_lc_rsp_t; + + // default value (for dangling ports) + parameter pwr_caliptra_ss_lc_rsp_t PWR_LC_RSP_DEFAULT = '{ + caliptra_ss_lc_done: 1'b1, + caliptra_ss_lc_idle: 1'b1 + }; + + typedef struct packed { + logic flash_idle; + } pwr_flash_t; + + parameter pwr_flash_t PWR_FLASH_DEFAULT = '{ + flash_idle: 1'b1 + }; + + // processor to pwrmgr + typedef struct packed { + logic core_sleeping; + } pwr_cpu_t; + + // cpu reset requests and status + typedef struct packed { + logic ndmreset_req; + } pwrmgr_cpu_t; + + // exported resets + + // default value for pwrmgr_ast_rsp_t (for dangling ports) + parameter pwrmgr_cpu_t PWRMGR_CPU_DEFAULT = '{ + ndmreset_req: '0 + }; + + // default value (for dangling ports) + parameter pwr_cpu_t PWR_CPU_DEFAULT = '{ + core_sleeping: 1'b0 + }; + + // default value (for dangling ports) + parameter int WAKEUPS_DEFAULT = '0; + parameter int RSTREQS_DEFAULT = '0; + + // peripherals to pwrmgr + typedef struct packed { + logic [pwrmgr_reg_pkg::NumWkups-1:0] wakeups; + // reset requests include external requests + escalation reset + logic [TotalResetWidth-1:0] rstreqs; + } pwr_peri_t; + + // power-up causes + typedef enum logic [1:0] { + Por = 2'h0, + Wake = 2'h1, + Reset = 2'h2 + } pwrup_cause_e; + + // low power hints + typedef enum logic { + None = 1'b0, + LowPower = 1'b1 + } low_power_hint_e; + + // fast fsm state enum + // Encoding generated with: + // $ ./util/design/sparse-fsm-encode.py -d 5 -m 19 -n 12 \ + // -s 3096160381 --language=sv + // + // Hamming distance histogram: + // + // 0: -- + // 1: -- + // 2: -- + // 3: -- + // 4: -- + // 5: ||||||||||||||||| (30.99%) + // 6: |||||||||||||||||||| (35.09%) + // 7: ||||||||| (15.79%) + // 8: |||||| (10.53%) + // 9: ||| (5.85%) + // 10: | (1.75%) + // 11: -- + // 12: -- + // + // Minimum Hamming distance: 5 + // Maximum Hamming distance: 10 + // Minimum Hamming weight: 2 + // Maximum Hamming weight: 10 + // + localparam int FastPwrStateWidth = 12; + typedef enum logic [FastPwrStateWidth-1:0] { + FastPwrStateLowPower = 12'b000000110111, + FastPwrStateEnableClocks = 12'b101011001110, + FastPwrStateReleaseLcRst = 12'b100111000000, + FastPwrStateOtpInit = 12'b111110100010, + FastPwrStateLcInit = 12'b101001010011, + FastPwrStateStrap = 12'b110000111010, + FastPwrStateAckPwrUp = 12'b000010101000, + FastPwrStateRomCheckDone = 12'b010111110011, + FastPwrStateRomCheckGood = 12'b010000000100, + FastPwrStateActive = 12'b001101100100, + FastPwrStateDisClks = 12'b001110010101, + FastPwrStateFallThrough = 12'b011011010000, + FastPwrStateNvmIdleChk = 12'b100101111001, + FastPwrStateLowPowerPrep = 12'b010110001111, + FastPwrStateNvmShutDown = 12'b001100001010, + FastPwrStateResetPrep = 12'b011001101111, + FastPwrStateResetWait = 12'b111111111100, + FastPwrStateReqPwrDn = 12'b111010001001, + FastPwrStateInvalid = 12'b110101010110 + } fast_pwr_state_e; + + // Encoding generated with: + // $ ./util/design/sparse-fsm-encode.py -d 5 -m 12 -n 10 \ + // -s 1726685338 --language=sv + // + // Hamming distance histogram: + // + // 0: -- + // 1: -- + // 2: -- + // 3: -- + // 4: -- + // 5: |||||||||||||||||||| (54.55%) + // 6: |||||||||||||||| (45.45%) + // 7: -- + // 8: -- + // 9: -- + // 10: -- + // + // Minimum Hamming distance: 5 + // Maximum Hamming distance: 6 + // Minimum Hamming weight: 2 + // Maximum Hamming weight: 8 + // + localparam int SlowPwrStateWidth = 10; + typedef enum logic [SlowPwrStateWidth-1:0] { + SlowPwrStateReset = 10'b0000100010, + SlowPwrStateLowPower = 10'b1011000111, + SlowPwrStateMainPowerOn = 10'b0110101111, + SlowPwrStatePwrClampOff = 10'b0110010001, + SlowPwrStateClocksOn = 10'b1010111100, + SlowPwrStateReqPwrUp = 10'b0011011010, + SlowPwrStateIdle = 10'b1111100000, + SlowPwrStateAckPwrDn = 10'b0001110101, + SlowPwrStateClocksOff = 10'b1101111011, + SlowPwrStatePwrClampOn = 10'b0101001100, + SlowPwrStateMainPowerOff = 10'b1000001001, + SlowPwrStateInvalid = 10'b1100010110 + } slow_pwr_state_e; + +endpackage // pwrmgr_pkg diff --git a/src/pwrmgr/rtl/pwrmgr_reg_pkg.sv b/src/pwrmgr/rtl/pwrmgr_reg_pkg.sv new file mode 100644 index 0000000..3f9cae5 --- /dev/null +++ b/src/pwrmgr/rtl/pwrmgr_reg_pkg.sv @@ -0,0 +1,279 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Package auto-generated by `reggen` containing data structure + +package pwrmgr_reg_pkg; + + // Param list + parameter int NumWkups = 6; + parameter int SYSRST_CTRL_AON_WKUP_REQ_IDX = 0; + parameter int ADC_CTRL_AON_WKUP_REQ_IDX = 1; + parameter int PINMUX_AON_PIN_WKUP_REQ_IDX = 2; + parameter int PINMUX_AON_USB_WKUP_REQ_IDX = 3; + parameter int AON_TIMER_AON_WKUP_REQ_IDX = 4; + parameter int SENSOR_CTRL_AON_WKUP_REQ_IDX = 5; + parameter int NumRstReqs = 2; + parameter int NumIntRstReqs = 2; + parameter int NumDebugRstReqs = 1; + parameter int ResetMainPwrIdx = 2; + parameter int ResetEscIdx = 3; + parameter int ResetNdmIdx = 4; + parameter int NumAlerts = 1; + + // Address widths within the block + parameter int BlockAw = 7; + + //////////////////////////// + // Typedefs for registers // + //////////////////////////// + + typedef struct packed { + logic q; + } pwrmgr_reg2hw_intr_state_reg_t; + + typedef struct packed { + logic q; + } pwrmgr_reg2hw_intr_enable_reg_t; + + typedef struct packed { + logic q; + logic qe; + } pwrmgr_reg2hw_intr_test_reg_t; + + typedef struct packed { + logic q; + logic qe; + } pwrmgr_reg2hw_alert_test_reg_t; + + typedef struct packed { + struct packed { + logic q; + } main_pd_n; + struct packed { + logic q; + } usb_clk_en_active; + struct packed { + logic q; + } usb_clk_en_lp; + struct packed { + logic q; + } io_clk_en; + struct packed { + logic q; + } core_clk_en; + struct packed { + logic q; + } low_power_hint; + } pwrmgr_reg2hw_control_reg_t; + + typedef struct packed { + logic q; + logic qe; + } pwrmgr_reg2hw_cfg_cdc_sync_reg_t; + + typedef struct packed { + logic q; + } pwrmgr_reg2hw_wakeup_en_mreg_t; + + typedef struct packed { + logic q; + } pwrmgr_reg2hw_reset_en_mreg_t; + + typedef struct packed { + logic q; + } pwrmgr_reg2hw_wake_info_capture_dis_reg_t; + + typedef struct packed { + struct packed { + logic q; + logic qe; + } abort; + struct packed { + logic q; + logic qe; + } fall_through; + struct packed { + logic [5:0] q; + logic qe; + } reasons; + } pwrmgr_reg2hw_wake_info_reg_t; + + typedef struct packed { + struct packed { + logic q; + } main_pd_glitch; + struct packed { + logic q; + } esc_timeout; + struct packed { + logic q; + } reg_intg_err; + } pwrmgr_reg2hw_fault_status_reg_t; + + typedef struct packed { + logic d; + logic de; + } pwrmgr_hw2reg_intr_state_reg_t; + + typedef struct packed { + logic d; + } pwrmgr_hw2reg_ctrl_cfg_regwen_reg_t; + + typedef struct packed { + struct packed { + logic d; + logic de; + } low_power_hint; + } pwrmgr_hw2reg_control_reg_t; + + typedef struct packed { + logic d; + logic de; + } pwrmgr_hw2reg_cfg_cdc_sync_reg_t; + + typedef struct packed { + logic d; + logic de; + } pwrmgr_hw2reg_wake_status_mreg_t; + + typedef struct packed { + logic d; + logic de; + } pwrmgr_hw2reg_reset_status_mreg_t; + + typedef struct packed { + logic d; + logic de; + } pwrmgr_hw2reg_escalate_reset_status_reg_t; + + typedef struct packed { + struct packed { + logic [5:0] d; + } reasons; + struct packed { + logic d; + } fall_through; + struct packed { + logic d; + } abort; + } pwrmgr_hw2reg_wake_info_reg_t; + + typedef struct packed { + struct packed { + logic d; + logic de; + } reg_intg_err; + struct packed { + logic d; + logic de; + } esc_timeout; + struct packed { + logic d; + logic de; + } main_pd_glitch; + } pwrmgr_hw2reg_fault_status_reg_t; + + // Register -> HW type + typedef struct packed { + pwrmgr_reg2hw_intr_state_reg_t intr_state; // [36:36] + pwrmgr_reg2hw_intr_enable_reg_t intr_enable; // [35:35] + pwrmgr_reg2hw_intr_test_reg_t intr_test; // [34:33] + pwrmgr_reg2hw_alert_test_reg_t alert_test; // [32:31] + pwrmgr_reg2hw_control_reg_t control; // [30:25] + pwrmgr_reg2hw_cfg_cdc_sync_reg_t cfg_cdc_sync; // [24:23] + pwrmgr_reg2hw_wakeup_en_mreg_t [5:0] wakeup_en; // [22:17] + pwrmgr_reg2hw_reset_en_mreg_t [1:0] reset_en; // [16:15] + pwrmgr_reg2hw_wake_info_capture_dis_reg_t wake_info_capture_dis; // [14:14] + pwrmgr_reg2hw_wake_info_reg_t wake_info; // [13:3] + pwrmgr_reg2hw_fault_status_reg_t fault_status; // [2:0] + } pwrmgr_reg2hw_t; + + // HW -> register type + typedef struct packed { + pwrmgr_hw2reg_intr_state_reg_t intr_state; // [38:37] + pwrmgr_hw2reg_ctrl_cfg_regwen_reg_t ctrl_cfg_regwen; // [36:36] + pwrmgr_hw2reg_control_reg_t control; // [35:34] + pwrmgr_hw2reg_cfg_cdc_sync_reg_t cfg_cdc_sync; // [33:32] + pwrmgr_hw2reg_wake_status_mreg_t [5:0] wake_status; // [31:20] + pwrmgr_hw2reg_reset_status_mreg_t [1:0] reset_status; // [19:16] + pwrmgr_hw2reg_escalate_reset_status_reg_t escalate_reset_status; // [15:14] + pwrmgr_hw2reg_wake_info_reg_t wake_info; // [13:6] + pwrmgr_hw2reg_fault_status_reg_t fault_status; // [5:0] + } pwrmgr_hw2reg_t; + + // Register offsets + parameter logic [BlockAw-1:0] PWRMGR_INTR_STATE_OFFSET = 7'h 0; + parameter logic [BlockAw-1:0] PWRMGR_INTR_ENABLE_OFFSET = 7'h 4; + parameter logic [BlockAw-1:0] PWRMGR_INTR_TEST_OFFSET = 7'h 8; + parameter logic [BlockAw-1:0] PWRMGR_ALERT_TEST_OFFSET = 7'h c; + parameter logic [BlockAw-1:0] PWRMGR_CTRL_CFG_REGWEN_OFFSET = 7'h 10; + parameter logic [BlockAw-1:0] PWRMGR_CONTROL_OFFSET = 7'h 14; + parameter logic [BlockAw-1:0] PWRMGR_CFG_CDC_SYNC_OFFSET = 7'h 18; + parameter logic [BlockAw-1:0] PWRMGR_WAKEUP_EN_REGWEN_OFFSET = 7'h 1c; + parameter logic [BlockAw-1:0] PWRMGR_WAKEUP_EN_OFFSET = 7'h 20; + parameter logic [BlockAw-1:0] PWRMGR_WAKE_STATUS_OFFSET = 7'h 24; + parameter logic [BlockAw-1:0] PWRMGR_RESET_EN_REGWEN_OFFSET = 7'h 28; + parameter logic [BlockAw-1:0] PWRMGR_RESET_EN_OFFSET = 7'h 2c; + parameter logic [BlockAw-1:0] PWRMGR_RESET_STATUS_OFFSET = 7'h 30; + parameter logic [BlockAw-1:0] PWRMGR_ESCALATE_RESET_STATUS_OFFSET = 7'h 34; + parameter logic [BlockAw-1:0] PWRMGR_WAKE_INFO_CAPTURE_DIS_OFFSET = 7'h 38; + parameter logic [BlockAw-1:0] PWRMGR_WAKE_INFO_OFFSET = 7'h 3c; + parameter logic [BlockAw-1:0] PWRMGR_FAULT_STATUS_OFFSET = 7'h 40; + + // Reset values for hwext registers and their fields + parameter logic [0:0] PWRMGR_INTR_TEST_RESVAL = 1'h 0; + parameter logic [0:0] PWRMGR_INTR_TEST_WAKEUP_RESVAL = 1'h 0; + parameter logic [0:0] PWRMGR_ALERT_TEST_RESVAL = 1'h 0; + parameter logic [0:0] PWRMGR_ALERT_TEST_FATAL_FAULT_RESVAL = 1'h 0; + parameter logic [0:0] PWRMGR_CTRL_CFG_REGWEN_RESVAL = 1'h 1; + parameter logic [0:0] PWRMGR_CTRL_CFG_REGWEN_EN_RESVAL = 1'h 1; + parameter logic [7:0] PWRMGR_WAKE_INFO_RESVAL = 8'h 0; + parameter logic [5:0] PWRMGR_WAKE_INFO_REASONS_RESVAL = 6'h 0; + parameter logic [0:0] PWRMGR_WAKE_INFO_FALL_THROUGH_RESVAL = 1'h 0; + parameter logic [0:0] PWRMGR_WAKE_INFO_ABORT_RESVAL = 1'h 0; + + // Register index + typedef enum int { + PWRMGR_INTR_STATE, + PWRMGR_INTR_ENABLE, + PWRMGR_INTR_TEST, + PWRMGR_ALERT_TEST, + PWRMGR_CTRL_CFG_REGWEN, + PWRMGR_CONTROL, + PWRMGR_CFG_CDC_SYNC, + PWRMGR_WAKEUP_EN_REGWEN, + PWRMGR_WAKEUP_EN, + PWRMGR_WAKE_STATUS, + PWRMGR_RESET_EN_REGWEN, + PWRMGR_RESET_EN, + PWRMGR_RESET_STATUS, + PWRMGR_ESCALATE_RESET_STATUS, + PWRMGR_WAKE_INFO_CAPTURE_DIS, + PWRMGR_WAKE_INFO, + PWRMGR_FAULT_STATUS + } pwrmgr_id_e; + + // Register width information to check illegal writes + parameter logic [3:0] PWRMGR_PERMIT [17] = '{ + 4'b 0001, // index[ 0] PWRMGR_INTR_STATE + 4'b 0001, // index[ 1] PWRMGR_INTR_ENABLE + 4'b 0001, // index[ 2] PWRMGR_INTR_TEST + 4'b 0001, // index[ 3] PWRMGR_ALERT_TEST + 4'b 0001, // index[ 4] PWRMGR_CTRL_CFG_REGWEN + 4'b 0011, // index[ 5] PWRMGR_CONTROL + 4'b 0001, // index[ 6] PWRMGR_CFG_CDC_SYNC + 4'b 0001, // index[ 7] PWRMGR_WAKEUP_EN_REGWEN + 4'b 0001, // index[ 8] PWRMGR_WAKEUP_EN + 4'b 0001, // index[ 9] PWRMGR_WAKE_STATUS + 4'b 0001, // index[10] PWRMGR_RESET_EN_REGWEN + 4'b 0001, // index[11] PWRMGR_RESET_EN + 4'b 0001, // index[12] PWRMGR_RESET_STATUS + 4'b 0001, // index[13] PWRMGR_ESCALATE_RESET_STATUS + 4'b 0001, // index[14] PWRMGR_WAKE_INFO_CAPTURE_DIS + 4'b 0001, // index[15] PWRMGR_WAKE_INFO + 4'b 0001 // index[16] PWRMGR_FAULT_STATUS + }; + +endpackage diff --git a/src/pwrmgr/rtl/pwrmgr_slow_fsm.sv b/src/pwrmgr/rtl/pwrmgr_slow_fsm.sv new file mode 100644 index 0000000..f78105a --- /dev/null +++ b/src/pwrmgr/rtl/pwrmgr_slow_fsm.sv @@ -0,0 +1,358 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Power Manager Slow FSM +// + +`include "prim_assert.sv" + +module pwrmgr_slow_fsm import pwrmgr_pkg::*; ( + input clk_i, + input rst_ni, + input rst_main_ni, + + // sync'ed requests from peripherals + input wakeup_i, + input reset_req_i, + + // interface with fast fsm + output logic req_pwrup_o, + output logic pwrup_cause_toggle_o, + output pwrup_cause_e pwrup_cause_o, + input ack_pwrup_i, + input req_pwrdn_i, + output logic ack_pwrdn_o, + output logic rst_req_o, + output logic fsm_invalid_o, + input clr_req_i, + output logic usb_ip_clk_en_o, + input usb_ip_clk_status_i, + + // low power entry configuration + input main_pd_ni, + input io_clk_en_i, + input core_clk_en_i, + input usb_clk_en_lp_i, + input usb_clk_en_active_i, + + // AST interface + input pwr_ast_rsp_t ast_i, + output pwr_ast_req_t ast_o +); + + slow_pwr_state_e state_q, state_d; + + // All signals crossing over to other domain must be flopped + pwrup_cause_e cause_q, cause_d; + logic cause_toggle_q, cause_toggle_d; + logic req_pwrup_q, req_pwrup_d; + logic ack_pwrdn_q, ack_pwrdn_d; + + logic clk_active; + + // All power signals and signals going to analog logic are flopped to avoid transitional glitches + logic pd_nq, pd_nd; + logic pwr_clamp_q, pwr_clamp_d; + logic pwr_clamp_env_q, pwr_clamp_env_d; + logic core_clk_en_q, core_clk_en_d; + logic io_clk_en_q, io_clk_en_d; + logic usb_clk_en_q, usb_clk_en_d; + logic fsm_invalid_q, fsm_invalid_d; + + logic all_clks_valid; + logic all_clks_invalid; + + // when to monitor pok for instability + // These are monitored only in active and low power states + logic mon_main_pok; + logic set_main_pok; + logic async_main_pok_st; + logic main_pok_st; + + // all clocks sources are valid + // if clocks (usb) not configured to be active, then just bypass check + assign all_clks_valid = ast_i.core_clk_val & + ast_i.io_clk_val & + (~usb_clk_en_active_i | ast_i.usb_clk_val); + + // usb clock state during low power is not completely controlled by + // input. + // if main_pd_ni is 0, (ie power will be turned off), then the low power + // state of usb is also off. If main_pd_ni is 1 (power will be kept on), + // then the low power state of usb is directly controlled. + logic usb_clk_en_lp; + assign usb_clk_en_lp = main_pd_ni & usb_clk_en_lp_i; + + // all other clocks are also diasbled when power is turned off. + logic core_clk_en; + logic io_clk_en; + assign core_clk_en = main_pd_ni & core_clk_en_i; + assign io_clk_en = main_pd_ni & io_clk_en_i; + + // if clocks were configured to turn off, make sure val is invalid + // if clocks were not configured to turn off, just bypass the check + assign all_clks_invalid = (core_clk_en | ~ast_i.core_clk_val) & + (io_clk_en | ~ast_i.io_clk_val) & + (usb_clk_en_lp | ~ast_i.usb_clk_val); + + // ensure that clock controls are constantly re-evaluated and not just + // in one specific state + // When fsm is invalid, force the clocks to be on such that the fast fsm + // can forcibly reset the system. + // In the event the clocks cannot be turned on even when forced, the fsm + // invalid signal forces power to turn off. + assign core_clk_en_d = fsm_invalid_q | (clk_active | core_clk_en); + assign io_clk_en_d = fsm_invalid_q | (clk_active | io_clk_en); + assign usb_clk_en_d = fsm_invalid_q | (clk_active ? usb_clk_en_active_i : usb_clk_en_lp); + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + cause_q <= Por; + cause_toggle_q <= 1'b0; + pd_nq <= 1'b1; + pwr_clamp_q <= 1'b1; + pwr_clamp_env_q <= 1'b1; + core_clk_en_q <= 1'b0; + io_clk_en_q <= 1'b0; + usb_clk_en_q <= 1'b0; + req_pwrup_q <= 1'b0; + ack_pwrdn_q <= 1'b0; + fsm_invalid_q <= 1'b0; + end else begin + cause_q <= cause_d; + cause_toggle_q <= cause_toggle_d; + pd_nq <= pd_nd; + pwr_clamp_q <= pwr_clamp_d; + pwr_clamp_env_q <= pwr_clamp_env_d; + core_clk_en_q <= core_clk_en_d; + io_clk_en_q <= io_clk_en_d; + usb_clk_en_q <= usb_clk_en_d; + req_pwrup_q <= req_pwrup_d; + ack_pwrdn_q <= ack_pwrdn_d; + fsm_invalid_q <= fsm_invalid_d; + end + end + + // SEC_CM: FSM.SPARSE + `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, slow_pwr_state_e, SlowPwrStateReset) + + always_comb begin + state_d = state_q; + cause_d = cause_q; + pd_nd = pd_nq; + cause_toggle_d = cause_toggle_q; + pwr_clamp_d = pwr_clamp_q; + pwr_clamp_env_d = pwr_clamp_env_q; + + req_pwrup_d = req_pwrup_q; + ack_pwrdn_d = ack_pwrdn_q; + fsm_invalid_d = fsm_invalid_q; + + set_main_pok = '0; + + clk_active = '0; + + unique case(state_q) + + SlowPwrStateReset: begin + state_d = SlowPwrStateMainPowerOn; + cause_d = Por; + end + + SlowPwrStateLowPower: begin + // reset request behaves identically to a wakeup, other than the power-up cause being + // different + if (wakeup_i || reset_req_i) begin + state_d = SlowPwrStateMainPowerOn; + cause_toggle_d = ~cause_toggle_q; + cause_d = reset_req_i ? Reset : Wake; + end + end + + SlowPwrStateMainPowerOn: begin + pd_nd = 1'b1; + + if (main_pok_st) begin + set_main_pok = 1'b1; + pwr_clamp_env_d = 1'b0; + state_d = SlowPwrStatePwrClampOff; + end + end + + SlowPwrStatePwrClampOff: begin + pwr_clamp_d = 1'b0; + state_d = SlowPwrStateClocksOn; + end + + SlowPwrStateClocksOn: begin + clk_active = 1'b1; + + if (all_clks_valid) begin + state_d = SlowPwrStateReqPwrUp; + end + end + + SlowPwrStateReqPwrUp: begin + clk_active = 1'b1; + req_pwrup_d = 1'b1; + + // req_pwrdn_i should be 0 here to indicate + // the request from the previous round has definitely completed + if (ack_pwrup_i && !req_pwrdn_i) begin + req_pwrup_d = 1'b0; + state_d = SlowPwrStateIdle; + end + end + + SlowPwrStateIdle: begin + // ack_pwrup_i should be 0 here to indicate + // the ack from the previous round has definitively completed + clk_active = 1'b1; + + if (req_pwrdn_i && !ack_pwrup_i) begin + state_d = SlowPwrStateAckPwrDn; + end + end + + SlowPwrStateAckPwrDn: begin + clk_active = 1'b1; + ack_pwrdn_d = 1'b1; + + if (!req_pwrdn_i) begin + ack_pwrdn_d = 1'b0; + state_d = SlowPwrStateClocksOff; + end + end + + SlowPwrStateClocksOff: begin + if (all_clks_invalid) begin + // if main power is turned off, assert early clamp ahead + pwr_clamp_env_d = ~main_pd_ni; + state_d = SlowPwrStatePwrClampOn; + end + end + + SlowPwrStatePwrClampOn: begin + // if main power is turned off, assert clamp ahead + pwr_clamp_d = pwr_clamp_env_q; + state_d = SlowPwrStateMainPowerOff; + end + + SlowPwrStateMainPowerOff: begin + pd_nd = main_pd_ni; + + // Proceed if power is already off, or if there was no intent to + // turn off the power. + if (!main_pok_st | main_pd_ni) begin + state_d = SlowPwrStateLowPower; + end + end + + // Very terminal state, kill everything + // Signal the fast FSM if it somehow is still running. + // Both FSMs are now permanently out of sync and the device + // must be rebooted. + // SEC_CM: FSM.TERMINAL + default: begin + fsm_invalid_d = 1'b1; + pd_nd = 1'b0; + pwr_clamp_d = 1'b1; + end + endcase // unique case (state_q) + end // always_comb + + // If the main_pok ever drops, capture that glitch + // and hold onto it for reset escalation + always_ff @(posedge clk_i or negedge rst_main_ni) begin + if (!rst_main_ni) begin + async_main_pok_st <= '0; + end else begin + async_main_pok_st <= ast_i.main_pok; + end + end + + // We need to synchronize the above because the reset + // may cause the signal to change at any time. + prim_flop_2sync # ( + .Width(1) + ) u_main_pok_sync ( + .clk_i, + .rst_ni, + .d_i(async_main_pok_st), + .q_o(main_pok_st) + ); + + // Determine when pok should be monitored + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + mon_main_pok <= '0; + end else if (!pd_nd && mon_main_pok) begin + mon_main_pok <= 1'b0; + end else if (set_main_pok) begin + mon_main_pok <= 1'b1; + end + end + + // power stability reset request + // If the main power becomes unstable for whatever reason, + // request reset + // SEC_CM: MAIN_PD.RST.LOCAL_ESC + logic pwr_rst_req; + assign pwr_rst_req = mon_main_pok & ~main_pok_st; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + rst_req_o <= '0; + end else if (clr_req_i) begin + rst_req_o <= '0; + end else begin + rst_req_o <= rst_req_o | pwr_rst_req; + end + end + + assign pwrup_cause_o = cause_q; + assign pwrup_cause_toggle_o = cause_toggle_q; + assign req_pwrup_o = req_pwrup_q; + assign ack_pwrdn_o = ack_pwrdn_q; + assign fsm_invalid_o = fsm_invalid_q; + + assign ast_o.core_clk_en = core_clk_en_q; + assign ast_o.io_clk_en = io_clk_en_q; + // usb's enable is handshake with pwr_fsm, as it can be turned on/off + // outside of the normal low power sequence + prim_flop #( + .Width(1), + .ResetValue('0) + ) u_usb_clk_en ( + .clk_i, + .rst_ni, + // immediate enable + // graceful disable when status is 0 + .d_i(usb_clk_en_q | usb_ip_clk_status_i), + .q_o(ast_o.usb_clk_en) + ); + assign usb_ip_clk_en_o = usb_clk_en_q; + + assign ast_o.main_pd_n = pd_nq; + assign ast_o.pwr_clamp_env = pwr_clamp_env_q; + assign ast_o.pwr_clamp = pwr_clamp_q; + // This is hardwired to 1 all the time + assign ast_o.slow_clk_en = 1'b1; + + + //////////////////////////// + /// Unused + //////////////////////////// + + logic unused_slow_clk_val; + assign unused_slow_clk_val = ast_i.slow_clk_val; + + //////////////////////////// + /// Assertion + //////////////////////////// + // Under normal circumstances, this should NEVER fire + // May need to add a signal to disable this check for simulation + `ASSERT(IntRstReq_A, pwr_rst_req == '0) + +endmodule diff --git a/src/pwrmgr/rtl/pwrmgr_wake_info.sv b/src/pwrmgr/rtl/pwrmgr_wake_info.sv new file mode 100644 index 0000000..ada62ea --- /dev/null +++ b/src/pwrmgr/rtl/pwrmgr_wake_info.sv @@ -0,0 +1,74 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Power Manager Wake Information +// + +`include "prim_assert.sv" + +module pwrmgr_wake_info import pwrmgr_pkg::*; import pwrmgr_reg_pkg::*; +( + input clk_i, + input rst_ni, + input wr_i, + input [TotalWakeWidth-1:0] data_i, + input start_capture_i, + input record_dis_i, + input [NumWkups-1:0] wakeups_i, + input fall_through_i, + input abort_i, + output pwrmgr_hw2reg_wake_info_reg_t info_o +); + + logic record_en; + + // detect rising edge of start_capture_i + logic start_capture_q1, start_capture; + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + start_capture_q1 <= 1'b1; + end else begin + start_capture_q1 <= start_capture_i; + end + end + + assign start_capture = start_capture_i & ~start_capture_q1; + + // generate the record enbale signal + // HW enables the recording + // Software can suppress the recording or disable it + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + record_en <= 1'b0; + end else if (start_capture && !record_dis_i) begin + // if not disabled by software + // a recording enable puls by HW starts recording + record_en <= 1'b1; + end else if (record_dis_i && record_en) begin + // if recording is already ongoing + // a disable command by software shuts things down + record_en <= 1'b0; + end + end + + logic [TotalWakeWidth-1:0] info; + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + info <= '0; + end else if (wr_i) begin + info <= info & ~data_i; // W1C + end else if (record_en) begin // If set once, hold until clear + info[0 +: NumWkups] <= info[0 +: NumWkups] | wakeups_i; + info[NumWkups +: 2] <= info[NumWkups +: 2] | {abort_i, fall_through_i}; + end + end + + // assign outputs + assign info_o.abort.d = info[NumWkups + 1]; + assign info_o.fall_through.d = info[NumWkups]; + assign info_o.reasons = info[NumWkups-1:0]; + + + +endmodule diff --git a/src/pwrmgr/util/reg_pwrmgr.py b/src/pwrmgr/util/reg_pwrmgr.py new file mode 100755 index 0000000..736fbb8 --- /dev/null +++ b/src/pwrmgr/util/reg_pwrmgr.py @@ -0,0 +1,42 @@ +#!/usr/bin/env python3 +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +r"""Convert mako template to Hjson register description +""" +import argparse +import sys +from io import StringIO + +from mako.template import Template + + +def main(): + parser = argparse.ArgumentParser(prog="reg_pwrmgr") + parser.add_argument('input', + nargs='?', + metavar='file', + type=argparse.FileType('r'), + default=sys.stdin, + help='input template file') + parser.add_argument('--n_wkups', + type=int, + default=16, + help='Number of Wakeup sources') + + args = parser.parse_args() + + # Determine output: if stdin then stdout if not then ?? + out = StringIO() + + reg_tpl = Template(args.input.read()) + out.write( + reg_tpl.render(NumWkups=args.n_wkups)) + + print(out.getvalue()) + + out.close() + + +if __name__ == "__main__": + main() diff --git a/src/tlul/BUILD b/src/tlul/BUILD new file mode 100644 index 0000000..ca0cd07 --- /dev/null +++ b/src/tlul/BUILD @@ -0,0 +1,12 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +package(default_visibility = ["//visibility:public"]) + +filegroup( + name = "all_files", + srcs = glob(["**"]) + [ + "//hw/ip/tlul/data:all_files", + ], +) diff --git a/src/tlul/README.md b/src/tlul/README.md new file mode 100644 index 0000000..98509a2 --- /dev/null +++ b/src/tlul/README.md @@ -0,0 +1,694 @@ +# Bus Specification + +# Overview + +This document specifies the bus functionality within a Comportable top level +system. This includes the bus protocol and all hardware IP that supports +creating the network on chip within that framework. + +## Features + +- Support for multiple bus hosts and bus devices1 +- Support for multiple clock domains +- Support for multiple outstanding requests +- Extendability for 32b or 64b data widths +- Extendability for flexible address widths +- Extendability for security features +- Low pin-count / area overhead +- Support for transaction sizes up to bus width (byte, 2B, 4B); no + support for bursts +- Suite of bus primitives to aid in fast fabric generation + +1lowRISC is avoiding the fraught terms master/slave and defaulting +to host/device where applicable. + +## Description + +For chip-level interconnect, Comportable devices will be using +[TileLink](https://static.dev.sifive.com/docs/tilelink/tilelink-spec-1.7-draft.pdf) +as its bus fabric protocol. For the purposes of our performance +requirement needs, the Uncached Lightweight (TL-UL) variant will +suffice. There is one minor modification to add the user extensions. This +is highlighted below, but otherwise all functionality follows the official +specification. The main signal names are kept the same as TL-UL and the +user extension signal groups follow the same timing and naming conventions +used in the TL-UL specification. Existing TL-UL IP blocks may be used +directly in devices that do not need the additional sideband signals, +or can be straightforwardly adapted to use the added features. + +TL-UL is a lightweight bus that combines the point-to-point +split-transaction features of the powerful TileLink (or AMBA AXI) +5-channel bus without the high pin-count overhead. It is intended to be +about on par of pincount with APB but with the transaction performance of +AXI-4, modulo the following assumptions. + +- Only one request (read or write) per cycle +- Only one response (read or write) per cycle +- No burst transactions + +Bus primitives are provided in the lowRISC IP library. These are +described later in this document. These primitives can be combined to form +a flexible crossbar of any M hosts to any N devices. As of this writing, +these crossbars are generated programmatically through usage of configuration files. +See the [tlgen reference manual](../../../util/tlgen/README.md) for more details. + +## Compatibility + +With the exception of the user extensions, the bus is +compliant with TileLink-UL. The bus primitives, hosts and peripherals +developed using the extended specification can be used with +blocks using the base specification. As a receiver baseline blocks +ignore the user signals and as a +source will generate a project-specific default value. Alternatively, +the blocks can be easily modified to make use of the user extensions. + +# Theory of Operations + +## Signals + +The table below lists all of the TL-UL signals. "Direction" is +w.r.t. a bus host, signals marked as output will be in the verilog +`typedef struct` tagged as host-to-device (`tl_h2d_t`) and those marked +as input will be in the device-to-host struct (`tl_d2h_t`). The literal +`typedef structs` follow. Size qualifiers are described below. The table +and structs include the additional (non-TL-UL standard) user extension +signals per direction to carry chip specific user bits. + +The function of the user bits are separately described in a separate table. + +| Signal Name | Direction | Description | +| --- | --- | --- | +| `a_valid` | output | Request from host is valid | +| `a_ready` | input | Request from host is accepted by device | +| `a_opcode[2:0]` | output | Request opcode (read, write, or partial write) | +| `a_param[2:0]` | output | unused | +| `a_address[AW-1:0]` | output | Request address of configurable width | +| `a_data[DW-1:0]` | output | Write request data of configurable width | +| `a_source[AIW-1:0]` | output | Request identifier of configurable width | +| `a_size[SZW-1:0]` | output | Request size (requested size is 2^`a_size`, thus 0 = byte, 1 = 16b, 2 = 32b, 3 = 64b, etc) | +| `a_mask[DBW-1:0]` | output | Write strobe, one bit per byte indicating which lanes of data are valid for this write request | +| `a_user` | output | Request attributes of configurable width, use TBD. **This is an augmentation to the TL-UL specification.** | +| `d_valid` | input | Response from device is valid | +| `d_ready` | output | Response from device is accepted by host | +| `d_opcode[2:0]` | input | Response opcode (Ack or Data) | +| `d_error` | input | Response is in error | +| `d_param[2:0]` | input | Response parameter (unused) | +| `d_size[SZW-1:0]` | input | Response data size | +| `d_data[DW-1:0]` | input | Response data of configurable width | +| `d_source[AIW-1:0]` | input | Bouncing of request ID of configurable width | +| `d_sink[DIW-1:0]` | input | Response ID of configurable width (possibly unused) | +| `d_user[DUW-1:0]` | input | Response attributes of configurable width; includes error responses plus other attributes TBD. **This is an augmentation to the TL-UL specification.** | + +The `a_user` bus contains several signals +- `instr_type` - controls whether the transaction is an instruction fetch type +- `cmd_intg` - carries the command integrity of the transaction +- `data_intg` - carries the write data integrity of the transaction + +The `d_user` bus contains several signals +- `rsp_intg` - carries the response integrity of the transaction +- `data_intg` - carries the read data integrity of the transaction + +The user bus is primarily used to distinguish data / instruction transactions while also supporting the bus integrity scheme. + +There are eight bus width parameters, defined here. Some are generated +widths based upon the other parameter sizes. + +- `AW`: width of address bus, default 32 +- `DW`: width of data bus, default 32 +- `DBW`: number of data bytes, generated == `DW/8` +- `SZW`: size width, covers 2^(x) <= `DBW`; (2 bit for 4B) +- `AIW`: width of address source (ID) bus, default 8 +- `DUW`: width of device user bits, default 4 +- `DIW`: width of sink bits, default 1 + +All widths are expected to be fixed for an entire project and referred +to in (what is currently called) `top_pkg`. The contents of `top_pkg` +(to define the widths) and `tlul_pkg` (to define the bus structs) are +given below. + +### Reset Timing + +Section 3.2.2 of the +[TileLink specification (1.7.1)](https://sifive.cdn.prismic.io/sifive%2F57f93ecf-2c42-46f7-9818-bcdd7d39400a_tilelink-spec-1.7.1.pdf) +has a requirement on TL-UL hosts ("masters" in TileLink terminology) that "`valid` signals must be driven LOW for at least 100 cycles while reset is asserted." +The TL-UL collateral within this library does **not** have this requirement on its TL-UL host drivers. +TL-UL devices within the library can tolerate shorter reset windows. +(See the reset section of the [Comportability Specification](../../../doc/contributing/hw/comportability/README.md) +for details on reset requirements.) + +### Signal and Struct Definitions + +The following shows Verilog structs to define the above parameters +and signals. + +```systemverilog +package top_pkg; + localparam TL_AW=32; + localparam TL_DW=32; + localparam TL_AIW=8; + localparam TL_DIW=1; + localparam TL_DUW=4; + localparam TL_DBW=(TL_DW>>3); + localparam TL_SZW=$clog2($clog2(TL_DBW)+1); +endpackage +``` + +```systemverilog +package tlul_pkg; + typedef enum logic [2:0] { + PutFullData = 3'h 0, + PutPartialData = 3'h 1, + Get = 3'h 4 + } tl_a_op_e; + typedef enum logic [2:0] { + AccessAck = 3'h 0, + AccessAckData = 3'h 1 + } tl_d_op_e; + + typedef struct packed { + logic [6:0] rsvd1; // Reserved for future use + logic parity_en; + logic [7:0] parity; // Use only lower TL_DBW bit + } tl_a_user_t; + + typedef struct packed { + logic a_valid; + tl_a_op_e a_opcode; + logic [2:0] a_param; + logic [top_pkg::TL_SZW-1:0] a_size; + logic [top_pkg::TL_AIW-1:0] a_source; + logic [top_pkg::TL_AW-1:0] a_address; + logic [top_pkg::TL_DBW-1:0] a_mask; + logic [top_pkg::TL_DW-1:0] a_data; + tl_a_user_t a_user; + + logic d_ready; + } tl_h2d_t; + + typedef struct packed { + logic d_valid; + tl_d_op_e d_opcode; + logic [2:0] d_param; + logic [top_pkg::TL_SZW-1:0] d_size; + logic [top_pkg::TL_AIW-1:0] d_source; + logic [top_pkg::TL_DIW-1:0] d_sink; + logic [top_pkg::TL_DW-1:0] d_data; + logic [top_pkg::TL_DUW-1:0] d_user; + logic d_error; + + logic a_ready; + } tl_d2h_t; + +endpackage +``` + +### Usage of Signals + +#### Usage of Address + +All signaling for host-request routing is encapsulated in the `a_addr` signal. +(See section 5.3 of the TileLink specification). +For a bus host to designate which device it is talking to, it only needs to indicate the correct device register/memory address. +The other host signals (namely `a_source` and `a_user`) do not enter into the address calculation. +All request steering must thus be made as a function of the address. + +#### Usage of Source and Sink ID Bits + +The `a_source` and `d_source` signals are used to steer the response from +a device back to a host through bus primitives. (See primitives section +that follows). It can also be used to ascribe request identifiers by a +host when response reordering is required (since TL-UL does not guarantee +in-order responses). For permission detection, static host identifiers +will be transmitted in the user field (see below). + +Some bus primitives, such as `M:1` sockets, need to add source bits +during request routing in order to be able to correctly route the +response. For instance, if one destination is addressed by N potential +hosts, log2N more source ID bits need to be added to the +outgoing request. The fabric architect needs to ensure that the attribute +`AIW` is big enough to cover the number of outstanding requests hosts +can make and the maximum source ID growth that could be added by bus +primitives. At this time, `AIW` is assumed to be 8 bits of ID growth, but +this is likely overkill. The fabric also needs to allow for how many host +ID bits are needed, for instance if converting from an AXI host that uses +`RID` or `WID`, enough bits must be provided to maintain those ID values. + +##### Source ID growth + +When a bus primitive needs to add source ID bits, it shifts left the +incoming `a_source` and post-pends its necessary sub-source bits. For +instance, if a 5:1 socket is needed, 3 sub-source bits are generated to +distinguish between hosts 0 through 4. So an 8-bit outgoing `a_source` +would be `{a_source_inbound[4:0],subsource[2:0]}`. When the response +returns, those 3 sub-source bits are shifted off, with `'0'` bits +shifted into the top, and returned to the originator's `d_source`. It +is recommended to have assertions in place to ensure no significant bits +of `a_source` are lost in `M:1` sockets. See the `M:1` socket primitive +for more details. + +##### Source ID requirements for host elements + +The potential for source ID growth (and contraction in the response) +implies that hosts may only use the low bits of the identifier and cannot +assume the entire `AIW` bits will be returned intact. If there are any hosts +that need more source bits returned than the host's maximum number of +outstanding transactions (for example the host uses some source bits as +internal sub-unit identifiers and some bits as transaction IDs from that +subunit) then the `AIW` value needs to be set accordingly. + +##### Source ID requirements for device elements + +All bus devices must simply return the associated `a_source` on the +response `d_source` bus. + +##### Source ID requirements for bus primitives + +Most bus primitives simply pass source ID bits opaquely from host end to +device end. The exception is for `M:1` sockets (see ID growth above). Other +elements (`1:N` sockets, domain crossing FIFOs, etc) should not modify +the `a_source` and `d_source` values, but pass them along. + +##### Sink ID Usage + +At this time there is no defined use for `d_sink`, but the TileLink-UL +protocol allows configurable bits to be passed back to the host to +indicate who responded. In theory this could be used as a security +guarantee, to ensure that the appropriate responder was targeted. At +this time the configurable width for sink is turned down to one bit. + +#### Usage of User Bits + +User bits are added to the TileLink-UL specification in order to prepare +for command and response modification in future IP. These are effectively +modifiers to the transactions that can qualify the request and the +response. The user bits follow the same timing as the source ID bits: +`a_user` matches `a_source` and `d_user` matches `d_source`. Usage of +user bits within a project must be assigned project-wide, but the bus +fabric does not rely on them for transport, and should pass the user +bits on blindly. Bus hosts and devices must understand their usage and +apply them appropriately. + +The following list gives examples of future usage for `a_user` and +`d_user` bits. + +- `a_user` modifications + - Instruction Type + - This indicates whether the transaction originates from a code fetch or data fetch. + - This attribute is used by downstream consumers to provide separate privilege control based on transaction type. + - Command Integrity + - This is the calculated integrity of the instruction type, transaction address, transaction op code and mask. + - The integrity is checked by downstream consumers to ensure the transaction has not been tampered. + + - Data Integrity + - This is calculated integrity of the write data. + - The integrity is checked by downstream consumers to ensure the transaction has not been tampered. + +- `d_user` modifications + - Response Integrity + - This is the calculated integrity of the response op code, response size and response error. + - This integrity is checked by the transaction originator to ensure the response has not been tampered. + + - Data Integrity + - This is the calculated integrity of the response read data. + - This integrity is checked by the transaction originator to ensure the response has not been tampered. + +#### Usage of Opcode, Size and Mask + +The request opcode (`a_opcode`) can designate between a write (`'Put'`) +and a read (`'Get'`) transaction. Writes can be designated as full +(`'PutFullData'`) or partial (`'PutPartialData'`) within the opcode +space. The request size (`a_size`) and mask (`a_mask`) is defined for +all read and write operations. Opcode (`a_opcode`) definitions are +shown below. Responses also have opcodes (`d_opcode`) to indicate read +response (`'AccessAckData'`) and write response (`'AccessAck'`). Error +indications are available on either with the `d_error` bit. Each bus +device has an option to support or not support the full variety of +bus transaction sizes. Their support will be documented in the device +specification. + +It should be noted that, even though non-contiguous `a_mask` values like +`0b1001` are permitted by the TL-UL spec, the TL-UL hosts within this project +**do not leverage non-contiguous masks**. I.e., the TL-UL hosts will only assert +`a_mask` values from the following restricted set for 32bit transfers: +``` +{'b0000, 'b0001, 'b0010, 'b0100, 'b1000, 'b0011, 'b0110, 'b1100, 'b0111, 'b1110, 'b1111}. +``` +The TL-UL devices within the project may or may not support certain subword +masks (both non-contiguous or contiguous ones), and they have the right to +assert `d_error` if they don't. + +| `a_opcode[2:0]` value | Name | Definition | +| :---: | :---: | --- | +| `3'b000` | `PutFullData` | Write of full bus width. `a_size` should be `'h2` to indicate 32b write (or `'h3` if/when 64b bus width is supported), though the bus specification allows these to be defined otherwise (see `PutPartialData` below) | +| `3'b001` | `PutPartialData` | Write of partial bus width. `a_size[SZW-1:0]` indicates how many bytes are transmitted. The encoding is `2^a_size` so `'h0` indicates 1 byte, `'h1` indicates 2 bytes, `'h2` indicates 4 bytes, etc. The lower bits of `a_address` are valid to indicate sub-word addressing, and the bits of `a_mask[DBW-1:0]` should indicate valid byte lanes. | +| `3'b100` | `Get` | Read of full bus width. The bus specification allows these to be defined otherwise (see PutPartialData above) for reads of sub-bus-width. | +| `3'b01x, 3'b101, 3'b11x` | `undefined` | All other opcodes are undefined. Bus devices should return an error. | + +| `d_opcode[2:0]` value | Name | Definition | +| :---: | :---: | --- | +| `3'b000` | `AccessAck` | Write command acknowledgement, no data | +| `3'b001` | `AccessAckData` | Read command acknowledgement, data valid on `d_data` | +| `3'b01x, 3'b1xx` | `undefined` | All other opcodes are undefined and should return an error. | + +#### Explicit Error Cases + +The TL-UL devices in this project contain a set of HW protocol checkers that raise a runtime error (`d_error`) if the request is in violation. +In particular, the following properties are checked: + +1. Wrong opcode, +2. Wrong combination of `a_addr[1:0]`, `a_size`, `a_mask`, for example: + - `a_size` must not be greater than `2`, + - Inactive lanes must be marked with `'b0` in `a_mask`, + - `PutFullData` must mark all active lanes with a `'b1` in `a_mask`, +3. Non-contiguous mask may lead to an error, depending on the device support (see previous section), +4. Register files always assume aligned 32bit accesses, see also [register tool manual](../../../util/reggen/README.md#error-responses), +5. Accesses to non-existent addresses. + +On the host side, orphaned responses (i.e. responses that do not have a valid request counterpart) and responses with the wrong opcode will be discarded. +It is planned to raise a critical hardware error that can be detected and reacted upon via other subsystems in those cases, but that feature has not been implemented yet. + +Note that the above checks also cover cases which are in principle allowed by the TL-UL spec, but are not supported by the hosts and devices within this project. +Further, devices and hosts may implement additional more restrictive checks, if needed. + +The remaining, basic properties as specified in the TL-UL spec are enforced at design time using assertions, and hence no additional hardware checkers are implemented to check for those properties (see also [TL-UL Protocol Checker Specification](./doc/TlulProtocolChecker.md)). + +The interconnect does not possess additional hardware mechanisms to detect and handle interconnect deadlocks due to malicious tampering attempts. +The reasons for this are that +1. the space of potential errors and resolutions would be very large, thus unnecessarily complicating the design, +2. any tampering attempt leading to an unresponsive system will eventually be detected by other subsystems within the top level system. + +### Bus Integrity Scheme +To be filled in. + + +## Timing Diagrams + +This section shows the timing relationship on the bus for writes with +response, and reads with response. This shows a few transactions, see +the TileLink specification for more examples. + +```wavejson +{ + signal: [ + { name: 'clk_i', wave: 'p...................' }, + { name: 'a_valid', wave: '0.1....0101...0.....' }, + { name: 'a_ready', wave: '0.1..01010...10.....' }, + { name: 'a_source', wave: '0.3333.0303...0.....', data: ['I0','I1','I2','I3','I4','I5'] }, + { name: 'a_opcode', wave: '0.3..3.0303...0.....', data: ['put-full','put-partial','pf', 'put-partial'] }, + { name: 'a_addr', wave: '703333.0303...7.....', data: ['A0', 'A1','A2','A3','A4','A5'] }, + { name: 'a_data', wave: '703333.0303...7.....', data: ['D0', 'D1','D2','D3','D4','D5'] }, + { name: 'a_size', wave: '703..3.0303...7.....', data: ['2', '0','2','1'] }, + { name: 'a_mask', wave: '7...03.7703...7.....', data: ['M3', 'M5'] }, + { name: 'a_user', wave: '0.3333.0303...0.....', data: ['AU0','AU1','AU2','AU3','AU4','AU5'] }, + {}, + { name: 'd_valid', wave: '0....1....0101....0.' }, + { name: 'd_ready', wave: '0......1..010...1.0.' }, + { name: 'd_source', wave: '7...03..330304...38.', data: ['I0','I1','I2','I3','I4','I5'] }, + { name: 'd_opcode', wave: '7...03....0304...38.', data: ['ACK','ACK','ACK'] }, + { name: 'd_user', wave: '7...03..330304...38.', data: ['DU0','DU1','DU2','DU3','DU4','DU5'] }, + { name: 'd_error', wave: '0............1...0..' }, + ], + head: { + text: 'TileLink-UL write transactions', + }, + foot: { + text: 'six write transactions (four full, two partial) with various req/ready delays, error on I4 response', + } +} +``` + +```wavejson +{ + signal: [ + { name: 'clk_i', wave: 'p...................' }, + { name: 'a_valid', wave: '0.1....0101...0.....' }, + { name: 'a_ready', wave: '0.1..01010...10.....' }, + { name: 'a_source', wave: '703333.0303...7.....', data: ['I0', 'I1','I2','I3','I4','I5'] }, + { name: 'a_opcode', wave: '0.3....0303...7.....', data: ['get', 'get', 'get'] }, + { name: 'a_addr', wave: '703333.0303...7.....', data: ['A0', 'A1','A2','A3','A4','A5'] }, + { name: 'a_user', wave: '703333.0303...7.....', data: ['AU0', 'AU1','AU2','AU3','AU4','AU5'] }, + {}, + { name: 'd_valid', wave: '0....1....0101....0.' }, + { name: 'd_ready', wave: '0......1..010...1.0.' }, + { name: 'd_source', wave: '7...03..330304...38.', data: ['I0', 'I1','I2','I3','I4','I5'] }, + { name: 'd_data', wave: '7...03..330304...38.', data: ['D0', 'D1','D2','D3','D4','D5'] }, + { name: 'd_opcode', wave: '7...03....0304...38.', data: ['DATA', 'DATA','DATA','DATA'] }, + { name: 'd_user', wave: '7...03..330304...38.', data: ['DU0', 'DU1','DU2','DU3','DU4','DU5'] }, + { name: 'd_error', wave: '0............1...0..', data: ['ACK', 'ACK','ACK','ACK','ERR','ACK'] }, + ], + head: { + text: 'TileLink-UL read transactions', + }, + foot: { + text: 'six read transactions with various req/ready delays, error on I4 response', + } +} +``` + +## Bus Primitives + +The bus primitives are defined in the following table and described in +detail below. + +| Element | Description | +| :---: | --- | +| `tlul_fifo_sync` | FIFO connecting one TL-UL host to one TL-UL device in a synchronous manner. Used to create elasticity in the bus, or as a sub-element within other elements. TL-UL protocol is maintained on both sides of the device. Parameters control many features of the FIFO (see detailed description that follows). | +| `tlul_fifo_async` | FIFO connecting one TL-UL host to one TL-UL device in an asynchronous manner. Used to create elasticity in the bus, or to cross clock domains, or as a sub-element within other elements. TL-UL protocol is maintained on both sides of the device. Parameters control many features of the FIFO (see detailed description that follows). | +| `tlul_socket_1n` | Demultiplexing element that connects 1 TL-UL host to N TL-UL devices. TL-UL protocol is maintained on the host side and with all devices. Parameter settings control many of the features of the socket (see detailed description that follows). | +| `tlul_socket_m1` | Multiplexing element that connects M TL-UL hosts to 1 TL-UL device. TL-UL protocol is maintained with all hosts and on the device side. Parameter settings control many of the features of the socket (see detailed description that follows). | +| `tlul_xbar` | Crossbar that connects M TL-UL hosts with N TL-UL devices. The connectivity matrix may be sparse, and not all nodes are required to be the same clock or reset domain. TL-UL protocol is maintained with all hosts and with all devices. Parameters and configuration settings control many of the features of the switch. This is not specified at this time, and will be done at a later date based upon project goals. | +| `tlul_adapter_sram` | Adapter that connects a TL-UL host to an sram type interface. | + +#### A Note on Directions + +In each of these devices, ports are named with respect to their usage, +not their direction. For instance, a `1:N` socket connects one host to +N devices. Thus the TL-UL port coming in is called the "host bus", +and the N device ports are called "device bus" 0 through N-1. Within +the Verilog module, the "host bus" is actually a device in the sense +that it receives requests and returns responses. This terminology can be +confusing within the bus element itself but should maintain consistency +in naming at the higher levels. + +### `tlul_fifo_sync` + +The TL-UL FIFO is a `1:1` bus element that provides elasticity (the +ability for transactions to stall on one side without affecting the other +side) on the bus. It is also used as a sub-element in other elements, like +sockets. Parameterization of the module is described in the table below. + +| name | description | +| :---: | --- | +| `ReqPass` | If 1, allow requests to pass through the FIFO with no clock delay if the request FIFO is empty (this may have timing implications). If false, at least one clock cycle of latency is created. Default is 1. | +| `RspPass` | If 1, allow responses to pass through the FIFO with no clock delay if the response FIFO is empty (this may have timing implications). If false, at least one clock cycle of latency is created. Default is 1. | +| `ReqDepth[4]` | Depth of request FIFO. Depth of zero is allowed only if `ReqPass` is 1. The maximum value for `ReqDepth` is 15. Default is 2. | +| `RspDepth[4]` | Depth of response FIFO. Depth of zero is allowed only if `RspPass` is 1. The maximum value for `RspDepth` is 15. Default is 2. | +| `SpareReqW` | The FIFO has spare bits in the request direction for auxiliary use by other bus elements. This parameter defines the size, default 1, must be >= 1 to avoid compilation errors. If the bit is not needed, the spare input should be tied to zero, and the spare output ignored. | +| `SpareRspW` | The FIFO has spare bits in the response direction for auxiliary use by other bus elements. This parameter defines the size, default 1, must be >= 1 to avoid compilation error. If the bit is not needed, the spare input should be tied to zero, and the spare output ignored. | + +When `Pass` is 1 and its corresponding `Depth` is 0, the FIFO feeds through the signals completely. +This allows more flexible control at compile-time on the FIFO overhead / latency trade-off without needing to re-code the design. + +The IO of the module are given in this table. See the struct above for +TL-UL typedef definitions. + +| direction | type / size | name | description | +| :---: | :---: | :---: | --- | +| `input` | | `clk_i` | clock | +| `input` | | `rst_ni` | active low reset | +| `input` | `tl_h2d_t` | `tl_h_i` | Incoming host request struct | +| `output` | `tl_d2h_t` | `tl_h_o` | Outgoing host response struct | +| `output` | `tl_h2d_t` | `tl_d_o` | Outgoing device request struct | +| `input` | `tl_d2h_t` | `tl_d_i` | Incoming device response struct | +| `input` | `[SpareReqW-1:0]` | `spare_req_i` | Spare request bits in| +| `output` | `[SpareReqW-1:0]` | `spare_req_o` | Spare request bits out | +| `input` | `[SpareRspW-1:0]` | `spare_rsp_i` | Spare response bits in | +| `output` | `[SpareRspW-1:0]` | `spare_rsp_o` | Spare response bits out | + +### `tlul_fifo_async` + +The TL-UL asynchronous FIFO is a `1:1` bus element that can be used to +cross clock domains. Parameterization of the module is described in the +table below. + +| name | description | +| :---: | --- | +| `ReqDepth[4]` | Depth of request FIFO. Depth of request FIFO. ReqDepth must be >= 2, and the maximum value is 15. | +| `RspDepth[4]` | Depth of response FIFO. RspDepth must be >= 2, and the maximum value is 15. | + +The IO of the module are given in this table. See the struct above for +TL-UL typedef definitions. + +| direction | type / size | name | description | +| :---: | :---: | :---: | --- | +| `input` | | `clk_h_i` | Host side clock | +| `input` | | `rst_h_ni` | Host side active low reset | +| `input` | | `clk_d_i` | Device side clock | +| `input` | | `rst_d_ni` | Device side active low reset | +| `input` | `tl_h2d_t` | `tl_h_i` | Incoming host request struct | +| `output` | `tl_d2h_t` | `tl_h_o` | Outgoing host response struct | +| `output` | `tl_h2d_t` | `tl_d_o` | Outgoing device request struct | +| `input` | `tl_d2h_t` | `tl_d_i` | Incoming device response struct | + +### `tlul_socket_1n` + +The TL-UL socket `1:N` is a bus element that connects 1 TL-UL host +to N TL-UL devices. It is a fundamental building block of the TL-UL +switch, and uses `tlul_fifo_sync` as its building block. It has a +several parameterization settings available, summarized here. Note +`tlul_socket_1n` is always synchronous. If asynchronous behavior is +desired, an `tlul_fifo_async` should be placed on the desired bus. + +| name | description | +| :---: | --- | +| `N` | Number of devices the socket communicates with, 2 <= N <= 15. | +| `HReqPass` | If 1, allow requests to pass through the host-side FIFO with no clock delay if the request FIFO is empty. If 0, at least one clock cycle of latency is created. Default is 1. | +| `HRspPass` | If 1, allow responses to pass through the host-side FIFO with no clock delay if the response FIFO is empty. If 0, at least one clock cycle of latency is created. Default is 1. | +| `HReqDepth[4]` | Depth of host-side request FIFO. Depth of zero is allowed if `ReqPass` is 1. A maximum value of 15 is allowed, default is 2. | +| `HRspDepth[4]` | Depth of host-side response FIFO. Depth of zero is allowed if `RspPass` is 1. A maximum value of 15 is allowed, default is 2. | +| `DReqPass[N]` | If 1, allow requests to pass through device i FIFO with no clock delay if the request FIFO is empty. If false, at least one clock cycle of latency is created. Default is 1. | +| `DRspPass[N]` | If 1, allow responses to pass through the device i FIFO with no clock delay if the response FIFO is empty. If 0, at least one clock cycle of latency is created. Default is 1. | +| `DReqDepth[N*4]` | Depth of device i request FIFO. Depth of zero is allowed if `ReqPass` is 1. A maximum value of 15 is allowed, default is 2. | +| `DRspDepth[N*4]` | Depth of device i response FIFO. Depth of zero is allowed if `RspPass` is 1. A maximum value of 15 is allowed, default is 2. | + +The diagram below shows the dataflow of the `tlul_socket_1n` and how +the `tlul_fifo_sync` modules are allocated. + +![tlul_socket_1n block diagram](./doc/tlul_socket_1n.svg) + +In this diagram, the full socket (`1:4` in this case) is shown, with +its single host port and four device ports. Also shown is the critical +device select input, which controls the transaction steering. To allow +flexibility the address decoding is done outside the socket. The TL-UL +specification requires that the decode only use the address bits, but no +other constraints are placed on how the external decode logic converts +the address to the output device selection signal (`dev_sel`). The +timing of `dev_sel` is such that it must be valid whenever `a_valid` +is true in order to steer the associated request. + +The address decoder can trigger an error response: if the value of +`dev_sel` is not between 0 and N-1, then `tlul_socket_1n` will provide +the error response to the request. This is implemented with a separate +piece of logic inside the socket which handles all requests to `dev_sel >= +N` and replies with an error. + +The IO of the socket are given in this table. See the struct above for +TL-UL `typedef` definitions. + +| direction | type / size | name | description | +| :---: | :---: | :---: | --- | +| `input` | | `clk_i` | clock | +| `input` | | `rst_ni` | active low reest | +| `input` | `tl_h2d_t` | `tl_h_i` | incoming host request struct | +| `output` | `tl_d2h_t` | `tl_h_o` | outgoing host response struct | +| `output` | `tl_h2d_t` | `tl_d_o[N]` | Outgoing device request struct for device port *i* (where *i* is from 0 to *N-1*) | +| `input` | `tl_d2h_t` | `tl_d_i[N]` | Incoming device response struct for device port *i* (where *i* is from 0 to *N-1*) | +| `input` | `[log2(N+1)-1:0]` | `dev_sel` | Device select for the current transaction provided in `tl_h_i` bus. Legal values from 0 to N-1 steer to the corresponding device port. Any other value returns an automatic error response. | + +In the current implementation, outstanding requests are tracked so that +no new requests can go to a device port if there already are outstanding +requests to a different device. This ensures that all transactions are +returned in order. This feature is still in discussion. + +### `tlul_socket_m1` + +The TL-UL socket `M:1` is a bus element that connects `M` TL-UL +hosts to 1 TL-UL device. Along with a `tlul_socket_1n`, this could +be used to build the TL-UL fabric, and uses `tlul_fifo` as its +building block. `tlul_socket_m1` has several parameterization settings +available. The `tlul_socket_m1` is synchronous, so a `tlul_fifo_async` +must be instantiated on any ports that run asynchronously. + +| name | description | +| :---: | --- | +| `M` | Number of hosts the socket communicates with, 2 <= M <= 15. | +| `HReqPass[M]` | `M` bit array to allow requests to pass through the host i FIFO with no clock delay if the request FIFO is empty. If `1'b0`, at least one clock cycle of latency is created. Default is `1'b1`. | +| `HRspPass[M]` | `M` bit array. If `bit[i]=1`, allow responses to pass through the host *i* FIFO with no clock delay if the response FIFO is empty. If false, at least one clock cycle of latency is created. Default is 1. | +| `HReqDepth[4*M]` | `Mx4` bit array. `bit[i*4+:4]` is depth of host *i* request FIFO. Depth of zero is allowed if `ReqPass` is true. A maximum value of 15 is allowed, default is 2. | +| `HRspDepth[4*M]` | `Mx4` bit array. `bit[i*4+:4]` is depth of host *i* response FIFO. Depth of zero is allowed if RspPass is true. A maximum value of 15 is allowed, default is 2. | +| `DReqPass` | If 1, allow requests to pass through device FIFO with no clock delay if the request FIFO is empty. If false, at least one clock cycle of latency is created. Default is 1. | +| `DRspPass` | If 1, allow responses to pass through the device FIFO with no clock delay if the response FIFO is empty. If false, at least one clock cycle of latency is created. Default is 1. | +| `DReqDepth[4]` | Depth of device i request FIFO. Depth of zero is allowed if `ReqPass` is true. A maximum value of 15 is allowed, default is 2. | +| `DRspDepth[4]` | Depth of device i response FIFO. Depth of zero is allowed if `RspPass` is true. A maximum value of 15 is allowed, default is 2. | + +The diagram below shows the dataflow of `tlul_socket_m1` for `4:1` +case and how the `tlul_fifo_sync` modules are allocated. + +![tlul_socket_m1 block diagram](./doc/tlul_socket_m1.svg) + +Requests coming from each host ports are arbitrated in the socket based +on round-robin scheme. `tlul_socket_m1`, unlike the `1:N` socket, doesn't +require the `dev_sel` input. As the request is forwarded, the request ID +(`a_source`) is modified as described in the ID Growth section. The ID +returned with a response (`d_source`) can thus be directly used to steer +the response to the appropriate host. + +The IO of `M:1` socket are given in this table. See the struct above for +TL `typedef` definitions. + +| direction | type / size | name | description | +| :---: | :---: | :---: | --- | +| `input` | | `clk_i` | clock | +| `input` | | `rst_ni` | active low reest | +| `input` | `tl_h2d_t` | `tl_h_i[M]` | unpacked array of incoming host request structs | +| `output` | `tl_d2h_t` | `tl_h_o[M]` | unpacked array of outgoing host response structs | +| `output` | `tl_h2d_t` | `tl_d_o` | outgoing device request struct | +| `input` | `tl_d2h_t` | `tl_d_i` | incoming device response struct | + +### `tlul_xbar` + +For details of the `tlul_xbar`, please refer to the [tlgen reference manual](../../../util/tlgen/README.md). +In general, tlgen stitches together various components described in the previous sections to create a full blown fabric switch. +Specifically, it implements the address to `dev_sel` steering logic and ensures the right connections are made from host to device. + + +### `tlul_adapter_sram` + +The TL-UL sram adapter is a bus element that connects a TL-UL interface to a memory like interface. +The memory interface is defined as follows: + +| name | direction | description | +| :---: | :---: | :---: | +| req | `output` | Memory interface transaction request | +| gnt | `input` | Memory interface transaction grant | +| we | `output` | Transaction write enable | +| addr | `output` | Transaction address | +| wdata | `output` | Transaction write data | +| wmask | `output` | Transaction write mask | +| rvalid | `input` | Transaction read valid from downstream | +| rdata | `input` | Transaction read data from downstream | +| rerror | `input` | Transaction read error from downstream | + +The diagram below is a block diagram that shows the construction of the adapter. +![tlul_adapter_sram_block diagram](./doc/tlul_adapter_sram.svg) + +All incoming transactions are checked for protocol errors and integrity. +The transactions are then forwarded to the `tlul_sram_byte` module, which determines whether the incoming transaction is a write, and whether the write transaction must be transformed to a read-modified-write. + +The transformation is done when integrity is enabled on the downstream storage and the incoming transaction is a legal partial write. +During this scenario, in order to correctly compute the storage integrity, the adapter must first read back whatever is present in memory so that the full integrity can be computed. +If an error is present during the protocol and integrity checks, or if the transaction is not a partial write (read or full write), then the transaction is passed through directly to the TL-UL-sram conversion. +If the transaction is a legal partial write, the `tlul_sram_byte` instead transforms the transaction into two: a full read followed by a full write for a read-modified-write of the intended address. + +Once past the `tlul_sram_byte`, a transaction accepted by downstream consumers has some of its attributes (type of operation, presence of error, size, source) stored in the `request fifo`. +This is needed to correctly construct the TL-UL d-channel response when the transaction is complete. + +The internally computed "read mask" is also stored in the `sramreqfifo` for read transactions. +This is needed to correctly mask off uninteresting bytes during a partial read. + +Any returning read data from downstream is stored inside the `rspfifo`. +This is needed in case the upstream TL-UL host back pressures the d-channel. + +#### Life of a Write Transaction +When a write transaction is received, the above steps are followed; however, nothing is stored in the `sramreqfifo`. +When downstream completes the write transaction, the stored `reqfifo` entry is used to construct the TL-UL response. +When the response is accepted by an upstream TL-UL host, the `reqfifo` entry popped. + +#### Life of a Read Transaction +When a read transaction is received, both the `reqfifo` and the `sramreqfifo` store a new entry. +The former stores transaction attributes, while the latter stores the read mask and read offset (in case the downstream read is larger than TL-UL bus width). +When downstream completes the read transaction through `rvalid_i`, the relevant data, as determined by the stored read mask and offset in `sramreqfifo`, is stored in the `rspfifo`. +The act of storing into the `rspfifo` also pops `sramreqfifo` entry. + +The `reqfifo` entry is used to construct the TL-UL response. +When the response is accepted by an upstream TL-UL host, the `reqfifo` and `rspfifo` entries are both popped. diff --git a/src/tlul/adapter_host.core b/src/tlul/adapter_host.core new file mode 100644 index 0000000..d08ee13 --- /dev/null +++ b/src/tlul/adapter_host.core @@ -0,0 +1,64 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:tlul:adapter_host:0.1" +description: "Req/Grant/RValid to TL-UL adapter (host)" + +filesets: + files_rtl: + depend: + - lowrisc:prim:all + - lowrisc:tlul:common + - lowrisc:tlul:trans_intg + - lowrisc:constants:top_pkg + files: + - rtl/tlul_adapter_host.sv + file_type: systemVerilogSource + + files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common + files: + - lint/tlul_adapter_host.vlt + file_type: vlt + + files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common + files: + - lint/tlul_adapter_host.waiver + file_type: waiver + + files_veriblelint_waiver: + depend: + # common waivers + - lowrisc:lint:common + +parameters: + SYNTHESIS: + datatype: bool + paramtype: vlogdefine + + +targets: + default: &default_target + filesets: + - tool_verilator ? (files_verilator_waiver) + - tool_ascentlint ? (files_ascentlint_waiver) + - tool_veriblelint ? (files_veriblelint_waiver) + - files_rtl + toplevel: tlul_adapter_host + + lint: + <<: *default_target + default_tool: verilator + parameters: + - SYNTHESIS=true + tools: + verilator: + mode: lint-only + verilator_options: + - "-Wall" diff --git a/src/tlul/adapter_reg.core b/src/tlul/adapter_reg.core new file mode 100644 index 0000000..aab7657 --- /dev/null +++ b/src/tlul/adapter_reg.core @@ -0,0 +1,64 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:tlul:adapter_reg:0.1" +description: "TL-UL to Register interface adapter" + +filesets: + files_rtl: + depend: + - lowrisc:prim:assert + - lowrisc:prim:secded + - lowrisc:tlul:common + - lowrisc:tlul:trans_intg + files: + - rtl/tlul_adapter_reg.sv + file_type: systemVerilogSource + + files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common + files: + - lint/tlul_adapter_reg.vlt + file_type: vlt + + files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common + files: + - lint/tlul_adapter_reg.waiver + file_type: waiver + + files_veriblelint_waiver: + depend: + # common waivers + - lowrisc:lint:common + +parameters: + SYNTHESIS: + datatype: bool + paramtype: vlogdefine + + +targets: + default: &default_target + filesets: + - tool_verilator ? (files_verilator_waiver) + - tool_ascentlint ? (files_ascentlint_waiver) + - tool_veriblelint ? (files_veriblelint_waiver) + - files_rtl + toplevel: tlul_adapter_reg + + lint: + <<: *default_target + default_tool: verilator + parameters: + - SYNTHESIS=true + tools: + verilator: + mode: lint-only + verilator_options: + - "-Wall" diff --git a/src/tlul/adapter_sram.core b/src/tlul/adapter_sram.core new file mode 100644 index 0000000..7107a00 --- /dev/null +++ b/src/tlul/adapter_sram.core @@ -0,0 +1,64 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:tlul:adapter_sram:0.1" +description: "TL-UL to SRAM adapter (device)" + +filesets: + files_rtl: + depend: + - lowrisc:prim:util + - lowrisc:prim:assert + - lowrisc:tlul:common + files: + - rtl/tlul_sram_byte.sv + - rtl/tlul_adapter_sram.sv + file_type: systemVerilogSource + + files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common + files: + - lint/tlul_adapter_sram.vlt + file_type: vlt + + files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common + files: + - lint/tlul_adapter_sram.waiver + file_type: waiver + + files_veriblelint_waiver: + depend: + # common waivers + - lowrisc:lint:common + +parameters: + SYNTHESIS: + datatype: bool + paramtype: vlogdefine + + +targets: + default: &default_target + filesets: + - tool_verilator ? (files_verilator_waiver) + - tool_ascentlint ? (files_ascentlint_waiver) + - tool_veriblelint ? (files_veriblelint_waiver) + - files_rtl + toplevel: tlul_adapter_sram + + lint: + <<: *default_target + default_tool: verilator + parameters: + - SYNTHESIS=true + tools: + verilator: + mode: lint-only + verilator_options: + - "-Wall" diff --git a/src/tlul/common.core b/src/tlul/common.core new file mode 100644 index 0000000..ebf1873 --- /dev/null +++ b/src/tlul/common.core @@ -0,0 +1,51 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:tlul:common:0.1" +description: "TL-UL common building blocks" + +filesets: + files_rtl: + depend: + - lowrisc:dv:pins_if + - lowrisc:prim:assert + - lowrisc:prim:fifo + - lowrisc:tlul:headers + - lowrisc:tlul:trans_intg + files: + - rtl/tlul_fifo_sync.sv + - rtl/tlul_fifo_async.sv + - rtl/tlul_assert.sv + - rtl/tlul_err.sv + - rtl/tlul_assert_multiple.sv + file_type: systemVerilogSource + + files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common + files: + - lint/tlul_common.vlt + file_type: vlt + + files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common + files: + - lint/tlul_common.waiver + file_type: waiver + + files_veriblelint_waiver: + depend: + # common waivers + - lowrisc:lint:common + +targets: + default: + filesets: + - tool_verilator ? (files_verilator_waiver) + - tool_ascentlint ? (files_ascentlint_waiver) + - tool_veriblelint ? (files_veriblelint_waiver) + - files_rtl diff --git a/src/tlul/config/compile.yml b/src/tlul/config/compile.yml new file mode 100644 index 0000000..6c11424 --- /dev/null +++ b/src/tlul/config/compile.yml @@ -0,0 +1,48 @@ +--- +provides: [tlul_pkg] +schema_version: 2.4.0 +requires: + - edn_pkg + - caliptra_prim_pkg +targets: + rtl: + directories: [$COMPILE_ROOT/rtl] + files: + - $COMPILE_ROOT/rtl/tlul_pkg.sv + - $COMPILE_ROOT/rtl/tlul_assert_multiple.sv + - $COMPILE_ROOT/rtl/tlul_assert.sv + tb: + directories: [$COMPILE_ROOT/rtl] + files: + - $COMPILE_ROOT/rtl/tlul_pkg.sv + - $COMPILE_ROOT/rtl/tlul_assert_multiple.sv + - $COMPILE_ROOT/rtl/tlul_assert.sv +--- +provides: [tlul] +schema_version: 2.4.0 +requires: + - caliptra_prim + - tlul_pkg +targets: + rtl: + directories: [$COMPILE_ROOT/rtl] + files: + - $COMPILE_ROOT/rtl/sram2tlul.sv + - $COMPILE_ROOT/rtl/tlul_adapter_host.sv + - $COMPILE_ROOT/rtl/tlul_adapter_reg.sv + - $COMPILE_ROOT/rtl/tlul_adapter_sram.sv + - $COMPILE_ROOT/rtl/tlul_cmd_intg_chk.sv + - $COMPILE_ROOT/rtl/tlul_cmd_intg_gen.sv + - $COMPILE_ROOT/rtl/tlul_data_integ_dec.sv + - $COMPILE_ROOT/rtl/tlul_data_integ_enc.sv + - $COMPILE_ROOT/rtl/tlul_err_resp.sv + - $COMPILE_ROOT/rtl/tlul_err.sv + - $COMPILE_ROOT/rtl/tlul_fifo_async.sv + - $COMPILE_ROOT/rtl/tlul_fifo_sync.sv + - $COMPILE_ROOT/rtl/tlul_caliptra_ss_lc_gate.sv + - $COMPILE_ROOT/rtl/tlul_rsp_intg_chk.sv + - $COMPILE_ROOT/rtl/tlul_rsp_intg_gen.sv + - $COMPILE_ROOT/rtl/tlul_socket_1n.sv + - $COMPILE_ROOT/rtl/tlul_socket_m1.sv + - $COMPILE_ROOT/rtl/tlul_sram_byte.sv + diff --git a/src/tlul/data/BUILD b/src/tlul/data/BUILD new file mode 100644 index 0000000..dda56de --- /dev/null +++ b/src/tlul/data/BUILD @@ -0,0 +1,10 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +package(default_visibility = ["//visibility:public"]) + +filegroup( + name = "all_files", + srcs = glob(["**"]), +) diff --git a/src/tlul/data/tlul.prj.hjson b/src/tlul/data/tlul.prj.hjson new file mode 100644 index 0000000..2d63adb --- /dev/null +++ b/src/tlul/data/tlul.prj.hjson @@ -0,0 +1,31 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +{ + name: "tlul", + design_spec: "../doc", + dv_doc: "../doc/dv", + hw_checklist: "/hw/top_earlgrey/ip/xbar/doc/checklist", + revisions: [ + { + version: "0.5.0", + life_stage: "L2", + design_stage: "D3", + verification_stage: "V3", + commit_id: "0078a3228c0d311cd40996a730ed8453640a6944", + notes: "The target for this entry is the autogenerated xbar_main within top_earlgrey." + } + { + version: "1.0.0", + life_stage: "L1", + design_stage: "D2", + verification_stage: "V2", + commit_id: "dae702d55b89a18621607b34f7ab8161be3706eb", + notes: '''Only the XBAR instances (xbar_main and xbar_peri) and TLUL components + that go into them are certified to V2. For exceptions see + [DV_DOC](https://docs.opentitan.org/hw/ip/tlul/doc/dv/index.html#design-features) + ''' + } + ] +} diff --git a/src/tlul/data/tlul_testplan.hjson b/src/tlul/data/tlul_testplan.hjson new file mode 100644 index 0000000..fd53a30 --- /dev/null +++ b/src/tlul/data/tlul_testplan.hjson @@ -0,0 +1,81 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + // Use the name 'main' for this generic testplan. The actual testplan that imports + // this file can override the name if needed. + name: main + testpoints: [ + { + name: xbar_smoke + desc: '''Sequentially test each host to access any device''' + stage: V1 + tests: ["xbar_smoke"] + } + { + name: xbar_base_random_sequence + desc: '''Enable all hosts to randomly send transactions to any device''' + stage: V2 + tests: ["xbar_random"] + } + { + name: xbar_random_delay + desc: '''Control delays through plusargs to create tests for below types of delay + - Zero delay for sending a/d_valid and a/d_ready + - Large delay from 0 ~ 1000 cycles + - Small delay (0-10 cycles) for a_channel, large delay (0-1000 cycles) for d_channel''' + stage: V2 + tests: ["xbar_smoke_zero_delays", "xbar_smoke_large_delays", "xbar_smoke_slow_rsp", + "xbar_random_zero_delays", "xbar_random_large_delays", "xbar_random_slow_rsp"] + } + { + name: xbar_unmapped_address + desc: ''' + - Host randomly drives transactions with mapped and unmapped address + - Ensure DUT returns d_error=1 if address is unmapped and transaction isn't passed down + to any device''' + stage: V2 + tests: ["xbar_unmapped_addr", "xbar_error_and_unmapped_addr"] + } + { + name: xbar_error_cases + desc: ''' + - Drive any random value on size, mask, opcode in both channels + - Ensure everything just pass through host to device or device to host''' + stage: V2 + tests: ["xbar_error_random", "xbar_error_and_unmapped_addr"] + } + { + name: xbar_all_access_same_device + desc: ''' + - Randomly pick a device, make all hosts to access this device + - If the device isn't accessible for the host, let the host randomly access the other + devices''' + stage: V2 + tests: ["xbar_access_same_device", "xbar_access_same_device_slow_rsp"] + } + { + name: xbar_all_hosts_use_same_source_id + desc: '''Test all hosts use same ID at the same same''' + stage: V2 + tests: ["xbar_same_source"] + } + { + name: xbar_stress_all + desc: ''' + - Combine all sequences and run in parallel + - Add random reset between each iteration''' + stage: V2 + tests: ["xbar_stress_all", "xbar_stress_all_with_error"] + } + { + name: xbar_stress_with_reset + desc: ''' + - Inject reset while stress_all is running, after reset is completed, kill the + stress seq and then start a new stress seq + - Run a few iteration to ensure reset doesn't break the design''' + stage: V2 + tests: ["xbar_stress_all_with_rand_reset", "xbar_stress_all_with_reset_error"] + } + ] +} diff --git a/src/tlul/doc/TlulProtocolChecker.md b/src/tlul/doc/TlulProtocolChecker.md new file mode 100644 index 0000000..684d110 --- /dev/null +++ b/src/tlul/doc/TlulProtocolChecker.md @@ -0,0 +1,222 @@ +# TL-UL Protocol Checker + +# TileLink-UL Protocol Checker + + +## **Overview** + +This document details the protocol checker +[tlul_assert.sv](https://github.com/lowRISC/opentitan/blob/master/hw/ip/tlul/rtl/tlul_assert.sv) +for TL-UL (TileLink Uncached Lightweight), based on +[TileLink specification version 1.7.1](https://sifive.cdn.prismic.io/sifive%2F57f93ecf-2c42-46f7-9818-bcdd7d39400a_tilelink-spec-1.7.1.pdf). + +The next sections list the checks for each signal of TL-UL channels A and D. +More details: + +* The source fields (`a_source` and `d_source`) identify in-flight +transactions rather than physical agents. A single agent can use multiple +source IDs to track multiple outstanding transactions. See spec section 5.4 +"Source and Sink Identifiers" for more details. +* The source fields are `TL_AIW` bits wide (defined in +[tlul_pkg.sv](https://github.com/lowRISC/opentitan/blob/master/hw/ip/tlul/rtl/tlul_pkg.sv)). +Therefore, there can be up to 2TL_AIW outstanding +requests at the same time. To keep track of these outstanding requests, the +protocol checker stores pending requests in the array `pend_req` of depth +`TL_AIW`, and removes them once their corresponding response has been received. +* A request can be responded within the same cycle as the request message is +accepted. Therefore, in each clock cycle, the protocol checker first processes +requests and thereafter responses. +* The package +[tlul_pkg.sv](https://github.com/lowRISC/opentitan/blob/master/hw/ip/tlul/rtl/tlul_pkg.sv) +defines the structs for channels A and D. +* In below tables, "known" means that a signal should have a value other +than X. +* The protocol checker has a parameter `EndpointType` which can either be +`"Host"` or `"Device"`. The difference between the `"Host"` and `"Device"` +variant is that some of the properties are formulated as SV assumptions in the +former, whereas the same properties are formulated as SV assertions in the +latter (and vice versa). The behavior of these two checkers in DV simulations +is identical, but in formal verification, this distinction is needed (otherwise +some of the assertions would have to be disabled). + +## **Request Channel (Channel A)** + +Below table lists all channel A signals and their checks. +In `"Device"` mode some of these properties are assumptions (`_M` suffix) and in `"Host"` mode they are assertions (`_A` suffix). + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Signal + Checks (assertion name: description) +
a_opcode + legalAOpcode_[M/A]: Only the following 3 opcodes are legal: +Get, PutFullData, PutPartialData. See spec section 6.2. +
a_param + legalAParam_[M/A]: This field is reserved, it must be 0. See +spec section 6.2. +
a_size + sizeMatchesMask_[M/A]: a_size can be calculated from a_mask +as follows: 2a_size must equal $countones(a_mask). See spec section +4.6. +

+aKnown_A: Make sure it's not X when a_valid is high. +

a_source + pendingReqPerSrc_[M/A]: There should be no more +than one pending request per each source ID. See spec section 5.4. +

+aKnown_A: Make sure it's not X when a_valid is high. +

a_address + addrSizeAligned_[M/A]: a_address must be aligned to +a_size: a_address & ((1 << a_size) - 1) == 0. See spec section 4.6. +

+aKnown_AMake sure it's not X when a_valid is high. +

a_mask + contigMask_[M/A]: a_mask must be contiguous for Get +and PutFullData (but not for PutPartialData). See spec sections 4.6 and 6.2. +

+sizeMatchesMask_[M/A]: See a_size above. +

+aKnown_AMake sure it's not X when a_valid is high. +

a_data + aDataKnown_[M/A]: a_data should not be X for opcodes +PutFullData and PutPartialData (it can be X for Get). Bytes of a_data, whose +corresponding a_mask bits are 0, can be X. See spec section 4.6. +
a_user + aKnown_AMake sure it's not X when a_valid is high. +
a_valid + aKnown_A: Make sure it's not X (except during reset). +
a_ready + aReadyKnown_A: Make sure it's not X (except during +reset). +
+ +## **Response Channel (Channel D)** + +Below table lists all channel D signals and their checks. +In `"Device"` mode some of these properties are assertions (`_A` suffix) and in `"Host"` mode they are assumptions (`_M` suffix). + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Signal + Checks (assertion name: description) +
d_opcode + respOpcode_[A/M]: If the original request was Get, +then the corresponding response must be AccessAckData. Otherwise, the response +must be AccessAck. See spec section 6.2. +
d_param + legalDParam_[A/M]: This field is reserved, it must be 0. See +spec section 6.2. +
d_size + respSzEqReqSz_[A/M]: The response must have +the same size as the original request. See spec section 6.2. +
d_source + respMustHaveReq_[A/M]: For each response, there must have +been a corresponding request with the same source ID value. See spec section +5.4. +

+noOutstandingReqsAtEndOfSim_A: Make sure that there are no +outstanding requests at the end of the simulation. +

+dKnown_A: Make sure it's not X when d_valid is high. +

d_sink + dKnown_A: Make sure it's not X when d_valid is high. +
d_data + dDataKnown_[A/M]: d_data should not be X for AccessAckData. +Bytes of d_data, whose corresponding mask bits of the original request are 0, +can be X. See spec section 4.6. +
d_error + dKnown_AMake sure it's not X when d_valid is high. +
d_user + dKnown_AMake sure it's not X when d_valid is high. +
d_valid + dKnown_A: Make sure it's not X (except during reset). +
d_ready + dReadyKnown_AMake sure it's not X (except during +reset). +
diff --git a/src/tlul/doc/dv/README.md b/src/tlul/doc/dv/README.md new file mode 100644 index 0000000..610f165 --- /dev/null +++ b/src/tlul/doc/dv/README.md @@ -0,0 +1,124 @@ +# TLUL XBAR DV document + + +## Goals +* **DV** + * Verify all TLUL XBAR IP features by running dynamic simulations with a SV/UVM based testbench + * Develop and run all tests based on the [testplan](#testplan) below towards closing code and functional coverage on the IP and all of its sub-modules +* **FPV** + * Verify TileLink device protocol compliance with an SVA based testbench + +## Current status +* [Design & verification stage](../../../../README.md) + * [HW development stages](../../../../../doc/project_governance/development_stages.md) +* [Simulation results](https://reports.opentitan.org/hw/ip/keymgr/dv/latest/report.html) + +## Design features +For detailed information on TLUL design features, please see the [TLUL design specification](../../README.md). + +Only following modules are verified in this testbench. +* tlul_socket_1n, tlul_socket_m1 +* tlul_fifo_async, tlul_fifo_sync + +The other TLUL modules as follows are verified in the blocks that instantiate them. +* tlul_adapter_* +* tlul_*intg* / tlul_*integ* +* tlul_err* +* tlul_sram_byte, sram2tlul + +## Testbench architecture +XBAR testbench has been constructed based on the `hw/dv/sv/dv_lib` + +### Block diagram +![Block diagram](tb.svg) + +### Top level testbench +Top level testbench is located at `hw/ip/tlul/dv/tb/tb.sv`. It instantiates the XBAR DUT module `hw/top_earlgrey/ip/xbar/rtl/autogen/xbar_main.sv`. +In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into `uvm_config_db`: +* [Clock and reset interface](../../../../dv/sv/common_ifs/README.md) +* [TileLink host interface](../../../../dv/sv/tl_agent/README.md) + +### Common DV utility components +The following utilities provide generic helper tasks and functions to perform activities that are common across the project: +* [common_ifs](../../../../dv/sv/common_ifs/README.md) +* [dv_utils_pkg](../../../../dv/sv/dv_utils/README.md) + +### Global types & methods +All common types and methods defined at the package level can be found in +`xbar_param`. Some of them in use are: +```systemverilog +// 3 hosts can access a same device, reserve upper 2 bits. If all hosts send +// maximum outstanding request in this device, the device needs extra 2 bits +// for source ID to accommodate all the requests +parameter int VALID_HOST_ID_WIDTH = 6 +``` + +### TL agent +XBAR env instantiates [tl_agent](../../../../dv/sv/tl_agent/README.md) for each xbar host and device, +which provides the ability to drive and independently monitor random traffic via +TL host/device interface. +* For host, source ID MSB 2 bits are tied to 0 and maximum number of outstanding request is 64 +* For device, max number of outstanding request = 64 * number of its accessible hosts. And device also supports out of order response + +### Stimulus strategy +#### Test sequences +All test sequences reside in `hw/ip/tlul/dv/env/seq_lib`. +The `xbar_base_vseq` virtual sequence is extended from `dv_base_vseq` and serves as a starting point. +All test sequences are extended from `xbar_base_vseq`. +It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call. +Some of the most commonly used tasks / functions are as follows: +* seq_init: Create and configure host and device sequences, extended class can override this function to control host/device sequence +* run_all_device_seq_nonblocking: Create passive response sequence for each device +* run_all_host_seq_in_parallel: Create host sequences to run in parallel + +#### Functional coverage +To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. +The following covergroups have been developed to prove that the test intent has been adequately met: +* common covergroup from tl_agent: Cover each host/device reaches its maximum outstanding requests +* same_device_access_cg: Cover each device has been accessed by all its hosts at the same time +* same_source_access_cg: Cover all hosts use the same ID at the same time and all the IDs have been used at this sequence +* max_delay_cg: Cover zero delay, small delay and large delay have been used in every host and device +* outstanding_cg: Cover each host/device hit its maximum outstanding requests + +### Self-checking strategy +#### Scoreboard +The `xbar_scoreboard` is primarily used for end to end checking. +It extends from scoreboard_pkg::scoreboard, which supports multiple queues and in-order/out-of-order comparison. +Scoreboard checks one transaction twice: +* In a_channel, host initializes a transaction and scoreboard checks if this transaction is received by a right device +* In d_channel, device initializes a response and scoreboard checks this response is returned to the right host + +When device receives a transaction, we don't predict which host drives it. +XBAR DUT may not drive transaction received from host to device in order. +Due to this limitation, scoreboard is designed as following: +* For a_channel, each device has a transaction queue. Monitor transaction from host and store it in a device queue based on item address. + When device receives a transaction, check if there is a same item in its queue and the item is allowed to be appeared out of order. +* For d_channel, use same structure to check items from device to host. +* If the transaction is unmapped, it won't be sent to any device. Host will return an error response with `d_error = 1`. + Each host has a queue used only for unmapped items. It stores the unmapped item from a_channel, then compare it with the same source ID response received in d_channel. + +Following analysis fifos are created to retrieve the data monitored by corresponding interface agents: +* a_chan_host/device_name, d_chan_host/device_name: These fifos provide transaction items at the end of address channel and data channel respectively from host/device + +Following item queues are created to store items for check +* a_chan_device_name: store items from all hosts that are sent to this device +* d_chan_device_name: store items from this device that are returned to all hosts + +Another limitation of scoreboard is that we don't check the conversion of source ID from host to device. +We set the source of expected item to 0 before put it into scoreboard queue and hack the source of actual item to 0 before comparison + +#### Assertions +* TLUL assertions: The `tb/xbar_bind.sv` binds the `tlul_assert` [assertions](../TlulProtocolChecker.md) to the IP to ensure TileLink interface protocol compliance. +* Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset. + +## Building and running tests +We are using our in-house developed [regression tool](../../../../../util/dvsim/README.md) for building and running our tests and regressions. +Please take a look at the link for detailed information on the usage, capabilities, features and known issues. +Here's how to run a smoke test: +```console +$ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/$CHIP/ip/$XBAR_IP/dv/autogen/${XBAR_IP}_sim_cfg.hjson -i xbar_smoke +``` +In this run command, $XBAR_IP can be xbar_main, xbar_peri, etc. $CHIP can be top_earlgrey, etc. + +## Testplan +[Testplan](../../data/tlul_testplan.hjson) diff --git a/src/tlul/doc/dv/tb.svg b/src/tlul/doc/dv/tb.svg new file mode 100644 index 0000000..373d440 --- /dev/null +++ b/src/tlul/doc/dv/tb.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/src/tlul/doc/tlul_adapter_sram.svg b/src/tlul/doc/tlul_adapter_sram.svg new file mode 100644 index 0000000..da115d0 --- /dev/null +++ b/src/tlul/doc/tlul_adapter_sram.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/src/tlul/doc/tlul_socket_1n.svg b/src/tlul/doc/tlul_socket_1n.svg new file mode 100644 index 0000000..c27eae7 --- /dev/null +++ b/src/tlul/doc/tlul_socket_1n.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/src/tlul/doc/tlul_socket_m1.svg b/src/tlul/doc/tlul_socket_m1.svg new file mode 100644 index 0000000..679c106 --- /dev/null +++ b/src/tlul/doc/tlul_socket_m1.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/src/tlul/generic_dv/README b/src/tlul/generic_dv/README new file mode 100644 index 0000000..7f4f4f1 --- /dev/null +++ b/src/tlul/generic_dv/README @@ -0,0 +1,7 @@ +# The location of running XBAR simulation +Don't run xbar simulation in the current directory: `hw/ip/tlul/generic_dv`. +Currently directory only contains the generic portion of the xbar TB, which is +used by all flavors of xbar. The simulation directory is along with actual xbar +design, for example: +* hw/top_earlgrey/ip/xbar_main/dv/autogen +* hw/top_earlgrey/ip/xbar_peri/dv/autogen diff --git a/src/tlul/generic_dv/env/seq_lib/xbar_access_same_device_vseq.sv b/src/tlul/generic_dv/env/seq_lib/xbar_access_same_device_vseq.sv new file mode 100644 index 0000000..f8671f3 --- /dev/null +++ b/src/tlul/generic_dv/env/seq_lib/xbar_access_same_device_vseq.sv @@ -0,0 +1,39 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// test all hosts to access same device +// randomly pick one device, if host can acess this device, change it to only access this device +// repeat above for a few times +class xbar_access_same_device_vseq extends xbar_random_vseq; + + `uvm_object_utils(xbar_access_same_device_vseq) + `uvm_object_new + + // more req to hit max outstanding number + function void pre_randomize(); + min_req_cnt = 200; + max_req_cnt = 300; + super.pre_randomize(); + endfunction + + virtual function void update_host_seq(); + int device_id = $urandom_range(0, xbar_devices.size - 1); + + if (cfg.en_cov) cov.same_device_access_cg.sample(device_id); + `uvm_info(`gfn, $sformatf("Picked device (%0s) for all hosts to access", + xbar_devices[device_id].device_name), UVM_HIGH) + + // change host to only access the picked device + foreach (host_seq[i]) begin + // if the selected device_id is a valid ID for this host, only store this id to use + if (device_id inside {host_seq[i].valid_device_id}) begin + host_seq[i].valid_device_id.delete(); + host_seq[i].valid_device_id.push_back(device_id); + `uvm_info(`gfn, $sformatf("Host (%0s) only accesses device (%0s)", + host_seq[i].get_name(), xbar_devices[device_id].device_name), UVM_HIGH) + end + end + endfunction + +endclass diff --git a/src/tlul/generic_dv/env/seq_lib/xbar_base_vseq.sv b/src/tlul/generic_dv/env/seq_lib/xbar_base_vseq.sv new file mode 100644 index 0000000..4fbd9e2 --- /dev/null +++ b/src/tlul/generic_dv/env/seq_lib/xbar_base_vseq.sv @@ -0,0 +1,121 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// --------------------------------------------- +// Xbar environment virtual sequence +// --------------------------------------------- +class xbar_base_vseq extends dv_base_vseq #(.CFG_T (xbar_env_cfg), + .COV_T (xbar_env_cov), + .VIRTUAL_SEQUENCER_T (xbar_virtual_sequencer)); + + // TL host and device sub-sequences + rand xbar_tl_host_seq host_seq[]; + rand tl_device_seq device_seq[]; + rand bit en_req_abort; + rand bit en_rsp_abort; + + uint min_req_cnt = 100; + uint max_req_cnt = 200; + + // if seq crosses with the other seq, only need to enable device rsp thread + bit do_device_rsp = 1; + + constraint req_cnt_c { + foreach (host_seq[i]) { + host_seq[i].req_cnt inside {[min_req_cnt : max_req_cnt]}; + } + } + + constraint en_req_abort_c { + en_req_abort dist { + 1 :/ 25, + 0 :/ 75 + }; + } + + constraint en_rsp_abort_c { + en_rsp_abort dist { + 1 :/ 25, + 0 :/ 75 + }; + } + `uvm_object_utils(xbar_base_vseq) + `uvm_object_new + + // create and configure host/device seq before randomize as host_seq/device_seq are rand + function void pre_randomize(); + host_seq = new[xbar_hosts.size()]; + device_seq = new[xbar_devices.size()]; + foreach (host_seq[i]) begin + host_seq[i] = xbar_tl_host_seq::type_id::create( + $sformatf("%0s_seq", xbar_hosts[i].host_name)); + // Default only send request to valid devices that is accessible by the host + foreach (xbar_devices[j]) begin + if (is_valid_path(xbar_hosts[i].host_name, xbar_devices[j].device_name)) begin + `uvm_info(get_full_name, $sformatf("Add device %0s to seq %0s", + xbar_devices[i].device_name, host_seq[i].get_name()), UVM_HIGH) + host_seq[i].valid_device_id.push_back(j); + end + end + end + foreach (device_seq[i]) begin + device_seq[i] = tl_device_seq#()::type_id::create( + $sformatf("%0s_seq", xbar_devices[i].device_name)); + device_seq[i].d_error_pct = $urandom_range(0, 70); + end + endfunction : pre_randomize + + function void post_randomize(); + foreach (host_seq[i]) begin + if (en_req_abort) host_seq[i].req_abort_pct = $urandom_range(0, 100); + end + foreach (device_seq[i]) begin + if (en_rsp_abort) device_seq[i].rsp_abort_pct = $urandom_range(0, 100); + end + endfunction : post_randomize + + virtual task run_all_device_seq_nonblocking(bit out_of_order_rsp = 1); + if (do_device_rsp) begin + foreach (device_seq[i]) begin + fork + automatic int device_id = i; + device_seq[device_id].out_of_order_rsp = out_of_order_rsp; + device_seq[device_id].start(p_sequencer.device_seqr[device_id]); + join_none + end + end + endtask + + virtual task run_host_seq(uint host_id); + host_seq[host_id].start(p_sequencer.host_seqr[host_id]); + `uvm_info(get_full_name(), $sformatf("%0s finished sending %0d requests", + host_seq[host_id].get_full_name(), + host_seq[host_id].req_cnt), UVM_LOW) + endtask + + // run host seq in parallel and use num_enabled_hosts to decide how many hosts to run + virtual task run_all_host_seq_in_parallel(); + int completed_seq_cnt; + int host_cnt; + int host_id_q[$]; + + // make host_id_q store all host_id in random order + foreach (host_seq[i]) host_id_q.push_back(i); + host_id_q.shuffle(); + + foreach (host_id_q[i]) begin + fork + automatic int host_id = host_id_q[i]; + begin + run_host_seq(host_id); + completed_seq_cnt += 1; + end + join_none + host_cnt++; + if (host_cnt >= cfg.num_enabled_hosts) break; + end + wait(completed_seq_cnt == cfg.num_enabled_hosts); + endtask + +endclass diff --git a/src/tlul/generic_dv/env/seq_lib/xbar_random_vseq.sv b/src/tlul/generic_dv/env/seq_lib/xbar_random_vseq.sv new file mode 100644 index 0000000..a837e1b --- /dev/null +++ b/src/tlul/generic_dv/env/seq_lib/xbar_random_vseq.sv @@ -0,0 +1,34 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// base random seq, most of xbar vseq will extend from this +class xbar_random_vseq extends xbar_base_vseq; + + `uvm_object_utils(xbar_random_vseq) + `uvm_object_new + + // override it to control host seq in extended classes + virtual function void update_host_seq(); + endfunction + + virtual task pre_start(); + super.pre_start(); + if (cfg.short_xbar_test) begin + num_trans_c.constraint_mode(0); + num_trans = $urandom_range(1, 3); + end + endtask + + virtual task body(); + run_all_device_seq_nonblocking(); + for (int i = 1; i <= num_trans; i++) begin + update_host_seq(); + run_all_host_seq_in_parallel(); + `uvm_info(`gfn, $sformatf("finished run %0d/%0d", i, num_trans), UVM_LOW) + // re-randomize for next loop + if (i <= num_trans) `DV_CHECK_RANDOMIZE_FATAL(this) + end + endtask + +endclass diff --git a/src/tlul/generic_dv/env/seq_lib/xbar_same_source_vseq.sv b/src/tlul/generic_dv/env/seq_lib/xbar_same_source_vseq.sv new file mode 100644 index 0000000..b4917c7 --- /dev/null +++ b/src/tlul/generic_dv/env/seq_lib/xbar_same_source_vseq.sv @@ -0,0 +1,37 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// test all hosts use same source id for each iteration +// reduce to 5-20 trans per iteration and increase interation number by x10 +class xbar_same_source_vseq extends xbar_random_vseq; + + `uvm_object_utils(xbar_same_source_vseq) + `uvm_object_new + + constraint num_trans_c { + num_trans inside {[10:200]}; + } + + // reduce to 5-20 trans per iteration + function void pre_randomize(); + min_req_cnt = 5; + max_req_cnt = 20; + super.pre_randomize(); + endfunction + + virtual function void update_host_seq(); + int source = $urandom_range(0, (1 << cfg.valid_a_source_width) - 1); + + // TODO: figure out a way to sample the cov below in the scb instead of here. + if (cfg.en_cov) cov.same_source_access_cg.sample(source); + `uvm_info(`gfn, $sformatf("Picked source (%0d) for all hosts", source), UVM_HIGH) + + // change host to only access the picked device + foreach (host_seq[i]) begin + host_seq[i].override_a_source_val = 1; + host_seq[i].overridden_a_source_val = source; + end + endfunction + +endclass diff --git a/src/tlul/generic_dv/env/seq_lib/xbar_seq_err_item.sv b/src/tlul/generic_dv/env/seq_lib/xbar_seq_err_item.sv new file mode 100644 index 0000000..5ede81d --- /dev/null +++ b/src/tlul/generic_dv/env/seq_lib/xbar_seq_err_item.sv @@ -0,0 +1,21 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// --------------------------------------------- +// TileLink sequence item with all protocol related constraint disabled +// --------------------------------------------- +class xbar_seq_err_item extends cip_tl_seq_item; + + `uvm_object_utils(xbar_seq_err_item) + `uvm_object_new + + function void pre_randomize(); + disable_a_chan_protocol_constraint(); + no_d_error_c.constraint_mode(0); + endfunction + + // Remove modification on a_user, so it's freely randomized + function void post_randomize(); + endfunction +endclass diff --git a/src/tlul/generic_dv/env/seq_lib/xbar_smoke_vseq.sv b/src/tlul/generic_dv/env/seq_lib/xbar_smoke_vseq.sv new file mode 100644 index 0000000..00ff87d --- /dev/null +++ b/src/tlul/generic_dv/env/seq_lib/xbar_smoke_vseq.sv @@ -0,0 +1,19 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Sequentially test each host to access any device +// device will respond in order +class xbar_smoke_vseq extends xbar_base_vseq; + + `uvm_object_utils(xbar_smoke_vseq) + `uvm_object_new + + virtual task body(); + run_all_device_seq_nonblocking(.out_of_order_rsp(0)); + foreach (host_seq[i]) begin + run_host_seq(i); + end + endtask + +endclass diff --git a/src/tlul/generic_dv/env/seq_lib/xbar_stress_all_vseq.sv b/src/tlul/generic_dv/env/seq_lib/xbar_stress_all_vseq.sv new file mode 100644 index 0000000..a55e7d0 --- /dev/null +++ b/src/tlul/generic_dv/env/seq_lib/xbar_stress_all_vseq.sv @@ -0,0 +1,64 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// combine all xbar seqs in one seq to run in parallel for mutiply times +class xbar_stress_all_vseq extends xbar_base_vseq; + `uvm_object_utils(xbar_stress_all_vseq) + + // reduce num_trans + constraint num_trans_c { + num_trans inside {[1:5]}; + } + + `uvm_object_new + + task body(); + string seq_names[] = {"xbar_smoke_vseq", + "xbar_random_vseq", + "xbar_access_same_device_vseq", + "xbar_same_source_vseq", + "xbar_unmapped_addr_vseq"}; + run_all_device_seq_nonblocking(); + for (int i = 1; i <= num_trans; i++) fork + begin // isolation thread + foreach (seq_names[i]) begin + automatic int seq_idx = i; + fork + if ($urandom_range(0, 1)) begin + uvm_sequence seq; + xbar_base_vseq xbar_vseq; + uint dly_to_start_seq; + + seq = create_seq_by_name(seq_names[seq_idx]); + `downcast(xbar_vseq, seq) + + // dut_init (reset) is done in xbar_stress_all_vseq + xbar_vseq.do_dut_init = 0; + // rsp thread is created in xbar_stress_all_vseq at line 22 + xbar_vseq.do_device_rsp = 0; + + xbar_vseq.set_sequencer(p_sequencer); + `DV_CHECK_RANDOMIZE_FATAL(xbar_vseq) + `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(dly_to_start_seq, + dly_to_start_seq dist { + 0 :/ 1, + [1:100] :/ 1, + [101:1000] :/ 1 + };) + cfg.clk_rst_vif.wait_clks(dly_to_start_seq); + xbar_vseq.start(p_sequencer); + end + join_none + end + wait fork; + // if this seq is called as a sub-seq, and run with another seq that contains reset, + // when reset is issued in both seq at the same time, can't know where is the end of reset + // hence, if we want to kill unfinished seq after reset, we may not kill it at a right time + if (do_apply_reset && $urandom_range(0, 1)) dut_init(); + `uvm_info(`gfn, $sformatf("finished run %0d/%0d", i, num_trans), UVM_LOW) + end // isolation thread + join + endtask : body + +endclass diff --git a/src/tlul/generic_dv/env/seq_lib/xbar_stress_all_with_rand_reset_vseq.sv b/src/tlul/generic_dv/env/seq_lib/xbar_stress_all_with_rand_reset_vseq.sv new file mode 100644 index 0000000..054a140 --- /dev/null +++ b/src/tlul/generic_dv/env/seq_lib/xbar_stress_all_with_rand_reset_vseq.sv @@ -0,0 +1,65 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// one thread running the hmac_stress_all sequence +// another thread randomly insert reset +class xbar_stress_all_with_rand_reset_vseq extends xbar_base_vseq; + `uvm_object_utils(xbar_stress_all_with_rand_reset_vseq) + + rand uint delay; + + `uvm_object_new + + constraint delay_c { + delay dist { + 0 :/ 1, + [1 :100] :/ 1, + [101 :10_000] :/ 8, + [10_001 :1_000_000] :/ 1 + }; + } + + task body(); + for (int i = 1; i <= num_trans; i++) begin + bit reset_ongoing; + xbar_stress_all_vseq xbar_vseq; + fork + begin : seq_wo_reset + xbar_vseq = xbar_stress_all_vseq::type_id::create("xbar_stress_all_vseq"); + + xbar_vseq.do_apply_reset = 0; + xbar_vseq.set_sequencer(p_sequencer); + `DV_CHECK_RANDOMIZE_FATAL(xbar_vseq) + xbar_vseq.start(p_sequencer); + // once reset starts, need to wait until reset is done + wait (reset_ongoing == 0); + `uvm_info(`gfn, $sformatf("Finished run %0d/%0d w/o reset", i, num_trans), UVM_LOW) + end + + begin : reset + `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(delay, + delay dist { + 1 :/ 1, + [2 :100] :/ 1, + [101 :10_000] :/ 8, + [10_001 :1_000_000] :/ 1 + };) + cfg.clk_rst_vif.wait_clks(delay); + reset_ongoing = 1; + // reset needs to be longger than any clocks to allow TLUL driver flash out all items + cfg.clk_rst_vif.apply_reset(.reset_width_clks($urandom_range(100, 200))); + reset_ongoing = 0; + `uvm_info(`gfn, $sformatf("Reset is issued for run %0d/%0d", i, num_trans), UVM_LOW) + end + join_any + foreach (p_sequencer.host_seqr[i]) p_sequencer.host_seqr[i].stop_sequences(); + foreach (p_sequencer.device_seqr[i]) p_sequencer.device_seqr[i].stop_sequences(); + disable fork; + // delay to avoid race condition when sending item and checking no item after reset occur at + // the same time + #1ps; + end // end for loop + endtask : body + +endclass diff --git a/src/tlul/generic_dv/env/seq_lib/xbar_tl_host_seq.sv b/src/tlul/generic_dv/env/seq_lib/xbar_tl_host_seq.sv new file mode 100644 index 0000000..d98f405 --- /dev/null +++ b/src/tlul/generic_dv/env/seq_lib/xbar_tl_host_seq.sv @@ -0,0 +1,69 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// --------------------------------------------- +// TileLink agent sequence library +// --------------------------------------------- + +// Basic xbar TL host sequence +class xbar_tl_host_seq extends tl_host_seq; + + // if enabled, will allow to access both mapped and unmapped addr + bit en_unmapped_addr = 0; + + int valid_device_id[$]; + + // control the chance to use last address for current item + int use_last_item_addr_pct = 5; + bit [AddrWidth - 1 : 0] last_item_addr; + + `uvm_object_utils(xbar_tl_host_seq) + `uvm_object_new + + virtual function void randomize_req(tl_seq_item req, int idx); + uint device_id; + bit is_mapped_addr; + bit use_last_item_addr; + uint addr_range_id; + + // randomize device_id, is_mapped_addr, addr_range_id first + if (valid_device_id.size() > 0) begin + device_id = $urandom_range(0, valid_device_id.size() - 1); + device_id = valid_device_id[device_id]; + end else begin + device_id = $urandom_range(0, xbar_devices.size() - 1); + end + if (use_last_item_addr_pct > $urandom_range(99, 0)) use_last_item_addr = 1; + if (en_unmapped_addr) begin + is_mapped_addr = $urandom_range(0, 1); + end else begin + is_mapped_addr = 1; + addr_range_id = $urandom_range(0, xbar_devices[device_id].addr_ranges.size() - 1); + end + if (!(req.randomize() with { + a_valid_delay inside {[min_req_delay:max_req_delay]}; + if (use_last_item_addr) { + a_addr == last_item_addr; + } else if (is_mapped_addr) { + a_addr inside {[xbar_devices[device_id].addr_ranges[addr_range_id].start_addr : + xbar_devices[device_id].addr_ranges[addr_range_id].end_addr]}; + } else { + foreach (xbar_devices[device_id].addr_ranges[i]) { + !(a_addr inside {[xbar_devices[device_id].addr_ranges[i].start_addr : + xbar_devices[device_id].addr_ranges[i].end_addr]}); + } + }})) begin + `uvm_fatal(get_full_name(), "Cannot randomize req") + end + + last_item_addr = req.a_addr; + endfunction + + // prevent seq runs out of source ID + virtual task pre_start_item(tl_seq_item req); + super.pre_start_item(req); + wait(pending_req.size() < cfg.max_outstanding_req); + endtask + +endclass diff --git a/src/tlul/generic_dv/env/seq_lib/xbar_unmapped_addr_vseq.sv b/src/tlul/generic_dv/env/seq_lib/xbar_unmapped_addr_vseq.sv new file mode 100644 index 0000000..df8dfa8 --- /dev/null +++ b/src/tlul/generic_dv/env/seq_lib/xbar_unmapped_addr_vseq.sv @@ -0,0 +1,19 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// allow host to drive unmapped addr +// expect xbar will return d_error=1 and won't pass it to any device +class xbar_unmapped_addr_vseq extends xbar_random_vseq; + + `uvm_object_utils(xbar_unmapped_addr_vseq) + `uvm_object_new + + // allow host to driver unmapped addr + virtual function void update_host_seq(); + foreach (host_seq[i]) begin + host_seq[i].en_unmapped_addr = 1; + end + endfunction + +endclass diff --git a/src/tlul/generic_dv/env/seq_lib/xbar_vseq_list.sv b/src/tlul/generic_dv/env/seq_lib/xbar_vseq_list.sv new file mode 100644 index 0000000..782b8eb --- /dev/null +++ b/src/tlul/generic_dv/env/seq_lib/xbar_vseq_list.sv @@ -0,0 +1,14 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +`include "xbar_seq_err_item.sv" +`include "xbar_tl_host_seq.sv" +`include "xbar_base_vseq.sv" +`include "xbar_smoke_vseq.sv" +`include "xbar_random_vseq.sv" +`include "xbar_access_same_device_vseq.sv" +`include "xbar_same_source_vseq.sv" +`include "xbar_unmapped_addr_vseq.sv" +`include "xbar_stress_all_vseq.sv" +`include "xbar_stress_all_with_rand_reset_vseq.sv" diff --git a/src/tlul/generic_dv/env/xbar_env.core b/src/tlul/generic_dv/env/xbar_env.core new file mode 100644 index 0000000..84a8ac5 --- /dev/null +++ b/src/tlul/generic_dv/env/xbar_env.core @@ -0,0 +1,37 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:dv:xbar_env:0.1" +description: "xbar DV UVM environmnt" +filesets: + files_dv: + depend: + - lowrisc:dv:dv_lib + - lowrisc:dv:cip_lib + - lowrisc:dv:tl_agent + - lowrisc:dv:scoreboard + files: + - xbar_env_pkg.sv + - xbar_env_cfg.sv: {is_include_file: true} + - xbar_env_cov.sv: {is_include_file: true} + - xbar_virtual_sequencer.sv: {is_include_file: true} + - xbar_env.sv: {is_include_file: true} + - xbar_scoreboard.sv: {is_include_file: true} + - seq_lib/xbar_vseq_list.sv: {is_include_file: true} + - seq_lib/xbar_seq_err_item.sv: {is_include_file: true} + - seq_lib/xbar_tl_host_seq.sv: {is_include_file: true} + - seq_lib/xbar_base_vseq.sv: {is_include_file: true} + - seq_lib/xbar_smoke_vseq.sv: {is_include_file: true} + - seq_lib/xbar_random_vseq.sv: {is_include_file: true} + - seq_lib/xbar_access_same_device_vseq.sv: {is_include_file: true} + - seq_lib/xbar_same_source_vseq.sv: {is_include_file: true} + - seq_lib/xbar_unmapped_addr_vseq.sv: {is_include_file: true} + - seq_lib/xbar_stress_all_vseq.sv: {is_include_file: true} + - seq_lib/xbar_stress_all_with_rand_reset_vseq.sv: {is_include_file: true} + file_type: systemVerilogSource + +targets: + default: + filesets: + - files_dv diff --git a/src/tlul/generic_dv/env/xbar_env.sv b/src/tlul/generic_dv/env/xbar_env.sv new file mode 100644 index 0000000..68e7b90 --- /dev/null +++ b/src/tlul/generic_dv/env/xbar_env.sv @@ -0,0 +1,100 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// --------------------------------------------- +// Xbar environment class +// --------------------------------------------- +class xbar_env extends dv_base_env#(.CFG_T (xbar_env_cfg), + .VIRTUAL_SEQUENCER_T(xbar_virtual_sequencer), + .SCOREBOARD_T (xbar_scoreboard), + .COV_T (xbar_env_cov)); + + tl_agent host_agent[]; + tl_agent device_agent[]; + + `uvm_component_utils(xbar_env) + + function new (string name, uvm_component parent); + super.new(name, parent); + endfunction : new + + function void build_phase(uvm_phase phase); + super.build_phase(phase); + + // use cip_tl_seq_item to create tl_seq_item with correct integrity values and obtain integrity + // related functions + tl_seq_item::type_id::set_type_override(cip_tl_seq_item::get_type()); + + // Connect TileLink host and device agents + host_agent = new[cfg.num_hosts]; + foreach (host_agent[i]) begin + host_agent[i] = tl_agent::type_id::create( + $sformatf("%0s_agent", xbar_hosts[i].host_name), this); + uvm_config_db#(tl_agent_cfg)::set(this, + $sformatf("%0s_agent", xbar_hosts[i].host_name),"cfg", cfg.host_agent_cfg[i]); + cfg.host_agent_cfg[i].en_cov = cfg.en_cov; + end + device_agent = new[cfg.num_devices]; + foreach (device_agent[i]) begin + device_agent[i] = tl_agent::type_id::create( + $sformatf("%0s_agent", xbar_devices[i].device_name), this); + uvm_config_db#(tl_agent_cfg)::set(this, + $sformatf("%0s_agent", xbar_devices[i].device_name), "cfg", cfg.device_agent_cfg[i]); + cfg.device_agent_cfg[i].en_cov = cfg.en_cov; + end + + // this clock isn't connected to design but only used for TB, like measure timeout, drive long + // enough reset (bigger than 1 cycle of any DUT clock). Use fixed frequency 100 Mhz + cfg.clk_rst_vif.set_freq_mhz(100); + + // increase timer as device may respond very slowly in test - xbar_main_random_slow_rsp + scoreboard.timeout_cycle_limit = 100_000; + // create analysis_fifos and scoreboard_queue + foreach (xbar_hosts[i]) begin + scoreboard.add_item_port({"a_chan_", xbar_hosts[i].host_name}, scoreboard_pkg::kSrcPort); + scoreboard.add_item_port({"d_chan_", xbar_hosts[i].host_name}, scoreboard_pkg::kDstPort); + // this queue is used to store expected rsp in d channel for unmapped address + scoreboard.add_item_queue({"host_unmapped_addr_", xbar_hosts[i].host_name}, + scoreboard_pkg::kInOrderCheck); + end + foreach (xbar_devices[i]) begin + scoreboard.add_item_port({"a_chan_", xbar_devices[i].device_name}, scoreboard_pkg::kDstPort); + scoreboard.add_item_port({"d_chan_", xbar_devices[i].device_name}, scoreboard_pkg::kSrcPort); + + scoreboard.add_item_queue({"a_chan_", xbar_devices[i].device_name}, + scoreboard_pkg::kOutOfOrderCheck); + scoreboard.add_item_queue({"d_chan_", xbar_devices[i].device_name}, + scoreboard_pkg::kOutOfOrderCheck); + end + endfunction : build_phase + + function void connect_phase(uvm_phase phase); + super.connect_phase(phase); + // Connect virtual sequencer + if (cfg.is_active) begin + virtual_sequencer.host_seqr = new[cfg.num_hosts]; + virtual_sequencer.device_seqr = new[cfg.num_devices]; + foreach (host_agent[i]) begin + virtual_sequencer.host_seqr[i] = host_agent[i].sequencer; + end + foreach (device_agent[i]) begin + virtual_sequencer.device_seqr[i] = device_agent[i].sequencer; + end + end + // Connect scoreboard + foreach (host_agent[i]) begin + host_agent[i].monitor.a_chan_port.connect( + scoreboard.item_fifos[{"a_chan_", xbar_hosts[i].host_name}].analysis_export); + host_agent[i].monitor.d_chan_port.connect( + scoreboard.item_fifos[{"d_chan_", xbar_hosts[i].host_name}].analysis_export); + end + foreach (device_agent[i]) begin + device_agent[i].monitor.a_chan_port.connect( + scoreboard.item_fifos[{"a_chan_", xbar_devices[i].device_name}].analysis_export); + device_agent[i].monitor.d_chan_port.connect( + scoreboard.item_fifos[{"d_chan_", xbar_devices[i].device_name}].analysis_export); + end + endfunction : connect_phase + +endclass diff --git a/src/tlul/generic_dv/env/xbar_env_cfg.sv b/src/tlul/generic_dv/env/xbar_env_cfg.sv new file mode 100644 index 0000000..e645243 --- /dev/null +++ b/src/tlul/generic_dv/env/xbar_env_cfg.sv @@ -0,0 +1,101 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// --------------------------------------------- +// Xbar environment configuration class +// --------------------------------------------- +class xbar_env_cfg extends dv_base_env_cfg; + + rand tl_agent_cfg host_agent_cfg[]; + rand tl_agent_cfg device_agent_cfg[]; + uint num_hosts; + uint num_devices; + uint num_enabled_hosts; + // Actual number of a_source bits used by the design. + uint valid_a_source_width; + // enable to drop valid without ready + rand bit allow_host_drop_valid_wo_ready; + rand bit allow_device_drop_valid_wo_ready; + uint min_host_valid_len = 1; + uint max_host_valid_len = 50; + uint min_device_valid_len = 1; + uint max_device_valid_len = 50; + // delays for TL transaction + uint min_host_req_delay = 0; + uint max_host_req_delay = 20; + uint min_host_rsp_delay = 0; + uint max_host_rsp_delay = 20; + uint min_device_req_delay = 0; + uint max_device_req_delay = 20; + uint min_device_rsp_delay = 0; + uint max_device_rsp_delay = 20; + + // option to run short iteration + bit short_xbar_test = 0; + `uvm_object_utils_begin(xbar_env_cfg) + `uvm_field_array_object(host_agent_cfg, UVM_DEFAULT) + `uvm_field_array_object(device_agent_cfg, UVM_DEFAULT) + `uvm_field_int(num_hosts, UVM_DEFAULT) + `uvm_field_int(num_devices, UVM_DEFAULT) + `uvm_object_utils_end + + `uvm_object_new + + virtual function void initialize(bit [TL_AW-1:0] csr_base_addr = '1); + is_initialized = 1'b1; + ral_model_names = {}; // no csr in xbar + // Host TL agent cfg + num_hosts = xbar_hosts.size(); + num_enabled_hosts = xbar_hosts.size(); + valid_a_source_width = top_pkg::TL_AIW - $clog2(num_hosts); + host_agent_cfg = new[num_hosts]; + foreach (host_agent_cfg[i]) begin + host_agent_cfg[i] = tl_agent_cfg::type_id:: + create($sformatf("%0s_agent_cfg", xbar_hosts[i].host_name)); + host_agent_cfg[i].if_mode = dv_utils_pkg::Host; + host_agent_cfg[i].valid_a_source_width = valid_a_source_width; + host_agent_cfg[i].max_outstanding_req = 1 << valid_a_source_width; + host_agent_cfg[i].host_can_stall_rsp_when_a_valid_high = $urandom_range(0, 1); + end + // Device TL agent cfg + num_devices = xbar_devices.size(); + device_agent_cfg = new[num_devices]; + foreach (device_agent_cfg[i]) begin + device_agent_cfg[i] = tl_agent_cfg::type_id:: + create($sformatf("%0s_agent_cfg", xbar_devices[i].device_name)); + device_agent_cfg[i].if_mode = dv_utils_pkg::Device; + device_agent_cfg[i].allow_d_valid_drop_wo_d_ready = allow_device_drop_valid_wo_ready; + // the max_outstanding_req depends on how many hosts can access the device + // device.max_outstanding_req = sum(all its hosts max_outstanding_req) + device_agent_cfg[i].max_outstanding_req = 0; // clear default value + foreach (xbar_hosts[j]) begin + if (xbar_devices[i].device_name inside {xbar_hosts[j].valid_devices}) begin + device_agent_cfg[i].max_outstanding_req += host_agent_cfg[j].max_outstanding_req; + end + end // foreach (xbar_hosts[j]) + end // foreach (device_agent_cfg[i]) + endfunction + + // update TLUL agent cfg according to this env cfg. These values may be updated in test + virtual function void update_agent_cfg(); + foreach (host_agent_cfg[i]) begin + host_agent_cfg[i].allow_a_valid_drop_wo_a_ready = allow_host_drop_valid_wo_ready; + host_agent_cfg[i].a_valid_len_min = min_host_valid_len; + host_agent_cfg[i].a_valid_len_max = max_host_valid_len; + host_agent_cfg[i].a_valid_delay_min = min_host_req_delay; + host_agent_cfg[i].a_valid_delay_max = max_host_req_delay; + host_agent_cfg[i].d_ready_delay_min = min_host_rsp_delay; + host_agent_cfg[i].d_ready_delay_max = max_host_rsp_delay; + end + foreach (device_agent_cfg[i]) begin + device_agent_cfg[i].allow_d_valid_drop_wo_d_ready = allow_device_drop_valid_wo_ready; + device_agent_cfg[i].d_valid_len_min = min_device_valid_len; + device_agent_cfg[i].d_valid_len_max = max_device_valid_len; + device_agent_cfg[i].d_valid_delay_min = min_device_req_delay; + device_agent_cfg[i].d_valid_delay_max = max_device_req_delay; + device_agent_cfg[i].a_ready_delay_min = min_device_rsp_delay; + device_agent_cfg[i].a_ready_delay_max = max_device_rsp_delay; + end + endfunction +endclass diff --git a/src/tlul/generic_dv/env/xbar_env_cov.sv b/src/tlul/generic_dv/env/xbar_env_cov.sv new file mode 100644 index 0000000..c1d8390 --- /dev/null +++ b/src/tlul/generic_dv/env/xbar_env_cov.sv @@ -0,0 +1,79 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// sample at xbar_access_same_device_vseq +covergroup same_device_access_cg (uint num_dev) with function sample(uint dev_id); + cp_dev: coverpoint dev_id { + bins all_values[] = {[0:num_dev-1]}; + illegal_bins bin_others = default; + } +endgroup + +// sample at xbar_same_source_vseq +covergroup same_source_access_cg (uint num_source) with function sample(uint source); + cp_dev: coverpoint source { + bins all_values[] = {[0:num_source-1]}; + illegal_bins bin_others = default; + } +endgroup + +// wrap covergroup as a class to use it as an associative array +// sample at xbar_env_cov::build_phase +class max_delay_cg_obj; + + covergroup max_delay_cg (string name) with function sample(uint req_dly, uint rsp_dly); + option.per_instance = 1; + option.name = name; + cp_req_dly: coverpoint req_dly { + bins zero = {0}; + bins small_delay = {[1:20]}; + bins big_delay = {[100:1000]}; + } + cp_rsp_dly: coverpoint rsp_dly { + bins zero = {0}; + bins small_delay = {[1:20]}; + bins big_delay = {[100:1000]}; + } + endgroup + + function new(string name = ""); + max_delay_cg = new(name); + endfunction : new + + function void sample(uint req_dly, uint rsp_dly); + max_delay_cg.sample(req_dly, rsp_dly); + endfunction : sample +endclass : max_delay_cg_obj + +class xbar_env_cov extends dv_base_env_cov #(.CFG_T(xbar_env_cfg)); + same_device_access_cg same_device_access_cg; + same_source_access_cg same_source_access_cg; + // cover mapped/unmapped addr per host + bit_toggle_cg_wrap host_access_mapped_addr_cg[string]; + // cover max_delay per host/device + max_delay_cg_obj max_delay_cg_obj[string]; + `uvm_component_utils(xbar_env_cov) + + function new(string name, uvm_component parent); + super.new(name, parent); + endfunction : new + + virtual function void build_phase(uvm_phase phase); + super.build_phase(phase); + same_device_access_cg = new(cfg.num_devices); + same_source_access_cg = new(1 << cfg.valid_a_source_width); + foreach (xbar_hosts[i]) begin + host_access_mapped_addr_cg[xbar_hosts[i].host_name] = new(xbar_hosts[i].host_name); + max_delay_cg_obj[xbar_hosts[i].host_name] = new(xbar_hosts[i].host_name); + max_delay_cg_obj[xbar_hosts[i].host_name].sample(cfg.max_host_req_delay, + cfg.max_host_rsp_delay); + end + foreach (xbar_devices[i]) begin + max_delay_cg_obj[xbar_devices[i].device_name] = new(xbar_devices[i].device_name); + max_delay_cg_obj[xbar_devices[i].device_name].sample(cfg.max_device_req_delay, + cfg.max_device_rsp_delay); + end + endfunction + +endclass diff --git a/src/tlul/generic_dv/env/xbar_env_pkg.sv b/src/tlul/generic_dv/env/xbar_env_pkg.sv new file mode 100644 index 0000000..332ad82 --- /dev/null +++ b/src/tlul/generic_dv/env/xbar_env_pkg.sv @@ -0,0 +1,71 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// --------------------------------------------- +// Xbar environment package +// --------------------------------------------- +package xbar_env_pkg; + + import uvm_pkg::*; + import top_pkg::*; + import dv_utils_pkg::*; + import tl_agent_pkg::*; + import dv_lib_pkg::*; + import cip_base_pkg::*; + + typedef struct { + string device_name; + addr_range_t addr_ranges[$]; + } tl_device_t; + + typedef struct { + string host_name; + int host_id; + string valid_devices[$]; + } tl_host_t; + + // this file is auto-generated and the path to this file should be provided in xbar_*_sim.core + `include "xbar_env_pkg__params.sv" + + function automatic int get_host_id(string name); + foreach (xbar_hosts[i]) begin + if (xbar_hosts[i].host_name == name) return i; + end + return -1; + endfunction + + function automatic bit is_valid_path(string host_name, string device_name); + foreach (xbar_hosts[i]) begin + if (xbar_hosts[i].host_name == host_name) begin + foreach (xbar_hosts[i].valid_devices[j]) begin + if (xbar_hosts[i].valid_devices[j] == device_name) + return 1; + end + end + end + return 0; + endfunction + + function automatic bit is_device_valid_addr(string device_name, bit [top_pkg::TL_AW-1 : 0] addr); + foreach (xbar_devices[i]) begin + if (xbar_devices[i].device_name == device_name) begin + foreach (xbar_devices[i].addr_ranges[j]) begin + if (addr inside {[xbar_devices[i].addr_ranges[j].start_addr : + xbar_devices[i].addr_ranges[j].end_addr]}) begin + return 1; + end + end + end + end + return 0; + endfunction + + `include "xbar_env_cfg.sv" + `include "xbar_env_cov.sv" + `include "xbar_virtual_sequencer.sv" + `include "xbar_scoreboard.sv" + `include "xbar_env.sv" + `include "xbar_vseq_list.sv" + +endpackage diff --git a/src/tlul/generic_dv/env/xbar_scoreboard.sv b/src/tlul/generic_dv/env/xbar_scoreboard.sv new file mode 100644 index 0000000..c724756 --- /dev/null +++ b/src/tlul/generic_dv/env/xbar_scoreboard.sv @@ -0,0 +1,142 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// ------------------------------------------------------------------------ +// Xbar scoreboard class +// Extend from common multi-streams scoreboard +// Use the device address map to determine the queue ID +// ------------------------------------------------------------------------ +class xbar_scoreboard extends scoreboard_pkg::scoreboard #(.ITEM_T(tl_seq_item), + .CFG_T (xbar_env_cfg), + .COV_T (xbar_env_cov)); + int chan_prefix_len = 7; + + `uvm_component_utils(xbar_scoreboard) + `uvm_component_new + + // Customize the get_queue_name function + // port_name is {"a/d_chan_", host/devce name} + // tl_channel is "a/d_chan_" + // tl_port is host/devce name + virtual function string get_queue_name(tl_seq_item tr, string port_name); + string queue_name; + string tl_channel; + string tl_port; + tl_channel = port_name.substr(0, chan_prefix_len-1); + + tl_port = port_name.substr(chan_prefix_len, port_name.len() - 1); + if (!port_dir.exists(port_name)) begin + `uvm_fatal(`gfn, $sformatf("Unexpected port name %0s", tl_port)) + end begin + queue_name = get_queue_full_name(tr, tl_port, tl_channel); + end + `uvm_info(`gfn, $sformatf("Scoreboard queue name : %0s", queue_name), UVM_HIGH) + return queue_name; + endfunction + + // queue name is a_chan_``device_name`` or d_chan_``device_name``, device name is its suffix + // a_chan_/d_chan_ is prefix, which is from input queue_prefix + // if port is a device, return {queue_prefix, device_name} + // if port is a host, need to find the pair device_name, then return {queue_prefix, device_name} + // if unmapped addr, src is host a_chan, dst is host d_chan, so, + // use another prefix and return {"host_unmapped_addr_", host_name} + virtual function string get_queue_full_name(tl_seq_item tr, + string tl_port, + string queue_prefix); + foreach (xbar_devices[i]) begin + if (xbar_devices[i].device_name == tl_port) return {queue_prefix, tl_port}; + end + foreach (xbar_hosts[i]) begin + if (xbar_hosts[i].host_name == tl_port) begin + // Current port is a host port, get pair device port from the address + foreach (xbar_devices[j]) begin + if (xbar_devices[j].device_name inside {xbar_hosts[i].valid_devices} && + is_device_valid_addr(xbar_devices[j].device_name, tr.a_addr)) begin + return {queue_prefix, xbar_devices[j].device_name}; + end + end + // it's unmapped address + `uvm_info(`gfn, $sformatf("Unmapped addr: 0x%0h at %0s", tr.a_addr, tl_port), UVM_HIGH) + return {"host_unmapped_addr_", tl_port}; + end + end + `uvm_error(`gfn, $sformatf("Found unexpected item at[%0s]: %0s", + tl_port, tr.convert2string())) + endfunction + + // from host to device, source ID may be changed and set all source ID to 0 + function tl_seq_item modify_source_id(tl_seq_item tr); + tl_seq_item tr_modified; + `downcast(tr_modified, tr.clone()); + tr_modified.a_source = 0; + tr_modified.d_source = 0; + return tr_modified; + endfunction + + // check if the item is from host and it has mapped address + function bit is_access_to_mapped_addr(tl_seq_item tr, string port_name); + string tl_port; + tl_port = port_name.substr(chan_prefix_len, port_name.len() - 1); + foreach (xbar_hosts[i]) begin + if (xbar_hosts[i].host_name == tl_port) begin + foreach (xbar_devices[j]) begin + if (xbar_devices[j].device_name inside {xbar_hosts[i].valid_devices} && + is_device_valid_addr(xbar_devices[j].device_name, tr.a_addr)) begin + if (cfg.en_cov) cov.host_access_mapped_addr_cg[tl_port].sample(1); + return 1; // host port and mapped address + end + end + if (cfg.en_cov) cov.host_access_mapped_addr_cg[tl_port].sample(0); + return 0; // host port, but unmapped address + end + end + return 1; // not host port + endfunction + + virtual function void process_src_packet(input tl_seq_item tr, + input string port_name, + output tl_seq_item transformed_tr[$]); + tl_seq_item modified_tr; + if (is_access_to_mapped_addr(tr, port_name)) begin + modified_tr = modify_source_id(tr); + // d_data is 0, when it's a write + if (modified_tr.d_opcode == tlul_pkg::AccessAck) modified_tr.d_data = 0; + transformed_tr = {modified_tr}; + end else begin + cip_tl_seq_item rsp; + `downcast(rsp, tr.clone()); + rsp.d_source = tr.a_source; + rsp.d_size = tr.a_size; + rsp.d_error = 1; + if (rsp.a_opcode == tlul_pkg::Get) begin + tlul_pkg::tl_a_user_t a_user = tlul_pkg::tl_a_user_t'(rsp.a_user); + // if an error occurs, when it's an instrution, return all 0 + // since it's an illegal instruction, otherwise, return all 1s + rsp.d_data = a_user.instr_type == prim_mubi_pkg::MuBi4True ? 0 : '1; + end else begin + rsp.d_data = 0; + end + rsp.d_opcode = rsp.a_opcode == tlul_pkg::Get ? + tlul_pkg::AccessAckData : tlul_pkg::AccessAck; + rsp.d_user = rsp.compute_d_user; + + transformed_tr = {rsp}; + end + endfunction + + virtual function void process_dst_packet(input tl_seq_item tr, + input string port_name, + output tl_seq_item transformed_tr); + // if item is mapped, item will pass from h2d or d2h, source id may be changed and we don't + // predict it, modify all source_id to 0. + // if unmapped, item isn't passed down. source id shouldn't be changed. Check it + if (is_access_to_mapped_addr(tr, port_name)) transformed_tr = modify_source_id(tr); + else transformed_tr = tr; + endfunction + + function string get_tl_port(string port_name); + return port_name.substr(chan_prefix_len, port_name.len()-1); + endfunction + +endclass diff --git a/src/tlul/generic_dv/env/xbar_virtual_sequencer.sv b/src/tlul/generic_dv/env/xbar_virtual_sequencer.sv new file mode 100644 index 0000000..b9368bf --- /dev/null +++ b/src/tlul/generic_dv/env/xbar_virtual_sequencer.sv @@ -0,0 +1,16 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// --------------------------------------------- +// Xbar environment virtual sequencer +// --------------------------------------------- +class xbar_virtual_sequencer extends dv_base_virtual_sequencer #(.CFG_T(xbar_env_cfg), + .COV_T(xbar_env_cov)); + + tl_sequencer host_seqr[]; + tl_sequencer device_seqr[]; + + `uvm_component_utils(xbar_virtual_sequencer) + `uvm_component_new +endclass diff --git a/src/tlul/generic_dv/tb/tb.sv b/src/tlul/generic_dv/tb/tb.sv new file mode 100644 index 0000000..d8b6c6f --- /dev/null +++ b/src/tlul/generic_dv/tb/tb.sv @@ -0,0 +1,27 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +module tb; + + import uvm_pkg::*; + import dv_utils_pkg::*; + import xbar_test_pkg::*; + + wire clk, rst_n; + // reference clock for scb/seq and this clock isn't connected to any design clock + // TODO, reset is the combined all the resets. Re-visit this if partial reset is needed + clk_rst_if clk_rst_if(.clk(clk), .rst_n(rst_n)); + + // this file is auto-generated and the path to this file should be provided in xbar_*_sim.core + `include "tb__xbar_connect.sv" + + initial begin + // drive clk and rst_n from clk_if + clk_rst_if.set_active(); + uvm_config_db#(virtual clk_rst_if)::set(null, "*.env*", "clk_rst_vif", clk_rst_if); + $timeformat(-12, 0, " ps", 12); + run_test(); + end + +endmodule diff --git a/src/tlul/generic_dv/tb/xbar_macros.core b/src/tlul/generic_dv/tb/xbar_macros.core new file mode 100644 index 0000000..9291518 --- /dev/null +++ b/src/tlul/generic_dv/tb/xbar_macros.core @@ -0,0 +1,17 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +name: "lowrisc:dv:xbar_macros:0.1" +description: "XBAR Macros" +filesets: + files_dv: + files: + - xbar_macros.svh + file_type: systemVerilogSource + +targets: + default: + filesets: + - files_dv diff --git a/src/tlul/generic_dv/tb/xbar_macros.svh b/src/tlul/generic_dv/tb/xbar_macros.svh new file mode 100644 index 0000000..99cf695 --- /dev/null +++ b/src/tlul/generic_dv/tb/xbar_macros.svh @@ -0,0 +1,49 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// --------------------------------------------- +// TileLink interface connection macros +// --------------------------------------------- + +// reset is from tb.clk_rst_if, disable driving reset in this clk_rst_if +`define DRIVE_CLK(name, freq = $urandom_range(10, 100)) \ + wire ``name``; \ + clk_rst_if clk_rst_if_``name``(.clk(``name``), .rst_n(rst_n)); \ + initial begin \ + clk_rst_if_``name``.set_active(.drive_rst_n_val(0)); \ + clk_rst_if_``name``.set_freq_mhz(freq); \ + end + +`define DRIVE_TL_DEVICE_IF(tl_name, path = dut, clk, rst_n, i_sfx = i, o_sfx = o) \ + force ``tl_name``_tl_if.h2d = ``path``.tl_``tl_name``_``o_sfx``; \ + force ``path``.tl_``tl_name``_``i_sfx`` = ``tl_name``_tl_if.d2h; \ + uvm_config_db#(virtual tl_if)::set(null, $sformatf("*env.%0s_agent", `"tl_name`"), "vif", \ + ``tl_name``_tl_if); + +`define DRIVE_TL_HOST_IF(tl_name, path = dut, clk, rst_n, i_sfx = i, o_sfx = o) \ + force ``tl_name``_tl_if.d2h = ``path``.tl_``tl_name``_``o_sfx``; \ + force ``path``.tl_``tl_name``_``i_sfx`` = ``tl_name``_tl_if.h2d; \ + uvm_config_db#(virtual tl_if)::set(null, $sformatf("*env.%0s_agent", `"tl_name`"), "vif", \ + ``tl_name``_tl_if); + +`define CONNECT_TL_DEVICE_IF(tl_name, path = dut, clk, rst_n, i_sfx = i, o_sfx = o) \ + tl_if ``tl_name``_tl_if(clk, rst_n); \ + initial begin \ + `DRIVE_TL_DEVICE_IF(tl_name, path, clk, rst_n, i_sfx, o_sfx) \ + end + +`define CONNECT_TL_HOST_IF(tl_name, path = dut, clk, rst_n, i_sfx = i, o_sfx = o) \ + tl_if ``tl_name``_tl_if(clk, rst_n); \ + initial begin \ + `DRIVE_TL_HOST_IF(tl_name, path, clk, rst_n, i_sfx, o_sfx) \ + end + +`define CONNECT_TL_MON_IF(dut_h2d, dut_d2h, tl_name, clk, rst_n) \ + tl_if ``tl_name``_tl_if(clk, rst_n); \ + initial begin \ + force ``tl_name``_tl_if.h2d = dut_h2d; \ + force ``tl_name``_tl_if.d2h = dut_d2h; \ + uvm_config_db#(virtual tl_if)::set(null, $sformatf("*%0s*", `"tl_name`"), "vif", \ + ``tl_name``_tl_if); \ + end diff --git a/src/tlul/generic_dv/tb/xbar_tb.core b/src/tlul/generic_dv/tb/xbar_tb.core new file mode 100644 index 0000000..163f3d7 --- /dev/null +++ b/src/tlul/generic_dv/tb/xbar_tb.core @@ -0,0 +1,21 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +name: "lowrisc:dv:xbar_tb:0.1" +description: "XBAR DV tb" +filesets: + files_dv: + depend: + - lowrisc:ip:tlul + - lowrisc:dv:xbar_test + - lowrisc:dv:xbar_macros + files: + - tb.sv + file_type: systemVerilogSource + +targets: + default: + filesets: + - files_dv diff --git a/src/tlul/generic_dv/tests/xbar_base_test.sv b/src/tlul/generic_dv/tests/xbar_base_test.sv new file mode 100644 index 0000000..7bd877d --- /dev/null +++ b/src/tlul/generic_dv/tests/xbar_base_test.sv @@ -0,0 +1,46 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class xbar_base_test extends dv_base_test #(.ENV_T(xbar_env), .CFG_T(xbar_env_cfg)); + `uvm_component_utils(xbar_base_test) + `uvm_component_new + + virtual function void build_phase(uvm_phase phase); + max_quit_count = 50; + test_timeout_ns = 600_000_000; // 600ms + super.build_phase(phase); + + if (cfg.zero_delays) begin + cfg.allow_host_drop_valid_wo_ready = 0; + cfg.allow_device_drop_valid_wo_ready = 0; + cfg.min_host_req_delay = 0; + cfg.max_host_req_delay = 0; + cfg.min_host_rsp_delay = 0; + cfg.max_host_rsp_delay = 0; + cfg.min_device_req_delay = 0; + cfg.max_device_req_delay = 0; + cfg.min_device_rsp_delay = 0; + cfg.max_device_rsp_delay = 0; + end + void'($value$plusargs("allow_host_drop_valid_wo_ready=%d", + cfg.allow_host_drop_valid_wo_ready)); + void'($value$plusargs("allow_device_drop_valid_wo_ready=%d", + cfg.allow_device_drop_valid_wo_ready)); + void'($value$plusargs("min_host_valid_len=%d", cfg.min_host_valid_len)); + void'($value$plusargs("max_host_valid_len=%d", cfg.max_host_valid_len)); + void'($value$plusargs("min_device_valid_len=%d", cfg.min_device_valid_len)); + void'($value$plusargs("max_device_valid_len=%d", cfg.max_device_valid_len)); + void'($value$plusargs("max_host_req_delay=%d", cfg.max_host_req_delay)); + void'($value$plusargs("min_host_rsp_delay=%d", cfg.min_host_rsp_delay)); + void'($value$plusargs("max_host_rsp_delay=%d", cfg.max_host_rsp_delay)); + void'($value$plusargs("min_device_req_delay=%d", cfg.min_device_req_delay)); + void'($value$plusargs("max_device_req_delay=%d", cfg.max_device_req_delay)); + void'($value$plusargs("min_device_rsp_delay=%d", cfg.min_device_rsp_delay)); + void'($value$plusargs("max_device_rsp_delay=%d", cfg.max_device_rsp_delay)); + void'($value$plusargs("num_enabled_hosts=%d", cfg.num_enabled_hosts)); + void'($value$plusargs("short_xbar_test=%b", cfg.short_xbar_test)); + cfg.update_agent_cfg(); + endfunction : build_phase + +endclass : xbar_base_test diff --git a/src/tlul/generic_dv/tests/xbar_error_test.sv b/src/tlul/generic_dv/tests/xbar_error_test.sv new file mode 100644 index 0000000..46ee911 --- /dev/null +++ b/src/tlul/generic_dv/tests/xbar_error_test.sv @@ -0,0 +1,21 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// override cip_tl_seq_item with xbar_seq_err_item to disable TL protocol related constraint +class xbar_error_test extends xbar_base_test; + `uvm_component_utils(xbar_error_test) + `uvm_component_new + + virtual function void build_phase(uvm_phase phase); + super.build_phase(phase); + cip_base_pkg::cip_tl_seq_item::type_id::set_type_override(xbar_seq_err_item::get_type()); + endfunction : build_phase + + virtual task run_phase(uvm_phase phase); + // disable assertions for TL errors + uvm_config_db#(bit)::set(null, "*", "tlul_assert_en", 0); + uvm_config_db#(bit)::set(null, "*", "tlul_d_error_assert_en", 0); + super.run_phase(phase); + endtask : run_phase +endclass : xbar_error_test diff --git a/src/tlul/generic_dv/tests/xbar_test.core b/src/tlul/generic_dv/tests/xbar_test.core new file mode 100644 index 0000000..d250455 --- /dev/null +++ b/src/tlul/generic_dv/tests/xbar_test.core @@ -0,0 +1,20 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:dv:xbar_test:0.1" +description: "xbar DV UVM test" +filesets: + files_dv: + depend: + - lowrisc:dv:xbar_env + files: + - xbar_test_pkg.sv + - xbar_base_test.sv: {is_include_file: true} + - xbar_error_test.sv: {is_include_file: true} + file_type: systemVerilogSource + +targets: + default: + filesets: + - files_dv diff --git a/src/tlul/generic_dv/tests/xbar_test_pkg.sv b/src/tlul/generic_dv/tests/xbar_test_pkg.sv new file mode 100644 index 0000000..1f1e0ca --- /dev/null +++ b/src/tlul/generic_dv/tests/xbar_test_pkg.sv @@ -0,0 +1,19 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// --------------------------------------------- +// xBar test package +// --------------------------------------------- +package xbar_test_pkg; + + import uvm_pkg::*; + import xbar_env_pkg::*; + import tl_agent_pkg::*; + import dv_utils_pkg::*; + import dv_lib_pkg::*; + + `include "xbar_base_test.sv" + `include "xbar_error_test.sv" + +endpackage diff --git a/src/tlul/generic_dv/xbar_sim_cfg.hjson b/src/tlul/generic_dv/xbar_sim_cfg.hjson new file mode 100644 index 0000000..c48d106 --- /dev/null +++ b/src/tlul/generic_dv/xbar_sim_cfg.hjson @@ -0,0 +1,49 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + // Name of the sim cfg: set in the sim_cfg that imports this file + // name: "{dut}" + + // Top level testbench name (sv module). + tb: tb + + // Top level dut name (sv module): set in the autogenerated sim cfg file that imports this. + dut: "" + + // Simulator used to sign off this block + tool: vcs + + // The top level (chip) into which this xbar is meant to go. This is set in the sim_cfg that + // imports this file. + top_chip: "" + + // Fusesoc core file used for building the file list. + fusesoc_core: "lowrisc:dv:{top_chip}_{dut}_sim:0.1" + + // Give the path to the testplan file since it's not in the default location. + testplan_doc_path: "{proj_root}/hw/ip/tlul/data/tlul_testplan.hjson" + + // Bypass VCS CHECK_SUM check as the exclusion file is generated without proper CHECK_SUM value + vcs_cov_analyze_opts: ["-excl_bypass_checks"] + vcs_cov_report_opts: ["-excl_bypass_checks"] + xcelium_cov_analyze_opts: [] + xcelium_cov_report_opts: [] + + cov_analyze_opts: ["{{tool}_cov_analyze_opts}"] + cov_report_opts: ["{{tool}_cov_report_opts}"] + + // Import additional common sim cfg files. + import_cfgs: [// Project wide common sim cfg file + "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson", + "{proj_root}/hw/ip/tlul/generic_dv/xbar_tests.hjson"] + + // Add additional tops for simulation. + sim_tops: ["{dut}_bind"] + + // Default iterations for all tests - each test entry can override this. + reseed: 50 + + // Enable cdc instrumentation. + run_opts: ["+cdc_instrumentation_enabled=1"] +} diff --git a/src/tlul/generic_dv/xbar_tests.hjson b/src/tlul/generic_dv/xbar_tests.hjson new file mode 100644 index 0000000..6216b5d --- /dev/null +++ b/src/tlul/generic_dv/xbar_tests.hjson @@ -0,0 +1,210 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + // Run with a named build mode, and enable a named run mode. This allows an external testbench to + // override this build / run mode to apply additional common settings for all of these tests. + build_modes: [ + { + name: xbar_build_mode + } + ] + run_modes: [ + { + name: xbar_run_mode + } + ] + + // We rename the "default" build mode to "xbar_build_mode" so that it can be use to apply + // additional settings externally. We hence, map other settings that assume the build mode to be + // called as "default" to "xbar_build_mode". + xbar_build_mode_vcs_cov_cfg_file: "{default_vcs_cov_cfg_file}" + xbar_build_mode_xcelium_cov_cfg_file: "{default_xcelium_cov_cfg_file}" + + // List of test specifications. + tests: [ + { + name: "xbar_smoke" + build_mode: "xbar_build_mode" + en_run_modes: ["xbar_run_mode"] + uvm_test: xbar_base_test + uvm_test_seq: xbar_smoke_vseq + } + + { + name: "xbar_smoke_zero_delays" + build_mode: "xbar_build_mode" + en_run_modes: ["xbar_run_mode"] + uvm_test: xbar_base_test + uvm_test_seq: xbar_smoke_vseq + run_opts: ["+zero_delays=1"] + } + + { + name: "xbar_smoke_large_delays" + build_mode: "xbar_build_mode" + en_run_modes: ["xbar_run_mode"] + uvm_test: xbar_base_test + uvm_test_seq: xbar_smoke_vseq + run_opts: ["+max_host_req_delay=1000", + "+max_host_rsp_delay=1000", + "+max_device_req_delay=1000", + "+max_device_rsp_delay=1000", + "+max_host_valid_len=2000", + "+max_device_valid_len=2000"] + } + + { + name: "xbar_smoke_slow_rsp" + build_mode: "xbar_build_mode" + en_run_modes: ["xbar_run_mode"] + uvm_test: xbar_base_test + uvm_test_seq: xbar_smoke_vseq + run_opts: ["+max_host_req_delay=10", + "+max_host_rsp_delay=1000", + "+max_device_req_delay=1000", + "+max_device_rsp_delay=10", + "+max_host_valid_len=2000", + "+max_device_valid_len=2000"] + } + + { + name: "xbar_random" + build_mode: "xbar_build_mode" + en_run_modes: ["xbar_run_mode"] + uvm_test: xbar_base_test + uvm_test_seq: xbar_random_vseq + } + + { + name: "xbar_random_zero_delays" + build_mode: "xbar_build_mode" + en_run_modes: ["xbar_run_mode"] + uvm_test: xbar_base_test + uvm_test_seq: xbar_random_vseq + run_opts: ["+zero_delays=1"] + } + + { + name: "xbar_random_large_delays" + build_mode: "xbar_build_mode" + en_run_modes: ["xbar_run_mode"] + uvm_test: xbar_base_test + uvm_test_seq: xbar_random_vseq + run_opts: ["+max_host_req_delay=1000", + "+max_host_rsp_delay=1000", + "+max_device_req_delay=1000", + "+max_device_rsp_delay=1000", + "+max_host_valid_len=2000", + "+max_device_valid_len=2000"] + } + + { + name: "xbar_random_slow_rsp" + build_mode: "xbar_build_mode" + en_run_modes: ["xbar_run_mode"] + uvm_test: xbar_base_test + uvm_test_seq: xbar_random_vseq + run_opts: ["+max_host_req_delay=10", + "+max_host_rsp_delay=1000", + "+max_device_req_delay=1000", + "+max_device_rsp_delay=10", + "+max_host_valid_len=2000", + "+max_device_valid_len=2000"] + } + + { + name: "xbar_access_same_device" + build_mode: "xbar_build_mode" + en_run_modes: ["xbar_run_mode"] + uvm_test: xbar_base_test + uvm_test_seq: xbar_access_same_device_vseq + } + + { + name: "xbar_access_same_device_slow_rsp" + build_mode: "xbar_build_mode" + en_run_modes: ["xbar_run_mode"] + uvm_test: xbar_base_test + uvm_test_seq: xbar_access_same_device_vseq + run_opts: ["+max_host_req_delay=10", + "+max_host_rsp_delay=1000", + "+max_device_req_delay=1000", + "+max_device_rsp_delay=10", + "+max_host_valid_len=2000", + "+max_device_valid_len=2000"] + } + + { + name: "xbar_same_source" + build_mode: "xbar_build_mode" + en_run_modes: ["xbar_run_mode"] + uvm_test: xbar_base_test + uvm_test_seq: xbar_same_source_vseq + } + + { + name: "xbar_error_random" + build_mode: "xbar_build_mode" + en_run_modes: ["xbar_run_mode"] + uvm_test: xbar_error_test + uvm_test_seq: xbar_random_vseq + } + + { + name: "xbar_unmapped_addr" + build_mode: "xbar_build_mode" + en_run_modes: ["xbar_run_mode"] + uvm_test: xbar_base_test + uvm_test_seq: xbar_unmapped_addr_vseq + } + + { + name: "xbar_error_and_unmapped_addr" + build_mode: "xbar_build_mode" + en_run_modes: ["xbar_run_mode"] + uvm_test: xbar_error_test + uvm_test_seq: xbar_unmapped_addr_vseq + } + + { + name: "xbar_stress_all" + build_mode: "xbar_build_mode" + en_run_modes: ["xbar_run_mode"] + uvm_test: xbar_base_test + uvm_test_seq: xbar_stress_all_vseq + } + + { + name: "xbar_stress_all_with_rand_reset" + build_mode: "xbar_build_mode" + en_run_modes: ["xbar_run_mode"] + uvm_test: xbar_base_test + uvm_test_seq: xbar_stress_all_with_rand_reset_vseq + } + + { + name: "xbar_stress_all_with_error" + build_mode: "xbar_build_mode" + en_run_modes: ["xbar_run_mode"] + uvm_test: xbar_error_test + uvm_test_seq: xbar_stress_all_vseq + } + + { + name: "xbar_stress_all_with_reset_error" + build_mode: "xbar_build_mode" + en_run_modes: ["xbar_run_mode"] + uvm_test: xbar_error_test + uvm_test_seq: xbar_stress_all_with_rand_reset_vseq + } + ] + + // List of regressions. + regressions: [ + { + name: smoke + tests: ["xbar_smoke"] + } + ] +} diff --git a/src/tlul/headers.core b/src/tlul/headers.core new file mode 100644 index 0000000..3da0e1c --- /dev/null +++ b/src/tlul/headers.core @@ -0,0 +1,21 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:tlul:headers:0.1" +description: "TL-UL headers" + +filesets: + files_rtl: + depend: + - lowrisc:constants:top_pkg + - lowrisc:prim:secded + - lowrisc:prim:mubi + files: + - rtl/tlul_pkg.sv + file_type: systemVerilogSource + +targets: + default: + filesets: + - files_rtl diff --git a/src/tlul/lint/tlul_adapter_host.vlt b/src/tlul/lint/tlul_adapter_host.vlt new file mode 100644 index 0000000..b8340b2 --- /dev/null +++ b/src/tlul/lint/tlul_adapter_host.vlt @@ -0,0 +1,4 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// diff --git a/src/tlul/lint/tlul_adapter_host.waiver b/src/tlul/lint/tlul_adapter_host.waiver new file mode 100644 index 0000000..971cb60 --- /dev/null +++ b/src/tlul/lint/tlul_adapter_host.waiver @@ -0,0 +1,14 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# waiver file for TLUL elements lint + +waive -rules {HIER_BRANCH_NOT_READ INPUT_NOT_READ} \ + -location {tlul_adapter_host.sv} \ + -regexp {'(clk_i|rst_ni)' is not read from} \ + -comment "These 2 signals are only used by assertions" +waive -rules {HIER_NET_NOT_READ INPUT_NOT_READ} \ + -location {tlul_adapter_host.sv} \ + -regexp {'tl_i.d_(error|opcode|param|sink|size|source|user)' is not read from} \ + -comment "Not all fields of response needed" diff --git a/src/tlul/lint/tlul_adapter_reg.vlt b/src/tlul/lint/tlul_adapter_reg.vlt new file mode 100644 index 0000000..b8340b2 --- /dev/null +++ b/src/tlul/lint/tlul_adapter_reg.vlt @@ -0,0 +1,4 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// diff --git a/src/tlul/lint/tlul_adapter_reg.waiver b/src/tlul/lint/tlul_adapter_reg.waiver new file mode 100644 index 0000000..0ef2a9b --- /dev/null +++ b/src/tlul/lint/tlul_adapter_reg.waiver @@ -0,0 +1,13 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# waiver file for TLUL elements lint + +# Adapter (RegIF) +waive -rules PARTIAL_CONST_ASSIGN -location {tlul_adapter_reg.sv} -regexp {rspop.*conditionally assigned a constant} \ + -comment "makes the code more readable" +waive -rules CONST_FF -location {tlul_adapter_reg.sv} -regexp {rspop.*is driven by constant zeros} \ + -comment "makes the code more readable" +waive -rules INPUT_NOT_READ -location {tlul_adapter_reg.sv} -regexp {Input port.*a_(address|param|user).*not read from} \ + -comment "several TLUL signals are not used by register file" diff --git a/src/tlul/lint/tlul_adapter_sram.vlt b/src/tlul/lint/tlul_adapter_sram.vlt new file mode 100644 index 0000000..acd297f --- /dev/null +++ b/src/tlul/lint/tlul_adapter_sram.vlt @@ -0,0 +1,17 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// + +`verilator_config + +// This signal is only used by an assertion. +lint_off -rule UNUSED -file "*/rtl/tlul_adapter_sram.sv" -match "Signal is not used: 'rspfifo_wready'" + +// Signal is not used: clk_i +// leaving clk and reset connected in-case we want to add assertions +lint_off -rule UNUSED -file "*/rtl/tlul_sram_byte.sv" -match "*clk_i*" + +// Signal is not used: rst_ni +// leaving clk and reset connected in-case we want to add assertions +lint_off -rule UNUSED -file "*/rtl/tlul_sram_byte.sv" -match "*rst_ni*" diff --git a/src/tlul/lint/tlul_adapter_sram.waiver b/src/tlul/lint/tlul_adapter_sram.waiver new file mode 100644 index 0000000..cfdadef --- /dev/null +++ b/src/tlul/lint/tlul_adapter_sram.waiver @@ -0,0 +1,31 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# waiver file for TLUL elements lint + +# Adapter (SRAM) +# INPUT_NOT_READ +waive -rules INPUT_NOT_READ -location {tlul_adapter_sram.sv} -regexp {Input port 'tl_i.a_(mask|param|user)} \ + -comment "Not necessary for SRAM access" +waive -rules HIER_NET_NOT_READ -regexp {Connected net 'tl_i.a_(mask|param|user).* is not read from in module 'tlul_adapter_sram'} \ + -comment "Not necessary for SRAM access" +waive -rules HIER_NET_NOT_READ -regexp {'rspfifo_full' is not read from in module 'tlul_adapter_sram'} \ + -comment "This signal is only used by assertions" +waive -rules CONST_OUTPUT -location {tlul_adapter_sram.sv} -regexp {tl_o\.d_(param|sink|user)} \ + -comment "Tied to 0" +waive -rules INPUT_NOT_READ -regexp {Input port 'tl_i.a_address.*' is not read from} \ + -comment "Not all bits of a_address are used (depending on the address parameters)" +waive -rules HIER_NET_NOT_READ -regexp {Connected net 'tl_i.a_address.*' at tlul_adapter_sram.sv.* is not read from in module 'tlul_adapter_sram'} \ + -comment "Not all bits of a_address are used (depending on the address parameters)" +waive -rules HIER_NET_NOT_READ -msg {Net 'rspfifo_wready' is not read from in module 'tlul_adapter_sram'} \ + -comment "This signal is only used by an assertion" +waive -rules NOT_READ -msg {Signal 'rspfifo_wready' is not read from in module 'tlul_adapter_sram'} \ + -comment "This signal is only used by an assertion" +waive -rules VAR_INDEX_RANGE -regexp {.*woffset' of length 1 is larger than the 0 bits required to address.*} \ + -comment "The woffset signal is tied to constant 0 in this case. Fixing this warning in RTL would complicate \ + the design since multiple generate blocks would be needed with almost identical content." +waive -rules HIER_BRANCH_NOT_READ -location {tlul_sram_byte.sv} -regexp {Net '(clk_i|rst_ni)' is not read from in module 'tlul_sram_byte'} \ + -comment "If EnableIntg=0, the module is just passed through" +waive -rules INPUT_NOT_READ -location {tlul_sram_byte.sv} -regexp {Input port '(clk_i|rst_ni)' is not read from} \ + -comment "If EnableIntg=0, the module is just passed through" diff --git a/src/tlul/lint/tlul_common.vlt b/src/tlul/lint/tlul_common.vlt new file mode 100644 index 0000000..54c798e --- /dev/null +++ b/src/tlul/lint/tlul_common.vlt @@ -0,0 +1,13 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +`verilator_config + +// TLUL Error +// All error checkings are comb logic and only portion of signals are used +lint_off -rule UNUSED -file "*/rtl/tlul_err.sv" + +// FIFOs +// The depth parameters are of type int unsigned, but the higher-level modules can extract the per-port FIFO depths from a M|N x 4 bit array and drive the LSBs only. +lint_off -rule WIDTH -file "*/rtl/tlul_fifo_sync.sv" -match "Operator VAR '*Depth' expects 32 bits on the Initial value, but Initial value's CONST '*' generates 4 bits." diff --git a/src/tlul/lint/tlul_common.waiver b/src/tlul/lint/tlul_common.waiver new file mode 100644 index 0000000..7e40f31 --- /dev/null +++ b/src/tlul/lint/tlul_common.waiver @@ -0,0 +1,17 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# waiver file for common TLUL elements + +# TLUL Error +waive -rules {HIER_NET_NOT_READ HIER_BRANCH_NOT_READ INPUT_NOT_READ NOT_READ PARAM_NOT_USED} -location {tlul_err.sv} \ + -comment "All error checkings are comb logic and only portion of signals are used" +waive -rules {ASSIGN_SIGN} -location {tlul_err.sv} -regexp {Unsigned target 'mask'} \ + -comment "Waive for readability" +waive -rules {HIER_NET_NOT_READ} -regexp {Connected net 'tl_i.a_(address|param|user).*in module 'tlul_err'} \ + -comment "unused signal is back-propagated to the instance" + +# TL-UL fifo +waive -rules {HIER_BRANCH_NOT_READ} -location {tlul_fifo_sync.sv} -regexp {Connected net '(clk_i|rst_ni)' at prim_fifo_sync.sv:.* is not read from in module 'prim_fifo_sync'} \ + -comment "In passthrough mode, clk and reset are not read form within this module" diff --git a/src/tlul/lint/tlul_lc_gate.vlt b/src/tlul/lint/tlul_lc_gate.vlt new file mode 100644 index 0000000..c589a2d --- /dev/null +++ b/src/tlul/lint/tlul_lc_gate.vlt @@ -0,0 +1,24 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// + +`verilator_config + +// These two signals are arrays that (combinatorially) feed between the +// indices. Tell Verilator to schedule the entries separately to avoid an +// UNOPTFLAT warning. +split_var -module "tlul_caliptra_ss_lc_gate" -var "tl_h2d_int" +split_var -module "tlul_caliptra_ss_lc_gate" -var "tl_d2h_int" + +// In tlul_caliptra_ss_lc_gate.sv, there's an always_comb block that writes to +// tl_h2d_error. This h2d signal feeds into the d2h signal through +// u_tlul_err_resp, which means a write to tl_h2d_error causes a change in +// tl_d2h_error, which retriggers the alway_comb block. This causes Verilator's +// reasonably cautious tracking logic to infer a circular dependency, giving +// UNOPTFLAT. +// +// The isolate_assignments metacomment here tells Verilator to split up that +// block and track the writes to tl_h2d_error separately from all the rest. +// This undoes the false loop. +isolate_assignments -module "tlul_caliptra_ss_lc_gate" -var "tl_h2d_error" diff --git a/src/tlul/lint/tlul_socket_1n.vlt b/src/tlul/lint/tlul_socket_1n.vlt new file mode 100644 index 0000000..b5e3601 --- /dev/null +++ b/src/tlul/lint/tlul_socket_1n.vlt @@ -0,0 +1,8 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +`verilator_config + +// a_ready not needed, goes into FIFO +lint_off -rule UNUSED -file "*/rtl/tlul_socket_1n.sv" -match "Bits of signal are not used: 'tl_t_p'[0]" diff --git a/src/tlul/lint/tlul_socket_1n.waiver b/src/tlul/lint/tlul_socket_1n.waiver new file mode 100644 index 0000000..c89edc0 --- /dev/null +++ b/src/tlul/lint/tlul_socket_1n.waiver @@ -0,0 +1,23 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# waiver file for TLUL elements lint + +# socket 1:N +waive -rules INVALID_COMPARE -location {tlul_socket_1n.sv} -regexp {Comparison '.*dev_select_t == NWD'.*can never be true} \ + -comment "lint appears to be confused about the width expansion of NWD'(2)'" +waive -rules MIXED_SIGN -location {tlul_socket_1n.sv} -regexp {Unsigned operand .* and signed .NWD} \ + -comment "is there a way to make NWD'(idx)' an unsigned operand?" +waive -rules HIER_NET_NOT_READ -location {tlul_socket_1n.sv} -regexp {a_(address|data|mask|param|size|user.*)' in module 'tlul_socket_1n'} \ + -comment "request collateral is not used in \[N\] case, just for error response" +waive -rules NOT_READ -location {tlul_socket_1n.sv} -regexp {'tl_t_p.a_ready' is not read from in module 'tlul_socket_1n'} \ + -comment "a_ready not needed, goes into FIFO" +waive -rules INTEGER -location {tlul_socket_1n.sv} -msg {'idx' of type int used as a non-constant value} \ + -comment "This compares int idx (signed) with a multibit logic variable (unsigned), which is fine" + +# err_rsp +waive -rules INPUT_NOT_READ -location {tlul_err_resp.sv} -regexp {Input port 'tl_h_i.a_.*' is not read from in module 'tlul_err_resp'} \ + -comment "error response does not require command/address information" +waive -rules CONST_OUTPUT -location {tlul_err_resp.sv} -regexp {Output 'tl_h_o.d_.*' is driven by constant} \ + -comment "error response hard codes reponse data collateral" diff --git a/src/tlul/lint/tlul_socket_m1.vlt b/src/tlul/lint/tlul_socket_m1.vlt new file mode 100644 index 0000000..8242684 --- /dev/null +++ b/src/tlul/lint/tlul_socket_m1.vlt @@ -0,0 +1,12 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// + +`verilator_config + +// tlul_socket_m1 uses an arbiter to route the h2d TL packets. We represent +// them by a tlul_pkg::tl_h2d_t object, but ignore the a_valid and d_ready +// fields. Rather than explicitly pull out the other bits of the structure, +// just waive the warning (and assume the synthesis tool will chuck them away). +lint_off -rule UNUSED -file "*/rtl/tlul_socket_m1.sv" -match "Bits of signal are not used: 'arb_data'[*,0]" diff --git a/src/tlul/lint/tlul_socket_m1.waiver b/src/tlul/lint/tlul_socket_m1.waiver new file mode 100644 index 0000000..81feed3 --- /dev/null +++ b/src/tlul/lint/tlul_socket_m1.waiver @@ -0,0 +1,17 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# waiver file for TLUL elements lint + +# socket M:1 +waive -rules HIER_NET_NOT_READ -location {tlul_socket_m1.sv} -regexp {a_.* in module 'tlul_socket_1n'} \ + -comment "request collateral is not used in \[N\] case, just for error response" +waive -rules HIER_NET_NOT_READ -location {tlul_socket_m1.sv} -regexp {Net 'arb_data.a_valid' is not read from in module 'tlul_socket_m1'} \ + -comment "valid is not used, it is assumed valid if it got into the arbiter" +waive -rules HIER_NET_NOT_READ -location {tlul_socket_m1.sv} -regexp {Net 'arb_data.d_ready' is not read from in module 'tlul_socket_m1'} \ + -comment "ready is not used, it is assumed valid if it got into the arbiter" +waive -rules NOT_READ -location {tlul_socket_m1.sv} -regexp {Signal 'arb_data.a_valid' is not read from in module 'tlul_socket_m1'} \ + -comment "valid is not used, it is assumed valid if it got into the arbiter" +waive -rules NOT_READ -location {tlul_socket_m1.sv} -regexp {Signal 'arb_data.d_ready' is not read from in module 'tlul_socket_m1'} \ + -comment "ready is not used, it is assumed valid if it got into the arbiter" diff --git a/src/tlul/lint/tlul_sram2tlul.vlt b/src/tlul/lint/tlul_sram2tlul.vlt new file mode 100644 index 0000000..b8340b2 --- /dev/null +++ b/src/tlul/lint/tlul_sram2tlul.vlt @@ -0,0 +1,4 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// diff --git a/src/tlul/lint/tlul_sram2tlul.waiver b/src/tlul/lint/tlul_sram2tlul.waiver new file mode 100644 index 0000000..8887d6b --- /dev/null +++ b/src/tlul/lint/tlul_sram2tlul.waiver @@ -0,0 +1,15 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# waiver file for TLUL elements lint + +# sram2tlul +waive -rules CONST_OUTPUT -location {sram2tlul.sv} -regexp {Output 'tl_o\.[ad]_.*' is driven by constant} \ + -comment "Outputs are fixed value for TL-UL converter" +waive -rules HIER_BRANCH_NOT_READ -location {sram2tlul.sv} -regexp {Net '(clk_i|rst_ni)' is not read from} \ + -comment "Leaving clock and reset port for next update, looking at TL-UL ready signal" +waive -rules INPUT_NOT_READ -location {sram2tlul.sv} -regexp {Input.*'(clk_i|rst_ni)' is not read} \ + -comment "leaving clock and reset in converter for future use, handling a_ready" +waive -rules INPUT_NOT_READ -location {sram2tlul.sv} -regexp {Input.*'tl_i\.[ad]_(ready|param|sink|size|source|user.*)' is not read} \ + -comment "Those values are not checked by SRAM TL-UL adapter" diff --git a/src/tlul/rtl/sram2tlul.sv b/src/tlul/rtl/sram2tlul.sv new file mode 100644 index 0000000..f967e2a --- /dev/null +++ b/src/tlul/rtl/sram2tlul.sv @@ -0,0 +1,62 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// SRAM interface to TL-UL converter +// Current version only supports if TL-UL width and SRAM width are same +// If SRAM interface requests more than MaxOutstanding cap, it generates +// error in simulation but not in Silicon. + +`include "caliptra_prim_assert.sv" + +module sram2tlul + import tlul_pkg::*; + #( + parameter int SramAw = 12, + parameter int SramDw = 32, + parameter logic [TL_AW-1:0] TlBaseAddr = 'h0 // Base address of SRAM request +) ( + input clk_i, + input rst_ni, + + output tl_h2d_t tl_o, + input tl_d2h_t tl_i, + + // SRAM + input mem_req_i, + input mem_write_i, + input [SramAw-1:0] mem_addr_i, + input [SramDw-1:0] mem_wdata_i, + output logic mem_rvalid_o, + output logic [SramDw-1:0] mem_rdata_o, + output logic [1:0] mem_error_o +); + + + + `CALIPTRA_ASSERT_INIT(wrongSramDw, SramDw == TL_DW) + + localparam int unsigned SRAM_DWB = $clog2(SramDw/8); + + assign tl_o.a_valid = mem_req_i; + assign tl_o.a_opcode = (mem_write_i) ? PutFullData : Get; + assign tl_o.a_param = '0; + assign tl_o.a_size = TL_SZW'(SRAM_DWB); // Max Size always + assign tl_o.a_source = '0; + assign tl_o.a_address = TlBaseAddr | + {{(TL_AW-SramAw-SRAM_DWB){1'b0}},mem_addr_i,{(SRAM_DWB){1'b0}}}; + assign tl_o.a_mask = '1; + assign tl_o.a_data = mem_wdata_i; + assign tl_o.a_user = '0; + + assign tl_o.d_ready = 1'b1; + + assign mem_rvalid_o = tl_i.d_valid && (tl_i.d_opcode == AccessAckData); + assign mem_rdata_o = tl_i.d_data; + assign mem_error_o = {2{tl_i.d_error}}; + + // below assertion fails when TL-UL doesn't accept request in a cycle, + // which is currently not supported by sram2tlul + `CALIPTRA_ASSERT(validNotReady, tl_o.a_valid |-> tl_i.a_ready) + +endmodule diff --git a/src/tlul/rtl/tlul_adapter_dmi.sv b/src/tlul/rtl/tlul_adapter_dmi.sv new file mode 100644 index 0000000..0570966 --- /dev/null +++ b/src/tlul/rtl/tlul_adapter_dmi.sv @@ -0,0 +1,182 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Tile-Link UL adapter for RISC-V debug module from the PULP project. +// +// Note that this module can only handle one outstanding request at a time. + +`include "prim_assert.sv" + +module tlul_adapter_dmi + import tlul_pkg::*; +#( + parameter bit CmdIntgCheck = 1, // 1: Enable command integrity check + parameter bit EnableRspIntgGen = 1, // 1: Generate response integrity + parameter bit EnableDataIntgGen = 1 // 1: Generate response data integrity +) ( + input clk_i, + input rst_ni, + + // TL-UL interface + input tl_h2d_t tl_h2d_i, + output tl_d2h_t tl_d2h_o, + + // control interface + output logic intg_error_o, + + output logic dmi_req_valid_o, + input logic dmi_req_ready_i, + output dm::dmi_req_t dmi_req_o, + + input logic dmi_resp_valid_i, + output logic dmi_resp_ready_o, + input dm::dmi_resp_t dmi_resp_i +); + + localparam int IdW = $bits(tl_h2d_i.a_source); + localparam int SzW = $bits(tl_h2d_i.a_size); + + logic a_ack, d_ack; // Indicates whether the corresponding valid/ready handshake completes. + logic outstanding_q; // Indicates whether there is a pending request. + assign a_ack = tl_h2d_i.a_valid & tl_d2h_o.a_ready; + assign d_ack = tl_d2h_o.d_valid & tl_h2d_i.d_ready; + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) outstanding_q <= 1'b0; + else if (a_ack) outstanding_q <= 1'b1; + else if (d_ack) outstanding_q <= 1'b0; + end + + // Decode Requests + logic rd_req, wr_req; + assign wr_req = tl_h2d_i.a_valid && ((tl_h2d_i.a_opcode == PutFullData) || + (tl_h2d_i.a_opcode == PutPartialData)); + assign rd_req = tl_h2d_i.a_valid && (tl_h2d_i.a_opcode == Get); + + // If we detect an error, the response will be returned immediately in the next cycle + // and we do not send a request out to the DMI. + logic error_d, error_q; + assign dmi_req_valid_o = (wr_req || rd_req) && !error_d; + // The DMI response can be accepted if there is a pending request without error. + assign dmi_resp_ready_o = outstanding_q && !error_q; + + // We expect a word-aligned address here, otherwise an error is returned (see further below). + assign dmi_req_o.addr = {2'b00, tl_h2d_i.a_address[top_pkg::TL_AW-1:2]}; + assign dmi_req_o.data = tl_h2d_i.a_data; + assign dmi_req_o.op = (wr_req) ? dm::DTM_WRITE : + (rd_req) ? dm::DTM_READ : dm::DTM_NOP; + + logic [IdW-1:0] reqid_q; + logic [SzW-1:0] reqsz_q; + tl_d_op_e rspop_q; + logic wr_req_q, rd_req_q; + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + reqid_q <= '0; + reqsz_q <= '0; + rspop_q <= AccessAck; + error_q <= 1'b0; + wr_req_q <= 1'b0; + rd_req_q <= 1'b0; + end else if (a_ack) begin + reqid_q <= tl_h2d_i.a_source; + reqsz_q <= tl_h2d_i.a_size; + // Return AccessAckData regardless of error + rspop_q <= (rd_req) ? AccessAckData : AccessAck; + rd_req_q <= rd_req; + wr_req_q <= wr_req; + error_q <= error_d; + end + end + + // Send back a bus error if the dm_csrs module responded with an error. + logic error_resp; + assign error_resp = error_q || (dmi_resp_i.resp == dm::DTM_ERR); + + tlul_pkg::tl_d2h_t tl_d2h_o_pre; + assign tl_d2h_o_pre = '{ + // We are ready to accept a request if there is no outstanding one and if the DMI is ready. + a_ready: dmi_req_ready_i && !outstanding_q, + // A data response is valid if the DMI response is valid and we've got an outstanding request. + // If the request resulted in an internal error, the error response is returned without a DMI + // response, since the request to the DMI has been suppressed by the error. + d_valid: (dmi_resp_valid_i || error_q) && outstanding_q, + d_opcode: rspop_q, + d_param: '0, + d_size: reqsz_q, + d_source: reqid_q, + d_sink: '0, + // Blank data upon error in the same way as other TL-UL adapters would in OpenTitan. + d_data: (rd_req_q && !(error_resp || wr_req_q)) ? dmi_resp_i.data : {top_pkg::TL_DW{1'b1}}, + d_user: '0, + d_error: error_resp + }; + + // outgoing integrity generation + tlul_rsp_intg_gen #( + .EnableRspIntgGen(EnableRspIntgGen), + .EnableDataIntgGen(EnableDataIntgGen) + ) u_rsp_intg_gen ( + .tl_i(tl_d2h_o_pre), + .tl_o(tl_d2h_o) + ); + + logic intg_error; + if (CmdIntgCheck) begin : gen_cmd_intg_check + logic intg_error_q; + tlul_cmd_intg_chk u_cmd_intg_chk ( + .tl_i(tl_h2d_i), + .err_o(intg_error) + ); + // permanently latch integrity error until reset + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + intg_error_q <= 1'b0; + end else if (intg_error) begin + intg_error_q <= 1'b1; + end + end + assign intg_error_o = intg_error_q; + end else begin : gen_no_cmd_intg_check + assign intg_error = 1'b0; + assign intg_error_o = 1'b0; + end + + //////////////////// + // Error Handling // + //////////////////// + + logic addr_align_err; // Size and alignment + logic be_err; // Byte enable error. + logic malformed_meta_err; // User signal format error or unsupported + logic tl_err; // Common TL-UL error checker + assign error_d = addr_align_err || + be_err || + malformed_meta_err || + tl_err || + intg_error; + + // addr_align_err + // Raised if addr isn't aligned with the size + // Read size error is checked in tlul_assert.sv + // Here is it added due to the limitation of register interface. + // Only word-align is accepted based on comportability spec. + assign addr_align_err = (wr_req) && |tl_h2d_i.a_address[1:0]; + + // The DMI does not support a non-all-ones byte enable. + assign be_err = (wr_req) && !(&tl_h2d_i.a_mask); + + // Don't allow unsupported values. + assign malformed_meta_err = tl_a_user_chk(tl_h2d_i.a_user); + + // tl_err : separate checker + tlul_err u_err ( + .clk_i, + .rst_ni, + .tl_i(tl_h2d_i), + .err_o (tl_err) + ); + + `ASSERT_INIT(DwMatchedWithDm_A, top_pkg::TL_DW == $bits(dmi_req_o.data)) + +endmodule : tlul_adapter_dmi diff --git a/src/tlul/rtl/tlul_adapter_host.sv b/src/tlul/rtl/tlul_adapter_host.sv new file mode 100644 index 0000000..4f06823 --- /dev/null +++ b/src/tlul/rtl/tlul_adapter_host.sv @@ -0,0 +1,190 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// tlul_adapter (Host adapter) converts basic req/grant/rvalid into TL-UL interface. If +// MAX_REQS == 1 it is purely combinational logic. If MAX_REQS > 1 flops are required. +// +// The host driving the adapter is responsible for ensuring it doesn't have more requests in flight +// than the specified MAX_REQS. +// +// The outgoing address is always word aligned. The access size is always the word size (as +// specified by TL_DW). For write accesses that occupy all lanes the operation is PutFullData, +// otherwise it is PutPartialData, mask is generated from be_i. For reads all lanes are enabled as +// required by TL-UL (every bit in mask set). +// +// When MAX_REQS > 1 tlul_adapter_host does not do anything to order responses from the TL-UL +// interface which could return them out of order. It is the host's responsibility to either only +// have outstanding requests to an address space it knows will return responses in order or to not +// care about out of order responses (note that if read data is returned out of order there is no +// way to determine this). + +`include "caliptra_prim_assert.sv" + +module tlul_adapter_host + import tlul_pkg::*; + import caliptra_prim_mubi_pkg::mubi4_t; +#( + parameter int unsigned MAX_REQS = 2, + parameter bit EnableDataIntgGen = 0, + parameter bit EnableRspDataIntgCheck = 0 +) ( + input clk_i, + input rst_ni, + + input req_i, + output logic gnt_o, + input logic [TL_AW-1:0] addr_i, + input logic we_i, + input logic [TL_DW-1:0] wdata_i, + input logic [DataIntgWidth-1:0] wdata_intg_i, + input logic [TL_DBW-1:0] be_i, + input mubi4_t instr_type_i, + input logic [RsvdWidth-1:0] user_rsvd_i, + + output logic valid_o, + output logic [TL_DW-1:0] rdata_o, + output logic [DataIntgWidth-1:0] rdata_intg_o, + output logic err_o, + output logic intg_err_o, + + output tl_h2d_t tl_o, + input tl_d2h_t tl_i +); + localparam int unsigned WordSize = $clog2(TL_DBW); + + logic [TL_AIW-1:0] tl_source; + logic [TL_DBW-1:0] tl_be; + tl_h2d_t tl_out; + + if (MAX_REQS == 1) begin : g_single_req + assign tl_source = '0; + end else begin : g_multiple_reqs + localparam int ReqNumW = $clog2(MAX_REQS); + localparam int unsigned MaxSource = MAX_REQS - 1; + localparam logic [ReqNumW-1:0] ReqNumOne = ReqNumW'(1'b1); + + logic [ReqNumW-1:0] source_d; + logic [ReqNumW-1:0] source_q; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + source_q <= '0; + end else begin + source_q <= source_d; + end + end + + always_comb begin + source_d = source_q; + + if (req_i && gnt_o) begin + if (source_q == MaxSource[ReqNumW-1:0]) begin + source_d = '0; + end else begin + source_d = source_q + ReqNumOne; + end + end + end + + assign tl_source = TL_AIW'(source_q); + end + + // For TL-UL Get opcode all active bytes must have their mask bit set, so all reads get all tl_be + // bits set. For writes the supplied be_i is used as the mask. + assign tl_be = ~we_i ? {TL_DBW{1'b1}} : be_i; + + assign tl_out = '{ + a_valid: req_i, + a_opcode: (~we_i) ? Get : + (&be_i) ? PutFullData : + PutPartialData, + a_param: 3'h0, + a_size: TL_SZW'(WordSize), + a_mask: tl_be, + a_source: tl_source, + a_address: {addr_i[31:WordSize], {WordSize{1'b0}}}, + a_data: wdata_i, + a_user: '{default: '0, data_intg: wdata_intg_i, instr_type: instr_type_i}, + d_ready: 1'b1 + }; + + tlul_cmd_intg_gen #(.EnableDataIntgGen (EnableDataIntgGen)) u_cmd_intg_gen ( + .tl_i(tl_out), + .tl_o(tl_o) + ); + + assign gnt_o = tl_i.a_ready; + + assign valid_o = tl_i.d_valid; + assign rdata_o = tl_i.d_data; + assign rdata_intg_o = tl_i.d_user.data_intg; + + logic intg_err; + tlul_rsp_intg_chk #( + .EnableRspDataIntgCheck(EnableRspDataIntgCheck) + ) u_rsp_chk ( + .tl_i, + .err_o(intg_err) + ); + + logic intg_err_q; + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + intg_err_q <= '0; + end else if (intg_err) begin + intg_err_q <= 1'b1; + end + end + + // err_o is transactional. This allows the host to continue + // debug without receiving an endless stream of errors. + assign err_o = tl_i.d_error | intg_err; + + // intg_err_o is permanent once detected, and should be used + // to trigger alerts + assign intg_err_o = intg_err_q | intg_err; + + // Addresses are assumed to be word-aligned, and the bottom bits are ignored + logic unused_addr_bottom_bits; + assign unused_addr_bottom_bits = ^addr_i[WordSize-1:0]; + + // Explicitly ignore unused fields of tl_i + logic unused_tl_i_fields; + assign unused_tl_i_fields = ^{tl_i.d_opcode, tl_i.d_param, + tl_i.d_size, tl_i.d_source, tl_i.d_sink, + tl_i.d_user}; + +`ifdef INC_ASSERT + //VCS coverage off + // pragma coverage off + localparam int OutstandingReqCntW = + (MAX_REQS == 2 ** $clog2(MAX_REQS)) ? $clog2(MAX_REQS) + 1 : $clog2(MAX_REQS); + localparam logic [OutstandingReqCntW-1:0] OutstandingReqCntOne = OutstandingReqCntW'(1'b1); + + logic [OutstandingReqCntW-1:0] outstanding_reqs_q; + logic [OutstandingReqCntW-1:0] outstanding_reqs_d; + + always_comb begin + outstanding_reqs_d = outstanding_reqs_q; + + if ((req_i && gnt_o) && !valid_o) begin + outstanding_reqs_d = outstanding_reqs_q + OutstandingReqCntOne; + end else if (!(req_i && gnt_o) && valid_o) begin + outstanding_reqs_d = outstanding_reqs_q - OutstandingReqCntOne; + end + end + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + outstanding_reqs_q <= '0; + end else begin + outstanding_reqs_q <= outstanding_reqs_d; + end + end + //VCS coverage on + // pragma coverage on + + `ASSERT(DontExceeedMaxReqs, req_i |-> outstanding_reqs_d <= MAX_REQS) +`endif +endmodule diff --git a/src/tlul/rtl/tlul_adapter_reg.sv b/src/tlul/rtl/tlul_adapter_reg.sv new file mode 100644 index 0000000..7f188ba --- /dev/null +++ b/src/tlul/rtl/tlul_adapter_reg.sv @@ -0,0 +1,231 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +`include "caliptra_prim_assert.sv" + +/** + * Tile-Link UL adapter for Register interface + * + * ICEBOX(#15822): Note that due to some modules with special needs (like + * the vendored-in RV_DM), this module has been extended so that it + * supports use cases outside of the generated reg_top module. This makes + * this adapter and its parameterization options a bit heavy. + * + * We should in the future come back to this and refactor / align the + * module and its parameterization needs. + */ + +module tlul_adapter_reg + import tlul_pkg::*; + import caliptra_prim_mubi_pkg::mubi4_t; +#( + parameter bit CmdIntgCheck = 0, // 1: Enable command integrity check + parameter bit EnableRspIntgGen = 0, // 1: Generate response integrity + parameter bit EnableDataIntgGen = 0, // 1: Generate response data integrity + parameter int RegAw = 8, // Width of register address + parameter int RegDw = 32, // Shall be matched with TL_DW + parameter int AccessLatency = 0, // 0: same cycle, 1: next cycle + localparam int RegBw = RegDw/8 +) ( + input clk_i, + input rst_ni, + + // TL-UL interface + input tl_h2d_t tl_i, + output tl_d2h_t tl_o, + + // control interface + input mubi4_t en_ifetch_i, + output logic intg_error_o, + + // Register interface + output logic re_o, + output logic we_o, + output logic [RegAw-1:0] addr_o, + output logic [RegDw-1:0] wdata_o, + output logic [RegBw-1:0] be_o, + input busy_i, + // The following two signals are expected + // to be returned in AccessLatency cycles. + input [RegDw-1:0] rdata_i, + // This can be a write or read error. + input error_i +); + + `CALIPTRA_ASSERT_INIT(AllowedLatency_A, AccessLatency inside {0, 1}) + + localparam int IW = $bits(tl_i.a_source); + localparam int SZW = $bits(tl_i.a_size); + + logic outstanding_q; // Indicates current request is pending + logic a_ack, d_ack; + + logic [RegDw-1:0] rdata, rdata_q; + logic error_q, error, err_internal, instr_error, intg_error; + + logic addr_align_err; // Size and alignment + logic tl_err; // Common TL-UL error checker + + logic [IW-1:0] reqid_q; + logic [SZW-1:0] reqsz_q; + tl_d_op_e rspop_q; + + logic rd_req, wr_req; + + assign a_ack = tl_i.a_valid & tl_o.a_ready; + assign d_ack = tl_o.d_valid & tl_i.d_ready; + // Request signal + assign wr_req = a_ack & ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData)); + assign rd_req = a_ack & (tl_i.a_opcode == Get); + + assign we_o = wr_req & ~err_internal; + assign re_o = rd_req & ~err_internal; + assign wdata_o = tl_i.a_data; + assign be_o = tl_i.a_mask; + + if (RegAw <= 2) begin : gen_only_one_reg + assign addr_o = '0; + end else begin : gen_more_regs + assign addr_o = {tl_i.a_address[RegAw-1:2], 2'b00}; // generate always word-align + end + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) outstanding_q <= 1'b0; + else if (a_ack) outstanding_q <= 1'b1; + else if (d_ack) outstanding_q <= 1'b0; + end + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + reqid_q <= '0; + reqsz_q <= '0; + rspop_q <= AccessAck; + end else if (a_ack) begin + reqid_q <= tl_i.a_source; + reqsz_q <= tl_i.a_size; + // Return AccessAckData regardless of error + rspop_q <= (rd_req) ? AccessAckData : AccessAck ; + end + end + + if (AccessLatency == 1) begin : gen_access_latency1 + logic wr_req_q, rd_req_q; + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + rdata_q <= '0; + error_q <= 1'b0; + wr_req_q <= 1'b0; + rd_req_q <= 1'b0; + end else begin + rd_req_q <= rd_req; + wr_req_q <= wr_req; + // Addressing phase + if (a_ack) begin + error_q <= err_internal; + // Response phase + end else begin + error_q <= error; + rdata_q <= rdata; + end + end + end + assign rdata = (error_i || error_q || wr_req_q) ? '1 : + (rd_req_q) ? rdata_i : + rdata_q; // backpressure case + assign error = (rd_req_q || wr_req_q) ? (error_q || error_i) : + error_q; // backpressure case + end else begin : gen_access_latency0 + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + rdata_q <= '0; + error_q <= 1'b0; + end else if (a_ack) begin + rdata_q <= (error_i || err_internal || wr_req) ? '1 : rdata_i; + error_q <= error_i || err_internal; + end + end + assign rdata = rdata_q; + assign error = error_q; + end + + tlul_pkg::tl_d2h_t tl_o_pre; + assign tl_o_pre = '{ + // busy is selected based on address + // thus if there is no valid transaction, we should ignore busy + a_ready: ~(outstanding_q | tl_i.a_valid & busy_i), + d_valid: outstanding_q, + d_opcode: rspop_q, + d_param: '0, + d_size: reqsz_q, + d_source: reqid_q, + d_sink: '0, + d_data: rdata, + d_user: '0, + d_error: error + }; + + // outgoing integrity generation + tlul_rsp_intg_gen #( + .EnableRspIntgGen(EnableRspIntgGen), + .EnableDataIntgGen(EnableDataIntgGen) + ) u_rsp_intg_gen ( + .tl_i(tl_o_pre), + .tl_o(tl_o) + ); + + if (CmdIntgCheck) begin : gen_cmd_intg_check + logic intg_error_q; + tlul_cmd_intg_chk u_cmd_intg_chk ( + .tl_i(tl_i), + .err_o(intg_error) + ); + // permanently latch integrity error until reset + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + intg_error_q <= 1'b0; + end else if (intg_error) begin + intg_error_q <= 1'b1; + end + end + assign intg_error_o = intg_error_q; + end else begin : gen_no_cmd_intg_check + assign intg_error = 1'b0; + assign intg_error_o = 1'b0; + end + + //////////////////// + // Error Handling // + //////////////////// + + // An instruction type transaction is only valid if en_ifetch is enabled + assign instr_error = caliptra_prim_mubi_pkg::mubi4_test_true_strict(tl_i.a_user.instr_type) & + caliptra_prim_mubi_pkg::mubi4_test_false_loose(en_ifetch_i); + + assign err_internal = addr_align_err | tl_err | instr_error | intg_error; + + // addr_align_err + // Raised if addr isn't aligned with the size + // Read size error is checked in tlul_assert.sv + // Here is it added due to the limitation of register interface. + always_comb begin + if (wr_req) begin + // Only word-align is accepted based on comportability spec + addr_align_err = |tl_i.a_address[1:0]; + end else begin + // No request + addr_align_err = 1'b0; + end + end + + // tl_err : separate checker + tlul_err u_err ( + .clk_i, + .rst_ni, + .tl_i, + .err_o (tl_err) + ); + + `CALIPTRA_ASSERT_INIT(MatchedWidthAssert, RegDw == TL_DW) + +endmodule diff --git a/src/tlul/rtl/tlul_adapter_sram.sv b/src/tlul/rtl/tlul_adapter_sram.sv new file mode 100644 index 0000000..63eaac8 --- /dev/null +++ b/src/tlul/rtl/tlul_adapter_sram.sv @@ -0,0 +1,674 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +`include "caliptra_prim_assert.sv" + +/** + * Tile-Link UL adapter for SRAM-like devices + * + * - Intentionally omitted BaseAddr in case of multiple memory maps are used in a SoC, + * it means that aliasing can happen if target device size in TL-UL crossbar is bigger + * than SRAM size + * - At most one of EnableDataIntgGen / EnableDataIntgPt can be enabled. However it + * possible for both to be disabled. + * A module can neither generate an integrity response nor pass through any pre-existing + * integrity. This might be the case for non-security critical memories where there is + * no stored integrity AND another entity upstream is already generating returning integrity. + * There is however no case where EnableDataIntgGen and EnableDataIntgPt are both true. + */ +module tlul_adapter_sram + import tlul_pkg::*; + import caliptra_prim_mubi_pkg::mubi4_t; +#( + parameter int SramAw = 12, + parameter int SramDw = 32, // Must be multiple of the TL width + parameter int Outstanding = 1, // Only one request is accepted + parameter int SramBusBankAW = 12, // SRAM bus address width of the SRAM bank. Only used + // when DataXorAddr=1. + parameter bit ByteAccess = 1, // 1: Enables sub-word write transactions. Note that this + // results in read-modify-write operations for integrity + // re-generation if EnableDataIntgPt is set to 1. + parameter bit ErrOnWrite = 0, // 1: Writes not allowed, automatically error + parameter bit ErrOnRead = 0, // 1: Reads not allowed, automatically error + parameter bit CmdIntgCheck = 0, // 1: Enable command integrity check + parameter bit EnableRspIntgGen = 0, // 1: Generate response integrity + parameter bit EnableDataIntgGen = 0, // 1: Generate response data integrity + parameter bit EnableDataIntgPt = 0, // 1: Passthrough command/response data integrity + parameter bit SecFifoPtr = 0, // 1: Duplicated fifo pointers + parameter bit EnableReadback = 0, // 1: Readback and check written/read data. + parameter bit DataXorAddr = 0, // 1: XOR data and address for address protection + localparam int WidthMult = SramDw / TL_DW, + localparam int IntgWidth = tlul_pkg::DataIntgWidth * WidthMult, + localparam int DataOutW = EnableDataIntgPt ? SramDw + IntgWidth : SramDw +) ( + input clk_i, + input rst_ni, + + // TL-UL interface + input tl_h2d_t tl_i, + output tl_d2h_t tl_o, + + // control interface + input mubi4_t en_ifetch_i, + + // SRAM interface + output logic req_o, + output mubi4_t req_type_o, + input gnt_i, + output logic we_o, + output logic [SramAw-1:0] addr_o, + output logic [DataOutW-1:0] wdata_o, + output logic [DataOutW-1:0] wmask_o, + output logic intg_error_o, + input [DataOutW-1:0] rdata_i, + input rvalid_i, + input [1:0] rerror_i, // 2 bit error [1]: Uncorrectable, [0]: Correctable + output logic compound_txn_in_progress_o, + input mubi4_t readback_en_i, + output logic readback_error_o, + input logic wr_collision_i, + input logic write_pending_i +); + + localparam int SramByte = SramDw/8; + localparam int DataBitWidth = caliptra_prim_util_pkg::vbits(SramByte); + localparam int WoffsetWidth = (SramByte == TL_DBW) ? 1 : + DataBitWidth - caliptra_prim_util_pkg::vbits(TL_DBW); + + logic error_det; // Internal protocol error checker + logic error_internal; // Internal protocol error checker + logic wr_attr_error; + logic instr_error; + logic wr_vld_error; + logic rd_vld_error; + logic rsp_fifo_error; + logic sramreqfifo_error; + logic reqfifo_error; + logic intg_error; + logic tlul_error; + logic readback_error; + logic sram_byte_readback_error; + + // readback check + logic readback_error_q; + if (EnableReadback) begin : gen_cmd_readback_check + assign readback_error = sram_byte_readback_error; + // permanently latch readback error until reset + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + readback_error_q <= '0; + end else if (readback_error) begin + readback_error_q <= 1'b1; + end + end + end else begin : gen_no_readback_check + logic unused_sram_byte_readback_error; + assign unused_sram_byte_readback_error = sram_byte_readback_error; + assign readback_error = '0; + assign readback_error_q = '0; + end + + // readback error output is permanent and should be used for alert generation + // or other downstream effects + assign readback_error_o = readback_error | readback_error_q; + + // integrity check + if (CmdIntgCheck) begin : gen_cmd_intg_check + tlul_cmd_intg_chk u_cmd_intg_chk ( + .tl_i(tl_i), + .err_o (intg_error) + ); + end else begin : gen_no_cmd_intg_check + assign intg_error = '0; + end + + // permanently latch integrity error until reset + logic intg_error_q; + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + intg_error_q <= '0; + end else if (intg_error || rsp_fifo_error || sramreqfifo_error || reqfifo_error) begin + intg_error_q <= 1'b1; + end + end + + // integrity error output is permanent and should be used for alert generation + // or other downstream effects + assign intg_error_o = intg_error | rsp_fifo_error | sramreqfifo_error | + reqfifo_error | intg_error_q; + + // wr_attr_error: Check if the request size, mask are permitted. + // Basic check of size, mask, addr align is done in tlul_err module. + // Here it checks any partial write if ByteAccess isn't allowed. + assign wr_attr_error = (tl_i.a_opcode == PutFullData || tl_i.a_opcode == PutPartialData) + ? ((ByteAccess == 0) ? + (tl_i.a_mask != '1 || tl_i.a_size != 2'h2) : 1'b0) + : 1'b0; + + // An instruction type transaction is only valid if en_ifetch is enabled + // If the instruction type is completely invalid, also considered an instruction error + assign instr_error = caliptra_prim_mubi_pkg::mubi4_test_invalid(tl_i.a_user.instr_type) | + (caliptra_prim_mubi_pkg::mubi4_test_true_strict(tl_i.a_user.instr_type) & + caliptra_prim_mubi_pkg::mubi4_test_false_loose(en_ifetch_i)); + + if (ErrOnWrite == 1) begin : gen_no_writes + assign wr_vld_error = tl_i.a_opcode != Get; + end else begin : gen_writes_allowed + assign wr_vld_error = 1'b0; + end + + if (ErrOnRead == 1) begin: gen_no_reads + assign rd_vld_error = tl_i.a_opcode == Get; + end else begin : gen_reads_allowed + assign rd_vld_error = 1'b0; + end + + // tlul protocol check + tlul_err u_err ( + .clk_i, + .rst_ni, + .tl_i(tl_i), + .err_o (tlul_error) + ); + + // error return is transactional and thus does not used the "latched" intg_err signal + assign error_det = wr_attr_error | wr_vld_error | rd_vld_error | instr_error | + tlul_error | intg_error; + + // from sram_byte to adapter logic + tl_h2d_t tl_i_int; + // from adapter logic to sram_byte + tl_d2h_t tl_o_int; + // from sram_byte to rsp_gen + tl_d2h_t tl_out; + + // not all parts of tl_i_int are used + logic unused_tl_i_int; + assign unused_tl_i_int = ^tl_i_int; + + tlul_rsp_intg_gen #( + .EnableRspIntgGen(EnableRspIntgGen), + .EnableDataIntgGen(EnableDataIntgGen) + ) u_rsp_gen ( + .tl_i(tl_out), + .tl_o + ); + + // byte handling for integrity + tlul_sram_byte #( + .EnableIntg(ByteAccess & EnableDataIntgPt & !ErrOnWrite), + .Outstanding(Outstanding), + .EnableReadback(EnableReadback) + ) u_sram_byte ( + .clk_i, + .rst_ni, + .tl_i, + .tl_o(tl_out), + .tl_sram_o(tl_i_int), + .tl_sram_i(tl_o_int), + .error_i(error_det), + .error_o(error_internal), + .alert_o(sram_byte_readback_error), + .compound_txn_in_progress_o, + .readback_en_i, + .wr_collision_i, + .write_pending_i + ); + + typedef struct packed { + logic [TL_DBW-1:0] mask ; // Byte mask within the TL-UL word + logic [WoffsetWidth-1:0] woffset ; // Offset of the TL-UL word within the SRAM word + } sram_req_t ; + + typedef struct packed { + logic [SramBusBankAW-1:0] addr; // Address of the request going to the memory. + } sram_req_addr_t ; + + typedef enum logic [1:0] { + OpWrite, + OpRead, + OpUnknown + } req_op_e ; + + typedef struct packed { + req_op_e op ; + logic error ; + caliptra_prim_mubi_pkg::mubi4_t instr_type; + logic [TL_SZW-1:0] size ; + logic [TL_AIW-1:0] source ; + } req_t ; + + typedef struct packed { + logic [TL_DW-1:0] data ; + logic [DataIntgWidth-1:0] data_intg ; + logic error ; + } rsp_t ; + + localparam int SramReqFifoWidth = $bits(sram_req_t) ; + localparam int ReqFifoWidth = $bits(req_t) ; + localparam int RspFifoWidth = $bits(rsp_t) ; + + // FIFO signal in case OutStand is greater than 1 + // If request is latched, {write, source} is pushed to req fifo. + // Req fifo is popped when D channel is acknowledged (v & r) + // D channel valid is asserted if it is write request or rsp fifo not empty if read. + logic reqfifo_wvalid, reqfifo_wready; + logic reqfifo_rvalid, reqfifo_rready; + req_t reqfifo_wdata, reqfifo_rdata; + + logic sramreqfifo_wvalid, sramreqfifo_wready; + logic sramreqfifo_rready; + sram_req_t sramreqfifo_wdata, sramreqfifo_rdata; + + logic sramreqaddrfifo_wready; + logic [SramBusBankAW-1:0] sramreqaddrfifo_wdata, sramreqaddrfifo_rdata; + + logic rspfifo_wvalid, rspfifo_wready; + logic rspfifo_rvalid, rspfifo_rready; + rsp_t rspfifo_wdata, rspfifo_rdata; + + logic a_ack, d_ack, sram_ack; + assign a_ack = tl_i_int.a_valid & tl_o_int.a_ready ; + assign d_ack = tl_o_int.d_valid & tl_i_int.d_ready ; + assign sram_ack = req_o & gnt_i ; + + // Valid handling + logic d_valid, d_error; + always_comb begin + d_valid = 1'b0; + + if (reqfifo_rvalid) begin + if (reqfifo_rdata.error) begin + // Return error response. Assume no request went out to SRAM + d_valid = 1'b1; + end else if (reqfifo_rdata.op == OpRead) begin + d_valid = rspfifo_rvalid; + end else begin + // Write without error + d_valid = 1'b1; + end + end else begin + d_valid = 1'b0; + end + end + + + + always_comb begin + d_error = 1'b0; + + if (reqfifo_rvalid) begin + if (reqfifo_rdata.op == OpRead) begin + d_error = rspfifo_rdata.error | reqfifo_rdata.error; + end else begin + d_error = reqfifo_rdata.error; + end + end else begin + d_error = 1'b0; + end + end + + logic vld_rd_rsp; + assign vld_rd_rsp = d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead); + // If the response data is not valid, we set it to an illegal blanking value which is determined + // by whether the current transaction is an instruction fetch or a regular read operation. + logic [TL_DW-1:0] error_blanking_data; + assign error_blanking_data = (caliptra_prim_mubi_pkg::mubi4_test_true_strict(reqfifo_rdata.instr_type)) ? + DataWhenInstrError : + DataWhenError; + + // Since DataWhenInstrError and DataWhenError can be arbitrary parameters + // we statically calculate the correct integrity values for these parameters here so that + // they do not have to be supplied externally. + logic [TL_DW-1:0] unused_instr, unused_data; + logic [DataIntgWidth-1:0] error_instr_integ, error_data_integ; + tlul_data_integ_enc u_tlul_data_integ_enc_instr ( + .data_i(DataMaxWidth'(DataWhenInstrError)), + .data_intg_o({error_instr_integ, unused_instr}) + ); + tlul_data_integ_enc u_tlul_data_integ_enc_data ( + .data_i(DataMaxWidth'(DataWhenError)), + .data_intg_o({error_data_integ, unused_data}) + ); + + logic [DataIntgWidth-1:0] error_blanking_integ; + assign error_blanking_integ = (caliptra_prim_mubi_pkg::mubi4_test_true_strict(reqfifo_rdata.instr_type)) ? + error_instr_integ : + error_data_integ; + + logic [TL_DW-1:0] d_data; + assign d_data = (vld_rd_rsp & ~d_error) ? rspfifo_rdata.data // valid read + : error_blanking_data; // write or TL-UL error + + // If this a write response with data fields set to 0, we have to set all ECC bits correctly + // since we are using an inverted Hsiao code. + logic [DataIntgWidth-1:0] data_intg; + assign data_intg = (vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : // TL-UL error + (vld_rd_rsp) ? rspfifo_rdata.data_intg : // valid read + caliptra_prim_secded_pkg::SecdedInv3932ZeroEcc; // valid write + + // When an error is seen on an incoming transaction it gets an immediate response without + // performing an SRAM request. It may be the transaction receives a ready the first cycle it is + // seen, but if not we force a ready the following cycle. This avoids factoring the error + // calculation into the outgoing ready preventing a feedthrough path from the incoming tilelink + // signals to the outgoing tilelink signals. + logic missed_err_gnt_d, missed_err_gnt_q; + + // Track whether we've seen an incoming transaction with an error that didn't get a ready + assign missed_err_gnt_d = error_internal & tl_i_int.a_valid & ~tl_o_int.a_ready; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + missed_err_gnt_q <= 1'b0; + end else begin + missed_err_gnt_q <= missed_err_gnt_d; + end + end + + assign tl_o_int = '{ + d_valid : d_valid , + d_opcode : (d_valid && reqfifo_rdata.op != OpRead) ? AccessAck : AccessAckData, + d_param : '0, + d_size : (d_valid) ? reqfifo_rdata.size : '0, + d_source : (d_valid) ? reqfifo_rdata.source : '0, + d_sink : 1'b0, + d_data : d_data, + d_user : '{default: '0, data_intg: data_intg}, + d_error : d_valid && d_error, + a_ready : (gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready & + sramreqaddrfifo_wready + }; + + // a_ready depends on the FIFO full condition and grant from SRAM (or SRAM arbiter) + // assemble response, including read response, write response, and error for unsupported stuff + + // Output to SRAM: + // Generate request only when no internal error occurs. If error occurs, the request should be + // dropped and returned error response to the host. So, error to be pushed to reqfifo. + // In this case, it is assumed the request is granted (may cause ordering issue later?) + assign req_o = tl_i_int.a_valid & reqfifo_wready & ~error_internal; + assign req_type_o = tl_i_int.a_user.instr_type; + assign we_o = tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}); + assign addr_o = (tl_i_int.a_valid) ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0; + + // Support SRAMs wider than the TL-UL word width by mapping the parts of the + // TL-UL address which are more fine-granular than the SRAM width to the + // SRAM write mask. + logic [WoffsetWidth-1:0] woffset; + if (TL_DW != SramDw) begin : gen_wordwidthadapt + assign woffset = tl_i_int.a_address[DataBitWidth-1:caliptra_prim_util_pkg::vbits(TL_DBW)]; + end else begin : gen_no_wordwidthadapt + assign woffset = '0; + end + + // The size of the data/wmask depends on whether passthrough integrity is enabled. + // If passthrough integrity is enabled, the data is concatenated with the integrity passed through + // the user bits. Otherwise, it is the data only. + localparam int DataWidth = EnableDataIntgPt ? TL_DW + DataIntgWidth : TL_DW; + + // Final combined wmask / wdata + logic [WidthMult-1:0][DataWidth-1:0] wmask_combined; + logic [WidthMult-1:0][DataWidth-1:0] wdata_combined; + + // Original tlul portion + logic [WidthMult-1:0][TL_DW-1:0] wmask_int; + logic [WidthMult-1:0][TL_DW-1:0] wdata_int; + + // Integrity portion + logic [WidthMult-1:0][DataIntgWidth-1:0] wmask_intg; + logic [WidthMult-1:0][DataIntgWidth-1:0] wdata_intg; + + always_comb begin + wmask_int = '0; + wdata_int = '0; + + if (tl_i_int.a_valid) begin + for (int i = 0 ; i < TL_DW/8 ; i++) begin + wmask_int[woffset][8*i +: 8] = {8{tl_i_int.a_mask[i]}}; + wdata_int[woffset][8*i +: 8] = (tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[8*i+:8] : '0; + end + end + end + + always_comb begin + wmask_intg = '0; + wdata_intg = '0; + + if (tl_i_int.a_valid) begin + wmask_intg[woffset] = {DataIntgWidth{1'b1}}; + wdata_intg[woffset] = tl_i_int.a_user.data_intg; + end + end + + for (genvar i = 0; i < WidthMult; i++) begin : gen_write_output + if (EnableDataIntgPt) begin : gen_combined_output + assign wmask_combined[i] = {wmask_intg[i], wmask_int[i]}; + assign wdata_combined[i] = {wdata_intg[i], wdata_int[i]}; + end else begin : gen_ft_output + logic unused_w; + assign wmask_combined[i] = wmask_int[i]; + assign wdata_combined[i] = wdata_int[i]; + assign unused_w = |wmask_intg & |wdata_intg; + end + end + + assign wmask_o = wmask_combined; + assign wdata_o = wdata_combined; + + assign reqfifo_wvalid = a_ack ; // Push to FIFO only when granted + assign reqfifo_wdata = '{ + op: (tl_i_int.a_opcode != Get) ? OpWrite : OpRead, // To return AccessAck for opcode error + error: error_internal, + instr_type: tl_i_int.a_user.instr_type, + size: tl_i_int.a_size, + source: tl_i_int.a_source + }; // Store the request only. Doesn't have to store data + assign reqfifo_rready = d_ack ; + + // push together with ReqFIFO, pop upon returning read + assign sramreqfifo_wdata = '{ + mask : tl_i_int.a_mask, + woffset : woffset + }; + assign sramreqfifo_wvalid = sram_ack & ~we_o; + assign sramreqfifo_rready = rspfifo_wvalid; + + assign rspfifo_wvalid = rvalid_i & reqfifo_rvalid; + + assign sramreqaddrfifo_wdata = tl_i_int.a_address[DataBitWidth+:SramBusBankAW]; + + // Make sure only requested bytes are forwarded + logic [WidthMult-1:0][DataWidth-1:0] rdata_reshaped; + logic [DataWidth-1:0] rdata_tlword; + + // This just changes the array format so that the correct word can be selected by indexing. + assign rdata_reshaped = rdata_i; + + if (EnableDataIntgPt) begin : gen_no_rmask + always_comb begin + // If the read mask is set to zero, all read data is zeroed out by the mask. + // We have to set the ECC bits accordingly since we are using an inverted Hsiao code. + rdata_tlword = caliptra_prim_secded_pkg::SecdedInv3932ZeroWord; + // Otherwise, if at least one mask bit is nonzero, we are passing through the integrity. + // In that case we need to feed back the entire word since otherwise the integrity + // will not calculate correctly. + if (|sramreqfifo_rdata.mask) begin + // Select correct word. + if (DataXorAddr) begin : gen_data_xor_addr + // When DataXorAddr is enabled, on a read, the address is XORed with the data fetched from + // the memory in the underlying memory controller (e.g., flash controller). At this point, + // the address is again removed. If the address in the read transaction has been modified, + // e.g., due to a fault, rdata now contains faulty data, which is detected by the + // integrity mechanism. + rdata_tlword = { + rdata_reshaped[sramreqfifo_rdata.woffset][DataWidth-1:TL_DW], + rdata_reshaped[sramreqfifo_rdata.woffset][TL_DW-1:0] ^ + {{(TL_DW-SramBusBankAW){1'b0}}, sramreqaddrfifo_rdata} + }; + end else begin: gen_no_data_xor_addr + rdata_tlword = rdata_reshaped[sramreqfifo_rdata.woffset]; + end + end + end + end else begin : gen_rmask + logic [DataWidth-1:0] rmask; + always_comb begin + rmask = '0; + for (int i = 0 ; i < TL_DW/8 ; i++) begin + rmask[8*i +: 8] = {8{sramreqfifo_rdata.mask[i]}}; + end + end + // Select correct word and mask it. + assign rdata_tlword = rdata_reshaped[sramreqfifo_rdata.woffset] & rmask; + end + + assign rspfifo_wdata = '{ + data : rdata_tlword[TL_DW-1:0], + data_intg : EnableDataIntgPt ? rdata_tlword[DataWidth-1 -: DataIntgWidth] : '0, + error : rerror_i[1] // Only care for Uncorrectable error + }; + assign rspfifo_rready = (reqfifo_rdata.op == OpRead & ~reqfifo_rdata.error) + ? reqfifo_rready : 1'b0 ; + + // This module only cares about uncorrectable errors. + logic unused_rerror; + assign unused_rerror = rerror_i[0]; + + // FIFO instance: REQ, RSP + + // ReqFIFO is to store the Access type to match to the Response data. + // For instance, SRAM accepts the write request but doesn't return the + // acknowledge. In this case, it may be hard to determine when the D + // response for the write data should send out if reads/writes are + // interleaved. So, to make it in-order (even TL-UL allows out-of-order + // responses), storing the request is necessary. And if the read entry + // is write op, it is safe to return the response right away. If it is + // read reqeust, then D response is waiting until read data arrives. + caliptra_prim_fifo_sync #( + .Width (ReqFifoWidth), + .Pass (1'b0), + .Depth (Outstanding), + .Secure (SecFifoPtr) + ) u_reqfifo ( + .clk_i, + .rst_ni, + .clr_i (1'b0), + .wvalid_i(reqfifo_wvalid), + .wready_o(reqfifo_wready), + .wdata_i (reqfifo_wdata), + .rvalid_o(reqfifo_rvalid), + .rready_i(reqfifo_rready), + .rdata_o (reqfifo_rdata), + .full_o (), + .depth_o (), + .err_o (reqfifo_error) + ); + + // sramreqfifo: + // While the ReqFIFO holds the request until it is sent back via TL-UL, the + // sramreqfifo only needs to hold the mask and word offset until the read + // data returns from memory. + caliptra_prim_fifo_sync #( + .Width (SramReqFifoWidth), + .Pass (1'b0), + .Depth (Outstanding), + .Secure (SecFifoPtr) + ) u_sramreqfifo ( + .clk_i, + .rst_ni, + .clr_i (1'b0), + .wvalid_i(sramreqfifo_wvalid), + .wready_o(sramreqfifo_wready), + .wdata_i (sramreqfifo_wdata), + .rvalid_o(), + .rready_i(sramreqfifo_rready), + .rdata_o (sramreqfifo_rdata), + .full_o (), + .depth_o (), + .err_o (sramreqfifo_error) + ); + + // sramreqaddrfifo: + // This fifo holds the address used for undoing the address XOR data infection. + if (DataXorAddr) begin : gen_data_xor_addr_fifo + prim_fifo_sync #( + .Width (SramBusBankAW), + .Pass (1'b0), + .Depth (Outstanding), + .OutputZeroIfEmpty (1) + ) u_sramreqaddrfifo ( + .clk_i, + .rst_ni, + .clr_i (1'b0), + .wvalid_i(sramreqfifo_wvalid), + .wready_o(sramreqaddrfifo_wready), + .wdata_i (sramreqaddrfifo_wdata), + .rvalid_o(), + .rready_i(sramreqfifo_rready), + .rdata_o (sramreqaddrfifo_rdata), + .full_o (), + .depth_o (), + .err_o () + ); + end else begin : gen_no_data_xor_addr_fifo + assign sramreqaddrfifo_wready = 1'b1; + assign sramreqaddrfifo_rdata = '0; + + // Tie-off unused signals + logic unused_sramreqaddrfifo; + assign unused_sramreqaddrfifo = ^{sramreqaddrfifo_wdata, sramreqaddrfifo_rdata}; + end + + // Rationale having #Outstanding depth in response FIFO. + // In normal case, if the host or the crossbar accepts the response data, + // response FIFO isn't needed. But if in any case it has a chance to be + // back pressured, the response FIFO should store the returned data not to + // lose the data from the SRAM interface. Remember, SRAM interface doesn't + // have back-pressure signal such as read_ready. + caliptra_prim_fifo_sync #( + .Width (RspFifoWidth), + .Pass (1'b1), + .Depth (Outstanding), + .Secure (SecFifoPtr) + ) u_rspfifo ( + .clk_i, + .rst_ni, + .clr_i (1'b0), + .wvalid_i(rspfifo_wvalid), + .wready_o(rspfifo_wready), + .wdata_i (rspfifo_wdata), + .rvalid_o(rspfifo_rvalid), + .rready_i(rspfifo_rready), + .rdata_o (rspfifo_rdata), + .full_o (), + .depth_o (), + .err_o (rsp_fifo_error) + ); + + // below assertion fails when SRAM rvalid is asserted even though ReqFifo is empty + `CALIPTRA_ASSERT(rvalidHighReqFifoEmpty, rvalid_i |-> reqfifo_rvalid) + + // below assertion fails when outstanding value is too small (SRAM rvalid is asserted + // even though the RspFifo is full) + `CALIPTRA_ASSERT(rvalidHighWhenRspFifoFull, rvalid_i |-> rspfifo_wready) + + // If both ErrOnWrite and ErrOnRead are set, this block is useless + `CALIPTRA_ASSERT_INIT(adapterNoReadOrWrite, (ErrOnWrite & ErrOnRead) == 0) + + `CALIPTRA_ASSERT_INIT(SramDwHasByteGranularity_A, SramDw % 8 == 0) + `CALIPTRA_ASSERT_INIT(SramDwIsMultipleOfTlulWidth_A, SramDw % TL_DW == 0) + + // These parameter options cannot both be true at the same time + `CALIPTRA_ASSERT_INIT(DataIntgOptions_A, ~(EnableDataIntgGen & EnableDataIntgPt)) + + // make sure outputs are defined + `CALIPTRA_ASSERT_KNOWN(TlOutKnown_A, tl_o.d_valid) + `CALIPTRA_ASSERT_KNOWN_IF(TlOutPayloadKnown_A, tl_o, tl_o.d_valid) + `CALIPTRA_ASSERT_KNOWN(ReqOutKnown_A, req_o ) + `CALIPTRA_ASSERT_KNOWN(WeOutKnown_A, we_o ) + `CALIPTRA_ASSERT_KNOWN(AddrOutKnown_A, addr_o ) + `CALIPTRA_ASSERT_KNOWN(WdataOutKnown_A, wdata_o) + `CALIPTRA_ASSERT_KNOWN(WmaskOutKnown_A, wmask_o) + +endmodule diff --git a/src/tlul/rtl/tlul_assert.sv b/src/tlul/rtl/tlul_assert.sv new file mode 100644 index 0000000..6fc79b2 --- /dev/null +++ b/src/tlul/rtl/tlul_assert.sv @@ -0,0 +1,437 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Protocol checker for TL-UL ports using assertions. Supports interface-widths +// up to 64bit. + +`include "caliptra_prim_assert.sv" + +module tlul_assert #( + parameter EndpointType = "Device" // can be either "Host" or "Device" +) ( + input clk_i, + input rst_ni, + + // tile link ports + input tlul_pkg::tl_h2d_t h2d, + input tlul_pkg::tl_d2h_t d2h +); + +`ifndef VERILATOR +`ifndef SYNTHESIS + +`ifdef UVM + import uvm_pkg::*; +`endif + import tlul_pkg::*; + //import top_pkg::*; + + ////////////////////////////////// + // check requests and responses // + ////////////////////////////////// + + // There are up to 2**TL_AIW possible source-IDs. Below array "pend_req" has one entry + // for each source-ID. Each entry has the following fields: + // - pend : is set to 1 to indicate up to 1 pending request for the source ID + // - opcode : "Get" requires "AccessAckData" response, "Put*" require "AccessAck" + // - size : d_size of response must match a_size of request + // - mask : is used to allow X for bytes whose mask bit is 0 + typedef struct packed { + bit pend; // set to 1 to indicate a pending request + tl_a_op_e opcode; + logic [TL_SZW-1:0] size; + logic [TL_DBW-1:0] mask; + } pend_req_t; + + pend_req_t [2**TL_AIW-1:0] pend_req; + + // To test TLUL error cases in UVM tests, pass the tlul_assert_en argument in the UVM config db, + // which will cause disable_sva to be set to 1. This disables some assertions about the + // well-formedness of the TL input. + bit disable_sva; + + // We have some assertions below about the behaviour of d2h.d_error. These aren't actually true + // for the xbar, since it doesn't return d_error for protocol errors. Disable these checks by + // passing tlul_d_error_assert_en in the UVM config db, which causes disable_d_error_sva to be set + // to 1. + bit disable_d_error_sva; + + logic [7:0] a_mask, d_mask; + logic [63:0] a_data, d_data; + assign a_mask = 8'(h2d.a_mask); + assign a_data = 64'(h2d.a_data); + assign d_mask = 8'(pend_req[d2h.d_source].mask); + assign d_data = 64'(d2h.d_data); + + //////////////////////////////////// + // keep track of pending requests // + //////////////////////////////////// + + // use negedge clk to avoid possible race conditions + always_ff @(negedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + pend_req <= '0; + end else begin + if (h2d.a_valid) begin + // store each request in pend_req array (we use blocking statements below so + // that we can handle the case where request and response for the same + // source-ID happen in the same cycle) + if (d2h.a_ready) begin + pend_req[h2d.a_source].pend <= 1; + pend_req[h2d.a_source].opcode <= h2d.a_opcode; + pend_req[h2d.a_source].size <= h2d.a_size; + pend_req[h2d.a_source].mask <= h2d.a_mask; + end + end // h2d.a_valid + + if (d2h.d_valid) begin + // update pend_req array + if (h2d.d_ready) begin + pend_req[d2h.d_source].pend <= 0; + end + end //d2h.d_valid + end + end + + ///////////////////////////////////////// + // define sequences for request checks // + ///////////////////////////////////////// + + sequence h2d_pre_S; + h2d.a_valid; + endsequence + + // a_opcode: only 3 opcodes are legal for requests + sequence legalAOpcode_S; + (h2d.a_opcode === PutFullData) || + (h2d.a_opcode === Get) || + (h2d.a_opcode === PutPartialData); + endsequence + + // a_param is reserved + sequence legalAParam_S; + h2d.a_param === '0; + endsequence + + // a_size: Size shouldn't be greater than the bus width in TL-UL (not in TL-UH) + // This assertion can be covered by below + // (a_size must less than or equal to ones of a_mask) + + // a_size: 2**a_size must greater than or equal to $countones(a_mask) for PutPartial and Get + sequence sizeGTEMask_S; + (h2d.a_opcode == PutFullData) || ((1 << h2d.a_size) >= $countones(h2d.a_mask)); + endsequence + + // a_size: 2**a_size must equal to $countones(a_mask) for PutFull + sequence sizeMatchesMask_S; + (h2d.a_opcode inside {PutPartialData, Get}) || + ((1 << h2d.a_size) === $countones(h2d.a_mask)); + endsequence + + // a_source: there should be no more than one pending request per each source ID + sequence pendingReqPerSrc_S; + pend_req[h2d.a_source].pend == 0; + endsequence + + // a_address must be aligned to a_size: a_address & ((1 << a_size) - 1) == 0 + sequence addrSizeAligned_S; + (h2d.a_address & ((1 << h2d.a_size)-1)) == '0; + endsequence + + // a_mask must be contiguous for Get and PutFullData requests + // the spec talks about "naturally aligned". Does this mean that bit [0] of + // mask is always 1? If that's true, then below code could be much simpler. + // However, the spec shows a timing diagram where bit 0 of mask is 0. + sequence contigMask_pre_S; + h2d.a_opcode != PutPartialData; + endsequence + + sequence contigMask_S; + $countones(h2d.a_mask ^ {h2d.a_mask[$bits(h2d.a_mask)-2:0], 1'b0}) <= 2; + endsequence + + // a_data must be known for opcode == Put*(depending on mask bits) + sequence aDataKnown_pre_S; + (h2d.a_opcode != Get); + endsequence + + sequence aDataKnown_S; + // no check if this lane mask is inactive + ((!a_mask[0]) || (a_mask[0] && !$isunknown(a_data[8*0 +: 8]))) && + ((!a_mask[1]) || (a_mask[1] && !$isunknown(a_data[8*1 +: 8]))) && + ((!a_mask[2]) || (a_mask[2] && !$isunknown(a_data[8*2 +: 8]))) && + ((!a_mask[3]) || (a_mask[3] && !$isunknown(a_data[8*3 +: 8]))) && + ((!a_mask[4]) || (a_mask[4] && !$isunknown(a_data[8*4 +: 8]))) && + ((!a_mask[5]) || (a_mask[5] && !$isunknown(a_data[8*5 +: 8]))) && + ((!a_mask[6]) || (a_mask[6] && !$isunknown(a_data[8*6 +: 8]))) && + ((!a_mask[7]) || (a_mask[7] && !$isunknown(a_data[8*7 +: 8]))); + endsequence + + ///////////////////////////////////////// + // define sequences for request checks // + ///////////////////////////////////////// + + sequence d2h_pre_S; + d2h.d_valid; + endsequence + + // d_opcode: if request was Get, then response must be AccessAckData + sequence respOpcode_S; + d2h.d_opcode === ((pend_req[d2h.d_source].opcode == Get) ? AccessAckData : AccessAck); + endsequence + + // d_param is reserved + sequence legalDParam_S; + d2h.d_param === '0; + endsequence + + // d_size must equal the a_size of the corresponding request + sequence respSzEqReqSz_S; + d2h.d_size === pend_req[d2h.d_source].size; + endsequence + + // d_source: each response should have a pending request using same source ID + sequence respMustHaveReq_S; + pend_req[d2h.d_source].pend; + endsequence + +// d_data must be known for AccessAckData (depending on mask bits) + sequence dDataKnown_pre_S; + d2h.d_opcode == AccessAckData; + endsequence + + sequence dDataKnown_S; + // no check if this lane mask is inactive + ((!d_mask[0]) || (d_mask[0] && !$isunknown(d_data[8*0 +: 8]))) && + ((!d_mask[1]) || (d_mask[1] && !$isunknown(d_data[8*1 +: 8]))) && + ((!d_mask[2]) || (d_mask[2] && !$isunknown(d_data[8*2 +: 8]))) && + ((!d_mask[3]) || (d_mask[3] && !$isunknown(d_data[8*3 +: 8]))) && + ((!d_mask[4]) || (d_mask[4] && !$isunknown(d_data[8*4 +: 8]))) && + ((!d_mask[5]) || (d_mask[5] && !$isunknown(d_data[8*5 +: 8]))) && + ((!d_mask[6]) || (d_mask[6] && !$isunknown(d_data[8*6 +: 8]))) && + ((!d_mask[7]) || (d_mask[7] && !$isunknown(d_data[8*7 +: 8]))); + endsequence + + ///////////////////////////////////////// + // define sequences for d_error checks // + ///////////////////////////////////////// + + sequence d_error_pre_S; + h2d.a_valid && d2h.a_ready; + endsequence + + sequence legalAOpcodeErr_S; + !(h2d.a_opcode inside {PutFullData, Get, PutPartialData}); + endsequence + + sequence sizeGTEMaskErr_S; + (1 << h2d.a_size) < $countones(h2d.a_mask); + endsequence + + sequence sizeMatchesMaskErr_S; + (h2d.a_opcode == PutFullData) && ((1 << h2d.a_size) != $countones(h2d.a_mask)); + endsequence + + sequence addrSizeAlignedErr_S; + (h2d.a_address & ((1 << h2d.a_size)-1)) != '0; + endsequence + + /////////////////////////////////// + // assemble properties and check // + /////////////////////////////////// + + // note: use negedge clk to avoid possible race conditions + // in this case all signals coming from the device side have an assumed property + if (EndpointType == "Host") begin : gen_host + // h2d + `CALIPTRA_ASSERT(legalAOpcode_A, h2d_pre_S |-> legalAOpcode_S, !clk_i, !rst_ni || disable_sva) + `CALIPTRA_ASSERT(legalAParam_A, h2d_pre_S |-> legalAParam_S, !clk_i, !rst_ni) + `CALIPTRA_ASSERT(sizeGTEMask_A, h2d_pre_S |-> sizeGTEMask_S, !clk_i, !rst_ni || disable_sva) + `CALIPTRA_ASSERT(sizeMatchesMask_A, h2d_pre_S |-> sizeMatchesMask_S, !clk_i, !rst_ni || disable_sva) + `CALIPTRA_ASSERT(pendingReqPerSrc_A, h2d_pre_S |-> pendingReqPerSrc_S, !clk_i, !rst_ni) + `CALIPTRA_ASSERT(addrSizeAligned_A, h2d_pre_S |-> addrSizeAligned_S, !clk_i, !rst_ni || disable_sva) + `CALIPTRA_ASSERT(contigMask_A, h2d_pre_S and contigMask_pre_S |-> contigMask_S, + !clk_i, !rst_ni || disable_sva) + `CALIPTRA_ASSERT(aDataKnown_A, h2d_pre_S and aDataKnown_pre_S |-> aDataKnown_S, !clk_i, !rst_ni) + // d2h + `CALIPTRA_ASSUME(respOpcode_M, d2h_pre_S |-> respOpcode_S, !clk_i, !rst_ni) + `CALIPTRA_ASSUME(legalDParam_M, d2h_pre_S |-> legalDParam_S, !clk_i, !rst_ni) + `CALIPTRA_ASSUME(respSzEqReqSz_M, d2h_pre_S |-> respSzEqReqSz_S, !clk_i, !rst_ni) + `CALIPTRA_ASSUME(respMustHaveReq_M, d2h_pre_S |-> respMustHaveReq_S, !clk_i, !rst_ni) + `CALIPTRA_ASSUME(dDataKnown_M, d2h_pre_S and dDataKnown_pre_S |-> dDataKnown_S, + !clk_i, !rst_ni || disable_sva) + // in this case all signals coming from the host side have an assumed property + end else if (EndpointType == "Device") begin : gen_device + // h2d + `CALIPTRA_ASSUME(legalAParam_M, h2d_pre_S |-> legalAParam_S, !clk_i, !rst_ni) + `CALIPTRA_ASSUME(pendingReqPerSrc_M, h2d_pre_S |-> pendingReqPerSrc_S, !clk_i, !rst_ni) + `CALIPTRA_ASSUME(aDataKnown_M, h2d_pre_S and aDataKnown_pre_S |-> aDataKnown_S, !clk_i, !rst_ni) + `CALIPTRA_ASSUME(contigMask_M, h2d_pre_S and contigMask_pre_S |-> contigMask_S, + !clk_i, !rst_ni || disable_sva) + // d2h + `CALIPTRA_ASSERT(respOpcode_A, d2h_pre_S |-> respOpcode_S, !clk_i, !rst_ni) + `CALIPTRA_ASSERT(legalDParam_A, d2h_pre_S |-> legalDParam_S, !clk_i, !rst_ni) + `CALIPTRA_ASSERT(respSzEqReqSz_A, d2h_pre_S |-> respSzEqReqSz_S, !clk_i, !rst_ni) + `CALIPTRA_ASSERT(respMustHaveReq_A, d2h_pre_S |-> respMustHaveReq_S, !clk_i, !rst_ni) + `CALIPTRA_ASSERT(dDataKnown_A, d2h_pre_S and dDataKnown_pre_S |-> dDataKnown_S, + !clk_i, !rst_ni || disable_sva) + // d2h error cases + `CALIPTRA_ASSERT(legalAOpcodeErr_A, d_error_pre_S and legalAOpcodeErr_S |=> + s_eventually (d2h.d_valid && d2h.d_error), , !rst_ni || disable_d_error_sva) + `CALIPTRA_ASSERT(sizeGTEMaskErr_A, d_error_pre_S and sizeGTEMaskErr_S |=> + s_eventually (d2h.d_valid && d2h.d_error), , !rst_ni || disable_d_error_sva) + `CALIPTRA_ASSERT(sizeMatchesMaskErr_A, d_error_pre_S and sizeMatchesMaskErr_S |=> + s_eventually (d2h.d_valid && d2h.d_error), , !rst_ni || disable_d_error_sva) + `CALIPTRA_ASSERT(addrSizeAlignedErr_A, d_error_pre_S and addrSizeAlignedErr_S |=> + s_eventually (d2h.d_valid && d2h.d_error), , !rst_ni || disable_d_error_sva) + end else begin : gen_unknown + initial begin : p_unknonw + `CALIPTRA_ASSERT_I(unknownConfig_A, 0 == 1) + end + end + + initial begin : p_dbw + // widths up to 64bit / 8 Byte are supported + `CALIPTRA_ASSERT_I(TlDbw_A, TL_DBW <= 8) + end + + // make sure all "pending" bits are 0 at the end of the sim + for (genvar ii = 0; ii < 2**TL_AIW; ii++) begin : gen_assert_final + `CALIPTRA_ASSERT_FINAL(noOutstandingReqsAtEndOfSim_A, (pend_req[ii].pend == 0)) + end + + //////////////////////////////////// + // additional checks for X values // + //////////////////////////////////// + + // a_* should be known when a_valid == 1 (a_opcode and a_param are already covered above) + // This also covers ASSERT_KNOWN of a_valid + `CALIPTRA_ASSERT_KNOWN_IF(aKnown_A, {h2d.a_size, h2d.a_source, h2d.a_address, h2d.a_mask, h2d.a_user}, + h2d.a_valid) + + // d_* should be known when d_valid == 1 (d_opcode, d_param, d_size already covered above) + // This also covers ASSERT_KNOWN of d_valid + `CALIPTRA_ASSERT_KNOWN_IF(dKnown_A, {d2h.d_source, d2h.d_sink, d2h.d_error, d2h.d_user}, d2h.d_valid) + + // make sure ready is not X after reset + `CALIPTRA_ASSERT_KNOWN(aReadyKnown_A, d2h.a_ready) + `CALIPTRA_ASSERT_KNOWN(dReadyKnown_A, h2d.d_ready) + + //////////////////////////////////// + // SVA coverage // + //////////////////////////////////// + `define TLUL_COVER(SEQ) `CALIPTRA_COVER(``SEQ``_C, ``SEQ``_S, !clk_i, !rst_ni || disable_sva) + + // host sends back2back requests + sequence b2bReq_S; + h2d.a_valid && d2h.a_ready ##1 h2d.a_valid; + endsequence + + // device sends back2back responses + sequence b2bRsp_S; + d2h.d_valid && h2d.d_ready ##1 d2h.d_valid; + endsequence + + // host sends back2back requests with same address + // UVM RAL can't issue this scenario, add this cover to make sure it's tested in some other seq + sequence b2bReqWithSameAddr_S; + bit [TL_AW-1:0] pre_addr; + (h2d.a_valid && d2h.a_ready, pre_addr = h2d.a_address) + ##1 h2d.a_valid && pre_addr == h2d.a_address; + endsequence + + // a_valid is dropped without a_ready + sequence aValidNotAccepted_S; + h2d.a_valid && !d2h.a_ready ##1 !h2d.a_valid; + endsequence + + // d_valid is dropped without a_ready + sequence dValidNotAccepted_S; + d2h.d_valid && !h2d.d_ready ##1 !d2h.d_valid; + endsequence + + // host uses same source for back2back items + sequence b2bSameSource_S; + bit [TL_AIW-1:0] pre_source; + (h2d.a_valid && d2h.a_ready, pre_source = h2d.a_source) ##1 h2d.a_valid[->1] + ##0 pre_source == h2d.a_source; + endsequence + + // a channal content is changed without being accepted + `define TLUL_A_CHAN_CONTENT_CHANGED_WO_ACCEPTED(NAME) \ + sequence a_``NAME``ChangedNotAccepted_S; \ + int pre; \ + (h2d.a_valid && !d2h.a_ready, pre = h2d.a_``NAME``) ##1 h2d.a_valid[->1] \ + ##0 pre != h2d.a_``NAME``; \ + endsequence \ + `TLUL_COVER(a_``NAME``ChangedNotAccepted) + + // d channal content is changed without being accepted + `define TLUL_D_CHAN_CONTENT_CHANGED_WO_ACCEPTED(NAME) \ + sequence d_``NAME``ChangedNotAccepted_S; \ + int pre; \ + (d2h.d_valid && !h2d.d_ready, pre = d2h.d_``NAME``) ##1 d2h.d_valid[->1] \ + ##0 pre != d2h.d_``NAME``; \ + endsequence \ + `TLUL_COVER(d_``NAME``ChangedNotAccepted) + + if (EndpointType == "Host") begin : gen_host_cov // DUT is host + `TLUL_COVER(b2bRsp) + `TLUL_COVER(dValidNotAccepted) + `TLUL_D_CHAN_CONTENT_CHANGED_WO_ACCEPTED(data) + `TLUL_D_CHAN_CONTENT_CHANGED_WO_ACCEPTED(opcode) + `TLUL_D_CHAN_CONTENT_CHANGED_WO_ACCEPTED(size) + `TLUL_D_CHAN_CONTENT_CHANGED_WO_ACCEPTED(source) + `TLUL_D_CHAN_CONTENT_CHANGED_WO_ACCEPTED(sink) + `TLUL_D_CHAN_CONTENT_CHANGED_WO_ACCEPTED(error) + end else if (EndpointType == "Device") begin : gen_device_cov // DUT is device + `TLUL_COVER(b2bReq) + `TLUL_COVER(b2bReqWithSameAddr) + `TLUL_COVER(aValidNotAccepted) + `TLUL_COVER(b2bSameSource) + `TLUL_A_CHAN_CONTENT_CHANGED_WO_ACCEPTED(address) + `TLUL_A_CHAN_CONTENT_CHANGED_WO_ACCEPTED(data) + `TLUL_A_CHAN_CONTENT_CHANGED_WO_ACCEPTED(opcode) + `TLUL_A_CHAN_CONTENT_CHANGED_WO_ACCEPTED(size) + `TLUL_A_CHAN_CONTENT_CHANGED_WO_ACCEPTED(source) + `TLUL_A_CHAN_CONTENT_CHANGED_WO_ACCEPTED(mask) + end else begin : gen_unknown_cov + initial begin : p_unknonw_cov + `CALIPTRA_ASSERT_I(unknownConfig_A, 0 == 1) + end + end + + `ifdef UVM + initial forever begin + bit tlul_assert_en; + uvm_config_db#(bit)::wait_modified(null, "%m", "tlul_assert_en"); + if (!uvm_config_db#(bit)::get(null, "%m", "tlul_assert_en", tlul_assert_en)) begin + `uvm_fatal("tlul_assert", "Can't find tlul_assert_en") + end + disable_sva = !tlul_assert_en; + end + initial forever begin + bit tlul_assert_en; + uvm_config_db#(bit)::wait_modified(null, "%m", "tlul_d_error_assert_en"); + if (!uvm_config_db#(bit)::get(null, "%m", "tlul_d_error_assert_en", tlul_assert_en)) begin + `uvm_fatal("tlul_assert", "Can't find tlul_d_error_assert_en") + end + disable_d_error_sva = !tlul_assert_en; + end + `else + // Set default values for the disable_*_sva signals (not disabling the assertions) + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + disable_sva <= 0; + disable_d_error_sva <= 0; + end + end + `endif + + `undef TLUL_COVER + `undef TLUL_A_CHAN_CONTENT_CHANGED_WO_ACCEPTED + `undef TLUL_D_CHAN_CONTENT_CHANGED_WO_ACCEPTED +`endif +`endif +endmodule : tlul_assert diff --git a/src/tlul/rtl/tlul_assert_multiple.sv b/src/tlul/rtl/tlul_assert_multiple.sv new file mode 100644 index 0000000..61a8e53 --- /dev/null +++ b/src/tlul/rtl/tlul_assert_multiple.sv @@ -0,0 +1,31 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Protocol checker for multiple TL-UL ports + +module tlul_assert_multiple #( + parameter int unsigned N = 2, + parameter EndpointType = "Device" // can be "Device" or "Host" +) ( + input clk_i, + input rst_ni, + + // tile link ports + input tlul_pkg::tl_h2d_t h2d [N], + input tlul_pkg::tl_d2h_t d2h [N] +); + + // instantiate N tlul_assert modules + for (genvar ii = 0; ii < N; ii++) begin : gen_assert + tlul_assert #( + .EndpointType(EndpointType) + ) tlul_assert ( + .clk_i, + .rst_ni, + // TL-UL ports + .h2d (h2d[ii]), + .d2h (d2h[ii]) + ); + end +endmodule diff --git a/src/tlul/rtl/tlul_caliptra_ss_lc_gate.sv b/src/tlul/rtl/tlul_caliptra_ss_lc_gate.sv new file mode 100644 index 0000000..f11bf84 --- /dev/null +++ b/src/tlul/rtl/tlul_caliptra_ss_lc_gate.sv @@ -0,0 +1,264 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Life cycle gating module for TL-UL protocol. +// Transactions are passed through when lc_en_i == ON. +// In all other cases (lc_en_i != ON) incoming transactions return a bus error. +// +// Note that the lc_en_i should be synchronized and buffered outside of this module using +// an instance of prim_caliptra_ss_lc_sync. + +module tlul_caliptra_ss_lc_gate + import tlul_pkg::*; + import caliptra_ss_lc_ctrl_pkg::*; +#( + // Number of LC gating muxes in each direction. + // It is recommended to set this parameter to 2, which results + // in a total of 4 gating muxes. + parameter int NumGatesPerDirection = 2, + // By default we return a TL-UL bus error response if the bus is gated. However, in some special + // cases we need to be able to return valid, all-zero responses instead (e.g. for the RV_DM). In + // those cases, ReturnBlankResp can be set to 1. + parameter bit ReturnBlankResp = 0, + // The maximum number of outstanding TL-UL requests at the output + parameter int unsigned Outstanding = 3 +) ( + input clk_i, + input rst_ni, + + // To host + input tl_h2d_t tl_h2d_i, + output tl_d2h_t tl_d2h_o, + + // To device + output tl_h2d_t tl_h2d_o, + input tl_d2h_t tl_d2h_i, + + // Flush control signaling + input flush_req_i, + output logic flush_ack_o, + + // Indicates whether there are pending responses on the device side. + output logic resp_pending_o, + + // LC control signal + input caliptra_ss_lc_tx_t lc_en_i, + output logic err_o +); + + ////////////////// + // Access Gates // + ////////////////// + + caliptra_ss_lc_tx_t err_en; + caliptra_ss_lc_tx_t [NumGatesPerDirection-1:0] err_en_buf; + + caliptra_prim_lc_sync #( + .NumCopies(NumGatesPerDirection), + .AsyncOn(0) + ) u_err_en_sync ( + .clk_i, + .rst_ni, + .lc_en_i(err_en), + .lc_en_o(err_en_buf) + ); + + tl_h2d_t tl_h2d_int [NumGatesPerDirection+1]; + tl_d2h_t tl_d2h_int [NumGatesPerDirection+1]; + for (genvar k = 0; k < NumGatesPerDirection; k++) begin : gen_caliptra_ss_lc_gating_muxes + // H -> D path. + caliptra_prim_blanker #( + .Width($bits(tl_h2d_t)) + ) u_prim_blanker_h2d ( + .in_i(tl_h2d_int[k]), + .en_i(caliptra_ss_lc_tx_test_false_strict(err_en_buf[k])), + .out_o(tl_h2d_int[k+1]) + ); + + // D -> H path. + caliptra_prim_blanker #( + .Width($bits(tl_d2h_t)) + ) u_prim_blanker_d2h ( + .in_i(tl_d2h_int[k+1]), + .en_i(caliptra_ss_lc_tx_test_false_strict(err_en_buf[k])), + .out_o(tl_d2h_int[k]) + ); + end + + // Assign signals on the device side. + assign tl_h2d_o = tl_h2d_int[NumGatesPerDirection]; + assign tl_d2h_int[NumGatesPerDirection] = tl_d2h_i; + + /////////////////////////// + // Host Side Interposing // + /////////////////////////// + + // Encoding generated with: + // $ ./util/design/sparse-fsm-encode.py -d 5 -m 4 -n 8 \ + // -s 3379253306 --language=sv + // + // Hamming distance histogram: + // + // 0: -- + // 1: -- + // 2: -- + // 3: -- + // 4: -- + // 5: |||||||||||||||||||| (66.67%) + // 6: |||||||||| (33.33%) + // 7: -- + // 8: -- + // + // Minimum Hamming distance: 5 + // Maximum Hamming distance: 6 + // Minimum Hamming weight: 3 + // Maximum Hamming weight: 5 + // + // Encoding generated with: + // $ ./util/design/sparse-fsm-encode.py -d 5 -m 5 -n 9 \ + // -s 686407169 --language=sv + // + // Hamming distance histogram: + // + // 0: -- + // 1: -- + // 2: -- + // 3: -- + // 4: -- + // 5: |||||||||||||||||||| (60.00%) + // 6: ||||||||||||| (40.00%) + // 7: -- + // 8: -- + // 9: -- + // + // Minimum Hamming distance: 5 + // Maximum Hamming distance: 6 + // Minimum Hamming weight: 3 + // Maximum Hamming weight: 6 + // + localparam int StateWidth = 9; + typedef enum logic [StateWidth-1:0] { + StActive = 9'b100100001, + StOutstanding = 9'b011100111, + StFlush = 9'b001001100, + StError = 9'b010111010, + StErrorOutstanding = 9'b100010110 + } state_e; + + state_e state_d, state_q; + `CALIPTRA_PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, StError) + + logic [caliptra_prim_util_pkg::vbits(Outstanding+1)-1:0] outstanding_txn; + logic a_ack; + logic d_ack; + assign a_ack = tl_h2d_i.a_valid & tl_d2h_o.a_ready; + assign d_ack = tl_h2d_i.d_ready & tl_d2h_o.d_valid; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + outstanding_txn <= '0; + end else if (a_ack && !d_ack) begin + outstanding_txn <= outstanding_txn + 1'b1; + end else if (d_ack && !a_ack) begin + outstanding_txn <= outstanding_txn - 1'b1; + end + end + + logic block_cmd; + always_comb begin + block_cmd = '0; + state_d = state_q; + err_en = Off; + err_o = '0; + flush_ack_o = '0; + resp_pending_o = 1'b0; + + unique case (state_q) + StActive: begin + if (caliptra_ss_lc_tx_test_false_loose(lc_en_i) || flush_req_i) begin + state_d = StOutstanding; + end + if (outstanding_txn != '0) begin + resp_pending_o = 1'b1; + end + end + + StOutstanding: begin + block_cmd = 1'b1; + if (outstanding_txn == '0) begin + state_d = caliptra_ss_lc_tx_test_false_loose(lc_en_i) ? StError : StFlush; + end else begin + resp_pending_o = 1'b1; + end + end + + StFlush: begin + block_cmd = 1'b1; + flush_ack_o = 1'b1; + if (caliptra_ss_lc_tx_test_false_loose(lc_en_i)) begin + state_d = StError; + end else if (!flush_req_i) begin + state_d = StActive; + end + end + + StError: begin + err_en = On; + if (caliptra_ss_lc_tx_test_true_strict(lc_en_i)) begin + state_d = StErrorOutstanding; + end + end + + StErrorOutstanding: begin + err_en = On; + block_cmd = 1'b1; + if (outstanding_txn == '0) begin + state_d = StActive; + end + end + + default: begin + err_o = 1'b1; + err_en = On; + end + + endcase // unique case (state_q) + end + + + // At the host side, we interpose the ready / valid signals so that we can return a bus error + // in case the lc signal is not set to ON. Note that this logic does not have to be duplicated + // since erroring back is considered a convenience feature so that the bus does not lock up. + tl_h2d_t tl_h2d_error; + tl_d2h_t tl_d2h_error; + always_comb begin + tl_h2d_int[0] = tl_h2d_i; + tl_d2h_o = tl_d2h_int[0]; + tl_h2d_error = '0; + + if (caliptra_ss_lc_tx_test_true_loose(err_en)) begin + tl_h2d_error = tl_h2d_i; + tl_d2h_o = tl_d2h_error; + end + + if (block_cmd) begin + tl_d2h_o.a_ready = 1'b0; + tl_h2d_int[0].a_valid = 1'b0; + tl_h2d_error.a_valid = 1'b0; + end + end + + tlul_err_resp #( + .ReturnBlankResp(ReturnBlankResp) + ) u_tlul_err_resp ( + .clk_i, + .rst_ni, + .tl_h_i(tl_h2d_error), + .tl_h_o(tl_d2h_error) + ); + + // Add assertion + `CALIPTRA_ASSERT(OutStandingOvfl_A, &outstanding_txn |-> ~a_ack) + +endmodule : tlul_caliptra_ss_lc_gate diff --git a/src/tlul/rtl/tlul_cmd_intg_chk.sv b/src/tlul/rtl/tlul_cmd_intg_chk.sv new file mode 100644 index 0000000..99e1e19 --- /dev/null +++ b/src/tlul/rtl/tlul_cmd_intg_chk.sv @@ -0,0 +1,53 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +`include "caliptra_prim_assert.sv" + +/** + * Tile-Link UL command integrity check + */ + +module tlul_cmd_intg_chk import tlul_pkg::*; ( + // TL-UL interface + input tl_h2d_t tl_i, + + // error output + output logic err_o +); + + logic [1:0] err; + logic data_err; + tl_h2d_cmd_intg_t cmd; + assign cmd = extract_h2d_cmd_intg(tl_i); + + caliptra_prim_secded_inv_64_57_dec u_chk ( + .data_i({tl_i.a_user.cmd_intg, H2DCmdMaxWidth'(cmd)}), + .data_o(), + .syndrome_o(), + .err_o(err) + ); + + tlul_data_integ_dec u_tlul_data_integ_dec ( + .data_intg_i({tl_i.a_user.data_intg, DataMaxWidth'(tl_i.a_data)}), + .data_err_o(data_err) + ); + + // error output is transactional, it is up to the instantiating module + // to determine if a permanent latch is feasible + // [LOWRISC] err and data_err is unknown when a_valid is low, so we can't cover + // the condition coverage - (|err | (|data_err)) == 0/1, when a_valid = 0, which is + // fine as driving unknown is better. `err_o` is used as a condition in other places, + // which needs to be covered with 0 and 1, so it's OK to disable the entire coverage. + //VCS coverage off + // pragma coverage off + assign err_o = tl_i.a_valid & (|err | (|data_err)); + //VCS coverage on + // pragma coverage on + + logic unused_tl; + assign unused_tl = |tl_i; + + `CALIPTRA_ASSERT_INIT(PayLoadWidthCheck, $bits(tl_h2d_cmd_intg_t) <= H2DCmdMaxWidth) + +endmodule // tlul_payload_chk diff --git a/src/tlul/rtl/tlul_cmd_intg_gen.sv b/src/tlul/rtl/tlul_cmd_intg_gen.sv new file mode 100644 index 0000000..b38b196 --- /dev/null +++ b/src/tlul/rtl/tlul_cmd_intg_gen.sv @@ -0,0 +1,58 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +`include "caliptra_prim_assert.sv" + +/** + * Tile-Link UL command integrity generator + */ + +module tlul_cmd_intg_gen import tlul_pkg::*; #( + parameter bit EnableDataIntgGen = 1'b1 +) ( + // TL-UL interface + input tl_h2d_t tl_i, + output tl_h2d_t tl_o +); + + tl_h2d_cmd_intg_t cmd; + assign cmd = extract_h2d_cmd_intg(tl_i); + logic [H2DCmdMaxWidth-1:0] unused_cmd_payload; + + logic [H2DCmdIntgWidth-1:0] cmd_intg; + caliptra_prim_secded_inv_64_57_enc u_cmd_gen ( + .data_i(H2DCmdMaxWidth'(cmd)), + .data_o({cmd_intg, unused_cmd_payload}) + ); + + logic [TL_DW-1:0] data_final; + logic [DataIntgWidth-1:0] data_intg; + + if (EnableDataIntgGen) begin : gen_data_intg + assign data_final = tl_i.a_data; + + logic [DataMaxWidth-1:0] unused_data; + caliptra_prim_secded_inv_39_32_enc u_data_gen ( + .data_i(DataMaxWidth'(data_final)), + .data_o({data_intg, unused_data}) + ); + end else begin : gen_passthrough_data_intg + assign data_final = tl_i.a_data; + assign data_intg = tl_i.a_user.data_intg; + end + + always_comb begin + tl_o = tl_i; + tl_o.a_data = data_final; + tl_o.a_user.cmd_intg = cmd_intg; + tl_o.a_user.data_intg = data_intg; + end + + + logic unused_tl; + assign unused_tl = ^tl_i; + + `CALIPTRA_ASSERT_INIT(PayMaxWidthCheck_A, $bits(tl_h2d_cmd_intg_t) <= H2DCmdMaxWidth) + +endmodule : tlul_cmd_intg_gen diff --git a/src/tlul/rtl/tlul_data_integ_dec.sv b/src/tlul/rtl/tlul_data_integ_dec.sv new file mode 100644 index 0000000..bd2f13b --- /dev/null +++ b/src/tlul/rtl/tlul_data_integ_dec.sv @@ -0,0 +1,27 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +`include "caliptra_prim_assert.sv" + +/** + * Data integrity decoder for bus integrity scheme + */ + +module tlul_data_integ_dec import tlul_pkg::*; ( + // TL-UL interface + input [DataMaxWidth+DataIntgWidth-1:0] data_intg_i, + output logic data_err_o +); + + logic [1:0] data_err; + caliptra_prim_secded_inv_39_32_dec u_data_chk ( + .data_i(data_intg_i), + .data_o(), + .syndrome_o(), + .err_o(data_err) + ); + + assign data_err_o = |data_err; + +endmodule : tlul_data_integ_dec diff --git a/src/tlul/rtl/tlul_data_integ_enc.sv b/src/tlul/rtl/tlul_data_integ_enc.sv new file mode 100644 index 0000000..ac0aee1 --- /dev/null +++ b/src/tlul/rtl/tlul_data_integ_enc.sv @@ -0,0 +1,22 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +`include "caliptra_prim_assert.sv" + +/** + * Data integrity encoder for bus integrity scheme + */ + +module tlul_data_integ_enc import tlul_pkg::*; ( + // TL-UL interface + input [DataMaxWidth-1:0] data_i, + output logic [DataMaxWidth+DataIntgWidth-1:0] data_intg_o +); + + caliptra_prim_secded_inv_39_32_enc u_data_gen ( + .data_i, + .data_o(data_intg_o) + ); + +endmodule : tlul_data_integ_enc diff --git a/src/tlul/rtl/tlul_err.sv b/src/tlul/rtl/tlul_err.sv new file mode 100644 index 0000000..0705ac1 --- /dev/null +++ b/src/tlul/rtl/tlul_err.sv @@ -0,0 +1,103 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + + +`include "caliptra_prim_assert.sv" + +module tlul_err import tlul_pkg::*; ( + input clk_i, + input rst_ni, + + input tl_h2d_t tl_i, + + output logic err_o +); + + localparam int IW = $bits(tl_i.a_source); + localparam int SZW = $bits(tl_i.a_size); + localparam int DW = $bits(tl_i.a_data); + localparam int MW = $bits(tl_i.a_mask); + localparam int SubAW = $clog2(DW/8); + + logic opcode_allowed, a_config_allowed; + + logic op_full, op_partial, op_get; + assign op_full = (tl_i.a_opcode == PutFullData); + assign op_partial = (tl_i.a_opcode == PutPartialData); + assign op_get = (tl_i.a_opcode == Get); + + // An instruction type transaction cannot be write + logic instr_wr_err; + assign instr_wr_err = caliptra_prim_mubi_pkg::mubi4_test_true_strict(tl_i.a_user.instr_type) & + (op_full | op_partial); + + logic instr_type_err; + assign instr_type_err = caliptra_prim_mubi_pkg::mubi4_test_invalid(tl_i.a_user.instr_type); + + // Anything that doesn't fall into the permitted category, it raises an error + assign err_o = ~(opcode_allowed & a_config_allowed) | instr_wr_err | instr_type_err; + + // opcode check + assign opcode_allowed = (tl_i.a_opcode == PutFullData) + | (tl_i.a_opcode == PutPartialData) + | (tl_i.a_opcode == Get); + + // a channel configuration check + logic addr_sz_chk; // address and size alignment check + logic mask_chk; // inactive lane a_mask check + logic fulldata_chk; // PutFullData should have size match to mask + + localparam bit [MW-1:0] MaskOne = 1; + logic [MW-1:0] mask; + + assign mask = MaskOne << tl_i.a_address[SubAW-1:0]; + + always_comb begin + addr_sz_chk = 1'b0; + mask_chk = 1'b0; + fulldata_chk = 1'b0; // Only valid when opcode is PutFullData + + if (tl_i.a_valid) begin + unique case (tl_i.a_size) + 'h0: begin // 1 Byte + addr_sz_chk = 1'b1; + mask_chk = ~|(tl_i.a_mask & ~mask); + fulldata_chk = |(tl_i.a_mask & mask); + end + + 'h1: begin // 2 Byte + addr_sz_chk = ~tl_i.a_address[0]; + // check inactive lanes if lower 2B, check a_mask[3:2], if uppwer 2B, a_mask[1:0] + mask_chk = (tl_i.a_address[1]) ? ~|(tl_i.a_mask & 4'b0011) + : ~|(tl_i.a_mask & 4'b1100); + fulldata_chk = (tl_i.a_address[1]) ? &tl_i.a_mask[3:2] : &tl_i.a_mask[1:0] ; + end + + 'h2: begin // 4 Byte + addr_sz_chk = ~|tl_i.a_address[SubAW-1:0]; + mask_chk = 1'b1; + fulldata_chk = &tl_i.a_mask[3:0]; + end + + default: begin // else + addr_sz_chk = 1'b0; + mask_chk = 1'b0; + fulldata_chk = 1'b0; + end + endcase + end else begin + addr_sz_chk = 1'b0; + mask_chk = 1'b0; + fulldata_chk = 1'b0; + end + end + + assign a_config_allowed = addr_sz_chk + & mask_chk + & (op_get | op_partial | fulldata_chk) ; + + // Only 32 bit data width for current tlul_err + `CALIPTRA_ASSERT_INIT(dataWidthOnly32_A, DW == 32) + +endmodule diff --git a/src/tlul/rtl/tlul_err_resp.sv b/src/tlul/rtl/tlul_err_resp.sv new file mode 100644 index 0000000..108c4f2 --- /dev/null +++ b/src/tlul/rtl/tlul_err_resp.sv @@ -0,0 +1,75 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// TL-UL error responder module, used by tlul_socket_1n to help response +// to requests to no correct address space. Responses are always one cycle +// after request with no stalling unless response is stuck on the way out. + +module tlul_err_resp #( + // By default, we return a proper bus error. In some cases, we need to return a blank all-zero + // response without setting the error bit, and for those cases ReturnBlankResp can be set to 1. + parameter bit ReturnBlankResp = 0 +) ( + input clk_i, + input rst_ni, + input tlul_pkg::tl_h2d_t tl_h_i, + output tlul_pkg::tl_d2h_t tl_h_o +); + import tlul_pkg::*; + import caliptra_prim_mubi_pkg::*; + + tl_a_op_e err_opcode; + logic [$bits(tl_h_i.a_source)-1:0] err_source; + logic [$bits(tl_h_i.a_size)-1:0] err_size; + logic err_rsp_pending; + mubi4_t err_instr_type; + tlul_pkg::tl_d2h_t tl_h_o_int; + + tlul_rsp_intg_gen #( + .EnableRspIntgGen(1), + .EnableDataIntgGen(1) + ) u_intg_gen ( + .tl_i(tl_h_o_int), + .tl_o(tl_h_o) + ); + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + err_rsp_pending <= 1'b0; + err_source <= {TL_AIW{1'b0}}; + err_opcode <= Get; + err_size <= '0; + err_instr_type <= MuBi4False; + end else if (err_rsp_pending && tl_h_i.d_ready) begin + err_rsp_pending <= 1'b0; + end else if (tl_h_i.a_valid && tl_h_o_int.a_ready) begin + err_rsp_pending <= 1'b1; + err_source <= tl_h_i.a_source; + err_opcode <= tl_h_i.a_opcode; + err_size <= tl_h_i.a_size; + err_instr_type <= tl_h_i.a_user.instr_type; + end + end + + assign tl_h_o_int.a_ready = ~err_rsp_pending; + assign tl_h_o_int.d_valid = err_rsp_pending; + if (ReturnBlankResp) begin : gen_zero_resp + assign tl_h_o_int.d_data = '0; + end else begin : gen_err_resp + assign tl_h_o_int.d_data = (mubi4_test_true_strict(err_instr_type)) ? DataWhenInstrError : + DataWhenError; + end + assign tl_h_o_int.d_source = err_source; + assign tl_h_o_int.d_sink = '0; + assign tl_h_o_int.d_param = '0; + assign tl_h_o_int.d_size = err_size; + assign tl_h_o_int.d_opcode = (err_opcode == Get) ? AccessAckData : AccessAck; + assign tl_h_o_int.d_user = '0; + assign tl_h_o_int.d_error = ~ReturnBlankResp; + + // Waive unused bits of tl_h_i + logic unused_tl_h; + assign unused_tl_h = ^{tl_h_i, err_instr_type}; + +endmodule diff --git a/src/tlul/rtl/tlul_fifo_async.sv b/src/tlul/rtl/tlul_fifo_async.sv new file mode 100644 index 0000000..c8dff01 --- /dev/null +++ b/src/tlul/rtl/tlul_fifo_async.sv @@ -0,0 +1,98 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// TL-UL fifo, used to add elasticity or an asynchronous clock crossing +// to an TL-UL bus. This instantiates two FIFOs, one for the request side, +// and one for the response side. + +`include "caliptra_prim_assert.sv" + +module tlul_fifo_async #( + parameter int unsigned ReqDepth = 4, + parameter int unsigned RspDepth = 4 +) ( + input clk_h_i, + input rst_h_ni, + input clk_d_i, + input rst_d_ni, + input tlul_pkg::tl_h2d_t tl_h_i, + output tlul_pkg::tl_d2h_t tl_h_o, + output tlul_pkg::tl_h2d_t tl_d_o, + input tlul_pkg::tl_d2h_t tl_d_i +); + + // Put everything on the request side into one FIFO + localparam int unsigned REQFIFO_WIDTH = $bits(tlul_pkg::tl_h2d_t)-2; + + prim_fifo_async #( + .Width(REQFIFO_WIDTH), + .Depth(ReqDepth), + .OutputZeroIfInvalid(1) + ) reqfifo ( + .clk_wr_i (clk_h_i), + .rst_wr_ni (rst_h_ni), + .clk_rd_i (clk_d_i), + .rst_rd_ni (rst_d_ni), + .wvalid_i (tl_h_i.a_valid), + .wready_o (tl_h_o.a_ready), + .wdata_i ({tl_h_i.a_opcode , + tl_h_i.a_param , + tl_h_i.a_size , + tl_h_i.a_source , + tl_h_i.a_address, + tl_h_i.a_mask , + tl_h_i.a_data , + tl_h_i.a_user }), + .rvalid_o (tl_d_o.a_valid), + .rready_i (tl_d_i.a_ready), + .rdata_o ({tl_d_o.a_opcode , + tl_d_o.a_param , + tl_d_o.a_size , + tl_d_o.a_source , + tl_d_o.a_address, + tl_d_o.a_mask , + tl_d_o.a_data , + tl_d_o.a_user }), + .wdepth_o (), + .rdepth_o () + ); + + // Put everything on the response side into the other FIFO + + localparam int unsigned RSPFIFO_WIDTH = $bits(tlul_pkg::tl_d2h_t) -2; + + prim_fifo_async #( + .Width(RSPFIFO_WIDTH), + .Depth(RspDepth), + .OutputZeroIfInvalid(1) + ) rspfifo ( + .clk_wr_i (clk_d_i), + .rst_wr_ni (rst_d_ni), + .clk_rd_i (clk_h_i), + .rst_rd_ni (rst_h_ni), + .wvalid_i (tl_d_i.d_valid), + .wready_o (tl_d_o.d_ready), + .wdata_i ({tl_d_i.d_opcode, + tl_d_i.d_param , + tl_d_i.d_size , + tl_d_i.d_source, + tl_d_i.d_sink , + tl_d_i.d_data , + tl_d_i.d_user , + tl_d_i.d_error }), + .rvalid_o (tl_h_o.d_valid), + .rready_i (tl_h_i.d_ready), + .rdata_o ({tl_h_o.d_opcode, + tl_h_o.d_param , + tl_h_o.d_size , + tl_h_o.d_source, + tl_h_o.d_sink , + tl_h_o.d_data , + tl_h_o.d_user , + tl_h_o.d_error }), + .wdepth_o (), + .rdepth_o () + ); + +endmodule diff --git a/src/tlul/rtl/tlul_fifo_sync.sv b/src/tlul/rtl/tlul_fifo_sync.sv new file mode 100644 index 0000000..b9abeca --- /dev/null +++ b/src/tlul/rtl/tlul_fifo_sync.sv @@ -0,0 +1,99 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// TL-UL fifo, used to add elasticity or an asynchronous clock crossing +// to an TL-UL bus. This instantiates two FIFOs, one for the request side, +// and one for the response side. + +module tlul_fifo_sync + import tlul_pkg::*; + #( + parameter bit ReqPass = 1'b1, + parameter bit RspPass = 1'b1, + parameter int unsigned ReqDepth = 2, + parameter int unsigned RspDepth = 2, + parameter int unsigned SpareReqW = 1, + parameter int unsigned SpareRspW = 1 +) ( + input clk_i, + input rst_ni, + input tlul_pkg::tl_h2d_t tl_h_i, + output tlul_pkg::tl_d2h_t tl_h_o, + output tlul_pkg::tl_h2d_t tl_d_o, + input tlul_pkg::tl_d2h_t tl_d_i, + input [SpareReqW-1:0] spare_req_i, + output [SpareReqW-1:0] spare_req_o, + input [SpareRspW-1:0] spare_rsp_i, + output [SpareRspW-1:0] spare_rsp_o +); + + // Put everything on the request side into one FIFO + localparam int unsigned REQFIFO_WIDTH = $bits(tlul_pkg::tl_h2d_t) -2 + SpareReqW; + + caliptra_prim_fifo_sync #(.Width(REQFIFO_WIDTH), .Pass(ReqPass), .Depth(ReqDepth)) reqfifo ( + .clk_i, + .rst_ni, + .clr_i (1'b0 ), + .wvalid_i (tl_h_i.a_valid), + .wready_o (tl_h_o.a_ready), + .wdata_i ({tl_h_i.a_opcode , + tl_h_i.a_param , + tl_h_i.a_size , + tl_h_i.a_source , + tl_h_i.a_address, + tl_h_i.a_mask , + tl_h_i.a_data , + tl_h_i.a_user , + spare_req_i}), + .rvalid_o (tl_d_o.a_valid), + .rready_i (tl_d_i.a_ready), + .rdata_o ({tl_d_o.a_opcode , + tl_d_o.a_param , + tl_d_o.a_size , + tl_d_o.a_source , + tl_d_o.a_address, + tl_d_o.a_mask , + tl_d_o.a_data , + tl_d_o.a_user , + spare_req_o}), + .full_o (), + .depth_o (), + .err_o ()); + + // Put everything on the response side into the other FIFO + + localparam int unsigned RSPFIFO_WIDTH = $bits(tlul_pkg::tl_d2h_t) -2 + SpareRspW; + + caliptra_prim_fifo_sync #(.Width(RSPFIFO_WIDTH), .Pass(RspPass), .Depth(RspDepth)) rspfifo ( + .clk_i, + .rst_ni, + .clr_i (1'b0 ), + .wvalid_i (tl_d_i.d_valid), + .wready_o (tl_d_o.d_ready), + .wdata_i ({tl_d_i.d_opcode, + tl_d_i.d_param , + tl_d_i.d_size , + tl_d_i.d_source, + tl_d_i.d_sink , + (tl_d_i.d_opcode == tlul_pkg::AccessAckData) ? tl_d_i.d_data : + {TL_DW{1'b0}} , + tl_d_i.d_user , + tl_d_i.d_error , + spare_rsp_i}), + .rvalid_o (tl_h_o.d_valid), + .rready_i (tl_h_i.d_ready), + .rdata_o ({tl_h_o.d_opcode, + tl_h_o.d_param , + tl_h_o.d_size , + tl_h_o.d_source, + tl_h_o.d_sink , + tl_h_o.d_data , + tl_h_o.d_user , + tl_h_o.d_error , + spare_rsp_o}), + .full_o (), + .depth_o (), + .err_o ()); + +endmodule diff --git a/src/tlul/rtl/tlul_jtag_dtm.sv b/src/tlul/rtl/tlul_jtag_dtm.sv new file mode 100644 index 0000000..fdbc184 --- /dev/null +++ b/src/tlul/rtl/tlul_jtag_dtm.sv @@ -0,0 +1,150 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// JTAG DTM to TL-UL Converter. +// This implements a JTAG DTM according to the RISC-V external debug v0.13 specification and +// uses the TL-UL protocol to transport read/write operations to the RISC-V debug module +// (i.e. the DMI is implemented with the TL-UL protocol): +// https://github.com/riscv/riscv-debug-spec/blob/release/riscv-debug-release.pdf +// + +module tlul_jtag_dtm #( + // Idcode value for the JTAG. + parameter logic [31:0] IdcodeValue = 32'h00000001, + parameter int unsigned NumDmiByteAbits = 18 +) ( + input clk_i, + input rst_ni, + input jtag_pkg::jtag_req_t jtag_i, + output jtag_pkg::jtag_rsp_t jtag_o, + // This bypasses the clock inverter inside the JTAG TAP for scanmmode. + input scan_rst_ni, + input prim_mubi_pkg::mubi4_t scanmode_i, + // TL-UL-based DMI + output tlul_pkg::tl_h2d_t tl_h2d_o, + input tlul_pkg::tl_d2h_t tl_d2h_i +); + + dm::dmi_req_t dmi_req; + logic dmi_req_valid; + logic dmi_req_ready; + dm::dmi_resp_t dmi_resp; + logic dmi_resp_ready; + logic dmi_resp_valid; + + logic scanmode; + prim_mubi4_dec u_prim_mubi4_dec ( + .mubi_i(scanmode_i), + .mubi_dec_o(scanmode) + ); + + logic tck_muxed; + logic trst_n_muxed; + prim_clock_mux2 #( + .NoFpgaBufG(1'b1) + ) u_prim_clock_mux2 ( + .clk0_i(jtag_i.tck), + .clk1_i(clk_i), + .sel_i (scanmode), + .clk_o (tck_muxed) + ); + + prim_clock_mux2 #( + .NoFpgaBufG(1'b1) + ) u_prim_rst_n_mux2 ( + .clk0_i(jtag_i.trst_n), + .clk1_i(scan_rst_ni), + .sel_i (scanmode), + .clk_o (trst_n_muxed) + ); + + // TODO: At the moment, this uses the JTAG DTM implementation from the PULP project. + // This module should be refactored in the future to support TL-UL directly, instead + // of a custom DMI protocol which necessitates another translation layer to TL-UL. + logic req_ready; + assign req_ready = dmi_req_ready && dmi_resp_ready; + + dmi_jtag #( + .IdcodeValue(IdcodeValue), + .NumDmiWordAbits(NumDmiByteAbits - 2) + ) u_dmi_jtag ( + .clk_i, + .rst_ni, + .testmode_i ( scanmode ), + .test_rst_ni ( scan_rst_ni ), + .dmi_rst_no ( ), // unused + .dmi_req_o ( dmi_req ), + .dmi_req_valid_o ( dmi_req_valid ), + // unless there is room for response, stall + .dmi_req_ready_i ( req_ready ), + .dmi_resp_i ( dmi_resp ), + .dmi_resp_ready_o ( dmi_resp_ready ), + .dmi_resp_valid_i ( dmi_resp_valid ), + .tck_i ( tck_muxed ), + .tms_i ( jtag_i.tms ), + .trst_ni ( trst_n_muxed ), + .td_i ( jtag_i.tdi ), + .td_o ( jtag_o.tdo ), + .tdo_oe_o ( jtag_o.tdo_oe ) + ); + + // Outstanding request handling. + logic pending_req_q; + always_ff @(posedge clk_i or negedge rst_ni) begin : p_pending + if (!rst_ni) begin + pending_req_q <= 1'b0; + end else begin + // New request + if (dmi_req_ready && dmi_req_valid && (!pending_req_q)) begin + pending_req_q <= 1'b1; + end else if (dmi_resp_valid) begin + pending_req_q <= 1'b0; + end + end + end + + // DMI to TL-UL transducing + logic dmi_error; + tlul_adapter_host #( + // Only make one request at a time. + .MAX_REQS(1), + .EnableDataIntgGen(1) + ) u_tap_tlul_host ( + .clk_i, + .rst_ni, + // Do not make more than one request at a time + .req_i ( dmi_req_valid && !pending_req_q ), + .gnt_o ( dmi_req_ready ), + .addr_i ( top_pkg::TL_AW'({dmi_req.addr, 2'b00}) ), + .we_i ( dmi_req.op == dm::DTM_WRITE ), + .wdata_i ( dmi_req.data ), + .wdata_intg_i ('0 ), + .be_i ( {top_pkg::TL_DBW{1'b1}} ), + .user_rsvd_i ('0 ), + .instr_type_i ( prim_mubi_pkg::MuBi4False ), + .valid_o ( dmi_resp_valid ), + .rdata_o ( dmi_resp.data ), + .rdata_intg_o ( ), + .err_o ( dmi_error ), + .intg_err_o ( ), + .tl_o ( tl_h2d_o ), + .tl_i ( tl_d2h_i ) + ); + + // We use the user channel to transmit the DMI response type. + assign dmi_resp.resp = (dmi_error) ? dm::DTM_ERR : dm::DTM_SUCCESS; + + // These signals are unused + logic unused_sigs; + assign unused_sigs = ^{ + dmi_req.addr[31:30], + tl_d2h_i.d_opcode, + tl_d2h_i.d_param, + tl_d2h_i.d_size, + tl_d2h_i.d_source, + tl_d2h_i.d_sink, + tl_d2h_i.d_error + }; + +endmodule : tlul_jtag_dtm diff --git a/src/tlul/rtl/tlul_lc_gate.sv b/src/tlul/rtl/tlul_lc_gate.sv new file mode 100644 index 0000000..104b351 --- /dev/null +++ b/src/tlul/rtl/tlul_lc_gate.sv @@ -0,0 +1,264 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Life cycle gating module for TL-UL protocol. +// Transactions are passed through when lc_en_i == ON. +// In all other cases (lc_en_i != ON) incoming transactions return a bus error. +// +// Note that the lc_en_i should be synchronized and buffered outside of this module using +// an instance of prim_lc_sync. + +module tlul_lc_gate + import tlul_pkg::*; + import lc_ctrl_pkg::*; +#( + // Number of LC gating muxes in each direction. + // It is recommended to set this parameter to 2, which results + // in a total of 4 gating muxes. + parameter int NumGatesPerDirection = 2, + // By default we return a TL-UL bus error response if the bus is gated. However, in some special + // cases we need to be able to return valid, all-zero responses instead (e.g. for the RV_DM). In + // those cases, ReturnBlankResp can be set to 1. + parameter bit ReturnBlankResp = 0, + // The maximum number of outstanding TL-UL requests at the output + parameter int unsigned Outstanding = 3 +) ( + input clk_i, + input rst_ni, + + // To host + input tl_h2d_t tl_h2d_i, + output tl_d2h_t tl_d2h_o, + + // To device + output tl_h2d_t tl_h2d_o, + input tl_d2h_t tl_d2h_i, + + // Flush control signaling + input flush_req_i, + output logic flush_ack_o, + + // Indicates whether there are pending responses on the device side. + output logic resp_pending_o, + + // LC control signal + input lc_tx_t lc_en_i, + output logic err_o +); + + ////////////////// + // Access Gates // + ////////////////// + + lc_tx_t err_en; + lc_tx_t [NumGatesPerDirection-1:0] err_en_buf; + + caliptra_prim_lc_sync #( + .NumCopies(NumGatesPerDirection), + .AsyncOn(0) + ) u_err_en_sync ( + .clk_i, + .rst_ni, + .lc_en_i(err_en), + .lc_en_o(err_en_buf) + ); + + tl_h2d_t tl_h2d_int [NumGatesPerDirection+1]; + tl_d2h_t tl_d2h_int [NumGatesPerDirection+1]; + for (genvar k = 0; k < NumGatesPerDirection; k++) begin : gen_lc_gating_muxes + // H -> D path. + caliptra_prim_blanker #( + .Width($bits(tl_h2d_t)) + ) u_prim_blanker_h2d ( + .in_i(tl_h2d_int[k]), + .en_i(lc_tx_test_false_strict(err_en_buf[k])), + .out_o(tl_h2d_int[k+1]) + ); + + // D -> H path. + caliptra_prim_blanker #( + .Width($bits(tl_d2h_t)) + ) u_prim_blanker_d2h ( + .in_i(tl_d2h_int[k+1]), + .en_i(lc_tx_test_false_strict(err_en_buf[k])), + .out_o(tl_d2h_int[k]) + ); + end + + // Assign signals on the device side. + assign tl_h2d_o = tl_h2d_int[NumGatesPerDirection]; + assign tl_d2h_int[NumGatesPerDirection] = tl_d2h_i; + + /////////////////////////// + // Host Side Interposing // + /////////////////////////// + + // Encoding generated with: + // $ ./util/design/sparse-fsm-encode.py -d 5 -m 4 -n 8 \ + // -s 3379253306 --language=sv + // + // Hamming distance histogram: + // + // 0: -- + // 1: -- + // 2: -- + // 3: -- + // 4: -- + // 5: |||||||||||||||||||| (66.67%) + // 6: |||||||||| (33.33%) + // 7: -- + // 8: -- + // + // Minimum Hamming distance: 5 + // Maximum Hamming distance: 6 + // Minimum Hamming weight: 3 + // Maximum Hamming weight: 5 + // + // Encoding generated with: + // $ ./util/design/sparse-fsm-encode.py -d 5 -m 5 -n 9 \ + // -s 686407169 --language=sv + // + // Hamming distance histogram: + // + // 0: -- + // 1: -- + // 2: -- + // 3: -- + // 4: -- + // 5: |||||||||||||||||||| (60.00%) + // 6: ||||||||||||| (40.00%) + // 7: -- + // 8: -- + // 9: -- + // + // Minimum Hamming distance: 5 + // Maximum Hamming distance: 6 + // Minimum Hamming weight: 3 + // Maximum Hamming weight: 6 + // + localparam int StateWidth = 9; + typedef enum logic [StateWidth-1:0] { + StActive = 9'b100100001, + StOutstanding = 9'b011100111, + StFlush = 9'b001001100, + StError = 9'b010111010, + StErrorOutstanding = 9'b100010110 + } state_e; + + state_e state_d, state_q; + `CALIPTRA_PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, StError) + + logic [caliptra_prim_util_pkg::vbits(Outstanding+1)-1:0] outstanding_txn; + logic a_ack; + logic d_ack; + assign a_ack = tl_h2d_i.a_valid & tl_d2h_o.a_ready; + assign d_ack = tl_h2d_i.d_ready & tl_d2h_o.d_valid; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + outstanding_txn <= '0; + end else if (a_ack && !d_ack) begin + outstanding_txn <= outstanding_txn + 1'b1; + end else if (d_ack && !a_ack) begin + outstanding_txn <= outstanding_txn - 1'b1; + end + end + + logic block_cmd; + always_comb begin + block_cmd = '0; + state_d = state_q; + err_en = Off; + err_o = '0; + flush_ack_o = '0; + resp_pending_o = 1'b0; + + unique case (state_q) + StActive: begin + if (lc_tx_test_false_loose(lc_en_i) || flush_req_i) begin + state_d = StOutstanding; + end + if (outstanding_txn != '0) begin + resp_pending_o = 1'b1; + end + end + + StOutstanding: begin + block_cmd = 1'b1; + if (outstanding_txn == '0) begin + state_d = lc_tx_test_false_loose(lc_en_i) ? StError : StFlush; + end else begin + resp_pending_o = 1'b1; + end + end + + StFlush: begin + block_cmd = 1'b1; + flush_ack_o = 1'b1; + if (lc_tx_test_false_loose(lc_en_i)) begin + state_d = StError; + end else if (!flush_req_i) begin + state_d = StActive; + end + end + + StError: begin + err_en = On; + if (lc_tx_test_true_strict(lc_en_i)) begin + state_d = StErrorOutstanding; + end + end + + StErrorOutstanding: begin + err_en = On; + block_cmd = 1'b1; + if (outstanding_txn == '0) begin + state_d = StActive; + end + end + + default: begin + err_o = 1'b1; + err_en = On; + end + + endcase // unique case (state_q) + end + + + // At the host side, we interpose the ready / valid signals so that we can return a bus error + // in case the lc signal is not set to ON. Note that this logic does not have to be duplicated + // since erroring back is considered a convenience feature so that the bus does not lock up. + tl_h2d_t tl_h2d_error; + tl_d2h_t tl_d2h_error; + always_comb begin + tl_h2d_int[0] = tl_h2d_i; + tl_d2h_o = tl_d2h_int[0]; + tl_h2d_error = '0; + + if (lc_tx_test_true_loose(err_en)) begin + tl_h2d_error = tl_h2d_i; + tl_d2h_o = tl_d2h_error; + end + + if (block_cmd) begin + tl_d2h_o.a_ready = 1'b0; + tl_h2d_int[0].a_valid = 1'b0; + tl_h2d_error.a_valid = 1'b0; + end + end + + tlul_err_resp #( + .ReturnBlankResp(ReturnBlankResp) + ) u_tlul_err_resp ( + .clk_i, + .rst_ni, + .tl_h_i(tl_h2d_error), + .tl_h_o(tl_d2h_error) + ); + + // Add assertion + `CALIPTRA_ASSERT(OutStandingOvfl_A, &outstanding_txn |-> ~a_ack) + +endmodule : tlul_lc_gate diff --git a/src/tlul/rtl/tlul_pkg.sv b/src/tlul/rtl/tlul_pkg.sv new file mode 100644 index 0000000..903b6ec --- /dev/null +++ b/src/tlul/rtl/tlul_pkg.sv @@ -0,0 +1,311 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// + +import caliptra_prim_pkg::*; +`ifndef TLUL_PKG_DEFINE +`define TLUL_PKG_DEFINE + +package tlul_pkg; + + parameter TL_AW=32; + parameter TL_DW=32; // = TL_DBW * 8; TL_DBW must be a power-of-two + parameter TL_AIW=8; // a_source, d_source + parameter TL_DIW=1; // d_sink + parameter TL_AUW=21; // a_user + parameter TL_DUW=14; // d_user + parameter TL_DBW=(TL_DW>>3); + parameter TL_SZW=$clog2($clog2(TL_DBW)+1); + + // this can be either PPC or BINTREE + // there is no functional difference, but timing and area behavior is different + // between the two instances. PPC can result in smaller implementations when timing + // is not critical, whereas BINTREE is favorable when timing pressure is high (but this + // may also result in a larger implementation). on FPGA targets, BINTREE is favorable + // both in terms of area and timing. + parameter ArbiterImpl = "PPC"; + + typedef enum logic [2:0] { + PutFullData = 3'h 0, + PutPartialData = 3'h 1, + Get = 3'h 4 + } tl_a_op_e; + + typedef enum logic [2:0] { + AccessAck = 3'h 0, + AccessAckData = 3'h 1 + } tl_d_op_e; + + parameter int H2DCmdMaxWidth = 57; + parameter int H2DCmdIntgWidth = 7; + parameter int H2DCmdFullWidth = H2DCmdMaxWidth + H2DCmdIntgWidth; + parameter int D2HRspMaxWidth = 57; + parameter int D2HRspIntgWidth = 7; + parameter int D2HRspFullWidth = D2HRspMaxWidth + D2HRspIntgWidth; + parameter int DataMaxWidth = 32; + parameter int DataIntgWidth = 7; + parameter int DataFullWidth = DataMaxWidth + DataIntgWidth; + parameter int RsvdWidth = TL_AUW - caliptra_prim_mubi_pkg::MuBi4Width - + H2DCmdIntgWidth - DataIntgWidth; + + // Data that is returned upon an a TL-UL error belonging to an instruction fetch. + // Note that this data will be returned with the correct bus integrity value. + parameter logic [TL_DW-1:0] DataWhenInstrError = '0; + // Data that is returned upon an a TL-UL error not belonging to an instruction fetch. + // Note that this data will be returned with the correct bus integrity value. + parameter logic [TL_DW-1:0] DataWhenError = {TL_DW{1'b1}}; + + typedef struct packed { + logic [RsvdWidth-1:0] rsvd; + caliptra_prim_mubi_pkg::mubi4_t instr_type; + logic [H2DCmdIntgWidth-1:0] cmd_intg; + logic [DataIntgWidth-1:0] data_intg; + } tl_a_user_t; + + parameter tl_a_user_t TL_A_USER_DEFAULT = '{ + rsvd: '0, + instr_type: caliptra_prim_mubi_pkg::MuBi4False, + cmd_intg: {H2DCmdIntgWidth{1'b1}}, + data_intg: {DataIntgWidth{1'b1}} + }; + + typedef struct packed { + caliptra_prim_mubi_pkg::mubi4_t instr_type; + logic [TL_AW-1:0] addr; + tl_a_op_e opcode; + logic [TL_DBW-1:0] mask; + } tl_h2d_cmd_intg_t; + + typedef struct packed { + logic a_valid; + tl_a_op_e a_opcode; + logic [2:0] a_param; + logic [TL_SZW-1:0] a_size; + logic [TL_AIW-1:0] a_source; + logic [TL_AW-1:0] a_address; + logic [TL_DBW-1:0] a_mask; + logic [TL_DW-1:0] a_data; + tl_a_user_t a_user; + + logic d_ready; + } tl_h2d_t; + + // The choice of all 1's as the blanked value is deliberate. + // It is assumed that most security features of the design are opt-in instead + // of opt-out. + // Given the opt-in nature, if a 0 were to propagate, the feature would be turned + // off. Whereas if a 1 were to propagate, it would either stay on or be turned on. + // There is however no perfect value for this purpose. + localparam logic [TL_DW-1:0] BlankedAData = {TL_DW{1'b1}}; + + localparam tl_h2d_t TL_H2D_DEFAULT = '{ + d_ready: 1'b1, + a_opcode: tl_a_op_e'('0), + a_user: TL_A_USER_DEFAULT, + a_data: BlankedAData, + default: '0 + }; + + typedef struct packed { + logic [D2HRspIntgWidth-1:0] rsp_intg; + logic [DataIntgWidth-1:0] data_intg; + } tl_d_user_t; + + parameter tl_d_user_t TL_D_USER_DEFAULT = '{ + rsp_intg: {D2HRspIntgWidth{1'b1}}, + data_intg: {DataIntgWidth{1'b1}} + }; + + typedef struct packed { + logic d_valid; + tl_d_op_e d_opcode; + logic [2:0] d_param; + logic [TL_SZW-1:0] d_size; // Bouncing back a_size + logic [TL_AIW-1:0] d_source; + logic [TL_DIW-1:0] d_sink; + logic [TL_DW-1:0] d_data; + tl_d_user_t d_user; + logic d_error; + + logic a_ready; + + } tl_d2h_t; + + typedef struct packed { + tl_d_op_e opcode; + logic [TL_SZW-1:0] size; + // Temporarily removed because source changes throughout the fabric + // and thus cannot be used for end-to-end checking. + // A different PR will propose a work-around (a hoaky one) to see if + // it gets the job done. + //logic [TL_AIW-1:0] source; + logic error; + } tl_d2h_rsp_intg_t; + + localparam tl_d2h_t TL_D2H_DEFAULT = '{ + a_ready: 1'b1, + d_opcode: tl_d_op_e'('0), + d_user: TL_D_USER_DEFAULT, + default: '0 + }; + + // Check user for unsupported values + function automatic logic tl_a_user_chk(tl_a_user_t user); + logic malformed_err; + logic unused_user; + unused_user = |user; + malformed_err = caliptra_prim_mubi_pkg::mubi4_test_invalid(user.instr_type); + return malformed_err; + endfunction // tl_a_user_chk + + // extract variables used for command checking + function automatic tl_h2d_cmd_intg_t extract_h2d_cmd_intg(tl_h2d_t tl); + tl_h2d_cmd_intg_t payload; + logic unused_tlul; + unused_tlul = ^tl; + payload.addr = tl.a_address; + payload.opcode = tl.a_opcode; + payload.mask = tl.a_mask; + payload.instr_type = tl.a_user.instr_type; + return payload; + endfunction // extract_h2d_payload + + // extract variables used for response checking + function automatic tl_d2h_rsp_intg_t extract_d2h_rsp_intg(tl_d2h_t tl); + tl_d2h_rsp_intg_t payload; + logic unused_tlul; + unused_tlul = ^tl; + payload.opcode = tl.d_opcode; + payload.size = tl.d_size; + //payload.source = tl.d_source; + payload.error = tl.d_error; + return payload; + endfunction // extract_d2h_rsp_intg + + // calculate ecc for command checking + function automatic logic [H2DCmdIntgWidth-1:0] get_cmd_intg(tl_h2d_t tl); + logic [H2DCmdIntgWidth-1:0] cmd_intg; + logic [H2DCmdMaxWidth-1:0] unused_cmd_payload; + tl_h2d_cmd_intg_t cmd; + cmd = extract_h2d_cmd_intg(tl); + {cmd_intg, unused_cmd_payload} = + caliptra_prim_secded_pkg::prim_secded_inv_64_57_enc(H2DCmdMaxWidth'(cmd)); + return cmd_intg; + endfunction // get_cmd_intg + + // calculate ecc for data checking + function automatic logic [DataIntgWidth-1:0] get_data_intg(logic [TL_DW-1:0] data); + logic [DataIntgWidth-1:0] data_intg; + logic [TL_DW-1:0] unused_data; + logic [DataIntgWidth + TL_DW - 1 : 0] enc_data; + enc_data = caliptra_prim_secded_pkg::prim_secded_inv_39_32_enc(data); + data_intg = enc_data[DataIntgWidth + TL_DW - 1 : TL_DW]; + unused_data = enc_data[TL_DW - 1 : 0]; + return data_intg; + endfunction // get_data_intg + + // return inverted integrity for command payload + function automatic logic [H2DCmdIntgWidth-1:0] get_bad_cmd_intg(tl_h2d_t tl); + logic [H2DCmdIntgWidth-1:0] cmd_intg; + cmd_intg = get_cmd_intg(tl); + return ~cmd_intg; + endfunction // get_bad_cmd_intg + + // return inverted integrity for data payload + function automatic logic [H2DCmdIntgWidth-1:0] get_bad_data_intg(logic [TL_DW-1:0] data); + logic [H2DCmdIntgWidth-1:0] data_intg; + data_intg = get_data_intg(data); + return ~data_intg; + endfunction // get_bad_data_intg + +endpackage + + +package axi_struct_pkg; + + typedef struct packed { + // AXI AW Channel + logic [31:0] awaddr; // 32-bit Address for write transaction + logic [1:0] awburst; // 2-bit Burst type (based on axi_burst_e width) + logic [2:0] awsize; // 3-bit Burst size + logic [7:0] awlen; // 8-bit Burst length + logic [31:0] awuser; // 32-bit User-defined signal + logic [7:0] awid; // 3-bit Write transaction ID + logic awlock; // Lock signal for atomic operations + logic awvalid; // Write address valid + + // AXI W Channel + logic [31:0] wdata; // 32-bit Write data + logic [3:0] wstrb; // 4-bit Write strobe (32/8 = 4) + logic wlast; // Last write in burst + logic wvalid; // Write data valid + + // AXI B Channel + logic bready; // Write response ready + } axi_wr_req_t; + + typedef struct packed { + + logic awready; // Write address ready + logic wready; // Write data ready + logic [1:0] bresp; // 2-bit Write response (based on axi_resp_e width) + logic [7:0] bid; // 3-bit Response ID + logic bvalid; // Write response valid + + } axi_wr_rsp_t; + + typedef struct packed { + + logic [31:0] araddr; // 32-bit Address for read transaction + logic [1:0] arburst; // 2-bit Burst type + logic [2:0] arsize; // 3-bit Burst size + logic [7:0] arlen; // 8-bit Burst length (max 255) + logic [31:0] aruser; // 32-bit User-defined signal for read + logic [7:0] arid; // 4-bit Read transaction ID + logic arlock; // Lock signal + logic arvalid; // Read address valid + + logic rready; // Read data ready + + } axi_rd_req_t; + + typedef struct packed { + + logic arready; // Read address ready + logic [31:0] rdata; // 32-bit Data returned from the read transaction + logic [1:0] rresp; // 2-bit Response status + logic [7:0] rid; // 4-bit Read transaction ID + logic rlast; // Last read in burst + logic rvalid; // Read data valid + + } axi_rd_rsp_t; + +endpackage +`endif + +// // Axi read package +// package axi_rd_pkg; + +// typedef struct packed { +// // AXI AR Channel +// logic [31:0] araddr; // 32-bit Address for read transaction +// logic [1:0] arburst; // 2-bit Burst type +// logic [2:0] arsize; // 3-bit Burst size +// logic [7:0] arlen; // 8-bit Burst length (max 255) +// logic [31:0] aruser; // 32-bit User-defined signal for read +// logic [3:0] arid; // 4-bit Read transaction ID +// logic arlock; // Lock signal +// logic arvalid; // Read address valid +// logic arready; // Read address ready + +// // AXI R Channel +// logic [31:0] rdata; // 32-bit Data returned from the read transaction +// logic [1:0] rresp; // 2-bit Response status +// logic [3:0] rid; // 4-bit Read transaction ID +// logic rlast; // Last read in burst +// logic rvalid; // Read data valid +// logic rready; // Read data ready +// } axi_rd_t; + +// endpackage diff --git a/src/tlul/rtl/tlul_rsp_intg_chk.sv b/src/tlul/rtl/tlul_rsp_intg_chk.sv new file mode 100644 index 0000000..0c5e270 --- /dev/null +++ b/src/tlul/rtl/tlul_rsp_intg_chk.sv @@ -0,0 +1,54 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +`include "caliptra_prim_assert.sv" + +/** + * Tile-Link UL response integrity check + */ + +module tlul_rsp_intg_chk import tlul_pkg::*; #( + parameter bit EnableRspDataIntgCheck = 0 +) ( + // TL-UL interface + input tl_d2h_t tl_i, + + // error output + output logic err_o +); + + logic [1:0] rsp_err; + tl_d2h_rsp_intg_t rsp; + assign rsp = extract_d2h_rsp_intg(tl_i); + + caliptra_prim_secded_inv_64_57_dec u_chk ( + .data_i({tl_i.d_user.rsp_intg, D2HRspMaxWidth'(rsp)}), + .data_o(), + .syndrome_o(), + .err_o(rsp_err) + ); + + logic rsp_data_err; + if (EnableRspDataIntgCheck) begin : gen_rsp_data_intg_check + tlul_data_integ_dec u_tlul_data_integ_dec ( + .data_intg_i({tl_i.d_user.data_intg, DataMaxWidth'(tl_i.d_data)}), + .data_err_o(rsp_data_err) + ); + end else begin : gen_no_rsp_data_intg_check + assign rsp_data_err = 1'b0; + end + + // error is not permanently latched as rsp_intg_chk is typically + // used near the host. + // if the error is permanent, it would imply the host could forever + // receive bus errors and lose all ability to debug. + // It should be up to the host to determine the permanence of this error. + assign err_o = tl_i.d_valid & (|rsp_err | rsp_data_err); + + logic unused_tl; + assign unused_tl = |tl_i; + + `CALIPTRA_ASSERT_INIT(PayLoadWidthCheck, $bits(tl_d2h_rsp_intg_t) <= D2HRspMaxWidth) + +endmodule // tlul_rsp_intg_chk diff --git a/src/tlul/rtl/tlul_rsp_intg_gen.sv b/src/tlul/rtl/tlul_rsp_intg_gen.sv new file mode 100644 index 0000000..741d4b6 --- /dev/null +++ b/src/tlul/rtl/tlul_rsp_intg_gen.sv @@ -0,0 +1,59 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +`include "caliptra_prim_assert.sv" + +/** + * Tile-Link UL response integrity generator + */ + +module tlul_rsp_intg_gen import tlul_pkg::*; #( + parameter bit EnableRspIntgGen = 1'b1, + parameter bit EnableDataIntgGen = 1'b1 +) ( + // TL-UL interface + input tl_d2h_t tl_i, + output tl_d2h_t tl_o +); + + logic [D2HRspIntgWidth-1:0] rsp_intg; + if (EnableRspIntgGen) begin : gen_rsp_intg + tl_d2h_rsp_intg_t rsp; + logic [D2HRspMaxWidth-1:0] unused_payload; + + assign rsp = extract_d2h_rsp_intg(tl_i); + + caliptra_prim_secded_inv_64_57_enc u_rsp_gen ( + .data_i(D2HRspMaxWidth'(rsp)), + .data_o({rsp_intg, unused_payload}) + ); + end else begin : gen_passthrough_rsp_intg + assign rsp_intg = tl_i.d_user.rsp_intg; + end + + logic [DataIntgWidth-1:0] data_intg; + if (EnableDataIntgGen) begin : gen_data_intg + logic [DataMaxWidth-1:0] unused_data; + tlul_data_integ_enc u_tlul_data_integ_enc ( + .data_i(DataMaxWidth'(tl_i.d_data)), + .data_intg_o({data_intg, unused_data}) + ); + end else begin : gen_passthrough_data_intg + assign data_intg = tl_i.d_user.data_intg; + end + + always_comb begin + tl_o = tl_i; + tl_o.d_user.rsp_intg = rsp_intg; + tl_o.d_user.data_intg = data_intg; + end + + logic unused_tl; + assign unused_tl = ^tl_i; + + + `CALIPTRA_ASSERT_INIT(PayLoadWidthCheck, $bits(tl_d2h_rsp_intg_t) <= D2HRspMaxWidth) + `CALIPTRA_ASSERT_INIT(DataWidthCheck_A, $bits(tl_i.d_data) <= DataMaxWidth) + +endmodule // tlul_rsp_intg_gen diff --git a/src/tlul/rtl/tlul_socket_1n.sv b/src/tlul/rtl/tlul_socket_1n.sv new file mode 100644 index 0000000..fb42df6 --- /dev/null +++ b/src/tlul/rtl/tlul_socket_1n.sv @@ -0,0 +1,255 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// TL-UL socket 1:N module +// +// configuration settings +// device_count: 4 +// +// Verilog parameters +// HReqPass: if 1 then host requests can pass through on empty fifo, +// default 1 +// HRspPass: if 1 then host responses can pass through on empty fifo, +// default 1 +// DReqPass: (one per device_count) if 1 then device i requests can +// pass through on empty fifo, default 1 +// DRspPass: (one per device_count) if 1 then device i responses can +// pass through on empty fifo, default 1 +// HReqDepth: Depth of host request FIFO, default 2 +// HRspDepth: Depth of host response FIFO, default 2 +// DReqDepth: (one per device_count) Depth of device i request FIFO, +// default 2 +// DRspDepth: (one per device_count) Depth of device i response FIFO, +// default 2 +// ExplicitErrs: This module always returns a request error if dev_select_i +// is greater than N-1. If ExplicitErrs is set then the width +// of the dev_select_i signal will be chosen to make sure that +// this is possible. This only makes a difference if N is a +// power of 2. +// +// Requests must stall to one device until all responses from other devices +// have returned. Need to keep a counter of all outstanding requests and +// wait until that counter is zero before switching devices. +// +// This module will return a request error if the input value of 'dev_select_i' +// is not within the range 0..N-1. Thus the instantiator of the socket +// can indicate error by any illegal value of dev_select_i. 4'b1111 is +// recommended for visibility +// +// The maximum value of N is 63 + +`include "caliptra_prim_assert.sv" + +module tlul_socket_1n #( + parameter int unsigned N = 4, + parameter bit HReqPass = 1'b1, + parameter bit HRspPass = 1'b1, + parameter bit [N-1:0] DReqPass = {N{1'b1}}, + parameter bit [N-1:0] DRspPass = {N{1'b1}}, + parameter bit [3:0] HReqDepth = 4'h1, + parameter bit [3:0] HRspDepth = 4'h1, + parameter bit [N*4-1:0] DReqDepth = {N{4'h1}}, + parameter bit [N*4-1:0] DRspDepth = {N{4'h1}}, + parameter bit ExplicitErrs = 1'b1, + + // The width of dev_select_i. We must be able to select any of the N devices + // (i.e. values 0..N-1). If ExplicitErrs is set, we also need to be able to + // represent N. + localparam int unsigned NWD = $clog2(ExplicitErrs ? N+1 : N) +) ( + input clk_i, + input rst_ni, + input tlul_pkg::tl_h2d_t tl_h_i, + output tlul_pkg::tl_d2h_t tl_h_o, + output tlul_pkg::tl_h2d_t tl_d_o [N], + input tlul_pkg::tl_d2h_t tl_d_i [N], + input [NWD-1:0] dev_select_i +); + + `CALIPTRA_ASSERT_INIT(maxN, N < 64) + + // Since our steering is done after potential FIFOing, we need to + // shove our device select bits into spare bits of reqfifo + + // instantiate the host fifo, create intermediate bus 't' + + // FIFO'd version of device select + logic [NWD-1:0] dev_select_t; + + tlul_pkg::tl_h2d_t tl_t_o; + tlul_pkg::tl_d2h_t tl_t_i; + + tlul_fifo_sync #( + .ReqPass(HReqPass), + .RspPass(HRspPass), + .ReqDepth(HReqDepth), + .RspDepth(HRspDepth), + .SpareReqW(NWD) + ) fifo_h ( + .clk_i, + .rst_ni, + .tl_h_i, + .tl_h_o, + .tl_d_o (tl_t_o), + .tl_d_i (tl_t_i), + .spare_req_i (dev_select_i), + .spare_req_o (dev_select_t), + .spare_rsp_i (1'b0), + .spare_rsp_o ()); + + + // We need to keep track of how many requests are outstanding, + // and to which device. New requests are compared to this and + // stall until that number is zero. + localparam int MaxOutstanding = 2**tlul_pkg::TL_AIW; // Up to 256 ounstanding + localparam int OutstandingW = $clog2(MaxOutstanding+1); + logic [OutstandingW-1:0] num_req_outstanding; + logic [NWD-1:0] dev_select_outstanding; + logic hold_all_requests; + logic accept_t_req, accept_t_rsp; + + assign accept_t_req = tl_t_o.a_valid & tl_t_i.a_ready; + assign accept_t_rsp = tl_t_i.d_valid & tl_t_o.d_ready; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + num_req_outstanding <= '0; + dev_select_outstanding <= '0; + end else if (accept_t_req) begin + if (!accept_t_rsp) begin + num_req_outstanding <= num_req_outstanding + 1'b1; + end + dev_select_outstanding <= dev_select_t; + end else if (accept_t_rsp) begin + num_req_outstanding <= num_req_outstanding - 1'b1; + end + end + + `CALIPTRA_ASSERT(NotOverflowed_A, + accept_t_req && !accept_t_rsp -> num_req_outstanding <= MaxOutstanding) + + assign hold_all_requests = + (num_req_outstanding != '0) & + (dev_select_t != dev_select_outstanding); + + // Make N copies of 't' request side with modified reqvalid, call + // them 'u[0]' .. 'u[n-1]'. + + tlul_pkg::tl_h2d_t tl_u_o [N+1]; + tlul_pkg::tl_d2h_t tl_u_i [N+1]; + + // ensure that when a device is not selected, both command + // data integrity can never match + tlul_pkg::tl_a_user_t blanked_auser; + assign blanked_auser = '{ + rsvd: tl_t_o.a_user.rsvd, + instr_type: tl_t_o.a_user.instr_type, + cmd_intg: tlul_pkg::get_bad_cmd_intg(tl_t_o), + data_intg: tlul_pkg::get_bad_data_intg(tlul_pkg::BlankedAData) + }; + + // if a host is not selected, or if requests are held off, blank the bus + for (genvar i = 0 ; i < N ; i++) begin : gen_u_o + logic dev_select; + assign dev_select = dev_select_t == NWD'(i) & ~hold_all_requests; + + assign tl_u_o[i].a_valid = tl_t_o.a_valid & dev_select; + assign tl_u_o[i].a_opcode = tl_t_o.a_opcode; + assign tl_u_o[i].a_param = tl_t_o.a_param; + assign tl_u_o[i].a_size = tl_t_o.a_size; + assign tl_u_o[i].a_source = tl_t_o.a_source; + assign tl_u_o[i].a_address = tl_t_o.a_address; + assign tl_u_o[i].a_mask = tl_t_o.a_mask; + assign tl_u_o[i].a_data = dev_select ? + tl_t_o.a_data : + tlul_pkg::BlankedAData; + assign tl_u_o[i].a_user = dev_select ? + tl_t_o.a_user : + blanked_auser; + + assign tl_u_o[i].d_ready = tl_t_o.d_ready; + end + + + tlul_pkg::tl_d2h_t tl_t_p ; + + // for the returning reqready, only look at the device we're addressing + logic hfifo_reqready; + always_comb begin + hfifo_reqready = tl_u_i[N].a_ready; // default to error + for (int idx = 0 ; idx < N ; idx++) begin + //if (dev_select_outstanding == NWD'(idx)) hfifo_reqready = tl_u_i[idx].a_ready; + if (dev_select_t == NWD'(idx)) hfifo_reqready = tl_u_i[idx].a_ready; + end + if (hold_all_requests) hfifo_reqready = 1'b0; + end + // Adding a_valid as a qualifier. This prevents the a_ready from having unknown value + // when the address is unknown and the Host TL-UL FIFO is bypass mode. + assign tl_t_i.a_ready = tl_t_o.a_valid & hfifo_reqready; + + always_comb begin + tl_t_p = tl_u_i[N]; + for (int idx = 0 ; idx < N ; idx++) begin + if (dev_select_outstanding == NWD'(idx)) tl_t_p = tl_u_i[idx]; + end + end + assign tl_t_i.d_valid = tl_t_p.d_valid ; + assign tl_t_i.d_opcode = tl_t_p.d_opcode; + assign tl_t_i.d_param = tl_t_p.d_param ; + assign tl_t_i.d_size = tl_t_p.d_size ; + assign tl_t_i.d_source = tl_t_p.d_source; + assign tl_t_i.d_sink = tl_t_p.d_sink ; + assign tl_t_i.d_data = tl_t_p.d_data ; + assign tl_t_i.d_user = tl_t_p.d_user ; + assign tl_t_i.d_error = tl_t_p.d_error ; + + // Instantiate all the device FIFOs + for (genvar i = 0 ; i < N ; i++) begin : gen_dfifo + tlul_fifo_sync #( + .ReqPass(DReqPass[i]), + .RspPass(DRspPass[i]), + .ReqDepth(DReqDepth[i*4+:4]), + .RspDepth(DRspDepth[i*4+:4]) + ) fifo_d ( + .clk_i, + .rst_ni, + .tl_h_i (tl_u_o[i]), + .tl_h_o (tl_u_i[i]), + .tl_d_o (tl_d_o[i]), + .tl_d_i (tl_d_i[i]), + .spare_req_i (1'b0), + .spare_req_o (), + .spare_rsp_i (1'b0), + .spare_rsp_o ()); + end + + // Instantiate the error responder. It's only needed if a value greater than + // N-1 is actually representable in NWD bits. + if ($clog2(N+1) <= NWD) begin : gen_err_resp + assign tl_u_o[N].d_ready = tl_t_o.d_ready; + assign tl_u_o[N].a_valid = tl_t_o.a_valid & + (dev_select_t >= NWD'(N)) & + ~hold_all_requests; + assign tl_u_o[N].a_opcode = tl_t_o.a_opcode; + assign tl_u_o[N].a_param = tl_t_o.a_param; + assign tl_u_o[N].a_size = tl_t_o.a_size; + assign tl_u_o[N].a_source = tl_t_o.a_source; + assign tl_u_o[N].a_address = tl_t_o.a_address; + assign tl_u_o[N].a_mask = tl_t_o.a_mask; + assign tl_u_o[N].a_data = tl_t_o.a_data; + assign tl_u_o[N].a_user = tl_t_o.a_user; + tlul_err_resp err_resp ( + .clk_i, + .rst_ni, + .tl_h_i (tl_u_o[N]), + .tl_h_o (tl_u_i[N]) + ); + end else begin : gen_no_err_resp // block: gen_err_resp + assign tl_u_o[N] = '0; + assign tl_u_i[N] = '0; + logic unused_sig; + assign unused_sig = ^tl_u_o[N]; + end + +endmodule diff --git a/src/tlul/rtl/tlul_socket_m1.sv b/src/tlul/rtl/tlul_socket_m1.sv new file mode 100644 index 0000000..3a8cf43 --- /dev/null +++ b/src/tlul/rtl/tlul_socket_m1.sv @@ -0,0 +1,260 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// TL-UL socket M:1 module +// +// Verilog parameters +// M: Number of host ports. +// HReqPass: M bit array to allow requests to pass through the host i +// FIFO with no clock delay if the request FIFO is empty. If +// 1'b0, at least one clock cycle of latency is created. +// Default is 1'b1. +// HRspPass: Same as HReqPass but for host response FIFO. +// HReqDepth: Mx4 bit array. bit[i*4+:4] is depth of host i request FIFO. +// Depth of zero is allowed if ReqPass is true. A maximum value +// of 16 is allowed, default is 2. +// HRspDepth: Same as HReqDepth but for host response FIFO. +// DReqPass: Same as HReqPass but for device request FIFO. +// DRspPass: Same as HReqPass but for device response FIFO. +// DReqDepth: Same as HReqDepth but for device request FIFO. +// DRspDepth: Same as HReqDepth but for device response FIFO. + +`include "caliptra_prim_assert.sv" + +module tlul_socket_m1 #( + parameter int unsigned M = 4, + parameter bit [M-1:0] HReqPass = {M{1'b1}}, + parameter bit [M-1:0] HRspPass = {M{1'b1}}, + parameter bit [M*4-1:0] HReqDepth = {M{4'h1}}, + parameter bit [M*4-1:0] HRspDepth = {M{4'h1}}, + parameter bit DReqPass = 1'b1, + parameter bit DRspPass = 1'b1, + parameter bit [3:0] DReqDepth = 4'h1, + parameter bit [3:0] DRspDepth = 4'h1 +) ( + input clk_i, + input rst_ni, + + input tlul_pkg::tl_h2d_t tl_h_i [M], + output tlul_pkg::tl_d2h_t tl_h_o [M], + + output tlul_pkg::tl_h2d_t tl_d_o, + input tlul_pkg::tl_d2h_t tl_d_i +); + + `CALIPTRA_ASSERT_INIT(maxM, M < 16) + + + // Signals + // + // tl_h_i/o[0] | tl_h_i/o[1] | ... | tl_h_i/o[M-1] + // | | | + // u_hostfifo[0] u_hostfifo[1] u_hostfifo[M-1] + // | | | + // hreq_fifo_o(i) / hrsp_fifo_i(i) + // --------------------------------------- + // | request/grant/req_data | + // | | + // | PRIM_ARBITER | + // | | + // | arb_valid / arb_ready / arb_data | + // --------------------------------------- + // | + // dreq_fifo_i / drsp_fifo_o + // | + // u_devicefifo + // | + // tl_d_o/i + // + // Required ID width to distinguish between host ports + // Used in response steering + localparam int unsigned IDW = tlul_pkg::TL_AIW; + localparam int unsigned STIDW = $clog2(M); + + tlul_pkg::tl_h2d_t hreq_fifo_o [M]; + tlul_pkg::tl_d2h_t hrsp_fifo_i [M]; + + logic [M-1:0] hrequest; + logic [M-1:0] hgrant; + + tlul_pkg::tl_h2d_t dreq_fifo_i; + tlul_pkg::tl_d2h_t drsp_fifo_o; + + logic arb_valid; + logic arb_ready; + tlul_pkg::tl_h2d_t arb_data; + + // Host Req/Rsp FIFO + for (genvar i = 0 ; i < M ; i++) begin : gen_host_fifo + tlul_pkg::tl_h2d_t hreq_fifo_i; + + // ID Shifting + logic [STIDW-1:0] reqid_sub; + logic [IDW-1:0] shifted_id; + assign reqid_sub = i; // can cause conversion error? + assign shifted_id = { + tl_h_i[i].a_source[0+:(IDW-STIDW)], + reqid_sub + }; + + `CALIPTRA_ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0) + + // assign not connected bits to nc_* signal to make lint happy + logic [IDW-1 : IDW-STIDW] unused_tl_h_source; + assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW]; + + // Put shifted ID + assign hreq_fifo_i = '{ + a_valid: tl_h_i[i].a_valid, + a_opcode: tl_h_i[i].a_opcode, + a_param: tl_h_i[i].a_param, + a_size: tl_h_i[i].a_size, + a_source: shifted_id, + a_address: tl_h_i[i].a_address, + a_mask: tl_h_i[i].a_mask, + a_data: tl_h_i[i].a_data, + a_user: tl_h_i[i].a_user, + d_ready: tl_h_i[i].d_ready + }; + + tlul_fifo_sync #( + .ReqPass (HReqPass[i]), + .RspPass (HRspPass[i]), + .ReqDepth (HReqDepth[i*4+:4]), + .RspDepth (HRspDepth[i*4+:4]), + .SpareReqW (1) + ) u_hostfifo ( + .clk_i, + .rst_ni, + .tl_h_i (hreq_fifo_i), + .tl_h_o (tl_h_o[i]), + .tl_d_o (hreq_fifo_o[i]), + .tl_d_i (hrsp_fifo_i[i]), + .spare_req_i (1'b0), + .spare_req_o (), + .spare_rsp_i (1'b0), + .spare_rsp_o () + ); + end + + // Device Req/Rsp FIFO + tlul_fifo_sync #( + .ReqPass (DReqPass), + .RspPass (DRspPass), + .ReqDepth (DReqDepth), + .RspDepth (DRspDepth), + .SpareReqW (1) + ) u_devicefifo ( + .clk_i, + .rst_ni, + .tl_h_i (dreq_fifo_i), + .tl_h_o (drsp_fifo_o), + .tl_d_o (tl_d_o), + .tl_d_i (tl_d_i), + .spare_req_i (1'b0), + .spare_req_o (), + .spare_rsp_i (1'b0), + .spare_rsp_o () + ); + + // Request Arbiter + for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt + assign hrequest[i] = hreq_fifo_o[i].a_valid; + end + + assign arb_ready = drsp_fifo_o.a_ready; + + if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc + prim_arbiter_ppc #( + .N (M), + .DW ($bits(tlul_pkg::tl_h2d_t)) + ) u_reqarb ( + .clk_i, + .rst_ni, + .req_chk_i ( 1'b0 ), // TL-UL allows dropping valid without ready. See #3354. + .req_i ( hrequest ), + .data_i ( hreq_fifo_o ), + .gnt_o ( hgrant ), + .idx_o ( ), + .valid_o ( arb_valid ), + .data_o ( arb_data ), + .ready_i ( arb_ready ) + ); + end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb + prim_arbiter_tree #( + .N (M), + .DW ($bits(tlul_pkg::tl_h2d_t)) + ) u_reqarb ( + .clk_i, + .rst_ni, + .req_chk_i ( 1'b0 ), // TL-UL allows dropping valid without ready. See #3354. + .req_i ( hrequest ), + .data_i ( hreq_fifo_o ), + .gnt_o ( hgrant ), + .idx_o ( ), + .valid_o ( arb_valid ), + .data_o ( arb_data ), + .ready_i ( arb_ready ) + ); + end else begin : gen_unknown + `CALIPTRA_ASSERT_INIT(UnknownArbImpl_A, 0) + end + + logic [ M-1:0] hfifo_rspvalid; + logic [ M-1:0] dfifo_rspready; + logic [IDW-1:0] hfifo_rspid; + logic dfifo_rspready_merged; + + // arb_data --> dreq_fifo_i + // dreq_fifo_i.hd_rspready <= dfifo_rspready + + assign dfifo_rspready_merged = |dfifo_rspready; + assign dreq_fifo_i = '{ + a_valid: arb_valid, + a_opcode: arb_data.a_opcode, + a_param: arb_data.a_param, + a_size: arb_data.a_size, + a_source: arb_data.a_source, + a_address: arb_data.a_address, + a_mask: arb_data.a_mask, + a_data: arb_data.a_data, + a_user: arb_data.a_user, + + d_ready: dfifo_rspready_merged + }; + + // Response ID steering + // drsp_fifo_o --> hrsp_fifo_i[i] + + // Response ID shifting before put into host fifo + assign hfifo_rspid = { + {STIDW{1'b0}}, + drsp_fifo_o.d_source[IDW-1:STIDW] + }; + for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting + assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid & + (drsp_fifo_o.d_source[0+:STIDW] == i); + assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready & + (drsp_fifo_o.d_source[0+:STIDW] == i) & + drsp_fifo_o.d_valid; + + assign hrsp_fifo_i[i] = '{ + d_valid: hfifo_rspvalid[i], + d_opcode: drsp_fifo_o.d_opcode, + d_param: drsp_fifo_o.d_param, + d_size: drsp_fifo_o.d_size, + d_source: hfifo_rspid, + d_sink: drsp_fifo_o.d_sink, + d_data: drsp_fifo_o.d_data, + d_user: drsp_fifo_o.d_user, + d_error: drsp_fifo_o.d_error, + a_ready: hgrant[i] + }; + end + + // this assertion fails when rspid[0+:STIDW] not in [0..M-1] + `CALIPTRA_ASSERT(rspIdInRange, drsp_fifo_o.d_valid |-> + drsp_fifo_o.d_source[0+:STIDW] >= 0 && drsp_fifo_o.d_source[0+:STIDW] < M) + +endmodule diff --git a/src/tlul/rtl/tlul_sram_byte.sv b/src/tlul/rtl/tlul_sram_byte.sv new file mode 100644 index 0000000..3b2d225 --- /dev/null +++ b/src/tlul/rtl/tlul_sram_byte.sv @@ -0,0 +1,723 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +`include "caliptra_prim_assert.sv" + +/** + * Tile-Link UL adapter for SRAM-like devices + * + * This module handles byte writes for tlul integrity. + * When a byte write is received, the downstream data is read first + * to correctly create the integrity constant. + * + * A tlul transaction goes through this module. If required, a + * tlul read transaction is generated out first. If not required, the + * incoming tlul transaction is directly muxed out. + */ +module tlul_sram_byte import tlul_pkg::*; #( + parameter bit EnableIntg = 0, // Enable integrity handling at byte level, + parameter int Outstanding = 1, + parameter bit EnableReadback = 0 // Enable readback checks on all transactions must have + // EnableIntg == 1 to enable +) ( + input clk_i, + input rst_ni, + + input tl_h2d_t tl_i, + output tl_d2h_t tl_o, + + output tl_h2d_t tl_sram_o, + input tl_d2h_t tl_sram_i, + + // if incoming transaction already has an error, do not + // attempt to handle the byte-write access. Instead treat as + // feedthrough and allow the system to directly error back. + // The error indication is also fed through + input error_i, + output logic error_o, + output logic alert_o, + + output logic compound_txn_in_progress_o, + + input caliptra_prim_mubi_pkg::mubi4_t readback_en_i, + + input logic wr_collision_i, + input logic write_pending_i +); + + import caliptra_prim_mubi_pkg::mubi4_t; + import caliptra_prim_mubi_pkg::mubi4_test_true_loose; + import caliptra_prim_mubi_pkg::mubi4_test_false_strict; + import caliptra_prim_mubi_pkg::MuBi4True; + import caliptra_prim_mubi_pkg::MuBi4False; + import caliptra_prim_mubi_pkg::MuBi4Width; + + // Encoding generated with: + // $ ./util/design/sparse-fsm-encode.py -d 3 -m 11 -n 8 \ + // -s 718546395 --language=sv + // + // Hamming distance histogram: + // + // 0: -- + // 1: -- + // 2: -- + // 3: |||||||||||||| (25.45%) + // 4: |||||||||||||||||||| (36.36%) + // 5: |||||||||||| (21.82%) + // 6: ||||||| (12.73%) + // 7: || (3.64%) + // 8: -- + // + // Minimum Hamming distance: 3 + // Maximum Hamming distance: 7 + // Minimum Hamming weight: 1 + // Maximum Hamming weight: 6 + // + localparam int StateWidth = 8; + typedef enum logic [StateWidth-1:0] { + StPassThru = 8'b01111110, + StWaitRd = 8'b00000010, + StWriteCmd = 8'b11110001, + StWrReadBackInit = 8'b10011001, + StWrReadBack = 8'b00001111, + StWrReadBackDWait = 8'b00110000, + StRdReadBack = 8'b10101100, + StRdReadBackDWait = 8'b11000000, + StByteWrReadBackInit = 8'b01010111, + StByteWrReadBack = 8'b11100111, + StByteWrReadBackDWait = 8'b11111111 + } state_e; + + if (EnableIntg) begin : gen_integ_handling + // state and selection + logic stall_host; + logic wait_phase; + logic rd_phase; + logic rd_wait; + logic wr_phase; + logic rdback_phase; + logic rdback_phase_wrreadback; + logic rdback_wait; + state_e state_d, state_q; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + state_q <= StPassThru; + end else begin + state_q <= state_d; + end + end + + // transaction qualifying signals + logic a_ack; // upstream a channel acknowledgement + logic d_ack; // upstream d channel acknowledgement + logic sram_a_ack; // downstream a channel acknowledgement + logic sram_d_ack; // downstream d channel acknowledgement + logic wr_txn; + logic byte_wr_txn; + logic byte_req_ack; + logic hold_tx_data; + + localparam int unsigned PendingTxnCntW = caliptra_prim_util_pkg::vbits(Outstanding+1); + logic [PendingTxnCntW-1:0] pending_txn_cnt; + + // prim fifo for capturing info + typedef struct packed { + logic [2:0] a_param; + logic [TL_SZW-1:0] a_size; + logic [TL_AIW-1:0] a_source; + logic [TL_AW-1:0] a_address; + logic [TL_DBW-1:0] a_mask; + logic [TL_DW-1:0] a_data; + tl_a_user_t a_user; + } tl_txn_data_t; + + tl_txn_data_t held_data; + + assign a_ack = tl_i.a_valid & tl_o.a_ready; + assign d_ack = tl_o.d_valid & tl_i.d_ready; + assign sram_a_ack = tl_sram_o.a_valid & tl_sram_i.a_ready; + assign sram_d_ack = tl_sram_i.d_valid & tl_sram_o.d_ready; + assign wr_txn = (tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData); + + assign byte_req_ack = byte_wr_txn & a_ack & ~error_i; + assign byte_wr_txn = tl_i.a_valid & ~&tl_i.a_mask & wr_txn; + + logic rdback_chk_ok; + mubi4_t rdback_check_q, rdback_check_d; + mubi4_t rdback_en_q, rdback_en_d; + logic [31:0] rdback_data_exp_q, rdback_data_exp_d; + logic [DataIntgWidth-1:0] rdback_data_exp_intg_q, rdback_data_exp_intg_d; + + if (EnableReadback) begin : gen_readback_logic + logic rdback_chk_ok_unbuf; + + assign rdback_chk_ok_unbuf = (rdback_data_exp_q == tl_sram_i.d_data); + + caliptra_prim_sec_anchor_buf #( + .Width(1) + ) u_rdback_chk_ok_buf ( + .in_i (rdback_chk_ok_unbuf), + .out_o(rdback_chk_ok) + ); + + caliptra_prim_flop #( + .Width(MuBi4Width), + .ResetValue(MuBi4Width'(MuBi4False)) + ) u_rdback_check_flop ( + .clk_i, + .rst_ni, + + .d_i(MuBi4Width'(rdback_check_d)), + .q_o({rdback_check_q}) + ); + + caliptra_prim_flop #( + .Width(MuBi4Width), + .ResetValue(MuBi4Width'(MuBi4False)) + ) u_rdback_en_flop ( + .clk_i, + .rst_ni, + + .d_i(MuBi4Width'(rdback_en_d)), + .q_o({rdback_en_q}) + ); + + caliptra_prim_flop #( + .Width(32), + .ResetValue(0) + ) u_rdback_data_exp ( + .clk_i, + .rst_ni, + + .d_i(rdback_data_exp_d), + .q_o(rdback_data_exp_q) + ); + + caliptra_prim_flop #( + .Width(DataIntgWidth), + .ResetValue(0) + ) u_rdback_data_exp_intg ( + .clk_i, + .rst_ni, + + .d_i(rdback_data_exp_intg_d), + .q_o(rdback_data_exp_intg_q) + ); + + // If the readback feature is enabled and we are currently in the readback phase, + // no address collision should happen inside prim_ram_1p_scr. If this would be the + // case, we would read from the holding register inside prim_ram_1p_scr instead of + // actually performing the readback from the memory. + `CALIPTRA_ASSERT(WRCollisionDuringReadBack_A, (rdback_phase | rdback_phase_wrreadback) & + mubi4_test_true_loose(rdback_en_q) |-> !wr_collision_i) + + + // If the readback feature is enabled, we assume that the write phase takes one extra cycle + // due to the underyling scrambling mechanism. If this additional cycle is not needed anymore + // in the future (e.g. due to the removale of the scrambling mechanism), the readback does not + // need to be delayed by once cylce in the FSM below. + `CALIPTRA_ASSERT(NoPendingWriteAfterWrite_A, wr_phase & mubi4_test_true_loose(rdback_en_q) + |=> write_pending_i) + + + end else begin: gen_no_readback_logic + assign rdback_chk_ok = 1'b0; + assign rdback_check_q = MuBi4False; + assign rdback_en_q = MuBi4False; + assign rdback_data_exp_q = 1'b0; + assign rdback_data_exp_intg_q = 1'b0; + + logic unused_rdback; + + assign unused_rdback = ^{rdback_check_d, rdback_data_exp_d, rdback_data_exp_intg_d}; + end + + // state machine handling + always_comb begin + rd_wait = 1'b0; + wait_phase = 1'b0; + stall_host = 1'b0; + wr_phase = 1'b0; + rd_phase = 1'b0; + rdback_phase = 1'b0; + rdback_phase_wrreadback = 1'b0; + rdback_wait = 1'b0; + state_d = state_q; + hold_tx_data = 1'b0; + alert_o = 1'b0; + rdback_check_d = rdback_check_q; + rdback_en_d = rdback_en_q; + rdback_data_exp_d = rdback_data_exp_q; + rdback_data_exp_intg_d = rdback_data_exp_intg_q; + + unique case (state_q) + StPassThru: begin + if (mubi4_test_true_loose(rdback_en_q) && mubi4_test_true_loose(rdback_check_q)) begin + // When we're expecting a readback check that means we'll see a data response from the + // SRAM this cycle which we need to check against the readback registers. During this + // cycle the data response out (via tl_o) will be squashed to invalid but we can accept + // a new transaction (via tl_i). + rdback_wait = 1'b1; + rdback_check_d = MuBi4False; + + // Perform the readback check. + if (!rdback_chk_ok) begin + alert_o = 1'b1; + end + end + + if (byte_wr_txn) begin + rd_phase = 1'b1; + if (byte_req_ack) begin + state_d = StWaitRd; + end + end else if (a_ack && mubi4_test_true_loose(rdback_en_q) && !error_i) begin + // For reads and full word writes we'll first do the transaction and then do a readback + // check. Setting `hold_tx_data` here will preserve the transaction information in + // u_sync_fifo for doing the readback transaction. + hold_tx_data = 1'b1; + state_d = wr_txn ? StWrReadBackInit : StRdReadBack; + end + + if (!tl_sram_o.a_valid && !tl_o.d_valid && + mubi4_test_false_strict(rdback_check_q)) begin + // Store readback enable into register when bus is idle and no readback is processed. + rdback_en_d = readback_en_i; + end + end + + // Due to the way things are serialized, there is no way for the logic to tell which read + // belongs to the partial read unless it flushes all prior transactions. Hence, we wait + // here until exactly one outstanding transaction remains (that one is the partial read). + StWaitRd: begin + rd_phase = 1'b1; + stall_host = 1'b1; + if (pending_txn_cnt == PendingTxnCntW'(1)) begin + rd_wait = 1'b1; + if (sram_d_ack) begin + state_d = StWriteCmd; + end + end + end + + StWriteCmd: begin + stall_host = 1'b1; + wr_phase = 1'b1; + + if (sram_a_ack) begin + state_d = mubi4_test_true_loose(rdback_en_q) ? StByteWrReadBackInit : StPassThru; + rdback_check_d = mubi4_test_true_loose(rdback_en_q) ? MuBi4True : MuBi4False; + rdback_data_exp_d = tl_sram_o.a_data; + rdback_data_exp_intg_d = tl_sram_o.a_user.data_intg; + end + end + + StWrReadBackInit: begin + // Perform readback after full write. To avoid that we read the holding register + // in the readback, wait until the write was processed by the memory module. + if (EnableReadback == 0) begin : gen_inv_state_StWrReadBackInit + // If readback is disabled, we shouldn't be in this state. + alert_o = 1'b1; + end + + // Stall the host to perform the readback in the next cycle. + stall_host = 1'b1; + + // Need to ensure there's no other transactions in flight before we do the readback (the + // initial write we're doing the readback for should be the only one active). + if (pending_txn_cnt == PendingTxnCntW'(1)) begin + wait_phase = 1'b1; + // Data we're checking against the readback is captured from the write transaction that + // was sent. + rdback_check_d = mubi4_test_true_loose(rdback_en_q) ? MuBi4True : MuBi4False; + rdback_data_exp_d = held_data.a_data; + rdback_data_exp_intg_d = held_data.a_user.data_intg; + if (d_ack) begin + // Got an immediate TL-UL write response. Wait for one cycle until the holding + // register is flushed and then perform the readback. + state_d = StWrReadBack; + end else begin + // No response yet to the initial write. + state_d = StWrReadBackDWait; + end + end + end + + StWrReadBack: begin + // Perform readback and check response in StPassThru. + if (EnableReadback == 0) begin : gen_inv_state_StWrReadBack + // If readback is disabled, we shouldn't be in this state. + alert_o = 1'b1; + end + + stall_host = 1'b1; + + rdback_phase = 1'b1; + + state_d = StPassThru; + end + + StWrReadBackDWait: begin + // We have not received the d_valid response of the initial write. Wait + // for the valid signal. + if (EnableReadback == 0) begin : gen_inv_state_StWrReadBackDWait + // If readback is disabled, we shouldn't be in this state. + alert_o = 1'b1; + end + + // Wait until we get write response. + wait_phase = 1'b1; + + stall_host = 1'b1; + + if (d_ack) begin + // Got the TL-UL write response. Wait for one cycle until the holding + // register is flushed and then perform the readback. + state_d = StWrReadBack; + end + end + + StByteWrReadBackInit: begin + // Perform readback after partial write. To avoid that we read the holding register + // in the readback, do the actual readback check in the next FSM state. + if (EnableReadback == 0) begin : gen_inv_state_StByteWrReadBackInit + // If readback is disabled, we shouldn't be in this state. + alert_o = 1'b1; + end + + // Sends out a read to a readback check on a partial write. The host is stalled whilst + // this is happening. + stall_host = 1'b1; + + // Wait until there is a single ongoing transaction. + if (pending_txn_cnt == PendingTxnCntW'(1)) begin + // Wait for one cycle with sending readback request to SRAM to avoid reading from + // holding register. + wait_phase = 1'b1; + + if (d_ack) begin + // Got an immediate TL-UL write response. Wait for one cycle until the holding + // register is flushed and then perform the readback. + state_d = StByteWrReadBack; + end else begin + // No response received for initial write. We already can send the + // request for the readback in the next cycle but we need to wait + // for the response for the initial write before doing the readback + // check. + state_d = StByteWrReadBackDWait; + end + end + end + + StByteWrReadBack: begin + // Wait until the memory module has completed the partial write. + // Perform readback and check response in StPassThru. + if (EnableReadback == 0) begin : gen_inv_state_StByteWrReadBack + // If readback is disabled, we shouldn't be in this state. + alert_o = 1'b1; + end + + stall_host = 1'b1; + + rdback_phase_wrreadback = 1'b1; + + state_d = StPassThru; + end + + StByteWrReadBackDWait: begin + if (EnableReadback == 0) begin : gen_inv_state_StByteWrReadBackDWait + // If readback is disabled, we shouldn't be in this state. + alert_o = 1'b1; + end + + stall_host = 1'b1; + + // Wait for one cycle with sending readback request to SRAM. + wait_phase = 1'b1; + + if (d_ack) begin + // Got the TL-UL write response. Wait for one cycle until the holding + // register is flushed and then perform the readback. + state_d = StByteWrReadBack; + end + end + + StRdReadBack: begin + if (EnableReadback == 0) begin : gen_inv_state_StRdReadBack + // If readback is disabled, we shouldn't be in this state. + alert_o = 1'b1; + end + + // Sends out a read to a readback check on a read. The host is stalled whilst + // this is happening. + stall_host = 1'b1; + + // Need to ensure there's no other transactions in flight before we do the readback (the + // read we're doing the readback for should be the only one active). + if (pending_txn_cnt == PendingTxnCntW'(1)) begin + rdback_phase = 1'b1; + + if (d_ack) begin + state_d = StPassThru; + // Data for the readback check comes from the first read. + rdback_check_d = mubi4_test_true_loose(rdback_en_q) ? MuBi4True : MuBi4False; + rdback_data_exp_d = tl_o.d_data; + rdback_data_exp_intg_d = tl_o.d_user.data_intg; + end else begin + // No response yet to the initial read, so go wait for it. + state_d = StRdReadBackDWait; + end + end + end + + StRdReadBackDWait : begin + if (EnableReadback == 0) begin : gen_inv_state_StRdReadBackDWait + // If readback is disabled, we shouldn't be in this state. + alert_o = 1'b1; + end + + stall_host = 1'b1; + + if (d_ack) begin + // Response received for first read. Now need to await data for the readback check + // which is done in the `StPassThru` state. + state_d = StPassThru; + // Data for the readback check comes from the first read. + rdback_check_d = mubi4_test_true_loose(rdback_en_q) ? MuBi4True : MuBi4False; + rdback_data_exp_d = tl_o.d_data; + rdback_data_exp_intg_d = tl_o.d_user.data_intg; + end + end + + default: begin + alert_o = 1'b1; + end + endcase // unique case (state_q) + + end + + tl_txn_data_t txn_data; + logic fifo_rdy; + logic txn_data_wr; + localparam int TxnDataWidth = $bits(tl_txn_data_t); + + assign txn_data = '{ + a_param: tl_i.a_param, + a_size: tl_i.a_size, + a_source: tl_i.a_source, + a_address: tl_i.a_address, + a_mask: tl_i.a_mask, + a_data: tl_i.a_data, + a_user: tl_i.a_user + }; + + + assign txn_data_wr = hold_tx_data | byte_req_ack; + + caliptra_prim_fifo_sync #( + .Width(TxnDataWidth), + .Pass(1'b0), + .Depth(1), + .OutputZeroIfEmpty(1'b0) + ) u_sync_fifo ( + .clk_i, + .rst_ni, + .clr_i(1'b0), + .wvalid_i(txn_data_wr), + .wready_o(fifo_rdy), + .wdata_i(txn_data), + .rvalid_o(), + .rready_i(sram_a_ack), + .rdata_o(held_data), + .full_o(), + .depth_o(), + .err_o() + ); + + // captured read data + logic [tlul_pkg::TL_DW-1:0] rsp_data; + always_ff @(posedge clk_i) begin + if (sram_d_ack && rd_wait) begin + rsp_data <= tl_sram_i.d_data; + end + end + + // while we could simply not assert a_ready to ensure the host keeps + // the request lines stable, there is no guarantee the hosts (if there are multiple) + // do not re-arbitrate on every cycle if its transactions are not accepted. + // As a result, it is better to capture the transaction attributes. + logic [tlul_pkg::TL_DW-1:0] combined_data, unused_data; + always_comb begin + for (int i = 0; i < tlul_pkg::TL_DBW; i++) begin + combined_data[i*8 +: 8] = held_data.a_mask[i] ? + held_data.a_data[i*8 +: 8] : + rsp_data[i*8 +: 8]; + end + end + + // Compute updated integrity bits for the data. + // Note that the CMD integrity does not have to be correct, since it is not consumed nor + // checked further downstream. + logic [tlul_pkg::DataIntgWidth-1:0] data_intg; + + tlul_data_integ_enc u_tlul_data_integ_enc ( + .data_i(combined_data), + .data_intg_o({data_intg, unused_data}) + ); + + tl_a_user_t combined_user; + always_comb begin + combined_user = held_data.a_user; + combined_user.data_intg = data_intg; + end + + localparam int unsigned AccessSize = $clog2(tlul_pkg::TL_DBW); + always_comb begin + // Pass-through by default + tl_sram_o = tl_i; + // If we're waiting for an internal read for RMW, or a readback read, we force this to 1. + tl_sram_o.d_ready = tl_i.d_ready | rd_wait | rdback_wait; + + // We take over the TL-UL bus if there is a pending read or write for the RMW transaction. + // TL-UL signals are selectively muxed below to reduce complexity and remove long timing + // paths through the error_i signal. In particular, we avoid creating paths from error_i + // to the address and data output since these may feed into RAM scrambling logic further + // downstream. + + // Write transactions for RMW or reads when in readback mode. + if (wr_phase | rdback_phase | rdback_phase_wrreadback) begin + tl_sram_o.a_valid = 1'b1; + // During a read-modify write, always access the entire word. + tl_sram_o.a_opcode = wr_phase ? PutFullData : Get; + // In either read-modify write or SRAM readback mode, use the mask, size and address + // of the original request. + tl_sram_o.a_size = + (wr_phase | rdback_phase_wrreadback) ? TL_SZW'(AccessSize) : held_data.a_size; + tl_sram_o.a_mask = + (wr_phase | rdback_phase_wrreadback) ? '{default: '1} : held_data.a_mask; + // override with held / combined data. + // need to use word aligned addresses here. + tl_sram_o.a_address = held_data.a_address; + tl_sram_o.a_address[AccessSize-1:0] = + (wr_phase | rdback_phase_wrreadback) ? '0 : held_data.a_address[AccessSize-1:0]; + tl_sram_o.a_source = held_data.a_source; + tl_sram_o.a_param = held_data.a_param; + tl_sram_o.a_data = wr_phase ? combined_data : '0; + tl_sram_o.a_user = wr_phase ? combined_user : '0; + // Read transactions for RMW. + end else if (rd_phase) begin + // need to use word aligned addresses here. + tl_sram_o.a_address[AccessSize-1:0] = '0; + // Only override the control signals if there is no error at the input. + if (!error_i || stall_host) begin + // Since we are performing a read-modify-write operation, + // we always access the entire word. + tl_sram_o.a_size = tlul_pkg::TL_SZW'(AccessSize); + tl_sram_o.a_mask = '{default: '1}; + // use incoming valid as long as we are not stalling the host + tl_sram_o.a_valid = tl_i.a_valid & ~stall_host; + tl_sram_o.a_opcode = Get; + end + end else if (wait_phase) begin + // Delay the readback request to avoid that we are reading the holding + // register. + tl_sram_o.a_valid = 1'b0; + end + end + + // This assert is necessary for the casting of AccessSize. + `CALIPTRA_ASSERT(TlulSramByteTlSize_A, tlul_pkg::TL_SZW >= $clog2(AccessSize + 1)) + + assign error_o = error_i & ~stall_host; + + logic size_fifo_rdy; + logic [tlul_pkg::TL_SZW-1:0] a_size; + caliptra_prim_fifo_sync #( + .Width(tlul_pkg::TL_SZW), + .Pass(1'b0), + .Depth(Outstanding), + .OutputZeroIfEmpty(1'b1) + ) u_sync_fifo_a_size ( + .clk_i, + .rst_ni, + .clr_i(1'b0), + .wvalid_i(a_ack), + .wready_o(size_fifo_rdy), + .wdata_i(tl_i.a_size), + .rvalid_o(), + .rready_i(d_ack), + .rdata_o(a_size), + .full_o(), + .depth_o(pending_txn_cnt), + .err_o() + ); + + always_comb begin + tl_o = tl_sram_i; + + // pass a_ready through directly if we are not stalling + tl_o.a_ready = tl_sram_i.a_ready & ~stall_host & fifo_rdy & size_fifo_rdy; + + // when internal logic has taken over, do not show response to host during + // read phase. During write phase, allow the host to see the completion. + tl_o.d_valid = tl_sram_i.d_valid & ~rd_wait & ~rdback_wait; + + // the size returned by tl_sram_i does not always correspond to the actual + // transaction size in cases where a read modify write operation is + // performed. Hence, we always return the registered size here. + tl_o.d_size = a_size; + end // always_comb + + // unused info from tl_sram_i + // see explanation in above block + logic unused_tl; + assign unused_tl = |tl_sram_i.d_size; + + // when byte access detected, go to wait read + `CALIPTRA_ASSERT(ByteAccessStateChange_A, a_ack & wr_txn & ~&tl_i.a_mask & ~error_i |=> + state_q inside {StWaitRd}) + // when in wait for read, a successful response should move to write phase + `CALIPTRA_ASSERT(ReadCompleteStateChange_A, + (state_q == StWaitRd) && (pending_txn_cnt == 1) && sram_d_ack |=> state_q == StWriteCmd) + // The readback logic assumes that any request on the readback channel will be instantly granted + // (i.e. after the initial SRAM read or write request from the external requester has been + // granted). This helps simplify the logic. It is guaranteed when connected to an SRAM as it + // produces no back pressure. When connected to a scrambled SRAM the key going invalid will + // cause a_ready to drop. The `compound_txn_in_progress_o` output is provided for this scenario. + // When asserted SRAM should not drop `a_ready` even if there is an invalid scrambling key. + `CALIPTRA_ASSERT(ReadbackAccessAlwaysGranted_A, (rdback_phase | rdback_phase_wrreadback) && !error_i + |-> tl_sram_i.a_ready) + + // The readback logic assumes the result of a read transaction issues for the readback will get + // an immediate response. This can be guaranteed when connected to a SRAM, see above comment. + `CALIPTRA_ASSERT(ReadbackDataImmediatelyAvailable_A, (state_q == StPassThru) && + mubi4_test_true_loose(rdback_en_q) && mubi4_test_true_loose(rdback_check_q) && + !error_i|-> tl_sram_i.d_valid) + + assign compound_txn_in_progress_o = wr_phase | rdback_phase | rdback_phase_wrreadback; + end else begin : gen_no_integ_handling + // In this case we pass everything just through. + assign tl_sram_o = tl_i; + assign tl_o = tl_sram_i; + assign error_o = error_i; + assign alert_o = 1'b0; + assign compound_txn_in_progress_o = 1'b0; + + // Signal only used in readback mode. + mubi4_t unused_readback_en; + assign unused_readback_en = readback_en_i; + + end + + // Signals only used for SVA. + logic unused_write_pending, unused_wr_collision; + assign unused_write_pending = write_pending_i; + assign unused_wr_collision = wr_collision_i; + + // EnableReadback requires that EnableIntg is on. + // EnableIntg can be used without EnableReadback. + `CALIPTRA_ASSERT_INIT(SramReadbackAndIntg, + (EnableReadback && EnableIntg) || (!EnableReadback && (EnableIntg || !EnableIntg))) +endmodule // tlul_adapter_sram diff --git a/src/tlul/socket_1n.core b/src/tlul/socket_1n.core new file mode 100644 index 0000000..a4c2e38 --- /dev/null +++ b/src/tlul/socket_1n.core @@ -0,0 +1,64 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:tlul:socket_1n:0.1" +description: "TL-UL socket 1:n" + +filesets: + files_rtl: + depend: + - lowrisc:prim:assert + - lowrisc:tlul:headers + - lowrisc:tlul:common + files: + - rtl/tlul_err_resp.sv + - rtl/tlul_socket_1n.sv + file_type: systemVerilogSource + + files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common + files: + - lint/tlul_socket_1n.vlt + file_type: vlt + + files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common + files: + - lint/tlul_socket_1n.waiver + file_type: waiver + + files_veriblelint_waiver: + depend: + # common waivers + - lowrisc:lint:common + +parameters: + SYNTHESIS: + datatype: bool + paramtype: vlogdefine + + +targets: + default: &default_target + filesets: + - tool_verilator ? (files_verilator_waiver) + - tool_ascentlint ? (files_ascentlint_waiver) + - tool_veriblelint ? (files_veriblelint_waiver) + - files_rtl + toplevel: tlul_socket_1n + + lint: + <<: *default_target + default_tool: verilator + parameters: + - SYNTHESIS=true + tools: + verilator: + mode: lint-only + verilator_options: + - "-Wall" diff --git a/src/tlul/socket_m1.core b/src/tlul/socket_m1.core new file mode 100644 index 0000000..e8e3af5 --- /dev/null +++ b/src/tlul/socket_m1.core @@ -0,0 +1,64 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:tlul:socket_m1:0.1" +description: "TL-UL socket m:1" + +filesets: + files_rtl: + depend: + - lowrisc:prim:assert + - lowrisc:prim:arbiter + - lowrisc:tlul:common + - lowrisc:tlul:headers + files: + - rtl/tlul_socket_m1.sv + file_type: systemVerilogSource + + files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common + files: + - lint/tlul_socket_m1.vlt + file_type: vlt + + files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common + files: + - lint/tlul_socket_m1.waiver + file_type: waiver + + files_veriblelint_waiver: + depend: + # common waivers + - lowrisc:lint:common + +parameters: + SYNTHESIS: + datatype: bool + paramtype: vlogdefine + + +targets: + default: &default_target + filesets: + - tool_verilator ? (files_verilator_waiver) + - tool_ascentlint ? (files_ascentlint_waiver) + - tool_veriblelint ? (files_veriblelint_waiver) + - files_rtl + toplevel: tlul_socket_m1 + + lint: + <<: *default_target + default_tool: verilator + parameters: + - SYNTHESIS=true + tools: + verilator: + mode: lint-only + verilator_options: + - "-Wall" diff --git a/src/tlul/sram2tlul.core b/src/tlul/sram2tlul.core new file mode 100644 index 0000000..f448990 --- /dev/null +++ b/src/tlul/sram2tlul.core @@ -0,0 +1,62 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:tlul:sram2tlul:0.1" +description: "SRAM to TL-UL adapter (host)" + +filesets: + files_rtl: + depend: + - lowrisc:prim:assert + - lowrisc:tlul:common + files: + - rtl/sram2tlul.sv + file_type: systemVerilogSource + + files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common + files: + - lint/tlul_sram2tlul.vlt + file_type: vlt + + files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common + files: + - lint/tlul_sram2tlul.waiver + file_type: waiver + + files_veriblelint_waiver: + depend: + # common waivers + - lowrisc:lint:common + +parameters: + SYNTHESIS: + datatype: bool + paramtype: vlogdefine + + +targets: + default: &default_target + filesets: + - tool_verilator ? (files_verilator_waiver) + - tool_ascentlint ? (files_ascentlint_waiver) + - tool_veriblelint ? (files_veriblelint_waiver) + - files_rtl + toplevel: sram2tlul + + lint: + <<: *default_target + default_tool: verilator + parameters: + - SYNTHESIS=true + tools: + verilator: + mode: lint-only + verilator_options: + - "-Wall" diff --git a/src/tlul/tlul.core b/src/tlul/tlul.core new file mode 100644 index 0000000..974060a --- /dev/null +++ b/src/tlul/tlul.core @@ -0,0 +1,21 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:ip:tlul:0.1" +description: "Transition core for TL-UL (deprecated)" + +filesets: + files_rtl: + depend: + - lowrisc:tlul:socket_1n + - lowrisc:tlul:socket_m1 + - lowrisc:tlul:adapter_sram + - lowrisc:tlul:adapter_reg + - lowrisc:tlul:sram2tlul + - lowrisc:tlul:caliptra_ss_lc_gate + +targets: + default: + filesets: + - files_rtl diff --git a/src/tlul/tlul_lc_gate.core b/src/tlul/tlul_lc_gate.core new file mode 100644 index 0000000..4820884 --- /dev/null +++ b/src/tlul/tlul_lc_gate.core @@ -0,0 +1,63 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:tlul:caliptra_ss_lc_gate:0.1" +description: "TL-UL Lifecycle Gate" + +filesets: + files_rtl: + depend: + - lowrisc:prim:assert + - lowrisc:tlul:common + - lowrisc:ip:caliptra_ss_lc_ctrl_pkg + - lowrisc:prim:blanker + - lowrisc:prim:sparse_fsm + files: + - rtl/tlul_caliptra_ss_lc_gate.sv + file_type: systemVerilogSource + + files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common + files: + - lint/tlul_caliptra_ss_lc_gate.vlt + file_type: vlt + + files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common + file_type: waiver + + files_veriblelint_waiver: + depend: + # common waivers + - lowrisc:lint:common + +parameters: + SYNTHESIS: + datatype: bool + paramtype: vlogdefine + + +targets: + default: &default_target + filesets: + - tool_verilator ? (files_verilator_waiver) + - tool_ascentlint ? (files_ascentlint_waiver) + - tool_veriblelint ? (files_veriblelint_waiver) + - files_rtl + toplevel: tlul_caliptra_ss_lc_gate + + lint: + <<: *default_target + default_tool: verilator + parameters: + - SYNTHESIS=true + tools: + verilator: + mode: lint-only + verilator_options: + - "-Wall" diff --git a/src/tlul/trans_intg.core b/src/tlul/trans_intg.core new file mode 100644 index 0000000..50b9dcd --- /dev/null +++ b/src/tlul/trans_intg.core @@ -0,0 +1,64 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:tlul:trans_intg:0.1" +description: "Tlul transmission integrity" + +filesets: + files_rtl: + depend: + - lowrisc:prim:assert + - lowrisc:prim:secded + - lowrisc:tlul:headers + files: + - rtl/tlul_data_integ_enc.sv + - rtl/tlul_data_integ_dec.sv + - rtl/tlul_cmd_intg_gen.sv + - rtl/tlul_cmd_intg_chk.sv + - rtl/tlul_rsp_intg_gen.sv + - rtl/tlul_rsp_intg_chk.sv + file_type: systemVerilogSource + + files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common + file_type: vlt + + files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common + file_type: waiver + + files_veriblelint_waiver: + depend: + # common waivers + - lowrisc:lint:common + +parameters: + SYNTHESIS: + datatype: bool + paramtype: vlogdefine + + +targets: + default: &default_target + filesets: + - tool_verilator ? (files_verilator_waiver) + - tool_ascentlint ? (files_ascentlint_waiver) + - tool_veriblelint ? (files_veriblelint_waiver) + - files_rtl + toplevel: tlul_payload_chk + + lint: + <<: *default_target + default_tool: verilator + parameters: + - SYNTHESIS=true + tools: + verilator: + mode: lint-only + verilator_options: + - "-Wall" diff --git a/third_party/caliptra-rtl b/third_party/caliptra-rtl index d371fc4..033f2b0 160000 --- a/third_party/caliptra-rtl +++ b/third_party/caliptra-rtl @@ -1 +1 @@ -Subproject commit d371fc4ba2e42433c0620ee13bac62be3fdb9a7a +Subproject commit 033f2b0dee14d78fd5ebccd6e3618092a1f38176